Boot log: asus-C436FA-Flip-hatch
- Kernel Warnings: 0
- Kernel Errors: 0
- Boot result: FAIL
- Warnings: 0
- Errors: 2
1 12:46:34.422948 lava-dispatcher, installed at version: 2023.10
2 12:46:34.423157 start: 0 validate
3 12:46:34.423283 Start time: 2024-01-03 12:46:34.423275+00:00 (UTC)
4 12:46:34.423394 Using caching service: 'http://localhost/cache/?uri=%s'
5 12:46:34.423528 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-ltp%2F20230623.0%2Famd64%2Finitrd.cpio.gz exists
6 12:46:34.694891 Using caching service: 'http://localhost/cache/?uri=%s'
7 12:46:34.695621 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-4.4.y-st-rt%2Fv4.4-st20-2890-g35edf5997b50a%2Fx86_64%2Fx86_64_defconfig%2Bx86-board%2Fgcc-10%2Fkernel%2FbzImage exists
8 12:46:34.968014 Using caching service: 'http://localhost/cache/?uri=%s'
9 12:46:34.968820 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-ltp%2F20230623.0%2Famd64%2Ffull.rootfs.tar.xz exists
10 12:46:35.239977 Using caching service: 'http://localhost/cache/?uri=%s'
11 12:46:35.240806 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-4.4.y-st-rt%2Fv4.4-st20-2890-g35edf5997b50a%2Fx86_64%2Fx86_64_defconfig%2Bx86-board%2Fgcc-10%2Fmodules.tar.xz exists
12 12:46:35.517959 validate duration: 1.09
14 12:46:35.519329 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 12:46:35.519858 start: 1.1 download-retry (timeout 00:10:00) [common]
16 12:46:35.520382 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 12:46:35.521023 Not decompressing ramdisk as can be used compressed.
18 12:46:35.521488 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-ltp/20230623.0/amd64/initrd.cpio.gz
19 12:46:35.521846 saving as /var/lib/lava/dispatcher/tmp/12437333/tftp-deploy-ms_81r7r/ramdisk/initrd.cpio.gz
20 12:46:35.522204 total size: 5671549 (5 MB)
21 12:46:35.527520 progress 0 % (0 MB)
22 12:46:35.537050 progress 5 % (0 MB)
23 12:46:35.544948 progress 10 % (0 MB)
24 12:46:35.549686 progress 15 % (0 MB)
25 12:46:35.553878 progress 20 % (1 MB)
26 12:46:35.557568 progress 25 % (1 MB)
27 12:46:35.560305 progress 30 % (1 MB)
28 12:46:35.563176 progress 35 % (1 MB)
29 12:46:35.565732 progress 40 % (2 MB)
30 12:46:35.567949 progress 45 % (2 MB)
31 12:46:35.570189 progress 50 % (2 MB)
32 12:46:35.572416 progress 55 % (3 MB)
33 12:46:35.574181 progress 60 % (3 MB)
34 12:46:35.576165 progress 65 % (3 MB)
35 12:46:35.578081 progress 70 % (3 MB)
36 12:46:35.579672 progress 75 % (4 MB)
37 12:46:35.581457 progress 80 % (4 MB)
38 12:46:35.583177 progress 85 % (4 MB)
39 12:46:35.584647 progress 90 % (4 MB)
40 12:46:35.586266 progress 95 % (5 MB)
41 12:46:35.587872 progress 100 % (5 MB)
42 12:46:35.587977 5 MB downloaded in 0.07 s (82.20 MB/s)
43 12:46:35.588193 end: 1.1.1 http-download (duration 00:00:00) [common]
45 12:46:35.588421 end: 1.1 download-retry (duration 00:00:00) [common]
46 12:46:35.588507 start: 1.2 download-retry (timeout 00:10:00) [common]
47 12:46:35.588587 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 12:46:35.588715 downloading http://storage.kernelci.org/cip/linux-4.4.y-st-rt/v4.4-st20-2890-g35edf5997b50a/x86_64/x86_64_defconfig+x86-board/gcc-10/kernel/bzImage
49 12:46:35.588788 saving as /var/lib/lava/dispatcher/tmp/12437333/tftp-deploy-ms_81r7r/kernel/bzImage
50 12:46:35.588849 total size: 8585104 (8 MB)
51 12:46:35.588907 No compression specified
52 12:46:35.590046 progress 0 % (0 MB)
53 12:46:35.592405 progress 5 % (0 MB)
54 12:46:35.594659 progress 10 % (0 MB)
55 12:46:35.597096 progress 15 % (1 MB)
56 12:46:35.599390 progress 20 % (1 MB)
57 12:46:35.601768 progress 25 % (2 MB)
58 12:46:35.604100 progress 30 % (2 MB)
59 12:46:35.606354 progress 35 % (2 MB)
60 12:46:35.608626 progress 40 % (3 MB)
61 12:46:35.610838 progress 45 % (3 MB)
62 12:46:35.613252 progress 50 % (4 MB)
63 12:46:35.615702 progress 55 % (4 MB)
64 12:46:35.617925 progress 60 % (4 MB)
65 12:46:35.620290 progress 65 % (5 MB)
66 12:46:35.622470 progress 70 % (5 MB)
67 12:46:35.624740 progress 75 % (6 MB)
68 12:46:35.626964 progress 80 % (6 MB)
69 12:46:35.629201 progress 85 % (6 MB)
70 12:46:35.631376 progress 90 % (7 MB)
71 12:46:35.633630 progress 95 % (7 MB)
72 12:46:35.635863 progress 100 % (8 MB)
73 12:46:35.636148 8 MB downloaded in 0.05 s (173.11 MB/s)
74 12:46:35.636292 end: 1.2.1 http-download (duration 00:00:00) [common]
76 12:46:35.636518 end: 1.2 download-retry (duration 00:00:00) [common]
77 12:46:35.636605 start: 1.3 download-retry (timeout 00:10:00) [common]
78 12:46:35.636687 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 12:46:35.636828 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-ltp/20230623.0/amd64/full.rootfs.tar.xz
80 12:46:35.636894 saving as /var/lib/lava/dispatcher/tmp/12437333/tftp-deploy-ms_81r7r/nfsrootfs/full.rootfs.tar
81 12:46:35.636953 total size: 126031368 (120 MB)
82 12:46:35.637013 Using unxz to decompress xz
83 12:46:35.641282 progress 0 % (0 MB)
84 12:46:36.126429 progress 5 % (6 MB)
85 12:46:36.611202 progress 10 % (12 MB)
86 12:46:37.104464 progress 15 % (18 MB)
87 12:46:37.608064 progress 20 % (24 MB)
88 12:46:37.949967 progress 25 % (30 MB)
89 12:46:38.286183 progress 30 % (36 MB)
90 12:46:38.549391 progress 35 % (42 MB)
91 12:46:38.728392 progress 40 % (48 MB)
92 12:46:39.093352 progress 45 % (54 MB)
93 12:46:39.463599 progress 50 % (60 MB)
94 12:46:39.800790 progress 55 % (66 MB)
95 12:46:40.157886 progress 60 % (72 MB)
96 12:46:40.494026 progress 65 % (78 MB)
97 12:46:40.876384 progress 70 % (84 MB)
98 12:46:41.289292 progress 75 % (90 MB)
99 12:46:41.700283 progress 80 % (96 MB)
100 12:46:41.797247 progress 85 % (102 MB)
101 12:46:41.950208 progress 90 % (108 MB)
102 12:46:42.281241 progress 95 % (114 MB)
103 12:46:42.650037 progress 100 % (120 MB)
104 12:46:42.654820 120 MB downloaded in 7.02 s (17.13 MB/s)
105 12:46:42.655072 end: 1.3.1 http-download (duration 00:00:07) [common]
107 12:46:42.655327 end: 1.3 download-retry (duration 00:00:07) [common]
108 12:46:42.655439 start: 1.4 download-retry (timeout 00:09:53) [common]
109 12:46:42.655537 start: 1.4.1 http-download (timeout 00:09:53) [common]
110 12:46:42.655689 downloading http://storage.kernelci.org/cip/linux-4.4.y-st-rt/v4.4-st20-2890-g35edf5997b50a/x86_64/x86_64_defconfig+x86-board/gcc-10/modules.tar.xz
111 12:46:42.655760 saving as /var/lib/lava/dispatcher/tmp/12437333/tftp-deploy-ms_81r7r/modules/modules.tar
112 12:46:42.655820 total size: 253660 (0 MB)
113 12:46:42.655883 Using unxz to decompress xz
114 12:46:42.660361 progress 12 % (0 MB)
115 12:46:42.660750 progress 25 % (0 MB)
116 12:46:42.661007 progress 38 % (0 MB)
117 12:46:42.662621 progress 51 % (0 MB)
118 12:46:42.664577 progress 64 % (0 MB)
119 12:46:42.666419 progress 77 % (0 MB)
120 12:46:42.668268 progress 90 % (0 MB)
121 12:46:42.670158 progress 100 % (0 MB)
122 12:46:42.675590 0 MB downloaded in 0.02 s (12.24 MB/s)
123 12:46:42.675820 end: 1.4.1 http-download (duration 00:00:00) [common]
125 12:46:42.676107 end: 1.4 download-retry (duration 00:00:00) [common]
126 12:46:42.676221 start: 1.5 prepare-tftp-overlay (timeout 00:09:53) [common]
127 12:46:42.676317 start: 1.5.1 extract-nfsrootfs (timeout 00:09:53) [common]
128 12:46:45.631543 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/12437333/extract-nfsrootfs-4kjdl8g9
129 12:46:45.631746 end: 1.5.1 extract-nfsrootfs (duration 00:00:03) [common]
130 12:46:45.631849 start: 1.5.2 lava-overlay (timeout 00:09:50) [common]
131 12:46:45.632013 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12437333/lava-overlay-ll72jzlq
132 12:46:45.632249 makedir: /var/lib/lava/dispatcher/tmp/12437333/lava-overlay-ll72jzlq/lava-12437333/bin
133 12:46:45.632352 makedir: /var/lib/lava/dispatcher/tmp/12437333/lava-overlay-ll72jzlq/lava-12437333/tests
134 12:46:45.632455 makedir: /var/lib/lava/dispatcher/tmp/12437333/lava-overlay-ll72jzlq/lava-12437333/results
135 12:46:45.632557 Creating /var/lib/lava/dispatcher/tmp/12437333/lava-overlay-ll72jzlq/lava-12437333/bin/lava-add-keys
136 12:46:45.632702 Creating /var/lib/lava/dispatcher/tmp/12437333/lava-overlay-ll72jzlq/lava-12437333/bin/lava-add-sources
137 12:46:45.632833 Creating /var/lib/lava/dispatcher/tmp/12437333/lava-overlay-ll72jzlq/lava-12437333/bin/lava-background-process-start
138 12:46:45.632963 Creating /var/lib/lava/dispatcher/tmp/12437333/lava-overlay-ll72jzlq/lava-12437333/bin/lava-background-process-stop
139 12:46:45.633092 Creating /var/lib/lava/dispatcher/tmp/12437333/lava-overlay-ll72jzlq/lava-12437333/bin/lava-common-functions
140 12:46:45.633219 Creating /var/lib/lava/dispatcher/tmp/12437333/lava-overlay-ll72jzlq/lava-12437333/bin/lava-echo-ipv4
141 12:46:45.633348 Creating /var/lib/lava/dispatcher/tmp/12437333/lava-overlay-ll72jzlq/lava-12437333/bin/lava-install-packages
142 12:46:45.633479 Creating /var/lib/lava/dispatcher/tmp/12437333/lava-overlay-ll72jzlq/lava-12437333/bin/lava-installed-packages
143 12:46:45.633605 Creating /var/lib/lava/dispatcher/tmp/12437333/lava-overlay-ll72jzlq/lava-12437333/bin/lava-os-build
144 12:46:45.633733 Creating /var/lib/lava/dispatcher/tmp/12437333/lava-overlay-ll72jzlq/lava-12437333/bin/lava-probe-channel
145 12:46:45.633860 Creating /var/lib/lava/dispatcher/tmp/12437333/lava-overlay-ll72jzlq/lava-12437333/bin/lava-probe-ip
146 12:46:45.633986 Creating /var/lib/lava/dispatcher/tmp/12437333/lava-overlay-ll72jzlq/lava-12437333/bin/lava-target-ip
147 12:46:45.634120 Creating /var/lib/lava/dispatcher/tmp/12437333/lava-overlay-ll72jzlq/lava-12437333/bin/lava-target-mac
148 12:46:45.634244 Creating /var/lib/lava/dispatcher/tmp/12437333/lava-overlay-ll72jzlq/lava-12437333/bin/lava-target-storage
149 12:46:45.634371 Creating /var/lib/lava/dispatcher/tmp/12437333/lava-overlay-ll72jzlq/lava-12437333/bin/lava-test-case
150 12:46:45.634498 Creating /var/lib/lava/dispatcher/tmp/12437333/lava-overlay-ll72jzlq/lava-12437333/bin/lava-test-event
151 12:46:45.634623 Creating /var/lib/lava/dispatcher/tmp/12437333/lava-overlay-ll72jzlq/lava-12437333/bin/lava-test-feedback
152 12:46:45.634748 Creating /var/lib/lava/dispatcher/tmp/12437333/lava-overlay-ll72jzlq/lava-12437333/bin/lava-test-raise
153 12:46:45.634872 Creating /var/lib/lava/dispatcher/tmp/12437333/lava-overlay-ll72jzlq/lava-12437333/bin/lava-test-reference
154 12:46:45.634997 Creating /var/lib/lava/dispatcher/tmp/12437333/lava-overlay-ll72jzlq/lava-12437333/bin/lava-test-runner
155 12:46:45.635121 Creating /var/lib/lava/dispatcher/tmp/12437333/lava-overlay-ll72jzlq/lava-12437333/bin/lava-test-set
156 12:46:45.635244 Creating /var/lib/lava/dispatcher/tmp/12437333/lava-overlay-ll72jzlq/lava-12437333/bin/lava-test-shell
157 12:46:45.635370 Updating /var/lib/lava/dispatcher/tmp/12437333/lava-overlay-ll72jzlq/lava-12437333/bin/lava-install-packages (oe)
158 12:46:45.635524 Updating /var/lib/lava/dispatcher/tmp/12437333/lava-overlay-ll72jzlq/lava-12437333/bin/lava-installed-packages (oe)
159 12:46:45.635647 Creating /var/lib/lava/dispatcher/tmp/12437333/lava-overlay-ll72jzlq/lava-12437333/environment
160 12:46:45.635744 LAVA metadata
161 12:46:45.635815 - LAVA_JOB_ID=12437333
162 12:46:45.635877 - LAVA_DISPATCHER_IP=192.168.201.1
163 12:46:45.635975 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:50) [common]
164 12:46:45.636041 skipped lava-vland-overlay
165 12:46:45.636119 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
166 12:46:45.636197 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:50) [common]
167 12:46:45.636256 skipped lava-multinode-overlay
168 12:46:45.636327 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
169 12:46:45.636404 start: 1.5.2.3 test-definition (timeout 00:09:50) [common]
170 12:46:45.636475 Loading test definitions
171 12:46:45.636562 start: 1.5.2.3.1 git-repo-action (timeout 00:09:50) [common]
172 12:46:45.636633 Using /lava-12437333 at stage 0
173 12:46:45.636731 Fetching tests from https://github.com/kernelci/test-definitions
174 12:46:45.636819 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions /var/lib/lava/dispatcher/tmp/12437333/lava-overlay-ll72jzlq/lava-12437333/0/tests/0_ltp-timers'
175 12:46:50.713548 Running '/usr/bin/git checkout kernelci.org
176 12:46:50.859977 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/12437333/lava-overlay-ll72jzlq/lava-12437333/0/tests/0_ltp-timers/automated/linux/ltp-open-posix/ltp-open-posix.yaml
177 12:46:50.860736 uuid=12437333_1.5.2.3.1 testdef=None
178 12:46:50.860896 end: 1.5.2.3.1 git-repo-action (duration 00:00:05) [common]
180 12:46:50.861139 start: 1.5.2.3.2 test-overlay (timeout 00:09:45) [common]
181 12:46:50.861809 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
183 12:46:50.862040 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:45) [common]
184 12:46:50.862915 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
186 12:46:50.863152 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:45) [common]
187 12:46:50.863976 runner path: /var/lib/lava/dispatcher/tmp/12437333/lava-overlay-ll72jzlq/lava-12437333/0/tests/0_ltp-timers test_uuid 12437333_1.5.2.3.1
188 12:46:50.864071 GRP_TEST='TMR'
189 12:46:50.864174 SKIPFILE='skipfile-lkft.yaml'
190 12:46:50.864233 SKIP_INSTALL='true'
191 12:46:50.864290 TST_CMDFILES=''
192 12:46:50.864429 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
194 12:46:50.864634 Creating lava-test-runner.conf files
195 12:46:50.864697 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12437333/lava-overlay-ll72jzlq/lava-12437333/0 for stage 0
196 12:46:50.864790 - 0_ltp-timers
197 12:46:50.864889 end: 1.5.2.3 test-definition (duration 00:00:05) [common]
198 12:46:50.864976 start: 1.5.2.4 compress-overlay (timeout 00:09:45) [common]
199 12:46:58.255851 end: 1.5.2.4 compress-overlay (duration 00:00:07) [common]
200 12:46:58.256008 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:37) [common]
201 12:46:58.256156 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
202 12:46:58.256256 end: 1.5.2 lava-overlay (duration 00:00:13) [common]
203 12:46:58.256348 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:37) [common]
204 12:46:58.398357 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:00) [common]
205 12:46:58.398753 start: 1.5.4 extract-modules (timeout 00:09:37) [common]
206 12:46:58.398872 extracting modules file /var/lib/lava/dispatcher/tmp/12437333/tftp-deploy-ms_81r7r/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12437333/extract-nfsrootfs-4kjdl8g9
207 12:46:58.412510 extracting modules file /var/lib/lava/dispatcher/tmp/12437333/tftp-deploy-ms_81r7r/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12437333/extract-overlay-ramdisk-mw_dwfu8/ramdisk
208 12:46:58.426058 end: 1.5.4 extract-modules (duration 00:00:00) [common]
209 12:46:58.426173 start: 1.5.5 apply-overlay-tftp (timeout 00:09:37) [common]
210 12:46:58.426262 [common] Applying overlay to NFS
211 12:46:58.426336 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12437333/compress-overlay-nrquq8dw/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12437333/extract-nfsrootfs-4kjdl8g9
212 12:46:59.346865 end: 1.5.5 apply-overlay-tftp (duration 00:00:01) [common]
213 12:46:59.347035 start: 1.5.6 configure-preseed-file (timeout 00:09:36) [common]
214 12:46:59.347132 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
215 12:46:59.347222 start: 1.5.7 compress-ramdisk (timeout 00:09:36) [common]
216 12:46:59.347300 Building ramdisk /var/lib/lava/dispatcher/tmp/12437333/extract-overlay-ramdisk-mw_dwfu8/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12437333/extract-overlay-ramdisk-mw_dwfu8/ramdisk
217 12:46:59.428732 >> 27216 blocks
218 12:46:59.993953 rename /var/lib/lava/dispatcher/tmp/12437333/extract-overlay-ramdisk-mw_dwfu8/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12437333/tftp-deploy-ms_81r7r/ramdisk/ramdisk.cpio.gz
219 12:46:59.994400 end: 1.5.7 compress-ramdisk (duration 00:00:01) [common]
220 12:46:59.994523 start: 1.5.8 prepare-kernel (timeout 00:09:36) [common]
221 12:46:59.994624 start: 1.5.8.1 prepare-fit (timeout 00:09:36) [common]
222 12:46:59.994718 No mkimage arch provided, not using FIT.
223 12:46:59.994805 end: 1.5.8.1 prepare-fit (duration 00:00:00) [common]
224 12:46:59.994888 end: 1.5.8 prepare-kernel (duration 00:00:00) [common]
225 12:46:59.994995 end: 1.5 prepare-tftp-overlay (duration 00:00:17) [common]
226 12:46:59.995088 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:36) [common]
227 12:46:59.995171 No LXC device requested
228 12:46:59.995250 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
229 12:46:59.995338 start: 1.7 deploy-device-env (timeout 00:09:36) [common]
230 12:46:59.995423 end: 1.7 deploy-device-env (duration 00:00:00) [common]
231 12:46:59.995494 Checking files for TFTP limit of 4294967296 bytes.
232 12:46:59.995900 end: 1 tftp-deploy (duration 00:00:24) [common]
233 12:46:59.996003 start: 2 depthcharge-action (timeout 00:05:00) [common]
234 12:46:59.996134 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
235 12:46:59.996266 substitutions:
236 12:46:59.996336 - {DTB}: None
237 12:46:59.996397 - {INITRD}: 12437333/tftp-deploy-ms_81r7r/ramdisk/ramdisk.cpio.gz
238 12:46:59.996455 - {KERNEL}: 12437333/tftp-deploy-ms_81r7r/kernel/bzImage
239 12:46:59.996511 - {LAVA_MAC}: None
240 12:46:59.996566 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/12437333/extract-nfsrootfs-4kjdl8g9
241 12:46:59.996668 - {NFS_SERVER_IP}: 192.168.201.1
242 12:46:59.996724 - {PRESEED_CONFIG}: None
243 12:46:59.996778 - {PRESEED_LOCAL}: None
244 12:46:59.996874 - {RAMDISK}: 12437333/tftp-deploy-ms_81r7r/ramdisk/ramdisk.cpio.gz
245 12:46:59.996928 - {ROOT_PART}: None
246 12:46:59.996981 - {ROOT}: None
247 12:46:59.997034 - {SERVER_IP}: 192.168.201.1
248 12:46:59.997086 - {TEE}: None
249 12:46:59.997138 Parsed boot commands:
250 12:46:59.997191 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
251 12:46:59.997366 Parsed boot commands: tftpboot 192.168.201.1 12437333/tftp-deploy-ms_81r7r/kernel/bzImage 12437333/tftp-deploy-ms_81r7r/kernel/cmdline 12437333/tftp-deploy-ms_81r7r/ramdisk/ramdisk.cpio.gz
252 12:46:59.997454 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
253 12:46:59.997538 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
254 12:46:59.997626 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
255 12:46:59.997711 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
256 12:46:59.997780 Not connected, no need to disconnect.
257 12:46:59.997853 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
258 12:46:59.997929 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
259 12:46:59.997995 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh asus-C436FA-Flip-hatch-cbg-0'
260 12:47:00.002133 Setting prompt string to ['lava-test: # ']
261 12:47:00.002500 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
262 12:47:00.002606 end: 2.2.1 reset-connection (duration 00:00:00) [common]
263 12:47:00.002733 start: 2.2.2 reset-device (timeout 00:05:00) [common]
264 12:47:00.002847 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
265 12:47:00.003068 Calling: 'pduclient' '--daemon=localhost' '--hostname=asus-C436FA-Flip-hatch-cbg-0' '--port=1' '--command=reboot'
266 12:47:05.143948 >> Command sent successfully.
267 12:47:05.155116 Returned 0 in 5 seconds
268 12:47:05.256503 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
270 12:47:05.258019 end: 2.2.2 reset-device (duration 00:00:05) [common]
271 12:47:05.258554 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
272 12:47:05.259041 Setting prompt string to 'Starting depthcharge on Helios...'
273 12:47:05.259412 Changing prompt to 'Starting depthcharge on Helios...'
274 12:47:05.259809 depthcharge-start: Wait for prompt Starting depthcharge on Helios... (timeout 00:05:00)
275 12:47:05.261238 [Enter `^Ec?' for help]
276 12:47:05.886355
277 12:47:05.887028
278 12:47:05.896998 coreboot-v1.9308_26_0.0.22-11197-gc9b4b7136b Thu Mar 18 05:35:38 UTC 2021 bootblock starting (log level: 8)...
279 12:47:05.900386 CPU: Intel(R) Core(TM) i5-10210U CPU @ 1.60GHz
280 12:47:05.906879 CPU: ID 806ec, Whiskeylake V0, ucode: 000000c9
281 12:47:05.910154 CPU: AES supported, TXT NOT supported, VT supported
282 12:47:05.917551 MCH: device id 9b61 (rev 0c) is CometLake-U (4+2)
283 12:47:05.920467 PCH: device id 0284 (rev 00) is Cometlake-U Premium
284 12:47:05.927112 IGD: device id 9b41 (rev 02) is CometLake ULT GT2
285 12:47:05.930409 VBOOT: Loading verstage.
286 12:47:05.934153 FMAP: Found "FLASH" version 1.1 at 0xc04000.
287 12:47:05.940350 FMAP: base = 0xff000000 size = 0x1000000 #areas = 31
288 12:47:05.943786 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
289 12:47:05.946792 CBFS @ c08000 size 3f8000
290 12:47:05.953455 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
291 12:47:05.957040 CBFS: Locating 'fallback/verstage'
292 12:47:05.960331 CBFS: Found @ offset 10fb80 size 1072c
293 12:47:05.964162
294 12:47:05.964726
295 12:47:05.973592 coreboot-v1.9308_26_0.0.22-11197-gc9b4b7136b Thu Mar 18 05:35:38 UTC 2021 verstage starting (log level: 8)...
296 12:47:05.988666 Probing TPM: . done!
297 12:47:05.991273 TPM ready after 0 ms
298 12:47:05.994736 Connected to device vid:did:rid of 1ae0:0028:00
299 12:47:06.004681 Firmware version: B2-C:0 RO_B:0.0.11/4d655eab RW_A:0.5.7/cr50_v1.9308_87_mp.514-29d5b602
300 12:47:06.008274 Initialized TPM device CR50 revision 0
301 12:47:06.055556 tlcl_send_startup: Startup return code is 0
302 12:47:06.056206 TPM: setup succeeded
303 12:47:06.068027 src/security/tpm/tss/tcg-2.0/tss.c:223 index 0x1007 return code 0
304 12:47:06.071800 Chrome EC: UHEPI supported
305 12:47:06.075139 Phase 1
306 12:47:06.078216 FMAP: area GBB found @ c05000 (12288 bytes)
307 12:47:06.085381 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x0 / 0x0
308 12:47:06.088265 Phase 2
309 12:47:06.088741 Phase 3
310 12:47:06.092231 FMAP: area GBB found @ c05000 (12288 bytes)
311 12:47:06.098238 VB2:vb2_report_dev_firmware() This is developer signed firmware
312 12:47:06.104841 FMAP: area VBLOCK_A found @ 400000 (65536 bytes)
313 12:47:06.108312 FMAP: area VBLOCK_A found @ 400000 (65536 bytes)
314 12:47:06.115126 VB2:vb2_verify_keyblock() Checking keyblock signature...
315 12:47:06.130727 FMAP: area VBLOCK_A found @ 400000 (65536 bytes)
316 12:47:06.133759 FMAP: area VBLOCK_A found @ 400000 (65536 bytes)
317 12:47:06.140352 VB2:vb2_verify_fw_preamble() Verifying preamble.
318 12:47:06.144605 Phase 4
319 12:47:06.147900 FMAP: area FW_MAIN_A found @ 410000 (3506112 bytes)
320 12:47:06.154626 VB2:vb2api_init_hash() HW crypto for hash_alg 2 not supported, using SW
321 12:47:06.334776 VB2:vb2_rsa_verify_digest() Digest check failed!
322 12:47:06.342070 VB2:vb2api_fail() Need recovery, reason: 0x1b / 0x7
323 12:47:06.342640 Saving nvdata
324 12:47:06.344248 Reboot requested (10020007)
325 12:47:06.347406 board_reset() called!
326 12:47:06.347915 full_reset() called!
327 12:47:10.853813
328 12:47:10.854378
329 12:47:10.863599 coreboot-v1.9308_26_0.0.22-11197-gc9b4b7136b Thu Mar 18 05:35:38 UTC 2021 bootblock starting (log level: 8)...
330 12:47:10.867434 CPU: Intel(R) Core(TM) i5-10210U CPU @ 1.60GHz
331 12:47:10.873726 CPU: ID 806ec, Whiskeylake V0, ucode: 000000c9
332 12:47:10.876751 CPU: AES supported, TXT NOT supported, VT supported
333 12:47:10.883438 MCH: device id 9b61 (rev 0c) is CometLake-U (4+2)
334 12:47:10.887039 PCH: device id 0284 (rev 00) is Cometlake-U Premium
335 12:47:10.893547 IGD: device id 9b41 (rev 02) is CometLake ULT GT2
336 12:47:10.896644 VBOOT: Loading verstage.
337 12:47:10.899876 FMAP: Found "FLASH" version 1.1 at 0xc04000.
338 12:47:10.906911 FMAP: base = 0xff000000 size = 0x1000000 #areas = 31
339 12:47:10.913385 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
340 12:47:10.913875 CBFS @ c08000 size 3f8000
341 12:47:10.920255 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
342 12:47:10.923403 CBFS: Locating 'fallback/verstage'
343 12:47:10.926508 CBFS: Found @ offset 10fb80 size 1072c
344 12:47:10.930772
345 12:47:10.931350
346 12:47:10.940895 coreboot-v1.9308_26_0.0.22-11197-gc9b4b7136b Thu Mar 18 05:35:38 UTC 2021 verstage starting (log level: 8)...
347 12:47:10.955225 Probing TPM: . done!
348 12:47:10.957989 TPM ready after 0 ms
349 12:47:10.961817 Connected to device vid:did:rid of 1ae0:0028:00
350 12:47:10.972428 Firmware version: B2-C:0 RO_B:0.0.11/4d655eab RW_A:0.5.7/cr50_v1.9308_87_mp.514-29d5b602
351 12:47:10.975161 Initialized TPM device CR50 revision 0
352 12:47:11.023440 tlcl_send_startup: Startup return code is 0
353 12:47:11.024023 TPM: setup succeeded
354 12:47:11.035349 src/security/tpm/tss/tcg-2.0/tss.c:223 index 0x1007 return code 0
355 12:47:11.039322 Chrome EC: UHEPI supported
356 12:47:11.042526 Phase 1
357 12:47:11.046535 FMAP: area GBB found @ c05000 (12288 bytes)
358 12:47:11.052614 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
359 12:47:11.058599 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x0
360 12:47:11.062374 Recovery requested (1009000e)
361 12:47:11.068630 Saving nvdata
362 12:47:11.074281 tlcl_extend: response is 0
363 12:47:11.083841 tlcl_extend: response is 0
364 12:47:11.090156 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
365 12:47:11.093357 CBFS @ c08000 size 3f8000
366 12:47:11.099905 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
367 12:47:11.103297 CBFS: Locating 'fallback/romstage'
368 12:47:11.106645 CBFS: Found @ offset 80 size 145fc
369 12:47:11.109472 Accumulated console time in verstage 98 ms
370 12:47:11.110176
371 12:47:11.110703
372 12:47:11.123099 coreboot-v1.9308_26_0.0.22-11197-gc9b4b7136b Thu Mar 18 05:35:38 UTC 2021 romstage starting (log level: 8)...
373 12:47:11.129665 VB2:vb2api_ec_sync() In recovery mode, skipping EC sync
374 12:47:11.133094 pm1_sts: 0100 pm1_en: 0000 pm1_cnt: 00001c00
375 12:47:11.136325 gpe0_sts[0]: 00000000 gpe0_en[0]: 00000000
376 12:47:11.142915 gpe0_sts[1]: 00200000 gpe0_en[1]: 00000000
377 12:47:11.146353 gpe0_sts[2]: 00000000 gpe0_en[2]: 00000000
378 12:47:11.149842 gpe0_sts[3]: 00000000 gpe0_en[3]: 00000000
379 12:47:11.152953 TCO_STS: 0000 0000
380 12:47:11.156209 GEN_PMCON: e0015238 00000200
381 12:47:11.159125 GBLRST_CAUSE: 00000000 00000000
382 12:47:11.159599 prev_sleep_state 5
383 12:47:11.163237 Boot Count incremented to 75341
384 12:47:11.169917 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
385 12:47:11.173111 CBFS @ c08000 size 3f8000
386 12:47:11.179431 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
387 12:47:11.180028 CBFS: Locating 'fspm.bin'
388 12:47:11.186247 CBFS: Found @ offset 5ffc0 size 71000
389 12:47:11.189741 Chrome EC: UHEPI supported
390 12:47:11.196503 FMAP: area RECOVERY_MRC_CACHE found @ ad0000 (65536 bytes)
391 12:47:11.199897 Probing TPM: done!
392 12:47:11.206472 Connected to device vid:did:rid of 1ae0:0028:00
393 12:47:11.216230 Firmware version: B2-C:0 RO_B:0.0.11/4d655eab RW_A:0.5.7/cr50_v1.9308_87_mp.514-29d5b602
394 12:47:11.222188 Initialized TPM device CR50 revision 0
395 12:47:11.231226 src/security/tpm/tss/tcg-2.0/tss.c:223 index 0x100b return code 0
396 12:47:11.237823 MRC: Hash comparison successful. Using data from RECOVERY_MRC_CACHE
397 12:47:11.241081 MRC cache found, size 1948
398 12:47:11.244728 bootmode is set to: 2
399 12:47:11.247735 PRMRR disabled by config.
400 12:47:11.250966 SPD INDEX = 1
401 12:47:11.254763 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
402 12:47:11.257870 CBFS @ c08000 size 3f8000
403 12:47:11.265018 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
404 12:47:11.265594 CBFS: Locating 'spd.bin'
405 12:47:11.268880 CBFS: Found @ offset 5fb80 size 400
406 12:47:11.270933 SPD: module type is LPDDR3
407 12:47:11.274642 SPD: module part is
408 12:47:11.281044 SPD: banks 16, ranks 2, rows 15, columns 11, density 8192 Mb
409 12:47:11.284664 SPD: device width 4 bits, bus width 8 bits
410 12:47:11.287884 SPD: module size is 4096 MB (per channel)
411 12:47:11.291030 memory slot: 0 configuration done.
412 12:47:11.294539 memory slot: 2 configuration done.
413 12:47:11.346685 CBMEM:
414 12:47:11.349419 IMD: root @ 99fff000 254 entries.
415 12:47:11.352624 IMD: root @ 99ffec00 62 entries.
416 12:47:11.356881 External stage cache:
417 12:47:11.359880 IMD: root @ 9abff000 254 entries.
418 12:47:11.363219 IMD: root @ 9abfec00 62 entries.
419 12:47:11.366921 Chrome EC: clear events_b mask to 0x0000000020004000
420 12:47:11.382401 src/security/tpm/tss/tcg-2.0/tss.c:223 index 0x100b return code 0
421 12:47:11.393061 tlcl_write: response is 0
422 12:47:11.405061 src/security/tpm/tss/tcg-2.0/tss.c:223 index 0x100b return code 0
423 12:47:11.411122 MRC: TPM MRC hash updated successfully.
424 12:47:11.411740 2 DIMMs found
425 12:47:11.414955 SMM Memory Map
426 12:47:11.418199 SMRAM : 0x9a000000 0x1000000
427 12:47:11.421135 Subregion 0: 0x9a000000 0xa00000
428 12:47:11.424457 Subregion 1: 0x9aa00000 0x200000
429 12:47:11.428030 Subregion 2: 0x9ac00000 0x400000
430 12:47:11.430946 top_of_ram = 0x9a000000
431 12:47:11.434483 MTRR Range: Start=99000000 End=9a000000 (Size 1000000)
432 12:47:11.440987 MTRR Range: Start=9a000000 End=9b000000 (Size 1000000)
433 12:47:11.444194 MTRR Range: Start=ff000000 End=0 (Size 1000000)
434 12:47:11.452306 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
435 12:47:11.454574 CBFS @ c08000 size 3f8000
436 12:47:11.458050 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
437 12:47:11.460784 CBFS: Locating 'fallback/postcar'
438 12:47:11.467776 CBFS: Found @ offset 107000 size 4b44
439 12:47:11.474049 Decompressing stage fallback/postcar @ 0x99c0bfc0 (35640 bytes)
440 12:47:11.484479 Loading module at 99c0c000 with entry 99c0c000. filesize: 0x4818 memsize: 0x8af8
441 12:47:11.487306 Processing 180 relocs. Offset value of 0x97c0c000
442 12:47:11.495442 Accumulated console time in romstage 286 ms
443 12:47:11.496249
444 12:47:11.496645
445 12:47:11.505563 coreboot-v1.9308_26_0.0.22-11197-gc9b4b7136b Thu Mar 18 05:35:38 UTC 2021 postcar starting (log level: 8)...
446 12:47:11.512109 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
447 12:47:11.515595 CBFS @ c08000 size 3f8000
448 12:47:11.518595 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
449 12:47:11.525336 CBFS: Locating 'fallback/ramstage'
450 12:47:11.528341 CBFS: Found @ offset 43380 size 1b9e8
451 12:47:11.535421 Decompressing stage fallback/ramstage @ 0x99baffc0 (372088 bytes)
452 12:47:11.567294 Loading module at 99bb0000 with entry 99bb0000. filesize: 0x40940 memsize: 0x5ad38
453 12:47:11.570884 Processing 3976 relocs. Offset value of 0x98db0000
454 12:47:11.576988 Accumulated console time in postcar 52 ms
455 12:47:11.577675
456 12:47:11.578057
457 12:47:11.587069 coreboot-v1.9308_26_0.0.22-11197-gc9b4b7136b Thu Mar 18 05:35:38 UTC 2021 ramstage starting (log level: 8)...
458 12:47:11.593733 FMAP: area RO_VPD found @ c00000 (16384 bytes)
459 12:47:11.597360 WARNING: RO_VPD is uninitialized or empty.
460 12:47:11.600341 FMAP: area RW_VPD found @ af8000 (8192 bytes)
461 12:47:11.606768 FMAP: area RW_VPD found @ af8000 (8192 bytes)
462 12:47:11.607247 Normal boot.
463 12:47:11.613809 BS: BS_PRE_DEVICE times (ms): entry 0 run 0 exit 0
464 12:47:11.616969 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
465 12:47:11.620564 CBFS @ c08000 size 3f8000
466 12:47:11.626691 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
467 12:47:11.630363 CBFS: Locating 'cpu_microcode_blob.bin'
468 12:47:11.633877 CBFS: Found @ offset 14700 size 2ec00
469 12:47:11.637388 microcode: sig=0x806ec pf=0x4 revision=0xc9
470 12:47:11.640158 Skip microcode update
471 12:47:11.646917 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
472 12:47:11.647507 CBFS @ c08000 size 3f8000
473 12:47:11.653187 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
474 12:47:11.656855 CBFS: Locating 'fsps.bin'
475 12:47:11.659907 CBFS: Found @ offset d1fc0 size 35000
476 12:47:11.685965 Detected 4 core, 8 thread CPU.
477 12:47:11.689034 Setting up SMI for CPU
478 12:47:11.692230 IED base = 0x9ac00000
479 12:47:11.692803 IED size = 0x00400000
480 12:47:11.695563 Will perform SMM setup.
481 12:47:11.702437 CPU: Intel(R) Core(TM) i5-10210U CPU @ 1.60GHz.
482 12:47:11.708762 Loading module at 00030000 with entry 00030000. filesize: 0x170 memsize: 0x170
483 12:47:11.711914 Processing 16 relocs. Offset value of 0x00030000
484 12:47:11.715933 Attempting to start 7 APs
485 12:47:11.718831 Waiting for 10ms after sending INIT.
486 12:47:11.735656 Waiting for 1st SIPI to complete...AP: slot 2 apic_id 1.
487 12:47:11.736297 done.
488 12:47:11.738820 AP: slot 7 apic_id 7.
489 12:47:11.742140 AP: slot 4 apic_id 6.
490 12:47:11.744888 Waiting for 2nd SIPI to complete...done.
491 12:47:11.748695 AP: slot 5 apic_id 2.
492 12:47:11.749267 AP: slot 6 apic_id 3.
493 12:47:11.751902 AP: slot 3 apic_id 5.
494 12:47:11.755115 AP: slot 1 apic_id 4.
495 12:47:11.761720 Loading module at 00038000 with entry 00038000. filesize: 0x1a8 memsize: 0x1a8
496 12:47:11.768729 Processing 13 relocs. Offset value of 0x00038000
497 12:47:11.775152 SMM Module: stub loaded at 00038000. Will call 99bcb71d(00000000)
498 12:47:11.778808 Installing SMM handler to 0x9a000000
499 12:47:11.784994 Loading module at 9a010000 with entry 9a010a52. filesize: 0x7e88 memsize: 0xcf58
500 12:47:11.791516 Processing 658 relocs. Offset value of 0x9a010000
501 12:47:11.798028 Loading module at 9a008000 with entry 9a008000. filesize: 0x1a8 memsize: 0x1a8
502 12:47:11.801768 Processing 13 relocs. Offset value of 0x9a008000
503 12:47:11.808929 SMM Module: placing jmp sequence at 9a007c00 rel16 0x03fd
504 12:47:11.814804 SMM Module: placing jmp sequence at 9a007800 rel16 0x07fd
505 12:47:11.821395 SMM Module: placing jmp sequence at 9a007400 rel16 0x0bfd
506 12:47:11.825476 SMM Module: placing jmp sequence at 9a007000 rel16 0x0ffd
507 12:47:11.831634 SMM Module: placing jmp sequence at 9a006c00 rel16 0x13fd
508 12:47:11.838157 SMM Module: placing jmp sequence at 9a006800 rel16 0x17fd
509 12:47:11.841187 SMM Module: placing jmp sequence at 9a006400 rel16 0x1bfd
510 12:47:11.847876 SMM Module: stub loaded at 9a008000. Will call 9a010a52(00000000)
511 12:47:11.851878 Clearing SMI status registers
512 12:47:11.854866 SMI_STS: PM1
513 12:47:11.855440 PM1_STS: PWRBTN
514 12:47:11.858035 TCO_STS: SECOND_TO
515 12:47:11.861527 New SMBASE 0x9a000000
516 12:47:11.864596 In relocation handler: CPU 0
517 12:47:11.868321 New SMBASE=0x9a000000 IEDBASE=0x9ac00000
518 12:47:11.871559 Writing SMRR. base = 0x9a000006, mask=0xff000800
519 12:47:11.874784 Relocation complete.
520 12:47:11.878150 New SMBASE 0x99fff800
521 12:47:11.881705 In relocation handler: CPU 2
522 12:47:11.884971 New SMBASE=0x99fff800 IEDBASE=0x9ac00000
523 12:47:11.887889 Writing SMRR. base = 0x9a000006, mask=0xff000800
524 12:47:11.891352 Relocation complete.
525 12:47:11.895487 New SMBASE 0x99ffec00
526 12:47:11.896133 In relocation handler: CPU 5
527 12:47:11.901014 New SMBASE=0x99ffec00 IEDBASE=0x9ac00000
528 12:47:11.904394 Writing SMRR. base = 0x9a000006, mask=0xff000800
529 12:47:11.907740 Relocation complete.
530 12:47:11.911042 New SMBASE 0x99ffe800
531 12:47:11.911614 In relocation handler: CPU 6
532 12:47:11.918171 New SMBASE=0x99ffe800 IEDBASE=0x9ac00000
533 12:47:11.921434 Writing SMRR. base = 0x9a000006, mask=0xff000800
534 12:47:11.924936 Relocation complete.
535 12:47:11.925505 New SMBASE 0x99fff000
536 12:47:11.927878 In relocation handler: CPU 4
537 12:47:11.934511 New SMBASE=0x99fff000 IEDBASE=0x9ac00000
538 12:47:11.937779 Writing SMRR. base = 0x9a000006, mask=0xff000800
539 12:47:11.941338 Relocation complete.
540 12:47:11.941900 New SMBASE 0x99fff400
541 12:47:11.944100 In relocation handler: CPU 3
542 12:47:11.950740 New SMBASE=0x99fff400 IEDBASE=0x9ac00000
543 12:47:11.954203 Writing SMRR. base = 0x9a000006, mask=0xff000800
544 12:47:11.957640 Relocation complete.
545 12:47:11.958253 New SMBASE 0x99fffc00
546 12:47:11.960495 In relocation handler: CPU 1
547 12:47:11.964169 New SMBASE=0x99fffc00 IEDBASE=0x9ac00000
548 12:47:11.970918 Writing SMRR. base = 0x9a000006, mask=0xff000800
549 12:47:11.973795 Relocation complete.
550 12:47:11.974555 New SMBASE 0x99ffe400
551 12:47:11.977093 In relocation handler: CPU 7
552 12:47:11.980449 New SMBASE=0x99ffe400 IEDBASE=0x9ac00000
553 12:47:11.986804 Writing SMRR. base = 0x9a000006, mask=0xff000800
554 12:47:11.990507 Relocation complete.
555 12:47:11.990973 Initializing CPU #0
556 12:47:11.993961 CPU: vendor Intel device 806ec
557 12:47:11.997040 CPU: family 06, model 8e, stepping 0c
558 12:47:12.000425 Clearing out pending MCEs
559 12:47:12.004080 Setting up local APIC...
560 12:47:12.007308 apic_id: 0x00 done.
561 12:47:12.007785 Turbo is available but hidden
562 12:47:12.010962 Turbo is available and visible
563 12:47:12.013793 VMX status: enabled
564 12:47:12.016938 IA32_FEATURE_CONTROL status: locked
565 12:47:12.020774 Skip microcode update
566 12:47:12.021342 CPU #0 initialized
567 12:47:12.023839 Initializing CPU #2
568 12:47:12.027205 Initializing CPU #5
569 12:47:12.027771 Initializing CPU #6
570 12:47:12.030207 CPU: vendor Intel device 806ec
571 12:47:12.033598 CPU: family 06, model 8e, stepping 0c
572 12:47:12.036824 CPU: vendor Intel device 806ec
573 12:47:12.040527 CPU: family 06, model 8e, stepping 0c
574 12:47:12.043426 Clearing out pending MCEs
575 12:47:12.046863 Clearing out pending MCEs
576 12:47:12.050463 Setting up local APIC...
577 12:47:12.053519 CPU: vendor Intel device 806ec
578 12:47:12.057121 CPU: family 06, model 8e, stepping 0c
579 12:47:12.060358 Clearing out pending MCEs
580 12:47:12.061011 Initializing CPU #1
581 12:47:12.063339 Initializing CPU #3
582 12:47:12.067147 CPU: vendor Intel device 806ec
583 12:47:12.070500 CPU: family 06, model 8e, stepping 0c
584 12:47:12.073315 CPU: vendor Intel device 806ec
585 12:47:12.076757 CPU: family 06, model 8e, stepping 0c
586 12:47:12.080145 Clearing out pending MCEs
587 12:47:12.083872 Clearing out pending MCEs
588 12:47:12.084507 Setting up local APIC...
589 12:47:12.086921 Initializing CPU #7
590 12:47:12.090034 Initializing CPU #4
591 12:47:12.093304 CPU: vendor Intel device 806ec
592 12:47:12.097159 CPU: family 06, model 8e, stepping 0c
593 12:47:12.100318 CPU: vendor Intel device 806ec
594 12:47:12.104187 CPU: family 06, model 8e, stepping 0c
595 12:47:12.106516 Clearing out pending MCEs
596 12:47:12.107093 Clearing out pending MCEs
597 12:47:12.109940 Setting up local APIC...
598 12:47:12.112980 Setting up local APIC...
599 12:47:12.116444 Setting up local APIC...
600 12:47:12.116929 Setting up local APIC...
601 12:47:12.120365 apic_id: 0x07 done.
602 12:47:12.123438 Setting up local APIC...
603 12:47:12.124009 apic_id: 0x01 done.
604 12:47:12.126626 apic_id: 0x06 done.
605 12:47:12.130162 VMX status: enabled
606 12:47:12.130725 VMX status: enabled
607 12:47:12.132757 IA32_FEATURE_CONTROL status: locked
608 12:47:12.140168 IA32_FEATURE_CONTROL status: locked
609 12:47:12.140757 Skip microcode update
610 12:47:12.143215 Skip microcode update
611 12:47:12.143789 CPU #7 initialized
612 12:47:12.146441 CPU #4 initialized
613 12:47:12.150212 VMX status: enabled
614 12:47:12.150803 apic_id: 0x05 done.
615 12:47:12.152801 apic_id: 0x04 done.
616 12:47:12.156478 VMX status: enabled
617 12:47:12.157048 VMX status: enabled
618 12:47:12.159760 IA32_FEATURE_CONTROL status: locked
619 12:47:12.163090 IA32_FEATURE_CONTROL status: locked
620 12:47:12.166809 Skip microcode update
621 12:47:12.169628 Skip microcode update
622 12:47:12.170095 CPU #3 initialized
623 12:47:12.172894 CPU #1 initialized
624 12:47:12.176378 IA32_FEATURE_CONTROL status: locked
625 12:47:12.180699 apic_id: 0x02 done.
626 12:47:12.181324 apic_id: 0x03 done.
627 12:47:12.183381 VMX status: enabled
628 12:47:12.186275 VMX status: enabled
629 12:47:12.189889 IA32_FEATURE_CONTROL status: locked
630 12:47:12.193301 IA32_FEATURE_CONTROL status: locked
631 12:47:12.193870 Skip microcode update
632 12:47:12.196235 Skip microcode update
633 12:47:12.199816 CPU #5 initialized
634 12:47:12.200440 CPU #6 initialized
635 12:47:12.204611 Skip microcode update
636 12:47:12.206094 CPU #2 initialized
637 12:47:12.209263 bsp_do_flight_plan done after 462 msecs.
638 12:47:12.212924 CPU: frequency set to 4200 MHz
639 12:47:12.213676 Enabling SMIs.
640 12:47:12.215945 Locking SMM.
641 12:47:12.229887 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
642 12:47:12.232792 CBFS @ c08000 size 3f8000
643 12:47:12.239486 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
644 12:47:12.240093 CBFS: Locating 'vbt.bin'
645 12:47:12.246367 CBFS: Found @ offset 5f5c0 size 499
646 12:47:12.249883 Found a VBT of 4608 bytes after decompression
647 12:47:12.434424 Display FSP Version Info HOB
648 12:47:12.437133 Reference Code - CPU = 9.0.1e.30
649 12:47:12.441487 uCode Version = 0.0.0.ca
650 12:47:12.444104 TXT ACM version = ff.ff.ff.ffff
651 12:47:12.447719 Display FSP Version Info HOB
652 12:47:12.450753 Reference Code - ME = 9.0.1e.30
653 12:47:12.454289 MEBx version = 0.0.0.0
654 12:47:12.457722 ME Firmware Version = Consumer SKU
655 12:47:12.461120 Display FSP Version Info HOB
656 12:47:12.464130 Reference Code - CML PCH = 9.0.1e.30
657 12:47:12.467430 PCH-CRID Status = Disabled
658 12:47:12.470361 PCH-CRID Original Value = ff.ff.ff.ffff
659 12:47:12.474190 PCH-CRID New Value = ff.ff.ff.ffff
660 12:47:12.476914 OPROM - RST - RAID = ff.ff.ff.ffff
661 12:47:12.480827 ChipsetInit Base Version = ff.ff.ff.ffff
662 12:47:12.484497 ChipsetInit Oem Version = ff.ff.ff.ffff
663 12:47:12.487379 Display FSP Version Info HOB
664 12:47:12.493532 Reference Code - SA - System Agent = 9.0.1e.30
665 12:47:12.496946 Reference Code - MRC = 0.7.1.6c
666 12:47:12.497514 SA - PCIe Version = 9.0.1e.30
667 12:47:12.500464 SA-CRID Status = Disabled
668 12:47:12.503794 SA-CRID Original Value = 0.0.0.c
669 12:47:12.506921 SA-CRID New Value = 0.0.0.c
670 12:47:12.510751 OPROM - VBIOS = ff.ff.ff.ffff
671 12:47:12.513198 RTC Init
672 12:47:12.517138 Set power on after power failure.
673 12:47:12.517832 Disabling Deep S3
674 12:47:12.520238 Disabling Deep S3
675 12:47:12.520803 Disabling Deep S4
676 12:47:12.524235 Disabling Deep S4
677 12:47:12.524828 Disabling Deep S5
678 12:47:12.527156 Disabling Deep S5
679 12:47:12.533586 BS: BS_DEV_INIT_CHIPS times (ms): entry 37 run 195 exit 1
680 12:47:12.534157 Enumerating buses...
681 12:47:12.540305 Show all devs... Before device enumeration.
682 12:47:12.540880 Root Device: enabled 1
683 12:47:12.544122 CPU_CLUSTER: 0: enabled 1
684 12:47:12.546973 DOMAIN: 0000: enabled 1
685 12:47:12.549819 APIC: 00: enabled 1
686 12:47:12.550289 PCI: 00:00.0: enabled 1
687 12:47:12.553310 PCI: 00:02.0: enabled 1
688 12:47:12.556711 PCI: 00:04.0: enabled 0
689 12:47:12.560328 PCI: 00:05.0: enabled 0
690 12:47:12.560908 PCI: 00:12.0: enabled 1
691 12:47:12.563858 PCI: 00:12.5: enabled 0
692 12:47:12.566808 PCI: 00:12.6: enabled 0
693 12:47:12.567375 PCI: 00:14.0: enabled 1
694 12:47:12.570076 PCI: 00:14.1: enabled 0
695 12:47:12.573289 PCI: 00:14.3: enabled 1
696 12:47:12.576697 PCI: 00:14.5: enabled 0
697 12:47:12.577264 PCI: 00:15.0: enabled 1
698 12:47:12.579981 PCI: 00:15.1: enabled 1
699 12:47:12.583577 PCI: 00:15.2: enabled 0
700 12:47:12.586971 PCI: 00:15.3: enabled 0
701 12:47:12.587535 PCI: 00:16.0: enabled 1
702 12:47:12.589840 PCI: 00:16.1: enabled 0
703 12:47:12.593211 PCI: 00:16.2: enabled 0
704 12:47:12.596698 PCI: 00:16.3: enabled 0
705 12:47:12.597269 PCI: 00:16.4: enabled 0
706 12:47:12.599724 PCI: 00:16.5: enabled 0
707 12:47:12.603566 PCI: 00:17.0: enabled 1
708 12:47:12.604195 PCI: 00:19.0: enabled 1
709 12:47:12.606160 PCI: 00:19.1: enabled 0
710 12:47:12.609735 PCI: 00:19.2: enabled 0
711 12:47:12.613143 PCI: 00:1a.0: enabled 0
712 12:47:12.613718 PCI: 00:1c.0: enabled 0
713 12:47:12.616887 PCI: 00:1c.1: enabled 0
714 12:47:12.619609 PCI: 00:1c.2: enabled 0
715 12:47:12.622838 PCI: 00:1c.3: enabled 0
716 12:47:12.623302 PCI: 00:1c.4: enabled 0
717 12:47:12.627572 PCI: 00:1c.5: enabled 0
718 12:47:12.629529 PCI: 00:1c.6: enabled 0
719 12:47:12.632781 PCI: 00:1c.7: enabled 0
720 12:47:12.633248 PCI: 00:1d.0: enabled 1
721 12:47:12.636024 PCI: 00:1d.1: enabled 0
722 12:47:12.639554 PCI: 00:1d.2: enabled 0
723 12:47:12.642883 PCI: 00:1d.3: enabled 0
724 12:47:12.643449 PCI: 00:1d.4: enabled 0
725 12:47:12.646288 PCI: 00:1d.5: enabled 1
726 12:47:12.649481 PCI: 00:1e.0: enabled 1
727 12:47:12.649947 PCI: 00:1e.1: enabled 0
728 12:47:12.652497 PCI: 00:1e.2: enabled 1
729 12:47:12.656036 PCI: 00:1e.3: enabled 1
730 12:47:12.659334 PCI: 00:1f.0: enabled 1
731 12:47:12.659797 PCI: 00:1f.1: enabled 1
732 12:47:12.662346 PCI: 00:1f.2: enabled 1
733 12:47:12.665897 PCI: 00:1f.3: enabled 1
734 12:47:12.669182 PCI: 00:1f.4: enabled 1
735 12:47:12.669656 PCI: 00:1f.5: enabled 1
736 12:47:12.672889 PCI: 00:1f.6: enabled 0
737 12:47:12.675771 USB0 port 0: enabled 1
738 12:47:12.676314 I2C: 00:15: enabled 1
739 12:47:12.678868 I2C: 00:5d: enabled 1
740 12:47:12.682502 GENERIC: 0.0: enabled 1
741 12:47:12.685784 I2C: 00:1a: enabled 1
742 12:47:12.686251 I2C: 00:38: enabled 1
743 12:47:12.689291 I2C: 00:39: enabled 1
744 12:47:12.692578 I2C: 00:3a: enabled 1
745 12:47:12.693002 I2C: 00:3b: enabled 1
746 12:47:12.695732 PCI: 00:00.0: enabled 1
747 12:47:12.699372 SPI: 00: enabled 1
748 12:47:12.699791 SPI: 01: enabled 1
749 12:47:12.702425 PNP: 0c09.0: enabled 1
750 12:47:12.705397 USB2 port 0: enabled 1
751 12:47:12.705821 USB2 port 1: enabled 1
752 12:47:12.709047 USB2 port 2: enabled 0
753 12:47:12.712278 USB2 port 3: enabled 0
754 12:47:12.712702 USB2 port 5: enabled 0
755 12:47:12.715809 USB2 port 6: enabled 1
756 12:47:12.718945 USB2 port 9: enabled 1
757 12:47:12.719372 USB3 port 0: enabled 1
758 12:47:12.722424 USB3 port 1: enabled 1
759 12:47:12.725709 USB3 port 2: enabled 1
760 12:47:12.729031 USB3 port 3: enabled 1
761 12:47:12.729555 USB3 port 4: enabled 0
762 12:47:12.732562 APIC: 04: enabled 1
763 12:47:12.733030 APIC: 01: enabled 1
764 12:47:12.736322 APIC: 05: enabled 1
765 12:47:12.739053 APIC: 06: enabled 1
766 12:47:12.739621 APIC: 02: enabled 1
767 12:47:12.742677 APIC: 03: enabled 1
768 12:47:12.745611 APIC: 07: enabled 1
769 12:47:12.746077 Compare with tree...
770 12:47:12.749268 Root Device: enabled 1
771 12:47:12.752453 CPU_CLUSTER: 0: enabled 1
772 12:47:12.753024 APIC: 00: enabled 1
773 12:47:12.755416 APIC: 04: enabled 1
774 12:47:12.759577 APIC: 01: enabled 1
775 12:47:12.760191 APIC: 05: enabled 1
776 12:47:12.762471 APIC: 06: enabled 1
777 12:47:12.765120 APIC: 02: enabled 1
778 12:47:12.765586 APIC: 03: enabled 1
779 12:47:12.768340 APIC: 07: enabled 1
780 12:47:12.772164 DOMAIN: 0000: enabled 1
781 12:47:12.775805 PCI: 00:00.0: enabled 1
782 12:47:12.778750 PCI: 00:02.0: enabled 1
783 12:47:12.779243 PCI: 00:04.0: enabled 0
784 12:47:12.782098 PCI: 00:05.0: enabled 0
785 12:47:12.785563 PCI: 00:12.0: enabled 1
786 12:47:12.788783 PCI: 00:12.5: enabled 0
787 12:47:12.791846 PCI: 00:12.6: enabled 0
788 12:47:12.792373 PCI: 00:14.0: enabled 1
789 12:47:12.795103 USB0 port 0: enabled 1
790 12:47:12.798429 USB2 port 0: enabled 1
791 12:47:12.802005 USB2 port 1: enabled 1
792 12:47:12.805364 USB2 port 2: enabled 0
793 12:47:12.805952 USB2 port 3: enabled 0
794 12:47:12.808529 USB2 port 5: enabled 0
795 12:47:12.811822 USB2 port 6: enabled 1
796 12:47:12.815520 USB2 port 9: enabled 1
797 12:47:12.818167 USB3 port 0: enabled 1
798 12:47:12.818658 USB3 port 1: enabled 1
799 12:47:12.821992 USB3 port 2: enabled 1
800 12:47:12.825047 USB3 port 3: enabled 1
801 12:47:12.829003 USB3 port 4: enabled 0
802 12:47:12.832010 PCI: 00:14.1: enabled 0
803 12:47:12.835699 PCI: 00:14.3: enabled 1
804 12:47:12.836322 PCI: 00:14.5: enabled 0
805 12:47:12.838038 PCI: 00:15.0: enabled 1
806 12:47:12.841958 I2C: 00:15: enabled 1
807 12:47:12.845549 PCI: 00:15.1: enabled 1
808 12:47:12.846125 I2C: 00:5d: enabled 1
809 12:47:12.848726 GENERIC: 0.0: enabled 1
810 12:47:12.852193 PCI: 00:15.2: enabled 0
811 12:47:12.854993 PCI: 00:15.3: enabled 0
812 12:47:12.858350 PCI: 00:16.0: enabled 1
813 12:47:12.858915 PCI: 00:16.1: enabled 0
814 12:47:12.861733 PCI: 00:16.2: enabled 0
815 12:47:12.865697 PCI: 00:16.3: enabled 0
816 12:47:12.868284 PCI: 00:16.4: enabled 0
817 12:47:12.871817 PCI: 00:16.5: enabled 0
818 12:47:12.872422 PCI: 00:17.0: enabled 1
819 12:47:12.874728 PCI: 00:19.0: enabled 1
820 12:47:12.878565 I2C: 00:1a: enabled 1
821 12:47:12.882406 I2C: 00:38: enabled 1
822 12:47:12.882974 I2C: 00:39: enabled 1
823 12:47:12.884576 I2C: 00:3a: enabled 1
824 12:47:12.888264 I2C: 00:3b: enabled 1
825 12:47:12.891494 PCI: 00:19.1: enabled 0
826 12:47:12.895081 PCI: 00:19.2: enabled 0
827 12:47:12.895655 PCI: 00:1a.0: enabled 0
828 12:47:12.897825 PCI: 00:1c.0: enabled 0
829 12:47:12.901272 PCI: 00:1c.1: enabled 0
830 12:47:12.904623 PCI: 00:1c.2: enabled 0
831 12:47:12.908293 PCI: 00:1c.3: enabled 0
832 12:47:12.908903 PCI: 00:1c.4: enabled 0
833 12:47:12.911835 PCI: 00:1c.5: enabled 0
834 12:47:12.914751 PCI: 00:1c.6: enabled 0
835 12:47:12.917743 PCI: 00:1c.7: enabled 0
836 12:47:12.918207 PCI: 00:1d.0: enabled 1
837 12:47:12.921026 PCI: 00:1d.1: enabled 0
838 12:47:12.924471 PCI: 00:1d.2: enabled 0
839 12:47:12.928418 PCI: 00:1d.3: enabled 0
840 12:47:12.931137 PCI: 00:1d.4: enabled 0
841 12:47:12.931611 PCI: 00:1d.5: enabled 1
842 12:47:12.934886 PCI: 00:00.0: enabled 1
843 12:47:12.938028 PCI: 00:1e.0: enabled 1
844 12:47:12.941338 PCI: 00:1e.1: enabled 0
845 12:47:12.944652 PCI: 00:1e.2: enabled 1
846 12:47:12.945228 SPI: 00: enabled 1
847 12:47:12.948365 PCI: 00:1e.3: enabled 1
848 12:47:12.952611 SPI: 01: enabled 1
849 12:47:12.954341 PCI: 00:1f.0: enabled 1
850 12:47:12.954930 PNP: 0c09.0: enabled 1
851 12:47:12.957982 PCI: 00:1f.1: enabled 1
852 12:47:12.961135 PCI: 00:1f.2: enabled 1
853 12:47:12.964450 PCI: 00:1f.3: enabled 1
854 12:47:12.967868 PCI: 00:1f.4: enabled 1
855 12:47:12.968501 PCI: 00:1f.5: enabled 1
856 12:47:12.971072 PCI: 00:1f.6: enabled 0
857 12:47:12.974352 Root Device scanning...
858 12:47:12.978164 scan_static_bus for Root Device
859 12:47:12.981142 CPU_CLUSTER: 0 enabled
860 12:47:12.981716 DOMAIN: 0000 enabled
861 12:47:12.984278 DOMAIN: 0000 scanning...
862 12:47:12.988522 PCI: pci_scan_bus for bus 00
863 12:47:12.991672 PCI: 00:00.0 [8086/0000] ops
864 12:47:12.994387 PCI: 00:00.0 [8086/9b61] enabled
865 12:47:12.997471 PCI: 00:02.0 [8086/0000] bus ops
866 12:47:13.000862 PCI: 00:02.0 [8086/9b41] enabled
867 12:47:13.004200 PCI: 00:04.0 [8086/1903] disabled
868 12:47:13.007575 PCI: 00:08.0 [8086/1911] enabled
869 12:47:13.010936 PCI: 00:12.0 [8086/02f9] enabled
870 12:47:13.014362 PCI: 00:14.0 [8086/0000] bus ops
871 12:47:13.017463 PCI: 00:14.0 [8086/02ed] enabled
872 12:47:13.020930 PCI: 00:14.2 [8086/02ef] enabled
873 12:47:13.023961 PCI: 00:14.3 [8086/02f0] enabled
874 12:47:13.027466 PCI: 00:15.0 [8086/0000] bus ops
875 12:47:13.030724 PCI: 00:15.0 [8086/02e8] enabled
876 12:47:13.033741 PCI: 00:15.1 [8086/0000] bus ops
877 12:47:13.037547 PCI: 00:15.1 [8086/02e9] enabled
878 12:47:13.040728 PCI: 00:16.0 [8086/0000] ops
879 12:47:13.044120 PCI: 00:16.0 [8086/02e0] enabled
880 12:47:13.047523 PCI: 00:17.0 [8086/0000] ops
881 12:47:13.050721 PCI: 00:17.0 [8086/02d3] enabled
882 12:47:13.054474 PCI: 00:19.0 [8086/0000] bus ops
883 12:47:13.057404 PCI: 00:19.0 [8086/02c5] enabled
884 12:47:13.061007 PCI: 00:1d.0 [8086/0000] bus ops
885 12:47:13.063852 PCI: 00:1d.0 [8086/02b0] enabled
886 12:47:13.067551 PCI: Static device PCI: 00:1d.5 not found, disabling it.
887 12:47:13.071134 PCI: 00:1e.0 [8086/0000] ops
888 12:47:13.074431 PCI: 00:1e.0 [8086/02a8] enabled
889 12:47:13.077204 PCI: 00:1e.2 [8086/0000] bus ops
890 12:47:13.081002 PCI: 00:1e.2 [8086/02aa] enabled
891 12:47:13.084004 PCI: 00:1e.3 [8086/0000] bus ops
892 12:47:13.087321 PCI: 00:1e.3 [8086/02ab] enabled
893 12:47:13.090457 PCI: 00:1f.0 [8086/0000] bus ops
894 12:47:13.093968 PCI: 00:1f.0 [8086/0284] enabled
895 12:47:13.100445 PCI: Static device PCI: 00:1f.1 not found, disabling it.
896 12:47:13.107059 PCI: Static device PCI: 00:1f.2 not found, disabling it.
897 12:47:13.110954 PCI: 00:1f.3 [8086/0000] bus ops
898 12:47:13.113936 PCI: 00:1f.3 [8086/02c8] enabled
899 12:47:13.117237 PCI: 00:1f.4 [8086/0000] bus ops
900 12:47:13.120265 PCI: 00:1f.4 [8086/02a3] enabled
901 12:47:13.123990 PCI: 00:1f.5 [8086/0000] bus ops
902 12:47:13.127189 PCI: 00:1f.5 [8086/02a4] enabled
903 12:47:13.129920 PCI: Leftover static devices:
904 12:47:13.130387 PCI: 00:05.0
905 12:47:13.130762 PCI: 00:12.5
906 12:47:13.133541 PCI: 00:12.6
907 12:47:13.134011 PCI: 00:14.1
908 12:47:13.136903 PCI: 00:14.5
909 12:47:13.137371 PCI: 00:15.2
910 12:47:13.140364 PCI: 00:15.3
911 12:47:13.140830 PCI: 00:16.1
912 12:47:13.141198 PCI: 00:16.2
913 12:47:13.143362 PCI: 00:16.3
914 12:47:13.143856 PCI: 00:16.4
915 12:47:13.147149 PCI: 00:16.5
916 12:47:13.147719 PCI: 00:19.1
917 12:47:13.148131 PCI: 00:19.2
918 12:47:13.150183 PCI: 00:1a.0
919 12:47:13.150753 PCI: 00:1c.0
920 12:47:13.153878 PCI: 00:1c.1
921 12:47:13.154469 PCI: 00:1c.2
922 12:47:13.154850 PCI: 00:1c.3
923 12:47:13.156797 PCI: 00:1c.4
924 12:47:13.157263 PCI: 00:1c.5
925 12:47:13.160157 PCI: 00:1c.6
926 12:47:13.160735 PCI: 00:1c.7
927 12:47:13.163235 PCI: 00:1d.1
928 12:47:13.163706 PCI: 00:1d.2
929 12:47:13.164119 PCI: 00:1d.3
930 12:47:13.167267 PCI: 00:1d.4
931 12:47:13.167839 PCI: 00:1d.5
932 12:47:13.170438 PCI: 00:1e.1
933 12:47:13.171016 PCI: 00:1f.1
934 12:47:13.171388 PCI: 00:1f.2
935 12:47:13.173933 PCI: 00:1f.6
936 12:47:13.177175 PCI: Check your devicetree.cb.
937 12:47:13.180681 PCI: 00:02.0 scanning...
938 12:47:13.183469 scan_generic_bus for PCI: 00:02.0
939 12:47:13.186914 scan_generic_bus for PCI: 00:02.0 done
940 12:47:13.193325 scan_bus: scanning of bus PCI: 00:02.0 took 10186 usecs
941 12:47:13.193905 PCI: 00:14.0 scanning...
942 12:47:13.197751 scan_static_bus for PCI: 00:14.0
943 12:47:13.200093 USB0 port 0 enabled
944 12:47:13.203809 USB0 port 0 scanning...
945 12:47:13.207286 scan_static_bus for USB0 port 0
946 12:47:13.207856 USB2 port 0 enabled
947 12:47:13.209533 USB2 port 1 enabled
948 12:47:13.213117 USB2 port 2 disabled
949 12:47:13.213689 USB2 port 3 disabled
950 12:47:13.216478 USB2 port 5 disabled
951 12:47:13.219788 USB2 port 6 enabled
952 12:47:13.220429 USB2 port 9 enabled
953 12:47:13.223606 USB3 port 0 enabled
954 12:47:13.224115 USB3 port 1 enabled
955 12:47:13.227042 USB3 port 2 enabled
956 12:47:13.229575 USB3 port 3 enabled
957 12:47:13.230047 USB3 port 4 disabled
958 12:47:13.233512 USB2 port 0 scanning...
959 12:47:13.236034 scan_static_bus for USB2 port 0
960 12:47:13.240170 scan_static_bus for USB2 port 0 done
961 12:47:13.246382 scan_bus: scanning of bus USB2 port 0 took 9696 usecs
962 12:47:13.249543 USB2 port 1 scanning...
963 12:47:13.252623 scan_static_bus for USB2 port 1
964 12:47:13.256131 scan_static_bus for USB2 port 1 done
965 12:47:13.259845 scan_bus: scanning of bus USB2 port 1 took 9696 usecs
966 12:47:13.262867 USB2 port 6 scanning...
967 12:47:13.266302 scan_static_bus for USB2 port 6
968 12:47:13.269645 scan_static_bus for USB2 port 6 done
969 12:47:13.276161 scan_bus: scanning of bus USB2 port 6 took 9705 usecs
970 12:47:13.279632 USB2 port 9 scanning...
971 12:47:13.283028 scan_static_bus for USB2 port 9
972 12:47:13.286138 scan_static_bus for USB2 port 9 done
973 12:47:13.289255 scan_bus: scanning of bus USB2 port 9 took 9697 usecs
974 12:47:13.293022 USB3 port 0 scanning...
975 12:47:13.296338 scan_static_bus for USB3 port 0
976 12:47:13.299299 scan_static_bus for USB3 port 0 done
977 12:47:13.305601 scan_bus: scanning of bus USB3 port 0 took 9703 usecs
978 12:47:13.309335 USB3 port 1 scanning...
979 12:47:13.312616 scan_static_bus for USB3 port 1
980 12:47:13.316038 scan_static_bus for USB3 port 1 done
981 12:47:13.319588 scan_bus: scanning of bus USB3 port 1 took 9704 usecs
982 12:47:13.322508 USB3 port 2 scanning...
983 12:47:13.326122 scan_static_bus for USB3 port 2
984 12:47:13.329185 scan_static_bus for USB3 port 2 done
985 12:47:13.335654 scan_bus: scanning of bus USB3 port 2 took 9688 usecs
986 12:47:13.339307 USB3 port 3 scanning...
987 12:47:13.342743 scan_static_bus for USB3 port 3
988 12:47:13.346328 scan_static_bus for USB3 port 3 done
989 12:47:13.348686 scan_bus: scanning of bus USB3 port 3 took 9696 usecs
990 12:47:13.355666 scan_static_bus for USB0 port 0 done
991 12:47:13.359298 scan_bus: scanning of bus USB0 port 0 took 155346 usecs
992 12:47:13.362278 scan_static_bus for PCI: 00:14.0 done
993 12:47:13.368887 scan_bus: scanning of bus PCI: 00:14.0 took 172945 usecs
994 12:47:13.371935 PCI: 00:15.0 scanning...
995 12:47:13.375770 scan_generic_bus for PCI: 00:15.0
996 12:47:13.378521 bus: PCI: 00:15.0[0]->I2C: 01:15 enabled
997 12:47:13.382576 scan_generic_bus for PCI: 00:15.0 done
998 12:47:13.388970 scan_bus: scanning of bus PCI: 00:15.0 took 14293 usecs
999 12:47:13.392296 PCI: 00:15.1 scanning...
1000 12:47:13.395777 scan_generic_bus for PCI: 00:15.1
1001 12:47:13.398422 bus: PCI: 00:15.1[0]->I2C: 02:5d enabled
1002 12:47:13.405428 bus: PCI: 00:15.1[0]->GENERIC: 0.0 enabled
1003 12:47:13.408305 scan_generic_bus for PCI: 00:15.1 done
1004 12:47:13.411689 scan_bus: scanning of bus PCI: 00:15.1 took 18598 usecs
1005 12:47:13.415146 PCI: 00:19.0 scanning...
1006 12:47:13.419565 scan_generic_bus for PCI: 00:19.0
1007 12:47:13.421459 bus: PCI: 00:19.0[0]->I2C: 03:1a enabled
1008 12:47:13.428504 bus: PCI: 00:19.0[0]->I2C: 03:38 enabled
1009 12:47:13.431669 bus: PCI: 00:19.0[0]->I2C: 03:39 enabled
1010 12:47:13.435484 bus: PCI: 00:19.0[0]->I2C: 03:3a enabled
1011 12:47:13.439233 bus: PCI: 00:19.0[0]->I2C: 03:3b enabled
1012 12:47:13.444776 scan_generic_bus for PCI: 00:19.0 done
1013 12:47:13.448505 scan_bus: scanning of bus PCI: 00:19.0 took 30715 usecs
1014 12:47:13.452305 PCI: 00:1d.0 scanning...
1015 12:47:13.454950 do_pci_scan_bridge for PCI: 00:1d.0
1016 12:47:13.458507 PCI: pci_scan_bus for bus 01
1017 12:47:13.461375 PCI: 01:00.0 [1c5c/1327] enabled
1018 12:47:13.464836 Enabling Common Clock Configuration
1019 12:47:13.471682 L1 Sub-State supported from root port 29
1020 12:47:13.472298 L1 Sub-State Support = 0xf
1021 12:47:13.474666 CommonModeRestoreTime = 0x28
1022 12:47:13.481930 Power On Value = 0x16, Power On Scale = 0x0
1023 12:47:13.482692 ASPM: Enabled L1
1024 12:47:13.488173 scan_bus: scanning of bus PCI: 00:1d.0 took 32772 usecs
1025 12:47:13.491362 PCI: 00:1e.2 scanning...
1026 12:47:13.495701 scan_generic_bus for PCI: 00:1e.2
1027 12:47:13.497802 bus: PCI: 00:1e.2[0]->SPI: 00 enabled
1028 12:47:13.501382 scan_generic_bus for PCI: 00:1e.2 done
1029 12:47:13.508019 scan_bus: scanning of bus PCI: 00:1e.2 took 13999 usecs
1030 12:47:13.508702 PCI: 00:1e.3 scanning...
1031 12:47:13.514354 scan_generic_bus for PCI: 00:1e.3
1032 12:47:13.518039 bus: PCI: 00:1e.3[0]->SPI: 01 enabled
1033 12:47:13.521593 scan_generic_bus for PCI: 00:1e.3 done
1034 12:47:13.524695 scan_bus: scanning of bus PCI: 00:1e.3 took 13990 usecs
1035 12:47:13.528166 PCI: 00:1f.0 scanning...
1036 12:47:13.531492 scan_static_bus for PCI: 00:1f.0
1037 12:47:13.534675 PNP: 0c09.0 enabled
1038 12:47:13.538458 scan_static_bus for PCI: 00:1f.0 done
1039 12:47:13.544497 scan_bus: scanning of bus PCI: 00:1f.0 took 12046 usecs
1040 12:47:13.547530 PCI: 00:1f.3 scanning...
1041 12:47:13.551089 scan_bus: scanning of bus PCI: 00:1f.3 took 2859 usecs
1042 12:47:13.554923 PCI: 00:1f.4 scanning...
1043 12:47:13.558361 scan_generic_bus for PCI: 00:1f.4
1044 12:47:13.561419 scan_generic_bus for PCI: 00:1f.4 done
1045 12:47:13.568001 scan_bus: scanning of bus PCI: 00:1f.4 took 10181 usecs
1046 12:47:13.571141 PCI: 00:1f.5 scanning...
1047 12:47:13.574672 scan_generic_bus for PCI: 00:1f.5
1048 12:47:13.578028 scan_generic_bus for PCI: 00:1f.5 done
1049 12:47:13.584701 scan_bus: scanning of bus PCI: 00:1f.5 took 10191 usecs
1050 12:47:13.587613 scan_bus: scanning of bus DOMAIN: 0000 took 604801 usecs
1051 12:47:13.593954 scan_static_bus for Root Device done
1052 12:47:13.597604 scan_bus: scanning of bus Root Device took 624716 usecs
1053 12:47:13.600797 done
1054 12:47:13.601398 Chrome EC: UHEPI supported
1055 12:47:13.607605 FMAP: area RECOVERY_MRC_CACHE found @ ad0000 (65536 bytes)
1056 12:47:13.613772 MRC: Checking cached data update for 'RECOVERY_MRC_CACHE'.
1057 12:47:13.620741 SF: Detected 00 0000 with sector size 0x1000, total 0x1000000
1058 12:47:13.627508 FMAP: area UNIFIED_MRC_CACHE found @ ad0000 (131072 bytes)
1059 12:47:13.630776 SPI flash protection: WPSW=0 SRP0=0
1060 12:47:13.637594 MRC: NOT enabling PRR for 'UNIFIED_MRC_CACHE'.
1061 12:47:13.640436 BS: BS_DEV_ENUMERATE times (ms): entry 0 run 10 exit 2
1062 12:47:13.644010 found VGA at PCI: 00:02.0
1063 12:47:13.647488 Setting up VGA for PCI: 00:02.0
1064 12:47:13.654034 Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
1065 12:47:13.657828 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
1066 12:47:13.660502 Allocating resources...
1067 12:47:13.660975 Reading resources...
1068 12:47:13.667277 Root Device read_resources bus 0 link: 0
1069 12:47:13.670758 CPU_CLUSTER: 0 read_resources bus 0 link: 0
1070 12:47:13.676974 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
1071 12:47:13.681184 DOMAIN: 0000 read_resources bus 0 link: 0
1072 12:47:13.687024 PCI: 00:14.0 read_resources bus 0 link: 0
1073 12:47:13.690481 USB0 port 0 read_resources bus 0 link: 0
1074 12:47:13.699237 USB0 port 0 read_resources bus 0 link: 0 done
1075 12:47:13.701529 PCI: 00:14.0 read_resources bus 0 link: 0 done
1076 12:47:13.708908 PCI: 00:15.0 read_resources bus 1 link: 0
1077 12:47:13.712466 PCI: 00:15.0 read_resources bus 1 link: 0 done
1078 12:47:13.719197 PCI: 00:15.1 read_resources bus 2 link: 0
1079 12:47:13.722191 PCI: 00:15.1 read_resources bus 2 link: 0 done
1080 12:47:13.729685 PCI: 00:19.0 read_resources bus 3 link: 0
1081 12:47:13.736324 PCI: 00:19.0 read_resources bus 3 link: 0 done
1082 12:47:13.739530 PCI: 00:1d.0 read_resources bus 1 link: 0
1083 12:47:13.746025 PCI: 00:1d.0 read_resources bus 1 link: 0 done
1084 12:47:13.750037 PCI: 00:1e.2 read_resources bus 4 link: 0
1085 12:47:13.756394 PCI: 00:1e.2 read_resources bus 4 link: 0 done
1086 12:47:13.759311 PCI: 00:1e.3 read_resources bus 5 link: 0
1087 12:47:13.765932 PCI: 00:1e.3 read_resources bus 5 link: 0 done
1088 12:47:13.769382 PCI: 00:1f.0 read_resources bus 0 link: 0
1089 12:47:13.777082 PCI: 00:1f.0 read_resources bus 0 link: 0 done
1090 12:47:13.783366 DOMAIN: 0000 read_resources bus 0 link: 0 done
1091 12:47:13.786612 Root Device read_resources bus 0 link: 0 done
1092 12:47:13.789418 Done reading resources.
1093 12:47:13.796251 Show resources in subtree (Root Device)...After reading.
1094 12:47:13.799630 Root Device child on link 0 CPU_CLUSTER: 0
1095 12:47:13.803522 CPU_CLUSTER: 0 child on link 0 APIC: 00
1096 12:47:13.804119 APIC: 00
1097 12:47:13.806040 APIC: 04
1098 12:47:13.806599 APIC: 01
1099 12:47:13.809658 APIC: 05
1100 12:47:13.810220 APIC: 06
1101 12:47:13.810588 APIC: 02
1102 12:47:13.812603 APIC: 03
1103 12:47:13.813065 APIC: 07
1104 12:47:13.816034 DOMAIN: 0000 child on link 0 PCI: 00:00.0
1105 12:47:13.872449 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
1106 12:47:13.873076 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100
1107 12:47:13.873993 PCI: 00:00.0
1108 12:47:13.874397 PCI: 00:00.0 resource base e0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index 0
1109 12:47:13.874866 PCI: 00:00.0 resource base fed10000 size 8000 align 0 gran 0 limit 0 flags f0000200 index 1
1110 12:47:13.875244 PCI: 00:00.0 resource base feda0000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 2
1111 12:47:13.922154 PCI: 00:00.0 resource base feda1000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 3
1112 12:47:13.922787 PCI: 00:00.0 resource base fc000000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 4
1113 12:47:13.923574 PCI: 00:00.0 resource base fed80000 size 4000 align 0 gran 0 limit 0 flags f0000200 index 5
1114 12:47:13.924193 PCI: 00:00.0 resource base fe000000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 6
1115 12:47:13.924558 PCI: 00:00.0 resource base fed90000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 7
1116 12:47:13.925256 PCI: 00:00.0 resource base fed91000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 8
1117 12:47:13.971945 PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 9
1118 12:47:13.972988 PCI: 00:00.0 resource base c0000 size 99f40000 align 0 gran 0 limit 0 flags e0004200 index a
1119 12:47:13.973423 PCI: 00:00.0 resource base 9a000000 size 1000000 align 0 gran 0 limit 0 flags f0004200 index b
1120 12:47:13.973807 PCI: 00:00.0 resource base 9b000000 size 4800000 align 0 gran 0 limit 0 flags f0000200 index c
1121 12:47:13.974211 PCI: 00:00.0 resource base 100000000 size 35e800000 align 0 gran 0 limit 0 flags e0004200 index d
1122 12:47:14.013947 PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index e
1123 12:47:14.014952 PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index f
1124 12:47:14.015355 PCI: 00:02.0
1125 12:47:14.015709 PCI: 00:02.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffffffffffff flags 201 index 10
1126 12:47:14.016087 PCI: 00:02.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffffffffffff flags 1201 index 18
1127 12:47:14.021355 PCI: 00:02.0 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 20
1128 12:47:14.021914 PCI: 00:04.0
1129 12:47:14.022281 PCI: 00:08.0
1130 12:47:14.031491 PCI: 00:08.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1131 12:47:14.034917 PCI: 00:12.0
1132 12:47:14.044976 PCI: 00:12.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1133 12:47:14.047994 PCI: 00:14.0 child on link 0 USB0 port 0
1134 12:47:14.057939 PCI: 00:14.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10
1135 12:47:14.061049 USB0 port 0 child on link 0 USB2 port 0
1136 12:47:14.064188 USB2 port 0
1137 12:47:14.064659 USB2 port 1
1138 12:47:14.067949 USB2 port 2
1139 12:47:14.068577 USB2 port 3
1140 12:47:14.071379 USB2 port 5
1141 12:47:14.071947 USB2 port 6
1142 12:47:14.074881 USB2 port 9
1143 12:47:14.077997 USB3 port 0
1144 12:47:14.078564 USB3 port 1
1145 12:47:14.080878 USB3 port 2
1146 12:47:14.081341 USB3 port 3
1147 12:47:14.084530 USB3 port 4
1148 12:47:14.085082 PCI: 00:14.2
1149 12:47:14.095032 PCI: 00:14.2 resource base 0 size 2000 align 13 gran 13 limit ffffffffffffffff flags 201 index 10
1150 12:47:14.104660 PCI: 00:14.2 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 18
1151 12:47:14.107517 PCI: 00:14.3
1152 12:47:14.117164 PCI: 00:14.3 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1153 12:47:14.120654 PCI: 00:15.0 child on link 0 I2C: 01:15
1154 12:47:14.130569 PCI: 00:15.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1155 12:47:14.131129 I2C: 01:15
1156 12:47:14.137053 PCI: 00:15.1 child on link 0 I2C: 02:5d
1157 12:47:14.147026 PCI: 00:15.1 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1158 12:47:14.147587 I2C: 02:5d
1159 12:47:14.150367 GENERIC: 0.0
1160 12:47:14.150926 PCI: 00:16.0
1161 12:47:14.160533 PCI: 00:16.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1162 12:47:14.163616 PCI: 00:17.0
1163 12:47:14.173186 PCI: 00:17.0 resource base 0 size 2000 align 13 gran 13 limit ffffffff flags 200 index 10
1164 12:47:14.180234 PCI: 00:17.0 resource base 0 size 100 align 12 gran 8 limit ffffffff flags 200 index 14
1165 12:47:14.190103 PCI: 00:17.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18
1166 12:47:14.196467 PCI: 00:17.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c
1167 12:47:14.206821 PCI: 00:17.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20
1168 12:47:14.216201 PCI: 00:17.0 resource base 0 size 800 align 12 gran 11 limit ffffffff flags 200 index 24
1169 12:47:14.220121 PCI: 00:19.0 child on link 0 I2C: 03:1a
1170 12:47:14.229762 PCI: 00:19.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1171 12:47:14.230334 I2C: 03:1a
1172 12:47:14.233109 I2C: 03:38
1173 12:47:14.233670 I2C: 03:39
1174 12:47:14.236960 I2C: 03:3a
1175 12:47:14.237527 I2C: 03:3b
1176 12:47:14.239617 PCI: 00:1d.0 child on link 0 PCI: 01:00.0
1177 12:47:14.249574 PCI: 00:1d.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
1178 12:47:14.259681 PCI: 00:1d.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
1179 12:47:14.269547 PCI: 00:1d.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
1180 12:47:14.270118 PCI: 01:00.0
1181 12:47:14.279071 PCI: 01:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1182 12:47:14.282318 PCI: 00:1e.0
1183 12:47:14.292458 PCI: 00:1e.0 resource base fe032000 size 1000 align 12 gran 12 limit ffffffffffffffff flags c0000200 index 10
1184 12:47:14.302221 PCI: 00:1e.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 18
1185 12:47:14.305869 PCI: 00:1e.2 child on link 0 SPI: 00
1186 12:47:14.316130 PCI: 00:1e.2 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1187 12:47:14.318880 SPI: 00
1188 12:47:14.322200 PCI: 00:1e.3 child on link 0 SPI: 01
1189 12:47:14.332240 PCI: 00:1e.3 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1190 12:47:14.332822 SPI: 01
1191 12:47:14.338830 PCI: 00:1f.0 child on link 0 PNP: 0c09.0
1192 12:47:14.345767 PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0000100 index 0
1193 12:47:14.355373 PCI: 00:1f.0 resource base 1800 size 100 align 0 gran 0 limit 0 flags c0000100 index 20
1194 12:47:14.359020 PNP: 0c09.0
1195 12:47:14.365077 PNP: 0c09.0 resource base 800 size 1ff align 0 gran 0 limit 0 flags c0000100 index 0
1196 12:47:14.368527 PCI: 00:1f.3
1197 12:47:14.378663 PCI: 00:1f.3 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1198 12:47:14.388526 PCI: 00:1f.3 resource base 0 size 100000 align 20 gran 20 limit ffffffffffffffff flags 201 index 20
1199 12:47:14.389116 PCI: 00:1f.4
1200 12:47:14.398460 PCI: 00:1f.4 resource base efa0 size 20 align 0 gran 0 limit efbf flags f0000100 index 20
1201 12:47:14.408437 PCI: 00:1f.4 resource base 0 size 100 align 12 gran 8 limit ffffffffffffffff flags 201 index 10
1202 12:47:14.409033 PCI: 00:1f.5
1203 12:47:14.418288 PCI: 00:1f.5 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
1204 12:47:14.424730 DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
1205 12:47:14.431871 PCI: 00:1d.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
1206 12:47:14.438167 PCI: 00:1d.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done
1207 12:47:14.441486 PCI: 00:02.0 20 * [0x0 - 0x3f] io
1208 12:47:14.445073 PCI: 00:17.0 20 * [0x40 - 0x5f] io
1209 12:47:14.448034 PCI: 00:17.0 18 * [0x60 - 0x67] io
1210 12:47:14.451200 PCI: 00:17.0 1c * [0x68 - 0x6b] io
1211 12:47:14.458243 DOMAIN: 0000 io: base: 6c size: 6c align: 6 gran: 0 limit: ffff done
1212 12:47:14.464298 DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff
1213 12:47:14.475003 PCI: 00:1d.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
1214 12:47:14.481426 PCI: 00:1d.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
1215 12:47:14.488343 PCI: 00:1d.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
1216 12:47:14.495409 PCI: 01:00.0 10 * [0x0 - 0x3fff] mem
1217 12:47:14.501676 PCI: 00:1d.0 mem: base: 4000 size: 100000 align: 20 gran: 20 limit: ffffffff done
1218 12:47:14.505394 PCI: 00:02.0 18 * [0x0 - 0xfffffff] prefmem
1219 12:47:14.511214 PCI: 00:02.0 10 * [0x10000000 - 0x10ffffff] mem
1220 12:47:14.514513 PCI: 00:1d.0 20 * [0x11000000 - 0x110fffff] mem
1221 12:47:14.521674 PCI: 00:1f.3 20 * [0x11100000 - 0x111fffff] mem
1222 12:47:14.524674 PCI: 00:14.0 10 * [0x11200000 - 0x1120ffff] mem
1223 12:47:14.531027 PCI: 00:14.3 10 * [0x11210000 - 0x11213fff] mem
1224 12:47:14.534347 PCI: 00:1f.3 10 * [0x11214000 - 0x11217fff] mem
1225 12:47:14.540974 PCI: 00:14.2 10 * [0x11218000 - 0x11219fff] mem
1226 12:47:14.544327 PCI: 00:17.0 10 * [0x1121a000 - 0x1121bfff] mem
1227 12:47:14.550993 PCI: 00:08.0 10 * [0x1121c000 - 0x1121cfff] mem
1228 12:47:14.554422 PCI: 00:12.0 10 * [0x1121d000 - 0x1121dfff] mem
1229 12:47:14.557547 PCI: 00:14.2 18 * [0x1121e000 - 0x1121efff] mem
1230 12:47:14.564369 PCI: 00:15.0 10 * [0x1121f000 - 0x1121ffff] mem
1231 12:47:14.567553 PCI: 00:15.1 10 * [0x11220000 - 0x11220fff] mem
1232 12:47:14.574725 PCI: 00:16.0 10 * [0x11221000 - 0x11221fff] mem
1233 12:47:14.577313 PCI: 00:19.0 10 * [0x11222000 - 0x11222fff] mem
1234 12:47:14.583800 PCI: 00:1e.0 18 * [0x11223000 - 0x11223fff] mem
1235 12:47:14.587357 PCI: 00:1e.2 10 * [0x11224000 - 0x11224fff] mem
1236 12:47:14.593865 PCI: 00:1e.3 10 * [0x11225000 - 0x11225fff] mem
1237 12:47:14.597619 PCI: 00:1f.5 10 * [0x11226000 - 0x11226fff] mem
1238 12:47:14.604315 PCI: 00:17.0 24 * [0x11227000 - 0x112277ff] mem
1239 12:47:14.607564 PCI: 00:17.0 14 * [0x11228000 - 0x112280ff] mem
1240 12:47:14.613470 PCI: 00:1f.4 10 * [0x11229000 - 0x112290ff] mem
1241 12:47:14.621412 DOMAIN: 0000 mem: base: 11229100 size: 11229100 align: 28 gran: 0 limit: ffffffff done
1242 12:47:14.623712 avoid_fixed_resources: DOMAIN: 0000
1243 12:47:14.630241 avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff
1244 12:47:14.637453 avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff
1245 12:47:14.643817 constrain_resources: PCI: 00:00.0 00 base e0000000 limit efffffff mem (fixed)
1246 12:47:14.650236 constrain_resources: PCI: 00:00.0 09 base 00000000 limit 0009ffff mem (fixed)
1247 12:47:14.660407 constrain_resources: PCI: 00:00.0 0a base 000c0000 limit 99ffffff mem (fixed)
1248 12:47:14.666946 constrain_resources: PCI: 00:00.0 0b base 9a000000 limit 9affffff mem (fixed)
1249 12:47:14.673819 constrain_resources: PCI: 00:00.0 0c base 9b000000 limit 9f7fffff mem (fixed)
1250 12:47:14.683187 constrain_resources: PCI: 00:1f.0 00 base 00000000 limit 00000fff io (fixed)
1251 12:47:14.690035 constrain_resources: PCI: 00:1f.0 20 base 00001800 limit 000018ff io (fixed)
1252 12:47:14.696659 constrain_resources: PCI: 00:1f.4 20 base 0000efa0 limit 0000efbf io (fixed)
1253 12:47:14.703725 avoid_fixed_resources:@DOMAIN: 0000 10000000 base 00001900 limit 0000ef9f
1254 12:47:14.713729 avoid_fixed_resources:@DOMAIN: 0000 10000100 base c0000000 limit dfffffff
1255 12:47:14.714294 Setting resources...
1256 12:47:14.719966 DOMAIN: 0000 io: base:1900 size:6c align:6 gran:0 limit:ef9f
1257 12:47:14.723520 PCI: 00:02.0 20 * [0x1c00 - 0x1c3f] io
1258 12:47:14.729975 PCI: 00:17.0 20 * [0x1c40 - 0x1c5f] io
1259 12:47:14.733051 PCI: 00:17.0 18 * [0x1c60 - 0x1c67] io
1260 12:47:14.736849 PCI: 00:17.0 1c * [0x1c68 - 0x1c6b] io
1261 12:47:14.743484 DOMAIN: 0000 io: next_base: 1c6c size: 6c align: 6 gran: 0 done
1262 12:47:14.750268 PCI: 00:1d.0 io: base:ef9f size:0 align:12 gran:12 limit:ef9f
1263 12:47:14.756988 PCI: 00:1d.0 io: next_base: ef9f size: 0 align: 12 gran: 12 done
1264 12:47:14.763379 DOMAIN: 0000 mem: base:c0000000 size:11229100 align:28 gran:0 limit:dfffffff
1265 12:47:14.769488 PCI: 00:02.0 18 * [0xc0000000 - 0xcfffffff] prefmem
1266 12:47:14.773340 PCI: 00:02.0 10 * [0xd0000000 - 0xd0ffffff] mem
1267 12:47:14.776180 PCI: 00:1d.0 20 * [0xd1000000 - 0xd10fffff] mem
1268 12:47:14.783218 PCI: 00:1f.3 20 * [0xd1100000 - 0xd11fffff] mem
1269 12:47:14.786260 PCI: 00:14.0 10 * [0xd1200000 - 0xd120ffff] mem
1270 12:47:14.793063 PCI: 00:14.3 10 * [0xd1210000 - 0xd1213fff] mem
1271 12:47:14.796614 PCI: 00:1f.3 10 * [0xd1214000 - 0xd1217fff] mem
1272 12:47:14.803208 PCI: 00:14.2 10 * [0xd1218000 - 0xd1219fff] mem
1273 12:47:14.806328 PCI: 00:17.0 10 * [0xd121a000 - 0xd121bfff] mem
1274 12:47:14.812995 PCI: 00:08.0 10 * [0xd121c000 - 0xd121cfff] mem
1275 12:47:14.816335 PCI: 00:12.0 10 * [0xd121d000 - 0xd121dfff] mem
1276 12:47:14.822607 PCI: 00:14.2 18 * [0xd121e000 - 0xd121efff] mem
1277 12:47:14.826532 PCI: 00:15.0 10 * [0xd121f000 - 0xd121ffff] mem
1278 12:47:14.833008 PCI: 00:15.1 10 * [0xd1220000 - 0xd1220fff] mem
1279 12:47:14.836370 PCI: 00:16.0 10 * [0xd1221000 - 0xd1221fff] mem
1280 12:47:14.839750 PCI: 00:19.0 10 * [0xd1222000 - 0xd1222fff] mem
1281 12:47:14.846217 PCI: 00:1e.0 18 * [0xd1223000 - 0xd1223fff] mem
1282 12:47:14.849714 PCI: 00:1e.2 10 * [0xd1224000 - 0xd1224fff] mem
1283 12:47:14.855917 PCI: 00:1e.3 10 * [0xd1225000 - 0xd1225fff] mem
1284 12:47:14.859550 PCI: 00:1f.5 10 * [0xd1226000 - 0xd1226fff] mem
1285 12:47:14.866094 PCI: 00:17.0 24 * [0xd1227000 - 0xd12277ff] mem
1286 12:47:14.869142 PCI: 00:17.0 14 * [0xd1228000 - 0xd12280ff] mem
1287 12:47:14.876140 PCI: 00:1f.4 10 * [0xd1229000 - 0xd12290ff] mem
1288 12:47:14.882469 DOMAIN: 0000 mem: next_base: d1229100 size: 11229100 align: 28 gran: 0 done
1289 12:47:14.888707 PCI: 00:1d.0 prefmem: base:dfffffff size:0 align:20 gran:20 limit:dfffffff
1290 12:47:14.895504 PCI: 00:1d.0 prefmem: next_base: dfffffff size: 0 align: 20 gran: 20 done
1291 12:47:14.906302 PCI: 00:1d.0 mem: base:d1000000 size:100000 align:20 gran:20 limit:d10fffff
1292 12:47:14.909227 PCI: 01:00.0 10 * [0xd1000000 - 0xd1003fff] mem
1293 12:47:14.915516 PCI: 00:1d.0 mem: next_base: d1004000 size: 100000 align: 20 gran: 20 done
1294 12:47:14.922001 Root Device assign_resources, bus 0 link: 0
1295 12:47:14.925417 DOMAIN: 0000 assign_resources, bus 0 link: 0
1296 12:47:14.935794 PCI: 00:02.0 10 <- [0x00d0000000 - 0x00d0ffffff] size 0x01000000 gran 0x18 mem64
1297 12:47:14.942182 PCI: 00:02.0 18 <- [0x00c0000000 - 0x00cfffffff] size 0x10000000 gran 0x1c prefmem64
1298 12:47:14.951924 PCI: 00:02.0 20 <- [0x0000001c00 - 0x0000001c3f] size 0x00000040 gran 0x06 io
1299 12:47:14.958796 PCI: 00:08.0 10 <- [0x00d121c000 - 0x00d121cfff] size 0x00001000 gran 0x0c mem64
1300 12:47:14.968317 PCI: 00:12.0 10 <- [0x00d121d000 - 0x00d121dfff] size 0x00001000 gran 0x0c mem64
1301 12:47:14.975075 PCI: 00:14.0 10 <- [0x00d1200000 - 0x00d120ffff] size 0x00010000 gran 0x10 mem64
1302 12:47:14.981723 PCI: 00:14.0 assign_resources, bus 0 link: 0
1303 12:47:14.984995 PCI: 00:14.0 assign_resources, bus 0 link: 0
1304 12:47:14.991734 PCI: 00:14.2 10 <- [0x00d1218000 - 0x00d1219fff] size 0x00002000 gran 0x0d mem64
1305 12:47:15.001411 PCI: 00:14.2 18 <- [0x00d121e000 - 0x00d121efff] size 0x00001000 gran 0x0c mem64
1306 12:47:15.007912 PCI: 00:14.3 10 <- [0x00d1210000 - 0x00d1213fff] size 0x00004000 gran 0x0e mem64
1307 12:47:15.018065 PCI: 00:15.0 10 <- [0x00d121f000 - 0x00d121ffff] size 0x00001000 gran 0x0c mem64
1308 12:47:15.022454 PCI: 00:15.0 assign_resources, bus 1 link: 0
1309 12:47:15.028197 PCI: 00:15.0 assign_resources, bus 1 link: 0
1310 12:47:15.034399 PCI: 00:15.1 10 <- [0x00d1220000 - 0x00d1220fff] size 0x00001000 gran 0x0c mem64
1311 12:47:15.041750 PCI: 00:15.1 assign_resources, bus 2 link: 0
1312 12:47:15.044679 PCI: 00:15.1 assign_resources, bus 2 link: 0
1313 12:47:15.054345 PCI: 00:16.0 10 <- [0x00d1221000 - 0x00d1221fff] size 0x00001000 gran 0x0c mem64
1314 12:47:15.061550 PCI: 00:17.0 10 <- [0x00d121a000 - 0x00d121bfff] size 0x00002000 gran 0x0d mem
1315 12:47:15.067726 PCI: 00:17.0 14 <- [0x00d1228000 - 0x00d12280ff] size 0x00000100 gran 0x08 mem
1316 12:47:15.078339 PCI: 00:17.0 18 <- [0x0000001c60 - 0x0000001c67] size 0x00000008 gran 0x03 io
1317 12:47:15.084321 PCI: 00:17.0 1c <- [0x0000001c68 - 0x0000001c6b] size 0x00000004 gran 0x02 io
1318 12:47:15.091576 PCI: 00:17.0 20 <- [0x0000001c40 - 0x0000001c5f] size 0x00000020 gran 0x05 io
1319 12:47:15.100911 PCI: 00:17.0 24 <- [0x00d1227000 - 0x00d12277ff] size 0x00000800 gran 0x0b mem
1320 12:47:15.107396 PCI: 00:19.0 10 <- [0x00d1222000 - 0x00d1222fff] size 0x00001000 gran 0x0c mem64
1321 12:47:15.111073 PCI: 00:19.0 assign_resources, bus 3 link: 0
1322 12:47:15.117318 PCI: 00:19.0 assign_resources, bus 3 link: 0
1323 12:47:15.123827 PCI: 00:1d.0 1c <- [0x000000ef9f - 0x000000ef9e] size 0x00000000 gran 0x0c bus 01 io
1324 12:47:15.133845 PCI: 00:1d.0 24 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 bus 01 prefmem
1325 12:47:15.144327 PCI: 00:1d.0 20 <- [0x00d1000000 - 0x00d10fffff] size 0x00100000 gran 0x14 bus 01 mem
1326 12:47:15.147197 PCI: 00:1d.0 assign_resources, bus 1 link: 0
1327 12:47:15.157303 PCI: 01:00.0 10 <- [0x00d1000000 - 0x00d1003fff] size 0x00004000 gran 0x0e mem64
1328 12:47:15.160796 PCI: 00:1d.0 assign_resources, bus 1 link: 0
1329 12:47:15.169988 PCI: 00:1e.0 18 <- [0x00d1223000 - 0x00d1223fff] size 0x00001000 gran 0x0c mem64
1330 12:47:15.176810 PCI: 00:1e.2 10 <- [0x00d1224000 - 0x00d1224fff] size 0x00001000 gran 0x0c mem64
1331 12:47:15.180739 PCI: 00:1e.2 assign_resources, bus 4 link: 0
1332 12:47:15.186770 PCI: 00:1e.2 assign_resources, bus 4 link: 0
1333 12:47:15.193356 PCI: 00:1e.3 10 <- [0x00d1225000 - 0x00d1225fff] size 0x00001000 gran 0x0c mem64
1334 12:47:15.199950 PCI: 00:1e.3 assign_resources, bus 5 link: 0
1335 12:47:15.203381 PCI: 00:1e.3 assign_resources, bus 5 link: 0
1336 12:47:15.210412 PCI: 00:1f.0 assign_resources, bus 0 link: 0
1337 12:47:15.213843 PCI: 00:1f.0 assign_resources, bus 0 link: 0
1338 12:47:15.219659 LPC: Trying to open IO window from 800 size 1ff
1339 12:47:15.226500 PCI: 00:1f.3 10 <- [0x00d1214000 - 0x00d1217fff] size 0x00004000 gran 0x0e mem64
1340 12:47:15.235967 PCI: 00:1f.3 20 <- [0x00d1100000 - 0x00d11fffff] size 0x00100000 gran 0x14 mem64
1341 12:47:15.243082 PCI: 00:1f.4 10 <- [0x00d1229000 - 0x00d12290ff] size 0x00000100 gran 0x08 mem64
1342 12:47:15.252569 PCI: 00:1f.5 10 <- [0x00d1226000 - 0x00d1226fff] size 0x00001000 gran 0x0c mem
1343 12:47:15.256132 DOMAIN: 0000 assign_resources, bus 0 link: 0
1344 12:47:15.260087 Root Device assign_resources, bus 0 link: 0
1345 12:47:15.262468 Done setting resources.
1346 12:47:15.268977 Show resources in subtree (Root Device)...After assigning values.
1347 12:47:15.272936 Root Device child on link 0 CPU_CLUSTER: 0
1348 12:47:15.279730 CPU_CLUSTER: 0 child on link 0 APIC: 00
1349 12:47:15.280335 APIC: 00
1350 12:47:15.280706 APIC: 04
1351 12:47:15.282589 APIC: 01
1352 12:47:15.283141 APIC: 05
1353 12:47:15.285694 APIC: 06
1354 12:47:15.286301 APIC: 02
1355 12:47:15.286671 APIC: 03
1356 12:47:15.288826 APIC: 07
1357 12:47:15.292860 DOMAIN: 0000 child on link 0 PCI: 00:00.0
1358 12:47:15.302028 DOMAIN: 0000 resource base 1900 size 6c align 6 gran 0 limit ef9f flags 40040100 index 10000000
1359 12:47:15.312846 DOMAIN: 0000 resource base c0000000 size 11229100 align 28 gran 0 limit dfffffff flags 40040200 index 10000100
1360 12:47:15.316251 PCI: 00:00.0
1361 12:47:15.325639 PCI: 00:00.0 resource base e0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index 0
1362 12:47:15.335349 PCI: 00:00.0 resource base fed10000 size 8000 align 0 gran 0 limit 0 flags f0000200 index 1
1363 12:47:15.341967 PCI: 00:00.0 resource base feda0000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 2
1364 12:47:15.351629 PCI: 00:00.0 resource base feda1000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 3
1365 12:47:15.361804 PCI: 00:00.0 resource base fc000000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 4
1366 12:47:15.371497 PCI: 00:00.0 resource base fed80000 size 4000 align 0 gran 0 limit 0 flags f0000200 index 5
1367 12:47:15.381438 PCI: 00:00.0 resource base fe000000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 6
1368 12:47:15.391953 PCI: 00:00.0 resource base fed90000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 7
1369 12:47:15.398218 PCI: 00:00.0 resource base fed91000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 8
1370 12:47:15.408222 PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 9
1371 12:47:15.417841 PCI: 00:00.0 resource base c0000 size 99f40000 align 0 gran 0 limit 0 flags e0004200 index a
1372 12:47:15.428013 PCI: 00:00.0 resource base 9a000000 size 1000000 align 0 gran 0 limit 0 flags f0004200 index b
1373 12:47:15.437570 PCI: 00:00.0 resource base 9b000000 size 4800000 align 0 gran 0 limit 0 flags f0000200 index c
1374 12:47:15.447734 PCI: 00:00.0 resource base 100000000 size 35e800000 align 0 gran 0 limit 0 flags e0004200 index d
1375 12:47:15.457262 PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index e
1376 12:47:15.463788 PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index f
1377 12:47:15.467410 PCI: 00:02.0
1378 12:47:15.476791 PCI: 00:02.0 resource base d0000000 size 1000000 align 24 gran 24 limit d0ffffff flags 60000201 index 10
1379 12:47:15.487159 PCI: 00:02.0 resource base c0000000 size 10000000 align 28 gran 28 limit cfffffff flags 60001201 index 18
1380 12:47:15.496888 PCI: 00:02.0 resource base 1c00 size 40 align 6 gran 6 limit 1c3f flags 60000100 index 20
1381 12:47:15.500356 PCI: 00:04.0
1382 12:47:15.500911 PCI: 00:08.0
1383 12:47:15.510674 PCI: 00:08.0 resource base d121c000 size 1000 align 12 gran 12 limit d121cfff flags 60000201 index 10
1384 12:47:15.513498 PCI: 00:12.0
1385 12:47:15.523128 PCI: 00:12.0 resource base d121d000 size 1000 align 12 gran 12 limit d121dfff flags 60000201 index 10
1386 12:47:15.526590 PCI: 00:14.0 child on link 0 USB0 port 0
1387 12:47:15.537516 PCI: 00:14.0 resource base d1200000 size 10000 align 16 gran 16 limit d120ffff flags 60000201 index 10
1388 12:47:15.543183 USB0 port 0 child on link 0 USB2 port 0
1389 12:47:15.543745 USB2 port 0
1390 12:47:15.546748 USB2 port 1
1391 12:47:15.547303 USB2 port 2
1392 12:47:15.549490 USB2 port 3
1393 12:47:15.549945 USB2 port 5
1394 12:47:15.553016 USB2 port 6
1395 12:47:15.553742 USB2 port 9
1396 12:47:15.556779 USB3 port 0
1397 12:47:15.557249 USB3 port 1
1398 12:47:15.559852 USB3 port 2
1399 12:47:15.560351 USB3 port 3
1400 12:47:15.563923 USB3 port 4
1401 12:47:15.564541 PCI: 00:14.2
1402 12:47:15.576369 PCI: 00:14.2 resource base d1218000 size 2000 align 13 gran 13 limit d1219fff flags 60000201 index 10
1403 12:47:15.586346 PCI: 00:14.2 resource base d121e000 size 1000 align 12 gran 12 limit d121efff flags 60000201 index 18
1404 12:47:15.586915 PCI: 00:14.3
1405 12:47:15.595805 PCI: 00:14.3 resource base d1210000 size 4000 align 14 gran 14 limit d1213fff flags 60000201 index 10
1406 12:47:15.602713 PCI: 00:15.0 child on link 0 I2C: 01:15
1407 12:47:15.612806 PCI: 00:15.0 resource base d121f000 size 1000 align 12 gran 12 limit d121ffff flags 60000201 index 10
1408 12:47:15.613354 I2C: 01:15
1409 12:47:15.619059 PCI: 00:15.1 child on link 0 I2C: 02:5d
1410 12:47:15.628785 PCI: 00:15.1 resource base d1220000 size 1000 align 12 gran 12 limit d1220fff flags 60000201 index 10
1411 12:47:15.629250 I2C: 02:5d
1412 12:47:15.632336 GENERIC: 0.0
1413 12:47:15.632892 PCI: 00:16.0
1414 12:47:15.642252 PCI: 00:16.0 resource base d1221000 size 1000 align 12 gran 12 limit d1221fff flags 60000201 index 10
1415 12:47:15.646352 PCI: 00:17.0
1416 12:47:15.655308 PCI: 00:17.0 resource base d121a000 size 2000 align 13 gran 13 limit d121bfff flags 60000200 index 10
1417 12:47:15.666268 PCI: 00:17.0 resource base d1228000 size 100 align 12 gran 8 limit d12280ff flags 60000200 index 14
1418 12:47:15.675359 PCI: 00:17.0 resource base 1c60 size 8 align 3 gran 3 limit 1c67 flags 60000100 index 18
1419 12:47:15.681887 PCI: 00:17.0 resource base 1c68 size 4 align 2 gran 2 limit 1c6b flags 60000100 index 1c
1420 12:47:15.692168 PCI: 00:17.0 resource base 1c40 size 20 align 5 gran 5 limit 1c5f flags 60000100 index 20
1421 12:47:15.701770 PCI: 00:17.0 resource base d1227000 size 800 align 12 gran 11 limit d12277ff flags 60000200 index 24
1422 12:47:15.708530 PCI: 00:19.0 child on link 0 I2C: 03:1a
1423 12:47:15.718446 PCI: 00:19.0 resource base d1222000 size 1000 align 12 gran 12 limit d1222fff flags 60000201 index 10
1424 12:47:15.719041 I2C: 03:1a
1425 12:47:15.721603 I2C: 03:38
1426 12:47:15.722160 I2C: 03:39
1427 12:47:15.725054 I2C: 03:3a
1428 12:47:15.725803 I2C: 03:3b
1429 12:47:15.728243 PCI: 00:1d.0 child on link 0 PCI: 01:00.0
1430 12:47:15.738375 PCI: 00:1d.0 resource base ef9f size 0 align 12 gran 12 limit ef9f flags 60080102 index 1c
1431 12:47:15.748246 PCI: 00:1d.0 resource base dfffffff size 0 align 20 gran 20 limit dfffffff flags 60081202 index 24
1432 12:47:15.758285 PCI: 00:1d.0 resource base d1000000 size 100000 align 20 gran 20 limit d10fffff flags 60080202 index 20
1433 12:47:15.761019 PCI: 01:00.0
1434 12:47:15.771351 PCI: 01:00.0 resource base d1000000 size 4000 align 14 gran 14 limit d1003fff flags 60000201 index 10
1435 12:47:15.774591 PCI: 00:1e.0
1436 12:47:15.784787 PCI: 00:1e.0 resource base fe032000 size 1000 align 12 gran 12 limit ffffffffffffffff flags c0000200 index 10
1437 12:47:15.794206 PCI: 00:1e.0 resource base d1223000 size 1000 align 12 gran 12 limit d1223fff flags 60000201 index 18
1438 12:47:15.797983 PCI: 00:1e.2 child on link 0 SPI: 00
1439 12:47:15.807837 PCI: 00:1e.2 resource base d1224000 size 1000 align 12 gran 12 limit d1224fff flags 60000201 index 10
1440 12:47:15.811220 SPI: 00
1441 12:47:15.814316 PCI: 00:1e.3 child on link 0 SPI: 01
1442 12:47:15.823969 PCI: 00:1e.3 resource base d1225000 size 1000 align 12 gran 12 limit d1225fff flags 60000201 index 10
1443 12:47:15.824591 SPI: 01
1444 12:47:15.831212 PCI: 00:1f.0 child on link 0 PNP: 0c09.0
1445 12:47:15.837113 PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0000100 index 0
1446 12:47:15.846716 PCI: 00:1f.0 resource base 1800 size 100 align 0 gran 0 limit 0 flags c0000100 index 20
1447 12:47:15.850502 PNP: 0c09.0
1448 12:47:15.856777 PNP: 0c09.0 resource base 800 size 1ff align 0 gran 0 limit 0 flags c0000100 index 0
1449 12:47:15.860348 PCI: 00:1f.3
1450 12:47:15.869803 PCI: 00:1f.3 resource base d1214000 size 4000 align 14 gran 14 limit d1217fff flags 60000201 index 10
1451 12:47:15.879855 PCI: 00:1f.3 resource base d1100000 size 100000 align 20 gran 20 limit d11fffff flags 60000201 index 20
1452 12:47:15.883426 PCI: 00:1f.4
1453 12:47:15.889626 PCI: 00:1f.4 resource base efa0 size 20 align 0 gran 0 limit efbf flags f0000100 index 20
1454 12:47:15.899551 PCI: 00:1f.4 resource base d1229000 size 100 align 12 gran 8 limit d12290ff flags 60000201 index 10
1455 12:47:15.902694 PCI: 00:1f.5
1456 12:47:15.912812 PCI: 00:1f.5 resource base d1226000 size 1000 align 12 gran 12 limit d1226fff flags 60000200 index 10
1457 12:47:15.915853 Done allocating resources.
1458 12:47:15.922711 BS: BS_DEV_RESOURCES times (ms): entry 0 run 30 exit 0
1459 12:47:15.922843 Enabling resources...
1460 12:47:15.929683 PCI: 00:00.0 subsystem <- 8086/9b61
1461 12:47:15.929790 PCI: 00:00.0 cmd <- 06
1462 12:47:15.932866 PCI: 00:02.0 subsystem <- 8086/9b41
1463 12:47:15.936356 PCI: 00:02.0 cmd <- 03
1464 12:47:15.939355 PCI: 00:08.0 cmd <- 06
1465 12:47:15.942557 PCI: 00:12.0 subsystem <- 8086/02f9
1466 12:47:15.945961 PCI: 00:12.0 cmd <- 02
1467 12:47:15.949686 PCI: 00:14.0 subsystem <- 8086/02ed
1468 12:47:15.953058 PCI: 00:14.0 cmd <- 02
1469 12:47:15.955685 PCI: 00:14.2 cmd <- 02
1470 12:47:15.959119 PCI: 00:14.3 subsystem <- 8086/02f0
1471 12:47:15.959196 PCI: 00:14.3 cmd <- 02
1472 12:47:15.966172 PCI: 00:15.0 subsystem <- 8086/02e8
1473 12:47:15.966287 PCI: 00:15.0 cmd <- 02
1474 12:47:15.969310 PCI: 00:15.1 subsystem <- 8086/02e9
1475 12:47:15.972741 PCI: 00:15.1 cmd <- 02
1476 12:47:15.975948 PCI: 00:16.0 subsystem <- 8086/02e0
1477 12:47:15.979163 PCI: 00:16.0 cmd <- 02
1478 12:47:15.982419 PCI: 00:17.0 subsystem <- 8086/02d3
1479 12:47:15.985822 PCI: 00:17.0 cmd <- 03
1480 12:47:15.989043 PCI: 00:19.0 subsystem <- 8086/02c5
1481 12:47:15.992587 PCI: 00:19.0 cmd <- 02
1482 12:47:15.996076 PCI: 00:1d.0 bridge ctrl <- 0013
1483 12:47:15.999500 PCI: 00:1d.0 subsystem <- 8086/02b0
1484 12:47:16.002899 PCI: 00:1d.0 cmd <- 06
1485 12:47:16.007012 PCI: 00:1e.0 subsystem <- 8086/02a8
1486 12:47:16.009105 PCI: 00:1e.0 cmd <- 06
1487 12:47:16.012557 PCI: 00:1e.2 subsystem <- 8086/02aa
1488 12:47:16.015720 PCI: 00:1e.2 cmd <- 06
1489 12:47:16.019054 PCI: 00:1e.3 subsystem <- 8086/02ab
1490 12:47:16.019136 PCI: 00:1e.3 cmd <- 02
1491 12:47:16.025762 PCI: 00:1f.0 subsystem <- 8086/0284
1492 12:47:16.025845 PCI: 00:1f.0 cmd <- 407
1493 12:47:16.029152 PCI: 00:1f.3 subsystem <- 8086/02c8
1494 12:47:16.032815 PCI: 00:1f.3 cmd <- 02
1495 12:47:16.035943 PCI: 00:1f.4 subsystem <- 8086/02a3
1496 12:47:16.039110 PCI: 00:1f.4 cmd <- 03
1497 12:47:16.042948 PCI: 00:1f.5 subsystem <- 8086/02a4
1498 12:47:16.046067 PCI: 00:1f.5 cmd <- 406
1499 12:47:16.054696 PCI: 01:00.0 cmd <- 02
1500 12:47:16.059911 done.
1501 12:47:16.072933 ME: Version: 14.0.39.1367
1502 12:47:16.079493 BS: BS_DEV_ENABLE times (ms): entry 0 run 17 exit 12
1503 12:47:16.082450 Initializing devices...
1504 12:47:16.082539 Root Device init ...
1505 12:47:16.088934 Chrome EC: Set SMI mask to 0x0000000000000000
1506 12:47:16.092166 Chrome EC: clear events_b mask to 0x0000000000000000
1507 12:47:16.099844 Chrome EC: Set S5 LAZY WAKE mask to 0x0000000000000006
1508 12:47:16.105803 Chrome EC: Set S3 LAZY WAKE mask to 0x0000000014001006
1509 12:47:16.112764 Chrome EC: Set S0iX LAZY WAKE mask to 0x0000000014081006
1510 12:47:16.115762 Chrome EC: Set WAKE mask to 0x0000000000000000
1511 12:47:16.119012 Root Device init finished in 35193 usecs
1512 12:47:16.122700 CPU_CLUSTER: 0 init ...
1513 12:47:16.129171 CPU_CLUSTER: 0 init finished in 2448 usecs
1514 12:47:16.133886 PCI: 00:00.0 init ...
1515 12:47:16.136605 CPU TDP: 15 Watts
1516 12:47:16.140023 CPU PL2 = 64 Watts
1517 12:47:16.143480 PCI: 00:00.0 init finished in 7078 usecs
1518 12:47:16.146782 PCI: 00:02.0 init ...
1519 12:47:16.149837 PCI: 00:02.0 init finished in 2246 usecs
1520 12:47:16.152887 PCI: 00:08.0 init ...
1521 12:47:16.156382 PCI: 00:08.0 init finished in 2255 usecs
1522 12:47:16.160003 PCI: 00:12.0 init ...
1523 12:47:16.163073 PCI: 00:12.0 init finished in 2244 usecs
1524 12:47:16.166588 PCI: 00:14.0 init ...
1525 12:47:16.169604 PCI: 00:14.0 init finished in 2254 usecs
1526 12:47:16.173068 PCI: 00:14.2 init ...
1527 12:47:16.176525 PCI: 00:14.2 init finished in 2254 usecs
1528 12:47:16.179580 PCI: 00:14.3 init ...
1529 12:47:16.183063 PCI: 00:14.3 init finished in 2271 usecs
1530 12:47:16.186435 PCI: 00:15.0 init ...
1531 12:47:16.190168 DW I2C bus 0 at 0xd121f000 (400 KHz)
1532 12:47:16.193644 PCI: 00:15.0 init finished in 5980 usecs
1533 12:47:16.195969 PCI: 00:15.1 init ...
1534 12:47:16.199525 DW I2C bus 1 at 0xd1220000 (400 KHz)
1535 12:47:16.205906 PCI: 00:15.1 init finished in 5979 usecs
1536 12:47:16.205990 PCI: 00:16.0 init ...
1537 12:47:16.212649 PCI: 00:16.0 init finished in 2246 usecs
1538 12:47:16.215724 PCI: 00:19.0 init ...
1539 12:47:16.219293 DW I2C bus 4 at 0xd1222000 (400 KHz)
1540 12:47:16.222665 PCI: 00:19.0 init finished in 5980 usecs
1541 12:47:16.225904 PCI: 00:1d.0 init ...
1542 12:47:16.229218 Initializing PCH PCIe bridge.
1543 12:47:16.232501 PCI: 00:1d.0 init finished in 5288 usecs
1544 12:47:16.235981 PCI: 00:1f.0 init ...
1545 12:47:16.239135 IOAPIC: Initializing IOAPIC at 0xfec00000
1546 12:47:16.246400 IOAPIC: Bootstrap Processor Local APIC = 0x00
1547 12:47:16.246483 IOAPIC: ID = 0x02
1548 12:47:16.249408 IOAPIC: Dumping registers
1549 12:47:16.252383 reg 0x0000: 0x02000000
1550 12:47:16.255725 reg 0x0001: 0x00770020
1551 12:47:16.255806 reg 0x0002: 0x00000000
1552 12:47:16.262406 PCI: 00:1f.0 init finished in 23563 usecs
1553 12:47:16.265698 PCI: 00:1f.4 init ...
1554 12:47:16.269000 PCI: 00:1f.4 init finished in 2264 usecs
1555 12:47:16.279568 PCI: 01:00.0 init ...
1556 12:47:16.282706 PCI: 01:00.0 init finished in 2245 usecs
1557 12:47:16.286837 PNP: 0c09.0 init ...
1558 12:47:16.290129 Google Chrome EC uptime: 11.089 seconds
1559 12:47:16.297206 Google Chrome AP resets since EC boot: 0
1560 12:47:16.300042 Google Chrome most recent AP reset causes:
1561 12:47:16.306675 Google Chrome EC reset flags at last EC boot: reset-pin
1562 12:47:16.310198 PNP: 0c09.0 init finished in 20606 usecs
1563 12:47:16.313336 Devices initialized
1564 12:47:16.316905 Show all devs... After init.
1565 12:47:16.316989 Root Device: enabled 1
1566 12:47:16.320140 CPU_CLUSTER: 0: enabled 1
1567 12:47:16.323326 DOMAIN: 0000: enabled 1
1568 12:47:16.323409 APIC: 00: enabled 1
1569 12:47:16.326586 PCI: 00:00.0: enabled 1
1570 12:47:16.330357 PCI: 00:02.0: enabled 1
1571 12:47:16.333260 PCI: 00:04.0: enabled 0
1572 12:47:16.333346 PCI: 00:05.0: enabled 0
1573 12:47:16.336758 PCI: 00:12.0: enabled 1
1574 12:47:16.339864 PCI: 00:12.5: enabled 0
1575 12:47:16.343203 PCI: 00:12.6: enabled 0
1576 12:47:16.343302 PCI: 00:14.0: enabled 1
1577 12:47:16.346626 PCI: 00:14.1: enabled 0
1578 12:47:16.349961 PCI: 00:14.3: enabled 1
1579 12:47:16.350120 PCI: 00:14.5: enabled 0
1580 12:47:16.353475 PCI: 00:15.0: enabled 1
1581 12:47:16.357141 PCI: 00:15.1: enabled 1
1582 12:47:16.360398 PCI: 00:15.2: enabled 0
1583 12:47:16.360543 PCI: 00:15.3: enabled 0
1584 12:47:16.363279 PCI: 00:16.0: enabled 1
1585 12:47:16.367009 PCI: 00:16.1: enabled 0
1586 12:47:16.369951 PCI: 00:16.2: enabled 0
1587 12:47:16.370209 PCI: 00:16.3: enabled 0
1588 12:47:16.372901 PCI: 00:16.4: enabled 0
1589 12:47:16.376479 PCI: 00:16.5: enabled 0
1590 12:47:16.379693 PCI: 00:17.0: enabled 1
1591 12:47:16.379776 PCI: 00:19.0: enabled 1
1592 12:47:16.383084 PCI: 00:19.1: enabled 0
1593 12:47:16.386221 PCI: 00:19.2: enabled 0
1594 12:47:16.386304 PCI: 00:1a.0: enabled 0
1595 12:47:16.389681 PCI: 00:1c.0: enabled 0
1596 12:47:16.393193 PCI: 00:1c.1: enabled 0
1597 12:47:16.396316 PCI: 00:1c.2: enabled 0
1598 12:47:16.396410 PCI: 00:1c.3: enabled 0
1599 12:47:16.399883 PCI: 00:1c.4: enabled 0
1600 12:47:16.403147 PCI: 00:1c.5: enabled 0
1601 12:47:16.406926 PCI: 00:1c.6: enabled 0
1602 12:47:16.407038 PCI: 00:1c.7: enabled 0
1603 12:47:16.409823 PCI: 00:1d.0: enabled 1
1604 12:47:16.412691 PCI: 00:1d.1: enabled 0
1605 12:47:16.417158 PCI: 00:1d.2: enabled 0
1606 12:47:16.417293 PCI: 00:1d.3: enabled 0
1607 12:47:16.419579 PCI: 00:1d.4: enabled 0
1608 12:47:16.422700 PCI: 00:1d.5: enabled 0
1609 12:47:16.426612 PCI: 00:1e.0: enabled 1
1610 12:47:16.426891 PCI: 00:1e.1: enabled 0
1611 12:47:16.430082 PCI: 00:1e.2: enabled 1
1612 12:47:16.433364 PCI: 00:1e.3: enabled 1
1613 12:47:16.433653 PCI: 00:1f.0: enabled 1
1614 12:47:16.436430 PCI: 00:1f.1: enabled 0
1615 12:47:16.440168 PCI: 00:1f.2: enabled 0
1616 12:47:16.443714 PCI: 00:1f.3: enabled 1
1617 12:47:16.444152 PCI: 00:1f.4: enabled 1
1618 12:47:16.446348 PCI: 00:1f.5: enabled 1
1619 12:47:16.450078 PCI: 00:1f.6: enabled 0
1620 12:47:16.452846 USB0 port 0: enabled 1
1621 12:47:16.453319 I2C: 01:15: enabled 1
1622 12:47:16.456343 I2C: 02:5d: enabled 1
1623 12:47:16.459450 GENERIC: 0.0: enabled 1
1624 12:47:16.460152 I2C: 03:1a: enabled 1
1625 12:47:16.463238 I2C: 03:38: enabled 1
1626 12:47:16.466937 I2C: 03:39: enabled 1
1627 12:47:16.467502 I2C: 03:3a: enabled 1
1628 12:47:16.469681 I2C: 03:3b: enabled 1
1629 12:47:16.472734 PCI: 00:00.0: enabled 1
1630 12:47:16.473188 SPI: 00: enabled 1
1631 12:47:16.476773 SPI: 01: enabled 1
1632 12:47:16.479710 PNP: 0c09.0: enabled 1
1633 12:47:16.480359 USB2 port 0: enabled 1
1634 12:47:16.483019 USB2 port 1: enabled 1
1635 12:47:16.486418 USB2 port 2: enabled 0
1636 12:47:16.486973 USB2 port 3: enabled 0
1637 12:47:16.489751 USB2 port 5: enabled 0
1638 12:47:16.493499 USB2 port 6: enabled 1
1639 12:47:16.496400 USB2 port 9: enabled 1
1640 12:47:16.496953 USB3 port 0: enabled 1
1641 12:47:16.499484 USB3 port 1: enabled 1
1642 12:47:16.502795 USB3 port 2: enabled 1
1643 12:47:16.503348 USB3 port 3: enabled 1
1644 12:47:16.506110 USB3 port 4: enabled 0
1645 12:47:16.508965 APIC: 04: enabled 1
1646 12:47:16.509425 APIC: 01: enabled 1
1647 12:47:16.512386 APIC: 05: enabled 1
1648 12:47:16.516683 APIC: 06: enabled 1
1649 12:47:16.517258 APIC: 02: enabled 1
1650 12:47:16.519070 APIC: 03: enabled 1
1651 12:47:16.519528 APIC: 07: enabled 1
1652 12:47:16.522551 PCI: 00:08.0: enabled 1
1653 12:47:16.525795 PCI: 00:14.2: enabled 1
1654 12:47:16.529313 PCI: 01:00.0: enabled 1
1655 12:47:16.533289 Disabling ACPI via APMC:
1656 12:47:16.535955 done.
1657 12:47:16.539828 FMAP: area RW_ELOG found @ af0000 (16384 bytes)
1658 12:47:16.542559 ELOG: NV offset 0xaf0000 size 0x4000
1659 12:47:16.549360 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
1660 12:47:16.555895 ELOG: Event(17) added with size 13 at 2024-01-03 12:47:16 UTC
1661 12:47:16.562993 ELOG: Event(92) added with size 9 at 2024-01-03 12:47:16 UTC
1662 12:47:16.569407 ELOG: Event(93) added with size 9 at 2024-01-03 12:47:16 UTC
1663 12:47:16.576203 ELOG: Event(9A) added with size 9 at 2024-01-03 12:47:16 UTC
1664 12:47:16.582828 ELOG: Event(9E) added with size 10 at 2024-01-03 12:47:16 UTC
1665 12:47:16.589329 ELOG: Event(9F) added with size 14 at 2024-01-03 12:47:16 UTC
1666 12:47:16.592417 BS: BS_DEV_INIT times (ms): entry 0 run 27 exit 6
1667 12:47:16.599813 ELOG: Event(A1) added with size 10 at 2024-01-03 12:47:16 UTC
1668 12:47:16.609357 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
1669 12:47:16.616518 ELOG: Event(A0) added with size 9 at 2024-01-03 12:47:16 UTC
1670 12:47:16.619610 elog_add_boot_reason: Logged dev mode boot
1671 12:47:16.620114 Finalize devices...
1672 12:47:16.623508 PCI: 00:17.0 final
1673 12:47:16.626423 Devices finalized
1674 12:47:16.629580 FMAP: area RW_NVRAM found @ afa000 (24576 bytes)
1675 12:47:16.635832 BS: BS_POST_DEVICE times (ms): entry 1 run 0 exit 0
1676 12:47:16.639983 ME: HFSTS1 : 0x90000245
1677 12:47:16.642751 ME: HFSTS2 : 0x3B850126
1678 12:47:16.649248 ME: HFSTS3 : 0x00000020
1679 12:47:16.652448 ME: HFSTS4 : 0x00004800
1680 12:47:16.656530 ME: HFSTS5 : 0x00000000
1681 12:47:16.659162 ME: HFSTS6 : 0x40400006
1682 12:47:16.662407 ME: Manufacturing Mode : NO
1683 12:47:16.666225 ME: FW Partition Table : OK
1684 12:47:16.669229 ME: Bringup Loader Failure : NO
1685 12:47:16.672553 ME: Firmware Init Complete : YES
1686 12:47:16.675697 ME: Boot Options Present : NO
1687 12:47:16.678859 ME: Update In Progress : NO
1688 12:47:16.682670 ME: D0i3 Support : YES
1689 12:47:16.685372 ME: Low Power State Enabled : NO
1690 12:47:16.688780 ME: CPU Replaced : NO
1691 12:47:16.692247 ME: CPU Replacement Valid : YES
1692 12:47:16.695911 ME: Current Working State : 5
1693 12:47:16.698539 ME: Current Operation State : 1
1694 12:47:16.702254 ME: Current Operation Mode : 0
1695 12:47:16.705354 ME: Error Code : 0
1696 12:47:16.709014 ME: CPU Debug Disabled : YES
1697 12:47:16.712171 ME: TXT Support : NO
1698 12:47:16.718646 BS: BS_OS_RESUME_CHECK times (ms): entry 0 run 0 exit 0
1699 12:47:16.725133 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
1700 12:47:16.725719 CBFS @ c08000 size 3f8000
1701 12:47:16.731804 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
1702 12:47:16.735654 CBFS: Locating 'fallback/dsdt.aml'
1703 12:47:16.738255 CBFS: Found @ offset 10bb80 size 3fa5
1704 12:47:16.744715 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
1705 12:47:16.748458 CBFS @ c08000 size 3f8000
1706 12:47:16.755206 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
1707 12:47:16.758450 CBFS: Locating 'fallback/slic'
1708 12:47:16.761196 CBFS: 'fallback/slic' not found.
1709 12:47:16.764947 ACPI: Writing ACPI tables at 99b3e000.
1710 12:47:16.767953 ACPI: * FACS
1711 12:47:16.768567 ACPI: * DSDT
1712 12:47:16.771563 Ramoops buffer: 0x100000@0x99a3d000.
1713 12:47:16.778138 FMAP: area RO_VPD found @ c00000 (16384 bytes)
1714 12:47:16.781626 FMAP: area RW_VPD found @ af8000 (8192 bytes)
1715 12:47:16.785031 Google Chrome EC: version:
1716 12:47:16.788124 ro: helios_v2.0.2659-56403530b
1717 12:47:16.791323 rw: helios_v2.0.2849-c41de27e7d
1718 12:47:16.794594 running image: 1
1719 12:47:16.797488 ACPI: * FADT
1720 12:47:16.797968 SCI is IRQ9
1721 12:47:16.800872 ACPI: added table 1/32, length now 40
1722 12:47:16.804488 ACPI: * SSDT
1723 12:47:16.807855 Found 1 CPU(s) with 8 core(s) each.
1724 12:47:16.811292 Error: Could not locate 'wifi_sar' in VPD.
1725 12:47:16.814461 Checking CBFS for default SAR values
1726 12:47:16.820699 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
1727 12:47:16.824364 CBFS @ c08000 size 3f8000
1728 12:47:16.831147 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
1729 12:47:16.834065 CBFS: Locating 'wifi_sar_defaults.hex'
1730 12:47:16.837254 CBFS: Found @ offset 5fac0 size 77
1731 12:47:16.841025 \_SB.PCI0.WFA3: Intel WiFi PCI: 00:14.3
1732 12:47:16.844237 \_SB.PCI0.I2C0.D015: ELAN Touchpad at I2C: 01:15
1733 12:47:16.851014 \_SB.PCI0.I2C1.H05D: Goodix Touchscreen at I2C: 02:5d
1734 12:47:16.857584 \_SB.PCI0.I2C4.RT58: Realtek RT5682 at I2C: 03:1a
1735 12:47:16.860908 failed to find key in VPD: dsm_calib_r0_0
1736 12:47:16.870547 Failed to get dsm_calib parameters from VPD with key dsm_calib_r0_0 and dsm_calib_temp_0
1737 12:47:16.873751 \_SB.PCI0.I2C4.RTWL: Realtek RT1011 Codec address 038h
1738 12:47:16.877041 failed to find key in VPD: dsm_calib_r0_1
1739 12:47:16.887684 Failed to get dsm_calib parameters from VPD with key dsm_calib_r0_1 and dsm_calib_temp_0
1740 12:47:16.894491 \_SB.PCI0.I2C4.RTWR: Realtek RT1011 Codec address 039h
1741 12:47:16.897080 failed to find key in VPD: dsm_calib_r0_2
1742 12:47:16.906994 Failed to get dsm_calib parameters from VPD with key dsm_calib_r0_2 and dsm_calib_temp_0
1743 12:47:16.910286 \_SB.PCI0.I2C4.RTTL: Realtek RT1011 Codec address 03ah
1744 12:47:16.917421 failed to find key in VPD: dsm_calib_r0_3
1745 12:47:16.923316 Failed to get dsm_calib parameters from VPD with key dsm_calib_r0_3 and dsm_calib_temp_0
1746 12:47:16.929791 \_SB.PCI0.I2C4.RTTR: Realtek RT1011 Codec address 03bh
1747 12:47:16.933481 \_SB.PCI0.SPI0.S001: SPI Device at SPI: 00
1748 12:47:16.936567 \_SB.PCI0.SPI1.CRFP: SPI Device at SPI: 01
1749 12:47:16.941217 EC returned error result code 1
1750 12:47:16.944167 EC returned error result code 1
1751 12:47:16.948503 EC returned error result code 1
1752 12:47:16.955433 PS2K: Bad resp from EC. Vivaldi disabled!
1753 12:47:16.958415 \_SB.PCI0.XHCI.RHUB.HS01: Left Type-C Port at USB2 port 0
1754 12:47:16.964787 \_SB.PCI0.XHCI.RHUB.HS02: Right Type-C Port 1 at USB2 port 1
1755 12:47:16.971253 \_SB.PCI0.XHCI.RHUB.HS07: Camera at USB2 port 6
1756 12:47:16.975148 \_SB.PCI0.XHCI.RHUB.HS10: Bluetooth at USB2 port 9
1757 12:47:16.981064 \_SB.PCI0.XHCI.RHUB.SS01: Left Type-C Port at USB3 port 0
1758 12:47:16.987668 \_SB.PCI0.XHCI.RHUB.SS02: Right Type-C Port 1 at USB3 port 1
1759 12:47:16.994413 \_SB.PCI0.XHCI.RHUB.SS03: Left Type-A Port at USB3 port 2
1760 12:47:16.997796 \_SB.PCI0.XHCI.RHUB.SS04: Right Type-A Port 1 at USB3 port 3
1761 12:47:17.001028 ACPI: added table 2/32, length now 44
1762 12:47:17.005203 ACPI: * MCFG
1763 12:47:17.007991 ACPI: added table 3/32, length now 48
1764 12:47:17.010994 ACPI: * TPM2
1765 12:47:17.014445 TPM2 log created at 99a2d000
1766 12:47:17.017405 ACPI: added table 4/32, length now 52
1767 12:47:17.017987 ACPI: * MADT
1768 12:47:17.021414 SCI is IRQ9
1769 12:47:17.024759 ACPI: added table 5/32, length now 56
1770 12:47:17.025327 current = 99b43ac0
1771 12:47:17.027554 ACPI: * DMAR
1772 12:47:17.031477 ACPI: added table 6/32, length now 60
1773 12:47:17.034454 ACPI: * IGD OpRegion
1774 12:47:17.034914 GMA: Found VBT in CBFS
1775 12:47:17.037448 GMA: Found valid VBT in CBFS
1776 12:47:17.040632 ACPI: added table 7/32, length now 64
1777 12:47:17.043851 ACPI: * HPET
1778 12:47:17.047347 ACPI: added table 8/32, length now 68
1779 12:47:17.047806 ACPI: done.
1780 12:47:17.050787 ACPI tables: 31744 bytes.
1781 12:47:17.054811 smbios_write_tables: 99a2c000
1782 12:47:17.057609 EC returned error result code 3
1783 12:47:17.060843 Couldn't obtain OEM name from CBI
1784 12:47:17.064340 Create SMBIOS type 17
1785 12:47:17.067414 PCI: 00:00.0 (Intel Cannonlake)
1786 12:47:17.070625 PCI: 00:14.3 (Intel WiFi)
1787 12:47:17.074046 SMBIOS tables: 939 bytes.
1788 12:47:17.077354 Writing table forward entry at 0x00000500
1789 12:47:17.083955 Wrote coreboot table at: 00000500, 0x10 bytes, checksum 4628
1790 12:47:17.087694 Writing coreboot table at 0x99b62000
1791 12:47:17.094386 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
1792 12:47:17.097287 1. 0000000000001000-000000000009ffff: RAM
1793 12:47:17.100830 2. 00000000000a0000-00000000000fffff: RESERVED
1794 12:47:17.107764 3. 0000000000100000-0000000099a2bfff: RAM
1795 12:47:17.110724 4. 0000000099a2c000-0000000099baffff: CONFIGURATION TABLES
1796 12:47:17.117364 5. 0000000099bb0000-0000000099c0afff: RAMSTAGE
1797 12:47:17.124410 6. 0000000099c0b000-0000000099ffffff: CONFIGURATION TABLES
1798 12:47:17.127748 7. 000000009a000000-000000009f7fffff: RESERVED
1799 12:47:17.134064 8. 00000000e0000000-00000000efffffff: RESERVED
1800 12:47:17.136949 9. 00000000fc000000-00000000fc000fff: RESERVED
1801 12:47:17.140992 10. 00000000fe000000-00000000fe00ffff: RESERVED
1802 12:47:17.147643 11. 00000000fed10000-00000000fed17fff: RESERVED
1803 12:47:17.151271 12. 00000000fed80000-00000000fed83fff: RESERVED
1804 12:47:17.156807 13. 00000000fed90000-00000000fed91fff: RESERVED
1805 12:47:17.160320 14. 00000000feda0000-00000000feda1fff: RESERVED
1806 12:47:17.163372 15. 0000000100000000-000000045e7fffff: RAM
1807 12:47:17.170075 Graphics framebuffer located at 0xc0000000
1808 12:47:17.173713 Passing 5 GPIOs to payload:
1809 12:47:17.176983 NAME | PORT | POLARITY | VALUE
1810 12:47:17.183502 write protect | undefined | high | low
1811 12:47:17.187000 lid | undefined | high | high
1812 12:47:17.193472 power | undefined | high | low
1813 12:47:17.200272 oprom | undefined | high | low
1814 12:47:17.203594 EC in RW | 0x000000cb | high | low
1815 12:47:17.206782 Board ID: 4
1816 12:47:17.210340 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
1817 12:47:17.213319 CBFS @ c08000 size 3f8000
1818 12:47:17.220253 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
1819 12:47:17.223420 Wrote coreboot table at: 99b62000, 0x5bc bytes, checksum 6baa
1820 12:47:17.227718 coreboot table: 1492 bytes.
1821 12:47:17.229832 IMD ROOT 0. 99fff000 00001000
1822 12:47:17.232727 IMD SMALL 1. 99ffe000 00001000
1823 12:47:17.236516 FSP MEMORY 2. 99c4e000 003b0000
1824 12:47:17.240239 CONSOLE 3. 99c2e000 00020000
1825 12:47:17.243120 FMAP 4. 99c2d000 0000054e
1826 12:47:17.246447 TIME STAMP 5. 99c2c000 00000910
1827 12:47:17.250027 VBOOT WORK 6. 99c18000 00014000
1828 12:47:17.253563 MRC DATA 7. 99c16000 00001958
1829 12:47:17.256305 ROMSTG STCK 8. 99c15000 00001000
1830 12:47:17.259670 AFTER CAR 9. 99c0b000 0000a000
1831 12:47:17.262854 RAMSTAGE 10. 99baf000 0005c000
1832 12:47:17.266380 REFCODE 11. 99b7a000 00035000
1833 12:47:17.269271 SMM BACKUP 12. 99b6a000 00010000
1834 12:47:17.272887 COREBOOT 13. 99b62000 00008000
1835 12:47:17.276269 ACPI 14. 99b3e000 00024000
1836 12:47:17.279090 ACPI GNVS 15. 99b3d000 00001000
1837 12:47:17.282771 RAMOOPS 16. 99a3d000 00100000
1838 12:47:17.286088 TPM2 TCGLOG17. 99a2d000 00010000
1839 12:47:17.289159 SMBIOS 18. 99a2c000 00000800
1840 12:47:17.292674 IMD small region:
1841 12:47:17.296381 IMD ROOT 0. 99ffec00 00000400
1842 12:47:17.299031 FSP RUNTIME 1. 99ffebe0 00000004
1843 12:47:17.302746 EC HOSTEVENT 2. 99ffebc0 00000008
1844 12:47:17.306053 POWER STATE 3. 99ffeb80 00000040
1845 12:47:17.309437 ROMSTAGE 4. 99ffeb60 00000004
1846 12:47:17.312684 MEM INFO 5. 99ffe9a0 000001b9
1847 12:47:17.316655 VPD 6. 99ffe920 0000006c
1848 12:47:17.319692 MTRR: Physical address space:
1849 12:47:17.326121 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
1850 12:47:17.332715 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
1851 12:47:17.339315 0x00000000000c0000 - 0x000000009b000000 size 0x9af40000 type 6
1852 12:47:17.345750 0x000000009b000000 - 0x00000000c0000000 size 0x25000000 type 0
1853 12:47:17.352655 0x00000000c0000000 - 0x00000000d0000000 size 0x10000000 type 1
1854 12:47:17.358943 0x00000000d0000000 - 0x0000000100000000 size 0x30000000 type 0
1855 12:47:17.365671 0x0000000100000000 - 0x000000045e800000 size 0x35e800000 type 6
1856 12:47:17.368908 MTRR: Fixed MSR 0x250 0x0606060606060606
1857 12:47:17.372238 MTRR: Fixed MSR 0x258 0x0606060606060606
1858 12:47:17.375939 MTRR: Fixed MSR 0x259 0x0000000000000000
1859 12:47:17.383796 MTRR: Fixed MSR 0x268 0x0606060606060606
1860 12:47:17.386050 MTRR: Fixed MSR 0x269 0x0606060606060606
1861 12:47:17.388954 MTRR: Fixed MSR 0x26a 0x0606060606060606
1862 12:47:17.392669 MTRR: Fixed MSR 0x26b 0x0606060606060606
1863 12:47:17.395245 MTRR: Fixed MSR 0x26c 0x0606060606060606
1864 12:47:17.401750 MTRR: Fixed MSR 0x26d 0x0606060606060606
1865 12:47:17.404989 MTRR: Fixed MSR 0x26e 0x0606060606060606
1866 12:47:17.408786 MTRR: Fixed MSR 0x26f 0x0606060606060606
1867 12:47:17.412127 call enable_fixed_mtrr()
1868 12:47:17.415304 CPU physical address size: 39 bits
1869 12:47:17.422079 MTRR: default type WB/UC MTRR counts: 6/8.
1870 12:47:17.425024 MTRR: WB selected as default type.
1871 12:47:17.431560 MTRR: 0 base 0x000000009b000000 mask 0x0000007fff000000 type 0
1872 12:47:17.435029 MTRR: 1 base 0x000000009c000000 mask 0x0000007ffc000000 type 0
1873 12:47:17.443717 MTRR: 2 base 0x00000000a0000000 mask 0x0000007fe0000000 type 0
1874 12:47:17.448008 MTRR: 3 base 0x00000000c0000000 mask 0x0000007ff0000000 type 1
1875 12:47:17.454960 MTRR: 4 base 0x00000000d0000000 mask 0x0000007ff0000000 type 0
1876 12:47:17.461465 MTRR: 5 base 0x00000000e0000000 mask 0x0000007fe0000000 type 0
1877 12:47:17.464533 MTRR: Fixed MSR 0x250 0x0606060606060606
1878 12:47:17.471338 MTRR: Fixed MSR 0x258 0x0606060606060606
1879 12:47:17.474690 MTRR: Fixed MSR 0x259 0x0000000000000000
1880 12:47:17.478402 MTRR: Fixed MSR 0x268 0x0606060606060606
1881 12:47:17.481512 MTRR: Fixed MSR 0x269 0x0606060606060606
1882 12:47:17.488260 MTRR: Fixed MSR 0x26a 0x0606060606060606
1883 12:47:17.491160 MTRR: Fixed MSR 0x26b 0x0606060606060606
1884 12:47:17.494311 MTRR: Fixed MSR 0x26c 0x0606060606060606
1885 12:47:17.497956 MTRR: Fixed MSR 0x26d 0x0606060606060606
1886 12:47:17.504369 MTRR: Fixed MSR 0x26e 0x0606060606060606
1887 12:47:17.507709 MTRR: Fixed MSR 0x26f 0x0606060606060606
1888 12:47:17.508217
1889 12:47:17.508588 MTRR check
1890 12:47:17.511035 Fixed MTRRs : Enabled
1891 12:47:17.514689 Variable MTRRs: Enabled
1892 12:47:17.515247
1893 12:47:17.517947 call enable_fixed_mtrr()
1894 12:47:17.521416 BS: BS_WRITE_TABLES times (ms): entry 0 run 9 exit 2
1895 12:47:17.524204 CPU physical address size: 39 bits
1896 12:47:17.531187 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
1897 12:47:17.534845 MTRR: Fixed MSR 0x250 0x0606060606060606
1898 12:47:17.538482 MTRR: Fixed MSR 0x258 0x0606060606060606
1899 12:47:17.544633 MTRR: Fixed MSR 0x259 0x0000000000000000
1900 12:47:17.547890 MTRR: Fixed MSR 0x268 0x0606060606060606
1901 12:47:17.551285 MTRR: Fixed MSR 0x269 0x0606060606060606
1902 12:47:17.554891 MTRR: Fixed MSR 0x26a 0x0606060606060606
1903 12:47:17.561266 MTRR: Fixed MSR 0x26b 0x0606060606060606
1904 12:47:17.564594 MTRR: Fixed MSR 0x26c 0x0606060606060606
1905 12:47:17.567633 MTRR: Fixed MSR 0x26d 0x0606060606060606
1906 12:47:17.571184 MTRR: Fixed MSR 0x26e 0x0606060606060606
1907 12:47:17.574102 MTRR: Fixed MSR 0x26f 0x0606060606060606
1908 12:47:17.580881 MTRR: Fixed MSR 0x250 0x0606060606060606
1909 12:47:17.584353 call enable_fixed_mtrr()
1910 12:47:17.587362 MTRR: Fixed MSR 0x250 0x0606060606060606
1911 12:47:17.590627 MTRR: Fixed MSR 0x258 0x0606060606060606
1912 12:47:17.594784 MTRR: Fixed MSR 0x259 0x0000000000000000
1913 12:47:17.600673 MTRR: Fixed MSR 0x268 0x0606060606060606
1914 12:47:17.604320 MTRR: Fixed MSR 0x269 0x0606060606060606
1915 12:47:17.607588 MTRR: Fixed MSR 0x26a 0x0606060606060606
1916 12:47:17.610640 MTRR: Fixed MSR 0x26b 0x0606060606060606
1917 12:47:17.613854 MTRR: Fixed MSR 0x26c 0x0606060606060606
1918 12:47:17.620507 MTRR: Fixed MSR 0x26d 0x0606060606060606
1919 12:47:17.624025 MTRR: Fixed MSR 0x26e 0x0606060606060606
1920 12:47:17.627552 MTRR: Fixed MSR 0x26f 0x0606060606060606
1921 12:47:17.633595 MTRR: Fixed MSR 0x250 0x0606060606060606
1922 12:47:17.634183 call enable_fixed_mtrr()
1923 12:47:17.640266 MTRR: Fixed MSR 0x258 0x0606060606060606
1924 12:47:17.644229 MTRR: Fixed MSR 0x259 0x0000000000000000
1925 12:47:17.647012 MTRR: Fixed MSR 0x268 0x0606060606060606
1926 12:47:17.650302 MTRR: Fixed MSR 0x269 0x0606060606060606
1927 12:47:17.653542 MTRR: Fixed MSR 0x26a 0x0606060606060606
1928 12:47:17.660261 MTRR: Fixed MSR 0x26b 0x0606060606060606
1929 12:47:17.663198 MTRR: Fixed MSR 0x26c 0x0606060606060606
1930 12:47:17.666844 MTRR: Fixed MSR 0x26d 0x0606060606060606
1931 12:47:17.670490 MTRR: Fixed MSR 0x26e 0x0606060606060606
1932 12:47:17.676693 MTRR: Fixed MSR 0x26f 0x0606060606060606
1933 12:47:17.680858 CPU physical address size: 39 bits
1934 12:47:17.683608 call enable_fixed_mtrr()
1935 12:47:17.686813 MTRR: Fixed MSR 0x250 0x0606060606060606
1936 12:47:17.690092 MTRR: Fixed MSR 0x250 0x0606060606060606
1937 12:47:17.693491 MTRR: Fixed MSR 0x258 0x0606060606060606
1938 12:47:17.700170 MTRR: Fixed MSR 0x259 0x0000000000000000
1939 12:47:17.703421 MTRR: Fixed MSR 0x268 0x0606060606060606
1940 12:47:17.706451 MTRR: Fixed MSR 0x269 0x0606060606060606
1941 12:47:17.709944 MTRR: Fixed MSR 0x26a 0x0606060606060606
1942 12:47:17.716557 MTRR: Fixed MSR 0x26b 0x0606060606060606
1943 12:47:17.719906 MTRR: Fixed MSR 0x26c 0x0606060606060606
1944 12:47:17.723443 MTRR: Fixed MSR 0x26d 0x0606060606060606
1945 12:47:17.727036 MTRR: Fixed MSR 0x26e 0x0606060606060606
1946 12:47:17.730176 MTRR: Fixed MSR 0x26f 0x0606060606060606
1947 12:47:17.736772 MTRR: Fixed MSR 0x258 0x0606060606060606
1948 12:47:17.739801 MTRR: Fixed MSR 0x259 0x0000000000000000
1949 12:47:17.742915 MTRR: Fixed MSR 0x268 0x0606060606060606
1950 12:47:17.749784 MTRR: Fixed MSR 0x269 0x0606060606060606
1951 12:47:17.752966 MTRR: Fixed MSR 0x26a 0x0606060606060606
1952 12:47:17.756176 MTRR: Fixed MSR 0x26b 0x0606060606060606
1953 12:47:17.759959 MTRR: Fixed MSR 0x26c 0x0606060606060606
1954 12:47:17.763428 MTRR: Fixed MSR 0x26d 0x0606060606060606
1955 12:47:17.769253 MTRR: Fixed MSR 0x26e 0x0606060606060606
1956 12:47:17.772563 MTRR: Fixed MSR 0x26f 0x0606060606060606
1957 12:47:17.775932 call enable_fixed_mtrr()
1958 12:47:17.779649 call enable_fixed_mtrr()
1959 12:47:17.782367 CPU physical address size: 39 bits
1960 12:47:17.786004 CPU physical address size: 39 bits
1961 12:47:17.789092 CBFS @ c08000 size 3f8000
1962 12:47:17.792226 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
1963 12:47:17.796254 CBFS: Locating 'fallback/payload'
1964 12:47:17.799486 CPU physical address size: 39 bits
1965 12:47:17.806123 MTRR: Fixed MSR 0x258 0x0606060606060606
1966 12:47:17.809463 MTRR: Fixed MSR 0x259 0x0000000000000000
1967 12:47:17.812601 MTRR: Fixed MSR 0x268 0x0606060606060606
1968 12:47:17.818958 MTRR: Fixed MSR 0x269 0x0606060606060606
1969 12:47:17.822379 MTRR: Fixed MSR 0x26a 0x0606060606060606
1970 12:47:17.825714 MTRR: Fixed MSR 0x26b 0x0606060606060606
1971 12:47:17.829638 MTRR: Fixed MSR 0x26c 0x0606060606060606
1972 12:47:17.832180 MTRR: Fixed MSR 0x26d 0x0606060606060606
1973 12:47:17.838740 MTRR: Fixed MSR 0x26e 0x0606060606060606
1974 12:47:17.842712 MTRR: Fixed MSR 0x26f 0x0606060606060606
1975 12:47:17.845321 CPU physical address size: 39 bits
1976 12:47:17.849037 call enable_fixed_mtrr()
1977 12:47:17.852205 CBFS: Found @ offset 1c96c0 size 3f798
1978 12:47:17.855528 CPU physical address size: 39 bits
1979 12:47:17.858861 Checking segment from ROM address 0xffdd16f8
1980 12:47:17.865233 Checking segment from ROM address 0xffdd1714
1981 12:47:17.868935 Loading segment from ROM address 0xffdd16f8
1982 12:47:17.871968 code (compression=0)
1983 12:47:17.878933 New segment dstaddr 0x30000000 memsize 0x657430 srcaddr 0xffdd1730 filesize 0x3f760
1984 12:47:17.888176 Loading Segment: addr: 0x30000000 memsz: 0x0000000000657430 filesz: 0x000000000003f760
1985 12:47:17.891413 it's not compressed!
1986 12:47:17.982671 [ 0x30000000, 3003f760, 0x30657430) <- ffdd1730
1987 12:47:17.990035 Clearing Segment: addr: 0x000000003003f760 memsz: 0x0000000000617cd0
1988 12:47:17.992675 Loading segment from ROM address 0xffdd1714
1989 12:47:17.995443 Entry Point 0x30000000
1990 12:47:17.998721 Loaded segments
1991 12:47:18.004715 Finalizing chipset.
1992 12:47:18.007798 Finalizing SMM.
1993 12:47:18.011502 BS: BS_PAYLOAD_LOAD times (ms): entry 0 run 88 exit 5
1994 12:47:18.014613 mp_park_aps done after 0 msecs.
1995 12:47:18.021441 Jumping to boot code at 30000000(99b62000)
1996 12:47:18.028312 CPU0: stack: 99bf9000 - 99bfa000, lowest used address 99bf99d8, stack used: 1576 bytes
1997 12:47:18.028884
1998 12:47:18.029251
1999 12:47:18.029583
2000 12:47:18.031215 Starting depthcharge on Helios...
2001 12:47:18.031673
2002 12:47:18.033031 end: 2.2.3 depthcharge-start (duration 00:00:13) [common]
2003 12:47:18.033572 start: 2.2.4 bootloader-commands (timeout 00:04:42) [common]
2004 12:47:18.034110 Setting prompt string to ['hatch:']
2005 12:47:18.034568 bootloader-commands: Wait for prompt ['hatch:'] (timeout 00:04:42)
2006 12:47:18.041064 WARNING: can't convert coreboot GPIOs, 'lid' won't be resampled at runtime!
2007 12:47:18.041628
2008 12:47:18.047915 WARNING: can't convert coreboot GPIOs, 'power' won't be resampled at runtime!
2009 12:47:18.048513
2010 12:47:18.054790 board_setup: Info: eMMC controller not present; skipping
2011 12:47:18.055345
2012 12:47:18.057649 New NVMe Controller 0x30053ac0 @ 00:1d:00
2013 12:47:18.058202
2014 12:47:18.064833 board_setup: Info: SDHCI controller not present; skipping
2015 12:47:18.065397
2016 12:47:18.071126 vboot_create_vbsd: creating legacy VbSharedDataHeader structure
2017 12:47:18.071687
2018 12:47:18.072172 Wipe memory regions:
2019 12:47:18.072524
2020 12:47:18.073998 [0x00000000001000, 0x000000000a0000)
2021 12:47:18.074606
2022 12:47:18.077367 [0x00000000100000, 0x00000030000000)
2023 12:47:18.143664
2024 12:47:18.146854 [0x00000030657430, 0x00000099a2c000)
2025 12:47:18.284189
2026 12:47:18.287412 [0x00000100000000, 0x0000045e800000)
2027 12:47:19.669241
2028 12:47:19.669841 R8152: Initializing
2029 12:47:19.670320
2030 12:47:19.672971 Version 9 (ocp_data = 6010)
2031 12:47:19.676793
2032 12:47:19.677264 R8152: Done initializing
2033 12:47:19.677740
2034 12:47:19.680259 Adding net device
2035 12:47:20.163118
2036 12:47:20.163701 R8152: Initializing
2037 12:47:20.164313
2038 12:47:20.166428 Version 6 (ocp_data = 5c30)
2039 12:47:20.166926
2040 12:47:20.169065 R8152: Done initializing
2041 12:47:20.169143
2042 12:47:20.175839 net_add_device: Attemp to include the same device
2043 12:47:20.176004
2044 12:47:20.183002 [firmware-hatch-12672.B-collabora] Jul 21 2021 08:27:58
2045 12:47:20.183173
2046 12:47:20.183251
2047 12:47:20.183320
2048 12:47:20.183625 Setting prompt string to ['hatch:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
2050 12:47:20.284247 hatch: tftpboot 192.168.201.1 12437333/tftp-deploy-ms_81r7r/kernel/bzImage 12437333/tftp-deploy-ms_81r7r/kernel/cmdline 12437333/tftp-deploy-ms_81r7r/ramdisk/ramdisk.cpio.gz
2051 12:47:20.284925 Setting prompt string to ['Starting kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
2052 12:47:20.285362 bootloader-commands: Wait for prompt ['Starting kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:40)
2053 12:47:20.289796 tftpboot 192.168.201.1 12437333/tftp-deploy-ms_81r7r/kernel/bzImploy-ms_81r7r/kernel/cmdline 12437333/tftp-deploy-ms_81r7r/ramdisk/ramdisk.cpio.gz
2054 12:47:20.290278
2055 12:47:20.290638 Waiting for link
2056 12:47:20.490838
2057 12:47:20.491535 done.
2058 12:47:20.491907
2059 12:47:20.492316 MAC: 00:24:32:50:1a:5f
2060 12:47:20.492689
2061 12:47:20.494074 Sending DHCP discover... done.
2062 12:47:20.494556
2063 12:47:20.497122 Waiting for reply... done.
2064 12:47:20.497580
2065 12:47:20.501411 Sending DHCP request... done.
2066 12:47:20.501913
2067 12:47:20.507503 Waiting for reply... done.
2068 12:47:20.508116
2069 12:47:20.508605 My ip is 192.168.201.21
2070 12:47:20.509059
2071 12:47:20.510567 The DHCP server ip is 192.168.201.1
2072 12:47:20.511038
2073 12:47:20.517611 TFTP server IP predefined by user: 192.168.201.1
2074 12:47:20.518189
2075 12:47:20.523969 Bootfile predefined by user: 12437333/tftp-deploy-ms_81r7r/kernel/bzImage
2076 12:47:20.524573
2077 12:47:20.527389 Sending tftp read request... done.
2078 12:47:20.527952
2079 12:47:20.536928 Waiting for the transfer...
2080 12:47:20.537483
2081 12:47:21.267624 00000000 ################################################################
2082 12:47:21.268253
2083 12:47:21.961482 00080000 ################################################################
2084 12:47:21.962077
2085 12:47:22.686564 00100000 ################################################################
2086 12:47:22.687071
2087 12:47:23.401897 00180000 ################################################################
2088 12:47:23.402465
2089 12:47:24.126962 00200000 ################################################################
2090 12:47:24.127547
2091 12:47:24.860876 00280000 ################################################################
2092 12:47:24.861409
2093 12:47:25.584632 00300000 ################################################################
2094 12:47:25.585167
2095 12:47:26.307846 00380000 ################################################################
2096 12:47:26.308476
2097 12:47:27.030116 00400000 ################################################################
2098 12:47:27.030704
2099 12:47:27.739802 00480000 ################################################################
2100 12:47:27.740451
2101 12:47:28.456772 00500000 ################################################################
2102 12:47:28.457294
2103 12:47:29.166008 00580000 ################################################################
2104 12:47:29.166543
2105 12:47:29.906361 00600000 ################################################################
2106 12:47:29.906920
2107 12:47:30.621445 00680000 ################################################################
2108 12:47:30.621987
2109 12:47:31.336402 00700000 ################################################################
2110 12:47:31.336967
2111 12:47:32.052748 00780000 ################################################################
2112 12:47:32.053318
2113 12:47:32.320991 00800000 ######################## done.
2114 12:47:32.321514
2115 12:47:32.324358 The bootfile was 8585104 bytes long.
2116 12:47:32.324785
2117 12:47:32.327547 Sending tftp read request... done.
2118 12:47:32.327965
2119 12:47:32.330834 Waiting for the transfer...
2120 12:47:32.331300
2121 12:47:33.012612 00000000 ################################################################
2122 12:47:33.013123
2123 12:47:33.735035 00080000 ################################################################
2124 12:47:33.735606
2125 12:47:34.474868 00100000 ################################################################
2126 12:47:34.475435
2127 12:47:35.210589 00180000 ################################################################
2128 12:47:35.211281
2129 12:47:35.935287 00200000 ################################################################
2130 12:47:35.935905
2131 12:47:36.642035 00280000 ################################################################
2132 12:47:36.642587
2133 12:47:37.359121 00300000 ################################################################
2134 12:47:37.359694
2135 12:47:38.085089 00380000 ################################################################
2136 12:47:38.085688
2137 12:47:38.814681 00400000 ################################################################
2138 12:47:38.815218
2139 12:47:39.540202 00480000 ################################################################
2140 12:47:39.540777
2141 12:47:40.255413 00500000 ################################################################
2142 12:47:40.256012
2143 12:47:40.579375 00580000 ############################# done.
2144 12:47:40.579943
2145 12:47:40.581851 Sending tftp read request... done.
2146 12:47:40.582311
2147 12:47:40.584746 Waiting for the transfer...
2148 12:47:40.585204
2149 12:47:40.585580 00000000 # done.
2150 12:47:40.588127
2151 12:47:40.595836 Command line loaded dynamically from TFTP file: 12437333/tftp-deploy-ms_81r7r/kernel/cmdline
2152 12:47:40.596567
2153 12:47:40.624639 The command line is: earlyprintk=uart8250,mmio32,0xfedc6000,115200n8 console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12437333/extract-nfsrootfs-4kjdl8g9,tcp,hard ip=dhcp tftpserverip=192.168.201.1
2154 12:47:40.625216
2155 12:47:40.631322 ec_init(0): CrosEC protocol v3 supported (256, 256)
2156 12:47:40.635588
2157 12:47:40.638187 Shutting down all USB controllers.
2158 12:47:40.638776
2159 12:47:40.639145 Removing current net device
2160 12:47:40.642685
2161 12:47:40.643275 Finalizing coreboot
2162 12:47:40.643645
2163 12:47:40.648774 Exiting depthcharge with code 4 at timestamp: 29978701
2164 12:47:40.649349
2165 12:47:40.649714
2166 12:47:40.650051 Starting kernel ...
2167 12:47:40.650374
2168 12:47:40.651690 end: 2.2.4 bootloader-commands (duration 00:00:23) [common]
2169 12:47:40.652256 start: 2.2.5 auto-login-action (timeout 00:04:19) [common]
2170 12:47:40.652667 Setting prompt string to ['Linux version [0-9]']
2171 12:47:40.653037 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
2172 12:47:40.653433 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
2173 12:47:40.654313
2175 12:51:59.653183 end: 2.2.5 auto-login-action (duration 00:04:19) [common]
2177 12:51:59.654266 depthcharge-retry failed: 1 of 1 attempts. 'auto-login-action timed out after 259 seconds'
2179 12:51:59.655102 end: 2.2 depthcharge-retry (duration 00:05:00) [common]
2182 12:51:59.656671 end: 2 depthcharge-action (duration 00:05:00) [common]
2184 12:51:59.658126 Cleaning after the job
2185 12:51:59.658629 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12437333/tftp-deploy-ms_81r7r/ramdisk
2186 12:51:59.664160 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12437333/tftp-deploy-ms_81r7r/kernel
2187 12:51:59.671028 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12437333/tftp-deploy-ms_81r7r/nfsrootfs
2188 12:51:59.811737 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12437333/tftp-deploy-ms_81r7r/modules
2189 12:51:59.812188 start: 4.1 power-off (timeout 00:00:30) [common]
2190 12:51:59.812362 Calling: 'pduclient' '--daemon=localhost' '--hostname=asus-C436FA-Flip-hatch-cbg-0' '--port=1' '--command=off'
2191 12:51:59.885809 >> Command sent successfully.
2192 12:51:59.889805 Returned 0 in 0 seconds
2193 12:51:59.990851 end: 4.1 power-off (duration 00:00:00) [common]
2195 12:51:59.992473 start: 4.2 read-feedback (timeout 00:10:00) [common]
2196 12:51:59.993826 Listened to connection for namespace 'common' for up to 1s
2198 12:51:59.995167 Listened to connection for namespace 'common' for up to 1s
2199 12:52:00.994400 Finalising connection for namespace 'common'
2200 12:52:00.995131 Disconnecting from shell: Finalise
2201 12:52:00.995559
2202 12:52:01.096626 end: 4.2 read-feedback (duration 00:00:01) [common]
2203 12:52:01.097305 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12437333
2204 12:52:01.636103 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12437333
2205 12:52:01.636323 JobError: Your job cannot terminate cleanly.