Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 44
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 33
1 22:15:49.657018 lava-dispatcher, installed at version: 2023.03
2 22:15:49.657217 start: 0 validate
3 22:15:49.657338 Start time: 2023-06-04 22:15:49.657331+00:00 (UTC)
4 22:15:49.657453 Using caching service: 'http://localhost/cache/?uri=%s'
5 22:15:49.657576 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20230527.0%2Farm64%2Finitrd.cpio.gz exists
6 22:15:49.947277 Using caching service: 'http://localhost/cache/?uri=%s'
7 22:15:49.948064 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1281-g84d5372e0f314%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 22:15:50.242559 Using caching service: 'http://localhost/cache/?uri=%s'
9 22:15:50.243387 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1281-g84d5372e0f314%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 22:15:50.538735 Using caching service: 'http://localhost/cache/?uri=%s'
11 22:15:50.539510 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20230527.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 22:15:50.835594 Using caching service: 'http://localhost/cache/?uri=%s'
13 22:15:50.836287 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1281-g84d5372e0f314%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 22:15:51.139006 validate duration: 1.48
16 22:15:51.140322 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 22:15:51.140872 start: 1.1 download-retry (timeout 00:10:00) [common]
18 22:15:51.141384 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 22:15:51.142029 Not decompressing ramdisk as can be used compressed.
20 22:15:51.142523 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20230527.0/arm64/initrd.cpio.gz
21 22:15:51.142884 saving as /var/lib/lava/dispatcher/tmp/10583911/tftp-deploy-_wzpf10d/ramdisk/initrd.cpio.gz
22 22:15:51.143276 total size: 5624321 (5MB)
23 22:15:51.149070 progress 0% (0MB)
24 22:15:51.157131 progress 5% (0MB)
25 22:15:51.162639 progress 10% (0MB)
26 22:15:51.166513 progress 15% (0MB)
27 22:15:51.170065 progress 20% (1MB)
28 22:15:51.172841 progress 25% (1MB)
29 22:15:51.175810 progress 30% (1MB)
30 22:15:51.178323 progress 35% (1MB)
31 22:15:51.180560 progress 40% (2MB)
32 22:15:51.182787 progress 45% (2MB)
33 22:15:51.184729 progress 50% (2MB)
34 22:15:51.186798 progress 55% (2MB)
35 22:15:51.188522 progress 60% (3MB)
36 22:15:51.190443 progress 65% (3MB)
37 22:15:51.192243 progress 70% (3MB)
38 22:15:51.193789 progress 75% (4MB)
39 22:15:51.195524 progress 80% (4MB)
40 22:15:51.196978 progress 85% (4MB)
41 22:15:51.198550 progress 90% (4MB)
42 22:15:51.200138 progress 95% (5MB)
43 22:15:51.201546 progress 100% (5MB)
44 22:15:51.201726 5MB downloaded in 0.06s (91.76MB/s)
45 22:15:51.201865 end: 1.1.1 http-download (duration 00:00:00) [common]
47 22:15:51.202087 end: 1.1 download-retry (duration 00:00:00) [common]
48 22:15:51.202168 start: 1.2 download-retry (timeout 00:10:00) [common]
49 22:15:51.202248 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 22:15:51.202371 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1281-g84d5372e0f314/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 22:15:51.202438 saving as /var/lib/lava/dispatcher/tmp/10583911/tftp-deploy-_wzpf10d/kernel/Image
52 22:15:51.202495 total size: 45746688 (43MB)
53 22:15:51.202552 No compression specified
54 22:15:51.203653 progress 0% (0MB)
55 22:15:51.214856 progress 5% (2MB)
56 22:15:51.226120 progress 10% (4MB)
57 22:15:51.237486 progress 15% (6MB)
58 22:15:51.249115 progress 20% (8MB)
59 22:15:51.260599 progress 25% (10MB)
60 22:15:51.271923 progress 30% (13MB)
61 22:15:51.283407 progress 35% (15MB)
62 22:15:51.294783 progress 40% (17MB)
63 22:15:51.306200 progress 45% (19MB)
64 22:15:51.317545 progress 50% (21MB)
65 22:15:51.328843 progress 55% (24MB)
66 22:15:51.340276 progress 60% (26MB)
67 22:15:51.351685 progress 65% (28MB)
68 22:15:51.363062 progress 70% (30MB)
69 22:15:51.374510 progress 75% (32MB)
70 22:15:51.385792 progress 80% (34MB)
71 22:15:51.397214 progress 85% (37MB)
72 22:15:51.408594 progress 90% (39MB)
73 22:15:51.419714 progress 95% (41MB)
74 22:15:51.430850 progress 100% (43MB)
75 22:15:51.430966 43MB downloaded in 0.23s (190.96MB/s)
76 22:15:51.431113 end: 1.2.1 http-download (duration 00:00:00) [common]
78 22:15:51.431335 end: 1.2 download-retry (duration 00:00:00) [common]
79 22:15:51.431419 start: 1.3 download-retry (timeout 00:10:00) [common]
80 22:15:51.431506 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 22:15:51.431643 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1281-g84d5372e0f314/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 22:15:51.431710 saving as /var/lib/lava/dispatcher/tmp/10583911/tftp-deploy-_wzpf10d/dtb/mt8192-asurada-spherion-r0.dtb
83 22:15:51.431767 total size: 46924 (0MB)
84 22:15:51.431824 No compression specified
85 22:15:51.432938 progress 69% (0MB)
86 22:15:51.433207 progress 100% (0MB)
87 22:15:51.433355 0MB downloaded in 0.00s (28.24MB/s)
88 22:15:51.433472 end: 1.3.1 http-download (duration 00:00:00) [common]
90 22:15:51.433688 end: 1.3 download-retry (duration 00:00:00) [common]
91 22:15:51.433770 start: 1.4 download-retry (timeout 00:10:00) [common]
92 22:15:51.433851 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 22:15:51.433957 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20230527.0/arm64/full.rootfs.tar.xz
94 22:15:51.434022 saving as /var/lib/lava/dispatcher/tmp/10583911/tftp-deploy-_wzpf10d/nfsrootfs/full.rootfs.tar
95 22:15:51.434080 total size: 195125384 (186MB)
96 22:15:51.434138 Using unxz to decompress xz
97 22:15:51.437734 progress 0% (0MB)
98 22:15:51.977167 progress 5% (9MB)
99 22:15:52.466023 progress 10% (18MB)
100 22:15:53.030799 progress 15% (27MB)
101 22:15:53.300022 progress 20% (37MB)
102 22:15:53.738257 progress 25% (46MB)
103 22:15:54.285756 progress 30% (55MB)
104 22:15:54.820465 progress 35% (65MB)
105 22:15:55.353661 progress 40% (74MB)
106 22:15:55.904423 progress 45% (83MB)
107 22:15:56.487067 progress 50% (93MB)
108 22:15:57.070879 progress 55% (102MB)
109 22:15:57.704879 progress 60% (111MB)
110 22:15:58.092149 progress 65% (120MB)
111 22:15:58.169274 progress 70% (130MB)
112 22:15:58.316401 progress 75% (139MB)
113 22:15:58.390882 progress 80% (148MB)
114 22:15:58.436981 progress 85% (158MB)
115 22:15:58.523998 progress 90% (167MB)
116 22:15:58.882695 progress 95% (176MB)
117 22:15:59.430625 progress 100% (186MB)
118 22:15:59.436635 186MB downloaded in 8.00s (23.25MB/s)
119 22:15:59.436918 end: 1.4.1 http-download (duration 00:00:08) [common]
121 22:15:59.437167 end: 1.4 download-retry (duration 00:00:08) [common]
122 22:15:59.437281 start: 1.5 download-retry (timeout 00:09:52) [common]
123 22:15:59.437365 start: 1.5.1 http-download (timeout 00:09:52) [common]
124 22:15:59.437511 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1281-g84d5372e0f314/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 22:15:59.437579 saving as /var/lib/lava/dispatcher/tmp/10583911/tftp-deploy-_wzpf10d/modules/modules.tar
126 22:15:59.437637 total size: 8541948 (8MB)
127 22:15:59.437696 Using unxz to decompress xz
128 22:15:59.441308 progress 0% (0MB)
129 22:15:59.462773 progress 5% (0MB)
130 22:15:59.487978 progress 10% (0MB)
131 22:15:59.512873 progress 15% (1MB)
132 22:15:59.537414 progress 20% (1MB)
133 22:15:59.560639 progress 25% (2MB)
134 22:15:59.587726 progress 30% (2MB)
135 22:15:59.612101 progress 35% (2MB)
136 22:15:59.635884 progress 40% (3MB)
137 22:15:59.659497 progress 45% (3MB)
138 22:15:59.683696 progress 50% (4MB)
139 22:15:59.706478 progress 55% (4MB)
140 22:15:59.730385 progress 60% (4MB)
141 22:15:59.754860 progress 65% (5MB)
142 22:15:59.778986 progress 70% (5MB)
143 22:15:59.801595 progress 75% (6MB)
144 22:15:59.824764 progress 80% (6MB)
145 22:15:59.848987 progress 85% (6MB)
146 22:15:59.877563 progress 90% (7MB)
147 22:15:59.902916 progress 95% (7MB)
148 22:15:59.926462 progress 100% (8MB)
149 22:15:59.933242 8MB downloaded in 0.50s (16.44MB/s)
150 22:15:59.933519 end: 1.5.1 http-download (duration 00:00:00) [common]
152 22:15:59.933830 end: 1.5 download-retry (duration 00:00:00) [common]
153 22:15:59.933960 start: 1.6 prepare-tftp-overlay (timeout 00:09:51) [common]
154 22:15:59.934055 start: 1.6.1 extract-nfsrootfs (timeout 00:09:51) [common]
155 22:16:03.421533 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/10583911/extract-nfsrootfs-av2vgxp6
156 22:16:03.421720 end: 1.6.1 extract-nfsrootfs (duration 00:00:03) [common]
157 22:16:03.421817 start: 1.6.2 lava-overlay (timeout 00:09:48) [common]
158 22:16:03.421982 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10583911/lava-overlay-26futv5k
159 22:16:03.422105 makedir: /var/lib/lava/dispatcher/tmp/10583911/lava-overlay-26futv5k/lava-10583911/bin
160 22:16:03.422209 makedir: /var/lib/lava/dispatcher/tmp/10583911/lava-overlay-26futv5k/lava-10583911/tests
161 22:16:03.422304 makedir: /var/lib/lava/dispatcher/tmp/10583911/lava-overlay-26futv5k/lava-10583911/results
162 22:16:03.422404 Creating /var/lib/lava/dispatcher/tmp/10583911/lava-overlay-26futv5k/lava-10583911/bin/lava-add-keys
163 22:16:03.422546 Creating /var/lib/lava/dispatcher/tmp/10583911/lava-overlay-26futv5k/lava-10583911/bin/lava-add-sources
164 22:16:03.422672 Creating /var/lib/lava/dispatcher/tmp/10583911/lava-overlay-26futv5k/lava-10583911/bin/lava-background-process-start
165 22:16:03.422797 Creating /var/lib/lava/dispatcher/tmp/10583911/lava-overlay-26futv5k/lava-10583911/bin/lava-background-process-stop
166 22:16:03.422919 Creating /var/lib/lava/dispatcher/tmp/10583911/lava-overlay-26futv5k/lava-10583911/bin/lava-common-functions
167 22:16:03.423041 Creating /var/lib/lava/dispatcher/tmp/10583911/lava-overlay-26futv5k/lava-10583911/bin/lava-echo-ipv4
168 22:16:03.423168 Creating /var/lib/lava/dispatcher/tmp/10583911/lava-overlay-26futv5k/lava-10583911/bin/lava-install-packages
169 22:16:03.423288 Creating /var/lib/lava/dispatcher/tmp/10583911/lava-overlay-26futv5k/lava-10583911/bin/lava-installed-packages
170 22:16:03.423407 Creating /var/lib/lava/dispatcher/tmp/10583911/lava-overlay-26futv5k/lava-10583911/bin/lava-os-build
171 22:16:03.423528 Creating /var/lib/lava/dispatcher/tmp/10583911/lava-overlay-26futv5k/lava-10583911/bin/lava-probe-channel
172 22:16:03.423647 Creating /var/lib/lava/dispatcher/tmp/10583911/lava-overlay-26futv5k/lava-10583911/bin/lava-probe-ip
173 22:16:03.423768 Creating /var/lib/lava/dispatcher/tmp/10583911/lava-overlay-26futv5k/lava-10583911/bin/lava-target-ip
174 22:16:03.423887 Creating /var/lib/lava/dispatcher/tmp/10583911/lava-overlay-26futv5k/lava-10583911/bin/lava-target-mac
175 22:16:03.424006 Creating /var/lib/lava/dispatcher/tmp/10583911/lava-overlay-26futv5k/lava-10583911/bin/lava-target-storage
176 22:16:03.424129 Creating /var/lib/lava/dispatcher/tmp/10583911/lava-overlay-26futv5k/lava-10583911/bin/lava-test-case
177 22:16:03.424250 Creating /var/lib/lava/dispatcher/tmp/10583911/lava-overlay-26futv5k/lava-10583911/bin/lava-test-event
178 22:16:03.424369 Creating /var/lib/lava/dispatcher/tmp/10583911/lava-overlay-26futv5k/lava-10583911/bin/lava-test-feedback
179 22:16:03.424488 Creating /var/lib/lava/dispatcher/tmp/10583911/lava-overlay-26futv5k/lava-10583911/bin/lava-test-raise
180 22:16:03.424606 Creating /var/lib/lava/dispatcher/tmp/10583911/lava-overlay-26futv5k/lava-10583911/bin/lava-test-reference
181 22:16:03.424726 Creating /var/lib/lava/dispatcher/tmp/10583911/lava-overlay-26futv5k/lava-10583911/bin/lava-test-runner
182 22:16:03.424845 Creating /var/lib/lava/dispatcher/tmp/10583911/lava-overlay-26futv5k/lava-10583911/bin/lava-test-set
183 22:16:03.424966 Creating /var/lib/lava/dispatcher/tmp/10583911/lava-overlay-26futv5k/lava-10583911/bin/lava-test-shell
184 22:16:03.425087 Updating /var/lib/lava/dispatcher/tmp/10583911/lava-overlay-26futv5k/lava-10583911/bin/lava-add-keys (debian)
185 22:16:03.425233 Updating /var/lib/lava/dispatcher/tmp/10583911/lava-overlay-26futv5k/lava-10583911/bin/lava-add-sources (debian)
186 22:16:03.425377 Updating /var/lib/lava/dispatcher/tmp/10583911/lava-overlay-26futv5k/lava-10583911/bin/lava-install-packages (debian)
187 22:16:03.425519 Updating /var/lib/lava/dispatcher/tmp/10583911/lava-overlay-26futv5k/lava-10583911/bin/lava-installed-packages (debian)
188 22:16:03.425653 Updating /var/lib/lava/dispatcher/tmp/10583911/lava-overlay-26futv5k/lava-10583911/bin/lava-os-build (debian)
189 22:16:03.425775 Creating /var/lib/lava/dispatcher/tmp/10583911/lava-overlay-26futv5k/lava-10583911/environment
190 22:16:03.425871 LAVA metadata
191 22:16:03.425940 - LAVA_JOB_ID=10583911
192 22:16:03.426002 - LAVA_DISPATCHER_IP=192.168.201.1
193 22:16:03.426100 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:48) [common]
194 22:16:03.426165 skipped lava-vland-overlay
195 22:16:03.426237 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 22:16:03.426314 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:48) [common]
197 22:16:03.426374 skipped lava-multinode-overlay
198 22:16:03.426445 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 22:16:03.426521 start: 1.6.2.3 test-definition (timeout 00:09:48) [common]
200 22:16:03.426592 Loading test definitions
201 22:16:03.426683 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:48) [common]
202 22:16:03.426753 Using /lava-10583911 at stage 0
203 22:16:03.427016 uuid=10583911_1.6.2.3.1 testdef=None
204 22:16:03.427257 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 22:16:03.427343 start: 1.6.2.3.2 test-overlay (timeout 00:09:48) [common]
206 22:16:03.427782 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 22:16:03.427998 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:48) [common]
209 22:16:03.428544 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 22:16:03.428771 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:48) [common]
212 22:16:03.429296 runner path: /var/lib/lava/dispatcher/tmp/10583911/lava-overlay-26futv5k/lava-10583911/0/tests/0_timesync-off test_uuid 10583911_1.6.2.3.1
213 22:16:03.429449 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 22:16:03.429672 start: 1.6.2.3.5 git-repo-action (timeout 00:09:48) [common]
216 22:16:03.429744 Using /lava-10583911 at stage 0
217 22:16:03.429839 Fetching tests from https://github.com/kernelci/test-definitions.git
218 22:16:03.429914 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/10583911/lava-overlay-26futv5k/lava-10583911/0/tests/1_kselftest-alsa'
219 22:16:06.282876 Running '/usr/bin/git checkout kernelci.org
220 22:16:06.426734 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/10583911/lava-overlay-26futv5k/lava-10583911/0/tests/1_kselftest-alsa/automated/linux/kselftest/kselftest.yaml
221 22:16:06.427449 uuid=10583911_1.6.2.3.5 testdef=None
222 22:16:06.427603 end: 1.6.2.3.5 git-repo-action (duration 00:00:03) [common]
224 22:16:06.427851 start: 1.6.2.3.6 test-overlay (timeout 00:09:45) [common]
225 22:16:06.428581 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 22:16:06.428815 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:45) [common]
228 22:16:06.429768 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 22:16:06.430001 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:45) [common]
231 22:16:06.430919 runner path: /var/lib/lava/dispatcher/tmp/10583911/lava-overlay-26futv5k/lava-10583911/0/tests/1_kselftest-alsa test_uuid 10583911_1.6.2.3.5
232 22:16:06.431011 BOARD='mt8192-asurada-spherion-r0'
233 22:16:06.431112 BRANCH='cip'
234 22:16:06.431199 SKIPFILE='/dev/null'
235 22:16:06.431257 SKIP_INSTALL='True'
236 22:16:06.431313 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1281-g84d5372e0f314/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 22:16:06.431370 TST_CASENAME=''
238 22:16:06.431426 TST_CMDFILES='alsa'
239 22:16:06.431564 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 22:16:06.431768 Creating lava-test-runner.conf files
242 22:16:06.431831 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10583911/lava-overlay-26futv5k/lava-10583911/0 for stage 0
243 22:16:06.431923 - 0_timesync-off
244 22:16:06.431991 - 1_kselftest-alsa
245 22:16:06.432084 end: 1.6.2.3 test-definition (duration 00:00:03) [common]
246 22:16:06.432171 start: 1.6.2.4 compress-overlay (timeout 00:09:45) [common]
247 22:16:14.142861 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 22:16:14.143009 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:37) [common]
249 22:16:14.143142 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 22:16:14.143241 end: 1.6.2 lava-overlay (duration 00:00:11) [common]
251 22:16:14.143332 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:37) [common]
252 22:16:14.305129 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 22:16:14.305476 start: 1.6.4 extract-modules (timeout 00:09:37) [common]
254 22:16:14.305591 extracting modules file /var/lib/lava/dispatcher/tmp/10583911/tftp-deploy-_wzpf10d/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10583911/extract-nfsrootfs-av2vgxp6
255 22:16:14.509168 extracting modules file /var/lib/lava/dispatcher/tmp/10583911/tftp-deploy-_wzpf10d/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10583911/extract-overlay-ramdisk-7eelbf1i/ramdisk
256 22:16:14.716366 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 22:16:14.716521 start: 1.6.5 apply-overlay-tftp (timeout 00:09:36) [common]
258 22:16:14.716619 [common] Applying overlay to NFS
259 22:16:14.716692 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10583911/compress-overlay-o_79urty/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10583911/extract-nfsrootfs-av2vgxp6
260 22:16:15.617464 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 22:16:15.617635 start: 1.6.6 configure-preseed-file (timeout 00:09:36) [common]
262 22:16:15.617736 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 22:16:15.617825 start: 1.6.7 compress-ramdisk (timeout 00:09:36) [common]
264 22:16:15.617907 Building ramdisk /var/lib/lava/dispatcher/tmp/10583911/extract-overlay-ramdisk-7eelbf1i/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10583911/extract-overlay-ramdisk-7eelbf1i/ramdisk
265 22:16:15.918055 >> 128921 blocks
266 22:16:17.994668 rename /var/lib/lava/dispatcher/tmp/10583911/extract-overlay-ramdisk-7eelbf1i/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10583911/tftp-deploy-_wzpf10d/ramdisk/ramdisk.cpio.gz
267 22:16:17.995130 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 22:16:17.995253 start: 1.6.8 prepare-kernel (timeout 00:09:33) [common]
269 22:16:17.995354 start: 1.6.8.1 prepare-fit (timeout 00:09:33) [common]
270 22:16:17.995452 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10583911/tftp-deploy-_wzpf10d/kernel/Image'
271 22:16:29.755676 Returned 0 in 11 seconds
272 22:16:29.856666 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10583911/tftp-deploy-_wzpf10d/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10583911/tftp-deploy-_wzpf10d/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10583911/tftp-deploy-_wzpf10d/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10583911/tftp-deploy-_wzpf10d/kernel/image.itb
273 22:16:30.179639 output: FIT description: Kernel Image image with one or more FDT blobs
274 22:16:30.179997 output: Created: Sun Jun 4 23:16:30 2023
275 22:16:30.180072 output: Image 0 (kernel-1)
276 22:16:30.180136 output: Description:
277 22:16:30.180198 output: Created: Sun Jun 4 23:16:30 2023
278 22:16:30.180258 output: Type: Kernel Image
279 22:16:30.180317 output: Compression: lzma compressed
280 22:16:30.180374 output: Data Size: 10081729 Bytes = 9845.44 KiB = 9.61 MiB
281 22:16:30.180431 output: Architecture: AArch64
282 22:16:30.180487 output: OS: Linux
283 22:16:30.180547 output: Load Address: 0x00000000
284 22:16:30.180605 output: Entry Point: 0x00000000
285 22:16:30.180663 output: Hash algo: crc32
286 22:16:30.180716 output: Hash value: 3b3111d8
287 22:16:30.180768 output: Image 1 (fdt-1)
288 22:16:30.180821 output: Description: mt8192-asurada-spherion-r0
289 22:16:30.180873 output: Created: Sun Jun 4 23:16:30 2023
290 22:16:30.180926 output: Type: Flat Device Tree
291 22:16:30.180979 output: Compression: uncompressed
292 22:16:30.181031 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
293 22:16:30.181085 output: Architecture: AArch64
294 22:16:30.181137 output: Hash algo: crc32
295 22:16:30.181190 output: Hash value: 1df858fa
296 22:16:30.181242 output: Image 2 (ramdisk-1)
297 22:16:30.181294 output: Description: unavailable
298 22:16:30.181346 output: Created: Sun Jun 4 23:16:30 2023
299 22:16:30.181399 output: Type: RAMDisk Image
300 22:16:30.181451 output: Compression: Unknown Compression
301 22:16:30.181504 output: Data Size: 18607675 Bytes = 18171.56 KiB = 17.75 MiB
302 22:16:30.181557 output: Architecture: AArch64
303 22:16:30.181609 output: OS: Linux
304 22:16:30.181661 output: Load Address: unavailable
305 22:16:30.181713 output: Entry Point: unavailable
306 22:16:30.181765 output: Hash algo: crc32
307 22:16:30.181817 output: Hash value: 9bc19553
308 22:16:30.181870 output: Default Configuration: 'conf-1'
309 22:16:30.181922 output: Configuration 0 (conf-1)
310 22:16:30.181974 output: Description: mt8192-asurada-spherion-r0
311 22:16:30.182026 output: Kernel: kernel-1
312 22:16:30.182079 output: Init Ramdisk: ramdisk-1
313 22:16:30.182132 output: FDT: fdt-1
314 22:16:30.182185 output: Loadables: kernel-1
315 22:16:30.182237 output:
316 22:16:30.182429 end: 1.6.8.1 prepare-fit (duration 00:00:12) [common]
317 22:16:30.182524 end: 1.6.8 prepare-kernel (duration 00:00:12) [common]
318 22:16:30.182632 end: 1.6 prepare-tftp-overlay (duration 00:00:30) [common]
319 22:16:30.182732 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:21) [common]
320 22:16:30.182813 No LXC device requested
321 22:16:30.182895 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 22:16:30.182979 start: 1.8 deploy-device-env (timeout 00:09:21) [common]
323 22:16:30.183065 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 22:16:30.183165 Checking files for TFTP limit of 4294967296 bytes.
325 22:16:30.183643 end: 1 tftp-deploy (duration 00:00:39) [common]
326 22:16:30.183749 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 22:16:30.183838 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 22:16:30.183965 substitutions:
329 22:16:30.184032 - {DTB}: 10583911/tftp-deploy-_wzpf10d/dtb/mt8192-asurada-spherion-r0.dtb
330 22:16:30.184096 - {INITRD}: 10583911/tftp-deploy-_wzpf10d/ramdisk/ramdisk.cpio.gz
331 22:16:30.184155 - {KERNEL}: 10583911/tftp-deploy-_wzpf10d/kernel/Image
332 22:16:30.184213 - {LAVA_MAC}: None
333 22:16:30.184270 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/10583911/extract-nfsrootfs-av2vgxp6
334 22:16:30.184326 - {NFS_SERVER_IP}: 192.168.201.1
335 22:16:30.184381 - {PRESEED_CONFIG}: None
336 22:16:30.184436 - {PRESEED_LOCAL}: None
337 22:16:30.184490 - {RAMDISK}: 10583911/tftp-deploy-_wzpf10d/ramdisk/ramdisk.cpio.gz
338 22:16:30.184544 - {ROOT_PART}: None
339 22:16:30.184599 - {ROOT}: None
340 22:16:30.184652 - {SERVER_IP}: 192.168.201.1
341 22:16:30.184706 - {TEE}: None
342 22:16:30.184759 Parsed boot commands:
343 22:16:30.184813 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 22:16:30.184988 Parsed boot commands: tftpboot 192.168.201.1 10583911/tftp-deploy-_wzpf10d/kernel/image.itb 10583911/tftp-deploy-_wzpf10d/kernel/cmdline
345 22:16:30.185077 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 22:16:30.185164 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 22:16:30.185256 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 22:16:30.185343 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 22:16:30.185416 Not connected, no need to disconnect.
350 22:16:30.185491 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 22:16:30.185570 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 22:16:30.185636 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-9'
353 22:16:30.189108 Setting prompt string to ['lava-test: # ']
354 22:16:30.189455 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 22:16:30.189563 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 22:16:30.189684 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 22:16:30.189808 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 22:16:30.190020 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=reboot'
359 22:16:35.339889 >> Command sent successfully.
360 22:16:35.350538 Returned 0 in 5 seconds
361 22:16:35.451754 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 22:16:35.453131 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 22:16:35.453648 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 22:16:35.454079 Setting prompt string to 'Starting depthcharge on Spherion...'
366 22:16:35.454415 Changing prompt to 'Starting depthcharge on Spherion...'
367 22:16:35.454761 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 22:16:35.456022 [Enter `^Ec?' for help]
369 22:16:35.615592
370 22:16:35.616216
371 22:16:35.616675 F0: 102B 0000
372 22:16:35.616997
373 22:16:35.617303 F3: 1001 0000 [0200]
374 22:16:35.617603
375 22:16:35.619175 F3: 1001 0000
376 22:16:35.619603
377 22:16:35.619937 F7: 102D 0000
378 22:16:35.620247
379 22:16:35.620547 F1: 0000 0000
380 22:16:35.620842
381 22:16:35.622254 V0: 0000 0000 [0001]
382 22:16:35.622678
383 22:16:35.623011 00: 0007 8000
384 22:16:35.623477
385 22:16:35.626021 01: 0000 0000
386 22:16:35.626456
387 22:16:35.626795 BP: 0C00 0209 [0000]
388 22:16:35.627157
389 22:16:35.629668 G0: 1182 0000
390 22:16:35.630091
391 22:16:35.630424 EC: 0000 0021 [4000]
392 22:16:35.630734
393 22:16:35.633409 S7: 0000 0000 [0000]
394 22:16:35.633834
395 22:16:35.634172 CC: 0000 0000 [0001]
396 22:16:35.634489
397 22:16:35.636221 T0: 0000 0040 [010F]
398 22:16:35.636649
399 22:16:35.637019 Jump to BL
400 22:16:35.637346
401 22:16:35.661707
402 22:16:35.662140
403 22:16:35.662475
404 22:16:35.668714 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 22:16:35.672660 ARM64: Exception handlers installed.
406 22:16:35.676107 ARM64: Testing exception
407 22:16:35.680025 ARM64: Done test exception
408 22:16:35.687539 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 22:16:35.694496 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 22:16:35.705316 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 22:16:35.712471 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 22:16:35.719323 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 22:16:35.729649 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 22:16:35.739165 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 22:16:35.745991 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 22:16:35.764506 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 22:16:35.767747 WDT: Last reset was cold boot
418 22:16:35.771148 SPI1(PAD0) initialized at 2873684 Hz
419 22:16:35.774439 SPI5(PAD0) initialized at 992727 Hz
420 22:16:35.777738 VBOOT: Loading verstage.
421 22:16:35.784662 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 22:16:35.787873 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 22:16:35.791037 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 22:16:35.794364 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 22:16:35.802104 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 22:16:35.808646 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 22:16:35.819567 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
428 22:16:35.819988
429 22:16:35.820332
430 22:16:35.829416 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 22:16:35.832365 ARM64: Exception handlers installed.
432 22:16:35.836450 ARM64: Testing exception
433 22:16:35.839225 ARM64: Done test exception
434 22:16:35.842712 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 22:16:35.845734 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 22:16:35.861500 Probing TPM: . done!
437 22:16:35.861986 TPM ready after 0 ms
438 22:16:35.867097 Connected to device vid:did:rid of 1ae0:0028:00
439 22:16:35.873875 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
440 22:16:35.915129 Initialized TPM device CR50 revision 0
441 22:16:35.927600 tlcl_send_startup: Startup return code is 0
442 22:16:35.928091 TPM: setup succeeded
443 22:16:35.940032 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 22:16:35.948797 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 22:16:35.955132 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 22:16:35.968734 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 22:16:35.972175 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 22:16:35.974998 in-header: 03 07 00 00 08 00 00 00
449 22:16:35.978558 in-data: aa e4 47 04 13 02 00 00
450 22:16:35.981985 Chrome EC: UHEPI supported
451 22:16:35.988438 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 22:16:35.991596 in-header: 03 ad 00 00 08 00 00 00
453 22:16:35.995287 in-data: 00 20 20 08 00 00 00 00
454 22:16:35.995705 Phase 1
455 22:16:36.001855 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 22:16:36.005536 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 22:16:36.011742 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 22:16:36.014992 Recovery requested (1009000e)
459 22:16:36.019804 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 22:16:36.027831 tlcl_extend: response is 0
461 22:16:36.035878 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 22:16:36.040796 tlcl_extend: response is 0
463 22:16:36.047660 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 22:16:36.068317 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
465 22:16:36.075470 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 22:16:36.075931
467 22:16:36.076275
468 22:16:36.085358 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 22:16:36.088713 ARM64: Exception handlers installed.
470 22:16:36.092004 ARM64: Testing exception
471 22:16:36.092514 ARM64: Done test exception
472 22:16:36.113953 pmic_efuse_setting: Set efuses in 11 msecs
473 22:16:36.117349 pmwrap_interface_init: Select PMIF_VLD_RDY
474 22:16:36.125783 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 22:16:36.127364 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 22:16:36.131028 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 22:16:36.137365 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 22:16:36.141126 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 22:16:36.148035 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 22:16:36.151636 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 22:16:36.157886 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 22:16:36.161061 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 22:16:36.164392 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 22:16:36.171129 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 22:16:36.174819 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 22:16:36.181214 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 22:16:36.184588 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 22:16:36.190917 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 22:16:36.197335 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 22:16:36.204268 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 22:16:36.207654 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 22:16:36.214043 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 22:16:36.220667 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 22:16:36.224003 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 22:16:36.231541 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 22:16:36.238503 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 22:16:36.242543 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 22:16:36.245999 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 22:16:36.253071 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 22:16:36.259247 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 22:16:36.262996 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 22:16:36.266246 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 22:16:36.273156 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 22:16:36.276741 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 22:16:36.281550 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 22:16:36.287878 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 22:16:36.291216 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 22:16:36.298515 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 22:16:36.301369 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 22:16:36.307775 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 22:16:36.311271 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 22:16:36.318284 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 22:16:36.321314 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 22:16:36.325383 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 22:16:36.332124 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 22:16:36.335405 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 22:16:36.338748 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 22:16:36.342124 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 22:16:36.348611 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 22:16:36.351958 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 22:16:36.355225 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 22:16:36.361565 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 22:16:36.364992 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 22:16:36.368672 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 22:16:36.374942 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 22:16:36.384579 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 22:16:36.387922 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 22:16:36.398059 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 22:16:36.404807 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 22:16:36.411550 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 22:16:36.414619 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 22:16:36.417931 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 22:16:36.426971 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6c, sec=0x2e
534 22:16:36.433024 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 22:16:36.435986 [RTC]rtc_osc_init,62: osc32con val = 0xde6c
536 22:16:36.442443 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 22:16:36.450959 [RTC]rtc_get_frequency_meter,154: input=15, output=835
538 22:16:36.460456 [RTC]rtc_get_frequency_meter,154: input=7, output=708
539 22:16:36.469604 [RTC]rtc_get_frequency_meter,154: input=11, output=771
540 22:16:36.479154 [RTC]rtc_get_frequency_meter,154: input=13, output=803
541 22:16:36.489345 [RTC]rtc_get_frequency_meter,154: input=12, output=788
542 22:16:36.498569 [RTC]rtc_get_frequency_meter,154: input=12, output=788
543 22:16:36.508373 [RTC]rtc_get_frequency_meter,154: input=13, output=804
544 22:16:36.510926 [RTC]rtc_eosc_cali,47: left: 12, middle: 12, right: 13
545 22:16:36.518203 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6c
546 22:16:36.522063 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 22:16:36.524744 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
548 22:16:36.531784 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 22:16:36.534978 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
550 22:16:36.538327 ADC[4]: Raw value=907097 ID=7
551 22:16:36.538803 ADC[3]: Raw value=214021 ID=1
552 22:16:36.541775 RAM Code: 0x71
553 22:16:36.544926 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 22:16:36.551706 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 22:16:36.558102 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
556 22:16:36.564658 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
557 22:16:36.568529 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 22:16:36.571699 in-header: 03 07 00 00 08 00 00 00
559 22:16:36.575250 in-data: aa e4 47 04 13 02 00 00
560 22:16:36.577925 Chrome EC: UHEPI supported
561 22:16:36.585203 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 22:16:36.588209 in-header: 03 dd 00 00 08 00 00 00
563 22:16:36.591171 in-data: 90 20 60 08 00 00 00 00
564 22:16:36.595451 MRC: failed to locate region type 0.
565 22:16:36.601611 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 22:16:36.605057 DRAM-K: Running full calibration
567 22:16:36.611006 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
568 22:16:36.611460 header.status = 0x0
569 22:16:36.614593 header.version = 0x6 (expected: 0x6)
570 22:16:36.617917 header.size = 0xd00 (expected: 0xd00)
571 22:16:36.621022 header.flags = 0x0
572 22:16:36.627634 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 22:16:36.644409 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
574 22:16:36.651156 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 22:16:36.654534 dram_init: ddr_geometry: 2
576 22:16:36.657718 [EMI] MDL number = 2
577 22:16:36.658139 [EMI] Get MDL freq = 0
578 22:16:36.661075 dram_init: ddr_type: 0
579 22:16:36.661496 is_discrete_lpddr4: 1
580 22:16:36.664263 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 22:16:36.664697
582 22:16:36.667392
583 22:16:36.667841 [Bian_co] ETT version 0.0.0.1
584 22:16:36.674272 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
585 22:16:36.674725
586 22:16:36.677913 dramc_set_vcore_voltage set vcore to 650000
587 22:16:36.681018 Read voltage for 800, 4
588 22:16:36.681450 Vio18 = 0
589 22:16:36.681800 Vcore = 650000
590 22:16:36.684405 Vdram = 0
591 22:16:36.684841 Vddq = 0
592 22:16:36.685178 Vmddr = 0
593 22:16:36.687968 dram_init: config_dvfs: 1
594 22:16:36.691051 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 22:16:36.697501 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 22:16:36.700998 [SwImpedanceCal] DRVP=8, DRVN=16, ODTN=9
597 22:16:36.704337 freq_region=0, Reg: DRVP=8, DRVN=16, ODTN=9
598 22:16:36.707617 [SwImpedanceCal] DRVP=14, DRVN=24, ODTN=9
599 22:16:36.714037 freq_region=1, Reg: DRVP=14, DRVN=24, ODTN=9
600 22:16:36.714464 MEM_TYPE=3, freq_sel=18
601 22:16:36.717718 sv_algorithm_assistance_LP4_1600
602 22:16:36.720438 ============ PULL DRAM RESETB DOWN ============
603 22:16:36.727427 ========== PULL DRAM RESETB DOWN end =========
604 22:16:36.730921 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 22:16:36.733881 ===================================
606 22:16:36.737019 LPDDR4 DRAM CONFIGURATION
607 22:16:36.740601 ===================================
608 22:16:36.741040 EX_ROW_EN[0] = 0x0
609 22:16:36.743892 EX_ROW_EN[1] = 0x0
610 22:16:36.744483 LP4Y_EN = 0x0
611 22:16:36.747428 WORK_FSP = 0x0
612 22:16:36.747848 WL = 0x2
613 22:16:36.750459 RL = 0x2
614 22:16:36.750881 BL = 0x2
615 22:16:36.754261 RPST = 0x0
616 22:16:36.754685 RD_PRE = 0x0
617 22:16:36.757140 WR_PRE = 0x1
618 22:16:36.760964 WR_PST = 0x0
619 22:16:36.761386 DBI_WR = 0x0
620 22:16:36.763803 DBI_RD = 0x0
621 22:16:36.764256 OTF = 0x1
622 22:16:36.767585 ===================================
623 22:16:36.770747 ===================================
624 22:16:36.771198 ANA top config
625 22:16:36.773856 ===================================
626 22:16:36.777416 DLL_ASYNC_EN = 0
627 22:16:36.780670 ALL_SLAVE_EN = 1
628 22:16:36.783916 NEW_RANK_MODE = 1
629 22:16:36.786943 DLL_IDLE_MODE = 1
630 22:16:36.787404 LP45_APHY_COMB_EN = 1
631 22:16:36.790290 TX_ODT_DIS = 1
632 22:16:36.794025 NEW_8X_MODE = 1
633 22:16:36.797650 ===================================
634 22:16:36.800338 ===================================
635 22:16:36.803976 data_rate = 1600
636 22:16:36.807173 CKR = 1
637 22:16:36.807602 DQ_P2S_RATIO = 8
638 22:16:36.810429 ===================================
639 22:16:36.813500 CA_P2S_RATIO = 8
640 22:16:36.817308 DQ_CA_OPEN = 0
641 22:16:36.820420 DQ_SEMI_OPEN = 0
642 22:16:36.823547 CA_SEMI_OPEN = 0
643 22:16:36.826928 CA_FULL_RATE = 0
644 22:16:36.827419 DQ_CKDIV4_EN = 1
645 22:16:36.830097 CA_CKDIV4_EN = 1
646 22:16:36.833708 CA_PREDIV_EN = 0
647 22:16:36.837141 PH8_DLY = 0
648 22:16:36.840131 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 22:16:36.843924 DQ_AAMCK_DIV = 4
650 22:16:36.844349 CA_AAMCK_DIV = 4
651 22:16:36.846717 CA_ADMCK_DIV = 4
652 22:16:36.850390 DQ_TRACK_CA_EN = 0
653 22:16:36.853349 CA_PICK = 800
654 22:16:36.857146 CA_MCKIO = 800
655 22:16:36.860784 MCKIO_SEMI = 0
656 22:16:36.863464 PLL_FREQ = 3068
657 22:16:36.863897 DQ_UI_PI_RATIO = 32
658 22:16:36.866592 CA_UI_PI_RATIO = 0
659 22:16:36.870203 ===================================
660 22:16:36.873760 ===================================
661 22:16:36.877160 memory_type:LPDDR4
662 22:16:36.880577 GP_NUM : 10
663 22:16:36.881002 SRAM_EN : 1
664 22:16:36.883583 MD32_EN : 0
665 22:16:36.886950 ===================================
666 22:16:36.887465 [ANA_INIT] >>>>>>>>>>>>>>
667 22:16:36.890340 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 22:16:36.893724 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 22:16:36.896961 ===================================
670 22:16:36.900084 data_rate = 1600,PCW = 0X7600
671 22:16:36.903392 ===================================
672 22:16:36.906840 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 22:16:36.913365 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 22:16:36.920229 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 22:16:36.923366 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 22:16:36.927121 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 22:16:36.930036 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 22:16:36.933535 [ANA_INIT] flow start
679 22:16:36.933957 [ANA_INIT] PLL >>>>>>>>
680 22:16:36.936443 [ANA_INIT] PLL <<<<<<<<
681 22:16:36.940108 [ANA_INIT] MIDPI >>>>>>>>
682 22:16:36.940589 [ANA_INIT] MIDPI <<<<<<<<
683 22:16:36.943268 [ANA_INIT] DLL >>>>>>>>
684 22:16:36.946662 [ANA_INIT] flow end
685 22:16:36.949827 ============ LP4 DIFF to SE enter ============
686 22:16:36.953601 ============ LP4 DIFF to SE exit ============
687 22:16:36.956691 [ANA_INIT] <<<<<<<<<<<<<
688 22:16:36.960072 [Flow] Enable top DCM control >>>>>
689 22:16:36.963258 [Flow] Enable top DCM control <<<<<
690 22:16:36.966490 Enable DLL master slave shuffle
691 22:16:36.969783 ==============================================================
692 22:16:36.973212 Gating Mode config
693 22:16:36.979944 ==============================================================
694 22:16:36.980386 Config description:
695 22:16:36.989561 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 22:16:36.996680 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 22:16:36.999766 SELPH_MODE 0: By rank 1: By Phase
698 22:16:37.007004 ==============================================================
699 22:16:37.010058 GAT_TRACK_EN = 1
700 22:16:37.013766 RX_GATING_MODE = 2
701 22:16:37.016326 RX_GATING_TRACK_MODE = 2
702 22:16:37.019573 SELPH_MODE = 1
703 22:16:37.023322 PICG_EARLY_EN = 1
704 22:16:37.026358 VALID_LAT_VALUE = 1
705 22:16:37.029475 ==============================================================
706 22:16:37.033044 Enter into Gating configuration >>>>
707 22:16:37.036583 Exit from Gating configuration <<<<
708 22:16:37.039298 Enter into DVFS_PRE_config >>>>>
709 22:16:37.052782 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 22:16:37.053242 Exit from DVFS_PRE_config <<<<<
711 22:16:37.056126 Enter into PICG configuration >>>>
712 22:16:37.059668 Exit from PICG configuration <<<<
713 22:16:37.062998 [RX_INPUT] configuration >>>>>
714 22:16:37.066359 [RX_INPUT] configuration <<<<<
715 22:16:37.072667 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 22:16:37.076507 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 22:16:37.083594 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 22:16:37.091013 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 22:16:37.094293 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 22:16:37.101443 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 22:16:37.105116 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 22:16:37.108306 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 22:16:37.112405 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 22:16:37.119550 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 22:16:37.123117 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 22:16:37.126486 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 22:16:37.130441 ===================================
728 22:16:37.133389 LPDDR4 DRAM CONFIGURATION
729 22:16:37.137004 ===================================
730 22:16:37.137431 EX_ROW_EN[0] = 0x0
731 22:16:37.140305 EX_ROW_EN[1] = 0x0
732 22:16:37.140729 LP4Y_EN = 0x0
733 22:16:37.143710 WORK_FSP = 0x0
734 22:16:37.144140 WL = 0x2
735 22:16:37.147842 RL = 0x2
736 22:16:37.148277 BL = 0x2
737 22:16:37.152006 RPST = 0x0
738 22:16:37.152385 RD_PRE = 0x0
739 22:16:37.152706 WR_PRE = 0x1
740 22:16:37.155657 WR_PST = 0x0
741 22:16:37.156076 DBI_WR = 0x0
742 22:16:37.158944 DBI_RD = 0x0
743 22:16:37.159440 OTF = 0x1
744 22:16:37.162548 ===================================
745 22:16:37.166422 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 22:16:37.170473 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 22:16:37.177186 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 22:16:37.180779 ===================================
749 22:16:37.181289 LPDDR4 DRAM CONFIGURATION
750 22:16:37.184615 ===================================
751 22:16:37.188293 EX_ROW_EN[0] = 0x10
752 22:16:37.188858 EX_ROW_EN[1] = 0x0
753 22:16:37.191949 LP4Y_EN = 0x0
754 22:16:37.192374 WORK_FSP = 0x0
755 22:16:37.195678 WL = 0x2
756 22:16:37.196107 RL = 0x2
757 22:16:37.199544 BL = 0x2
758 22:16:37.199972 RPST = 0x0
759 22:16:37.200309 RD_PRE = 0x0
760 22:16:37.202843 WR_PRE = 0x1
761 22:16:37.203392 WR_PST = 0x0
762 22:16:37.206730 DBI_WR = 0x0
763 22:16:37.207313 DBI_RD = 0x0
764 22:16:37.210203 OTF = 0x1
765 22:16:37.213896 ===================================
766 22:16:37.217528 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 22:16:37.223390 nWR fixed to 40
768 22:16:37.227013 [ModeRegInit_LP4] CH0 RK0
769 22:16:37.227483 [ModeRegInit_LP4] CH0 RK1
770 22:16:37.229951 [ModeRegInit_LP4] CH1 RK0
771 22:16:37.233720 [ModeRegInit_LP4] CH1 RK1
772 22:16:37.234165 match AC timing 13
773 22:16:37.237378 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
774 22:16:37.240854 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 22:16:37.248061 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 22:16:37.251479 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 22:16:37.257517 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 22:16:37.257944 [EMI DOE] emi_dcm 0
779 22:16:37.260611 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 22:16:37.261103 ==
781 22:16:37.263990 Dram Type= 6, Freq= 0, CH_0, rank 0
782 22:16:37.272007 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
783 22:16:37.272482 ==
784 22:16:37.275337 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 22:16:37.282061 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 22:16:37.290380 [CA 0] Center 37 (6~68) winsize 63
787 22:16:37.293770 [CA 1] Center 36 (6~67) winsize 62
788 22:16:37.297169 [CA 2] Center 34 (4~65) winsize 62
789 22:16:37.300412 [CA 3] Center 34 (4~65) winsize 62
790 22:16:37.304001 [CA 4] Center 33 (3~64) winsize 62
791 22:16:37.307465 [CA 5] Center 33 (3~64) winsize 62
792 22:16:37.307885
793 22:16:37.311118 [CmdBusTrainingLP45] Vref(ca) range 1: 32
794 22:16:37.311620
795 22:16:37.314579 [CATrainingPosCal] consider 1 rank data
796 22:16:37.317293 u2DelayCellTimex100 = 270/100 ps
797 22:16:37.321023 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
798 22:16:37.324088 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
799 22:16:37.327161 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
800 22:16:37.331108 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
801 22:16:37.337514 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
802 22:16:37.340637 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
803 22:16:37.341060
804 22:16:37.344030 CA PerBit enable=1, Macro0, CA PI delay=33
805 22:16:37.344451
806 22:16:37.347473 [CBTSetCACLKResult] CA Dly = 33
807 22:16:37.347895 CS Dly: 7 (0~38)
808 22:16:37.348233 ==
809 22:16:37.350905 Dram Type= 6, Freq= 0, CH_0, rank 1
810 22:16:37.357087 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 22:16:37.357512 ==
812 22:16:37.360409 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 22:16:37.367241 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 22:16:37.377193 [CA 0] Center 37 (6~68) winsize 63
815 22:16:37.379962 [CA 1] Center 37 (7~68) winsize 62
816 22:16:37.383147 [CA 2] Center 34 (4~65) winsize 62
817 22:16:37.386840 [CA 3] Center 34 (4~65) winsize 62
818 22:16:37.389641 [CA 4] Center 33 (3~64) winsize 62
819 22:16:37.393108 [CA 5] Center 33 (3~64) winsize 62
820 22:16:37.393531
821 22:16:37.396689 [CmdBusTrainingLP45] Vref(ca) range 1: 32
822 22:16:37.397109
823 22:16:37.399789 [CATrainingPosCal] consider 2 rank data
824 22:16:37.403220 u2DelayCellTimex100 = 270/100 ps
825 22:16:37.406612 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
826 22:16:37.411100 CA1 delay=37 (7~67),Diff = 4 PI (28 cell)
827 22:16:37.413920 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
828 22:16:37.420265 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
829 22:16:37.423552 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
830 22:16:37.427272 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
831 22:16:37.427692
832 22:16:37.431220 CA PerBit enable=1, Macro0, CA PI delay=33
833 22:16:37.431785
834 22:16:37.433830 [CBTSetCACLKResult] CA Dly = 33
835 22:16:37.434374 CS Dly: 7 (0~38)
836 22:16:37.434693
837 22:16:37.438052 ----->DramcWriteLeveling(PI) begin...
838 22:16:37.438564 ==
839 22:16:37.441652 Dram Type= 6, Freq= 0, CH_0, rank 0
840 22:16:37.444848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
841 22:16:37.445409 ==
842 22:16:37.448144 Write leveling (Byte 0): 35 => 35
843 22:16:37.451612 Write leveling (Byte 1): 30 => 30
844 22:16:37.454595 DramcWriteLeveling(PI) end<-----
845 22:16:37.455127
846 22:16:37.455470 ==
847 22:16:37.457948 Dram Type= 6, Freq= 0, CH_0, rank 0
848 22:16:37.461605 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
849 22:16:37.462056 ==
850 22:16:37.464866 [Gating] SW mode calibration
851 22:16:37.471572 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 22:16:37.477962 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 22:16:37.481251 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
854 22:16:37.488130 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
855 22:16:37.491508 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
856 22:16:37.495001 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 22:16:37.501441 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 22:16:37.504663 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 22:16:37.508019 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 22:16:37.514874 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 22:16:37.518200 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 22:16:37.521382 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 22:16:37.527951 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 22:16:37.531481 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 22:16:37.534673 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 22:16:37.538276 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 22:16:37.544696 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 22:16:37.547600 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 22:16:37.551384 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 22:16:37.557925 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
871 22:16:37.560998 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
872 22:16:37.564816 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 22:16:37.570998 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 22:16:37.574302 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 22:16:37.577863 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 22:16:37.584008 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 22:16:37.587505 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 22:16:37.591231 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
879 22:16:37.597964 0 9 8 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
880 22:16:37.601178 0 9 12 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 1)
881 22:16:37.604530 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 22:16:37.611133 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 22:16:37.614516 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 22:16:37.617544 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 22:16:37.624111 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
886 22:16:37.627482 0 10 4 | B1->B0 | 3434 3232 | 1 0 | (1 1) (1 0)
887 22:16:37.631009 0 10 8 | B1->B0 | 3333 2e2e | 1 0 | (1 0) (0 0)
888 22:16:37.637321 0 10 12 | B1->B0 | 2828 2323 | 0 0 | (1 0) (0 0)
889 22:16:37.640942 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 22:16:37.644058 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 22:16:37.650553 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 22:16:37.653860 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 22:16:37.657366 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
894 22:16:37.663904 0 11 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
895 22:16:37.667207 0 11 8 | B1->B0 | 2323 3838 | 1 0 | (0 0) (1 1)
896 22:16:37.670918 0 11 12 | B1->B0 | 3939 4646 | 1 0 | (0 0) (0 0)
897 22:16:37.677502 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 22:16:37.680273 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 22:16:37.683540 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 22:16:37.689797 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 22:16:37.693368 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
902 22:16:37.696946 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
903 22:16:37.703364 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
904 22:16:37.706820 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
905 22:16:37.709802 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 22:16:37.713098 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 22:16:37.720153 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 22:16:37.723475 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 22:16:37.726777 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 22:16:37.733085 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 22:16:37.736418 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 22:16:37.739701 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 22:16:37.746548 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 22:16:37.749649 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 22:16:37.753392 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 22:16:37.759753 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 22:16:37.763209 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
918 22:16:37.766393 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
919 22:16:37.773554 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
920 22:16:37.776050 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
921 22:16:37.779988 Total UI for P1: 0, mck2ui 16
922 22:16:37.783183 best dqsien dly found for B0: ( 0, 14, 6)
923 22:16:37.786485 Total UI for P1: 0, mck2ui 16
924 22:16:37.789668 best dqsien dly found for B1: ( 0, 14, 10)
925 22:16:37.793070 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
926 22:16:37.796461 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
927 22:16:37.796882
928 22:16:37.799599 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
929 22:16:37.803320 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
930 22:16:37.806365 [Gating] SW calibration Done
931 22:16:37.806802 ==
932 22:16:37.809594 Dram Type= 6, Freq= 0, CH_0, rank 0
933 22:16:37.813176 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 22:16:37.813262 ==
935 22:16:37.816765 RX Vref Scan: 0
936 22:16:37.816846
937 22:16:37.820147 RX Vref 0 -> 0, step: 1
938 22:16:37.820229
939 22:16:37.820293 RX Delay -130 -> 252, step: 16
940 22:16:37.826522 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
941 22:16:37.830179 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
942 22:16:37.833363 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
943 22:16:37.836960 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
944 22:16:37.841076 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
945 22:16:37.844820 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
946 22:16:37.848532 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
947 22:16:37.851859 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
948 22:16:37.859480 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
949 22:16:37.862969 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
950 22:16:37.866414 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
951 22:16:37.869989 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
952 22:16:37.873299 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
953 22:16:37.877300 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
954 22:16:37.881470 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
955 22:16:37.884645 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
956 22:16:37.884739 ==
957 22:16:37.888210 Dram Type= 6, Freq= 0, CH_0, rank 0
958 22:16:37.892487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
959 22:16:37.892619 ==
960 22:16:37.896481 DQS Delay:
961 22:16:37.896581 DQS0 = 0, DQS1 = 0
962 22:16:37.896665 DQM Delay:
963 22:16:37.900270 DQM0 = 86, DQM1 = 72
964 22:16:37.900382 DQ Delay:
965 22:16:37.903040 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
966 22:16:37.906564 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =93
967 22:16:37.910231 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
968 22:16:37.914107 DQ12 =77, DQ13 =77, DQ14 =85, DQ15 =85
969 22:16:37.914267
970 22:16:37.914396
971 22:16:37.914517 ==
972 22:16:37.918039 Dram Type= 6, Freq= 0, CH_0, rank 0
973 22:16:37.921578 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
974 22:16:37.921756 ==
975 22:16:37.921912
976 22:16:37.922140
977 22:16:37.924725 TX Vref Scan disable
978 22:16:37.924936 == TX Byte 0 ==
979 22:16:37.932090 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
980 22:16:37.935954 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
981 22:16:37.936340 == TX Byte 1 ==
982 22:16:37.939406 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
983 22:16:37.945973 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
984 22:16:37.946393 ==
985 22:16:37.949659 Dram Type= 6, Freq= 0, CH_0, rank 0
986 22:16:37.953643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
987 22:16:37.954229 ==
988 22:16:37.966439 TX Vref=22, minBit 3, minWin=27, winSum=440
989 22:16:37.970061 TX Vref=24, minBit 3, minWin=27, winSum=440
990 22:16:37.973874 TX Vref=26, minBit 8, minWin=27, winSum=445
991 22:16:37.978083 TX Vref=28, minBit 4, minWin=27, winSum=445
992 22:16:37.980739 TX Vref=30, minBit 0, minWin=27, winSum=446
993 22:16:37.984111 TX Vref=32, minBit 0, minWin=27, winSum=442
994 22:16:37.990916 [TxChooseVref] Worse bit 0, Min win 27, Win sum 446, Final Vref 30
995 22:16:37.991440
996 22:16:37.991789 Final TX Range 1 Vref 30
997 22:16:37.992229
998 22:16:37.994092 ==
999 22:16:37.997562 Dram Type= 6, Freq= 0, CH_0, rank 0
1000 22:16:38.000711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1001 22:16:38.001131 ==
1002 22:16:38.001466
1003 22:16:38.001774
1004 22:16:38.004108 TX Vref Scan disable
1005 22:16:38.004528 == TX Byte 0 ==
1006 22:16:38.010775 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1007 22:16:38.014336 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1008 22:16:38.017579 == TX Byte 1 ==
1009 22:16:38.020531 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1010 22:16:38.023951 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1011 22:16:38.024376
1012 22:16:38.024710 [DATLAT]
1013 22:16:38.027524 Freq=800, CH0 RK0
1014 22:16:38.027945
1015 22:16:38.028273 DATLAT Default: 0xa
1016 22:16:38.030741 0, 0xFFFF, sum = 0
1017 22:16:38.031222 1, 0xFFFF, sum = 0
1018 22:16:38.033892 2, 0xFFFF, sum = 0
1019 22:16:38.034318 3, 0xFFFF, sum = 0
1020 22:16:38.037126 4, 0xFFFF, sum = 0
1021 22:16:38.040314 5, 0xFFFF, sum = 0
1022 22:16:38.040742 6, 0xFFFF, sum = 0
1023 22:16:38.043645 7, 0xFFFF, sum = 0
1024 22:16:38.044076 8, 0xFFFF, sum = 0
1025 22:16:38.046978 9, 0x0, sum = 1
1026 22:16:38.047442 10, 0x0, sum = 2
1027 22:16:38.050625 11, 0x0, sum = 3
1028 22:16:38.051045 12, 0x0, sum = 4
1029 22:16:38.051646 best_step = 10
1030 22:16:38.051982
1031 22:16:38.053808 ==
1032 22:16:38.057773 Dram Type= 6, Freq= 0, CH_0, rank 0
1033 22:16:38.060855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1034 22:16:38.061288 ==
1035 22:16:38.061618 RX Vref Scan: 1
1036 22:16:38.061921
1037 22:16:38.063821 Set Vref Range= 32 -> 127
1038 22:16:38.064233
1039 22:16:38.067128 RX Vref 32 -> 127, step: 1
1040 22:16:38.067546
1041 22:16:38.070598 RX Delay -111 -> 252, step: 8
1042 22:16:38.071011
1043 22:16:38.073656 Set Vref, RX VrefLevel [Byte0]: 32
1044 22:16:38.077519 [Byte1]: 32
1045 22:16:38.077934
1046 22:16:38.080381 Set Vref, RX VrefLevel [Byte0]: 33
1047 22:16:38.084103 [Byte1]: 33
1048 22:16:38.084515
1049 22:16:38.087850 Set Vref, RX VrefLevel [Byte0]: 34
1050 22:16:38.090360 [Byte1]: 34
1051 22:16:38.094156
1052 22:16:38.094569 Set Vref, RX VrefLevel [Byte0]: 35
1053 22:16:38.097585 [Byte1]: 35
1054 22:16:38.101525
1055 22:16:38.101940 Set Vref, RX VrefLevel [Byte0]: 36
1056 22:16:38.104832 [Byte1]: 36
1057 22:16:38.110057
1058 22:16:38.110469 Set Vref, RX VrefLevel [Byte0]: 37
1059 22:16:38.112868 [Byte1]: 37
1060 22:16:38.116794
1061 22:16:38.117206 Set Vref, RX VrefLevel [Byte0]: 38
1062 22:16:38.120638 [Byte1]: 38
1063 22:16:38.124707
1064 22:16:38.125117 Set Vref, RX VrefLevel [Byte0]: 39
1065 22:16:38.128019 [Byte1]: 39
1066 22:16:38.132222
1067 22:16:38.132633 Set Vref, RX VrefLevel [Byte0]: 40
1068 22:16:38.135493 [Byte1]: 40
1069 22:16:38.139636
1070 22:16:38.140063 Set Vref, RX VrefLevel [Byte0]: 41
1071 22:16:38.143167 [Byte1]: 41
1072 22:16:38.147511
1073 22:16:38.147921 Set Vref, RX VrefLevel [Byte0]: 42
1074 22:16:38.150925 [Byte1]: 42
1075 22:16:38.155130
1076 22:16:38.155541 Set Vref, RX VrefLevel [Byte0]: 43
1077 22:16:38.158437 [Byte1]: 43
1078 22:16:38.162829
1079 22:16:38.163273 Set Vref, RX VrefLevel [Byte0]: 44
1080 22:16:38.166135 [Byte1]: 44
1081 22:16:38.170764
1082 22:16:38.171224 Set Vref, RX VrefLevel [Byte0]: 45
1083 22:16:38.174222 [Byte1]: 45
1084 22:16:38.178364
1085 22:16:38.178775 Set Vref, RX VrefLevel [Byte0]: 46
1086 22:16:38.181295 [Byte1]: 46
1087 22:16:38.185810
1088 22:16:38.186222 Set Vref, RX VrefLevel [Byte0]: 47
1089 22:16:38.189206 [Byte1]: 47
1090 22:16:38.193431
1091 22:16:38.193841 Set Vref, RX VrefLevel [Byte0]: 48
1092 22:16:38.196738 [Byte1]: 48
1093 22:16:38.200993
1094 22:16:38.201405 Set Vref, RX VrefLevel [Byte0]: 49
1095 22:16:38.204170 [Byte1]: 49
1096 22:16:38.208740
1097 22:16:38.209149 Set Vref, RX VrefLevel [Byte0]: 50
1098 22:16:38.211926 [Byte1]: 50
1099 22:16:38.216243
1100 22:16:38.216652 Set Vref, RX VrefLevel [Byte0]: 51
1101 22:16:38.220496 [Byte1]: 51
1102 22:16:38.223809
1103 22:16:38.224219 Set Vref, RX VrefLevel [Byte0]: 52
1104 22:16:38.227567 [Byte1]: 52
1105 22:16:38.232137
1106 22:16:38.232551 Set Vref, RX VrefLevel [Byte0]: 53
1107 22:16:38.238292 [Byte1]: 53
1108 22:16:38.238703
1109 22:16:38.241112 Set Vref, RX VrefLevel [Byte0]: 54
1110 22:16:38.245047 [Byte1]: 54
1111 22:16:38.245460
1112 22:16:38.248240 Set Vref, RX VrefLevel [Byte0]: 55
1113 22:16:38.251630 [Byte1]: 55
1114 22:16:38.254731
1115 22:16:38.255180 Set Vref, RX VrefLevel [Byte0]: 56
1116 22:16:38.257984 [Byte1]: 56
1117 22:16:38.262121
1118 22:16:38.262534 Set Vref, RX VrefLevel [Byte0]: 57
1119 22:16:38.265483 [Byte1]: 57
1120 22:16:38.269982
1121 22:16:38.270391 Set Vref, RX VrefLevel [Byte0]: 58
1122 22:16:38.273422 [Byte1]: 58
1123 22:16:38.277195
1124 22:16:38.277607 Set Vref, RX VrefLevel [Byte0]: 59
1125 22:16:38.280659 [Byte1]: 59
1126 22:16:38.284784
1127 22:16:38.285194 Set Vref, RX VrefLevel [Byte0]: 60
1128 22:16:38.288405 [Byte1]: 60
1129 22:16:38.292486
1130 22:16:38.292898 Set Vref, RX VrefLevel [Byte0]: 61
1131 22:16:38.296282 [Byte1]: 61
1132 22:16:38.301003
1133 22:16:38.301415 Set Vref, RX VrefLevel [Byte0]: 62
1134 22:16:38.304214 [Byte1]: 62
1135 22:16:38.307924
1136 22:16:38.308342 Set Vref, RX VrefLevel [Byte0]: 63
1137 22:16:38.311599 [Byte1]: 63
1138 22:16:38.315687
1139 22:16:38.316098 Set Vref, RX VrefLevel [Byte0]: 64
1140 22:16:38.318789 [Byte1]: 64
1141 22:16:38.323294
1142 22:16:38.323705 Set Vref, RX VrefLevel [Byte0]: 65
1143 22:16:38.326699 [Byte1]: 65
1144 22:16:38.330932
1145 22:16:38.331376 Set Vref, RX VrefLevel [Byte0]: 66
1146 22:16:38.334446 [Byte1]: 66
1147 22:16:38.338527
1148 22:16:38.338939 Set Vref, RX VrefLevel [Byte0]: 67
1149 22:16:38.342086 [Byte1]: 67
1150 22:16:38.345974
1151 22:16:38.346384 Set Vref, RX VrefLevel [Byte0]: 68
1152 22:16:38.349519 [Byte1]: 68
1153 22:16:38.354358
1154 22:16:38.354773 Set Vref, RX VrefLevel [Byte0]: 69
1155 22:16:38.357637 [Byte1]: 69
1156 22:16:38.361947
1157 22:16:38.362361 Set Vref, RX VrefLevel [Byte0]: 70
1158 22:16:38.365128 [Byte1]: 70
1159 22:16:38.369722
1160 22:16:38.370138 Set Vref, RX VrefLevel [Byte0]: 71
1161 22:16:38.373103 [Byte1]: 71
1162 22:16:38.376990
1163 22:16:38.377381 Set Vref, RX VrefLevel [Byte0]: 72
1164 22:16:38.381310 [Byte1]: 72
1165 22:16:38.384809
1166 22:16:38.385221 Set Vref, RX VrefLevel [Byte0]: 73
1167 22:16:38.388338 [Byte1]: 73
1168 22:16:38.392659
1169 22:16:38.393086 Set Vref, RX VrefLevel [Byte0]: 74
1170 22:16:38.396062 [Byte1]: 74
1171 22:16:38.399886
1172 22:16:38.400312 Set Vref, RX VrefLevel [Byte0]: 75
1173 22:16:38.403534 [Byte1]: 75
1174 22:16:38.407920
1175 22:16:38.408344 Set Vref, RX VrefLevel [Byte0]: 76
1176 22:16:38.411169 [Byte1]: 76
1177 22:16:38.415693
1178 22:16:38.416114 Set Vref, RX VrefLevel [Byte0]: 77
1179 22:16:38.418822 [Byte1]: 77
1180 22:16:38.422789
1181 22:16:38.423252 Set Vref, RX VrefLevel [Byte0]: 78
1182 22:16:38.426316 [Byte1]: 78
1183 22:16:38.430735
1184 22:16:38.431198 Set Vref, RX VrefLevel [Byte0]: 79
1185 22:16:38.433518 [Byte1]: 79
1186 22:16:38.438443
1187 22:16:38.438866 Set Vref, RX VrefLevel [Byte0]: 80
1188 22:16:38.442076 [Byte1]: 80
1189 22:16:38.446119
1190 22:16:38.446638 Final RX Vref Byte 0 = 61 to rank0
1191 22:16:38.449866 Final RX Vref Byte 1 = 59 to rank0
1192 22:16:38.453468 Final RX Vref Byte 0 = 61 to rank1
1193 22:16:38.456987 Final RX Vref Byte 1 = 59 to rank1==
1194 22:16:38.460696 Dram Type= 6, Freq= 0, CH_0, rank 0
1195 22:16:38.464112 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1196 22:16:38.464556 ==
1197 22:16:38.465050 DQS Delay:
1198 22:16:38.467600 DQS0 = 0, DQS1 = 0
1199 22:16:38.468014 DQM Delay:
1200 22:16:38.471440 DQM0 = 86, DQM1 = 75
1201 22:16:38.471857 DQ Delay:
1202 22:16:38.474963 DQ0 =84, DQ1 =92, DQ2 =84, DQ3 =80
1203 22:16:38.478745 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96
1204 22:16:38.481986 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =68
1205 22:16:38.482478 DQ12 =80, DQ13 =80, DQ14 =84, DQ15 =84
1206 22:16:38.486373
1207 22:16:38.486823
1208 22:16:38.493291 [DQSOSCAuto] RK0, (LSB)MR18= 0x4627, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 392 ps
1209 22:16:38.496273 CH0 RK0: MR19=606, MR18=4627
1210 22:16:38.499940 CH0_RK0: MR19=0x606, MR18=0x4627, DQSOSC=392, MR23=63, INC=96, DEC=64
1211 22:16:38.500362
1212 22:16:38.503036 ----->DramcWriteLeveling(PI) begin...
1213 22:16:38.506220 ==
1214 22:16:38.506637 Dram Type= 6, Freq= 0, CH_0, rank 1
1215 22:16:38.512918 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1216 22:16:38.513423 ==
1217 22:16:38.516524 Write leveling (Byte 0): 31 => 31
1218 22:16:38.520319 Write leveling (Byte 1): 31 => 31
1219 22:16:38.522882 DramcWriteLeveling(PI) end<-----
1220 22:16:38.523406
1221 22:16:38.523801 ==
1222 22:16:38.526498 Dram Type= 6, Freq= 0, CH_0, rank 1
1223 22:16:38.530894 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1224 22:16:38.531434 ==
1225 22:16:38.533924 [Gating] SW mode calibration
1226 22:16:38.581881 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1227 22:16:38.582323 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1228 22:16:38.583029 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1229 22:16:38.583794 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1230 22:16:38.584206 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 22:16:38.584586 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 22:16:38.584898 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 22:16:38.585247 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 22:16:38.585583 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 22:16:38.586032 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 22:16:38.625730 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 22:16:38.626149 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 22:16:38.626478 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 22:16:38.627145 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 22:16:38.627526 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 22:16:38.627857 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 22:16:38.628148 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 22:16:38.628507 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 22:16:38.628872 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 22:16:38.629164 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1246 22:16:38.651751 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1247 22:16:38.652554 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1248 22:16:38.653313 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1249 22:16:38.653766 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1250 22:16:38.654105 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1251 22:16:38.655853 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1252 22:16:38.656273 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1253 22:16:38.659163 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1254 22:16:38.662159 0 9 8 | B1->B0 | 2424 2b2b | 0 0 | (0 0) (0 0)
1255 22:16:38.668846 0 9 12 | B1->B0 | 3231 3434 | 1 1 | (0 0) (1 1)
1256 22:16:38.672285 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1257 22:16:38.675977 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1258 22:16:38.681868 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1259 22:16:38.685270 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1260 22:16:38.688515 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1261 22:16:38.695268 0 10 4 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
1262 22:16:38.698637 0 10 8 | B1->B0 | 2f2f 2929 | 0 0 | (0 0) (0 0)
1263 22:16:38.702069 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1264 22:16:38.708662 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1265 22:16:38.712129 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1266 22:16:38.714881 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1267 22:16:38.721643 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1268 22:16:38.725200 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1269 22:16:38.728336 0 11 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1270 22:16:38.734570 0 11 8 | B1->B0 | 3030 3a3a | 0 1 | (1 1) (0 0)
1271 22:16:38.737752 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1272 22:16:38.741252 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1273 22:16:38.748088 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1274 22:16:38.750780 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1275 22:16:38.754309 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1276 22:16:38.761222 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1277 22:16:38.764453 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1278 22:16:38.767582 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1279 22:16:38.774446 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1280 22:16:38.777374 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1281 22:16:38.780719 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1282 22:16:38.787953 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1283 22:16:38.791141 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1284 22:16:38.794056 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1285 22:16:38.800382 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1286 22:16:38.803914 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1287 22:16:38.807636 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1288 22:16:38.814012 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1289 22:16:38.817329 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1290 22:16:38.820388 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1291 22:16:38.827234 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1292 22:16:38.830762 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1293 22:16:38.833582 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1294 22:16:38.840199 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1295 22:16:38.843898 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1296 22:16:38.846927 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1297 22:16:38.850561 Total UI for P1: 0, mck2ui 16
1298 22:16:38.853696 best dqsien dly found for B0: ( 0, 14, 8)
1299 22:16:38.857142 Total UI for P1: 0, mck2ui 16
1300 22:16:38.860473 best dqsien dly found for B1: ( 0, 14, 8)
1301 22:16:38.863701 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1302 22:16:38.867246 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1303 22:16:38.867658
1304 22:16:38.870312 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1305 22:16:38.876895 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1306 22:16:38.877308 [Gating] SW calibration Done
1307 22:16:38.877632 ==
1308 22:16:38.880474 Dram Type= 6, Freq= 0, CH_0, rank 1
1309 22:16:38.886697 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1310 22:16:38.887150 ==
1311 22:16:38.887482 RX Vref Scan: 0
1312 22:16:38.887788
1313 22:16:38.889981 RX Vref 0 -> 0, step: 1
1314 22:16:38.890434
1315 22:16:38.893691 RX Delay -130 -> 252, step: 16
1316 22:16:38.896976 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1317 22:16:38.899919 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1318 22:16:38.903303 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1319 22:16:38.909860 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1320 22:16:38.913294 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1321 22:16:38.916370 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1322 22:16:38.919564 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1323 22:16:38.923260 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1324 22:16:38.929703 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1325 22:16:38.932863 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1326 22:16:38.936631 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1327 22:16:38.939732 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1328 22:16:38.943214 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1329 22:16:38.949335 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1330 22:16:38.952729 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1331 22:16:38.956516 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1332 22:16:38.956928 ==
1333 22:16:38.959558 Dram Type= 6, Freq= 0, CH_0, rank 1
1334 22:16:38.963222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1335 22:16:38.966136 ==
1336 22:16:38.966549 DQS Delay:
1337 22:16:38.966875 DQS0 = 0, DQS1 = 0
1338 22:16:38.969653 DQM Delay:
1339 22:16:38.970063 DQM0 = 87, DQM1 = 79
1340 22:16:38.973133 DQ Delay:
1341 22:16:38.976474 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =77
1342 22:16:38.976887 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =101
1343 22:16:38.979692 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1344 22:16:38.986180 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
1345 22:16:38.986702
1346 22:16:38.987027
1347 22:16:38.987359 ==
1348 22:16:38.989373 Dram Type= 6, Freq= 0, CH_0, rank 1
1349 22:16:38.992843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1350 22:16:38.993312 ==
1351 22:16:38.993638
1352 22:16:38.993938
1353 22:16:38.996202 TX Vref Scan disable
1354 22:16:38.996613 == TX Byte 0 ==
1355 22:16:39.002908 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1356 22:16:39.005987 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1357 22:16:39.006401 == TX Byte 1 ==
1358 22:16:39.012526 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1359 22:16:39.015540 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1360 22:16:39.015991 ==
1361 22:16:39.019177 Dram Type= 6, Freq= 0, CH_0, rank 1
1362 22:16:39.022437 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1363 22:16:39.022842 ==
1364 22:16:39.036576 TX Vref=22, minBit 12, minWin=27, winSum=446
1365 22:16:39.040452 TX Vref=24, minBit 9, minWin=27, winSum=448
1366 22:16:39.044172 TX Vref=26, minBit 9, minWin=27, winSum=449
1367 22:16:39.047413 TX Vref=28, minBit 9, minWin=27, winSum=450
1368 22:16:39.050880 TX Vref=30, minBit 9, minWin=27, winSum=447
1369 22:16:39.054776 TX Vref=32, minBit 9, minWin=27, winSum=445
1370 22:16:39.062399 [TxChooseVref] Worse bit 9, Min win 27, Win sum 450, Final Vref 28
1371 22:16:39.062813
1372 22:16:39.063177 Final TX Range 1 Vref 28
1373 22:16:39.063480
1374 22:16:39.065429 ==
1375 22:16:39.065830 Dram Type= 6, Freq= 0, CH_0, rank 1
1376 22:16:39.072388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1377 22:16:39.073021 ==
1378 22:16:39.073483
1379 22:16:39.073796
1380 22:16:39.074081 TX Vref Scan disable
1381 22:16:39.076519 == TX Byte 0 ==
1382 22:16:39.079472 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1383 22:16:39.082864 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1384 22:16:39.086868 == TX Byte 1 ==
1385 22:16:39.090436 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1386 22:16:39.094608 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1387 22:16:39.095141
1388 22:16:39.095690 [DATLAT]
1389 22:16:39.097922 Freq=800, CH0 RK1
1390 22:16:39.098490
1391 22:16:39.099012 DATLAT Default: 0xa
1392 22:16:39.101563 0, 0xFFFF, sum = 0
1393 22:16:39.102011 1, 0xFFFF, sum = 0
1394 22:16:39.105101 2, 0xFFFF, sum = 0
1395 22:16:39.105516 3, 0xFFFF, sum = 0
1396 22:16:39.108579 4, 0xFFFF, sum = 0
1397 22:16:39.109237 5, 0xFFFF, sum = 0
1398 22:16:39.112539 6, 0xFFFF, sum = 0
1399 22:16:39.113075 7, 0xFFFF, sum = 0
1400 22:16:39.115144 8, 0xFFFF, sum = 0
1401 22:16:39.115552 9, 0x0, sum = 1
1402 22:16:39.119257 10, 0x0, sum = 2
1403 22:16:39.119668 11, 0x0, sum = 3
1404 22:16:39.119993 12, 0x0, sum = 4
1405 22:16:39.122981 best_step = 10
1406 22:16:39.123423
1407 22:16:39.123737 ==
1408 22:16:39.126630 Dram Type= 6, Freq= 0, CH_0, rank 1
1409 22:16:39.130390 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1410 22:16:39.130793 ==
1411 22:16:39.131134 RX Vref Scan: 0
1412 22:16:39.131432
1413 22:16:39.133924 RX Vref 0 -> 0, step: 1
1414 22:16:39.134324
1415 22:16:39.137494 RX Delay -95 -> 252, step: 8
1416 22:16:39.141241 iDelay=209, Bit 0, Center 80 (-31 ~ 192) 224
1417 22:16:39.144978 iDelay=209, Bit 1, Center 92 (-23 ~ 208) 232
1418 22:16:39.148341 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1419 22:16:39.152015 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1420 22:16:39.159646 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
1421 22:16:39.163538 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1422 22:16:39.167257 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1423 22:16:39.171012 iDelay=209, Bit 7, Center 92 (-23 ~ 208) 232
1424 22:16:39.174651 iDelay=209, Bit 8, Center 68 (-47 ~ 184) 232
1425 22:16:39.178057 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1426 22:16:39.181835 iDelay=209, Bit 10, Center 80 (-39 ~ 200) 240
1427 22:16:39.185205 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
1428 22:16:39.188793 iDelay=209, Bit 12, Center 84 (-31 ~ 200) 232
1429 22:16:39.192952 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
1430 22:16:39.196365 iDelay=209, Bit 14, Center 84 (-31 ~ 200) 232
1431 22:16:39.204147 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1432 22:16:39.204550 ==
1433 22:16:39.204867 Dram Type= 6, Freq= 0, CH_0, rank 1
1434 22:16:39.210943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1435 22:16:39.211381 ==
1436 22:16:39.211725 DQS Delay:
1437 22:16:39.212024 DQS0 = 0, DQS1 = 0
1438 22:16:39.214551 DQM Delay:
1439 22:16:39.214953 DQM0 = 85, DQM1 = 77
1440 22:16:39.218208 DQ Delay:
1441 22:16:39.218612 DQ0 =80, DQ1 =92, DQ2 =80, DQ3 =84
1442 22:16:39.221913 DQ4 =84, DQ5 =76, DQ6 =92, DQ7 =92
1443 22:16:39.225763 DQ8 =68, DQ9 =64, DQ10 =80, DQ11 =68
1444 22:16:39.229032 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
1445 22:16:39.229437
1446 22:16:39.229756
1447 22:16:39.237060 [DQSOSCAuto] RK1, (LSB)MR18= 0x4309, (MSB)MR19= 0x606, tDQSOscB0 = 407 ps tDQSOscB1 = 393 ps
1448 22:16:39.240140 CH0 RK1: MR19=606, MR18=4309
1449 22:16:39.247712 CH0_RK1: MR19=0x606, MR18=0x4309, DQSOSC=393, MR23=63, INC=95, DEC=63
1450 22:16:39.251199 [RxdqsGatingPostProcess] freq 800
1451 22:16:39.255044 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1452 22:16:39.258423 Pre-setting of DQS Precalculation
1453 22:16:39.262289 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1454 22:16:39.262700 ==
1455 22:16:39.265913 Dram Type= 6, Freq= 0, CH_1, rank 0
1456 22:16:39.269719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1457 22:16:39.270129 ==
1458 22:16:39.276698 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1459 22:16:39.283817 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1460 22:16:39.292020 [CA 0] Center 36 (6~67) winsize 62
1461 22:16:39.294874 [CA 1] Center 36 (6~67) winsize 62
1462 22:16:39.298059 [CA 2] Center 34 (4~65) winsize 62
1463 22:16:39.301922 [CA 3] Center 34 (3~65) winsize 63
1464 22:16:39.305688 [CA 4] Center 34 (4~65) winsize 62
1465 22:16:39.309243 [CA 5] Center 34 (3~65) winsize 63
1466 22:16:39.309684
1467 22:16:39.313084 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1468 22:16:39.313513
1469 22:16:39.316704 [CATrainingPosCal] consider 1 rank data
1470 22:16:39.320775 u2DelayCellTimex100 = 270/100 ps
1471 22:16:39.323904 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1472 22:16:39.327993 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1473 22:16:39.331870 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1474 22:16:39.335148 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1475 22:16:39.335578 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1476 22:16:39.342797 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1477 22:16:39.343254
1478 22:16:39.346266 CA PerBit enable=1, Macro0, CA PI delay=34
1479 22:16:39.346690
1480 22:16:39.347149 [CBTSetCACLKResult] CA Dly = 34
1481 22:16:39.349484 CS Dly: 5 (0~36)
1482 22:16:39.349905 ==
1483 22:16:39.352762 Dram Type= 6, Freq= 0, CH_1, rank 1
1484 22:16:39.356122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1485 22:16:39.356537 ==
1486 22:16:39.362633 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1487 22:16:39.369344 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1488 22:16:39.377549 [CA 0] Center 36 (6~67) winsize 62
1489 22:16:39.380893 [CA 1] Center 37 (6~68) winsize 63
1490 22:16:39.383819 [CA 2] Center 34 (4~65) winsize 62
1491 22:16:39.387479 [CA 3] Center 34 (3~65) winsize 63
1492 22:16:39.390782 [CA 4] Center 34 (4~65) winsize 62
1493 22:16:39.394052 [CA 5] Center 33 (3~64) winsize 62
1494 22:16:39.394478
1495 22:16:39.397305 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1496 22:16:39.397730
1497 22:16:39.400493 [CATrainingPosCal] consider 2 rank data
1498 22:16:39.404021 u2DelayCellTimex100 = 270/100 ps
1499 22:16:39.407384 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1500 22:16:39.413764 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1501 22:16:39.416848 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1502 22:16:39.420639 CA3 delay=34 (3~65),Diff = 1 PI (7 cell)
1503 22:16:39.423578 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1504 22:16:39.426733 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1505 22:16:39.427198
1506 22:16:39.430535 CA PerBit enable=1, Macro0, CA PI delay=33
1507 22:16:39.430960
1508 22:16:39.433617 [CBTSetCACLKResult] CA Dly = 33
1509 22:16:39.436750 CS Dly: 6 (0~38)
1510 22:16:39.437172
1511 22:16:39.440153 ----->DramcWriteLeveling(PI) begin...
1512 22:16:39.440582 ==
1513 22:16:39.443926 Dram Type= 6, Freq= 0, CH_1, rank 0
1514 22:16:39.446705 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1515 22:16:39.447186 ==
1516 22:16:39.450231 Write leveling (Byte 0): 28 => 28
1517 22:16:39.453565 Write leveling (Byte 1): 28 => 28
1518 22:16:39.456733 DramcWriteLeveling(PI) end<-----
1519 22:16:39.457157
1520 22:16:39.457577 ==
1521 22:16:39.460206 Dram Type= 6, Freq= 0, CH_1, rank 0
1522 22:16:39.463230 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1523 22:16:39.463676 ==
1524 22:16:39.466647 [Gating] SW mode calibration
1525 22:16:39.473852 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1526 22:16:39.480259 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1527 22:16:39.483374 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1528 22:16:39.486494 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1529 22:16:39.493437 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 22:16:39.496920 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 22:16:39.500065 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 22:16:39.506690 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 22:16:39.509958 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 22:16:39.513019 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 22:16:39.520100 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 22:16:39.523247 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 22:16:39.526859 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 22:16:39.532742 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 22:16:39.536680 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 22:16:39.539993 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 22:16:39.546162 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 22:16:39.549561 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 22:16:39.553253 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1544 22:16:39.556654 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1545 22:16:39.562759 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1546 22:16:39.566124 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1547 22:16:39.569374 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1548 22:16:39.576715 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1549 22:16:39.579976 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1550 22:16:39.582728 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1551 22:16:39.589546 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1552 22:16:39.593260 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1553 22:16:39.595964 0 9 8 | B1->B0 | 2f2f 3232 | 1 1 | (1 1) (1 1)
1554 22:16:39.602640 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1555 22:16:39.606001 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1556 22:16:39.609419 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1557 22:16:39.616171 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1558 22:16:39.619498 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1559 22:16:39.623184 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1560 22:16:39.629280 0 10 4 | B1->B0 | 3333 3232 | 0 0 | (0 0) (0 1)
1561 22:16:39.632970 0 10 8 | B1->B0 | 2828 2626 | 0 0 | (0 0) (0 0)
1562 22:16:39.635904 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1563 22:16:39.642445 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1564 22:16:39.646223 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1565 22:16:39.649702 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1566 22:16:39.656136 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1567 22:16:39.659331 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1568 22:16:39.662609 0 11 4 | B1->B0 | 2828 2a2a | 0 1 | (0 0) (0 0)
1569 22:16:39.669061 0 11 8 | B1->B0 | 3939 4241 | 1 1 | (0 0) (0 0)
1570 22:16:39.672530 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1571 22:16:39.675639 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1572 22:16:39.682234 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1573 22:16:39.685917 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1574 22:16:39.688926 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1575 22:16:39.695708 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1576 22:16:39.698843 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1577 22:16:39.702390 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1578 22:16:39.709393 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1579 22:16:39.712575 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1580 22:16:39.715520 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1581 22:16:39.719431 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1582 22:16:39.725828 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1583 22:16:39.728795 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1584 22:16:39.732463 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1585 22:16:39.739166 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1586 22:16:39.742422 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1587 22:16:39.745703 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1588 22:16:39.752325 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1589 22:16:39.755432 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1590 22:16:39.759265 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1591 22:16:39.765311 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1592 22:16:39.769013 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1593 22:16:39.772242 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1594 22:16:39.775133 Total UI for P1: 0, mck2ui 16
1595 22:16:39.778633 best dqsien dly found for B0: ( 0, 14, 2)
1596 22:16:39.785661 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1597 22:16:39.786089 Total UI for P1: 0, mck2ui 16
1598 22:16:39.791917 best dqsien dly found for B1: ( 0, 14, 6)
1599 22:16:39.794986 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1600 22:16:39.798418 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1601 22:16:39.798889
1602 22:16:39.801733 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1603 22:16:39.804966 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1604 22:16:39.808330 [Gating] SW calibration Done
1605 22:16:39.808759 ==
1606 22:16:39.811926 Dram Type= 6, Freq= 0, CH_1, rank 0
1607 22:16:39.814825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1608 22:16:39.815302 ==
1609 22:16:39.818293 RX Vref Scan: 0
1610 22:16:39.818714
1611 22:16:39.819179 RX Vref 0 -> 0, step: 1
1612 22:16:39.819585
1613 22:16:39.821284 RX Delay -130 -> 252, step: 16
1614 22:16:39.828533 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1615 22:16:39.831467 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1616 22:16:39.834736 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1617 22:16:39.837808 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1618 22:16:39.841308 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1619 22:16:39.847869 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1620 22:16:39.851335 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1621 22:16:39.854428 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1622 22:16:39.857933 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1623 22:16:39.861617 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1624 22:16:39.868058 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1625 22:16:39.871162 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1626 22:16:39.874649 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1627 22:16:39.877983 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1628 22:16:39.884574 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1629 22:16:39.888008 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1630 22:16:39.888456 ==
1631 22:16:39.891020 Dram Type= 6, Freq= 0, CH_1, rank 0
1632 22:16:39.894706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1633 22:16:39.895158 ==
1634 22:16:39.895486 DQS Delay:
1635 22:16:39.897704 DQS0 = 0, DQS1 = 0
1636 22:16:39.898111 DQM Delay:
1637 22:16:39.900943 DQM0 = 89, DQM1 = 79
1638 22:16:39.901464 DQ Delay:
1639 22:16:39.904312 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =85
1640 22:16:39.907406 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1641 22:16:39.910907 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1642 22:16:39.915008 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1643 22:16:39.915576
1644 22:16:39.915904
1645 22:16:39.916280 ==
1646 22:16:39.917339 Dram Type= 6, Freq= 0, CH_1, rank 0
1647 22:16:39.921197 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1648 22:16:39.924210 ==
1649 22:16:39.924616
1650 22:16:39.924933
1651 22:16:39.925231 TX Vref Scan disable
1652 22:16:39.927403 == TX Byte 0 ==
1653 22:16:39.930753 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1654 22:16:39.934049 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1655 22:16:39.937356 == TX Byte 1 ==
1656 22:16:39.940201 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1657 22:16:39.946936 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1658 22:16:39.947049 ==
1659 22:16:39.950195 Dram Type= 6, Freq= 0, CH_1, rank 0
1660 22:16:39.953225 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1661 22:16:39.953305 ==
1662 22:16:39.965908 TX Vref=22, minBit 8, minWin=27, winSum=443
1663 22:16:39.969177 TX Vref=24, minBit 9, minWin=27, winSum=447
1664 22:16:39.972613 TX Vref=26, minBit 9, minWin=27, winSum=449
1665 22:16:39.976178 TX Vref=28, minBit 9, minWin=27, winSum=448
1666 22:16:39.979722 TX Vref=30, minBit 10, minWin=27, winSum=451
1667 22:16:39.986513 TX Vref=32, minBit 8, minWin=27, winSum=446
1668 22:16:39.989239 [TxChooseVref] Worse bit 10, Min win 27, Win sum 451, Final Vref 30
1669 22:16:39.989362
1670 22:16:39.992579 Final TX Range 1 Vref 30
1671 22:16:39.992697
1672 22:16:39.992812 ==
1673 22:16:39.996152 Dram Type= 6, Freq= 0, CH_1, rank 0
1674 22:16:39.998851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1675 22:16:40.002387 ==
1676 22:16:40.002466
1677 22:16:40.002528
1678 22:16:40.002586 TX Vref Scan disable
1679 22:16:40.005777 == TX Byte 0 ==
1680 22:16:40.009427 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1681 22:16:40.015787 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1682 22:16:40.015867 == TX Byte 1 ==
1683 22:16:40.019389 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1684 22:16:40.025573 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1685 22:16:40.025651
1686 22:16:40.025713 [DATLAT]
1687 22:16:40.025770 Freq=800, CH1 RK0
1688 22:16:40.025826
1689 22:16:40.028877 DATLAT Default: 0xa
1690 22:16:40.028955 0, 0xFFFF, sum = 0
1691 22:16:40.032427 1, 0xFFFF, sum = 0
1692 22:16:40.035612 2, 0xFFFF, sum = 0
1693 22:16:40.035692 3, 0xFFFF, sum = 0
1694 22:16:40.038733 4, 0xFFFF, sum = 0
1695 22:16:40.038814 5, 0xFFFF, sum = 0
1696 22:16:40.042304 6, 0xFFFF, sum = 0
1697 22:16:40.042384 7, 0xFFFF, sum = 0
1698 22:16:40.045570 8, 0xFFFF, sum = 0
1699 22:16:40.045651 9, 0x0, sum = 1
1700 22:16:40.049024 10, 0x0, sum = 2
1701 22:16:40.049104 11, 0x0, sum = 3
1702 22:16:40.051871 12, 0x0, sum = 4
1703 22:16:40.051951 best_step = 10
1704 22:16:40.052013
1705 22:16:40.052071 ==
1706 22:16:40.055428 Dram Type= 6, Freq= 0, CH_1, rank 0
1707 22:16:40.058531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1708 22:16:40.058644 ==
1709 22:16:40.061925 RX Vref Scan: 1
1710 22:16:40.062047
1711 22:16:40.065142 Set Vref Range= 32 -> 127
1712 22:16:40.065247
1713 22:16:40.065312 RX Vref 32 -> 127, step: 1
1714 22:16:40.065372
1715 22:16:40.068717 RX Delay -95 -> 252, step: 8
1716 22:16:40.068823
1717 22:16:40.071915 Set Vref, RX VrefLevel [Byte0]: 32
1718 22:16:40.075141 [Byte1]: 32
1719 22:16:40.079015
1720 22:16:40.079140 Set Vref, RX VrefLevel [Byte0]: 33
1721 22:16:40.082248 [Byte1]: 33
1722 22:16:40.086494
1723 22:16:40.086575 Set Vref, RX VrefLevel [Byte0]: 34
1724 22:16:40.089593 [Byte1]: 34
1725 22:16:40.093804
1726 22:16:40.093884 Set Vref, RX VrefLevel [Byte0]: 35
1727 22:16:40.097173 [Byte1]: 35
1728 22:16:40.101455
1729 22:16:40.101535 Set Vref, RX VrefLevel [Byte0]: 36
1730 22:16:40.105376 [Byte1]: 36
1731 22:16:40.109050
1732 22:16:40.109131 Set Vref, RX VrefLevel [Byte0]: 37
1733 22:16:40.112366 [Byte1]: 37
1734 22:16:40.116527
1735 22:16:40.116607 Set Vref, RX VrefLevel [Byte0]: 38
1736 22:16:40.120107 [Byte1]: 38
1737 22:16:40.124493
1738 22:16:40.124574 Set Vref, RX VrefLevel [Byte0]: 39
1739 22:16:40.127584 [Byte1]: 39
1740 22:16:40.131813
1741 22:16:40.131894 Set Vref, RX VrefLevel [Byte0]: 40
1742 22:16:40.135708 [Byte1]: 40
1743 22:16:40.139696
1744 22:16:40.139776 Set Vref, RX VrefLevel [Byte0]: 41
1745 22:16:40.143336 [Byte1]: 41
1746 22:16:40.146837
1747 22:16:40.146917 Set Vref, RX VrefLevel [Byte0]: 42
1748 22:16:40.150354 [Byte1]: 42
1749 22:16:40.154717
1750 22:16:40.154798 Set Vref, RX VrefLevel [Byte0]: 43
1751 22:16:40.157818 [Byte1]: 43
1752 22:16:40.162824
1753 22:16:40.162904 Set Vref, RX VrefLevel [Byte0]: 44
1754 22:16:40.165551 [Byte1]: 44
1755 22:16:40.169995
1756 22:16:40.170075 Set Vref, RX VrefLevel [Byte0]: 45
1757 22:16:40.173364 [Byte1]: 45
1758 22:16:40.177466
1759 22:16:40.177565 Set Vref, RX VrefLevel [Byte0]: 46
1760 22:16:40.180860 [Byte1]: 46
1761 22:16:40.185217
1762 22:16:40.185291 Set Vref, RX VrefLevel [Byte0]: 47
1763 22:16:40.188544 [Byte1]: 47
1764 22:16:40.192538
1765 22:16:40.192607 Set Vref, RX VrefLevel [Byte0]: 48
1766 22:16:40.196465 [Byte1]: 48
1767 22:16:40.200327
1768 22:16:40.200422 Set Vref, RX VrefLevel [Byte0]: 49
1769 22:16:40.203392 [Byte1]: 49
1770 22:16:40.208022
1771 22:16:40.208094 Set Vref, RX VrefLevel [Byte0]: 50
1772 22:16:40.211633 [Byte1]: 50
1773 22:16:40.215366
1774 22:16:40.215435 Set Vref, RX VrefLevel [Byte0]: 51
1775 22:16:40.218980 [Byte1]: 51
1776 22:16:40.223161
1777 22:16:40.223265 Set Vref, RX VrefLevel [Byte0]: 52
1778 22:16:40.226225 [Byte1]: 52
1779 22:16:40.230774
1780 22:16:40.230873 Set Vref, RX VrefLevel [Byte0]: 53
1781 22:16:40.234015 [Byte1]: 53
1782 22:16:40.238304
1783 22:16:40.238375 Set Vref, RX VrefLevel [Byte0]: 54
1784 22:16:40.241906 [Byte1]: 54
1785 22:16:40.245791
1786 22:16:40.245888 Set Vref, RX VrefLevel [Byte0]: 55
1787 22:16:40.249256 [Byte1]: 55
1788 22:16:40.253602
1789 22:16:40.253700 Set Vref, RX VrefLevel [Byte0]: 56
1790 22:16:40.256662 [Byte1]: 56
1791 22:16:40.260993
1792 22:16:40.261094 Set Vref, RX VrefLevel [Byte0]: 57
1793 22:16:40.264611 [Byte1]: 57
1794 22:16:40.268430
1795 22:16:40.268544 Set Vref, RX VrefLevel [Byte0]: 58
1796 22:16:40.272222 [Byte1]: 58
1797 22:16:40.276438
1798 22:16:40.276537 Set Vref, RX VrefLevel [Byte0]: 59
1799 22:16:40.279490 [Byte1]: 59
1800 22:16:40.283928
1801 22:16:40.283997 Set Vref, RX VrefLevel [Byte0]: 60
1802 22:16:40.287052 [Byte1]: 60
1803 22:16:40.291185
1804 22:16:40.291292 Set Vref, RX VrefLevel [Byte0]: 61
1805 22:16:40.295021 [Byte1]: 61
1806 22:16:40.299272
1807 22:16:40.299355 Set Vref, RX VrefLevel [Byte0]: 62
1808 22:16:40.302048 [Byte1]: 62
1809 22:16:40.307015
1810 22:16:40.307133 Set Vref, RX VrefLevel [Byte0]: 63
1811 22:16:40.310199 [Byte1]: 63
1812 22:16:40.314092
1813 22:16:40.314172 Set Vref, RX VrefLevel [Byte0]: 64
1814 22:16:40.317204 [Byte1]: 64
1815 22:16:40.322050
1816 22:16:40.322130 Set Vref, RX VrefLevel [Byte0]: 65
1817 22:16:40.324922 [Byte1]: 65
1818 22:16:40.329448
1819 22:16:40.329528 Set Vref, RX VrefLevel [Byte0]: 66
1820 22:16:40.332791 [Byte1]: 66
1821 22:16:40.336964
1822 22:16:40.337043 Set Vref, RX VrefLevel [Byte0]: 67
1823 22:16:40.340436 [Byte1]: 67
1824 22:16:40.344717
1825 22:16:40.344800 Set Vref, RX VrefLevel [Byte0]: 68
1826 22:16:40.348193 [Byte1]: 68
1827 22:16:40.352252
1828 22:16:40.352331 Set Vref, RX VrefLevel [Byte0]: 69
1829 22:16:40.355599 [Byte1]: 69
1830 22:16:40.359986
1831 22:16:40.360066 Set Vref, RX VrefLevel [Byte0]: 70
1832 22:16:40.362921 [Byte1]: 70
1833 22:16:40.367737
1834 22:16:40.367815 Set Vref, RX VrefLevel [Byte0]: 71
1835 22:16:40.370629 [Byte1]: 71
1836 22:16:40.375014
1837 22:16:40.375131 Set Vref, RX VrefLevel [Byte0]: 72
1838 22:16:40.378588 [Byte1]: 72
1839 22:16:40.382541
1840 22:16:40.382620 Set Vref, RX VrefLevel [Byte0]: 73
1841 22:16:40.386350 [Byte1]: 73
1842 22:16:40.390607
1843 22:16:40.390686 Set Vref, RX VrefLevel [Byte0]: 74
1844 22:16:40.393670 [Byte1]: 74
1845 22:16:40.397664
1846 22:16:40.397743 Final RX Vref Byte 0 = 56 to rank0
1847 22:16:40.401687 Final RX Vref Byte 1 = 64 to rank0
1848 22:16:40.404591 Final RX Vref Byte 0 = 56 to rank1
1849 22:16:40.407897 Final RX Vref Byte 1 = 64 to rank1==
1850 22:16:40.410922 Dram Type= 6, Freq= 0, CH_1, rank 0
1851 22:16:40.417643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1852 22:16:40.417723 ==
1853 22:16:40.417787 DQS Delay:
1854 22:16:40.417844 DQS0 = 0, DQS1 = 0
1855 22:16:40.420940 DQM Delay:
1856 22:16:40.421019 DQM0 = 87, DQM1 = 79
1857 22:16:40.424689 DQ Delay:
1858 22:16:40.427891 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1859 22:16:40.431199 DQ4 =84, DQ5 =100, DQ6 =100, DQ7 =80
1860 22:16:40.434373 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1861 22:16:40.437714 DQ12 =88, DQ13 =84, DQ14 =88, DQ15 =88
1862 22:16:40.437811
1863 22:16:40.437877
1864 22:16:40.443948 [DQSOSCAuto] RK0, (LSB)MR18= 0x3521, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 396 ps
1865 22:16:40.447122 CH1 RK0: MR19=606, MR18=3521
1866 22:16:40.453770 CH1_RK0: MR19=0x606, MR18=0x3521, DQSOSC=396, MR23=63, INC=94, DEC=62
1867 22:16:40.453884
1868 22:16:40.457348 ----->DramcWriteLeveling(PI) begin...
1869 22:16:40.457459 ==
1870 22:16:40.461225 Dram Type= 6, Freq= 0, CH_1, rank 1
1871 22:16:40.463604 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1872 22:16:40.463736 ==
1873 22:16:40.467269 Write leveling (Byte 0): 27 => 27
1874 22:16:40.470713 Write leveling (Byte 1): 31 => 31
1875 22:16:40.473986 DramcWriteLeveling(PI) end<-----
1876 22:16:40.474156
1877 22:16:40.474287 ==
1878 22:16:40.477130 Dram Type= 6, Freq= 0, CH_1, rank 1
1879 22:16:40.480609 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1880 22:16:40.483909 ==
1881 22:16:40.484155 [Gating] SW mode calibration
1882 22:16:40.490549 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1883 22:16:40.497473 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1884 22:16:40.501263 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1885 22:16:40.506899 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1886 22:16:40.510140 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 22:16:40.513860 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 22:16:40.520477 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 22:16:40.523852 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 22:16:40.526955 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 22:16:40.534146 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 22:16:40.537040 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 22:16:40.540033 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 22:16:40.547170 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 22:16:40.550333 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 22:16:40.553627 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 22:16:40.560323 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 22:16:40.563597 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1899 22:16:40.566517 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 22:16:40.573499 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1901 22:16:40.576671 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1902 22:16:40.579969 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
1903 22:16:40.586667 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1904 22:16:40.590240 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1905 22:16:40.593261 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1906 22:16:40.599658 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1907 22:16:40.603585 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1908 22:16:40.605984 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1909 22:16:40.613081 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1910 22:16:40.615918 0 9 8 | B1->B0 | 3232 2424 | 0 0 | (1 1) (0 0)
1911 22:16:40.618977 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1912 22:16:40.626340 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1913 22:16:40.629381 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1914 22:16:40.632141 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1915 22:16:40.639026 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1916 22:16:40.642371 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1917 22:16:40.645885 0 10 4 | B1->B0 | 3232 3434 | 0 1 | (1 0) (1 0)
1918 22:16:40.649125 0 10 8 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (1 0)
1919 22:16:40.655400 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1920 22:16:40.659165 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1921 22:16:40.662384 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1922 22:16:40.669028 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1923 22:16:40.672372 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1924 22:16:40.675500 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1925 22:16:40.682008 0 11 4 | B1->B0 | 2828 2626 | 0 1 | (0 0) (0 0)
1926 22:16:40.685342 0 11 8 | B1->B0 | 3e3e 3636 | 0 1 | (0 0) (0 0)
1927 22:16:40.688880 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1928 22:16:40.695297 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1929 22:16:40.698557 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1930 22:16:40.702197 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1931 22:16:40.709733 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1932 22:16:40.712363 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1933 22:16:40.715310 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1934 22:16:40.721778 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1935 22:16:40.725765 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1936 22:16:40.729091 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1937 22:16:40.735680 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1938 22:16:40.739035 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1939 22:16:40.741806 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1940 22:16:40.749161 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1941 22:16:40.752143 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1942 22:16:40.755201 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1943 22:16:40.762153 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1944 22:16:40.765374 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1945 22:16:40.768749 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1946 22:16:40.775384 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1947 22:16:40.778669 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1948 22:16:40.781914 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1949 22:16:40.788307 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1950 22:16:40.791616 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1951 22:16:40.794967 Total UI for P1: 0, mck2ui 16
1952 22:16:40.798482 best dqsien dly found for B0: ( 0, 14, 4)
1953 22:16:40.802017 Total UI for P1: 0, mck2ui 16
1954 22:16:40.805125 best dqsien dly found for B1: ( 0, 14, 4)
1955 22:16:40.808155 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1956 22:16:40.811629 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1957 22:16:40.811721
1958 22:16:40.814995 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1959 22:16:40.818167 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1960 22:16:40.822033 [Gating] SW calibration Done
1961 22:16:40.822140 ==
1962 22:16:40.824907 Dram Type= 6, Freq= 0, CH_1, rank 1
1963 22:16:40.828019 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1964 22:16:40.828151 ==
1965 22:16:40.831291 RX Vref Scan: 0
1966 22:16:40.831423
1967 22:16:40.834423 RX Vref 0 -> 0, step: 1
1968 22:16:40.834570
1969 22:16:40.834684 RX Delay -130 -> 252, step: 16
1970 22:16:40.841367 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1971 22:16:40.844602 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1972 22:16:40.847813 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1973 22:16:40.851315 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1974 22:16:40.854565 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1975 22:16:40.861124 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1976 22:16:40.864815 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1977 22:16:40.868075 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1978 22:16:40.871254 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1979 22:16:40.874534 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1980 22:16:40.881078 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1981 22:16:40.884624 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1982 22:16:40.887907 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1983 22:16:40.890993 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1984 22:16:40.897726 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1985 22:16:40.901217 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1986 22:16:40.901293 ==
1987 22:16:40.904478 Dram Type= 6, Freq= 0, CH_1, rank 1
1988 22:16:40.907879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1989 22:16:40.907957 ==
1990 22:16:40.911444 DQS Delay:
1991 22:16:40.911517 DQS0 = 0, DQS1 = 0
1992 22:16:40.911593 DQM Delay:
1993 22:16:40.914881 DQM0 = 87, DQM1 = 79
1994 22:16:40.914952 DQ Delay:
1995 22:16:40.917346 DQ0 =85, DQ1 =77, DQ2 =77, DQ3 =85
1996 22:16:40.920842 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1997 22:16:40.924152 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1998 22:16:40.927503 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1999 22:16:40.927577
2000 22:16:40.927654
2001 22:16:40.927729 ==
2002 22:16:40.931169 Dram Type= 6, Freq= 0, CH_1, rank 1
2003 22:16:40.937408 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2004 22:16:40.937483 ==
2005 22:16:40.937560
2006 22:16:40.937634
2007 22:16:40.937707 TX Vref Scan disable
2008 22:16:40.941122 == TX Byte 0 ==
2009 22:16:40.944336 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2010 22:16:40.947914 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2011 22:16:40.950928 == TX Byte 1 ==
2012 22:16:40.954554 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
2013 22:16:40.961097 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
2014 22:16:40.961174 ==
2015 22:16:40.964085 Dram Type= 6, Freq= 0, CH_1, rank 1
2016 22:16:40.967316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2017 22:16:40.967390 ==
2018 22:16:40.980520 TX Vref=22, minBit 9, minWin=26, winSum=446
2019 22:16:40.983825 TX Vref=24, minBit 8, minWin=27, winSum=449
2020 22:16:40.987340 TX Vref=26, minBit 8, minWin=27, winSum=448
2021 22:16:40.990184 TX Vref=28, minBit 15, minWin=27, winSum=454
2022 22:16:40.993648 TX Vref=30, minBit 8, minWin=27, winSum=450
2023 22:16:41.000435 TX Vref=32, minBit 8, minWin=27, winSum=451
2024 22:16:41.003632 [TxChooseVref] Worse bit 15, Min win 27, Win sum 454, Final Vref 28
2025 22:16:41.003717
2026 22:16:41.007224 Final TX Range 1 Vref 28
2027 22:16:41.007307
2028 22:16:41.007389 ==
2029 22:16:41.010259 Dram Type= 6, Freq= 0, CH_1, rank 1
2030 22:16:41.013442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2031 22:16:41.016714 ==
2032 22:16:41.016796
2033 22:16:41.016877
2034 22:16:41.016954 TX Vref Scan disable
2035 22:16:41.020683 == TX Byte 0 ==
2036 22:16:41.023928 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2037 22:16:41.030615 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2038 22:16:41.030698 == TX Byte 1 ==
2039 22:16:41.033614 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
2040 22:16:41.040538 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
2041 22:16:41.040621
2042 22:16:41.040704 [DATLAT]
2043 22:16:41.040780 Freq=800, CH1 RK1
2044 22:16:41.040856
2045 22:16:41.044130 DATLAT Default: 0xa
2046 22:16:41.044213 0, 0xFFFF, sum = 0
2047 22:16:41.047088 1, 0xFFFF, sum = 0
2048 22:16:41.047185 2, 0xFFFF, sum = 0
2049 22:16:41.050393 3, 0xFFFF, sum = 0
2050 22:16:41.053391 4, 0xFFFF, sum = 0
2051 22:16:41.053475 5, 0xFFFF, sum = 0
2052 22:16:41.056631 6, 0xFFFF, sum = 0
2053 22:16:41.056715 7, 0xFFFF, sum = 0
2054 22:16:41.060001 8, 0xFFFF, sum = 0
2055 22:16:41.060084 9, 0x0, sum = 1
2056 22:16:41.063483 10, 0x0, sum = 2
2057 22:16:41.063567 11, 0x0, sum = 3
2058 22:16:41.063650 12, 0x0, sum = 4
2059 22:16:41.066569 best_step = 10
2060 22:16:41.066650
2061 22:16:41.066731 ==
2062 22:16:41.070270 Dram Type= 6, Freq= 0, CH_1, rank 1
2063 22:16:41.073524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2064 22:16:41.073607 ==
2065 22:16:41.076786 RX Vref Scan: 0
2066 22:16:41.076870
2067 22:16:41.076934 RX Vref 0 -> 0, step: 1
2068 22:16:41.080003
2069 22:16:41.080069 RX Delay -95 -> 252, step: 8
2070 22:16:41.087360 iDelay=217, Bit 0, Center 92 (-23 ~ 208) 232
2071 22:16:41.090667 iDelay=217, Bit 1, Center 80 (-31 ~ 192) 224
2072 22:16:41.094245 iDelay=217, Bit 2, Center 80 (-31 ~ 192) 224
2073 22:16:41.097052 iDelay=217, Bit 3, Center 88 (-23 ~ 200) 224
2074 22:16:41.100565 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
2075 22:16:41.107268 iDelay=217, Bit 5, Center 96 (-15 ~ 208) 224
2076 22:16:41.110732 iDelay=217, Bit 6, Center 100 (-15 ~ 216) 232
2077 22:16:41.113867 iDelay=217, Bit 7, Center 84 (-31 ~ 200) 232
2078 22:16:41.117139 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
2079 22:16:41.120732 iDelay=217, Bit 9, Center 68 (-47 ~ 184) 232
2080 22:16:41.126982 iDelay=217, Bit 10, Center 84 (-31 ~ 200) 232
2081 22:16:41.130944 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
2082 22:16:41.133812 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
2083 22:16:41.136917 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
2084 22:16:41.143669 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
2085 22:16:41.147182 iDelay=217, Bit 15, Center 88 (-31 ~ 208) 240
2086 22:16:41.147265 ==
2087 22:16:41.150409 Dram Type= 6, Freq= 0, CH_1, rank 1
2088 22:16:41.153428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2089 22:16:41.153521 ==
2090 22:16:41.156891 DQS Delay:
2091 22:16:41.156982 DQS0 = 0, DQS1 = 0
2092 22:16:41.157053 DQM Delay:
2093 22:16:41.160122 DQM0 = 88, DQM1 = 78
2094 22:16:41.160531 DQ Delay:
2095 22:16:41.163583 DQ0 =92, DQ1 =80, DQ2 =80, DQ3 =88
2096 22:16:41.167225 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =84
2097 22:16:41.170591 DQ8 =68, DQ9 =68, DQ10 =84, DQ11 =68
2098 22:16:41.173550 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =88
2099 22:16:41.173963
2100 22:16:41.174281
2101 22:16:41.183624 [DQSOSCAuto] RK1, (LSB)MR18= 0x1a12, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 403 ps
2102 22:16:41.184040 CH1 RK1: MR19=606, MR18=1A12
2103 22:16:41.190659 CH1_RK1: MR19=0x606, MR18=0x1A12, DQSOSC=403, MR23=63, INC=90, DEC=60
2104 22:16:41.193275 [RxdqsGatingPostProcess] freq 800
2105 22:16:41.200467 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2106 22:16:41.203639 Pre-setting of DQS Precalculation
2107 22:16:41.206721 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2108 22:16:41.213219 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2109 22:16:41.223301 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2110 22:16:41.223765
2111 22:16:41.224203
2112 22:16:41.226868 [Calibration Summary] 1600 Mbps
2113 22:16:41.227350 CH 0, Rank 0
2114 22:16:41.230022 SW Impedance : PASS
2115 22:16:41.230104 DUTY Scan : NO K
2116 22:16:41.233206 ZQ Calibration : PASS
2117 22:16:41.236439 Jitter Meter : NO K
2118 22:16:41.236521 CBT Training : PASS
2119 22:16:41.239878 Write leveling : PASS
2120 22:16:41.242851 RX DQS gating : PASS
2121 22:16:41.242932 RX DQ/DQS(RDDQC) : PASS
2122 22:16:41.246536 TX DQ/DQS : PASS
2123 22:16:41.246617 RX DATLAT : PASS
2124 22:16:41.249333 RX DQ/DQS(Engine): PASS
2125 22:16:41.253381 TX OE : NO K
2126 22:16:41.253462 All Pass.
2127 22:16:41.253525
2128 22:16:41.253583 CH 0, Rank 1
2129 22:16:41.255938 SW Impedance : PASS
2130 22:16:41.259504 DUTY Scan : NO K
2131 22:16:41.259585 ZQ Calibration : PASS
2132 22:16:41.262736 Jitter Meter : NO K
2133 22:16:41.265912 CBT Training : PASS
2134 22:16:41.265993 Write leveling : PASS
2135 22:16:41.269527 RX DQS gating : PASS
2136 22:16:41.272567 RX DQ/DQS(RDDQC) : PASS
2137 22:16:41.272649 TX DQ/DQS : PASS
2138 22:16:41.276231 RX DATLAT : PASS
2139 22:16:41.279405 RX DQ/DQS(Engine): PASS
2140 22:16:41.279489 TX OE : NO K
2141 22:16:41.282817 All Pass.
2142 22:16:41.282897
2143 22:16:41.282960 CH 1, Rank 0
2144 22:16:41.285864 SW Impedance : PASS
2145 22:16:41.285946 DUTY Scan : NO K
2146 22:16:41.289171 ZQ Calibration : PASS
2147 22:16:41.292878 Jitter Meter : NO K
2148 22:16:41.293007 CBT Training : PASS
2149 22:16:41.296054 Write leveling : PASS
2150 22:16:41.299294 RX DQS gating : PASS
2151 22:16:41.299405 RX DQ/DQS(RDDQC) : PASS
2152 22:16:41.302303 TX DQ/DQS : PASS
2153 22:16:41.305779 RX DATLAT : PASS
2154 22:16:41.305860 RX DQ/DQS(Engine): PASS
2155 22:16:41.309164 TX OE : NO K
2156 22:16:41.309244 All Pass.
2157 22:16:41.309308
2158 22:16:41.312807 CH 1, Rank 1
2159 22:16:41.312888 SW Impedance : PASS
2160 22:16:41.315406 DUTY Scan : NO K
2161 22:16:41.315487 ZQ Calibration : PASS
2162 22:16:41.318767 Jitter Meter : NO K
2163 22:16:41.323204 CBT Training : PASS
2164 22:16:41.323622 Write leveling : PASS
2165 22:16:41.325772 RX DQS gating : PASS
2166 22:16:41.329167 RX DQ/DQS(RDDQC) : PASS
2167 22:16:41.329591 TX DQ/DQS : PASS
2168 22:16:41.332472 RX DATLAT : PASS
2169 22:16:41.335761 RX DQ/DQS(Engine): PASS
2170 22:16:41.336207 TX OE : NO K
2171 22:16:41.339221 All Pass.
2172 22:16:41.339643
2173 22:16:41.340060 DramC Write-DBI off
2174 22:16:41.342410 PER_BANK_REFRESH: Hybrid Mode
2175 22:16:41.342834 TX_TRACKING: ON
2176 22:16:41.345899 [GetDramInforAfterCalByMRR] Vendor 6.
2177 22:16:41.352606 [GetDramInforAfterCalByMRR] Revision 606.
2178 22:16:41.356138 [GetDramInforAfterCalByMRR] Revision 2 0.
2179 22:16:41.356606 MR0 0x3b3b
2180 22:16:41.357061 MR8 0x5151
2181 22:16:41.359489 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2182 22:16:41.359910
2183 22:16:41.362865 MR0 0x3b3b
2184 22:16:41.363385 MR8 0x5151
2185 22:16:41.365607 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2186 22:16:41.366099
2187 22:16:41.375578 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2188 22:16:41.379313 [FAST_K] Save calibration result to emmc
2189 22:16:41.382612 [FAST_K] Save calibration result to emmc
2190 22:16:41.385622 dram_init: config_dvfs: 1
2191 22:16:41.389127 dramc_set_vcore_voltage set vcore to 662500
2192 22:16:41.392403 Read voltage for 1200, 2
2193 22:16:41.392991 Vio18 = 0
2194 22:16:41.393488 Vcore = 662500
2195 22:16:41.396065 Vdram = 0
2196 22:16:41.396653 Vddq = 0
2197 22:16:41.397229 Vmddr = 0
2198 22:16:41.401928 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2199 22:16:41.405376 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2200 22:16:41.408983 MEM_TYPE=3, freq_sel=15
2201 22:16:41.412010 sv_algorithm_assistance_LP4_1600
2202 22:16:41.415619 ============ PULL DRAM RESETB DOWN ============
2203 22:16:41.419050 ========== PULL DRAM RESETB DOWN end =========
2204 22:16:41.425325 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2205 22:16:41.428814 ===================================
2206 22:16:41.432388 LPDDR4 DRAM CONFIGURATION
2207 22:16:41.435347 ===================================
2208 22:16:41.435757 EX_ROW_EN[0] = 0x0
2209 22:16:41.438272 EX_ROW_EN[1] = 0x0
2210 22:16:41.438677 LP4Y_EN = 0x0
2211 22:16:41.441668 WORK_FSP = 0x0
2212 22:16:41.442080 WL = 0x4
2213 22:16:41.445294 RL = 0x4
2214 22:16:41.445725 BL = 0x2
2215 22:16:41.448544 RPST = 0x0
2216 22:16:41.448982 RD_PRE = 0x0
2217 22:16:41.451780 WR_PRE = 0x1
2218 22:16:41.452199 WR_PST = 0x0
2219 22:16:41.455232 DBI_WR = 0x0
2220 22:16:41.455648 DBI_RD = 0x0
2221 22:16:41.458771 OTF = 0x1
2222 22:16:41.461619 ===================================
2223 22:16:41.465266 ===================================
2224 22:16:41.465716 ANA top config
2225 22:16:41.468173 ===================================
2226 22:16:41.472108 DLL_ASYNC_EN = 0
2227 22:16:41.475156 ALL_SLAVE_EN = 0
2228 22:16:41.478126 NEW_RANK_MODE = 1
2229 22:16:41.478573 DLL_IDLE_MODE = 1
2230 22:16:41.481648 LP45_APHY_COMB_EN = 1
2231 22:16:41.485050 TX_ODT_DIS = 1
2232 22:16:41.488682 NEW_8X_MODE = 1
2233 22:16:41.491501 ===================================
2234 22:16:41.494870 ===================================
2235 22:16:41.498071 data_rate = 2400
2236 22:16:41.501775 CKR = 1
2237 22:16:41.502193 DQ_P2S_RATIO = 8
2238 22:16:41.504827 ===================================
2239 22:16:41.508367 CA_P2S_RATIO = 8
2240 22:16:41.512508 DQ_CA_OPEN = 0
2241 22:16:41.514959 DQ_SEMI_OPEN = 0
2242 22:16:41.518060 CA_SEMI_OPEN = 0
2243 22:16:41.521414 CA_FULL_RATE = 0
2244 22:16:41.521882 DQ_CKDIV4_EN = 0
2245 22:16:41.525074 CA_CKDIV4_EN = 0
2246 22:16:41.528808 CA_PREDIV_EN = 0
2247 22:16:41.531568 PH8_DLY = 17
2248 22:16:41.534777 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2249 22:16:41.538017 DQ_AAMCK_DIV = 4
2250 22:16:41.538433 CA_AAMCK_DIV = 4
2251 22:16:41.541645 CA_ADMCK_DIV = 4
2252 22:16:41.544819 DQ_TRACK_CA_EN = 0
2253 22:16:41.548027 CA_PICK = 1200
2254 22:16:41.551589 CA_MCKIO = 1200
2255 22:16:41.554754 MCKIO_SEMI = 0
2256 22:16:41.558163 PLL_FREQ = 2366
2257 22:16:41.558582 DQ_UI_PI_RATIO = 32
2258 22:16:41.561294 CA_UI_PI_RATIO = 0
2259 22:16:41.564404 ===================================
2260 22:16:41.567671 ===================================
2261 22:16:41.571458 memory_type:LPDDR4
2262 22:16:41.574585 GP_NUM : 10
2263 22:16:41.575147 SRAM_EN : 1
2264 22:16:41.578042 MD32_EN : 0
2265 22:16:41.580923 ===================================
2266 22:16:41.584227 [ANA_INIT] >>>>>>>>>>>>>>
2267 22:16:41.584782 <<<<<< [CONFIGURE PHASE]: ANA_TX
2268 22:16:41.590806 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2269 22:16:41.593967 ===================================
2270 22:16:41.594502 data_rate = 2400,PCW = 0X5b00
2271 22:16:41.597515 ===================================
2272 22:16:41.600623 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2273 22:16:41.607514 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2274 22:16:41.614199 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2275 22:16:41.617560 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2276 22:16:41.620992 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2277 22:16:41.624523 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2278 22:16:41.627760 [ANA_INIT] flow start
2279 22:16:41.628178 [ANA_INIT] PLL >>>>>>>>
2280 22:16:41.631091 [ANA_INIT] PLL <<<<<<<<
2281 22:16:41.634187 [ANA_INIT] MIDPI >>>>>>>>
2282 22:16:41.637629 [ANA_INIT] MIDPI <<<<<<<<
2283 22:16:41.638046 [ANA_INIT] DLL >>>>>>>>
2284 22:16:41.640948 [ANA_INIT] DLL <<<<<<<<
2285 22:16:41.641366 [ANA_INIT] flow end
2286 22:16:41.647604 ============ LP4 DIFF to SE enter ============
2287 22:16:41.650631 ============ LP4 DIFF to SE exit ============
2288 22:16:41.654267 [ANA_INIT] <<<<<<<<<<<<<
2289 22:16:41.657749 [Flow] Enable top DCM control >>>>>
2290 22:16:41.661035 [Flow] Enable top DCM control <<<<<
2291 22:16:41.661534 Enable DLL master slave shuffle
2292 22:16:41.667172 ==============================================================
2293 22:16:41.670394 Gating Mode config
2294 22:16:41.674065 ==============================================================
2295 22:16:41.677567 Config description:
2296 22:16:41.687273 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2297 22:16:41.694158 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2298 22:16:41.697138 SELPH_MODE 0: By rank 1: By Phase
2299 22:16:41.703547 ==============================================================
2300 22:16:41.707089 GAT_TRACK_EN = 1
2301 22:16:41.710455 RX_GATING_MODE = 2
2302 22:16:41.713730 RX_GATING_TRACK_MODE = 2
2303 22:16:41.717087 SELPH_MODE = 1
2304 22:16:41.720172 PICG_EARLY_EN = 1
2305 22:16:41.720590 VALID_LAT_VALUE = 1
2306 22:16:41.727261 ==============================================================
2307 22:16:41.730459 Enter into Gating configuration >>>>
2308 22:16:41.733739 Exit from Gating configuration <<<<
2309 22:16:41.737061 Enter into DVFS_PRE_config >>>>>
2310 22:16:41.746720 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2311 22:16:41.749988 Exit from DVFS_PRE_config <<<<<
2312 22:16:41.754026 Enter into PICG configuration >>>>
2313 22:16:41.756809 Exit from PICG configuration <<<<
2314 22:16:41.760432 [RX_INPUT] configuration >>>>>
2315 22:16:41.763494 [RX_INPUT] configuration <<<<<
2316 22:16:41.766576 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2317 22:16:41.773259 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2318 22:16:41.779906 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2319 22:16:41.786854 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2320 22:16:41.793364 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2321 22:16:41.799413 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2322 22:16:41.803344 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2323 22:16:41.806559 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2324 22:16:41.810013 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2325 22:16:41.816449 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2326 22:16:41.819426 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2327 22:16:41.822989 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2328 22:16:41.826121 ===================================
2329 22:16:41.829980 LPDDR4 DRAM CONFIGURATION
2330 22:16:41.833737 ===================================
2331 22:16:41.834152 EX_ROW_EN[0] = 0x0
2332 22:16:41.836317 EX_ROW_EN[1] = 0x0
2333 22:16:41.836728 LP4Y_EN = 0x0
2334 22:16:41.839746 WORK_FSP = 0x0
2335 22:16:41.843537 WL = 0x4
2336 22:16:41.843962 RL = 0x4
2337 22:16:41.846391 BL = 0x2
2338 22:16:41.846808 RPST = 0x0
2339 22:16:41.849571 RD_PRE = 0x0
2340 22:16:41.849986 WR_PRE = 0x1
2341 22:16:41.852833 WR_PST = 0x0
2342 22:16:41.853250 DBI_WR = 0x0
2343 22:16:41.856058 DBI_RD = 0x0
2344 22:16:41.856473 OTF = 0x1
2345 22:16:41.859701 ===================================
2346 22:16:41.862809 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2347 22:16:41.868905 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2348 22:16:41.872862 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2349 22:16:41.875577 ===================================
2350 22:16:41.879215 LPDDR4 DRAM CONFIGURATION
2351 22:16:41.882124 ===================================
2352 22:16:41.882206 EX_ROW_EN[0] = 0x10
2353 22:16:41.885644 EX_ROW_EN[1] = 0x0
2354 22:16:41.885783 LP4Y_EN = 0x0
2355 22:16:41.889224 WORK_FSP = 0x0
2356 22:16:41.889311 WL = 0x4
2357 22:16:41.892052 RL = 0x4
2358 22:16:41.895461 BL = 0x2
2359 22:16:41.895555 RPST = 0x0
2360 22:16:41.898920 RD_PRE = 0x0
2361 22:16:41.899050 WR_PRE = 0x1
2362 22:16:41.902211 WR_PST = 0x0
2363 22:16:41.902344 DBI_WR = 0x0
2364 22:16:41.905442 DBI_RD = 0x0
2365 22:16:41.905535 OTF = 0x1
2366 22:16:41.908600 ===================================
2367 22:16:41.915068 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2368 22:16:41.915191 ==
2369 22:16:41.919276 Dram Type= 6, Freq= 0, CH_0, rank 0
2370 22:16:41.922540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2371 22:16:41.923007 ==
2372 22:16:41.925695 [Duty_Offset_Calibration]
2373 22:16:41.929047 B0:1 B1:-1 CA:0
2374 22:16:41.929125
2375 22:16:41.931689 [DutyScan_Calibration_Flow] k_type=0
2376 22:16:41.940141
2377 22:16:41.940234 ==CLK 0==
2378 22:16:41.943229 Final CLK duty delay cell = 0
2379 22:16:41.946558 [0] MAX Duty = 5125%(X100), DQS PI = 24
2380 22:16:41.949800 [0] MIN Duty = 4907%(X100), DQS PI = 6
2381 22:16:41.949878 [0] AVG Duty = 5016%(X100)
2382 22:16:41.953280
2383 22:16:41.956629 CH0 CLK Duty spec in!! Max-Min= 218%
2384 22:16:41.959717 [DutyScan_Calibration_Flow] ====Done====
2385 22:16:41.959796
2386 22:16:41.963265 [DutyScan_Calibration_Flow] k_type=1
2387 22:16:41.978025
2388 22:16:41.978133 ==DQS 0 ==
2389 22:16:41.980910 Final DQS duty delay cell = -4
2390 22:16:41.984251 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2391 22:16:41.987646 [-4] MIN Duty = 4875%(X100), DQS PI = 56
2392 22:16:41.991048 [-4] AVG Duty = 4968%(X100)
2393 22:16:41.991188
2394 22:16:41.991290 ==DQS 1 ==
2395 22:16:41.994887 Final DQS duty delay cell = -4
2396 22:16:41.998018 [-4] MAX Duty = 5000%(X100), DQS PI = 4
2397 22:16:42.001226 [-4] MIN Duty = 4876%(X100), DQS PI = 22
2398 22:16:42.004552 [-4] AVG Duty = 4938%(X100)
2399 22:16:42.004746
2400 22:16:42.007912 CH0 DQS 0 Duty spec in!! Max-Min= 187%
2401 22:16:42.008148
2402 22:16:42.011142 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2403 22:16:42.014830 [DutyScan_Calibration_Flow] ====Done====
2404 22:16:42.015210
2405 22:16:42.017920 [DutyScan_Calibration_Flow] k_type=3
2406 22:16:42.035939
2407 22:16:42.036344 ==DQM 0 ==
2408 22:16:42.039398 Final DQM duty delay cell = 0
2409 22:16:42.042681 [0] MAX Duty = 5031%(X100), DQS PI = 16
2410 22:16:42.045902 [0] MIN Duty = 4907%(X100), DQS PI = 6
2411 22:16:42.049863 [0] AVG Duty = 4969%(X100)
2412 22:16:42.050321
2413 22:16:42.050654 ==DQM 1 ==
2414 22:16:42.052464 Final DQM duty delay cell = 4
2415 22:16:42.056397 [4] MAX Duty = 5187%(X100), DQS PI = 16
2416 22:16:42.059220 [4] MIN Duty = 5000%(X100), DQS PI = 24
2417 22:16:42.062531 [4] AVG Duty = 5093%(X100)
2418 22:16:42.062940
2419 22:16:42.065722 CH0 DQM 0 Duty spec in!! Max-Min= 124%
2420 22:16:42.066232
2421 22:16:42.069416 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2422 22:16:42.072723 [DutyScan_Calibration_Flow] ====Done====
2423 22:16:42.073129
2424 22:16:42.075638 [DutyScan_Calibration_Flow] k_type=2
2425 22:16:42.091249
2426 22:16:42.091652 ==DQ 0 ==
2427 22:16:42.094398 Final DQ duty delay cell = -4
2428 22:16:42.097430 [-4] MAX Duty = 5031%(X100), DQS PI = 20
2429 22:16:42.100679 [-4] MIN Duty = 4907%(X100), DQS PI = 48
2430 22:16:42.104062 [-4] AVG Duty = 4969%(X100)
2431 22:16:42.104473
2432 22:16:42.104789 ==DQ 1 ==
2433 22:16:42.107538 Final DQ duty delay cell = -4
2434 22:16:42.110782 [-4] MAX Duty = 5000%(X100), DQS PI = 54
2435 22:16:42.114360 [-4] MIN Duty = 4876%(X100), DQS PI = 16
2436 22:16:42.117661 [-4] AVG Duty = 4938%(X100)
2437 22:16:42.118068
2438 22:16:42.121066 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2439 22:16:42.121473
2440 22:16:42.123911 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2441 22:16:42.127390 [DutyScan_Calibration_Flow] ====Done====
2442 22:16:42.127796 ==
2443 22:16:42.130289 Dram Type= 6, Freq= 0, CH_1, rank 0
2444 22:16:42.134127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2445 22:16:42.134546 ==
2446 22:16:42.137448 [Duty_Offset_Calibration]
2447 22:16:42.140533 B0:-1 B1:1 CA:2
2448 22:16:42.140958
2449 22:16:42.143940 [DutyScan_Calibration_Flow] k_type=0
2450 22:16:42.151617
2451 22:16:42.152035 ==CLK 0==
2452 22:16:42.154919 Final CLK duty delay cell = 0
2453 22:16:42.158543 [0] MAX Duty = 5156%(X100), DQS PI = 22
2454 22:16:42.162037 [0] MIN Duty = 4969%(X100), DQS PI = 60
2455 22:16:42.165689 [0] AVG Duty = 5062%(X100)
2456 22:16:42.166105
2457 22:16:42.168176 CH1 CLK Duty spec in!! Max-Min= 187%
2458 22:16:42.171950 [DutyScan_Calibration_Flow] ====Done====
2459 22:16:42.172391
2460 22:16:42.175130 [DutyScan_Calibration_Flow] k_type=1
2461 22:16:42.191395
2462 22:16:42.191796 ==DQS 0 ==
2463 22:16:42.194760 Final DQS duty delay cell = 0
2464 22:16:42.197919 [0] MAX Duty = 5156%(X100), DQS PI = 48
2465 22:16:42.201033 [0] MIN Duty = 4938%(X100), DQS PI = 6
2466 22:16:42.201447 [0] AVG Duty = 5047%(X100)
2467 22:16:42.204817
2468 22:16:42.205245 ==DQS 1 ==
2469 22:16:42.207645 Final DQS duty delay cell = 0
2470 22:16:42.211217 [0] MAX Duty = 5094%(X100), DQS PI = 12
2471 22:16:42.214050 [0] MIN Duty = 4969%(X100), DQS PI = 56
2472 22:16:42.217698 [0] AVG Duty = 5031%(X100)
2473 22:16:42.217778
2474 22:16:42.220738 CH1 DQS 0 Duty spec in!! Max-Min= 218%
2475 22:16:42.220818
2476 22:16:42.223767 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2477 22:16:42.227552 [DutyScan_Calibration_Flow] ====Done====
2478 22:16:42.227631
2479 22:16:42.230581 [DutyScan_Calibration_Flow] k_type=3
2480 22:16:42.246557
2481 22:16:42.246711 ==DQM 0 ==
2482 22:16:42.249924 Final DQM duty delay cell = -4
2483 22:16:42.253377 [-4] MAX Duty = 5031%(X100), DQS PI = 34
2484 22:16:42.256530 [-4] MIN Duty = 4844%(X100), DQS PI = 8
2485 22:16:42.259681 [-4] AVG Duty = 4937%(X100)
2486 22:16:42.259760
2487 22:16:42.259823 ==DQM 1 ==
2488 22:16:42.262870 Final DQM duty delay cell = 0
2489 22:16:42.266009 [0] MAX Duty = 5187%(X100), DQS PI = 4
2490 22:16:42.269799 [0] MIN Duty = 4969%(X100), DQS PI = 28
2491 22:16:42.272908 [0] AVG Duty = 5078%(X100)
2492 22:16:42.272988
2493 22:16:42.276447 CH1 DQM 0 Duty spec in!! Max-Min= 187%
2494 22:16:42.276526
2495 22:16:42.279563 CH1 DQM 1 Duty spec in!! Max-Min= 218%
2496 22:16:42.282607 [DutyScan_Calibration_Flow] ====Done====
2497 22:16:42.282687
2498 22:16:42.286031 [DutyScan_Calibration_Flow] k_type=2
2499 22:16:42.303361
2500 22:16:42.303442 ==DQ 0 ==
2501 22:16:42.306674 Final DQ duty delay cell = 0
2502 22:16:42.309938 [0] MAX Duty = 5187%(X100), DQS PI = 28
2503 22:16:42.313221 [0] MIN Duty = 4907%(X100), DQS PI = 6
2504 22:16:42.313307 [0] AVG Duty = 5047%(X100)
2505 22:16:42.316812
2506 22:16:42.316979 ==DQ 1 ==
2507 22:16:42.320087 Final DQ duty delay cell = 0
2508 22:16:42.322828 [0] MAX Duty = 5156%(X100), DQS PI = 10
2509 22:16:42.326219 [0] MIN Duty = 4969%(X100), DQS PI = 58
2510 22:16:42.326380 [0] AVG Duty = 5062%(X100)
2511 22:16:42.329449
2512 22:16:42.332825 CH1 DQ 0 Duty spec in!! Max-Min= 280%
2513 22:16:42.332948
2514 22:16:42.336326 CH1 DQ 1 Duty spec in!! Max-Min= 187%
2515 22:16:42.339607 [DutyScan_Calibration_Flow] ====Done====
2516 22:16:42.342646 nWR fixed to 30
2517 22:16:42.342727 [ModeRegInit_LP4] CH0 RK0
2518 22:16:42.346205 [ModeRegInit_LP4] CH0 RK1
2519 22:16:42.349629 [ModeRegInit_LP4] CH1 RK0
2520 22:16:42.353065 [ModeRegInit_LP4] CH1 RK1
2521 22:16:42.353145 match AC timing 7
2522 22:16:42.359395 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2523 22:16:42.362798 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2524 22:16:42.365820 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2525 22:16:42.372694 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2526 22:16:42.375824 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2527 22:16:42.375945 ==
2528 22:16:42.379291 Dram Type= 6, Freq= 0, CH_0, rank 0
2529 22:16:42.382872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2530 22:16:42.382962 ==
2531 22:16:42.389060 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2532 22:16:42.395698 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2533 22:16:42.403245 [CA 0] Center 39 (9~70) winsize 62
2534 22:16:42.406543 [CA 1] Center 39 (9~69) winsize 61
2535 22:16:42.409764 [CA 2] Center 35 (5~66) winsize 62
2536 22:16:42.413037 [CA 3] Center 35 (5~66) winsize 62
2537 22:16:42.416279 [CA 4] Center 33 (4~63) winsize 60
2538 22:16:42.419700 [CA 5] Center 33 (3~63) winsize 61
2539 22:16:42.419850
2540 22:16:42.423202 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2541 22:16:42.423372
2542 22:16:42.426404 [CATrainingPosCal] consider 1 rank data
2543 22:16:42.429897 u2DelayCellTimex100 = 270/100 ps
2544 22:16:42.433202 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2545 22:16:42.436445 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2546 22:16:42.443305 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2547 22:16:42.446613 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2548 22:16:42.449665 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
2549 22:16:42.453619 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2550 22:16:42.454031
2551 22:16:42.456589 CA PerBit enable=1, Macro0, CA PI delay=33
2552 22:16:42.457004
2553 22:16:42.459946 [CBTSetCACLKResult] CA Dly = 33
2554 22:16:42.460358 CS Dly: 8 (0~39)
2555 22:16:42.463212 ==
2556 22:16:42.466496 Dram Type= 6, Freq= 0, CH_0, rank 1
2557 22:16:42.469783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2558 22:16:42.470257 ==
2559 22:16:42.472965 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2560 22:16:42.480628 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2561 22:16:42.489001 [CA 0] Center 39 (9~70) winsize 62
2562 22:16:42.492317 [CA 1] Center 39 (9~70) winsize 62
2563 22:16:42.495995 [CA 2] Center 35 (5~66) winsize 62
2564 22:16:42.499144 [CA 3] Center 34 (4~65) winsize 62
2565 22:16:42.502576 [CA 4] Center 33 (3~64) winsize 62
2566 22:16:42.505681 [CA 5] Center 33 (3~63) winsize 61
2567 22:16:42.506156
2568 22:16:42.508884 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2569 22:16:42.509357
2570 22:16:42.512215 [CATrainingPosCal] consider 2 rank data
2571 22:16:42.515389 u2DelayCellTimex100 = 270/100 ps
2572 22:16:42.518755 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2573 22:16:42.525566 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2574 22:16:42.529280 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2575 22:16:42.532111 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2576 22:16:42.535545 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
2577 22:16:42.538660 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2578 22:16:42.539105
2579 22:16:42.541970 CA PerBit enable=1, Macro0, CA PI delay=33
2580 22:16:42.542377
2581 22:16:42.545180 [CBTSetCACLKResult] CA Dly = 33
2582 22:16:42.545588 CS Dly: 9 (0~41)
2583 22:16:42.548830
2584 22:16:42.552374 ----->DramcWriteLeveling(PI) begin...
2585 22:16:42.552791 ==
2586 22:16:42.555377 Dram Type= 6, Freq= 0, CH_0, rank 0
2587 22:16:42.558555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2588 22:16:42.558968 ==
2589 22:16:42.562176 Write leveling (Byte 0): 33 => 33
2590 22:16:42.565726 Write leveling (Byte 1): 29 => 29
2591 22:16:42.568851 DramcWriteLeveling(PI) end<-----
2592 22:16:42.569281
2593 22:16:42.569601 ==
2594 22:16:42.572085 Dram Type= 6, Freq= 0, CH_0, rank 0
2595 22:16:42.575816 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2596 22:16:42.576250 ==
2597 22:16:42.578666 [Gating] SW mode calibration
2598 22:16:42.585406 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2599 22:16:42.591804 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2600 22:16:42.595395 0 15 0 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
2601 22:16:42.598698 0 15 4 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 1)
2602 22:16:42.605252 0 15 8 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
2603 22:16:42.608461 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2604 22:16:42.611807 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2605 22:16:42.618870 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2606 22:16:42.621950 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2607 22:16:42.625349 0 15 28 | B1->B0 | 3434 2d2d | 1 0 | (1 1) (0 1)
2608 22:16:42.631900 1 0 0 | B1->B0 | 2e2e 2323 | 0 0 | (1 0) (0 0)
2609 22:16:42.635181 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2610 22:16:42.638356 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2611 22:16:42.641617 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2612 22:16:42.648415 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2613 22:16:42.651784 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2614 22:16:42.655368 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2615 22:16:42.661742 1 0 28 | B1->B0 | 2323 3737 | 0 0 | (0 0) (0 0)
2616 22:16:42.665302 1 1 0 | B1->B0 | 2424 4444 | 0 0 | (0 0) (0 0)
2617 22:16:42.668031 1 1 4 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
2618 22:16:42.675030 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2619 22:16:42.678511 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2620 22:16:42.681573 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2621 22:16:42.688082 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2622 22:16:42.691532 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2623 22:16:42.694946 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2624 22:16:42.701366 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2625 22:16:42.705274 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2626 22:16:42.708520 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2627 22:16:42.714750 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2628 22:16:42.718182 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2629 22:16:42.721390 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2630 22:16:42.727848 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2631 22:16:42.731684 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2632 22:16:42.734577 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2633 22:16:42.741379 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2634 22:16:42.744504 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2635 22:16:42.748086 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2636 22:16:42.754577 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2637 22:16:42.758160 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2638 22:16:42.761085 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2639 22:16:42.767939 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2640 22:16:42.771449 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2641 22:16:42.774387 Total UI for P1: 0, mck2ui 16
2642 22:16:42.778193 best dqsien dly found for B0: ( 1, 3, 26)
2643 22:16:42.781315 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2644 22:16:42.784612 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2645 22:16:42.787950 Total UI for P1: 0, mck2ui 16
2646 22:16:42.790990 best dqsien dly found for B1: ( 1, 4, 2)
2647 22:16:42.794541 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2648 22:16:42.800884 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2649 22:16:42.801363
2650 22:16:42.804612 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2651 22:16:42.808096 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2652 22:16:42.811089 [Gating] SW calibration Done
2653 22:16:42.811563 ==
2654 22:16:42.814207 Dram Type= 6, Freq= 0, CH_0, rank 0
2655 22:16:42.817826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2656 22:16:42.818247 ==
2657 22:16:42.818627 RX Vref Scan: 0
2658 22:16:42.821235
2659 22:16:42.821770 RX Vref 0 -> 0, step: 1
2660 22:16:42.822105
2661 22:16:42.824325 RX Delay -40 -> 252, step: 8
2662 22:16:42.827607 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2663 22:16:42.831125 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2664 22:16:42.837381 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2665 22:16:42.841479 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2666 22:16:42.844373 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2667 22:16:42.847571 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2668 22:16:42.850853 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2669 22:16:42.857931 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2670 22:16:42.860821 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2671 22:16:42.864148 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2672 22:16:42.867578 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2673 22:16:42.870838 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2674 22:16:42.877014 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2675 22:16:42.880532 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2676 22:16:42.884547 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2677 22:16:42.887739 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2678 22:16:42.888174 ==
2679 22:16:42.890744 Dram Type= 6, Freq= 0, CH_0, rank 0
2680 22:16:42.897167 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2681 22:16:42.897587 ==
2682 22:16:42.897912 DQS Delay:
2683 22:16:42.900815 DQS0 = 0, DQS1 = 0
2684 22:16:42.901229 DQM Delay:
2685 22:16:42.901552 DQM0 = 119, DQM1 = 106
2686 22:16:42.903853 DQ Delay:
2687 22:16:42.907100 DQ0 =119, DQ1 =119, DQ2 =115, DQ3 =115
2688 22:16:42.910495 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =127
2689 22:16:42.913945 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2690 22:16:42.917078 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2691 22:16:42.917496
2692 22:16:42.917818
2693 22:16:42.918118 ==
2694 22:16:42.920480 Dram Type= 6, Freq= 0, CH_0, rank 0
2695 22:16:42.923857 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2696 22:16:42.926795 ==
2697 22:16:42.927235
2698 22:16:42.927558
2699 22:16:42.927860 TX Vref Scan disable
2700 22:16:42.930395 == TX Byte 0 ==
2701 22:16:42.933382 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2702 22:16:42.937017 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2703 22:16:42.940015 == TX Byte 1 ==
2704 22:16:42.943750 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2705 22:16:42.946686 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2706 22:16:42.950268 ==
2707 22:16:42.953521 Dram Type= 6, Freq= 0, CH_0, rank 0
2708 22:16:42.956988 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2709 22:16:42.957367 ==
2710 22:16:42.968175 TX Vref=22, minBit 4, minWin=25, winSum=415
2711 22:16:42.971655 TX Vref=24, minBit 13, minWin=25, winSum=420
2712 22:16:42.974902 TX Vref=26, minBit 5, minWin=26, winSum=429
2713 22:16:42.978353 TX Vref=28, minBit 5, minWin=26, winSum=433
2714 22:16:42.981465 TX Vref=30, minBit 4, minWin=26, winSum=436
2715 22:16:42.984960 TX Vref=32, minBit 5, minWin=26, winSum=433
2716 22:16:42.991314 [TxChooseVref] Worse bit 4, Min win 26, Win sum 436, Final Vref 30
2717 22:16:42.991755
2718 22:16:42.994745 Final TX Range 1 Vref 30
2719 22:16:42.995186
2720 22:16:42.995509 ==
2721 22:16:42.997840 Dram Type= 6, Freq= 0, CH_0, rank 0
2722 22:16:43.001059 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2723 22:16:43.001139 ==
2724 22:16:43.001201
2725 22:16:43.004326
2726 22:16:43.004410 TX Vref Scan disable
2727 22:16:43.007658 == TX Byte 0 ==
2728 22:16:43.010974 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2729 22:16:43.014565 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2730 22:16:43.017411 == TX Byte 1 ==
2731 22:16:43.021001 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2732 22:16:43.024402 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2733 22:16:43.027724
2734 22:16:43.027803 [DATLAT]
2735 22:16:43.027865 Freq=1200, CH0 RK0
2736 22:16:43.027923
2737 22:16:43.030922 DATLAT Default: 0xd
2738 22:16:43.031001 0, 0xFFFF, sum = 0
2739 22:16:43.034032 1, 0xFFFF, sum = 0
2740 22:16:43.034112 2, 0xFFFF, sum = 0
2741 22:16:43.038333 3, 0xFFFF, sum = 0
2742 22:16:43.040921 4, 0xFFFF, sum = 0
2743 22:16:43.041334 5, 0xFFFF, sum = 0
2744 22:16:43.043929 6, 0xFFFF, sum = 0
2745 22:16:43.044010 7, 0xFFFF, sum = 0
2746 22:16:43.047924 8, 0xFFFF, sum = 0
2747 22:16:43.048005 9, 0xFFFF, sum = 0
2748 22:16:43.050899 10, 0xFFFF, sum = 0
2749 22:16:43.051013 11, 0xFFFF, sum = 0
2750 22:16:43.054253 12, 0x0, sum = 1
2751 22:16:43.054334 13, 0x0, sum = 2
2752 22:16:43.057513 14, 0x0, sum = 3
2753 22:16:43.057593 15, 0x0, sum = 4
2754 22:16:43.057656 best_step = 13
2755 22:16:43.060984
2756 22:16:43.061063 ==
2757 22:16:43.064601 Dram Type= 6, Freq= 0, CH_0, rank 0
2758 22:16:43.067225 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2759 22:16:43.067306 ==
2760 22:16:43.067369 RX Vref Scan: 1
2761 22:16:43.067428
2762 22:16:43.070776 Set Vref Range= 32 -> 127
2763 22:16:43.070857
2764 22:16:43.074192 RX Vref 32 -> 127, step: 1
2765 22:16:43.074273
2766 22:16:43.077482 RX Delay -21 -> 252, step: 4
2767 22:16:43.077562
2768 22:16:43.080559 Set Vref, RX VrefLevel [Byte0]: 32
2769 22:16:43.084040 [Byte1]: 32
2770 22:16:43.084120
2771 22:16:43.087465 Set Vref, RX VrefLevel [Byte0]: 33
2772 22:16:43.090896 [Byte1]: 33
2773 22:16:43.093902
2774 22:16:43.093982 Set Vref, RX VrefLevel [Byte0]: 34
2775 22:16:43.097532 [Byte1]: 34
2776 22:16:43.101815
2777 22:16:43.101895 Set Vref, RX VrefLevel [Byte0]: 35
2778 22:16:43.105633 [Byte1]: 35
2779 22:16:43.110136
2780 22:16:43.110690 Set Vref, RX VrefLevel [Byte0]: 36
2781 22:16:43.113432 [Byte1]: 36
2782 22:16:43.117941
2783 22:16:43.118352 Set Vref, RX VrefLevel [Byte0]: 37
2784 22:16:43.120933 [Byte1]: 37
2785 22:16:43.125977
2786 22:16:43.126056 Set Vref, RX VrefLevel [Byte0]: 38
2787 22:16:43.129277 [Byte1]: 38
2788 22:16:43.133931
2789 22:16:43.134023 Set Vref, RX VrefLevel [Byte0]: 39
2790 22:16:43.136833 [Byte1]: 39
2791 22:16:43.141822
2792 22:16:43.141902 Set Vref, RX VrefLevel [Byte0]: 40
2793 22:16:43.144918 [Byte1]: 40
2794 22:16:43.149406
2795 22:16:43.149491 Set Vref, RX VrefLevel [Byte0]: 41
2796 22:16:43.152601 [Byte1]: 41
2797 22:16:43.157427
2798 22:16:43.157519 Set Vref, RX VrefLevel [Byte0]: 42
2799 22:16:43.160972 [Byte1]: 42
2800 22:16:43.165164
2801 22:16:43.165272 Set Vref, RX VrefLevel [Byte0]: 43
2802 22:16:43.168658 [Byte1]: 43
2803 22:16:43.173433
2804 22:16:43.173569 Set Vref, RX VrefLevel [Byte0]: 44
2805 22:16:43.176879 [Byte1]: 44
2806 22:16:43.181290
2807 22:16:43.181441 Set Vref, RX VrefLevel [Byte0]: 45
2808 22:16:43.184650 [Byte1]: 45
2809 22:16:43.189044
2810 22:16:43.189243 Set Vref, RX VrefLevel [Byte0]: 46
2811 22:16:43.192357 [Byte1]: 46
2812 22:16:43.197286
2813 22:16:43.197523 Set Vref, RX VrefLevel [Byte0]: 47
2814 22:16:43.200802 [Byte1]: 47
2815 22:16:43.205500
2816 22:16:43.205883 Set Vref, RX VrefLevel [Byte0]: 48
2817 22:16:43.208403 [Byte1]: 48
2818 22:16:43.213752
2819 22:16:43.214168 Set Vref, RX VrefLevel [Byte0]: 49
2820 22:16:43.216970 [Byte1]: 49
2821 22:16:43.221270
2822 22:16:43.221686 Set Vref, RX VrefLevel [Byte0]: 50
2823 22:16:43.224957 [Byte1]: 50
2824 22:16:43.229098
2825 22:16:43.229512 Set Vref, RX VrefLevel [Byte0]: 51
2826 22:16:43.232511 [Byte1]: 51
2827 22:16:43.237024
2828 22:16:43.237439 Set Vref, RX VrefLevel [Byte0]: 52
2829 22:16:43.240403 [Byte1]: 52
2830 22:16:43.245084
2831 22:16:43.245503 Set Vref, RX VrefLevel [Byte0]: 53
2832 22:16:43.248392 [Byte1]: 53
2833 22:16:43.253358
2834 22:16:43.253773 Set Vref, RX VrefLevel [Byte0]: 54
2835 22:16:43.255745 [Byte1]: 54
2836 22:16:43.260529
2837 22:16:43.260608 Set Vref, RX VrefLevel [Byte0]: 55
2838 22:16:43.263782 [Byte1]: 55
2839 22:16:43.268568
2840 22:16:43.268647 Set Vref, RX VrefLevel [Byte0]: 56
2841 22:16:43.271777 [Byte1]: 56
2842 22:16:43.276417
2843 22:16:43.276497 Set Vref, RX VrefLevel [Byte0]: 57
2844 22:16:43.279768 [Byte1]: 57
2845 22:16:43.284491
2846 22:16:43.287546 Set Vref, RX VrefLevel [Byte0]: 58
2847 22:16:43.287632 [Byte1]: 58
2848 22:16:43.292063
2849 22:16:43.292155 Set Vref, RX VrefLevel [Byte0]: 59
2850 22:16:43.295691 [Byte1]: 59
2851 22:16:43.300319
2852 22:16:43.300427 Set Vref, RX VrefLevel [Byte0]: 60
2853 22:16:43.303335 [Byte1]: 60
2854 22:16:43.307948
2855 22:16:43.308089 Set Vref, RX VrefLevel [Byte0]: 61
2856 22:16:43.311407 [Byte1]: 61
2857 22:16:43.316084
2858 22:16:43.316232 Set Vref, RX VrefLevel [Byte0]: 62
2859 22:16:43.319087 [Byte1]: 62
2860 22:16:43.324293
2861 22:16:43.324489 Set Vref, RX VrefLevel [Byte0]: 63
2862 22:16:43.327659 [Byte1]: 63
2863 22:16:43.331748
2864 22:16:43.331983 Set Vref, RX VrefLevel [Byte0]: 64
2865 22:16:43.335537 [Byte1]: 64
2866 22:16:43.340122
2867 22:16:43.340509 Set Vref, RX VrefLevel [Byte0]: 65
2868 22:16:43.343164 [Byte1]: 65
2869 22:16:43.347670
2870 22:16:43.348081 Set Vref, RX VrefLevel [Byte0]: 66
2871 22:16:43.351408 [Byte1]: 66
2872 22:16:43.356660
2873 22:16:43.357070 Set Vref, RX VrefLevel [Byte0]: 67
2874 22:16:43.359221 [Byte1]: 67
2875 22:16:43.363895
2876 22:16:43.364306 Set Vref, RX VrefLevel [Byte0]: 68
2877 22:16:43.367176 [Byte1]: 68
2878 22:16:43.371491
2879 22:16:43.371902 Set Vref, RX VrefLevel [Byte0]: 69
2880 22:16:43.374918 [Byte1]: 69
2881 22:16:43.379630
2882 22:16:43.380040 Set Vref, RX VrefLevel [Byte0]: 70
2883 22:16:43.382885 [Byte1]: 70
2884 22:16:43.388086
2885 22:16:43.388498 Set Vref, RX VrefLevel [Byte0]: 71
2886 22:16:43.390816 [Byte1]: 71
2887 22:16:43.395388
2888 22:16:43.395799 Set Vref, RX VrefLevel [Byte0]: 72
2889 22:16:43.399013 [Byte1]: 72
2890 22:16:43.403751
2891 22:16:43.404163 Set Vref, RX VrefLevel [Byte0]: 73
2892 22:16:43.407082 [Byte1]: 73
2893 22:16:43.411597
2894 22:16:43.412007 Set Vref, RX VrefLevel [Byte0]: 74
2895 22:16:43.414550 [Byte1]: 74
2896 22:16:43.419329
2897 22:16:43.419739 Set Vref, RX VrefLevel [Byte0]: 75
2898 22:16:43.422393 [Byte1]: 75
2899 22:16:43.427482
2900 22:16:43.427893 Set Vref, RX VrefLevel [Byte0]: 76
2901 22:16:43.430494 [Byte1]: 76
2902 22:16:43.435107
2903 22:16:43.435514 Set Vref, RX VrefLevel [Byte0]: 77
2904 22:16:43.438624 [Byte1]: 77
2905 22:16:43.443380
2906 22:16:43.443791 Final RX Vref Byte 0 = 58 to rank0
2907 22:16:43.446359 Final RX Vref Byte 1 = 51 to rank0
2908 22:16:43.449396 Final RX Vref Byte 0 = 58 to rank1
2909 22:16:43.452834 Final RX Vref Byte 1 = 51 to rank1==
2910 22:16:43.456507 Dram Type= 6, Freq= 0, CH_0, rank 0
2911 22:16:43.462959 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2912 22:16:43.463425 ==
2913 22:16:43.463750 DQS Delay:
2914 22:16:43.464053 DQS0 = 0, DQS1 = 0
2915 22:16:43.466396 DQM Delay:
2916 22:16:43.466808 DQM0 = 118, DQM1 = 107
2917 22:16:43.469609 DQ Delay:
2918 22:16:43.472639 DQ0 =116, DQ1 =120, DQ2 =116, DQ3 =114
2919 22:16:43.476427 DQ4 =120, DQ5 =114, DQ6 =126, DQ7 =124
2920 22:16:43.479971 DQ8 =98, DQ9 =94, DQ10 =110, DQ11 =100
2921 22:16:43.482820 DQ12 =112, DQ13 =110, DQ14 =120, DQ15 =116
2922 22:16:43.483215
2923 22:16:43.483522
2924 22:16:43.492508 [DQSOSCAuto] RK0, (LSB)MR18= 0xdf9, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 405 ps
2925 22:16:43.492883 CH0 RK0: MR19=403, MR18=DF9
2926 22:16:43.499172 CH0_RK0: MR19=0x403, MR18=0xDF9, DQSOSC=405, MR23=63, INC=39, DEC=26
2927 22:16:43.499556
2928 22:16:43.502746 ----->DramcWriteLeveling(PI) begin...
2929 22:16:43.503156 ==
2930 22:16:43.505901 Dram Type= 6, Freq= 0, CH_0, rank 1
2931 22:16:43.509827 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2932 22:16:43.513090 ==
2933 22:16:43.513600 Write leveling (Byte 0): 32 => 32
2934 22:16:43.516411 Write leveling (Byte 1): 32 => 32
2935 22:16:43.519339 DramcWriteLeveling(PI) end<-----
2936 22:16:43.519771
2937 22:16:43.520111 ==
2938 22:16:43.522675 Dram Type= 6, Freq= 0, CH_0, rank 1
2939 22:16:43.529770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2940 22:16:43.530280 ==
2941 22:16:43.532661 [Gating] SW mode calibration
2942 22:16:43.539023 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2943 22:16:43.542439 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2944 22:16:43.548865 0 15 0 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
2945 22:16:43.552679 0 15 4 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
2946 22:16:43.555897 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2947 22:16:43.562563 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2948 22:16:43.565587 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2949 22:16:43.568744 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2950 22:16:43.572399 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2951 22:16:43.579041 0 15 28 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
2952 22:16:43.582463 1 0 0 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
2953 22:16:43.585647 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2954 22:16:43.592657 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2955 22:16:43.595953 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2956 22:16:43.599352 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2957 22:16:43.605426 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2958 22:16:43.608902 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2959 22:16:43.612314 1 0 28 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
2960 22:16:43.618621 1 1 0 | B1->B0 | 3737 4343 | 1 0 | (0 0) (0 0)
2961 22:16:43.622708 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2962 22:16:43.626098 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2963 22:16:43.632089 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2964 22:16:43.636346 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2965 22:16:43.638603 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2966 22:16:43.645537 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2967 22:16:43.649136 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2968 22:16:43.652456 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2969 22:16:43.659159 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2970 22:16:43.661986 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2971 22:16:43.665836 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2972 22:16:43.671984 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2973 22:16:43.675606 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2974 22:16:43.678793 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2975 22:16:43.685229 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2976 22:16:43.688659 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2977 22:16:43.692003 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2978 22:16:43.695755 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2979 22:16:43.701878 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2980 22:16:43.705490 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2981 22:16:43.708595 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2982 22:16:43.715317 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2983 22:16:43.718593 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2984 22:16:43.721738 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2985 22:16:43.725245 Total UI for P1: 0, mck2ui 16
2986 22:16:43.728463 best dqsien dly found for B0: ( 1, 3, 28)
2987 22:16:43.732250 Total UI for P1: 0, mck2ui 16
2988 22:16:43.734911 best dqsien dly found for B1: ( 1, 3, 28)
2989 22:16:43.738384 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2990 22:16:43.741956 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2991 22:16:43.744982
2992 22:16:43.748478 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2993 22:16:43.751911 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2994 22:16:43.754906 [Gating] SW calibration Done
2995 22:16:43.755383 ==
2996 22:16:43.758155 Dram Type= 6, Freq= 0, CH_0, rank 1
2997 22:16:43.761893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2998 22:16:43.762323 ==
2999 22:16:43.762653 RX Vref Scan: 0
3000 22:16:43.765400
3001 22:16:43.765765 RX Vref 0 -> 0, step: 1
3002 22:16:43.766074
3003 22:16:43.768444 RX Delay -40 -> 252, step: 8
3004 22:16:43.772412 iDelay=200, Bit 0, Center 115 (48 ~ 183) 136
3005 22:16:43.775153 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
3006 22:16:43.781989 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
3007 22:16:43.785281 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3008 22:16:43.788300 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3009 22:16:43.792013 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
3010 22:16:43.795491 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3011 22:16:43.801722 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
3012 22:16:43.804947 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3013 22:16:43.808171 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3014 22:16:43.811385 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3015 22:16:43.815387 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3016 22:16:43.821479 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3017 22:16:43.824943 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3018 22:16:43.828024 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3019 22:16:43.831402 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3020 22:16:43.831817 ==
3021 22:16:43.834739 Dram Type= 6, Freq= 0, CH_0, rank 1
3022 22:16:43.841581 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3023 22:16:43.841999 ==
3024 22:16:43.842323 DQS Delay:
3025 22:16:43.842625 DQS0 = 0, DQS1 = 0
3026 22:16:43.844658 DQM Delay:
3027 22:16:43.845130 DQM0 = 117, DQM1 = 108
3028 22:16:43.848027 DQ Delay:
3029 22:16:43.851673 DQ0 =115, DQ1 =119, DQ2 =111, DQ3 =115
3030 22:16:43.854453 DQ4 =119, DQ5 =111, DQ6 =123, DQ7 =127
3031 22:16:43.857843 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
3032 22:16:43.861266 DQ12 =111, DQ13 =119, DQ14 =119, DQ15 =115
3033 22:16:43.861677
3034 22:16:43.862007
3035 22:16:43.862341 ==
3036 22:16:43.864767 Dram Type= 6, Freq= 0, CH_0, rank 1
3037 22:16:43.868347 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3038 22:16:43.868798 ==
3039 22:16:43.871019
3040 22:16:43.871494
3041 22:16:43.871944 TX Vref Scan disable
3042 22:16:43.874948 == TX Byte 0 ==
3043 22:16:43.878395 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3044 22:16:43.881386 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3045 22:16:43.884466 == TX Byte 1 ==
3046 22:16:43.887602 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
3047 22:16:43.891133 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
3048 22:16:43.891541 ==
3049 22:16:43.894395 Dram Type= 6, Freq= 0, CH_0, rank 1
3050 22:16:43.900913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3051 22:16:43.901352 ==
3052 22:16:43.912031 TX Vref=22, minBit 5, minWin=25, winSum=421
3053 22:16:43.915048 TX Vref=24, minBit 5, minWin=25, winSum=422
3054 22:16:43.918339 TX Vref=26, minBit 1, minWin=26, winSum=430
3055 22:16:43.921535 TX Vref=28, minBit 1, minWin=26, winSum=430
3056 22:16:43.924580 TX Vref=30, minBit 12, minWin=26, winSum=432
3057 22:16:43.931665 TX Vref=32, minBit 10, minWin=26, winSum=431
3058 22:16:43.934803 [TxChooseVref] Worse bit 12, Min win 26, Win sum 432, Final Vref 30
3059 22:16:43.938580
3060 22:16:43.939199 Final TX Range 1 Vref 30
3061 22:16:43.939595
3062 22:16:43.939902 ==
3063 22:16:43.941478 Dram Type= 6, Freq= 0, CH_0, rank 1
3064 22:16:43.948132 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3065 22:16:43.948549 ==
3066 22:16:43.948868
3067 22:16:43.949163
3068 22:16:43.949590 TX Vref Scan disable
3069 22:16:43.951493 == TX Byte 0 ==
3070 22:16:43.955172 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3071 22:16:43.961825 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3072 22:16:43.962307 == TX Byte 1 ==
3073 22:16:43.964830 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
3074 22:16:43.971568 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
3075 22:16:43.972029
3076 22:16:43.972360 [DATLAT]
3077 22:16:43.972667 Freq=1200, CH0 RK1
3078 22:16:43.973071
3079 22:16:43.974749 DATLAT Default: 0xd
3080 22:16:43.975283 0, 0xFFFF, sum = 0
3081 22:16:43.978246 1, 0xFFFF, sum = 0
3082 22:16:43.981440 2, 0xFFFF, sum = 0
3083 22:16:43.981860 3, 0xFFFF, sum = 0
3084 22:16:43.984747 4, 0xFFFF, sum = 0
3085 22:16:43.985222 5, 0xFFFF, sum = 0
3086 22:16:43.987577 6, 0xFFFF, sum = 0
3087 22:16:43.987660 7, 0xFFFF, sum = 0
3088 22:16:43.990862 8, 0xFFFF, sum = 0
3089 22:16:43.990944 9, 0xFFFF, sum = 0
3090 22:16:43.994550 10, 0xFFFF, sum = 0
3091 22:16:43.994632 11, 0xFFFF, sum = 0
3092 22:16:43.997870 12, 0x0, sum = 1
3093 22:16:43.997952 13, 0x0, sum = 2
3094 22:16:44.001067 14, 0x0, sum = 3
3095 22:16:44.001150 15, 0x0, sum = 4
3096 22:16:44.004107 best_step = 13
3097 22:16:44.004187
3098 22:16:44.004250 ==
3099 22:16:44.007571 Dram Type= 6, Freq= 0, CH_0, rank 1
3100 22:16:44.010692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3101 22:16:44.010779 ==
3102 22:16:44.014390 RX Vref Scan: 0
3103 22:16:44.014483
3104 22:16:44.014555 RX Vref 0 -> 0, step: 1
3105 22:16:44.014623
3106 22:16:44.017814 RX Delay -21 -> 252, step: 4
3107 22:16:44.024326 iDelay=199, Bit 0, Center 114 (47 ~ 182) 136
3108 22:16:44.027999 iDelay=199, Bit 1, Center 118 (47 ~ 190) 144
3109 22:16:44.030848 iDelay=199, Bit 2, Center 110 (43 ~ 178) 136
3110 22:16:44.033957 iDelay=199, Bit 3, Center 114 (43 ~ 186) 144
3111 22:16:44.037365 iDelay=199, Bit 4, Center 116 (47 ~ 186) 140
3112 22:16:44.043692 iDelay=199, Bit 5, Center 110 (43 ~ 178) 136
3113 22:16:44.047244 iDelay=199, Bit 6, Center 128 (59 ~ 198) 140
3114 22:16:44.050479 iDelay=199, Bit 7, Center 124 (55 ~ 194) 140
3115 22:16:44.054049 iDelay=199, Bit 8, Center 96 (27 ~ 166) 140
3116 22:16:44.057610 iDelay=199, Bit 9, Center 94 (27 ~ 162) 136
3117 22:16:44.064234 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
3118 22:16:44.067157 iDelay=199, Bit 11, Center 100 (35 ~ 166) 132
3119 22:16:44.070587 iDelay=199, Bit 12, Center 114 (47 ~ 182) 136
3120 22:16:44.073686 iDelay=199, Bit 13, Center 116 (51 ~ 182) 132
3121 22:16:44.076780 iDelay=199, Bit 14, Center 118 (55 ~ 182) 128
3122 22:16:44.083676 iDelay=199, Bit 15, Center 116 (51 ~ 182) 132
3123 22:16:44.083764 ==
3124 22:16:44.086983 Dram Type= 6, Freq= 0, CH_0, rank 1
3125 22:16:44.090487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3126 22:16:44.090583 ==
3127 22:16:44.090678 DQS Delay:
3128 22:16:44.093559 DQS0 = 0, DQS1 = 0
3129 22:16:44.093661 DQM Delay:
3130 22:16:44.097422 DQM0 = 116, DQM1 = 108
3131 22:16:44.097525 DQ Delay:
3132 22:16:44.100666 DQ0 =114, DQ1 =118, DQ2 =110, DQ3 =114
3133 22:16:44.103909 DQ4 =116, DQ5 =110, DQ6 =128, DQ7 =124
3134 22:16:44.106760 DQ8 =96, DQ9 =94, DQ10 =110, DQ11 =100
3135 22:16:44.110199 DQ12 =114, DQ13 =116, DQ14 =118, DQ15 =116
3136 22:16:44.110337
3137 22:16:44.113805
3138 22:16:44.120222 [DQSOSCAuto] RK1, (LSB)MR18= 0x10eb, (MSB)MR19= 0x403, tDQSOscB0 = 418 ps tDQSOscB1 = 403 ps
3139 22:16:44.123247 CH0 RK1: MR19=403, MR18=10EB
3140 22:16:44.130239 CH0_RK1: MR19=0x403, MR18=0x10EB, DQSOSC=403, MR23=63, INC=40, DEC=26
3141 22:16:44.133566 [RxdqsGatingPostProcess] freq 1200
3142 22:16:44.136550 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3143 22:16:44.139790 best DQS0 dly(2T, 0.5T) = (0, 11)
3144 22:16:44.142964 best DQS1 dly(2T, 0.5T) = (0, 12)
3145 22:16:44.146447 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3146 22:16:44.149857 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3147 22:16:44.153098 best DQS0 dly(2T, 0.5T) = (0, 11)
3148 22:16:44.156678 best DQS1 dly(2T, 0.5T) = (0, 11)
3149 22:16:44.159956 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3150 22:16:44.162986 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3151 22:16:44.166725 Pre-setting of DQS Precalculation
3152 22:16:44.169741 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3153 22:16:44.170152 ==
3154 22:16:44.172879 Dram Type= 6, Freq= 0, CH_1, rank 0
3155 22:16:44.179667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3156 22:16:44.180083 ==
3157 22:16:44.182880 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3158 22:16:44.189534 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3159 22:16:44.198275 [CA 0] Center 37 (7~68) winsize 62
3160 22:16:44.201394 [CA 1] Center 37 (7~68) winsize 62
3161 22:16:44.204948 [CA 2] Center 34 (4~64) winsize 61
3162 22:16:44.208572 [CA 3] Center 33 (3~64) winsize 62
3163 22:16:44.211367 [CA 4] Center 34 (4~64) winsize 61
3164 22:16:44.214907 [CA 5] Center 33 (3~64) winsize 62
3165 22:16:44.215505
3166 22:16:44.218479 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3167 22:16:44.218890
3168 22:16:44.221701 [CATrainingPosCal] consider 1 rank data
3169 22:16:44.224532 u2DelayCellTimex100 = 270/100 ps
3170 22:16:44.227928 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3171 22:16:44.234704 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3172 22:16:44.237744 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3173 22:16:44.241013 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3174 22:16:44.244560 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3175 22:16:44.247790 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3176 22:16:44.248203
3177 22:16:44.251152 CA PerBit enable=1, Macro0, CA PI delay=33
3178 22:16:44.251565
3179 22:16:44.254655 [CBTSetCACLKResult] CA Dly = 33
3180 22:16:44.255100 CS Dly: 6 (0~37)
3181 22:16:44.258215 ==
3182 22:16:44.261323 Dram Type= 6, Freq= 0, CH_1, rank 1
3183 22:16:44.264240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3184 22:16:44.264654 ==
3185 22:16:44.267691 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3186 22:16:44.274731 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3187 22:16:44.283890 [CA 0] Center 37 (7~68) winsize 62
3188 22:16:44.287239 [CA 1] Center 38 (8~68) winsize 61
3189 22:16:44.290419 [CA 2] Center 34 (4~65) winsize 62
3190 22:16:44.294470 [CA 3] Center 33 (3~64) winsize 62
3191 22:16:44.296866 [CA 4] Center 34 (3~65) winsize 63
3192 22:16:44.300402 [CA 5] Center 33 (3~64) winsize 62
3193 22:16:44.300863
3194 22:16:44.303288 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3195 22:16:44.303706
3196 22:16:44.307221 [CATrainingPosCal] consider 2 rank data
3197 22:16:44.310120 u2DelayCellTimex100 = 270/100 ps
3198 22:16:44.313370 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3199 22:16:44.320336 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3200 22:16:44.323526 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3201 22:16:44.326459 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3202 22:16:44.330212 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3203 22:16:44.333373 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3204 22:16:44.333790
3205 22:16:44.336999 CA PerBit enable=1, Macro0, CA PI delay=33
3206 22:16:44.337420
3207 22:16:44.339954 [CBTSetCACLKResult] CA Dly = 33
3208 22:16:44.340373 CS Dly: 7 (0~40)
3209 22:16:44.343465
3210 22:16:44.346403 ----->DramcWriteLeveling(PI) begin...
3211 22:16:44.346825 ==
3212 22:16:44.349845 Dram Type= 6, Freq= 0, CH_1, rank 0
3213 22:16:44.353188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3214 22:16:44.353608 ==
3215 22:16:44.357066 Write leveling (Byte 0): 23 => 23
3216 22:16:44.360079 Write leveling (Byte 1): 29 => 29
3217 22:16:44.363202 DramcWriteLeveling(PI) end<-----
3218 22:16:44.363684
3219 22:16:44.364017 ==
3220 22:16:44.366421 Dram Type= 6, Freq= 0, CH_1, rank 0
3221 22:16:44.370157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3222 22:16:44.370576 ==
3223 22:16:44.373104 [Gating] SW mode calibration
3224 22:16:44.379609 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3225 22:16:44.386458 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3226 22:16:44.389481 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3227 22:16:44.393410 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3228 22:16:44.399531 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3229 22:16:44.403216 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3230 22:16:44.406330 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3231 22:16:44.412902 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3232 22:16:44.415867 0 15 24 | B1->B0 | 3434 2d2d | 0 1 | (0 1) (1 0)
3233 22:16:44.419158 0 15 28 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
3234 22:16:44.426218 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3235 22:16:44.429405 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3236 22:16:44.433231 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3237 22:16:44.439418 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3238 22:16:44.442480 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3239 22:16:44.446046 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3240 22:16:44.452654 1 0 24 | B1->B0 | 2424 3737 | 0 0 | (0 0) (0 0)
3241 22:16:44.455856 1 0 28 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
3242 22:16:44.459576 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3243 22:16:44.465511 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3244 22:16:44.469123 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3245 22:16:44.472411 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3246 22:16:44.478835 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3247 22:16:44.482395 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3248 22:16:44.485607 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3249 22:16:44.492792 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3250 22:16:44.495603 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3251 22:16:44.499025 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3252 22:16:44.502213 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3253 22:16:44.508980 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3254 22:16:44.512547 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3255 22:16:44.515415 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3256 22:16:44.521998 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3257 22:16:44.525720 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3258 22:16:44.528650 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3259 22:16:44.535739 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3260 22:16:44.538910 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3261 22:16:44.542005 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3262 22:16:44.548734 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3263 22:16:44.552115 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3264 22:16:44.555258 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3265 22:16:44.561980 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3266 22:16:44.565307 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3267 22:16:44.568448 Total UI for P1: 0, mck2ui 16
3268 22:16:44.571889 best dqsien dly found for B0: ( 1, 3, 26)
3269 22:16:44.575532 Total UI for P1: 0, mck2ui 16
3270 22:16:44.578846 best dqsien dly found for B1: ( 1, 3, 28)
3271 22:16:44.582103 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3272 22:16:44.585057 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3273 22:16:44.585476
3274 22:16:44.588485 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3275 22:16:44.591704 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3276 22:16:44.595255 [Gating] SW calibration Done
3277 22:16:44.595671 ==
3278 22:16:44.598084 Dram Type= 6, Freq= 0, CH_1, rank 0
3279 22:16:44.605224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3280 22:16:44.605665 ==
3281 22:16:44.605997 RX Vref Scan: 0
3282 22:16:44.606300
3283 22:16:44.608565 RX Vref 0 -> 0, step: 1
3284 22:16:44.608982
3285 22:16:44.611354 RX Delay -40 -> 252, step: 8
3286 22:16:44.614931 iDelay=208, Bit 0, Center 123 (48 ~ 199) 152
3287 22:16:44.618548 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3288 22:16:44.621422 iDelay=208, Bit 2, Center 111 (40 ~ 183) 144
3289 22:16:44.624955 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3290 22:16:44.631519 iDelay=208, Bit 4, Center 115 (48 ~ 183) 136
3291 22:16:44.634534 iDelay=208, Bit 5, Center 131 (56 ~ 207) 152
3292 22:16:44.637827 iDelay=208, Bit 6, Center 127 (56 ~ 199) 144
3293 22:16:44.641607 iDelay=208, Bit 7, Center 115 (48 ~ 183) 136
3294 22:16:44.644825 iDelay=208, Bit 8, Center 95 (24 ~ 167) 144
3295 22:16:44.651113 iDelay=208, Bit 9, Center 99 (24 ~ 175) 152
3296 22:16:44.654493 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3297 22:16:44.657770 iDelay=208, Bit 11, Center 95 (24 ~ 167) 144
3298 22:16:44.661225 iDelay=208, Bit 12, Center 115 (40 ~ 191) 152
3299 22:16:44.664397 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3300 22:16:44.671106 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3301 22:16:44.674509 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3302 22:16:44.674922 ==
3303 22:16:44.677980 Dram Type= 6, Freq= 0, CH_1, rank 0
3304 22:16:44.681453 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3305 22:16:44.681871 ==
3306 22:16:44.684534 DQS Delay:
3307 22:16:44.684948 DQS0 = 0, DQS1 = 0
3308 22:16:44.685272 DQM Delay:
3309 22:16:44.687574 DQM0 = 118, DQM1 = 108
3310 22:16:44.688007 DQ Delay:
3311 22:16:44.691255 DQ0 =123, DQ1 =111, DQ2 =111, DQ3 =115
3312 22:16:44.694324 DQ4 =115, DQ5 =131, DQ6 =127, DQ7 =115
3313 22:16:44.697952 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =95
3314 22:16:44.704271 DQ12 =115, DQ13 =119, DQ14 =115, DQ15 =119
3315 22:16:44.704695
3316 22:16:44.705081
3317 22:16:44.705393 ==
3318 22:16:44.707826 Dram Type= 6, Freq= 0, CH_1, rank 0
3319 22:16:44.711380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3320 22:16:44.711798 ==
3321 22:16:44.712125
3322 22:16:44.712427
3323 22:16:44.714458 TX Vref Scan disable
3324 22:16:44.714909 == TX Byte 0 ==
3325 22:16:44.721089 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
3326 22:16:44.724356 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
3327 22:16:44.724776 == TX Byte 1 ==
3328 22:16:44.730899 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3329 22:16:44.734362 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3330 22:16:44.734780 ==
3331 22:16:44.737874 Dram Type= 6, Freq= 0, CH_1, rank 0
3332 22:16:44.740920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3333 22:16:44.741338 ==
3334 22:16:44.754154 TX Vref=22, minBit 8, minWin=25, winSum=414
3335 22:16:44.757227 TX Vref=24, minBit 8, minWin=25, winSum=422
3336 22:16:44.760643 TX Vref=26, minBit 8, minWin=25, winSum=427
3337 22:16:44.763601 TX Vref=28, minBit 9, minWin=26, winSum=436
3338 22:16:44.767559 TX Vref=30, minBit 9, minWin=25, winSum=429
3339 22:16:44.773956 TX Vref=32, minBit 9, minWin=25, winSum=428
3340 22:16:44.776901 [TxChooseVref] Worse bit 9, Min win 26, Win sum 436, Final Vref 28
3341 22:16:44.777354
3342 22:16:44.780703 Final TX Range 1 Vref 28
3343 22:16:44.781120
3344 22:16:44.781463 ==
3345 22:16:44.783711 Dram Type= 6, Freq= 0, CH_1, rank 0
3346 22:16:44.787872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3347 22:16:44.790429 ==
3348 22:16:44.790974
3349 22:16:44.791369
3350 22:16:44.791678 TX Vref Scan disable
3351 22:16:44.793608 == TX Byte 0 ==
3352 22:16:44.797305 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
3353 22:16:44.800258 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
3354 22:16:44.803385 == TX Byte 1 ==
3355 22:16:44.807127 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3356 22:16:44.813436 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3357 22:16:44.813851
3358 22:16:44.814172 [DATLAT]
3359 22:16:44.814470 Freq=1200, CH1 RK0
3360 22:16:44.814752
3361 22:16:44.816638 DATLAT Default: 0xd
3362 22:16:44.817040 0, 0xFFFF, sum = 0
3363 22:16:44.820429 1, 0xFFFF, sum = 0
3364 22:16:44.824048 2, 0xFFFF, sum = 0
3365 22:16:44.824456 3, 0xFFFF, sum = 0
3366 22:16:44.826985 4, 0xFFFF, sum = 0
3367 22:16:44.827418 5, 0xFFFF, sum = 0
3368 22:16:44.830128 6, 0xFFFF, sum = 0
3369 22:16:44.830536 7, 0xFFFF, sum = 0
3370 22:16:44.833164 8, 0xFFFF, sum = 0
3371 22:16:44.833704 9, 0xFFFF, sum = 0
3372 22:16:44.836640 10, 0xFFFF, sum = 0
3373 22:16:44.837215 11, 0xFFFF, sum = 0
3374 22:16:44.840565 12, 0x0, sum = 1
3375 22:16:44.840855 13, 0x0, sum = 2
3376 22:16:44.843157 14, 0x0, sum = 3
3377 22:16:44.843449 15, 0x0, sum = 4
3378 22:16:44.846619 best_step = 13
3379 22:16:44.846902
3380 22:16:44.847147 ==
3381 22:16:44.850012 Dram Type= 6, Freq= 0, CH_1, rank 0
3382 22:16:44.853222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3383 22:16:44.853522 ==
3384 22:16:44.853744 RX Vref Scan: 1
3385 22:16:44.856384
3386 22:16:44.856668 Set Vref Range= 32 -> 127
3387 22:16:44.856893
3388 22:16:44.859940 RX Vref 32 -> 127, step: 1
3389 22:16:44.860249
3390 22:16:44.863085 RX Delay -21 -> 252, step: 4
3391 22:16:44.863371
3392 22:16:44.866946 Set Vref, RX VrefLevel [Byte0]: 32
3393 22:16:44.870115 [Byte1]: 32
3394 22:16:44.870483
3395 22:16:44.873292 Set Vref, RX VrefLevel [Byte0]: 33
3396 22:16:44.877013 [Byte1]: 33
3397 22:16:44.880441
3398 22:16:44.880856 Set Vref, RX VrefLevel [Byte0]: 34
3399 22:16:44.883319 [Byte1]: 34
3400 22:16:44.888665
3401 22:16:44.889068 Set Vref, RX VrefLevel [Byte0]: 35
3402 22:16:44.891833 [Byte1]: 35
3403 22:16:44.896567
3404 22:16:44.897052 Set Vref, RX VrefLevel [Byte0]: 36
3405 22:16:44.899323 [Byte1]: 36
3406 22:16:44.903553
3407 22:16:44.907681 Set Vref, RX VrefLevel [Byte0]: 37
3408 22:16:44.908094 [Byte1]: 37
3409 22:16:44.911861
3410 22:16:44.912262 Set Vref, RX VrefLevel [Byte0]: 38
3411 22:16:44.915284 [Byte1]: 38
3412 22:16:44.920232
3413 22:16:44.920635 Set Vref, RX VrefLevel [Byte0]: 39
3414 22:16:44.923154 [Byte1]: 39
3415 22:16:44.927575
3416 22:16:44.927978 Set Vref, RX VrefLevel [Byte0]: 40
3417 22:16:44.931556 [Byte1]: 40
3418 22:16:44.935773
3419 22:16:44.936172 Set Vref, RX VrefLevel [Byte0]: 41
3420 22:16:44.938596 [Byte1]: 41
3421 22:16:44.943530
3422 22:16:44.943939 Set Vref, RX VrefLevel [Byte0]: 42
3423 22:16:44.946916 [Byte1]: 42
3424 22:16:44.951587
3425 22:16:44.951988 Set Vref, RX VrefLevel [Byte0]: 43
3426 22:16:44.954534 [Byte1]: 43
3427 22:16:44.959479
3428 22:16:44.959908 Set Vref, RX VrefLevel [Byte0]: 44
3429 22:16:44.962466 [Byte1]: 44
3430 22:16:44.967525
3431 22:16:44.967928 Set Vref, RX VrefLevel [Byte0]: 45
3432 22:16:44.970719 [Byte1]: 45
3433 22:16:44.974956
3434 22:16:44.975406 Set Vref, RX VrefLevel [Byte0]: 46
3435 22:16:44.978720 [Byte1]: 46
3436 22:16:44.983025
3437 22:16:44.983465 Set Vref, RX VrefLevel [Byte0]: 47
3438 22:16:44.986944 [Byte1]: 47
3439 22:16:44.991146
3440 22:16:44.991557 Set Vref, RX VrefLevel [Byte0]: 48
3441 22:16:44.995007 [Byte1]: 48
3442 22:16:44.999135
3443 22:16:44.999549 Set Vref, RX VrefLevel [Byte0]: 49
3444 22:16:45.002302 [Byte1]: 49
3445 22:16:45.007032
3446 22:16:45.007534 Set Vref, RX VrefLevel [Byte0]: 50
3447 22:16:45.010035 [Byte1]: 50
3448 22:16:45.014658
3449 22:16:45.015106 Set Vref, RX VrefLevel [Byte0]: 51
3450 22:16:45.018319 [Byte1]: 51
3451 22:16:45.022909
3452 22:16:45.023350 Set Vref, RX VrefLevel [Byte0]: 52
3453 22:16:45.026069 [Byte1]: 52
3454 22:16:45.030828
3455 22:16:45.031266 Set Vref, RX VrefLevel [Byte0]: 53
3456 22:16:45.033808 [Byte1]: 53
3457 22:16:45.038527
3458 22:16:45.038937 Set Vref, RX VrefLevel [Byte0]: 54
3459 22:16:45.041929 [Byte1]: 54
3460 22:16:45.046590
3461 22:16:45.047001 Set Vref, RX VrefLevel [Byte0]: 55
3462 22:16:45.050047 [Byte1]: 55
3463 22:16:45.054423
3464 22:16:45.054834 Set Vref, RX VrefLevel [Byte0]: 56
3465 22:16:45.057793 [Byte1]: 56
3466 22:16:45.062405
3467 22:16:45.062815 Set Vref, RX VrefLevel [Byte0]: 57
3468 22:16:45.065914 [Byte1]: 57
3469 22:16:45.070305
3470 22:16:45.070716 Set Vref, RX VrefLevel [Byte0]: 58
3471 22:16:45.073281 [Byte1]: 58
3472 22:16:45.077936
3473 22:16:45.078391 Set Vref, RX VrefLevel [Byte0]: 59
3474 22:16:45.081279 [Byte1]: 59
3475 22:16:45.086203
3476 22:16:45.086585 Set Vref, RX VrefLevel [Byte0]: 60
3477 22:16:45.089768 [Byte1]: 60
3478 22:16:45.094211
3479 22:16:45.097156 Set Vref, RX VrefLevel [Byte0]: 61
3480 22:16:45.100193 [Byte1]: 61
3481 22:16:45.100618
3482 22:16:45.103935 Set Vref, RX VrefLevel [Byte0]: 62
3483 22:16:45.106883 [Byte1]: 62
3484 22:16:45.107386
3485 22:16:45.110271 Set Vref, RX VrefLevel [Byte0]: 63
3486 22:16:45.113526 [Byte1]: 63
3487 22:16:45.117653
3488 22:16:45.118242 Set Vref, RX VrefLevel [Byte0]: 64
3489 22:16:45.121091 [Byte1]: 64
3490 22:16:45.125992
3491 22:16:45.126584 Set Vref, RX VrefLevel [Byte0]: 65
3492 22:16:45.129133 [Byte1]: 65
3493 22:16:45.133818
3494 22:16:45.134223 Set Vref, RX VrefLevel [Byte0]: 66
3495 22:16:45.136820 [Byte1]: 66
3496 22:16:45.141888
3497 22:16:45.142294 Set Vref, RX VrefLevel [Byte0]: 67
3498 22:16:45.145097 [Byte1]: 67
3499 22:16:45.149299
3500 22:16:45.149702 Final RX Vref Byte 0 = 47 to rank0
3501 22:16:45.152968 Final RX Vref Byte 1 = 53 to rank0
3502 22:16:45.156210 Final RX Vref Byte 0 = 47 to rank1
3503 22:16:45.159209 Final RX Vref Byte 1 = 53 to rank1==
3504 22:16:45.162839 Dram Type= 6, Freq= 0, CH_1, rank 0
3505 22:16:45.169437 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3506 22:16:45.169854 ==
3507 22:16:45.170173 DQS Delay:
3508 22:16:45.170471 DQS0 = 0, DQS1 = 0
3509 22:16:45.172981 DQM Delay:
3510 22:16:45.173391 DQM0 = 116, DQM1 = 110
3511 22:16:45.176495 DQ Delay:
3512 22:16:45.178925 DQ0 =118, DQ1 =112, DQ2 =106, DQ3 =112
3513 22:16:45.182687 DQ4 =112, DQ5 =126, DQ6 =126, DQ7 =116
3514 22:16:45.185788 DQ8 =96, DQ9 =102, DQ10 =112, DQ11 =100
3515 22:16:45.188952 DQ12 =118, DQ13 =118, DQ14 =118, DQ15 =118
3516 22:16:45.189366
3517 22:16:45.189708
3518 22:16:45.199015 [DQSOSCAuto] RK0, (LSB)MR18= 0x5f9, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 408 ps
3519 22:16:45.199476 CH1 RK0: MR19=403, MR18=5F9
3520 22:16:45.205785 CH1_RK0: MR19=0x403, MR18=0x5F9, DQSOSC=408, MR23=63, INC=39, DEC=26
3521 22:16:45.206225
3522 22:16:45.209217 ----->DramcWriteLeveling(PI) begin...
3523 22:16:45.209634 ==
3524 22:16:45.212678 Dram Type= 6, Freq= 0, CH_1, rank 1
3525 22:16:45.215726 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3526 22:16:45.218932 ==
3527 22:16:45.219389 Write leveling (Byte 0): 25 => 25
3528 22:16:45.222333 Write leveling (Byte 1): 27 => 27
3529 22:16:45.225382 DramcWriteLeveling(PI) end<-----
3530 22:16:45.225792
3531 22:16:45.226115 ==
3532 22:16:45.228990 Dram Type= 6, Freq= 0, CH_1, rank 1
3533 22:16:45.235809 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3534 22:16:45.236228 ==
3535 22:16:45.238600 [Gating] SW mode calibration
3536 22:16:45.245828 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3537 22:16:45.248491 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3538 22:16:45.255307 0 15 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
3539 22:16:45.258363 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3540 22:16:45.261921 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3541 22:16:45.268194 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3542 22:16:45.271596 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3543 22:16:45.274799 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3544 22:16:45.281697 0 15 24 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
3545 22:16:45.284767 0 15 28 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
3546 22:16:45.288221 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3547 22:16:45.294939 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3548 22:16:45.297886 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3549 22:16:45.301195 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3550 22:16:45.307723 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3551 22:16:45.311224 1 0 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3552 22:16:45.314585 1 0 24 | B1->B0 | 3e3e 2928 | 0 1 | (0 0) (0 0)
3553 22:16:45.321255 1 0 28 | B1->B0 | 4545 4545 | 0 0 | (0 0) (0 0)
3554 22:16:45.324690 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3555 22:16:45.327962 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3556 22:16:45.334178 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3557 22:16:45.337634 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3558 22:16:45.341393 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3559 22:16:45.347710 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3560 22:16:45.351027 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3561 22:16:45.354321 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3562 22:16:45.361058 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3563 22:16:45.364282 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3564 22:16:45.367598 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3565 22:16:45.373879 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3566 22:16:45.377763 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3567 22:16:45.380547 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3568 22:16:45.387467 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3569 22:16:45.390790 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3570 22:16:45.393961 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3571 22:16:45.400502 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3572 22:16:45.403378 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3573 22:16:45.407038 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3574 22:16:45.413753 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3575 22:16:45.416413 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3576 22:16:45.419726 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3577 22:16:45.426674 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3578 22:16:45.426835 Total UI for P1: 0, mck2ui 16
3579 22:16:45.433007 best dqsien dly found for B1: ( 1, 3, 24)
3580 22:16:45.436811 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3581 22:16:45.440122 Total UI for P1: 0, mck2ui 16
3582 22:16:45.442909 best dqsien dly found for B0: ( 1, 3, 26)
3583 22:16:45.446039 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3584 22:16:45.449518 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3585 22:16:45.449620
3586 22:16:45.452706 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3587 22:16:45.456512 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3588 22:16:45.459745 [Gating] SW calibration Done
3589 22:16:45.459830 ==
3590 22:16:45.463206 Dram Type= 6, Freq= 0, CH_1, rank 1
3591 22:16:45.466113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3592 22:16:45.470036 ==
3593 22:16:45.470453 RX Vref Scan: 0
3594 22:16:45.470838
3595 22:16:45.472951 RX Vref 0 -> 0, step: 1
3596 22:16:45.473372
3597 22:16:45.476521 RX Delay -40 -> 252, step: 8
3598 22:16:45.479913 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3599 22:16:45.482910 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3600 22:16:45.486053 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3601 22:16:45.489405 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3602 22:16:45.496249 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3603 22:16:45.499524 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3604 22:16:45.503023 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3605 22:16:45.506262 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3606 22:16:45.509697 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3607 22:16:45.516282 iDelay=200, Bit 9, Center 99 (24 ~ 175) 152
3608 22:16:45.519019 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3609 22:16:45.522739 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3610 22:16:45.526068 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3611 22:16:45.529001 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3612 22:16:45.535704 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3613 22:16:45.538569 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3614 22:16:45.538980 ==
3615 22:16:45.542768 Dram Type= 6, Freq= 0, CH_1, rank 1
3616 22:16:45.545806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3617 22:16:45.546223 ==
3618 22:16:45.548994 DQS Delay:
3619 22:16:45.549402 DQS0 = 0, DQS1 = 0
3620 22:16:45.549724 DQM Delay:
3621 22:16:45.551935 DQM0 = 116, DQM1 = 110
3622 22:16:45.552347 DQ Delay:
3623 22:16:45.555382 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =111
3624 22:16:45.561591 DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =115
3625 22:16:45.564920 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =103
3626 22:16:45.569167 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3627 22:16:45.569585
3628 22:16:45.569911
3629 22:16:45.570213 ==
3630 22:16:45.571885 Dram Type= 6, Freq= 0, CH_1, rank 1
3631 22:16:45.575625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3632 22:16:45.576047 ==
3633 22:16:45.576372
3634 22:16:45.576750
3635 22:16:45.578480 TX Vref Scan disable
3636 22:16:45.581762 == TX Byte 0 ==
3637 22:16:45.584875 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3638 22:16:45.588109 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3639 22:16:45.591795 == TX Byte 1 ==
3640 22:16:45.594965 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3641 22:16:45.598044 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3642 22:16:45.598533 ==
3643 22:16:45.601575 Dram Type= 6, Freq= 0, CH_1, rank 1
3644 22:16:45.604735 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3645 22:16:45.607846 ==
3646 22:16:45.618079 TX Vref=22, minBit 9, minWin=25, winSum=423
3647 22:16:45.621115 TX Vref=24, minBit 3, minWin=26, winSum=431
3648 22:16:45.624674 TX Vref=26, minBit 9, minWin=26, winSum=430
3649 22:16:45.627731 TX Vref=28, minBit 10, minWin=26, winSum=437
3650 22:16:45.631211 TX Vref=30, minBit 9, minWin=26, winSum=435
3651 22:16:45.637751 TX Vref=32, minBit 9, minWin=26, winSum=433
3652 22:16:45.641010 [TxChooseVref] Worse bit 10, Min win 26, Win sum 437, Final Vref 28
3653 22:16:45.641095
3654 22:16:45.643912 Final TX Range 1 Vref 28
3655 22:16:45.643994
3656 22:16:45.644059 ==
3657 22:16:45.647628 Dram Type= 6, Freq= 0, CH_1, rank 1
3658 22:16:45.650676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3659 22:16:45.654226 ==
3660 22:16:45.654307
3661 22:16:45.654369
3662 22:16:45.654426 TX Vref Scan disable
3663 22:16:45.657734 == TX Byte 0 ==
3664 22:16:45.660848 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3665 22:16:45.667388 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3666 22:16:45.667469 == TX Byte 1 ==
3667 22:16:45.670570 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3668 22:16:45.677517 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3669 22:16:45.677599
3670 22:16:45.677674 [DATLAT]
3671 22:16:45.677733 Freq=1200, CH1 RK1
3672 22:16:45.677790
3673 22:16:45.680541 DATLAT Default: 0xd
3674 22:16:45.684540 0, 0xFFFF, sum = 0
3675 22:16:45.684623 1, 0xFFFF, sum = 0
3676 22:16:45.687370 2, 0xFFFF, sum = 0
3677 22:16:45.687452 3, 0xFFFF, sum = 0
3678 22:16:45.690802 4, 0xFFFF, sum = 0
3679 22:16:45.690885 5, 0xFFFF, sum = 0
3680 22:16:45.693935 6, 0xFFFF, sum = 0
3681 22:16:45.694023 7, 0xFFFF, sum = 0
3682 22:16:45.697297 8, 0xFFFF, sum = 0
3683 22:16:45.697385 9, 0xFFFF, sum = 0
3684 22:16:45.700489 10, 0xFFFF, sum = 0
3685 22:16:45.700584 11, 0xFFFF, sum = 0
3686 22:16:45.704081 12, 0x0, sum = 1
3687 22:16:45.704184 13, 0x0, sum = 2
3688 22:16:45.707117 14, 0x0, sum = 3
3689 22:16:45.707257 15, 0x0, sum = 4
3690 22:16:45.710141 best_step = 13
3691 22:16:45.710251
3692 22:16:45.710337 ==
3693 22:16:45.713492 Dram Type= 6, Freq= 0, CH_1, rank 1
3694 22:16:45.716964 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3695 22:16:45.717086 ==
3696 22:16:45.720550 RX Vref Scan: 0
3697 22:16:45.720683
3698 22:16:45.720787 RX Vref 0 -> 0, step: 1
3699 22:16:45.720884
3700 22:16:45.723773 RX Delay -21 -> 252, step: 4
3701 22:16:45.730292 iDelay=199, Bit 0, Center 120 (55 ~ 186) 132
3702 22:16:45.734028 iDelay=199, Bit 1, Center 110 (43 ~ 178) 136
3703 22:16:45.736726 iDelay=199, Bit 2, Center 106 (43 ~ 170) 128
3704 22:16:45.740347 iDelay=199, Bit 3, Center 114 (51 ~ 178) 128
3705 22:16:45.746530 iDelay=199, Bit 4, Center 114 (47 ~ 182) 136
3706 22:16:45.750260 iDelay=199, Bit 5, Center 126 (63 ~ 190) 128
3707 22:16:45.753195 iDelay=199, Bit 6, Center 130 (63 ~ 198) 136
3708 22:16:45.756282 iDelay=199, Bit 7, Center 112 (47 ~ 178) 132
3709 22:16:45.759892 iDelay=199, Bit 8, Center 96 (31 ~ 162) 132
3710 22:16:45.766823 iDelay=199, Bit 9, Center 100 (35 ~ 166) 132
3711 22:16:45.769936 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
3712 22:16:45.773012 iDelay=199, Bit 11, Center 100 (35 ~ 166) 132
3713 22:16:45.776440 iDelay=199, Bit 12, Center 118 (51 ~ 186) 136
3714 22:16:45.779774 iDelay=199, Bit 13, Center 118 (51 ~ 186) 136
3715 22:16:45.786168 iDelay=199, Bit 14, Center 118 (51 ~ 186) 136
3716 22:16:45.790022 iDelay=199, Bit 15, Center 120 (51 ~ 190) 140
3717 22:16:45.790498 ==
3718 22:16:45.792715 Dram Type= 6, Freq= 0, CH_1, rank 1
3719 22:16:45.796093 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3720 22:16:45.796566 ==
3721 22:16:45.799343 DQS Delay:
3722 22:16:45.799814 DQS0 = 0, DQS1 = 0
3723 22:16:45.800142 DQM Delay:
3724 22:16:45.803124 DQM0 = 116, DQM1 = 110
3725 22:16:45.803547 DQ Delay:
3726 22:16:45.806311 DQ0 =120, DQ1 =110, DQ2 =106, DQ3 =114
3727 22:16:45.809567 DQ4 =114, DQ5 =126, DQ6 =130, DQ7 =112
3728 22:16:45.816058 DQ8 =96, DQ9 =100, DQ10 =110, DQ11 =100
3729 22:16:45.819507 DQ12 =118, DQ13 =118, DQ14 =118, DQ15 =120
3730 22:16:45.819926
3731 22:16:45.820434
3732 22:16:45.825689 [DQSOSCAuto] RK1, (LSB)MR18= 0xf7f1, (MSB)MR19= 0x303, tDQSOscB0 = 416 ps tDQSOscB1 = 413 ps
3733 22:16:45.828901 CH1 RK1: MR19=303, MR18=F7F1
3734 22:16:45.835365 CH1_RK1: MR19=0x303, MR18=0xF7F1, DQSOSC=413, MR23=63, INC=38, DEC=25
3735 22:16:45.838925 [RxdqsGatingPostProcess] freq 1200
3736 22:16:45.844954 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3737 22:16:45.848702 best DQS0 dly(2T, 0.5T) = (0, 11)
3738 22:16:45.849123 best DQS1 dly(2T, 0.5T) = (0, 11)
3739 22:16:45.851932 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3740 22:16:45.855186 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3741 22:16:45.858464 best DQS0 dly(2T, 0.5T) = (0, 11)
3742 22:16:45.861867 best DQS1 dly(2T, 0.5T) = (0, 11)
3743 22:16:45.864651 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3744 22:16:45.868215 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3745 22:16:45.871439 Pre-setting of DQS Precalculation
3746 22:16:45.878244 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3747 22:16:45.885032 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3748 22:16:45.890919 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3749 22:16:45.891373
3750 22:16:45.891696
3751 22:16:45.894509 [Calibration Summary] 2400 Mbps
3752 22:16:45.894919 CH 0, Rank 0
3753 22:16:45.897680 SW Impedance : PASS
3754 22:16:45.901231 DUTY Scan : NO K
3755 22:16:45.901645 ZQ Calibration : PASS
3756 22:16:45.904344 Jitter Meter : NO K
3757 22:16:45.908056 CBT Training : PASS
3758 22:16:45.908468 Write leveling : PASS
3759 22:16:45.911144 RX DQS gating : PASS
3760 22:16:45.914360 RX DQ/DQS(RDDQC) : PASS
3761 22:16:45.914773 TX DQ/DQS : PASS
3762 22:16:45.917576 RX DATLAT : PASS
3763 22:16:45.920896 RX DQ/DQS(Engine): PASS
3764 22:16:45.921315 TX OE : NO K
3765 22:16:45.924337 All Pass.
3766 22:16:45.924774
3767 22:16:45.925156 CH 0, Rank 1
3768 22:16:45.927939 SW Impedance : PASS
3769 22:16:45.928402 DUTY Scan : NO K
3770 22:16:45.931029 ZQ Calibration : PASS
3771 22:16:45.934210 Jitter Meter : NO K
3772 22:16:45.934722 CBT Training : PASS
3773 22:16:45.937546 Write leveling : PASS
3774 22:16:45.940836 RX DQS gating : PASS
3775 22:16:45.941212 RX DQ/DQS(RDDQC) : PASS
3776 22:16:45.944276 TX DQ/DQS : PASS
3777 22:16:45.947323 RX DATLAT : PASS
3778 22:16:45.947804 RX DQ/DQS(Engine): PASS
3779 22:16:45.950259 TX OE : NO K
3780 22:16:45.950682 All Pass.
3781 22:16:45.951005
3782 22:16:45.954113 CH 1, Rank 0
3783 22:16:45.954520 SW Impedance : PASS
3784 22:16:45.957440 DUTY Scan : NO K
3785 22:16:45.960244 ZQ Calibration : PASS
3786 22:16:45.960653 Jitter Meter : NO K
3787 22:16:45.963792 CBT Training : PASS
3788 22:16:45.964203 Write leveling : PASS
3789 22:16:45.967107 RX DQS gating : PASS
3790 22:16:45.970279 RX DQ/DQS(RDDQC) : PASS
3791 22:16:45.970688 TX DQ/DQS : PASS
3792 22:16:45.973779 RX DATLAT : PASS
3793 22:16:45.977070 RX DQ/DQS(Engine): PASS
3794 22:16:45.977476 TX OE : NO K
3795 22:16:45.979916 All Pass.
3796 22:16:45.980331
3797 22:16:45.980649 CH 1, Rank 1
3798 22:16:45.983325 SW Impedance : PASS
3799 22:16:45.983762 DUTY Scan : NO K
3800 22:16:45.986853 ZQ Calibration : PASS
3801 22:16:45.989878 Jitter Meter : NO K
3802 22:16:45.990296 CBT Training : PASS
3803 22:16:45.993416 Write leveling : PASS
3804 22:16:45.996829 RX DQS gating : PASS
3805 22:16:45.997239 RX DQ/DQS(RDDQC) : PASS
3806 22:16:46.000173 TX DQ/DQS : PASS
3807 22:16:46.002985 RX DATLAT : PASS
3808 22:16:46.003543 RX DQ/DQS(Engine): PASS
3809 22:16:46.006985 TX OE : NO K
3810 22:16:46.007494 All Pass.
3811 22:16:46.007830
3812 22:16:46.009925 DramC Write-DBI off
3813 22:16:46.013410 PER_BANK_REFRESH: Hybrid Mode
3814 22:16:46.013866 TX_TRACKING: ON
3815 22:16:46.023164 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3816 22:16:46.026498 [FAST_K] Save calibration result to emmc
3817 22:16:46.029892 dramc_set_vcore_voltage set vcore to 650000
3818 22:16:46.032858 Read voltage for 600, 5
3819 22:16:46.033330 Vio18 = 0
3820 22:16:46.033658 Vcore = 650000
3821 22:16:46.036400 Vdram = 0
3822 22:16:46.036866 Vddq = 0
3823 22:16:46.037202 Vmddr = 0
3824 22:16:46.043119 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3825 22:16:46.046589 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3826 22:16:46.049603 MEM_TYPE=3, freq_sel=19
3827 22:16:46.053082 sv_algorithm_assistance_LP4_1600
3828 22:16:46.055937 ============ PULL DRAM RESETB DOWN ============
3829 22:16:46.059638 ========== PULL DRAM RESETB DOWN end =========
3830 22:16:46.066209 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3831 22:16:46.069210 ===================================
3832 22:16:46.072804 LPDDR4 DRAM CONFIGURATION
3833 22:16:46.076302 ===================================
3834 22:16:46.076721 EX_ROW_EN[0] = 0x0
3835 22:16:46.079677 EX_ROW_EN[1] = 0x0
3836 22:16:46.080093 LP4Y_EN = 0x0
3837 22:16:46.082705 WORK_FSP = 0x0
3838 22:16:46.083170 WL = 0x2
3839 22:16:46.085998 RL = 0x2
3840 22:16:46.086412 BL = 0x2
3841 22:16:46.089628 RPST = 0x0
3842 22:16:46.090043 RD_PRE = 0x0
3843 22:16:46.092430 WR_PRE = 0x1
3844 22:16:46.092843 WR_PST = 0x0
3845 22:16:46.096026 DBI_WR = 0x0
3846 22:16:46.096444 DBI_RD = 0x0
3847 22:16:46.099151 OTF = 0x1
3848 22:16:46.102898 ===================================
3849 22:16:46.105993 ===================================
3850 22:16:46.106409 ANA top config
3851 22:16:46.109394 ===================================
3852 22:16:46.112992 DLL_ASYNC_EN = 0
3853 22:16:46.115603 ALL_SLAVE_EN = 1
3854 22:16:46.118799 NEW_RANK_MODE = 1
3855 22:16:46.122128 DLL_IDLE_MODE = 1
3856 22:16:46.122544 LP45_APHY_COMB_EN = 1
3857 22:16:46.125279 TX_ODT_DIS = 1
3858 22:16:46.128851 NEW_8X_MODE = 1
3859 22:16:46.131991 ===================================
3860 22:16:46.135444 ===================================
3861 22:16:46.138706 data_rate = 1200
3862 22:16:46.142319 CKR = 1
3863 22:16:46.142737 DQ_P2S_RATIO = 8
3864 22:16:46.145446 ===================================
3865 22:16:46.148452 CA_P2S_RATIO = 8
3866 22:16:46.151979 DQ_CA_OPEN = 0
3867 22:16:46.154883 DQ_SEMI_OPEN = 0
3868 22:16:46.158444 CA_SEMI_OPEN = 0
3869 22:16:46.162290 CA_FULL_RATE = 0
3870 22:16:46.165295 DQ_CKDIV4_EN = 1
3871 22:16:46.165734 CA_CKDIV4_EN = 1
3872 22:16:46.168246 CA_PREDIV_EN = 0
3873 22:16:46.171363 PH8_DLY = 0
3874 22:16:46.175023 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3875 22:16:46.177902 DQ_AAMCK_DIV = 4
3876 22:16:46.181498 CA_AAMCK_DIV = 4
3877 22:16:46.181950 CA_ADMCK_DIV = 4
3878 22:16:46.184883 DQ_TRACK_CA_EN = 0
3879 22:16:46.187692 CA_PICK = 600
3880 22:16:46.191924 CA_MCKIO = 600
3881 22:16:46.195134 MCKIO_SEMI = 0
3882 22:16:46.197604 PLL_FREQ = 2288
3883 22:16:46.201255 DQ_UI_PI_RATIO = 32
3884 22:16:46.201672 CA_UI_PI_RATIO = 0
3885 22:16:46.204399 ===================================
3886 22:16:46.208000 ===================================
3887 22:16:46.211413 memory_type:LPDDR4
3888 22:16:46.214194 GP_NUM : 10
3889 22:16:46.214607 SRAM_EN : 1
3890 22:16:46.217483 MD32_EN : 0
3891 22:16:46.221075 ===================================
3892 22:16:46.224122 [ANA_INIT] >>>>>>>>>>>>>>
3893 22:16:46.227968 <<<<<< [CONFIGURE PHASE]: ANA_TX
3894 22:16:46.230917 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3895 22:16:46.234443 ===================================
3896 22:16:46.234859 data_rate = 1200,PCW = 0X5800
3897 22:16:46.237766 ===================================
3898 22:16:46.241045 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3899 22:16:46.247265 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3900 22:16:46.254274 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3901 22:16:46.257626 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3902 22:16:46.260120 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3903 22:16:46.263622 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3904 22:16:46.266941 [ANA_INIT] flow start
3905 22:16:46.270151 [ANA_INIT] PLL >>>>>>>>
3906 22:16:46.270272 [ANA_INIT] PLL <<<<<<<<
3907 22:16:46.273742 [ANA_INIT] MIDPI >>>>>>>>
3908 22:16:46.276684 [ANA_INIT] MIDPI <<<<<<<<
3909 22:16:46.276818 [ANA_INIT] DLL >>>>>>>>
3910 22:16:46.280387 [ANA_INIT] flow end
3911 22:16:46.283885 ============ LP4 DIFF to SE enter ============
3912 22:16:46.290659 ============ LP4 DIFF to SE exit ============
3913 22:16:46.290859 [ANA_INIT] <<<<<<<<<<<<<
3914 22:16:46.293622 [Flow] Enable top DCM control >>>>>
3915 22:16:46.296935 [Flow] Enable top DCM control <<<<<
3916 22:16:46.299996 Enable DLL master slave shuffle
3917 22:16:46.306866 ==============================================================
3918 22:16:46.307311 Gating Mode config
3919 22:16:46.313307 ==============================================================
3920 22:16:46.316506 Config description:
3921 22:16:46.323587 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3922 22:16:46.332980 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3923 22:16:46.336649 SELPH_MODE 0: By rank 1: By Phase
3924 22:16:46.343225 ==============================================================
3925 22:16:46.346291 GAT_TRACK_EN = 1
3926 22:16:46.346706 RX_GATING_MODE = 2
3927 22:16:46.349623 RX_GATING_TRACK_MODE = 2
3928 22:16:46.352738 SELPH_MODE = 1
3929 22:16:46.356556 PICG_EARLY_EN = 1
3930 22:16:46.359649 VALID_LAT_VALUE = 1
3931 22:16:46.366398 ==============================================================
3932 22:16:46.369450 Enter into Gating configuration >>>>
3933 22:16:46.372429 Exit from Gating configuration <<<<
3934 22:16:46.375933 Enter into DVFS_PRE_config >>>>>
3935 22:16:46.385850 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3936 22:16:46.389155 Exit from DVFS_PRE_config <<<<<
3937 22:16:46.392645 Enter into PICG configuration >>>>
3938 22:16:46.395421 Exit from PICG configuration <<<<
3939 22:16:46.399251 [RX_INPUT] configuration >>>>>
3940 22:16:46.402371 [RX_INPUT] configuration <<<<<
3941 22:16:46.405705 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3942 22:16:46.412195 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3943 22:16:46.418853 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3944 22:16:46.425794 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3945 22:16:46.431982 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3946 22:16:46.435307 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3947 22:16:46.442136 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3948 22:16:46.445512 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3949 22:16:46.448986 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3950 22:16:46.452230 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3951 22:16:46.455217 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3952 22:16:46.461977 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3953 22:16:46.465996 ===================================
3954 22:16:46.468869 LPDDR4 DRAM CONFIGURATION
3955 22:16:46.472115 ===================================
3956 22:16:46.472611 EX_ROW_EN[0] = 0x0
3957 22:16:46.475493 EX_ROW_EN[1] = 0x0
3958 22:16:46.475931 LP4Y_EN = 0x0
3959 22:16:46.478425 WORK_FSP = 0x0
3960 22:16:46.478833 WL = 0x2
3961 22:16:46.481914 RL = 0x2
3962 22:16:46.482339 BL = 0x2
3963 22:16:46.485093 RPST = 0x0
3964 22:16:46.485502 RD_PRE = 0x0
3965 22:16:46.488279 WR_PRE = 0x1
3966 22:16:46.488774 WR_PST = 0x0
3967 22:16:46.491593 DBI_WR = 0x0
3968 22:16:46.492007 DBI_RD = 0x0
3969 22:16:46.495202 OTF = 0x1
3970 22:16:46.498183 ===================================
3971 22:16:46.501540 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3972 22:16:46.505102 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3973 22:16:46.511652 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3974 22:16:46.514253 ===================================
3975 22:16:46.517578 LPDDR4 DRAM CONFIGURATION
3976 22:16:46.521080 ===================================
3977 22:16:46.521183 EX_ROW_EN[0] = 0x10
3978 22:16:46.524344 EX_ROW_EN[1] = 0x0
3979 22:16:46.524418 LP4Y_EN = 0x0
3980 22:16:46.527511 WORK_FSP = 0x0
3981 22:16:46.527581 WL = 0x2
3982 22:16:46.531455 RL = 0x2
3983 22:16:46.531524 BL = 0x2
3984 22:16:46.534278 RPST = 0x0
3985 22:16:46.534346 RD_PRE = 0x0
3986 22:16:46.537389 WR_PRE = 0x1
3987 22:16:46.537457 WR_PST = 0x0
3988 22:16:46.541427 DBI_WR = 0x0
3989 22:16:46.544245 DBI_RD = 0x0
3990 22:16:46.544312 OTF = 0x1
3991 22:16:46.547647 ===================================
3992 22:16:46.554031 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3993 22:16:46.557538 nWR fixed to 30
3994 22:16:46.560638 [ModeRegInit_LP4] CH0 RK0
3995 22:16:46.560710 [ModeRegInit_LP4] CH0 RK1
3996 22:16:46.564037 [ModeRegInit_LP4] CH1 RK0
3997 22:16:46.567123 [ModeRegInit_LP4] CH1 RK1
3998 22:16:46.567193 match AC timing 17
3999 22:16:46.574025 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
4000 22:16:46.577077 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4001 22:16:46.580722 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
4002 22:16:46.587180 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
4003 22:16:46.590453 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
4004 22:16:46.590552 ==
4005 22:16:46.593529 Dram Type= 6, Freq= 0, CH_0, rank 0
4006 22:16:46.596795 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4007 22:16:46.600420 ==
4008 22:16:46.603367 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4009 22:16:46.610116 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4010 22:16:46.613632 [CA 0] Center 36 (6~66) winsize 61
4011 22:16:46.616879 [CA 1] Center 36 (6~66) winsize 61
4012 22:16:46.619759 [CA 2] Center 34 (3~65) winsize 63
4013 22:16:46.623487 [CA 3] Center 34 (3~65) winsize 63
4014 22:16:46.626867 [CA 4] Center 33 (3~64) winsize 62
4015 22:16:46.630041 [CA 5] Center 33 (2~64) winsize 63
4016 22:16:46.630122
4017 22:16:46.633779 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4018 22:16:46.633852
4019 22:16:46.636724 [CATrainingPosCal] consider 1 rank data
4020 22:16:46.640120 u2DelayCellTimex100 = 270/100 ps
4021 22:16:46.643155 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4022 22:16:46.646417 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4023 22:16:46.649584 CA2 delay=34 (3~65),Diff = 1 PI (9 cell)
4024 22:16:46.656163 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4025 22:16:46.659415 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4026 22:16:46.663341 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4027 22:16:46.663421
4028 22:16:46.666281 CA PerBit enable=1, Macro0, CA PI delay=33
4029 22:16:46.666361
4030 22:16:46.669388 [CBTSetCACLKResult] CA Dly = 33
4031 22:16:46.669469 CS Dly: 5 (0~36)
4032 22:16:46.669535 ==
4033 22:16:46.672720 Dram Type= 6, Freq= 0, CH_0, rank 1
4034 22:16:46.680264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4035 22:16:46.680345 ==
4036 22:16:46.682773 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4037 22:16:46.689402 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4038 22:16:46.693338 [CA 0] Center 35 (5~66) winsize 62
4039 22:16:46.696474 [CA 1] Center 36 (6~66) winsize 61
4040 22:16:46.700081 [CA 2] Center 34 (4~64) winsize 61
4041 22:16:46.703513 [CA 3] Center 33 (3~64) winsize 62
4042 22:16:46.706481 [CA 4] Center 33 (2~64) winsize 63
4043 22:16:46.710043 [CA 5] Center 33 (2~64) winsize 63
4044 22:16:46.710455
4045 22:16:46.713095 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4046 22:16:46.713507
4047 22:16:46.716233 [CATrainingPosCal] consider 2 rank data
4048 22:16:46.719804 u2DelayCellTimex100 = 270/100 ps
4049 22:16:46.722655 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4050 22:16:46.729202 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4051 22:16:46.733037 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
4052 22:16:46.736211 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4053 22:16:46.739108 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4054 22:16:46.742876 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4055 22:16:46.743320
4056 22:16:46.745996 CA PerBit enable=1, Macro0, CA PI delay=33
4057 22:16:46.746411
4058 22:16:46.749420 [CBTSetCACLKResult] CA Dly = 33
4059 22:16:46.752496 CS Dly: 5 (0~36)
4060 22:16:46.752906
4061 22:16:46.755704 ----->DramcWriteLeveling(PI) begin...
4062 22:16:46.756119 ==
4063 22:16:46.759494 Dram Type= 6, Freq= 0, CH_0, rank 0
4064 22:16:46.762463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4065 22:16:46.762878 ==
4066 22:16:46.765721 Write leveling (Byte 0): 31 => 31
4067 22:16:46.769197 Write leveling (Byte 1): 29 => 29
4068 22:16:46.772209 DramcWriteLeveling(PI) end<-----
4069 22:16:46.772624
4070 22:16:46.772947 ==
4071 22:16:46.776360 Dram Type= 6, Freq= 0, CH_0, rank 0
4072 22:16:46.778836 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4073 22:16:46.779270 ==
4074 22:16:46.782021 [Gating] SW mode calibration
4075 22:16:46.788773 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4076 22:16:46.795372 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4077 22:16:46.798596 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4078 22:16:46.801760 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4079 22:16:46.808541 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4080 22:16:46.811757 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4081 22:16:46.815527 0 9 16 | B1->B0 | 3030 2a2a | 1 1 | (0 0) (0 0)
4082 22:16:46.821909 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4083 22:16:46.824955 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4084 22:16:46.831844 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4085 22:16:46.834567 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4086 22:16:46.837790 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4087 22:16:46.845272 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4088 22:16:46.847923 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4089 22:16:46.851565 0 10 16 | B1->B0 | 3535 3e3e | 0 0 | (0 0) (0 0)
4090 22:16:46.854452 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4091 22:16:46.861168 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4092 22:16:46.864561 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4093 22:16:46.867981 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4094 22:16:46.874251 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4095 22:16:46.877521 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4096 22:16:46.880782 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4097 22:16:46.887847 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4098 22:16:46.891162 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4099 22:16:46.894348 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4100 22:16:46.901495 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4101 22:16:46.904107 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4102 22:16:46.907212 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4103 22:16:46.914256 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4104 22:16:46.917575 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4105 22:16:46.920687 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4106 22:16:46.927573 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4107 22:16:46.930799 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4108 22:16:46.933992 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4109 22:16:46.940192 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4110 22:16:46.943652 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4111 22:16:46.946927 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4112 22:16:46.953819 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4113 22:16:46.957246 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4114 22:16:46.960284 Total UI for P1: 0, mck2ui 16
4115 22:16:46.963507 best dqsien dly found for B0: ( 0, 13, 12)
4116 22:16:46.966997 Total UI for P1: 0, mck2ui 16
4117 22:16:46.969992 best dqsien dly found for B1: ( 0, 13, 14)
4118 22:16:46.973603 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4119 22:16:46.976817 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4120 22:16:46.977199
4121 22:16:46.979866 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4122 22:16:46.986553 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4123 22:16:46.986965 [Gating] SW calibration Done
4124 22:16:46.987363 ==
4125 22:16:46.989962 Dram Type= 6, Freq= 0, CH_0, rank 0
4126 22:16:46.996853 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4127 22:16:46.997267 ==
4128 22:16:46.997593 RX Vref Scan: 0
4129 22:16:46.997893
4130 22:16:47.000146 RX Vref 0 -> 0, step: 1
4131 22:16:47.000666
4132 22:16:47.003540 RX Delay -230 -> 252, step: 16
4133 22:16:47.006659 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4134 22:16:47.010199 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4135 22:16:47.013330 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4136 22:16:47.019668 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4137 22:16:47.022963 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4138 22:16:47.026480 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4139 22:16:47.029998 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4140 22:16:47.036431 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4141 22:16:47.039515 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4142 22:16:47.042672 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4143 22:16:47.046068 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4144 22:16:47.053227 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4145 22:16:47.056227 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4146 22:16:47.059558 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4147 22:16:47.062844 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4148 22:16:47.069159 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4149 22:16:47.069573 ==
4150 22:16:47.072741 Dram Type= 6, Freq= 0, CH_0, rank 0
4151 22:16:47.075629 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4152 22:16:47.076046 ==
4153 22:16:47.076369 DQS Delay:
4154 22:16:47.078871 DQS0 = 0, DQS1 = 0
4155 22:16:47.079392 DQM Delay:
4156 22:16:47.082634 DQM0 = 42, DQM1 = 30
4157 22:16:47.083042 DQ Delay:
4158 22:16:47.085695 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =33
4159 22:16:47.089115 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49
4160 22:16:47.092263 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4161 22:16:47.095598 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4162 22:16:47.096006
4163 22:16:47.096325
4164 22:16:47.096621 ==
4165 22:16:47.099198 Dram Type= 6, Freq= 0, CH_0, rank 0
4166 22:16:47.102212 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4167 22:16:47.102625 ==
4168 22:16:47.105692
4169 22:16:47.106102
4170 22:16:47.106420 TX Vref Scan disable
4171 22:16:47.108869 == TX Byte 0 ==
4172 22:16:47.112626 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4173 22:16:47.115667 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4174 22:16:47.118597 == TX Byte 1 ==
4175 22:16:47.122337 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4176 22:16:47.125503 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4177 22:16:47.128927 ==
4178 22:16:47.131919 Dram Type= 6, Freq= 0, CH_0, rank 0
4179 22:16:47.135210 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4180 22:16:47.135623 ==
4181 22:16:47.135949
4182 22:16:47.136247
4183 22:16:47.138419 TX Vref Scan disable
4184 22:16:47.138988 == TX Byte 0 ==
4185 22:16:47.145074 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4186 22:16:47.148583 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4187 22:16:47.151565 == TX Byte 1 ==
4188 22:16:47.155039 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4189 22:16:47.158345 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4190 22:16:47.158761
4191 22:16:47.159138 [DATLAT]
4192 22:16:47.161562 Freq=600, CH0 RK0
4193 22:16:47.161979
4194 22:16:47.164949 DATLAT Default: 0x9
4195 22:16:47.165364 0, 0xFFFF, sum = 0
4196 22:16:47.168105 1, 0xFFFF, sum = 0
4197 22:16:47.168530 2, 0xFFFF, sum = 0
4198 22:16:47.171666 3, 0xFFFF, sum = 0
4199 22:16:47.172089 4, 0xFFFF, sum = 0
4200 22:16:47.175093 5, 0xFFFF, sum = 0
4201 22:16:47.175536 6, 0xFFFF, sum = 0
4202 22:16:47.178015 7, 0xFFFF, sum = 0
4203 22:16:47.178437 8, 0x0, sum = 1
4204 22:16:47.181615 9, 0x0, sum = 2
4205 22:16:47.182038 10, 0x0, sum = 3
4206 22:16:47.184725 11, 0x0, sum = 4
4207 22:16:47.185206 best_step = 9
4208 22:16:47.185703
4209 22:16:47.186025 ==
4210 22:16:47.187665 Dram Type= 6, Freq= 0, CH_0, rank 0
4211 22:16:47.191214 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4212 22:16:47.191633 ==
4213 22:16:47.195053 RX Vref Scan: 1
4214 22:16:47.195520
4215 22:16:47.197765 RX Vref 0 -> 0, step: 1
4216 22:16:47.198181
4217 22:16:47.198509 RX Delay -195 -> 252, step: 8
4218 22:16:47.198818
4219 22:16:47.201317 Set Vref, RX VrefLevel [Byte0]: 58
4220 22:16:47.204506 [Byte1]: 51
4221 22:16:47.209151
4222 22:16:47.209565 Final RX Vref Byte 0 = 58 to rank0
4223 22:16:47.212276 Final RX Vref Byte 1 = 51 to rank0
4224 22:16:47.215636 Final RX Vref Byte 0 = 58 to rank1
4225 22:16:47.219029 Final RX Vref Byte 1 = 51 to rank1==
4226 22:16:47.221848 Dram Type= 6, Freq= 0, CH_0, rank 0
4227 22:16:47.229354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4228 22:16:47.229764 ==
4229 22:16:47.230111 DQS Delay:
4230 22:16:47.232122 DQS0 = 0, DQS1 = 0
4231 22:16:47.232497 DQM Delay:
4232 22:16:47.232814 DQM0 = 43, DQM1 = 33
4233 22:16:47.235306 DQ Delay:
4234 22:16:47.238638 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4235 22:16:47.242123 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =52
4236 22:16:47.245415 DQ8 =24, DQ9 =24, DQ10 =32, DQ11 =28
4237 22:16:47.248159 DQ12 =36, DQ13 =36, DQ14 =44, DQ15 =40
4238 22:16:47.248569
4239 22:16:47.248888
4240 22:16:47.254700 [DQSOSCAuto] RK0, (LSB)MR18= 0x6239, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 391 ps
4241 22:16:47.257897 CH0 RK0: MR19=808, MR18=6239
4242 22:16:47.264984 CH0_RK0: MR19=0x808, MR18=0x6239, DQSOSC=391, MR23=63, INC=171, DEC=114
4243 22:16:47.265405
4244 22:16:47.267965 ----->DramcWriteLeveling(PI) begin...
4245 22:16:47.268423 ==
4246 22:16:47.271441 Dram Type= 6, Freq= 0, CH_0, rank 1
4247 22:16:47.274700 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4248 22:16:47.275157 ==
4249 22:16:47.277722 Write leveling (Byte 0): 33 => 33
4250 22:16:47.281157 Write leveling (Byte 1): 33 => 33
4251 22:16:47.284199 DramcWriteLeveling(PI) end<-----
4252 22:16:47.284625
4253 22:16:47.285053 ==
4254 22:16:47.287428 Dram Type= 6, Freq= 0, CH_0, rank 1
4255 22:16:47.294505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4256 22:16:47.294919 ==
4257 22:16:47.295337 [Gating] SW mode calibration
4258 22:16:47.304334 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4259 22:16:47.307842 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4260 22:16:47.313921 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4261 22:16:47.317562 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4262 22:16:47.320890 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4263 22:16:47.327106 0 9 12 | B1->B0 | 3434 3434 | 0 0 | (0 0) (0 1)
4264 22:16:47.330851 0 9 16 | B1->B0 | 3030 2424 | 0 0 | (1 1) (0 0)
4265 22:16:47.333627 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4266 22:16:47.340464 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4267 22:16:47.343643 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4268 22:16:47.347165 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4269 22:16:47.353751 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4270 22:16:47.357008 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4271 22:16:47.360263 0 10 12 | B1->B0 | 2424 2626 | 0 0 | (0 0) (0 0)
4272 22:16:47.366776 0 10 16 | B1->B0 | 3939 4343 | 0 0 | (1 1) (0 0)
4273 22:16:47.370077 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4274 22:16:47.373252 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4275 22:16:47.380031 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4276 22:16:47.382980 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4277 22:16:47.386561 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4278 22:16:47.393312 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4279 22:16:47.396403 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4280 22:16:47.400164 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4281 22:16:47.406485 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4282 22:16:47.409627 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4283 22:16:47.413686 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4284 22:16:47.419602 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4285 22:16:47.422628 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4286 22:16:47.426448 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4287 22:16:47.432670 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4288 22:16:47.435888 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4289 22:16:47.439585 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4290 22:16:47.446045 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4291 22:16:47.448932 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4292 22:16:47.452355 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4293 22:16:47.458973 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4294 22:16:47.462267 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4295 22:16:47.465757 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4296 22:16:47.472542 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4297 22:16:47.472975 Total UI for P1: 0, mck2ui 16
4298 22:16:47.478976 best dqsien dly found for B0: ( 0, 13, 12)
4299 22:16:47.479453 Total UI for P1: 0, mck2ui 16
4300 22:16:47.482411 best dqsien dly found for B1: ( 0, 13, 12)
4301 22:16:47.488775 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4302 22:16:47.491782 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4303 22:16:47.492217
4304 22:16:47.495025 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4305 22:16:47.498847 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4306 22:16:47.501938 [Gating] SW calibration Done
4307 22:16:47.502348 ==
4308 22:16:47.505440 Dram Type= 6, Freq= 0, CH_0, rank 1
4309 22:16:47.508601 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4310 22:16:47.509062 ==
4311 22:16:47.512089 RX Vref Scan: 0
4312 22:16:47.512521
4313 22:16:47.512844 RX Vref 0 -> 0, step: 1
4314 22:16:47.513145
4315 22:16:47.514883 RX Delay -230 -> 252, step: 16
4316 22:16:47.521726 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4317 22:16:47.525137 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4318 22:16:47.528178 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4319 22:16:47.531658 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4320 22:16:47.534985 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4321 22:16:47.541454 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4322 22:16:47.544590 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4323 22:16:47.548263 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4324 22:16:47.551561 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4325 22:16:47.557971 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4326 22:16:47.561274 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4327 22:16:47.564596 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4328 22:16:47.567657 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4329 22:16:47.574164 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4330 22:16:47.577948 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4331 22:16:47.580845 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4332 22:16:47.581256 ==
4333 22:16:47.584101 Dram Type= 6, Freq= 0, CH_0, rank 1
4334 22:16:47.590853 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4335 22:16:47.591325 ==
4336 22:16:47.591653 DQS Delay:
4337 22:16:47.591953 DQS0 = 0, DQS1 = 0
4338 22:16:47.594155 DQM Delay:
4339 22:16:47.594566 DQM0 = 42, DQM1 = 33
4340 22:16:47.597877 DQ Delay:
4341 22:16:47.600976 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =33
4342 22:16:47.601452 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4343 22:16:47.603903 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4344 22:16:47.610519 DQ12 =33, DQ13 =41, DQ14 =49, DQ15 =41
4345 22:16:47.610978
4346 22:16:47.611336
4347 22:16:47.611685 ==
4348 22:16:47.614275 Dram Type= 6, Freq= 0, CH_0, rank 1
4349 22:16:47.617061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4350 22:16:47.617545 ==
4351 22:16:47.617880
4352 22:16:47.618233
4353 22:16:47.620232 TX Vref Scan disable
4354 22:16:47.620648 == TX Byte 0 ==
4355 22:16:47.627359 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4356 22:16:47.630699 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4357 22:16:47.631190 == TX Byte 1 ==
4358 22:16:47.637132 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4359 22:16:47.640187 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4360 22:16:47.640591 ==
4361 22:16:47.643729 Dram Type= 6, Freq= 0, CH_0, rank 1
4362 22:16:47.646602 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4363 22:16:47.647185 ==
4364 22:16:47.649796
4365 22:16:47.650247
4366 22:16:47.650657 TX Vref Scan disable
4367 22:16:47.653826 == TX Byte 0 ==
4368 22:16:47.657034 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4369 22:16:47.663426 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4370 22:16:47.663834 == TX Byte 1 ==
4371 22:16:47.666955 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4372 22:16:47.673755 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4373 22:16:47.674265
4374 22:16:47.674726 [DATLAT]
4375 22:16:47.675190 Freq=600, CH0 RK1
4376 22:16:47.675592
4377 22:16:47.676920 DATLAT Default: 0x9
4378 22:16:47.677351 0, 0xFFFF, sum = 0
4379 22:16:47.680166 1, 0xFFFF, sum = 0
4380 22:16:47.683728 2, 0xFFFF, sum = 0
4381 22:16:47.684196 3, 0xFFFF, sum = 0
4382 22:16:47.687045 4, 0xFFFF, sum = 0
4383 22:16:47.687575 5, 0xFFFF, sum = 0
4384 22:16:47.690079 6, 0xFFFF, sum = 0
4385 22:16:47.690637 7, 0xFFFF, sum = 0
4386 22:16:47.693159 8, 0x0, sum = 1
4387 22:16:47.693620 9, 0x0, sum = 2
4388 22:16:47.693949 10, 0x0, sum = 3
4389 22:16:47.696438 11, 0x0, sum = 4
4390 22:16:47.696849 best_step = 9
4391 22:16:47.697218
4392 22:16:47.699589 ==
4393 22:16:47.699998 Dram Type= 6, Freq= 0, CH_0, rank 1
4394 22:16:47.706551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4395 22:16:47.706963 ==
4396 22:16:47.707361 RX Vref Scan: 0
4397 22:16:47.707690
4398 22:16:47.709764 RX Vref 0 -> 0, step: 1
4399 22:16:47.710313
4400 22:16:47.713136 RX Delay -195 -> 252, step: 8
4401 22:16:47.719567 iDelay=205, Bit 0, Center 36 (-115 ~ 188) 304
4402 22:16:47.722935 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4403 22:16:47.726090 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4404 22:16:47.729839 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4405 22:16:47.733211 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4406 22:16:47.739367 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4407 22:16:47.743201 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4408 22:16:47.746258 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4409 22:16:47.749711 iDelay=205, Bit 8, Center 28 (-123 ~ 180) 304
4410 22:16:47.756188 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4411 22:16:47.759348 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4412 22:16:47.762716 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4413 22:16:47.766182 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4414 22:16:47.772685 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4415 22:16:47.776327 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4416 22:16:47.779523 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4417 22:16:47.780120 ==
4418 22:16:47.782550 Dram Type= 6, Freq= 0, CH_0, rank 1
4419 22:16:47.785806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4420 22:16:47.786214 ==
4421 22:16:47.789275 DQS Delay:
4422 22:16:47.789750 DQS0 = 0, DQS1 = 0
4423 22:16:47.792360 DQM Delay:
4424 22:16:47.792816 DQM0 = 41, DQM1 = 36
4425 22:16:47.793143 DQ Delay:
4426 22:16:47.795730 DQ0 =36, DQ1 =44, DQ2 =36, DQ3 =40
4427 22:16:47.798766 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4428 22:16:47.802164 DQ8 =28, DQ9 =20, DQ10 =40, DQ11 =28
4429 22:16:47.806183 DQ12 =44, DQ13 =44, DQ14 =44, DQ15 =44
4430 22:16:47.806587
4431 22:16:47.809390
4432 22:16:47.815946 [DQSOSCAuto] RK1, (LSB)MR18= 0x6518, (MSB)MR19= 0x808, tDQSOscB0 = 405 ps tDQSOscB1 = 390 ps
4433 22:16:47.818915 CH0 RK1: MR19=808, MR18=6518
4434 22:16:47.825787 CH0_RK1: MR19=0x808, MR18=0x6518, DQSOSC=390, MR23=63, INC=172, DEC=114
4435 22:16:47.828553 [RxdqsGatingPostProcess] freq 600
4436 22:16:47.832055 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4437 22:16:47.835601 Pre-setting of DQS Precalculation
4438 22:16:47.842030 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4439 22:16:47.842528 ==
4440 22:16:47.845796 Dram Type= 6, Freq= 0, CH_1, rank 0
4441 22:16:47.848531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4442 22:16:47.848953 ==
4443 22:16:47.855329 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4444 22:16:47.858923 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4445 22:16:47.862753 [CA 0] Center 35 (5~66) winsize 62
4446 22:16:47.866035 [CA 1] Center 35 (5~66) winsize 62
4447 22:16:47.869466 [CA 2] Center 34 (4~65) winsize 62
4448 22:16:47.872483 [CA 3] Center 33 (3~64) winsize 62
4449 22:16:47.876181 [CA 4] Center 34 (4~65) winsize 62
4450 22:16:47.879329 [CA 5] Center 33 (3~64) winsize 62
4451 22:16:47.879740
4452 22:16:47.882159 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4453 22:16:47.882589
4454 22:16:47.886282 [CATrainingPosCal] consider 1 rank data
4455 22:16:47.890045 u2DelayCellTimex100 = 270/100 ps
4456 22:16:47.892754 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4457 22:16:47.898779 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4458 22:16:47.902222 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4459 22:16:47.905442 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4460 22:16:47.909252 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4461 22:16:47.911877 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4462 22:16:47.912466
4463 22:16:47.915468 CA PerBit enable=1, Macro0, CA PI delay=33
4464 22:16:47.915897
4465 22:16:47.918582 [CBTSetCACLKResult] CA Dly = 33
4466 22:16:47.921968 CS Dly: 5 (0~36)
4467 22:16:47.922395 ==
4468 22:16:47.925187 Dram Type= 6, Freq= 0, CH_1, rank 1
4469 22:16:47.928725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4470 22:16:47.929158 ==
4471 22:16:47.934942 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4472 22:16:47.938058 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4473 22:16:47.942758 [CA 0] Center 35 (5~66) winsize 62
4474 22:16:47.946159 [CA 1] Center 36 (6~66) winsize 61
4475 22:16:47.949196 [CA 2] Center 34 (4~65) winsize 62
4476 22:16:47.952412 [CA 3] Center 34 (3~65) winsize 63
4477 22:16:47.955760 [CA 4] Center 34 (4~65) winsize 62
4478 22:16:47.959654 [CA 5] Center 34 (3~65) winsize 63
4479 22:16:47.960072
4480 22:16:47.962755 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4481 22:16:47.963215
4482 22:16:47.965936 [CATrainingPosCal] consider 2 rank data
4483 22:16:47.969319 u2DelayCellTimex100 = 270/100 ps
4484 22:16:47.972424 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4485 22:16:47.978693 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4486 22:16:47.982411 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4487 22:16:47.985738 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4488 22:16:47.988818 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4489 22:16:47.992475 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4490 22:16:47.992894
4491 22:16:47.995756 CA PerBit enable=1, Macro0, CA PI delay=33
4492 22:16:47.996174
4493 22:16:47.998831 [CBTSetCACLKResult] CA Dly = 33
4494 22:16:48.002640 CS Dly: 5 (0~37)
4495 22:16:48.003087
4496 22:16:48.005543 ----->DramcWriteLeveling(PI) begin...
4497 22:16:48.005966 ==
4498 22:16:48.008942 Dram Type= 6, Freq= 0, CH_1, rank 0
4499 22:16:48.011972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4500 22:16:48.012392 ==
4501 22:16:48.015714 Write leveling (Byte 0): 29 => 29
4502 22:16:48.018480 Write leveling (Byte 1): 29 => 29
4503 22:16:48.021936 DramcWriteLeveling(PI) end<-----
4504 22:16:48.022354
4505 22:16:48.022682 ==
4506 22:16:48.025306 Dram Type= 6, Freq= 0, CH_1, rank 0
4507 22:16:48.029040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4508 22:16:48.029550 ==
4509 22:16:48.031621 [Gating] SW mode calibration
4510 22:16:48.038878 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4511 22:16:48.045273 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4512 22:16:48.048285 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4513 22:16:48.052003 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4514 22:16:48.058689 0 9 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
4515 22:16:48.061817 0 9 12 | B1->B0 | 3232 2f2f | 1 1 | (1 0) (0 0)
4516 22:16:48.065191 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4517 22:16:48.072029 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4518 22:16:48.074870 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4519 22:16:48.078428 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4520 22:16:48.084901 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4521 22:16:48.088308 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4522 22:16:48.091504 0 10 8 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
4523 22:16:48.098083 0 10 12 | B1->B0 | 2e2e 4141 | 0 0 | (0 0) (1 1)
4524 22:16:48.101222 0 10 16 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
4525 22:16:48.104486 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4526 22:16:48.110869 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4527 22:16:48.114184 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4528 22:16:48.117330 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4529 22:16:48.124097 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4530 22:16:48.127493 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4531 22:16:48.130713 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4532 22:16:48.137596 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4533 22:16:48.140520 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4534 22:16:48.144268 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4535 22:16:48.150520 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4536 22:16:48.153812 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4537 22:16:48.157059 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4538 22:16:48.163918 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4539 22:16:48.167575 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4540 22:16:48.170236 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4541 22:16:48.176693 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4542 22:16:48.180156 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4543 22:16:48.183408 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4544 22:16:48.190355 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4545 22:16:48.193592 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4546 22:16:48.196983 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4547 22:16:48.204095 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4548 22:16:48.206732 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4549 22:16:48.210076 Total UI for P1: 0, mck2ui 16
4550 22:16:48.213260 best dqsien dly found for B0: ( 0, 13, 12)
4551 22:16:48.216480 Total UI for P1: 0, mck2ui 16
4552 22:16:48.220058 best dqsien dly found for B1: ( 0, 13, 12)
4553 22:16:48.223306 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4554 22:16:48.226283 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4555 22:16:48.226701
4556 22:16:48.229934 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4557 22:16:48.233651 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4558 22:16:48.236767 [Gating] SW calibration Done
4559 22:16:48.237186 ==
4560 22:16:48.239916 Dram Type= 6, Freq= 0, CH_1, rank 0
4561 22:16:48.246663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4562 22:16:48.247224 ==
4563 22:16:48.247640 RX Vref Scan: 0
4564 22:16:48.247960
4565 22:16:48.249888 RX Vref 0 -> 0, step: 1
4566 22:16:48.250269
4567 22:16:48.252846 RX Delay -230 -> 252, step: 16
4568 22:16:48.256356 iDelay=218, Bit 0, Center 65 (-86 ~ 217) 304
4569 22:16:48.259441 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4570 22:16:48.262901 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4571 22:16:48.269597 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4572 22:16:48.272685 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4573 22:16:48.276100 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4574 22:16:48.279174 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4575 22:16:48.282697 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4576 22:16:48.289117 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4577 22:16:48.292701 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4578 22:16:48.296036 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4579 22:16:48.299385 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4580 22:16:48.305897 iDelay=218, Bit 12, Center 41 (-134 ~ 217) 352
4581 22:16:48.309348 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4582 22:16:48.313035 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4583 22:16:48.316325 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4584 22:16:48.316809 ==
4585 22:16:48.319616 Dram Type= 6, Freq= 0, CH_1, rank 0
4586 22:16:48.325868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4587 22:16:48.326286 ==
4588 22:16:48.326610 DQS Delay:
4589 22:16:48.329192 DQS0 = 0, DQS1 = 0
4590 22:16:48.329604 DQM Delay:
4591 22:16:48.332449 DQM0 = 49, DQM1 = 36
4592 22:16:48.332910 DQ Delay:
4593 22:16:48.335837 DQ0 =65, DQ1 =41, DQ2 =33, DQ3 =41
4594 22:16:48.339469 DQ4 =41, DQ5 =65, DQ6 =65, DQ7 =41
4595 22:16:48.342431 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =25
4596 22:16:48.345539 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =49
4597 22:16:48.346026
4598 22:16:48.346409
4599 22:16:48.346725 ==
4600 22:16:48.349133 Dram Type= 6, Freq= 0, CH_1, rank 0
4601 22:16:48.352365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4602 22:16:48.352853 ==
4603 22:16:48.353243
4604 22:16:48.353549
4605 22:16:48.355579 TX Vref Scan disable
4606 22:16:48.358664 == TX Byte 0 ==
4607 22:16:48.361919 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4608 22:16:48.365986 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4609 22:16:48.368984 == TX Byte 1 ==
4610 22:16:48.372349 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4611 22:16:48.376142 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4612 22:16:48.376565 ==
4613 22:16:48.378715 Dram Type= 6, Freq= 0, CH_1, rank 0
4614 22:16:48.382102 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4615 22:16:48.385462 ==
4616 22:16:48.385895
4617 22:16:48.386215
4618 22:16:48.386511 TX Vref Scan disable
4619 22:16:48.389352 == TX Byte 0 ==
4620 22:16:48.392885 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4621 22:16:48.399653 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4622 22:16:48.400064 == TX Byte 1 ==
4623 22:16:48.402621 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4624 22:16:48.409623 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4625 22:16:48.410031
4626 22:16:48.410351 [DATLAT]
4627 22:16:48.410648 Freq=600, CH1 RK0
4628 22:16:48.410938
4629 22:16:48.412518 DATLAT Default: 0x9
4630 22:16:48.412922 0, 0xFFFF, sum = 0
4631 22:16:48.416344 1, 0xFFFF, sum = 0
4632 22:16:48.419467 2, 0xFFFF, sum = 0
4633 22:16:48.419908 3, 0xFFFF, sum = 0
4634 22:16:48.422472 4, 0xFFFF, sum = 0
4635 22:16:48.422902 5, 0xFFFF, sum = 0
4636 22:16:48.425540 6, 0xFFFF, sum = 0
4637 22:16:48.425964 7, 0xFFFF, sum = 0
4638 22:16:48.429159 8, 0x0, sum = 1
4639 22:16:48.429579 9, 0x0, sum = 2
4640 22:16:48.429929 10, 0x0, sum = 3
4641 22:16:48.432904 11, 0x0, sum = 4
4642 22:16:48.433336 best_step = 9
4643 22:16:48.433655
4644 22:16:48.433949 ==
4645 22:16:48.435542 Dram Type= 6, Freq= 0, CH_1, rank 0
4646 22:16:48.442260 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4647 22:16:48.442670 ==
4648 22:16:48.442992 RX Vref Scan: 1
4649 22:16:48.443336
4650 22:16:48.445519 RX Vref 0 -> 0, step: 1
4651 22:16:48.445926
4652 22:16:48.449102 RX Delay -179 -> 252, step: 8
4653 22:16:48.449509
4654 22:16:48.452156 Set Vref, RX VrefLevel [Byte0]: 47
4655 22:16:48.455154 [Byte1]: 53
4656 22:16:48.455561
4657 22:16:48.458751 Final RX Vref Byte 0 = 47 to rank0
4658 22:16:48.462304 Final RX Vref Byte 1 = 53 to rank0
4659 22:16:48.465314 Final RX Vref Byte 0 = 47 to rank1
4660 22:16:48.469103 Final RX Vref Byte 1 = 53 to rank1==
4661 22:16:48.472076 Dram Type= 6, Freq= 0, CH_1, rank 0
4662 22:16:48.475052 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4663 22:16:48.475491 ==
4664 22:16:48.478661 DQS Delay:
4665 22:16:48.479094 DQS0 = 0, DQS1 = 0
4666 22:16:48.481913 DQM Delay:
4667 22:16:48.482401 DQM0 = 46, DQM1 = 37
4668 22:16:48.482729 DQ Delay:
4669 22:16:48.485271 DQ0 =48, DQ1 =40, DQ2 =40, DQ3 =44
4670 22:16:48.488488 DQ4 =44, DQ5 =56, DQ6 =60, DQ7 =40
4671 22:16:48.491687 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =28
4672 22:16:48.495359 DQ12 =48, DQ13 =40, DQ14 =48, DQ15 =48
4673 22:16:48.495784
4674 22:16:48.498396
4675 22:16:48.505089 [DQSOSCAuto] RK0, (LSB)MR18= 0x5237, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 394 ps
4676 22:16:48.508072 CH1 RK0: MR19=808, MR18=5237
4677 22:16:48.514860 CH1_RK0: MR19=0x808, MR18=0x5237, DQSOSC=394, MR23=63, INC=168, DEC=112
4678 22:16:48.515352
4679 22:16:48.518204 ----->DramcWriteLeveling(PI) begin...
4680 22:16:48.518703 ==
4681 22:16:48.521209 Dram Type= 6, Freq= 0, CH_1, rank 1
4682 22:16:48.524742 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4683 22:16:48.525155 ==
4684 22:16:48.528349 Write leveling (Byte 0): 28 => 28
4685 22:16:48.531250 Write leveling (Byte 1): 30 => 30
4686 22:16:48.534729 DramcWriteLeveling(PI) end<-----
4687 22:16:48.535166
4688 22:16:48.535510 ==
4689 22:16:48.537714 Dram Type= 6, Freq= 0, CH_1, rank 1
4690 22:16:48.541250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4691 22:16:48.541665 ==
4692 22:16:48.544583 [Gating] SW mode calibration
4693 22:16:48.551385 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4694 22:16:48.557454 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4695 22:16:48.560833 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4696 22:16:48.567791 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4697 22:16:48.571270 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4698 22:16:48.574152 0 9 12 | B1->B0 | 2f2f 3434 | 0 1 | (1 1) (1 0)
4699 22:16:48.580516 0 9 16 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
4700 22:16:48.584304 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4701 22:16:48.587248 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4702 22:16:48.594098 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4703 22:16:48.597250 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4704 22:16:48.600843 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4705 22:16:48.603964 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4706 22:16:48.610615 0 10 12 | B1->B0 | 3232 2f2f | 0 0 | (0 0) (0 0)
4707 22:16:48.613906 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4708 22:16:48.617398 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4709 22:16:48.623985 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4710 22:16:48.627442 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4711 22:16:48.630328 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4712 22:16:48.637091 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4713 22:16:48.640397 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4714 22:16:48.643474 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4715 22:16:48.649927 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4716 22:16:48.653309 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4717 22:16:48.657230 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4718 22:16:48.663555 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4719 22:16:48.666609 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4720 22:16:48.669806 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4721 22:16:48.676712 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4722 22:16:48.679938 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4723 22:16:48.683464 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4724 22:16:48.689960 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4725 22:16:48.693126 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4726 22:16:48.696755 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4727 22:16:48.703313 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4728 22:16:48.706172 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4729 22:16:48.709924 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4730 22:16:48.716266 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4731 22:16:48.719858 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4732 22:16:48.723175 Total UI for P1: 0, mck2ui 16
4733 22:16:48.725936 best dqsien dly found for B1: ( 0, 13, 12)
4734 22:16:48.729741 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4735 22:16:48.732847 Total UI for P1: 0, mck2ui 16
4736 22:16:48.735927 best dqsien dly found for B0: ( 0, 13, 14)
4737 22:16:48.739599 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4738 22:16:48.745831 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4739 22:16:48.746247
4740 22:16:48.749544 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4741 22:16:48.752316 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4742 22:16:48.755538 [Gating] SW calibration Done
4743 22:16:48.755947 ==
4744 22:16:48.759118 Dram Type= 6, Freq= 0, CH_1, rank 1
4745 22:16:48.762689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4746 22:16:48.763131 ==
4747 22:16:48.765423 RX Vref Scan: 0
4748 22:16:48.765833
4749 22:16:48.766155 RX Vref 0 -> 0, step: 1
4750 22:16:48.766456
4751 22:16:48.769063 RX Delay -230 -> 252, step: 16
4752 22:16:48.772352 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4753 22:16:48.778691 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4754 22:16:48.782370 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4755 22:16:48.785450 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4756 22:16:48.788357 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4757 22:16:48.796009 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4758 22:16:48.798951 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4759 22:16:48.801710 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4760 22:16:48.805401 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4761 22:16:48.808403 iDelay=218, Bit 9, Center 33 (-134 ~ 201) 336
4762 22:16:48.815389 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4763 22:16:48.818508 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4764 22:16:48.821619 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4765 22:16:48.828466 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4766 22:16:48.832327 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4767 22:16:48.835086 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4768 22:16:48.835504 ==
4769 22:16:48.838315 Dram Type= 6, Freq= 0, CH_1, rank 1
4770 22:16:48.841616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4771 22:16:48.842042 ==
4772 22:16:48.844852 DQS Delay:
4773 22:16:48.845229 DQS0 = 0, DQS1 = 0
4774 22:16:48.848119 DQM Delay:
4775 22:16:48.848471 DQM0 = 43, DQM1 = 39
4776 22:16:48.848766 DQ Delay:
4777 22:16:48.851746 DQ0 =41, DQ1 =41, DQ2 =25, DQ3 =41
4778 22:16:48.854551 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4779 22:16:48.858377 DQ8 =17, DQ9 =33, DQ10 =33, DQ11 =33
4780 22:16:48.861398 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4781 22:16:48.861817
4782 22:16:48.862134
4783 22:16:48.864480 ==
4784 22:16:48.868102 Dram Type= 6, Freq= 0, CH_1, rank 1
4785 22:16:48.871626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4786 22:16:48.872075 ==
4787 22:16:48.872396
4788 22:16:48.872688
4789 22:16:48.874648 TX Vref Scan disable
4790 22:16:48.875053 == TX Byte 0 ==
4791 22:16:48.881161 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4792 22:16:48.884665 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4793 22:16:48.885086 == TX Byte 1 ==
4794 22:16:48.890785 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4795 22:16:48.894066 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4796 22:16:48.894502 ==
4797 22:16:48.897706 Dram Type= 6, Freq= 0, CH_1, rank 1
4798 22:16:48.900766 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4799 22:16:48.901179 ==
4800 22:16:48.901503
4801 22:16:48.901807
4802 22:16:48.904257 TX Vref Scan disable
4803 22:16:48.907218 == TX Byte 0 ==
4804 22:16:48.910851 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4805 22:16:48.913956 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4806 22:16:48.917236 == TX Byte 1 ==
4807 22:16:48.920772 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4808 22:16:48.924573 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4809 22:16:48.925002
4810 22:16:48.927419 [DATLAT]
4811 22:16:48.927842 Freq=600, CH1 RK1
4812 22:16:48.928264
4813 22:16:48.930432 DATLAT Default: 0x9
4814 22:16:48.930855 0, 0xFFFF, sum = 0
4815 22:16:48.933991 1, 0xFFFF, sum = 0
4816 22:16:48.934441 2, 0xFFFF, sum = 0
4817 22:16:48.937296 3, 0xFFFF, sum = 0
4818 22:16:48.937726 4, 0xFFFF, sum = 0
4819 22:16:48.940911 5, 0xFFFF, sum = 0
4820 22:16:48.944011 6, 0xFFFF, sum = 0
4821 22:16:48.944444 7, 0xFFFF, sum = 0
4822 22:16:48.944873 8, 0x0, sum = 1
4823 22:16:48.947016 9, 0x0, sum = 2
4824 22:16:48.947484 10, 0x0, sum = 3
4825 22:16:48.950084 11, 0x0, sum = 4
4826 22:16:48.950514 best_step = 9
4827 22:16:48.950935
4828 22:16:48.951357 ==
4829 22:16:48.953885 Dram Type= 6, Freq= 0, CH_1, rank 1
4830 22:16:48.959920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4831 22:16:48.960347 ==
4832 22:16:48.960772 RX Vref Scan: 0
4833 22:16:48.961167
4834 22:16:48.963826 RX Vref 0 -> 0, step: 1
4835 22:16:48.964250
4836 22:16:48.966499 RX Delay -195 -> 252, step: 8
4837 22:16:48.970377 iDelay=205, Bit 0, Center 48 (-99 ~ 196) 296
4838 22:16:48.976965 iDelay=205, Bit 1, Center 40 (-107 ~ 188) 296
4839 22:16:48.980177 iDelay=205, Bit 2, Center 32 (-115 ~ 180) 296
4840 22:16:48.983154 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4841 22:16:48.986689 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4842 22:16:48.993467 iDelay=205, Bit 5, Center 56 (-91 ~ 204) 296
4843 22:16:48.996930 iDelay=205, Bit 6, Center 56 (-91 ~ 204) 296
4844 22:16:49.000243 iDelay=205, Bit 7, Center 44 (-107 ~ 196) 304
4845 22:16:49.002975 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4846 22:16:49.006351 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4847 22:16:49.013142 iDelay=205, Bit 10, Center 36 (-115 ~ 188) 304
4848 22:16:49.016176 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4849 22:16:49.019835 iDelay=205, Bit 12, Center 48 (-107 ~ 204) 312
4850 22:16:49.022790 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4851 22:16:49.029921 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4852 22:16:49.032732 iDelay=205, Bit 15, Center 48 (-107 ~ 204) 312
4853 22:16:49.033148 ==
4854 22:16:49.036050 Dram Type= 6, Freq= 0, CH_1, rank 1
4855 22:16:49.039176 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4856 22:16:49.039612 ==
4857 22:16:49.042835 DQS Delay:
4858 22:16:49.043305 DQS0 = 0, DQS1 = 0
4859 22:16:49.045840 DQM Delay:
4860 22:16:49.046260 DQM0 = 45, DQM1 = 37
4861 22:16:49.046684 DQ Delay:
4862 22:16:49.049480 DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =44
4863 22:16:49.052522 DQ4 =44, DQ5 =56, DQ6 =56, DQ7 =44
4864 22:16:49.055971 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =28
4865 22:16:49.059145 DQ12 =48, DQ13 =44, DQ14 =44, DQ15 =48
4866 22:16:49.059568
4867 22:16:49.059988
4868 22:16:49.069309 [DQSOSCAuto] RK1, (LSB)MR18= 0x2e23, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 401 ps
4869 22:16:49.072429 CH1 RK1: MR19=808, MR18=2E23
4870 22:16:49.079218 CH1_RK1: MR19=0x808, MR18=0x2E23, DQSOSC=401, MR23=63, INC=163, DEC=108
4871 22:16:49.079655 [RxdqsGatingPostProcess] freq 600
4872 22:16:49.085864 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4873 22:16:49.089468 Pre-setting of DQS Precalculation
4874 22:16:49.092346 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4875 22:16:49.102085 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4876 22:16:49.109228 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4877 22:16:49.109646
4878 22:16:49.110027
4879 22:16:49.111943 [Calibration Summary] 1200 Mbps
4880 22:16:49.112359 CH 0, Rank 0
4881 22:16:49.115292 SW Impedance : PASS
4882 22:16:49.115707 DUTY Scan : NO K
4883 22:16:49.118562 ZQ Calibration : PASS
4884 22:16:49.122178 Jitter Meter : NO K
4885 22:16:49.122599 CBT Training : PASS
4886 22:16:49.125163 Write leveling : PASS
4887 22:16:49.128656 RX DQS gating : PASS
4888 22:16:49.129128 RX DQ/DQS(RDDQC) : PASS
4889 22:16:49.132238 TX DQ/DQS : PASS
4890 22:16:49.135303 RX DATLAT : PASS
4891 22:16:49.135757 RX DQ/DQS(Engine): PASS
4892 22:16:49.138351 TX OE : NO K
4893 22:16:49.138826 All Pass.
4894 22:16:49.139238
4895 22:16:49.142167 CH 0, Rank 1
4896 22:16:49.142582 SW Impedance : PASS
4897 22:16:49.144832 DUTY Scan : NO K
4898 22:16:49.148227 ZQ Calibration : PASS
4899 22:16:49.148688 Jitter Meter : NO K
4900 22:16:49.151695 CBT Training : PASS
4901 22:16:49.155017 Write leveling : PASS
4902 22:16:49.155509 RX DQS gating : PASS
4903 22:16:49.158688 RX DQ/DQS(RDDQC) : PASS
4904 22:16:49.162151 TX DQ/DQS : PASS
4905 22:16:49.162582 RX DATLAT : PASS
4906 22:16:49.164624 RX DQ/DQS(Engine): PASS
4907 22:16:49.168120 TX OE : NO K
4908 22:16:49.168552 All Pass.
4909 22:16:49.168902
4910 22:16:49.169204 CH 1, Rank 0
4911 22:16:49.171559 SW Impedance : PASS
4912 22:16:49.174710 DUTY Scan : NO K
4913 22:16:49.175184 ZQ Calibration : PASS
4914 22:16:49.178047 Jitter Meter : NO K
4915 22:16:49.180926 CBT Training : PASS
4916 22:16:49.181344 Write leveling : PASS
4917 22:16:49.184635 RX DQS gating : PASS
4918 22:16:49.185078 RX DQ/DQS(RDDQC) : PASS
4919 22:16:49.187870 TX DQ/DQS : PASS
4920 22:16:49.191445 RX DATLAT : PASS
4921 22:16:49.191886 RX DQ/DQS(Engine): PASS
4922 22:16:49.194643 TX OE : NO K
4923 22:16:49.195277 All Pass.
4924 22:16:49.195716
4925 22:16:49.197599 CH 1, Rank 1
4926 22:16:49.198023 SW Impedance : PASS
4927 22:16:49.201190 DUTY Scan : NO K
4928 22:16:49.204528 ZQ Calibration : PASS
4929 22:16:49.204938 Jitter Meter : NO K
4930 22:16:49.208115 CBT Training : PASS
4931 22:16:49.211183 Write leveling : PASS
4932 22:16:49.211595 RX DQS gating : PASS
4933 22:16:49.214161 RX DQ/DQS(RDDQC) : PASS
4934 22:16:49.217536 TX DQ/DQS : PASS
4935 22:16:49.217944 RX DATLAT : PASS
4936 22:16:49.221387 RX DQ/DQS(Engine): PASS
4937 22:16:49.224312 TX OE : NO K
4938 22:16:49.224706 All Pass.
4939 22:16:49.225028
4940 22:16:49.225338 DramC Write-DBI off
4941 22:16:49.227587 PER_BANK_REFRESH: Hybrid Mode
4942 22:16:49.230675 TX_TRACKING: ON
4943 22:16:49.237381 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4944 22:16:49.243902 [FAST_K] Save calibration result to emmc
4945 22:16:49.246903 dramc_set_vcore_voltage set vcore to 662500
4946 22:16:49.247404 Read voltage for 933, 3
4947 22:16:49.250654 Vio18 = 0
4948 22:16:49.251096 Vcore = 662500
4949 22:16:49.251428 Vdram = 0
4950 22:16:49.253627 Vddq = 0
4951 22:16:49.254039 Vmddr = 0
4952 22:16:49.257141 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4953 22:16:49.263481 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4954 22:16:49.266946 MEM_TYPE=3, freq_sel=17
4955 22:16:49.270208 sv_algorithm_assistance_LP4_1600
4956 22:16:49.273583 ============ PULL DRAM RESETB DOWN ============
4957 22:16:49.276555 ========== PULL DRAM RESETB DOWN end =========
4958 22:16:49.283172 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4959 22:16:49.287152 ===================================
4960 22:16:49.287568 LPDDR4 DRAM CONFIGURATION
4961 22:16:49.290329 ===================================
4962 22:16:49.293171 EX_ROW_EN[0] = 0x0
4963 22:16:49.293625 EX_ROW_EN[1] = 0x0
4964 22:16:49.296874 LP4Y_EN = 0x0
4965 22:16:49.299950 WORK_FSP = 0x0
4966 22:16:49.300389 WL = 0x3
4967 22:16:49.303238 RL = 0x3
4968 22:16:49.303669 BL = 0x2
4969 22:16:49.306359 RPST = 0x0
4970 22:16:49.306900 RD_PRE = 0x0
4971 22:16:49.310051 WR_PRE = 0x1
4972 22:16:49.310462 WR_PST = 0x0
4973 22:16:49.313188 DBI_WR = 0x0
4974 22:16:49.313633 DBI_RD = 0x0
4975 22:16:49.316712 OTF = 0x1
4976 22:16:49.320013 ===================================
4977 22:16:49.322839 ===================================
4978 22:16:49.323342 ANA top config
4979 22:16:49.326148 ===================================
4980 22:16:49.329734 DLL_ASYNC_EN = 0
4981 22:16:49.332886 ALL_SLAVE_EN = 1
4982 22:16:49.333398 NEW_RANK_MODE = 1
4983 22:16:49.335965 DLL_IDLE_MODE = 1
4984 22:16:49.339376 LP45_APHY_COMB_EN = 1
4985 22:16:49.342492 TX_ODT_DIS = 1
4986 22:16:49.345902 NEW_8X_MODE = 1
4987 22:16:49.349262 ===================================
4988 22:16:49.352210 ===================================
4989 22:16:49.356242 data_rate = 1866
4990 22:16:49.356651 CKR = 1
4991 22:16:49.359036 DQ_P2S_RATIO = 8
4992 22:16:49.362663 ===================================
4993 22:16:49.365802 CA_P2S_RATIO = 8
4994 22:16:49.368715 DQ_CA_OPEN = 0
4995 22:16:49.372557 DQ_SEMI_OPEN = 0
4996 22:16:49.375440 CA_SEMI_OPEN = 0
4997 22:16:49.375991 CA_FULL_RATE = 0
4998 22:16:49.378820 DQ_CKDIV4_EN = 1
4999 22:16:49.382228 CA_CKDIV4_EN = 1
5000 22:16:49.385571 CA_PREDIV_EN = 0
5001 22:16:49.388466 PH8_DLY = 0
5002 22:16:49.392036 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
5003 22:16:49.392506 DQ_AAMCK_DIV = 4
5004 22:16:49.395354 CA_AAMCK_DIV = 4
5005 22:16:49.398091 CA_ADMCK_DIV = 4
5006 22:16:49.401810 DQ_TRACK_CA_EN = 0
5007 22:16:49.405161 CA_PICK = 933
5008 22:16:49.408062 CA_MCKIO = 933
5009 22:16:49.411781 MCKIO_SEMI = 0
5010 22:16:49.414698 PLL_FREQ = 3732
5011 22:16:49.415155 DQ_UI_PI_RATIO = 32
5012 22:16:49.418482 CA_UI_PI_RATIO = 0
5013 22:16:49.421587 ===================================
5014 22:16:49.425022 ===================================
5015 22:16:49.427997 memory_type:LPDDR4
5016 22:16:49.431433 GP_NUM : 10
5017 22:16:49.431856 SRAM_EN : 1
5018 22:16:49.434538 MD32_EN : 0
5019 22:16:49.438035 ===================================
5020 22:16:49.441120 [ANA_INIT] >>>>>>>>>>>>>>
5021 22:16:49.441618 <<<<<< [CONFIGURE PHASE]: ANA_TX
5022 22:16:49.444782 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5023 22:16:49.448029 ===================================
5024 22:16:49.451576 data_rate = 1866,PCW = 0X8f00
5025 22:16:49.454314 ===================================
5026 22:16:49.457923 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5027 22:16:49.464678 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5028 22:16:49.470825 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5029 22:16:49.474365 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5030 22:16:49.477705 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5031 22:16:49.481098 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5032 22:16:49.483848 [ANA_INIT] flow start
5033 22:16:49.484265 [ANA_INIT] PLL >>>>>>>>
5034 22:16:49.487266 [ANA_INIT] PLL <<<<<<<<
5035 22:16:49.490958 [ANA_INIT] MIDPI >>>>>>>>
5036 22:16:49.493968 [ANA_INIT] MIDPI <<<<<<<<
5037 22:16:49.494384 [ANA_INIT] DLL >>>>>>>>
5038 22:16:49.497079 [ANA_INIT] flow end
5039 22:16:49.500485 ============ LP4 DIFF to SE enter ============
5040 22:16:49.503662 ============ LP4 DIFF to SE exit ============
5041 22:16:49.507521 [ANA_INIT] <<<<<<<<<<<<<
5042 22:16:49.510486 [Flow] Enable top DCM control >>>>>
5043 22:16:49.513555 [Flow] Enable top DCM control <<<<<
5044 22:16:49.516992 Enable DLL master slave shuffle
5045 22:16:49.523803 ==============================================================
5046 22:16:49.524227 Gating Mode config
5047 22:16:49.530577 ==============================================================
5048 22:16:49.531105 Config description:
5049 22:16:49.539943 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5050 22:16:49.546544 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5051 22:16:49.553145 SELPH_MODE 0: By rank 1: By Phase
5052 22:16:49.559947 ==============================================================
5053 22:16:49.560379 GAT_TRACK_EN = 1
5054 22:16:49.563171 RX_GATING_MODE = 2
5055 22:16:49.566805 RX_GATING_TRACK_MODE = 2
5056 22:16:49.569728 SELPH_MODE = 1
5057 22:16:49.573195 PICG_EARLY_EN = 1
5058 22:16:49.576483 VALID_LAT_VALUE = 1
5059 22:16:49.582777 ==============================================================
5060 22:16:49.586280 Enter into Gating configuration >>>>
5061 22:16:49.589365 Exit from Gating configuration <<<<
5062 22:16:49.592968 Enter into DVFS_PRE_config >>>>>
5063 22:16:49.602783 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5064 22:16:49.606515 Exit from DVFS_PRE_config <<<<<
5065 22:16:49.609330 Enter into PICG configuration >>>>
5066 22:16:49.612798 Exit from PICG configuration <<<<
5067 22:16:49.615823 [RX_INPUT] configuration >>>>>
5068 22:16:49.619339 [RX_INPUT] configuration <<<<<
5069 22:16:49.622914 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5070 22:16:49.629221 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5071 22:16:49.636966 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5072 22:16:49.639038 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5073 22:16:49.645706 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5074 22:16:49.652408 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5075 22:16:49.655225 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5076 22:16:49.662289 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5077 22:16:49.665234 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5078 22:16:49.668455 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5079 22:16:49.672447 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5080 22:16:49.678434 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5081 22:16:49.682018 ===================================
5082 22:16:49.684919 LPDDR4 DRAM CONFIGURATION
5083 22:16:49.688224 ===================================
5084 22:16:49.688637 EX_ROW_EN[0] = 0x0
5085 22:16:49.691894 EX_ROW_EN[1] = 0x0
5086 22:16:49.692307 LP4Y_EN = 0x0
5087 22:16:49.694610 WORK_FSP = 0x0
5088 22:16:49.695020 WL = 0x3
5089 22:16:49.697728 RL = 0x3
5090 22:16:49.698138 BL = 0x2
5091 22:16:49.701189 RPST = 0x0
5092 22:16:49.701598 RD_PRE = 0x0
5093 22:16:49.704282 WR_PRE = 0x1
5094 22:16:49.704693 WR_PST = 0x0
5095 22:16:49.707660 DBI_WR = 0x0
5096 22:16:49.711302 DBI_RD = 0x0
5097 22:16:49.711766 OTF = 0x1
5098 22:16:49.714187 ===================================
5099 22:16:49.717448 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5100 22:16:49.721551 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5101 22:16:49.727446 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5102 22:16:49.730884 ===================================
5103 22:16:49.734176 LPDDR4 DRAM CONFIGURATION
5104 22:16:49.737770 ===================================
5105 22:16:49.738187 EX_ROW_EN[0] = 0x10
5106 22:16:49.740882 EX_ROW_EN[1] = 0x0
5107 22:16:49.741296 LP4Y_EN = 0x0
5108 22:16:49.744227 WORK_FSP = 0x0
5109 22:16:49.744640 WL = 0x3
5110 22:16:49.747298 RL = 0x3
5111 22:16:49.747716 BL = 0x2
5112 22:16:49.750863 RPST = 0x0
5113 22:16:49.753976 RD_PRE = 0x0
5114 22:16:49.754388 WR_PRE = 0x1
5115 22:16:49.757293 WR_PST = 0x0
5116 22:16:49.757707 DBI_WR = 0x0
5117 22:16:49.760363 DBI_RD = 0x0
5118 22:16:49.760796 OTF = 0x1
5119 22:16:49.763504 ===================================
5120 22:16:49.770213 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5121 22:16:49.774351 nWR fixed to 30
5122 22:16:49.777685 [ModeRegInit_LP4] CH0 RK0
5123 22:16:49.778096 [ModeRegInit_LP4] CH0 RK1
5124 22:16:49.780897 [ModeRegInit_LP4] CH1 RK0
5125 22:16:49.784045 [ModeRegInit_LP4] CH1 RK1
5126 22:16:49.784522 match AC timing 9
5127 22:16:49.790547 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5128 22:16:49.793926 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5129 22:16:49.797041 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5130 22:16:49.804105 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5131 22:16:49.807284 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5132 22:16:49.807759 ==
5133 22:16:49.810427 Dram Type= 6, Freq= 0, CH_0, rank 0
5134 22:16:49.813756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5135 22:16:49.814233 ==
5136 22:16:49.820002 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5137 22:16:49.827048 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5138 22:16:49.830238 [CA 0] Center 37 (7~68) winsize 62
5139 22:16:49.833272 [CA 1] Center 37 (7~68) winsize 62
5140 22:16:49.836739 [CA 2] Center 34 (4~65) winsize 62
5141 22:16:49.839875 [CA 3] Center 34 (4~65) winsize 62
5142 22:16:49.843279 [CA 4] Center 33 (3~64) winsize 62
5143 22:16:49.846928 [CA 5] Center 33 (3~64) winsize 62
5144 22:16:49.847384
5145 22:16:49.849899 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5146 22:16:49.850316
5147 22:16:49.853480 [CATrainingPosCal] consider 1 rank data
5148 22:16:49.856620 u2DelayCellTimex100 = 270/100 ps
5149 22:16:49.859457 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5150 22:16:49.862641 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5151 22:16:49.865896 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5152 22:16:49.872567 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5153 22:16:49.876117 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5154 22:16:49.879733 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5155 22:16:49.879814
5156 22:16:49.882756 CA PerBit enable=1, Macro0, CA PI delay=33
5157 22:16:49.882837
5158 22:16:49.885985 [CBTSetCACLKResult] CA Dly = 33
5159 22:16:49.886065 CS Dly: 7 (0~38)
5160 22:16:49.886129 ==
5161 22:16:49.889345 Dram Type= 6, Freq= 0, CH_0, rank 1
5162 22:16:49.895918 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5163 22:16:49.895999 ==
5164 22:16:49.899067 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5165 22:16:49.905392 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5166 22:16:49.908933 [CA 0] Center 37 (7~68) winsize 62
5167 22:16:49.912464 [CA 1] Center 37 (7~68) winsize 62
5168 22:16:49.915552 [CA 2] Center 34 (4~65) winsize 62
5169 22:16:49.918973 [CA 3] Center 34 (4~65) winsize 62
5170 22:16:49.922559 [CA 4] Center 33 (3~64) winsize 62
5171 22:16:49.925357 [CA 5] Center 33 (3~63) winsize 61
5172 22:16:49.925476
5173 22:16:49.929442 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5174 22:16:49.929561
5175 22:16:49.932222 [CATrainingPosCal] consider 2 rank data
5176 22:16:49.935629 u2DelayCellTimex100 = 270/100 ps
5177 22:16:49.938628 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5178 22:16:49.945494 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5179 22:16:49.948509 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5180 22:16:49.951932 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5181 22:16:49.955820 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5182 22:16:49.958841 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5183 22:16:49.959165
5184 22:16:49.961984 CA PerBit enable=1, Macro0, CA PI delay=33
5185 22:16:49.962363
5186 22:16:49.965136 [CBTSetCACLKResult] CA Dly = 33
5187 22:16:49.968640 CS Dly: 7 (0~39)
5188 22:16:49.969053
5189 22:16:49.972249 ----->DramcWriteLeveling(PI) begin...
5190 22:16:49.972669 ==
5191 22:16:49.975426 Dram Type= 6, Freq= 0, CH_0, rank 0
5192 22:16:49.978465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5193 22:16:49.978879 ==
5194 22:16:49.981858 Write leveling (Byte 0): 32 => 32
5195 22:16:49.985229 Write leveling (Byte 1): 32 => 32
5196 22:16:49.988523 DramcWriteLeveling(PI) end<-----
5197 22:16:49.988937
5198 22:16:49.989261 ==
5199 22:16:49.991544 Dram Type= 6, Freq= 0, CH_0, rank 0
5200 22:16:49.994807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5201 22:16:49.995337 ==
5202 22:16:49.998257 [Gating] SW mode calibration
5203 22:16:50.005055 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5204 22:16:50.011536 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5205 22:16:50.014727 0 14 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
5206 22:16:50.018050 0 14 4 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
5207 22:16:50.024733 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5208 22:16:50.027676 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5209 22:16:50.031406 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5210 22:16:50.037674 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5211 22:16:50.040790 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5212 22:16:50.044551 0 14 28 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 1)
5213 22:16:50.050881 0 15 0 | B1->B0 | 3030 2323 | 1 0 | (1 0) (0 0)
5214 22:16:50.054280 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5215 22:16:50.057511 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5216 22:16:50.063951 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5217 22:16:50.067428 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5218 22:16:50.071321 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5219 22:16:50.077570 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5220 22:16:50.080756 0 15 28 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
5221 22:16:50.083745 1 0 0 | B1->B0 | 2d2d 4545 | 0 0 | (0 0) (0 0)
5222 22:16:50.090565 1 0 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5223 22:16:50.093581 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5224 22:16:50.097285 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5225 22:16:50.103843 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5226 22:16:50.107334 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5227 22:16:50.110287 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5228 22:16:50.117040 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5229 22:16:50.120213 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5230 22:16:50.123594 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5231 22:16:50.130730 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5232 22:16:50.133574 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5233 22:16:50.136697 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5234 22:16:50.143395 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5235 22:16:50.146696 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5236 22:16:50.149886 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5237 22:16:50.156201 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5238 22:16:50.159870 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5239 22:16:50.162858 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5240 22:16:50.170005 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5241 22:16:50.173276 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5242 22:16:50.176332 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5243 22:16:50.182716 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5244 22:16:50.186238 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5245 22:16:50.189956 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5246 22:16:50.192797 Total UI for P1: 0, mck2ui 16
5247 22:16:50.196264 best dqsien dly found for B0: ( 1, 2, 28)
5248 22:16:50.202835 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5249 22:16:50.206201 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5250 22:16:50.209302 Total UI for P1: 0, mck2ui 16
5251 22:16:50.212761 best dqsien dly found for B1: ( 1, 3, 2)
5252 22:16:50.215930 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5253 22:16:50.219115 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5254 22:16:50.219529
5255 22:16:50.222486 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5256 22:16:50.226075 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5257 22:16:50.229464 [Gating] SW calibration Done
5258 22:16:50.229875 ==
5259 22:16:50.232237 Dram Type= 6, Freq= 0, CH_0, rank 0
5260 22:16:50.239165 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5261 22:16:50.239619 ==
5262 22:16:50.240055 RX Vref Scan: 0
5263 22:16:50.240387
5264 22:16:50.242205 RX Vref 0 -> 0, step: 1
5265 22:16:50.242617
5266 22:16:50.245440 RX Delay -80 -> 252, step: 8
5267 22:16:50.248988 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5268 22:16:50.252015 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5269 22:16:50.255398 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5270 22:16:50.258510 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5271 22:16:50.262167 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5272 22:16:50.268518 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
5273 22:16:50.271901 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5274 22:16:50.275391 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5275 22:16:50.278687 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5276 22:16:50.281989 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5277 22:16:50.288592 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5278 22:16:50.291856 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5279 22:16:50.295206 iDelay=208, Bit 12, Center 87 (-8 ~ 183) 192
5280 22:16:50.298535 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5281 22:16:50.301339 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5282 22:16:50.308591 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5283 22:16:50.308983 ==
5284 22:16:50.311296 Dram Type= 6, Freq= 0, CH_0, rank 0
5285 22:16:50.314855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5286 22:16:50.315340 ==
5287 22:16:50.315647 DQS Delay:
5288 22:16:50.318522 DQS0 = 0, DQS1 = 0
5289 22:16:50.318956 DQM Delay:
5290 22:16:50.321501 DQM0 = 97, DQM1 = 85
5291 22:16:50.321933 DQ Delay:
5292 22:16:50.324659 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =91
5293 22:16:50.328794 DQ4 =99, DQ5 =83, DQ6 =107, DQ7 =107
5294 22:16:50.331519 DQ8 =79, DQ9 =79, DQ10 =83, DQ11 =79
5295 22:16:50.334733 DQ12 =87, DQ13 =91, DQ14 =95, DQ15 =91
5296 22:16:50.335233
5297 22:16:50.335589
5298 22:16:50.335889 ==
5299 22:16:50.338275 Dram Type= 6, Freq= 0, CH_0, rank 0
5300 22:16:50.344899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5301 22:16:50.345441 ==
5302 22:16:50.345762
5303 22:16:50.346080
5304 22:16:50.346363 TX Vref Scan disable
5305 22:16:50.347672 == TX Byte 0 ==
5306 22:16:50.350905 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5307 22:16:50.357550 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5308 22:16:50.357961 == TX Byte 1 ==
5309 22:16:50.360978 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5310 22:16:50.367667 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5311 22:16:50.368084 ==
5312 22:16:50.370566 Dram Type= 6, Freq= 0, CH_0, rank 0
5313 22:16:50.373936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5314 22:16:50.374346 ==
5315 22:16:50.374688
5316 22:16:50.375110
5317 22:16:50.377661 TX Vref Scan disable
5318 22:16:50.378086 == TX Byte 0 ==
5319 22:16:50.383853 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5320 22:16:50.387256 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5321 22:16:50.387666 == TX Byte 1 ==
5322 22:16:50.393850 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5323 22:16:50.397443 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5324 22:16:50.397912
5325 22:16:50.398282 [DATLAT]
5326 22:16:50.400406 Freq=933, CH0 RK0
5327 22:16:50.400837
5328 22:16:50.401206 DATLAT Default: 0xd
5329 22:16:50.404061 0, 0xFFFF, sum = 0
5330 22:16:50.404475 1, 0xFFFF, sum = 0
5331 22:16:50.407230 2, 0xFFFF, sum = 0
5332 22:16:50.410506 3, 0xFFFF, sum = 0
5333 22:16:50.410921 4, 0xFFFF, sum = 0
5334 22:16:50.413809 5, 0xFFFF, sum = 0
5335 22:16:50.414228 6, 0xFFFF, sum = 0
5336 22:16:50.417535 7, 0xFFFF, sum = 0
5337 22:16:50.417968 8, 0xFFFF, sum = 0
5338 22:16:50.420534 9, 0xFFFF, sum = 0
5339 22:16:50.420960 10, 0x0, sum = 1
5340 22:16:50.423757 11, 0x0, sum = 2
5341 22:16:50.424189 12, 0x0, sum = 3
5342 22:16:50.427373 13, 0x0, sum = 4
5343 22:16:50.427825 best_step = 11
5344 22:16:50.428145
5345 22:16:50.428448 ==
5346 22:16:50.430391 Dram Type= 6, Freq= 0, CH_0, rank 0
5347 22:16:50.433583 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5348 22:16:50.434029 ==
5349 22:16:50.437127 RX Vref Scan: 1
5350 22:16:50.437567
5351 22:16:50.440084 RX Vref 0 -> 0, step: 1
5352 22:16:50.440534
5353 22:16:50.440866 RX Delay -61 -> 252, step: 4
5354 22:16:50.441194
5355 22:16:50.443446 Set Vref, RX VrefLevel [Byte0]: 58
5356 22:16:50.447235 [Byte1]: 51
5357 22:16:50.451624
5358 22:16:50.452036 Final RX Vref Byte 0 = 58 to rank0
5359 22:16:50.455357 Final RX Vref Byte 1 = 51 to rank0
5360 22:16:50.458326 Final RX Vref Byte 0 = 58 to rank1
5361 22:16:50.461449 Final RX Vref Byte 1 = 51 to rank1==
5362 22:16:50.464795 Dram Type= 6, Freq= 0, CH_0, rank 0
5363 22:16:50.471127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5364 22:16:50.471568 ==
5365 22:16:50.471928 DQS Delay:
5366 22:16:50.474415 DQS0 = 0, DQS1 = 0
5367 22:16:50.474868 DQM Delay:
5368 22:16:50.475238 DQM0 = 97, DQM1 = 86
5369 22:16:50.478061 DQ Delay:
5370 22:16:50.481576 DQ0 =96, DQ1 =98, DQ2 =94, DQ3 =94
5371 22:16:50.484582 DQ4 =98, DQ5 =88, DQ6 =106, DQ7 =108
5372 22:16:50.487929 DQ8 =78, DQ9 =74, DQ10 =86, DQ11 =80
5373 22:16:50.491721 DQ12 =90, DQ13 =88, DQ14 =100, DQ15 =92
5374 22:16:50.492129
5375 22:16:50.492483
5376 22:16:50.497714 [DQSOSCAuto] RK0, (LSB)MR18= 0x2910, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 408 ps
5377 22:16:50.501359 CH0 RK0: MR19=505, MR18=2910
5378 22:16:50.507588 CH0_RK0: MR19=0x505, MR18=0x2910, DQSOSC=408, MR23=63, INC=65, DEC=43
5379 22:16:50.508014
5380 22:16:50.511011 ----->DramcWriteLeveling(PI) begin...
5381 22:16:50.511480 ==
5382 22:16:50.514265 Dram Type= 6, Freq= 0, CH_0, rank 1
5383 22:16:50.517614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5384 22:16:50.518022 ==
5385 22:16:50.520648 Write leveling (Byte 0): 30 => 30
5386 22:16:50.524197 Write leveling (Byte 1): 31 => 31
5387 22:16:50.527355 DramcWriteLeveling(PI) end<-----
5388 22:16:50.527587
5389 22:16:50.527760 ==
5390 22:16:50.530256 Dram Type= 6, Freq= 0, CH_0, rank 1
5391 22:16:50.537147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5392 22:16:50.537553 ==
5393 22:16:50.537869 [Gating] SW mode calibration
5394 22:16:50.547763 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5395 22:16:50.550580 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5396 22:16:50.554013 0 14 0 | B1->B0 | 2d2d 3333 | 1 1 | (0 0) (1 1)
5397 22:16:50.560490 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5398 22:16:50.563823 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5399 22:16:50.567154 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5400 22:16:50.573798 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5401 22:16:50.577037 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5402 22:16:50.580687 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5403 22:16:50.587087 0 14 28 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 1)
5404 22:16:50.590222 0 15 0 | B1->B0 | 2f2f 2828 | 0 0 | (0 0) (0 0)
5405 22:16:50.593731 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5406 22:16:50.600214 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5407 22:16:50.603681 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5408 22:16:50.607154 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5409 22:16:50.613749 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5410 22:16:50.616679 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5411 22:16:50.619976 0 15 28 | B1->B0 | 2524 3535 | 1 0 | (0 0) (1 1)
5412 22:16:50.626683 1 0 0 | B1->B0 | 3c3c 4343 | 1 0 | (0 0) (0 0)
5413 22:16:50.629827 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5414 22:16:50.633270 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5415 22:16:50.639616 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5416 22:16:50.643151 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5417 22:16:50.646338 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5418 22:16:50.653361 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5419 22:16:50.655989 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5420 22:16:50.659307 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5421 22:16:50.665966 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5422 22:16:50.669332 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5423 22:16:50.672720 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5424 22:16:50.679481 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5425 22:16:50.682470 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5426 22:16:50.685712 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5427 22:16:50.692383 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5428 22:16:50.695847 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5429 22:16:50.698989 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5430 22:16:50.705816 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5431 22:16:50.709223 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5432 22:16:50.712371 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5433 22:16:50.719560 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5434 22:16:50.722617 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5435 22:16:50.725217 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5436 22:16:50.731818 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5437 22:16:50.735287 Total UI for P1: 0, mck2ui 16
5438 22:16:50.738562 best dqsien dly found for B0: ( 1, 2, 28)
5439 22:16:50.742379 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5440 22:16:50.745059 Total UI for P1: 0, mck2ui 16
5441 22:16:50.748544 best dqsien dly found for B1: ( 1, 3, 2)
5442 22:16:50.751808 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5443 22:16:50.755346 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5444 22:16:50.755762
5445 22:16:50.758429 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5446 22:16:50.761337 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5447 22:16:50.764674 [Gating] SW calibration Done
5448 22:16:50.765089 ==
5449 22:16:50.768292 Dram Type= 6, Freq= 0, CH_0, rank 1
5450 22:16:50.774727 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5451 22:16:50.775216 ==
5452 22:16:50.775557 RX Vref Scan: 0
5453 22:16:50.775864
5454 22:16:50.778196 RX Vref 0 -> 0, step: 1
5455 22:16:50.778610
5456 22:16:50.781489 RX Delay -80 -> 252, step: 8
5457 22:16:50.784731 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5458 22:16:50.787685 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5459 22:16:50.791155 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5460 22:16:50.794528 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5461 22:16:50.801098 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5462 22:16:50.804224 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5463 22:16:50.807773 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5464 22:16:50.811210 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5465 22:16:50.814217 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5466 22:16:50.820885 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5467 22:16:50.824380 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5468 22:16:50.827578 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5469 22:16:50.830941 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5470 22:16:50.834053 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5471 22:16:50.840816 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5472 22:16:50.844014 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5473 22:16:50.844428 ==
5474 22:16:50.847248 Dram Type= 6, Freq= 0, CH_0, rank 1
5475 22:16:50.850586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5476 22:16:50.851000 ==
5477 22:16:50.853686 DQS Delay:
5478 22:16:50.854121 DQS0 = 0, DQS1 = 0
5479 22:16:50.854449 DQM Delay:
5480 22:16:50.857094 DQM0 = 96, DQM1 = 87
5481 22:16:50.857507 DQ Delay:
5482 22:16:50.860095 DQ0 =95, DQ1 =99, DQ2 =87, DQ3 =91
5483 22:16:50.864543 DQ4 =95, DQ5 =87, DQ6 =107, DQ7 =107
5484 22:16:50.866930 DQ8 =79, DQ9 =75, DQ10 =91, DQ11 =83
5485 22:16:50.869996 DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =91
5486 22:16:50.870408
5487 22:16:50.870728
5488 22:16:50.871026 ==
5489 22:16:50.873605 Dram Type= 6, Freq= 0, CH_0, rank 1
5490 22:16:50.880075 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5491 22:16:50.880485 ==
5492 22:16:50.880809
5493 22:16:50.881101
5494 22:16:50.881383 TX Vref Scan disable
5495 22:16:50.883572 == TX Byte 0 ==
5496 22:16:50.887272 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5497 22:16:50.893481 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5498 22:16:50.893890 == TX Byte 1 ==
5499 22:16:50.896776 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5500 22:16:50.903409 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5501 22:16:50.903822 ==
5502 22:16:50.906776 Dram Type= 6, Freq= 0, CH_0, rank 1
5503 22:16:50.910383 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5504 22:16:50.910792 ==
5505 22:16:50.911181
5506 22:16:50.911488
5507 22:16:50.913054 TX Vref Scan disable
5508 22:16:50.913466 == TX Byte 0 ==
5509 22:16:50.919755 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5510 22:16:50.923305 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5511 22:16:50.923725 == TX Byte 1 ==
5512 22:16:50.929659 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5513 22:16:50.932893 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5514 22:16:50.933308
5515 22:16:50.933628 [DATLAT]
5516 22:16:50.936473 Freq=933, CH0 RK1
5517 22:16:50.936889
5518 22:16:50.937208 DATLAT Default: 0xb
5519 22:16:50.939511 0, 0xFFFF, sum = 0
5520 22:16:50.939926 1, 0xFFFF, sum = 0
5521 22:16:50.943408 2, 0xFFFF, sum = 0
5522 22:16:50.946438 3, 0xFFFF, sum = 0
5523 22:16:50.946851 4, 0xFFFF, sum = 0
5524 22:16:50.949489 5, 0xFFFF, sum = 0
5525 22:16:50.949907 6, 0xFFFF, sum = 0
5526 22:16:50.952870 7, 0xFFFF, sum = 0
5527 22:16:50.953290 8, 0xFFFF, sum = 0
5528 22:16:50.956176 9, 0xFFFF, sum = 0
5529 22:16:50.956595 10, 0x0, sum = 1
5530 22:16:50.959524 11, 0x0, sum = 2
5531 22:16:50.959942 12, 0x0, sum = 3
5532 22:16:50.962773 13, 0x0, sum = 4
5533 22:16:50.963218 best_step = 11
5534 22:16:50.963540
5535 22:16:50.963839 ==
5536 22:16:50.966081 Dram Type= 6, Freq= 0, CH_0, rank 1
5537 22:16:50.969494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5538 22:16:50.969908 ==
5539 22:16:50.972824 RX Vref Scan: 0
5540 22:16:50.973284
5541 22:16:50.975826 RX Vref 0 -> 0, step: 1
5542 22:16:50.976249
5543 22:16:50.976593 RX Delay -69 -> 252, step: 4
5544 22:16:50.984123 iDelay=203, Bit 0, Center 94 (3 ~ 186) 184
5545 22:16:50.987447 iDelay=203, Bit 1, Center 96 (-1 ~ 194) 196
5546 22:16:50.990763 iDelay=203, Bit 2, Center 90 (-1 ~ 182) 184
5547 22:16:50.993734 iDelay=203, Bit 3, Center 94 (-1 ~ 190) 192
5548 22:16:50.997840 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5549 22:16:51.000467 iDelay=203, Bit 5, Center 86 (-9 ~ 182) 192
5550 22:16:51.007330 iDelay=203, Bit 6, Center 106 (11 ~ 202) 192
5551 22:16:51.011259 iDelay=203, Bit 7, Center 104 (11 ~ 198) 188
5552 22:16:51.013774 iDelay=203, Bit 8, Center 78 (-13 ~ 170) 184
5553 22:16:51.017110 iDelay=203, Bit 9, Center 76 (-17 ~ 170) 188
5554 22:16:51.020453 iDelay=203, Bit 10, Center 88 (-5 ~ 182) 188
5555 22:16:51.027088 iDelay=203, Bit 11, Center 82 (-9 ~ 174) 184
5556 22:16:51.030418 iDelay=203, Bit 12, Center 92 (-1 ~ 186) 188
5557 22:16:51.034189 iDelay=203, Bit 13, Center 92 (-1 ~ 186) 188
5558 22:16:51.036953 iDelay=203, Bit 14, Center 100 (11 ~ 190) 180
5559 22:16:51.043110 iDelay=203, Bit 15, Center 92 (-1 ~ 186) 188
5560 22:16:51.043566 ==
5561 22:16:51.046558 Dram Type= 6, Freq= 0, CH_0, rank 1
5562 22:16:51.050234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5563 22:16:51.050780 ==
5564 22:16:51.051178 DQS Delay:
5565 22:16:51.053253 DQS0 = 0, DQS1 = 0
5566 22:16:51.053703 DQM Delay:
5567 22:16:51.056446 DQM0 = 95, DQM1 = 87
5568 22:16:51.056897 DQ Delay:
5569 22:16:51.060005 DQ0 =94, DQ1 =96, DQ2 =90, DQ3 =94
5570 22:16:51.063125 DQ4 =96, DQ5 =86, DQ6 =106, DQ7 =104
5571 22:16:51.066756 DQ8 =78, DQ9 =76, DQ10 =88, DQ11 =82
5572 22:16:51.069879 DQ12 =92, DQ13 =92, DQ14 =100, DQ15 =92
5573 22:16:51.070287
5574 22:16:51.070604
5575 22:16:51.079661 [DQSOSCAuto] RK1, (LSB)MR18= 0x27f6, (MSB)MR19= 0x504, tDQSOscB0 = 425 ps tDQSOscB1 = 409 ps
5576 22:16:51.080080 CH0 RK1: MR19=504, MR18=27F6
5577 22:16:51.086295 CH0_RK1: MR19=0x504, MR18=0x27F6, DQSOSC=409, MR23=63, INC=64, DEC=43
5578 22:16:51.089205 [RxdqsGatingPostProcess] freq 933
5579 22:16:51.096105 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5580 22:16:51.099370 best DQS0 dly(2T, 0.5T) = (0, 10)
5581 22:16:51.102712 best DQS1 dly(2T, 0.5T) = (0, 11)
5582 22:16:51.106134 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5583 22:16:51.109396 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5584 22:16:51.112443 best DQS0 dly(2T, 0.5T) = (0, 10)
5585 22:16:51.112853 best DQS1 dly(2T, 0.5T) = (0, 11)
5586 22:16:51.116300 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5587 22:16:51.119148 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5588 22:16:51.122391 Pre-setting of DQS Precalculation
5589 22:16:51.128866 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5590 22:16:51.129376 ==
5591 22:16:51.132507 Dram Type= 6, Freq= 0, CH_1, rank 0
5592 22:16:51.135736 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5593 22:16:51.136259 ==
5594 22:16:51.142114 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5595 22:16:51.149037 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5596 22:16:51.152089 [CA 0] Center 37 (6~68) winsize 63
5597 22:16:51.155317 [CA 1] Center 37 (6~68) winsize 63
5598 22:16:51.158976 [CA 2] Center 34 (4~65) winsize 62
5599 22:16:51.162154 [CA 3] Center 34 (4~64) winsize 61
5600 22:16:51.165086 [CA 4] Center 34 (4~65) winsize 62
5601 22:16:51.168521 [CA 5] Center 33 (3~64) winsize 62
5602 22:16:51.168956
5603 22:16:51.172095 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5604 22:16:51.172513
5605 22:16:51.175429 [CATrainingPosCal] consider 1 rank data
5606 22:16:51.178465 u2DelayCellTimex100 = 270/100 ps
5607 22:16:51.181778 CA0 delay=37 (6~68),Diff = 4 PI (24 cell)
5608 22:16:51.185514 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5609 22:16:51.188403 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5610 22:16:51.191815 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5611 22:16:51.194797 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5612 22:16:51.198661 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5613 22:16:51.199234
5614 22:16:51.204881 CA PerBit enable=1, Macro0, CA PI delay=33
5615 22:16:51.205294
5616 22:16:51.208666 [CBTSetCACLKResult] CA Dly = 33
5617 22:16:51.209078 CS Dly: 6 (0~37)
5618 22:16:51.209423 ==
5619 22:16:51.211892 Dram Type= 6, Freq= 0, CH_1, rank 1
5620 22:16:51.215034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5621 22:16:51.215509 ==
5622 22:16:51.221673 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5623 22:16:51.227948 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5624 22:16:51.231156 [CA 0] Center 37 (7~67) winsize 61
5625 22:16:51.234932 [CA 1] Center 37 (7~68) winsize 62
5626 22:16:51.237753 [CA 2] Center 34 (4~65) winsize 62
5627 22:16:51.241327 [CA 3] Center 34 (4~65) winsize 62
5628 22:16:51.244410 [CA 4] Center 34 (4~65) winsize 62
5629 22:16:51.248116 [CA 5] Center 33 (3~64) winsize 62
5630 22:16:51.248529
5631 22:16:51.251226 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5632 22:16:51.251636
5633 22:16:51.254678 [CATrainingPosCal] consider 2 rank data
5634 22:16:51.258317 u2DelayCellTimex100 = 270/100 ps
5635 22:16:51.261075 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5636 22:16:51.264118 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5637 22:16:51.267944 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5638 22:16:51.270954 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5639 22:16:51.277418 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5640 22:16:51.280629 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5641 22:16:51.281040
5642 22:16:51.284333 CA PerBit enable=1, Macro0, CA PI delay=33
5643 22:16:51.284743
5644 22:16:51.287165 [CBTSetCACLKResult] CA Dly = 33
5645 22:16:51.287575 CS Dly: 7 (0~39)
5646 22:16:51.287896
5647 22:16:51.290769 ----->DramcWriteLeveling(PI) begin...
5648 22:16:51.291297 ==
5649 22:16:51.294288 Dram Type= 6, Freq= 0, CH_1, rank 0
5650 22:16:51.301426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5651 22:16:51.301836 ==
5652 22:16:51.304211 Write leveling (Byte 0): 25 => 25
5653 22:16:51.307730 Write leveling (Byte 1): 29 => 29
5654 22:16:51.308137 DramcWriteLeveling(PI) end<-----
5655 22:16:51.310553
5656 22:16:51.311117 ==
5657 22:16:51.313958 Dram Type= 6, Freq= 0, CH_1, rank 0
5658 22:16:51.316993 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5659 22:16:51.317404 ==
5660 22:16:51.320320 [Gating] SW mode calibration
5661 22:16:51.326953 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5662 22:16:51.330618 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5663 22:16:51.336801 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5664 22:16:51.340117 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5665 22:16:51.343333 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5666 22:16:51.349932 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5667 22:16:51.353351 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5668 22:16:51.356661 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5669 22:16:51.363296 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
5670 22:16:51.366774 0 14 28 | B1->B0 | 2d2d 2323 | 0 0 | (1 0) (0 0)
5671 22:16:51.370141 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5672 22:16:51.376787 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5673 22:16:51.380021 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5674 22:16:51.382989 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5675 22:16:51.390254 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5676 22:16:51.393246 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5677 22:16:51.396544 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5678 22:16:51.403555 0 15 28 | B1->B0 | 3737 3b3b | 0 1 | (1 1) (0 0)
5679 22:16:51.406918 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5680 22:16:51.409778 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5681 22:16:51.416585 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5682 22:16:51.419762 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5683 22:16:51.423006 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5684 22:16:51.429397 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5685 22:16:51.432870 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5686 22:16:51.436021 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5687 22:16:51.443018 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5688 22:16:51.446377 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5689 22:16:51.449206 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5690 22:16:51.455903 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5691 22:16:51.459576 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5692 22:16:51.462553 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5693 22:16:51.469251 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5694 22:16:51.472291 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5695 22:16:51.475456 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5696 22:16:51.482074 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5697 22:16:51.485653 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5698 22:16:51.488584 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5699 22:16:51.495231 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5700 22:16:51.498844 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5701 22:16:51.501979 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5702 22:16:51.508368 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5703 22:16:51.508787 Total UI for P1: 0, mck2ui 16
5704 22:16:51.515201 best dqsien dly found for B0: ( 1, 2, 24)
5705 22:16:51.515620 Total UI for P1: 0, mck2ui 16
5706 22:16:51.522121 best dqsien dly found for B1: ( 1, 2, 24)
5707 22:16:51.525394 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5708 22:16:51.528439 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5709 22:16:51.528856
5710 22:16:51.532443 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5711 22:16:51.535465 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5712 22:16:51.538465 [Gating] SW calibration Done
5713 22:16:51.538880 ==
5714 22:16:51.541899 Dram Type= 6, Freq= 0, CH_1, rank 0
5715 22:16:51.545223 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5716 22:16:51.545645 ==
5717 22:16:51.548477 RX Vref Scan: 0
5718 22:16:51.548910
5719 22:16:51.549378 RX Vref 0 -> 0, step: 1
5720 22:16:51.549763
5721 22:16:51.552125 RX Delay -80 -> 252, step: 8
5722 22:16:51.558749 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5723 22:16:51.562014 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5724 22:16:51.564960 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5725 22:16:51.568331 iDelay=208, Bit 3, Center 99 (0 ~ 199) 200
5726 22:16:51.571424 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5727 22:16:51.574390 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5728 22:16:51.580977 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5729 22:16:51.584540 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5730 22:16:51.587932 iDelay=208, Bit 8, Center 83 (-16 ~ 183) 200
5731 22:16:51.591164 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5732 22:16:51.594387 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5733 22:16:51.600785 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5734 22:16:51.604182 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5735 22:16:51.607794 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5736 22:16:51.610784 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5737 22:16:51.613949 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5738 22:16:51.614382 ==
5739 22:16:51.617833 Dram Type= 6, Freq= 0, CH_1, rank 0
5740 22:16:51.623917 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5741 22:16:51.624338 ==
5742 22:16:51.624667 DQS Delay:
5743 22:16:51.627384 DQS0 = 0, DQS1 = 0
5744 22:16:51.627798 DQM Delay:
5745 22:16:51.628125 DQM0 = 101, DQM1 = 91
5746 22:16:51.630758 DQ Delay:
5747 22:16:51.634051 DQ0 =107, DQ1 =95, DQ2 =95, DQ3 =99
5748 22:16:51.637421 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =95
5749 22:16:51.640713 DQ8 =83, DQ9 =83, DQ10 =91, DQ11 =79
5750 22:16:51.643844 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =99
5751 22:16:51.644261
5752 22:16:51.644585
5753 22:16:51.644884 ==
5754 22:16:51.646970 Dram Type= 6, Freq= 0, CH_1, rank 0
5755 22:16:51.650638 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5756 22:16:51.651130 ==
5757 22:16:51.651518
5758 22:16:51.651851
5759 22:16:51.653931 TX Vref Scan disable
5760 22:16:51.657304 == TX Byte 0 ==
5761 22:16:51.660780 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5762 22:16:51.663604 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5763 22:16:51.666709 == TX Byte 1 ==
5764 22:16:51.670427 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5765 22:16:51.673588 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5766 22:16:51.674017 ==
5767 22:16:51.676570 Dram Type= 6, Freq= 0, CH_1, rank 0
5768 22:16:51.683673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5769 22:16:51.684088 ==
5770 22:16:51.684427
5771 22:16:51.684730
5772 22:16:51.685015 TX Vref Scan disable
5773 22:16:51.687801 == TX Byte 0 ==
5774 22:16:51.690391 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5775 22:16:51.697156 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5776 22:16:51.697571 == TX Byte 1 ==
5777 22:16:51.700463 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5778 22:16:51.707002 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5779 22:16:51.707457
5780 22:16:51.707780 [DATLAT]
5781 22:16:51.708084 Freq=933, CH1 RK0
5782 22:16:51.708373
5783 22:16:51.710283 DATLAT Default: 0xd
5784 22:16:51.710694 0, 0xFFFF, sum = 0
5785 22:16:51.713450 1, 0xFFFF, sum = 0
5786 22:16:51.717095 2, 0xFFFF, sum = 0
5787 22:16:51.717513 3, 0xFFFF, sum = 0
5788 22:16:51.720332 4, 0xFFFF, sum = 0
5789 22:16:51.720750 5, 0xFFFF, sum = 0
5790 22:16:51.723538 6, 0xFFFF, sum = 0
5791 22:16:51.723957 7, 0xFFFF, sum = 0
5792 22:16:51.726760 8, 0xFFFF, sum = 0
5793 22:16:51.727205 9, 0xFFFF, sum = 0
5794 22:16:51.729884 10, 0x0, sum = 1
5795 22:16:51.730301 11, 0x0, sum = 2
5796 22:16:51.733617 12, 0x0, sum = 3
5797 22:16:51.734034 13, 0x0, sum = 4
5798 22:16:51.736613 best_step = 11
5799 22:16:51.737022
5800 22:16:51.737343 ==
5801 22:16:51.740045 Dram Type= 6, Freq= 0, CH_1, rank 0
5802 22:16:51.743245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5803 22:16:51.743659 ==
5804 22:16:51.743976 RX Vref Scan: 1
5805 22:16:51.746662
5806 22:16:51.747101 RX Vref 0 -> 0, step: 1
5807 22:16:51.747435
5808 22:16:51.750217 RX Delay -61 -> 252, step: 4
5809 22:16:51.750627
5810 22:16:51.752934 Set Vref, RX VrefLevel [Byte0]: 47
5811 22:16:51.756075 [Byte1]: 53
5812 22:16:51.759852
5813 22:16:51.760292 Final RX Vref Byte 0 = 47 to rank0
5814 22:16:51.763298 Final RX Vref Byte 1 = 53 to rank0
5815 22:16:51.766450 Final RX Vref Byte 0 = 47 to rank1
5816 22:16:51.769754 Final RX Vref Byte 1 = 53 to rank1==
5817 22:16:51.773320 Dram Type= 6, Freq= 0, CH_1, rank 0
5818 22:16:51.779679 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5819 22:16:51.780190 ==
5820 22:16:51.780669 DQS Delay:
5821 22:16:51.782824 DQS0 = 0, DQS1 = 0
5822 22:16:51.783453 DQM Delay:
5823 22:16:51.783922 DQM0 = 101, DQM1 = 95
5824 22:16:51.786399 DQ Delay:
5825 22:16:51.789234 DQ0 =106, DQ1 =96, DQ2 =92, DQ3 =98
5826 22:16:51.792785 DQ4 =100, DQ5 =112, DQ6 =112, DQ7 =98
5827 22:16:51.795968 DQ8 =82, DQ9 =86, DQ10 =94, DQ11 =84
5828 22:16:51.799542 DQ12 =102, DQ13 =100, DQ14 =106, DQ15 =106
5829 22:16:51.799953
5830 22:16:51.800273
5831 22:16:51.806257 [DQSOSCAuto] RK0, (LSB)MR18= 0x1b0b, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 413 ps
5832 22:16:51.809219 CH1 RK0: MR19=505, MR18=1B0B
5833 22:16:51.815772 CH1_RK0: MR19=0x505, MR18=0x1B0B, DQSOSC=413, MR23=63, INC=63, DEC=42
5834 22:16:51.816194
5835 22:16:51.818948 ----->DramcWriteLeveling(PI) begin...
5836 22:16:51.819404 ==
5837 22:16:51.822232 Dram Type= 6, Freq= 0, CH_1, rank 1
5838 22:16:51.825826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5839 22:16:51.828664 ==
5840 22:16:51.832305 Write leveling (Byte 0): 26 => 26
5841 22:16:51.832720 Write leveling (Byte 1): 27 => 27
5842 22:16:51.835373 DramcWriteLeveling(PI) end<-----
5843 22:16:51.835790
5844 22:16:51.836114 ==
5845 22:16:51.838883 Dram Type= 6, Freq= 0, CH_1, rank 1
5846 22:16:51.845764 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5847 22:16:51.846241 ==
5848 22:16:51.849010 [Gating] SW mode calibration
5849 22:16:51.855630 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5850 22:16:51.858511 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5851 22:16:51.865007 0 14 0 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
5852 22:16:51.868381 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5853 22:16:51.872051 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5854 22:16:51.878680 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5855 22:16:51.881879 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5856 22:16:51.885119 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5857 22:16:51.891843 0 14 24 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
5858 22:16:51.895005 0 14 28 | B1->B0 | 2a2a 2f2f | 0 0 | (0 0) (0 0)
5859 22:16:51.897959 0 15 0 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (1 1)
5860 22:16:51.905067 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5861 22:16:51.908642 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5862 22:16:51.911545 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5863 22:16:51.918163 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5864 22:16:51.921145 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5865 22:16:51.924921 0 15 24 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
5866 22:16:51.931607 0 15 28 | B1->B0 | 4242 3737 | 0 0 | (0 0) (0 0)
5867 22:16:51.934443 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5868 22:16:51.938241 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5869 22:16:51.944782 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5870 22:16:51.948035 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5871 22:16:51.951103 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5872 22:16:51.957536 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5873 22:16:51.960944 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5874 22:16:51.964440 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5875 22:16:51.970647 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5876 22:16:51.974188 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5877 22:16:51.977460 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5878 22:16:51.983946 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5879 22:16:51.987146 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5880 22:16:51.990597 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5881 22:16:51.997109 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5882 22:16:52.000581 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5883 22:16:52.003588 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5884 22:16:52.010629 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5885 22:16:52.013739 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5886 22:16:52.017199 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5887 22:16:52.023566 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5888 22:16:52.027097 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5889 22:16:52.030217 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5890 22:16:52.036907 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5891 22:16:52.037325 Total UI for P1: 0, mck2ui 16
5892 22:16:52.043504 best dqsien dly found for B0: ( 1, 2, 24)
5893 22:16:52.043966 Total UI for P1: 0, mck2ui 16
5894 22:16:52.046858 best dqsien dly found for B1: ( 1, 2, 24)
5895 22:16:52.053400 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5896 22:16:52.056805 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5897 22:16:52.057217
5898 22:16:52.060015 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5899 22:16:52.063036 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5900 22:16:52.066694 [Gating] SW calibration Done
5901 22:16:52.067147 ==
5902 22:16:52.069654 Dram Type= 6, Freq= 0, CH_1, rank 1
5903 22:16:52.072928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5904 22:16:52.073345 ==
5905 22:16:52.076526 RX Vref Scan: 0
5906 22:16:52.076937
5907 22:16:52.077254 RX Vref 0 -> 0, step: 1
5908 22:16:52.077551
5909 22:16:52.079814 RX Delay -80 -> 252, step: 8
5910 22:16:52.083177 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5911 22:16:52.089794 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5912 22:16:52.092640 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5913 22:16:52.096479 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5914 22:16:52.099667 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5915 22:16:52.103116 iDelay=208, Bit 5, Center 107 (16 ~ 199) 184
5916 22:16:52.106003 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5917 22:16:52.112565 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5918 22:16:52.116289 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5919 22:16:52.119379 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5920 22:16:52.122789 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5921 22:16:52.126003 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5922 22:16:52.132736 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5923 22:16:52.135273 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5924 22:16:52.138888 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5925 22:16:52.142154 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5926 22:16:52.142594 ==
5927 22:16:52.145385 Dram Type= 6, Freq= 0, CH_1, rank 1
5928 22:16:52.149199 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5929 22:16:52.152104 ==
5930 22:16:52.152572 DQS Delay:
5931 22:16:52.152904 DQS0 = 0, DQS1 = 0
5932 22:16:52.155349 DQM Delay:
5933 22:16:52.155796 DQM0 = 99, DQM1 = 91
5934 22:16:52.158603 DQ Delay:
5935 22:16:52.162202 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =95
5936 22:16:52.165146 DQ4 =95, DQ5 =107, DQ6 =111, DQ7 =95
5937 22:16:52.168559 DQ8 =79, DQ9 =79, DQ10 =95, DQ11 =87
5938 22:16:52.171556 DQ12 =99, DQ13 =99, DQ14 =95, DQ15 =99
5939 22:16:52.171997
5940 22:16:52.172327
5941 22:16:52.172634 ==
5942 22:16:52.175183 Dram Type= 6, Freq= 0, CH_1, rank 1
5943 22:16:52.178360 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5944 22:16:52.178808 ==
5945 22:16:52.179176
5946 22:16:52.179617
5947 22:16:52.181564 TX Vref Scan disable
5948 22:16:52.182079 == TX Byte 0 ==
5949 22:16:52.188298 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5950 22:16:52.191490 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5951 22:16:52.191989 == TX Byte 1 ==
5952 22:16:52.198027 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5953 22:16:52.201215 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5954 22:16:52.201639 ==
5955 22:16:52.204464 Dram Type= 6, Freq= 0, CH_1, rank 1
5956 22:16:52.208007 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5957 22:16:52.208486 ==
5958 22:16:52.211108
5959 22:16:52.211589
5960 22:16:52.211934 TX Vref Scan disable
5961 22:16:52.214687 == TX Byte 0 ==
5962 22:16:52.217989 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5963 22:16:52.224807 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5964 22:16:52.225307 == TX Byte 1 ==
5965 22:16:52.227629 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5966 22:16:52.234428 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5967 22:16:52.234875
5968 22:16:52.235316 [DATLAT]
5969 22:16:52.235687 Freq=933, CH1 RK1
5970 22:16:52.236019
5971 22:16:52.237881 DATLAT Default: 0xb
5972 22:16:52.240905 0, 0xFFFF, sum = 0
5973 22:16:52.241329 1, 0xFFFF, sum = 0
5974 22:16:52.244522 2, 0xFFFF, sum = 0
5975 22:16:52.244941 3, 0xFFFF, sum = 0
5976 22:16:52.247341 4, 0xFFFF, sum = 0
5977 22:16:52.247798 5, 0xFFFF, sum = 0
5978 22:16:52.250466 6, 0xFFFF, sum = 0
5979 22:16:52.250909 7, 0xFFFF, sum = 0
5980 22:16:52.254378 8, 0xFFFF, sum = 0
5981 22:16:52.254846 9, 0xFFFF, sum = 0
5982 22:16:52.257308 10, 0x0, sum = 1
5983 22:16:52.257749 11, 0x0, sum = 2
5984 22:16:52.260472 12, 0x0, sum = 3
5985 22:16:52.260981 13, 0x0, sum = 4
5986 22:16:52.263912 best_step = 11
5987 22:16:52.264346
5988 22:16:52.264668 ==
5989 22:16:52.267161 Dram Type= 6, Freq= 0, CH_1, rank 1
5990 22:16:52.270231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5991 22:16:52.270652 ==
5992 22:16:52.274053 RX Vref Scan: 0
5993 22:16:52.274561
5994 22:16:52.274902 RX Vref 0 -> 0, step: 1
5995 22:16:52.275342
5996 22:16:52.277174 RX Delay -61 -> 252, step: 4
5997 22:16:52.283608 iDelay=207, Bit 0, Center 106 (19 ~ 194) 176
5998 22:16:52.287161 iDelay=207, Bit 1, Center 96 (11 ~ 182) 172
5999 22:16:52.290230 iDelay=207, Bit 2, Center 90 (3 ~ 178) 176
6000 22:16:52.293625 iDelay=207, Bit 3, Center 98 (15 ~ 182) 168
6001 22:16:52.296839 iDelay=207, Bit 4, Center 98 (7 ~ 190) 184
6002 22:16:52.303356 iDelay=207, Bit 5, Center 110 (23 ~ 198) 176
6003 22:16:52.306813 iDelay=207, Bit 6, Center 116 (27 ~ 206) 180
6004 22:16:52.310087 iDelay=207, Bit 7, Center 98 (7 ~ 190) 184
6005 22:16:52.313092 iDelay=207, Bit 8, Center 82 (-9 ~ 174) 184
6006 22:16:52.316399 iDelay=207, Bit 9, Center 84 (-5 ~ 174) 180
6007 22:16:52.319779 iDelay=207, Bit 10, Center 92 (-1 ~ 186) 188
6008 22:16:52.326659 iDelay=207, Bit 11, Center 84 (-5 ~ 174) 180
6009 22:16:52.330607 iDelay=207, Bit 12, Center 104 (15 ~ 194) 180
6010 22:16:52.333153 iDelay=207, Bit 13, Center 102 (11 ~ 194) 184
6011 22:16:52.336670 iDelay=207, Bit 14, Center 98 (7 ~ 190) 184
6012 22:16:52.340034 iDelay=207, Bit 15, Center 104 (15 ~ 194) 180
6013 22:16:52.343503 ==
6014 22:16:52.346708 Dram Type= 6, Freq= 0, CH_1, rank 1
6015 22:16:52.349812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
6016 22:16:52.350232 ==
6017 22:16:52.350591 DQS Delay:
6018 22:16:52.353480 DQS0 = 0, DQS1 = 0
6019 22:16:52.353895 DQM Delay:
6020 22:16:52.356747 DQM0 = 101, DQM1 = 93
6021 22:16:52.357242 DQ Delay:
6022 22:16:52.359465 DQ0 =106, DQ1 =96, DQ2 =90, DQ3 =98
6023 22:16:52.363528 DQ4 =98, DQ5 =110, DQ6 =116, DQ7 =98
6024 22:16:52.366266 DQ8 =82, DQ9 =84, DQ10 =92, DQ11 =84
6025 22:16:52.369627 DQ12 =104, DQ13 =102, DQ14 =98, DQ15 =104
6026 22:16:52.370065
6027 22:16:52.370506
6028 22:16:52.379322 [DQSOSCAuto] RK1, (LSB)MR18= 0x801, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 419 ps
6029 22:16:52.379770 CH1 RK1: MR19=505, MR18=801
6030 22:16:52.386044 CH1_RK1: MR19=0x505, MR18=0x801, DQSOSC=419, MR23=63, INC=61, DEC=41
6031 22:16:52.389337 [RxdqsGatingPostProcess] freq 933
6032 22:16:52.395845 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6033 22:16:52.399231 best DQS0 dly(2T, 0.5T) = (0, 10)
6034 22:16:52.402421 best DQS1 dly(2T, 0.5T) = (0, 10)
6035 22:16:52.405868 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6036 22:16:52.408806 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6037 22:16:52.412553 best DQS0 dly(2T, 0.5T) = (0, 10)
6038 22:16:52.413020 best DQS1 dly(2T, 0.5T) = (0, 10)
6039 22:16:52.415934 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6040 22:16:52.419387 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6041 22:16:52.422116 Pre-setting of DQS Precalculation
6042 22:16:52.429081 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6043 22:16:52.435113 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6044 22:16:52.442128 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6045 22:16:52.442724
6046 22:16:52.443218
6047 22:16:52.445168 [Calibration Summary] 1866 Mbps
6048 22:16:52.448423 CH 0, Rank 0
6049 22:16:52.448781 SW Impedance : PASS
6050 22:16:52.451729 DUTY Scan : NO K
6051 22:16:52.455951 ZQ Calibration : PASS
6052 22:16:52.456361 Jitter Meter : NO K
6053 22:16:52.458783 CBT Training : PASS
6054 22:16:52.459433 Write leveling : PASS
6055 22:16:52.461642 RX DQS gating : PASS
6056 22:16:52.465231 RX DQ/DQS(RDDQC) : PASS
6057 22:16:52.465640 TX DQ/DQS : PASS
6058 22:16:52.468582 RX DATLAT : PASS
6059 22:16:52.471495 RX DQ/DQS(Engine): PASS
6060 22:16:52.471900 TX OE : NO K
6061 22:16:52.475115 All Pass.
6062 22:16:52.475538
6063 22:16:52.475855 CH 0, Rank 1
6064 22:16:52.478390 SW Impedance : PASS
6065 22:16:52.478822 DUTY Scan : NO K
6066 22:16:52.481468 ZQ Calibration : PASS
6067 22:16:52.484715 Jitter Meter : NO K
6068 22:16:52.485123 CBT Training : PASS
6069 22:16:52.488660 Write leveling : PASS
6070 22:16:52.491309 RX DQS gating : PASS
6071 22:16:52.491716 RX DQ/DQS(RDDQC) : PASS
6072 22:16:52.494832 TX DQ/DQS : PASS
6073 22:16:52.497986 RX DATLAT : PASS
6074 22:16:52.498393 RX DQ/DQS(Engine): PASS
6075 22:16:52.501120 TX OE : NO K
6076 22:16:52.501533 All Pass.
6077 22:16:52.501853
6078 22:16:52.504535 CH 1, Rank 0
6079 22:16:52.504945 SW Impedance : PASS
6080 22:16:52.507897 DUTY Scan : NO K
6081 22:16:52.510771 ZQ Calibration : PASS
6082 22:16:52.511216 Jitter Meter : NO K
6083 22:16:52.514436 CBT Training : PASS
6084 22:16:52.517462 Write leveling : PASS
6085 22:16:52.517875 RX DQS gating : PASS
6086 22:16:52.520959 RX DQ/DQS(RDDQC) : PASS
6087 22:16:52.524671 TX DQ/DQS : PASS
6088 22:16:52.525085 RX DATLAT : PASS
6089 22:16:52.527608 RX DQ/DQS(Engine): PASS
6090 22:16:52.531047 TX OE : NO K
6091 22:16:52.531496 All Pass.
6092 22:16:52.531819
6093 22:16:52.532120 CH 1, Rank 1
6094 22:16:52.534092 SW Impedance : PASS
6095 22:16:52.537408 DUTY Scan : NO K
6096 22:16:52.537817 ZQ Calibration : PASS
6097 22:16:52.541100 Jitter Meter : NO K
6098 22:16:52.541646 CBT Training : PASS
6099 22:16:52.543901 Write leveling : PASS
6100 22:16:52.547728 RX DQS gating : PASS
6101 22:16:52.548141 RX DQ/DQS(RDDQC) : PASS
6102 22:16:52.550575 TX DQ/DQS : PASS
6103 22:16:52.554257 RX DATLAT : PASS
6104 22:16:52.554697 RX DQ/DQS(Engine): PASS
6105 22:16:52.557502 TX OE : NO K
6106 22:16:52.557933 All Pass.
6107 22:16:52.558256
6108 22:16:52.560706 DramC Write-DBI off
6109 22:16:52.564131 PER_BANK_REFRESH: Hybrid Mode
6110 22:16:52.564542 TX_TRACKING: ON
6111 22:16:52.573644 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6112 22:16:52.577496 [FAST_K] Save calibration result to emmc
6113 22:16:52.580706 dramc_set_vcore_voltage set vcore to 650000
6114 22:16:52.583826 Read voltage for 400, 6
6115 22:16:52.584239 Vio18 = 0
6116 22:16:52.584560 Vcore = 650000
6117 22:16:52.586819 Vdram = 0
6118 22:16:52.587341 Vddq = 0
6119 22:16:52.587674 Vmddr = 0
6120 22:16:52.593824 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6121 22:16:52.596942 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6122 22:16:52.600167 MEM_TYPE=3, freq_sel=20
6123 22:16:52.603757 sv_algorithm_assistance_LP4_800
6124 22:16:52.606782 ============ PULL DRAM RESETB DOWN ============
6125 22:16:52.613703 ========== PULL DRAM RESETB DOWN end =========
6126 22:16:52.616640 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6127 22:16:52.620207 ===================================
6128 22:16:52.623160 LPDDR4 DRAM CONFIGURATION
6129 22:16:52.626490 ===================================
6130 22:16:52.626906 EX_ROW_EN[0] = 0x0
6131 22:16:52.630308 EX_ROW_EN[1] = 0x0
6132 22:16:52.630796 LP4Y_EN = 0x0
6133 22:16:52.633420 WORK_FSP = 0x0
6134 22:16:52.633906 WL = 0x2
6135 22:16:52.636802 RL = 0x2
6136 22:16:52.636881 BL = 0x2
6137 22:16:52.639743 RPST = 0x0
6138 22:16:52.639828 RD_PRE = 0x0
6139 22:16:52.643339 WR_PRE = 0x1
6140 22:16:52.646174 WR_PST = 0x0
6141 22:16:52.646265 DBI_WR = 0x0
6142 22:16:52.649662 DBI_RD = 0x0
6143 22:16:52.649771 OTF = 0x1
6144 22:16:52.653004 ===================================
6145 22:16:52.655862 ===================================
6146 22:16:52.659107 ANA top config
6147 22:16:52.662736 ===================================
6148 22:16:52.662823 DLL_ASYNC_EN = 0
6149 22:16:52.666121 ALL_SLAVE_EN = 1
6150 22:16:52.669531 NEW_RANK_MODE = 1
6151 22:16:52.672390 DLL_IDLE_MODE = 1
6152 22:16:52.672505 LP45_APHY_COMB_EN = 1
6153 22:16:52.675553 TX_ODT_DIS = 1
6154 22:16:52.678995 NEW_8X_MODE = 1
6155 22:16:52.682115 ===================================
6156 22:16:52.685712 ===================================
6157 22:16:52.689200 data_rate = 800
6158 22:16:52.692064 CKR = 1
6159 22:16:52.695515 DQ_P2S_RATIO = 4
6160 22:16:52.698922 ===================================
6161 22:16:52.699045 CA_P2S_RATIO = 4
6162 22:16:52.702541 DQ_CA_OPEN = 0
6163 22:16:52.705356 DQ_SEMI_OPEN = 1
6164 22:16:52.708699 CA_SEMI_OPEN = 1
6165 22:16:52.712373 CA_FULL_RATE = 0
6166 22:16:52.715345 DQ_CKDIV4_EN = 0
6167 22:16:52.715481 CA_CKDIV4_EN = 1
6168 22:16:52.718507 CA_PREDIV_EN = 0
6169 22:16:52.722044 PH8_DLY = 0
6170 22:16:52.725278 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6171 22:16:52.729147 DQ_AAMCK_DIV = 0
6172 22:16:52.731823 CA_AAMCK_DIV = 0
6173 22:16:52.732010 CA_ADMCK_DIV = 4
6174 22:16:52.735317 DQ_TRACK_CA_EN = 0
6175 22:16:52.738280 CA_PICK = 800
6176 22:16:52.741823 CA_MCKIO = 400
6177 22:16:52.745062 MCKIO_SEMI = 400
6178 22:16:52.748525 PLL_FREQ = 3016
6179 22:16:52.752128 DQ_UI_PI_RATIO = 32
6180 22:16:52.755204 CA_UI_PI_RATIO = 32
6181 22:16:52.758462 ===================================
6182 22:16:52.761452 ===================================
6183 22:16:52.761811 memory_type:LPDDR4
6184 22:16:52.764928 GP_NUM : 10
6185 22:16:52.767949 SRAM_EN : 1
6186 22:16:52.768301 MD32_EN : 0
6187 22:16:52.771250 ===================================
6188 22:16:52.774767 [ANA_INIT] >>>>>>>>>>>>>>
6189 22:16:52.778038 <<<<<< [CONFIGURE PHASE]: ANA_TX
6190 22:16:52.781155 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6191 22:16:52.784999 ===================================
6192 22:16:52.787903 data_rate = 800,PCW = 0X7400
6193 22:16:52.791086 ===================================
6194 22:16:52.795184 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6195 22:16:52.798274 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6196 22:16:52.810572 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6197 22:16:52.813988 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6198 22:16:52.817313 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6199 22:16:52.821153 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6200 22:16:52.824181 [ANA_INIT] flow start
6201 22:16:52.827672 [ANA_INIT] PLL >>>>>>>>
6202 22:16:52.827753 [ANA_INIT] PLL <<<<<<<<
6203 22:16:52.831205 [ANA_INIT] MIDPI >>>>>>>>
6204 22:16:52.834059 [ANA_INIT] MIDPI <<<<<<<<
6205 22:16:52.834158 [ANA_INIT] DLL >>>>>>>>
6206 22:16:52.837388 [ANA_INIT] flow end
6207 22:16:52.841008 ============ LP4 DIFF to SE enter ============
6208 22:16:52.843628 ============ LP4 DIFF to SE exit ============
6209 22:16:52.847228 [ANA_INIT] <<<<<<<<<<<<<
6210 22:16:52.850505 [Flow] Enable top DCM control >>>>>
6211 22:16:52.853918 [Flow] Enable top DCM control <<<<<
6212 22:16:52.857161 Enable DLL master slave shuffle
6213 22:16:52.863484 ==============================================================
6214 22:16:52.863639 Gating Mode config
6215 22:16:52.870398 ==============================================================
6216 22:16:52.873452 Config description:
6217 22:16:52.880274 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6218 22:16:52.887329 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6219 22:16:52.893859 SELPH_MODE 0: By rank 1: By Phase
6220 22:16:52.900856 ==============================================================
6221 22:16:52.901280 GAT_TRACK_EN = 0
6222 22:16:52.903400 RX_GATING_MODE = 2
6223 22:16:52.906987 RX_GATING_TRACK_MODE = 2
6224 22:16:52.910216 SELPH_MODE = 1
6225 22:16:52.913331 PICG_EARLY_EN = 1
6226 22:16:52.916642 VALID_LAT_VALUE = 1
6227 22:16:52.923249 ==============================================================
6228 22:16:52.926610 Enter into Gating configuration >>>>
6229 22:16:52.929881 Exit from Gating configuration <<<<
6230 22:16:52.933218 Enter into DVFS_PRE_config >>>>>
6231 22:16:52.942831 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6232 22:16:52.946553 Exit from DVFS_PRE_config <<<<<
6233 22:16:52.949647 Enter into PICG configuration >>>>
6234 22:16:52.953455 Exit from PICG configuration <<<<
6235 22:16:52.956274 [RX_INPUT] configuration >>>>>
6236 22:16:52.959447 [RX_INPUT] configuration <<<<<
6237 22:16:52.962883 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6238 22:16:52.969392 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6239 22:16:52.976361 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6240 22:16:52.982377 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6241 22:16:52.986253 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6242 22:16:52.992849 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6243 22:16:52.995770 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6244 22:16:53.002234 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6245 22:16:53.005373 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6246 22:16:53.008861 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6247 22:16:53.012278 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6248 22:16:53.019046 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6249 22:16:53.021839 ===================================
6250 22:16:53.026003 LPDDR4 DRAM CONFIGURATION
6251 22:16:53.028166 ===================================
6252 22:16:53.028379 EX_ROW_EN[0] = 0x0
6253 22:16:53.031715 EX_ROW_EN[1] = 0x0
6254 22:16:53.031891 LP4Y_EN = 0x0
6255 22:16:53.034841 WORK_FSP = 0x0
6256 22:16:53.035011 WL = 0x2
6257 22:16:53.038413 RL = 0x2
6258 22:16:53.038670 BL = 0x2
6259 22:16:53.041625 RPST = 0x0
6260 22:16:53.041913 RD_PRE = 0x0
6261 22:16:53.045044 WR_PRE = 0x1
6262 22:16:53.048375 WR_PST = 0x0
6263 22:16:53.048574 DBI_WR = 0x0
6264 22:16:53.052074 DBI_RD = 0x0
6265 22:16:53.052410 OTF = 0x1
6266 22:16:53.055831 ===================================
6267 22:16:53.058916 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6268 22:16:53.061787 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6269 22:16:53.068847 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6270 22:16:53.071648 ===================================
6271 22:16:53.075384 LPDDR4 DRAM CONFIGURATION
6272 22:16:53.078278 ===================================
6273 22:16:53.078738 EX_ROW_EN[0] = 0x10
6274 22:16:53.081622 EX_ROW_EN[1] = 0x0
6275 22:16:53.082122 LP4Y_EN = 0x0
6276 22:16:53.085402 WORK_FSP = 0x0
6277 22:16:53.085961 WL = 0x2
6278 22:16:53.088239 RL = 0x2
6279 22:16:53.088804 BL = 0x2
6280 22:16:53.091588 RPST = 0x0
6281 22:16:53.094936 RD_PRE = 0x0
6282 22:16:53.095626 WR_PRE = 0x1
6283 22:16:53.097937 WR_PST = 0x0
6284 22:16:53.098396 DBI_WR = 0x0
6285 22:16:53.101332 DBI_RD = 0x0
6286 22:16:53.101884 OTF = 0x1
6287 22:16:53.104961 ===================================
6288 22:16:53.111229 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6289 22:16:53.115271 nWR fixed to 30
6290 22:16:53.118264 [ModeRegInit_LP4] CH0 RK0
6291 22:16:53.118725 [ModeRegInit_LP4] CH0 RK1
6292 22:16:53.121450 [ModeRegInit_LP4] CH1 RK0
6293 22:16:53.125331 [ModeRegInit_LP4] CH1 RK1
6294 22:16:53.125789 match AC timing 19
6295 22:16:53.131228 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6296 22:16:53.135202 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6297 22:16:53.138255 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6298 22:16:53.145135 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6299 22:16:53.148716 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6300 22:16:53.149178 ==
6301 22:16:53.151607 Dram Type= 6, Freq= 0, CH_0, rank 0
6302 22:16:53.154795 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6303 22:16:53.155404 ==
6304 22:16:53.161324 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6305 22:16:53.167916 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6306 22:16:53.171345 [CA 0] Center 36 (8~64) winsize 57
6307 22:16:53.174948 [CA 1] Center 36 (8~64) winsize 57
6308 22:16:53.178050 [CA 2] Center 36 (8~64) winsize 57
6309 22:16:53.181199 [CA 3] Center 36 (8~64) winsize 57
6310 22:16:53.185191 [CA 4] Center 36 (8~64) winsize 57
6311 22:16:53.185748 [CA 5] Center 36 (8~64) winsize 57
6312 22:16:53.187899
6313 22:16:53.191518 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6314 22:16:53.191980
6315 22:16:53.194626 [CATrainingPosCal] consider 1 rank data
6316 22:16:53.197939 u2DelayCellTimex100 = 270/100 ps
6317 22:16:53.201255 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6318 22:16:53.204578 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6319 22:16:53.207810 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6320 22:16:53.210788 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6321 22:16:53.214251 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6322 22:16:53.217638 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6323 22:16:53.218188
6324 22:16:53.220789 CA PerBit enable=1, Macro0, CA PI delay=36
6325 22:16:53.224073
6326 22:16:53.224524 [CBTSetCACLKResult] CA Dly = 36
6327 22:16:53.226969 CS Dly: 1 (0~32)
6328 22:16:53.227464 ==
6329 22:16:53.230566 Dram Type= 6, Freq= 0, CH_0, rank 1
6330 22:16:53.234329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6331 22:16:53.234885 ==
6332 22:16:53.240616 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6333 22:16:53.247245 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6334 22:16:53.249875 [CA 0] Center 36 (8~64) winsize 57
6335 22:16:53.253700 [CA 1] Center 36 (8~64) winsize 57
6336 22:16:53.256958 [CA 2] Center 36 (8~64) winsize 57
6337 22:16:53.260019 [CA 3] Center 36 (8~64) winsize 57
6338 22:16:53.260597 [CA 4] Center 36 (8~64) winsize 57
6339 22:16:53.263504 [CA 5] Center 36 (8~64) winsize 57
6340 22:16:53.263955
6341 22:16:53.270331 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6342 22:16:53.270977
6343 22:16:53.273403 [CATrainingPosCal] consider 2 rank data
6344 22:16:53.276495 u2DelayCellTimex100 = 270/100 ps
6345 22:16:53.280161 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6346 22:16:53.283548 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6347 22:16:53.287203 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6348 22:16:53.289957 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6349 22:16:53.293124 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6350 22:16:53.296804 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6351 22:16:53.297391
6352 22:16:53.300048 CA PerBit enable=1, Macro0, CA PI delay=36
6353 22:16:53.300503
6354 22:16:53.303101 [CBTSetCACLKResult] CA Dly = 36
6355 22:16:53.306203 CS Dly: 1 (0~32)
6356 22:16:53.306753
6357 22:16:53.309886 ----->DramcWriteLeveling(PI) begin...
6358 22:16:53.310444 ==
6359 22:16:53.312759 Dram Type= 6, Freq= 0, CH_0, rank 0
6360 22:16:53.315975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6361 22:16:53.316425 ==
6362 22:16:53.319598 Write leveling (Byte 0): 40 => 8
6363 22:16:53.323109 Write leveling (Byte 1): 32 => 0
6364 22:16:53.325827 DramcWriteLeveling(PI) end<-----
6365 22:16:53.326280
6366 22:16:53.326621 ==
6367 22:16:53.329492 Dram Type= 6, Freq= 0, CH_0, rank 0
6368 22:16:53.333043 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6369 22:16:53.333488 ==
6370 22:16:53.336148 [Gating] SW mode calibration
6371 22:16:53.342713 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6372 22:16:53.349315 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6373 22:16:53.352704 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6374 22:16:53.359040 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6375 22:16:53.362320 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6376 22:16:53.366084 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6377 22:16:53.372764 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6378 22:16:53.375824 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6379 22:16:53.379419 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6380 22:16:53.385210 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6381 22:16:53.388803 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6382 22:16:53.392186 Total UI for P1: 0, mck2ui 16
6383 22:16:53.395694 best dqsien dly found for B0: ( 0, 14, 24)
6384 22:16:53.398851 Total UI for P1: 0, mck2ui 16
6385 22:16:53.401789 best dqsien dly found for B1: ( 0, 14, 24)
6386 22:16:53.405285 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6387 22:16:53.409310 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6388 22:16:53.409755
6389 22:16:53.411850 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6390 22:16:53.415427 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6391 22:16:53.418492 [Gating] SW calibration Done
6392 22:16:53.418931 ==
6393 22:16:53.421699 Dram Type= 6, Freq= 0, CH_0, rank 0
6394 22:16:53.425170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6395 22:16:53.428204 ==
6396 22:16:53.428761 RX Vref Scan: 0
6397 22:16:53.429119
6398 22:16:53.431949 RX Vref 0 -> 0, step: 1
6399 22:16:53.432359
6400 22:16:53.435134 RX Delay -410 -> 252, step: 16
6401 22:16:53.438510 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6402 22:16:53.441591 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6403 22:16:53.444810 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6404 22:16:53.452057 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6405 22:16:53.454823 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6406 22:16:53.458733 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6407 22:16:53.462140 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6408 22:16:53.467907 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6409 22:16:53.471333 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6410 22:16:53.474146 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6411 22:16:53.477754 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6412 22:16:53.484443 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6413 22:16:53.487952 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6414 22:16:53.490800 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6415 22:16:53.497399 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6416 22:16:53.500957 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6417 22:16:53.501370 ==
6418 22:16:53.504382 Dram Type= 6, Freq= 0, CH_0, rank 0
6419 22:16:53.507399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6420 22:16:53.507850 ==
6421 22:16:53.510727 DQS Delay:
6422 22:16:53.511307 DQS0 = 43, DQS1 = 51
6423 22:16:53.514139 DQM Delay:
6424 22:16:53.514546 DQM0 = 9, DQM1 = 6
6425 22:16:53.514894 DQ Delay:
6426 22:16:53.517173 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =0
6427 22:16:53.520705 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6428 22:16:53.523807 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6429 22:16:53.527447 DQ12 =8, DQ13 =8, DQ14 =16, DQ15 =8
6430 22:16:53.527912
6431 22:16:53.528245
6432 22:16:53.528544 ==
6433 22:16:53.530302 Dram Type= 6, Freq= 0, CH_0, rank 0
6434 22:16:53.533653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6435 22:16:53.534082 ==
6436 22:16:53.537208
6437 22:16:53.537620
6438 22:16:53.537941 TX Vref Scan disable
6439 22:16:53.540281 == TX Byte 0 ==
6440 22:16:53.544036 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6441 22:16:53.546886 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6442 22:16:53.550434 == TX Byte 1 ==
6443 22:16:53.553889 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6444 22:16:53.556837 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6445 22:16:53.557253 ==
6446 22:16:53.560067 Dram Type= 6, Freq= 0, CH_0, rank 0
6447 22:16:53.566575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6448 22:16:53.566988 ==
6449 22:16:53.567347
6450 22:16:53.567650
6451 22:16:53.567937 TX Vref Scan disable
6452 22:16:53.570084 == TX Byte 0 ==
6453 22:16:53.573787 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6454 22:16:53.576691 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6455 22:16:53.580074 == TX Byte 1 ==
6456 22:16:53.583487 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6457 22:16:53.586998 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6458 22:16:53.587524
6459 22:16:53.590069 [DATLAT]
6460 22:16:53.590489 Freq=400, CH0 RK0
6461 22:16:53.590912
6462 22:16:53.593448 DATLAT Default: 0xf
6463 22:16:53.593870 0, 0xFFFF, sum = 0
6464 22:16:53.596790 1, 0xFFFF, sum = 0
6465 22:16:53.597217 2, 0xFFFF, sum = 0
6466 22:16:53.599964 3, 0xFFFF, sum = 0
6467 22:16:53.600408 4, 0xFFFF, sum = 0
6468 22:16:53.603745 5, 0xFFFF, sum = 0
6469 22:16:53.604267 6, 0xFFFF, sum = 0
6470 22:16:53.607260 7, 0xFFFF, sum = 0
6471 22:16:53.607784 8, 0xFFFF, sum = 0
6472 22:16:53.610177 9, 0xFFFF, sum = 0
6473 22:16:53.613891 10, 0xFFFF, sum = 0
6474 22:16:53.614458 11, 0xFFFF, sum = 0
6475 22:16:53.616792 12, 0xFFFF, sum = 0
6476 22:16:53.617358 13, 0x0, sum = 1
6477 22:16:53.619600 14, 0x0, sum = 2
6478 22:16:53.620032 15, 0x0, sum = 3
6479 22:16:53.620458 16, 0x0, sum = 4
6480 22:16:53.623049 best_step = 14
6481 22:16:53.623500
6482 22:16:53.623917 ==
6483 22:16:53.626184 Dram Type= 6, Freq= 0, CH_0, rank 0
6484 22:16:53.629820 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6485 22:16:53.630354 ==
6486 22:16:53.633536 RX Vref Scan: 1
6487 22:16:53.634065
6488 22:16:53.636586 RX Vref 0 -> 0, step: 1
6489 22:16:53.637105
6490 22:16:53.637534 RX Delay -343 -> 252, step: 8
6491 22:16:53.637937
6492 22:16:53.639756 Set Vref, RX VrefLevel [Byte0]: 58
6493 22:16:53.643109 [Byte1]: 51
6494 22:16:53.648676
6495 22:16:53.649201 Final RX Vref Byte 0 = 58 to rank0
6496 22:16:53.652117 Final RX Vref Byte 1 = 51 to rank0
6497 22:16:53.654852 Final RX Vref Byte 0 = 58 to rank1
6498 22:16:53.658329 Final RX Vref Byte 1 = 51 to rank1==
6499 22:16:53.661508 Dram Type= 6, Freq= 0, CH_0, rank 0
6500 22:16:53.667979 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6501 22:16:53.668487 ==
6502 22:16:53.668869 DQS Delay:
6503 22:16:53.671911 DQS0 = 44, DQS1 = 60
6504 22:16:53.672418 DQM Delay:
6505 22:16:53.672743 DQM0 = 8, DQM1 = 12
6506 22:16:53.674362 DQ Delay:
6507 22:16:53.678262 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =4
6508 22:16:53.681458 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6509 22:16:53.682024 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =4
6510 22:16:53.684395 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6511 22:16:53.687900
6512 22:16:53.688490
6513 22:16:53.694595 [DQSOSCAuto] RK0, (LSB)MR18= 0xc184, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 385 ps
6514 22:16:53.698027 CH0 RK0: MR19=C0C, MR18=C184
6515 22:16:53.704527 CH0_RK0: MR19=0xC0C, MR18=0xC184, DQSOSC=385, MR23=63, INC=398, DEC=265
6516 22:16:53.705094 ==
6517 22:16:53.707603 Dram Type= 6, Freq= 0, CH_0, rank 1
6518 22:16:53.711033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6519 22:16:53.711637 ==
6520 22:16:53.713964 [Gating] SW mode calibration
6521 22:16:53.720811 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6522 22:16:53.728528 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6523 22:16:53.730996 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6524 22:16:53.734224 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6525 22:16:53.740844 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6526 22:16:53.743911 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6527 22:16:53.747122 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6528 22:16:53.753883 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6529 22:16:53.757732 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6530 22:16:53.760441 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6531 22:16:53.768065 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6532 22:16:53.768615 Total UI for P1: 0, mck2ui 16
6533 22:16:53.773760 best dqsien dly found for B0: ( 0, 14, 24)
6534 22:16:53.774327 Total UI for P1: 0, mck2ui 16
6535 22:16:53.780421 best dqsien dly found for B1: ( 0, 14, 24)
6536 22:16:53.783761 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6537 22:16:53.786898 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6538 22:16:53.787485
6539 22:16:53.789952 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6540 22:16:53.793748 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6541 22:16:53.797091 [Gating] SW calibration Done
6542 22:16:53.797550 ==
6543 22:16:53.799986 Dram Type= 6, Freq= 0, CH_0, rank 1
6544 22:16:53.803685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6545 22:16:53.804242 ==
6546 22:16:53.806984 RX Vref Scan: 0
6547 22:16:53.807574
6548 22:16:53.807935 RX Vref 0 -> 0, step: 1
6549 22:16:53.808266
6550 22:16:53.810240 RX Delay -410 -> 252, step: 16
6551 22:16:53.816805 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6552 22:16:53.820113 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6553 22:16:53.823004 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6554 22:16:53.826141 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6555 22:16:53.833466 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6556 22:16:53.836756 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6557 22:16:53.839618 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6558 22:16:53.843203 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6559 22:16:53.849724 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6560 22:16:53.853048 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6561 22:16:53.856056 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6562 22:16:53.862337 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6563 22:16:53.865974 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6564 22:16:53.869527 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6565 22:16:53.872913 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6566 22:16:53.879557 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6567 22:16:53.880115 ==
6568 22:16:53.882713 Dram Type= 6, Freq= 0, CH_0, rank 1
6569 22:16:53.885836 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6570 22:16:53.886399 ==
6571 22:16:53.886766 DQS Delay:
6572 22:16:53.888988 DQS0 = 43, DQS1 = 59
6573 22:16:53.889500 DQM Delay:
6574 22:16:53.892685 DQM0 = 11, DQM1 = 16
6575 22:16:53.893258 DQ Delay:
6576 22:16:53.895567 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6577 22:16:53.899287 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =24
6578 22:16:53.902655 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6579 22:16:53.905860 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6580 22:16:53.906488
6581 22:16:53.906853
6582 22:16:53.907294 ==
6583 22:16:53.908590 Dram Type= 6, Freq= 0, CH_0, rank 1
6584 22:16:53.912357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6585 22:16:53.912919 ==
6586 22:16:53.913280
6587 22:16:53.913611
6588 22:16:53.915447 TX Vref Scan disable
6589 22:16:53.918806 == TX Byte 0 ==
6590 22:16:53.922654 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6591 22:16:53.925726 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6592 22:16:53.928419 == TX Byte 1 ==
6593 22:16:53.931974 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6594 22:16:53.935237 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6595 22:16:53.935812 ==
6596 22:16:53.938776 Dram Type= 6, Freq= 0, CH_0, rank 1
6597 22:16:53.941978 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6598 22:16:53.942573 ==
6599 22:16:53.945211
6600 22:16:53.945664
6601 22:16:53.946019 TX Vref Scan disable
6602 22:16:53.948623 == TX Byte 0 ==
6603 22:16:53.951944 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6604 22:16:53.954975 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6605 22:16:53.958864 == TX Byte 1 ==
6606 22:16:53.961667 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6607 22:16:53.964629 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6608 22:16:53.965087
6609 22:16:53.965441 [DATLAT]
6610 22:16:53.968467 Freq=400, CH0 RK1
6611 22:16:53.969110
6612 22:16:53.971918 DATLAT Default: 0xe
6613 22:16:53.972484 0, 0xFFFF, sum = 0
6614 22:16:53.975132 1, 0xFFFF, sum = 0
6615 22:16:53.975702 2, 0xFFFF, sum = 0
6616 22:16:53.977801 3, 0xFFFF, sum = 0
6617 22:16:53.978265 4, 0xFFFF, sum = 0
6618 22:16:53.981484 5, 0xFFFF, sum = 0
6619 22:16:53.982051 6, 0xFFFF, sum = 0
6620 22:16:53.984357 7, 0xFFFF, sum = 0
6621 22:16:53.984821 8, 0xFFFF, sum = 0
6622 22:16:53.988232 9, 0xFFFF, sum = 0
6623 22:16:53.988839 10, 0xFFFF, sum = 0
6624 22:16:53.991143 11, 0xFFFF, sum = 0
6625 22:16:53.991611 12, 0xFFFF, sum = 0
6626 22:16:53.994445 13, 0x0, sum = 1
6627 22:16:53.995022 14, 0x0, sum = 2
6628 22:16:53.997836 15, 0x0, sum = 3
6629 22:16:53.998403 16, 0x0, sum = 4
6630 22:16:54.000890 best_step = 14
6631 22:16:54.001345
6632 22:16:54.001700 ==
6633 22:16:54.004377 Dram Type= 6, Freq= 0, CH_0, rank 1
6634 22:16:54.008111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6635 22:16:54.008680 ==
6636 22:16:54.011390 RX Vref Scan: 0
6637 22:16:54.011849
6638 22:16:54.012208 RX Vref 0 -> 0, step: 1
6639 22:16:54.012545
6640 22:16:54.014497 RX Delay -359 -> 252, step: 8
6641 22:16:54.022613 iDelay=217, Bit 0, Center -40 (-279 ~ 200) 480
6642 22:16:54.025711 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6643 22:16:54.029472 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6644 22:16:54.035829 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6645 22:16:54.039682 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6646 22:16:54.042396 iDelay=217, Bit 5, Center -44 (-287 ~ 200) 488
6647 22:16:54.045614 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6648 22:16:54.052068 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6649 22:16:54.056087 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6650 22:16:54.059053 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6651 22:16:54.061905 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
6652 22:16:54.069127 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6653 22:16:54.071968 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6654 22:16:54.075604 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6655 22:16:54.078785 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6656 22:16:54.085681 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6657 22:16:54.086238 ==
6658 22:16:54.088411 Dram Type= 6, Freq= 0, CH_0, rank 1
6659 22:16:54.091931 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6660 22:16:54.092390 ==
6661 22:16:54.092750 DQS Delay:
6662 22:16:54.095525 DQS0 = 44, DQS1 = 60
6663 22:16:54.096078 DQM Delay:
6664 22:16:54.098503 DQM0 = 8, DQM1 = 14
6665 22:16:54.099096 DQ Delay:
6666 22:16:54.101831 DQ0 =4, DQ1 =12, DQ2 =4, DQ3 =8
6667 22:16:54.105386 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6668 22:16:54.108484 DQ8 =4, DQ9 =0, DQ10 =20, DQ11 =8
6669 22:16:54.111529 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6670 22:16:54.111983
6671 22:16:54.112337
6672 22:16:54.118361 [DQSOSCAuto] RK1, (LSB)MR18= 0xb742, (MSB)MR19= 0xc0c, tDQSOscB0 = 401 ps tDQSOscB1 = 387 ps
6673 22:16:54.121630 CH0 RK1: MR19=C0C, MR18=B742
6674 22:16:54.128179 CH0_RK1: MR19=0xC0C, MR18=0xB742, DQSOSC=387, MR23=63, INC=394, DEC=262
6675 22:16:54.131675 [RxdqsGatingPostProcess] freq 400
6676 22:16:54.138211 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6677 22:16:54.141866 best DQS0 dly(2T, 0.5T) = (0, 10)
6678 22:16:54.144803 best DQS1 dly(2T, 0.5T) = (0, 10)
6679 22:16:54.147883 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6680 22:16:54.151468 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6681 22:16:54.151928 best DQS0 dly(2T, 0.5T) = (0, 10)
6682 22:16:54.154783 best DQS1 dly(2T, 0.5T) = (0, 10)
6683 22:16:54.158355 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6684 22:16:54.161428 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6685 22:16:54.164594 Pre-setting of DQS Precalculation
6686 22:16:54.171364 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6687 22:16:54.171902 ==
6688 22:16:54.174581 Dram Type= 6, Freq= 0, CH_1, rank 0
6689 22:16:54.178035 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6690 22:16:54.178493 ==
6691 22:16:54.185023 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6692 22:16:54.190859 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6693 22:16:54.194235 [CA 0] Center 36 (8~64) winsize 57
6694 22:16:54.197780 [CA 1] Center 36 (8~64) winsize 57
6695 22:16:54.198344 [CA 2] Center 36 (8~64) winsize 57
6696 22:16:54.200926 [CA 3] Center 36 (8~64) winsize 57
6697 22:16:54.204331 [CA 4] Center 36 (8~64) winsize 57
6698 22:16:54.207505 [CA 5] Center 36 (8~64) winsize 57
6699 22:16:54.208071
6700 22:16:54.210370 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6701 22:16:54.210855
6702 22:16:54.217573 [CATrainingPosCal] consider 1 rank data
6703 22:16:54.218155 u2DelayCellTimex100 = 270/100 ps
6704 22:16:54.224177 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6705 22:16:54.227923 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6706 22:16:54.230759 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6707 22:16:54.233611 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6708 22:16:54.237154 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6709 22:16:54.240545 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6710 22:16:54.241008
6711 22:16:54.243750 CA PerBit enable=1, Macro0, CA PI delay=36
6712 22:16:54.244410
6713 22:16:54.246933 [CBTSetCACLKResult] CA Dly = 36
6714 22:16:54.250142 CS Dly: 1 (0~32)
6715 22:16:54.250839 ==
6716 22:16:54.253537 Dram Type= 6, Freq= 0, CH_1, rank 1
6717 22:16:54.256788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6718 22:16:54.257512 ==
6719 22:16:54.263500 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6720 22:16:54.266591 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6721 22:16:54.270264 [CA 0] Center 36 (8~64) winsize 57
6722 22:16:54.273910 [CA 1] Center 36 (8~64) winsize 57
6723 22:16:54.276724 [CA 2] Center 36 (8~64) winsize 57
6724 22:16:54.279885 [CA 3] Center 36 (8~64) winsize 57
6725 22:16:54.283097 [CA 4] Center 36 (8~64) winsize 57
6726 22:16:54.286500 [CA 5] Center 36 (8~64) winsize 57
6727 22:16:54.286789
6728 22:16:54.289573 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6729 22:16:54.289846
6730 22:16:54.292872 [CATrainingPosCal] consider 2 rank data
6731 22:16:54.295741 u2DelayCellTimex100 = 270/100 ps
6732 22:16:54.299316 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6733 22:16:54.306137 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6734 22:16:54.309121 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6735 22:16:54.312333 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6736 22:16:54.315788 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6737 22:16:54.318984 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6738 22:16:54.319127
6739 22:16:54.322316 CA PerBit enable=1, Macro0, CA PI delay=36
6740 22:16:54.322441
6741 22:16:54.325991 [CBTSetCACLKResult] CA Dly = 36
6742 22:16:54.326115 CS Dly: 1 (0~32)
6743 22:16:54.328883
6744 22:16:54.332512 ----->DramcWriteLeveling(PI) begin...
6745 22:16:54.332639 ==
6746 22:16:54.335476 Dram Type= 6, Freq= 0, CH_1, rank 0
6747 22:16:54.339228 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6748 22:16:54.339353 ==
6749 22:16:54.342185 Write leveling (Byte 0): 40 => 8
6750 22:16:54.345444 Write leveling (Byte 1): 32 => 0
6751 22:16:54.348613 DramcWriteLeveling(PI) end<-----
6752 22:16:54.348737
6753 22:16:54.348850 ==
6754 22:16:54.352519 Dram Type= 6, Freq= 0, CH_1, rank 0
6755 22:16:54.355026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6756 22:16:54.355188 ==
6757 22:16:54.358648 [Gating] SW mode calibration
6758 22:16:54.364971 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6759 22:16:54.371607 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6760 22:16:54.374713 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6761 22:16:54.378136 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6762 22:16:54.385291 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6763 22:16:54.388266 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6764 22:16:54.391718 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6765 22:16:54.398219 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6766 22:16:54.401730 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6767 22:16:54.404619 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6768 22:16:54.411577 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6769 22:16:54.414600 Total UI for P1: 0, mck2ui 16
6770 22:16:54.417736 best dqsien dly found for B0: ( 0, 14, 24)
6771 22:16:54.421183 Total UI for P1: 0, mck2ui 16
6772 22:16:54.424500 best dqsien dly found for B1: ( 0, 14, 24)
6773 22:16:54.427454 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6774 22:16:54.431111 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6775 22:16:54.431237
6776 22:16:54.434044 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6777 22:16:54.437736 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6778 22:16:54.441183 [Gating] SW calibration Done
6779 22:16:54.441264 ==
6780 22:16:54.444004 Dram Type= 6, Freq= 0, CH_1, rank 0
6781 22:16:54.446962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6782 22:16:54.447044 ==
6783 22:16:54.450656 RX Vref Scan: 0
6784 22:16:54.450810
6785 22:16:54.453963 RX Vref 0 -> 0, step: 1
6786 22:16:54.454043
6787 22:16:54.454105 RX Delay -410 -> 252, step: 16
6788 22:16:54.460888 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6789 22:16:54.464314 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6790 22:16:54.467253 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6791 22:16:54.473937 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6792 22:16:54.477218 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6793 22:16:54.480889 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6794 22:16:54.483983 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6795 22:16:54.490099 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6796 22:16:54.493913 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6797 22:16:54.496889 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6798 22:16:54.500665 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6799 22:16:54.506915 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6800 22:16:54.510455 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6801 22:16:54.513204 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6802 22:16:54.516515 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6803 22:16:54.523485 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6804 22:16:54.523578 ==
6805 22:16:54.526744 Dram Type= 6, Freq= 0, CH_1, rank 0
6806 22:16:54.529675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6807 22:16:54.529792 ==
6808 22:16:54.529871 DQS Delay:
6809 22:16:54.533232 DQS0 = 43, DQS1 = 51
6810 22:16:54.533313 DQM Delay:
6811 22:16:54.536329 DQM0 = 12, DQM1 = 14
6812 22:16:54.536410 DQ Delay:
6813 22:16:54.539548 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6814 22:16:54.543388 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6815 22:16:54.546003 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6816 22:16:54.549511 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6817 22:16:54.549592
6818 22:16:54.549654
6819 22:16:54.549712 ==
6820 22:16:54.552971 Dram Type= 6, Freq= 0, CH_1, rank 0
6821 22:16:54.556126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6822 22:16:54.556206 ==
6823 22:16:54.559874
6824 22:16:54.559953
6825 22:16:54.560014 TX Vref Scan disable
6826 22:16:54.562933 == TX Byte 0 ==
6827 22:16:54.566251 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6828 22:16:54.570000 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6829 22:16:54.572996 == TX Byte 1 ==
6830 22:16:54.576287 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6831 22:16:54.579422 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6832 22:16:54.579501 ==
6833 22:16:54.583151 Dram Type= 6, Freq= 0, CH_1, rank 0
6834 22:16:54.589053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6835 22:16:54.589141 ==
6836 22:16:54.589210
6837 22:16:54.589269
6838 22:16:54.589327 TX Vref Scan disable
6839 22:16:54.592623 == TX Byte 0 ==
6840 22:16:54.595516 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6841 22:16:54.599470 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6842 22:16:54.602280 == TX Byte 1 ==
6843 22:16:54.606124 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6844 22:16:54.609061 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6845 22:16:54.609141
6846 22:16:54.612081 [DATLAT]
6847 22:16:54.612160 Freq=400, CH1 RK0
6848 22:16:54.612223
6849 22:16:54.615553 DATLAT Default: 0xf
6850 22:16:54.615631 0, 0xFFFF, sum = 0
6851 22:16:54.618873 1, 0xFFFF, sum = 0
6852 22:16:54.618953 2, 0xFFFF, sum = 0
6853 22:16:54.622653 3, 0xFFFF, sum = 0
6854 22:16:54.622734 4, 0xFFFF, sum = 0
6855 22:16:54.625481 5, 0xFFFF, sum = 0
6856 22:16:54.625562 6, 0xFFFF, sum = 0
6857 22:16:54.628532 7, 0xFFFF, sum = 0
6858 22:16:54.632149 8, 0xFFFF, sum = 0
6859 22:16:54.632256 9, 0xFFFF, sum = 0
6860 22:16:54.635181 10, 0xFFFF, sum = 0
6861 22:16:54.635260 11, 0xFFFF, sum = 0
6862 22:16:54.638630 12, 0xFFFF, sum = 0
6863 22:16:54.638709 13, 0x0, sum = 1
6864 22:16:54.641898 14, 0x0, sum = 2
6865 22:16:54.642046 15, 0x0, sum = 3
6866 22:16:54.644971 16, 0x0, sum = 4
6867 22:16:54.645051 best_step = 14
6868 22:16:54.645113
6869 22:16:54.645170 ==
6870 22:16:54.648696 Dram Type= 6, Freq= 0, CH_1, rank 0
6871 22:16:54.651998 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6872 22:16:54.652076 ==
6873 22:16:54.654975 RX Vref Scan: 1
6874 22:16:54.655107
6875 22:16:54.658191 RX Vref 0 -> 0, step: 1
6876 22:16:54.658270
6877 22:16:54.658330 RX Delay -343 -> 252, step: 8
6878 22:16:54.661783
6879 22:16:54.661861 Set Vref, RX VrefLevel [Byte0]: 47
6880 22:16:54.665042 [Byte1]: 53
6881 22:16:54.670916
6882 22:16:54.670994 Final RX Vref Byte 0 = 47 to rank0
6883 22:16:54.674093 Final RX Vref Byte 1 = 53 to rank0
6884 22:16:54.677439 Final RX Vref Byte 0 = 47 to rank1
6885 22:16:54.680427 Final RX Vref Byte 1 = 53 to rank1==
6886 22:16:54.683569 Dram Type= 6, Freq= 0, CH_1, rank 0
6887 22:16:54.690576 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6888 22:16:54.690657 ==
6889 22:16:54.690719 DQS Delay:
6890 22:16:54.693812 DQS0 = 44, DQS1 = 56
6891 22:16:54.693900 DQM Delay:
6892 22:16:54.693961 DQM0 = 8, DQM1 = 12
6893 22:16:54.696906 DQ Delay:
6894 22:16:54.700443 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6895 22:16:54.700522 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =4
6896 22:16:54.704022 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6897 22:16:54.706891 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6898 22:16:54.706994
6899 22:16:54.710395
6900 22:16:54.717141 [DQSOSCAuto] RK0, (LSB)MR18= 0x9d73, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 390 ps
6901 22:16:54.720059 CH1 RK0: MR19=C0C, MR18=9D73
6902 22:16:54.726634 CH1_RK0: MR19=0xC0C, MR18=0x9D73, DQSOSC=390, MR23=63, INC=388, DEC=258
6903 22:16:54.726777 ==
6904 22:16:54.730053 Dram Type= 6, Freq= 0, CH_1, rank 1
6905 22:16:54.733348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6906 22:16:54.733429 ==
6907 22:16:54.736756 [Gating] SW mode calibration
6908 22:16:54.742961 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6909 22:16:54.749873 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6910 22:16:54.753361 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6911 22:16:54.756358 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6912 22:16:54.763027 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6913 22:16:54.766335 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6914 22:16:54.769837 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6915 22:16:54.775990 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6916 22:16:54.779267 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6917 22:16:54.782873 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6918 22:16:54.789515 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6919 22:16:54.789598 Total UI for P1: 0, mck2ui 16
6920 22:16:54.796144 best dqsien dly found for B0: ( 0, 14, 24)
6921 22:16:54.796225 Total UI for P1: 0, mck2ui 16
6922 22:16:54.802536 best dqsien dly found for B1: ( 0, 14, 24)
6923 22:16:54.805512 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6924 22:16:54.809311 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6925 22:16:54.809392
6926 22:16:54.812183 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6927 22:16:54.815726 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6928 22:16:54.818916 [Gating] SW calibration Done
6929 22:16:54.818996 ==
6930 22:16:54.822214 Dram Type= 6, Freq= 0, CH_1, rank 1
6931 22:16:54.825552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6932 22:16:54.825633 ==
6933 22:16:54.829077 RX Vref Scan: 0
6934 22:16:54.829157
6935 22:16:54.829219 RX Vref 0 -> 0, step: 1
6936 22:16:54.832364
6937 22:16:54.832445 RX Delay -410 -> 252, step: 16
6938 22:16:54.838772 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6939 22:16:54.842514 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6940 22:16:54.845739 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6941 22:16:54.848412 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6942 22:16:54.855476 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6943 22:16:54.858590 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6944 22:16:54.861862 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6945 22:16:54.864989 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6946 22:16:54.872004 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6947 22:16:54.875337 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6948 22:16:54.878134 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6949 22:16:54.885081 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6950 22:16:54.888549 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6951 22:16:54.891989 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6952 22:16:54.894812 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6953 22:16:54.901288 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6954 22:16:54.901371 ==
6955 22:16:54.904770 Dram Type= 6, Freq= 0, CH_1, rank 1
6956 22:16:54.907678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6957 22:16:54.907760 ==
6958 22:16:54.907826 DQS Delay:
6959 22:16:54.911527 DQS0 = 51, DQS1 = 51
6960 22:16:54.911609 DQM Delay:
6961 22:16:54.914811 DQM0 = 20, DQM1 = 14
6962 22:16:54.914892 DQ Delay:
6963 22:16:54.917854 DQ0 =32, DQ1 =16, DQ2 =0, DQ3 =16
6964 22:16:54.921451 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6965 22:16:54.924554 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6966 22:16:54.927974 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6967 22:16:54.928132
6968 22:16:54.928204
6969 22:16:54.928271 ==
6970 22:16:54.931007 Dram Type= 6, Freq= 0, CH_1, rank 1
6971 22:16:54.934550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6972 22:16:54.934702 ==
6973 22:16:54.937855
6974 22:16:54.938030
6975 22:16:54.938111 TX Vref Scan disable
6976 22:16:54.941100 == TX Byte 0 ==
6977 22:16:54.944671 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6978 22:16:54.948334 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6979 22:16:54.951048 == TX Byte 1 ==
6980 22:16:54.954278 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6981 22:16:54.957674 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6982 22:16:54.957843 ==
6983 22:16:54.961441 Dram Type= 6, Freq= 0, CH_1, rank 1
6984 22:16:54.964127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6985 22:16:54.967947 ==
6986 22:16:54.968131
6987 22:16:54.968228
6988 22:16:54.968316 TX Vref Scan disable
6989 22:16:54.971272 == TX Byte 0 ==
6990 22:16:54.974470 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6991 22:16:54.977627 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6992 22:16:54.980696 == TX Byte 1 ==
6993 22:16:54.984145 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6994 22:16:54.987577 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6995 22:16:54.987798
6996 22:16:54.990486 [DATLAT]
6997 22:16:54.990730 Freq=400, CH1 RK1
6998 22:16:54.990905
6999 22:16:54.993736 DATLAT Default: 0xe
7000 22:16:54.993943 0, 0xFFFF, sum = 0
7001 22:16:54.997306 1, 0xFFFF, sum = 0
7002 22:16:54.997549 2, 0xFFFF, sum = 0
7003 22:16:55.001004 3, 0xFFFF, sum = 0
7004 22:16:55.001396 4, 0xFFFF, sum = 0
7005 22:16:55.004877 5, 0xFFFF, sum = 0
7006 22:16:55.005362 6, 0xFFFF, sum = 0
7007 22:16:55.007367 7, 0xFFFF, sum = 0
7008 22:16:55.007754 8, 0xFFFF, sum = 0
7009 22:16:55.011084 9, 0xFFFF, sum = 0
7010 22:16:55.011556 10, 0xFFFF, sum = 0
7011 22:16:55.014276 11, 0xFFFF, sum = 0
7012 22:16:55.017541 12, 0xFFFF, sum = 0
7013 22:16:55.018099 13, 0x0, sum = 1
7014 22:16:55.018734 14, 0x0, sum = 2
7015 22:16:55.020567 15, 0x0, sum = 3
7016 22:16:55.021040 16, 0x0, sum = 4
7017 22:16:55.023893 best_step = 14
7018 22:16:55.024346
7019 22:16:55.024704 ==
7020 22:16:55.027751 Dram Type= 6, Freq= 0, CH_1, rank 1
7021 22:16:55.031010 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7022 22:16:55.031618 ==
7023 22:16:55.034203 RX Vref Scan: 0
7024 22:16:55.034656
7025 22:16:55.035013 RX Vref 0 -> 0, step: 1
7026 22:16:55.035416
7027 22:16:55.037251 RX Delay -343 -> 252, step: 8
7028 22:16:55.045663 iDelay=225, Bit 0, Center -32 (-271 ~ 208) 480
7029 22:16:55.048765 iDelay=225, Bit 1, Center -40 (-279 ~ 200) 480
7030 22:16:55.052570 iDelay=225, Bit 2, Center -48 (-287 ~ 192) 480
7031 22:16:55.055171 iDelay=225, Bit 3, Center -40 (-279 ~ 200) 480
7032 22:16:55.061741 iDelay=225, Bit 4, Center -36 (-279 ~ 208) 488
7033 22:16:55.065223 iDelay=225, Bit 5, Center -28 (-271 ~ 216) 488
7034 22:16:55.068577 iDelay=225, Bit 6, Center -24 (-271 ~ 224) 496
7035 22:16:55.075349 iDelay=225, Bit 7, Center -36 (-279 ~ 208) 488
7036 22:16:55.078667 iDelay=225, Bit 8, Center -56 (-303 ~ 192) 496
7037 22:16:55.081630 iDelay=225, Bit 9, Center -56 (-303 ~ 192) 496
7038 22:16:55.085055 iDelay=225, Bit 10, Center -44 (-295 ~ 208) 504
7039 22:16:55.091447 iDelay=225, Bit 11, Center -52 (-295 ~ 192) 488
7040 22:16:55.094748 iDelay=225, Bit 12, Center -36 (-287 ~ 216) 504
7041 22:16:55.098352 iDelay=225, Bit 13, Center -40 (-287 ~ 208) 496
7042 22:16:55.101776 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
7043 22:16:55.108182 iDelay=225, Bit 15, Center -32 (-279 ~ 216) 496
7044 22:16:55.108805 ==
7045 22:16:55.110997 Dram Type= 6, Freq= 0, CH_1, rank 1
7046 22:16:55.114778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7047 22:16:55.115266 ==
7048 22:16:55.115626 DQS Delay:
7049 22:16:55.117909 DQS0 = 48, DQS1 = 56
7050 22:16:55.118358 DQM Delay:
7051 22:16:55.121301 DQM0 = 12, DQM1 = 11
7052 22:16:55.121751 DQ Delay:
7053 22:16:55.124416 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
7054 22:16:55.127684 DQ4 =12, DQ5 =20, DQ6 =24, DQ7 =12
7055 22:16:55.131139 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
7056 22:16:55.135038 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =24
7057 22:16:55.135535
7058 22:16:55.135890
7059 22:16:55.144656 [DQSOSCAuto] RK1, (LSB)MR18= 0x6756, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 396 ps
7060 22:16:55.145227 CH1 RK1: MR19=C0C, MR18=6756
7061 22:16:55.151089 CH1_RK1: MR19=0xC0C, MR18=0x6756, DQSOSC=396, MR23=63, INC=376, DEC=251
7062 22:16:55.154000 [RxdqsGatingPostProcess] freq 400
7063 22:16:55.160460 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7064 22:16:55.164080 best DQS0 dly(2T, 0.5T) = (0, 10)
7065 22:16:55.167522 best DQS1 dly(2T, 0.5T) = (0, 10)
7066 22:16:55.170974 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7067 22:16:55.173866 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7068 22:16:55.177358 best DQS0 dly(2T, 0.5T) = (0, 10)
7069 22:16:55.180501 best DQS1 dly(2T, 0.5T) = (0, 10)
7070 22:16:55.183548 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7071 22:16:55.186792 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7072 22:16:55.187281 Pre-setting of DQS Precalculation
7073 22:16:55.194047 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7074 22:16:55.200471 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7075 22:16:55.206651 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7076 22:16:55.207535
7077 22:16:55.208253
7078 22:16:55.209951 [Calibration Summary] 800 Mbps
7079 22:16:55.213516 CH 0, Rank 0
7080 22:16:55.214279 SW Impedance : PASS
7081 22:16:55.216891 DUTY Scan : NO K
7082 22:16:55.220458 ZQ Calibration : PASS
7083 22:16:55.221131 Jitter Meter : NO K
7084 22:16:55.222960 CBT Training : PASS
7085 22:16:55.226602 Write leveling : PASS
7086 22:16:55.227099 RX DQS gating : PASS
7087 22:16:55.229683 RX DQ/DQS(RDDQC) : PASS
7088 22:16:55.233031 TX DQ/DQS : PASS
7089 22:16:55.233413 RX DATLAT : PASS
7090 22:16:55.236163 RX DQ/DQS(Engine): PASS
7091 22:16:55.236448 TX OE : NO K
7092 22:16:55.239362 All Pass.
7093 22:16:55.239671
7094 22:16:55.239880 CH 0, Rank 1
7095 22:16:55.242918 SW Impedance : PASS
7096 22:16:55.243181 DUTY Scan : NO K
7097 22:16:55.245754 ZQ Calibration : PASS
7098 22:16:55.249220 Jitter Meter : NO K
7099 22:16:55.249439 CBT Training : PASS
7100 22:16:55.252415 Write leveling : NO K
7101 22:16:55.255665 RX DQS gating : PASS
7102 22:16:55.255824 RX DQ/DQS(RDDQC) : PASS
7103 22:16:55.258927 TX DQ/DQS : PASS
7104 22:16:55.262384 RX DATLAT : PASS
7105 22:16:55.262481 RX DQ/DQS(Engine): PASS
7106 22:16:55.266456 TX OE : NO K
7107 22:16:55.266622 All Pass.
7108 22:16:55.266701
7109 22:16:55.269436 CH 1, Rank 0
7110 22:16:55.269602 SW Impedance : PASS
7111 22:16:55.272413 DUTY Scan : NO K
7112 22:16:55.275847 ZQ Calibration : PASS
7113 22:16:55.276009 Jitter Meter : NO K
7114 22:16:55.278926 CBT Training : PASS
7115 22:16:55.282705 Write leveling : PASS
7116 22:16:55.282867 RX DQS gating : PASS
7117 22:16:55.285531 RX DQ/DQS(RDDQC) : PASS
7118 22:16:55.289307 TX DQ/DQS : PASS
7119 22:16:55.289470 RX DATLAT : PASS
7120 22:16:55.292410 RX DQ/DQS(Engine): PASS
7121 22:16:55.295852 TX OE : NO K
7122 22:16:55.295989 All Pass.
7123 22:16:55.296062
7124 22:16:55.296130 CH 1, Rank 1
7125 22:16:55.299021 SW Impedance : PASS
7126 22:16:55.302129 DUTY Scan : NO K
7127 22:16:55.302251 ZQ Calibration : PASS
7128 22:16:55.305442 Jitter Meter : NO K
7129 22:16:55.308997 CBT Training : PASS
7130 22:16:55.309166 Write leveling : NO K
7131 22:16:55.311823 RX DQS gating : PASS
7132 22:16:55.315463 RX DQ/DQS(RDDQC) : PASS
7133 22:16:55.315647 TX DQ/DQS : PASS
7134 22:16:55.318696 RX DATLAT : PASS
7135 22:16:55.321769 RX DQ/DQS(Engine): PASS
7136 22:16:55.321989 TX OE : NO K
7137 22:16:55.322108 All Pass.
7138 22:16:55.322205
7139 22:16:55.325046 DramC Write-DBI off
7140 22:16:55.328503 PER_BANK_REFRESH: Hybrid Mode
7141 22:16:55.328705 TX_TRACKING: ON
7142 22:16:55.338200 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7143 22:16:55.342342 [FAST_K] Save calibration result to emmc
7144 22:16:55.345251 dramc_set_vcore_voltage set vcore to 725000
7145 22:16:55.348268 Read voltage for 1600, 0
7146 22:16:55.348559 Vio18 = 0
7147 22:16:55.351626 Vcore = 725000
7148 22:16:55.351871 Vdram = 0
7149 22:16:55.352060 Vddq = 0
7150 22:16:55.352234 Vmddr = 0
7151 22:16:55.358021 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7152 22:16:55.365380 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7153 22:16:55.365942 MEM_TYPE=3, freq_sel=13
7154 22:16:55.368111 sv_algorithm_assistance_LP4_3733
7155 22:16:55.371806 ============ PULL DRAM RESETB DOWN ============
7156 22:16:55.378103 ========== PULL DRAM RESETB DOWN end =========
7157 22:16:55.381622 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7158 22:16:55.384674 ===================================
7159 22:16:55.388113 LPDDR4 DRAM CONFIGURATION
7160 22:16:55.391574 ===================================
7161 22:16:55.392147 EX_ROW_EN[0] = 0x0
7162 22:16:55.394778 EX_ROW_EN[1] = 0x0
7163 22:16:55.398331 LP4Y_EN = 0x0
7164 22:16:55.398788 WORK_FSP = 0x1
7165 22:16:55.401444 WL = 0x5
7166 22:16:55.401902 RL = 0x5
7167 22:16:55.404956 BL = 0x2
7168 22:16:55.405518 RPST = 0x0
7169 22:16:55.407938 RD_PRE = 0x0
7170 22:16:55.408499 WR_PRE = 0x1
7171 22:16:55.411544 WR_PST = 0x1
7172 22:16:55.412110 DBI_WR = 0x0
7173 22:16:55.414395 DBI_RD = 0x0
7174 22:16:55.414952 OTF = 0x1
7175 22:16:55.417857 ===================================
7176 22:16:55.420799 ===================================
7177 22:16:55.424314 ANA top config
7178 22:16:55.427502 ===================================
7179 22:16:55.427966 DLL_ASYNC_EN = 0
7180 22:16:55.431424 ALL_SLAVE_EN = 0
7181 22:16:55.434233 NEW_RANK_MODE = 1
7182 22:16:55.437872 DLL_IDLE_MODE = 1
7183 22:16:55.440796 LP45_APHY_COMB_EN = 1
7184 22:16:55.441257 TX_ODT_DIS = 0
7185 22:16:55.444610 NEW_8X_MODE = 1
7186 22:16:55.447929 ===================================
7187 22:16:55.450992 ===================================
7188 22:16:55.454445 data_rate = 3200
7189 22:16:55.457611 CKR = 1
7190 22:16:55.460713 DQ_P2S_RATIO = 8
7191 22:16:55.463941 ===================================
7192 22:16:55.467422 CA_P2S_RATIO = 8
7193 22:16:55.467983 DQ_CA_OPEN = 0
7194 22:16:55.470272 DQ_SEMI_OPEN = 0
7195 22:16:55.474001 CA_SEMI_OPEN = 0
7196 22:16:55.477295 CA_FULL_RATE = 0
7197 22:16:55.480224 DQ_CKDIV4_EN = 0
7198 22:16:55.484049 CA_CKDIV4_EN = 0
7199 22:16:55.484602 CA_PREDIV_EN = 0
7200 22:16:55.486910 PH8_DLY = 12
7201 22:16:55.490360 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7202 22:16:55.493325 DQ_AAMCK_DIV = 4
7203 22:16:55.496741 CA_AAMCK_DIV = 4
7204 22:16:55.499911 CA_ADMCK_DIV = 4
7205 22:16:55.500372 DQ_TRACK_CA_EN = 0
7206 22:16:55.503343 CA_PICK = 1600
7207 22:16:55.506988 CA_MCKIO = 1600
7208 22:16:55.510189 MCKIO_SEMI = 0
7209 22:16:55.513677 PLL_FREQ = 3068
7210 22:16:55.516705 DQ_UI_PI_RATIO = 32
7211 22:16:55.519732 CA_UI_PI_RATIO = 0
7212 22:16:55.523385 ===================================
7213 22:16:55.526411 ===================================
7214 22:16:55.529531 memory_type:LPDDR4
7215 22:16:55.529992 GP_NUM : 10
7216 22:16:55.533178 SRAM_EN : 1
7217 22:16:55.533680 MD32_EN : 0
7218 22:16:55.536285 ===================================
7219 22:16:55.539975 [ANA_INIT] >>>>>>>>>>>>>>
7220 22:16:55.543372 <<<<<< [CONFIGURE PHASE]: ANA_TX
7221 22:16:55.546526 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7222 22:16:55.549687 ===================================
7223 22:16:55.553743 data_rate = 3200,PCW = 0X7600
7224 22:16:55.556280 ===================================
7225 22:16:55.559706 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7226 22:16:55.566312 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7227 22:16:55.570061 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7228 22:16:55.576476 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7229 22:16:55.579406 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7230 22:16:55.582680 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7231 22:16:55.583308 [ANA_INIT] flow start
7232 22:16:55.585724 [ANA_INIT] PLL >>>>>>>>
7233 22:16:55.588916 [ANA_INIT] PLL <<<<<<<<
7234 22:16:55.589375 [ANA_INIT] MIDPI >>>>>>>>
7235 22:16:55.593419 [ANA_INIT] MIDPI <<<<<<<<
7236 22:16:55.595547 [ANA_INIT] DLL >>>>>>>>
7237 22:16:55.596027 [ANA_INIT] DLL <<<<<<<<
7238 22:16:55.598861 [ANA_INIT] flow end
7239 22:16:55.602964 ============ LP4 DIFF to SE enter ============
7240 22:16:55.609444 ============ LP4 DIFF to SE exit ============
7241 22:16:55.610005 [ANA_INIT] <<<<<<<<<<<<<
7242 22:16:55.612043 [Flow] Enable top DCM control >>>>>
7243 22:16:55.615878 [Flow] Enable top DCM control <<<<<
7244 22:16:55.619247 Enable DLL master slave shuffle
7245 22:16:55.625562 ==============================================================
7246 22:16:55.626027 Gating Mode config
7247 22:16:55.632353 ==============================================================
7248 22:16:55.635893 Config description:
7249 22:16:55.645710 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7250 22:16:55.651957 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7251 22:16:55.655357 SELPH_MODE 0: By rank 1: By Phase
7252 22:16:55.662432 ==============================================================
7253 22:16:55.664801 GAT_TRACK_EN = 1
7254 22:16:55.665302 RX_GATING_MODE = 2
7255 22:16:55.668349 RX_GATING_TRACK_MODE = 2
7256 22:16:55.671732 SELPH_MODE = 1
7257 22:16:55.675701 PICG_EARLY_EN = 1
7258 22:16:55.678387 VALID_LAT_VALUE = 1
7259 22:16:55.685166 ==============================================================
7260 22:16:55.688516 Enter into Gating configuration >>>>
7261 22:16:55.692191 Exit from Gating configuration <<<<
7262 22:16:55.694967 Enter into DVFS_PRE_config >>>>>
7263 22:16:55.704343 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7264 22:16:55.708087 Exit from DVFS_PRE_config <<<<<
7265 22:16:55.711792 Enter into PICG configuration >>>>
7266 22:16:55.714864 Exit from PICG configuration <<<<
7267 22:16:55.718314 [RX_INPUT] configuration >>>>>
7268 22:16:55.720952 [RX_INPUT] configuration <<<<<
7269 22:16:55.724299 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7270 22:16:55.731754 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7271 22:16:55.737775 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7272 22:16:55.744128 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7273 22:16:55.750350 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7274 22:16:55.754072 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7275 22:16:55.760996 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7276 22:16:55.763873 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7277 22:16:55.767684 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7278 22:16:55.770565 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7279 22:16:55.776682 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7280 22:16:55.780312 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7281 22:16:55.783659 ===================================
7282 22:16:55.786610 LPDDR4 DRAM CONFIGURATION
7283 22:16:55.790572 ===================================
7284 22:16:55.791181 EX_ROW_EN[0] = 0x0
7285 22:16:55.793449 EX_ROW_EN[1] = 0x0
7286 22:16:55.794013 LP4Y_EN = 0x0
7287 22:16:55.796568 WORK_FSP = 0x1
7288 22:16:55.797129 WL = 0x5
7289 22:16:55.800082 RL = 0x5
7290 22:16:55.800597 BL = 0x2
7291 22:16:55.803917 RPST = 0x0
7292 22:16:55.807779 RD_PRE = 0x0
7293 22:16:55.808343 WR_PRE = 0x1
7294 22:16:55.810142 WR_PST = 0x1
7295 22:16:55.810600 DBI_WR = 0x0
7296 22:16:55.813004 DBI_RD = 0x0
7297 22:16:55.813465 OTF = 0x1
7298 22:16:55.817245 ===================================
7299 22:16:55.819585 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7300 22:16:55.826527 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7301 22:16:55.830470 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7302 22:16:55.833200 ===================================
7303 22:16:55.836551 LPDDR4 DRAM CONFIGURATION
7304 22:16:55.839652 ===================================
7305 22:16:55.840120 EX_ROW_EN[0] = 0x10
7306 22:16:55.843223 EX_ROW_EN[1] = 0x0
7307 22:16:55.843803 LP4Y_EN = 0x0
7308 22:16:55.846468 WORK_FSP = 0x1
7309 22:16:55.849553 WL = 0x5
7310 22:16:55.850129 RL = 0x5
7311 22:16:55.852975 BL = 0x2
7312 22:16:55.853537 RPST = 0x0
7313 22:16:55.855866 RD_PRE = 0x0
7314 22:16:55.856323 WR_PRE = 0x1
7315 22:16:55.859486 WR_PST = 0x1
7316 22:16:55.860062 DBI_WR = 0x0
7317 22:16:55.863112 DBI_RD = 0x0
7318 22:16:55.863680 OTF = 0x1
7319 22:16:55.866314 ===================================
7320 22:16:55.872592 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7321 22:16:55.873172 ==
7322 22:16:55.875877 Dram Type= 6, Freq= 0, CH_0, rank 0
7323 22:16:55.879045 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7324 22:16:55.883031 ==
7325 22:16:55.883625 [Duty_Offset_Calibration]
7326 22:16:55.886012 B0:1 B1:-1 CA:0
7327 22:16:55.886576
7328 22:16:55.888914 [DutyScan_Calibration_Flow] k_type=0
7329 22:16:55.898424
7330 22:16:55.899007 ==CLK 0==
7331 22:16:55.901175 Final CLK duty delay cell = 0
7332 22:16:55.904671 [0] MAX Duty = 5156%(X100), DQS PI = 22
7333 22:16:55.908391 [0] MIN Duty = 4907%(X100), DQS PI = 4
7334 22:16:55.908964 [0] AVG Duty = 5031%(X100)
7335 22:16:55.911819
7336 22:16:55.914378 CH0 CLK Duty spec in!! Max-Min= 249%
7337 22:16:55.917819 [DutyScan_Calibration_Flow] ====Done====
7338 22:16:55.918381
7339 22:16:55.920882 [DutyScan_Calibration_Flow] k_type=1
7340 22:16:55.937145
7341 22:16:55.937707 ==DQS 0 ==
7342 22:16:55.940658 Final DQS duty delay cell = -4
7343 22:16:55.943738 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7344 22:16:55.947042 [-4] MIN Duty = 4844%(X100), DQS PI = 48
7345 22:16:55.950650 [-4] AVG Duty = 4922%(X100)
7346 22:16:55.951278
7347 22:16:55.951647 ==DQS 1 ==
7348 22:16:55.953853 Final DQS duty delay cell = 0
7349 22:16:55.956365 [0] MAX Duty = 5187%(X100), DQS PI = 4
7350 22:16:55.959944 [0] MIN Duty = 5031%(X100), DQS PI = 20
7351 22:16:55.963661 [0] AVG Duty = 5109%(X100)
7352 22:16:55.964244
7353 22:16:55.966839 CH0 DQS 0 Duty spec in!! Max-Min= 156%
7354 22:16:55.967348
7355 22:16:55.970170 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7356 22:16:55.972837 [DutyScan_Calibration_Flow] ====Done====
7357 22:16:55.973300
7358 22:16:55.976203 [DutyScan_Calibration_Flow] k_type=3
7359 22:16:55.994530
7360 22:16:55.994980 ==DQM 0 ==
7361 22:16:55.997461 Final DQM duty delay cell = 0
7362 22:16:56.001173 [0] MAX Duty = 5124%(X100), DQS PI = 20
7363 22:16:56.004539 [0] MIN Duty = 4907%(X100), DQS PI = 10
7364 22:16:56.008090 [0] AVG Duty = 5015%(X100)
7365 22:16:56.008626
7366 22:16:56.009017 ==DQM 1 ==
7367 22:16:56.010877 Final DQM duty delay cell = 0
7368 22:16:56.014466 [0] MAX Duty = 5031%(X100), DQS PI = 6
7369 22:16:56.017711 [0] MIN Duty = 4813%(X100), DQS PI = 20
7370 22:16:56.020701 [0] AVG Duty = 4922%(X100)
7371 22:16:56.021243
7372 22:16:56.025505 CH0 DQM 0 Duty spec in!! Max-Min= 217%
7373 22:16:56.025966
7374 22:16:56.027122 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7375 22:16:56.031268 [DutyScan_Calibration_Flow] ====Done====
7376 22:16:56.031713
7377 22:16:56.034774 [DutyScan_Calibration_Flow] k_type=2
7378 22:16:56.050667
7379 22:16:56.051470 ==DQ 0 ==
7380 22:16:56.054660 Final DQ duty delay cell = -4
7381 22:16:56.057289 [-4] MAX Duty = 5031%(X100), DQS PI = 24
7382 22:16:56.060765 [-4] MIN Duty = 4876%(X100), DQS PI = 54
7383 22:16:56.063926 [-4] AVG Duty = 4953%(X100)
7384 22:16:56.064369
7385 22:16:56.064716 ==DQ 1 ==
7386 22:16:56.067279 Final DQ duty delay cell = 0
7387 22:16:56.070870 [0] MAX Duty = 5125%(X100), DQS PI = 2
7388 22:16:56.073835 [0] MIN Duty = 4969%(X100), DQS PI = 38
7389 22:16:56.077306 [0] AVG Duty = 5047%(X100)
7390 22:16:56.077858
7391 22:16:56.080280 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7392 22:16:56.080731
7393 22:16:56.084025 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7394 22:16:56.087590 [DutyScan_Calibration_Flow] ====Done====
7395 22:16:56.088159 ==
7396 22:16:56.089918 Dram Type= 6, Freq= 0, CH_1, rank 0
7397 22:16:56.093939 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7398 22:16:56.094493 ==
7399 22:16:56.097030 [Duty_Offset_Calibration]
7400 22:16:56.097478 B0:-1 B1:1 CA:2
7401 22:16:56.097833
7402 22:16:56.100288 [DutyScan_Calibration_Flow] k_type=0
7403 22:16:56.111599
7404 22:16:56.112168 ==CLK 0==
7405 22:16:56.114631 Final CLK duty delay cell = 0
7406 22:16:56.118996 [0] MAX Duty = 5187%(X100), DQS PI = 24
7407 22:16:56.121578 [0] MIN Duty = 5000%(X100), DQS PI = 0
7408 22:16:56.122134 [0] AVG Duty = 5093%(X100)
7409 22:16:56.124743
7410 22:16:56.127777 CH1 CLK Duty spec in!! Max-Min= 187%
7411 22:16:56.131493 [DutyScan_Calibration_Flow] ====Done====
7412 22:16:56.131936
7413 22:16:56.134088 [DutyScan_Calibration_Flow] k_type=1
7414 22:16:56.151620
7415 22:16:56.152344 ==DQS 0 ==
7416 22:16:56.154602 Final DQS duty delay cell = 0
7417 22:16:56.157755 [0] MAX Duty = 5156%(X100), DQS PI = 20
7418 22:16:56.161532 [0] MIN Duty = 4938%(X100), DQS PI = 10
7419 22:16:56.164181 [0] AVG Duty = 5047%(X100)
7420 22:16:56.164746
7421 22:16:56.165107 ==DQS 1 ==
7422 22:16:56.168021 Final DQS duty delay cell = 0
7423 22:16:56.171165 [0] MAX Duty = 5093%(X100), DQS PI = 26
7424 22:16:56.173867 [0] MIN Duty = 4969%(X100), DQS PI = 54
7425 22:16:56.178011 [0] AVG Duty = 5031%(X100)
7426 22:16:56.178589
7427 22:16:56.180427 CH1 DQS 0 Duty spec in!! Max-Min= 218%
7428 22:16:56.180888
7429 22:16:56.184346 CH1 DQS 1 Duty spec in!! Max-Min= 124%
7430 22:16:56.187451 [DutyScan_Calibration_Flow] ====Done====
7431 22:16:56.188020
7432 22:16:56.190408 [DutyScan_Calibration_Flow] k_type=3
7433 22:16:56.208232
7434 22:16:56.208829 ==DQM 0 ==
7435 22:16:56.211296 Final DQM duty delay cell = 0
7436 22:16:56.214359 [0] MAX Duty = 5218%(X100), DQS PI = 18
7437 22:16:56.218157 [0] MIN Duty = 5031%(X100), DQS PI = 8
7438 22:16:56.221289 [0] AVG Duty = 5124%(X100)
7439 22:16:56.221755
7440 22:16:56.222110 ==DQM 1 ==
7441 22:16:56.225260 Final DQM duty delay cell = 0
7442 22:16:56.227895 [0] MAX Duty = 5156%(X100), DQS PI = 4
7443 22:16:56.231139 [0] MIN Duty = 4969%(X100), DQS PI = 34
7444 22:16:56.231619 [0] AVG Duty = 5062%(X100)
7445 22:16:56.234544
7446 22:16:56.237889 CH1 DQM 0 Duty spec in!! Max-Min= 187%
7447 22:16:56.238346
7448 22:16:56.241758 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7449 22:16:56.244935 [DutyScan_Calibration_Flow] ====Done====
7450 22:16:56.245484
7451 22:16:56.247617 [DutyScan_Calibration_Flow] k_type=2
7452 22:16:56.265096
7453 22:16:56.265645 ==DQ 0 ==
7454 22:16:56.267966 Final DQ duty delay cell = 0
7455 22:16:56.271442 [0] MAX Duty = 5156%(X100), DQS PI = 30
7456 22:16:56.275214 [0] MIN Duty = 4906%(X100), DQS PI = 10
7457 22:16:56.275763 [0] AVG Duty = 5031%(X100)
7458 22:16:56.278053
7459 22:16:56.278623 ==DQ 1 ==
7460 22:16:56.280913 Final DQ duty delay cell = 0
7461 22:16:56.284295 [0] MAX Duty = 5156%(X100), DQS PI = 8
7462 22:16:56.287788 [0] MIN Duty = 4969%(X100), DQS PI = 56
7463 22:16:56.288361 [0] AVG Duty = 5062%(X100)
7464 22:16:56.291150
7465 22:16:56.294351 CH1 DQ 0 Duty spec in!! Max-Min= 250%
7466 22:16:56.294901
7467 22:16:56.297799 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7468 22:16:56.301003 [DutyScan_Calibration_Flow] ====Done====
7469 22:16:56.304571 nWR fixed to 30
7470 22:16:56.308615 [ModeRegInit_LP4] CH0 RK0
7471 22:16:56.309343 [ModeRegInit_LP4] CH0 RK1
7472 22:16:56.310926 [ModeRegInit_LP4] CH1 RK0
7473 22:16:56.313958 [ModeRegInit_LP4] CH1 RK1
7474 22:16:56.314508 match AC timing 5
7475 22:16:56.320990 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7476 22:16:56.324000 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7477 22:16:56.327340 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7478 22:16:56.334169 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7479 22:16:56.336859 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7480 22:16:56.337320 [MiockJmeterHQA]
7481 22:16:56.337680
7482 22:16:56.341241 [DramcMiockJmeter] u1RxGatingPI = 0
7483 22:16:56.344204 0 : 4257, 4029
7484 22:16:56.344764 4 : 4252, 4027
7485 22:16:56.347614 8 : 4253, 4027
7486 22:16:56.348076 12 : 4252, 4027
7487 22:16:56.350973 16 : 4253, 4027
7488 22:16:56.351575 20 : 4253, 4026
7489 22:16:56.352036 24 : 4363, 4138
7490 22:16:56.353550 28 : 4363, 4137
7491 22:16:56.354014 32 : 4253, 4026
7492 22:16:56.356961 36 : 4253, 4026
7493 22:16:56.357422 40 : 4250, 4027
7494 22:16:56.360739 44 : 4361, 4137
7495 22:16:56.361314 48 : 4250, 4026
7496 22:16:56.363568 52 : 4360, 4138
7497 22:16:56.364030 56 : 4252, 4026
7498 22:16:56.364394 60 : 4250, 4027
7499 22:16:56.366981 64 : 4250, 4027
7500 22:16:56.367572 68 : 4250, 4026
7501 22:16:56.370394 72 : 4360, 4138
7502 22:16:56.370955 76 : 4250, 4027
7503 22:16:56.373793 80 : 4361, 4137
7504 22:16:56.374358 84 : 4250, 4026
7505 22:16:56.376805 88 : 4250, 4026
7506 22:16:56.377268 92 : 4250, 396
7507 22:16:56.377629 96 : 4249, 0
7508 22:16:56.380535 100 : 4250, 0
7509 22:16:56.380999 104 : 4250, 0
7510 22:16:56.381360 108 : 4250, 0
7511 22:16:56.383536 112 : 4250, 0
7512 22:16:56.383996 116 : 4360, 0
7513 22:16:56.386832 120 : 4360, 0
7514 22:16:56.387328 124 : 4250, 0
7515 22:16:56.387692 128 : 4253, 0
7516 22:16:56.390752 132 : 4250, 0
7517 22:16:56.391370 136 : 4250, 0
7518 22:16:56.392939 140 : 4250, 0
7519 22:16:56.393405 144 : 4249, 0
7520 22:16:56.393787 148 : 4252, 0
7521 22:16:56.396403 152 : 4250, 0
7522 22:16:56.396863 156 : 4250, 0
7523 22:16:56.400150 160 : 4252, 0
7524 22:16:56.400611 164 : 4361, 0
7525 22:16:56.400976 168 : 4361, 0
7526 22:16:56.403443 172 : 4363, 0
7527 22:16:56.403898 176 : 4250, 0
7528 22:16:56.406418 180 : 4250, 0
7529 22:16:56.406836 184 : 4250, 0
7530 22:16:56.407193 188 : 4250, 0
7531 22:16:56.409722 192 : 4250, 0
7532 22:16:56.410239 196 : 4249, 0
7533 22:16:56.413404 200 : 4252, 0
7534 22:16:56.413923 204 : 4361, 0
7535 22:16:56.414259 208 : 4249, 0
7536 22:16:56.416818 212 : 4250, 0
7537 22:16:56.417237 216 : 4361, 0
7538 22:16:56.417564 220 : 4360, 0
7539 22:16:56.419633 224 : 4363, 330
7540 22:16:56.420051 228 : 4250, 3608
7541 22:16:56.422873 232 : 4360, 4138
7542 22:16:56.423321 236 : 4249, 4027
7543 22:16:56.426237 240 : 4250, 4026
7544 22:16:56.426653 244 : 4360, 4138
7545 22:16:56.429415 248 : 4361, 4137
7546 22:16:56.429836 252 : 4248, 4024
7547 22:16:56.432947 256 : 4361, 4137
7548 22:16:56.433470 260 : 4360, 4138
7549 22:16:56.435716 264 : 4250, 4027
7550 22:16:56.436133 268 : 4250, 4027
7551 22:16:56.439802 272 : 4250, 4026
7552 22:16:56.440316 276 : 4250, 4027
7553 22:16:56.443003 280 : 4250, 4027
7554 22:16:56.443486 284 : 4250, 4027
7555 22:16:56.443823 288 : 4250, 4026
7556 22:16:56.446222 292 : 4250, 4027
7557 22:16:56.446756 296 : 4360, 4138
7558 22:16:56.449355 300 : 4361, 4137
7559 22:16:56.449863 304 : 4250, 4026
7560 22:16:56.452409 308 : 4361, 4137
7561 22:16:56.452823 312 : 4360, 4138
7562 22:16:56.456009 316 : 4250, 4027
7563 22:16:56.456422 320 : 4250, 4027
7564 22:16:56.459377 324 : 4250, 4026
7565 22:16:56.459927 328 : 4250, 4027
7566 22:16:56.462236 332 : 4250, 4026
7567 22:16:56.462694 336 : 4250, 3656
7568 22:16:56.466152 340 : 4250, 2089
7569 22:16:56.466746
7570 22:16:56.467163 MIOCK jitter meter ch=0
7571 22:16:56.467621
7572 22:16:56.469460 1T = (340-92) = 248 dly cells
7573 22:16:56.475979 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 262/100 ps
7574 22:16:56.476570 ==
7575 22:16:56.479284 Dram Type= 6, Freq= 0, CH_0, rank 0
7576 22:16:56.481979 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7577 22:16:56.482436 ==
7578 22:16:56.488848 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7579 22:16:56.491854 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7580 22:16:56.495354 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7581 22:16:56.501787 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7582 22:16:56.512028 [CA 0] Center 43 (13~74) winsize 62
7583 22:16:56.515559 [CA 1] Center 43 (13~73) winsize 61
7584 22:16:56.518604 [CA 2] Center 38 (9~68) winsize 60
7585 22:16:56.521678 [CA 3] Center 38 (8~68) winsize 61
7586 22:16:56.524873 [CA 4] Center 36 (7~66) winsize 60
7587 22:16:56.528874 [CA 5] Center 35 (6~65) winsize 60
7588 22:16:56.529326
7589 22:16:56.531214 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7590 22:16:56.531664
7591 22:16:56.538655 [CATrainingPosCal] consider 1 rank data
7592 22:16:56.539247 u2DelayCellTimex100 = 262/100 ps
7593 22:16:56.545009 CA0 delay=43 (13~74),Diff = 8 PI (29 cell)
7594 22:16:56.547699 CA1 delay=43 (13~73),Diff = 8 PI (29 cell)
7595 22:16:56.551149 CA2 delay=38 (9~68),Diff = 3 PI (11 cell)
7596 22:16:56.554934 CA3 delay=38 (8~68),Diff = 3 PI (11 cell)
7597 22:16:56.558131 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7598 22:16:56.561261 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7599 22:16:56.561817
7600 22:16:56.564681 CA PerBit enable=1, Macro0, CA PI delay=35
7601 22:16:56.565242
7602 22:16:56.567957 [CBTSetCACLKResult] CA Dly = 35
7603 22:16:56.571157 CS Dly: 12 (0~43)
7604 22:16:56.574769 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7605 22:16:56.577857 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7606 22:16:56.578409 ==
7607 22:16:56.581460 Dram Type= 6, Freq= 0, CH_0, rank 1
7608 22:16:56.587673 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7609 22:16:56.588227 ==
7610 22:16:56.591005 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7611 22:16:56.597331 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7612 22:16:56.601039 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7613 22:16:56.607828 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7614 22:16:56.615328 [CA 0] Center 43 (13~74) winsize 62
7615 22:16:56.618842 [CA 1] Center 44 (14~74) winsize 61
7616 22:16:56.622332 [CA 2] Center 38 (9~68) winsize 60
7617 22:16:56.625655 [CA 3] Center 38 (9~68) winsize 60
7618 22:16:56.628445 [CA 4] Center 36 (7~66) winsize 60
7619 22:16:56.631739 [CA 5] Center 36 (6~66) winsize 61
7620 22:16:56.632196
7621 22:16:56.634617 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7622 22:16:56.635184
7623 22:16:56.641984 [CATrainingPosCal] consider 2 rank data
7624 22:16:56.642543 u2DelayCellTimex100 = 262/100 ps
7625 22:16:56.649080 CA0 delay=43 (13~74),Diff = 8 PI (29 cell)
7626 22:16:56.651310 CA1 delay=43 (14~73),Diff = 8 PI (29 cell)
7627 22:16:56.655619 CA2 delay=38 (9~68),Diff = 3 PI (11 cell)
7628 22:16:56.658125 CA3 delay=38 (9~68),Diff = 3 PI (11 cell)
7629 22:16:56.661335 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7630 22:16:56.664961 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7631 22:16:56.665515
7632 22:16:56.668030 CA PerBit enable=1, Macro0, CA PI delay=35
7633 22:16:56.668508
7634 22:16:56.671442 [CBTSetCACLKResult] CA Dly = 35
7635 22:16:56.674715 CS Dly: 12 (0~44)
7636 22:16:56.678160 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7637 22:16:56.681230 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7638 22:16:56.681807
7639 22:16:56.684715 ----->DramcWriteLeveling(PI) begin...
7640 22:16:56.685176 ==
7641 22:16:56.687962 Dram Type= 6, Freq= 0, CH_0, rank 0
7642 22:16:56.694638 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7643 22:16:56.695236 ==
7644 22:16:56.698424 Write leveling (Byte 0): 35 => 35
7645 22:16:56.701916 Write leveling (Byte 1): 26 => 26
7646 22:16:56.702375 DramcWriteLeveling(PI) end<-----
7647 22:16:56.705035
7648 22:16:56.705586 ==
7649 22:16:56.708695 Dram Type= 6, Freq= 0, CH_0, rank 0
7650 22:16:56.711810 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7651 22:16:56.712367 ==
7652 22:16:56.714742 [Gating] SW mode calibration
7653 22:16:56.720961 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7654 22:16:56.724408 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7655 22:16:56.730623 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7656 22:16:56.734755 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7657 22:16:56.737580 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7658 22:16:56.743955 1 4 12 | B1->B0 | 2323 2929 | 0 1 | (0 0) (1 1)
7659 22:16:56.748021 1 4 16 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
7660 22:16:56.750976 1 4 20 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7661 22:16:56.757465 1 4 24 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
7662 22:16:56.761101 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7663 22:16:56.764389 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7664 22:16:56.770853 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7665 22:16:56.774500 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7666 22:16:56.777502 1 5 12 | B1->B0 | 3434 2c2c | 1 1 | (1 1) (1 0)
7667 22:16:56.784298 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7668 22:16:56.787138 1 5 20 | B1->B0 | 3434 2323 | 0 0 | (1 0) (0 0)
7669 22:16:56.790528 1 5 24 | B1->B0 | 2828 2323 | 0 0 | (1 0) (0 0)
7670 22:16:56.797296 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7671 22:16:56.800076 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7672 22:16:56.804129 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7673 22:16:56.810773 1 6 8 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
7674 22:16:56.813728 1 6 12 | B1->B0 | 2323 3b3b | 0 0 | (0 0) (0 0)
7675 22:16:56.816982 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7676 22:16:56.823881 1 6 20 | B1->B0 | 2a29 4646 | 1 0 | (1 1) (0 0)
7677 22:16:56.826696 1 6 24 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
7678 22:16:56.829908 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7679 22:16:56.836964 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7680 22:16:56.839748 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7681 22:16:56.842978 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7682 22:16:56.849972 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7683 22:16:56.853267 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7684 22:16:56.856237 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7685 22:16:56.863178 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7686 22:16:56.866439 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7687 22:16:56.869673 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7688 22:16:56.876311 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7689 22:16:56.879467 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7690 22:16:56.882650 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7691 22:16:56.889503 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7692 22:16:56.893108 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7693 22:16:56.896305 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7694 22:16:56.902967 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7695 22:16:56.905923 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7696 22:16:56.909338 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7697 22:16:56.915940 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7698 22:16:56.919500 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7699 22:16:56.923111 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7700 22:16:56.926322 Total UI for P1: 0, mck2ui 16
7701 22:16:56.929336 best dqsien dly found for B0: ( 1, 9, 10)
7702 22:16:56.935660 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7703 22:16:56.939275 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7704 22:16:56.942357 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7705 22:16:56.945877 Total UI for P1: 0, mck2ui 16
7706 22:16:56.949104 best dqsien dly found for B1: ( 1, 9, 22)
7707 22:16:56.952167 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7708 22:16:56.955829 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7709 22:16:56.956519
7710 22:16:56.962475 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7711 22:16:56.965599 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7712 22:16:56.969156 [Gating] SW calibration Done
7713 22:16:56.969746 ==
7714 22:16:56.972033 Dram Type= 6, Freq= 0, CH_0, rank 0
7715 22:16:56.975625 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7716 22:16:56.976188 ==
7717 22:16:56.976549 RX Vref Scan: 0
7718 22:16:56.978643
7719 22:16:56.979135 RX Vref 0 -> 0, step: 1
7720 22:16:56.979506
7721 22:16:56.982029 RX Delay 0 -> 252, step: 8
7722 22:16:56.984935 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7723 22:16:56.988288 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7724 22:16:56.994749 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7725 22:16:56.998793 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7726 22:16:57.001540 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7727 22:16:57.004923 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7728 22:16:57.007822 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7729 22:16:57.015201 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7730 22:16:57.017904 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7731 22:16:57.021765 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7732 22:16:57.025351 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
7733 22:16:57.031037 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7734 22:16:57.034113 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7735 22:16:57.037688 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7736 22:16:57.041133 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7737 22:16:57.044072 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7738 22:16:57.047709 ==
7739 22:16:57.051006 Dram Type= 6, Freq= 0, CH_0, rank 0
7740 22:16:57.053892 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7741 22:16:57.054464 ==
7742 22:16:57.054825 DQS Delay:
7743 22:16:57.057149 DQS0 = 0, DQS1 = 0
7744 22:16:57.057649 DQM Delay:
7745 22:16:57.060811 DQM0 = 136, DQM1 = 127
7746 22:16:57.061374 DQ Delay:
7747 22:16:57.063929 DQ0 =135, DQ1 =139, DQ2 =131, DQ3 =131
7748 22:16:57.067350 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =147
7749 22:16:57.070259 DQ8 =119, DQ9 =115, DQ10 =127, DQ11 =119
7750 22:16:57.074273 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =135
7751 22:16:57.074861
7752 22:16:57.075293
7753 22:16:57.076930 ==
7754 22:16:57.079932 Dram Type= 6, Freq= 0, CH_0, rank 0
7755 22:16:57.083784 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7756 22:16:57.084251 ==
7757 22:16:57.084614
7758 22:16:57.084946
7759 22:16:57.086801 TX Vref Scan disable
7760 22:16:57.087419 == TX Byte 0 ==
7761 22:16:57.093236 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7762 22:16:57.096849 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7763 22:16:57.097313 == TX Byte 1 ==
7764 22:16:57.103271 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7765 22:16:57.106693 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7766 22:16:57.107295 ==
7767 22:16:57.110116 Dram Type= 6, Freq= 0, CH_0, rank 0
7768 22:16:57.113152 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7769 22:16:57.113750 ==
7770 22:16:57.126505
7771 22:16:57.129062 TX Vref early break, caculate TX vref
7772 22:16:57.132824 TX Vref=16, minBit 1, minWin=22, winSum=371
7773 22:16:57.135803 TX Vref=18, minBit 1, minWin=23, winSum=376
7774 22:16:57.139650 TX Vref=20, minBit 0, minWin=23, winSum=387
7775 22:16:57.142648 TX Vref=22, minBit 3, minWin=24, winSum=399
7776 22:16:57.146783 TX Vref=24, minBit 0, minWin=25, winSum=410
7777 22:16:57.152653 TX Vref=26, minBit 4, minWin=24, winSum=410
7778 22:16:57.155624 TX Vref=28, minBit 0, minWin=25, winSum=417
7779 22:16:57.159168 TX Vref=30, minBit 0, minWin=24, winSum=404
7780 22:16:57.162464 TX Vref=32, minBit 0, minWin=24, winSum=395
7781 22:16:57.169494 [TxChooseVref] Worse bit 0, Min win 25, Win sum 417, Final Vref 28
7782 22:16:57.170077
7783 22:16:57.172677 Final TX Range 0 Vref 28
7784 22:16:57.173243
7785 22:16:57.173606 ==
7786 22:16:57.175500 Dram Type= 6, Freq= 0, CH_0, rank 0
7787 22:16:57.179136 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7788 22:16:57.179724 ==
7789 22:16:57.180095
7790 22:16:57.180429
7791 22:16:57.181866 TX Vref Scan disable
7792 22:16:57.188703 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
7793 22:16:57.189256 == TX Byte 0 ==
7794 22:16:57.191868 u2DelayCellOfst[0]=18 cells (5 PI)
7795 22:16:57.195631 u2DelayCellOfst[1]=18 cells (5 PI)
7796 22:16:57.198456 u2DelayCellOfst[2]=14 cells (4 PI)
7797 22:16:57.201489 u2DelayCellOfst[3]=14 cells (4 PI)
7798 22:16:57.205301 u2DelayCellOfst[4]=11 cells (3 PI)
7799 22:16:57.208279 u2DelayCellOfst[5]=0 cells (0 PI)
7800 22:16:57.211612 u2DelayCellOfst[6]=18 cells (5 PI)
7801 22:16:57.215268 u2DelayCellOfst[7]=22 cells (6 PI)
7802 22:16:57.218264 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
7803 22:16:57.222089 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7804 22:16:57.225254 == TX Byte 1 ==
7805 22:16:57.225715 u2DelayCellOfst[8]=0 cells (0 PI)
7806 22:16:57.228396 u2DelayCellOfst[9]=3 cells (1 PI)
7807 22:16:57.231703 u2DelayCellOfst[10]=7 cells (2 PI)
7808 22:16:57.235728 u2DelayCellOfst[11]=3 cells (1 PI)
7809 22:16:57.238521 u2DelayCellOfst[12]=14 cells (4 PI)
7810 22:16:57.241938 u2DelayCellOfst[13]=14 cells (4 PI)
7811 22:16:57.244729 u2DelayCellOfst[14]=14 cells (4 PI)
7812 22:16:57.248814 u2DelayCellOfst[15]=14 cells (4 PI)
7813 22:16:57.251743 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7814 22:16:57.257924 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7815 22:16:57.258381 DramC Write-DBI on
7816 22:16:57.258737 ==
7817 22:16:57.261902 Dram Type= 6, Freq= 0, CH_0, rank 0
7818 22:16:57.267908 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7819 22:16:57.268450 ==
7820 22:16:57.268805
7821 22:16:57.269159
7822 22:16:57.269474 TX Vref Scan disable
7823 22:16:57.272235 == TX Byte 0 ==
7824 22:16:57.275601 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7825 22:16:57.278811 == TX Byte 1 ==
7826 22:16:57.281990 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
7827 22:16:57.284960 DramC Write-DBI off
7828 22:16:57.285409
7829 22:16:57.285762 [DATLAT]
7830 22:16:57.286091 Freq=1600, CH0 RK0
7831 22:16:57.286411
7832 22:16:57.288591 DATLAT Default: 0xf
7833 22:16:57.289038 0, 0xFFFF, sum = 0
7834 22:16:57.291591 1, 0xFFFF, sum = 0
7835 22:16:57.295299 2, 0xFFFF, sum = 0
7836 22:16:57.295858 3, 0xFFFF, sum = 0
7837 22:16:57.298733 4, 0xFFFF, sum = 0
7838 22:16:57.299346 5, 0xFFFF, sum = 0
7839 22:16:57.301389 6, 0xFFFF, sum = 0
7840 22:16:57.301850 7, 0xFFFF, sum = 0
7841 22:16:57.305120 8, 0xFFFF, sum = 0
7842 22:16:57.305726 9, 0xFFFF, sum = 0
7843 22:16:57.307854 10, 0xFFFF, sum = 0
7844 22:16:57.308320 11, 0xFFFF, sum = 0
7845 22:16:57.311464 12, 0xFFFF, sum = 0
7846 22:16:57.312030 13, 0xFFFF, sum = 0
7847 22:16:57.314899 14, 0x0, sum = 1
7848 22:16:57.315504 15, 0x0, sum = 2
7849 22:16:57.318211 16, 0x0, sum = 3
7850 22:16:57.318775 17, 0x0, sum = 4
7851 22:16:57.321483 best_step = 15
7852 22:16:57.322039
7853 22:16:57.322399 ==
7854 22:16:57.324989 Dram Type= 6, Freq= 0, CH_0, rank 0
7855 22:16:57.327907 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7856 22:16:57.328370 ==
7857 22:16:57.331389 RX Vref Scan: 1
7858 22:16:57.331851
7859 22:16:57.332209 Set Vref Range= 24 -> 127
7860 22:16:57.332543
7861 22:16:57.334986 RX Vref 24 -> 127, step: 1
7862 22:16:57.335483
7863 22:16:57.338025 RX Delay 19 -> 252, step: 4
7864 22:16:57.338588
7865 22:16:57.341556 Set Vref, RX VrefLevel [Byte0]: 24
7866 22:16:57.344859 [Byte1]: 24
7867 22:16:57.345423
7868 22:16:57.348246 Set Vref, RX VrefLevel [Byte0]: 25
7869 22:16:57.351223 [Byte1]: 25
7870 22:16:57.354544
7871 22:16:57.355150 Set Vref, RX VrefLevel [Byte0]: 26
7872 22:16:57.358070 [Byte1]: 26
7873 22:16:57.362217
7874 22:16:57.362792 Set Vref, RX VrefLevel [Byte0]: 27
7875 22:16:57.365738 [Byte1]: 27
7876 22:16:57.369274
7877 22:16:57.369734 Set Vref, RX VrefLevel [Byte0]: 28
7878 22:16:57.372968 [Byte1]: 28
7879 22:16:57.377509
7880 22:16:57.378073 Set Vref, RX VrefLevel [Byte0]: 29
7881 22:16:57.380348 [Byte1]: 29
7882 22:16:57.385189
7883 22:16:57.385746 Set Vref, RX VrefLevel [Byte0]: 30
7884 22:16:57.391588 [Byte1]: 30
7885 22:16:57.392049
7886 22:16:57.394758 Set Vref, RX VrefLevel [Byte0]: 31
7887 22:16:57.398591 [Byte1]: 31
7888 22:16:57.399200
7889 22:16:57.401038 Set Vref, RX VrefLevel [Byte0]: 32
7890 22:16:57.404598 [Byte1]: 32
7891 22:16:57.407657
7892 22:16:57.408115 Set Vref, RX VrefLevel [Byte0]: 33
7893 22:16:57.410766 [Byte1]: 33
7894 22:16:57.415134
7895 22:16:57.415709 Set Vref, RX VrefLevel [Byte0]: 34
7896 22:16:57.418391 [Byte1]: 34
7897 22:16:57.422668
7898 22:16:57.423239 Set Vref, RX VrefLevel [Byte0]: 35
7899 22:16:57.425821 [Byte1]: 35
7900 22:16:57.430049
7901 22:16:57.430619 Set Vref, RX VrefLevel [Byte0]: 36
7902 22:16:57.433540 [Byte1]: 36
7903 22:16:57.438019
7904 22:16:57.438592 Set Vref, RX VrefLevel [Byte0]: 37
7905 22:16:57.441274 [Byte1]: 37
7906 22:16:57.446034
7907 22:16:57.446595 Set Vref, RX VrefLevel [Byte0]: 38
7908 22:16:57.448451 [Byte1]: 38
7909 22:16:57.453131
7910 22:16:57.453707 Set Vref, RX VrefLevel [Byte0]: 39
7911 22:16:57.456020 [Byte1]: 39
7912 22:16:57.460732
7913 22:16:57.461289 Set Vref, RX VrefLevel [Byte0]: 40
7914 22:16:57.464496 [Byte1]: 40
7915 22:16:57.468146
7916 22:16:57.468766 Set Vref, RX VrefLevel [Byte0]: 41
7917 22:16:57.471051 [Byte1]: 41
7918 22:16:57.475564
7919 22:16:57.476122 Set Vref, RX VrefLevel [Byte0]: 42
7920 22:16:57.478956 [Byte1]: 42
7921 22:16:57.483373
7922 22:16:57.483938 Set Vref, RX VrefLevel [Byte0]: 43
7923 22:16:57.486774 [Byte1]: 43
7924 22:16:57.491442
7925 22:16:57.492010 Set Vref, RX VrefLevel [Byte0]: 44
7926 22:16:57.493946 [Byte1]: 44
7927 22:16:57.498379
7928 22:16:57.498982 Set Vref, RX VrefLevel [Byte0]: 45
7929 22:16:57.502149 [Byte1]: 45
7930 22:16:57.506207
7931 22:16:57.506772 Set Vref, RX VrefLevel [Byte0]: 46
7932 22:16:57.509086 [Byte1]: 46
7933 22:16:57.513358
7934 22:16:57.513915 Set Vref, RX VrefLevel [Byte0]: 47
7935 22:16:57.517461 [Byte1]: 47
7936 22:16:57.521117
7937 22:16:57.521678 Set Vref, RX VrefLevel [Byte0]: 48
7938 22:16:57.524226 [Byte1]: 48
7939 22:16:57.528697
7940 22:16:57.529267 Set Vref, RX VrefLevel [Byte0]: 49
7941 22:16:57.531640 [Byte1]: 49
7942 22:16:57.535929
7943 22:16:57.536386 Set Vref, RX VrefLevel [Byte0]: 50
7944 22:16:57.539496 [Byte1]: 50
7945 22:16:57.543870
7946 22:16:57.544328 Set Vref, RX VrefLevel [Byte0]: 51
7947 22:16:57.547171 [Byte1]: 51
7948 22:16:57.551432
7949 22:16:57.551918 Set Vref, RX VrefLevel [Byte0]: 52
7950 22:16:57.554489 [Byte1]: 52
7951 22:16:57.559273
7952 22:16:57.559840 Set Vref, RX VrefLevel [Byte0]: 53
7953 22:16:57.562537 [Byte1]: 53
7954 22:16:57.566557
7955 22:16:57.567141 Set Vref, RX VrefLevel [Byte0]: 54
7956 22:16:57.570228 [Byte1]: 54
7957 22:16:57.574434
7958 22:16:57.574982 Set Vref, RX VrefLevel [Byte0]: 55
7959 22:16:57.577418 [Byte1]: 55
7960 22:16:57.582191
7961 22:16:57.582746 Set Vref, RX VrefLevel [Byte0]: 56
7962 22:16:57.585121 [Byte1]: 56
7963 22:16:57.588923
7964 22:16:57.589403 Set Vref, RX VrefLevel [Byte0]: 57
7965 22:16:57.592469 [Byte1]: 57
7966 22:16:57.596687
7967 22:16:57.597143 Set Vref, RX VrefLevel [Byte0]: 58
7968 22:16:57.600336 [Byte1]: 58
7969 22:16:57.604507
7970 22:16:57.605057 Set Vref, RX VrefLevel [Byte0]: 59
7971 22:16:57.608041 [Byte1]: 59
7972 22:16:57.612433
7973 22:16:57.612983 Set Vref, RX VrefLevel [Byte0]: 60
7974 22:16:57.615161 [Byte1]: 60
7975 22:16:57.619629
7976 22:16:57.620186 Set Vref, RX VrefLevel [Byte0]: 61
7977 22:16:57.622657 [Byte1]: 61
7978 22:16:57.627046
7979 22:16:57.627535 Set Vref, RX VrefLevel [Byte0]: 62
7980 22:16:57.630395 [Byte1]: 62
7981 22:16:57.634983
7982 22:16:57.635469 Set Vref, RX VrefLevel [Byte0]: 63
7983 22:16:57.638109 [Byte1]: 63
7984 22:16:57.642432
7985 22:16:57.642987 Set Vref, RX VrefLevel [Byte0]: 64
7986 22:16:57.646105 [Byte1]: 64
7987 22:16:57.650078
7988 22:16:57.650629 Set Vref, RX VrefLevel [Byte0]: 65
7989 22:16:57.653522 [Byte1]: 65
7990 22:16:57.657749
7991 22:16:57.658296 Set Vref, RX VrefLevel [Byte0]: 66
7992 22:16:57.660783 [Byte1]: 66
7993 22:16:57.665375
7994 22:16:57.665925 Set Vref, RX VrefLevel [Byte0]: 67
7995 22:16:57.668290 [Byte1]: 67
7996 22:16:57.672593
7997 22:16:57.673144 Set Vref, RX VrefLevel [Byte0]: 68
7998 22:16:57.676008 [Byte1]: 68
7999 22:16:57.680459
8000 22:16:57.680908 Set Vref, RX VrefLevel [Byte0]: 69
8001 22:16:57.683589 [Byte1]: 69
8002 22:16:57.687480
8003 22:16:57.688025 Set Vref, RX VrefLevel [Byte0]: 70
8004 22:16:57.691466 [Byte1]: 70
8005 22:16:57.695452
8006 22:16:57.696037 Set Vref, RX VrefLevel [Byte0]: 71
8007 22:16:57.698271 [Byte1]: 71
8008 22:16:57.703528
8009 22:16:57.704092 Set Vref, RX VrefLevel [Byte0]: 72
8010 22:16:57.706260 [Byte1]: 72
8011 22:16:57.710983
8012 22:16:57.711584 Set Vref, RX VrefLevel [Byte0]: 73
8013 22:16:57.714036 [Byte1]: 73
8014 22:16:57.718250
8015 22:16:57.721103 Set Vref, RX VrefLevel [Byte0]: 74
8016 22:16:57.724864 [Byte1]: 74
8017 22:16:57.725422
8018 22:16:57.727558 Set Vref, RX VrefLevel [Byte0]: 75
8019 22:16:57.730989 [Byte1]: 75
8020 22:16:57.731492
8021 22:16:57.734265 Set Vref, RX VrefLevel [Byte0]: 76
8022 22:16:57.738193 [Byte1]: 76
8023 22:16:57.738753
8024 22:16:57.740881 Set Vref, RX VrefLevel [Byte0]: 77
8025 22:16:57.744223 [Byte1]: 77
8026 22:16:57.748333
8027 22:16:57.748885 Set Vref, RX VrefLevel [Byte0]: 78
8028 22:16:57.752824 [Byte1]: 78
8029 22:16:57.755464
8030 22:16:57.755916 Set Vref, RX VrefLevel [Byte0]: 79
8031 22:16:57.758895 [Byte1]: 79
8032 22:16:57.764080
8033 22:16:57.764637 Set Vref, RX VrefLevel [Byte0]: 80
8034 22:16:57.766664 [Byte1]: 80
8035 22:16:57.771315
8036 22:16:57.771900 Final RX Vref Byte 0 = 65 to rank0
8037 22:16:57.774774 Final RX Vref Byte 1 = 60 to rank0
8038 22:16:57.778020 Final RX Vref Byte 0 = 65 to rank1
8039 22:16:57.780984 Final RX Vref Byte 1 = 60 to rank1==
8040 22:16:57.783767 Dram Type= 6, Freq= 0, CH_0, rank 0
8041 22:16:57.790638 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8042 22:16:57.791249 ==
8043 22:16:57.791613 DQS Delay:
8044 22:16:57.794254 DQS0 = 0, DQS1 = 0
8045 22:16:57.794814 DQM Delay:
8046 22:16:57.797195 DQM0 = 133, DQM1 = 123
8047 22:16:57.797653 DQ Delay:
8048 22:16:57.801117 DQ0 =130, DQ1 =136, DQ2 =132, DQ3 =132
8049 22:16:57.803630 DQ4 =134, DQ5 =122, DQ6 =140, DQ7 =142
8050 22:16:57.807229 DQ8 =114, DQ9 =112, DQ10 =124, DQ11 =118
8051 22:16:57.810848 DQ12 =128, DQ13 =126, DQ14 =134, DQ15 =128
8052 22:16:57.811460
8053 22:16:57.811823
8054 22:16:57.812258
8055 22:16:57.813493 [DramC_TX_OE_Calibration] TA2
8056 22:16:57.816876 Original DQ_B0 (3 6) =30, OEN = 27
8057 22:16:57.820096 Original DQ_B1 (3 6) =30, OEN = 27
8058 22:16:57.823777 24, 0x0, End_B0=24 End_B1=24
8059 22:16:57.827226 25, 0x0, End_B0=25 End_B1=25
8060 22:16:57.827788 26, 0x0, End_B0=26 End_B1=26
8061 22:16:57.830154 27, 0x0, End_B0=27 End_B1=27
8062 22:16:57.833380 28, 0x0, End_B0=28 End_B1=28
8063 22:16:57.836929 29, 0x0, End_B0=29 End_B1=29
8064 22:16:57.837402 30, 0x0, End_B0=30 End_B1=30
8065 22:16:57.839893 31, 0x4141, End_B0=30 End_B1=30
8066 22:16:57.843509 Byte0 end_step=30 best_step=27
8067 22:16:57.846473 Byte1 end_step=30 best_step=27
8068 22:16:57.850042 Byte0 TX OE(2T, 0.5T) = (3, 3)
8069 22:16:57.853680 Byte1 TX OE(2T, 0.5T) = (3, 3)
8070 22:16:57.854245
8071 22:16:57.854609
8072 22:16:57.860204 [DQSOSCAuto] RK0, (LSB)MR18= 0x2415, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 391 ps
8073 22:16:57.863097 CH0 RK0: MR19=303, MR18=2415
8074 22:16:57.869374 CH0_RK0: MR19=0x303, MR18=0x2415, DQSOSC=391, MR23=63, INC=24, DEC=16
8075 22:16:57.869853
8076 22:16:57.873030 ----->DramcWriteLeveling(PI) begin...
8077 22:16:57.873496 ==
8078 22:16:57.875926 Dram Type= 6, Freq= 0, CH_0, rank 1
8079 22:16:57.880269 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8080 22:16:57.880730 ==
8081 22:16:57.882872 Write leveling (Byte 0): 36 => 36
8082 22:16:57.886001 Write leveling (Byte 1): 28 => 28
8083 22:16:57.889836 DramcWriteLeveling(PI) end<-----
8084 22:16:57.890465
8085 22:16:57.890843 ==
8086 22:16:57.892422 Dram Type= 6, Freq= 0, CH_0, rank 1
8087 22:16:57.899727 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8088 22:16:57.900304 ==
8089 22:16:57.900670 [Gating] SW mode calibration
8090 22:16:57.909641 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8091 22:16:57.912395 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8092 22:16:57.919416 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8093 22:16:57.922644 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8094 22:16:57.925765 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8095 22:16:57.932493 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8096 22:16:57.935755 1 4 16 | B1->B0 | 2322 3434 | 1 0 | (0 0) (0 0)
8097 22:16:57.938914 1 4 20 | B1->B0 | 2a2a 3434 | 0 1 | (0 0) (1 1)
8098 22:16:57.942286 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8099 22:16:57.948936 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8100 22:16:57.952467 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8101 22:16:57.955638 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8102 22:16:57.961851 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8103 22:16:57.965580 1 5 12 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
8104 22:16:57.969131 1 5 16 | B1->B0 | 3434 2929 | 1 0 | (1 0) (0 0)
8105 22:16:57.975478 1 5 20 | B1->B0 | 2b2b 2323 | 1 0 | (1 0) (0 0)
8106 22:16:57.978707 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8107 22:16:57.981946 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8108 22:16:57.988575 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8109 22:16:57.991527 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8110 22:16:57.994879 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8111 22:16:58.002081 1 6 12 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
8112 22:16:58.004899 1 6 16 | B1->B0 | 3131 4646 | 1 0 | (1 1) (0 0)
8113 22:16:58.008238 1 6 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8114 22:16:58.014837 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8115 22:16:58.017872 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8116 22:16:58.021488 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8117 22:16:58.028026 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8118 22:16:58.030960 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8119 22:16:58.034999 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8120 22:16:58.041424 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8121 22:16:58.044488 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8122 22:16:58.048313 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8123 22:16:58.054873 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8124 22:16:58.057791 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8125 22:16:58.060928 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8126 22:16:58.067689 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8127 22:16:58.071466 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8128 22:16:58.073897 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8129 22:16:58.080807 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8130 22:16:58.084363 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8131 22:16:58.088081 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8132 22:16:58.093976 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8133 22:16:58.097183 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8134 22:16:58.100707 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8135 22:16:58.107824 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8136 22:16:58.110924 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8137 22:16:58.114607 Total UI for P1: 0, mck2ui 16
8138 22:16:58.117298 best dqsien dly found for B0: ( 1, 9, 10)
8139 22:16:58.120986 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8140 22:16:58.123531 Total UI for P1: 0, mck2ui 16
8141 22:16:58.127514 best dqsien dly found for B1: ( 1, 9, 16)
8142 22:16:58.130480 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8143 22:16:58.134432 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8144 22:16:58.135129
8145 22:16:58.141349 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8146 22:16:58.143641 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8147 22:16:58.147164 [Gating] SW calibration Done
8148 22:16:58.147739 ==
8149 22:16:58.150423 Dram Type= 6, Freq= 0, CH_0, rank 1
8150 22:16:58.153912 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8151 22:16:58.154492 ==
8152 22:16:58.154858 RX Vref Scan: 0
8153 22:16:58.156520
8154 22:16:58.156970 RX Vref 0 -> 0, step: 1
8155 22:16:58.157326
8156 22:16:58.160209 RX Delay 0 -> 252, step: 8
8157 22:16:58.163805 iDelay=208, Bit 0, Center 135 (80 ~ 191) 112
8158 22:16:58.166639 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8159 22:16:58.173029 iDelay=208, Bit 2, Center 127 (72 ~ 183) 112
8160 22:16:58.176598 iDelay=208, Bit 3, Center 127 (72 ~ 183) 112
8161 22:16:58.180206 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8162 22:16:58.183691 iDelay=208, Bit 5, Center 123 (64 ~ 183) 120
8163 22:16:58.186740 iDelay=208, Bit 6, Center 139 (80 ~ 199) 120
8164 22:16:58.193171 iDelay=208, Bit 7, Center 147 (88 ~ 207) 120
8165 22:16:58.196083 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8166 22:16:58.199940 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8167 22:16:58.202719 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8168 22:16:58.209628 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8169 22:16:58.212765 iDelay=208, Bit 12, Center 131 (72 ~ 191) 120
8170 22:16:58.216887 iDelay=208, Bit 13, Center 135 (80 ~ 191) 112
8171 22:16:58.219122 iDelay=208, Bit 14, Center 139 (80 ~ 199) 120
8172 22:16:58.223105 iDelay=208, Bit 15, Center 135 (80 ~ 191) 112
8173 22:16:58.226904 ==
8174 22:16:58.229587 Dram Type= 6, Freq= 0, CH_0, rank 1
8175 22:16:58.232935 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8176 22:16:58.233513 ==
8177 22:16:58.233870 DQS Delay:
8178 22:16:58.235644 DQS0 = 0, DQS1 = 0
8179 22:16:58.236093 DQM Delay:
8180 22:16:58.239513 DQM0 = 133, DQM1 = 129
8181 22:16:58.239961 DQ Delay:
8182 22:16:58.242605 DQ0 =135, DQ1 =135, DQ2 =127, DQ3 =127
8183 22:16:58.246035 DQ4 =135, DQ5 =123, DQ6 =139, DQ7 =147
8184 22:16:58.249006 DQ8 =119, DQ9 =115, DQ10 =131, DQ11 =127
8185 22:16:58.252419 DQ12 =131, DQ13 =135, DQ14 =139, DQ15 =135
8186 22:16:58.252966
8187 22:16:58.253318
8188 22:16:58.255715 ==
8189 22:16:58.256166 Dram Type= 6, Freq= 0, CH_0, rank 1
8190 22:16:58.262421 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8191 22:16:58.262987 ==
8192 22:16:58.263401
8193 22:16:58.263729
8194 22:16:58.265305 TX Vref Scan disable
8195 22:16:58.265758 == TX Byte 0 ==
8196 22:16:58.268663 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8197 22:16:58.275993 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8198 22:16:58.276561 == TX Byte 1 ==
8199 22:16:58.279015 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8200 22:16:58.285243 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8201 22:16:58.285698 ==
8202 22:16:58.289041 Dram Type= 6, Freq= 0, CH_0, rank 1
8203 22:16:58.291721 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8204 22:16:58.292275 ==
8205 22:16:58.305710
8206 22:16:58.308949 TX Vref early break, caculate TX vref
8207 22:16:58.312543 TX Vref=16, minBit 0, minWin=23, winSum=380
8208 22:16:58.316084 TX Vref=18, minBit 0, minWin=23, winSum=385
8209 22:16:58.319629 TX Vref=20, minBit 0, minWin=23, winSum=394
8210 22:16:58.322419 TX Vref=22, minBit 1, minWin=24, winSum=406
8211 22:16:58.325755 TX Vref=24, minBit 1, minWin=24, winSum=411
8212 22:16:58.332425 TX Vref=26, minBit 0, minWin=24, winSum=414
8213 22:16:58.335154 TX Vref=28, minBit 0, minWin=25, winSum=410
8214 22:16:58.338710 TX Vref=30, minBit 0, minWin=24, winSum=404
8215 22:16:58.342083 TX Vref=32, minBit 7, minWin=23, winSum=396
8216 22:16:58.345310 TX Vref=34, minBit 0, minWin=23, winSum=389
8217 22:16:58.351859 [TxChooseVref] Worse bit 0, Min win 25, Win sum 410, Final Vref 28
8218 22:16:58.352432
8219 22:16:58.355431 Final TX Range 0 Vref 28
8220 22:16:58.355883
8221 22:16:58.356235 ==
8222 22:16:58.358387 Dram Type= 6, Freq= 0, CH_0, rank 1
8223 22:16:58.361913 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8224 22:16:58.362372 ==
8225 22:16:58.362725
8226 22:16:58.363051
8227 22:16:58.365073 TX Vref Scan disable
8228 22:16:58.371487 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8229 22:16:58.372080 == TX Byte 0 ==
8230 22:16:58.374978 u2DelayCellOfst[0]=11 cells (3 PI)
8231 22:16:58.378379 u2DelayCellOfst[1]=14 cells (4 PI)
8232 22:16:58.381127 u2DelayCellOfst[2]=11 cells (3 PI)
8233 22:16:58.384609 u2DelayCellOfst[3]=11 cells (3 PI)
8234 22:16:58.387814 u2DelayCellOfst[4]=7 cells (2 PI)
8235 22:16:58.391433 u2DelayCellOfst[5]=0 cells (0 PI)
8236 22:16:58.395198 u2DelayCellOfst[6]=18 cells (5 PI)
8237 22:16:58.397678 u2DelayCellOfst[7]=18 cells (5 PI)
8238 22:16:58.401010 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8239 22:16:58.404334 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8240 22:16:58.408139 == TX Byte 1 ==
8241 22:16:58.410849 u2DelayCellOfst[8]=0 cells (0 PI)
8242 22:16:58.414664 u2DelayCellOfst[9]=3 cells (1 PI)
8243 22:16:58.417383 u2DelayCellOfst[10]=7 cells (2 PI)
8244 22:16:58.420840 u2DelayCellOfst[11]=3 cells (1 PI)
8245 22:16:58.424834 u2DelayCellOfst[12]=11 cells (3 PI)
8246 22:16:58.425393 u2DelayCellOfst[13]=11 cells (3 PI)
8247 22:16:58.427701 u2DelayCellOfst[14]=18 cells (5 PI)
8248 22:16:58.430692 u2DelayCellOfst[15]=11 cells (3 PI)
8249 22:16:58.437562 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8250 22:16:58.440534 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8251 22:16:58.440991 DramC Write-DBI on
8252 22:16:58.444284 ==
8253 22:16:58.447338 Dram Type= 6, Freq= 0, CH_0, rank 1
8254 22:16:58.451185 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8255 22:16:58.451740 ==
8256 22:16:58.452098
8257 22:16:58.452430
8258 22:16:58.453415 TX Vref Scan disable
8259 22:16:58.453866 == TX Byte 0 ==
8260 22:16:58.460582 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
8261 22:16:58.461112 == TX Byte 1 ==
8262 22:16:58.463855 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8263 22:16:58.467357 DramC Write-DBI off
8264 22:16:58.467910
8265 22:16:58.468269 [DATLAT]
8266 22:16:58.470609 Freq=1600, CH0 RK1
8267 22:16:58.471205
8268 22:16:58.471567 DATLAT Default: 0xf
8269 22:16:58.473702 0, 0xFFFF, sum = 0
8270 22:16:58.474192 1, 0xFFFF, sum = 0
8271 22:16:58.476713 2, 0xFFFF, sum = 0
8272 22:16:58.480494 3, 0xFFFF, sum = 0
8273 22:16:58.481070 4, 0xFFFF, sum = 0
8274 22:16:58.483404 5, 0xFFFF, sum = 0
8275 22:16:58.483870 6, 0xFFFF, sum = 0
8276 22:16:58.487174 7, 0xFFFF, sum = 0
8277 22:16:58.487882 8, 0xFFFF, sum = 0
8278 22:16:58.490425 9, 0xFFFF, sum = 0
8279 22:16:58.490990 10, 0xFFFF, sum = 0
8280 22:16:58.493459 11, 0xFFFF, sum = 0
8281 22:16:58.494102 12, 0xFFFF, sum = 0
8282 22:16:58.496698 13, 0xFFFF, sum = 0
8283 22:16:58.497185 14, 0x0, sum = 1
8284 22:16:58.500250 15, 0x0, sum = 2
8285 22:16:58.500737 16, 0x0, sum = 3
8286 22:16:58.504309 17, 0x0, sum = 4
8287 22:16:58.504863 best_step = 15
8288 22:16:58.505227
8289 22:16:58.505580 ==
8290 22:16:58.506592 Dram Type= 6, Freq= 0, CH_0, rank 1
8291 22:16:58.513291 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8292 22:16:58.513849 ==
8293 22:16:58.514211 RX Vref Scan: 0
8294 22:16:58.514546
8295 22:16:58.516328 RX Vref 0 -> 0, step: 1
8296 22:16:58.516787
8297 22:16:58.520069 RX Delay 11 -> 252, step: 4
8298 22:16:58.523116 iDelay=195, Bit 0, Center 128 (79 ~ 178) 100
8299 22:16:58.526430 iDelay=195, Bit 1, Center 136 (83 ~ 190) 108
8300 22:16:58.530132 iDelay=195, Bit 2, Center 126 (75 ~ 178) 104
8301 22:16:58.536321 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8302 22:16:58.539684 iDelay=195, Bit 4, Center 132 (79 ~ 186) 108
8303 22:16:58.542704 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
8304 22:16:58.546281 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8305 22:16:58.549461 iDelay=195, Bit 7, Center 138 (87 ~ 190) 104
8306 22:16:58.555779 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8307 22:16:58.559516 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8308 22:16:58.562770 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8309 22:16:58.565411 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8310 22:16:58.572700 iDelay=195, Bit 12, Center 130 (79 ~ 182) 104
8311 22:16:58.575613 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8312 22:16:58.579105 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
8313 22:16:58.582618 iDelay=195, Bit 15, Center 134 (83 ~ 186) 104
8314 22:16:58.583211 ==
8315 22:16:58.585769 Dram Type= 6, Freq= 0, CH_0, rank 1
8316 22:16:58.592352 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8317 22:16:58.592908 ==
8318 22:16:58.593278 DQS Delay:
8319 22:16:58.593613 DQS0 = 0, DQS1 = 0
8320 22:16:58.595810 DQM Delay:
8321 22:16:58.596266 DQM0 = 130, DQM1 = 126
8322 22:16:58.598937 DQ Delay:
8323 22:16:58.602392 DQ0 =128, DQ1 =136, DQ2 =126, DQ3 =128
8324 22:16:58.605953 DQ4 =132, DQ5 =120, DQ6 =138, DQ7 =138
8325 22:16:58.609290 DQ8 =116, DQ9 =112, DQ10 =128, DQ11 =120
8326 22:16:58.611980 DQ12 =130, DQ13 =132, DQ14 =136, DQ15 =134
8327 22:16:58.612433
8328 22:16:58.612783
8329 22:16:58.613109
8330 22:16:58.615554 [DramC_TX_OE_Calibration] TA2
8331 22:16:58.618836 Original DQ_B0 (3 6) =30, OEN = 27
8332 22:16:58.622404 Original DQ_B1 (3 6) =30, OEN = 27
8333 22:16:58.625219 24, 0x0, End_B0=24 End_B1=24
8334 22:16:58.625821 25, 0x0, End_B0=25 End_B1=25
8335 22:16:58.628614 26, 0x0, End_B0=26 End_B1=26
8336 22:16:58.632230 27, 0x0, End_B0=27 End_B1=27
8337 22:16:58.635289 28, 0x0, End_B0=28 End_B1=28
8338 22:16:58.638660 29, 0x0, End_B0=29 End_B1=29
8339 22:16:58.639172 30, 0x0, End_B0=30 End_B1=30
8340 22:16:58.641786 31, 0x4141, End_B0=30 End_B1=30
8341 22:16:58.645801 Byte0 end_step=30 best_step=27
8342 22:16:58.648605 Byte1 end_step=30 best_step=27
8343 22:16:58.652489 Byte0 TX OE(2T, 0.5T) = (3, 3)
8344 22:16:58.654845 Byte1 TX OE(2T, 0.5T) = (3, 3)
8345 22:16:58.655361
8346 22:16:58.655718
8347 22:16:58.662319 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f03, (MSB)MR19= 0x303, tDQSOscB0 = 408 ps tDQSOscB1 = 394 ps
8348 22:16:58.665066 CH0 RK1: MR19=303, MR18=1F03
8349 22:16:58.671538 CH0_RK1: MR19=0x303, MR18=0x1F03, DQSOSC=394, MR23=63, INC=23, DEC=15
8350 22:16:58.674954 [RxdqsGatingPostProcess] freq 1600
8351 22:16:58.678407 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8352 22:16:58.681529 best DQS0 dly(2T, 0.5T) = (1, 1)
8353 22:16:58.685076 best DQS1 dly(2T, 0.5T) = (1, 1)
8354 22:16:58.688029 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8355 22:16:58.691743 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8356 22:16:58.694893 best DQS0 dly(2T, 0.5T) = (1, 1)
8357 22:16:58.698095 best DQS1 dly(2T, 0.5T) = (1, 1)
8358 22:16:58.701186 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8359 22:16:58.704328 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8360 22:16:58.707755 Pre-setting of DQS Precalculation
8361 22:16:58.711207 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8362 22:16:58.711674 ==
8363 22:16:58.714936 Dram Type= 6, Freq= 0, CH_1, rank 0
8364 22:16:58.721348 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8365 22:16:58.721753 ==
8366 22:16:58.724795 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8367 22:16:58.727784 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8368 22:16:58.734312 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8369 22:16:58.740630 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8370 22:16:58.748848 [CA 0] Center 41 (12~71) winsize 60
8371 22:16:58.751602 [CA 1] Center 42 (12~72) winsize 61
8372 22:16:58.755113 [CA 2] Center 37 (8~66) winsize 59
8373 22:16:58.758627 [CA 3] Center 35 (6~65) winsize 60
8374 22:16:58.761620 [CA 4] Center 36 (7~66) winsize 60
8375 22:16:58.764855 [CA 5] Center 36 (7~66) winsize 60
8376 22:16:58.765305
8377 22:16:58.768137 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8378 22:16:58.768582
8379 22:16:58.771599 [CATrainingPosCal] consider 1 rank data
8380 22:16:58.774676 u2DelayCellTimex100 = 262/100 ps
8381 22:16:58.781475 CA0 delay=41 (12~71),Diff = 6 PI (22 cell)
8382 22:16:58.784761 CA1 delay=42 (12~72),Diff = 7 PI (26 cell)
8383 22:16:58.787576 CA2 delay=37 (8~66),Diff = 2 PI (7 cell)
8384 22:16:58.791737 CA3 delay=35 (6~65),Diff = 0 PI (0 cell)
8385 22:16:58.794407 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
8386 22:16:58.797844 CA5 delay=36 (7~66),Diff = 1 PI (3 cell)
8387 22:16:58.798291
8388 22:16:58.801306 CA PerBit enable=1, Macro0, CA PI delay=35
8389 22:16:58.801774
8390 22:16:58.803946 [CBTSetCACLKResult] CA Dly = 35
8391 22:16:58.808119 CS Dly: 9 (0~40)
8392 22:16:58.810843 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8393 22:16:58.814383 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8394 22:16:58.814928 ==
8395 22:16:58.817985 Dram Type= 6, Freq= 0, CH_1, rank 1
8396 22:16:58.824224 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8397 22:16:58.824773 ==
8398 22:16:58.827455 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8399 22:16:58.834291 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8400 22:16:58.837329 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8401 22:16:58.843389 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8402 22:16:58.851773 [CA 0] Center 42 (12~72) winsize 61
8403 22:16:58.855680 [CA 1] Center 42 (13~72) winsize 60
8404 22:16:58.858765 [CA 2] Center 37 (8~67) winsize 60
8405 22:16:58.861138 [CA 3] Center 36 (7~66) winsize 60
8406 22:16:58.864915 [CA 4] Center 37 (8~67) winsize 60
8407 22:16:58.867943 [CA 5] Center 37 (7~67) winsize 61
8408 22:16:58.868388
8409 22:16:58.871488 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8410 22:16:58.872038
8411 22:16:58.878288 [CATrainingPosCal] consider 2 rank data
8412 22:16:58.878854 u2DelayCellTimex100 = 262/100 ps
8413 22:16:58.884660 CA0 delay=41 (12~71),Diff = 5 PI (18 cell)
8414 22:16:58.887785 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8415 22:16:58.891560 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8416 22:16:58.895003 CA3 delay=36 (7~65),Diff = 0 PI (0 cell)
8417 22:16:58.897930 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8418 22:16:58.900959 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8419 22:16:58.901409
8420 22:16:58.904330 CA PerBit enable=1, Macro0, CA PI delay=36
8421 22:16:58.904904
8422 22:16:58.907995 [CBTSetCACLKResult] CA Dly = 36
8423 22:16:58.911348 CS Dly: 11 (0~44)
8424 22:16:58.914288 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8425 22:16:58.917639 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8426 22:16:58.918195
8427 22:16:58.920962 ----->DramcWriteLeveling(PI) begin...
8428 22:16:58.921525 ==
8429 22:16:58.924447 Dram Type= 6, Freq= 0, CH_1, rank 0
8430 22:16:58.930969 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8431 22:16:58.931752 ==
8432 22:16:58.933593 Write leveling (Byte 0): 24 => 24
8433 22:16:58.937313 Write leveling (Byte 1): 27 => 27
8434 22:16:58.940235 DramcWriteLeveling(PI) end<-----
8435 22:16:58.940677
8436 22:16:58.941018 ==
8437 22:16:58.943273 Dram Type= 6, Freq= 0, CH_1, rank 0
8438 22:16:58.947199 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8439 22:16:58.947740 ==
8440 22:16:58.950231 [Gating] SW mode calibration
8441 22:16:58.957114 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8442 22:16:58.963638 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8443 22:16:58.966755 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8444 22:16:58.971300 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8445 22:16:58.976928 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8446 22:16:58.980670 1 4 12 | B1->B0 | 2e2e 3333 | 0 1 | (0 0) (1 1)
8447 22:16:58.983208 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8448 22:16:58.990656 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8449 22:16:58.993330 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8450 22:16:58.996395 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8451 22:16:59.003603 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8452 22:16:59.006290 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8453 22:16:59.009829 1 5 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
8454 22:16:59.016081 1 5 12 | B1->B0 | 2f2f 2525 | 0 0 | (1 0) (1 0)
8455 22:16:59.019509 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8456 22:16:59.023274 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8457 22:16:59.026251 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8458 22:16:59.032693 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8459 22:16:59.035992 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8460 22:16:59.039171 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8461 22:16:59.045664 1 6 8 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (0 0)
8462 22:16:59.049347 1 6 12 | B1->B0 | 4040 4646 | 1 0 | (0 0) (0 0)
8463 22:16:59.052644 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8464 22:16:59.059610 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8465 22:16:59.062649 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8466 22:16:59.069631 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8467 22:16:59.071946 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8468 22:16:59.075880 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8469 22:16:59.082705 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8470 22:16:59.085670 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8471 22:16:59.089142 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8472 22:16:59.095411 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8473 22:16:59.098375 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8474 22:16:59.102552 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8475 22:16:59.108925 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8476 22:16:59.111850 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8477 22:16:59.115929 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8478 22:16:59.118222 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8479 22:16:59.125131 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8480 22:16:59.128483 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8481 22:16:59.131425 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8482 22:16:59.138229 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8483 22:16:59.141612 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8484 22:16:59.147867 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8485 22:16:59.151577 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8486 22:16:59.154642 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8487 22:16:59.160881 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8488 22:16:59.161422 Total UI for P1: 0, mck2ui 16
8489 22:16:59.168002 best dqsien dly found for B0: ( 1, 9, 10)
8490 22:16:59.171038 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8491 22:16:59.174575 Total UI for P1: 0, mck2ui 16
8492 22:16:59.177801 best dqsien dly found for B1: ( 1, 9, 12)
8493 22:16:59.181216 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8494 22:16:59.184206 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8495 22:16:59.184662
8496 22:16:59.187160 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8497 22:16:59.190863 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8498 22:16:59.194022 [Gating] SW calibration Done
8499 22:16:59.194473 ==
8500 22:16:59.197360 Dram Type= 6, Freq= 0, CH_1, rank 0
8501 22:16:59.203906 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8502 22:16:59.204359 ==
8503 22:16:59.204710 RX Vref Scan: 0
8504 22:16:59.205120
8505 22:16:59.206765 RX Vref 0 -> 0, step: 1
8506 22:16:59.207249
8507 22:16:59.210652 RX Delay 0 -> 252, step: 8
8508 22:16:59.213213 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8509 22:16:59.216671 iDelay=208, Bit 1, Center 131 (80 ~ 183) 104
8510 22:16:59.220302 iDelay=208, Bit 2, Center 127 (72 ~ 183) 112
8511 22:16:59.223887 iDelay=208, Bit 3, Center 139 (88 ~ 191) 104
8512 22:16:59.230403 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8513 22:16:59.233608 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8514 22:16:59.236258 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8515 22:16:59.240296 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8516 22:16:59.245944 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8517 22:16:59.249332 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8518 22:16:59.253192 iDelay=208, Bit 10, Center 131 (80 ~ 183) 104
8519 22:16:59.256657 iDelay=208, Bit 11, Center 123 (72 ~ 175) 104
8520 22:16:59.259672 iDelay=208, Bit 12, Center 139 (88 ~ 191) 104
8521 22:16:59.266159 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8522 22:16:59.270119 iDelay=208, Bit 14, Center 139 (80 ~ 199) 120
8523 22:16:59.272545 iDelay=208, Bit 15, Center 139 (88 ~ 191) 104
8524 22:16:59.273001 ==
8525 22:16:59.275751 Dram Type= 6, Freq= 0, CH_1, rank 0
8526 22:16:59.279004 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8527 22:16:59.283166 ==
8528 22:16:59.283721 DQS Delay:
8529 22:16:59.284080 DQS0 = 0, DQS1 = 0
8530 22:16:59.286019 DQM Delay:
8531 22:16:59.286470 DQM0 = 138, DQM1 = 131
8532 22:16:59.289165 DQ Delay:
8533 22:16:59.292383 DQ0 =139, DQ1 =131, DQ2 =127, DQ3 =139
8534 22:16:59.295745 DQ4 =135, DQ5 =151, DQ6 =147, DQ7 =135
8535 22:16:59.299141 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
8536 22:16:59.302130 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =139
8537 22:16:59.302712
8538 22:16:59.303122
8539 22:16:59.303471 ==
8540 22:16:59.305662 Dram Type= 6, Freq= 0, CH_1, rank 0
8541 22:16:59.308989 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8542 22:16:59.309543 ==
8543 22:16:59.312240
8544 22:16:59.312684
8545 22:16:59.313127 TX Vref Scan disable
8546 22:16:59.315280 == TX Byte 0 ==
8547 22:16:59.319164 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8548 22:16:59.322732 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8549 22:16:59.326195 == TX Byte 1 ==
8550 22:16:59.329137 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8551 22:16:59.332029 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8552 22:16:59.332488 ==
8553 22:16:59.335409 Dram Type= 6, Freq= 0, CH_1, rank 0
8554 22:16:59.341843 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8555 22:16:59.342593 ==
8556 22:16:59.353773
8557 22:16:59.357477 TX Vref early break, caculate TX vref
8558 22:16:59.360372 TX Vref=16, minBit 0, minWin=22, winSum=376
8559 22:16:59.363852 TX Vref=18, minBit 0, minWin=23, winSum=384
8560 22:16:59.366939 TX Vref=20, minBit 5, minWin=23, winSum=394
8561 22:16:59.369915 TX Vref=22, minBit 0, minWin=24, winSum=406
8562 22:16:59.373547 TX Vref=24, minBit 0, minWin=24, winSum=411
8563 22:16:59.380503 TX Vref=26, minBit 5, minWin=24, winSum=416
8564 22:16:59.383937 TX Vref=28, minBit 1, minWin=25, winSum=419
8565 22:16:59.386980 TX Vref=30, minBit 1, minWin=24, winSum=413
8566 22:16:59.390139 TX Vref=32, minBit 0, minWin=23, winSum=400
8567 22:16:59.393517 TX Vref=34, minBit 1, minWin=23, winSum=394
8568 22:16:59.400557 [TxChooseVref] Worse bit 1, Min win 25, Win sum 419, Final Vref 28
8569 22:16:59.401029
8570 22:16:59.403320 Final TX Range 0 Vref 28
8571 22:16:59.403773
8572 22:16:59.404179 ==
8573 22:16:59.406265 Dram Type= 6, Freq= 0, CH_1, rank 0
8574 22:16:59.410291 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8575 22:16:59.410853 ==
8576 22:16:59.411275
8577 22:16:59.411610
8578 22:16:59.413312 TX Vref Scan disable
8579 22:16:59.419925 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8580 22:16:59.420547 == TX Byte 0 ==
8581 22:16:59.423001 u2DelayCellOfst[0]=18 cells (5 PI)
8582 22:16:59.426571 u2DelayCellOfst[1]=11 cells (3 PI)
8583 22:16:59.429815 u2DelayCellOfst[2]=0 cells (0 PI)
8584 22:16:59.432920 u2DelayCellOfst[3]=3 cells (1 PI)
8585 22:16:59.436286 u2DelayCellOfst[4]=7 cells (2 PI)
8586 22:16:59.440013 u2DelayCellOfst[5]=22 cells (6 PI)
8587 22:16:59.442526 u2DelayCellOfst[6]=18 cells (5 PI)
8588 22:16:59.446298 u2DelayCellOfst[7]=3 cells (1 PI)
8589 22:16:59.449470 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8590 22:16:59.452247 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8591 22:16:59.455901 == TX Byte 1 ==
8592 22:16:59.459744 u2DelayCellOfst[8]=0 cells (0 PI)
8593 22:16:59.460293 u2DelayCellOfst[9]=3 cells (1 PI)
8594 22:16:59.462982 u2DelayCellOfst[10]=11 cells (3 PI)
8595 22:16:59.466074 u2DelayCellOfst[11]=7 cells (2 PI)
8596 22:16:59.469234 u2DelayCellOfst[12]=14 cells (4 PI)
8597 22:16:59.472394 u2DelayCellOfst[13]=18 cells (5 PI)
8598 22:16:59.475994 u2DelayCellOfst[14]=18 cells (5 PI)
8599 22:16:59.478970 u2DelayCellOfst[15]=18 cells (5 PI)
8600 22:16:59.485941 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8601 22:16:59.488724 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8602 22:16:59.489180 DramC Write-DBI on
8603 22:16:59.489530 ==
8604 22:16:59.492596 Dram Type= 6, Freq= 0, CH_1, rank 0
8605 22:16:59.499373 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8606 22:16:59.499922 ==
8607 22:16:59.500286
8608 22:16:59.500614
8609 22:16:59.500928 TX Vref Scan disable
8610 22:16:59.503322 == TX Byte 0 ==
8611 22:16:59.506720 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8612 22:16:59.509974 == TX Byte 1 ==
8613 22:16:59.513100 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8614 22:16:59.515952 DramC Write-DBI off
8615 22:16:59.516491
8616 22:16:59.516847 [DATLAT]
8617 22:16:59.517175 Freq=1600, CH1 RK0
8618 22:16:59.517490
8619 22:16:59.519218 DATLAT Default: 0xf
8620 22:16:59.522593 0, 0xFFFF, sum = 0
8621 22:16:59.523215 1, 0xFFFF, sum = 0
8622 22:16:59.526434 2, 0xFFFF, sum = 0
8623 22:16:59.526984 3, 0xFFFF, sum = 0
8624 22:16:59.529290 4, 0xFFFF, sum = 0
8625 22:16:59.529854 5, 0xFFFF, sum = 0
8626 22:16:59.533064 6, 0xFFFF, sum = 0
8627 22:16:59.533522 7, 0xFFFF, sum = 0
8628 22:16:59.536426 8, 0xFFFF, sum = 0
8629 22:16:59.536992 9, 0xFFFF, sum = 0
8630 22:16:59.539590 10, 0xFFFF, sum = 0
8631 22:16:59.540143 11, 0xFFFF, sum = 0
8632 22:16:59.542922 12, 0xFFFF, sum = 0
8633 22:16:59.543831 13, 0xFFFF, sum = 0
8634 22:16:59.545989 14, 0x0, sum = 1
8635 22:16:59.546446 15, 0x0, sum = 2
8636 22:16:59.549587 16, 0x0, sum = 3
8637 22:16:59.550136 17, 0x0, sum = 4
8638 22:16:59.552820 best_step = 15
8639 22:16:59.553366
8640 22:16:59.553723 ==
8641 22:16:59.555740 Dram Type= 6, Freq= 0, CH_1, rank 0
8642 22:16:59.559205 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8643 22:16:59.559681 ==
8644 22:16:59.562695 RX Vref Scan: 1
8645 22:16:59.563290
8646 22:16:59.563717 Set Vref Range= 24 -> 127
8647 22:16:59.564239
8648 22:16:59.565937 RX Vref 24 -> 127, step: 1
8649 22:16:59.566386
8650 22:16:59.568856 RX Delay 19 -> 252, step: 4
8651 22:16:59.569308
8652 22:16:59.572563 Set Vref, RX VrefLevel [Byte0]: 24
8653 22:16:59.575938 [Byte1]: 24
8654 22:16:59.576487
8655 22:16:59.578619 Set Vref, RX VrefLevel [Byte0]: 25
8656 22:16:59.582286 [Byte1]: 25
8657 22:16:59.585252
8658 22:16:59.585703 Set Vref, RX VrefLevel [Byte0]: 26
8659 22:16:59.588972 [Byte1]: 26
8660 22:16:59.594171
8661 22:16:59.594715 Set Vref, RX VrefLevel [Byte0]: 27
8662 22:16:59.596731 [Byte1]: 27
8663 22:16:59.600976
8664 22:16:59.601486 Set Vref, RX VrefLevel [Byte0]: 28
8665 22:16:59.603904 [Byte1]: 28
8666 22:16:59.608059
8667 22:16:59.608508 Set Vref, RX VrefLevel [Byte0]: 29
8668 22:16:59.611249 [Byte1]: 29
8669 22:16:59.615847
8670 22:16:59.615925 Set Vref, RX VrefLevel [Byte0]: 30
8671 22:16:59.618810 [Byte1]: 30
8672 22:16:59.623215
8673 22:16:59.623292 Set Vref, RX VrefLevel [Byte0]: 31
8674 22:16:59.626399 [Byte1]: 31
8675 22:16:59.631450
8676 22:16:59.631539 Set Vref, RX VrefLevel [Byte0]: 32
8677 22:16:59.633931 [Byte1]: 32
8678 22:16:59.638395
8679 22:16:59.638474 Set Vref, RX VrefLevel [Byte0]: 33
8680 22:16:59.641400 [Byte1]: 33
8681 22:16:59.645510
8682 22:16:59.645595 Set Vref, RX VrefLevel [Byte0]: 34
8683 22:16:59.648854 [Byte1]: 34
8684 22:16:59.653323
8685 22:16:59.653414 Set Vref, RX VrefLevel [Byte0]: 35
8686 22:16:59.656616 [Byte1]: 35
8687 22:16:59.660703
8688 22:16:59.660809 Set Vref, RX VrefLevel [Byte0]: 36
8689 22:16:59.664226 [Byte1]: 36
8690 22:16:59.668469
8691 22:16:59.668548 Set Vref, RX VrefLevel [Byte0]: 37
8692 22:16:59.671905 [Byte1]: 37
8693 22:16:59.676033
8694 22:16:59.676124 Set Vref, RX VrefLevel [Byte0]: 38
8695 22:16:59.679392 [Byte1]: 38
8696 22:16:59.683872
8697 22:16:59.683970 Set Vref, RX VrefLevel [Byte0]: 39
8698 22:16:59.686937 [Byte1]: 39
8699 22:16:59.691474
8700 22:16:59.691554 Set Vref, RX VrefLevel [Byte0]: 40
8701 22:16:59.694406 [Byte1]: 40
8702 22:16:59.698832
8703 22:16:59.701867 Set Vref, RX VrefLevel [Byte0]: 41
8704 22:16:59.705769 [Byte1]: 41
8705 22:16:59.705870
8706 22:16:59.708799 Set Vref, RX VrefLevel [Byte0]: 42
8707 22:16:59.711743 [Byte1]: 42
8708 22:16:59.711855
8709 22:16:59.715530 Set Vref, RX VrefLevel [Byte0]: 43
8710 22:16:59.718670 [Byte1]: 43
8711 22:16:59.718814
8712 22:16:59.721662 Set Vref, RX VrefLevel [Byte0]: 44
8713 22:16:59.725320 [Byte1]: 44
8714 22:16:59.729498
8715 22:16:59.729664 Set Vref, RX VrefLevel [Byte0]: 45
8716 22:16:59.732661 [Byte1]: 45
8717 22:16:59.736562
8718 22:16:59.736642 Set Vref, RX VrefLevel [Byte0]: 46
8719 22:16:59.739969 [Byte1]: 46
8720 22:16:59.744223
8721 22:16:59.744304 Set Vref, RX VrefLevel [Byte0]: 47
8722 22:16:59.747355 [Byte1]: 47
8723 22:16:59.752183
8724 22:16:59.752348 Set Vref, RX VrefLevel [Byte0]: 48
8725 22:16:59.754847 [Byte1]: 48
8726 22:16:59.759947
8727 22:16:59.760128 Set Vref, RX VrefLevel [Byte0]: 49
8728 22:16:59.762748 [Byte1]: 49
8729 22:16:59.767242
8730 22:16:59.767413 Set Vref, RX VrefLevel [Byte0]: 50
8731 22:16:59.770323 [Byte1]: 50
8732 22:16:59.774508
8733 22:16:59.774735 Set Vref, RX VrefLevel [Byte0]: 51
8734 22:16:59.777723 [Byte1]: 51
8735 22:16:59.782178
8736 22:16:59.782412 Set Vref, RX VrefLevel [Byte0]: 52
8737 22:16:59.785584 [Byte1]: 52
8738 22:16:59.790351
8739 22:16:59.790636 Set Vref, RX VrefLevel [Byte0]: 53
8740 22:16:59.793504 [Byte1]: 53
8741 22:16:59.797369
8742 22:16:59.797694 Set Vref, RX VrefLevel [Byte0]: 54
8743 22:16:59.801200 [Byte1]: 54
8744 22:16:59.805228
8745 22:16:59.805708 Set Vref, RX VrefLevel [Byte0]: 55
8746 22:16:59.808301 [Byte1]: 55
8747 22:16:59.813310
8748 22:16:59.813862 Set Vref, RX VrefLevel [Byte0]: 56
8749 22:16:59.815986 [Byte1]: 56
8750 22:16:59.820480
8751 22:16:59.821034 Set Vref, RX VrefLevel [Byte0]: 57
8752 22:16:59.823365 [Byte1]: 57
8753 22:16:59.828134
8754 22:16:59.828698 Set Vref, RX VrefLevel [Byte0]: 58
8755 22:16:59.831027 [Byte1]: 58
8756 22:16:59.835864
8757 22:16:59.836427 Set Vref, RX VrefLevel [Byte0]: 59
8758 22:16:59.839025 [Byte1]: 59
8759 22:16:59.842861
8760 22:16:59.843358 Set Vref, RX VrefLevel [Byte0]: 60
8761 22:16:59.846229 [Byte1]: 60
8762 22:16:59.850596
8763 22:16:59.851051 Set Vref, RX VrefLevel [Byte0]: 61
8764 22:16:59.853836 [Byte1]: 61
8765 22:16:59.858666
8766 22:16:59.859262 Set Vref, RX VrefLevel [Byte0]: 62
8767 22:16:59.861869 [Byte1]: 62
8768 22:16:59.866305
8769 22:16:59.866863 Set Vref, RX VrefLevel [Byte0]: 63
8770 22:16:59.869014 [Byte1]: 63
8771 22:16:59.873717
8772 22:16:59.874275 Set Vref, RX VrefLevel [Byte0]: 64
8773 22:16:59.876523 [Byte1]: 64
8774 22:16:59.881103
8775 22:16:59.881669 Set Vref, RX VrefLevel [Byte0]: 65
8776 22:16:59.884139 [Byte1]: 65
8777 22:16:59.888520
8778 22:16:59.889115 Set Vref, RX VrefLevel [Byte0]: 66
8779 22:16:59.891556 [Byte1]: 66
8780 22:16:59.896387
8781 22:16:59.896945 Set Vref, RX VrefLevel [Byte0]: 67
8782 22:16:59.899543 [Byte1]: 67
8783 22:16:59.903788
8784 22:16:59.904339 Set Vref, RX VrefLevel [Byte0]: 68
8785 22:16:59.906998 [Byte1]: 68
8786 22:16:59.911251
8787 22:16:59.911799 Set Vref, RX VrefLevel [Byte0]: 69
8788 22:16:59.914469 [Byte1]: 69
8789 22:16:59.918925
8790 22:16:59.919503 Set Vref, RX VrefLevel [Byte0]: 70
8791 22:16:59.922671 [Byte1]: 70
8792 22:16:59.926697
8793 22:16:59.927318 Set Vref, RX VrefLevel [Byte0]: 71
8794 22:16:59.930497 [Byte1]: 71
8795 22:16:59.933988
8796 22:16:59.934451 Set Vref, RX VrefLevel [Byte0]: 72
8797 22:16:59.937048 [Byte1]: 72
8798 22:16:59.941808
8799 22:16:59.942399 Set Vref, RX VrefLevel [Byte0]: 73
8800 22:16:59.944675 [Byte1]: 73
8801 22:16:59.948787
8802 22:16:59.949243 Set Vref, RX VrefLevel [Byte0]: 74
8803 22:16:59.952136 [Byte1]: 74
8804 22:16:59.956533
8805 22:16:59.957085 Set Vref, RX VrefLevel [Byte0]: 75
8806 22:16:59.959645 [Byte1]: 75
8807 22:16:59.964001
8808 22:16:59.964553 Final RX Vref Byte 0 = 55 to rank0
8809 22:16:59.967656 Final RX Vref Byte 1 = 62 to rank0
8810 22:16:59.971015 Final RX Vref Byte 0 = 55 to rank1
8811 22:16:59.974467 Final RX Vref Byte 1 = 62 to rank1==
8812 22:16:59.977728 Dram Type= 6, Freq= 0, CH_1, rank 0
8813 22:16:59.984164 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8814 22:16:59.984728 ==
8815 22:16:59.985085 DQS Delay:
8816 22:16:59.985435 DQS0 = 0, DQS1 = 0
8817 22:16:59.987884 DQM Delay:
8818 22:16:59.988395 DQM0 = 134, DQM1 = 129
8819 22:16:59.990912 DQ Delay:
8820 22:16:59.993883 DQ0 =142, DQ1 =128, DQ2 =124, DQ3 =132
8821 22:16:59.997911 DQ4 =132, DQ5 =148, DQ6 =144, DQ7 =128
8822 22:17:00.001249 DQ8 =116, DQ9 =116, DQ10 =132, DQ11 =120
8823 22:17:00.004192 DQ12 =138, DQ13 =136, DQ14 =138, DQ15 =138
8824 22:17:00.004645
8825 22:17:00.004998
8826 22:17:00.005325
8827 22:17:00.007355 [DramC_TX_OE_Calibration] TA2
8828 22:17:00.010436 Original DQ_B0 (3 6) =30, OEN = 27
8829 22:17:00.013762 Original DQ_B1 (3 6) =30, OEN = 27
8830 22:17:00.017059 24, 0x0, End_B0=24 End_B1=24
8831 22:17:00.017688 25, 0x0, End_B0=25 End_B1=25
8832 22:17:00.020602 26, 0x0, End_B0=26 End_B1=26
8833 22:17:00.024118 27, 0x0, End_B0=27 End_B1=27
8834 22:17:00.026889 28, 0x0, End_B0=28 End_B1=28
8835 22:17:00.030560 29, 0x0, End_B0=29 End_B1=29
8836 22:17:00.031288 30, 0x0, End_B0=30 End_B1=30
8837 22:17:00.033965 31, 0x4141, End_B0=30 End_B1=30
8838 22:17:00.036953 Byte0 end_step=30 best_step=27
8839 22:17:00.040406 Byte1 end_step=30 best_step=27
8840 22:17:00.043485 Byte0 TX OE(2T, 0.5T) = (3, 3)
8841 22:17:00.046388 Byte1 TX OE(2T, 0.5T) = (3, 3)
8842 22:17:00.046903
8843 22:17:00.047312
8844 22:17:00.053148 [DQSOSCAuto] RK0, (LSB)MR18= 0x170c, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 398 ps
8845 22:17:00.056474 CH1 RK0: MR19=303, MR18=170C
8846 22:17:00.063445 CH1_RK0: MR19=0x303, MR18=0x170C, DQSOSC=398, MR23=63, INC=23, DEC=15
8847 22:17:00.064026
8848 22:17:00.067226 ----->DramcWriteLeveling(PI) begin...
8849 22:17:00.067797 ==
8850 22:17:00.069546 Dram Type= 6, Freq= 0, CH_1, rank 1
8851 22:17:00.072693 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8852 22:17:00.073150 ==
8853 22:17:00.076143 Write leveling (Byte 0): 25 => 25
8854 22:17:00.079604 Write leveling (Byte 1): 26 => 26
8855 22:17:00.082446 DramcWriteLeveling(PI) end<-----
8856 22:17:00.082898
8857 22:17:00.083276 ==
8858 22:17:00.086108 Dram Type= 6, Freq= 0, CH_1, rank 1
8859 22:17:00.093175 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8860 22:17:00.093728 ==
8861 22:17:00.094093 [Gating] SW mode calibration
8862 22:17:00.102800 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8863 22:17:00.105829 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8864 22:17:00.109364 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8865 22:17:00.116597 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8866 22:17:00.119034 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8867 22:17:00.122448 1 4 12 | B1->B0 | 3434 2525 | 0 0 | (0 0) (0 0)
8868 22:17:00.129122 1 4 16 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
8869 22:17:00.132397 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8870 22:17:00.135661 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8871 22:17:00.142097 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8872 22:17:00.145602 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8873 22:17:00.148762 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8874 22:17:00.156505 1 5 8 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 0)
8875 22:17:00.159178 1 5 12 | B1->B0 | 2424 3434 | 0 1 | (1 0) (1 0)
8876 22:17:00.162037 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
8877 22:17:00.168499 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8878 22:17:00.171443 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8879 22:17:00.174958 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8880 22:17:00.181300 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8881 22:17:00.185120 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8882 22:17:00.188168 1 6 8 | B1->B0 | 2929 2323 | 1 0 | (0 0) (0 0)
8883 22:17:00.194528 1 6 12 | B1->B0 | 4646 2727 | 0 0 | (0 0) (0 0)
8884 22:17:00.197838 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8885 22:17:00.204713 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8886 22:17:00.208208 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8887 22:17:00.211232 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8888 22:17:00.217516 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8889 22:17:00.221220 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8890 22:17:00.224867 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8891 22:17:00.227623 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8892 22:17:00.234346 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8893 22:17:00.238425 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8894 22:17:00.241458 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8895 22:17:00.247757 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8896 22:17:00.250573 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8897 22:17:00.253864 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8898 22:17:00.260848 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8899 22:17:00.264063 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8900 22:17:00.267143 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8901 22:17:00.274185 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8902 22:17:00.277044 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8903 22:17:00.280511 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8904 22:17:00.287691 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8905 22:17:00.290699 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8906 22:17:00.293659 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8907 22:17:00.300574 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8908 22:17:00.303634 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8909 22:17:00.307012 Total UI for P1: 0, mck2ui 16
8910 22:17:00.310803 best dqsien dly found for B0: ( 1, 9, 10)
8911 22:17:00.313931 Total UI for P1: 0, mck2ui 16
8912 22:17:00.316919 best dqsien dly found for B1: ( 1, 9, 10)
8913 22:17:00.320087 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8914 22:17:00.323834 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8915 22:17:00.324402
8916 22:17:00.326790 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8917 22:17:00.333137 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8918 22:17:00.333690 [Gating] SW calibration Done
8919 22:17:00.334077 ==
8920 22:17:00.336753 Dram Type= 6, Freq= 0, CH_1, rank 1
8921 22:17:00.343268 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8922 22:17:00.343826 ==
8923 22:17:00.344192 RX Vref Scan: 0
8924 22:17:00.344529
8925 22:17:00.346691 RX Vref 0 -> 0, step: 1
8926 22:17:00.347244
8927 22:17:00.349391 RX Delay 0 -> 252, step: 8
8928 22:17:00.352886 iDelay=208, Bit 0, Center 139 (80 ~ 199) 120
8929 22:17:00.356362 iDelay=208, Bit 1, Center 131 (72 ~ 191) 120
8930 22:17:00.360297 iDelay=208, Bit 2, Center 123 (64 ~ 183) 120
8931 22:17:00.366591 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8932 22:17:00.369523 iDelay=208, Bit 4, Center 135 (72 ~ 199) 128
8933 22:17:00.373081 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8934 22:17:00.376764 iDelay=208, Bit 6, Center 147 (88 ~ 207) 120
8935 22:17:00.379559 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8936 22:17:00.386616 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8937 22:17:00.390113 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8938 22:17:00.392645 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8939 22:17:00.396552 iDelay=208, Bit 11, Center 123 (64 ~ 183) 120
8940 22:17:00.399359 iDelay=208, Bit 12, Center 139 (80 ~ 199) 120
8941 22:17:00.405912 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8942 22:17:00.409300 iDelay=208, Bit 14, Center 135 (72 ~ 199) 128
8943 22:17:00.412423 iDelay=208, Bit 15, Center 139 (80 ~ 199) 120
8944 22:17:00.412974 ==
8945 22:17:00.415445 Dram Type= 6, Freq= 0, CH_1, rank 1
8946 22:17:00.422852 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8947 22:17:00.423437 ==
8948 22:17:00.423804 DQS Delay:
8949 22:17:00.424138 DQS0 = 0, DQS1 = 0
8950 22:17:00.425976 DQM Delay:
8951 22:17:00.426528 DQM0 = 136, DQM1 = 129
8952 22:17:00.429418 DQ Delay:
8953 22:17:00.432254 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8954 22:17:00.435317 DQ4 =135, DQ5 =147, DQ6 =147, DQ7 =135
8955 22:17:00.438814 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8956 22:17:00.442768 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8957 22:17:00.443389
8958 22:17:00.443768
8959 22:17:00.444104 ==
8960 22:17:00.445027 Dram Type= 6, Freq= 0, CH_1, rank 1
8961 22:17:00.448302 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8962 22:17:00.451725 ==
8963 22:17:00.452174
8964 22:17:00.452525
8965 22:17:00.452976 TX Vref Scan disable
8966 22:17:00.455497 == TX Byte 0 ==
8967 22:17:00.458152 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8968 22:17:00.461793 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8969 22:17:00.464800 == TX Byte 1 ==
8970 22:17:00.468195 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8971 22:17:00.474911 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8972 22:17:00.475418 ==
8973 22:17:00.478310 Dram Type= 6, Freq= 0, CH_1, rank 1
8974 22:17:00.481570 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8975 22:17:00.482132 ==
8976 22:17:00.494015
8977 22:17:00.497349 TX Vref early break, caculate TX vref
8978 22:17:00.500475 TX Vref=16, minBit 1, minWin=23, winSum=386
8979 22:17:00.503851 TX Vref=18, minBit 1, minWin=23, winSum=396
8980 22:17:00.507649 TX Vref=20, minBit 0, minWin=24, winSum=407
8981 22:17:00.510565 TX Vref=22, minBit 0, minWin=25, winSum=417
8982 22:17:00.514130 TX Vref=24, minBit 1, minWin=25, winSum=424
8983 22:17:00.520200 TX Vref=26, minBit 1, minWin=25, winSum=426
8984 22:17:00.523991 TX Vref=28, minBit 0, minWin=26, winSum=429
8985 22:17:00.526716 TX Vref=30, minBit 0, minWin=25, winSum=425
8986 22:17:00.530284 TX Vref=32, minBit 0, minWin=25, winSum=414
8987 22:17:00.533875 TX Vref=34, minBit 0, minWin=24, winSum=405
8988 22:17:00.539871 [TxChooseVref] Worse bit 0, Min win 26, Win sum 429, Final Vref 28
8989 22:17:00.540489
8990 22:17:00.543481 Final TX Range 0 Vref 28
8991 22:17:00.544036
8992 22:17:00.544393 ==
8993 22:17:00.547550 Dram Type= 6, Freq= 0, CH_1, rank 1
8994 22:17:00.550103 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8995 22:17:00.550559 ==
8996 22:17:00.550916
8997 22:17:00.551292
8998 22:17:00.553516 TX Vref Scan disable
8999 22:17:00.559920 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
9000 22:17:00.560392 == TX Byte 0 ==
9001 22:17:00.562873 u2DelayCellOfst[0]=22 cells (6 PI)
9002 22:17:00.566187 u2DelayCellOfst[1]=14 cells (4 PI)
9003 22:17:00.569958 u2DelayCellOfst[2]=0 cells (0 PI)
9004 22:17:00.572679 u2DelayCellOfst[3]=7 cells (2 PI)
9005 22:17:00.576550 u2DelayCellOfst[4]=11 cells (3 PI)
9006 22:17:00.580097 u2DelayCellOfst[5]=22 cells (6 PI)
9007 22:17:00.583026 u2DelayCellOfst[6]=22 cells (6 PI)
9008 22:17:00.586121 u2DelayCellOfst[7]=7 cells (2 PI)
9009 22:17:00.589651 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
9010 22:17:00.592728 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
9011 22:17:00.595978 == TX Byte 1 ==
9012 22:17:00.599201 u2DelayCellOfst[8]=0 cells (0 PI)
9013 22:17:00.602389 u2DelayCellOfst[9]=7 cells (2 PI)
9014 22:17:00.605970 u2DelayCellOfst[10]=11 cells (3 PI)
9015 22:17:00.606431 u2DelayCellOfst[11]=7 cells (2 PI)
9016 22:17:00.609040 u2DelayCellOfst[12]=18 cells (5 PI)
9017 22:17:00.612548 u2DelayCellOfst[13]=18 cells (5 PI)
9018 22:17:00.615713 u2DelayCellOfst[14]=18 cells (5 PI)
9019 22:17:00.619251 u2DelayCellOfst[15]=18 cells (5 PI)
9020 22:17:00.626299 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
9021 22:17:00.629015 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
9022 22:17:00.629573 DramC Write-DBI on
9023 22:17:00.629937 ==
9024 22:17:00.632275 Dram Type= 6, Freq= 0, CH_1, rank 1
9025 22:17:00.639219 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9026 22:17:00.639778 ==
9027 22:17:00.640146
9028 22:17:00.640479
9029 22:17:00.642200 TX Vref Scan disable
9030 22:17:00.642753 == TX Byte 0 ==
9031 22:17:00.648828 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
9032 22:17:00.649294 == TX Byte 1 ==
9033 22:17:00.651942 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
9034 22:17:00.655881 DramC Write-DBI off
9035 22:17:00.656338
9036 22:17:00.656694 [DATLAT]
9037 22:17:00.658866 Freq=1600, CH1 RK1
9038 22:17:00.659357
9039 22:17:00.659719 DATLAT Default: 0xf
9040 22:17:00.661696 0, 0xFFFF, sum = 0
9041 22:17:00.662160 1, 0xFFFF, sum = 0
9042 22:17:00.665291 2, 0xFFFF, sum = 0
9043 22:17:00.665751 3, 0xFFFF, sum = 0
9044 22:17:00.668445 4, 0xFFFF, sum = 0
9045 22:17:00.668905 5, 0xFFFF, sum = 0
9046 22:17:00.671884 6, 0xFFFF, sum = 0
9047 22:17:00.672346 7, 0xFFFF, sum = 0
9048 22:17:00.675384 8, 0xFFFF, sum = 0
9049 22:17:00.678691 9, 0xFFFF, sum = 0
9050 22:17:00.679330 10, 0xFFFF, sum = 0
9051 22:17:00.681733 11, 0xFFFF, sum = 0
9052 22:17:00.682262 12, 0xFFFF, sum = 0
9053 22:17:00.685425 13, 0xFFFF, sum = 0
9054 22:17:00.685842 14, 0x0, sum = 1
9055 22:17:00.688813 15, 0x0, sum = 2
9056 22:17:00.689231 16, 0x0, sum = 3
9057 22:17:00.692254 17, 0x0, sum = 4
9058 22:17:00.692785 best_step = 15
9059 22:17:00.693116
9060 22:17:00.693420 ==
9061 22:17:00.695370 Dram Type= 6, Freq= 0, CH_1, rank 1
9062 22:17:00.698033 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9063 22:17:00.698460 ==
9064 22:17:00.701540 RX Vref Scan: 0
9065 22:17:00.701949
9066 22:17:00.704548 RX Vref 0 -> 0, step: 1
9067 22:17:00.704962
9068 22:17:00.705351 RX Delay 11 -> 252, step: 4
9069 22:17:00.712179 iDelay=203, Bit 0, Center 140 (87 ~ 194) 108
9070 22:17:00.715903 iDelay=203, Bit 1, Center 128 (75 ~ 182) 108
9071 22:17:00.718824 iDelay=203, Bit 2, Center 122 (67 ~ 178) 112
9072 22:17:00.721933 iDelay=203, Bit 3, Center 130 (79 ~ 182) 104
9073 22:17:00.725975 iDelay=203, Bit 4, Center 132 (79 ~ 186) 108
9074 22:17:00.732766 iDelay=203, Bit 5, Center 144 (91 ~ 198) 108
9075 22:17:00.735107 iDelay=203, Bit 6, Center 146 (91 ~ 202) 112
9076 22:17:00.738458 iDelay=203, Bit 7, Center 130 (79 ~ 182) 104
9077 22:17:00.741825 iDelay=203, Bit 8, Center 114 (59 ~ 170) 112
9078 22:17:00.745349 iDelay=203, Bit 9, Center 116 (63 ~ 170) 108
9079 22:17:00.751672 iDelay=203, Bit 10, Center 126 (71 ~ 182) 112
9080 22:17:00.755121 iDelay=203, Bit 11, Center 118 (67 ~ 170) 104
9081 22:17:00.758325 iDelay=203, Bit 12, Center 134 (79 ~ 190) 112
9082 22:17:00.761767 iDelay=203, Bit 13, Center 134 (83 ~ 186) 104
9083 22:17:00.768232 iDelay=203, Bit 14, Center 134 (79 ~ 190) 112
9084 22:17:00.771630 iDelay=203, Bit 15, Center 138 (83 ~ 194) 112
9085 22:17:00.772043 ==
9086 22:17:00.774790 Dram Type= 6, Freq= 0, CH_1, rank 1
9087 22:17:00.778328 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9088 22:17:00.778752 ==
9089 22:17:00.782318 DQS Delay:
9090 22:17:00.782963 DQS0 = 0, DQS1 = 0
9091 22:17:00.783360 DQM Delay:
9092 22:17:00.785280 DQM0 = 134, DQM1 = 126
9093 22:17:00.785794 DQ Delay:
9094 22:17:00.787807 DQ0 =140, DQ1 =128, DQ2 =122, DQ3 =130
9095 22:17:00.791994 DQ4 =132, DQ5 =144, DQ6 =146, DQ7 =130
9096 22:17:00.794927 DQ8 =114, DQ9 =116, DQ10 =126, DQ11 =118
9097 22:17:00.801640 DQ12 =134, DQ13 =134, DQ14 =134, DQ15 =138
9098 22:17:00.802185
9099 22:17:00.802547
9100 22:17:00.802952
9101 22:17:00.804444 [DramC_TX_OE_Calibration] TA2
9102 22:17:00.808593 Original DQ_B0 (3 6) =30, OEN = 27
9103 22:17:00.809156 Original DQ_B1 (3 6) =30, OEN = 27
9104 22:17:00.811442 24, 0x0, End_B0=24 End_B1=24
9105 22:17:00.815180 25, 0x0, End_B0=25 End_B1=25
9106 22:17:00.817971 26, 0x0, End_B0=26 End_B1=26
9107 22:17:00.821198 27, 0x0, End_B0=27 End_B1=27
9108 22:17:00.821665 28, 0x0, End_B0=28 End_B1=28
9109 22:17:00.824795 29, 0x0, End_B0=29 End_B1=29
9110 22:17:00.827909 30, 0x0, End_B0=30 End_B1=30
9111 22:17:00.831184 31, 0x4141, End_B0=30 End_B1=30
9112 22:17:00.834806 Byte0 end_step=30 best_step=27
9113 22:17:00.838148 Byte1 end_step=30 best_step=27
9114 22:17:00.838699 Byte0 TX OE(2T, 0.5T) = (3, 3)
9115 22:17:00.840874 Byte1 TX OE(2T, 0.5T) = (3, 3)
9116 22:17:00.841333
9117 22:17:00.841693
9118 22:17:00.850841 [DQSOSCAuto] RK1, (LSB)MR18= 0xe0b, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 402 ps
9119 22:17:00.854116 CH1 RK1: MR19=303, MR18=E0B
9120 22:17:00.857553 CH1_RK1: MR19=0x303, MR18=0xE0B, DQSOSC=402, MR23=63, INC=22, DEC=15
9121 22:17:00.860713 [RxdqsGatingPostProcess] freq 1600
9122 22:17:00.867163 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9123 22:17:00.870646 best DQS0 dly(2T, 0.5T) = (1, 1)
9124 22:17:00.873651 best DQS1 dly(2T, 0.5T) = (1, 1)
9125 22:17:00.877110 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9126 22:17:00.880487 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9127 22:17:00.883535 best DQS0 dly(2T, 0.5T) = (1, 1)
9128 22:17:00.883995 best DQS1 dly(2T, 0.5T) = (1, 1)
9129 22:17:00.887419 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9130 22:17:00.890576 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9131 22:17:00.893882 Pre-setting of DQS Precalculation
9132 22:17:00.900571 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9133 22:17:00.907146 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9134 22:17:00.913354 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9135 22:17:00.913894
9136 22:17:00.914252
9137 22:17:00.916845 [Calibration Summary] 3200 Mbps
9138 22:17:00.920717 CH 0, Rank 0
9139 22:17:00.921272 SW Impedance : PASS
9140 22:17:00.923399 DUTY Scan : NO K
9141 22:17:00.923862 ZQ Calibration : PASS
9142 22:17:00.926628 Jitter Meter : NO K
9143 22:17:00.930102 CBT Training : PASS
9144 22:17:00.930686 Write leveling : PASS
9145 22:17:00.933415 RX DQS gating : PASS
9146 22:17:00.937318 RX DQ/DQS(RDDQC) : PASS
9147 22:17:00.937928 TX DQ/DQS : PASS
9148 22:17:00.940192 RX DATLAT : PASS
9149 22:17:00.943430 RX DQ/DQS(Engine): PASS
9150 22:17:00.943982 TX OE : PASS
9151 22:17:00.946901 All Pass.
9152 22:17:00.947510
9153 22:17:00.947973 CH 0, Rank 1
9154 22:17:00.949989 SW Impedance : PASS
9155 22:17:00.950445 DUTY Scan : NO K
9156 22:17:00.953113 ZQ Calibration : PASS
9157 22:17:00.956978 Jitter Meter : NO K
9158 22:17:00.957538 CBT Training : PASS
9159 22:17:00.959895 Write leveling : PASS
9160 22:17:00.963661 RX DQS gating : PASS
9161 22:17:00.964217 RX DQ/DQS(RDDQC) : PASS
9162 22:17:00.967007 TX DQ/DQS : PASS
9163 22:17:00.970161 RX DATLAT : PASS
9164 22:17:00.970721 RX DQ/DQS(Engine): PASS
9165 22:17:00.973052 TX OE : PASS
9166 22:17:00.973609 All Pass.
9167 22:17:00.973969
9168 22:17:00.976243 CH 1, Rank 0
9169 22:17:00.976700 SW Impedance : PASS
9170 22:17:00.979726 DUTY Scan : NO K
9171 22:17:00.982878 ZQ Calibration : PASS
9172 22:17:00.983510 Jitter Meter : NO K
9173 22:17:00.985954 CBT Training : PASS
9174 22:17:00.986542 Write leveling : PASS
9175 22:17:00.989472 RX DQS gating : PASS
9176 22:17:00.992864 RX DQ/DQS(RDDQC) : PASS
9177 22:17:00.993317 TX DQ/DQS : PASS
9178 22:17:00.995863 RX DATLAT : PASS
9179 22:17:00.999378 RX DQ/DQS(Engine): PASS
9180 22:17:00.999837 TX OE : PASS
9181 22:17:01.002524 All Pass.
9182 22:17:01.002970
9183 22:17:01.003483 CH 1, Rank 1
9184 22:17:01.006359 SW Impedance : PASS
9185 22:17:01.006810 DUTY Scan : NO K
9186 22:17:01.009791 ZQ Calibration : PASS
9187 22:17:01.012660 Jitter Meter : NO K
9188 22:17:01.013228 CBT Training : PASS
9189 22:17:01.015666 Write leveling : PASS
9190 22:17:01.019209 RX DQS gating : PASS
9191 22:17:01.019663 RX DQ/DQS(RDDQC) : PASS
9192 22:17:01.022653 TX DQ/DQS : PASS
9193 22:17:01.026111 RX DATLAT : PASS
9194 22:17:01.026780 RX DQ/DQS(Engine): PASS
9195 22:17:01.029577 TX OE : PASS
9196 22:17:01.030128 All Pass.
9197 22:17:01.030551
9198 22:17:01.032995 DramC Write-DBI on
9199 22:17:01.035634 PER_BANK_REFRESH: Hybrid Mode
9200 22:17:01.036260 TX_TRACKING: ON
9201 22:17:01.045839 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9202 22:17:01.052665 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9203 22:17:01.059260 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9204 22:17:01.062795 [FAST_K] Save calibration result to emmc
9205 22:17:01.066006 sync common calibartion params.
9206 22:17:01.069150 sync cbt_mode0:1, 1:1
9207 22:17:01.072905 dram_init: ddr_geometry: 2
9208 22:17:01.073458 dram_init: ddr_geometry: 2
9209 22:17:01.075790 dram_init: ddr_geometry: 2
9210 22:17:01.079008 0:dram_rank_size:100000000
9211 22:17:01.082251 1:dram_rank_size:100000000
9212 22:17:01.085656 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9213 22:17:01.088610 DFS_SHUFFLE_HW_MODE: ON
9214 22:17:01.091973 dramc_set_vcore_voltage set vcore to 725000
9215 22:17:01.095627 Read voltage for 1600, 0
9216 22:17:01.096129 Vio18 = 0
9217 22:17:01.096486 Vcore = 725000
9218 22:17:01.098708 Vdram = 0
9219 22:17:01.099217 Vddq = 0
9220 22:17:01.099622 Vmddr = 0
9221 22:17:01.102273 switch to 3200 Mbps bootup
9222 22:17:01.105467 [DramcRunTimeConfig]
9223 22:17:01.106009 PHYPLL
9224 22:17:01.106364 DPM_CONTROL_AFTERK: ON
9225 22:17:01.109029 PER_BANK_REFRESH: ON
9226 22:17:01.112218 REFRESH_OVERHEAD_REDUCTION: ON
9227 22:17:01.112771 CMD_PICG_NEW_MODE: OFF
9228 22:17:01.116400 XRTWTW_NEW_MODE: ON
9229 22:17:01.118737 XRTRTR_NEW_MODE: ON
9230 22:17:01.119327 TX_TRACKING: ON
9231 22:17:01.122394 RDSEL_TRACKING: OFF
9232 22:17:01.122947 DQS Precalculation for DVFS: ON
9233 22:17:01.125785 RX_TRACKING: OFF
9234 22:17:01.126235 HW_GATING DBG: ON
9235 22:17:01.128467 ZQCS_ENABLE_LP4: ON
9236 22:17:01.128918 RX_PICG_NEW_MODE: ON
9237 22:17:01.132222 TX_PICG_NEW_MODE: ON
9238 22:17:01.134979 ENABLE_RX_DCM_DPHY: ON
9239 22:17:01.138119 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9240 22:17:01.138574 DUMMY_READ_FOR_TRACKING: OFF
9241 22:17:01.141556 !!! SPM_CONTROL_AFTERK: OFF
9242 22:17:01.144685 !!! SPM could not control APHY
9243 22:17:01.148151 IMPEDANCE_TRACKING: ON
9244 22:17:01.148601 TEMP_SENSOR: ON
9245 22:17:01.151437 HW_SAVE_FOR_SR: OFF
9246 22:17:01.154842 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9247 22:17:01.158086 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9248 22:17:01.158641 Read ODT Tracking: ON
9249 22:17:01.161475 Refresh Rate DeBounce: ON
9250 22:17:01.164660 DFS_NO_QUEUE_FLUSH: ON
9251 22:17:01.167984 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9252 22:17:01.168472 ENABLE_DFS_RUNTIME_MRW: OFF
9253 22:17:01.171172 DDR_RESERVE_NEW_MODE: ON
9254 22:17:01.174535 MR_CBT_SWITCH_FREQ: ON
9255 22:17:01.174985 =========================
9256 22:17:01.194736 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9257 22:17:01.197643 dram_init: ddr_geometry: 2
9258 22:17:01.216394 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9259 22:17:01.219689 dram_init: dram init end (result: 0)
9260 22:17:01.226650 DRAM-K: Full calibration passed in 24609 msecs
9261 22:17:01.229455 MRC: failed to locate region type 0.
9262 22:17:01.230095 DRAM rank0 size:0x100000000,
9263 22:17:01.232435 DRAM rank1 size=0x100000000
9264 22:17:01.242688 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9265 22:17:01.249560 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9266 22:17:01.255582 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9267 22:17:01.265365 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9268 22:17:01.265911 DRAM rank0 size:0x100000000,
9269 22:17:01.268995 DRAM rank1 size=0x100000000
9270 22:17:01.269542 CBMEM:
9271 22:17:01.272063 IMD: root @ 0xfffff000 254 entries.
9272 22:17:01.275331 IMD: root @ 0xffffec00 62 entries.
9273 22:17:01.279050 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9274 22:17:01.285361 WARNING: RO_VPD is uninitialized or empty.
9275 22:17:01.288826 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9276 22:17:01.296248 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9277 22:17:01.309347 read SPI 0x42894 0xe01e: 6223 us, 9219 KB/s, 73.752 Mbps
9278 22:17:01.320514 BS: romstage times (exec / console): total (unknown) / 24107 ms
9279 22:17:01.321078
9280 22:17:01.321437
9281 22:17:01.330196 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9282 22:17:01.334153 ARM64: Exception handlers installed.
9283 22:17:01.336540 ARM64: Testing exception
9284 22:17:01.340002 ARM64: Done test exception
9285 22:17:01.340582 Enumerating buses...
9286 22:17:01.343752 Show all devs... Before device enumeration.
9287 22:17:01.346490 Root Device: enabled 1
9288 22:17:01.349948 CPU_CLUSTER: 0: enabled 1
9289 22:17:01.350524 CPU: 00: enabled 1
9290 22:17:01.353151 Compare with tree...
9291 22:17:01.353611 Root Device: enabled 1
9292 22:17:01.357159 CPU_CLUSTER: 0: enabled 1
9293 22:17:01.359754 CPU: 00: enabled 1
9294 22:17:01.360211 Root Device scanning...
9295 22:17:01.362991 scan_static_bus for Root Device
9296 22:17:01.366009 CPU_CLUSTER: 0 enabled
9297 22:17:01.369977 scan_static_bus for Root Device done
9298 22:17:01.373325 scan_bus: bus Root Device finished in 8 msecs
9299 22:17:01.373896 done
9300 22:17:01.379315 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9301 22:17:01.382766 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9302 22:17:01.389207 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9303 22:17:01.396688 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9304 22:17:01.397251 Allocating resources...
9305 22:17:01.399204 Reading resources...
9306 22:17:01.402361 Root Device read_resources bus 0 link: 0
9307 22:17:01.405684 DRAM rank0 size:0x100000000,
9308 22:17:01.406160 DRAM rank1 size=0x100000000
9309 22:17:01.413062 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9310 22:17:01.413630 CPU: 00 missing read_resources
9311 22:17:01.419182 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9312 22:17:01.422742 Root Device read_resources bus 0 link: 0 done
9313 22:17:01.426383 Done reading resources.
9314 22:17:01.429628 Show resources in subtree (Root Device)...After reading.
9315 22:17:01.432631 Root Device child on link 0 CPU_CLUSTER: 0
9316 22:17:01.435627 CPU_CLUSTER: 0 child on link 0 CPU: 00
9317 22:17:01.445438 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9318 22:17:01.445995 CPU: 00
9319 22:17:01.452123 Root Device assign_resources, bus 0 link: 0
9320 22:17:01.455145 CPU_CLUSTER: 0 missing set_resources
9321 22:17:01.458721 Root Device assign_resources, bus 0 link: 0 done
9322 22:17:01.462139 Done setting resources.
9323 22:17:01.465089 Show resources in subtree (Root Device)...After assigning values.
9324 22:17:01.468373 Root Device child on link 0 CPU_CLUSTER: 0
9325 22:17:01.475092 CPU_CLUSTER: 0 child on link 0 CPU: 00
9326 22:17:01.482024 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9327 22:17:01.484745 CPU: 00
9328 22:17:01.485315 Done allocating resources.
9329 22:17:01.491825 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9330 22:17:01.492290 Enabling resources...
9331 22:17:01.494394 done.
9332 22:17:01.498363 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9333 22:17:01.501278 Initializing devices...
9334 22:17:01.501760 Root Device init
9335 22:17:01.504622 init hardware done!
9336 22:17:01.505085 0x00000018: ctrlr->caps
9337 22:17:01.507719 52.000 MHz: ctrlr->f_max
9338 22:17:01.511365 0.400 MHz: ctrlr->f_min
9339 22:17:01.514921 0x40ff8080: ctrlr->voltages
9340 22:17:01.515573 sclk: 390625
9341 22:17:01.515940 Bus Width = 1
9342 22:17:01.517989 sclk: 390625
9343 22:17:01.518441 Bus Width = 1
9344 22:17:01.520913 Early init status = 3
9345 22:17:01.524366 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9346 22:17:01.529779 in-header: 03 fc 00 00 01 00 00 00
9347 22:17:01.533163 in-data: 00
9348 22:17:01.535954 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9349 22:17:01.540738 in-header: 03 fd 00 00 00 00 00 00
9350 22:17:01.544291 in-data:
9351 22:17:01.547433 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9352 22:17:01.552083 in-header: 03 fc 00 00 01 00 00 00
9353 22:17:01.555175 in-data: 00
9354 22:17:01.558692 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9355 22:17:01.565460 in-header: 03 fd 00 00 00 00 00 00
9356 22:17:01.569218 in-data:
9357 22:17:01.571733 [SSUSB] Setting up USB HOST controller...
9358 22:17:01.575008 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9359 22:17:01.578907 [SSUSB] phy power-on done.
9360 22:17:01.581823 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9361 22:17:01.588159 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9362 22:17:01.591963 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9363 22:17:01.598251 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9364 22:17:01.605013 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9365 22:17:01.611512 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9366 22:17:01.618014 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9367 22:17:01.624555 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9368 22:17:01.628191 SPM: binary array size = 0x9dc
9369 22:17:01.631209 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9370 22:17:01.637723 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9371 22:17:01.644059 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9372 22:17:01.651098 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9373 22:17:01.653977 configure_display: Starting display init
9374 22:17:01.688773 anx7625_power_on_init: Init interface.
9375 22:17:01.691681 anx7625_disable_pd_protocol: Disabled PD feature.
9376 22:17:01.694960 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9377 22:17:01.722976 anx7625_start_dp_work: Secure OCM version=00
9378 22:17:01.727145 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9379 22:17:01.741020 sp_tx_get_edid_block: EDID Block = 1
9380 22:17:01.843998 Extracted contents:
9381 22:17:01.846807 header: 00 ff ff ff ff ff ff 00
9382 22:17:01.850508 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9383 22:17:01.853930 version: 01 04
9384 22:17:01.856717 basic params: 95 1f 11 78 0a
9385 22:17:01.860389 chroma info: 76 90 94 55 54 90 27 21 50 54
9386 22:17:01.864084 established: 00 00 00
9387 22:17:01.869987 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9388 22:17:01.873597 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9389 22:17:01.879822 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9390 22:17:01.886860 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9391 22:17:01.893286 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9392 22:17:01.897050 extensions: 00
9393 22:17:01.897605 checksum: fb
9394 22:17:01.897967
9395 22:17:01.899539 Manufacturer: IVO Model 57d Serial Number 0
9396 22:17:01.902838 Made week 0 of 2020
9397 22:17:01.906841 EDID version: 1.4
9398 22:17:01.907476 Digital display
9399 22:17:01.909576 6 bits per primary color channel
9400 22:17:01.910141 DisplayPort interface
9401 22:17:01.913121 Maximum image size: 31 cm x 17 cm
9402 22:17:01.916099 Gamma: 220%
9403 22:17:01.916646 Check DPMS levels
9404 22:17:01.920022 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9405 22:17:01.926182 First detailed timing is preferred timing
9406 22:17:01.926749 Established timings supported:
9407 22:17:01.929520 Standard timings supported:
9408 22:17:01.933047 Detailed timings
9409 22:17:01.936003 Hex of detail: 383680a07038204018303c0035ae10000019
9410 22:17:01.942450 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9411 22:17:01.946005 0780 0798 07c8 0820 hborder 0
9412 22:17:01.949782 0438 043b 0447 0458 vborder 0
9413 22:17:01.953036 -hsync -vsync
9414 22:17:01.953596 Did detailed timing
9415 22:17:01.959328 Hex of detail: 000000000000000000000000000000000000
9416 22:17:01.962798 Manufacturer-specified data, tag 0
9417 22:17:01.965733 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9418 22:17:01.968824 ASCII string: InfoVision
9419 22:17:01.972906 Hex of detail: 000000fe00523134304e574635205248200a
9420 22:17:01.975826 ASCII string: R140NWF5 RH
9421 22:17:01.976298 Checksum
9422 22:17:01.979279 Checksum: 0xfb (valid)
9423 22:17:01.982610 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9424 22:17:01.985973 DSI data_rate: 832800000 bps
9425 22:17:01.992197 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9426 22:17:01.995400 anx7625_parse_edid: pixelclock(138800).
9427 22:17:01.999232 hactive(1920), hsync(48), hfp(24), hbp(88)
9428 22:17:02.001884 vactive(1080), vsync(12), vfp(3), vbp(17)
9429 22:17:02.005416 anx7625_dsi_config: config dsi.
9430 22:17:02.011941 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9431 22:17:02.025305 anx7625_dsi_config: success to config DSI
9432 22:17:02.028992 anx7625_dp_start: MIPI phy setup OK.
9433 22:17:02.032478 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9434 22:17:02.035517 mtk_ddp_mode_set invalid vrefresh 60
9435 22:17:02.039580 main_disp_path_setup
9436 22:17:02.040139 ovl_layer_smi_id_en
9437 22:17:02.042497 ovl_layer_smi_id_en
9438 22:17:02.043102 ccorr_config
9439 22:17:02.043518 aal_config
9440 22:17:02.045898 gamma_config
9441 22:17:02.046459 postmask_config
9442 22:17:02.048794 dither_config
9443 22:17:02.051783 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9444 22:17:02.059231 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9445 22:17:02.061890 Root Device init finished in 556 msecs
9446 22:17:02.065460 CPU_CLUSTER: 0 init
9447 22:17:02.071995 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9448 22:17:02.078981 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9449 22:17:02.079571 APU_MBOX 0x190000b0 = 0x10001
9450 22:17:02.081836 APU_MBOX 0x190001b0 = 0x10001
9451 22:17:02.085217 APU_MBOX 0x190005b0 = 0x10001
9452 22:17:02.088884 APU_MBOX 0x190006b0 = 0x10001
9453 22:17:02.095747 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9454 22:17:02.104766 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9455 22:17:02.117084 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9456 22:17:02.123897 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9457 22:17:02.135398 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9458 22:17:02.144476 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9459 22:17:02.148230 CPU_CLUSTER: 0 init finished in 81 msecs
9460 22:17:02.151348 Devices initialized
9461 22:17:02.154944 Show all devs... After init.
9462 22:17:02.155605 Root Device: enabled 1
9463 22:17:02.157533 CPU_CLUSTER: 0: enabled 1
9464 22:17:02.161534 CPU: 00: enabled 1
9465 22:17:02.164382 BS: BS_DEV_INIT run times (exec / console): 214 / 447 ms
9466 22:17:02.167979 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9467 22:17:02.170544 ELOG: NV offset 0x57f000 size 0x1000
9468 22:17:02.177460 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9469 22:17:02.184153 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9470 22:17:02.187733 ELOG: Event(17) added with size 13 at 2023-06-04 22:17:02 UTC
9471 22:17:02.194441 out: cmd=0x121: 03 db 21 01 00 00 00 00
9472 22:17:02.197234 in-header: 03 cb 00 00 2c 00 00 00
9473 22:17:02.207449 in-data: 94 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9474 22:17:02.214387 ELOG: Event(A1) added with size 10 at 2023-06-04 22:17:02 UTC
9475 22:17:02.220617 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9476 22:17:02.226845 ELOG: Event(A0) added with size 9 at 2023-06-04 22:17:02 UTC
9477 22:17:02.230215 elog_add_boot_reason: Logged dev mode boot
9478 22:17:02.236725 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9479 22:17:02.237279 Finalize devices...
9480 22:17:02.240229 Devices finalized
9481 22:17:02.243394 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9482 22:17:02.246871 Writing coreboot table at 0xffe64000
9483 22:17:02.249954 0. 000000000010a000-0000000000113fff: RAMSTAGE
9484 22:17:02.256640 1. 0000000040000000-00000000400fffff: RAM
9485 22:17:02.260401 2. 0000000040100000-000000004032afff: RAMSTAGE
9486 22:17:02.263253 3. 000000004032b000-00000000545fffff: RAM
9487 22:17:02.266991 4. 0000000054600000-000000005465ffff: BL31
9488 22:17:02.270112 5. 0000000054660000-00000000ffe63fff: RAM
9489 22:17:02.276695 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9490 22:17:02.279611 7. 0000000100000000-000000023fffffff: RAM
9491 22:17:02.282643 Passing 5 GPIOs to payload:
9492 22:17:02.286106 NAME | PORT | POLARITY | VALUE
9493 22:17:02.292581 EC in RW | 0x000000aa | low | undefined
9494 22:17:02.295901 EC interrupt | 0x00000005 | low | undefined
9495 22:17:02.299610 TPM interrupt | 0x000000ab | high | undefined
9496 22:17:02.306376 SD card detect | 0x00000011 | high | undefined
9497 22:17:02.309128 speaker enable | 0x00000093 | high | undefined
9498 22:17:02.313204 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9499 22:17:02.316151 in-header: 03 f9 00 00 02 00 00 00
9500 22:17:02.319725 in-data: 02 00
9501 22:17:02.323212 ADC[4]: Raw value=903400 ID=7
9502 22:17:02.326833 ADC[3]: Raw value=213282 ID=1
9503 22:17:02.327440 RAM Code: 0x71
9504 22:17:02.329512 ADC[6]: Raw value=75036 ID=0
9505 22:17:02.332710 ADC[5]: Raw value=213652 ID=1
9506 22:17:02.333279 SKU Code: 0x1
9507 22:17:02.339727 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum a129
9508 22:17:02.340356 coreboot table: 964 bytes.
9509 22:17:02.342475 IMD ROOT 0. 0xfffff000 0x00001000
9510 22:17:02.345612 IMD SMALL 1. 0xffffe000 0x00001000
9511 22:17:02.349195 RO MCACHE 2. 0xffffc000 0x00001104
9512 22:17:02.352674 CONSOLE 3. 0xfff7c000 0x00080000
9513 22:17:02.355918 FMAP 4. 0xfff7b000 0x00000452
9514 22:17:02.358629 TIME STAMP 5. 0xfff7a000 0x00000910
9515 22:17:02.362636 VBOOT WORK 6. 0xfff66000 0x00014000
9516 22:17:02.365711 RAMOOPS 7. 0xffe66000 0x00100000
9517 22:17:02.368729 COREBOOT 8. 0xffe64000 0x00002000
9518 22:17:02.372383 IMD small region:
9519 22:17:02.375380 IMD ROOT 0. 0xffffec00 0x00000400
9520 22:17:02.378601 VPD 1. 0xffffeba0 0x0000004c
9521 22:17:02.382255 MMC STATUS 2. 0xffffeb80 0x00000004
9522 22:17:02.389184 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9523 22:17:02.389764 Probing TPM: done!
9524 22:17:02.395233 Connected to device vid:did:rid of 1ae0:0028:00
9525 22:17:02.402301 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9526 22:17:02.405224 Initialized TPM device CR50 revision 0
9527 22:17:02.408648 Checking cr50 for pending updates
9528 22:17:02.414668 Reading cr50 TPM mode
9529 22:17:02.423196 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9530 22:17:02.429509 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9531 22:17:02.469702 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9532 22:17:02.472984 Checking segment from ROM address 0x40100000
9533 22:17:02.476179 Checking segment from ROM address 0x4010001c
9534 22:17:02.483250 Loading segment from ROM address 0x40100000
9535 22:17:02.483820 code (compression=0)
9536 22:17:02.493614 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9537 22:17:02.499726 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9538 22:17:02.500285 it's not compressed!
9539 22:17:02.506302 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9540 22:17:02.512843 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9541 22:17:02.530298 Loading segment from ROM address 0x4010001c
9542 22:17:02.530866 Entry Point 0x80000000
9543 22:17:02.533908 Loaded segments
9544 22:17:02.537331 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9545 22:17:02.543567 Jumping to boot code at 0x80000000(0xffe64000)
9546 22:17:02.550347 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9547 22:17:02.556440 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9548 22:17:02.564459 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9549 22:17:02.567553 Checking segment from ROM address 0x40100000
9550 22:17:02.570561 Checking segment from ROM address 0x4010001c
9551 22:17:02.577973 Loading segment from ROM address 0x40100000
9552 22:17:02.578538 code (compression=1)
9553 22:17:02.584318 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9554 22:17:02.594105 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9555 22:17:02.594677 using LZMA
9556 22:17:02.603143 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9557 22:17:02.609725 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9558 22:17:02.612721 Loading segment from ROM address 0x4010001c
9559 22:17:02.613288 Entry Point 0x54601000
9560 22:17:02.616513 Loaded segments
9561 22:17:02.619859 NOTICE: MT8192 bl31_setup
9562 22:17:02.626387 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9563 22:17:02.630161 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9564 22:17:02.633637 WARNING: region 0:
9565 22:17:02.636278 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9566 22:17:02.636744 WARNING: region 1:
9567 22:17:02.643329 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9568 22:17:02.646549 WARNING: region 2:
9569 22:17:02.649990 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9570 22:17:02.653064 WARNING: region 3:
9571 22:17:02.656373 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9572 22:17:02.659471 WARNING: region 4:
9573 22:17:02.666431 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9574 22:17:02.667000 WARNING: region 5:
9575 22:17:02.669237 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9576 22:17:02.672870 WARNING: region 6:
9577 22:17:02.676699 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9578 22:17:02.679434 WARNING: region 7:
9579 22:17:02.683029 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9580 22:17:02.689661 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9581 22:17:02.692847 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9582 22:17:02.695849 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9583 22:17:02.702600 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9584 22:17:02.706269 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9585 22:17:02.712933 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9586 22:17:02.716172 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9587 22:17:02.719168 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9588 22:17:02.726569 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9589 22:17:02.729386 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9590 22:17:02.732744 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9591 22:17:02.739347 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9592 22:17:02.742754 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9593 22:17:02.749328 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9594 22:17:02.752858 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9595 22:17:02.755995 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9596 22:17:02.762018 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9597 22:17:02.766392 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9598 22:17:02.771785 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9599 22:17:02.775489 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9600 22:17:02.779238 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9601 22:17:02.785592 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9602 22:17:02.789417 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9603 22:17:02.792058 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9604 22:17:02.798845 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9605 22:17:02.802112 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9606 22:17:02.809027 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9607 22:17:02.811615 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9608 22:17:02.818396 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9609 22:17:02.822310 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9610 22:17:02.825339 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9611 22:17:02.831912 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9612 22:17:02.835713 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9613 22:17:02.838628 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9614 22:17:02.842135 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9615 22:17:02.848256 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9616 22:17:02.852299 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9617 22:17:02.855192 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9618 22:17:02.858206 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9619 22:17:02.864791 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9620 22:17:02.868582 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9621 22:17:02.871974 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9622 22:17:02.875126 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9623 22:17:02.881801 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9624 22:17:02.885116 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9625 22:17:02.888072 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9626 22:17:02.895006 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9627 22:17:02.897963 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9628 22:17:02.901757 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9629 22:17:02.908005 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9630 22:17:02.910922 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9631 22:17:02.918338 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9632 22:17:02.921048 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9633 22:17:02.924534 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9634 22:17:02.930763 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9635 22:17:02.934385 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9636 22:17:02.941077 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9637 22:17:02.944706 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9638 22:17:02.950525 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9639 22:17:02.953881 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9640 22:17:02.957293 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9641 22:17:02.963816 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9642 22:17:02.967014 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9643 22:17:02.973985 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9644 22:17:02.976986 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9645 22:17:02.983513 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9646 22:17:02.986855 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9647 22:17:02.994006 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9648 22:17:02.997034 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9649 22:17:03.000265 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9650 22:17:03.006956 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9651 22:17:03.009699 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9652 22:17:03.017329 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9653 22:17:03.020448 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9654 22:17:03.027553 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9655 22:17:03.030557 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9656 22:17:03.036608 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9657 22:17:03.040246 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9658 22:17:03.043193 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9659 22:17:03.049601 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9660 22:17:03.053262 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9661 22:17:03.060177 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9662 22:17:03.063545 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9663 22:17:03.070153 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9664 22:17:03.073404 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9665 22:17:03.079896 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9666 22:17:03.083373 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9667 22:17:03.086633 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9668 22:17:03.093339 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9669 22:17:03.096548 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9670 22:17:03.103633 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9671 22:17:03.107111 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9672 22:17:03.113314 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9673 22:17:03.116855 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9674 22:17:03.123764 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9675 22:17:03.126685 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9676 22:17:03.129931 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9677 22:17:03.133118 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9678 22:17:03.140041 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9679 22:17:03.143266 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9680 22:17:03.146507 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9681 22:17:03.153593 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9682 22:17:03.156875 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9683 22:17:03.159874 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9684 22:17:03.166535 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9685 22:17:03.169452 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9686 22:17:03.176474 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9687 22:17:03.179771 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9688 22:17:03.183043 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9689 22:17:03.189817 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9690 22:17:03.193309 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9691 22:17:03.199700 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9692 22:17:03.202901 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9693 22:17:03.209718 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9694 22:17:03.212653 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9695 22:17:03.216383 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9696 22:17:03.219623 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9697 22:17:03.225942 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9698 22:17:03.229530 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9699 22:17:03.233292 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9700 22:17:03.239676 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9701 22:17:03.242707 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9702 22:17:03.246030 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9703 22:17:03.249376 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9704 22:17:03.256249 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9705 22:17:03.259426 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9706 22:17:03.265894 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9707 22:17:03.269678 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9708 22:17:03.272279 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9709 22:17:03.278638 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9710 22:17:03.282395 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9711 22:17:03.288989 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9712 22:17:03.292223 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9713 22:17:03.295922 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9714 22:17:03.302681 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9715 22:17:03.305687 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9716 22:17:03.312228 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9717 22:17:03.315816 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9718 22:17:03.319473 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9719 22:17:03.326230 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9720 22:17:03.329227 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9721 22:17:03.335223 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9722 22:17:03.339236 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9723 22:17:03.342110 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9724 22:17:03.348490 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9725 22:17:03.351968 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9726 22:17:03.358653 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9727 22:17:03.362035 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9728 22:17:03.365047 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9729 22:17:03.371505 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9730 22:17:03.375194 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9731 22:17:03.378552 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9732 22:17:03.385151 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9733 22:17:03.388134 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9734 22:17:03.395386 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9735 22:17:03.398235 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9736 22:17:03.401936 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9737 22:17:03.407897 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9738 22:17:03.411631 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9739 22:17:03.418405 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9740 22:17:03.421759 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9741 22:17:03.424637 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9742 22:17:03.432542 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9743 22:17:03.434788 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9744 22:17:03.440767 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9745 22:17:03.444467 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9746 22:17:03.447652 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9747 22:17:03.454682 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9748 22:17:03.457527 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9749 22:17:03.464111 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9750 22:17:03.467604 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9751 22:17:03.471085 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9752 22:17:03.477755 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9753 22:17:03.481004 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9754 22:17:03.487606 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9755 22:17:03.490407 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9756 22:17:03.494412 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9757 22:17:03.500919 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9758 22:17:03.503547 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9759 22:17:03.510725 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9760 22:17:03.513489 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9761 22:17:03.516694 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9762 22:17:03.523374 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9763 22:17:03.526946 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9764 22:17:03.533943 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9765 22:17:03.536332 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9766 22:17:03.540029 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9767 22:17:03.546654 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9768 22:17:03.549983 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9769 22:17:03.556796 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9770 22:17:03.560000 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9771 22:17:03.566334 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9772 22:17:03.569331 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9773 22:17:03.573423 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9774 22:17:03.579796 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9775 22:17:03.583423 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9776 22:17:03.590453 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9777 22:17:03.592951 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9778 22:17:03.599215 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9779 22:17:03.602597 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9780 22:17:03.605890 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9781 22:17:03.612986 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9782 22:17:03.616018 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9783 22:17:03.622503 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9784 22:17:03.625910 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9785 22:17:03.632724 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9786 22:17:03.636018 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9787 22:17:03.638871 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9788 22:17:03.645184 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9789 22:17:03.648640 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9790 22:17:03.655508 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9791 22:17:03.658554 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9792 22:17:03.664869 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9793 22:17:03.668873 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9794 22:17:03.671761 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9795 22:17:03.678895 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9796 22:17:03.681833 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9797 22:17:03.688103 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9798 22:17:03.691694 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9799 22:17:03.698200 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9800 22:17:03.701334 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9801 22:17:03.704331 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9802 22:17:03.711263 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9803 22:17:03.714832 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9804 22:17:03.720935 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9805 22:17:03.724066 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9806 22:17:03.731224 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9807 22:17:03.734471 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9808 22:17:03.737993 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9809 22:17:03.744813 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9810 22:17:03.747512 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9811 22:17:03.751457 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9812 22:17:03.754467 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9813 22:17:03.760642 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9814 22:17:03.764305 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9815 22:17:03.767663 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9816 22:17:03.774021 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9817 22:17:03.777072 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9818 22:17:03.781385 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9819 22:17:03.787596 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9820 22:17:03.790997 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9821 22:17:03.797202 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9822 22:17:03.800581 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9823 22:17:03.803742 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9824 22:17:03.810512 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9825 22:17:03.813307 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9826 22:17:03.816891 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9827 22:17:03.823733 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9828 22:17:03.826784 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9829 22:17:03.830427 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9830 22:17:03.836892 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9831 22:17:03.840159 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9832 22:17:03.846907 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9833 22:17:03.849799 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9834 22:17:03.853339 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9835 22:17:03.859676 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9836 22:17:03.862973 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9837 22:17:03.869802 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9838 22:17:03.873147 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9839 22:17:03.876548 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9840 22:17:03.883694 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9841 22:17:03.886236 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9842 22:17:03.889212 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9843 22:17:03.896230 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9844 22:17:03.899524 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9845 22:17:03.902994 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9846 22:17:03.909949 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9847 22:17:03.912469 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9848 22:17:03.919347 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9849 22:17:03.922494 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9850 22:17:03.925957 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9851 22:17:03.929238 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9852 22:17:03.932519 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9853 22:17:03.939219 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9854 22:17:03.942260 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9855 22:17:03.945867 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9856 22:17:03.949466 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9857 22:17:03.956012 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9858 22:17:03.958813 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9859 22:17:03.962328 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9860 22:17:03.968233 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9861 22:17:03.971680 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9862 22:17:03.975252 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9863 22:17:03.982004 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9864 22:17:03.985155 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9865 22:17:03.992043 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9866 22:17:03.994836 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9867 22:17:04.001887 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9868 22:17:04.004767 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9869 22:17:04.008439 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9870 22:17:04.015186 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9871 22:17:04.018080 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9872 22:17:04.024928 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9873 22:17:04.027857 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9874 22:17:04.031277 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9875 22:17:04.037678 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9876 22:17:04.041437 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9877 22:17:04.047757 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9878 22:17:04.050957 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9879 22:17:04.054548 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9880 22:17:04.061186 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9881 22:17:04.064201 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9882 22:17:04.071322 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9883 22:17:04.074074 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9884 22:17:04.081087 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9885 22:17:04.083865 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9886 22:17:04.087391 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9887 22:17:04.093933 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9888 22:17:04.096785 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9889 22:17:04.103756 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9890 22:17:04.107377 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9891 22:17:04.113695 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9892 22:17:04.117530 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9893 22:17:04.120228 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9894 22:17:04.126537 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9895 22:17:04.130084 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9896 22:17:04.136714 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9897 22:17:04.139831 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9898 22:17:04.143699 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9899 22:17:04.149578 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9900 22:17:04.153111 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9901 22:17:04.159594 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9902 22:17:04.163291 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9903 22:17:04.170009 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9904 22:17:04.172976 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9905 22:17:04.176266 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9906 22:17:04.182658 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9907 22:17:04.185998 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9908 22:17:04.193071 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9909 22:17:04.195954 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9910 22:17:04.198903 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9911 22:17:04.206330 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9912 22:17:04.209686 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9913 22:17:04.216310 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9914 22:17:04.218900 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9915 22:17:04.225754 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9916 22:17:04.228925 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9917 22:17:04.232015 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9918 22:17:04.238901 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9919 22:17:04.242020 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9920 22:17:04.248826 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9921 22:17:04.251830 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9922 22:17:04.258844 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9923 22:17:04.262268 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9924 22:17:04.265227 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9925 22:17:04.271433 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9926 22:17:04.274998 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9927 22:17:04.281989 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9928 22:17:04.284987 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9929 22:17:04.288556 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9930 22:17:04.295220 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9931 22:17:04.298540 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9932 22:17:04.304764 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9933 22:17:04.308186 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9934 22:17:04.315130 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9935 22:17:04.317831 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9936 22:17:04.321191 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9937 22:17:04.327967 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9938 22:17:04.331217 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9939 22:17:04.337823 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9940 22:17:04.340806 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9941 22:17:04.347366 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9942 22:17:04.350915 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9943 22:17:04.357215 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9944 22:17:04.360777 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9945 22:17:04.364498 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9946 22:17:04.370650 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9947 22:17:04.373850 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9948 22:17:04.380764 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9949 22:17:04.384039 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9950 22:17:04.390408 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9951 22:17:04.393599 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9952 22:17:04.400148 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9953 22:17:04.403627 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9954 22:17:04.407241 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9955 22:17:04.413912 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9956 22:17:04.417098 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9957 22:17:04.423387 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9958 22:17:04.426892 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9959 22:17:04.434000 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9960 22:17:04.436869 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9961 22:17:04.443141 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9962 22:17:04.446784 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9963 22:17:04.450184 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9964 22:17:04.456547 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9965 22:17:04.460304 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9966 22:17:04.466667 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9967 22:17:04.469728 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9968 22:17:04.476570 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9969 22:17:04.479910 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9970 22:17:04.486394 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9971 22:17:04.489501 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9972 22:17:04.492726 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9973 22:17:04.499287 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9974 22:17:04.502867 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9975 22:17:04.509945 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9976 22:17:04.513008 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9977 22:17:04.519740 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9978 22:17:04.522712 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9979 22:17:04.526259 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9980 22:17:04.532457 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9981 22:17:04.536022 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9982 22:17:04.542559 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9983 22:17:04.545388 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9984 22:17:04.552483 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9985 22:17:04.555136 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9986 22:17:04.562010 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9987 22:17:04.565567 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9988 22:17:04.568697 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9989 22:17:04.575132 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9990 22:17:04.578882 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9991 22:17:04.585455 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9992 22:17:04.588623 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9993 22:17:04.595564 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9994 22:17:04.598696 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9995 22:17:04.605568 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9996 22:17:04.608741 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9997 22:17:04.615048 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9998 22:17:04.618521 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9999 22:17:04.624962 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
10000 22:17:04.628530 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
10001 22:17:04.635232 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
10002 22:17:04.638574 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
10003 22:17:04.644928 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
10004 22:17:04.648251 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
10005 22:17:04.654351 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
10006 22:17:04.658269 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
10007 22:17:04.664433 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
10008 22:17:04.667703 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
10009 22:17:04.674308 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
10010 22:17:04.678410 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
10011 22:17:04.684638 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
10012 22:17:04.687407 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
10013 22:17:04.694333 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
10014 22:17:04.697373 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
10015 22:17:04.700889 INFO: [APUAPC] vio 0
10016 22:17:04.704170 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
10017 22:17:04.710357 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
10018 22:17:04.714043 INFO: [APUAPC] D0_APC_0: 0x400510
10019 22:17:04.717676 INFO: [APUAPC] D0_APC_1: 0x0
10020 22:17:04.721149 INFO: [APUAPC] D0_APC_2: 0x1540
10021 22:17:04.721698 INFO: [APUAPC] D0_APC_3: 0x0
10022 22:17:04.724275 INFO: [APUAPC] D1_APC_0: 0xffffffff
10023 22:17:04.730606 INFO: [APUAPC] D1_APC_1: 0xffffffff
10024 22:17:04.733813 INFO: [APUAPC] D1_APC_2: 0x3fffff
10025 22:17:04.734362 INFO: [APUAPC] D1_APC_3: 0x0
10026 22:17:04.737099 INFO: [APUAPC] D2_APC_0: 0xffffffff
10027 22:17:04.740712 INFO: [APUAPC] D2_APC_1: 0xffffffff
10028 22:17:04.744174 INFO: [APUAPC] D2_APC_2: 0x3fffff
10029 22:17:04.747123 INFO: [APUAPC] D2_APC_3: 0x0
10030 22:17:04.750297 INFO: [APUAPC] D3_APC_0: 0xffffffff
10031 22:17:04.753365 INFO: [APUAPC] D3_APC_1: 0xffffffff
10032 22:17:04.757006 INFO: [APUAPC] D3_APC_2: 0x3fffff
10033 22:17:04.760062 INFO: [APUAPC] D3_APC_3: 0x0
10034 22:17:04.763672 INFO: [APUAPC] D4_APC_0: 0xffffffff
10035 22:17:04.766640 INFO: [APUAPC] D4_APC_1: 0xffffffff
10036 22:17:04.770269 INFO: [APUAPC] D4_APC_2: 0x3fffff
10037 22:17:04.773295 INFO: [APUAPC] D4_APC_3: 0x0
10038 22:17:04.777497 INFO: [APUAPC] D5_APC_0: 0xffffffff
10039 22:17:04.779873 INFO: [APUAPC] D5_APC_1: 0xffffffff
10040 22:17:04.782840 INFO: [APUAPC] D5_APC_2: 0x3fffff
10041 22:17:04.786411 INFO: [APUAPC] D5_APC_3: 0x0
10042 22:17:04.790115 INFO: [APUAPC] D6_APC_0: 0xffffffff
10043 22:17:04.792979 INFO: [APUAPC] D6_APC_1: 0xffffffff
10044 22:17:04.796408 INFO: [APUAPC] D6_APC_2: 0x3fffff
10045 22:17:04.799185 INFO: [APUAPC] D6_APC_3: 0x0
10046 22:17:04.803042 INFO: [APUAPC] D7_APC_0: 0xffffffff
10047 22:17:04.806653 INFO: [APUAPC] D7_APC_1: 0xffffffff
10048 22:17:04.809768 INFO: [APUAPC] D7_APC_2: 0x3fffff
10049 22:17:04.813454 INFO: [APUAPC] D7_APC_3: 0x0
10050 22:17:04.816289 INFO: [APUAPC] D8_APC_0: 0xffffffff
10051 22:17:04.819741 INFO: [APUAPC] D8_APC_1: 0xffffffff
10052 22:17:04.823039 INFO: [APUAPC] D8_APC_2: 0x3fffff
10053 22:17:04.826055 INFO: [APUAPC] D8_APC_3: 0x0
10054 22:17:04.829397 INFO: [APUAPC] D9_APC_0: 0xffffffff
10055 22:17:04.832724 INFO: [APUAPC] D9_APC_1: 0xffffffff
10056 22:17:04.835965 INFO: [APUAPC] D9_APC_2: 0x3fffff
10057 22:17:04.839209 INFO: [APUAPC] D9_APC_3: 0x0
10058 22:17:04.842742 INFO: [APUAPC] D10_APC_0: 0xffffffff
10059 22:17:04.845521 INFO: [APUAPC] D10_APC_1: 0xffffffff
10060 22:17:04.849209 INFO: [APUAPC] D10_APC_2: 0x3fffff
10061 22:17:04.852010 INFO: [APUAPC] D10_APC_3: 0x0
10062 22:17:04.855701 INFO: [APUAPC] D11_APC_0: 0xffffffff
10063 22:17:04.858911 INFO: [APUAPC] D11_APC_1: 0xffffffff
10064 22:17:04.862993 INFO: [APUAPC] D11_APC_2: 0x3fffff
10065 22:17:04.865412 INFO: [APUAPC] D11_APC_3: 0x0
10066 22:17:04.869009 INFO: [APUAPC] D12_APC_0: 0xffffffff
10067 22:17:04.872483 INFO: [APUAPC] D12_APC_1: 0xffffffff
10068 22:17:04.875225 INFO: [APUAPC] D12_APC_2: 0x3fffff
10069 22:17:04.878656 INFO: [APUAPC] D12_APC_3: 0x0
10070 22:17:04.881963 INFO: [APUAPC] D13_APC_0: 0xffffffff
10071 22:17:04.885262 INFO: [APUAPC] D13_APC_1: 0xffffffff
10072 22:17:04.888472 INFO: [APUAPC] D13_APC_2: 0x3fffff
10073 22:17:04.892243 INFO: [APUAPC] D13_APC_3: 0x0
10074 22:17:04.895412 INFO: [APUAPC] D14_APC_0: 0xffffffff
10075 22:17:04.898986 INFO: [APUAPC] D14_APC_1: 0xffffffff
10076 22:17:04.901734 INFO: [APUAPC] D14_APC_2: 0x3fffff
10077 22:17:04.905838 INFO: [APUAPC] D14_APC_3: 0x0
10078 22:17:04.908599 INFO: [APUAPC] D15_APC_0: 0xffffffff
10079 22:17:04.911435 INFO: [APUAPC] D15_APC_1: 0xffffffff
10080 22:17:04.916000 INFO: [APUAPC] D15_APC_2: 0x3fffff
10081 22:17:04.918769 INFO: [APUAPC] D15_APC_3: 0x0
10082 22:17:04.921870 INFO: [APUAPC] APC_CON: 0x4
10083 22:17:04.925455 INFO: [NOCDAPC] D0_APC_0: 0x0
10084 22:17:04.929352 INFO: [NOCDAPC] D0_APC_1: 0x0
10085 22:17:04.931952 INFO: [NOCDAPC] D1_APC_0: 0x0
10086 22:17:04.934934 INFO: [NOCDAPC] D1_APC_1: 0xfff
10087 22:17:04.938609 INFO: [NOCDAPC] D2_APC_0: 0x0
10088 22:17:04.942343 INFO: [NOCDAPC] D2_APC_1: 0xfff
10089 22:17:04.942896 INFO: [NOCDAPC] D3_APC_0: 0x0
10090 22:17:04.944905 INFO: [NOCDAPC] D3_APC_1: 0xfff
10091 22:17:04.948485 INFO: [NOCDAPC] D4_APC_0: 0x0
10092 22:17:04.951920 INFO: [NOCDAPC] D4_APC_1: 0xfff
10093 22:17:04.955500 INFO: [NOCDAPC] D5_APC_0: 0x0
10094 22:17:04.958316 INFO: [NOCDAPC] D5_APC_1: 0xfff
10095 22:17:04.961722 INFO: [NOCDAPC] D6_APC_0: 0x0
10096 22:17:04.964620 INFO: [NOCDAPC] D6_APC_1: 0xfff
10097 22:17:04.968235 INFO: [NOCDAPC] D7_APC_0: 0x0
10098 22:17:04.971537 INFO: [NOCDAPC] D7_APC_1: 0xfff
10099 22:17:04.972102 INFO: [NOCDAPC] D8_APC_0: 0x0
10100 22:17:04.974763 INFO: [NOCDAPC] D8_APC_1: 0xfff
10101 22:17:04.978242 INFO: [NOCDAPC] D9_APC_0: 0x0
10102 22:17:04.982077 INFO: [NOCDAPC] D9_APC_1: 0xfff
10103 22:17:04.985242 INFO: [NOCDAPC] D10_APC_0: 0x0
10104 22:17:04.987775 INFO: [NOCDAPC] D10_APC_1: 0xfff
10105 22:17:04.991395 INFO: [NOCDAPC] D11_APC_0: 0x0
10106 22:17:04.994637 INFO: [NOCDAPC] D11_APC_1: 0xfff
10107 22:17:04.997973 INFO: [NOCDAPC] D12_APC_0: 0x0
10108 22:17:05.001643 INFO: [NOCDAPC] D12_APC_1: 0xfff
10109 22:17:05.004717 INFO: [NOCDAPC] D13_APC_0: 0x0
10110 22:17:05.007546 INFO: [NOCDAPC] D13_APC_1: 0xfff
10111 22:17:05.011041 INFO: [NOCDAPC] D14_APC_0: 0x0
10112 22:17:05.014906 INFO: [NOCDAPC] D14_APC_1: 0xfff
10113 22:17:05.017397 INFO: [NOCDAPC] D15_APC_0: 0x0
10114 22:17:05.021405 INFO: [NOCDAPC] D15_APC_1: 0xfff
10115 22:17:05.021983 INFO: [NOCDAPC] APC_CON: 0x4
10116 22:17:05.024196 INFO: [APUAPC] set_apusys_apc done
10117 22:17:05.027674 INFO: [DEVAPC] devapc_init done
10118 22:17:05.034389 INFO: GICv3 without legacy support detected.
10119 22:17:05.037625 INFO: ARM GICv3 driver initialized in EL3
10120 22:17:05.041098 INFO: Maximum SPI INTID supported: 639
10121 22:17:05.044303 INFO: BL31: Initializing runtime services
10122 22:17:05.050997 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10123 22:17:05.054077 INFO: SPM: enable CPC mode
10124 22:17:05.057725 INFO: mcdi ready for mcusys-off-idle and system suspend
10125 22:17:05.064295 INFO: BL31: Preparing for EL3 exit to normal world
10126 22:17:05.067281 INFO: Entry point address = 0x80000000
10127 22:17:05.067841 INFO: SPSR = 0x8
10128 22:17:05.074641
10129 22:17:05.075288
10130 22:17:05.075728
10131 22:17:05.077276 Starting depthcharge on Spherion...
10132 22:17:05.077745
10133 22:17:05.078103 Wipe memory regions:
10134 22:17:05.078435
10135 22:17:05.081265 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10136 22:17:05.081865 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10137 22:17:05.082328 Setting prompt string to ['asurada:']
10138 22:17:05.082772 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10139 22:17:05.083534 [0x00000040000000, 0x00000054600000)
10140 22:17:05.203596
10141 22:17:05.204164 [0x00000054660000, 0x00000080000000)
10142 22:17:05.463989
10143 22:17:05.464551 [0x000000821a7280, 0x000000ffe64000)
10144 22:17:06.209461
10145 22:17:06.210045 [0x00000100000000, 0x00000240000000)
10146 22:17:08.099346
10147 22:17:08.102311 Initializing XHCI USB controller at 0x11200000.
10148 22:17:09.084182
10149 22:17:09.084743 R8152: Initializing
10150 22:17:09.085109
10151 22:17:09.087888 Version 9 (ocp_data = 6010)
10152 22:17:09.088519
10153 22:17:09.090893 R8152: Done initializing
10154 22:17:09.091500
10155 22:17:09.091892 Adding net device
10156 22:17:09.611974
10157 22:17:09.615081 [firmware-asurada-13885.B-collabora] Dec 14 2021 15:21:43
10158 22:17:09.615515
10159 22:17:09.615843
10160 22:17:09.616148
10161 22:17:09.616866 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10163 22:17:09.718061 asurada: tftpboot 192.168.201.1 10583911/tftp-deploy-_wzpf10d/kernel/image.itb 10583911/tftp-deploy-_wzpf10d/kernel/cmdline
10164 22:17:09.718743 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10165 22:17:09.719215 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:20)
10166 22:17:09.724145 tftpboot 192.168.201.1 10583911/tftp-deploy-_wzpf10d/kernel/image.itp-deploy-_wzpf10d/kernel/cmdline
10167 22:17:09.724633
10168 22:17:09.724994 Waiting for link
10169 22:17:09.926212
10170 22:17:09.926793 done.
10171 22:17:09.927341
10172 22:17:09.927668 MAC: f4:f5:e8:50:de:0a
10173 22:17:09.927970
10174 22:17:09.929174 Sending DHCP discover... done.
10175 22:17:09.929589
10176 22:17:09.932875 Waiting for reply... done.
10177 22:17:09.933339
10178 22:17:09.936354 Sending DHCP request... done.
10179 22:17:09.936767
10180 22:17:09.937091 Waiting for reply... done.
10181 22:17:09.937392
10182 22:17:09.939546 My ip is 192.168.201.14
10183 22:17:09.939957
10184 22:17:09.942260 The DHCP server ip is 192.168.201.1
10185 22:17:09.942490
10186 22:17:09.945542 TFTP server IP predefined by user: 192.168.201.1
10187 22:17:09.945624
10188 22:17:09.952647 Bootfile predefined by user: 10583911/tftp-deploy-_wzpf10d/kernel/image.itb
10189 22:17:09.952733
10190 22:17:09.955431 Sending tftp read request... done.
10191 22:17:09.955516
10192 22:17:09.959019 Waiting for the transfer...
10193 22:17:09.959121
10194 22:17:10.207832 00000000 ################################################################
10195 22:17:10.207968
10196 22:17:10.433177 00080000 ################################################################
10197 22:17:10.433305
10198 22:17:10.655949 00100000 ################################################################
10199 22:17:10.656120
10200 22:17:10.879969 00180000 ################################################################
10201 22:17:10.880104
10202 22:17:11.104825 00200000 ################################################################
10203 22:17:11.104956
10204 22:17:11.329687 00280000 ################################################################
10205 22:17:11.329829
10206 22:17:11.555018 00300000 ################################################################
10207 22:17:11.555186
10208 22:17:11.780996 00380000 ################################################################
10209 22:17:11.781133
10210 22:17:12.007482 00400000 ################################################################
10211 22:17:12.007617
10212 22:17:12.233434 00480000 ################################################################
10213 22:17:12.233565
10214 22:17:12.458599 00500000 ################################################################
10215 22:17:12.458750
10216 22:17:12.684780 00580000 ################################################################
10217 22:17:12.684916
10218 22:17:12.910606 00600000 ################################################################
10219 22:17:12.910744
10220 22:17:13.136647 00680000 ################################################################
10221 22:17:13.136786
10222 22:17:13.365996 00700000 ################################################################
10223 22:17:13.366139
10224 22:17:13.592415 00780000 ################################################################
10225 22:17:13.592552
10226 22:17:13.816768 00800000 ################################################################
10227 22:17:13.816901
10228 22:17:14.041728 00880000 ################################################################
10229 22:17:14.041866
10230 22:17:14.290935 00900000 ################################################################
10231 22:17:14.291114
10232 22:17:14.517047 00980000 ################################################################
10233 22:17:14.517188
10234 22:17:14.749945 00a00000 ################################################################
10235 22:17:14.750089
10236 22:17:15.020335 00a80000 ################################################################
10237 22:17:15.020474
10238 22:17:15.272927 00b00000 ################################################################
10239 22:17:15.273069
10240 22:17:15.499290 00b80000 ################################################################
10241 22:17:15.499420
10242 22:17:15.725419 00c00000 ################################################################
10243 22:17:15.725552
10244 22:17:15.952343 00c80000 ################################################################
10245 22:17:15.952482
10246 22:17:16.178275 00d00000 ################################################################
10247 22:17:16.178413
10248 22:17:16.404931 00d80000 ################################################################
10249 22:17:16.405066
10250 22:17:16.631738 00e00000 ################################################################
10251 22:17:16.631874
10252 22:17:16.857286 00e80000 ################################################################
10253 22:17:16.857423
10254 22:17:17.083669 00f00000 ################################################################
10255 22:17:17.083815
10256 22:17:17.310214 00f80000 ################################################################
10257 22:17:17.310352
10258 22:17:17.536628 01000000 ################################################################
10259 22:17:17.536763
10260 22:17:17.804066 01080000 ################################################################
10261 22:17:17.804203
10262 22:17:18.075009 01100000 ################################################################
10263 22:17:18.075204
10264 22:17:18.346029 01180000 ################################################################
10265 22:17:18.346169
10266 22:17:18.580086 01200000 ################################################################
10267 22:17:18.580228
10268 22:17:18.805441 01280000 ################################################################
10269 22:17:18.805614
10270 22:17:19.031253 01300000 ################################################################
10271 22:17:19.031392
10272 22:17:19.257463 01380000 ################################################################
10273 22:17:19.257601
10274 22:17:19.492593 01400000 ################################################################
10275 22:17:19.492727
10276 22:17:19.739312 01480000 ################################################################
10277 22:17:19.739470
10278 22:17:19.973401 01500000 ################################################################
10279 22:17:19.973548
10280 22:17:20.212743 01580000 ################################################################
10281 22:17:20.212887
10282 22:17:20.437814 01600000 ################################################################
10283 22:17:20.437952
10284 22:17:20.663857 01680000 ################################################################
10285 22:17:20.663990
10286 22:17:20.889641 01700000 ################################################################
10287 22:17:20.889773
10288 22:17:21.115655 01780000 ################################################################
10289 22:17:21.115794
10290 22:17:21.355419 01800000 ################################################################
10291 22:17:21.355566
10292 22:17:21.581168 01880000 ################################################################
10293 22:17:21.581306
10294 22:17:21.809029 01900000 ################################################################
10295 22:17:21.809166
10296 22:17:22.036557 01980000 ################################################################
10297 22:17:22.036700
10298 22:17:22.262590 01a00000 ################################################################
10299 22:17:22.262728
10300 22:17:22.489694 01a80000 ################################################################
10301 22:17:22.489830
10302 22:17:22.672941 01b00000 ##################################################### done.
10303 22:17:22.673094
10304 22:17:22.675796 The bootfile was 28738362 bytes long.
10305 22:17:22.675875
10306 22:17:22.679288 Sending tftp read request... done.
10307 22:17:22.679367
10308 22:17:22.682929 Waiting for the transfer...
10309 22:17:22.683016
10310 22:17:22.683095 00000000 # done.
10311 22:17:22.683164
10312 22:17:22.689248 Command line loaded dynamically from TFTP file: 10583911/tftp-deploy-_wzpf10d/kernel/cmdline
10313 22:17:22.689340
10314 22:17:22.708741 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10583911/extract-nfsrootfs-av2vgxp6,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10315 22:17:22.708832
10316 22:17:22.712265 Loading FIT.
10317 22:17:22.712357
10318 22:17:22.715160 Image ramdisk-1 has 18607675 bytes.
10319 22:17:22.715251
10320 22:17:22.715334 Image fdt-1 has 46924 bytes.
10321 22:17:22.719041
10322 22:17:22.719190 Image kernel-1 has 10081729 bytes.
10323 22:17:22.719305
10324 22:17:22.728509 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10325 22:17:22.728666
10326 22:17:22.744845 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10327 22:17:22.748308
10328 22:17:22.752429 Choosing best match conf-1 for compat google,spherion-rev2.
10329 22:17:22.756488
10330 22:17:22.760524 Connected to device vid:did:rid of 1ae0:0028:00
10331 22:17:22.768202
10332 22:17:22.771383 tpm_get_response: command 0x17b, return code 0x0
10333 22:17:22.771844
10334 22:17:22.774458 ec_init: CrosEC protocol v3 supported (256, 248)
10335 22:17:22.778603
10336 22:17:22.782319 tpm_cleanup: add release locality here.
10337 22:17:22.782732
10338 22:17:22.783055 Shutting down all USB controllers.
10339 22:17:22.785289
10340 22:17:22.785721 Removing current net device
10341 22:17:22.786048
10342 22:17:22.791696 Exiting depthcharge with code 4 at timestamp: 47126532
10343 22:17:22.792186
10344 22:17:22.795692 LZMA decompressing kernel-1 to 0x821a6718
10345 22:17:22.796208
10346 22:17:22.798664 LZMA decompressing kernel-1 to 0x40000000
10347 22:17:24.067171
10348 22:17:24.067721 jumping to kernel
10349 22:17:24.069148 end: 2.2.4 bootloader-commands (duration 00:00:19) [common]
10350 22:17:24.069649 start: 2.2.5 auto-login-action (timeout 00:04:06) [common]
10351 22:17:24.070046 Setting prompt string to ['Linux version [0-9]']
10352 22:17:24.070407 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10353 22:17:24.070766 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10354 22:17:24.148662
10355 22:17:24.151569 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10356 22:17:24.155903 start: 2.2.5.1 login-action (timeout 00:04:06) [common]
10357 22:17:24.156457 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10358 22:17:24.156913 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10359 22:17:24.157308 Using line separator: #'\n'#
10360 22:17:24.157707 No login prompt set.
10361 22:17:24.158060 Parsing kernel messages
10362 22:17:24.158367 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10363 22:17:24.158918 [login-action] Waiting for messages, (timeout 00:04:06)
10364 22:17:24.174455 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j1606555-arm64-gcc-10-defconfig-arm64-chromebook-vtq55) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sun Jun 4 21:56:05 UTC 2023
10365 22:17:24.177536 [ 0.000000] random: crng init done
10366 22:17:24.184269 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10367 22:17:24.184829 [ 0.000000] efi: UEFI not found.
10368 22:17:24.194433 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10369 22:17:24.200810 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10370 22:17:24.211275 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10371 22:17:24.220892 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10372 22:17:24.227464 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10373 22:17:24.233985 [ 0.000000] printk: bootconsole [mtk8250] enabled
10374 22:17:24.240409 [ 0.000000] NUMA: No NUMA configuration found
10375 22:17:24.247413 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10376 22:17:24.250573 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcda00-0x23efcffff]
10377 22:17:24.253713 [ 0.000000] Zone ranges:
10378 22:17:24.261077 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10379 22:17:24.263989 [ 0.000000] DMA32 empty
10380 22:17:24.270148 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10381 22:17:24.273962 [ 0.000000] Movable zone start for each node
10382 22:17:24.277293 [ 0.000000] Early memory node ranges
10383 22:17:24.283209 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10384 22:17:24.289910 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10385 22:17:24.296671 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10386 22:17:24.303246 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10387 22:17:24.310180 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10388 22:17:24.315996 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10389 22:17:24.372590 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10390 22:17:24.378958 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10391 22:17:24.385418 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10392 22:17:24.389398 [ 0.000000] psci: probing for conduit method from DT.
10393 22:17:24.395887 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10394 22:17:24.398649 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10395 22:17:24.405536 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10396 22:17:24.408715 [ 0.000000] psci: SMC Calling Convention v1.2
10397 22:17:24.415496 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10398 22:17:24.419047 [ 0.000000] Detected VIPT I-cache on CPU0
10399 22:17:24.425002 [ 0.000000] CPU features: detected: GIC system register CPU interface
10400 22:17:24.431628 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10401 22:17:24.438529 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10402 22:17:24.444661 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10403 22:17:24.454728 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10404 22:17:24.461828 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10405 22:17:24.464581 [ 0.000000] alternatives: applying boot alternatives
10406 22:17:24.471220 [ 0.000000] Fallback order for Node 0: 0
10407 22:17:24.477887 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10408 22:17:24.481247 [ 0.000000] Policy zone: Normal
10409 22:17:24.500933 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10583911/extract-nfsrootfs-av2vgxp6,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10410 22:17:24.510733 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10411 22:17:24.522739 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10412 22:17:24.532955 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10413 22:17:24.539781 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10414 22:17:24.542686 <6>[ 0.000000] software IO TLB: area num 8.
10415 22:17:24.599576 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10416 22:17:24.749144 <6>[ 0.000000] Memory: 7954772K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 397996K reserved, 32768K cma-reserved)
10417 22:17:24.755616 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10418 22:17:24.762112 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10419 22:17:24.765379 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10420 22:17:24.772280 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10421 22:17:24.778599 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10422 22:17:24.781681 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10423 22:17:24.792094 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10424 22:17:24.798647 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10425 22:17:24.805009 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10426 22:17:24.811495 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10427 22:17:24.815399 <6>[ 0.000000] GICv3: 608 SPIs implemented
10428 22:17:24.818173 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10429 22:17:24.824859 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10430 22:17:24.827976 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10431 22:17:24.834614 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10432 22:17:24.847582 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10433 22:17:24.861106 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10434 22:17:24.867717 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10435 22:17:24.875531 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10436 22:17:24.889557 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10437 22:17:24.895310 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10438 22:17:24.902211 <6>[ 0.009181] Console: colour dummy device 80x25
10439 22:17:24.912486 <6>[ 0.013910] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10440 22:17:24.918282 <6>[ 0.024351] pid_max: default: 32768 minimum: 301
10441 22:17:24.922572 <6>[ 0.029225] LSM: Security Framework initializing
10442 22:17:24.928202 <6>[ 0.034164] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10443 22:17:24.938636 <6>[ 0.041977] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10444 22:17:24.948241 <6>[ 0.051462] cblist_init_generic: Setting adjustable number of callback queues.
10445 22:17:24.952037 <6>[ 0.058914] cblist_init_generic: Setting shift to 3 and lim to 1.
10446 22:17:24.958845 <6>[ 0.065253] cblist_init_generic: Setting shift to 3 and lim to 1.
10447 22:17:24.964349 <6>[ 0.071661] rcu: Hierarchical SRCU implementation.
10448 22:17:24.971271 <6>[ 0.076674] rcu: Max phase no-delay instances is 1000.
10449 22:17:24.977800 <6>[ 0.083726] EFI services will not be available.
10450 22:17:24.981016 <6>[ 0.088701] smp: Bringing up secondary CPUs ...
10451 22:17:24.990247 <6>[ 0.093782] Detected VIPT I-cache on CPU1
10452 22:17:24.995976 <6>[ 0.093858] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10453 22:17:25.002567 <6>[ 0.093888] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10454 22:17:25.005307 <6>[ 0.094222] Detected VIPT I-cache on CPU2
10455 22:17:25.012404 <6>[ 0.094272] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10456 22:17:25.022026 <6>[ 0.094288] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10457 22:17:25.024870 <6>[ 0.094549] Detected VIPT I-cache on CPU3
10458 22:17:25.031816 <6>[ 0.094596] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10459 22:17:25.037959 <6>[ 0.094609] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10460 22:17:25.041383 <6>[ 0.094920] CPU features: detected: Spectre-v4
10461 22:17:25.048459 <6>[ 0.094926] CPU features: detected: Spectre-BHB
10462 22:17:25.051513 <6>[ 0.094931] Detected PIPT I-cache on CPU4
10463 22:17:25.058209 <6>[ 0.094989] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10464 22:17:25.064409 <6>[ 0.095005] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10465 22:17:25.071257 <6>[ 0.095306] Detected PIPT I-cache on CPU5
10466 22:17:25.078353 <6>[ 0.095367] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10467 22:17:25.084258 <6>[ 0.095384] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10468 22:17:25.088184 <6>[ 0.095666] Detected PIPT I-cache on CPU6
10469 22:17:25.094624 <6>[ 0.095732] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10470 22:17:25.101570 <6>[ 0.095748] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10471 22:17:25.107934 <6>[ 0.096045] Detected PIPT I-cache on CPU7
10472 22:17:25.114225 <6>[ 0.096109] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10473 22:17:25.121493 <6>[ 0.096126] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10474 22:17:25.123924 <6>[ 0.096173] smp: Brought up 1 node, 8 CPUs
10475 22:17:25.130768 <6>[ 0.237437] SMP: Total of 8 processors activated.
10476 22:17:25.134073 <6>[ 0.242358] CPU features: detected: 32-bit EL0 Support
10477 22:17:25.144268 <6>[ 0.247754] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10478 22:17:25.150835 <6>[ 0.256553] CPU features: detected: Common not Private translations
10479 22:17:25.157236 <6>[ 0.263028] CPU features: detected: CRC32 instructions
10480 22:17:25.163623 <6>[ 0.268413] CPU features: detected: RCpc load-acquire (LDAPR)
10481 22:17:25.167246 <6>[ 0.274372] CPU features: detected: LSE atomic instructions
10482 22:17:25.173638 <6>[ 0.280153] CPU features: detected: Privileged Access Never
10483 22:17:25.180079 <6>[ 0.285969] CPU features: detected: RAS Extension Support
10484 22:17:25.186295 <6>[ 0.291577] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10485 22:17:25.189983 <6>[ 0.298796] CPU: All CPU(s) started at EL2
10486 22:17:25.196835 <6>[ 0.303139] alternatives: applying system-wide alternatives
10487 22:17:25.206895 <6>[ 0.313886] devtmpfs: initialized
10488 22:17:25.219148 <6>[ 0.322799] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10489 22:17:25.228989 <6>[ 0.332764] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10490 22:17:25.235484 <6>[ 0.340510] pinctrl core: initialized pinctrl subsystem
10491 22:17:25.238630 <6>[ 0.347154] DMI not present or invalid.
10492 22:17:25.244876 <6>[ 0.351577] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10493 22:17:25.255015 <6>[ 0.358479] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10494 22:17:25.261829 <6>[ 0.366068] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10495 22:17:25.271481 <6>[ 0.374283] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10496 22:17:25.274766 <6>[ 0.382534] audit: initializing netlink subsys (disabled)
10497 22:17:25.285309 <5>[ 0.388233] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10498 22:17:25.291460 <6>[ 0.388945] thermal_sys: Registered thermal governor 'step_wise'
10499 22:17:25.297920 <6>[ 0.396199] thermal_sys: Registered thermal governor 'power_allocator'
10500 22:17:25.301189 <6>[ 0.402455] cpuidle: using governor menu
10501 22:17:25.307703 <6>[ 0.413423] NET: Registered PF_QIPCRTR protocol family
10502 22:17:25.314515 <6>[ 0.418951] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10503 22:17:25.321086 <6>[ 0.426055] ASID allocator initialised with 32768 entries
10504 22:17:25.324566 <6>[ 0.432643] Serial: AMBA PL011 UART driver
10505 22:17:25.334296 <4>[ 0.441369] Trying to register duplicate clock ID: 134
10506 22:17:25.390488 <6>[ 0.500981] KASLR enabled
10507 22:17:25.404475 <6>[ 0.508693] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10508 22:17:25.411544 <6>[ 0.515708] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10509 22:17:25.418007 <6>[ 0.522198] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10510 22:17:25.424377 <6>[ 0.529202] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10511 22:17:25.431115 <6>[ 0.535687] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10512 22:17:25.438110 <6>[ 0.542693] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10513 22:17:25.444408 <6>[ 0.549183] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10514 22:17:25.450669 <6>[ 0.556189] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10515 22:17:25.454100 <6>[ 0.563678] ACPI: Interpreter disabled.
10516 22:17:25.463416 <6>[ 0.570078] iommu: Default domain type: Translated
10517 22:17:25.469701 <6>[ 0.575218] iommu: DMA domain TLB invalidation policy: strict mode
10518 22:17:25.473270 <5>[ 0.581875] SCSI subsystem initialized
10519 22:17:25.479245 <6>[ 0.586115] usbcore: registered new interface driver usbfs
10520 22:17:25.486148 <6>[ 0.591845] usbcore: registered new interface driver hub
10521 22:17:25.489425 <6>[ 0.597398] usbcore: registered new device driver usb
10522 22:17:25.496456 <6>[ 0.603506] pps_core: LinuxPPS API ver. 1 registered
10523 22:17:25.506103 <6>[ 0.608699] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10524 22:17:25.509270 <6>[ 0.618044] PTP clock support registered
10525 22:17:25.512498 <6>[ 0.622284] EDAC MC: Ver: 3.0.0
10526 22:17:25.520442 <6>[ 0.627468] FPGA manager framework
10527 22:17:25.523702 <6>[ 0.631146] Advanced Linux Sound Architecture Driver Initialized.
10528 22:17:25.527185 <6>[ 0.637915] vgaarb: loaded
10529 22:17:25.534184 <6>[ 0.641092] clocksource: Switched to clocksource arch_sys_counter
10530 22:17:25.540806 <5>[ 0.647544] VFS: Disk quotas dquot_6.6.0
10531 22:17:25.546992 <6>[ 0.651728] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10532 22:17:25.550257 <6>[ 0.658905] pnp: PnP ACPI: disabled
10533 22:17:25.558232 <6>[ 0.665601] NET: Registered PF_INET protocol family
10534 22:17:25.567947 <6>[ 0.671180] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10535 22:17:25.579931 <6>[ 0.683480] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10536 22:17:25.590008 <6>[ 0.692293] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10537 22:17:25.595803 <6>[ 0.700264] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10538 22:17:25.605995 <6>[ 0.708921] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10539 22:17:25.612776 <6>[ 0.718666] TCP: Hash tables configured (established 65536 bind 65536)
10540 22:17:25.619206 <6>[ 0.725526] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10541 22:17:25.629055 <6>[ 0.732725] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10542 22:17:25.635551 <6>[ 0.740429] NET: Registered PF_UNIX/PF_LOCAL protocol family
10543 22:17:25.642024 <6>[ 0.746593] RPC: Registered named UNIX socket transport module.
10544 22:17:25.644997 <6>[ 0.752746] RPC: Registered udp transport module.
10545 22:17:25.652282 <6>[ 0.757680] RPC: Registered tcp transport module.
10546 22:17:25.658606 <6>[ 0.762614] RPC: Registered tcp NFSv4.1 backchannel transport module.
10547 22:17:25.661855 <6>[ 0.769287] PCI: CLS 0 bytes, default 64
10548 22:17:25.664580 <6>[ 0.773680] Unpacking initramfs...
10549 22:17:25.674902 <6>[ 0.777766] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10550 22:17:25.681355 <6>[ 0.786407] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10551 22:17:25.688061 <6>[ 0.795238] kvm [1]: IPA Size Limit: 40 bits
10552 22:17:25.691153 <6>[ 0.799762] kvm [1]: GICv3: no GICV resource entry
10553 22:17:25.697335 <6>[ 0.804788] kvm [1]: disabling GICv2 emulation
10554 22:17:25.704654 <6>[ 0.809473] kvm [1]: GIC system register CPU interface enabled
10555 22:17:25.707721 <6>[ 0.815644] kvm [1]: vgic interrupt IRQ18
10556 22:17:25.714452 <6>[ 0.819999] kvm [1]: VHE mode initialized successfully
10557 22:17:25.717689 <5>[ 0.826383] Initialise system trusted keyrings
10558 22:17:25.724276 <6>[ 0.831171] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10559 22:17:25.734198 <6>[ 0.841415] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10560 22:17:25.740785 <5>[ 0.847784] NFS: Registering the id_resolver key type
10561 22:17:25.743868 <5>[ 0.853093] Key type id_resolver registered
10562 22:17:25.750657 <5>[ 0.857508] Key type id_legacy registered
10563 22:17:25.757240 <6>[ 0.861805] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10564 22:17:25.764304 <6>[ 0.868725] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10565 22:17:25.769832 <6>[ 0.876474] 9p: Installing v9fs 9p2000 file system support
10566 22:17:25.807279 <5>[ 0.915064] Key type asymmetric registered
10567 22:17:25.811155 <5>[ 0.919396] Asymmetric key parser 'x509' registered
10568 22:17:25.820450 <6>[ 0.924543] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10569 22:17:25.823931 <6>[ 0.932156] io scheduler mq-deadline registered
10570 22:17:25.827049 <6>[ 0.936918] io scheduler kyber registered
10571 22:17:25.846748 <6>[ 0.953839] EINJ: ACPI disabled.
10572 22:17:25.878657 <4>[ 0.979452] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10573 22:17:25.888577 <4>[ 0.990085] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10574 22:17:25.907040 <6>[ 1.010998] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10575 22:17:25.910190 <6>[ 1.019111] printk: console [ttyS0] disabled
10576 22:17:25.939786 <6>[ 1.043755] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10577 22:17:25.946455 <6>[ 1.053237] printk: console [ttyS0] enabled
10578 22:17:25.949907 <6>[ 1.053237] printk: console [ttyS0] enabled
10579 22:17:25.956499 <6>[ 1.062133] printk: bootconsole [mtk8250] disabled
10580 22:17:25.959644 <6>[ 1.062133] printk: bootconsole [mtk8250] disabled
10581 22:17:25.966344 <6>[ 1.073350] SuperH (H)SCI(F) driver initialized
10582 22:17:25.969201 <6>[ 1.078616] msm_serial: driver initialized
10583 22:17:25.983873 <6>[ 1.087506] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10584 22:17:25.993575 <6>[ 1.096053] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10585 22:17:25.999967 <6>[ 1.104595] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10586 22:17:26.010127 <6>[ 1.113224] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10587 22:17:26.019497 <6>[ 1.121932] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10588 22:17:26.026345 <6>[ 1.130653] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10589 22:17:26.036274 <6>[ 1.139196] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10590 22:17:26.042892 <6>[ 1.147996] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10591 22:17:26.052553 <6>[ 1.156540] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10592 22:17:26.064559 <6>[ 1.172007] loop: module loaded
10593 22:17:26.071314 <6>[ 1.178074] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10594 22:17:26.093937 <4>[ 1.201450] mtk-pmic-keys: Failed to locate of_node [id: -1]
10595 22:17:26.100897 <6>[ 1.208263] megasas: 07.719.03.00-rc1
10596 22:17:26.110951 <6>[ 1.217792] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10597 22:17:26.116822 <6>[ 1.224480] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10598 22:17:26.133615 <6>[ 1.240431] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10599 22:17:26.193017 <6>[ 1.293841] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10600 22:17:26.491322 <6>[ 1.598681] Freeing initrd memory: 18168K
10601 22:17:26.502876 <6>[ 1.610159] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10602 22:17:26.513709 <6>[ 1.621144] tun: Universal TUN/TAP device driver, 1.6
10603 22:17:26.517408 <6>[ 1.627195] thunder_xcv, ver 1.0
10604 22:17:26.519917 <6>[ 1.630703] thunder_bgx, ver 1.0
10605 22:17:26.523937 <6>[ 1.634199] nicpf, ver 1.0
10606 22:17:26.534228 <6>[ 1.638201] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10607 22:17:26.537296 <6>[ 1.645675] hns3: Copyright (c) 2017 Huawei Corporation.
10608 22:17:26.543895 <6>[ 1.651260] hclge is initializing
10609 22:17:26.547210 <6>[ 1.654841] e1000: Intel(R) PRO/1000 Network Driver
10610 22:17:26.553946 <6>[ 1.659969] e1000: Copyright (c) 1999-2006 Intel Corporation.
10611 22:17:26.557189 <6>[ 1.665982] e1000e: Intel(R) PRO/1000 Network Driver
10612 22:17:26.563707 <6>[ 1.671197] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10613 22:17:26.570649 <6>[ 1.677387] igb: Intel(R) Gigabit Ethernet Network Driver
10614 22:17:26.577172 <6>[ 1.683037] igb: Copyright (c) 2007-2014 Intel Corporation.
10615 22:17:26.583997 <6>[ 1.688873] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10616 22:17:26.590045 <6>[ 1.695390] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10617 22:17:26.593506 <6>[ 1.701847] sky2: driver version 1.30
10618 22:17:26.600847 <6>[ 1.706836] VFIO - User Level meta-driver version: 0.3
10619 22:17:26.607494 <6>[ 1.714971] usbcore: registered new interface driver usb-storage
10620 22:17:26.614237 <6>[ 1.721421] usbcore: registered new device driver onboard-usb-hub
10621 22:17:26.623040 <6>[ 1.730478] mt6397-rtc mt6359-rtc: registered as rtc0
10622 22:17:26.633118 <6>[ 1.735948] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-04T22:17:26 UTC (1685917046)
10623 22:17:26.636364 <6>[ 1.745543] i2c_dev: i2c /dev entries driver
10624 22:17:26.653375 <6>[ 1.757197] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10625 22:17:26.660332 <6>[ 1.767385] sdhci: Secure Digital Host Controller Interface driver
10626 22:17:26.666591 <6>[ 1.773824] sdhci: Copyright(c) Pierre Ossman
10627 22:17:26.673504 <6>[ 1.779215] Synopsys Designware Multimedia Card Interface Driver
10628 22:17:26.676545 <6>[ 1.785835] mmc0: CQHCI version 5.10
10629 22:17:26.683554 <6>[ 1.786370] sdhci-pltfm: SDHCI platform and OF driver helper
10630 22:17:26.691002 <6>[ 1.797991] ledtrig-cpu: registered to indicate activity on CPUs
10631 22:17:26.701213 <6>[ 1.805425] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10632 22:17:26.707750 <6>[ 1.812824] usbcore: registered new interface driver usbhid
10633 22:17:26.711318 <6>[ 1.818652] usbhid: USB HID core driver
10634 22:17:26.717656 <6>[ 1.822898] spi_master spi0: will run message pump with realtime priority
10635 22:17:26.764904 <6>[ 1.865366] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10636 22:17:26.784169 <6>[ 1.880811] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10637 22:17:26.787235 <6>[ 1.894401] mmc0: Command Queue Engine enabled
10638 22:17:26.793746 <6>[ 1.895897] cros-ec-spi spi0.0: Chrome EC device registered
10639 22:17:26.800562 <6>[ 1.899139] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10640 22:17:26.803873 <6>[ 1.912289] mmcblk0: mmc0:0001 DA4128 116 GiB
10641 22:17:26.817169 <6>[ 1.920965] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10642 22:17:26.823846 <6>[ 1.922228] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10643 22:17:26.830378 <6>[ 1.932381] NET: Registered PF_PACKET protocol family
10644 22:17:26.833481 <6>[ 1.937250] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10645 22:17:26.840182 <6>[ 1.941634] 9pnet: Installing 9P2000 support
10646 22:17:26.842825 <6>[ 1.947431] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10647 22:17:26.850226 <5>[ 1.951305] Key type dns_resolver registered
10648 22:17:26.856364 <6>[ 1.957193] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10649 22:17:26.859941 <6>[ 1.961607] registered taskstats version 1
10650 22:17:26.862993 <5>[ 1.971911] Loading compiled-in X.509 certificates
10651 22:17:26.898885 <4>[ 1.999835] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10652 22:17:26.908876 <4>[ 2.010536] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10653 22:17:26.919284 <3>[ 2.023354] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10654 22:17:26.931209 <6>[ 2.038577] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10655 22:17:26.938647 <6>[ 2.045445] xhci-mtk 11200000.usb: xHCI Host Controller
10656 22:17:26.944635 <6>[ 2.050945] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10657 22:17:26.954646 <6>[ 2.058797] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10658 22:17:26.961394 <6>[ 2.068230] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10659 22:17:26.967760 <6>[ 2.074434] xhci-mtk 11200000.usb: xHCI Host Controller
10660 22:17:26.975277 <6>[ 2.079941] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10661 22:17:26.981129 <6>[ 2.087600] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10662 22:17:26.988201 <6>[ 2.095502] hub 1-0:1.0: USB hub found
10663 22:17:26.991621 <6>[ 2.099537] hub 1-0:1.0: 1 port detected
10664 22:17:27.001590 <6>[ 2.103902] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10665 22:17:27.004958 <6>[ 2.112738] hub 2-0:1.0: USB hub found
10666 22:17:27.007847 <6>[ 2.116768] hub 2-0:1.0: 1 port detected
10667 22:17:27.016613 <6>[ 2.123932] mtk-msdc 11f70000.mmc: Got CD GPIO
10668 22:17:27.034428 <6>[ 2.138232] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10669 22:17:27.040611 <6>[ 2.146264] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10670 22:17:27.050777 <4>[ 2.154243] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10671 22:17:27.060524 <6>[ 2.163904] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10672 22:17:27.067181 <6>[ 2.171987] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10673 22:17:27.077290 <6>[ 2.180022] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10674 22:17:27.083450 <6>[ 2.187937] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10675 22:17:27.090626 <6>[ 2.195758] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10676 22:17:27.100175 <6>[ 2.203578] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10677 22:17:27.110259 <6>[ 2.214364] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10678 22:17:27.120273 <6>[ 2.222752] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10679 22:17:27.127223 <6>[ 2.231096] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10680 22:17:27.137213 <6>[ 2.239438] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10681 22:17:27.143156 <6>[ 2.247782] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10682 22:17:27.153091 <6>[ 2.256129] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10683 22:17:27.159997 <6>[ 2.264473] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10684 22:17:27.169799 <6>[ 2.272814] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10685 22:17:27.176698 <6>[ 2.281158] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10686 22:17:27.186497 <6>[ 2.289500] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10687 22:17:27.193483 <6>[ 2.297843] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10688 22:17:27.203313 <6>[ 2.306185] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10689 22:17:27.209549 <6>[ 2.314528] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10690 22:17:27.219233 <6>[ 2.322873] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10691 22:17:27.226110 <6>[ 2.331227] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10692 22:17:27.232472 <6>[ 2.340150] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10693 22:17:27.239967 <6>[ 2.347587] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10694 22:17:27.247304 <6>[ 2.354611] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10695 22:17:27.257469 <6>[ 2.361698] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10696 22:17:27.264372 <6>[ 2.368964] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10697 22:17:27.274040 <6>[ 2.375912] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10698 22:17:27.280907 <6>[ 2.385057] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10699 22:17:27.290592 <6>[ 2.394184] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10700 22:17:27.300867 <6>[ 2.403485] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10701 22:17:27.311336 <6>[ 2.412959] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10702 22:17:27.320512 <6>[ 2.422433] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10703 22:17:27.326979 <6>[ 2.431559] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10704 22:17:27.336826 <6>[ 2.441033] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10705 22:17:27.346683 <6>[ 2.450160] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10706 22:17:27.356821 <6>[ 2.459462] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10707 22:17:27.367307 <6>[ 2.469628] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10708 22:17:27.376753 <6>[ 2.481139] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10709 22:17:27.383914 <6>[ 2.491053] Trying to probe devices needed for running init ...
10710 22:17:27.397449 <6>[ 2.501598] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10711 22:17:27.426041 <6>[ 2.533603] hub 2-1:1.0: USB hub found
10712 22:17:27.429516 <6>[ 2.538090] hub 2-1:1.0: 3 ports detected
10713 22:17:27.548703 <6>[ 2.653330] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10714 22:17:27.701772 <6>[ 2.809264] hub 1-1:1.0: USB hub found
10715 22:17:27.705442 <6>[ 2.813618] hub 1-1:1.0: 4 ports detected
10716 22:17:28.025333 <6>[ 3.129363] usb 1-1.1: new high-speed USB device number 3 using xhci-mtk
10717 22:17:28.155754 <6>[ 3.263264] hub 1-1.1:1.0: USB hub found
10718 22:17:28.158955 <6>[ 3.267546] hub 1-1.1:1.0: 4 ports detected
10719 22:17:28.272426 <6>[ 3.377145] usb 1-1.4: new high-speed USB device number 4 using xhci-mtk
10720 22:17:28.405957 <6>[ 3.513566] hub 1-1.4:1.0: USB hub found
10721 22:17:28.408831 <6>[ 3.518227] hub 1-1.4:1.0: 2 ports detected
10722 22:17:28.489015 <6>[ 3.593365] usb 1-1.1.1: new high-speed USB device number 5 using xhci-mtk
10723 22:17:28.677439 <6>[ 3.781364] usb 1-1.1.4: new full-speed USB device number 6 using xhci-mtk
10724 22:17:28.762307 <3>[ 3.869578] usb 1-1.1.4: device descriptor read/64, error -32
10725 22:17:28.953560 <3>[ 4.061569] usb 1-1.1.4: device descriptor read/64, error -32
10726 22:17:29.148599 <6>[ 4.253367] usb 1-1.4.1: new high-speed USB device number 7 using xhci-mtk
10727 22:17:29.336838 <6>[ 4.441366] usb 1-1.1.4: new full-speed USB device number 8 using xhci-mtk
10728 22:17:29.422423 <3>[ 4.529604] usb 1-1.1.4: device descriptor read/64, error -32
10729 22:17:29.614074 <3>[ 4.721578] usb 1-1.1.4: device descriptor read/64, error -32
10730 22:17:29.725772 <6>[ 4.833940] usb 1-1.1-port4: attempt power cycle
10731 22:17:29.813226 <6>[ 4.917392] usb 1-1.4.2: new high-speed USB device number 9 using xhci-mtk
10732 22:17:30.336603 <6>[ 5.441365] usb 1-1.1.4: new full-speed USB device number 10 using xhci-mtk
10733 22:17:30.343797 <4>[ 5.448820] usb 1-1.1.4: Device not responding to setup address.
10734 22:17:30.554080 <4>[ 5.661643] usb 1-1.1.4: Device not responding to setup address.
10735 22:17:30.765261 <3>[ 5.873356] usb 1-1.1.4: device not accepting address 10, error -71
10736 22:17:30.852740 <6>[ 5.957394] usb 1-1.1.4: new full-speed USB device number 11 using xhci-mtk
10737 22:17:30.859751 <4>[ 5.964843] usb 1-1.1.4: Device not responding to setup address.
10738 22:17:31.069770 <4>[ 6.177647] usb 1-1.1.4: Device not responding to setup address.
10739 22:17:31.281109 <3>[ 6.389353] usb 1-1.1.4: device not accepting address 11, error -71
10740 22:17:31.288283 <3>[ 6.396306] usb 1-1.1-port4: unable to enumerate USB device
10741 22:17:39.657819 <6>[ 14.769826] ALSA device list:
10742 22:17:39.664536 <6>[ 14.773053] No soundcards found.
10743 22:17:39.670666 <6>[ 14.779413] Freeing unused kernel memory: 8384K
10744 22:17:39.673988 <6>[ 14.784327] Run /init as init process
10745 22:17:39.682661 Loading, please wait...
10746 22:17:39.707601 Starting systemd-udevd version 252.6-1
10747 22:17:40.088621 <6>[ 15.194638] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10748 22:17:40.095414 <6>[ 15.204666] remoteproc remoteproc0: scp is available
10749 22:17:40.105211 <3>[ 15.205379] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10750 22:17:40.115328 <4>[ 15.210140] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10751 22:17:40.121976 <3>[ 15.218179] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10752 22:17:40.128719 <6>[ 15.227825] remoteproc remoteproc0: powering up scp
10753 22:17:40.135735 <4>[ 15.227855] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10754 22:17:40.145360 <6>[ 15.235538] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10755 22:17:40.151970 <6>[ 15.235563] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10756 22:17:40.161786 <6>[ 15.235572] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10757 22:17:40.168384 <3>[ 15.235941] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10758 22:17:40.175527 <3>[ 15.241160] remoteproc remoteproc0: request_firmware failed: -2
10759 22:17:40.181350 <6>[ 15.251278] mc: Linux media interface: v0.10
10760 22:17:40.188415 <6>[ 15.251324] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10761 22:17:40.195217 <3>[ 15.251632] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10762 22:17:40.205252 <3>[ 15.251644] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10763 22:17:40.211785 <3>[ 15.251652] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10764 22:17:40.222141 <3>[ 15.251659] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10765 22:17:40.228973 <3>[ 15.251666] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10766 22:17:40.238153 <3>[ 15.251702] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10767 22:17:40.244965 <3>[ 15.251737] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10768 22:17:40.251164 <3>[ 15.251744] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10769 22:17:40.261683 <3>[ 15.251750] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10770 22:17:40.268864 <3>[ 15.251784] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10771 22:17:40.278747 <3>[ 15.251791] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10772 22:17:40.285024 <3>[ 15.251798] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10773 22:17:40.292227 <3>[ 15.251804] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10774 22:17:40.301907 <3>[ 15.251811] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10775 22:17:40.308662 <3>[ 15.251835] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10776 22:17:40.314673 <6>[ 15.251922] usbcore: registered new interface driver r8152
10777 22:17:40.321864 <4>[ 15.258882] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10778 22:17:40.331633 <4>[ 15.286652] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10779 22:17:40.334927 <4>[ 15.286652] Fallback method does not support PEC.
10780 22:17:40.341504 <6>[ 15.291049] videodev: Linux video capture interface: v2.00
10781 22:17:40.347788 <4>[ 15.291415] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10782 22:17:40.358144 <3>[ 15.315423] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10783 22:17:40.364602 <6>[ 15.353402] usb 1-1.1.1: reset high-speed USB device number 5 using xhci-mtk
10784 22:17:40.371169 <6>[ 15.358476] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10785 22:17:40.377534 <6>[ 15.358483] pci_bus 0000:00: root bus resource [bus 00-ff]
10786 22:17:40.384640 <6>[ 15.358488] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10787 22:17:40.394318 <6>[ 15.358493] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10788 22:17:40.401311 <6>[ 15.358519] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10789 22:17:40.407599 <6>[ 15.358538] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10790 22:17:40.414289 <6>[ 15.358610] pci 0000:00:00.0: supports D1 D2
10791 22:17:40.420991 <6>[ 15.358614] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10792 22:17:40.427131 <6>[ 15.360054] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10793 22:17:40.437251 <6>[ 15.377562] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10794 22:17:40.443620 <6>[ 15.383441] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10795 22:17:40.454002 <6>[ 15.391872] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10796 22:17:40.460239 <6>[ 15.399433] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10797 22:17:40.470164 <3>[ 15.409007] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10798 22:17:40.480248 <6>[ 15.411646] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10799 22:17:40.487190 <6>[ 15.415890] usbcore: registered new interface driver cdc_ether
10800 22:17:40.494001 <6>[ 15.429832] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10801 22:17:40.500478 <6>[ 15.451141] usbcore: registered new interface driver r8153_ecm
10802 22:17:40.503656 <6>[ 15.451175] Bluetooth: Core ver 2.22
10803 22:17:40.510072 <6>[ 15.451222] NET: Registered PF_BLUETOOTH protocol family
10804 22:17:40.517047 <6>[ 15.451225] Bluetooth: HCI device and connection manager initialized
10805 22:17:40.519777 <6>[ 15.451238] Bluetooth: HCI socket layer initialized
10806 22:17:40.526386 <6>[ 15.451243] Bluetooth: L2CAP socket layer initialized
10807 22:17:40.529773 <6>[ 15.451253] Bluetooth: SCO socket layer initialized
10808 22:17:40.539956 <6>[ 15.456187] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10809 22:17:40.546677 <4>[ 15.472404] r8152 1-1.1.1:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10810 22:17:40.553475 <6>[ 15.472987] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10811 22:17:40.566274 <6>[ 15.474368] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10812 22:17:40.573049 <6>[ 15.474488] usbcore: registered new interface driver uvcvideo
10813 22:17:40.577210 <6>[ 15.479701] pci 0000:01:00.0: supports D1 D2
10814 22:17:40.586316 <4>[ 15.486496] r8152 1-1.1.1:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10815 22:17:40.592544 <6>[ 15.487137] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10816 22:17:40.599414 <6>[ 15.492223] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10817 22:17:40.606185 <6>[ 15.499824] usbcore: registered new interface driver btusb
10818 22:17:40.615705 <4>[ 15.500274] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10819 22:17:40.622514 <3>[ 15.500281] Bluetooth: hci0: Failed to load firmware file (-2)
10820 22:17:40.625898 <3>[ 15.500284] Bluetooth: hci0: Failed to set up firmware (-2)
10821 22:17:40.638985 <4>[ 15.500287] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10822 22:17:40.645786 <6>[ 15.521264] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10823 22:17:40.649178 <6>[ 15.557295] r8152 1-1.1.1:1.0 eth0: v1.12.13
10824 22:17:40.659433 <6>[ 15.558975] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10825 22:17:40.661769 <6>[ 15.577439] r8152 1-1.1.1:1.0 enxf4f5e850de0a: renamed from eth0
10826 22:17:40.671666 <6>[ 15.584240] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10827 22:17:40.678202 <6>[ 15.584253] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10828 22:17:40.688870 <6>[ 15.793265] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10829 22:17:40.695594 <6>[ 15.801276] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10830 22:17:40.701805 <6>[ 15.809283] pci 0000:00:00.0: PCI bridge to [bus 01]
10831 22:17:40.708048 <6>[ 15.814504] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10832 22:17:40.715214 <6>[ 15.822613] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10833 22:17:40.721764 <6>[ 15.829736] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10834 22:17:40.727833 <6>[ 15.836232] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10835 22:17:40.743831 <5>[ 15.849331] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10836 22:17:40.762498 <5>[ 15.868382] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10837 22:17:40.769272 <4>[ 15.875271] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10838 22:17:40.776312 <6>[ 15.884153] cfg80211: failed to load regulatory.db
10839 22:17:40.798413 <6>[ 15.903642] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10840 22:17:40.804606 <6>[ 15.911233] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10841 22:17:40.829133 <6>[ 15.937880] mt7921e 0000:01:00.0: ASIC revision: 79610010
10842 22:17:40.926407 <4>[ 16.028186] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10843 22:17:40.929276 Begin: Loading essential drivers ... done.
10844 22:17:40.932601 Begin: Running /scripts/init-premount ... done.
10845 22:17:40.938760 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10846 22:17:40.948789 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10847 22:17:40.952609 Device /sys/class/net/enxf4f5e850de0a found
10848 22:17:40.955780 done.
10849 22:17:40.972200 Begin: Waiting up to 180 secs for any network device to become available ... done.
10850 22:17:41.024628 <4>[ 16.127037] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10851 22:17:41.035508 IP-Config: enxf4f5e850de0a hardware address f4:f5:e8:50:de:0a mtu 1500 DHCP
10852 22:17:41.124295 <4>[ 16.227057] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10853 22:17:41.224142 <4>[ 16.327037] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10854 22:17:41.324352 <4>[ 16.427054] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10855 22:17:41.424276 <4>[ 16.527013] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10856 22:17:41.524348 <4>[ 16.627004] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10857 22:17:41.623964 <4>[ 16.726996] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10858 22:17:41.724103 <4>[ 16.826979] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10859 22:17:41.824546 <4>[ 16.926986] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10860 22:17:41.916485 <3>[ 17.024971] mt7921e 0000:01:00.0: hardware init failed
10861 22:17:42.126373 IP-Config: no response after 2 secs - giving up
10862 22:17:42.179240 IP-Config: enxf4f5e850de0a hardware address f4:f5:e8:50:de:0a mtu 1500 DHCP
10863 22:17:42.191570 <6>[ 17.300608] r8152 1-1.1.1:1.0 enxf4f5e850de0a: carrier on
10864 22:17:43.281447 IP-Config: enxf4f5e850de0a complete (dhcp from 192.168.201.1):
10865 22:17:43.287926 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10866 22:17:43.294581 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10867 22:17:43.301039 host : mt8192-asurada-spherion-r0-cbg-9
10868 22:17:43.307443 domain : lava-rack
10869 22:17:43.314248 rootserver: 192.168.201.1 rootpath:
10870 22:17:43.314704 filename :
10871 22:17:43.363395 done.
10872 22:17:43.370713 Begin: Running /scripts/nfs-bottom ... done.
10873 22:17:43.382983 Begin: Running /scripts/init-bottom ... done.
10874 22:17:44.621978 <6>[ 19.731314] NET: Registered PF_INET6 protocol family
10875 22:17:44.628589 <6>[ 19.737586] Segment Routing with IPv6
10876 22:17:44.632017 <6>[ 19.741540] In-situ OAM (IOAM) with IPv6
10877 22:17:44.804742 <30>[ 19.887825] systemd[1]: systemd 252.6-1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10878 22:17:44.811955 <30>[ 19.920091] systemd[1]: Detected architecture arm64.
10879 22:17:44.818654
10880 22:17:44.822287 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10881 22:17:44.822856
10882 22:17:44.844920 <30>[ 19.954260] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10883 22:17:45.496813 <30>[ 20.603202] systemd[1]: Queued start job for default target graphical.target.
10884 22:17:45.541093 <30>[ 20.647123] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10885 22:17:45.547506 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10886 22:17:45.567684 <30>[ 20.674049] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10887 22:17:45.575013 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10888 22:17:45.595991 <30>[ 20.702314] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10889 22:17:45.606495 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10890 22:17:45.624092 <30>[ 20.730100] systemd[1]: Created slice user.slice - User and Session Slice.
10891 22:17:45.630344 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10892 22:17:45.650304 <30>[ 20.753502] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10893 22:17:45.657173 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10894 22:17:45.678547 <30>[ 20.781613] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10895 22:17:45.684964 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10896 22:17:45.713641 <30>[ 20.809534] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10897 22:17:45.722766 <30>[ 20.829300] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10898 22:17:45.730523 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10899 22:17:45.746942 <30>[ 20.853342] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10900 22:17:45.757030 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10901 22:17:45.771945 <30>[ 20.881390] systemd[1]: Reached target paths.target - Path Units.
10902 22:17:45.781521 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10903 22:17:45.799402 <30>[ 20.905450] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10904 22:17:45.805562 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10905 22:17:45.819880 <30>[ 20.929338] systemd[1]: Reached target slices.target - Slice Units.
10906 22:17:45.829667 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10907 22:17:45.843802 <30>[ 20.953366] systemd[1]: Reached target swap.target - Swaps.
10908 22:17:45.850354 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10909 22:17:45.867379 <30>[ 20.973372] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10910 22:17:45.876680 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10911 22:17:45.895647 <30>[ 21.001675] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10912 22:17:45.905459 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10913 22:17:45.924831 <30>[ 21.030773] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10914 22:17:45.934218 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10915 22:17:45.952287 <30>[ 21.058696] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10916 22:17:45.962425 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10917 22:17:45.979623 <30>[ 21.085654] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10918 22:17:45.985952 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10919 22:17:46.004284 <30>[ 21.110707] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10920 22:17:46.014109 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10921 22:17:46.032672 <30>[ 21.139415] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10922 22:17:46.043538 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10923 22:17:46.059362 <30>[ 21.165425] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10924 22:17:46.065900 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10925 22:17:46.107030 <30>[ 21.213366] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10926 22:17:46.113709 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10927 22:17:46.132661 <30>[ 21.239407] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10928 22:17:46.139383 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10929 22:17:46.161664 <30>[ 21.267922] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10930 22:17:46.167594 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10931 22:17:46.193837 <30>[ 21.293470] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10932 22:17:46.218984 <30>[ 21.325578] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10933 22:17:46.229348 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10934 22:17:46.253485 <30>[ 21.359813] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10935 22:17:46.259723 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10936 22:17:46.281121 <30>[ 21.387709] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10937 22:17:46.287995 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10938 22:17:46.313427 <30>[ 21.419909] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10939 22:17:46.323343 Startin<6>[ 21.428909] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10940 22:17:46.330504 g [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10941 22:17:46.371504 <30>[ 21.477665] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10942 22:17:46.377509 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10943 22:17:46.401646 <30>[ 21.507881] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10944 22:17:46.408234 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10945 22:17:46.429344 <30>[ 21.535919] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10946 22:17:46.439119 Starting [0;1;39mmodprobe@loop.ser…e<6>[ 21.548102] fuse: init (API version 7.37)
10947 22:17:46.439542 [0m - Load Kernel Module loop...
10948 22:17:46.467571 <30>[ 21.574153] systemd[1]: Starting systemd-journald.service - Journal Service...
10949 22:17:46.474583 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10950 22:17:46.507638 <30>[ 21.613816] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10951 22:17:46.513754 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10952 22:17:46.540708 <30>[ 21.643795] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10953 22:17:46.547443 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10954 22:17:46.569623 <30>[ 21.675873] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10955 22:17:46.579133 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10956 22:17:46.596914 <30>[ 21.703512] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10957 22:17:46.603229 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10958 22:17:46.625699 <30>[ 21.732460] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10959 22:17:46.632373 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10960 22:17:46.655138 <30>[ 21.761793] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10961 22:17:46.662120 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10962 22:17:46.679668 <30>[ 21.785590] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10963 22:17:46.686625 <3>[ 21.792196] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10964 22:17:46.696354 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10965 22:17:46.715865 <30>[ 21.821967] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10966 22:17:46.725624 <3>[ 21.829057] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10967 22:17:46.732778 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10968 22:17:46.751741 <30>[ 21.858247] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10969 22:17:46.758526 <30>[ 21.866074] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10970 22:17:46.771947 [[0;32m OK [0m] Finished [0<3>[ 21.877323] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10971 22:17:46.778332 ;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10972 22:17:46.796212 <30>[ 21.902135] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10973 22:17:46.803515 <30>[ 21.909826] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10974 22:17:46.812900 <3>[ 21.911802] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10975 22:17:46.819927 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10976 22:17:46.837171 <30>[ 21.946168] systemd[1]: modprobe@drm.service: Deactivated successfully.
10977 22:17:46.847045 <3>[ 21.951889] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10978 22:17:46.853768 <30>[ 21.953545] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10979 22:17:46.863626 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10980 22:17:46.879503 <30>[ 21.986109] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
10981 22:17:46.886462 <3>[ 21.986743] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10982 22:17:46.896855 <30>[ 21.994287] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
10983 22:17:46.906311 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10984 22:17:46.920295 <3>[ 22.026602] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10985 22:17:46.930095 <30>[ 22.036386] systemd[1]: modprobe@fuse.service: Deactivated successfully.
10986 22:17:46.937167 <30>[ 22.043842] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
10987 22:17:46.943621 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
10988 22:17:46.953188 <3>[ 22.060084] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10989 22:17:46.963373 <30>[ 22.070232] systemd[1]: modprobe@loop.service: Deactivated successfully.
10990 22:17:46.970823 <30>[ 22.077877] systemd[1]: Finished modprobe@loop.service - Load Kernel Module loop.
10991 22:17:46.980357 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10992 22:17:46.996149 <30>[ 22.102016] systemd[1]: Finished systemd-modules-load.service - Load Kernel Modules.
10993 22:17:47.002813 <3>[ 22.106941] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10994 22:17:47.012275 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10995 22:17:47.034642 <3>[ 22.140894] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10996 22:17:47.048162 <30>[ 22.150690] systemd[1]: Finished systemd-network-generator.service - Generate network units from Kernel command line.
10997 22:17:47.054257 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10998 22:17:47.075320 <30>[ 22.182124] systemd[1]: Finished systemd-remount-fs.service - Remount Root and Kernel File Systems.
10999 22:17:47.085029 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
11000 22:17:47.108123 <30>[ 22.214175] systemd[1]: Reached target network-pre.target - Preparation for Network.
11001 22:17:47.114489 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
11002 22:17:47.167048 <30>[ 22.273359] systemd[1]: Mounting sys-fs-fuse-connections.mount - FUSE Control File System...
11003 22:17:47.186759 Mounting [0;1;39msys-fs-fuse-conne…<4>[ 22.285186] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
11004 22:17:47.193634 <3>[ 22.302131] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
11005 22:17:47.196639 [0m - FUSE Control File System...
11006 22:17:47.221908 <30>[ 22.328333] systemd[1]: Mounting sys-kernel-config.mount - Kernel Configuration File System...
11007 22:17:47.228657 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
11008 22:17:47.254429 <30>[ 22.357303] systemd[1]: systemd-firstboot.service - First Boot Wizard was skipped because of an unmet condition check (ConditionFirstBoot=yes).
11009 22:17:47.270542 <30>[ 22.370736] systemd[1]: systemd-pstore.service - Platform Persistent Storage Archival was skipped because of an unmet condition check (ConditionDirectoryNotEmpty=/sys/fs/pstore).
11010 22:17:47.283228 <30>[ 22.389603] systemd[1]: Starting systemd-random-seed.service - Load/Save Random Seed...
11011 22:17:47.289253 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
11012 22:17:47.316099 <30>[ 22.419499] systemd[1]: systemd-repart.service - Repartition Root Disk was skipped because no trigger condition checks were met.
11013 22:17:47.366896 <30>[ 22.473611] systemd[1]: Starting systemd-sysctl.service - Apply Kernel Variables...
11014 22:17:47.373503 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
11015 22:17:47.393419 <30>[ 22.500347] systemd[1]: Starting systemd-sysusers.service - Create System Users...
11016 22:17:47.399772 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
11017 22:17:47.423086 <30>[ 22.529854] systemd[1]: Started systemd-journald.service - Journal Service.
11018 22:17:47.429262 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
11019 22:17:47.448527 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
11020 22:17:47.467910 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
11021 22:17:47.483090 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
11022 22:17:47.499877 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
11023 22:17:47.515733 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
11024 22:17:47.531633 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
11025 22:17:47.575351 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
11026 22:17:47.596563 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
11027 22:17:47.628922 <46>[ 22.735165] systemd-journald[298]: Received client request to flush runtime journal.
11028 22:17:48.707351 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
11029 22:17:48.730882 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
11030 22:17:48.750240 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
11031 22:17:49.018445 Starting [0;1;39msystemd-binfmt.se…et Up Additional Binary Formats...
11032 22:17:49.036914 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
11033 22:17:49.055518 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
11034 22:17:49.075473 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-bi… Set Up Additional Binary Formats.
11035 22:17:49.091607 See 'systemctl status systemd-binfmt.service' for details.
11036 22:17:49.133065 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
11037 22:17:49.232847 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
11038 22:17:49.286228 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
11039 22:17:49.344595 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
11040 22:17:49.593538 <6>[ 24.704039] remoteproc remoteproc0: powering up scp
11041 22:17:49.603169 <4>[ 24.709636] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
11042 22:17:49.610077 <3>[ 24.719479] remoteproc remoteproc0: request_firmware failed: -2
11043 22:17:49.616530 <3>[ 24.725682] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
11044 22:17:49.645291 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11045 22:17:49.661800 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11046 22:17:49.678263 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11047 22:17:49.714438 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11048 22:17:49.738139 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11049 22:17:49.788988 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11050 22:17:49.810779 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11051 22:17:49.843061 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
11052 22:17:49.858952 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
11053 22:17:49.880154 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
11054 22:17:49.938486 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
11055 22:17:49.960791 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
11056 22:17:50.004756 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
11057 22:17:50.106211 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
11058 22:17:50.126619 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
11059 22:17:50.142741 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
11060 22:17:50.158695 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
11061 22:17:50.182887 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
11062 22:17:50.202326 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
11063 22:17:50.218793 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
11064 22:17:50.238204 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
11065 22:17:50.257648 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
11066 22:17:50.274698 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11067 22:17:50.292733 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11068 22:17:50.310623 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11069 22:17:50.326865 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11070 22:17:50.375534 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11071 22:17:50.407339 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
11072 22:17:50.506212 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11073 22:17:50.524084 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11074 22:17:50.696572 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11075 22:17:50.746366 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11076 22:17:50.802630 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11077 22:17:50.822639 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11078 22:17:50.843278 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11079 22:17:50.869069 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
11080 22:17:50.889009 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11081 22:17:50.912766 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11082 22:17:50.930873 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11083 22:17:51.002999 Starting [0;1;39msystemd-hostnamed.service[0m - Hostname Service...
11084 22:17:51.021142 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11085 22:17:51.057988 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11086 22:17:51.156613 [[0;32m OK [0m] Started [0;1;39msystemd-hostnamed.service[0m - Hostname Service.
11087 22:17:51.223202
11088 22:17:51.223698
11089 22:17:51.226073 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11090 22:17:51.226485
11091 22:17:51.230121 debian-bookworm-arm64 login: root (automatic login)
11092 22:17:51.230534
11093 22:17:51.230858
11094 22:17:51.464562 Linux debian-bookworm-arm64 6.1.31 #1 SMP PREEMPT Sun Jun 4 21:56:05 UTC 2023 aarch64
11095 22:17:51.464691
11096 22:17:51.471343 The programs included with the Debian GNU/Linux system are free software;
11097 22:17:51.478009 the exact distribution terms for each program are described in the
11098 22:17:51.480989 individual files in /usr/share/doc/*/copyright.
11099 22:17:51.481080
11100 22:17:51.487630 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11101 22:17:51.491133 permitted by applicable law.
11102 22:17:52.385214 Matched prompt #10: / #
11104 22:17:52.386355 Setting prompt string to ['/ #']
11105 22:17:52.386784 end: 2.2.5.1 login-action (duration 00:00:28) [common]
11107 22:17:52.387779 end: 2.2.5 auto-login-action (duration 00:00:28) [common]
11108 22:17:52.388216 start: 2.2.6 expect-shell-connection (timeout 00:03:38) [common]
11109 22:17:52.388570 Setting prompt string to ['/ #']
11110 22:17:52.388871 Forcing a shell prompt, looking for ['/ #']
11112 22:17:52.439592 / #
11113 22:17:52.439916 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11114 22:17:52.440177 Waiting using forced prompt support (timeout 00:02:30)
11115 22:17:52.445274
11116 22:17:52.445863 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11117 22:17:52.446136 start: 2.2.7 export-device-env (timeout 00:03:38) [common]
11119 22:17:52.546956 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10583911/extract-nfsrootfs-av2vgxp6'
11120 22:17:52.552777 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10583911/extract-nfsrootfs-av2vgxp6'
11122 22:17:52.654304 / # export NFS_SERVER_IP='192.168.201.1'
11123 22:17:52.660652 export NFS_SERVER_IP='192.168.201.1'
11124 22:17:52.661716 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11125 22:17:52.662306 end: 2.2 depthcharge-retry (duration 00:01:22) [common]
11126 22:17:52.662790 end: 2 depthcharge-action (duration 00:01:22) [common]
11127 22:17:52.663359 start: 3 lava-test-retry (timeout 00:07:58) [common]
11128 22:17:52.663829 start: 3.1 lava-test-shell (timeout 00:07:58) [common]
11129 22:17:52.664222 Using namespace: common
11131 22:17:52.765521 / # #
11132 22:17:52.766205 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11133 22:17:52.772024 #
11134 22:17:52.772881 Using /lava-10583911
11136 22:17:52.874058 / # export SHELL=/bin/bash
11137 22:17:52.880396 export SHELL=/bin/bash
11139 22:17:52.982044 / # . /lava-10583911/environment
11140 22:17:52.988464 . /lava-10583911/environment
11142 22:17:53.094323 / # /lava-10583911/bin/lava-test-runner /lava-10583911/0
11143 22:17:53.094994 Test shell timeout: 10s (minimum of the action and connection timeout)
11144 22:17:53.101020 /lava-10583911/bin/lava-test-runner /lava-10583911/0
11145 22:17:53.309788 + export TESTRUN_ID=0_timesync-off
11146 22:17:53.313072 + TESTRUN_ID=0_timesync-off
11147 22:17:53.316476 + cd /lava-10583911/0/tests/0_timesync-off
11148 22:17:53.319690 ++ cat uuid
11149 22:17:53.323291 + UUID=10583911_1.6.2.3.1
11150 22:17:53.323718 + set +x
11151 22:17:53.326971 <LAVA_SIGNAL_STARTRUN 0_timesync-off 10583911_1.6.2.3.1>
11152 22:17:53.327725 Received signal: <STARTRUN> 0_timesync-off 10583911_1.6.2.3.1
11153 22:17:53.328100 Starting test lava.0_timesync-off (10583911_1.6.2.3.1)
11154 22:17:53.328506 Skipping test definition patterns.
11155 22:17:53.329438 + systemctl stop systemd-timesyncd
11156 22:17:53.383488 + set +x
11157 22:17:53.386639 <LAVA_SIGNAL_ENDRUN 0_timesync-off 10583911_1.6.2.3.1>
11158 22:17:53.387341 Received signal: <ENDRUN> 0_timesync-off 10583911_1.6.2.3.1
11159 22:17:53.387792 Ending use of test pattern.
11160 22:17:53.388140 Ending test lava.0_timesync-off (10583911_1.6.2.3.1), duration 0.06
11162 22:17:53.442964 + export TESTRUN_ID=1_kselftest-alsa
11163 22:17:53.446219 + TESTRUN_ID=1_kselftest-alsa
11164 22:17:53.453211 + cd /lava-10583911/0/tests/1_kselftest-alsa
11165 22:17:53.453636 ++ cat uuid
11166 22:17:53.456293 + UUID=10583911_1.6.2.3.5
11167 22:17:53.456722 + set +x
11168 22:17:53.462907 <LAVA_SIGNAL_STARTRUN 1_kselftest-alsa 10583911_1.6.2.3.5>
11169 22:17:53.463650 Received signal: <STARTRUN> 1_kselftest-alsa 10583911_1.6.2.3.5
11170 22:17:53.464004 Starting test lava.1_kselftest-alsa (10583911_1.6.2.3.5)
11171 22:17:53.464390 Skipping test definition patterns.
11172 22:17:53.466163 + cd ./automated/linux/kselftest/
11173 22:17:53.492246 + ./kselftest.sh -c alsa -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1281-g84d5372e0f314/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11174 22:17:53.521683 INFO: install_deps skipped
11175 22:17:54.005702 --2023-06-04 22:17:53-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1281-g84d5372e0f314/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11176 22:17:54.012140 Resolving storage.kernelci.org (storage.kernelci.org)... 52.250.1.28
11177 22:17:54.146477 Connecting to storage.kernelci.org (storage.kernelci.org)|52.250.1.28|:80... connected.
11178 22:17:54.288980 HTTP request sent, awaiting response... 200 OK
11179 22:17:54.292999 Length: 2860264 (2.7M) [application/octet-stream]
11180 22:17:54.295715 Saving to: 'kselftest.tar.xz'
11181 22:17:54.296177
11182 22:17:54.296533
11183 22:17:54.574671 kselftest.tar.xz 0%[ ] 0 --.-KB/s
11184 22:17:54.859795 kselftest.tar.xz 1%[ ] 46.39K 162KB/s
11185 22:17:55.191804 kselftest.tar.xz 7%[> ] 214.67K 373KB/s
11186 22:17:55.488309 kselftest.tar.xz 28%[====> ] 805.75K 885KB/s
11187 22:17:55.619411 kselftest.tar.xz 69%[============> ] 1.90M 1.57MB/s
11188 22:17:55.626300 kselftest.tar.xz 100%[===================>] 2.73M 2.03MB/s in 1.3s
11189 22:17:55.626754
11190 22:17:55.875448 2023-06-04 22:17:55 (2.03 MB/s) - 'kselftest.tar.xz' saved [2860264/2860264]
11191 22:17:55.876053
11192 22:18:00.401245 skiplist:
11193 22:18:00.404115 ========================================
11194 22:18:00.407451 ========================================
11195 22:18:00.443424 alsa:mixer-test
11196 22:18:00.460673 ============== Tests to run ===============
11197 22:18:00.461118 alsa:mixer-test
11198 22:18:00.463707 ===========End Tests to run ===============
11199 22:18:00.549409 <12>[ 35.661350] kselftest: Running tests in alsa
11200 22:18:00.557095 TAP version 13
11201 22:18:00.571255 1..1
11202 22:18:00.584862 # selftests: alsa: mixer-test
11203 22:18:01.012346 # TAP version 13
11204 22:18:01.012897 # 1..0
11205 22:18:01.019281 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:0 error:0
11206 22:18:01.021846 ok 1 selftests: alsa: mixer-test
11207 22:18:01.644654 alsa_mixer-test pass
11208 22:18:01.673026 + ../../utils/send-to-lava.sh ./output/result.txt
11209 22:18:01.733355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test RESULT=pass>
11210 22:18:01.733793 + set +x
11211 22:18:01.734391 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test RESULT=pass
11213 22:18:01.739823 <LAVA_SIGNAL_ENDRUN 1_kselftest-alsa 10583911_1.6.2.3.5>
11214 22:18:01.740484 Received signal: <ENDRUN> 1_kselftest-alsa 10583911_1.6.2.3.5
11215 22:18:01.740843 Ending use of test pattern.
11216 22:18:01.741153 Ending test lava.1_kselftest-alsa (10583911_1.6.2.3.5), duration 8.28
11218 22:18:01.743046 <LAVA_TEST_RUNNER EXIT>
11219 22:18:01.743739 ok: lava_test_shell seems to have completed
11220 22:18:01.744214 alsa_mixer-test: pass
11221 22:18:01.744621 end: 3.1 lava-test-shell (duration 00:00:09) [common]
11222 22:18:01.745082 end: 3 lava-test-retry (duration 00:00:09) [common]
11223 22:18:01.745513 start: 4 finalize (timeout 00:07:49) [common]
11224 22:18:01.745956 start: 4.1 power-off (timeout 00:00:30) [common]
11225 22:18:01.746707 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=off'
11226 22:18:01.831074 >> Command sent successfully.
11227 22:18:01.835536 Returned 0 in 0 seconds
11228 22:18:01.936485 end: 4.1 power-off (duration 00:00:00) [common]
11230 22:18:01.938004 start: 4.2 read-feedback (timeout 00:07:49) [common]
11231 22:18:01.939337 Listened to connection for namespace 'common' for up to 1s
11232 22:18:02.939388 Finalising connection for namespace 'common'
11233 22:18:02.940120 Disconnecting from shell: Finalise
11234 22:18:02.940577 / #
11235 22:18:03.041681 end: 4.2 read-feedback (duration 00:00:01) [common]
11236 22:18:03.042415 end: 4 finalize (duration 00:00:01) [common]
11237 22:18:03.043034 Cleaning after the job
11238 22:18:03.043597 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10583911/tftp-deploy-_wzpf10d/ramdisk
11239 22:18:03.055131 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10583911/tftp-deploy-_wzpf10d/kernel
11240 22:18:03.082976 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10583911/tftp-deploy-_wzpf10d/dtb
11241 22:18:03.083339 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10583911/tftp-deploy-_wzpf10d/nfsrootfs
11242 22:18:03.161319 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10583911/tftp-deploy-_wzpf10d/modules
11243 22:18:03.166550 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10583911
11244 22:18:03.682228 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10583911
11245 22:18:03.682408 Job finished correctly