Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 131
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 25
1 22:15:48.270612 lava-dispatcher, installed at version: 2023.03
2 22:15:48.270811 start: 0 validate
3 22:15:48.270952 Start time: 2023-06-04 22:15:48.270945+00:00 (UTC)
4 22:15:48.271073 Using caching service: 'http://localhost/cache/?uri=%s'
5 22:15:48.271203 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230527.0%2Farm64%2Frootfs.cpio.gz exists
6 22:15:48.562008 Using caching service: 'http://localhost/cache/?uri=%s'
7 22:15:48.562759 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1281-g84d5372e0f314%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 22:15:48.856895 Using caching service: 'http://localhost/cache/?uri=%s'
9 22:15:48.857638 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1281-g84d5372e0f314%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 22:15:49.149908 Using caching service: 'http://localhost/cache/?uri=%s'
11 22:15:49.151000 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1281-g84d5372e0f314%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 22:15:49.454555 validate duration: 1.18
14 22:15:49.455715 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 22:15:49.456341 start: 1.1 download-retry (timeout 00:10:00) [common]
16 22:15:49.456804 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 22:15:49.457519 Not decompressing ramdisk as can be used compressed.
18 22:15:49.458065 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230527.0/arm64/rootfs.cpio.gz
19 22:15:49.458503 saving as /var/lib/lava/dispatcher/tmp/10583915/tftp-deploy-z4tjqdiw/ramdisk/rootfs.cpio.gz
20 22:15:49.458833 total size: 84903995 (80MB)
21 22:15:49.463881 progress 0% (0MB)
22 22:15:49.509738 progress 5% (4MB)
23 22:15:49.531726 progress 10% (8MB)
24 22:15:49.553105 progress 15% (12MB)
25 22:15:49.574737 progress 20% (16MB)
26 22:15:49.596242 progress 25% (20MB)
27 22:15:49.618445 progress 30% (24MB)
28 22:15:49.640120 progress 35% (28MB)
29 22:15:49.661970 progress 40% (32MB)
30 22:15:49.683541 progress 45% (36MB)
31 22:15:49.704811 progress 50% (40MB)
32 22:15:49.726103 progress 55% (44MB)
33 22:15:49.747198 progress 60% (48MB)
34 22:15:49.768298 progress 65% (52MB)
35 22:15:49.789418 progress 70% (56MB)
36 22:15:49.810952 progress 75% (60MB)
37 22:15:49.832070 progress 80% (64MB)
38 22:15:49.853204 progress 85% (68MB)
39 22:15:49.874485 progress 90% (72MB)
40 22:15:49.895755 progress 95% (76MB)
41 22:15:49.916957 progress 100% (80MB)
42 22:15:49.917119 80MB downloaded in 0.46s (176.68MB/s)
43 22:15:49.917281 end: 1.1.1 http-download (duration 00:00:00) [common]
45 22:15:49.917516 end: 1.1 download-retry (duration 00:00:00) [common]
46 22:15:49.917605 start: 1.2 download-retry (timeout 00:10:00) [common]
47 22:15:49.917689 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 22:15:49.917821 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1281-g84d5372e0f314/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 22:15:49.917895 saving as /var/lib/lava/dispatcher/tmp/10583915/tftp-deploy-z4tjqdiw/kernel/Image
50 22:15:49.917959 total size: 45746688 (43MB)
51 22:15:49.918020 No compression specified
52 22:15:49.919098 progress 0% (0MB)
53 22:15:49.930675 progress 5% (2MB)
54 22:15:49.942280 progress 10% (4MB)
55 22:15:49.953722 progress 15% (6MB)
56 22:15:49.965166 progress 20% (8MB)
57 22:15:49.976667 progress 25% (10MB)
58 22:15:49.988173 progress 30% (13MB)
59 22:15:49.999789 progress 35% (15MB)
60 22:15:50.011573 progress 40% (17MB)
61 22:15:50.023102 progress 45% (19MB)
62 22:15:50.034629 progress 50% (21MB)
63 22:15:50.046122 progress 55% (24MB)
64 22:15:50.057927 progress 60% (26MB)
65 22:15:50.069596 progress 65% (28MB)
66 22:15:50.081476 progress 70% (30MB)
67 22:15:50.093133 progress 75% (32MB)
68 22:15:50.104721 progress 80% (34MB)
69 22:15:50.116417 progress 85% (37MB)
70 22:15:50.128014 progress 90% (39MB)
71 22:15:50.139296 progress 95% (41MB)
72 22:15:50.150603 progress 100% (43MB)
73 22:15:50.150729 43MB downloaded in 0.23s (187.43MB/s)
74 22:15:50.150873 end: 1.2.1 http-download (duration 00:00:00) [common]
76 22:15:50.151098 end: 1.2 download-retry (duration 00:00:00) [common]
77 22:15:50.151184 start: 1.3 download-retry (timeout 00:09:59) [common]
78 22:15:50.151267 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 22:15:50.151407 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1281-g84d5372e0f314/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 22:15:50.151481 saving as /var/lib/lava/dispatcher/tmp/10583915/tftp-deploy-z4tjqdiw/dtb/mt8192-asurada-spherion-r0.dtb
81 22:15:50.151542 total size: 46924 (0MB)
82 22:15:50.151602 No compression specified
83 22:15:50.152724 progress 69% (0MB)
84 22:15:50.152991 progress 100% (0MB)
85 22:15:50.153144 0MB downloaded in 0.00s (27.99MB/s)
86 22:15:50.153263 end: 1.3.1 http-download (duration 00:00:00) [common]
88 22:15:50.153479 end: 1.3 download-retry (duration 00:00:00) [common]
89 22:15:50.153563 start: 1.4 download-retry (timeout 00:09:59) [common]
90 22:15:50.153645 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 22:15:50.153753 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1281-g84d5372e0f314/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 22:15:50.153822 saving as /var/lib/lava/dispatcher/tmp/10583915/tftp-deploy-z4tjqdiw/modules/modules.tar
93 22:15:50.153882 total size: 8541948 (8MB)
94 22:15:50.153941 Using unxz to decompress xz
95 22:15:50.157680 progress 0% (0MB)
96 22:15:50.179483 progress 5% (0MB)
97 22:15:50.205371 progress 10% (0MB)
98 22:15:50.231788 progress 15% (1MB)
99 22:15:50.257173 progress 20% (1MB)
100 22:15:50.280709 progress 25% (2MB)
101 22:15:50.307627 progress 30% (2MB)
102 22:15:50.333300 progress 35% (2MB)
103 22:15:50.358383 progress 40% (3MB)
104 22:15:50.382696 progress 45% (3MB)
105 22:15:50.407420 progress 50% (4MB)
106 22:15:50.431780 progress 55% (4MB)
107 22:15:50.457492 progress 60% (4MB)
108 22:15:50.483592 progress 65% (5MB)
109 22:15:50.509056 progress 70% (5MB)
110 22:15:50.533004 progress 75% (6MB)
111 22:15:50.558112 progress 80% (6MB)
112 22:15:50.583887 progress 85% (6MB)
113 22:15:50.614395 progress 90% (7MB)
114 22:15:50.640133 progress 95% (7MB)
115 22:15:50.665544 progress 100% (8MB)
116 22:15:50.671766 8MB downloaded in 0.52s (15.73MB/s)
117 22:15:50.672086 end: 1.4.1 http-download (duration 00:00:01) [common]
119 22:15:50.672354 end: 1.4 download-retry (duration 00:00:01) [common]
120 22:15:50.672452 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 22:15:50.672549 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 22:15:50.672634 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 22:15:50.672720 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 22:15:50.672945 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10583915/lava-overlay-2zb26p9e
125 22:15:50.673081 makedir: /var/lib/lava/dispatcher/tmp/10583915/lava-overlay-2zb26p9e/lava-10583915/bin
126 22:15:50.673184 makedir: /var/lib/lava/dispatcher/tmp/10583915/lava-overlay-2zb26p9e/lava-10583915/tests
127 22:15:50.673281 makedir: /var/lib/lava/dispatcher/tmp/10583915/lava-overlay-2zb26p9e/lava-10583915/results
128 22:15:50.673399 Creating /var/lib/lava/dispatcher/tmp/10583915/lava-overlay-2zb26p9e/lava-10583915/bin/lava-add-keys
129 22:15:50.673545 Creating /var/lib/lava/dispatcher/tmp/10583915/lava-overlay-2zb26p9e/lava-10583915/bin/lava-add-sources
130 22:15:50.673674 Creating /var/lib/lava/dispatcher/tmp/10583915/lava-overlay-2zb26p9e/lava-10583915/bin/lava-background-process-start
131 22:15:50.673801 Creating /var/lib/lava/dispatcher/tmp/10583915/lava-overlay-2zb26p9e/lava-10583915/bin/lava-background-process-stop
132 22:15:50.673926 Creating /var/lib/lava/dispatcher/tmp/10583915/lava-overlay-2zb26p9e/lava-10583915/bin/lava-common-functions
133 22:15:50.674049 Creating /var/lib/lava/dispatcher/tmp/10583915/lava-overlay-2zb26p9e/lava-10583915/bin/lava-echo-ipv4
134 22:15:50.674172 Creating /var/lib/lava/dispatcher/tmp/10583915/lava-overlay-2zb26p9e/lava-10583915/bin/lava-install-packages
135 22:15:50.674293 Creating /var/lib/lava/dispatcher/tmp/10583915/lava-overlay-2zb26p9e/lava-10583915/bin/lava-installed-packages
136 22:15:50.674414 Creating /var/lib/lava/dispatcher/tmp/10583915/lava-overlay-2zb26p9e/lava-10583915/bin/lava-os-build
137 22:15:50.674535 Creating /var/lib/lava/dispatcher/tmp/10583915/lava-overlay-2zb26p9e/lava-10583915/bin/lava-probe-channel
138 22:15:50.674657 Creating /var/lib/lava/dispatcher/tmp/10583915/lava-overlay-2zb26p9e/lava-10583915/bin/lava-probe-ip
139 22:15:50.674778 Creating /var/lib/lava/dispatcher/tmp/10583915/lava-overlay-2zb26p9e/lava-10583915/bin/lava-target-ip
140 22:15:50.674900 Creating /var/lib/lava/dispatcher/tmp/10583915/lava-overlay-2zb26p9e/lava-10583915/bin/lava-target-mac
141 22:15:50.675020 Creating /var/lib/lava/dispatcher/tmp/10583915/lava-overlay-2zb26p9e/lava-10583915/bin/lava-target-storage
142 22:15:50.675146 Creating /var/lib/lava/dispatcher/tmp/10583915/lava-overlay-2zb26p9e/lava-10583915/bin/lava-test-case
143 22:15:50.675268 Creating /var/lib/lava/dispatcher/tmp/10583915/lava-overlay-2zb26p9e/lava-10583915/bin/lava-test-event
144 22:15:50.675387 Creating /var/lib/lava/dispatcher/tmp/10583915/lava-overlay-2zb26p9e/lava-10583915/bin/lava-test-feedback
145 22:15:50.675508 Creating /var/lib/lava/dispatcher/tmp/10583915/lava-overlay-2zb26p9e/lava-10583915/bin/lava-test-raise
146 22:15:50.675631 Creating /var/lib/lava/dispatcher/tmp/10583915/lava-overlay-2zb26p9e/lava-10583915/bin/lava-test-reference
147 22:15:50.675753 Creating /var/lib/lava/dispatcher/tmp/10583915/lava-overlay-2zb26p9e/lava-10583915/bin/lava-test-runner
148 22:15:50.675875 Creating /var/lib/lava/dispatcher/tmp/10583915/lava-overlay-2zb26p9e/lava-10583915/bin/lava-test-set
149 22:15:50.676040 Creating /var/lib/lava/dispatcher/tmp/10583915/lava-overlay-2zb26p9e/lava-10583915/bin/lava-test-shell
150 22:15:50.676218 Updating /var/lib/lava/dispatcher/tmp/10583915/lava-overlay-2zb26p9e/lava-10583915/bin/lava-install-packages (oe)
151 22:15:50.676415 Updating /var/lib/lava/dispatcher/tmp/10583915/lava-overlay-2zb26p9e/lava-10583915/bin/lava-installed-packages (oe)
152 22:15:50.676540 Creating /var/lib/lava/dispatcher/tmp/10583915/lava-overlay-2zb26p9e/lava-10583915/environment
153 22:15:50.676647 LAVA metadata
154 22:15:50.676722 - LAVA_JOB_ID=10583915
155 22:15:50.676786 - LAVA_DISPATCHER_IP=192.168.201.1
156 22:15:50.676890 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 22:15:50.676958 skipped lava-vland-overlay
158 22:15:50.677033 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 22:15:50.677115 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 22:15:50.677180 skipped lava-multinode-overlay
161 22:15:50.677252 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 22:15:50.677337 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 22:15:50.677414 Loading test definitions
164 22:15:50.677508 start: 1.5.2.3.1 git-repo-action (timeout 00:09:59) [common]
165 22:15:50.677582 Using /lava-10583915 at stage 0
166 22:15:50.677680 Fetching tests from https://github.com/kernelci/kernelci-core
167 22:15:50.677762 Running '/usr/bin/git clone -b kernelci.org --depth=1 https://github.com/kernelci/kernelci-core /var/lib/lava/dispatcher/tmp/10583915/lava-overlay-2zb26p9e/lava-10583915/0/tests/0_sleep'
168 22:15:51.358649 Removing '.git' directory in /var/lib/lava/dispatcher/tmp/10583915/lava-overlay-2zb26p9e/lava-10583915/0/tests/0_sleep
169 22:15:51.359803 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/10583915/lava-overlay-2zb26p9e/lava-10583915/0/tests/0_sleep/config/lava/sleep/sleep.yaml
170 22:15:51.360329 uuid=10583915_1.5.2.3.1 testdef=None
171 22:15:51.360476 end: 1.5.2.3.1 git-repo-action (duration 00:00:01) [common]
173 22:15:51.360729 start: 1.5.2.3.2 test-overlay (timeout 00:09:58) [common]
174 22:15:51.361280 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
176 22:15:51.361518 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:58) [common]
177 22:15:51.362238 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
179 22:15:51.362484 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:58) [common]
180 22:15:51.363140 runner path: /var/lib/lava/dispatcher/tmp/10583915/lava-overlay-2zb26p9e/lava-10583915/0/tests/0_sleep test_uuid 10583915_1.5.2.3.1
181 22:15:51.363229 sleep_params='mem freeze'
182 22:15:51.363369 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
184 22:15:51.363602 Creating lava-test-runner.conf files
185 22:15:51.363683 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10583915/lava-overlay-2zb26p9e/lava-10583915/0 for stage 0
186 22:15:51.363775 - 0_sleep
187 22:15:51.363880 end: 1.5.2.3 test-definition (duration 00:00:01) [common]
188 22:15:51.364004 start: 1.5.2.4 compress-overlay (timeout 00:09:58) [common]
189 22:15:51.483161 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
190 22:15:51.483312 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:58) [common]
191 22:15:51.483406 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
192 22:15:51.483545 end: 1.5.2 lava-overlay (duration 00:00:01) [common]
193 22:15:51.483643 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:58) [common]
194 22:15:53.841000 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:02) [common]
195 22:15:53.841372 start: 1.5.4 extract-modules (timeout 00:09:56) [common]
196 22:15:53.841490 extracting modules file /var/lib/lava/dispatcher/tmp/10583915/tftp-deploy-z4tjqdiw/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10583915/extract-overlay-ramdisk-kuwtz2ju/ramdisk
197 22:15:54.076741 end: 1.5.4 extract-modules (duration 00:00:00) [common]
198 22:15:54.076919 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
199 22:15:54.077015 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10583915/compress-overlay-lk256yo0/overlay-1.5.2.4.tar.gz to ramdisk
200 22:15:54.077090 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10583915/compress-overlay-lk256yo0/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10583915/extract-overlay-ramdisk-kuwtz2ju/ramdisk
201 22:15:54.166216 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
202 22:15:54.166374 start: 1.5.6 configure-preseed-file (timeout 00:09:55) [common]
203 22:15:54.166470 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
204 22:15:54.166564 start: 1.5.7 compress-ramdisk (timeout 00:09:55) [common]
205 22:15:54.166653 Building ramdisk /var/lib/lava/dispatcher/tmp/10583915/extract-overlay-ramdisk-kuwtz2ju/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10583915/extract-overlay-ramdisk-kuwtz2ju/ramdisk
206 22:15:56.023870 >> 561588 blocks
207 22:16:05.868637 rename /var/lib/lava/dispatcher/tmp/10583915/extract-overlay-ramdisk-kuwtz2ju/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10583915/tftp-deploy-z4tjqdiw/ramdisk/ramdisk.cpio.gz
208 22:16:05.869094 end: 1.5.7 compress-ramdisk (duration 00:00:12) [common]
209 22:16:05.869218 start: 1.5.8 prepare-kernel (timeout 00:09:44) [common]
210 22:16:05.869315 start: 1.5.8.1 prepare-fit (timeout 00:09:44) [common]
211 22:16:05.869423 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10583915/tftp-deploy-z4tjqdiw/kernel/Image'
212 22:16:17.590417 Returned 0 in 11 seconds
213 22:16:17.691283 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10583915/tftp-deploy-z4tjqdiw/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10583915/tftp-deploy-z4tjqdiw/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10583915/tftp-deploy-z4tjqdiw/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10583915/tftp-deploy-z4tjqdiw/kernel/image.itb
214 22:16:19.063740 output: FIT description: Kernel Image image with one or more FDT blobs
215 22:16:19.064111 output: Created: Sun Jun 4 23:16:18 2023
216 22:16:19.064187 output: Image 0 (kernel-1)
217 22:16:19.064257 output: Description:
218 22:16:19.064317 output: Created: Sun Jun 4 23:16:18 2023
219 22:16:19.064382 output: Type: Kernel Image
220 22:16:19.064443 output: Compression: lzma compressed
221 22:16:19.064526 output: Data Size: 10081729 Bytes = 9845.44 KiB = 9.61 MiB
222 22:16:19.064593 output: Architecture: AArch64
223 22:16:19.064652 output: OS: Linux
224 22:16:19.064712 output: Load Address: 0x00000000
225 22:16:19.064768 output: Entry Point: 0x00000000
226 22:16:19.064826 output: Hash algo: crc32
227 22:16:19.064881 output: Hash value: 3b3111d8
228 22:16:19.064935 output: Image 1 (fdt-1)
229 22:16:19.064988 output: Description: mt8192-asurada-spherion-r0
230 22:16:19.065042 output: Created: Sun Jun 4 23:16:18 2023
231 22:16:19.065122 output: Type: Flat Device Tree
232 22:16:19.065201 output: Compression: uncompressed
233 22:16:19.065256 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
234 22:16:19.065311 output: Architecture: AArch64
235 22:16:19.065364 output: Hash algo: crc32
236 22:16:19.065417 output: Hash value: 1df858fa
237 22:16:19.065470 output: Image 2 (ramdisk-1)
238 22:16:19.065523 output: Description: unavailable
239 22:16:19.065577 output: Created: Sun Jun 4 23:16:18 2023
240 22:16:19.065631 output: Type: RAMDisk Image
241 22:16:19.065684 output: Compression: Unknown Compression
242 22:16:19.065737 output: Data Size: 98157889 Bytes = 95857.31 KiB = 93.61 MiB
243 22:16:19.065791 output: Architecture: AArch64
244 22:16:19.065844 output: OS: Linux
245 22:16:19.065898 output: Load Address: unavailable
246 22:16:19.065951 output: Entry Point: unavailable
247 22:16:19.066004 output: Hash algo: crc32
248 22:16:19.066057 output: Hash value: 6ca03d5a
249 22:16:19.066126 output: Default Configuration: 'conf-1'
250 22:16:19.066184 output: Configuration 0 (conf-1)
251 22:16:19.066238 output: Description: mt8192-asurada-spherion-r0
252 22:16:19.066291 output: Kernel: kernel-1
253 22:16:19.066344 output: Init Ramdisk: ramdisk-1
254 22:16:19.066397 output: FDT: fdt-1
255 22:16:19.066450 output: Loadables: kernel-1
256 22:16:19.066527 output:
257 22:16:19.066740 end: 1.5.8.1 prepare-fit (duration 00:00:13) [common]
258 22:16:19.066839 end: 1.5.8 prepare-kernel (duration 00:00:13) [common]
259 22:16:19.066964 end: 1.5 prepare-tftp-overlay (duration 00:00:28) [common]
260 22:16:19.067060 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:30) [common]
261 22:16:19.067139 No LXC device requested
262 22:16:19.067219 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
263 22:16:19.067307 start: 1.7 deploy-device-env (timeout 00:09:30) [common]
264 22:16:19.067382 end: 1.7 deploy-device-env (duration 00:00:00) [common]
265 22:16:19.067474 Checking files for TFTP limit of 4294967296 bytes.
266 22:16:19.067980 end: 1 tftp-deploy (duration 00:00:30) [common]
267 22:16:19.068090 start: 2 depthcharge-action (timeout 00:05:00) [common]
268 22:16:19.068181 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
269 22:16:19.068333 substitutions:
270 22:16:19.068403 - {DTB}: 10583915/tftp-deploy-z4tjqdiw/dtb/mt8192-asurada-spherion-r0.dtb
271 22:16:19.068467 - {INITRD}: 10583915/tftp-deploy-z4tjqdiw/ramdisk/ramdisk.cpio.gz
272 22:16:19.068527 - {KERNEL}: 10583915/tftp-deploy-z4tjqdiw/kernel/Image
273 22:16:19.068607 - {LAVA_MAC}: None
274 22:16:19.068685 - {PRESEED_CONFIG}: None
275 22:16:19.068746 - {PRESEED_LOCAL}: None
276 22:16:19.068801 - {RAMDISK}: 10583915/tftp-deploy-z4tjqdiw/ramdisk/ramdisk.cpio.gz
277 22:16:19.068857 - {ROOT_PART}: None
278 22:16:19.068912 - {ROOT}: None
279 22:16:19.068988 - {SERVER_IP}: 192.168.201.1
280 22:16:19.069074 - {TEE}: None
281 22:16:19.069157 Parsed boot commands:
282 22:16:19.069237 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
283 22:16:19.069409 Parsed boot commands: tftpboot 192.168.201.1 10583915/tftp-deploy-z4tjqdiw/kernel/image.itb 10583915/tftp-deploy-z4tjqdiw/kernel/cmdline
284 22:16:19.069522 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
285 22:16:19.069608 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
286 22:16:19.069701 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
287 22:16:19.069790 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
288 22:16:19.069862 Not connected, no need to disconnect.
289 22:16:19.069939 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
290 22:16:19.070049 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
291 22:16:19.070121 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-3'
292 22:16:19.073523 Setting prompt string to ['lava-test: # ']
293 22:16:19.073865 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
294 22:16:19.073974 end: 2.2.1 reset-connection (duration 00:00:00) [common]
295 22:16:19.074076 start: 2.2.2 reset-device (timeout 00:05:00) [common]
296 22:16:19.074163 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
297 22:16:19.074362 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=reboot'
298 22:16:24.224171 >> Command sent successfully.
299 22:16:24.234091 Returned 0 in 5 seconds
300 22:16:24.335316 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
302 22:16:24.337390 end: 2.2.2 reset-device (duration 00:00:05) [common]
303 22:16:24.338136 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
304 22:16:24.338741 Setting prompt string to 'Starting depthcharge on Spherion...'
305 22:16:24.339283 Changing prompt to 'Starting depthcharge on Spherion...'
306 22:16:24.339823 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
307 22:16:24.341423 [Enter `^Ec?' for help]
308 22:16:24.500488
309 22:16:24.501057
310 22:16:24.501521 F0: 102B 0000
311 22:16:24.501945
312 22:16:24.505361 F3: 1001 0000 [0200]
313 22:16:24.505902
314 22:16:24.506369 F3: 1001 0000
315 22:16:24.506797
316 22:16:24.507212 F7: 102D 0000
317 22:16:24.507716
318 22:16:24.508158 F1: 0000 0000
319 22:16:24.508844
320 22:16:24.509209 V0: 0000 0000 [0001]
321 22:16:24.509614
322 22:16:24.510112 00: 0007 8000
323 22:16:24.511790
324 22:16:24.512292 01: 0000 0000
325 22:16:24.512750
326 22:16:24.513173 BP: 0C00 0209 [0000]
327 22:16:24.513588
328 22:16:24.515651 G0: 1182 0000
329 22:16:24.516178
330 22:16:24.516683 EC: 0000 0021 [4000]
331 22:16:24.517153
332 22:16:24.518571 S7: 0000 0000 [0000]
333 22:16:24.519013
334 22:16:24.519452 CC: 0000 0000 [0001]
335 22:16:24.519943
336 22:16:24.521730 T0: 0000 0040 [010F]
337 22:16:24.522246
338 22:16:24.522730 Jump to BL
339 22:16:24.523193
340 22:16:24.547890
341 22:16:24.548420
342 22:16:24.548805
343 22:16:24.555057 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
344 22:16:24.558522 ARM64: Exception handlers installed.
345 22:16:24.563454 ARM64: Testing exception
346 22:16:24.565911 ARM64: Done test exception
347 22:16:24.573654 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
348 22:16:24.580783 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
349 22:16:24.588533 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
350 22:16:24.598579 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
351 22:16:24.604639 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
352 22:16:24.615226 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
353 22:16:24.625441 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
354 22:16:24.632399 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
355 22:16:24.650227 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
356 22:16:24.653937 WDT: Last reset was cold boot
357 22:16:24.656705 SPI1(PAD0) initialized at 2873684 Hz
358 22:16:24.660173 SPI5(PAD0) initialized at 992727 Hz
359 22:16:24.664227 VBOOT: Loading verstage.
360 22:16:24.670383 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
361 22:16:24.673899 FMAP: Found "FLASH" version 1.1 at 0x20000.
362 22:16:24.676829 FMAP: base = 0x0 size = 0x800000 #areas = 25
363 22:16:24.680376 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
364 22:16:24.687894 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
365 22:16:24.694503 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
366 22:16:24.705409 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
367 22:16:24.705666
368 22:16:24.705832
369 22:16:24.715291 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
370 22:16:24.718652 ARM64: Exception handlers installed.
371 22:16:24.721864 ARM64: Testing exception
372 22:16:24.722181 ARM64: Done test exception
373 22:16:24.728780 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
374 22:16:24.732366 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
375 22:16:24.746529 Probing TPM: . done!
376 22:16:24.747040 TPM ready after 0 ms
377 22:16:24.753449 Connected to device vid:did:rid of 1ae0:0028:00
378 22:16:24.760447 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
379 22:16:24.819693 Initialized TPM device CR50 revision 0
380 22:16:24.831180 tlcl_send_startup: Startup return code is 0
381 22:16:24.831623 TPM: setup succeeded
382 22:16:24.843017 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
383 22:16:24.851329 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
384 22:16:24.863150 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
385 22:16:24.873124 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
386 22:16:24.876528 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
387 22:16:24.882165 in-header: 03 07 00 00 08 00 00 00
388 22:16:24.885826 in-data: aa e4 47 04 13 02 00 00
389 22:16:24.889468 Chrome EC: UHEPI supported
390 22:16:24.896901 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
391 22:16:24.900940 in-header: 03 ad 00 00 08 00 00 00
392 22:16:24.904366 in-data: 00 20 20 08 00 00 00 00
393 22:16:24.904806 Phase 1
394 22:16:24.907835 FMAP: area GBB found @ 3f5000 (12032 bytes)
395 22:16:24.914740 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
396 22:16:24.918252 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
397 22:16:24.922129 Recovery requested (1009000e)
398 22:16:24.930954 TPM: Extending digest for VBOOT: boot mode into PCR 0
399 22:16:24.937059 tlcl_extend: response is 0
400 22:16:24.947251 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
401 22:16:24.953276 tlcl_extend: response is 0
402 22:16:24.960735 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
403 22:16:24.980112 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
404 22:16:24.987236 BS: bootblock times (exec / console): total (unknown) / 148 ms
405 22:16:24.987730
406 22:16:24.988293
407 22:16:24.997631 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
408 22:16:25.001496 ARM64: Exception handlers installed.
409 22:16:25.001955 ARM64: Testing exception
410 22:16:25.004215 ARM64: Done test exception
411 22:16:25.025387 pmic_efuse_setting: Set efuses in 11 msecs
412 22:16:25.028866 pmwrap_interface_init: Select PMIF_VLD_RDY
413 22:16:25.035772 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
414 22:16:25.039176 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
415 22:16:25.045411 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
416 22:16:25.049842 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
417 22:16:25.052892 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
418 22:16:25.060226 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
419 22:16:25.064344 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
420 22:16:25.067721 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
421 22:16:25.071624 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
422 22:16:25.078580 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
423 22:16:25.081812 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
424 22:16:25.085450 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
425 22:16:25.092589 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
426 22:16:25.096293 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
427 22:16:25.104218 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
428 22:16:25.107851 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
429 22:16:25.114969 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
430 22:16:25.122539 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
431 22:16:25.125606 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
432 22:16:25.132458 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
433 22:16:25.136368 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
434 22:16:25.143212 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
435 22:16:25.147119 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
436 22:16:25.154921 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
437 22:16:25.158590 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
438 22:16:25.166068 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
439 22:16:25.169706 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
440 22:16:25.173416 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
441 22:16:25.180899 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
442 22:16:25.184716 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
443 22:16:25.188057 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
444 22:16:25.195533 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
445 22:16:25.199694 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
446 22:16:25.202825 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
447 22:16:25.211178 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
448 22:16:25.214319 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
449 22:16:25.222028 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
450 22:16:25.225401 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
451 22:16:25.229422 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
452 22:16:25.232688 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
453 22:16:25.236111 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
454 22:16:25.243449 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
455 22:16:25.247175 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
456 22:16:25.250751 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
457 22:16:25.254561 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
458 22:16:25.258414 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
459 22:16:25.266491 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
460 22:16:25.269742 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
461 22:16:25.273679 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
462 22:16:25.276763 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
463 22:16:25.280060 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
464 22:16:25.287548 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
465 22:16:25.298380 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
466 22:16:25.301752 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
467 22:16:25.309191 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
468 22:16:25.320115 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
469 22:16:25.324137 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
470 22:16:25.327527 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
471 22:16:25.330819 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
472 22:16:25.339270 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x0
473 22:16:25.342407 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
474 22:16:25.350308 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
475 22:16:25.354086 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
476 22:16:25.362564 [RTC]rtc_get_frequency_meter,154: input=15, output=789
477 22:16:25.372180 [RTC]rtc_get_frequency_meter,154: input=23, output=979
478 22:16:25.382115 [RTC]rtc_get_frequency_meter,154: input=19, output=883
479 22:16:25.391743 [RTC]rtc_get_frequency_meter,154: input=17, output=837
480 22:16:25.401146 [RTC]rtc_get_frequency_meter,154: input=16, output=814
481 22:16:25.410547 [RTC]rtc_get_frequency_meter,154: input=15, output=791
482 22:16:25.420829 [RTC]rtc_get_frequency_meter,154: input=16, output=813
483 22:16:25.424812 [RTC]rtc_eosc_cali,47: left: 15, middle: 15, right: 16
484 22:16:25.428458 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
485 22:16:25.432570 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
486 22:16:25.440200 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
487 22:16:25.443422 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
488 22:16:25.447295 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
489 22:16:25.450964 ADC[4]: Raw value=901697 ID=7
490 22:16:25.451394 ADC[3]: Raw value=213336 ID=1
491 22:16:25.455042 RAM Code: 0x71
492 22:16:25.458150 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
493 22:16:25.461870 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
494 22:16:25.472570 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
495 22:16:25.476710 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
496 22:16:25.479768 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
497 22:16:25.485548 in-header: 03 07 00 00 08 00 00 00
498 22:16:25.489235 in-data: aa e4 47 04 13 02 00 00
499 22:16:25.492601 Chrome EC: UHEPI supported
500 22:16:25.500070 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
501 22:16:25.504395 in-header: 03 ed 00 00 08 00 00 00
502 22:16:25.504839 in-data: 80 20 60 08 00 00 00 00
503 22:16:25.507565 MRC: failed to locate region type 0.
504 22:16:25.515399 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
505 22:16:25.518773 DRAM-K: Running full calibration
506 22:16:25.522405 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
507 22:16:25.526435 header.status = 0x0
508 22:16:25.530142 header.version = 0x6 (expected: 0x6)
509 22:16:25.533968 header.size = 0xd00 (expected: 0xd00)
510 22:16:25.534401 header.flags = 0x0
511 22:16:25.541642 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
512 22:16:25.558621 read SPI 0x72590 0x1c583: 12500 us, 9287 KB/s, 74.296 Mbps
513 22:16:25.565506 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
514 22:16:25.568718 dram_init: ddr_geometry: 2
515 22:16:25.569180 [EMI] MDL number = 2
516 22:16:25.572822 [EMI] Get MDL freq = 0
517 22:16:25.573274 dram_init: ddr_type: 0
518 22:16:25.576254 is_discrete_lpddr4: 1
519 22:16:25.579784 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
520 22:16:25.580562
521 22:16:25.581125
522 22:16:25.583749 [Bian_co] ETT version 0.0.0.1
523 22:16:25.587301 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
524 22:16:25.587731
525 22:16:25.590949 dramc_set_vcore_voltage set vcore to 650000
526 22:16:25.594775 Read voltage for 800, 4
527 22:16:25.595223 Vio18 = 0
528 22:16:25.595587 Vcore = 650000
529 22:16:25.598096 Vdram = 0
530 22:16:25.598551 Vddq = 0
531 22:16:25.598894 Vmddr = 0
532 22:16:25.601801 dram_init: config_dvfs: 1
533 22:16:25.605603 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
534 22:16:25.612107 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
535 22:16:25.615594 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=10
536 22:16:25.619130 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=10
537 22:16:25.622384 [SwImpedanceCal] DRVP=12, DRVN=25, ODTN=9
538 22:16:25.625459 freq_region=1, Reg: DRVP=12, DRVN=25, ODTN=9
539 22:16:25.628961 MEM_TYPE=3, freq_sel=18
540 22:16:25.632095 sv_algorithm_assistance_LP4_1600
541 22:16:25.636076 ============ PULL DRAM RESETB DOWN ============
542 22:16:25.639345 ========== PULL DRAM RESETB DOWN end =========
543 22:16:25.645911 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
544 22:16:25.649236 ===================================
545 22:16:25.649685 LPDDR4 DRAM CONFIGURATION
546 22:16:25.652410 ===================================
547 22:16:25.655316 EX_ROW_EN[0] = 0x0
548 22:16:25.659090 EX_ROW_EN[1] = 0x0
549 22:16:25.659517 LP4Y_EN = 0x0
550 22:16:25.662456 WORK_FSP = 0x0
551 22:16:25.662884 WL = 0x2
552 22:16:25.665858 RL = 0x2
553 22:16:25.666281 BL = 0x2
554 22:16:25.668998 RPST = 0x0
555 22:16:25.669428 RD_PRE = 0x0
556 22:16:25.672057 WR_PRE = 0x1
557 22:16:25.672490 WR_PST = 0x0
558 22:16:25.675872 DBI_WR = 0x0
559 22:16:25.676337 DBI_RD = 0x0
560 22:16:25.679271 OTF = 0x1
561 22:16:25.682306 ===================================
562 22:16:25.685731 ===================================
563 22:16:25.686272 ANA top config
564 22:16:25.689274 ===================================
565 22:16:25.692485 DLL_ASYNC_EN = 0
566 22:16:25.695490 ALL_SLAVE_EN = 1
567 22:16:25.696076 NEW_RANK_MODE = 1
568 22:16:25.699378 DLL_IDLE_MODE = 1
569 22:16:25.702367 LP45_APHY_COMB_EN = 1
570 22:16:25.705532 TX_ODT_DIS = 1
571 22:16:25.705984 NEW_8X_MODE = 1
572 22:16:25.708856 ===================================
573 22:16:25.712129 ===================================
574 22:16:25.715852 data_rate = 1600
575 22:16:25.718859 CKR = 1
576 22:16:25.722290 DQ_P2S_RATIO = 8
577 22:16:25.726265 ===================================
578 22:16:25.729186 CA_P2S_RATIO = 8
579 22:16:25.732375 DQ_CA_OPEN = 0
580 22:16:25.732811 DQ_SEMI_OPEN = 0
581 22:16:25.735574 CA_SEMI_OPEN = 0
582 22:16:25.739055 CA_FULL_RATE = 0
583 22:16:25.742524 DQ_CKDIV4_EN = 1
584 22:16:25.746463 CA_CKDIV4_EN = 1
585 22:16:25.749108 CA_PREDIV_EN = 0
586 22:16:25.749563 PH8_DLY = 0
587 22:16:25.752392 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
588 22:16:25.756629 DQ_AAMCK_DIV = 4
589 22:16:25.758997 CA_AAMCK_DIV = 4
590 22:16:25.762938 CA_ADMCK_DIV = 4
591 22:16:25.765763 DQ_TRACK_CA_EN = 0
592 22:16:25.766317 CA_PICK = 800
593 22:16:25.769486 CA_MCKIO = 800
594 22:16:25.772616 MCKIO_SEMI = 0
595 22:16:25.776410 PLL_FREQ = 3068
596 22:16:25.779596 DQ_UI_PI_RATIO = 32
597 22:16:25.783461 CA_UI_PI_RATIO = 0
598 22:16:25.783935 ===================================
599 22:16:25.787674 ===================================
600 22:16:25.791055 memory_type:LPDDR4
601 22:16:25.791539 GP_NUM : 10
602 22:16:25.794336 SRAM_EN : 1
603 22:16:25.798104 MD32_EN : 0
604 22:16:25.801927 ===================================
605 22:16:25.802511 [ANA_INIT] >>>>>>>>>>>>>>
606 22:16:25.805021 <<<<<< [CONFIGURE PHASE]: ANA_TX
607 22:16:25.808640 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
608 22:16:25.812140 ===================================
609 22:16:25.815856 data_rate = 1600,PCW = 0X7600
610 22:16:25.819093 ===================================
611 22:16:25.822781 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
612 22:16:25.826199 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
613 22:16:25.832789 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
614 22:16:25.835576 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
615 22:16:25.839548 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
616 22:16:25.843058 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
617 22:16:25.845725 [ANA_INIT] flow start
618 22:16:25.849202 [ANA_INIT] PLL >>>>>>>>
619 22:16:25.849642 [ANA_INIT] PLL <<<<<<<<
620 22:16:25.852958 [ANA_INIT] MIDPI >>>>>>>>
621 22:16:25.856070 [ANA_INIT] MIDPI <<<<<<<<
622 22:16:25.856508 [ANA_INIT] DLL >>>>>>>>
623 22:16:25.858977 [ANA_INIT] flow end
624 22:16:25.862819 ============ LP4 DIFF to SE enter ============
625 22:16:25.869132 ============ LP4 DIFF to SE exit ============
626 22:16:25.869586 [ANA_INIT] <<<<<<<<<<<<<
627 22:16:25.872473 [Flow] Enable top DCM control >>>>>
628 22:16:25.875622 [Flow] Enable top DCM control <<<<<
629 22:16:25.879356 Enable DLL master slave shuffle
630 22:16:25.886436 ==============================================================
631 22:16:25.886999 Gating Mode config
632 22:16:25.892526 ==============================================================
633 22:16:25.895878 Config description:
634 22:16:25.902525 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
635 22:16:25.909129 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
636 22:16:25.915897 SELPH_MODE 0: By rank 1: By Phase
637 22:16:25.918954 ==============================================================
638 22:16:25.922926 GAT_TRACK_EN = 1
639 22:16:25.925985 RX_GATING_MODE = 2
640 22:16:25.930557 RX_GATING_TRACK_MODE = 2
641 22:16:25.932481 SELPH_MODE = 1
642 22:16:25.935797 PICG_EARLY_EN = 1
643 22:16:25.939045 VALID_LAT_VALUE = 1
644 22:16:25.946162 ==============================================================
645 22:16:25.949777 Enter into Gating configuration >>>>
646 22:16:25.952606 Exit from Gating configuration <<<<
647 22:16:25.953344 Enter into DVFS_PRE_config >>>>>
648 22:16:25.965801 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
649 22:16:25.969307 Exit from DVFS_PRE_config <<<<<
650 22:16:25.972859 Enter into PICG configuration >>>>
651 22:16:25.975756 Exit from PICG configuration <<<<
652 22:16:25.976240 [RX_INPUT] configuration >>>>>
653 22:16:25.979093 [RX_INPUT] configuration <<<<<
654 22:16:25.985765 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
655 22:16:25.989139 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
656 22:16:25.996931 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
657 22:16:26.003160 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
658 22:16:26.010045 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
659 22:16:26.016817 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
660 22:16:26.019728 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
661 22:16:26.023566 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
662 22:16:26.026508 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
663 22:16:26.033146 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
664 22:16:26.036655 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
665 22:16:26.039872 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
666 22:16:26.043465 ===================================
667 22:16:26.046525 LPDDR4 DRAM CONFIGURATION
668 22:16:26.050375 ===================================
669 22:16:26.050460 EX_ROW_EN[0] = 0x0
670 22:16:26.053061 EX_ROW_EN[1] = 0x0
671 22:16:26.053171 LP4Y_EN = 0x0
672 22:16:26.056794 WORK_FSP = 0x0
673 22:16:26.056879 WL = 0x2
674 22:16:26.059791 RL = 0x2
675 22:16:26.059901 BL = 0x2
676 22:16:26.063098 RPST = 0x0
677 22:16:26.067165 RD_PRE = 0x0
678 22:16:26.067272 WR_PRE = 0x1
679 22:16:26.069802 WR_PST = 0x0
680 22:16:26.069892 DBI_WR = 0x0
681 22:16:26.073677 DBI_RD = 0x0
682 22:16:26.073775 OTF = 0x1
683 22:16:26.077060 ===================================
684 22:16:26.079913 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
685 22:16:26.083144 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
686 22:16:26.090107 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
687 22:16:26.093940 ===================================
688 22:16:26.097084 LPDDR4 DRAM CONFIGURATION
689 22:16:26.097252 ===================================
690 22:16:26.100375 EX_ROW_EN[0] = 0x10
691 22:16:26.103638 EX_ROW_EN[1] = 0x0
692 22:16:26.103835 LP4Y_EN = 0x0
693 22:16:26.107177 WORK_FSP = 0x0
694 22:16:26.107481 WL = 0x2
695 22:16:26.110354 RL = 0x2
696 22:16:26.110655 BL = 0x2
697 22:16:26.113474 RPST = 0x0
698 22:16:26.113817 RD_PRE = 0x0
699 22:16:26.117202 WR_PRE = 0x1
700 22:16:26.117614 WR_PST = 0x0
701 22:16:26.120351 DBI_WR = 0x0
702 22:16:26.120769 DBI_RD = 0x0
703 22:16:26.123871 OTF = 0x1
704 22:16:26.127133 ===================================
705 22:16:26.133875 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
706 22:16:26.137079 nWR fixed to 40
707 22:16:26.140208 [ModeRegInit_LP4] CH0 RK0
708 22:16:26.140971 [ModeRegInit_LP4] CH0 RK1
709 22:16:26.143843 [ModeRegInit_LP4] CH1 RK0
710 22:16:26.146997 [ModeRegInit_LP4] CH1 RK1
711 22:16:26.147562 match AC timing 13
712 22:16:26.153851 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
713 22:16:26.157485 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
714 22:16:26.160220 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
715 22:16:26.167316 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
716 22:16:26.170898 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
717 22:16:26.171378 [EMI DOE] emi_dcm 0
718 22:16:26.176666 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
719 22:16:26.177194 ==
720 22:16:26.180349 Dram Type= 6, Freq= 0, CH_0, rank 0
721 22:16:26.183583 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
722 22:16:26.184304 ==
723 22:16:26.190475 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
724 22:16:26.193578 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
725 22:16:26.204347 [CA 0] Center 37 (7~68) winsize 62
726 22:16:26.207795 [CA 1] Center 37 (6~68) winsize 63
727 22:16:26.211055 [CA 2] Center 35 (5~66) winsize 62
728 22:16:26.214586 [CA 3] Center 34 (4~65) winsize 62
729 22:16:26.217489 [CA 4] Center 34 (4~65) winsize 62
730 22:16:26.221032 [CA 5] Center 34 (4~64) winsize 61
731 22:16:26.221461
732 22:16:26.224191 [CmdBusTrainingLP45] Vref(ca) range 1: 34
733 22:16:26.224652
734 22:16:26.227266 [CATrainingPosCal] consider 1 rank data
735 22:16:26.230434 u2DelayCellTimex100 = 270/100 ps
736 22:16:26.234017 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
737 22:16:26.237171 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
738 22:16:26.243995 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
739 22:16:26.247496 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
740 22:16:26.250665 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
741 22:16:26.253967 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
742 22:16:26.254400
743 22:16:26.257192 CA PerBit enable=1, Macro0, CA PI delay=34
744 22:16:26.257691
745 22:16:26.260751 [CBTSetCACLKResult] CA Dly = 34
746 22:16:26.261183 CS Dly: 4 (0~35)
747 22:16:26.264057 ==
748 22:16:26.268137 Dram Type= 6, Freq= 0, CH_0, rank 1
749 22:16:26.270986 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
750 22:16:26.271564 ==
751 22:16:26.274455 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
752 22:16:26.280591 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
753 22:16:26.290722 [CA 0] Center 37 (6~68) winsize 63
754 22:16:26.293517 [CA 1] Center 37 (7~68) winsize 62
755 22:16:26.296949 [CA 2] Center 35 (5~66) winsize 62
756 22:16:26.300466 [CA 3] Center 35 (4~66) winsize 63
757 22:16:26.303556 [CA 4] Center 34 (4~64) winsize 61
758 22:16:26.306768 [CA 5] Center 34 (4~64) winsize 61
759 22:16:26.307201
760 22:16:26.310441 [CmdBusTrainingLP45] Vref(ca) range 1: 32
761 22:16:26.310872
762 22:16:26.313932 [CATrainingPosCal] consider 2 rank data
763 22:16:26.316972 u2DelayCellTimex100 = 270/100 ps
764 22:16:26.320463 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
765 22:16:26.327221 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
766 22:16:26.329924 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
767 22:16:26.333231 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
768 22:16:26.336736 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
769 22:16:26.340053 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
770 22:16:26.340485
771 22:16:26.343126 CA PerBit enable=1, Macro0, CA PI delay=34
772 22:16:26.343557
773 22:16:26.346324 [CBTSetCACLKResult] CA Dly = 34
774 22:16:26.346688 CS Dly: 5 (0~37)
775 22:16:26.349989
776 22:16:26.353226 ----->DramcWriteLeveling(PI) begin...
777 22:16:26.353679 ==
778 22:16:26.356853 Dram Type= 6, Freq= 0, CH_0, rank 0
779 22:16:26.360382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
780 22:16:26.360823 ==
781 22:16:26.363896 Write leveling (Byte 0): 30 => 30
782 22:16:26.367475 Write leveling (Byte 1): 28 => 28
783 22:16:26.367911 DramcWriteLeveling(PI) end<-----
784 22:16:26.368330
785 22:16:26.371669 ==
786 22:16:26.372173 Dram Type= 6, Freq= 0, CH_0, rank 0
787 22:16:26.378153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
788 22:16:26.378594 ==
789 22:16:26.380793 [Gating] SW mode calibration
790 22:16:26.389233 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
791 22:16:26.391372 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
792 22:16:26.395142 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
793 22:16:26.401584 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
794 22:16:26.404638 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
795 22:16:26.408325 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 22:16:26.415086 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 22:16:26.418613 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 22:16:26.421750 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 22:16:26.428443 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 22:16:26.431897 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 22:16:26.435433 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 22:16:26.442074 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 22:16:26.445670 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 22:16:26.448594 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 22:16:26.451580 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 22:16:26.458371 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 22:16:26.461740 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 22:16:26.465478 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 22:16:26.471807 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
810 22:16:26.475464 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
811 22:16:26.478182 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
812 22:16:26.485261 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
813 22:16:26.489172 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
814 22:16:26.492227 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
815 22:16:26.498215 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
816 22:16:26.501705 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
817 22:16:26.505091 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
818 22:16:26.512098 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
819 22:16:26.515336 0 9 12 | B1->B0 | 2b2b 3030 | 0 0 | (0 0) (0 0)
820 22:16:26.519082 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
821 22:16:26.522012 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
822 22:16:26.528532 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
823 22:16:26.531922 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
824 22:16:26.535364 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
825 22:16:26.541937 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
826 22:16:26.545570 0 10 8 | B1->B0 | 3333 2f2f | 1 1 | (1 0) (1 0)
827 22:16:26.548514 0 10 12 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
828 22:16:26.555554 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
829 22:16:26.558610 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
830 22:16:26.561893 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
831 22:16:26.568866 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
832 22:16:26.571844 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
833 22:16:26.575531 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
834 22:16:26.582633 0 11 8 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
835 22:16:26.585322 0 11 12 | B1->B0 | 3b3b 4343 | 0 0 | (0 0) (0 0)
836 22:16:26.588584 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
837 22:16:26.595225 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
838 22:16:26.598838 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
839 22:16:26.602039 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
840 22:16:26.605111 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
841 22:16:26.611853 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
842 22:16:26.615893 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
843 22:16:26.619127 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
844 22:16:26.625751 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 22:16:26.628378 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 22:16:26.631914 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 22:16:26.638882 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 22:16:26.641941 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 22:16:26.645424 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 22:16:26.652151 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 22:16:26.655244 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
852 22:16:26.659111 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
853 22:16:26.665510 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
854 22:16:26.668758 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
855 22:16:26.672028 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
856 22:16:26.678655 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
857 22:16:26.681681 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
858 22:16:26.685247 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
859 22:16:26.691883 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
860 22:16:26.692367 Total UI for P1: 0, mck2ui 16
861 22:16:26.699026 best dqsien dly found for B0: ( 0, 14, 8)
862 22:16:26.702297 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
863 22:16:26.705150 Total UI for P1: 0, mck2ui 16
864 22:16:26.708409 best dqsien dly found for B1: ( 0, 14, 10)
865 22:16:26.711801 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
866 22:16:26.715503 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
867 22:16:26.716174
868 22:16:26.718486 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
869 22:16:26.721956 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
870 22:16:26.725259 [Gating] SW calibration Done
871 22:16:26.725694 ==
872 22:16:26.728346 Dram Type= 6, Freq= 0, CH_0, rank 0
873 22:16:26.732116 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
874 22:16:26.732571 ==
875 22:16:26.735498 RX Vref Scan: 0
876 22:16:26.735936
877 22:16:26.738533 RX Vref 0 -> 0, step: 1
878 22:16:26.739071
879 22:16:26.739422 RX Delay -130 -> 252, step: 16
880 22:16:26.745478 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
881 22:16:26.748426 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
882 22:16:26.752037 iDelay=206, Bit 2, Center 85 (-34 ~ 205) 240
883 22:16:26.755416 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
884 22:16:26.758543 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
885 22:16:26.765114 iDelay=206, Bit 5, Center 69 (-50 ~ 189) 240
886 22:16:26.768571 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
887 22:16:26.771668 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
888 22:16:26.775476 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
889 22:16:26.778739 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
890 22:16:26.785702 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
891 22:16:26.788570 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
892 22:16:26.792421 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
893 22:16:26.795590 iDelay=206, Bit 13, Center 77 (-34 ~ 189) 224
894 22:16:26.798490 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
895 22:16:26.805377 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
896 22:16:26.805851 ==
897 22:16:26.808947 Dram Type= 6, Freq= 0, CH_0, rank 0
898 22:16:26.812024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
899 22:16:26.812487 ==
900 22:16:26.812830 DQS Delay:
901 22:16:26.815352 DQS0 = 0, DQS1 = 0
902 22:16:26.815778 DQM Delay:
903 22:16:26.818517 DQM0 = 83, DQM1 = 77
904 22:16:26.818944 DQ Delay:
905 22:16:26.822241 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
906 22:16:26.825126 DQ4 =85, DQ5 =69, DQ6 =85, DQ7 =85
907 22:16:26.828669 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
908 22:16:26.831842 DQ12 =85, DQ13 =77, DQ14 =85, DQ15 =85
909 22:16:26.832311
910 22:16:26.832673
911 22:16:26.832995 ==
912 22:16:26.835274 Dram Type= 6, Freq= 0, CH_0, rank 0
913 22:16:26.838415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
914 22:16:26.838499 ==
915 22:16:26.838565
916 22:16:26.841539
917 22:16:26.841621 TX Vref Scan disable
918 22:16:26.844820 == TX Byte 0 ==
919 22:16:26.847929 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
920 22:16:26.851170 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
921 22:16:26.854916 == TX Byte 1 ==
922 22:16:26.858295 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
923 22:16:26.861809 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
924 22:16:26.861893 ==
925 22:16:26.864654 Dram Type= 6, Freq= 0, CH_0, rank 0
926 22:16:26.871384 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
927 22:16:26.871468 ==
928 22:16:26.883793 TX Vref=22, minBit 5, minWin=27, winSum=442
929 22:16:26.887498 TX Vref=24, minBit 3, minWin=27, winSum=441
930 22:16:26.890634 TX Vref=26, minBit 5, minWin=27, winSum=446
931 22:16:26.893615 TX Vref=28, minBit 1, minWin=28, winSum=451
932 22:16:26.896996 TX Vref=30, minBit 12, minWin=27, winSum=453
933 22:16:26.903805 TX Vref=32, minBit 12, minWin=27, winSum=449
934 22:16:26.907279 [TxChooseVref] Worse bit 1, Min win 28, Win sum 451, Final Vref 28
935 22:16:26.907714
936 22:16:26.911085 Final TX Range 1 Vref 28
937 22:16:26.911517
938 22:16:26.911855 ==
939 22:16:26.913813 Dram Type= 6, Freq= 0, CH_0, rank 0
940 22:16:26.917187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
941 22:16:26.917629 ==
942 22:16:26.917976
943 22:16:26.920997
944 22:16:26.921424 TX Vref Scan disable
945 22:16:26.923951 == TX Byte 0 ==
946 22:16:26.927411 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
947 22:16:26.933823 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
948 22:16:26.934255 == TX Byte 1 ==
949 22:16:26.937212 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
950 22:16:26.943590 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
951 22:16:26.944063
952 22:16:26.944412 [DATLAT]
953 22:16:26.944733 Freq=800, CH0 RK0
954 22:16:26.945061
955 22:16:26.947865 DATLAT Default: 0xa
956 22:16:26.948336 0, 0xFFFF, sum = 0
957 22:16:26.950581 1, 0xFFFF, sum = 0
958 22:16:26.951030 2, 0xFFFF, sum = 0
959 22:16:26.954019 3, 0xFFFF, sum = 0
960 22:16:26.954453 4, 0xFFFF, sum = 0
961 22:16:26.957214 5, 0xFFFF, sum = 0
962 22:16:26.957649 6, 0xFFFF, sum = 0
963 22:16:26.960459 7, 0xFFFF, sum = 0
964 22:16:26.963853 8, 0xFFFF, sum = 0
965 22:16:26.964323 9, 0x0, sum = 1
966 22:16:26.964676 10, 0x0, sum = 2
967 22:16:26.967509 11, 0x0, sum = 3
968 22:16:26.967944 12, 0x0, sum = 4
969 22:16:26.970840 best_step = 10
970 22:16:26.971398
971 22:16:26.971761 ==
972 22:16:26.974730 Dram Type= 6, Freq= 0, CH_0, rank 0
973 22:16:26.977392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
974 22:16:26.977827 ==
975 22:16:26.980605 RX Vref Scan: 1
976 22:16:26.981031
977 22:16:26.981374 Set Vref Range= 32 -> 127
978 22:16:26.981698
979 22:16:26.984546 RX Vref 32 -> 127, step: 1
980 22:16:26.985067
981 22:16:26.987409 RX Delay -95 -> 252, step: 8
982 22:16:26.988097
983 22:16:26.991341 Set Vref, RX VrefLevel [Byte0]: 32
984 22:16:26.994049 [Byte1]: 32
985 22:16:26.994512
986 22:16:26.997729 Set Vref, RX VrefLevel [Byte0]: 33
987 22:16:27.001094 [Byte1]: 33
988 22:16:27.004085
989 22:16:27.004513 Set Vref, RX VrefLevel [Byte0]: 34
990 22:16:27.007914 [Byte1]: 34
991 22:16:27.012282
992 22:16:27.012707 Set Vref, RX VrefLevel [Byte0]: 35
993 22:16:27.015195 [Byte1]: 35
994 22:16:27.019586
995 22:16:27.020049 Set Vref, RX VrefLevel [Byte0]: 36
996 22:16:27.022925 [Byte1]: 36
997 22:16:27.026917
998 22:16:27.027346 Set Vref, RX VrefLevel [Byte0]: 37
999 22:16:27.030118 [Byte1]: 37
1000 22:16:27.034626
1001 22:16:27.035053 Set Vref, RX VrefLevel [Byte0]: 38
1002 22:16:27.037784 [Byte1]: 38
1003 22:16:27.042563
1004 22:16:27.045425 Set Vref, RX VrefLevel [Byte0]: 39
1005 22:16:27.046025 [Byte1]: 39
1006 22:16:27.049387
1007 22:16:27.049816 Set Vref, RX VrefLevel [Byte0]: 40
1008 22:16:27.053313 [Byte1]: 40
1009 22:16:27.058171
1010 22:16:27.058599 Set Vref, RX VrefLevel [Byte0]: 41
1011 22:16:27.061806 [Byte1]: 41
1012 22:16:27.064893
1013 22:16:27.065327 Set Vref, RX VrefLevel [Byte0]: 42
1014 22:16:27.068782 [Byte1]: 42
1015 22:16:27.072551
1016 22:16:27.072984 Set Vref, RX VrefLevel [Byte0]: 43
1017 22:16:27.075945 [Byte1]: 43
1018 22:16:27.080152
1019 22:16:27.080720 Set Vref, RX VrefLevel [Byte0]: 44
1020 22:16:27.083694 [Byte1]: 44
1021 22:16:27.087573
1022 22:16:27.088070 Set Vref, RX VrefLevel [Byte0]: 45
1023 22:16:27.091199 [Byte1]: 45
1024 22:16:27.095235
1025 22:16:27.095830 Set Vref, RX VrefLevel [Byte0]: 46
1026 22:16:27.098623 [Byte1]: 46
1027 22:16:27.102866
1028 22:16:27.103289 Set Vref, RX VrefLevel [Byte0]: 47
1029 22:16:27.106174 [Byte1]: 47
1030 22:16:27.110359
1031 22:16:27.110780 Set Vref, RX VrefLevel [Byte0]: 48
1032 22:16:27.113588 [Byte1]: 48
1033 22:16:27.118158
1034 22:16:27.118579 Set Vref, RX VrefLevel [Byte0]: 49
1035 22:16:27.121631 [Byte1]: 49
1036 22:16:27.125511
1037 22:16:27.128998 Set Vref, RX VrefLevel [Byte0]: 50
1038 22:16:27.129464 [Byte1]: 50
1039 22:16:27.133399
1040 22:16:27.133822 Set Vref, RX VrefLevel [Byte0]: 51
1041 22:16:27.136978 [Byte1]: 51
1042 22:16:27.140931
1043 22:16:27.141353 Set Vref, RX VrefLevel [Byte0]: 52
1044 22:16:27.144202 [Byte1]: 52
1045 22:16:27.148969
1046 22:16:27.149392 Set Vref, RX VrefLevel [Byte0]: 53
1047 22:16:27.151638 [Byte1]: 53
1048 22:16:27.156257
1049 22:16:27.156783 Set Vref, RX VrefLevel [Byte0]: 54
1050 22:16:27.159179 [Byte1]: 54
1051 22:16:27.164033
1052 22:16:27.164457 Set Vref, RX VrefLevel [Byte0]: 55
1053 22:16:27.167081 [Byte1]: 55
1054 22:16:27.171304
1055 22:16:27.171775 Set Vref, RX VrefLevel [Byte0]: 56
1056 22:16:27.175150 [Byte1]: 56
1057 22:16:27.178744
1058 22:16:27.179174 Set Vref, RX VrefLevel [Byte0]: 57
1059 22:16:27.182367 [Byte1]: 57
1060 22:16:27.186372
1061 22:16:27.186821 Set Vref, RX VrefLevel [Byte0]: 58
1062 22:16:27.190016 [Byte1]: 58
1063 22:16:27.193853
1064 22:16:27.194289 Set Vref, RX VrefLevel [Byte0]: 59
1065 22:16:27.197720 [Byte1]: 59
1066 22:16:27.201704
1067 22:16:27.202127 Set Vref, RX VrefLevel [Byte0]: 60
1068 22:16:27.204977 [Byte1]: 60
1069 22:16:27.208942
1070 22:16:27.209501 Set Vref, RX VrefLevel [Byte0]: 61
1071 22:16:27.212525 [Byte1]: 61
1072 22:16:27.216500
1073 22:16:27.216582 Set Vref, RX VrefLevel [Byte0]: 62
1074 22:16:27.220318 [Byte1]: 62
1075 22:16:27.224116
1076 22:16:27.224540 Set Vref, RX VrefLevel [Byte0]: 63
1077 22:16:27.227508 [Byte1]: 63
1078 22:16:27.231757
1079 22:16:27.232225 Set Vref, RX VrefLevel [Byte0]: 64
1080 22:16:27.234861 [Byte1]: 64
1081 22:16:27.239243
1082 22:16:27.239325 Set Vref, RX VrefLevel [Byte0]: 65
1083 22:16:27.242731 [Byte1]: 65
1084 22:16:27.247111
1085 22:16:27.247194 Set Vref, RX VrefLevel [Byte0]: 66
1086 22:16:27.250258 [Byte1]: 66
1087 22:16:27.254515
1088 22:16:27.254597 Set Vref, RX VrefLevel [Byte0]: 67
1089 22:16:27.261035 [Byte1]: 67
1090 22:16:27.261136
1091 22:16:27.264802 Set Vref, RX VrefLevel [Byte0]: 68
1092 22:16:27.267580 [Byte1]: 68
1093 22:16:27.267663
1094 22:16:27.271331 Set Vref, RX VrefLevel [Byte0]: 69
1095 22:16:27.274729 [Byte1]: 69
1096 22:16:27.274811
1097 22:16:27.277407 Set Vref, RX VrefLevel [Byte0]: 70
1098 22:16:27.280824 [Byte1]: 70
1099 22:16:27.284605
1100 22:16:27.284687 Set Vref, RX VrefLevel [Byte0]: 71
1101 22:16:27.287975 [Byte1]: 71
1102 22:16:27.292614
1103 22:16:27.292698 Set Vref, RX VrefLevel [Byte0]: 72
1104 22:16:27.296264 [Byte1]: 72
1105 22:16:27.300567
1106 22:16:27.300649 Set Vref, RX VrefLevel [Byte0]: 73
1107 22:16:27.303178 [Byte1]: 73
1108 22:16:27.307602
1109 22:16:27.307684 Set Vref, RX VrefLevel [Byte0]: 74
1110 22:16:27.310842 [Byte1]: 74
1111 22:16:27.315103
1112 22:16:27.315191 Set Vref, RX VrefLevel [Byte0]: 75
1113 22:16:27.318660 [Byte1]: 75
1114 22:16:27.322777
1115 22:16:27.322879 Set Vref, RX VrefLevel [Byte0]: 76
1116 22:16:27.326278 [Byte1]: 76
1117 22:16:27.330568
1118 22:16:27.330681 Final RX Vref Byte 0 = 61 to rank0
1119 22:16:27.334378 Final RX Vref Byte 1 = 58 to rank0
1120 22:16:27.338151 Final RX Vref Byte 0 = 61 to rank1
1121 22:16:27.340741 Final RX Vref Byte 1 = 58 to rank1==
1122 22:16:27.344032 Dram Type= 6, Freq= 0, CH_0, rank 0
1123 22:16:27.351308 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1124 22:16:27.351750 ==
1125 22:16:27.352142 DQS Delay:
1126 22:16:27.352471 DQS0 = 0, DQS1 = 0
1127 22:16:27.353971 DQM Delay:
1128 22:16:27.354398 DQM0 = 87, DQM1 = 79
1129 22:16:27.357729 DQ Delay:
1130 22:16:27.360756 DQ0 =88, DQ1 =92, DQ2 =84, DQ3 =84
1131 22:16:27.361183 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =92
1132 22:16:27.364031 DQ8 =68, DQ9 =64, DQ10 =80, DQ11 =76
1133 22:16:27.367314 DQ12 =88, DQ13 =80, DQ14 =92, DQ15 =88
1134 22:16:27.370764
1135 22:16:27.371186
1136 22:16:27.377415 [DQSOSCAuto] RK0, (LSB)MR18= 0x280f, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 399 ps
1137 22:16:27.380957 CH0 RK0: MR19=606, MR18=280F
1138 22:16:27.387607 CH0_RK0: MR19=0x606, MR18=0x280F, DQSOSC=399, MR23=63, INC=92, DEC=61
1139 22:16:27.388079
1140 22:16:27.390937 ----->DramcWriteLeveling(PI) begin...
1141 22:16:27.391372 ==
1142 22:16:27.393993 Dram Type= 6, Freq= 0, CH_0, rank 1
1143 22:16:27.397725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1144 22:16:27.398156 ==
1145 22:16:27.400768 Write leveling (Byte 0): 30 => 30
1146 22:16:27.404160 Write leveling (Byte 1): 29 => 29
1147 22:16:27.407275 DramcWriteLeveling(PI) end<-----
1148 22:16:27.407699
1149 22:16:27.408105 ==
1150 22:16:27.410682 Dram Type= 6, Freq= 0, CH_0, rank 1
1151 22:16:27.414230 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1152 22:16:27.414657 ==
1153 22:16:27.417581 [Gating] SW mode calibration
1154 22:16:27.424263 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1155 22:16:27.430799 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1156 22:16:27.433862 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1157 22:16:27.437458 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1158 22:16:27.480818 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1159 22:16:27.481573 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 22:16:27.481846 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 22:16:27.482189 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 22:16:27.482363 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 22:16:27.482457 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 22:16:27.482522 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 22:16:27.482596 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 22:16:27.483167 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 22:16:27.483250 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 22:16:27.504759 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 22:16:27.505061 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 22:16:27.505462 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 22:16:27.505724 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 22:16:27.505797 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 22:16:27.508508 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
1174 22:16:27.511758 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1175 22:16:27.518554 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 22:16:27.521858 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 22:16:27.525495 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 22:16:27.531779 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 22:16:27.535119 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 22:16:27.538812 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 22:16:27.542160 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 22:16:27.548802 0 9 8 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
1183 22:16:27.551924 0 9 12 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
1184 22:16:27.555198 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1185 22:16:27.562446 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1186 22:16:27.565571 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1187 22:16:27.569098 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1188 22:16:27.575424 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1189 22:16:27.578809 0 10 4 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
1190 22:16:27.581894 0 10 8 | B1->B0 | 3232 2626 | 0 0 | (0 1) (0 0)
1191 22:16:27.588818 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 22:16:27.592311 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 22:16:27.595732 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 22:16:27.602570 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 22:16:27.605698 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 22:16:27.609334 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1197 22:16:27.612965 0 11 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1198 22:16:27.620998 0 11 8 | B1->B0 | 2d2d 4444 | 0 0 | (0 0) (0 0)
1199 22:16:27.624258 0 11 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
1200 22:16:27.627207 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1201 22:16:27.630622 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1202 22:16:27.637933 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1203 22:16:27.641194 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1204 22:16:27.644264 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1205 22:16:27.647797 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1206 22:16:27.654595 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1207 22:16:27.658478 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 22:16:27.661121 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 22:16:27.668264 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 22:16:27.671874 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 22:16:27.674648 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 22:16:27.681274 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 22:16:27.684546 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 22:16:27.688181 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 22:16:27.694806 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 22:16:27.698105 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 22:16:27.701955 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 22:16:27.705368 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 22:16:27.712123 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 22:16:27.715404 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1221 22:16:27.718355 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1222 22:16:27.725122 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1223 22:16:27.729019 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1224 22:16:27.732035 Total UI for P1: 0, mck2ui 16
1225 22:16:27.735144 best dqsien dly found for B0: ( 0, 14, 6)
1226 22:16:27.738348 Total UI for P1: 0, mck2ui 16
1227 22:16:27.741780 best dqsien dly found for B1: ( 0, 14, 10)
1228 22:16:27.745132 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1229 22:16:27.748959 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1230 22:16:27.749376
1231 22:16:27.752562 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1232 22:16:27.755330 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1233 22:16:27.758475 [Gating] SW calibration Done
1234 22:16:27.758890 ==
1235 22:16:27.762293 Dram Type= 6, Freq= 0, CH_0, rank 1
1236 22:16:27.765341 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1237 22:16:27.765839 ==
1238 22:16:27.768682 RX Vref Scan: 0
1239 22:16:27.769099
1240 22:16:27.772050 RX Vref 0 -> 0, step: 1
1241 22:16:27.772468
1242 22:16:27.775151 RX Delay -130 -> 252, step: 16
1243 22:16:27.778213 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1244 22:16:27.781861 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1245 22:16:27.785070 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1246 22:16:27.788475 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1247 22:16:27.795340 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1248 22:16:27.798342 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1249 22:16:27.801894 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1250 22:16:27.805344 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1251 22:16:27.808359 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
1252 22:16:27.814748 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1253 22:16:27.818343 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1254 22:16:27.821259 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1255 22:16:27.825482 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1256 22:16:27.828147 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1257 22:16:27.835146 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1258 22:16:27.838527 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1259 22:16:27.839012 ==
1260 22:16:27.841612 Dram Type= 6, Freq= 0, CH_0, rank 1
1261 22:16:27.845024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1262 22:16:27.845447 ==
1263 22:16:27.848366 DQS Delay:
1264 22:16:27.848786 DQS0 = 0, DQS1 = 0
1265 22:16:27.849125 DQM Delay:
1266 22:16:27.852368 DQM0 = 86, DQM1 = 76
1267 22:16:27.852788 DQ Delay:
1268 22:16:27.854968 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
1269 22:16:27.858635 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =93
1270 22:16:27.861713 DQ8 =61, DQ9 =69, DQ10 =77, DQ11 =69
1271 22:16:27.865008 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
1272 22:16:27.865435
1273 22:16:27.865775
1274 22:16:27.866090 ==
1275 22:16:27.868140 Dram Type= 6, Freq= 0, CH_0, rank 1
1276 22:16:27.874879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1277 22:16:27.875305 ==
1278 22:16:27.875642
1279 22:16:27.875975
1280 22:16:27.876294 TX Vref Scan disable
1281 22:16:27.878475 == TX Byte 0 ==
1282 22:16:27.881758 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1283 22:16:27.888215 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1284 22:16:27.888848 == TX Byte 1 ==
1285 22:16:27.891430 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1286 22:16:27.895289 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1287 22:16:27.898665 ==
1288 22:16:27.901554 Dram Type= 6, Freq= 0, CH_0, rank 1
1289 22:16:27.905236 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1290 22:16:27.905663 ==
1291 22:16:27.917348 TX Vref=22, minBit 3, minWin=27, winSum=445
1292 22:16:27.920883 TX Vref=24, minBit 1, minWin=27, winSum=443
1293 22:16:27.924443 TX Vref=26, minBit 12, minWin=27, winSum=453
1294 22:16:27.927450 TX Vref=28, minBit 3, minWin=27, winSum=453
1295 22:16:27.930551 TX Vref=30, minBit 13, minWin=27, winSum=455
1296 22:16:27.937643 TX Vref=32, minBit 13, minWin=27, winSum=453
1297 22:16:27.941201 [TxChooseVref] Worse bit 13, Min win 27, Win sum 455, Final Vref 30
1298 22:16:27.941628
1299 22:16:27.944053 Final TX Range 1 Vref 30
1300 22:16:27.944472
1301 22:16:27.944807 ==
1302 22:16:27.947343 Dram Type= 6, Freq= 0, CH_0, rank 1
1303 22:16:27.950779 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1304 22:16:27.954345 ==
1305 22:16:27.954760
1306 22:16:27.955085
1307 22:16:27.955394 TX Vref Scan disable
1308 22:16:27.957508 == TX Byte 0 ==
1309 22:16:27.961181 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1310 22:16:27.967587 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1311 22:16:27.967811 == TX Byte 1 ==
1312 22:16:27.970708 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1313 22:16:27.977424 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1314 22:16:27.977711
1315 22:16:27.977888 [DATLAT]
1316 22:16:27.978054 Freq=800, CH0 RK1
1317 22:16:27.978215
1318 22:16:27.981009 DATLAT Default: 0xa
1319 22:16:27.981317 0, 0xFFFF, sum = 0
1320 22:16:27.984219 1, 0xFFFF, sum = 0
1321 22:16:27.984505 2, 0xFFFF, sum = 0
1322 22:16:27.987111 3, 0xFFFF, sum = 0
1323 22:16:27.990478 4, 0xFFFF, sum = 0
1324 22:16:27.990844 5, 0xFFFF, sum = 0
1325 22:16:27.993913 6, 0xFFFF, sum = 0
1326 22:16:27.994134 7, 0xFFFF, sum = 0
1327 22:16:27.997391 8, 0xFFFF, sum = 0
1328 22:16:27.997615 9, 0x0, sum = 1
1329 22:16:27.997793 10, 0x0, sum = 2
1330 22:16:28.001227 11, 0x0, sum = 3
1331 22:16:28.001539 12, 0x0, sum = 4
1332 22:16:28.004168 best_step = 10
1333 22:16:28.004438
1334 22:16:28.004649 ==
1335 22:16:28.007894 Dram Type= 6, Freq= 0, CH_0, rank 1
1336 22:16:28.010587 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1337 22:16:28.010933 ==
1338 22:16:28.014385 RX Vref Scan: 0
1339 22:16:28.014834
1340 22:16:28.015187 RX Vref 0 -> 0, step: 1
1341 22:16:28.015519
1342 22:16:28.017844 RX Delay -95 -> 252, step: 8
1343 22:16:28.024637 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1344 22:16:28.027821 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1345 22:16:28.031081 iDelay=209, Bit 2, Center 84 (-31 ~ 200) 232
1346 22:16:28.034159 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1347 22:16:28.037497 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1348 22:16:28.044733 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1349 22:16:28.047688 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1350 22:16:28.051708 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1351 22:16:28.054317 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1352 22:16:28.058170 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1353 22:16:28.064607 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1354 22:16:28.067433 iDelay=209, Bit 11, Center 68 (-39 ~ 176) 216
1355 22:16:28.070654 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1356 22:16:28.074115 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1357 22:16:28.077353 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1358 22:16:28.084004 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1359 22:16:28.084471 ==
1360 22:16:28.087634 Dram Type= 6, Freq= 0, CH_0, rank 1
1361 22:16:28.091274 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1362 22:16:28.092034 ==
1363 22:16:28.092465 DQS Delay:
1364 22:16:28.093978 DQS0 = 0, DQS1 = 0
1365 22:16:28.094441 DQM Delay:
1366 22:16:28.097510 DQM0 = 87, DQM1 = 78
1367 22:16:28.097917 DQ Delay:
1368 22:16:28.100957 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1369 22:16:28.103860 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1370 22:16:28.107147 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1371 22:16:28.110645 DQ12 =84, DQ13 =84, DQ14 =88, DQ15 =88
1372 22:16:28.111054
1373 22:16:28.111376
1374 22:16:28.120631 [DQSOSCAuto] RK1, (LSB)MR18= 0x2c15, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 398 ps
1375 22:16:28.121079 CH0 RK1: MR19=606, MR18=2C15
1376 22:16:28.127633 CH0_RK1: MR19=0x606, MR18=0x2C15, DQSOSC=398, MR23=63, INC=93, DEC=62
1377 22:16:28.130878 [RxdqsGatingPostProcess] freq 800
1378 22:16:28.137251 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1379 22:16:28.140334 Pre-setting of DQS Precalculation
1380 22:16:28.144127 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1381 22:16:28.144550 ==
1382 22:16:28.147270 Dram Type= 6, Freq= 0, CH_1, rank 0
1383 22:16:28.150488 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1384 22:16:28.153808 ==
1385 22:16:28.158046 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1386 22:16:28.163867 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1387 22:16:28.172768 [CA 0] Center 36 (5~67) winsize 63
1388 22:16:28.176541 [CA 1] Center 36 (5~67) winsize 63
1389 22:16:28.179233 [CA 2] Center 34 (4~64) winsize 61
1390 22:16:28.182718 [CA 3] Center 33 (3~64) winsize 62
1391 22:16:28.186856 [CA 4] Center 34 (3~65) winsize 63
1392 22:16:28.189627 [CA 5] Center 33 (3~64) winsize 62
1393 22:16:28.190092
1394 22:16:28.192398 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1395 22:16:28.192904
1396 22:16:28.196199 [CATrainingPosCal] consider 1 rank data
1397 22:16:28.199441 u2DelayCellTimex100 = 270/100 ps
1398 22:16:28.202776 CA0 delay=36 (5~67),Diff = 3 PI (21 cell)
1399 22:16:28.206289 CA1 delay=36 (5~67),Diff = 3 PI (21 cell)
1400 22:16:28.212343 CA2 delay=34 (4~64),Diff = 1 PI (7 cell)
1401 22:16:28.216048 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1402 22:16:28.219244 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
1403 22:16:28.222721 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1404 22:16:28.223176
1405 22:16:28.226011 CA PerBit enable=1, Macro0, CA PI delay=33
1406 22:16:28.226465
1407 22:16:28.229202 [CBTSetCACLKResult] CA Dly = 33
1408 22:16:28.229610 CS Dly: 5 (0~36)
1409 22:16:28.229931 ==
1410 22:16:28.232453 Dram Type= 6, Freq= 0, CH_1, rank 1
1411 22:16:28.239473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1412 22:16:28.239884 ==
1413 22:16:28.242712 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1414 22:16:28.249836 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1415 22:16:28.258391 [CA 0] Center 36 (5~67) winsize 63
1416 22:16:28.262134 [CA 1] Center 36 (5~67) winsize 63
1417 22:16:28.265454 [CA 2] Center 34 (4~64) winsize 61
1418 22:16:28.268803 [CA 3] Center 33 (3~64) winsize 62
1419 22:16:28.271798 [CA 4] Center 34 (3~65) winsize 63
1420 22:16:28.275418 [CA 5] Center 33 (3~64) winsize 62
1421 22:16:28.275855
1422 22:16:28.279231 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1423 22:16:28.279642
1424 22:16:28.282937 [CATrainingPosCal] consider 2 rank data
1425 22:16:28.286985 u2DelayCellTimex100 = 270/100 ps
1426 22:16:28.290523 CA0 delay=36 (5~67),Diff = 3 PI (21 cell)
1427 22:16:28.294715 CA1 delay=36 (5~67),Diff = 3 PI (21 cell)
1428 22:16:28.297975 CA2 delay=34 (4~64),Diff = 1 PI (7 cell)
1429 22:16:28.302046 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1430 22:16:28.305631 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
1431 22:16:28.308985 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1432 22:16:28.309499
1433 22:16:28.312826 CA PerBit enable=1, Macro0, CA PI delay=33
1434 22:16:28.313314
1435 22:16:28.316251 [CBTSetCACLKResult] CA Dly = 33
1436 22:16:28.316671 CS Dly: 5 (0~36)
1437 22:16:28.317008
1438 22:16:28.318938 ----->DramcWriteLeveling(PI) begin...
1439 22:16:28.319365 ==
1440 22:16:28.322479 Dram Type= 6, Freq= 0, CH_1, rank 0
1441 22:16:28.329108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1442 22:16:28.329532 ==
1443 22:16:28.332482 Write leveling (Byte 0): 29 => 29
1444 22:16:28.332905 Write leveling (Byte 1): 31 => 31
1445 22:16:28.335994 DramcWriteLeveling(PI) end<-----
1446 22:16:28.336432
1447 22:16:28.336826 ==
1448 22:16:28.339814 Dram Type= 6, Freq= 0, CH_1, rank 0
1449 22:16:28.345946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1450 22:16:28.346389 ==
1451 22:16:28.349222 [Gating] SW mode calibration
1452 22:16:28.356197 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1453 22:16:28.359289 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1454 22:16:28.366221 0 6 0 | B1->B0 | 2423 2323 | 1 0 | (1 1) (1 1)
1455 22:16:28.369259 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1456 22:16:28.372977 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1457 22:16:28.376220 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 22:16:28.383057 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 22:16:28.385887 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 22:16:28.389376 0 6 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1461 22:16:28.395896 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 22:16:28.399278 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 22:16:28.402961 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 22:16:28.409219 0 7 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1465 22:16:28.412464 0 7 12 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1466 22:16:28.415896 0 7 16 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1467 22:16:28.422813 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 22:16:28.426135 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 22:16:28.429904 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 22:16:28.436254 0 8 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1471 22:16:28.439171 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1472 22:16:28.443139 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 22:16:28.449539 0 8 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1474 22:16:28.453306 0 8 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1475 22:16:28.456373 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 22:16:28.463182 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 22:16:28.466280 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 22:16:28.469836 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 22:16:28.476059 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 22:16:28.479251 0 9 8 | B1->B0 | 2626 2626 | 0 0 | (0 0) (0 0)
1481 22:16:28.482340 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1482 22:16:28.486417 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1483 22:16:28.492833 0 9 20 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1484 22:16:28.495804 0 9 24 | B1->B0 | 3535 3434 | 1 1 | (0 0) (1 1)
1485 22:16:28.499196 0 9 28 | B1->B0 | 3535 3434 | 1 1 | (0 0) (1 1)
1486 22:16:28.505692 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1487 22:16:28.509103 0 10 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 0)
1488 22:16:28.512453 0 10 8 | B1->B0 | 2f2f 2e2e | 0 0 | (0 0) (0 0)
1489 22:16:28.519102 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1490 22:16:28.522571 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 22:16:28.526002 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 22:16:28.532551 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 22:16:28.535442 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 22:16:28.538815 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1495 22:16:28.545938 0 11 4 | B1->B0 | 2424 2323 | 1 0 | (0 0) (0 0)
1496 22:16:28.548835 0 11 8 | B1->B0 | 3636 3838 | 1 1 | (0 0) (0 0)
1497 22:16:28.551975 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 22:16:28.558860 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1499 22:16:28.561773 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1500 22:16:28.565388 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1501 22:16:28.571725 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1502 22:16:28.575098 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1503 22:16:28.578589 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1504 22:16:28.585480 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 22:16:28.588385 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 22:16:28.592353 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 22:16:28.595545 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 22:16:28.602065 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 22:16:28.605649 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 22:16:28.608805 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 22:16:28.614958 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 22:16:28.618753 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 22:16:28.622131 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 22:16:28.628737 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 22:16:28.632058 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 22:16:28.635155 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 22:16:28.641790 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1518 22:16:28.645198 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1519 22:16:28.648506 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1520 22:16:28.655238 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1521 22:16:28.655310 Total UI for P1: 0, mck2ui 16
1522 22:16:28.661752 best dqsien dly found for B0: ( 0, 14, 4)
1523 22:16:28.661824 Total UI for P1: 0, mck2ui 16
1524 22:16:28.668856 best dqsien dly found for B1: ( 0, 14, 4)
1525 22:16:28.671558 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1526 22:16:28.675024 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1527 22:16:28.675092
1528 22:16:28.678454 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1529 22:16:28.681642 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1530 22:16:28.684902 [Gating] SW calibration Done
1531 22:16:28.684968 ==
1532 22:16:28.688418 Dram Type= 6, Freq= 0, CH_1, rank 0
1533 22:16:28.691492 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1534 22:16:28.691569 ==
1535 22:16:28.695125 RX Vref Scan: 0
1536 22:16:28.695210
1537 22:16:28.695274 RX Vref 0 -> 0, step: 1
1538 22:16:28.695334
1539 22:16:28.698310 RX Delay -130 -> 252, step: 16
1540 22:16:28.701890 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1541 22:16:28.708472 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1542 22:16:28.711987 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1543 22:16:28.715307 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1544 22:16:28.718161 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1545 22:16:28.721681 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1546 22:16:28.728278 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1547 22:16:28.731660 iDelay=206, Bit 7, Center 69 (-50 ~ 189) 240
1548 22:16:28.735266 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1549 22:16:28.738513 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1550 22:16:28.741879 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1551 22:16:28.748222 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1552 22:16:28.751510 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1553 22:16:28.754896 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1554 22:16:28.758160 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1555 22:16:28.762181 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1556 22:16:28.765077 ==
1557 22:16:28.765161 Dram Type= 6, Freq= 0, CH_1, rank 0
1558 22:16:28.771504 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1559 22:16:28.771579 ==
1560 22:16:28.771642 DQS Delay:
1561 22:16:28.775006 DQS0 = 0, DQS1 = 0
1562 22:16:28.775105 DQM Delay:
1563 22:16:28.778163 DQM0 = 81, DQM1 = 76
1564 22:16:28.778275 DQ Delay:
1565 22:16:28.781473 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =85
1566 22:16:28.784923 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =69
1567 22:16:28.787867 DQ8 =69, DQ9 =61, DQ10 =69, DQ11 =69
1568 22:16:28.791555 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1569 22:16:28.791682
1570 22:16:28.791839
1571 22:16:28.791930 ==
1572 22:16:28.794895 Dram Type= 6, Freq= 0, CH_1, rank 0
1573 22:16:28.798664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1574 22:16:28.798746 ==
1575 22:16:28.798810
1576 22:16:28.798870
1577 22:16:28.801538 TX Vref Scan disable
1578 22:16:28.804921 == TX Byte 0 ==
1579 22:16:28.808446 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1580 22:16:28.811603 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1581 22:16:28.814888 == TX Byte 1 ==
1582 22:16:28.818802 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1583 22:16:28.821921 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1584 22:16:28.822002 ==
1585 22:16:28.825405 Dram Type= 6, Freq= 0, CH_1, rank 0
1586 22:16:28.828813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1587 22:16:28.828894 ==
1588 22:16:28.842701 TX Vref=22, minBit 8, minWin=26, winSum=435
1589 22:16:28.845855 TX Vref=24, minBit 8, minWin=26, winSum=438
1590 22:16:28.849370 TX Vref=26, minBit 11, minWin=26, winSum=441
1591 22:16:28.852579 TX Vref=28, minBit 8, minWin=27, winSum=449
1592 22:16:28.856559 TX Vref=30, minBit 0, minWin=28, winSum=454
1593 22:16:28.860067 TX Vref=32, minBit 4, minWin=28, winSum=456
1594 22:16:28.866897 [TxChooseVref] Worse bit 4, Min win 28, Win sum 456, Final Vref 32
1595 22:16:28.866980
1596 22:16:28.869766 Final TX Range 1 Vref 32
1597 22:16:28.869848
1598 22:16:28.869912 ==
1599 22:16:28.873580 Dram Type= 6, Freq= 0, CH_1, rank 0
1600 22:16:28.876715 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1601 22:16:28.876797 ==
1602 22:16:28.876862
1603 22:16:28.876920
1604 22:16:28.879781 TX Vref Scan disable
1605 22:16:28.883029 == TX Byte 0 ==
1606 22:16:28.886369 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1607 22:16:28.889460 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1608 22:16:28.893224 == TX Byte 1 ==
1609 22:16:28.896602 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1610 22:16:28.900229 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1611 22:16:28.900311
1612 22:16:28.903417 [DATLAT]
1613 22:16:28.903497 Freq=800, CH1 RK0
1614 22:16:28.903562
1615 22:16:28.906291 DATLAT Default: 0xa
1616 22:16:28.906377 0, 0xFFFF, sum = 0
1617 22:16:28.909889 1, 0xFFFF, sum = 0
1618 22:16:28.909971 2, 0xFFFF, sum = 0
1619 22:16:28.913048 3, 0xFFFF, sum = 0
1620 22:16:28.913135 4, 0xFFFF, sum = 0
1621 22:16:28.916629 5, 0xFFFF, sum = 0
1622 22:16:28.916712 6, 0xFFFF, sum = 0
1623 22:16:28.919918 7, 0xFFFF, sum = 0
1624 22:16:28.920041 8, 0xFFFF, sum = 0
1625 22:16:28.923301 9, 0x0, sum = 1
1626 22:16:28.923383 10, 0x0, sum = 2
1627 22:16:28.926686 11, 0x0, sum = 3
1628 22:16:28.926767 12, 0x0, sum = 4
1629 22:16:28.930261 best_step = 10
1630 22:16:28.930342
1631 22:16:28.930406 ==
1632 22:16:28.933330 Dram Type= 6, Freq= 0, CH_1, rank 0
1633 22:16:28.936514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1634 22:16:28.936643 ==
1635 22:16:28.936709 RX Vref Scan: 1
1636 22:16:28.939927
1637 22:16:28.940031 Set Vref Range= 32 -> 127
1638 22:16:28.940097
1639 22:16:28.943506 RX Vref 32 -> 127, step: 1
1640 22:16:28.943586
1641 22:16:28.946514 RX Delay -95 -> 252, step: 8
1642 22:16:28.946596
1643 22:16:28.949809 Set Vref, RX VrefLevel [Byte0]: 32
1644 22:16:28.953247 [Byte1]: 32
1645 22:16:28.953328
1646 22:16:28.956528 Set Vref, RX VrefLevel [Byte0]: 33
1647 22:16:28.960153 [Byte1]: 33
1648 22:16:28.960233
1649 22:16:28.963279 Set Vref, RX VrefLevel [Byte0]: 34
1650 22:16:28.966573 [Byte1]: 34
1651 22:16:28.970118
1652 22:16:28.970199 Set Vref, RX VrefLevel [Byte0]: 35
1653 22:16:28.973737 [Byte1]: 35
1654 22:16:28.978562
1655 22:16:28.978643 Set Vref, RX VrefLevel [Byte0]: 36
1656 22:16:28.981718 [Byte1]: 36
1657 22:16:28.985832
1658 22:16:28.985913 Set Vref, RX VrefLevel [Byte0]: 37
1659 22:16:28.988862 [Byte1]: 37
1660 22:16:28.993088
1661 22:16:28.993169 Set Vref, RX VrefLevel [Byte0]: 38
1662 22:16:28.996230 [Byte1]: 38
1663 22:16:29.000934
1664 22:16:29.004443 Set Vref, RX VrefLevel [Byte0]: 39
1665 22:16:29.004525 [Byte1]: 39
1666 22:16:29.008255
1667 22:16:29.008335 Set Vref, RX VrefLevel [Byte0]: 40
1668 22:16:29.011553 [Byte1]: 40
1669 22:16:29.016126
1670 22:16:29.016206 Set Vref, RX VrefLevel [Byte0]: 41
1671 22:16:29.019400 [Byte1]: 41
1672 22:16:29.024120
1673 22:16:29.024200 Set Vref, RX VrefLevel [Byte0]: 42
1674 22:16:29.027016 [Byte1]: 42
1675 22:16:29.031449
1676 22:16:29.031530 Set Vref, RX VrefLevel [Byte0]: 43
1677 22:16:29.034470 [Byte1]: 43
1678 22:16:29.038998
1679 22:16:29.039080 Set Vref, RX VrefLevel [Byte0]: 44
1680 22:16:29.042206 [Byte1]: 44
1681 22:16:29.046278
1682 22:16:29.046360 Set Vref, RX VrefLevel [Byte0]: 45
1683 22:16:29.049587 [Byte1]: 45
1684 22:16:29.054176
1685 22:16:29.054258 Set Vref, RX VrefLevel [Byte0]: 46
1686 22:16:29.057220 [Byte1]: 46
1687 22:16:29.061496
1688 22:16:29.061576 Set Vref, RX VrefLevel [Byte0]: 47
1689 22:16:29.064943 [Byte1]: 47
1690 22:16:29.069131
1691 22:16:29.069212 Set Vref, RX VrefLevel [Byte0]: 48
1692 22:16:29.072234 [Byte1]: 48
1693 22:16:29.076927
1694 22:16:29.077009 Set Vref, RX VrefLevel [Byte0]: 49
1695 22:16:29.079893 [Byte1]: 49
1696 22:16:29.084070
1697 22:16:29.084151 Set Vref, RX VrefLevel [Byte0]: 50
1698 22:16:29.087433 [Byte1]: 50
1699 22:16:29.091602
1700 22:16:29.091684 Set Vref, RX VrefLevel [Byte0]: 51
1701 22:16:29.095304 [Byte1]: 51
1702 22:16:29.100077
1703 22:16:29.100172 Set Vref, RX VrefLevel [Byte0]: 52
1704 22:16:29.102739 [Byte1]: 52
1705 22:16:29.107491
1706 22:16:29.107566 Set Vref, RX VrefLevel [Byte0]: 53
1707 22:16:29.110634 [Byte1]: 53
1708 22:16:29.115019
1709 22:16:29.115102 Set Vref, RX VrefLevel [Byte0]: 54
1710 22:16:29.118348 [Byte1]: 54
1711 22:16:29.122235
1712 22:16:29.122311 Set Vref, RX VrefLevel [Byte0]: 55
1713 22:16:29.125744 [Byte1]: 55
1714 22:16:29.129840
1715 22:16:29.129922 Set Vref, RX VrefLevel [Byte0]: 56
1716 22:16:29.133530 [Byte1]: 56
1717 22:16:29.137406
1718 22:16:29.137481 Set Vref, RX VrefLevel [Byte0]: 57
1719 22:16:29.140738 [Byte1]: 57
1720 22:16:29.145004
1721 22:16:29.145105 Set Vref, RX VrefLevel [Byte0]: 58
1722 22:16:29.148901 [Byte1]: 58
1723 22:16:29.152822
1724 22:16:29.152895 Set Vref, RX VrefLevel [Byte0]: 59
1725 22:16:29.155784 [Byte1]: 59
1726 22:16:29.160158
1727 22:16:29.160236 Set Vref, RX VrefLevel [Byte0]: 60
1728 22:16:29.163931 [Byte1]: 60
1729 22:16:29.167751
1730 22:16:29.167826 Set Vref, RX VrefLevel [Byte0]: 61
1731 22:16:29.171176 [Byte1]: 61
1732 22:16:29.175763
1733 22:16:29.175843 Set Vref, RX VrefLevel [Byte0]: 62
1734 22:16:29.178505 [Byte1]: 62
1735 22:16:29.182854
1736 22:16:29.182941 Set Vref, RX VrefLevel [Byte0]: 63
1737 22:16:29.186659 [Byte1]: 63
1738 22:16:29.190800
1739 22:16:29.190873 Set Vref, RX VrefLevel [Byte0]: 64
1740 22:16:29.193949 [Byte1]: 64
1741 22:16:29.198562
1742 22:16:29.198644 Set Vref, RX VrefLevel [Byte0]: 65
1743 22:16:29.201987 [Byte1]: 65
1744 22:16:29.206226
1745 22:16:29.206370 Set Vref, RX VrefLevel [Byte0]: 66
1746 22:16:29.209465 [Byte1]: 66
1747 22:16:29.213586
1748 22:16:29.213659 Set Vref, RX VrefLevel [Byte0]: 67
1749 22:16:29.216524 [Byte1]: 67
1750 22:16:29.221211
1751 22:16:29.221285 Set Vref, RX VrefLevel [Byte0]: 68
1752 22:16:29.224317 [Byte1]: 68
1753 22:16:29.228667
1754 22:16:29.228743 Set Vref, RX VrefLevel [Byte0]: 69
1755 22:16:29.232190 [Byte1]: 69
1756 22:16:29.236179
1757 22:16:29.236283 Set Vref, RX VrefLevel [Byte0]: 70
1758 22:16:29.239463 [Byte1]: 70
1759 22:16:29.243736
1760 22:16:29.243808 Set Vref, RX VrefLevel [Byte0]: 71
1761 22:16:29.247837 [Byte1]: 71
1762 22:16:29.251683
1763 22:16:29.251761 Set Vref, RX VrefLevel [Byte0]: 72
1764 22:16:29.255566 [Byte1]: 72
1765 22:16:29.258846
1766 22:16:29.258919 Set Vref, RX VrefLevel [Byte0]: 73
1767 22:16:29.262150 [Byte1]: 73
1768 22:16:29.266615
1769 22:16:29.266693 Set Vref, RX VrefLevel [Byte0]: 74
1770 22:16:29.270019 [Byte1]: 74
1771 22:16:29.274413
1772 22:16:29.274498 Set Vref, RX VrefLevel [Byte0]: 75
1773 22:16:29.277345 [Byte1]: 75
1774 22:16:29.281586
1775 22:16:29.281669 Set Vref, RX VrefLevel [Byte0]: 76
1776 22:16:29.285210 [Byte1]: 76
1777 22:16:29.289738
1778 22:16:29.289812 Final RX Vref Byte 0 = 66 to rank0
1779 22:16:29.292890 Final RX Vref Byte 1 = 60 to rank0
1780 22:16:29.296028 Final RX Vref Byte 0 = 66 to rank1
1781 22:16:29.299244 Final RX Vref Byte 1 = 60 to rank1==
1782 22:16:29.302895 Dram Type= 6, Freq= 0, CH_1, rank 0
1783 22:16:29.309675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1784 22:16:29.309750 ==
1785 22:16:29.309821 DQS Delay:
1786 22:16:29.309884 DQS0 = 0, DQS1 = 0
1787 22:16:29.312555 DQM Delay:
1788 22:16:29.312627 DQM0 = 82, DQM1 = 74
1789 22:16:29.316277 DQ Delay:
1790 22:16:29.319241 DQ0 =88, DQ1 =76, DQ2 =72, DQ3 =80
1791 22:16:29.319311 DQ4 =80, DQ5 =96, DQ6 =92, DQ7 =76
1792 22:16:29.322849 DQ8 =60, DQ9 =60, DQ10 =76, DQ11 =72
1793 22:16:29.326214 DQ12 =84, DQ13 =84, DQ14 =80, DQ15 =76
1794 22:16:29.329509
1795 22:16:29.329580
1796 22:16:29.336395 [DQSOSCAuto] RK0, (LSB)MR18= 0x27fd, (MSB)MR19= 0x605, tDQSOscB0 = 410 ps tDQSOscB1 = 400 ps
1797 22:16:29.340055 CH1 RK0: MR19=605, MR18=27FD
1798 22:16:29.346928 CH1_RK0: MR19=0x605, MR18=0x27FD, DQSOSC=400, MR23=63, INC=92, DEC=61
1799 22:16:29.347038
1800 22:16:29.349466 ----->DramcWriteLeveling(PI) begin...
1801 22:16:29.349565 ==
1802 22:16:29.353480 Dram Type= 6, Freq= 0, CH_1, rank 1
1803 22:16:29.356490 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1804 22:16:29.356587 ==
1805 22:16:29.359831 Write leveling (Byte 0): 28 => 28
1806 22:16:29.362908 Write leveling (Byte 1): 28 => 28
1807 22:16:29.366360 DramcWriteLeveling(PI) end<-----
1808 22:16:29.366442
1809 22:16:29.366517 ==
1810 22:16:29.369941 Dram Type= 6, Freq= 0, CH_1, rank 1
1811 22:16:29.372817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1812 22:16:29.372900 ==
1813 22:16:29.376142 [Gating] SW mode calibration
1814 22:16:29.383040 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1815 22:16:29.389949 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1816 22:16:29.392996 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1817 22:16:29.396193 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1818 22:16:29.403313 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 22:16:29.406690 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 22:16:29.409723 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 22:16:29.412818 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 22:16:29.420070 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 22:16:29.422992 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 22:16:29.426512 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 22:16:29.432994 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 22:16:29.436508 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 22:16:29.439868 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 22:16:29.446584 0 7 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1829 22:16:29.450090 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 22:16:29.453642 0 7 24 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1831 22:16:29.459918 0 7 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1832 22:16:29.462942 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1833 22:16:29.466376 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1834 22:16:29.473349 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 22:16:29.476862 0 8 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1836 22:16:29.479727 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 22:16:29.486569 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 22:16:29.489897 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 22:16:29.493431 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 22:16:29.499940 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 22:16:29.503616 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 22:16:29.507150 0 9 8 | B1->B0 | 2d2d 3333 | 0 1 | (0 0) (1 1)
1843 22:16:29.510136 0 9 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1844 22:16:29.516794 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1845 22:16:29.520127 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1846 22:16:29.523398 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1847 22:16:29.529873 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1848 22:16:29.533018 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1849 22:16:29.537485 0 10 4 | B1->B0 | 3030 2f2f | 1 1 | (1 1) (1 1)
1850 22:16:29.543482 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 22:16:29.546714 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 22:16:29.549996 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 22:16:29.557194 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 22:16:29.560489 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 22:16:29.563639 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 22:16:29.570000 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1857 22:16:29.573559 0 11 4 | B1->B0 | 2d2d 3535 | 1 1 | (0 0) (0 0)
1858 22:16:29.576674 0 11 8 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
1859 22:16:29.583530 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1860 22:16:29.586899 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1861 22:16:29.590104 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1862 22:16:29.593793 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1863 22:16:29.599939 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1864 22:16:29.603320 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1865 22:16:29.606876 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1866 22:16:29.613200 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1867 22:16:29.617191 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 22:16:29.620092 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 22:16:29.626834 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 22:16:29.629974 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 22:16:29.633442 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 22:16:29.639871 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 22:16:29.643593 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 22:16:29.646837 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 22:16:29.653213 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 22:16:29.656799 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 22:16:29.660262 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 22:16:29.667205 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 22:16:29.669754 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1880 22:16:29.673187 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1881 22:16:29.680257 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1882 22:16:29.683193 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1883 22:16:29.686559 Total UI for P1: 0, mck2ui 16
1884 22:16:29.689698 best dqsien dly found for B0: ( 0, 14, 6)
1885 22:16:29.693281 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1886 22:16:29.696570 Total UI for P1: 0, mck2ui 16
1887 22:16:29.699860 best dqsien dly found for B1: ( 0, 14, 8)
1888 22:16:29.703537 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1889 22:16:29.706994 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1890 22:16:29.707076
1891 22:16:29.710174 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1892 22:16:29.713445 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1893 22:16:29.716806 [Gating] SW calibration Done
1894 22:16:29.716889 ==
1895 22:16:29.720190 Dram Type= 6, Freq= 0, CH_1, rank 1
1896 22:16:29.723527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1897 22:16:29.727194 ==
1898 22:16:29.727276 RX Vref Scan: 0
1899 22:16:29.727342
1900 22:16:29.730536 RX Vref 0 -> 0, step: 1
1901 22:16:29.730617
1902 22:16:29.733627 RX Delay -130 -> 252, step: 16
1903 22:16:29.737425 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1904 22:16:29.739929 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1905 22:16:29.743800 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1906 22:16:29.746773 iDelay=206, Bit 3, Center 77 (-34 ~ 189) 224
1907 22:16:29.753487 iDelay=206, Bit 4, Center 77 (-34 ~ 189) 224
1908 22:16:29.757117 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1909 22:16:29.760523 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1910 22:16:29.763480 iDelay=206, Bit 7, Center 77 (-34 ~ 189) 224
1911 22:16:29.767084 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
1912 22:16:29.773460 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1913 22:16:29.776622 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1914 22:16:29.779936 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1915 22:16:29.783940 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1916 22:16:29.786726 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1917 22:16:29.793673 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1918 22:16:29.796773 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1919 22:16:29.796888 ==
1920 22:16:29.800047 Dram Type= 6, Freq= 0, CH_1, rank 1
1921 22:16:29.803252 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1922 22:16:29.803336 ==
1923 22:16:29.807305 DQS Delay:
1924 22:16:29.807387 DQS0 = 0, DQS1 = 0
1925 22:16:29.807452 DQM Delay:
1926 22:16:29.810234 DQM0 = 80, DQM1 = 76
1927 22:16:29.810316 DQ Delay:
1928 22:16:29.813919 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =77
1929 22:16:29.817302 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1930 22:16:29.820521 DQ8 =61, DQ9 =69, DQ10 =69, DQ11 =69
1931 22:16:29.823675 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1932 22:16:29.823757
1933 22:16:29.823821
1934 22:16:29.823880 ==
1935 22:16:29.827722 Dram Type= 6, Freq= 0, CH_1, rank 1
1936 22:16:29.830265 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1937 22:16:29.833702 ==
1938 22:16:29.833783
1939 22:16:29.833846
1940 22:16:29.833919 TX Vref Scan disable
1941 22:16:29.836855 == TX Byte 0 ==
1942 22:16:29.840756 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1943 22:16:29.843761 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1944 22:16:29.847163 == TX Byte 1 ==
1945 22:16:29.850474 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1946 22:16:29.853839 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1947 22:16:29.856761 ==
1948 22:16:29.856842 Dram Type= 6, Freq= 0, CH_1, rank 1
1949 22:16:29.863326 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1950 22:16:29.863408 ==
1951 22:16:29.875353 TX Vref=22, minBit 6, minWin=27, winSum=441
1952 22:16:29.879436 TX Vref=24, minBit 0, minWin=27, winSum=442
1953 22:16:29.882047 TX Vref=26, minBit 10, minWin=27, winSum=446
1954 22:16:29.885400 TX Vref=28, minBit 15, minWin=27, winSum=449
1955 22:16:29.888734 TX Vref=30, minBit 13, minWin=27, winSum=453
1956 22:16:29.895427 TX Vref=32, minBit 0, minWin=28, winSum=452
1957 22:16:29.898551 [TxChooseVref] Worse bit 0, Min win 28, Win sum 452, Final Vref 32
1958 22:16:29.898655
1959 22:16:29.902404 Final TX Range 1 Vref 32
1960 22:16:29.902495
1961 22:16:29.902559 ==
1962 22:16:29.905478 Dram Type= 6, Freq= 0, CH_1, rank 1
1963 22:16:29.908886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1964 22:16:29.911646 ==
1965 22:16:29.911749
1966 22:16:29.911811
1967 22:16:29.911871 TX Vref Scan disable
1968 22:16:29.915775 == TX Byte 0 ==
1969 22:16:29.918899 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1970 22:16:29.922386 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1971 22:16:29.925589 == TX Byte 1 ==
1972 22:16:29.929140 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1973 22:16:29.932292 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1974 22:16:29.935514
1975 22:16:29.935608 [DATLAT]
1976 22:16:29.935674 Freq=800, CH1 RK1
1977 22:16:29.935736
1978 22:16:29.938654 DATLAT Default: 0xa
1979 22:16:29.938737 0, 0xFFFF, sum = 0
1980 22:16:29.942218 1, 0xFFFF, sum = 0
1981 22:16:29.942302 2, 0xFFFF, sum = 0
1982 22:16:29.945369 3, 0xFFFF, sum = 0
1983 22:16:29.945452 4, 0xFFFF, sum = 0
1984 22:16:29.948936 5, 0xFFFF, sum = 0
1985 22:16:29.952043 6, 0xFFFF, sum = 0
1986 22:16:29.952127 7, 0xFFFF, sum = 0
1987 22:16:29.955308 8, 0xFFFF, sum = 0
1988 22:16:29.955392 9, 0x0, sum = 1
1989 22:16:29.955459 10, 0x0, sum = 2
1990 22:16:29.959097 11, 0x0, sum = 3
1991 22:16:29.959181 12, 0x0, sum = 4
1992 22:16:29.962475 best_step = 10
1993 22:16:29.962558
1994 22:16:29.962623 ==
1995 22:16:29.965549 Dram Type= 6, Freq= 0, CH_1, rank 1
1996 22:16:29.969310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1997 22:16:29.969387 ==
1998 22:16:29.972393 RX Vref Scan: 0
1999 22:16:29.972465
2000 22:16:29.972526 RX Vref 0 -> 0, step: 1
2001 22:16:29.972586
2002 22:16:29.975127 RX Delay -111 -> 252, step: 8
2003 22:16:29.982359 iDelay=201, Bit 0, Center 80 (-31 ~ 192) 224
2004 22:16:29.985624 iDelay=201, Bit 1, Center 76 (-39 ~ 192) 232
2005 22:16:29.989304 iDelay=201, Bit 2, Center 68 (-47 ~ 184) 232
2006 22:16:29.992277 iDelay=201, Bit 3, Center 80 (-31 ~ 192) 224
2007 22:16:29.996135 iDelay=201, Bit 4, Center 80 (-31 ~ 192) 224
2008 22:16:30.002182 iDelay=201, Bit 5, Center 88 (-23 ~ 200) 224
2009 22:16:30.005876 iDelay=201, Bit 6, Center 88 (-23 ~ 200) 224
2010 22:16:30.009407 iDelay=201, Bit 7, Center 76 (-31 ~ 184) 216
2011 22:16:30.012345 iDelay=201, Bit 8, Center 64 (-55 ~ 184) 240
2012 22:16:30.015865 iDelay=201, Bit 9, Center 64 (-47 ~ 176) 224
2013 22:16:30.022871 iDelay=201, Bit 10, Center 72 (-47 ~ 192) 240
2014 22:16:30.025559 iDelay=201, Bit 11, Center 68 (-47 ~ 184) 232
2015 22:16:30.028890 iDelay=201, Bit 12, Center 84 (-31 ~ 200) 232
2016 22:16:30.032206 iDelay=201, Bit 13, Center 84 (-31 ~ 200) 232
2017 22:16:30.035727 iDelay=201, Bit 14, Center 80 (-39 ~ 200) 240
2018 22:16:30.042232 iDelay=201, Bit 15, Center 84 (-31 ~ 200) 232
2019 22:16:30.042312 ==
2020 22:16:30.046196 Dram Type= 6, Freq= 0, CH_1, rank 1
2021 22:16:30.049025 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2022 22:16:30.049098 ==
2023 22:16:30.049161 DQS Delay:
2024 22:16:30.052115 DQS0 = 0, DQS1 = 0
2025 22:16:30.052187 DQM Delay:
2026 22:16:30.055889 DQM0 = 79, DQM1 = 75
2027 22:16:30.055965 DQ Delay:
2028 22:16:30.058895 DQ0 =80, DQ1 =76, DQ2 =68, DQ3 =80
2029 22:16:30.062402 DQ4 =80, DQ5 =88, DQ6 =88, DQ7 =76
2030 22:16:30.065840 DQ8 =64, DQ9 =64, DQ10 =72, DQ11 =68
2031 22:16:30.069069 DQ12 =84, DQ13 =84, DQ14 =80, DQ15 =84
2032 22:16:30.069141
2033 22:16:30.069203
2034 22:16:30.075683 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f29, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 402 ps
2035 22:16:30.079041 CH1 RK1: MR19=606, MR18=1F29
2036 22:16:30.085797 CH1_RK1: MR19=0x606, MR18=0x1F29, DQSOSC=399, MR23=63, INC=92, DEC=61
2037 22:16:30.088818 [RxdqsGatingPostProcess] freq 800
2038 22:16:30.095873 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2039 22:16:30.098967 Pre-setting of DQS Precalculation
2040 22:16:30.102105 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2041 22:16:30.108789 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2042 22:16:30.116143 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2043 22:16:30.116241
2044 22:16:30.116307
2045 22:16:30.118869 [Calibration Summary] 1600 Mbps
2046 22:16:30.122690 CH 0, Rank 0
2047 22:16:30.122773 SW Impedance : PASS
2048 22:16:30.126237 DUTY Scan : NO K
2049 22:16:30.128820 ZQ Calibration : PASS
2050 22:16:30.128903 Jitter Meter : NO K
2051 22:16:30.132569 CBT Training : PASS
2052 22:16:30.136083 Write leveling : PASS
2053 22:16:30.136166 RX DQS gating : PASS
2054 22:16:30.139254 RX DQ/DQS(RDDQC) : PASS
2055 22:16:30.142399 TX DQ/DQS : PASS
2056 22:16:30.142482 RX DATLAT : PASS
2057 22:16:30.145858 RX DQ/DQS(Engine): PASS
2058 22:16:30.145941 TX OE : NO K
2059 22:16:30.148857 All Pass.
2060 22:16:30.148940
2061 22:16:30.149005 CH 0, Rank 1
2062 22:16:30.152262 SW Impedance : PASS
2063 22:16:30.152357 DUTY Scan : NO K
2064 22:16:30.155818 ZQ Calibration : PASS
2065 22:16:30.158931 Jitter Meter : NO K
2066 22:16:30.159010 CBT Training : PASS
2067 22:16:30.162268 Write leveling : PASS
2068 22:16:30.165815 RX DQS gating : PASS
2069 22:16:30.165902 RX DQ/DQS(RDDQC) : PASS
2070 22:16:30.169068 TX DQ/DQS : PASS
2071 22:16:30.172199 RX DATLAT : PASS
2072 22:16:30.172291 RX DQ/DQS(Engine): PASS
2073 22:16:30.175381 TX OE : NO K
2074 22:16:30.175489 All Pass.
2075 22:16:30.175574
2076 22:16:30.178852 CH 1, Rank 0
2077 22:16:30.178957 SW Impedance : PASS
2078 22:16:30.182568 DUTY Scan : NO K
2079 22:16:30.185803 ZQ Calibration : PASS
2080 22:16:30.185924 Jitter Meter : NO K
2081 22:16:30.188841 CBT Training : PASS
2082 22:16:30.192276 Write leveling : PASS
2083 22:16:30.192458 RX DQS gating : PASS
2084 22:16:30.195717 RX DQ/DQS(RDDQC) : PASS
2085 22:16:30.195868 TX DQ/DQS : PASS
2086 22:16:30.199259 RX DATLAT : PASS
2087 22:16:30.202445 RX DQ/DQS(Engine): PASS
2088 22:16:30.202698 TX OE : NO K
2089 22:16:30.205896 All Pass.
2090 22:16:30.206144
2091 22:16:30.206385 CH 1, Rank 1
2092 22:16:30.209026 SW Impedance : PASS
2093 22:16:30.209364 DUTY Scan : NO K
2094 22:16:30.212923 ZQ Calibration : PASS
2095 22:16:30.215834 Jitter Meter : NO K
2096 22:16:30.216322 CBT Training : PASS
2097 22:16:30.219249 Write leveling : PASS
2098 22:16:30.222558 RX DQS gating : PASS
2099 22:16:30.223010 RX DQ/DQS(RDDQC) : PASS
2100 22:16:30.225715 TX DQ/DQS : PASS
2101 22:16:30.229916 RX DATLAT : PASS
2102 22:16:30.230409 RX DQ/DQS(Engine): PASS
2103 22:16:30.232410 TX OE : NO K
2104 22:16:30.232867 All Pass.
2105 22:16:30.233271
2106 22:16:30.236362 DramC Write-DBI off
2107 22:16:30.238925 PER_BANK_REFRESH: Hybrid Mode
2108 22:16:30.239352 TX_TRACKING: ON
2109 22:16:30.242877 [GetDramInforAfterCalByMRR] Vendor 6.
2110 22:16:30.246157 [GetDramInforAfterCalByMRR] Revision 606.
2111 22:16:30.249462 [GetDramInforAfterCalByMRR] Revision 2 0.
2112 22:16:30.252401 MR0 0x3b3b
2113 22:16:30.252941 MR8 0x5151
2114 22:16:30.256042 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2115 22:16:30.256523
2116 22:16:30.256917 MR0 0x3b3b
2117 22:16:30.259732 MR8 0x5151
2118 22:16:30.262400 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2119 22:16:30.262919
2120 22:16:30.269196 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2121 22:16:30.272657 [FAST_K] Save calibration result to emmc
2122 22:16:30.279051 [FAST_K] Save calibration result to emmc
2123 22:16:30.279543 dram_init: config_dvfs: 1
2124 22:16:30.282968 dramc_set_vcore_voltage set vcore to 662500
2125 22:16:30.285976 Read voltage for 1200, 2
2126 22:16:30.286467 Vio18 = 0
2127 22:16:30.289223 Vcore = 662500
2128 22:16:30.289647 Vdram = 0
2129 22:16:30.289986 Vddq = 0
2130 22:16:30.292825 Vmddr = 0
2131 22:16:30.295858 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2132 22:16:30.302567 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2133 22:16:30.303148 MEM_TYPE=3, freq_sel=15
2134 22:16:30.306096 sv_algorithm_assistance_LP4_1600
2135 22:16:30.312508 ============ PULL DRAM RESETB DOWN ============
2136 22:16:30.315613 ========== PULL DRAM RESETB DOWN end =========
2137 22:16:30.319073 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2138 22:16:30.322632 ===================================
2139 22:16:30.325965 LPDDR4 DRAM CONFIGURATION
2140 22:16:30.329249 ===================================
2141 22:16:30.332795 EX_ROW_EN[0] = 0x0
2142 22:16:30.333210 EX_ROW_EN[1] = 0x0
2143 22:16:30.335715 LP4Y_EN = 0x0
2144 22:16:30.336255 WORK_FSP = 0x0
2145 22:16:30.338941 WL = 0x4
2146 22:16:30.339358 RL = 0x4
2147 22:16:30.342100 BL = 0x2
2148 22:16:30.342513 RPST = 0x0
2149 22:16:30.346044 RD_PRE = 0x0
2150 22:16:30.346459 WR_PRE = 0x1
2151 22:16:30.349221 WR_PST = 0x0
2152 22:16:30.349637 DBI_WR = 0x0
2153 22:16:30.352391 DBI_RD = 0x0
2154 22:16:30.352817 OTF = 0x1
2155 22:16:30.355751 ===================================
2156 22:16:30.359111 ===================================
2157 22:16:30.362586 ANA top config
2158 22:16:30.365601 ===================================
2159 22:16:30.366036 DLL_ASYNC_EN = 0
2160 22:16:30.369593 ALL_SLAVE_EN = 0
2161 22:16:30.372098 NEW_RANK_MODE = 1
2162 22:16:30.376013 DLL_IDLE_MODE = 1
2163 22:16:30.378718 LP45_APHY_COMB_EN = 1
2164 22:16:30.379135 TX_ODT_DIS = 1
2165 22:16:30.382097 NEW_8X_MODE = 1
2166 22:16:30.385388 ===================================
2167 22:16:30.388366 ===================================
2168 22:16:30.392071 data_rate = 2400
2169 22:16:30.395255 CKR = 1
2170 22:16:30.398670 DQ_P2S_RATIO = 8
2171 22:16:30.401960 ===================================
2172 22:16:30.402042 CA_P2S_RATIO = 8
2173 22:16:30.405598 DQ_CA_OPEN = 0
2174 22:16:30.408853 DQ_SEMI_OPEN = 0
2175 22:16:30.411889 CA_SEMI_OPEN = 0
2176 22:16:30.415326 CA_FULL_RATE = 0
2177 22:16:30.418641 DQ_CKDIV4_EN = 0
2178 22:16:30.418722 CA_CKDIV4_EN = 0
2179 22:16:30.421790 CA_PREDIV_EN = 0
2180 22:16:30.425428 PH8_DLY = 17
2181 22:16:30.428773 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2182 22:16:30.431749 DQ_AAMCK_DIV = 4
2183 22:16:30.435429 CA_AAMCK_DIV = 4
2184 22:16:30.435510 CA_ADMCK_DIV = 4
2185 22:16:30.438498 DQ_TRACK_CA_EN = 0
2186 22:16:30.441835 CA_PICK = 1200
2187 22:16:30.445278 CA_MCKIO = 1200
2188 22:16:30.449120 MCKIO_SEMI = 0
2189 22:16:30.451710 PLL_FREQ = 2366
2190 22:16:30.455316 DQ_UI_PI_RATIO = 32
2191 22:16:30.455397 CA_UI_PI_RATIO = 0
2192 22:16:30.459015 ===================================
2193 22:16:30.462567 ===================================
2194 22:16:30.465058 memory_type:LPDDR4
2195 22:16:30.468654 GP_NUM : 10
2196 22:16:30.468735 SRAM_EN : 1
2197 22:16:30.471990 MD32_EN : 0
2198 22:16:30.475313 ===================================
2199 22:16:30.478652 [ANA_INIT] >>>>>>>>>>>>>>
2200 22:16:30.481786 <<<<<< [CONFIGURE PHASE]: ANA_TX
2201 22:16:30.485306 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2202 22:16:30.488586 ===================================
2203 22:16:30.488667 data_rate = 2400,PCW = 0X5b00
2204 22:16:30.492474 ===================================
2205 22:16:30.495680 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2206 22:16:30.502225 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2207 22:16:30.508907 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2208 22:16:30.512065 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2209 22:16:30.515471 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2210 22:16:30.518868 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2211 22:16:30.521982 [ANA_INIT] flow start
2212 22:16:30.522056 [ANA_INIT] PLL >>>>>>>>
2213 22:16:30.525948 [ANA_INIT] PLL <<<<<<<<
2214 22:16:30.528586 [ANA_INIT] MIDPI >>>>>>>>
2215 22:16:30.532418 [ANA_INIT] MIDPI <<<<<<<<
2216 22:16:30.532496 [ANA_INIT] DLL >>>>>>>>
2217 22:16:30.535309 [ANA_INIT] DLL <<<<<<<<
2218 22:16:30.535378 [ANA_INIT] flow end
2219 22:16:30.542195 ============ LP4 DIFF to SE enter ============
2220 22:16:30.545402 ============ LP4 DIFF to SE exit ============
2221 22:16:30.548881 [ANA_INIT] <<<<<<<<<<<<<
2222 22:16:30.551883 [Flow] Enable top DCM control >>>>>
2223 22:16:30.555625 [Flow] Enable top DCM control <<<<<
2224 22:16:30.555694 Enable DLL master slave shuffle
2225 22:16:30.562330 ==============================================================
2226 22:16:30.566108 Gating Mode config
2227 22:16:30.569000 ==============================================================
2228 22:16:30.572045 Config description:
2229 22:16:30.583172 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2230 22:16:30.588887 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2231 22:16:30.592405 SELPH_MODE 0: By rank 1: By Phase
2232 22:16:30.598955 ==============================================================
2233 22:16:30.601920 GAT_TRACK_EN = 1
2234 22:16:30.605678 RX_GATING_MODE = 2
2235 22:16:30.609055 RX_GATING_TRACK_MODE = 2
2236 22:16:30.609124 SELPH_MODE = 1
2237 22:16:30.612171 PICG_EARLY_EN = 1
2238 22:16:30.615594 VALID_LAT_VALUE = 1
2239 22:16:30.621922 ==============================================================
2240 22:16:30.625617 Enter into Gating configuration >>>>
2241 22:16:30.629094 Exit from Gating configuration <<<<
2242 22:16:30.631700 Enter into DVFS_PRE_config >>>>>
2243 22:16:30.642228 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2244 22:16:30.645262 Exit from DVFS_PRE_config <<<<<
2245 22:16:30.648470 Enter into PICG configuration >>>>
2246 22:16:30.651854 Exit from PICG configuration <<<<
2247 22:16:30.655297 [RX_INPUT] configuration >>>>>
2248 22:16:30.658804 [RX_INPUT] configuration <<<<<
2249 22:16:30.661730 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2250 22:16:30.668791 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2251 22:16:30.675833 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2252 22:16:30.681882 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2253 22:16:30.689199 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2254 22:16:30.691676 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2255 22:16:30.698601 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2256 22:16:30.702148 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2257 22:16:30.704757 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2258 22:16:30.708317 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2259 22:16:30.715101 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2260 22:16:30.718094 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2261 22:16:30.721400 ===================================
2262 22:16:30.724873 LPDDR4 DRAM CONFIGURATION
2263 22:16:30.728121 ===================================
2264 22:16:30.728223 EX_ROW_EN[0] = 0x0
2265 22:16:30.731810 EX_ROW_EN[1] = 0x0
2266 22:16:30.731927 LP4Y_EN = 0x0
2267 22:16:30.734780 WORK_FSP = 0x0
2268 22:16:30.734880 WL = 0x4
2269 22:16:30.737980 RL = 0x4
2270 22:16:30.738095 BL = 0x2
2271 22:16:30.741684 RPST = 0x0
2272 22:16:30.741786 RD_PRE = 0x0
2273 22:16:30.744902 WR_PRE = 0x1
2274 22:16:30.744978 WR_PST = 0x0
2275 22:16:30.748262 DBI_WR = 0x0
2276 22:16:30.748335 DBI_RD = 0x0
2277 22:16:30.751506 OTF = 0x1
2278 22:16:30.754940 ===================================
2279 22:16:30.758436 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2280 22:16:30.761602 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2281 22:16:30.768050 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2282 22:16:30.771338 ===================================
2283 22:16:30.771437 LPDDR4 DRAM CONFIGURATION
2284 22:16:30.774722 ===================================
2285 22:16:30.778333 EX_ROW_EN[0] = 0x10
2286 22:16:30.781210 EX_ROW_EN[1] = 0x0
2287 22:16:30.781282 LP4Y_EN = 0x0
2288 22:16:30.785632 WORK_FSP = 0x0
2289 22:16:30.785709 WL = 0x4
2290 22:16:30.787876 RL = 0x4
2291 22:16:30.787982 BL = 0x2
2292 22:16:30.791768 RPST = 0x0
2293 22:16:30.791840 RD_PRE = 0x0
2294 22:16:30.794349 WR_PRE = 0x1
2295 22:16:30.794416 WR_PST = 0x0
2296 22:16:30.797927 DBI_WR = 0x0
2297 22:16:30.798011 DBI_RD = 0x0
2298 22:16:30.801008 OTF = 0x1
2299 22:16:30.804667 ===================================
2300 22:16:30.811461 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2301 22:16:30.811542 ==
2302 22:16:30.814972 Dram Type= 6, Freq= 0, CH_0, rank 0
2303 22:16:30.817696 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2304 22:16:30.817766 ==
2305 22:16:30.821278 [Duty_Offset_Calibration]
2306 22:16:30.821346 B0:2 B1:-1 CA:1
2307 22:16:30.821406
2308 22:16:30.824801 [DutyScan_Calibration_Flow] k_type=0
2309 22:16:30.834043
2310 22:16:30.834117 ==CLK 0==
2311 22:16:30.837371 Final CLK duty delay cell = -4
2312 22:16:30.841063 [-4] MAX Duty = 5031%(X100), DQS PI = 4
2313 22:16:30.844238 [-4] MIN Duty = 4875%(X100), DQS PI = 32
2314 22:16:30.847431 [-4] AVG Duty = 4953%(X100)
2315 22:16:30.847505
2316 22:16:30.850670 CH0 CLK Duty spec in!! Max-Min= 156%
2317 22:16:30.854392 [DutyScan_Calibration_Flow] ====Done====
2318 22:16:30.854485
2319 22:16:30.858145 [DutyScan_Calibration_Flow] k_type=1
2320 22:16:30.872270
2321 22:16:30.872368 ==DQS 0 ==
2322 22:16:30.875535 Final DQS duty delay cell = -4
2323 22:16:30.879107 [-4] MAX Duty = 5000%(X100), DQS PI = 44
2324 22:16:30.882287 [-4] MIN Duty = 4876%(X100), DQS PI = 12
2325 22:16:30.886050 [-4] AVG Duty = 4938%(X100)
2326 22:16:30.886121
2327 22:16:30.886182 ==DQS 1 ==
2328 22:16:30.889221 Final DQS duty delay cell = -4
2329 22:16:30.892568 [-4] MAX Duty = 5124%(X100), DQS PI = 16
2330 22:16:30.896170 [-4] MIN Duty = 5000%(X100), DQS PI = 42
2331 22:16:30.899135 [-4] AVG Duty = 5062%(X100)
2332 22:16:30.899217
2333 22:16:30.902243 CH0 DQS 0 Duty spec in!! Max-Min= 124%
2334 22:16:30.902329
2335 22:16:30.905643 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2336 22:16:30.909043 [DutyScan_Calibration_Flow] ====Done====
2337 22:16:30.909115
2338 22:16:30.912275 [DutyScan_Calibration_Flow] k_type=3
2339 22:16:30.929906
2340 22:16:30.929983 ==DQM 0 ==
2341 22:16:30.933042 Final DQM duty delay cell = 0
2342 22:16:30.936170 [0] MAX Duty = 5000%(X100), DQS PI = 46
2343 22:16:30.939670 [0] MIN Duty = 4907%(X100), DQS PI = 0
2344 22:16:30.939740 [0] AVG Duty = 4953%(X100)
2345 22:16:30.942743
2346 22:16:30.942837 ==DQM 1 ==
2347 22:16:30.946446 Final DQM duty delay cell = 0
2348 22:16:30.949841 [0] MAX Duty = 5156%(X100), DQS PI = 62
2349 22:16:30.953386 [0] MIN Duty = 4969%(X100), DQS PI = 10
2350 22:16:30.953478 [0] AVG Duty = 5062%(X100)
2351 22:16:30.956942
2352 22:16:30.959966 CH0 DQM 0 Duty spec in!! Max-Min= 93%
2353 22:16:30.960076
2354 22:16:30.963442 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2355 22:16:30.966525 [DutyScan_Calibration_Flow] ====Done====
2356 22:16:30.966634
2357 22:16:30.969545 [DutyScan_Calibration_Flow] k_type=2
2358 22:16:30.985507
2359 22:16:30.985593 ==DQ 0 ==
2360 22:16:30.989168 Final DQ duty delay cell = -4
2361 22:16:30.992347 [-4] MAX Duty = 5062%(X100), DQS PI = 54
2362 22:16:30.995305 [-4] MIN Duty = 4876%(X100), DQS PI = 18
2363 22:16:30.998689 [-4] AVG Duty = 4969%(X100)
2364 22:16:30.998767
2365 22:16:30.998830 ==DQ 1 ==
2366 22:16:31.002040 Final DQ duty delay cell = 0
2367 22:16:31.005287 [0] MAX Duty = 5031%(X100), DQS PI = 18
2368 22:16:31.009134 [0] MIN Duty = 4907%(X100), DQS PI = 46
2369 22:16:31.009219 [0] AVG Duty = 4969%(X100)
2370 22:16:31.012534
2371 22:16:31.015690 CH0 DQ 0 Duty spec in!! Max-Min= 186%
2372 22:16:31.015783
2373 22:16:31.019198 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2374 22:16:31.022266 [DutyScan_Calibration_Flow] ====Done====
2375 22:16:31.022378 ==
2376 22:16:31.025913 Dram Type= 6, Freq= 0, CH_1, rank 0
2377 22:16:31.029319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2378 22:16:31.029425 ==
2379 22:16:31.032543 [Duty_Offset_Calibration]
2380 22:16:31.032657 B0:1 B1:1 CA:2
2381 22:16:31.032754
2382 22:16:31.035830 [DutyScan_Calibration_Flow] k_type=0
2383 22:16:31.046111
2384 22:16:31.046303 ==CLK 0==
2385 22:16:31.049511 Final CLK duty delay cell = 0
2386 22:16:31.052384 [0] MAX Duty = 5187%(X100), DQS PI = 24
2387 22:16:31.055627 [0] MIN Duty = 4938%(X100), DQS PI = 48
2388 22:16:31.055846 [0] AVG Duty = 5062%(X100)
2389 22:16:31.058925
2390 22:16:31.062604 CH1 CLK Duty spec in!! Max-Min= 249%
2391 22:16:31.066228 [DutyScan_Calibration_Flow] ====Done====
2392 22:16:31.066575
2393 22:16:31.069097 [DutyScan_Calibration_Flow] k_type=1
2394 22:16:31.085755
2395 22:16:31.086202 ==DQS 0 ==
2396 22:16:31.088838 Final DQS duty delay cell = 0
2397 22:16:31.092629 [0] MAX Duty = 5031%(X100), DQS PI = 18
2398 22:16:31.095159 [0] MIN Duty = 4844%(X100), DQS PI = 50
2399 22:16:31.095597 [0] AVG Duty = 4937%(X100)
2400 22:16:31.098891
2401 22:16:31.099384 ==DQS 1 ==
2402 22:16:31.101964 Final DQS duty delay cell = 0
2403 22:16:31.105923 [0] MAX Duty = 5062%(X100), DQS PI = 36
2404 22:16:31.108962 [0] MIN Duty = 4907%(X100), DQS PI = 16
2405 22:16:31.109411 [0] AVG Duty = 4984%(X100)
2406 22:16:31.112249
2407 22:16:31.115758 CH1 DQS 0 Duty spec in!! Max-Min= 187%
2408 22:16:31.116357
2409 22:16:31.118880 CH1 DQS 1 Duty spec in!! Max-Min= 155%
2410 22:16:31.122320 [DutyScan_Calibration_Flow] ====Done====
2411 22:16:31.122872
2412 22:16:31.125389 [DutyScan_Calibration_Flow] k_type=3
2413 22:16:31.141754
2414 22:16:31.142366 ==DQM 0 ==
2415 22:16:31.145519 Final DQM duty delay cell = 0
2416 22:16:31.148408 [0] MAX Duty = 5093%(X100), DQS PI = 18
2417 22:16:31.151873 [0] MIN Duty = 4907%(X100), DQS PI = 48
2418 22:16:31.152453 [0] AVG Duty = 5000%(X100)
2419 22:16:31.155715
2420 22:16:31.156304 ==DQM 1 ==
2421 22:16:31.158701 Final DQM duty delay cell = 0
2422 22:16:31.161870 [0] MAX Duty = 5156%(X100), DQS PI = 62
2423 22:16:31.165308 [0] MIN Duty = 4938%(X100), DQS PI = 22
2424 22:16:31.165762 [0] AVG Duty = 5047%(X100)
2425 22:16:31.168671
2426 22:16:31.171948 CH1 DQM 0 Duty spec in!! Max-Min= 186%
2427 22:16:31.172438
2428 22:16:31.175846 CH1 DQM 1 Duty spec in!! Max-Min= 218%
2429 22:16:31.178679 [DutyScan_Calibration_Flow] ====Done====
2430 22:16:31.179088
2431 22:16:31.181982 [DutyScan_Calibration_Flow] k_type=2
2432 22:16:31.198280
2433 22:16:31.198800 ==DQ 0 ==
2434 22:16:31.201932 Final DQ duty delay cell = 0
2435 22:16:31.205758 [0] MAX Duty = 5093%(X100), DQS PI = 18
2436 22:16:31.208867 [0] MIN Duty = 4938%(X100), DQS PI = 50
2437 22:16:31.209381 [0] AVG Duty = 5015%(X100)
2438 22:16:31.211827
2439 22:16:31.212432 ==DQ 1 ==
2440 22:16:31.215196 Final DQ duty delay cell = 0
2441 22:16:31.218493 [0] MAX Duty = 5093%(X100), DQS PI = 8
2442 22:16:31.222248 [0] MIN Duty = 5031%(X100), DQS PI = 2
2443 22:16:31.222824 [0] AVG Duty = 5062%(X100)
2444 22:16:31.223304
2445 22:16:31.225382 CH1 DQ 0 Duty spec in!! Max-Min= 155%
2446 22:16:31.225823
2447 22:16:31.228277 CH1 DQ 1 Duty spec in!! Max-Min= 62%
2448 22:16:31.235384 [DutyScan_Calibration_Flow] ====Done====
2449 22:16:31.238228 nWR fixed to 30
2450 22:16:31.238655 [ModeRegInit_LP4] CH0 RK0
2451 22:16:31.241920 [ModeRegInit_LP4] CH0 RK1
2452 22:16:31.245659 [ModeRegInit_LP4] CH1 RK0
2453 22:16:31.246183 [ModeRegInit_LP4] CH1 RK1
2454 22:16:31.248424 match AC timing 7
2455 22:16:31.251996 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2456 22:16:31.255169 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2457 22:16:31.262106 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2458 22:16:31.265266 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2459 22:16:31.271945 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2460 22:16:31.272435 ==
2461 22:16:31.275202 Dram Type= 6, Freq= 0, CH_0, rank 0
2462 22:16:31.278331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2463 22:16:31.278769 ==
2464 22:16:31.284951 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2465 22:16:31.288175 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2466 22:16:31.298528 [CA 0] Center 40 (10~71) winsize 62
2467 22:16:31.302175 [CA 1] Center 39 (9~70) winsize 62
2468 22:16:31.304991 [CA 2] Center 36 (6~67) winsize 62
2469 22:16:31.308926 [CA 3] Center 35 (5~66) winsize 62
2470 22:16:31.311592 [CA 4] Center 34 (4~65) winsize 62
2471 22:16:31.314708 [CA 5] Center 34 (4~64) winsize 61
2472 22:16:31.315265
2473 22:16:31.318419 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2474 22:16:31.318986
2475 22:16:31.321741 [CATrainingPosCal] consider 1 rank data
2476 22:16:31.325085 u2DelayCellTimex100 = 270/100 ps
2477 22:16:31.328621 CA0 delay=40 (10~71),Diff = 6 PI (28 cell)
2478 22:16:31.334653 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2479 22:16:31.338106 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2480 22:16:31.341175 CA3 delay=35 (5~66),Diff = 1 PI (4 cell)
2481 22:16:31.344913 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
2482 22:16:31.348317 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2483 22:16:31.348753
2484 22:16:31.351944 CA PerBit enable=1, Macro0, CA PI delay=34
2485 22:16:31.352420
2486 22:16:31.355044 [CBTSetCACLKResult] CA Dly = 34
2487 22:16:31.355469 CS Dly: 7 (0~38)
2488 22:16:31.358112 ==
2489 22:16:31.361683 Dram Type= 6, Freq= 0, CH_0, rank 1
2490 22:16:31.364946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2491 22:16:31.365376 ==
2492 22:16:31.368199 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2493 22:16:31.375018 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2494 22:16:31.384328 [CA 0] Center 39 (9~70) winsize 62
2495 22:16:31.387599 [CA 1] Center 39 (9~70) winsize 62
2496 22:16:31.390837 [CA 2] Center 36 (6~67) winsize 62
2497 22:16:31.394447 [CA 3] Center 36 (5~67) winsize 63
2498 22:16:31.397481 [CA 4] Center 34 (4~65) winsize 62
2499 22:16:31.400475 [CA 5] Center 34 (4~64) winsize 61
2500 22:16:31.401083
2501 22:16:31.403817 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2502 22:16:31.404334
2503 22:16:31.407555 [CATrainingPosCal] consider 2 rank data
2504 22:16:31.410890 u2DelayCellTimex100 = 270/100 ps
2505 22:16:31.414086 CA0 delay=40 (10~70),Diff = 6 PI (28 cell)
2506 22:16:31.417682 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2507 22:16:31.424734 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2508 22:16:31.427569 CA3 delay=35 (5~66),Diff = 1 PI (4 cell)
2509 22:16:31.430645 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
2510 22:16:31.434300 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2511 22:16:31.434875
2512 22:16:31.437699 CA PerBit enable=1, Macro0, CA PI delay=34
2513 22:16:31.438316
2514 22:16:31.441105 [CBTSetCACLKResult] CA Dly = 34
2515 22:16:31.441716 CS Dly: 8 (0~41)
2516 22:16:31.442226
2517 22:16:31.444416 ----->DramcWriteLeveling(PI) begin...
2518 22:16:31.447207 ==
2519 22:16:31.451194 Dram Type= 6, Freq= 0, CH_0, rank 0
2520 22:16:31.453934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2521 22:16:31.454501 ==
2522 22:16:31.457271 Write leveling (Byte 0): 30 => 30
2523 22:16:31.460877 Write leveling (Byte 1): 30 => 30
2524 22:16:31.464225 DramcWriteLeveling(PI) end<-----
2525 22:16:31.464729
2526 22:16:31.465268 ==
2527 22:16:31.467520 Dram Type= 6, Freq= 0, CH_0, rank 0
2528 22:16:31.470888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2529 22:16:31.471473 ==
2530 22:16:31.474062 [Gating] SW mode calibration
2531 22:16:31.480799 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2532 22:16:31.487517 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2533 22:16:31.490893 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2534 22:16:31.493747 0 15 4 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
2535 22:16:31.500574 0 15 8 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
2536 22:16:31.504017 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2537 22:16:31.507171 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2538 22:16:31.510427 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2539 22:16:31.517551 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2540 22:16:31.520905 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2541 22:16:31.524579 1 0 0 | B1->B0 | 3434 2d2d | 0 0 | (0 1) (1 0)
2542 22:16:31.530789 1 0 4 | B1->B0 | 2c2c 2323 | 0 0 | (1 0) (0 0)
2543 22:16:31.533752 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2544 22:16:31.537307 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2545 22:16:31.544187 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2546 22:16:31.547707 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2547 22:16:31.550435 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2548 22:16:31.557369 1 0 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2549 22:16:31.561050 1 1 0 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
2550 22:16:31.564126 1 1 4 | B1->B0 | 3d3d 4545 | 0 0 | (0 0) (0 0)
2551 22:16:31.570205 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2552 22:16:31.573580 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2553 22:16:31.577025 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2554 22:16:31.583891 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2555 22:16:31.587311 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2556 22:16:31.590553 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2557 22:16:31.597143 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2558 22:16:31.600251 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 22:16:31.603392 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2560 22:16:31.610339 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 22:16:31.613812 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 22:16:31.617617 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 22:16:31.620795 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 22:16:31.626665 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 22:16:31.630446 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 22:16:31.633632 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 22:16:31.640507 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 22:16:31.643808 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 22:16:31.647143 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2570 22:16:31.653465 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2571 22:16:31.656775 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2572 22:16:31.660316 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2573 22:16:31.666993 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2574 22:16:31.670540 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2575 22:16:31.673602 Total UI for P1: 0, mck2ui 16
2576 22:16:31.676724 best dqsien dly found for B0: ( 1, 4, 0)
2577 22:16:31.680564 Total UI for P1: 0, mck2ui 16
2578 22:16:31.683848 best dqsien dly found for B1: ( 1, 4, 0)
2579 22:16:31.686909 best DQS0 dly(MCK, UI, PI) = (1, 4, 0)
2580 22:16:31.690360 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2581 22:16:31.690914
2582 22:16:31.693683 best DQS0 P1 dly(MCK, UI, PI) = (1, 8, 0)
2583 22:16:31.696969 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2584 22:16:31.700611 [Gating] SW calibration Done
2585 22:16:31.701046 ==
2586 22:16:31.703748 Dram Type= 6, Freq= 0, CH_0, rank 0
2587 22:16:31.707095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2588 22:16:31.707515 ==
2589 22:16:31.710331 RX Vref Scan: 0
2590 22:16:31.710747
2591 22:16:31.713589 RX Vref 0 -> 0, step: 1
2592 22:16:31.714004
2593 22:16:31.714333 RX Delay -40 -> 252, step: 8
2594 22:16:31.719769 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2595 22:16:31.723474 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2596 22:16:31.727029 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2597 22:16:31.730017 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2598 22:16:31.733078 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2599 22:16:31.739929 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2600 22:16:31.743287 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2601 22:16:31.746900 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2602 22:16:31.750013 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2603 22:16:31.753731 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2604 22:16:31.759790 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2605 22:16:31.763467 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2606 22:16:31.766962 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2607 22:16:31.769812 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2608 22:16:31.773299 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2609 22:16:31.779810 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2610 22:16:31.779892 ==
2611 22:16:31.783210 Dram Type= 6, Freq= 0, CH_0, rank 0
2612 22:16:31.786723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2613 22:16:31.786805 ==
2614 22:16:31.786871 DQS Delay:
2615 22:16:31.789773 DQS0 = 0, DQS1 = 0
2616 22:16:31.789854 DQM Delay:
2617 22:16:31.792963 DQM0 = 115, DQM1 = 107
2618 22:16:31.793045 DQ Delay:
2619 22:16:31.796216 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =111
2620 22:16:31.799706 DQ4 =115, DQ5 =111, DQ6 =123, DQ7 =123
2621 22:16:31.803034 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =99
2622 22:16:31.806601 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115
2623 22:16:31.806715
2624 22:16:31.806781
2625 22:16:31.806842 ==
2626 22:16:31.810380 Dram Type= 6, Freq= 0, CH_0, rank 0
2627 22:16:31.816658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2628 22:16:31.816741 ==
2629 22:16:31.816804
2630 22:16:31.816864
2631 22:16:31.816923 TX Vref Scan disable
2632 22:16:31.820057 == TX Byte 0 ==
2633 22:16:31.823533 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2634 22:16:31.826683 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2635 22:16:31.829904 == TX Byte 1 ==
2636 22:16:31.833504 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2637 22:16:31.836681 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2638 22:16:31.840150 ==
2639 22:16:31.843379 Dram Type= 6, Freq= 0, CH_0, rank 0
2640 22:16:31.846785 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2641 22:16:31.846867 ==
2642 22:16:31.858080 TX Vref=22, minBit 1, minWin=24, winSum=416
2643 22:16:31.861424 TX Vref=24, minBit 1, minWin=25, winSum=418
2644 22:16:31.864322 TX Vref=26, minBit 0, minWin=26, winSum=425
2645 22:16:31.867558 TX Vref=28, minBit 0, minWin=26, winSum=428
2646 22:16:31.871032 TX Vref=30, minBit 0, minWin=26, winSum=431
2647 22:16:31.874767 TX Vref=32, minBit 5, minWin=26, winSum=437
2648 22:16:31.880879 [TxChooseVref] Worse bit 5, Min win 26, Win sum 437, Final Vref 32
2649 22:16:31.880962
2650 22:16:31.884773 Final TX Range 1 Vref 32
2651 22:16:31.884855
2652 22:16:31.884939 ==
2653 22:16:31.887725 Dram Type= 6, Freq= 0, CH_0, rank 0
2654 22:16:31.890769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2655 22:16:31.890852 ==
2656 22:16:31.894549
2657 22:16:31.894630
2658 22:16:31.894694 TX Vref Scan disable
2659 22:16:31.898199 == TX Byte 0 ==
2660 22:16:31.900956 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2661 22:16:31.904879 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2662 22:16:31.907839 == TX Byte 1 ==
2663 22:16:31.911334 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2664 22:16:31.914726 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2665 22:16:31.914808
2666 22:16:31.917785 [DATLAT]
2667 22:16:31.917867 Freq=1200, CH0 RK0
2668 22:16:31.917932
2669 22:16:31.920915 DATLAT Default: 0xd
2670 22:16:31.920996 0, 0xFFFF, sum = 0
2671 22:16:31.924201 1, 0xFFFF, sum = 0
2672 22:16:31.924284 2, 0xFFFF, sum = 0
2673 22:16:31.927532 3, 0xFFFF, sum = 0
2674 22:16:31.927614 4, 0xFFFF, sum = 0
2675 22:16:31.931324 5, 0xFFFF, sum = 0
2676 22:16:31.931407 6, 0xFFFF, sum = 0
2677 22:16:31.934377 7, 0xFFFF, sum = 0
2678 22:16:31.934460 8, 0xFFFF, sum = 0
2679 22:16:31.937956 9, 0xFFFF, sum = 0
2680 22:16:31.941358 10, 0xFFFF, sum = 0
2681 22:16:31.941441 11, 0xFFFF, sum = 0
2682 22:16:31.944316 12, 0x0, sum = 1
2683 22:16:31.944398 13, 0x0, sum = 2
2684 22:16:31.944464 14, 0x0, sum = 3
2685 22:16:31.947567 15, 0x0, sum = 4
2686 22:16:31.947649 best_step = 13
2687 22:16:31.947714
2688 22:16:31.951084 ==
2689 22:16:31.951166 Dram Type= 6, Freq= 0, CH_0, rank 0
2690 22:16:31.957589 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2691 22:16:31.957674 ==
2692 22:16:31.957740 RX Vref Scan: 1
2693 22:16:31.957799
2694 22:16:31.961052 Set Vref Range= 32 -> 127
2695 22:16:31.961134
2696 22:16:31.964235 RX Vref 32 -> 127, step: 1
2697 22:16:31.964316
2698 22:16:31.968209 RX Delay -21 -> 252, step: 4
2699 22:16:31.968290
2700 22:16:31.971222 Set Vref, RX VrefLevel [Byte0]: 32
2701 22:16:31.974466 [Byte1]: 32
2702 22:16:31.974548
2703 22:16:31.978043 Set Vref, RX VrefLevel [Byte0]: 33
2704 22:16:31.981177 [Byte1]: 33
2705 22:16:31.981320
2706 22:16:31.984463 Set Vref, RX VrefLevel [Byte0]: 34
2707 22:16:31.987489 [Byte1]: 34
2708 22:16:31.991881
2709 22:16:31.992024 Set Vref, RX VrefLevel [Byte0]: 35
2710 22:16:31.995183 [Byte1]: 35
2711 22:16:32.000004
2712 22:16:32.000099 Set Vref, RX VrefLevel [Byte0]: 36
2713 22:16:32.003245 [Byte1]: 36
2714 22:16:32.007815
2715 22:16:32.007897 Set Vref, RX VrefLevel [Byte0]: 37
2716 22:16:32.011354 [Byte1]: 37
2717 22:16:32.015530
2718 22:16:32.015627 Set Vref, RX VrefLevel [Byte0]: 38
2719 22:16:32.019375 [Byte1]: 38
2720 22:16:32.023843
2721 22:16:32.023924 Set Vref, RX VrefLevel [Byte0]: 39
2722 22:16:32.026980 [Byte1]: 39
2723 22:16:32.031472
2724 22:16:32.031553 Set Vref, RX VrefLevel [Byte0]: 40
2725 22:16:32.034831 [Byte1]: 40
2726 22:16:32.039398
2727 22:16:32.039479 Set Vref, RX VrefLevel [Byte0]: 41
2728 22:16:32.043074 [Byte1]: 41
2729 22:16:32.047704
2730 22:16:32.047792 Set Vref, RX VrefLevel [Byte0]: 42
2731 22:16:32.050577 [Byte1]: 42
2732 22:16:32.055113
2733 22:16:32.055207 Set Vref, RX VrefLevel [Byte0]: 43
2734 22:16:32.058826 [Byte1]: 43
2735 22:16:32.063348
2736 22:16:32.063458 Set Vref, RX VrefLevel [Byte0]: 44
2737 22:16:32.066541 [Byte1]: 44
2738 22:16:32.071289
2739 22:16:32.071410 Set Vref, RX VrefLevel [Byte0]: 45
2740 22:16:32.075057 [Byte1]: 45
2741 22:16:32.079224
2742 22:16:32.079423 Set Vref, RX VrefLevel [Byte0]: 46
2743 22:16:32.082872 [Byte1]: 46
2744 22:16:32.087381
2745 22:16:32.087798 Set Vref, RX VrefLevel [Byte0]: 47
2746 22:16:32.090798 [Byte1]: 47
2747 22:16:32.095175
2748 22:16:32.095595 Set Vref, RX VrefLevel [Byte0]: 48
2749 22:16:32.098507 [Byte1]: 48
2750 22:16:32.103989
2751 22:16:32.104427 Set Vref, RX VrefLevel [Byte0]: 49
2752 22:16:32.106889 [Byte1]: 49
2753 22:16:32.110882
2754 22:16:32.111299 Set Vref, RX VrefLevel [Byte0]: 50
2755 22:16:32.114478 [Byte1]: 50
2756 22:16:32.119114
2757 22:16:32.119533 Set Vref, RX VrefLevel [Byte0]: 51
2758 22:16:32.122308 [Byte1]: 51
2759 22:16:32.127124
2760 22:16:32.127541 Set Vref, RX VrefLevel [Byte0]: 52
2761 22:16:32.130287 [Byte1]: 52
2762 22:16:32.135113
2763 22:16:32.135545 Set Vref, RX VrefLevel [Byte0]: 53
2764 22:16:32.138627 [Byte1]: 53
2765 22:16:32.142953
2766 22:16:32.143368 Set Vref, RX VrefLevel [Byte0]: 54
2767 22:16:32.146102 [Byte1]: 54
2768 22:16:32.150778
2769 22:16:32.151279 Set Vref, RX VrefLevel [Byte0]: 55
2770 22:16:32.154124 [Byte1]: 55
2771 22:16:32.158618
2772 22:16:32.159053 Set Vref, RX VrefLevel [Byte0]: 56
2773 22:16:32.162517 [Byte1]: 56
2774 22:16:32.166631
2775 22:16:32.167081 Set Vref, RX VrefLevel [Byte0]: 57
2776 22:16:32.169841 [Byte1]: 57
2777 22:16:32.175204
2778 22:16:32.175621 Set Vref, RX VrefLevel [Byte0]: 58
2779 22:16:32.177951 [Byte1]: 58
2780 22:16:32.182732
2781 22:16:32.183151 Set Vref, RX VrefLevel [Byte0]: 59
2782 22:16:32.185562 [Byte1]: 59
2783 22:16:32.190727
2784 22:16:32.191145 Set Vref, RX VrefLevel [Byte0]: 60
2785 22:16:32.193514 [Byte1]: 60
2786 22:16:32.198013
2787 22:16:32.198477 Set Vref, RX VrefLevel [Byte0]: 61
2788 22:16:32.201494 [Byte1]: 61
2789 22:16:32.206589
2790 22:16:32.207005 Set Vref, RX VrefLevel [Byte0]: 62
2791 22:16:32.210026 [Byte1]: 62
2792 22:16:32.215080
2793 22:16:32.215500 Set Vref, RX VrefLevel [Byte0]: 63
2794 22:16:32.217739 [Byte1]: 63
2795 22:16:32.222118
2796 22:16:32.225622 Set Vref, RX VrefLevel [Byte0]: 64
2797 22:16:32.228966 [Byte1]: 64
2798 22:16:32.229389
2799 22:16:32.232287 Set Vref, RX VrefLevel [Byte0]: 65
2800 22:16:32.235134 [Byte1]: 65
2801 22:16:32.235552
2802 22:16:32.238538 Set Vref, RX VrefLevel [Byte0]: 66
2803 22:16:32.242296 [Byte1]: 66
2804 22:16:32.246070
2805 22:16:32.246489 Set Vref, RX VrefLevel [Byte0]: 67
2806 22:16:32.249504 [Byte1]: 67
2807 22:16:32.254232
2808 22:16:32.254653 Set Vref, RX VrefLevel [Byte0]: 68
2809 22:16:32.257132 [Byte1]: 68
2810 22:16:32.261580
2811 22:16:32.261998 Set Vref, RX VrefLevel [Byte0]: 69
2812 22:16:32.265440 [Byte1]: 69
2813 22:16:32.269592
2814 22:16:32.270011 Final RX Vref Byte 0 = 53 to rank0
2815 22:16:32.273120 Final RX Vref Byte 1 = 51 to rank0
2816 22:16:32.276237 Final RX Vref Byte 0 = 53 to rank1
2817 22:16:32.279690 Final RX Vref Byte 1 = 51 to rank1==
2818 22:16:32.282769 Dram Type= 6, Freq= 0, CH_0, rank 0
2819 22:16:32.289616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2820 22:16:32.290040 ==
2821 22:16:32.290559 DQS Delay:
2822 22:16:32.290911 DQS0 = 0, DQS1 = 0
2823 22:16:32.292908 DQM Delay:
2824 22:16:32.293008 DQM0 = 115, DQM1 = 104
2825 22:16:32.295713 DQ Delay:
2826 22:16:32.299265 DQ0 =114, DQ1 =114, DQ2 =112, DQ3 =114
2827 22:16:32.302690 DQ4 =116, DQ5 =108, DQ6 =120, DQ7 =122
2828 22:16:32.305882 DQ8 =92, DQ9 =90, DQ10 =104, DQ11 =96
2829 22:16:32.308844 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114
2830 22:16:32.308927
2831 22:16:32.308992
2832 22:16:32.315934 [DQSOSCAuto] RK0, (LSB)MR18= 0xfded, (MSB)MR19= 0x303, tDQSOscB0 = 417 ps tDQSOscB1 = 411 ps
2833 22:16:32.318975 CH0 RK0: MR19=303, MR18=FDED
2834 22:16:32.325806 CH0_RK0: MR19=0x303, MR18=0xFDED, DQSOSC=411, MR23=63, INC=38, DEC=25
2835 22:16:32.325894
2836 22:16:32.329536 ----->DramcWriteLeveling(PI) begin...
2837 22:16:32.329631 ==
2838 22:16:32.332410 Dram Type= 6, Freq= 0, CH_0, rank 1
2839 22:16:32.335972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2840 22:16:32.338940 ==
2841 22:16:32.339050 Write leveling (Byte 0): 33 => 33
2842 22:16:32.342976 Write leveling (Byte 1): 29 => 29
2843 22:16:32.346032 DramcWriteLeveling(PI) end<-----
2844 22:16:32.346154
2845 22:16:32.346249 ==
2846 22:16:32.349155 Dram Type= 6, Freq= 0, CH_0, rank 1
2847 22:16:32.355527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2848 22:16:32.355727 ==
2849 22:16:32.355899 [Gating] SW mode calibration
2850 22:16:32.366011 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2851 22:16:32.369286 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2852 22:16:32.372462 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2853 22:16:32.379405 0 15 4 | B1->B0 | 2d2d 3434 | 1 1 | (0 0) (1 1)
2854 22:16:32.383433 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2855 22:16:32.386155 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2856 22:16:32.393300 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2857 22:16:32.396151 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2858 22:16:32.399249 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2859 22:16:32.405975 0 15 28 | B1->B0 | 3434 2929 | 1 1 | (1 1) (1 0)
2860 22:16:32.409249 1 0 0 | B1->B0 | 2e2e 2626 | 0 0 | (0 1) (0 0)
2861 22:16:32.413121 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2862 22:16:32.419372 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2863 22:16:32.422871 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2864 22:16:32.426167 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2865 22:16:32.433170 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2866 22:16:32.436415 1 0 24 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
2867 22:16:32.439866 1 0 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
2868 22:16:32.446225 1 1 0 | B1->B0 | 2c2c 3939 | 0 1 | (0 0) (0 0)
2869 22:16:32.449387 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2870 22:16:32.452962 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2871 22:16:32.459094 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2872 22:16:32.462917 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2873 22:16:32.466579 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2874 22:16:32.469707 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2875 22:16:32.476074 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2876 22:16:32.479310 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2877 22:16:32.482519 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2878 22:16:32.489512 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2879 22:16:32.492815 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2880 22:16:32.496553 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2881 22:16:32.502534 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2882 22:16:32.506145 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2883 22:16:32.509820 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 22:16:32.515812 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 22:16:32.519126 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 22:16:32.522736 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 22:16:32.529222 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 22:16:32.532991 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2889 22:16:32.535755 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2890 22:16:32.542291 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2891 22:16:32.545842 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2892 22:16:32.549047 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2893 22:16:32.552245 Total UI for P1: 0, mck2ui 16
2894 22:16:32.555809 best dqsien dly found for B0: ( 1, 3, 28)
2895 22:16:32.562841 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2896 22:16:32.563449 Total UI for P1: 0, mck2ui 16
2897 22:16:32.569215 best dqsien dly found for B1: ( 1, 4, 0)
2898 22:16:32.572238 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2899 22:16:32.575712 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2900 22:16:32.576342
2901 22:16:32.579102 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2902 22:16:32.582143 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2903 22:16:32.585522 [Gating] SW calibration Done
2904 22:16:32.586137 ==
2905 22:16:32.589220 Dram Type= 6, Freq= 0, CH_0, rank 1
2906 22:16:32.592643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2907 22:16:32.593277 ==
2908 22:16:32.595785 RX Vref Scan: 0
2909 22:16:32.596311
2910 22:16:32.596740 RX Vref 0 -> 0, step: 1
2911 22:16:32.597172
2912 22:16:32.598992 RX Delay -40 -> 252, step: 8
2913 22:16:32.602229 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2914 22:16:32.605981 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2915 22:16:32.612474 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2916 22:16:32.616125 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2917 22:16:32.619091 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2918 22:16:32.622327 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2919 22:16:32.625757 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2920 22:16:32.632473 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2921 22:16:32.635720 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2922 22:16:32.638912 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2923 22:16:32.642960 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2924 22:16:32.646155 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2925 22:16:32.652780 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2926 22:16:32.656070 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2927 22:16:32.659023 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2928 22:16:32.662327 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2929 22:16:32.662894 ==
2930 22:16:32.665773 Dram Type= 6, Freq= 0, CH_0, rank 1
2931 22:16:32.669647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2932 22:16:32.672407 ==
2933 22:16:32.672930 DQS Delay:
2934 22:16:32.673401 DQS0 = 0, DQS1 = 0
2935 22:16:32.676121 DQM Delay:
2936 22:16:32.676685 DQM0 = 115, DQM1 = 106
2937 22:16:32.679431 DQ Delay:
2938 22:16:32.682846 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =115
2939 22:16:32.686262 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2940 22:16:32.689529 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =99
2941 22:16:32.692210 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
2942 22:16:32.692822
2943 22:16:32.693370
2944 22:16:32.693881 ==
2945 22:16:32.696026 Dram Type= 6, Freq= 0, CH_0, rank 1
2946 22:16:32.699246 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2947 22:16:32.699849 ==
2948 22:16:32.700295
2949 22:16:32.700696
2950 22:16:32.702341 TX Vref Scan disable
2951 22:16:32.706224 == TX Byte 0 ==
2952 22:16:32.709045 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2953 22:16:32.712511 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2954 22:16:32.715804 == TX Byte 1 ==
2955 22:16:32.719650 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2956 22:16:32.722592 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2957 22:16:32.723117 ==
2958 22:16:32.725927 Dram Type= 6, Freq= 0, CH_0, rank 1
2959 22:16:32.729316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2960 22:16:32.732226 ==
2961 22:16:32.742715 TX Vref=22, minBit 3, minWin=25, winSum=426
2962 22:16:32.746233 TX Vref=24, minBit 3, minWin=25, winSum=433
2963 22:16:32.749709 TX Vref=26, minBit 2, minWin=26, winSum=432
2964 22:16:32.753399 TX Vref=28, minBit 14, minWin=26, winSum=438
2965 22:16:32.756217 TX Vref=30, minBit 4, minWin=26, winSum=436
2966 22:16:32.762953 TX Vref=32, minBit 13, minWin=26, winSum=440
2967 22:16:32.766081 [TxChooseVref] Worse bit 13, Min win 26, Win sum 440, Final Vref 32
2968 22:16:32.766707
2969 22:16:32.769533 Final TX Range 1 Vref 32
2970 22:16:32.770111
2971 22:16:32.770590 ==
2972 22:16:32.773827 Dram Type= 6, Freq= 0, CH_0, rank 1
2973 22:16:32.775865 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2974 22:16:32.775995 ==
2975 22:16:32.778994
2976 22:16:32.779101
2977 22:16:32.779231 TX Vref Scan disable
2978 22:16:32.782970 == TX Byte 0 ==
2979 22:16:32.786093 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2980 22:16:32.792419 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2981 22:16:32.792521 == TX Byte 1 ==
2982 22:16:32.795899 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2983 22:16:32.802579 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2984 22:16:32.802680
2985 22:16:32.802775 [DATLAT]
2986 22:16:32.802866 Freq=1200, CH0 RK1
2987 22:16:32.802954
2988 22:16:32.805674 DATLAT Default: 0xd
2989 22:16:32.805773 0, 0xFFFF, sum = 0
2990 22:16:32.809709 1, 0xFFFF, sum = 0
2991 22:16:32.809813 2, 0xFFFF, sum = 0
2992 22:16:32.812608 3, 0xFFFF, sum = 0
2993 22:16:32.815856 4, 0xFFFF, sum = 0
2994 22:16:32.815973 5, 0xFFFF, sum = 0
2995 22:16:32.819052 6, 0xFFFF, sum = 0
2996 22:16:32.819128 7, 0xFFFF, sum = 0
2997 22:16:32.822823 8, 0xFFFF, sum = 0
2998 22:16:32.822923 9, 0xFFFF, sum = 0
2999 22:16:32.825959 10, 0xFFFF, sum = 0
3000 22:16:32.826059 11, 0xFFFF, sum = 0
3001 22:16:32.829260 12, 0x0, sum = 1
3002 22:16:32.829358 13, 0x0, sum = 2
3003 22:16:32.832219 14, 0x0, sum = 3
3004 22:16:32.832297 15, 0x0, sum = 4
3005 22:16:32.832359 best_step = 13
3006 22:16:32.836209
3007 22:16:32.836285 ==
3008 22:16:32.839306 Dram Type= 6, Freq= 0, CH_0, rank 1
3009 22:16:32.842529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3010 22:16:32.842625 ==
3011 22:16:32.842716 RX Vref Scan: 0
3012 22:16:32.842806
3013 22:16:32.845874 RX Vref 0 -> 0, step: 1
3014 22:16:32.845968
3015 22:16:32.849266 RX Delay -21 -> 252, step: 4
3016 22:16:32.852358 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3017 22:16:32.859400 iDelay=195, Bit 1, Center 114 (43 ~ 186) 144
3018 22:16:32.862320 iDelay=195, Bit 2, Center 110 (39 ~ 182) 144
3019 22:16:32.865621 iDelay=195, Bit 3, Center 114 (43 ~ 186) 144
3020 22:16:32.868855 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3021 22:16:32.872407 iDelay=195, Bit 5, Center 104 (35 ~ 174) 140
3022 22:16:32.879223 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3023 22:16:32.882540 iDelay=195, Bit 7, Center 120 (51 ~ 190) 140
3024 22:16:32.885856 iDelay=195, Bit 8, Center 94 (27 ~ 162) 136
3025 22:16:32.889192 iDelay=195, Bit 9, Center 92 (23 ~ 162) 140
3026 22:16:32.892183 iDelay=195, Bit 10, Center 106 (39 ~ 174) 136
3027 22:16:32.899060 iDelay=195, Bit 11, Center 96 (31 ~ 162) 132
3028 22:16:32.902462 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3029 22:16:32.905749 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3030 22:16:32.909286 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3031 22:16:32.912126 iDelay=195, Bit 15, Center 114 (47 ~ 182) 136
3032 22:16:32.912201 ==
3033 22:16:32.916205 Dram Type= 6, Freq= 0, CH_0, rank 1
3034 22:16:32.922709 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3035 22:16:32.922812 ==
3036 22:16:32.922903 DQS Delay:
3037 22:16:32.926026 DQS0 = 0, DQS1 = 0
3038 22:16:32.926125 DQM Delay:
3039 22:16:32.929210 DQM0 = 113, DQM1 = 104
3040 22:16:32.929309 DQ Delay:
3041 22:16:32.932252 DQ0 =114, DQ1 =114, DQ2 =110, DQ3 =114
3042 22:16:32.935416 DQ4 =112, DQ5 =104, DQ6 =122, DQ7 =120
3043 22:16:32.939168 DQ8 =94, DQ9 =92, DQ10 =106, DQ11 =96
3044 22:16:32.942133 DQ12 =110, DQ13 =110, DQ14 =116, DQ15 =114
3045 22:16:32.942230
3046 22:16:32.942320
3047 22:16:32.952394 [DQSOSCAuto] RK1, (LSB)MR18= 0x3f4, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 408 ps
3048 22:16:32.952503 CH0 RK1: MR19=403, MR18=3F4
3049 22:16:32.958821 CH0_RK1: MR19=0x403, MR18=0x3F4, DQSOSC=408, MR23=63, INC=39, DEC=26
3050 22:16:32.962481 [RxdqsGatingPostProcess] freq 1200
3051 22:16:32.969449 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3052 22:16:32.972190 best DQS0 dly(2T, 0.5T) = (0, 12)
3053 22:16:32.975806 best DQS1 dly(2T, 0.5T) = (0, 12)
3054 22:16:32.975931 best DQS0 P1 dly(2T, 0.5T) = (1, 0)
3055 22:16:32.978839 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3056 22:16:32.982231 best DQS0 dly(2T, 0.5T) = (0, 11)
3057 22:16:32.985457 best DQS1 dly(2T, 0.5T) = (0, 12)
3058 22:16:32.988866 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3059 22:16:32.992091 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3060 22:16:32.995789 Pre-setting of DQS Precalculation
3061 22:16:33.002153 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3062 22:16:33.002382 ==
3063 22:16:33.005588 Dram Type= 6, Freq= 0, CH_1, rank 0
3064 22:16:33.009609 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3065 22:16:33.009857 ==
3066 22:16:33.015540 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3067 22:16:33.019087 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3068 22:16:33.028701 [CA 0] Center 38 (9~68) winsize 60
3069 22:16:33.032430 [CA 1] Center 38 (8~68) winsize 61
3070 22:16:33.035552 [CA 2] Center 35 (5~65) winsize 61
3071 22:16:33.038670 [CA 3] Center 34 (4~65) winsize 62
3072 22:16:33.042437 [CA 4] Center 34 (4~65) winsize 62
3073 22:16:33.045279 [CA 5] Center 34 (4~64) winsize 61
3074 22:16:33.045683
3075 22:16:33.048564 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3076 22:16:33.048951
3077 22:16:33.052134 [CATrainingPosCal] consider 1 rank data
3078 22:16:33.055315 u2DelayCellTimex100 = 270/100 ps
3079 22:16:33.058817 CA0 delay=38 (9~68),Diff = 4 PI (19 cell)
3080 22:16:33.062427 CA1 delay=38 (8~68),Diff = 4 PI (19 cell)
3081 22:16:33.068690 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3082 22:16:33.072336 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3083 22:16:33.075600 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3084 22:16:33.078908 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3085 22:16:33.079302
3086 22:16:33.082322 CA PerBit enable=1, Macro0, CA PI delay=34
3087 22:16:33.082714
3088 22:16:33.085462 [CBTSetCACLKResult] CA Dly = 34
3089 22:16:33.085875 CS Dly: 6 (0~37)
3090 22:16:33.086314 ==
3091 22:16:33.088576 Dram Type= 6, Freq= 0, CH_1, rank 1
3092 22:16:33.095190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3093 22:16:33.095724 ==
3094 22:16:33.099620 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3095 22:16:33.105465 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3096 22:16:33.114424 [CA 0] Center 38 (8~68) winsize 61
3097 22:16:33.117585 [CA 1] Center 38 (9~68) winsize 60
3098 22:16:33.120936 [CA 2] Center 34 (4~65) winsize 62
3099 22:16:33.123975 [CA 3] Center 34 (4~65) winsize 62
3100 22:16:33.127009 [CA 4] Center 34 (4~65) winsize 62
3101 22:16:33.130997 [CA 5] Center 33 (3~64) winsize 62
3102 22:16:33.131103
3103 22:16:33.134089 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3104 22:16:33.134195
3105 22:16:33.137520 [CATrainingPosCal] consider 2 rank data
3106 22:16:33.140803 u2DelayCellTimex100 = 270/100 ps
3107 22:16:33.143687 CA0 delay=38 (9~68),Diff = 4 PI (19 cell)
3108 22:16:33.146947 CA1 delay=38 (9~68),Diff = 4 PI (19 cell)
3109 22:16:33.154109 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3110 22:16:33.157624 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3111 22:16:33.160674 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3112 22:16:33.163769 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3113 22:16:33.163883
3114 22:16:33.167298 CA PerBit enable=1, Macro0, CA PI delay=34
3115 22:16:33.167382
3116 22:16:33.170481 [CBTSetCACLKResult] CA Dly = 34
3117 22:16:33.170563 CS Dly: 7 (0~40)
3118 22:16:33.170627
3119 22:16:33.174045 ----->DramcWriteLeveling(PI) begin...
3120 22:16:33.177668 ==
3121 22:16:33.177749 Dram Type= 6, Freq= 0, CH_1, rank 0
3122 22:16:33.183715 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3123 22:16:33.183797 ==
3124 22:16:33.187018 Write leveling (Byte 0): 27 => 27
3125 22:16:33.190728 Write leveling (Byte 1): 29 => 29
3126 22:16:33.194276 DramcWriteLeveling(PI) end<-----
3127 22:16:33.194356
3128 22:16:33.194423 ==
3129 22:16:33.197800 Dram Type= 6, Freq= 0, CH_1, rank 0
3130 22:16:33.200730 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3131 22:16:33.200812 ==
3132 22:16:33.203916 [Gating] SW mode calibration
3133 22:16:33.210897 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3134 22:16:33.214216 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3135 22:16:33.220779 0 15 0 | B1->B0 | 2b2b 2525 | 0 0 | (0 0) (0 0)
3136 22:16:33.224495 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 0)
3137 22:16:33.227848 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3138 22:16:33.234787 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3139 22:16:33.237702 0 15 16 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3140 22:16:33.240964 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3141 22:16:33.247608 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3142 22:16:33.250746 0 15 28 | B1->B0 | 3434 3434 | 0 0 | (0 0) (0 1)
3143 22:16:33.254108 1 0 0 | B1->B0 | 2424 2b2b | 0 1 | (0 0) (1 0)
3144 22:16:33.261306 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3145 22:16:33.264340 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3146 22:16:33.267686 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3147 22:16:33.274249 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3148 22:16:33.278163 1 0 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3149 22:16:33.281119 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3150 22:16:33.284152 1 0 28 | B1->B0 | 2828 2424 | 1 0 | (0 0) (0 0)
3151 22:16:33.291274 1 1 0 | B1->B0 | 4444 3a3a | 0 0 | (0 0) (0 0)
3152 22:16:33.294379 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3153 22:16:33.297645 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3154 22:16:33.304534 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3155 22:16:33.307369 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3156 22:16:33.311066 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3157 22:16:33.317567 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3158 22:16:33.321045 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3159 22:16:33.324147 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3160 22:16:33.330799 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3161 22:16:33.334362 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3162 22:16:33.337829 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3163 22:16:33.343859 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3164 22:16:33.347166 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3165 22:16:33.351178 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3166 22:16:33.357302 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 22:16:33.360995 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 22:16:33.364138 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 22:16:33.370657 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 22:16:33.374473 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 22:16:33.377725 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3172 22:16:33.380976 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3173 22:16:33.387368 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3174 22:16:33.390914 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3175 22:16:33.394208 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3176 22:16:33.397759 Total UI for P1: 0, mck2ui 16
3177 22:16:33.400784 best dqsien dly found for B1: ( 1, 3, 28)
3178 22:16:33.407255 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3179 22:16:33.410683 Total UI for P1: 0, mck2ui 16
3180 22:16:33.414384 best dqsien dly found for B0: ( 1, 3, 30)
3181 22:16:33.417363 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
3182 22:16:33.420327 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3183 22:16:33.420410
3184 22:16:33.424154 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
3185 22:16:33.427022 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3186 22:16:33.430779 [Gating] SW calibration Done
3187 22:16:33.430861 ==
3188 22:16:33.433886 Dram Type= 6, Freq= 0, CH_1, rank 0
3189 22:16:33.437623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3190 22:16:33.437705 ==
3191 22:16:33.440524 RX Vref Scan: 0
3192 22:16:33.440606
3193 22:16:33.440671 RX Vref 0 -> 0, step: 1
3194 22:16:33.443936
3195 22:16:33.444025 RX Delay -40 -> 252, step: 8
3196 22:16:33.450744 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3197 22:16:33.454075 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3198 22:16:33.457354 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3199 22:16:33.460584 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3200 22:16:33.464262 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3201 22:16:33.467602 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3202 22:16:33.473948 iDelay=200, Bit 6, Center 123 (56 ~ 191) 136
3203 22:16:33.477392 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3204 22:16:33.480580 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3205 22:16:33.483967 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3206 22:16:33.487199 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
3207 22:16:33.494148 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3208 22:16:33.497156 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3209 22:16:33.500793 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
3210 22:16:33.504234 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3211 22:16:33.507795 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3212 22:16:33.510837 ==
3213 22:16:33.510920 Dram Type= 6, Freq= 0, CH_1, rank 0
3214 22:16:33.517250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3215 22:16:33.517333 ==
3216 22:16:33.517398 DQS Delay:
3217 22:16:33.520541 DQS0 = 0, DQS1 = 0
3218 22:16:33.520622 DQM Delay:
3219 22:16:33.524756 DQM0 = 116, DQM1 = 108
3220 22:16:33.524838 DQ Delay:
3221 22:16:33.527468 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =119
3222 22:16:33.530713 DQ4 =111, DQ5 =127, DQ6 =123, DQ7 =115
3223 22:16:33.534038 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
3224 22:16:33.537288 DQ12 =123, DQ13 =115, DQ14 =111, DQ15 =111
3225 22:16:33.537371
3226 22:16:33.537435
3227 22:16:33.537495 ==
3228 22:16:33.540543 Dram Type= 6, Freq= 0, CH_1, rank 0
3229 22:16:33.547185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3230 22:16:33.547270 ==
3231 22:16:33.547335
3232 22:16:33.547395
3233 22:16:33.547453 TX Vref Scan disable
3234 22:16:33.550894 == TX Byte 0 ==
3235 22:16:33.553858 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3236 22:16:33.560214 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3237 22:16:33.560330 == TX Byte 1 ==
3238 22:16:33.563797 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3239 22:16:33.570699 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3240 22:16:33.570777 ==
3241 22:16:33.573964 Dram Type= 6, Freq= 0, CH_1, rank 0
3242 22:16:33.576951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3243 22:16:33.577035 ==
3244 22:16:33.588529 TX Vref=22, minBit 2, minWin=25, winSum=413
3245 22:16:33.591614 TX Vref=24, minBit 10, minWin=25, winSum=418
3246 22:16:33.595181 TX Vref=26, minBit 1, minWin=26, winSum=424
3247 22:16:33.598721 TX Vref=28, minBit 2, minWin=25, winSum=425
3248 22:16:33.601927 TX Vref=30, minBit 1, minWin=26, winSum=429
3249 22:16:33.608465 TX Vref=32, minBit 13, minWin=25, winSum=426
3250 22:16:33.611800 [TxChooseVref] Worse bit 1, Min win 26, Win sum 429, Final Vref 30
3251 22:16:33.611883
3252 22:16:33.615068 Final TX Range 1 Vref 30
3253 22:16:33.615151
3254 22:16:33.615215 ==
3255 22:16:33.618502 Dram Type= 6, Freq= 0, CH_1, rank 0
3256 22:16:33.622052 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3257 22:16:33.622136 ==
3258 22:16:33.625034
3259 22:16:33.625116
3260 22:16:33.625181 TX Vref Scan disable
3261 22:16:33.628691 == TX Byte 0 ==
3262 22:16:33.631825 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3263 22:16:33.635324 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3264 22:16:33.638642 == TX Byte 1 ==
3265 22:16:33.641987 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3266 22:16:33.644961 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3267 22:16:33.648881
3268 22:16:33.649320 [DATLAT]
3269 22:16:33.649659 Freq=1200, CH1 RK0
3270 22:16:33.649984
3271 22:16:33.652051 DATLAT Default: 0xd
3272 22:16:33.652479 0, 0xFFFF, sum = 0
3273 22:16:33.655654 1, 0xFFFF, sum = 0
3274 22:16:33.656129 2, 0xFFFF, sum = 0
3275 22:16:33.659153 3, 0xFFFF, sum = 0
3276 22:16:33.659637 4, 0xFFFF, sum = 0
3277 22:16:33.662049 5, 0xFFFF, sum = 0
3278 22:16:33.665338 6, 0xFFFF, sum = 0
3279 22:16:33.665778 7, 0xFFFF, sum = 0
3280 22:16:33.668838 8, 0xFFFF, sum = 0
3281 22:16:33.669273 9, 0xFFFF, sum = 0
3282 22:16:33.671920 10, 0xFFFF, sum = 0
3283 22:16:33.672394 11, 0xFFFF, sum = 0
3284 22:16:33.675381 12, 0x0, sum = 1
3285 22:16:33.675889 13, 0x0, sum = 2
3286 22:16:33.678472 14, 0x0, sum = 3
3287 22:16:33.678958 15, 0x0, sum = 4
3288 22:16:33.679309 best_step = 13
3289 22:16:33.679678
3290 22:16:33.681950 ==
3291 22:16:33.686055 Dram Type= 6, Freq= 0, CH_1, rank 0
3292 22:16:33.689117 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3293 22:16:33.689605 ==
3294 22:16:33.690070 RX Vref Scan: 1
3295 22:16:33.690487
3296 22:16:33.692283 Set Vref Range= 32 -> 127
3297 22:16:33.692756
3298 22:16:33.696138 RX Vref 32 -> 127, step: 1
3299 22:16:33.696583
3300 22:16:33.698963 RX Delay -21 -> 252, step: 4
3301 22:16:33.699499
3302 22:16:33.702085 Set Vref, RX VrefLevel [Byte0]: 32
3303 22:16:33.705162 [Byte1]: 32
3304 22:16:33.705830
3305 22:16:33.709272 Set Vref, RX VrefLevel [Byte0]: 33
3306 22:16:33.712141 [Byte1]: 33
3307 22:16:33.712675
3308 22:16:33.715876 Set Vref, RX VrefLevel [Byte0]: 34
3309 22:16:33.718983 [Byte1]: 34
3310 22:16:33.723853
3311 22:16:33.724397 Set Vref, RX VrefLevel [Byte0]: 35
3312 22:16:33.726418 [Byte1]: 35
3313 22:16:33.731093
3314 22:16:33.731508 Set Vref, RX VrefLevel [Byte0]: 36
3315 22:16:33.734029 [Byte1]: 36
3316 22:16:33.738481
3317 22:16:33.738945 Set Vref, RX VrefLevel [Byte0]: 37
3318 22:16:33.742066 [Byte1]: 37
3319 22:16:33.746540
3320 22:16:33.747157 Set Vref, RX VrefLevel [Byte0]: 38
3321 22:16:33.753624 [Byte1]: 38
3322 22:16:33.754193
3323 22:16:33.756517 Set Vref, RX VrefLevel [Byte0]: 39
3324 22:16:33.759591 [Byte1]: 39
3325 22:16:33.760213
3326 22:16:33.763028 Set Vref, RX VrefLevel [Byte0]: 40
3327 22:16:33.766192 [Byte1]: 40
3328 22:16:33.770465
3329 22:16:33.771051 Set Vref, RX VrefLevel [Byte0]: 41
3330 22:16:33.774188 [Byte1]: 41
3331 22:16:33.778702
3332 22:16:33.779271 Set Vref, RX VrefLevel [Byte0]: 42
3333 22:16:33.781510 [Byte1]: 42
3334 22:16:33.786137
3335 22:16:33.786758 Set Vref, RX VrefLevel [Byte0]: 43
3336 22:16:33.789827 [Byte1]: 43
3337 22:16:33.794537
3338 22:16:33.795127 Set Vref, RX VrefLevel [Byte0]: 44
3339 22:16:33.798235 [Byte1]: 44
3340 22:16:33.801920
3341 22:16:33.802530 Set Vref, RX VrefLevel [Byte0]: 45
3342 22:16:33.805459 [Byte1]: 45
3343 22:16:33.810122
3344 22:16:33.810717 Set Vref, RX VrefLevel [Byte0]: 46
3345 22:16:33.813649 [Byte1]: 46
3346 22:16:33.818213
3347 22:16:33.818796 Set Vref, RX VrefLevel [Byte0]: 47
3348 22:16:33.821817 [Byte1]: 47
3349 22:16:33.826053
3350 22:16:33.826630 Set Vref, RX VrefLevel [Byte0]: 48
3351 22:16:33.829084 [Byte1]: 48
3352 22:16:33.833861
3353 22:16:33.834440 Set Vref, RX VrefLevel [Byte0]: 49
3354 22:16:33.837169 [Byte1]: 49
3355 22:16:33.841781
3356 22:16:33.842353 Set Vref, RX VrefLevel [Byte0]: 50
3357 22:16:33.845255 [Byte1]: 50
3358 22:16:33.849865
3359 22:16:33.850431 Set Vref, RX VrefLevel [Byte0]: 51
3360 22:16:33.852903 [Byte1]: 51
3361 22:16:33.857436
3362 22:16:33.858018 Set Vref, RX VrefLevel [Byte0]: 52
3363 22:16:33.861001 [Byte1]: 52
3364 22:16:33.865797
3365 22:16:33.866208 Set Vref, RX VrefLevel [Byte0]: 53
3366 22:16:33.868901 [Byte1]: 53
3367 22:16:33.873681
3368 22:16:33.874130 Set Vref, RX VrefLevel [Byte0]: 54
3369 22:16:33.876855 [Byte1]: 54
3370 22:16:33.881566
3371 22:16:33.882043 Set Vref, RX VrefLevel [Byte0]: 55
3372 22:16:33.885100 [Byte1]: 55
3373 22:16:33.889228
3374 22:16:33.889830 Set Vref, RX VrefLevel [Byte0]: 56
3375 22:16:33.892710 [Byte1]: 56
3376 22:16:33.897342
3377 22:16:33.897964 Set Vref, RX VrefLevel [Byte0]: 57
3378 22:16:33.900458 [Byte1]: 57
3379 22:16:33.905513
3380 22:16:33.906075 Set Vref, RX VrefLevel [Byte0]: 58
3381 22:16:33.908291 [Byte1]: 58
3382 22:16:33.912797
3383 22:16:33.913377 Set Vref, RX VrefLevel [Byte0]: 59
3384 22:16:33.919844 [Byte1]: 59
3385 22:16:33.920308
3386 22:16:33.922791 Set Vref, RX VrefLevel [Byte0]: 60
3387 22:16:33.926286 [Byte1]: 60
3388 22:16:33.926864
3389 22:16:33.929486 Set Vref, RX VrefLevel [Byte0]: 61
3390 22:16:33.933297 [Byte1]: 61
3391 22:16:33.936842
3392 22:16:33.937297 Set Vref, RX VrefLevel [Byte0]: 62
3393 22:16:33.940474 [Byte1]: 62
3394 22:16:33.944825
3395 22:16:33.945273 Set Vref, RX VrefLevel [Byte0]: 63
3396 22:16:33.947913 [Byte1]: 63
3397 22:16:33.953063
3398 22:16:33.953571 Set Vref, RX VrefLevel [Byte0]: 64
3399 22:16:33.956049 [Byte1]: 64
3400 22:16:33.960799
3401 22:16:33.961303 Set Vref, RX VrefLevel [Byte0]: 65
3402 22:16:33.963932 [Byte1]: 65
3403 22:16:33.968644
3404 22:16:33.969054 Set Vref, RX VrefLevel [Byte0]: 66
3405 22:16:33.971763 [Byte1]: 66
3406 22:16:33.976958
3407 22:16:33.977374 Set Vref, RX VrefLevel [Byte0]: 67
3408 22:16:33.979520 [Byte1]: 67
3409 22:16:33.984455
3410 22:16:33.984873 Set Vref, RX VrefLevel [Byte0]: 68
3411 22:16:33.987929 [Byte1]: 68
3412 22:16:33.992055
3413 22:16:33.992516 Set Vref, RX VrefLevel [Byte0]: 69
3414 22:16:33.995777 [Byte1]: 69
3415 22:16:34.000057
3416 22:16:34.000508 Final RX Vref Byte 0 = 58 to rank0
3417 22:16:34.003317 Final RX Vref Byte 1 = 52 to rank0
3418 22:16:34.007103 Final RX Vref Byte 0 = 58 to rank1
3419 22:16:34.009902 Final RX Vref Byte 1 = 52 to rank1==
3420 22:16:34.014691 Dram Type= 6, Freq= 0, CH_1, rank 0
3421 22:16:34.020125 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3422 22:16:34.020543 ==
3423 22:16:34.020885 DQS Delay:
3424 22:16:34.021197 DQS0 = 0, DQS1 = 0
3425 22:16:34.023494 DQM Delay:
3426 22:16:34.023909 DQM0 = 116, DQM1 = 109
3427 22:16:34.026802 DQ Delay:
3428 22:16:34.030157 DQ0 =118, DQ1 =110, DQ2 =106, DQ3 =114
3429 22:16:34.033699 DQ4 =116, DQ5 =126, DQ6 =126, DQ7 =114
3430 22:16:34.036783 DQ8 =98, DQ9 =98, DQ10 =112, DQ11 =106
3431 22:16:34.039929 DQ12 =116, DQ13 =116, DQ14 =116, DQ15 =114
3432 22:16:34.040393
3433 22:16:34.040723
3434 22:16:34.046728 [DQSOSCAuto] RK0, (LSB)MR18= 0xfee2, (MSB)MR19= 0x303, tDQSOscB0 = 422 ps tDQSOscB1 = 410 ps
3435 22:16:34.050421 CH1 RK0: MR19=303, MR18=FEE2
3436 22:16:34.057334 CH1_RK0: MR19=0x303, MR18=0xFEE2, DQSOSC=410, MR23=63, INC=39, DEC=26
3437 22:16:34.057811
3438 22:16:34.060503 ----->DramcWriteLeveling(PI) begin...
3439 22:16:34.061098 ==
3440 22:16:34.063819 Dram Type= 6, Freq= 0, CH_1, rank 1
3441 22:16:34.067054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3442 22:16:34.067506 ==
3443 22:16:34.070641 Write leveling (Byte 0): 25 => 25
3444 22:16:34.073638 Write leveling (Byte 1): 29 => 29
3445 22:16:34.076946 DramcWriteLeveling(PI) end<-----
3446 22:16:34.077372
3447 22:16:34.077706 ==
3448 22:16:34.080700 Dram Type= 6, Freq= 0, CH_1, rank 1
3449 22:16:34.087505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3450 22:16:34.088262 ==
3451 22:16:34.088629 [Gating] SW mode calibration
3452 22:16:34.097304 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3453 22:16:34.100303 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3454 22:16:34.104399 0 15 0 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
3455 22:16:34.111145 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3456 22:16:34.114276 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3457 22:16:34.116901 0 15 12 | B1->B0 | 3534 3434 | 1 1 | (0 0) (1 1)
3458 22:16:34.123654 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3459 22:16:34.127344 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3460 22:16:34.130266 0 15 24 | B1->B0 | 3434 2626 | 0 0 | (0 0) (1 0)
3461 22:16:34.137208 0 15 28 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
3462 22:16:34.140383 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3463 22:16:34.143412 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3464 22:16:34.150616 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3465 22:16:34.153835 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3466 22:16:34.157171 1 0 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3467 22:16:34.160714 1 0 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3468 22:16:34.167391 1 0 24 | B1->B0 | 2626 3e3e | 1 1 | (0 0) (0 0)
3469 22:16:34.170655 1 0 28 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
3470 22:16:34.174252 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3471 22:16:34.180152 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3472 22:16:34.184119 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3473 22:16:34.186895 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3474 22:16:34.193601 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3475 22:16:34.197161 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3476 22:16:34.199924 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3477 22:16:34.206838 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3478 22:16:34.209979 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3479 22:16:34.213436 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3480 22:16:34.220126 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3481 22:16:34.223514 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3482 22:16:34.226886 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3483 22:16:34.233398 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3484 22:16:34.236690 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3485 22:16:34.239928 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3486 22:16:34.246569 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3487 22:16:34.250184 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3488 22:16:34.253260 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3489 22:16:34.260287 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3490 22:16:34.263554 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3491 22:16:34.266466 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3492 22:16:34.273100 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3493 22:16:34.276665 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3494 22:16:34.279798 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3495 22:16:34.283913 Total UI for P1: 0, mck2ui 16
3496 22:16:34.286786 best dqsien dly found for B0: ( 1, 3, 24)
3497 22:16:34.290351 Total UI for P1: 0, mck2ui 16
3498 22:16:34.293256 best dqsien dly found for B1: ( 1, 3, 28)
3499 22:16:34.296520 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3500 22:16:34.300624 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3501 22:16:34.301192
3502 22:16:34.306298 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3503 22:16:34.309797 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3504 22:16:34.310312 [Gating] SW calibration Done
3505 22:16:34.312961 ==
3506 22:16:34.316058 Dram Type= 6, Freq= 0, CH_1, rank 1
3507 22:16:34.319736 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3508 22:16:34.320276 ==
3509 22:16:34.320658 RX Vref Scan: 0
3510 22:16:34.321012
3511 22:16:34.322691 RX Vref 0 -> 0, step: 1
3512 22:16:34.323159
3513 22:16:34.326269 RX Delay -40 -> 252, step: 8
3514 22:16:34.330063 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3515 22:16:34.332878 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3516 22:16:34.336080 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3517 22:16:34.342486 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
3518 22:16:34.346660 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3519 22:16:34.349509 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3520 22:16:34.352737 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3521 22:16:34.355994 iDelay=200, Bit 7, Center 107 (40 ~ 175) 136
3522 22:16:34.362405 iDelay=200, Bit 8, Center 99 (24 ~ 175) 152
3523 22:16:34.365982 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3524 22:16:34.369723 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3525 22:16:34.372675 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
3526 22:16:34.376022 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
3527 22:16:34.383256 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3528 22:16:34.386231 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3529 22:16:34.389273 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3530 22:16:34.389722 ==
3531 22:16:34.392836 Dram Type= 6, Freq= 0, CH_1, rank 1
3532 22:16:34.396062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3533 22:16:34.399039 ==
3534 22:16:34.399455 DQS Delay:
3535 22:16:34.399789 DQS0 = 0, DQS1 = 0
3536 22:16:34.402486 DQM Delay:
3537 22:16:34.402903 DQM0 = 113, DQM1 = 109
3538 22:16:34.405879 DQ Delay:
3539 22:16:34.409289 DQ0 =115, DQ1 =111, DQ2 =103, DQ3 =115
3540 22:16:34.412436 DQ4 =111, DQ5 =127, DQ6 =119, DQ7 =107
3541 22:16:34.416176 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =99
3542 22:16:34.419435 DQ12 =115, DQ13 =119, DQ14 =119, DQ15 =119
3543 22:16:34.419860
3544 22:16:34.420272
3545 22:16:34.420595 ==
3546 22:16:34.422391 Dram Type= 6, Freq= 0, CH_1, rank 1
3547 22:16:34.425839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3548 22:16:34.426265 ==
3549 22:16:34.426607
3550 22:16:34.426924
3551 22:16:34.429085 TX Vref Scan disable
3552 22:16:34.432305 == TX Byte 0 ==
3553 22:16:34.435801 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3554 22:16:34.439063 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3555 22:16:34.442482 == TX Byte 1 ==
3556 22:16:34.445569 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3557 22:16:34.449135 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3558 22:16:34.449559 ==
3559 22:16:34.452422 Dram Type= 6, Freq= 0, CH_1, rank 1
3560 22:16:34.455900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3561 22:16:34.458650 ==
3562 22:16:34.469057 TX Vref=22, minBit 0, minWin=25, winSum=419
3563 22:16:34.472990 TX Vref=24, minBit 3, minWin=25, winSum=423
3564 22:16:34.475719 TX Vref=26, minBit 0, minWin=25, winSum=430
3565 22:16:34.478821 TX Vref=28, minBit 3, minWin=25, winSum=430
3566 22:16:34.482175 TX Vref=30, minBit 0, minWin=27, winSum=436
3567 22:16:34.489212 TX Vref=32, minBit 3, minWin=26, winSum=435
3568 22:16:34.492138 [TxChooseVref] Worse bit 0, Min win 27, Win sum 436, Final Vref 30
3569 22:16:34.492575
3570 22:16:34.495674 Final TX Range 1 Vref 30
3571 22:16:34.496251
3572 22:16:34.496753 ==
3573 22:16:34.498789 Dram Type= 6, Freq= 0, CH_1, rank 1
3574 22:16:34.502287 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3575 22:16:34.502725 ==
3576 22:16:34.505736
3577 22:16:34.506287
3578 22:16:34.506652 TX Vref Scan disable
3579 22:16:34.509328 == TX Byte 0 ==
3580 22:16:34.512185 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3581 22:16:34.516053 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3582 22:16:34.518889 == TX Byte 1 ==
3583 22:16:34.521972 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3584 22:16:34.528907 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3585 22:16:34.529610
3586 22:16:34.530233 [DATLAT]
3587 22:16:34.530790 Freq=1200, CH1 RK1
3588 22:16:34.531264
3589 22:16:34.532117 DATLAT Default: 0xd
3590 22:16:34.532638 0, 0xFFFF, sum = 0
3591 22:16:34.536228 1, 0xFFFF, sum = 0
3592 22:16:34.536668 2, 0xFFFF, sum = 0
3593 22:16:34.538940 3, 0xFFFF, sum = 0
3594 22:16:34.542356 4, 0xFFFF, sum = 0
3595 22:16:34.542780 5, 0xFFFF, sum = 0
3596 22:16:34.545449 6, 0xFFFF, sum = 0
3597 22:16:34.545874 7, 0xFFFF, sum = 0
3598 22:16:34.549079 8, 0xFFFF, sum = 0
3599 22:16:34.549505 9, 0xFFFF, sum = 0
3600 22:16:34.551865 10, 0xFFFF, sum = 0
3601 22:16:34.552347 11, 0xFFFF, sum = 0
3602 22:16:34.555922 12, 0x0, sum = 1
3603 22:16:34.556403 13, 0x0, sum = 2
3604 22:16:34.559211 14, 0x0, sum = 3
3605 22:16:34.559634 15, 0x0, sum = 4
3606 22:16:34.560013 best_step = 13
3607 22:16:34.561947
3608 22:16:34.562358 ==
3609 22:16:34.565027 Dram Type= 6, Freq= 0, CH_1, rank 1
3610 22:16:34.568722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3611 22:16:34.569143 ==
3612 22:16:34.569478 RX Vref Scan: 0
3613 22:16:34.569789
3614 22:16:34.572643 RX Vref 0 -> 0, step: 1
3615 22:16:34.573059
3616 22:16:34.575756 RX Delay -21 -> 252, step: 4
3617 22:16:34.578917 iDelay=191, Bit 0, Center 112 (43 ~ 182) 140
3618 22:16:34.585114 iDelay=191, Bit 1, Center 108 (43 ~ 174) 132
3619 22:16:34.589166 iDelay=191, Bit 2, Center 106 (43 ~ 170) 128
3620 22:16:34.592042 iDelay=191, Bit 3, Center 112 (47 ~ 178) 132
3621 22:16:34.595392 iDelay=191, Bit 4, Center 114 (47 ~ 182) 136
3622 22:16:34.598236 iDelay=191, Bit 5, Center 124 (59 ~ 190) 132
3623 22:16:34.604980 iDelay=191, Bit 6, Center 122 (55 ~ 190) 136
3624 22:16:34.608878 iDelay=191, Bit 7, Center 110 (47 ~ 174) 128
3625 22:16:34.611592 iDelay=191, Bit 8, Center 98 (31 ~ 166) 136
3626 22:16:34.615192 iDelay=191, Bit 9, Center 98 (35 ~ 162) 128
3627 22:16:34.618346 iDelay=191, Bit 10, Center 110 (43 ~ 178) 136
3628 22:16:34.625179 iDelay=191, Bit 11, Center 102 (35 ~ 170) 136
3629 22:16:34.628247 iDelay=191, Bit 12, Center 114 (51 ~ 178) 128
3630 22:16:34.632185 iDelay=191, Bit 13, Center 118 (55 ~ 182) 128
3631 22:16:34.634866 iDelay=191, Bit 14, Center 118 (55 ~ 182) 128
3632 22:16:34.638614 iDelay=191, Bit 15, Center 118 (55 ~ 182) 128
3633 22:16:34.642130 ==
3634 22:16:34.642556 Dram Type= 6, Freq= 0, CH_1, rank 1
3635 22:16:34.648622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3636 22:16:34.649111 ==
3637 22:16:34.649516 DQS Delay:
3638 22:16:34.651585 DQS0 = 0, DQS1 = 0
3639 22:16:34.652109 DQM Delay:
3640 22:16:34.655050 DQM0 = 113, DQM1 = 109
3641 22:16:34.655534 DQ Delay:
3642 22:16:34.658364 DQ0 =112, DQ1 =108, DQ2 =106, DQ3 =112
3643 22:16:34.661885 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =110
3644 22:16:34.665432 DQ8 =98, DQ9 =98, DQ10 =110, DQ11 =102
3645 22:16:34.668462 DQ12 =114, DQ13 =118, DQ14 =118, DQ15 =118
3646 22:16:34.668951
3647 22:16:34.669356
3648 22:16:34.678074 [DQSOSCAuto] RK1, (LSB)MR18= 0xf5fd, (MSB)MR19= 0x303, tDQSOscB0 = 411 ps tDQSOscB1 = 414 ps
3649 22:16:34.681334 CH1 RK1: MR19=303, MR18=F5FD
3650 22:16:34.685298 CH1_RK1: MR19=0x303, MR18=0xF5FD, DQSOSC=411, MR23=63, INC=38, DEC=25
3651 22:16:34.688043 [RxdqsGatingPostProcess] freq 1200
3652 22:16:34.694733 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3653 22:16:34.698359 best DQS0 dly(2T, 0.5T) = (0, 11)
3654 22:16:34.701108 best DQS1 dly(2T, 0.5T) = (0, 11)
3655 22:16:34.704778 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3656 22:16:34.708359 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3657 22:16:34.711673 best DQS0 dly(2T, 0.5T) = (0, 11)
3658 22:16:34.714444 best DQS1 dly(2T, 0.5T) = (0, 11)
3659 22:16:34.717672 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3660 22:16:34.721476 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3661 22:16:34.721587 Pre-setting of DQS Precalculation
3662 22:16:34.727814 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3663 22:16:34.734135 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3664 22:16:34.741507 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3665 22:16:34.741654
3666 22:16:34.741790
3667 22:16:34.744303 [Calibration Summary] 2400 Mbps
3668 22:16:34.747482 CH 0, Rank 0
3669 22:16:34.747640 SW Impedance : PASS
3670 22:16:34.751308 DUTY Scan : NO K
3671 22:16:34.754856 ZQ Calibration : PASS
3672 22:16:34.754941 Jitter Meter : NO K
3673 22:16:34.757710 CBT Training : PASS
3674 22:16:34.761395 Write leveling : PASS
3675 22:16:34.761487 RX DQS gating : PASS
3676 22:16:34.764225 RX DQ/DQS(RDDQC) : PASS
3677 22:16:34.767378 TX DQ/DQS : PASS
3678 22:16:34.767467 RX DATLAT : PASS
3679 22:16:34.770987 RX DQ/DQS(Engine): PASS
3680 22:16:34.771082 TX OE : NO K
3681 22:16:34.773988 All Pass.
3682 22:16:34.774109
3683 22:16:34.774206 CH 0, Rank 1
3684 22:16:34.777203 SW Impedance : PASS
3685 22:16:34.777324 DUTY Scan : NO K
3686 22:16:34.781072 ZQ Calibration : PASS
3687 22:16:34.783885 Jitter Meter : NO K
3688 22:16:34.784048 CBT Training : PASS
3689 22:16:34.787117 Write leveling : PASS
3690 22:16:34.790609 RX DQS gating : PASS
3691 22:16:34.790801 RX DQ/DQS(RDDQC) : PASS
3692 22:16:34.793959 TX DQ/DQS : PASS
3693 22:16:34.797421 RX DATLAT : PASS
3694 22:16:34.797631 RX DQ/DQS(Engine): PASS
3695 22:16:34.800780 TX OE : NO K
3696 22:16:34.801048 All Pass.
3697 22:16:34.801257
3698 22:16:34.803781 CH 1, Rank 0
3699 22:16:34.804135 SW Impedance : PASS
3700 22:16:34.806978 DUTY Scan : NO K
3701 22:16:34.810536 ZQ Calibration : PASS
3702 22:16:34.811028 Jitter Meter : NO K
3703 22:16:34.813719 CBT Training : PASS
3704 22:16:34.817067 Write leveling : PASS
3705 22:16:34.817563 RX DQS gating : PASS
3706 22:16:34.820820 RX DQ/DQS(RDDQC) : PASS
3707 22:16:34.824197 TX DQ/DQS : PASS
3708 22:16:34.824756 RX DATLAT : PASS
3709 22:16:34.827736 RX DQ/DQS(Engine): PASS
3710 22:16:34.828316 TX OE : NO K
3711 22:16:34.830650 All Pass.
3712 22:16:34.831171
3713 22:16:34.831583 CH 1, Rank 1
3714 22:16:34.833598 SW Impedance : PASS
3715 22:16:34.834119 DUTY Scan : NO K
3716 22:16:34.837306 ZQ Calibration : PASS
3717 22:16:34.840301 Jitter Meter : NO K
3718 22:16:34.840793 CBT Training : PASS
3719 22:16:34.843655 Write leveling : PASS
3720 22:16:34.847531 RX DQS gating : PASS
3721 22:16:34.848014 RX DQ/DQS(RDDQC) : PASS
3722 22:16:34.850930 TX DQ/DQS : PASS
3723 22:16:34.853962 RX DATLAT : PASS
3724 22:16:34.854474 RX DQ/DQS(Engine): PASS
3725 22:16:34.857342 TX OE : NO K
3726 22:16:34.857782 All Pass.
3727 22:16:34.858123
3728 22:16:34.860944 DramC Write-DBI off
3729 22:16:34.864113 PER_BANK_REFRESH: Hybrid Mode
3730 22:16:34.864673 TX_TRACKING: ON
3731 22:16:34.874373 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3732 22:16:34.877201 [FAST_K] Save calibration result to emmc
3733 22:16:34.880549 dramc_set_vcore_voltage set vcore to 650000
3734 22:16:34.883647 Read voltage for 600, 5
3735 22:16:34.884161 Vio18 = 0
3736 22:16:34.884556 Vcore = 650000
3737 22:16:34.887376 Vdram = 0
3738 22:16:34.887779 Vddq = 0
3739 22:16:34.888171 Vmddr = 0
3740 22:16:34.893312 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3741 22:16:34.896767 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3742 22:16:34.900219 MEM_TYPE=3, freq_sel=19
3743 22:16:34.903898 sv_algorithm_assistance_LP4_1600
3744 22:16:34.906858 ============ PULL DRAM RESETB DOWN ============
3745 22:16:34.910515 ========== PULL DRAM RESETB DOWN end =========
3746 22:16:34.916685 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3747 22:16:34.919791 ===================================
3748 22:16:34.923156 LPDDR4 DRAM CONFIGURATION
3749 22:16:34.926678 ===================================
3750 22:16:34.927105 EX_ROW_EN[0] = 0x0
3751 22:16:34.930206 EX_ROW_EN[1] = 0x0
3752 22:16:34.930679 LP4Y_EN = 0x0
3753 22:16:34.933404 WORK_FSP = 0x0
3754 22:16:34.933827 WL = 0x2
3755 22:16:34.936680 RL = 0x2
3756 22:16:34.937100 BL = 0x2
3757 22:16:34.939810 RPST = 0x0
3758 22:16:34.940429 RD_PRE = 0x0
3759 22:16:34.943683 WR_PRE = 0x1
3760 22:16:34.944260 WR_PST = 0x0
3761 22:16:34.946775 DBI_WR = 0x0
3762 22:16:34.947362 DBI_RD = 0x0
3763 22:16:34.950203 OTF = 0x1
3764 22:16:34.953584 ===================================
3765 22:16:34.956783 ===================================
3766 22:16:34.957373 ANA top config
3767 22:16:34.959880 ===================================
3768 22:16:34.963185 DLL_ASYNC_EN = 0
3769 22:16:34.966775 ALL_SLAVE_EN = 1
3770 22:16:34.969956 NEW_RANK_MODE = 1
3771 22:16:34.970549 DLL_IDLE_MODE = 1
3772 22:16:34.973410 LP45_APHY_COMB_EN = 1
3773 22:16:34.976681 TX_ODT_DIS = 1
3774 22:16:34.979753 NEW_8X_MODE = 1
3775 22:16:34.983204 ===================================
3776 22:16:34.986711 ===================================
3777 22:16:34.990549 data_rate = 1200
3778 22:16:34.991002 CKR = 1
3779 22:16:34.993621 DQ_P2S_RATIO = 8
3780 22:16:34.996602 ===================================
3781 22:16:34.999721 CA_P2S_RATIO = 8
3782 22:16:35.002992 DQ_CA_OPEN = 0
3783 22:16:35.007194 DQ_SEMI_OPEN = 0
3784 22:16:35.010050 CA_SEMI_OPEN = 0
3785 22:16:35.010472 CA_FULL_RATE = 0
3786 22:16:35.012876 DQ_CKDIV4_EN = 1
3787 22:16:35.016770 CA_CKDIV4_EN = 1
3788 22:16:35.020070 CA_PREDIV_EN = 0
3789 22:16:35.023049 PH8_DLY = 0
3790 22:16:35.026253 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3791 22:16:35.026838 DQ_AAMCK_DIV = 4
3792 22:16:35.029784 CA_AAMCK_DIV = 4
3793 22:16:35.033157 CA_ADMCK_DIV = 4
3794 22:16:35.036545 DQ_TRACK_CA_EN = 0
3795 22:16:35.039774 CA_PICK = 600
3796 22:16:35.043375 CA_MCKIO = 600
3797 22:16:35.046238 MCKIO_SEMI = 0
3798 22:16:35.046746 PLL_FREQ = 2288
3799 22:16:35.049352 DQ_UI_PI_RATIO = 32
3800 22:16:35.053129 CA_UI_PI_RATIO = 0
3801 22:16:35.055867 ===================================
3802 22:16:35.059729 ===================================
3803 22:16:35.062726 memory_type:LPDDR4
3804 22:16:35.063384 GP_NUM : 10
3805 22:16:35.066044 SRAM_EN : 1
3806 22:16:35.068994 MD32_EN : 0
3807 22:16:35.072600 ===================================
3808 22:16:35.073012 [ANA_INIT] >>>>>>>>>>>>>>
3809 22:16:35.076012 <<<<<< [CONFIGURE PHASE]: ANA_TX
3810 22:16:35.079341 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3811 22:16:35.082468 ===================================
3812 22:16:35.085722 data_rate = 1200,PCW = 0X5800
3813 22:16:35.089018 ===================================
3814 22:16:35.092989 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3815 22:16:35.099428 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3816 22:16:35.106447 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3817 22:16:35.108879 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3818 22:16:35.112934 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3819 22:16:35.115411 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3820 22:16:35.118975 [ANA_INIT] flow start
3821 22:16:35.119243 [ANA_INIT] PLL >>>>>>>>
3822 22:16:35.122087 [ANA_INIT] PLL <<<<<<<<
3823 22:16:35.125820 [ANA_INIT] MIDPI >>>>>>>>
3824 22:16:35.126126 [ANA_INIT] MIDPI <<<<<<<<
3825 22:16:35.129421 [ANA_INIT] DLL >>>>>>>>
3826 22:16:35.132181 [ANA_INIT] flow end
3827 22:16:35.135775 ============ LP4 DIFF to SE enter ============
3828 22:16:35.139011 ============ LP4 DIFF to SE exit ============
3829 22:16:35.142456 [ANA_INIT] <<<<<<<<<<<<<
3830 22:16:35.145763 [Flow] Enable top DCM control >>>>>
3831 22:16:35.149048 [Flow] Enable top DCM control <<<<<
3832 22:16:35.152241 Enable DLL master slave shuffle
3833 22:16:35.155119 ==============================================================
3834 22:16:35.158884 Gating Mode config
3835 22:16:35.165259 ==============================================================
3836 22:16:35.165353 Config description:
3837 22:16:35.175505 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3838 22:16:35.181961 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3839 22:16:35.185065 SELPH_MODE 0: By rank 1: By Phase
3840 22:16:35.192106 ==============================================================
3841 22:16:35.195261 GAT_TRACK_EN = 1
3842 22:16:35.198805 RX_GATING_MODE = 2
3843 22:16:35.201924 RX_GATING_TRACK_MODE = 2
3844 22:16:35.205391 SELPH_MODE = 1
3845 22:16:35.209138 PICG_EARLY_EN = 1
3846 22:16:35.212081 VALID_LAT_VALUE = 1
3847 22:16:35.215593 ==============================================================
3848 22:16:35.218592 Enter into Gating configuration >>>>
3849 22:16:35.221650 Exit from Gating configuration <<<<
3850 22:16:35.225086 Enter into DVFS_PRE_config >>>>>
3851 22:16:35.235143 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3852 22:16:35.239017 Exit from DVFS_PRE_config <<<<<
3853 22:16:35.241975 Enter into PICG configuration >>>>
3854 22:16:35.245307 Exit from PICG configuration <<<<
3855 22:16:35.248591 [RX_INPUT] configuration >>>>>
3856 22:16:35.252121 [RX_INPUT] configuration <<<<<
3857 22:16:35.258442 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3858 22:16:35.262268 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3859 22:16:35.268800 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3860 22:16:35.274932 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3861 22:16:35.281489 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3862 22:16:35.288372 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3863 22:16:35.291343 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3864 22:16:35.294823 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3865 22:16:35.298351 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3866 22:16:35.304626 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3867 22:16:35.308854 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3868 22:16:35.311388 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3869 22:16:35.314688 ===================================
3870 22:16:35.317834 LPDDR4 DRAM CONFIGURATION
3871 22:16:35.321237 ===================================
3872 22:16:35.321661 EX_ROW_EN[0] = 0x0
3873 22:16:35.324810 EX_ROW_EN[1] = 0x0
3874 22:16:35.327794 LP4Y_EN = 0x0
3875 22:16:35.328298 WORK_FSP = 0x0
3876 22:16:35.331588 WL = 0x2
3877 22:16:35.332045 RL = 0x2
3878 22:16:35.334899 BL = 0x2
3879 22:16:35.335403 RPST = 0x0
3880 22:16:35.337992 RD_PRE = 0x0
3881 22:16:35.338413 WR_PRE = 0x1
3882 22:16:35.341270 WR_PST = 0x0
3883 22:16:35.341689 DBI_WR = 0x0
3884 22:16:35.344900 DBI_RD = 0x0
3885 22:16:35.345322 OTF = 0x1
3886 22:16:35.347801 ===================================
3887 22:16:35.351298 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3888 22:16:35.358144 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3889 22:16:35.361258 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3890 22:16:35.364635 ===================================
3891 22:16:35.368261 LPDDR4 DRAM CONFIGURATION
3892 22:16:35.371623 ===================================
3893 22:16:35.372333 EX_ROW_EN[0] = 0x10
3894 22:16:35.374895 EX_ROW_EN[1] = 0x0
3895 22:16:35.377558 LP4Y_EN = 0x0
3896 22:16:35.378212 WORK_FSP = 0x0
3897 22:16:35.381264 WL = 0x2
3898 22:16:35.381712 RL = 0x2
3899 22:16:35.384372 BL = 0x2
3900 22:16:35.384787 RPST = 0x0
3901 22:16:35.387862 RD_PRE = 0x0
3902 22:16:35.388306 WR_PRE = 0x1
3903 22:16:35.390928 WR_PST = 0x0
3904 22:16:35.391343 DBI_WR = 0x0
3905 22:16:35.394642 DBI_RD = 0x0
3906 22:16:35.395060 OTF = 0x1
3907 22:16:35.397777 ===================================
3908 22:16:35.404513 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3909 22:16:35.408647 nWR fixed to 30
3910 22:16:35.412402 [ModeRegInit_LP4] CH0 RK0
3911 22:16:35.412949 [ModeRegInit_LP4] CH0 RK1
3912 22:16:35.415177 [ModeRegInit_LP4] CH1 RK0
3913 22:16:35.418524 [ModeRegInit_LP4] CH1 RK1
3914 22:16:35.419031 match AC timing 17
3915 22:16:35.425630 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3916 22:16:35.428881 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3917 22:16:35.431770 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3918 22:16:35.438682 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3919 22:16:35.441615 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3920 22:16:35.442044 ==
3921 22:16:35.444911 Dram Type= 6, Freq= 0, CH_0, rank 0
3922 22:16:35.448309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3923 22:16:35.448737 ==
3924 22:16:35.454627 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3925 22:16:35.461913 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3926 22:16:35.464987 [CA 0] Center 36 (6~66) winsize 61
3927 22:16:35.468168 [CA 1] Center 36 (6~66) winsize 61
3928 22:16:35.471268 [CA 2] Center 34 (4~65) winsize 62
3929 22:16:35.475315 [CA 3] Center 34 (4~65) winsize 62
3930 22:16:35.477999 [CA 4] Center 34 (4~64) winsize 61
3931 22:16:35.481365 [CA 5] Center 33 (3~64) winsize 62
3932 22:16:35.481764
3933 22:16:35.484808 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3934 22:16:35.485408
3935 22:16:35.487887 [CATrainingPosCal] consider 1 rank data
3936 22:16:35.491334 u2DelayCellTimex100 = 270/100 ps
3937 22:16:35.494761 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3938 22:16:35.497800 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3939 22:16:35.501997 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3940 22:16:35.505141 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3941 22:16:35.511110 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
3942 22:16:35.514367 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3943 22:16:35.514913
3944 22:16:35.517592 CA PerBit enable=1, Macro0, CA PI delay=33
3945 22:16:35.518140
3946 22:16:35.520763 [CBTSetCACLKResult] CA Dly = 33
3947 22:16:35.521254 CS Dly: 4 (0~35)
3948 22:16:35.521684 ==
3949 22:16:35.524494 Dram Type= 6, Freq= 0, CH_0, rank 1
3950 22:16:35.531089 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3951 22:16:35.531646 ==
3952 22:16:35.534137 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3953 22:16:35.540781 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3954 22:16:35.543870 [CA 0] Center 36 (6~66) winsize 61
3955 22:16:35.547042 [CA 1] Center 36 (6~66) winsize 61
3956 22:16:35.550443 [CA 2] Center 34 (4~65) winsize 62
3957 22:16:35.553739 [CA 3] Center 34 (4~65) winsize 62
3958 22:16:35.557165 [CA 4] Center 33 (3~64) winsize 62
3959 22:16:35.560380 [CA 5] Center 33 (3~64) winsize 62
3960 22:16:35.560806
3961 22:16:35.564366 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3962 22:16:35.564784
3963 22:16:35.566976 [CATrainingPosCal] consider 2 rank data
3964 22:16:35.570722 u2DelayCellTimex100 = 270/100 ps
3965 22:16:35.574104 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3966 22:16:35.581047 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3967 22:16:35.584124 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3968 22:16:35.587374 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3969 22:16:35.590678 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
3970 22:16:35.593829 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3971 22:16:35.594393
3972 22:16:35.597336 CA PerBit enable=1, Macro0, CA PI delay=33
3973 22:16:35.597896
3974 22:16:35.600231 [CBTSetCACLKResult] CA Dly = 33
3975 22:16:35.600775 CS Dly: 5 (0~37)
3976 22:16:35.601206
3977 22:16:35.606760 ----->DramcWriteLeveling(PI) begin...
3978 22:16:35.607435 ==
3979 22:16:35.610220 Dram Type= 6, Freq= 0, CH_0, rank 0
3980 22:16:35.613555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3981 22:16:35.614198 ==
3982 22:16:35.616760 Write leveling (Byte 0): 33 => 33
3983 22:16:35.620157 Write leveling (Byte 1): 29 => 29
3984 22:16:35.624031 DramcWriteLeveling(PI) end<-----
3985 22:16:35.624723
3986 22:16:35.625353 ==
3987 22:16:35.627293 Dram Type= 6, Freq= 0, CH_0, rank 0
3988 22:16:35.630562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3989 22:16:35.631261 ==
3990 22:16:35.633244 [Gating] SW mode calibration
3991 22:16:35.639950 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3992 22:16:35.646591 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3993 22:16:35.649945 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3994 22:16:35.653940 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3995 22:16:35.660081 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3996 22:16:35.663355 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3997 22:16:35.666657 0 9 16 | B1->B0 | 3131 2d2d | 0 0 | (0 0) (1 1)
3998 22:16:35.670100 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3999 22:16:35.676542 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4000 22:16:35.680052 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4001 22:16:35.683400 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4002 22:16:35.690839 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4003 22:16:35.693566 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4004 22:16:35.696710 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4005 22:16:35.703226 0 10 16 | B1->B0 | 302f 3c3c | 1 0 | (0 0) (0 0)
4006 22:16:35.706600 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4007 22:16:35.709821 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4008 22:16:35.716173 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4009 22:16:35.719538 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4010 22:16:35.723073 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4011 22:16:35.729529 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4012 22:16:35.732932 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4013 22:16:35.736802 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4014 22:16:35.743180 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4015 22:16:35.746227 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4016 22:16:35.749914 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4017 22:16:35.756752 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4018 22:16:35.760122 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4019 22:16:35.763082 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4020 22:16:35.770199 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4021 22:16:35.773183 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4022 22:16:35.776218 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4023 22:16:35.782874 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4024 22:16:35.786261 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4025 22:16:35.789425 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4026 22:16:35.796447 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4027 22:16:35.799241 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4028 22:16:35.802913 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4029 22:16:35.809286 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4030 22:16:35.812715 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4031 22:16:35.816134 Total UI for P1: 0, mck2ui 16
4032 22:16:35.819136 best dqsien dly found for B0: ( 0, 13, 16)
4033 22:16:35.822907 Total UI for P1: 0, mck2ui 16
4034 22:16:35.825857 best dqsien dly found for B1: ( 0, 13, 18)
4035 22:16:35.829542 best DQS0 dly(MCK, UI, PI) = (0, 13, 16)
4036 22:16:35.832499 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4037 22:16:35.832935
4038 22:16:35.836093 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 16)
4039 22:16:35.839719 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4040 22:16:35.843106 [Gating] SW calibration Done
4041 22:16:35.843656 ==
4042 22:16:35.846284 Dram Type= 6, Freq= 0, CH_0, rank 0
4043 22:16:35.850011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4044 22:16:35.850496 ==
4045 22:16:35.853079 RX Vref Scan: 0
4046 22:16:35.853558
4047 22:16:35.856022 RX Vref 0 -> 0, step: 1
4048 22:16:35.856452
4049 22:16:35.859086 RX Delay -230 -> 252, step: 16
4050 22:16:35.862385 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4051 22:16:35.865788 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4052 22:16:35.868780 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4053 22:16:35.872568 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4054 22:16:35.879411 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4055 22:16:35.882485 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4056 22:16:35.885696 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4057 22:16:35.888625 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4058 22:16:35.895621 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4059 22:16:35.898922 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4060 22:16:35.902702 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4061 22:16:35.905604 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4062 22:16:35.908800 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4063 22:16:35.915946 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4064 22:16:35.919471 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4065 22:16:35.922281 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4066 22:16:35.922790 ==
4067 22:16:35.925503 Dram Type= 6, Freq= 0, CH_0, rank 0
4068 22:16:35.932034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4069 22:16:35.932596 ==
4070 22:16:35.933075 DQS Delay:
4071 22:16:35.933532 DQS0 = 0, DQS1 = 0
4072 22:16:35.935034 DQM Delay:
4073 22:16:35.935516 DQM0 = 41, DQM1 = 32
4074 22:16:35.938514 DQ Delay:
4075 22:16:35.941825 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4076 22:16:35.945525 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4077 22:16:35.949108 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4078 22:16:35.951837 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =41
4079 22:16:35.952407
4080 22:16:35.952862
4081 22:16:35.953205 ==
4082 22:16:35.955367 Dram Type= 6, Freq= 0, CH_0, rank 0
4083 22:16:35.958506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4084 22:16:35.958937 ==
4085 22:16:35.959271
4086 22:16:35.959577
4087 22:16:35.962086 TX Vref Scan disable
4088 22:16:35.962499 == TX Byte 0 ==
4089 22:16:35.968486 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4090 22:16:35.971902 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4091 22:16:35.972387 == TX Byte 1 ==
4092 22:16:35.978446 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4093 22:16:35.981907 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4094 22:16:35.982331 ==
4095 22:16:35.985090 Dram Type= 6, Freq= 0, CH_0, rank 0
4096 22:16:35.988834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4097 22:16:35.989260 ==
4098 22:16:35.989595
4099 22:16:35.989909
4100 22:16:35.991877 TX Vref Scan disable
4101 22:16:35.995368 == TX Byte 0 ==
4102 22:16:35.998995 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4103 22:16:36.005445 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4104 22:16:36.005863 == TX Byte 1 ==
4105 22:16:36.008381 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4106 22:16:36.015619 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4107 22:16:36.016223
4108 22:16:36.016620 [DATLAT]
4109 22:16:36.016940 Freq=600, CH0 RK0
4110 22:16:36.017261
4111 22:16:36.018737 DATLAT Default: 0x9
4112 22:16:36.019151 0, 0xFFFF, sum = 0
4113 22:16:36.021941 1, 0xFFFF, sum = 0
4114 22:16:36.025713 2, 0xFFFF, sum = 0
4115 22:16:36.026136 3, 0xFFFF, sum = 0
4116 22:16:36.028527 4, 0xFFFF, sum = 0
4117 22:16:36.028948 5, 0xFFFF, sum = 0
4118 22:16:36.032129 6, 0xFFFF, sum = 0
4119 22:16:36.032554 7, 0xFFFF, sum = 0
4120 22:16:36.035283 8, 0x0, sum = 1
4121 22:16:36.035703 9, 0x0, sum = 2
4122 22:16:36.036090 10, 0x0, sum = 3
4123 22:16:36.038919 11, 0x0, sum = 4
4124 22:16:36.039342 best_step = 9
4125 22:16:36.039673
4126 22:16:36.040017 ==
4127 22:16:36.041717 Dram Type= 6, Freq= 0, CH_0, rank 0
4128 22:16:36.048756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4129 22:16:36.049178 ==
4130 22:16:36.049511 RX Vref Scan: 1
4131 22:16:36.049866
4132 22:16:36.051728 RX Vref 0 -> 0, step: 1
4133 22:16:36.052196
4134 22:16:36.055189 RX Delay -195 -> 252, step: 8
4135 22:16:36.055606
4136 22:16:36.058415 Set Vref, RX VrefLevel [Byte0]: 53
4137 22:16:36.061978 [Byte1]: 51
4138 22:16:36.062396
4139 22:16:36.065269 Final RX Vref Byte 0 = 53 to rank0
4140 22:16:36.068499 Final RX Vref Byte 1 = 51 to rank0
4141 22:16:36.071306 Final RX Vref Byte 0 = 53 to rank1
4142 22:16:36.074532 Final RX Vref Byte 1 = 51 to rank1==
4143 22:16:36.077868 Dram Type= 6, Freq= 0, CH_0, rank 0
4144 22:16:36.081564 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4145 22:16:36.081647 ==
4146 22:16:36.084206 DQS Delay:
4147 22:16:36.084287 DQS0 = 0, DQS1 = 0
4148 22:16:36.087591 DQM Delay:
4149 22:16:36.087687 DQM0 = 41, DQM1 = 34
4150 22:16:36.087753 DQ Delay:
4151 22:16:36.091140 DQ0 =44, DQ1 =40, DQ2 =36, DQ3 =40
4152 22:16:36.094494 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4153 22:16:36.097811 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =32
4154 22:16:36.101151 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44
4155 22:16:36.101252
4156 22:16:36.101331
4157 22:16:36.110953 [DQSOSCAuto] RK0, (LSB)MR18= 0x3d1b, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 398 ps
4158 22:16:36.114163 CH0 RK0: MR19=808, MR18=3D1B
4159 22:16:36.121029 CH0_RK0: MR19=0x808, MR18=0x3D1B, DQSOSC=398, MR23=63, INC=165, DEC=110
4160 22:16:36.121190
4161 22:16:36.124178 ----->DramcWriteLeveling(PI) begin...
4162 22:16:36.124361 ==
4163 22:16:36.127876 Dram Type= 6, Freq= 0, CH_0, rank 1
4164 22:16:36.130959 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4165 22:16:36.131169 ==
4166 22:16:36.134575 Write leveling (Byte 0): 31 => 31
4167 22:16:36.137897 Write leveling (Byte 1): 31 => 31
4168 22:16:36.141185 DramcWriteLeveling(PI) end<-----
4169 22:16:36.141525
4170 22:16:36.141875 ==
4171 22:16:36.144644 Dram Type= 6, Freq= 0, CH_0, rank 1
4172 22:16:36.147719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4173 22:16:36.148234 ==
4174 22:16:36.150971 [Gating] SW mode calibration
4175 22:16:36.157928 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4176 22:16:36.164822 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4177 22:16:36.167771 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4178 22:16:36.171601 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4179 22:16:36.177668 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4180 22:16:36.180974 0 9 12 | B1->B0 | 3434 3232 | 1 1 | (1 0) (1 0)
4181 22:16:36.184859 0 9 16 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
4182 22:16:36.191105 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4183 22:16:36.194638 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4184 22:16:36.197625 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4185 22:16:36.204429 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4186 22:16:36.207857 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4187 22:16:36.211143 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4188 22:16:36.217656 0 10 12 | B1->B0 | 2323 3838 | 0 0 | (0 0) (0 0)
4189 22:16:36.220259 0 10 16 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
4190 22:16:36.223635 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4191 22:16:36.226995 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4192 22:16:36.234119 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4193 22:16:36.237542 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4194 22:16:36.240773 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4195 22:16:36.247722 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4196 22:16:36.250697 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4197 22:16:36.254272 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4198 22:16:36.261154 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4199 22:16:36.264628 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4200 22:16:36.267447 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4201 22:16:36.274238 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4202 22:16:36.277525 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4203 22:16:36.281041 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4204 22:16:36.287736 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4205 22:16:36.290924 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4206 22:16:36.294256 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4207 22:16:36.301123 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4208 22:16:36.304014 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4209 22:16:36.307837 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4210 22:16:36.314081 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4211 22:16:36.317630 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4212 22:16:36.320708 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4213 22:16:36.327131 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4214 22:16:36.327555 Total UI for P1: 0, mck2ui 16
4215 22:16:36.334045 best dqsien dly found for B0: ( 0, 13, 12)
4216 22:16:36.337516 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4217 22:16:36.340410 Total UI for P1: 0, mck2ui 16
4218 22:16:36.343540 best dqsien dly found for B1: ( 0, 13, 16)
4219 22:16:36.346851 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4220 22:16:36.350316 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4221 22:16:36.350742
4222 22:16:36.353928 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4223 22:16:36.356845 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4224 22:16:36.359939 [Gating] SW calibration Done
4225 22:16:36.360437 ==
4226 22:16:36.363201 Dram Type= 6, Freq= 0, CH_0, rank 1
4227 22:16:36.370263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4228 22:16:36.370734 ==
4229 22:16:36.371121 RX Vref Scan: 0
4230 22:16:36.371520
4231 22:16:36.373844 RX Vref 0 -> 0, step: 1
4232 22:16:36.374292
4233 22:16:36.376830 RX Delay -230 -> 252, step: 16
4234 22:16:36.379914 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4235 22:16:36.383767 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4236 22:16:36.386741 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4237 22:16:36.393399 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4238 22:16:36.396564 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4239 22:16:36.399632 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4240 22:16:36.403184 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4241 22:16:36.406485 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4242 22:16:36.413179 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4243 22:16:36.416585 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4244 22:16:36.419896 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4245 22:16:36.422793 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4246 22:16:36.429693 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4247 22:16:36.433156 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4248 22:16:36.436489 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4249 22:16:36.439502 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4250 22:16:36.442562 ==
4251 22:16:36.442645 Dram Type= 6, Freq= 0, CH_0, rank 1
4252 22:16:36.449337 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4253 22:16:36.449420 ==
4254 22:16:36.449486 DQS Delay:
4255 22:16:36.452574 DQS0 = 0, DQS1 = 0
4256 22:16:36.452657 DQM Delay:
4257 22:16:36.455903 DQM0 = 39, DQM1 = 34
4258 22:16:36.456040 DQ Delay:
4259 22:16:36.459068 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4260 22:16:36.463354 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4261 22:16:36.465954 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =25
4262 22:16:36.469127 DQ12 =33, DQ13 =41, DQ14 =49, DQ15 =41
4263 22:16:36.469210
4264 22:16:36.469276
4265 22:16:36.469337 ==
4266 22:16:36.472551 Dram Type= 6, Freq= 0, CH_0, rank 1
4267 22:16:36.475634 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4268 22:16:36.475717 ==
4269 22:16:36.475783
4270 22:16:36.475844
4271 22:16:36.479450 TX Vref Scan disable
4272 22:16:36.482808 == TX Byte 0 ==
4273 22:16:36.486296 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4274 22:16:36.489665 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4275 22:16:36.492333 == TX Byte 1 ==
4276 22:16:36.495477 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4277 22:16:36.498829 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4278 22:16:36.498899 ==
4279 22:16:36.502844 Dram Type= 6, Freq= 0, CH_0, rank 1
4280 22:16:36.505314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4281 22:16:36.508880 ==
4282 22:16:36.508951
4283 22:16:36.509021
4284 22:16:36.509090 TX Vref Scan disable
4285 22:16:36.512934 == TX Byte 0 ==
4286 22:16:36.516201 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4287 22:16:36.523070 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4288 22:16:36.523148 == TX Byte 1 ==
4289 22:16:36.526176 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4290 22:16:36.532886 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4291 22:16:36.532974
4292 22:16:36.533038 [DATLAT]
4293 22:16:36.533103 Freq=600, CH0 RK1
4294 22:16:36.533164
4295 22:16:36.536235 DATLAT Default: 0x9
4296 22:16:36.536329 0, 0xFFFF, sum = 0
4297 22:16:36.539453 1, 0xFFFF, sum = 0
4298 22:16:36.539524 2, 0xFFFF, sum = 0
4299 22:16:36.542518 3, 0xFFFF, sum = 0
4300 22:16:36.546345 4, 0xFFFF, sum = 0
4301 22:16:36.546417 5, 0xFFFF, sum = 0
4302 22:16:36.549479 6, 0xFFFF, sum = 0
4303 22:16:36.549551 7, 0xFFFF, sum = 0
4304 22:16:36.552295 8, 0x0, sum = 1
4305 22:16:36.552400 9, 0x0, sum = 2
4306 22:16:36.552468 10, 0x0, sum = 3
4307 22:16:36.555764 11, 0x0, sum = 4
4308 22:16:36.555843 best_step = 9
4309 22:16:36.555914
4310 22:16:36.556042 ==
4311 22:16:36.559420 Dram Type= 6, Freq= 0, CH_0, rank 1
4312 22:16:36.565712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4313 22:16:36.565797 ==
4314 22:16:36.565860 RX Vref Scan: 0
4315 22:16:36.565924
4316 22:16:36.569270 RX Vref 0 -> 0, step: 1
4317 22:16:36.569337
4318 22:16:36.572471 RX Delay -179 -> 252, step: 8
4319 22:16:36.576073 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4320 22:16:36.582428 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4321 22:16:36.585493 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4322 22:16:36.588938 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4323 22:16:36.592081 iDelay=205, Bit 4, Center 36 (-115 ~ 188) 304
4324 22:16:36.599022 iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304
4325 22:16:36.602333 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4326 22:16:36.605070 iDelay=205, Bit 7, Center 44 (-107 ~ 196) 304
4327 22:16:36.608348 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4328 22:16:36.615101 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4329 22:16:36.618515 iDelay=205, Bit 10, Center 36 (-115 ~ 188) 304
4330 22:16:36.621855 iDelay=205, Bit 11, Center 20 (-131 ~ 172) 304
4331 22:16:36.625543 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4332 22:16:36.628542 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4333 22:16:36.635585 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4334 22:16:36.638732 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4335 22:16:36.638810 ==
4336 22:16:36.642703 Dram Type= 6, Freq= 0, CH_0, rank 1
4337 22:16:36.646062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4338 22:16:36.646133 ==
4339 22:16:36.648908 DQS Delay:
4340 22:16:36.648979 DQS0 = 0, DQS1 = 0
4341 22:16:36.649058 DQM Delay:
4342 22:16:36.651872 DQM0 = 39, DQM1 = 33
4343 22:16:36.651990 DQ Delay:
4344 22:16:36.655538 DQ0 =40, DQ1 =40, DQ2 =36, DQ3 =40
4345 22:16:36.658562 DQ4 =36, DQ5 =28, DQ6 =48, DQ7 =44
4346 22:16:36.662367 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =20
4347 22:16:36.665273 DQ12 =36, DQ13 =40, DQ14 =44, DQ15 =40
4348 22:16:36.665352
4349 22:16:36.665425
4350 22:16:36.675405 [DQSOSCAuto] RK1, (LSB)MR18= 0x4627, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 396 ps
4351 22:16:36.675482 CH0 RK1: MR19=808, MR18=4627
4352 22:16:36.682175 CH0_RK1: MR19=0x808, MR18=0x4627, DQSOSC=396, MR23=63, INC=167, DEC=111
4353 22:16:36.685412 [RxdqsGatingPostProcess] freq 600
4354 22:16:36.691899 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4355 22:16:36.696001 Pre-setting of DQS Precalculation
4356 22:16:36.698645 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4357 22:16:36.698717 ==
4358 22:16:36.701857 Dram Type= 6, Freq= 0, CH_1, rank 0
4359 22:16:36.708457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4360 22:16:36.708531 ==
4361 22:16:36.711693 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4362 22:16:36.718499 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4363 22:16:36.721737 [CA 0] Center 35 (5~66) winsize 62
4364 22:16:36.725272 [CA 1] Center 35 (5~66) winsize 62
4365 22:16:36.728912 [CA 2] Center 34 (4~65) winsize 62
4366 22:16:36.732224 [CA 3] Center 33 (3~64) winsize 62
4367 22:16:36.735151 [CA 4] Center 34 (3~65) winsize 63
4368 22:16:36.739075 [CA 5] Center 33 (3~64) winsize 62
4369 22:16:36.739249
4370 22:16:36.741841 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4371 22:16:36.741980
4372 22:16:36.745200 [CATrainingPosCal] consider 1 rank data
4373 22:16:36.748949 u2DelayCellTimex100 = 270/100 ps
4374 22:16:36.752911 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4375 22:16:36.755307 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4376 22:16:36.761763 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4377 22:16:36.765094 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4378 22:16:36.768180 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4379 22:16:36.772058 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4380 22:16:36.772333
4381 22:16:36.775472 CA PerBit enable=1, Macro0, CA PI delay=33
4382 22:16:36.775795
4383 22:16:36.778446 [CBTSetCACLKResult] CA Dly = 33
4384 22:16:36.778831 CS Dly: 4 (0~35)
4385 22:16:36.782187 ==
4386 22:16:36.785368 Dram Type= 6, Freq= 0, CH_1, rank 1
4387 22:16:36.789641 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4388 22:16:36.790205 ==
4389 22:16:36.791908 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4390 22:16:36.798266 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4391 22:16:36.801913 [CA 0] Center 35 (5~66) winsize 62
4392 22:16:36.805662 [CA 1] Center 36 (6~66) winsize 61
4393 22:16:36.808776 [CA 2] Center 34 (4~65) winsize 62
4394 22:16:36.812236 [CA 3] Center 34 (3~65) winsize 63
4395 22:16:36.815213 [CA 4] Center 34 (4~65) winsize 62
4396 22:16:36.818735 [CA 5] Center 33 (3~64) winsize 62
4397 22:16:36.819284
4398 22:16:36.822093 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4399 22:16:36.822550
4400 22:16:36.825135 [CATrainingPosCal] consider 2 rank data
4401 22:16:36.828284 u2DelayCellTimex100 = 270/100 ps
4402 22:16:36.832286 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4403 22:16:36.838323 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4404 22:16:36.841794 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4405 22:16:36.844939 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4406 22:16:36.848495 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4407 22:16:36.851676 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4408 22:16:36.852234
4409 22:16:36.855348 CA PerBit enable=1, Macro0, CA PI delay=33
4410 22:16:36.855911
4411 22:16:36.858541 [CBTSetCACLKResult] CA Dly = 33
4412 22:16:36.861701 CS Dly: 5 (0~38)
4413 22:16:36.862269
4414 22:16:36.865278 ----->DramcWriteLeveling(PI) begin...
4415 22:16:36.865719 ==
4416 22:16:36.867873 Dram Type= 6, Freq= 0, CH_1, rank 0
4417 22:16:36.871386 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4418 22:16:36.871909 ==
4419 22:16:36.874398 Write leveling (Byte 0): 28 => 28
4420 22:16:36.877928 Write leveling (Byte 1): 32 => 32
4421 22:16:36.881164 DramcWriteLeveling(PI) end<-----
4422 22:16:36.881704
4423 22:16:36.882055 ==
4424 22:16:36.884389 Dram Type= 6, Freq= 0, CH_1, rank 0
4425 22:16:36.887822 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4426 22:16:36.888330 ==
4427 22:16:36.891112 [Gating] SW mode calibration
4428 22:16:36.897884 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4429 22:16:36.903739 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4430 22:16:36.907368 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4431 22:16:36.910581 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4432 22:16:36.917135 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4433 22:16:36.920626 0 9 12 | B1->B0 | 3434 3333 | 1 1 | (0 0) (0 1)
4434 22:16:36.923788 0 9 16 | B1->B0 | 2929 2424 | 0 0 | (1 1) (0 0)
4435 22:16:36.930170 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4436 22:16:36.933538 0 9 24 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
4437 22:16:36.937005 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4438 22:16:36.943452 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4439 22:16:36.947051 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4440 22:16:36.950266 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4441 22:16:36.957363 0 10 12 | B1->B0 | 2626 2b2b | 0 0 | (0 0) (1 1)
4442 22:16:36.960157 0 10 16 | B1->B0 | 4343 4343 | 0 0 | (0 0) (0 0)
4443 22:16:36.963731 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4444 22:16:36.970542 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4445 22:16:36.973601 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4446 22:16:36.976643 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4447 22:16:36.983412 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4448 22:16:36.987156 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4449 22:16:36.990093 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4450 22:16:36.996980 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4451 22:16:36.999888 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4452 22:16:37.003139 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4453 22:16:37.010081 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4454 22:16:37.013391 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4455 22:16:37.016699 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4456 22:16:37.023749 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4457 22:16:37.026601 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4458 22:16:37.029667 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4459 22:16:37.036792 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4460 22:16:37.040066 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4461 22:16:37.043493 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4462 22:16:37.050209 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4463 22:16:37.053436 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4464 22:16:37.056746 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4465 22:16:37.060079 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4466 22:16:37.063337 Total UI for P1: 0, mck2ui 16
4467 22:16:37.066558 best dqsien dly found for B1: ( 0, 13, 10)
4468 22:16:37.073110 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4469 22:16:37.076756 Total UI for P1: 0, mck2ui 16
4470 22:16:37.079920 best dqsien dly found for B0: ( 0, 13, 12)
4471 22:16:37.083126 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4472 22:16:37.086289 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4473 22:16:37.086380
4474 22:16:37.090024 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4475 22:16:37.093958 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4476 22:16:37.096559 [Gating] SW calibration Done
4477 22:16:37.096792 ==
4478 22:16:37.100329 Dram Type= 6, Freq= 0, CH_1, rank 0
4479 22:16:37.103124 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4480 22:16:37.103268 ==
4481 22:16:37.106785 RX Vref Scan: 0
4482 22:16:37.106918
4483 22:16:37.109983 RX Vref 0 -> 0, step: 1
4484 22:16:37.110156
4485 22:16:37.110303 RX Delay -230 -> 252, step: 16
4486 22:16:37.116256 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4487 22:16:37.119668 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4488 22:16:37.123307 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4489 22:16:37.126748 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4490 22:16:37.133307 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4491 22:16:37.136529 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4492 22:16:37.139790 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4493 22:16:37.143090 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4494 22:16:37.149878 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4495 22:16:37.152855 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4496 22:16:37.156245 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4497 22:16:37.159446 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4498 22:16:37.166546 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4499 22:16:37.169665 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4500 22:16:37.173583 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4501 22:16:37.175937 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4502 22:16:37.176382 ==
4503 22:16:37.179396 Dram Type= 6, Freq= 0, CH_1, rank 0
4504 22:16:37.186223 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4505 22:16:37.186649 ==
4506 22:16:37.186983 DQS Delay:
4507 22:16:37.187293 DQS0 = 0, DQS1 = 0
4508 22:16:37.189611 DQM Delay:
4509 22:16:37.190033 DQM0 = 43, DQM1 = 35
4510 22:16:37.193760 DQ Delay:
4511 22:16:37.196249 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4512 22:16:37.199283 DQ4 =41, DQ5 =49, DQ6 =57, DQ7 =41
4513 22:16:37.203127 DQ8 =17, DQ9 =17, DQ10 =41, DQ11 =33
4514 22:16:37.205985 DQ12 =49, DQ13 =41, DQ14 =41, DQ15 =41
4515 22:16:37.206406
4516 22:16:37.206743
4517 22:16:37.207091 ==
4518 22:16:37.209653 Dram Type= 6, Freq= 0, CH_1, rank 0
4519 22:16:37.212748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4520 22:16:37.213171 ==
4521 22:16:37.213502
4522 22:16:37.213812
4523 22:16:37.216506 TX Vref Scan disable
4524 22:16:37.216925 == TX Byte 0 ==
4525 22:16:37.222685 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4526 22:16:37.226479 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4527 22:16:37.226904 == TX Byte 1 ==
4528 22:16:37.233305 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4529 22:16:37.235833 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4530 22:16:37.236309 ==
4531 22:16:37.239125 Dram Type= 6, Freq= 0, CH_1, rank 0
4532 22:16:37.242822 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4533 22:16:37.243365 ==
4534 22:16:37.243715
4535 22:16:37.244078
4536 22:16:37.246013 TX Vref Scan disable
4537 22:16:37.249805 == TX Byte 0 ==
4538 22:16:37.253415 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4539 22:16:37.255976 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4540 22:16:37.259084 == TX Byte 1 ==
4541 22:16:37.263385 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4542 22:16:37.266534 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4543 22:16:37.269193
4544 22:16:37.269633 [DATLAT]
4545 22:16:37.269971 Freq=600, CH1 RK0
4546 22:16:37.270287
4547 22:16:37.272553 DATLAT Default: 0x9
4548 22:16:37.272970 0, 0xFFFF, sum = 0
4549 22:16:37.276126 1, 0xFFFF, sum = 0
4550 22:16:37.276649 2, 0xFFFF, sum = 0
4551 22:16:37.279640 3, 0xFFFF, sum = 0
4552 22:16:37.280093 4, 0xFFFF, sum = 0
4553 22:16:37.282564 5, 0xFFFF, sum = 0
4554 22:16:37.285699 6, 0xFFFF, sum = 0
4555 22:16:37.286129 7, 0xFFFF, sum = 0
4556 22:16:37.286471 8, 0x0, sum = 1
4557 22:16:37.289351 9, 0x0, sum = 2
4558 22:16:37.289778 10, 0x0, sum = 3
4559 22:16:37.292603 11, 0x0, sum = 4
4560 22:16:37.293033 best_step = 9
4561 22:16:37.293368
4562 22:16:37.293678 ==
4563 22:16:37.295348 Dram Type= 6, Freq= 0, CH_1, rank 0
4564 22:16:37.302008 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4565 22:16:37.302091 ==
4566 22:16:37.302156 RX Vref Scan: 1
4567 22:16:37.302217
4568 22:16:37.305292 RX Vref 0 -> 0, step: 1
4569 22:16:37.305373
4570 22:16:37.309010 RX Delay -195 -> 252, step: 8
4571 22:16:37.309092
4572 22:16:37.312178 Set Vref, RX VrefLevel [Byte0]: 58
4573 22:16:37.315370 [Byte1]: 52
4574 22:16:37.315452
4575 22:16:37.319055 Final RX Vref Byte 0 = 58 to rank0
4576 22:16:37.322050 Final RX Vref Byte 1 = 52 to rank0
4577 22:16:37.325044 Final RX Vref Byte 0 = 58 to rank1
4578 22:16:37.328785 Final RX Vref Byte 1 = 52 to rank1==
4579 22:16:37.332243 Dram Type= 6, Freq= 0, CH_1, rank 0
4580 22:16:37.335484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4581 22:16:37.335567 ==
4582 22:16:37.338577 DQS Delay:
4583 22:16:37.338659 DQS0 = 0, DQS1 = 0
4584 22:16:37.342278 DQM Delay:
4585 22:16:37.342359 DQM0 = 40, DQM1 = 33
4586 22:16:37.342464 DQ Delay:
4587 22:16:37.345039 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =40
4588 22:16:37.348398 DQ4 =36, DQ5 =48, DQ6 =52, DQ7 =36
4589 22:16:37.352250 DQ8 =20, DQ9 =24, DQ10 =36, DQ11 =24
4590 22:16:37.355342 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4591 22:16:37.355423
4592 22:16:37.355488
4593 22:16:37.365219 [DQSOSCAuto] RK0, (LSB)MR18= 0x4006, (MSB)MR19= 0x808, tDQSOscB0 = 408 ps tDQSOscB1 = 397 ps
4594 22:16:37.368292 CH1 RK0: MR19=808, MR18=4006
4595 22:16:37.375139 CH1_RK0: MR19=0x808, MR18=0x4006, DQSOSC=397, MR23=63, INC=166, DEC=110
4596 22:16:37.375223
4597 22:16:37.378199 ----->DramcWriteLeveling(PI) begin...
4598 22:16:37.378282 ==
4599 22:16:37.381611 Dram Type= 6, Freq= 0, CH_1, rank 1
4600 22:16:37.386278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4601 22:16:37.386360 ==
4602 22:16:37.388443 Write leveling (Byte 0): 28 => 28
4603 22:16:37.391725 Write leveling (Byte 1): 29 => 29
4604 22:16:37.395029 DramcWriteLeveling(PI) end<-----
4605 22:16:37.395111
4606 22:16:37.395175 ==
4607 22:16:37.398627 Dram Type= 6, Freq= 0, CH_1, rank 1
4608 22:16:37.401789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4609 22:16:37.401871 ==
4610 22:16:37.405140 [Gating] SW mode calibration
4611 22:16:37.411870 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4612 22:16:37.417914 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4613 22:16:37.421927 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4614 22:16:37.424971 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4615 22:16:37.431317 0 9 8 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 0)
4616 22:16:37.434955 0 9 12 | B1->B0 | 3333 2d2d | 1 1 | (1 1) (1 0)
4617 22:16:37.437952 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4618 22:16:37.445151 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4619 22:16:37.448220 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4620 22:16:37.451749 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4621 22:16:37.455155 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4622 22:16:37.461856 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4623 22:16:37.465108 0 10 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
4624 22:16:37.468418 0 10 12 | B1->B0 | 3232 3d3d | 0 1 | (0 0) (0 0)
4625 22:16:37.474643 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4626 22:16:37.478363 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4627 22:16:37.481361 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4628 22:16:37.488290 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4629 22:16:37.491509 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4630 22:16:37.494594 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4631 22:16:37.501452 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4632 22:16:37.504835 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4633 22:16:37.507925 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4634 22:16:37.514784 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4635 22:16:37.518341 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4636 22:16:37.521045 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4637 22:16:37.527919 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4638 22:16:37.531725 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4639 22:16:37.534121 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4640 22:16:37.541148 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4641 22:16:37.544324 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4642 22:16:37.547801 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4643 22:16:37.554414 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4644 22:16:37.557875 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4645 22:16:37.560588 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4646 22:16:37.567791 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4647 22:16:37.570591 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4648 22:16:37.574080 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4649 22:16:37.580779 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4650 22:16:37.580864 Total UI for P1: 0, mck2ui 16
4651 22:16:37.587631 best dqsien dly found for B0: ( 0, 13, 12)
4652 22:16:37.587714 Total UI for P1: 0, mck2ui 16
4653 22:16:37.590846 best dqsien dly found for B1: ( 0, 13, 14)
4654 22:16:37.597403 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4655 22:16:37.600670 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4656 22:16:37.600744
4657 22:16:37.603941 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4658 22:16:37.607368 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4659 22:16:37.610516 [Gating] SW calibration Done
4660 22:16:37.610600 ==
4661 22:16:37.614324 Dram Type= 6, Freq= 0, CH_1, rank 1
4662 22:16:37.617445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4663 22:16:37.617528 ==
4664 22:16:37.620832 RX Vref Scan: 0
4665 22:16:37.620904
4666 22:16:37.620979 RX Vref 0 -> 0, step: 1
4667 22:16:37.621038
4668 22:16:37.623766 RX Delay -230 -> 252, step: 16
4669 22:16:37.627165 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4670 22:16:37.633858 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4671 22:16:37.636973 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4672 22:16:37.640226 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4673 22:16:37.643681 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4674 22:16:37.650304 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4675 22:16:37.653511 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4676 22:16:37.656733 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4677 22:16:37.660106 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4678 22:16:37.666929 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4679 22:16:37.670154 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4680 22:16:37.673343 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4681 22:16:37.677033 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4682 22:16:37.680643 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4683 22:16:37.686910 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4684 22:16:37.690265 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4685 22:16:37.690340 ==
4686 22:16:37.693694 Dram Type= 6, Freq= 0, CH_1, rank 1
4687 22:16:37.696821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4688 22:16:37.696895 ==
4689 22:16:37.700550 DQS Delay:
4690 22:16:37.700638 DQS0 = 0, DQS1 = 0
4691 22:16:37.703217 DQM Delay:
4692 22:16:37.703305 DQM0 = 39, DQM1 = 36
4693 22:16:37.703375 DQ Delay:
4694 22:16:37.706541 DQ0 =41, DQ1 =33, DQ2 =25, DQ3 =41
4695 22:16:37.710343 DQ4 =33, DQ5 =57, DQ6 =49, DQ7 =33
4696 22:16:37.713675 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4697 22:16:37.716532 DQ12 =41, DQ13 =49, DQ14 =41, DQ15 =41
4698 22:16:37.716644
4699 22:16:37.716732
4700 22:16:37.719837 ==
4701 22:16:37.723414 Dram Type= 6, Freq= 0, CH_1, rank 1
4702 22:16:37.726769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4703 22:16:37.726906 ==
4704 22:16:37.727014
4705 22:16:37.727114
4706 22:16:37.729631 TX Vref Scan disable
4707 22:16:37.729774 == TX Byte 0 ==
4708 22:16:37.736349 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4709 22:16:37.739656 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4710 22:16:37.739834 == TX Byte 1 ==
4711 22:16:37.746250 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4712 22:16:37.749594 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4713 22:16:37.749669 ==
4714 22:16:37.753186 Dram Type= 6, Freq= 0, CH_1, rank 1
4715 22:16:37.756264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4716 22:16:37.756347 ==
4717 22:16:37.756410
4718 22:16:37.756475
4719 22:16:37.759567 TX Vref Scan disable
4720 22:16:37.762866 == TX Byte 0 ==
4721 22:16:37.766150 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4722 22:16:37.769551 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4723 22:16:37.773144 == TX Byte 1 ==
4724 22:16:37.776282 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4725 22:16:37.779403 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4726 22:16:37.779476
4727 22:16:37.782725 [DATLAT]
4728 22:16:37.782797 Freq=600, CH1 RK1
4729 22:16:37.782860
4730 22:16:37.786010 DATLAT Default: 0x9
4731 22:16:37.786086 0, 0xFFFF, sum = 0
4732 22:16:37.789723 1, 0xFFFF, sum = 0
4733 22:16:37.789797 2, 0xFFFF, sum = 0
4734 22:16:37.793175 3, 0xFFFF, sum = 0
4735 22:16:37.793246 4, 0xFFFF, sum = 0
4736 22:16:37.795826 5, 0xFFFF, sum = 0
4737 22:16:37.795901 6, 0xFFFF, sum = 0
4738 22:16:37.799295 7, 0xFFFF, sum = 0
4739 22:16:37.799486 8, 0x0, sum = 1
4740 22:16:37.802669 9, 0x0, sum = 2
4741 22:16:37.802789 10, 0x0, sum = 3
4742 22:16:37.806199 11, 0x0, sum = 4
4743 22:16:37.806294 best_step = 9
4744 22:16:37.806383
4745 22:16:37.806459 ==
4746 22:16:37.809943 Dram Type= 6, Freq= 0, CH_1, rank 1
4747 22:16:37.815585 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4748 22:16:37.815662 ==
4749 22:16:37.815733 RX Vref Scan: 0
4750 22:16:37.815796
4751 22:16:37.819606 RX Vref 0 -> 0, step: 1
4752 22:16:37.819677
4753 22:16:37.822618 RX Delay -179 -> 252, step: 8
4754 22:16:37.825912 iDelay=205, Bit 0, Center 44 (-107 ~ 196) 304
4755 22:16:37.832953 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4756 22:16:37.835571 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4757 22:16:37.839200 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4758 22:16:37.841927 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4759 22:16:37.845773 iDelay=205, Bit 5, Center 52 (-99 ~ 204) 304
4760 22:16:37.852340 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4761 22:16:37.855880 iDelay=205, Bit 7, Center 36 (-115 ~ 188) 304
4762 22:16:37.858932 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4763 22:16:37.862298 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4764 22:16:37.868768 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4765 22:16:37.872255 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4766 22:16:37.875373 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4767 22:16:37.878870 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4768 22:16:37.885329 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4769 22:16:37.888569 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4770 22:16:37.888654 ==
4771 22:16:37.891869 Dram Type= 6, Freq= 0, CH_1, rank 1
4772 22:16:37.895397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4773 22:16:37.895493 ==
4774 22:16:37.898451 DQS Delay:
4775 22:16:37.898534 DQS0 = 0, DQS1 = 0
4776 22:16:37.898604 DQM Delay:
4777 22:16:37.901876 DQM0 = 39, DQM1 = 33
4778 22:16:37.901966 DQ Delay:
4779 22:16:37.905188 DQ0 =44, DQ1 =32, DQ2 =24, DQ3 =36
4780 22:16:37.908873 DQ4 =40, DQ5 =52, DQ6 =48, DQ7 =36
4781 22:16:37.912078 DQ8 =20, DQ9 =24, DQ10 =36, DQ11 =24
4782 22:16:37.915383 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4783 22:16:37.915461
4784 22:16:37.915541
4785 22:16:37.925132 [DQSOSCAuto] RK1, (LSB)MR18= 0x3746, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 399 ps
4786 22:16:37.925252 CH1 RK1: MR19=808, MR18=3746
4787 22:16:37.931878 CH1_RK1: MR19=0x808, MR18=0x3746, DQSOSC=396, MR23=63, INC=167, DEC=111
4788 22:16:37.935096 [RxdqsGatingPostProcess] freq 600
4789 22:16:37.941675 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4790 22:16:37.945457 Pre-setting of DQS Precalculation
4791 22:16:37.948257 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4792 22:16:37.955789 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4793 22:16:37.965505 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4794 22:16:37.965936
4795 22:16:37.966266
4796 22:16:37.966579 [Calibration Summary] 1200 Mbps
4797 22:16:37.968463 CH 0, Rank 0
4798 22:16:37.968797 SW Impedance : PASS
4799 22:16:37.972521 DUTY Scan : NO K
4800 22:16:37.975401 ZQ Calibration : PASS
4801 22:16:37.975823 Jitter Meter : NO K
4802 22:16:37.978831 CBT Training : PASS
4803 22:16:37.982261 Write leveling : PASS
4804 22:16:37.982730 RX DQS gating : PASS
4805 22:16:37.985550 RX DQ/DQS(RDDQC) : PASS
4806 22:16:37.988919 TX DQ/DQS : PASS
4807 22:16:37.989298 RX DATLAT : PASS
4808 22:16:37.992111 RX DQ/DQS(Engine): PASS
4809 22:16:37.995292 TX OE : NO K
4810 22:16:37.995668 All Pass.
4811 22:16:37.996067
4812 22:16:37.996393 CH 0, Rank 1
4813 22:16:37.998793 SW Impedance : PASS
4814 22:16:38.001841 DUTY Scan : NO K
4815 22:16:38.002317 ZQ Calibration : PASS
4816 22:16:38.005133 Jitter Meter : NO K
4817 22:16:38.008859 CBT Training : PASS
4818 22:16:38.009280 Write leveling : PASS
4819 22:16:38.011808 RX DQS gating : PASS
4820 22:16:38.015349 RX DQ/DQS(RDDQC) : PASS
4821 22:16:38.015818 TX DQ/DQS : PASS
4822 22:16:38.018464 RX DATLAT : PASS
4823 22:16:38.018916 RX DQ/DQS(Engine): PASS
4824 22:16:38.021856 TX OE : NO K
4825 22:16:38.022296 All Pass.
4826 22:16:38.022629
4827 22:16:38.025106 CH 1, Rank 0
4828 22:16:38.025600 SW Impedance : PASS
4829 22:16:38.028595 DUTY Scan : NO K
4830 22:16:38.032197 ZQ Calibration : PASS
4831 22:16:38.032655 Jitter Meter : NO K
4832 22:16:38.035611 CBT Training : PASS
4833 22:16:38.038401 Write leveling : PASS
4834 22:16:38.038821 RX DQS gating : PASS
4835 22:16:38.041703 RX DQ/DQS(RDDQC) : PASS
4836 22:16:38.044947 TX DQ/DQS : PASS
4837 22:16:38.045366 RX DATLAT : PASS
4838 22:16:38.048642 RX DQ/DQS(Engine): PASS
4839 22:16:38.051723 TX OE : NO K
4840 22:16:38.052413 All Pass.
4841 22:16:38.052840
4842 22:16:38.053253 CH 1, Rank 1
4843 22:16:38.055032 SW Impedance : PASS
4844 22:16:38.058215 DUTY Scan : NO K
4845 22:16:38.058727 ZQ Calibration : PASS
4846 22:16:38.062064 Jitter Meter : NO K
4847 22:16:38.064924 CBT Training : PASS
4848 22:16:38.065411 Write leveling : PASS
4849 22:16:38.068673 RX DQS gating : PASS
4850 22:16:38.071942 RX DQ/DQS(RDDQC) : PASS
4851 22:16:38.072448 TX DQ/DQS : PASS
4852 22:16:38.075063 RX DATLAT : PASS
4853 22:16:38.075541 RX DQ/DQS(Engine): PASS
4854 22:16:38.078198 TX OE : NO K
4855 22:16:38.078679 All Pass.
4856 22:16:38.079023
4857 22:16:38.081938 DramC Write-DBI off
4858 22:16:38.084878 PER_BANK_REFRESH: Hybrid Mode
4859 22:16:38.085305 TX_TRACKING: ON
4860 22:16:38.094522 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4861 22:16:38.098092 [FAST_K] Save calibration result to emmc
4862 22:16:38.101408 dramc_set_vcore_voltage set vcore to 662500
4863 22:16:38.104699 Read voltage for 933, 3
4864 22:16:38.105170 Vio18 = 0
4865 22:16:38.108342 Vcore = 662500
4866 22:16:38.108787 Vdram = 0
4867 22:16:38.109121 Vddq = 0
4868 22:16:38.109434 Vmddr = 0
4869 22:16:38.114513 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4870 22:16:38.121441 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4871 22:16:38.121863 MEM_TYPE=3, freq_sel=17
4872 22:16:38.124800 sv_algorithm_assistance_LP4_1600
4873 22:16:38.127987 ============ PULL DRAM RESETB DOWN ============
4874 22:16:38.134775 ========== PULL DRAM RESETB DOWN end =========
4875 22:16:38.137723 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4876 22:16:38.141249 ===================================
4877 22:16:38.144201 LPDDR4 DRAM CONFIGURATION
4878 22:16:38.147649 ===================================
4879 22:16:38.148101 EX_ROW_EN[0] = 0x0
4880 22:16:38.150816 EX_ROW_EN[1] = 0x0
4881 22:16:38.151233 LP4Y_EN = 0x0
4882 22:16:38.154392 WORK_FSP = 0x0
4883 22:16:38.154809 WL = 0x3
4884 22:16:38.157536 RL = 0x3
4885 22:16:38.157951 BL = 0x2
4886 22:16:38.160977 RPST = 0x0
4887 22:16:38.164982 RD_PRE = 0x0
4888 22:16:38.165399 WR_PRE = 0x1
4889 22:16:38.167731 WR_PST = 0x0
4890 22:16:38.168177 DBI_WR = 0x0
4891 22:16:38.171016 DBI_RD = 0x0
4892 22:16:38.171430 OTF = 0x1
4893 22:16:38.174313 ===================================
4894 22:16:38.177450 ===================================
4895 22:16:38.180621 ANA top config
4896 22:16:38.184031 ===================================
4897 22:16:38.184448 DLL_ASYNC_EN = 0
4898 22:16:38.187299 ALL_SLAVE_EN = 1
4899 22:16:38.190705 NEW_RANK_MODE = 1
4900 22:16:38.194234 DLL_IDLE_MODE = 1
4901 22:16:38.194683 LP45_APHY_COMB_EN = 1
4902 22:16:38.197169 TX_ODT_DIS = 1
4903 22:16:38.200576 NEW_8X_MODE = 1
4904 22:16:38.204194 ===================================
4905 22:16:38.207312 ===================================
4906 22:16:38.210753 data_rate = 1866
4907 22:16:38.213767 CKR = 1
4908 22:16:38.214183 DQ_P2S_RATIO = 8
4909 22:16:38.217768 ===================================
4910 22:16:38.220759 CA_P2S_RATIO = 8
4911 22:16:38.223914 DQ_CA_OPEN = 0
4912 22:16:38.227133 DQ_SEMI_OPEN = 0
4913 22:16:38.230516 CA_SEMI_OPEN = 0
4914 22:16:38.234353 CA_FULL_RATE = 0
4915 22:16:38.234768 DQ_CKDIV4_EN = 1
4916 22:16:38.237373 CA_CKDIV4_EN = 1
4917 22:16:38.240717 CA_PREDIV_EN = 0
4918 22:16:38.244032 PH8_DLY = 0
4919 22:16:38.247268 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4920 22:16:38.250499 DQ_AAMCK_DIV = 4
4921 22:16:38.250987 CA_AAMCK_DIV = 4
4922 22:16:38.253948 CA_ADMCK_DIV = 4
4923 22:16:38.257169 DQ_TRACK_CA_EN = 0
4924 22:16:38.260416 CA_PICK = 933
4925 22:16:38.263752 CA_MCKIO = 933
4926 22:16:38.267076 MCKIO_SEMI = 0
4927 22:16:38.270242 PLL_FREQ = 3732
4928 22:16:38.270658 DQ_UI_PI_RATIO = 32
4929 22:16:38.273701 CA_UI_PI_RATIO = 0
4930 22:16:38.277193 ===================================
4931 22:16:38.280591 ===================================
4932 22:16:38.283542 memory_type:LPDDR4
4933 22:16:38.287371 GP_NUM : 10
4934 22:16:38.287800 SRAM_EN : 1
4935 22:16:38.290674 MD32_EN : 0
4936 22:16:38.293840 ===================================
4937 22:16:38.296936 [ANA_INIT] >>>>>>>>>>>>>>
4938 22:16:38.297379 <<<<<< [CONFIGURE PHASE]: ANA_TX
4939 22:16:38.300236 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4940 22:16:38.303615 ===================================
4941 22:16:38.307224 data_rate = 1866,PCW = 0X8f00
4942 22:16:38.310287 ===================================
4943 22:16:38.313865 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4944 22:16:38.320668 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4945 22:16:38.326891 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4946 22:16:38.330605 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4947 22:16:38.333342 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4948 22:16:38.336633 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4949 22:16:38.340342 [ANA_INIT] flow start
4950 22:16:38.340784 [ANA_INIT] PLL >>>>>>>>
4951 22:16:38.343511 [ANA_INIT] PLL <<<<<<<<
4952 22:16:38.346929 [ANA_INIT] MIDPI >>>>>>>>
4953 22:16:38.349754 [ANA_INIT] MIDPI <<<<<<<<
4954 22:16:38.350200 [ANA_INIT] DLL >>>>>>>>
4955 22:16:38.353714 [ANA_INIT] flow end
4956 22:16:38.356569 ============ LP4 DIFF to SE enter ============
4957 22:16:38.359979 ============ LP4 DIFF to SE exit ============
4958 22:16:38.363264 [ANA_INIT] <<<<<<<<<<<<<
4959 22:16:38.366866 [Flow] Enable top DCM control >>>>>
4960 22:16:38.369781 [Flow] Enable top DCM control <<<<<
4961 22:16:38.373263 Enable DLL master slave shuffle
4962 22:16:38.376845 ==============================================================
4963 22:16:38.379865 Gating Mode config
4964 22:16:38.386779 ==============================================================
4965 22:16:38.387210 Config description:
4966 22:16:38.396748 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4967 22:16:38.403370 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4968 22:16:38.409936 SELPH_MODE 0: By rank 1: By Phase
4969 22:16:38.413322 ==============================================================
4970 22:16:38.416525 GAT_TRACK_EN = 1
4971 22:16:38.419687 RX_GATING_MODE = 2
4972 22:16:38.422894 RX_GATING_TRACK_MODE = 2
4973 22:16:38.426238 SELPH_MODE = 1
4974 22:16:38.429657 PICG_EARLY_EN = 1
4975 22:16:38.432892 VALID_LAT_VALUE = 1
4976 22:16:38.436833 ==============================================================
4977 22:16:38.440076 Enter into Gating configuration >>>>
4978 22:16:38.443308 Exit from Gating configuration <<<<
4979 22:16:38.446047 Enter into DVFS_PRE_config >>>>>
4980 22:16:38.459750 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4981 22:16:38.462817 Exit from DVFS_PRE_config <<<<<
4982 22:16:38.466651 Enter into PICG configuration >>>>
4983 22:16:38.467111 Exit from PICG configuration <<<<
4984 22:16:38.469404 [RX_INPUT] configuration >>>>>
4985 22:16:38.472822 [RX_INPUT] configuration <<<<<
4986 22:16:38.479278 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4987 22:16:38.482867 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4988 22:16:38.489209 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4989 22:16:38.495901 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4990 22:16:38.502479 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4991 22:16:38.509152 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4992 22:16:38.512720 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4993 22:16:38.515641 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4994 22:16:38.518678 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4995 22:16:38.525311 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4996 22:16:38.528702 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4997 22:16:38.532207 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4998 22:16:38.535331 ===================================
4999 22:16:38.539435 LPDDR4 DRAM CONFIGURATION
5000 22:16:38.542394 ===================================
5001 22:16:38.545799 EX_ROW_EN[0] = 0x0
5002 22:16:38.545920 EX_ROW_EN[1] = 0x0
5003 22:16:38.548517 LP4Y_EN = 0x0
5004 22:16:38.548612 WORK_FSP = 0x0
5005 22:16:38.552227 WL = 0x3
5006 22:16:38.552309 RL = 0x3
5007 22:16:38.555245 BL = 0x2
5008 22:16:38.555326 RPST = 0x0
5009 22:16:38.559371 RD_PRE = 0x0
5010 22:16:38.559452 WR_PRE = 0x1
5011 22:16:38.562245 WR_PST = 0x0
5012 22:16:38.562331 DBI_WR = 0x0
5013 22:16:38.565494 DBI_RD = 0x0
5014 22:16:38.565587 OTF = 0x1
5015 22:16:38.569113 ===================================
5016 22:16:38.575258 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5017 22:16:38.578785 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5018 22:16:38.581839 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5019 22:16:38.585820 ===================================
5020 22:16:38.589121 LPDDR4 DRAM CONFIGURATION
5021 22:16:38.592023 ===================================
5022 22:16:38.595452 EX_ROW_EN[0] = 0x10
5023 22:16:38.595623 EX_ROW_EN[1] = 0x0
5024 22:16:38.598848 LP4Y_EN = 0x0
5025 22:16:38.599019 WORK_FSP = 0x0
5026 22:16:38.601875 WL = 0x3
5027 22:16:38.602074 RL = 0x3
5028 22:16:38.605229 BL = 0x2
5029 22:16:38.605467 RPST = 0x0
5030 22:16:38.608551 RD_PRE = 0x0
5031 22:16:38.608790 WR_PRE = 0x1
5032 22:16:38.611790 WR_PST = 0x0
5033 22:16:38.612113 DBI_WR = 0x0
5034 22:16:38.615841 DBI_RD = 0x0
5035 22:16:38.616246 OTF = 0x1
5036 22:16:38.618534 ===================================
5037 22:16:38.625563 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5038 22:16:38.630244 nWR fixed to 30
5039 22:16:38.633763 [ModeRegInit_LP4] CH0 RK0
5040 22:16:38.634178 [ModeRegInit_LP4] CH0 RK1
5041 22:16:38.636905 [ModeRegInit_LP4] CH1 RK0
5042 22:16:38.639890 [ModeRegInit_LP4] CH1 RK1
5043 22:16:38.640336 match AC timing 9
5044 22:16:38.646517 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5045 22:16:38.649762 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5046 22:16:38.652920 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5047 22:16:38.660034 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5048 22:16:38.663168 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5049 22:16:38.663586 ==
5050 22:16:38.666970 Dram Type= 6, Freq= 0, CH_0, rank 0
5051 22:16:38.670047 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5052 22:16:38.670465 ==
5053 22:16:38.676636 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5054 22:16:38.683271 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5055 22:16:38.686401 [CA 0] Center 38 (8~69) winsize 62
5056 22:16:38.689795 [CA 1] Center 37 (7~68) winsize 62
5057 22:16:38.693188 [CA 2] Center 35 (5~66) winsize 62
5058 22:16:38.697025 [CA 3] Center 35 (4~66) winsize 63
5059 22:16:38.699615 [CA 4] Center 34 (4~64) winsize 61
5060 22:16:38.703260 [CA 5] Center 34 (4~64) winsize 61
5061 22:16:38.703684
5062 22:16:38.706845 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5063 22:16:38.707285
5064 22:16:38.709637 [CATrainingPosCal] consider 1 rank data
5065 22:16:38.713022 u2DelayCellTimex100 = 270/100 ps
5066 22:16:38.716406 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5067 22:16:38.720304 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5068 22:16:38.723132 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5069 22:16:38.726281 CA3 delay=35 (4~66),Diff = 1 PI (6 cell)
5070 22:16:38.729334 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5071 22:16:38.732678 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5072 22:16:38.736692
5073 22:16:38.739400 CA PerBit enable=1, Macro0, CA PI delay=34
5074 22:16:38.739816
5075 22:16:38.743235 [CBTSetCACLKResult] CA Dly = 34
5076 22:16:38.743650 CS Dly: 6 (0~37)
5077 22:16:38.744020 ==
5078 22:16:38.746182 Dram Type= 6, Freq= 0, CH_0, rank 1
5079 22:16:38.749502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5080 22:16:38.749921 ==
5081 22:16:38.756106 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5082 22:16:38.763299 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5083 22:16:38.766212 [CA 0] Center 38 (8~69) winsize 62
5084 22:16:38.769511 [CA 1] Center 38 (8~69) winsize 62
5085 22:16:38.772606 [CA 2] Center 35 (5~66) winsize 62
5086 22:16:38.775892 [CA 3] Center 35 (5~65) winsize 61
5087 22:16:38.779278 [CA 4] Center 34 (4~65) winsize 62
5088 22:16:38.782624 [CA 5] Center 33 (3~64) winsize 62
5089 22:16:38.783050
5090 22:16:38.785889 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5091 22:16:38.786308
5092 22:16:38.789148 [CATrainingPosCal] consider 2 rank data
5093 22:16:38.792413 u2DelayCellTimex100 = 270/100 ps
5094 22:16:38.796397 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5095 22:16:38.799691 CA1 delay=38 (8~68),Diff = 4 PI (24 cell)
5096 22:16:38.802671 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5097 22:16:38.806119 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5098 22:16:38.809239 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5099 22:16:38.816006 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5100 22:16:38.816481
5101 22:16:38.819257 CA PerBit enable=1, Macro0, CA PI delay=34
5102 22:16:38.819673
5103 22:16:38.822549 [CBTSetCACLKResult] CA Dly = 34
5104 22:16:38.822963 CS Dly: 7 (0~39)
5105 22:16:38.823292
5106 22:16:38.826050 ----->DramcWriteLeveling(PI) begin...
5107 22:16:38.826574 ==
5108 22:16:38.829404 Dram Type= 6, Freq= 0, CH_0, rank 0
5109 22:16:38.836365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5110 22:16:38.836808 ==
5111 22:16:38.837181 Write leveling (Byte 0): 29 => 29
5112 22:16:38.839128 Write leveling (Byte 1): 27 => 27
5113 22:16:38.842565 DramcWriteLeveling(PI) end<-----
5114 22:16:38.843130
5115 22:16:38.843555 ==
5116 22:16:38.845761 Dram Type= 6, Freq= 0, CH_0, rank 0
5117 22:16:38.852598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5118 22:16:38.853039 ==
5119 22:16:38.855694 [Gating] SW mode calibration
5120 22:16:38.863140 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5121 22:16:38.866090 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5122 22:16:38.872971 0 14 0 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (0 0)
5123 22:16:38.875534 0 14 4 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
5124 22:16:38.879652 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5125 22:16:38.885719 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5126 22:16:38.888854 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5127 22:16:38.892237 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5128 22:16:38.895540 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5129 22:16:38.902313 0 14 28 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 1)
5130 22:16:38.905610 0 15 0 | B1->B0 | 3030 2727 | 0 0 | (0 1) (0 0)
5131 22:16:38.909070 0 15 4 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
5132 22:16:38.915679 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5133 22:16:38.918856 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5134 22:16:38.922378 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5135 22:16:38.928769 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5136 22:16:38.932060 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5137 22:16:38.936026 0 15 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5138 22:16:38.942501 1 0 0 | B1->B0 | 3434 4242 | 0 0 | (0 0) (0 0)
5139 22:16:38.945640 1 0 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5140 22:16:38.948932 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5141 22:16:38.955257 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5142 22:16:38.959085 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5143 22:16:38.962613 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5144 22:16:38.968969 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5145 22:16:38.972258 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5146 22:16:38.975192 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5147 22:16:38.981862 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5148 22:16:38.984760 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5149 22:16:38.988476 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5150 22:16:38.996028 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5151 22:16:38.998217 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5152 22:16:39.001423 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5153 22:16:39.008289 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5154 22:16:39.012048 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5155 22:16:39.015340 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5156 22:16:39.021198 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5157 22:16:39.024478 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5158 22:16:39.028229 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5159 22:16:39.034812 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5160 22:16:39.038035 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5161 22:16:39.041509 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5162 22:16:39.045307 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5163 22:16:39.051187 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5164 22:16:39.054783 Total UI for P1: 0, mck2ui 16
5165 22:16:39.057963 best dqsien dly found for B0: ( 1, 3, 0)
5166 22:16:39.061452 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5167 22:16:39.064460 Total UI for P1: 0, mck2ui 16
5168 22:16:39.067894 best dqsien dly found for B1: ( 1, 3, 2)
5169 22:16:39.071260 best DQS0 dly(MCK, UI, PI) = (1, 3, 0)
5170 22:16:39.074842 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5171 22:16:39.074918
5172 22:16:39.077854 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 0)
5173 22:16:39.081331 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5174 22:16:39.084709 [Gating] SW calibration Done
5175 22:16:39.084781 ==
5176 22:16:39.088360 Dram Type= 6, Freq= 0, CH_0, rank 0
5177 22:16:39.091061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5178 22:16:39.094532 ==
5179 22:16:39.094604 RX Vref Scan: 0
5180 22:16:39.094665
5181 22:16:39.097990 RX Vref 0 -> 0, step: 1
5182 22:16:39.098059
5183 22:16:39.101194 RX Delay -80 -> 252, step: 8
5184 22:16:39.104408 iDelay=200, Bit 0, Center 99 (8 ~ 191) 184
5185 22:16:39.107925 iDelay=200, Bit 1, Center 99 (0 ~ 199) 200
5186 22:16:39.111039 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5187 22:16:39.114514 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5188 22:16:39.118102 iDelay=200, Bit 4, Center 103 (8 ~ 199) 192
5189 22:16:39.124882 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5190 22:16:39.127936 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5191 22:16:39.131303 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5192 22:16:39.134689 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5193 22:16:39.137936 iDelay=200, Bit 9, Center 75 (-16 ~ 167) 184
5194 22:16:39.141105 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5195 22:16:39.147512 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5196 22:16:39.150973 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5197 22:16:39.154602 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5198 22:16:39.157489 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5199 22:16:39.160973 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5200 22:16:39.161044 ==
5201 22:16:39.164457 Dram Type= 6, Freq= 0, CH_0, rank 0
5202 22:16:39.170987 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5203 22:16:39.171061 ==
5204 22:16:39.171124 DQS Delay:
5205 22:16:39.174379 DQS0 = 0, DQS1 = 0
5206 22:16:39.174483 DQM Delay:
5207 22:16:39.174572 DQM0 = 98, DQM1 = 88
5208 22:16:39.177770 DQ Delay:
5209 22:16:39.181022 DQ0 =99, DQ1 =99, DQ2 =95, DQ3 =95
5210 22:16:39.184496 DQ4 =103, DQ5 =87, DQ6 =103, DQ7 =103
5211 22:16:39.187776 DQ8 =83, DQ9 =75, DQ10 =87, DQ11 =83
5212 22:16:39.191012 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5213 22:16:39.191085
5214 22:16:39.191146
5215 22:16:39.191204 ==
5216 22:16:39.194018 Dram Type= 6, Freq= 0, CH_0, rank 0
5217 22:16:39.197336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5218 22:16:39.197408 ==
5219 22:16:39.197469
5220 22:16:39.197539
5221 22:16:39.200937 TX Vref Scan disable
5222 22:16:39.204124 == TX Byte 0 ==
5223 22:16:39.207400 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5224 22:16:39.210951 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5225 22:16:39.214072 == TX Byte 1 ==
5226 22:16:39.217098 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5227 22:16:39.220437 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5228 22:16:39.220511 ==
5229 22:16:39.223932 Dram Type= 6, Freq= 0, CH_0, rank 0
5230 22:16:39.227260 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5231 22:16:39.230730 ==
5232 22:16:39.230811
5233 22:16:39.230876
5234 22:16:39.230936 TX Vref Scan disable
5235 22:16:39.233871 == TX Byte 0 ==
5236 22:16:39.237647 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5237 22:16:39.244176 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5238 22:16:39.244259 == TX Byte 1 ==
5239 22:16:39.247631 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5240 22:16:39.253773 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5241 22:16:39.253855
5242 22:16:39.253920 [DATLAT]
5243 22:16:39.253982 Freq=933, CH0 RK0
5244 22:16:39.254042
5245 22:16:39.257426 DATLAT Default: 0xd
5246 22:16:39.257508 0, 0xFFFF, sum = 0
5247 22:16:39.260650 1, 0xFFFF, sum = 0
5248 22:16:39.260732 2, 0xFFFF, sum = 0
5249 22:16:39.263886 3, 0xFFFF, sum = 0
5250 22:16:39.267191 4, 0xFFFF, sum = 0
5251 22:16:39.267275 5, 0xFFFF, sum = 0
5252 22:16:39.270833 6, 0xFFFF, sum = 0
5253 22:16:39.270916 7, 0xFFFF, sum = 0
5254 22:16:39.273596 8, 0xFFFF, sum = 0
5255 22:16:39.273680 9, 0xFFFF, sum = 0
5256 22:16:39.277100 10, 0x0, sum = 1
5257 22:16:39.277182 11, 0x0, sum = 2
5258 22:16:39.280100 12, 0x0, sum = 3
5259 22:16:39.280183 13, 0x0, sum = 4
5260 22:16:39.280249 best_step = 11
5261 22:16:39.280309
5262 22:16:39.284121 ==
5263 22:16:39.287168 Dram Type= 6, Freq= 0, CH_0, rank 0
5264 22:16:39.290524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5265 22:16:39.290606 ==
5266 22:16:39.290671 RX Vref Scan: 1
5267 22:16:39.290730
5268 22:16:39.293804 RX Vref 0 -> 0, step: 1
5269 22:16:39.293886
5270 22:16:39.296724 RX Delay -61 -> 252, step: 4
5271 22:16:39.296806
5272 22:16:39.300218 Set Vref, RX VrefLevel [Byte0]: 53
5273 22:16:39.303718 [Byte1]: 51
5274 22:16:39.303799
5275 22:16:39.306689 Final RX Vref Byte 0 = 53 to rank0
5276 22:16:39.310359 Final RX Vref Byte 1 = 51 to rank0
5277 22:16:39.313488 Final RX Vref Byte 0 = 53 to rank1
5278 22:16:39.316951 Final RX Vref Byte 1 = 51 to rank1==
5279 22:16:39.319969 Dram Type= 6, Freq= 0, CH_0, rank 0
5280 22:16:39.323499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5281 22:16:39.326455 ==
5282 22:16:39.326540 DQS Delay:
5283 22:16:39.326607 DQS0 = 0, DQS1 = 0
5284 22:16:39.330006 DQM Delay:
5285 22:16:39.330086 DQM0 = 96, DQM1 = 88
5286 22:16:39.333047 DQ Delay:
5287 22:16:39.336349 DQ0 =98, DQ1 =98, DQ2 =94, DQ3 =94
5288 22:16:39.340171 DQ4 =98, DQ5 =84, DQ6 =104, DQ7 =102
5289 22:16:39.340250 DQ8 =78, DQ9 =78, DQ10 =88, DQ11 =80
5290 22:16:39.346330 DQ12 =96, DQ13 =90, DQ14 =98, DQ15 =96
5291 22:16:39.346407
5292 22:16:39.346470
5293 22:16:39.353361 [DQSOSCAuto] RK0, (LSB)MR18= 0x14ff, (MSB)MR19= 0x504, tDQSOscB0 = 422 ps tDQSOscB1 = 415 ps
5294 22:16:39.356712 CH0 RK0: MR19=504, MR18=14FF
5295 22:16:39.363092 CH0_RK0: MR19=0x504, MR18=0x14FF, DQSOSC=415, MR23=63, INC=62, DEC=41
5296 22:16:39.363167
5297 22:16:39.367306 ----->DramcWriteLeveling(PI) begin...
5298 22:16:39.367382 ==
5299 22:16:39.369692 Dram Type= 6, Freq= 0, CH_0, rank 1
5300 22:16:39.372894 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5301 22:16:39.372964 ==
5302 22:16:39.376665 Write leveling (Byte 0): 30 => 30
5303 22:16:39.379847 Write leveling (Byte 1): 29 => 29
5304 22:16:39.383002 DramcWriteLeveling(PI) end<-----
5305 22:16:39.383075
5306 22:16:39.383137 ==
5307 22:16:39.386450 Dram Type= 6, Freq= 0, CH_0, rank 1
5308 22:16:39.389986 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5309 22:16:39.390057 ==
5310 22:16:39.393041 [Gating] SW mode calibration
5311 22:16:39.399649 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5312 22:16:39.406344 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5313 22:16:39.409388 0 14 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
5314 22:16:39.412773 0 14 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5315 22:16:39.419390 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5316 22:16:39.422702 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5317 22:16:39.426220 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5318 22:16:39.433078 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5319 22:16:39.436194 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5320 22:16:39.439415 0 14 28 | B1->B0 | 3131 2c2c | 0 0 | (0 0) (0 0)
5321 22:16:39.446425 0 15 0 | B1->B0 | 3030 2323 | 0 0 | (1 0) (0 0)
5322 22:16:39.449755 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5323 22:16:39.452818 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5324 22:16:39.459227 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5325 22:16:39.462647 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5326 22:16:39.466040 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5327 22:16:39.473449 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5328 22:16:39.476083 0 15 28 | B1->B0 | 2424 3030 | 0 0 | (0 0) (0 0)
5329 22:16:39.479979 1 0 0 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
5330 22:16:39.486274 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5331 22:16:39.490062 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5332 22:16:39.492815 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5333 22:16:39.499670 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5334 22:16:39.502826 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5335 22:16:39.506189 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5336 22:16:39.512618 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5337 22:16:39.516302 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5338 22:16:39.519237 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5339 22:16:39.526311 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5340 22:16:39.529057 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5341 22:16:39.532677 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5342 22:16:39.535853 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5343 22:16:39.542742 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5344 22:16:39.546052 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5345 22:16:39.549302 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5346 22:16:39.555834 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5347 22:16:39.558740 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5348 22:16:39.562275 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5349 22:16:39.569009 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5350 22:16:39.572522 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5351 22:16:39.575881 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5352 22:16:39.582246 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5353 22:16:39.585649 Total UI for P1: 0, mck2ui 16
5354 22:16:39.589362 best dqsien dly found for B0: ( 1, 2, 24)
5355 22:16:39.592808 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5356 22:16:39.595492 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5357 22:16:39.602116 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5358 22:16:39.602203 Total UI for P1: 0, mck2ui 16
5359 22:16:39.608939 best dqsien dly found for B1: ( 1, 3, 0)
5360 22:16:39.612883 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5361 22:16:39.615333 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5362 22:16:39.615415
5363 22:16:39.618974 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5364 22:16:39.622369 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5365 22:16:39.625829 [Gating] SW calibration Done
5366 22:16:39.625911 ==
5367 22:16:39.628834 Dram Type= 6, Freq= 0, CH_0, rank 1
5368 22:16:39.631883 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5369 22:16:39.631992 ==
5370 22:16:39.635482 RX Vref Scan: 0
5371 22:16:39.635563
5372 22:16:39.635628 RX Vref 0 -> 0, step: 1
5373 22:16:39.635687
5374 22:16:39.638555 RX Delay -80 -> 252, step: 8
5375 22:16:39.642438 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5376 22:16:39.648504 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5377 22:16:39.651711 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5378 22:16:39.655360 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5379 22:16:39.659513 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5380 22:16:39.662011 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
5381 22:16:39.665588 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5382 22:16:39.672171 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5383 22:16:39.675247 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5384 22:16:39.679136 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5385 22:16:39.682485 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5386 22:16:39.685063 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5387 22:16:39.691647 iDelay=208, Bit 12, Center 87 (-8 ~ 183) 192
5388 22:16:39.694993 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5389 22:16:39.698859 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5390 22:16:39.701507 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5391 22:16:39.701589 ==
5392 22:16:39.705217 Dram Type= 6, Freq= 0, CH_0, rank 1
5393 22:16:39.708467 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5394 22:16:39.711809 ==
5395 22:16:39.711891 DQS Delay:
5396 22:16:39.711976 DQS0 = 0, DQS1 = 0
5397 22:16:39.714751 DQM Delay:
5398 22:16:39.714832 DQM0 = 95, DQM1 = 86
5399 22:16:39.718310 DQ Delay:
5400 22:16:39.718391 DQ0 =95, DQ1 =99, DQ2 =91, DQ3 =91
5401 22:16:39.721315 DQ4 =95, DQ5 =83, DQ6 =107, DQ7 =103
5402 22:16:39.725151 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =79
5403 22:16:39.728108 DQ12 =87, DQ13 =91, DQ14 =95, DQ15 =95
5404 22:16:39.731725
5405 22:16:39.731807
5406 22:16:39.731871 ==
5407 22:16:39.735139 Dram Type= 6, Freq= 0, CH_0, rank 1
5408 22:16:39.738667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5409 22:16:39.738750 ==
5410 22:16:39.738815
5411 22:16:39.738875
5412 22:16:39.741413 TX Vref Scan disable
5413 22:16:39.741495 == TX Byte 0 ==
5414 22:16:39.748214 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5415 22:16:39.751670 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5416 22:16:39.751752 == TX Byte 1 ==
5417 22:16:39.757954 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5418 22:16:39.761672 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5419 22:16:39.761754 ==
5420 22:16:39.764840 Dram Type= 6, Freq= 0, CH_0, rank 1
5421 22:16:39.768397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5422 22:16:39.768480 ==
5423 22:16:39.768545
5424 22:16:39.768606
5425 22:16:39.771670 TX Vref Scan disable
5426 22:16:39.774557 == TX Byte 0 ==
5427 22:16:39.777853 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5428 22:16:39.781126 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5429 22:16:39.784578 == TX Byte 1 ==
5430 22:16:39.787888 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5431 22:16:39.791577 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5432 22:16:39.791659
5433 22:16:39.794382 [DATLAT]
5434 22:16:39.794464 Freq=933, CH0 RK1
5435 22:16:39.794530
5436 22:16:39.797822 DATLAT Default: 0xb
5437 22:16:39.797904 0, 0xFFFF, sum = 0
5438 22:16:39.801413 1, 0xFFFF, sum = 0
5439 22:16:39.801495 2, 0xFFFF, sum = 0
5440 22:16:39.804480 3, 0xFFFF, sum = 0
5441 22:16:39.804563 4, 0xFFFF, sum = 0
5442 22:16:39.808107 5, 0xFFFF, sum = 0
5443 22:16:39.808189 6, 0xFFFF, sum = 0
5444 22:16:39.811204 7, 0xFFFF, sum = 0
5445 22:16:39.811286 8, 0xFFFF, sum = 0
5446 22:16:39.814387 9, 0xFFFF, sum = 0
5447 22:16:39.814471 10, 0x0, sum = 1
5448 22:16:39.817639 11, 0x0, sum = 2
5449 22:16:39.817750 12, 0x0, sum = 3
5450 22:16:39.821077 13, 0x0, sum = 4
5451 22:16:39.821160 best_step = 11
5452 22:16:39.821225
5453 22:16:39.821285 ==
5454 22:16:39.824408 Dram Type= 6, Freq= 0, CH_0, rank 1
5455 22:16:39.830849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5456 22:16:39.830959 ==
5457 22:16:39.831041 RX Vref Scan: 0
5458 22:16:39.831101
5459 22:16:39.834572 RX Vref 0 -> 0, step: 1
5460 22:16:39.834654
5461 22:16:39.837704 RX Delay -61 -> 252, step: 4
5462 22:16:39.840917 iDelay=199, Bit 0, Center 94 (-1 ~ 190) 192
5463 22:16:39.844510 iDelay=199, Bit 1, Center 96 (3 ~ 190) 188
5464 22:16:39.850786 iDelay=199, Bit 2, Center 92 (-1 ~ 186) 188
5465 22:16:39.854054 iDelay=199, Bit 3, Center 94 (-1 ~ 190) 192
5466 22:16:39.857979 iDelay=199, Bit 4, Center 94 (3 ~ 186) 184
5467 22:16:39.860728 iDelay=199, Bit 5, Center 84 (-9 ~ 178) 188
5468 22:16:39.863848 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5469 22:16:39.870952 iDelay=199, Bit 7, Center 102 (11 ~ 194) 184
5470 22:16:39.874547 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5471 22:16:39.878027 iDelay=199, Bit 9, Center 80 (-9 ~ 170) 180
5472 22:16:39.880947 iDelay=199, Bit 10, Center 88 (-1 ~ 178) 180
5473 22:16:39.884248 iDelay=199, Bit 11, Center 78 (-9 ~ 166) 176
5474 22:16:39.887338 iDelay=199, Bit 12, Center 92 (3 ~ 182) 180
5475 22:16:39.894327 iDelay=199, Bit 13, Center 92 (3 ~ 182) 180
5476 22:16:39.897357 iDelay=199, Bit 14, Center 96 (7 ~ 186) 180
5477 22:16:39.900641 iDelay=199, Bit 15, Center 94 (3 ~ 186) 184
5478 22:16:39.900818 ==
5479 22:16:39.904621 Dram Type= 6, Freq= 0, CH_0, rank 1
5480 22:16:39.907669 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5481 22:16:39.907925 ==
5482 22:16:39.910654 DQS Delay:
5483 22:16:39.910925 DQS0 = 0, DQS1 = 0
5484 22:16:39.911164 DQM Delay:
5485 22:16:39.914556 DQM0 = 95, DQM1 = 87
5486 22:16:39.914880 DQ Delay:
5487 22:16:39.917651 DQ0 =94, DQ1 =96, DQ2 =92, DQ3 =94
5488 22:16:39.920803 DQ4 =94, DQ5 =84, DQ6 =104, DQ7 =102
5489 22:16:39.924245 DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =78
5490 22:16:39.927797 DQ12 =92, DQ13 =92, DQ14 =96, DQ15 =94
5491 22:16:39.928282
5492 22:16:39.928672
5493 22:16:39.937446 [DQSOSCAuto] RK1, (LSB)MR18= 0x1603, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 414 ps
5494 22:16:39.941141 CH0 RK1: MR19=505, MR18=1603
5495 22:16:39.943855 CH0_RK1: MR19=0x505, MR18=0x1603, DQSOSC=414, MR23=63, INC=63, DEC=42
5496 22:16:39.947443 [RxdqsGatingPostProcess] freq 933
5497 22:16:39.954214 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5498 22:16:39.957718 best DQS0 dly(2T, 0.5T) = (0, 11)
5499 22:16:39.960653 best DQS1 dly(2T, 0.5T) = (0, 11)
5500 22:16:39.964026 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
5501 22:16:39.967666 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5502 22:16:39.971248 best DQS0 dly(2T, 0.5T) = (0, 10)
5503 22:16:39.973820 best DQS1 dly(2T, 0.5T) = (0, 11)
5504 22:16:39.977140 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5505 22:16:39.980527 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5506 22:16:39.980905 Pre-setting of DQS Precalculation
5507 22:16:39.987187 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5508 22:16:39.987609 ==
5509 22:16:39.990564 Dram Type= 6, Freq= 0, CH_1, rank 0
5510 22:16:39.994061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5511 22:16:39.994488 ==
5512 22:16:40.000860 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5513 22:16:40.007360 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5514 22:16:40.010364 [CA 0] Center 36 (6~67) winsize 62
5515 22:16:40.014054 [CA 1] Center 36 (6~67) winsize 62
5516 22:16:40.017230 [CA 2] Center 34 (4~64) winsize 61
5517 22:16:40.020705 [CA 3] Center 33 (3~64) winsize 62
5518 22:16:40.023862 [CA 4] Center 34 (3~65) winsize 63
5519 22:16:40.027059 [CA 5] Center 33 (3~63) winsize 61
5520 22:16:40.027427
5521 22:16:40.030717 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5522 22:16:40.031083
5523 22:16:40.033882 [CATrainingPosCal] consider 1 rank data
5524 22:16:40.037271 u2DelayCellTimex100 = 270/100 ps
5525 22:16:40.040236 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5526 22:16:40.043524 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5527 22:16:40.047462 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5528 22:16:40.050179 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5529 22:16:40.053624 CA4 delay=34 (3~65),Diff = 1 PI (6 cell)
5530 22:16:40.057094 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5531 22:16:40.060650
5532 22:16:40.063747 CA PerBit enable=1, Macro0, CA PI delay=33
5533 22:16:40.064163
5534 22:16:40.067127 [CBTSetCACLKResult] CA Dly = 33
5535 22:16:40.067491 CS Dly: 4 (0~35)
5536 22:16:40.067827 ==
5537 22:16:40.070404 Dram Type= 6, Freq= 0, CH_1, rank 1
5538 22:16:40.073645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5539 22:16:40.074024 ==
5540 22:16:40.080139 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5541 22:16:40.086757 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5542 22:16:40.090163 [CA 0] Center 36 (6~67) winsize 62
5543 22:16:40.093761 [CA 1] Center 36 (6~67) winsize 62
5544 22:16:40.096808 [CA 2] Center 33 (3~64) winsize 62
5545 22:16:40.100200 [CA 3] Center 33 (3~64) winsize 62
5546 22:16:40.103441 [CA 4] Center 33 (3~64) winsize 62
5547 22:16:40.106669 [CA 5] Center 33 (3~63) winsize 61
5548 22:16:40.107059
5549 22:16:40.110033 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5550 22:16:40.110482
5551 22:16:40.113453 [CATrainingPosCal] consider 2 rank data
5552 22:16:40.116745 u2DelayCellTimex100 = 270/100 ps
5553 22:16:40.120029 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5554 22:16:40.124028 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5555 22:16:40.127174 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5556 22:16:40.130157 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5557 22:16:40.133494 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5558 22:16:40.140378 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5559 22:16:40.140802
5560 22:16:40.143188 CA PerBit enable=1, Macro0, CA PI delay=33
5561 22:16:40.143609
5562 22:16:40.146565 [CBTSetCACLKResult] CA Dly = 33
5563 22:16:40.146984 CS Dly: 5 (0~37)
5564 22:16:40.147316
5565 22:16:40.149919 ----->DramcWriteLeveling(PI) begin...
5566 22:16:40.150348 ==
5567 22:16:40.153065 Dram Type= 6, Freq= 0, CH_1, rank 0
5568 22:16:40.156420 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5569 22:16:40.159639 ==
5570 22:16:40.163276 Write leveling (Byte 0): 27 => 27
5571 22:16:40.163699 Write leveling (Byte 1): 31 => 31
5572 22:16:40.166903 DramcWriteLeveling(PI) end<-----
5573 22:16:40.167322
5574 22:16:40.167675 ==
5575 22:16:40.169873 Dram Type= 6, Freq= 0, CH_1, rank 0
5576 22:16:40.176615 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5577 22:16:40.177039 ==
5578 22:16:40.179613 [Gating] SW mode calibration
5579 22:16:40.186353 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5580 22:16:40.189737 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5581 22:16:40.196108 0 14 0 | B1->B0 | 2f2f 3333 | 1 0 | (1 1) (0 0)
5582 22:16:40.199583 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5583 22:16:40.203256 0 14 8 | B1->B0 | 3535 3434 | 1 1 | (0 0) (1 1)
5584 22:16:40.209616 0 14 12 | B1->B0 | 3534 3434 | 1 1 | (0 0) (1 1)
5585 22:16:40.213172 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5586 22:16:40.216618 0 14 20 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5587 22:16:40.222596 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5588 22:16:40.226715 0 14 28 | B1->B0 | 2e2e 3030 | 0 0 | (1 0) (1 0)
5589 22:16:40.229612 0 15 0 | B1->B0 | 2727 2525 | 0 0 | (1 0) (1 0)
5590 22:16:40.236087 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5591 22:16:40.239204 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5592 22:16:40.243079 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5593 22:16:40.249332 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5594 22:16:40.252580 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5595 22:16:40.255880 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5596 22:16:40.259321 0 15 28 | B1->B0 | 3a3a 3131 | 0 0 | (0 0) (0 0)
5597 22:16:40.266130 1 0 0 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5598 22:16:40.269183 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5599 22:16:40.272462 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5600 22:16:40.279491 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5601 22:16:40.282637 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5602 22:16:40.285817 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5603 22:16:40.292448 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5604 22:16:40.296145 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5605 22:16:40.299031 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5606 22:16:40.305745 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5607 22:16:40.309545 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5608 22:16:40.312199 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5609 22:16:40.318840 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5610 22:16:40.322064 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5611 22:16:40.325594 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5612 22:16:40.332611 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5613 22:16:40.335884 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5614 22:16:40.339007 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5615 22:16:40.345465 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5616 22:16:40.348647 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5617 22:16:40.351883 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5618 22:16:40.358649 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5619 22:16:40.362145 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5620 22:16:40.364922 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5621 22:16:40.371909 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5622 22:16:40.372012 Total UI for P1: 0, mck2ui 16
5623 22:16:40.377876 best dqsien dly found for B0: ( 1, 2, 28)
5624 22:16:40.377959 Total UI for P1: 0, mck2ui 16
5625 22:16:40.384760 best dqsien dly found for B1: ( 1, 2, 28)
5626 22:16:40.387860 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5627 22:16:40.391439 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5628 22:16:40.391521
5629 22:16:40.394374 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5630 22:16:40.397988 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5631 22:16:40.401476 [Gating] SW calibration Done
5632 22:16:40.401557 ==
5633 22:16:40.404924 Dram Type= 6, Freq= 0, CH_1, rank 0
5634 22:16:40.407942 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5635 22:16:40.408044 ==
5636 22:16:40.411121 RX Vref Scan: 0
5637 22:16:40.411205
5638 22:16:40.411275 RX Vref 0 -> 0, step: 1
5639 22:16:40.411337
5640 22:16:40.414279 RX Delay -80 -> 252, step: 8
5641 22:16:40.418276 iDelay=208, Bit 0, Center 99 (8 ~ 191) 184
5642 22:16:40.424532 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5643 22:16:40.427917 iDelay=208, Bit 2, Center 83 (-8 ~ 175) 184
5644 22:16:40.430725 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5645 22:16:40.434287 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5646 22:16:40.437754 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5647 22:16:40.440794 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5648 22:16:40.447929 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5649 22:16:40.451003 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5650 22:16:40.454815 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5651 22:16:40.457871 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5652 22:16:40.461772 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5653 22:16:40.467457 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5654 22:16:40.471117 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5655 22:16:40.474581 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5656 22:16:40.477755 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5657 22:16:40.477837 ==
5658 22:16:40.480618 Dram Type= 6, Freq= 0, CH_1, rank 0
5659 22:16:40.484473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5660 22:16:40.484555 ==
5661 22:16:40.487964 DQS Delay:
5662 22:16:40.488059 DQS0 = 0, DQS1 = 0
5663 22:16:40.490567 DQM Delay:
5664 22:16:40.490648 DQM0 = 97, DQM1 = 89
5665 22:16:40.490713 DQ Delay:
5666 22:16:40.493955 DQ0 =99, DQ1 =95, DQ2 =83, DQ3 =95
5667 22:16:40.497694 DQ4 =95, DQ5 =107, DQ6 =107, DQ7 =95
5668 22:16:40.500732 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5669 22:16:40.504167 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5670 22:16:40.504249
5671 22:16:40.504314
5672 22:16:40.507219 ==
5673 22:16:40.510468 Dram Type= 6, Freq= 0, CH_1, rank 0
5674 22:16:40.514313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5675 22:16:40.514395 ==
5676 22:16:40.514460
5677 22:16:40.514519
5678 22:16:40.517461 TX Vref Scan disable
5679 22:16:40.517542 == TX Byte 0 ==
5680 22:16:40.520743 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5681 22:16:40.527520 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5682 22:16:40.527602 == TX Byte 1 ==
5683 22:16:40.530516 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5684 22:16:40.537372 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5685 22:16:40.537461 ==
5686 22:16:40.540780 Dram Type= 6, Freq= 0, CH_1, rank 0
5687 22:16:40.543990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5688 22:16:40.544086 ==
5689 22:16:40.544161
5690 22:16:40.544230
5691 22:16:40.547709 TX Vref Scan disable
5692 22:16:40.551388 == TX Byte 0 ==
5693 22:16:40.554547 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5694 22:16:40.557839 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5695 22:16:40.561038 == TX Byte 1 ==
5696 22:16:40.564525 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5697 22:16:40.567569 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5698 22:16:40.568031
5699 22:16:40.570881 [DATLAT]
5700 22:16:40.571298 Freq=933, CH1 RK0
5701 22:16:40.571630
5702 22:16:40.574502 DATLAT Default: 0xd
5703 22:16:40.574921 0, 0xFFFF, sum = 0
5704 22:16:40.577740 1, 0xFFFF, sum = 0
5705 22:16:40.578167 2, 0xFFFF, sum = 0
5706 22:16:40.580860 3, 0xFFFF, sum = 0
5707 22:16:40.581319 4, 0xFFFF, sum = 0
5708 22:16:40.584511 5, 0xFFFF, sum = 0
5709 22:16:40.584937 6, 0xFFFF, sum = 0
5710 22:16:40.588039 7, 0xFFFF, sum = 0
5711 22:16:40.588465 8, 0xFFFF, sum = 0
5712 22:16:40.590787 9, 0xFFFF, sum = 0
5713 22:16:40.591225 10, 0x0, sum = 1
5714 22:16:40.594527 11, 0x0, sum = 2
5715 22:16:40.594953 12, 0x0, sum = 3
5716 22:16:40.597689 13, 0x0, sum = 4
5717 22:16:40.598113 best_step = 11
5718 22:16:40.598447
5719 22:16:40.598758 ==
5720 22:16:40.600882 Dram Type= 6, Freq= 0, CH_1, rank 0
5721 22:16:40.604065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5722 22:16:40.607341 ==
5723 22:16:40.607761 RX Vref Scan: 1
5724 22:16:40.608141
5725 22:16:40.610758 RX Vref 0 -> 0, step: 1
5726 22:16:40.611174
5727 22:16:40.614442 RX Delay -61 -> 252, step: 4
5728 22:16:40.614860
5729 22:16:40.617474 Set Vref, RX VrefLevel [Byte0]: 58
5730 22:16:40.617896 [Byte1]: 52
5731 22:16:40.622880
5732 22:16:40.623298 Final RX Vref Byte 0 = 58 to rank0
5733 22:16:40.625978 Final RX Vref Byte 1 = 52 to rank0
5734 22:16:40.629335 Final RX Vref Byte 0 = 58 to rank1
5735 22:16:40.632388 Final RX Vref Byte 1 = 52 to rank1==
5736 22:16:40.635712 Dram Type= 6, Freq= 0, CH_1, rank 0
5737 22:16:40.642673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5738 22:16:40.643230 ==
5739 22:16:40.643716 DQS Delay:
5740 22:16:40.645781 DQS0 = 0, DQS1 = 0
5741 22:16:40.646196 DQM Delay:
5742 22:16:40.646527 DQM0 = 97, DQM1 = 91
5743 22:16:40.650029 DQ Delay:
5744 22:16:40.653215 DQ0 =102, DQ1 =92, DQ2 =88, DQ3 =98
5745 22:16:40.655653 DQ4 =96, DQ5 =106, DQ6 =106, DQ7 =94
5746 22:16:40.659223 DQ8 =82, DQ9 =80, DQ10 =90, DQ11 =88
5747 22:16:40.662476 DQ12 =100, DQ13 =96, DQ14 =100, DQ15 =96
5748 22:16:40.662894
5749 22:16:40.663227
5750 22:16:40.669113 [DQSOSCAuto] RK0, (LSB)MR18= 0x11ee, (MSB)MR19= 0x504, tDQSOscB0 = 428 ps tDQSOscB1 = 416 ps
5751 22:16:40.672054 CH1 RK0: MR19=504, MR18=11EE
5752 22:16:40.678596 CH1_RK0: MR19=0x504, MR18=0x11EE, DQSOSC=416, MR23=63, INC=62, DEC=41
5753 22:16:40.679032
5754 22:16:40.681883 ----->DramcWriteLeveling(PI) begin...
5755 22:16:40.682290 ==
5756 22:16:40.685745 Dram Type= 6, Freq= 0, CH_1, rank 1
5757 22:16:40.688355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5758 22:16:40.688746 ==
5759 22:16:40.692131 Write leveling (Byte 0): 26 => 26
5760 22:16:40.695332 Write leveling (Byte 1): 28 => 28
5761 22:16:40.698758 DramcWriteLeveling(PI) end<-----
5762 22:16:40.699145
5763 22:16:40.699474 ==
5764 22:16:40.702042 Dram Type= 6, Freq= 0, CH_1, rank 1
5765 22:16:40.705416 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5766 22:16:40.708177 ==
5767 22:16:40.708537 [Gating] SW mode calibration
5768 22:16:40.718517 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5769 22:16:40.721513 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5770 22:16:40.725121 0 14 0 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5771 22:16:40.732186 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5772 22:16:40.734811 0 14 8 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5773 22:16:40.738160 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5774 22:16:40.744356 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5775 22:16:40.747488 0 14 20 | B1->B0 | 3535 3434 | 1 1 | (0 0) (1 1)
5776 22:16:40.750816 0 14 24 | B1->B0 | 3131 2d2d | 1 0 | (1 0) (0 1)
5777 22:16:40.757347 0 14 28 | B1->B0 | 2828 2323 | 0 0 | (1 0) (1 0)
5778 22:16:40.761188 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5779 22:16:40.764109 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5780 22:16:40.770890 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5781 22:16:40.774107 0 15 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5782 22:16:40.777384 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5783 22:16:40.784163 0 15 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5784 22:16:40.787370 0 15 24 | B1->B0 | 2c2c 3939 | 1 0 | (0 0) (0 0)
5785 22:16:40.790637 0 15 28 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
5786 22:16:40.797462 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5787 22:16:40.800809 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5788 22:16:40.804268 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5789 22:16:40.810545 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5790 22:16:40.813663 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5791 22:16:40.817325 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5792 22:16:40.824140 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5793 22:16:40.827477 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5794 22:16:40.830555 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5795 22:16:40.837068 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5796 22:16:40.840466 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5797 22:16:40.843365 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5798 22:16:40.850370 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5799 22:16:40.853502 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5800 22:16:40.856820 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5801 22:16:40.863356 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5802 22:16:40.866984 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5803 22:16:40.869894 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5804 22:16:40.876748 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5805 22:16:40.879875 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5806 22:16:40.883286 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5807 22:16:40.889777 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5808 22:16:40.892848 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5809 22:16:40.896598 Total UI for P1: 0, mck2ui 16
5810 22:16:40.899852 best dqsien dly found for B0: ( 1, 2, 20)
5811 22:16:40.902952 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5812 22:16:40.906840 Total UI for P1: 0, mck2ui 16
5813 22:16:40.910039 best dqsien dly found for B1: ( 1, 2, 24)
5814 22:16:40.913523 best DQS0 dly(MCK, UI, PI) = (1, 2, 20)
5815 22:16:40.916622 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5816 22:16:40.916703
5817 22:16:40.923197 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 20)
5818 22:16:40.926473 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5819 22:16:40.926554 [Gating] SW calibration Done
5820 22:16:40.929588 ==
5821 22:16:40.933116 Dram Type= 6, Freq= 0, CH_1, rank 1
5822 22:16:40.936438 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5823 22:16:40.936521 ==
5824 22:16:40.936586 RX Vref Scan: 0
5825 22:16:40.936647
5826 22:16:40.939449 RX Vref 0 -> 0, step: 1
5827 22:16:40.939530
5828 22:16:40.943088 RX Delay -80 -> 252, step: 8
5829 22:16:40.946680 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5830 22:16:40.949755 iDelay=200, Bit 1, Center 87 (-8 ~ 183) 192
5831 22:16:40.952793 iDelay=200, Bit 2, Center 87 (-8 ~ 183) 192
5832 22:16:40.959429 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5833 22:16:40.962681 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5834 22:16:40.966093 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5835 22:16:40.969279 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5836 22:16:40.972898 iDelay=200, Bit 7, Center 87 (-8 ~ 183) 192
5837 22:16:40.976070 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5838 22:16:40.982750 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5839 22:16:40.985780 iDelay=200, Bit 10, Center 91 (-8 ~ 191) 200
5840 22:16:40.989398 iDelay=200, Bit 11, Center 79 (-16 ~ 175) 192
5841 22:16:40.992775 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5842 22:16:40.995940 iDelay=200, Bit 13, Center 99 (0 ~ 199) 200
5843 22:16:41.002237 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5844 22:16:41.005847 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5845 22:16:41.005982 ==
5846 22:16:41.009033 Dram Type= 6, Freq= 0, CH_1, rank 1
5847 22:16:41.012327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5848 22:16:41.012501 ==
5849 22:16:41.012641 DQS Delay:
5850 22:16:41.015974 DQS0 = 0, DQS1 = 0
5851 22:16:41.016146 DQM Delay:
5852 22:16:41.019529 DQM0 = 94, DQM1 = 89
5853 22:16:41.019728 DQ Delay:
5854 22:16:41.022727 DQ0 =95, DQ1 =87, DQ2 =87, DQ3 =95
5855 22:16:41.026236 DQ4 =95, DQ5 =103, DQ6 =103, DQ7 =87
5856 22:16:41.029059 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =79
5857 22:16:41.032780 DQ12 =95, DQ13 =99, DQ14 =95, DQ15 =95
5858 22:16:41.033205
5859 22:16:41.033524
5860 22:16:41.033837 ==
5861 22:16:41.035824 Dram Type= 6, Freq= 0, CH_1, rank 1
5862 22:16:41.040056 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5863 22:16:41.042773 ==
5864 22:16:41.043204
5865 22:16:41.043565
5866 22:16:41.043885 TX Vref Scan disable
5867 22:16:41.046003 == TX Byte 0 ==
5868 22:16:41.049421 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5869 22:16:41.053256 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5870 22:16:41.056378 == TX Byte 1 ==
5871 22:16:41.059391 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5872 22:16:41.062722 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5873 22:16:41.065807 ==
5874 22:16:41.066230 Dram Type= 6, Freq= 0, CH_1, rank 1
5875 22:16:41.072939 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5876 22:16:41.073405 ==
5877 22:16:41.073749
5878 22:16:41.074086
5879 22:16:41.076005 TX Vref Scan disable
5880 22:16:41.076477 == TX Byte 0 ==
5881 22:16:41.083024 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5882 22:16:41.085986 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5883 22:16:41.086453 == TX Byte 1 ==
5884 22:16:41.092391 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5885 22:16:41.095757 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5886 22:16:41.096252
5887 22:16:41.096589 [DATLAT]
5888 22:16:41.098967 Freq=933, CH1 RK1
5889 22:16:41.099420
5890 22:16:41.099756 DATLAT Default: 0xb
5891 22:16:41.102592 0, 0xFFFF, sum = 0
5892 22:16:41.103027 1, 0xFFFF, sum = 0
5893 22:16:41.105585 2, 0xFFFF, sum = 0
5894 22:16:41.106035 3, 0xFFFF, sum = 0
5895 22:16:41.109260 4, 0xFFFF, sum = 0
5896 22:16:41.109695 5, 0xFFFF, sum = 0
5897 22:16:41.112392 6, 0xFFFF, sum = 0
5898 22:16:41.112833 7, 0xFFFF, sum = 0
5899 22:16:41.116055 8, 0xFFFF, sum = 0
5900 22:16:41.116488 9, 0xFFFF, sum = 0
5901 22:16:41.119743 10, 0x0, sum = 1
5902 22:16:41.120214 11, 0x0, sum = 2
5903 22:16:41.122593 12, 0x0, sum = 3
5904 22:16:41.123022 13, 0x0, sum = 4
5905 22:16:41.126143 best_step = 11
5906 22:16:41.126621
5907 22:16:41.126968 ==
5908 22:16:41.129389 Dram Type= 6, Freq= 0, CH_1, rank 1
5909 22:16:41.132378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5910 22:16:41.133142 ==
5911 22:16:41.135571 RX Vref Scan: 0
5912 22:16:41.136043
5913 22:16:41.136384 RX Vref 0 -> 0, step: 1
5914 22:16:41.136700
5915 22:16:41.139124 RX Delay -61 -> 252, step: 4
5916 22:16:41.145847 iDelay=199, Bit 0, Center 98 (7 ~ 190) 184
5917 22:16:41.149492 iDelay=199, Bit 1, Center 88 (-5 ~ 182) 188
5918 22:16:41.152552 iDelay=199, Bit 2, Center 86 (-5 ~ 178) 184
5919 22:16:41.155905 iDelay=199, Bit 3, Center 94 (3 ~ 186) 184
5920 22:16:41.159021 iDelay=199, Bit 4, Center 98 (7 ~ 190) 184
5921 22:16:41.165909 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5922 22:16:41.169153 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5923 22:16:41.172365 iDelay=199, Bit 7, Center 92 (3 ~ 182) 180
5924 22:16:41.176052 iDelay=199, Bit 8, Center 80 (-13 ~ 174) 188
5925 22:16:41.179365 iDelay=199, Bit 9, Center 78 (-13 ~ 170) 184
5926 22:16:41.182093 iDelay=199, Bit 10, Center 92 (-1 ~ 186) 188
5927 22:16:41.188637 iDelay=199, Bit 11, Center 84 (-5 ~ 174) 180
5928 22:16:41.192006 iDelay=199, Bit 12, Center 98 (11 ~ 186) 176
5929 22:16:41.195244 iDelay=199, Bit 13, Center 100 (11 ~ 190) 180
5930 22:16:41.199326 iDelay=199, Bit 14, Center 100 (11 ~ 190) 180
5931 22:16:41.205492 iDelay=199, Bit 15, Center 98 (7 ~ 190) 184
5932 22:16:41.205912 ==
5933 22:16:41.209129 Dram Type= 6, Freq= 0, CH_1, rank 1
5934 22:16:41.212096 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5935 22:16:41.212515 ==
5936 22:16:41.212847 DQS Delay:
5937 22:16:41.215240 DQS0 = 0, DQS1 = 0
5938 22:16:41.215656 DQM Delay:
5939 22:16:41.218898 DQM0 = 95, DQM1 = 91
5940 22:16:41.219312 DQ Delay:
5941 22:16:41.221775 DQ0 =98, DQ1 =88, DQ2 =86, DQ3 =94
5942 22:16:41.225013 DQ4 =98, DQ5 =106, DQ6 =104, DQ7 =92
5943 22:16:41.229059 DQ8 =80, DQ9 =78, DQ10 =92, DQ11 =84
5944 22:16:41.232421 DQ12 =98, DQ13 =100, DQ14 =100, DQ15 =98
5945 22:16:41.232843
5946 22:16:41.233178
5947 22:16:41.238220 [DQSOSCAuto] RK1, (LSB)MR18= 0x1019, (MSB)MR19= 0x505, tDQSOscB0 = 413 ps tDQSOscB1 = 416 ps
5948 22:16:41.242084 CH1 RK1: MR19=505, MR18=1019
5949 22:16:41.248626 CH1_RK1: MR19=0x505, MR18=0x1019, DQSOSC=413, MR23=63, INC=63, DEC=42
5950 22:16:41.251883 [RxdqsGatingPostProcess] freq 933
5951 22:16:41.258399 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5952 22:16:41.262135 best DQS0 dly(2T, 0.5T) = (0, 10)
5953 22:16:41.262552 best DQS1 dly(2T, 0.5T) = (0, 10)
5954 22:16:41.265354 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5955 22:16:41.268630 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5956 22:16:41.271649 best DQS0 dly(2T, 0.5T) = (0, 10)
5957 22:16:41.275396 best DQS1 dly(2T, 0.5T) = (0, 10)
5958 22:16:41.278232 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5959 22:16:41.281877 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5960 22:16:41.285251 Pre-setting of DQS Precalculation
5961 22:16:41.291723 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5962 22:16:41.298222 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5963 22:16:41.305117 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5964 22:16:41.305533
5965 22:16:41.305862
5966 22:16:41.308522 [Calibration Summary] 1866 Mbps
5967 22:16:41.308942 CH 0, Rank 0
5968 22:16:41.311318 SW Impedance : PASS
5969 22:16:41.314419 DUTY Scan : NO K
5970 22:16:41.314500 ZQ Calibration : PASS
5971 22:16:41.318312 Jitter Meter : NO K
5972 22:16:41.320926 CBT Training : PASS
5973 22:16:41.321007 Write leveling : PASS
5974 22:16:41.324185 RX DQS gating : PASS
5975 22:16:41.328292 RX DQ/DQS(RDDQC) : PASS
5976 22:16:41.328373 TX DQ/DQS : PASS
5977 22:16:41.331019 RX DATLAT : PASS
5978 22:16:41.331100 RX DQ/DQS(Engine): PASS
5979 22:16:41.334851 TX OE : NO K
5980 22:16:41.334957 All Pass.
5981 22:16:41.335027
5982 22:16:41.337758 CH 0, Rank 1
5983 22:16:41.337839 SW Impedance : PASS
5984 22:16:41.341325 DUTY Scan : NO K
5985 22:16:41.344246 ZQ Calibration : PASS
5986 22:16:41.344327 Jitter Meter : NO K
5987 22:16:41.347839 CBT Training : PASS
5988 22:16:41.350988 Write leveling : PASS
5989 22:16:41.351069 RX DQS gating : PASS
5990 22:16:41.354103 RX DQ/DQS(RDDQC) : PASS
5991 22:16:41.357755 TX DQ/DQS : PASS
5992 22:16:41.357837 RX DATLAT : PASS
5993 22:16:41.361076 RX DQ/DQS(Engine): PASS
5994 22:16:41.364408 TX OE : NO K
5995 22:16:41.364489 All Pass.
5996 22:16:41.364553
5997 22:16:41.364613 CH 1, Rank 0
5998 22:16:41.367914 SW Impedance : PASS
5999 22:16:41.370893 DUTY Scan : NO K
6000 22:16:41.370973 ZQ Calibration : PASS
6001 22:16:41.374347 Jitter Meter : NO K
6002 22:16:41.377994 CBT Training : PASS
6003 22:16:41.378075 Write leveling : PASS
6004 22:16:41.381146 RX DQS gating : PASS
6005 22:16:41.381227 RX DQ/DQS(RDDQC) : PASS
6006 22:16:41.384408 TX DQ/DQS : PASS
6007 22:16:41.387719 RX DATLAT : PASS
6008 22:16:41.387825 RX DQ/DQS(Engine): PASS
6009 22:16:41.390768 TX OE : NO K
6010 22:16:41.390849 All Pass.
6011 22:16:41.390913
6012 22:16:41.394259 CH 1, Rank 1
6013 22:16:41.394340 SW Impedance : PASS
6014 22:16:41.397362 DUTY Scan : NO K
6015 22:16:41.401243 ZQ Calibration : PASS
6016 22:16:41.401339 Jitter Meter : NO K
6017 22:16:41.404454 CBT Training : PASS
6018 22:16:41.407714 Write leveling : PASS
6019 22:16:41.407814 RX DQS gating : PASS
6020 22:16:41.410903 RX DQ/DQS(RDDQC) : PASS
6021 22:16:41.414086 TX DQ/DQS : PASS
6022 22:16:41.414219 RX DATLAT : PASS
6023 22:16:41.417275 RX DQ/DQS(Engine): PASS
6024 22:16:41.421011 TX OE : NO K
6025 22:16:41.421132 All Pass.
6026 22:16:41.421243
6027 22:16:41.421342 DramC Write-DBI off
6028 22:16:41.424477 PER_BANK_REFRESH: Hybrid Mode
6029 22:16:41.427471 TX_TRACKING: ON
6030 22:16:41.433886 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6031 22:16:41.441589 [FAST_K] Save calibration result to emmc
6032 22:16:41.444214 dramc_set_vcore_voltage set vcore to 650000
6033 22:16:41.444451 Read voltage for 400, 6
6034 22:16:41.447400 Vio18 = 0
6035 22:16:41.447695 Vcore = 650000
6036 22:16:41.447930 Vdram = 0
6037 22:16:41.450622 Vddq = 0
6038 22:16:41.450915 Vmddr = 0
6039 22:16:41.454273 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6040 22:16:41.460958 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6041 22:16:41.464131 MEM_TYPE=3, freq_sel=20
6042 22:16:41.468021 sv_algorithm_assistance_LP4_800
6043 22:16:41.471108 ============ PULL DRAM RESETB DOWN ============
6044 22:16:41.473987 ========== PULL DRAM RESETB DOWN end =========
6045 22:16:41.477301 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6046 22:16:41.480417 ===================================
6047 22:16:41.484097 LPDDR4 DRAM CONFIGURATION
6048 22:16:41.488020 ===================================
6049 22:16:41.491012 EX_ROW_EN[0] = 0x0
6050 22:16:41.491430 EX_ROW_EN[1] = 0x0
6051 22:16:41.494391 LP4Y_EN = 0x0
6052 22:16:41.494809 WORK_FSP = 0x0
6053 22:16:41.497508 WL = 0x2
6054 22:16:41.497926 RL = 0x2
6055 22:16:41.500587 BL = 0x2
6056 22:16:41.501005 RPST = 0x0
6057 22:16:41.504009 RD_PRE = 0x0
6058 22:16:41.504430 WR_PRE = 0x1
6059 22:16:41.508250 WR_PST = 0x0
6060 22:16:41.508668 DBI_WR = 0x0
6061 22:16:41.510765 DBI_RD = 0x0
6062 22:16:41.514082 OTF = 0x1
6063 22:16:41.517142 ===================================
6064 22:16:41.520433 ===================================
6065 22:16:41.520855 ANA top config
6066 22:16:41.524159 ===================================
6067 22:16:41.527029 DLL_ASYNC_EN = 0
6068 22:16:41.527444 ALL_SLAVE_EN = 1
6069 22:16:41.530426 NEW_RANK_MODE = 1
6070 22:16:41.533527 DLL_IDLE_MODE = 1
6071 22:16:41.537370 LP45_APHY_COMB_EN = 1
6072 22:16:41.540531 TX_ODT_DIS = 1
6073 22:16:41.541124 NEW_8X_MODE = 1
6074 22:16:41.543694 ===================================
6075 22:16:41.547212 ===================================
6076 22:16:41.550159 data_rate = 800
6077 22:16:41.553964 CKR = 1
6078 22:16:41.556978 DQ_P2S_RATIO = 4
6079 22:16:41.560051 ===================================
6080 22:16:41.563715 CA_P2S_RATIO = 4
6081 22:16:41.567064 DQ_CA_OPEN = 0
6082 22:16:41.567523 DQ_SEMI_OPEN = 1
6083 22:16:41.570115 CA_SEMI_OPEN = 1
6084 22:16:41.573568 CA_FULL_RATE = 0
6085 22:16:41.577187 DQ_CKDIV4_EN = 0
6086 22:16:41.580065 CA_CKDIV4_EN = 1
6087 22:16:41.583317 CA_PREDIV_EN = 0
6088 22:16:41.583767 PH8_DLY = 0
6089 22:16:41.586600 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6090 22:16:41.590085 DQ_AAMCK_DIV = 0
6091 22:16:41.593729 CA_AAMCK_DIV = 0
6092 22:16:41.596965 CA_ADMCK_DIV = 4
6093 22:16:41.600572 DQ_TRACK_CA_EN = 0
6094 22:16:41.603381 CA_PICK = 800
6095 22:16:41.603948 CA_MCKIO = 400
6096 22:16:41.606242 MCKIO_SEMI = 400
6097 22:16:41.610095 PLL_FREQ = 3016
6098 22:16:41.613469 DQ_UI_PI_RATIO = 32
6099 22:16:41.616871 CA_UI_PI_RATIO = 32
6100 22:16:41.619551 ===================================
6101 22:16:41.623226 ===================================
6102 22:16:41.626508 memory_type:LPDDR4
6103 22:16:41.626980 GP_NUM : 10
6104 22:16:41.629961 SRAM_EN : 1
6105 22:16:41.630566 MD32_EN : 0
6106 22:16:41.632910 ===================================
6107 22:16:41.636293 [ANA_INIT] >>>>>>>>>>>>>>
6108 22:16:41.639714 <<<<<< [CONFIGURE PHASE]: ANA_TX
6109 22:16:41.643273 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6110 22:16:41.646187 ===================================
6111 22:16:41.649599 data_rate = 800,PCW = 0X7400
6112 22:16:41.653171 ===================================
6113 22:16:41.656529 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6114 22:16:41.662918 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6115 22:16:41.672995 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6116 22:16:41.676288 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6117 22:16:41.679730 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6118 22:16:41.683082 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6119 22:16:41.686251 [ANA_INIT] flow start
6120 22:16:41.689533 [ANA_INIT] PLL >>>>>>>>
6121 22:16:41.689976 [ANA_INIT] PLL <<<<<<<<
6122 22:16:41.693248 [ANA_INIT] MIDPI >>>>>>>>
6123 22:16:41.696654 [ANA_INIT] MIDPI <<<<<<<<
6124 22:16:41.697225 [ANA_INIT] DLL >>>>>>>>
6125 22:16:41.699621 [ANA_INIT] flow end
6126 22:16:41.703766 ============ LP4 DIFF to SE enter ============
6127 22:16:41.709530 ============ LP4 DIFF to SE exit ============
6128 22:16:41.709976 [ANA_INIT] <<<<<<<<<<<<<
6129 22:16:41.712740 [Flow] Enable top DCM control >>>>>
6130 22:16:41.716199 [Flow] Enable top DCM control <<<<<
6131 22:16:41.719526 Enable DLL master slave shuffle
6132 22:16:41.726060 ==============================================================
6133 22:16:41.726492 Gating Mode config
6134 22:16:41.733528 ==============================================================
6135 22:16:41.736262 Config description:
6136 22:16:41.742862 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6137 22:16:41.749548 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6138 22:16:41.755904 SELPH_MODE 0: By rank 1: By Phase
6139 22:16:41.762617 ==============================================================
6140 22:16:41.763038 GAT_TRACK_EN = 0
6141 22:16:41.766086 RX_GATING_MODE = 2
6142 22:16:41.769228 RX_GATING_TRACK_MODE = 2
6143 22:16:41.772559 SELPH_MODE = 1
6144 22:16:41.776665 PICG_EARLY_EN = 1
6145 22:16:41.780519 VALID_LAT_VALUE = 1
6146 22:16:41.786298 ==============================================================
6147 22:16:41.789500 Enter into Gating configuration >>>>
6148 22:16:41.793038 Exit from Gating configuration <<<<
6149 22:16:41.796221 Enter into DVFS_PRE_config >>>>>
6150 22:16:41.806397 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6151 22:16:41.809134 Exit from DVFS_PRE_config <<<<<
6152 22:16:41.812941 Enter into PICG configuration >>>>
6153 22:16:41.816181 Exit from PICG configuration <<<<
6154 22:16:41.819818 [RX_INPUT] configuration >>>>>
6155 22:16:41.820266 [RX_INPUT] configuration <<<<<
6156 22:16:41.825981 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6157 22:16:41.832991 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6158 22:16:41.836141 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6159 22:16:41.842639 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6160 22:16:41.849684 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6161 22:16:41.856076 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6162 22:16:41.858996 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6163 22:16:41.862659 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6164 22:16:41.868826 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6165 22:16:41.872574 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6166 22:16:41.875833 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6167 22:16:41.882205 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6168 22:16:41.886076 ===================================
6169 22:16:41.886593 LPDDR4 DRAM CONFIGURATION
6170 22:16:41.888943 ===================================
6171 22:16:41.892338 EX_ROW_EN[0] = 0x0
6172 22:16:41.892874 EX_ROW_EN[1] = 0x0
6173 22:16:41.895782 LP4Y_EN = 0x0
6174 22:16:41.896249 WORK_FSP = 0x0
6175 22:16:41.898960 WL = 0x2
6176 22:16:41.902474 RL = 0x2
6177 22:16:41.902901 BL = 0x2
6178 22:16:41.905470 RPST = 0x0
6179 22:16:41.905895 RD_PRE = 0x0
6180 22:16:41.909386 WR_PRE = 0x1
6181 22:16:41.909812 WR_PST = 0x0
6182 22:16:41.913194 DBI_WR = 0x0
6183 22:16:41.913619 DBI_RD = 0x0
6184 22:16:41.915398 OTF = 0x1
6185 22:16:41.919523 ===================================
6186 22:16:41.922124 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6187 22:16:41.925890 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6188 22:16:41.928789 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6189 22:16:41.932520 ===================================
6190 22:16:41.935225 LPDDR4 DRAM CONFIGURATION
6191 22:16:41.938676 ===================================
6192 22:16:41.942236 EX_ROW_EN[0] = 0x10
6193 22:16:41.942657 EX_ROW_EN[1] = 0x0
6194 22:16:41.945771 LP4Y_EN = 0x0
6195 22:16:41.946192 WORK_FSP = 0x0
6196 22:16:41.948841 WL = 0x2
6197 22:16:41.949260 RL = 0x2
6198 22:16:41.952083 BL = 0x2
6199 22:16:41.952501 RPST = 0x0
6200 22:16:41.955511 RD_PRE = 0x0
6201 22:16:41.959074 WR_PRE = 0x1
6202 22:16:41.959582 WR_PST = 0x0
6203 22:16:41.962141 DBI_WR = 0x0
6204 22:16:41.962557 DBI_RD = 0x0
6205 22:16:41.965335 OTF = 0x1
6206 22:16:41.968949 ===================================
6207 22:16:41.972126 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6208 22:16:41.977160 nWR fixed to 30
6209 22:16:41.980510 [ModeRegInit_LP4] CH0 RK0
6210 22:16:41.981045 [ModeRegInit_LP4] CH0 RK1
6211 22:16:41.983943 [ModeRegInit_LP4] CH1 RK0
6212 22:16:41.986920 [ModeRegInit_LP4] CH1 RK1
6213 22:16:41.987334 match AC timing 19
6214 22:16:41.993721 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6215 22:16:41.997053 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6216 22:16:41.999910 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6217 22:16:42.006871 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6218 22:16:42.010058 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6219 22:16:42.010139 ==
6220 22:16:42.013654 Dram Type= 6, Freq= 0, CH_0, rank 0
6221 22:16:42.016896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6222 22:16:42.016978 ==
6223 22:16:42.023315 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6224 22:16:42.030137 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6225 22:16:42.033038 [CA 0] Center 36 (8~64) winsize 57
6226 22:16:42.036386 [CA 1] Center 36 (8~64) winsize 57
6227 22:16:42.039751 [CA 2] Center 36 (8~64) winsize 57
6228 22:16:42.043347 [CA 3] Center 36 (8~64) winsize 57
6229 22:16:42.043428 [CA 4] Center 36 (8~64) winsize 57
6230 22:16:42.046674 [CA 5] Center 36 (8~64) winsize 57
6231 22:16:42.046755
6232 22:16:42.053110 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6233 22:16:42.053191
6234 22:16:42.056483 [CATrainingPosCal] consider 1 rank data
6235 22:16:42.059661 u2DelayCellTimex100 = 270/100 ps
6236 22:16:42.062982 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6237 22:16:42.066480 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6238 22:16:42.069914 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6239 22:16:42.073072 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6240 22:16:42.076230 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6241 22:16:42.079583 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6242 22:16:42.079664
6243 22:16:42.083048 CA PerBit enable=1, Macro0, CA PI delay=36
6244 22:16:42.083129
6245 22:16:42.086249 [CBTSetCACLKResult] CA Dly = 36
6246 22:16:42.089793 CS Dly: 1 (0~32)
6247 22:16:42.089880 ==
6248 22:16:42.092820 Dram Type= 6, Freq= 0, CH_0, rank 1
6249 22:16:42.096849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6250 22:16:42.096950 ==
6251 22:16:42.102997 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6252 22:16:42.106411 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6253 22:16:42.109435 [CA 0] Center 36 (8~64) winsize 57
6254 22:16:42.113251 [CA 1] Center 36 (8~64) winsize 57
6255 22:16:42.115970 [CA 2] Center 36 (8~64) winsize 57
6256 22:16:42.119649 [CA 3] Center 36 (8~64) winsize 57
6257 22:16:42.123132 [CA 4] Center 36 (8~64) winsize 57
6258 22:16:42.126197 [CA 5] Center 36 (8~64) winsize 57
6259 22:16:42.126413
6260 22:16:42.129797 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6261 22:16:42.130004
6262 22:16:42.132841 [CATrainingPosCal] consider 2 rank data
6263 22:16:42.136071 u2DelayCellTimex100 = 270/100 ps
6264 22:16:42.139705 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6265 22:16:42.143111 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6266 22:16:42.149451 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6267 22:16:42.152474 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6268 22:16:42.155930 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6269 22:16:42.159165 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6270 22:16:42.159248
6271 22:16:42.163073 CA PerBit enable=1, Macro0, CA PI delay=36
6272 22:16:42.163150
6273 22:16:42.166015 [CBTSetCACLKResult] CA Dly = 36
6274 22:16:42.166087 CS Dly: 1 (0~32)
6275 22:16:42.166149
6276 22:16:42.169407 ----->DramcWriteLeveling(PI) begin...
6277 22:16:42.172847 ==
6278 22:16:42.175928 Dram Type= 6, Freq= 0, CH_0, rank 0
6279 22:16:42.179337 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6280 22:16:42.179428 ==
6281 22:16:42.182482 Write leveling (Byte 0): 40 => 8
6282 22:16:42.185626 Write leveling (Byte 1): 32 => 0
6283 22:16:42.189245 DramcWriteLeveling(PI) end<-----
6284 22:16:42.189353
6285 22:16:42.189446 ==
6286 22:16:42.192270 Dram Type= 6, Freq= 0, CH_0, rank 0
6287 22:16:42.195604 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6288 22:16:42.195724 ==
6289 22:16:42.198805 [Gating] SW mode calibration
6290 22:16:42.205600 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6291 22:16:42.212610 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6292 22:16:42.216019 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6293 22:16:42.219132 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6294 22:16:42.225857 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6295 22:16:42.229566 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6296 22:16:42.232418 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6297 22:16:42.235813 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6298 22:16:42.242871 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6299 22:16:42.245965 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6300 22:16:42.248713 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6301 22:16:42.252710 Total UI for P1: 0, mck2ui 16
6302 22:16:42.255432 best dqsien dly found for B0: ( 0, 14, 24)
6303 22:16:42.258957 Total UI for P1: 0, mck2ui 16
6304 22:16:42.262482 best dqsien dly found for B1: ( 0, 14, 24)
6305 22:16:42.266020 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6306 22:16:42.272600 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6307 22:16:42.273008
6308 22:16:42.275469 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6309 22:16:42.279230 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6310 22:16:42.282465 [Gating] SW calibration Done
6311 22:16:42.282873 ==
6312 22:16:42.285409 Dram Type= 6, Freq= 0, CH_0, rank 0
6313 22:16:42.288688 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6314 22:16:42.289140 ==
6315 22:16:42.292203 RX Vref Scan: 0
6316 22:16:42.292609
6317 22:16:42.292934 RX Vref 0 -> 0, step: 1
6318 22:16:42.293238
6319 22:16:42.295578 RX Delay -410 -> 252, step: 16
6320 22:16:42.298638 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6321 22:16:42.305614 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6322 22:16:42.308616 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6323 22:16:42.312070 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6324 22:16:42.315441 iDelay=230, Bit 4, Center -19 (-266 ~ 229) 496
6325 22:16:42.322200 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6326 22:16:42.325221 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6327 22:16:42.328754 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6328 22:16:42.331898 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6329 22:16:42.338555 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6330 22:16:42.341926 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6331 22:16:42.345452 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6332 22:16:42.348624 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6333 22:16:42.355389 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6334 22:16:42.358906 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6335 22:16:42.361771 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6336 22:16:42.362193 ==
6337 22:16:42.365376 Dram Type= 6, Freq= 0, CH_0, rank 0
6338 22:16:42.371735 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6339 22:16:42.372176 ==
6340 22:16:42.372497 DQS Delay:
6341 22:16:42.374886 DQS0 = 35, DQS1 = 51
6342 22:16:42.375292 DQM Delay:
6343 22:16:42.375616 DQM0 = 7, DQM1 = 10
6344 22:16:42.378135 DQ Delay:
6345 22:16:42.382160 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6346 22:16:42.382568 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6347 22:16:42.385213 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6348 22:16:42.388967 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6349 22:16:42.389373
6350 22:16:42.391909
6351 22:16:42.392362 ==
6352 22:16:42.395793 Dram Type= 6, Freq= 0, CH_0, rank 0
6353 22:16:42.398448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6354 22:16:42.398866 ==
6355 22:16:42.399195
6356 22:16:42.399502
6357 22:16:42.401977 TX Vref Scan disable
6358 22:16:42.402391 == TX Byte 0 ==
6359 22:16:42.404846 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6360 22:16:42.411551 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6361 22:16:42.412005 == TX Byte 1 ==
6362 22:16:42.415128 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6363 22:16:42.421679 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6364 22:16:42.422099 ==
6365 22:16:42.425307 Dram Type= 6, Freq= 0, CH_0, rank 0
6366 22:16:42.428790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6367 22:16:42.429208 ==
6368 22:16:42.429539
6369 22:16:42.429849
6370 22:16:42.431255 TX Vref Scan disable
6371 22:16:42.431672 == TX Byte 0 ==
6372 22:16:42.438020 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6373 22:16:42.441604 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6374 22:16:42.442021 == TX Byte 1 ==
6375 22:16:42.448625 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6376 22:16:42.451622 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6377 22:16:42.452091
6378 22:16:42.452431 [DATLAT]
6379 22:16:42.454576 Freq=400, CH0 RK0
6380 22:16:42.454991
6381 22:16:42.455322 DATLAT Default: 0xf
6382 22:16:42.457922 0, 0xFFFF, sum = 0
6383 22:16:42.458385 1, 0xFFFF, sum = 0
6384 22:16:42.461157 2, 0xFFFF, sum = 0
6385 22:16:42.461580 3, 0xFFFF, sum = 0
6386 22:16:42.464627 4, 0xFFFF, sum = 0
6387 22:16:42.465049 5, 0xFFFF, sum = 0
6388 22:16:42.468233 6, 0xFFFF, sum = 0
6389 22:16:42.468655 7, 0xFFFF, sum = 0
6390 22:16:42.471147 8, 0xFFFF, sum = 0
6391 22:16:42.471567 9, 0xFFFF, sum = 0
6392 22:16:42.475081 10, 0xFFFF, sum = 0
6393 22:16:42.478144 11, 0xFFFF, sum = 0
6394 22:16:42.478678 12, 0xFFFF, sum = 0
6395 22:16:42.479027 13, 0x0, sum = 1
6396 22:16:42.481157 14, 0x0, sum = 2
6397 22:16:42.481582 15, 0x0, sum = 3
6398 22:16:42.484217 16, 0x0, sum = 4
6399 22:16:42.484641 best_step = 14
6400 22:16:42.484975
6401 22:16:42.485289 ==
6402 22:16:42.487797 Dram Type= 6, Freq= 0, CH_0, rank 0
6403 22:16:42.494759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6404 22:16:42.495179 ==
6405 22:16:42.495510 RX Vref Scan: 1
6406 22:16:42.495819
6407 22:16:42.497886 RX Vref 0 -> 0, step: 1
6408 22:16:42.498301
6409 22:16:42.501233 RX Delay -343 -> 252, step: 8
6410 22:16:42.501650
6411 22:16:42.504134 Set Vref, RX VrefLevel [Byte0]: 53
6412 22:16:42.507562 [Byte1]: 51
6413 22:16:42.510982
6414 22:16:42.511397 Final RX Vref Byte 0 = 53 to rank0
6415 22:16:42.514232 Final RX Vref Byte 1 = 51 to rank0
6416 22:16:42.517598 Final RX Vref Byte 0 = 53 to rank1
6417 22:16:42.521619 Final RX Vref Byte 1 = 51 to rank1==
6418 22:16:42.524396 Dram Type= 6, Freq= 0, CH_0, rank 0
6419 22:16:42.531146 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6420 22:16:42.531576 ==
6421 22:16:42.531909 DQS Delay:
6422 22:16:42.534174 DQS0 = 44, DQS1 = 60
6423 22:16:42.534596 DQM Delay:
6424 22:16:42.534929 DQM0 = 11, DQM1 = 15
6425 22:16:42.537459 DQ Delay:
6426 22:16:42.541507 DQ0 =12, DQ1 =12, DQ2 =4, DQ3 =8
6427 22:16:42.541938 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6428 22:16:42.544506 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =12
6429 22:16:42.548068 DQ12 =20, DQ13 =20, DQ14 =28, DQ15 =28
6430 22:16:42.548506
6431 22:16:42.551317
6432 22:16:42.557882 [DQSOSCAuto] RK0, (LSB)MR18= 0x8351, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 393 ps
6433 22:16:42.561228 CH0 RK0: MR19=C0C, MR18=8351
6434 22:16:42.568213 CH0_RK0: MR19=0xC0C, MR18=0x8351, DQSOSC=393, MR23=63, INC=382, DEC=254
6435 22:16:42.568665 ==
6436 22:16:42.570431 Dram Type= 6, Freq= 0, CH_0, rank 1
6437 22:16:42.574815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6438 22:16:42.575325 ==
6439 22:16:42.577196 [Gating] SW mode calibration
6440 22:16:42.584712 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6441 22:16:42.590995 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6442 22:16:42.593943 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6443 22:16:42.597295 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6444 22:16:42.604020 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6445 22:16:42.607411 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6446 22:16:42.610927 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6447 22:16:42.617283 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6448 22:16:42.620714 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6449 22:16:42.623950 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6450 22:16:42.627128 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6451 22:16:42.630750 Total UI for P1: 0, mck2ui 16
6452 22:16:42.633994 best dqsien dly found for B0: ( 0, 14, 24)
6453 22:16:42.637019 Total UI for P1: 0, mck2ui 16
6454 22:16:42.640454 best dqsien dly found for B1: ( 0, 14, 24)
6455 22:16:42.643770 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6456 22:16:42.650356 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6457 22:16:42.650922
6458 22:16:42.653576 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6459 22:16:42.657579 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6460 22:16:42.660454 [Gating] SW calibration Done
6461 22:16:42.660895 ==
6462 22:16:42.664054 Dram Type= 6, Freq= 0, CH_0, rank 1
6463 22:16:42.667127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6464 22:16:42.667553 ==
6465 22:16:42.670210 RX Vref Scan: 0
6466 22:16:42.670635
6467 22:16:42.670976 RX Vref 0 -> 0, step: 1
6468 22:16:42.671295
6469 22:16:42.674218 RX Delay -410 -> 252, step: 16
6470 22:16:42.676817 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6471 22:16:42.683810 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6472 22:16:42.687395 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6473 22:16:42.691122 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6474 22:16:42.693339 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6475 22:16:42.700347 iDelay=230, Bit 5, Center -43 (-282 ~ 197) 480
6476 22:16:42.703627 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6477 22:16:42.707072 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6478 22:16:42.709958 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6479 22:16:42.716873 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6480 22:16:42.720237 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6481 22:16:42.723494 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6482 22:16:42.730198 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6483 22:16:42.733253 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6484 22:16:42.736436 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6485 22:16:42.739875 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6486 22:16:42.743339 ==
6487 22:16:42.743867 Dram Type= 6, Freq= 0, CH_0, rank 1
6488 22:16:42.749999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6489 22:16:42.750519 ==
6490 22:16:42.750858 DQS Delay:
6491 22:16:42.753179 DQS0 = 43, DQS1 = 51
6492 22:16:42.753598 DQM Delay:
6493 22:16:42.756492 DQM0 = 11, DQM1 = 10
6494 22:16:42.756942 DQ Delay:
6495 22:16:42.759512 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6496 22:16:42.762836 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =24
6497 22:16:42.766189 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6498 22:16:42.769323 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6499 22:16:42.769740
6500 22:16:42.770073
6501 22:16:42.770433 ==
6502 22:16:42.772535 Dram Type= 6, Freq= 0, CH_0, rank 1
6503 22:16:42.776331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6504 22:16:42.776773 ==
6505 22:16:42.777108
6506 22:16:42.777416
6507 22:16:42.779073 TX Vref Scan disable
6508 22:16:42.779488 == TX Byte 0 ==
6509 22:16:42.785874 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6510 22:16:42.789626 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6511 22:16:42.790063 == TX Byte 1 ==
6512 22:16:42.792767 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6513 22:16:42.799359 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6514 22:16:42.799817 ==
6515 22:16:42.803002 Dram Type= 6, Freq= 0, CH_0, rank 1
6516 22:16:42.805826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6517 22:16:42.806263 ==
6518 22:16:42.806695
6519 22:16:42.807102
6520 22:16:42.809861 TX Vref Scan disable
6521 22:16:42.810293 == TX Byte 0 ==
6522 22:16:42.816297 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6523 22:16:42.819168 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6524 22:16:42.819603 == TX Byte 1 ==
6525 22:16:42.823057 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6526 22:16:42.829382 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6527 22:16:42.829920
6528 22:16:42.830361 [DATLAT]
6529 22:16:42.832773 Freq=400, CH0 RK1
6530 22:16:42.833228
6531 22:16:42.833662 DATLAT Default: 0xe
6532 22:16:42.836164 0, 0xFFFF, sum = 0
6533 22:16:42.836621 1, 0xFFFF, sum = 0
6534 22:16:42.839846 2, 0xFFFF, sum = 0
6535 22:16:42.840375 3, 0xFFFF, sum = 0
6536 22:16:42.842939 4, 0xFFFF, sum = 0
6537 22:16:42.843467 5, 0xFFFF, sum = 0
6538 22:16:42.845933 6, 0xFFFF, sum = 0
6539 22:16:42.846453 7, 0xFFFF, sum = 0
6540 22:16:42.849433 8, 0xFFFF, sum = 0
6541 22:16:42.849963 9, 0xFFFF, sum = 0
6542 22:16:42.852738 10, 0xFFFF, sum = 0
6543 22:16:42.853261 11, 0xFFFF, sum = 0
6544 22:16:42.856084 12, 0xFFFF, sum = 0
6545 22:16:42.856630 13, 0x0, sum = 1
6546 22:16:42.859401 14, 0x0, sum = 2
6547 22:16:42.859926 15, 0x0, sum = 3
6548 22:16:42.862745 16, 0x0, sum = 4
6549 22:16:42.863207 best_step = 14
6550 22:16:42.863601
6551 22:16:42.864027 ==
6552 22:16:42.865939 Dram Type= 6, Freq= 0, CH_0, rank 1
6553 22:16:42.872482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6554 22:16:42.873040 ==
6555 22:16:42.873458 RX Vref Scan: 0
6556 22:16:42.873840
6557 22:16:42.876052 RX Vref 0 -> 0, step: 1
6558 22:16:42.876485
6559 22:16:42.879326 RX Delay -343 -> 252, step: 8
6560 22:16:42.885840 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6561 22:16:42.889539 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6562 22:16:42.892505 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6563 22:16:42.896252 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6564 22:16:42.902638 iDelay=217, Bit 4, Center -36 (-271 ~ 200) 472
6565 22:16:42.905737 iDelay=217, Bit 5, Center -44 (-279 ~ 192) 472
6566 22:16:42.909766 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6567 22:16:42.912783 iDelay=217, Bit 7, Center -32 (-271 ~ 208) 480
6568 22:16:42.918892 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6569 22:16:42.922488 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
6570 22:16:42.925593 iDelay=217, Bit 10, Center -40 (-279 ~ 200) 480
6571 22:16:42.928621 iDelay=217, Bit 11, Center -56 (-295 ~ 184) 480
6572 22:16:42.935392 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6573 22:16:42.938897 iDelay=217, Bit 13, Center -40 (-279 ~ 200) 480
6574 22:16:42.942269 iDelay=217, Bit 14, Center -32 (-271 ~ 208) 480
6575 22:16:42.945936 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6576 22:16:42.949028 ==
6577 22:16:42.952266 Dram Type= 6, Freq= 0, CH_0, rank 1
6578 22:16:42.955301 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6579 22:16:42.955720 ==
6580 22:16:42.956109 DQS Delay:
6581 22:16:42.959205 DQS0 = 44, DQS1 = 60
6582 22:16:42.959621 DQM Delay:
6583 22:16:42.961839 DQM0 = 9, DQM1 = 14
6584 22:16:42.962254 DQ Delay:
6585 22:16:42.965412 DQ0 =12, DQ1 =12, DQ2 =4, DQ3 =8
6586 22:16:42.969083 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =12
6587 22:16:42.972259 DQ8 =0, DQ9 =4, DQ10 =20, DQ11 =4
6588 22:16:42.975731 DQ12 =16, DQ13 =20, DQ14 =28, DQ15 =24
6589 22:16:42.976312
6590 22:16:42.976661
6591 22:16:42.982118 [DQSOSCAuto] RK1, (LSB)MR18= 0x9669, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 391 ps
6592 22:16:42.985220 CH0 RK1: MR19=C0C, MR18=9669
6593 22:16:42.991864 CH0_RK1: MR19=0xC0C, MR18=0x9669, DQSOSC=391, MR23=63, INC=386, DEC=257
6594 22:16:42.995514 [RxdqsGatingPostProcess] freq 400
6595 22:16:42.998904 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6596 22:16:43.002154 best DQS0 dly(2T, 0.5T) = (0, 10)
6597 22:16:43.005178 best DQS1 dly(2T, 0.5T) = (0, 10)
6598 22:16:43.008592 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6599 22:16:43.011627 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6600 22:16:43.015523 best DQS0 dly(2T, 0.5T) = (0, 10)
6601 22:16:43.018509 best DQS1 dly(2T, 0.5T) = (0, 10)
6602 22:16:43.021990 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6603 22:16:43.025224 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6604 22:16:43.028773 Pre-setting of DQS Precalculation
6605 22:16:43.032245 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6606 22:16:43.032663 ==
6607 22:16:43.035267 Dram Type= 6, Freq= 0, CH_1, rank 0
6608 22:16:43.042020 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6609 22:16:43.042443 ==
6610 22:16:43.045329 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6611 22:16:43.052108 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6612 22:16:43.054964 [CA 0] Center 36 (8~64) winsize 57
6613 22:16:43.059149 [CA 1] Center 36 (8~64) winsize 57
6614 22:16:43.062465 [CA 2] Center 36 (8~64) winsize 57
6615 22:16:43.064968 [CA 3] Center 36 (8~64) winsize 57
6616 22:16:43.068487 [CA 4] Center 36 (8~64) winsize 57
6617 22:16:43.071624 [CA 5] Center 36 (8~64) winsize 57
6618 22:16:43.072194
6619 22:16:43.075197 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6620 22:16:43.075614
6621 22:16:43.079260 [CATrainingPosCal] consider 1 rank data
6622 22:16:43.081958 u2DelayCellTimex100 = 270/100 ps
6623 22:16:43.084957 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6624 22:16:43.088590 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6625 22:16:43.091353 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6626 22:16:43.095127 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6627 22:16:43.098208 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6628 22:16:43.104514 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6629 22:16:43.104935
6630 22:16:43.108036 CA PerBit enable=1, Macro0, CA PI delay=36
6631 22:16:43.108477
6632 22:16:43.111583 [CBTSetCACLKResult] CA Dly = 36
6633 22:16:43.112030 CS Dly: 1 (0~32)
6634 22:16:43.112370 ==
6635 22:16:43.114848 Dram Type= 6, Freq= 0, CH_1, rank 1
6636 22:16:43.118023 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6637 22:16:43.121272 ==
6638 22:16:43.124868 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6639 22:16:43.131416 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6640 22:16:43.134543 [CA 0] Center 36 (8~64) winsize 57
6641 22:16:43.138064 [CA 1] Center 36 (8~64) winsize 57
6642 22:16:43.141224 [CA 2] Center 36 (8~64) winsize 57
6643 22:16:43.144813 [CA 3] Center 36 (8~64) winsize 57
6644 22:16:43.148235 [CA 4] Center 36 (8~64) winsize 57
6645 22:16:43.151226 [CA 5] Center 36 (8~64) winsize 57
6646 22:16:43.151645
6647 22:16:43.154417 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6648 22:16:43.154853
6649 22:16:43.158313 [CATrainingPosCal] consider 2 rank data
6650 22:16:43.161205 u2DelayCellTimex100 = 270/100 ps
6651 22:16:43.164859 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6652 22:16:43.168047 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6653 22:16:43.171122 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6654 22:16:43.175255 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6655 22:16:43.177514 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6656 22:16:43.181223 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6657 22:16:43.181643
6658 22:16:43.184524 CA PerBit enable=1, Macro0, CA PI delay=36
6659 22:16:43.187721
6660 22:16:43.188181 [CBTSetCACLKResult] CA Dly = 36
6661 22:16:43.191145 CS Dly: 1 (0~32)
6662 22:16:43.191586
6663 22:16:43.194470 ----->DramcWriteLeveling(PI) begin...
6664 22:16:43.194908 ==
6665 22:16:43.198095 Dram Type= 6, Freq= 0, CH_1, rank 0
6666 22:16:43.201212 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6667 22:16:43.201631 ==
6668 22:16:43.204407 Write leveling (Byte 0): 40 => 8
6669 22:16:43.207796 Write leveling (Byte 1): 40 => 8
6670 22:16:43.211144 DramcWriteLeveling(PI) end<-----
6671 22:16:43.211562
6672 22:16:43.211893 ==
6673 22:16:43.214702 Dram Type= 6, Freq= 0, CH_1, rank 0
6674 22:16:43.217823 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6675 22:16:43.218422 ==
6676 22:16:43.221420 [Gating] SW mode calibration
6677 22:16:43.228022 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6678 22:16:43.234454 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6679 22:16:43.237448 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6680 22:16:43.245086 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6681 22:16:43.247510 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6682 22:16:43.251016 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6683 22:16:43.257381 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6684 22:16:43.260660 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6685 22:16:43.264253 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6686 22:16:43.271386 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6687 22:16:43.274618 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6688 22:16:43.277546 Total UI for P1: 0, mck2ui 16
6689 22:16:43.280743 best dqsien dly found for B0: ( 0, 14, 24)
6690 22:16:43.284640 Total UI for P1: 0, mck2ui 16
6691 22:16:43.287337 best dqsien dly found for B1: ( 0, 14, 24)
6692 22:16:43.290763 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6693 22:16:43.294086 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6694 22:16:43.294606
6695 22:16:43.297106 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6696 22:16:43.300364 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6697 22:16:43.304250 [Gating] SW calibration Done
6698 22:16:43.304822 ==
6699 22:16:43.307172 Dram Type= 6, Freq= 0, CH_1, rank 0
6700 22:16:43.309996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6701 22:16:43.313332 ==
6702 22:16:43.313950 RX Vref Scan: 0
6703 22:16:43.314469
6704 22:16:43.316631 RX Vref 0 -> 0, step: 1
6705 22:16:43.317118
6706 22:16:43.320063 RX Delay -410 -> 252, step: 16
6707 22:16:43.323259 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6708 22:16:43.326882 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6709 22:16:43.329966 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6710 22:16:43.337322 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6711 22:16:43.340406 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6712 22:16:43.343368 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6713 22:16:43.346852 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6714 22:16:43.353323 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6715 22:16:43.356942 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6716 22:16:43.360006 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6717 22:16:43.363712 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6718 22:16:43.369823 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6719 22:16:43.373330 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6720 22:16:43.376233 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6721 22:16:43.383416 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6722 22:16:43.387122 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6723 22:16:43.387545 ==
6724 22:16:43.389877 Dram Type= 6, Freq= 0, CH_1, rank 0
6725 22:16:43.393040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6726 22:16:43.393466 ==
6727 22:16:43.396194 DQS Delay:
6728 22:16:43.396614 DQS0 = 51, DQS1 = 59
6729 22:16:43.396950 DQM Delay:
6730 22:16:43.399861 DQM0 = 19, DQM1 = 17
6731 22:16:43.400323 DQ Delay:
6732 22:16:43.403348 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6733 22:16:43.406253 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6734 22:16:43.409769 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6735 22:16:43.412957 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6736 22:16:43.413378
6737 22:16:43.413712
6738 22:16:43.414024 ==
6739 22:16:43.416637 Dram Type= 6, Freq= 0, CH_1, rank 0
6740 22:16:43.419994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6741 22:16:43.423160 ==
6742 22:16:43.423672
6743 22:16:43.424062
6744 22:16:43.424388 TX Vref Scan disable
6745 22:16:43.426800 == TX Byte 0 ==
6746 22:16:43.429650 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6747 22:16:43.433256 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6748 22:16:43.436539 == TX Byte 1 ==
6749 22:16:43.439889 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6750 22:16:43.443147 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6751 22:16:43.443664 ==
6752 22:16:43.446653 Dram Type= 6, Freq= 0, CH_1, rank 0
6753 22:16:43.452849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6754 22:16:43.453276 ==
6755 22:16:43.453612
6756 22:16:43.453926
6757 22:16:43.454225 TX Vref Scan disable
6758 22:16:43.456182 == TX Byte 0 ==
6759 22:16:43.459567 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6760 22:16:43.462919 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6761 22:16:43.466384 == TX Byte 1 ==
6762 22:16:43.469672 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6763 22:16:43.473236 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6764 22:16:43.473657
6765 22:16:43.476583 [DATLAT]
6766 22:16:43.477004 Freq=400, CH1 RK0
6767 22:16:43.477342
6768 22:16:43.479823 DATLAT Default: 0xf
6769 22:16:43.480272 0, 0xFFFF, sum = 0
6770 22:16:43.483094 1, 0xFFFF, sum = 0
6771 22:16:43.483523 2, 0xFFFF, sum = 0
6772 22:16:43.486339 3, 0xFFFF, sum = 0
6773 22:16:43.486766 4, 0xFFFF, sum = 0
6774 22:16:43.490506 5, 0xFFFF, sum = 0
6775 22:16:43.491035 6, 0xFFFF, sum = 0
6776 22:16:43.493214 7, 0xFFFF, sum = 0
6777 22:16:43.493643 8, 0xFFFF, sum = 0
6778 22:16:43.496538 9, 0xFFFF, sum = 0
6779 22:16:43.497069 10, 0xFFFF, sum = 0
6780 22:16:43.499348 11, 0xFFFF, sum = 0
6781 22:16:43.499776 12, 0xFFFF, sum = 0
6782 22:16:43.503369 13, 0x0, sum = 1
6783 22:16:43.503800 14, 0x0, sum = 2
6784 22:16:43.506143 15, 0x0, sum = 3
6785 22:16:43.506573 16, 0x0, sum = 4
6786 22:16:43.509760 best_step = 14
6787 22:16:43.510182
6788 22:16:43.510515 ==
6789 22:16:43.512440 Dram Type= 6, Freq= 0, CH_1, rank 0
6790 22:16:43.516094 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6791 22:16:43.516517 ==
6792 22:16:43.519610 RX Vref Scan: 1
6793 22:16:43.520058
6794 22:16:43.520396 RX Vref 0 -> 0, step: 1
6795 22:16:43.520710
6796 22:16:43.522857 RX Delay -359 -> 252, step: 8
6797 22:16:43.523280
6798 22:16:43.526110 Set Vref, RX VrefLevel [Byte0]: 58
6799 22:16:43.529435 [Byte1]: 52
6800 22:16:43.534361
6801 22:16:43.534892 Final RX Vref Byte 0 = 58 to rank0
6802 22:16:43.538029 Final RX Vref Byte 1 = 52 to rank0
6803 22:16:43.541003 Final RX Vref Byte 0 = 58 to rank1
6804 22:16:43.544056 Final RX Vref Byte 1 = 52 to rank1==
6805 22:16:43.547399 Dram Type= 6, Freq= 0, CH_1, rank 0
6806 22:16:43.554250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6807 22:16:43.554677 ==
6808 22:16:43.555012 DQS Delay:
6809 22:16:43.558744 DQS0 = 48, DQS1 = 60
6810 22:16:43.559166 DQM Delay:
6811 22:16:43.559501 DQM0 = 12, DQM1 = 13
6812 22:16:43.560675 DQ Delay:
6813 22:16:43.564151 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6814 22:16:43.564570 DQ4 =8, DQ5 =20, DQ6 =24, DQ7 =8
6815 22:16:43.567778 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =8
6816 22:16:43.570825 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6817 22:16:43.571248
6818 22:16:43.571577
6819 22:16:43.581332 [DQSOSCAuto] RK0, (LSB)MR18= 0x8931, (MSB)MR19= 0xc0c, tDQSOscB0 = 403 ps tDQSOscB1 = 392 ps
6820 22:16:43.584419 CH1 RK0: MR19=C0C, MR18=8931
6821 22:16:43.590621 CH1_RK0: MR19=0xC0C, MR18=0x8931, DQSOSC=392, MR23=63, INC=384, DEC=256
6822 22:16:43.590705 ==
6823 22:16:43.593494 Dram Type= 6, Freq= 0, CH_1, rank 1
6824 22:16:43.596742 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6825 22:16:43.596826 ==
6826 22:16:43.600464 [Gating] SW mode calibration
6827 22:16:43.607224 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6828 22:16:43.613309 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6829 22:16:43.616636 0 11 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
6830 22:16:43.619858 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6831 22:16:43.627014 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6832 22:16:43.630320 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6833 22:16:43.633541 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6834 22:16:43.637163 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6835 22:16:43.643516 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6836 22:16:43.646698 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6837 22:16:43.650010 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6838 22:16:43.653357 Total UI for P1: 0, mck2ui 16
6839 22:16:43.656617 best dqsien dly found for B0: ( 0, 14, 24)
6840 22:16:43.659774 Total UI for P1: 0, mck2ui 16
6841 22:16:43.663536 best dqsien dly found for B1: ( 0, 14, 24)
6842 22:16:43.666615 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6843 22:16:43.673458 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6844 22:16:43.673659
6845 22:16:43.676436 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6846 22:16:43.679805 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6847 22:16:43.683780 [Gating] SW calibration Done
6848 22:16:43.684110 ==
6849 22:16:43.686788 Dram Type= 6, Freq= 0, CH_1, rank 1
6850 22:16:43.689993 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6851 22:16:43.690383 ==
6852 22:16:43.693171 RX Vref Scan: 0
6853 22:16:43.693593
6854 22:16:43.693924 RX Vref 0 -> 0, step: 1
6855 22:16:43.694239
6856 22:16:43.696376 RX Delay -410 -> 252, step: 16
6857 22:16:43.700529 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6858 22:16:43.707194 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6859 22:16:43.710124 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6860 22:16:43.713803 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6861 22:16:43.716385 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6862 22:16:43.723806 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6863 22:16:43.726946 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6864 22:16:43.730249 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6865 22:16:43.732903 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6866 22:16:43.739822 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6867 22:16:43.743106 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6868 22:16:43.746669 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6869 22:16:43.749648 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6870 22:16:43.756514 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6871 22:16:43.759512 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6872 22:16:43.762818 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6873 22:16:43.763242 ==
6874 22:16:43.766033 Dram Type= 6, Freq= 0, CH_1, rank 1
6875 22:16:43.772583 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6876 22:16:43.773079 ==
6877 22:16:43.773546 DQS Delay:
6878 22:16:43.776486 DQS0 = 51, DQS1 = 59
6879 22:16:43.776908 DQM Delay:
6880 22:16:43.779201 DQM0 = 17, DQM1 = 19
6881 22:16:43.779621 DQ Delay:
6882 22:16:43.782591 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =16
6883 22:16:43.786484 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6884 22:16:43.789830 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6885 22:16:43.792605 DQ12 =24, DQ13 =32, DQ14 =32, DQ15 =32
6886 22:16:43.793057
6887 22:16:43.793402
6888 22:16:43.793715 ==
6889 22:16:43.796173 Dram Type= 6, Freq= 0, CH_1, rank 1
6890 22:16:43.799774 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6891 22:16:43.800229 ==
6892 22:16:43.800566
6893 22:16:43.800880
6894 22:16:43.802816 TX Vref Scan disable
6895 22:16:43.803331 == TX Byte 0 ==
6896 22:16:43.809235 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6897 22:16:43.813151 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6898 22:16:43.813586 == TX Byte 1 ==
6899 22:16:43.816237 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6900 22:16:43.822472 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6901 22:16:43.822896 ==
6902 22:16:43.826379 Dram Type= 6, Freq= 0, CH_1, rank 1
6903 22:16:43.829193 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6904 22:16:43.829619 ==
6905 22:16:43.829956
6906 22:16:43.830266
6907 22:16:43.832493 TX Vref Scan disable
6908 22:16:43.832915 == TX Byte 0 ==
6909 22:16:43.839058 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6910 22:16:43.842676 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6911 22:16:43.843101 == TX Byte 1 ==
6912 22:16:43.849109 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6913 22:16:43.852173 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6914 22:16:43.852593
6915 22:16:43.852926 [DATLAT]
6916 22:16:43.855812 Freq=400, CH1 RK1
6917 22:16:43.856271
6918 22:16:43.856607 DATLAT Default: 0xe
6919 22:16:43.858950 0, 0xFFFF, sum = 0
6920 22:16:43.859379 1, 0xFFFF, sum = 0
6921 22:16:43.862166 2, 0xFFFF, sum = 0
6922 22:16:43.862594 3, 0xFFFF, sum = 0
6923 22:16:43.865732 4, 0xFFFF, sum = 0
6924 22:16:43.866157 5, 0xFFFF, sum = 0
6925 22:16:43.869315 6, 0xFFFF, sum = 0
6926 22:16:43.869741 7, 0xFFFF, sum = 0
6927 22:16:43.872488 8, 0xFFFF, sum = 0
6928 22:16:43.872915 9, 0xFFFF, sum = 0
6929 22:16:43.875680 10, 0xFFFF, sum = 0
6930 22:16:43.876142 11, 0xFFFF, sum = 0
6931 22:16:43.880013 12, 0xFFFF, sum = 0
6932 22:16:43.880697 13, 0x0, sum = 1
6933 22:16:43.882555 14, 0x0, sum = 2
6934 22:16:43.882981 15, 0x0, sum = 3
6935 22:16:43.885837 16, 0x0, sum = 4
6936 22:16:43.886265 best_step = 14
6937 22:16:43.886603
6938 22:16:43.886917 ==
6939 22:16:43.888774 Dram Type= 6, Freq= 0, CH_1, rank 1
6940 22:16:43.895702 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6941 22:16:43.896150 ==
6942 22:16:43.896490 RX Vref Scan: 0
6943 22:16:43.896806
6944 22:16:43.898982 RX Vref 0 -> 0, step: 1
6945 22:16:43.899404
6946 22:16:43.902323 RX Delay -359 -> 252, step: 8
6947 22:16:43.908976 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6948 22:16:43.912428 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
6949 22:16:43.915335 iDelay=217, Bit 2, Center -52 (-295 ~ 192) 488
6950 22:16:43.918426 iDelay=217, Bit 3, Center -40 (-279 ~ 200) 480
6951 22:16:43.925279 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6952 22:16:43.928494 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6953 22:16:43.931994 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6954 22:16:43.936025 iDelay=217, Bit 7, Center -40 (-279 ~ 200) 480
6955 22:16:43.941899 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6956 22:16:43.945317 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
6957 22:16:43.948403 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6958 22:16:43.952105 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6959 22:16:43.958408 iDelay=217, Bit 12, Center -40 (-279 ~ 200) 480
6960 22:16:43.962090 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6961 22:16:43.965711 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6962 22:16:43.972389 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6963 22:16:43.972811 ==
6964 22:16:43.975109 Dram Type= 6, Freq= 0, CH_1, rank 1
6965 22:16:43.978814 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6966 22:16:43.979238 ==
6967 22:16:43.979571 DQS Delay:
6968 22:16:43.981602 DQS0 = 52, DQS1 = 56
6969 22:16:43.982023 DQM Delay:
6970 22:16:43.985620 DQM0 = 14, DQM1 = 9
6971 22:16:43.986041 DQ Delay:
6972 22:16:43.988710 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6973 22:16:43.991774 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =12
6974 22:16:43.994961 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
6975 22:16:43.998858 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6976 22:16:43.999278
6977 22:16:43.999612
6978 22:16:44.005315 [DQSOSCAuto] RK1, (LSB)MR18= 0x758a, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 395 ps
6979 22:16:44.008526 CH1 RK1: MR19=C0C, MR18=758A
6980 22:16:44.015310 CH1_RK1: MR19=0xC0C, MR18=0x758A, DQSOSC=392, MR23=63, INC=384, DEC=256
6981 22:16:44.019076 [RxdqsGatingPostProcess] freq 400
6982 22:16:44.025204 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6983 22:16:44.025635 best DQS0 dly(2T, 0.5T) = (0, 10)
6984 22:16:44.028567 best DQS1 dly(2T, 0.5T) = (0, 10)
6985 22:16:44.031823 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6986 22:16:44.034886 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6987 22:16:44.038691 best DQS0 dly(2T, 0.5T) = (0, 10)
6988 22:16:44.041898 best DQS1 dly(2T, 0.5T) = (0, 10)
6989 22:16:44.045045 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6990 22:16:44.048063 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6991 22:16:44.051239 Pre-setting of DQS Precalculation
6992 22:16:44.058407 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6993 22:16:44.064758 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6994 22:16:44.071308 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6995 22:16:44.071733
6996 22:16:44.072106
6997 22:16:44.074953 [Calibration Summary] 800 Mbps
6998 22:16:44.075374 CH 0, Rank 0
6999 22:16:44.078452 SW Impedance : PASS
7000 22:16:44.078872 DUTY Scan : NO K
7001 22:16:44.081662 ZQ Calibration : PASS
7002 22:16:44.084640 Jitter Meter : NO K
7003 22:16:44.085060 CBT Training : PASS
7004 22:16:44.088051 Write leveling : PASS
7005 22:16:44.091427 RX DQS gating : PASS
7006 22:16:44.091948 RX DQ/DQS(RDDQC) : PASS
7007 22:16:44.094672 TX DQ/DQS : PASS
7008 22:16:44.098604 RX DATLAT : PASS
7009 22:16:44.099199 RX DQ/DQS(Engine): PASS
7010 22:16:44.101738 TX OE : NO K
7011 22:16:44.102263 All Pass.
7012 22:16:44.102600
7013 22:16:44.104813 CH 0, Rank 1
7014 22:16:44.105233 SW Impedance : PASS
7015 22:16:44.108166 DUTY Scan : NO K
7016 22:16:44.111341 ZQ Calibration : PASS
7017 22:16:44.111764 Jitter Meter : NO K
7018 22:16:44.114670 CBT Training : PASS
7019 22:16:44.118935 Write leveling : NO K
7020 22:16:44.119354 RX DQS gating : PASS
7021 22:16:44.121697 RX DQ/DQS(RDDQC) : PASS
7022 22:16:44.124581 TX DQ/DQS : PASS
7023 22:16:44.125002 RX DATLAT : PASS
7024 22:16:44.127695 RX DQ/DQS(Engine): PASS
7025 22:16:44.131569 TX OE : NO K
7026 22:16:44.132008 All Pass.
7027 22:16:44.132347
7028 22:16:44.132664 CH 1, Rank 0
7029 22:16:44.134117 SW Impedance : PASS
7030 22:16:44.137868 DUTY Scan : NO K
7031 22:16:44.138289 ZQ Calibration : PASS
7032 22:16:44.140918 Jitter Meter : NO K
7033 22:16:44.141339 CBT Training : PASS
7034 22:16:44.144391 Write leveling : PASS
7035 22:16:44.148016 RX DQS gating : PASS
7036 22:16:44.148502 RX DQ/DQS(RDDQC) : PASS
7037 22:16:44.150763 TX DQ/DQS : PASS
7038 22:16:44.154394 RX DATLAT : PASS
7039 22:16:44.154812 RX DQ/DQS(Engine): PASS
7040 22:16:44.157493 TX OE : NO K
7041 22:16:44.157917 All Pass.
7042 22:16:44.158253
7043 22:16:44.161226 CH 1, Rank 1
7044 22:16:44.161645 SW Impedance : PASS
7045 22:16:44.163904 DUTY Scan : NO K
7046 22:16:44.167691 ZQ Calibration : PASS
7047 22:16:44.168262 Jitter Meter : NO K
7048 22:16:44.171210 CBT Training : PASS
7049 22:16:44.173984 Write leveling : NO K
7050 22:16:44.174405 RX DQS gating : PASS
7051 22:16:44.177291 RX DQ/DQS(RDDQC) : PASS
7052 22:16:44.180703 TX DQ/DQS : PASS
7053 22:16:44.181128 RX DATLAT : PASS
7054 22:16:44.184160 RX DQ/DQS(Engine): PASS
7055 22:16:44.184582 TX OE : NO K
7056 22:16:44.187361 All Pass.
7057 22:16:44.187775
7058 22:16:44.188168 DramC Write-DBI off
7059 22:16:44.191021 PER_BANK_REFRESH: Hybrid Mode
7060 22:16:44.194118 TX_TRACKING: ON
7061 22:16:44.200374 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7062 22:16:44.204012 [FAST_K] Save calibration result to emmc
7063 22:16:44.211201 dramc_set_vcore_voltage set vcore to 725000
7064 22:16:44.211622 Read voltage for 1600, 0
7065 22:16:44.213839 Vio18 = 0
7066 22:16:44.214257 Vcore = 725000
7067 22:16:44.214592 Vdram = 0
7068 22:16:44.217267 Vddq = 0
7069 22:16:44.217689 Vmddr = 0
7070 22:16:44.220776 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7071 22:16:44.227324 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7072 22:16:44.230460 MEM_TYPE=3, freq_sel=13
7073 22:16:44.230930 sv_algorithm_assistance_LP4_3733
7074 22:16:44.237166 ============ PULL DRAM RESETB DOWN ============
7075 22:16:44.240225 ========== PULL DRAM RESETB DOWN end =========
7076 22:16:44.243831 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7077 22:16:44.246873 ===================================
7078 22:16:44.250710 LPDDR4 DRAM CONFIGURATION
7079 22:16:44.253835 ===================================
7080 22:16:44.257418 EX_ROW_EN[0] = 0x0
7081 22:16:44.257832 EX_ROW_EN[1] = 0x0
7082 22:16:44.260409 LP4Y_EN = 0x0
7083 22:16:44.260873 WORK_FSP = 0x1
7084 22:16:44.264056 WL = 0x5
7085 22:16:44.264471 RL = 0x5
7086 22:16:44.267236 BL = 0x2
7087 22:16:44.267696 RPST = 0x0
7088 22:16:44.270406 RD_PRE = 0x0
7089 22:16:44.270820 WR_PRE = 0x1
7090 22:16:44.273649 WR_PST = 0x1
7091 22:16:44.277219 DBI_WR = 0x0
7092 22:16:44.277692 DBI_RD = 0x0
7093 22:16:44.280180 OTF = 0x1
7094 22:16:44.283504 ===================================
7095 22:16:44.286727 ===================================
7096 22:16:44.287140 ANA top config
7097 22:16:44.289764 ===================================
7098 22:16:44.293244 DLL_ASYNC_EN = 0
7099 22:16:44.293706 ALL_SLAVE_EN = 0
7100 22:16:44.296690 NEW_RANK_MODE = 1
7101 22:16:44.299689 DLL_IDLE_MODE = 1
7102 22:16:44.304062 LP45_APHY_COMB_EN = 1
7103 22:16:44.306533 TX_ODT_DIS = 0
7104 22:16:44.306949 NEW_8X_MODE = 1
7105 22:16:44.310257 ===================================
7106 22:16:44.313565 ===================================
7107 22:16:44.316898 data_rate = 3200
7108 22:16:44.319706 CKR = 1
7109 22:16:44.323407 DQ_P2S_RATIO = 8
7110 22:16:44.326493 ===================================
7111 22:16:44.330305 CA_P2S_RATIO = 8
7112 22:16:44.333355 DQ_CA_OPEN = 0
7113 22:16:44.333772 DQ_SEMI_OPEN = 0
7114 22:16:44.336382 CA_SEMI_OPEN = 0
7115 22:16:44.340074 CA_FULL_RATE = 0
7116 22:16:44.343180 DQ_CKDIV4_EN = 0
7117 22:16:44.346232 CA_CKDIV4_EN = 0
7118 22:16:44.349603 CA_PREDIV_EN = 0
7119 22:16:44.350043 PH8_DLY = 12
7120 22:16:44.353398 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7121 22:16:44.356506 DQ_AAMCK_DIV = 4
7122 22:16:44.360071 CA_AAMCK_DIV = 4
7123 22:16:44.362960 CA_ADMCK_DIV = 4
7124 22:16:44.366472 DQ_TRACK_CA_EN = 0
7125 22:16:44.366926 CA_PICK = 1600
7126 22:16:44.369518 CA_MCKIO = 1600
7127 22:16:44.373197 MCKIO_SEMI = 0
7128 22:16:44.376421 PLL_FREQ = 3068
7129 22:16:44.379678 DQ_UI_PI_RATIO = 32
7130 22:16:44.382953 CA_UI_PI_RATIO = 0
7131 22:16:44.386379 ===================================
7132 22:16:44.389738 ===================================
7133 22:16:44.392730 memory_type:LPDDR4
7134 22:16:44.393154 GP_NUM : 10
7135 22:16:44.396128 SRAM_EN : 1
7136 22:16:44.396612 MD32_EN : 0
7137 22:16:44.399803 ===================================
7138 22:16:44.402676 [ANA_INIT] >>>>>>>>>>>>>>
7139 22:16:44.406075 <<<<<< [CONFIGURE PHASE]: ANA_TX
7140 22:16:44.409663 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7141 22:16:44.412886 ===================================
7142 22:16:44.416566 data_rate = 3200,PCW = 0X7600
7143 22:16:44.419809 ===================================
7144 22:16:44.423430 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7145 22:16:44.426432 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7146 22:16:44.432873 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7147 22:16:44.436106 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7148 22:16:44.442867 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7149 22:16:44.446384 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7150 22:16:44.446854 [ANA_INIT] flow start
7151 22:16:44.449173 [ANA_INIT] PLL >>>>>>>>
7152 22:16:44.452766 [ANA_INIT] PLL <<<<<<<<
7153 22:16:44.453193 [ANA_INIT] MIDPI >>>>>>>>
7154 22:16:44.456476 [ANA_INIT] MIDPI <<<<<<<<
7155 22:16:44.459298 [ANA_INIT] DLL >>>>>>>>
7156 22:16:44.459723 [ANA_INIT] DLL <<<<<<<<
7157 22:16:44.462798 [ANA_INIT] flow end
7158 22:16:44.466066 ============ LP4 DIFF to SE enter ============
7159 22:16:44.469209 ============ LP4 DIFF to SE exit ============
7160 22:16:44.472349 [ANA_INIT] <<<<<<<<<<<<<
7161 22:16:44.475631 [Flow] Enable top DCM control >>>>>
7162 22:16:44.479027 [Flow] Enable top DCM control <<<<<
7163 22:16:44.482228 Enable DLL master slave shuffle
7164 22:16:44.489219 ==============================================================
7165 22:16:44.489642 Gating Mode config
7166 22:16:44.496203 ==============================================================
7167 22:16:44.496633 Config description:
7168 22:16:44.506238 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7169 22:16:44.512499 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7170 22:16:44.519102 SELPH_MODE 0: By rank 1: By Phase
7171 22:16:44.522649 ==============================================================
7172 22:16:44.526066 GAT_TRACK_EN = 1
7173 22:16:44.528969 RX_GATING_MODE = 2
7174 22:16:44.532697 RX_GATING_TRACK_MODE = 2
7175 22:16:44.536096 SELPH_MODE = 1
7176 22:16:44.538847 PICG_EARLY_EN = 1
7177 22:16:44.541846 VALID_LAT_VALUE = 1
7178 22:16:44.548796 ==============================================================
7179 22:16:44.552122 Enter into Gating configuration >>>>
7180 22:16:44.555396 Exit from Gating configuration <<<<
7181 22:16:44.559097 Enter into DVFS_PRE_config >>>>>
7182 22:16:44.568978 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7183 22:16:44.572103 Exit from DVFS_PRE_config <<<<<
7184 22:16:44.575150 Enter into PICG configuration >>>>
7185 22:16:44.578752 Exit from PICG configuration <<<<
7186 22:16:44.579173 [RX_INPUT] configuration >>>>>
7187 22:16:44.581845 [RX_INPUT] configuration <<<<<
7188 22:16:44.588640 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7189 22:16:44.595108 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7190 22:16:44.598548 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7191 22:16:44.605327 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7192 22:16:44.612004 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7193 22:16:44.618458 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7194 22:16:44.621752 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7195 22:16:44.625372 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7196 22:16:44.632060 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7197 22:16:44.635013 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7198 22:16:44.638167 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7199 22:16:44.642099 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7200 22:16:44.645364 ===================================
7201 22:16:44.648464 LPDDR4 DRAM CONFIGURATION
7202 22:16:44.651754 ===================================
7203 22:16:44.655134 EX_ROW_EN[0] = 0x0
7204 22:16:44.655551 EX_ROW_EN[1] = 0x0
7205 22:16:44.658761 LP4Y_EN = 0x0
7206 22:16:44.659182 WORK_FSP = 0x1
7207 22:16:44.662201 WL = 0x5
7208 22:16:44.662620 RL = 0x5
7209 22:16:44.664909 BL = 0x2
7210 22:16:44.665329 RPST = 0x0
7211 22:16:44.668390 RD_PRE = 0x0
7212 22:16:44.668808 WR_PRE = 0x1
7213 22:16:44.671575 WR_PST = 0x1
7214 22:16:44.674847 DBI_WR = 0x0
7215 22:16:44.675268 DBI_RD = 0x0
7216 22:16:44.678519 OTF = 0x1
7217 22:16:44.681601 ===================================
7218 22:16:44.684950 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7219 22:16:44.688588 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7220 22:16:44.691344 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7221 22:16:44.694557 ===================================
7222 22:16:44.697589 LPDDR4 DRAM CONFIGURATION
7223 22:16:44.701372 ===================================
7224 22:16:44.704189 EX_ROW_EN[0] = 0x10
7225 22:16:44.704272 EX_ROW_EN[1] = 0x0
7226 22:16:44.708104 LP4Y_EN = 0x0
7227 22:16:44.708194 WORK_FSP = 0x1
7228 22:16:44.711359 WL = 0x5
7229 22:16:44.711449 RL = 0x5
7230 22:16:44.714589 BL = 0x2
7231 22:16:44.714685 RPST = 0x0
7232 22:16:44.717758 RD_PRE = 0x0
7233 22:16:44.717862 WR_PRE = 0x1
7234 22:16:44.720860 WR_PST = 0x1
7235 22:16:44.724249 DBI_WR = 0x0
7236 22:16:44.724362 DBI_RD = 0x0
7237 22:16:44.727496 OTF = 0x1
7238 22:16:44.730737 ===================================
7239 22:16:44.734201 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7240 22:16:44.737804 ==
7241 22:16:44.737960 Dram Type= 6, Freq= 0, CH_0, rank 0
7242 22:16:44.744156 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7243 22:16:44.744335 ==
7244 22:16:44.747630 [Duty_Offset_Calibration]
7245 22:16:44.747836 B0:2 B1:-1 CA:1
7246 22:16:44.748076
7247 22:16:44.750968 [DutyScan_Calibration_Flow] k_type=0
7248 22:16:44.760444
7249 22:16:44.760749 ==CLK 0==
7250 22:16:44.763345 Final CLK duty delay cell = -4
7251 22:16:44.766618 [-4] MAX Duty = 5031%(X100), DQS PI = 22
7252 22:16:44.770108 [-4] MIN Duty = 4844%(X100), DQS PI = 32
7253 22:16:44.773548 [-4] AVG Duty = 4937%(X100)
7254 22:16:44.773977
7255 22:16:44.776683 CH0 CLK Duty spec in!! Max-Min= 187%
7256 22:16:44.780169 [DutyScan_Calibration_Flow] ====Done====
7257 22:16:44.780603
7258 22:16:44.783345 [DutyScan_Calibration_Flow] k_type=1
7259 22:16:44.799500
7260 22:16:44.799930 ==DQS 0 ==
7261 22:16:44.803289 Final DQS duty delay cell = 0
7262 22:16:44.806268 [0] MAX Duty = 5125%(X100), DQS PI = 20
7263 22:16:44.809256 [0] MIN Duty = 5000%(X100), DQS PI = 14
7264 22:16:44.812947 [0] AVG Duty = 5062%(X100)
7265 22:16:44.813424
7266 22:16:44.813854 ==DQS 1 ==
7267 22:16:44.816616 Final DQS duty delay cell = -4
7268 22:16:44.819776 [-4] MAX Duty = 5093%(X100), DQS PI = 0
7269 22:16:44.822536 [-4] MIN Duty = 5031%(X100), DQS PI = 6
7270 22:16:44.826048 [-4] AVG Duty = 5062%(X100)
7271 22:16:44.826482
7272 22:16:44.829351 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7273 22:16:44.829782
7274 22:16:44.832722 CH0 DQS 1 Duty spec in!! Max-Min= 62%
7275 22:16:44.835899 [DutyScan_Calibration_Flow] ====Done====
7276 22:16:44.836359
7277 22:16:44.839368 [DutyScan_Calibration_Flow] k_type=3
7278 22:16:44.856896
7279 22:16:44.857348 ==DQM 0 ==
7280 22:16:44.860077 Final DQM duty delay cell = 0
7281 22:16:44.863827 [0] MAX Duty = 5000%(X100), DQS PI = 20
7282 22:16:44.866762 [0] MIN Duty = 4875%(X100), DQS PI = 6
7283 22:16:44.870038 [0] AVG Duty = 4937%(X100)
7284 22:16:44.870461
7285 22:16:44.870796 ==DQM 1 ==
7286 22:16:44.873398 Final DQM duty delay cell = 0
7287 22:16:44.877003 [0] MAX Duty = 5218%(X100), DQS PI = 58
7288 22:16:44.879885 [0] MIN Duty = 4969%(X100), DQS PI = 18
7289 22:16:44.883253 [0] AVG Duty = 5093%(X100)
7290 22:16:44.883673
7291 22:16:44.887172 CH0 DQM 0 Duty spec in!! Max-Min= 125%
7292 22:16:44.887761
7293 22:16:44.890062 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7294 22:16:44.893233 [DutyScan_Calibration_Flow] ====Done====
7295 22:16:44.893666
7296 22:16:44.896603 [DutyScan_Calibration_Flow] k_type=2
7297 22:16:44.913400
7298 22:16:44.913828 ==DQ 0 ==
7299 22:16:44.916502 Final DQ duty delay cell = -4
7300 22:16:44.919692 [-4] MAX Duty = 5062%(X100), DQS PI = 56
7301 22:16:44.923642 [-4] MIN Duty = 4844%(X100), DQS PI = 28
7302 22:16:44.926815 [-4] AVG Duty = 4953%(X100)
7303 22:16:44.927307
7304 22:16:44.927751 ==DQ 1 ==
7305 22:16:44.930168 Final DQ duty delay cell = 0
7306 22:16:44.933010 [0] MAX Duty = 5031%(X100), DQS PI = 30
7307 22:16:44.936328 [0] MIN Duty = 4907%(X100), DQS PI = 18
7308 22:16:44.939935 [0] AVG Duty = 4969%(X100)
7309 22:16:44.940432
7310 22:16:44.943135 CH0 DQ 0 Duty spec in!! Max-Min= 218%
7311 22:16:44.943546
7312 22:16:44.946466 CH0 DQ 1 Duty spec in!! Max-Min= 124%
7313 22:16:44.949756 [DutyScan_Calibration_Flow] ====Done====
7314 22:16:44.950192 ==
7315 22:16:44.953743 Dram Type= 6, Freq= 0, CH_1, rank 0
7316 22:16:44.956382 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7317 22:16:44.956795 ==
7318 22:16:44.959989 [Duty_Offset_Calibration]
7319 22:16:44.960419 B0:1 B1:1 CA:2
7320 22:16:44.960746
7321 22:16:44.962968 [DutyScan_Calibration_Flow] k_type=0
7322 22:16:44.974015
7323 22:16:44.974421 ==CLK 0==
7324 22:16:44.977273 Final CLK duty delay cell = 0
7325 22:16:44.981001 [0] MAX Duty = 5187%(X100), DQS PI = 24
7326 22:16:44.984233 [0] MIN Duty = 4969%(X100), DQS PI = 40
7327 22:16:44.984646 [0] AVG Duty = 5078%(X100)
7328 22:16:44.987109
7329 22:16:44.990730 CH1 CLK Duty spec in!! Max-Min= 218%
7330 22:16:44.993535 [DutyScan_Calibration_Flow] ====Done====
7331 22:16:44.993946
7332 22:16:44.996911 [DutyScan_Calibration_Flow] k_type=1
7333 22:16:45.013437
7334 22:16:45.013863 ==DQS 0 ==
7335 22:16:45.016950 Final DQS duty delay cell = 0
7336 22:16:45.020101 [0] MAX Duty = 5094%(X100), DQS PI = 20
7337 22:16:45.024028 [0] MIN Duty = 4813%(X100), DQS PI = 52
7338 22:16:45.026870 [0] AVG Duty = 4953%(X100)
7339 22:16:45.027404
7340 22:16:45.027750 ==DQS 1 ==
7341 22:16:45.030623 Final DQS duty delay cell = 0
7342 22:16:45.033452 [0] MAX Duty = 5062%(X100), DQS PI = 56
7343 22:16:45.037009 [0] MIN Duty = 4938%(X100), DQS PI = 12
7344 22:16:45.040245 [0] AVG Duty = 5000%(X100)
7345 22:16:45.040660
7346 22:16:45.043338 CH1 DQS 0 Duty spec in!! Max-Min= 281%
7347 22:16:45.043789
7348 22:16:45.046519 CH1 DQS 1 Duty spec in!! Max-Min= 124%
7349 22:16:45.049806 [DutyScan_Calibration_Flow] ====Done====
7350 22:16:45.050260
7351 22:16:45.053492 [DutyScan_Calibration_Flow] k_type=3
7352 22:16:45.070806
7353 22:16:45.071222 ==DQM 0 ==
7354 22:16:45.074059 Final DQM duty delay cell = 0
7355 22:16:45.077526 [0] MAX Duty = 5187%(X100), DQS PI = 20
7356 22:16:45.081281 [0] MIN Duty = 4844%(X100), DQS PI = 52
7357 22:16:45.084522 [0] AVG Duty = 5015%(X100)
7358 22:16:45.085056
7359 22:16:45.085529 ==DQM 1 ==
7360 22:16:45.087278 Final DQM duty delay cell = 0
7361 22:16:45.090619 [0] MAX Duty = 5125%(X100), DQS PI = 10
7362 22:16:45.094014 [0] MIN Duty = 4875%(X100), DQS PI = 22
7363 22:16:45.097119 [0] AVG Duty = 5000%(X100)
7364 22:16:45.097534
7365 22:16:45.100564 CH1 DQM 0 Duty spec in!! Max-Min= 343%
7366 22:16:45.100978
7367 22:16:45.104404 CH1 DQM 1 Duty spec in!! Max-Min= 250%
7368 22:16:45.107159 [DutyScan_Calibration_Flow] ====Done====
7369 22:16:45.107672
7370 22:16:45.110582 [DutyScan_Calibration_Flow] k_type=2
7371 22:16:45.127498
7372 22:16:45.128091 ==DQ 0 ==
7373 22:16:45.131131 Final DQ duty delay cell = 0
7374 22:16:45.134254 [0] MAX Duty = 5156%(X100), DQS PI = 20
7375 22:16:45.138231 [0] MIN Duty = 4907%(X100), DQS PI = 52
7376 22:16:45.138840 [0] AVG Duty = 5031%(X100)
7377 22:16:45.139362
7378 22:16:45.140760 ==DQ 1 ==
7379 22:16:45.144742 Final DQ duty delay cell = 0
7380 22:16:45.147302 [0] MAX Duty = 5093%(X100), DQS PI = 8
7381 22:16:45.151034 [0] MIN Duty = 5031%(X100), DQS PI = 0
7382 22:16:45.151606 [0] AVG Duty = 5062%(X100)
7383 22:16:45.152165
7384 22:16:45.154373 CH1 DQ 0 Duty spec in!! Max-Min= 249%
7385 22:16:45.154810
7386 22:16:45.157746 CH1 DQ 1 Duty spec in!! Max-Min= 62%
7387 22:16:45.164739 [DutyScan_Calibration_Flow] ====Done====
7388 22:16:45.167519 nWR fixed to 30
7389 22:16:45.168168 [ModeRegInit_LP4] CH0 RK0
7390 22:16:45.171034 [ModeRegInit_LP4] CH0 RK1
7391 22:16:45.174151 [ModeRegInit_LP4] CH1 RK0
7392 22:16:45.174697 [ModeRegInit_LP4] CH1 RK1
7393 22:16:45.177590 match AC timing 5
7394 22:16:45.180953 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7395 22:16:45.184334 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7396 22:16:45.191232 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7397 22:16:45.193818 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7398 22:16:45.200809 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7399 22:16:45.201386 [MiockJmeterHQA]
7400 22:16:45.201808
7401 22:16:45.204067 [DramcMiockJmeter] u1RxGatingPI = 0
7402 22:16:45.207563 0 : 4258, 4029
7403 22:16:45.208299 4 : 4252, 4027
7404 22:16:45.208725 8 : 4257, 4029
7405 22:16:45.210458 12 : 4253, 4027
7406 22:16:45.211011 16 : 4252, 4027
7407 22:16:45.213801 20 : 4252, 4026
7408 22:16:45.214288 24 : 4258, 4031
7409 22:16:45.217731 28 : 4363, 4137
7410 22:16:45.218310 32 : 4254, 4027
7411 22:16:45.218692 36 : 4253, 4027
7412 22:16:45.220737 40 : 4252, 4027
7413 22:16:45.221213 44 : 4252, 4027
7414 22:16:45.224673 48 : 4253, 4027
7415 22:16:45.225147 52 : 4361, 4137
7416 22:16:45.227460 56 : 4363, 4138
7417 22:16:45.228100 60 : 4250, 4027
7418 22:16:45.230862 64 : 4250, 4027
7419 22:16:45.231339 68 : 4250, 4027
7420 22:16:45.231719 72 : 4250, 4027
7421 22:16:45.234192 76 : 4255, 4031
7422 22:16:45.234665 80 : 4360, 4137
7423 22:16:45.237359 84 : 4249, 4027
7424 22:16:45.237832 88 : 4249, 4027
7425 22:16:45.240680 92 : 4250, 4027
7426 22:16:45.241133 96 : 4250, 3102
7427 22:16:45.241481 100 : 4251, 0
7428 22:16:45.244117 104 : 4250, 0
7429 22:16:45.244554 108 : 4363, 0
7430 22:16:45.247372 112 : 4360, 0
7431 22:16:45.247801 116 : 4360, 0
7432 22:16:45.248194 120 : 4250, 0
7433 22:16:45.251271 124 : 4360, 0
7434 22:16:45.251706 128 : 4250, 0
7435 22:16:45.254246 132 : 4250, 0
7436 22:16:45.254677 136 : 4250, 0
7437 22:16:45.255023 140 : 4250, 0
7438 22:16:45.257229 144 : 4250, 0
7439 22:16:45.257767 148 : 4250, 0
7440 22:16:45.260779 152 : 4249, 0
7441 22:16:45.261206 156 : 4252, 0
7442 22:16:45.261549 160 : 4361, 0
7443 22:16:45.263879 164 : 4360, 0
7444 22:16:45.264388 168 : 4360, 0
7445 22:16:45.264740 172 : 4250, 0
7446 22:16:45.267524 176 : 4361, 0
7447 22:16:45.268145 180 : 4249, 0
7448 22:16:45.270394 184 : 4250, 0
7449 22:16:45.270825 188 : 4250, 0
7450 22:16:45.271171 192 : 4250, 0
7451 22:16:45.274280 196 : 4250, 0
7452 22:16:45.274711 200 : 4250, 0
7453 22:16:45.277273 204 : 4250, 0
7454 22:16:45.277706 208 : 4252, 0
7455 22:16:45.278050 212 : 4361, 149
7456 22:16:45.280631 216 : 4360, 3824
7457 22:16:45.281061 220 : 4250, 4027
7458 22:16:45.283812 224 : 4249, 4027
7459 22:16:45.284312 228 : 4250, 4027
7460 22:16:45.287347 232 : 4252, 4029
7461 22:16:45.287871 236 : 4249, 4027
7462 22:16:45.290542 240 : 4250, 4027
7463 22:16:45.291112 244 : 4361, 4138
7464 22:16:45.294001 248 : 4250, 4027
7465 22:16:45.294433 252 : 4250, 4027
7466 22:16:45.296844 256 : 4360, 4137
7467 22:16:45.297284 260 : 4250, 4027
7468 22:16:45.297637 264 : 4250, 4027
7469 22:16:45.300396 268 : 4360, 4138
7470 22:16:45.300963 272 : 4250, 4027
7471 22:16:45.304217 276 : 4250, 4027
7472 22:16:45.304647 280 : 4250, 4026
7473 22:16:45.307153 284 : 4250, 4027
7474 22:16:45.307584 288 : 4249, 4027
7475 22:16:45.310975 292 : 4250, 4027
7476 22:16:45.311543 296 : 4360, 4137
7477 22:16:45.313915 300 : 4250, 4027
7478 22:16:45.314319 304 : 4250, 4027
7479 22:16:45.317606 308 : 4361, 4137
7480 22:16:45.318153 312 : 4250, 4027
7481 22:16:45.320077 316 : 4250, 4026
7482 22:16:45.320645 320 : 4360, 4138
7483 22:16:45.321139 324 : 4250, 4027
7484 22:16:45.323397 328 : 4250, 4027
7485 22:16:45.323845 332 : 4250, 2684
7486 22:16:45.326590 336 : 4250, 10
7487 22:16:45.327020
7488 22:16:45.330152 MIOCK jitter meter ch=0
7489 22:16:45.330573
7490 22:16:45.330910 1T = (336-100) = 236 dly cells
7491 22:16:45.337354 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7492 22:16:45.337786 ==
7493 22:16:45.340528 Dram Type= 6, Freq= 0, CH_0, rank 0
7494 22:16:45.343377 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7495 22:16:45.347098 ==
7496 22:16:45.349934 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7497 22:16:45.353186 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7498 22:16:45.359768 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7499 22:16:45.366743 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7500 22:16:45.374331 [CA 0] Center 44 (14~75) winsize 62
7501 22:16:45.377243 [CA 1] Center 44 (13~75) winsize 63
7502 22:16:45.380541 [CA 2] Center 40 (11~69) winsize 59
7503 22:16:45.383641 [CA 3] Center 39 (10~69) winsize 60
7504 22:16:45.387544 [CA 4] Center 38 (8~68) winsize 61
7505 22:16:45.390581 [CA 5] Center 37 (7~67) winsize 61
7506 22:16:45.391103
7507 22:16:45.394146 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7508 22:16:45.394586
7509 22:16:45.400524 [CATrainingPosCal] consider 1 rank data
7510 22:16:45.400944 u2DelayCellTimex100 = 275/100 ps
7511 22:16:45.407043 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7512 22:16:45.410987 CA1 delay=44 (13~75),Diff = 7 PI (24 cell)
7513 22:16:45.413579 CA2 delay=40 (11~69),Diff = 3 PI (10 cell)
7514 22:16:45.417346 CA3 delay=39 (10~69),Diff = 2 PI (7 cell)
7515 22:16:45.420559 CA4 delay=38 (8~68),Diff = 1 PI (3 cell)
7516 22:16:45.423570 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7517 22:16:45.424014
7518 22:16:45.427159 CA PerBit enable=1, Macro0, CA PI delay=37
7519 22:16:45.427673
7520 22:16:45.430343 [CBTSetCACLKResult] CA Dly = 37
7521 22:16:45.433579 CS Dly: 10 (0~41)
7522 22:16:45.437095 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7523 22:16:45.440476 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7524 22:16:45.440901 ==
7525 22:16:45.444132 Dram Type= 6, Freq= 0, CH_0, rank 1
7526 22:16:45.450674 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7527 22:16:45.451200 ==
7528 22:16:45.453587 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7529 22:16:45.459910 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7530 22:16:45.463283 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7531 22:16:45.470293 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7532 22:16:45.477945 [CA 0] Center 44 (14~75) winsize 62
7533 22:16:45.481457 [CA 1] Center 44 (14~75) winsize 62
7534 22:16:45.484442 [CA 2] Center 40 (11~69) winsize 59
7535 22:16:45.487871 [CA 3] Center 39 (10~69) winsize 60
7536 22:16:45.491093 [CA 4] Center 38 (8~68) winsize 61
7537 22:16:45.494676 [CA 5] Center 37 (7~67) winsize 61
7538 22:16:45.495114
7539 22:16:45.498375 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7540 22:16:45.498940
7541 22:16:45.501323 [CATrainingPosCal] consider 2 rank data
7542 22:16:45.504935 u2DelayCellTimex100 = 275/100 ps
7543 22:16:45.511559 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7544 22:16:45.514626 CA1 delay=44 (14~75),Diff = 7 PI (24 cell)
7545 22:16:45.517959 CA2 delay=40 (11~69),Diff = 3 PI (10 cell)
7546 22:16:45.521468 CA3 delay=39 (10~69),Diff = 2 PI (7 cell)
7547 22:16:45.524234 CA4 delay=38 (8~68),Diff = 1 PI (3 cell)
7548 22:16:45.527871 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7549 22:16:45.528493
7550 22:16:45.531527 CA PerBit enable=1, Macro0, CA PI delay=37
7551 22:16:45.532144
7552 22:16:45.534419 [CBTSetCACLKResult] CA Dly = 37
7553 22:16:45.537801 CS Dly: 11 (0~44)
7554 22:16:45.541326 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7555 22:16:45.544011 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7556 22:16:45.544488
7557 22:16:45.547647 ----->DramcWriteLeveling(PI) begin...
7558 22:16:45.548115 ==
7559 22:16:45.551444 Dram Type= 6, Freq= 0, CH_0, rank 0
7560 22:16:45.557512 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7561 22:16:45.558003 ==
7562 22:16:45.560524 Write leveling (Byte 0): 33 => 33
7563 22:16:45.564234 Write leveling (Byte 1): 25 => 25
7564 22:16:45.564810 DramcWriteLeveling(PI) end<-----
7565 22:16:45.567355
7566 22:16:45.567924 ==
7567 22:16:45.570645 Dram Type= 6, Freq= 0, CH_0, rank 0
7568 22:16:45.573734 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7569 22:16:45.574318 ==
7570 22:16:45.577101 [Gating] SW mode calibration
7571 22:16:45.584106 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7572 22:16:45.587254 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7573 22:16:45.593840 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7574 22:16:45.597216 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7575 22:16:45.600394 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7576 22:16:45.606851 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7577 22:16:45.610845 1 4 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7578 22:16:45.613757 1 4 20 | B1->B0 | 2322 3434 | 1 0 | (0 0) (0 0)
7579 22:16:45.620295 1 4 24 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
7580 22:16:45.623483 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7581 22:16:45.626926 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7582 22:16:45.633826 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7583 22:16:45.636734 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7584 22:16:45.640413 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7585 22:16:45.646796 1 5 16 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 0)
7586 22:16:45.650098 1 5 20 | B1->B0 | 3434 2828 | 1 0 | (1 0) (1 0)
7587 22:16:45.653311 1 5 24 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
7588 22:16:45.660034 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7589 22:16:45.663316 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7590 22:16:45.666570 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7591 22:16:45.673375 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7592 22:16:45.676697 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7593 22:16:45.679790 1 6 16 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
7594 22:16:45.686765 1 6 20 | B1->B0 | 2c2c 4646 | 0 0 | (0 0) (0 0)
7595 22:16:45.689932 1 6 24 | B1->B0 | 3e3e 4646 | 1 0 | (0 0) (0 0)
7596 22:16:45.693056 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7597 22:16:45.699981 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7598 22:16:45.703064 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7599 22:16:45.706546 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7600 22:16:45.713004 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7601 22:16:45.716654 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7602 22:16:45.719598 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7603 22:16:45.726635 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7604 22:16:45.729548 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7605 22:16:45.733102 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7606 22:16:45.739543 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7607 22:16:45.743288 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7608 22:16:45.746339 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7609 22:16:45.749477 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7610 22:16:45.756565 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7611 22:16:45.759234 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7612 22:16:45.765721 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7613 22:16:45.769336 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7614 22:16:45.772741 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7615 22:16:45.779180 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7616 22:16:45.782807 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7617 22:16:45.786159 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7618 22:16:45.792607 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7619 22:16:45.793170 Total UI for P1: 0, mck2ui 16
7620 22:16:45.796230 best dqsien dly found for B0: ( 1, 9, 16)
7621 22:16:45.802544 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7622 22:16:45.805990 Total UI for P1: 0, mck2ui 16
7623 22:16:45.809036 best dqsien dly found for B1: ( 1, 9, 20)
7624 22:16:45.812113 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
7625 22:16:45.815404 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7626 22:16:45.815877
7627 22:16:45.818759 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
7628 22:16:45.822568 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7629 22:16:45.825518 [Gating] SW calibration Done
7630 22:16:45.825984 ==
7631 22:16:45.828618 Dram Type= 6, Freq= 0, CH_0, rank 0
7632 22:16:45.832576 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7633 22:16:45.832999 ==
7634 22:16:45.835637 RX Vref Scan: 0
7635 22:16:45.836100
7636 22:16:45.838589 RX Vref 0 -> 0, step: 1
7637 22:16:45.839010
7638 22:16:45.839345 RX Delay 0 -> 252, step: 8
7639 22:16:45.845836 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
7640 22:16:45.848748 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7641 22:16:45.852456 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7642 22:16:45.855691 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7643 22:16:45.858886 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7644 22:16:45.865786 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7645 22:16:45.868574 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7646 22:16:45.872127 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
7647 22:16:45.875462 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7648 22:16:45.879182 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7649 22:16:45.885653 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7650 22:16:45.888898 iDelay=200, Bit 11, Center 119 (72 ~ 167) 96
7651 22:16:45.892130 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7652 22:16:45.895224 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7653 22:16:45.898932 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7654 22:16:45.905675 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7655 22:16:45.906244 ==
7656 22:16:45.908445 Dram Type= 6, Freq= 0, CH_0, rank 0
7657 22:16:45.911779 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7658 22:16:45.912463 ==
7659 22:16:45.912850 DQS Delay:
7660 22:16:45.915288 DQS0 = 0, DQS1 = 0
7661 22:16:45.915778 DQM Delay:
7662 22:16:45.918485 DQM0 = 132, DQM1 = 125
7663 22:16:45.919029 DQ Delay:
7664 22:16:45.921452 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7665 22:16:45.924929 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
7666 22:16:45.928409 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =119
7667 22:16:45.931442 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7668 22:16:45.935152
7669 22:16:45.935578
7670 22:16:45.935916 ==
7671 22:16:45.938384 Dram Type= 6, Freq= 0, CH_0, rank 0
7672 22:16:45.941269 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7673 22:16:45.941698 ==
7674 22:16:45.942113
7675 22:16:45.942462
7676 22:16:45.944978 TX Vref Scan disable
7677 22:16:45.945409 == TX Byte 0 ==
7678 22:16:45.951554 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7679 22:16:45.954831 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7680 22:16:45.955332 == TX Byte 1 ==
7681 22:16:45.961348 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7682 22:16:45.964987 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7683 22:16:45.965329 ==
7684 22:16:45.967847 Dram Type= 6, Freq= 0, CH_0, rank 0
7685 22:16:45.971352 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7686 22:16:45.971654 ==
7687 22:16:45.987295
7688 22:16:45.989987 TX Vref early break, caculate TX vref
7689 22:16:45.993806 TX Vref=16, minBit 1, minWin=21, winSum=354
7690 22:16:45.997457 TX Vref=18, minBit 0, minWin=22, winSum=370
7691 22:16:46.000276 TX Vref=20, minBit 4, minWin=22, winSum=379
7692 22:16:46.003796 TX Vref=22, minBit 2, minWin=23, winSum=386
7693 22:16:46.006873 TX Vref=24, minBit 4, minWin=23, winSum=398
7694 22:16:46.013380 TX Vref=26, minBit 1, minWin=24, winSum=404
7695 22:16:46.016609 TX Vref=28, minBit 4, minWin=24, winSum=413
7696 22:16:46.020445 TX Vref=30, minBit 3, minWin=24, winSum=410
7697 22:16:46.023855 TX Vref=32, minBit 4, minWin=24, winSum=406
7698 22:16:46.026733 TX Vref=34, minBit 4, minWin=23, winSum=397
7699 22:16:46.030101 TX Vref=36, minBit 0, minWin=23, winSum=385
7700 22:16:46.037025 [TxChooseVref] Worse bit 4, Min win 24, Win sum 413, Final Vref 28
7701 22:16:46.037558
7702 22:16:46.041011 Final TX Range 0 Vref 28
7703 22:16:46.041435
7704 22:16:46.041768 ==
7705 22:16:46.043240 Dram Type= 6, Freq= 0, CH_0, rank 0
7706 22:16:46.047122 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7707 22:16:46.047544 ==
7708 22:16:46.047874
7709 22:16:46.048242
7710 22:16:46.050744 TX Vref Scan disable
7711 22:16:46.056537 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7712 22:16:46.057146 == TX Byte 0 ==
7713 22:16:46.060265 u2DelayCellOfst[0]=14 cells (4 PI)
7714 22:16:46.063477 u2DelayCellOfst[1]=17 cells (5 PI)
7715 22:16:46.066689 u2DelayCellOfst[2]=10 cells (3 PI)
7716 22:16:46.070455 u2DelayCellOfst[3]=10 cells (3 PI)
7717 22:16:46.073511 u2DelayCellOfst[4]=10 cells (3 PI)
7718 22:16:46.077248 u2DelayCellOfst[5]=0 cells (0 PI)
7719 22:16:46.080144 u2DelayCellOfst[6]=17 cells (5 PI)
7720 22:16:46.083429 u2DelayCellOfst[7]=17 cells (5 PI)
7721 22:16:46.086713 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7722 22:16:46.090142 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7723 22:16:46.093826 == TX Byte 1 ==
7724 22:16:46.096993 u2DelayCellOfst[8]=0 cells (0 PI)
7725 22:16:46.099781 u2DelayCellOfst[9]=0 cells (0 PI)
7726 22:16:46.100270 u2DelayCellOfst[10]=7 cells (2 PI)
7727 22:16:46.103171 u2DelayCellOfst[11]=0 cells (0 PI)
7728 22:16:46.106764 u2DelayCellOfst[12]=10 cells (3 PI)
7729 22:16:46.110515 u2DelayCellOfst[13]=10 cells (3 PI)
7730 22:16:46.113296 u2DelayCellOfst[14]=14 cells (4 PI)
7731 22:16:46.116768 u2DelayCellOfst[15]=10 cells (3 PI)
7732 22:16:46.123359 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7733 22:16:46.126553 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7734 22:16:46.127080 DramC Write-DBI on
7735 22:16:46.127428 ==
7736 22:16:46.129973 Dram Type= 6, Freq= 0, CH_0, rank 0
7737 22:16:46.136262 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7738 22:16:46.136794 ==
7739 22:16:46.137148
7740 22:16:46.137471
7741 22:16:46.137779 TX Vref Scan disable
7742 22:16:46.140345 == TX Byte 0 ==
7743 22:16:46.144002 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7744 22:16:46.147245 == TX Byte 1 ==
7745 22:16:46.150702 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
7746 22:16:46.151154 DramC Write-DBI off
7747 22:16:46.153955
7748 22:16:46.154378 [DATLAT]
7749 22:16:46.154714 Freq=1600, CH0 RK0
7750 22:16:46.155031
7751 22:16:46.157204 DATLAT Default: 0xf
7752 22:16:46.157636 0, 0xFFFF, sum = 0
7753 22:16:46.160514 1, 0xFFFF, sum = 0
7754 22:16:46.160943 2, 0xFFFF, sum = 0
7755 22:16:46.163653 3, 0xFFFF, sum = 0
7756 22:16:46.167361 4, 0xFFFF, sum = 0
7757 22:16:46.167795 5, 0xFFFF, sum = 0
7758 22:16:46.170315 6, 0xFFFF, sum = 0
7759 22:16:46.170839 7, 0xFFFF, sum = 0
7760 22:16:46.174039 8, 0xFFFF, sum = 0
7761 22:16:46.174557 9, 0xFFFF, sum = 0
7762 22:16:46.177451 10, 0xFFFF, sum = 0
7763 22:16:46.177878 11, 0xFFFF, sum = 0
7764 22:16:46.180365 12, 0xFFFF, sum = 0
7765 22:16:46.180795 13, 0xFFFF, sum = 0
7766 22:16:46.183898 14, 0x0, sum = 1
7767 22:16:46.184362 15, 0x0, sum = 2
7768 22:16:46.186925 16, 0x0, sum = 3
7769 22:16:46.187377 17, 0x0, sum = 4
7770 22:16:46.190109 best_step = 15
7771 22:16:46.190556
7772 22:16:46.190892 ==
7773 22:16:46.193554 Dram Type= 6, Freq= 0, CH_0, rank 0
7774 22:16:46.197521 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7775 22:16:46.197948 ==
7776 22:16:46.200400 RX Vref Scan: 1
7777 22:16:46.200821
7778 22:16:46.201155 Set Vref Range= 24 -> 127
7779 22:16:46.201471
7780 22:16:46.204067 RX Vref 24 -> 127, step: 1
7781 22:16:46.204702
7782 22:16:46.206808 RX Delay 11 -> 252, step: 4
7783 22:16:46.207227
7784 22:16:46.210355 Set Vref, RX VrefLevel [Byte0]: 24
7785 22:16:46.213616 [Byte1]: 24
7786 22:16:46.214102
7787 22:16:46.216882 Set Vref, RX VrefLevel [Byte0]: 25
7788 22:16:46.220428 [Byte1]: 25
7789 22:16:46.220848
7790 22:16:46.223670 Set Vref, RX VrefLevel [Byte0]: 26
7791 22:16:46.226783 [Byte1]: 26
7792 22:16:46.230949
7793 22:16:46.231505 Set Vref, RX VrefLevel [Byte0]: 27
7794 22:16:46.234310 [Byte1]: 27
7795 22:16:46.238518
7796 22:16:46.239104 Set Vref, RX VrefLevel [Byte0]: 28
7797 22:16:46.241863 [Byte1]: 28
7798 22:16:46.245925
7799 22:16:46.246349 Set Vref, RX VrefLevel [Byte0]: 29
7800 22:16:46.249727 [Byte1]: 29
7801 22:16:46.254024
7802 22:16:46.254446 Set Vref, RX VrefLevel [Byte0]: 30
7803 22:16:46.257038 [Byte1]: 30
7804 22:16:46.261199
7805 22:16:46.261621 Set Vref, RX VrefLevel [Byte0]: 31
7806 22:16:46.264700 [Byte1]: 31
7807 22:16:46.269021
7808 22:16:46.269492 Set Vref, RX VrefLevel [Byte0]: 32
7809 22:16:46.272228 [Byte1]: 32
7810 22:16:46.276544
7811 22:16:46.276994 Set Vref, RX VrefLevel [Byte0]: 33
7812 22:16:46.279502 [Byte1]: 33
7813 22:16:46.283965
7814 22:16:46.284082 Set Vref, RX VrefLevel [Byte0]: 34
7815 22:16:46.290290 [Byte1]: 34
7816 22:16:46.290381
7817 22:16:46.293315 Set Vref, RX VrefLevel [Byte0]: 35
7818 22:16:46.296785 [Byte1]: 35
7819 22:16:46.296878
7820 22:16:46.300216 Set Vref, RX VrefLevel [Byte0]: 36
7821 22:16:46.303779 [Byte1]: 36
7822 22:16:46.303888
7823 22:16:46.307035 Set Vref, RX VrefLevel [Byte0]: 37
7824 22:16:46.310135 [Byte1]: 37
7825 22:16:46.314662
7826 22:16:46.314859 Set Vref, RX VrefLevel [Byte0]: 38
7827 22:16:46.317669 [Byte1]: 38
7828 22:16:46.322499
7829 22:16:46.322680 Set Vref, RX VrefLevel [Byte0]: 39
7830 22:16:46.325344 [Byte1]: 39
7831 22:16:46.329856
7832 22:16:46.330056 Set Vref, RX VrefLevel [Byte0]: 40
7833 22:16:46.333397 [Byte1]: 40
7834 22:16:46.337496
7835 22:16:46.337735 Set Vref, RX VrefLevel [Byte0]: 41
7836 22:16:46.340838 [Byte1]: 41
7837 22:16:46.344884
7838 22:16:46.345295 Set Vref, RX VrefLevel [Byte0]: 42
7839 22:16:46.348501 [Byte1]: 42
7840 22:16:46.352914
7841 22:16:46.353331 Set Vref, RX VrefLevel [Byte0]: 43
7842 22:16:46.356237 [Byte1]: 43
7843 22:16:46.360676
7844 22:16:46.361141 Set Vref, RX VrefLevel [Byte0]: 44
7845 22:16:46.363899 [Byte1]: 44
7846 22:16:46.368285
7847 22:16:46.368705 Set Vref, RX VrefLevel [Byte0]: 45
7848 22:16:46.371130 [Byte1]: 45
7849 22:16:46.375627
7850 22:16:46.376161 Set Vref, RX VrefLevel [Byte0]: 46
7851 22:16:46.379065 [Byte1]: 46
7852 22:16:46.383246
7853 22:16:46.383771 Set Vref, RX VrefLevel [Byte0]: 47
7854 22:16:46.389451 [Byte1]: 47
7855 22:16:46.389872
7856 22:16:46.392609 Set Vref, RX VrefLevel [Byte0]: 48
7857 22:16:46.396673 [Byte1]: 48
7858 22:16:46.397092
7859 22:16:46.399406 Set Vref, RX VrefLevel [Byte0]: 49
7860 22:16:46.402818 [Byte1]: 49
7861 22:16:46.406471
7862 22:16:46.406887 Set Vref, RX VrefLevel [Byte0]: 50
7863 22:16:46.409588 [Byte1]: 50
7864 22:16:46.413388
7865 22:16:46.413805 Set Vref, RX VrefLevel [Byte0]: 51
7866 22:16:46.416721 [Byte1]: 51
7867 22:16:46.421091
7868 22:16:46.421504 Set Vref, RX VrefLevel [Byte0]: 52
7869 22:16:46.424777 [Byte1]: 52
7870 22:16:46.429535
7871 22:16:46.430066 Set Vref, RX VrefLevel [Byte0]: 53
7872 22:16:46.432488 [Byte1]: 53
7873 22:16:46.436874
7874 22:16:46.437415 Set Vref, RX VrefLevel [Byte0]: 54
7875 22:16:46.439932 [Byte1]: 54
7876 22:16:46.443779
7877 22:16:46.444292 Set Vref, RX VrefLevel [Byte0]: 55
7878 22:16:46.447495 [Byte1]: 55
7879 22:16:46.451916
7880 22:16:46.452476 Set Vref, RX VrefLevel [Byte0]: 56
7881 22:16:46.455036 [Byte1]: 56
7882 22:16:46.459399
7883 22:16:46.459842 Set Vref, RX VrefLevel [Byte0]: 57
7884 22:16:46.462714 [Byte1]: 57
7885 22:16:46.467751
7886 22:16:46.468221 Set Vref, RX VrefLevel [Byte0]: 58
7887 22:16:46.470351 [Byte1]: 58
7888 22:16:46.474945
7889 22:16:46.475445 Set Vref, RX VrefLevel [Byte0]: 59
7890 22:16:46.478019 [Byte1]: 59
7891 22:16:46.482340
7892 22:16:46.482866 Set Vref, RX VrefLevel [Byte0]: 60
7893 22:16:46.485612 [Byte1]: 60
7894 22:16:46.489770
7895 22:16:46.490197 Set Vref, RX VrefLevel [Byte0]: 61
7896 22:16:46.493353 [Byte1]: 61
7897 22:16:46.497397
7898 22:16:46.497868 Set Vref, RX VrefLevel [Byte0]: 62
7899 22:16:46.500550 [Byte1]: 62
7900 22:16:46.505160
7901 22:16:46.505629 Set Vref, RX VrefLevel [Byte0]: 63
7902 22:16:46.508632 [Byte1]: 63
7903 22:16:46.512909
7904 22:16:46.513479 Set Vref, RX VrefLevel [Byte0]: 64
7905 22:16:46.515846 [Byte1]: 64
7906 22:16:46.520175
7907 22:16:46.520697 Set Vref, RX VrefLevel [Byte0]: 65
7908 22:16:46.523302 [Byte1]: 65
7909 22:16:46.528144
7910 22:16:46.528662 Set Vref, RX VrefLevel [Byte0]: 66
7911 22:16:46.531066 [Byte1]: 66
7912 22:16:46.535451
7913 22:16:46.535874 Set Vref, RX VrefLevel [Byte0]: 67
7914 22:16:46.538971 [Byte1]: 67
7915 22:16:46.543040
7916 22:16:46.543461 Set Vref, RX VrefLevel [Byte0]: 68
7917 22:16:46.546574 [Byte1]: 68
7918 22:16:46.550876
7919 22:16:46.551464 Set Vref, RX VrefLevel [Byte0]: 69
7920 22:16:46.554170 [Byte1]: 69
7921 22:16:46.558461
7922 22:16:46.558893 Set Vref, RX VrefLevel [Byte0]: 70
7923 22:16:46.561317 [Byte1]: 70
7924 22:16:46.565732
7925 22:16:46.566155 Set Vref, RX VrefLevel [Byte0]: 71
7926 22:16:46.569838 [Byte1]: 71
7927 22:16:46.573662
7928 22:16:46.574202 Set Vref, RX VrefLevel [Byte0]: 72
7929 22:16:46.577205 [Byte1]: 72
7930 22:16:46.581249
7931 22:16:46.581768 Set Vref, RX VrefLevel [Byte0]: 73
7932 22:16:46.584213 [Byte1]: 73
7933 22:16:46.588538
7934 22:16:46.589048 Set Vref, RX VrefLevel [Byte0]: 74
7935 22:16:46.591936 [Byte1]: 74
7936 22:16:46.596481
7937 22:16:46.597000 Set Vref, RX VrefLevel [Byte0]: 75
7938 22:16:46.599896 [Byte1]: 75
7939 22:16:46.604090
7940 22:16:46.604678 Set Vref, RX VrefLevel [Byte0]: 76
7941 22:16:46.607372 [Byte1]: 76
7942 22:16:46.611686
7943 22:16:46.612290 Final RX Vref Byte 0 = 56 to rank0
7944 22:16:46.615111 Final RX Vref Byte 1 = 62 to rank0
7945 22:16:46.618571 Final RX Vref Byte 0 = 56 to rank1
7946 22:16:46.622032 Final RX Vref Byte 1 = 62 to rank1==
7947 22:16:46.624696 Dram Type= 6, Freq= 0, CH_0, rank 0
7948 22:16:46.631570 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7949 22:16:46.632081 ==
7950 22:16:46.632539 DQS Delay:
7951 22:16:46.632959 DQS0 = 0, DQS1 = 0
7952 22:16:46.635314 DQM Delay:
7953 22:16:46.635750 DQM0 = 129, DQM1 = 122
7954 22:16:46.638417 DQ Delay:
7955 22:16:46.641601 DQ0 =130, DQ1 =132, DQ2 =126, DQ3 =126
7956 22:16:46.644708 DQ4 =132, DQ5 =120, DQ6 =136, DQ7 =136
7957 22:16:46.648138 DQ8 =110, DQ9 =110, DQ10 =122, DQ11 =118
7958 22:16:46.651404 DQ12 =128, DQ13 =126, DQ14 =132, DQ15 =134
7959 22:16:46.651859
7960 22:16:46.652246
7961 22:16:46.652561
7962 22:16:46.655379 [DramC_TX_OE_Calibration] TA2
7963 22:16:46.658680 Original DQ_B0 (3 6) =30, OEN = 27
7964 22:16:46.661279 Original DQ_B1 (3 6) =30, OEN = 27
7965 22:16:46.665174 24, 0x0, End_B0=24 End_B1=24
7966 22:16:46.665604 25, 0x0, End_B0=25 End_B1=25
7967 22:16:46.668253 26, 0x0, End_B0=26 End_B1=26
7968 22:16:46.672116 27, 0x0, End_B0=27 End_B1=27
7969 22:16:46.675145 28, 0x0, End_B0=28 End_B1=28
7970 22:16:46.675678 29, 0x0, End_B0=29 End_B1=29
7971 22:16:46.678201 30, 0x0, End_B0=30 End_B1=30
7972 22:16:46.681578 31, 0x4141, End_B0=30 End_B1=30
7973 22:16:46.685072 Byte0 end_step=30 best_step=27
7974 22:16:46.688221 Byte1 end_step=30 best_step=27
7975 22:16:46.691536 Byte0 TX OE(2T, 0.5T) = (3, 3)
7976 22:16:46.692172 Byte1 TX OE(2T, 0.5T) = (3, 3)
7977 22:16:46.692536
7978 22:16:46.695029
7979 22:16:46.701418 [DQSOSCAuto] RK0, (LSB)MR18= 0x1408, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 399 ps
7980 22:16:46.704521 CH0 RK0: MR19=303, MR18=1408
7981 22:16:46.711379 CH0_RK0: MR19=0x303, MR18=0x1408, DQSOSC=399, MR23=63, INC=23, DEC=15
7982 22:16:46.711810
7983 22:16:46.714829 ----->DramcWriteLeveling(PI) begin...
7984 22:16:46.715258 ==
7985 22:16:46.718022 Dram Type= 6, Freq= 0, CH_0, rank 1
7986 22:16:46.721098 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7987 22:16:46.721528 ==
7988 22:16:46.725066 Write leveling (Byte 0): 33 => 33
7989 22:16:46.728022 Write leveling (Byte 1): 25 => 25
7990 22:16:46.731589 DramcWriteLeveling(PI) end<-----
7991 22:16:46.732098
7992 22:16:46.732486 ==
7993 22:16:46.734667 Dram Type= 6, Freq= 0, CH_0, rank 1
7994 22:16:46.737991 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7995 22:16:46.738424 ==
7996 22:16:46.741235 [Gating] SW mode calibration
7997 22:16:46.747691 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7998 22:16:46.754384 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7999 22:16:46.757825 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8000 22:16:46.760787 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8001 22:16:46.767835 1 4 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8002 22:16:46.770574 1 4 12 | B1->B0 | 2323 3232 | 0 1 | (0 0) (0 0)
8003 22:16:46.774212 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8004 22:16:46.780904 1 4 20 | B1->B0 | 2c2c 3434 | 0 1 | (0 0) (1 1)
8005 22:16:46.784259 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8006 22:16:46.787150 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8007 22:16:46.793916 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8008 22:16:46.797286 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8009 22:16:46.800488 1 5 8 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
8010 22:16:46.807390 1 5 12 | B1->B0 | 3434 2626 | 1 0 | (1 1) (0 1)
8011 22:16:46.810585 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
8012 22:16:46.813820 1 5 20 | B1->B0 | 3030 2323 | 1 0 | (1 0) (0 0)
8013 22:16:46.820542 1 5 24 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
8014 22:16:46.823500 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8015 22:16:46.826982 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8016 22:16:46.834314 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8017 22:16:46.837195 1 6 8 | B1->B0 | 2323 3535 | 0 0 | (0 0) (1 1)
8018 22:16:46.840537 1 6 12 | B1->B0 | 2323 4242 | 0 0 | (0 0) (0 0)
8019 22:16:46.846573 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8020 22:16:46.850254 1 6 20 | B1->B0 | 3030 4646 | 0 0 | (0 0) (0 0)
8021 22:16:46.853435 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8022 22:16:46.860149 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8023 22:16:46.863496 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8024 22:16:46.866693 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8025 22:16:46.874024 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8026 22:16:46.876994 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8027 22:16:46.880052 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8028 22:16:46.886491 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8029 22:16:46.890146 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8030 22:16:46.893443 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8031 22:16:46.900254 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8032 22:16:46.903801 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8033 22:16:46.907050 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8034 22:16:46.912796 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8035 22:16:46.916105 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8036 22:16:46.919470 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8037 22:16:46.926040 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8038 22:16:46.929305 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8039 22:16:46.933112 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8040 22:16:46.939426 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8041 22:16:46.942527 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8042 22:16:46.946231 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8043 22:16:46.949471 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8044 22:16:46.952967 Total UI for P1: 0, mck2ui 16
8045 22:16:46.956424 best dqsien dly found for B0: ( 1, 9, 8)
8046 22:16:46.962716 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8047 22:16:46.966298 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8048 22:16:46.969227 Total UI for P1: 0, mck2ui 16
8049 22:16:46.972674 best dqsien dly found for B1: ( 1, 9, 20)
8050 22:16:46.975827 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8051 22:16:46.979639 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
8052 22:16:46.979740
8053 22:16:46.983029 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8054 22:16:46.986049 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
8055 22:16:46.989379 [Gating] SW calibration Done
8056 22:16:46.989535 ==
8057 22:16:46.992789 Dram Type= 6, Freq= 0, CH_0, rank 1
8058 22:16:46.999227 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8059 22:16:46.999425 ==
8060 22:16:46.999597 RX Vref Scan: 0
8061 22:16:46.999761
8062 22:16:47.002389 RX Vref 0 -> 0, step: 1
8063 22:16:47.002563
8064 22:16:47.006368 RX Delay 0 -> 252, step: 8
8065 22:16:47.009609 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8066 22:16:47.012392 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8067 22:16:47.015926 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8068 22:16:47.019421 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8069 22:16:47.026163 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8070 22:16:47.029476 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8071 22:16:47.032579 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8072 22:16:47.035944 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8073 22:16:47.039080 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8074 22:16:47.045916 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8075 22:16:47.049130 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8076 22:16:47.052607 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8077 22:16:47.055997 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8078 22:16:47.059117 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8079 22:16:47.065914 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8080 22:16:47.069459 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8081 22:16:47.069617 ==
8082 22:16:47.072433 Dram Type= 6, Freq= 0, CH_0, rank 1
8083 22:16:47.075783 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8084 22:16:47.076116 ==
8085 22:16:47.079765 DQS Delay:
8086 22:16:47.080090 DQS0 = 0, DQS1 = 0
8087 22:16:47.080277 DQM Delay:
8088 22:16:47.082465 DQM0 = 131, DQM1 = 123
8089 22:16:47.082678 DQ Delay:
8090 22:16:47.086154 DQ0 =131, DQ1 =131, DQ2 =127, DQ3 =131
8091 22:16:47.089320 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
8092 22:16:47.095667 DQ8 =115, DQ9 =115, DQ10 =123, DQ11 =115
8093 22:16:47.099368 DQ12 =127, DQ13 =131, DQ14 =131, DQ15 =131
8094 22:16:47.099795
8095 22:16:47.100179
8096 22:16:47.100561 ==
8097 22:16:47.102510 Dram Type= 6, Freq= 0, CH_0, rank 1
8098 22:16:47.105960 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8099 22:16:47.106383 ==
8100 22:16:47.106841
8101 22:16:47.107256
8102 22:16:47.109043 TX Vref Scan disable
8103 22:16:47.109556 == TX Byte 0 ==
8104 22:16:47.116101 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8105 22:16:47.119179 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8106 22:16:47.119595 == TX Byte 1 ==
8107 22:16:47.126075 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8108 22:16:47.129998 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8109 22:16:47.130530 ==
8110 22:16:47.132293 Dram Type= 6, Freq= 0, CH_0, rank 1
8111 22:16:47.135711 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8112 22:16:47.136160 ==
8113 22:16:47.152983
8114 22:16:47.156331 TX Vref early break, caculate TX vref
8115 22:16:47.160619 TX Vref=16, minBit 3, minWin=22, winSum=369
8116 22:16:47.163283 TX Vref=18, minBit 8, minWin=22, winSum=373
8117 22:16:47.166691 TX Vref=20, minBit 1, minWin=23, winSum=386
8118 22:16:47.169604 TX Vref=22, minBit 1, minWin=24, winSum=395
8119 22:16:47.173247 TX Vref=24, minBit 4, minWin=24, winSum=401
8120 22:16:47.179760 TX Vref=26, minBit 11, minWin=24, winSum=408
8121 22:16:47.183360 TX Vref=28, minBit 0, minWin=25, winSum=414
8122 22:16:47.186189 TX Vref=30, minBit 4, minWin=25, winSum=414
8123 22:16:47.189398 TX Vref=32, minBit 0, minWin=24, winSum=408
8124 22:16:47.192562 TX Vref=34, minBit 0, minWin=24, winSum=402
8125 22:16:47.199524 TX Vref=36, minBit 0, minWin=24, winSum=393
8126 22:16:47.202666 TX Vref=38, minBit 0, minWin=22, winSum=379
8127 22:16:47.206609 [TxChooseVref] Worse bit 0, Min win 25, Win sum 414, Final Vref 28
8128 22:16:47.209273
8129 22:16:47.209745 Final TX Range 0 Vref 28
8130 22:16:47.210121
8131 22:16:47.210470 ==
8132 22:16:47.212805 Dram Type= 6, Freq= 0, CH_0, rank 1
8133 22:16:47.218715 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8134 22:16:47.219187 ==
8135 22:16:47.219563
8136 22:16:47.219913
8137 22:16:47.220309 TX Vref Scan disable
8138 22:16:47.226659 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8139 22:16:47.227262 == TX Byte 0 ==
8140 22:16:47.229956 u2DelayCellOfst[0]=14 cells (4 PI)
8141 22:16:47.233229 u2DelayCellOfst[1]=17 cells (5 PI)
8142 22:16:47.236334 u2DelayCellOfst[2]=10 cells (3 PI)
8143 22:16:47.240108 u2DelayCellOfst[3]=14 cells (4 PI)
8144 22:16:47.243133 u2DelayCellOfst[4]=10 cells (3 PI)
8145 22:16:47.245944 u2DelayCellOfst[5]=0 cells (0 PI)
8146 22:16:47.249745 u2DelayCellOfst[6]=17 cells (5 PI)
8147 22:16:47.252763 u2DelayCellOfst[7]=17 cells (5 PI)
8148 22:16:47.256447 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
8149 22:16:47.259858 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8150 22:16:47.262764 == TX Byte 1 ==
8151 22:16:47.266368 u2DelayCellOfst[8]=0 cells (0 PI)
8152 22:16:47.269267 u2DelayCellOfst[9]=0 cells (0 PI)
8153 22:16:47.272674 u2DelayCellOfst[10]=7 cells (2 PI)
8154 22:16:47.275908 u2DelayCellOfst[11]=0 cells (0 PI)
8155 22:16:47.279733 u2DelayCellOfst[12]=10 cells (3 PI)
8156 22:16:47.282989 u2DelayCellOfst[13]=10 cells (3 PI)
8157 22:16:47.283511 u2DelayCellOfst[14]=14 cells (4 PI)
8158 22:16:47.286527 u2DelayCellOfst[15]=10 cells (3 PI)
8159 22:16:47.293148 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8160 22:16:47.296454 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8161 22:16:47.296978 DramC Write-DBI on
8162 22:16:47.299520 ==
8163 22:16:47.302617 Dram Type= 6, Freq= 0, CH_0, rank 1
8164 22:16:47.306324 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8165 22:16:47.306889 ==
8166 22:16:47.307263
8167 22:16:47.307609
8168 22:16:47.309757 TX Vref Scan disable
8169 22:16:47.310317 == TX Byte 0 ==
8170 22:16:47.316062 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
8171 22:16:47.316610 == TX Byte 1 ==
8172 22:16:47.319271 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8173 22:16:47.323439 DramC Write-DBI off
8174 22:16:47.324034
8175 22:16:47.324414 [DATLAT]
8176 22:16:47.326432 Freq=1600, CH0 RK1
8177 22:16:47.326993
8178 22:16:47.327364 DATLAT Default: 0xf
8179 22:16:47.329105 0, 0xFFFF, sum = 0
8180 22:16:47.329578 1, 0xFFFF, sum = 0
8181 22:16:47.332482 2, 0xFFFF, sum = 0
8182 22:16:47.332951 3, 0xFFFF, sum = 0
8183 22:16:47.336303 4, 0xFFFF, sum = 0
8184 22:16:47.336778 5, 0xFFFF, sum = 0
8185 22:16:47.339425 6, 0xFFFF, sum = 0
8186 22:16:47.340032 7, 0xFFFF, sum = 0
8187 22:16:47.343438 8, 0xFFFF, sum = 0
8188 22:16:47.346150 9, 0xFFFF, sum = 0
8189 22:16:47.346625 10, 0xFFFF, sum = 0
8190 22:16:47.349772 11, 0xFFFF, sum = 0
8191 22:16:47.350354 12, 0xFFFF, sum = 0
8192 22:16:47.352920 13, 0xFFFF, sum = 0
8193 22:16:47.353493 14, 0x0, sum = 1
8194 22:16:47.356059 15, 0x0, sum = 2
8195 22:16:47.356532 16, 0x0, sum = 3
8196 22:16:47.359077 17, 0x0, sum = 4
8197 22:16:47.359644 best_step = 15
8198 22:16:47.360049
8199 22:16:47.360401 ==
8200 22:16:47.362317 Dram Type= 6, Freq= 0, CH_0, rank 1
8201 22:16:47.365672 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8202 22:16:47.366138 ==
8203 22:16:47.369396 RX Vref Scan: 0
8204 22:16:47.369859
8205 22:16:47.372171 RX Vref 0 -> 0, step: 1
8206 22:16:47.372592
8207 22:16:47.372928 RX Delay 11 -> 252, step: 4
8208 22:16:47.379929 iDelay=191, Bit 0, Center 126 (71 ~ 182) 112
8209 22:16:47.383500 iDelay=191, Bit 1, Center 130 (75 ~ 186) 112
8210 22:16:47.386082 iDelay=191, Bit 2, Center 122 (67 ~ 178) 112
8211 22:16:47.389925 iDelay=191, Bit 3, Center 126 (71 ~ 182) 112
8212 22:16:47.393267 iDelay=191, Bit 4, Center 126 (75 ~ 178) 104
8213 22:16:47.399484 iDelay=191, Bit 5, Center 114 (59 ~ 170) 112
8214 22:16:47.403321 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8215 22:16:47.406198 iDelay=191, Bit 7, Center 136 (83 ~ 190) 108
8216 22:16:47.409903 iDelay=191, Bit 8, Center 112 (59 ~ 166) 108
8217 22:16:47.412900 iDelay=191, Bit 9, Center 110 (55 ~ 166) 112
8218 22:16:47.420103 iDelay=191, Bit 10, Center 122 (67 ~ 178) 112
8219 22:16:47.422919 iDelay=191, Bit 11, Center 116 (63 ~ 170) 108
8220 22:16:47.426541 iDelay=191, Bit 12, Center 126 (75 ~ 178) 104
8221 22:16:47.430398 iDelay=191, Bit 13, Center 126 (71 ~ 182) 112
8222 22:16:47.432981 iDelay=191, Bit 14, Center 134 (79 ~ 190) 112
8223 22:16:47.439665 iDelay=191, Bit 15, Center 132 (75 ~ 190) 116
8224 22:16:47.440215 ==
8225 22:16:47.442807 Dram Type= 6, Freq= 0, CH_0, rank 1
8226 22:16:47.446323 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8227 22:16:47.446761 ==
8228 22:16:47.447092 DQS Delay:
8229 22:16:47.449167 DQS0 = 0, DQS1 = 0
8230 22:16:47.449580 DQM Delay:
8231 22:16:47.452811 DQM0 = 126, DQM1 = 122
8232 22:16:47.453291 DQ Delay:
8233 22:16:47.456150 DQ0 =126, DQ1 =130, DQ2 =122, DQ3 =126
8234 22:16:47.459551 DQ4 =126, DQ5 =114, DQ6 =134, DQ7 =136
8235 22:16:47.462789 DQ8 =112, DQ9 =110, DQ10 =122, DQ11 =116
8236 22:16:47.466495 DQ12 =126, DQ13 =126, DQ14 =134, DQ15 =132
8237 22:16:47.469541
8238 22:16:47.469997
8239 22:16:47.470360
8240 22:16:47.470698 [DramC_TX_OE_Calibration] TA2
8241 22:16:47.472752 Original DQ_B0 (3 6) =30, OEN = 27
8242 22:16:47.476104 Original DQ_B1 (3 6) =30, OEN = 27
8243 22:16:47.479388 24, 0x0, End_B0=24 End_B1=24
8244 22:16:47.482840 25, 0x0, End_B0=25 End_B1=25
8245 22:16:47.486174 26, 0x0, End_B0=26 End_B1=26
8246 22:16:47.486737 27, 0x0, End_B0=27 End_B1=27
8247 22:16:47.489664 28, 0x0, End_B0=28 End_B1=28
8248 22:16:47.492648 29, 0x0, End_B0=29 End_B1=29
8249 22:16:47.495950 30, 0x0, End_B0=30 End_B1=30
8250 22:16:47.499421 31, 0x4141, End_B0=30 End_B1=30
8251 22:16:47.499890 Byte0 end_step=30 best_step=27
8252 22:16:47.502816 Byte1 end_step=30 best_step=27
8253 22:16:47.506642 Byte0 TX OE(2T, 0.5T) = (3, 3)
8254 22:16:47.509537 Byte1 TX OE(2T, 0.5T) = (3, 3)
8255 22:16:47.510146
8256 22:16:47.510520
8257 22:16:47.519119 [DQSOSCAuto] RK1, (LSB)MR18= 0x190e, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 397 ps
8258 22:16:47.519679 CH0 RK1: MR19=303, MR18=190E
8259 22:16:47.525860 CH0_RK1: MR19=0x303, MR18=0x190E, DQSOSC=397, MR23=63, INC=23, DEC=15
8260 22:16:47.529036 [RxdqsGatingPostProcess] freq 1600
8261 22:16:47.535511 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8262 22:16:47.538765 best DQS0 dly(2T, 0.5T) = (1, 1)
8263 22:16:47.542160 best DQS1 dly(2T, 0.5T) = (1, 1)
8264 22:16:47.545680 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8265 22:16:47.548562 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8266 22:16:47.548989 best DQS0 dly(2T, 0.5T) = (1, 1)
8267 22:16:47.552564 best DQS1 dly(2T, 0.5T) = (1, 1)
8268 22:16:47.556220 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8269 22:16:47.558927 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8270 22:16:47.562362 Pre-setting of DQS Precalculation
8271 22:16:47.568464 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8272 22:16:47.568936 ==
8273 22:16:47.572094 Dram Type= 6, Freq= 0, CH_1, rank 0
8274 22:16:47.576048 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8275 22:16:47.576642 ==
8276 22:16:47.582318 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8277 22:16:47.585070 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8278 22:16:47.588489 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8279 22:16:47.595186 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8280 22:16:47.603847 [CA 0] Center 42 (14~71) winsize 58
8281 22:16:47.607607 [CA 1] Center 41 (12~71) winsize 60
8282 22:16:47.610931 [CA 2] Center 37 (9~66) winsize 58
8283 22:16:47.614157 [CA 3] Center 36 (7~65) winsize 59
8284 22:16:47.617138 [CA 4] Center 37 (7~67) winsize 61
8285 22:16:47.620113 [CA 5] Center 36 (7~66) winsize 60
8286 22:16:47.620584
8287 22:16:47.624122 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8288 22:16:47.624690
8289 22:16:47.627108 [CATrainingPosCal] consider 1 rank data
8290 22:16:47.630479 u2DelayCellTimex100 = 275/100 ps
8291 22:16:47.633849 CA0 delay=42 (14~71),Diff = 6 PI (21 cell)
8292 22:16:47.640824 CA1 delay=41 (12~71),Diff = 5 PI (17 cell)
8293 22:16:47.643822 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8294 22:16:47.646721 CA3 delay=36 (7~65),Diff = 0 PI (0 cell)
8295 22:16:47.649851 CA4 delay=37 (7~67),Diff = 1 PI (3 cell)
8296 22:16:47.653272 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8297 22:16:47.653849
8298 22:16:47.656812 CA PerBit enable=1, Macro0, CA PI delay=36
8299 22:16:47.657270
8300 22:16:47.659878 [CBTSetCACLKResult] CA Dly = 36
8301 22:16:47.663182 CS Dly: 9 (0~40)
8302 22:16:47.667094 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8303 22:16:47.670197 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8304 22:16:47.670604 ==
8305 22:16:47.673098 Dram Type= 6, Freq= 0, CH_1, rank 1
8306 22:16:47.676146 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8307 22:16:47.679999 ==
8308 22:16:47.683194 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8309 22:16:47.686693 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8310 22:16:47.692954 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8311 22:16:47.699743 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8312 22:16:47.707193 [CA 0] Center 43 (14~72) winsize 59
8313 22:16:47.710538 [CA 1] Center 43 (14~72) winsize 59
8314 22:16:47.713700 [CA 2] Center 37 (8~67) winsize 60
8315 22:16:47.716921 [CA 3] Center 37 (8~67) winsize 60
8316 22:16:47.720064 [CA 4] Center 38 (9~68) winsize 60
8317 22:16:47.723455 [CA 5] Center 37 (8~66) winsize 59
8318 22:16:47.724042
8319 22:16:47.727110 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8320 22:16:47.727659
8321 22:16:47.733650 [CATrainingPosCal] consider 2 rank data
8322 22:16:47.734203 u2DelayCellTimex100 = 275/100 ps
8323 22:16:47.739721 CA0 delay=42 (14~71),Diff = 6 PI (21 cell)
8324 22:16:47.743294 CA1 delay=42 (14~71),Diff = 6 PI (21 cell)
8325 22:16:47.746602 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8326 22:16:47.749843 CA3 delay=36 (8~65),Diff = 0 PI (0 cell)
8327 22:16:47.752746 CA4 delay=38 (9~67),Diff = 2 PI (7 cell)
8328 22:16:47.756424 CA5 delay=37 (8~66),Diff = 1 PI (3 cell)
8329 22:16:47.756977
8330 22:16:47.759849 CA PerBit enable=1, Macro0, CA PI delay=36
8331 22:16:47.760447
8332 22:16:47.763423 [CBTSetCACLKResult] CA Dly = 36
8333 22:16:47.766293 CS Dly: 11 (0~44)
8334 22:16:47.769686 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8335 22:16:47.773566 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8336 22:16:47.774117
8337 22:16:47.776410 ----->DramcWriteLeveling(PI) begin...
8338 22:16:47.776969 ==
8339 22:16:47.779462 Dram Type= 6, Freq= 0, CH_1, rank 0
8340 22:16:47.786533 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8341 22:16:47.787088 ==
8342 22:16:47.789879 Write leveling (Byte 0): 26 => 26
8343 22:16:47.792936 Write leveling (Byte 1): 28 => 28
8344 22:16:47.793426 DramcWriteLeveling(PI) end<-----
8345 22:16:47.793795
8346 22:16:47.796593 ==
8347 22:16:47.799484 Dram Type= 6, Freq= 0, CH_1, rank 0
8348 22:16:47.803672 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8349 22:16:47.804291 ==
8350 22:16:47.806026 [Gating] SW mode calibration
8351 22:16:47.812938 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8352 22:16:47.816697 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8353 22:16:47.822893 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8354 22:16:47.825857 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8355 22:16:47.829686 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8356 22:16:47.836873 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8357 22:16:47.839615 1 4 16 | B1->B0 | 3131 2424 | 0 0 | (0 0) (0 0)
8358 22:16:47.842945 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8359 22:16:47.849763 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8360 22:16:47.852567 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8361 22:16:47.856068 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8362 22:16:47.863058 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8363 22:16:47.865643 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8364 22:16:47.868762 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8365 22:16:47.876424 1 5 16 | B1->B0 | 3030 3333 | 1 1 | (1 0) (1 0)
8366 22:16:47.879212 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8367 22:16:47.882510 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8368 22:16:47.889483 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8369 22:16:47.892451 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8370 22:16:47.895550 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8371 22:16:47.902607 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8372 22:16:47.905308 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8373 22:16:47.908856 1 6 16 | B1->B0 | 3535 2929 | 0 0 | (0 0) (0 0)
8374 22:16:47.915389 1 6 20 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
8375 22:16:47.919568 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8376 22:16:47.922686 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8377 22:16:47.925603 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8378 22:16:47.932179 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8379 22:16:47.935402 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8380 22:16:47.939070 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8381 22:16:47.945496 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8382 22:16:47.948514 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8383 22:16:47.952843 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8384 22:16:47.959327 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8385 22:16:47.962339 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8386 22:16:47.965264 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8387 22:16:47.971867 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8388 22:16:47.975476 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8389 22:16:47.978669 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8390 22:16:47.984980 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8391 22:16:47.988787 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8392 22:16:47.992007 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8393 22:16:47.998596 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8394 22:16:48.001917 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8395 22:16:48.005287 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8396 22:16:48.012348 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8397 22:16:48.015290 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8398 22:16:48.018771 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8399 22:16:48.021989 Total UI for P1: 0, mck2ui 16
8400 22:16:48.025263 best dqsien dly found for B0: ( 1, 9, 14)
8401 22:16:48.031941 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8402 22:16:48.032541 Total UI for P1: 0, mck2ui 16
8403 22:16:48.038543 best dqsien dly found for B1: ( 1, 9, 16)
8404 22:16:48.041980 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8405 22:16:48.044941 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8406 22:16:48.045579
8407 22:16:48.048506 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8408 22:16:48.051848 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8409 22:16:48.054900 [Gating] SW calibration Done
8410 22:16:48.055357 ==
8411 22:16:48.058635 Dram Type= 6, Freq= 0, CH_1, rank 0
8412 22:16:48.062124 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8413 22:16:48.062688 ==
8414 22:16:48.065223 RX Vref Scan: 0
8415 22:16:48.065715
8416 22:16:48.066086 RX Vref 0 -> 0, step: 1
8417 22:16:48.066450
8418 22:16:48.068430 RX Delay 0 -> 252, step: 8
8419 22:16:48.071259 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8420 22:16:48.078132 iDelay=208, Bit 1, Center 127 (72 ~ 183) 112
8421 22:16:48.082699 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8422 22:16:48.084716 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8423 22:16:48.088529 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8424 22:16:48.091760 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8425 22:16:48.098743 iDelay=208, Bit 6, Center 143 (96 ~ 191) 96
8426 22:16:48.101583 iDelay=208, Bit 7, Center 131 (80 ~ 183) 104
8427 22:16:48.105713 iDelay=208, Bit 8, Center 111 (56 ~ 167) 112
8428 22:16:48.108546 iDelay=208, Bit 9, Center 115 (64 ~ 167) 104
8429 22:16:48.111609 iDelay=208, Bit 10, Center 127 (72 ~ 183) 112
8430 22:16:48.118157 iDelay=208, Bit 11, Center 123 (72 ~ 175) 104
8431 22:16:48.121841 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8432 22:16:48.124616 iDelay=208, Bit 13, Center 135 (80 ~ 191) 112
8433 22:16:48.128893 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8434 22:16:48.131422 iDelay=208, Bit 15, Center 131 (80 ~ 183) 104
8435 22:16:48.132009 ==
8436 22:16:48.134931 Dram Type= 6, Freq= 0, CH_1, rank 0
8437 22:16:48.141318 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8438 22:16:48.141884 ==
8439 22:16:48.142261 DQS Delay:
8440 22:16:48.144873 DQS0 = 0, DQS1 = 0
8441 22:16:48.145445 DQM Delay:
8442 22:16:48.148338 DQM0 = 135, DQM1 = 126
8443 22:16:48.148895 DQ Delay:
8444 22:16:48.151415 DQ0 =139, DQ1 =127, DQ2 =123, DQ3 =135
8445 22:16:48.154358 DQ4 =135, DQ5 =147, DQ6 =143, DQ7 =131
8446 22:16:48.158042 DQ8 =111, DQ9 =115, DQ10 =127, DQ11 =123
8447 22:16:48.161564 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =131
8448 22:16:48.162123
8449 22:16:48.162492
8450 22:16:48.162834 ==
8451 22:16:48.164658 Dram Type= 6, Freq= 0, CH_1, rank 0
8452 22:16:48.171113 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8453 22:16:48.171581 ==
8454 22:16:48.171951
8455 22:16:48.172349
8456 22:16:48.172762 TX Vref Scan disable
8457 22:16:48.174797 == TX Byte 0 ==
8458 22:16:48.177596 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8459 22:16:48.184587 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8460 22:16:48.185145 == TX Byte 1 ==
8461 22:16:48.188320 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8462 22:16:48.195192 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8463 22:16:48.195764 ==
8464 22:16:48.197793 Dram Type= 6, Freq= 0, CH_1, rank 0
8465 22:16:48.201034 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8466 22:16:48.201515 ==
8467 22:16:48.214954
8468 22:16:48.217561 TX Vref early break, caculate TX vref
8469 22:16:48.221297 TX Vref=16, minBit 8, minWin=20, winSum=358
8470 22:16:48.224350 TX Vref=18, minBit 8, minWin=21, winSum=366
8471 22:16:48.227671 TX Vref=20, minBit 8, minWin=21, winSum=383
8472 22:16:48.231588 TX Vref=22, minBit 8, minWin=22, winSum=387
8473 22:16:48.234230 TX Vref=24, minBit 5, minWin=24, winSum=400
8474 22:16:48.241199 TX Vref=26, minBit 5, minWin=24, winSum=407
8475 22:16:48.244752 TX Vref=28, minBit 8, minWin=24, winSum=413
8476 22:16:48.248491 TX Vref=30, minBit 1, minWin=25, winSum=415
8477 22:16:48.251037 TX Vref=32, minBit 0, minWin=25, winSum=412
8478 22:16:48.254763 TX Vref=34, minBit 11, minWin=23, winSum=397
8479 22:16:48.257862 TX Vref=36, minBit 0, minWin=23, winSum=386
8480 22:16:48.264787 [TxChooseVref] Worse bit 1, Min win 25, Win sum 415, Final Vref 30
8481 22:16:48.265359
8482 22:16:48.267776 Final TX Range 0 Vref 30
8483 22:16:48.268406
8484 22:16:48.268784 ==
8485 22:16:48.271189 Dram Type= 6, Freq= 0, CH_1, rank 0
8486 22:16:48.274770 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8487 22:16:48.275269 ==
8488 22:16:48.275607
8489 22:16:48.275921
8490 22:16:48.277558 TX Vref Scan disable
8491 22:16:48.284561 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8492 22:16:48.285076 == TX Byte 0 ==
8493 22:16:48.287304 u2DelayCellOfst[0]=17 cells (5 PI)
8494 22:16:48.291448 u2DelayCellOfst[1]=14 cells (4 PI)
8495 22:16:48.294517 u2DelayCellOfst[2]=0 cells (0 PI)
8496 22:16:48.297499 u2DelayCellOfst[3]=7 cells (2 PI)
8497 22:16:48.300647 u2DelayCellOfst[4]=7 cells (2 PI)
8498 22:16:48.304437 u2DelayCellOfst[5]=21 cells (6 PI)
8499 22:16:48.307922 u2DelayCellOfst[6]=17 cells (5 PI)
8500 22:16:48.310778 u2DelayCellOfst[7]=7 cells (2 PI)
8501 22:16:48.314154 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8502 22:16:48.317940 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8503 22:16:48.320801 == TX Byte 1 ==
8504 22:16:48.324353 u2DelayCellOfst[8]=0 cells (0 PI)
8505 22:16:48.324782 u2DelayCellOfst[9]=3 cells (1 PI)
8506 22:16:48.327246 u2DelayCellOfst[10]=10 cells (3 PI)
8507 22:16:48.330429 u2DelayCellOfst[11]=7 cells (2 PI)
8508 22:16:48.333638 u2DelayCellOfst[12]=14 cells (4 PI)
8509 22:16:48.337112 u2DelayCellOfst[13]=17 cells (5 PI)
8510 22:16:48.340814 u2DelayCellOfst[14]=17 cells (5 PI)
8511 22:16:48.343613 u2DelayCellOfst[15]=17 cells (5 PI)
8512 22:16:48.347018 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8513 22:16:48.353616 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8514 22:16:48.353801 DramC Write-DBI on
8515 22:16:48.353947 ==
8516 22:16:48.357260 Dram Type= 6, Freq= 0, CH_1, rank 0
8517 22:16:48.363415 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8518 22:16:48.363551 ==
8519 22:16:48.363657
8520 22:16:48.363755
8521 22:16:48.363849 TX Vref Scan disable
8522 22:16:48.367706 == TX Byte 0 ==
8523 22:16:48.371105 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8524 22:16:48.373779 == TX Byte 1 ==
8525 22:16:48.377308 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8526 22:16:48.380143 DramC Write-DBI off
8527 22:16:48.380241
8528 22:16:48.380336 [DATLAT]
8529 22:16:48.380427 Freq=1600, CH1 RK0
8530 22:16:48.380516
8531 22:16:48.383489 DATLAT Default: 0xf
8532 22:16:48.387043 0, 0xFFFF, sum = 0
8533 22:16:48.387129 1, 0xFFFF, sum = 0
8534 22:16:48.389982 2, 0xFFFF, sum = 0
8535 22:16:48.390069 3, 0xFFFF, sum = 0
8536 22:16:48.393556 4, 0xFFFF, sum = 0
8537 22:16:48.393643 5, 0xFFFF, sum = 0
8538 22:16:48.396780 6, 0xFFFF, sum = 0
8539 22:16:48.396866 7, 0xFFFF, sum = 0
8540 22:16:48.400454 8, 0xFFFF, sum = 0
8541 22:16:48.400542 9, 0xFFFF, sum = 0
8542 22:16:48.403625 10, 0xFFFF, sum = 0
8543 22:16:48.403713 11, 0xFFFF, sum = 0
8544 22:16:48.406855 12, 0xFFFF, sum = 0
8545 22:16:48.406942 13, 0xFFFF, sum = 0
8546 22:16:48.409947 14, 0x0, sum = 1
8547 22:16:48.410030 15, 0x0, sum = 2
8548 22:16:48.413251 16, 0x0, sum = 3
8549 22:16:48.413334 17, 0x0, sum = 4
8550 22:16:48.416388 best_step = 15
8551 22:16:48.416470
8552 22:16:48.416534 ==
8553 22:16:48.419671 Dram Type= 6, Freq= 0, CH_1, rank 0
8554 22:16:48.422887 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8555 22:16:48.422970 ==
8556 22:16:48.426952 RX Vref Scan: 1
8557 22:16:48.427035
8558 22:16:48.427100 Set Vref Range= 24 -> 127
8559 22:16:48.427161
8560 22:16:48.429791 RX Vref 24 -> 127, step: 1
8561 22:16:48.429874
8562 22:16:48.433004 RX Delay 11 -> 252, step: 4
8563 22:16:48.433086
8564 22:16:48.436386 Set Vref, RX VrefLevel [Byte0]: 24
8565 22:16:48.439725 [Byte1]: 24
8566 22:16:48.439832
8567 22:16:48.442906 Set Vref, RX VrefLevel [Byte0]: 25
8568 22:16:48.446446 [Byte1]: 25
8569 22:16:48.449675
8570 22:16:48.449757 Set Vref, RX VrefLevel [Byte0]: 26
8571 22:16:48.453327 [Byte1]: 26
8572 22:16:48.457336
8573 22:16:48.457419 Set Vref, RX VrefLevel [Byte0]: 27
8574 22:16:48.461252 [Byte1]: 27
8575 22:16:48.465550
8576 22:16:48.465632 Set Vref, RX VrefLevel [Byte0]: 28
8577 22:16:48.468341 [Byte1]: 28
8578 22:16:48.473386
8579 22:16:48.473471 Set Vref, RX VrefLevel [Byte0]: 29
8580 22:16:48.479779 [Byte1]: 29
8581 22:16:48.479888
8582 22:16:48.482234 Set Vref, RX VrefLevel [Byte0]: 30
8583 22:16:48.485731 [Byte1]: 30
8584 22:16:48.485821
8585 22:16:48.489338 Set Vref, RX VrefLevel [Byte0]: 31
8586 22:16:48.492557 [Byte1]: 31
8587 22:16:48.492639
8588 22:16:48.495904 Set Vref, RX VrefLevel [Byte0]: 32
8589 22:16:48.499182 [Byte1]: 32
8590 22:16:48.503568
8591 22:16:48.503651 Set Vref, RX VrefLevel [Byte0]: 33
8592 22:16:48.507227 [Byte1]: 33
8593 22:16:48.511158
8594 22:16:48.511292 Set Vref, RX VrefLevel [Byte0]: 34
8595 22:16:48.514027 [Byte1]: 34
8596 22:16:48.518994
8597 22:16:48.519128 Set Vref, RX VrefLevel [Byte0]: 35
8598 22:16:48.521667 [Byte1]: 35
8599 22:16:48.526140
8600 22:16:48.526272 Set Vref, RX VrefLevel [Byte0]: 36
8601 22:16:48.529193 [Byte1]: 36
8602 22:16:48.534028
8603 22:16:48.534163 Set Vref, RX VrefLevel [Byte0]: 37
8604 22:16:48.536848 [Byte1]: 37
8605 22:16:48.541074
8606 22:16:48.541205 Set Vref, RX VrefLevel [Byte0]: 38
8607 22:16:48.544533 [Byte1]: 38
8608 22:16:48.548640
8609 22:16:48.548773 Set Vref, RX VrefLevel [Byte0]: 39
8610 22:16:48.551936 [Byte1]: 39
8611 22:16:48.556777
8612 22:16:48.556909 Set Vref, RX VrefLevel [Byte0]: 40
8613 22:16:48.559913 [Byte1]: 40
8614 22:16:48.564412
8615 22:16:48.564538 Set Vref, RX VrefLevel [Byte0]: 41
8616 22:16:48.567595 [Byte1]: 41
8617 22:16:48.571474
8618 22:16:48.571556 Set Vref, RX VrefLevel [Byte0]: 42
8619 22:16:48.575037 [Byte1]: 42
8620 22:16:48.579229
8621 22:16:48.579309 Set Vref, RX VrefLevel [Byte0]: 43
8622 22:16:48.583049 [Byte1]: 43
8623 22:16:48.587416
8624 22:16:48.587499 Set Vref, RX VrefLevel [Byte0]: 44
8625 22:16:48.590323 [Byte1]: 44
8626 22:16:48.594416
8627 22:16:48.594497 Set Vref, RX VrefLevel [Byte0]: 45
8628 22:16:48.597786 [Byte1]: 45
8629 22:16:48.601976
8630 22:16:48.602057 Set Vref, RX VrefLevel [Byte0]: 46
8631 22:16:48.605561 [Byte1]: 46
8632 22:16:48.609727
8633 22:16:48.609808 Set Vref, RX VrefLevel [Byte0]: 47
8634 22:16:48.613477 [Byte1]: 47
8635 22:16:48.617455
8636 22:16:48.617536 Set Vref, RX VrefLevel [Byte0]: 48
8637 22:16:48.621179 [Byte1]: 48
8638 22:16:48.624916
8639 22:16:48.624997 Set Vref, RX VrefLevel [Byte0]: 49
8640 22:16:48.628095 [Byte1]: 49
8641 22:16:48.632606
8642 22:16:48.632687 Set Vref, RX VrefLevel [Byte0]: 50
8643 22:16:48.636112 [Byte1]: 50
8644 22:16:48.640128
8645 22:16:48.640210 Set Vref, RX VrefLevel [Byte0]: 51
8646 22:16:48.643365 [Byte1]: 51
8647 22:16:48.647580
8648 22:16:48.647661 Set Vref, RX VrefLevel [Byte0]: 52
8649 22:16:48.651505 [Byte1]: 52
8650 22:16:48.655563
8651 22:16:48.655643 Set Vref, RX VrefLevel [Byte0]: 53
8652 22:16:48.659238 [Byte1]: 53
8653 22:16:48.663433
8654 22:16:48.663514 Set Vref, RX VrefLevel [Byte0]: 54
8655 22:16:48.666319 [Byte1]: 54
8656 22:16:48.671109
8657 22:16:48.671193 Set Vref, RX VrefLevel [Byte0]: 55
8658 22:16:48.673981 [Byte1]: 55
8659 22:16:48.678244
8660 22:16:48.678326 Set Vref, RX VrefLevel [Byte0]: 56
8661 22:16:48.681368 [Byte1]: 56
8662 22:16:48.685566
8663 22:16:48.685647 Set Vref, RX VrefLevel [Byte0]: 57
8664 22:16:48.689159 [Byte1]: 57
8665 22:16:48.693360
8666 22:16:48.693441 Set Vref, RX VrefLevel [Byte0]: 58
8667 22:16:48.696989 [Byte1]: 58
8668 22:16:48.701232
8669 22:16:48.701314 Set Vref, RX VrefLevel [Byte0]: 59
8670 22:16:48.704379 [Byte1]: 59
8671 22:16:48.708494
8672 22:16:48.708576 Set Vref, RX VrefLevel [Byte0]: 60
8673 22:16:48.712158 [Byte1]: 60
8674 22:16:48.716832
8675 22:16:48.716915 Set Vref, RX VrefLevel [Byte0]: 61
8676 22:16:48.719464 [Byte1]: 61
8677 22:16:48.724208
8678 22:16:48.724291 Set Vref, RX VrefLevel [Byte0]: 62
8679 22:16:48.727030 [Byte1]: 62
8680 22:16:48.732037
8681 22:16:48.732144 Set Vref, RX VrefLevel [Byte0]: 63
8682 22:16:48.734917 [Byte1]: 63
8683 22:16:48.739699
8684 22:16:48.739779 Set Vref, RX VrefLevel [Byte0]: 64
8685 22:16:48.742534 [Byte1]: 64
8686 22:16:48.746923
8687 22:16:48.747006 Set Vref, RX VrefLevel [Byte0]: 65
8688 22:16:48.750148 [Byte1]: 65
8689 22:16:48.754171
8690 22:16:48.754253 Set Vref, RX VrefLevel [Byte0]: 66
8691 22:16:48.757589 [Byte1]: 66
8692 22:16:48.762173
8693 22:16:48.762253 Set Vref, RX VrefLevel [Byte0]: 67
8694 22:16:48.765380 [Byte1]: 67
8695 22:16:48.769800
8696 22:16:48.769883 Set Vref, RX VrefLevel [Byte0]: 68
8697 22:16:48.772724 [Byte1]: 68
8698 22:16:48.777559
8699 22:16:48.777640 Set Vref, RX VrefLevel [Byte0]: 69
8700 22:16:48.780776 [Byte1]: 69
8701 22:16:48.784854
8702 22:16:48.784934 Set Vref, RX VrefLevel [Byte0]: 70
8703 22:16:48.787846 [Byte1]: 70
8704 22:16:48.793101
8705 22:16:48.793184 Set Vref, RX VrefLevel [Byte0]: 71
8706 22:16:48.796283 [Byte1]: 71
8707 22:16:48.799941
8708 22:16:48.800094 Set Vref, RX VrefLevel [Byte0]: 72
8709 22:16:48.803231 [Byte1]: 72
8710 22:16:48.807415
8711 22:16:48.811087 Set Vref, RX VrefLevel [Byte0]: 73
8712 22:16:48.815143 [Byte1]: 73
8713 22:16:48.815224
8714 22:16:48.817502 Set Vref, RX VrefLevel [Byte0]: 74
8715 22:16:48.820820 [Byte1]: 74
8716 22:16:48.820940
8717 22:16:48.824435 Final RX Vref Byte 0 = 58 to rank0
8718 22:16:48.827388 Final RX Vref Byte 1 = 57 to rank0
8719 22:16:48.830842 Final RX Vref Byte 0 = 58 to rank1
8720 22:16:48.835246 Final RX Vref Byte 1 = 57 to rank1==
8721 22:16:48.837917 Dram Type= 6, Freq= 0, CH_1, rank 0
8722 22:16:48.840657 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8723 22:16:48.840741 ==
8724 22:16:48.843730 DQS Delay:
8725 22:16:48.843836 DQS0 = 0, DQS1 = 0
8726 22:16:48.843929 DQM Delay:
8727 22:16:48.847379 DQM0 = 131, DQM1 = 124
8728 22:16:48.847461 DQ Delay:
8729 22:16:48.850553 DQ0 =134, DQ1 =126, DQ2 =120, DQ3 =130
8730 22:16:48.853796 DQ4 =130, DQ5 =142, DQ6 =142, DQ7 =128
8731 22:16:48.860777 DQ8 =110, DQ9 =112, DQ10 =128, DQ11 =118
8732 22:16:48.863909 DQ12 =132, DQ13 =132, DQ14 =130, DQ15 =132
8733 22:16:48.864043
8734 22:16:48.864108
8735 22:16:48.864167
8736 22:16:48.867361 [DramC_TX_OE_Calibration] TA2
8737 22:16:48.870421 Original DQ_B0 (3 6) =30, OEN = 27
8738 22:16:48.873744 Original DQ_B1 (3 6) =30, OEN = 27
8739 22:16:48.873829 24, 0x0, End_B0=24 End_B1=24
8740 22:16:48.877040 25, 0x0, End_B0=25 End_B1=25
8741 22:16:48.880681 26, 0x0, End_B0=26 End_B1=26
8742 22:16:48.883568 27, 0x0, End_B0=27 End_B1=27
8743 22:16:48.883651 28, 0x0, End_B0=28 End_B1=28
8744 22:16:48.886724 29, 0x0, End_B0=29 End_B1=29
8745 22:16:48.890172 30, 0x0, End_B0=30 End_B1=30
8746 22:16:48.893587 31, 0x4141, End_B0=30 End_B1=30
8747 22:16:48.896755 Byte0 end_step=30 best_step=27
8748 22:16:48.899861 Byte1 end_step=30 best_step=27
8749 22:16:48.899989 Byte0 TX OE(2T, 0.5T) = (3, 3)
8750 22:16:48.903229 Byte1 TX OE(2T, 0.5T) = (3, 3)
8751 22:16:48.903311
8752 22:16:48.903376
8753 22:16:48.913481 [DQSOSCAuto] RK0, (LSB)MR18= 0x14fe, (MSB)MR19= 0x302, tDQSOscB0 = 411 ps tDQSOscB1 = 399 ps
8754 22:16:48.916715 CH1 RK0: MR19=302, MR18=14FE
8755 22:16:48.919864 CH1_RK0: MR19=0x302, MR18=0x14FE, DQSOSC=399, MR23=63, INC=23, DEC=15
8756 22:16:48.923753
8757 22:16:48.926246 ----->DramcWriteLeveling(PI) begin...
8758 22:16:48.926330 ==
8759 22:16:48.929692 Dram Type= 6, Freq= 0, CH_1, rank 1
8760 22:16:48.933032 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8761 22:16:48.933115 ==
8762 22:16:48.936410 Write leveling (Byte 0): 27 => 27
8763 22:16:48.939829 Write leveling (Byte 1): 28 => 28
8764 22:16:48.943029 DramcWriteLeveling(PI) end<-----
8765 22:16:48.943111
8766 22:16:48.943176 ==
8767 22:16:48.946621 Dram Type= 6, Freq= 0, CH_1, rank 1
8768 22:16:48.949933 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8769 22:16:48.950018 ==
8770 22:16:48.953089 [Gating] SW mode calibration
8771 22:16:48.959724 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8772 22:16:48.966484 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8773 22:16:48.969404 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8774 22:16:48.972872 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8775 22:16:48.979733 1 4 8 | B1->B0 | 2323 3030 | 0 1 | (0 0) (1 1)
8776 22:16:48.982807 1 4 12 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
8777 22:16:48.986058 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8778 22:16:48.992954 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8779 22:16:48.996257 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8780 22:16:48.999525 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8781 22:16:49.006015 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8782 22:16:49.009042 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8783 22:16:49.012397 1 5 8 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 0)
8784 22:16:49.019399 1 5 12 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)
8785 22:16:49.022973 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8786 22:16:49.025559 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8787 22:16:49.032651 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8788 22:16:49.035828 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8789 22:16:49.038931 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8790 22:16:49.046166 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8791 22:16:49.048852 1 6 8 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
8792 22:16:49.052526 1 6 12 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
8793 22:16:49.059081 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8794 22:16:49.062646 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8795 22:16:49.065641 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8796 22:16:49.068811 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8797 22:16:49.076160 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8798 22:16:49.079693 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8799 22:16:49.082534 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8800 22:16:49.090062 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8801 22:16:49.092696 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8802 22:16:49.095918 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8803 22:16:49.102183 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8804 22:16:49.105678 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8805 22:16:49.109115 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8806 22:16:49.115726 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8807 22:16:49.119217 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8808 22:16:49.122845 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8809 22:16:49.129084 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8810 22:16:49.132392 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8811 22:16:49.135621 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8812 22:16:49.142370 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8813 22:16:49.146006 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8814 22:16:49.148839 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8815 22:16:49.155440 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8816 22:16:49.159609 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8817 22:16:49.162788 Total UI for P1: 0, mck2ui 16
8818 22:16:49.165533 best dqsien dly found for B0: ( 1, 9, 6)
8819 22:16:49.169218 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8820 22:16:49.172448 Total UI for P1: 0, mck2ui 16
8821 22:16:49.175560 best dqsien dly found for B1: ( 1, 9, 10)
8822 22:16:49.179227 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8823 22:16:49.182532 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8824 22:16:49.183051
8825 22:16:49.189262 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8826 22:16:49.192099 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8827 22:16:49.192520 [Gating] SW calibration Done
8828 22:16:49.195661 ==
8829 22:16:49.199217 Dram Type= 6, Freq= 0, CH_1, rank 1
8830 22:16:49.202222 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8831 22:16:49.202645 ==
8832 22:16:49.202978 RX Vref Scan: 0
8833 22:16:49.203291
8834 22:16:49.204951 RX Vref 0 -> 0, step: 1
8835 22:16:49.205366
8836 22:16:49.208758 RX Delay 0 -> 252, step: 8
8837 22:16:49.211987 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8838 22:16:49.215346 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8839 22:16:49.218308 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8840 22:16:49.225165 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8841 22:16:49.228308 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8842 22:16:49.232258 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8843 22:16:49.235588 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8844 22:16:49.238221 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8845 22:16:49.245654 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8846 22:16:49.248118 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8847 22:16:49.251858 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8848 22:16:49.255097 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8849 22:16:49.258381 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8850 22:16:49.264657 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
8851 22:16:49.268348 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8852 22:16:49.271444 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8853 22:16:49.271895 ==
8854 22:16:49.274816 Dram Type= 6, Freq= 0, CH_1, rank 1
8855 22:16:49.278102 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8856 22:16:49.281779 ==
8857 22:16:49.282311 DQS Delay:
8858 22:16:49.282652 DQS0 = 0, DQS1 = 0
8859 22:16:49.284799 DQM Delay:
8860 22:16:49.285223 DQM0 = 133, DQM1 = 128
8861 22:16:49.288419 DQ Delay:
8862 22:16:49.291317 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =135
8863 22:16:49.294850 DQ4 =135, DQ5 =147, DQ6 =139, DQ7 =127
8864 22:16:49.298188 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8865 22:16:49.301660 DQ12 =135, DQ13 =139, DQ14 =135, DQ15 =135
8866 22:16:49.302085
8867 22:16:49.302443
8868 22:16:49.302760 ==
8869 22:16:49.305015 Dram Type= 6, Freq= 0, CH_1, rank 1
8870 22:16:49.308584 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8871 22:16:49.309120 ==
8872 22:16:49.309468
8873 22:16:49.311909
8874 22:16:49.312449 TX Vref Scan disable
8875 22:16:49.315015 == TX Byte 0 ==
8876 22:16:49.318783 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8877 22:16:49.321276 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8878 22:16:49.324612 == TX Byte 1 ==
8879 22:16:49.328246 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8880 22:16:49.331454 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8881 22:16:49.331993 ==
8882 22:16:49.335411 Dram Type= 6, Freq= 0, CH_1, rank 1
8883 22:16:49.341410 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8884 22:16:49.341944 ==
8885 22:16:49.354186
8886 22:16:49.357322 TX Vref early break, caculate TX vref
8887 22:16:49.360354 TX Vref=16, minBit 8, minWin=21, winSum=367
8888 22:16:49.363271 TX Vref=18, minBit 0, minWin=23, winSum=381
8889 22:16:49.367139 TX Vref=20, minBit 0, minWin=23, winSum=387
8890 22:16:49.370168 TX Vref=22, minBit 8, minWin=24, winSum=397
8891 22:16:49.373387 TX Vref=24, minBit 0, minWin=24, winSum=407
8892 22:16:49.380551 TX Vref=26, minBit 0, minWin=25, winSum=412
8893 22:16:49.383303 TX Vref=28, minBit 0, minWin=25, winSum=417
8894 22:16:49.386639 TX Vref=30, minBit 0, minWin=24, winSum=417
8895 22:16:49.389694 TX Vref=32, minBit 0, minWin=25, winSum=410
8896 22:16:49.393723 TX Vref=34, minBit 0, minWin=23, winSum=397
8897 22:16:49.396872 TX Vref=36, minBit 0, minWin=23, winSum=389
8898 22:16:49.403134 [TxChooseVref] Worse bit 0, Min win 25, Win sum 417, Final Vref 28
8899 22:16:49.403663
8900 22:16:49.406844 Final TX Range 0 Vref 28
8901 22:16:49.407365
8902 22:16:49.407702 ==
8903 22:16:49.410009 Dram Type= 6, Freq= 0, CH_1, rank 1
8904 22:16:49.413254 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8905 22:16:49.413786 ==
8906 22:16:49.414127
8907 22:16:49.416669
8908 22:16:49.417187 TX Vref Scan disable
8909 22:16:49.423089 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8910 22:16:49.423600 == TX Byte 0 ==
8911 22:16:49.426685 u2DelayCellOfst[0]=17 cells (5 PI)
8912 22:16:49.429497 u2DelayCellOfst[1]=10 cells (3 PI)
8913 22:16:49.432912 u2DelayCellOfst[2]=0 cells (0 PI)
8914 22:16:49.436154 u2DelayCellOfst[3]=7 cells (2 PI)
8915 22:16:49.439761 u2DelayCellOfst[4]=7 cells (2 PI)
8916 22:16:49.443240 u2DelayCellOfst[5]=21 cells (6 PI)
8917 22:16:49.446564 u2DelayCellOfst[6]=17 cells (5 PI)
8918 22:16:49.449968 u2DelayCellOfst[7]=7 cells (2 PI)
8919 22:16:49.452952 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8920 22:16:49.456461 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8921 22:16:49.460020 == TX Byte 1 ==
8922 22:16:49.463060 u2DelayCellOfst[8]=0 cells (0 PI)
8923 22:16:49.466028 u2DelayCellOfst[9]=3 cells (1 PI)
8924 22:16:49.466456 u2DelayCellOfst[10]=10 cells (3 PI)
8925 22:16:49.469228 u2DelayCellOfst[11]=3 cells (1 PI)
8926 22:16:49.472612 u2DelayCellOfst[12]=14 cells (4 PI)
8927 22:16:49.476023 u2DelayCellOfst[13]=14 cells (4 PI)
8928 22:16:49.479660 u2DelayCellOfst[14]=17 cells (5 PI)
8929 22:16:49.482944 u2DelayCellOfst[15]=14 cells (4 PI)
8930 22:16:49.489272 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8931 22:16:49.493436 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8932 22:16:49.493972 DramC Write-DBI on
8933 22:16:49.494316 ==
8934 22:16:49.496122 Dram Type= 6, Freq= 0, CH_1, rank 1
8935 22:16:49.502586 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8936 22:16:49.503109 ==
8937 22:16:49.503456
8938 22:16:49.503767
8939 22:16:49.504095 TX Vref Scan disable
8940 22:16:49.506748 == TX Byte 0 ==
8941 22:16:49.509996 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8942 22:16:49.513341 == TX Byte 1 ==
8943 22:16:49.516549 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8944 22:16:49.519720 DramC Write-DBI off
8945 22:16:49.520341
8946 22:16:49.520683 [DATLAT]
8947 22:16:49.521018 Freq=1600, CH1 RK1
8948 22:16:49.521396
8949 22:16:49.522945 DATLAT Default: 0xf
8950 22:16:49.523366 0, 0xFFFF, sum = 0
8951 22:16:49.526874 1, 0xFFFF, sum = 0
8952 22:16:49.529862 2, 0xFFFF, sum = 0
8953 22:16:49.530305 3, 0xFFFF, sum = 0
8954 22:16:49.533532 4, 0xFFFF, sum = 0
8955 22:16:49.533974 5, 0xFFFF, sum = 0
8956 22:16:49.536726 6, 0xFFFF, sum = 0
8957 22:16:49.536810 7, 0xFFFF, sum = 0
8958 22:16:49.540570 8, 0xFFFF, sum = 0
8959 22:16:49.540709 9, 0xFFFF, sum = 0
8960 22:16:49.542795 10, 0xFFFF, sum = 0
8961 22:16:49.542921 11, 0xFFFF, sum = 0
8962 22:16:49.546295 12, 0xFFFF, sum = 0
8963 22:16:49.546392 13, 0xFFFF, sum = 0
8964 22:16:49.549714 14, 0x0, sum = 1
8965 22:16:49.549811 15, 0x0, sum = 2
8966 22:16:49.553346 16, 0x0, sum = 3
8967 22:16:49.553521 17, 0x0, sum = 4
8968 22:16:49.556609 best_step = 15
8969 22:16:49.556783
8970 22:16:49.556866 ==
8971 22:16:49.560137 Dram Type= 6, Freq= 0, CH_1, rank 1
8972 22:16:49.563713 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8973 22:16:49.563895 ==
8974 22:16:49.564000 RX Vref Scan: 0
8975 22:16:49.564093
8976 22:16:49.566514 RX Vref 0 -> 0, step: 1
8977 22:16:49.566659
8978 22:16:49.570172 RX Delay 11 -> 252, step: 4
8979 22:16:49.573629 iDelay=195, Bit 0, Center 132 (83 ~ 182) 100
8980 22:16:49.580323 iDelay=195, Bit 1, Center 124 (71 ~ 178) 108
8981 22:16:49.583432 iDelay=195, Bit 2, Center 118 (67 ~ 170) 104
8982 22:16:49.586573 iDelay=195, Bit 3, Center 126 (75 ~ 178) 104
8983 22:16:49.590237 iDelay=195, Bit 4, Center 130 (79 ~ 182) 104
8984 22:16:49.593143 iDelay=195, Bit 5, Center 144 (95 ~ 194) 100
8985 22:16:49.599918 iDelay=195, Bit 6, Center 138 (87 ~ 190) 104
8986 22:16:49.603414 iDelay=195, Bit 7, Center 126 (75 ~ 178) 104
8987 22:16:49.606268 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
8988 22:16:49.609880 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8989 22:16:49.613349 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8990 22:16:49.619536 iDelay=195, Bit 11, Center 118 (63 ~ 174) 112
8991 22:16:49.623225 iDelay=195, Bit 12, Center 134 (83 ~ 186) 104
8992 22:16:49.626091 iDelay=195, Bit 13, Center 134 (83 ~ 186) 104
8993 22:16:49.630006 iDelay=195, Bit 14, Center 134 (79 ~ 190) 112
8994 22:16:49.632640 iDelay=195, Bit 15, Center 136 (83 ~ 190) 108
8995 22:16:49.636463 ==
8996 22:16:49.639499 Dram Type= 6, Freq= 0, CH_1, rank 1
8997 22:16:49.643321 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8998 22:16:49.643748 ==
8999 22:16:49.644133 DQS Delay:
9000 22:16:49.647014 DQS0 = 0, DQS1 = 0
9001 22:16:49.647316 DQM Delay:
9002 22:16:49.649405 DQM0 = 129, DQM1 = 126
9003 22:16:49.649708 DQ Delay:
9004 22:16:49.652703 DQ0 =132, DQ1 =124, DQ2 =118, DQ3 =126
9005 22:16:49.656369 DQ4 =130, DQ5 =144, DQ6 =138, DQ7 =126
9006 22:16:49.659271 DQ8 =114, DQ9 =112, DQ10 =128, DQ11 =118
9007 22:16:49.662876 DQ12 =134, DQ13 =134, DQ14 =134, DQ15 =136
9008 22:16:49.663146
9009 22:16:49.663304
9010 22:16:49.663447
9011 22:16:49.666046 [DramC_TX_OE_Calibration] TA2
9012 22:16:49.669392 Original DQ_B0 (3 6) =30, OEN = 27
9013 22:16:49.672328 Original DQ_B1 (3 6) =30, OEN = 27
9014 22:16:49.676005 24, 0x0, End_B0=24 End_B1=24
9015 22:16:49.679546 25, 0x0, End_B0=25 End_B1=25
9016 22:16:49.679821 26, 0x0, End_B0=26 End_B1=26
9017 22:16:49.682743 27, 0x0, End_B0=27 End_B1=27
9018 22:16:49.686396 28, 0x0, End_B0=28 End_B1=28
9019 22:16:49.689380 29, 0x0, End_B0=29 End_B1=29
9020 22:16:49.689652 30, 0x0, End_B0=30 End_B1=30
9021 22:16:49.692599 31, 0x5151, End_B0=30 End_B1=30
9022 22:16:49.696174 Byte0 end_step=30 best_step=27
9023 22:16:49.699327 Byte1 end_step=30 best_step=27
9024 22:16:49.702767 Byte0 TX OE(2T, 0.5T) = (3, 3)
9025 22:16:49.705992 Byte1 TX OE(2T, 0.5T) = (3, 3)
9026 22:16:49.706400
9027 22:16:49.706736
9028 22:16:49.712740 [DQSOSCAuto] RK1, (LSB)MR18= 0x1016, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 401 ps
9029 22:16:49.716175 CH1 RK1: MR19=303, MR18=1016
9030 22:16:49.723102 CH1_RK1: MR19=0x303, MR18=0x1016, DQSOSC=398, MR23=63, INC=23, DEC=15
9031 22:16:49.726291 [RxdqsGatingPostProcess] freq 1600
9032 22:16:49.733149 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9033 22:16:49.733684 best DQS0 dly(2T, 0.5T) = (1, 1)
9034 22:16:49.736071 best DQS1 dly(2T, 0.5T) = (1, 1)
9035 22:16:49.739283 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9036 22:16:49.742591 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9037 22:16:49.745947 best DQS0 dly(2T, 0.5T) = (1, 1)
9038 22:16:49.749821 best DQS1 dly(2T, 0.5T) = (1, 1)
9039 22:16:49.752275 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9040 22:16:49.756049 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9041 22:16:49.759648 Pre-setting of DQS Precalculation
9042 22:16:49.762984 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9043 22:16:49.772650 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9044 22:16:49.779455 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9045 22:16:49.780008
9046 22:16:49.780354
9047 22:16:49.782778 [Calibration Summary] 3200 Mbps
9048 22:16:49.783309 CH 0, Rank 0
9049 22:16:49.785906 SW Impedance : PASS
9050 22:16:49.786423 DUTY Scan : NO K
9051 22:16:49.789152 ZQ Calibration : PASS
9052 22:16:49.792478 Jitter Meter : NO K
9053 22:16:49.792909 CBT Training : PASS
9054 22:16:49.796100 Write leveling : PASS
9055 22:16:49.799242 RX DQS gating : PASS
9056 22:16:49.799762 RX DQ/DQS(RDDQC) : PASS
9057 22:16:49.802664 TX DQ/DQS : PASS
9058 22:16:49.805853 RX DATLAT : PASS
9059 22:16:49.806377 RX DQ/DQS(Engine): PASS
9060 22:16:49.809008 TX OE : PASS
9061 22:16:49.809532 All Pass.
9062 22:16:49.809878
9063 22:16:49.810197 CH 0, Rank 1
9064 22:16:49.812638 SW Impedance : PASS
9065 22:16:49.815652 DUTY Scan : NO K
9066 22:16:49.816202 ZQ Calibration : PASS
9067 22:16:49.818971 Jitter Meter : NO K
9068 22:16:49.822881 CBT Training : PASS
9069 22:16:49.823397 Write leveling : PASS
9070 22:16:49.825585 RX DQS gating : PASS
9071 22:16:49.828642 RX DQ/DQS(RDDQC) : PASS
9072 22:16:49.829068 TX DQ/DQS : PASS
9073 22:16:49.832337 RX DATLAT : PASS
9074 22:16:49.836080 RX DQ/DQS(Engine): PASS
9075 22:16:49.836594 TX OE : PASS
9076 22:16:49.839215 All Pass.
9077 22:16:49.839727
9078 22:16:49.840116 CH 1, Rank 0
9079 22:16:49.842605 SW Impedance : PASS
9080 22:16:49.843116 DUTY Scan : NO K
9081 22:16:49.845300 ZQ Calibration : PASS
9082 22:16:49.848871 Jitter Meter : NO K
9083 22:16:49.849394 CBT Training : PASS
9084 22:16:49.852012 Write leveling : PASS
9085 22:16:49.856108 RX DQS gating : PASS
9086 22:16:49.856534 RX DQ/DQS(RDDQC) : PASS
9087 22:16:49.859251 TX DQ/DQS : PASS
9088 22:16:49.859781 RX DATLAT : PASS
9089 22:16:49.862280 RX DQ/DQS(Engine): PASS
9090 22:16:49.865387 TX OE : PASS
9091 22:16:49.865838 All Pass.
9092 22:16:49.866179
9093 22:16:49.866534 CH 1, Rank 1
9094 22:16:49.868638 SW Impedance : PASS
9095 22:16:49.871911 DUTY Scan : NO K
9096 22:16:49.872579 ZQ Calibration : PASS
9097 22:16:49.875710 Jitter Meter : NO K
9098 22:16:49.878845 CBT Training : PASS
9099 22:16:49.879360 Write leveling : PASS
9100 22:16:49.881473 RX DQS gating : PASS
9101 22:16:49.885196 RX DQ/DQS(RDDQC) : PASS
9102 22:16:49.885718 TX DQ/DQS : PASS
9103 22:16:49.888606 RX DATLAT : PASS
9104 22:16:49.892132 RX DQ/DQS(Engine): PASS
9105 22:16:49.892650 TX OE : PASS
9106 22:16:49.895320 All Pass.
9107 22:16:49.895840
9108 22:16:49.896234 DramC Write-DBI on
9109 22:16:49.898595 PER_BANK_REFRESH: Hybrid Mode
9110 22:16:49.899137 TX_TRACKING: ON
9111 22:16:49.908179 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9112 22:16:49.918395 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9113 22:16:49.925476 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9114 22:16:49.928483 [FAST_K] Save calibration result to emmc
9115 22:16:49.932127 sync common calibartion params.
9116 22:16:49.932641 sync cbt_mode0:1, 1:1
9117 22:16:49.934938 dram_init: ddr_geometry: 2
9118 22:16:49.938295 dram_init: ddr_geometry: 2
9119 22:16:49.938862 dram_init: ddr_geometry: 2
9120 22:16:49.941643 0:dram_rank_size:100000000
9121 22:16:49.944821 1:dram_rank_size:100000000
9122 22:16:49.951921 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9123 22:16:49.952492 DFS_SHUFFLE_HW_MODE: ON
9124 22:16:49.955274 dramc_set_vcore_voltage set vcore to 725000
9125 22:16:49.958132 Read voltage for 1600, 0
9126 22:16:49.958656 Vio18 = 0
9127 22:16:49.961372 Vcore = 725000
9128 22:16:49.961794 Vdram = 0
9129 22:16:49.962131 Vddq = 0
9130 22:16:49.965228 Vmddr = 0
9131 22:16:49.965754 switch to 3200 Mbps bootup
9132 22:16:49.969068 [DramcRunTimeConfig]
9133 22:16:49.969594 PHYPLL
9134 22:16:49.971364 DPM_CONTROL_AFTERK: ON
9135 22:16:49.971782 PER_BANK_REFRESH: ON
9136 22:16:49.974669 REFRESH_OVERHEAD_REDUCTION: ON
9137 22:16:49.978742 CMD_PICG_NEW_MODE: OFF
9138 22:16:49.979269 XRTWTW_NEW_MODE: ON
9139 22:16:49.981238 XRTRTR_NEW_MODE: ON
9140 22:16:49.981656 TX_TRACKING: ON
9141 22:16:49.984650 RDSEL_TRACKING: OFF
9142 22:16:49.988731 DQS Precalculation for DVFS: ON
9143 22:16:49.989150 RX_TRACKING: OFF
9144 22:16:49.991142 HW_GATING DBG: ON
9145 22:16:49.991560 ZQCS_ENABLE_LP4: ON
9146 22:16:49.995116 RX_PICG_NEW_MODE: ON
9147 22:16:49.995535 TX_PICG_NEW_MODE: ON
9148 22:16:49.997709 ENABLE_RX_DCM_DPHY: ON
9149 22:16:50.001728 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9150 22:16:50.004778 DUMMY_READ_FOR_TRACKING: OFF
9151 22:16:50.005201 !!! SPM_CONTROL_AFTERK: OFF
9152 22:16:50.007878 !!! SPM could not control APHY
9153 22:16:50.011533 IMPEDANCE_TRACKING: ON
9154 22:16:50.012089 TEMP_SENSOR: ON
9155 22:16:50.015154 HW_SAVE_FOR_SR: OFF
9156 22:16:50.017962 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9157 22:16:50.020973 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9158 22:16:50.021393 Read ODT Tracking: ON
9159 22:16:50.024484 Refresh Rate DeBounce: ON
9160 22:16:50.028244 DFS_NO_QUEUE_FLUSH: ON
9161 22:16:50.031342 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9162 22:16:50.034620 ENABLE_DFS_RUNTIME_MRW: OFF
9163 22:16:50.035041 DDR_RESERVE_NEW_MODE: ON
9164 22:16:50.038040 MR_CBT_SWITCH_FREQ: ON
9165 22:16:50.040774 =========================
9166 22:16:50.058472 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9167 22:16:50.062468 dram_init: ddr_geometry: 2
9168 22:16:50.080411 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9169 22:16:50.083168 dram_init: dram init end (result: 0)
9170 22:16:50.089819 DRAM-K: Full calibration passed in 24559 msecs
9171 22:16:50.092921 MRC: failed to locate region type 0.
9172 22:16:50.093382 DRAM rank0 size:0x100000000,
9173 22:16:50.096493 DRAM rank1 size=0x100000000
9174 22:16:50.106763 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9175 22:16:50.113009 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9176 22:16:50.120369 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9177 22:16:50.126506 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9178 22:16:50.129721 DRAM rank0 size:0x100000000,
9179 22:16:50.133285 DRAM rank1 size=0x100000000
9180 22:16:50.133804 CBMEM:
9181 22:16:50.136329 IMD: root @ 0xfffff000 254 entries.
9182 22:16:50.140117 IMD: root @ 0xffffec00 62 entries.
9183 22:16:50.143665 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9184 22:16:50.146538 WARNING: RO_VPD is uninitialized or empty.
9185 22:16:50.153142 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9186 22:16:50.160483 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9187 22:16:50.172742 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9188 22:16:50.184307 BS: romstage times (exec / console): total (unknown) / 24067 ms
9189 22:16:50.184830
9190 22:16:50.185163
9191 22:16:50.194210 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9192 22:16:50.197795 ARM64: Exception handlers installed.
9193 22:16:50.201032 ARM64: Testing exception
9194 22:16:50.203585 ARM64: Done test exception
9195 22:16:50.204041 Enumerating buses...
9196 22:16:50.207113 Show all devs... Before device enumeration.
9197 22:16:50.210028 Root Device: enabled 1
9198 22:16:50.214089 CPU_CLUSTER: 0: enabled 1
9199 22:16:50.214626 CPU: 00: enabled 1
9200 22:16:50.217232 Compare with tree...
9201 22:16:50.217761 Root Device: enabled 1
9202 22:16:50.220447 CPU_CLUSTER: 0: enabled 1
9203 22:16:50.223694 CPU: 00: enabled 1
9204 22:16:50.224274 Root Device scanning...
9205 22:16:50.227614 scan_static_bus for Root Device
9206 22:16:50.230424 CPU_CLUSTER: 0 enabled
9207 22:16:50.233643 scan_static_bus for Root Device done
9208 22:16:50.236823 scan_bus: bus Root Device finished in 8 msecs
9209 22:16:50.237296 done
9210 22:16:50.243926 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9211 22:16:50.246945 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9212 22:16:50.254149 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9213 22:16:50.257363 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9214 22:16:50.260313 Allocating resources...
9215 22:16:50.263683 Reading resources...
9216 22:16:50.266929 Root Device read_resources bus 0 link: 0
9217 22:16:50.267450 DRAM rank0 size:0x100000000,
9218 22:16:50.270743 DRAM rank1 size=0x100000000
9219 22:16:50.273652 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9220 22:16:50.276683 CPU: 00 missing read_resources
9221 22:16:50.283762 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9222 22:16:50.286938 Root Device read_resources bus 0 link: 0 done
9223 22:16:50.287452 Done reading resources.
9224 22:16:50.293487 Show resources in subtree (Root Device)...After reading.
9225 22:16:50.296853 Root Device child on link 0 CPU_CLUSTER: 0
9226 22:16:50.300709 CPU_CLUSTER: 0 child on link 0 CPU: 00
9227 22:16:50.310040 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9228 22:16:50.310567 CPU: 00
9229 22:16:50.313108 Root Device assign_resources, bus 0 link: 0
9230 22:16:50.316899 CPU_CLUSTER: 0 missing set_resources
9231 22:16:50.323053 Root Device assign_resources, bus 0 link: 0 done
9232 22:16:50.323690 Done setting resources.
9233 22:16:50.329732 Show resources in subtree (Root Device)...After assigning values.
9234 22:16:50.333490 Root Device child on link 0 CPU_CLUSTER: 0
9235 22:16:50.337061 CPU_CLUSTER: 0 child on link 0 CPU: 00
9236 22:16:50.346821 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9237 22:16:50.347352 CPU: 00
9238 22:16:50.350395 Done allocating resources.
9239 22:16:50.353482 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9240 22:16:50.356390 Enabling resources...
9241 22:16:50.356809 done.
9242 22:16:50.363387 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9243 22:16:50.363925 Initializing devices...
9244 22:16:50.366482 Root Device init
9245 22:16:50.366900 init hardware done!
9246 22:16:50.370000 0x00000018: ctrlr->caps
9247 22:16:50.373089 52.000 MHz: ctrlr->f_max
9248 22:16:50.373629 0.400 MHz: ctrlr->f_min
9249 22:16:50.376302 0x40ff8080: ctrlr->voltages
9250 22:16:50.376732 sclk: 390625
9251 22:16:50.379535 Bus Width = 1
9252 22:16:50.379981 sclk: 390625
9253 22:16:50.383183 Bus Width = 1
9254 22:16:50.383747 Early init status = 3
9255 22:16:50.390138 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9256 22:16:50.393468 in-header: 03 fc 00 00 01 00 00 00
9257 22:16:50.393910 in-data: 00
9258 22:16:50.400043 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9259 22:16:50.403251 in-header: 03 fd 00 00 00 00 00 00
9260 22:16:50.406028 in-data:
9261 22:16:50.409020 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9262 22:16:50.413195 in-header: 03 fc 00 00 01 00 00 00
9263 22:16:50.416269 in-data: 00
9264 22:16:50.419621 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9265 22:16:50.424919 in-header: 03 fd 00 00 00 00 00 00
9266 22:16:50.427994 in-data:
9267 22:16:50.430852 [SSUSB] Setting up USB HOST controller...
9268 22:16:50.434051 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9269 22:16:50.437418 [SSUSB] phy power-on done.
9270 22:16:50.441406 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9271 22:16:50.447668 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9272 22:16:50.450746 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9273 22:16:50.457496 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9274 22:16:50.464104 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9275 22:16:50.470542 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9276 22:16:50.477429 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9277 22:16:50.483924 read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps
9278 22:16:50.487321 SPM: binary array size = 0x9dc
9279 22:16:50.490472 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9280 22:16:50.497524 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9281 22:16:50.503732 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9282 22:16:50.507453 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9283 22:16:50.513747 configure_display: Starting display init
9284 22:16:50.547880 anx7625_power_on_init: Init interface.
9285 22:16:50.550921 anx7625_disable_pd_protocol: Disabled PD feature.
9286 22:16:50.554522 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9287 22:16:50.582659 anx7625_start_dp_work: Secure OCM version=00
9288 22:16:50.585685 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9289 22:16:50.600305 sp_tx_get_edid_block: EDID Block = 1
9290 22:16:50.703387 Extracted contents:
9291 22:16:50.705960 header: 00 ff ff ff ff ff ff 00
9292 22:16:50.709872 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9293 22:16:50.712956 version: 01 04
9294 22:16:50.716126 basic params: 95 1f 11 78 0a
9295 22:16:50.719736 chroma info: 76 90 94 55 54 90 27 21 50 54
9296 22:16:50.722396 established: 00 00 00
9297 22:16:50.729523 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9298 22:16:50.732226 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9299 22:16:50.739183 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9300 22:16:50.745502 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9301 22:16:50.752546 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9302 22:16:50.756124 extensions: 00
9303 22:16:50.756631 checksum: fb
9304 22:16:50.756958
9305 22:16:50.759086 Manufacturer: IVO Model 57d Serial Number 0
9306 22:16:50.762206 Made week 0 of 2020
9307 22:16:50.762719 EDID version: 1.4
9308 22:16:50.765774 Digital display
9309 22:16:50.768792 6 bits per primary color channel
9310 22:16:50.769239 DisplayPort interface
9311 22:16:50.772080 Maximum image size: 31 cm x 17 cm
9312 22:16:50.776237 Gamma: 220%
9313 22:16:50.776645 Check DPMS levels
9314 22:16:50.779188 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9315 22:16:50.785369 First detailed timing is preferred timing
9316 22:16:50.785782 Established timings supported:
9317 22:16:50.788699 Standard timings supported:
9318 22:16:50.791903 Detailed timings
9319 22:16:50.795477 Hex of detail: 383680a07038204018303c0035ae10000019
9320 22:16:50.799152 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9321 22:16:50.805469 0780 0798 07c8 0820 hborder 0
9322 22:16:50.808844 0438 043b 0447 0458 vborder 0
9323 22:16:50.812024 -hsync -vsync
9324 22:16:50.812550 Did detailed timing
9325 22:16:50.818565 Hex of detail: 000000000000000000000000000000000000
9326 22:16:50.819101 Manufacturer-specified data, tag 0
9327 22:16:50.825269 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9328 22:16:50.828630 ASCII string: InfoVision
9329 22:16:50.831908 Hex of detail: 000000fe00523134304e574635205248200a
9330 22:16:50.835730 ASCII string: R140NWF5 RH
9331 22:16:50.836355 Checksum
9332 22:16:50.838995 Checksum: 0xfb (valid)
9333 22:16:50.841987 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9334 22:16:50.845576 DSI data_rate: 832800000 bps
9335 22:16:50.852046 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9336 22:16:50.855113 anx7625_parse_edid: pixelclock(138800).
9337 22:16:50.858848 hactive(1920), hsync(48), hfp(24), hbp(88)
9338 22:16:50.862231 vactive(1080), vsync(12), vfp(3), vbp(17)
9339 22:16:50.865519 anx7625_dsi_config: config dsi.
9340 22:16:50.871937 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9341 22:16:50.884725 anx7625_dsi_config: success to config DSI
9342 22:16:50.888231 anx7625_dp_start: MIPI phy setup OK.
9343 22:16:50.891463 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9344 22:16:50.894864 mtk_ddp_mode_set invalid vrefresh 60
9345 22:16:50.898235 main_disp_path_setup
9346 22:16:50.898774 ovl_layer_smi_id_en
9347 22:16:50.901002 ovl_layer_smi_id_en
9348 22:16:50.901502 ccorr_config
9349 22:16:50.901869 aal_config
9350 22:16:50.904695 gamma_config
9351 22:16:50.905158 postmask_config
9352 22:16:50.907851 dither_config
9353 22:16:50.911532 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9354 22:16:50.918631 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9355 22:16:50.921339 Root Device init finished in 551 msecs
9356 22:16:50.924428 CPU_CLUSTER: 0 init
9357 22:16:50.931281 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9358 22:16:50.934732 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9359 22:16:50.937808 APU_MBOX 0x190000b0 = 0x10001
9360 22:16:50.941250 APU_MBOX 0x190001b0 = 0x10001
9361 22:16:50.944615 APU_MBOX 0x190005b0 = 0x10001
9362 22:16:50.948751 APU_MBOX 0x190006b0 = 0x10001
9363 22:16:50.951576 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9364 22:16:50.963604 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9365 22:16:50.976041 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9366 22:16:50.982614 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9367 22:16:50.994556 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9368 22:16:51.003996 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9369 22:16:51.007152 CPU_CLUSTER: 0 init finished in 81 msecs
9370 22:16:51.010730 Devices initialized
9371 22:16:51.013421 Show all devs... After init.
9372 22:16:51.013887 Root Device: enabled 1
9373 22:16:51.017156 CPU_CLUSTER: 0: enabled 1
9374 22:16:51.020200 CPU: 00: enabled 1
9375 22:16:51.023761 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms
9376 22:16:51.026982 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9377 22:16:51.030143 ELOG: NV offset 0x57f000 size 0x1000
9378 22:16:51.037884 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9379 22:16:51.043076 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9380 22:16:51.046511 ELOG: Event(17) added with size 13 at 2023-06-04 22:17:03 UTC
9381 22:16:51.053039 out: cmd=0x121: 03 db 21 01 00 00 00 00
9382 22:16:51.056437 in-header: 03 e4 00 00 2c 00 00 00
9383 22:16:51.069464 in-data: 7b 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9384 22:16:51.074137 ELOG: Event(A1) added with size 10 at 2023-06-04 22:17:03 UTC
9385 22:16:51.079320 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9386 22:16:51.086534 ELOG: Event(A0) added with size 9 at 2023-06-04 22:17:03 UTC
9387 22:16:51.090137 elog_add_boot_reason: Logged dev mode boot
9388 22:16:51.096271 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9389 22:16:51.096830 Finalize devices...
9390 22:16:51.100030 Devices finalized
9391 22:16:51.102905 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9392 22:16:51.106428 Writing coreboot table at 0xffe64000
9393 22:16:51.109371 0. 000000000010a000-0000000000113fff: RAMSTAGE
9394 22:16:51.115737 1. 0000000040000000-00000000400fffff: RAM
9395 22:16:51.119833 2. 0000000040100000-000000004032afff: RAMSTAGE
9396 22:16:51.123265 3. 000000004032b000-00000000545fffff: RAM
9397 22:16:51.126167 4. 0000000054600000-000000005465ffff: BL31
9398 22:16:51.129913 5. 0000000054660000-00000000ffe63fff: RAM
9399 22:16:51.135861 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9400 22:16:51.139439 7. 0000000100000000-000000023fffffff: RAM
9401 22:16:51.142765 Passing 5 GPIOs to payload:
9402 22:16:51.146294 NAME | PORT | POLARITY | VALUE
9403 22:16:51.153165 EC in RW | 0x000000aa | low | undefined
9404 22:16:51.156029 EC interrupt | 0x00000005 | low | undefined
9405 22:16:51.158975 TPM interrupt | 0x000000ab | high | undefined
9406 22:16:51.165821 SD card detect | 0x00000011 | high | undefined
9407 22:16:51.169196 speaker enable | 0x00000093 | high | undefined
9408 22:16:51.172498 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9409 22:16:51.175635 in-header: 03 f9 00 00 02 00 00 00
9410 22:16:51.178991 in-data: 02 00
9411 22:16:51.182830 ADC[4]: Raw value=900590 ID=7
9412 22:16:51.185380 ADC[3]: Raw value=213336 ID=1
9413 22:16:51.185847 RAM Code: 0x71
9414 22:16:51.188734 ADC[6]: Raw value=74557 ID=0
9415 22:16:51.191998 ADC[5]: Raw value=212229 ID=1
9416 22:16:51.192461 SKU Code: 0x1
9417 22:16:51.198745 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum ded1
9418 22:16:51.199267 coreboot table: 964 bytes.
9419 22:16:51.201564 IMD ROOT 0. 0xfffff000 0x00001000
9420 22:16:51.204777 IMD SMALL 1. 0xffffe000 0x00001000
9421 22:16:51.208211 RO MCACHE 2. 0xffffc000 0x00001104
9422 22:16:51.211871 CONSOLE 3. 0xfff7c000 0x00080000
9423 22:16:51.215452 FMAP 4. 0xfff7b000 0x00000452
9424 22:16:51.218486 TIME STAMP 5. 0xfff7a000 0x00000910
9425 22:16:51.221939 VBOOT WORK 6. 0xfff66000 0x00014000
9426 22:16:51.224963 RAMOOPS 7. 0xffe66000 0x00100000
9427 22:16:51.228360 COREBOOT 8. 0xffe64000 0x00002000
9428 22:16:51.231330 IMD small region:
9429 22:16:51.235136 IMD ROOT 0. 0xffffec00 0x00000400
9430 22:16:51.237939 VPD 1. 0xffffeba0 0x0000004c
9431 22:16:51.241434 MMC STATUS 2. 0xffffeb80 0x00000004
9432 22:16:51.248040 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9433 22:16:51.248567 Probing TPM: done!
9434 22:16:51.251811 Connected to device vid:did:rid of 1ae0:0028:00
9435 22:16:51.263367 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9436 22:16:51.266077 Initialized TPM device CR50 revision 0
9437 22:16:51.269817 Checking cr50 for pending updates
9438 22:16:51.273450 Reading cr50 TPM mode
9439 22:16:51.282111 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9440 22:16:51.289314 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9441 22:16:51.328763 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9442 22:16:51.332347 Checking segment from ROM address 0x40100000
9443 22:16:51.336219 Checking segment from ROM address 0x4010001c
9444 22:16:51.342748 Loading segment from ROM address 0x40100000
9445 22:16:51.343330 code (compression=0)
9446 22:16:51.349750 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9447 22:16:51.359124 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9448 22:16:51.359700 it's not compressed!
9449 22:16:51.365940 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9450 22:16:51.369184 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9451 22:16:51.389948 Loading segment from ROM address 0x4010001c
9452 22:16:51.390519 Entry Point 0x80000000
9453 22:16:51.392640 Loaded segments
9454 22:16:51.396374 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9455 22:16:51.402589 Jumping to boot code at 0x80000000(0xffe64000)
9456 22:16:51.409339 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9457 22:16:51.415724 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9458 22:16:51.424072 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9459 22:16:51.427283 Checking segment from ROM address 0x40100000
9460 22:16:51.430813 Checking segment from ROM address 0x4010001c
9461 22:16:51.437188 Loading segment from ROM address 0x40100000
9462 22:16:51.437759 code (compression=1)
9463 22:16:51.443619 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9464 22:16:51.453851 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9465 22:16:51.454425 using LZMA
9466 22:16:51.462774 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9467 22:16:51.468943 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9468 22:16:51.472578 Loading segment from ROM address 0x4010001c
9469 22:16:51.473152 Entry Point 0x54601000
9470 22:16:51.475803 Loaded segments
9471 22:16:51.479057 NOTICE: MT8192 bl31_setup
9472 22:16:51.486031 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9473 22:16:51.489125 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9474 22:16:51.492661 WARNING: region 0:
9475 22:16:51.496113 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9476 22:16:51.496758 WARNING: region 1:
9477 22:16:51.502772 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9478 22:16:51.505944 WARNING: region 2:
9479 22:16:51.509426 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9480 22:16:51.513023 WARNING: region 3:
9481 22:16:51.515657 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9482 22:16:51.519066 WARNING: region 4:
9483 22:16:51.522705 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9484 22:16:51.525652 WARNING: region 5:
9485 22:16:51.529448 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9486 22:16:51.532517 WARNING: region 6:
9487 22:16:51.536043 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9488 22:16:51.536434 WARNING: region 7:
9489 22:16:51.542569 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9490 22:16:51.549325 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9491 22:16:51.552643 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9492 22:16:51.556107 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9493 22:16:51.562737 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9494 22:16:51.565943 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9495 22:16:51.569331 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9496 22:16:51.576396 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9497 22:16:51.579355 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9498 22:16:51.582461 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9499 22:16:51.590010 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9500 22:16:51.592629 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9501 22:16:51.599701 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9502 22:16:51.602789 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9503 22:16:51.606607 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9504 22:16:51.613034 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9505 22:16:51.616643 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9506 22:16:51.619407 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9507 22:16:51.626357 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9508 22:16:51.629455 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9509 22:16:51.635579 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9510 22:16:51.638998 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9511 22:16:51.642866 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9512 22:16:51.649795 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9513 22:16:51.652861 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9514 22:16:51.659305 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9515 22:16:51.662924 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9516 22:16:51.666103 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9517 22:16:51.672618 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9518 22:16:51.675861 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9519 22:16:51.679520 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9520 22:16:51.686273 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9521 22:16:51.689646 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9522 22:16:51.692558 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9523 22:16:51.699868 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9524 22:16:51.703322 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9525 22:16:51.706281 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9526 22:16:51.709496 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9527 22:16:51.716166 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9528 22:16:51.719692 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9529 22:16:51.724103 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9530 22:16:51.726111 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9531 22:16:51.732687 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9532 22:16:51.735916 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9533 22:16:51.739232 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9534 22:16:51.742789 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9535 22:16:51.749467 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9536 22:16:51.752712 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9537 22:16:51.756198 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9538 22:16:51.762917 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9539 22:16:51.766185 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9540 22:16:51.769484 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9541 22:16:51.775640 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9542 22:16:51.779713 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9543 22:16:51.786185 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9544 22:16:51.789436 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9545 22:16:51.796629 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9546 22:16:51.799633 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9547 22:16:51.802878 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9548 22:16:51.809887 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9549 22:16:51.813061 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9550 22:16:51.819656 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9551 22:16:51.822891 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9552 22:16:51.830002 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9553 22:16:51.832697 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9554 22:16:51.839153 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9555 22:16:51.843053 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9556 22:16:51.845805 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9557 22:16:51.853596 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9558 22:16:51.855908 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9559 22:16:51.862479 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9560 22:16:51.866373 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9561 22:16:51.872555 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9562 22:16:51.876214 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9563 22:16:51.879433 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9564 22:16:51.885975 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9565 22:16:51.889636 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9566 22:16:51.896116 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9567 22:16:51.899445 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9568 22:16:51.906202 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9569 22:16:51.909005 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9570 22:16:51.912473 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9571 22:16:51.919630 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9572 22:16:51.922724 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9573 22:16:51.929636 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9574 22:16:51.932791 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9575 22:16:51.939726 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9576 22:16:51.942723 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9577 22:16:51.946389 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9578 22:16:51.952377 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9579 22:16:51.956060 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9580 22:16:51.962554 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9581 22:16:51.966017 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9582 22:16:51.972523 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9583 22:16:51.976171 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9584 22:16:51.982789 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9585 22:16:51.985570 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9586 22:16:51.989348 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9587 22:16:51.992314 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9588 22:16:51.999581 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9589 22:16:52.002215 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9590 22:16:52.006177 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9591 22:16:52.012474 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9592 22:16:52.015902 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9593 22:16:52.019097 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9594 22:16:52.025524 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9595 22:16:52.029658 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9596 22:16:52.036159 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9597 22:16:52.039242 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9598 22:16:52.042937 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9599 22:16:52.049568 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9600 22:16:52.052647 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9601 22:16:52.058845 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9602 22:16:52.062685 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9603 22:16:52.065975 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9604 22:16:52.073195 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9605 22:16:52.075829 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9606 22:16:52.079502 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9607 22:16:52.085765 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9608 22:16:52.089249 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9609 22:16:52.092307 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9610 22:16:52.096107 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9611 22:16:52.103103 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9612 22:16:52.106031 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9613 22:16:52.109157 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9614 22:16:52.116037 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9615 22:16:52.119174 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9616 22:16:52.123151 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9617 22:16:52.129549 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9618 22:16:52.132882 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9619 22:16:52.139076 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9620 22:16:52.143031 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9621 22:16:52.145611 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9622 22:16:52.152636 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9623 22:16:52.156226 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9624 22:16:52.159198 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9625 22:16:52.165810 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9626 22:16:52.169503 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9627 22:16:52.175910 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9628 22:16:52.179207 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9629 22:16:52.183200 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9630 22:16:52.189697 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9631 22:16:52.192250 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9632 22:16:52.199089 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9633 22:16:52.202855 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9634 22:16:52.205843 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9635 22:16:52.212807 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9636 22:16:52.216108 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9637 22:16:52.219587 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9638 22:16:52.225915 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9639 22:16:52.228811 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9640 22:16:52.236340 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9641 22:16:52.239256 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9642 22:16:52.242448 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9643 22:16:52.249815 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9644 22:16:52.252529 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9645 22:16:52.259230 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9646 22:16:52.262521 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9647 22:16:52.265432 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9648 22:16:52.272536 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9649 22:16:52.275935 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9650 22:16:52.282934 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9651 22:16:52.285541 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9652 22:16:52.288919 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9653 22:16:52.295666 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9654 22:16:52.299029 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9655 22:16:52.305207 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9656 22:16:52.308768 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9657 22:16:52.312178 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9658 22:16:52.318705 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9659 22:16:52.322226 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9660 22:16:52.329088 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9661 22:16:52.332077 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9662 22:16:52.335688 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9663 22:16:52.342210 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9664 22:16:52.345635 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9665 22:16:52.348588 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9666 22:16:52.355558 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9667 22:16:52.358881 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9668 22:16:52.364882 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9669 22:16:52.368640 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9670 22:16:52.371730 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9671 22:16:52.378573 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9672 22:16:52.381689 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9673 22:16:52.388823 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9674 22:16:52.391637 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9675 22:16:52.394767 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9676 22:16:52.401582 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9677 22:16:52.404897 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9678 22:16:52.411749 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9679 22:16:52.415201 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9680 22:16:52.418637 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9681 22:16:52.425233 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9682 22:16:52.428859 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9683 22:16:52.434766 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9684 22:16:52.437641 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9685 22:16:52.445283 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9686 22:16:52.448349 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9687 22:16:52.451815 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9688 22:16:52.457982 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9689 22:16:52.461569 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9690 22:16:52.467804 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9691 22:16:52.471091 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9692 22:16:52.474588 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9693 22:16:52.481321 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9694 22:16:52.484362 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9695 22:16:52.491330 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9696 22:16:52.495139 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9697 22:16:52.500609 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9698 22:16:52.504024 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9699 22:16:52.508030 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9700 22:16:52.514122 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9701 22:16:52.518031 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9702 22:16:52.523981 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9703 22:16:52.527694 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9704 22:16:52.530924 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9705 22:16:52.537332 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9706 22:16:52.540739 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9707 22:16:52.547607 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9708 22:16:52.550638 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9709 22:16:52.557159 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9710 22:16:52.560508 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9711 22:16:52.564606 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9712 22:16:52.570718 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9713 22:16:52.573835 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9714 22:16:52.580796 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9715 22:16:52.584112 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9716 22:16:52.590294 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9717 22:16:52.594069 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9718 22:16:52.597640 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9719 22:16:52.603821 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9720 22:16:52.607477 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9721 22:16:52.610405 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9722 22:16:52.614215 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9723 22:16:52.617224 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9724 22:16:52.623928 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9725 22:16:52.627604 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9726 22:16:52.633682 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9727 22:16:52.637172 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9728 22:16:52.640351 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9729 22:16:52.647337 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9730 22:16:52.650834 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9731 22:16:52.653995 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9732 22:16:52.660445 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9733 22:16:52.664257 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9734 22:16:52.667383 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9735 22:16:52.673577 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9736 22:16:52.677054 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9737 22:16:52.683930 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9738 22:16:52.686684 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9739 22:16:52.690413 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9740 22:16:52.697317 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9741 22:16:52.700826 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9742 22:16:52.703351 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9743 22:16:52.709975 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9744 22:16:52.713945 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9745 22:16:52.716862 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9746 22:16:52.723381 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9747 22:16:52.726860 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9748 22:16:52.733555 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9749 22:16:52.736899 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9750 22:16:52.740411 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9751 22:16:52.746420 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9752 22:16:52.750725 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9753 22:16:52.753929 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9754 22:16:52.759927 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9755 22:16:52.763230 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9756 22:16:52.770129 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9757 22:16:52.773999 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9758 22:16:52.777151 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9759 22:16:52.780808 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9760 22:16:52.786928 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9761 22:16:52.789898 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9762 22:16:52.793404 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9763 22:16:52.796631 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9764 22:16:52.803274 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9765 22:16:52.806854 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9766 22:16:52.810039 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9767 22:16:52.813223 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9768 22:16:52.819618 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9769 22:16:52.823365 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9770 22:16:52.826354 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9771 22:16:52.829529 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9772 22:16:52.836255 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9773 22:16:52.839283 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9774 22:16:52.846954 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9775 22:16:52.850033 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9776 22:16:52.856567 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9777 22:16:52.859528 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9778 22:16:52.863145 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9779 22:16:52.870090 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9780 22:16:52.873251 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9781 22:16:52.879304 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9782 22:16:52.882809 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9783 22:16:52.886152 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9784 22:16:52.892514 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9785 22:16:52.895820 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9786 22:16:52.903054 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9787 22:16:52.906204 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9788 22:16:52.909046 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9789 22:16:52.916248 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9790 22:16:52.919037 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9791 22:16:52.925707 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9792 22:16:52.929191 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9793 22:16:52.932481 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9794 22:16:52.938828 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9795 22:16:52.942251 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9796 22:16:52.950638 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9797 22:16:52.952778 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9798 22:16:52.956205 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9799 22:16:52.962999 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9800 22:16:52.966383 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9801 22:16:52.972178 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9802 22:16:52.975756 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9803 22:16:52.978836 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9804 22:16:52.985769 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9805 22:16:52.988864 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9806 22:16:52.995594 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9807 22:16:52.999379 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9808 22:16:53.005450 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9809 22:16:53.008794 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9810 22:16:53.012470 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9811 22:16:53.018440 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9812 22:16:53.021884 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9813 22:16:53.028580 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9814 22:16:53.031600 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9815 22:16:53.035151 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9816 22:16:53.042343 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9817 22:16:53.045731 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9818 22:16:53.051717 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9819 22:16:53.055329 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9820 22:16:53.058722 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9821 22:16:53.065701 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9822 22:16:53.068653 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9823 22:16:53.075235 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9824 22:16:53.078701 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9825 22:16:53.085547 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9826 22:16:53.089050 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9827 22:16:53.091874 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9828 22:16:53.098564 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9829 22:16:53.102589 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9830 22:16:53.108244 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9831 22:16:53.111539 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9832 22:16:53.115334 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9833 22:16:53.121854 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9834 22:16:53.125340 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9835 22:16:53.128535 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9836 22:16:53.135319 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9837 22:16:53.138297 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9838 22:16:53.145372 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9839 22:16:53.148500 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9840 22:16:53.155004 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9841 22:16:53.158394 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9842 22:16:53.161693 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9843 22:16:53.168325 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9844 22:16:53.171305 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9845 22:16:53.178560 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9846 22:16:53.181720 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9847 22:16:53.188637 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9848 22:16:53.191291 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9849 22:16:53.194987 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9850 22:16:53.201401 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9851 22:16:53.204816 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9852 22:16:53.211585 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9853 22:16:53.215177 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9854 22:16:53.221386 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9855 22:16:53.224794 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9856 22:16:53.227774 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9857 22:16:53.235009 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9858 22:16:53.238333 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9859 22:16:53.244328 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9860 22:16:53.248576 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9861 22:16:53.254865 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9862 22:16:53.257985 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9863 22:16:53.264553 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9864 22:16:53.267799 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9865 22:16:53.271383 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9866 22:16:53.278213 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9867 22:16:53.281167 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9868 22:16:53.287768 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9869 22:16:53.291262 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9870 22:16:53.298089 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9871 22:16:53.300776 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9872 22:16:53.304667 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9873 22:16:53.311432 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9874 22:16:53.314237 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9875 22:16:53.321020 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9876 22:16:53.324401 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9877 22:16:53.330954 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9878 22:16:53.334877 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9879 22:16:53.337575 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9880 22:16:53.344300 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9881 22:16:53.348102 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9882 22:16:53.355572 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9883 22:16:53.357277 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9884 22:16:53.364516 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9885 22:16:53.367775 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9886 22:16:53.370935 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9887 22:16:53.377200 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9888 22:16:53.380660 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9889 22:16:53.388492 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9890 22:16:53.391013 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9891 22:16:53.397479 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9892 22:16:53.400921 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9893 22:16:53.404471 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9894 22:16:53.410860 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9895 22:16:53.414229 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9896 22:16:53.420728 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9897 22:16:53.424111 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9898 22:16:53.430691 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9899 22:16:53.434630 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9900 22:16:53.440425 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9901 22:16:53.444298 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9902 22:16:53.450690 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9903 22:16:53.453794 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9904 22:16:53.460126 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9905 22:16:53.464096 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9906 22:16:53.470658 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9907 22:16:53.473533 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9908 22:16:53.480703 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9909 22:16:53.484032 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9910 22:16:53.487536 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9911 22:16:53.493347 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9912 22:16:53.496989 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9913 22:16:53.504072 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9914 22:16:53.506687 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9915 22:16:53.513136 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9916 22:16:53.517077 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9917 22:16:53.523844 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9918 22:16:53.527091 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9919 22:16:53.533843 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9920 22:16:53.537075 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9921 22:16:53.543769 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9922 22:16:53.546978 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9923 22:16:53.553660 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9924 22:16:53.557122 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9925 22:16:53.560519 INFO: [APUAPC] vio 0
9926 22:16:53.563325 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9927 22:16:53.570592 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9928 22:16:53.573701 INFO: [APUAPC] D0_APC_0: 0x400510
9929 22:16:53.576464 INFO: [APUAPC] D0_APC_1: 0x0
9930 22:16:53.580501 INFO: [APUAPC] D0_APC_2: 0x1540
9931 22:16:53.581104 INFO: [APUAPC] D0_APC_3: 0x0
9932 22:16:53.584091 INFO: [APUAPC] D1_APC_0: 0xffffffff
9933 22:16:53.586726 INFO: [APUAPC] D1_APC_1: 0xffffffff
9934 22:16:53.590472 INFO: [APUAPC] D1_APC_2: 0x3fffff
9935 22:16:53.593422 INFO: [APUAPC] D1_APC_3: 0x0
9936 22:16:53.596928 INFO: [APUAPC] D2_APC_0: 0xffffffff
9937 22:16:53.600477 INFO: [APUAPC] D2_APC_1: 0xffffffff
9938 22:16:53.603311 INFO: [APUAPC] D2_APC_2: 0x3fffff
9939 22:16:53.606722 INFO: [APUAPC] D2_APC_3: 0x0
9940 22:16:53.610008 INFO: [APUAPC] D3_APC_0: 0xffffffff
9941 22:16:53.613239 INFO: [APUAPC] D3_APC_1: 0xffffffff
9942 22:16:53.616734 INFO: [APUAPC] D3_APC_2: 0x3fffff
9943 22:16:53.619833 INFO: [APUAPC] D3_APC_3: 0x0
9944 22:16:53.623368 INFO: [APUAPC] D4_APC_0: 0xffffffff
9945 22:16:53.626781 INFO: [APUAPC] D4_APC_1: 0xffffffff
9946 22:16:53.629892 INFO: [APUAPC] D4_APC_2: 0x3fffff
9947 22:16:53.633202 INFO: [APUAPC] D4_APC_3: 0x0
9948 22:16:53.636652 INFO: [APUAPC] D5_APC_0: 0xffffffff
9949 22:16:53.639840 INFO: [APUAPC] D5_APC_1: 0xffffffff
9950 22:16:53.643064 INFO: [APUAPC] D5_APC_2: 0x3fffff
9951 22:16:53.646885 INFO: [APUAPC] D5_APC_3: 0x0
9952 22:16:53.649843 INFO: [APUAPC] D6_APC_0: 0xffffffff
9953 22:16:53.652893 INFO: [APUAPC] D6_APC_1: 0xffffffff
9954 22:16:53.656512 INFO: [APUAPC] D6_APC_2: 0x3fffff
9955 22:16:53.659703 INFO: [APUAPC] D6_APC_3: 0x0
9956 22:16:53.662810 INFO: [APUAPC] D7_APC_0: 0xffffffff
9957 22:16:53.666796 INFO: [APUAPC] D7_APC_1: 0xffffffff
9958 22:16:53.669587 INFO: [APUAPC] D7_APC_2: 0x3fffff
9959 22:16:53.672897 INFO: [APUAPC] D7_APC_3: 0x0
9960 22:16:53.676125 INFO: [APUAPC] D8_APC_0: 0xffffffff
9961 22:16:53.679407 INFO: [APUAPC] D8_APC_1: 0xffffffff
9962 22:16:53.683047 INFO: [APUAPC] D8_APC_2: 0x3fffff
9963 22:16:53.686122 INFO: [APUAPC] D8_APC_3: 0x0
9964 22:16:53.689370 INFO: [APUAPC] D9_APC_0: 0xffffffff
9965 22:16:53.692899 INFO: [APUAPC] D9_APC_1: 0xffffffff
9966 22:16:53.695989 INFO: [APUAPC] D9_APC_2: 0x3fffff
9967 22:16:53.700036 INFO: [APUAPC] D9_APC_3: 0x0
9968 22:16:53.703104 INFO: [APUAPC] D10_APC_0: 0xffffffff
9969 22:16:53.705987 INFO: [APUAPC] D10_APC_1: 0xffffffff
9970 22:16:53.709249 INFO: [APUAPC] D10_APC_2: 0x3fffff
9971 22:16:53.712597 INFO: [APUAPC] D10_APC_3: 0x0
9972 22:16:53.716125 INFO: [APUAPC] D11_APC_0: 0xffffffff
9973 22:16:53.719795 INFO: [APUAPC] D11_APC_1: 0xffffffff
9974 22:16:53.723803 INFO: [APUAPC] D11_APC_2: 0x3fffff
9975 22:16:53.726160 INFO: [APUAPC] D11_APC_3: 0x0
9976 22:16:53.729565 INFO: [APUAPC] D12_APC_0: 0xffffffff
9977 22:16:53.733167 INFO: [APUAPC] D12_APC_1: 0xffffffff
9978 22:16:53.736487 INFO: [APUAPC] D12_APC_2: 0x3fffff
9979 22:16:53.739420 INFO: [APUAPC] D12_APC_3: 0x0
9980 22:16:53.742602 INFO: [APUAPC] D13_APC_0: 0xffffffff
9981 22:16:53.746149 INFO: [APUAPC] D13_APC_1: 0xffffffff
9982 22:16:53.749146 INFO: [APUAPC] D13_APC_2: 0x3fffff
9983 22:16:53.752889 INFO: [APUAPC] D13_APC_3: 0x0
9984 22:16:53.756341 INFO: [APUAPC] D14_APC_0: 0xffffffff
9985 22:16:53.759515 INFO: [APUAPC] D14_APC_1: 0xffffffff
9986 22:16:53.762455 INFO: [APUAPC] D14_APC_2: 0x3fffff
9987 22:16:53.765892 INFO: [APUAPC] D14_APC_3: 0x0
9988 22:16:53.769621 INFO: [APUAPC] D15_APC_0: 0xffffffff
9989 22:16:53.773126 INFO: [APUAPC] D15_APC_1: 0xffffffff
9990 22:16:53.776049 INFO: [APUAPC] D15_APC_2: 0x3fffff
9991 22:16:53.779202 INFO: [APUAPC] D15_APC_3: 0x0
9992 22:16:53.782886 INFO: [APUAPC] APC_CON: 0x4
9993 22:16:53.785815 INFO: [NOCDAPC] D0_APC_0: 0x0
9994 22:16:53.786288 INFO: [NOCDAPC] D0_APC_1: 0x0
9995 22:16:53.788759 INFO: [NOCDAPC] D1_APC_0: 0x0
9996 22:16:53.792815 INFO: [NOCDAPC] D1_APC_1: 0xfff
9997 22:16:53.795607 INFO: [NOCDAPC] D2_APC_0: 0x0
9998 22:16:53.799129 INFO: [NOCDAPC] D2_APC_1: 0xfff
9999 22:16:53.802279 INFO: [NOCDAPC] D3_APC_0: 0x0
10000 22:16:53.806035 INFO: [NOCDAPC] D3_APC_1: 0xfff
10001 22:16:53.808718 INFO: [NOCDAPC] D4_APC_0: 0x0
10002 22:16:53.812671 INFO: [NOCDAPC] D4_APC_1: 0xfff
10003 22:16:53.815943 INFO: [NOCDAPC] D5_APC_0: 0x0
10004 22:16:53.818707 INFO: [NOCDAPC] D5_APC_1: 0xfff
10005 22:16:53.819177 INFO: [NOCDAPC] D6_APC_0: 0x0
10006 22:16:53.822930 INFO: [NOCDAPC] D6_APC_1: 0xfff
10007 22:16:53.825934 INFO: [NOCDAPC] D7_APC_0: 0x0
10008 22:16:53.829327 INFO: [NOCDAPC] D7_APC_1: 0xfff
10009 22:16:53.832411 INFO: [NOCDAPC] D8_APC_0: 0x0
10010 22:16:53.835753 INFO: [NOCDAPC] D8_APC_1: 0xfff
10011 22:16:53.839027 INFO: [NOCDAPC] D9_APC_0: 0x0
10012 22:16:53.842691 INFO: [NOCDAPC] D9_APC_1: 0xfff
10013 22:16:53.846150 INFO: [NOCDAPC] D10_APC_0: 0x0
10014 22:16:53.848979 INFO: [NOCDAPC] D10_APC_1: 0xfff
10015 22:16:53.852340 INFO: [NOCDAPC] D11_APC_0: 0x0
10016 22:16:53.852903 INFO: [NOCDAPC] D11_APC_1: 0xfff
10017 22:16:53.855798 INFO: [NOCDAPC] D12_APC_0: 0x0
10018 22:16:53.859051 INFO: [NOCDAPC] D12_APC_1: 0xfff
10019 22:16:53.862295 INFO: [NOCDAPC] D13_APC_0: 0x0
10020 22:16:53.865675 INFO: [NOCDAPC] D13_APC_1: 0xfff
10021 22:16:53.868931 INFO: [NOCDAPC] D14_APC_0: 0x0
10022 22:16:53.872671 INFO: [NOCDAPC] D14_APC_1: 0xfff
10023 22:16:53.875624 INFO: [NOCDAPC] D15_APC_0: 0x0
10024 22:16:53.878926 INFO: [NOCDAPC] D15_APC_1: 0xfff
10025 22:16:53.881998 INFO: [NOCDAPC] APC_CON: 0x4
10026 22:16:53.885302 INFO: [APUAPC] set_apusys_apc done
10027 22:16:53.889043 INFO: [DEVAPC] devapc_init done
10028 22:16:53.892266 INFO: GICv3 without legacy support detected.
10029 22:16:53.895096 INFO: ARM GICv3 driver initialized in EL3
10030 22:16:53.898870 INFO: Maximum SPI INTID supported: 639
10031 22:16:53.905954 INFO: BL31: Initializing runtime services
10032 22:16:53.908697 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10033 22:16:53.912069 INFO: SPM: enable CPC mode
10034 22:16:53.918946 INFO: mcdi ready for mcusys-off-idle and system suspend
10035 22:16:53.922636 INFO: BL31: Preparing for EL3 exit to normal world
10036 22:16:53.924911 INFO: Entry point address = 0x80000000
10037 22:16:53.928716 INFO: SPSR = 0x8
10038 22:16:53.933777
10039 22:16:53.934332
10040 22:16:53.934705
10041 22:16:53.936829 Starting depthcharge on Spherion...
10042 22:16:53.937298
10043 22:16:53.937676 Wipe memory regions:
10044 22:16:53.938024
10045 22:16:53.940432 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10046 22:16:53.940973 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10047 22:16:53.941429 Setting prompt string to ['asurada:']
10048 22:16:53.941880 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10049 22:16:53.942637 [0x00000040000000, 0x00000054600000)
10050 22:16:54.062362
10051 22:16:54.062945 [0x00000054660000, 0x00000080000000)
10052 22:16:54.323485
10053 22:16:54.324093 [0x000000821a7280, 0x000000ffe64000)
10054 22:16:55.068499
10055 22:16:55.069065 [0x00000100000000, 0x00000240000000)
10056 22:16:56.958440
10057 22:16:56.961605 Initializing XHCI USB controller at 0x11200000.
10058 22:16:58.000076
10059 22:16:58.002864 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10060 22:16:58.003431
10061 22:16:58.003806
10062 22:16:58.004203
10063 22:16:58.005023 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10065 22:16:58.106470 asurada: tftpboot 192.168.201.1 10583915/tftp-deploy-z4tjqdiw/kernel/image.itb 10583915/tftp-deploy-z4tjqdiw/kernel/cmdline
10066 22:16:58.107138 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10067 22:16:58.107619 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10068 22:16:58.112057 tftpboot 192.168.201.1 10583915/tftp-deploy-z4tjqdiw/kernel/image.itp-deploy-z4tjqdiw/kernel/cmdline
10069 22:16:58.112147
10070 22:16:58.112217 Waiting for link
10071 22:16:58.272928
10072 22:16:58.273490 R8152: Initializing
10073 22:16:58.273883
10074 22:16:58.276772 Version 6 (ocp_data = 5c30)
10075 22:16:58.277337
10076 22:16:58.279704 R8152: Done initializing
10077 22:16:58.280206
10078 22:16:58.280580 Adding net device
10079 22:17:00.303784
10080 22:17:00.304347 done.
10081 22:17:00.304704
10082 22:17:00.305024 MAC: 00:24:32:30:78:52
10083 22:17:00.305331
10084 22:17:00.307137 Sending DHCP discover... done.
10085 22:17:00.307565
10086 22:17:00.310728 Waiting for reply... done.
10087 22:17:00.311154
10088 22:17:00.313707 Sending DHCP request... done.
10089 22:17:00.314171
10090 22:17:00.314512 Waiting for reply... done.
10091 22:17:00.314835
10092 22:17:00.317089 My ip is 192.168.201.14
10093 22:17:00.317514
10094 22:17:00.320378 The DHCP server ip is 192.168.201.1
10095 22:17:00.320804
10096 22:17:00.323922 TFTP server IP predefined by user: 192.168.201.1
10097 22:17:00.324390
10098 22:17:00.330255 Bootfile predefined by user: 10583915/tftp-deploy-z4tjqdiw/kernel/image.itb
10099 22:17:00.330843
10100 22:17:00.333730 Sending tftp read request... done.
10101 22:17:00.334344
10102 22:17:00.341995 Waiting for the transfer...
10103 22:17:00.342568
10104 22:17:00.996271 00000000 ################################################################
10105 22:17:00.996413
10106 22:17:01.665800 00080000 ################################################################
10107 22:17:01.666319
10108 22:17:02.395925 00100000 ################################################################
10109 22:17:02.396685
10110 22:17:03.010200 00180000 ################################################################
10111 22:17:03.010353
10112 22:17:03.694641 00200000 ################################################################
10113 22:17:03.695169
10114 22:17:04.421075 00280000 ################################################################
10115 22:17:04.421673
10116 22:17:05.147291 00300000 ################################################################
10117 22:17:05.147881
10118 22:17:05.871234 00380000 ################################################################
10119 22:17:05.871784
10120 22:17:06.587629 00400000 ################################################################
10121 22:17:06.588334
10122 22:17:07.312696 00480000 ################################################################
10123 22:17:07.313089
10124 22:17:08.033602 00500000 ################################################################
10125 22:17:08.034185
10126 22:17:08.732370 00580000 ################################################################
10127 22:17:08.732880
10128 22:17:09.432733 00600000 ################################################################
10129 22:17:09.433308
10130 22:17:10.159316 00680000 ################################################################
10131 22:17:10.159864
10132 22:17:10.868422 00700000 ################################################################
10133 22:17:10.868995
10134 22:17:11.578761 00780000 ################################################################
10135 22:17:11.579289
10136 22:17:12.287985 00800000 ################################################################
10137 22:17:12.288515
10138 22:17:12.996239 00880000 ################################################################
10139 22:17:12.996796
10140 22:17:13.697935 00900000 ################################################################
10141 22:17:13.698467
10142 22:17:14.431752 00980000 ################################################################
10143 22:17:14.432395
10144 22:17:15.169382 00a00000 ################################################################
10145 22:17:15.169910
10146 22:17:15.890265 00a80000 ################################################################
10147 22:17:15.890794
10148 22:17:16.608145 00b00000 ################################################################
10149 22:17:16.608692
10150 22:17:17.330930 00b80000 ################################################################
10151 22:17:17.331544
10152 22:17:18.049998 00c00000 ################################################################
10153 22:17:18.050531
10154 22:17:18.784830 00c80000 ################################################################
10155 22:17:18.785604
10156 22:17:19.507115 00d00000 ################################################################
10157 22:17:19.507726
10158 22:17:20.215049 00d80000 ################################################################
10159 22:17:20.215616
10160 22:17:20.924437 00e00000 ################################################################
10161 22:17:20.924958
10162 22:17:21.625636 00e80000 ################################################################
10163 22:17:21.626262
10164 22:17:22.319931 00f00000 ################################################################
10165 22:17:22.320551
10166 22:17:23.043631 00f80000 ################################################################
10167 22:17:23.044293
10168 22:17:23.752407 01000000 ################################################################
10169 22:17:23.752963
10170 22:17:24.470506 01080000 ################################################################
10171 22:17:24.471026
10172 22:17:25.183074 01100000 ################################################################
10173 22:17:25.183623
10174 22:17:25.897624 01180000 ################################################################
10175 22:17:25.898156
10176 22:17:26.607632 01200000 ################################################################
10177 22:17:26.608192
10178 22:17:27.322695 01280000 ################################################################
10179 22:17:27.323467
10180 22:17:28.063879 01300000 ################################################################
10181 22:17:28.064485
10182 22:17:28.781994 01380000 ################################################################
10183 22:17:28.782551
10184 22:17:29.498806 01400000 ################################################################
10185 22:17:29.499319
10186 22:17:30.235880 01480000 ################################################################
10187 22:17:30.236506
10188 22:17:30.950912 01500000 ################################################################
10189 22:17:30.951465
10190 22:17:31.662767 01580000 ################################################################
10191 22:17:31.663295
10192 22:17:32.385241 01600000 ################################################################
10193 22:17:32.385783
10194 22:17:33.116375 01680000 ################################################################
10195 22:17:33.116971
10196 22:17:33.852815 01700000 ################################################################
10197 22:17:33.853356
10198 22:17:34.564228 01780000 ################################################################
10199 22:17:34.564754
10200 22:17:35.263781 01800000 ################################################################
10201 22:17:35.264328
10202 22:17:35.982501 01880000 ################################################################
10203 22:17:35.983051
10204 22:17:36.693476 01900000 ################################################################
10205 22:17:36.693986
10206 22:17:37.416526 01980000 ################################################################
10207 22:17:37.417135
10208 22:17:38.141820 01a00000 ################################################################
10209 22:17:38.142406
10210 22:17:38.866876 01a80000 ################################################################
10211 22:17:38.867444
10212 22:17:39.592525 01b00000 ################################################################
10213 22:17:39.593083
10214 22:17:40.304613 01b80000 ################################################################
10215 22:17:40.305209
10216 22:17:41.035999 01c00000 ################################################################
10217 22:17:41.036588
10218 22:17:41.763497 01c80000 ################################################################
10219 22:17:41.764089
10220 22:17:42.493803 01d00000 ################################################################
10221 22:17:42.494340
10222 22:17:43.224724 01d80000 ################################################################
10223 22:17:43.225304
10224 22:17:43.951463 01e00000 ################################################################
10225 22:17:43.952146
10226 22:17:44.688772 01e80000 ################################################################
10227 22:17:44.689330
10228 22:17:45.405323 01f00000 ################################################################
10229 22:17:45.405838
10230 22:17:46.124409 01f80000 ################################################################
10231 22:17:46.124932
10232 22:17:46.830213 02000000 ################################################################
10233 22:17:46.830753
10234 22:17:47.550284 02080000 ################################################################
10235 22:17:47.550831
10236 22:17:48.276271 02100000 ################################################################
10237 22:17:48.276419
10238 22:17:48.963515 02180000 ################################################################
10239 22:17:48.964142
10240 22:17:49.679440 02200000 ################################################################
10241 22:17:49.679574
10242 22:17:50.256351 02280000 ################################################################
10243 22:17:50.256491
10244 22:17:50.830621 02300000 ################################################################
10245 22:17:50.830776
10246 22:17:51.406513 02380000 ################################################################
10247 22:17:51.406668
10248 22:17:51.979770 02400000 ################################################################
10249 22:17:51.979916
10250 22:17:52.566639 02480000 ################################################################
10251 22:17:52.566792
10252 22:17:53.181275 02500000 ################################################################
10253 22:17:53.181905
10254 22:17:53.816162 02580000 ################################################################
10255 22:17:53.816310
10256 22:17:54.407921 02600000 ################################################################
10257 22:17:54.408105
10258 22:17:55.013258 02680000 ################################################################
10259 22:17:55.013409
10260 22:17:55.615858 02700000 ################################################################
10261 22:17:55.616041
10262 22:17:56.221627 02780000 ################################################################
10263 22:17:56.221777
10264 22:17:56.825349 02800000 ################################################################
10265 22:17:56.825502
10266 22:17:57.430632 02880000 ################################################################
10267 22:17:57.430788
10268 22:17:58.030633 02900000 ################################################################
10269 22:17:58.030785
10270 22:17:58.631853 02980000 ################################################################
10271 22:17:58.632011
10272 22:17:59.235277 02a00000 ################################################################
10273 22:17:59.235425
10274 22:17:59.811728 02a80000 ################################################################
10275 22:17:59.811885
10276 22:18:00.388582 02b00000 ################################################################
10277 22:18:00.388741
10278 22:18:00.963828 02b80000 ################################################################
10279 22:18:00.964016
10280 22:18:01.526663 02c00000 ################################################################
10281 22:18:01.526824
10282 22:18:02.101506 02c80000 ################################################################
10283 22:18:02.101666
10284 22:18:02.675565 02d00000 ################################################################
10285 22:18:02.675727
10286 22:18:03.251372 02d80000 ################################################################
10287 22:18:03.251524
10288 22:18:03.827795 02e00000 ################################################################
10289 22:18:03.827961
10290 22:18:04.391177 02e80000 ################################################################
10291 22:18:04.391332
10292 22:18:04.927578 02f00000 ################################################################
10293 22:18:04.927788
10294 22:18:05.457976 02f80000 ################################################################
10295 22:18:05.458134
10296 22:18:06.018522 03000000 ################################################################
10297 22:18:06.018671
10298 22:18:06.584358 03080000 ################################################################
10299 22:18:06.584508
10300 22:18:07.141225 03100000 ################################################################
10301 22:18:07.141381
10302 22:18:07.672106 03180000 ################################################################
10303 22:18:07.672262
10304 22:18:08.199361 03200000 ################################################################
10305 22:18:08.199510
10306 22:18:08.724135 03280000 ################################################################
10307 22:18:08.724285
10308 22:18:09.266399 03300000 ################################################################
10309 22:18:09.266553
10310 22:18:09.791970 03380000 ################################################################
10311 22:18:09.792132
10312 22:18:10.336454 03400000 ################################################################
10313 22:18:10.336607
10314 22:18:10.861438 03480000 ################################################################
10315 22:18:10.861593
10316 22:18:11.461490 03500000 ################################################################
10317 22:18:11.461646
10318 22:18:12.103708 03580000 ################################################################
10319 22:18:12.104276
10320 22:18:12.809742 03600000 ################################################################
10321 22:18:12.810271
10322 22:18:13.526933 03680000 ################################################################
10323 22:18:13.527717
10324 22:18:14.229967 03700000 ################################################################
10325 22:18:14.230488
10326 22:18:14.940320 03780000 ################################################################
10327 22:18:14.940880
10328 22:18:15.646770 03800000 ################################################################
10329 22:18:15.647338
10330 22:18:16.368125 03880000 ################################################################
10331 22:18:16.368692
10332 22:18:17.089868 03900000 ################################################################
10333 22:18:17.090413
10334 22:18:17.788894 03980000 ################################################################
10335 22:18:17.789397
10336 22:18:18.486654 03a00000 ################################################################
10337 22:18:18.487163
10338 22:18:19.203646 03a80000 ################################################################
10339 22:18:19.204181
10340 22:18:19.908303 03b00000 ################################################################
10341 22:18:19.908876
10342 22:18:20.626304 03b80000 ################################################################
10343 22:18:20.626838
10344 22:18:21.313130 03c00000 ################################################################
10345 22:18:21.313647
10346 22:18:21.895878 03c80000 ################################################################
10347 22:18:21.896070
10348 22:18:22.443206 03d00000 ################################################################
10349 22:18:22.443358
10350 22:18:22.971664 03d80000 ################################################################
10351 22:18:22.971835
10352 22:18:23.530398 03e00000 ################################################################
10353 22:18:23.530542
10354 22:18:24.088228 03e80000 ################################################################
10355 22:18:24.088378
10356 22:18:24.653119 03f00000 ################################################################
10357 22:18:24.653277
10358 22:18:25.218871 03f80000 ################################################################
10359 22:18:25.219019
10360 22:18:25.777699 04000000 ################################################################
10361 22:18:25.777848
10362 22:18:26.349845 04080000 ################################################################
10363 22:18:26.350015
10364 22:18:26.918919 04100000 ################################################################
10365 22:18:26.919083
10366 22:18:27.502344 04180000 ################################################################
10367 22:18:27.502502
10368 22:18:28.077961 04200000 ################################################################
10369 22:18:28.078101
10370 22:18:28.648173 04280000 ################################################################
10371 22:18:28.648319
10372 22:18:29.220025 04300000 ################################################################
10373 22:18:29.220204
10374 22:18:29.798459 04380000 ################################################################
10375 22:18:29.798623
10376 22:18:30.384269 04400000 ################################################################
10377 22:18:30.384414
10378 22:18:30.964856 04480000 ################################################################
10379 22:18:30.965001
10380 22:18:31.537858 04500000 ################################################################
10381 22:18:31.538034
10382 22:18:32.113964 04580000 ################################################################
10383 22:18:32.114125
10384 22:18:32.680061 04600000 ################################################################
10385 22:18:32.680205
10386 22:18:33.246823 04680000 ################################################################
10387 22:18:33.246970
10388 22:18:33.820894 04700000 ################################################################
10389 22:18:33.821044
10390 22:18:34.382491 04780000 ################################################################
10391 22:18:34.382645
10392 22:18:34.946705 04800000 ################################################################
10393 22:18:34.946854
10394 22:18:35.506722 04880000 ################################################################
10395 22:18:35.506866
10396 22:18:36.066299 04900000 ################################################################
10397 22:18:36.066444
10398 22:18:36.625091 04980000 ################################################################
10399 22:18:36.625236
10400 22:18:37.202828 04a00000 ################################################################
10401 22:18:37.202967
10402 22:18:37.770343 04a80000 ################################################################
10403 22:18:37.770515
10404 22:18:38.315149 04b00000 ################################################################
10405 22:18:38.315289
10406 22:18:38.870170 04b80000 ################################################################
10407 22:18:38.870312
10408 22:18:39.437305 04c00000 ################################################################
10409 22:18:39.437452
10410 22:18:40.010384 04c80000 ################################################################
10411 22:18:40.010521
10412 22:18:40.572233 04d00000 ################################################################
10413 22:18:40.572375
10414 22:18:41.136120 04d80000 ################################################################
10415 22:18:41.136263
10416 22:18:41.703582 04e00000 ################################################################
10417 22:18:41.703733
10418 22:18:42.267641 04e80000 ################################################################
10419 22:18:42.267796
10420 22:18:42.834661 04f00000 ################################################################
10421 22:18:42.834811
10422 22:18:43.400001 04f80000 ################################################################
10423 22:18:43.400134
10424 22:18:43.971292 05000000 ################################################################
10425 22:18:43.971431
10426 22:18:44.539054 05080000 ################################################################
10427 22:18:44.539198
10428 22:18:45.106287 05100000 ################################################################
10429 22:18:45.106438
10430 22:18:45.683835 05180000 ################################################################
10431 22:18:45.684012
10432 22:18:46.270937 05200000 ################################################################
10433 22:18:46.271088
10434 22:18:46.855706 05280000 ################################################################
10435 22:18:46.855855
10436 22:18:47.448657 05300000 ################################################################
10437 22:18:47.448809
10438 22:18:48.028307 05380000 ################################################################
10439 22:18:48.028455
10440 22:18:48.597499 05400000 ################################################################
10441 22:18:48.597652
10442 22:18:49.177094 05480000 ################################################################
10443 22:18:49.177247
10444 22:18:49.757131 05500000 ################################################################
10445 22:18:49.757272
10446 22:18:50.319299 05580000 ################################################################
10447 22:18:50.319476
10448 22:18:50.885896 05600000 ################################################################
10449 22:18:50.886072
10450 22:18:51.447823 05680000 ################################################################
10451 22:18:51.448009
10452 22:18:52.021849 05700000 ################################################################
10453 22:18:52.022034
10454 22:18:52.592612 05780000 ################################################################
10455 22:18:52.592745
10456 22:18:53.171952 05800000 ################################################################
10457 22:18:53.172114
10458 22:18:53.748471 05880000 ################################################################
10459 22:18:53.748630
10460 22:18:54.316872 05900000 ################################################################
10461 22:18:54.317024
10462 22:18:54.887509 05980000 ################################################################
10463 22:18:54.887659
10464 22:18:55.446311 05a00000 ################################################################
10465 22:18:55.446448
10466 22:18:56.009566 05a80000 ################################################################
10467 22:18:56.009719
10468 22:18:56.608144 05b00000 ################################################################
10469 22:18:56.608298
10470 22:18:57.207691 05b80000 ################################################################
10471 22:18:57.207848
10472 22:18:57.798601 05c00000 ################################################################
10473 22:18:57.798740
10474 22:18:58.375695 05c80000 ################################################################
10475 22:18:58.375851
10476 22:18:58.963235 05d00000 ################################################################
10477 22:18:58.963376
10478 22:18:59.567495 05d80000 ################################################################
10479 22:18:59.567653
10480 22:19:00.166036 05e00000 ################################################################
10481 22:19:00.166198
10482 22:19:00.764429 05e80000 ################################################################
10483 22:19:00.764576
10484 22:19:01.349399 05f00000 ################################################################
10485 22:19:01.349538
10486 22:19:01.939833 05f80000 ################################################################
10487 22:19:01.940026
10488 22:19:02.528364 06000000 ################################################################
10489 22:19:02.528525
10490 22:19:03.126513 06080000 ################################################################
10491 22:19:03.126673
10492 22:19:03.733950 06100000 ################################################################
10493 22:19:03.734107
10494 22:19:04.334008 06180000 ################################################################
10495 22:19:04.334209
10496 22:19:04.936040 06200000 ################################################################
10497 22:19:04.936191
10498 22:19:05.535882 06280000 ################################################################
10499 22:19:05.536089
10500 22:19:06.133793 06300000 ################################################################
10501 22:19:06.133946
10502 22:19:06.739532 06380000 ################################################################
10503 22:19:06.739685
10504 22:19:07.337932 06400000 ################################################################
10505 22:19:07.338088
10506 22:19:07.930037 06480000 ################################################################
10507 22:19:07.930194
10508 22:19:08.522672 06500000 ################################################################
10509 22:19:08.522824
10510 22:19:09.135195 06580000 ################################################################
10511 22:19:09.135352
10512 22:19:09.797649 06600000 ################################################################
10513 22:19:09.798171
10514 22:19:10.519546 06680000 ################################################################
10515 22:19:10.520114
10516 22:19:10.896134 06700000 ################################### done.
10517 22:19:10.896664
10518 22:19:10.899584 The bootfile was 108288578 bytes long.
10519 22:19:10.900119
10520 22:19:10.902955 Sending tftp read request... done.
10521 22:19:10.903381
10522 22:19:10.906820 Waiting for the transfer...
10523 22:19:10.907247
10524 22:19:10.907589 00000000 # done.
10525 22:19:10.907940
10526 22:19:10.912840 Command line loaded dynamically from TFTP file: 10583915/tftp-deploy-z4tjqdiw/kernel/cmdline
10527 22:19:10.913271
10528 22:19:10.926319 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10529 22:19:10.926843
10530 22:19:10.927186 Loading FIT.
10531 22:19:10.927502
10532 22:19:10.929223 Image ramdisk-1 has 98157889 bytes.
10533 22:19:10.929646
10534 22:19:10.933066 Image fdt-1 has 46924 bytes.
10535 22:19:10.933602
10536 22:19:10.936833 Image kernel-1 has 10081729 bytes.
10537 22:19:10.937371
10538 22:19:10.945990 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10539 22:19:10.946515
10540 22:19:10.962967 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10541 22:19:10.963533
10542 22:19:10.965801 Choosing best match conf-1 for compat google,spherion-rev2.
10543 22:19:10.969694
10544 22:19:10.973285 Connected to device vid:did:rid of 1ae0:0028:00
10545 22:19:10.983433
10546 22:19:10.986692 tpm_get_response: command 0x17b, return code 0x0
10547 22:19:10.987225
10548 22:19:10.989850 ec_init: CrosEC protocol v3 supported (256, 248)
10549 22:19:10.994485
10550 22:19:10.997333 tpm_cleanup: add release locality here.
10551 22:19:10.997766
10552 22:19:10.998105 Shutting down all USB controllers.
10553 22:19:11.000523
10554 22:19:11.000971 Removing current net device
10555 22:19:11.001314
10556 22:19:11.007324 Exiting depthcharge with code 4 at timestamp: 166456321
10557 22:19:11.008001
10558 22:19:11.011018 LZMA decompressing kernel-1 to 0x821a6718
10559 22:19:11.011446
10560 22:19:11.014225 LZMA decompressing kernel-1 to 0x40000000
10561 22:19:12.281299
10562 22:19:12.281890 jumping to kernel
10563 22:19:12.283676 end: 2.2.4 bootloader-commands (duration 00:02:18) [common]
10564 22:19:12.284300 start: 2.2.5 auto-login-action (timeout 00:02:07) [common]
10565 22:19:12.284735 Setting prompt string to ['Linux version [0-9]']
10566 22:19:12.285125 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10567 22:19:12.285518 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10568 22:19:12.363468
10569 22:19:12.366693 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10570 22:19:12.371063 start: 2.2.5.1 login-action (timeout 00:02:07) [common]
10571 22:19:12.371650 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10572 22:19:12.372207 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10573 22:19:12.372650 Using line separator: #'\n'#
10574 22:19:12.373005 No login prompt set.
10575 22:19:12.373366 Parsing kernel messages
10576 22:19:12.373688 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10577 22:19:12.374286 [login-action] Waiting for messages, (timeout 00:02:07)
10578 22:19:12.389962 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j1606555-arm64-gcc-10-defconfig-arm64-chromebook-vtq55) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sun Jun 4 21:56:05 UTC 2023
10579 22:19:12.393083 [ 0.000000] random: crng init done
10580 22:19:12.396395 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10581 22:19:12.399514 [ 0.000000] efi: UEFI not found.
10582 22:19:12.409708 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10583 22:19:12.416331 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10584 22:19:12.427031 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10585 22:19:12.436137 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10586 22:19:12.442381 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10587 22:19:12.446049 [ 0.000000] printk: bootconsole [mtk8250] enabled
10588 22:19:12.454833 [ 0.000000] NUMA: No NUMA configuration found
10589 22:19:12.461543 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10590 22:19:12.467994 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcda00-0x23efcffff]
10591 22:19:12.468575 [ 0.000000] Zone ranges:
10592 22:19:12.474565 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10593 22:19:12.478621 [ 0.000000] DMA32 empty
10594 22:19:12.484714 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10595 22:19:12.487781 [ 0.000000] Movable zone start for each node
10596 22:19:12.491465 [ 0.000000] Early memory node ranges
10597 22:19:12.497944 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10598 22:19:12.504188 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10599 22:19:12.510848 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10600 22:19:12.517755 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10601 22:19:12.524386 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10602 22:19:12.530820 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10603 22:19:12.587896 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10604 22:19:12.593949 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10605 22:19:12.600642 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10606 22:19:12.603911 [ 0.000000] psci: probing for conduit method from DT.
10607 22:19:12.610599 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10608 22:19:12.613884 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10609 22:19:12.620769 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10610 22:19:12.624712 [ 0.000000] psci: SMC Calling Convention v1.2
10611 22:19:12.630181 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10612 22:19:12.633923 [ 0.000000] Detected VIPT I-cache on CPU0
10613 22:19:12.640662 [ 0.000000] CPU features: detected: GIC system register CPU interface
10614 22:19:12.647276 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10615 22:19:12.653770 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10616 22:19:12.660480 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10617 22:19:12.667466 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10618 22:19:12.673670 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10619 22:19:12.680781 [ 0.000000] alternatives: applying boot alternatives
10620 22:19:12.683732 [ 0.000000] Fallback order for Node 0: 0
10621 22:19:12.690542 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10622 22:19:12.693503 [ 0.000000] Policy zone: Normal
10623 22:19:12.706822 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10624 22:19:12.716624 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10625 22:19:12.729283 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10626 22:19:12.739399 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10627 22:19:12.746193 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10628 22:19:12.749510 <6>[ 0.000000] software IO TLB: area num 8.
10629 22:19:12.805493 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10630 22:19:12.954592 <6>[ 0.000000] Memory: 7877080K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 475688K reserved, 32768K cma-reserved)
10631 22:19:12.961628 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10632 22:19:12.968008 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10633 22:19:12.971909 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10634 22:19:12.978420 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10635 22:19:12.984668 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10636 22:19:12.988868 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10637 22:19:12.998674 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10638 22:19:13.004356 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10639 22:19:13.008067 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10640 22:19:13.015715 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10641 22:19:13.019376 <6>[ 0.000000] GICv3: 608 SPIs implemented
10642 22:19:13.026009 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10643 22:19:13.028965 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10644 22:19:13.032166 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10645 22:19:13.042139 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10646 22:19:13.051864 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10647 22:19:13.065871 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10648 22:19:13.071675 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10649 22:19:13.081312 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10650 22:19:13.094718 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10651 22:19:13.100985 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10652 22:19:13.107665 <6>[ 0.009175] Console: colour dummy device 80x25
10653 22:19:13.117564 <6>[ 0.013905] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10654 22:19:13.124667 <6>[ 0.024348] pid_max: default: 32768 minimum: 301
10655 22:19:13.127577 <6>[ 0.029221] LSM: Security Framework initializing
10656 22:19:13.134187 <6>[ 0.034158] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10657 22:19:13.144107 <6>[ 0.041972] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10658 22:19:13.150418 <6>[ 0.051318] cblist_init_generic: Setting adjustable number of callback queues.
10659 22:19:13.157236 <6>[ 0.058773] cblist_init_generic: Setting shift to 3 and lim to 1.
10660 22:19:13.163732 <6>[ 0.065151] cblist_init_generic: Setting shift to 3 and lim to 1.
10661 22:19:13.170394 <6>[ 0.071557] rcu: Hierarchical SRCU implementation.
10662 22:19:13.173682 <6>[ 0.076603] rcu: Max phase no-delay instances is 1000.
10663 22:19:13.182495 <6>[ 0.083624] EFI services will not be available.
10664 22:19:13.184951 <6>[ 0.088597] smp: Bringing up secondary CPUs ...
10665 22:19:13.194554 <6>[ 0.093680] Detected VIPT I-cache on CPU1
10666 22:19:13.201033 <6>[ 0.093752] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10667 22:19:13.208134 <6>[ 0.093783] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10668 22:19:13.211471 <6>[ 0.094123] Detected VIPT I-cache on CPU2
10669 22:19:13.217710 <6>[ 0.094176] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10670 22:19:13.224170 <6>[ 0.094194] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10671 22:19:13.230958 <6>[ 0.094456] Detected VIPT I-cache on CPU3
10672 22:19:13.237949 <6>[ 0.094504] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10673 22:19:13.244137 <6>[ 0.094519] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10674 22:19:13.247862 <6>[ 0.094827] CPU features: detected: Spectre-v4
10675 22:19:13.254675 <6>[ 0.094833] CPU features: detected: Spectre-BHB
10676 22:19:13.257137 <6>[ 0.094839] Detected PIPT I-cache on CPU4
10677 22:19:13.264053 <6>[ 0.094898] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10678 22:19:13.270526 <6>[ 0.094916] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10679 22:19:13.278063 <6>[ 0.095213] Detected PIPT I-cache on CPU5
10680 22:19:13.284089 <6>[ 0.095276] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10681 22:19:13.290583 <6>[ 0.095292] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10682 22:19:13.294080 <6>[ 0.095579] Detected PIPT I-cache on CPU6
10683 22:19:13.300513 <6>[ 0.095645] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10684 22:19:13.307377 <6>[ 0.095661] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10685 22:19:13.313506 <6>[ 0.095961] Detected PIPT I-cache on CPU7
10686 22:19:13.320367 <6>[ 0.096026] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10687 22:19:13.327083 <6>[ 0.096042] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10688 22:19:13.330380 <6>[ 0.096091] smp: Brought up 1 node, 8 CPUs
10689 22:19:13.337614 <6>[ 0.237447] SMP: Total of 8 processors activated.
10690 22:19:13.340491 <6>[ 0.242368] CPU features: detected: 32-bit EL0 Support
10691 22:19:13.350335 <6>[ 0.247763] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10692 22:19:13.356355 <6>[ 0.256618] CPU features: detected: Common not Private translations
10693 22:19:13.363090 <6>[ 0.263133] CPU features: detected: CRC32 instructions
10694 22:19:13.366974 <6>[ 0.268485] CPU features: detected: RCpc load-acquire (LDAPR)
10695 22:19:13.373385 <6>[ 0.274481] CPU features: detected: LSE atomic instructions
10696 22:19:13.380166 <6>[ 0.280262] CPU features: detected: Privileged Access Never
10697 22:19:13.386407 <6>[ 0.286042] CPU features: detected: RAS Extension Support
10698 22:19:13.393457 <6>[ 0.291651] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10699 22:19:13.396460 <6>[ 0.298869] CPU: All CPU(s) started at EL2
10700 22:19:13.403622 <6>[ 0.303186] alternatives: applying system-wide alternatives
10701 22:19:13.412359 <6>[ 0.313889] devtmpfs: initialized
10702 22:19:13.427526 <6>[ 0.322611] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10703 22:19:13.434256 <6>[ 0.332575] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10704 22:19:13.440836 <6>[ 0.340594] pinctrl core: initialized pinctrl subsystem
10705 22:19:13.444518 <6>[ 0.347247] DMI not present or invalid.
10706 22:19:13.450976 <6>[ 0.351623] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10707 22:19:13.460726 <6>[ 0.358485] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10708 22:19:13.467074 <6>[ 0.366073] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10709 22:19:13.476967 <6>[ 0.374288] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10710 22:19:13.480851 <6>[ 0.382533] audit: initializing netlink subsys (disabled)
10711 22:19:13.490517 <5>[ 0.388229] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10712 22:19:13.497392 <6>[ 0.388919] thermal_sys: Registered thermal governor 'step_wise'
10713 22:19:13.503749 <6>[ 0.396198] thermal_sys: Registered thermal governor 'power_allocator'
10714 22:19:13.507518 <6>[ 0.402452] cpuidle: using governor menu
10715 22:19:13.513629 <6>[ 0.413412] NET: Registered PF_QIPCRTR protocol family
10716 22:19:13.520144 <6>[ 0.418862] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10717 22:19:13.523492 <6>[ 0.425968] ASID allocator initialised with 32768 entries
10718 22:19:13.530594 <6>[ 0.432516] Serial: AMBA PL011 UART driver
10719 22:19:13.539840 <4>[ 0.441117] Trying to register duplicate clock ID: 134
10720 22:19:13.593506 <6>[ 0.498340] KASLR enabled
10721 22:19:13.607387 <6>[ 0.506061] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10722 22:19:13.614586 <6>[ 0.513074] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10723 22:19:13.620776 <6>[ 0.519566] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10724 22:19:13.627703 <6>[ 0.526572] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10725 22:19:13.634029 <6>[ 0.533061] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10726 22:19:13.640747 <6>[ 0.540066] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10727 22:19:13.647908 <6>[ 0.546553] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10728 22:19:13.653875 <6>[ 0.553559] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10729 22:19:13.657528 <6>[ 0.561082] ACPI: Interpreter disabled.
10730 22:19:13.665713 <6>[ 0.567478] iommu: Default domain type: Translated
10731 22:19:13.672658 <6>[ 0.572592] iommu: DMA domain TLB invalidation policy: strict mode
10732 22:19:13.676058 <5>[ 0.579245] SCSI subsystem initialized
10733 22:19:13.682758 <6>[ 0.583411] usbcore: registered new interface driver usbfs
10734 22:19:13.689086 <6>[ 0.589146] usbcore: registered new interface driver hub
10735 22:19:13.692662 <6>[ 0.594697] usbcore: registered new device driver usb
10736 22:19:13.699187 <6>[ 0.600775] pps_core: LinuxPPS API ver. 1 registered
10737 22:19:13.708725 <6>[ 0.605968] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10738 22:19:13.712627 <6>[ 0.615317] PTP clock support registered
10739 22:19:13.715930 <6>[ 0.619560] EDAC MC: Ver: 3.0.0
10740 22:19:13.723264 <6>[ 0.624701] FPGA manager framework
10741 22:19:13.729535 <6>[ 0.628381] Advanced Linux Sound Architecture Driver Initialized.
10742 22:19:13.732870 <6>[ 0.635151] vgaarb: loaded
10743 22:19:13.739400 <6>[ 0.638318] clocksource: Switched to clocksource arch_sys_counter
10744 22:19:13.743575 <5>[ 0.644759] VFS: Disk quotas dquot_6.6.0
10745 22:19:13.749586 <6>[ 0.648945] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10746 22:19:13.752780 <6>[ 0.656138] pnp: PnP ACPI: disabled
10747 22:19:13.761401 <6>[ 0.662877] NET: Registered PF_INET protocol family
10748 22:19:13.770904 <6>[ 0.668462] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10749 22:19:13.782960 <6>[ 0.680763] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10750 22:19:13.792412 <6>[ 0.689577] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10751 22:19:13.799534 <6>[ 0.697547] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10752 22:19:13.805716 <6>[ 0.706251] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10753 22:19:13.817720 <6>[ 0.716000] TCP: Hash tables configured (established 65536 bind 65536)
10754 22:19:13.824920 <6>[ 0.722854] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10755 22:19:13.830909 <6>[ 0.730050] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10756 22:19:13.838374 <6>[ 0.737751] NET: Registered PF_UNIX/PF_LOCAL protocol family
10757 22:19:13.844776 <6>[ 0.743924] RPC: Registered named UNIX socket transport module.
10758 22:19:13.847240 <6>[ 0.750078] RPC: Registered udp transport module.
10759 22:19:13.854031 <6>[ 0.755012] RPC: Registered tcp transport module.
10760 22:19:13.860735 <6>[ 0.759943] RPC: Registered tcp NFSv4.1 backchannel transport module.
10761 22:19:13.864566 <6>[ 0.766611] PCI: CLS 0 bytes, default 64
10762 22:19:13.867163 <6>[ 0.770869] Unpacking initramfs...
10763 22:19:13.884509 <6>[ 0.782973] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10764 22:19:13.894876 <6>[ 0.791626] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10765 22:19:13.897817 <6>[ 0.800457] kvm [1]: IPA Size Limit: 40 bits
10766 22:19:13.904557 <6>[ 0.804980] kvm [1]: GICv3: no GICV resource entry
10767 22:19:13.907819 <6>[ 0.810003] kvm [1]: disabling GICv2 emulation
10768 22:19:13.914921 <6>[ 0.814692] kvm [1]: GIC system register CPU interface enabled
10769 22:19:13.918027 <6>[ 0.820852] kvm [1]: vgic interrupt IRQ18
10770 22:19:13.924912 <6>[ 0.826386] kvm [1]: VHE mode initialized successfully
10771 22:19:13.931273 <5>[ 0.832794] Initialise system trusted keyrings
10772 22:19:13.938313 <6>[ 0.837558] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10773 22:19:13.945976 <6>[ 0.847565] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10774 22:19:13.952327 <5>[ 0.853966] NFS: Registering the id_resolver key type
10775 22:19:13.955610 <5>[ 0.859271] Key type id_resolver registered
10776 22:19:13.962481 <5>[ 0.863688] Key type id_legacy registered
10777 22:19:13.968776 <6>[ 0.867969] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10778 22:19:13.976005 <6>[ 0.874891] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10779 22:19:13.982286 <6>[ 0.882649] 9p: Installing v9fs 9p2000 file system support
10780 22:19:14.019547 <5>[ 0.921131] Key type asymmetric registered
10781 22:19:14.022848 <5>[ 0.925470] Asymmetric key parser 'x509' registered
10782 22:19:14.032921 <6>[ 0.930621] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10783 22:19:14.036069 <6>[ 0.938238] io scheduler mq-deadline registered
10784 22:19:14.039523 <6>[ 0.942999] io scheduler kyber registered
10785 22:19:14.058380 <6>[ 0.959985] EINJ: ACPI disabled.
10786 22:19:14.090493 <4>[ 0.985233] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10787 22:19:14.100366 <4>[ 0.995862] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10788 22:19:14.115124 <6>[ 1.016575] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10789 22:19:14.123079 <6>[ 1.024605] printk: console [ttyS0] disabled
10790 22:19:14.150981 <6>[ 1.049273] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10791 22:19:14.157131 <6>[ 1.058747] printk: console [ttyS0] enabled
10792 22:19:14.160319 <6>[ 1.058747] printk: console [ttyS0] enabled
10793 22:19:14.167393 <6>[ 1.067641] printk: bootconsole [mtk8250] disabled
10794 22:19:14.170618 <6>[ 1.067641] printk: bootconsole [mtk8250] disabled
10795 22:19:14.177260 <6>[ 1.078883] SuperH (H)SCI(F) driver initialized
10796 22:19:14.180482 <6>[ 1.084141] msm_serial: driver initialized
10797 22:19:14.194846 <6>[ 1.093006] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10798 22:19:14.204269 <6>[ 1.101552] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10799 22:19:14.211120 <6>[ 1.110095] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10800 22:19:14.221263 <6>[ 1.118723] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10801 22:19:14.230547 <6>[ 1.127431] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10802 22:19:14.238230 <6>[ 1.136151] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10803 22:19:14.247649 <6>[ 1.144692] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10804 22:19:14.254786 <6>[ 1.153497] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10805 22:19:14.263919 <6>[ 1.162040] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10806 22:19:14.276162 <6>[ 1.177545] loop: module loaded
10807 22:19:14.282469 <6>[ 1.183501] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10808 22:19:14.304781 <4>[ 1.206481] mtk-pmic-keys: Failed to locate of_node [id: -1]
10809 22:19:14.311742 <6>[ 1.213210] megasas: 07.719.03.00-rc1
10810 22:19:14.320782 <6>[ 1.222768] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10811 22:19:14.328004 <6>[ 1.229717] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10812 22:19:14.344891 <6>[ 1.246502] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10813 22:19:14.405124 <6>[ 1.300693] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10814 22:19:17.872115 <6>[ 4.774185] Freeing initrd memory: 95856K
10815 22:19:17.882560 <6>[ 4.784445] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10816 22:19:17.893403 <6>[ 4.795561] tun: Universal TUN/TAP device driver, 1.6
10817 22:19:17.896758 <6>[ 4.801621] thunder_xcv, ver 1.0
10818 22:19:17.900166 <6>[ 4.805126] thunder_bgx, ver 1.0
10819 22:19:17.903386 <6>[ 4.808622] nicpf, ver 1.0
10820 22:19:17.913675 <6>[ 4.812631] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10821 22:19:17.917050 <6>[ 4.820106] hns3: Copyright (c) 2017 Huawei Corporation.
10822 22:19:17.923949 <6>[ 4.825691] hclge is initializing
10823 22:19:17.926610 <6>[ 4.829275] e1000: Intel(R) PRO/1000 Network Driver
10824 22:19:17.933735 <6>[ 4.834404] e1000: Copyright (c) 1999-2006 Intel Corporation.
10825 22:19:17.937428 <6>[ 4.840419] e1000e: Intel(R) PRO/1000 Network Driver
10826 22:19:17.943162 <6>[ 4.845635] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10827 22:19:17.949959 <6>[ 4.851823] igb: Intel(R) Gigabit Ethernet Network Driver
10828 22:19:17.956701 <6>[ 4.857472] igb: Copyright (c) 2007-2014 Intel Corporation.
10829 22:19:17.963251 <6>[ 4.863309] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10830 22:19:17.970054 <6>[ 4.869826] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10831 22:19:17.973368 <6>[ 4.876287] sky2: driver version 1.30
10832 22:19:17.979754 <6>[ 4.881257] VFIO - User Level meta-driver version: 0.3
10833 22:19:17.987144 <6>[ 4.889398] usbcore: registered new interface driver usb-storage
10834 22:19:17.993826 <6>[ 4.895847] usbcore: registered new device driver onboard-usb-hub
10835 22:19:18.003083 <6>[ 4.904930] mt6397-rtc mt6359-rtc: registered as rtc0
10836 22:19:18.012505 <6>[ 4.910430] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-04T22:19:30 UTC (1685917170)
10837 22:19:18.015644 <6>[ 4.920027] i2c_dev: i2c /dev entries driver
10838 22:19:18.032969 <6>[ 4.931676] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10839 22:19:18.039661 <6>[ 4.941892] sdhci: Secure Digital Host Controller Interface driver
10840 22:19:18.047424 <6>[ 4.948329] sdhci: Copyright(c) Pierre Ossman
10841 22:19:18.053224 <6>[ 4.953748] Synopsys Designware Multimedia Card Interface Driver
10842 22:19:18.056354 <6>[ 4.960464] mmc0: CQHCI version 5.10
10843 22:19:18.062634 <6>[ 4.960896] sdhci-pltfm: SDHCI platform and OF driver helper
10844 22:19:18.070647 <6>[ 4.972642] ledtrig-cpu: registered to indicate activity on CPUs
10845 22:19:18.081351 <6>[ 4.980006] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10846 22:19:18.087422 <6>[ 4.987412] usbcore: registered new interface driver usbhid
10847 22:19:18.090880 <6>[ 4.993240] usbhid: USB HID core driver
10848 22:19:18.097999 <6>[ 4.997496] spi_master spi0: will run message pump with realtime priority
10849 22:19:18.145816 <6>[ 5.041387] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10850 22:19:18.164981 <6>[ 5.057077] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10851 22:19:18.168232 <6>[ 5.070705] mmc0: Command Queue Engine enabled
10852 22:19:18.175580 <6>[ 5.072266] cros-ec-spi spi0.0: Chrome EC device registered
10853 22:19:18.181927 <6>[ 5.075449] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10854 22:19:18.185090 <6>[ 5.088644] mmcblk0: mmc0:0001 DA4128 116 GiB
10855 22:19:18.200278 <6>[ 5.099149] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10856 22:19:18.207281 <6>[ 5.102147] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10857 22:19:18.213242 <6>[ 5.110572] NET: Registered PF_PACKET protocol family
10858 22:19:18.216745 <6>[ 5.116666] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10859 22:19:18.223795 <6>[ 5.119817] 9pnet: Installing 9P2000 support
10860 22:19:18.227033 <6>[ 5.125840] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10861 22:19:18.233726 <5>[ 5.129500] Key type dns_resolver registered
10862 22:19:18.240852 <6>[ 5.135483] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10863 22:19:18.243161 <6>[ 5.139815] registered taskstats version 1
10864 22:19:18.246878 <5>[ 5.150106] Loading compiled-in X.509 certificates
10865 22:19:18.280814 <4>[ 5.176372] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10866 22:19:18.290752 <4>[ 5.187053] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10867 22:19:18.300566 <3>[ 5.199700] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10868 22:19:18.312563 <6>[ 5.214540] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10869 22:19:18.319951 <6>[ 5.221290] xhci-mtk 11200000.usb: xHCI Host Controller
10870 22:19:18.325820 <6>[ 5.226790] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10871 22:19:18.335443 <6>[ 5.234641] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10872 22:19:18.342074 <6>[ 5.244066] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10873 22:19:18.349074 <6>[ 5.250145] xhci-mtk 11200000.usb: xHCI Host Controller
10874 22:19:18.355909 <6>[ 5.255627] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10875 22:19:18.361725 <6>[ 5.263279] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10876 22:19:18.368736 <6>[ 5.270994] hub 1-0:1.0: USB hub found
10877 22:19:18.372242 <6>[ 5.275013] hub 1-0:1.0: 1 port detected
10878 22:19:18.381801 <6>[ 5.279342] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10879 22:19:18.385281 <6>[ 5.287932] hub 2-0:1.0: USB hub found
10880 22:19:18.388946 <6>[ 5.291946] hub 2-0:1.0: 1 port detected
10881 22:19:18.397138 <6>[ 5.299260] mtk-msdc 11f70000.mmc: Got CD GPIO
10882 22:19:18.414381 <6>[ 5.313465] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10883 22:19:18.421259 <6>[ 5.321502] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10884 22:19:18.431111 <4>[ 5.329469] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10885 22:19:18.441076 <6>[ 5.339135] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10886 22:19:18.448071 <6>[ 5.347217] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10887 22:19:18.457375 <6>[ 5.355236] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10888 22:19:18.463866 <6>[ 5.363163] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10889 22:19:18.471185 <6>[ 5.370988] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10890 22:19:18.480393 <6>[ 5.378810] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10891 22:19:18.490675 <6>[ 5.389498] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10892 22:19:18.497164 <6>[ 5.397868] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10893 22:19:18.507658 <6>[ 5.406220] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10894 22:19:18.517617 <6>[ 5.414563] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10895 22:19:18.523804 <6>[ 5.422906] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10896 22:19:18.533760 <6>[ 5.431256] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10897 22:19:18.540468 <6>[ 5.439599] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10898 22:19:18.550279 <6>[ 5.447941] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10899 22:19:18.557121 <6>[ 5.456283] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10900 22:19:18.567169 <6>[ 5.464626] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10901 22:19:18.573282 <6>[ 5.472975] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10902 22:19:18.583235 <6>[ 5.481318] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10903 22:19:18.589813 <6>[ 5.489661] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10904 22:19:18.599942 <6>[ 5.498004] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10905 22:19:18.606968 <6>[ 5.506349] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10906 22:19:18.612720 <6>[ 5.515250] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10907 22:19:18.620068 <6>[ 5.522684] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10908 22:19:18.627261 <6>[ 5.529721] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10909 22:19:18.634749 <6>[ 5.536818] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10910 22:19:18.645632 <6>[ 5.544104] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10911 22:19:18.651393 <6>[ 5.551024] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10912 22:19:18.661399 <6>[ 5.560164] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10913 22:19:18.671653 <6>[ 5.569291] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10914 22:19:18.681180 <6>[ 5.578592] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10915 22:19:18.691608 <6>[ 5.588071] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10916 22:19:18.697845 <6>[ 5.597546] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10917 22:19:18.707326 <6>[ 5.606673] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10918 22:19:18.718181 <6>[ 5.616146] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10919 22:19:18.727910 <6>[ 5.625272] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10920 22:19:18.737690 <6>[ 5.634573] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10921 22:19:18.747408 <6>[ 5.644738] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10922 22:19:18.757489 <6>[ 5.656217] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10923 22:19:18.780318 <6>[ 5.678649] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10924 22:19:18.807107 <6>[ 5.709237] hub 2-1:1.0: USB hub found
10925 22:19:18.810483 <6>[ 5.713687] hub 2-1:1.0: 3 ports detected
10926 22:19:18.931456 <6>[ 5.830589] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10927 22:19:19.086098 <6>[ 5.988173] hub 1-1:1.0: USB hub found
10928 22:19:19.088915 <6>[ 5.992630] hub 1-1:1.0: 4 ports detected
10929 22:19:19.167343 <6>[ 6.066571] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10930 22:19:19.411564 <6>[ 6.310590] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10931 22:19:19.544534 <6>[ 6.446863] hub 1-1.4:1.0: USB hub found
10932 22:19:19.547841 <6>[ 6.451519] hub 1-1.4:1.0: 2 ports detected
10933 22:19:19.843669 <6>[ 6.742592] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10934 22:19:20.035676 <6>[ 6.934592] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10935 22:19:31.055363 <6>[ 17.962995] ALSA device list:
10936 22:19:31.061730 <6>[ 17.966230] No soundcards found.
10937 22:19:31.074304 <6>[ 17.978664] Freeing unused kernel memory: 8384K
10938 22:19:31.078296 <6>[ 17.983573] Run /init as init process
10939 22:19:31.107623 <6>[ 18.012179] NET: Registered PF_INET6 protocol family
10940 22:19:31.114418 <6>[ 18.018255] Segment Routing with IPv6
10941 22:19:31.117931 <6>[ 18.022195] In-situ OAM (IOAM) with IPv6
10942 22:19:31.151765 <30>[ 18.036534] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10943 22:19:31.155493 <30>[ 18.060384] systemd[1]: Detected architecture arm64.
10944 22:19:31.155639
10945 22:19:31.162078 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10946 22:19:31.162232
10947 22:19:31.174423 <30>[ 18.078680] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10948 22:19:31.312414 <30>[ 18.213633] systemd[1]: Queued start job for default target Graphical Interface.
10949 22:19:31.355414 <30>[ 18.259845] systemd[1]: Created slice system-getty.slice.
10950 22:19:31.361753 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10951 22:19:31.378651 <30>[ 18.283167] systemd[1]: Created slice system-modprobe.slice.
10952 22:19:31.385234 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10953 22:19:31.403316 <30>[ 18.307064] systemd[1]: Created slice system-serial\x2dgetty.slice.
10954 22:19:31.412771 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10955 22:19:31.427943 <30>[ 18.331635] systemd[1]: Created slice User and Session Slice.
10956 22:19:31.433795 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10957 22:19:31.454200 <30>[ 18.355128] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10958 22:19:31.464450 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10959 22:19:31.482071 <30>[ 18.383117] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10960 22:19:31.488588 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10961 22:19:31.508980 <30>[ 18.406681] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10962 22:19:31.515387 <30>[ 18.418724] systemd[1]: Reached target Local Encrypted Volumes.
10963 22:19:31.521902 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10964 22:19:31.538888 <30>[ 18.442981] systemd[1]: Reached target Paths.
10965 22:19:31.541847 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10966 22:19:31.558208 <30>[ 18.462630] systemd[1]: Reached target Remote File Systems.
10967 22:19:31.565514 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10968 22:19:31.578231 <30>[ 18.482630] systemd[1]: Reached target Slices.
10969 22:19:31.581721 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10970 22:19:31.598284 <30>[ 18.502645] systemd[1]: Reached target Swap.
10971 22:19:31.601376 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10972 22:19:31.621791 <30>[ 18.522959] systemd[1]: Listening on initctl Compatibility Named Pipe.
10973 22:19:31.628480 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10974 22:19:31.635503 <30>[ 18.537684] systemd[1]: Listening on Journal Audit Socket.
10975 22:19:31.641649 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10976 22:19:31.654545 <30>[ 18.558898] systemd[1]: Listening on Journal Socket (/dev/log).
10977 22:19:31.661146 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10978 22:19:31.678943 <30>[ 18.582902] systemd[1]: Listening on Journal Socket.
10979 22:19:31.685148 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10980 22:19:31.698476 <30>[ 18.602896] systemd[1]: Listening on udev Control Socket.
10981 22:19:31.705152 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10982 22:19:31.723077 <30>[ 18.627258] systemd[1]: Listening on udev Kernel Socket.
10983 22:19:31.729926 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10984 22:19:31.766574 <30>[ 18.670824] systemd[1]: Mounting Huge Pages File System...
10985 22:19:31.773185 Mounting [0;1;39mHuge Pages File System[0m...
10986 22:19:31.788449 <30>[ 18.692490] systemd[1]: Mounting POSIX Message Queue File System...
10987 22:19:31.794907 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10988 22:19:31.812532 <30>[ 18.716570] systemd[1]: Mounting Kernel Debug File System...
10989 22:19:31.818897 Mounting [0;1;39mKernel Debug File System[0m...
10990 22:19:31.837575 <30>[ 18.738885] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10991 22:19:31.848574 <30>[ 18.749795] systemd[1]: Starting Create list of static device nodes for the current kernel...
10992 22:19:31.855235 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10993 22:19:31.891022 <30>[ 18.795085] systemd[1]: Starting Load Kernel Module configfs...
10994 22:19:31.897482 Starting [0;1;39mLoad Kernel Module configfs[0m...
10995 22:19:31.912491 <30>[ 18.816953] systemd[1]: Starting Load Kernel Module drm...
10996 22:19:31.919526 Starting [0;1;39mLoad Kernel Module drm[0m...
10997 22:19:31.937694 <30>[ 18.838793] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10998 22:19:31.948532 <30>[ 18.852487] systemd[1]: Starting Journal Service...
10999 22:19:31.951172 Starting [0;1;39mJournal Service[0m...
11000 22:19:31.968792 <30>[ 18.873294] systemd[1]: Starting Load Kernel Modules...
11001 22:19:31.975624 Starting [0;1;39mLoad Kernel Modules[0m...
11002 22:19:31.996650 <30>[ 18.897553] systemd[1]: Starting Remount Root and Kernel File Systems...
11003 22:19:32.002811 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
11004 22:19:32.020953 <30>[ 18.925242] systemd[1]: Starting Coldplug All udev Devices...
11005 22:19:32.028136 Starting [0;1;39mColdplug All udev Devices[0m...
11006 22:19:32.044865 <30>[ 18.949094] systemd[1]: Mounted Huge Pages File System.
11007 22:19:32.051107 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
11008 22:19:32.067483 <30>[ 18.971419] systemd[1]: Started Journal Service.
11009 22:19:32.073725 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
11010 22:19:32.087633 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
11011 22:19:32.103012 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
11012 22:19:32.123013 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
11013 22:19:32.140615 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
11014 22:19:32.164335 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
11015 22:19:32.179873 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
11016 22:19:32.199439 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
11017 22:19:32.214648 See 'systemctl status systemd-remount-fs.service' for details.
11018 22:19:32.286834 Mounting [0;1;39mKernel Configuration File System[0m...
11019 22:19:32.304616 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
11020 22:19:32.322346 <46>[ 19.223152] systemd-journald[177]: Received client request to flush runtime journal.
11021 22:19:32.330664 Starting [0;1;39mLoad/Save Random Seed[0m...
11022 22:19:32.349032 Starting [0;1;39mApply Kernel Variables[0m...
11023 22:19:32.369188 Starting [0;1;39mCreate System Users[0m...
11024 22:19:32.391778 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
11025 22:19:32.414680 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
11026 22:19:32.430981 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
11027 22:19:32.451773 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
11028 22:19:32.466991 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
11029 22:19:32.482746 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
11030 22:19:32.538636 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
11031 22:19:32.563311 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
11032 22:19:32.578609 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
11033 22:19:32.599366 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
11034 22:19:32.646668 Starting [0;1;39mCreate Volatile Files and Directories[0m...
11035 22:19:32.673724 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
11036 22:19:32.695093 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
11037 22:19:32.718401 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
11038 22:19:32.759312 Starting [0;1;39mNetwork Time Synchronization[0m...
11039 22:19:32.781663 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
11040 22:19:32.818503 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
11041 22:19:32.874756 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
11042 22:19:32.881629 <6>[ 19.783781] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
11043 22:19:32.894969 <6>[ 19.799318] remoteproc remoteproc0: scp is available
11044 22:19:32.904568 <4>[ 19.804886] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
11045 22:19:32.911666 <6>[ 19.814749] remoteproc remoteproc0: powering up scp
11046 22:19:32.921372 <4>[ 19.821602] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
11047 22:19:32.931310 <3>[ 19.823200] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11048 22:19:32.937603 <3>[ 19.831491] remoteproc remoteproc0: request_firmware failed: -2
11049 22:19:32.944694 <3>[ 19.841095] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11050 22:19:32.954434 Startin<3>[ 19.854486] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11051 22:19:32.964518 g [0;1;39mLoad/<3>[ 19.864301] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11052 22:19:32.974254 Save Screen …o<6>[ 19.868370] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
11053 22:19:32.980461 f leds:white:kbd<3>[ 19.873412] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11054 22:19:32.990456 <3>[ 19.873420] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11055 22:19:33.000394 _backlight[0m..<3>[ 19.873431] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11056 22:19:33.000482 .
11057 22:19:33.007040 <3>[ 19.873440] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11058 22:19:33.017012 <3>[ 19.890841] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11059 22:19:33.023504 <6>[ 19.900045] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
11060 22:19:33.033390 <3>[ 19.911148] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11061 22:19:33.043554 <6>[ 19.918377] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
11062 22:19:33.049845 <3>[ 19.925944] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11063 22:19:33.057077 <4>[ 19.954618] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
11064 22:19:33.063095 <6>[ 19.959113] mc: Linux media interface: v0.10
11065 22:19:33.070034 <3>[ 19.959378] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11066 22:19:33.076160 <3>[ 19.960604] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11067 22:19:33.086808 <6>[ 19.960721] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
11068 22:19:33.093370 <4>[ 19.975821] elants_i2c 4-0010: supply vccio not found, using dummy regulator
11069 22:19:33.100506 <3>[ 19.979402] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11070 22:19:33.110445 <3>[ 19.979415] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11071 22:19:33.117003 <3>[ 19.979431] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11072 22:19:33.126642 <3>[ 19.979440] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11073 22:19:33.133285 <3>[ 19.989521] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11074 22:19:33.144183 <4>[ 19.991587] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
11075 22:19:33.147342 <4>[ 19.991587] Fallback method does not support PEC.
11076 22:19:33.156995 <3>[ 20.008671] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11077 22:19:33.163533 <6>[ 20.032088] videodev: Linux video capture interface: v2.00
11078 22:19:33.166658 <6>[ 20.060363] usbcore: registered new interface driver r8152
11079 22:19:33.176310 <6>[ 20.065819] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
11080 22:19:33.180189 <6>[ 20.084712] pci_bus 0000:00: root bus resource [bus 00-ff]
11081 22:19:33.189460 [[0;32m OK [<6>[ 20.090741] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
11082 22:19:33.199525 0m] Started [0;<6>[ 20.099412] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
11083 22:19:33.210155 1;39mNetwork Tim<6>[ 20.111634] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
11084 22:19:33.220046 e Synchronizatio<6>[ 20.112430] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
11085 22:19:33.230182 <6>[ 20.114825] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
11086 22:19:33.237113 <6>[ 20.118142] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
11087 22:19:33.244427 <3>[ 20.128116] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11088 22:19:33.247526 n[0m.
11089 22:19:33.254543 <3>[ 20.128950] power_supply sbs-5-000b: driver failed to report `capacity_error_margin' property: -6
11090 22:19:33.264224 <6>[ 20.130367] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
11091 22:19:33.267265 <6>[ 20.139292] pci 0000:00:00.0: supports D1 D2
11092 22:19:33.277413 <3>[ 20.153778] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11093 22:19:33.283842 <6>[ 20.155153] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11094 22:19:33.294202 <6>[ 20.157840] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
11095 22:19:33.301002 <6>[ 20.165527] usbcore: registered new interface driver cdc_ether
11096 22:19:33.303573 <6>[ 20.174767] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
11097 22:19:33.313617 <6>[ 20.174921] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
11098 22:19:33.316986 <6>[ 20.188434] usbcore: registered new interface driver r8153_ecm
11099 22:19:33.323592 <6>[ 20.188438] Bluetooth: Core ver 2.22
11100 22:19:33.327344 <6>[ 20.188536] NET: Registered PF_BLUETOOTH protocol family
11101 22:19:33.333448 <6>[ 20.188539] Bluetooth: HCI device and connection manager initialized
11102 22:19:33.340724 <6>[ 20.188576] Bluetooth: HCI socket layer initialized
11103 22:19:33.346953 <6>[ 20.188589] Bluetooth: L2CAP socket layer initialized
11104 22:19:33.350003 <6>[ 20.188603] Bluetooth: SCO socket layer initialized
11105 22:19:33.356704 <6>[ 20.194330] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
11106 22:19:33.363096 <6>[ 20.209575] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
11107 22:19:33.373372 <4>[ 20.210801] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
11108 22:19:33.383010 <4>[ 20.210812] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
11109 22:19:33.390324 <6>[ 20.214962] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
11110 22:19:33.402705 <6>[ 20.224016] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
11111 22:19:33.409307 <6>[ 20.228226] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
11112 22:19:33.416401 <6>[ 20.232446] usbcore: registered new interface driver uvcvideo
11113 22:19:33.423196 <6>[ 20.233012] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
11114 22:19:33.426415 <6>[ 20.233108] usbcore: registered new interface driver btusb
11115 22:19:33.437298 <4>[ 20.233997] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
11116 22:19:33.444301 <3>[ 20.234009] Bluetooth: hci0: Failed to load firmware file (-2)
11117 22:19:33.451458 <3>[ 20.234014] Bluetooth: hci0: Failed to set up firmware (-2)
11118 22:19:33.461610 <4>[ 20.234017] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
11119 22:19:33.464766 <6>[ 20.237851] remoteproc remoteproc0: powering up scp
11120 22:19:33.471598 <6>[ 20.237895] pci 0000:01:00.0: supports D1 D2
11121 22:19:33.478123 <6>[ 20.237899] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11122 22:19:33.484924 <6>[ 20.246543] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
11123 22:19:33.494646 <4>[ 20.249882] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
11124 22:19:33.501313 <6>[ 20.254976] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
11125 22:19:33.507924 <3>[ 20.260048] remoteproc remoteproc0: request_firmware failed: -2
11126 22:19:33.514785 <6>[ 20.267513] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
11127 22:19:33.524918 <6>[ 20.267527] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
11128 22:19:33.531625 <3>[ 20.274581] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
11129 22:19:33.535251 <6>[ 20.274738] r8152 2-1.3:1.0 eth0: v1.12.13
11130 22:19:33.544692 <6>[ 20.283601] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
11131 22:19:33.548368 <6>[ 20.286687] r8152 2-1.3:1.0 enx002432307852: renamed from eth0
11132 22:19:33.559159 <3>[ 20.344293] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
11133 22:19:33.565581 <6>[ 20.347802] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
11134 22:19:33.575922 <3>[ 20.350729] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11135 22:19:33.582889 <3>[ 20.351515] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
11136 22:19:33.593522 <3>[ 20.373240] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11137 22:19:33.596408 <6>[ 20.375272] pci 0000:00:00.0: PCI bridge to [bus 01]
11138 22:19:33.606591 <3>[ 20.410575] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11139 22:19:33.616735 <6>[ 20.411440] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
11140 22:19:33.623399 <3>[ 20.438365] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11141 22:19:33.629918 <6>[ 20.441320] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
11142 22:19:33.636297 [[0;32m OK [<6>[ 20.540734] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
11143 22:19:33.646464 0m] Finished [0<6>[ 20.548213] pcieport 0000:00:00.0: AER: enabled with IRQ 283
11144 22:19:33.649945 ;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
11145 22:19:33.666555 <5>[ 20.567843] cfg80211: Loading compiled-in X.509 certificates for regulatory database
11146 22:19:33.678554 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
11147 22:19:33.684751 <5>[ 20.588676] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
11148 22:19:33.694498 <4>[ 20.595628] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
11149 22:19:33.701135 <6>[ 20.604517] cfg80211: failed to load regulatory.db
11150 22:19:33.747236 <6>[ 20.648500] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
11151 22:19:33.753735 <6>[ 20.656018] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
11152 22:19:33.778053 <6>[ 20.682488] mt7921e 0000:01:00.0: ASIC revision: 79610010
11153 22:19:33.861503 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
11154 22:19:33.884703 <4>[ 20.782635] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11155 22:19:33.891015 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
11156 22:19:33.909768 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
11157 22:19:33.926218 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
11158 22:19:33.942103 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
11159 22:19:33.961690 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
11160 22:19:33.973865 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
11161 22:19:34.005814 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message B<4>[ 20.901814] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11162 22:19:34.005934 us Socket[0m.
11163 22:19:34.022897 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
11164 22:19:34.037896 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
11165 22:19:34.057561 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
11166 22:19:34.090735 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
11167 22:19:34.124587 <4>[ 21.022781] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11168 22:19:34.135125 Starting [0;1;39mUser Login Management[0m...
11169 22:19:34.152724 Starting [0;1;39mPermit User Sessions[0m...
11170 22:19:34.171090 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
11171 22:19:34.186410 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
11172 22:19:34.203576 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11173 22:19:34.214472 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11174 22:19:34.248205 <4>[ 21.145925] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11175 22:19:34.254736 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11176 22:19:34.261493 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11177 22:19:34.284116 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11178 22:19:34.290957 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11179 22:19:34.306284 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11180 22:19:34.366866 <4>[ 21.265040] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11181 22:19:34.373748 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11182 22:19:34.402957 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11183 22:19:34.421518
11184 22:19:34.421603
11185 22:19:34.424836 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11186 22:19:34.424911
11187 22:19:34.427878 debian-bullseye-arm64 login: root (automatic login)
11188 22:19:34.427970
11189 22:19:34.428046
11190 22:19:34.444971 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Sun Jun 4 21:56:05 UTC 2023 aarch64
11191 22:19:34.445061
11192 22:19:34.451146 The programs included with the Debian GNU/Linux system are free software;
11193 22:19:34.457826 the exact distribution terms for each program are described in the
11194 22:19:34.460834 individual files in /usr/share/doc/*/copyright.
11195 22:19:34.460914
11196 22:19:34.467408 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11197 22:19:34.470649 permitted by applicable law.
11198 22:19:34.470994 Matched prompt #10: / #
11200 22:19:34.471251 Setting prompt string to ['/ #']
11201 22:19:34.471350 end: 2.2.5.1 login-action (duration 00:00:22) [common]
11203 22:19:34.471550 end: 2.2.5 auto-login-action (duration 00:00:22) [common]
11204 22:19:34.471639 start: 2.2.6 expect-shell-connection (timeout 00:01:45) [common]
11205 22:19:34.471712 Setting prompt string to ['/ #']
11206 22:19:34.471776 Forcing a shell prompt, looking for ['/ #']
11208 22:19:34.521960 / #
11209 22:19:34.522072 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11210 22:19:34.522217 Waiting using forced prompt support (timeout 00:02:30)
11211 22:19:34.522354 <4>[ 21.384920] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11212 22:19:34.526740
11213 22:19:34.527001 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11214 22:19:34.527094 start: 2.2.7 export-device-env (timeout 00:01:45) [common]
11215 22:19:34.527188 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11216 22:19:34.527278 end: 2.2 depthcharge-retry (duration 00:03:15) [common]
11217 22:19:34.527385 end: 2 depthcharge-action (duration 00:03:15) [common]
11218 22:19:34.527488 start: 3 lava-test-retry (timeout 00:05:00) [common]
11219 22:19:34.527575 start: 3.1 lava-test-shell (timeout 00:05:00) [common]
11220 22:19:34.527651 Using namespace: common
11222 22:19:34.627933 / # #
11223 22:19:34.628126 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:05:00)
11224 22:19:34.628239 #<4>[ 21.504877] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11225 22:19:34.633292
11226 22:19:34.633547 Using /lava-10583915
11228 22:19:34.733880 / # export SHELL=/bin/sh
11229 22:19:34.734117 export SHELL=/bin/sh<4>[ 21.624977] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11230 22:19:34.738479
11232 22:19:34.838937 / #. /lava-10583915/environment
11233 22:19:34.880078 . /lava-10583915/environment<4>[ 21.744974] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11234 22:19:34.880198
11236 22:19:34.980666 / # /lava-10583915/bin/lava-test-runner /lava-10583915/0
11237 22:19:34.980804 Test shell timeout: 10s (minimum of the action and connection timeout)
11238 22:19:34.981195 /lava-10583915/bin/lava-test-runner /lava-10583915/0<4>[ 21.864740] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11239 22:19:34.986046
11240 22:19:35.028037 + export TESTRUN_ID=0_sleep
11241 22:19:35.028149 + cd /lava-10583915/0/tests/0_sleep
11242 22:19:35.028233 + cat uuid
11243 22:19:35.028299 + UUID=10583915_1.5.2.3.1
11244 22:19:35.028362 + set +x
11245 22:19:35.028596 <LAVA_SIGNAL_STARTRUN 0_sleep 10583915_1.5.2.3.1>
11246 22:19:35.028661 + ./config/lava/sleep/sleep.sh mem freeze
11247 22:19:35.028907 Received signal: <STARTRUN> 0_sleep 10583915_1.5.2.3.1
11248 22:19:35.029000 Starting test lava.0_sleep (10583915_1.5.2.3.1)
11249 22:19:35.029095 Skipping test definition patterns.
11250 22:19:35.029188 Received signal: <TESTCASE> TEST_CASE_ID=rtc-exist RESULT=pass
11252 22:19:35.029393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc-exist RESULT=pass>
11253 22:19:35.032322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc-wakeup-enabled RESULT=pass>
11254 22:19:35.032559 Received signal: <TESTCASE> TEST_CASE_ID=rtc-wakeup-enabled RESULT=pass
11256 22:19:35.035840 rtcwake: assuming RTC uses UTC ...
11257 22:19:35.043109 rtcwake: wakeup from "mem" usi<6>[ 21.948736] PM: suspend entry (deep)
11258 22:19:35.049274 ng rtc0 at Sun J<6>[ 21.952957] Filesystems sync: 0.000 seconds
11259 22:19:35.052585 un 4 22:19:53 2023
11260 22:19:35.055392 <6>[ 21.961169] Freezing user space processes
11261 22:19:35.066339 <6>[ 21.967315] Freezing user space processes completed (elapsed 0.001 seconds)
11262 22:19:35.069517 <6>[ 21.974594] OOM killer disabled.
11263 22:19:35.072865 <6>[ 21.978077] Freezing remaining freezable tasks
11264 22:19:35.079567 <3>[ 21.982676] mt7921e 0000:01:00.0: hardware init failed
11265 22:19:35.085646 <6>[ 21.984124] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11266 22:19:35.092693 <6>[ 21.995849] printk: Suspending console(s) (use no_console_suspend to debug)
11267 22:19:38.483750 <3>[ 25.162666] mt7921e 0000:01:00.0: Message 00020007 (seq 6) timeout
11268 22:19:38.493763 <3>[ 25.162725] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11269 22:19:38.503344 <3>[ 25.162758] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11270 22:19:38.510155 <3>[ 25.162786] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11271 22:19:38.516906 <3>[ 25.163038] PM: Some devices failed to suspend, or early wake event detected
11272 22:19:38.526509 <4>[ 25.178167] typec port0-partner: PM: parent port0 should not be sleeping
11273 22:19:38.529881 <6>[ 25.435322] OOM killer enabled.
11274 22:19:38.536691 <6>[ 25.438727] Restarting tasks ... done.
11275 22:19:38.539946 <5>[ 25.445435] random: crng reseeded on system resumption
11276 22:19:38.543862 <6>[ 25.452517] PM: suspend exit
11277 22:19:38.547521 rtcwake: write error
11278 22:19:38.555494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-1 RESULT=fail>
11279 22:19:38.555768 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-1 RESULT=fail
11281 22:19:38.558779 rtcwake: assuming RTC uses UTC ...
11282 22:19:38.566073 rtcwake: wakeup from "mem" using rtc0 at Sun Jun 4 22:19:57 2023
11283 22:19:38.578312 <6>[ 25.483387] PM: suspend entry (deep)
11284 22:19:38.581611 <6>[ 25.487278] Filesystems sync: 0.000 seconds
11285 22:19:38.584988 <6>[ 25.492396] Freezing user space processes
11286 22:19:38.596171 <6>[ 25.498353] Freezing user space processes completed (elapsed 0.001 seconds)
11287 22:19:38.599715 <6>[ 25.505574] OOM killer disabled.
11288 22:19:38.602977 <6>[ 25.509058] Freezing remaining freezable tasks
11289 22:19:38.612972 <6>[ 25.514990] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11290 22:19:38.619540 <6>[ 25.522656] printk: Suspending console(s) (use no_console_suspend to debug)
11291 22:19:42.074550 <3>[ 28.746637] mt7921e 0000:01:00.0: Message 00020007 (seq 7) timeout
11292 22:19:42.084430 <3>[ 28.746661] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11293 22:19:42.094679 <3>[ 28.746694] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11294 22:19:42.101356 <3>[ 28.746716] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11295 22:19:42.107908 <3>[ 28.747274] PM: Some devices failed to suspend, or early wake event detected
11296 22:19:42.110837 <6>[ 29.019743] OOM killer enabled.
11297 22:19:42.118999 <6>[ 29.023147] Restarting tasks ... done.
11298 22:19:42.122255 <5>[ 29.028626] random: crng reseeded on system resumption
11299 22:19:42.126669 <6>[ 29.035437] PM: suspend exit
11300 22:19:42.129848 rtcwake: write error
11301 22:19:42.138215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-2 RESULT=fail>
11302 22:19:42.138549 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-2 RESULT=fail
11304 22:19:42.141070 rtcwake: assuming RTC uses UTC ...
11305 22:19:42.147873 rtcwake: wakeup from "mem" using rtc0 at Sun Jun 4 22:20:00 2023
11306 22:19:42.161416 <6>[ 29.066528] PM: suspend entry (deep)
11307 22:19:42.164248 <6>[ 29.070446] Filesystems sync: 0.000 seconds
11308 22:19:42.167736 <6>[ 29.075506] Freezing user space processes
11309 22:19:42.179213 <6>[ 29.081504] Freezing user space processes completed (elapsed 0.001 seconds)
11310 22:19:42.182916 <6>[ 29.088831] OOM killer disabled.
11311 22:19:42.185683 <6>[ 29.092322] Freezing remaining freezable tasks
11312 22:19:42.196779 <6>[ 29.098454] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11313 22:19:42.202976 <6>[ 29.106133] printk: Suspending console(s) (use no_console_suspend to debug)
11314 22:19:45.661743 <3>[ 32.330589] mt7921e 0000:01:00.0: Message 00020007 (seq 8) timeout
11315 22:19:45.671934 <3>[ 32.330620] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11316 22:19:45.682247 <3>[ 32.330651] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11317 22:19:45.688595 <3>[ 32.330671] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11318 22:19:45.695118 <3>[ 32.331145] PM: Some devices failed to suspend, or early wake event detected
11319 22:19:45.701672 <6>[ 32.607794] OOM killer enabled.
11320 22:19:45.704975 <6>[ 32.611192] Restarting tasks ... done.
11321 22:19:45.711503 <5>[ 32.616729] random: crng reseeded on system resumption
11322 22:19:45.715053 <6>[ 32.624371] PM: suspend exit
11323 22:19:45.718134 rtcwake: write error
11324 22:19:45.726169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-3 RESULT=fail>
11325 22:19:45.726534 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-3 RESULT=fail
11327 22:19:45.729551 rtcwake: assuming RTC uses UTC ...
11328 22:19:45.736213 rtcwake: wakeup from "mem" using rtc0 at Sun Jun 4 22:20:04 2023
11329 22:19:45.748875 <6>[ 32.654865] PM: suspend entry (deep)
11330 22:19:45.752681 <6>[ 32.658771] Filesystems sync: 0.000 seconds
11331 22:19:45.755850 <6>[ 32.663871] Freezing user space processes
11332 22:19:45.767407 <6>[ 32.669919] Freezing user space processes completed (elapsed 0.001 seconds)
11333 22:19:45.770498 <6>[ 32.677176] OOM killer disabled.
11334 22:19:45.774253 <6>[ 32.680659] Freezing remaining freezable tasks
11335 22:19:45.783943 <6>[ 32.686381] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11336 22:19:45.790897 <6>[ 32.694036] printk: Suspending console(s) (use no_console_suspend to debug)
11337 22:19:49.242124 <3>[ 35.914598] mt7921e 0000:01:00.0: Message 00020007 (seq 9) timeout
11338 22:19:49.252710 <3>[ 35.914622] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11339 22:19:49.262450 <3>[ 35.914648] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11340 22:19:49.269368 <3>[ 35.914670] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11341 22:19:49.275658 <3>[ 35.915090] PM: Some devices failed to suspend, or early wake event detected
11342 22:19:49.278914 <6>[ 36.188368] OOM killer enabled.
11343 22:19:49.287321 <6>[ 36.191771] Restarting tasks ... done.
11344 22:19:49.290986 <5>[ 36.197846] random: crng reseeded on system resumption
11345 22:19:49.295099 <6>[ 36.204895] PM: suspend exit
11346 22:19:49.298559 rtcwake: write error
11347 22:19:49.306537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-4 RESULT=fail>
11348 22:19:49.306858 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-4 RESULT=fail
11350 22:19:49.310321 rtcwake: assuming RTC uses UTC ...
11351 22:19:49.316486 rtcwake: wakeup from "mem" using rtc0 at Sun Jun 4 22:20:08 2023
11352 22:19:49.329688 <6>[ 36.235904] PM: suspend entry (deep)
11353 22:19:49.332822 <6>[ 36.239804] Filesystems sync: 0.000 seconds
11354 22:19:49.335817 <6>[ 36.244894] Freezing user space processes
11355 22:19:49.347879 <6>[ 36.250957] Freezing user space processes completed (elapsed 0.001 seconds)
11356 22:19:49.350987 <6>[ 36.258182] OOM killer disabled.
11357 22:19:49.354484 <6>[ 36.261664] Freezing remaining freezable tasks
11358 22:19:49.364939 <6>[ 36.267738] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11359 22:19:49.370944 <6>[ 36.275395] printk: Suspending console(s) (use no_console_suspend to debug)
11360 22:19:52.821520 <3>[ 39.498595] mt7921e 0000:01:00.0: Message 00020007 (seq 10) timeout
11361 22:19:52.831511 <3>[ 39.498621] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11362 22:19:52.841374 <3>[ 39.498654] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11363 22:19:52.848484 <3>[ 39.498674] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11364 22:19:52.855192 <3>[ 39.498976] PM: Some devices failed to suspend, or early wake event detected
11365 22:19:52.861704 <6>[ 39.768252] OOM killer enabled.
11366 22:19:52.864942 <6>[ 39.771651] Restarting tasks ... done.
11367 22:19:52.871041 <5>[ 39.777373] random: crng reseeded on system resumption
11368 22:19:52.875278 <6>[ 39.784122] PM: suspend exit
11369 22:19:52.878182 rtcwake: write error
11370 22:19:52.884888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-5 RESULT=fail>
11371 22:19:52.885178 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-5 RESULT=fail
11373 22:19:52.889027 rtcwake: assuming RTC uses UTC ...
11374 22:19:52.894618 rtcwake: wakeup from "mem" using rtc0 at Sun Jun 4 22:20:11 2023
11375 22:19:52.908465 <6>[ 39.814680] PM: suspend entry (deep)
11376 22:19:52.911677 <6>[ 39.818618] Filesystems sync: 0.000 seconds
11377 22:19:52.914565 <6>[ 39.823741] Freezing user space processes
11378 22:19:52.926112 <6>[ 39.829721] Freezing user space processes completed (elapsed 0.001 seconds)
11379 22:19:52.929513 <6>[ 39.837017] OOM killer disabled.
11380 22:19:52.933046 <6>[ 39.840507] Freezing remaining freezable tasks
11381 22:19:52.943081 <6>[ 39.846403] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11382 22:19:52.949593 <6>[ 39.854057] printk: Suspending console(s) (use no_console_suspend to debug)
11383 22:19:56.410060 <3>[ 43.082595] mt7921e 0000:01:00.0: Message 00020007 (seq 11) timeout
11384 22:19:56.423254 <3>[ 43.082621] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11385 22:19:56.429820 <3>[ 43.082654] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11386 22:19:56.436177 <3>[ 43.082675] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11387 22:19:56.446808 <3>[ 43.083116] PM: Some devices failed to suspend, or early wake event detected
11388 22:19:56.449127 <6>[ 43.356456] OOM killer enabled.
11389 22:19:56.452741 <6>[ 43.359858] Restarting tasks ... done.
11390 22:19:56.459769 <5>[ 43.365983] random: crng reseeded on system resumption
11391 22:19:56.463538 <6>[ 43.373574] PM: suspend exit
11392 22:19:56.467719 rtcwake: write error
11393 22:19:56.474495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-6 RESULT=fail>
11394 22:19:56.475249 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-6 RESULT=fail
11396 22:19:56.478320 rtcwake: assuming RTC uses UTC ...
11397 22:19:56.484590 rtcwake: wakeup from "mem" using rtc0 at Sun Jun 4 22:20:15 2023
11398 22:19:56.497959 <6>[ 43.404337] PM: suspend entry (deep)
11399 22:19:56.501523 <6>[ 43.408250] Filesystems sync: 0.000 seconds
11400 22:19:56.504350 <6>[ 43.413301] Freezing user space processes
11401 22:19:56.515947 <6>[ 43.419199] Freezing user space processes completed (elapsed 0.001 seconds)
11402 22:19:56.518896 <6>[ 43.426420] OOM killer disabled.
11403 22:19:56.522583 <6>[ 43.429896] Freezing remaining freezable tasks
11404 22:19:56.532727 <6>[ 43.436045] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11405 22:19:56.539283 <6>[ 43.443738] printk: Suspending console(s) (use no_console_suspend to debug)
11406 22:19:59.984753 <3>[ 46.666618] mt7921e 0000:01:00.0: Message 00020007 (seq 12) timeout
11407 22:19:59.997995 <3>[ 46.666645] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11408 22:20:00.004315 <3>[ 46.666685] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11409 22:20:00.011520 <3>[ 46.666708] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11410 22:20:00.021506 <3>[ 46.667072] PM: Some devices failed to suspend, or early wake event detected
11411 22:20:00.024373 <6>[ 46.932151] OOM killer enabled.
11412 22:20:00.027724 <6>[ 46.935550] Restarting tasks ... done.
11413 22:20:00.034405 <5>[ 46.941261] random: crng reseeded on system resumption
11414 22:20:00.037624 <6>[ 46.947880] PM: suspend exit
11415 22:20:00.040879 rtcwake: write error
11416 22:20:00.048806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-7 RESULT=fail>
11417 22:20:00.049631 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-7 RESULT=fail
11419 22:20:00.051831 rtcwake: assuming RTC uses UTC ...
11420 22:20:00.058349 rtcwake: wakeup from "mem" using rtc0 at Sun Jun 4 22:20:18 2023
11421 22:20:00.071123 <6>[ 46.978572] PM: suspend entry (deep)
11422 22:20:00.074346 <6>[ 46.982505] Filesystems sync: 0.000 seconds
11423 22:20:00.081389 <6>[ 46.987644] Freezing user space processes
11424 22:20:00.087680 <6>[ 46.993753] Freezing user space processes completed (elapsed 0.001 seconds)
11425 22:20:00.091090 <6>[ 47.001017] OOM killer disabled.
11426 22:20:00.097928 <6>[ 47.004501] Freezing remaining freezable tasks
11427 22:20:00.104520 <6>[ 47.010412] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11428 22:20:00.114041 <6>[ 47.018068] printk: Suspending console(s) (use no_console_suspend to debug)
11429 22:20:03.565235 <6>[ 48.202682] vpu: disabling
11430 22:20:03.568479 <6>[ 48.202776] vproc2: disabling
11431 22:20:03.572135 <6>[ 48.202814] vproc1: disabling
11432 22:20:03.575393 <6>[ 48.202852] vaud18: disabling
11433 22:20:03.578647 <6>[ 48.203035] vsram_others: disabling
11434 22:20:03.582328 <6>[ 48.203180] va09: disabling
11435 22:20:03.584596 <6>[ 48.203235] vsram_md: disabling
11436 22:20:03.588495 <6>[ 48.203331] Vgpu: disabling
11437 22:20:03.594907 <3>[ 50.250630] mt7921e 0000:01:00.0: Message 00020007 (seq 13) timeout
11438 22:20:03.605414 <3>[ 50.250666] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11439 22:20:03.615184 <3>[ 50.250702] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11440 22:20:03.621880 <3>[ 50.250723] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11441 22:20:03.628411 <3>[ 50.250968] PM: Some devices failed to suspend, or early wake event detected
11442 22:20:03.631464 <6>[ 50.541542] OOM killer enabled.
11443 22:20:03.639392 <6>[ 50.544940] Restarting tasks ... done.
11444 22:20:03.642764 <5>[ 50.550783] random: crng reseeded on system resumption
11445 22:20:03.646730 <6>[ 50.557125] PM: suspend exit
11446 22:20:03.649975 rtcwake: write error
11447 22:20:03.657575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-8 RESULT=fail>
11448 22:20:03.658444 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-8 RESULT=fail
11450 22:20:03.660615 rtcwake: assuming RTC uses UTC ...
11451 22:20:03.667940 rtcwake: wakeup from "mem" using rtc0 at Sun Jun 4 22:20:22 2023
11452 22:20:03.680064 <6>[ 50.587549] PM: suspend entry (deep)
11453 22:20:03.683335 <6>[ 50.591460] Filesystems sync: 0.000 seconds
11454 22:20:03.689750 <6>[ 50.596676] Freezing user space processes
11455 22:20:03.697705 <6>[ 50.602467] Freezing user space processes completed (elapsed 0.001 seconds)
11456 22:20:03.699799 <6>[ 50.609694] OOM killer disabled.
11457 22:20:03.706792 <6>[ 50.613177] Freezing remaining freezable tasks
11458 22:20:03.713174 <6>[ 50.619177] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11459 22:20:03.722550 <6>[ 50.626845] printk: Suspending console(s) (use no_console_suspend to debug)
11460 22:20:07.159791 <3>[ 53.834608] mt7921e 0000:01:00.0: Message 00020007 (seq 14) timeout
11461 22:20:07.169984 <3>[ 53.834644] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11462 22:20:07.179834 <3>[ 53.834680] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11463 22:20:07.186180 <3>[ 53.834708] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11464 22:20:07.192970 <3>[ 53.835046] PM: Some devices failed to suspend, or early wake event detected
11465 22:20:07.196276 <6>[ 54.107794] OOM killer enabled.
11466 22:20:07.204492 <6>[ 54.111193] Restarting tasks ... done.
11467 22:20:07.207951 <5>[ 54.116886] random: crng reseeded on system resumption
11468 22:20:07.212403 <6>[ 54.123976] PM: suspend exit
11469 22:20:07.215811 rtcwake: write error
11470 22:20:07.223779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-9 RESULT=fail>
11471 22:20:07.224505 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-9 RESULT=fail
11473 22:20:07.227289 rtcwake: assuming RTC uses UTC ...
11474 22:20:07.233980 rtcwake: wakeup from "mem" using rtc0 at Sun Jun 4 22:20:25 2023
11475 22:20:07.246370 <6>[ 54.154655] PM: suspend entry (deep)
11476 22:20:07.249915 <6>[ 54.158546] Filesystems sync: 0.000 seconds
11477 22:20:07.253214 <6>[ 54.163560] Freezing user space processes
11478 22:20:07.264566 <6>[ 54.169440] Freezing user space processes completed (elapsed 0.001 seconds)
11479 22:20:07.268080 <6>[ 54.176719] OOM killer disabled.
11480 22:20:07.271088 <6>[ 54.180206] Freezing remaining freezable tasks
11481 22:20:07.281292 <6>[ 54.186133] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11482 22:20:07.287756 <6>[ 54.193786] printk: Suspending console(s) (use no_console_suspend to debug)
11483 22:20:10.742739 <3>[ 57.418568] mt7921e 0000:01:00.0: Message 00020007 (seq 15) timeout
11484 22:20:10.752888 <3>[ 57.418592] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11485 22:20:10.763140 <3>[ 57.418618] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11486 22:20:10.769106 <3>[ 57.418639] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11487 22:20:10.779028 <3>[ 57.419015] PM: Some devices failed to suspend, or early wake event detected
11488 22:20:10.782909 <6>[ 57.691805] OOM killer enabled.
11489 22:20:10.786237 <6>[ 57.695204] Restarting tasks ... done.
11490 22:20:10.792610 <5>[ 57.700793] random: crng reseeded on system resumption
11491 22:20:10.795915 <6>[ 57.707753] PM: suspend exit
11492 22:20:10.799381 rtcwake: write error
11493 22:20:10.806806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-10 RESULT=fail>
11494 22:20:10.807118 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-10 RESULT=fail
11496 22:20:10.810310 rtcwake: assuming RTC uses UTC ...
11497 22:20:10.816453 rtcwake: wakeup from "freeze" using rtc0 at Sun Jun 4 22:20:29 2023
11498 22:20:10.830900 <6>[ 57.739958] PM: suspend entry (s2idle)
11499 22:20:10.834066 <6>[ 57.744035] Filesystems sync: 0.000 seconds
11500 22:20:10.840838 <6>[ 57.749080] Freezing user space processes
11501 22:20:10.847652 <6>[ 57.755073] Freezing user space processes completed (elapsed 0.001 seconds)
11502 22:20:10.851241 <6>[ 57.762344] OOM killer disabled.
11503 22:20:10.857748 <6>[ 57.765822] Freezing remaining freezable tasks
11504 22:20:10.864344 <6>[ 57.771731] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11505 22:20:10.874083 <6>[ 57.779389] printk: Suspending console(s) (use no_console_suspend to debug)
11506 22:20:14.327116 <3>[ 61.002566] mt7921e 0000:01:00.0: Message 00020007 (seq 1) timeout
11507 22:20:14.336880 <3>[ 61.002590] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11508 22:20:14.346923 <3>[ 61.002615] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11509 22:20:14.353783 <3>[ 61.002637] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11510 22:20:14.360035 <3>[ 61.003126] PM: Some devices failed to suspend, or early wake event detected
11511 22:20:14.366750 <6>[ 61.276222] OOM killer enabled.
11512 22:20:14.370050 <6>[ 61.279622] Restarting tasks ... done.
11513 22:20:14.376548 <5>[ 61.285207] random: crng reseeded on system resumption
11514 22:20:14.379928 <6>[ 61.291896] PM: suspend exit
11515 22:20:14.383158 rtcwake: write error
11516 22:20:14.390336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-1 RESULT=fail>
11517 22:20:14.390600 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-1 RESULT=fail
11519 22:20:14.393738 rtcwake: assuming RTC uses UTC ...
11520 22:20:14.400192 rtcwake: wakeup from "freeze" using rtc0 at Sun Jun 4 22:20:33 2023
11521 22:20:14.413518 <6>[ 61.322546] PM: suspend entry (s2idle)
11522 22:20:14.416754 <6>[ 61.326613] Filesystems sync: 0.000 seconds
11523 22:20:14.422821 <6>[ 61.331623] Freezing user space processes
11524 22:20:14.429917 <6>[ 61.337468] Freezing user space processes completed (elapsed 0.001 seconds)
11525 22:20:14.433300 <6>[ 61.344749] OOM killer disabled.
11526 22:20:14.439448 <6>[ 61.348243] Freezing remaining freezable tasks
11527 22:20:14.446097 <6>[ 61.354160] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11528 22:20:14.456041 <6>[ 61.361814] printk: Suspending console(s) (use no_console_suspend to debug)
11529 22:20:17.910739 <3>[ 64.586592] mt7921e 0000:01:00.0: Message 00020007 (seq 2) timeout
11530 22:20:17.920188 <3>[ 64.586616] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11531 22:20:17.930965 <3>[ 64.586650] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11532 22:20:17.937429 <3>[ 64.586671] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11533 22:20:17.943748 <3>[ 64.587100] PM: Some devices failed to suspend, or early wake event detected
11534 22:20:17.950729 <6>[ 64.860222] OOM killer enabled.
11535 22:20:17.953598 <6>[ 64.863620] Restarting tasks ... done.
11536 22:20:17.960266 <5>[ 64.869275] random: crng reseeded on system resumption
11537 22:20:17.963437 <6>[ 64.876181] PM: suspend exit
11538 22:20:17.966865 rtcwake: write error
11539 22:20:17.974520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-2 RESULT=fail>
11540 22:20:17.974782 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-2 RESULT=fail
11542 22:20:17.977792 rtcwake: assuming RTC uses UTC ...
11543 22:20:17.984539 rtcwake: wakeup from "freeze" using rtc0 at Sun Jun 4 22:20:36 2023
11544 22:20:17.997329 <6>[ 64.906824] PM: suspend entry (s2idle)
11545 22:20:18.000114 <6>[ 64.910915] Filesystems sync: 0.000 seconds
11546 22:20:18.006859 <6>[ 64.916028] Freezing user space processes
11547 22:20:18.013729 <6>[ 64.922110] Freezing user space processes completed (elapsed 0.001 seconds)
11548 22:20:18.017073 <6>[ 64.929442] OOM killer disabled.
11549 22:20:18.023436 <6>[ 64.932941] Freezing remaining freezable tasks
11550 22:20:18.030363 <6>[ 64.938911] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11551 22:20:18.039911 <6>[ 64.946567] printk: Suspending console(s) (use no_console_suspend to debug)
11552 22:20:21.494229 <3>[ 68.170589] mt7921e 0000:01:00.0: Message 00020007 (seq 3) timeout
11553 22:20:21.504568 <3>[ 68.170614] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11554 22:20:21.514187 <3>[ 68.170647] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11555 22:20:21.521151 <3>[ 68.170668] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11556 22:20:21.527690 <3>[ 68.170967] PM: Some devices failed to suspend, or early wake event detected
11557 22:20:21.530749 <6>[ 68.444360] OOM killer enabled.
11558 22:20:21.539721 <6>[ 68.447762] Restarting tasks ... done.
11559 22:20:21.542808 <5>[ 68.453818] random: crng reseeded on system resumption
11560 22:20:21.548137 <6>[ 68.461149] PM: suspend exit
11561 22:20:21.551260 rtcwake: write error
11562 22:20:21.558844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-3 RESULT=fail>
11563 22:20:21.559141 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-3 RESULT=fail
11565 22:20:21.561913 rtcwake: assuming RTC uses UTC ...
11566 22:20:21.568852 rtcwake: wakeup from "freeze" using rtc0 at Sun Jun 4 22:20:40 2023
11567 22:20:21.581964 <6>[ 68.491827] PM: suspend entry (s2idle)
11568 22:20:21.585452 <6>[ 68.495945] Filesystems sync: 0.000 seconds
11569 22:20:21.591644 <6>[ 68.500996] Freezing user space processes
11570 22:20:21.598270 <6>[ 68.506925] Freezing user space processes completed (elapsed 0.001 seconds)
11571 22:20:21.601451 <6>[ 68.514150] OOM killer disabled.
11572 22:20:21.608421 <6>[ 68.517632] Freezing remaining freezable tasks
11573 22:20:21.614822 <6>[ 68.523631] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11574 22:20:21.624705 <6>[ 68.531291] printk: Suspending console(s) (use no_console_suspend to debug)
11575 22:20:25.077816 <3>[ 71.754596] mt7921e 0000:01:00.0: Message 00020007 (seq 4) timeout
11576 22:20:25.088235 <3>[ 71.754621] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11577 22:20:25.097968 <3>[ 71.754653] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11578 22:20:25.104549 <3>[ 71.754675] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11579 22:20:25.111076 <3>[ 71.755108] PM: Some devices failed to suspend, or early wake event detected
11580 22:20:25.117991 <6>[ 72.028234] OOM killer enabled.
11581 22:20:25.120877 <6>[ 72.031634] Restarting tasks ... done.
11582 22:20:25.127170 <5>[ 72.037236] random: crng reseeded on system resumption
11583 22:20:25.130639 <6>[ 72.043917] PM: suspend exit
11584 22:20:25.134032 rtcwake: write error
11585 22:20:25.141637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-4 RESULT=fail>
11586 22:20:25.142006 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-4 RESULT=fail
11588 22:20:25.144625 rtcwake: assuming RTC uses UTC ...
11589 22:20:25.150933 rtcwake: wakeup from "freeze" using rtc0 at Sun Jun 4 22:20:43 2023
11590 22:20:25.164293 <6>[ 72.074599] PM: suspend entry (s2idle)
11591 22:20:25.167543 <6>[ 72.078674] Filesystems sync: 0.000 seconds
11592 22:20:25.170475 <6>[ 72.083699] Freezing user space processes
11593 22:20:25.182506 <6>[ 72.089717] Freezing user space processes completed (elapsed 0.001 seconds)
11594 22:20:25.185683 <6>[ 72.097032] OOM killer disabled.
11595 22:20:25.188906 <6>[ 72.100521] Freezing remaining freezable tasks
11596 22:20:25.198746 <6>[ 72.106357] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11597 22:20:25.205434 <6>[ 72.114012] printk: Suspending console(s) (use no_console_suspend to debug)
11598 22:20:28.661747 <3>[ 75.338616] mt7921e 0000:01:00.0: Message 00020007 (seq 5) timeout
11599 22:20:28.671666 <3>[ 75.338644] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11600 22:20:28.681339 <3>[ 75.338681] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11601 22:20:28.688057 <3>[ 75.338701] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11602 22:20:28.694643 <3>[ 75.339079] PM: Some devices failed to suspend, or early wake event detected
11603 22:20:28.701508 <6>[ 75.612399] OOM killer enabled.
11604 22:20:28.705232 <6>[ 75.615802] Restarting tasks ... done.
11605 22:20:28.711488 <5>[ 75.621974] random: crng reseeded on system resumption
11606 22:20:28.714703 <6>[ 75.628443] PM: suspend exit
11607 22:20:28.718078 rtcwake: write error
11608 22:20:28.725228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-5 RESULT=fail>
11609 22:20:28.725529 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-5 RESULT=fail
11611 22:20:28.728825 rtcwake: assuming RTC uses UTC ...
11612 22:20:28.735338 rtcwake: wakeup from "freeze" using rtc0 at Sun Jun 4 22:20:47 2023
11613 22:20:28.747881 <6>[ 75.659078] PM: suspend entry (s2idle)
11614 22:20:28.751890 <6>[ 75.663161] Filesystems sync: 0.000 seconds
11615 22:20:28.757731 <6>[ 75.668298] Freezing user space processes
11616 22:20:28.764482 <6>[ 75.674365] Freezing user space processes completed (elapsed 0.001 seconds)
11617 22:20:28.767941 <6>[ 75.681596] OOM killer disabled.
11618 22:20:28.774334 <6>[ 75.685079] Freezing remaining freezable tasks
11619 22:20:28.781254 <6>[ 75.690996] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11620 22:20:28.791119 <6>[ 75.698650] printk: Suspending console(s) (use no_console_suspend to debug)
11621 22:20:32.246060 <3>[ 78.922606] mt7921e 0000:01:00.0: Message 00020007 (seq 6) timeout
11622 22:20:32.256030 <3>[ 78.922630] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11623 22:20:32.265658 <3>[ 78.922664] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11624 22:20:32.272357 <3>[ 78.922686] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11625 22:20:32.278463 <3>[ 78.923122] PM: Some devices failed to suspend, or early wake event detected
11626 22:20:32.285539 <6>[ 79.196377] OOM killer enabled.
11627 22:20:32.288738 <6>[ 79.199778] Restarting tasks ... done.
11628 22:20:32.294876 <5>[ 79.205966] random: crng reseeded on system resumption
11629 22:20:32.298520 <6>[ 79.213058] PM: suspend exit
11630 22:20:32.302367 rtcwake: write error
11631 22:20:32.310371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-6 RESULT=fail>
11632 22:20:32.311146 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-6 RESULT=fail
11634 22:20:32.313671 rtcwake: assuming RTC uses UTC ...
11635 22:20:32.320348 rtcwake: wakeup from "freeze" using rtc0 at Sun Jun 4 22:20:51 2023
11636 22:20:32.332980 <6>[ 79.243915] PM: suspend entry (s2idle)
11637 22:20:32.336055 <6>[ 79.248001] Filesystems sync: 0.000 seconds
11638 22:20:32.342935 <6>[ 79.253174] Freezing user space processes
11639 22:20:32.349516 <6>[ 79.259054] Freezing user space processes completed (elapsed 0.001 seconds)
11640 22:20:32.352933 <6>[ 79.266278] OOM killer disabled.
11641 22:20:32.359777 <6>[ 79.269762] Freezing remaining freezable tasks
11642 22:20:32.365676 <6>[ 79.275835] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11643 22:20:32.375691 <6>[ 79.283530] printk: Suspending console(s) (use no_console_suspend to debug)
11644 22:20:36.289298 <3>[ 82.506595] mt7921e 0000:01:00.0: Message 00020007 (seq 7) timeout
11645 22:20:36.289929 <3>[ 82.506620] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11646 22:20:36.290383 <3>[ 82.506653] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11647 22:20:36.290756 <3>[ 82.506674] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11648 22:20:36.291091 <3>[ 82.507084] PM: Some devices failed to suspend, or early wake event detected
11649 22:20:36.291413 <6>[ 82.780238] OOM killer enabled.
11650 22:20:36.291724 <6>[ 82.783637] Restarting tasks ... done.
11651 22:20:36.292078 <5>[ 82.789305] random: crng reseeded on system resumption
11652 22:20:36.292396 <6>[ 82.795709] PM: suspend exit
11653 22:20:36.292699 rtcwake: write error
11654 22:20:36.293000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-7 RESULT=fail>
11655 22:20:36.293302 rtcwake: assuming RTC uses UTC ...
11656 22:20:36.293600 rtcwake: wakeup from "freeze" using rtc0 at Sun Jun 4 22:20:54 2023
11657 22:20:36.293902 <6>[ 82.826592] PM: suspend entry (s2idle)
11658 22:20:36.294193 <6>[ 82.830670] Filesystems sync: 0.000 seconds
11659 22:20:36.294302 <6>[ 82.835903] Freezing user space processes
11660 22:20:36.294368 <6>[ 82.842015] Freezing user space processes completed (elapsed 0.001 seconds)
11661 22:20:36.294419 <6>[ 82.849346] OOM killer disabled.
11662 22:20:36.294470 <6>[ 82.852846] Freezing remaining freezable tasks
11663 22:20:36.294522 <6>[ 82.858376] Freezing remaining freezable tasks completed (elapsed 0.000 seconds)
11664 22:20:36.294574 <6>[ 82.866032] printk: Suspending console(s) (use no_console_suspend to debug)
11665 22:20:36.294805 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-7 RESULT=fail
11667 22:20:39.412781 <3>[ 86.090592] mt7921e 0000:01:00.0: Message 00020007 (seq 8) timeout
11668 22:20:39.422671 <3>[ 86.090617] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11669 22:20:39.432346 <3>[ 86.090649] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11670 22:20:39.439185 <3>[ 86.090670] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11671 22:20:39.445827 <3>[ 86.091100] PM: Some devices failed to suspend, or early wake event detected
11672 22:20:39.448938 <6>[ 86.364357] OOM killer enabled.
11673 22:20:39.458389 <6>[ 86.367758] Restarting tasks ... done.
11674 22:20:39.461644 <5>[ 86.374034] random: crng reseeded on system resumption
11675 22:20:39.465379 <6>[ 86.380952] PM: suspend exit
11676 22:20:39.469219 rtcwake: write error
11677 22:20:39.476828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-8 RESULT=fail>
11678 22:20:39.477523 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-8 RESULT=fail
11680 22:20:39.480135 rtcwake: assuming RTC uses UTC ...
11681 22:20:39.486713 rtcwake: wakeup from "freeze" using rtc0 at Sun Jun 4 22:20:58 2023
11682 22:20:39.499660 <6>[ 86.411738] PM: suspend entry (s2idle)
11683 22:20:39.503309 <6>[ 86.415792] Filesystems sync: 0.000 seconds
11684 22:20:39.509413 <6>[ 86.420919] Freezing user space processes
11685 22:20:39.516280 <6>[ 86.426934] Freezing user space processes completed (elapsed 0.001 seconds)
11686 22:20:39.519294 <6>[ 86.434158] OOM killer disabled.
11687 22:20:39.526370 <6>[ 86.437640] Freezing remaining freezable tasks
11688 22:20:39.532536 <6>[ 86.443565] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11689 22:20:39.542181 <6>[ 86.451225] printk: Suspending console(s) (use no_console_suspend to debug)
11690 22:20:43.249454 <3>[ 89.674642] mt7921e 0000:01:00.0: Message 00020007 (seq 9) timeout
11691 22:20:43.250025 <3>[ 89.674670] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11692 22:20:43.250402 <3>[ 89.674709] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11693 22:20:43.250749 <3>[ 89.674737] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11694 22:20:43.251080 <3>[ 89.675038] PM: Some devices failed to suspend, or early wake event detected
11695 22:20:43.251402 <6>[ 89.940371] OOM killer enabled.
11696 22:20:43.251714 <6>[ 89.943773] Restarting tasks ... done.
11697 22:20:43.252070 <5>[ 89.949817] random: crng reseeded on system resumption
11698 22:20:43.252388 <6>[ 89.956270] PM: suspend exit
11699 22:20:43.252693 rtcwake: write error
11700 22:20:43.253017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-9 RESULT=fail>
11701 22:20:43.253319 rtcwake: assuming RTC uses UTC ...
11702 22:20:43.253617 rtcwake: wakeup from "freeze" using rtc0 at Sun Jun 4 22:21:01 2023
11703 22:20:43.253919 <6>[ 89.986795] PM: suspend entry (s2idle)
11704 22:20:43.254324 <6>[ 89.990871] Filesystems sync: 0.000 seconds
11705 22:20:43.254638 <6>[ 89.995996] Freezing user space processes
11706 22:20:43.254940 <6>[ 90.001883] Freezing user space processes completed (elapsed 0.001 seconds)
11707 22:20:43.255242 <6>[ 90.009111] OOM killer disabled.
11708 22:20:43.255603 <6>[ 90.012591] Freezing remaining freezable tasks
11709 22:20:43.255906 <6>[ 90.018367] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11710 22:20:43.256253 <6>[ 90.026021] printk: Suspending console(s) (use no_console_suspend to debug)
11711 22:20:43.256799 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-9 RESULT=fail
11713 22:20:46.570778 <3>[ 93.258598] mt7921e 0000:01:00.0: Message 00020007 (seq 10) timeout
11714 22:20:46.581313 <3>[ 93.258623] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11715 22:20:46.590850 <3>[ 93.258655] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11716 22:20:46.597311 <3>[ 93.258676] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11717 22:20:46.607622 <3>[ 93.259106] PM: Some devices failed to suspend, or early wake event detected
11718 22:20:46.610584 <6>[ 93.524274] OOM killer enabled.
11719 22:20:46.614630 <6>[ 93.527672] Restarting tasks ... done.
11720 22:20:46.620528 <5>[ 93.533417] random: crng reseeded on system resumption
11721 22:20:46.624413 <6>[ 93.539900] PM: suspend exit
11722 22:20:46.626988 rtcwake: write error
11723 22:20:46.634577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-10 RESULT=fail>
11724 22:20:46.634857 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-10 RESULT=fail
11726 22:20:46.637972 + set +x
11727 22:20:46.641245 <LAVA_SIGNAL_ENDRUN 0_sleep 10583915_1.5.2.3.1>
11728 22:20:46.641318 <LAVA_TEST_RUNNER EXIT>
11729 22:20:46.641598 Received signal: <ENDRUN> 0_sleep 10583915_1.5.2.3.1
11730 22:20:46.641687 Ending use of test pattern.
11731 22:20:46.641751 Ending test lava.0_sleep (10583915_1.5.2.3.1), duration 71.61
11733 22:20:46.642283 ok: lava_test_shell seems to have completed
11734 22:20:46.642644 rtc-exist: pass
rtc-wakeup-enabled: pass
rtcwake-freeze-1: fail
rtcwake-freeze-10: fail
rtcwake-freeze-2: fail
rtcwake-freeze-3: fail
rtcwake-freeze-4: fail
rtcwake-freeze-5: fail
rtcwake-freeze-6: fail
rtcwake-freeze-7: fail
rtcwake-freeze-8: fail
rtcwake-freeze-9: fail
rtcwake-mem-1: fail
rtcwake-mem-10: fail
rtcwake-mem-2: fail
rtcwake-mem-3: fail
rtcwake-mem-4: fail
rtcwake-mem-5: fail
rtcwake-mem-6: fail
rtcwake-mem-7: fail
rtcwake-mem-8: fail
rtcwake-mem-9: fail
11735 22:20:46.642780 end: 3.1 lava-test-shell (duration 00:01:12) [common]
11736 22:20:46.642895 end: 3 lava-test-retry (duration 00:01:12) [common]
11737 22:20:46.643011 start: 4 finalize (timeout 00:05:03) [common]
11738 22:20:46.643139 start: 4.1 power-off (timeout 00:00:30) [common]
11739 22:20:46.643425 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=off'
11740 22:20:46.718351 >> Command sent successfully.
11741 22:20:46.720791 Returned 0 in 0 seconds
11742 22:20:46.821184 end: 4.1 power-off (duration 00:00:00) [common]
11744 22:20:46.821504 start: 4.2 read-feedback (timeout 00:05:03) [common]
11745 22:20:46.821762 Listened to connection for namespace 'common' for up to 1s
11746 22:20:46.822045 Listened to connection for namespace 'common' for up to 1s
11747 22:20:47.822717 Finalising connection for namespace 'common'
11748 22:20:47.822895 Disconnecting from shell: Finalise
11749 22:20:47.822981 / #
11750 22:20:47.923301 end: 4.2 read-feedback (duration 00:00:01) [common]
11751 22:20:47.923461 end: 4 finalize (duration 00:00:01) [common]
11752 22:20:47.923582 Cleaning after the job
11753 22:20:47.923686 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10583915/tftp-deploy-z4tjqdiw/ramdisk
11754 22:20:47.933868 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10583915/tftp-deploy-z4tjqdiw/kernel
11755 22:20:47.950657 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10583915/tftp-deploy-z4tjqdiw/dtb
11756 22:20:47.950865 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10583915/tftp-deploy-z4tjqdiw/modules
11757 22:20:47.956069 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10583915
11758 22:20:48.093219 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10583915
11759 22:20:48.093395 Job finished correctly