Boot log: mt8192-asurada-spherion-r0
- Errors: 1
- Kernel Errors: 34
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 70
1 22:11:47.986515 lava-dispatcher, installed at version: 2023.03
2 22:11:47.986710 start: 0 validate
3 22:11:47.986837 Start time: 2023-06-04 22:11:47.986830+00:00 (UTC)
4 22:11:47.986951 Using caching service: 'http://localhost/cache/?uri=%s'
5 22:11:47.987077 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-v4l2%2F20230527.0%2Farm64%2Frootfs.cpio.gz exists
6 22:11:48.275627 Using caching service: 'http://localhost/cache/?uri=%s'
7 22:11:48.276425 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1281-g84d5372e0f314%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 22:11:48.567354 Using caching service: 'http://localhost/cache/?uri=%s'
9 22:11:48.568156 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1281-g84d5372e0f314%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 22:12:16.612073 Using caching service: 'http://localhost/cache/?uri=%s'
11 22:12:16.612822 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1281-g84d5372e0f314%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 22:12:17.185429 validate duration: 29.20
14 22:12:17.185689 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 22:12:17.185784 start: 1.1 download-retry (timeout 00:10:00) [common]
16 22:12:17.185873 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 22:12:17.185991 Not decompressing ramdisk as can be used compressed.
18 22:12:17.186079 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-v4l2/20230527.0/arm64/rootfs.cpio.gz
19 22:12:17.186150 saving as /var/lib/lava/dispatcher/tmp/10583875/tftp-deploy-v0ttru9s/ramdisk/rootfs.cpio.gz
20 22:12:17.186213 total size: 27151647 (25MB)
21 22:12:20.913295 progress 0% (0MB)
22 22:12:20.923721 progress 5% (1MB)
23 22:12:20.930327 progress 10% (2MB)
24 22:12:20.937301 progress 15% (3MB)
25 22:12:20.943997 progress 20% (5MB)
26 22:12:20.950893 progress 25% (6MB)
27 22:12:20.957651 progress 30% (7MB)
28 22:12:20.964671 progress 35% (9MB)
29 22:12:20.971481 progress 40% (10MB)
30 22:12:20.978148 progress 45% (11MB)
31 22:12:20.985024 progress 50% (12MB)
32 22:12:20.991814 progress 55% (14MB)
33 22:12:20.998752 progress 60% (15MB)
34 22:12:21.005338 progress 65% (16MB)
35 22:12:21.012088 progress 70% (18MB)
36 22:12:21.018689 progress 75% (19MB)
37 22:12:21.025309 progress 80% (20MB)
38 22:12:21.032061 progress 85% (22MB)
39 22:12:21.038762 progress 90% (23MB)
40 22:12:21.045447 progress 95% (24MB)
41 22:12:21.052046 progress 100% (25MB)
42 22:12:21.052230 25MB downloaded in 3.87s (6.70MB/s)
43 22:12:21.052387 end: 1.1.1 http-download (duration 00:00:04) [common]
45 22:12:21.052641 end: 1.1 download-retry (duration 00:00:04) [common]
46 22:12:21.052743 start: 1.2 download-retry (timeout 00:09:56) [common]
47 22:12:21.052828 start: 1.2.1 http-download (timeout 00:09:56) [common]
48 22:12:21.052960 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1281-g84d5372e0f314/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 22:12:21.053032 saving as /var/lib/lava/dispatcher/tmp/10583875/tftp-deploy-v0ttru9s/kernel/Image
50 22:12:21.053093 total size: 45746688 (43MB)
51 22:12:21.053153 No compression specified
52 22:12:21.341141 progress 0% (0MB)
53 22:12:21.388404 progress 5% (2MB)
54 22:12:21.405835 progress 10% (4MB)
55 22:12:21.418322 progress 15% (6MB)
56 22:12:21.429496 progress 20% (8MB)
57 22:12:21.440711 progress 25% (10MB)
58 22:12:21.451709 progress 30% (13MB)
59 22:12:21.462871 progress 35% (15MB)
60 22:12:21.474242 progress 40% (17MB)
61 22:12:21.485788 progress 45% (19MB)
62 22:12:21.497401 progress 50% (21MB)
63 22:12:21.508724 progress 55% (24MB)
64 22:12:21.519974 progress 60% (26MB)
65 22:12:21.531158 progress 65% (28MB)
66 22:12:21.542371 progress 70% (30MB)
67 22:12:21.553537 progress 75% (32MB)
68 22:12:21.564583 progress 80% (34MB)
69 22:12:21.575969 progress 85% (37MB)
70 22:12:21.587369 progress 90% (39MB)
71 22:12:21.598914 progress 95% (41MB)
72 22:12:21.610119 progress 100% (43MB)
73 22:12:21.610239 43MB downloaded in 0.56s (78.31MB/s)
74 22:12:21.610424 end: 1.2.1 http-download (duration 00:00:01) [common]
76 22:12:21.610653 end: 1.2 download-retry (duration 00:00:01) [common]
77 22:12:21.610740 start: 1.3 download-retry (timeout 00:09:56) [common]
78 22:12:21.610830 start: 1.3.1 http-download (timeout 00:09:56) [common]
79 22:12:21.610968 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1281-g84d5372e0f314/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 22:12:21.611041 saving as /var/lib/lava/dispatcher/tmp/10583875/tftp-deploy-v0ttru9s/dtb/mt8192-asurada-spherion-r0.dtb
81 22:12:21.611104 total size: 46924 (0MB)
82 22:12:21.611164 No compression specified
83 22:12:21.612368 progress 69% (0MB)
84 22:12:21.612640 progress 100% (0MB)
85 22:12:21.612791 0MB downloaded in 0.00s (26.56MB/s)
86 22:12:21.612912 end: 1.3.1 http-download (duration 00:00:00) [common]
88 22:12:21.613126 end: 1.3 download-retry (duration 00:00:00) [common]
89 22:12:21.613208 start: 1.4 download-retry (timeout 00:09:56) [common]
90 22:12:21.613288 start: 1.4.1 http-download (timeout 00:09:56) [common]
91 22:12:21.613394 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1281-g84d5372e0f314/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 22:12:21.613460 saving as /var/lib/lava/dispatcher/tmp/10583875/tftp-deploy-v0ttru9s/modules/modules.tar
93 22:12:21.613519 total size: 8541948 (8MB)
94 22:12:21.613577 Using unxz to decompress xz
95 22:12:21.617199 progress 0% (0MB)
96 22:12:21.638520 progress 5% (0MB)
97 22:12:21.662873 progress 10% (0MB)
98 22:12:21.687897 progress 15% (1MB)
99 22:12:21.712651 progress 20% (1MB)
100 22:12:21.735359 progress 25% (2MB)
101 22:12:21.760862 progress 30% (2MB)
102 22:12:21.784803 progress 35% (2MB)
103 22:12:21.808519 progress 40% (3MB)
104 22:12:21.831756 progress 45% (3MB)
105 22:12:21.855723 progress 50% (4MB)
106 22:12:21.878280 progress 55% (4MB)
107 22:12:21.902075 progress 60% (4MB)
108 22:12:21.926663 progress 65% (5MB)
109 22:12:21.950550 progress 70% (5MB)
110 22:12:21.973062 progress 75% (6MB)
111 22:12:21.996421 progress 80% (6MB)
112 22:12:22.020415 progress 85% (6MB)
113 22:12:22.048571 progress 90% (7MB)
114 22:12:22.073065 progress 95% (7MB)
115 22:12:22.096722 progress 100% (8MB)
116 22:12:22.102472 8MB downloaded in 0.49s (16.66MB/s)
117 22:12:22.102774 end: 1.4.1 http-download (duration 00:00:00) [common]
119 22:12:22.103035 end: 1.4 download-retry (duration 00:00:00) [common]
120 22:12:22.103129 start: 1.5 prepare-tftp-overlay (timeout 00:09:55) [common]
121 22:12:22.103224 start: 1.5.1 extract-nfsrootfs (timeout 00:09:55) [common]
122 22:12:22.103308 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 22:12:22.103396 start: 1.5.2 lava-overlay (timeout 00:09:55) [common]
124 22:12:22.103614 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10583875/lava-overlay-x1n1uuwi
125 22:12:22.103740 makedir: /var/lib/lava/dispatcher/tmp/10583875/lava-overlay-x1n1uuwi/lava-10583875/bin
126 22:12:22.103846 makedir: /var/lib/lava/dispatcher/tmp/10583875/lava-overlay-x1n1uuwi/lava-10583875/tests
127 22:12:22.103941 makedir: /var/lib/lava/dispatcher/tmp/10583875/lava-overlay-x1n1uuwi/lava-10583875/results
128 22:12:22.104054 Creating /var/lib/lava/dispatcher/tmp/10583875/lava-overlay-x1n1uuwi/lava-10583875/bin/lava-add-keys
129 22:12:22.104194 Creating /var/lib/lava/dispatcher/tmp/10583875/lava-overlay-x1n1uuwi/lava-10583875/bin/lava-add-sources
130 22:12:22.104321 Creating /var/lib/lava/dispatcher/tmp/10583875/lava-overlay-x1n1uuwi/lava-10583875/bin/lava-background-process-start
131 22:12:22.104445 Creating /var/lib/lava/dispatcher/tmp/10583875/lava-overlay-x1n1uuwi/lava-10583875/bin/lava-background-process-stop
132 22:12:22.104568 Creating /var/lib/lava/dispatcher/tmp/10583875/lava-overlay-x1n1uuwi/lava-10583875/bin/lava-common-functions
133 22:12:22.104774 Creating /var/lib/lava/dispatcher/tmp/10583875/lava-overlay-x1n1uuwi/lava-10583875/bin/lava-echo-ipv4
134 22:12:22.104897 Creating /var/lib/lava/dispatcher/tmp/10583875/lava-overlay-x1n1uuwi/lava-10583875/bin/lava-install-packages
135 22:12:22.105016 Creating /var/lib/lava/dispatcher/tmp/10583875/lava-overlay-x1n1uuwi/lava-10583875/bin/lava-installed-packages
136 22:12:22.105133 Creating /var/lib/lava/dispatcher/tmp/10583875/lava-overlay-x1n1uuwi/lava-10583875/bin/lava-os-build
137 22:12:22.105252 Creating /var/lib/lava/dispatcher/tmp/10583875/lava-overlay-x1n1uuwi/lava-10583875/bin/lava-probe-channel
138 22:12:22.105372 Creating /var/lib/lava/dispatcher/tmp/10583875/lava-overlay-x1n1uuwi/lava-10583875/bin/lava-probe-ip
139 22:12:22.105491 Creating /var/lib/lava/dispatcher/tmp/10583875/lava-overlay-x1n1uuwi/lava-10583875/bin/lava-target-ip
140 22:12:22.105611 Creating /var/lib/lava/dispatcher/tmp/10583875/lava-overlay-x1n1uuwi/lava-10583875/bin/lava-target-mac
141 22:12:22.105729 Creating /var/lib/lava/dispatcher/tmp/10583875/lava-overlay-x1n1uuwi/lava-10583875/bin/lava-target-storage
142 22:12:22.105852 Creating /var/lib/lava/dispatcher/tmp/10583875/lava-overlay-x1n1uuwi/lava-10583875/bin/lava-test-case
143 22:12:22.105972 Creating /var/lib/lava/dispatcher/tmp/10583875/lava-overlay-x1n1uuwi/lava-10583875/bin/lava-test-event
144 22:12:22.106089 Creating /var/lib/lava/dispatcher/tmp/10583875/lava-overlay-x1n1uuwi/lava-10583875/bin/lava-test-feedback
145 22:12:22.106208 Creating /var/lib/lava/dispatcher/tmp/10583875/lava-overlay-x1n1uuwi/lava-10583875/bin/lava-test-raise
146 22:12:22.106329 Creating /var/lib/lava/dispatcher/tmp/10583875/lava-overlay-x1n1uuwi/lava-10583875/bin/lava-test-reference
147 22:12:22.106489 Creating /var/lib/lava/dispatcher/tmp/10583875/lava-overlay-x1n1uuwi/lava-10583875/bin/lava-test-runner
148 22:12:22.106607 Creating /var/lib/lava/dispatcher/tmp/10583875/lava-overlay-x1n1uuwi/lava-10583875/bin/lava-test-set
149 22:12:22.106729 Creating /var/lib/lava/dispatcher/tmp/10583875/lava-overlay-x1n1uuwi/lava-10583875/bin/lava-test-shell
150 22:12:22.106851 Updating /var/lib/lava/dispatcher/tmp/10583875/lava-overlay-x1n1uuwi/lava-10583875/bin/lava-install-packages (oe)
151 22:12:22.107000 Updating /var/lib/lava/dispatcher/tmp/10583875/lava-overlay-x1n1uuwi/lava-10583875/bin/lava-installed-packages (oe)
152 22:12:22.107118 Creating /var/lib/lava/dispatcher/tmp/10583875/lava-overlay-x1n1uuwi/lava-10583875/environment
153 22:12:22.107215 LAVA metadata
154 22:12:22.107291 - LAVA_JOB_ID=10583875
155 22:12:22.107355 - LAVA_DISPATCHER_IP=192.168.201.1
156 22:12:22.107457 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:55) [common]
157 22:12:22.107528 skipped lava-vland-overlay
158 22:12:22.107603 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 22:12:22.107682 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:55) [common]
160 22:12:22.107745 skipped lava-multinode-overlay
161 22:12:22.107818 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 22:12:22.107902 start: 1.5.2.3 test-definition (timeout 00:09:55) [common]
163 22:12:22.107977 Loading test definitions
164 22:12:22.108069 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:55) [common]
165 22:12:22.108143 Using /lava-10583875 at stage 0
166 22:12:22.108423 uuid=10583875_1.5.2.3.1 testdef=None
167 22:12:22.108510 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 22:12:22.108595 start: 1.5.2.3.2 test-overlay (timeout 00:09:55) [common]
169 22:12:22.109091 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 22:12:22.109308 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:55) [common]
172 22:12:22.109885 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 22:12:22.110112 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:55) [common]
175 22:12:22.111052 runner path: /var/lib/lava/dispatcher/tmp/10583875/lava-overlay-x1n1uuwi/lava-10583875/0/tests/0_v4l2-compliance-mtk-vcodec-enc test_uuid 10583875_1.5.2.3.1
176 22:12:22.111203 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 22:12:22.111407 Creating lava-test-runner.conf files
179 22:12:22.111470 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10583875/lava-overlay-x1n1uuwi/lava-10583875/0 for stage 0
180 22:12:22.111557 - 0_v4l2-compliance-mtk-vcodec-enc
181 22:12:22.111657 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 22:12:22.111743 start: 1.5.2.4 compress-overlay (timeout 00:09:55) [common]
183 22:12:22.118143 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 22:12:22.118246 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:55) [common]
185 22:12:22.118335 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 22:12:22.118455 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 22:12:22.118542 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:55) [common]
188 22:12:22.793872 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 22:12:22.794228 start: 1.5.4 extract-modules (timeout 00:09:54) [common]
190 22:12:22.794359 extracting modules file /var/lib/lava/dispatcher/tmp/10583875/tftp-deploy-v0ttru9s/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10583875/extract-overlay-ramdisk-zz4aaclv/ramdisk
191 22:12:22.997679 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 22:12:22.997850 start: 1.5.5 apply-overlay-tftp (timeout 00:09:54) [common]
193 22:12:22.997942 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10583875/compress-overlay-lr7f7wst/overlay-1.5.2.4.tar.gz to ramdisk
194 22:12:22.998014 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10583875/compress-overlay-lr7f7wst/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10583875/extract-overlay-ramdisk-zz4aaclv/ramdisk
195 22:12:23.004519 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 22:12:23.004630 start: 1.5.6 configure-preseed-file (timeout 00:09:54) [common]
197 22:12:23.004721 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 22:12:23.004810 start: 1.5.7 compress-ramdisk (timeout 00:09:54) [common]
199 22:12:23.004922 Building ramdisk /var/lib/lava/dispatcher/tmp/10583875/extract-overlay-ramdisk-zz4aaclv/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10583875/extract-overlay-ramdisk-zz4aaclv/ramdisk
200 22:12:23.555112 >> 230334 blocks
201 22:12:27.417394 rename /var/lib/lava/dispatcher/tmp/10583875/extract-overlay-ramdisk-zz4aaclv/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10583875/tftp-deploy-v0ttru9s/ramdisk/ramdisk.cpio.gz
202 22:12:27.417799 end: 1.5.7 compress-ramdisk (duration 00:00:04) [common]
203 22:12:27.417924 start: 1.5.8 prepare-kernel (timeout 00:09:50) [common]
204 22:12:27.418023 start: 1.5.8.1 prepare-fit (timeout 00:09:50) [common]
205 22:12:27.418128 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10583875/tftp-deploy-v0ttru9s/kernel/Image'
206 22:12:38.548579 Returned 0 in 11 seconds
207 22:12:38.649651 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10583875/tftp-deploy-v0ttru9s/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10583875/tftp-deploy-v0ttru9s/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10583875/tftp-deploy-v0ttru9s/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10583875/tftp-deploy-v0ttru9s/kernel/image.itb
208 22:12:39.266855 output: FIT description: Kernel Image image with one or more FDT blobs
209 22:12:39.267202 output: Created: Sun Jun 4 23:12:39 2023
210 22:12:39.267278 output: Image 0 (kernel-1)
211 22:12:39.267343 output: Description:
212 22:12:39.267409 output: Created: Sun Jun 4 23:12:39 2023
213 22:12:39.267473 output: Type: Kernel Image
214 22:12:39.267534 output: Compression: lzma compressed
215 22:12:39.267597 output: Data Size: 10081729 Bytes = 9845.44 KiB = 9.61 MiB
216 22:12:39.267657 output: Architecture: AArch64
217 22:12:39.267718 output: OS: Linux
218 22:12:39.267778 output: Load Address: 0x00000000
219 22:12:39.267851 output: Entry Point: 0x00000000
220 22:12:39.267950 output: Hash algo: crc32
221 22:12:39.268005 output: Hash value: 3b3111d8
222 22:12:39.268059 output: Image 1 (fdt-1)
223 22:12:39.268112 output: Description: mt8192-asurada-spherion-r0
224 22:12:39.268166 output: Created: Sun Jun 4 23:12:39 2023
225 22:12:39.268220 output: Type: Flat Device Tree
226 22:12:39.268274 output: Compression: uncompressed
227 22:12:39.268327 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
228 22:12:39.268381 output: Architecture: AArch64
229 22:12:39.268434 output: Hash algo: crc32
230 22:12:39.268487 output: Hash value: 1df858fa
231 22:12:39.268541 output: Image 2 (ramdisk-1)
232 22:12:39.268594 output: Description: unavailable
233 22:12:39.268648 output: Created: Sun Jun 4 23:12:39 2023
234 22:12:39.268702 output: Type: RAMDisk Image
235 22:12:39.268755 output: Compression: Unknown Compression
236 22:12:39.268808 output: Data Size: 40135494 Bytes = 39194.82 KiB = 38.28 MiB
237 22:12:39.268861 output: Architecture: AArch64
238 22:12:39.268914 output: OS: Linux
239 22:12:39.268967 output: Load Address: unavailable
240 22:12:39.269021 output: Entry Point: unavailable
241 22:12:39.269074 output: Hash algo: crc32
242 22:12:39.269128 output: Hash value: c937e918
243 22:12:39.269181 output: Default Configuration: 'conf-1'
244 22:12:39.269234 output: Configuration 0 (conf-1)
245 22:12:39.269287 output: Description: mt8192-asurada-spherion-r0
246 22:12:39.269340 output: Kernel: kernel-1
247 22:12:39.269393 output: Init Ramdisk: ramdisk-1
248 22:12:39.269446 output: FDT: fdt-1
249 22:12:39.269499 output: Loadables: kernel-1
250 22:12:39.269552 output:
251 22:12:39.269741 end: 1.5.8.1 prepare-fit (duration 00:00:12) [common]
252 22:12:39.269854 end: 1.5.8 prepare-kernel (duration 00:00:12) [common]
253 22:12:39.270002 end: 1.5 prepare-tftp-overlay (duration 00:00:17) [common]
254 22:12:39.270091 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:38) [common]
255 22:12:39.270169 No LXC device requested
256 22:12:39.270247 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 22:12:39.270334 start: 1.7 deploy-device-env (timeout 00:09:38) [common]
258 22:12:39.270455 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 22:12:39.270524 Checking files for TFTP limit of 4294967296 bytes.
260 22:12:39.271015 end: 1 tftp-deploy (duration 00:00:22) [common]
261 22:12:39.271121 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 22:12:39.271210 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 22:12:39.271330 substitutions:
264 22:12:39.271397 - {DTB}: 10583875/tftp-deploy-v0ttru9s/dtb/mt8192-asurada-spherion-r0.dtb
265 22:12:39.271462 - {INITRD}: 10583875/tftp-deploy-v0ttru9s/ramdisk/ramdisk.cpio.gz
266 22:12:39.271523 - {KERNEL}: 10583875/tftp-deploy-v0ttru9s/kernel/Image
267 22:12:39.271581 - {LAVA_MAC}: None
268 22:12:39.271639 - {PRESEED_CONFIG}: None
269 22:12:39.271696 - {PRESEED_LOCAL}: None
270 22:12:39.271752 - {RAMDISK}: 10583875/tftp-deploy-v0ttru9s/ramdisk/ramdisk.cpio.gz
271 22:12:39.271808 - {ROOT_PART}: None
272 22:12:39.271900 - {ROOT}: None
273 22:12:39.271982 - {SERVER_IP}: 192.168.201.1
274 22:12:39.272037 - {TEE}: None
275 22:12:39.272093 Parsed boot commands:
276 22:12:39.272147 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 22:12:39.272317 Parsed boot commands: tftpboot 192.168.201.1 10583875/tftp-deploy-v0ttru9s/kernel/image.itb 10583875/tftp-deploy-v0ttru9s/kernel/cmdline
278 22:12:39.272406 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 22:12:39.272492 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 22:12:39.272583 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 22:12:39.272669 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 22:12:39.272740 Not connected, no need to disconnect.
283 22:12:39.272815 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 22:12:39.272895 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 22:12:39.272961 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-1'
286 22:12:39.276325 Setting prompt string to ['lava-test: # ']
287 22:12:39.276643 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 22:12:39.276749 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 22:12:39.276844 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 22:12:39.276933 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 22:12:39.277122 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=reboot'
292 22:12:44.422113 >> Command sent successfully.
293 22:12:44.428230 Returned 0 in 5 seconds
294 22:12:44.528919 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 22:12:44.532419 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 22:12:44.533070 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 22:12:44.533558 Setting prompt string to 'Starting depthcharge on Spherion...'
299 22:12:44.533960 Changing prompt to 'Starting depthcharge on Spherion...'
300 22:12:44.534458 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 22:12:44.535708 [Enter `^Ec?' for help]
302 22:12:44.699290
303 22:12:44.699883
304 22:12:44.700378 F0: 102B 0000
305 22:12:44.700840
306 22:12:44.701288 F3: 1001 0000 [0200]
307 22:12:44.701730
308 22:12:44.702482 F3: 1001 0000
309 22:12:44.702860
310 22:12:44.703312 F7: 102D 0000
311 22:12:44.703862
312 22:12:44.706470 F1: 0000 0000
313 22:12:44.707073
314 22:12:44.707569 V0: 0000 0000 [0001]
315 22:12:44.708032
316 22:12:44.709272 00: 0007 8000
317 22:12:44.709806
318 22:12:44.710293 01: 0000 0000
319 22:12:44.710794
320 22:12:44.712643 BP: 0C00 0209 [0000]
321 22:12:44.713233
322 22:12:44.713723 G0: 1182 0000
323 22:12:44.714179
324 22:12:44.716126 EC: 0000 0021 [4000]
325 22:12:44.716616
326 22:12:44.717104 S7: 0000 0000 [0000]
327 22:12:44.717522
328 22:12:44.719223 CC: 0000 0000 [0001]
329 22:12:44.719768
330 22:12:44.720213 T0: 0000 0040 [010F]
331 22:12:44.720739
332 22:12:44.722425 Jump to BL
333 22:12:44.722852
334 22:12:44.746427
335 22:12:44.747028
336 22:12:44.747374
337 22:12:44.753877 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 22:12:44.757404 ARM64: Exception handlers installed.
339 22:12:44.761173 ARM64: Testing exception
340 22:12:44.765417 ARM64: Done test exception
341 22:12:44.771324 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 22:12:44.781345 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 22:12:44.788958 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 22:12:44.798249 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 22:12:44.805254 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 22:12:44.811361 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 22:12:44.823661 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 22:12:44.830184 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 22:12:44.849383 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 22:12:44.852874 WDT: Last reset was cold boot
351 22:12:44.856621 SPI1(PAD0) initialized at 2873684 Hz
352 22:12:44.859187 SPI5(PAD0) initialized at 992727 Hz
353 22:12:44.862950 VBOOT: Loading verstage.
354 22:12:44.869524 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 22:12:44.872554 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 22:12:44.875856 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 22:12:44.879305 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 22:12:44.887118 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 22:12:44.893454 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 22:12:44.904499 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
361 22:12:44.905072
362 22:12:44.905457
363 22:12:44.914410 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 22:12:44.917851 ARM64: Exception handlers installed.
365 22:12:44.920904 ARM64: Testing exception
366 22:12:44.921490 ARM64: Done test exception
367 22:12:44.927544 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 22:12:44.930681 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 22:12:44.945016 Probing TPM: . done!
370 22:12:44.945584 TPM ready after 0 ms
371 22:12:44.952339 Connected to device vid:did:rid of 1ae0:0028:00
372 22:12:44.958989 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
373 22:12:44.962638 Initialized TPM device CR50 revision 0
374 22:12:45.027851 tlcl_send_startup: Startup return code is 0
375 22:12:45.028419 TPM: setup succeeded
376 22:12:45.039833 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 22:12:45.048116 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 22:12:45.058641 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 22:12:45.067704 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 22:12:45.070945 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 22:12:45.078457 in-header: 03 07 00 00 08 00 00 00
382 22:12:45.081724 in-data: aa e4 47 04 13 02 00 00
383 22:12:45.085606 Chrome EC: UHEPI supported
384 22:12:45.092947 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 22:12:45.096193 in-header: 03 ad 00 00 08 00 00 00
386 22:12:45.099965 in-data: 00 20 20 08 00 00 00 00
387 22:12:45.100607 Phase 1
388 22:12:45.103744 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 22:12:45.111175 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 22:12:45.114987 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 22:12:45.118698 Recovery requested (1009000e)
392 22:12:45.128549 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 22:12:45.133084 tlcl_extend: response is 0
394 22:12:45.142736 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 22:12:45.148618 tlcl_extend: response is 0
396 22:12:45.156281 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 22:12:45.176666 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
398 22:12:45.183074 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 22:12:45.183589
400 22:12:45.183926
401 22:12:45.193459 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 22:12:45.196991 ARM64: Exception handlers installed.
403 22:12:45.197521 ARM64: Testing exception
404 22:12:45.200506 ARM64: Done test exception
405 22:12:45.221740 pmic_efuse_setting: Set efuses in 11 msecs
406 22:12:45.224548 pmwrap_interface_init: Select PMIF_VLD_RDY
407 22:12:45.231104 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 22:12:45.235314 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 22:12:45.241699 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 22:12:45.245070 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 22:12:45.248473 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 22:12:45.255969 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 22:12:45.259118 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 22:12:45.263125 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 22:12:45.270228 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 22:12:45.274461 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 22:12:45.277543 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 22:12:45.284773 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 22:12:45.287854 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 22:12:45.294488 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 22:12:45.298204 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 22:12:45.305163 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 22:12:45.312031 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 22:12:45.315557 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 22:12:45.322783 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 22:12:45.329830 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 22:12:45.333703 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 22:12:45.339073 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 22:12:45.346065 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 22:12:45.349274 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 22:12:45.356126 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 22:12:45.359178 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 22:12:45.365856 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 22:12:45.369768 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 22:12:45.376052 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 22:12:45.379261 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 22:12:45.386106 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 22:12:45.389328 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 22:12:45.396265 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 22:12:45.399680 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 22:12:45.406161 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 22:12:45.409599 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 22:12:45.415580 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 22:12:45.418940 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 22:12:45.426300 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 22:12:45.430170 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 22:12:45.434224 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 22:12:45.436847 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 22:12:45.443818 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 22:12:45.447130 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 22:12:45.450738 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 22:12:45.456934 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 22:12:45.460315 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 22:12:45.463779 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 22:12:45.467263 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 22:12:45.473636 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 22:12:45.477008 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 22:12:45.483336 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 22:12:45.493213 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 22:12:45.496945 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 22:12:45.507522 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 22:12:45.513098 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 22:12:45.519957 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 22:12:45.523458 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 22:12:45.526275 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 22:12:45.534232 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x30
467 22:12:45.541045 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 22:12:45.544210 [RTC]rtc_osc_init,62: osc32con val = 0xde70
469 22:12:45.547523 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 22:12:45.558911 [RTC]rtc_get_frequency_meter,154: input=15, output=771
471 22:12:45.568774 [RTC]rtc_get_frequency_meter,154: input=23, output=959
472 22:12:45.577527 [RTC]rtc_get_frequency_meter,154: input=19, output=865
473 22:12:45.587054 [RTC]rtc_get_frequency_meter,154: input=17, output=818
474 22:12:45.596617 [RTC]rtc_get_frequency_meter,154: input=16, output=797
475 22:12:45.606333 [RTC]rtc_get_frequency_meter,154: input=15, output=772
476 22:12:45.615906 [RTC]rtc_get_frequency_meter,154: input=16, output=794
477 22:12:45.620304 [RTC]rtc_eosc_cali,47: left: 15, middle: 15, right: 16
478 22:12:45.626210 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
479 22:12:45.629679 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 22:12:45.632660 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
481 22:12:45.639888 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 22:12:45.642896 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
483 22:12:45.646124 ADC[4]: Raw value=902139 ID=7
484 22:12:45.646649 ADC[3]: Raw value=213179 ID=1
485 22:12:45.649549 RAM Code: 0x71
486 22:12:45.653427 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 22:12:45.659602 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 22:12:45.666523 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 22:12:45.673099 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 22:12:45.676213 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 22:12:45.679373 in-header: 03 07 00 00 08 00 00 00
492 22:12:45.682824 in-data: aa e4 47 04 13 02 00 00
493 22:12:45.685841 Chrome EC: UHEPI supported
494 22:12:45.692511 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 22:12:45.696135 in-header: 03 ed 00 00 08 00 00 00
496 22:12:45.699684 in-data: 80 20 60 08 00 00 00 00
497 22:12:45.702538 MRC: failed to locate region type 0.
498 22:12:45.709240 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 22:12:45.712484 DRAM-K: Running full calibration
500 22:12:45.719247 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 22:12:45.719784 header.status = 0x0
502 22:12:45.722559 header.version = 0x6 (expected: 0x6)
503 22:12:45.726246 header.size = 0xd00 (expected: 0xd00)
504 22:12:45.729427 header.flags = 0x0
505 22:12:45.735793 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 22:12:45.752923 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
507 22:12:45.760601 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 22:12:45.764652 dram_init: ddr_geometry: 2
509 22:12:45.765237 [EMI] MDL number = 2
510 22:12:45.767936 [EMI] Get MDL freq = 0
511 22:12:45.768524 dram_init: ddr_type: 0
512 22:12:45.772116 is_discrete_lpddr4: 1
513 22:12:45.775609 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 22:12:45.776198
515 22:12:45.776589
516 22:12:45.776940 [Bian_co] ETT version 0.0.0.1
517 22:12:45.782846 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 22:12:45.783326
519 22:12:45.786825 dramc_set_vcore_voltage set vcore to 650000
520 22:12:45.787411 Read voltage for 800, 4
521 22:12:45.790821 Vio18 = 0
522 22:12:45.791299 Vcore = 650000
523 22:12:45.791681 Vdram = 0
524 22:12:45.792034 Vddq = 0
525 22:12:45.793613 Vmddr = 0
526 22:12:45.794087 dram_init: config_dvfs: 1
527 22:12:45.800412 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 22:12:45.803648 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 22:12:45.810447 [SwImpedanceCal] DRVP=10, DRVN=17, ODTN=9
530 22:12:45.813991 freq_region=0, Reg: DRVP=10, DRVN=17, ODTN=9
531 22:12:45.817334 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
532 22:12:45.820899 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
533 22:12:45.825296 MEM_TYPE=3, freq_sel=18
534 22:12:45.827605 sv_algorithm_assistance_LP4_1600
535 22:12:45.830710 ============ PULL DRAM RESETB DOWN ============
536 22:12:45.833611 ========== PULL DRAM RESETB DOWN end =========
537 22:12:45.840736 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 22:12:45.841358 ===================================
539 22:12:45.843598 LPDDR4 DRAM CONFIGURATION
540 22:12:45.847662 ===================================
541 22:12:45.850759 EX_ROW_EN[0] = 0x0
542 22:12:45.851254 EX_ROW_EN[1] = 0x0
543 22:12:45.854919 LP4Y_EN = 0x0
544 22:12:45.855437 WORK_FSP = 0x0
545 22:12:45.858042 WL = 0x2
546 22:12:45.858552 RL = 0x2
547 22:12:45.861853 BL = 0x2
548 22:12:45.862292 RPST = 0x0
549 22:12:45.865921 RD_PRE = 0x0
550 22:12:45.866406 WR_PRE = 0x1
551 22:12:45.866846 WR_PST = 0x0
552 22:12:45.869299 DBI_WR = 0x0
553 22:12:45.869735 DBI_RD = 0x0
554 22:12:45.873595 OTF = 0x1
555 22:12:45.876955 ===================================
556 22:12:45.879754 ===================================
557 22:12:45.880295 ANA top config
558 22:12:45.883172 ===================================
559 22:12:45.886338 DLL_ASYNC_EN = 0
560 22:12:45.889877 ALL_SLAVE_EN = 1
561 22:12:45.893007 NEW_RANK_MODE = 1
562 22:12:45.893564 DLL_IDLE_MODE = 1
563 22:12:45.896126 LP45_APHY_COMB_EN = 1
564 22:12:45.899724 TX_ODT_DIS = 1
565 22:12:45.902854 NEW_8X_MODE = 1
566 22:12:45.906465 ===================================
567 22:12:45.909466 ===================================
568 22:12:45.910026 data_rate = 1600
569 22:12:45.913136 CKR = 1
570 22:12:45.916218 DQ_P2S_RATIO = 8
571 22:12:45.920059 ===================================
572 22:12:45.923045 CA_P2S_RATIO = 8
573 22:12:45.926221 DQ_CA_OPEN = 0
574 22:12:45.929766 DQ_SEMI_OPEN = 0
575 22:12:45.930309 CA_SEMI_OPEN = 0
576 22:12:45.932682 CA_FULL_RATE = 0
577 22:12:45.936387 DQ_CKDIV4_EN = 1
578 22:12:45.939745 CA_CKDIV4_EN = 1
579 22:12:45.942530 CA_PREDIV_EN = 0
580 22:12:45.946552 PH8_DLY = 0
581 22:12:45.947007 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 22:12:45.949049 DQ_AAMCK_DIV = 4
583 22:12:45.954176 CA_AAMCK_DIV = 4
584 22:12:45.956281 CA_ADMCK_DIV = 4
585 22:12:45.959687 DQ_TRACK_CA_EN = 0
586 22:12:45.963365 CA_PICK = 800
587 22:12:45.963953 CA_MCKIO = 800
588 22:12:45.966097 MCKIO_SEMI = 0
589 22:12:45.970340 PLL_FREQ = 3068
590 22:12:45.973512 DQ_UI_PI_RATIO = 32
591 22:12:45.977054 CA_UI_PI_RATIO = 0
592 22:12:45.981592 ===================================
593 22:12:45.982173 ===================================
594 22:12:45.984676 memory_type:LPDDR4
595 22:12:45.988847 GP_NUM : 10
596 22:12:45.989423 SRAM_EN : 1
597 22:12:45.991795 MD32_EN : 0
598 22:12:45.995031 ===================================
599 22:12:45.995516 [ANA_INIT] >>>>>>>>>>>>>>
600 22:12:45.998798 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 22:12:46.002495 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 22:12:46.006800 ===================================
603 22:12:46.009896 data_rate = 1600,PCW = 0X7600
604 22:12:46.013147 ===================================
605 22:12:46.016328 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 22:12:46.019667 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 22:12:46.026152 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 22:12:46.030276 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 22:12:46.036719 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 22:12:46.040111 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 22:12:46.040692 [ANA_INIT] flow start
612 22:12:46.042919 [ANA_INIT] PLL >>>>>>>>
613 22:12:46.046467 [ANA_INIT] PLL <<<<<<<<
614 22:12:46.047167 [ANA_INIT] MIDPI >>>>>>>>
615 22:12:46.049323 [ANA_INIT] MIDPI <<<<<<<<
616 22:12:46.052974 [ANA_INIT] DLL >>>>>>>>
617 22:12:46.053576 [ANA_INIT] flow end
618 22:12:46.056474 ============ LP4 DIFF to SE enter ============
619 22:12:46.063944 ============ LP4 DIFF to SE exit ============
620 22:12:46.064534 [ANA_INIT] <<<<<<<<<<<<<
621 22:12:46.066140 [Flow] Enable top DCM control >>>>>
622 22:12:46.069757 [Flow] Enable top DCM control <<<<<
623 22:12:46.073738 Enable DLL master slave shuffle
624 22:12:46.079909 ==============================================================
625 22:12:46.080497 Gating Mode config
626 22:12:46.086341 ==============================================================
627 22:12:46.089903 Config description:
628 22:12:46.099596 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 22:12:46.106485 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 22:12:46.109821 SELPH_MODE 0: By rank 1: By Phase
631 22:12:46.116713 ==============================================================
632 22:12:46.119893 GAT_TRACK_EN = 1
633 22:12:46.120481 RX_GATING_MODE = 2
634 22:12:46.123251 RX_GATING_TRACK_MODE = 2
635 22:12:46.126514 SELPH_MODE = 1
636 22:12:46.129951 PICG_EARLY_EN = 1
637 22:12:46.133501 VALID_LAT_VALUE = 1
638 22:12:46.140279 ==============================================================
639 22:12:46.143593 Enter into Gating configuration >>>>
640 22:12:46.146404 Exit from Gating configuration <<<<
641 22:12:46.149878 Enter into DVFS_PRE_config >>>>>
642 22:12:46.160306 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 22:12:46.163249 Exit from DVFS_PRE_config <<<<<
644 22:12:46.166723 Enter into PICG configuration >>>>
645 22:12:46.169771 Exit from PICG configuration <<<<
646 22:12:46.173362 [RX_INPUT] configuration >>>>>
647 22:12:46.173933 [RX_INPUT] configuration <<<<<
648 22:12:46.180001 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 22:12:46.186157 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 22:12:46.193061 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 22:12:46.196301 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 22:12:46.203224 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 22:12:46.209803 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 22:12:46.213116 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 22:12:46.216563 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 22:12:46.223324 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 22:12:46.226923 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 22:12:46.229938 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 22:12:46.236347 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 22:12:46.239761 ===================================
661 22:12:46.240531 LPDDR4 DRAM CONFIGURATION
662 22:12:46.243025 ===================================
663 22:12:46.246482 EX_ROW_EN[0] = 0x0
664 22:12:46.247259 EX_ROW_EN[1] = 0x0
665 22:12:46.249222 LP4Y_EN = 0x0
666 22:12:46.253036 WORK_FSP = 0x0
667 22:12:46.253620 WL = 0x2
668 22:12:46.255886 RL = 0x2
669 22:12:46.256470 BL = 0x2
670 22:12:46.259021 RPST = 0x0
671 22:12:46.259503 RD_PRE = 0x0
672 22:12:46.263061 WR_PRE = 0x1
673 22:12:46.263647 WR_PST = 0x0
674 22:12:46.266002 DBI_WR = 0x0
675 22:12:46.266510 DBI_RD = 0x0
676 22:12:46.269284 OTF = 0x1
677 22:12:46.272783 ===================================
678 22:12:46.275989 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 22:12:46.279511 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 22:12:46.285798 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 22:12:46.286416 ===================================
682 22:12:46.289358 LPDDR4 DRAM CONFIGURATION
683 22:12:46.292888 ===================================
684 22:12:46.296097 EX_ROW_EN[0] = 0x10
685 22:12:46.296675 EX_ROW_EN[1] = 0x0
686 22:12:46.299215 LP4Y_EN = 0x0
687 22:12:46.299799 WORK_FSP = 0x0
688 22:12:46.303275 WL = 0x2
689 22:12:46.303857 RL = 0x2
690 22:12:46.307123 BL = 0x2
691 22:12:46.307705 RPST = 0x0
692 22:12:46.309543 RD_PRE = 0x0
693 22:12:46.310202 WR_PRE = 0x1
694 22:12:46.313493 WR_PST = 0x0
695 22:12:46.314322 DBI_WR = 0x0
696 22:12:46.316996 DBI_RD = 0x0
697 22:12:46.317473 OTF = 0x1
698 22:12:46.320190 ===================================
699 22:12:46.327192 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 22:12:46.331761 nWR fixed to 40
701 22:12:46.335124 [ModeRegInit_LP4] CH0 RK0
702 22:12:46.335604 [ModeRegInit_LP4] CH0 RK1
703 22:12:46.338746 [ModeRegInit_LP4] CH1 RK0
704 22:12:46.339332 [ModeRegInit_LP4] CH1 RK1
705 22:12:46.342551 match AC timing 13
706 22:12:46.346146 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 22:12:46.349472 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 22:12:46.356449 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 22:12:46.360186 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 22:12:46.363353 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 22:12:46.367735 [EMI DOE] emi_dcm 0
712 22:12:46.371197 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 22:12:46.371669 ==
714 22:12:46.374916 Dram Type= 6, Freq= 0, CH_0, rank 0
715 22:12:46.378479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 22:12:46.379076 ==
717 22:12:46.381854 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 22:12:46.389359 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 22:12:46.399085 [CA 0] Center 38 (7~69) winsize 63
720 22:12:46.402927 [CA 1] Center 38 (7~69) winsize 63
721 22:12:46.406830 [CA 2] Center 35 (5~66) winsize 62
722 22:12:46.410519 [CA 3] Center 35 (5~66) winsize 62
723 22:12:46.413949 [CA 4] Center 35 (4~66) winsize 63
724 22:12:46.417604 [CA 5] Center 33 (3~64) winsize 62
725 22:12:46.418201
726 22:12:46.421718 [CmdBusTrainingLP45] Vref(ca) range 1: 32
727 22:12:46.422307
728 22:12:46.425398 [CATrainingPosCal] consider 1 rank data
729 22:12:46.426009 u2DelayCellTimex100 = 270/100 ps
730 22:12:46.428801 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
731 22:12:46.432073 CA1 delay=38 (7~69),Diff = 5 PI (36 cell)
732 22:12:46.436063 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
733 22:12:46.439661 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
734 22:12:46.443094 CA4 delay=35 (4~66),Diff = 2 PI (14 cell)
735 22:12:46.446797 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
736 22:12:46.447426
737 22:12:46.454216 CA PerBit enable=1, Macro0, CA PI delay=33
738 22:12:46.454744
739 22:12:46.455124 [CBTSetCACLKResult] CA Dly = 33
740 22:12:46.458107 CS Dly: 5 (0~36)
741 22:12:46.458646 ==
742 22:12:46.461952 Dram Type= 6, Freq= 0, CH_0, rank 1
743 22:12:46.465476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 22:12:46.466071 ==
745 22:12:46.469254 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 22:12:46.476273 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 22:12:46.485494 [CA 0] Center 38 (7~69) winsize 63
748 22:12:46.488834 [CA 1] Center 38 (7~69) winsize 63
749 22:12:46.492636 [CA 2] Center 36 (6~66) winsize 61
750 22:12:46.496310 [CA 3] Center 36 (5~67) winsize 63
751 22:12:46.500130 [CA 4] Center 35 (4~66) winsize 63
752 22:12:46.503291 [CA 5] Center 34 (4~65) winsize 62
753 22:12:46.503885
754 22:12:46.506455 [CmdBusTrainingLP45] Vref(ca) range 1: 34
755 22:12:46.506934
756 22:12:46.510533 [CATrainingPosCal] consider 2 rank data
757 22:12:46.514468 u2DelayCellTimex100 = 270/100 ps
758 22:12:46.518029 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
759 22:12:46.522303 CA1 delay=38 (7~69),Diff = 4 PI (28 cell)
760 22:12:46.525504 CA2 delay=36 (6~66),Diff = 2 PI (14 cell)
761 22:12:46.529278 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
762 22:12:46.532639 CA4 delay=35 (4~66),Diff = 1 PI (7 cell)
763 22:12:46.536081 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
764 22:12:46.536557
765 22:12:46.539967 CA PerBit enable=1, Macro0, CA PI delay=34
766 22:12:46.540483
767 22:12:46.540865 [CBTSetCACLKResult] CA Dly = 34
768 22:12:46.543702 CS Dly: 6 (0~38)
769 22:12:46.544183
770 22:12:46.547623 ----->DramcWriteLeveling(PI) begin...
771 22:12:46.548162 ==
772 22:12:46.550846 Dram Type= 6, Freq= 0, CH_0, rank 0
773 22:12:46.554895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 22:12:46.555373 ==
775 22:12:46.558410 Write leveling (Byte 0): 30 => 30
776 22:12:46.561968 Write leveling (Byte 1): 29 => 29
777 22:12:46.562488 DramcWriteLeveling(PI) end<-----
778 22:12:46.566245
779 22:12:46.566842 ==
780 22:12:46.567198 Dram Type= 6, Freq= 0, CH_0, rank 0
781 22:12:46.572898 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 22:12:46.573341 ==
783 22:12:46.573692 [Gating] SW mode calibration
784 22:12:46.580576 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 22:12:46.588076 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 22:12:46.591913 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 22:12:46.596068 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
788 22:12:46.599650 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
789 22:12:46.603447 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 22:12:46.610488 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 22:12:46.614338 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 22:12:46.617972 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 22:12:46.621224 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 22:12:46.627934 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 22:12:46.630924 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 22:12:46.633816 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 22:12:46.640454 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 22:12:46.643905 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 22:12:46.647051 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 22:12:46.653761 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 22:12:46.657083 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 22:12:46.660519 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
803 22:12:46.667511 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
804 22:12:46.670414 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 22:12:46.674486 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
806 22:12:46.680475 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 22:12:46.683873 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 22:12:46.686976 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 22:12:46.690759 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 22:12:46.697063 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 22:12:46.700347 0 9 4 | B1->B0 | 2323 2424 | 0 1 | (0 0) (1 1)
812 22:12:46.703716 0 9 8 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
813 22:12:46.710324 0 9 12 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
814 22:12:46.713814 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 22:12:46.716722 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 22:12:46.723967 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 22:12:46.727086 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 22:12:46.730751 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 22:12:46.737067 0 10 4 | B1->B0 | 3434 3232 | 1 0 | (1 0) (0 1)
820 22:12:46.740593 0 10 8 | B1->B0 | 3030 2323 | 1 0 | (1 0) (0 0)
821 22:12:46.743937 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 22:12:46.750253 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 22:12:46.753717 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 22:12:46.756821 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 22:12:46.763851 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 22:12:46.766980 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 22:12:46.770404 0 11 4 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
828 22:12:46.777188 0 11 8 | B1->B0 | 2b2b 4646 | 0 0 | (0 0) (0 0)
829 22:12:46.779949 0 11 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
830 22:12:46.783953 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 22:12:46.790173 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 22:12:46.793583 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 22:12:46.797231 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 22:12:46.803587 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 22:12:46.807079 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
836 22:12:46.810499 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
837 22:12:46.814193 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 22:12:46.820450 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 22:12:46.823814 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 22:12:46.826952 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 22:12:46.833523 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 22:12:46.836862 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 22:12:46.840222 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 22:12:46.846852 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 22:12:46.850141 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 22:12:46.853398 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 22:12:46.860238 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 22:12:46.863582 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 22:12:46.866578 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 22:12:46.873719 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 22:12:46.877660 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
852 22:12:46.880071 Total UI for P1: 0, mck2ui 16
853 22:12:46.883602 best dqsien dly found for B0: ( 0, 14, 2)
854 22:12:46.887205 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
855 22:12:46.893759 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
856 22:12:46.894344 Total UI for P1: 0, mck2ui 16
857 22:12:46.896710 best dqsien dly found for B1: ( 0, 14, 6)
858 22:12:46.903367 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
859 22:12:46.906552 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
860 22:12:46.907031
861 22:12:46.910418 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
862 22:12:46.914072 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
863 22:12:46.916661 [Gating] SW calibration Done
864 22:12:46.917228 ==
865 22:12:46.919817 Dram Type= 6, Freq= 0, CH_0, rank 0
866 22:12:46.923930 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
867 22:12:46.924507 ==
868 22:12:46.926575 RX Vref Scan: 0
869 22:12:46.927052
870 22:12:46.927430 RX Vref 0 -> 0, step: 1
871 22:12:46.927789
872 22:12:46.929686 RX Delay -130 -> 252, step: 16
873 22:12:46.933309 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
874 22:12:46.940031 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
875 22:12:46.943245 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
876 22:12:46.946741 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
877 22:12:46.949835 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
878 22:12:46.953706 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
879 22:12:46.960042 iDelay=222, Bit 6, Center 109 (-2 ~ 221) 224
880 22:12:46.962955 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
881 22:12:46.966527 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
882 22:12:46.969929 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
883 22:12:46.972913 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
884 22:12:46.979608 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
885 22:12:46.983012 iDelay=222, Bit 12, Center 85 (-18 ~ 189) 208
886 22:12:46.986540 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
887 22:12:46.990460 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
888 22:12:46.993210 iDelay=222, Bit 15, Center 85 (-18 ~ 189) 208
889 22:12:46.996604 ==
890 22:12:46.997139 Dram Type= 6, Freq= 0, CH_0, rank 0
891 22:12:47.003261 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
892 22:12:47.003795 ==
893 22:12:47.004145 DQS Delay:
894 22:12:47.007289 DQS0 = 0, DQS1 = 0
895 22:12:47.007816 DQM Delay:
896 22:12:47.010034 DQM0 = 94, DQM1 = 80
897 22:12:47.010580 DQ Delay:
898 22:12:47.013131 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =93
899 22:12:47.016767 DQ4 =93, DQ5 =77, DQ6 =109, DQ7 =101
900 22:12:47.019588 DQ8 =77, DQ9 =61, DQ10 =77, DQ11 =77
901 22:12:47.023491 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
902 22:12:47.024022
903 22:12:47.024372
904 22:12:47.024693 ==
905 22:12:47.026502 Dram Type= 6, Freq= 0, CH_0, rank 0
906 22:12:47.029766 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
907 22:12:47.030300 ==
908 22:12:47.030704
909 22:12:47.031031
910 22:12:47.033125 TX Vref Scan disable
911 22:12:47.036157 == TX Byte 0 ==
912 22:12:47.039842 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
913 22:12:47.043255 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
914 22:12:47.046473 == TX Byte 1 ==
915 22:12:47.049301 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
916 22:12:47.052721 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
917 22:12:47.053179 ==
918 22:12:47.056523 Dram Type= 6, Freq= 0, CH_0, rank 0
919 22:12:47.059844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
920 22:12:47.063074 ==
921 22:12:47.074270 TX Vref=22, minBit 6, minWin=27, winSum=440
922 22:12:47.077529 TX Vref=24, minBit 6, minWin=27, winSum=445
923 22:12:47.080405 TX Vref=26, minBit 6, minWin=27, winSum=447
924 22:12:47.084253 TX Vref=28, minBit 12, minWin=27, winSum=454
925 22:12:47.087270 TX Vref=30, minBit 3, minWin=28, winSum=454
926 22:12:47.093964 TX Vref=32, minBit 10, minWin=27, winSum=453
927 22:12:47.097313 [TxChooseVref] Worse bit 3, Min win 28, Win sum 454, Final Vref 30
928 22:12:47.097886
929 22:12:47.101042 Final TX Range 1 Vref 30
930 22:12:47.101617
931 22:12:47.102002 ==
932 22:12:47.103885 Dram Type= 6, Freq= 0, CH_0, rank 0
933 22:12:47.107140 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 22:12:47.107618 ==
935 22:12:47.110509
936 22:12:47.111034
937 22:12:47.111417 TX Vref Scan disable
938 22:12:47.114739 == TX Byte 0 ==
939 22:12:47.117561 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
940 22:12:47.124303 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
941 22:12:47.124889 == TX Byte 1 ==
942 22:12:47.127683 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
943 22:12:47.134169 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
944 22:12:47.134824
945 22:12:47.135274 [DATLAT]
946 22:12:47.135634 Freq=800, CH0 RK0
947 22:12:47.135973
948 22:12:47.137493 DATLAT Default: 0xa
949 22:12:47.137962 0, 0xFFFF, sum = 0
950 22:12:47.141138 1, 0xFFFF, sum = 0
951 22:12:47.141720 2, 0xFFFF, sum = 0
952 22:12:47.144086 3, 0xFFFF, sum = 0
953 22:12:47.144664 4, 0xFFFF, sum = 0
954 22:12:47.147408 5, 0xFFFF, sum = 0
955 22:12:47.150992 6, 0xFFFF, sum = 0
956 22:12:47.151615 7, 0xFFFF, sum = 0
957 22:12:47.153899 8, 0xFFFF, sum = 0
958 22:12:47.154413 9, 0x0, sum = 1
959 22:12:47.154809 10, 0x0, sum = 2
960 22:12:47.157603 11, 0x0, sum = 3
961 22:12:47.158180 12, 0x0, sum = 4
962 22:12:47.160798 best_step = 10
963 22:12:47.161365
964 22:12:47.161744 ==
965 22:12:47.164401 Dram Type= 6, Freq= 0, CH_0, rank 0
966 22:12:47.167614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
967 22:12:47.168180 ==
968 22:12:47.171055 RX Vref Scan: 1
969 22:12:47.171615
970 22:12:47.171985 Set Vref Range= 32 -> 127
971 22:12:47.172332
972 22:12:47.173819 RX Vref 32 -> 127, step: 1
973 22:12:47.174288
974 22:12:47.177936 RX Delay -95 -> 252, step: 8
975 22:12:47.178551
976 22:12:47.180819 Set Vref, RX VrefLevel [Byte0]: 32
977 22:12:47.183896 [Byte1]: 32
978 22:12:47.184465
979 22:12:47.187311 Set Vref, RX VrefLevel [Byte0]: 33
980 22:12:47.190471 [Byte1]: 33
981 22:12:47.194514
982 22:12:47.195073 Set Vref, RX VrefLevel [Byte0]: 34
983 22:12:47.198051 [Byte1]: 34
984 22:12:47.202095
985 22:12:47.202701 Set Vref, RX VrefLevel [Byte0]: 35
986 22:12:47.205810 [Byte1]: 35
987 22:12:47.209900
988 22:12:47.210462 Set Vref, RX VrefLevel [Byte0]: 36
989 22:12:47.213111 [Byte1]: 36
990 22:12:47.217443
991 22:12:47.217973 Set Vref, RX VrefLevel [Byte0]: 37
992 22:12:47.220560 [Byte1]: 37
993 22:12:47.225508
994 22:12:47.226077 Set Vref, RX VrefLevel [Byte0]: 38
995 22:12:47.228857 [Byte1]: 38
996 22:12:47.232822
997 22:12:47.233391 Set Vref, RX VrefLevel [Byte0]: 39
998 22:12:47.236342 [Byte1]: 39
999 22:12:47.240429
1000 22:12:47.240996 Set Vref, RX VrefLevel [Byte0]: 40
1001 22:12:47.244250 [Byte1]: 40
1002 22:12:47.247849
1003 22:12:47.248318 Set Vref, RX VrefLevel [Byte0]: 41
1004 22:12:47.251576 [Byte1]: 41
1005 22:12:47.255538
1006 22:12:47.256009 Set Vref, RX VrefLevel [Byte0]: 42
1007 22:12:47.258755 [Byte1]: 42
1008 22:12:47.263214
1009 22:12:47.263784 Set Vref, RX VrefLevel [Byte0]: 43
1010 22:12:47.266252 [Byte1]: 43
1011 22:12:47.270532
1012 22:12:47.271098 Set Vref, RX VrefLevel [Byte0]: 44
1013 22:12:47.273910 [Byte1]: 44
1014 22:12:47.278303
1015 22:12:47.278929 Set Vref, RX VrefLevel [Byte0]: 45
1016 22:12:47.281170 [Byte1]: 45
1017 22:12:47.285578
1018 22:12:47.286159 Set Vref, RX VrefLevel [Byte0]: 46
1019 22:12:47.288782 [Byte1]: 46
1020 22:12:47.293103
1021 22:12:47.293668 Set Vref, RX VrefLevel [Byte0]: 47
1022 22:12:47.297117 [Byte1]: 47
1023 22:12:47.301132
1024 22:12:47.301704 Set Vref, RX VrefLevel [Byte0]: 48
1025 22:12:47.304113 [Byte1]: 48
1026 22:12:47.308570
1027 22:12:47.309153 Set Vref, RX VrefLevel [Byte0]: 49
1028 22:12:47.311422 [Byte1]: 49
1029 22:12:47.316008
1030 22:12:47.316583 Set Vref, RX VrefLevel [Byte0]: 50
1031 22:12:47.319509 [Byte1]: 50
1032 22:12:47.323956
1033 22:12:47.324525 Set Vref, RX VrefLevel [Byte0]: 51
1034 22:12:47.327044 [Byte1]: 51
1035 22:12:47.331320
1036 22:12:47.331886 Set Vref, RX VrefLevel [Byte0]: 52
1037 22:12:47.334596 [Byte1]: 52
1038 22:12:47.339093
1039 22:12:47.339657 Set Vref, RX VrefLevel [Byte0]: 53
1040 22:12:47.342190 [Byte1]: 53
1041 22:12:47.346502
1042 22:12:47.347070 Set Vref, RX VrefLevel [Byte0]: 54
1043 22:12:47.349693 [Byte1]: 54
1044 22:12:47.354176
1045 22:12:47.354688 Set Vref, RX VrefLevel [Byte0]: 55
1046 22:12:47.357576 [Byte1]: 55
1047 22:12:47.361983
1048 22:12:47.362592 Set Vref, RX VrefLevel [Byte0]: 56
1049 22:12:47.365041 [Byte1]: 56
1050 22:12:47.369311
1051 22:12:47.369881 Set Vref, RX VrefLevel [Byte0]: 57
1052 22:12:47.372443 [Byte1]: 57
1053 22:12:47.376878
1054 22:12:47.377446 Set Vref, RX VrefLevel [Byte0]: 58
1055 22:12:47.379971 [Byte1]: 58
1056 22:12:47.385762
1057 22:12:47.386330 Set Vref, RX VrefLevel [Byte0]: 59
1058 22:12:47.387391 [Byte1]: 59
1059 22:12:47.392046
1060 22:12:47.392619 Set Vref, RX VrefLevel [Byte0]: 60
1061 22:12:47.395101 [Byte1]: 60
1062 22:12:47.399832
1063 22:12:47.400401 Set Vref, RX VrefLevel [Byte0]: 61
1064 22:12:47.403132 [Byte1]: 61
1065 22:12:47.407263
1066 22:12:47.407999 Set Vref, RX VrefLevel [Byte0]: 62
1067 22:12:47.410557 [Byte1]: 62
1068 22:12:47.414847
1069 22:12:47.415558 Set Vref, RX VrefLevel [Byte0]: 63
1070 22:12:47.418304 [Byte1]: 63
1071 22:12:47.422252
1072 22:12:47.422762 Set Vref, RX VrefLevel [Byte0]: 64
1073 22:12:47.425588 [Byte1]: 64
1074 22:12:47.429901
1075 22:12:47.430577 Set Vref, RX VrefLevel [Byte0]: 65
1076 22:12:47.433465 [Byte1]: 65
1077 22:12:47.437748
1078 22:12:47.438318 Set Vref, RX VrefLevel [Byte0]: 66
1079 22:12:47.440957 [Byte1]: 66
1080 22:12:47.445297
1081 22:12:47.445864 Set Vref, RX VrefLevel [Byte0]: 67
1082 22:12:47.448332 [Byte1]: 67
1083 22:12:47.454424
1084 22:12:47.454901 Set Vref, RX VrefLevel [Byte0]: 68
1085 22:12:47.456098 [Byte1]: 68
1086 22:12:47.460876
1087 22:12:47.461449 Set Vref, RX VrefLevel [Byte0]: 69
1088 22:12:47.463787 [Byte1]: 69
1089 22:12:47.468203
1090 22:12:47.468774 Set Vref, RX VrefLevel [Byte0]: 70
1091 22:12:47.471697 [Byte1]: 70
1092 22:12:47.475928
1093 22:12:47.476511 Set Vref, RX VrefLevel [Byte0]: 71
1094 22:12:47.478883 [Byte1]: 71
1095 22:12:47.483061
1096 22:12:47.483634 Set Vref, RX VrefLevel [Byte0]: 72
1097 22:12:47.486668 [Byte1]: 72
1098 22:12:47.491047
1099 22:12:47.491521 Set Vref, RX VrefLevel [Byte0]: 73
1100 22:12:47.494394 [Byte1]: 73
1101 22:12:47.498582
1102 22:12:47.499154 Set Vref, RX VrefLevel [Byte0]: 74
1103 22:12:47.501501 [Byte1]: 74
1104 22:12:47.505949
1105 22:12:47.506563 Set Vref, RX VrefLevel [Byte0]: 75
1106 22:12:47.509138 [Byte1]: 75
1107 22:12:47.513527
1108 22:12:47.516684 Set Vref, RX VrefLevel [Byte0]: 76
1109 22:12:47.517159 [Byte1]: 76
1110 22:12:47.520785
1111 22:12:47.521254 Final RX Vref Byte 0 = 59 to rank0
1112 22:12:47.524636 Final RX Vref Byte 1 = 63 to rank0
1113 22:12:47.528042 Final RX Vref Byte 0 = 59 to rank1
1114 22:12:47.531663 Final RX Vref Byte 1 = 63 to rank1==
1115 22:12:47.534319 Dram Type= 6, Freq= 0, CH_0, rank 0
1116 22:12:47.541394 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1117 22:12:47.541972 ==
1118 22:12:47.542405 DQS Delay:
1119 22:12:47.542771 DQS0 = 0, DQS1 = 0
1120 22:12:47.544950 DQM Delay:
1121 22:12:47.545523 DQM0 = 93, DQM1 = 83
1122 22:12:47.547744 DQ Delay:
1123 22:12:47.550879 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1124 22:12:47.554672 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104
1125 22:12:47.557721 DQ8 =72, DQ9 =72, DQ10 =80, DQ11 =80
1126 22:12:47.561451 DQ12 =88, DQ13 =88, DQ14 =92, DQ15 =92
1127 22:12:47.562018
1128 22:12:47.562441
1129 22:12:47.567602 [DQSOSCAuto] RK0, (LSB)MR18= 0x3a35, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 395 ps
1130 22:12:47.570992 CH0 RK0: MR19=606, MR18=3A35
1131 22:12:47.577670 CH0_RK0: MR19=0x606, MR18=0x3A35, DQSOSC=395, MR23=63, INC=94, DEC=63
1132 22:12:47.578241
1133 22:12:47.581177 ----->DramcWriteLeveling(PI) begin...
1134 22:12:47.581780 ==
1135 22:12:47.584462 Dram Type= 6, Freq= 0, CH_0, rank 1
1136 22:12:47.587902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1137 22:12:47.588502 ==
1138 22:12:47.591179 Write leveling (Byte 0): 32 => 32
1139 22:12:47.595016 Write leveling (Byte 1): 33 => 33
1140 22:12:47.597503 DramcWriteLeveling(PI) end<-----
1141 22:12:47.598067
1142 22:12:47.598484 ==
1143 22:12:47.601461 Dram Type= 6, Freq= 0, CH_0, rank 1
1144 22:12:47.604813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1145 22:12:47.605328 ==
1146 22:12:47.607557 [Gating] SW mode calibration
1147 22:12:47.614437 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1148 22:12:47.621310 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1149 22:12:47.624202 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1150 22:12:47.668476 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1151 22:12:47.669393 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1152 22:12:47.669807 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1153 22:12:47.670174 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1154 22:12:47.670632 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 22:12:47.671057 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 22:12:47.671407 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 22:12:47.671740 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 22:12:47.672065 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 22:12:47.672383 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 22:12:47.688632 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 22:12:47.689233 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 22:12:47.689946 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 22:12:47.690330 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 22:12:47.692086 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 22:12:47.695932 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 22:12:47.698873 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1167 22:12:47.705578 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1168 22:12:47.708708 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 22:12:47.712105 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 22:12:47.715438 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 22:12:47.721970 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 22:12:47.725455 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 22:12:47.728656 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 22:12:47.735182 0 9 4 | B1->B0 | 2323 2625 | 0 1 | (0 0) (0 0)
1175 22:12:47.738502 0 9 8 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
1176 22:12:47.742221 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1177 22:12:47.748977 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1178 22:12:47.751935 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1179 22:12:47.755203 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1180 22:12:47.762034 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 22:12:47.765443 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1182 22:12:47.769288 0 10 4 | B1->B0 | 3434 3030 | 1 0 | (1 0) (1 0)
1183 22:12:47.775141 0 10 8 | B1->B0 | 2b2b 2323 | 1 0 | (1 0) (1 0)
1184 22:12:47.778924 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 22:12:47.782195 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 22:12:47.788878 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 22:12:47.791826 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 22:12:47.795301 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 22:12:47.802292 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 22:12:47.805470 0 11 4 | B1->B0 | 2626 3232 | 0 0 | (0 0) (0 0)
1191 22:12:47.809131 0 11 8 | B1->B0 | 3d3d 4646 | 1 0 | (0 0) (0 0)
1192 22:12:47.812427 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1193 22:12:47.819524 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1194 22:12:47.823769 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1195 22:12:47.826196 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1196 22:12:47.829718 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 22:12:47.836689 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 22:12:47.840662 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 22:12:47.843893 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1200 22:12:47.850375 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 22:12:47.853694 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 22:12:47.856458 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 22:12:47.864217 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 22:12:47.866860 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 22:12:47.870192 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 22:12:47.876673 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 22:12:47.880267 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 22:12:47.882983 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 22:12:47.886926 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 22:12:47.893884 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 22:12:47.896656 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 22:12:47.900350 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 22:12:47.906928 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 22:12:47.910076 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1215 22:12:47.913201 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1216 22:12:47.917393 Total UI for P1: 0, mck2ui 16
1217 22:12:47.920293 best dqsien dly found for B0: ( 0, 14, 4)
1218 22:12:47.926642 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1219 22:12:47.927223 Total UI for P1: 0, mck2ui 16
1220 22:12:47.933487 best dqsien dly found for B1: ( 0, 14, 6)
1221 22:12:47.936642 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1222 22:12:47.940083 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1223 22:12:47.940651
1224 22:12:47.943759 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1225 22:12:47.946782 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1226 22:12:47.950714 [Gating] SW calibration Done
1227 22:12:47.951381 ==
1228 22:12:47.953269 Dram Type= 6, Freq= 0, CH_0, rank 1
1229 22:12:47.956525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1230 22:12:47.957005 ==
1231 22:12:47.960521 RX Vref Scan: 0
1232 22:12:47.961094
1233 22:12:47.961475 RX Vref 0 -> 0, step: 1
1234 22:12:47.961827
1235 22:12:47.962925 RX Delay -130 -> 252, step: 16
1236 22:12:47.966228 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1237 22:12:47.973438 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1238 22:12:47.976428 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
1239 22:12:47.980239 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1240 22:12:47.982713 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1241 22:12:47.986392 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
1242 22:12:47.992983 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1243 22:12:47.996757 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1244 22:12:47.999744 iDelay=222, Bit 8, Center 69 (-34 ~ 173) 208
1245 22:12:48.002952 iDelay=222, Bit 9, Center 69 (-34 ~ 173) 208
1246 22:12:48.006552 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1247 22:12:48.012557 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1248 22:12:48.016711 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1249 22:12:48.019959 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1250 22:12:48.022791 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1251 22:12:48.029359 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1252 22:12:48.029829 ==
1253 22:12:48.032866 Dram Type= 6, Freq= 0, CH_0, rank 1
1254 22:12:48.035927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1255 22:12:48.036438 ==
1256 22:12:48.036924 DQS Delay:
1257 22:12:48.039368 DQS0 = 0, DQS1 = 0
1258 22:12:48.039837 DQM Delay:
1259 22:12:48.042790 DQM0 = 91, DQM1 = 80
1260 22:12:48.043260 DQ Delay:
1261 22:12:48.046344 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =85
1262 22:12:48.049766 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =93
1263 22:12:48.052829 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =77
1264 22:12:48.056093 DQ12 =77, DQ13 =85, DQ14 =93, DQ15 =93
1265 22:12:48.056565
1266 22:12:48.056999
1267 22:12:48.057348 ==
1268 22:12:48.060050 Dram Type= 6, Freq= 0, CH_0, rank 1
1269 22:12:48.063103 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1270 22:12:48.063681 ==
1271 22:12:48.064067
1272 22:12:48.064415
1273 22:12:48.066075 TX Vref Scan disable
1274 22:12:48.070259 == TX Byte 0 ==
1275 22:12:48.072845 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1276 22:12:48.076268 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1277 22:12:48.079784 == TX Byte 1 ==
1278 22:12:48.082911 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1279 22:12:48.086457 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1280 22:12:48.087031 ==
1281 22:12:48.090445 Dram Type= 6, Freq= 0, CH_0, rank 1
1282 22:12:48.096161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1283 22:12:48.096742 ==
1284 22:12:48.107628 TX Vref=22, minBit 3, minWin=27, winSum=445
1285 22:12:48.110771 TX Vref=24, minBit 11, minWin=27, winSum=452
1286 22:12:48.114589 TX Vref=26, minBit 8, minWin=27, winSum=449
1287 22:12:48.117839 TX Vref=28, minBit 8, minWin=28, winSum=457
1288 22:12:48.120918 TX Vref=30, minBit 8, minWin=28, winSum=457
1289 22:12:48.127528 TX Vref=32, minBit 8, minWin=28, winSum=457
1290 22:12:48.131132 [TxChooseVref] Worse bit 8, Min win 28, Win sum 457, Final Vref 28
1291 22:12:48.131707
1292 22:12:48.133908 Final TX Range 1 Vref 28
1293 22:12:48.134392
1294 22:12:48.134760 ==
1295 22:12:48.136924 Dram Type= 6, Freq= 0, CH_0, rank 1
1296 22:12:48.140196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1297 22:12:48.143478 ==
1298 22:12:48.143936
1299 22:12:48.144301
1300 22:12:48.144636 TX Vref Scan disable
1301 22:12:48.147420 == TX Byte 0 ==
1302 22:12:48.150934 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1303 22:12:48.157241 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1304 22:12:48.157669 == TX Byte 1 ==
1305 22:12:48.160590 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1306 22:12:48.167045 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1307 22:12:48.167344
1308 22:12:48.167582 [DATLAT]
1309 22:12:48.167801 Freq=800, CH0 RK1
1310 22:12:48.168016
1311 22:12:48.170804 DATLAT Default: 0xa
1312 22:12:48.171190 0, 0xFFFF, sum = 0
1313 22:12:48.174450 1, 0xFFFF, sum = 0
1314 22:12:48.174839 2, 0xFFFF, sum = 0
1315 22:12:48.177452 3, 0xFFFF, sum = 0
1316 22:12:48.177973 4, 0xFFFF, sum = 0
1317 22:12:48.180551 5, 0xFFFF, sum = 0
1318 22:12:48.183664 6, 0xFFFF, sum = 0
1319 22:12:48.183972 7, 0xFFFF, sum = 0
1320 22:12:48.187025 8, 0xFFFF, sum = 0
1321 22:12:48.187402 9, 0x0, sum = 1
1322 22:12:48.187705 10, 0x0, sum = 2
1323 22:12:48.190712 11, 0x0, sum = 3
1324 22:12:48.191108 12, 0x0, sum = 4
1325 22:12:48.194365 best_step = 10
1326 22:12:48.194866
1327 22:12:48.195241 ==
1328 22:12:48.197565 Dram Type= 6, Freq= 0, CH_0, rank 1
1329 22:12:48.200681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1330 22:12:48.201238 ==
1331 22:12:48.204065 RX Vref Scan: 0
1332 22:12:48.204616
1333 22:12:48.204989 RX Vref 0 -> 0, step: 1
1334 22:12:48.207268
1335 22:12:48.207805 RX Delay -79 -> 252, step: 8
1336 22:12:48.214212 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1337 22:12:48.217940 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1338 22:12:48.220513 iDelay=209, Bit 2, Center 92 (-15 ~ 200) 216
1339 22:12:48.224009 iDelay=209, Bit 3, Center 84 (-23 ~ 192) 216
1340 22:12:48.227775 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1341 22:12:48.235008 iDelay=209, Bit 5, Center 80 (-31 ~ 192) 224
1342 22:12:48.237867 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1343 22:12:48.240643 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1344 22:12:48.244006 iDelay=209, Bit 8, Center 72 (-31 ~ 176) 208
1345 22:12:48.247485 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1346 22:12:48.253955 iDelay=209, Bit 10, Center 80 (-23 ~ 184) 208
1347 22:12:48.258421 iDelay=209, Bit 11, Center 76 (-23 ~ 176) 200
1348 22:12:48.260507 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1349 22:12:48.263887 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1350 22:12:48.267242 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1351 22:12:48.273892 iDelay=209, Bit 15, Center 88 (-15 ~ 192) 208
1352 22:12:48.274486 ==
1353 22:12:48.277225 Dram Type= 6, Freq= 0, CH_0, rank 1
1354 22:12:48.280674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1355 22:12:48.281238 ==
1356 22:12:48.281610 DQS Delay:
1357 22:12:48.283582 DQS0 = 0, DQS1 = 0
1358 22:12:48.284044 DQM Delay:
1359 22:12:48.286994 DQM0 = 91, DQM1 = 81
1360 22:12:48.287453 DQ Delay:
1361 22:12:48.290524 DQ0 =88, DQ1 =92, DQ2 =92, DQ3 =84
1362 22:12:48.294245 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1363 22:12:48.297419 DQ8 =72, DQ9 =72, DQ10 =80, DQ11 =76
1364 22:12:48.300575 DQ12 =84, DQ13 =84, DQ14 =92, DQ15 =88
1365 22:12:48.301126
1366 22:12:48.301491
1367 22:12:48.310575 [DQSOSCAuto] RK1, (LSB)MR18= 0x4721, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 392 ps
1368 22:12:48.311137 CH0 RK1: MR19=606, MR18=4721
1369 22:12:48.317379 CH0_RK1: MR19=0x606, MR18=0x4721, DQSOSC=392, MR23=63, INC=96, DEC=64
1370 22:12:48.320790 [RxdqsGatingPostProcess] freq 800
1371 22:12:48.327121 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1372 22:12:48.330783 Pre-setting of DQS Precalculation
1373 22:12:48.333788 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1374 22:12:48.334341 ==
1375 22:12:48.336762 Dram Type= 6, Freq= 0, CH_1, rank 0
1376 22:12:48.340567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1377 22:12:48.344091 ==
1378 22:12:48.347503 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1379 22:12:48.353591 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1380 22:12:48.362901 [CA 0] Center 36 (6~67) winsize 62
1381 22:12:48.366705 [CA 1] Center 36 (6~67) winsize 62
1382 22:12:48.369649 [CA 2] Center 34 (4~65) winsize 62
1383 22:12:48.372908 [CA 3] Center 34 (4~65) winsize 62
1384 22:12:48.375897 [CA 4] Center 34 (4~65) winsize 62
1385 22:12:48.379199 [CA 5] Center 33 (3~64) winsize 62
1386 22:12:48.379662
1387 22:12:48.382652 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1388 22:12:48.383113
1389 22:12:48.385936 [CATrainingPosCal] consider 1 rank data
1390 22:12:48.389716 u2DelayCellTimex100 = 270/100 ps
1391 22:12:48.392699 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1392 22:12:48.399094 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1393 22:12:48.402865 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1394 22:12:48.406316 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1395 22:12:48.409220 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1396 22:12:48.412479 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1397 22:12:48.413036
1398 22:12:48.415892 CA PerBit enable=1, Macro0, CA PI delay=33
1399 22:12:48.416447
1400 22:12:48.419330 [CBTSetCACLKResult] CA Dly = 33
1401 22:12:48.419884 CS Dly: 5 (0~36)
1402 22:12:48.422330 ==
1403 22:12:48.422982 Dram Type= 6, Freq= 0, CH_1, rank 1
1404 22:12:48.429250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1405 22:12:48.429791 ==
1406 22:12:48.432244 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1407 22:12:48.439279 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1408 22:12:48.448832 [CA 0] Center 37 (7~67) winsize 61
1409 22:12:48.451802 [CA 1] Center 37 (6~68) winsize 63
1410 22:12:48.455703 [CA 2] Center 35 (5~66) winsize 62
1411 22:12:48.458825 [CA 3] Center 34 (4~65) winsize 62
1412 22:12:48.462471 [CA 4] Center 34 (4~65) winsize 62
1413 22:12:48.466176 [CA 5] Center 34 (3~65) winsize 63
1414 22:12:48.466805
1415 22:12:48.469258 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1416 22:12:48.469841
1417 22:12:48.472263 [CATrainingPosCal] consider 2 rank data
1418 22:12:48.475881 u2DelayCellTimex100 = 270/100 ps
1419 22:12:48.479659 CA0 delay=37 (7~67),Diff = 4 PI (28 cell)
1420 22:12:48.483593 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1421 22:12:48.487239 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1422 22:12:48.491040 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1423 22:12:48.494756 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1424 22:12:48.498207 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1425 22:12:48.498708
1426 22:12:48.503001 CA PerBit enable=1, Macro0, CA PI delay=33
1427 22:12:48.503607
1428 22:12:48.505834 [CBTSetCACLKResult] CA Dly = 33
1429 22:12:48.506477 CS Dly: 6 (0~38)
1430 22:12:48.506865
1431 22:12:48.508778 ----->DramcWriteLeveling(PI) begin...
1432 22:12:48.512284 ==
1433 22:12:48.515362 Dram Type= 6, Freq= 0, CH_1, rank 0
1434 22:12:48.519002 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1435 22:12:48.519568 ==
1436 22:12:48.522089 Write leveling (Byte 0): 25 => 25
1437 22:12:48.525421 Write leveling (Byte 1): 30 => 30
1438 22:12:48.528719 DramcWriteLeveling(PI) end<-----
1439 22:12:48.529283
1440 22:12:48.529661 ==
1441 22:12:48.532178 Dram Type= 6, Freq= 0, CH_1, rank 0
1442 22:12:48.535229 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1443 22:12:48.535793 ==
1444 22:12:48.538522 [Gating] SW mode calibration
1445 22:12:48.545302 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1446 22:12:48.548725 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1447 22:12:48.555481 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1448 22:12:48.558506 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1449 22:12:48.562108 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1450 22:12:48.568747 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1451 22:12:48.571653 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 22:12:48.575143 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 22:12:48.582163 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 22:12:48.584940 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 22:12:48.588553 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 22:12:48.594982 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 22:12:48.598465 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 22:12:48.602270 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 22:12:48.608786 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 22:12:48.611637 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 22:12:48.615532 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 22:12:48.621704 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 22:12:48.625447 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1464 22:12:48.628789 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1465 22:12:48.635173 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1466 22:12:48.638241 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 22:12:48.641795 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 22:12:48.648706 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 22:12:48.651897 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 22:12:48.654782 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 22:12:48.661499 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 22:12:48.664746 0 9 4 | B1->B0 | 2424 2a2a | 0 0 | (0 0) (1 1)
1473 22:12:48.667985 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1474 22:12:48.674827 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1475 22:12:48.677968 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1476 22:12:48.681426 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1477 22:12:48.684721 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1478 22:12:48.691188 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1479 22:12:48.694801 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1480 22:12:48.697961 0 10 4 | B1->B0 | 2b2b 2b2b | 0 0 | (0 1) (0 0)
1481 22:12:48.704603 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 22:12:48.707850 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 22:12:48.711128 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 22:12:48.718182 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 22:12:48.721285 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 22:12:48.725008 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 22:12:48.731213 0 11 0 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
1488 22:12:48.734842 0 11 4 | B1->B0 | 2e2e 3737 | 1 0 | (0 0) (1 1)
1489 22:12:48.738068 0 11 8 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
1490 22:12:48.744977 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1491 22:12:48.748557 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1492 22:12:48.751190 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1493 22:12:48.757968 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1494 22:12:48.761339 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 22:12:48.764775 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 22:12:48.771113 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1497 22:12:48.774941 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1498 22:12:48.777973 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1499 22:12:48.784600 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 22:12:48.787548 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 22:12:48.791351 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 22:12:48.797958 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 22:12:48.801020 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 22:12:48.804524 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 22:12:48.811708 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 22:12:48.814517 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 22:12:48.818200 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 22:12:48.821142 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 22:12:48.827936 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 22:12:48.831031 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 22:12:48.834489 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 22:12:48.841255 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1513 22:12:48.844882 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1514 22:12:48.848599 Total UI for P1: 0, mck2ui 16
1515 22:12:48.851006 best dqsien dly found for B0: ( 0, 14, 4)
1516 22:12:48.854669 Total UI for P1: 0, mck2ui 16
1517 22:12:48.857453 best dqsien dly found for B1: ( 0, 14, 4)
1518 22:12:48.860502 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1519 22:12:48.864574 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1520 22:12:48.865132
1521 22:12:48.867304 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1522 22:12:48.870963 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1523 22:12:48.874341 [Gating] SW calibration Done
1524 22:12:48.874934 ==
1525 22:12:48.877843 Dram Type= 6, Freq= 0, CH_1, rank 0
1526 22:12:48.883804 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1527 22:12:48.884386 ==
1528 22:12:48.884770 RX Vref Scan: 0
1529 22:12:48.885119
1530 22:12:48.887139 RX Vref 0 -> 0, step: 1
1531 22:12:48.887606
1532 22:12:48.890577 RX Delay -130 -> 252, step: 16
1533 22:12:48.893897 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1534 22:12:48.897313 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1535 22:12:48.900969 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1536 22:12:48.903997 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1537 22:12:48.910823 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1538 22:12:48.914787 iDelay=222, Bit 5, Center 101 (-2 ~ 205) 208
1539 22:12:48.917323 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1540 22:12:48.920316 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1541 22:12:48.923632 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1542 22:12:48.930474 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1543 22:12:48.933783 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1544 22:12:48.937279 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1545 22:12:48.940856 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1546 22:12:48.948592 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1547 22:12:48.950511 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1548 22:12:48.953358 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1549 22:12:48.953828 ==
1550 22:12:48.957682 Dram Type= 6, Freq= 0, CH_1, rank 0
1551 22:12:48.960017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1552 22:12:48.960488 ==
1553 22:12:48.963220 DQS Delay:
1554 22:12:48.963679 DQS0 = 0, DQS1 = 0
1555 22:12:48.966756 DQM Delay:
1556 22:12:48.967216 DQM0 = 90, DQM1 = 80
1557 22:12:48.967580 DQ Delay:
1558 22:12:48.970165 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1559 22:12:48.973976 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1560 22:12:48.977059 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1561 22:12:48.980517 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1562 22:12:48.981073
1563 22:12:48.981442
1564 22:12:48.983190 ==
1565 22:12:48.986652 Dram Type= 6, Freq= 0, CH_1, rank 0
1566 22:12:48.990435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1567 22:12:48.990994 ==
1568 22:12:48.991366
1569 22:12:48.991706
1570 22:12:48.993233 TX Vref Scan disable
1571 22:12:48.993702 == TX Byte 0 ==
1572 22:12:48.996559 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1573 22:12:49.003370 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1574 22:12:49.003938 == TX Byte 1 ==
1575 22:12:49.010487 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1576 22:12:49.013370 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1577 22:12:49.013933 ==
1578 22:12:49.016571 Dram Type= 6, Freq= 0, CH_1, rank 0
1579 22:12:49.020215 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1580 22:12:49.020815 ==
1581 22:12:49.033557 TX Vref=22, minBit 8, minWin=27, winSum=450
1582 22:12:49.037175 TX Vref=24, minBit 13, minWin=27, winSum=452
1583 22:12:49.040414 TX Vref=26, minBit 4, minWin=28, winSum=456
1584 22:12:49.043704 TX Vref=28, minBit 15, minWin=27, winSum=458
1585 22:12:49.047875 TX Vref=30, minBit 15, minWin=27, winSum=458
1586 22:12:49.053981 TX Vref=32, minBit 9, minWin=27, winSum=458
1587 22:12:49.057852 [TxChooseVref] Worse bit 4, Min win 28, Win sum 456, Final Vref 26
1588 22:12:49.058485
1589 22:12:49.061247 Final TX Range 1 Vref 26
1590 22:12:49.061706
1591 22:12:49.062292 ==
1592 22:12:49.064196 Dram Type= 6, Freq= 0, CH_1, rank 0
1593 22:12:49.067505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1594 22:12:49.068078 ==
1595 22:12:49.068452
1596 22:12:49.068794
1597 22:12:49.071017 TX Vref Scan disable
1598 22:12:49.074517 == TX Byte 0 ==
1599 22:12:49.078030 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1600 22:12:49.081018 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1601 22:12:49.084491 == TX Byte 1 ==
1602 22:12:49.088173 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1603 22:12:49.090694 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1604 22:12:49.094048
1605 22:12:49.094674 [DATLAT]
1606 22:12:49.095053 Freq=800, CH1 RK0
1607 22:12:49.095402
1608 22:12:49.097043 DATLAT Default: 0xa
1609 22:12:49.097507 0, 0xFFFF, sum = 0
1610 22:12:49.101093 1, 0xFFFF, sum = 0
1611 22:12:49.101666 2, 0xFFFF, sum = 0
1612 22:12:49.104447 3, 0xFFFF, sum = 0
1613 22:12:49.105019 4, 0xFFFF, sum = 0
1614 22:12:49.107908 5, 0xFFFF, sum = 0
1615 22:12:49.110638 6, 0xFFFF, sum = 0
1616 22:12:49.111220 7, 0xFFFF, sum = 0
1617 22:12:49.113947 8, 0xFFFF, sum = 0
1618 22:12:49.114569 9, 0x0, sum = 1
1619 22:12:49.114967 10, 0x0, sum = 2
1620 22:12:49.117608 11, 0x0, sum = 3
1621 22:12:49.118181 12, 0x0, sum = 4
1622 22:12:49.120636 best_step = 10
1623 22:12:49.121198
1624 22:12:49.121571 ==
1625 22:12:49.124280 Dram Type= 6, Freq= 0, CH_1, rank 0
1626 22:12:49.127013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1627 22:12:49.127521 ==
1628 22:12:49.130671 RX Vref Scan: 1
1629 22:12:49.131135
1630 22:12:49.131498 Set Vref Range= 32 -> 127
1631 22:12:49.131861
1632 22:12:49.134256 RX Vref 32 -> 127, step: 1
1633 22:12:49.134874
1634 22:12:49.136912 RX Delay -95 -> 252, step: 8
1635 22:12:49.137379
1636 22:12:49.140382 Set Vref, RX VrefLevel [Byte0]: 32
1637 22:12:49.144002 [Byte1]: 32
1638 22:12:49.144583
1639 22:12:49.147288 Set Vref, RX VrefLevel [Byte0]: 33
1640 22:12:49.150953 [Byte1]: 33
1641 22:12:49.154330
1642 22:12:49.154840 Set Vref, RX VrefLevel [Byte0]: 34
1643 22:12:49.157370 [Byte1]: 34
1644 22:12:49.161753
1645 22:12:49.162314 Set Vref, RX VrefLevel [Byte0]: 35
1646 22:12:49.164856 [Byte1]: 35
1647 22:12:49.169752
1648 22:12:49.170314 Set Vref, RX VrefLevel [Byte0]: 36
1649 22:12:49.172906 [Byte1]: 36
1650 22:12:49.177514
1651 22:12:49.178072 Set Vref, RX VrefLevel [Byte0]: 37
1652 22:12:49.180418 [Byte1]: 37
1653 22:12:49.184692
1654 22:12:49.185293 Set Vref, RX VrefLevel [Byte0]: 38
1655 22:12:49.188413 [Byte1]: 38
1656 22:12:49.192254
1657 22:12:49.192835 Set Vref, RX VrefLevel [Byte0]: 39
1658 22:12:49.195491 [Byte1]: 39
1659 22:12:49.200095
1660 22:12:49.200659 Set Vref, RX VrefLevel [Byte0]: 40
1661 22:12:49.202877 [Byte1]: 40
1662 22:12:49.208086
1663 22:12:49.208693 Set Vref, RX VrefLevel [Byte0]: 41
1664 22:12:49.210939 [Byte1]: 41
1665 22:12:49.215312
1666 22:12:49.215873 Set Vref, RX VrefLevel [Byte0]: 42
1667 22:12:49.218520 [Byte1]: 42
1668 22:12:49.223629
1669 22:12:49.224230 Set Vref, RX VrefLevel [Byte0]: 43
1670 22:12:49.226199 [Byte1]: 43
1671 22:12:49.230564
1672 22:12:49.231119 Set Vref, RX VrefLevel [Byte0]: 44
1673 22:12:49.233390 [Byte1]: 44
1674 22:12:49.237828
1675 22:12:49.238420 Set Vref, RX VrefLevel [Byte0]: 45
1676 22:12:49.241795 [Byte1]: 45
1677 22:12:49.245648
1678 22:12:49.246204 Set Vref, RX VrefLevel [Byte0]: 46
1679 22:12:49.248486 [Byte1]: 46
1680 22:12:49.253491
1681 22:12:49.254057 Set Vref, RX VrefLevel [Byte0]: 47
1682 22:12:49.256136 [Byte1]: 47
1683 22:12:49.260955
1684 22:12:49.261527 Set Vref, RX VrefLevel [Byte0]: 48
1685 22:12:49.263697 [Byte1]: 48
1686 22:12:49.268171
1687 22:12:49.268634 Set Vref, RX VrefLevel [Byte0]: 49
1688 22:12:49.272002 [Byte1]: 49
1689 22:12:49.276193
1690 22:12:49.276753 Set Vref, RX VrefLevel [Byte0]: 50
1691 22:12:49.282321 [Byte1]: 50
1692 22:12:49.282925
1693 22:12:49.285658 Set Vref, RX VrefLevel [Byte0]: 51
1694 22:12:49.289016 [Byte1]: 51
1695 22:12:49.289580
1696 22:12:49.292214 Set Vref, RX VrefLevel [Byte0]: 52
1697 22:12:49.295438 [Byte1]: 52
1698 22:12:49.295978
1699 22:12:49.298734 Set Vref, RX VrefLevel [Byte0]: 53
1700 22:12:49.302769 [Byte1]: 53
1701 22:12:49.307197
1702 22:12:49.307753 Set Vref, RX VrefLevel [Byte0]: 54
1703 22:12:49.309658 [Byte1]: 54
1704 22:12:49.313891
1705 22:12:49.314521 Set Vref, RX VrefLevel [Byte0]: 55
1706 22:12:49.317825 [Byte1]: 55
1707 22:12:49.321740
1708 22:12:49.322300 Set Vref, RX VrefLevel [Byte0]: 56
1709 22:12:49.324976 [Byte1]: 56
1710 22:12:49.329011
1711 22:12:49.329633 Set Vref, RX VrefLevel [Byte0]: 57
1712 22:12:49.332231 [Byte1]: 57
1713 22:12:49.336714
1714 22:12:49.337272 Set Vref, RX VrefLevel [Byte0]: 58
1715 22:12:49.339765 [Byte1]: 58
1716 22:12:49.345096
1717 22:12:49.345712 Set Vref, RX VrefLevel [Byte0]: 59
1718 22:12:49.348211 [Byte1]: 59
1719 22:12:49.352303
1720 22:12:49.352866 Set Vref, RX VrefLevel [Byte0]: 60
1721 22:12:49.354893 [Byte1]: 60
1722 22:12:49.359295
1723 22:12:49.359857 Set Vref, RX VrefLevel [Byte0]: 61
1724 22:12:49.363175 [Byte1]: 61
1725 22:12:49.367006
1726 22:12:49.367471 Set Vref, RX VrefLevel [Byte0]: 62
1727 22:12:49.370855 [Byte1]: 62
1728 22:12:49.374564
1729 22:12:49.375128 Set Vref, RX VrefLevel [Byte0]: 63
1730 22:12:49.377920 [Byte1]: 63
1731 22:12:49.382109
1732 22:12:49.382730 Set Vref, RX VrefLevel [Byte0]: 64
1733 22:12:49.385807 [Byte1]: 64
1734 22:12:49.389909
1735 22:12:49.390518 Set Vref, RX VrefLevel [Byte0]: 65
1736 22:12:49.393072 [Byte1]: 65
1737 22:12:49.397241
1738 22:12:49.397709 Set Vref, RX VrefLevel [Byte0]: 66
1739 22:12:49.400415 [Byte1]: 66
1740 22:12:49.405084
1741 22:12:49.405644 Set Vref, RX VrefLevel [Byte0]: 67
1742 22:12:49.408470 [Byte1]: 67
1743 22:12:49.413051
1744 22:12:49.413617 Set Vref, RX VrefLevel [Byte0]: 68
1745 22:12:49.415950 [Byte1]: 68
1746 22:12:49.420854
1747 22:12:49.421425 Set Vref, RX VrefLevel [Byte0]: 69
1748 22:12:49.423545 [Byte1]: 69
1749 22:12:49.427599
1750 22:12:49.428161 Set Vref, RX VrefLevel [Byte0]: 70
1751 22:12:49.431007 [Byte1]: 70
1752 22:12:49.435317
1753 22:12:49.435872 Set Vref, RX VrefLevel [Byte0]: 71
1754 22:12:49.438335 [Byte1]: 71
1755 22:12:49.443026
1756 22:12:49.443490 Set Vref, RX VrefLevel [Byte0]: 72
1757 22:12:49.447228 [Byte1]: 72
1758 22:12:49.450688
1759 22:12:49.451255 Set Vref, RX VrefLevel [Byte0]: 73
1760 22:12:49.453988 [Byte1]: 73
1761 22:12:49.458032
1762 22:12:49.458531 Set Vref, RX VrefLevel [Byte0]: 74
1763 22:12:49.461311 [Byte1]: 74
1764 22:12:49.465849
1765 22:12:49.466319 Set Vref, RX VrefLevel [Byte0]: 75
1766 22:12:49.469331 [Byte1]: 75
1767 22:12:49.473309
1768 22:12:49.473877 Set Vref, RX VrefLevel [Byte0]: 76
1769 22:12:49.476722 [Byte1]: 76
1770 22:12:49.481273
1771 22:12:49.481839 Set Vref, RX VrefLevel [Byte0]: 77
1772 22:12:49.484557 [Byte1]: 77
1773 22:12:49.489002
1774 22:12:49.489565 Set Vref, RX VrefLevel [Byte0]: 78
1775 22:12:49.492697 [Byte1]: 78
1776 22:12:49.496156
1777 22:12:49.496620 Final RX Vref Byte 0 = 50 to rank0
1778 22:12:49.499659 Final RX Vref Byte 1 = 63 to rank0
1779 22:12:49.502918 Final RX Vref Byte 0 = 50 to rank1
1780 22:12:49.506549 Final RX Vref Byte 1 = 63 to rank1==
1781 22:12:49.509647 Dram Type= 6, Freq= 0, CH_1, rank 0
1782 22:12:49.516267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1783 22:12:49.516838 ==
1784 22:12:49.517210 DQS Delay:
1785 22:12:49.519052 DQS0 = 0, DQS1 = 0
1786 22:12:49.519520 DQM Delay:
1787 22:12:49.519893 DQM0 = 92, DQM1 = 83
1788 22:12:49.522745 DQ Delay:
1789 22:12:49.525908 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =88
1790 22:12:49.529715 DQ4 =92, DQ5 =100, DQ6 =100, DQ7 =88
1791 22:12:49.532757 DQ8 =72, DQ9 =72, DQ10 =88, DQ11 =80
1792 22:12:49.536321 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =88
1793 22:12:49.536885
1794 22:12:49.537253
1795 22:12:49.542777 [DQSOSCAuto] RK0, (LSB)MR18= 0x3250, (MSB)MR19= 0x606, tDQSOscB0 = 389 ps tDQSOscB1 = 397 ps
1796 22:12:49.546645 CH1 RK0: MR19=606, MR18=3250
1797 22:12:49.552623 CH1_RK0: MR19=0x606, MR18=0x3250, DQSOSC=389, MR23=63, INC=97, DEC=65
1798 22:12:49.553192
1799 22:12:49.555754 ----->DramcWriteLeveling(PI) begin...
1800 22:12:49.556229 ==
1801 22:12:49.559128 Dram Type= 6, Freq= 0, CH_1, rank 1
1802 22:12:49.562435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1803 22:12:49.563006 ==
1804 22:12:49.565755 Write leveling (Byte 0): 31 => 31
1805 22:12:49.569136 Write leveling (Byte 1): 31 => 31
1806 22:12:49.572136 DramcWriteLeveling(PI) end<-----
1807 22:12:49.572603
1808 22:12:49.572973 ==
1809 22:12:49.576512 Dram Type= 6, Freq= 0, CH_1, rank 1
1810 22:12:49.578827 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1811 22:12:49.579292 ==
1812 22:12:49.583000 [Gating] SW mode calibration
1813 22:12:49.589299 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1814 22:12:49.595468 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1815 22:12:49.599279 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1816 22:12:49.606029 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1817 22:12:49.608984 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 22:12:49.612291 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 22:12:49.615620 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 22:12:49.622079 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 22:12:49.626281 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 22:12:49.629136 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 22:12:49.635822 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 22:12:49.638721 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 22:12:49.642298 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 22:12:49.649393 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 22:12:49.652984 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 22:12:49.655575 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 22:12:49.662401 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 22:12:49.665249 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 22:12:49.669081 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 22:12:49.675459 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1833 22:12:49.678791 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 22:12:49.682144 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 22:12:49.689627 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 22:12:49.691995 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 22:12:49.695113 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 22:12:49.701940 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 22:12:49.705957 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 22:12:49.708679 0 9 4 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
1841 22:12:49.715147 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (0 0) (1 1)
1842 22:12:49.718950 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1843 22:12:49.721661 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1844 22:12:49.728557 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1845 22:12:49.732083 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1846 22:12:49.734924 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1847 22:12:49.741530 0 10 0 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 0)
1848 22:12:49.745068 0 10 4 | B1->B0 | 2f2f 2f2f | 0 0 | (0 0) (0 0)
1849 22:12:49.748646 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 22:12:49.754790 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 22:12:49.758649 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 22:12:49.761840 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 22:12:49.768559 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 22:12:49.771611 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 22:12:49.774579 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 22:12:49.781616 0 11 4 | B1->B0 | 3030 2f2f | 0 0 | (0 0) (0 0)
1857 22:12:49.784851 0 11 8 | B1->B0 | 4444 4444 | 0 0 | (0 0) (0 0)
1858 22:12:49.788166 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1859 22:12:49.791647 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1860 22:12:49.798405 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1861 22:12:49.801098 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1862 22:12:49.804453 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1863 22:12:49.811185 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1864 22:12:49.814899 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1865 22:12:49.818021 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 22:12:49.824574 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 22:12:49.827862 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 22:12:49.831611 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 22:12:49.837764 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 22:12:49.841691 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 22:12:49.845518 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 22:12:49.851856 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 22:12:49.854296 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 22:12:49.857647 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 22:12:49.864294 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 22:12:49.867501 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 22:12:49.870882 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 22:12:49.878067 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 22:12:49.881296 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1880 22:12:49.884865 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1881 22:12:49.891407 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1882 22:12:49.891993 Total UI for P1: 0, mck2ui 16
1883 22:12:49.897685 best dqsien dly found for B0: ( 0, 14, 6)
1884 22:12:49.898463 Total UI for P1: 0, mck2ui 16
1885 22:12:49.901466 best dqsien dly found for B1: ( 0, 14, 4)
1886 22:12:49.908439 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1887 22:12:49.910791 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1888 22:12:49.911266
1889 22:12:49.914525 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1890 22:12:49.918166 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1891 22:12:49.920898 [Gating] SW calibration Done
1892 22:12:49.921457 ==
1893 22:12:49.924857 Dram Type= 6, Freq= 0, CH_1, rank 1
1894 22:12:49.927649 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1895 22:12:49.928123 ==
1896 22:12:49.928499 RX Vref Scan: 0
1897 22:12:49.931231
1898 22:12:49.931794 RX Vref 0 -> 0, step: 1
1899 22:12:49.932176
1900 22:12:49.934454 RX Delay -130 -> 252, step: 16
1901 22:12:49.938108 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1902 22:12:49.943917 iDelay=206, Bit 1, Center 85 (-18 ~ 189) 208
1903 22:12:49.947993 iDelay=206, Bit 2, Center 85 (-18 ~ 189) 208
1904 22:12:49.951010 iDelay=206, Bit 3, Center 85 (-18 ~ 189) 208
1905 22:12:49.954070 iDelay=206, Bit 4, Center 85 (-18 ~ 189) 208
1906 22:12:49.958208 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1907 22:12:49.964084 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1908 22:12:49.967505 iDelay=206, Bit 7, Center 85 (-18 ~ 189) 208
1909 22:12:49.970529 iDelay=206, Bit 8, Center 61 (-50 ~ 173) 224
1910 22:12:49.973916 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
1911 22:12:49.977576 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1912 22:12:49.983849 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1913 22:12:49.987350 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1914 22:12:49.991156 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
1915 22:12:49.994256 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1916 22:12:49.997650 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
1917 22:12:49.998214 ==
1918 22:12:50.000726 Dram Type= 6, Freq= 0, CH_1, rank 1
1919 22:12:50.007121 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1920 22:12:50.007685 ==
1921 22:12:50.008063 DQS Delay:
1922 22:12:50.010755 DQS0 = 0, DQS1 = 0
1923 22:12:50.011314 DQM Delay:
1924 22:12:50.013818 DQM0 = 88, DQM1 = 83
1925 22:12:50.014491 DQ Delay:
1926 22:12:50.017674 DQ0 =93, DQ1 =85, DQ2 =85, DQ3 =85
1927 22:12:50.020340 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =85
1928 22:12:50.023917 DQ8 =61, DQ9 =77, DQ10 =85, DQ11 =77
1929 22:12:50.026645 DQ12 =93, DQ13 =93, DQ14 =85, DQ15 =93
1930 22:12:50.027119
1931 22:12:50.027491
1932 22:12:50.027835 ==
1933 22:12:50.030229 Dram Type= 6, Freq= 0, CH_1, rank 1
1934 22:12:50.033796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1935 22:12:50.034409 ==
1936 22:12:50.034805
1937 22:12:50.035156
1938 22:12:50.036890 TX Vref Scan disable
1939 22:12:50.040153 == TX Byte 0 ==
1940 22:12:50.043681 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1941 22:12:50.046701 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1942 22:12:50.050497 == TX Byte 1 ==
1943 22:12:50.053548 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1944 22:12:50.056679 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1945 22:12:50.057173 ==
1946 22:12:50.060673 Dram Type= 6, Freq= 0, CH_1, rank 1
1947 22:12:50.063328 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1948 22:12:50.066743 ==
1949 22:12:50.078063 TX Vref=22, minBit 13, minWin=27, winSum=448
1950 22:12:50.081228 TX Vref=24, minBit 12, minWin=27, winSum=450
1951 22:12:50.084538 TX Vref=26, minBit 8, minWin=27, winSum=451
1952 22:12:50.087680 TX Vref=28, minBit 8, minWin=28, winSum=458
1953 22:12:50.091177 TX Vref=30, minBit 15, minWin=27, winSum=455
1954 22:12:50.098700 TX Vref=32, minBit 0, minWin=28, winSum=457
1955 22:12:50.101535 [TxChooseVref] Worse bit 8, Min win 28, Win sum 458, Final Vref 28
1956 22:12:50.102098
1957 22:12:50.104934 Final TX Range 1 Vref 28
1958 22:12:50.105503
1959 22:12:50.105877 ==
1960 22:12:50.108180 Dram Type= 6, Freq= 0, CH_1, rank 1
1961 22:12:50.111618 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1962 22:12:50.114389 ==
1963 22:12:50.114868
1964 22:12:50.115243
1965 22:12:50.115592 TX Vref Scan disable
1966 22:12:50.117818 == TX Byte 0 ==
1967 22:12:50.121392 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1968 22:12:50.127914 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1969 22:12:50.128469 == TX Byte 1 ==
1970 22:12:50.132325 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1971 22:12:50.138126 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1972 22:12:50.138755
1973 22:12:50.139264 [DATLAT]
1974 22:12:50.139764 Freq=800, CH1 RK1
1975 22:12:50.140131
1976 22:12:50.141198 DATLAT Default: 0xa
1977 22:12:50.141672 0, 0xFFFF, sum = 0
1978 22:12:50.144546 1, 0xFFFF, sum = 0
1979 22:12:50.145023 2, 0xFFFF, sum = 0
1980 22:12:50.148266 3, 0xFFFF, sum = 0
1981 22:12:50.151536 4, 0xFFFF, sum = 0
1982 22:12:50.152109 5, 0xFFFF, sum = 0
1983 22:12:50.154588 6, 0xFFFF, sum = 0
1984 22:12:50.155144 7, 0xFFFF, sum = 0
1985 22:12:50.157650 8, 0xFFFF, sum = 0
1986 22:12:50.158127 9, 0x0, sum = 1
1987 22:12:50.161374 10, 0x0, sum = 2
1988 22:12:50.161953 11, 0x0, sum = 3
1989 22:12:50.162341 12, 0x0, sum = 4
1990 22:12:50.164745 best_step = 10
1991 22:12:50.165298
1992 22:12:50.165730 ==
1993 22:12:50.168004 Dram Type= 6, Freq= 0, CH_1, rank 1
1994 22:12:50.171034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1995 22:12:50.171512 ==
1996 22:12:50.175082 RX Vref Scan: 0
1997 22:12:50.175643
1998 22:12:50.176024 RX Vref 0 -> 0, step: 1
1999 22:12:50.176378
2000 22:12:50.177425 RX Delay -95 -> 252, step: 8
2001 22:12:50.184831 iDelay=209, Bit 0, Center 92 (-7 ~ 192) 200
2002 22:12:50.187906 iDelay=209, Bit 1, Center 84 (-15 ~ 184) 200
2003 22:12:50.191702 iDelay=209, Bit 2, Center 80 (-23 ~ 184) 208
2004 22:12:50.194730 iDelay=209, Bit 3, Center 88 (-15 ~ 192) 208
2005 22:12:50.198542 iDelay=209, Bit 4, Center 96 (-7 ~ 200) 208
2006 22:12:50.205401 iDelay=209, Bit 5, Center 100 (-7 ~ 208) 216
2007 22:12:50.208640 iDelay=209, Bit 6, Center 96 (-7 ~ 200) 208
2008 22:12:50.211560 iDelay=209, Bit 7, Center 88 (-15 ~ 192) 208
2009 22:12:50.215193 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2010 22:12:50.218249 iDelay=209, Bit 9, Center 76 (-31 ~ 184) 216
2011 22:12:50.224770 iDelay=209, Bit 10, Center 88 (-23 ~ 200) 224
2012 22:12:50.227868 iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224
2013 22:12:50.231085 iDelay=209, Bit 12, Center 88 (-23 ~ 200) 224
2014 22:12:50.234556 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2015 22:12:50.238072 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2016 22:12:50.244433 iDelay=209, Bit 15, Center 96 (-15 ~ 208) 224
2017 22:12:50.244911 ==
2018 22:12:50.247748 Dram Type= 6, Freq= 0, CH_1, rank 1
2019 22:12:50.251195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2020 22:12:50.251670 ==
2021 22:12:50.252046 DQS Delay:
2022 22:12:50.254427 DQS0 = 0, DQS1 = 0
2023 22:12:50.254901 DQM Delay:
2024 22:12:50.257645 DQM0 = 90, DQM1 = 84
2025 22:12:50.258253 DQ Delay:
2026 22:12:50.261095 DQ0 =92, DQ1 =84, DQ2 =80, DQ3 =88
2027 22:12:50.264529 DQ4 =96, DQ5 =100, DQ6 =96, DQ7 =88
2028 22:12:50.267946 DQ8 =68, DQ9 =76, DQ10 =88, DQ11 =80
2029 22:12:50.270926 DQ12 =88, DQ13 =88, DQ14 =88, DQ15 =96
2030 22:12:50.271399
2031 22:12:50.271771
2032 22:12:50.278396 [DQSOSCAuto] RK1, (LSB)MR18= 0x3e13, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 394 ps
2033 22:12:50.281182 CH1 RK1: MR19=606, MR18=3E13
2034 22:12:50.287852 CH1_RK1: MR19=0x606, MR18=0x3E13, DQSOSC=394, MR23=63, INC=95, DEC=63
2035 22:12:50.291253 [RxdqsGatingPostProcess] freq 800
2036 22:12:50.297882 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2037 22:12:50.301908 Pre-setting of DQS Precalculation
2038 22:12:50.304253 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2039 22:12:50.311260 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2040 22:12:50.318139 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2041 22:12:50.318754
2042 22:12:50.320956
2043 22:12:50.321514 [Calibration Summary] 1600 Mbps
2044 22:12:50.324242 CH 0, Rank 0
2045 22:12:50.324806 SW Impedance : PASS
2046 22:12:50.327805 DUTY Scan : NO K
2047 22:12:50.330717 ZQ Calibration : PASS
2048 22:12:50.331278 Jitter Meter : NO K
2049 22:12:50.333895 CBT Training : PASS
2050 22:12:50.337591 Write leveling : PASS
2051 22:12:50.338186 RX DQS gating : PASS
2052 22:12:50.340564 RX DQ/DQS(RDDQC) : PASS
2053 22:12:50.344070 TX DQ/DQS : PASS
2054 22:12:50.344703 RX DATLAT : PASS
2055 22:12:50.347585 RX DQ/DQS(Engine): PASS
2056 22:12:50.350765 TX OE : NO K
2057 22:12:50.351238 All Pass.
2058 22:12:50.351617
2059 22:12:50.351968 CH 0, Rank 1
2060 22:12:50.354536 SW Impedance : PASS
2061 22:12:50.357122 DUTY Scan : NO K
2062 22:12:50.357672 ZQ Calibration : PASS
2063 22:12:50.360998 Jitter Meter : NO K
2064 22:12:50.361562 CBT Training : PASS
2065 22:12:50.364467 Write leveling : PASS
2066 22:12:50.367811 RX DQS gating : PASS
2067 22:12:50.368378 RX DQ/DQS(RDDQC) : PASS
2068 22:12:50.370714 TX DQ/DQS : PASS
2069 22:12:50.373961 RX DATLAT : PASS
2070 22:12:50.374575 RX DQ/DQS(Engine): PASS
2071 22:12:50.377488 TX OE : NO K
2072 22:12:50.378055 All Pass.
2073 22:12:50.378481
2074 22:12:50.380772 CH 1, Rank 0
2075 22:12:50.381332 SW Impedance : PASS
2076 22:12:50.384421 DUTY Scan : NO K
2077 22:12:50.387057 ZQ Calibration : PASS
2078 22:12:50.387556 Jitter Meter : NO K
2079 22:12:50.390923 CBT Training : PASS
2080 22:12:50.394194 Write leveling : PASS
2081 22:12:50.394813 RX DQS gating : PASS
2082 22:12:50.397612 RX DQ/DQS(RDDQC) : PASS
2083 22:12:50.400489 TX DQ/DQS : PASS
2084 22:12:50.401057 RX DATLAT : PASS
2085 22:12:50.404497 RX DQ/DQS(Engine): PASS
2086 22:12:50.407191 TX OE : NO K
2087 22:12:50.407757 All Pass.
2088 22:12:50.408138
2089 22:12:50.408483 CH 1, Rank 1
2090 22:12:50.410980 SW Impedance : PASS
2091 22:12:50.413697 DUTY Scan : NO K
2092 22:12:50.414259 ZQ Calibration : PASS
2093 22:12:50.417455 Jitter Meter : NO K
2094 22:12:50.420835 CBT Training : PASS
2095 22:12:50.421400 Write leveling : PASS
2096 22:12:50.424340 RX DQS gating : PASS
2097 22:12:50.424908 RX DQ/DQS(RDDQC) : PASS
2098 22:12:50.427096 TX DQ/DQS : PASS
2099 22:12:50.430856 RX DATLAT : PASS
2100 22:12:50.431423 RX DQ/DQS(Engine): PASS
2101 22:12:50.433400 TX OE : NO K
2102 22:12:50.433872 All Pass.
2103 22:12:50.434248
2104 22:12:50.436834 DramC Write-DBI off
2105 22:12:50.439987 PER_BANK_REFRESH: Hybrid Mode
2106 22:12:50.440487 TX_TRACKING: ON
2107 22:12:50.443208 [GetDramInforAfterCalByMRR] Vendor 6.
2108 22:12:50.447288 [GetDramInforAfterCalByMRR] Revision 606.
2109 22:12:50.449888 [GetDramInforAfterCalByMRR] Revision 2 0.
2110 22:12:50.453737 MR0 0x3b3b
2111 22:12:50.454296 MR8 0x5151
2112 22:12:50.456834 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2113 22:12:50.457305
2114 22:12:50.460300 MR0 0x3b3b
2115 22:12:50.460891 MR8 0x5151
2116 22:12:50.463238 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2117 22:12:50.463729
2118 22:12:50.473124 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2119 22:12:50.476604 [FAST_K] Save calibration result to emmc
2120 22:12:50.479925 [FAST_K] Save calibration result to emmc
2121 22:12:50.483165 dram_init: config_dvfs: 1
2122 22:12:50.486555 dramc_set_vcore_voltage set vcore to 662500
2123 22:12:50.487116 Read voltage for 1200, 2
2124 22:12:50.490031 Vio18 = 0
2125 22:12:50.490644 Vcore = 662500
2126 22:12:50.491029 Vdram = 0
2127 22:12:50.493911 Vddq = 0
2128 22:12:50.494522 Vmddr = 0
2129 22:12:50.496839 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2130 22:12:50.503311 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2131 22:12:50.506986 MEM_TYPE=3, freq_sel=15
2132 22:12:50.510212 sv_algorithm_assistance_LP4_1600
2133 22:12:50.513528 ============ PULL DRAM RESETB DOWN ============
2134 22:12:50.516802 ========== PULL DRAM RESETB DOWN end =========
2135 22:12:50.523123 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2136 22:12:50.526656 ===================================
2137 22:12:50.527276 LPDDR4 DRAM CONFIGURATION
2138 22:12:50.530257 ===================================
2139 22:12:50.533221 EX_ROW_EN[0] = 0x0
2140 22:12:50.533781 EX_ROW_EN[1] = 0x0
2141 22:12:50.537284 LP4Y_EN = 0x0
2142 22:12:50.537849 WORK_FSP = 0x0
2143 22:12:50.539691 WL = 0x4
2144 22:12:50.543007 RL = 0x4
2145 22:12:50.543480 BL = 0x2
2146 22:12:50.546487 RPST = 0x0
2147 22:12:50.547045 RD_PRE = 0x0
2148 22:12:50.549820 WR_PRE = 0x1
2149 22:12:50.550422 WR_PST = 0x0
2150 22:12:50.553065 DBI_WR = 0x0
2151 22:12:50.553631 DBI_RD = 0x0
2152 22:12:50.556509 OTF = 0x1
2153 22:12:50.559974 ===================================
2154 22:12:50.562667 ===================================
2155 22:12:50.563147 ANA top config
2156 22:12:50.565890 ===================================
2157 22:12:50.569525 DLL_ASYNC_EN = 0
2158 22:12:50.572604 ALL_SLAVE_EN = 0
2159 22:12:50.573081 NEW_RANK_MODE = 1
2160 22:12:50.576257 DLL_IDLE_MODE = 1
2161 22:12:50.579210 LP45_APHY_COMB_EN = 1
2162 22:12:50.582645 TX_ODT_DIS = 1
2163 22:12:50.585931 NEW_8X_MODE = 1
2164 22:12:50.589538 ===================================
2165 22:12:50.592775 ===================================
2166 22:12:50.593345 data_rate = 2400
2167 22:12:50.596310 CKR = 1
2168 22:12:50.599441 DQ_P2S_RATIO = 8
2169 22:12:50.603009 ===================================
2170 22:12:50.606215 CA_P2S_RATIO = 8
2171 22:12:50.609535 DQ_CA_OPEN = 0
2172 22:12:50.612634 DQ_SEMI_OPEN = 0
2173 22:12:50.613109 CA_SEMI_OPEN = 0
2174 22:12:50.616247 CA_FULL_RATE = 0
2175 22:12:50.619269 DQ_CKDIV4_EN = 0
2176 22:12:50.622714 CA_CKDIV4_EN = 0
2177 22:12:50.626344 CA_PREDIV_EN = 0
2178 22:12:50.629514 PH8_DLY = 17
2179 22:12:50.630082 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2180 22:12:50.633089 DQ_AAMCK_DIV = 4
2181 22:12:50.636450 CA_AAMCK_DIV = 4
2182 22:12:50.639466 CA_ADMCK_DIV = 4
2183 22:12:50.642548 DQ_TRACK_CA_EN = 0
2184 22:12:50.645984 CA_PICK = 1200
2185 22:12:50.649457 CA_MCKIO = 1200
2186 22:12:50.650022 MCKIO_SEMI = 0
2187 22:12:50.652565 PLL_FREQ = 2366
2188 22:12:50.656165 DQ_UI_PI_RATIO = 32
2189 22:12:50.658844 CA_UI_PI_RATIO = 0
2190 22:12:50.662708 ===================================
2191 22:12:50.665812 ===================================
2192 22:12:50.669663 memory_type:LPDDR4
2193 22:12:50.670224 GP_NUM : 10
2194 22:12:50.672592 SRAM_EN : 1
2195 22:12:50.673064 MD32_EN : 0
2196 22:12:50.676031 ===================================
2197 22:12:50.679220 [ANA_INIT] >>>>>>>>>>>>>>
2198 22:12:50.682652 <<<<<< [CONFIGURE PHASE]: ANA_TX
2199 22:12:50.685944 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2200 22:12:50.689082 ===================================
2201 22:12:50.692551 data_rate = 2400,PCW = 0X5b00
2202 22:12:50.695672 ===================================
2203 22:12:50.699570 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2204 22:12:50.705651 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2205 22:12:50.709067 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2206 22:12:50.715859 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2207 22:12:50.719009 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2208 22:12:50.722613 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2209 22:12:50.723182 [ANA_INIT] flow start
2210 22:12:50.726015 [ANA_INIT] PLL >>>>>>>>
2211 22:12:50.728966 [ANA_INIT] PLL <<<<<<<<
2212 22:12:50.729528 [ANA_INIT] MIDPI >>>>>>>>
2213 22:12:50.732155 [ANA_INIT] MIDPI <<<<<<<<
2214 22:12:50.735361 [ANA_INIT] DLL >>>>>>>>
2215 22:12:50.735926 [ANA_INIT] DLL <<<<<<<<
2216 22:12:50.739073 [ANA_INIT] flow end
2217 22:12:50.742003 ============ LP4 DIFF to SE enter ============
2218 22:12:50.749383 ============ LP4 DIFF to SE exit ============
2219 22:12:50.749951 [ANA_INIT] <<<<<<<<<<<<<
2220 22:12:50.751914 [Flow] Enable top DCM control >>>>>
2221 22:12:50.756115 [Flow] Enable top DCM control <<<<<
2222 22:12:50.758616 Enable DLL master slave shuffle
2223 22:12:50.765700 ==============================================================
2224 22:12:50.766265 Gating Mode config
2225 22:12:50.772090 ==============================================================
2226 22:12:50.775603 Config description:
2227 22:12:50.782231 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2228 22:12:50.788493 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2229 22:12:50.795662 SELPH_MODE 0: By rank 1: By Phase
2230 22:12:50.802026 ==============================================================
2231 22:12:50.802738 GAT_TRACK_EN = 1
2232 22:12:50.806148 RX_GATING_MODE = 2
2233 22:12:50.808745 RX_GATING_TRACK_MODE = 2
2234 22:12:50.811836 SELPH_MODE = 1
2235 22:12:50.815738 PICG_EARLY_EN = 1
2236 22:12:50.818785 VALID_LAT_VALUE = 1
2237 22:12:50.825079 ==============================================================
2238 22:12:50.829103 Enter into Gating configuration >>>>
2239 22:12:50.831738 Exit from Gating configuration <<<<
2240 22:12:50.835139 Enter into DVFS_PRE_config >>>>>
2241 22:12:50.844923 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2242 22:12:50.848272 Exit from DVFS_PRE_config <<<<<
2243 22:12:50.851646 Enter into PICG configuration >>>>
2244 22:12:50.855043 Exit from PICG configuration <<<<
2245 22:12:50.857987 [RX_INPUT] configuration >>>>>
2246 22:12:50.861714 [RX_INPUT] configuration <<<<<
2247 22:12:50.865019 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2248 22:12:50.871288 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2249 22:12:50.878445 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2250 22:12:50.881867 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2251 22:12:50.888483 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2252 22:12:50.894295 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2253 22:12:50.898151 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2254 22:12:50.901432 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2255 22:12:50.908043 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2256 22:12:50.910968 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2257 22:12:50.914677 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2258 22:12:50.921634 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2259 22:12:50.924653 ===================================
2260 22:12:50.925228 LPDDR4 DRAM CONFIGURATION
2261 22:12:50.927665 ===================================
2262 22:12:50.931227 EX_ROW_EN[0] = 0x0
2263 22:12:50.934452 EX_ROW_EN[1] = 0x0
2264 22:12:50.935021 LP4Y_EN = 0x0
2265 22:12:50.937708 WORK_FSP = 0x0
2266 22:12:50.938284 WL = 0x4
2267 22:12:50.941235 RL = 0x4
2268 22:12:50.941814 BL = 0x2
2269 22:12:50.944542 RPST = 0x0
2270 22:12:50.945118 RD_PRE = 0x0
2271 22:12:50.947554 WR_PRE = 0x1
2272 22:12:50.948022 WR_PST = 0x0
2273 22:12:50.951140 DBI_WR = 0x0
2274 22:12:50.951733 DBI_RD = 0x0
2275 22:12:50.955071 OTF = 0x1
2276 22:12:50.957825 ===================================
2277 22:12:50.961572 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2278 22:12:50.964567 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2279 22:12:50.971081 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2280 22:12:50.973996 ===================================
2281 22:12:50.974554 LPDDR4 DRAM CONFIGURATION
2282 22:12:50.977669 ===================================
2283 22:12:50.981039 EX_ROW_EN[0] = 0x10
2284 22:12:50.981603 EX_ROW_EN[1] = 0x0
2285 22:12:50.984718 LP4Y_EN = 0x0
2286 22:12:50.988254 WORK_FSP = 0x0
2287 22:12:50.988779 WL = 0x4
2288 22:12:50.990537 RL = 0x4
2289 22:12:50.991009 BL = 0x2
2290 22:12:50.994748 RPST = 0x0
2291 22:12:50.995312 RD_PRE = 0x0
2292 22:12:50.997247 WR_PRE = 0x1
2293 22:12:50.997745 WR_PST = 0x0
2294 22:12:51.000512 DBI_WR = 0x0
2295 22:12:51.000969 DBI_RD = 0x0
2296 22:12:51.003811 OTF = 0x1
2297 22:12:51.007032 ===================================
2298 22:12:51.013931 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2299 22:12:51.014419 ==
2300 22:12:51.017884 Dram Type= 6, Freq= 0, CH_0, rank 0
2301 22:12:51.020545 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2302 22:12:51.021003 ==
2303 22:12:51.024520 [Duty_Offset_Calibration]
2304 22:12:51.025080 B0:2 B1:0 CA:1
2305 22:12:51.025442
2306 22:12:51.026915 [DutyScan_Calibration_Flow] k_type=0
2307 22:12:51.036517
2308 22:12:51.037068 ==CLK 0==
2309 22:12:51.040051 Final CLK duty delay cell = -4
2310 22:12:51.043344 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2311 22:12:51.046421 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2312 22:12:51.049747 [-4] AVG Duty = 4953%(X100)
2313 22:12:51.050289
2314 22:12:51.053521 CH0 CLK Duty spec in!! Max-Min= 156%
2315 22:12:51.056029 [DutyScan_Calibration_Flow] ====Done====
2316 22:12:51.056425
2317 22:12:51.059494 [DutyScan_Calibration_Flow] k_type=1
2318 22:12:51.075050
2319 22:12:51.075598 ==DQS 0 ==
2320 22:12:51.078375 Final DQS duty delay cell = 0
2321 22:12:51.081933 [0] MAX Duty = 5187%(X100), DQS PI = 30
2322 22:12:51.085359 [0] MIN Duty = 4938%(X100), DQS PI = 2
2323 22:12:51.088282 [0] AVG Duty = 5062%(X100)
2324 22:12:51.088740
2325 22:12:51.089184 ==DQS 1 ==
2326 22:12:51.091908 Final DQS duty delay cell = -4
2327 22:12:51.094978 [-4] MAX Duty = 5124%(X100), DQS PI = 32
2328 22:12:51.098589 [-4] MIN Duty = 4938%(X100), DQS PI = 8
2329 22:12:51.101655 [-4] AVG Duty = 5031%(X100)
2330 22:12:51.102216
2331 22:12:51.104793 CH0 DQS 0 Duty spec in!! Max-Min= 249%
2332 22:12:51.105343
2333 22:12:51.108762 CH0 DQS 1 Duty spec in!! Max-Min= 186%
2334 22:12:51.111855 [DutyScan_Calibration_Flow] ====Done====
2335 22:12:51.112443
2336 22:12:51.114794 [DutyScan_Calibration_Flow] k_type=3
2337 22:12:51.131411
2338 22:12:51.131976 ==DQM 0 ==
2339 22:12:51.134994 Final DQM duty delay cell = 0
2340 22:12:51.138048 [0] MAX Duty = 5062%(X100), DQS PI = 24
2341 22:12:51.141269 [0] MIN Duty = 4844%(X100), DQS PI = 0
2342 22:12:51.141819 [0] AVG Duty = 4953%(X100)
2343 22:12:51.145269
2344 22:12:51.145815 ==DQM 1 ==
2345 22:12:51.147948 Final DQM duty delay cell = -4
2346 22:12:51.151308 [-4] MAX Duty = 5000%(X100), DQS PI = 32
2347 22:12:51.155150 [-4] MIN Duty = 4813%(X100), DQS PI = 14
2348 22:12:51.158201 [-4] AVG Duty = 4906%(X100)
2349 22:12:51.158824
2350 22:12:51.160857 CH0 DQM 0 Duty spec in!! Max-Min= 218%
2351 22:12:51.161312
2352 22:12:51.164472 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2353 22:12:51.167994 [DutyScan_Calibration_Flow] ====Done====
2354 22:12:51.168549
2355 22:12:51.171086 [DutyScan_Calibration_Flow] k_type=2
2356 22:12:51.187294
2357 22:12:51.187843 ==DQ 0 ==
2358 22:12:51.190597 Final DQ duty delay cell = -4
2359 22:12:51.194236 [-4] MAX Duty = 5062%(X100), DQS PI = 34
2360 22:12:51.197616 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2361 22:12:51.201051 [-4] AVG Duty = 4984%(X100)
2362 22:12:51.201597
2363 22:12:51.201952 ==DQ 1 ==
2364 22:12:51.204316 Final DQ duty delay cell = 0
2365 22:12:51.207516 [0] MAX Duty = 4938%(X100), DQS PI = 4
2366 22:12:51.210785 [0] MIN Duty = 4907%(X100), DQS PI = 0
2367 22:12:51.211349 [0] AVG Duty = 4922%(X100)
2368 22:12:51.213751
2369 22:12:51.217302 CH0 DQ 0 Duty spec in!! Max-Min= 155%
2370 22:12:51.217856
2371 22:12:51.220814 CH0 DQ 1 Duty spec in!! Max-Min= 31%
2372 22:12:51.223667 [DutyScan_Calibration_Flow] ====Done====
2373 22:12:51.224121 ==
2374 22:12:51.226888 Dram Type= 6, Freq= 0, CH_1, rank 0
2375 22:12:51.230319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2376 22:12:51.230955 ==
2377 22:12:51.233666 [Duty_Offset_Calibration]
2378 22:12:51.234222 B0:0 B1:-1 CA:2
2379 22:12:51.234684
2380 22:12:51.237300 [DutyScan_Calibration_Flow] k_type=0
2381 22:12:51.247364
2382 22:12:51.247909 ==CLK 0==
2383 22:12:51.251101 Final CLK duty delay cell = 0
2384 22:12:51.254560 [0] MAX Duty = 5156%(X100), DQS PI = 16
2385 22:12:51.257655 [0] MIN Duty = 4938%(X100), DQS PI = 44
2386 22:12:51.258205 [0] AVG Duty = 5047%(X100)
2387 22:12:51.260794
2388 22:12:51.261248 CH1 CLK Duty spec in!! Max-Min= 218%
2389 22:12:51.267305 [DutyScan_Calibration_Flow] ====Done====
2390 22:12:51.267849
2391 22:12:51.270582 [DutyScan_Calibration_Flow] k_type=1
2392 22:12:51.287071
2393 22:12:51.287628 ==DQS 0 ==
2394 22:12:51.290054 Final DQS duty delay cell = 0
2395 22:12:51.293637 [0] MAX Duty = 5093%(X100), DQS PI = 24
2396 22:12:51.297444 [0] MIN Duty = 4969%(X100), DQS PI = 0
2397 22:12:51.298006 [0] AVG Duty = 5031%(X100)
2398 22:12:51.299804
2399 22:12:51.300287 ==DQS 1 ==
2400 22:12:51.303327 Final DQS duty delay cell = 0
2401 22:12:51.307219 [0] MAX Duty = 5187%(X100), DQS PI = 0
2402 22:12:51.310285 [0] MIN Duty = 4844%(X100), DQS PI = 34
2403 22:12:51.310901 [0] AVG Duty = 5015%(X100)
2404 22:12:51.313519
2405 22:12:51.316502 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2406 22:12:51.317102
2407 22:12:51.320072 CH1 DQS 1 Duty spec in!! Max-Min= 343%
2408 22:12:51.323206 [DutyScan_Calibration_Flow] ====Done====
2409 22:12:51.323836
2410 22:12:51.326557 [DutyScan_Calibration_Flow] k_type=3
2411 22:12:51.343069
2412 22:12:51.343677 ==DQM 0 ==
2413 22:12:51.346807 Final DQM duty delay cell = 4
2414 22:12:51.350231 [4] MAX Duty = 5093%(X100), DQS PI = 20
2415 22:12:51.353313 [4] MIN Duty = 4969%(X100), DQS PI = 28
2416 22:12:51.356811 [4] AVG Duty = 5031%(X100)
2417 22:12:51.357391
2418 22:12:51.357877 ==DQM 1 ==
2419 22:12:51.359845 Final DQM duty delay cell = -4
2420 22:12:51.363323 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2421 22:12:51.366564 [-4] MIN Duty = 4751%(X100), DQS PI = 36
2422 22:12:51.369938 [-4] AVG Duty = 4875%(X100)
2423 22:12:51.370559
2424 22:12:51.373878 CH1 DQM 0 Duty spec in!! Max-Min= 124%
2425 22:12:51.374514
2426 22:12:51.376334 CH1 DQM 1 Duty spec in!! Max-Min= 249%
2427 22:12:51.380214 [DutyScan_Calibration_Flow] ====Done====
2428 22:12:51.380804
2429 22:12:51.383160 [DutyScan_Calibration_Flow] k_type=2
2430 22:12:51.400226
2431 22:12:51.400805 ==DQ 0 ==
2432 22:12:51.403604 Final DQ duty delay cell = 0
2433 22:12:51.406724 [0] MAX Duty = 5062%(X100), DQS PI = 16
2434 22:12:51.409983 [0] MIN Duty = 4938%(X100), DQS PI = 44
2435 22:12:51.410614 [0] AVG Duty = 5000%(X100)
2436 22:12:51.413616
2437 22:12:51.414195 ==DQ 1 ==
2438 22:12:51.416798 Final DQ duty delay cell = 0
2439 22:12:51.420141 [0] MAX Duty = 5031%(X100), DQS PI = 2
2440 22:12:51.423465 [0] MIN Duty = 4813%(X100), DQS PI = 36
2441 22:12:51.424053 [0] AVG Duty = 4922%(X100)
2442 22:12:51.424543
2443 22:12:51.426762 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2444 22:12:51.429628
2445 22:12:51.433024 CH1 DQ 1 Duty spec in!! Max-Min= 218%
2446 22:12:51.436398 [DutyScan_Calibration_Flow] ====Done====
2447 22:12:51.439824 nWR fixed to 30
2448 22:12:51.440503 [ModeRegInit_LP4] CH0 RK0
2449 22:12:51.443097 [ModeRegInit_LP4] CH0 RK1
2450 22:12:51.446722 [ModeRegInit_LP4] CH1 RK0
2451 22:12:51.447331 [ModeRegInit_LP4] CH1 RK1
2452 22:12:51.449566 match AC timing 7
2453 22:12:51.453004 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2454 22:12:51.459522 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2455 22:12:51.463257 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2456 22:12:51.469724 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2457 22:12:51.473434 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2458 22:12:51.474030 ==
2459 22:12:51.476114 Dram Type= 6, Freq= 0, CH_0, rank 0
2460 22:12:51.480486 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2461 22:12:51.481073 ==
2462 22:12:51.486504 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2463 22:12:51.492955 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2464 22:12:51.500219 [CA 0] Center 38 (7~69) winsize 63
2465 22:12:51.503242 [CA 1] Center 38 (8~69) winsize 62
2466 22:12:51.506975 [CA 2] Center 35 (4~66) winsize 63
2467 22:12:51.509780 [CA 3] Center 34 (4~65) winsize 62
2468 22:12:51.513292 [CA 4] Center 34 (4~64) winsize 61
2469 22:12:51.516484 [CA 5] Center 33 (3~64) winsize 62
2470 22:12:51.517059
2471 22:12:51.519637 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2472 22:12:51.520216
2473 22:12:51.523240 [CATrainingPosCal] consider 1 rank data
2474 22:12:51.526387 u2DelayCellTimex100 = 270/100 ps
2475 22:12:51.529681 CA0 delay=38 (7~69),Diff = 5 PI (24 cell)
2476 22:12:51.536288 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2477 22:12:51.539844 CA2 delay=35 (4~66),Diff = 2 PI (9 cell)
2478 22:12:51.542901 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
2479 22:12:51.546196 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2480 22:12:51.549615 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2481 22:12:51.550209
2482 22:12:51.552857 CA PerBit enable=1, Macro0, CA PI delay=33
2483 22:12:51.553484
2484 22:12:51.555969 [CBTSetCACLKResult] CA Dly = 33
2485 22:12:51.556450 CS Dly: 6 (0~37)
2486 22:12:51.559385 ==
2487 22:12:51.563039 Dram Type= 6, Freq= 0, CH_0, rank 1
2488 22:12:51.566227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2489 22:12:51.566849 ==
2490 22:12:51.569827 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2491 22:12:51.576093 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2492 22:12:51.586077 [CA 0] Center 39 (8~70) winsize 63
2493 22:12:51.588906 [CA 1] Center 38 (8~69) winsize 62
2494 22:12:51.593068 [CA 2] Center 35 (5~66) winsize 62
2495 22:12:51.596175 [CA 3] Center 35 (5~66) winsize 62
2496 22:12:51.598818 [CA 4] Center 34 (4~65) winsize 62
2497 22:12:51.602412 [CA 5] Center 34 (4~64) winsize 61
2498 22:12:51.602999
2499 22:12:51.605392 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2500 22:12:51.605973
2501 22:12:51.609050 [CATrainingPosCal] consider 2 rank data
2502 22:12:51.612152 u2DelayCellTimex100 = 270/100 ps
2503 22:12:51.615753 CA0 delay=38 (8~69),Diff = 4 PI (19 cell)
2504 22:12:51.622104 CA1 delay=38 (8~69),Diff = 4 PI (19 cell)
2505 22:12:51.626080 CA2 delay=35 (5~66),Diff = 1 PI (4 cell)
2506 22:12:51.628900 CA3 delay=35 (5~65),Diff = 1 PI (4 cell)
2507 22:12:51.632626 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
2508 22:12:51.635404 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2509 22:12:51.635989
2510 22:12:51.639880 CA PerBit enable=1, Macro0, CA PI delay=34
2511 22:12:51.640465
2512 22:12:51.642020 [CBTSetCACLKResult] CA Dly = 34
2513 22:12:51.642538 CS Dly: 7 (0~39)
2514 22:12:51.643013
2515 22:12:51.648536 ----->DramcWriteLeveling(PI) begin...
2516 22:12:51.649119 ==
2517 22:12:51.652102 Dram Type= 6, Freq= 0, CH_0, rank 0
2518 22:12:51.655123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2519 22:12:51.655708 ==
2520 22:12:51.658581 Write leveling (Byte 0): 35 => 35
2521 22:12:51.661853 Write leveling (Byte 1): 30 => 30
2522 22:12:51.665158 DramcWriteLeveling(PI) end<-----
2523 22:12:51.665738
2524 22:12:51.666225 ==
2525 22:12:51.668633 Dram Type= 6, Freq= 0, CH_0, rank 0
2526 22:12:51.672235 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2527 22:12:51.672817 ==
2528 22:12:51.675174 [Gating] SW mode calibration
2529 22:12:51.681954 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2530 22:12:51.688815 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2531 22:12:51.692390 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2532 22:12:51.695032 0 15 4 | B1->B0 | 2d2c 3434 | 1 1 | (0 0) (1 1)
2533 22:12:51.701695 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2534 22:12:51.705337 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2535 22:12:51.708869 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2536 22:12:51.715288 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2537 22:12:51.718916 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
2538 22:12:51.722023 0 15 28 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
2539 22:12:51.725254 1 0 0 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
2540 22:12:51.731976 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2541 22:12:51.735255 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2542 22:12:51.738700 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2543 22:12:51.744991 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2544 22:12:51.748462 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2545 22:12:51.751632 1 0 24 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
2546 22:12:51.757905 1 0 28 | B1->B0 | 2727 4646 | 0 0 | (0 0) (0 0)
2547 22:12:51.761320 1 1 0 | B1->B0 | 2e2e 4646 | 0 0 | (0 0) (0 0)
2548 22:12:51.765121 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2549 22:12:51.771912 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2550 22:12:51.774691 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2551 22:12:51.778938 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2552 22:12:51.784530 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2553 22:12:51.788191 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2554 22:12:51.791187 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2555 22:12:51.798125 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2556 22:12:51.801591 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 22:12:51.804637 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 22:12:51.811313 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 22:12:51.815429 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 22:12:51.818521 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 22:12:51.824767 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 22:12:51.828343 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 22:12:51.831689 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 22:12:51.838421 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 22:12:51.842002 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 22:12:51.844848 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 22:12:51.851950 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 22:12:51.854834 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 22:12:51.858441 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2570 22:12:51.860999 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2571 22:12:51.868313 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2572 22:12:51.871458 Total UI for P1: 0, mck2ui 16
2573 22:12:51.874529 best dqsien dly found for B0: ( 1, 3, 26)
2574 22:12:51.877939 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2575 22:12:51.881028 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2576 22:12:51.884288 Total UI for P1: 0, mck2ui 16
2577 22:12:51.887913 best dqsien dly found for B1: ( 1, 4, 2)
2578 22:12:51.890837 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2579 22:12:51.894318 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2580 22:12:51.897920
2581 22:12:51.901191 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2582 22:12:51.904478 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2583 22:12:51.908489 [Gating] SW calibration Done
2584 22:12:51.909057 ==
2585 22:12:51.911123 Dram Type= 6, Freq= 0, CH_0, rank 0
2586 22:12:51.914688 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2587 22:12:51.915269 ==
2588 22:12:51.915649 RX Vref Scan: 0
2589 22:12:51.915997
2590 22:12:51.917645 RX Vref 0 -> 0, step: 1
2591 22:12:51.918219
2592 22:12:51.921216 RX Delay -40 -> 252, step: 8
2593 22:12:51.924380 iDelay=208, Bit 0, Center 123 (56 ~ 191) 136
2594 22:12:51.928019 iDelay=208, Bit 1, Center 127 (56 ~ 199) 144
2595 22:12:51.934476 iDelay=208, Bit 2, Center 119 (48 ~ 191) 144
2596 22:12:51.938112 iDelay=208, Bit 3, Center 119 (48 ~ 191) 144
2597 22:12:51.941014 iDelay=208, Bit 4, Center 127 (56 ~ 199) 144
2598 22:12:51.943955 iDelay=208, Bit 5, Center 115 (48 ~ 183) 136
2599 22:12:51.947188 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
2600 22:12:51.954157 iDelay=208, Bit 7, Center 127 (56 ~ 199) 144
2601 22:12:51.957483 iDelay=208, Bit 8, Center 99 (32 ~ 167) 136
2602 22:12:51.961058 iDelay=208, Bit 9, Center 99 (32 ~ 167) 136
2603 22:12:51.964105 iDelay=208, Bit 10, Center 107 (40 ~ 175) 136
2604 22:12:51.967350 iDelay=208, Bit 11, Center 107 (40 ~ 175) 136
2605 22:12:51.973970 iDelay=208, Bit 12, Center 115 (48 ~ 183) 136
2606 22:12:51.977121 iDelay=208, Bit 13, Center 115 (48 ~ 183) 136
2607 22:12:51.981313 iDelay=208, Bit 14, Center 123 (56 ~ 191) 136
2608 22:12:51.983676 iDelay=208, Bit 15, Center 115 (48 ~ 183) 136
2609 22:12:51.984144 ==
2610 22:12:51.987031 Dram Type= 6, Freq= 0, CH_0, rank 0
2611 22:12:51.993839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2612 22:12:51.994439 ==
2613 22:12:51.994836 DQS Delay:
2614 22:12:51.997105 DQS0 = 0, DQS1 = 0
2615 22:12:51.997572 DQM Delay:
2616 22:12:51.997945 DQM0 = 123, DQM1 = 110
2617 22:12:52.000684 DQ Delay:
2618 22:12:52.004705 DQ0 =123, DQ1 =127, DQ2 =119, DQ3 =119
2619 22:12:52.007128 DQ4 =127, DQ5 =115, DQ6 =131, DQ7 =127
2620 22:12:52.010377 DQ8 =99, DQ9 =99, DQ10 =107, DQ11 =107
2621 22:12:52.014620 DQ12 =115, DQ13 =115, DQ14 =123, DQ15 =115
2622 22:12:52.015177
2623 22:12:52.015547
2624 22:12:52.015889 ==
2625 22:12:52.017322 Dram Type= 6, Freq= 0, CH_0, rank 0
2626 22:12:52.020580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2627 22:12:52.023651 ==
2628 22:12:52.024211
2629 22:12:52.024583
2630 22:12:52.024923 TX Vref Scan disable
2631 22:12:52.026943 == TX Byte 0 ==
2632 22:12:52.030436 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2633 22:12:52.033849 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2634 22:12:52.037502 == TX Byte 1 ==
2635 22:12:52.040546 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2636 22:12:52.043811 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2637 22:12:52.044430 ==
2638 22:12:52.047272 Dram Type= 6, Freq= 0, CH_0, rank 0
2639 22:12:52.053503 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2640 22:12:52.054296 ==
2641 22:12:52.065000 TX Vref=22, minBit 7, minWin=23, winSum=403
2642 22:12:52.067923 TX Vref=24, minBit 0, minWin=24, winSum=404
2643 22:12:52.071306 TX Vref=26, minBit 0, minWin=25, winSum=415
2644 22:12:52.074800 TX Vref=28, minBit 5, minWin=25, winSum=417
2645 22:12:52.077750 TX Vref=30, minBit 0, minWin=25, winSum=419
2646 22:12:52.084407 TX Vref=32, minBit 1, minWin=25, winSum=417
2647 22:12:52.087661 [TxChooseVref] Worse bit 0, Min win 25, Win sum 419, Final Vref 30
2648 22:12:52.088133
2649 22:12:52.090906 Final TX Range 1 Vref 30
2650 22:12:52.091409
2651 22:12:52.091779 ==
2652 22:12:52.095045 Dram Type= 6, Freq= 0, CH_0, rank 0
2653 22:12:52.097824 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2654 22:12:52.098295 ==
2655 22:12:52.098741
2656 22:12:52.101509
2657 22:12:52.102099 TX Vref Scan disable
2658 22:12:52.104621 == TX Byte 0 ==
2659 22:12:52.107930 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2660 22:12:52.111004 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2661 22:12:52.114657 == TX Byte 1 ==
2662 22:12:52.118076 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2663 22:12:52.121092 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2664 22:12:52.125058
2665 22:12:52.125620 [DATLAT]
2666 22:12:52.125989 Freq=1200, CH0 RK0
2667 22:12:52.126335
2668 22:12:52.127620 DATLAT Default: 0xd
2669 22:12:52.128080 0, 0xFFFF, sum = 0
2670 22:12:52.130998 1, 0xFFFF, sum = 0
2671 22:12:52.131566 2, 0xFFFF, sum = 0
2672 22:12:52.134954 3, 0xFFFF, sum = 0
2673 22:12:52.135527 4, 0xFFFF, sum = 0
2674 22:12:52.138264 5, 0xFFFF, sum = 0
2675 22:12:52.138875 6, 0xFFFF, sum = 0
2676 22:12:52.141226 7, 0xFFFF, sum = 0
2677 22:12:52.144487 8, 0xFFFF, sum = 0
2678 22:12:52.144960 9, 0xFFFF, sum = 0
2679 22:12:52.147969 10, 0xFFFF, sum = 0
2680 22:12:52.148545 11, 0xFFFF, sum = 0
2681 22:12:52.151032 12, 0x0, sum = 1
2682 22:12:52.151505 13, 0x0, sum = 2
2683 22:12:52.154804 14, 0x0, sum = 3
2684 22:12:52.155377 15, 0x0, sum = 4
2685 22:12:52.155765 best_step = 13
2686 22:12:52.156113
2687 22:12:52.158239 ==
2688 22:12:52.160990 Dram Type= 6, Freq= 0, CH_0, rank 0
2689 22:12:52.165356 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2690 22:12:52.165927 ==
2691 22:12:52.166303 RX Vref Scan: 1
2692 22:12:52.166679
2693 22:12:52.167728 Set Vref Range= 32 -> 127
2694 22:12:52.168192
2695 22:12:52.171291 RX Vref 32 -> 127, step: 1
2696 22:12:52.171862
2697 22:12:52.175021 RX Delay -13 -> 252, step: 4
2698 22:12:52.175594
2699 22:12:52.178041 Set Vref, RX VrefLevel [Byte0]: 32
2700 22:12:52.180985 [Byte1]: 32
2701 22:12:52.181454
2702 22:12:52.184404 Set Vref, RX VrefLevel [Byte0]: 33
2703 22:12:52.187419 [Byte1]: 33
2704 22:12:52.187908
2705 22:12:52.191193 Set Vref, RX VrefLevel [Byte0]: 34
2706 22:12:52.194081 [Byte1]: 34
2707 22:12:52.198423
2708 22:12:52.198889 Set Vref, RX VrefLevel [Byte0]: 35
2709 22:12:52.201895 [Byte1]: 35
2710 22:12:52.206196
2711 22:12:52.206725 Set Vref, RX VrefLevel [Byte0]: 36
2712 22:12:52.209525 [Byte1]: 36
2713 22:12:52.214345
2714 22:12:52.214953 Set Vref, RX VrefLevel [Byte0]: 37
2715 22:12:52.217664 [Byte1]: 37
2716 22:12:52.222568
2717 22:12:52.223167 Set Vref, RX VrefLevel [Byte0]: 38
2718 22:12:52.225770 [Byte1]: 38
2719 22:12:52.231486
2720 22:12:52.232050 Set Vref, RX VrefLevel [Byte0]: 39
2721 22:12:52.234055 [Byte1]: 39
2722 22:12:52.238697
2723 22:12:52.239260 Set Vref, RX VrefLevel [Byte0]: 40
2724 22:12:52.241242 [Byte1]: 40
2725 22:12:52.245732
2726 22:12:52.246197 Set Vref, RX VrefLevel [Byte0]: 41
2727 22:12:52.249275 [Byte1]: 41
2728 22:12:52.253923
2729 22:12:52.254512 Set Vref, RX VrefLevel [Byte0]: 42
2730 22:12:52.256996 [Byte1]: 42
2731 22:12:52.261818
2732 22:12:52.262420 Set Vref, RX VrefLevel [Byte0]: 43
2733 22:12:52.265391 [Byte1]: 43
2734 22:12:52.269919
2735 22:12:52.270518 Set Vref, RX VrefLevel [Byte0]: 44
2736 22:12:52.272939 [Byte1]: 44
2737 22:12:52.277800
2738 22:12:52.278394 Set Vref, RX VrefLevel [Byte0]: 45
2739 22:12:52.281363 [Byte1]: 45
2740 22:12:52.285612
2741 22:12:52.286177 Set Vref, RX VrefLevel [Byte0]: 46
2742 22:12:52.289171 [Byte1]: 46
2743 22:12:52.293390
2744 22:12:52.293966 Set Vref, RX VrefLevel [Byte0]: 47
2745 22:12:52.296495 [Byte1]: 47
2746 22:12:52.300993
2747 22:12:52.301562 Set Vref, RX VrefLevel [Byte0]: 48
2748 22:12:52.304641 [Byte1]: 48
2749 22:12:52.308896
2750 22:12:52.309474 Set Vref, RX VrefLevel [Byte0]: 49
2751 22:12:52.312310 [Byte1]: 49
2752 22:12:52.317045
2753 22:12:52.317617 Set Vref, RX VrefLevel [Byte0]: 50
2754 22:12:52.320407 [Byte1]: 50
2755 22:12:52.324832
2756 22:12:52.325398 Set Vref, RX VrefLevel [Byte0]: 51
2757 22:12:52.327803 [Byte1]: 51
2758 22:12:52.333339
2759 22:12:52.333924 Set Vref, RX VrefLevel [Byte0]: 52
2760 22:12:52.336186 [Byte1]: 52
2761 22:12:52.340648
2762 22:12:52.341205 Set Vref, RX VrefLevel [Byte0]: 53
2763 22:12:52.343656 [Byte1]: 53
2764 22:12:52.349501
2765 22:12:52.350067 Set Vref, RX VrefLevel [Byte0]: 54
2766 22:12:52.351544 [Byte1]: 54
2767 22:12:52.356741
2768 22:12:52.357313 Set Vref, RX VrefLevel [Byte0]: 55
2769 22:12:52.360255 [Byte1]: 55
2770 22:12:52.364597
2771 22:12:52.365158 Set Vref, RX VrefLevel [Byte0]: 56
2772 22:12:52.367669 [Byte1]: 56
2773 22:12:52.372241
2774 22:12:52.372800 Set Vref, RX VrefLevel [Byte0]: 57
2775 22:12:52.375828 [Byte1]: 57
2776 22:12:52.380163
2777 22:12:52.380726 Set Vref, RX VrefLevel [Byte0]: 58
2778 22:12:52.383660 [Byte1]: 58
2779 22:12:52.388130
2780 22:12:52.388691 Set Vref, RX VrefLevel [Byte0]: 59
2781 22:12:52.395081 [Byte1]: 59
2782 22:12:52.395651
2783 22:12:52.397872 Set Vref, RX VrefLevel [Byte0]: 60
2784 22:12:52.401234 [Byte1]: 60
2785 22:12:52.401814
2786 22:12:52.404432 Set Vref, RX VrefLevel [Byte0]: 61
2787 22:12:52.408545 [Byte1]: 61
2788 22:12:52.411331
2789 22:12:52.411820 Set Vref, RX VrefLevel [Byte0]: 62
2790 22:12:52.414590 [Byte1]: 62
2791 22:12:52.419351
2792 22:12:52.419914 Set Vref, RX VrefLevel [Byte0]: 63
2793 22:12:52.422651 [Byte1]: 63
2794 22:12:52.427525
2795 22:12:52.428088 Set Vref, RX VrefLevel [Byte0]: 64
2796 22:12:52.430666 [Byte1]: 64
2797 22:12:52.435298
2798 22:12:52.435865 Set Vref, RX VrefLevel [Byte0]: 65
2799 22:12:52.438463 [Byte1]: 65
2800 22:12:52.443740
2801 22:12:52.444304 Set Vref, RX VrefLevel [Byte0]: 66
2802 22:12:52.446314 [Byte1]: 66
2803 22:12:52.451031
2804 22:12:52.451605 Set Vref, RX VrefLevel [Byte0]: 67
2805 22:12:52.454570 [Byte1]: 67
2806 22:12:52.459236
2807 22:12:52.459808 Set Vref, RX VrefLevel [Byte0]: 68
2808 22:12:52.462752 [Byte1]: 68
2809 22:12:52.467280
2810 22:12:52.467849 Set Vref, RX VrefLevel [Byte0]: 69
2811 22:12:52.470502 [Byte1]: 69
2812 22:12:52.474935
2813 22:12:52.475504 Set Vref, RX VrefLevel [Byte0]: 70
2814 22:12:52.478395 [Byte1]: 70
2815 22:12:52.483326
2816 22:12:52.483900 Set Vref, RX VrefLevel [Byte0]: 71
2817 22:12:52.485773 [Byte1]: 71
2818 22:12:52.490738
2819 22:12:52.493767 Final RX Vref Byte 0 = 60 to rank0
2820 22:12:52.494324 Final RX Vref Byte 1 = 51 to rank0
2821 22:12:52.497342 Final RX Vref Byte 0 = 60 to rank1
2822 22:12:52.500531 Final RX Vref Byte 1 = 51 to rank1==
2823 22:12:52.503908 Dram Type= 6, Freq= 0, CH_0, rank 0
2824 22:12:52.510567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2825 22:12:52.511132 ==
2826 22:12:52.511569 DQS Delay:
2827 22:12:52.513435 DQS0 = 0, DQS1 = 0
2828 22:12:52.513944 DQM Delay:
2829 22:12:52.514305 DQM0 = 123, DQM1 = 109
2830 22:12:52.517047 DQ Delay:
2831 22:12:52.520874 DQ0 =122, DQ1 =122, DQ2 =120, DQ3 =120
2832 22:12:52.523729 DQ4 =126, DQ5 =116, DQ6 =130, DQ7 =128
2833 22:12:52.526801 DQ8 =102, DQ9 =94, DQ10 =110, DQ11 =104
2834 22:12:52.530491 DQ12 =116, DQ13 =110, DQ14 =122, DQ15 =116
2835 22:12:52.531072
2836 22:12:52.531444
2837 22:12:52.540087 [DQSOSCAuto] RK0, (LSB)MR18= 0xe0a, (MSB)MR19= 0x404, tDQSOscB0 = 406 ps tDQSOscB1 = 404 ps
2838 22:12:52.540667 CH0 RK0: MR19=404, MR18=E0A
2839 22:12:52.547306 CH0_RK0: MR19=0x404, MR18=0xE0A, DQSOSC=404, MR23=63, INC=40, DEC=26
2840 22:12:52.547781
2841 22:12:52.549769 ----->DramcWriteLeveling(PI) begin...
2842 22:12:52.550297 ==
2843 22:12:52.553627 Dram Type= 6, Freq= 0, CH_0, rank 1
2844 22:12:52.560724 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2845 22:12:52.561291 ==
2846 22:12:52.564849 Write leveling (Byte 0): 37 => 37
2847 22:12:52.565409 Write leveling (Byte 1): 29 => 29
2848 22:12:52.566921 DramcWriteLeveling(PI) end<-----
2849 22:12:52.567385
2850 22:12:52.567753 ==
2851 22:12:52.570447 Dram Type= 6, Freq= 0, CH_0, rank 1
2852 22:12:52.576754 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2853 22:12:52.577317 ==
2854 22:12:52.580468 [Gating] SW mode calibration
2855 22:12:52.586329 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2856 22:12:52.590109 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2857 22:12:52.596721 0 15 0 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
2858 22:12:52.600322 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2859 22:12:52.603030 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2860 22:12:52.610182 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2861 22:12:52.613533 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2862 22:12:52.616455 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2863 22:12:52.623013 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2864 22:12:52.626439 0 15 28 | B1->B0 | 2f2f 2b2b | 0 0 | (0 1) (0 0)
2865 22:12:52.629931 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
2866 22:12:52.636311 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2867 22:12:52.639419 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2868 22:12:52.643104 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2869 22:12:52.646826 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2870 22:12:52.653134 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2871 22:12:52.656274 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2872 22:12:52.659785 1 0 28 | B1->B0 | 3838 3e3e | 0 1 | (0 0) (0 0)
2873 22:12:52.666268 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2874 22:12:52.669718 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2875 22:12:52.672937 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2876 22:12:52.679319 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2877 22:12:52.683296 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2878 22:12:52.686077 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2879 22:12:52.692748 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2880 22:12:52.696329 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2881 22:12:52.700158 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2882 22:12:52.706163 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2883 22:12:52.709900 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 22:12:52.712831 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 22:12:52.719376 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 22:12:52.723148 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 22:12:52.725960 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 22:12:52.732686 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2889 22:12:52.736634 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2890 22:12:52.739138 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2891 22:12:52.745940 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2892 22:12:52.749108 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2893 22:12:52.752389 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2894 22:12:52.758933 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2895 22:12:52.762198 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2896 22:12:52.765817 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2897 22:12:52.772032 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2898 22:12:52.775648 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2899 22:12:52.779613 Total UI for P1: 0, mck2ui 16
2900 22:12:52.782514 best dqsien dly found for B0: ( 1, 3, 30)
2901 22:12:52.785465 Total UI for P1: 0, mck2ui 16
2902 22:12:52.789084 best dqsien dly found for B1: ( 1, 3, 30)
2903 22:12:52.792239 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2904 22:12:52.796107 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2905 22:12:52.796672
2906 22:12:52.798847 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2907 22:12:52.801972 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2908 22:12:52.805281 [Gating] SW calibration Done
2909 22:12:52.805747 ==
2910 22:12:52.809021 Dram Type= 6, Freq= 0, CH_0, rank 1
2911 22:12:52.812139 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2912 22:12:52.812703 ==
2913 22:12:52.815285 RX Vref Scan: 0
2914 22:12:52.815845
2915 22:12:52.819063 RX Vref 0 -> 0, step: 1
2916 22:12:52.819624
2917 22:12:52.819997 RX Delay -40 -> 252, step: 8
2918 22:12:52.826051 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2919 22:12:52.829279 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2920 22:12:52.832287 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2921 22:12:52.835687 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2922 22:12:52.838905 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2923 22:12:52.845184 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2924 22:12:52.848324 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2925 22:12:52.851533 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2926 22:12:52.855487 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2927 22:12:52.858827 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2928 22:12:52.865141 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2929 22:12:52.868709 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2930 22:12:52.871861 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2931 22:12:52.875739 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2932 22:12:52.878863 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
2933 22:12:52.885433 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2934 22:12:52.886209 ==
2935 22:12:52.888623 Dram Type= 6, Freq= 0, CH_0, rank 1
2936 22:12:52.891701 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2937 22:12:52.892174 ==
2938 22:12:52.892564 DQS Delay:
2939 22:12:52.895531 DQS0 = 0, DQS1 = 0
2940 22:12:52.895996 DQM Delay:
2941 22:12:52.898124 DQM0 = 120, DQM1 = 108
2942 22:12:52.898619 DQ Delay:
2943 22:12:52.902011 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
2944 22:12:52.904657 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2945 22:12:52.908592 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
2946 22:12:52.911983 DQ12 =111, DQ13 =115, DQ14 =115, DQ15 =115
2947 22:12:52.912549
2948 22:12:52.914949
2949 22:12:52.915514 ==
2950 22:12:52.918527 Dram Type= 6, Freq= 0, CH_0, rank 1
2951 22:12:52.921713 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2952 22:12:52.922284 ==
2953 22:12:52.922693
2954 22:12:52.923037
2955 22:12:52.924916 TX Vref Scan disable
2956 22:12:52.925482 == TX Byte 0 ==
2957 22:12:52.932002 Update DQ dly =855 (3 ,2, 23) DQ OEN =(2 ,7)
2958 22:12:52.935079 Update DQM dly =855 (3 ,2, 23) DQM OEN =(2 ,7)
2959 22:12:52.935649 == TX Byte 1 ==
2960 22:12:52.942158 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2961 22:12:52.944728 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2962 22:12:52.945295 ==
2963 22:12:52.948296 Dram Type= 6, Freq= 0, CH_0, rank 1
2964 22:12:52.951286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2965 22:12:52.951757 ==
2966 22:12:52.964798 TX Vref=22, minBit 12, minWin=24, winSum=415
2967 22:12:52.967774 TX Vref=24, minBit 0, minWin=26, winSum=426
2968 22:12:52.971214 TX Vref=26, minBit 1, minWin=26, winSum=426
2969 22:12:52.974681 TX Vref=28, minBit 1, minWin=26, winSum=429
2970 22:12:52.978103 TX Vref=30, minBit 10, minWin=26, winSum=434
2971 22:12:52.984991 TX Vref=32, minBit 12, minWin=26, winSum=434
2972 22:12:52.987492 [TxChooseVref] Worse bit 10, Min win 26, Win sum 434, Final Vref 30
2973 22:12:52.987962
2974 22:12:52.990926 Final TX Range 1 Vref 30
2975 22:12:52.991400
2976 22:12:52.991771 ==
2977 22:12:52.994304 Dram Type= 6, Freq= 0, CH_0, rank 1
2978 22:12:52.998709 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2979 22:12:53.001208 ==
2980 22:12:53.001781
2981 22:12:53.002156
2982 22:12:53.002571 TX Vref Scan disable
2983 22:12:53.004425 == TX Byte 0 ==
2984 22:12:53.008036 Update DQ dly =855 (3 ,2, 23) DQ OEN =(2 ,7)
2985 22:12:53.015113 Update DQM dly =855 (3 ,2, 23) DQM OEN =(2 ,7)
2986 22:12:53.015688 == TX Byte 1 ==
2987 22:12:53.017880 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2988 22:12:53.024854 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2989 22:12:53.025428
2990 22:12:53.025803 [DATLAT]
2991 22:12:53.026149 Freq=1200, CH0 RK1
2992 22:12:53.026526
2993 22:12:53.027692 DATLAT Default: 0xd
2994 22:12:53.031292 0, 0xFFFF, sum = 0
2995 22:12:53.031876 1, 0xFFFF, sum = 0
2996 22:12:53.034529 2, 0xFFFF, sum = 0
2997 22:12:53.035105 3, 0xFFFF, sum = 0
2998 22:12:53.037829 4, 0xFFFF, sum = 0
2999 22:12:53.038453 5, 0xFFFF, sum = 0
3000 22:12:53.041354 6, 0xFFFF, sum = 0
3001 22:12:53.041934 7, 0xFFFF, sum = 0
3002 22:12:53.044736 8, 0xFFFF, sum = 0
3003 22:12:53.045315 9, 0xFFFF, sum = 0
3004 22:12:53.048086 10, 0xFFFF, sum = 0
3005 22:12:53.048667 11, 0xFFFF, sum = 0
3006 22:12:53.050843 12, 0x0, sum = 1
3007 22:12:53.051319 13, 0x0, sum = 2
3008 22:12:53.054597 14, 0x0, sum = 3
3009 22:12:53.055181 15, 0x0, sum = 4
3010 22:12:53.057778 best_step = 13
3011 22:12:53.058384
3012 22:12:53.058773 ==
3013 22:12:53.060816 Dram Type= 6, Freq= 0, CH_0, rank 1
3014 22:12:53.063970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3015 22:12:53.064494 ==
3016 22:12:53.064984 RX Vref Scan: 0
3017 22:12:53.067098
3018 22:12:53.067567 RX Vref 0 -> 0, step: 1
3019 22:12:53.067944
3020 22:12:53.070469 RX Delay -21 -> 252, step: 4
3021 22:12:53.077495 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3022 22:12:53.080539 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3023 22:12:53.084245 iDelay=195, Bit 2, Center 116 (51 ~ 182) 132
3024 22:12:53.087360 iDelay=195, Bit 3, Center 114 (47 ~ 182) 136
3025 22:12:53.090405 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3026 22:12:53.097591 iDelay=195, Bit 5, Center 114 (51 ~ 178) 128
3027 22:12:53.100722 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3028 22:12:53.104064 iDelay=195, Bit 7, Center 124 (55 ~ 194) 140
3029 22:12:53.106938 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3030 22:12:53.110667 iDelay=195, Bit 9, Center 94 (31 ~ 158) 128
3031 22:12:53.113998 iDelay=195, Bit 10, Center 108 (47 ~ 170) 124
3032 22:12:53.120511 iDelay=195, Bit 11, Center 104 (43 ~ 166) 124
3033 22:12:53.123942 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3034 22:12:53.127275 iDelay=195, Bit 13, Center 110 (47 ~ 174) 128
3035 22:12:53.130703 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3036 22:12:53.137291 iDelay=195, Bit 15, Center 116 (55 ~ 178) 124
3037 22:12:53.137876 ==
3038 22:12:53.140498 Dram Type= 6, Freq= 0, CH_0, rank 1
3039 22:12:53.143830 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3040 22:12:53.144408 ==
3041 22:12:53.144897 DQS Delay:
3042 22:12:53.146928 DQS0 = 0, DQS1 = 0
3043 22:12:53.147404 DQM Delay:
3044 22:12:53.150549 DQM0 = 119, DQM1 = 107
3045 22:12:53.151118 DQ Delay:
3046 22:12:53.154338 DQ0 =118, DQ1 =122, DQ2 =116, DQ3 =114
3047 22:12:53.157029 DQ4 =122, DQ5 =114, DQ6 =126, DQ7 =124
3048 22:12:53.161103 DQ8 =98, DQ9 =94, DQ10 =108, DQ11 =104
3049 22:12:53.164111 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =116
3050 22:12:53.164692
3051 22:12:53.165219
3052 22:12:53.173519 [DQSOSCAuto] RK1, (LSB)MR18= 0xdf5, (MSB)MR19= 0x403, tDQSOscB0 = 414 ps tDQSOscB1 = 405 ps
3053 22:12:53.176810 CH0 RK1: MR19=403, MR18=DF5
3054 22:12:53.180487 CH0_RK1: MR19=0x403, MR18=0xDF5, DQSOSC=405, MR23=63, INC=39, DEC=26
3055 22:12:53.183452 [RxdqsGatingPostProcess] freq 1200
3056 22:12:53.189694 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3057 22:12:53.193556 best DQS0 dly(2T, 0.5T) = (0, 11)
3058 22:12:53.196926 best DQS1 dly(2T, 0.5T) = (0, 12)
3059 22:12:53.200172 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3060 22:12:53.203810 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3061 22:12:53.206388 best DQS0 dly(2T, 0.5T) = (0, 11)
3062 22:12:53.210342 best DQS1 dly(2T, 0.5T) = (0, 11)
3063 22:12:53.213342 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3064 22:12:53.217258 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3065 22:12:53.220249 Pre-setting of DQS Precalculation
3066 22:12:53.223430 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3067 22:12:53.224002 ==
3068 22:12:53.227417 Dram Type= 6, Freq= 0, CH_1, rank 0
3069 22:12:53.229967 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3070 22:12:53.230569 ==
3071 22:12:53.237069 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3072 22:12:53.244277 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3073 22:12:53.250889 [CA 0] Center 37 (7~68) winsize 62
3074 22:12:53.254437 [CA 1] Center 37 (7~68) winsize 62
3075 22:12:53.257753 [CA 2] Center 35 (5~65) winsize 61
3076 22:12:53.261349 [CA 3] Center 34 (4~65) winsize 62
3077 22:12:53.264010 [CA 4] Center 34 (4~64) winsize 61
3078 22:12:53.267666 [CA 5] Center 33 (3~64) winsize 62
3079 22:12:53.268237
3080 22:12:53.270765 [CmdBusTrainingLP45] Vref(ca) range 1: 31
3081 22:12:53.271326
3082 22:12:53.273876 [CATrainingPosCal] consider 1 rank data
3083 22:12:53.277175 u2DelayCellTimex100 = 270/100 ps
3084 22:12:53.280547 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3085 22:12:53.287249 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3086 22:12:53.290904 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3087 22:12:53.293789 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3088 22:12:53.297245 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3089 22:12:53.300716 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3090 22:12:53.301292
3091 22:12:53.303781 CA PerBit enable=1, Macro0, CA PI delay=33
3092 22:12:53.304249
3093 22:12:53.307182 [CBTSetCACLKResult] CA Dly = 33
3094 22:12:53.307647 CS Dly: 5 (0~36)
3095 22:12:53.310708 ==
3096 22:12:53.311326 Dram Type= 6, Freq= 0, CH_1, rank 1
3097 22:12:53.317636 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3098 22:12:53.318215 ==
3099 22:12:53.320768 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3100 22:12:53.327784 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3101 22:12:53.336537 [CA 0] Center 38 (8~68) winsize 61
3102 22:12:53.339631 [CA 1] Center 38 (8~68) winsize 61
3103 22:12:53.343267 [CA 2] Center 35 (5~66) winsize 62
3104 22:12:53.346986 [CA 3] Center 34 (4~65) winsize 62
3105 22:12:53.350532 [CA 4] Center 35 (5~65) winsize 61
3106 22:12:53.352976 [CA 5] Center 34 (4~64) winsize 61
3107 22:12:53.353548
3108 22:12:53.356675 [CmdBusTrainingLP45] Vref(ca) range 1: 31
3109 22:12:53.357253
3110 22:12:53.359207 [CATrainingPosCal] consider 2 rank data
3111 22:12:53.362994 u2DelayCellTimex100 = 270/100 ps
3112 22:12:53.366029 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3113 22:12:53.372892 CA1 delay=38 (8~68),Diff = 4 PI (19 cell)
3114 22:12:53.376150 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3115 22:12:53.379211 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3116 22:12:53.382641 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
3117 22:12:53.385615 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3118 22:12:53.386098
3119 22:12:53.388799 CA PerBit enable=1, Macro0, CA PI delay=34
3120 22:12:53.389263
3121 22:12:53.392442 [CBTSetCACLKResult] CA Dly = 34
3122 22:12:53.395636 CS Dly: 6 (0~39)
3123 22:12:53.396102
3124 22:12:53.399053 ----->DramcWriteLeveling(PI) begin...
3125 22:12:53.399553 ==
3126 22:12:53.402422 Dram Type= 6, Freq= 0, CH_1, rank 0
3127 22:12:53.405422 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3128 22:12:53.405890 ==
3129 22:12:53.409507 Write leveling (Byte 0): 23 => 23
3130 22:12:53.412335 Write leveling (Byte 1): 29 => 29
3131 22:12:53.415968 DramcWriteLeveling(PI) end<-----
3132 22:12:53.416612
3133 22:12:53.417007 ==
3134 22:12:53.418711 Dram Type= 6, Freq= 0, CH_1, rank 0
3135 22:12:53.422759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3136 22:12:53.423324 ==
3137 22:12:53.425406 [Gating] SW mode calibration
3138 22:12:53.432355 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3139 22:12:53.439160 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3140 22:12:53.442815 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3141 22:12:53.446000 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3142 22:12:53.452320 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3143 22:12:53.455280 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3144 22:12:53.458969 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3145 22:12:53.466016 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3146 22:12:53.469043 0 15 24 | B1->B0 | 2c2c 2626 | 0 1 | (0 1) (1 0)
3147 22:12:53.471978 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3148 22:12:53.479104 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3149 22:12:53.482762 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3150 22:12:53.485295 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3151 22:12:53.492091 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3152 22:12:53.495042 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3153 22:12:53.498608 1 0 20 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
3154 22:12:53.504839 1 0 24 | B1->B0 | 3b3b 4141 | 0 0 | (0 0) (0 0)
3155 22:12:53.508231 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3156 22:12:53.511605 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3157 22:12:53.518277 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3158 22:12:53.521873 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3159 22:12:53.525364 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3160 22:12:53.531582 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3161 22:12:53.535310 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3162 22:12:53.538484 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3163 22:12:53.544937 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3164 22:12:53.547831 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3165 22:12:53.552577 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3166 22:12:53.558033 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 22:12:53.561669 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 22:12:53.564970 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 22:12:53.571288 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 22:12:53.574554 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 22:12:53.577966 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3172 22:12:53.584979 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3173 22:12:53.588299 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3174 22:12:53.590894 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3175 22:12:53.597781 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3176 22:12:53.601039 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3177 22:12:53.604388 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3178 22:12:53.610712 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3179 22:12:53.614433 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3180 22:12:53.617298 Total UI for P1: 0, mck2ui 16
3181 22:12:53.620713 best dqsien dly found for B0: ( 1, 3, 22)
3182 22:12:53.623932 Total UI for P1: 0, mck2ui 16
3183 22:12:53.627069 best dqsien dly found for B1: ( 1, 3, 24)
3184 22:12:53.631009 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3185 22:12:53.633773 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3186 22:12:53.634243
3187 22:12:53.637114 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3188 22:12:53.640619 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3189 22:12:53.644023 [Gating] SW calibration Done
3190 22:12:53.644595 ==
3191 22:12:53.647255 Dram Type= 6, Freq= 0, CH_1, rank 0
3192 22:12:53.650428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3193 22:12:53.651002 ==
3194 22:12:53.653621 RX Vref Scan: 0
3195 22:12:53.654091
3196 22:12:53.657116 RX Vref 0 -> 0, step: 1
3197 22:12:53.657677
3198 22:12:53.658055 RX Delay -40 -> 252, step: 8
3199 22:12:53.664421 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3200 22:12:53.667180 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3201 22:12:53.670576 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3202 22:12:53.673944 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3203 22:12:53.677042 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3204 22:12:53.684271 iDelay=200, Bit 5, Center 127 (64 ~ 191) 128
3205 22:12:53.686986 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3206 22:12:53.690123 iDelay=200, Bit 7, Center 119 (56 ~ 183) 128
3207 22:12:53.693966 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3208 22:12:53.696895 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3209 22:12:53.703619 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3210 22:12:53.706935 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3211 22:12:53.710426 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3212 22:12:53.713130 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3213 22:12:53.720334 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3214 22:12:53.723600 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3215 22:12:53.724165 ==
3216 22:12:53.726567 Dram Type= 6, Freq= 0, CH_1, rank 0
3217 22:12:53.729957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3218 22:12:53.730568 ==
3219 22:12:53.730956 DQS Delay:
3220 22:12:53.733322 DQS0 = 0, DQS1 = 0
3221 22:12:53.733896 DQM Delay:
3222 22:12:53.736575 DQM0 = 119, DQM1 = 112
3223 22:12:53.737042 DQ Delay:
3224 22:12:53.739875 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3225 22:12:53.743710 DQ4 =115, DQ5 =127, DQ6 =131, DQ7 =119
3226 22:12:53.746594 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3227 22:12:53.750153 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3228 22:12:53.752945
3229 22:12:53.753440
3230 22:12:53.753809 ==
3231 22:12:53.756569 Dram Type= 6, Freq= 0, CH_1, rank 0
3232 22:12:53.759936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3233 22:12:53.760501 ==
3234 22:12:53.760879
3235 22:12:53.761228
3236 22:12:53.763100 TX Vref Scan disable
3237 22:12:53.763571 == TX Byte 0 ==
3238 22:12:53.770229 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3239 22:12:53.773275 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3240 22:12:53.773838 == TX Byte 1 ==
3241 22:12:53.780019 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3242 22:12:53.783271 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3243 22:12:53.783836 ==
3244 22:12:53.786468 Dram Type= 6, Freq= 0, CH_1, rank 0
3245 22:12:53.789833 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3246 22:12:53.790480 ==
3247 22:12:53.802895 TX Vref=22, minBit 1, minWin=24, winSum=407
3248 22:12:53.805673 TX Vref=24, minBit 11, minWin=24, winSum=413
3249 22:12:53.809914 TX Vref=26, minBit 9, minWin=25, winSum=415
3250 22:12:53.812479 TX Vref=28, minBit 9, minWin=25, winSum=420
3251 22:12:53.815360 TX Vref=30, minBit 10, minWin=25, winSum=421
3252 22:12:53.822313 TX Vref=32, minBit 1, minWin=26, winSum=424
3253 22:12:53.825504 [TxChooseVref] Worse bit 1, Min win 26, Win sum 424, Final Vref 32
3254 22:12:53.826069
3255 22:12:53.828811 Final TX Range 1 Vref 32
3256 22:12:53.829381
3257 22:12:53.829754 ==
3258 22:12:53.832748 Dram Type= 6, Freq= 0, CH_1, rank 0
3259 22:12:53.836110 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3260 22:12:53.836584 ==
3261 22:12:53.839113
3262 22:12:53.839682
3263 22:12:53.840054 TX Vref Scan disable
3264 22:12:53.841986 == TX Byte 0 ==
3265 22:12:53.845523 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3266 22:12:53.852263 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3267 22:12:53.852855 == TX Byte 1 ==
3268 22:12:53.855334 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3269 22:12:53.862000 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3270 22:12:53.862632
3271 22:12:53.863009 [DATLAT]
3272 22:12:53.863353 Freq=1200, CH1 RK0
3273 22:12:53.863685
3274 22:12:53.865747 DATLAT Default: 0xd
3275 22:12:53.866313 0, 0xFFFF, sum = 0
3276 22:12:53.868532 1, 0xFFFF, sum = 0
3277 22:12:53.871983 2, 0xFFFF, sum = 0
3278 22:12:53.872462 3, 0xFFFF, sum = 0
3279 22:12:53.875056 4, 0xFFFF, sum = 0
3280 22:12:53.875530 5, 0xFFFF, sum = 0
3281 22:12:53.879344 6, 0xFFFF, sum = 0
3282 22:12:53.879924 7, 0xFFFF, sum = 0
3283 22:12:53.882285 8, 0xFFFF, sum = 0
3284 22:12:53.882910 9, 0xFFFF, sum = 0
3285 22:12:53.885465 10, 0xFFFF, sum = 0
3286 22:12:53.886045 11, 0xFFFF, sum = 0
3287 22:12:53.888554 12, 0x0, sum = 1
3288 22:12:53.889032 13, 0x0, sum = 2
3289 22:12:53.892090 14, 0x0, sum = 3
3290 22:12:53.892566 15, 0x0, sum = 4
3291 22:12:53.895425 best_step = 13
3292 22:12:53.895892
3293 22:12:53.896258 ==
3294 22:12:53.898777 Dram Type= 6, Freq= 0, CH_1, rank 0
3295 22:12:53.901707 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3296 22:12:53.902170 ==
3297 22:12:53.902598 RX Vref Scan: 1
3298 22:12:53.905208
3299 22:12:53.905661 Set Vref Range= 32 -> 127
3300 22:12:53.906015
3301 22:12:53.908026 RX Vref 32 -> 127, step: 1
3302 22:12:53.908440
3303 22:12:53.911401 RX Delay -13 -> 252, step: 4
3304 22:12:53.911815
3305 22:12:53.915070 Set Vref, RX VrefLevel [Byte0]: 32
3306 22:12:53.918589 [Byte1]: 32
3307 22:12:53.919005
3308 22:12:53.922067 Set Vref, RX VrefLevel [Byte0]: 33
3309 22:12:53.924727 [Byte1]: 33
3310 22:12:53.928824
3311 22:12:53.929446 Set Vref, RX VrefLevel [Byte0]: 34
3312 22:12:53.931921 [Byte1]: 34
3313 22:12:53.936466
3314 22:12:53.936879 Set Vref, RX VrefLevel [Byte0]: 35
3315 22:12:53.939456 [Byte1]: 35
3316 22:12:53.944029
3317 22:12:53.944442 Set Vref, RX VrefLevel [Byte0]: 36
3318 22:12:53.947529 [Byte1]: 36
3319 22:12:53.952217
3320 22:12:53.952629 Set Vref, RX VrefLevel [Byte0]: 37
3321 22:12:53.955257 [Byte1]: 37
3322 22:12:53.960736
3323 22:12:53.961326 Set Vref, RX VrefLevel [Byte0]: 38
3324 22:12:53.963615 [Byte1]: 38
3325 22:12:53.968325
3326 22:12:53.968830 Set Vref, RX VrefLevel [Byte0]: 39
3327 22:12:53.971330 [Byte1]: 39
3328 22:12:53.976619
3329 22:12:53.977128 Set Vref, RX VrefLevel [Byte0]: 40
3330 22:12:53.979210 [Byte1]: 40
3331 22:12:53.983974
3332 22:12:53.984481 Set Vref, RX VrefLevel [Byte0]: 41
3333 22:12:53.987287 [Byte1]: 41
3334 22:12:53.991549
3335 22:12:53.991966 Set Vref, RX VrefLevel [Byte0]: 42
3336 22:12:53.995529 [Byte1]: 42
3337 22:12:53.999665
3338 22:12:54.000174 Set Vref, RX VrefLevel [Byte0]: 43
3339 22:12:54.002779 [Byte1]: 43
3340 22:12:54.008388
3341 22:12:54.008897 Set Vref, RX VrefLevel [Byte0]: 44
3342 22:12:54.010785 [Byte1]: 44
3343 22:12:54.015229
3344 22:12:54.015735 Set Vref, RX VrefLevel [Byte0]: 45
3345 22:12:54.018975 [Byte1]: 45
3346 22:12:54.023188
3347 22:12:54.023734 Set Vref, RX VrefLevel [Byte0]: 46
3348 22:12:54.026590 [Byte1]: 46
3349 22:12:54.031251
3350 22:12:54.031798 Set Vref, RX VrefLevel [Byte0]: 47
3351 22:12:54.034691 [Byte1]: 47
3352 22:12:54.039286
3353 22:12:54.039842 Set Vref, RX VrefLevel [Byte0]: 48
3354 22:12:54.042570 [Byte1]: 48
3355 22:12:54.046586
3356 22:12:54.047043 Set Vref, RX VrefLevel [Byte0]: 49
3357 22:12:54.051799 [Byte1]: 49
3358 22:12:54.055380
3359 22:12:54.055834 Set Vref, RX VrefLevel [Byte0]: 50
3360 22:12:54.057940 [Byte1]: 50
3361 22:12:54.062469
3362 22:12:54.062958 Set Vref, RX VrefLevel [Byte0]: 51
3363 22:12:54.065756 [Byte1]: 51
3364 22:12:54.070466
3365 22:12:54.070924 Set Vref, RX VrefLevel [Byte0]: 52
3366 22:12:54.073661 [Byte1]: 52
3367 22:12:54.078606
3368 22:12:54.079064 Set Vref, RX VrefLevel [Byte0]: 53
3369 22:12:54.081644 [Byte1]: 53
3370 22:12:54.086476
3371 22:12:54.086941 Set Vref, RX VrefLevel [Byte0]: 54
3372 22:12:54.089627 [Byte1]: 54
3373 22:12:54.094669
3374 22:12:54.095168 Set Vref, RX VrefLevel [Byte0]: 55
3375 22:12:54.097383 [Byte1]: 55
3376 22:12:54.102521
3377 22:12:54.102994 Set Vref, RX VrefLevel [Byte0]: 56
3378 22:12:54.105323 [Byte1]: 56
3379 22:12:54.110242
3380 22:12:54.110740 Set Vref, RX VrefLevel [Byte0]: 57
3381 22:12:54.113505 [Byte1]: 57
3382 22:12:54.117775
3383 22:12:54.118021 Set Vref, RX VrefLevel [Byte0]: 58
3384 22:12:54.120897 [Byte1]: 58
3385 22:12:54.126285
3386 22:12:54.126499 Set Vref, RX VrefLevel [Byte0]: 59
3387 22:12:54.128480 [Byte1]: 59
3388 22:12:54.133505
3389 22:12:54.133647 Set Vref, RX VrefLevel [Byte0]: 60
3390 22:12:54.136528 [Byte1]: 60
3391 22:12:54.141072
3392 22:12:54.141197 Set Vref, RX VrefLevel [Byte0]: 61
3393 22:12:54.144184 [Byte1]: 61
3394 22:12:54.149378
3395 22:12:54.149490 Set Vref, RX VrefLevel [Byte0]: 62
3396 22:12:54.152418 [Byte1]: 62
3397 22:12:54.156955
3398 22:12:54.157059 Set Vref, RX VrefLevel [Byte0]: 63
3399 22:12:54.160247 [Byte1]: 63
3400 22:12:54.164706
3401 22:12:54.164801 Set Vref, RX VrefLevel [Byte0]: 64
3402 22:12:54.167851 [Byte1]: 64
3403 22:12:54.172638
3404 22:12:54.172726 Set Vref, RX VrefLevel [Byte0]: 65
3405 22:12:54.175946 [Byte1]: 65
3406 22:12:54.180612
3407 22:12:54.180731 Set Vref, RX VrefLevel [Byte0]: 66
3408 22:12:54.183950 [Byte1]: 66
3409 22:12:54.188541
3410 22:12:54.188671 Set Vref, RX VrefLevel [Byte0]: 67
3411 22:12:54.191674 [Byte1]: 67
3412 22:12:54.196324
3413 22:12:54.196408 Final RX Vref Byte 0 = 51 to rank0
3414 22:12:54.199885 Final RX Vref Byte 1 = 58 to rank0
3415 22:12:54.203334 Final RX Vref Byte 0 = 51 to rank1
3416 22:12:54.206577 Final RX Vref Byte 1 = 58 to rank1==
3417 22:12:54.209908 Dram Type= 6, Freq= 0, CH_1, rank 0
3418 22:12:54.216089 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3419 22:12:54.216253 ==
3420 22:12:54.216331 DQS Delay:
3421 22:12:54.219603 DQS0 = 0, DQS1 = 0
3422 22:12:54.219768 DQM Delay:
3423 22:12:54.222776 DQM0 = 119, DQM1 = 113
3424 22:12:54.222901 DQ Delay:
3425 22:12:54.226138 DQ0 =120, DQ1 =112, DQ2 =112, DQ3 =118
3426 22:12:54.229489 DQ4 =118, DQ5 =128, DQ6 =130, DQ7 =118
3427 22:12:54.232700 DQ8 =102, DQ9 =100, DQ10 =118, DQ11 =106
3428 22:12:54.235955 DQ12 =124, DQ13 =118, DQ14 =120, DQ15 =120
3429 22:12:54.236138
3430 22:12:54.236232
3431 22:12:54.245740 [DQSOSCAuto] RK0, (LSB)MR18= 0xff13, (MSB)MR19= 0x304, tDQSOscB0 = 402 ps tDQSOscB1 = 410 ps
3432 22:12:54.245945 CH1 RK0: MR19=304, MR18=FF13
3433 22:12:54.252691 CH1_RK0: MR19=0x304, MR18=0xFF13, DQSOSC=402, MR23=63, INC=40, DEC=27
3434 22:12:54.252911
3435 22:12:54.255970 ----->DramcWriteLeveling(PI) begin...
3436 22:12:54.256212 ==
3437 22:12:54.258760 Dram Type= 6, Freq= 0, CH_1, rank 1
3438 22:12:54.266329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3439 22:12:54.266636 ==
3440 22:12:54.269669 Write leveling (Byte 0): 25 => 25
3441 22:12:54.272402 Write leveling (Byte 1): 30 => 30
3442 22:12:54.272650 DramcWriteLeveling(PI) end<-----
3443 22:12:54.275900
3444 22:12:54.276304 ==
3445 22:12:54.279042 Dram Type= 6, Freq= 0, CH_1, rank 1
3446 22:12:54.282764 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3447 22:12:54.283264 ==
3448 22:12:54.286006 [Gating] SW mode calibration
3449 22:12:54.292512 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3450 22:12:54.296019 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3451 22:12:54.302535 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3452 22:12:54.305830 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3453 22:12:54.309055 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3454 22:12:54.315982 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3455 22:12:54.318567 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3456 22:12:54.322266 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
3457 22:12:54.328891 0 15 24 | B1->B0 | 2828 3434 | 0 1 | (1 0) (1 0)
3458 22:12:54.332129 0 15 28 | B1->B0 | 2323 2e2e | 0 0 | (1 0) (1 0)
3459 22:12:54.336261 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3460 22:12:54.342477 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3461 22:12:54.346079 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3462 22:12:54.348415 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3463 22:12:54.355501 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3464 22:12:54.358754 1 0 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3465 22:12:54.361505 1 0 24 | B1->B0 | 4141 3131 | 0 1 | (0 0) (0 0)
3466 22:12:54.368041 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3467 22:12:54.371517 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3468 22:12:54.374900 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3469 22:12:54.381819 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3470 22:12:54.385010 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3471 22:12:54.388268 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3472 22:12:54.394712 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3473 22:12:54.398255 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3474 22:12:54.401546 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3475 22:12:54.408159 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3476 22:12:54.411458 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3477 22:12:54.415254 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3478 22:12:54.421498 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3479 22:12:54.424601 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3480 22:12:54.427750 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3481 22:12:54.435144 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3482 22:12:54.438070 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3483 22:12:54.441310 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3484 22:12:54.447447 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3485 22:12:54.450525 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3486 22:12:54.454392 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3487 22:12:54.460808 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3488 22:12:54.464256 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3489 22:12:54.467301 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3490 22:12:54.473896 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3491 22:12:54.477260 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3492 22:12:54.480350 Total UI for P1: 0, mck2ui 16
3493 22:12:54.483745 best dqsien dly found for B0: ( 1, 3, 26)
3494 22:12:54.487060 Total UI for P1: 0, mck2ui 16
3495 22:12:54.490852 best dqsien dly found for B1: ( 1, 3, 26)
3496 22:12:54.493719 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3497 22:12:54.496804 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3498 22:12:54.497272
3499 22:12:54.500300 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3500 22:12:54.503467 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3501 22:12:54.506717 [Gating] SW calibration Done
3502 22:12:54.507311 ==
3503 22:12:54.509991 Dram Type= 6, Freq= 0, CH_1, rank 1
3504 22:12:54.517148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3505 22:12:54.517722 ==
3506 22:12:54.518097 RX Vref Scan: 0
3507 22:12:54.518475
3508 22:12:54.520301 RX Vref 0 -> 0, step: 1
3509 22:12:54.520867
3510 22:12:54.523576 RX Delay -40 -> 252, step: 8
3511 22:12:54.526993 iDelay=200, Bit 0, Center 123 (64 ~ 183) 120
3512 22:12:54.530085 iDelay=200, Bit 1, Center 111 (48 ~ 175) 128
3513 22:12:54.533664 iDelay=200, Bit 2, Center 111 (48 ~ 175) 128
3514 22:12:54.539879 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3515 22:12:54.543179 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
3516 22:12:54.546721 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3517 22:12:54.549616 iDelay=200, Bit 6, Center 123 (56 ~ 191) 136
3518 22:12:54.553427 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3519 22:12:54.556614 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3520 22:12:54.563560 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3521 22:12:54.567045 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3522 22:12:54.569526 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3523 22:12:54.573188 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3524 22:12:54.579715 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3525 22:12:54.582915 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3526 22:12:54.586457 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3527 22:12:54.586924 ==
3528 22:12:54.589774 Dram Type= 6, Freq= 0, CH_1, rank 1
3529 22:12:54.592946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3530 22:12:54.593420 ==
3531 22:12:54.596090 DQS Delay:
3532 22:12:54.596593 DQS0 = 0, DQS1 = 0
3533 22:12:54.600170 DQM Delay:
3534 22:12:54.600741 DQM0 = 119, DQM1 = 113
3535 22:12:54.602646 DQ Delay:
3536 22:12:54.605986 DQ0 =123, DQ1 =111, DQ2 =111, DQ3 =119
3537 22:12:54.609248 DQ4 =123, DQ5 =131, DQ6 =123, DQ7 =115
3538 22:12:54.613179 DQ8 =99, DQ9 =103, DQ10 =115, DQ11 =107
3539 22:12:54.616172 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3540 22:12:54.616745
3541 22:12:54.617118
3542 22:12:54.617458 ==
3543 22:12:54.619447 Dram Type= 6, Freq= 0, CH_1, rank 1
3544 22:12:54.623243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3545 22:12:54.623820 ==
3546 22:12:54.624198
3547 22:12:54.626131
3548 22:12:54.626750 TX Vref Scan disable
3549 22:12:54.628985 == TX Byte 0 ==
3550 22:12:54.632752 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3551 22:12:54.635918 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3552 22:12:54.638940 == TX Byte 1 ==
3553 22:12:54.642236 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3554 22:12:54.645726 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3555 22:12:54.646296 ==
3556 22:12:54.649709 Dram Type= 6, Freq= 0, CH_1, rank 1
3557 22:12:54.655411 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3558 22:12:54.655989 ==
3559 22:12:54.666443 TX Vref=22, minBit 1, minWin=25, winSum=420
3560 22:12:54.669631 TX Vref=24, minBit 1, minWin=25, winSum=423
3561 22:12:54.673482 TX Vref=26, minBit 1, minWin=26, winSum=427
3562 22:12:54.676670 TX Vref=28, minBit 9, minWin=25, winSum=426
3563 22:12:54.680159 TX Vref=30, minBit 0, minWin=26, winSum=427
3564 22:12:54.686514 TX Vref=32, minBit 1, minWin=26, winSum=428
3565 22:12:54.689336 [TxChooseVref] Worse bit 1, Min win 26, Win sum 428, Final Vref 32
3566 22:12:54.689911
3567 22:12:54.692370 Final TX Range 1 Vref 32
3568 22:12:54.692839
3569 22:12:54.693210 ==
3570 22:12:54.695577 Dram Type= 6, Freq= 0, CH_1, rank 1
3571 22:12:54.699088 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3572 22:12:54.702117 ==
3573 22:12:54.702626
3574 22:12:54.702995
3575 22:12:54.703337 TX Vref Scan disable
3576 22:12:54.705797 == TX Byte 0 ==
3577 22:12:54.709559 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3578 22:12:54.716044 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3579 22:12:54.716603 == TX Byte 1 ==
3580 22:12:54.718992 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3581 22:12:54.726328 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3582 22:12:54.726934
3583 22:12:54.727308 [DATLAT]
3584 22:12:54.727652 Freq=1200, CH1 RK1
3585 22:12:54.727983
3586 22:12:54.729014 DATLAT Default: 0xd
3587 22:12:54.732609 0, 0xFFFF, sum = 0
3588 22:12:54.733183 1, 0xFFFF, sum = 0
3589 22:12:54.735657 2, 0xFFFF, sum = 0
3590 22:12:54.736235 3, 0xFFFF, sum = 0
3591 22:12:54.739019 4, 0xFFFF, sum = 0
3592 22:12:54.739492 5, 0xFFFF, sum = 0
3593 22:12:54.742426 6, 0xFFFF, sum = 0
3594 22:12:54.742995 7, 0xFFFF, sum = 0
3595 22:12:54.745962 8, 0xFFFF, sum = 0
3596 22:12:54.746563 9, 0xFFFF, sum = 0
3597 22:12:54.748806 10, 0xFFFF, sum = 0
3598 22:12:54.749382 11, 0xFFFF, sum = 0
3599 22:12:54.752384 12, 0x0, sum = 1
3600 22:12:54.752961 13, 0x0, sum = 2
3601 22:12:54.755620 14, 0x0, sum = 3
3602 22:12:54.756201 15, 0x0, sum = 4
3603 22:12:54.758697 best_step = 13
3604 22:12:54.759267
3605 22:12:54.759640 ==
3606 22:12:54.762009 Dram Type= 6, Freq= 0, CH_1, rank 1
3607 22:12:54.765572 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3608 22:12:54.766149 ==
3609 22:12:54.768846 RX Vref Scan: 0
3610 22:12:54.769415
3611 22:12:54.769788 RX Vref 0 -> 0, step: 1
3612 22:12:54.770134
3613 22:12:54.772297 RX Delay -13 -> 252, step: 4
3614 22:12:54.779087 iDelay=195, Bit 0, Center 122 (63 ~ 182) 120
3615 22:12:54.782406 iDelay=195, Bit 1, Center 114 (55 ~ 174) 120
3616 22:12:54.785157 iDelay=195, Bit 2, Center 108 (51 ~ 166) 116
3617 22:12:54.789006 iDelay=195, Bit 3, Center 118 (59 ~ 178) 120
3618 22:12:54.791756 iDelay=195, Bit 4, Center 120 (59 ~ 182) 124
3619 22:12:54.798391 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3620 22:12:54.801940 iDelay=195, Bit 6, Center 126 (67 ~ 186) 120
3621 22:12:54.805157 iDelay=195, Bit 7, Center 116 (55 ~ 178) 124
3622 22:12:54.808243 iDelay=195, Bit 8, Center 100 (39 ~ 162) 124
3623 22:12:54.811378 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3624 22:12:54.818490 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3625 22:12:54.821131 iDelay=195, Bit 11, Center 108 (43 ~ 174) 132
3626 22:12:54.824929 iDelay=195, Bit 12, Center 122 (59 ~ 186) 128
3627 22:12:54.828238 iDelay=195, Bit 13, Center 122 (59 ~ 186) 128
3628 22:12:54.835028 iDelay=195, Bit 14, Center 120 (59 ~ 182) 124
3629 22:12:54.837771 iDelay=195, Bit 15, Center 124 (59 ~ 190) 132
3630 22:12:54.838239 ==
3631 22:12:54.841446 Dram Type= 6, Freq= 0, CH_1, rank 1
3632 22:12:54.845319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3633 22:12:54.845888 ==
3634 22:12:54.848095 DQS Delay:
3635 22:12:54.848664 DQS0 = 0, DQS1 = 0
3636 22:12:54.849033 DQM Delay:
3637 22:12:54.851034 DQM0 = 119, DQM1 = 114
3638 22:12:54.851502 DQ Delay:
3639 22:12:54.854725 DQ0 =122, DQ1 =114, DQ2 =108, DQ3 =118
3640 22:12:54.858047 DQ4 =120, DQ5 =130, DQ6 =126, DQ7 =116
3641 22:12:54.861043 DQ8 =100, DQ9 =102, DQ10 =114, DQ11 =108
3642 22:12:54.867663 DQ12 =122, DQ13 =122, DQ14 =120, DQ15 =124
3643 22:12:54.868233
3644 22:12:54.868604
3645 22:12:54.874713 [DQSOSCAuto] RK1, (LSB)MR18= 0xbef, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 405 ps
3646 22:12:54.878412 CH1 RK1: MR19=403, MR18=BEF
3647 22:12:54.884923 CH1_RK1: MR19=0x403, MR18=0xBEF, DQSOSC=405, MR23=63, INC=39, DEC=26
3648 22:12:54.887894 [RxdqsGatingPostProcess] freq 1200
3649 22:12:54.890933 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3650 22:12:54.894193 best DQS0 dly(2T, 0.5T) = (0, 11)
3651 22:12:54.897069 best DQS1 dly(2T, 0.5T) = (0, 11)
3652 22:12:54.900586 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3653 22:12:54.904093 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3654 22:12:54.907054 best DQS0 dly(2T, 0.5T) = (0, 11)
3655 22:12:54.910689 best DQS1 dly(2T, 0.5T) = (0, 11)
3656 22:12:54.913946 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3657 22:12:54.917095 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3658 22:12:54.920563 Pre-setting of DQS Precalculation
3659 22:12:54.924727 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3660 22:12:54.933490 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3661 22:12:54.941028 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3662 22:12:54.941609
3663 22:12:54.941983
3664 22:12:54.943647 [Calibration Summary] 2400 Mbps
3665 22:12:54.944220 CH 0, Rank 0
3666 22:12:54.947058 SW Impedance : PASS
3667 22:12:54.947632 DUTY Scan : NO K
3668 22:12:54.950125 ZQ Calibration : PASS
3669 22:12:54.953595 Jitter Meter : NO K
3670 22:12:54.954164 CBT Training : PASS
3671 22:12:54.956716 Write leveling : PASS
3672 22:12:54.960347 RX DQS gating : PASS
3673 22:12:54.960916 RX DQ/DQS(RDDQC) : PASS
3674 22:12:54.963646 TX DQ/DQS : PASS
3675 22:12:54.966987 RX DATLAT : PASS
3676 22:12:54.967559 RX DQ/DQS(Engine): PASS
3677 22:12:54.969870 TX OE : NO K
3678 22:12:54.970397 All Pass.
3679 22:12:54.970779
3680 22:12:54.973344 CH 0, Rank 1
3681 22:12:54.973915 SW Impedance : PASS
3682 22:12:54.976915 DUTY Scan : NO K
3683 22:12:54.980742 ZQ Calibration : PASS
3684 22:12:54.981313 Jitter Meter : NO K
3685 22:12:54.983111 CBT Training : PASS
3686 22:12:54.987197 Write leveling : PASS
3687 22:12:54.987771 RX DQS gating : PASS
3688 22:12:54.989940 RX DQ/DQS(RDDQC) : PASS
3689 22:12:54.993484 TX DQ/DQS : PASS
3690 22:12:54.994056 RX DATLAT : PASS
3691 22:12:54.996436 RX DQ/DQS(Engine): PASS
3692 22:12:54.996904 TX OE : NO K
3693 22:12:54.999794 All Pass.
3694 22:12:55.000354
3695 22:12:55.000724 CH 1, Rank 0
3696 22:12:55.002891 SW Impedance : PASS
3697 22:12:55.003382 DUTY Scan : NO K
3698 22:12:55.006286 ZQ Calibration : PASS
3699 22:12:55.010127 Jitter Meter : NO K
3700 22:12:55.010817 CBT Training : PASS
3701 22:12:55.013030 Write leveling : PASS
3702 22:12:55.016754 RX DQS gating : PASS
3703 22:12:55.017343 RX DQ/DQS(RDDQC) : PASS
3704 22:12:55.019777 TX DQ/DQS : PASS
3705 22:12:55.024307 RX DATLAT : PASS
3706 22:12:55.024863 RX DQ/DQS(Engine): PASS
3707 22:12:55.026829 TX OE : NO K
3708 22:12:55.027317 All Pass.
3709 22:12:55.027695
3710 22:12:55.029777 CH 1, Rank 1
3711 22:12:55.030337 SW Impedance : PASS
3712 22:12:55.032951 DUTY Scan : NO K
3713 22:12:55.036449 ZQ Calibration : PASS
3714 22:12:55.036914 Jitter Meter : NO K
3715 22:12:55.039528 CBT Training : PASS
3716 22:12:55.042933 Write leveling : PASS
3717 22:12:55.043532 RX DQS gating : PASS
3718 22:12:55.046319 RX DQ/DQS(RDDQC) : PASS
3719 22:12:55.050575 TX DQ/DQS : PASS
3720 22:12:55.051187 RX DATLAT : PASS
3721 22:12:55.053025 RX DQ/DQS(Engine): PASS
3722 22:12:55.053587 TX OE : NO K
3723 22:12:55.055880 All Pass.
3724 22:12:55.056384
3725 22:12:55.056787 DramC Write-DBI off
3726 22:12:55.059588 PER_BANK_REFRESH: Hybrid Mode
3727 22:12:55.062921 TX_TRACKING: ON
3728 22:12:55.069518 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3729 22:12:55.072946 [FAST_K] Save calibration result to emmc
3730 22:12:55.079374 dramc_set_vcore_voltage set vcore to 650000
3731 22:12:55.079947 Read voltage for 600, 5
3732 22:12:55.080319 Vio18 = 0
3733 22:12:55.082586 Vcore = 650000
3734 22:12:55.083142 Vdram = 0
3735 22:12:55.083511 Vddq = 0
3736 22:12:55.085848 Vmddr = 0
3737 22:12:55.089352 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3738 22:12:55.095836 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3739 22:12:55.099879 MEM_TYPE=3, freq_sel=19
3740 22:12:55.100441 sv_algorithm_assistance_LP4_1600
3741 22:12:55.106481 ============ PULL DRAM RESETB DOWN ============
3742 22:12:55.109010 ========== PULL DRAM RESETB DOWN end =========
3743 22:12:55.112649 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3744 22:12:55.115746 ===================================
3745 22:12:55.118835 LPDDR4 DRAM CONFIGURATION
3746 22:12:55.122218 ===================================
3747 22:12:55.125321 EX_ROW_EN[0] = 0x0
3748 22:12:55.125914 EX_ROW_EN[1] = 0x0
3749 22:12:55.128918 LP4Y_EN = 0x0
3750 22:12:55.129480 WORK_FSP = 0x0
3751 22:12:55.132866 WL = 0x2
3752 22:12:55.133435 RL = 0x2
3753 22:12:55.135441 BL = 0x2
3754 22:12:55.135898 RPST = 0x0
3755 22:12:55.138983 RD_PRE = 0x0
3756 22:12:55.139542 WR_PRE = 0x1
3757 22:12:55.142745 WR_PST = 0x0
3758 22:12:55.143210 DBI_WR = 0x0
3759 22:12:55.145737 DBI_RD = 0x0
3760 22:12:55.148987 OTF = 0x1
3761 22:12:55.152213 ===================================
3762 22:12:55.152780 ===================================
3763 22:12:55.155612 ANA top config
3764 22:12:55.158625 ===================================
3765 22:12:55.162012 DLL_ASYNC_EN = 0
3766 22:12:55.162631 ALL_SLAVE_EN = 1
3767 22:12:55.165646 NEW_RANK_MODE = 1
3768 22:12:55.168727 DLL_IDLE_MODE = 1
3769 22:12:55.171939 LP45_APHY_COMB_EN = 1
3770 22:12:55.175286 TX_ODT_DIS = 1
3771 22:12:55.175855 NEW_8X_MODE = 1
3772 22:12:55.178518 ===================================
3773 22:12:55.182703 ===================================
3774 22:12:55.185172 data_rate = 1200
3775 22:12:55.188522 CKR = 1
3776 22:12:55.191822 DQ_P2S_RATIO = 8
3777 22:12:55.195257 ===================================
3778 22:12:55.198030 CA_P2S_RATIO = 8
3779 22:12:55.201745 DQ_CA_OPEN = 0
3780 22:12:55.202309 DQ_SEMI_OPEN = 0
3781 22:12:55.204983 CA_SEMI_OPEN = 0
3782 22:12:55.208076 CA_FULL_RATE = 0
3783 22:12:55.211292 DQ_CKDIV4_EN = 1
3784 22:12:55.214666 CA_CKDIV4_EN = 1
3785 22:12:55.218127 CA_PREDIV_EN = 0
3786 22:12:55.218736 PH8_DLY = 0
3787 22:12:55.221464 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3788 22:12:55.224476 DQ_AAMCK_DIV = 4
3789 22:12:55.228040 CA_AAMCK_DIV = 4
3790 22:12:55.231537 CA_ADMCK_DIV = 4
3791 22:12:55.234627 DQ_TRACK_CA_EN = 0
3792 22:12:55.237698 CA_PICK = 600
3793 22:12:55.238169 CA_MCKIO = 600
3794 22:12:55.241084 MCKIO_SEMI = 0
3795 22:12:55.244640 PLL_FREQ = 2288
3796 22:12:55.247795 DQ_UI_PI_RATIO = 32
3797 22:12:55.251501 CA_UI_PI_RATIO = 0
3798 22:12:55.254513 ===================================
3799 22:12:55.257609 ===================================
3800 22:12:55.261064 memory_type:LPDDR4
3801 22:12:55.261635 GP_NUM : 10
3802 22:12:55.264950 SRAM_EN : 1
3803 22:12:55.265525 MD32_EN : 0
3804 22:12:55.267676 ===================================
3805 22:12:55.271070 [ANA_INIT] >>>>>>>>>>>>>>
3806 22:12:55.274419 <<<<<< [CONFIGURE PHASE]: ANA_TX
3807 22:12:55.277727 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3808 22:12:55.281044 ===================================
3809 22:12:55.284565 data_rate = 1200,PCW = 0X5800
3810 22:12:55.288071 ===================================
3811 22:12:55.290813 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3812 22:12:55.297111 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3813 22:12:55.300793 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3814 22:12:55.307057 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3815 22:12:55.310475 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3816 22:12:55.314343 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3817 22:12:55.314954 [ANA_INIT] flow start
3818 22:12:55.317213 [ANA_INIT] PLL >>>>>>>>
3819 22:12:55.320603 [ANA_INIT] PLL <<<<<<<<
3820 22:12:55.321165 [ANA_INIT] MIDPI >>>>>>>>
3821 22:12:55.323738 [ANA_INIT] MIDPI <<<<<<<<
3822 22:12:55.327153 [ANA_INIT] DLL >>>>>>>>
3823 22:12:55.327612 [ANA_INIT] flow end
3824 22:12:55.334046 ============ LP4 DIFF to SE enter ============
3825 22:12:55.337293 ============ LP4 DIFF to SE exit ============
3826 22:12:55.340575 [ANA_INIT] <<<<<<<<<<<<<
3827 22:12:55.343742 [Flow] Enable top DCM control >>>>>
3828 22:12:55.347145 [Flow] Enable top DCM control <<<<<
3829 22:12:55.347609 Enable DLL master slave shuffle
3830 22:12:55.354513 ==============================================================
3831 22:12:55.357345 Gating Mode config
3832 22:12:55.360589 ==============================================================
3833 22:12:55.363986 Config description:
3834 22:12:55.373964 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3835 22:12:55.380004 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3836 22:12:55.383366 SELPH_MODE 0: By rank 1: By Phase
3837 22:12:55.390071 ==============================================================
3838 22:12:55.393417 GAT_TRACK_EN = 1
3839 22:12:55.396902 RX_GATING_MODE = 2
3840 22:12:55.400333 RX_GATING_TRACK_MODE = 2
3841 22:12:55.403610 SELPH_MODE = 1
3842 22:12:55.406749 PICG_EARLY_EN = 1
3843 22:12:55.407322 VALID_LAT_VALUE = 1
3844 22:12:55.413515 ==============================================================
3845 22:12:55.416502 Enter into Gating configuration >>>>
3846 22:12:55.419841 Exit from Gating configuration <<<<
3847 22:12:55.423118 Enter into DVFS_PRE_config >>>>>
3848 22:12:55.433372 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3849 22:12:55.436289 Exit from DVFS_PRE_config <<<<<
3850 22:12:55.439806 Enter into PICG configuration >>>>
3851 22:12:55.442910 Exit from PICG configuration <<<<
3852 22:12:55.446066 [RX_INPUT] configuration >>>>>
3853 22:12:55.449868 [RX_INPUT] configuration <<<<<
3854 22:12:55.456095 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3855 22:12:55.459280 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3856 22:12:55.466521 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3857 22:12:55.473035 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3858 22:12:55.479318 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3859 22:12:55.486415 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3860 22:12:55.489995 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3861 22:12:55.492750 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3862 22:12:55.496656 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3863 22:12:55.502818 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3864 22:12:55.505973 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3865 22:12:55.509314 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3866 22:12:55.512474 ===================================
3867 22:12:55.516559 LPDDR4 DRAM CONFIGURATION
3868 22:12:55.519470 ===================================
3869 22:12:55.520050 EX_ROW_EN[0] = 0x0
3870 22:12:55.523072 EX_ROW_EN[1] = 0x0
3871 22:12:55.523643 LP4Y_EN = 0x0
3872 22:12:55.525997 WORK_FSP = 0x0
3873 22:12:55.529385 WL = 0x2
3874 22:12:55.529956 RL = 0x2
3875 22:12:55.532474 BL = 0x2
3876 22:12:55.533047 RPST = 0x0
3877 22:12:55.535732 RD_PRE = 0x0
3878 22:12:55.536309 WR_PRE = 0x1
3879 22:12:55.539205 WR_PST = 0x0
3880 22:12:55.539680 DBI_WR = 0x0
3881 22:12:55.543121 DBI_RD = 0x0
3882 22:12:55.543694 OTF = 0x1
3883 22:12:55.545421 ===================================
3884 22:12:55.548702 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3885 22:12:55.555433 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3886 22:12:55.558923 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3887 22:12:55.561945 ===================================
3888 22:12:55.565669 LPDDR4 DRAM CONFIGURATION
3889 22:12:55.569109 ===================================
3890 22:12:55.569686 EX_ROW_EN[0] = 0x10
3891 22:12:55.571824 EX_ROW_EN[1] = 0x0
3892 22:12:55.572302 LP4Y_EN = 0x0
3893 22:12:55.575637 WORK_FSP = 0x0
3894 22:12:55.578894 WL = 0x2
3895 22:12:55.579474 RL = 0x2
3896 22:12:55.582497 BL = 0x2
3897 22:12:55.583064 RPST = 0x0
3898 22:12:55.585398 RD_PRE = 0x0
3899 22:12:55.585971 WR_PRE = 0x1
3900 22:12:55.589692 WR_PST = 0x0
3901 22:12:55.590263 DBI_WR = 0x0
3902 22:12:55.593034 DBI_RD = 0x0
3903 22:12:55.593610 OTF = 0x1
3904 22:12:55.594915 ===================================
3905 22:12:55.601619 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3906 22:12:55.606213 nWR fixed to 30
3907 22:12:55.609685 [ModeRegInit_LP4] CH0 RK0
3908 22:12:55.610324 [ModeRegInit_LP4] CH0 RK1
3909 22:12:55.612235 [ModeRegInit_LP4] CH1 RK0
3910 22:12:55.616056 [ModeRegInit_LP4] CH1 RK1
3911 22:12:55.616635 match AC timing 17
3912 22:12:55.622751 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3913 22:12:55.626030 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3914 22:12:55.629002 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3915 22:12:55.635659 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3916 22:12:55.639181 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3917 22:12:55.639754 ==
3918 22:12:55.642335 Dram Type= 6, Freq= 0, CH_0, rank 0
3919 22:12:55.645919 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3920 22:12:55.646518 ==
3921 22:12:55.651982 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3922 22:12:55.658434 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3923 22:12:55.662062 [CA 0] Center 36 (6~66) winsize 61
3924 22:12:55.665847 [CA 1] Center 36 (6~67) winsize 62
3925 22:12:55.668406 [CA 2] Center 34 (4~65) winsize 62
3926 22:12:55.671981 [CA 3] Center 34 (3~65) winsize 63
3927 22:12:55.675910 [CA 4] Center 33 (3~64) winsize 62
3928 22:12:55.678644 [CA 5] Center 33 (2~64) winsize 63
3929 22:12:55.679160
3930 22:12:55.681582 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3931 22:12:55.682137
3932 22:12:55.684861 [CATrainingPosCal] consider 1 rank data
3933 22:12:55.688846 u2DelayCellTimex100 = 270/100 ps
3934 22:12:55.692258 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3935 22:12:55.695008 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3936 22:12:55.698672 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3937 22:12:55.704993 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3938 22:12:55.708307 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3939 22:12:55.711114 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
3940 22:12:55.711577
3941 22:12:55.715618 CA PerBit enable=1, Macro0, CA PI delay=33
3942 22:12:55.716172
3943 22:12:55.717874 [CBTSetCACLKResult] CA Dly = 33
3944 22:12:55.718333 CS Dly: 5 (0~36)
3945 22:12:55.718754 ==
3946 22:12:55.721243 Dram Type= 6, Freq= 0, CH_0, rank 1
3947 22:12:55.727914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3948 22:12:55.728473 ==
3949 22:12:55.731775 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3950 22:12:55.737730 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3951 22:12:55.741840 [CA 0] Center 36 (6~67) winsize 62
3952 22:12:55.744639 [CA 1] Center 36 (6~67) winsize 62
3953 22:12:55.747749 [CA 2] Center 34 (4~65) winsize 62
3954 22:12:55.750858 [CA 3] Center 34 (4~65) winsize 62
3955 22:12:55.754704 [CA 4] Center 34 (3~65) winsize 63
3956 22:12:55.757632 [CA 5] Center 33 (3~64) winsize 62
3957 22:12:55.758114
3958 22:12:55.761498 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3959 22:12:55.762046
3960 22:12:55.764925 [CATrainingPosCal] consider 2 rank data
3961 22:12:55.767420 u2DelayCellTimex100 = 270/100 ps
3962 22:12:55.770899 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3963 22:12:55.777514 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3964 22:12:55.781105 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3965 22:12:55.784415 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3966 22:12:55.787873 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3967 22:12:55.791186 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3968 22:12:55.791751
3969 22:12:55.794114 CA PerBit enable=1, Macro0, CA PI delay=33
3970 22:12:55.794725
3971 22:12:55.797648 [CBTSetCACLKResult] CA Dly = 33
3972 22:12:55.798199 CS Dly: 6 (0~38)
3973 22:12:55.800688
3974 22:12:55.804333 ----->DramcWriteLeveling(PI) begin...
3975 22:12:55.804901 ==
3976 22:12:55.807147 Dram Type= 6, Freq= 0, CH_0, rank 0
3977 22:12:55.810714 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3978 22:12:55.811181 ==
3979 22:12:55.814186 Write leveling (Byte 0): 35 => 35
3980 22:12:55.818007 Write leveling (Byte 1): 32 => 32
3981 22:12:55.821039 DramcWriteLeveling(PI) end<-----
3982 22:12:55.821602
3983 22:12:55.821965 ==
3984 22:12:55.825077 Dram Type= 6, Freq= 0, CH_0, rank 0
3985 22:12:55.827182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3986 22:12:55.827648 ==
3987 22:12:55.831205 [Gating] SW mode calibration
3988 22:12:55.837282 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3989 22:12:55.843775 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3990 22:12:55.847167 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3991 22:12:55.850188 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3992 22:12:55.856769 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3993 22:12:55.860100 0 9 12 | B1->B0 | 3434 2e2e | 1 0 | (0 0) (1 0)
3994 22:12:55.863138 0 9 16 | B1->B0 | 2626 2323 | 0 0 | (0 1) (1 0)
3995 22:12:55.869713 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3996 22:12:55.873004 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3997 22:12:55.876252 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3998 22:12:55.883136 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3999 22:12:55.886389 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4000 22:12:55.889710 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4001 22:12:55.896318 0 10 12 | B1->B0 | 2828 3d3d | 0 0 | (0 0) (0 0)
4002 22:12:55.899440 0 10 16 | B1->B0 | 3a3a 4646 | 1 0 | (0 0) (0 0)
4003 22:12:55.902558 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4004 22:12:55.909472 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4005 22:12:55.912788 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4006 22:12:55.916905 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4007 22:12:55.923079 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4008 22:12:55.926453 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4009 22:12:55.929761 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4010 22:12:55.936333 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4011 22:12:55.938917 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4012 22:12:55.943023 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4013 22:12:55.949191 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4014 22:12:55.952774 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4015 22:12:55.955745 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4016 22:12:55.962400 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4017 22:12:55.966336 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4018 22:12:55.969198 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4019 22:12:55.975178 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4020 22:12:55.978815 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4021 22:12:55.981736 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4022 22:12:55.988482 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4023 22:12:55.991640 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4024 22:12:55.995341 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4025 22:12:56.002110 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4026 22:12:56.005197 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4027 22:12:56.008406 Total UI for P1: 0, mck2ui 16
4028 22:12:56.011292 best dqsien dly found for B0: ( 0, 13, 12)
4029 22:12:56.015257 Total UI for P1: 0, mck2ui 16
4030 22:12:56.018470 best dqsien dly found for B1: ( 0, 13, 14)
4031 22:12:56.021640 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4032 22:12:56.025118 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4033 22:12:56.025677
4034 22:12:56.028575 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4035 22:12:56.035137 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4036 22:12:56.035703 [Gating] SW calibration Done
4037 22:12:56.036080 ==
4038 22:12:56.038229 Dram Type= 6, Freq= 0, CH_0, rank 0
4039 22:12:56.045044 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4040 22:12:56.045609 ==
4041 22:12:56.045985 RX Vref Scan: 0
4042 22:12:56.046329
4043 22:12:56.048709 RX Vref 0 -> 0, step: 1
4044 22:12:56.049268
4045 22:12:56.051278 RX Delay -230 -> 252, step: 16
4046 22:12:56.054632 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4047 22:12:56.058818 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4048 22:12:56.061856 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4049 22:12:56.068040 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4050 22:12:56.071190 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4051 22:12:56.074789 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4052 22:12:56.077800 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4053 22:12:56.085607 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4054 22:12:56.087797 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4055 22:12:56.090761 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4056 22:12:56.094636 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4057 22:12:56.100862 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4058 22:12:56.104276 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4059 22:12:56.108369 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4060 22:12:56.110549 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4061 22:12:56.117682 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4062 22:12:56.118245 ==
4063 22:12:56.121223 Dram Type= 6, Freq= 0, CH_0, rank 0
4064 22:12:56.124428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4065 22:12:56.124998 ==
4066 22:12:56.125373 DQS Delay:
4067 22:12:56.127269 DQS0 = 0, DQS1 = 0
4068 22:12:56.127770 DQM Delay:
4069 22:12:56.131195 DQM0 = 51, DQM1 = 39
4070 22:12:56.131755 DQ Delay:
4071 22:12:56.134741 DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =41
4072 22:12:56.137722 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57
4073 22:12:56.141864 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =33
4074 22:12:56.144420 DQ12 =41, DQ13 =41, DQ14 =57, DQ15 =41
4075 22:12:56.144987
4076 22:12:56.145356
4077 22:12:56.145698 ==
4078 22:12:56.147026 Dram Type= 6, Freq= 0, CH_0, rank 0
4079 22:12:56.150779 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4080 22:12:56.151344 ==
4081 22:12:56.151715
4082 22:12:56.153472
4083 22:12:56.153934 TX Vref Scan disable
4084 22:12:56.157363 == TX Byte 0 ==
4085 22:12:56.160630 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4086 22:12:56.164129 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4087 22:12:56.167009 == TX Byte 1 ==
4088 22:12:56.170687 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4089 22:12:56.173931 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4090 22:12:56.174504 ==
4091 22:12:56.177324 Dram Type= 6, Freq= 0, CH_0, rank 0
4092 22:12:56.183807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4093 22:12:56.184369 ==
4094 22:12:56.184736
4095 22:12:56.185076
4096 22:12:56.187001 TX Vref Scan disable
4097 22:12:56.187472 == TX Byte 0 ==
4098 22:12:56.193764 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4099 22:12:56.196608 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4100 22:12:56.197171 == TX Byte 1 ==
4101 22:12:56.202927 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4102 22:12:56.206973 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4103 22:12:56.207439
4104 22:12:56.207809 [DATLAT]
4105 22:12:56.210010 Freq=600, CH0 RK0
4106 22:12:56.210595
4107 22:12:56.210971 DATLAT Default: 0x9
4108 22:12:56.213218 0, 0xFFFF, sum = 0
4109 22:12:56.213692 1, 0xFFFF, sum = 0
4110 22:12:56.217077 2, 0xFFFF, sum = 0
4111 22:12:56.217650 3, 0xFFFF, sum = 0
4112 22:12:56.219884 4, 0xFFFF, sum = 0
4113 22:12:56.223199 5, 0xFFFF, sum = 0
4114 22:12:56.223672 6, 0xFFFF, sum = 0
4115 22:12:56.226245 7, 0xFFFF, sum = 0
4116 22:12:56.226746 8, 0x0, sum = 1
4117 22:12:56.227123 9, 0x0, sum = 2
4118 22:12:56.229793 10, 0x0, sum = 3
4119 22:12:56.230386 11, 0x0, sum = 4
4120 22:12:56.233368 best_step = 9
4121 22:12:56.233927
4122 22:12:56.234300 ==
4123 22:12:56.236830 Dram Type= 6, Freq= 0, CH_0, rank 0
4124 22:12:56.239851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4125 22:12:56.240418 ==
4126 22:12:56.243276 RX Vref Scan: 1
4127 22:12:56.243839
4128 22:12:56.244215 RX Vref 0 -> 0, step: 1
4129 22:12:56.244561
4130 22:12:56.246702 RX Delay -179 -> 252, step: 8
4131 22:12:56.247264
4132 22:12:56.250160 Set Vref, RX VrefLevel [Byte0]: 60
4133 22:12:56.252969 [Byte1]: 51
4134 22:12:56.257280
4135 22:12:56.257839 Final RX Vref Byte 0 = 60 to rank0
4136 22:12:56.260272 Final RX Vref Byte 1 = 51 to rank0
4137 22:12:56.263731 Final RX Vref Byte 0 = 60 to rank1
4138 22:12:56.267286 Final RX Vref Byte 1 = 51 to rank1==
4139 22:12:56.270395 Dram Type= 6, Freq= 0, CH_0, rank 0
4140 22:12:56.277452 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4141 22:12:56.278017 ==
4142 22:12:56.278438 DQS Delay:
4143 22:12:56.279871 DQS0 = 0, DQS1 = 0
4144 22:12:56.280333 DQM Delay:
4145 22:12:56.280698 DQM0 = 50, DQM1 = 37
4146 22:12:56.283345 DQ Delay:
4147 22:12:56.286758 DQ0 =48, DQ1 =48, DQ2 =48, DQ3 =48
4148 22:12:56.290227 DQ4 =52, DQ5 =40, DQ6 =60, DQ7 =56
4149 22:12:56.293731 DQ8 =32, DQ9 =24, DQ10 =36, DQ11 =32
4150 22:12:56.296315 DQ12 =44, DQ13 =40, DQ14 =48, DQ15 =44
4151 22:12:56.296736
4152 22:12:56.297093
4153 22:12:56.303517 [DQSOSCAuto] RK0, (LSB)MR18= 0x5b55, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 392 ps
4154 22:12:56.306466 CH0 RK0: MR19=808, MR18=5B55
4155 22:12:56.313374 CH0_RK0: MR19=0x808, MR18=0x5B55, DQSOSC=392, MR23=63, INC=170, DEC=113
4156 22:12:56.313941
4157 22:12:56.317004 ----->DramcWriteLeveling(PI) begin...
4158 22:12:56.317573 ==
4159 22:12:56.319703 Dram Type= 6, Freq= 0, CH_0, rank 1
4160 22:12:56.323232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4161 22:12:56.323702 ==
4162 22:12:56.326696 Write leveling (Byte 0): 34 => 34
4163 22:12:56.329712 Write leveling (Byte 1): 30 => 30
4164 22:12:56.333118 DramcWriteLeveling(PI) end<-----
4165 22:12:56.333679
4166 22:12:56.334050 ==
4167 22:12:56.336526 Dram Type= 6, Freq= 0, CH_0, rank 1
4168 22:12:56.339835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4169 22:12:56.340405 ==
4170 22:12:56.343021 [Gating] SW mode calibration
4171 22:12:56.350170 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4172 22:12:56.356252 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4173 22:12:56.359769 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4174 22:12:56.366862 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4175 22:12:56.369629 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4176 22:12:56.373115 0 9 12 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
4177 22:12:56.379458 0 9 16 | B1->B0 | 2727 2525 | 0 0 | (0 0) (0 0)
4178 22:12:56.382908 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4179 22:12:56.385872 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4180 22:12:56.392966 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4181 22:12:56.395501 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4182 22:12:56.399568 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4183 22:12:56.405579 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4184 22:12:56.408972 0 10 12 | B1->B0 | 3030 3232 | 0 0 | (1 1) (0 0)
4185 22:12:56.412099 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4186 22:12:56.418878 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4187 22:12:56.422065 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4188 22:12:56.425623 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4189 22:12:56.432272 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4190 22:12:56.435551 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4191 22:12:56.438676 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4192 22:12:56.445338 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4193 22:12:56.449340 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4194 22:12:56.452153 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4195 22:12:56.458808 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4196 22:12:56.461843 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4197 22:12:56.465294 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4198 22:12:56.471742 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4199 22:12:56.474971 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4200 22:12:56.478797 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4201 22:12:56.485963 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4202 22:12:56.488928 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4203 22:12:56.492073 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4204 22:12:56.498479 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4205 22:12:56.501425 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4206 22:12:56.505072 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4207 22:12:56.511344 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4208 22:12:56.514616 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4209 22:12:56.518429 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4210 22:12:56.521461 Total UI for P1: 0, mck2ui 16
4211 22:12:56.524943 best dqsien dly found for B0: ( 0, 13, 12)
4212 22:12:56.528057 Total UI for P1: 0, mck2ui 16
4213 22:12:56.530998 best dqsien dly found for B1: ( 0, 13, 12)
4214 22:12:56.534249 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4215 22:12:56.537714 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4216 22:12:56.538276
4217 22:12:56.544509 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4218 22:12:56.547770 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4219 22:12:56.548338 [Gating] SW calibration Done
4220 22:12:56.551305 ==
4221 22:12:56.554543 Dram Type= 6, Freq= 0, CH_0, rank 1
4222 22:12:56.557968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4223 22:12:56.558574 ==
4224 22:12:56.558958 RX Vref Scan: 0
4225 22:12:56.559310
4226 22:12:56.560561 RX Vref 0 -> 0, step: 1
4227 22:12:56.561029
4228 22:12:56.564452 RX Delay -230 -> 252, step: 16
4229 22:12:56.567125 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4230 22:12:56.573842 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4231 22:12:56.577346 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4232 22:12:56.580348 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4233 22:12:56.583777 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4234 22:12:56.587098 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4235 22:12:56.593865 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4236 22:12:56.596922 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4237 22:12:56.600211 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4238 22:12:56.603406 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4239 22:12:56.610270 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4240 22:12:56.614433 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4241 22:12:56.616314 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4242 22:12:56.619891 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4243 22:12:56.626520 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4244 22:12:56.629833 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4245 22:12:56.630444 ==
4246 22:12:56.633152 Dram Type= 6, Freq= 0, CH_0, rank 1
4247 22:12:56.636887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4248 22:12:56.637465 ==
4249 22:12:56.639770 DQS Delay:
4250 22:12:56.640487 DQS0 = 0, DQS1 = 0
4251 22:12:56.640871 DQM Delay:
4252 22:12:56.642939 DQM0 = 51, DQM1 = 42
4253 22:12:56.643410 DQ Delay:
4254 22:12:56.646712 DQ0 =41, DQ1 =57, DQ2 =41, DQ3 =49
4255 22:12:56.649656 DQ4 =49, DQ5 =41, DQ6 =65, DQ7 =65
4256 22:12:56.652861 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =41
4257 22:12:56.656335 DQ12 =41, DQ13 =49, DQ14 =57, DQ15 =49
4258 22:12:56.656901
4259 22:12:56.657279
4260 22:12:56.657624 ==
4261 22:12:56.659556 Dram Type= 6, Freq= 0, CH_0, rank 1
4262 22:12:56.666236 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4263 22:12:56.666839 ==
4264 22:12:56.667217
4265 22:12:56.667565
4266 22:12:56.667897 TX Vref Scan disable
4267 22:12:56.669902 == TX Byte 0 ==
4268 22:12:56.673520 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4269 22:12:56.680031 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4270 22:12:56.680595 == TX Byte 1 ==
4271 22:12:56.683216 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4272 22:12:56.689970 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4273 22:12:56.690557 ==
4274 22:12:56.693254 Dram Type= 6, Freq= 0, CH_0, rank 1
4275 22:12:56.696419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4276 22:12:56.696982 ==
4277 22:12:56.697360
4278 22:12:56.697709
4279 22:12:56.699253 TX Vref Scan disable
4280 22:12:56.703218 == TX Byte 0 ==
4281 22:12:56.705883 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4282 22:12:56.709770 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4283 22:12:56.712716 == TX Byte 1 ==
4284 22:12:56.716134 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4285 22:12:56.719935 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4286 22:12:56.720504
4287 22:12:56.720883 [DATLAT]
4288 22:12:56.722879 Freq=600, CH0 RK1
4289 22:12:56.723346
4290 22:12:56.726465 DATLAT Default: 0x9
4291 22:12:56.726926 0, 0xFFFF, sum = 0
4292 22:12:56.729547 1, 0xFFFF, sum = 0
4293 22:12:56.730006 2, 0xFFFF, sum = 0
4294 22:12:56.732435 3, 0xFFFF, sum = 0
4295 22:12:56.732896 4, 0xFFFF, sum = 0
4296 22:12:56.735792 5, 0xFFFF, sum = 0
4297 22:12:56.736253 6, 0xFFFF, sum = 0
4298 22:12:56.739159 7, 0xFFFF, sum = 0
4299 22:12:56.739619 8, 0x0, sum = 1
4300 22:12:56.742236 9, 0x0, sum = 2
4301 22:12:56.742746 10, 0x0, sum = 3
4302 22:12:56.745693 11, 0x0, sum = 4
4303 22:12:56.746155 best_step = 9
4304 22:12:56.746547
4305 22:12:56.746884 ==
4306 22:12:56.749557 Dram Type= 6, Freq= 0, CH_0, rank 1
4307 22:12:56.752806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4308 22:12:56.753128 ==
4309 22:12:56.756068 RX Vref Scan: 0
4310 22:12:56.756387
4311 22:12:56.758926 RX Vref 0 -> 0, step: 1
4312 22:12:56.759243
4313 22:12:56.759491 RX Delay -179 -> 252, step: 8
4314 22:12:56.767203 iDelay=205, Bit 0, Center 44 (-107 ~ 196) 304
4315 22:12:56.770336 iDelay=205, Bit 1, Center 48 (-99 ~ 196) 296
4316 22:12:56.773605 iDelay=205, Bit 2, Center 48 (-99 ~ 196) 296
4317 22:12:56.777042 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4318 22:12:56.783630 iDelay=205, Bit 4, Center 52 (-91 ~ 196) 288
4319 22:12:56.787228 iDelay=205, Bit 5, Center 40 (-107 ~ 188) 296
4320 22:12:56.791261 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4321 22:12:56.793409 iDelay=205, Bit 7, Center 56 (-91 ~ 204) 296
4322 22:12:56.796975 iDelay=205, Bit 8, Center 36 (-107 ~ 180) 288
4323 22:12:56.803078 iDelay=205, Bit 9, Center 28 (-115 ~ 172) 288
4324 22:12:56.806697 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4325 22:12:56.810077 iDelay=205, Bit 11, Center 32 (-115 ~ 180) 296
4326 22:12:56.813571 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4327 22:12:56.820696 iDelay=205, Bit 13, Center 48 (-91 ~ 188) 280
4328 22:12:56.822910 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4329 22:12:56.826643 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4330 22:12:56.827098 ==
4331 22:12:56.829673 Dram Type= 6, Freq= 0, CH_0, rank 1
4332 22:12:56.832938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4333 22:12:56.833498 ==
4334 22:12:56.836417 DQS Delay:
4335 22:12:56.836971 DQS0 = 0, DQS1 = 0
4336 22:12:56.839731 DQM Delay:
4337 22:12:56.840187 DQM0 = 49, DQM1 = 42
4338 22:12:56.840589 DQ Delay:
4339 22:12:56.842814 DQ0 =44, DQ1 =48, DQ2 =48, DQ3 =44
4340 22:12:56.845944 DQ4 =52, DQ5 =40, DQ6 =60, DQ7 =56
4341 22:12:56.849355 DQ8 =36, DQ9 =28, DQ10 =40, DQ11 =32
4342 22:12:56.853131 DQ12 =48, DQ13 =48, DQ14 =52, DQ15 =52
4343 22:12:56.853732
4344 22:12:56.855849
4345 22:12:56.862620 [DQSOSCAuto] RK1, (LSB)MR18= 0x6331, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 391 ps
4346 22:12:56.866437 CH0 RK1: MR19=808, MR18=6331
4347 22:12:56.872636 CH0_RK1: MR19=0x808, MR18=0x6331, DQSOSC=391, MR23=63, INC=171, DEC=114
4348 22:12:56.876016 [RxdqsGatingPostProcess] freq 600
4349 22:12:56.879186 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4350 22:12:56.882629 Pre-setting of DQS Precalculation
4351 22:12:56.889062 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4352 22:12:56.889608 ==
4353 22:12:56.892723 Dram Type= 6, Freq= 0, CH_1, rank 0
4354 22:12:56.896168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4355 22:12:56.896727 ==
4356 22:12:56.902064 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4357 22:12:56.905982 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
4358 22:12:56.909748 [CA 0] Center 35 (5~66) winsize 62
4359 22:12:56.913355 [CA 1] Center 35 (5~66) winsize 62
4360 22:12:56.916437 [CA 2] Center 34 (4~65) winsize 62
4361 22:12:56.919667 [CA 3] Center 34 (3~65) winsize 63
4362 22:12:56.923317 [CA 4] Center 34 (4~65) winsize 62
4363 22:12:56.926453 [CA 5] Center 33 (3~64) winsize 62
4364 22:12:56.927012
4365 22:12:56.929916 [CmdBusTrainingLP45] Vref(ca) range 1: 31
4366 22:12:56.930410
4367 22:12:56.932794 [CATrainingPosCal] consider 1 rank data
4368 22:12:56.936036 u2DelayCellTimex100 = 270/100 ps
4369 22:12:56.939340 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4370 22:12:56.946044 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4371 22:12:56.949471 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4372 22:12:56.952813 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4373 22:12:56.955868 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4374 22:12:56.959347 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4375 22:12:56.959911
4376 22:12:56.962996 CA PerBit enable=1, Macro0, CA PI delay=33
4377 22:12:56.963463
4378 22:12:56.966203 [CBTSetCACLKResult] CA Dly = 33
4379 22:12:56.969324 CS Dly: 5 (0~36)
4380 22:12:56.969878 ==
4381 22:12:56.972768 Dram Type= 6, Freq= 0, CH_1, rank 1
4382 22:12:56.975917 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4383 22:12:56.976387 ==
4384 22:12:56.982413 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4385 22:12:56.985787 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
4386 22:12:56.989796 [CA 0] Center 36 (6~66) winsize 61
4387 22:12:56.993225 [CA 1] Center 36 (6~66) winsize 61
4388 22:12:56.996541 [CA 2] Center 34 (4~65) winsize 62
4389 22:12:57.000753 [CA 3] Center 34 (4~65) winsize 62
4390 22:12:57.002866 [CA 4] Center 34 (4~65) winsize 62
4391 22:12:57.006528 [CA 5] Center 34 (4~65) winsize 62
4392 22:12:57.007096
4393 22:12:57.009394 [CmdBusTrainingLP45] Vref(ca) range 1: 31
4394 22:12:57.009859
4395 22:12:57.013088 [CATrainingPosCal] consider 2 rank data
4396 22:12:57.016056 u2DelayCellTimex100 = 270/100 ps
4397 22:12:57.019730 CA0 delay=36 (6~66),Diff = 2 PI (19 cell)
4398 22:12:57.026215 CA1 delay=36 (6~66),Diff = 2 PI (19 cell)
4399 22:12:57.029485 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4400 22:12:57.033571 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4401 22:12:57.036353 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4402 22:12:57.039556 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4403 22:12:57.040115
4404 22:12:57.042627 CA PerBit enable=1, Macro0, CA PI delay=34
4405 22:12:57.043197
4406 22:12:57.045996 [CBTSetCACLKResult] CA Dly = 34
4407 22:12:57.049095 CS Dly: 5 (0~37)
4408 22:12:57.049658
4409 22:12:57.052339 ----->DramcWriteLeveling(PI) begin...
4410 22:12:57.052906 ==
4411 22:12:57.055830 Dram Type= 6, Freq= 0, CH_1, rank 0
4412 22:12:57.058990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4413 22:12:57.059598 ==
4414 22:12:57.062409 Write leveling (Byte 0): 28 => 28
4415 22:12:57.066085 Write leveling (Byte 1): 31 => 31
4416 22:12:57.069551 DramcWriteLeveling(PI) end<-----
4417 22:12:57.070115
4418 22:12:57.070534 ==
4419 22:12:57.072713 Dram Type= 6, Freq= 0, CH_1, rank 0
4420 22:12:57.075630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4421 22:12:57.076109 ==
4422 22:12:57.079379 [Gating] SW mode calibration
4423 22:12:57.086017 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4424 22:12:57.092367 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4425 22:12:57.095576 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4426 22:12:57.098913 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4427 22:12:57.105714 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4428 22:12:57.109426 0 9 12 | B1->B0 | 2d2d 2e2e | 1 1 | (0 0) (1 1)
4429 22:12:57.112177 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4430 22:12:57.118864 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4431 22:12:57.121945 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4432 22:12:57.125403 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4433 22:12:57.131800 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4434 22:12:57.135304 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4435 22:12:57.138792 0 10 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
4436 22:12:57.144915 0 10 12 | B1->B0 | 3d3d 4040 | 0 0 | (0 0) (0 0)
4437 22:12:57.148546 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4438 22:12:57.151364 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4439 22:12:57.158504 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4440 22:12:57.161464 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4441 22:12:57.164639 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4442 22:12:57.172468 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4443 22:12:57.174615 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4444 22:12:57.177755 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4445 22:12:57.184664 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4446 22:12:57.187916 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4447 22:12:57.191515 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4448 22:12:57.197945 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4449 22:12:57.201247 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4450 22:12:57.205493 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4451 22:12:57.211557 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4452 22:12:57.214434 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4453 22:12:57.217726 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4454 22:12:57.224641 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4455 22:12:57.228222 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4456 22:12:57.231144 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4457 22:12:57.237619 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4458 22:12:57.241599 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4459 22:12:57.244636 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4460 22:12:57.251200 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4461 22:12:57.254517 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4462 22:12:57.257108 Total UI for P1: 0, mck2ui 16
4463 22:12:57.260793 best dqsien dly found for B0: ( 0, 13, 10)
4464 22:12:57.264316 Total UI for P1: 0, mck2ui 16
4465 22:12:57.267418 best dqsien dly found for B1: ( 0, 13, 10)
4466 22:12:57.270770 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4467 22:12:57.274191 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4468 22:12:57.274782
4469 22:12:57.277337 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4470 22:12:57.280311 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4471 22:12:57.284359 [Gating] SW calibration Done
4472 22:12:57.284917 ==
4473 22:12:57.287418 Dram Type= 6, Freq= 0, CH_1, rank 0
4474 22:12:57.290674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4475 22:12:57.293763 ==
4476 22:12:57.294225 RX Vref Scan: 0
4477 22:12:57.294645
4478 22:12:57.297256 RX Vref 0 -> 0, step: 1
4479 22:12:57.297821
4480 22:12:57.300136 RX Delay -230 -> 252, step: 16
4481 22:12:57.303836 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4482 22:12:57.307315 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4483 22:12:57.310110 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4484 22:12:57.317087 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4485 22:12:57.321100 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4486 22:12:57.323778 iDelay=218, Bit 5, Center 57 (-86 ~ 201) 288
4487 22:12:57.326740 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4488 22:12:57.330793 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4489 22:12:57.337112 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4490 22:12:57.340108 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4491 22:12:57.343882 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4492 22:12:57.347614 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4493 22:12:57.353920 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4494 22:12:57.356778 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4495 22:12:57.360053 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4496 22:12:57.363864 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4497 22:12:57.364482 ==
4498 22:12:57.366745 Dram Type= 6, Freq= 0, CH_1, rank 0
4499 22:12:57.373216 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4500 22:12:57.373781 ==
4501 22:12:57.374151 DQS Delay:
4502 22:12:57.376444 DQS0 = 0, DQS1 = 0
4503 22:12:57.376907 DQM Delay:
4504 22:12:57.377276 DQM0 = 50, DQM1 = 40
4505 22:12:57.380029 DQ Delay:
4506 22:12:57.383285 DQ0 =49, DQ1 =49, DQ2 =41, DQ3 =49
4507 22:12:57.386761 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4508 22:12:57.390618 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4509 22:12:57.393561 DQ12 =57, DQ13 =49, DQ14 =41, DQ15 =49
4510 22:12:57.394123
4511 22:12:57.394535
4512 22:12:57.394887 ==
4513 22:12:57.396973 Dram Type= 6, Freq= 0, CH_1, rank 0
4514 22:12:57.400884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4515 22:12:57.401453 ==
4516 22:12:57.401830
4517 22:12:57.402201
4518 22:12:57.403121 TX Vref Scan disable
4519 22:12:57.406251 == TX Byte 0 ==
4520 22:12:57.410101 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4521 22:12:57.413133 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4522 22:12:57.417327 == TX Byte 1 ==
4523 22:12:57.419876 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4524 22:12:57.422811 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4525 22:12:57.423278 ==
4526 22:12:57.426466 Dram Type= 6, Freq= 0, CH_1, rank 0
4527 22:12:57.429913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4528 22:12:57.433943 ==
4529 22:12:57.434541
4530 22:12:57.434915
4531 22:12:57.435257 TX Vref Scan disable
4532 22:12:57.436565 == TX Byte 0 ==
4533 22:12:57.439919 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4534 22:12:57.446793 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4535 22:12:57.447358 == TX Byte 1 ==
4536 22:12:57.449910 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4537 22:12:57.456910 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4538 22:12:57.457473
4539 22:12:57.457847 [DATLAT]
4540 22:12:57.458194 Freq=600, CH1 RK0
4541 22:12:57.458578
4542 22:12:57.459602 DATLAT Default: 0x9
4543 22:12:57.463036 0, 0xFFFF, sum = 0
4544 22:12:57.463608 1, 0xFFFF, sum = 0
4545 22:12:57.466518 2, 0xFFFF, sum = 0
4546 22:12:57.467079 3, 0xFFFF, sum = 0
4547 22:12:57.469877 4, 0xFFFF, sum = 0
4548 22:12:57.470490 5, 0xFFFF, sum = 0
4549 22:12:57.473091 6, 0xFFFF, sum = 0
4550 22:12:57.473671 7, 0xFFFF, sum = 0
4551 22:12:57.476149 8, 0x0, sum = 1
4552 22:12:57.476630 9, 0x0, sum = 2
4553 22:12:57.477008 10, 0x0, sum = 3
4554 22:12:57.479739 11, 0x0, sum = 4
4555 22:12:57.480321 best_step = 9
4556 22:12:57.480699
4557 22:12:57.482926 ==
4558 22:12:57.483396 Dram Type= 6, Freq= 0, CH_1, rank 0
4559 22:12:57.490034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4560 22:12:57.490641 ==
4561 22:12:57.491016 RX Vref Scan: 1
4562 22:12:57.491361
4563 22:12:57.492657 RX Vref 0 -> 0, step: 1
4564 22:12:57.493137
4565 22:12:57.496409 RX Delay -179 -> 252, step: 8
4566 22:12:57.496968
4567 22:12:57.500561 Set Vref, RX VrefLevel [Byte0]: 51
4568 22:12:57.502628 [Byte1]: 58
4569 22:12:57.503100
4570 22:12:57.506461 Final RX Vref Byte 0 = 51 to rank0
4571 22:12:57.509434 Final RX Vref Byte 1 = 58 to rank0
4572 22:12:57.512496 Final RX Vref Byte 0 = 51 to rank1
4573 22:12:57.515695 Final RX Vref Byte 1 = 58 to rank1==
4574 22:12:57.519547 Dram Type= 6, Freq= 0, CH_1, rank 0
4575 22:12:57.522896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4576 22:12:57.523366 ==
4577 22:12:57.525499 DQS Delay:
4578 22:12:57.525964 DQS0 = 0, DQS1 = 0
4579 22:12:57.529305 DQM Delay:
4580 22:12:57.529865 DQM0 = 48, DQM1 = 39
4581 22:12:57.530236 DQ Delay:
4582 22:12:57.532402 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4583 22:12:57.536067 DQ4 =48, DQ5 =60, DQ6 =60, DQ7 =44
4584 22:12:57.539452 DQ8 =28, DQ9 =28, DQ10 =44, DQ11 =32
4585 22:12:57.542519 DQ12 =52, DQ13 =44, DQ14 =44, DQ15 =44
4586 22:12:57.543084
4587 22:12:57.545631
4588 22:12:57.552488 [DQSOSCAuto] RK0, (LSB)MR18= 0x4d74, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps
4589 22:12:57.555343 CH1 RK0: MR19=808, MR18=4D74
4590 22:12:57.562222 CH1_RK0: MR19=0x808, MR18=0x4D74, DQSOSC=388, MR23=63, INC=174, DEC=116
4591 22:12:57.562822
4592 22:12:57.565553 ----->DramcWriteLeveling(PI) begin...
4593 22:12:57.566120 ==
4594 22:12:57.569140 Dram Type= 6, Freq= 0, CH_1, rank 1
4595 22:12:57.572082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4596 22:12:57.572563 ==
4597 22:12:57.575363 Write leveling (Byte 0): 28 => 28
4598 22:12:57.578425 Write leveling (Byte 1): 29 => 29
4599 22:12:57.581953 DramcWriteLeveling(PI) end<-----
4600 22:12:57.582555
4601 22:12:57.582936 ==
4602 22:12:57.585184 Dram Type= 6, Freq= 0, CH_1, rank 1
4603 22:12:57.588398 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4604 22:12:57.588869 ==
4605 22:12:57.591955 [Gating] SW mode calibration
4606 22:12:57.598692 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4607 22:12:57.605513 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4608 22:12:57.608846 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4609 22:12:57.612223 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4610 22:12:57.618387 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
4611 22:12:57.622875 0 9 12 | B1->B0 | 2d2d 3232 | 1 1 | (1 1) (1 0)
4612 22:12:57.625469 0 9 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4613 22:12:57.632209 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4614 22:12:57.635197 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4615 22:12:57.638341 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4616 22:12:57.645284 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4617 22:12:57.648248 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4618 22:12:57.651767 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4619 22:12:57.658343 0 10 12 | B1->B0 | 3e3e 3333 | 0 0 | (0 0) (0 0)
4620 22:12:57.661674 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4621 22:12:57.665048 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4622 22:12:57.671252 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4623 22:12:57.674805 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4624 22:12:57.677621 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4625 22:12:57.684702 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4626 22:12:57.688012 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4627 22:12:57.691138 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4628 22:12:57.698388 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4629 22:12:57.701517 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4630 22:12:57.704325 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4631 22:12:57.711024 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4632 22:12:57.714723 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4633 22:12:57.717445 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4634 22:12:57.724771 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4635 22:12:57.727691 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4636 22:12:57.731067 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4637 22:12:57.738244 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4638 22:12:57.741416 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4639 22:12:57.744676 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4640 22:12:57.751145 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4641 22:12:57.754517 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4642 22:12:57.757695 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4643 22:12:57.764065 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4644 22:12:57.764633 Total UI for P1: 0, mck2ui 16
4645 22:12:57.770897 best dqsien dly found for B0: ( 0, 13, 10)
4646 22:12:57.771458 Total UI for P1: 0, mck2ui 16
4647 22:12:57.777270 best dqsien dly found for B1: ( 0, 13, 10)
4648 22:12:57.780849 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4649 22:12:57.784032 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4650 22:12:57.784587
4651 22:12:57.787752 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4652 22:12:57.790792 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4653 22:12:57.794069 [Gating] SW calibration Done
4654 22:12:57.794574 ==
4655 22:12:57.797867 Dram Type= 6, Freq= 0, CH_1, rank 1
4656 22:12:57.800287 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4657 22:12:57.800956 ==
4658 22:12:57.803844 RX Vref Scan: 0
4659 22:12:57.804391
4660 22:12:57.804761 RX Vref 0 -> 0, step: 1
4661 22:12:57.806868
4662 22:12:57.807425 RX Delay -230 -> 252, step: 16
4663 22:12:57.813655 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4664 22:12:57.816393 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4665 22:12:57.820072 iDelay=218, Bit 2, Center 41 (-102 ~ 185) 288
4666 22:12:57.823048 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4667 22:12:57.830219 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4668 22:12:57.833756 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4669 22:12:57.836578 iDelay=218, Bit 6, Center 57 (-86 ~ 201) 288
4670 22:12:57.839760 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4671 22:12:57.843291 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4672 22:12:57.849880 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4673 22:12:57.853731 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4674 22:12:57.856454 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4675 22:12:57.859588 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4676 22:12:57.866591 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4677 22:12:57.869540 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4678 22:12:57.872849 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4679 22:12:57.873410 ==
4680 22:12:57.876165 Dram Type= 6, Freq= 0, CH_1, rank 1
4681 22:12:57.879203 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4682 22:12:57.882974 ==
4683 22:12:57.883535 DQS Delay:
4684 22:12:57.883905 DQS0 = 0, DQS1 = 0
4685 22:12:57.886499 DQM Delay:
4686 22:12:57.887128 DQM0 = 52, DQM1 = 46
4687 22:12:57.889548 DQ Delay:
4688 22:12:57.892646 DQ0 =57, DQ1 =49, DQ2 =41, DQ3 =49
4689 22:12:57.893274 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4690 22:12:57.895959 DQ8 =25, DQ9 =33, DQ10 =49, DQ11 =41
4691 22:12:57.899112 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4692 22:12:57.902560
4693 22:12:57.903052
4694 22:12:57.903503 ==
4695 22:12:57.905963 Dram Type= 6, Freq= 0, CH_1, rank 1
4696 22:12:57.909383 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4697 22:12:57.909876 ==
4698 22:12:57.910246
4699 22:12:57.910647
4700 22:12:57.912105 TX Vref Scan disable
4701 22:12:57.912581 == TX Byte 0 ==
4702 22:12:57.918544 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4703 22:12:57.922459 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4704 22:12:57.923030 == TX Byte 1 ==
4705 22:12:57.929069 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4706 22:12:57.932318 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4707 22:12:57.932885 ==
4708 22:12:57.935535 Dram Type= 6, Freq= 0, CH_1, rank 1
4709 22:12:57.939391 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4710 22:12:57.939964 ==
4711 22:12:57.940336
4712 22:12:57.941702
4713 22:12:57.942161 TX Vref Scan disable
4714 22:12:57.945553 == TX Byte 0 ==
4715 22:12:57.949023 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4716 22:12:57.955288 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4717 22:12:57.955859 == TX Byte 1 ==
4718 22:12:57.958965 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4719 22:12:57.965538 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4720 22:12:57.966108
4721 22:12:57.966515 [DATLAT]
4722 22:12:57.966864 Freq=600, CH1 RK1
4723 22:12:57.967196
4724 22:12:57.969111 DATLAT Default: 0x9
4725 22:12:57.969677 0, 0xFFFF, sum = 0
4726 22:12:57.971862 1, 0xFFFF, sum = 0
4727 22:12:57.972437 2, 0xFFFF, sum = 0
4728 22:12:57.975890 3, 0xFFFF, sum = 0
4729 22:12:57.978445 4, 0xFFFF, sum = 0
4730 22:12:57.978918 5, 0xFFFF, sum = 0
4731 22:12:57.981809 6, 0xFFFF, sum = 0
4732 22:12:57.982410 7, 0xFFFF, sum = 0
4733 22:12:57.985381 8, 0x0, sum = 1
4734 22:12:57.985953 9, 0x0, sum = 2
4735 22:12:57.986333 10, 0x0, sum = 3
4736 22:12:57.988361 11, 0x0, sum = 4
4737 22:12:57.988937 best_step = 9
4738 22:12:57.989315
4739 22:12:57.989660 ==
4740 22:12:57.991763 Dram Type= 6, Freq= 0, CH_1, rank 1
4741 22:12:57.998348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4742 22:12:57.998956 ==
4743 22:12:57.999329 RX Vref Scan: 0
4744 22:12:57.999692
4745 22:12:58.001325 RX Vref 0 -> 0, step: 1
4746 22:12:58.001790
4747 22:12:58.004929 RX Delay -179 -> 252, step: 8
4748 22:12:58.008188 iDelay=205, Bit 0, Center 52 (-83 ~ 188) 272
4749 22:12:58.014790 iDelay=205, Bit 1, Center 44 (-91 ~ 180) 272
4750 22:12:58.018050 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4751 22:12:58.021937 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4752 22:12:58.024582 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4753 22:12:58.028153 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4754 22:12:58.034908 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4755 22:12:58.038416 iDelay=205, Bit 7, Center 48 (-91 ~ 188) 280
4756 22:12:58.041324 iDelay=205, Bit 8, Center 28 (-115 ~ 172) 288
4757 22:12:58.044822 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4758 22:12:58.051274 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4759 22:12:58.054730 iDelay=205, Bit 11, Center 36 (-115 ~ 188) 304
4760 22:12:58.058212 iDelay=205, Bit 12, Center 52 (-99 ~ 204) 304
4761 22:12:58.061915 iDelay=205, Bit 13, Center 48 (-99 ~ 196) 296
4762 22:12:58.067891 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4763 22:12:58.071668 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4764 22:12:58.072245 ==
4765 22:12:58.074608 Dram Type= 6, Freq= 0, CH_1, rank 1
4766 22:12:58.077726 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4767 22:12:58.078336 ==
4768 22:12:58.078759 DQS Delay:
4769 22:12:58.081147 DQS0 = 0, DQS1 = 0
4770 22:12:58.081716 DQM Delay:
4771 22:12:58.084606 DQM0 = 48, DQM1 = 42
4772 22:12:58.085178 DQ Delay:
4773 22:12:58.088996 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4774 22:12:58.090862 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4775 22:12:58.094262 DQ8 =28, DQ9 =32, DQ10 =40, DQ11 =36
4776 22:12:58.098072 DQ12 =52, DQ13 =48, DQ14 =48, DQ15 =56
4777 22:12:58.098681
4778 22:12:58.099060
4779 22:12:58.107618 [DQSOSCAuto] RK1, (LSB)MR18= 0x541a, (MSB)MR19= 0x808, tDQSOscB0 = 405 ps tDQSOscB1 = 393 ps
4780 22:12:58.108220 CH1 RK1: MR19=808, MR18=541A
4781 22:12:58.113816 CH1_RK1: MR19=0x808, MR18=0x541A, DQSOSC=393, MR23=63, INC=169, DEC=113
4782 22:12:58.117328 [RxdqsGatingPostProcess] freq 600
4783 22:12:58.123738 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4784 22:12:58.127055 Pre-setting of DQS Precalculation
4785 22:12:58.130722 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4786 22:12:58.137454 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4787 22:12:58.147178 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4788 22:12:58.147887
4789 22:12:58.148277
4790 22:12:58.150261 [Calibration Summary] 1200 Mbps
4791 22:12:58.150873 CH 0, Rank 0
4792 22:12:58.153504 SW Impedance : PASS
4793 22:12:58.154068 DUTY Scan : NO K
4794 22:12:58.156703 ZQ Calibration : PASS
4795 22:12:58.160423 Jitter Meter : NO K
4796 22:12:58.160985 CBT Training : PASS
4797 22:12:58.163540 Write leveling : PASS
4798 22:12:58.164103 RX DQS gating : PASS
4799 22:12:58.167357 RX DQ/DQS(RDDQC) : PASS
4800 22:12:58.170312 TX DQ/DQS : PASS
4801 22:12:58.170906 RX DATLAT : PASS
4802 22:12:58.173758 RX DQ/DQS(Engine): PASS
4803 22:12:58.176957 TX OE : NO K
4804 22:12:58.177522 All Pass.
4805 22:12:58.177898
4806 22:12:58.178243 CH 0, Rank 1
4807 22:12:58.180342 SW Impedance : PASS
4808 22:12:58.183412 DUTY Scan : NO K
4809 22:12:58.183977 ZQ Calibration : PASS
4810 22:12:58.186931 Jitter Meter : NO K
4811 22:12:58.190149 CBT Training : PASS
4812 22:12:58.190751 Write leveling : PASS
4813 22:12:58.193728 RX DQS gating : PASS
4814 22:12:58.197278 RX DQ/DQS(RDDQC) : PASS
4815 22:12:58.197840 TX DQ/DQS : PASS
4816 22:12:58.200472 RX DATLAT : PASS
4817 22:12:58.203359 RX DQ/DQS(Engine): PASS
4818 22:12:58.204018 TX OE : NO K
4819 22:12:58.207119 All Pass.
4820 22:12:58.207581
4821 22:12:58.207947 CH 1, Rank 0
4822 22:12:58.209929 SW Impedance : PASS
4823 22:12:58.210429 DUTY Scan : NO K
4824 22:12:58.213204 ZQ Calibration : PASS
4825 22:12:58.216741 Jitter Meter : NO K
4826 22:12:58.217205 CBT Training : PASS
4827 22:12:58.219802 Write leveling : PASS
4828 22:12:58.220289 RX DQS gating : PASS
4829 22:12:58.223310 RX DQ/DQS(RDDQC) : PASS
4830 22:12:58.226134 TX DQ/DQS : PASS
4831 22:12:58.226648 RX DATLAT : PASS
4832 22:12:58.229977 RX DQ/DQS(Engine): PASS
4833 22:12:58.233610 TX OE : NO K
4834 22:12:58.234189 All Pass.
4835 22:12:58.234626
4836 22:12:58.234974 CH 1, Rank 1
4837 22:12:58.236689 SW Impedance : PASS
4838 22:12:58.239535 DUTY Scan : NO K
4839 22:12:58.240001 ZQ Calibration : PASS
4840 22:12:58.243156 Jitter Meter : NO K
4841 22:12:58.246471 CBT Training : PASS
4842 22:12:58.246933 Write leveling : PASS
4843 22:12:58.249735 RX DQS gating : PASS
4844 22:12:58.252514 RX DQ/DQS(RDDQC) : PASS
4845 22:12:58.252982 TX DQ/DQS : PASS
4846 22:12:58.256140 RX DATLAT : PASS
4847 22:12:58.259342 RX DQ/DQS(Engine): PASS
4848 22:12:58.259907 TX OE : NO K
4849 22:12:58.263285 All Pass.
4850 22:12:58.263842
4851 22:12:58.264210 DramC Write-DBI off
4852 22:12:58.266019 PER_BANK_REFRESH: Hybrid Mode
4853 22:12:58.266619 TX_TRACKING: ON
4854 22:12:58.276041 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4855 22:12:58.279451 [FAST_K] Save calibration result to emmc
4856 22:12:58.283248 dramc_set_vcore_voltage set vcore to 662500
4857 22:12:58.285898 Read voltage for 933, 3
4858 22:12:58.286500 Vio18 = 0
4859 22:12:58.289577 Vcore = 662500
4860 22:12:58.290138 Vdram = 0
4861 22:12:58.290549 Vddq = 0
4862 22:12:58.292394 Vmddr = 0
4863 22:12:58.296032 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4864 22:12:58.302797 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4865 22:12:58.303364 MEM_TYPE=3, freq_sel=17
4866 22:12:58.305727 sv_algorithm_assistance_LP4_1600
4867 22:12:58.312255 ============ PULL DRAM RESETB DOWN ============
4868 22:12:58.315301 ========== PULL DRAM RESETB DOWN end =========
4869 22:12:58.319197 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4870 22:12:58.321994 ===================================
4871 22:12:58.325459 LPDDR4 DRAM CONFIGURATION
4872 22:12:58.328673 ===================================
4873 22:12:58.332074 EX_ROW_EN[0] = 0x0
4874 22:12:58.332642 EX_ROW_EN[1] = 0x0
4875 22:12:58.335833 LP4Y_EN = 0x0
4876 22:12:58.336398 WORK_FSP = 0x0
4877 22:12:58.339109 WL = 0x3
4878 22:12:58.339575 RL = 0x3
4879 22:12:58.341978 BL = 0x2
4880 22:12:58.342580 RPST = 0x0
4881 22:12:58.345236 RD_PRE = 0x0
4882 22:12:58.345702 WR_PRE = 0x1
4883 22:12:58.348904 WR_PST = 0x0
4884 22:12:58.349388 DBI_WR = 0x0
4885 22:12:58.352035 DBI_RD = 0x0
4886 22:12:58.352523 OTF = 0x1
4887 22:12:58.355256 ===================================
4888 22:12:58.358499 ===================================
4889 22:12:58.361952 ANA top config
4890 22:12:58.365335 ===================================
4891 22:12:58.365909 DLL_ASYNC_EN = 0
4892 22:12:58.368694 ALL_SLAVE_EN = 1
4893 22:12:58.371741 NEW_RANK_MODE = 1
4894 22:12:58.375041 DLL_IDLE_MODE = 1
4895 22:12:58.378318 LP45_APHY_COMB_EN = 1
4896 22:12:58.378811 TX_ODT_DIS = 1
4897 22:12:58.381776 NEW_8X_MODE = 1
4898 22:12:58.385363 ===================================
4899 22:12:58.388743 ===================================
4900 22:12:58.391974 data_rate = 1866
4901 22:12:58.394874 CKR = 1
4902 22:12:58.398546 DQ_P2S_RATIO = 8
4903 22:12:58.402176 ===================================
4904 22:12:58.404505 CA_P2S_RATIO = 8
4905 22:12:58.404977 DQ_CA_OPEN = 0
4906 22:12:58.408746 DQ_SEMI_OPEN = 0
4907 22:12:58.411798 CA_SEMI_OPEN = 0
4908 22:12:58.415004 CA_FULL_RATE = 0
4909 22:12:58.417704 DQ_CKDIV4_EN = 1
4910 22:12:58.421248 CA_CKDIV4_EN = 1
4911 22:12:58.421824 CA_PREDIV_EN = 0
4912 22:12:58.424334 PH8_DLY = 0
4913 22:12:58.427863 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4914 22:12:58.430906 DQ_AAMCK_DIV = 4
4915 22:12:58.434267 CA_AAMCK_DIV = 4
4916 22:12:58.437613 CA_ADMCK_DIV = 4
4917 22:12:58.438106 DQ_TRACK_CA_EN = 0
4918 22:12:58.441021 CA_PICK = 933
4919 22:12:58.444465 CA_MCKIO = 933
4920 22:12:58.447609 MCKIO_SEMI = 0
4921 22:12:58.451126 PLL_FREQ = 3732
4922 22:12:58.454925 DQ_UI_PI_RATIO = 32
4923 22:12:58.457932 CA_UI_PI_RATIO = 0
4924 22:12:58.460874 ===================================
4925 22:12:58.464271 ===================================
4926 22:12:58.464835 memory_type:LPDDR4
4927 22:12:58.467667 GP_NUM : 10
4928 22:12:58.471305 SRAM_EN : 1
4929 22:12:58.471867 MD32_EN : 0
4930 22:12:58.474627 ===================================
4931 22:12:58.477696 [ANA_INIT] >>>>>>>>>>>>>>
4932 22:12:58.480913 <<<<<< [CONFIGURE PHASE]: ANA_TX
4933 22:12:58.484158 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4934 22:12:58.487274 ===================================
4935 22:12:58.490851 data_rate = 1866,PCW = 0X8f00
4936 22:12:58.494016 ===================================
4937 22:12:58.497942 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4938 22:12:58.501092 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4939 22:12:58.507289 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4940 22:12:58.510529 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4941 22:12:58.516755 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4942 22:12:58.520223 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4943 22:12:58.520697 [ANA_INIT] flow start
4944 22:12:58.524253 [ANA_INIT] PLL >>>>>>>>
4945 22:12:58.526923 [ANA_INIT] PLL <<<<<<<<
4946 22:12:58.527394 [ANA_INIT] MIDPI >>>>>>>>
4947 22:12:58.530608 [ANA_INIT] MIDPI <<<<<<<<
4948 22:12:58.533443 [ANA_INIT] DLL >>>>>>>>
4949 22:12:58.534001 [ANA_INIT] flow end
4950 22:12:58.536775 ============ LP4 DIFF to SE enter ============
4951 22:12:58.543460 ============ LP4 DIFF to SE exit ============
4952 22:12:58.544031 [ANA_INIT] <<<<<<<<<<<<<
4953 22:12:58.546740 [Flow] Enable top DCM control >>>>>
4954 22:12:58.550439 [Flow] Enable top DCM control <<<<<
4955 22:12:58.553297 Enable DLL master slave shuffle
4956 22:12:58.560098 ==============================================================
4957 22:12:58.563316 Gating Mode config
4958 22:12:58.566847 ==============================================================
4959 22:12:58.570251 Config description:
4960 22:12:58.579610 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4961 22:12:58.586747 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4962 22:12:58.590004 SELPH_MODE 0: By rank 1: By Phase
4963 22:12:58.596485 ==============================================================
4964 22:12:58.600188 GAT_TRACK_EN = 1
4965 22:12:58.602842 RX_GATING_MODE = 2
4966 22:12:58.606072 RX_GATING_TRACK_MODE = 2
4967 22:12:58.609743 SELPH_MODE = 1
4968 22:12:58.610306 PICG_EARLY_EN = 1
4969 22:12:58.612960 VALID_LAT_VALUE = 1
4970 22:12:58.619532 ==============================================================
4971 22:12:58.623121 Enter into Gating configuration >>>>
4972 22:12:58.626288 Exit from Gating configuration <<<<
4973 22:12:58.630052 Enter into DVFS_PRE_config >>>>>
4974 22:12:58.639804 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4975 22:12:58.642685 Exit from DVFS_PRE_config <<<<<
4976 22:12:58.646504 Enter into PICG configuration >>>>
4977 22:12:58.649186 Exit from PICG configuration <<<<
4978 22:12:58.652753 [RX_INPUT] configuration >>>>>
4979 22:12:58.655689 [RX_INPUT] configuration <<<<<
4980 22:12:58.659288 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4981 22:12:58.665647 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4982 22:12:58.672721 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4983 22:12:58.678785 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4984 22:12:58.685673 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4985 22:12:58.692592 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4986 22:12:58.695333 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4987 22:12:58.699083 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4988 22:12:58.701865 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4989 22:12:58.708955 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4990 22:12:58.712542 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4991 22:12:58.715808 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4992 22:12:58.718157 ===================================
4993 22:12:58.721950 LPDDR4 DRAM CONFIGURATION
4994 22:12:58.725400 ===================================
4995 22:12:58.725964 EX_ROW_EN[0] = 0x0
4996 22:12:58.728318 EX_ROW_EN[1] = 0x0
4997 22:12:58.728777 LP4Y_EN = 0x0
4998 22:12:58.731816 WORK_FSP = 0x0
4999 22:12:58.735650 WL = 0x3
5000 22:12:58.736210 RL = 0x3
5001 22:12:58.738299 BL = 0x2
5002 22:12:58.738911 RPST = 0x0
5003 22:12:58.741680 RD_PRE = 0x0
5004 22:12:58.742240 WR_PRE = 0x1
5005 22:12:58.745076 WR_PST = 0x0
5006 22:12:58.745638 DBI_WR = 0x0
5007 22:12:58.749518 DBI_RD = 0x0
5008 22:12:58.750101 OTF = 0x1
5009 22:12:58.751296 ===================================
5010 22:12:58.754469 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5011 22:12:58.761543 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5012 22:12:58.764692 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5013 22:12:58.768813 ===================================
5014 22:12:58.771036 LPDDR4 DRAM CONFIGURATION
5015 22:12:58.774727 ===================================
5016 22:12:58.775190 EX_ROW_EN[0] = 0x10
5017 22:12:58.778404 EX_ROW_EN[1] = 0x0
5018 22:12:58.781070 LP4Y_EN = 0x0
5019 22:12:58.781533 WORK_FSP = 0x0
5020 22:12:58.784829 WL = 0x3
5021 22:12:58.785309 RL = 0x3
5022 22:12:58.788054 BL = 0x2
5023 22:12:58.788628 RPST = 0x0
5024 22:12:58.790933 RD_PRE = 0x0
5025 22:12:58.791398 WR_PRE = 0x1
5026 22:12:58.794814 WR_PST = 0x0
5027 22:12:58.795380 DBI_WR = 0x0
5028 22:12:58.797773 DBI_RD = 0x0
5029 22:12:58.798338 OTF = 0x1
5030 22:12:58.801416 ===================================
5031 22:12:58.807827 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5032 22:12:58.812069 nWR fixed to 30
5033 22:12:58.815406 [ModeRegInit_LP4] CH0 RK0
5034 22:12:58.815976 [ModeRegInit_LP4] CH0 RK1
5035 22:12:58.818189 [ModeRegInit_LP4] CH1 RK0
5036 22:12:58.821797 [ModeRegInit_LP4] CH1 RK1
5037 22:12:58.822413 match AC timing 9
5038 22:12:58.828479 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5039 22:12:58.832539 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5040 22:12:58.834584 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5041 22:12:58.841530 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5042 22:12:58.845045 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5043 22:12:58.845618 ==
5044 22:12:58.847961 Dram Type= 6, Freq= 0, CH_0, rank 0
5045 22:12:58.851154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5046 22:12:58.851629 ==
5047 22:12:58.857746 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5048 22:12:58.864449 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5049 22:12:58.867676 [CA 0] Center 37 (7~68) winsize 62
5050 22:12:58.871126 [CA 1] Center 38 (8~69) winsize 62
5051 22:12:58.874728 [CA 2] Center 35 (5~66) winsize 62
5052 22:12:58.878107 [CA 3] Center 35 (5~65) winsize 61
5053 22:12:58.881041 [CA 4] Center 35 (5~65) winsize 61
5054 22:12:58.884706 [CA 5] Center 33 (3~64) winsize 62
5055 22:12:58.885286
5056 22:12:58.887958 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5057 22:12:58.888542
5058 22:12:58.891099 [CATrainingPosCal] consider 1 rank data
5059 22:12:58.894548 u2DelayCellTimex100 = 270/100 ps
5060 22:12:58.897710 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5061 22:12:58.901219 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5062 22:12:58.904826 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5063 22:12:58.907743 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5064 22:12:58.914239 CA4 delay=35 (5~65),Diff = 2 PI (12 cell)
5065 22:12:58.917213 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5066 22:12:58.917720
5067 22:12:58.920827 CA PerBit enable=1, Macro0, CA PI delay=33
5068 22:12:58.921312
5069 22:12:58.924451 [CBTSetCACLKResult] CA Dly = 33
5070 22:12:58.925026 CS Dly: 7 (0~38)
5071 22:12:58.925520 ==
5072 22:12:58.927611 Dram Type= 6, Freq= 0, CH_0, rank 1
5073 22:12:58.934320 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5074 22:12:58.934929 ==
5075 22:12:58.937544 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5076 22:12:58.943897 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5077 22:12:58.947009 [CA 0] Center 38 (8~69) winsize 62
5078 22:12:58.950565 [CA 1] Center 38 (8~69) winsize 62
5079 22:12:58.954054 [CA 2] Center 35 (5~66) winsize 62
5080 22:12:58.957448 [CA 3] Center 35 (5~66) winsize 62
5081 22:12:58.960848 [CA 4] Center 34 (4~65) winsize 62
5082 22:12:58.963816 [CA 5] Center 34 (4~65) winsize 62
5083 22:12:58.964528
5084 22:12:58.966703 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5085 22:12:58.967166
5086 22:12:58.970022 [CATrainingPosCal] consider 2 rank data
5087 22:12:58.973529 u2DelayCellTimex100 = 270/100 ps
5088 22:12:58.976804 CA0 delay=38 (8~68),Diff = 4 PI (24 cell)
5089 22:12:58.983295 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5090 22:12:58.986741 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5091 22:12:58.990179 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5092 22:12:58.993546 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
5093 22:12:58.996622 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5094 22:12:58.997133
5095 22:12:59.000009 CA PerBit enable=1, Macro0, CA PI delay=34
5096 22:12:59.000572
5097 22:12:59.003469 [CBTSetCACLKResult] CA Dly = 34
5098 22:12:59.006290 CS Dly: 7 (0~39)
5099 22:12:59.006860
5100 22:12:59.010031 ----->DramcWriteLeveling(PI) begin...
5101 22:12:59.010645 ==
5102 22:12:59.013971 Dram Type= 6, Freq= 0, CH_0, rank 0
5103 22:12:59.017015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5104 22:12:59.017575 ==
5105 22:12:59.019474 Write leveling (Byte 0): 32 => 32
5106 22:12:59.023533 Write leveling (Byte 1): 31 => 31
5107 22:12:59.026402 DramcWriteLeveling(PI) end<-----
5108 22:12:59.026983
5109 22:12:59.027351 ==
5110 22:12:59.030030 Dram Type= 6, Freq= 0, CH_0, rank 0
5111 22:12:59.032899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5112 22:12:59.033364 ==
5113 22:12:59.036761 [Gating] SW mode calibration
5114 22:12:59.042892 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5115 22:12:59.050270 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5116 22:12:59.052882 0 14 0 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
5117 22:12:59.056277 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5118 22:12:59.062889 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5119 22:12:59.066297 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5120 22:12:59.069428 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5121 22:12:59.076485 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5122 22:12:59.078951 0 14 24 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (1 0)
5123 22:12:59.082907 0 14 28 | B1->B0 | 3030 2323 | 1 0 | (1 0) (1 0)
5124 22:12:59.089484 0 15 0 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
5125 22:12:59.092533 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5126 22:12:59.095746 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5127 22:12:59.102542 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5128 22:12:59.105589 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5129 22:12:59.109259 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5130 22:12:59.115423 0 15 24 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
5131 22:12:59.118868 0 15 28 | B1->B0 | 2b2b 4646 | 0 0 | (1 1) (0 0)
5132 22:12:59.122021 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5133 22:12:59.129138 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5134 22:12:59.132157 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5135 22:12:59.135320 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5136 22:12:59.142132 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5137 22:12:59.145729 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5138 22:12:59.148811 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5139 22:12:59.155011 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5140 22:12:59.158892 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5141 22:12:59.162232 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5142 22:12:59.168867 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5143 22:12:59.172024 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5144 22:12:59.175277 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5145 22:12:59.181799 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5146 22:12:59.185195 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5147 22:12:59.188646 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5148 22:12:59.195191 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5149 22:12:59.198489 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5150 22:12:59.201523 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5151 22:12:59.208235 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5152 22:12:59.212023 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5153 22:12:59.215285 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5154 22:12:59.221508 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5155 22:12:59.225024 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5156 22:12:59.228049 Total UI for P1: 0, mck2ui 16
5157 22:12:59.231260 best dqsien dly found for B0: ( 1, 2, 22)
5158 22:12:59.234975 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5159 22:12:59.238163 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5160 22:12:59.241557 Total UI for P1: 0, mck2ui 16
5161 22:12:59.244867 best dqsien dly found for B1: ( 1, 2, 30)
5162 22:12:59.251737 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5163 22:12:59.254770 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5164 22:12:59.255337
5165 22:12:59.258320 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5166 22:12:59.261368 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5167 22:12:59.264447 [Gating] SW calibration Done
5168 22:12:59.265013 ==
5169 22:12:59.267702 Dram Type= 6, Freq= 0, CH_0, rank 0
5170 22:12:59.271100 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5171 22:12:59.271670 ==
5172 22:12:59.274512 RX Vref Scan: 0
5173 22:12:59.275071
5174 22:12:59.275441 RX Vref 0 -> 0, step: 1
5175 22:12:59.275784
5176 22:12:59.277655 RX Delay -80 -> 252, step: 8
5177 22:12:59.280772 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5178 22:12:59.287902 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5179 22:12:59.291550 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5180 22:12:59.294245 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5181 22:12:59.297821 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5182 22:12:59.300623 iDelay=208, Bit 5, Center 99 (8 ~ 191) 184
5183 22:12:59.304293 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5184 22:12:59.310647 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5185 22:12:59.314342 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5186 22:12:59.317893 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5187 22:12:59.320334 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5188 22:12:59.323558 iDelay=208, Bit 11, Center 91 (8 ~ 175) 168
5189 22:12:59.330642 iDelay=208, Bit 12, Center 95 (8 ~ 183) 176
5190 22:12:59.335038 iDelay=208, Bit 13, Center 95 (8 ~ 183) 176
5191 22:12:59.337270 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5192 22:12:59.340779 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5193 22:12:59.341344 ==
5194 22:12:59.343867 Dram Type= 6, Freq= 0, CH_0, rank 0
5195 22:12:59.347081 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5196 22:12:59.347548 ==
5197 22:12:59.350718 DQS Delay:
5198 22:12:59.351282 DQS0 = 0, DQS1 = 0
5199 22:12:59.353736 DQM Delay:
5200 22:12:59.354298 DQM0 = 106, DQM1 = 91
5201 22:12:59.357252 DQ Delay:
5202 22:12:59.360427 DQ0 =107, DQ1 =107, DQ2 =99, DQ3 =99
5203 22:12:59.363422 DQ4 =107, DQ5 =99, DQ6 =115, DQ7 =115
5204 22:12:59.366662 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =91
5205 22:12:59.370490 DQ12 =95, DQ13 =95, DQ14 =99, DQ15 =99
5206 22:12:59.371057
5207 22:12:59.371423
5208 22:12:59.371764 ==
5209 22:12:59.373421 Dram Type= 6, Freq= 0, CH_0, rank 0
5210 22:12:59.376967 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5211 22:12:59.377536 ==
5212 22:12:59.377909
5213 22:12:59.378251
5214 22:12:59.380260 TX Vref Scan disable
5215 22:12:59.380722 == TX Byte 0 ==
5216 22:12:59.386755 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5217 22:12:59.390290 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5218 22:12:59.390894 == TX Byte 1 ==
5219 22:12:59.396887 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5220 22:12:59.399796 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5221 22:12:59.400368 ==
5222 22:12:59.403651 Dram Type= 6, Freq= 0, CH_0, rank 0
5223 22:12:59.406479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5224 22:12:59.406950 ==
5225 22:12:59.407353
5226 22:12:59.409684
5227 22:12:59.410243 TX Vref Scan disable
5228 22:12:59.412937 == TX Byte 0 ==
5229 22:12:59.416435 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5230 22:12:59.419488 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5231 22:12:59.423848 == TX Byte 1 ==
5232 22:12:59.426094 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5233 22:12:59.429369 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5234 22:12:59.432838
5235 22:12:59.433254 [DATLAT]
5236 22:12:59.433585 Freq=933, CH0 RK0
5237 22:12:59.433894
5238 22:12:59.436242 DATLAT Default: 0xd
5239 22:12:59.436760 0, 0xFFFF, sum = 0
5240 22:12:59.439805 1, 0xFFFF, sum = 0
5241 22:12:59.440335 2, 0xFFFF, sum = 0
5242 22:12:59.442708 3, 0xFFFF, sum = 0
5243 22:12:59.446048 4, 0xFFFF, sum = 0
5244 22:12:59.446500 5, 0xFFFF, sum = 0
5245 22:12:59.449352 6, 0xFFFF, sum = 0
5246 22:12:59.449878 7, 0xFFFF, sum = 0
5247 22:12:59.452583 8, 0xFFFF, sum = 0
5248 22:12:59.453009 9, 0xFFFF, sum = 0
5249 22:12:59.455957 10, 0x0, sum = 1
5250 22:12:59.456379 11, 0x0, sum = 2
5251 22:12:59.459553 12, 0x0, sum = 3
5252 22:12:59.459991 13, 0x0, sum = 4
5253 22:12:59.460327 best_step = 11
5254 22:12:59.460634
5255 22:12:59.462732 ==
5256 22:12:59.465793 Dram Type= 6, Freq= 0, CH_0, rank 0
5257 22:12:59.469019 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5258 22:12:59.469543 ==
5259 22:12:59.469883 RX Vref Scan: 1
5260 22:12:59.470191
5261 22:12:59.472319 RX Vref 0 -> 0, step: 1
5262 22:12:59.472831
5263 22:12:59.476336 RX Delay -53 -> 252, step: 4
5264 22:12:59.476856
5265 22:12:59.479005 Set Vref, RX VrefLevel [Byte0]: 60
5266 22:12:59.482409 [Byte1]: 51
5267 22:12:59.482939
5268 22:12:59.485751 Final RX Vref Byte 0 = 60 to rank0
5269 22:12:59.489104 Final RX Vref Byte 1 = 51 to rank0
5270 22:12:59.492336 Final RX Vref Byte 0 = 60 to rank1
5271 22:12:59.495831 Final RX Vref Byte 1 = 51 to rank1==
5272 22:12:59.498947 Dram Type= 6, Freq= 0, CH_0, rank 0
5273 22:12:59.502458 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5274 22:12:59.505379 ==
5275 22:12:59.505896 DQS Delay:
5276 22:12:59.506227 DQS0 = 0, DQS1 = 0
5277 22:12:59.509356 DQM Delay:
5278 22:12:59.509774 DQM0 = 107, DQM1 = 92
5279 22:12:59.512125 DQ Delay:
5280 22:12:59.515209 DQ0 =106, DQ1 =108, DQ2 =104, DQ3 =106
5281 22:12:59.518520 DQ4 =108, DQ5 =98, DQ6 =116, DQ7 =116
5282 22:12:59.521820 DQ8 =86, DQ9 =78, DQ10 =94, DQ11 =90
5283 22:12:59.525186 DQ12 =96, DQ13 =94, DQ14 =104, DQ15 =100
5284 22:12:59.525707
5285 22:12:59.526042
5286 22:12:59.532198 [DQSOSCAuto] RK0, (LSB)MR18= 0x221e, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 411 ps
5287 22:12:59.534847 CH0 RK0: MR19=505, MR18=221E
5288 22:12:59.541890 CH0_RK0: MR19=0x505, MR18=0x221E, DQSOSC=411, MR23=63, INC=64, DEC=42
5289 22:12:59.542459
5290 22:12:59.545534 ----->DramcWriteLeveling(PI) begin...
5291 22:12:59.546060 ==
5292 22:12:59.548436 Dram Type= 6, Freq= 0, CH_0, rank 1
5293 22:12:59.551342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5294 22:12:59.551754 ==
5295 22:12:59.555005 Write leveling (Byte 0): 34 => 34
5296 22:12:59.557985 Write leveling (Byte 1): 27 => 27
5297 22:12:59.561349 DramcWriteLeveling(PI) end<-----
5298 22:12:59.561758
5299 22:12:59.562075 ==
5300 22:12:59.564916 Dram Type= 6, Freq= 0, CH_0, rank 1
5301 22:12:59.572169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5302 22:12:59.572683 ==
5303 22:12:59.573010 [Gating] SW mode calibration
5304 22:12:59.581674 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5305 22:12:59.584727 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5306 22:12:59.587841 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5307 22:12:59.594845 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5308 22:12:59.597749 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5309 22:12:59.601222 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5310 22:12:59.607857 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5311 22:12:59.611302 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5312 22:12:59.614443 0 14 24 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
5313 22:12:59.620864 0 14 28 | B1->B0 | 2e2e 2626 | 0 0 | (0 1) (0 0)
5314 22:12:59.623970 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5315 22:12:59.627341 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5316 22:12:59.634443 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5317 22:12:59.637823 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5318 22:12:59.641357 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5319 22:12:59.647812 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5320 22:12:59.651070 0 15 24 | B1->B0 | 2727 2e2e | 0 0 | (0 0) (0 0)
5321 22:12:59.654489 0 15 28 | B1->B0 | 3b3b 4444 | 0 0 | (0 0) (0 0)
5322 22:12:59.660435 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5323 22:12:59.664950 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5324 22:12:59.668008 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5325 22:12:59.673823 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5326 22:12:59.677991 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5327 22:12:59.680436 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5328 22:12:59.687507 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5329 22:12:59.690514 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5330 22:12:59.694861 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5331 22:12:59.700602 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5332 22:12:59.704319 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5333 22:12:59.707188 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5334 22:12:59.713463 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5335 22:12:59.716863 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5336 22:12:59.720716 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5337 22:12:59.726458 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5338 22:12:59.729799 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5339 22:12:59.733644 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5340 22:12:59.740103 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5341 22:12:59.743598 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5342 22:12:59.746647 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5343 22:12:59.752712 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5344 22:12:59.756687 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5345 22:12:59.759452 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5346 22:12:59.762864 Total UI for P1: 0, mck2ui 16
5347 22:12:59.766966 best dqsien dly found for B0: ( 1, 2, 24)
5348 22:12:59.772701 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5349 22:12:59.776025 Total UI for P1: 0, mck2ui 16
5350 22:12:59.779269 best dqsien dly found for B1: ( 1, 2, 26)
5351 22:12:59.782243 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5352 22:12:59.786190 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5353 22:12:59.786780
5354 22:12:59.789790 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5355 22:12:59.793334 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5356 22:12:59.796229 [Gating] SW calibration Done
5357 22:12:59.796781 ==
5358 22:12:59.799151 Dram Type= 6, Freq= 0, CH_0, rank 1
5359 22:12:59.802425 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5360 22:12:59.802984 ==
5361 22:12:59.805819 RX Vref Scan: 0
5362 22:12:59.806401
5363 22:12:59.809141 RX Vref 0 -> 0, step: 1
5364 22:12:59.809697
5365 22:12:59.810059 RX Delay -80 -> 252, step: 8
5366 22:12:59.815643 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5367 22:12:59.819133 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5368 22:12:59.821779 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5369 22:12:59.825289 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5370 22:12:59.828673 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5371 22:12:59.835612 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5372 22:12:59.838332 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5373 22:12:59.842135 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5374 22:12:59.845153 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5375 22:12:59.848795 iDelay=208, Bit 9, Center 83 (0 ~ 167) 168
5376 22:12:59.852575 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5377 22:12:59.858411 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5378 22:12:59.861668 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5379 22:12:59.865138 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5380 22:12:59.868457 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5381 22:12:59.871749 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5382 22:12:59.872306 ==
5383 22:12:59.875129 Dram Type= 6, Freq= 0, CH_0, rank 1
5384 22:12:59.881916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5385 22:12:59.882527 ==
5386 22:12:59.882911 DQS Delay:
5387 22:12:59.883402 DQS0 = 0, DQS1 = 0
5388 22:12:59.885570 DQM Delay:
5389 22:12:59.886124 DQM0 = 104, DQM1 = 91
5390 22:12:59.888539 DQ Delay:
5391 22:12:59.891539 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5392 22:12:59.895074 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =111
5393 22:12:59.898399 DQ8 =87, DQ9 =83, DQ10 =91, DQ11 =87
5394 22:12:59.901641 DQ12 =95, DQ13 =91, DQ14 =99, DQ15 =99
5395 22:12:59.902200
5396 22:12:59.902624
5397 22:12:59.902972 ==
5398 22:12:59.904652 Dram Type= 6, Freq= 0, CH_0, rank 1
5399 22:12:59.908171 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5400 22:12:59.908654 ==
5401 22:12:59.909024
5402 22:12:59.909363
5403 22:12:59.912896 TX Vref Scan disable
5404 22:12:59.914602 == TX Byte 0 ==
5405 22:12:59.918264 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5406 22:12:59.921408 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5407 22:12:59.924522 == TX Byte 1 ==
5408 22:12:59.928401 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5409 22:12:59.931721 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5410 22:12:59.932330 ==
5411 22:12:59.934866 Dram Type= 6, Freq= 0, CH_0, rank 1
5412 22:12:59.938032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5413 22:12:59.941419 ==
5414 22:12:59.941968
5415 22:12:59.942335
5416 22:12:59.942726 TX Vref Scan disable
5417 22:12:59.945819 == TX Byte 0 ==
5418 22:12:59.947922 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5419 22:12:59.955331 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5420 22:12:59.955888 == TX Byte 1 ==
5421 22:12:59.958001 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5422 22:12:59.964577 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5423 22:12:59.965152
5424 22:12:59.965524 [DATLAT]
5425 22:12:59.965867 Freq=933, CH0 RK1
5426 22:12:59.966200
5427 22:12:59.967894 DATLAT Default: 0xb
5428 22:12:59.968450 0, 0xFFFF, sum = 0
5429 22:12:59.971741 1, 0xFFFF, sum = 0
5430 22:12:59.974689 2, 0xFFFF, sum = 0
5431 22:12:59.975251 3, 0xFFFF, sum = 0
5432 22:12:59.977965 4, 0xFFFF, sum = 0
5433 22:12:59.978572 5, 0xFFFF, sum = 0
5434 22:12:59.981322 6, 0xFFFF, sum = 0
5435 22:12:59.981880 7, 0xFFFF, sum = 0
5436 22:12:59.984399 8, 0xFFFF, sum = 0
5437 22:12:59.984962 9, 0xFFFF, sum = 0
5438 22:12:59.988027 10, 0x0, sum = 1
5439 22:12:59.988596 11, 0x0, sum = 2
5440 22:12:59.991160 12, 0x0, sum = 3
5441 22:12:59.991725 13, 0x0, sum = 4
5442 22:12:59.992102 best_step = 11
5443 22:12:59.994967
5444 22:12:59.995522 ==
5445 22:12:59.997639 Dram Type= 6, Freq= 0, CH_0, rank 1
5446 22:13:00.001256 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5447 22:13:00.001821 ==
5448 22:13:00.002195 RX Vref Scan: 0
5449 22:13:00.002596
5450 22:13:00.004914 RX Vref 0 -> 0, step: 1
5451 22:13:00.005468
5452 22:13:00.007166 RX Delay -45 -> 252, step: 4
5453 22:13:00.014160 iDelay=203, Bit 0, Center 104 (19 ~ 190) 172
5454 22:13:00.017893 iDelay=203, Bit 1, Center 106 (19 ~ 194) 176
5455 22:13:00.020487 iDelay=203, Bit 2, Center 102 (15 ~ 190) 176
5456 22:13:00.023869 iDelay=203, Bit 3, Center 98 (15 ~ 182) 168
5457 22:13:00.028015 iDelay=203, Bit 4, Center 104 (19 ~ 190) 172
5458 22:13:00.033782 iDelay=203, Bit 5, Center 96 (11 ~ 182) 172
5459 22:13:00.037186 iDelay=203, Bit 6, Center 114 (27 ~ 202) 176
5460 22:13:00.040712 iDelay=203, Bit 7, Center 110 (23 ~ 198) 176
5461 22:13:00.043977 iDelay=203, Bit 8, Center 84 (-1 ~ 170) 172
5462 22:13:00.047583 iDelay=203, Bit 9, Center 78 (-5 ~ 162) 168
5463 22:13:00.050684 iDelay=203, Bit 10, Center 92 (7 ~ 178) 172
5464 22:13:00.057189 iDelay=203, Bit 11, Center 92 (11 ~ 174) 164
5465 22:13:00.060149 iDelay=203, Bit 12, Center 96 (11 ~ 182) 172
5466 22:13:00.063682 iDelay=203, Bit 13, Center 94 (11 ~ 178) 168
5467 22:13:00.067024 iDelay=203, Bit 14, Center 100 (15 ~ 186) 172
5468 22:13:00.073707 iDelay=203, Bit 15, Center 100 (19 ~ 182) 164
5469 22:13:00.074270 ==
5470 22:13:00.076776 Dram Type= 6, Freq= 0, CH_0, rank 1
5471 22:13:00.080431 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5472 22:13:00.080991 ==
5473 22:13:00.081364 DQS Delay:
5474 22:13:00.083152 DQS0 = 0, DQS1 = 0
5475 22:13:00.083653 DQM Delay:
5476 22:13:00.087047 DQM0 = 104, DQM1 = 92
5477 22:13:00.087610 DQ Delay:
5478 22:13:00.090021 DQ0 =104, DQ1 =106, DQ2 =102, DQ3 =98
5479 22:13:00.093143 DQ4 =104, DQ5 =96, DQ6 =114, DQ7 =110
5480 22:13:00.097015 DQ8 =84, DQ9 =78, DQ10 =92, DQ11 =92
5481 22:13:00.100422 DQ12 =96, DQ13 =94, DQ14 =100, DQ15 =100
5482 22:13:00.100991
5483 22:13:00.101362
5484 22:13:00.110055 [DQSOSCAuto] RK1, (LSB)MR18= 0x2608, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 409 ps
5485 22:13:00.110655 CH0 RK1: MR19=505, MR18=2608
5486 22:13:00.117386 CH0_RK1: MR19=0x505, MR18=0x2608, DQSOSC=409, MR23=63, INC=64, DEC=43
5487 22:13:00.119683 [RxdqsGatingPostProcess] freq 933
5488 22:13:00.127024 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5489 22:13:00.129760 best DQS0 dly(2T, 0.5T) = (0, 10)
5490 22:13:00.133286 best DQS1 dly(2T, 0.5T) = (0, 10)
5491 22:13:00.136650 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5492 22:13:00.139653 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5493 22:13:00.143691 best DQS0 dly(2T, 0.5T) = (0, 10)
5494 22:13:00.144281 best DQS1 dly(2T, 0.5T) = (0, 10)
5495 22:13:00.146333 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5496 22:13:00.149701 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5497 22:13:00.153096 Pre-setting of DQS Precalculation
5498 22:13:00.159481 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5499 22:13:00.160084 ==
5500 22:13:00.162725 Dram Type= 6, Freq= 0, CH_1, rank 0
5501 22:13:00.166475 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5502 22:13:00.166911 ==
5503 22:13:00.172716 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5504 22:13:00.179886 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
5505 22:13:00.183710 [CA 0] Center 37 (7~68) winsize 62
5506 22:13:00.186375 [CA 1] Center 37 (7~68) winsize 62
5507 22:13:00.189420 [CA 2] Center 35 (5~66) winsize 62
5508 22:13:00.192823 [CA 3] Center 35 (5~65) winsize 61
5509 22:13:00.196766 [CA 4] Center 35 (5~66) winsize 62
5510 22:13:00.199625 [CA 5] Center 34 (4~65) winsize 62
5511 22:13:00.200192
5512 22:13:00.202912 [CmdBusTrainingLP45] Vref(ca) range 1: 31
5513 22:13:00.203479
5514 22:13:00.206594 [CATrainingPosCal] consider 1 rank data
5515 22:13:00.209427 u2DelayCellTimex100 = 270/100 ps
5516 22:13:00.213145 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5517 22:13:00.216140 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5518 22:13:00.219241 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5519 22:13:00.222494 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5520 22:13:00.225433 CA4 delay=35 (5~66),Diff = 1 PI (6 cell)
5521 22:13:00.229559 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
5522 22:13:00.230125
5523 22:13:00.235606 CA PerBit enable=1, Macro0, CA PI delay=34
5524 22:13:00.236169
5525 22:13:00.238571 [CBTSetCACLKResult] CA Dly = 34
5526 22:13:00.239030 CS Dly: 6 (0~37)
5527 22:13:00.239396 ==
5528 22:13:00.242021 Dram Type= 6, Freq= 0, CH_1, rank 1
5529 22:13:00.245434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5530 22:13:00.246002 ==
5531 22:13:00.251858 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5532 22:13:00.258481 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
5533 22:13:00.261878 [CA 0] Center 38 (8~68) winsize 61
5534 22:13:00.265246 [CA 1] Center 38 (8~69) winsize 62
5535 22:13:00.268636 [CA 2] Center 36 (6~66) winsize 61
5536 22:13:00.271446 [CA 3] Center 35 (4~66) winsize 63
5537 22:13:00.275524 [CA 4] Center 36 (6~66) winsize 61
5538 22:13:00.278403 [CA 5] Center 34 (4~65) winsize 62
5539 22:13:00.278870
5540 22:13:00.281815 [CmdBusTrainingLP45] Vref(ca) range 1: 31
5541 22:13:00.282413
5542 22:13:00.284799 [CATrainingPosCal] consider 2 rank data
5543 22:13:00.288888 u2DelayCellTimex100 = 270/100 ps
5544 22:13:00.292041 CA0 delay=38 (8~68),Diff = 4 PI (24 cell)
5545 22:13:00.295097 CA1 delay=38 (8~68),Diff = 4 PI (24 cell)
5546 22:13:00.298514 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5547 22:13:00.301697 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5548 22:13:00.308699 CA4 delay=36 (6~66),Diff = 2 PI (12 cell)
5549 22:13:00.311565 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
5550 22:13:00.312131
5551 22:13:00.314951 CA PerBit enable=1, Macro0, CA PI delay=34
5552 22:13:00.315515
5553 22:13:00.319166 [CBTSetCACLKResult] CA Dly = 34
5554 22:13:00.319732 CS Dly: 7 (0~39)
5555 22:13:00.320105
5556 22:13:00.321240 ----->DramcWriteLeveling(PI) begin...
5557 22:13:00.321707 ==
5558 22:13:00.324858 Dram Type= 6, Freq= 0, CH_1, rank 0
5559 22:13:00.331500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5560 22:13:00.332067 ==
5561 22:13:00.334814 Write leveling (Byte 0): 27 => 27
5562 22:13:00.338508 Write leveling (Byte 1): 29 => 29
5563 22:13:00.339071 DramcWriteLeveling(PI) end<-----
5564 22:13:00.341359
5565 22:13:00.341920 ==
5566 22:13:00.344919 Dram Type= 6, Freq= 0, CH_1, rank 0
5567 22:13:00.348473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5568 22:13:00.349039 ==
5569 22:13:00.351548 [Gating] SW mode calibration
5570 22:13:00.358158 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5571 22:13:00.360839 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5572 22:13:00.368261 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5573 22:13:00.371077 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5574 22:13:00.374588 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5575 22:13:00.381803 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5576 22:13:00.384208 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5577 22:13:00.387530 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5578 22:13:00.394623 0 14 24 | B1->B0 | 3434 3030 | 0 0 | (0 1) (1 1)
5579 22:13:00.397785 0 14 28 | B1->B0 | 2828 2323 | 0 0 | (1 0) (1 0)
5580 22:13:00.401319 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5581 22:13:00.407731 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5582 22:13:00.411022 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5583 22:13:00.414325 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5584 22:13:00.420995 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5585 22:13:00.424361 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5586 22:13:00.427203 0 15 24 | B1->B0 | 2626 2828 | 0 0 | (0 0) (1 1)
5587 22:13:00.434486 0 15 28 | B1->B0 | 3939 3e3e | 1 0 | (0 0) (0 0)
5588 22:13:00.437668 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5589 22:13:00.440549 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5590 22:13:00.448027 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5591 22:13:00.450678 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5592 22:13:00.454296 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5593 22:13:00.461040 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5594 22:13:00.463911 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5595 22:13:00.467458 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5596 22:13:00.473921 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5597 22:13:00.477313 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5598 22:13:00.480367 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5599 22:13:00.486908 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5600 22:13:00.490792 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5601 22:13:00.493676 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5602 22:13:00.500217 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5603 22:13:00.503955 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5604 22:13:00.506750 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5605 22:13:00.513296 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5606 22:13:00.516818 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5607 22:13:00.520085 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5608 22:13:00.526677 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5609 22:13:00.530100 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5610 22:13:00.533632 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5611 22:13:00.540061 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5612 22:13:00.540633 Total UI for P1: 0, mck2ui 16
5613 22:13:00.546743 best dqsien dly found for B0: ( 1, 2, 22)
5614 22:13:00.547312 Total UI for P1: 0, mck2ui 16
5615 22:13:00.553314 best dqsien dly found for B1: ( 1, 2, 24)
5616 22:13:00.556801 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5617 22:13:00.559539 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5618 22:13:00.560112
5619 22:13:00.562820 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5620 22:13:00.566494 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5621 22:13:00.569526 [Gating] SW calibration Done
5622 22:13:00.570085 ==
5623 22:13:00.573375 Dram Type= 6, Freq= 0, CH_1, rank 0
5624 22:13:00.576455 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5625 22:13:00.576929 ==
5626 22:13:00.579554 RX Vref Scan: 0
5627 22:13:00.580119
5628 22:13:00.580498 RX Vref 0 -> 0, step: 1
5629 22:13:00.580848
5630 22:13:00.583067 RX Delay -80 -> 252, step: 8
5631 22:13:00.585946 iDelay=208, Bit 0, Center 103 (16 ~ 191) 176
5632 22:13:00.592620 iDelay=208, Bit 1, Center 95 (8 ~ 183) 176
5633 22:13:00.596149 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5634 22:13:00.599596 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5635 22:13:00.602553 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5636 22:13:00.606562 iDelay=208, Bit 5, Center 111 (24 ~ 199) 176
5637 22:13:00.609600 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5638 22:13:00.616236 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5639 22:13:00.619601 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5640 22:13:00.622854 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5641 22:13:00.625982 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5642 22:13:00.629076 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5643 22:13:00.633097 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5644 22:13:00.639285 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5645 22:13:00.642747 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5646 22:13:00.646147 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5647 22:13:00.646765 ==
5648 22:13:00.649087 Dram Type= 6, Freq= 0, CH_1, rank 0
5649 22:13:00.652645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5650 22:13:00.653216 ==
5651 22:13:00.655311 DQS Delay:
5652 22:13:00.655776 DQS0 = 0, DQS1 = 0
5653 22:13:00.659461 DQM Delay:
5654 22:13:00.660029 DQM0 = 101, DQM1 = 96
5655 22:13:00.660402 DQ Delay:
5656 22:13:00.662147 DQ0 =103, DQ1 =95, DQ2 =91, DQ3 =99
5657 22:13:00.665790 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =99
5658 22:13:00.668902 DQ8 =83, DQ9 =83, DQ10 =99, DQ11 =91
5659 22:13:00.675810 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5660 22:13:00.676541
5661 22:13:00.676947
5662 22:13:00.677296 ==
5663 22:13:00.679058 Dram Type= 6, Freq= 0, CH_1, rank 0
5664 22:13:00.682096 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5665 22:13:00.682714 ==
5666 22:13:00.683094
5667 22:13:00.683439
5668 22:13:00.685299 TX Vref Scan disable
5669 22:13:00.685788 == TX Byte 0 ==
5670 22:13:00.692133 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5671 22:13:00.695171 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5672 22:13:00.695745 == TX Byte 1 ==
5673 22:13:00.701580 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5674 22:13:00.705361 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5675 22:13:00.706127 ==
5676 22:13:00.708408 Dram Type= 6, Freq= 0, CH_1, rank 0
5677 22:13:00.711783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5678 22:13:00.712356 ==
5679 22:13:00.714865
5680 22:13:00.715424
5681 22:13:00.715938 TX Vref Scan disable
5682 22:13:00.718043 == TX Byte 0 ==
5683 22:13:00.721840 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5684 22:13:00.728692 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5685 22:13:00.729412 == TX Byte 1 ==
5686 22:13:00.731719 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5687 22:13:00.738083 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5688 22:13:00.738692
5689 22:13:00.739074 [DATLAT]
5690 22:13:00.739420 Freq=933, CH1 RK0
5691 22:13:00.739757
5692 22:13:00.741451 DATLAT Default: 0xd
5693 22:13:00.741911 0, 0xFFFF, sum = 0
5694 22:13:00.744425 1, 0xFFFF, sum = 0
5695 22:13:00.748036 2, 0xFFFF, sum = 0
5696 22:13:00.748603 3, 0xFFFF, sum = 0
5697 22:13:00.750966 4, 0xFFFF, sum = 0
5698 22:13:00.751440 5, 0xFFFF, sum = 0
5699 22:13:00.754767 6, 0xFFFF, sum = 0
5700 22:13:00.755335 7, 0xFFFF, sum = 0
5701 22:13:00.758238 8, 0xFFFF, sum = 0
5702 22:13:00.758867 9, 0xFFFF, sum = 0
5703 22:13:00.761288 10, 0x0, sum = 1
5704 22:13:00.761864 11, 0x0, sum = 2
5705 22:13:00.764566 12, 0x0, sum = 3
5706 22:13:00.765138 13, 0x0, sum = 4
5707 22:13:00.765519 best_step = 11
5708 22:13:00.767781
5709 22:13:00.768343 ==
5710 22:13:00.771186 Dram Type= 6, Freq= 0, CH_1, rank 0
5711 22:13:00.774312 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5712 22:13:00.774918 ==
5713 22:13:00.775294 RX Vref Scan: 1
5714 22:13:00.775637
5715 22:13:00.777897 RX Vref 0 -> 0, step: 1
5716 22:13:00.778538
5717 22:13:00.781019 RX Delay -53 -> 252, step: 4
5718 22:13:00.781581
5719 22:13:00.784768 Set Vref, RX VrefLevel [Byte0]: 51
5720 22:13:00.787904 [Byte1]: 58
5721 22:13:00.791020
5722 22:13:00.791592 Final RX Vref Byte 0 = 51 to rank0
5723 22:13:00.794239 Final RX Vref Byte 1 = 58 to rank0
5724 22:13:00.797532 Final RX Vref Byte 0 = 51 to rank1
5725 22:13:00.800880 Final RX Vref Byte 1 = 58 to rank1==
5726 22:13:00.804679 Dram Type= 6, Freq= 0, CH_1, rank 0
5727 22:13:00.810848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5728 22:13:00.811420 ==
5729 22:13:00.811795 DQS Delay:
5730 22:13:00.812140 DQS0 = 0, DQS1 = 0
5731 22:13:00.814835 DQM Delay:
5732 22:13:00.815300 DQM0 = 104, DQM1 = 98
5733 22:13:00.817380 DQ Delay:
5734 22:13:00.820716 DQ0 =108, DQ1 =98, DQ2 =96, DQ3 =102
5735 22:13:00.824076 DQ4 =104, DQ5 =112, DQ6 =114, DQ7 =100
5736 22:13:00.827137 DQ8 =88, DQ9 =84, DQ10 =102, DQ11 =92
5737 22:13:00.830280 DQ12 =108, DQ13 =104, DQ14 =102, DQ15 =104
5738 22:13:00.830786
5739 22:13:00.831160
5740 22:13:00.840505 [DQSOSCAuto] RK0, (LSB)MR18= 0x1b33, (MSB)MR19= 0x505, tDQSOscB0 = 405 ps tDQSOscB1 = 413 ps
5741 22:13:00.841082 CH1 RK0: MR19=505, MR18=1B33
5742 22:13:00.846916 CH1_RK0: MR19=0x505, MR18=0x1B33, DQSOSC=405, MR23=63, INC=66, DEC=44
5743 22:13:00.847486
5744 22:13:00.850345 ----->DramcWriteLeveling(PI) begin...
5745 22:13:00.850948 ==
5746 22:13:00.853470 Dram Type= 6, Freq= 0, CH_1, rank 1
5747 22:13:00.860155 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5748 22:13:00.860734 ==
5749 22:13:00.863167 Write leveling (Byte 0): 27 => 27
5750 22:13:00.863647 Write leveling (Byte 1): 27 => 27
5751 22:13:00.866917 DramcWriteLeveling(PI) end<-----
5752 22:13:00.867486
5753 22:13:00.867853 ==
5754 22:13:00.870121 Dram Type= 6, Freq= 0, CH_1, rank 1
5755 22:13:00.876878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5756 22:13:00.877451 ==
5757 22:13:00.880515 [Gating] SW mode calibration
5758 22:13:00.886639 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5759 22:13:00.889735 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5760 22:13:00.896454 0 14 0 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
5761 22:13:00.900128 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5762 22:13:00.903152 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5763 22:13:00.909472 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5764 22:13:00.912789 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5765 22:13:00.916455 0 14 20 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5766 22:13:00.923429 0 14 24 | B1->B0 | 3030 3333 | 0 1 | (0 1) (1 1)
5767 22:13:00.925961 0 14 28 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (1 1)
5768 22:13:00.929431 0 15 0 | B1->B0 | 2323 2626 | 0 1 | (0 0) (0 0)
5769 22:13:00.936278 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5770 22:13:00.939179 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5771 22:13:00.942844 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5772 22:13:00.949885 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5773 22:13:00.952625 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5774 22:13:00.956423 0 15 24 | B1->B0 | 2f2f 2a2a | 0 0 | (0 0) (1 1)
5775 22:13:00.963196 0 15 28 | B1->B0 | 4444 3a3a | 0 0 | (0 0) (0 0)
5776 22:13:00.966533 1 0 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
5777 22:13:00.969444 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5778 22:13:00.976249 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5779 22:13:00.979297 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5780 22:13:00.982731 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5781 22:13:00.989380 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5782 22:13:00.994170 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5783 22:13:00.995112 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5784 22:13:01.002088 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5785 22:13:01.005381 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5786 22:13:01.008836 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5787 22:13:01.015309 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5788 22:13:01.018814 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5789 22:13:01.021975 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5790 22:13:01.028649 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5791 22:13:01.031482 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5792 22:13:01.035188 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5793 22:13:01.042409 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5794 22:13:01.045028 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5795 22:13:01.048560 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5796 22:13:01.054947 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5797 22:13:01.058200 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5798 22:13:01.061871 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5799 22:13:01.068858 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5800 22:13:01.071685 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5801 22:13:01.075116 Total UI for P1: 0, mck2ui 16
5802 22:13:01.078227 best dqsien dly found for B0: ( 1, 2, 26)
5803 22:13:01.081457 Total UI for P1: 0, mck2ui 16
5804 22:13:01.084634 best dqsien dly found for B1: ( 1, 2, 26)
5805 22:13:01.088250 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5806 22:13:01.091796 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5807 22:13:01.092375
5808 22:13:01.094968 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5809 22:13:01.097846 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5810 22:13:01.101361 [Gating] SW calibration Done
5811 22:13:01.101942 ==
5812 22:13:01.104644 Dram Type= 6, Freq= 0, CH_1, rank 1
5813 22:13:01.107963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5814 22:13:01.108532 ==
5815 22:13:01.110885 RX Vref Scan: 0
5816 22:13:01.111351
5817 22:13:01.114231 RX Vref 0 -> 0, step: 1
5818 22:13:01.114730
5819 22:13:01.115101 RX Delay -80 -> 252, step: 8
5820 22:13:01.121053 iDelay=200, Bit 0, Center 103 (16 ~ 191) 176
5821 22:13:01.124535 iDelay=200, Bit 1, Center 99 (16 ~ 183) 168
5822 22:13:01.127486 iDelay=200, Bit 2, Center 87 (0 ~ 175) 176
5823 22:13:01.130981 iDelay=200, Bit 3, Center 99 (8 ~ 191) 184
5824 22:13:01.134699 iDelay=200, Bit 4, Center 103 (16 ~ 191) 176
5825 22:13:01.140865 iDelay=200, Bit 5, Center 107 (16 ~ 199) 184
5826 22:13:01.144278 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5827 22:13:01.148356 iDelay=200, Bit 7, Center 103 (16 ~ 191) 176
5828 22:13:01.150745 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5829 22:13:01.154226 iDelay=200, Bit 9, Center 83 (-8 ~ 175) 184
5830 22:13:01.157664 iDelay=200, Bit 10, Center 95 (0 ~ 191) 192
5831 22:13:01.164712 iDelay=200, Bit 11, Center 87 (-8 ~ 183) 192
5832 22:13:01.167663 iDelay=200, Bit 12, Center 107 (16 ~ 199) 184
5833 22:13:01.170743 iDelay=200, Bit 13, Center 103 (8 ~ 199) 192
5834 22:13:01.174017 iDelay=200, Bit 14, Center 99 (8 ~ 191) 184
5835 22:13:01.177491 iDelay=200, Bit 15, Center 103 (8 ~ 199) 192
5836 22:13:01.180990 ==
5837 22:13:01.184128 Dram Type= 6, Freq= 0, CH_1, rank 1
5838 22:13:01.187884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5839 22:13:01.188451 ==
5840 22:13:01.188822 DQS Delay:
5841 22:13:01.190663 DQS0 = 0, DQS1 = 0
5842 22:13:01.191220 DQM Delay:
5843 22:13:01.193871 DQM0 = 101, DQM1 = 95
5844 22:13:01.194469 DQ Delay:
5845 22:13:01.197046 DQ0 =103, DQ1 =99, DQ2 =87, DQ3 =99
5846 22:13:01.200620 DQ4 =103, DQ5 =107, DQ6 =107, DQ7 =103
5847 22:13:01.203942 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87
5848 22:13:01.208045 DQ12 =107, DQ13 =103, DQ14 =99, DQ15 =103
5849 22:13:01.208611
5850 22:13:01.209021
5851 22:13:01.209361 ==
5852 22:13:01.210296 Dram Type= 6, Freq= 0, CH_1, rank 1
5853 22:13:01.216972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5854 22:13:01.217712 ==
5855 22:13:01.218118
5856 22:13:01.218509
5857 22:13:01.218902 TX Vref Scan disable
5858 22:13:01.219768 == TX Byte 0 ==
5859 22:13:01.223404 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5860 22:13:01.226704 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5861 22:13:01.230181 == TX Byte 1 ==
5862 22:13:01.233624 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5863 22:13:01.240051 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5864 22:13:01.240617 ==
5865 22:13:01.243342 Dram Type= 6, Freq= 0, CH_1, rank 1
5866 22:13:01.246748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5867 22:13:01.247348 ==
5868 22:13:01.247723
5869 22:13:01.248064
5870 22:13:01.249657 TX Vref Scan disable
5871 22:13:01.250116 == TX Byte 0 ==
5872 22:13:01.256857 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5873 22:13:01.260349 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5874 22:13:01.260925 == TX Byte 1 ==
5875 22:13:01.266535 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5876 22:13:01.269970 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5877 22:13:01.270567
5878 22:13:01.270939 [DATLAT]
5879 22:13:01.273180 Freq=933, CH1 RK1
5880 22:13:01.273754
5881 22:13:01.274125 DATLAT Default: 0xb
5882 22:13:01.276705 0, 0xFFFF, sum = 0
5883 22:13:01.277274 1, 0xFFFF, sum = 0
5884 22:13:01.280842 2, 0xFFFF, sum = 0
5885 22:13:01.281413 3, 0xFFFF, sum = 0
5886 22:13:01.283356 4, 0xFFFF, sum = 0
5887 22:13:01.286836 5, 0xFFFF, sum = 0
5888 22:13:01.287439 6, 0xFFFF, sum = 0
5889 22:13:01.289834 7, 0xFFFF, sum = 0
5890 22:13:01.290424 8, 0xFFFF, sum = 0
5891 22:13:01.293136 9, 0xFFFF, sum = 0
5892 22:13:01.293704 10, 0x0, sum = 1
5893 22:13:01.296429 11, 0x0, sum = 2
5894 22:13:01.296999 12, 0x0, sum = 3
5895 22:13:01.297380 13, 0x0, sum = 4
5896 22:13:01.299718 best_step = 11
5897 22:13:01.300280
5898 22:13:01.300652 ==
5899 22:13:01.303024 Dram Type= 6, Freq= 0, CH_1, rank 1
5900 22:13:01.306683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5901 22:13:01.307250 ==
5902 22:13:01.310087 RX Vref Scan: 0
5903 22:13:01.310770
5904 22:13:01.311146 RX Vref 0 -> 0, step: 1
5905 22:13:01.313245
5906 22:13:01.313834 RX Delay -53 -> 252, step: 4
5907 22:13:01.320511 iDelay=199, Bit 0, Center 110 (35 ~ 186) 152
5908 22:13:01.323547 iDelay=199, Bit 1, Center 98 (19 ~ 178) 160
5909 22:13:01.326668 iDelay=199, Bit 2, Center 94 (15 ~ 174) 160
5910 22:13:01.330103 iDelay=199, Bit 3, Center 102 (19 ~ 186) 168
5911 22:13:01.333639 iDelay=199, Bit 4, Center 104 (23 ~ 186) 164
5912 22:13:01.340100 iDelay=199, Bit 5, Center 116 (35 ~ 198) 164
5913 22:13:01.343292 iDelay=199, Bit 6, Center 110 (27 ~ 194) 168
5914 22:13:01.346832 iDelay=199, Bit 7, Center 102 (23 ~ 182) 160
5915 22:13:01.350261 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5916 22:13:01.353855 iDelay=199, Bit 9, Center 86 (-1 ~ 174) 176
5917 22:13:01.360303 iDelay=199, Bit 10, Center 98 (11 ~ 186) 176
5918 22:13:01.363686 iDelay=199, Bit 11, Center 92 (7 ~ 178) 172
5919 22:13:01.367091 iDelay=199, Bit 12, Center 110 (27 ~ 194) 168
5920 22:13:01.370274 iDelay=199, Bit 13, Center 104 (19 ~ 190) 172
5921 22:13:01.373265 iDelay=199, Bit 14, Center 104 (19 ~ 190) 172
5922 22:13:01.380119 iDelay=199, Bit 15, Center 106 (19 ~ 194) 176
5923 22:13:01.380679 ==
5924 22:13:01.383517 Dram Type= 6, Freq= 0, CH_1, rank 1
5925 22:13:01.387099 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5926 22:13:01.387691 ==
5927 22:13:01.388062 DQS Delay:
5928 22:13:01.389743 DQS0 = 0, DQS1 = 0
5929 22:13:01.390308 DQM Delay:
5930 22:13:01.393053 DQM0 = 104, DQM1 = 98
5931 22:13:01.393617 DQ Delay:
5932 22:13:01.396464 DQ0 =110, DQ1 =98, DQ2 =94, DQ3 =102
5933 22:13:01.399823 DQ4 =104, DQ5 =116, DQ6 =110, DQ7 =102
5934 22:13:01.403497 DQ8 =84, DQ9 =86, DQ10 =98, DQ11 =92
5935 22:13:01.406767 DQ12 =110, DQ13 =104, DQ14 =104, DQ15 =106
5936 22:13:01.407333
5937 22:13:01.407701
5938 22:13:01.416749 [DQSOSCAuto] RK1, (LSB)MR18= 0x22fe, (MSB)MR19= 0x504, tDQSOscB0 = 422 ps tDQSOscB1 = 411 ps
5939 22:13:01.419667 CH1 RK1: MR19=504, MR18=22FE
5940 22:13:01.425937 CH1_RK1: MR19=0x504, MR18=0x22FE, DQSOSC=411, MR23=63, INC=64, DEC=42
5941 22:13:01.426645 [RxdqsGatingPostProcess] freq 933
5942 22:13:01.432618 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5943 22:13:01.435691 best DQS0 dly(2T, 0.5T) = (0, 10)
5944 22:13:01.439133 best DQS1 dly(2T, 0.5T) = (0, 10)
5945 22:13:01.442712 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5946 22:13:01.445980 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5947 22:13:01.449869 best DQS0 dly(2T, 0.5T) = (0, 10)
5948 22:13:01.452432 best DQS1 dly(2T, 0.5T) = (0, 10)
5949 22:13:01.455714 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5950 22:13:01.459694 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5951 22:13:01.462191 Pre-setting of DQS Precalculation
5952 22:13:01.465614 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5953 22:13:01.472233 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5954 22:13:01.482235 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5955 22:13:01.482839
5956 22:13:01.483209
5957 22:13:01.485309 [Calibration Summary] 1866 Mbps
5958 22:13:01.485869 CH 0, Rank 0
5959 22:13:01.488884 SW Impedance : PASS
5960 22:13:01.489443 DUTY Scan : NO K
5961 22:13:01.491969 ZQ Calibration : PASS
5962 22:13:01.492535 Jitter Meter : NO K
5963 22:13:01.495279 CBT Training : PASS
5964 22:13:01.498936 Write leveling : PASS
5965 22:13:01.499494 RX DQS gating : PASS
5966 22:13:01.502175 RX DQ/DQS(RDDQC) : PASS
5967 22:13:01.505516 TX DQ/DQS : PASS
5968 22:13:01.506082 RX DATLAT : PASS
5969 22:13:01.508821 RX DQ/DQS(Engine): PASS
5970 22:13:01.512333 TX OE : NO K
5971 22:13:01.512897 All Pass.
5972 22:13:01.513266
5973 22:13:01.513608 CH 0, Rank 1
5974 22:13:01.514938 SW Impedance : PASS
5975 22:13:01.518543 DUTY Scan : NO K
5976 22:13:01.519098 ZQ Calibration : PASS
5977 22:13:01.521858 Jitter Meter : NO K
5978 22:13:01.525063 CBT Training : PASS
5979 22:13:01.525630 Write leveling : PASS
5980 22:13:01.528397 RX DQS gating : PASS
5981 22:13:01.531434 RX DQ/DQS(RDDQC) : PASS
5982 22:13:01.531948 TX DQ/DQS : PASS
5983 22:13:01.534718 RX DATLAT : PASS
5984 22:13:01.538286 RX DQ/DQS(Engine): PASS
5985 22:13:01.538892 TX OE : NO K
5986 22:13:01.541208 All Pass.
5987 22:13:01.541680
5988 22:13:01.542115 CH 1, Rank 0
5989 22:13:01.544767 SW Impedance : PASS
5990 22:13:01.545326 DUTY Scan : NO K
5991 22:13:01.547989 ZQ Calibration : PASS
5992 22:13:01.551402 Jitter Meter : NO K
5993 22:13:01.551948 CBT Training : PASS
5994 22:13:01.554470 Write leveling : PASS
5995 22:13:01.554932 RX DQS gating : PASS
5996 22:13:01.557754 RX DQ/DQS(RDDQC) : PASS
5997 22:13:01.561078 TX DQ/DQS : PASS
5998 22:13:01.561542 RX DATLAT : PASS
5999 22:13:01.564635 RX DQ/DQS(Engine): PASS
6000 22:13:01.568279 TX OE : NO K
6001 22:13:01.568846 All Pass.
6002 22:13:01.569213
6003 22:13:01.569548 CH 1, Rank 1
6004 22:13:01.571813 SW Impedance : PASS
6005 22:13:01.574534 DUTY Scan : NO K
6006 22:13:01.574993 ZQ Calibration : PASS
6007 22:13:01.578030 Jitter Meter : NO K
6008 22:13:01.581268 CBT Training : PASS
6009 22:13:01.581823 Write leveling : PASS
6010 22:13:01.585829 RX DQS gating : PASS
6011 22:13:01.587982 RX DQ/DQS(RDDQC) : PASS
6012 22:13:01.588445 TX DQ/DQS : PASS
6013 22:13:01.591397 RX DATLAT : PASS
6014 22:13:01.595003 RX DQ/DQS(Engine): PASS
6015 22:13:01.595566 TX OE : NO K
6016 22:13:01.597894 All Pass.
6017 22:13:01.598497
6018 22:13:01.598878 DramC Write-DBI off
6019 22:13:01.601323 PER_BANK_REFRESH: Hybrid Mode
6020 22:13:01.601874 TX_TRACKING: ON
6021 22:13:01.611097 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6022 22:13:01.614549 [FAST_K] Save calibration result to emmc
6023 22:13:01.617745 dramc_set_vcore_voltage set vcore to 650000
6024 22:13:01.621337 Read voltage for 400, 6
6025 22:13:01.621900 Vio18 = 0
6026 22:13:01.624729 Vcore = 650000
6027 22:13:01.625295 Vdram = 0
6028 22:13:01.625664 Vddq = 0
6029 22:13:01.627320 Vmddr = 0
6030 22:13:01.630737 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6031 22:13:01.637301 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6032 22:13:01.637869 MEM_TYPE=3, freq_sel=20
6033 22:13:01.640904 sv_algorithm_assistance_LP4_800
6034 22:13:01.644054 ============ PULL DRAM RESETB DOWN ============
6035 22:13:01.651109 ========== PULL DRAM RESETB DOWN end =========
6036 22:13:01.654144 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6037 22:13:01.657718 ===================================
6038 22:13:01.660907 LPDDR4 DRAM CONFIGURATION
6039 22:13:01.663669 ===================================
6040 22:13:01.664272 EX_ROW_EN[0] = 0x0
6041 22:13:01.667641 EX_ROW_EN[1] = 0x0
6042 22:13:01.670773 LP4Y_EN = 0x0
6043 22:13:01.671394 WORK_FSP = 0x0
6044 22:13:01.673735 WL = 0x2
6045 22:13:01.674194 RL = 0x2
6046 22:13:01.677310 BL = 0x2
6047 22:13:01.677880 RPST = 0x0
6048 22:13:01.680586 RD_PRE = 0x0
6049 22:13:01.681143 WR_PRE = 0x1
6050 22:13:01.684613 WR_PST = 0x0
6051 22:13:01.685173 DBI_WR = 0x0
6052 22:13:01.687080 DBI_RD = 0x0
6053 22:13:01.687539 OTF = 0x1
6054 22:13:01.690262 ===================================
6055 22:13:01.694059 ===================================
6056 22:13:01.697231 ANA top config
6057 22:13:01.700358 ===================================
6058 22:13:01.700919 DLL_ASYNC_EN = 0
6059 22:13:01.703598 ALL_SLAVE_EN = 1
6060 22:13:01.706869 NEW_RANK_MODE = 1
6061 22:13:01.711252 DLL_IDLE_MODE = 1
6062 22:13:01.713504 LP45_APHY_COMB_EN = 1
6063 22:13:01.714066 TX_ODT_DIS = 1
6064 22:13:01.717434 NEW_8X_MODE = 1
6065 22:13:01.720381 ===================================
6066 22:13:01.724265 ===================================
6067 22:13:01.726679 data_rate = 800
6068 22:13:01.730031 CKR = 1
6069 22:13:01.733551 DQ_P2S_RATIO = 4
6070 22:13:01.736589 ===================================
6071 22:13:01.740420 CA_P2S_RATIO = 4
6072 22:13:01.740979 DQ_CA_OPEN = 0
6073 22:13:01.743585 DQ_SEMI_OPEN = 1
6074 22:13:01.746305 CA_SEMI_OPEN = 1
6075 22:13:01.749739 CA_FULL_RATE = 0
6076 22:13:01.753402 DQ_CKDIV4_EN = 0
6077 22:13:01.756387 CA_CKDIV4_EN = 1
6078 22:13:01.756954 CA_PREDIV_EN = 0
6079 22:13:01.759314 PH8_DLY = 0
6080 22:13:01.762597 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6081 22:13:01.766180 DQ_AAMCK_DIV = 0
6082 22:13:01.770032 CA_AAMCK_DIV = 0
6083 22:13:01.772952 CA_ADMCK_DIV = 4
6084 22:13:01.773511 DQ_TRACK_CA_EN = 0
6085 22:13:01.776223 CA_PICK = 800
6086 22:13:01.779782 CA_MCKIO = 400
6087 22:13:01.782507 MCKIO_SEMI = 400
6088 22:13:01.785936 PLL_FREQ = 3016
6089 22:13:01.789067 DQ_UI_PI_RATIO = 32
6090 22:13:01.792592 CA_UI_PI_RATIO = 32
6091 22:13:01.795746 ===================================
6092 22:13:01.799182 ===================================
6093 22:13:01.799737 memory_type:LPDDR4
6094 22:13:01.802127 GP_NUM : 10
6095 22:13:01.805822 SRAM_EN : 1
6096 22:13:01.806420 MD32_EN : 0
6097 22:13:01.809146 ===================================
6098 22:13:01.813335 [ANA_INIT] >>>>>>>>>>>>>>
6099 22:13:01.815728 <<<<<< [CONFIGURE PHASE]: ANA_TX
6100 22:13:01.818977 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6101 22:13:01.822968 ===================================
6102 22:13:01.825808 data_rate = 800,PCW = 0X7400
6103 22:13:01.828609 ===================================
6104 22:13:01.832089 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6105 22:13:01.835449 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6106 22:13:01.848658 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6107 22:13:01.851688 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6108 22:13:01.855118 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6109 22:13:01.858384 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6110 22:13:01.861684 [ANA_INIT] flow start
6111 22:13:01.864811 [ANA_INIT] PLL >>>>>>>>
6112 22:13:01.865281 [ANA_INIT] PLL <<<<<<<<
6113 22:13:01.868188 [ANA_INIT] MIDPI >>>>>>>>
6114 22:13:01.871490 [ANA_INIT] MIDPI <<<<<<<<
6115 22:13:01.874724 [ANA_INIT] DLL >>>>>>>>
6116 22:13:01.875309 [ANA_INIT] flow end
6117 22:13:01.878263 ============ LP4 DIFF to SE enter ============
6118 22:13:01.884846 ============ LP4 DIFF to SE exit ============
6119 22:13:01.885481 [ANA_INIT] <<<<<<<<<<<<<
6120 22:13:01.888140 [Flow] Enable top DCM control >>>>>
6121 22:13:01.891456 [Flow] Enable top DCM control <<<<<
6122 22:13:01.894980 Enable DLL master slave shuffle
6123 22:13:01.901407 ==============================================================
6124 22:13:01.901981 Gating Mode config
6125 22:13:01.908162 ==============================================================
6126 22:13:01.911983 Config description:
6127 22:13:01.921258 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6128 22:13:01.927748 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6129 22:13:01.931471 SELPH_MODE 0: By rank 1: By Phase
6130 22:13:01.938245 ==============================================================
6131 22:13:01.941904 GAT_TRACK_EN = 0
6132 22:13:01.944543 RX_GATING_MODE = 2
6133 22:13:01.945103 RX_GATING_TRACK_MODE = 2
6134 22:13:01.947741 SELPH_MODE = 1
6135 22:13:01.951009 PICG_EARLY_EN = 1
6136 22:13:01.954845 VALID_LAT_VALUE = 1
6137 22:13:01.960705 ==============================================================
6138 22:13:01.964234 Enter into Gating configuration >>>>
6139 22:13:01.967514 Exit from Gating configuration <<<<
6140 22:13:01.970619 Enter into DVFS_PRE_config >>>>>
6141 22:13:01.980861 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6142 22:13:01.983470 Exit from DVFS_PRE_config <<<<<
6143 22:13:01.987161 Enter into PICG configuration >>>>
6144 22:13:01.990453 Exit from PICG configuration <<<<
6145 22:13:01.993354 [RX_INPUT] configuration >>>>>
6146 22:13:01.996725 [RX_INPUT] configuration <<<<<
6147 22:13:02.000508 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6148 22:13:02.007109 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6149 22:13:02.013578 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6150 22:13:02.020194 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6151 22:13:02.026751 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6152 22:13:02.029847 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6153 22:13:02.036676 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6154 22:13:02.039945 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6155 22:13:02.043273 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6156 22:13:02.046678 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6157 22:13:02.053872 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6158 22:13:02.056731 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6159 22:13:02.059542 ===================================
6160 22:13:02.062863 LPDDR4 DRAM CONFIGURATION
6161 22:13:02.066661 ===================================
6162 22:13:02.067134 EX_ROW_EN[0] = 0x0
6163 22:13:02.069910 EX_ROW_EN[1] = 0x0
6164 22:13:02.070500 LP4Y_EN = 0x0
6165 22:13:02.072889 WORK_FSP = 0x0
6166 22:13:02.073468 WL = 0x2
6167 22:13:02.076019 RL = 0x2
6168 22:13:02.079476 BL = 0x2
6169 22:13:02.079997 RPST = 0x0
6170 22:13:02.083272 RD_PRE = 0x0
6171 22:13:02.083904 WR_PRE = 0x1
6172 22:13:02.086267 WR_PST = 0x0
6173 22:13:02.086865 DBI_WR = 0x0
6174 22:13:02.089326 DBI_RD = 0x0
6175 22:13:02.089793 OTF = 0x1
6176 22:13:02.093050 ===================================
6177 22:13:02.096070 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6178 22:13:02.102778 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6179 22:13:02.105760 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6180 22:13:02.109894 ===================================
6181 22:13:02.112553 LPDDR4 DRAM CONFIGURATION
6182 22:13:02.116523 ===================================
6183 22:13:02.117088 EX_ROW_EN[0] = 0x10
6184 22:13:02.119102 EX_ROW_EN[1] = 0x0
6185 22:13:02.119566 LP4Y_EN = 0x0
6186 22:13:02.122510 WORK_FSP = 0x0
6187 22:13:02.123094 WL = 0x2
6188 22:13:02.125397 RL = 0x2
6189 22:13:02.128883 BL = 0x2
6190 22:13:02.129349 RPST = 0x0
6191 22:13:02.132098 RD_PRE = 0x0
6192 22:13:02.132563 WR_PRE = 0x1
6193 22:13:02.135838 WR_PST = 0x0
6194 22:13:02.136305 DBI_WR = 0x0
6195 22:13:02.138840 DBI_RD = 0x0
6196 22:13:02.139306 OTF = 0x1
6197 22:13:02.141907 ===================================
6198 22:13:02.149234 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6199 22:13:02.152884 nWR fixed to 30
6200 22:13:02.156581 [ModeRegInit_LP4] CH0 RK0
6201 22:13:02.157153 [ModeRegInit_LP4] CH0 RK1
6202 22:13:02.159198 [ModeRegInit_LP4] CH1 RK0
6203 22:13:02.163023 [ModeRegInit_LP4] CH1 RK1
6204 22:13:02.163590 match AC timing 19
6205 22:13:02.170023 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6206 22:13:02.172762 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6207 22:13:02.176148 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6208 22:13:02.182430 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6209 22:13:02.185826 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6210 22:13:02.186426 ==
6211 22:13:02.188845 Dram Type= 6, Freq= 0, CH_0, rank 0
6212 22:13:02.192569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6213 22:13:02.193134 ==
6214 22:13:02.198967 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6215 22:13:02.205860 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6216 22:13:02.208905 [CA 0] Center 36 (8~64) winsize 57
6217 22:13:02.212442 [CA 1] Center 36 (8~64) winsize 57
6218 22:13:02.215747 [CA 2] Center 36 (8~64) winsize 57
6219 22:13:02.219533 [CA 3] Center 36 (8~64) winsize 57
6220 22:13:02.222109 [CA 4] Center 36 (8~64) winsize 57
6221 22:13:02.225507 [CA 5] Center 36 (8~64) winsize 57
6222 22:13:02.226065
6223 22:13:02.229121 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6224 22:13:02.229685
6225 22:13:02.232173 [CATrainingPosCal] consider 1 rank data
6226 22:13:02.235866 u2DelayCellTimex100 = 270/100 ps
6227 22:13:02.238410 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6228 22:13:02.241858 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6229 22:13:02.245175 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6230 22:13:02.248887 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6231 22:13:02.251843 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6232 22:13:02.255655 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6233 22:13:02.256220
6234 22:13:02.258305 CA PerBit enable=1, Macro0, CA PI delay=36
6235 22:13:02.261771
6236 22:13:02.262326 [CBTSetCACLKResult] CA Dly = 36
6237 22:13:02.265047 CS Dly: 1 (0~32)
6238 22:13:02.265557 ==
6239 22:13:02.268731 Dram Type= 6, Freq= 0, CH_0, rank 1
6240 22:13:02.271725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6241 22:13:02.272293 ==
6242 22:13:02.278513 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6243 22:13:02.284912 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6244 22:13:02.287838 [CA 0] Center 36 (8~64) winsize 57
6245 22:13:02.291341 [CA 1] Center 36 (8~64) winsize 57
6246 22:13:02.294468 [CA 2] Center 36 (8~64) winsize 57
6247 22:13:02.297821 [CA 3] Center 36 (8~64) winsize 57
6248 22:13:02.298288 [CA 4] Center 36 (8~64) winsize 57
6249 22:13:02.301125 [CA 5] Center 36 (8~64) winsize 57
6250 22:13:02.301686
6251 22:13:02.307646 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6252 22:13:02.308208
6253 22:13:02.311570 [CATrainingPosCal] consider 2 rank data
6254 22:13:02.314659 u2DelayCellTimex100 = 270/100 ps
6255 22:13:02.317542 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6256 22:13:02.320906 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6257 22:13:02.324437 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6258 22:13:02.327495 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6259 22:13:02.330898 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6260 22:13:02.334208 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6261 22:13:02.334808
6262 22:13:02.337191 CA PerBit enable=1, Macro0, CA PI delay=36
6263 22:13:02.337659
6264 22:13:02.340820 [CBTSetCACLKResult] CA Dly = 36
6265 22:13:02.344113 CS Dly: 1 (0~32)
6266 22:13:02.344670
6267 22:13:02.347136 ----->DramcWriteLeveling(PI) begin...
6268 22:13:02.347615 ==
6269 22:13:02.350821 Dram Type= 6, Freq= 0, CH_0, rank 0
6270 22:13:02.354240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6271 22:13:02.354837 ==
6272 22:13:02.357259 Write leveling (Byte 0): 40 => 8
6273 22:13:02.361061 Write leveling (Byte 1): 32 => 0
6274 22:13:02.363737 DramcWriteLeveling(PI) end<-----
6275 22:13:02.364205
6276 22:13:02.364578 ==
6277 22:13:02.367054 Dram Type= 6, Freq= 0, CH_0, rank 0
6278 22:13:02.370992 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6279 22:13:02.371560 ==
6280 22:13:02.374246 [Gating] SW mode calibration
6281 22:13:02.380456 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6282 22:13:02.387122 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6283 22:13:02.390422 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6284 22:13:02.396576 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6285 22:13:02.400792 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6286 22:13:02.403633 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6287 22:13:02.410156 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6288 22:13:02.413051 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6289 22:13:02.416463 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6290 22:13:02.423214 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6291 22:13:02.426725 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6292 22:13:02.429658 Total UI for P1: 0, mck2ui 16
6293 22:13:02.433174 best dqsien dly found for B0: ( 0, 14, 24)
6294 22:13:02.436881 Total UI for P1: 0, mck2ui 16
6295 22:13:02.439348 best dqsien dly found for B1: ( 0, 14, 24)
6296 22:13:02.442849 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6297 22:13:02.446103 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6298 22:13:02.446609
6299 22:13:02.449443 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6300 22:13:02.452533 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6301 22:13:02.456466 [Gating] SW calibration Done
6302 22:13:02.456975 ==
6303 22:13:02.459333 Dram Type= 6, Freq= 0, CH_0, rank 0
6304 22:13:02.465614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6305 22:13:02.466112 ==
6306 22:13:02.466484 RX Vref Scan: 0
6307 22:13:02.466802
6308 22:13:02.469214 RX Vref 0 -> 0, step: 1
6309 22:13:02.469719
6310 22:13:02.472538 RX Delay -410 -> 252, step: 16
6311 22:13:02.476398 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6312 22:13:02.479352 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6313 22:13:02.485404 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6314 22:13:02.488962 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6315 22:13:02.492823 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6316 22:13:02.495978 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6317 22:13:02.501988 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6318 22:13:02.505666 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6319 22:13:02.508765 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6320 22:13:02.511827 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6321 22:13:02.518918 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6322 22:13:02.522258 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6323 22:13:02.525195 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6324 22:13:02.528628 iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480
6325 22:13:02.535045 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6326 22:13:02.538515 iDelay=230, Bit 15, Center -27 (-266 ~ 213) 480
6327 22:13:02.538932 ==
6328 22:13:02.542000 Dram Type= 6, Freq= 0, CH_0, rank 0
6329 22:13:02.545132 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6330 22:13:02.545645 ==
6331 22:13:02.548508 DQS Delay:
6332 22:13:02.549012 DQS0 = 27, DQS1 = 43
6333 22:13:02.551937 DQM Delay:
6334 22:13:02.552446 DQM0 = 12, DQM1 = 13
6335 22:13:02.552776 DQ Delay:
6336 22:13:02.555422 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6337 22:13:02.558672 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =24
6338 22:13:02.561654 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6339 22:13:02.564865 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6340 22:13:02.565401
6341 22:13:02.565736
6342 22:13:02.566041 ==
6343 22:13:02.568663 Dram Type= 6, Freq= 0, CH_0, rank 0
6344 22:13:02.575146 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6345 22:13:02.575659 ==
6346 22:13:02.575989
6347 22:13:02.576291
6348 22:13:02.576582 TX Vref Scan disable
6349 22:13:02.577951 == TX Byte 0 ==
6350 22:13:02.581752 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6351 22:13:02.584821 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6352 22:13:02.588023 == TX Byte 1 ==
6353 22:13:02.591301 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6354 22:13:02.595231 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6355 22:13:02.597554 ==
6356 22:13:02.600997 Dram Type= 6, Freq= 0, CH_0, rank 0
6357 22:13:02.604479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6358 22:13:02.605026 ==
6359 22:13:02.605382
6360 22:13:02.605695
6361 22:13:02.607626 TX Vref Scan disable
6362 22:13:02.608063 == TX Byte 0 ==
6363 22:13:02.610947 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6364 22:13:02.617290 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6365 22:13:02.617781 == TX Byte 1 ==
6366 22:13:02.621121 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6367 22:13:02.627409 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6368 22:13:02.627931
6369 22:13:02.628272 [DATLAT]
6370 22:13:02.628591 Freq=400, CH0 RK0
6371 22:13:02.630445
6372 22:13:02.630863 DATLAT Default: 0xf
6373 22:13:02.634253 0, 0xFFFF, sum = 0
6374 22:13:02.634840 1, 0xFFFF, sum = 0
6375 22:13:02.637118 2, 0xFFFF, sum = 0
6376 22:13:02.637574 3, 0xFFFF, sum = 0
6377 22:13:02.640681 4, 0xFFFF, sum = 0
6378 22:13:02.641164 5, 0xFFFF, sum = 0
6379 22:13:02.643782 6, 0xFFFF, sum = 0
6380 22:13:02.644306 7, 0xFFFF, sum = 0
6381 22:13:02.647283 8, 0xFFFF, sum = 0
6382 22:13:02.647809 9, 0xFFFF, sum = 0
6383 22:13:02.650503 10, 0xFFFF, sum = 0
6384 22:13:02.651024 11, 0xFFFF, sum = 0
6385 22:13:02.654031 12, 0xFFFF, sum = 0
6386 22:13:02.654594 13, 0x0, sum = 1
6387 22:13:02.657209 14, 0x0, sum = 2
6388 22:13:02.657732 15, 0x0, sum = 3
6389 22:13:02.660323 16, 0x0, sum = 4
6390 22:13:02.660850 best_step = 14
6391 22:13:02.661187
6392 22:13:02.661593 ==
6393 22:13:02.664035 Dram Type= 6, Freq= 0, CH_0, rank 0
6394 22:13:02.670462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6395 22:13:02.670984 ==
6396 22:13:02.671327 RX Vref Scan: 1
6397 22:13:02.671645
6398 22:13:02.674031 RX Vref 0 -> 0, step: 1
6399 22:13:02.674598
6400 22:13:02.677199 RX Delay -327 -> 252, step: 8
6401 22:13:02.677711
6402 22:13:02.679980 Set Vref, RX VrefLevel [Byte0]: 60
6403 22:13:02.683218 [Byte1]: 51
6404 22:13:02.687191
6405 22:13:02.687709 Final RX Vref Byte 0 = 60 to rank0
6406 22:13:02.689999 Final RX Vref Byte 1 = 51 to rank0
6407 22:13:02.693040 Final RX Vref Byte 0 = 60 to rank1
6408 22:13:02.696608 Final RX Vref Byte 1 = 51 to rank1==
6409 22:13:02.699689 Dram Type= 6, Freq= 0, CH_0, rank 0
6410 22:13:02.706405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6411 22:13:02.706927 ==
6412 22:13:02.707270 DQS Delay:
6413 22:13:02.709830 DQS0 = 28, DQS1 = 44
6414 22:13:02.710400 DQM Delay:
6415 22:13:02.710756 DQM0 = 12, DQM1 = 12
6416 22:13:02.712735 DQ Delay:
6417 22:13:02.716006 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6418 22:13:02.720237 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =20
6419 22:13:02.720757 DQ8 =8, DQ9 =0, DQ10 =8, DQ11 =4
6420 22:13:02.723085 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6421 22:13:02.726611
6422 22:13:02.727129
6423 22:13:02.732954 [DQSOSCAuto] RK0, (LSB)MR18= 0xb4ad, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 387 ps
6424 22:13:02.736121 CH0 RK0: MR19=C0C, MR18=B4AD
6425 22:13:02.742618 CH0_RK0: MR19=0xC0C, MR18=0xB4AD, DQSOSC=387, MR23=63, INC=394, DEC=262
6426 22:13:02.743144 ==
6427 22:13:02.745692 Dram Type= 6, Freq= 0, CH_0, rank 1
6428 22:13:02.748877 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6429 22:13:02.749403 ==
6430 22:13:02.752655 [Gating] SW mode calibration
6431 22:13:02.759276 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6432 22:13:02.765507 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6433 22:13:02.769567 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6434 22:13:02.772726 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6435 22:13:02.779333 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6436 22:13:02.782514 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6437 22:13:02.785856 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6438 22:13:02.792444 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6439 22:13:02.795999 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6440 22:13:02.799203 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6441 22:13:02.805723 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6442 22:13:02.806283 Total UI for P1: 0, mck2ui 16
6443 22:13:02.812024 best dqsien dly found for B0: ( 0, 14, 24)
6444 22:13:02.812588 Total UI for P1: 0, mck2ui 16
6445 22:13:02.818593 best dqsien dly found for B1: ( 0, 14, 24)
6446 22:13:02.821691 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6447 22:13:02.826004 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6448 22:13:02.826600
6449 22:13:02.828423 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6450 22:13:02.832191 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6451 22:13:02.835035 [Gating] SW calibration Done
6452 22:13:02.835513 ==
6453 22:13:02.838693 Dram Type= 6, Freq= 0, CH_0, rank 1
6454 22:13:02.841278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6455 22:13:02.841747 ==
6456 22:13:02.845207 RX Vref Scan: 0
6457 22:13:02.845912
6458 22:13:02.846297 RX Vref 0 -> 0, step: 1
6459 22:13:02.848356
6460 22:13:02.848861 RX Delay -410 -> 252, step: 16
6461 22:13:02.855043 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6462 22:13:02.858439 iDelay=230, Bit 1, Center -11 (-234 ~ 213) 448
6463 22:13:02.861663 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6464 22:13:02.865594 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6465 22:13:02.871313 iDelay=230, Bit 4, Center -11 (-234 ~ 213) 448
6466 22:13:02.875126 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6467 22:13:02.878338 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6468 22:13:02.881509 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6469 22:13:02.888032 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6470 22:13:02.891239 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6471 22:13:02.897180 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6472 22:13:02.897292 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6473 22:13:02.904390 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6474 22:13:02.908171 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6475 22:13:02.911049 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6476 22:13:02.917931 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6477 22:13:02.918539 ==
6478 22:13:02.920801 Dram Type= 6, Freq= 0, CH_0, rank 1
6479 22:13:02.924559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6480 22:13:02.925122 ==
6481 22:13:02.925497 DQS Delay:
6482 22:13:02.927628 DQS0 = 27, DQS1 = 43
6483 22:13:02.928208 DQM Delay:
6484 22:13:02.930725 DQM0 = 13, DQM1 = 15
6485 22:13:02.931212 DQ Delay:
6486 22:13:02.933777 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6487 22:13:02.937651 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6488 22:13:02.940586 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6489 22:13:02.944455 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =24
6490 22:13:02.945019
6491 22:13:02.945395
6492 22:13:02.945741 ==
6493 22:13:02.946949 Dram Type= 6, Freq= 0, CH_0, rank 1
6494 22:13:02.950248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6495 22:13:02.950767 ==
6496 22:13:02.951146
6497 22:13:02.953327
6498 22:13:02.953797 TX Vref Scan disable
6499 22:13:02.956976 == TX Byte 0 ==
6500 22:13:02.960197 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6501 22:13:02.963769 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6502 22:13:02.966729 == TX Byte 1 ==
6503 22:13:02.970608 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6504 22:13:02.973346 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6505 22:13:02.973911 ==
6506 22:13:02.976816 Dram Type= 6, Freq= 0, CH_0, rank 1
6507 22:13:02.980518 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6508 22:13:02.983623 ==
6509 22:13:02.984184
6510 22:13:02.984562
6511 22:13:02.984907 TX Vref Scan disable
6512 22:13:02.986459 == TX Byte 0 ==
6513 22:13:02.989581 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6514 22:13:02.993267 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6515 22:13:02.996388 == TX Byte 1 ==
6516 22:13:02.999804 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6517 22:13:03.003045 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6518 22:13:03.003612
6519 22:13:03.006310 [DATLAT]
6520 22:13:03.006812 Freq=400, CH0 RK1
6521 22:13:03.007188
6522 22:13:03.009423 DATLAT Default: 0xe
6523 22:13:03.009911 0, 0xFFFF, sum = 0
6524 22:13:03.013253 1, 0xFFFF, sum = 0
6525 22:13:03.013891 2, 0xFFFF, sum = 0
6526 22:13:03.016160 3, 0xFFFF, sum = 0
6527 22:13:03.016734 4, 0xFFFF, sum = 0
6528 22:13:03.019759 5, 0xFFFF, sum = 0
6529 22:13:03.020331 6, 0xFFFF, sum = 0
6530 22:13:03.022832 7, 0xFFFF, sum = 0
6531 22:13:03.023308 8, 0xFFFF, sum = 0
6532 22:13:03.026905 9, 0xFFFF, sum = 0
6533 22:13:03.027477 10, 0xFFFF, sum = 0
6534 22:13:03.029342 11, 0xFFFF, sum = 0
6535 22:13:03.029862 12, 0xFFFF, sum = 0
6536 22:13:03.032440 13, 0x0, sum = 1
6537 22:13:03.032961 14, 0x0, sum = 2
6538 22:13:03.035710 15, 0x0, sum = 3
6539 22:13:03.036189 16, 0x0, sum = 4
6540 22:13:03.039493 best_step = 14
6541 22:13:03.039957
6542 22:13:03.040326 ==
6543 22:13:03.042701 Dram Type= 6, Freq= 0, CH_0, rank 1
6544 22:13:03.045781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6545 22:13:03.046255 ==
6546 22:13:03.049160 RX Vref Scan: 0
6547 22:13:03.049724
6548 22:13:03.050099 RX Vref 0 -> 0, step: 1
6549 22:13:03.050513
6550 22:13:03.052045 RX Delay -327 -> 252, step: 8
6551 22:13:03.060622 iDelay=217, Bit 0, Center -20 (-247 ~ 208) 456
6552 22:13:03.063874 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6553 22:13:03.067043 iDelay=217, Bit 2, Center -24 (-247 ~ 200) 448
6554 22:13:03.070995 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6555 22:13:03.077296 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6556 22:13:03.080591 iDelay=217, Bit 5, Center -28 (-255 ~ 200) 456
6557 22:13:03.084018 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6558 22:13:03.087169 iDelay=217, Bit 7, Center -12 (-239 ~ 216) 456
6559 22:13:03.093843 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6560 22:13:03.097014 iDelay=217, Bit 9, Center -40 (-263 ~ 184) 448
6561 22:13:03.100588 iDelay=217, Bit 10, Center -28 (-255 ~ 200) 456
6562 22:13:03.107185 iDelay=217, Bit 11, Center -32 (-255 ~ 192) 448
6563 22:13:03.110265 iDelay=217, Bit 12, Center -24 (-247 ~ 200) 448
6564 22:13:03.113652 iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440
6565 22:13:03.116731 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6566 22:13:03.123656 iDelay=217, Bit 15, Center -20 (-247 ~ 208) 456
6567 22:13:03.124218 ==
6568 22:13:03.126816 Dram Type= 6, Freq= 0, CH_0, rank 1
6569 22:13:03.130042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6570 22:13:03.130552 ==
6571 22:13:03.130933 DQS Delay:
6572 22:13:03.133535 DQS0 = 28, DQS1 = 40
6573 22:13:03.134001 DQM Delay:
6574 22:13:03.136939 DQM0 = 9, DQM1 = 12
6575 22:13:03.137408 DQ Delay:
6576 22:13:03.139738 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =4
6577 22:13:03.143156 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6578 22:13:03.146448 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =8
6579 22:13:03.150410 DQ12 =16, DQ13 =20, DQ14 =20, DQ15 =20
6580 22:13:03.150839
6581 22:13:03.151195
6582 22:13:03.156328 [DQSOSCAuto] RK1, (LSB)MR18= 0xc275, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 385 ps
6583 22:13:03.159734 CH0 RK1: MR19=C0C, MR18=C275
6584 22:13:03.166592 CH0_RK1: MR19=0xC0C, MR18=0xC275, DQSOSC=385, MR23=63, INC=398, DEC=265
6585 22:13:03.169881 [RxdqsGatingPostProcess] freq 400
6586 22:13:03.176637 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6587 22:13:03.179689 best DQS0 dly(2T, 0.5T) = (0, 10)
6588 22:13:03.180168 best DQS1 dly(2T, 0.5T) = (0, 10)
6589 22:13:03.182751 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6590 22:13:03.186782 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6591 22:13:03.189884 best DQS0 dly(2T, 0.5T) = (0, 10)
6592 22:13:03.193087 best DQS1 dly(2T, 0.5T) = (0, 10)
6593 22:13:03.196882 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6594 22:13:03.199816 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6595 22:13:03.203298 Pre-setting of DQS Precalculation
6596 22:13:03.209382 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6597 22:13:03.209885 ==
6598 22:13:03.212542 Dram Type= 6, Freq= 0, CH_1, rank 0
6599 22:13:03.215724 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6600 22:13:03.216191 ==
6601 22:13:03.222919 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6602 22:13:03.225674 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
6603 22:13:03.229188 [CA 0] Center 36 (8~64) winsize 57
6604 22:13:03.232992 [CA 1] Center 36 (8~64) winsize 57
6605 22:13:03.235946 [CA 2] Center 36 (8~64) winsize 57
6606 22:13:03.239038 [CA 3] Center 36 (8~64) winsize 57
6607 22:13:03.242666 [CA 4] Center 36 (8~64) winsize 57
6608 22:13:03.245851 [CA 5] Center 36 (8~64) winsize 57
6609 22:13:03.246460
6610 22:13:03.249331 [CmdBusTrainingLP45] Vref(ca) range 1: 31
6611 22:13:03.249899
6612 22:13:03.252858 [CATrainingPosCal] consider 1 rank data
6613 22:13:03.255966 u2DelayCellTimex100 = 270/100 ps
6614 22:13:03.259116 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6615 22:13:03.265707 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6616 22:13:03.269195 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6617 22:13:03.272485 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6618 22:13:03.275444 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6619 22:13:03.278758 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6620 22:13:03.279315
6621 22:13:03.282035 CA PerBit enable=1, Macro0, CA PI delay=36
6622 22:13:03.282551
6623 22:13:03.285530 [CBTSetCACLKResult] CA Dly = 36
6624 22:13:03.286000 CS Dly: 1 (0~32)
6625 22:13:03.288917 ==
6626 22:13:03.291923 Dram Type= 6, Freq= 0, CH_1, rank 1
6627 22:13:03.295835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6628 22:13:03.296399 ==
6629 22:13:03.299590 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6630 22:13:03.305521 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
6631 22:13:03.308812 [CA 0] Center 36 (8~64) winsize 57
6632 22:13:03.312119 [CA 1] Center 36 (8~64) winsize 57
6633 22:13:03.315616 [CA 2] Center 36 (8~64) winsize 57
6634 22:13:03.319052 [CA 3] Center 36 (8~64) winsize 57
6635 22:13:03.322102 [CA 4] Center 36 (8~64) winsize 57
6636 22:13:03.325217 [CA 5] Center 36 (8~64) winsize 57
6637 22:13:03.325786
6638 22:13:03.328768 [CmdBusTrainingLP45] Vref(ca) range 1: 31
6639 22:13:03.329336
6640 22:13:03.332452 [CATrainingPosCal] consider 2 rank data
6641 22:13:03.335686 u2DelayCellTimex100 = 270/100 ps
6642 22:13:03.338993 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6643 22:13:03.341710 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6644 22:13:03.344953 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6645 22:13:03.352160 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6646 22:13:03.354827 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6647 22:13:03.358237 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6648 22:13:03.358851
6649 22:13:03.361676 CA PerBit enable=1, Macro0, CA PI delay=36
6650 22:13:03.362242
6651 22:13:03.364673 [CBTSetCACLKResult] CA Dly = 36
6652 22:13:03.365145 CS Dly: 1 (0~32)
6653 22:13:03.365521
6654 22:13:03.367856 ----->DramcWriteLeveling(PI) begin...
6655 22:13:03.368335 ==
6656 22:13:03.371146 Dram Type= 6, Freq= 0, CH_1, rank 0
6657 22:13:03.378294 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6658 22:13:03.378804 ==
6659 22:13:03.382081 Write leveling (Byte 0): 40 => 8
6660 22:13:03.384827 Write leveling (Byte 1): 32 => 0
6661 22:13:03.385402 DramcWriteLeveling(PI) end<-----
6662 22:13:03.387879
6663 22:13:03.388441 ==
6664 22:13:03.391449 Dram Type= 6, Freq= 0, CH_1, rank 0
6665 22:13:03.394377 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6666 22:13:03.394952 ==
6667 22:13:03.398051 [Gating] SW mode calibration
6668 22:13:03.404379 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6669 22:13:03.408104 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6670 22:13:03.414872 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6671 22:13:03.417665 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6672 22:13:03.420849 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6673 22:13:03.428052 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6674 22:13:03.431149 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6675 22:13:03.434170 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6676 22:13:03.440771 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6677 22:13:03.443724 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6678 22:13:03.450821 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6679 22:13:03.451393 Total UI for P1: 0, mck2ui 16
6680 22:13:03.453656 best dqsien dly found for B0: ( 0, 14, 24)
6681 22:13:03.456935 Total UI for P1: 0, mck2ui 16
6682 22:13:03.460666 best dqsien dly found for B1: ( 0, 14, 24)
6683 22:13:03.466754 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6684 22:13:03.469972 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6685 22:13:03.470485
6686 22:13:03.473395 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6687 22:13:03.477009 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6688 22:13:03.480696 [Gating] SW calibration Done
6689 22:13:03.481259 ==
6690 22:13:03.483918 Dram Type= 6, Freq= 0, CH_1, rank 0
6691 22:13:03.486903 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6692 22:13:03.487380 ==
6693 22:13:03.490606 RX Vref Scan: 0
6694 22:13:03.491165
6695 22:13:03.491543 RX Vref 0 -> 0, step: 1
6696 22:13:03.491893
6697 22:13:03.494054 RX Delay -410 -> 252, step: 16
6698 22:13:03.496809 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6699 22:13:03.503859 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6700 22:13:03.507111 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6701 22:13:03.510061 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6702 22:13:03.516589 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6703 22:13:03.519718 iDelay=230, Bit 5, Center -11 (-234 ~ 213) 448
6704 22:13:03.523257 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6705 22:13:03.526509 iDelay=230, Bit 7, Center -27 (-266 ~ 213) 480
6706 22:13:03.533314 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6707 22:13:03.536255 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6708 22:13:03.540232 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6709 22:13:03.543189 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6710 22:13:03.550163 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6711 22:13:03.553011 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6712 22:13:03.556380 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6713 22:13:03.559908 iDelay=230, Bit 15, Center -19 (-266 ~ 229) 496
6714 22:13:03.563578 ==
6715 22:13:03.564163 Dram Type= 6, Freq= 0, CH_1, rank 0
6716 22:13:03.569706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6717 22:13:03.570280 ==
6718 22:13:03.570714 DQS Delay:
6719 22:13:03.572983 DQS0 = 27, DQS1 = 35
6720 22:13:03.573455 DQM Delay:
6721 22:13:03.576554 DQM0 = 7, DQM1 = 10
6722 22:13:03.577116 DQ Delay:
6723 22:13:03.579589 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =8
6724 22:13:03.583096 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =0
6725 22:13:03.583668 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6726 22:13:03.586463 DQ12 =24, DQ13 =16, DQ14 =8, DQ15 =16
6727 22:13:03.587023
6728 22:13:03.589484
6729 22:13:03.589950 ==
6730 22:13:03.592682 Dram Type= 6, Freq= 0, CH_1, rank 0
6731 22:13:03.596638 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6732 22:13:03.597111 ==
6733 22:13:03.597490
6734 22:13:03.597839
6735 22:13:03.599455 TX Vref Scan disable
6736 22:13:03.599927 == TX Byte 0 ==
6737 22:13:03.602858 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6738 22:13:03.609726 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6739 22:13:03.610294 == TX Byte 1 ==
6740 22:13:03.612711 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6741 22:13:03.619565 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6742 22:13:03.620126 ==
6743 22:13:03.623223 Dram Type= 6, Freq= 0, CH_1, rank 0
6744 22:13:03.626195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6745 22:13:03.626788 ==
6746 22:13:03.627166
6747 22:13:03.627510
6748 22:13:03.628782 TX Vref Scan disable
6749 22:13:03.629248 == TX Byte 0 ==
6750 22:13:03.635604 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6751 22:13:03.638910 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6752 22:13:03.639472 == TX Byte 1 ==
6753 22:13:03.645484 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6754 22:13:03.648742 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6755 22:13:03.649309
6756 22:13:03.649685 [DATLAT]
6757 22:13:03.652143 Freq=400, CH1 RK0
6758 22:13:03.652711
6759 22:13:03.653089 DATLAT Default: 0xf
6760 22:13:03.655689 0, 0xFFFF, sum = 0
6761 22:13:03.656265 1, 0xFFFF, sum = 0
6762 22:13:03.659075 2, 0xFFFF, sum = 0
6763 22:13:03.659645 3, 0xFFFF, sum = 0
6764 22:13:03.661881 4, 0xFFFF, sum = 0
6765 22:13:03.662487 5, 0xFFFF, sum = 0
6766 22:13:03.665730 6, 0xFFFF, sum = 0
6767 22:13:03.668558 7, 0xFFFF, sum = 0
6768 22:13:03.669041 8, 0xFFFF, sum = 0
6769 22:13:03.671767 9, 0xFFFF, sum = 0
6770 22:13:03.672256 10, 0xFFFF, sum = 0
6771 22:13:03.675248 11, 0xFFFF, sum = 0
6772 22:13:03.675822 12, 0xFFFF, sum = 0
6773 22:13:03.678460 13, 0x0, sum = 1
6774 22:13:03.678937 14, 0x0, sum = 2
6775 22:13:03.681786 15, 0x0, sum = 3
6776 22:13:03.682265 16, 0x0, sum = 4
6777 22:13:03.682711 best_step = 14
6778 22:13:03.683066
6779 22:13:03.685035 ==
6780 22:13:03.688777 Dram Type= 6, Freq= 0, CH_1, rank 0
6781 22:13:03.691945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6782 22:13:03.692419 ==
6783 22:13:03.692797 RX Vref Scan: 1
6784 22:13:03.693152
6785 22:13:03.695364 RX Vref 0 -> 0, step: 1
6786 22:13:03.695834
6787 22:13:03.699234 RX Delay -311 -> 252, step: 8
6788 22:13:03.699710
6789 22:13:03.701820 Set Vref, RX VrefLevel [Byte0]: 51
6790 22:13:03.704837 [Byte1]: 58
6791 22:13:03.708793
6792 22:13:03.709357 Final RX Vref Byte 0 = 51 to rank0
6793 22:13:03.712290 Final RX Vref Byte 1 = 58 to rank0
6794 22:13:03.715440 Final RX Vref Byte 0 = 51 to rank1
6795 22:13:03.718773 Final RX Vref Byte 1 = 58 to rank1==
6796 22:13:03.722727 Dram Type= 6, Freq= 0, CH_1, rank 0
6797 22:13:03.728757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6798 22:13:03.729337 ==
6799 22:13:03.729721 DQS Delay:
6800 22:13:03.731633 DQS0 = 32, DQS1 = 44
6801 22:13:03.732104 DQM Delay:
6802 22:13:03.732482 DQM0 = 12, DQM1 = 16
6803 22:13:03.735673 DQ Delay:
6804 22:13:03.739002 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6805 22:13:03.742023 DQ4 =12, DQ5 =24, DQ6 =20, DQ7 =8
6806 22:13:03.742624 DQ8 =4, DQ9 =0, DQ10 =20, DQ11 =8
6807 22:13:03.745163 DQ12 =28, DQ13 =24, DQ14 =20, DQ15 =24
6808 22:13:03.748401
6809 22:13:03.748962
6810 22:13:03.755196 [DQSOSCAuto] RK0, (LSB)MR18= 0x95cf, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 391 ps
6811 22:13:03.758252 CH1 RK0: MR19=C0C, MR18=95CF
6812 22:13:03.764846 CH1_RK0: MR19=0xC0C, MR18=0x95CF, DQSOSC=384, MR23=63, INC=400, DEC=267
6813 22:13:03.765413 ==
6814 22:13:03.768093 Dram Type= 6, Freq= 0, CH_1, rank 1
6815 22:13:03.771624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6816 22:13:03.772193 ==
6817 22:13:03.775261 [Gating] SW mode calibration
6818 22:13:03.781300 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6819 22:13:03.787920 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6820 22:13:03.791688 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6821 22:13:03.794738 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6822 22:13:03.800946 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6823 22:13:03.804613 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6824 22:13:03.807687 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6825 22:13:03.814118 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6826 22:13:03.817530 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6827 22:13:03.821442 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6828 22:13:03.827254 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6829 22:13:03.831270 Total UI for P1: 0, mck2ui 16
6830 22:13:03.833748 best dqsien dly found for B0: ( 0, 14, 24)
6831 22:13:03.837649 Total UI for P1: 0, mck2ui 16
6832 22:13:03.840915 best dqsien dly found for B1: ( 0, 14, 24)
6833 22:13:03.843631 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6834 22:13:03.847915 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6835 22:13:03.848483
6836 22:13:03.850603 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6837 22:13:03.854029 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6838 22:13:03.857280 [Gating] SW calibration Done
6839 22:13:03.857842 ==
6840 22:13:03.860439 Dram Type= 6, Freq= 0, CH_1, rank 1
6841 22:13:03.863964 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6842 22:13:03.864533 ==
6843 22:13:03.866770 RX Vref Scan: 0
6844 22:13:03.867243
6845 22:13:03.870544 RX Vref 0 -> 0, step: 1
6846 22:13:03.871106
6847 22:13:03.871486 RX Delay -410 -> 252, step: 16
6848 22:13:03.877145 iDelay=230, Bit 0, Center -11 (-234 ~ 213) 448
6849 22:13:03.880347 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6850 22:13:03.883614 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6851 22:13:03.886988 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6852 22:13:03.893457 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6853 22:13:03.897255 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6854 22:13:03.900306 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6855 22:13:03.903950 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6856 22:13:03.909936 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6857 22:13:03.913304 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6858 22:13:03.916307 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6859 22:13:03.923284 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6860 22:13:03.926791 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6861 22:13:03.930670 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6862 22:13:03.933970 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6863 22:13:03.939587 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6864 22:13:03.940152 ==
6865 22:13:03.942763 Dram Type= 6, Freq= 0, CH_1, rank 1
6866 22:13:03.946136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6867 22:13:03.946655 ==
6868 22:13:03.947038 DQS Delay:
6869 22:13:03.949628 DQS0 = 35, DQS1 = 43
6870 22:13:03.950204 DQM Delay:
6871 22:13:03.952666 DQM0 = 18, DQM1 = 18
6872 22:13:03.953228 DQ Delay:
6873 22:13:03.956212 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6874 22:13:03.959777 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6875 22:13:03.962905 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6876 22:13:03.966417 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =32
6877 22:13:03.966981
6878 22:13:03.967361
6879 22:13:03.967714 ==
6880 22:13:03.968578 Dram Type= 6, Freq= 0, CH_1, rank 1
6881 22:13:03.975625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6882 22:13:03.976189 ==
6883 22:13:03.976562
6884 22:13:03.976905
6885 22:13:03.977233 TX Vref Scan disable
6886 22:13:03.979062 == TX Byte 0 ==
6887 22:13:03.982265 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6888 22:13:03.985933 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6889 22:13:03.988904 == TX Byte 1 ==
6890 22:13:03.992415 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6891 22:13:03.995509 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6892 22:13:03.996072 ==
6893 22:13:03.998449 Dram Type= 6, Freq= 0, CH_1, rank 1
6894 22:13:04.005149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6895 22:13:04.005731 ==
6896 22:13:04.006115
6897 22:13:04.006483
6898 22:13:04.008743 TX Vref Scan disable
6899 22:13:04.009212 == TX Byte 0 ==
6900 22:13:04.011567 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6901 22:13:04.015050 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6902 22:13:04.018454 == TX Byte 1 ==
6903 22:13:04.021909 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6904 22:13:04.024560 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6905 22:13:04.025027
6906 22:13:04.028065 [DATLAT]
6907 22:13:04.028630 Freq=400, CH1 RK1
6908 22:13:04.029009
6909 22:13:04.031356 DATLAT Default: 0xe
6910 22:13:04.031842 0, 0xFFFF, sum = 0
6911 22:13:04.034783 1, 0xFFFF, sum = 0
6912 22:13:04.035252 2, 0xFFFF, sum = 0
6913 22:13:04.038242 3, 0xFFFF, sum = 0
6914 22:13:04.038853 4, 0xFFFF, sum = 0
6915 22:13:04.041581 5, 0xFFFF, sum = 0
6916 22:13:04.044892 6, 0xFFFF, sum = 0
6917 22:13:04.045681 7, 0xFFFF, sum = 0
6918 22:13:04.048449 8, 0xFFFF, sum = 0
6919 22:13:04.049010 9, 0xFFFF, sum = 0
6920 22:13:04.051675 10, 0xFFFF, sum = 0
6921 22:13:04.052238 11, 0xFFFF, sum = 0
6922 22:13:04.054539 12, 0xFFFF, sum = 0
6923 22:13:04.055102 13, 0x0, sum = 1
6924 22:13:04.058407 14, 0x0, sum = 2
6925 22:13:04.058983 15, 0x0, sum = 3
6926 22:13:04.061527 16, 0x0, sum = 4
6927 22:13:04.062090 best_step = 14
6928 22:13:04.062514
6929 22:13:04.062865 ==
6930 22:13:04.065106 Dram Type= 6, Freq= 0, CH_1, rank 1
6931 22:13:04.067723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6932 22:13:04.068193 ==
6933 22:13:04.071093 RX Vref Scan: 0
6934 22:13:04.071553
6935 22:13:04.075004 RX Vref 0 -> 0, step: 1
6936 22:13:04.075559
6937 22:13:04.075933 RX Delay -327 -> 252, step: 8
6938 22:13:04.084099 iDelay=217, Bit 0, Center -16 (-231 ~ 200) 432
6939 22:13:04.086618 iDelay=217, Bit 1, Center -28 (-247 ~ 192) 440
6940 22:13:04.089897 iDelay=217, Bit 2, Center -32 (-255 ~ 192) 448
6941 22:13:04.097040 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6942 22:13:04.099808 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6943 22:13:04.103292 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6944 22:13:04.106325 iDelay=217, Bit 6, Center -16 (-239 ~ 208) 448
6945 22:13:04.112634 iDelay=217, Bit 7, Center -24 (-247 ~ 200) 448
6946 22:13:04.115946 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6947 22:13:04.119127 iDelay=217, Bit 9, Center -36 (-263 ~ 192) 456
6948 22:13:04.122778 iDelay=217, Bit 10, Center -24 (-255 ~ 208) 464
6949 22:13:04.129324 iDelay=217, Bit 11, Center -32 (-263 ~ 200) 464
6950 22:13:04.133088 iDelay=217, Bit 12, Center -16 (-247 ~ 216) 464
6951 22:13:04.136092 iDelay=217, Bit 13, Center -20 (-247 ~ 208) 456
6952 22:13:04.139411 iDelay=217, Bit 14, Center -24 (-255 ~ 208) 464
6953 22:13:04.146514 iDelay=217, Bit 15, Center -16 (-247 ~ 216) 464
6954 22:13:04.147071 ==
6955 22:13:04.149088 Dram Type= 6, Freq= 0, CH_1, rank 1
6956 22:13:04.153012 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6957 22:13:04.153579 ==
6958 22:13:04.153956 DQS Delay:
6959 22:13:04.155943 DQS0 = 32, DQS1 = 36
6960 22:13:04.156505 DQM Delay:
6961 22:13:04.159777 DQM0 = 11, DQM1 = 10
6962 22:13:04.160339 DQ Delay:
6963 22:13:04.162722 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8
6964 22:13:04.166088 DQ4 =16, DQ5 =24, DQ6 =16, DQ7 =8
6965 22:13:04.169150 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6966 22:13:04.173188 DQ12 =20, DQ13 =16, DQ14 =12, DQ15 =20
6967 22:13:04.173764
6968 22:13:04.174136
6969 22:13:04.179276 [DQSOSCAuto] RK1, (LSB)MR18= 0xa54e, (MSB)MR19= 0xc0c, tDQSOscB0 = 400 ps tDQSOscB1 = 389 ps
6970 22:13:04.182751 CH1 RK1: MR19=C0C, MR18=A54E
6971 22:13:04.189366 CH1_RK1: MR19=0xC0C, MR18=0xA54E, DQSOSC=389, MR23=63, INC=390, DEC=260
6972 22:13:04.192852 [RxdqsGatingPostProcess] freq 400
6973 22:13:04.199276 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6974 22:13:04.202305 best DQS0 dly(2T, 0.5T) = (0, 10)
6975 22:13:04.205639 best DQS1 dly(2T, 0.5T) = (0, 10)
6976 22:13:04.208828 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6977 22:13:04.212268 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6978 22:13:04.212908 best DQS0 dly(2T, 0.5T) = (0, 10)
6979 22:13:04.215409 best DQS1 dly(2T, 0.5T) = (0, 10)
6980 22:13:04.218997 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6981 22:13:04.222142 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6982 22:13:04.225942 Pre-setting of DQS Precalculation
6983 22:13:04.232300 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6984 22:13:04.238537 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6985 22:13:04.245140 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6986 22:13:04.245714
6987 22:13:04.246098
6988 22:13:04.248751 [Calibration Summary] 800 Mbps
6989 22:13:04.249317 CH 0, Rank 0
6990 22:13:04.251909 SW Impedance : PASS
6991 22:13:04.254851 DUTY Scan : NO K
6992 22:13:04.255317 ZQ Calibration : PASS
6993 22:13:04.258499 Jitter Meter : NO K
6994 22:13:04.262008 CBT Training : PASS
6995 22:13:04.262619 Write leveling : PASS
6996 22:13:04.265175 RX DQS gating : PASS
6997 22:13:04.268376 RX DQ/DQS(RDDQC) : PASS
6998 22:13:04.268844 TX DQ/DQS : PASS
6999 22:13:04.271515 RX DATLAT : PASS
7000 22:13:04.274938 RX DQ/DQS(Engine): PASS
7001 22:13:04.275505 TX OE : NO K
7002 22:13:04.278439 All Pass.
7003 22:13:04.278996
7004 22:13:04.279366 CH 0, Rank 1
7005 22:13:04.281765 SW Impedance : PASS
7006 22:13:04.282325 DUTY Scan : NO K
7007 22:13:04.285060 ZQ Calibration : PASS
7008 22:13:04.288186 Jitter Meter : NO K
7009 22:13:04.288749 CBT Training : PASS
7010 22:13:04.291627 Write leveling : NO K
7011 22:13:04.295313 RX DQS gating : PASS
7012 22:13:04.295874 RX DQ/DQS(RDDQC) : PASS
7013 22:13:04.298410 TX DQ/DQS : PASS
7014 22:13:04.298975 RX DATLAT : PASS
7015 22:13:04.301630 RX DQ/DQS(Engine): PASS
7016 22:13:04.304595 TX OE : NO K
7017 22:13:04.305159 All Pass.
7018 22:13:04.305531
7019 22:13:04.305873 CH 1, Rank 0
7020 22:13:04.308326 SW Impedance : PASS
7021 22:13:04.312008 DUTY Scan : NO K
7022 22:13:04.312600 ZQ Calibration : PASS
7023 22:13:04.314459 Jitter Meter : NO K
7024 22:13:04.317816 CBT Training : PASS
7025 22:13:04.318413 Write leveling : PASS
7026 22:13:04.321368 RX DQS gating : PASS
7027 22:13:04.324820 RX DQ/DQS(RDDQC) : PASS
7028 22:13:04.325393 TX DQ/DQS : PASS
7029 22:13:04.327705 RX DATLAT : PASS
7030 22:13:04.330949 RX DQ/DQS(Engine): PASS
7031 22:13:04.331411 TX OE : NO K
7032 22:13:04.335244 All Pass.
7033 22:13:04.335822
7034 22:13:04.336219 CH 1, Rank 1
7035 22:13:04.337268 SW Impedance : PASS
7036 22:13:04.337733 DUTY Scan : NO K
7037 22:13:04.340884 ZQ Calibration : PASS
7038 22:13:04.344736 Jitter Meter : NO K
7039 22:13:04.345203 CBT Training : PASS
7040 22:13:04.347320 Write leveling : NO K
7041 22:13:04.350747 RX DQS gating : PASS
7042 22:13:04.351231 RX DQ/DQS(RDDQC) : PASS
7043 22:13:04.354277 TX DQ/DQS : PASS
7044 22:13:04.358299 RX DATLAT : PASS
7045 22:13:04.358928 RX DQ/DQS(Engine): PASS
7046 22:13:04.360966 TX OE : NO K
7047 22:13:04.361542 All Pass.
7048 22:13:04.361922
7049 22:13:04.364034 DramC Write-DBI off
7050 22:13:04.367340 PER_BANK_REFRESH: Hybrid Mode
7051 22:13:04.367824 TX_TRACKING: ON
7052 22:13:04.377268 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7053 22:13:04.380387 [FAST_K] Save calibration result to emmc
7054 22:13:04.383592 dramc_set_vcore_voltage set vcore to 725000
7055 22:13:04.386987 Read voltage for 1600, 0
7056 22:13:04.387559 Vio18 = 0
7057 22:13:04.387939 Vcore = 725000
7058 22:13:04.390558 Vdram = 0
7059 22:13:04.391134 Vddq = 0
7060 22:13:04.391515 Vmddr = 0
7061 22:13:04.396854 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7062 22:13:04.400798 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7063 22:13:04.403541 MEM_TYPE=3, freq_sel=13
7064 22:13:04.407272 sv_algorithm_assistance_LP4_3733
7065 22:13:04.410852 ============ PULL DRAM RESETB DOWN ============
7066 22:13:04.413396 ========== PULL DRAM RESETB DOWN end =========
7067 22:13:04.419930 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7068 22:13:04.423090 ===================================
7069 22:13:04.426437 LPDDR4 DRAM CONFIGURATION
7070 22:13:04.429657 ===================================
7071 22:13:04.430130 EX_ROW_EN[0] = 0x0
7072 22:13:04.433216 EX_ROW_EN[1] = 0x0
7073 22:13:04.433683 LP4Y_EN = 0x0
7074 22:13:04.436565 WORK_FSP = 0x1
7075 22:13:04.437032 WL = 0x5
7076 22:13:04.439907 RL = 0x5
7077 22:13:04.440468 BL = 0x2
7078 22:13:04.442812 RPST = 0x0
7079 22:13:04.443280 RD_PRE = 0x0
7080 22:13:04.446394 WR_PRE = 0x1
7081 22:13:04.446958 WR_PST = 0x1
7082 22:13:04.449797 DBI_WR = 0x0
7083 22:13:04.452975 DBI_RD = 0x0
7084 22:13:04.453447 OTF = 0x1
7085 22:13:04.456104 ===================================
7086 22:13:04.459774 ===================================
7087 22:13:04.460352 ANA top config
7088 22:13:04.462564 ===================================
7089 22:13:04.466483 DLL_ASYNC_EN = 0
7090 22:13:04.469430 ALL_SLAVE_EN = 0
7091 22:13:04.473089 NEW_RANK_MODE = 1
7092 22:13:04.476007 DLL_IDLE_MODE = 1
7093 22:13:04.476568 LP45_APHY_COMB_EN = 1
7094 22:13:04.479253 TX_ODT_DIS = 0
7095 22:13:04.482583 NEW_8X_MODE = 1
7096 22:13:04.486495 ===================================
7097 22:13:04.489940 ===================================
7098 22:13:04.493089 data_rate = 3200
7099 22:13:04.495789 CKR = 1
7100 22:13:04.496256 DQ_P2S_RATIO = 8
7101 22:13:04.499296 ===================================
7102 22:13:04.502523 CA_P2S_RATIO = 8
7103 22:13:04.506317 DQ_CA_OPEN = 0
7104 22:13:04.509605 DQ_SEMI_OPEN = 0
7105 22:13:04.512673 CA_SEMI_OPEN = 0
7106 22:13:04.515918 CA_FULL_RATE = 0
7107 22:13:04.516486 DQ_CKDIV4_EN = 0
7108 22:13:04.519258 CA_CKDIV4_EN = 0
7109 22:13:04.522499 CA_PREDIV_EN = 0
7110 22:13:04.525448 PH8_DLY = 12
7111 22:13:04.529324 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7112 22:13:04.531959 DQ_AAMCK_DIV = 4
7113 22:13:04.535713 CA_AAMCK_DIV = 4
7114 22:13:04.536181 CA_ADMCK_DIV = 4
7115 22:13:04.538916 DQ_TRACK_CA_EN = 0
7116 22:13:04.542415 CA_PICK = 1600
7117 22:13:04.545516 CA_MCKIO = 1600
7118 22:13:04.548688 MCKIO_SEMI = 0
7119 22:13:04.551972 PLL_FREQ = 3068
7120 22:13:04.555477 DQ_UI_PI_RATIO = 32
7121 22:13:04.556049 CA_UI_PI_RATIO = 0
7122 22:13:04.558844 ===================================
7123 22:13:04.562408 ===================================
7124 22:13:04.565340 memory_type:LPDDR4
7125 22:13:04.568379 GP_NUM : 10
7126 22:13:04.568848 SRAM_EN : 1
7127 22:13:04.571954 MD32_EN : 0
7128 22:13:04.575657 ===================================
7129 22:13:04.578164 [ANA_INIT] >>>>>>>>>>>>>>
7130 22:13:04.581936 <<<<<< [CONFIGURE PHASE]: ANA_TX
7131 22:13:04.585365 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7132 22:13:04.589050 ===================================
7133 22:13:04.589638 data_rate = 3200,PCW = 0X7600
7134 22:13:04.591642 ===================================
7135 22:13:04.595290 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7136 22:13:04.602635 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7137 22:13:04.608341 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7138 22:13:04.611678 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7139 22:13:04.614925 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7140 22:13:04.618282 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7141 22:13:04.621986 [ANA_INIT] flow start
7142 22:13:04.624769 [ANA_INIT] PLL >>>>>>>>
7143 22:13:04.625250 [ANA_INIT] PLL <<<<<<<<
7144 22:13:04.628537 [ANA_INIT] MIDPI >>>>>>>>
7145 22:13:04.631224 [ANA_INIT] MIDPI <<<<<<<<
7146 22:13:04.631811 [ANA_INIT] DLL >>>>>>>>
7147 22:13:04.634484 [ANA_INIT] DLL <<<<<<<<
7148 22:13:04.638263 [ANA_INIT] flow end
7149 22:13:04.641473 ============ LP4 DIFF to SE enter ============
7150 22:13:04.644947 ============ LP4 DIFF to SE exit ============
7151 22:13:04.648132 [ANA_INIT] <<<<<<<<<<<<<
7152 22:13:04.651165 [Flow] Enable top DCM control >>>>>
7153 22:13:04.655131 [Flow] Enable top DCM control <<<<<
7154 22:13:04.657592 Enable DLL master slave shuffle
7155 22:13:04.661275 ==============================================================
7156 22:13:04.664153 Gating Mode config
7157 22:13:04.670882 ==============================================================
7158 22:13:04.671438 Config description:
7159 22:13:04.680801 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7160 22:13:04.687792 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7161 22:13:04.694391 SELPH_MODE 0: By rank 1: By Phase
7162 22:13:04.697406 ==============================================================
7163 22:13:04.700993 GAT_TRACK_EN = 1
7164 22:13:04.704287 RX_GATING_MODE = 2
7165 22:13:04.707252 RX_GATING_TRACK_MODE = 2
7166 22:13:04.710807 SELPH_MODE = 1
7167 22:13:04.713814 PICG_EARLY_EN = 1
7168 22:13:04.717051 VALID_LAT_VALUE = 1
7169 22:13:04.720684 ==============================================================
7170 22:13:04.723872 Enter into Gating configuration >>>>
7171 22:13:04.727259 Exit from Gating configuration <<<<
7172 22:13:04.731080 Enter into DVFS_PRE_config >>>>>
7173 22:13:04.743418 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7174 22:13:04.747804 Exit from DVFS_PRE_config <<<<<
7175 22:13:04.750103 Enter into PICG configuration >>>>
7176 22:13:04.753303 Exit from PICG configuration <<<<
7177 22:13:04.753867 [RX_INPUT] configuration >>>>>
7178 22:13:04.756781 [RX_INPUT] configuration <<<<<
7179 22:13:04.763848 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7180 22:13:04.766709 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7181 22:13:04.773353 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7182 22:13:04.779942 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7183 22:13:04.787338 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7184 22:13:04.793323 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7185 22:13:04.796749 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7186 22:13:04.799975 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7187 22:13:04.806452 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7188 22:13:04.809673 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7189 22:13:04.813040 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7190 22:13:04.816347 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7191 22:13:04.820025 ===================================
7192 22:13:04.823027 LPDDR4 DRAM CONFIGURATION
7193 22:13:04.826636 ===================================
7194 22:13:04.830083 EX_ROW_EN[0] = 0x0
7195 22:13:04.830695 EX_ROW_EN[1] = 0x0
7196 22:13:04.832944 LP4Y_EN = 0x0
7197 22:13:04.833511 WORK_FSP = 0x1
7198 22:13:04.837297 WL = 0x5
7199 22:13:04.837868 RL = 0x5
7200 22:13:04.839112 BL = 0x2
7201 22:13:04.843305 RPST = 0x0
7202 22:13:04.843883 RD_PRE = 0x0
7203 22:13:04.846099 WR_PRE = 0x1
7204 22:13:04.846728 WR_PST = 0x1
7205 22:13:04.849593 DBI_WR = 0x0
7206 22:13:04.850242 DBI_RD = 0x0
7207 22:13:04.852773 OTF = 0x1
7208 22:13:04.855751 ===================================
7209 22:13:04.858885 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7210 22:13:04.862145 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7211 22:13:04.865915 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7212 22:13:04.869595 ===================================
7213 22:13:04.872430 LPDDR4 DRAM CONFIGURATION
7214 22:13:04.876041 ===================================
7215 22:13:04.879061 EX_ROW_EN[0] = 0x10
7216 22:13:04.879530 EX_ROW_EN[1] = 0x0
7217 22:13:04.882408 LP4Y_EN = 0x0
7218 22:13:04.882876 WORK_FSP = 0x1
7219 22:13:04.885697 WL = 0x5
7220 22:13:04.886272 RL = 0x5
7221 22:13:04.889105 BL = 0x2
7222 22:13:04.892034 RPST = 0x0
7223 22:13:04.892593 RD_PRE = 0x0
7224 22:13:04.895437 WR_PRE = 0x1
7225 22:13:04.896000 WR_PST = 0x1
7226 22:13:04.899265 DBI_WR = 0x0
7227 22:13:04.899830 DBI_RD = 0x0
7228 22:13:04.902147 OTF = 0x1
7229 22:13:04.905280 ===================================
7230 22:13:04.912401 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7231 22:13:04.912969 ==
7232 22:13:04.914824 Dram Type= 6, Freq= 0, CH_0, rank 0
7233 22:13:04.918475 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7234 22:13:04.919055 ==
7235 22:13:04.922001 [Duty_Offset_Calibration]
7236 22:13:04.922596 B0:2 B1:0 CA:1
7237 22:13:04.922973
7238 22:13:04.924843 [DutyScan_Calibration_Flow] k_type=0
7239 22:13:04.934713
7240 22:13:04.935273 ==CLK 0==
7241 22:13:04.938176 Final CLK duty delay cell = -4
7242 22:13:04.941833 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7243 22:13:04.945275 [-4] MIN Duty = 4813%(X100), DQS PI = 0
7244 22:13:04.947537 [-4] AVG Duty = 4922%(X100)
7245 22:13:04.948006
7246 22:13:04.951388 CH0 CLK Duty spec in!! Max-Min= 218%
7247 22:13:04.954260 [DutyScan_Calibration_Flow] ====Done====
7248 22:13:04.954985
7249 22:13:04.957028 [DutyScan_Calibration_Flow] k_type=1
7250 22:13:04.974100
7251 22:13:04.974715 ==DQS 0 ==
7252 22:13:04.977427 Final DQS duty delay cell = 0
7253 22:13:04.980612 [0] MAX Duty = 5249%(X100), DQS PI = 32
7254 22:13:04.984819 [0] MIN Duty = 4969%(X100), DQS PI = 0
7255 22:13:04.987618 [0] AVG Duty = 5109%(X100)
7256 22:13:04.988088
7257 22:13:04.988460 ==DQS 1 ==
7258 22:13:04.990563 Final DQS duty delay cell = -4
7259 22:13:04.993714 [-4] MAX Duty = 5125%(X100), DQS PI = 28
7260 22:13:04.997220 [-4] MIN Duty = 4875%(X100), DQS PI = 4
7261 22:13:05.000419 [-4] AVG Duty = 5000%(X100)
7262 22:13:05.000978
7263 22:13:05.003939 CH0 DQS 0 Duty spec in!! Max-Min= 280%
7264 22:13:05.004503
7265 22:13:05.007275 CH0 DQS 1 Duty spec in!! Max-Min= 250%
7266 22:13:05.011014 [DutyScan_Calibration_Flow] ====Done====
7267 22:13:05.011572
7268 22:13:05.013569 [DutyScan_Calibration_Flow] k_type=3
7269 22:13:05.030873
7270 22:13:05.031433 ==DQM 0 ==
7271 22:13:05.033572 Final DQM duty delay cell = 0
7272 22:13:05.037303 [0] MAX Duty = 5093%(X100), DQS PI = 26
7273 22:13:05.040759 [0] MIN Duty = 4813%(X100), DQS PI = 52
7274 22:13:05.043821 [0] AVG Duty = 4953%(X100)
7275 22:13:05.044380
7276 22:13:05.044752 ==DQM 1 ==
7277 22:13:05.047172 Final DQM duty delay cell = -4
7278 22:13:05.050579 [-4] MAX Duty = 5031%(X100), DQS PI = 44
7279 22:13:05.053586 [-4] MIN Duty = 4751%(X100), DQS PI = 10
7280 22:13:05.056930 [-4] AVG Duty = 4891%(X100)
7281 22:13:05.057534
7282 22:13:05.059899 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7283 22:13:05.060464
7284 22:13:05.063008 CH0 DQM 1 Duty spec in!! Max-Min= 280%
7285 22:13:05.066602 [DutyScan_Calibration_Flow] ====Done====
7286 22:13:05.067167
7287 22:13:05.070624 [DutyScan_Calibration_Flow] k_type=2
7288 22:13:05.088064
7289 22:13:05.088621 ==DQ 0 ==
7290 22:13:05.091738 Final DQ duty delay cell = 0
7291 22:13:05.094484 [0] MAX Duty = 5156%(X100), DQS PI = 36
7292 22:13:05.097908 [0] MIN Duty = 5000%(X100), DQS PI = 16
7293 22:13:05.098387 [0] AVG Duty = 5078%(X100)
7294 22:13:05.101447
7295 22:13:05.101899 ==DQ 1 ==
7296 22:13:05.104431 Final DQ duty delay cell = 0
7297 22:13:05.107684 [0] MAX Duty = 4969%(X100), DQS PI = 44
7298 22:13:05.111092 [0] MIN Duty = 4875%(X100), DQS PI = 10
7299 22:13:05.111549 [0] AVG Duty = 4922%(X100)
7300 22:13:05.111909
7301 22:13:05.117638 CH0 DQ 0 Duty spec in!! Max-Min= 156%
7302 22:13:05.118142
7303 22:13:05.121424 CH0 DQ 1 Duty spec in!! Max-Min= 94%
7304 22:13:05.125135 [DutyScan_Calibration_Flow] ====Done====
7305 22:13:05.125552 ==
7306 22:13:05.127903 Dram Type= 6, Freq= 0, CH_1, rank 0
7307 22:13:05.131033 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7308 22:13:05.131449 ==
7309 22:13:05.134313 [Duty_Offset_Calibration]
7310 22:13:05.134767 B0:0 B1:-1 CA:2
7311 22:13:05.135035
7312 22:13:05.138109 [DutyScan_Calibration_Flow] k_type=0
7313 22:13:05.148450
7314 22:13:05.148957 ==CLK 0==
7315 22:13:05.152444 Final CLK duty delay cell = 0
7316 22:13:05.154962 [0] MAX Duty = 5156%(X100), DQS PI = 40
7317 22:13:05.158585 [0] MIN Duty = 4906%(X100), DQS PI = 12
7318 22:13:05.161555 [0] AVG Duty = 5031%(X100)
7319 22:13:05.162050
7320 22:13:05.165541 CH1 CLK Duty spec in!! Max-Min= 250%
7321 22:13:05.168487 [DutyScan_Calibration_Flow] ====Done====
7322 22:13:05.169184
7323 22:13:05.171151 [DutyScan_Calibration_Flow] k_type=1
7324 22:13:05.188072
7325 22:13:05.188627 ==DQS 0 ==
7326 22:13:05.191387 Final DQS duty delay cell = 0
7327 22:13:05.194627 [0] MAX Duty = 5093%(X100), DQS PI = 10
7328 22:13:05.197741 [0] MIN Duty = 5000%(X100), DQS PI = 0
7329 22:13:05.201219 [0] AVG Duty = 5046%(X100)
7330 22:13:05.201767
7331 22:13:05.202125 ==DQS 1 ==
7332 22:13:05.204660 Final DQS duty delay cell = 0
7333 22:13:05.207796 [0] MAX Duty = 5218%(X100), DQS PI = 28
7334 22:13:05.211179 [0] MIN Duty = 4813%(X100), DQS PI = 2
7335 22:13:05.214953 [0] AVG Duty = 5015%(X100)
7336 22:13:05.215509
7337 22:13:05.217854 CH1 DQS 0 Duty spec in!! Max-Min= 93%
7338 22:13:05.218497
7339 22:13:05.221139 CH1 DQS 1 Duty spec in!! Max-Min= 405%
7340 22:13:05.224591 [DutyScan_Calibration_Flow] ====Done====
7341 22:13:05.225134
7342 22:13:05.227762 [DutyScan_Calibration_Flow] k_type=3
7343 22:13:05.245119
7344 22:13:05.245663 ==DQM 0 ==
7345 22:13:05.248215 Final DQM duty delay cell = 4
7346 22:13:05.251564 [4] MAX Duty = 5156%(X100), DQS PI = 24
7347 22:13:05.254451 [4] MIN Duty = 4969%(X100), DQS PI = 2
7348 22:13:05.258310 [4] AVG Duty = 5062%(X100)
7349 22:13:05.258896
7350 22:13:05.259260 ==DQM 1 ==
7351 22:13:05.261378 Final DQM duty delay cell = -4
7352 22:13:05.264313 [-4] MAX Duty = 4969%(X100), DQS PI = 30
7353 22:13:05.268765 [-4] MIN Duty = 4719%(X100), DQS PI = 0
7354 22:13:05.270965 [-4] AVG Duty = 4844%(X100)
7355 22:13:05.271470
7356 22:13:05.274581 CH1 DQM 0 Duty spec in!! Max-Min= 187%
7357 22:13:05.275144
7358 22:13:05.277837 CH1 DQM 1 Duty spec in!! Max-Min= 250%
7359 22:13:05.281284 [DutyScan_Calibration_Flow] ====Done====
7360 22:13:05.281866
7361 22:13:05.284348 [DutyScan_Calibration_Flow] k_type=2
7362 22:13:05.301699
7363 22:13:05.302255 ==DQ 0 ==
7364 22:13:05.305184 Final DQ duty delay cell = 0
7365 22:13:05.308592 [0] MAX Duty = 5093%(X100), DQS PI = 22
7366 22:13:05.311997 [0] MIN Duty = 4938%(X100), DQS PI = 0
7367 22:13:05.312560 [0] AVG Duty = 5015%(X100)
7368 22:13:05.312936
7369 22:13:05.314992 ==DQ 1 ==
7370 22:13:05.318132 Final DQ duty delay cell = 0
7371 22:13:05.321757 [0] MAX Duty = 5094%(X100), DQS PI = 34
7372 22:13:05.325313 [0] MIN Duty = 4813%(X100), DQS PI = 2
7373 22:13:05.325870 [0] AVG Duty = 4953%(X100)
7374 22:13:05.329021
7375 22:13:05.331176 CH1 DQ 0 Duty spec in!! Max-Min= 155%
7376 22:13:05.331646
7377 22:13:05.334940 CH1 DQ 1 Duty spec in!! Max-Min= 281%
7378 22:13:05.337962 [DutyScan_Calibration_Flow] ====Done====
7379 22:13:05.341167 nWR fixed to 30
7380 22:13:05.341634 [ModeRegInit_LP4] CH0 RK0
7381 22:13:05.344507 [ModeRegInit_LP4] CH0 RK1
7382 22:13:05.348050 [ModeRegInit_LP4] CH1 RK0
7383 22:13:05.351266 [ModeRegInit_LP4] CH1 RK1
7384 22:13:05.351826 match AC timing 5
7385 22:13:05.357985 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7386 22:13:05.361291 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7387 22:13:05.364714 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7388 22:13:05.370922 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7389 22:13:05.374324 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7390 22:13:05.374925 [MiockJmeterHQA]
7391 22:13:05.375295
7392 22:13:05.377724 [DramcMiockJmeter] u1RxGatingPI = 0
7393 22:13:05.380967 0 : 4252, 4027
7394 22:13:05.381548 4 : 4252, 4027
7395 22:13:05.383905 8 : 4252, 4027
7396 22:13:05.384377 12 : 4252, 4027
7397 22:13:05.387402 16 : 4253, 4027
7398 22:13:05.387978 20 : 4255, 4029
7399 22:13:05.388358 24 : 4253, 4027
7400 22:13:05.390484 28 : 4364, 4137
7401 22:13:05.390961 32 : 4252, 4027
7402 22:13:05.394247 36 : 4252, 4027
7403 22:13:05.394891 40 : 4252, 4027
7404 22:13:05.397422 44 : 4255, 4030
7405 22:13:05.398073 48 : 4363, 4138
7406 22:13:05.400455 52 : 4363, 4137
7407 22:13:05.400927 56 : 4252, 4027
7408 22:13:05.401301 60 : 4253, 4026
7409 22:13:05.403769 64 : 4252, 4027
7410 22:13:05.404240 68 : 4253, 4029
7411 22:13:05.406857 72 : 4361, 4137
7412 22:13:05.407327 76 : 4250, 4027
7413 22:13:05.410919 80 : 4363, 4140
7414 22:13:05.411496 84 : 4255, 4029
7415 22:13:05.414930 88 : 4250, 3645
7416 22:13:05.415519 92 : 4250, 0
7417 22:13:05.415899 96 : 4363, 0
7418 22:13:05.417610 100 : 4250, 0
7419 22:13:05.418081 104 : 4250, 0
7420 22:13:05.418479 108 : 4250, 0
7421 22:13:05.420358 112 : 4250, 0
7422 22:13:05.421002 116 : 4252, 0
7423 22:13:05.423710 120 : 4360, 0
7424 22:13:05.424182 124 : 4250, 0
7425 22:13:05.424562 128 : 4249, 0
7426 22:13:05.426994 132 : 4255, 0
7427 22:13:05.427465 136 : 4361, 0
7428 22:13:05.430495 140 : 4250, 0
7429 22:13:05.431073 144 : 4253, 0
7430 22:13:05.431457 148 : 4250, 0
7431 22:13:05.433847 152 : 4361, 0
7432 22:13:05.434459 156 : 4250, 0
7433 22:13:05.437649 160 : 4252, 0
7434 22:13:05.438225 164 : 4250, 0
7435 22:13:05.438650 168 : 4252, 0
7436 22:13:05.439967 172 : 4363, 0
7437 22:13:05.440439 176 : 4252, 0
7438 22:13:05.443574 180 : 4250, 0
7439 22:13:05.444149 184 : 4250, 0
7440 22:13:05.444528 188 : 4361, 0
7441 22:13:05.446742 192 : 4249, 0
7442 22:13:05.447315 196 : 4250, 0
7443 22:13:05.447693 200 : 4250, 9
7444 22:13:05.450321 204 : 4361, 2368
7445 22:13:05.450916 208 : 4361, 4138
7446 22:13:05.453437 212 : 4361, 4138
7447 22:13:05.453905 216 : 4248, 4024
7448 22:13:05.456756 220 : 4250, 4027
7449 22:13:05.457334 224 : 4361, 4138
7450 22:13:05.460087 228 : 4361, 4137
7451 22:13:05.460663 232 : 4250, 4026
7452 22:13:05.463086 236 : 4250, 4027
7453 22:13:05.463557 240 : 4250, 4027
7454 22:13:05.466409 244 : 4250, 4026
7455 22:13:05.466884 248 : 4250, 4026
7456 22:13:05.469540 252 : 4252, 4030
7457 22:13:05.470017 256 : 4250, 4027
7458 22:13:05.473152 260 : 4361, 4138
7459 22:13:05.473628 264 : 4250, 4027
7460 22:13:05.474004 268 : 4250, 4027
7461 22:13:05.476420 272 : 4250, 4027
7462 22:13:05.476897 276 : 4361, 4138
7463 22:13:05.480081 280 : 4361, 4137
7464 22:13:05.480663 284 : 4250, 4027
7465 22:13:05.483247 288 : 4363, 4140
7466 22:13:05.483726 292 : 4250, 4027
7467 22:13:05.486735 296 : 4250, 4026
7468 22:13:05.487308 300 : 4250, 4026
7469 22:13:05.490499 304 : 4252, 4030
7470 22:13:05.491077 308 : 4250, 4027
7471 22:13:05.492766 312 : 4361, 4003
7472 22:13:05.493244 316 : 4250, 1797
7473 22:13:05.493621
7474 22:13:05.496387 MIOCK jitter meter ch=0
7475 22:13:05.496957
7476 22:13:05.499528 1T = (316-92) = 224 dly cells
7477 22:13:05.502850 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7478 22:13:05.503420 ==
7479 22:13:05.506162 Dram Type= 6, Freq= 0, CH_0, rank 0
7480 22:13:05.512654 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7481 22:13:05.513212 ==
7482 22:13:05.516537 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7483 22:13:05.522550 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7484 22:13:05.526413 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7485 22:13:05.532974 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7486 22:13:05.541256 [CA 0] Center 42 (12~72) winsize 61
7487 22:13:05.544279 [CA 1] Center 42 (12~72) winsize 61
7488 22:13:05.547282 [CA 2] Center 37 (7~67) winsize 61
7489 22:13:05.550528 [CA 3] Center 37 (7~67) winsize 61
7490 22:13:05.553408 [CA 4] Center 36 (6~66) winsize 61
7491 22:13:05.556621 [CA 5] Center 35 (5~65) winsize 61
7492 22:13:05.557086
7493 22:13:05.560393 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7494 22:13:05.563566
7495 22:13:05.566732 [CATrainingPosCal] consider 1 rank data
7496 22:13:05.567297 u2DelayCellTimex100 = 290/100 ps
7497 22:13:05.573875 CA0 delay=42 (12~72),Diff = 7 PI (23 cell)
7498 22:13:05.577602 CA1 delay=42 (12~72),Diff = 7 PI (23 cell)
7499 22:13:05.580007 CA2 delay=37 (7~67),Diff = 2 PI (6 cell)
7500 22:13:05.583181 CA3 delay=37 (7~67),Diff = 2 PI (6 cell)
7501 22:13:05.586175 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7502 22:13:05.589752 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7503 22:13:05.590216
7504 22:13:05.593423 CA PerBit enable=1, Macro0, CA PI delay=35
7505 22:13:05.593984
7506 22:13:05.596695 [CBTSetCACLKResult] CA Dly = 35
7507 22:13:05.599583 CS Dly: 10 (0~41)
7508 22:13:05.603263 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7509 22:13:05.606687 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7510 22:13:05.607269 ==
7511 22:13:05.610259 Dram Type= 6, Freq= 0, CH_0, rank 1
7512 22:13:05.616566 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7513 22:13:05.617135 ==
7514 22:13:05.619979 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7515 22:13:05.625913 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7516 22:13:05.629018 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7517 22:13:05.635780 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7518 22:13:05.643867 [CA 0] Center 43 (13~74) winsize 62
7519 22:13:05.647286 [CA 1] Center 43 (13~73) winsize 61
7520 22:13:05.650188 [CA 2] Center 38 (9~68) winsize 60
7521 22:13:05.653991 [CA 3] Center 38 (9~68) winsize 60
7522 22:13:05.657100 [CA 4] Center 37 (7~67) winsize 61
7523 22:13:05.660090 [CA 5] Center 36 (7~66) winsize 60
7524 22:13:05.660557
7525 22:13:05.663716 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7526 22:13:05.664280
7527 22:13:05.666919 [CATrainingPosCal] consider 2 rank data
7528 22:13:05.670846 u2DelayCellTimex100 = 290/100 ps
7529 22:13:05.677073 CA0 delay=42 (13~72),Diff = 6 PI (20 cell)
7530 22:13:05.680194 CA1 delay=42 (13~72),Diff = 6 PI (20 cell)
7531 22:13:05.683702 CA2 delay=38 (9~67),Diff = 2 PI (6 cell)
7532 22:13:05.686864 CA3 delay=38 (9~67),Diff = 2 PI (6 cell)
7533 22:13:05.690103 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7534 22:13:05.693443 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
7535 22:13:05.694001
7536 22:13:05.697020 CA PerBit enable=1, Macro0, CA PI delay=36
7537 22:13:05.697588
7538 22:13:05.699804 [CBTSetCACLKResult] CA Dly = 36
7539 22:13:05.703288 CS Dly: 11 (0~43)
7540 22:13:05.706670 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7541 22:13:05.709691 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7542 22:13:05.710312
7543 22:13:05.713117 ----->DramcWriteLeveling(PI) begin...
7544 22:13:05.713685 ==
7545 22:13:05.717001 Dram Type= 6, Freq= 0, CH_0, rank 0
7546 22:13:05.723177 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7547 22:13:05.723748 ==
7548 22:13:05.726338 Write leveling (Byte 0): 36 => 36
7549 22:13:05.730048 Write leveling (Byte 1): 33 => 33
7550 22:13:05.730662 DramcWriteLeveling(PI) end<-----
7551 22:13:05.731044
7552 22:13:05.733291 ==
7553 22:13:05.736231 Dram Type= 6, Freq= 0, CH_0, rank 0
7554 22:13:05.739872 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7555 22:13:05.740341 ==
7556 22:13:05.743197 [Gating] SW mode calibration
7557 22:13:05.749650 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7558 22:13:05.753262 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7559 22:13:05.759781 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7560 22:13:05.762663 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7561 22:13:05.766443 1 4 8 | B1->B0 | 2323 2929 | 0 1 | (0 0) (1 1)
7562 22:13:05.772591 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7563 22:13:05.776390 1 4 16 | B1->B0 | 2322 3434 | 1 1 | (0 0) (1 1)
7564 22:13:05.779087 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7565 22:13:05.786379 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7566 22:13:05.789536 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7567 22:13:05.792792 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7568 22:13:05.799049 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7569 22:13:05.802821 1 5 8 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
7570 22:13:05.805566 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7571 22:13:05.812888 1 5 16 | B1->B0 | 3232 2323 | 0 0 | (0 1) (0 0)
7572 22:13:05.815757 1 5 20 | B1->B0 | 2929 2323 | 1 0 | (1 0) (0 0)
7573 22:13:05.819226 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7574 22:13:05.825380 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7575 22:13:05.828758 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7576 22:13:05.832417 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7577 22:13:05.838640 1 6 8 | B1->B0 | 2323 3d3d | 0 0 | (0 0) (0 0)
7578 22:13:05.842001 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7579 22:13:05.845440 1 6 16 | B1->B0 | 2e2e 4646 | 0 0 | (1 1) (0 0)
7580 22:13:05.851860 1 6 20 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
7581 22:13:05.856234 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7582 22:13:05.858561 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7583 22:13:05.865239 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7584 22:13:05.868642 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7585 22:13:05.871791 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7586 22:13:05.878657 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7587 22:13:05.881966 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7588 22:13:05.885172 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7589 22:13:05.892181 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7590 22:13:05.894942 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7591 22:13:05.898568 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7592 22:13:05.904808 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7593 22:13:05.908131 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7594 22:13:05.911375 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7595 22:13:05.917943 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7596 22:13:05.921188 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7597 22:13:05.924230 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7598 22:13:05.931148 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7599 22:13:05.934568 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7600 22:13:05.937612 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7601 22:13:05.944465 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7602 22:13:05.947567 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7603 22:13:05.951408 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7604 22:13:05.954155 Total UI for P1: 0, mck2ui 16
7605 22:13:05.957604 best dqsien dly found for B0: ( 1, 9, 10)
7606 22:13:05.964667 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7607 22:13:05.967661 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7608 22:13:05.970770 Total UI for P1: 0, mck2ui 16
7609 22:13:05.973909 best dqsien dly found for B1: ( 1, 9, 18)
7610 22:13:05.977294 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7611 22:13:05.980810 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7612 22:13:05.981384
7613 22:13:05.984767 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7614 22:13:05.987316 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7615 22:13:05.990531 [Gating] SW calibration Done
7616 22:13:05.991104 ==
7617 22:13:05.994535 Dram Type= 6, Freq= 0, CH_0, rank 0
7618 22:13:06.001378 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7619 22:13:06.001956 ==
7620 22:13:06.002338 RX Vref Scan: 0
7621 22:13:06.002723
7622 22:13:06.003649 RX Vref 0 -> 0, step: 1
7623 22:13:06.004116
7624 22:13:06.007230 RX Delay 0 -> 252, step: 8
7625 22:13:06.010611 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7626 22:13:06.013644 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7627 22:13:06.017062 iDelay=200, Bit 2, Center 135 (88 ~ 183) 96
7628 22:13:06.020475 iDelay=200, Bit 3, Center 135 (88 ~ 183) 96
7629 22:13:06.027155 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7630 22:13:06.030584 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7631 22:13:06.033363 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7632 22:13:06.036537 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7633 22:13:06.040053 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7634 22:13:06.046906 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7635 22:13:06.049731 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7636 22:13:06.053597 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
7637 22:13:06.056531 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7638 22:13:06.059865 iDelay=200, Bit 13, Center 127 (80 ~ 175) 96
7639 22:13:06.066624 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7640 22:13:06.069743 iDelay=200, Bit 15, Center 135 (88 ~ 183) 96
7641 22:13:06.070213 ==
7642 22:13:06.073005 Dram Type= 6, Freq= 0, CH_0, rank 0
7643 22:13:06.076838 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7644 22:13:06.077404 ==
7645 22:13:06.080295 DQS Delay:
7646 22:13:06.080858 DQS0 = 0, DQS1 = 0
7647 22:13:06.081236 DQM Delay:
7648 22:13:06.083456 DQM0 = 137, DQM1 = 127
7649 22:13:06.084019 DQ Delay:
7650 22:13:06.086141 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
7651 22:13:06.089804 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =147
7652 22:13:06.093351 DQ8 =119, DQ9 =115, DQ10 =123, DQ11 =127
7653 22:13:06.099678 DQ12 =131, DQ13 =127, DQ14 =139, DQ15 =135
7654 22:13:06.100252
7655 22:13:06.100628
7656 22:13:06.100970 ==
7657 22:13:06.103324 Dram Type= 6, Freq= 0, CH_0, rank 0
7658 22:13:06.106162 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7659 22:13:06.106769 ==
7660 22:13:06.107148
7661 22:13:06.107491
7662 22:13:06.109649 TX Vref Scan disable
7663 22:13:06.110210 == TX Byte 0 ==
7664 22:13:06.116331 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7665 22:13:06.119898 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7666 22:13:06.120554 == TX Byte 1 ==
7667 22:13:06.126089 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7668 22:13:06.129388 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7669 22:13:06.129955 ==
7670 22:13:06.133046 Dram Type= 6, Freq= 0, CH_0, rank 0
7671 22:13:06.135772 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7672 22:13:06.136239 ==
7673 22:13:06.150405
7674 22:13:06.153268 TX Vref early break, caculate TX vref
7675 22:13:06.156364 TX Vref=16, minBit 12, minWin=22, winSum=377
7676 22:13:06.160120 TX Vref=18, minBit 6, minWin=23, winSum=386
7677 22:13:06.163463 TX Vref=20, minBit 7, minWin=23, winSum=398
7678 22:13:06.166829 TX Vref=22, minBit 0, minWin=24, winSum=406
7679 22:13:06.169997 TX Vref=24, minBit 7, minWin=24, winSum=412
7680 22:13:06.177198 TX Vref=26, minBit 0, minWin=26, winSum=426
7681 22:13:06.180128 TX Vref=28, minBit 0, minWin=26, winSum=428
7682 22:13:06.183572 TX Vref=30, minBit 0, minWin=25, winSum=419
7683 22:13:06.186823 TX Vref=32, minBit 0, minWin=25, winSum=416
7684 22:13:06.190190 TX Vref=34, minBit 0, minWin=24, winSum=404
7685 22:13:06.196727 [TxChooseVref] Worse bit 0, Min win 26, Win sum 428, Final Vref 28
7686 22:13:06.197295
7687 22:13:06.200384 Final TX Range 0 Vref 28
7688 22:13:06.200856
7689 22:13:06.201227 ==
7690 22:13:06.203089 Dram Type= 6, Freq= 0, CH_0, rank 0
7691 22:13:06.206406 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7692 22:13:06.206986 ==
7693 22:13:06.207362
7694 22:13:06.207707
7695 22:13:06.209712 TX Vref Scan disable
7696 22:13:06.217011 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7697 22:13:06.217584 == TX Byte 0 ==
7698 22:13:06.219566 u2DelayCellOfst[0]=10 cells (3 PI)
7699 22:13:06.223046 u2DelayCellOfst[1]=16 cells (5 PI)
7700 22:13:06.226265 u2DelayCellOfst[2]=10 cells (3 PI)
7701 22:13:06.229827 u2DelayCellOfst[3]=10 cells (3 PI)
7702 22:13:06.233189 u2DelayCellOfst[4]=6 cells (2 PI)
7703 22:13:06.236606 u2DelayCellOfst[5]=0 cells (0 PI)
7704 22:13:06.239976 u2DelayCellOfst[6]=16 cells (5 PI)
7705 22:13:06.243185 u2DelayCellOfst[7]=13 cells (4 PI)
7706 22:13:06.245882 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7707 22:13:06.249424 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7708 22:13:06.252593 == TX Byte 1 ==
7709 22:13:06.255907 u2DelayCellOfst[8]=0 cells (0 PI)
7710 22:13:06.256466 u2DelayCellOfst[9]=0 cells (0 PI)
7711 22:13:06.258874 u2DelayCellOfst[10]=6 cells (2 PI)
7712 22:13:06.262460 u2DelayCellOfst[11]=3 cells (1 PI)
7713 22:13:06.265532 u2DelayCellOfst[12]=13 cells (4 PI)
7714 22:13:06.269047 u2DelayCellOfst[13]=10 cells (3 PI)
7715 22:13:06.272528 u2DelayCellOfst[14]=16 cells (5 PI)
7716 22:13:06.276129 u2DelayCellOfst[15]=10 cells (3 PI)
7717 22:13:06.279739 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7718 22:13:06.286105 Update DQM dly =988 (3 ,6, 28) DQM OEN =(3 ,3)
7719 22:13:06.286699 DramC Write-DBI on
7720 22:13:06.287103 ==
7721 22:13:06.288993 Dram Type= 6, Freq= 0, CH_0, rank 0
7722 22:13:06.295500 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7723 22:13:06.296068 ==
7724 22:13:06.296446
7725 22:13:06.296792
7726 22:13:06.297121 TX Vref Scan disable
7727 22:13:06.299215 == TX Byte 0 ==
7728 22:13:06.303067 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7729 22:13:06.306176 == TX Byte 1 ==
7730 22:13:06.309419 Update DQM dly =729 (2 ,6, 25) DQM OEN =(3 ,3)
7731 22:13:06.313517 DramC Write-DBI off
7732 22:13:06.314080
7733 22:13:06.314507 [DATLAT]
7734 22:13:06.314866 Freq=1600, CH0 RK0
7735 22:13:06.315205
7736 22:13:06.315848 DATLAT Default: 0xf
7737 22:13:06.316206 0, 0xFFFF, sum = 0
7738 22:13:06.319813 1, 0xFFFF, sum = 0
7739 22:13:06.322999 2, 0xFFFF, sum = 0
7740 22:13:06.323566 3, 0xFFFF, sum = 0
7741 22:13:06.326266 4, 0xFFFF, sum = 0
7742 22:13:06.326885 5, 0xFFFF, sum = 0
7743 22:13:06.329161 6, 0xFFFF, sum = 0
7744 22:13:06.329726 7, 0xFFFF, sum = 0
7745 22:13:06.333411 8, 0xFFFF, sum = 0
7746 22:13:06.333984 9, 0xFFFF, sum = 0
7747 22:13:06.336766 10, 0xFFFF, sum = 0
7748 22:13:06.337338 11, 0xFFFF, sum = 0
7749 22:13:06.338975 12, 0xFFFF, sum = 0
7750 22:13:06.339446 13, 0xFFFF, sum = 0
7751 22:13:06.342467 14, 0x0, sum = 1
7752 22:13:06.342936 15, 0x0, sum = 2
7753 22:13:06.345832 16, 0x0, sum = 3
7754 22:13:06.346298 17, 0x0, sum = 4
7755 22:13:06.348887 best_step = 15
7756 22:13:06.349447
7757 22:13:06.349870 ==
7758 22:13:06.352514 Dram Type= 6, Freq= 0, CH_0, rank 0
7759 22:13:06.355420 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7760 22:13:06.355937 ==
7761 22:13:06.359161 RX Vref Scan: 1
7762 22:13:06.359618
7763 22:13:06.359979 Set Vref Range= 24 -> 127
7764 22:13:06.360322
7765 22:13:06.362411 RX Vref 24 -> 127, step: 1
7766 22:13:06.362887
7767 22:13:06.365333 RX Delay 19 -> 252, step: 4
7768 22:13:06.365807
7769 22:13:06.369031 Set Vref, RX VrefLevel [Byte0]: 24
7770 22:13:06.372217 [Byte1]: 24
7771 22:13:06.372685
7772 22:13:06.375128 Set Vref, RX VrefLevel [Byte0]: 25
7773 22:13:06.378966 [Byte1]: 25
7774 22:13:06.381885
7775 22:13:06.382383 Set Vref, RX VrefLevel [Byte0]: 26
7776 22:13:06.385626 [Byte1]: 26
7777 22:13:06.390224
7778 22:13:06.390828 Set Vref, RX VrefLevel [Byte0]: 27
7779 22:13:06.393264 [Byte1]: 27
7780 22:13:06.397313
7781 22:13:06.397879 Set Vref, RX VrefLevel [Byte0]: 28
7782 22:13:06.400368 [Byte1]: 28
7783 22:13:06.405481
7784 22:13:06.406054 Set Vref, RX VrefLevel [Byte0]: 29
7785 22:13:06.408291 [Byte1]: 29
7786 22:13:06.412489
7787 22:13:06.415581 Set Vref, RX VrefLevel [Byte0]: 30
7788 22:13:06.419033 [Byte1]: 30
7789 22:13:06.419607
7790 22:13:06.422961 Set Vref, RX VrefLevel [Byte0]: 31
7791 22:13:06.425705 [Byte1]: 31
7792 22:13:06.426278
7793 22:13:06.428935 Set Vref, RX VrefLevel [Byte0]: 32
7794 22:13:06.432707 [Byte1]: 32
7795 22:13:06.433284
7796 22:13:06.435896 Set Vref, RX VrefLevel [Byte0]: 33
7797 22:13:06.438702 [Byte1]: 33
7798 22:13:06.442868
7799 22:13:06.443438 Set Vref, RX VrefLevel [Byte0]: 34
7800 22:13:06.449198 [Byte1]: 34
7801 22:13:06.449770
7802 22:13:06.452371 Set Vref, RX VrefLevel [Byte0]: 35
7803 22:13:06.455640 [Byte1]: 35
7804 22:13:06.456217
7805 22:13:06.458914 Set Vref, RX VrefLevel [Byte0]: 36
7806 22:13:06.462130 [Byte1]: 36
7807 22:13:06.465140
7808 22:13:06.465609 Set Vref, RX VrefLevel [Byte0]: 37
7809 22:13:06.468882 [Byte1]: 37
7810 22:13:06.472939
7811 22:13:06.473409 Set Vref, RX VrefLevel [Byte0]: 38
7812 22:13:06.476227 [Byte1]: 38
7813 22:13:06.480714
7814 22:13:06.481280 Set Vref, RX VrefLevel [Byte0]: 39
7815 22:13:06.483842 [Byte1]: 39
7816 22:13:06.487897
7817 22:13:06.488357 Set Vref, RX VrefLevel [Byte0]: 40
7818 22:13:06.491633 [Byte1]: 40
7819 22:13:06.495904
7820 22:13:06.496478 Set Vref, RX VrefLevel [Byte0]: 41
7821 22:13:06.499401 [Byte1]: 41
7822 22:13:06.504161
7823 22:13:06.504723 Set Vref, RX VrefLevel [Byte0]: 42
7824 22:13:06.506575 [Byte1]: 42
7825 22:13:06.510964
7826 22:13:06.511523 Set Vref, RX VrefLevel [Byte0]: 43
7827 22:13:06.514473 [Byte1]: 43
7828 22:13:06.518728
7829 22:13:06.519288 Set Vref, RX VrefLevel [Byte0]: 44
7830 22:13:06.521448 [Byte1]: 44
7831 22:13:06.526734
7832 22:13:06.527290 Set Vref, RX VrefLevel [Byte0]: 45
7833 22:13:06.529631 [Byte1]: 45
7834 22:13:06.534226
7835 22:13:06.534831 Set Vref, RX VrefLevel [Byte0]: 46
7836 22:13:06.536784 [Byte1]: 46
7837 22:13:06.541371
7838 22:13:06.541925 Set Vref, RX VrefLevel [Byte0]: 47
7839 22:13:06.544434 [Byte1]: 47
7840 22:13:06.549017
7841 22:13:06.549572 Set Vref, RX VrefLevel [Byte0]: 48
7842 22:13:06.551976 [Byte1]: 48
7843 22:13:06.556365
7844 22:13:06.556918 Set Vref, RX VrefLevel [Byte0]: 49
7845 22:13:06.559307 [Byte1]: 49
7846 22:13:06.563916
7847 22:13:06.564519 Set Vref, RX VrefLevel [Byte0]: 50
7848 22:13:06.567029 [Byte1]: 50
7849 22:13:06.571727
7850 22:13:06.572252 Set Vref, RX VrefLevel [Byte0]: 51
7851 22:13:06.574879 [Byte1]: 51
7852 22:13:06.579197
7853 22:13:06.579660 Set Vref, RX VrefLevel [Byte0]: 52
7854 22:13:06.582036 [Byte1]: 52
7855 22:13:06.587105
7856 22:13:06.587564 Set Vref, RX VrefLevel [Byte0]: 53
7857 22:13:06.589900 [Byte1]: 53
7858 22:13:06.594907
7859 22:13:06.595461 Set Vref, RX VrefLevel [Byte0]: 54
7860 22:13:06.597306 [Byte1]: 54
7861 22:13:06.601454
7862 22:13:06.601918 Set Vref, RX VrefLevel [Byte0]: 55
7863 22:13:06.605075 [Byte1]: 55
7864 22:13:06.609473
7865 22:13:06.610038 Set Vref, RX VrefLevel [Byte0]: 56
7866 22:13:06.612657 [Byte1]: 56
7867 22:13:06.617176
7868 22:13:06.617744 Set Vref, RX VrefLevel [Byte0]: 57
7869 22:13:06.620232 [Byte1]: 57
7870 22:13:06.624693
7871 22:13:06.625262 Set Vref, RX VrefLevel [Byte0]: 58
7872 22:13:06.629463 [Byte1]: 58
7873 22:13:06.632034
7874 22:13:06.632600 Set Vref, RX VrefLevel [Byte0]: 59
7875 22:13:06.635404 [Byte1]: 59
7876 22:13:06.640029
7877 22:13:06.640594 Set Vref, RX VrefLevel [Byte0]: 60
7878 22:13:06.642835 [Byte1]: 60
7879 22:13:06.647250
7880 22:13:06.647817 Set Vref, RX VrefLevel [Byte0]: 61
7881 22:13:06.650870 [Byte1]: 61
7882 22:13:06.654941
7883 22:13:06.655518 Set Vref, RX VrefLevel [Byte0]: 62
7884 22:13:06.658099 [Byte1]: 62
7885 22:13:06.662489
7886 22:13:06.662957 Set Vref, RX VrefLevel [Byte0]: 63
7887 22:13:06.665920 [Byte1]: 63
7888 22:13:06.669615
7889 22:13:06.670183 Set Vref, RX VrefLevel [Byte0]: 64
7890 22:13:06.673239 [Byte1]: 64
7891 22:13:06.677297
7892 22:13:06.680757 Set Vref, RX VrefLevel [Byte0]: 65
7893 22:13:06.683715 [Byte1]: 65
7894 22:13:06.684184
7895 22:13:06.686934 Set Vref, RX VrefLevel [Byte0]: 66
7896 22:13:06.690755 [Byte1]: 66
7897 22:13:06.691350
7898 22:13:06.693828 Set Vref, RX VrefLevel [Byte0]: 67
7899 22:13:06.697390 [Byte1]: 67
7900 22:13:06.697962
7901 22:13:06.700270 Set Vref, RX VrefLevel [Byte0]: 68
7902 22:13:06.703397 [Byte1]: 68
7903 22:13:06.707492
7904 22:13:06.707954 Set Vref, RX VrefLevel [Byte0]: 69
7905 22:13:06.711161 [Byte1]: 69
7906 22:13:06.715236
7907 22:13:06.715793 Set Vref, RX VrefLevel [Byte0]: 70
7908 22:13:06.719054 [Byte1]: 70
7909 22:13:06.722916
7910 22:13:06.723479 Set Vref, RX VrefLevel [Byte0]: 71
7911 22:13:06.727580 [Byte1]: 71
7912 22:13:06.730687
7913 22:13:06.731247 Set Vref, RX VrefLevel [Byte0]: 72
7914 22:13:06.733723 [Byte1]: 72
7915 22:13:06.738334
7916 22:13:06.738950 Set Vref, RX VrefLevel [Byte0]: 73
7917 22:13:06.741617 [Byte1]: 73
7918 22:13:06.746209
7919 22:13:06.746820 Set Vref, RX VrefLevel [Byte0]: 74
7920 22:13:06.749316 [Byte1]: 74
7921 22:13:06.753719
7922 22:13:06.754278 Set Vref, RX VrefLevel [Byte0]: 75
7923 22:13:06.756542 [Byte1]: 75
7924 22:13:06.760712
7925 22:13:06.761305 Set Vref, RX VrefLevel [Byte0]: 76
7926 22:13:06.764364 [Byte1]: 76
7927 22:13:06.768085
7928 22:13:06.768556 Set Vref, RX VrefLevel [Byte0]: 77
7929 22:13:06.771766 [Byte1]: 77
7930 22:13:06.775657
7931 22:13:06.776116 Set Vref, RX VrefLevel [Byte0]: 78
7932 22:13:06.779200 [Byte1]: 78
7933 22:13:06.784049
7934 22:13:06.784608 Set Vref, RX VrefLevel [Byte0]: 79
7935 22:13:06.786835 [Byte1]: 79
7936 22:13:06.791376
7937 22:13:06.791959 Set Vref, RX VrefLevel [Byte0]: 80
7938 22:13:06.794432 [Byte1]: 80
7939 22:13:06.798487
7940 22:13:06.799044 Final RX Vref Byte 0 = 61 to rank0
7941 22:13:06.801846 Final RX Vref Byte 1 = 61 to rank0
7942 22:13:06.806015 Final RX Vref Byte 0 = 61 to rank1
7943 22:13:06.808532 Final RX Vref Byte 1 = 61 to rank1==
7944 22:13:06.811830 Dram Type= 6, Freq= 0, CH_0, rank 0
7945 22:13:06.818582 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7946 22:13:06.819150 ==
7947 22:13:06.819521 DQS Delay:
7948 22:13:06.821650 DQS0 = 0, DQS1 = 0
7949 22:13:06.822153 DQM Delay:
7950 22:13:06.822560 DQM0 = 137, DQM1 = 124
7951 22:13:06.825178 DQ Delay:
7952 22:13:06.828299 DQ0 =136, DQ1 =140, DQ2 =132, DQ3 =134
7953 22:13:06.832120 DQ4 =140, DQ5 =126, DQ6 =146, DQ7 =144
7954 22:13:06.834755 DQ8 =116, DQ9 =112, DQ10 =126, DQ11 =118
7955 22:13:06.838035 DQ12 =128, DQ13 =128, DQ14 =136, DQ15 =134
7956 22:13:06.838678
7957 22:13:06.839069
7958 22:13:06.839499
7959 22:13:06.841399 [DramC_TX_OE_Calibration] TA2
7960 22:13:06.844960 Original DQ_B0 (3 6) =30, OEN = 27
7961 22:13:06.848127 Original DQ_B1 (3 6) =30, OEN = 27
7962 22:13:06.851649 24, 0x0, End_B0=24 End_B1=24
7963 22:13:06.854721 25, 0x0, End_B0=25 End_B1=25
7964 22:13:06.855293 26, 0x0, End_B0=26 End_B1=26
7965 22:13:06.858008 27, 0x0, End_B0=27 End_B1=27
7966 22:13:06.861155 28, 0x0, End_B0=28 End_B1=28
7967 22:13:06.864605 29, 0x0, End_B0=29 End_B1=29
7968 22:13:06.865181 30, 0x0, End_B0=30 End_B1=30
7969 22:13:06.867932 31, 0x4141, End_B0=30 End_B1=30
7970 22:13:06.871288 Byte0 end_step=30 best_step=27
7971 22:13:06.875030 Byte1 end_step=30 best_step=27
7972 22:13:06.877661 Byte0 TX OE(2T, 0.5T) = (3, 3)
7973 22:13:06.881446 Byte1 TX OE(2T, 0.5T) = (3, 3)
7974 22:13:06.882023
7975 22:13:06.882643
7976 22:13:06.887491 [DQSOSCAuto] RK0, (LSB)MR18= 0x1d1b, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 395 ps
7977 22:13:06.890901 CH0 RK0: MR19=303, MR18=1D1B
7978 22:13:06.897491 CH0_RK0: MR19=0x303, MR18=0x1D1B, DQSOSC=395, MR23=63, INC=23, DEC=15
7979 22:13:06.898067
7980 22:13:06.901162 ----->DramcWriteLeveling(PI) begin...
7981 22:13:06.901778 ==
7982 22:13:06.903864 Dram Type= 6, Freq= 0, CH_0, rank 1
7983 22:13:06.908161 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7984 22:13:06.908742 ==
7985 22:13:06.910848 Write leveling (Byte 0): 37 => 37
7986 22:13:06.914010 Write leveling (Byte 1): 31 => 31
7987 22:13:06.917558 DramcWriteLeveling(PI) end<-----
7988 22:13:06.918138
7989 22:13:06.918669 ==
7990 22:13:06.920781 Dram Type= 6, Freq= 0, CH_0, rank 1
7991 22:13:06.924369 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7992 22:13:06.927658 ==
7993 22:13:06.928219 [Gating] SW mode calibration
7994 22:13:06.937171 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7995 22:13:06.940765 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7996 22:13:06.944005 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7997 22:13:06.950863 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7998 22:13:06.953961 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7999 22:13:06.957328 1 4 12 | B1->B0 | 2626 3030 | 0 1 | (0 0) (1 1)
8000 22:13:06.963662 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8001 22:13:06.966944 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8002 22:13:06.970741 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8003 22:13:06.978719 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8004 22:13:06.980773 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8005 22:13:06.983887 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8006 22:13:06.990150 1 5 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
8007 22:13:06.993687 1 5 12 | B1->B0 | 3434 2d2d | 1 0 | (1 0) (1 0)
8008 22:13:06.996588 1 5 16 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
8009 22:13:07.004128 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8010 22:13:07.007108 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8011 22:13:07.010036 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8012 22:13:07.017025 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8013 22:13:07.019526 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8014 22:13:07.023020 1 6 8 | B1->B0 | 2323 3030 | 0 1 | (0 0) (0 0)
8015 22:13:07.029694 1 6 12 | B1->B0 | 3434 4646 | 0 0 | (1 1) (0 0)
8016 22:13:07.032836 1 6 16 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
8017 22:13:07.036637 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8018 22:13:07.043279 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8019 22:13:07.046494 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8020 22:13:07.050135 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8021 22:13:07.056706 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8022 22:13:07.060037 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8023 22:13:07.062793 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8024 22:13:07.069785 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8025 22:13:07.073185 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8026 22:13:07.075991 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8027 22:13:07.082758 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8028 22:13:07.086061 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8029 22:13:07.089317 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8030 22:13:07.095932 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8031 22:13:07.098961 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8032 22:13:07.102471 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8033 22:13:07.109002 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8034 22:13:07.112408 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8035 22:13:07.115769 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8036 22:13:07.122002 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8037 22:13:07.125601 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8038 22:13:07.129170 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8039 22:13:07.135380 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8040 22:13:07.139004 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8041 22:13:07.142204 Total UI for P1: 0, mck2ui 16
8042 22:13:07.145531 best dqsien dly found for B0: ( 1, 9, 10)
8043 22:13:07.149254 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8044 22:13:07.151920 Total UI for P1: 0, mck2ui 16
8045 22:13:07.155660 best dqsien dly found for B1: ( 1, 9, 14)
8046 22:13:07.158794 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8047 22:13:07.162955 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8048 22:13:07.163560
8049 22:13:07.168703 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8050 22:13:07.171872 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8051 22:13:07.172437 [Gating] SW calibration Done
8052 22:13:07.174854 ==
8053 22:13:07.178968 Dram Type= 6, Freq= 0, CH_0, rank 1
8054 22:13:07.182400 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8055 22:13:07.182968 ==
8056 22:13:07.183342 RX Vref Scan: 0
8057 22:13:07.183687
8058 22:13:07.185218 RX Vref 0 -> 0, step: 1
8059 22:13:07.185680
8060 22:13:07.188575 RX Delay 0 -> 252, step: 8
8061 22:13:07.191774 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8062 22:13:07.194904 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8063 22:13:07.198253 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8064 22:13:07.205058 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8065 22:13:07.208232 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8066 22:13:07.211612 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8067 22:13:07.214763 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8068 22:13:07.217756 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8069 22:13:07.224387 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8070 22:13:07.227882 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8071 22:13:07.231326 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8072 22:13:07.234685 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8073 22:13:07.240988 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8074 22:13:07.244390 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
8075 22:13:07.247735 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8076 22:13:07.251489 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8077 22:13:07.252067 ==
8078 22:13:07.254612 Dram Type= 6, Freq= 0, CH_0, rank 1
8079 22:13:07.261202 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8080 22:13:07.261777 ==
8081 22:13:07.262153 DQS Delay:
8082 22:13:07.262521 DQS0 = 0, DQS1 = 0
8083 22:13:07.264264 DQM Delay:
8084 22:13:07.264732 DQM0 = 136, DQM1 = 125
8085 22:13:07.268664 DQ Delay:
8086 22:13:07.270749 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =131
8087 22:13:07.274019 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8088 22:13:07.277780 DQ8 =119, DQ9 =111, DQ10 =123, DQ11 =123
8089 22:13:07.281104 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
8090 22:13:07.281676
8091 22:13:07.282048
8092 22:13:07.282445 ==
8093 22:13:07.283915 Dram Type= 6, Freq= 0, CH_0, rank 1
8094 22:13:07.287637 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8095 22:13:07.290793 ==
8096 22:13:07.291363
8097 22:13:07.291736
8098 22:13:07.292081 TX Vref Scan disable
8099 22:13:07.294322 == TX Byte 0 ==
8100 22:13:07.297792 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
8101 22:13:07.301537 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8102 22:13:07.303955 == TX Byte 1 ==
8103 22:13:07.307310 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8104 22:13:07.310404 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8105 22:13:07.314003 ==
8106 22:13:07.316975 Dram Type= 6, Freq= 0, CH_0, rank 1
8107 22:13:07.320601 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8108 22:13:07.321184 ==
8109 22:13:07.334294
8110 22:13:07.338082 TX Vref early break, caculate TX vref
8111 22:13:07.341583 TX Vref=16, minBit 1, minWin=23, winSum=386
8112 22:13:07.344719 TX Vref=18, minBit 2, minWin=23, winSum=391
8113 22:13:07.347758 TX Vref=20, minBit 0, minWin=24, winSum=403
8114 22:13:07.350895 TX Vref=22, minBit 0, minWin=24, winSum=411
8115 22:13:07.354703 TX Vref=24, minBit 2, minWin=25, winSum=423
8116 22:13:07.361078 TX Vref=26, minBit 0, minWin=26, winSum=427
8117 22:13:07.364196 TX Vref=28, minBit 0, minWin=26, winSum=431
8118 22:13:07.367669 TX Vref=30, minBit 7, minWin=25, winSum=425
8119 22:13:07.371313 TX Vref=32, minBit 2, minWin=25, winSum=420
8120 22:13:07.374654 TX Vref=34, minBit 2, minWin=24, winSum=409
8121 22:13:07.377221 TX Vref=36, minBit 0, minWin=24, winSum=400
8122 22:13:07.384831 [TxChooseVref] Worse bit 0, Min win 26, Win sum 431, Final Vref 28
8123 22:13:07.385393
8124 22:13:07.387853 Final TX Range 0 Vref 28
8125 22:13:07.388420
8126 22:13:07.388794 ==
8127 22:13:07.391049 Dram Type= 6, Freq= 0, CH_0, rank 1
8128 22:13:07.394217 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8129 22:13:07.394815 ==
8130 22:13:07.395190
8131 22:13:07.397388
8132 22:13:07.397943 TX Vref Scan disable
8133 22:13:07.403771 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8134 22:13:07.404324 == TX Byte 0 ==
8135 22:13:07.407342 u2DelayCellOfst[0]=10 cells (3 PI)
8136 22:13:07.410441 u2DelayCellOfst[1]=16 cells (5 PI)
8137 22:13:07.414319 u2DelayCellOfst[2]=10 cells (3 PI)
8138 22:13:07.416803 u2DelayCellOfst[3]=10 cells (3 PI)
8139 22:13:07.420780 u2DelayCellOfst[4]=6 cells (2 PI)
8140 22:13:07.423759 u2DelayCellOfst[5]=0 cells (0 PI)
8141 22:13:07.427437 u2DelayCellOfst[6]=16 cells (5 PI)
8142 22:13:07.430217 u2DelayCellOfst[7]=16 cells (5 PI)
8143 22:13:07.433549 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8144 22:13:07.436860 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8145 22:13:07.439986 == TX Byte 1 ==
8146 22:13:07.443692 u2DelayCellOfst[8]=3 cells (1 PI)
8147 22:13:07.446677 u2DelayCellOfst[9]=0 cells (0 PI)
8148 22:13:07.450421 u2DelayCellOfst[10]=6 cells (2 PI)
8149 22:13:07.453653 u2DelayCellOfst[11]=3 cells (1 PI)
8150 22:13:07.456966 u2DelayCellOfst[12]=13 cells (4 PI)
8151 22:13:07.457532 u2DelayCellOfst[13]=13 cells (4 PI)
8152 22:13:07.460165 u2DelayCellOfst[14]=16 cells (5 PI)
8153 22:13:07.463466 u2DelayCellOfst[15]=13 cells (4 PI)
8154 22:13:07.470504 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8155 22:13:07.473181 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8156 22:13:07.473759 DramC Write-DBI on
8157 22:13:07.476697 ==
8158 22:13:07.480421 Dram Type= 6, Freq= 0, CH_0, rank 1
8159 22:13:07.483153 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8160 22:13:07.483624 ==
8161 22:13:07.483990
8162 22:13:07.484328
8163 22:13:07.486395 TX Vref Scan disable
8164 22:13:07.486962 == TX Byte 0 ==
8165 22:13:07.493144 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8166 22:13:07.493710 == TX Byte 1 ==
8167 22:13:07.496389 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8168 22:13:07.499572 DramC Write-DBI off
8169 22:13:07.500133
8170 22:13:07.500500 [DATLAT]
8171 22:13:07.503279 Freq=1600, CH0 RK1
8172 22:13:07.503881
8173 22:13:07.504250 DATLAT Default: 0xf
8174 22:13:07.506507 0, 0xFFFF, sum = 0
8175 22:13:07.507081 1, 0xFFFF, sum = 0
8176 22:13:07.509583 2, 0xFFFF, sum = 0
8177 22:13:07.510151 3, 0xFFFF, sum = 0
8178 22:13:07.512852 4, 0xFFFF, sum = 0
8179 22:13:07.516188 5, 0xFFFF, sum = 0
8180 22:13:07.516753 6, 0xFFFF, sum = 0
8181 22:13:07.519291 7, 0xFFFF, sum = 0
8182 22:13:07.519857 8, 0xFFFF, sum = 0
8183 22:13:07.522805 9, 0xFFFF, sum = 0
8184 22:13:07.523389 10, 0xFFFF, sum = 0
8185 22:13:07.525790 11, 0xFFFF, sum = 0
8186 22:13:07.526261 12, 0xFFFF, sum = 0
8187 22:13:07.529841 13, 0xFFFF, sum = 0
8188 22:13:07.530470 14, 0x0, sum = 1
8189 22:13:07.532394 15, 0x0, sum = 2
8190 22:13:07.532864 16, 0x0, sum = 3
8191 22:13:07.537068 17, 0x0, sum = 4
8192 22:13:07.537833 best_step = 15
8193 22:13:07.538222
8194 22:13:07.538640 ==
8195 22:13:07.539582 Dram Type= 6, Freq= 0, CH_0, rank 1
8196 22:13:07.542396 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8197 22:13:07.545999 ==
8198 22:13:07.546601 RX Vref Scan: 0
8199 22:13:07.546980
8200 22:13:07.548895 RX Vref 0 -> 0, step: 1
8201 22:13:07.549356
8202 22:13:07.552485 RX Delay 11 -> 252, step: 4
8203 22:13:07.555708 iDelay=191, Bit 0, Center 132 (83 ~ 182) 100
8204 22:13:07.559291 iDelay=191, Bit 1, Center 136 (87 ~ 186) 100
8205 22:13:07.561929 iDelay=191, Bit 2, Center 130 (83 ~ 178) 96
8206 22:13:07.569117 iDelay=191, Bit 3, Center 130 (83 ~ 178) 96
8207 22:13:07.572505 iDelay=191, Bit 4, Center 136 (87 ~ 186) 100
8208 22:13:07.575296 iDelay=191, Bit 5, Center 124 (75 ~ 174) 100
8209 22:13:07.578544 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8210 22:13:07.583103 iDelay=191, Bit 7, Center 138 (87 ~ 190) 104
8211 22:13:07.588969 iDelay=191, Bit 8, Center 116 (67 ~ 166) 100
8212 22:13:07.592077 iDelay=191, Bit 9, Center 112 (59 ~ 166) 108
8213 22:13:07.595312 iDelay=191, Bit 10, Center 124 (75 ~ 174) 100
8214 22:13:07.599303 iDelay=191, Bit 11, Center 120 (71 ~ 170) 100
8215 22:13:07.602126 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8216 22:13:07.608815 iDelay=191, Bit 13, Center 128 (79 ~ 178) 100
8217 22:13:07.611431 iDelay=191, Bit 14, Center 132 (79 ~ 186) 108
8218 22:13:07.615074 iDelay=191, Bit 15, Center 128 (75 ~ 182) 108
8219 22:13:07.615643 ==
8220 22:13:07.618200 Dram Type= 6, Freq= 0, CH_0, rank 1
8221 22:13:07.624939 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8222 22:13:07.625512 ==
8223 22:13:07.625887 DQS Delay:
8224 22:13:07.626232 DQS0 = 0, DQS1 = 0
8225 22:13:07.628035 DQM Delay:
8226 22:13:07.628496 DQM0 = 133, DQM1 = 123
8227 22:13:07.631105 DQ Delay:
8228 22:13:07.634763 DQ0 =132, DQ1 =136, DQ2 =130, DQ3 =130
8229 22:13:07.638092 DQ4 =136, DQ5 =124, DQ6 =140, DQ7 =138
8230 22:13:07.641331 DQ8 =116, DQ9 =112, DQ10 =124, DQ11 =120
8231 22:13:07.644786 DQ12 =128, DQ13 =128, DQ14 =132, DQ15 =128
8232 22:13:07.645355
8233 22:13:07.645723
8234 22:13:07.646065
8235 22:13:07.647913 [DramC_TX_OE_Calibration] TA2
8236 22:13:07.651189 Original DQ_B0 (3 6) =30, OEN = 27
8237 22:13:07.654423 Original DQ_B1 (3 6) =30, OEN = 27
8238 22:13:07.657992 24, 0x0, End_B0=24 End_B1=24
8239 22:13:07.658502 25, 0x0, End_B0=25 End_B1=25
8240 22:13:07.661364 26, 0x0, End_B0=26 End_B1=26
8241 22:13:07.664193 27, 0x0, End_B0=27 End_B1=27
8242 22:13:07.667671 28, 0x0, End_B0=28 End_B1=28
8243 22:13:07.670796 29, 0x0, End_B0=29 End_B1=29
8244 22:13:07.671272 30, 0x0, End_B0=30 End_B1=30
8245 22:13:07.674208 31, 0x4141, End_B0=30 End_B1=30
8246 22:13:07.677425 Byte0 end_step=30 best_step=27
8247 22:13:07.680910 Byte1 end_step=30 best_step=27
8248 22:13:07.684413 Byte0 TX OE(2T, 0.5T) = (3, 3)
8249 22:13:07.687359 Byte1 TX OE(2T, 0.5T) = (3, 3)
8250 22:13:07.687924
8251 22:13:07.688295
8252 22:13:07.694090 [DQSOSCAuto] RK1, (LSB)MR18= 0x210e, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 393 ps
8253 22:13:07.697991 CH0 RK1: MR19=303, MR18=210E
8254 22:13:07.704195 CH0_RK1: MR19=0x303, MR18=0x210E, DQSOSC=393, MR23=63, INC=23, DEC=15
8255 22:13:07.707966 [RxdqsGatingPostProcess] freq 1600
8256 22:13:07.710923 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8257 22:13:07.714132 best DQS0 dly(2T, 0.5T) = (1, 1)
8258 22:13:07.717583 best DQS1 dly(2T, 0.5T) = (1, 1)
8259 22:13:07.721363 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8260 22:13:07.723827 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8261 22:13:07.727322 best DQS0 dly(2T, 0.5T) = (1, 1)
8262 22:13:07.730660 best DQS1 dly(2T, 0.5T) = (1, 1)
8263 22:13:07.733830 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8264 22:13:07.736880 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8265 22:13:07.740658 Pre-setting of DQS Precalculation
8266 22:13:07.743798 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8267 22:13:07.744375 ==
8268 22:13:07.747706 Dram Type= 6, Freq= 0, CH_1, rank 0
8269 22:13:07.751089 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8270 22:13:07.753669 ==
8271 22:13:07.757701 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8272 22:13:07.760236 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8273 22:13:07.767125 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8274 22:13:07.773487 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8275 22:13:07.780882 [CA 0] Center 42 (12~72) winsize 61
8276 22:13:07.784347 [CA 1] Center 42 (12~72) winsize 61
8277 22:13:07.787140 [CA 2] Center 38 (9~68) winsize 60
8278 22:13:07.790488 [CA 3] Center 37 (8~67) winsize 60
8279 22:13:07.794115 [CA 4] Center 37 (8~67) winsize 60
8280 22:13:07.797270 [CA 5] Center 37 (7~67) winsize 61
8281 22:13:07.797831
8282 22:13:07.801197 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8283 22:13:07.801757
8284 22:13:07.807030 [CATrainingPosCal] consider 1 rank data
8285 22:13:07.807599 u2DelayCellTimex100 = 290/100 ps
8286 22:13:07.814134 CA0 delay=42 (12~72),Diff = 5 PI (16 cell)
8287 22:13:07.817001 CA1 delay=42 (12~72),Diff = 5 PI (16 cell)
8288 22:13:07.820386 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8289 22:13:07.823293 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8290 22:13:07.826995 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8291 22:13:07.830509 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
8292 22:13:07.831071
8293 22:13:07.833310 CA PerBit enable=1, Macro0, CA PI delay=37
8294 22:13:07.833763
8295 22:13:07.836460 [CBTSetCACLKResult] CA Dly = 37
8296 22:13:07.839918 CS Dly: 8 (0~39)
8297 22:13:07.842956 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8298 22:13:07.846458 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8299 22:13:07.846912 ==
8300 22:13:07.849894 Dram Type= 6, Freq= 0, CH_1, rank 1
8301 22:13:07.856704 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8302 22:13:07.857256 ==
8303 22:13:07.859668 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8304 22:13:07.866465 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8305 22:13:07.870555 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8306 22:13:07.876851 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8307 22:13:07.883883 [CA 0] Center 41 (12~71) winsize 60
8308 22:13:07.886867 [CA 1] Center 41 (12~71) winsize 60
8309 22:13:07.890723 [CA 2] Center 38 (9~67) winsize 59
8310 22:13:07.894166 [CA 3] Center 37 (8~67) winsize 60
8311 22:13:07.897427 [CA 4] Center 37 (8~67) winsize 60
8312 22:13:07.900366 [CA 5] Center 37 (7~67) winsize 61
8313 22:13:07.900923
8314 22:13:07.903694 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8315 22:13:07.904152
8316 22:13:07.910956 [CATrainingPosCal] consider 2 rank data
8317 22:13:07.911519 u2DelayCellTimex100 = 290/100 ps
8318 22:13:07.916965 CA0 delay=41 (12~71),Diff = 4 PI (13 cell)
8319 22:13:07.920102 CA1 delay=41 (12~71),Diff = 4 PI (13 cell)
8320 22:13:07.923561 CA2 delay=38 (9~67),Diff = 1 PI (3 cell)
8321 22:13:07.927216 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8322 22:13:07.930722 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8323 22:13:07.933274 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
8324 22:13:07.933836
8325 22:13:07.936989 CA PerBit enable=1, Macro0, CA PI delay=37
8326 22:13:07.937549
8327 22:13:07.940409 [CBTSetCACLKResult] CA Dly = 37
8328 22:13:07.943215 CS Dly: 9 (0~42)
8329 22:13:07.946903 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8330 22:13:07.949812 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8331 22:13:07.950393
8332 22:13:07.953566 ----->DramcWriteLeveling(PI) begin...
8333 22:13:07.954129 ==
8334 22:13:07.956766 Dram Type= 6, Freq= 0, CH_1, rank 0
8335 22:13:07.962999 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8336 22:13:07.963570 ==
8337 22:13:07.966217 Write leveling (Byte 0): 25 => 25
8338 22:13:07.969484 Write leveling (Byte 1): 27 => 27
8339 22:13:07.969941 DramcWriteLeveling(PI) end<-----
8340 22:13:07.970303
8341 22:13:07.973365 ==
8342 22:13:07.976194 Dram Type= 6, Freq= 0, CH_1, rank 0
8343 22:13:07.979363 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8344 22:13:07.979824 ==
8345 22:13:07.983492 [Gating] SW mode calibration
8346 22:13:07.990049 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8347 22:13:07.992797 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8348 22:13:07.999475 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8349 22:13:08.002709 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
8350 22:13:08.005748 1 4 8 | B1->B0 | 2b2b 2f2f | 0 0 | (0 0) (0 0)
8351 22:13:08.012406 1 4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8352 22:13:08.016145 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8353 22:13:08.019032 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8354 22:13:08.025704 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8355 22:13:08.028989 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8356 22:13:08.032403 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8357 22:13:08.038958 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8358 22:13:08.042960 1 5 8 | B1->B0 | 2b2b 2929 | 1 1 | (1 1) (1 0)
8359 22:13:08.045978 1 5 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8360 22:13:08.053097 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8361 22:13:08.055640 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8362 22:13:08.059346 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8363 22:13:08.065358 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8364 22:13:08.069106 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8365 22:13:08.072478 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8366 22:13:08.078205 1 6 8 | B1->B0 | 3c3c 4141 | 0 0 | (0 0) (0 0)
8367 22:13:08.082153 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8368 22:13:08.085722 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8369 22:13:08.092520 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8370 22:13:08.095460 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8371 22:13:08.098161 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8372 22:13:08.105299 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8373 22:13:08.108406 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8374 22:13:08.111709 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8375 22:13:08.118479 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8376 22:13:08.121887 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8377 22:13:08.124731 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8378 22:13:08.131685 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8379 22:13:08.134775 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8380 22:13:08.138393 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8381 22:13:08.144650 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8382 22:13:08.148166 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8383 22:13:08.151207 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8384 22:13:08.158310 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8385 22:13:08.161178 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8386 22:13:08.164750 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8387 22:13:08.170935 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8388 22:13:08.174101 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8389 22:13:08.177365 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8390 22:13:08.184136 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8391 22:13:08.187366 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8392 22:13:08.190659 Total UI for P1: 0, mck2ui 16
8393 22:13:08.194143 best dqsien dly found for B0: ( 1, 9, 6)
8394 22:13:08.197688 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8395 22:13:08.201397 Total UI for P1: 0, mck2ui 16
8396 22:13:08.203930 best dqsien dly found for B1: ( 1, 9, 10)
8397 22:13:08.207650 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8398 22:13:08.211032 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8399 22:13:08.211612
8400 22:13:08.217284 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8401 22:13:08.220881 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8402 22:13:08.221457 [Gating] SW calibration Done
8403 22:13:08.224050 ==
8404 22:13:08.227827 Dram Type= 6, Freq= 0, CH_1, rank 0
8405 22:13:08.231025 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8406 22:13:08.231606 ==
8407 22:13:08.232095 RX Vref Scan: 0
8408 22:13:08.232549
8409 22:13:08.233646 RX Vref 0 -> 0, step: 1
8410 22:13:08.234124
8411 22:13:08.237437 RX Delay 0 -> 252, step: 8
8412 22:13:08.240428 iDelay=200, Bit 0, Center 139 (96 ~ 183) 88
8413 22:13:08.243690 iDelay=200, Bit 1, Center 135 (88 ~ 183) 96
8414 22:13:08.247185 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8415 22:13:08.253933 iDelay=200, Bit 3, Center 139 (88 ~ 191) 104
8416 22:13:08.257506 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8417 22:13:08.261161 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8418 22:13:08.263821 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8419 22:13:08.267113 iDelay=200, Bit 7, Center 135 (88 ~ 183) 96
8420 22:13:08.273659 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8421 22:13:08.276541 iDelay=200, Bit 9, Center 119 (72 ~ 167) 96
8422 22:13:08.280260 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8423 22:13:08.284095 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8424 22:13:08.286529 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8425 22:13:08.293152 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8426 22:13:08.296597 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8427 22:13:08.300185 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8428 22:13:08.300764 ==
8429 22:13:08.303293 Dram Type= 6, Freq= 0, CH_1, rank 0
8430 22:13:08.306537 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8431 22:13:08.307023 ==
8432 22:13:08.310008 DQS Delay:
8433 22:13:08.310616 DQS0 = 0, DQS1 = 0
8434 22:13:08.312916 DQM Delay:
8435 22:13:08.313380 DQM0 = 137, DQM1 = 131
8436 22:13:08.316536 DQ Delay:
8437 22:13:08.319769 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =139
8438 22:13:08.323543 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8439 22:13:08.326382 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =127
8440 22:13:08.330333 DQ12 =139, DQ13 =135, DQ14 =139, DQ15 =139
8441 22:13:08.330933
8442 22:13:08.331303
8443 22:13:08.331642 ==
8444 22:13:08.333354 Dram Type= 6, Freq= 0, CH_1, rank 0
8445 22:13:08.336760 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8446 22:13:08.337323 ==
8447 22:13:08.337695
8448 22:13:08.338039
8449 22:13:08.339809 TX Vref Scan disable
8450 22:13:08.343005 == TX Byte 0 ==
8451 22:13:08.346547 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8452 22:13:08.349581 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8453 22:13:08.353279 == TX Byte 1 ==
8454 22:13:08.356056 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8455 22:13:08.359359 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8456 22:13:08.359927 ==
8457 22:13:08.362912 Dram Type= 6, Freq= 0, CH_1, rank 0
8458 22:13:08.369324 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8459 22:13:08.370031 ==
8460 22:13:08.380558
8461 22:13:08.383770 TX Vref early break, caculate TX vref
8462 22:13:08.387319 TX Vref=16, minBit 10, minWin=21, winSum=369
8463 22:13:08.390613 TX Vref=18, minBit 15, minWin=22, winSum=383
8464 22:13:08.393919 TX Vref=20, minBit 14, minWin=23, winSum=395
8465 22:13:08.397270 TX Vref=22, minBit 9, minWin=24, winSum=402
8466 22:13:08.403796 TX Vref=24, minBit 10, minWin=24, winSum=413
8467 22:13:08.407036 TX Vref=26, minBit 0, minWin=25, winSum=420
8468 22:13:08.410139 TX Vref=28, minBit 14, minWin=25, winSum=425
8469 22:13:08.413741 TX Vref=30, minBit 14, minWin=24, winSum=416
8470 22:13:08.416909 TX Vref=32, minBit 13, minWin=24, winSum=410
8471 22:13:08.423323 TX Vref=34, minBit 6, minWin=24, winSum=398
8472 22:13:08.427193 [TxChooseVref] Worse bit 14, Min win 25, Win sum 425, Final Vref 28
8473 22:13:08.427755
8474 22:13:08.430084 Final TX Range 0 Vref 28
8475 22:13:08.430700
8476 22:13:08.431072 ==
8477 22:13:08.434612 Dram Type= 6, Freq= 0, CH_1, rank 0
8478 22:13:08.438025 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8479 22:13:08.438633 ==
8480 22:13:08.439690
8481 22:13:08.440145
8482 22:13:08.440505 TX Vref Scan disable
8483 22:13:08.446973 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8484 22:13:08.447540 == TX Byte 0 ==
8485 22:13:08.450029 u2DelayCellOfst[0]=16 cells (5 PI)
8486 22:13:08.453497 u2DelayCellOfst[1]=10 cells (3 PI)
8487 22:13:08.457679 u2DelayCellOfst[2]=0 cells (0 PI)
8488 22:13:08.460242 u2DelayCellOfst[3]=3 cells (1 PI)
8489 22:13:08.463688 u2DelayCellOfst[4]=6 cells (2 PI)
8490 22:13:08.466515 u2DelayCellOfst[5]=16 cells (5 PI)
8491 22:13:08.469979 u2DelayCellOfst[6]=16 cells (5 PI)
8492 22:13:08.473391 u2DelayCellOfst[7]=3 cells (1 PI)
8493 22:13:08.476462 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8494 22:13:08.479891 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8495 22:13:08.483044 == TX Byte 1 ==
8496 22:13:08.486751 u2DelayCellOfst[8]=0 cells (0 PI)
8497 22:13:08.489925 u2DelayCellOfst[9]=3 cells (1 PI)
8498 22:13:08.492895 u2DelayCellOfst[10]=10 cells (3 PI)
8499 22:13:08.493460 u2DelayCellOfst[11]=3 cells (1 PI)
8500 22:13:08.496416 u2DelayCellOfst[12]=13 cells (4 PI)
8501 22:13:08.499999 u2DelayCellOfst[13]=20 cells (6 PI)
8502 22:13:08.503037 u2DelayCellOfst[14]=20 cells (6 PI)
8503 22:13:08.506457 u2DelayCellOfst[15]=16 cells (5 PI)
8504 22:13:08.513132 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8505 22:13:08.516483 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8506 22:13:08.517144 DramC Write-DBI on
8507 22:13:08.520116 ==
8508 22:13:08.522746 Dram Type= 6, Freq= 0, CH_1, rank 0
8509 22:13:08.526181 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8510 22:13:08.526670 ==
8511 22:13:08.527043
8512 22:13:08.527387
8513 22:13:08.529664 TX Vref Scan disable
8514 22:13:08.530237 == TX Byte 0 ==
8515 22:13:08.536328 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8516 22:13:08.536921 == TX Byte 1 ==
8517 22:13:08.539568 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8518 22:13:08.542522 DramC Write-DBI off
8519 22:13:08.543095
8520 22:13:08.543472 [DATLAT]
8521 22:13:08.546258 Freq=1600, CH1 RK0
8522 22:13:08.546877
8523 22:13:08.547254 DATLAT Default: 0xf
8524 22:13:08.549708 0, 0xFFFF, sum = 0
8525 22:13:08.550291 1, 0xFFFF, sum = 0
8526 22:13:08.552657 2, 0xFFFF, sum = 0
8527 22:13:08.553241 3, 0xFFFF, sum = 0
8528 22:13:08.556446 4, 0xFFFF, sum = 0
8529 22:13:08.557029 5, 0xFFFF, sum = 0
8530 22:13:08.559253 6, 0xFFFF, sum = 0
8531 22:13:08.562467 7, 0xFFFF, sum = 0
8532 22:13:08.563051 8, 0xFFFF, sum = 0
8533 22:13:08.565894 9, 0xFFFF, sum = 0
8534 22:13:08.566514 10, 0xFFFF, sum = 0
8535 22:13:08.569099 11, 0xFFFF, sum = 0
8536 22:13:08.569684 12, 0xFFFF, sum = 0
8537 22:13:08.571852 13, 0xFFFF, sum = 0
8538 22:13:08.572333 14, 0x0, sum = 1
8539 22:13:08.575639 15, 0x0, sum = 2
8540 22:13:08.576221 16, 0x0, sum = 3
8541 22:13:08.578808 17, 0x0, sum = 4
8542 22:13:08.579287 best_step = 15
8543 22:13:08.579736
8544 22:13:08.580106 ==
8545 22:13:08.581991 Dram Type= 6, Freq= 0, CH_1, rank 0
8546 22:13:08.585360 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8547 22:13:08.588634 ==
8548 22:13:08.589195 RX Vref Scan: 1
8549 22:13:08.589567
8550 22:13:08.592065 Set Vref Range= 24 -> 127
8551 22:13:08.592532
8552 22:13:08.594940 RX Vref 24 -> 127, step: 1
8553 22:13:08.595410
8554 22:13:08.595780 RX Delay 19 -> 252, step: 4
8555 22:13:08.596128
8556 22:13:08.598423 Set Vref, RX VrefLevel [Byte0]: 24
8557 22:13:08.601738 [Byte1]: 24
8558 22:13:08.605478
8559 22:13:08.605947 Set Vref, RX VrefLevel [Byte0]: 25
8560 22:13:08.608682 [Byte1]: 25
8561 22:13:08.613582
8562 22:13:08.614142 Set Vref, RX VrefLevel [Byte0]: 26
8563 22:13:08.616654 [Byte1]: 26
8564 22:13:08.621618
8565 22:13:08.622175 Set Vref, RX VrefLevel [Byte0]: 27
8566 22:13:08.624145 [Byte1]: 27
8567 22:13:08.629151
8568 22:13:08.629710 Set Vref, RX VrefLevel [Byte0]: 28
8569 22:13:08.631607 [Byte1]: 28
8570 22:13:08.635950
8571 22:13:08.636506 Set Vref, RX VrefLevel [Byte0]: 29
8572 22:13:08.639175 [Byte1]: 29
8573 22:13:08.643418
8574 22:13:08.644004 Set Vref, RX VrefLevel [Byte0]: 30
8575 22:13:08.647297 [Byte1]: 30
8576 22:13:08.651312
8577 22:13:08.651867 Set Vref, RX VrefLevel [Byte0]: 31
8578 22:13:08.655021 [Byte1]: 31
8579 22:13:08.658861
8580 22:13:08.659420 Set Vref, RX VrefLevel [Byte0]: 32
8581 22:13:08.662153 [Byte1]: 32
8582 22:13:08.666167
8583 22:13:08.666768 Set Vref, RX VrefLevel [Byte0]: 33
8584 22:13:08.669768 [Byte1]: 33
8585 22:13:08.673528
8586 22:13:08.673995 Set Vref, RX VrefLevel [Byte0]: 34
8587 22:13:08.677459 [Byte1]: 34
8588 22:13:08.681775
8589 22:13:08.682335 Set Vref, RX VrefLevel [Byte0]: 35
8590 22:13:08.685655 [Byte1]: 35
8591 22:13:08.689354
8592 22:13:08.689923 Set Vref, RX VrefLevel [Byte0]: 36
8593 22:13:08.692423 [Byte1]: 36
8594 22:13:08.696873
8595 22:13:08.697429 Set Vref, RX VrefLevel [Byte0]: 37
8596 22:13:08.699683 [Byte1]: 37
8597 22:13:08.704461
8598 22:13:08.705017 Set Vref, RX VrefLevel [Byte0]: 38
8599 22:13:08.707824 [Byte1]: 38
8600 22:13:08.711527
8601 22:13:08.712094 Set Vref, RX VrefLevel [Byte0]: 39
8602 22:13:08.715083 [Byte1]: 39
8603 22:13:08.719186
8604 22:13:08.719746 Set Vref, RX VrefLevel [Byte0]: 40
8605 22:13:08.722403 [Byte1]: 40
8606 22:13:08.727798
8607 22:13:08.730085 Set Vref, RX VrefLevel [Byte0]: 41
8608 22:13:08.733274 [Byte1]: 41
8609 22:13:08.733834
8610 22:13:08.736531 Set Vref, RX VrefLevel [Byte0]: 42
8611 22:13:08.740026 [Byte1]: 42
8612 22:13:08.740596
8613 22:13:08.743196 Set Vref, RX VrefLevel [Byte0]: 43
8614 22:13:08.746512 [Byte1]: 43
8615 22:13:08.747078
8616 22:13:08.749754 Set Vref, RX VrefLevel [Byte0]: 44
8617 22:13:08.753328 [Byte1]: 44
8618 22:13:08.757303
8619 22:13:08.757862 Set Vref, RX VrefLevel [Byte0]: 45
8620 22:13:08.760915 [Byte1]: 45
8621 22:13:08.764592
8622 22:13:08.765152 Set Vref, RX VrefLevel [Byte0]: 46
8623 22:13:08.768201 [Byte1]: 46
8624 22:13:08.772185
8625 22:13:08.772780 Set Vref, RX VrefLevel [Byte0]: 47
8626 22:13:08.775661 [Byte1]: 47
8627 22:13:08.780153
8628 22:13:08.780612 Set Vref, RX VrefLevel [Byte0]: 48
8629 22:13:08.783166 [Byte1]: 48
8630 22:13:08.787911
8631 22:13:08.788471 Set Vref, RX VrefLevel [Byte0]: 49
8632 22:13:08.790498 [Byte1]: 49
8633 22:13:08.795281
8634 22:13:08.795841 Set Vref, RX VrefLevel [Byte0]: 50
8635 22:13:08.798400 [Byte1]: 50
8636 22:13:08.803129
8637 22:13:08.803689 Set Vref, RX VrefLevel [Byte0]: 51
8638 22:13:08.805895 [Byte1]: 51
8639 22:13:08.810042
8640 22:13:08.810644 Set Vref, RX VrefLevel [Byte0]: 52
8641 22:13:08.813477 [Byte1]: 52
8642 22:13:08.817575
8643 22:13:08.818132 Set Vref, RX VrefLevel [Byte0]: 53
8644 22:13:08.821214 [Byte1]: 53
8645 22:13:08.825139
8646 22:13:08.825615 Set Vref, RX VrefLevel [Byte0]: 54
8647 22:13:08.828654 [Byte1]: 54
8648 22:13:08.833326
8649 22:13:08.833889 Set Vref, RX VrefLevel [Byte0]: 55
8650 22:13:08.836034 [Byte1]: 55
8651 22:13:08.840302
8652 22:13:08.840773 Set Vref, RX VrefLevel [Byte0]: 56
8653 22:13:08.843537 [Byte1]: 56
8654 22:13:08.847937
8655 22:13:08.848506 Set Vref, RX VrefLevel [Byte0]: 57
8656 22:13:08.851240 [Byte1]: 57
8657 22:13:08.855545
8658 22:13:08.856121 Set Vref, RX VrefLevel [Byte0]: 58
8659 22:13:08.859385 [Byte1]: 58
8660 22:13:08.863323
8661 22:13:08.863882 Set Vref, RX VrefLevel [Byte0]: 59
8662 22:13:08.866323 [Byte1]: 59
8663 22:13:08.870988
8664 22:13:08.871547 Set Vref, RX VrefLevel [Byte0]: 60
8665 22:13:08.873702 [Byte1]: 60
8666 22:13:08.878105
8667 22:13:08.878739 Set Vref, RX VrefLevel [Byte0]: 61
8668 22:13:08.881884 [Byte1]: 61
8669 22:13:08.886153
8670 22:13:08.886751 Set Vref, RX VrefLevel [Byte0]: 62
8671 22:13:08.889526 [Byte1]: 62
8672 22:13:08.893592
8673 22:13:08.894154 Set Vref, RX VrefLevel [Byte0]: 63
8674 22:13:08.897147 [Byte1]: 63
8675 22:13:08.901304
8676 22:13:08.901864 Set Vref, RX VrefLevel [Byte0]: 64
8677 22:13:08.904279 [Byte1]: 64
8678 22:13:08.908628
8679 22:13:08.909188 Set Vref, RX VrefLevel [Byte0]: 65
8680 22:13:08.912315 [Byte1]: 65
8681 22:13:08.915909
8682 22:13:08.916376 Set Vref, RX VrefLevel [Byte0]: 66
8683 22:13:08.919132 [Byte1]: 66
8684 22:13:08.923473
8685 22:13:08.923941 Set Vref, RX VrefLevel [Byte0]: 67
8686 22:13:08.926907 [Byte1]: 67
8687 22:13:08.931283
8688 22:13:08.931845 Set Vref, RX VrefLevel [Byte0]: 68
8689 22:13:08.934689 [Byte1]: 68
8690 22:13:08.938999
8691 22:13:08.939553 Set Vref, RX VrefLevel [Byte0]: 69
8692 22:13:08.942339 [Byte1]: 69
8693 22:13:08.946591
8694 22:13:08.947159 Set Vref, RX VrefLevel [Byte0]: 70
8695 22:13:08.949624 [Byte1]: 70
8696 22:13:08.954230
8697 22:13:08.954834 Set Vref, RX VrefLevel [Byte0]: 71
8698 22:13:08.957662 [Byte1]: 71
8699 22:13:08.961832
8700 22:13:08.962420 Set Vref, RX VrefLevel [Byte0]: 72
8701 22:13:08.964793 [Byte1]: 72
8702 22:13:08.969244
8703 22:13:08.969806 Set Vref, RX VrefLevel [Byte0]: 73
8704 22:13:08.972689 [Byte1]: 73
8705 22:13:08.976744
8706 22:13:08.977307 Set Vref, RX VrefLevel [Byte0]: 74
8707 22:13:08.980299 [Byte1]: 74
8708 22:13:08.984358
8709 22:13:08.984921 Set Vref, RX VrefLevel [Byte0]: 75
8710 22:13:08.987972 [Byte1]: 75
8711 22:13:08.991902
8712 22:13:08.992463 Final RX Vref Byte 0 = 59 to rank0
8713 22:13:08.995262 Final RX Vref Byte 1 = 61 to rank0
8714 22:13:08.998765 Final RX Vref Byte 0 = 59 to rank1
8715 22:13:09.001941 Final RX Vref Byte 1 = 61 to rank1==
8716 22:13:09.005841 Dram Type= 6, Freq= 0, CH_1, rank 0
8717 22:13:09.011675 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8718 22:13:09.012243 ==
8719 22:13:09.012618 DQS Delay:
8720 22:13:09.015150 DQS0 = 0, DQS1 = 0
8721 22:13:09.015618 DQM Delay:
8722 22:13:09.015987 DQM0 = 134, DQM1 = 130
8723 22:13:09.018163 DQ Delay:
8724 22:13:09.021786 DQ0 =138, DQ1 =128, DQ2 =122, DQ3 =132
8725 22:13:09.025308 DQ4 =130, DQ5 =144, DQ6 =146, DQ7 =132
8726 22:13:09.028023 DQ8 =116, DQ9 =120, DQ10 =132, DQ11 =124
8727 22:13:09.031455 DQ12 =140, DQ13 =134, DQ14 =136, DQ15 =138
8728 22:13:09.032022
8729 22:13:09.032396
8730 22:13:09.032739
8731 22:13:09.034599 [DramC_TX_OE_Calibration] TA2
8732 22:13:09.038181 Original DQ_B0 (3 6) =30, OEN = 27
8733 22:13:09.041936 Original DQ_B1 (3 6) =30, OEN = 27
8734 22:13:09.044869 24, 0x0, End_B0=24 End_B1=24
8735 22:13:09.045380 25, 0x0, End_B0=25 End_B1=25
8736 22:13:09.048313 26, 0x0, End_B0=26 End_B1=26
8737 22:13:09.051284 27, 0x0, End_B0=27 End_B1=27
8738 22:13:09.054539 28, 0x0, End_B0=28 End_B1=28
8739 22:13:09.057841 29, 0x0, End_B0=29 End_B1=29
8740 22:13:09.058444 30, 0x0, End_B0=30 End_B1=30
8741 22:13:09.061485 31, 0x4141, End_B0=30 End_B1=30
8742 22:13:09.064900 Byte0 end_step=30 best_step=27
8743 22:13:09.067765 Byte1 end_step=30 best_step=27
8744 22:13:09.071267 Byte0 TX OE(2T, 0.5T) = (3, 3)
8745 22:13:09.074799 Byte1 TX OE(2T, 0.5T) = (3, 3)
8746 22:13:09.075373
8747 22:13:09.075853
8748 22:13:09.081185 [DQSOSCAuto] RK0, (LSB)MR18= 0x1725, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
8749 22:13:09.084601 CH1 RK0: MR19=303, MR18=1725
8750 22:13:09.091186 CH1_RK0: MR19=0x303, MR18=0x1725, DQSOSC=391, MR23=63, INC=24, DEC=16
8751 22:13:09.091761
8752 22:13:09.094921 ----->DramcWriteLeveling(PI) begin...
8753 22:13:09.095499 ==
8754 22:13:09.097613 Dram Type= 6, Freq= 0, CH_1, rank 1
8755 22:13:09.101208 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8756 22:13:09.101780 ==
8757 22:13:09.104817 Write leveling (Byte 0): 24 => 24
8758 22:13:09.107271 Write leveling (Byte 1): 28 => 28
8759 22:13:09.111197 DramcWriteLeveling(PI) end<-----
8760 22:13:09.111764
8761 22:13:09.112135 ==
8762 22:13:09.114280 Dram Type= 6, Freq= 0, CH_1, rank 1
8763 22:13:09.117631 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8764 22:13:09.120858 ==
8765 22:13:09.121427 [Gating] SW mode calibration
8766 22:13:09.130507 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8767 22:13:09.133671 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8768 22:13:09.137242 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8769 22:13:09.143636 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8770 22:13:09.147164 1 4 8 | B1->B0 | 3232 2323 | 0 0 | (0 0) (0 0)
8771 22:13:09.150202 1 4 12 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (0 0)
8772 22:13:09.157129 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8773 22:13:09.159665 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8774 22:13:09.163361 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8775 22:13:09.169746 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8776 22:13:09.173189 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8777 22:13:09.176668 1 5 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8778 22:13:09.183293 1 5 8 | B1->B0 | 2424 3434 | 0 1 | (1 0) (1 0)
8779 22:13:09.187027 1 5 12 | B1->B0 | 2323 3232 | 0 0 | (1 0) (0 1)
8780 22:13:09.189549 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8781 22:13:09.196300 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8782 22:13:09.199813 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8783 22:13:09.202759 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8784 22:13:09.209724 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8785 22:13:09.212713 1 6 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8786 22:13:09.216163 1 6 8 | B1->B0 | 4444 2525 | 0 0 | (0 0) (0 0)
8787 22:13:09.223230 1 6 12 | B1->B0 | 4646 3f3f | 0 0 | (0 0) (0 0)
8788 22:13:09.225847 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8789 22:13:09.229278 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8790 22:13:09.235724 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8791 22:13:09.239038 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8792 22:13:09.242300 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8793 22:13:09.249292 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8794 22:13:09.252284 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8795 22:13:09.255762 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8796 22:13:09.261919 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8797 22:13:09.265290 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8798 22:13:09.268478 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8799 22:13:09.275410 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8800 22:13:09.278398 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8801 22:13:09.281970 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8802 22:13:09.288786 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8803 22:13:09.291987 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8804 22:13:09.295041 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8805 22:13:09.301720 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8806 22:13:09.305192 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8807 22:13:09.308186 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8808 22:13:09.314928 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8809 22:13:09.318289 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8810 22:13:09.324495 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8811 22:13:09.328019 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8812 22:13:09.331232 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8813 22:13:09.334449 Total UI for P1: 0, mck2ui 16
8814 22:13:09.337706 best dqsien dly found for B0: ( 1, 9, 10)
8815 22:13:09.341586 Total UI for P1: 0, mck2ui 16
8816 22:13:09.344128 best dqsien dly found for B1: ( 1, 9, 8)
8817 22:13:09.348092 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8818 22:13:09.350902 best DQS1 dly(MCK, UI, PI) = (1, 9, 8)
8819 22:13:09.351369
8820 22:13:09.354103 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8821 22:13:09.361194 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 8)
8822 22:13:09.361763 [Gating] SW calibration Done
8823 22:13:09.362140 ==
8824 22:13:09.364051 Dram Type= 6, Freq= 0, CH_1, rank 1
8825 22:13:09.370870 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8826 22:13:09.371342 ==
8827 22:13:09.371715 RX Vref Scan: 0
8828 22:13:09.372065
8829 22:13:09.374202 RX Vref 0 -> 0, step: 1
8830 22:13:09.374702
8831 22:13:09.377507 RX Delay 0 -> 252, step: 8
8832 22:13:09.381054 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8833 22:13:09.384216 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8834 22:13:09.387402 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8835 22:13:09.394264 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8836 22:13:09.397240 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8837 22:13:09.400432 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8838 22:13:09.403776 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8839 22:13:09.407024 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8840 22:13:09.414009 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8841 22:13:09.417052 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8842 22:13:09.420617 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8843 22:13:09.423997 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8844 22:13:09.427069 iDelay=200, Bit 12, Center 143 (88 ~ 199) 112
8845 22:13:09.433944 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8846 22:13:09.437574 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8847 22:13:09.440255 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8848 22:13:09.440831 ==
8849 22:13:09.443291 Dram Type= 6, Freq= 0, CH_1, rank 1
8850 22:13:09.446519 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8851 22:13:09.449642 ==
8852 22:13:09.450113 DQS Delay:
8853 22:13:09.450605 DQS0 = 0, DQS1 = 0
8854 22:13:09.453286 DQM Delay:
8855 22:13:09.453860 DQM0 = 135, DQM1 = 131
8856 22:13:09.456266 DQ Delay:
8857 22:13:09.459688 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8858 22:13:09.463030 DQ4 =135, DQ5 =147, DQ6 =139, DQ7 =135
8859 22:13:09.466410 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =127
8860 22:13:09.469317 DQ12 =143, DQ13 =139, DQ14 =135, DQ15 =143
8861 22:13:09.469787
8862 22:13:09.470156
8863 22:13:09.470586 ==
8864 22:13:09.472691 Dram Type= 6, Freq= 0, CH_1, rank 1
8865 22:13:09.476206 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8866 22:13:09.479856 ==
8867 22:13:09.480328
8868 22:13:09.480704
8869 22:13:09.481051 TX Vref Scan disable
8870 22:13:09.482536 == TX Byte 0 ==
8871 22:13:09.485845 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8872 22:13:09.489342 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8873 22:13:09.492851 == TX Byte 1 ==
8874 22:13:09.495969 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8875 22:13:09.499366 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8876 22:13:09.499933 ==
8877 22:13:09.502882 Dram Type= 6, Freq= 0, CH_1, rank 1
8878 22:13:09.509224 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8879 22:13:09.509776 ==
8880 22:13:09.521215
8881 22:13:09.524587 TX Vref early break, caculate TX vref
8882 22:13:09.527694 TX Vref=16, minBit 9, minWin=22, winSum=382
8883 22:13:09.531270 TX Vref=18, minBit 9, minWin=23, winSum=392
8884 22:13:09.534715 TX Vref=20, minBit 11, minWin=23, winSum=397
8885 22:13:09.537586 TX Vref=22, minBit 8, minWin=24, winSum=403
8886 22:13:09.541333 TX Vref=24, minBit 12, minWin=24, winSum=416
8887 22:13:09.547488 TX Vref=26, minBit 9, minWin=24, winSum=422
8888 22:13:09.550984 TX Vref=28, minBit 10, minWin=24, winSum=421
8889 22:13:09.554205 TX Vref=30, minBit 10, minWin=24, winSum=414
8890 22:13:09.558118 TX Vref=32, minBit 10, minWin=23, winSum=405
8891 22:13:09.560781 TX Vref=34, minBit 0, minWin=24, winSum=398
8892 22:13:09.567435 [TxChooseVref] Worse bit 9, Min win 24, Win sum 422, Final Vref 26
8893 22:13:09.567999
8894 22:13:09.570900 Final TX Range 0 Vref 26
8895 22:13:09.571482
8896 22:13:09.571864 ==
8897 22:13:09.573898 Dram Type= 6, Freq= 0, CH_1, rank 1
8898 22:13:09.577383 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8899 22:13:09.578116 ==
8900 22:13:09.578563
8901 22:13:09.580526
8902 22:13:09.580990 TX Vref Scan disable
8903 22:13:09.588077 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8904 22:13:09.588553 == TX Byte 0 ==
8905 22:13:09.590443 u2DelayCellOfst[0]=13 cells (4 PI)
8906 22:13:09.593893 u2DelayCellOfst[1]=10 cells (3 PI)
8907 22:13:09.597205 u2DelayCellOfst[2]=0 cells (0 PI)
8908 22:13:09.600779 u2DelayCellOfst[3]=3 cells (1 PI)
8909 22:13:09.603707 u2DelayCellOfst[4]=6 cells (2 PI)
8910 22:13:09.607066 u2DelayCellOfst[5]=16 cells (5 PI)
8911 22:13:09.610466 u2DelayCellOfst[6]=16 cells (5 PI)
8912 22:13:09.614279 u2DelayCellOfst[7]=3 cells (1 PI)
8913 22:13:09.617501 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8914 22:13:09.620421 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8915 22:13:09.623575 == TX Byte 1 ==
8916 22:13:09.627094 u2DelayCellOfst[8]=0 cells (0 PI)
8917 22:13:09.630192 u2DelayCellOfst[9]=3 cells (1 PI)
8918 22:13:09.633987 u2DelayCellOfst[10]=6 cells (2 PI)
8919 22:13:09.634599 u2DelayCellOfst[11]=3 cells (1 PI)
8920 22:13:09.636748 u2DelayCellOfst[12]=13 cells (4 PI)
8921 22:13:09.640240 u2DelayCellOfst[13]=13 cells (4 PI)
8922 22:13:09.643933 u2DelayCellOfst[14]=13 cells (4 PI)
8923 22:13:09.646809 u2DelayCellOfst[15]=13 cells (4 PI)
8924 22:13:09.653666 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8925 22:13:09.656396 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8926 22:13:09.656864 DramC Write-DBI on
8927 22:13:09.661096 ==
8928 22:13:09.661590 Dram Type= 6, Freq= 0, CH_1, rank 1
8929 22:13:09.666720 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8930 22:13:09.667187 ==
8931 22:13:09.667556
8932 22:13:09.667895
8933 22:13:09.669656 TX Vref Scan disable
8934 22:13:09.670119 == TX Byte 0 ==
8935 22:13:09.676278 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8936 22:13:09.676763 == TX Byte 1 ==
8937 22:13:09.679524 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8938 22:13:09.683043 DramC Write-DBI off
8939 22:13:09.683527
8940 22:13:09.683910 [DATLAT]
8941 22:13:09.686136 Freq=1600, CH1 RK1
8942 22:13:09.686726
8943 22:13:09.687128 DATLAT Default: 0xf
8944 22:13:09.689560 0, 0xFFFF, sum = 0
8945 22:13:09.690045 1, 0xFFFF, sum = 0
8946 22:13:09.692679 2, 0xFFFF, sum = 0
8947 22:13:09.693102 3, 0xFFFF, sum = 0
8948 22:13:09.696093 4, 0xFFFF, sum = 0
8949 22:13:09.696539 5, 0xFFFF, sum = 0
8950 22:13:09.699787 6, 0xFFFF, sum = 0
8951 22:13:09.700206 7, 0xFFFF, sum = 0
8952 22:13:09.702581 8, 0xFFFF, sum = 0
8953 22:13:09.706058 9, 0xFFFF, sum = 0
8954 22:13:09.706621 10, 0xFFFF, sum = 0
8955 22:13:09.709233 11, 0xFFFF, sum = 0
8956 22:13:09.709733 12, 0xFFFF, sum = 0
8957 22:13:09.713244 13, 0xFFFF, sum = 0
8958 22:13:09.713775 14, 0x0, sum = 1
8959 22:13:09.715827 15, 0x0, sum = 2
8960 22:13:09.716255 16, 0x0, sum = 3
8961 22:13:09.719752 17, 0x0, sum = 4
8962 22:13:09.720319 best_step = 15
8963 22:13:09.720693
8964 22:13:09.721033 ==
8965 22:13:09.722322 Dram Type= 6, Freq= 0, CH_1, rank 1
8966 22:13:09.726061 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8967 22:13:09.726670 ==
8968 22:13:09.730020 RX Vref Scan: 0
8969 22:13:09.730630
8970 22:13:09.732642 RX Vref 0 -> 0, step: 1
8971 22:13:09.733203
8972 22:13:09.733571 RX Delay 19 -> 252, step: 4
8973 22:13:09.739953 iDelay=195, Bit 0, Center 136 (91 ~ 182) 92
8974 22:13:09.742796 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
8975 22:13:09.746539 iDelay=195, Bit 2, Center 120 (71 ~ 170) 100
8976 22:13:09.749857 iDelay=195, Bit 3, Center 132 (83 ~ 182) 100
8977 22:13:09.753067 iDelay=195, Bit 4, Center 134 (87 ~ 182) 96
8978 22:13:09.759722 iDelay=195, Bit 5, Center 144 (99 ~ 190) 92
8979 22:13:09.762645 iDelay=195, Bit 6, Center 142 (95 ~ 190) 96
8980 22:13:09.766917 iDelay=195, Bit 7, Center 132 (83 ~ 182) 100
8981 22:13:09.769916 iDelay=195, Bit 8, Center 112 (63 ~ 162) 100
8982 22:13:09.773229 iDelay=195, Bit 9, Center 120 (71 ~ 170) 100
8983 22:13:09.779397 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
8984 22:13:09.782929 iDelay=195, Bit 11, Center 126 (75 ~ 178) 104
8985 22:13:09.786145 iDelay=195, Bit 12, Center 138 (87 ~ 190) 104
8986 22:13:09.789661 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
8987 22:13:09.792596 iDelay=195, Bit 14, Center 138 (91 ~ 186) 96
8988 22:13:09.799933 iDelay=195, Bit 15, Center 140 (87 ~ 194) 108
8989 22:13:09.800496 ==
8990 22:13:09.802735 Dram Type= 6, Freq= 0, CH_1, rank 1
8991 22:13:09.805777 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8992 22:13:09.806339 ==
8993 22:13:09.806773 DQS Delay:
8994 22:13:09.809145 DQS0 = 0, DQS1 = 0
8995 22:13:09.809668 DQM Delay:
8996 22:13:09.812476 DQM0 = 133, DQM1 = 130
8997 22:13:09.813037 DQ Delay:
8998 22:13:09.815578 DQ0 =136, DQ1 =130, DQ2 =120, DQ3 =132
8999 22:13:09.819209 DQ4 =134, DQ5 =144, DQ6 =142, DQ7 =132
9000 22:13:09.822691 DQ8 =112, DQ9 =120, DQ10 =130, DQ11 =126
9001 22:13:09.826085 DQ12 =138, DQ13 =136, DQ14 =138, DQ15 =140
9002 22:13:09.826690
9003 22:13:09.829347
9004 22:13:09.829899
9005 22:13:09.830273 [DramC_TX_OE_Calibration] TA2
9006 22:13:09.833255 Original DQ_B0 (3 6) =30, OEN = 27
9007 22:13:09.835884 Original DQ_B1 (3 6) =30, OEN = 27
9008 22:13:09.838824 24, 0x0, End_B0=24 End_B1=24
9009 22:13:09.842217 25, 0x0, End_B0=25 End_B1=25
9010 22:13:09.845730 26, 0x0, End_B0=26 End_B1=26
9011 22:13:09.846295 27, 0x0, End_B0=27 End_B1=27
9012 22:13:09.848837 28, 0x0, End_B0=28 End_B1=28
9013 22:13:09.852374 29, 0x0, End_B0=29 End_B1=29
9014 22:13:09.855820 30, 0x0, End_B0=30 End_B1=30
9015 22:13:09.858948 31, 0x4545, End_B0=30 End_B1=30
9016 22:13:09.862373 Byte0 end_step=30 best_step=27
9017 22:13:09.862940 Byte1 end_step=30 best_step=27
9018 22:13:09.865529 Byte0 TX OE(2T, 0.5T) = (3, 3)
9019 22:13:09.869084 Byte1 TX OE(2T, 0.5T) = (3, 3)
9020 22:13:09.869642
9021 22:13:09.870035
9022 22:13:09.878305 [DQSOSCAuto] RK1, (LSB)MR18= 0x1a06, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 396 ps
9023 22:13:09.878915 CH1 RK1: MR19=303, MR18=1A06
9024 22:13:09.885077 CH1_RK1: MR19=0x303, MR18=0x1A06, DQSOSC=396, MR23=63, INC=23, DEC=15
9025 22:13:09.888235 [RxdqsGatingPostProcess] freq 1600
9026 22:13:09.894845 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9027 22:13:09.898260 best DQS0 dly(2T, 0.5T) = (1, 1)
9028 22:13:09.901466 best DQS1 dly(2T, 0.5T) = (1, 1)
9029 22:13:09.905238 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9030 22:13:09.908425 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9031 22:13:09.908987 best DQS0 dly(2T, 0.5T) = (1, 1)
9032 22:13:09.911728 best DQS1 dly(2T, 0.5T) = (1, 1)
9033 22:13:09.914750 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9034 22:13:09.918520 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9035 22:13:09.921603 Pre-setting of DQS Precalculation
9036 22:13:09.928257 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9037 22:13:09.934988 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9038 22:13:09.941330 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9039 22:13:09.941899
9040 22:13:09.942266
9041 22:13:09.944707 [Calibration Summary] 3200 Mbps
9042 22:13:09.945269 CH 0, Rank 0
9043 22:13:09.947689 SW Impedance : PASS
9044 22:13:09.951287 DUTY Scan : NO K
9045 22:13:09.951864 ZQ Calibration : PASS
9046 22:13:09.954521 Jitter Meter : NO K
9047 22:13:09.957921 CBT Training : PASS
9048 22:13:09.958520 Write leveling : PASS
9049 22:13:09.961456 RX DQS gating : PASS
9050 22:13:09.965114 RX DQ/DQS(RDDQC) : PASS
9051 22:13:09.965676 TX DQ/DQS : PASS
9052 22:13:09.968057 RX DATLAT : PASS
9053 22:13:09.971057 RX DQ/DQS(Engine): PASS
9054 22:13:09.971521 TX OE : PASS
9055 22:13:09.974766 All Pass.
9056 22:13:09.975325
9057 22:13:09.975693 CH 0, Rank 1
9058 22:13:09.977701 SW Impedance : PASS
9059 22:13:09.978265 DUTY Scan : NO K
9060 22:13:09.980882 ZQ Calibration : PASS
9061 22:13:09.984622 Jitter Meter : NO K
9062 22:13:09.985369 CBT Training : PASS
9063 22:13:09.987844 Write leveling : PASS
9064 22:13:09.988408 RX DQS gating : PASS
9065 22:13:09.991055 RX DQ/DQS(RDDQC) : PASS
9066 22:13:09.993877 TX DQ/DQS : PASS
9067 22:13:09.994342 RX DATLAT : PASS
9068 22:13:09.997542 RX DQ/DQS(Engine): PASS
9069 22:13:10.000757 TX OE : PASS
9070 22:13:10.001219 All Pass.
9071 22:13:10.001584
9072 22:13:10.001920 CH 1, Rank 0
9073 22:13:10.004271 SW Impedance : PASS
9074 22:13:10.007453 DUTY Scan : NO K
9075 22:13:10.007918 ZQ Calibration : PASS
9076 22:13:10.011651 Jitter Meter : NO K
9077 22:13:10.014240 CBT Training : PASS
9078 22:13:10.014995 Write leveling : PASS
9079 22:13:10.018004 RX DQS gating : PASS
9080 22:13:10.021039 RX DQ/DQS(RDDQC) : PASS
9081 22:13:10.021602 TX DQ/DQS : PASS
9082 22:13:10.023934 RX DATLAT : PASS
9083 22:13:10.027838 RX DQ/DQS(Engine): PASS
9084 22:13:10.028494 TX OE : PASS
9085 22:13:10.028876 All Pass.
9086 22:13:10.030740
9087 22:13:10.031298 CH 1, Rank 1
9088 22:13:10.034603 SW Impedance : PASS
9089 22:13:10.035157 DUTY Scan : NO K
9090 22:13:10.037950 ZQ Calibration : PASS
9091 22:13:10.038557 Jitter Meter : NO K
9092 22:13:10.041205 CBT Training : PASS
9093 22:13:10.044133 Write leveling : PASS
9094 22:13:10.044697 RX DQS gating : PASS
9095 22:13:10.047047 RX DQ/DQS(RDDQC) : PASS
9096 22:13:10.050922 TX DQ/DQS : PASS
9097 22:13:10.051484 RX DATLAT : PASS
9098 22:13:10.054138 RX DQ/DQS(Engine): PASS
9099 22:13:10.057209 TX OE : PASS
9100 22:13:10.057770 All Pass.
9101 22:13:10.058137
9102 22:13:10.060732 DramC Write-DBI on
9103 22:13:10.061290 PER_BANK_REFRESH: Hybrid Mode
9104 22:13:10.064112 TX_TRACKING: ON
9105 22:13:10.073605 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9106 22:13:10.080247 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9107 22:13:10.086694 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9108 22:13:10.090585 [FAST_K] Save calibration result to emmc
9109 22:13:10.093420 sync common calibartion params.
9110 22:13:10.096827 sync cbt_mode0:1, 1:1
9111 22:13:10.097419 dram_init: ddr_geometry: 2
9112 22:13:10.100354 dram_init: ddr_geometry: 2
9113 22:13:10.103175 dram_init: ddr_geometry: 2
9114 22:13:10.106510 0:dram_rank_size:100000000
9115 22:13:10.106999 1:dram_rank_size:100000000
9116 22:13:10.113780 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9117 22:13:10.116587 DFS_SHUFFLE_HW_MODE: ON
9118 22:13:10.119850 dramc_set_vcore_voltage set vcore to 725000
9119 22:13:10.123003 Read voltage for 1600, 0
9120 22:13:10.123486 Vio18 = 0
9121 22:13:10.123878 Vcore = 725000
9122 22:13:10.126548 Vdram = 0
9123 22:13:10.127101 Vddq = 0
9124 22:13:10.127468 Vmddr = 0
9125 22:13:10.130709 switch to 3200 Mbps bootup
9126 22:13:10.131172 [DramcRunTimeConfig]
9127 22:13:10.132862 PHYPLL
9128 22:13:10.133322 DPM_CONTROL_AFTERK: ON
9129 22:13:10.136456 PER_BANK_REFRESH: ON
9130 22:13:10.139694 REFRESH_OVERHEAD_REDUCTION: ON
9131 22:13:10.140256 CMD_PICG_NEW_MODE: OFF
9132 22:13:10.143174 XRTWTW_NEW_MODE: ON
9133 22:13:10.143739 XRTRTR_NEW_MODE: ON
9134 22:13:10.146553 TX_TRACKING: ON
9135 22:13:10.147116 RDSEL_TRACKING: OFF
9136 22:13:10.150248 DQS Precalculation for DVFS: ON
9137 22:13:10.152771 RX_TRACKING: OFF
9138 22:13:10.153241 HW_GATING DBG: ON
9139 22:13:10.156635 ZQCS_ENABLE_LP4: ON
9140 22:13:10.157204 RX_PICG_NEW_MODE: ON
9141 22:13:10.159881 TX_PICG_NEW_MODE: ON
9142 22:13:10.162786 ENABLE_RX_DCM_DPHY: ON
9143 22:13:10.163355 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9144 22:13:10.166157 DUMMY_READ_FOR_TRACKING: OFF
9145 22:13:10.169528 !!! SPM_CONTROL_AFTERK: OFF
9146 22:13:10.172873 !!! SPM could not control APHY
9147 22:13:10.175776 IMPEDANCE_TRACKING: ON
9148 22:13:10.176352 TEMP_SENSOR: ON
9149 22:13:10.178889 HW_SAVE_FOR_SR: OFF
9150 22:13:10.179357 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9151 22:13:10.185768 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9152 22:13:10.186337 Read ODT Tracking: ON
9153 22:13:10.189376 Refresh Rate DeBounce: ON
9154 22:13:10.189945 DFS_NO_QUEUE_FLUSH: ON
9155 22:13:10.192776 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9156 22:13:10.195337 ENABLE_DFS_RUNTIME_MRW: OFF
9157 22:13:10.198920 DDR_RESERVE_NEW_MODE: ON
9158 22:13:10.202152 MR_CBT_SWITCH_FREQ: ON
9159 22:13:10.202720 =========================
9160 22:13:10.221560 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9161 22:13:10.225214 dram_init: ddr_geometry: 2
9162 22:13:10.243317 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9163 22:13:10.246725 dram_init: dram init end (result: 0)
9164 22:13:10.253207 DRAM-K: Full calibration passed in 24529 msecs
9165 22:13:10.257285 MRC: failed to locate region type 0.
9166 22:13:10.257859 DRAM rank0 size:0x100000000,
9167 22:13:10.259789 DRAM rank1 size=0x100000000
9168 22:13:10.269981 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9169 22:13:10.276345 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9170 22:13:10.282669 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9171 22:13:10.293716 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9172 22:13:10.294291 DRAM rank0 size:0x100000000,
9173 22:13:10.296335 DRAM rank1 size=0x100000000
9174 22:13:10.296905 CBMEM:
9175 22:13:10.300204 IMD: root @ 0xfffff000 254 entries.
9176 22:13:10.302700 IMD: root @ 0xffffec00 62 entries.
9177 22:13:10.305893 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9178 22:13:10.312716 WARNING: RO_VPD is uninitialized or empty.
9179 22:13:10.315631 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9180 22:13:10.323177 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9181 22:13:10.336099 read SPI 0x42894 0xe01e: 6226 us, 9215 KB/s, 73.720 Mbps
9182 22:13:10.347411 BS: romstage times (exec / console): total (unknown) / 24041 ms
9183 22:13:10.347991
9184 22:13:10.348367
9185 22:13:10.357939 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9186 22:13:10.360862 ARM64: Exception handlers installed.
9187 22:13:10.364465 ARM64: Testing exception
9188 22:13:10.367385 ARM64: Done test exception
9189 22:13:10.367955 Enumerating buses...
9190 22:13:10.370763 Show all devs... Before device enumeration.
9191 22:13:10.373855 Root Device: enabled 1
9192 22:13:10.377334 CPU_CLUSTER: 0: enabled 1
9193 22:13:10.377906 CPU: 00: enabled 1
9194 22:13:10.380355 Compare with tree...
9195 22:13:10.380851 Root Device: enabled 1
9196 22:13:10.383447 CPU_CLUSTER: 0: enabled 1
9197 22:13:10.387300 CPU: 00: enabled 1
9198 22:13:10.387879 Root Device scanning...
9199 22:13:10.390834 scan_static_bus for Root Device
9200 22:13:10.394509 CPU_CLUSTER: 0 enabled
9201 22:13:10.397363 scan_static_bus for Root Device done
9202 22:13:10.400757 scan_bus: bus Root Device finished in 8 msecs
9203 22:13:10.401332 done
9204 22:13:10.407598 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9205 22:13:10.410016 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9206 22:13:10.416945 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9207 22:13:10.420424 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9208 22:13:10.424149 Allocating resources...
9209 22:13:10.426942 Reading resources...
9210 22:13:10.430122 Root Device read_resources bus 0 link: 0
9211 22:13:10.433435 DRAM rank0 size:0x100000000,
9212 22:13:10.434009 DRAM rank1 size=0x100000000
9213 22:13:10.437469 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9214 22:13:10.440845 CPU: 00 missing read_resources
9215 22:13:10.446869 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9216 22:13:10.450022 Root Device read_resources bus 0 link: 0 done
9217 22:13:10.450573 Done reading resources.
9218 22:13:10.457553 Show resources in subtree (Root Device)...After reading.
9219 22:13:10.459907 Root Device child on link 0 CPU_CLUSTER: 0
9220 22:13:10.463269 CPU_CLUSTER: 0 child on link 0 CPU: 00
9221 22:13:10.473472 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9222 22:13:10.474053 CPU: 00
9223 22:13:10.476777 Root Device assign_resources, bus 0 link: 0
9224 22:13:10.480200 CPU_CLUSTER: 0 missing set_resources
9225 22:13:10.486813 Root Device assign_resources, bus 0 link: 0 done
9226 22:13:10.487385 Done setting resources.
9227 22:13:10.493234 Show resources in subtree (Root Device)...After assigning values.
9228 22:13:10.496442 Root Device child on link 0 CPU_CLUSTER: 0
9229 22:13:10.499769 CPU_CLUSTER: 0 child on link 0 CPU: 00
9230 22:13:10.509598 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9231 22:13:10.510181 CPU: 00
9232 22:13:10.512867 Done allocating resources.
9233 22:13:10.519517 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9234 22:13:10.520175 Enabling resources...
9235 22:13:10.520661 done.
9236 22:13:10.526189 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9237 22:13:10.526848 Initializing devices...
9238 22:13:10.529880 Root Device init
9239 22:13:10.533463 init hardware done!
9240 22:13:10.534048 0x00000018: ctrlr->caps
9241 22:13:10.536077 52.000 MHz: ctrlr->f_max
9242 22:13:10.539719 0.400 MHz: ctrlr->f_min
9243 22:13:10.540303 0x40ff8080: ctrlr->voltages
9244 22:13:10.543089 sclk: 390625
9245 22:13:10.543676 Bus Width = 1
9246 22:13:10.544062 sclk: 390625
9247 22:13:10.545672 Bus Width = 1
9248 22:13:10.546144 Early init status = 3
9249 22:13:10.552281 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9250 22:13:10.556591 in-header: 03 fc 00 00 01 00 00 00
9251 22:13:10.558986 in-data: 00
9252 22:13:10.562426 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9253 22:13:10.566708 in-header: 03 fd 00 00 00 00 00 00
9254 22:13:10.569552 in-data:
9255 22:13:10.572994 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9256 22:13:10.576925 in-header: 03 fc 00 00 01 00 00 00
9257 22:13:10.580187 in-data: 00
9258 22:13:10.582999 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9259 22:13:10.588666 in-header: 03 fd 00 00 00 00 00 00
9260 22:13:10.592196 in-data:
9261 22:13:10.595217 [SSUSB] Setting up USB HOST controller...
9262 22:13:10.599010 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9263 22:13:10.601644 [SSUSB] phy power-on done.
9264 22:13:10.605100 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9265 22:13:10.611988 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9266 22:13:10.615323 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9267 22:13:10.621416 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9268 22:13:10.627996 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9269 22:13:10.635255 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9270 22:13:10.641659 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9271 22:13:10.647789 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9272 22:13:10.651699 SPM: binary array size = 0x9dc
9273 22:13:10.654748 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9274 22:13:10.661514 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9275 22:13:10.668749 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9276 22:13:10.675261 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9277 22:13:10.677843 configure_display: Starting display init
9278 22:13:10.711916 anx7625_power_on_init: Init interface.
9279 22:13:10.714961 anx7625_disable_pd_protocol: Disabled PD feature.
9280 22:13:10.718786 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9281 22:13:10.746239 anx7625_start_dp_work: Secure OCM version=00
9282 22:13:10.749206 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9283 22:13:10.764582 sp_tx_get_edid_block: EDID Block = 1
9284 22:13:10.867358 Extracted contents:
9285 22:13:10.870238 header: 00 ff ff ff ff ff ff 00
9286 22:13:10.873977 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9287 22:13:10.876957 version: 01 04
9288 22:13:10.880480 basic params: 95 1f 11 78 0a
9289 22:13:10.883511 chroma info: 76 90 94 55 54 90 27 21 50 54
9290 22:13:10.886873 established: 00 00 00
9291 22:13:10.893490 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9292 22:13:10.896271 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9293 22:13:10.903165 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9294 22:13:10.909969 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9295 22:13:10.916190 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9296 22:13:10.919490 extensions: 00
9297 22:13:10.919945 checksum: fb
9298 22:13:10.920307
9299 22:13:10.923270 Manufacturer: IVO Model 57d Serial Number 0
9300 22:13:10.927179 Made week 0 of 2020
9301 22:13:10.929479 EDID version: 1.4
9302 22:13:10.929894 Digital display
9303 22:13:10.933007 6 bits per primary color channel
9304 22:13:10.933533 DisplayPort interface
9305 22:13:10.936402 Maximum image size: 31 cm x 17 cm
9306 22:13:10.939772 Gamma: 220%
9307 22:13:10.940291 Check DPMS levels
9308 22:13:10.946219 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9309 22:13:10.949301 First detailed timing is preferred timing
9310 22:13:10.949757 Established timings supported:
9311 22:13:10.952704 Standard timings supported:
9312 22:13:10.956157 Detailed timings
9313 22:13:10.959272 Hex of detail: 383680a07038204018303c0035ae10000019
9314 22:13:10.966037 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9315 22:13:10.969272 0780 0798 07c8 0820 hborder 0
9316 22:13:10.972690 0438 043b 0447 0458 vborder 0
9317 22:13:10.975997 -hsync -vsync
9318 22:13:10.976518 Did detailed timing
9319 22:13:10.982607 Hex of detail: 000000000000000000000000000000000000
9320 22:13:10.985640 Manufacturer-specified data, tag 0
9321 22:13:10.988918 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9322 22:13:10.992564 ASCII string: InfoVision
9323 22:13:10.995649 Hex of detail: 000000fe00523134304e574635205248200a
9324 22:13:10.998917 ASCII string: R140NWF5 RH
9325 22:13:10.999437 Checksum
9326 22:13:11.002194 Checksum: 0xfb (valid)
9327 22:13:11.005569 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9328 22:13:11.009116 DSI data_rate: 832800000 bps
9329 22:13:11.015838 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9330 22:13:11.018687 anx7625_parse_edid: pixelclock(138800).
9331 22:13:11.022026 hactive(1920), hsync(48), hfp(24), hbp(88)
9332 22:13:11.025227 vactive(1080), vsync(12), vfp(3), vbp(17)
9333 22:13:11.029620 anx7625_dsi_config: config dsi.
9334 22:13:11.035407 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9335 22:13:11.049743 anx7625_dsi_config: success to config DSI
9336 22:13:11.052424 anx7625_dp_start: MIPI phy setup OK.
9337 22:13:11.055465 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9338 22:13:11.058870 mtk_ddp_mode_set invalid vrefresh 60
9339 22:13:11.062291 main_disp_path_setup
9340 22:13:11.062898 ovl_layer_smi_id_en
9341 22:13:11.065563 ovl_layer_smi_id_en
9342 22:13:11.066034 ccorr_config
9343 22:13:11.066451 aal_config
9344 22:13:11.068816 gamma_config
9345 22:13:11.069379 postmask_config
9346 22:13:11.072115 dither_config
9347 22:13:11.075685 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9348 22:13:11.081758 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9349 22:13:11.085559 Root Device init finished in 552 msecs
9350 22:13:11.088446 CPU_CLUSTER: 0 init
9351 22:13:11.095223 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9352 22:13:11.102010 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9353 22:13:11.102627 APU_MBOX 0x190000b0 = 0x10001
9354 22:13:11.105193 APU_MBOX 0x190001b0 = 0x10001
9355 22:13:11.108667 APU_MBOX 0x190005b0 = 0x10001
9356 22:13:11.111566 APU_MBOX 0x190006b0 = 0x10001
9357 22:13:11.118250 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9358 22:13:11.128549 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9359 22:13:11.140622 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9360 22:13:11.146952 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9361 22:13:11.158983 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9362 22:13:11.167519 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9363 22:13:11.171221 CPU_CLUSTER: 0 init finished in 81 msecs
9364 22:13:11.174634 Devices initialized
9365 22:13:11.177593 Show all devs... After init.
9366 22:13:11.178162 Root Device: enabled 1
9367 22:13:11.181384 CPU_CLUSTER: 0: enabled 1
9368 22:13:11.183863 CPU: 00: enabled 1
9369 22:13:11.187519 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms
9370 22:13:11.190731 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9371 22:13:11.193872 ELOG: NV offset 0x57f000 size 0x1000
9372 22:13:11.200717 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9373 22:13:11.207213 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9374 22:13:11.210826 ELOG: Event(17) added with size 13 at 2023-06-04 22:13:23 UTC
9375 22:13:11.217470 out: cmd=0x121: 03 db 21 01 00 00 00 00
9376 22:13:11.221451 in-header: 03 00 00 00 2c 00 00 00
9377 22:13:11.230622 in-data: 5f 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9378 22:13:11.237179 ELOG: Event(A1) added with size 10 at 2023-06-04 22:13:23 UTC
9379 22:13:11.243635 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9380 22:13:11.250417 ELOG: Event(A0) added with size 9 at 2023-06-04 22:13:23 UTC
9381 22:13:11.254283 elog_add_boot_reason: Logged dev mode boot
9382 22:13:11.260264 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9383 22:13:11.260844 Finalize devices...
9384 22:13:11.263487 Devices finalized
9385 22:13:11.266646 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9386 22:13:11.270192 Writing coreboot table at 0xffe64000
9387 22:13:11.273840 0. 000000000010a000-0000000000113fff: RAMSTAGE
9388 22:13:11.279769 1. 0000000040000000-00000000400fffff: RAM
9389 22:13:11.283444 2. 0000000040100000-000000004032afff: RAMSTAGE
9390 22:13:11.286655 3. 000000004032b000-00000000545fffff: RAM
9391 22:13:11.290155 4. 0000000054600000-000000005465ffff: BL31
9392 22:13:11.293051 5. 0000000054660000-00000000ffe63fff: RAM
9393 22:13:11.300013 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9394 22:13:11.303444 7. 0000000100000000-000000023fffffff: RAM
9395 22:13:11.306625 Passing 5 GPIOs to payload:
9396 22:13:11.310010 NAME | PORT | POLARITY | VALUE
9397 22:13:11.316619 EC in RW | 0x000000aa | low | undefined
9398 22:13:11.320266 EC interrupt | 0x00000005 | low | undefined
9399 22:13:11.323236 TPM interrupt | 0x000000ab | high | undefined
9400 22:13:11.330270 SD card detect | 0x00000011 | high | undefined
9401 22:13:11.333085 speaker enable | 0x00000093 | high | undefined
9402 22:13:11.336366 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9403 22:13:11.339723 in-header: 03 f9 00 00 02 00 00 00
9404 22:13:11.342945 in-data: 02 00
9405 22:13:11.346603 ADC[4]: Raw value=901032 ID=7
9406 22:13:11.347177 ADC[3]: Raw value=213179 ID=1
9407 22:13:11.349468 RAM Code: 0x71
9408 22:13:11.352862 ADC[6]: Raw value=74502 ID=0
9409 22:13:11.353433 ADC[5]: Raw value=212072 ID=1
9410 22:13:11.356014 SKU Code: 0x1
9411 22:13:11.363304 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 4ba3
9412 22:13:11.363873 coreboot table: 964 bytes.
9413 22:13:11.366335 IMD ROOT 0. 0xfffff000 0x00001000
9414 22:13:11.369317 IMD SMALL 1. 0xffffe000 0x00001000
9415 22:13:11.372593 RO MCACHE 2. 0xffffc000 0x00001104
9416 22:13:11.375736 CONSOLE 3. 0xfff7c000 0x00080000
9417 22:13:11.379062 FMAP 4. 0xfff7b000 0x00000452
9418 22:13:11.382233 TIME STAMP 5. 0xfff7a000 0x00000910
9419 22:13:11.385635 VBOOT WORK 6. 0xfff66000 0x00014000
9420 22:13:11.388709 RAMOOPS 7. 0xffe66000 0x00100000
9421 22:13:11.392202 COREBOOT 8. 0xffe64000 0x00002000
9422 22:13:11.395466 IMD small region:
9423 22:13:11.398552 IMD ROOT 0. 0xffffec00 0x00000400
9424 22:13:11.402216 VPD 1. 0xffffeba0 0x0000004c
9425 22:13:11.405758 MMC STATUS 2. 0xffffeb80 0x00000004
9426 22:13:11.409140 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9427 22:13:11.412672 Probing TPM: done!
9428 22:13:11.415441 Connected to device vid:did:rid of 1ae0:0028:00
9429 22:13:11.427086 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9430 22:13:11.430019 Initialized TPM device CR50 revision 0
9431 22:13:11.433370 Checking cr50 for pending updates
9432 22:13:11.437282 Reading cr50 TPM mode
9433 22:13:11.446032 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9434 22:13:11.452541 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9435 22:13:11.492677 read SPI 0x3990ec 0x4f1b0: 34854 us, 9296 KB/s, 74.368 Mbps
9436 22:13:11.495980 Checking segment from ROM address 0x40100000
9437 22:13:11.499518 Checking segment from ROM address 0x4010001c
9438 22:13:11.506056 Loading segment from ROM address 0x40100000
9439 22:13:11.506773 code (compression=0)
9440 22:13:11.516195 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9441 22:13:11.522624 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9442 22:13:11.523215 it's not compressed!
9443 22:13:11.529514 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9444 22:13:11.533597 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9445 22:13:11.553388 Loading segment from ROM address 0x4010001c
9446 22:13:11.553965 Entry Point 0x80000000
9447 22:13:11.556591 Loaded segments
9448 22:13:11.559821 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9449 22:13:11.566611 Jumping to boot code at 0x80000000(0xffe64000)
9450 22:13:11.573262 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9451 22:13:11.579636 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9452 22:13:11.587231 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9453 22:13:11.590556 Checking segment from ROM address 0x40100000
9454 22:13:11.593893 Checking segment from ROM address 0x4010001c
9455 22:13:11.600734 Loading segment from ROM address 0x40100000
9456 22:13:11.601298 code (compression=1)
9457 22:13:11.607118 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9458 22:13:11.617306 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9459 22:13:11.617883 using LZMA
9460 22:13:11.625697 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9461 22:13:11.633280 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9462 22:13:11.635451 Loading segment from ROM address 0x4010001c
9463 22:13:11.638993 Entry Point 0x54601000
9464 22:13:11.639565 Loaded segments
9465 22:13:11.642799 NOTICE: MT8192 bl31_setup
9466 22:13:11.650325 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9467 22:13:11.652567 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9468 22:13:11.656529 WARNING: region 0:
9469 22:13:11.659241 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9470 22:13:11.659818 WARNING: region 1:
9471 22:13:11.666580 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9472 22:13:11.669675 WARNING: region 2:
9473 22:13:11.672771 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9474 22:13:11.675927 WARNING: region 3:
9475 22:13:11.679356 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9476 22:13:11.682943 WARNING: region 4:
9477 22:13:11.689558 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9478 22:13:11.690125 WARNING: region 5:
9479 22:13:11.692867 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9480 22:13:11.696312 WARNING: region 6:
9481 22:13:11.699259 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9482 22:13:11.702431 WARNING: region 7:
9483 22:13:11.705887 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9484 22:13:11.712952 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9485 22:13:11.716418 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9486 22:13:11.719373 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9487 22:13:11.726419 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9488 22:13:11.729398 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9489 22:13:11.732857 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9490 22:13:11.739510 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9491 22:13:11.742873 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9492 22:13:11.749422 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9493 22:13:11.752385 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9494 22:13:11.756257 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9495 22:13:11.762629 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9496 22:13:11.766995 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9497 22:13:11.769511 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9498 22:13:11.775899 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9499 22:13:11.779159 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9500 22:13:11.786757 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9501 22:13:11.789354 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9502 22:13:11.792850 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9503 22:13:11.799377 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9504 22:13:11.802437 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9505 22:13:11.805738 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9506 22:13:11.812418 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9507 22:13:11.815641 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9508 22:13:11.822509 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9509 22:13:11.825897 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9510 22:13:11.829663 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9511 22:13:11.835993 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9512 22:13:11.838984 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9513 22:13:11.846063 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9514 22:13:11.849530 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9515 22:13:11.852413 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9516 22:13:11.859200 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9517 22:13:11.862817 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9518 22:13:11.866216 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9519 22:13:11.869390 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9520 22:13:11.876222 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9521 22:13:11.879682 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9522 22:13:11.882810 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9523 22:13:11.885755 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9524 22:13:11.893282 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9525 22:13:11.896282 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9526 22:13:11.899153 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9527 22:13:11.902744 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9528 22:13:11.910444 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9529 22:13:11.912564 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9530 22:13:11.915778 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9531 22:13:11.919075 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9532 22:13:11.925741 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9533 22:13:11.928869 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9534 22:13:11.935649 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9535 22:13:11.938986 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9536 22:13:11.945753 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9537 22:13:11.948951 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9538 22:13:11.952532 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9539 22:13:11.959240 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9540 22:13:11.962608 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9541 22:13:11.969267 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9542 22:13:11.972589 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9543 22:13:11.979262 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9544 22:13:11.982348 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9545 22:13:11.989075 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9546 22:13:11.991941 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9547 22:13:11.995786 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9548 22:13:12.003219 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9549 22:13:12.005440 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9550 22:13:12.012338 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9551 22:13:12.015549 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9552 22:13:12.022248 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9553 22:13:12.025746 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9554 22:13:12.028935 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9555 22:13:12.035277 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9556 22:13:12.039377 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9557 22:13:12.045512 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9558 22:13:12.049286 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9559 22:13:12.055714 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9560 22:13:12.059204 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9561 22:13:12.062552 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9562 22:13:12.069146 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9563 22:13:12.072181 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9564 22:13:12.079111 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9565 22:13:12.082318 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9566 22:13:12.089085 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9567 22:13:12.092468 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9568 22:13:12.095941 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9569 22:13:12.102509 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9570 22:13:12.105813 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9571 22:13:12.112163 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9572 22:13:12.115991 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9573 22:13:12.122450 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9574 22:13:12.126245 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9575 22:13:12.128860 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9576 22:13:12.135407 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9577 22:13:12.138932 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9578 22:13:12.145572 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9579 22:13:12.148676 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9580 22:13:12.155217 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9581 22:13:12.158479 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9582 22:13:12.162105 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9583 22:13:12.165111 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9584 22:13:12.172292 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9585 22:13:12.175203 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9586 22:13:12.179060 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9587 22:13:12.185287 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9588 22:13:12.188979 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9589 22:13:12.191574 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9590 22:13:12.198587 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9591 22:13:12.202217 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9592 22:13:12.208158 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9593 22:13:12.211354 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9594 22:13:12.218263 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9595 22:13:12.222071 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9596 22:13:12.225335 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9597 22:13:12.231711 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9598 22:13:12.234853 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9599 22:13:12.241892 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9600 22:13:12.244866 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9601 22:13:12.249184 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9602 22:13:12.254750 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9603 22:13:12.258183 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9604 22:13:12.261442 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9605 22:13:12.264519 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9606 22:13:12.268503 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9607 22:13:12.274730 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9608 22:13:12.278029 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9609 22:13:12.281753 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9610 22:13:12.288096 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9611 22:13:12.291649 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9612 22:13:12.298121 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9613 22:13:12.301272 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9614 22:13:12.304516 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9615 22:13:12.311260 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9616 22:13:12.314617 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9617 22:13:12.321618 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9618 22:13:12.325242 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9619 22:13:12.328144 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9620 22:13:12.334219 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9621 22:13:12.337827 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9622 22:13:12.344378 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9623 22:13:12.347625 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9624 22:13:12.350713 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9625 22:13:12.358163 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9626 22:13:12.361709 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9627 22:13:12.367616 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9628 22:13:12.370829 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9629 22:13:12.374100 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9630 22:13:12.380908 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9631 22:13:12.384771 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9632 22:13:12.390957 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9633 22:13:12.394288 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9634 22:13:12.398084 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9635 22:13:12.404301 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9636 22:13:12.407257 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9637 22:13:12.414735 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9638 22:13:12.417173 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9639 22:13:12.420573 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9640 22:13:12.427254 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9641 22:13:12.431254 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9642 22:13:12.433568 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9643 22:13:12.440433 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9644 22:13:12.444167 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9645 22:13:12.450135 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9646 22:13:12.453414 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9647 22:13:12.456733 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9648 22:13:12.463456 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9649 22:13:12.466794 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9650 22:13:12.473084 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9651 22:13:12.476596 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9652 22:13:12.480126 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9653 22:13:12.486446 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9654 22:13:12.490385 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9655 22:13:12.496712 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9656 22:13:12.499787 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9657 22:13:12.503030 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9658 22:13:12.510034 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9659 22:13:12.513598 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9660 22:13:12.519810 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9661 22:13:12.523124 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9662 22:13:12.526077 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9663 22:13:12.532852 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9664 22:13:12.536663 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9665 22:13:12.543007 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9666 22:13:12.546333 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9667 22:13:12.549970 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9668 22:13:12.556808 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9669 22:13:12.559178 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9670 22:13:12.566266 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9671 22:13:12.569330 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9672 22:13:12.572420 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9673 22:13:12.579029 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9674 22:13:12.582322 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9675 22:13:12.589751 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9676 22:13:12.592271 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9677 22:13:12.599142 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9678 22:13:12.602641 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9679 22:13:12.605433 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9680 22:13:12.612402 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9681 22:13:12.615909 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9682 22:13:12.622212 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9683 22:13:12.625377 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9684 22:13:12.629108 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9685 22:13:12.635504 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9686 22:13:12.638370 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9687 22:13:12.645255 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9688 22:13:12.648727 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9689 22:13:12.655079 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9690 22:13:12.658526 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9691 22:13:12.662308 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9692 22:13:12.668083 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9693 22:13:12.672276 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9694 22:13:12.678158 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9695 22:13:12.681809 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9696 22:13:12.688368 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9697 22:13:12.691419 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9698 22:13:12.694973 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9699 22:13:12.701636 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9700 22:13:12.704773 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9701 22:13:12.711661 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9702 22:13:12.714824 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9703 22:13:12.721703 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9704 22:13:12.724811 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9705 22:13:12.728042 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9706 22:13:12.734755 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9707 22:13:12.738317 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9708 22:13:12.744401 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9709 22:13:12.747962 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9710 22:13:12.754465 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9711 22:13:12.757980 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9712 22:13:12.761184 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9713 22:13:12.767587 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9714 22:13:12.770874 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9715 22:13:12.774257 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9716 22:13:12.777453 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9717 22:13:12.780529 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9718 22:13:12.787413 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9719 22:13:12.790463 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9720 22:13:12.797087 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9721 22:13:12.800421 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9722 22:13:12.803760 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9723 22:13:12.810314 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9724 22:13:12.813478 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9725 22:13:12.820314 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9726 22:13:12.823869 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9727 22:13:12.826729 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9728 22:13:12.833811 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9729 22:13:12.837026 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9730 22:13:12.840554 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9731 22:13:12.846857 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9732 22:13:12.850088 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9733 22:13:12.856759 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9734 22:13:12.860075 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9735 22:13:12.863247 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9736 22:13:12.869935 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9737 22:13:12.873100 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9738 22:13:12.876450 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9739 22:13:12.882943 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9740 22:13:12.886104 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9741 22:13:12.892951 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9742 22:13:12.896026 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9743 22:13:12.899721 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9744 22:13:12.906179 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9745 22:13:12.909640 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9746 22:13:12.913809 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9747 22:13:12.919625 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9748 22:13:12.922602 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9749 22:13:12.926012 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9750 22:13:12.932817 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9751 22:13:12.935761 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9752 22:13:12.942592 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9753 22:13:12.946055 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9754 22:13:12.949349 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9755 22:13:12.952644 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9756 22:13:12.956038 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9757 22:13:12.962484 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9758 22:13:12.965722 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9759 22:13:12.969356 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9760 22:13:12.972824 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9761 22:13:12.978917 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9762 22:13:12.982489 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9763 22:13:12.985418 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9764 22:13:12.991681 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9765 22:13:12.995590 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9766 22:13:12.998471 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9767 22:13:13.005059 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9768 22:13:13.008262 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9769 22:13:13.015146 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9770 22:13:13.018466 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9771 22:13:13.021673 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9772 22:13:13.028294 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9773 22:13:13.031884 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9774 22:13:13.038877 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9775 22:13:13.041834 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9776 22:13:13.044695 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9777 22:13:13.052121 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9778 22:13:13.054843 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9779 22:13:13.061350 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9780 22:13:13.064880 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9781 22:13:13.072513 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9782 22:13:13.075071 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9783 22:13:13.078282 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9784 22:13:13.084957 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9785 22:13:13.087575 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9786 22:13:13.094871 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9787 22:13:13.097916 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9788 22:13:13.104165 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9789 22:13:13.107554 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9790 22:13:13.110919 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9791 22:13:13.118134 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9792 22:13:13.121671 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9793 22:13:13.127712 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9794 22:13:13.130727 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9795 22:13:13.133984 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9796 22:13:13.141983 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9797 22:13:13.144067 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9798 22:13:13.150760 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9799 22:13:13.154256 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9800 22:13:13.157547 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9801 22:13:13.163858 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9802 22:13:13.167227 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9803 22:13:13.173759 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9804 22:13:13.177262 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9805 22:13:13.180417 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9806 22:13:13.187054 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9807 22:13:13.190449 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9808 22:13:13.196753 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9809 22:13:13.200320 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9810 22:13:13.206736 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9811 22:13:13.210483 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9812 22:13:13.213541 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9813 22:13:13.219908 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9814 22:13:13.223136 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9815 22:13:13.230719 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9816 22:13:13.233262 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9817 22:13:13.236243 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9818 22:13:13.243423 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9819 22:13:13.246445 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9820 22:13:13.252898 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9821 22:13:13.256300 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9822 22:13:13.262737 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9823 22:13:13.266315 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9824 22:13:13.269483 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9825 22:13:13.276528 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9826 22:13:13.279085 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9827 22:13:13.286261 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9828 22:13:13.289175 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9829 22:13:13.292879 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9830 22:13:13.299627 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9831 22:13:13.302423 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9832 22:13:13.309647 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9833 22:13:13.312284 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9834 22:13:13.319179 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9835 22:13:13.322343 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9836 22:13:13.326173 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9837 22:13:13.332361 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9838 22:13:13.335478 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9839 22:13:13.342166 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9840 22:13:13.345629 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9841 22:13:13.352206 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9842 22:13:13.355301 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9843 22:13:13.358980 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9844 22:13:13.365379 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9845 22:13:13.368934 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9846 22:13:13.375415 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9847 22:13:13.378475 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9848 22:13:13.385206 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9849 22:13:13.388367 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9850 22:13:13.395422 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9851 22:13:13.398474 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9852 22:13:13.402017 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9853 22:13:13.408421 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9854 22:13:13.411924 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9855 22:13:13.418029 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9856 22:13:13.421836 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9857 22:13:13.427922 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9858 22:13:13.431426 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9859 22:13:13.434835 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9860 22:13:13.441986 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9861 22:13:13.444863 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9862 22:13:13.451853 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9863 22:13:13.455063 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9864 22:13:13.461886 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9865 22:13:13.464906 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9866 22:13:13.471297 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9867 22:13:13.474937 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9868 22:13:13.478402 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9869 22:13:13.484884 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9870 22:13:13.487749 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9871 22:13:13.494557 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9872 22:13:13.497357 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9873 22:13:13.504411 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9874 22:13:13.507951 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9875 22:13:13.514597 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9876 22:13:13.517425 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9877 22:13:13.520570 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9878 22:13:13.527227 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9879 22:13:13.530838 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9880 22:13:13.537791 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9881 22:13:13.540783 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9882 22:13:13.547218 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9883 22:13:13.550478 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9884 22:13:13.557167 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9885 22:13:13.560581 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9886 22:13:13.563675 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9887 22:13:13.570486 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9888 22:13:13.573704 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9889 22:13:13.580399 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9890 22:13:13.583577 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9891 22:13:13.590737 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9892 22:13:13.593935 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9893 22:13:13.600093 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9894 22:13:13.603535 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9895 22:13:13.610198 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9896 22:13:13.613104 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9897 22:13:13.619923 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9898 22:13:13.622949 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9899 22:13:13.626169 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9900 22:13:13.633258 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9901 22:13:13.636450 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9902 22:13:13.643210 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9903 22:13:13.646151 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9904 22:13:13.653272 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9905 22:13:13.656029 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9906 22:13:13.662377 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9907 22:13:13.666170 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9908 22:13:13.672841 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9909 22:13:13.675790 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9910 22:13:13.682749 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9911 22:13:13.685556 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9912 22:13:13.692314 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9913 22:13:13.698942 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9914 22:13:13.702099 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9915 22:13:13.709148 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9916 22:13:13.711894 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9917 22:13:13.719237 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9918 22:13:13.721768 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9919 22:13:13.722240 INFO: [APUAPC] vio 0
9920 22:13:13.729432 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9921 22:13:13.732925 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9922 22:13:13.735801 INFO: [APUAPC] D0_APC_0: 0x400510
9923 22:13:13.739358 INFO: [APUAPC] D0_APC_1: 0x0
9924 22:13:13.742987 INFO: [APUAPC] D0_APC_2: 0x1540
9925 22:13:13.746012 INFO: [APUAPC] D0_APC_3: 0x0
9926 22:13:13.749531 INFO: [APUAPC] D1_APC_0: 0xffffffff
9927 22:13:13.752766 INFO: [APUAPC] D1_APC_1: 0xffffffff
9928 22:13:13.755895 INFO: [APUAPC] D1_APC_2: 0x3fffff
9929 22:13:13.759157 INFO: [APUAPC] D1_APC_3: 0x0
9930 22:13:13.762785 INFO: [APUAPC] D2_APC_0: 0xffffffff
9931 22:13:13.765811 INFO: [APUAPC] D2_APC_1: 0xffffffff
9932 22:13:13.769183 INFO: [APUAPC] D2_APC_2: 0x3fffff
9933 22:13:13.772663 INFO: [APUAPC] D2_APC_3: 0x0
9934 22:13:13.775770 INFO: [APUAPC] D3_APC_0: 0xffffffff
9935 22:13:13.779647 INFO: [APUAPC] D3_APC_1: 0xffffffff
9936 22:13:13.782452 INFO: [APUAPC] D3_APC_2: 0x3fffff
9937 22:13:13.786764 INFO: [APUAPC] D3_APC_3: 0x0
9938 22:13:13.788767 INFO: [APUAPC] D4_APC_0: 0xffffffff
9939 22:13:13.792413 INFO: [APUAPC] D4_APC_1: 0xffffffff
9940 22:13:13.796015 INFO: [APUAPC] D4_APC_2: 0x3fffff
9941 22:13:13.799118 INFO: [APUAPC] D4_APC_3: 0x0
9942 22:13:13.802041 INFO: [APUAPC] D5_APC_0: 0xffffffff
9943 22:13:13.805789 INFO: [APUAPC] D5_APC_1: 0xffffffff
9944 22:13:13.808861 INFO: [APUAPC] D5_APC_2: 0x3fffff
9945 22:13:13.809434 INFO: [APUAPC] D5_APC_3: 0x0
9946 22:13:13.812096 INFO: [APUAPC] D6_APC_0: 0xffffffff
9947 22:13:13.819040 INFO: [APUAPC] D6_APC_1: 0xffffffff
9948 22:13:13.822505 INFO: [APUAPC] D6_APC_2: 0x3fffff
9949 22:13:13.823074 INFO: [APUAPC] D6_APC_3: 0x0
9950 22:13:13.825472 INFO: [APUAPC] D7_APC_0: 0xffffffff
9951 22:13:13.828719 INFO: [APUAPC] D7_APC_1: 0xffffffff
9952 22:13:13.832198 INFO: [APUAPC] D7_APC_2: 0x3fffff
9953 22:13:13.835310 INFO: [APUAPC] D7_APC_3: 0x0
9954 22:13:13.838391 INFO: [APUAPC] D8_APC_0: 0xffffffff
9955 22:13:13.841807 INFO: [APUAPC] D8_APC_1: 0xffffffff
9956 22:13:13.845157 INFO: [APUAPC] D8_APC_2: 0x3fffff
9957 22:13:13.848331 INFO: [APUAPC] D8_APC_3: 0x0
9958 22:13:13.851756 INFO: [APUAPC] D9_APC_0: 0xffffffff
9959 22:13:13.855314 INFO: [APUAPC] D9_APC_1: 0xffffffff
9960 22:13:13.858496 INFO: [APUAPC] D9_APC_2: 0x3fffff
9961 22:13:13.861555 INFO: [APUAPC] D9_APC_3: 0x0
9962 22:13:13.865142 INFO: [APUAPC] D10_APC_0: 0xffffffff
9963 22:13:13.868240 INFO: [APUAPC] D10_APC_1: 0xffffffff
9964 22:13:13.871765 INFO: [APUAPC] D10_APC_2: 0x3fffff
9965 22:13:13.875012 INFO: [APUAPC] D10_APC_3: 0x0
9966 22:13:13.878068 INFO: [APUAPC] D11_APC_0: 0xffffffff
9967 22:13:13.881470 INFO: [APUAPC] D11_APC_1: 0xffffffff
9968 22:13:13.884591 INFO: [APUAPC] D11_APC_2: 0x3fffff
9969 22:13:13.887804 INFO: [APUAPC] D11_APC_3: 0x0
9970 22:13:13.891523 INFO: [APUAPC] D12_APC_0: 0xffffffff
9971 22:13:13.895163 INFO: [APUAPC] D12_APC_1: 0xffffffff
9972 22:13:13.897870 INFO: [APUAPC] D12_APC_2: 0x3fffff
9973 22:13:13.900996 INFO: [APUAPC] D12_APC_3: 0x0
9974 22:13:13.905520 INFO: [APUAPC] D13_APC_0: 0xffffffff
9975 22:13:13.907888 INFO: [APUAPC] D13_APC_1: 0xffffffff
9976 22:13:13.911258 INFO: [APUAPC] D13_APC_2: 0x3fffff
9977 22:13:13.914814 INFO: [APUAPC] D13_APC_3: 0x0
9978 22:13:13.917997 INFO: [APUAPC] D14_APC_0: 0xffffffff
9979 22:13:13.924694 INFO: [APUAPC] D14_APC_1: 0xffffffff
9980 22:13:13.927731 INFO: [APUAPC] D14_APC_2: 0x3fffff
9981 22:13:13.928227 INFO: [APUAPC] D14_APC_3: 0x0
9982 22:13:13.934532 INFO: [APUAPC] D15_APC_0: 0xffffffff
9983 22:13:13.937328 INFO: [APUAPC] D15_APC_1: 0xffffffff
9984 22:13:13.940942 INFO: [APUAPC] D15_APC_2: 0x3fffff
9985 22:13:13.943822 INFO: [APUAPC] D15_APC_3: 0x0
9986 22:13:13.944296 INFO: [APUAPC] APC_CON: 0x4
9987 22:13:13.947490 INFO: [NOCDAPC] D0_APC_0: 0x0
9988 22:13:13.950826 INFO: [NOCDAPC] D0_APC_1: 0x0
9989 22:13:13.954008 INFO: [NOCDAPC] D1_APC_0: 0x0
9990 22:13:13.957463 INFO: [NOCDAPC] D1_APC_1: 0xfff
9991 22:13:13.960843 INFO: [NOCDAPC] D2_APC_0: 0x0
9992 22:13:13.964011 INFO: [NOCDAPC] D2_APC_1: 0xfff
9993 22:13:13.966969 INFO: [NOCDAPC] D3_APC_0: 0x0
9994 22:13:13.970418 INFO: [NOCDAPC] D3_APC_1: 0xfff
9995 22:13:13.970892 INFO: [NOCDAPC] D4_APC_0: 0x0
9996 22:13:13.974228 INFO: [NOCDAPC] D4_APC_1: 0xfff
9997 22:13:13.977030 INFO: [NOCDAPC] D5_APC_0: 0x0
9998 22:13:13.980165 INFO: [NOCDAPC] D5_APC_1: 0xfff
9999 22:13:13.983754 INFO: [NOCDAPC] D6_APC_0: 0x0
10000 22:13:13.986887 INFO: [NOCDAPC] D6_APC_1: 0xfff
10001 22:13:13.990078 INFO: [NOCDAPC] D7_APC_0: 0x0
10002 22:13:13.993855 INFO: [NOCDAPC] D7_APC_1: 0xfff
10003 22:13:13.997044 INFO: [NOCDAPC] D8_APC_0: 0x0
10004 22:13:13.999841 INFO: [NOCDAPC] D8_APC_1: 0xfff
10005 22:13:14.003972 INFO: [NOCDAPC] D9_APC_0: 0x0
10006 22:13:14.006822 INFO: [NOCDAPC] D9_APC_1: 0xfff
10007 22:13:14.010187 INFO: [NOCDAPC] D10_APC_0: 0x0
10008 22:13:14.010801 INFO: [NOCDAPC] D10_APC_1: 0xfff
10009 22:13:14.013828 INFO: [NOCDAPC] D11_APC_0: 0x0
10010 22:13:14.017102 INFO: [NOCDAPC] D11_APC_1: 0xfff
10011 22:13:14.020001 INFO: [NOCDAPC] D12_APC_0: 0x0
10012 22:13:14.023949 INFO: [NOCDAPC] D12_APC_1: 0xfff
10013 22:13:14.027320 INFO: [NOCDAPC] D13_APC_0: 0x0
10014 22:13:14.030113 INFO: [NOCDAPC] D13_APC_1: 0xfff
10015 22:13:14.033290 INFO: [NOCDAPC] D14_APC_0: 0x0
10016 22:13:14.036338 INFO: [NOCDAPC] D14_APC_1: 0xfff
10017 22:13:14.039981 INFO: [NOCDAPC] D15_APC_0: 0x0
10018 22:13:14.043253 INFO: [NOCDAPC] D15_APC_1: 0xfff
10019 22:13:14.046604 INFO: [NOCDAPC] APC_CON: 0x4
10020 22:13:14.050308 INFO: [APUAPC] set_apusys_apc done
10021 22:13:14.053015 INFO: [DEVAPC] devapc_init done
10022 22:13:14.056539 INFO: GICv3 without legacy support detected.
10023 22:13:14.059811 INFO: ARM GICv3 driver initialized in EL3
10024 22:13:14.063515 INFO: Maximum SPI INTID supported: 639
10025 22:13:14.066264 INFO: BL31: Initializing runtime services
10026 22:13:14.073549 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10027 22:13:14.076615 INFO: SPM: enable CPC mode
10028 22:13:14.082941 INFO: mcdi ready for mcusys-off-idle and system suspend
10029 22:13:14.086511 INFO: BL31: Preparing for EL3 exit to normal world
10030 22:13:14.089263 INFO: Entry point address = 0x80000000
10031 22:13:14.092978 INFO: SPSR = 0x8
10032 22:13:14.097603
10033 22:13:14.098160
10034 22:13:14.098572
10035 22:13:14.100709 Starting depthcharge on Spherion...
10036 22:13:14.101181
10037 22:13:14.101547 Wipe memory regions:
10038 22:13:14.101890
10039 22:13:14.104413 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10040 22:13:14.104986 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10041 22:13:14.105445 Setting prompt string to ['asurada:']
10042 22:13:14.105897 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10043 22:13:14.106655 [0x00000040000000, 0x00000054600000)
10044 22:13:14.226566
10045 22:13:14.227124 [0x00000054660000, 0x00000080000000)
10046 22:13:14.486484
10047 22:13:14.487052 [0x000000821a7280, 0x000000ffe64000)
10048 22:13:15.230419
10049 22:13:15.230986 [0x00000100000000, 0x00000240000000)
10050 22:13:17.116917
10051 22:13:17.119673 Initializing XHCI USB controller at 0x11200000.
10052 22:13:18.159245
10053 22:13:18.162516 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10054 22:13:18.163085
10055 22:13:18.163494
10056 22:13:18.163860
10057 22:13:18.164636 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10059 22:13:18.266093 asurada: tftpboot 192.168.201.1 10583875/tftp-deploy-v0ttru9s/kernel/image.itb 10583875/tftp-deploy-v0ttru9s/kernel/cmdline
10060 22:13:18.266813 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10061 22:13:18.267395 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10062 22:13:18.272458 tftpboot 192.168.201.1 10583875/tftp-deploy-v0ttru9s/kernel/image.itp-deploy-v0ttru9s/kernel/cmdline
10063 22:13:18.273047
10064 22:13:18.273534 Waiting for link
10065 22:13:18.432694
10066 22:13:18.433270 R8152: Initializing
10067 22:13:18.433754
10068 22:13:18.435961 Version 9 (ocp_data = 6010)
10069 22:13:18.436533
10070 22:13:18.438871 R8152: Done initializing
10071 22:13:18.439339
10072 22:13:18.439708 Adding net device
10073 22:13:20.380349
10074 22:13:20.380979 done.
10075 22:13:20.381418
10076 22:13:20.381777 MAC: 00:e0:4c:72:2d:d6
10077 22:13:20.382176
10078 22:13:20.383488 Sending DHCP discover... done.
10079 22:13:20.383957
10080 22:13:20.386659 Waiting for reply... done.
10081 22:13:20.387127
10082 22:13:20.390260 Sending DHCP request... done.
10083 22:13:20.390813
10084 22:13:20.391354 Waiting for reply... done.
10085 22:13:20.391733
10086 22:13:20.393699 My ip is 192.168.201.21
10087 22:13:20.394166
10088 22:13:20.396579 The DHCP server ip is 192.168.201.1
10089 22:13:20.397157
10090 22:13:20.399786 TFTP server IP predefined by user: 192.168.201.1
10091 22:13:20.400283
10092 22:13:20.407323 Bootfile predefined by user: 10583875/tftp-deploy-v0ttru9s/kernel/image.itb
10093 22:13:20.407975
10094 22:13:20.409592 Sending tftp read request... done.
10095 22:13:20.410059
10096 22:13:20.416991 Waiting for the transfer...
10097 22:13:20.417461
10098 22:13:20.820296 00000000 ################################################################
10099 22:13:20.820810
10100 22:13:21.194660 00080000 ################################################################
10101 22:13:21.195162
10102 22:13:21.462952 00100000 ################################################################
10103 22:13:21.463094
10104 22:13:21.714643 00180000 ################################################################
10105 22:13:21.714784
10106 22:13:22.006258 00200000 ################################################################
10107 22:13:22.006393
10108 22:13:22.296238 00280000 ################################################################
10109 22:13:22.296373
10110 22:13:22.566900 00300000 ################################################################
10111 22:13:22.567034
10112 22:13:22.840531 00380000 ################################################################
10113 22:13:22.840663
10114 22:13:23.092403 00400000 ################################################################
10115 22:13:23.092549
10116 22:13:23.370491 00480000 ################################################################
10117 22:13:23.370640
10118 22:13:23.624490 00500000 ################################################################
10119 22:13:23.624622
10120 22:13:23.887022 00580000 ################################################################
10121 22:13:23.887151
10122 22:13:24.135758 00600000 ################################################################
10123 22:13:24.135886
10124 22:13:24.385532 00680000 ################################################################
10125 22:13:24.385661
10126 22:13:24.655299 00700000 ################################################################
10127 22:13:24.655429
10128 22:13:24.920985 00780000 ################################################################
10129 22:13:24.921113
10130 22:13:25.211837 00800000 ################################################################
10131 22:13:25.211966
10132 22:13:25.481152 00880000 ################################################################
10133 22:13:25.481286
10134 22:13:25.747580 00900000 ################################################################
10135 22:13:25.747712
10136 22:13:26.044489 00980000 ################################################################
10137 22:13:26.044620
10138 22:13:26.340369 00a00000 ################################################################
10139 22:13:26.340507
10140 22:13:26.627732 00a80000 ################################################################
10141 22:13:26.627855
10142 22:13:26.911336 00b00000 ################################################################
10143 22:13:26.911466
10144 22:13:27.191283 00b80000 ################################################################
10145 22:13:27.191431
10146 22:13:27.488951 00c00000 ################################################################
10147 22:13:27.489082
10148 22:13:27.786596 00c80000 ################################################################
10149 22:13:27.786734
10150 22:13:28.084149 00d00000 ################################################################
10151 22:13:28.084279
10152 22:13:28.381779 00d80000 ################################################################
10153 22:13:28.381910
10154 22:13:28.680003 00e00000 ################################################################
10155 22:13:28.680134
10156 22:13:28.960065 00e80000 ################################################################
10157 22:13:28.960210
10158 22:13:29.220109 00f00000 ################################################################
10159 22:13:29.220233
10160 22:13:29.469621 00f80000 ################################################################
10161 22:13:29.469750
10162 22:13:29.719768 01000000 ################################################################
10163 22:13:29.719895
10164 22:13:29.970104 01080000 ################################################################
10165 22:13:29.970230
10166 22:13:30.220842 01100000 ################################################################
10167 22:13:30.220988
10168 22:13:30.478075 01180000 ################################################################
10169 22:13:30.478220
10170 22:13:30.734814 01200000 ################################################################
10171 22:13:30.734943
10172 22:13:30.988890 01280000 ################################################################
10173 22:13:30.989020
10174 22:13:31.263194 01300000 ################################################################
10175 22:13:31.263325
10176 22:13:31.513755 01380000 ################################################################
10177 22:13:31.513899
10178 22:13:31.764669 01400000 ################################################################
10179 22:13:31.764801
10180 22:13:32.013669 01480000 ################################################################
10181 22:13:32.013791
10182 22:13:32.263887 01500000 ################################################################
10183 22:13:32.264018
10184 22:13:32.540773 01580000 ################################################################
10185 22:13:32.540902
10186 22:13:32.800668 01600000 ################################################################
10187 22:13:32.800805
10188 22:13:33.096274 01680000 ################################################################
10189 22:13:33.096412
10190 22:13:33.380466 01700000 ################################################################
10191 22:13:33.380616
10192 22:13:33.769320 01780000 ################################################################
10193 22:13:33.769875
10194 22:13:34.145212 01800000 ################################################################
10195 22:13:34.145792
10196 22:13:34.540676 01880000 ################################################################
10197 22:13:34.541211
10198 22:13:34.913111 01900000 ################################################################
10199 22:13:34.913615
10200 22:13:35.275968 01980000 ################################################################
10201 22:13:35.276469
10202 22:13:35.654904 01a00000 ################################################################
10203 22:13:35.655415
10204 22:13:36.045449 01a80000 ################################################################
10205 22:13:36.046008
10206 22:13:36.426812 01b00000 ################################################################
10207 22:13:36.427320
10208 22:13:36.811344 01b80000 ################################################################
10209 22:13:36.811855
10210 22:13:37.192172 01c00000 ################################################################
10211 22:13:37.192727
10212 22:13:37.579692 01c80000 ################################################################
10213 22:13:37.580340
10214 22:13:37.978408 01d00000 ################################################################
10215 22:13:37.978975
10216 22:13:38.309613 01d80000 ################################################################
10217 22:13:38.309752
10218 22:13:38.575345 01e00000 ################################################################
10219 22:13:38.575473
10220 22:13:38.825588 01e80000 ################################################################
10221 22:13:38.825717
10222 22:13:39.113281 01f00000 ################################################################
10223 22:13:39.113408
10224 22:13:39.402628 01f80000 ################################################################
10225 22:13:39.402758
10226 22:13:39.668516 02000000 ################################################################
10227 22:13:39.668642
10228 22:13:39.965176 02080000 ################################################################
10229 22:13:39.965305
10230 22:13:40.261643 02100000 ################################################################
10231 22:13:40.261775
10232 22:13:40.522665 02180000 ################################################################
10233 22:13:40.522797
10234 22:13:40.771899 02200000 ################################################################
10235 22:13:40.772023
10236 22:13:41.022690 02280000 ################################################################
10237 22:13:41.022814
10238 22:13:41.274098 02300000 ################################################################
10239 22:13:41.274219
10240 22:13:41.526821 02380000 ################################################################
10241 22:13:41.526972
10242 22:13:41.800625 02400000 ################################################################
10243 22:13:41.800756
10244 22:13:42.093251 02480000 ################################################################
10245 22:13:42.093387
10246 22:13:42.387780 02500000 ################################################################
10247 22:13:42.387912
10248 22:13:42.684035 02580000 ################################################################
10249 22:13:42.684168
10250 22:13:42.966236 02600000 ################################################################
10251 22:13:42.966377
10252 22:13:43.221449 02680000 ################################################################
10253 22:13:43.221578
10254 22:13:43.471517 02700000 ################################################################
10255 22:13:43.471643
10256 22:13:43.732447 02780000 ################################################################
10257 22:13:43.732598
10258 22:13:44.029797 02800000 ################################################################
10259 22:13:44.029929
10260 22:13:44.323927 02880000 ################################################################
10261 22:13:44.324056
10262 22:13:44.621184 02900000 ################################################################
10263 22:13:44.621316
10264 22:13:44.918120 02980000 ################################################################
10265 22:13:44.918251
10266 22:13:45.211631 02a00000 ################################################################
10267 22:13:45.211758
10268 22:13:45.508223 02a80000 ################################################################
10269 22:13:45.508360
10270 22:13:45.787907 02b00000 ################################################################
10271 22:13:45.788035
10272 22:13:46.037720 02b80000 ################################################################
10273 22:13:46.037848
10274 22:13:46.326621 02c00000 ################################################################
10275 22:13:46.326744
10276 22:13:46.623411 02c80000 ################################################################
10277 22:13:46.623551
10278 22:13:46.923728 02d00000 ################################################################
10279 22:13:46.923865
10280 22:13:47.222214 02d80000 ################################################################
10281 22:13:47.222344
10282 22:13:47.489908 02e00000 ################################################################
10283 22:13:47.490040
10284 22:13:47.786421 02e80000 ################################################################
10285 22:13:47.786547
10286 22:13:48.046205 02f00000 ################################################################
10287 22:13:48.046339
10288 22:13:48.287511 02f80000 ######################################################### done.
10289 22:13:48.287636
10290 22:13:48.290899 The bootfile was 50266182 bytes long.
10291 22:13:48.291326
10292 22:13:48.294145 Sending tftp read request... done.
10293 22:13:48.294636
10294 22:13:48.295041 Waiting for the transfer...
10295 22:13:48.297699
10296 22:13:48.298116 00000000 # done.
10297 22:13:48.298513
10298 22:13:48.304526 Command line loaded dynamically from TFTP file: 10583875/tftp-deploy-v0ttru9s/kernel/cmdline
10299 22:13:48.305102
10300 22:13:48.317885 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10301 22:13:48.318495
10302 22:13:48.318877 Loading FIT.
10303 22:13:48.319224
10304 22:13:48.320519 Image ramdisk-1 has 40135494 bytes.
10305 22:13:48.320985
10306 22:13:48.324176 Image fdt-1 has 46924 bytes.
10307 22:13:48.324744
10308 22:13:48.327019 Image kernel-1 has 10081729 bytes.
10309 22:13:48.327485
10310 22:13:48.337721 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10311 22:13:48.338288
10312 22:13:48.353982 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10313 22:13:48.354587
10314 22:13:48.357312 Choosing best match conf-1 for compat google,spherion-rev2.
10315 22:13:48.363109
10316 22:13:48.367924 Connected to device vid:did:rid of 1ae0:0028:00
10317 22:13:48.374513
10318 22:13:48.377301 tpm_get_response: command 0x17b, return code 0x0
10319 22:13:48.377769
10320 22:13:48.380908 ec_init: CrosEC protocol v3 supported (256, 248)
10321 22:13:48.386726
10322 22:13:48.389864 tpm_cleanup: add release locality here.
10323 22:13:48.390463
10324 22:13:48.390885 Shutting down all USB controllers.
10325 22:13:48.392591
10326 22:13:48.393050 Removing current net device
10327 22:13:48.393444
10328 22:13:48.399709 Exiting depthcharge with code 4 at timestamp: 63649563
10329 22:13:48.400173
10330 22:13:48.402674 LZMA decompressing kernel-1 to 0x821a6718
10331 22:13:48.403140
10332 22:13:48.405791 LZMA decompressing kernel-1 to 0x40000000
10333 22:13:49.674326
10334 22:13:49.674982 jumping to kernel
10335 22:13:49.676523 end: 2.2.4 bootloader-commands (duration 00:00:36) [common]
10336 22:13:49.677059 start: 2.2.5 auto-login-action (timeout 00:03:50) [common]
10337 22:13:49.677472 Setting prompt string to ['Linux version [0-9]']
10338 22:13:49.677855 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10339 22:13:49.678234 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10340 22:13:49.756056
10341 22:13:49.759185 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10342 22:13:49.763103 start: 2.2.5.1 login-action (timeout 00:03:50) [common]
10343 22:13:49.763705 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10344 22:13:49.764168 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10345 22:13:49.764578 Using line separator: #'\n'#
10346 22:13:49.764945 No login prompt set.
10347 22:13:49.765322 Parsing kernel messages
10348 22:13:49.765649 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10349 22:13:49.766202 [login-action] Waiting for messages, (timeout 00:03:50)
10350 22:13:49.782324 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j1606555-arm64-gcc-10-defconfig-arm64-chromebook-vtq55) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sun Jun 4 21:56:05 UTC 2023
10351 22:13:49.785190 [ 0.000000] random: crng init done
10352 22:13:49.792051 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10353 22:13:49.792621 [ 0.000000] efi: UEFI not found.
10354 22:13:49.802082 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10355 22:13:49.808769 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10356 22:13:49.818509 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10357 22:13:49.828409 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10358 22:13:49.835010 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10359 22:13:49.841297 [ 0.000000] printk: bootconsole [mtk8250] enabled
10360 22:13:49.848747 [ 0.000000] NUMA: No NUMA configuration found
10361 22:13:49.855067 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10362 22:13:49.857855 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcda00-0x23efcffff]
10363 22:13:49.861468 [ 0.000000] Zone ranges:
10364 22:13:49.867698 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10365 22:13:49.871159 [ 0.000000] DMA32 empty
10366 22:13:49.877237 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10367 22:13:49.880609 [ 0.000000] Movable zone start for each node
10368 22:13:49.884108 [ 0.000000] Early memory node ranges
10369 22:13:49.890669 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10370 22:13:49.897620 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10371 22:13:49.903717 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10372 22:13:49.910598 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10373 22:13:49.917908 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10374 22:13:49.923420 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10375 22:13:49.979550 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10376 22:13:49.986075 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10377 22:13:49.992541 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10378 22:13:49.996464 [ 0.000000] psci: probing for conduit method from DT.
10379 22:13:50.002974 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10380 22:13:50.006565 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10381 22:13:50.012372 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10382 22:13:50.015523 [ 0.000000] psci: SMC Calling Convention v1.2
10383 22:13:50.022607 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10384 22:13:50.025978 [ 0.000000] Detected VIPT I-cache on CPU0
10385 22:13:50.032983 [ 0.000000] CPU features: detected: GIC system register CPU interface
10386 22:13:50.039311 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10387 22:13:50.046378 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10388 22:13:50.052404 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10389 22:13:50.061822 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10390 22:13:50.068891 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10391 22:13:50.072399 [ 0.000000] alternatives: applying boot alternatives
10392 22:13:50.078744 [ 0.000000] Fallback order for Node 0: 0
10393 22:13:50.085038 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10394 22:13:50.088573 [ 0.000000] Policy zone: Normal
10395 22:13:50.098308 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10396 22:13:50.111467 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10397 22:13:50.121985 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10398 22:13:50.131466 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10399 22:13:50.138235 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10400 22:13:50.141472 <6>[ 0.000000] software IO TLB: area num 8.
10401 22:13:50.198039 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10402 22:13:50.347289 <6>[ 0.000000] Memory: 7933744K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 419024K reserved, 32768K cma-reserved)
10403 22:13:50.354298 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10404 22:13:50.361125 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10405 22:13:50.364500 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10406 22:13:50.370566 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10407 22:13:50.377064 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10408 22:13:50.380199 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10409 22:13:50.389937 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10410 22:13:50.396948 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10411 22:13:50.403410 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10412 22:13:50.410408 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10413 22:13:50.413718 <6>[ 0.000000] GICv3: 608 SPIs implemented
10414 22:13:50.417033 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10415 22:13:50.423061 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10416 22:13:50.426815 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10417 22:13:50.433595 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10418 22:13:50.446424 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10419 22:13:50.456688 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10420 22:13:50.466740 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10421 22:13:50.474252 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10422 22:13:50.486807 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10423 22:13:50.493527 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10424 22:13:50.500508 <6>[ 0.009177] Console: colour dummy device 80x25
10425 22:13:50.509882 <6>[ 0.013907] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10426 22:13:50.516493 <6>[ 0.024350] pid_max: default: 32768 minimum: 301
10427 22:13:50.520290 <6>[ 0.029224] LSM: Security Framework initializing
10428 22:13:50.526944 <6>[ 0.034192] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10429 22:13:50.537015 <6>[ 0.042004] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10430 22:13:50.546220 <6>[ 0.051482] cblist_init_generic: Setting adjustable number of callback queues.
10431 22:13:50.550083 <6>[ 0.058935] cblist_init_generic: Setting shift to 3 and lim to 1.
10432 22:13:50.556337 <6>[ 0.065274] cblist_init_generic: Setting shift to 3 and lim to 1.
10433 22:13:50.563278 <6>[ 0.071682] rcu: Hierarchical SRCU implementation.
10434 22:13:50.570153 <6>[ 0.076726] rcu: Max phase no-delay instances is 1000.
10435 22:13:50.572765 <6>[ 0.083747] EFI services will not be available.
10436 22:13:50.579851 <6>[ 0.088752] smp: Bringing up secondary CPUs ...
10437 22:13:50.587209 <6>[ 0.093805] Detected VIPT I-cache on CPU1
10438 22:13:50.594015 <6>[ 0.093875] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10439 22:13:50.600427 <6>[ 0.093906] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10440 22:13:50.603309 <6>[ 0.094240] Detected VIPT I-cache on CPU2
10441 22:13:50.610494 <6>[ 0.094291] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10442 22:13:50.620047 <6>[ 0.094307] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10443 22:13:50.623710 <6>[ 0.094565] Detected VIPT I-cache on CPU3
10444 22:13:50.630239 <6>[ 0.094611] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10445 22:13:50.636845 <6>[ 0.094626] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10446 22:13:50.640201 <6>[ 0.094931] CPU features: detected: Spectre-v4
10447 22:13:50.646747 <6>[ 0.094937] CPU features: detected: Spectre-BHB
10448 22:13:50.650472 <6>[ 0.094943] Detected PIPT I-cache on CPU4
10449 22:13:50.657065 <6>[ 0.095000] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10450 22:13:50.663107 <6>[ 0.095017] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10451 22:13:50.669804 <6>[ 0.095319] Detected PIPT I-cache on CPU5
10452 22:13:50.676893 <6>[ 0.095381] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10453 22:13:50.682964 <6>[ 0.095398] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10454 22:13:50.686142 <6>[ 0.095682] Detected PIPT I-cache on CPU6
10455 22:13:50.692896 <6>[ 0.095746] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10456 22:13:50.699089 <6>[ 0.095763] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10457 22:13:50.705852 <6>[ 0.096060] Detected PIPT I-cache on CPU7
10458 22:13:50.712499 <6>[ 0.096124] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10459 22:13:50.718828 <6>[ 0.096140] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10460 22:13:50.722411 <6>[ 0.096187] smp: Brought up 1 node, 8 CPUs
10461 22:13:50.729157 <6>[ 0.237501] SMP: Total of 8 processors activated.
10462 22:13:50.732484 <6>[ 0.242422] CPU features: detected: 32-bit EL0 Support
10463 22:13:50.742072 <6>[ 0.247784] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10464 22:13:50.749585 <6>[ 0.256639] CPU features: detected: Common not Private translations
10465 22:13:50.755215 <6>[ 0.263115] CPU features: detected: CRC32 instructions
10466 22:13:50.762548 <6>[ 0.268499] CPU features: detected: RCpc load-acquire (LDAPR)
10467 22:13:50.765609 <6>[ 0.274495] CPU features: detected: LSE atomic instructions
10468 22:13:50.772038 <6>[ 0.280277] CPU features: detected: Privileged Access Never
10469 22:13:50.778322 <6>[ 0.286092] CPU features: detected: RAS Extension Support
10470 22:13:50.785208 <6>[ 0.291700] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10471 22:13:50.788809 <6>[ 0.298922] CPU: All CPU(s) started at EL2
10472 22:13:50.794793 <6>[ 0.303244] alternatives: applying system-wide alternatives
10473 22:13:50.804984 <6>[ 0.313946] devtmpfs: initialized
10474 22:13:50.820031 <6>[ 0.322712] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10475 22:13:50.827079 <6>[ 0.332676] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10476 22:13:50.833474 <6>[ 0.340880] pinctrl core: initialized pinctrl subsystem
10477 22:13:50.836985 <6>[ 0.347519] DMI not present or invalid.
10478 22:13:50.843529 <6>[ 0.351935] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10479 22:13:50.853386 <6>[ 0.358825] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10480 22:13:50.859728 <6>[ 0.366408] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10481 22:13:50.869963 <6>[ 0.374643] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10482 22:13:50.873199 <6>[ 0.382891] audit: initializing netlink subsys (disabled)
10483 22:13:50.883042 <5>[ 0.388592] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10484 22:13:50.889489 <6>[ 0.389302] thermal_sys: Registered thermal governor 'step_wise'
10485 22:13:50.895903 <6>[ 0.396558] thermal_sys: Registered thermal governor 'power_allocator'
10486 22:13:50.899474 <6>[ 0.402815] cpuidle: using governor menu
10487 22:13:50.906300 <6>[ 0.413782] NET: Registered PF_QIPCRTR protocol family
10488 22:13:50.912393 <6>[ 0.419299] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10489 22:13:50.918924 <6>[ 0.426404] ASID allocator initialised with 32768 entries
10490 22:13:50.922416 <6>[ 0.432968] Serial: AMBA PL011 UART driver
10491 22:13:50.932531 <4>[ 0.441614] Trying to register duplicate clock ID: 134
10492 22:13:50.986649 <6>[ 0.498829] KASLR enabled
10493 22:13:51.000634 <6>[ 0.506505] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10494 22:13:51.007595 <6>[ 0.513519] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10495 22:13:51.013612 <6>[ 0.520010] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10496 22:13:51.020641 <6>[ 0.527016] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10497 22:13:51.026805 <6>[ 0.533504] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10498 22:13:51.033763 <6>[ 0.540509] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10499 22:13:51.040240 <6>[ 0.546999] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10500 22:13:51.046613 <6>[ 0.554004] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10501 22:13:51.049812 <6>[ 0.561484] ACPI: Interpreter disabled.
10502 22:13:51.058918 <6>[ 0.567917] iommu: Default domain type: Translated
10503 22:13:51.065678 <6>[ 0.573030] iommu: DMA domain TLB invalidation policy: strict mode
10504 22:13:51.068859 <5>[ 0.579689] SCSI subsystem initialized
10505 22:13:51.075821 <6>[ 0.583927] usbcore: registered new interface driver usbfs
10506 22:13:51.082200 <6>[ 0.589657] usbcore: registered new interface driver hub
10507 22:13:51.085510 <6>[ 0.595209] usbcore: registered new device driver usb
10508 22:13:51.092402 <6>[ 0.601311] pps_core: LinuxPPS API ver. 1 registered
10509 22:13:51.102331 <6>[ 0.606505] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10510 22:13:51.106643 <6>[ 0.615851] PTP clock support registered
10511 22:13:51.108840 <6>[ 0.620090] EDAC MC: Ver: 3.0.0
10512 22:13:51.116205 <6>[ 0.625277] FPGA manager framework
10513 22:13:51.123114 <6>[ 0.628956] Advanced Linux Sound Architecture Driver Initialized.
10514 22:13:51.126558 <6>[ 0.635716] vgaarb: loaded
10515 22:13:51.132531 <6>[ 0.638888] clocksource: Switched to clocksource arch_sys_counter
10516 22:13:51.135731 <5>[ 0.645344] VFS: Disk quotas dquot_6.6.0
10517 22:13:51.142556 <6>[ 0.649533] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10518 22:13:51.145725 <6>[ 0.656727] pnp: PnP ACPI: disabled
10519 22:13:51.154223 <6>[ 0.663455] NET: Registered PF_INET protocol family
10520 22:13:51.164251 <6>[ 0.669050] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10521 22:13:51.175285 <6>[ 0.681370] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10522 22:13:51.185582 <6>[ 0.690188] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10523 22:13:51.192387 <6>[ 0.698158] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10524 22:13:51.202262 <6>[ 0.706859] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10525 22:13:51.208502 <6>[ 0.716598] TCP: Hash tables configured (established 65536 bind 65536)
10526 22:13:51.215456 <6>[ 0.723396] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10527 22:13:51.225146 <6>[ 0.730596] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10528 22:13:51.231022 <6>[ 0.738294] NET: Registered PF_UNIX/PF_LOCAL protocol family
10529 22:13:51.238103 <6>[ 0.744458] RPC: Registered named UNIX socket transport module.
10530 22:13:51.241167 <6>[ 0.750614] RPC: Registered udp transport module.
10531 22:13:51.247546 <6>[ 0.755549] RPC: Registered tcp transport module.
10532 22:13:51.254378 <6>[ 0.760481] RPC: Registered tcp NFSv4.1 backchannel transport module.
10533 22:13:51.258308 <6>[ 0.767153] PCI: CLS 0 bytes, default 64
10534 22:13:51.260589 <6>[ 0.771533] Unpacking initramfs...
10535 22:13:51.285009 <6>[ 0.790997] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10536 22:13:51.294981 <6>[ 0.799666] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10537 22:13:51.298628 <6>[ 0.808509] kvm [1]: IPA Size Limit: 40 bits
10538 22:13:51.305658 <6>[ 0.813037] kvm [1]: GICv3: no GICV resource entry
10539 22:13:51.308865 <6>[ 0.818058] kvm [1]: disabling GICv2 emulation
10540 22:13:51.314891 <6>[ 0.822744] kvm [1]: GIC system register CPU interface enabled
10541 22:13:51.318477 <6>[ 0.828917] kvm [1]: vgic interrupt IRQ18
10542 22:13:51.325006 <6>[ 0.833273] kvm [1]: VHE mode initialized successfully
10543 22:13:51.331567 <5>[ 0.839665] Initialise system trusted keyrings
10544 22:13:51.337942 <6>[ 0.844478] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10545 22:13:51.345511 <6>[ 0.854644] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10546 22:13:51.352049 <5>[ 0.861012] NFS: Registering the id_resolver key type
10547 22:13:51.355407 <5>[ 0.866313] Key type id_resolver registered
10548 22:13:51.362650 <5>[ 0.870731] Key type id_legacy registered
10549 22:13:51.369603 <6>[ 0.875008] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10550 22:13:51.374905 <6>[ 0.881930] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10551 22:13:51.381778 <6>[ 0.889639] 9p: Installing v9fs 9p2000 file system support
10552 22:13:51.418122 <5>[ 0.927141] Key type asymmetric registered
10553 22:13:51.421507 <5>[ 0.931472] Asymmetric key parser 'x509' registered
10554 22:13:51.431270 <6>[ 0.936614] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10555 22:13:51.434440 <6>[ 0.944228] io scheduler mq-deadline registered
10556 22:13:51.437746 <6>[ 0.949005] io scheduler kyber registered
10557 22:13:51.456672 <6>[ 0.965751] EINJ: ACPI disabled.
10558 22:13:51.488510 <4>[ 0.990901] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10559 22:13:51.498069 <4>[ 1.001528] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10560 22:13:51.513046 <6>[ 1.022189] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10561 22:13:51.520844 <6>[ 1.030138] printk: console [ttyS0] disabled
10562 22:13:51.548779 <6>[ 1.054785] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10563 22:13:51.555469 <6>[ 1.064278] printk: console [ttyS0] enabled
10564 22:13:51.558805 <6>[ 1.064278] printk: console [ttyS0] enabled
10565 22:13:51.565159 <6>[ 1.073173] printk: bootconsole [mtk8250] disabled
10566 22:13:51.568369 <6>[ 1.073173] printk: bootconsole [mtk8250] disabled
10567 22:13:51.575514 <6>[ 1.084390] SuperH (H)SCI(F) driver initialized
10568 22:13:51.578522 <6>[ 1.089655] msm_serial: driver initialized
10569 22:13:51.592802 <6>[ 1.098551] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10570 22:13:51.602776 <6>[ 1.107097] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10571 22:13:51.609426 <6>[ 1.115638] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10572 22:13:51.618835 <6>[ 1.124270] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10573 22:13:51.629576 <6>[ 1.132977] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10574 22:13:51.635362 <6>[ 1.141689] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10575 22:13:51.645470 <6>[ 1.150229] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10576 22:13:51.652117 <6>[ 1.159024] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10577 22:13:51.662196 <6>[ 1.167567] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10578 22:13:51.673799 <6>[ 1.183090] loop: module loaded
10579 22:13:51.680311 <6>[ 1.189106] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10580 22:13:51.703815 <4>[ 1.212330] mtk-pmic-keys: Failed to locate of_node [id: -1]
10581 22:13:51.709897 <6>[ 1.219104] megasas: 07.719.03.00-rc1
10582 22:13:51.719340 <6>[ 1.228463] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10583 22:13:51.729424 <6>[ 1.238285] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10584 22:13:51.745768 <6>[ 1.254958] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10585 22:13:51.806272 <6>[ 1.308986] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10586 22:13:52.882416 <6>[ 2.391788] Freeing initrd memory: 39192K
10587 22:13:52.892592 <6>[ 2.402284] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10588 22:13:52.903665 <6>[ 2.413135] tun: Universal TUN/TAP device driver, 1.6
10589 22:13:52.906820 <6>[ 2.419193] thunder_xcv, ver 1.0
10590 22:13:52.910144 <6>[ 2.422691] thunder_bgx, ver 1.0
10591 22:13:52.914722 <6>[ 2.426188] nicpf, ver 1.0
10592 22:13:52.923992 <6>[ 2.430180] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10593 22:13:52.927128 <6>[ 2.437655] hns3: Copyright (c) 2017 Huawei Corporation.
10594 22:13:52.934058 <6>[ 2.443243] hclge is initializing
10595 22:13:52.937253 <6>[ 2.446815] e1000: Intel(R) PRO/1000 Network Driver
10596 22:13:52.943885 <6>[ 2.451945] e1000: Copyright (c) 1999-2006 Intel Corporation.
10597 22:13:52.947027 <6>[ 2.457958] e1000e: Intel(R) PRO/1000 Network Driver
10598 22:13:52.954108 <6>[ 2.463174] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10599 22:13:52.960862 <6>[ 2.469358] igb: Intel(R) Gigabit Ethernet Network Driver
10600 22:13:52.967273 <6>[ 2.475008] igb: Copyright (c) 2007-2014 Intel Corporation.
10601 22:13:52.973910 <6>[ 2.480845] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10602 22:13:52.981821 <6>[ 2.487362] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10603 22:13:52.983498 <6>[ 2.493819] sky2: driver version 1.30
10604 22:13:52.989830 <6>[ 2.498789] VFIO - User Level meta-driver version: 0.3
10605 22:13:52.997338 <6>[ 2.506916] usbcore: registered new interface driver usb-storage
10606 22:13:53.004155 <6>[ 2.513355] usbcore: registered new device driver onboard-usb-hub
10607 22:13:53.013095 <6>[ 2.522369] mt6397-rtc mt6359-rtc: registered as rtc0
10608 22:13:53.023295 <6>[ 2.527833] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-04T22:14:05 UTC (1685916845)
10609 22:13:53.026031 <6>[ 2.537387] i2c_dev: i2c /dev entries driver
10610 22:13:53.043105 <6>[ 2.549049] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10611 22:13:53.050282 <6>[ 2.559243] sdhci: Secure Digital Host Controller Interface driver
10612 22:13:53.056445 <6>[ 2.565681] sdhci: Copyright(c) Pierre Ossman
10613 22:13:53.063189 <6>[ 2.571079] Synopsys Designware Multimedia Card Interface Driver
10614 22:13:53.066908 <6>[ 2.577697] mmc0: CQHCI version 5.10
10615 22:13:53.073558 <6>[ 2.578255] sdhci-pltfm: SDHCI platform and OF driver helper
10616 22:13:53.080226 <6>[ 2.589569] ledtrig-cpu: registered to indicate activity on CPUs
10617 22:13:53.091094 <6>[ 2.596940] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10618 22:13:53.097904 <6>[ 2.604339] usbcore: registered new interface driver usbhid
10619 22:13:53.100911 <6>[ 2.610166] usbhid: USB HID core driver
10620 22:13:53.107394 <6>[ 2.614405] spi_master spi0: will run message pump with realtime priority
10621 22:13:53.151624 <6>[ 2.654612] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10622 22:13:53.170846 <6>[ 2.669682] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10623 22:13:53.173707 <6>[ 2.683255] mmc0: Command Queue Engine enabled
10624 22:13:53.180940 <6>[ 2.685481] cros-ec-spi spi0.0: Chrome EC device registered
10625 22:13:53.187475 <6>[ 2.688014] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10626 22:13:53.190896 <6>[ 2.700957] mmcblk0: mmc0:0001 DA4128 116 GiB
10627 22:13:53.200944 <6>[ 2.710598] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10628 22:13:53.211173 <6>[ 2.711209] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10629 22:13:53.217445 <6>[ 2.717928] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10630 22:13:53.221130 <6>[ 2.727912] NET: Registered PF_PACKET protocol family
10631 22:13:53.227373 <6>[ 2.731726] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10632 22:13:53.231003 <6>[ 2.736461] 9pnet: Installing 9P2000 support
10633 22:13:53.238141 <6>[ 2.742217] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10634 22:13:53.244456 <5>[ 2.746145] Key type dns_resolver registered
10635 22:13:53.247354 <6>[ 2.757645] registered taskstats version 1
10636 22:13:53.254528 <5>[ 2.762035] Loading compiled-in X.509 certificates
10637 22:13:53.287096 <4>[ 2.789723] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10638 22:13:53.297397 <4>[ 2.800411] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10639 22:13:53.306819 <3>[ 2.813123] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10640 22:13:53.319512 <6>[ 2.828690] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10641 22:13:53.326134 <6>[ 2.835465] xhci-mtk 11200000.usb: xHCI Host Controller
10642 22:13:53.332492 <6>[ 2.840971] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10643 22:13:53.342874 <6>[ 2.848830] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10644 22:13:53.349848 <6>[ 2.858284] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10645 22:13:53.356005 <6>[ 2.864376] xhci-mtk 11200000.usb: xHCI Host Controller
10646 22:13:53.362577 <6>[ 2.869862] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10647 22:13:53.369601 <6>[ 2.877521] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10648 22:13:53.376143 <6>[ 2.885198] hub 1-0:1.0: USB hub found
10649 22:13:53.379539 <6>[ 2.889218] hub 1-0:1.0: 1 port detected
10650 22:13:53.389330 <6>[ 2.893559] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10651 22:13:53.392177 <6>[ 2.902266] hub 2-0:1.0: USB hub found
10652 22:13:53.395433 <6>[ 2.906307] hub 2-0:1.0: 1 port detected
10653 22:13:53.404347 <6>[ 2.913662] mtk-msdc 11f70000.mmc: Got CD GPIO
10654 22:13:53.420587 <6>[ 2.926970] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10655 22:13:53.427173 <6>[ 2.934992] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10656 22:13:53.437662 <4>[ 2.942973] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10657 22:13:53.446964 <6>[ 2.952632] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10658 22:13:53.453802 <6>[ 2.960715] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10659 22:13:53.463766 <6>[ 2.968738] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10660 22:13:53.470892 <6>[ 2.976653] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10661 22:13:53.476705 <6>[ 2.984473] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10662 22:13:53.486639 <6>[ 2.992294] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10663 22:13:53.496887 <6>[ 3.002771] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10664 22:13:53.506671 <6>[ 3.011178] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10665 22:13:53.513642 <6>[ 3.019534] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10666 22:13:53.523252 <6>[ 3.027878] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10667 22:13:53.529525 <6>[ 3.036222] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10668 22:13:53.539706 <6>[ 3.044565] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10669 22:13:53.545981 <6>[ 3.052908] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10670 22:13:53.556299 <6>[ 3.061251] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10671 22:13:53.562630 <6>[ 3.069593] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10672 22:13:53.572984 <6>[ 3.077936] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10673 22:13:53.579347 <6>[ 3.086279] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10674 22:13:53.589563 <6>[ 3.094629] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10675 22:13:53.595765 <6>[ 3.102974] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10676 22:13:53.605674 <6>[ 3.111320] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10677 22:13:53.612339 <6>[ 3.119666] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10678 22:13:53.619189 <6>[ 3.128598] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10679 22:13:53.627014 <6>[ 3.136091] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10680 22:13:53.633710 <6>[ 3.143212] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10681 22:13:53.644026 <6>[ 3.150380] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10682 22:13:53.650805 <6>[ 3.157722] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10683 22:13:53.660833 <6>[ 3.164639] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10684 22:13:53.667213 <6>[ 3.173780] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10685 22:13:53.677401 <6>[ 3.182908] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10686 22:13:53.687689 <6>[ 3.192212] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10687 22:13:53.696831 <6>[ 3.201687] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10688 22:13:53.707204 <6>[ 3.211161] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10689 22:13:53.717473 <6>[ 3.220287] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10690 22:13:53.723850 <6>[ 3.229769] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10691 22:13:53.733628 <6>[ 3.238906] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10692 22:13:53.743144 <6>[ 3.248209] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10693 22:13:53.753164 <6>[ 3.258376] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10694 22:13:53.763622 <6>[ 3.269835] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10695 22:13:53.784860 <6>[ 3.291158] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10696 22:13:53.812450 <6>[ 3.321549] hub 2-1:1.0: USB hub found
10697 22:13:53.815443 <6>[ 3.325961] hub 2-1:1.0: 3 ports detected
10698 22:13:53.937660 <6>[ 3.443094] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10699 22:13:54.091522 <6>[ 3.600905] hub 1-1:1.0: USB hub found
10700 22:13:54.094659 <6>[ 3.605397] hub 1-1:1.0: 4 ports detected
10701 22:13:54.169333 <6>[ 3.675405] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10702 22:13:54.416536 <6>[ 3.923160] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10703 22:13:54.550000 <6>[ 4.059299] hub 1-1.4:1.0: USB hub found
10704 22:13:54.553232 <6>[ 4.063955] hub 1-1.4:1.0: 2 ports detected
10705 22:13:54.848960 <6>[ 4.355159] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10706 22:13:55.041142 <6>[ 4.547161] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10707 22:14:06.049788 <6>[ 15.563721] ALSA device list:
10708 22:14:06.056107 <6>[ 15.566978] No soundcards found.
10709 22:14:06.068561 <6>[ 15.579395] Freeing unused kernel memory: 8384K
10710 22:14:06.071670 <6>[ 15.584326] Run /init as init process
10711 22:14:06.102334 <6>[ 15.613115] NET: Registered PF_INET6 protocol family
10712 22:14:06.108581 <6>[ 15.619408] Segment Routing with IPv6
10713 22:14:06.111917 <6>[ 15.623354] In-situ OAM (IOAM) with IPv6
10714 22:14:06.147130 <30>[ 15.637808] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10715 22:14:06.150005 <30>[ 15.661675] systemd[1]: Detected architecture arm64.
10716 22:14:06.153670
10717 22:14:06.156636 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10718 22:14:06.157201
10719 22:14:06.172275 <30>[ 15.683291] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10720 22:14:06.333194 <30>[ 15.840829] systemd[1]: Queued start job for default target Graphical Interface.
10721 22:14:06.378709 <30>[ 15.888464] systemd[1]: Created slice system-getty.slice.
10722 22:14:06.384258 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10723 22:14:06.400648 <30>[ 15.911756] systemd[1]: Created slice system-modprobe.slice.
10724 22:14:06.407973 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10725 22:14:06.425140 <30>[ 15.935631] systemd[1]: Created slice system-serial\x2dgetty.slice.
10726 22:14:06.434635 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10727 22:14:06.449495 <30>[ 15.960235] systemd[1]: Created slice User and Session Slice.
10728 22:14:06.455759 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10729 22:14:06.476576 <30>[ 15.983690] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10730 22:14:06.486141 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10731 22:14:06.504229 <30>[ 16.011692] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10732 22:14:06.510758 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10733 22:14:06.531100 <30>[ 16.035273] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10734 22:14:06.537960 <30>[ 16.047308] systemd[1]: Reached target Local Encrypted Volumes.
10735 22:14:06.544234 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10736 22:14:06.560979 <30>[ 16.071520] systemd[1]: Reached target Paths.
10737 22:14:06.564431 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10738 22:14:06.580263 <30>[ 16.091205] systemd[1]: Reached target Remote File Systems.
10739 22:14:06.586959 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10740 22:14:06.600399 <30>[ 16.111191] systemd[1]: Reached target Slices.
10741 22:14:06.603617 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10742 22:14:06.622239 <30>[ 16.131207] systemd[1]: Reached target Swap.
10743 22:14:06.623581 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10744 22:14:06.643934 <30>[ 16.151499] systemd[1]: Listening on initctl Compatibility Named Pipe.
10745 22:14:06.650480 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10746 22:14:06.656995 <30>[ 16.166234] systemd[1]: Listening on Journal Audit Socket.
10747 22:14:06.663440 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10748 22:14:06.676932 <30>[ 16.187457] systemd[1]: Listening on Journal Socket (/dev/log).
10749 22:14:06.683057 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10750 22:14:06.700692 <30>[ 16.211478] systemd[1]: Listening on Journal Socket.
10751 22:14:06.707324 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10752 22:14:06.723957 <30>[ 16.231509] systemd[1]: Listening on Network Service Netlink Socket.
10753 22:14:06.730446 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10754 22:14:06.745155 <30>[ 16.255939] systemd[1]: Listening on udev Control Socket.
10755 22:14:06.752021 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10756 22:14:06.769209 <30>[ 16.279879] systemd[1]: Listening on udev Kernel Socket.
10757 22:14:06.775714 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10758 22:14:06.812965 <30>[ 16.323395] systemd[1]: Mounting Huge Pages File System...
10759 22:14:06.818804 Mounting [0;1;39mHuge Pages File System[0m...
10760 22:14:06.834511 <30>[ 16.345073] systemd[1]: Mounting POSIX Message Queue File System...
10761 22:14:06.841821 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10762 22:14:06.858751 <30>[ 16.369268] systemd[1]: Mounting Kernel Debug File System...
10763 22:14:06.865145 Mounting [0;1;39mKernel Debug File System[0m...
10764 22:14:06.883584 <30>[ 16.391401] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10765 22:14:06.894847 <30>[ 16.402295] systemd[1]: Starting Create list of static device nodes for the current kernel...
10766 22:14:06.901284 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10767 22:14:06.918836 <30>[ 16.429346] systemd[1]: Starting Load Kernel Module configfs...
10768 22:14:06.925312 Starting [0;1;39mLoad Kernel Module configfs[0m...
10769 22:14:06.942797 <30>[ 16.453356] systemd[1]: Starting Load Kernel Module drm...
10770 22:14:06.949651 Starting [0;1;39mLoad Kernel Module drm[0m...
10771 22:14:06.967722 <30>[ 16.475333] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10772 22:14:06.996751 <30>[ 16.507659] systemd[1]: Starting Journal Service...
10773 22:14:06.999949 Starting [0;1;39mJournal Service[0m...
10774 22:14:07.019038 <30>[ 16.529805] systemd[1]: Starting Load Kernel Modules...
10775 22:14:07.025886 Starting [0;1;39mLoad Kernel Modules[0m...
10776 22:14:07.046484 <30>[ 16.553762] systemd[1]: Starting Remount Root and Kernel File Systems...
10777 22:14:07.052621 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10778 22:14:07.070874 <30>[ 16.581779] systemd[1]: Starting Coldplug All udev Devices...
10779 22:14:07.077428 Starting [0;1;39mColdplug All udev Devices[0m...
10780 22:14:07.099734 <30>[ 16.610430] systemd[1]: Started Journal Service.
10781 22:14:07.105950 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10782 22:14:07.126284 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10783 22:14:07.145156 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10784 22:14:07.161239 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10785 22:14:07.181290 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10786 22:14:07.198845 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10787 22:14:07.214609 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10788 22:14:07.229383 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10789 22:14:07.249634 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10790 22:14:07.264573 See 'systemctl status systemd-remount-fs.service' for details.
10791 22:14:07.317491 Mounting [0;1;39mKernel Configuration File System[0m...
10792 22:14:07.335847 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10793 22:14:07.351745 <46>[ 16.859191] systemd-journald[184]: Received client request to flush runtime journal.
10794 22:14:07.360719 Starting [0;1;39mLoad/Save Random Seed[0m...
10795 22:14:07.379809 Starting [0;1;39mApply Kernel Variables[0m...
10796 22:14:07.396065 Starting [0;1;39mCreate System Users[0m...
10797 22:14:07.413613 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10798 22:14:07.432769 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10799 22:14:07.445227 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10800 22:14:07.461361 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10801 22:14:07.477758 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10802 22:14:07.493434 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10803 22:14:07.549494 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10804 22:14:07.572851 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10805 22:14:07.588760 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10806 22:14:07.604616 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10807 22:14:07.636717 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10808 22:14:07.664188 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10809 22:14:07.685243 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10810 22:14:07.705356 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10811 22:14:07.762094 Starting [0;1;39mNetwork Service[0m...
10812 22:14:07.786157 Starting [0;1;39mNetwork Time Synchronization[0m...
10813 22:14:07.803243 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10814 22:14:07.843237 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10815 22:14:07.856658 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10816 22:14:07.903702 [[0;32m OK [0m] Created slic<6>[ 17.410467] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10817 22:14:07.906637 e [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10818 22:14:07.920723 <3>[ 17.428157] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10819 22:14:07.927677 <3>[ 17.436351] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10820 22:14:07.936732 <3>[ 17.444451] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10821 22:14:07.940487 <6>[ 17.445077] remoteproc remoteproc0: scp is available
10822 22:14:07.949979 <6>[ 17.453612] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10823 22:14:07.953339 <6>[ 17.458493] remoteproc remoteproc0: powering up scp
10824 22:14:07.963251 <6>[ 17.465937] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10825 22:14:07.973204 <6>[ 17.470575] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10826 22:14:07.976539 <6>[ 17.470604] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10827 22:14:07.986931 <6>[ 17.479399] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10828 22:14:07.993194 <3>[ 17.497138] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10829 22:14:08.005002 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10830 22:14:08.015249 <3>[ 17.523075] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10831 22:14:08.022726 <3>[ 17.531442] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10832 22:14:08.031971 <3>[ 17.539662] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10833 22:14:08.038437 <4>[ 17.540100] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10834 22:14:08.048685 <3>[ 17.547756] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10835 22:14:08.055175 <3>[ 17.552572] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10836 22:14:08.058607 <6>[ 17.559381] mc: Linux media interface: v0.10
10837 22:14:08.068334 <4>[ 17.563341] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10838 22:14:08.075006 <3>[ 17.573439] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10839 22:14:08.084921 <3>[ 17.591367] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10840 22:14:08.091296 <3>[ 17.591390] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10841 22:14:08.098132 <3>[ 17.591572] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10842 22:14:08.108898 <6>[ 17.593413] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10843 22:14:08.114496 Startin<6>[ 17.613343] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10844 22:14:08.124874 g [0;1;39mNetwo<6>[ 17.615762] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10845 22:14:08.134438 rk Name Resoluti<3>[ 17.615770] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10846 22:14:08.137844 on[0m...
10847 22:14:08.141000 <6>[ 17.615778] remoteproc remoteproc0: remote processor scp is now up
10848 22:14:08.151562 <3>[ 17.615786] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10849 22:14:08.158515 <3>[ 17.615804] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10850 22:14:08.167796 <3>[ 17.615813] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10851 22:14:08.174609 <3>[ 17.632748] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10852 22:14:08.181448 <6>[ 17.642411] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10853 22:14:08.191343 <4>[ 17.651236] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10854 22:14:08.194751 <4>[ 17.651236] Fallback method does not support PEC.
10855 22:14:08.201126 <6>[ 17.662222] usbcore: registered new interface driver r8152
10856 22:14:08.207704 <6>[ 17.666954] pci_bus 0000:00: root bus resource [bus 00-ff]
10857 22:14:08.214410 <3>[ 17.675199] elants_i2c 4-0010: invalid 'hello' packet: ff ff ff ff
10858 22:14:08.220664 <6>[ 17.683053] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10859 22:14:08.231160 <3>[ 17.702343] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10860 22:14:08.240721 <6>[ 17.713161] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10861 22:14:08.247257 <6>[ 17.747214] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10862 22:14:08.254005 <6>[ 17.755681] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10863 22:14:08.261211 <6>[ 17.764091] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10864 22:14:08.267513 <6>[ 17.769297] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10865 22:14:08.278126 <6>[ 17.771274] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10866 22:14:08.288419 <6>[ 17.771645] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10867 22:14:08.298295 <6>[ 17.779236] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10868 22:14:08.304627 <4>[ 17.781915] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10869 22:14:08.314385 <4>[ 17.781924] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10870 22:14:08.317685 <6>[ 17.785181] pci 0000:00:00.0: supports D1 D2
10871 22:14:08.327598 <3>[ 17.790938] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10872 22:14:08.334777 <3>[ 17.791190] elants_i2c 4-0010: invalid 'hello' packet: ff ff ff ff
10873 22:14:08.342111 <3>[ 17.791839] power_supply sbs-5-000b: driver failed to report `temp' property: -6
10874 22:14:08.348368 <3>[ 17.814493] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10875 22:14:08.357948 <6>[ 17.821296] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10876 22:14:08.364770 <6>[ 17.823220] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10877 22:14:08.367873 <6>[ 17.850951] r8152 2-1.3:1.0 eth0: v1.12.13
10878 22:14:08.374465 <6>[ 17.856901] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10879 22:14:08.384516 <3>[ 17.865736] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10880 22:14:08.391053 <6>[ 17.872435] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10881 22:14:08.398159 <3>[ 17.895056] elants_i2c 4-0010: invalid 'hello' packet: ff ff ff ff
10882 22:14:08.404475 <6>[ 17.900093] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10883 22:14:08.411084 <3>[ 17.907830] elants_i2c 4-0010: (read fw id) unexpected response: ff ff
10884 22:14:08.421426 <6>[ 17.913983] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10885 22:14:08.427993 <6>[ 17.921569] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10886 22:14:08.434929 <6>[ 17.928343] pci 0000:01:00.0: supports D1 D2
10887 22:14:08.441386 <3>[ 17.949788] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10888 22:14:08.448193 <6>[ 17.950718] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10889 22:14:08.457912 [[0;32m OK [<6>[ 17.951641] videodev: Linux video capture interface: v2.00
10890 22:14:08.465528 0m] Started [0;1;39mNetwork Tim<6>[ 17.974869] Bluetooth: Core ver 2.22
10891 22:14:08.471275 e Synchronizatio<6>[ 17.979487] NET: Registered PF_BLUETOOTH protocol family
10892 22:14:08.471842 n[0m.
10893 22:14:08.478032 <6>[ 17.980075] usbcore: registered new interface driver cdc_ether
10894 22:14:08.484423 <6>[ 17.986318] Bluetooth: HCI device and connection manager initialized
10895 22:14:08.487691 <6>[ 17.986353] Bluetooth: HCI socket layer initialized
10896 22:14:08.494527 <6>[ 17.986366] Bluetooth: L2CAP socket layer initialized
10897 22:14:08.497818 <6>[ 17.986381] Bluetooth: SCO socket layer initialized
10898 22:14:08.507599 <6>[ 17.986469] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10899 22:14:08.510996 <6>[ 18.000242] usbcore: registered new interface driver r8153_ecm
10900 22:14:08.520723 <6>[ 18.004946] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10901 22:14:08.527160 <6>[ 18.011818] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10902 22:14:08.534435 <6>[ 18.015354] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10903 22:14:08.545767 <6>[ 18.015370] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10904 22:14:08.552119 <6>[ 18.015388] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10905 22:14:08.559137 <6>[ 18.015405] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10906 22:14:08.572141 <6>[ 18.024749] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10907 22:14:08.578590 <6>[ 18.025112] r8152 2-1.3:1.0 enx00e04c722dd6: renamed from eth0
10908 22:14:08.582134 <6>[ 18.028360] pci 0000:00:00.0: PCI bridge to [bus 01]
10909 22:14:08.588406 <6>[ 18.036687] usbcore: registered new interface driver uvcvideo
10910 22:14:08.594693 <6>[ 18.037387] usbcore: registered new interface driver btusb
10911 22:14:08.604916 <4>[ 18.038218] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10912 22:14:08.611176 <3>[ 18.038234] Bluetooth: hci0: Failed to load firmware file (-2)
10913 22:14:08.617898 <3>[ 18.038239] Bluetooth: hci0: Failed to set up firmware (-2)
10914 22:14:08.627818 <4>[ 18.038243] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10915 22:14:08.634426 <6>[ 18.038300] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10916 22:14:08.640929 <6>[ 18.043490] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10917 22:14:08.647774 <6>[ 18.043709] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10918 22:14:08.658313 <3>[ 18.058953] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10919 22:14:08.667601 <3>[ 18.059765] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10920 22:14:08.670799 <6>[ 18.060396] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10921 22:14:08.681713 <3>[ 18.060540] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10922 22:14:08.687529 <6>[ 18.060669] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10923 22:14:08.693819 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10924 22:14:08.718229 [[0;32m OK [0m] Finished [0<5>[ 18.224149] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10925 22:14:08.728105 ;1;39mLoad/Save <3>[ 18.234530] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10926 22:14:08.737812 Screen …s of leds:white:kbd_ba<5>[ 18.245388] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10927 22:14:08.738309 cklight[0m.
10928 22:14:08.750177 <4>[ 18.258037] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10929 22:14:08.756859 <6>[ 18.267059] cfg80211: failed to load regulatory.db
10930 22:14:08.760303 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10931 22:14:08.801007 <6>[ 18.308775] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10932 22:14:08.808103 <6>[ 18.316286] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10933 22:14:08.831839 <6>[ 18.342978] mt7921e 0000:01:00.0: ASIC revision: 79610010
10934 22:14:08.937969 <4>[ 18.442526] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10935 22:14:08.944893 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10936 22:14:08.960428 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10937 22:14:08.979424 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10938 22:14:08.992828 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10939 22:14:09.011405 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10940 22:14:09.024334 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10941 22:14:09.044098 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10942 22:14:09.057537 <4>[ 18.561629] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10943 22:14:09.064313 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10944 22:14:09.080522 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10945 22:14:09.101035 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10946 22:14:09.112622 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10947 22:14:09.128192 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10948 22:14:09.147694 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10949 22:14:09.178245 <4>[ 18.682819] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10950 22:14:09.209125 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10951 22:14:09.235828 Starting [0;1;39mUser Login Management[0m...
10952 22:14:09.250448 Starting [0;1;39mPermit User Sessions[0m...
10953 22:14:09.268375 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10954 22:14:09.279839 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10955 22:14:09.292895 <4>[ 18.795818] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10956 22:14:09.293545
10957 22:14:09.299212 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10958 22:14:09.321081 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10959 22:14:09.339299 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10960 22:14:09.356419 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10961 22:14:09.373856 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10962 22:14:09.380634 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10963 22:14:09.398629 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10964 22:14:09.413809 <4>[ 18.918511] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10965 22:14:09.456586 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10966 22:14:09.480614 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10967 22:14:09.499131
10968 22:14:09.499772
10969 22:14:09.502241 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10970 22:14:09.502748
10971 22:14:09.505563 debian-bullseye-arm64 login: root (automatic login)
10972 22:14:09.506131
10973 22:14:09.506558
10974 22:14:09.534187 <4>[ 19.038812] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10975 22:14:09.540901 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Sun Jun 4 21:56:05 UTC 2023 aarch64
10976 22:14:09.541479
10977 22:14:09.547849 The programs included with the Debian GNU/Linux system are free software;
10978 22:14:09.554340 the exact distribution terms for each program are described in the
10979 22:14:09.558046 individual files in /usr/share/doc/*/copyright.
10980 22:14:09.560783
10981 22:14:09.563899 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10982 22:14:09.567549 permitted by applicable law.
10983 22:14:09.568842 Matched prompt #10: / #
10985 22:14:09.569957 Setting prompt string to ['/ #']
10986 22:14:09.570456 end: 2.2.5.1 login-action (duration 00:00:20) [common]
10988 22:14:09.571512 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
10989 22:14:09.571975 start: 2.2.6 expect-shell-connection (timeout 00:03:30) [common]
10990 22:14:09.572374 Setting prompt string to ['/ #']
10991 22:14:09.572715 Forcing a shell prompt, looking for ['/ #']
10993 22:14:09.623588 / #
10994 22:14:09.624293 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10995 22:14:09.624840 Waiting using forced prompt support (timeout 00:02:30)
10996 22:14:09.630404
10997 22:14:09.631346 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10998 22:14:09.631862 start: 2.2.7 export-device-env (timeout 00:03:30) [common]
10999 22:14:09.632393 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11000 22:14:09.632873 end: 2.2 depthcharge-retry (duration 00:01:30) [common]
11001 22:14:09.633332 end: 2 depthcharge-action (duration 00:01:30) [common]
11002 22:14:09.633812 start: 3 lava-test-retry (timeout 00:08:08) [common]
11003 22:14:09.634274 start: 3.1 lava-test-shell (timeout 00:08:08) [common]
11004 22:14:09.634713 Using namespace: common
11006 22:14:09.735931 / # #
11007 22:14:09.736590 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11008 22:14:09.737266 <4>[ 19.161238] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11009 22:14:09.742687 #
11010 22:14:09.743563 Using /lava-10583875
11012 22:14:09.844772 / # export SHELL=/bin/sh
11013 22:14:09.845564 <4>[ 19.281550] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11014 22:14:09.851560 export SHELL=/bin/sh
11016 22:14:09.953213 / # . /lava-10583875/environment
11017 22:14:09.954062 <4>[ 19.400906] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11018 22:14:09.994881 . /lava-10583875/environment<6>[ 19.466431] IPv6: ADDRCONF(NETDEV_CHANGE): enx00e04c722dd6: link becomes ready
11019 22:14:09.995449
11020 22:14:09.995829 <6>[ 19.474533] r8152 2-1.3:1.0 enx00e04c722dd6: carrier on
11022 22:14:10.097328 / # /lava-10583875/bin/lava-test-runner /lava-10583875/0
11023 22:14:10.097963 Test shell timeout: 10s (minimum of the action and connection timeout)
11024 22:14:10.099926 <4>[ 19.521459] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11025 22:14:10.138978 /lava-10583875/bin/lava-test-runner /lava-10583875/0
11026 22:14:10.139612 <3>[ 19.641143] mt7921e 0000:01:00.0: hardware init failed
11027 22:14:10.140327 + export TESTRUN_ID=0_v4l2-compliance-mtk-vcodec-enc
11028 22:14:10.140788 + cd /lava-10583875/0/tests/0_v4l2-compliance-mtk-vcodec-enc
11029 22:14:10.142812 + cat uuid
11030 22:14:10.143411 + UUID=10583875_1.5.2.3.1
11031 22:14:10.143790 + set +x
11032 22:14:10.149687 <LAVA_SIGNAL_STARTRUN 0_v4l2-compliance-mtk-vcodec-enc 10583875_1.5.2.3.1>
11033 22:14:10.150554 Received signal: <STARTRUN> 0_v4l2-compliance-mtk-vcodec-enc 10583875_1.5.2.3.1
11034 22:14:10.151009 Starting test lava.0_v4l2-compliance-mtk-vcodec-enc (10583875_1.5.2.3.1)
11035 22:14:10.151475 Skipping test definition patterns.
11036 22:14:10.156339 + /usr/bin/v4l2-parser.sh -d mtk-vcodec-enc
11037 22:14:10.159259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=device-presence RESULT=pass>
11038 22:14:10.159984 Received signal: <TESTCASE> TEST_CASE_ID=device-presence RESULT=pass
11040 22:14:10.169366 device: /dev/vide<4>[ 19.678139] use of bytesused == 0 is deprecated and will be removed in the future,
11041 22:14:10.169920 o2
11042 22:14:10.176016 <4>[ 19.686623] use the actual size instead.
11043 22:14:10.183011 <4>[ 19.692683] ------------[ cut here ]------------
11044 22:14:10.186418 <4>[ 19.697626] get_vaddr_frames() cannot follow VM_IO mapping
11045 22:14:10.199357 <4>[ 19.697866] WARNING: CPU: 1 PID: 314 at drivers/media/common/videobuf2/frame_vector.c:59 get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11046 22:14:10.248992 <4>[ 19.715977] Modules linked in: mt7921e mt7921_common mt76_connac_lib mt76 mac80211 libarc4 cfg80211 btusb mtk_vcodec_enc mtk_vcodec_common btintel mtk_vpu btmtk uvcvideo v4l2_mem2mem btrtl r8153_ecm videobuf2_vmalloc videobuf2_dma_contig btbcm videobuf2_memops videobuf2_v4l2 cdc_ether bluetooth videobuf2_common videodev usbnet ecdh_generic cros_ec_rpmsg crct10dif_ce r8152 ecc elan_i2c rfkill mc elants_i2c sbs_battery hid_google_hammer pcie_mediatek_gen3 cros_ec_chardev cros_ec_typec hid_vivaldi_common mtk_scp mtk_rpmsg mtk_scp_ipi ip_tables x_tables ipv6
11047 22:14:10.255076 <4>[ 19.765362] CPU: 1 PID: 314 Comm: v4l2-compliance Not tainted 6.1.31 #1
11048 22:14:10.261745 <4>[ 19.772226] Hardware name: Google Spherion (rev0 - 3) (DT)
11049 22:14:10.268318 <4>[ 19.777960] pstate: 60400009 (nZCv daif +PAN -UAO -TCO -DIT -SSBS BTYPE=--)
11050 22:14:10.275696 <4>[ 19.785172] pc : get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11051 22:14:10.281622 <4>[ 19.791263] lr : get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11052 22:14:10.285045 <4>[ 19.797354] sp : ffff8000091d3850
11053 22:14:10.292101 <4>[ 19.800916] x29: ffff8000091d3850 x28: ffffa99961bf1000 x27: ffffa99961bed238
11054 22:14:10.298523 <4>[ 19.808304] x26: 0000000000000000 x25: ffffa999d22dacb8 x24: ffff233e8eff9298
11055 22:14:10.308000 <4>[ 19.815691] x23: ffff233e89724400 x22: ffff233e80d48010 x21: 0000000000000000
11056 22:14:10.314887 <4>[ 19.823077] x20: 00000000fffffff2 x19: ffff233e8e1a6000 x18: fffffffffffe9678
11057 22:14:10.321324 <4>[ 19.830465] x17: 0000000000000000 x16: ffffa999d048bb60 x15: 0000000000000038
11058 22:14:10.327911 <4>[ 19.837852] x14: 000000000000035d x13: 0000000000000000 x12: 0000000000000000
11059 22:14:10.338011 <4>[ 19.845239] x11: 0000000000000000 x10: 0000000000000a60 x9 : ffff8000091d3700
11060 22:14:10.344118 <4>[ 19.852626] x8 : ffff233e8e4c8ac0 x7 : ffff233fbef2ee40 x6 : 000000000000035a
11061 22:14:10.351089 <4>[ 19.860013] x5 : 00000000410fd050 x4 : 0000000000c0000e x3 : 0000000000200000
11062 22:14:10.357938 <4>[ 19.867399] x2 : 0000000000000000 x1 : 0000000000000000 x0 : ffff233e8e4c8000
11063 22:14:10.361263 <4>[ 19.874786] Call trace:
11064 22:14:10.367391 <4>[ 19.877483] get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11065 22:14:10.374172 <4>[ 19.883226] vb2_create_framevec+0x50/0xac [videobuf2_memops]
11066 22:14:10.381451 <4>[ 19.889228] vb2_dc_get_userptr+0x9c/0x310 [videobuf2_dma_contig]
11067 22:14:10.384214 <4>[ 19.895579] __prepare_userptr+0x280/0x410 [videobuf2_common]
11068 22:14:10.390797 <4>[ 19.901583] __buf_prepare+0x1a0/0x244 [videobuf2_common]
11069 22:14:10.397598 <4>[ 19.907239] vb2_core_prepare_buf+0x3c/0x140 [videobuf2_common]
11070 22:14:10.404007 <4>[ 19.913416] vb2_prepare_buf+0x68/0xc0 [videobuf2_v4l2]
11071 22:14:10.407089 <4>[ 19.918916] v4l2_m2m_prepare_buf+0x40/0x90 [v4l2_mem2mem]
11072 22:14:10.413970 <4>[ 19.924731] v4l2_m2m_ioctl_prepare_buf+0x18/0x24 [v4l2_mem2mem]
11073 22:14:10.421020 <4>[ 19.930996] v4l_prepare_buf+0x48/0x60 [videodev]
11074 22:14:10.423367 <4>[ 19.936053] __video_do_ioctl+0x184/0x3d0 [videodev]
11075 22:14:10.429900 <4>[ 19.941296] video_usercopy+0x358/0x680 [videodev]
11076 22:14:10.433640 <4>[ 19.946368] video_ioctl2+0x18/0x30 [videodev]
11077 22:14:10.440196 <4>[ 19.951090] v4l2_ioctl+0x40/0x60 [videodev]
11078 22:14:10.443143 <4>[ 19.955641] __arm64_sys_ioctl+0xa8/0xf0
11079 22:14:10.446751 <4>[ 19.959822] invoke_syscall+0x48/0x114
11080 22:14:10.453704 <4>[ 19.963828] el0_svc_common.constprop.0+0x44/0xec
11081 22:14:10.456623 <4>[ 19.968783] do_el0_svc+0x2c/0xd0
11082 22:14:10.460276 <4>[ 19.972349] el0_svc+0x2c/0x84
11083 22:14:10.463208 <4>[ 19.975660] el0t_64_sync_handler+0xb8/0xc0
11084 22:14:10.467060 <4>[ 19.980096] el0t_64_sync+0x18c/0x190
11085 22:14:10.472904 <4>[ 19.984010] ---[ end trace 0000000000000000 ]---
11086 22:14:10.486102 v4l2-compliance 1.25.0-1, 64 bits, 64-bit time_t
11087 22:14:10.495077 v4l2-compliance SHA: 52926c1f2f03 2023-05-25 13:56:39
11088 22:14:10.501239
11089 22:14:10.513744 Compliance test for mtk-vcodec-enc device /dev/video2:
11090 22:14:10.519972
11091 22:14:10.530043 Driver Info:
11092 22:14:10.539090 Driver name : mtk-vcodec-enc
11093 22:14:10.551160 Card type : MT8192 video encoder
11094 22:14:10.561390 Bus info : platform:17020000.vcodec
11095 22:14:10.567289 Driver version : 6.1.31
11096 22:14:10.576632 Capabilities : 0x84204000
11097 22:14:10.585636 Video Memory-to-Memory Multiplanar
11098 22:14:10.595491 Streaming
11099 22:14:10.604744 Extended Pix Format
11100 22:14:10.613934 Device Capabilities
11101 22:14:10.623293 Device Caps : 0x04204000
11102 22:14:10.633925 Video Memory-to-Memory Multiplanar
11103 22:14:10.642549 Streaming
11104 22:14:10.653048 Extended Pix Format
11105 22:14:10.663645 Detected Stateful Encoder
11106 22:14:10.672827
11107 22:14:10.682730 Required ioctls:
11108 22:14:10.695869 <LAVA_SIGNAL_TESTSET START Required-ioctls>
11109 22:14:10.696466 test VIDIOC_QUERYCAP: OK
11110 22:14:10.697159 Received signal: <TESTSET> START Required-ioctls
11111 22:14:10.697559 Starting test_set Required-ioctls
11112 22:14:10.721058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11113 22:14:10.721893 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11115 22:14:10.724127 test invalid ioctls: OK
11116 22:14:10.744365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-ioctls RESULT=pass>
11117 22:14:10.745027
11118 22:14:10.745674 Received signal: <TESTCASE> TEST_CASE_ID=invalid-ioctls RESULT=pass
11120 22:14:10.753573 Allow for multiple opens:
11121 22:14:10.760631 <LAVA_SIGNAL_TESTSET STOP>
11122 22:14:10.761461 Received signal: <TESTSET> STOP
11123 22:14:10.761868 Closing test_set Required-ioctls
11124 22:14:10.770817 <LAVA_SIGNAL_TESTSET START Allow-for-multiple-opens>
11125 22:14:10.771662 Received signal: <TESTSET> START Allow-for-multiple-opens
11126 22:14:10.772073 Starting test_set Allow-for-multiple-opens
11127 22:14:10.773947 test second /dev/video2 open: OK
11128 22:14:10.794969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=second-/dev/video2-open RESULT=pass>
11129 22:14:10.795805 Received signal: <TESTCASE> TEST_CASE_ID=second-/dev/video2-open RESULT=pass
11131 22:14:10.796967 test VIDIOC_QUERYCAP: OK
11132 22:14:10.817785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11133 22:14:10.818654 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11135 22:14:10.821512 test VIDIOC_G/S_PRIORITY: OK
11136 22:14:10.841316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass>
11137 22:14:10.842206 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass
11139 22:14:10.844020 test for unlimited opens: OK
11140 22:14:10.865322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=for-unlimited-opens RESULT=pass>
11141 22:14:10.865892
11142 22:14:10.866528 Received signal: <TESTCASE> TEST_CASE_ID=for-unlimited-opens RESULT=pass
11144 22:14:10.875267 Debug ioctls:
11145 22:14:10.883245 <LAVA_SIGNAL_TESTSET STOP>
11146 22:14:10.884072 Received signal: <TESTSET> STOP
11147 22:14:10.884460 Closing test_set Allow-for-multiple-opens
11148 22:14:10.891629 <LAVA_SIGNAL_TESTSET START Debug-ioctls>
11149 22:14:10.892474 Received signal: <TESTSET> START Debug-ioctls
11150 22:14:10.892884 Starting test_set Debug-ioctls
11151 22:14:10.895274 test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
11152 22:14:10.914827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass>
11153 22:14:10.915644 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass
11155 22:14:10.921188 test VIDIOC_LOG_STATUS: OK (Not Supported)
11156 22:14:10.938166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass>
11157 22:14:10.938816
11158 22:14:10.939567 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass
11160 22:14:10.946720 Input ioctls:
11161 22:14:10.953321 <LAVA_SIGNAL_TESTSET STOP>
11162 22:14:10.954157 Received signal: <TESTSET> STOP
11163 22:14:10.954625 Closing test_set Debug-ioctls
11164 22:14:10.962286 <LAVA_SIGNAL_TESTSET START Input-ioctls>
11165 22:14:10.963177 Received signal: <TESTSET> START Input-ioctls
11166 22:14:10.963574 Starting test_set Input-ioctls
11167 22:14:10.965700 test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
11168 22:14:10.990392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass>
11169 22:14:10.991247 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass
11171 22:14:10.992736 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11172 22:14:11.011160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11173 22:14:11.012009 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11175 22:14:11.017143 test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
11176 22:14:11.035177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass>
11177 22:14:11.035992 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass
11179 22:14:11.041931 test VIDIOC_ENUMAUDIO: OK (Not Supported)
11180 22:14:11.059429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass>
11181 22:14:11.060270 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass
11183 22:14:11.062005 test VIDIOC_G/S/ENUMINPUT: OK (Not Supported)
11184 22:14:11.082624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass>
11185 22:14:11.083419 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass
11187 22:14:11.085724 test VIDIOC_G/S_AUDIO: OK (Not Supported)
11188 22:14:11.108866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass>
11189 22:14:11.109696 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass
11191 22:14:11.111279 Inputs: 0 Audio Inputs: 0 Tuners: 0
11192 22:14:11.117998
11193 22:14:11.134530 test VIDIOC_G/S_MODULATOR: OK (Not Supported)
11194 22:14:11.154967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass>
11195 22:14:11.155789 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass
11197 22:14:11.161442 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11198 22:14:11.180242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11199 22:14:11.181071 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11201 22:14:11.185383 test VIDIOC_ENUMAUDOUT: OK (Not Supported)
11202 22:14:11.203487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass>
11203 22:14:11.204318 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass
11205 22:14:11.210212 test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
11206 22:14:11.228551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass>
11207 22:14:11.229377 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass
11209 22:14:11.235068 test VIDIOC_G/S_AUDOUT: OK (Not Supported)
11210 22:14:11.253275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass>
11211 22:14:11.253825
11212 22:14:11.254481 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass
11214 22:14:11.271116 test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
11215 22:14:11.290968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass>
11216 22:14:11.291855 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass
11218 22:14:11.297408 test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
11219 22:14:11.319831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass>
11220 22:14:11.320662 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass
11222 22:14:11.322577 test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
11223 22:14:11.345938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass>
11224 22:14:11.347018 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass
11226 22:14:11.348814 test VIDIOC_G/S_EDID: OK (Not Supported)
11227 22:14:11.374465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass>
11228 22:14:11.375021
11229 22:14:11.375810 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass
11231 22:14:11.389214 Control ioctls:
11232 22:14:11.396150 <LAVA_SIGNAL_TESTSET STOP>
11233 22:14:11.396884 Received signal: <TESTSET> STOP
11234 22:14:11.397288 Closing test_set Input-ioctls
11235 22:14:11.406730 <LAVA_SIGNAL_TESTSET START Control-ioctls>
11236 22:14:11.407567 Received signal: <TESTSET> START Control-ioctls
11237 22:14:11.407967 Starting test_set Control-ioctls
11238 22:14:11.409395 test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
11239 22:14:11.434334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass>
11240 22:14:11.434974 test VIDIOC_QUERYCTRL: OK
11241 22:14:11.435725 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass
11243 22:14:11.454716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass>
11244 22:14:11.455555 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass
11246 22:14:11.458001 test VIDIOC_G/S_CTRL: OK
11247 22:14:11.482191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass>
11248 22:14:11.483066 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass
11250 22:14:11.485165 test VIDIOC_G/S/TRY_EXT_CTRLS: OK
11251 22:14:11.507936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass>
11252 22:14:11.508776 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass
11254 22:14:11.518028 fail: ../utils/v4l2-compliance/v4l2-test-controls.cpp(1167): node->codec_mask & STATEFUL_ENCODER
11255 22:14:11.521067 test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: FAIL
11256 22:14:11.545302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail>
11257 22:14:11.546292 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail
11259 22:14:11.548127 test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
11260 22:14:11.567098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass>
11261 22:14:11.567946 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass
11263 22:14:11.571071 Standard Controls: 16 Private Controls: 0
11264 22:14:11.577522
11265 22:14:11.588206 Format ioctls:
11266 22:14:11.594847 <LAVA_SIGNAL_TESTSET STOP>
11267 22:14:11.595680 Received signal: <TESTSET> STOP
11268 22:14:11.596071 Closing test_set Control-ioctls
11269 22:14:11.604316 <LAVA_SIGNAL_TESTSET START Format-ioctls>
11270 22:14:11.605125 Received signal: <TESTSET> START Format-ioctls
11271 22:14:11.605520 Starting test_set Format-ioctls
11272 22:14:11.607984 test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
11273 22:14:11.633342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass>
11274 22:14:11.634174 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass
11276 22:14:11.636309 test VIDIOC_G/S_PARM: OK
11277 22:14:11.655021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass>
11278 22:14:11.655854 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass
11280 22:14:11.658472 test VIDIOC_G_FBUF: OK (Not Supported)
11281 22:14:11.678252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass>
11282 22:14:11.679220 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass
11284 22:14:11.681971 test VIDIOC_G_FMT: OK
11285 22:14:11.702740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass>
11286 22:14:11.703563 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass
11288 22:14:11.705841 test VIDIOC_TRY_FMT: OK
11289 22:14:11.726300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass>
11290 22:14:11.727179 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass
11292 22:14:11.736990 fail: ../utils/v4l2-compliance/v4l2-test-formats.cpp(924): sel.r.width != fmt.g_width()
11293 22:14:11.737772 test VIDIOC_S_FMT: FAIL
11294 22:14:11.758807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail>
11295 22:14:11.759636 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail
11297 22:14:11.762335 test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
11298 22:14:11.782279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass>
11299 22:14:11.783161 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass
11301 22:14:11.785071 test Cropping: OK
11302 22:14:11.805925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Cropping RESULT=pass>
11303 22:14:11.806767 Received signal: <TESTCASE> TEST_CASE_ID=Cropping RESULT=pass
11305 22:14:11.809152 test Composing: OK (Not Supported)
11306 22:14:11.829645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Composing RESULT=pass>
11307 22:14:11.830487 Received signal: <TESTCASE> TEST_CASE_ID=Composing RESULT=pass
11309 22:14:11.832967 test Scaling: OK (Not Supported)
11310 22:14:11.854400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Scaling RESULT=pass>
11311 22:14:11.854973
11312 22:14:11.855609 Received signal: <TESTCASE> TEST_CASE_ID=Scaling RESULT=pass
11314 22:14:11.863821 Codec ioctls:
11315 22:14:11.869870 <LAVA_SIGNAL_TESTSET STOP>
11316 22:14:11.870749 Received signal: <TESTSET> STOP
11317 22:14:11.871161 Closing test_set Format-ioctls
11318 22:14:11.878871 <LAVA_SIGNAL_TESTSET START Codec-ioctls>
11319 22:14:11.879707 Received signal: <TESTSET> START Codec-ioctls
11320 22:14:11.880106 Starting test_set Codec-ioctls
11321 22:14:11.881812 test VIDIOC_(TRY_)ENCODER_CMD: OK
11322 22:14:11.900779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass>
11323 22:14:11.901635 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass
11325 22:14:11.907383 test VIDIOC_G_ENC_INDEX: OK (Not Supported)
11326 22:14:11.926618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass>
11327 22:14:11.927475 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass
11329 22:14:11.933251 test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
11330 22:14:11.950583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass>
11331 22:14:11.951155
11332 22:14:11.951791 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass
11334 22:14:11.960556 Buffer ioctls:
11335 22:14:11.967280 <LAVA_SIGNAL_TESTSET STOP>
11336 22:14:11.968109 Received signal: <TESTSET> STOP
11337 22:14:11.968500 Closing test_set Codec-ioctls
11338 22:14:11.977086 <LAVA_SIGNAL_TESTSET START Buffer-ioctls>
11339 22:14:11.977917 Received signal: <TESTSET> START Buffer-ioctls
11340 22:14:11.978310 Starting test_set Buffer-ioctls
11341 22:14:11.980143 test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
11342 22:14:12.005074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass>
11343 22:14:12.005643 test VIDIOC_EXPBUF: OK
11344 22:14:12.006294 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass
11346 22:14:12.025853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass>
11347 22:14:12.026736 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass
11349 22:14:12.028699 test Requests: OK (Not Supported)
11350 22:14:12.049550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Requests RESULT=pass>
11351 22:14:12.050120
11352 22:14:12.050810 Received signal: <TESTCASE> TEST_CASE_ID=Requests RESULT=pass
11354 22:14:12.059585 Test input 0:
11355 22:14:12.070001
11356 22:14:12.080824 Streaming ioctls:
11357 22:14:12.087581 <LAVA_SIGNAL_TESTSET STOP>
11358 22:14:12.088416 Received signal: <TESTSET> STOP
11359 22:14:12.088809 Closing test_set Buffer-ioctls
11360 22:14:12.096393 <LAVA_SIGNAL_TESTSET START Streaming-ioctls_Test-input-0>
11361 22:14:12.097262 Received signal: <TESTSET> START Streaming-ioctls_Test-input-0
11362 22:14:12.097670 Starting test_set Streaming-ioctls_Test-input-0
11363 22:14:12.099714 test read/write: OK (Not Supported)
11364 22:14:12.121321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=read/write RESULT=pass>
11365 22:14:12.122154 Received signal: <TESTCASE> TEST_CASE_ID=read/write RESULT=pass
11367 22:14:12.128141 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(2778): node->streamon(q.g_type())
11368 22:14:12.138746 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(2825): testBlockingDQBuf(node, q)
11369 22:14:12.142661 test blocking wait: FAIL
11370 22:14:12.166729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blocking-wait RESULT=fail>
11371 22:14:12.167576 Received signal: <TESTCASE> TEST_CASE_ID=blocking-wait RESULT=fail
11373 22:14:12.176325 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1430): node->streamon(q.g_type())
11374 22:14:12.176898 test MMAP (select): FAIL
11375 22:14:12.202122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-select RESULT=fail>
11376 22:14:12.203001 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-select RESULT=fail
11378 22:14:12.208065 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1430): node->streamon(q.g_type())
11379 22:14:12.212161 test MMAP (epoll): FAIL
11380 22:14:12.236096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-epoll RESULT=fail>
11381 22:14:12.236944 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-epoll RESULT=fail
11383 22:14:12.243108 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1602): ret && ret != ENOTTY (got 22)
11384 22:14:12.253358 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1733): setupUserPtr(node, q)
11385 22:14:12.257297 test USERPTR (select): FAIL
11386 22:14:12.282562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-select RESULT=fail>
11387 22:14:12.283409 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-select RESULT=fail
11389 22:14:12.288528 test DMABUF: Cannot test, specify --expbuf-device
11390 22:14:12.289103
11391 22:14:12.308469 Total for mtk-vcodec-enc device /dev/video2: 50, Succeeded: 44, Failed: 6, Warnings: 0
11392 22:14:12.311625 <LAVA_TEST_RUNNER EXIT>
11393 22:14:12.312467 ok: lava_test_shell seems to have completed
11394 22:14:12.312902 Marking unfinished test run as failed
11396 22:14:12.317846 Composing:
result: pass
set: Format-ioctls
Cropping:
result: pass
set: Format-ioctls
MMAP-epoll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-select:
result: fail
set: Streaming-ioctls_Test-input-0
Requests:
result: pass
set: Buffer-ioctls
Scaling:
result: pass
set: Format-ioctls
USERPTR-select:
result: fail
set: Streaming-ioctls_Test-input-0
VIDIOC_DBG_G/S_REGISTER:
result: pass
set: Debug-ioctls
VIDIOC_DV_TIMINGS_CAP:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_STD:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDIO:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDOUT:
result: pass
set: Input-ioctls
VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS:
result: pass
set: Format-ioctls
VIDIOC_EXPBUF:
result: pass
set: Buffer-ioctls
VIDIOC_G/S/ENUMINPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/ENUMOUTPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/TRY_EXT_CTRLS:
result: pass
set: Control-ioctls
VIDIOC_G/S_AUDIO:
result: pass
set: Input-ioctls
VIDIOC_G/S_AUDOUT:
result: pass
set: Input-ioctls
VIDIOC_G/S_CTRL:
result: pass
set: Control-ioctls
VIDIOC_G/S_EDID:
result: pass
set: Input-ioctls
VIDIOC_G/S_FREQUENCY:
result: pass
set: Input-ioctls
VIDIOC_G/S_JPEGCOMP:
result: pass
set: Control-ioctls
VIDIOC_G/S_MODULATOR:
result: pass
set: Input-ioctls
VIDIOC_G/S_PARM:
result: pass
set: Format-ioctls
VIDIOC_G/S_PRIORITY:
result: pass
set: Allow-for-multiple-opens
VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS:
result: pass
set: Input-ioctls
VIDIOC_G_ENC_INDEX:
result: pass
set: Codec-ioctls
VIDIOC_G_FBUF:
result: pass
set: Format-ioctls
VIDIOC_G_FMT:
result: pass
set: Format-ioctls
VIDIOC_G_SLICED_VBI_CAP:
result: pass
set: Format-ioctls
VIDIOC_LOG_STATUS:
result: pass
set: Debug-ioctls
VIDIOC_QUERYCAP:
result: pass
set: Allow-for-multiple-opens
VIDIOC_QUERYCTRL:
result: pass
set: Control-ioctls
VIDIOC_QUERY_EXT_CTRL/QUERYMENU:
result: pass
set: Control-ioctls
VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF:
result: pass
set: Buffer-ioctls
VIDIOC_S_FMT:
result: fail
set: Format-ioctls
VIDIOC_S_HW_FREQ_SEEK:
result: pass
set: Input-ioctls
VIDIOC_TRY_DECODER_CMD:
result: pass
set: Codec-ioctls
VIDIOC_TRY_ENCODER_CMD:
result: pass
set: Codec-ioctls
VIDIOC_TRY_FMT:
result: pass
set: Format-ioctls
VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT:
result: fail
set: Control-ioctls
blocking-wait:
result: fail
set: Streaming-ioctls_Test-input-0
device-presence: pass
for-unlimited-opens:
result: pass
set: Allow-for-multiple-opens
invalid-ioctls:
result: pass
set: Required-ioctls
read/write:
result: pass
set: Streaming-ioctls_Test-input-0
second-/dev/video2-open:
result: pass
set: Allow-for-multiple-opens
11397 22:14:12.318505 end: 3.1 lava-test-shell (duration 00:00:03) [common]
11398 22:14:12.318975 end: 3 lava-test-retry (duration 00:00:03) [common]
11399 22:14:12.319474 start: 4 finalize (timeout 00:08:05) [common]
11400 22:14:12.319959 start: 4.1 power-off (timeout 00:00:30) [common]
11401 22:14:12.320795 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=off'
11402 22:14:12.443532 >> Command sent successfully.
11403 22:14:12.448047 Returned 0 in 0 seconds
11404 22:14:12.549032 end: 4.1 power-off (duration 00:00:00) [common]
11406 22:14:12.550663 start: 4.2 read-feedback (timeout 00:08:05) [common]
11407 22:14:12.551967 Listened to connection for namespace 'common' for up to 1s
11408 22:14:13.552635 Finalising connection for namespace 'common'
11409 22:14:13.553325 Disconnecting from shell: Finalise
11410 22:14:13.553825 / #
11411 22:14:13.655005 end: 4.2 read-feedback (duration 00:00:01) [common]
11412 22:14:13.655714 end: 4 finalize (duration 00:00:01) [common]
11413 22:14:13.656306 Cleaning after the job
11414 22:14:13.656815 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10583875/tftp-deploy-v0ttru9s/ramdisk
11415 22:14:13.677656 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10583875/tftp-deploy-v0ttru9s/kernel
11416 22:14:13.696728 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10583875/tftp-deploy-v0ttru9s/dtb
11417 22:14:13.697094 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10583875/tftp-deploy-v0ttru9s/modules
11418 22:14:13.706589 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10583875
11419 22:14:13.763404 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10583875
11420 22:14:13.763583 Job finished correctly