Boot log: mt8192-asurada-spherion-r0
- Errors: 1
- Kernel Errors: 30
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 64
1 22:11:49.954835 lava-dispatcher, installed at version: 2023.03
2 22:11:49.955071 start: 0 validate
3 22:11:49.955217 Start time: 2023-06-04 22:11:49.955209+00:00 (UTC)
4 22:11:49.955352 Using caching service: 'http://localhost/cache/?uri=%s'
5 22:11:49.955490 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-v4l2%2F20230527.0%2Farm64%2Frootfs.cpio.gz exists
6 22:11:50.249428 Using caching service: 'http://localhost/cache/?uri=%s'
7 22:11:50.250286 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1281-g84d5372e0f314%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 22:12:13.766696 Using caching service: 'http://localhost/cache/?uri=%s'
9 22:12:13.767446 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1281-g84d5372e0f314%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 22:12:14.052480 Using caching service: 'http://localhost/cache/?uri=%s'
11 22:12:14.053136 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1281-g84d5372e0f314%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 22:12:17.343329 validate duration: 27.39
14 22:12:17.343577 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 22:12:17.343673 start: 1.1 download-retry (timeout 00:10:00) [common]
16 22:12:17.343760 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 22:12:17.343887 Not decompressing ramdisk as can be used compressed.
18 22:12:17.343969 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-v4l2/20230527.0/arm64/rootfs.cpio.gz
19 22:12:17.344037 saving as /var/lib/lava/dispatcher/tmp/10583861/tftp-deploy-vhgxdhl0/ramdisk/rootfs.cpio.gz
20 22:12:17.344096 total size: 27151647 (25MB)
21 22:12:17.634006 progress 0% (0MB)
22 22:12:17.641033 progress 5% (1MB)
23 22:12:17.647819 progress 10% (2MB)
24 22:12:17.654830 progress 15% (3MB)
25 22:12:17.661626 progress 20% (5MB)
26 22:12:17.668555 progress 25% (6MB)
27 22:12:17.675389 progress 30% (7MB)
28 22:12:17.682332 progress 35% (9MB)
29 22:12:17.689044 progress 40% (10MB)
30 22:12:17.695801 progress 45% (11MB)
31 22:12:17.702753 progress 50% (12MB)
32 22:12:17.709460 progress 55% (14MB)
33 22:12:17.716428 progress 60% (15MB)
34 22:12:17.723197 progress 65% (16MB)
35 22:12:17.730173 progress 70% (18MB)
36 22:12:17.736951 progress 75% (19MB)
37 22:12:17.743812 progress 80% (20MB)
38 22:12:17.750815 progress 85% (22MB)
39 22:12:17.757447 progress 90% (23MB)
40 22:12:17.764265 progress 95% (24MB)
41 22:12:17.770934 progress 100% (25MB)
42 22:12:17.771128 25MB downloaded in 0.43s (60.64MB/s)
43 22:12:17.771281 end: 1.1.1 http-download (duration 00:00:00) [common]
45 22:12:17.771516 end: 1.1 download-retry (duration 00:00:00) [common]
46 22:12:17.771600 start: 1.2 download-retry (timeout 00:10:00) [common]
47 22:12:17.771684 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 22:12:17.771812 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1281-g84d5372e0f314/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 22:12:17.771883 saving as /var/lib/lava/dispatcher/tmp/10583861/tftp-deploy-vhgxdhl0/kernel/Image
50 22:12:17.771945 total size: 45746688 (43MB)
51 22:12:17.772005 No compression specified
52 22:12:17.773166 progress 0% (0MB)
53 22:12:17.784600 progress 5% (2MB)
54 22:12:17.796207 progress 10% (4MB)
55 22:12:17.807980 progress 15% (6MB)
56 22:12:17.819812 progress 20% (8MB)
57 22:12:17.831370 progress 25% (10MB)
58 22:12:17.842837 progress 30% (13MB)
59 22:12:17.854509 progress 35% (15MB)
60 22:12:17.866053 progress 40% (17MB)
61 22:12:17.877660 progress 45% (19MB)
62 22:12:17.889288 progress 50% (21MB)
63 22:12:17.900722 progress 55% (24MB)
64 22:12:17.912397 progress 60% (26MB)
65 22:12:17.924161 progress 65% (28MB)
66 22:12:17.935849 progress 70% (30MB)
67 22:12:17.947478 progress 75% (32MB)
68 22:12:17.959028 progress 80% (34MB)
69 22:12:17.970690 progress 85% (37MB)
70 22:12:17.982313 progress 90% (39MB)
71 22:12:17.994636 progress 95% (41MB)
72 22:12:18.006214 progress 100% (43MB)
73 22:12:18.006378 43MB downloaded in 0.23s (186.10MB/s)
74 22:12:18.006531 end: 1.2.1 http-download (duration 00:00:00) [common]
76 22:12:18.006759 end: 1.2 download-retry (duration 00:00:00) [common]
77 22:12:18.006844 start: 1.3 download-retry (timeout 00:09:59) [common]
78 22:12:18.006934 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 22:12:18.007099 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1281-g84d5372e0f314/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 22:12:18.007171 saving as /var/lib/lava/dispatcher/tmp/10583861/tftp-deploy-vhgxdhl0/dtb/mt8192-asurada-spherion-r0.dtb
81 22:12:18.007234 total size: 46924 (0MB)
82 22:12:18.007294 No compression specified
83 22:12:18.008369 progress 69% (0MB)
84 22:12:18.008640 progress 100% (0MB)
85 22:12:18.008792 0MB downloaded in 0.00s (28.77MB/s)
86 22:12:18.008910 end: 1.3.1 http-download (duration 00:00:00) [common]
88 22:12:18.009165 end: 1.3 download-retry (duration 00:00:00) [common]
89 22:12:18.009249 start: 1.4 download-retry (timeout 00:09:59) [common]
90 22:12:18.009331 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 22:12:18.009441 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1281-g84d5372e0f314/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 22:12:18.009531 saving as /var/lib/lava/dispatcher/tmp/10583861/tftp-deploy-vhgxdhl0/modules/modules.tar
93 22:12:18.009608 total size: 8541948 (8MB)
94 22:12:18.009668 Using unxz to decompress xz
95 22:12:18.013593 progress 0% (0MB)
96 22:12:18.036009 progress 5% (0MB)
97 22:12:18.061827 progress 10% (0MB)
98 22:12:18.087288 progress 15% (1MB)
99 22:12:18.112322 progress 20% (1MB)
100 22:12:18.136461 progress 25% (2MB)
101 22:12:18.164906 progress 30% (2MB)
102 22:12:18.191292 progress 35% (2MB)
103 22:12:18.216864 progress 40% (3MB)
104 22:12:18.241940 progress 45% (3MB)
105 22:12:18.267654 progress 50% (4MB)
106 22:12:18.291173 progress 55% (4MB)
107 22:12:18.315848 progress 60% (4MB)
108 22:12:18.341615 progress 65% (5MB)
109 22:12:18.367020 progress 70% (5MB)
110 22:12:18.390672 progress 75% (6MB)
111 22:12:18.414787 progress 80% (6MB)
112 22:12:18.439673 progress 85% (6MB)
113 22:12:18.469169 progress 90% (7MB)
114 22:12:18.494663 progress 95% (7MB)
115 22:12:18.518778 progress 100% (8MB)
116 22:12:18.524569 8MB downloaded in 0.51s (15.82MB/s)
117 22:12:18.524854 end: 1.4.1 http-download (duration 00:00:01) [common]
119 22:12:18.525119 end: 1.4 download-retry (duration 00:00:01) [common]
120 22:12:18.525215 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 22:12:18.525310 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 22:12:18.525393 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 22:12:18.525491 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 22:12:18.525779 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10583861/lava-overlay-24y5q6vq
125 22:12:18.525925 makedir: /var/lib/lava/dispatcher/tmp/10583861/lava-overlay-24y5q6vq/lava-10583861/bin
126 22:12:18.526046 makedir: /var/lib/lava/dispatcher/tmp/10583861/lava-overlay-24y5q6vq/lava-10583861/tests
127 22:12:18.526158 makedir: /var/lib/lava/dispatcher/tmp/10583861/lava-overlay-24y5q6vq/lava-10583861/results
128 22:12:18.526286 Creating /var/lib/lava/dispatcher/tmp/10583861/lava-overlay-24y5q6vq/lava-10583861/bin/lava-add-keys
129 22:12:18.526447 Creating /var/lib/lava/dispatcher/tmp/10583861/lava-overlay-24y5q6vq/lava-10583861/bin/lava-add-sources
130 22:12:18.526594 Creating /var/lib/lava/dispatcher/tmp/10583861/lava-overlay-24y5q6vq/lava-10583861/bin/lava-background-process-start
131 22:12:18.526764 Creating /var/lib/lava/dispatcher/tmp/10583861/lava-overlay-24y5q6vq/lava-10583861/bin/lava-background-process-stop
132 22:12:18.526927 Creating /var/lib/lava/dispatcher/tmp/10583861/lava-overlay-24y5q6vq/lava-10583861/bin/lava-common-functions
133 22:12:18.527070 Creating /var/lib/lava/dispatcher/tmp/10583861/lava-overlay-24y5q6vq/lava-10583861/bin/lava-echo-ipv4
134 22:12:18.527234 Creating /var/lib/lava/dispatcher/tmp/10583861/lava-overlay-24y5q6vq/lava-10583861/bin/lava-install-packages
135 22:12:18.527372 Creating /var/lib/lava/dispatcher/tmp/10583861/lava-overlay-24y5q6vq/lava-10583861/bin/lava-installed-packages
136 22:12:18.527508 Creating /var/lib/lava/dispatcher/tmp/10583861/lava-overlay-24y5q6vq/lava-10583861/bin/lava-os-build
137 22:12:18.527647 Creating /var/lib/lava/dispatcher/tmp/10583861/lava-overlay-24y5q6vq/lava-10583861/bin/lava-probe-channel
138 22:12:18.527786 Creating /var/lib/lava/dispatcher/tmp/10583861/lava-overlay-24y5q6vq/lava-10583861/bin/lava-probe-ip
139 22:12:18.527930 Creating /var/lib/lava/dispatcher/tmp/10583861/lava-overlay-24y5q6vq/lava-10583861/bin/lava-target-ip
140 22:12:18.528097 Creating /var/lib/lava/dispatcher/tmp/10583861/lava-overlay-24y5q6vq/lava-10583861/bin/lava-target-mac
141 22:12:18.528262 Creating /var/lib/lava/dispatcher/tmp/10583861/lava-overlay-24y5q6vq/lava-10583861/bin/lava-target-storage
142 22:12:18.528428 Creating /var/lib/lava/dispatcher/tmp/10583861/lava-overlay-24y5q6vq/lava-10583861/bin/lava-test-case
143 22:12:18.528567 Creating /var/lib/lava/dispatcher/tmp/10583861/lava-overlay-24y5q6vq/lava-10583861/bin/lava-test-event
144 22:12:18.528703 Creating /var/lib/lava/dispatcher/tmp/10583861/lava-overlay-24y5q6vq/lava-10583861/bin/lava-test-feedback
145 22:12:18.528841 Creating /var/lib/lava/dispatcher/tmp/10583861/lava-overlay-24y5q6vq/lava-10583861/bin/lava-test-raise
146 22:12:18.528982 Creating /var/lib/lava/dispatcher/tmp/10583861/lava-overlay-24y5q6vq/lava-10583861/bin/lava-test-reference
147 22:12:18.529123 Creating /var/lib/lava/dispatcher/tmp/10583861/lava-overlay-24y5q6vq/lava-10583861/bin/lava-test-runner
148 22:12:18.529288 Creating /var/lib/lava/dispatcher/tmp/10583861/lava-overlay-24y5q6vq/lava-10583861/bin/lava-test-set
149 22:12:18.529455 Creating /var/lib/lava/dispatcher/tmp/10583861/lava-overlay-24y5q6vq/lava-10583861/bin/lava-test-shell
150 22:12:18.529665 Updating /var/lib/lava/dispatcher/tmp/10583861/lava-overlay-24y5q6vq/lava-10583861/bin/lava-install-packages (oe)
151 22:12:18.529878 Updating /var/lib/lava/dispatcher/tmp/10583861/lava-overlay-24y5q6vq/lava-10583861/bin/lava-installed-packages (oe)
152 22:12:18.530040 Creating /var/lib/lava/dispatcher/tmp/10583861/lava-overlay-24y5q6vq/lava-10583861/environment
153 22:12:18.530150 LAVA metadata
154 22:12:18.530226 - LAVA_JOB_ID=10583861
155 22:12:18.530293 - LAVA_DISPATCHER_IP=192.168.201.1
156 22:12:18.530401 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 22:12:18.530472 skipped lava-vland-overlay
158 22:12:18.530548 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 22:12:18.530627 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 22:12:18.530693 skipped lava-multinode-overlay
161 22:12:18.530766 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 22:12:18.530848 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 22:12:18.530927 Loading test definitions
164 22:12:18.531022 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 22:12:18.531097 Using /lava-10583861 at stage 0
166 22:12:18.531389 uuid=10583861_1.5.2.3.1 testdef=None
167 22:12:18.531484 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 22:12:18.531585 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 22:12:18.532302 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 22:12:18.532578 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 22:12:18.533192 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 22:12:18.533455 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 22:12:18.534382 runner path: /var/lib/lava/dispatcher/tmp/10583861/lava-overlay-24y5q6vq/lava-10583861/0/tests/0_v4l2-compliance-uvc test_uuid 10583861_1.5.2.3.1
176 22:12:18.534575 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 22:12:18.534924 Creating lava-test-runner.conf files
179 22:12:18.535026 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10583861/lava-overlay-24y5q6vq/lava-10583861/0 for stage 0
180 22:12:18.535139 - 0_v4l2-compliance-uvc
181 22:12:18.535275 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 22:12:18.535372 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 22:12:18.542431 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 22:12:18.542557 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 22:12:18.542658 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 22:12:18.542761 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 22:12:18.542868 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 22:12:19.255600 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 22:12:19.255964 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 22:12:19.256085 extracting modules file /var/lib/lava/dispatcher/tmp/10583861/tftp-deploy-vhgxdhl0/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10583861/extract-overlay-ramdisk-4pzq6zhk/ramdisk
191 22:12:19.470493 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 22:12:19.470667 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 22:12:19.470762 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10583861/compress-overlay-288azcaq/overlay-1.5.2.4.tar.gz to ramdisk
194 22:12:19.470834 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10583861/compress-overlay-288azcaq/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10583861/extract-overlay-ramdisk-4pzq6zhk/ramdisk
195 22:12:19.477479 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 22:12:19.477653 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 22:12:19.477745 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 22:12:19.477833 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 22:12:19.477914 Building ramdisk /var/lib/lava/dispatcher/tmp/10583861/extract-overlay-ramdisk-4pzq6zhk/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10583861/extract-overlay-ramdisk-4pzq6zhk/ramdisk
200 22:12:20.083677 >> 230334 blocks
201 22:12:24.096042 rename /var/lib/lava/dispatcher/tmp/10583861/extract-overlay-ramdisk-4pzq6zhk/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10583861/tftp-deploy-vhgxdhl0/ramdisk/ramdisk.cpio.gz
202 22:12:24.096480 end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
203 22:12:24.096608 start: 1.5.8 prepare-kernel (timeout 00:09:53) [common]
204 22:12:24.096710 start: 1.5.8.1 prepare-fit (timeout 00:09:53) [common]
205 22:12:24.096817 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10583861/tftp-deploy-vhgxdhl0/kernel/Image'
206 22:12:36.353833 Returned 0 in 12 seconds
207 22:12:36.454525 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10583861/tftp-deploy-vhgxdhl0/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10583861/tftp-deploy-vhgxdhl0/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10583861/tftp-deploy-vhgxdhl0/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10583861/tftp-deploy-vhgxdhl0/kernel/image.itb
208 22:12:37.129310 output: FIT description: Kernel Image image with one or more FDT blobs
209 22:12:37.129701 output: Created: Sun Jun 4 23:12:37 2023
210 22:12:37.129781 output: Image 0 (kernel-1)
211 22:12:37.129848 output: Description:
212 22:12:37.129912 output: Created: Sun Jun 4 23:12:37 2023
213 22:12:37.129975 output: Type: Kernel Image
214 22:12:37.130035 output: Compression: lzma compressed
215 22:12:37.130097 output: Data Size: 10081729 Bytes = 9845.44 KiB = 9.61 MiB
216 22:12:37.130156 output: Architecture: AArch64
217 22:12:37.130214 output: OS: Linux
218 22:12:37.130274 output: Load Address: 0x00000000
219 22:12:37.130333 output: Entry Point: 0x00000000
220 22:12:37.130390 output: Hash algo: crc32
221 22:12:37.130447 output: Hash value: 3b3111d8
222 22:12:37.130501 output: Image 1 (fdt-1)
223 22:12:37.130556 output: Description: mt8192-asurada-spherion-r0
224 22:12:37.130610 output: Created: Sun Jun 4 23:12:37 2023
225 22:12:37.130664 output: Type: Flat Device Tree
226 22:12:37.130719 output: Compression: uncompressed
227 22:12:37.130773 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
228 22:12:37.130828 output: Architecture: AArch64
229 22:12:37.130881 output: Hash algo: crc32
230 22:12:37.130935 output: Hash value: 1df858fa
231 22:12:37.130988 output: Image 2 (ramdisk-1)
232 22:12:37.131042 output: Description: unavailable
233 22:12:37.131095 output: Created: Sun Jun 4 23:12:37 2023
234 22:12:37.131149 output: Type: RAMDisk Image
235 22:12:37.131203 output: Compression: Unknown Compression
236 22:12:37.131256 output: Data Size: 40122768 Bytes = 39182.39 KiB = 38.26 MiB
237 22:12:37.131311 output: Architecture: AArch64
238 22:12:37.131364 output: OS: Linux
239 22:12:37.131418 output: Load Address: unavailable
240 22:12:37.131471 output: Entry Point: unavailable
241 22:12:37.131525 output: Hash algo: crc32
242 22:12:37.131578 output: Hash value: 3f9d44ae
243 22:12:37.131631 output: Default Configuration: 'conf-1'
244 22:12:37.131685 output: Configuration 0 (conf-1)
245 22:12:37.131739 output: Description: mt8192-asurada-spherion-r0
246 22:12:37.131792 output: Kernel: kernel-1
247 22:12:37.131845 output: Init Ramdisk: ramdisk-1
248 22:12:37.131899 output: FDT: fdt-1
249 22:12:37.131952 output: Loadables: kernel-1
250 22:12:37.132005 output:
251 22:12:37.132197 end: 1.5.8.1 prepare-fit (duration 00:00:13) [common]
252 22:12:37.132294 end: 1.5.8 prepare-kernel (duration 00:00:13) [common]
253 22:12:37.132395 end: 1.5 prepare-tftp-overlay (duration 00:00:19) [common]
254 22:12:37.132488 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:40) [common]
255 22:12:37.132563 No LXC device requested
256 22:12:37.132642 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 22:12:37.132728 start: 1.7 deploy-device-env (timeout 00:09:40) [common]
258 22:12:37.132806 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 22:12:37.132874 Checking files for TFTP limit of 4294967296 bytes.
260 22:12:37.133363 end: 1 tftp-deploy (duration 00:00:20) [common]
261 22:12:37.133468 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 22:12:37.133621 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 22:12:37.133746 substitutions:
264 22:12:37.133813 - {DTB}: 10583861/tftp-deploy-vhgxdhl0/dtb/mt8192-asurada-spherion-r0.dtb
265 22:12:37.133877 - {INITRD}: 10583861/tftp-deploy-vhgxdhl0/ramdisk/ramdisk.cpio.gz
266 22:12:37.133937 - {KERNEL}: 10583861/tftp-deploy-vhgxdhl0/kernel/Image
267 22:12:37.133995 - {LAVA_MAC}: None
268 22:12:37.134052 - {PRESEED_CONFIG}: None
269 22:12:37.134108 - {PRESEED_LOCAL}: None
270 22:12:37.134163 - {RAMDISK}: 10583861/tftp-deploy-vhgxdhl0/ramdisk/ramdisk.cpio.gz
271 22:12:37.134219 - {ROOT_PART}: None
272 22:12:37.134274 - {ROOT}: None
273 22:12:37.134329 - {SERVER_IP}: 192.168.201.1
274 22:12:37.134383 - {TEE}: None
275 22:12:37.134438 Parsed boot commands:
276 22:12:37.134493 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 22:12:37.134662 Parsed boot commands: tftpboot 192.168.201.1 10583861/tftp-deploy-vhgxdhl0/kernel/image.itb 10583861/tftp-deploy-vhgxdhl0/kernel/cmdline
278 22:12:37.134753 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 22:12:37.134839 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 22:12:37.134935 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 22:12:37.135023 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 22:12:37.135096 Not connected, no need to disconnect.
283 22:12:37.135174 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 22:12:37.135256 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 22:12:37.135322 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-0'
286 22:12:37.138765 Setting prompt string to ['lava-test: # ']
287 22:12:37.139146 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 22:12:37.139258 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 22:12:37.139359 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 22:12:37.139450 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 22:12:37.139648 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=reboot'
292 22:12:42.269874 >> Command sent successfully.
293 22:12:42.272184 Returned 0 in 5 seconds
294 22:12:42.372602 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 22:12:42.373365 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 22:12:42.373505 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 22:12:42.373678 Setting prompt string to 'Starting depthcharge on Spherion...'
299 22:12:42.373781 Changing prompt to 'Starting depthcharge on Spherion...'
300 22:12:42.373887 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 22:12:42.374239 [Enter `^Ec?' for help]
302 22:12:42.547421
303 22:12:42.547605
304 22:12:42.547710 F0: 102B 0000
305 22:12:42.547806
306 22:12:42.547899 F3: 1001 0000 [0200]
307 22:12:42.547992
308 22:12:42.550992 F3: 1001 0000
309 22:12:42.551102
310 22:12:42.551198 F7: 102D 0000
311 22:12:42.551290
312 22:12:42.551375 F1: 0000 0000
313 22:12:42.553984
314 22:12:42.554094 V0: 0000 0000 [0001]
315 22:12:42.554193
316 22:12:42.554286 00: 0007 8000
317 22:12:42.557631
318 22:12:42.557737 01: 0000 0000
319 22:12:42.557829
320 22:12:42.557917 BP: 0C00 0209 [0000]
321 22:12:42.558007
322 22:12:42.561174 G0: 1182 0000
323 22:12:42.561279
324 22:12:42.561373 EC: 0000 0021 [4000]
325 22:12:42.561467
326 22:12:42.564494 S7: 0000 0000 [0000]
327 22:12:42.564603
328 22:12:42.564698 CC: 0000 0000 [0001]
329 22:12:42.564791
330 22:12:42.567529 T0: 0000 0040 [010F]
331 22:12:42.567637
332 22:12:42.567731 Jump to BL
333 22:12:42.567823
334 22:12:42.594064
335 22:12:42.594181
336 22:12:42.594276
337 22:12:42.601672 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 22:12:42.605114 ARM64: Exception handlers installed.
339 22:12:42.608658 ARM64: Testing exception
340 22:12:42.612314 ARM64: Done test exception
341 22:12:42.619142 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 22:12:42.628796 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 22:12:42.636041 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 22:12:42.645783 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 22:12:42.652895 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 22:12:42.659524 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 22:12:42.670921 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 22:12:42.677470 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 22:12:42.696629 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 22:12:42.700299 WDT: Last reset was cold boot
351 22:12:42.703455 SPI1(PAD0) initialized at 2873684 Hz
352 22:12:42.706699 SPI5(PAD0) initialized at 992727 Hz
353 22:12:42.710279 VBOOT: Loading verstage.
354 22:12:42.716919 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 22:12:42.720064 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 22:12:42.723502 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 22:12:42.726468 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 22:12:42.734383 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 22:12:42.740751 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 22:12:42.752109 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
361 22:12:42.752222
362 22:12:42.752318
363 22:12:42.762644 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 22:12:42.766215 ARM64: Exception handlers installed.
365 22:12:42.769243 ARM64: Testing exception
366 22:12:42.769354 ARM64: Done test exception
367 22:12:42.775948 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 22:12:42.779078 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 22:12:42.792858 Probing TPM: . done!
370 22:12:42.792971 TPM ready after 0 ms
371 22:12:42.800338 Connected to device vid:did:rid of 1ae0:0028:00
372 22:12:42.806969 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.153/cr50_v3.94_pp.113-620c9b9523
373 22:12:42.866920 Initialized TPM device CR50 revision 0
374 22:12:42.878641 tlcl_send_startup: Startup return code is 0
375 22:12:42.878763 TPM: setup succeeded
376 22:12:42.890182 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 22:12:42.899567 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 22:12:42.913054 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 22:12:42.920706 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 22:12:42.925040 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 22:12:42.928533 in-header: 03 07 00 00 08 00 00 00
382 22:12:42.931699 in-data: aa e4 47 04 13 02 00 00
383 22:12:42.931810 Chrome EC: UHEPI supported
384 22:12:42.938937 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 22:12:42.943647 in-header: 03 95 00 00 08 00 00 00
386 22:12:42.947376 in-data: 18 20 20 08 00 00 00 00
387 22:12:42.947488 Phase 1
388 22:12:42.954651 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 22:12:42.957899 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 22:12:42.966025 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 22:12:42.966132 Recovery requested (1009000e)
392 22:12:42.977156 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 22:12:42.982032 tlcl_extend: response is 0
394 22:12:42.991668 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 22:12:42.996615 tlcl_extend: response is 0
396 22:12:43.003946 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 22:12:43.023579 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
398 22:12:43.030376 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 22:12:43.030490
400 22:12:43.030582
401 22:12:43.040762 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 22:12:43.043744 ARM64: Exception handlers installed.
403 22:12:43.047074 ARM64: Testing exception
404 22:12:43.047183 ARM64: Done test exception
405 22:12:43.068975 pmic_efuse_setting: Set efuses in 11 msecs
406 22:12:43.072533 pmwrap_interface_init: Select PMIF_VLD_RDY
407 22:12:43.079609 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 22:12:43.082421 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 22:12:43.086634 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 22:12:43.093838 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 22:12:43.097448 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 22:12:43.101322 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 22:12:43.108536 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 22:12:43.112876 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 22:12:43.116517 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 22:12:43.120224 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 22:12:43.127241 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 22:12:43.130921 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 22:12:43.135117 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 22:12:43.142413 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 22:12:43.145465 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 22:12:43.153172 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 22:12:43.157057 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 22:12:43.164996 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 22:12:43.169261 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 22:12:43.176231 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 22:12:43.179814 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 22:12:43.187334 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 22:12:43.191222 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 22:12:43.198446 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 22:12:43.202167 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 22:12:43.210207 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 22:12:43.213860 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 22:12:43.217060 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 22:12:43.224804 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 22:12:43.228414 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 22:12:43.232380 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 22:12:43.240169 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 22:12:43.243264 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 22:12:43.247015 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 22:12:43.254120 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 22:12:43.258090 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 22:12:43.261752 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 22:12:43.269124 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 22:12:43.272752 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 22:12:43.277078 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 22:12:43.280486 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 22:12:43.288164 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 22:12:43.291696 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 22:12:43.295218 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 22:12:43.298671 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 22:12:43.302844 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 22:12:43.306728 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 22:12:43.310435 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 22:12:43.317165 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 22:12:43.321459 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 22:12:43.325026 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 22:12:43.332693 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 22:12:43.339763 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 22:12:43.343732 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 22:12:43.354863 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 22:12:43.362026 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 22:12:43.365996 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 22:12:43.370264 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 22:12:43.373485 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 22:12:43.382887 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x0
467 22:12:43.386787 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 22:12:43.390844 [RTC]rtc_osc_init,62: osc32con val = 0xde70
469 22:12:43.398220 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 22:12:43.406438 [RTC]rtc_get_frequency_meter,154: input=15, output=760
471 22:12:43.416479 [RTC]rtc_get_frequency_meter,154: input=23, output=942
472 22:12:43.425785 [RTC]rtc_get_frequency_meter,154: input=19, output=851
473 22:12:43.435071 [RTC]rtc_get_frequency_meter,154: input=17, output=805
474 22:12:43.444528 [RTC]rtc_get_frequency_meter,154: input=16, output=782
475 22:12:43.454711 [RTC]rtc_get_frequency_meter,154: input=16, output=782
476 22:12:43.464582 [RTC]rtc_get_frequency_meter,154: input=17, output=805
477 22:12:43.468016 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
478 22:12:43.472142 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
479 22:12:43.476004 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 22:12:43.483538 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
481 22:12:43.487183 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 22:12:43.491250 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
483 22:12:43.491362 ADC[4]: Raw value=906203 ID=7
484 22:12:43.494507 ADC[3]: Raw value=213441 ID=1
485 22:12:43.498637 RAM Code: 0x71
486 22:12:43.502211 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 22:12:43.506216 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 22:12:43.513599 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 22:12:43.521044 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 22:12:43.524750 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 22:12:43.528837 in-header: 03 07 00 00 08 00 00 00
492 22:12:43.532647 in-data: aa e4 47 04 13 02 00 00
493 22:12:43.532732 Chrome EC: UHEPI supported
494 22:12:43.539866 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 22:12:43.544441 in-header: 03 95 00 00 08 00 00 00
496 22:12:43.548838 in-data: 18 20 20 08 00 00 00 00
497 22:12:43.552219 MRC: failed to locate region type 0.
498 22:12:43.559913 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 22:12:43.560030 DRAM-K: Running full calibration
500 22:12:43.567992 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 22:12:43.568086 header.status = 0x0
502 22:12:43.571764 header.version = 0x6 (expected: 0x6)
503 22:12:43.575495 header.size = 0xd00 (expected: 0xd00)
504 22:12:43.578809 header.flags = 0x0
505 22:12:43.582466 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 22:12:43.602264 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
507 22:12:43.610457 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 22:12:43.610603 dram_init: ddr_geometry: 2
509 22:12:43.613506 [EMI] MDL number = 2
510 22:12:43.617054 [EMI] Get MDL freq = 0
511 22:12:43.617154 dram_init: ddr_type: 0
512 22:12:43.621169 is_discrete_lpddr4: 1
513 22:12:43.625002 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 22:12:43.625091
515 22:12:43.625158
516 22:12:43.625220 [Bian_co] ETT version 0.0.0.1
517 22:12:43.632435 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 22:12:43.632534
519 22:12:43.636592 dramc_set_vcore_voltage set vcore to 650000
520 22:12:43.636721 Read voltage for 800, 4
521 22:12:43.636800 Vio18 = 0
522 22:12:43.640378 Vcore = 650000
523 22:12:43.640482 Vdram = 0
524 22:12:43.640577 Vddq = 0
525 22:12:43.640648 Vmddr = 0
526 22:12:43.643904 dram_init: config_dvfs: 1
527 22:12:43.647605 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 22:12:43.655042 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 22:12:43.658742 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
530 22:12:43.662680 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
531 22:12:43.666647 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
532 22:12:43.670315 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
533 22:12:43.673376 MEM_TYPE=3, freq_sel=18
534 22:12:43.673466 sv_algorithm_assistance_LP4_1600
535 22:12:43.680118 ============ PULL DRAM RESETB DOWN ============
536 22:12:43.683173 ========== PULL DRAM RESETB DOWN end =========
537 22:12:43.686814 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 22:12:43.689850 ===================================
539 22:12:43.693941 LPDDR4 DRAM CONFIGURATION
540 22:12:43.698100 ===================================
541 22:12:43.698196 EX_ROW_EN[0] = 0x0
542 22:12:43.701956 EX_ROW_EN[1] = 0x0
543 22:12:43.702046 LP4Y_EN = 0x0
544 22:12:43.705248 WORK_FSP = 0x0
545 22:12:43.705367 WL = 0x2
546 22:12:43.709211 RL = 0x2
547 22:12:43.709346 BL = 0x2
548 22:12:43.712800 RPST = 0x0
549 22:12:43.712905 RD_PRE = 0x0
550 22:12:43.716039 WR_PRE = 0x1
551 22:12:43.716147 WR_PST = 0x0
552 22:12:43.719175 DBI_WR = 0x0
553 22:12:43.719261 DBI_RD = 0x0
554 22:12:43.722726 OTF = 0x1
555 22:12:43.726151 ===================================
556 22:12:43.729672 ===================================
557 22:12:43.729768 ANA top config
558 22:12:43.732704 ===================================
559 22:12:43.736238 DLL_ASYNC_EN = 0
560 22:12:43.736351 ALL_SLAVE_EN = 1
561 22:12:43.739335 NEW_RANK_MODE = 1
562 22:12:43.743005 DLL_IDLE_MODE = 1
563 22:12:43.746071 LP45_APHY_COMB_EN = 1
564 22:12:43.749948 TX_ODT_DIS = 1
565 22:12:43.750039 NEW_8X_MODE = 1
566 22:12:43.753417 ===================================
567 22:12:43.757233 ===================================
568 22:12:43.760326 data_rate = 1600
569 22:12:43.763406 CKR = 1
570 22:12:43.767021 DQ_P2S_RATIO = 8
571 22:12:43.770276 ===================================
572 22:12:43.770390 CA_P2S_RATIO = 8
573 22:12:43.773702 DQ_CA_OPEN = 0
574 22:12:43.777062 DQ_SEMI_OPEN = 0
575 22:12:43.780636 CA_SEMI_OPEN = 0
576 22:12:43.783492 CA_FULL_RATE = 0
577 22:12:43.787114 DQ_CKDIV4_EN = 1
578 22:12:43.787203 CA_CKDIV4_EN = 1
579 22:12:43.790425 CA_PREDIV_EN = 0
580 22:12:43.793464 PH8_DLY = 0
581 22:12:43.797093 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 22:12:43.800793 DQ_AAMCK_DIV = 4
583 22:12:43.800882 CA_AAMCK_DIV = 4
584 22:12:43.803962 CA_ADMCK_DIV = 4
585 22:12:43.807486 DQ_TRACK_CA_EN = 0
586 22:12:43.810343 CA_PICK = 800
587 22:12:43.814384 CA_MCKIO = 800
588 22:12:43.817852 MCKIO_SEMI = 0
589 22:12:43.817942 PLL_FREQ = 3068
590 22:12:43.821381 DQ_UI_PI_RATIO = 32
591 22:12:43.825503 CA_UI_PI_RATIO = 0
592 22:12:43.829378 ===================================
593 22:12:43.832906 ===================================
594 22:12:43.833000 memory_type:LPDDR4
595 22:12:43.836895 GP_NUM : 10
596 22:12:43.836985 SRAM_EN : 1
597 22:12:43.840803 MD32_EN : 0
598 22:12:43.844508 ===================================
599 22:12:43.844604 [ANA_INIT] >>>>>>>>>>>>>>
600 22:12:43.848401 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 22:12:43.851840 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 22:12:43.855000 ===================================
603 22:12:43.858096 data_rate = 1600,PCW = 0X7600
604 22:12:43.861706 ===================================
605 22:12:43.864700 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 22:12:43.871523 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 22:12:43.875051 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 22:12:43.881907 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 22:12:43.884818 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 22:12:43.888355 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 22:12:43.888446 [ANA_INIT] flow start
612 22:12:43.891904 [ANA_INIT] PLL >>>>>>>>
613 22:12:43.895153 [ANA_INIT] PLL <<<<<<<<
614 22:12:43.895241 [ANA_INIT] MIDPI >>>>>>>>
615 22:12:43.898215 [ANA_INIT] MIDPI <<<<<<<<
616 22:12:43.901772 [ANA_INIT] DLL >>>>>>>>
617 22:12:43.901858 [ANA_INIT] flow end
618 22:12:43.908351 ============ LP4 DIFF to SE enter ============
619 22:12:43.911728 ============ LP4 DIFF to SE exit ============
620 22:12:43.911824 [ANA_INIT] <<<<<<<<<<<<<
621 22:12:43.915159 [Flow] Enable top DCM control >>>>>
622 22:12:43.918215 [Flow] Enable top DCM control <<<<<
623 22:12:43.921429 Enable DLL master slave shuffle
624 22:12:43.928167 ==============================================================
625 22:12:43.931731 Gating Mode config
626 22:12:43.935156 ==============================================================
627 22:12:43.938457 Config description:
628 22:12:43.948119 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 22:12:43.954909 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 22:12:43.958387 SELPH_MODE 0: By rank 1: By Phase
631 22:12:43.965068 ==============================================================
632 22:12:43.968112 GAT_TRACK_EN = 1
633 22:12:43.972036 RX_GATING_MODE = 2
634 22:12:43.972128 RX_GATING_TRACK_MODE = 2
635 22:12:43.975008 SELPH_MODE = 1
636 22:12:43.978708 PICG_EARLY_EN = 1
637 22:12:43.982159 VALID_LAT_VALUE = 1
638 22:12:43.988448 ==============================================================
639 22:12:43.991853 Enter into Gating configuration >>>>
640 22:12:43.995391 Exit from Gating configuration <<<<
641 22:12:43.998417 Enter into DVFS_PRE_config >>>>>
642 22:12:44.008524 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 22:12:44.011958 Exit from DVFS_PRE_config <<<<<
644 22:12:44.015004 Enter into PICG configuration >>>>
645 22:12:44.018239 Exit from PICG configuration <<<<
646 22:12:44.021747 [RX_INPUT] configuration >>>>>
647 22:12:44.025213 [RX_INPUT] configuration <<<<<
648 22:12:44.028552 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 22:12:44.035184 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 22:12:44.042146 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 22:12:44.045316 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 22:12:44.051952 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 22:12:44.058716 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 22:12:44.062364 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 22:12:44.065451 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 22:12:44.072116 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 22:12:44.075238 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 22:12:44.078348 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 22:12:44.085127 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 22:12:44.085234 ===================================
661 22:12:44.088792 LPDDR4 DRAM CONFIGURATION
662 22:12:44.091714 ===================================
663 22:12:44.095506 EX_ROW_EN[0] = 0x0
664 22:12:44.095601 EX_ROW_EN[1] = 0x0
665 22:12:44.098522 LP4Y_EN = 0x0
666 22:12:44.098611 WORK_FSP = 0x0
667 22:12:44.102190 WL = 0x2
668 22:12:44.102278 RL = 0x2
669 22:12:44.105224 BL = 0x2
670 22:12:44.105310 RPST = 0x0
671 22:12:44.108896 RD_PRE = 0x0
672 22:12:44.108990 WR_PRE = 0x1
673 22:12:44.111867 WR_PST = 0x0
674 22:12:44.115468 DBI_WR = 0x0
675 22:12:44.115560 DBI_RD = 0x0
676 22:12:44.118438 OTF = 0x1
677 22:12:44.121931 ===================================
678 22:12:44.125364 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 22:12:44.128888 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 22:12:44.132253 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 22:12:44.135651 ===================================
682 22:12:44.139045 LPDDR4 DRAM CONFIGURATION
683 22:12:44.142196 ===================================
684 22:12:44.145734 EX_ROW_EN[0] = 0x10
685 22:12:44.145825 EX_ROW_EN[1] = 0x0
686 22:12:44.149279 LP4Y_EN = 0x0
687 22:12:44.149374 WORK_FSP = 0x0
688 22:12:44.152432 WL = 0x2
689 22:12:44.152526 RL = 0x2
690 22:12:44.155963 BL = 0x2
691 22:12:44.156053 RPST = 0x0
692 22:12:44.159038 RD_PRE = 0x0
693 22:12:44.159126 WR_PRE = 0x1
694 22:12:44.162758 WR_PST = 0x0
695 22:12:44.162847 DBI_WR = 0x0
696 22:12:44.165781 DBI_RD = 0x0
697 22:12:44.165872 OTF = 0x1
698 22:12:44.169472 ===================================
699 22:12:44.175707 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 22:12:44.179917 nWR fixed to 40
701 22:12:44.183660 [ModeRegInit_LP4] CH0 RK0
702 22:12:44.183753 [ModeRegInit_LP4] CH0 RK1
703 22:12:44.186844 [ModeRegInit_LP4] CH1 RK0
704 22:12:44.190254 [ModeRegInit_LP4] CH1 RK1
705 22:12:44.190346 match AC timing 13
706 22:12:44.197001 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 22:12:44.200350 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 22:12:44.203731 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 22:12:44.210196 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 22:12:44.213408 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 22:12:44.213516 [EMI DOE] emi_dcm 0
712 22:12:44.220163 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 22:12:44.220266 ==
714 22:12:44.223876 Dram Type= 6, Freq= 0, CH_0, rank 0
715 22:12:44.227311 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 22:12:44.227409 ==
717 22:12:44.233450 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 22:12:44.236984 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 22:12:44.247346 [CA 0] Center 36 (6~67) winsize 62
720 22:12:44.250980 [CA 1] Center 36 (6~67) winsize 62
721 22:12:44.254227 [CA 2] Center 34 (4~65) winsize 62
722 22:12:44.257456 [CA 3] Center 33 (3~64) winsize 62
723 22:12:44.260962 [CA 4] Center 33 (3~63) winsize 61
724 22:12:44.264011 [CA 5] Center 32 (3~62) winsize 60
725 22:12:44.264106
726 22:12:44.267647 [CmdBusTrainingLP45] Vref(ca) range 1: 32
727 22:12:44.267735
728 22:12:44.270739 [CATrainingPosCal] consider 1 rank data
729 22:12:44.274385 u2DelayCellTimex100 = 270/100 ps
730 22:12:44.277307 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
731 22:12:44.281093 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
732 22:12:44.287770 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
733 22:12:44.291008 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
734 22:12:44.294624 CA4 delay=33 (3~63),Diff = 1 PI (7 cell)
735 22:12:44.297684 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
736 22:12:44.297784
737 22:12:44.300668 CA PerBit enable=1, Macro0, CA PI delay=32
738 22:12:44.300753
739 22:12:44.304208 [CBTSetCACLKResult] CA Dly = 32
740 22:12:44.304294 CS Dly: 5 (0~36)
741 22:12:44.304361 ==
742 22:12:44.307710 Dram Type= 6, Freq= 0, CH_0, rank 1
743 22:12:44.314369 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 22:12:44.314482 ==
745 22:12:44.317823 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 22:12:44.324725 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 22:12:44.334059 [CA 0] Center 36 (6~67) winsize 62
748 22:12:44.336989 [CA 1] Center 36 (6~67) winsize 62
749 22:12:44.340354 [CA 2] Center 34 (4~65) winsize 62
750 22:12:44.343896 [CA 3] Center 33 (3~64) winsize 62
751 22:12:44.347365 [CA 4] Center 33 (3~63) winsize 61
752 22:12:44.350675 [CA 5] Center 32 (2~63) winsize 62
753 22:12:44.350767
754 22:12:44.353632 [CmdBusTrainingLP45] Vref(ca) range 1: 34
755 22:12:44.353718
756 22:12:44.357387 [CATrainingPosCal] consider 2 rank data
757 22:12:44.360362 u2DelayCellTimex100 = 270/100 ps
758 22:12:44.364002 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
759 22:12:44.367562 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
760 22:12:44.370863 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
761 22:12:44.377200 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
762 22:12:44.380361 CA4 delay=33 (3~63),Diff = 1 PI (7 cell)
763 22:12:44.383885 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
764 22:12:44.383981
765 22:12:44.387747 CA PerBit enable=1, Macro0, CA PI delay=32
766 22:12:44.387839
767 22:12:44.390662 [CBTSetCACLKResult] CA Dly = 32
768 22:12:44.390750 CS Dly: 5 (0~36)
769 22:12:44.390818
770 22:12:44.394404 ----->DramcWriteLeveling(PI) begin...
771 22:12:44.394494 ==
772 22:12:44.398199 Dram Type= 6, Freq= 0, CH_0, rank 0
773 22:12:44.402259 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 22:12:44.402363 ==
775 22:12:44.406182 Write leveling (Byte 0): 32 => 32
776 22:12:44.409901 Write leveling (Byte 1): 28 => 28
777 22:12:44.413334 DramcWriteLeveling(PI) end<-----
778 22:12:44.413437
779 22:12:44.413507 ==
780 22:12:44.416299 Dram Type= 6, Freq= 0, CH_0, rank 0
781 22:12:44.419885 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 22:12:44.419975 ==
783 22:12:44.423749 [Gating] SW mode calibration
784 22:12:44.430299 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 22:12:44.434072 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 22:12:44.440452 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 22:12:44.443932 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
788 22:12:44.446970 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
789 22:12:44.453586 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 22:12:44.457216 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 22:12:44.460870 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 22:12:44.466971 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 22:12:44.470721 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 22:12:44.473772 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 22:12:44.480542 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 22:12:44.484097 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 22:12:44.487009 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 22:12:44.493722 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 22:12:44.497332 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 22:12:44.500422 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 22:12:44.503691 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 22:12:44.510822 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
803 22:12:44.513947 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
804 22:12:44.517433 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
805 22:12:44.523581 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 22:12:44.527072 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 22:12:44.530320 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 22:12:44.537441 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 22:12:44.540433 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 22:12:44.543906 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 22:12:44.550403 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 22:12:44.553894 0 9 8 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (0 0)
813 22:12:44.557373 0 9 12 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
814 22:12:44.563803 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 22:12:44.567359 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 22:12:44.570869 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 22:12:44.577482 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 22:12:44.581023 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 22:12:44.584071 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
820 22:12:44.587131 0 10 8 | B1->B0 | 3030 2424 | 1 0 | (1 0) (0 0)
821 22:12:44.593832 0 10 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
822 22:12:44.596988 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 22:12:44.600453 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 22:12:44.607189 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 22:12:44.610769 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 22:12:44.613802 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 22:12:44.620552 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 22:12:44.623993 0 11 8 | B1->B0 | 2f2f 4040 | 0 0 | (0 0) (0 0)
829 22:12:44.627369 0 11 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
830 22:12:44.633706 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 22:12:44.637261 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 22:12:44.640930 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 22:12:44.647614 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 22:12:44.650576 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 22:12:44.654124 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
836 22:12:44.660615 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
837 22:12:44.664204 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 22:12:44.667639 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 22:12:44.670460 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 22:12:44.677919 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 22:12:44.680803 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 22:12:44.684239 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 22:12:44.691056 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 22:12:44.694136 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 22:12:44.697459 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 22:12:44.704129 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 22:12:44.707744 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 22:12:44.710844 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 22:12:44.717395 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 22:12:44.721275 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 22:12:44.724402 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
852 22:12:44.731110 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
853 22:12:44.731234 Total UI for P1: 0, mck2ui 16
854 22:12:44.734115 best dqsien dly found for B0: ( 0, 14, 4)
855 22:12:44.740967 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
856 22:12:44.744454 Total UI for P1: 0, mck2ui 16
857 22:12:44.748153 best dqsien dly found for B1: ( 0, 14, 10)
858 22:12:44.751707 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
859 22:12:44.755084 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
860 22:12:44.755203
861 22:12:44.758446 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
862 22:12:44.761892 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
863 22:12:44.764699 [Gating] SW calibration Done
864 22:12:44.764790 ==
865 22:12:44.768299 Dram Type= 6, Freq= 0, CH_0, rank 0
866 22:12:44.771545 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
867 22:12:44.771636 ==
868 22:12:44.775201 RX Vref Scan: 0
869 22:12:44.775290
870 22:12:44.775359 RX Vref 0 -> 0, step: 1
871 22:12:44.775421
872 22:12:44.778281 RX Delay -130 -> 252, step: 16
873 22:12:44.782037 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
874 22:12:44.788587 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
875 22:12:44.791584 iDelay=206, Bit 2, Center 85 (-34 ~ 205) 240
876 22:12:44.795251 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
877 22:12:44.798395 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
878 22:12:44.801807 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
879 22:12:44.808361 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
880 22:12:44.811895 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
881 22:12:44.815018 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
882 22:12:44.818631 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
883 22:12:44.821542 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
884 22:12:44.828563 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
885 22:12:44.832087 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
886 22:12:44.834879 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
887 22:12:44.838518 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
888 22:12:44.841490 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
889 22:12:44.841620 ==
890 22:12:44.845473 Dram Type= 6, Freq= 0, CH_0, rank 0
891 22:12:44.851804 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
892 22:12:44.851904 ==
893 22:12:44.852007 DQS Delay:
894 22:12:44.854913 DQS0 = 0, DQS1 = 0
895 22:12:44.855000 DQM Delay:
896 22:12:44.855066 DQM0 = 89, DQM1 = 82
897 22:12:44.858588 DQ Delay:
898 22:12:44.862124 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85
899 22:12:44.864974 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
900 22:12:44.868358 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
901 22:12:44.871814 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
902 22:12:44.871907
903 22:12:44.872005
904 22:12:44.872066 ==
905 22:12:44.875150 Dram Type= 6, Freq= 0, CH_0, rank 0
906 22:12:44.878619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
907 22:12:44.878708 ==
908 22:12:44.878776
909 22:12:44.878836
910 22:12:44.881795 TX Vref Scan disable
911 22:12:44.881881 == TX Byte 0 ==
912 22:12:44.888450 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
913 22:12:44.891773 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
914 22:12:44.891870 == TX Byte 1 ==
915 22:12:44.898412 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
916 22:12:44.902318 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
917 22:12:44.902415 ==
918 22:12:44.905170 Dram Type= 6, Freq= 0, CH_0, rank 0
919 22:12:44.908372 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
920 22:12:44.908470 ==
921 22:12:44.923225 TX Vref=22, minBit 1, minWin=27, winSum=446
922 22:12:44.926216 TX Vref=24, minBit 4, minWin=27, winSum=450
923 22:12:44.929908 TX Vref=26, minBit 10, minWin=27, winSum=457
924 22:12:44.932946 TX Vref=28, minBit 4, minWin=28, winSum=456
925 22:12:44.936367 TX Vref=30, minBit 0, minWin=28, winSum=457
926 22:12:44.939450 TX Vref=32, minBit 0, minWin=28, winSum=455
927 22:12:44.946295 [TxChooseVref] Worse bit 0, Min win 28, Win sum 457, Final Vref 30
928 22:12:44.946413
929 22:12:44.949998 Final TX Range 1 Vref 30
930 22:12:44.950091
931 22:12:44.950178 ==
932 22:12:44.953030 Dram Type= 6, Freq= 0, CH_0, rank 0
933 22:12:44.956706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 22:12:44.956799 ==
935 22:12:44.956886
936 22:12:44.959440
937 22:12:44.959526 TX Vref Scan disable
938 22:12:44.963008 == TX Byte 0 ==
939 22:12:44.966545 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
940 22:12:44.969478 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
941 22:12:44.973314 == TX Byte 1 ==
942 22:12:44.976160 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
943 22:12:44.979493 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
944 22:12:44.982860
945 22:12:44.982955 [DATLAT]
946 22:12:44.983042 Freq=800, CH0 RK0
947 22:12:44.983138
948 22:12:44.986082 DATLAT Default: 0xa
949 22:12:44.986171 0, 0xFFFF, sum = 0
950 22:12:44.989572 1, 0xFFFF, sum = 0
951 22:12:44.989663 2, 0xFFFF, sum = 0
952 22:12:44.992982 3, 0xFFFF, sum = 0
953 22:12:44.993073 4, 0xFFFF, sum = 0
954 22:12:44.996317 5, 0xFFFF, sum = 0
955 22:12:44.996409 6, 0xFFFF, sum = 0
956 22:12:44.999610 7, 0xFFFF, sum = 0
957 22:12:45.002908 8, 0xFFFF, sum = 0
958 22:12:45.003006 9, 0x0, sum = 1
959 22:12:45.003095 10, 0x0, sum = 2
960 22:12:45.006768 11, 0x0, sum = 3
961 22:12:45.006859 12, 0x0, sum = 4
962 22:12:45.009703 best_step = 10
963 22:12:45.009816
964 22:12:45.009921 ==
965 22:12:45.013343 Dram Type= 6, Freq= 0, CH_0, rank 0
966 22:12:45.016475 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
967 22:12:45.016567 ==
968 22:12:45.020024 RX Vref Scan: 1
969 22:12:45.020113
970 22:12:45.020179 Set Vref Range= 32 -> 127
971 22:12:45.020241
972 22:12:45.023426 RX Vref 32 -> 127, step: 1
973 22:12:45.023513
974 22:12:45.026389 RX Delay -95 -> 252, step: 8
975 22:12:45.026477
976 22:12:45.029683 Set Vref, RX VrefLevel [Byte0]: 32
977 22:12:45.033134 [Byte1]: 32
978 22:12:45.033224
979 22:12:45.036766 Set Vref, RX VrefLevel [Byte0]: 33
980 22:12:45.040280 [Byte1]: 33
981 22:12:45.043111
982 22:12:45.043200 Set Vref, RX VrefLevel [Byte0]: 34
983 22:12:45.046737 [Byte1]: 34
984 22:12:45.051022
985 22:12:45.051125 Set Vref, RX VrefLevel [Byte0]: 35
986 22:12:45.054107 [Byte1]: 35
987 22:12:45.058990
988 22:12:45.059084 Set Vref, RX VrefLevel [Byte0]: 36
989 22:12:45.062718 [Byte1]: 36
990 22:12:45.066335
991 22:12:45.066430 Set Vref, RX VrefLevel [Byte0]: 37
992 22:12:45.069757 [Byte1]: 37
993 22:12:45.074663
994 22:12:45.074763 Set Vref, RX VrefLevel [Byte0]: 38
995 22:12:45.077631 [Byte1]: 38
996 22:12:45.081270
997 22:12:45.081366 Set Vref, RX VrefLevel [Byte0]: 39
998 22:12:45.084715 [Byte1]: 39
999 22:12:45.089065
1000 22:12:45.089171 Set Vref, RX VrefLevel [Byte0]: 40
1001 22:12:45.092638 [Byte1]: 40
1002 22:12:45.096686
1003 22:12:45.096780 Set Vref, RX VrefLevel [Byte0]: 41
1004 22:12:45.100115 [Byte1]: 41
1005 22:12:45.103761
1006 22:12:45.103884 Set Vref, RX VrefLevel [Byte0]: 42
1007 22:12:45.107315 [Byte1]: 42
1008 22:12:45.111949
1009 22:12:45.112055 Set Vref, RX VrefLevel [Byte0]: 43
1010 22:12:45.114907 [Byte1]: 43
1011 22:12:45.119225
1012 22:12:45.119320 Set Vref, RX VrefLevel [Byte0]: 44
1013 22:12:45.122865 [Byte1]: 44
1014 22:12:45.126961
1015 22:12:45.127051 Set Vref, RX VrefLevel [Byte0]: 45
1016 22:12:45.130456 [Byte1]: 45
1017 22:12:45.134587
1018 22:12:45.134681 Set Vref, RX VrefLevel [Byte0]: 46
1019 22:12:45.137468 [Byte1]: 46
1020 22:12:45.142353
1021 22:12:45.142442 Set Vref, RX VrefLevel [Byte0]: 47
1022 22:12:45.145119 [Byte1]: 47
1023 22:12:45.150010
1024 22:12:45.150106 Set Vref, RX VrefLevel [Byte0]: 48
1025 22:12:45.153017 [Byte1]: 48
1026 22:12:45.157356
1027 22:12:45.157444 Set Vref, RX VrefLevel [Byte0]: 49
1028 22:12:45.160456 [Byte1]: 49
1029 22:12:45.165374
1030 22:12:45.165468 Set Vref, RX VrefLevel [Byte0]: 50
1031 22:12:45.168289 [Byte1]: 50
1032 22:12:45.172357
1033 22:12:45.172445 Set Vref, RX VrefLevel [Byte0]: 51
1034 22:12:45.176009 [Byte1]: 51
1035 22:12:45.180316
1036 22:12:45.180403 Set Vref, RX VrefLevel [Byte0]: 52
1037 22:12:45.186460 [Byte1]: 52
1038 22:12:45.186554
1039 22:12:45.190058 Set Vref, RX VrefLevel [Byte0]: 53
1040 22:12:45.193419 [Byte1]: 53
1041 22:12:45.193518
1042 22:12:45.196409 Set Vref, RX VrefLevel [Byte0]: 54
1043 22:12:45.200223 [Byte1]: 54
1044 22:12:45.200314
1045 22:12:45.203416 Set Vref, RX VrefLevel [Byte0]: 55
1046 22:12:45.206404 [Byte1]: 55
1047 22:12:45.210758
1048 22:12:45.210858 Set Vref, RX VrefLevel [Byte0]: 56
1049 22:12:45.213969 [Byte1]: 56
1050 22:12:45.218318
1051 22:12:45.218408 Set Vref, RX VrefLevel [Byte0]: 57
1052 22:12:45.221286 [Byte1]: 57
1053 22:12:45.225828
1054 22:12:45.225920 Set Vref, RX VrefLevel [Byte0]: 58
1055 22:12:45.229304 [Byte1]: 58
1056 22:12:45.233401
1057 22:12:45.233491 Set Vref, RX VrefLevel [Byte0]: 59
1058 22:12:45.236601 [Byte1]: 59
1059 22:12:45.241047
1060 22:12:45.241144 Set Vref, RX VrefLevel [Byte0]: 60
1061 22:12:45.244155 [Byte1]: 60
1062 22:12:45.248516
1063 22:12:45.248607 Set Vref, RX VrefLevel [Byte0]: 61
1064 22:12:45.252023 [Byte1]: 61
1065 22:12:45.256008
1066 22:12:45.256097 Set Vref, RX VrefLevel [Byte0]: 62
1067 22:12:45.259060 [Byte1]: 62
1068 22:12:45.263615
1069 22:12:45.263703 Set Vref, RX VrefLevel [Byte0]: 63
1070 22:12:45.266805 [Byte1]: 63
1071 22:12:45.271119
1072 22:12:45.271207 Set Vref, RX VrefLevel [Byte0]: 64
1073 22:12:45.274773 [Byte1]: 64
1074 22:12:45.278783
1075 22:12:45.278870 Set Vref, RX VrefLevel [Byte0]: 65
1076 22:12:45.282004 [Byte1]: 65
1077 22:12:45.286884
1078 22:12:45.286971 Set Vref, RX VrefLevel [Byte0]: 66
1079 22:12:45.289855 [Byte1]: 66
1080 22:12:45.294112
1081 22:12:45.294200 Set Vref, RX VrefLevel [Byte0]: 67
1082 22:12:45.297176 [Byte1]: 67
1083 22:12:45.301931
1084 22:12:45.302024 Set Vref, RX VrefLevel [Byte0]: 68
1085 22:12:45.304841 [Byte1]: 68
1086 22:12:45.309439
1087 22:12:45.309597 Set Vref, RX VrefLevel [Byte0]: 69
1088 22:12:45.312353 [Byte1]: 69
1089 22:12:45.317129
1090 22:12:45.317222 Set Vref, RX VrefLevel [Byte0]: 70
1091 22:12:45.320248 [Byte1]: 70
1092 22:12:45.324422
1093 22:12:45.324510 Set Vref, RX VrefLevel [Byte0]: 71
1094 22:12:45.327915 [Byte1]: 71
1095 22:12:45.331787
1096 22:12:45.331876 Set Vref, RX VrefLevel [Byte0]: 72
1097 22:12:45.335522 [Byte1]: 72
1098 22:12:45.339779
1099 22:12:45.339882 Set Vref, RX VrefLevel [Byte0]: 73
1100 22:12:45.343044 [Byte1]: 73
1101 22:12:45.347322
1102 22:12:45.347416 Set Vref, RX VrefLevel [Byte0]: 74
1103 22:12:45.350375 [Byte1]: 74
1104 22:12:45.354647
1105 22:12:45.354737 Set Vref, RX VrefLevel [Byte0]: 75
1106 22:12:45.358206 [Byte1]: 75
1107 22:12:45.362402
1108 22:12:45.362491 Set Vref, RX VrefLevel [Byte0]: 76
1109 22:12:45.365639 [Byte1]: 76
1110 22:12:45.370334
1111 22:12:45.370425 Set Vref, RX VrefLevel [Byte0]: 77
1112 22:12:45.373407 [Byte1]: 77
1113 22:12:45.377649
1114 22:12:45.377737 Final RX Vref Byte 0 = 58 to rank0
1115 22:12:45.380701 Final RX Vref Byte 1 = 53 to rank0
1116 22:12:45.384149 Final RX Vref Byte 0 = 58 to rank1
1117 22:12:45.387718 Final RX Vref Byte 1 = 53 to rank1==
1118 22:12:45.390965 Dram Type= 6, Freq= 0, CH_0, rank 0
1119 22:12:45.397481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1120 22:12:45.397628 ==
1121 22:12:45.397695 DQS Delay:
1122 22:12:45.397756 DQS0 = 0, DQS1 = 0
1123 22:12:45.401272 DQM Delay:
1124 22:12:45.401357 DQM0 = 92, DQM1 = 85
1125 22:12:45.404111 DQ Delay:
1126 22:12:45.407622 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1127 22:12:45.411124 DQ4 =96, DQ5 =80, DQ6 =100, DQ7 =100
1128 22:12:45.411220 DQ8 =72, DQ9 =76, DQ10 =88, DQ11 =76
1129 22:12:45.417656 DQ12 =92, DQ13 =92, DQ14 =96, DQ15 =92
1130 22:12:45.417762
1131 22:12:45.417828
1132 22:12:45.424470 [DQSOSCAuto] RK0, (LSB)MR18= 0x4d43, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 390 ps
1133 22:12:45.428008 CH0 RK0: MR19=606, MR18=4D43
1134 22:12:45.434353 CH0_RK0: MR19=0x606, MR18=0x4D43, DQSOSC=390, MR23=63, INC=97, DEC=64
1135 22:12:45.434464
1136 22:12:45.438004 ----->DramcWriteLeveling(PI) begin...
1137 22:12:45.438097 ==
1138 22:12:45.441338 Dram Type= 6, Freq= 0, CH_0, rank 1
1139 22:12:45.444380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1140 22:12:45.444468 ==
1141 22:12:45.447936 Write leveling (Byte 0): 34 => 34
1142 22:12:45.451528 Write leveling (Byte 1): 31 => 31
1143 22:12:45.454756 DramcWriteLeveling(PI) end<-----
1144 22:12:45.454846
1145 22:12:45.454912 ==
1146 22:12:45.458350 Dram Type= 6, Freq= 0, CH_0, rank 1
1147 22:12:45.461795 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1148 22:12:45.461883 ==
1149 22:12:45.464703 [Gating] SW mode calibration
1150 22:12:45.511858 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1151 22:12:45.512023 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1152 22:12:45.512316 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1153 22:12:45.512425 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1154 22:12:45.512501 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1155 22:12:45.512922 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 22:12:45.513190 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 22:12:45.513275 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 22:12:45.513342 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 22:12:45.513435 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 22:12:45.556171 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 22:12:45.556594 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 22:12:45.557302 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 22:12:45.557386 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 22:12:45.557980 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 22:12:45.558242 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 22:12:45.558311 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 22:12:45.558553 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 22:12:45.558618 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 22:12:45.558690 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1170 22:12:45.574655 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1171 22:12:45.575336 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1172 22:12:45.575613 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 22:12:45.575686 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 22:12:45.578453 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 22:12:45.581429 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 22:12:45.588235 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 22:12:45.591826 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 22:12:45.594697 0 9 8 | B1->B0 | 2c2c 2828 | 0 0 | (0 0) (0 0)
1179 22:12:45.598130 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1180 22:12:45.604867 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 22:12:45.608684 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1182 22:12:45.611552 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1183 22:12:45.618192 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1184 22:12:45.621550 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1185 22:12:45.625260 0 10 4 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
1186 22:12:45.631969 0 10 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (1 0)
1187 22:12:45.635718 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 22:12:45.639035 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 22:12:45.642435 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 22:12:45.649437 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 22:12:45.653399 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 22:12:45.656479 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 22:12:45.660076 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 22:12:45.666833 0 11 8 | B1->B0 | 4040 3939 | 0 1 | (0 0) (0 0)
1195 22:12:45.670436 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1196 22:12:45.673855 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 22:12:45.680211 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 22:12:45.683745 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 22:12:45.686818 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 22:12:45.690568 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1201 22:12:45.697427 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1202 22:12:45.700291 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1203 22:12:45.703735 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1204 22:12:45.710543 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 22:12:45.713728 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 22:12:45.717282 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 22:12:45.724036 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 22:12:45.727225 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 22:12:45.731053 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 22:12:45.737244 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 22:12:45.740636 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 22:12:45.744104 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 22:12:45.750638 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 22:12:45.754167 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 22:12:45.757085 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 22:12:45.763951 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 22:12:45.767067 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1218 22:12:45.770821 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1219 22:12:45.773854 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1220 22:12:45.777008 Total UI for P1: 0, mck2ui 16
1221 22:12:45.780947 best dqsien dly found for B0: ( 0, 14, 6)
1222 22:12:45.784230 Total UI for P1: 0, mck2ui 16
1223 22:12:45.787350 best dqsien dly found for B1: ( 0, 14, 8)
1224 22:12:45.790410 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1225 22:12:45.793935 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1226 22:12:45.797104
1227 22:12:45.800630 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1228 22:12:45.804379 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1229 22:12:45.804472 [Gating] SW calibration Done
1230 22:12:45.808123 ==
1231 22:12:45.810730 Dram Type= 6, Freq= 0, CH_0, rank 1
1232 22:12:45.814434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1233 22:12:45.814532 ==
1234 22:12:45.814600 RX Vref Scan: 0
1235 22:12:45.814663
1236 22:12:45.817419 RX Vref 0 -> 0, step: 1
1237 22:12:45.817504
1238 22:12:45.821115 RX Delay -130 -> 252, step: 16
1239 22:12:45.824260 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1240 22:12:45.827451 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1241 22:12:45.830952 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
1242 22:12:45.837704 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1243 22:12:45.841175 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1244 22:12:45.844104 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1245 22:12:45.847954 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1246 22:12:45.850899 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1247 22:12:45.857740 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1248 22:12:45.861243 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1249 22:12:45.864142 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1250 22:12:45.867780 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1251 22:12:45.871362 iDelay=222, Bit 12, Center 85 (-18 ~ 189) 208
1252 22:12:45.878176 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1253 22:12:45.881093 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1254 22:12:45.884496 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1255 22:12:45.884587 ==
1256 22:12:45.887862 Dram Type= 6, Freq= 0, CH_0, rank 1
1257 22:12:45.891368 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1258 22:12:45.891456 ==
1259 22:12:45.894378 DQS Delay:
1260 22:12:45.894463 DQS0 = 0, DQS1 = 0
1261 22:12:45.897797 DQM Delay:
1262 22:12:45.897881 DQM0 = 93, DQM1 = 84
1263 22:12:45.897947 DQ Delay:
1264 22:12:45.901501 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =93
1265 22:12:45.904757 DQ4 =93, DQ5 =85, DQ6 =93, DQ7 =101
1266 22:12:45.908427 DQ8 =77, DQ9 =77, DQ10 =77, DQ11 =77
1267 22:12:45.911220 DQ12 =85, DQ13 =93, DQ14 =93, DQ15 =93
1268 22:12:45.911308
1269 22:12:45.911373
1270 22:12:45.911433 ==
1271 22:12:45.914795 Dram Type= 6, Freq= 0, CH_0, rank 1
1272 22:12:45.921175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1273 22:12:45.921289 ==
1274 22:12:45.921360
1275 22:12:45.921421
1276 22:12:45.921480 TX Vref Scan disable
1277 22:12:45.925477 == TX Byte 0 ==
1278 22:12:45.928488 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1279 22:12:45.932231 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1280 22:12:45.935289 == TX Byte 1 ==
1281 22:12:45.938803 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1282 22:12:45.941824 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1283 22:12:45.945162 ==
1284 22:12:45.948382 Dram Type= 6, Freq= 0, CH_0, rank 1
1285 22:12:45.952217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1286 22:12:45.952312 ==
1287 22:12:45.964347 TX Vref=22, minBit 8, minWin=27, winSum=447
1288 22:12:45.967724 TX Vref=24, minBit 9, minWin=27, winSum=451
1289 22:12:45.971312 TX Vref=26, minBit 1, minWin=28, winSum=455
1290 22:12:45.975056 TX Vref=28, minBit 1, minWin=28, winSum=454
1291 22:12:45.978029 TX Vref=30, minBit 8, minWin=27, winSum=450
1292 22:12:45.981020 TX Vref=32, minBit 10, minWin=27, winSum=452
1293 22:12:45.988191 [TxChooseVref] Worse bit 1, Min win 28, Win sum 455, Final Vref 26
1294 22:12:45.988317
1295 22:12:45.991173 Final TX Range 1 Vref 26
1296 22:12:45.991258
1297 22:12:45.991323 ==
1298 22:12:45.995044 Dram Type= 6, Freq= 0, CH_0, rank 1
1299 22:12:45.998087 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1300 22:12:45.998175 ==
1301 22:12:45.998239
1302 22:12:46.001398
1303 22:12:46.001482 TX Vref Scan disable
1304 22:12:46.004268 == TX Byte 0 ==
1305 22:12:46.008156 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1306 22:12:46.011305 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1307 22:12:46.014733 == TX Byte 1 ==
1308 22:12:46.017709 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1309 22:12:46.024332 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1310 22:12:46.024442
1311 22:12:46.024508 [DATLAT]
1312 22:12:46.024568 Freq=800, CH0 RK1
1313 22:12:46.024626
1314 22:12:46.028225 DATLAT Default: 0xa
1315 22:12:46.028336 0, 0xFFFF, sum = 0
1316 22:12:46.031436 1, 0xFFFF, sum = 0
1317 22:12:46.031540 2, 0xFFFF, sum = 0
1318 22:12:46.034378 3, 0xFFFF, sum = 0
1319 22:12:46.034463 4, 0xFFFF, sum = 0
1320 22:12:46.038082 5, 0xFFFF, sum = 0
1321 22:12:46.038167 6, 0xFFFF, sum = 0
1322 22:12:46.041216 7, 0xFFFF, sum = 0
1323 22:12:46.044694 8, 0xFFFF, sum = 0
1324 22:12:46.044782 9, 0x0, sum = 1
1325 22:12:46.044849 10, 0x0, sum = 2
1326 22:12:46.048378 11, 0x0, sum = 3
1327 22:12:46.048463 12, 0x0, sum = 4
1328 22:12:46.051059 best_step = 10
1329 22:12:46.051143
1330 22:12:46.051207 ==
1331 22:12:46.054664 Dram Type= 6, Freq= 0, CH_0, rank 1
1332 22:12:46.057987 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1333 22:12:46.058076 ==
1334 22:12:46.061355 RX Vref Scan: 0
1335 22:12:46.061440
1336 22:12:46.061503 RX Vref 0 -> 0, step: 1
1337 22:12:46.061644
1338 22:12:46.064672 RX Delay -79 -> 252, step: 8
1339 22:12:46.071058 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1340 22:12:46.074366 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1341 22:12:46.077806 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1342 22:12:46.081416 iDelay=209, Bit 3, Center 88 (-23 ~ 200) 224
1343 22:12:46.084524 iDelay=209, Bit 4, Center 96 (-15 ~ 208) 224
1344 22:12:46.091200 iDelay=209, Bit 5, Center 88 (-23 ~ 200) 224
1345 22:12:46.094555 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1346 22:12:46.097885 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1347 22:12:46.101438 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
1348 22:12:46.104991 iDelay=209, Bit 9, Center 76 (-31 ~ 184) 216
1349 22:12:46.111690 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1350 22:12:46.114540 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1351 22:12:46.118217 iDelay=209, Bit 12, Center 88 (-15 ~ 192) 208
1352 22:12:46.121194 iDelay=209, Bit 13, Center 88 (-15 ~ 192) 208
1353 22:12:46.124990 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1354 22:12:46.131576 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1355 22:12:46.131683 ==
1356 22:12:46.134724 Dram Type= 6, Freq= 0, CH_0, rank 1
1357 22:12:46.138369 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1358 22:12:46.138458 ==
1359 22:12:46.138523 DQS Delay:
1360 22:12:46.141310 DQS0 = 0, DQS1 = 0
1361 22:12:46.141395 DQM Delay:
1362 22:12:46.145011 DQM0 = 93, DQM1 = 83
1363 22:12:46.145099 DQ Delay:
1364 22:12:46.148048 DQ0 =92, DQ1 =92, DQ2 =88, DQ3 =88
1365 22:12:46.151366 DQ4 =96, DQ5 =88, DQ6 =100, DQ7 =100
1366 22:12:46.154928 DQ8 =76, DQ9 =76, DQ10 =84, DQ11 =76
1367 22:12:46.157907 DQ12 =88, DQ13 =88, DQ14 =92, DQ15 =88
1368 22:12:46.157996
1369 22:12:46.158063
1370 22:12:46.164860 [DQSOSCAuto] RK1, (LSB)MR18= 0x4314, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 393 ps
1371 22:12:46.167957 CH0 RK1: MR19=606, MR18=4314
1372 22:12:46.174660 CH0_RK1: MR19=0x606, MR18=0x4314, DQSOSC=393, MR23=63, INC=95, DEC=63
1373 22:12:46.178323 [RxdqsGatingPostProcess] freq 800
1374 22:12:46.185079 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1375 22:12:46.185196 Pre-setting of DQS Precalculation
1376 22:12:46.191769 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1377 22:12:46.191886 ==
1378 22:12:46.194684 Dram Type= 6, Freq= 0, CH_1, rank 0
1379 22:12:46.198172 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1380 22:12:46.198291 ==
1381 22:12:46.204700 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1382 22:12:46.211323 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1383 22:12:46.219761 [CA 0] Center 36 (6~67) winsize 62
1384 22:12:46.223347 [CA 1] Center 36 (6~67) winsize 62
1385 22:12:46.226448 [CA 2] Center 34 (4~65) winsize 62
1386 22:12:46.229408 [CA 3] Center 34 (4~65) winsize 62
1387 22:12:46.233066 [CA 4] Center 35 (5~65) winsize 61
1388 22:12:46.236050 [CA 5] Center 34 (4~65) winsize 62
1389 22:12:46.236140
1390 22:12:46.239607 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1391 22:12:46.239693
1392 22:12:46.243227 [CATrainingPosCal] consider 1 rank data
1393 22:12:46.246237 u2DelayCellTimex100 = 270/100 ps
1394 22:12:46.249859 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1395 22:12:46.253060 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1396 22:12:46.259988 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1397 22:12:46.263507 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1398 22:12:46.266400 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1399 22:12:46.269862 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1400 22:12:46.269954
1401 22:12:46.273194 CA PerBit enable=1, Macro0, CA PI delay=34
1402 22:12:46.273283
1403 22:12:46.276407 [CBTSetCACLKResult] CA Dly = 34
1404 22:12:46.276495 CS Dly: 5 (0~36)
1405 22:12:46.276562 ==
1406 22:12:46.279582 Dram Type= 6, Freq= 0, CH_1, rank 1
1407 22:12:46.286584 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1408 22:12:46.286688 ==
1409 22:12:46.289767 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1410 22:12:46.296815 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1411 22:12:46.306257 [CA 0] Center 36 (6~67) winsize 62
1412 22:12:46.309914 [CA 1] Center 37 (6~68) winsize 63
1413 22:12:46.313437 [CA 2] Center 35 (5~66) winsize 62
1414 22:12:46.317215 [CA 3] Center 34 (4~65) winsize 62
1415 22:12:46.320624 [CA 4] Center 35 (5~66) winsize 62
1416 22:12:46.324447 [CA 5] Center 34 (4~65) winsize 62
1417 22:12:46.324540
1418 22:12:46.328129 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1419 22:12:46.328217
1420 22:12:46.331787 [CATrainingPosCal] consider 2 rank data
1421 22:12:46.331873 u2DelayCellTimex100 = 270/100 ps
1422 22:12:46.336236 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1423 22:12:46.339334 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1424 22:12:46.342974 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1425 22:12:46.346676 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1426 22:12:46.353088 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1427 22:12:46.356107 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1428 22:12:46.356197
1429 22:12:46.359790 CA PerBit enable=1, Macro0, CA PI delay=34
1430 22:12:46.359875
1431 22:12:46.362857 [CBTSetCACLKResult] CA Dly = 34
1432 22:12:46.362943 CS Dly: 6 (0~38)
1433 22:12:46.363009
1434 22:12:46.366621 ----->DramcWriteLeveling(PI) begin...
1435 22:12:46.366707 ==
1436 22:12:46.370076 Dram Type= 6, Freq= 0, CH_1, rank 0
1437 22:12:46.376190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1438 22:12:46.376291 ==
1439 22:12:46.379516 Write leveling (Byte 0): 27 => 27
1440 22:12:46.379606 Write leveling (Byte 1): 27 => 27
1441 22:12:46.382937 DramcWriteLeveling(PI) end<-----
1442 22:12:46.383026
1443 22:12:46.383094 ==
1444 22:12:46.386017 Dram Type= 6, Freq= 0, CH_1, rank 0
1445 22:12:46.392851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1446 22:12:46.392954 ==
1447 22:12:46.396371 [Gating] SW mode calibration
1448 22:12:46.403104 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1449 22:12:46.406625 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1450 22:12:46.412676 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1451 22:12:46.416387 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1452 22:12:46.419684 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 22:12:46.426148 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 22:12:46.429248 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 22:12:46.432800 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 22:12:46.439730 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 22:12:46.442710 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 22:12:46.446415 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 22:12:46.449363 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 22:12:46.455905 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 22:12:46.459510 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 22:12:46.462611 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 22:12:46.469815 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 22:12:46.472701 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 22:12:46.476193 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 22:12:46.483114 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 22:12:46.486513 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1468 22:12:46.489997 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 22:12:46.496033 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 22:12:46.499432 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 22:12:46.502968 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 22:12:46.509889 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 22:12:46.512794 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 22:12:46.516666 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 22:12:46.522814 0 9 4 | B1->B0 | 2323 2626 | 0 1 | (0 0) (0 0)
1476 22:12:46.526434 0 9 8 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
1477 22:12:46.529481 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1478 22:12:46.536012 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1479 22:12:46.539765 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1480 22:12:46.542799 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1481 22:12:46.546036 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1482 22:12:46.553257 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1483 22:12:46.556206 0 10 4 | B1->B0 | 3131 2e2e | 1 1 | (1 0) (1 1)
1484 22:12:46.559350 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1485 22:12:46.566353 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 22:12:46.569373 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 22:12:46.573105 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 22:12:46.579414 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 22:12:46.582881 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 22:12:46.586264 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 22:12:46.592933 0 11 4 | B1->B0 | 2828 3434 | 1 0 | (0 0) (0 0)
1492 22:12:46.596552 0 11 8 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
1493 22:12:46.599500 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1494 22:12:46.606291 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 22:12:46.609814 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 22:12:46.613191 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 22:12:46.619871 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 22:12:46.622838 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1499 22:12:46.626461 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1500 22:12:46.629682 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 22:12:46.636254 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 22:12:46.639791 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 22:12:46.642878 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 22:12:46.649549 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 22:12:46.653345 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 22:12:46.656164 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 22:12:46.663459 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 22:12:46.666282 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 22:12:46.669832 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 22:12:46.676429 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 22:12:46.679778 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 22:12:46.683316 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 22:12:46.690166 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 22:12:46.693152 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 22:12:46.696646 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1516 22:12:46.699918 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1517 22:12:46.703249 Total UI for P1: 0, mck2ui 16
1518 22:12:46.706861 best dqsien dly found for B0: ( 0, 14, 4)
1519 22:12:46.709766 Total UI for P1: 0, mck2ui 16
1520 22:12:46.713084 best dqsien dly found for B1: ( 0, 14, 4)
1521 22:12:46.716445 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1522 22:12:46.720334 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1523 22:12:46.723408
1524 22:12:46.726836 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1525 22:12:46.730028 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1526 22:12:46.730115 [Gating] SW calibration Done
1527 22:12:46.733622 ==
1528 22:12:46.736872 Dram Type= 6, Freq= 0, CH_1, rank 0
1529 22:12:46.739990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1530 22:12:46.740077 ==
1531 22:12:46.740144 RX Vref Scan: 0
1532 22:12:46.740205
1533 22:12:46.743400 RX Vref 0 -> 0, step: 1
1534 22:12:46.743486
1535 22:12:46.747138 RX Delay -130 -> 252, step: 16
1536 22:12:46.750141 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1537 22:12:46.753826 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1538 22:12:46.756944 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1539 22:12:46.763599 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1540 22:12:46.766688 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1541 22:12:46.770329 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1542 22:12:46.773906 iDelay=222, Bit 6, Center 109 (-2 ~ 221) 224
1543 22:12:46.776964 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1544 22:12:46.783718 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1545 22:12:46.786733 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1546 22:12:46.790158 iDelay=222, Bit 10, Center 93 (-2 ~ 189) 192
1547 22:12:46.793446 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1548 22:12:46.796722 iDelay=222, Bit 12, Center 101 (-2 ~ 205) 208
1549 22:12:46.803693 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1550 22:12:46.806864 iDelay=222, Bit 14, Center 101 (-2 ~ 205) 208
1551 22:12:46.810501 iDelay=222, Bit 15, Center 101 (-2 ~ 205) 208
1552 22:12:46.810593 ==
1553 22:12:46.813817 Dram Type= 6, Freq= 0, CH_1, rank 0
1554 22:12:46.817347 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1555 22:12:46.817443 ==
1556 22:12:46.820239 DQS Delay:
1557 22:12:46.820351 DQS0 = 0, DQS1 = 0
1558 22:12:46.823609 DQM Delay:
1559 22:12:46.823725 DQM0 = 95, DQM1 = 92
1560 22:12:46.823838 DQ Delay:
1561 22:12:46.826690 DQ0 =101, DQ1 =85, DQ2 =77, DQ3 =93
1562 22:12:46.830468 DQ4 =93, DQ5 =109, DQ6 =109, DQ7 =93
1563 22:12:46.833460 DQ8 =77, DQ9 =77, DQ10 =93, DQ11 =85
1564 22:12:46.837253 DQ12 =101, DQ13 =101, DQ14 =101, DQ15 =101
1565 22:12:46.840328
1566 22:12:46.840449
1567 22:12:46.840543 ==
1568 22:12:46.843478 Dram Type= 6, Freq= 0, CH_1, rank 0
1569 22:12:46.847016 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1570 22:12:46.847102 ==
1571 22:12:46.847166
1572 22:12:46.847225
1573 22:12:46.850063 TX Vref Scan disable
1574 22:12:46.850183 == TX Byte 0 ==
1575 22:12:46.856977 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1576 22:12:46.861198 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1577 22:12:46.861303 == TX Byte 1 ==
1578 22:12:46.867110 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1579 22:12:46.870216 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1580 22:12:46.870298 ==
1581 22:12:46.873888 Dram Type= 6, Freq= 0, CH_1, rank 0
1582 22:12:46.876765 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1583 22:12:46.876911 ==
1584 22:12:46.890823 TX Vref=22, minBit 0, minWin=26, winSum=435
1585 22:12:46.894251 TX Vref=24, minBit 1, minWin=26, winSum=435
1586 22:12:46.897249 TX Vref=26, minBit 1, minWin=27, winSum=446
1587 22:12:46.900772 TX Vref=28, minBit 1, minWin=27, winSum=445
1588 22:12:46.904001 TX Vref=30, minBit 2, minWin=26, winSum=445
1589 22:12:46.907781 TX Vref=32, minBit 0, minWin=27, winSum=443
1590 22:12:46.914077 [TxChooseVref] Worse bit 1, Min win 27, Win sum 446, Final Vref 26
1591 22:12:46.914195
1592 22:12:46.917463 Final TX Range 1 Vref 26
1593 22:12:46.917594
1594 22:12:46.917659 ==
1595 22:12:46.920621 Dram Type= 6, Freq= 0, CH_1, rank 0
1596 22:12:46.924125 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1597 22:12:46.924211 ==
1598 22:12:46.924276
1599 22:12:46.924334
1600 22:12:46.927526 TX Vref Scan disable
1601 22:12:46.930622 == TX Byte 0 ==
1602 22:12:46.933942 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1603 22:12:46.937446 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1604 22:12:46.940661 == TX Byte 1 ==
1605 22:12:46.944241 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1606 22:12:46.947242 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1607 22:12:46.947329
1608 22:12:46.950964 [DATLAT]
1609 22:12:46.951051 Freq=800, CH1 RK0
1610 22:12:46.951116
1611 22:12:46.953866 DATLAT Default: 0xa
1612 22:12:46.953949 0, 0xFFFF, sum = 0
1613 22:12:46.957366 1, 0xFFFF, sum = 0
1614 22:12:46.957452 2, 0xFFFF, sum = 0
1615 22:12:46.961030 3, 0xFFFF, sum = 0
1616 22:12:46.961115 4, 0xFFFF, sum = 0
1617 22:12:46.964012 5, 0xFFFF, sum = 0
1618 22:12:46.964098 6, 0xFFFF, sum = 0
1619 22:12:46.967223 7, 0xFFFF, sum = 0
1620 22:12:46.967308 8, 0xFFFF, sum = 0
1621 22:12:46.970768 9, 0x0, sum = 1
1622 22:12:46.970855 10, 0x0, sum = 2
1623 22:12:46.973991 11, 0x0, sum = 3
1624 22:12:46.974077 12, 0x0, sum = 4
1625 22:12:46.977787 best_step = 10
1626 22:12:46.977873
1627 22:12:46.977938 ==
1628 22:12:46.980738 Dram Type= 6, Freq= 0, CH_1, rank 0
1629 22:12:46.984534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1630 22:12:46.984622 ==
1631 22:12:46.984687 RX Vref Scan: 1
1632 22:12:46.987290
1633 22:12:46.987375 Set Vref Range= 32 -> 127
1634 22:12:46.987440
1635 22:12:46.990847 RX Vref 32 -> 127, step: 1
1636 22:12:46.990941
1637 22:12:46.994428 RX Delay -79 -> 252, step: 8
1638 22:12:46.994513
1639 22:12:46.997465 Set Vref, RX VrefLevel [Byte0]: 32
1640 22:12:47.000766 [Byte1]: 32
1641 22:12:47.000853
1642 22:12:47.004271 Set Vref, RX VrefLevel [Byte0]: 33
1643 22:12:47.007679 [Byte1]: 33
1644 22:12:47.007770
1645 22:12:47.010948 Set Vref, RX VrefLevel [Byte0]: 34
1646 22:12:47.014790 [Byte1]: 34
1647 22:12:47.017781
1648 22:12:47.017875 Set Vref, RX VrefLevel [Byte0]: 35
1649 22:12:47.021434 [Byte1]: 35
1650 22:12:47.025283
1651 22:12:47.025373 Set Vref, RX VrefLevel [Byte0]: 36
1652 22:12:47.028769 [Byte1]: 36
1653 22:12:47.032935
1654 22:12:47.033034 Set Vref, RX VrefLevel [Byte0]: 37
1655 22:12:47.036327 [Byte1]: 37
1656 22:12:47.040862
1657 22:12:47.040963 Set Vref, RX VrefLevel [Byte0]: 38
1658 22:12:47.043879 [Byte1]: 38
1659 22:12:47.048041
1660 22:12:47.048130 Set Vref, RX VrefLevel [Byte0]: 39
1661 22:12:47.051848 [Byte1]: 39
1662 22:12:47.055534
1663 22:12:47.055621 Set Vref, RX VrefLevel [Byte0]: 40
1664 22:12:47.059097 [Byte1]: 40
1665 22:12:47.063135
1666 22:12:47.063226 Set Vref, RX VrefLevel [Byte0]: 41
1667 22:12:47.066206 [Byte1]: 41
1668 22:12:47.070537
1669 22:12:47.070626 Set Vref, RX VrefLevel [Byte0]: 42
1670 22:12:47.074106 [Byte1]: 42
1671 22:12:47.078534
1672 22:12:47.078625 Set Vref, RX VrefLevel [Byte0]: 43
1673 22:12:47.081460 [Byte1]: 43
1674 22:12:47.085743
1675 22:12:47.085833 Set Vref, RX VrefLevel [Byte0]: 44
1676 22:12:47.089549 [Byte1]: 44
1677 22:12:47.093375
1678 22:12:47.093467 Set Vref, RX VrefLevel [Byte0]: 45
1679 22:12:47.096867 [Byte1]: 45
1680 22:12:47.101142
1681 22:12:47.101232 Set Vref, RX VrefLevel [Byte0]: 46
1682 22:12:47.104194 [Byte1]: 46
1683 22:12:47.108854
1684 22:12:47.108948 Set Vref, RX VrefLevel [Byte0]: 47
1685 22:12:47.111791 [Byte1]: 47
1686 22:12:47.116119
1687 22:12:47.116216 Set Vref, RX VrefLevel [Byte0]: 48
1688 22:12:47.119492 [Byte1]: 48
1689 22:12:47.123750
1690 22:12:47.123842 Set Vref, RX VrefLevel [Byte0]: 49
1691 22:12:47.127084 [Byte1]: 49
1692 22:12:47.131112
1693 22:12:47.131202 Set Vref, RX VrefLevel [Byte0]: 50
1694 22:12:47.134572 [Byte1]: 50
1695 22:12:47.138709
1696 22:12:47.138800 Set Vref, RX VrefLevel [Byte0]: 51
1697 22:12:47.142076 [Byte1]: 51
1698 22:12:47.146138
1699 22:12:47.146229 Set Vref, RX VrefLevel [Byte0]: 52
1700 22:12:47.149789 [Byte1]: 52
1701 22:12:47.154101
1702 22:12:47.154193 Set Vref, RX VrefLevel [Byte0]: 53
1703 22:12:47.157077 [Byte1]: 53
1704 22:12:47.161290
1705 22:12:47.161379 Set Vref, RX VrefLevel [Byte0]: 54
1706 22:12:47.164488 [Byte1]: 54
1707 22:12:47.168947
1708 22:12:47.169056 Set Vref, RX VrefLevel [Byte0]: 55
1709 22:12:47.171926 [Byte1]: 55
1710 22:12:47.176150
1711 22:12:47.176240 Set Vref, RX VrefLevel [Byte0]: 56
1712 22:12:47.179731 [Byte1]: 56
1713 22:12:47.183985
1714 22:12:47.184076 Set Vref, RX VrefLevel [Byte0]: 57
1715 22:12:47.187316 [Byte1]: 57
1716 22:12:47.191629
1717 22:12:47.191725 Set Vref, RX VrefLevel [Byte0]: 58
1718 22:12:47.194612 [Byte1]: 58
1719 22:12:47.199085
1720 22:12:47.199177 Set Vref, RX VrefLevel [Byte0]: 59
1721 22:12:47.202390 [Byte1]: 59
1722 22:12:47.206627
1723 22:12:47.206717 Set Vref, RX VrefLevel [Byte0]: 60
1724 22:12:47.210325 [Byte1]: 60
1725 22:12:47.214359
1726 22:12:47.214479 Set Vref, RX VrefLevel [Byte0]: 61
1727 22:12:47.217251 [Byte1]: 61
1728 22:12:47.221810
1729 22:12:47.221901 Set Vref, RX VrefLevel [Byte0]: 62
1730 22:12:47.225222 [Byte1]: 62
1731 22:12:47.229533
1732 22:12:47.229638 Set Vref, RX VrefLevel [Byte0]: 63
1733 22:12:47.232666 [Byte1]: 63
1734 22:12:47.237037
1735 22:12:47.237125 Set Vref, RX VrefLevel [Byte0]: 64
1736 22:12:47.240068 [Byte1]: 64
1737 22:12:47.244612
1738 22:12:47.244727 Set Vref, RX VrefLevel [Byte0]: 65
1739 22:12:47.248019 [Byte1]: 65
1740 22:12:47.252047
1741 22:12:47.252136 Set Vref, RX VrefLevel [Byte0]: 66
1742 22:12:47.255057 [Byte1]: 66
1743 22:12:47.259300
1744 22:12:47.259388 Set Vref, RX VrefLevel [Byte0]: 67
1745 22:12:47.262934 [Byte1]: 67
1746 22:12:47.267188
1747 22:12:47.267275 Set Vref, RX VrefLevel [Byte0]: 68
1748 22:12:47.270460 [Byte1]: 68
1749 22:12:47.274374
1750 22:12:47.274459 Set Vref, RX VrefLevel [Byte0]: 69
1751 22:12:47.278070 [Byte1]: 69
1752 22:12:47.282169
1753 22:12:47.282259 Set Vref, RX VrefLevel [Byte0]: 70
1754 22:12:47.285697 [Byte1]: 70
1755 22:12:47.289408
1756 22:12:47.289496 Set Vref, RX VrefLevel [Byte0]: 71
1757 22:12:47.293203 [Byte1]: 71
1758 22:12:47.297497
1759 22:12:47.297597 Set Vref, RX VrefLevel [Byte0]: 72
1760 22:12:47.300590 [Byte1]: 72
1761 22:12:47.304793
1762 22:12:47.304882 Final RX Vref Byte 0 = 59 to rank0
1763 22:12:47.308157 Final RX Vref Byte 1 = 55 to rank0
1764 22:12:47.311286 Final RX Vref Byte 0 = 59 to rank1
1765 22:12:47.314999 Final RX Vref Byte 1 = 55 to rank1==
1766 22:12:47.317987 Dram Type= 6, Freq= 0, CH_1, rank 0
1767 22:12:47.324417 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1768 22:12:47.324525 ==
1769 22:12:47.324595 DQS Delay:
1770 22:12:47.324657 DQS0 = 0, DQS1 = 0
1771 22:12:47.328341 DQM Delay:
1772 22:12:47.328425 DQM0 = 95, DQM1 = 89
1773 22:12:47.331472 DQ Delay:
1774 22:12:47.334608 DQ0 =100, DQ1 =88, DQ2 =84, DQ3 =88
1775 22:12:47.338106 DQ4 =96, DQ5 =108, DQ6 =104, DQ7 =92
1776 22:12:47.341700 DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =84
1777 22:12:47.345093 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
1778 22:12:47.345183
1779 22:12:47.345247
1780 22:12:47.351385 [DQSOSCAuto] RK0, (LSB)MR18= 0x314e, (MSB)MR19= 0x606, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
1781 22:12:47.355034 CH1 RK0: MR19=606, MR18=314E
1782 22:12:47.361201 CH1_RK0: MR19=0x606, MR18=0x314E, DQSOSC=390, MR23=63, INC=97, DEC=64
1783 22:12:47.361308
1784 22:12:47.364458 ----->DramcWriteLeveling(PI) begin...
1785 22:12:47.364545 ==
1786 22:12:47.368137 Dram Type= 6, Freq= 0, CH_1, rank 1
1787 22:12:47.371053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1788 22:12:47.371141 ==
1789 22:12:47.374776 Write leveling (Byte 0): 26 => 26
1790 22:12:47.377741 Write leveling (Byte 1): 28 => 28
1791 22:12:47.381243 DramcWriteLeveling(PI) end<-----
1792 22:12:47.381330
1793 22:12:47.381396 ==
1794 22:12:47.384785 Dram Type= 6, Freq= 0, CH_1, rank 1
1795 22:12:47.388225 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1796 22:12:47.388316 ==
1797 22:12:47.391423 [Gating] SW mode calibration
1798 22:12:47.398182 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1799 22:12:47.405033 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1800 22:12:47.408093 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1801 22:12:47.411613 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1802 22:12:47.418228 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1803 22:12:47.421239 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1804 22:12:47.424612 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1805 22:12:47.431597 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1806 22:12:47.434853 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1807 22:12:47.438479 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1808 22:12:47.444790 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1809 22:12:47.448584 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1810 22:12:47.451953 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 22:12:47.458296 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 22:12:47.461701 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 22:12:47.465223 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 22:12:47.467972 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 22:12:47.475282 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 22:12:47.478367 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1817 22:12:47.481438 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 1)
1818 22:12:47.488493 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 22:12:47.491849 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 22:12:47.494868 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 22:12:47.501617 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 22:12:47.504876 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 22:12:47.508534 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 22:12:47.515202 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 22:12:47.518753 0 9 4 | B1->B0 | 2b2b 2323 | 1 1 | (0 0) (1 1)
1826 22:12:47.521554 0 9 8 | B1->B0 | 3434 3131 | 0 1 | (0 0) (1 1)
1827 22:12:47.528265 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1828 22:12:47.532185 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1829 22:12:47.534966 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1830 22:12:47.541791 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1831 22:12:47.545235 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1832 22:12:47.548190 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1833 22:12:47.551688 0 10 4 | B1->B0 | 3030 3131 | 0 0 | (1 1) (1 1)
1834 22:12:47.558148 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 0)
1835 22:12:47.561540 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 22:12:47.565119 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 22:12:47.572105 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 22:12:47.575048 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 22:12:47.578685 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 22:12:47.584758 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 22:12:47.588480 0 11 4 | B1->B0 | 3a3a 3131 | 0 0 | (0 0) (0 0)
1842 22:12:47.591674 0 11 8 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
1843 22:12:47.598558 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1844 22:12:47.601734 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1845 22:12:47.605321 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1846 22:12:47.612233 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1847 22:12:47.615215 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1848 22:12:47.618250 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1849 22:12:47.625036 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1850 22:12:47.628421 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1851 22:12:47.631380 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1852 22:12:47.638528 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1853 22:12:47.642019 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1854 22:12:47.645058 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1855 22:12:47.648406 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1856 22:12:47.655389 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1857 22:12:47.658048 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1858 22:12:47.661646 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 22:12:47.668342 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1860 22:12:47.671814 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 22:12:47.674748 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 22:12:47.681620 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 22:12:47.684878 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 22:12:47.688469 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1865 22:12:47.695186 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1866 22:12:47.698268 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1867 22:12:47.701910 Total UI for P1: 0, mck2ui 16
1868 22:12:47.705621 best dqsien dly found for B0: ( 0, 14, 4)
1869 22:12:47.708209 Total UI for P1: 0, mck2ui 16
1870 22:12:47.711707 best dqsien dly found for B1: ( 0, 14, 2)
1871 22:12:47.715402 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1872 22:12:47.718673 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1873 22:12:47.718763
1874 22:12:47.721673 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1875 22:12:47.725330 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1876 22:12:47.728355 [Gating] SW calibration Done
1877 22:12:47.728441 ==
1878 22:12:47.731988 Dram Type= 6, Freq= 0, CH_1, rank 1
1879 22:12:47.735557 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1880 22:12:47.735647 ==
1881 22:12:47.738622 RX Vref Scan: 0
1882 22:12:47.738707
1883 22:12:47.741752 RX Vref 0 -> 0, step: 1
1884 22:12:47.741836
1885 22:12:47.741902 RX Delay -130 -> 252, step: 16
1886 22:12:47.748475 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1887 22:12:47.751985 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1888 22:12:47.755305 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1889 22:12:47.758101 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1890 22:12:47.761713 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1891 22:12:47.768416 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1892 22:12:47.771987 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1893 22:12:47.774990 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1894 22:12:47.778256 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1895 22:12:47.781710 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1896 22:12:47.788429 iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224
1897 22:12:47.791521 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1898 22:12:47.795299 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1899 22:12:47.798336 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1900 22:12:47.801981 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1901 22:12:47.808768 iDelay=222, Bit 15, Center 101 (-2 ~ 205) 208
1902 22:12:47.808874 ==
1903 22:12:47.811626 Dram Type= 6, Freq= 0, CH_1, rank 1
1904 22:12:47.815162 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1905 22:12:47.815257 ==
1906 22:12:47.815325 DQS Delay:
1907 22:12:47.818753 DQS0 = 0, DQS1 = 0
1908 22:12:47.818841 DQM Delay:
1909 22:12:47.821815 DQM0 = 92, DQM1 = 89
1910 22:12:47.821901 DQ Delay:
1911 22:12:47.825391 DQ0 =101, DQ1 =85, DQ2 =77, DQ3 =85
1912 22:12:47.828551 DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93
1913 22:12:47.832245 DQ8 =77, DQ9 =77, DQ10 =93, DQ11 =77
1914 22:12:47.835137 DQ12 =93, DQ13 =101, DQ14 =93, DQ15 =101
1915 22:12:47.835225
1916 22:12:47.835291
1917 22:12:47.835352 ==
1918 22:12:47.839151 Dram Type= 6, Freq= 0, CH_1, rank 1
1919 22:12:47.841786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1920 22:12:47.841894 ==
1921 22:12:47.845367
1922 22:12:47.845472
1923 22:12:47.845567 TX Vref Scan disable
1924 22:12:47.848658 == TX Byte 0 ==
1925 22:12:47.852089 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1926 22:12:47.855566 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1927 22:12:47.858554 == TX Byte 1 ==
1928 22:12:47.861730 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1929 22:12:47.865369 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1930 22:12:47.865484 ==
1931 22:12:47.868828 Dram Type= 6, Freq= 0, CH_1, rank 1
1932 22:12:47.875685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1933 22:12:47.875791 ==
1934 22:12:47.887016 TX Vref=22, minBit 1, minWin=26, winSum=442
1935 22:12:47.890397 TX Vref=24, minBit 0, minWin=27, winSum=443
1936 22:12:47.893845 TX Vref=26, minBit 0, minWin=27, winSum=449
1937 22:12:47.897400 TX Vref=28, minBit 2, minWin=27, winSum=448
1938 22:12:47.900525 TX Vref=30, minBit 2, minWin=27, winSum=450
1939 22:12:47.903632 TX Vref=32, minBit 1, minWin=27, winSum=446
1940 22:12:47.910372 [TxChooseVref] Worse bit 2, Min win 27, Win sum 450, Final Vref 30
1941 22:12:47.910503
1942 22:12:47.913819 Final TX Range 1 Vref 30
1943 22:12:47.913908
1944 22:12:47.913975 ==
1945 22:12:47.916951 Dram Type= 6, Freq= 0, CH_1, rank 1
1946 22:12:47.920660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1947 22:12:47.920752 ==
1948 22:12:47.920819
1949 22:12:47.924087
1950 22:12:47.924177 TX Vref Scan disable
1951 22:12:47.927136 == TX Byte 0 ==
1952 22:12:47.930412 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1953 22:12:47.934207 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1954 22:12:47.937064 == TX Byte 1 ==
1955 22:12:47.940536 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1956 22:12:47.943517 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1957 22:12:47.946759
1958 22:12:47.946874 [DATLAT]
1959 22:12:47.946969 Freq=800, CH1 RK1
1960 22:12:47.947059
1961 22:12:47.950091 DATLAT Default: 0xa
1962 22:12:47.950175 0, 0xFFFF, sum = 0
1963 22:12:47.953413 1, 0xFFFF, sum = 0
1964 22:12:47.953500 2, 0xFFFF, sum = 0
1965 22:12:47.957343 3, 0xFFFF, sum = 0
1966 22:12:47.957431 4, 0xFFFF, sum = 0
1967 22:12:47.960248 5, 0xFFFF, sum = 0
1968 22:12:47.963895 6, 0xFFFF, sum = 0
1969 22:12:47.963987 7, 0xFFFF, sum = 0
1970 22:12:47.966863 8, 0xFFFF, sum = 0
1971 22:12:47.966949 9, 0x0, sum = 1
1972 22:12:47.967018 10, 0x0, sum = 2
1973 22:12:47.970376 11, 0x0, sum = 3
1974 22:12:47.970468 12, 0x0, sum = 4
1975 22:12:47.973675 best_step = 10
1976 22:12:47.973766
1977 22:12:47.973835 ==
1978 22:12:47.977045 Dram Type= 6, Freq= 0, CH_1, rank 1
1979 22:12:47.980431 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1980 22:12:47.980520 ==
1981 22:12:47.983437 RX Vref Scan: 0
1982 22:12:47.983524
1983 22:12:47.983590 RX Vref 0 -> 0, step: 1
1984 22:12:47.983651
1985 22:12:47.986868 RX Delay -79 -> 252, step: 8
1986 22:12:47.994076 iDelay=209, Bit 0, Center 104 (9 ~ 200) 192
1987 22:12:47.997451 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
1988 22:12:48.000911 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
1989 22:12:48.003733 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
1990 22:12:48.007279 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
1991 22:12:48.010411 iDelay=209, Bit 5, Center 108 (9 ~ 208) 200
1992 22:12:48.017183 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
1993 22:12:48.020759 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
1994 22:12:48.023930 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
1995 22:12:48.027484 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
1996 22:12:48.030934 iDelay=209, Bit 10, Center 92 (-15 ~ 200) 216
1997 22:12:48.037176 iDelay=209, Bit 11, Center 84 (-23 ~ 192) 216
1998 22:12:48.040462 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
1999 22:12:48.044018 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
2000 22:12:48.047109 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
2001 22:12:48.050589 iDelay=209, Bit 15, Center 96 (-7 ~ 200) 208
2002 22:12:48.050679 ==
2003 22:12:48.053813 Dram Type= 6, Freq= 0, CH_1, rank 1
2004 22:12:48.060410 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2005 22:12:48.060512 ==
2006 22:12:48.060580 DQS Delay:
2007 22:12:48.063947 DQS0 = 0, DQS1 = 0
2008 22:12:48.064033 DQM Delay:
2009 22:12:48.064100 DQM0 = 97, DQM1 = 90
2010 22:12:48.067356 DQ Delay:
2011 22:12:48.070402 DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92
2012 22:12:48.074059 DQ4 =92, DQ5 =108, DQ6 =108, DQ7 =96
2013 22:12:48.077664 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =84
2014 22:12:48.080983 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =96
2015 22:12:48.081099
2016 22:12:48.081199
2017 22:12:48.087297 [DQSOSCAuto] RK1, (LSB)MR18= 0x450f, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 392 ps
2018 22:12:48.090538 CH1 RK1: MR19=606, MR18=450F
2019 22:12:48.097465 CH1_RK1: MR19=0x606, MR18=0x450F, DQSOSC=392, MR23=63, INC=96, DEC=64
2020 22:12:48.100907 [RxdqsGatingPostProcess] freq 800
2021 22:12:48.103784 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2022 22:12:48.107724 Pre-setting of DQS Precalculation
2023 22:12:48.114038 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2024 22:12:48.120471 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2025 22:12:48.127318 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2026 22:12:48.127429
2027 22:12:48.127494
2028 22:12:48.130768 [Calibration Summary] 1600 Mbps
2029 22:12:48.130854 CH 0, Rank 0
2030 22:12:48.134194 SW Impedance : PASS
2031 22:12:48.137179 DUTY Scan : NO K
2032 22:12:48.137292 ZQ Calibration : PASS
2033 22:12:48.141282 Jitter Meter : NO K
2034 22:12:48.144214 CBT Training : PASS
2035 22:12:48.144301 Write leveling : PASS
2036 22:12:48.147227 RX DQS gating : PASS
2037 22:12:48.150329 RX DQ/DQS(RDDQC) : PASS
2038 22:12:48.150415 TX DQ/DQS : PASS
2039 22:12:48.153468 RX DATLAT : PASS
2040 22:12:48.157443 RX DQ/DQS(Engine): PASS
2041 22:12:48.157584 TX OE : NO K
2042 22:12:48.160835 All Pass.
2043 22:12:48.160922
2044 22:12:48.160987 CH 0, Rank 1
2045 22:12:48.163678 SW Impedance : PASS
2046 22:12:48.163763 DUTY Scan : NO K
2047 22:12:48.167454 ZQ Calibration : PASS
2048 22:12:48.170446 Jitter Meter : NO K
2049 22:12:48.170532 CBT Training : PASS
2050 22:12:48.173909 Write leveling : PASS
2051 22:12:48.173996 RX DQS gating : PASS
2052 22:12:48.177426 RX DQ/DQS(RDDQC) : PASS
2053 22:12:48.180442 TX DQ/DQS : PASS
2054 22:12:48.180529 RX DATLAT : PASS
2055 22:12:48.184075 RX DQ/DQS(Engine): PASS
2056 22:12:48.187418 TX OE : NO K
2057 22:12:48.187509 All Pass.
2058 22:12:48.187575
2059 22:12:48.187637 CH 1, Rank 0
2060 22:12:48.190759 SW Impedance : PASS
2061 22:12:48.194055 DUTY Scan : NO K
2062 22:12:48.194146 ZQ Calibration : PASS
2063 22:12:48.197413 Jitter Meter : NO K
2064 22:12:48.200828 CBT Training : PASS
2065 22:12:48.200916 Write leveling : PASS
2066 22:12:48.203962 RX DQS gating : PASS
2067 22:12:48.204047 RX DQ/DQS(RDDQC) : PASS
2068 22:12:48.207576 TX DQ/DQS : PASS
2069 22:12:48.210534 RX DATLAT : PASS
2070 22:12:48.210621 RX DQ/DQS(Engine): PASS
2071 22:12:48.214264 TX OE : NO K
2072 22:12:48.214379 All Pass.
2073 22:12:48.214476
2074 22:12:48.217604 CH 1, Rank 1
2075 22:12:48.217693 SW Impedance : PASS
2076 22:12:48.221084 DUTY Scan : NO K
2077 22:12:48.224269 ZQ Calibration : PASS
2078 22:12:48.224355 Jitter Meter : NO K
2079 22:12:48.227786 CBT Training : PASS
2080 22:12:48.230723 Write leveling : PASS
2081 22:12:48.230838 RX DQS gating : PASS
2082 22:12:48.234470 RX DQ/DQS(RDDQC) : PASS
2083 22:12:48.234583 TX DQ/DQS : PASS
2084 22:12:48.238176 RX DATLAT : PASS
2085 22:12:48.241037 RX DQ/DQS(Engine): PASS
2086 22:12:48.241123 TX OE : NO K
2087 22:12:48.244724 All Pass.
2088 22:12:48.244809
2089 22:12:48.244875 DramC Write-DBI off
2090 22:12:48.247668 PER_BANK_REFRESH: Hybrid Mode
2091 22:12:48.251335 TX_TRACKING: ON
2092 22:12:48.254383 [GetDramInforAfterCalByMRR] Vendor 6.
2093 22:12:48.257481 [GetDramInforAfterCalByMRR] Revision 606.
2094 22:12:48.261037 [GetDramInforAfterCalByMRR] Revision 2 0.
2095 22:12:48.261125 MR0 0x3b3b
2096 22:12:48.261191 MR8 0x5151
2097 22:12:48.267519 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2098 22:12:48.267616
2099 22:12:48.267683 MR0 0x3b3b
2100 22:12:48.267744 MR8 0x5151
2101 22:12:48.271158 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2102 22:12:48.271244
2103 22:12:48.280736 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2104 22:12:48.284292 [FAST_K] Save calibration result to emmc
2105 22:12:48.287854 [FAST_K] Save calibration result to emmc
2106 22:12:48.290940 dram_init: config_dvfs: 1
2107 22:12:48.294106 dramc_set_vcore_voltage set vcore to 662500
2108 22:12:48.297630 Read voltage for 1200, 2
2109 22:12:48.297721 Vio18 = 0
2110 22:12:48.297824 Vcore = 662500
2111 22:12:48.300843 Vdram = 0
2112 22:12:48.300929 Vddq = 0
2113 22:12:48.300995 Vmddr = 0
2114 22:12:48.307704 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2115 22:12:48.310864 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2116 22:12:48.314067 MEM_TYPE=3, freq_sel=15
2117 22:12:48.317732 sv_algorithm_assistance_LP4_1600
2118 22:12:48.320980 ============ PULL DRAM RESETB DOWN ============
2119 22:12:48.324331 ========== PULL DRAM RESETB DOWN end =========
2120 22:12:48.331016 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2121 22:12:48.334693 ===================================
2122 22:12:48.334792 LPDDR4 DRAM CONFIGURATION
2123 22:12:48.337654 ===================================
2124 22:12:48.341264 EX_ROW_EN[0] = 0x0
2125 22:12:48.344361 EX_ROW_EN[1] = 0x0
2126 22:12:48.344451 LP4Y_EN = 0x0
2127 22:12:48.347904 WORK_FSP = 0x0
2128 22:12:48.347992 WL = 0x4
2129 22:12:48.351163 RL = 0x4
2130 22:12:48.351250 BL = 0x2
2131 22:12:48.354880 RPST = 0x0
2132 22:12:48.354968 RD_PRE = 0x0
2133 22:12:48.358151 WR_PRE = 0x1
2134 22:12:48.358242 WR_PST = 0x0
2135 22:12:48.361280 DBI_WR = 0x0
2136 22:12:48.361365 DBI_RD = 0x0
2137 22:12:48.364683 OTF = 0x1
2138 22:12:48.367776 ===================================
2139 22:12:48.371240 ===================================
2140 22:12:48.371331 ANA top config
2141 22:12:48.374625 ===================================
2142 22:12:48.377455 DLL_ASYNC_EN = 0
2143 22:12:48.381294 ALL_SLAVE_EN = 0
2144 22:12:48.384898 NEW_RANK_MODE = 1
2145 22:12:48.384992 DLL_IDLE_MODE = 1
2146 22:12:48.387883 LP45_APHY_COMB_EN = 1
2147 22:12:48.391623 TX_ODT_DIS = 1
2148 22:12:48.394573 NEW_8X_MODE = 1
2149 22:12:48.397807 ===================================
2150 22:12:48.401313 ===================================
2151 22:12:48.404498 data_rate = 2400
2152 22:12:48.404590 CKR = 1
2153 22:12:48.407530 DQ_P2S_RATIO = 8
2154 22:12:48.411093 ===================================
2155 22:12:48.414142 CA_P2S_RATIO = 8
2156 22:12:48.417646 DQ_CA_OPEN = 0
2157 22:12:48.420985 DQ_SEMI_OPEN = 0
2158 22:12:48.421075 CA_SEMI_OPEN = 0
2159 22:12:48.424354 CA_FULL_RATE = 0
2160 22:12:48.427966 DQ_CKDIV4_EN = 0
2161 22:12:48.431320 CA_CKDIV4_EN = 0
2162 22:12:48.434542 CA_PREDIV_EN = 0
2163 22:12:48.437867 PH8_DLY = 17
2164 22:12:48.437956 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2165 22:12:48.441214 DQ_AAMCK_DIV = 4
2166 22:12:48.444937 CA_AAMCK_DIV = 4
2167 22:12:48.447994 CA_ADMCK_DIV = 4
2168 22:12:48.451649 DQ_TRACK_CA_EN = 0
2169 22:12:48.454850 CA_PICK = 1200
2170 22:12:48.454939 CA_MCKIO = 1200
2171 22:12:48.457925 MCKIO_SEMI = 0
2172 22:12:48.461486 PLL_FREQ = 2366
2173 22:12:48.464700 DQ_UI_PI_RATIO = 32
2174 22:12:48.468141 CA_UI_PI_RATIO = 0
2175 22:12:48.472070 ===================================
2176 22:12:48.474908 ===================================
2177 22:12:48.478507 memory_type:LPDDR4
2178 22:12:48.478597 GP_NUM : 10
2179 22:12:48.481395 SRAM_EN : 1
2180 22:12:48.481507 MD32_EN : 0
2181 22:12:48.484937 ===================================
2182 22:12:48.488061 [ANA_INIT] >>>>>>>>>>>>>>
2183 22:12:48.491565 <<<<<< [CONFIGURE PHASE]: ANA_TX
2184 22:12:48.495198 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2185 22:12:48.498206 ===================================
2186 22:12:48.501929 data_rate = 2400,PCW = 0X5b00
2187 22:12:48.505042 ===================================
2188 22:12:48.508141 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2189 22:12:48.511691 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2190 22:12:48.518226 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2191 22:12:48.521410 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2192 22:12:48.524858 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2193 22:12:48.531609 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2194 22:12:48.531720 [ANA_INIT] flow start
2195 22:12:48.535094 [ANA_INIT] PLL >>>>>>>>
2196 22:12:48.535181 [ANA_INIT] PLL <<<<<<<<
2197 22:12:48.538522 [ANA_INIT] MIDPI >>>>>>>>
2198 22:12:48.541714 [ANA_INIT] MIDPI <<<<<<<<
2199 22:12:48.544924 [ANA_INIT] DLL >>>>>>>>
2200 22:12:48.545014 [ANA_INIT] DLL <<<<<<<<
2201 22:12:48.548348 [ANA_INIT] flow end
2202 22:12:48.551843 ============ LP4 DIFF to SE enter ============
2203 22:12:48.554880 ============ LP4 DIFF to SE exit ============
2204 22:12:48.558360 [ANA_INIT] <<<<<<<<<<<<<
2205 22:12:48.561794 [Flow] Enable top DCM control >>>>>
2206 22:12:48.564803 [Flow] Enable top DCM control <<<<<
2207 22:12:48.568386 Enable DLL master slave shuffle
2208 22:12:48.574694 ==============================================================
2209 22:12:48.574806 Gating Mode config
2210 22:12:48.581881 ==============================================================
2211 22:12:48.581983 Config description:
2212 22:12:48.591435 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2213 22:12:48.598577 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2214 22:12:48.605331 SELPH_MODE 0: By rank 1: By Phase
2215 22:12:48.608416 ==============================================================
2216 22:12:48.612145 GAT_TRACK_EN = 1
2217 22:12:48.615062 RX_GATING_MODE = 2
2218 22:12:48.618919 RX_GATING_TRACK_MODE = 2
2219 22:12:48.621820 SELPH_MODE = 1
2220 22:12:48.625253 PICG_EARLY_EN = 1
2221 22:12:48.628687 VALID_LAT_VALUE = 1
2222 22:12:48.631969 ==============================================================
2223 22:12:48.635490 Enter into Gating configuration >>>>
2224 22:12:48.639151 Exit from Gating configuration <<<<
2225 22:12:48.642498 Enter into DVFS_PRE_config >>>>>
2226 22:12:48.652707 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2227 22:12:48.655374 Exit from DVFS_PRE_config <<<<<
2228 22:12:48.659010 Enter into PICG configuration >>>>
2229 22:12:48.661887 Exit from PICG configuration <<<<
2230 22:12:48.665451 [RX_INPUT] configuration >>>>>
2231 22:12:48.668624 [RX_INPUT] configuration <<<<<
2232 22:12:48.675384 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2233 22:12:48.678616 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2234 22:12:48.685891 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2235 22:12:48.692446 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2236 22:12:48.698715 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2237 22:12:48.705329 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2238 22:12:48.709014 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2239 22:12:48.712274 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2240 22:12:48.715307 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2241 22:12:48.718883 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2242 22:12:48.725741 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2243 22:12:48.728734 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2244 22:12:48.732172 ===================================
2245 22:12:48.735534 LPDDR4 DRAM CONFIGURATION
2246 22:12:48.739176 ===================================
2247 22:12:48.739270 EX_ROW_EN[0] = 0x0
2248 22:12:48.742325 EX_ROW_EN[1] = 0x0
2249 22:12:48.742413 LP4Y_EN = 0x0
2250 22:12:48.745715 WORK_FSP = 0x0
2251 22:12:48.745801 WL = 0x4
2252 22:12:48.748728 RL = 0x4
2253 22:12:48.748813 BL = 0x2
2254 22:12:48.752523 RPST = 0x0
2255 22:12:48.752610 RD_PRE = 0x0
2256 22:12:48.755566 WR_PRE = 0x1
2257 22:12:48.755673 WR_PST = 0x0
2258 22:12:48.759413 DBI_WR = 0x0
2259 22:12:48.759502 DBI_RD = 0x0
2260 22:12:48.762706 OTF = 0x1
2261 22:12:48.765460 ===================================
2262 22:12:48.768959 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2263 22:12:48.772666 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2264 22:12:48.778986 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2265 22:12:48.782455 ===================================
2266 22:12:48.782552 LPDDR4 DRAM CONFIGURATION
2267 22:12:48.785460 ===================================
2268 22:12:48.789372 EX_ROW_EN[0] = 0x10
2269 22:12:48.792242 EX_ROW_EN[1] = 0x0
2270 22:12:48.792332 LP4Y_EN = 0x0
2271 22:12:48.795598 WORK_FSP = 0x0
2272 22:12:48.795683 WL = 0x4
2273 22:12:48.799081 RL = 0x4
2274 22:12:48.799191 BL = 0x2
2275 22:12:48.802457 RPST = 0x0
2276 22:12:48.802542 RD_PRE = 0x0
2277 22:12:48.805610 WR_PRE = 0x1
2278 22:12:48.805722 WR_PST = 0x0
2279 22:12:48.809227 DBI_WR = 0x0
2280 22:12:48.809330 DBI_RD = 0x0
2281 22:12:48.812404 OTF = 0x1
2282 22:12:48.816036 ===================================
2283 22:12:48.822303 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2284 22:12:48.822410 ==
2285 22:12:48.825854 Dram Type= 6, Freq= 0, CH_0, rank 0
2286 22:12:48.829008 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2287 22:12:48.829095 ==
2288 22:12:48.832865 [Duty_Offset_Calibration]
2289 22:12:48.832950 B0:2 B1:1 CA:1
2290 22:12:48.833015
2291 22:12:48.835744 [DutyScan_Calibration_Flow] k_type=0
2292 22:12:48.845826
2293 22:12:48.845955 ==CLK 0==
2294 22:12:48.849222 Final CLK duty delay cell = 0
2295 22:12:48.852731 [0] MAX Duty = 5187%(X100), DQS PI = 24
2296 22:12:48.855689 [0] MIN Duty = 4844%(X100), DQS PI = 46
2297 22:12:48.855779 [0] AVG Duty = 5015%(X100)
2298 22:12:48.859259
2299 22:12:48.862752 CH0 CLK Duty spec in!! Max-Min= 343%
2300 22:12:48.865804 [DutyScan_Calibration_Flow] ====Done====
2301 22:12:48.865891
2302 22:12:48.869489 [DutyScan_Calibration_Flow] k_type=1
2303 22:12:48.883832
2304 22:12:48.883976 ==DQS 0 ==
2305 22:12:48.887147 Final DQS duty delay cell = -4
2306 22:12:48.890232 [-4] MAX Duty = 5124%(X100), DQS PI = 24
2307 22:12:48.893458 [-4] MIN Duty = 4751%(X100), DQS PI = 0
2308 22:12:48.897080 [-4] AVG Duty = 4937%(X100)
2309 22:12:48.897167
2310 22:12:48.897230 ==DQS 1 ==
2311 22:12:48.900139 Final DQS duty delay cell = -4
2312 22:12:48.903922 [-4] MAX Duty = 4969%(X100), DQS PI = 0
2313 22:12:48.906951 [-4] MIN Duty = 4844%(X100), DQS PI = 32
2314 22:12:48.910329 [-4] AVG Duty = 4906%(X100)
2315 22:12:48.910415
2316 22:12:48.913718 CH0 DQS 0 Duty spec in!! Max-Min= 373%
2317 22:12:48.913802
2318 22:12:48.917027 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2319 22:12:48.920751 [DutyScan_Calibration_Flow] ====Done====
2320 22:12:48.920844
2321 22:12:48.923621 [DutyScan_Calibration_Flow] k_type=3
2322 22:12:48.940870
2323 22:12:48.941020 ==DQM 0 ==
2324 22:12:48.944030 Final DQM duty delay cell = 0
2325 22:12:48.947554 [0] MAX Duty = 5156%(X100), DQS PI = 30
2326 22:12:48.950820 [0] MIN Duty = 4906%(X100), DQS PI = 52
2327 22:12:48.954307 [0] AVG Duty = 5031%(X100)
2328 22:12:48.954395
2329 22:12:48.954458 ==DQM 1 ==
2330 22:12:48.957525 Final DQM duty delay cell = 0
2331 22:12:48.960652 [0] MAX Duty = 5124%(X100), DQS PI = 8
2332 22:12:48.964179 [0] MIN Duty = 5031%(X100), DQS PI = 36
2333 22:12:48.964266 [0] AVG Duty = 5077%(X100)
2334 22:12:48.967645
2335 22:12:48.970981 CH0 DQM 0 Duty spec in!! Max-Min= 250%
2336 22:12:48.971079
2337 22:12:48.974204 CH0 DQM 1 Duty spec in!! Max-Min= 93%
2338 22:12:48.977432 [DutyScan_Calibration_Flow] ====Done====
2339 22:12:48.977547
2340 22:12:48.981021 [DutyScan_Calibration_Flow] k_type=2
2341 22:12:48.997079
2342 22:12:48.997224 ==DQ 0 ==
2343 22:12:49.000687 Final DQ duty delay cell = 0
2344 22:12:49.003952 [0] MAX Duty = 5062%(X100), DQS PI = 32
2345 22:12:49.007433 [0] MIN Duty = 4875%(X100), DQS PI = 0
2346 22:12:49.007525 [0] AVG Duty = 4968%(X100)
2347 22:12:49.007593
2348 22:12:49.010636 ==DQ 1 ==
2349 22:12:49.013706 Final DQ duty delay cell = 0
2350 22:12:49.017101 [0] MAX Duty = 5093%(X100), DQS PI = 8
2351 22:12:49.020700 [0] MIN Duty = 4938%(X100), DQS PI = 36
2352 22:12:49.020794 [0] AVG Duty = 5015%(X100)
2353 22:12:49.020863
2354 22:12:49.024186 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2355 22:12:49.024273
2356 22:12:49.027443 CH0 DQ 1 Duty spec in!! Max-Min= 155%
2357 22:12:49.034177 [DutyScan_Calibration_Flow] ====Done====
2358 22:12:49.034279 ==
2359 22:12:49.037174 Dram Type= 6, Freq= 0, CH_1, rank 0
2360 22:12:49.040342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2361 22:12:49.040430 ==
2362 22:12:49.043828 [Duty_Offset_Calibration]
2363 22:12:49.043913 B0:1 B1:0 CA:0
2364 22:12:49.043979
2365 22:12:49.046935 [DutyScan_Calibration_Flow] k_type=0
2366 22:12:49.056491
2367 22:12:49.056611 ==CLK 0==
2368 22:12:49.059771 Final CLK duty delay cell = -4
2369 22:12:49.062551 [-4] MAX Duty = 5000%(X100), DQS PI = 22
2370 22:12:49.066143 [-4] MIN Duty = 4907%(X100), DQS PI = 12
2371 22:12:49.069664 [-4] AVG Duty = 4953%(X100)
2372 22:12:49.069755
2373 22:12:49.072578 CH1 CLK Duty spec in!! Max-Min= 93%
2374 22:12:49.075992 [DutyScan_Calibration_Flow] ====Done====
2375 22:12:49.076082
2376 22:12:49.079527 [DutyScan_Calibration_Flow] k_type=1
2377 22:12:49.095759
2378 22:12:49.095905 ==DQS 0 ==
2379 22:12:49.099440 Final DQS duty delay cell = 0
2380 22:12:49.102307 [0] MAX Duty = 5094%(X100), DQS PI = 28
2381 22:12:49.105949 [0] MIN Duty = 4875%(X100), DQS PI = 0
2382 22:12:49.106043 [0] AVG Duty = 4984%(X100)
2383 22:12:49.109109
2384 22:12:49.109194 ==DQS 1 ==
2385 22:12:49.112294 Final DQS duty delay cell = 0
2386 22:12:49.115836 [0] MAX Duty = 5187%(X100), DQS PI = 18
2387 22:12:49.119392 [0] MIN Duty = 4969%(X100), DQS PI = 10
2388 22:12:49.122499 [0] AVG Duty = 5078%(X100)
2389 22:12:49.122590
2390 22:12:49.125693 CH1 DQS 0 Duty spec in!! Max-Min= 219%
2391 22:12:49.125803
2392 22:12:49.129154 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2393 22:12:49.132521 [DutyScan_Calibration_Flow] ====Done====
2394 22:12:49.132610
2395 22:12:49.135612 [DutyScan_Calibration_Flow] k_type=3
2396 22:12:49.152257
2397 22:12:49.152405 ==DQM 0 ==
2398 22:12:49.155795 Final DQM duty delay cell = 0
2399 22:12:49.159272 [0] MAX Duty = 5156%(X100), DQS PI = 6
2400 22:12:49.162720 [0] MIN Duty = 5031%(X100), DQS PI = 0
2401 22:12:49.162815 [0] AVG Duty = 5093%(X100)
2402 22:12:49.165492
2403 22:12:49.165601 ==DQM 1 ==
2404 22:12:49.169076 Final DQM duty delay cell = 0
2405 22:12:49.172288 [0] MAX Duty = 5031%(X100), DQS PI = 16
2406 22:12:49.175792 [0] MIN Duty = 4907%(X100), DQS PI = 34
2407 22:12:49.175876 [0] AVG Duty = 4969%(X100)
2408 22:12:49.179198
2409 22:12:49.182505 CH1 DQM 0 Duty spec in!! Max-Min= 125%
2410 22:12:49.182592
2411 22:12:49.186195 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2412 22:12:49.188936 [DutyScan_Calibration_Flow] ====Done====
2413 22:12:49.189021
2414 22:12:49.192441 [DutyScan_Calibration_Flow] k_type=2
2415 22:12:49.208047
2416 22:12:49.208197 ==DQ 0 ==
2417 22:12:49.211717 Final DQ duty delay cell = -4
2418 22:12:49.214785 [-4] MAX Duty = 5094%(X100), DQS PI = 10
2419 22:12:49.218299 [-4] MIN Duty = 4938%(X100), DQS PI = 0
2420 22:12:49.218394 [-4] AVG Duty = 5016%(X100)
2421 22:12:49.221483
2422 22:12:49.221592 ==DQ 1 ==
2423 22:12:49.224913 Final DQ duty delay cell = 0
2424 22:12:49.228581 [0] MAX Duty = 5125%(X100), DQS PI = 18
2425 22:12:49.231670 [0] MIN Duty = 4969%(X100), DQS PI = 12
2426 22:12:49.231758 [0] AVG Duty = 5047%(X100)
2427 22:12:49.231823
2428 22:12:49.237971 CH1 DQ 0 Duty spec in!! Max-Min= 156%
2429 22:12:49.238068
2430 22:12:49.241437 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2431 22:12:49.244674 [DutyScan_Calibration_Flow] ====Done====
2432 22:12:49.248235 nWR fixed to 30
2433 22:12:49.248324 [ModeRegInit_LP4] CH0 RK0
2434 22:12:49.251465 [ModeRegInit_LP4] CH0 RK1
2435 22:12:49.255067 [ModeRegInit_LP4] CH1 RK0
2436 22:12:49.257985 [ModeRegInit_LP4] CH1 RK1
2437 22:12:49.258072 match AC timing 7
2438 22:12:49.261736 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2439 22:12:49.265178 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2440 22:12:49.271555 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2441 22:12:49.274977 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2442 22:12:49.281992 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2443 22:12:49.282103 ==
2444 22:12:49.284937 Dram Type= 6, Freq= 0, CH_0, rank 0
2445 22:12:49.288310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2446 22:12:49.288401 ==
2447 22:12:49.294999 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2448 22:12:49.298584 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2449 22:12:49.308648 [CA 0] Center 39 (8~70) winsize 63
2450 22:12:49.311971 [CA 1] Center 39 (8~70) winsize 63
2451 22:12:49.315222 [CA 2] Center 35 (5~66) winsize 62
2452 22:12:49.318077 [CA 3] Center 34 (4~65) winsize 62
2453 22:12:49.321962 [CA 4] Center 33 (3~64) winsize 62
2454 22:12:49.324832 [CA 5] Center 32 (3~62) winsize 60
2455 22:12:49.324922
2456 22:12:49.328428 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2457 22:12:49.328518
2458 22:12:49.331520 [CATrainingPosCal] consider 1 rank data
2459 22:12:49.335151 u2DelayCellTimex100 = 270/100 ps
2460 22:12:49.338616 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2461 22:12:49.341791 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2462 22:12:49.348334 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2463 22:12:49.351888 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2464 22:12:49.355587 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2465 22:12:49.358668 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2466 22:12:49.358758
2467 22:12:49.361547 CA PerBit enable=1, Macro0, CA PI delay=32
2468 22:12:49.361651
2469 22:12:49.365439 [CBTSetCACLKResult] CA Dly = 32
2470 22:12:49.365588 CS Dly: 6 (0~37)
2471 22:12:49.365673 ==
2472 22:12:49.368382 Dram Type= 6, Freq= 0, CH_0, rank 1
2473 22:12:49.375328 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2474 22:12:49.375434 ==
2475 22:12:49.378720 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2476 22:12:49.385139 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2477 22:12:49.394059 [CA 0] Center 38 (8~69) winsize 62
2478 22:12:49.397412 [CA 1] Center 38 (8~69) winsize 62
2479 22:12:49.400910 [CA 2] Center 35 (4~66) winsize 63
2480 22:12:49.404003 [CA 3] Center 34 (4~65) winsize 62
2481 22:12:49.408216 [CA 4] Center 33 (3~63) winsize 61
2482 22:12:49.410902 [CA 5] Center 32 (3~62) winsize 60
2483 22:12:49.411018
2484 22:12:49.414394 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2485 22:12:49.414482
2486 22:12:49.417363 [CATrainingPosCal] consider 2 rank data
2487 22:12:49.421066 u2DelayCellTimex100 = 270/100 ps
2488 22:12:49.424453 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2489 22:12:49.427425 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2490 22:12:49.434289 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2491 22:12:49.437931 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2492 22:12:49.440865 CA4 delay=33 (3~63),Diff = 1 PI (4 cell)
2493 22:12:49.444477 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2494 22:12:49.444569
2495 22:12:49.448136 CA PerBit enable=1, Macro0, CA PI delay=32
2496 22:12:49.448224
2497 22:12:49.451073 [CBTSetCACLKResult] CA Dly = 32
2498 22:12:49.451159 CS Dly: 6 (0~38)
2499 22:12:49.451243
2500 22:12:49.454546 ----->DramcWriteLeveling(PI) begin...
2501 22:12:49.454635 ==
2502 22:12:49.457524 Dram Type= 6, Freq= 0, CH_0, rank 0
2503 22:12:49.464475 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2504 22:12:49.464576 ==
2505 22:12:49.467528 Write leveling (Byte 0): 34 => 34
2506 22:12:49.471269 Write leveling (Byte 1): 29 => 29
2507 22:12:49.471359 DramcWriteLeveling(PI) end<-----
2508 22:12:49.474321
2509 22:12:49.474407 ==
2510 22:12:49.477637 Dram Type= 6, Freq= 0, CH_0, rank 0
2511 22:12:49.480750 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2512 22:12:49.480864 ==
2513 22:12:49.484191 [Gating] SW mode calibration
2514 22:12:49.490879 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2515 22:12:49.494484 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2516 22:12:49.501324 0 15 0 | B1->B0 | 2323 3333 | 0 0 | (0 0) (1 1)
2517 22:12:49.504295 0 15 4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
2518 22:12:49.507774 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2519 22:12:49.514088 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2520 22:12:49.517416 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2521 22:12:49.520982 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2522 22:12:49.527613 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
2523 22:12:49.531074 0 15 28 | B1->B0 | 3434 2424 | 0 0 | (0 0) (1 0)
2524 22:12:49.534859 1 0 0 | B1->B0 | 2828 2323 | 1 0 | (1 0) (1 0)
2525 22:12:49.541457 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2526 22:12:49.544442 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2527 22:12:49.547984 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2528 22:12:49.551061 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2529 22:12:49.558035 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2530 22:12:49.560985 1 0 24 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (0 0)
2531 22:12:49.564739 1 0 28 | B1->B0 | 2828 4646 | 0 0 | (0 0) (0 0)
2532 22:12:49.571429 1 1 0 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
2533 22:12:49.574423 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2534 22:12:49.577479 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2535 22:12:49.584126 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2536 22:12:49.587634 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2537 22:12:49.590964 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2538 22:12:49.597962 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2539 22:12:49.600834 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2540 22:12:49.604271 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2541 22:12:49.611157 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2542 22:12:49.614427 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2543 22:12:49.617864 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2544 22:12:49.624758 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2545 22:12:49.627963 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2546 22:12:49.631513 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2547 22:12:49.637644 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2548 22:12:49.641085 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2549 22:12:49.644914 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2550 22:12:49.651334 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2551 22:12:49.654350 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2552 22:12:49.658071 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2553 22:12:49.660978 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 22:12:49.667584 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2555 22:12:49.671302 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2556 22:12:49.674388 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2557 22:12:49.678032 Total UI for P1: 0, mck2ui 16
2558 22:12:49.681203 best dqsien dly found for B0: ( 1, 3, 26)
2559 22:12:49.687849 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2560 22:12:49.687978 Total UI for P1: 0, mck2ui 16
2561 22:12:49.694367 best dqsien dly found for B1: ( 1, 4, 0)
2562 22:12:49.697779 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2563 22:12:49.701295 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2564 22:12:49.701408
2565 22:12:49.704543 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2566 22:12:49.708022 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2567 22:12:49.711557 [Gating] SW calibration Done
2568 22:12:49.711665 ==
2569 22:12:49.714842 Dram Type= 6, Freq= 0, CH_0, rank 0
2570 22:12:49.717961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2571 22:12:49.718069 ==
2572 22:12:49.721640 RX Vref Scan: 0
2573 22:12:49.721730
2574 22:12:49.721830 RX Vref 0 -> 0, step: 1
2575 22:12:49.721921
2576 22:12:49.725126 RX Delay -40 -> 252, step: 8
2577 22:12:49.728376 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2578 22:12:49.731402 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2579 22:12:49.738246 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2580 22:12:49.742031 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2581 22:12:49.744897 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2582 22:12:49.748427 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2583 22:12:49.751523 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2584 22:12:49.758798 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2585 22:12:49.762064 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2586 22:12:49.765182 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
2587 22:12:49.768686 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
2588 22:12:49.772150 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2589 22:12:49.775070 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2590 22:12:49.781871 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2591 22:12:49.785045 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2592 22:12:49.788455 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2593 22:12:49.788557 ==
2594 22:12:49.792245 Dram Type= 6, Freq= 0, CH_0, rank 0
2595 22:12:49.795429 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2596 22:12:49.798843 ==
2597 22:12:49.798966 DQS Delay:
2598 22:12:49.799060 DQS0 = 0, DQS1 = 0
2599 22:12:49.801770 DQM Delay:
2600 22:12:49.801871 DQM0 = 121, DQM1 = 114
2601 22:12:49.804865 DQ Delay:
2602 22:12:49.808411 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2603 22:12:49.812007 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2604 22:12:49.815070 DQ8 =99, DQ9 =107, DQ10 =115, DQ11 =107
2605 22:12:49.818298 DQ12 =119, DQ13 =123, DQ14 =123, DQ15 =119
2606 22:12:49.818411
2607 22:12:49.818507
2608 22:12:49.818651 ==
2609 22:12:49.821809 Dram Type= 6, Freq= 0, CH_0, rank 0
2610 22:12:49.825364 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2611 22:12:49.825472 ==
2612 22:12:49.825590
2613 22:12:49.825655
2614 22:12:49.828564 TX Vref Scan disable
2615 22:12:49.831863 == TX Byte 0 ==
2616 22:12:49.835272 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2617 22:12:49.838395 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2618 22:12:49.841884 == TX Byte 1 ==
2619 22:12:49.845412 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2620 22:12:49.848924 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2621 22:12:49.849035 ==
2622 22:12:49.851814 Dram Type= 6, Freq= 0, CH_0, rank 0
2623 22:12:49.855682 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2624 22:12:49.858726 ==
2625 22:12:49.869102 TX Vref=22, minBit 0, minWin=24, winSum=402
2626 22:12:49.872661 TX Vref=24, minBit 0, minWin=24, winSum=415
2627 22:12:49.875878 TX Vref=26, minBit 0, minWin=26, winSum=422
2628 22:12:49.879338 TX Vref=28, minBit 0, minWin=26, winSum=423
2629 22:12:49.882304 TX Vref=30, minBit 0, minWin=26, winSum=420
2630 22:12:49.885952 TX Vref=32, minBit 0, minWin=26, winSum=423
2631 22:12:49.892684 [TxChooseVref] Worse bit 0, Min win 26, Win sum 423, Final Vref 28
2632 22:12:49.892813
2633 22:12:49.896250 Final TX Range 1 Vref 28
2634 22:12:49.896354
2635 22:12:49.896455 ==
2636 22:12:49.899307 Dram Type= 6, Freq= 0, CH_0, rank 0
2637 22:12:49.902363 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2638 22:12:49.902469 ==
2639 22:12:49.902566
2640 22:12:49.902661
2641 22:12:49.906412 TX Vref Scan disable
2642 22:12:49.909133 == TX Byte 0 ==
2643 22:12:49.912576 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2644 22:12:49.916158 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2645 22:12:49.919061 == TX Byte 1 ==
2646 22:12:49.922534 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2647 22:12:49.925995 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2648 22:12:49.926102
2649 22:12:49.929503 [DATLAT]
2650 22:12:49.929613 Freq=1200, CH0 RK0
2651 22:12:49.929681
2652 22:12:49.932592 DATLAT Default: 0xd
2653 22:12:49.932671 0, 0xFFFF, sum = 0
2654 22:12:49.935637 1, 0xFFFF, sum = 0
2655 22:12:49.935740 2, 0xFFFF, sum = 0
2656 22:12:49.938926 3, 0xFFFF, sum = 0
2657 22:12:49.939029 4, 0xFFFF, sum = 0
2658 22:12:49.942453 5, 0xFFFF, sum = 0
2659 22:12:49.942556 6, 0xFFFF, sum = 0
2660 22:12:49.945736 7, 0xFFFF, sum = 0
2661 22:12:49.945846 8, 0xFFFF, sum = 0
2662 22:12:49.949344 9, 0xFFFF, sum = 0
2663 22:12:49.949448 10, 0xFFFF, sum = 0
2664 22:12:49.952257 11, 0xFFFF, sum = 0
2665 22:12:49.952359 12, 0x0, sum = 1
2666 22:12:49.955997 13, 0x0, sum = 2
2667 22:12:49.956109 14, 0x0, sum = 3
2668 22:12:49.959756 15, 0x0, sum = 4
2669 22:12:49.959858 best_step = 13
2670 22:12:49.959946
2671 22:12:49.960043 ==
2672 22:12:49.962573 Dram Type= 6, Freq= 0, CH_0, rank 0
2673 22:12:49.969260 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2674 22:12:49.969376 ==
2675 22:12:49.969469 RX Vref Scan: 1
2676 22:12:49.969605
2677 22:12:49.972978 Set Vref Range= 32 -> 127
2678 22:12:49.973087
2679 22:12:49.975944 RX Vref 32 -> 127, step: 1
2680 22:12:49.976045
2681 22:12:49.976135 RX Delay -13 -> 252, step: 4
2682 22:12:49.979771
2683 22:12:49.979874 Set Vref, RX VrefLevel [Byte0]: 32
2684 22:12:49.982807 [Byte1]: 32
2685 22:12:49.987362
2686 22:12:49.987479 Set Vref, RX VrefLevel [Byte0]: 33
2687 22:12:49.990466 [Byte1]: 33
2688 22:12:49.995381
2689 22:12:49.995493 Set Vref, RX VrefLevel [Byte0]: 34
2690 22:12:49.998305 [Byte1]: 34
2691 22:12:50.003086
2692 22:12:50.003197 Set Vref, RX VrefLevel [Byte0]: 35
2693 22:12:50.006283 [Byte1]: 35
2694 22:12:50.011060
2695 22:12:50.011180 Set Vref, RX VrefLevel [Byte0]: 36
2696 22:12:50.014660 [Byte1]: 36
2697 22:12:50.018603
2698 22:12:50.018725 Set Vref, RX VrefLevel [Byte0]: 37
2699 22:12:50.021915 [Byte1]: 37
2700 22:12:50.026746
2701 22:12:50.026863 Set Vref, RX VrefLevel [Byte0]: 38
2702 22:12:50.030086 [Byte1]: 38
2703 22:12:50.034995
2704 22:12:50.035083 Set Vref, RX VrefLevel [Byte0]: 39
2705 22:12:50.037988 [Byte1]: 39
2706 22:12:50.042207
2707 22:12:50.042301 Set Vref, RX VrefLevel [Byte0]: 40
2708 22:12:50.046089 [Byte1]: 40
2709 22:12:50.050333
2710 22:12:50.050434 Set Vref, RX VrefLevel [Byte0]: 41
2711 22:12:50.053646 [Byte1]: 41
2712 22:12:50.058180
2713 22:12:50.058277 Set Vref, RX VrefLevel [Byte0]: 42
2714 22:12:50.061671 [Byte1]: 42
2715 22:12:50.065995
2716 22:12:50.066088 Set Vref, RX VrefLevel [Byte0]: 43
2717 22:12:50.069684 [Byte1]: 43
2718 22:12:50.074666
2719 22:12:50.074760 Set Vref, RX VrefLevel [Byte0]: 44
2720 22:12:50.077694 [Byte1]: 44
2721 22:12:50.081727
2722 22:12:50.081817 Set Vref, RX VrefLevel [Byte0]: 45
2723 22:12:50.085409 [Byte1]: 45
2724 22:12:50.089718
2725 22:12:50.089810 Set Vref, RX VrefLevel [Byte0]: 46
2726 22:12:50.093380 [Byte1]: 46
2727 22:12:50.097784
2728 22:12:50.097877 Set Vref, RX VrefLevel [Byte0]: 47
2729 22:12:50.101360 [Byte1]: 47
2730 22:12:50.105593
2731 22:12:50.105683 Set Vref, RX VrefLevel [Byte0]: 48
2732 22:12:50.108727 [Byte1]: 48
2733 22:12:50.113285
2734 22:12:50.113408 Set Vref, RX VrefLevel [Byte0]: 49
2735 22:12:50.116566 [Byte1]: 49
2736 22:12:50.121307
2737 22:12:50.121440 Set Vref, RX VrefLevel [Byte0]: 50
2738 22:12:50.124602 [Byte1]: 50
2739 22:12:50.129087
2740 22:12:50.129214 Set Vref, RX VrefLevel [Byte0]: 51
2741 22:12:50.132508 [Byte1]: 51
2742 22:12:50.137153
2743 22:12:50.137274 Set Vref, RX VrefLevel [Byte0]: 52
2744 22:12:50.140512 [Byte1]: 52
2745 22:12:50.145032
2746 22:12:50.145124 Set Vref, RX VrefLevel [Byte0]: 53
2747 22:12:50.148600 [Byte1]: 53
2748 22:12:50.153007
2749 22:12:50.153108 Set Vref, RX VrefLevel [Byte0]: 54
2750 22:12:50.156087 [Byte1]: 54
2751 22:12:50.160766
2752 22:12:50.160856 Set Vref, RX VrefLevel [Byte0]: 55
2753 22:12:50.164076 [Byte1]: 55
2754 22:12:50.169063
2755 22:12:50.169179 Set Vref, RX VrefLevel [Byte0]: 56
2756 22:12:50.171991 [Byte1]: 56
2757 22:12:50.176449
2758 22:12:50.176535 Set Vref, RX VrefLevel [Byte0]: 57
2759 22:12:50.179530 [Byte1]: 57
2760 22:12:50.184448
2761 22:12:50.184550 Set Vref, RX VrefLevel [Byte0]: 58
2762 22:12:50.187495 [Byte1]: 58
2763 22:12:50.192369
2764 22:12:50.192455 Set Vref, RX VrefLevel [Byte0]: 59
2765 22:12:50.195394 [Byte1]: 59
2766 22:12:50.200231
2767 22:12:50.200328 Set Vref, RX VrefLevel [Byte0]: 60
2768 22:12:50.203309 [Byte1]: 60
2769 22:12:50.208156
2770 22:12:50.208241 Set Vref, RX VrefLevel [Byte0]: 61
2771 22:12:50.211846 [Byte1]: 61
2772 22:12:50.216158
2773 22:12:50.216239 Set Vref, RX VrefLevel [Byte0]: 62
2774 22:12:50.219680 [Byte1]: 62
2775 22:12:50.224113
2776 22:12:50.224230 Set Vref, RX VrefLevel [Byte0]: 63
2777 22:12:50.227483 [Byte1]: 63
2778 22:12:50.232191
2779 22:12:50.232289 Set Vref, RX VrefLevel [Byte0]: 64
2780 22:12:50.234992 [Byte1]: 64
2781 22:12:50.239575
2782 22:12:50.239671 Set Vref, RX VrefLevel [Byte0]: 65
2783 22:12:50.243241 [Byte1]: 65
2784 22:12:50.247698
2785 22:12:50.247801 Set Vref, RX VrefLevel [Byte0]: 66
2786 22:12:50.250833 [Byte1]: 66
2787 22:12:50.255282
2788 22:12:50.255378 Set Vref, RX VrefLevel [Byte0]: 67
2789 22:12:50.259014 [Byte1]: 67
2790 22:12:50.263525
2791 22:12:50.263622 Set Vref, RX VrefLevel [Byte0]: 68
2792 22:12:50.266749 [Byte1]: 68
2793 22:12:50.271106
2794 22:12:50.271202 Set Vref, RX VrefLevel [Byte0]: 69
2795 22:12:50.274755 [Byte1]: 69
2796 22:12:50.278873
2797 22:12:50.278966 Set Vref, RX VrefLevel [Byte0]: 70
2798 22:12:50.282511 [Byte1]: 70
2799 22:12:50.286822
2800 22:12:50.286915 Final RX Vref Byte 0 = 55 to rank0
2801 22:12:50.290106 Final RX Vref Byte 1 = 53 to rank0
2802 22:12:50.293625 Final RX Vref Byte 0 = 55 to rank1
2803 22:12:50.296924 Final RX Vref Byte 1 = 53 to rank1==
2804 22:12:50.300550 Dram Type= 6, Freq= 0, CH_0, rank 0
2805 22:12:50.304013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2806 22:12:50.306915 ==
2807 22:12:50.307006 DQS Delay:
2808 22:12:50.307073 DQS0 = 0, DQS1 = 0
2809 22:12:50.310714 DQM Delay:
2810 22:12:50.310800 DQM0 = 120, DQM1 = 113
2811 22:12:50.313707 DQ Delay:
2812 22:12:50.316893 DQ0 =120, DQ1 =120, DQ2 =118, DQ3 =120
2813 22:12:50.320511 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =128
2814 22:12:50.323640 DQ8 =100, DQ9 =102, DQ10 =116, DQ11 =106
2815 22:12:50.327314 DQ12 =120, DQ13 =116, DQ14 =126, DQ15 =122
2816 22:12:50.327405
2817 22:12:50.327472
2818 22:12:50.333498 [DQSOSCAuto] RK0, (LSB)MR18= 0x140d, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 402 ps
2819 22:12:50.337532 CH0 RK0: MR19=404, MR18=140D
2820 22:12:50.343790 CH0_RK0: MR19=0x404, MR18=0x140D, DQSOSC=402, MR23=63, INC=40, DEC=27
2821 22:12:50.343901
2822 22:12:50.347435 ----->DramcWriteLeveling(PI) begin...
2823 22:12:50.347524 ==
2824 22:12:50.350811 Dram Type= 6, Freq= 0, CH_0, rank 1
2825 22:12:50.353802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2826 22:12:50.357420 ==
2827 22:12:50.357545 Write leveling (Byte 0): 35 => 35
2828 22:12:50.360553 Write leveling (Byte 1): 29 => 29
2829 22:12:50.364271 DramcWriteLeveling(PI) end<-----
2830 22:12:50.364361
2831 22:12:50.364428 ==
2832 22:12:50.367062 Dram Type= 6, Freq= 0, CH_0, rank 1
2833 22:12:50.373985 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2834 22:12:50.374095 ==
2835 22:12:50.374164 [Gating] SW mode calibration
2836 22:12:50.384365 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2837 22:12:50.387257 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2838 22:12:50.391085 0 15 0 | B1->B0 | 3333 3030 | 1 1 | (1 1) (1 1)
2839 22:12:50.397562 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2840 22:12:50.400771 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2841 22:12:50.404301 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2842 22:12:50.410977 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2843 22:12:50.413870 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2844 22:12:50.417500 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2845 22:12:50.423861 0 15 28 | B1->B0 | 3030 2b2b | 0 1 | (0 1) (1 0)
2846 22:12:50.427654 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
2847 22:12:50.430757 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2848 22:12:50.437197 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2849 22:12:50.440758 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2850 22:12:50.444148 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2851 22:12:50.450561 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2852 22:12:50.453998 1 0 24 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
2853 22:12:50.457423 1 0 28 | B1->B0 | 3737 3636 | 0 0 | (0 0) (1 1)
2854 22:12:50.460691 1 1 0 | B1->B0 | 4646 4544 | 0 1 | (0 0) (0 0)
2855 22:12:50.467690 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2856 22:12:50.470659 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2857 22:12:50.473984 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2858 22:12:50.480778 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2859 22:12:50.484071 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2860 22:12:50.487954 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2861 22:12:50.494144 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2862 22:12:50.497686 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2863 22:12:50.500635 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2864 22:12:50.507561 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2865 22:12:50.510708 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2866 22:12:50.514229 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2867 22:12:50.520699 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2868 22:12:50.523867 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2869 22:12:50.527566 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2870 22:12:50.534124 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2871 22:12:50.537229 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2872 22:12:50.540809 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2873 22:12:50.547520 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2874 22:12:50.551183 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2875 22:12:50.554602 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2876 22:12:50.558020 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
2877 22:12:50.564444 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2878 22:12:50.567635 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2879 22:12:50.571041 Total UI for P1: 0, mck2ui 16
2880 22:12:50.574099 best dqsien dly found for B0: ( 1, 3, 28)
2881 22:12:50.577405 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2882 22:12:50.581142 Total UI for P1: 0, mck2ui 16
2883 22:12:50.584602 best dqsien dly found for B1: ( 1, 3, 28)
2884 22:12:50.587698 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2885 22:12:50.591168 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2886 22:12:50.591259
2887 22:12:50.597886 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2888 22:12:50.601106 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2889 22:12:50.601212 [Gating] SW calibration Done
2890 22:12:50.604503 ==
2891 22:12:50.604599 Dram Type= 6, Freq= 0, CH_0, rank 1
2892 22:12:50.611484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2893 22:12:50.611595 ==
2894 22:12:50.611688 RX Vref Scan: 0
2895 22:12:50.611776
2896 22:12:50.614364 RX Vref 0 -> 0, step: 1
2897 22:12:50.614464
2898 22:12:50.617895 RX Delay -40 -> 252, step: 8
2899 22:12:50.620964 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2900 22:12:50.624562 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2901 22:12:50.627641 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2902 22:12:50.634387 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2903 22:12:50.638139 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2904 22:12:50.641101 iDelay=200, Bit 5, Center 119 (48 ~ 191) 144
2905 22:12:50.644818 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2906 22:12:50.647700 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2907 22:12:50.651323 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2908 22:12:50.658144 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2909 22:12:50.661342 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2910 22:12:50.664595 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2911 22:12:50.668031 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2912 22:12:50.671373 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2913 22:12:50.677890 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2914 22:12:50.681465 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
2915 22:12:50.681596 ==
2916 22:12:50.684361 Dram Type= 6, Freq= 0, CH_0, rank 1
2917 22:12:50.687803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2918 22:12:50.687907 ==
2919 22:12:50.690940 DQS Delay:
2920 22:12:50.691040 DQS0 = 0, DQS1 = 0
2921 22:12:50.691134 DQM Delay:
2922 22:12:50.694349 DQM0 = 122, DQM1 = 112
2923 22:12:50.694449 DQ Delay:
2924 22:12:50.698219 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =119
2925 22:12:50.701787 DQ4 =127, DQ5 =119, DQ6 =127, DQ7 =127
2926 22:12:50.704541 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
2927 22:12:50.711703 DQ12 =115, DQ13 =119, DQ14 =123, DQ15 =123
2928 22:12:50.711808
2929 22:12:50.711902
2930 22:12:50.711989 ==
2931 22:12:50.714791 Dram Type= 6, Freq= 0, CH_0, rank 1
2932 22:12:50.718330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2933 22:12:50.718433 ==
2934 22:12:50.718523
2935 22:12:50.718614
2936 22:12:50.721640 TX Vref Scan disable
2937 22:12:50.721743 == TX Byte 0 ==
2938 22:12:50.728028 Update DQ dly =855 (3 ,2, 23) DQ OEN =(2 ,7)
2939 22:12:50.731788 Update DQM dly =855 (3 ,2, 23) DQM OEN =(2 ,7)
2940 22:12:50.731891 == TX Byte 1 ==
2941 22:12:50.737934 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2942 22:12:50.741648 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2943 22:12:50.741752 ==
2944 22:12:50.744650 Dram Type= 6, Freq= 0, CH_0, rank 1
2945 22:12:50.748354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2946 22:12:50.748458 ==
2947 22:12:50.761200 TX Vref=22, minBit 1, minWin=25, winSum=419
2948 22:12:50.764485 TX Vref=24, minBit 0, minWin=26, winSum=427
2949 22:12:50.767931 TX Vref=26, minBit 3, minWin=25, winSum=426
2950 22:12:50.771397 TX Vref=28, minBit 1, minWin=26, winSum=429
2951 22:12:50.774782 TX Vref=30, minBit 5, minWin=25, winSum=435
2952 22:12:50.778438 TX Vref=32, minBit 5, minWin=25, winSum=428
2953 22:12:50.784969 [TxChooseVref] Worse bit 1, Min win 26, Win sum 429, Final Vref 28
2954 22:12:50.785076
2955 22:12:50.788102 Final TX Range 1 Vref 28
2956 22:12:50.788205
2957 22:12:50.788301 ==
2958 22:12:50.791576 Dram Type= 6, Freq= 0, CH_0, rank 1
2959 22:12:50.794960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2960 22:12:50.795052 ==
2961 22:12:50.795123
2962 22:12:50.795187
2963 22:12:50.798368 TX Vref Scan disable
2964 22:12:50.802001 == TX Byte 0 ==
2965 22:12:50.804780 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2966 22:12:50.808316 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2967 22:12:50.811517 == TX Byte 1 ==
2968 22:12:50.815093 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2969 22:12:50.818501 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2970 22:12:50.818602
2971 22:12:50.821853 [DATLAT]
2972 22:12:50.821961 Freq=1200, CH0 RK1
2973 22:12:50.822055
2974 22:12:50.825398 DATLAT Default: 0xd
2975 22:12:50.825499 0, 0xFFFF, sum = 0
2976 22:12:50.828422 1, 0xFFFF, sum = 0
2977 22:12:50.828525 2, 0xFFFF, sum = 0
2978 22:12:50.832205 3, 0xFFFF, sum = 0
2979 22:12:50.832316 4, 0xFFFF, sum = 0
2980 22:12:50.835012 5, 0xFFFF, sum = 0
2981 22:12:50.835116 6, 0xFFFF, sum = 0
2982 22:12:50.838579 7, 0xFFFF, sum = 0
2983 22:12:50.838689 8, 0xFFFF, sum = 0
2984 22:12:50.842382 9, 0xFFFF, sum = 0
2985 22:12:50.842486 10, 0xFFFF, sum = 0
2986 22:12:50.845637 11, 0xFFFF, sum = 0
2987 22:12:50.845736 12, 0x0, sum = 1
2988 22:12:50.848423 13, 0x0, sum = 2
2989 22:12:50.848524 14, 0x0, sum = 3
2990 22:12:50.851553 15, 0x0, sum = 4
2991 22:12:50.851656 best_step = 13
2992 22:12:50.851745
2993 22:12:50.851843 ==
2994 22:12:50.855280 Dram Type= 6, Freq= 0, CH_0, rank 1
2995 22:12:50.862080 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2996 22:12:50.862183 ==
2997 22:12:50.862274 RX Vref Scan: 0
2998 22:12:50.862373
2999 22:12:50.865005 RX Vref 0 -> 0, step: 1
3000 22:12:50.865113
3001 22:12:50.868616 RX Delay -13 -> 252, step: 4
3002 22:12:50.872295 iDelay=195, Bit 0, Center 120 (51 ~ 190) 140
3003 22:12:50.875243 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3004 22:12:50.878515 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3005 22:12:50.885391 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
3006 22:12:50.888705 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3007 22:12:50.892116 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3008 22:12:50.895566 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3009 22:12:50.898495 iDelay=195, Bit 7, Center 128 (63 ~ 194) 132
3010 22:12:50.905406 iDelay=195, Bit 8, Center 100 (35 ~ 166) 132
3011 22:12:50.908834 iDelay=195, Bit 9, Center 100 (35 ~ 166) 132
3012 22:12:50.911892 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3013 22:12:50.915510 iDelay=195, Bit 11, Center 104 (39 ~ 170) 132
3014 22:12:50.919098 iDelay=195, Bit 12, Center 116 (55 ~ 178) 124
3015 22:12:50.925475 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3016 22:12:50.928574 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3017 22:12:50.932414 iDelay=195, Bit 15, Center 118 (55 ~ 182) 128
3018 22:12:50.932496 ==
3019 22:12:50.935946 Dram Type= 6, Freq= 0, CH_0, rank 1
3020 22:12:50.938705 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3021 22:12:50.938789 ==
3022 22:12:50.942401 DQS Delay:
3023 22:12:50.942484 DQS0 = 0, DQS1 = 0
3024 22:12:50.945405 DQM Delay:
3025 22:12:50.945503 DQM0 = 121, DQM1 = 111
3026 22:12:50.945610 DQ Delay:
3027 22:12:50.952124 DQ0 =120, DQ1 =122, DQ2 =118, DQ3 =118
3028 22:12:50.955389 DQ4 =122, DQ5 =116, DQ6 =126, DQ7 =128
3029 22:12:50.958969 DQ8 =100, DQ9 =100, DQ10 =110, DQ11 =104
3030 22:12:50.962642 DQ12 =116, DQ13 =118, DQ14 =122, DQ15 =118
3031 22:12:50.962741
3032 22:12:50.962807
3033 22:12:50.968563 [DQSOSCAuto] RK1, (LSB)MR18= 0x13f4, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 402 ps
3034 22:12:50.972132 CH0 RK1: MR19=403, MR18=13F4
3035 22:12:50.978762 CH0_RK1: MR19=0x403, MR18=0x13F4, DQSOSC=402, MR23=63, INC=40, DEC=27
3036 22:12:50.982282 [RxdqsGatingPostProcess] freq 1200
3037 22:12:50.989022 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3038 22:12:50.989111 best DQS0 dly(2T, 0.5T) = (0, 11)
3039 22:12:50.992428 best DQS1 dly(2T, 0.5T) = (0, 12)
3040 22:12:50.995765 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3041 22:12:50.999087 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3042 22:12:51.002212 best DQS0 dly(2T, 0.5T) = (0, 11)
3043 22:12:51.005852 best DQS1 dly(2T, 0.5T) = (0, 11)
3044 22:12:51.008718 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3045 22:12:51.012352 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3046 22:12:51.015686 Pre-setting of DQS Precalculation
3047 22:12:51.019197 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3048 22:12:51.019283 ==
3049 22:12:51.022311 Dram Type= 6, Freq= 0, CH_1, rank 0
3050 22:12:51.029345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3051 22:12:51.029454 ==
3052 22:12:51.032651 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3053 22:12:51.039199 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3054 22:12:51.048201 [CA 0] Center 37 (7~67) winsize 61
3055 22:12:51.051219 [CA 1] Center 37 (7~68) winsize 62
3056 22:12:51.054469 [CA 2] Center 35 (5~65) winsize 61
3057 22:12:51.058227 [CA 3] Center 34 (4~64) winsize 61
3058 22:12:51.061125 [CA 4] Center 34 (4~64) winsize 61
3059 22:12:51.064932 [CA 5] Center 33 (3~63) winsize 61
3060 22:12:51.065021
3061 22:12:51.068081 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3062 22:12:51.068167
3063 22:12:51.070911 [CATrainingPosCal] consider 1 rank data
3064 22:12:51.074829 u2DelayCellTimex100 = 270/100 ps
3065 22:12:51.077729 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3066 22:12:51.081116 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3067 22:12:51.087823 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3068 22:12:51.091066 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3069 22:12:51.094361 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3070 22:12:51.097875 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3071 22:12:51.097959
3072 22:12:51.101454 CA PerBit enable=1, Macro0, CA PI delay=33
3073 22:12:51.101546
3074 22:12:51.104842 [CBTSetCACLKResult] CA Dly = 33
3075 22:12:51.104927 CS Dly: 8 (0~39)
3076 22:12:51.104993 ==
3077 22:12:51.108424 Dram Type= 6, Freq= 0, CH_1, rank 1
3078 22:12:51.114558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3079 22:12:51.114673 ==
3080 22:12:51.118239 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3081 22:12:51.124416 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3082 22:12:51.133615 [CA 0] Center 37 (7~68) winsize 62
3083 22:12:51.136818 [CA 1] Center 38 (7~69) winsize 63
3084 22:12:51.140598 [CA 2] Center 35 (5~65) winsize 61
3085 22:12:51.143799 [CA 3] Center 34 (4~65) winsize 62
3086 22:12:51.146998 [CA 4] Center 34 (4~64) winsize 61
3087 22:12:51.150579 [CA 5] Center 34 (4~64) winsize 61
3088 22:12:51.150679
3089 22:12:51.153994 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3090 22:12:51.154108
3091 22:12:51.157076 [CATrainingPosCal] consider 2 rank data
3092 22:12:51.160250 u2DelayCellTimex100 = 270/100 ps
3093 22:12:51.163980 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3094 22:12:51.167185 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3095 22:12:51.170816 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3096 22:12:51.176929 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3097 22:12:51.180411 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3098 22:12:51.183517 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3099 22:12:51.183618
3100 22:12:51.187194 CA PerBit enable=1, Macro0, CA PI delay=33
3101 22:12:51.187271
3102 22:12:51.190653 [CBTSetCACLKResult] CA Dly = 33
3103 22:12:51.190754 CS Dly: 9 (0~41)
3104 22:12:51.190834
3105 22:12:51.193717 ----->DramcWriteLeveling(PI) begin...
3106 22:12:51.193817 ==
3107 22:12:51.197073 Dram Type= 6, Freq= 0, CH_1, rank 0
3108 22:12:51.204043 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3109 22:12:51.204129 ==
3110 22:12:51.206877 Write leveling (Byte 0): 28 => 28
3111 22:12:51.210270 Write leveling (Byte 1): 30 => 30
3112 22:12:51.210350 DramcWriteLeveling(PI) end<-----
3113 22:12:51.210430
3114 22:12:51.213981 ==
3115 22:12:51.217397 Dram Type= 6, Freq= 0, CH_1, rank 0
3116 22:12:51.220919 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3117 22:12:51.221007 ==
3118 22:12:51.223932 [Gating] SW mode calibration
3119 22:12:51.230861 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3120 22:12:51.233656 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3121 22:12:51.240877 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3122 22:12:51.243855 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3123 22:12:51.247351 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3124 22:12:51.254184 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3125 22:12:51.257633 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3126 22:12:51.260545 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3127 22:12:51.267357 0 15 24 | B1->B0 | 2e2e 2727 | 1 0 | (1 0) (0 0)
3128 22:12:51.270463 0 15 28 | B1->B0 | 2727 2323 | 0 0 | (0 0) (1 0)
3129 22:12:51.274037 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3130 22:12:51.277124 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3131 22:12:51.283777 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3132 22:12:51.287303 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3133 22:12:51.291078 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3134 22:12:51.297795 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3135 22:12:51.300663 1 0 24 | B1->B0 | 3131 3e3e | 0 1 | (0 0) (0 0)
3136 22:12:51.303947 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3137 22:12:51.310783 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3138 22:12:51.314013 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3139 22:12:51.317499 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3140 22:12:51.324573 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3141 22:12:51.327844 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3142 22:12:51.330771 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3143 22:12:51.337583 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3144 22:12:51.340929 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3145 22:12:51.343945 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3146 22:12:51.350655 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3147 22:12:51.354308 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3148 22:12:51.357473 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3149 22:12:51.363882 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3150 22:12:51.367399 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3151 22:12:51.371149 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3152 22:12:51.374235 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3153 22:12:51.380539 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3154 22:12:51.384088 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3155 22:12:51.387281 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3156 22:12:51.394453 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3157 22:12:51.397684 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3158 22:12:51.401138 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3159 22:12:51.407994 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3160 22:12:51.410974 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3161 22:12:51.414019 Total UI for P1: 0, mck2ui 16
3162 22:12:51.417537 best dqsien dly found for B0: ( 1, 3, 24)
3163 22:12:51.420888 Total UI for P1: 0, mck2ui 16
3164 22:12:51.424400 best dqsien dly found for B1: ( 1, 3, 24)
3165 22:12:51.427294 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3166 22:12:51.431295 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3167 22:12:51.431376
3168 22:12:51.434684 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3169 22:12:51.437765 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3170 22:12:51.441015 [Gating] SW calibration Done
3171 22:12:51.441097 ==
3172 22:12:51.444540 Dram Type= 6, Freq= 0, CH_1, rank 0
3173 22:12:51.447936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3174 22:12:51.448048 ==
3175 22:12:51.450773 RX Vref Scan: 0
3176 22:12:51.450857
3177 22:12:51.454121 RX Vref 0 -> 0, step: 1
3178 22:12:51.454203
3179 22:12:51.454266 RX Delay -40 -> 252, step: 8
3180 22:12:51.461002 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3181 22:12:51.464661 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3182 22:12:51.467823 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3183 22:12:51.471154 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3184 22:12:51.474620 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3185 22:12:51.481288 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3186 22:12:51.484357 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3187 22:12:51.487934 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3188 22:12:51.490968 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3189 22:12:51.494529 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3190 22:12:51.497693 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3191 22:12:51.504518 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3192 22:12:51.508423 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3193 22:12:51.511569 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3194 22:12:51.514642 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3195 22:12:51.521180 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3196 22:12:51.521310 ==
3197 22:12:51.524961 Dram Type= 6, Freq= 0, CH_1, rank 0
3198 22:12:51.527828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3199 22:12:51.527912 ==
3200 22:12:51.527978 DQS Delay:
3201 22:12:51.531209 DQS0 = 0, DQS1 = 0
3202 22:12:51.531292 DQM Delay:
3203 22:12:51.534597 DQM0 = 119, DQM1 = 116
3204 22:12:51.534681 DQ Delay:
3205 22:12:51.538090 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3206 22:12:51.541768 DQ4 =119, DQ5 =127, DQ6 =127, DQ7 =119
3207 22:12:51.544958 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3208 22:12:51.548410 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3209 22:12:51.548495
3210 22:12:51.548560
3211 22:12:51.548621 ==
3212 22:12:51.551747 Dram Type= 6, Freq= 0, CH_1, rank 0
3213 22:12:51.558070 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3214 22:12:51.558155 ==
3215 22:12:51.558221
3216 22:12:51.558282
3217 22:12:51.558340 TX Vref Scan disable
3218 22:12:51.561536 == TX Byte 0 ==
3219 22:12:51.565486 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3220 22:12:51.568374 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3221 22:12:51.572095 == TX Byte 1 ==
3222 22:12:51.575143 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3223 22:12:51.578372 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3224 22:12:51.582087 ==
3225 22:12:51.585172 Dram Type= 6, Freq= 0, CH_1, rank 0
3226 22:12:51.588338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3227 22:12:51.588422 ==
3228 22:12:51.599296 TX Vref=22, minBit 1, minWin=24, winSum=410
3229 22:12:51.602761 TX Vref=24, minBit 9, minWin=25, winSum=416
3230 22:12:51.605962 TX Vref=26, minBit 0, minWin=25, winSum=424
3231 22:12:51.609208 TX Vref=28, minBit 1, minWin=26, winSum=425
3232 22:12:51.612731 TX Vref=30, minBit 1, minWin=26, winSum=428
3233 22:12:51.615817 TX Vref=32, minBit 1, minWin=26, winSum=429
3234 22:12:51.622616 [TxChooseVref] Worse bit 1, Min win 26, Win sum 429, Final Vref 32
3235 22:12:51.622711
3236 22:12:51.625968 Final TX Range 1 Vref 32
3237 22:12:51.626053
3238 22:12:51.626118 ==
3239 22:12:51.629686 Dram Type= 6, Freq= 0, CH_1, rank 0
3240 22:12:51.632633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3241 22:12:51.632716 ==
3242 22:12:51.632781
3243 22:12:51.636281
3244 22:12:51.636363 TX Vref Scan disable
3245 22:12:51.639420 == TX Byte 0 ==
3246 22:12:51.642972 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3247 22:12:51.646159 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3248 22:12:51.649827 == TX Byte 1 ==
3249 22:12:51.652536 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3250 22:12:51.656148 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3251 22:12:51.656261
3252 22:12:51.659606 [DATLAT]
3253 22:12:51.659689 Freq=1200, CH1 RK0
3254 22:12:51.659754
3255 22:12:51.663105 DATLAT Default: 0xd
3256 22:12:51.663188 0, 0xFFFF, sum = 0
3257 22:12:51.666068 1, 0xFFFF, sum = 0
3258 22:12:51.666152 2, 0xFFFF, sum = 0
3259 22:12:51.669449 3, 0xFFFF, sum = 0
3260 22:12:51.669573 4, 0xFFFF, sum = 0
3261 22:12:51.673051 5, 0xFFFF, sum = 0
3262 22:12:51.673134 6, 0xFFFF, sum = 0
3263 22:12:51.675923 7, 0xFFFF, sum = 0
3264 22:12:51.676006 8, 0xFFFF, sum = 0
3265 22:12:51.679689 9, 0xFFFF, sum = 0
3266 22:12:51.682633 10, 0xFFFF, sum = 0
3267 22:12:51.682718 11, 0xFFFF, sum = 0
3268 22:12:51.686095 12, 0x0, sum = 1
3269 22:12:51.686189 13, 0x0, sum = 2
3270 22:12:51.686287 14, 0x0, sum = 3
3271 22:12:51.689268 15, 0x0, sum = 4
3272 22:12:51.689352 best_step = 13
3273 22:12:51.689418
3274 22:12:51.689478 ==
3275 22:12:51.692929 Dram Type= 6, Freq= 0, CH_1, rank 0
3276 22:12:51.699681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3277 22:12:51.699768 ==
3278 22:12:51.699834 RX Vref Scan: 1
3279 22:12:51.699895
3280 22:12:51.703276 Set Vref Range= 32 -> 127
3281 22:12:51.703358
3282 22:12:51.706615 RX Vref 32 -> 127, step: 1
3283 22:12:51.706698
3284 22:12:51.706767 RX Delay -5 -> 252, step: 4
3285 22:12:51.710120
3286 22:12:51.710203 Set Vref, RX VrefLevel [Byte0]: 32
3287 22:12:51.713094 [Byte1]: 32
3288 22:12:51.717413
3289 22:12:51.717524 Set Vref, RX VrefLevel [Byte0]: 33
3290 22:12:51.721067 [Byte1]: 33
3291 22:12:51.725403
3292 22:12:51.725490 Set Vref, RX VrefLevel [Byte0]: 34
3293 22:12:51.728934 [Byte1]: 34
3294 22:12:51.733286
3295 22:12:51.733375 Set Vref, RX VrefLevel [Byte0]: 35
3296 22:12:51.737066 [Byte1]: 35
3297 22:12:51.740965
3298 22:12:51.741049 Set Vref, RX VrefLevel [Byte0]: 36
3299 22:12:51.744620 [Byte1]: 36
3300 22:12:51.749110
3301 22:12:51.749220 Set Vref, RX VrefLevel [Byte0]: 37
3302 22:12:51.752662 [Byte1]: 37
3303 22:12:51.756726
3304 22:12:51.756810 Set Vref, RX VrefLevel [Byte0]: 38
3305 22:12:51.760078 [Byte1]: 38
3306 22:12:51.764622
3307 22:12:51.764707 Set Vref, RX VrefLevel [Byte0]: 39
3308 22:12:51.767780 [Byte1]: 39
3309 22:12:51.772671
3310 22:12:51.772756 Set Vref, RX VrefLevel [Byte0]: 40
3311 22:12:51.775645 [Byte1]: 40
3312 22:12:51.780468
3313 22:12:51.780552 Set Vref, RX VrefLevel [Byte0]: 41
3314 22:12:51.783501 [Byte1]: 41
3315 22:12:51.788291
3316 22:12:51.788376 Set Vref, RX VrefLevel [Byte0]: 42
3317 22:12:51.791652 [Byte1]: 42
3318 22:12:51.796163
3319 22:12:51.796247 Set Vref, RX VrefLevel [Byte0]: 43
3320 22:12:51.799146 [Byte1]: 43
3321 22:12:51.804051
3322 22:12:51.804132 Set Vref, RX VrefLevel [Byte0]: 44
3323 22:12:51.806945 [Byte1]: 44
3324 22:12:51.811694
3325 22:12:51.814782 Set Vref, RX VrefLevel [Byte0]: 45
3326 22:12:51.818053 [Byte1]: 45
3327 22:12:51.818134
3328 22:12:51.821578 Set Vref, RX VrefLevel [Byte0]: 46
3329 22:12:51.825263 [Byte1]: 46
3330 22:12:51.825365
3331 22:12:51.828267 Set Vref, RX VrefLevel [Byte0]: 47
3332 22:12:51.831278 [Byte1]: 47
3333 22:12:51.835492
3334 22:12:51.835565 Set Vref, RX VrefLevel [Byte0]: 48
3335 22:12:51.838636 [Byte1]: 48
3336 22:12:51.843030
3337 22:12:51.843114 Set Vref, RX VrefLevel [Byte0]: 49
3338 22:12:51.846308 [Byte1]: 49
3339 22:12:51.851083
3340 22:12:51.851169 Set Vref, RX VrefLevel [Byte0]: 50
3341 22:12:51.854475 [Byte1]: 50
3342 22:12:51.859269
3343 22:12:51.859361 Set Vref, RX VrefLevel [Byte0]: 51
3344 22:12:51.862218 [Byte1]: 51
3345 22:12:51.866736
3346 22:12:51.866814 Set Vref, RX VrefLevel [Byte0]: 52
3347 22:12:51.869850 [Byte1]: 52
3348 22:12:51.874455
3349 22:12:51.874539 Set Vref, RX VrefLevel [Byte0]: 53
3350 22:12:51.877771 [Byte1]: 53
3351 22:12:51.882262
3352 22:12:51.882350 Set Vref, RX VrefLevel [Byte0]: 54
3353 22:12:51.885907 [Byte1]: 54
3354 22:12:51.890139
3355 22:12:51.890231 Set Vref, RX VrefLevel [Byte0]: 55
3356 22:12:51.893774 [Byte1]: 55
3357 22:12:51.898375
3358 22:12:51.898463 Set Vref, RX VrefLevel [Byte0]: 56
3359 22:12:51.901439 [Byte1]: 56
3360 22:12:51.905737
3361 22:12:51.905825 Set Vref, RX VrefLevel [Byte0]: 57
3362 22:12:51.909606 [Byte1]: 57
3363 22:12:51.913832
3364 22:12:51.913924 Set Vref, RX VrefLevel [Byte0]: 58
3365 22:12:51.917385 [Byte1]: 58
3366 22:12:51.921664
3367 22:12:51.921751 Set Vref, RX VrefLevel [Byte0]: 59
3368 22:12:51.925247 [Byte1]: 59
3369 22:12:51.929571
3370 22:12:51.929659 Set Vref, RX VrefLevel [Byte0]: 60
3371 22:12:51.932858 [Byte1]: 60
3372 22:12:51.937835
3373 22:12:51.937924 Set Vref, RX VrefLevel [Byte0]: 61
3374 22:12:51.940809 [Byte1]: 61
3375 22:12:51.945139
3376 22:12:51.945225 Set Vref, RX VrefLevel [Byte0]: 62
3377 22:12:51.948341 [Byte1]: 62
3378 22:12:51.952968
3379 22:12:51.953054 Set Vref, RX VrefLevel [Byte0]: 63
3380 22:12:51.956429 [Byte1]: 63
3381 22:12:51.961051
3382 22:12:51.961136 Set Vref, RX VrefLevel [Byte0]: 64
3383 22:12:51.964380 [Byte1]: 64
3384 22:12:51.968734
3385 22:12:51.968820 Set Vref, RX VrefLevel [Byte0]: 65
3386 22:12:51.972003 [Byte1]: 65
3387 22:12:51.976810
3388 22:12:51.976901 Set Vref, RX VrefLevel [Byte0]: 66
3389 22:12:51.979711 [Byte1]: 66
3390 22:12:51.984370
3391 22:12:51.984456 Set Vref, RX VrefLevel [Byte0]: 67
3392 22:12:51.987722 [Byte1]: 67
3393 22:12:51.992140
3394 22:12:51.992226 Set Vref, RX VrefLevel [Byte0]: 68
3395 22:12:51.995376 [Byte1]: 68
3396 22:12:52.000189
3397 22:12:52.000277 Final RX Vref Byte 0 = 54 to rank0
3398 22:12:52.003649 Final RX Vref Byte 1 = 45 to rank0
3399 22:12:52.006675 Final RX Vref Byte 0 = 54 to rank1
3400 22:12:52.010422 Final RX Vref Byte 1 = 45 to rank1==
3401 22:12:52.013378 Dram Type= 6, Freq= 0, CH_1, rank 0
3402 22:12:52.019916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3403 22:12:52.020009 ==
3404 22:12:52.020095 DQS Delay:
3405 22:12:52.020176 DQS0 = 0, DQS1 = 0
3406 22:12:52.023609 DQM Delay:
3407 22:12:52.023696 DQM0 = 120, DQM1 = 115
3408 22:12:52.027092 DQ Delay:
3409 22:12:52.030163 DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =116
3410 22:12:52.033870 DQ4 =120, DQ5 =128, DQ6 =128, DQ7 =120
3411 22:12:52.036937 DQ8 =102, DQ9 =106, DQ10 =116, DQ11 =108
3412 22:12:52.039912 DQ12 =122, DQ13 =120, DQ14 =124, DQ15 =126
3413 22:12:52.039996
3414 22:12:52.040062
3415 22:12:52.046640 [DQSOSCAuto] RK0, (LSB)MR18= 0x113, (MSB)MR19= 0x404, tDQSOscB0 = 402 ps tDQSOscB1 = 409 ps
3416 22:12:52.050543 CH1 RK0: MR19=404, MR18=113
3417 22:12:52.057002 CH1_RK0: MR19=0x404, MR18=0x113, DQSOSC=402, MR23=63, INC=40, DEC=27
3418 22:12:52.057089
3419 22:12:52.059954 ----->DramcWriteLeveling(PI) begin...
3420 22:12:52.060040 ==
3421 22:12:52.063375 Dram Type= 6, Freq= 0, CH_1, rank 1
3422 22:12:52.066799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3423 22:12:52.066885 ==
3424 22:12:52.070212 Write leveling (Byte 0): 26 => 26
3425 22:12:52.073451 Write leveling (Byte 1): 29 => 29
3426 22:12:52.076922 DramcWriteLeveling(PI) end<-----
3427 22:12:52.077007
3428 22:12:52.077073 ==
3429 22:12:52.080538 Dram Type= 6, Freq= 0, CH_1, rank 1
3430 22:12:52.086959 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3431 22:12:52.087044 ==
3432 22:12:52.087111 [Gating] SW mode calibration
3433 22:12:52.097146 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3434 22:12:52.100064 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3435 22:12:52.103711 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3436 22:12:52.110010 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3437 22:12:52.113820 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3438 22:12:52.116831 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3439 22:12:52.123581 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3440 22:12:52.127188 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
3441 22:12:52.130263 0 15 24 | B1->B0 | 2c2c 3434 | 0 1 | (1 0) (1 0)
3442 22:12:52.137640 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
3443 22:12:52.140761 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3444 22:12:52.143760 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3445 22:12:52.147421 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3446 22:12:52.154114 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3447 22:12:52.157293 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3448 22:12:52.160508 1 0 20 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
3449 22:12:52.167423 1 0 24 | B1->B0 | 4545 3131 | 0 0 | (0 0) (0 0)
3450 22:12:52.170374 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3451 22:12:52.173810 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3452 22:12:52.180573 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3453 22:12:52.184045 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3454 22:12:52.187016 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3455 22:12:52.193889 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3456 22:12:52.197251 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3457 22:12:52.200578 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3458 22:12:52.207019 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3459 22:12:52.210665 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3460 22:12:52.213721 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3461 22:12:52.220228 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3462 22:12:52.223730 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3463 22:12:52.227036 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3464 22:12:52.233445 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3465 22:12:52.237208 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3466 22:12:52.240078 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3467 22:12:52.246854 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3468 22:12:52.250339 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3469 22:12:52.253375 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3470 22:12:52.260250 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3471 22:12:52.263361 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3472 22:12:52.266919 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3473 22:12:52.273278 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3474 22:12:52.276623 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3475 22:12:52.280194 Total UI for P1: 0, mck2ui 16
3476 22:12:52.283724 best dqsien dly found for B1: ( 1, 3, 24)
3477 22:12:52.286958 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3478 22:12:52.290037 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3479 22:12:52.292988 Total UI for P1: 0, mck2ui 16
3480 22:12:52.296375 best dqsien dly found for B0: ( 1, 3, 28)
3481 22:12:52.299935 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3482 22:12:52.306767 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3483 22:12:52.306868
3484 22:12:52.309835 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3485 22:12:52.313418 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3486 22:12:52.316421 [Gating] SW calibration Done
3487 22:12:52.316525 ==
3488 22:12:52.319976 Dram Type= 6, Freq= 0, CH_1, rank 1
3489 22:12:52.322935 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3490 22:12:52.323027 ==
3491 22:12:52.323093 RX Vref Scan: 0
3492 22:12:52.326651
3493 22:12:52.326756 RX Vref 0 -> 0, step: 1
3494 22:12:52.326846
3495 22:12:52.329594 RX Delay -40 -> 252, step: 8
3496 22:12:52.333104 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3497 22:12:52.336213 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
3498 22:12:52.343014 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3499 22:12:52.346704 iDelay=200, Bit 3, Center 119 (56 ~ 183) 128
3500 22:12:52.349624 iDelay=200, Bit 4, Center 119 (56 ~ 183) 128
3501 22:12:52.353256 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3502 22:12:52.356247 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3503 22:12:52.363072 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3504 22:12:52.366259 iDelay=200, Bit 8, Center 107 (40 ~ 175) 136
3505 22:12:52.369266 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3506 22:12:52.373081 iDelay=200, Bit 10, Center 119 (56 ~ 183) 128
3507 22:12:52.379866 iDelay=200, Bit 11, Center 115 (48 ~ 183) 136
3508 22:12:52.382493 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3509 22:12:52.386391 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
3510 22:12:52.389255 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3511 22:12:52.392585 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
3512 22:12:52.396254 ==
3513 22:12:52.396345 Dram Type= 6, Freq= 0, CH_1, rank 1
3514 22:12:52.402491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3515 22:12:52.402592 ==
3516 22:12:52.402662 DQS Delay:
3517 22:12:52.405912 DQS0 = 0, DQS1 = 0
3518 22:12:52.405987 DQM Delay:
3519 22:12:52.409387 DQM0 = 121, DQM1 = 118
3520 22:12:52.409493 DQ Delay:
3521 22:12:52.412733 DQ0 =123, DQ1 =119, DQ2 =107, DQ3 =119
3522 22:12:52.415979 DQ4 =119, DQ5 =131, DQ6 =131, DQ7 =123
3523 22:12:52.419586 DQ8 =107, DQ9 =107, DQ10 =119, DQ11 =115
3524 22:12:52.422585 DQ12 =127, DQ13 =123, DQ14 =123, DQ15 =127
3525 22:12:52.422679
3526 22:12:52.422747
3527 22:12:52.422807 ==
3528 22:12:52.426016 Dram Type= 6, Freq= 0, CH_1, rank 1
3529 22:12:52.432662 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3530 22:12:52.432802 ==
3531 22:12:52.432905
3532 22:12:52.433016
3533 22:12:52.433117 TX Vref Scan disable
3534 22:12:52.435731 == TX Byte 0 ==
3535 22:12:52.439607 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3536 22:12:52.445624 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3537 22:12:52.445718 == TX Byte 1 ==
3538 22:12:52.449309 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3539 22:12:52.455971 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3540 22:12:52.456070 ==
3541 22:12:52.459093 Dram Type= 6, Freq= 0, CH_1, rank 1
3542 22:12:52.462816 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3543 22:12:52.462899 ==
3544 22:12:52.474014 TX Vref=22, minBit 9, minWin=25, winSum=423
3545 22:12:52.477085 TX Vref=24, minBit 10, minWin=25, winSum=426
3546 22:12:52.480841 TX Vref=26, minBit 1, minWin=26, winSum=429
3547 22:12:52.483888 TX Vref=28, minBit 9, minWin=26, winSum=435
3548 22:12:52.487048 TX Vref=30, minBit 9, minWin=26, winSum=434
3549 22:12:52.493976 TX Vref=32, minBit 9, minWin=26, winSum=434
3550 22:12:52.497174 [TxChooseVref] Worse bit 9, Min win 26, Win sum 435, Final Vref 28
3551 22:12:52.497264
3552 22:12:52.500593 Final TX Range 1 Vref 28
3553 22:12:52.500682
3554 22:12:52.500782 ==
3555 22:12:52.503675 Dram Type= 6, Freq= 0, CH_1, rank 1
3556 22:12:52.507253 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3557 22:12:52.507367 ==
3558 22:12:52.510485
3559 22:12:52.510570
3560 22:12:52.510634 TX Vref Scan disable
3561 22:12:52.513347 == TX Byte 0 ==
3562 22:12:52.516923 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3563 22:12:52.523409 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3564 22:12:52.523521 == TX Byte 1 ==
3565 22:12:52.526826 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3566 22:12:52.533699 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3567 22:12:52.533788
3568 22:12:52.533853 [DATLAT]
3569 22:12:52.533913 Freq=1200, CH1 RK1
3570 22:12:52.533972
3571 22:12:52.537100 DATLAT Default: 0xd
3572 22:12:52.537174 0, 0xFFFF, sum = 0
3573 22:12:52.540536 1, 0xFFFF, sum = 0
3574 22:12:52.540609 2, 0xFFFF, sum = 0
3575 22:12:52.543660 3, 0xFFFF, sum = 0
3576 22:12:52.546643 4, 0xFFFF, sum = 0
3577 22:12:52.546728 5, 0xFFFF, sum = 0
3578 22:12:52.550111 6, 0xFFFF, sum = 0
3579 22:12:52.550196 7, 0xFFFF, sum = 0
3580 22:12:52.553156 8, 0xFFFF, sum = 0
3581 22:12:52.553239 9, 0xFFFF, sum = 0
3582 22:12:52.556711 10, 0xFFFF, sum = 0
3583 22:12:52.556795 11, 0xFFFF, sum = 0
3584 22:12:52.559880 12, 0x0, sum = 1
3585 22:12:52.559964 13, 0x0, sum = 2
3586 22:12:52.563439 14, 0x0, sum = 3
3587 22:12:52.563523 15, 0x0, sum = 4
3588 22:12:52.563590 best_step = 13
3589 22:12:52.563649
3590 22:12:52.567334 ==
3591 22:12:52.570427 Dram Type= 6, Freq= 0, CH_1, rank 1
3592 22:12:52.573869 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3593 22:12:52.573955 ==
3594 22:12:52.574021 RX Vref Scan: 0
3595 22:12:52.574081
3596 22:12:52.577172 RX Vref 0 -> 0, step: 1
3597 22:12:52.577256
3598 22:12:52.579977 RX Delay -5 -> 252, step: 4
3599 22:12:52.583690 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3600 22:12:52.590237 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3601 22:12:52.593295 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3602 22:12:52.596910 iDelay=195, Bit 3, Center 114 (55 ~ 174) 120
3603 22:12:52.599886 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3604 22:12:52.603583 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3605 22:12:52.606646 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3606 22:12:52.613630 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3607 22:12:52.616453 iDelay=195, Bit 8, Center 104 (43 ~ 166) 124
3608 22:12:52.620241 iDelay=195, Bit 9, Center 106 (47 ~ 166) 120
3609 22:12:52.623400 iDelay=195, Bit 10, Center 116 (55 ~ 178) 124
3610 22:12:52.629812 iDelay=195, Bit 11, Center 110 (51 ~ 170) 120
3611 22:12:52.633501 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3612 22:12:52.636255 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3613 22:12:52.640021 iDelay=195, Bit 14, Center 120 (63 ~ 178) 116
3614 22:12:52.643262 iDelay=195, Bit 15, Center 124 (63 ~ 186) 124
3615 22:12:52.646605 ==
3616 22:12:52.649646 Dram Type= 6, Freq= 0, CH_1, rank 1
3617 22:12:52.653142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3618 22:12:52.653226 ==
3619 22:12:52.653292 DQS Delay:
3620 22:12:52.656301 DQS0 = 0, DQS1 = 0
3621 22:12:52.656383 DQM Delay:
3622 22:12:52.659985 DQM0 = 119, DQM1 = 116
3623 22:12:52.660068 DQ Delay:
3624 22:12:52.662849 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =114
3625 22:12:52.666467 DQ4 =116, DQ5 =130, DQ6 =130, DQ7 =120
3626 22:12:52.669446 DQ8 =104, DQ9 =106, DQ10 =116, DQ11 =110
3627 22:12:52.672720 DQ12 =126, DQ13 =124, DQ14 =120, DQ15 =124
3628 22:12:52.672803
3629 22:12:52.672868
3630 22:12:52.683073 [DQSOSCAuto] RK1, (LSB)MR18= 0x10ed, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 403 ps
3631 22:12:52.686281 CH1 RK1: MR19=403, MR18=10ED
3632 22:12:52.689894 CH1_RK1: MR19=0x403, MR18=0x10ED, DQSOSC=403, MR23=63, INC=40, DEC=26
3633 22:12:52.692799 [RxdqsGatingPostProcess] freq 1200
3634 22:12:52.699388 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3635 22:12:52.703249 best DQS0 dly(2T, 0.5T) = (0, 11)
3636 22:12:52.706264 best DQS1 dly(2T, 0.5T) = (0, 11)
3637 22:12:52.709500 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3638 22:12:52.712920 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3639 22:12:52.716572 best DQS0 dly(2T, 0.5T) = (0, 11)
3640 22:12:52.719500 best DQS1 dly(2T, 0.5T) = (0, 11)
3641 22:12:52.722979 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3642 22:12:52.726025 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3643 22:12:52.726114 Pre-setting of DQS Precalculation
3644 22:12:52.733137 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3645 22:12:52.739749 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3646 22:12:52.746211 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3647 22:12:52.746308
3648 22:12:52.746373
3649 22:12:52.749710 [Calibration Summary] 2400 Mbps
3650 22:12:52.752900 CH 0, Rank 0
3651 22:12:52.752985 SW Impedance : PASS
3652 22:12:52.756324 DUTY Scan : NO K
3653 22:12:52.759650 ZQ Calibration : PASS
3654 22:12:52.759734 Jitter Meter : NO K
3655 22:12:52.762844 CBT Training : PASS
3656 22:12:52.765872 Write leveling : PASS
3657 22:12:52.765955 RX DQS gating : PASS
3658 22:12:52.769452 RX DQ/DQS(RDDQC) : PASS
3659 22:12:52.769575 TX DQ/DQS : PASS
3660 22:12:52.773255 RX DATLAT : PASS
3661 22:12:52.776126 RX DQ/DQS(Engine): PASS
3662 22:12:52.776209 TX OE : NO K
3663 22:12:52.779580 All Pass.
3664 22:12:52.779662
3665 22:12:52.779728 CH 0, Rank 1
3666 22:12:52.782549 SW Impedance : PASS
3667 22:12:52.782632 DUTY Scan : NO K
3668 22:12:52.786260 ZQ Calibration : PASS
3669 22:12:52.789248 Jitter Meter : NO K
3670 22:12:52.789331 CBT Training : PASS
3671 22:12:52.793070 Write leveling : PASS
3672 22:12:52.796054 RX DQS gating : PASS
3673 22:12:52.796142 RX DQ/DQS(RDDQC) : PASS
3674 22:12:52.799414 TX DQ/DQS : PASS
3675 22:12:52.802533 RX DATLAT : PASS
3676 22:12:52.802617 RX DQ/DQS(Engine): PASS
3677 22:12:52.806282 TX OE : NO K
3678 22:12:52.806365 All Pass.
3679 22:12:52.806429
3680 22:12:52.809384 CH 1, Rank 0
3681 22:12:52.809492 SW Impedance : PASS
3682 22:12:52.812877 DUTY Scan : NO K
3683 22:12:52.815957 ZQ Calibration : PASS
3684 22:12:52.816039 Jitter Meter : NO K
3685 22:12:52.819338 CBT Training : PASS
3686 22:12:52.819421 Write leveling : PASS
3687 22:12:52.822878 RX DQS gating : PASS
3688 22:12:52.825857 RX DQ/DQS(RDDQC) : PASS
3689 22:12:52.825943 TX DQ/DQS : PASS
3690 22:12:52.829194 RX DATLAT : PASS
3691 22:12:52.832751 RX DQ/DQS(Engine): PASS
3692 22:12:52.832835 TX OE : NO K
3693 22:12:52.836039 All Pass.
3694 22:12:52.836123
3695 22:12:52.836189 CH 1, Rank 1
3696 22:12:52.839206 SW Impedance : PASS
3697 22:12:52.839290 DUTY Scan : NO K
3698 22:12:52.842530 ZQ Calibration : PASS
3699 22:12:52.846063 Jitter Meter : NO K
3700 22:12:52.846149 CBT Training : PASS
3701 22:12:52.849478 Write leveling : PASS
3702 22:12:52.852438 RX DQS gating : PASS
3703 22:12:52.852520 RX DQ/DQS(RDDQC) : PASS
3704 22:12:52.856118 TX DQ/DQS : PASS
3705 22:12:52.856201 RX DATLAT : PASS
3706 22:12:52.859678 RX DQ/DQS(Engine): PASS
3707 22:12:52.862713 TX OE : NO K
3708 22:12:52.862796 All Pass.
3709 22:12:52.862861
3710 22:12:52.865919 DramC Write-DBI off
3711 22:12:52.866006 PER_BANK_REFRESH: Hybrid Mode
3712 22:12:52.869529 TX_TRACKING: ON
3713 22:12:52.879321 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3714 22:12:52.882797 [FAST_K] Save calibration result to emmc
3715 22:12:52.885899 dramc_set_vcore_voltage set vcore to 650000
3716 22:12:52.886011 Read voltage for 600, 5
3717 22:12:52.889176 Vio18 = 0
3718 22:12:52.889283 Vcore = 650000
3719 22:12:52.889375 Vdram = 0
3720 22:12:52.892730 Vddq = 0
3721 22:12:52.892812 Vmddr = 0
3722 22:12:52.895898 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3723 22:12:52.902818 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3724 22:12:52.905942 MEM_TYPE=3, freq_sel=19
3725 22:12:52.909660 sv_algorithm_assistance_LP4_1600
3726 22:12:52.912432 ============ PULL DRAM RESETB DOWN ============
3727 22:12:52.915975 ========== PULL DRAM RESETB DOWN end =========
3728 22:12:52.922692 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3729 22:12:52.926291 ===================================
3730 22:12:52.926376 LPDDR4 DRAM CONFIGURATION
3731 22:12:52.930030 ===================================
3732 22:12:52.932835 EX_ROW_EN[0] = 0x0
3733 22:12:52.932934 EX_ROW_EN[1] = 0x0
3734 22:12:52.936241 LP4Y_EN = 0x0
3735 22:12:52.936324 WORK_FSP = 0x0
3736 22:12:52.939294 WL = 0x2
3737 22:12:52.939399 RL = 0x2
3738 22:12:52.942721 BL = 0x2
3739 22:12:52.946218 RPST = 0x0
3740 22:12:52.946300 RD_PRE = 0x0
3741 22:12:52.949694 WR_PRE = 0x1
3742 22:12:52.949777 WR_PST = 0x0
3743 22:12:52.952698 DBI_WR = 0x0
3744 22:12:52.952785 DBI_RD = 0x0
3745 22:12:52.956145 OTF = 0x1
3746 22:12:52.959185 ===================================
3747 22:12:52.962869 ===================================
3748 22:12:52.962952 ANA top config
3749 22:12:52.965781 ===================================
3750 22:12:52.969258 DLL_ASYNC_EN = 0
3751 22:12:52.972858 ALL_SLAVE_EN = 1
3752 22:12:52.972939 NEW_RANK_MODE = 1
3753 22:12:52.976120 DLL_IDLE_MODE = 1
3754 22:12:52.979013 LP45_APHY_COMB_EN = 1
3755 22:12:52.982947 TX_ODT_DIS = 1
3756 22:12:52.983023 NEW_8X_MODE = 1
3757 22:12:52.985813 ===================================
3758 22:12:52.989003 ===================================
3759 22:12:52.992672 data_rate = 1200
3760 22:12:52.995744 CKR = 1
3761 22:12:52.999383 DQ_P2S_RATIO = 8
3762 22:12:53.002464 ===================================
3763 22:12:53.005951 CA_P2S_RATIO = 8
3764 22:12:53.009024 DQ_CA_OPEN = 0
3765 22:12:53.009106 DQ_SEMI_OPEN = 0
3766 22:12:53.012884 CA_SEMI_OPEN = 0
3767 22:12:53.015824 CA_FULL_RATE = 0
3768 22:12:53.019277 DQ_CKDIV4_EN = 1
3769 22:12:53.022409 CA_CKDIV4_EN = 1
3770 22:12:53.025422 CA_PREDIV_EN = 0
3771 22:12:53.025565 PH8_DLY = 0
3772 22:12:53.029083 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3773 22:12:53.032543 DQ_AAMCK_DIV = 4
3774 22:12:53.036130 CA_AAMCK_DIV = 4
3775 22:12:53.039148 CA_ADMCK_DIV = 4
3776 22:12:53.042092 DQ_TRACK_CA_EN = 0
3777 22:12:53.045645 CA_PICK = 600
3778 22:12:53.045727 CA_MCKIO = 600
3779 22:12:53.049147 MCKIO_SEMI = 0
3780 22:12:53.052044 PLL_FREQ = 2288
3781 22:12:53.055398 DQ_UI_PI_RATIO = 32
3782 22:12:53.058746 CA_UI_PI_RATIO = 0
3783 22:12:53.062210 ===================================
3784 22:12:53.065696 ===================================
3785 22:12:53.068678 memory_type:LPDDR4
3786 22:12:53.068759 GP_NUM : 10
3787 22:12:53.071777 SRAM_EN : 1
3788 22:12:53.071858 MD32_EN : 0
3789 22:12:53.075786 ===================================
3790 22:12:53.078770 [ANA_INIT] >>>>>>>>>>>>>>
3791 22:12:53.081937 <<<<<< [CONFIGURE PHASE]: ANA_TX
3792 22:12:53.085317 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3793 22:12:53.088898 ===================================
3794 22:12:53.092006 data_rate = 1200,PCW = 0X5800
3795 22:12:53.095635 ===================================
3796 22:12:53.099253 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3797 22:12:53.102369 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3798 22:12:53.109105 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3799 22:12:53.112145 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3800 22:12:53.115872 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3801 22:12:53.122333 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3802 22:12:53.122444 [ANA_INIT] flow start
3803 22:12:53.125391 [ANA_INIT] PLL >>>>>>>>
3804 22:12:53.125490 [ANA_INIT] PLL <<<<<<<<
3805 22:12:53.129276 [ANA_INIT] MIDPI >>>>>>>>
3806 22:12:53.132299 [ANA_INIT] MIDPI <<<<<<<<
3807 22:12:53.135856 [ANA_INIT] DLL >>>>>>>>
3808 22:12:53.135938 [ANA_INIT] flow end
3809 22:12:53.138705 ============ LP4 DIFF to SE enter ============
3810 22:12:53.145649 ============ LP4 DIFF to SE exit ============
3811 22:12:53.145732 [ANA_INIT] <<<<<<<<<<<<<
3812 22:12:53.149191 [Flow] Enable top DCM control >>>>>
3813 22:12:53.152110 [Flow] Enable top DCM control <<<<<
3814 22:12:53.155465 Enable DLL master slave shuffle
3815 22:12:53.162341 ==============================================================
3816 22:12:53.162428 Gating Mode config
3817 22:12:53.168706 ==============================================================
3818 22:12:53.172198 Config description:
3819 22:12:53.179088 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3820 22:12:53.185482 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3821 22:12:53.192422 SELPH_MODE 0: By rank 1: By Phase
3822 22:12:53.198728 ==============================================================
3823 22:12:53.198814 GAT_TRACK_EN = 1
3824 22:12:53.202121 RX_GATING_MODE = 2
3825 22:12:53.205187 RX_GATING_TRACK_MODE = 2
3826 22:12:53.208677 SELPH_MODE = 1
3827 22:12:53.212384 PICG_EARLY_EN = 1
3828 22:12:53.215379 VALID_LAT_VALUE = 1
3829 22:12:53.222205 ==============================================================
3830 22:12:53.225063 Enter into Gating configuration >>>>
3831 22:12:53.228567 Exit from Gating configuration <<<<
3832 22:12:53.232210 Enter into DVFS_PRE_config >>>>>
3833 22:12:53.241924 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3834 22:12:53.245159 Exit from DVFS_PRE_config <<<<<
3835 22:12:53.248780 Enter into PICG configuration >>>>
3836 22:12:53.252249 Exit from PICG configuration <<<<
3837 22:12:53.255144 [RX_INPUT] configuration >>>>>
3838 22:12:53.258819 [RX_INPUT] configuration <<<<<
3839 22:12:53.261533 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3840 22:12:53.268411 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3841 22:12:53.275553 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3842 22:12:53.278517 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3843 22:12:53.285061 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3844 22:12:53.291661 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3845 22:12:53.294661 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3846 22:12:53.298219 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3847 22:12:53.304633 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3848 22:12:53.308106 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3849 22:12:53.311941 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3850 22:12:53.318557 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3851 22:12:53.321750 ===================================
3852 22:12:53.321834 LPDDR4 DRAM CONFIGURATION
3853 22:12:53.324886 ===================================
3854 22:12:53.328404 EX_ROW_EN[0] = 0x0
3855 22:12:53.331482 EX_ROW_EN[1] = 0x0
3856 22:12:53.331593 LP4Y_EN = 0x0
3857 22:12:53.334869 WORK_FSP = 0x0
3858 22:12:53.334951 WL = 0x2
3859 22:12:53.337949 RL = 0x2
3860 22:12:53.338031 BL = 0x2
3861 22:12:53.341764 RPST = 0x0
3862 22:12:53.341847 RD_PRE = 0x0
3863 22:12:53.344771 WR_PRE = 0x1
3864 22:12:53.344853 WR_PST = 0x0
3865 22:12:53.348497 DBI_WR = 0x0
3866 22:12:53.348580 DBI_RD = 0x0
3867 22:12:53.351903 OTF = 0x1
3868 22:12:53.354829 ===================================
3869 22:12:53.358314 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3870 22:12:53.361309 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3871 22:12:53.368117 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3872 22:12:53.371691 ===================================
3873 22:12:53.371790 LPDDR4 DRAM CONFIGURATION
3874 22:12:53.374589 ===================================
3875 22:12:53.378097 EX_ROW_EN[0] = 0x10
3876 22:12:53.378181 EX_ROW_EN[1] = 0x0
3877 22:12:53.381558 LP4Y_EN = 0x0
3878 22:12:53.381641 WORK_FSP = 0x0
3879 22:12:53.384924 WL = 0x2
3880 22:12:53.387993 RL = 0x2
3881 22:12:53.388098 BL = 0x2
3882 22:12:53.391043 RPST = 0x0
3883 22:12:53.391125 RD_PRE = 0x0
3884 22:12:53.394681 WR_PRE = 0x1
3885 22:12:53.394763 WR_PST = 0x0
3886 22:12:53.397822 DBI_WR = 0x0
3887 22:12:53.397904 DBI_RD = 0x0
3888 22:12:53.401319 OTF = 0x1
3889 22:12:53.404368 ===================================
3890 22:12:53.410909 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3891 22:12:53.414669 nWR fixed to 30
3892 22:12:53.414753 [ModeRegInit_LP4] CH0 RK0
3893 22:12:53.417536 [ModeRegInit_LP4] CH0 RK1
3894 22:12:53.421240 [ModeRegInit_LP4] CH1 RK0
3895 22:12:53.421323 [ModeRegInit_LP4] CH1 RK1
3896 22:12:53.424346 match AC timing 17
3897 22:12:53.427589 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3898 22:12:53.434207 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3899 22:12:53.437331 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3900 22:12:53.440835 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3901 22:12:53.447748 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3902 22:12:53.447832 ==
3903 22:12:53.450872 Dram Type= 6, Freq= 0, CH_0, rank 0
3904 22:12:53.454144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3905 22:12:53.454228 ==
3906 22:12:53.460847 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3907 22:12:53.464233 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3908 22:12:53.468879 [CA 0] Center 35 (5~66) winsize 62
3909 22:12:53.472429 [CA 1] Center 36 (5~67) winsize 63
3910 22:12:53.475274 [CA 2] Center 33 (3~64) winsize 62
3911 22:12:53.478814 [CA 3] Center 33 (2~64) winsize 63
3912 22:12:53.482189 [CA 4] Center 33 (2~64) winsize 63
3913 22:12:53.485226 [CA 5] Center 32 (2~63) winsize 62
3914 22:12:53.485309
3915 22:12:53.488817 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3916 22:12:53.488899
3917 22:12:53.492309 [CATrainingPosCal] consider 1 rank data
3918 22:12:53.495787 u2DelayCellTimex100 = 270/100 ps
3919 22:12:53.498709 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3920 22:12:53.501961 CA1 delay=36 (5~67),Diff = 4 PI (38 cell)
3921 22:12:53.509106 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3922 22:12:53.512024 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
3923 22:12:53.515395 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3924 22:12:53.518582 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3925 22:12:53.518665
3926 22:12:53.522310 CA PerBit enable=1, Macro0, CA PI delay=32
3927 22:12:53.522393
3928 22:12:53.525268 [CBTSetCACLKResult] CA Dly = 32
3929 22:12:53.525351 CS Dly: 4 (0~35)
3930 22:12:53.528865 ==
3931 22:12:53.528947 Dram Type= 6, Freq= 0, CH_0, rank 1
3932 22:12:53.535624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3933 22:12:53.535708 ==
3934 22:12:53.539119 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3935 22:12:53.545189 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3936 22:12:53.549002 [CA 0] Center 35 (5~66) winsize 62
3937 22:12:53.552641 [CA 1] Center 35 (5~66) winsize 62
3938 22:12:53.555836 [CA 2] Center 34 (3~65) winsize 63
3939 22:12:53.558709 [CA 3] Center 34 (3~65) winsize 63
3940 22:12:53.562156 [CA 4] Center 33 (2~64) winsize 63
3941 22:12:53.565284 [CA 5] Center 32 (2~63) winsize 62
3942 22:12:53.565367
3943 22:12:53.568678 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3944 22:12:53.568761
3945 22:12:53.572210 [CATrainingPosCal] consider 2 rank data
3946 22:12:53.575837 u2DelayCellTimex100 = 270/100 ps
3947 22:12:53.578841 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3948 22:12:53.582282 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3949 22:12:53.588841 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3950 22:12:53.592000 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
3951 22:12:53.595329 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3952 22:12:53.598792 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3953 22:12:53.598875
3954 22:12:53.602281 CA PerBit enable=1, Macro0, CA PI delay=32
3955 22:12:53.602365
3956 22:12:53.605658 [CBTSetCACLKResult] CA Dly = 32
3957 22:12:53.605742 CS Dly: 4 (0~35)
3958 22:12:53.605808
3959 22:12:53.608469 ----->DramcWriteLeveling(PI) begin...
3960 22:12:53.612097 ==
3961 22:12:53.615103 Dram Type= 6, Freq= 0, CH_0, rank 0
3962 22:12:53.618712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3963 22:12:53.618802 ==
3964 22:12:53.621606 Write leveling (Byte 0): 35 => 35
3965 22:12:53.625317 Write leveling (Byte 1): 32 => 32
3966 22:12:53.628583 DramcWriteLeveling(PI) end<-----
3967 22:12:53.628667
3968 22:12:53.628732 ==
3969 22:12:53.632059 Dram Type= 6, Freq= 0, CH_0, rank 0
3970 22:12:53.635095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3971 22:12:53.635178 ==
3972 22:12:53.638751 [Gating] SW mode calibration
3973 22:12:53.645325 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3974 22:12:53.648493 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3975 22:12:53.655278 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3976 22:12:53.658877 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3977 22:12:53.662017 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3978 22:12:53.668155 0 9 12 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
3979 22:12:53.672071 0 9 16 | B1->B0 | 3131 2323 | 0 0 | (0 0) (0 0)
3980 22:12:53.675363 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3981 22:12:53.681648 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3982 22:12:53.685120 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3983 22:12:53.688410 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3984 22:12:53.694954 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3985 22:12:53.698571 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3986 22:12:53.701743 0 10 12 | B1->B0 | 2323 3232 | 0 1 | (0 0) (0 0)
3987 22:12:53.708559 0 10 16 | B1->B0 | 3736 4646 | 1 0 | (0 0) (0 0)
3988 22:12:53.711321 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3989 22:12:53.714699 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3990 22:12:53.721251 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3991 22:12:53.725028 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3992 22:12:53.727827 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3993 22:12:53.734560 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3994 22:12:53.738245 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3995 22:12:53.741137 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3996 22:12:53.748321 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3997 22:12:53.751329 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3998 22:12:53.754983 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3999 22:12:53.761212 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4000 22:12:53.764347 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4001 22:12:53.768020 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4002 22:12:53.774253 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 22:12:53.777694 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 22:12:53.781448 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 22:12:53.788369 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 22:12:53.791346 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 22:12:53.794741 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 22:12:53.801179 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 22:12:53.804926 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4010 22:12:53.808041 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4011 22:12:53.811070 Total UI for P1: 0, mck2ui 16
4012 22:12:53.814518 best dqsien dly found for B0: ( 0, 13, 10)
4013 22:12:53.817976 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4014 22:12:53.824509 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4015 22:12:53.827612 Total UI for P1: 0, mck2ui 16
4016 22:12:53.831076 best dqsien dly found for B1: ( 0, 13, 16)
4017 22:12:53.834612 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4018 22:12:53.837519 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4019 22:12:53.837617
4020 22:12:53.840906 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4021 22:12:53.844491 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4022 22:12:53.847605 [Gating] SW calibration Done
4023 22:12:53.847684 ==
4024 22:12:53.851102 Dram Type= 6, Freq= 0, CH_0, rank 0
4025 22:12:53.854977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4026 22:12:53.855061 ==
4027 22:12:53.857980 RX Vref Scan: 0
4028 22:12:53.858055
4029 22:12:53.858121 RX Vref 0 -> 0, step: 1
4030 22:12:53.861272
4031 22:12:53.861344 RX Delay -230 -> 252, step: 16
4032 22:12:53.867945 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4033 22:12:53.871120 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4034 22:12:53.874708 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4035 22:12:53.877655 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4036 22:12:53.881135 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4037 22:12:53.888246 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4038 22:12:53.891116 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4039 22:12:53.894346 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4040 22:12:53.897791 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4041 22:12:53.904564 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4042 22:12:53.907570 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4043 22:12:53.911072 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4044 22:12:53.914067 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4045 22:12:53.920696 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4046 22:12:53.924298 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4047 22:12:53.928086 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4048 22:12:53.928175 ==
4049 22:12:53.931206 Dram Type= 6, Freq= 0, CH_0, rank 0
4050 22:12:53.934660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4051 22:12:53.934744 ==
4052 22:12:53.937775 DQS Delay:
4053 22:12:53.937856 DQS0 = 0, DQS1 = 0
4054 22:12:53.941043 DQM Delay:
4055 22:12:53.941126 DQM0 = 51, DQM1 = 45
4056 22:12:53.941191 DQ Delay:
4057 22:12:53.944407 DQ0 =49, DQ1 =57, DQ2 =41, DQ3 =41
4058 22:12:53.947474 DQ4 =49, DQ5 =41, DQ6 =65, DQ7 =65
4059 22:12:53.951240 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =41
4060 22:12:53.954219 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =57
4061 22:12:53.954324
4062 22:12:53.954422
4063 22:12:53.954513 ==
4064 22:12:53.957706 Dram Type= 6, Freq= 0, CH_0, rank 0
4065 22:12:53.964053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4066 22:12:53.964137 ==
4067 22:12:53.964202
4068 22:12:53.964260
4069 22:12:53.964317 TX Vref Scan disable
4070 22:12:53.968348 == TX Byte 0 ==
4071 22:12:53.971434 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4072 22:12:53.978080 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4073 22:12:53.978163 == TX Byte 1 ==
4074 22:12:53.981801 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4075 22:12:53.988150 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4076 22:12:53.988269 ==
4077 22:12:53.991462 Dram Type= 6, Freq= 0, CH_0, rank 0
4078 22:12:53.994659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4079 22:12:53.994742 ==
4080 22:12:53.994806
4081 22:12:53.994867
4082 22:12:53.998420 TX Vref Scan disable
4083 22:12:54.001403 == TX Byte 0 ==
4084 22:12:54.004893 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4085 22:12:54.008488 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4086 22:12:54.011446 == TX Byte 1 ==
4087 22:12:54.014757 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4088 22:12:54.017843 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4089 22:12:54.017926
4090 22:12:54.017991 [DATLAT]
4091 22:12:54.021468 Freq=600, CH0 RK0
4092 22:12:54.021597
4093 22:12:54.021662 DATLAT Default: 0x9
4094 22:12:54.024984 0, 0xFFFF, sum = 0
4095 22:12:54.025068 1, 0xFFFF, sum = 0
4096 22:12:54.027830 2, 0xFFFF, sum = 0
4097 22:12:54.031713 3, 0xFFFF, sum = 0
4098 22:12:54.031798 4, 0xFFFF, sum = 0
4099 22:12:54.034573 5, 0xFFFF, sum = 0
4100 22:12:54.034657 6, 0xFFFF, sum = 0
4101 22:12:54.038029 7, 0xFFFF, sum = 0
4102 22:12:54.038112 8, 0x0, sum = 1
4103 22:12:54.038180 9, 0x0, sum = 2
4104 22:12:54.041442 10, 0x0, sum = 3
4105 22:12:54.041585 11, 0x0, sum = 4
4106 22:12:54.044993 best_step = 9
4107 22:12:54.045074
4108 22:12:54.045138 ==
4109 22:12:54.048000 Dram Type= 6, Freq= 0, CH_0, rank 0
4110 22:12:54.051683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4111 22:12:54.051771 ==
4112 22:12:54.054591 RX Vref Scan: 1
4113 22:12:54.054673
4114 22:12:54.054737 RX Vref 0 -> 0, step: 1
4115 22:12:54.054797
4116 22:12:54.058061 RX Delay -163 -> 252, step: 8
4117 22:12:54.058142
4118 22:12:54.061111 Set Vref, RX VrefLevel [Byte0]: 55
4119 22:12:54.064690 [Byte1]: 53
4120 22:12:54.068944
4121 22:12:54.069026 Final RX Vref Byte 0 = 55 to rank0
4122 22:12:54.072082 Final RX Vref Byte 1 = 53 to rank0
4123 22:12:54.075212 Final RX Vref Byte 0 = 55 to rank1
4124 22:12:54.078921 Final RX Vref Byte 1 = 53 to rank1==
4125 22:12:54.082007 Dram Type= 6, Freq= 0, CH_0, rank 0
4126 22:12:54.088724 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4127 22:12:54.088810 ==
4128 22:12:54.088897 DQS Delay:
4129 22:12:54.091624 DQS0 = 0, DQS1 = 0
4130 22:12:54.091709 DQM Delay:
4131 22:12:54.091794 DQM0 = 53, DQM1 = 47
4132 22:12:54.095157 DQ Delay:
4133 22:12:54.098501 DQ0 =52, DQ1 =56, DQ2 =48, DQ3 =52
4134 22:12:54.101779 DQ4 =52, DQ5 =44, DQ6 =64, DQ7 =60
4135 22:12:54.105153 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40
4136 22:12:54.108909 DQ12 =56, DQ13 =52, DQ14 =56, DQ15 =52
4137 22:12:54.108994
4138 22:12:54.109079
4139 22:12:54.115382 [DQSOSCAuto] RK0, (LSB)MR18= 0x7568, (MSB)MR19= 0x808, tDQSOscB0 = 390 ps tDQSOscB1 = 387 ps
4140 22:12:54.118709 CH0 RK0: MR19=808, MR18=7568
4141 22:12:54.125038 CH0_RK0: MR19=0x808, MR18=0x7568, DQSOSC=387, MR23=63, INC=175, DEC=116
4142 22:12:54.125132
4143 22:12:54.128122 ----->DramcWriteLeveling(PI) begin...
4144 22:12:54.128210 ==
4145 22:12:54.131701 Dram Type= 6, Freq= 0, CH_0, rank 1
4146 22:12:54.134918 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4147 22:12:54.135005 ==
4148 22:12:54.138538 Write leveling (Byte 0): 35 => 35
4149 22:12:54.141444 Write leveling (Byte 1): 32 => 32
4150 22:12:54.145052 DramcWriteLeveling(PI) end<-----
4151 22:12:54.145137
4152 22:12:54.145238 ==
4153 22:12:54.148456 Dram Type= 6, Freq= 0, CH_0, rank 1
4154 22:12:54.151520 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4155 22:12:54.151606 ==
4156 22:12:54.155111 [Gating] SW mode calibration
4157 22:12:54.161898 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4158 22:12:54.168150 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4159 22:12:54.172030 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4160 22:12:54.178046 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4161 22:12:54.181780 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4162 22:12:54.184926 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
4163 22:12:54.191681 0 9 16 | B1->B0 | 2b2b 2c2c | 0 0 | (1 1) (1 1)
4164 22:12:54.194537 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4165 22:12:54.197822 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4166 22:12:54.201202 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4167 22:12:54.207707 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4168 22:12:54.211646 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4169 22:12:54.214389 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4170 22:12:54.221234 0 10 12 | B1->B0 | 2a2a 2b2b | 1 1 | (0 0) (0 0)
4171 22:12:54.224745 0 10 16 | B1->B0 | 3e3e 4343 | 0 0 | (0 0) (0 0)
4172 22:12:54.228013 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4173 22:12:54.234541 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4174 22:12:54.238093 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4175 22:12:54.241558 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4176 22:12:54.247948 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4177 22:12:54.251578 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4178 22:12:54.254892 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4179 22:12:54.261474 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4180 22:12:54.264438 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4181 22:12:54.268135 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4182 22:12:54.274355 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4183 22:12:54.277971 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4184 22:12:54.280788 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4185 22:12:54.287914 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4186 22:12:54.290925 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4187 22:12:54.294631 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4188 22:12:54.300838 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4189 22:12:54.304731 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4190 22:12:54.307519 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4191 22:12:54.314450 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4192 22:12:54.317724 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4193 22:12:54.321194 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4194 22:12:54.327780 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4195 22:12:54.331109 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4196 22:12:54.334085 Total UI for P1: 0, mck2ui 16
4197 22:12:54.337321 best dqsien dly found for B0: ( 0, 13, 14)
4198 22:12:54.340797 Total UI for P1: 0, mck2ui 16
4199 22:12:54.344428 best dqsien dly found for B1: ( 0, 13, 14)
4200 22:12:54.348079 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4201 22:12:54.351149 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4202 22:12:54.351235
4203 22:12:54.354257 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4204 22:12:54.358012 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4205 22:12:54.360923 [Gating] SW calibration Done
4206 22:12:54.361008 ==
4207 22:12:54.364443 Dram Type= 6, Freq= 0, CH_0, rank 1
4208 22:12:54.367375 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4209 22:12:54.367461 ==
4210 22:12:54.370599 RX Vref Scan: 0
4211 22:12:54.370683
4212 22:12:54.374172 RX Vref 0 -> 0, step: 1
4213 22:12:54.374255
4214 22:12:54.374321 RX Delay -230 -> 252, step: 16
4215 22:12:54.380656 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4216 22:12:54.384024 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4217 22:12:54.387784 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4218 22:12:54.390690 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4219 22:12:54.397587 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4220 22:12:54.400562 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4221 22:12:54.403732 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4222 22:12:54.407418 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4223 22:12:54.410409 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4224 22:12:54.417348 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4225 22:12:54.420387 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4226 22:12:54.423873 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4227 22:12:54.427462 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4228 22:12:54.433870 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4229 22:12:54.437295 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4230 22:12:54.440327 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4231 22:12:54.440411 ==
4232 22:12:54.443575 Dram Type= 6, Freq= 0, CH_0, rank 1
4233 22:12:54.447053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4234 22:12:54.450774 ==
4235 22:12:54.450858 DQS Delay:
4236 22:12:54.450924 DQS0 = 0, DQS1 = 0
4237 22:12:54.453580 DQM Delay:
4238 22:12:54.453663 DQM0 = 50, DQM1 = 42
4239 22:12:54.457254 DQ Delay:
4240 22:12:54.460244 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =41
4241 22:12:54.460370 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57
4242 22:12:54.463978 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =33
4243 22:12:54.467007 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4244 22:12:54.470494
4245 22:12:54.470577
4246 22:12:54.470643 ==
4247 22:12:54.473444 Dram Type= 6, Freq= 0, CH_0, rank 1
4248 22:12:54.477063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4249 22:12:54.477148 ==
4250 22:12:54.477214
4251 22:12:54.477274
4252 22:12:54.480672 TX Vref Scan disable
4253 22:12:54.480771 == TX Byte 0 ==
4254 22:12:54.486944 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4255 22:12:54.490223 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4256 22:12:54.490315 == TX Byte 1 ==
4257 22:12:54.497189 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4258 22:12:54.500248 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4259 22:12:54.500332 ==
4260 22:12:54.503948 Dram Type= 6, Freq= 0, CH_0, rank 1
4261 22:12:54.506996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4262 22:12:54.507080 ==
4263 22:12:54.507146
4264 22:12:54.507207
4265 22:12:54.510311 TX Vref Scan disable
4266 22:12:54.513821 == TX Byte 0 ==
4267 22:12:54.516921 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4268 22:12:54.520403 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4269 22:12:54.524039 == TX Byte 1 ==
4270 22:12:54.526604 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4271 22:12:54.530347 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4272 22:12:54.533732
4273 22:12:54.533816 [DATLAT]
4274 22:12:54.533882 Freq=600, CH0 RK1
4275 22:12:54.533943
4276 22:12:54.536869 DATLAT Default: 0x9
4277 22:12:54.536953 0, 0xFFFF, sum = 0
4278 22:12:54.540245 1, 0xFFFF, sum = 0
4279 22:12:54.540330 2, 0xFFFF, sum = 0
4280 22:12:54.543782 3, 0xFFFF, sum = 0
4281 22:12:54.543867 4, 0xFFFF, sum = 0
4282 22:12:54.546749 5, 0xFFFF, sum = 0
4283 22:12:54.550117 6, 0xFFFF, sum = 0
4284 22:12:54.550201 7, 0xFFFF, sum = 0
4285 22:12:54.550269 8, 0x0, sum = 1
4286 22:12:54.553757 9, 0x0, sum = 2
4287 22:12:54.553842 10, 0x0, sum = 3
4288 22:12:54.556505 11, 0x0, sum = 4
4289 22:12:54.556589 best_step = 9
4290 22:12:54.556654
4291 22:12:54.556714 ==
4292 22:12:54.560073 Dram Type= 6, Freq= 0, CH_0, rank 1
4293 22:12:54.566947 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4294 22:12:54.567040 ==
4295 22:12:54.567106 RX Vref Scan: 0
4296 22:12:54.567166
4297 22:12:54.569966 RX Vref 0 -> 0, step: 1
4298 22:12:54.570048
4299 22:12:54.573025 RX Delay -163 -> 252, step: 8
4300 22:12:54.576628 iDelay=197, Bit 0, Center 52 (-91 ~ 196) 288
4301 22:12:54.583162 iDelay=197, Bit 1, Center 52 (-91 ~ 196) 288
4302 22:12:54.586872 iDelay=197, Bit 2, Center 52 (-91 ~ 196) 288
4303 22:12:54.589822 iDelay=197, Bit 3, Center 48 (-99 ~ 196) 296
4304 22:12:54.593023 iDelay=197, Bit 4, Center 52 (-91 ~ 196) 288
4305 22:12:54.596575 iDelay=197, Bit 5, Center 44 (-99 ~ 188) 288
4306 22:12:54.603108 iDelay=197, Bit 6, Center 56 (-83 ~ 196) 280
4307 22:12:54.606159 iDelay=197, Bit 7, Center 60 (-75 ~ 196) 272
4308 22:12:54.609773 iDelay=197, Bit 8, Center 36 (-107 ~ 180) 288
4309 22:12:54.613010 iDelay=197, Bit 9, Center 36 (-107 ~ 180) 288
4310 22:12:54.616211 iDelay=197, Bit 10, Center 48 (-91 ~ 188) 280
4311 22:12:54.623171 iDelay=197, Bit 11, Center 40 (-99 ~ 180) 280
4312 22:12:54.626509 iDelay=197, Bit 12, Center 52 (-91 ~ 196) 288
4313 22:12:54.629824 iDelay=197, Bit 13, Center 52 (-91 ~ 196) 288
4314 22:12:54.632751 iDelay=197, Bit 14, Center 56 (-83 ~ 196) 280
4315 22:12:54.636631 iDelay=197, Bit 15, Center 52 (-91 ~ 196) 288
4316 22:12:54.639603 ==
4317 22:12:54.643074 Dram Type= 6, Freq= 0, CH_0, rank 1
4318 22:12:54.645950 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4319 22:12:54.646033 ==
4320 22:12:54.646098 DQS Delay:
4321 22:12:54.649318 DQS0 = 0, DQS1 = 0
4322 22:12:54.649445 DQM Delay:
4323 22:12:54.652829 DQM0 = 52, DQM1 = 46
4324 22:12:54.652909 DQ Delay:
4325 22:12:54.656202 DQ0 =52, DQ1 =52, DQ2 =52, DQ3 =48
4326 22:12:54.659625 DQ4 =52, DQ5 =44, DQ6 =56, DQ7 =60
4327 22:12:54.663208 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40
4328 22:12:54.666209 DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =52
4329 22:12:54.666291
4330 22:12:54.666354
4331 22:12:54.672986 [DQSOSCAuto] RK1, (LSB)MR18= 0x6626, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 390 ps
4332 22:12:54.676128 CH0 RK1: MR19=808, MR18=6626
4333 22:12:54.683152 CH0_RK1: MR19=0x808, MR18=0x6626, DQSOSC=390, MR23=63, INC=172, DEC=114
4334 22:12:54.686558 [RxdqsGatingPostProcess] freq 600
4335 22:12:54.689874 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4336 22:12:54.693011 Pre-setting of DQS Precalculation
4337 22:12:54.699810 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4338 22:12:54.699891 ==
4339 22:12:54.703297 Dram Type= 6, Freq= 0, CH_1, rank 0
4340 22:12:54.706137 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4341 22:12:54.706225 ==
4342 22:12:54.712980 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4343 22:12:54.719864 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4344 22:12:54.722951 [CA 0] Center 36 (5~67) winsize 63
4345 22:12:54.726384 [CA 1] Center 36 (6~67) winsize 62
4346 22:12:54.729878 [CA 2] Center 35 (4~66) winsize 63
4347 22:12:54.733122 [CA 3] Center 34 (4~65) winsize 62
4348 22:12:54.736147 [CA 4] Center 34 (4~65) winsize 62
4349 22:12:54.739686 [CA 5] Center 34 (3~65) winsize 63
4350 22:12:54.739770
4351 22:12:54.743208 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4352 22:12:54.743319
4353 22:12:54.746061 [CATrainingPosCal] consider 1 rank data
4354 22:12:54.749460 u2DelayCellTimex100 = 270/100 ps
4355 22:12:54.753116 CA0 delay=36 (5~67),Diff = 2 PI (19 cell)
4356 22:12:54.755897 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
4357 22:12:54.759968 CA2 delay=35 (4~66),Diff = 1 PI (9 cell)
4358 22:12:54.762618 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4359 22:12:54.766190 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4360 22:12:54.769521 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4361 22:12:54.769618
4362 22:12:54.776111 CA PerBit enable=1, Macro0, CA PI delay=34
4363 22:12:54.776200
4364 22:12:54.776265 [CBTSetCACLKResult] CA Dly = 34
4365 22:12:54.779751 CS Dly: 6 (0~37)
4366 22:12:54.779835 ==
4367 22:12:54.782784 Dram Type= 6, Freq= 0, CH_1, rank 1
4368 22:12:54.785897 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4369 22:12:54.785982 ==
4370 22:12:54.792580 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4371 22:12:54.799019 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4372 22:12:54.802760 [CA 0] Center 36 (6~67) winsize 62
4373 22:12:54.805767 [CA 1] Center 36 (6~67) winsize 62
4374 22:12:54.809694 [CA 2] Center 35 (4~66) winsize 63
4375 22:12:54.812646 [CA 3] Center 35 (4~66) winsize 63
4376 22:12:54.815715 [CA 4] Center 34 (4~65) winsize 62
4377 22:12:54.819523 [CA 5] Center 34 (4~65) winsize 62
4378 22:12:54.819607
4379 22:12:54.822555 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4380 22:12:54.822638
4381 22:12:54.825690 [CATrainingPosCal] consider 2 rank data
4382 22:12:54.829308 u2DelayCellTimex100 = 270/100 ps
4383 22:12:54.832509 CA0 delay=36 (6~67),Diff = 2 PI (19 cell)
4384 22:12:54.835972 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
4385 22:12:54.839550 CA2 delay=35 (4~66),Diff = 1 PI (9 cell)
4386 22:12:54.842557 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4387 22:12:54.845960 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4388 22:12:54.849040 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4389 22:12:54.849126
4390 22:12:54.856131 CA PerBit enable=1, Macro0, CA PI delay=34
4391 22:12:54.856219
4392 22:12:54.856285 [CBTSetCACLKResult] CA Dly = 34
4393 22:12:54.859410 CS Dly: 6 (0~37)
4394 22:12:54.859493
4395 22:12:54.862807 ----->DramcWriteLeveling(PI) begin...
4396 22:12:54.862891 ==
4397 22:12:54.866203 Dram Type= 6, Freq= 0, CH_1, rank 0
4398 22:12:54.869666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4399 22:12:54.869751 ==
4400 22:12:54.872383 Write leveling (Byte 0): 29 => 29
4401 22:12:54.875928 Write leveling (Byte 1): 29 => 29
4402 22:12:54.878850 DramcWriteLeveling(PI) end<-----
4403 22:12:54.878924
4404 22:12:54.878993 ==
4405 22:12:54.882866 Dram Type= 6, Freq= 0, CH_1, rank 0
4406 22:12:54.885848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4407 22:12:54.888961 ==
4408 22:12:54.889045 [Gating] SW mode calibration
4409 22:12:54.898995 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4410 22:12:54.902277 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4411 22:12:54.905624 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4412 22:12:54.912240 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4413 22:12:54.915745 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4414 22:12:54.918917 0 9 12 | B1->B0 | 2f2f 2d2d | 0 1 | (0 1) (1 0)
4415 22:12:54.925420 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4416 22:12:54.928808 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4417 22:12:54.931903 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4418 22:12:54.939265 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4419 22:12:54.942193 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4420 22:12:54.945500 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4421 22:12:54.952653 0 10 8 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
4422 22:12:54.955407 0 10 12 | B1->B0 | 3434 3b3b | 0 0 | (0 0) (0 0)
4423 22:12:54.958862 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4424 22:12:54.965529 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4425 22:12:54.968772 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4426 22:12:54.972514 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4427 22:12:54.978714 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4428 22:12:54.982001 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4429 22:12:54.985635 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4430 22:12:54.992367 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4431 22:12:54.995397 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4432 22:12:54.998330 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4433 22:12:55.005038 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4434 22:12:55.008615 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4435 22:12:55.011902 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4436 22:12:55.015343 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4437 22:12:55.021759 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4438 22:12:55.024859 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 22:12:55.028539 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4440 22:12:55.035380 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4441 22:12:55.038305 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4442 22:12:55.041499 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 22:12:55.048735 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4444 22:12:55.051589 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4445 22:12:55.054908 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4446 22:12:55.061817 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4447 22:12:55.061918 Total UI for P1: 0, mck2ui 16
4448 22:12:55.068584 best dqsien dly found for B1: ( 0, 13, 10)
4449 22:12:55.071451 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4450 22:12:55.074870 Total UI for P1: 0, mck2ui 16
4451 22:12:55.078191 best dqsien dly found for B0: ( 0, 13, 12)
4452 22:12:55.081672 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4453 22:12:55.084604 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4454 22:12:55.084719
4455 22:12:55.088567 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4456 22:12:55.091389 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4457 22:12:55.094918 [Gating] SW calibration Done
4458 22:12:55.095025 ==
4459 22:12:55.098163 Dram Type= 6, Freq= 0, CH_1, rank 0
4460 22:12:55.104554 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4461 22:12:55.104637 ==
4462 22:12:55.104701 RX Vref Scan: 0
4463 22:12:55.104762
4464 22:12:55.108126 RX Vref 0 -> 0, step: 1
4465 22:12:55.108226
4466 22:12:55.111214 RX Delay -230 -> 252, step: 16
4467 22:12:55.114827 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4468 22:12:55.118355 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4469 22:12:55.121760 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4470 22:12:55.128001 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4471 22:12:55.131836 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4472 22:12:55.134804 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4473 22:12:55.137997 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4474 22:12:55.141604 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4475 22:12:55.148534 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4476 22:12:55.151489 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4477 22:12:55.154824 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4478 22:12:55.158093 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4479 22:12:55.164375 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4480 22:12:55.167966 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4481 22:12:55.170932 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4482 22:12:55.174297 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4483 22:12:55.174382 ==
4484 22:12:55.177825 Dram Type= 6, Freq= 0, CH_1, rank 0
4485 22:12:55.184892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4486 22:12:55.184977 ==
4487 22:12:55.185060 DQS Delay:
4488 22:12:55.187677 DQS0 = 0, DQS1 = 0
4489 22:12:55.187761 DQM Delay:
4490 22:12:55.190951 DQM0 = 47, DQM1 = 46
4491 22:12:55.191035 DQ Delay:
4492 22:12:55.194367 DQ0 =57, DQ1 =41, DQ2 =41, DQ3 =41
4493 22:12:55.197845 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4494 22:12:55.201197 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4495 22:12:55.204258 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4496 22:12:55.204343
4497 22:12:55.204427
4498 22:12:55.204505 ==
4499 22:12:55.207311 Dram Type= 6, Freq= 0, CH_1, rank 0
4500 22:12:55.211003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4501 22:12:55.211086 ==
4502 22:12:55.211152
4503 22:12:55.211211
4504 22:12:55.214110 TX Vref Scan disable
4505 22:12:55.217538 == TX Byte 0 ==
4506 22:12:55.221108 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4507 22:12:55.224252 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4508 22:12:55.227748 == TX Byte 1 ==
4509 22:12:55.230616 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4510 22:12:55.234070 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4511 22:12:55.234153 ==
4512 22:12:55.237757 Dram Type= 6, Freq= 0, CH_1, rank 0
4513 22:12:55.240860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4514 22:12:55.244014 ==
4515 22:12:55.244096
4516 22:12:55.244162
4517 22:12:55.244221 TX Vref Scan disable
4518 22:12:55.248284 == TX Byte 0 ==
4519 22:12:55.251469 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4520 22:12:55.257681 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4521 22:12:55.257764 == TX Byte 1 ==
4522 22:12:55.261314 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4523 22:12:55.267826 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4524 22:12:55.267909
4525 22:12:55.267991 [DATLAT]
4526 22:12:55.268066 Freq=600, CH1 RK0
4527 22:12:55.268126
4528 22:12:55.271454 DATLAT Default: 0x9
4529 22:12:55.271536 0, 0xFFFF, sum = 0
4530 22:12:55.274423 1, 0xFFFF, sum = 0
4531 22:12:55.277667 2, 0xFFFF, sum = 0
4532 22:12:55.277751 3, 0xFFFF, sum = 0
4533 22:12:55.281122 4, 0xFFFF, sum = 0
4534 22:12:55.281206 5, 0xFFFF, sum = 0
4535 22:12:55.284573 6, 0xFFFF, sum = 0
4536 22:12:55.284657 7, 0xFFFF, sum = 0
4537 22:12:55.287837 8, 0x0, sum = 1
4538 22:12:55.287931 9, 0x0, sum = 2
4539 22:12:55.288114 10, 0x0, sum = 3
4540 22:12:55.290919 11, 0x0, sum = 4
4541 22:12:55.291002 best_step = 9
4542 22:12:55.291068
4543 22:12:55.291128 ==
4544 22:12:55.294625 Dram Type= 6, Freq= 0, CH_1, rank 0
4545 22:12:55.301143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4546 22:12:55.301230 ==
4547 22:12:55.301297 RX Vref Scan: 1
4548 22:12:55.301358
4549 22:12:55.304035 RX Vref 0 -> 0, step: 1
4550 22:12:55.304118
4551 22:12:55.307411 RX Delay -163 -> 252, step: 8
4552 22:12:55.307493
4553 22:12:55.310900 Set Vref, RX VrefLevel [Byte0]: 54
4554 22:12:55.314624 [Byte1]: 45
4555 22:12:55.314706
4556 22:12:55.317626 Final RX Vref Byte 0 = 54 to rank0
4557 22:12:55.320997 Final RX Vref Byte 1 = 45 to rank0
4558 22:12:55.323883 Final RX Vref Byte 0 = 54 to rank1
4559 22:12:55.327727 Final RX Vref Byte 1 = 45 to rank1==
4560 22:12:55.330539 Dram Type= 6, Freq= 0, CH_1, rank 0
4561 22:12:55.334253 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4562 22:12:55.334336 ==
4563 22:12:55.337558 DQS Delay:
4564 22:12:55.337639 DQS0 = 0, DQS1 = 0
4565 22:12:55.341113 DQM Delay:
4566 22:12:55.341194 DQM0 = 48, DQM1 = 46
4567 22:12:55.341259 DQ Delay:
4568 22:12:55.344152 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4569 22:12:55.347778 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4570 22:12:55.350851 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =40
4571 22:12:55.354600 DQ12 =56, DQ13 =52, DQ14 =52, DQ15 =56
4572 22:12:55.354682
4573 22:12:55.354746
4574 22:12:55.364247 [DQSOSCAuto] RK0, (LSB)MR18= 0x496f, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
4575 22:12:55.367337 CH1 RK0: MR19=808, MR18=496F
4576 22:12:55.373787 CH1_RK0: MR19=0x808, MR18=0x496F, DQSOSC=389, MR23=63, INC=173, DEC=115
4577 22:12:55.373870
4578 22:12:55.377501 ----->DramcWriteLeveling(PI) begin...
4579 22:12:55.377607 ==
4580 22:12:55.380601 Dram Type= 6, Freq= 0, CH_1, rank 1
4581 22:12:55.383925 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4582 22:12:55.384009 ==
4583 22:12:55.387364 Write leveling (Byte 0): 31 => 31
4584 22:12:55.390702 Write leveling (Byte 1): 32 => 32
4585 22:12:55.393922 DramcWriteLeveling(PI) end<-----
4586 22:12:55.394005
4587 22:12:55.394070 ==
4588 22:12:55.397197 Dram Type= 6, Freq= 0, CH_1, rank 1
4589 22:12:55.400625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4590 22:12:55.400708 ==
4591 22:12:55.404157 [Gating] SW mode calibration
4592 22:12:55.410595 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4593 22:12:55.416988 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4594 22:12:55.420516 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4595 22:12:55.423689 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4596 22:12:55.430769 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
4597 22:12:55.433877 0 9 12 | B1->B0 | 2e2e 2e2e | 1 0 | (1 0) (0 1)
4598 22:12:55.437316 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4599 22:12:55.443730 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4600 22:12:55.447342 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4601 22:12:55.450341 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4602 22:12:55.457071 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4603 22:12:55.460132 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4604 22:12:55.463348 0 10 8 | B1->B0 | 2525 2424 | 0 0 | (0 0) (0 0)
4605 22:12:55.470005 0 10 12 | B1->B0 | 3e3e 3535 | 0 0 | (1 1) (0 0)
4606 22:12:55.473691 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4607 22:12:55.477429 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4608 22:12:55.480139 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4609 22:12:55.486628 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4610 22:12:55.490130 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4611 22:12:55.493533 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4612 22:12:55.500201 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4613 22:12:55.503413 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4614 22:12:55.506975 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4615 22:12:55.513797 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4616 22:12:55.516691 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4617 22:12:55.520137 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4618 22:12:55.526637 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4619 22:12:55.530070 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4620 22:12:55.533709 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4621 22:12:55.540274 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4622 22:12:55.543318 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4623 22:12:55.546875 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4624 22:12:55.553463 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4625 22:12:55.556556 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4626 22:12:55.560245 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4627 22:12:55.566549 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4628 22:12:55.569648 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4629 22:12:55.573161 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4630 22:12:55.576493 Total UI for P1: 0, mck2ui 16
4631 22:12:55.579971 best dqsien dly found for B0: ( 0, 13, 10)
4632 22:12:55.583309 Total UI for P1: 0, mck2ui 16
4633 22:12:55.586600 best dqsien dly found for B1: ( 0, 13, 8)
4634 22:12:55.590077 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4635 22:12:55.593182 best DQS1 dly(MCK, UI, PI) = (0, 13, 8)
4636 22:12:55.593285
4637 22:12:55.596589 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4638 22:12:55.603215 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 8)
4639 22:12:55.603322 [Gating] SW calibration Done
4640 22:12:55.603417 ==
4641 22:12:55.606745 Dram Type= 6, Freq= 0, CH_1, rank 1
4642 22:12:55.613100 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4643 22:12:55.613203 ==
4644 22:12:55.613298 RX Vref Scan: 0
4645 22:12:55.613388
4646 22:12:55.616662 RX Vref 0 -> 0, step: 1
4647 22:12:55.616738
4648 22:12:55.619832 RX Delay -230 -> 252, step: 16
4649 22:12:55.623451 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4650 22:12:55.626929 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4651 22:12:55.630334 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4652 22:12:55.636610 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4653 22:12:55.640138 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4654 22:12:55.643405 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4655 22:12:55.647107 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4656 22:12:55.649885 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4657 22:12:55.656502 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4658 22:12:55.659875 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4659 22:12:55.663467 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4660 22:12:55.666569 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4661 22:12:55.673216 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4662 22:12:55.676921 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4663 22:12:55.679940 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4664 22:12:55.683067 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4665 22:12:55.686505 ==
4666 22:12:55.686601 Dram Type= 6, Freq= 0, CH_1, rank 1
4667 22:12:55.693197 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4668 22:12:55.693308 ==
4669 22:12:55.693400 DQS Delay:
4670 22:12:55.696257 DQS0 = 0, DQS1 = 0
4671 22:12:55.696355 DQM Delay:
4672 22:12:55.699776 DQM0 = 50, DQM1 = 46
4673 22:12:55.699875 DQ Delay:
4674 22:12:55.702825 DQ0 =49, DQ1 =49, DQ2 =33, DQ3 =49
4675 22:12:55.706404 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4676 22:12:55.709661 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4677 22:12:55.713307 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4678 22:12:55.713414
4679 22:12:55.713507
4680 22:12:55.713578 ==
4681 22:12:55.715992 Dram Type= 6, Freq= 0, CH_1, rank 1
4682 22:12:55.719525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4683 22:12:55.719629 ==
4684 22:12:55.719719
4685 22:12:55.719849
4686 22:12:55.722806 TX Vref Scan disable
4687 22:12:55.726231 == TX Byte 0 ==
4688 22:12:55.729500 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4689 22:12:55.732851 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4690 22:12:55.736341 == TX Byte 1 ==
4691 22:12:55.739876 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4692 22:12:55.742649 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4693 22:12:55.742752 ==
4694 22:12:55.746060 Dram Type= 6, Freq= 0, CH_1, rank 1
4695 22:12:55.752486 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4696 22:12:55.752589 ==
4697 22:12:55.752661
4698 22:12:55.752721
4699 22:12:55.752779 TX Vref Scan disable
4700 22:12:55.756590 == TX Byte 0 ==
4701 22:12:55.759942 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4702 22:12:55.763039 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4703 22:12:55.766538 == TX Byte 1 ==
4704 22:12:55.769791 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4705 22:12:55.773370 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4706 22:12:55.777179
4707 22:12:55.777280 [DATLAT]
4708 22:12:55.777373 Freq=600, CH1 RK1
4709 22:12:55.777460
4710 22:12:55.780139 DATLAT Default: 0x9
4711 22:12:55.780235 0, 0xFFFF, sum = 0
4712 22:12:55.783301 1, 0xFFFF, sum = 0
4713 22:12:55.783401 2, 0xFFFF, sum = 0
4714 22:12:55.786409 3, 0xFFFF, sum = 0
4715 22:12:55.786482 4, 0xFFFF, sum = 0
4716 22:12:55.789902 5, 0xFFFF, sum = 0
4717 22:12:55.793527 6, 0xFFFF, sum = 0
4718 22:12:55.793605 7, 0xFFFF, sum = 0
4719 22:12:55.793668 8, 0x0, sum = 1
4720 22:12:55.796539 9, 0x0, sum = 2
4721 22:12:55.796636 10, 0x0, sum = 3
4722 22:12:55.800291 11, 0x0, sum = 4
4723 22:12:55.800394 best_step = 9
4724 22:12:55.800485
4725 22:12:55.800571 ==
4726 22:12:55.803177 Dram Type= 6, Freq= 0, CH_1, rank 1
4727 22:12:55.810006 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4728 22:12:55.810085 ==
4729 22:12:55.810149 RX Vref Scan: 0
4730 22:12:55.810216
4731 22:12:55.813357 RX Vref 0 -> 0, step: 1
4732 22:12:55.813456
4733 22:12:55.816726 RX Delay -163 -> 252, step: 8
4734 22:12:55.819489 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4735 22:12:55.826115 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4736 22:12:55.829627 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4737 22:12:55.833063 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4738 22:12:55.836383 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4739 22:12:55.839562 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4740 22:12:55.846389 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4741 22:12:55.849748 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4742 22:12:55.853058 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4743 22:12:55.856788 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4744 22:12:55.859730 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4745 22:12:55.866243 iDelay=205, Bit 11, Center 36 (-107 ~ 180) 288
4746 22:12:55.869684 iDelay=205, Bit 12, Center 56 (-91 ~ 204) 296
4747 22:12:55.873175 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4748 22:12:55.876415 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4749 22:12:55.880246 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4750 22:12:55.883164 ==
4751 22:12:55.883243 Dram Type= 6, Freq= 0, CH_1, rank 1
4752 22:12:55.890067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4753 22:12:55.890167 ==
4754 22:12:55.890261 DQS Delay:
4755 22:12:55.893117 DQS0 = 0, DQS1 = 0
4756 22:12:55.893215 DQM Delay:
4757 22:12:55.896359 DQM0 = 49, DQM1 = 45
4758 22:12:55.896456 DQ Delay:
4759 22:12:55.899398 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4760 22:12:55.903219 DQ4 =48, DQ5 =60, DQ6 =60, DQ7 =48
4761 22:12:55.906355 DQ8 =32, DQ9 =32, DQ10 =48, DQ11 =36
4762 22:12:55.909984 DQ12 =56, DQ13 =52, DQ14 =52, DQ15 =52
4763 22:12:55.910085
4764 22:12:55.910175
4765 22:12:55.916706 [DQSOSCAuto] RK1, (LSB)MR18= 0x6e25, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 389 ps
4766 22:12:55.919656 CH1 RK1: MR19=808, MR18=6E25
4767 22:12:55.926104 CH1_RK1: MR19=0x808, MR18=0x6E25, DQSOSC=389, MR23=63, INC=173, DEC=115
4768 22:12:55.929613 [RxdqsGatingPostProcess] freq 600
4769 22:12:55.936368 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4770 22:12:55.936473 Pre-setting of DQS Precalculation
4771 22:12:55.943130 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4772 22:12:55.949679 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4773 22:12:55.956319 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4774 22:12:55.956428
4775 22:12:55.956520
4776 22:12:55.959632 [Calibration Summary] 1200 Mbps
4777 22:12:55.959733 CH 0, Rank 0
4778 22:12:55.963081 SW Impedance : PASS
4779 22:12:55.966796 DUTY Scan : NO K
4780 22:12:55.966926 ZQ Calibration : PASS
4781 22:12:55.969546 Jitter Meter : NO K
4782 22:12:55.972711 CBT Training : PASS
4783 22:12:55.972814 Write leveling : PASS
4784 22:12:55.976038 RX DQS gating : PASS
4785 22:12:55.979674 RX DQ/DQS(RDDQC) : PASS
4786 22:12:55.979782 TX DQ/DQS : PASS
4787 22:12:55.982951 RX DATLAT : PASS
4788 22:12:55.986681 RX DQ/DQS(Engine): PASS
4789 22:12:55.986777 TX OE : NO K
4790 22:12:55.986844 All Pass.
4791 22:12:55.989319
4792 22:12:55.989401 CH 0, Rank 1
4793 22:12:55.993188 SW Impedance : PASS
4794 22:12:55.993270 DUTY Scan : NO K
4795 22:12:55.996280 ZQ Calibration : PASS
4796 22:12:55.999558 Jitter Meter : NO K
4797 22:12:55.999640 CBT Training : PASS
4798 22:12:56.002712 Write leveling : PASS
4799 22:12:56.002794 RX DQS gating : PASS
4800 22:12:56.006542 RX DQ/DQS(RDDQC) : PASS
4801 22:12:56.009506 TX DQ/DQS : PASS
4802 22:12:56.009640 RX DATLAT : PASS
4803 22:12:56.013249 RX DQ/DQS(Engine): PASS
4804 22:12:56.016361 TX OE : NO K
4805 22:12:56.016444 All Pass.
4806 22:12:56.016509
4807 22:12:56.016568 CH 1, Rank 0
4808 22:12:56.019541 SW Impedance : PASS
4809 22:12:56.022587 DUTY Scan : NO K
4810 22:12:56.022669 ZQ Calibration : PASS
4811 22:12:56.026411 Jitter Meter : NO K
4812 22:12:56.029422 CBT Training : PASS
4813 22:12:56.029504 Write leveling : PASS
4814 22:12:56.032929 RX DQS gating : PASS
4815 22:12:56.035968 RX DQ/DQS(RDDQC) : PASS
4816 22:12:56.036050 TX DQ/DQS : PASS
4817 22:12:56.039574 RX DATLAT : PASS
4818 22:12:56.042944 RX DQ/DQS(Engine): PASS
4819 22:12:56.043027 TX OE : NO K
4820 22:12:56.043093 All Pass.
4821 22:12:56.045827
4822 22:12:56.045909 CH 1, Rank 1
4823 22:12:56.049461 SW Impedance : PASS
4824 22:12:56.049566 DUTY Scan : NO K
4825 22:12:56.052577 ZQ Calibration : PASS
4826 22:12:56.056129 Jitter Meter : NO K
4827 22:12:56.056212 CBT Training : PASS
4828 22:12:56.059721 Write leveling : PASS
4829 22:12:56.059803 RX DQS gating : PASS
4830 22:12:56.062757 RX DQ/DQS(RDDQC) : PASS
4831 22:12:56.065774 TX DQ/DQS : PASS
4832 22:12:56.065856 RX DATLAT : PASS
4833 22:12:56.069177 RX DQ/DQS(Engine): PASS
4834 22:12:56.072942 TX OE : NO K
4835 22:12:56.073025 All Pass.
4836 22:12:56.073090
4837 22:12:56.075856 DramC Write-DBI off
4838 22:12:56.075937 PER_BANK_REFRESH: Hybrid Mode
4839 22:12:56.079491 TX_TRACKING: ON
4840 22:12:56.086055 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4841 22:12:56.092389 [FAST_K] Save calibration result to emmc
4842 22:12:56.096139 dramc_set_vcore_voltage set vcore to 662500
4843 22:12:56.096221 Read voltage for 933, 3
4844 22:12:56.099220 Vio18 = 0
4845 22:12:56.099301 Vcore = 662500
4846 22:12:56.099366 Vdram = 0
4847 22:12:56.102707 Vddq = 0
4848 22:12:56.102790 Vmddr = 0
4849 22:12:56.105915 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4850 22:12:56.112910 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4851 22:12:56.116022 MEM_TYPE=3, freq_sel=17
4852 22:12:56.119192 sv_algorithm_assistance_LP4_1600
4853 22:12:56.122980 ============ PULL DRAM RESETB DOWN ============
4854 22:12:56.126007 ========== PULL DRAM RESETB DOWN end =========
4855 22:12:56.129001 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4856 22:12:56.132252 ===================================
4857 22:12:56.135754 LPDDR4 DRAM CONFIGURATION
4858 22:12:56.139485 ===================================
4859 22:12:56.142805 EX_ROW_EN[0] = 0x0
4860 22:12:56.142888 EX_ROW_EN[1] = 0x0
4861 22:12:56.145724 LP4Y_EN = 0x0
4862 22:12:56.145807 WORK_FSP = 0x0
4863 22:12:56.149179 WL = 0x3
4864 22:12:56.149261 RL = 0x3
4865 22:12:56.152733 BL = 0x2
4866 22:12:56.152815 RPST = 0x0
4867 22:12:56.155700 RD_PRE = 0x0
4868 22:12:56.155782 WR_PRE = 0x1
4869 22:12:56.159068 WR_PST = 0x0
4870 22:12:56.159150 DBI_WR = 0x0
4871 22:12:56.162580 DBI_RD = 0x0
4872 22:12:56.166161 OTF = 0x1
4873 22:12:56.169166 ===================================
4874 22:12:56.169252 ===================================
4875 22:12:56.172864 ANA top config
4876 22:12:56.175777 ===================================
4877 22:12:56.178967 DLL_ASYNC_EN = 0
4878 22:12:56.179040 ALL_SLAVE_EN = 1
4879 22:12:56.182565 NEW_RANK_MODE = 1
4880 22:12:56.185668 DLL_IDLE_MODE = 1
4881 22:12:56.188926 LP45_APHY_COMB_EN = 1
4882 22:12:56.192268 TX_ODT_DIS = 1
4883 22:12:56.192340 NEW_8X_MODE = 1
4884 22:12:56.195898 ===================================
4885 22:12:56.198959 ===================================
4886 22:12:56.202779 data_rate = 1866
4887 22:12:56.205702 CKR = 1
4888 22:12:56.209424 DQ_P2S_RATIO = 8
4889 22:12:56.212636 ===================================
4890 22:12:56.215731 CA_P2S_RATIO = 8
4891 22:12:56.215814 DQ_CA_OPEN = 0
4892 22:12:56.218987 DQ_SEMI_OPEN = 0
4893 22:12:56.222694 CA_SEMI_OPEN = 0
4894 22:12:56.225859 CA_FULL_RATE = 0
4895 22:12:56.228847 DQ_CKDIV4_EN = 1
4896 22:12:56.232472 CA_CKDIV4_EN = 1
4897 22:12:56.232555 CA_PREDIV_EN = 0
4898 22:12:56.235804 PH8_DLY = 0
4899 22:12:56.238761 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4900 22:12:56.242536 DQ_AAMCK_DIV = 4
4901 22:12:56.245630 CA_AAMCK_DIV = 4
4902 22:12:56.248977 CA_ADMCK_DIV = 4
4903 22:12:56.249085 DQ_TRACK_CA_EN = 0
4904 22:12:56.252041 CA_PICK = 933
4905 22:12:56.255400 CA_MCKIO = 933
4906 22:12:56.258774 MCKIO_SEMI = 0
4907 22:12:56.262172 PLL_FREQ = 3732
4908 22:12:56.265692 DQ_UI_PI_RATIO = 32
4909 22:12:56.269167 CA_UI_PI_RATIO = 0
4910 22:12:56.272105 ===================================
4911 22:12:56.275508 ===================================
4912 22:12:56.275592 memory_type:LPDDR4
4913 22:12:56.278611 GP_NUM : 10
4914 22:12:56.282172 SRAM_EN : 1
4915 22:12:56.282255 MD32_EN : 0
4916 22:12:56.285683 ===================================
4917 22:12:56.288571 [ANA_INIT] >>>>>>>>>>>>>>
4918 22:12:56.292099 <<<<<< [CONFIGURE PHASE]: ANA_TX
4919 22:12:56.295702 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4920 22:12:56.298857 ===================================
4921 22:12:56.301862 data_rate = 1866,PCW = 0X8f00
4922 22:12:56.305621 ===================================
4923 22:12:56.308532 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4924 22:12:56.312066 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4925 22:12:56.318613 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4926 22:12:56.321670 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4927 22:12:56.325373 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4928 22:12:56.328554 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4929 22:12:56.331742 [ANA_INIT] flow start
4930 22:12:56.335281 [ANA_INIT] PLL >>>>>>>>
4931 22:12:56.335380 [ANA_INIT] PLL <<<<<<<<
4932 22:12:56.338321 [ANA_INIT] MIDPI >>>>>>>>
4933 22:12:56.341706 [ANA_INIT] MIDPI <<<<<<<<
4934 22:12:56.345353 [ANA_INIT] DLL >>>>>>>>
4935 22:12:56.345476 [ANA_INIT] flow end
4936 22:12:56.348467 ============ LP4 DIFF to SE enter ============
4937 22:12:56.355005 ============ LP4 DIFF to SE exit ============
4938 22:12:56.355088 [ANA_INIT] <<<<<<<<<<<<<
4939 22:12:56.358201 [Flow] Enable top DCM control >>>>>
4940 22:12:56.361495 [Flow] Enable top DCM control <<<<<
4941 22:12:56.365266 Enable DLL master slave shuffle
4942 22:12:56.371988 ==============================================================
4943 22:12:56.372070 Gating Mode config
4944 22:12:56.378240 ==============================================================
4945 22:12:56.381973 Config description:
4946 22:12:56.391321 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4947 22:12:56.398394 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4948 22:12:56.401907 SELPH_MODE 0: By rank 1: By Phase
4949 22:12:56.407972 ==============================================================
4950 22:12:56.411711 GAT_TRACK_EN = 1
4951 22:12:56.411792 RX_GATING_MODE = 2
4952 22:12:56.414694 RX_GATING_TRACK_MODE = 2
4953 22:12:56.418366 SELPH_MODE = 1
4954 22:12:56.421413 PICG_EARLY_EN = 1
4955 22:12:56.424670 VALID_LAT_VALUE = 1
4956 22:12:56.431544 ==============================================================
4957 22:12:56.434753 Enter into Gating configuration >>>>
4958 22:12:56.437683 Exit from Gating configuration <<<<
4959 22:12:56.441095 Enter into DVFS_PRE_config >>>>>
4960 22:12:56.451303 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4961 22:12:56.454875 Exit from DVFS_PRE_config <<<<<
4962 22:12:56.458124 Enter into PICG configuration >>>>
4963 22:12:56.461073 Exit from PICG configuration <<<<
4964 22:12:56.464686 [RX_INPUT] configuration >>>>>
4965 22:12:56.467774 [RX_INPUT] configuration <<<<<
4966 22:12:56.471164 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4967 22:12:56.478282 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4968 22:12:56.484646 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4969 22:12:56.488183 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4970 22:12:56.494765 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4971 22:12:56.500889 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4972 22:12:56.504677 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4973 22:12:56.511279 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4974 22:12:56.514568 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4975 22:12:56.518009 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4976 22:12:56.520953 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4977 22:12:56.528006 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4978 22:12:56.531231 ===================================
4979 22:12:56.531315 LPDDR4 DRAM CONFIGURATION
4980 22:12:56.534503 ===================================
4981 22:12:56.538176 EX_ROW_EN[0] = 0x0
4982 22:12:56.541147 EX_ROW_EN[1] = 0x0
4983 22:12:56.541230 LP4Y_EN = 0x0
4984 22:12:56.544859 WORK_FSP = 0x0
4985 22:12:56.544942 WL = 0x3
4986 22:12:56.547848 RL = 0x3
4987 22:12:56.547931 BL = 0x2
4988 22:12:56.551047 RPST = 0x0
4989 22:12:56.551130 RD_PRE = 0x0
4990 22:12:56.554292 WR_PRE = 0x1
4991 22:12:56.554374 WR_PST = 0x0
4992 22:12:56.558000 DBI_WR = 0x0
4993 22:12:56.558083 DBI_RD = 0x0
4994 22:12:56.560859 OTF = 0x1
4995 22:12:56.564114 ===================================
4996 22:12:56.567771 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4997 22:12:56.570957 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4998 22:12:56.577961 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4999 22:12:56.578047 ===================================
5000 22:12:56.581493 LPDDR4 DRAM CONFIGURATION
5001 22:12:56.584435 ===================================
5002 22:12:56.587439 EX_ROW_EN[0] = 0x10
5003 22:12:56.587521 EX_ROW_EN[1] = 0x0
5004 22:12:56.590726 LP4Y_EN = 0x0
5005 22:12:56.590809 WORK_FSP = 0x0
5006 22:12:56.594131 WL = 0x3
5007 22:12:56.594214 RL = 0x3
5008 22:12:56.597622 BL = 0x2
5009 22:12:56.597735 RPST = 0x0
5010 22:12:56.601330 RD_PRE = 0x0
5011 22:12:56.604154 WR_PRE = 0x1
5012 22:12:56.604237 WR_PST = 0x0
5013 22:12:56.607895 DBI_WR = 0x0
5014 22:12:56.607977 DBI_RD = 0x0
5015 22:12:56.610950 OTF = 0x1
5016 22:12:56.614655 ===================================
5017 22:12:56.617470 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5018 22:12:56.622704 nWR fixed to 30
5019 22:12:56.626466 [ModeRegInit_LP4] CH0 RK0
5020 22:12:56.626549 [ModeRegInit_LP4] CH0 RK1
5021 22:12:56.629456 [ModeRegInit_LP4] CH1 RK0
5022 22:12:56.632702 [ModeRegInit_LP4] CH1 RK1
5023 22:12:56.632785 match AC timing 9
5024 22:12:56.639619 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5025 22:12:56.642902 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5026 22:12:56.646059 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5027 22:12:56.652689 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5028 22:12:56.656247 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5029 22:12:56.656330 ==
5030 22:12:56.659329 Dram Type= 6, Freq= 0, CH_0, rank 0
5031 22:12:56.663185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5032 22:12:56.663268 ==
5033 22:12:56.669912 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5034 22:12:56.676556 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5035 22:12:56.679371 [CA 0] Center 37 (6~68) winsize 63
5036 22:12:56.682920 [CA 1] Center 37 (7~68) winsize 62
5037 22:12:56.686430 [CA 2] Center 34 (4~65) winsize 62
5038 22:12:56.689388 [CA 3] Center 33 (3~64) winsize 62
5039 22:12:56.693009 [CA 4] Center 33 (3~64) winsize 62
5040 22:12:56.696382 [CA 5] Center 32 (2~62) winsize 61
5041 22:12:56.696465
5042 22:12:56.699434 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5043 22:12:56.699517
5044 22:12:56.702904 [CATrainingPosCal] consider 1 rank data
5045 22:12:56.706546 u2DelayCellTimex100 = 270/100 ps
5046 22:12:56.709517 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5047 22:12:56.713191 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5048 22:12:56.716396 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5049 22:12:56.719807 CA3 delay=33 (3~64),Diff = 1 PI (6 cell)
5050 22:12:56.722869 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5051 22:12:56.726457 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5052 22:12:56.726541
5053 22:12:56.733041 CA PerBit enable=1, Macro0, CA PI delay=32
5054 22:12:56.733125
5055 22:12:56.733190 [CBTSetCACLKResult] CA Dly = 32
5056 22:12:56.736310 CS Dly: 5 (0~36)
5057 22:12:56.736392 ==
5058 22:12:56.739316 Dram Type= 6, Freq= 0, CH_0, rank 1
5059 22:12:56.742872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5060 22:12:56.742956 ==
5061 22:12:56.749472 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5062 22:12:56.756113 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5063 22:12:56.759211 [CA 0] Center 37 (6~68) winsize 63
5064 22:12:56.763021 [CA 1] Center 37 (7~68) winsize 62
5065 22:12:56.766016 [CA 2] Center 34 (4~65) winsize 62
5066 22:12:56.769576 [CA 3] Center 34 (3~65) winsize 63
5067 22:12:56.772879 [CA 4] Center 32 (2~63) winsize 62
5068 22:12:56.775870 [CA 5] Center 32 (2~62) winsize 61
5069 22:12:56.775954
5070 22:12:56.779146 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5071 22:12:56.779230
5072 22:12:56.782734 [CATrainingPosCal] consider 2 rank data
5073 22:12:56.786110 u2DelayCellTimex100 = 270/100 ps
5074 22:12:56.789772 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5075 22:12:56.792410 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5076 22:12:56.795882 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5077 22:12:56.799687 CA3 delay=33 (3~64),Diff = 1 PI (6 cell)
5078 22:12:56.802406 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5079 22:12:56.805780 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5080 22:12:56.809154
5081 22:12:56.812887 CA PerBit enable=1, Macro0, CA PI delay=32
5082 22:12:56.812971
5083 22:12:56.815733 [CBTSetCACLKResult] CA Dly = 32
5084 22:12:56.815817 CS Dly: 5 (0~37)
5085 22:12:56.815902
5086 22:12:56.819449 ----->DramcWriteLeveling(PI) begin...
5087 22:12:56.819534 ==
5088 22:12:56.822482 Dram Type= 6, Freq= 0, CH_0, rank 0
5089 22:12:56.826028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5090 22:12:56.828766 ==
5091 22:12:56.828850 Write leveling (Byte 0): 30 => 30
5092 22:12:56.832583 Write leveling (Byte 1): 28 => 28
5093 22:12:56.835790 DramcWriteLeveling(PI) end<-----
5094 22:12:56.835874
5095 22:12:56.835958 ==
5096 22:12:56.839098 Dram Type= 6, Freq= 0, CH_0, rank 0
5097 22:12:56.845818 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5098 22:12:56.845903 ==
5099 22:12:56.845986 [Gating] SW mode calibration
5100 22:12:56.855678 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5101 22:12:56.858978 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5102 22:12:56.865822 0 14 0 | B1->B0 | 2727 3434 | 0 1 | (0 0) (1 1)
5103 22:12:56.869063 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5104 22:12:56.872524 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5105 22:12:56.875725 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5106 22:12:56.882513 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5107 22:12:56.885857 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5108 22:12:56.888916 0 14 24 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
5109 22:12:56.895348 0 14 28 | B1->B0 | 3333 2424 | 0 0 | (0 1) (0 0)
5110 22:12:56.898778 0 15 0 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
5111 22:12:56.902367 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5112 22:12:56.908571 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5113 22:12:56.912156 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5114 22:12:56.915693 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5115 22:12:56.922154 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5116 22:12:56.925671 0 15 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5117 22:12:56.928705 0 15 28 | B1->B0 | 2525 3a3a | 0 0 | (0 0) (0 0)
5118 22:12:56.935611 1 0 0 | B1->B0 | 4040 4646 | 1 0 | (0 0) (0 0)
5119 22:12:56.939111 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5120 22:12:56.942472 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5121 22:12:56.948550 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5122 22:12:56.952180 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5123 22:12:56.955268 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5124 22:12:56.962194 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5125 22:12:56.965095 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5126 22:12:56.968357 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5127 22:12:56.975019 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5128 22:12:56.978609 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5129 22:12:56.981539 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5130 22:12:56.988533 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5131 22:12:56.991676 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5132 22:12:56.995385 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5133 22:12:57.001953 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5134 22:12:57.004933 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5135 22:12:57.008579 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5136 22:12:57.012169 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5137 22:12:57.018278 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5138 22:12:57.021634 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5139 22:12:57.025218 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5140 22:12:57.032157 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5141 22:12:57.035353 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5142 22:12:57.038790 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5143 22:12:57.041882 Total UI for P1: 0, mck2ui 16
5144 22:12:57.045213 best dqsien dly found for B0: ( 1, 2, 26)
5145 22:12:57.052232 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5146 22:12:57.052336 Total UI for P1: 0, mck2ui 16
5147 22:12:57.058440 best dqsien dly found for B1: ( 1, 3, 0)
5148 22:12:57.062179 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5149 22:12:57.065143 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5150 22:12:57.065226
5151 22:12:57.068185 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5152 22:12:57.072036 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5153 22:12:57.075220 [Gating] SW calibration Done
5154 22:12:57.075303 ==
5155 22:12:57.079060 Dram Type= 6, Freq= 0, CH_0, rank 0
5156 22:12:57.081829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5157 22:12:57.081913 ==
5158 22:12:57.084937 RX Vref Scan: 0
5159 22:12:57.085019
5160 22:12:57.085084 RX Vref 0 -> 0, step: 1
5161 22:12:57.085144
5162 22:12:57.088148 RX Delay -80 -> 252, step: 8
5163 22:12:57.091939 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5164 22:12:57.098761 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5165 22:12:57.101619 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5166 22:12:57.105306 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5167 22:12:57.108266 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5168 22:12:57.111358 iDelay=208, Bit 5, Center 95 (8 ~ 183) 176
5169 22:12:57.115130 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5170 22:12:57.121644 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5171 22:12:57.124547 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5172 22:12:57.127876 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5173 22:12:57.131411 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5174 22:12:57.134474 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5175 22:12:57.137887 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5176 22:12:57.144421 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5177 22:12:57.148056 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5178 22:12:57.151571 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5179 22:12:57.151669 ==
5180 22:12:57.154740 Dram Type= 6, Freq= 0, CH_0, rank 0
5181 22:12:57.157749 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5182 22:12:57.161188 ==
5183 22:12:57.161293 DQS Delay:
5184 22:12:57.161387 DQS0 = 0, DQS1 = 0
5185 22:12:57.164282 DQM Delay:
5186 22:12:57.164387 DQM0 = 104, DQM1 = 94
5187 22:12:57.167415 DQ Delay:
5188 22:12:57.171171 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5189 22:12:57.174208 DQ4 =107, DQ5 =95, DQ6 =111, DQ7 =115
5190 22:12:57.177305 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =91
5191 22:12:57.181028 DQ12 =99, DQ13 =103, DQ14 =103, DQ15 =99
5192 22:12:57.181138
5193 22:12:57.181229
5194 22:12:57.181325 ==
5195 22:12:57.184243 Dram Type= 6, Freq= 0, CH_0, rank 0
5196 22:12:57.187587 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5197 22:12:57.187687 ==
5198 22:12:57.187778
5199 22:12:57.187874
5200 22:12:57.191004 TX Vref Scan disable
5201 22:12:57.194179 == TX Byte 0 ==
5202 22:12:57.197817 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5203 22:12:57.200771 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5204 22:12:57.203843 == TX Byte 1 ==
5205 22:12:57.207528 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5206 22:12:57.210679 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5207 22:12:57.210779 ==
5208 22:12:57.214276 Dram Type= 6, Freq= 0, CH_0, rank 0
5209 22:12:57.217505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5210 22:12:57.217636 ==
5211 22:12:57.221168
5212 22:12:57.221264
5213 22:12:57.221355 TX Vref Scan disable
5214 22:12:57.224151 == TX Byte 0 ==
5215 22:12:57.227888 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5216 22:12:57.230781 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5217 22:12:57.234248 == TX Byte 1 ==
5218 22:12:57.237231 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5219 22:12:57.240726 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5220 22:12:57.244464
5221 22:12:57.244544 [DATLAT]
5222 22:12:57.244609 Freq=933, CH0 RK0
5223 22:12:57.244668
5224 22:12:57.247599 DATLAT Default: 0xd
5225 22:12:57.247680 0, 0xFFFF, sum = 0
5226 22:12:57.250897 1, 0xFFFF, sum = 0
5227 22:12:57.250980 2, 0xFFFF, sum = 0
5228 22:12:57.253992 3, 0xFFFF, sum = 0
5229 22:12:57.254103 4, 0xFFFF, sum = 0
5230 22:12:57.257442 5, 0xFFFF, sum = 0
5231 22:12:57.260996 6, 0xFFFF, sum = 0
5232 22:12:57.261078 7, 0xFFFF, sum = 0
5233 22:12:57.264314 8, 0xFFFF, sum = 0
5234 22:12:57.264414 9, 0xFFFF, sum = 0
5235 22:12:57.267716 10, 0x0, sum = 1
5236 22:12:57.267798 11, 0x0, sum = 2
5237 22:12:57.267864 12, 0x0, sum = 3
5238 22:12:57.270621 13, 0x0, sum = 4
5239 22:12:57.270703 best_step = 11
5240 22:12:57.270767
5241 22:12:57.274247 ==
5242 22:12:57.274328 Dram Type= 6, Freq= 0, CH_0, rank 0
5243 22:12:57.280736 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5244 22:12:57.280818 ==
5245 22:12:57.280883 RX Vref Scan: 1
5246 22:12:57.280942
5247 22:12:57.283814 RX Vref 0 -> 0, step: 1
5248 22:12:57.283895
5249 22:12:57.287524 RX Delay -53 -> 252, step: 4
5250 22:12:57.287605
5251 22:12:57.290411 Set Vref, RX VrefLevel [Byte0]: 55
5252 22:12:57.294111 [Byte1]: 53
5253 22:12:57.294192
5254 22:12:57.297274 Final RX Vref Byte 0 = 55 to rank0
5255 22:12:57.300397 Final RX Vref Byte 1 = 53 to rank0
5256 22:12:57.303578 Final RX Vref Byte 0 = 55 to rank1
5257 22:12:57.307358 Final RX Vref Byte 1 = 53 to rank1==
5258 22:12:57.310915 Dram Type= 6, Freq= 0, CH_0, rank 0
5259 22:12:57.313527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5260 22:12:57.313609 ==
5261 22:12:57.316979 DQS Delay:
5262 22:12:57.317060 DQS0 = 0, DQS1 = 0
5263 22:12:57.320762 DQM Delay:
5264 22:12:57.320842 DQM0 = 104, DQM1 = 97
5265 22:12:57.320906 DQ Delay:
5266 22:12:57.326957 DQ0 =104, DQ1 =106, DQ2 =104, DQ3 =102
5267 22:12:57.330446 DQ4 =106, DQ5 =96, DQ6 =110, DQ7 =110
5268 22:12:57.333456 DQ8 =86, DQ9 =88, DQ10 =96, DQ11 =92
5269 22:12:57.337070 DQ12 =102, DQ13 =102, DQ14 =106, DQ15 =104
5270 22:12:57.337176
5271 22:12:57.337254
5272 22:12:57.343435 [DQSOSCAuto] RK0, (LSB)MR18= 0x342c, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 405 ps
5273 22:12:57.346924 CH0 RK0: MR19=505, MR18=342C
5274 22:12:57.353631 CH0_RK0: MR19=0x505, MR18=0x342C, DQSOSC=405, MR23=63, INC=66, DEC=44
5275 22:12:57.353713
5276 22:12:57.356656 ----->DramcWriteLeveling(PI) begin...
5277 22:12:57.356766 ==
5278 22:12:57.360274 Dram Type= 6, Freq= 0, CH_0, rank 1
5279 22:12:57.363769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5280 22:12:57.363851 ==
5281 22:12:57.367243 Write leveling (Byte 0): 34 => 34
5282 22:12:57.370100 Write leveling (Byte 1): 32 => 32
5283 22:12:57.373729 DramcWriteLeveling(PI) end<-----
5284 22:12:57.373809
5285 22:12:57.373873 ==
5286 22:12:57.377192 Dram Type= 6, Freq= 0, CH_0, rank 1
5287 22:12:57.380783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5288 22:12:57.380864 ==
5289 22:12:57.383819 [Gating] SW mode calibration
5290 22:12:57.390711 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5291 22:12:57.396796 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5292 22:12:57.400474 0 14 0 | B1->B0 | 3434 3232 | 0 1 | (0 0) (1 1)
5293 22:12:57.406886 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5294 22:12:57.409868 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5295 22:12:57.413262 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5296 22:12:57.420291 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5297 22:12:57.423315 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5298 22:12:57.427101 0 14 24 | B1->B0 | 3434 3434 | 0 0 | (0 0) (0 0)
5299 22:12:57.433351 0 14 28 | B1->B0 | 2929 2e2e | 0 0 | (0 0) (0 1)
5300 22:12:57.437019 0 15 0 | B1->B0 | 2525 2525 | 0 0 | (0 0) (1 0)
5301 22:12:57.440110 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5302 22:12:57.443571 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5303 22:12:57.450032 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5304 22:12:57.453546 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5305 22:12:57.457079 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5306 22:12:57.463611 0 15 24 | B1->B0 | 2626 2424 | 0 0 | (0 0) (0 0)
5307 22:12:57.466860 0 15 28 | B1->B0 | 3a3a 3636 | 1 1 | (0 0) (0 0)
5308 22:12:57.470319 1 0 0 | B1->B0 | 4444 4545 | 0 0 | (0 0) (0 0)
5309 22:12:57.476429 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5310 22:12:57.479973 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5311 22:12:57.483421 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5312 22:12:57.490274 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5313 22:12:57.493344 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5314 22:12:57.496565 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5315 22:12:57.503287 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5316 22:12:57.506976 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5317 22:12:57.509874 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5318 22:12:57.516768 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5319 22:12:57.520388 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5320 22:12:57.523595 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5321 22:12:57.530331 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5322 22:12:57.533394 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5323 22:12:57.536552 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5324 22:12:57.543178 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5325 22:12:57.546349 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5326 22:12:57.549497 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5327 22:12:57.556294 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5328 22:12:57.559863 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5329 22:12:57.562918 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5330 22:12:57.566551 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5331 22:12:57.573121 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5332 22:12:57.576238 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5333 22:12:57.579903 Total UI for P1: 0, mck2ui 16
5334 22:12:57.582974 best dqsien dly found for B0: ( 1, 2, 28)
5335 22:12:57.586561 Total UI for P1: 0, mck2ui 16
5336 22:12:57.589781 best dqsien dly found for B1: ( 1, 2, 28)
5337 22:12:57.593137 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5338 22:12:57.596824 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5339 22:12:57.596916
5340 22:12:57.599677 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5341 22:12:57.603244 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5342 22:12:57.606577 [Gating] SW calibration Done
5343 22:12:57.606657 ==
5344 22:12:57.609671 Dram Type= 6, Freq= 0, CH_0, rank 1
5345 22:12:57.616456 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5346 22:12:57.616536 ==
5347 22:12:57.616599 RX Vref Scan: 0
5348 22:12:57.616658
5349 22:12:57.619957 RX Vref 0 -> 0, step: 1
5350 22:12:57.620037
5351 22:12:57.623010 RX Delay -80 -> 252, step: 8
5352 22:12:57.626271 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5353 22:12:57.629929 iDelay=208, Bit 1, Center 111 (24 ~ 199) 176
5354 22:12:57.632988 iDelay=208, Bit 2, Center 103 (8 ~ 199) 192
5355 22:12:57.636120 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5356 22:12:57.643083 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5357 22:12:57.646232 iDelay=208, Bit 5, Center 99 (8 ~ 191) 184
5358 22:12:57.649747 iDelay=208, Bit 6, Center 111 (24 ~ 199) 176
5359 22:12:57.652676 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5360 22:12:57.656191 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5361 22:12:57.659889 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5362 22:12:57.666400 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5363 22:12:57.669432 iDelay=208, Bit 11, Center 91 (8 ~ 175) 168
5364 22:12:57.672648 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5365 22:12:57.675988 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5366 22:12:57.679505 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5367 22:12:57.682758 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5368 22:12:57.686608 ==
5369 22:12:57.689632 Dram Type= 6, Freq= 0, CH_0, rank 1
5370 22:12:57.693143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5371 22:12:57.693227 ==
5372 22:12:57.693311 DQS Delay:
5373 22:12:57.696169 DQS0 = 0, DQS1 = 0
5374 22:12:57.696253 DQM Delay:
5375 22:12:57.699202 DQM0 = 106, DQM1 = 94
5376 22:12:57.699285 DQ Delay:
5377 22:12:57.702850 DQ0 =107, DQ1 =111, DQ2 =103, DQ3 =99
5378 22:12:57.706160 DQ4 =107, DQ5 =99, DQ6 =111, DQ7 =115
5379 22:12:57.709097 DQ8 =87, DQ9 =83, DQ10 =95, DQ11 =91
5380 22:12:57.712828 DQ12 =99, DQ13 =99, DQ14 =103, DQ15 =99
5381 22:12:57.712911
5382 22:12:57.712976
5383 22:12:57.713036 ==
5384 22:12:57.715956 Dram Type= 6, Freq= 0, CH_0, rank 1
5385 22:12:57.719650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5386 22:12:57.722968 ==
5387 22:12:57.723050
5388 22:12:57.723115
5389 22:12:57.723173 TX Vref Scan disable
5390 22:12:57.725823 == TX Byte 0 ==
5391 22:12:57.728936 Update DQ dly =719 (2 ,6, 15) DQ OEN =(2 ,3)
5392 22:12:57.732567 Update DQM dly =719 (2 ,6, 15) DQM OEN =(2 ,3)
5393 22:12:57.735887 == TX Byte 1 ==
5394 22:12:57.739476 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5395 22:12:57.742649 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5396 22:12:57.742732 ==
5397 22:12:57.745805 Dram Type= 6, Freq= 0, CH_0, rank 1
5398 22:12:57.752473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5399 22:12:57.752556 ==
5400 22:12:57.752622
5401 22:12:57.752683
5402 22:12:57.756252 TX Vref Scan disable
5403 22:12:57.756334 == TX Byte 0 ==
5404 22:12:57.762543 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5405 22:12:57.765549 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5406 22:12:57.765632 == TX Byte 1 ==
5407 22:12:57.772519 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5408 22:12:57.776149 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5409 22:12:57.776232
5410 22:12:57.776297 [DATLAT]
5411 22:12:57.779121 Freq=933, CH0 RK1
5412 22:12:57.779204
5413 22:12:57.779276 DATLAT Default: 0xb
5414 22:12:57.782476 0, 0xFFFF, sum = 0
5415 22:12:57.782560 1, 0xFFFF, sum = 0
5416 22:12:57.785666 2, 0xFFFF, sum = 0
5417 22:12:57.785750 3, 0xFFFF, sum = 0
5418 22:12:57.789570 4, 0xFFFF, sum = 0
5419 22:12:57.789653 5, 0xFFFF, sum = 0
5420 22:12:57.792627 6, 0xFFFF, sum = 0
5421 22:12:57.792710 7, 0xFFFF, sum = 0
5422 22:12:57.795701 8, 0xFFFF, sum = 0
5423 22:12:57.795784 9, 0xFFFF, sum = 0
5424 22:12:57.799299 10, 0x0, sum = 1
5425 22:12:57.799382 11, 0x0, sum = 2
5426 22:12:57.802155 12, 0x0, sum = 3
5427 22:12:57.802237 13, 0x0, sum = 4
5428 22:12:57.805530 best_step = 11
5429 22:12:57.805633
5430 22:12:57.805698 ==
5431 22:12:57.809182 Dram Type= 6, Freq= 0, CH_0, rank 1
5432 22:12:57.812034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5433 22:12:57.812115 ==
5434 22:12:57.815495 RX Vref Scan: 0
5435 22:12:57.815576
5436 22:12:57.815640 RX Vref 0 -> 0, step: 1
5437 22:12:57.815700
5438 22:12:57.818991 RX Delay -53 -> 252, step: 4
5439 22:12:57.826064 iDelay=199, Bit 0, Center 102 (15 ~ 190) 176
5440 22:12:57.829279 iDelay=199, Bit 1, Center 108 (23 ~ 194) 172
5441 22:12:57.832949 iDelay=199, Bit 2, Center 100 (11 ~ 190) 180
5442 22:12:57.835947 iDelay=199, Bit 3, Center 100 (11 ~ 190) 180
5443 22:12:57.839201 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176
5444 22:12:57.845541 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5445 22:12:57.849253 iDelay=199, Bit 6, Center 110 (27 ~ 194) 168
5446 22:12:57.852224 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5447 22:12:57.856147 iDelay=199, Bit 8, Center 86 (3 ~ 170) 168
5448 22:12:57.859106 iDelay=199, Bit 9, Center 86 (3 ~ 170) 168
5449 22:12:57.862682 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5450 22:12:57.868921 iDelay=199, Bit 11, Center 88 (7 ~ 170) 164
5451 22:12:57.872578 iDelay=199, Bit 12, Center 100 (19 ~ 182) 164
5452 22:12:57.875391 iDelay=199, Bit 13, Center 98 (15 ~ 182) 168
5453 22:12:57.878969 iDelay=199, Bit 14, Center 106 (23 ~ 190) 168
5454 22:12:57.885319 iDelay=199, Bit 15, Center 102 (19 ~ 186) 168
5455 22:12:57.885400 ==
5456 22:12:57.888806 Dram Type= 6, Freq= 0, CH_0, rank 1
5457 22:12:57.892531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5458 22:12:57.892613 ==
5459 22:12:57.892678 DQS Delay:
5460 22:12:57.895512 DQS0 = 0, DQS1 = 0
5461 22:12:57.895601 DQM Delay:
5462 22:12:57.898904 DQM0 = 104, DQM1 = 95
5463 22:12:57.898985 DQ Delay:
5464 22:12:57.902290 DQ0 =102, DQ1 =108, DQ2 =100, DQ3 =100
5465 22:12:57.905376 DQ4 =106, DQ5 =98, DQ6 =110, DQ7 =112
5466 22:12:57.908831 DQ8 =86, DQ9 =86, DQ10 =94, DQ11 =88
5467 22:12:57.912166 DQ12 =100, DQ13 =98, DQ14 =106, DQ15 =102
5468 22:12:57.912249
5469 22:12:57.912314
5470 22:12:57.922014 [DQSOSCAuto] RK1, (LSB)MR18= 0x2a02, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 408 ps
5471 22:12:57.922098 CH0 RK1: MR19=505, MR18=2A02
5472 22:12:57.928795 CH0_RK1: MR19=0x505, MR18=0x2A02, DQSOSC=408, MR23=63, INC=65, DEC=43
5473 22:12:57.931986 [RxdqsGatingPostProcess] freq 933
5474 22:12:57.938573 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5475 22:12:57.942152 best DQS0 dly(2T, 0.5T) = (0, 10)
5476 22:12:57.945257 best DQS1 dly(2T, 0.5T) = (0, 11)
5477 22:12:57.948902 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5478 22:12:57.951991 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5479 22:12:57.955150 best DQS0 dly(2T, 0.5T) = (0, 10)
5480 22:12:57.955233 best DQS1 dly(2T, 0.5T) = (0, 10)
5481 22:12:57.958402 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5482 22:12:57.962099 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5483 22:12:57.965233 Pre-setting of DQS Precalculation
5484 22:12:57.971929 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5485 22:12:57.972013 ==
5486 22:12:57.975301 Dram Type= 6, Freq= 0, CH_1, rank 0
5487 22:12:57.978265 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5488 22:12:57.978348 ==
5489 22:12:57.985479 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5490 22:12:57.991764 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5491 22:12:57.995037 [CA 0] Center 36 (6~67) winsize 62
5492 22:12:57.998539 [CA 1] Center 36 (6~67) winsize 62
5493 22:12:58.001675 [CA 2] Center 34 (4~65) winsize 62
5494 22:12:58.005499 [CA 3] Center 34 (4~64) winsize 61
5495 22:12:58.008472 [CA 4] Center 34 (4~65) winsize 62
5496 22:12:58.012004 [CA 5] Center 33 (3~64) winsize 62
5497 22:12:58.012087
5498 22:12:58.015031 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5499 22:12:58.015113
5500 22:12:58.018801 [CATrainingPosCal] consider 1 rank data
5501 22:12:58.021671 u2DelayCellTimex100 = 270/100 ps
5502 22:12:58.024896 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5503 22:12:58.028495 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5504 22:12:58.031773 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5505 22:12:58.034886 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5506 22:12:58.038445 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5507 22:12:58.041651 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5508 22:12:58.041734
5509 22:12:58.048503 CA PerBit enable=1, Macro0, CA PI delay=33
5510 22:12:58.048586
5511 22:12:58.048651 [CBTSetCACLKResult] CA Dly = 33
5512 22:12:58.051581 CS Dly: 7 (0~38)
5513 22:12:58.051664 ==
5514 22:12:58.054718 Dram Type= 6, Freq= 0, CH_1, rank 1
5515 22:12:58.057807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5516 22:12:58.057890 ==
5517 22:12:58.064690 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5518 22:12:58.071539 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5519 22:12:58.075012 [CA 0] Center 36 (6~67) winsize 62
5520 22:12:58.078111 [CA 1] Center 37 (6~68) winsize 63
5521 22:12:58.081156 [CA 2] Center 35 (5~65) winsize 61
5522 22:12:58.084530 [CA 3] Center 34 (4~65) winsize 62
5523 22:12:58.088021 [CA 4] Center 34 (4~65) winsize 62
5524 22:12:58.091465 [CA 5] Center 33 (3~64) winsize 62
5525 22:12:58.091548
5526 22:12:58.094630 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5527 22:12:58.094713
5528 22:12:58.098053 [CATrainingPosCal] consider 2 rank data
5529 22:12:58.101426 u2DelayCellTimex100 = 270/100 ps
5530 22:12:58.104776 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5531 22:12:58.107964 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5532 22:12:58.111180 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5533 22:12:58.114802 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5534 22:12:58.118251 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5535 22:12:58.121344 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5536 22:12:58.124279
5537 22:12:58.128081 CA PerBit enable=1, Macro0, CA PI delay=33
5538 22:12:58.128164
5539 22:12:58.131502 [CBTSetCACLKResult] CA Dly = 33
5540 22:12:58.131585 CS Dly: 7 (0~39)
5541 22:12:58.131650
5542 22:12:58.134418 ----->DramcWriteLeveling(PI) begin...
5543 22:12:58.134502 ==
5544 22:12:58.137744 Dram Type= 6, Freq= 0, CH_1, rank 0
5545 22:12:58.140798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5546 22:12:58.144113 ==
5547 22:12:58.144196 Write leveling (Byte 0): 29 => 29
5548 22:12:58.147854 Write leveling (Byte 1): 29 => 29
5549 22:12:58.151355 DramcWriteLeveling(PI) end<-----
5550 22:12:58.151438
5551 22:12:58.151503 ==
5552 22:12:58.154417 Dram Type= 6, Freq= 0, CH_1, rank 0
5553 22:12:58.160807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5554 22:12:58.160890 ==
5555 22:12:58.164349 [Gating] SW mode calibration
5556 22:12:58.170701 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5557 22:12:58.174583 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5558 22:12:58.180922 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5559 22:12:58.184526 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5560 22:12:58.187382 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5561 22:12:58.191109 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5562 22:12:58.197430 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5563 22:12:58.201001 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5564 22:12:58.204594 0 14 24 | B1->B0 | 3232 2f2f | 1 0 | (1 0) (0 0)
5565 22:12:58.210636 0 14 28 | B1->B0 | 2424 2323 | 1 0 | (1 0) (0 0)
5566 22:12:58.214287 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5567 22:12:58.217431 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5568 22:12:58.224080 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5569 22:12:58.227318 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5570 22:12:58.230950 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5571 22:12:58.237443 0 15 20 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
5572 22:12:58.240710 0 15 24 | B1->B0 | 2626 3434 | 0 0 | (0 0) (0 0)
5573 22:12:58.243982 0 15 28 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
5574 22:12:58.250627 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5575 22:12:58.253795 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5576 22:12:58.257451 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5577 22:12:58.264201 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5578 22:12:58.267343 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5579 22:12:58.270454 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5580 22:12:58.277288 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5581 22:12:58.280497 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5582 22:12:58.283858 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5583 22:12:58.290889 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5584 22:12:58.293754 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5585 22:12:58.297403 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5586 22:12:58.303643 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5587 22:12:58.307314 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5588 22:12:58.310321 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5589 22:12:58.317227 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5590 22:12:58.320300 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5591 22:12:58.323891 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5592 22:12:58.330945 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5593 22:12:58.333950 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5594 22:12:58.336999 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5595 22:12:58.340591 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5596 22:12:58.347263 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5597 22:12:58.350284 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5598 22:12:58.353772 Total UI for P1: 0, mck2ui 16
5599 22:12:58.357305 best dqsien dly found for B0: ( 1, 2, 24)
5600 22:12:58.360268 Total UI for P1: 0, mck2ui 16
5601 22:12:58.363420 best dqsien dly found for B1: ( 1, 2, 24)
5602 22:12:58.366718 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5603 22:12:58.370407 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5604 22:12:58.370491
5605 22:12:58.373413 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5606 22:12:58.376705 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5607 22:12:58.380441 [Gating] SW calibration Done
5608 22:12:58.380523 ==
5609 22:12:58.383493 Dram Type= 6, Freq= 0, CH_1, rank 0
5610 22:12:58.390363 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5611 22:12:58.390446 ==
5612 22:12:58.390512 RX Vref Scan: 0
5613 22:12:58.390573
5614 22:12:58.393331 RX Vref 0 -> 0, step: 1
5615 22:12:58.393414
5616 22:12:58.396857 RX Delay -80 -> 252, step: 8
5617 22:12:58.399962 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5618 22:12:58.403661 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5619 22:12:58.406952 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5620 22:12:58.409985 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5621 22:12:58.413405 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5622 22:12:58.419930 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5623 22:12:58.423265 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5624 22:12:58.426615 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5625 22:12:58.430002 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5626 22:12:58.433167 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5627 22:12:58.436896 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5628 22:12:58.443489 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5629 22:12:58.446582 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5630 22:12:58.449564 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5631 22:12:58.453361 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5632 22:12:58.459570 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5633 22:12:58.459651 ==
5634 22:12:58.463035 Dram Type= 6, Freq= 0, CH_1, rank 0
5635 22:12:58.466621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5636 22:12:58.466703 ==
5637 22:12:58.466769 DQS Delay:
5638 22:12:58.469925 DQS0 = 0, DQS1 = 0
5639 22:12:58.470006 DQM Delay:
5640 22:12:58.473186 DQM0 = 103, DQM1 = 98
5641 22:12:58.473294 DQ Delay:
5642 22:12:58.476278 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5643 22:12:58.480038 DQ4 =99, DQ5 =115, DQ6 =115, DQ7 =103
5644 22:12:58.483217 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =91
5645 22:12:58.486319 DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =107
5646 22:12:58.486399
5647 22:12:58.486463
5648 22:12:58.486522 ==
5649 22:12:58.489449 Dram Type= 6, Freq= 0, CH_1, rank 0
5650 22:12:58.493299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5651 22:12:58.496367 ==
5652 22:12:58.496448
5653 22:12:58.496511
5654 22:12:58.496569 TX Vref Scan disable
5655 22:12:58.499838 == TX Byte 0 ==
5656 22:12:58.503029 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5657 22:12:58.506352 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5658 22:12:58.509246 == TX Byte 1 ==
5659 22:12:58.512796 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5660 22:12:58.516091 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5661 22:12:58.519711 ==
5662 22:12:58.522553 Dram Type= 6, Freq= 0, CH_1, rank 0
5663 22:12:58.525973 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5664 22:12:58.526048 ==
5665 22:12:58.526110
5666 22:12:58.526169
5667 22:12:58.529837 TX Vref Scan disable
5668 22:12:58.529909 == TX Byte 0 ==
5669 22:12:58.535966 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5670 22:12:58.539513 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5671 22:12:58.539595 == TX Byte 1 ==
5672 22:12:58.545933 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5673 22:12:58.549439 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5674 22:12:58.549586
5675 22:12:58.549684 [DATLAT]
5676 22:12:58.552568 Freq=933, CH1 RK0
5677 22:12:58.552651
5678 22:12:58.552716 DATLAT Default: 0xd
5679 22:12:58.556105 0, 0xFFFF, sum = 0
5680 22:12:58.556190 1, 0xFFFF, sum = 0
5681 22:12:58.559177 2, 0xFFFF, sum = 0
5682 22:12:58.559261 3, 0xFFFF, sum = 0
5683 22:12:58.562579 4, 0xFFFF, sum = 0
5684 22:12:58.562663 5, 0xFFFF, sum = 0
5685 22:12:58.565762 6, 0xFFFF, sum = 0
5686 22:12:58.565846 7, 0xFFFF, sum = 0
5687 22:12:58.569278 8, 0xFFFF, sum = 0
5688 22:12:58.572856 9, 0xFFFF, sum = 0
5689 22:12:58.572940 10, 0x0, sum = 1
5690 22:12:58.573007 11, 0x0, sum = 2
5691 22:12:58.575922 12, 0x0, sum = 3
5692 22:12:58.576006 13, 0x0, sum = 4
5693 22:12:58.579155 best_step = 11
5694 22:12:58.579237
5695 22:12:58.579303 ==
5696 22:12:58.582817 Dram Type= 6, Freq= 0, CH_1, rank 0
5697 22:12:58.585957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5698 22:12:58.586040 ==
5699 22:12:58.589053 RX Vref Scan: 1
5700 22:12:58.589135
5701 22:12:58.589200 RX Vref 0 -> 0, step: 1
5702 22:12:58.589261
5703 22:12:58.592728 RX Delay -45 -> 252, step: 4
5704 22:12:58.592810
5705 22:12:58.595806 Set Vref, RX VrefLevel [Byte0]: 54
5706 22:12:58.598913 [Byte1]: 45
5707 22:12:58.602995
5708 22:12:58.603077 Final RX Vref Byte 0 = 54 to rank0
5709 22:12:58.606777 Final RX Vref Byte 1 = 45 to rank0
5710 22:12:58.610114 Final RX Vref Byte 0 = 54 to rank1
5711 22:12:58.612879 Final RX Vref Byte 1 = 45 to rank1==
5712 22:12:58.616719 Dram Type= 6, Freq= 0, CH_1, rank 0
5713 22:12:58.623034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5714 22:12:58.623118 ==
5715 22:12:58.623184 DQS Delay:
5716 22:12:58.623245 DQS0 = 0, DQS1 = 0
5717 22:12:58.626447 DQM Delay:
5718 22:12:58.626529 DQM0 = 103, DQM1 = 99
5719 22:12:58.630186 DQ Delay:
5720 22:12:58.633170 DQ0 =106, DQ1 =96, DQ2 =94, DQ3 =100
5721 22:12:58.636547 DQ4 =102, DQ5 =112, DQ6 =112, DQ7 =102
5722 22:12:58.640377 DQ8 =88, DQ9 =90, DQ10 =100, DQ11 =92
5723 22:12:58.642957 DQ12 =106, DQ13 =106, DQ14 =108, DQ15 =108
5724 22:12:58.643040
5725 22:12:58.643106
5726 22:12:58.649710 [DQSOSCAuto] RK0, (LSB)MR18= 0x162d, (MSB)MR19= 0x505, tDQSOscB0 = 407 ps tDQSOscB1 = 414 ps
5727 22:12:58.653201 CH1 RK0: MR19=505, MR18=162D
5728 22:12:58.659685 CH1_RK0: MR19=0x505, MR18=0x162D, DQSOSC=407, MR23=63, INC=65, DEC=43
5729 22:12:58.659797
5730 22:12:58.663092 ----->DramcWriteLeveling(PI) begin...
5731 22:12:58.663193 ==
5732 22:12:58.666424 Dram Type= 6, Freq= 0, CH_1, rank 1
5733 22:12:58.669378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5734 22:12:58.669479 ==
5735 22:12:58.672968 Write leveling (Byte 0): 29 => 29
5736 22:12:58.676337 Write leveling (Byte 1): 28 => 28
5737 22:12:58.679350 DramcWriteLeveling(PI) end<-----
5738 22:12:58.679448
5739 22:12:58.679538 ==
5740 22:12:58.682988 Dram Type= 6, Freq= 0, CH_1, rank 1
5741 22:12:58.689840 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5742 22:12:58.689924 ==
5743 22:12:58.689990 [Gating] SW mode calibration
5744 22:12:58.699947 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5745 22:12:58.703022 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5746 22:12:58.706805 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5747 22:12:58.713451 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5748 22:12:58.716649 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5749 22:12:58.719582 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5750 22:12:58.726423 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5751 22:12:58.729897 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5752 22:12:58.732702 0 14 24 | B1->B0 | 2e2e 3030 | 1 1 | (1 0) (1 0)
5753 22:12:58.739239 0 14 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5754 22:12:58.742621 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5755 22:12:58.746101 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5756 22:12:58.752686 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5757 22:12:58.756035 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5758 22:12:58.759095 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5759 22:12:58.765671 0 15 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5760 22:12:58.769379 0 15 24 | B1->B0 | 3737 2b2b | 0 0 | (0 0) (0 0)
5761 22:12:58.772252 0 15 28 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
5762 22:12:58.778787 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5763 22:12:58.782209 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5764 22:12:58.785848 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5765 22:12:58.792222 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5766 22:12:58.795240 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5767 22:12:58.798525 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5768 22:12:58.805319 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5769 22:12:58.808913 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5770 22:12:58.812051 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5771 22:12:58.818873 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5772 22:12:58.822106 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5773 22:12:58.825242 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5774 22:12:58.832038 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5775 22:12:58.835660 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5776 22:12:58.838472 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5777 22:12:58.845391 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5778 22:12:58.848730 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5779 22:12:58.852129 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5780 22:12:58.858890 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5781 22:12:58.861681 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5782 22:12:58.865178 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5783 22:12:58.871751 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5784 22:12:58.875103 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5785 22:12:58.878795 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5786 22:12:58.881712 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5787 22:12:58.885072 Total UI for P1: 0, mck2ui 16
5788 22:12:58.888653 best dqsien dly found for B1: ( 1, 2, 26)
5789 22:12:58.895484 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5790 22:12:58.898598 Total UI for P1: 0, mck2ui 16
5791 22:12:58.901857 best dqsien dly found for B0: ( 1, 2, 28)
5792 22:12:58.905337 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5793 22:12:58.908449 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5794 22:12:58.908556
5795 22:12:58.911582 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5796 22:12:58.915314 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5797 22:12:58.918372 [Gating] SW calibration Done
5798 22:12:58.918456 ==
5799 22:12:58.921529 Dram Type= 6, Freq= 0, CH_1, rank 1
5800 22:12:58.925197 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5801 22:12:58.925280 ==
5802 22:12:58.928332 RX Vref Scan: 0
5803 22:12:58.928416
5804 22:12:58.928499 RX Vref 0 -> 0, step: 1
5805 22:12:58.928577
5806 22:12:58.931506 RX Delay -80 -> 252, step: 8
5807 22:12:58.938408 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5808 22:12:58.941628 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5809 22:12:58.945036 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5810 22:12:58.948041 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5811 22:12:58.951615 iDelay=208, Bit 4, Center 95 (8 ~ 183) 176
5812 22:12:58.955054 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5813 22:12:58.961579 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5814 22:12:58.965087 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5815 22:12:58.968567 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5816 22:12:58.971446 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5817 22:12:58.974809 iDelay=208, Bit 10, Center 103 (16 ~ 191) 176
5818 22:12:58.977997 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5819 22:12:58.984742 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5820 22:12:58.988433 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5821 22:12:58.991513 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5822 22:12:58.995100 iDelay=208, Bit 15, Center 103 (16 ~ 191) 176
5823 22:12:58.995182 ==
5824 22:12:58.998133 Dram Type= 6, Freq= 0, CH_1, rank 1
5825 22:12:59.001922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5826 22:12:59.005143 ==
5827 22:12:59.005225 DQS Delay:
5828 22:12:59.005288 DQS0 = 0, DQS1 = 0
5829 22:12:59.008351 DQM Delay:
5830 22:12:59.008432 DQM0 = 102, DQM1 = 97
5831 22:12:59.011429 DQ Delay:
5832 22:12:59.015072 DQ0 =107, DQ1 =99, DQ2 =91, DQ3 =99
5833 22:12:59.018220 DQ4 =95, DQ5 =115, DQ6 =115, DQ7 =99
5834 22:12:59.021270 DQ8 =87, DQ9 =87, DQ10 =103, DQ11 =91
5835 22:12:59.025089 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5836 22:12:59.025171
5837 22:12:59.025235
5838 22:12:59.025294 ==
5839 22:12:59.028185 Dram Type= 6, Freq= 0, CH_1, rank 1
5840 22:12:59.031508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5841 22:12:59.031589 ==
5842 22:12:59.031653
5843 22:12:59.031713
5844 22:12:59.035196 TX Vref Scan disable
5845 22:12:59.038190 == TX Byte 0 ==
5846 22:12:59.042098 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5847 22:12:59.045008 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5848 22:12:59.047950 == TX Byte 1 ==
5849 22:12:59.051471 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5850 22:12:59.054485 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5851 22:12:59.054576 ==
5852 22:12:59.058197 Dram Type= 6, Freq= 0, CH_1, rank 1
5853 22:12:59.061501 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5854 22:12:59.061621 ==
5855 22:12:59.064496
5856 22:12:59.064577
5857 22:12:59.064651 TX Vref Scan disable
5858 22:12:59.068254 == TX Byte 0 ==
5859 22:12:59.071800 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5860 22:12:59.077908 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5861 22:12:59.077990 == TX Byte 1 ==
5862 22:12:59.081157 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5863 22:12:59.088149 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5864 22:12:59.088231
5865 22:12:59.088295 [DATLAT]
5866 22:12:59.088355 Freq=933, CH1 RK1
5867 22:12:59.088413
5868 22:12:59.091185 DATLAT Default: 0xb
5869 22:12:59.091267 0, 0xFFFF, sum = 0
5870 22:12:59.094601 1, 0xFFFF, sum = 0
5871 22:12:59.094684 2, 0xFFFF, sum = 0
5872 22:12:59.097780 3, 0xFFFF, sum = 0
5873 22:12:59.101160 4, 0xFFFF, sum = 0
5874 22:12:59.101242 5, 0xFFFF, sum = 0
5875 22:12:59.104569 6, 0xFFFF, sum = 0
5876 22:12:59.104676 7, 0xFFFF, sum = 0
5877 22:12:59.107610 8, 0xFFFF, sum = 0
5878 22:12:59.107693 9, 0xFFFF, sum = 0
5879 22:12:59.111056 10, 0x0, sum = 1
5880 22:12:59.111139 11, 0x0, sum = 2
5881 22:12:59.114739 12, 0x0, sum = 3
5882 22:12:59.114822 13, 0x0, sum = 4
5883 22:12:59.114889 best_step = 11
5884 22:12:59.114948
5885 22:12:59.117783 ==
5886 22:12:59.121554 Dram Type= 6, Freq= 0, CH_1, rank 1
5887 22:12:59.124497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5888 22:12:59.124580 ==
5889 22:12:59.124645 RX Vref Scan: 0
5890 22:12:59.124705
5891 22:12:59.127785 RX Vref 0 -> 0, step: 1
5892 22:12:59.127867
5893 22:12:59.130846 RX Delay -45 -> 252, step: 4
5894 22:12:59.134757 iDelay=203, Bit 0, Center 110 (27 ~ 194) 168
5895 22:12:59.141405 iDelay=203, Bit 1, Center 98 (15 ~ 182) 168
5896 22:12:59.144472 iDelay=203, Bit 2, Center 94 (11 ~ 178) 168
5897 22:12:59.147597 iDelay=203, Bit 3, Center 100 (19 ~ 182) 164
5898 22:12:59.151156 iDelay=203, Bit 4, Center 100 (19 ~ 182) 164
5899 22:12:59.154891 iDelay=203, Bit 5, Center 118 (35 ~ 202) 168
5900 22:12:59.158164 iDelay=203, Bit 6, Center 114 (31 ~ 198) 168
5901 22:12:59.164445 iDelay=203, Bit 7, Center 102 (19 ~ 186) 168
5902 22:12:59.167954 iDelay=203, Bit 8, Center 90 (7 ~ 174) 168
5903 22:12:59.171006 iDelay=203, Bit 9, Center 90 (7 ~ 174) 168
5904 22:12:59.174650 iDelay=203, Bit 10, Center 96 (11 ~ 182) 172
5905 22:12:59.178159 iDelay=203, Bit 11, Center 92 (7 ~ 178) 172
5906 22:12:59.184445 iDelay=203, Bit 12, Center 108 (23 ~ 194) 172
5907 22:12:59.187749 iDelay=203, Bit 13, Center 104 (23 ~ 186) 164
5908 22:12:59.191428 iDelay=203, Bit 14, Center 104 (23 ~ 186) 164
5909 22:12:59.194346 iDelay=203, Bit 15, Center 108 (23 ~ 194) 172
5910 22:12:59.194429 ==
5911 22:12:59.198029 Dram Type= 6, Freq= 0, CH_1, rank 1
5912 22:12:59.204571 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5913 22:12:59.204655 ==
5914 22:12:59.204728 DQS Delay:
5915 22:12:59.204798 DQS0 = 0, DQS1 = 0
5916 22:12:59.207491 DQM Delay:
5917 22:12:59.207591 DQM0 = 104, DQM1 = 99
5918 22:12:59.210924 DQ Delay:
5919 22:12:59.214620 DQ0 =110, DQ1 =98, DQ2 =94, DQ3 =100
5920 22:12:59.217645 DQ4 =100, DQ5 =118, DQ6 =114, DQ7 =102
5921 22:12:59.221013 DQ8 =90, DQ9 =90, DQ10 =96, DQ11 =92
5922 22:12:59.224018 DQ12 =108, DQ13 =104, DQ14 =104, DQ15 =108
5923 22:12:59.224102
5924 22:12:59.224167
5925 22:12:59.230738 [DQSOSCAuto] RK1, (LSB)MR18= 0x3205, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 406 ps
5926 22:12:59.233983 CH1 RK1: MR19=505, MR18=3205
5927 22:12:59.240850 CH1_RK1: MR19=0x505, MR18=0x3205, DQSOSC=406, MR23=63, INC=65, DEC=43
5928 22:12:59.243922 [RxdqsGatingPostProcess] freq 933
5929 22:12:59.250954 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5930 22:12:59.251037 best DQS0 dly(2T, 0.5T) = (0, 10)
5931 22:12:59.253868 best DQS1 dly(2T, 0.5T) = (0, 10)
5932 22:12:59.257088 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5933 22:12:59.260831 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5934 22:12:59.264353 best DQS0 dly(2T, 0.5T) = (0, 10)
5935 22:12:59.267340 best DQS1 dly(2T, 0.5T) = (0, 10)
5936 22:12:59.270918 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5937 22:12:59.273697 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5938 22:12:59.277493 Pre-setting of DQS Precalculation
5939 22:12:59.283903 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5940 22:12:59.290472 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5941 22:12:59.297205 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5942 22:12:59.297289
5943 22:12:59.297354
5944 22:12:59.300853 [Calibration Summary] 1866 Mbps
5945 22:12:59.300936 CH 0, Rank 0
5946 22:12:59.303784 SW Impedance : PASS
5947 22:12:59.307328 DUTY Scan : NO K
5948 22:12:59.307411 ZQ Calibration : PASS
5949 22:12:59.310800 Jitter Meter : NO K
5950 22:12:59.310902 CBT Training : PASS
5951 22:12:59.313907 Write leveling : PASS
5952 22:12:59.317654 RX DQS gating : PASS
5953 22:12:59.317736 RX DQ/DQS(RDDQC) : PASS
5954 22:12:59.320403 TX DQ/DQS : PASS
5955 22:12:59.323613 RX DATLAT : PASS
5956 22:12:59.323696 RX DQ/DQS(Engine): PASS
5957 22:12:59.327364 TX OE : NO K
5958 22:12:59.327447 All Pass.
5959 22:12:59.327512
5960 22:12:59.330309 CH 0, Rank 1
5961 22:12:59.330419 SW Impedance : PASS
5962 22:12:59.333906 DUTY Scan : NO K
5963 22:12:59.336737 ZQ Calibration : PASS
5964 22:12:59.336819 Jitter Meter : NO K
5965 22:12:59.340478 CBT Training : PASS
5966 22:12:59.343447 Write leveling : PASS
5967 22:12:59.343530 RX DQS gating : PASS
5968 22:12:59.346736 RX DQ/DQS(RDDQC) : PASS
5969 22:12:59.350471 TX DQ/DQS : PASS
5970 22:12:59.350554 RX DATLAT : PASS
5971 22:12:59.353775 RX DQ/DQS(Engine): PASS
5972 22:12:59.356909 TX OE : NO K
5973 22:12:59.356992 All Pass.
5974 22:12:59.357057
5975 22:12:59.357117 CH 1, Rank 0
5976 22:12:59.360256 SW Impedance : PASS
5977 22:12:59.363342 DUTY Scan : NO K
5978 22:12:59.363425 ZQ Calibration : PASS
5979 22:12:59.367079 Jitter Meter : NO K
5980 22:12:59.370159 CBT Training : PASS
5981 22:12:59.370242 Write leveling : PASS
5982 22:12:59.373234 RX DQS gating : PASS
5983 22:12:59.373317 RX DQ/DQS(RDDQC) : PASS
5984 22:12:59.376666 TX DQ/DQS : PASS
5985 22:12:59.380193 RX DATLAT : PASS
5986 22:12:59.380276 RX DQ/DQS(Engine): PASS
5987 22:12:59.383094 TX OE : NO K
5988 22:12:59.383176 All Pass.
5989 22:12:59.383242
5990 22:12:59.386663 CH 1, Rank 1
5991 22:12:59.386776 SW Impedance : PASS
5992 22:12:59.390302 DUTY Scan : NO K
5993 22:12:59.393311 ZQ Calibration : PASS
5994 22:12:59.393393 Jitter Meter : NO K
5995 22:12:59.396836 CBT Training : PASS
5996 22:12:59.399786 Write leveling : PASS
5997 22:12:59.399868 RX DQS gating : PASS
5998 22:12:59.403498 RX DQ/DQS(RDDQC) : PASS
5999 22:12:59.406491 TX DQ/DQS : PASS
6000 22:12:59.406573 RX DATLAT : PASS
6001 22:12:59.410027 RX DQ/DQS(Engine): PASS
6002 22:12:59.413106 TX OE : NO K
6003 22:12:59.413189 All Pass.
6004 22:12:59.413280
6005 22:12:59.413371 DramC Write-DBI off
6006 22:12:59.416660 PER_BANK_REFRESH: Hybrid Mode
6007 22:12:59.419601 TX_TRACKING: ON
6008 22:12:59.426610 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6009 22:12:59.429608 [FAST_K] Save calibration result to emmc
6010 22:12:59.436385 dramc_set_vcore_voltage set vcore to 650000
6011 22:12:59.436497 Read voltage for 400, 6
6012 22:12:59.440160 Vio18 = 0
6013 22:12:59.440262 Vcore = 650000
6014 22:12:59.440355 Vdram = 0
6015 22:12:59.443001 Vddq = 0
6016 22:12:59.443100 Vmddr = 0
6017 22:12:59.446280 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6018 22:12:59.453116 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6019 22:12:59.456234 MEM_TYPE=3, freq_sel=20
6020 22:12:59.456335 sv_algorithm_assistance_LP4_800
6021 22:12:59.462999 ============ PULL DRAM RESETB DOWN ============
6022 22:12:59.466622 ========== PULL DRAM RESETB DOWN end =========
6023 22:12:59.469855 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6024 22:12:59.472819 ===================================
6025 22:12:59.475943 LPDDR4 DRAM CONFIGURATION
6026 22:12:59.479483 ===================================
6027 22:12:59.482956 EX_ROW_EN[0] = 0x0
6028 22:12:59.483056 EX_ROW_EN[1] = 0x0
6029 22:12:59.485991 LP4Y_EN = 0x0
6030 22:12:59.486069 WORK_FSP = 0x0
6031 22:12:59.489208 WL = 0x2
6032 22:12:59.489305 RL = 0x2
6033 22:12:59.492887 BL = 0x2
6034 22:12:59.492985 RPST = 0x0
6035 22:12:59.496082 RD_PRE = 0x0
6036 22:12:59.496179 WR_PRE = 0x1
6037 22:12:59.499135 WR_PST = 0x0
6038 22:12:59.499233 DBI_WR = 0x0
6039 22:12:59.502806 DBI_RD = 0x0
6040 22:12:59.506230 OTF = 0x1
6041 22:12:59.506307 ===================================
6042 22:12:59.509290 ===================================
6043 22:12:59.512592 ANA top config
6044 22:12:59.516054 ===================================
6045 22:12:59.519594 DLL_ASYNC_EN = 0
6046 22:12:59.519693 ALL_SLAVE_EN = 1
6047 22:12:59.522727 NEW_RANK_MODE = 1
6048 22:12:59.525803 DLL_IDLE_MODE = 1
6049 22:12:59.529227 LP45_APHY_COMB_EN = 1
6050 22:12:59.532332 TX_ODT_DIS = 1
6051 22:12:59.532435 NEW_8X_MODE = 1
6052 22:12:59.536040 ===================================
6053 22:12:59.539100 ===================================
6054 22:12:59.542723 data_rate = 800
6055 22:12:59.545885 CKR = 1
6056 22:12:59.549036 DQ_P2S_RATIO = 4
6057 22:12:59.552917 ===================================
6058 22:12:59.555980 CA_P2S_RATIO = 4
6059 22:12:59.556080 DQ_CA_OPEN = 0
6060 22:12:59.559009 DQ_SEMI_OPEN = 1
6061 22:12:59.562763 CA_SEMI_OPEN = 1
6062 22:12:59.565723 CA_FULL_RATE = 0
6063 22:12:59.569329 DQ_CKDIV4_EN = 0
6064 22:12:59.572480 CA_CKDIV4_EN = 1
6065 22:12:59.572577 CA_PREDIV_EN = 0
6066 22:12:59.576336 PH8_DLY = 0
6067 22:12:59.579380 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6068 22:12:59.582536 DQ_AAMCK_DIV = 0
6069 22:12:59.586139 CA_AAMCK_DIV = 0
6070 22:12:59.589080 CA_ADMCK_DIV = 4
6071 22:12:59.589184 DQ_TRACK_CA_EN = 0
6072 22:12:59.592529 CA_PICK = 800
6073 22:12:59.596219 CA_MCKIO = 400
6074 22:12:59.599292 MCKIO_SEMI = 400
6075 22:12:59.602614 PLL_FREQ = 3016
6076 22:12:59.605996 DQ_UI_PI_RATIO = 32
6077 22:12:59.609497 CA_UI_PI_RATIO = 32
6078 22:12:59.612634 ===================================
6079 22:12:59.615707 ===================================
6080 22:12:59.615818 memory_type:LPDDR4
6081 22:12:59.619369 GP_NUM : 10
6082 22:12:59.622466 SRAM_EN : 1
6083 22:12:59.622544 MD32_EN : 0
6084 22:12:59.626072 ===================================
6085 22:12:59.629223 [ANA_INIT] >>>>>>>>>>>>>>
6086 22:12:59.632711 <<<<<< [CONFIGURE PHASE]: ANA_TX
6087 22:12:59.635623 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6088 22:12:59.639345 ===================================
6089 22:12:59.642442 data_rate = 800,PCW = 0X7400
6090 22:12:59.646095 ===================================
6091 22:12:59.649308 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6092 22:12:59.652245 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6093 22:12:59.666010 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6094 22:12:59.669115 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6095 22:12:59.672197 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6096 22:12:59.675791 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6097 22:12:59.678873 [ANA_INIT] flow start
6098 22:12:59.678948 [ANA_INIT] PLL >>>>>>>>
6099 22:12:59.682083 [ANA_INIT] PLL <<<<<<<<
6100 22:12:59.685979 [ANA_INIT] MIDPI >>>>>>>>
6101 22:12:59.688897 [ANA_INIT] MIDPI <<<<<<<<
6102 22:12:59.688999 [ANA_INIT] DLL >>>>>>>>
6103 22:12:59.692480 [ANA_INIT] flow end
6104 22:12:59.695541 ============ LP4 DIFF to SE enter ============
6105 22:12:59.698700 ============ LP4 DIFF to SE exit ============
6106 22:12:59.702310 [ANA_INIT] <<<<<<<<<<<<<
6107 22:12:59.705334 [Flow] Enable top DCM control >>>>>
6108 22:12:59.708947 [Flow] Enable top DCM control <<<<<
6109 22:12:59.712281 Enable DLL master slave shuffle
6110 22:12:59.718272 ==============================================================
6111 22:12:59.718350 Gating Mode config
6112 22:12:59.725123 ==============================================================
6113 22:12:59.725225 Config description:
6114 22:12:59.734703 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6115 22:12:59.741809 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6116 22:12:59.748357 SELPH_MODE 0: By rank 1: By Phase
6117 22:12:59.751357 ==============================================================
6118 22:12:59.755101 GAT_TRACK_EN = 0
6119 22:12:59.758207 RX_GATING_MODE = 2
6120 22:12:59.761328 RX_GATING_TRACK_MODE = 2
6121 22:12:59.765102 SELPH_MODE = 1
6122 22:12:59.768929 PICG_EARLY_EN = 1
6123 22:12:59.771386 VALID_LAT_VALUE = 1
6124 22:12:59.778537 ==============================================================
6125 22:12:59.781849 Enter into Gating configuration >>>>
6126 22:12:59.784916 Exit from Gating configuration <<<<
6127 22:12:59.788080 Enter into DVFS_PRE_config >>>>>
6128 22:12:59.798222 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6129 22:12:59.801186 Exit from DVFS_PRE_config <<<<<
6130 22:12:59.804732 Enter into PICG configuration >>>>
6131 22:12:59.808293 Exit from PICG configuration <<<<
6132 22:12:59.811218 [RX_INPUT] configuration >>>>>
6133 22:12:59.811318 [RX_INPUT] configuration <<<<<
6134 22:12:59.818237 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6135 22:12:59.824726 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6136 22:12:59.828327 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6137 22:12:59.834827 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6138 22:12:59.841018 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6139 22:12:59.848319 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6140 22:12:59.851246 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6141 22:12:59.854716 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6142 22:12:59.861605 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6143 22:12:59.864782 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6144 22:12:59.868491 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6145 22:12:59.871545 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6146 22:12:59.874573 ===================================
6147 22:12:59.877753 LPDDR4 DRAM CONFIGURATION
6148 22:12:59.881187 ===================================
6149 22:12:59.884891 EX_ROW_EN[0] = 0x0
6150 22:12:59.884993 EX_ROW_EN[1] = 0x0
6151 22:12:59.887675 LP4Y_EN = 0x0
6152 22:12:59.887773 WORK_FSP = 0x0
6153 22:12:59.891391 WL = 0x2
6154 22:12:59.891491 RL = 0x2
6155 22:12:59.894556 BL = 0x2
6156 22:12:59.894659 RPST = 0x0
6157 22:12:59.898063 RD_PRE = 0x0
6158 22:12:59.898140 WR_PRE = 0x1
6159 22:12:59.901233 WR_PST = 0x0
6160 22:12:59.904690 DBI_WR = 0x0
6161 22:12:59.904794 DBI_RD = 0x0
6162 22:12:59.907730 OTF = 0x1
6163 22:12:59.911306 ===================================
6164 22:12:59.914299 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6165 22:12:59.917939 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6166 22:12:59.921578 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6167 22:12:59.924683 ===================================
6168 22:12:59.927626 LPDDR4 DRAM CONFIGURATION
6169 22:12:59.930899 ===================================
6170 22:12:59.934620 EX_ROW_EN[0] = 0x10
6171 22:12:59.934728 EX_ROW_EN[1] = 0x0
6172 22:12:59.937631 LP4Y_EN = 0x0
6173 22:12:59.937739 WORK_FSP = 0x0
6174 22:12:59.940753 WL = 0x2
6175 22:12:59.940823 RL = 0x2
6176 22:12:59.944596 BL = 0x2
6177 22:12:59.944693 RPST = 0x0
6178 22:12:59.947683 RD_PRE = 0x0
6179 22:12:59.947781 WR_PRE = 0x1
6180 22:12:59.950801 WR_PST = 0x0
6181 22:12:59.950896 DBI_WR = 0x0
6182 22:12:59.954290 DBI_RD = 0x0
6183 22:12:59.954391 OTF = 0x1
6184 22:12:59.957400 ===================================
6185 22:12:59.964432 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6186 22:12:59.968953 nWR fixed to 30
6187 22:12:59.972203 [ModeRegInit_LP4] CH0 RK0
6188 22:12:59.972305 [ModeRegInit_LP4] CH0 RK1
6189 22:12:59.976105 [ModeRegInit_LP4] CH1 RK0
6190 22:12:59.979118 [ModeRegInit_LP4] CH1 RK1
6191 22:12:59.979189 match AC timing 19
6192 22:12:59.985774 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6193 22:12:59.989537 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6194 22:12:59.992686 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6195 22:12:59.999446 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6196 22:13:00.002571 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6197 22:13:00.002671 ==
6198 22:13:00.005632 Dram Type= 6, Freq= 0, CH_0, rank 0
6199 22:13:00.009300 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6200 22:13:00.009399 ==
6201 22:13:00.015807 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6202 22:13:00.022297 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6203 22:13:00.026020 [CA 0] Center 36 (8~64) winsize 57
6204 22:13:00.028833 [CA 1] Center 36 (8~64) winsize 57
6205 22:13:00.032450 [CA 2] Center 36 (8~64) winsize 57
6206 22:13:00.035378 [CA 3] Center 36 (8~64) winsize 57
6207 22:13:00.035482 [CA 4] Center 36 (8~64) winsize 57
6208 22:13:00.038849 [CA 5] Center 36 (8~64) winsize 57
6209 22:13:00.038951
6210 22:13:00.045008 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6211 22:13:00.045108
6212 22:13:00.048697 [CATrainingPosCal] consider 1 rank data
6213 22:13:00.051784 u2DelayCellTimex100 = 270/100 ps
6214 22:13:00.054786 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6215 22:13:00.058389 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6216 22:13:00.061484 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6217 22:13:00.065001 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6218 22:13:00.068648 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6219 22:13:00.071582 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6220 22:13:00.071683
6221 22:13:00.075148 CA PerBit enable=1, Macro0, CA PI delay=36
6222 22:13:00.075243
6223 22:13:00.078019 [CBTSetCACLKResult] CA Dly = 36
6224 22:13:00.081694 CS Dly: 1 (0~32)
6225 22:13:00.081795 ==
6226 22:13:00.084814 Dram Type= 6, Freq= 0, CH_0, rank 1
6227 22:13:00.087957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6228 22:13:00.088030 ==
6229 22:13:00.094957 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6230 22:13:00.101197 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6231 22:13:00.104420 [CA 0] Center 36 (8~64) winsize 57
6232 22:13:00.108182 [CA 1] Center 36 (8~64) winsize 57
6233 22:13:00.108255 [CA 2] Center 36 (8~64) winsize 57
6234 22:13:00.111131 [CA 3] Center 36 (8~64) winsize 57
6235 22:13:00.114340 [CA 4] Center 36 (8~64) winsize 57
6236 22:13:00.117776 [CA 5] Center 36 (8~64) winsize 57
6237 22:13:00.117846
6238 22:13:00.121263 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6239 22:13:00.124776
6240 22:13:00.127766 [CATrainingPosCal] consider 2 rank data
6241 22:13:00.127862 u2DelayCellTimex100 = 270/100 ps
6242 22:13:00.134874 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6243 22:13:00.137699 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6244 22:13:00.141288 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6245 22:13:00.144600 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6246 22:13:00.147653 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6247 22:13:00.151333 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6248 22:13:00.151418
6249 22:13:00.154183 CA PerBit enable=1, Macro0, CA PI delay=36
6250 22:13:00.154264
6251 22:13:00.157937 [CBTSetCACLKResult] CA Dly = 36
6252 22:13:00.161036 CS Dly: 1 (0~32)
6253 22:13:00.161117
6254 22:13:00.164757 ----->DramcWriteLeveling(PI) begin...
6255 22:13:00.164840 ==
6256 22:13:00.167957 Dram Type= 6, Freq= 0, CH_0, rank 0
6257 22:13:00.171036 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6258 22:13:00.171118 ==
6259 22:13:00.174474 Write leveling (Byte 0): 40 => 8
6260 22:13:00.177958 Write leveling (Byte 1): 40 => 8
6261 22:13:00.181382 DramcWriteLeveling(PI) end<-----
6262 22:13:00.181489
6263 22:13:00.181598 ==
6264 22:13:00.185015 Dram Type= 6, Freq= 0, CH_0, rank 0
6265 22:13:00.188203 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6266 22:13:00.188284 ==
6267 22:13:00.191168 [Gating] SW mode calibration
6268 22:13:00.197909 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6269 22:13:00.204179 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6270 22:13:00.207859 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6271 22:13:00.211097 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6272 22:13:00.217304 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6273 22:13:00.220961 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6274 22:13:00.223947 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6275 22:13:00.230540 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6276 22:13:00.234187 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6277 22:13:00.237106 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6278 22:13:00.244052 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6279 22:13:00.244134 Total UI for P1: 0, mck2ui 16
6280 22:13:00.250570 best dqsien dly found for B0: ( 0, 14, 24)
6281 22:13:00.250652 Total UI for P1: 0, mck2ui 16
6282 22:13:00.254084 best dqsien dly found for B1: ( 0, 14, 24)
6283 22:13:00.260791 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6284 22:13:00.264064 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6285 22:13:00.264146
6286 22:13:00.267602 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6287 22:13:00.270818 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6288 22:13:00.273857 [Gating] SW calibration Done
6289 22:13:00.273962 ==
6290 22:13:00.277687 Dram Type= 6, Freq= 0, CH_0, rank 0
6291 22:13:00.280440 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6292 22:13:00.280522 ==
6293 22:13:00.283579 RX Vref Scan: 0
6294 22:13:00.283659
6295 22:13:00.283721 RX Vref 0 -> 0, step: 1
6296 22:13:00.283780
6297 22:13:00.287263 RX Delay -410 -> 252, step: 16
6298 22:13:00.293902 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6299 22:13:00.296933 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6300 22:13:00.300733 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6301 22:13:00.303758 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6302 22:13:00.306987 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6303 22:13:00.313800 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6304 22:13:00.316993 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6305 22:13:00.320588 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6306 22:13:00.323790 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6307 22:13:00.330485 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6308 22:13:00.333674 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6309 22:13:00.337271 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6310 22:13:00.340817 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6311 22:13:00.347269 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6312 22:13:00.350246 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6313 22:13:00.353839 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6314 22:13:00.353945 ==
6315 22:13:00.357722 Dram Type= 6, Freq= 0, CH_0, rank 0
6316 22:13:00.363683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6317 22:13:00.363763 ==
6318 22:13:00.363825 DQS Delay:
6319 22:13:00.367368 DQS0 = 27, DQS1 = 35
6320 22:13:00.367447 DQM Delay:
6321 22:13:00.367509 DQM0 = 10, DQM1 = 11
6322 22:13:00.370281 DQ Delay:
6323 22:13:00.373966 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6324 22:13:00.374079 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6325 22:13:00.376980 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6326 22:13:00.380712 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6327 22:13:00.383599
6328 22:13:00.383678
6329 22:13:00.383739 ==
6330 22:13:00.386726 Dram Type= 6, Freq= 0, CH_0, rank 0
6331 22:13:00.390226 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6332 22:13:00.390306 ==
6333 22:13:00.390371
6334 22:13:00.390428
6335 22:13:00.393638 TX Vref Scan disable
6336 22:13:00.393717 == TX Byte 0 ==
6337 22:13:00.397238 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6338 22:13:00.403754 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6339 22:13:00.403833 == TX Byte 1 ==
6340 22:13:00.406786 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6341 22:13:00.413760 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6342 22:13:00.413839 ==
6343 22:13:00.416768 Dram Type= 6, Freq= 0, CH_0, rank 0
6344 22:13:00.420504 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6345 22:13:00.420583 ==
6346 22:13:00.420646
6347 22:13:00.420703
6348 22:13:00.423786 TX Vref Scan disable
6349 22:13:00.423865 == TX Byte 0 ==
6350 22:13:00.426874 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6351 22:13:00.433424 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6352 22:13:00.433504 == TX Byte 1 ==
6353 22:13:00.436583 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6354 22:13:00.443904 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6355 22:13:00.443984
6356 22:13:00.444045 [DATLAT]
6357 22:13:00.444103 Freq=400, CH0 RK0
6358 22:13:00.444171
6359 22:13:00.447092 DATLAT Default: 0xf
6360 22:13:00.447171 0, 0xFFFF, sum = 0
6361 22:13:00.450508 1, 0xFFFF, sum = 0
6362 22:13:00.453590 2, 0xFFFF, sum = 0
6363 22:13:00.453672 3, 0xFFFF, sum = 0
6364 22:13:00.456873 4, 0xFFFF, sum = 0
6365 22:13:00.456955 5, 0xFFFF, sum = 0
6366 22:13:00.460440 6, 0xFFFF, sum = 0
6367 22:13:00.460522 7, 0xFFFF, sum = 0
6368 22:13:00.464107 8, 0xFFFF, sum = 0
6369 22:13:00.464190 9, 0xFFFF, sum = 0
6370 22:13:00.466969 10, 0xFFFF, sum = 0
6371 22:13:00.467052 11, 0xFFFF, sum = 0
6372 22:13:00.470491 12, 0xFFFF, sum = 0
6373 22:13:00.470574 13, 0x0, sum = 1
6374 22:13:00.473473 14, 0x0, sum = 2
6375 22:13:00.473600 15, 0x0, sum = 3
6376 22:13:00.477345 16, 0x0, sum = 4
6377 22:13:00.477427 best_step = 14
6378 22:13:00.477491
6379 22:13:00.477591 ==
6380 22:13:00.480132 Dram Type= 6, Freq= 0, CH_0, rank 0
6381 22:13:00.483792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6382 22:13:00.486888 ==
6383 22:13:00.486968 RX Vref Scan: 1
6384 22:13:00.487033
6385 22:13:00.490691 RX Vref 0 -> 0, step: 1
6386 22:13:00.490772
6387 22:13:00.493466 RX Delay -311 -> 252, step: 8
6388 22:13:00.493593
6389 22:13:00.497177 Set Vref, RX VrefLevel [Byte0]: 55
6390 22:13:00.500056 [Byte1]: 53
6391 22:13:00.500137
6392 22:13:00.503284 Final RX Vref Byte 0 = 55 to rank0
6393 22:13:00.506770 Final RX Vref Byte 1 = 53 to rank0
6394 22:13:00.509922 Final RX Vref Byte 0 = 55 to rank1
6395 22:13:00.513000 Final RX Vref Byte 1 = 53 to rank1==
6396 22:13:00.516259 Dram Type= 6, Freq= 0, CH_0, rank 0
6397 22:13:00.519870 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6398 22:13:00.519952 ==
6399 22:13:00.523487 DQS Delay:
6400 22:13:00.523567 DQS0 = 28, DQS1 = 36
6401 22:13:00.526657 DQM Delay:
6402 22:13:00.526738 DQM0 = 10, DQM1 = 13
6403 22:13:00.526802 DQ Delay:
6404 22:13:00.529639 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6405 22:13:00.533481 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6406 22:13:00.536539 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6407 22:13:00.539415 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6408 22:13:00.539496
6409 22:13:00.539560
6410 22:13:00.549803 [DQSOSCAuto] RK0, (LSB)MR18= 0xd2bf, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 383 ps
6411 22:13:00.552745 CH0 RK0: MR19=C0C, MR18=D2BF
6412 22:13:00.556291 CH0_RK0: MR19=0xC0C, MR18=0xD2BF, DQSOSC=383, MR23=63, INC=402, DEC=268
6413 22:13:00.559894 ==
6414 22:13:00.562855 Dram Type= 6, Freq= 0, CH_0, rank 1
6415 22:13:00.566167 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6416 22:13:00.566248 ==
6417 22:13:00.569385 [Gating] SW mode calibration
6418 22:13:00.575865 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6419 22:13:00.579562 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6420 22:13:00.586365 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6421 22:13:00.589229 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6422 22:13:00.592321 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6423 22:13:00.599230 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6424 22:13:00.602937 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6425 22:13:00.605929 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6426 22:13:00.612700 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6427 22:13:00.615853 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6428 22:13:00.619104 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6429 22:13:00.622766 Total UI for P1: 0, mck2ui 16
6430 22:13:00.625882 best dqsien dly found for B0: ( 0, 14, 24)
6431 22:13:00.629280 Total UI for P1: 0, mck2ui 16
6432 22:13:00.632352 best dqsien dly found for B1: ( 0, 14, 24)
6433 22:13:00.636185 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6434 22:13:00.639262 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6435 22:13:00.639343
6436 22:13:00.645467 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6437 22:13:00.649277 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6438 22:13:00.652184 [Gating] SW calibration Done
6439 22:13:00.652264 ==
6440 22:13:00.655781 Dram Type= 6, Freq= 0, CH_0, rank 1
6441 22:13:00.658847 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6442 22:13:00.658928 ==
6443 22:13:00.658993 RX Vref Scan: 0
6444 22:13:00.659051
6445 22:13:00.662318 RX Vref 0 -> 0, step: 1
6446 22:13:00.662399
6447 22:13:00.665456 RX Delay -410 -> 252, step: 16
6448 22:13:00.668708 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6449 22:13:00.675751 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6450 22:13:00.678756 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6451 22:13:00.682454 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6452 22:13:00.685450 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6453 22:13:00.692250 iDelay=230, Bit 5, Center -19 (-250 ~ 213) 464
6454 22:13:00.695694 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6455 22:13:00.698694 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6456 22:13:00.702417 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6457 22:13:00.705434 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6458 22:13:00.711941 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6459 22:13:00.715296 iDelay=230, Bit 11, Center -27 (-250 ~ 197) 448
6460 22:13:00.718898 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6461 22:13:00.725632 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6462 22:13:00.728632 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6463 22:13:00.731812 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6464 22:13:00.731894 ==
6465 22:13:00.735659 Dram Type= 6, Freq= 0, CH_0, rank 1
6466 22:13:00.738585 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6467 22:13:00.738667 ==
6468 22:13:00.742326 DQS Delay:
6469 22:13:00.742433 DQS0 = 19, DQS1 = 35
6470 22:13:00.745200 DQM Delay:
6471 22:13:00.745281 DQM0 = 5, DQM1 = 12
6472 22:13:00.748435 DQ Delay:
6473 22:13:00.748516 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6474 22:13:00.752145 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6475 22:13:00.755255 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6476 22:13:00.758999 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6477 22:13:00.759080
6478 22:13:00.759142
6479 22:13:00.759201 ==
6480 22:13:00.761865 Dram Type= 6, Freq= 0, CH_0, rank 1
6481 22:13:00.768468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6482 22:13:00.768551 ==
6483 22:13:00.768616
6484 22:13:00.768674
6485 22:13:00.768731 TX Vref Scan disable
6486 22:13:00.772080 == TX Byte 0 ==
6487 22:13:00.775131 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6488 22:13:00.778571 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6489 22:13:00.781830 == TX Byte 1 ==
6490 22:13:00.785484 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6491 22:13:00.788456 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6492 22:13:00.788566 ==
6493 22:13:00.792189 Dram Type= 6, Freq= 0, CH_0, rank 1
6494 22:13:00.798330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6495 22:13:00.798441 ==
6496 22:13:00.798525
6497 22:13:00.798585
6498 22:13:00.798641 TX Vref Scan disable
6499 22:13:00.802055 == TX Byte 0 ==
6500 22:13:00.805626 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6501 22:13:00.808825 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6502 22:13:00.812490 == TX Byte 1 ==
6503 22:13:00.815379 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6504 22:13:00.818305 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6505 22:13:00.818387
6506 22:13:00.821665 [DATLAT]
6507 22:13:00.821750 Freq=400, CH0 RK1
6508 22:13:00.821835
6509 22:13:00.825065 DATLAT Default: 0xe
6510 22:13:00.825150 0, 0xFFFF, sum = 0
6511 22:13:00.828886 1, 0xFFFF, sum = 0
6512 22:13:00.828973 2, 0xFFFF, sum = 0
6513 22:13:00.832085 3, 0xFFFF, sum = 0
6514 22:13:00.832172 4, 0xFFFF, sum = 0
6515 22:13:00.835005 5, 0xFFFF, sum = 0
6516 22:13:00.835117 6, 0xFFFF, sum = 0
6517 22:13:00.838748 7, 0xFFFF, sum = 0
6518 22:13:00.838834 8, 0xFFFF, sum = 0
6519 22:13:00.841833 9, 0xFFFF, sum = 0
6520 22:13:00.841920 10, 0xFFFF, sum = 0
6521 22:13:00.845040 11, 0xFFFF, sum = 0
6522 22:13:00.845126 12, 0xFFFF, sum = 0
6523 22:13:00.848447 13, 0x0, sum = 1
6524 22:13:00.848533 14, 0x0, sum = 2
6525 22:13:00.851565 15, 0x0, sum = 3
6526 22:13:00.851651 16, 0x0, sum = 4
6527 22:13:00.854786 best_step = 14
6528 22:13:00.854870
6529 22:13:00.854954 ==
6530 22:13:00.858296 Dram Type= 6, Freq= 0, CH_0, rank 1
6531 22:13:00.861669 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6532 22:13:00.861754 ==
6533 22:13:00.865257 RX Vref Scan: 0
6534 22:13:00.865366
6535 22:13:00.865469 RX Vref 0 -> 0, step: 1
6536 22:13:00.865563
6537 22:13:00.868290 RX Delay -311 -> 252, step: 8
6538 22:13:00.876366 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6539 22:13:00.880031 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6540 22:13:00.883436 iDelay=217, Bit 2, Center -16 (-239 ~ 208) 448
6541 22:13:00.886385 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6542 22:13:00.893440 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6543 22:13:00.896690 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6544 22:13:00.899528 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6545 22:13:00.903199 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6546 22:13:00.909837 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6547 22:13:00.912823 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6548 22:13:00.915966 iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440
6549 22:13:00.919354 iDelay=217, Bit 11, Center -28 (-247 ~ 192) 440
6550 22:13:00.925991 iDelay=217, Bit 12, Center -20 (-239 ~ 200) 440
6551 22:13:00.929327 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6552 22:13:00.933142 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440
6553 22:13:00.939185 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6554 22:13:00.939270 ==
6555 22:13:00.943113 Dram Type= 6, Freq= 0, CH_0, rank 1
6556 22:13:00.946014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6557 22:13:00.946098 ==
6558 22:13:00.946162 DQS Delay:
6559 22:13:00.949278 DQS0 = 24, DQS1 = 32
6560 22:13:00.949360 DQM Delay:
6561 22:13:00.952657 DQM0 = 8, DQM1 = 10
6562 22:13:00.952738 DQ Delay:
6563 22:13:00.956431 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6564 22:13:00.959420 DQ4 =8, DQ5 =0, DQ6 =12, DQ7 =16
6565 22:13:00.962471 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6566 22:13:00.966255 DQ12 =12, DQ13 =16, DQ14 =20, DQ15 =16
6567 22:13:00.966371
6568 22:13:00.966473
6569 22:13:00.972884 [DQSOSCAuto] RK1, (LSB)MR18= 0xbe5d, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 386 ps
6570 22:13:00.976398 CH0 RK1: MR19=C0C, MR18=BE5D
6571 22:13:00.982910 CH0_RK1: MR19=0xC0C, MR18=0xBE5D, DQSOSC=386, MR23=63, INC=396, DEC=264
6572 22:13:00.985956 [RxdqsGatingPostProcess] freq 400
6573 22:13:00.989404 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6574 22:13:00.992931 best DQS0 dly(2T, 0.5T) = (0, 10)
6575 22:13:00.996388 best DQS1 dly(2T, 0.5T) = (0, 10)
6576 22:13:00.999954 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6577 22:13:01.002904 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6578 22:13:01.006055 best DQS0 dly(2T, 0.5T) = (0, 10)
6579 22:13:01.009232 best DQS1 dly(2T, 0.5T) = (0, 10)
6580 22:13:01.013115 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6581 22:13:01.016112 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6582 22:13:01.019208 Pre-setting of DQS Precalculation
6583 22:13:01.022784 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6584 22:13:01.022868 ==
6585 22:13:01.026175 Dram Type= 6, Freq= 0, CH_1, rank 0
6586 22:13:01.032644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6587 22:13:01.032754 ==
6588 22:13:01.036087 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6589 22:13:01.042401 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6590 22:13:01.046195 [CA 0] Center 36 (8~64) winsize 57
6591 22:13:01.049324 [CA 1] Center 36 (8~64) winsize 57
6592 22:13:01.052501 [CA 2] Center 36 (8~64) winsize 57
6593 22:13:01.055811 [CA 3] Center 36 (8~64) winsize 57
6594 22:13:01.059343 [CA 4] Center 36 (8~64) winsize 57
6595 22:13:01.062507 [CA 5] Center 36 (8~64) winsize 57
6596 22:13:01.062614
6597 22:13:01.065628 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6598 22:13:01.065752
6599 22:13:01.068833 [CATrainingPosCal] consider 1 rank data
6600 22:13:01.072658 u2DelayCellTimex100 = 270/100 ps
6601 22:13:01.075675 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6602 22:13:01.079405 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6603 22:13:01.082431 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6604 22:13:01.086242 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6605 22:13:01.089229 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6606 22:13:01.092454 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6607 22:13:01.095985
6608 22:13:01.099029 CA PerBit enable=1, Macro0, CA PI delay=36
6609 22:13:01.099173
6610 22:13:01.102469 [CBTSetCACLKResult] CA Dly = 36
6611 22:13:01.102579 CS Dly: 1 (0~32)
6612 22:13:01.102684 ==
6613 22:13:01.105459 Dram Type= 6, Freq= 0, CH_1, rank 1
6614 22:13:01.109057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6615 22:13:01.109197 ==
6616 22:13:01.115813 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6617 22:13:01.122080 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6618 22:13:01.125959 [CA 0] Center 36 (8~64) winsize 57
6619 22:13:01.128840 [CA 1] Center 36 (8~64) winsize 57
6620 22:13:01.132585 [CA 2] Center 36 (8~64) winsize 57
6621 22:13:01.135529 [CA 3] Center 36 (8~64) winsize 57
6622 22:13:01.139169 [CA 4] Center 36 (8~64) winsize 57
6623 22:13:01.139250 [CA 5] Center 36 (8~64) winsize 57
6624 22:13:01.141869
6625 22:13:01.145525 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6626 22:13:01.145603
6627 22:13:01.149213 [CATrainingPosCal] consider 2 rank data
6628 22:13:01.152391 u2DelayCellTimex100 = 270/100 ps
6629 22:13:01.155494 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6630 22:13:01.158638 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6631 22:13:01.162296 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6632 22:13:01.165503 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6633 22:13:01.169305 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6634 22:13:01.172410 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6635 22:13:01.172485
6636 22:13:01.175415 CA PerBit enable=1, Macro0, CA PI delay=36
6637 22:13:01.175496
6638 22:13:01.178452 [CBTSetCACLKResult] CA Dly = 36
6639 22:13:01.182122 CS Dly: 1 (0~32)
6640 22:13:01.182205
6641 22:13:01.185726 ----->DramcWriteLeveling(PI) begin...
6642 22:13:01.185817 ==
6643 22:13:01.188665 Dram Type= 6, Freq= 0, CH_1, rank 0
6644 22:13:01.192321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6645 22:13:01.192403 ==
6646 22:13:01.195338 Write leveling (Byte 0): 40 => 8
6647 22:13:01.198602 Write leveling (Byte 1): 40 => 8
6648 22:13:01.202232 DramcWriteLeveling(PI) end<-----
6649 22:13:01.202324
6650 22:13:01.202392 ==
6651 22:13:01.205709 Dram Type= 6, Freq= 0, CH_1, rank 0
6652 22:13:01.208681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6653 22:13:01.208787 ==
6654 22:13:01.211846 [Gating] SW mode calibration
6655 22:13:01.218857 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6656 22:13:01.225619 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6657 22:13:01.228789 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6658 22:13:01.232413 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6659 22:13:01.238978 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6660 22:13:01.242108 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6661 22:13:01.245335 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6662 22:13:01.252110 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6663 22:13:01.255189 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6664 22:13:01.258393 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6665 22:13:01.265264 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6666 22:13:01.268469 Total UI for P1: 0, mck2ui 16
6667 22:13:01.271524 best dqsien dly found for B0: ( 0, 14, 24)
6668 22:13:01.275349 Total UI for P1: 0, mck2ui 16
6669 22:13:01.278502 best dqsien dly found for B1: ( 0, 14, 24)
6670 22:13:01.281468 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6671 22:13:01.285021 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6672 22:13:01.285126
6673 22:13:01.288164 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6674 22:13:01.291858 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6675 22:13:01.295131 [Gating] SW calibration Done
6676 22:13:01.295233 ==
6677 22:13:01.298137 Dram Type= 6, Freq= 0, CH_1, rank 0
6678 22:13:01.301838 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6679 22:13:01.301944 ==
6680 22:13:01.304796 RX Vref Scan: 0
6681 22:13:01.304898
6682 22:13:01.304989 RX Vref 0 -> 0, step: 1
6683 22:13:01.308535
6684 22:13:01.308635 RX Delay -410 -> 252, step: 16
6685 22:13:01.314882 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6686 22:13:01.318528 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6687 22:13:01.321521 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6688 22:13:01.325182 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6689 22:13:01.331634 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6690 22:13:01.335097 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6691 22:13:01.338252 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6692 22:13:01.341913 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6693 22:13:01.348401 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6694 22:13:01.351385 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6695 22:13:01.354950 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6696 22:13:01.357811 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6697 22:13:01.364796 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6698 22:13:01.367931 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6699 22:13:01.371496 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6700 22:13:01.374675 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6701 22:13:01.378397 ==
6702 22:13:01.381667 Dram Type= 6, Freq= 0, CH_1, rank 0
6703 22:13:01.384578 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6704 22:13:01.384663 ==
6705 22:13:01.384749 DQS Delay:
6706 22:13:01.388304 DQS0 = 35, DQS1 = 35
6707 22:13:01.388389 DQM Delay:
6708 22:13:01.391346 DQM0 = 17, DQM1 = 13
6709 22:13:01.391431 DQ Delay:
6710 22:13:01.394945 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =16
6711 22:13:01.397870 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6712 22:13:01.401495 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6713 22:13:01.404834 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6714 22:13:01.404929
6715 22:13:01.405035
6716 22:13:01.405114 ==
6717 22:13:01.407918 Dram Type= 6, Freq= 0, CH_1, rank 0
6718 22:13:01.411086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6719 22:13:01.411186 ==
6720 22:13:01.411304
6721 22:13:01.411434
6722 22:13:01.414804 TX Vref Scan disable
6723 22:13:01.414928 == TX Byte 0 ==
6724 22:13:01.421385 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6725 22:13:01.424473 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6726 22:13:01.424616 == TX Byte 1 ==
6727 22:13:01.431563 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6728 22:13:01.434570 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6729 22:13:01.434692 ==
6730 22:13:01.437911 Dram Type= 6, Freq= 0, CH_1, rank 0
6731 22:13:01.441417 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6732 22:13:01.441581 ==
6733 22:13:01.441654
6734 22:13:01.441716
6735 22:13:01.444511 TX Vref Scan disable
6736 22:13:01.444582 == TX Byte 0 ==
6737 22:13:01.451172 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6738 22:13:01.454569 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6739 22:13:01.454662 == TX Byte 1 ==
6740 22:13:01.460999 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6741 22:13:01.464755 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6742 22:13:01.464840
6743 22:13:01.464907 [DATLAT]
6744 22:13:01.467898 Freq=400, CH1 RK0
6745 22:13:01.467982
6746 22:13:01.468048 DATLAT Default: 0xf
6747 22:13:01.470940 0, 0xFFFF, sum = 0
6748 22:13:01.471025 1, 0xFFFF, sum = 0
6749 22:13:01.474468 2, 0xFFFF, sum = 0
6750 22:13:01.474553 3, 0xFFFF, sum = 0
6751 22:13:01.477621 4, 0xFFFF, sum = 0
6752 22:13:01.477708 5, 0xFFFF, sum = 0
6753 22:13:01.481485 6, 0xFFFF, sum = 0
6754 22:13:01.481565 7, 0xFFFF, sum = 0
6755 22:13:01.484496 8, 0xFFFF, sum = 0
6756 22:13:01.484581 9, 0xFFFF, sum = 0
6757 22:13:01.487649 10, 0xFFFF, sum = 0
6758 22:13:01.491503 11, 0xFFFF, sum = 0
6759 22:13:01.491588 12, 0xFFFF, sum = 0
6760 22:13:01.494478 13, 0x0, sum = 1
6761 22:13:01.494564 14, 0x0, sum = 2
6762 22:13:01.494631 15, 0x0, sum = 3
6763 22:13:01.498027 16, 0x0, sum = 4
6764 22:13:01.498113 best_step = 14
6765 22:13:01.498194
6766 22:13:01.501010 ==
6767 22:13:01.501094 Dram Type= 6, Freq= 0, CH_1, rank 0
6768 22:13:01.507690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6769 22:13:01.507778 ==
6770 22:13:01.507850 RX Vref Scan: 1
6771 22:13:01.507947
6772 22:13:01.510898 RX Vref 0 -> 0, step: 1
6773 22:13:01.511007
6774 22:13:01.514631 RX Delay -311 -> 252, step: 8
6775 22:13:01.514742
6776 22:13:01.518103 Set Vref, RX VrefLevel [Byte0]: 54
6777 22:13:01.520653 [Byte1]: 45
6778 22:13:01.524105
6779 22:13:01.524215 Final RX Vref Byte 0 = 54 to rank0
6780 22:13:01.527894 Final RX Vref Byte 1 = 45 to rank0
6781 22:13:01.530610 Final RX Vref Byte 0 = 54 to rank1
6782 22:13:01.534411 Final RX Vref Byte 1 = 45 to rank1==
6783 22:13:01.537445 Dram Type= 6, Freq= 0, CH_1, rank 0
6784 22:13:01.543776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6785 22:13:01.543883 ==
6786 22:13:01.543954 DQS Delay:
6787 22:13:01.547391 DQS0 = 28, DQS1 = 32
6788 22:13:01.547508 DQM Delay:
6789 22:13:01.547612 DQM0 = 10, DQM1 = 11
6790 22:13:01.550497 DQ Delay:
6791 22:13:01.554151 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =12
6792 22:13:01.554227 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =8
6793 22:13:01.557236 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6794 22:13:01.560770 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =20
6795 22:13:01.560897
6796 22:13:01.564192
6797 22:13:01.570753 [DQSOSCAuto] RK0, (LSB)MR18= 0x95cd, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 391 ps
6798 22:13:01.574088 CH1 RK0: MR19=C0C, MR18=95CD
6799 22:13:01.580947 CH1_RK0: MR19=0xC0C, MR18=0x95CD, DQSOSC=384, MR23=63, INC=400, DEC=267
6800 22:13:01.581036 ==
6801 22:13:01.584062 Dram Type= 6, Freq= 0, CH_1, rank 1
6802 22:13:01.587229 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6803 22:13:01.587316 ==
6804 22:13:01.591206 [Gating] SW mode calibration
6805 22:13:01.608282 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6806 22:13:01.608406 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6807 22:13:01.608512 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6808 22:13:01.610464 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6809 22:13:01.614344 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6810 22:13:01.620779 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6811 22:13:01.624036 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6812 22:13:01.627787 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6813 22:13:01.634242 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6814 22:13:01.637181 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6815 22:13:01.640721 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6816 22:13:01.643992 Total UI for P1: 0, mck2ui 16
6817 22:13:01.647802 best dqsien dly found for B0: ( 0, 14, 24)
6818 22:13:01.650703 Total UI for P1: 0, mck2ui 16
6819 22:13:01.654357 best dqsien dly found for B1: ( 0, 14, 24)
6820 22:13:01.657514 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6821 22:13:01.660577 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6822 22:13:01.660694
6823 22:13:01.667547 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6824 22:13:01.670392 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6825 22:13:01.673912 [Gating] SW calibration Done
6826 22:13:01.673990 ==
6827 22:13:01.677655 Dram Type= 6, Freq= 0, CH_1, rank 1
6828 22:13:01.680682 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6829 22:13:01.680784 ==
6830 22:13:01.680885 RX Vref Scan: 0
6831 22:13:01.680975
6832 22:13:01.683722 RX Vref 0 -> 0, step: 1
6833 22:13:01.683824
6834 22:13:01.687579 RX Delay -410 -> 252, step: 16
6835 22:13:01.690787 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6836 22:13:01.697614 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6837 22:13:01.700727 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6838 22:13:01.703927 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6839 22:13:01.707407 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6840 22:13:01.710996 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6841 22:13:01.717112 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6842 22:13:01.720808 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6843 22:13:01.724017 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6844 22:13:01.727772 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6845 22:13:01.733736 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6846 22:13:01.737298 iDelay=230, Bit 11, Center -19 (-250 ~ 213) 464
6847 22:13:01.740194 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6848 22:13:01.747004 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6849 22:13:01.750512 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6850 22:13:01.753732 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6851 22:13:01.753899 ==
6852 22:13:01.756904 Dram Type= 6, Freq= 0, CH_1, rank 1
6853 22:13:01.760428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6854 22:13:01.760560 ==
6855 22:13:01.763530 DQS Delay:
6856 22:13:01.763620 DQS0 = 35, DQS1 = 35
6857 22:13:01.766901 DQM Delay:
6858 22:13:01.766993 DQM0 = 18, DQM1 = 14
6859 22:13:01.767060 DQ Delay:
6860 22:13:01.770381 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6861 22:13:01.773959 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6862 22:13:01.777004 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6863 22:13:01.780333 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6864 22:13:01.780463
6865 22:13:01.780587
6866 22:13:01.780702 ==
6867 22:13:01.784046 Dram Type= 6, Freq= 0, CH_1, rank 1
6868 22:13:01.790926 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6869 22:13:01.791012 ==
6870 22:13:01.791079
6871 22:13:01.791138
6872 22:13:01.794026 TX Vref Scan disable
6873 22:13:01.794113 == TX Byte 0 ==
6874 22:13:01.797289 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6875 22:13:01.800323 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6876 22:13:01.803902 == TX Byte 1 ==
6877 22:13:01.806858 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6878 22:13:01.810584 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6879 22:13:01.813784 ==
6880 22:13:01.813898 Dram Type= 6, Freq= 0, CH_1, rank 1
6881 22:13:01.820349 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6882 22:13:01.820449 ==
6883 22:13:01.820564
6884 22:13:01.820658
6885 22:13:01.823608 TX Vref Scan disable
6886 22:13:01.823789 == TX Byte 0 ==
6887 22:13:01.826850 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6888 22:13:01.830531 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6889 22:13:01.833677 == TX Byte 1 ==
6890 22:13:01.836927 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6891 22:13:01.840192 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6892 22:13:01.840278
6893 22:13:01.843843 [DATLAT]
6894 22:13:01.843949 Freq=400, CH1 RK1
6895 22:13:01.844047
6896 22:13:01.847008 DATLAT Default: 0xe
6897 22:13:01.847093 0, 0xFFFF, sum = 0
6898 22:13:01.850115 1, 0xFFFF, sum = 0
6899 22:13:01.850203 2, 0xFFFF, sum = 0
6900 22:13:01.853943 3, 0xFFFF, sum = 0
6901 22:13:01.854061 4, 0xFFFF, sum = 0
6902 22:13:01.857195 5, 0xFFFF, sum = 0
6903 22:13:01.860255 6, 0xFFFF, sum = 0
6904 22:13:01.860372 7, 0xFFFF, sum = 0
6905 22:13:01.863453 8, 0xFFFF, sum = 0
6906 22:13:01.863572 9, 0xFFFF, sum = 0
6907 22:13:01.867025 10, 0xFFFF, sum = 0
6908 22:13:01.867115 11, 0xFFFF, sum = 0
6909 22:13:01.870175 12, 0xFFFF, sum = 0
6910 22:13:01.870256 13, 0x0, sum = 1
6911 22:13:01.873789 14, 0x0, sum = 2
6912 22:13:01.873868 15, 0x0, sum = 3
6913 22:13:01.877184 16, 0x0, sum = 4
6914 22:13:01.877288 best_step = 14
6915 22:13:01.877379
6916 22:13:01.877477 ==
6917 22:13:01.880554 Dram Type= 6, Freq= 0, CH_1, rank 1
6918 22:13:01.883552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6919 22:13:01.883660 ==
6920 22:13:01.886952 RX Vref Scan: 0
6921 22:13:01.887061
6922 22:13:01.890107 RX Vref 0 -> 0, step: 1
6923 22:13:01.890212
6924 22:13:01.890309 RX Delay -311 -> 252, step: 8
6925 22:13:01.898464 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6926 22:13:01.901719 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
6927 22:13:01.905479 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6928 22:13:01.908763 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6929 22:13:01.915302 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6930 22:13:01.918819 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6931 22:13:01.922141 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6932 22:13:01.925041 iDelay=217, Bit 7, Center -16 (-239 ~ 208) 448
6933 22:13:01.931920 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6934 22:13:01.934972 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6935 22:13:01.938610 iDelay=217, Bit 10, Center -24 (-247 ~ 200) 448
6936 22:13:01.941831 iDelay=217, Bit 11, Center -28 (-247 ~ 192) 440
6937 22:13:01.948893 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
6938 22:13:01.952130 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6939 22:13:01.955594 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6940 22:13:01.958817 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6941 22:13:01.961868 ==
6942 22:13:01.965517 Dram Type= 6, Freq= 0, CH_1, rank 1
6943 22:13:01.968606 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6944 22:13:01.968691 ==
6945 22:13:01.968759 DQS Delay:
6946 22:13:01.972200 DQS0 = 28, DQS1 = 36
6947 22:13:01.972284 DQM Delay:
6948 22:13:01.975224 DQM0 = 10, DQM1 = 13
6949 22:13:01.975350 DQ Delay:
6950 22:13:01.978488 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =4
6951 22:13:01.982067 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =12
6952 22:13:01.985035 DQ8 =0, DQ9 =4, DQ10 =12, DQ11 =8
6953 22:13:01.988515 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =20
6954 22:13:01.988633
6955 22:13:01.988727
6956 22:13:01.995402 [DQSOSCAuto] RK1, (LSB)MR18= 0xc95a, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 384 ps
6957 22:13:01.998770 CH1 RK1: MR19=C0C, MR18=C95A
6958 22:13:02.005467 CH1_RK1: MR19=0xC0C, MR18=0xC95A, DQSOSC=384, MR23=63, INC=400, DEC=267
6959 22:13:02.008653 [RxdqsGatingPostProcess] freq 400
6960 22:13:02.011818 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6961 22:13:02.015437 best DQS0 dly(2T, 0.5T) = (0, 10)
6962 22:13:02.018454 best DQS1 dly(2T, 0.5T) = (0, 10)
6963 22:13:02.021989 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6964 22:13:02.025084 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6965 22:13:02.028690 best DQS0 dly(2T, 0.5T) = (0, 10)
6966 22:13:02.032376 best DQS1 dly(2T, 0.5T) = (0, 10)
6967 22:13:02.035442 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6968 22:13:02.038678 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6969 22:13:02.042001 Pre-setting of DQS Precalculation
6970 22:13:02.045120 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6971 22:13:02.055363 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6972 22:13:02.061817 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6973 22:13:02.061902
6974 22:13:02.061967
6975 22:13:02.065178 [Calibration Summary] 800 Mbps
6976 22:13:02.065276 CH 0, Rank 0
6977 22:13:02.068919 SW Impedance : PASS
6978 22:13:02.068991 DUTY Scan : NO K
6979 22:13:02.072024 ZQ Calibration : PASS
6980 22:13:02.075858 Jitter Meter : NO K
6981 22:13:02.075958 CBT Training : PASS
6982 22:13:02.078471 Write leveling : PASS
6983 22:13:02.078559 RX DQS gating : PASS
6984 22:13:02.082341 RX DQ/DQS(RDDQC) : PASS
6985 22:13:02.085438 TX DQ/DQS : PASS
6986 22:13:02.085581 RX DATLAT : PASS
6987 22:13:02.088658 RX DQ/DQS(Engine): PASS
6988 22:13:02.091768 TX OE : NO K
6989 22:13:02.091841 All Pass.
6990 22:13:02.091908
6991 22:13:02.091967 CH 0, Rank 1
6992 22:13:02.095318 SW Impedance : PASS
6993 22:13:02.098738 DUTY Scan : NO K
6994 22:13:02.098814 ZQ Calibration : PASS
6995 22:13:02.102480 Jitter Meter : NO K
6996 22:13:02.105309 CBT Training : PASS
6997 22:13:02.105408 Write leveling : NO K
6998 22:13:02.108867 RX DQS gating : PASS
6999 22:13:02.112465 RX DQ/DQS(RDDQC) : PASS
7000 22:13:02.112546 TX DQ/DQS : PASS
7001 22:13:02.115716 RX DATLAT : PASS
7002 22:13:02.118694 RX DQ/DQS(Engine): PASS
7003 22:13:02.118776 TX OE : NO K
7004 22:13:02.118840 All Pass.
7005 22:13:02.121849
7006 22:13:02.121930 CH 1, Rank 0
7007 22:13:02.125499 SW Impedance : PASS
7008 22:13:02.125631 DUTY Scan : NO K
7009 22:13:02.128960 ZQ Calibration : PASS
7010 22:13:02.129045 Jitter Meter : NO K
7011 22:13:02.131960 CBT Training : PASS
7012 22:13:02.135775 Write leveling : PASS
7013 22:13:02.135920 RX DQS gating : PASS
7014 22:13:02.138990 RX DQ/DQS(RDDQC) : PASS
7015 22:13:02.142059 TX DQ/DQS : PASS
7016 22:13:02.142142 RX DATLAT : PASS
7017 22:13:02.145813 RX DQ/DQS(Engine): PASS
7018 22:13:02.148707 TX OE : NO K
7019 22:13:02.148805 All Pass.
7020 22:13:02.148876
7021 22:13:02.148937 CH 1, Rank 1
7022 22:13:02.151749 SW Impedance : PASS
7023 22:13:02.155315 DUTY Scan : NO K
7024 22:13:02.155397 ZQ Calibration : PASS
7025 22:13:02.158994 Jitter Meter : NO K
7026 22:13:02.162315 CBT Training : PASS
7027 22:13:02.162396 Write leveling : NO K
7028 22:13:02.165422 RX DQS gating : PASS
7029 22:13:02.168522 RX DQ/DQS(RDDQC) : PASS
7030 22:13:02.168603 TX DQ/DQS : PASS
7031 22:13:02.171660 RX DATLAT : PASS
7032 22:13:02.171741 RX DQ/DQS(Engine): PASS
7033 22:13:02.175609 TX OE : NO K
7034 22:13:02.175691 All Pass.
7035 22:13:02.175755
7036 22:13:02.178614 DramC Write-DBI off
7037 22:13:02.182112 PER_BANK_REFRESH: Hybrid Mode
7038 22:13:02.182193 TX_TRACKING: ON
7039 22:13:02.191899 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7040 22:13:02.195002 [FAST_K] Save calibration result to emmc
7041 22:13:02.198887 dramc_set_vcore_voltage set vcore to 725000
7042 22:13:02.201900 Read voltage for 1600, 0
7043 22:13:02.201982 Vio18 = 0
7044 22:13:02.205451 Vcore = 725000
7045 22:13:02.205571 Vdram = 0
7046 22:13:02.205637 Vddq = 0
7047 22:13:02.205698 Vmddr = 0
7048 22:13:02.211810 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7049 22:13:02.214882 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7050 22:13:02.218484 MEM_TYPE=3, freq_sel=13
7051 22:13:02.221670 sv_algorithm_assistance_LP4_3733
7052 22:13:02.225209 ============ PULL DRAM RESETB DOWN ============
7053 22:13:02.231598 ========== PULL DRAM RESETB DOWN end =========
7054 22:13:02.235090 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7055 22:13:02.238289 ===================================
7056 22:13:02.241418 LPDDR4 DRAM CONFIGURATION
7057 22:13:02.245108 ===================================
7058 22:13:02.245197 EX_ROW_EN[0] = 0x0
7059 22:13:02.248357 EX_ROW_EN[1] = 0x0
7060 22:13:02.248449 LP4Y_EN = 0x0
7061 22:13:02.251802 WORK_FSP = 0x1
7062 22:13:02.251885 WL = 0x5
7063 22:13:02.255068 RL = 0x5
7064 22:13:02.255176 BL = 0x2
7065 22:13:02.258851 RPST = 0x0
7066 22:13:02.258959 RD_PRE = 0x0
7067 22:13:02.262305 WR_PRE = 0x1
7068 22:13:02.262408 WR_PST = 0x1
7069 22:13:02.265307 DBI_WR = 0x0
7070 22:13:02.265388 DBI_RD = 0x0
7071 22:13:02.268702 OTF = 0x1
7072 22:13:02.271804 ===================================
7073 22:13:02.275742 ===================================
7074 22:13:02.275825 ANA top config
7075 22:13:02.278661 ===================================
7076 22:13:02.282075 DLL_ASYNC_EN = 0
7077 22:13:02.285169 ALL_SLAVE_EN = 0
7078 22:13:02.288218 NEW_RANK_MODE = 1
7079 22:13:02.288318 DLL_IDLE_MODE = 1
7080 22:13:02.291768 LP45_APHY_COMB_EN = 1
7081 22:13:02.295389 TX_ODT_DIS = 0
7082 22:13:02.298606 NEW_8X_MODE = 1
7083 22:13:02.301861 ===================================
7084 22:13:02.305431 ===================================
7085 22:13:02.308529 data_rate = 3200
7086 22:13:02.308628 CKR = 1
7087 22:13:02.312296 DQ_P2S_RATIO = 8
7088 22:13:02.315348 ===================================
7089 22:13:02.318277 CA_P2S_RATIO = 8
7090 22:13:02.321917 DQ_CA_OPEN = 0
7091 22:13:02.324919 DQ_SEMI_OPEN = 0
7092 22:13:02.328406 CA_SEMI_OPEN = 0
7093 22:13:02.328519 CA_FULL_RATE = 0
7094 22:13:02.332031 DQ_CKDIV4_EN = 0
7095 22:13:02.335082 CA_CKDIV4_EN = 0
7096 22:13:02.338703 CA_PREDIV_EN = 0
7097 22:13:02.341766 PH8_DLY = 12
7098 22:13:02.345424 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7099 22:13:02.345559 DQ_AAMCK_DIV = 4
7100 22:13:02.348513 CA_AAMCK_DIV = 4
7101 22:13:02.351793 CA_ADMCK_DIV = 4
7102 22:13:02.355583 DQ_TRACK_CA_EN = 0
7103 22:13:02.358251 CA_PICK = 1600
7104 22:13:02.362062 CA_MCKIO = 1600
7105 22:13:02.365139 MCKIO_SEMI = 0
7106 22:13:02.365260 PLL_FREQ = 3068
7107 22:13:02.368626 DQ_UI_PI_RATIO = 32
7108 22:13:02.371837 CA_UI_PI_RATIO = 0
7109 22:13:02.374980 ===================================
7110 22:13:02.378825 ===================================
7111 22:13:02.381917 memory_type:LPDDR4
7112 22:13:02.381999 GP_NUM : 10
7113 22:13:02.385077 SRAM_EN : 1
7114 22:13:02.388219 MD32_EN : 0
7115 22:13:02.391986 ===================================
7116 22:13:02.392100 [ANA_INIT] >>>>>>>>>>>>>>
7117 22:13:02.395013 <<<<<< [CONFIGURE PHASE]: ANA_TX
7118 22:13:02.398014 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7119 22:13:02.401679 ===================================
7120 22:13:02.404810 data_rate = 3200,PCW = 0X7600
7121 22:13:02.408382 ===================================
7122 22:13:02.411393 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7123 22:13:02.418105 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7124 22:13:02.421282 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7125 22:13:02.428255 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7126 22:13:02.431172 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7127 22:13:02.434634 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7128 22:13:02.438195 [ANA_INIT] flow start
7129 22:13:02.438309 [ANA_INIT] PLL >>>>>>>>
7130 22:13:02.441195 [ANA_INIT] PLL <<<<<<<<
7131 22:13:02.444678 [ANA_INIT] MIDPI >>>>>>>>
7132 22:13:02.444781 [ANA_INIT] MIDPI <<<<<<<<
7133 22:13:02.448086 [ANA_INIT] DLL >>>>>>>>
7134 22:13:02.451278 [ANA_INIT] DLL <<<<<<<<
7135 22:13:02.451376 [ANA_INIT] flow end
7136 22:13:02.455314 ============ LP4 DIFF to SE enter ============
7137 22:13:02.461222 ============ LP4 DIFF to SE exit ============
7138 22:13:02.461324 [ANA_INIT] <<<<<<<<<<<<<
7139 22:13:02.464336 [Flow] Enable top DCM control >>>>>
7140 22:13:02.467837 [Flow] Enable top DCM control <<<<<
7141 22:13:02.471447 Enable DLL master slave shuffle
7142 22:13:02.477644 ==============================================================
7143 22:13:02.477743 Gating Mode config
7144 22:13:02.484515 ==============================================================
7145 22:13:02.488393 Config description:
7146 22:13:02.497813 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7147 22:13:02.504665 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7148 22:13:02.507696 SELPH_MODE 0: By rank 1: By Phase
7149 22:13:02.514820 ==============================================================
7150 22:13:02.517958 GAT_TRACK_EN = 1
7151 22:13:02.521193 RX_GATING_MODE = 2
7152 22:13:02.521275 RX_GATING_TRACK_MODE = 2
7153 22:13:02.524311 SELPH_MODE = 1
7154 22:13:02.527907 PICG_EARLY_EN = 1
7155 22:13:02.530966 VALID_LAT_VALUE = 1
7156 22:13:02.538010 ==============================================================
7157 22:13:02.541049 Enter into Gating configuration >>>>
7158 22:13:02.544714 Exit from Gating configuration <<<<
7159 22:13:02.548201 Enter into DVFS_PRE_config >>>>>
7160 22:13:02.557797 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7161 22:13:02.561436 Exit from DVFS_PRE_config <<<<<
7162 22:13:02.564213 Enter into PICG configuration >>>>
7163 22:13:02.567949 Exit from PICG configuration <<<<
7164 22:13:02.570986 [RX_INPUT] configuration >>>>>
7165 22:13:02.574521 [RX_INPUT] configuration <<<<<
7166 22:13:02.577628 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7167 22:13:02.584775 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7168 22:13:02.591700 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7169 22:13:02.594964 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7170 22:13:02.601344 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7171 22:13:02.607762 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7172 22:13:02.611548 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7173 22:13:02.614579 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7174 22:13:02.621856 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7175 22:13:02.624803 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7176 22:13:02.627927 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7177 22:13:02.635274 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7178 22:13:02.638105 ===================================
7179 22:13:02.638215 LPDDR4 DRAM CONFIGURATION
7180 22:13:02.641017 ===================================
7181 22:13:02.644394 EX_ROW_EN[0] = 0x0
7182 22:13:02.644494 EX_ROW_EN[1] = 0x0
7183 22:13:02.647531 LP4Y_EN = 0x0
7184 22:13:02.651198 WORK_FSP = 0x1
7185 22:13:02.651304 WL = 0x5
7186 22:13:02.654181 RL = 0x5
7187 22:13:02.654258 BL = 0x2
7188 22:13:02.658080 RPST = 0x0
7189 22:13:02.658187 RD_PRE = 0x0
7190 22:13:02.660952 WR_PRE = 0x1
7191 22:13:02.661031 WR_PST = 0x1
7192 22:13:02.664842 DBI_WR = 0x0
7193 22:13:02.664944 DBI_RD = 0x0
7194 22:13:02.667627 OTF = 0x1
7195 22:13:02.671420 ===================================
7196 22:13:02.674427 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7197 22:13:02.678270 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7198 22:13:02.684477 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7199 22:13:02.684561 ===================================
7200 22:13:02.687886 LPDDR4 DRAM CONFIGURATION
7201 22:13:02.691388 ===================================
7202 22:13:02.694630 EX_ROW_EN[0] = 0x10
7203 22:13:02.694711 EX_ROW_EN[1] = 0x0
7204 22:13:02.697783 LP4Y_EN = 0x0
7205 22:13:02.697867 WORK_FSP = 0x1
7206 22:13:02.700909 WL = 0x5
7207 22:13:02.700993 RL = 0x5
7208 22:13:02.704246 BL = 0x2
7209 22:13:02.704329 RPST = 0x0
7210 22:13:02.708015 RD_PRE = 0x0
7211 22:13:02.711209 WR_PRE = 0x1
7212 22:13:02.711317 WR_PST = 0x1
7213 22:13:02.714269 DBI_WR = 0x0
7214 22:13:02.714360 DBI_RD = 0x0
7215 22:13:02.717945 OTF = 0x1
7216 22:13:02.721157 ===================================
7217 22:13:02.724423 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7218 22:13:02.727511 ==
7219 22:13:02.727608 Dram Type= 6, Freq= 0, CH_0, rank 0
7220 22:13:02.734135 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7221 22:13:02.734242 ==
7222 22:13:02.737644 [Duty_Offset_Calibration]
7223 22:13:02.737731 B0:2 B1:1 CA:1
7224 22:13:02.737835
7225 22:13:02.740665 [DutyScan_Calibration_Flow] k_type=0
7226 22:13:02.750616
7227 22:13:02.750700 ==CLK 0==
7228 22:13:02.753759 Final CLK duty delay cell = 0
7229 22:13:02.757291 [0] MAX Duty = 5156%(X100), DQS PI = 22
7230 22:13:02.760817 [0] MIN Duty = 4907%(X100), DQS PI = 0
7231 22:13:02.760899 [0] AVG Duty = 5031%(X100)
7232 22:13:02.764170
7233 22:13:02.767085 CH0 CLK Duty spec in!! Max-Min= 249%
7234 22:13:02.770643 [DutyScan_Calibration_Flow] ====Done====
7235 22:13:02.770725
7236 22:13:02.774302 [DutyScan_Calibration_Flow] k_type=1
7237 22:13:02.789887
7238 22:13:02.789972 ==DQS 0 ==
7239 22:13:02.792992 Final DQS duty delay cell = -4
7240 22:13:02.796576 [-4] MAX Duty = 5125%(X100), DQS PI = 26
7241 22:13:02.799775 [-4] MIN Duty = 4657%(X100), DQS PI = 0
7242 22:13:02.802930 [-4] AVG Duty = 4891%(X100)
7243 22:13:02.803014
7244 22:13:02.803109 ==DQS 1 ==
7245 22:13:02.806296 Final DQS duty delay cell = 0
7246 22:13:02.809890 [0] MAX Duty = 5218%(X100), DQS PI = 20
7247 22:13:02.813120 [0] MIN Duty = 5062%(X100), DQS PI = 32
7248 22:13:02.816722 [0] AVG Duty = 5140%(X100)
7249 22:13:02.816805
7250 22:13:02.819785 CH0 DQS 0 Duty spec in!! Max-Min= 468%
7251 22:13:02.819871
7252 22:13:02.822879 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7253 22:13:02.826463 [DutyScan_Calibration_Flow] ====Done====
7254 22:13:02.826546
7255 22:13:02.829708 [DutyScan_Calibration_Flow] k_type=3
7256 22:13:02.846773
7257 22:13:02.846861 ==DQM 0 ==
7258 22:13:02.849948 Final DQM duty delay cell = 0
7259 22:13:02.853633 [0] MAX Duty = 5218%(X100), DQS PI = 34
7260 22:13:02.856209 [0] MIN Duty = 4907%(X100), DQS PI = 0
7261 22:13:02.856286 [0] AVG Duty = 5062%(X100)
7262 22:13:02.860107
7263 22:13:02.860189 ==DQM 1 ==
7264 22:13:02.863033 Final DQM duty delay cell = -4
7265 22:13:02.866704 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7266 22:13:02.869875 [-4] MIN Duty = 4844%(X100), DQS PI = 34
7267 22:13:02.872913 [-4] AVG Duty = 4922%(X100)
7268 22:13:02.873013
7269 22:13:02.876307 CH0 DQM 0 Duty spec in!! Max-Min= 311%
7270 22:13:02.876386
7271 22:13:02.879851 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7272 22:13:02.882904 [DutyScan_Calibration_Flow] ====Done====
7273 22:13:02.882979
7274 22:13:02.886418 [DutyScan_Calibration_Flow] k_type=2
7275 22:13:02.904097
7276 22:13:02.904180 ==DQ 0 ==
7277 22:13:02.907248 Final DQ duty delay cell = 0
7278 22:13:02.910586 [0] MAX Duty = 5062%(X100), DQS PI = 24
7279 22:13:02.913635 [0] MIN Duty = 4907%(X100), DQS PI = 0
7280 22:13:02.913718 [0] AVG Duty = 4984%(X100)
7281 22:13:02.913783
7282 22:13:02.916960 ==DQ 1 ==
7283 22:13:02.920711 Final DQ duty delay cell = 0
7284 22:13:02.923726 [0] MAX Duty = 5125%(X100), DQS PI = 6
7285 22:13:02.927352 [0] MIN Duty = 4938%(X100), DQS PI = 34
7286 22:13:02.927439 [0] AVG Duty = 5031%(X100)
7287 22:13:02.927504
7288 22:13:02.930589 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7289 22:13:02.930660
7290 22:13:02.937354 CH0 DQ 1 Duty spec in!! Max-Min= 187%
7291 22:13:02.940709 [DutyScan_Calibration_Flow] ====Done====
7292 22:13:02.940791 ==
7293 22:13:02.943671 Dram Type= 6, Freq= 0, CH_1, rank 0
7294 22:13:02.947350 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7295 22:13:02.947434 ==
7296 22:13:02.950389 [Duty_Offset_Calibration]
7297 22:13:02.950483 B0:1 B1:0 CA:0
7298 22:13:02.950548
7299 22:13:02.953427 [DutyScan_Calibration_Flow] k_type=0
7300 22:13:02.963599
7301 22:13:02.963702 ==CLK 0==
7302 22:13:02.966552 Final CLK duty delay cell = -4
7303 22:13:02.970224 [-4] MAX Duty = 5000%(X100), DQS PI = 24
7304 22:13:02.973390 [-4] MIN Duty = 4844%(X100), DQS PI = 2
7305 22:13:02.976493 [-4] AVG Duty = 4922%(X100)
7306 22:13:02.976573
7307 22:13:02.980114 CH1 CLK Duty spec in!! Max-Min= 156%
7308 22:13:02.983053 [DutyScan_Calibration_Flow] ====Done====
7309 22:13:02.983133
7310 22:13:02.986776 [DutyScan_Calibration_Flow] k_type=1
7311 22:13:03.003551
7312 22:13:03.003632 ==DQS 0 ==
7313 22:13:03.006518 Final DQS duty delay cell = 0
7314 22:13:03.009706 [0] MAX Duty = 5094%(X100), DQS PI = 16
7315 22:13:03.013474 [0] MIN Duty = 4844%(X100), DQS PI = 44
7316 22:13:03.013593 [0] AVG Duty = 4969%(X100)
7317 22:13:03.016479
7318 22:13:03.016558 ==DQS 1 ==
7319 22:13:03.019703 Final DQS duty delay cell = 0
7320 22:13:03.023051 [0] MAX Duty = 5281%(X100), DQS PI = 18
7321 22:13:03.026815 [0] MIN Duty = 4969%(X100), DQS PI = 8
7322 22:13:03.026894 [0] AVG Duty = 5125%(X100)
7323 22:13:03.029682
7324 22:13:03.033385 CH1 DQS 0 Duty spec in!! Max-Min= 250%
7325 22:13:03.033464
7326 22:13:03.036601 CH1 DQS 1 Duty spec in!! Max-Min= 312%
7327 22:13:03.040291 [DutyScan_Calibration_Flow] ====Done====
7328 22:13:03.040370
7329 22:13:03.043325 [DutyScan_Calibration_Flow] k_type=3
7330 22:13:03.060068
7331 22:13:03.060160 ==DQM 0 ==
7332 22:13:03.063460 Final DQM duty delay cell = 0
7333 22:13:03.066476 [0] MAX Duty = 5218%(X100), DQS PI = 18
7334 22:13:03.070276 [0] MIN Duty = 4969%(X100), DQS PI = 48
7335 22:13:03.073289 [0] AVG Duty = 5093%(X100)
7336 22:13:03.073371
7337 22:13:03.073434 ==DQM 1 ==
7338 22:13:03.076808 Final DQM duty delay cell = 0
7339 22:13:03.079816 [0] MAX Duty = 5093%(X100), DQS PI = 42
7340 22:13:03.082980 [0] MIN Duty = 4907%(X100), DQS PI = 34
7341 22:13:03.086478 [0] AVG Duty = 5000%(X100)
7342 22:13:03.086559
7343 22:13:03.089880 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7344 22:13:03.089960
7345 22:13:03.093058 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7346 22:13:03.096510 [DutyScan_Calibration_Flow] ====Done====
7347 22:13:03.096590
7348 22:13:03.099651 [DutyScan_Calibration_Flow] k_type=2
7349 22:13:03.116620
7350 22:13:03.116769 ==DQ 0 ==
7351 22:13:03.119561 Final DQ duty delay cell = -4
7352 22:13:03.122916 [-4] MAX Duty = 5031%(X100), DQS PI = 10
7353 22:13:03.126004 [-4] MIN Duty = 4875%(X100), DQS PI = 46
7354 22:13:03.129875 [-4] AVG Duty = 4953%(X100)
7355 22:13:03.129958
7356 22:13:03.130022 ==DQ 1 ==
7357 22:13:03.132817 Final DQ duty delay cell = 0
7358 22:13:03.136119 [0] MAX Duty = 5124%(X100), DQS PI = 16
7359 22:13:03.139256 [0] MIN Duty = 4938%(X100), DQS PI = 8
7360 22:13:03.143082 [0] AVG Duty = 5031%(X100)
7361 22:13:03.143194
7362 22:13:03.145993 CH1 DQ 0 Duty spec in!! Max-Min= 156%
7363 22:13:03.146071
7364 22:13:03.149270 CH1 DQ 1 Duty spec in!! Max-Min= 186%
7365 22:13:03.152937 [DutyScan_Calibration_Flow] ====Done====
7366 22:13:03.156021 nWR fixed to 30
7367 22:13:03.159688 [ModeRegInit_LP4] CH0 RK0
7368 22:13:03.159764 [ModeRegInit_LP4] CH0 RK1
7369 22:13:03.162716 [ModeRegInit_LP4] CH1 RK0
7370 22:13:03.166146 [ModeRegInit_LP4] CH1 RK1
7371 22:13:03.166261 match AC timing 5
7372 22:13:03.172962 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7373 22:13:03.175806 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7374 22:13:03.179351 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7375 22:13:03.186112 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7376 22:13:03.189204 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7377 22:13:03.189287 [MiockJmeterHQA]
7378 22:13:03.189351
7379 22:13:03.192884 [DramcMiockJmeter] u1RxGatingPI = 0
7380 22:13:03.196117 0 : 4253, 4027
7381 22:13:03.196202 4 : 4253, 4027
7382 22:13:03.199367 8 : 4253, 4027
7383 22:13:03.199487 12 : 4255, 4029
7384 22:13:03.199588 16 : 4252, 4027
7385 22:13:03.202727 20 : 4363, 4138
7386 22:13:03.202841 24 : 4363, 4137
7387 22:13:03.205836 28 : 4252, 4027
7388 22:13:03.205914 32 : 4253, 4027
7389 22:13:03.209397 36 : 4253, 4026
7390 22:13:03.209505 40 : 4252, 4027
7391 22:13:03.212455 44 : 4255, 4029
7392 22:13:03.212558 48 : 4363, 4138
7393 22:13:03.212704 52 : 4252, 4027
7394 22:13:03.215526 56 : 4253, 4026
7395 22:13:03.215596 60 : 4250, 4027
7396 22:13:03.218917 64 : 4253, 4030
7397 22:13:03.219003 68 : 4250, 4026
7398 22:13:03.222753 72 : 4360, 4138
7399 22:13:03.222822 76 : 4360, 4137
7400 22:13:03.225731 80 : 4253, 4029
7401 22:13:03.225830 84 : 4250, 4026
7402 22:13:03.225929 88 : 4250, 218
7403 22:13:03.228985 92 : 4250, 0
7404 22:13:03.229081 96 : 4252, 0
7405 22:13:03.229169 100 : 4360, 0
7406 22:13:03.232152 104 : 4361, 0
7407 22:13:03.232247 108 : 4250, 0
7408 22:13:03.235735 112 : 4250, 0
7409 22:13:03.235833 116 : 4250, 0
7410 22:13:03.235928 120 : 4250, 0
7411 22:13:03.238732 124 : 4250, 0
7412 22:13:03.238832 128 : 4250, 0
7413 22:13:03.242640 132 : 4253, 0
7414 22:13:03.242716 136 : 4253, 0
7415 22:13:03.242779 140 : 4250, 0
7416 22:13:03.245750 144 : 4253, 0
7417 22:13:03.245832 148 : 4361, 0
7418 22:13:03.249353 152 : 4360, 0
7419 22:13:03.249463 156 : 4363, 0
7420 22:13:03.249591 160 : 4250, 0
7421 22:13:03.252329 164 : 4253, 0
7422 22:13:03.252438 168 : 4251, 0
7423 22:13:03.252532 172 : 4250, 0
7424 22:13:03.255677 176 : 4250, 0
7425 22:13:03.255760 180 : 4250, 0
7426 22:13:03.258972 184 : 4253, 0
7427 22:13:03.259055 188 : 4253, 0
7428 22:13:03.259121 192 : 4250, 0
7429 22:13:03.262564 196 : 4253, 0
7430 22:13:03.262647 200 : 4365, 0
7431 22:13:03.265685 204 : 4360, 1493
7432 22:13:03.265768 208 : 4360, 4129
7433 22:13:03.268679 212 : 4248, 4024
7434 22:13:03.268761 216 : 4361, 4137
7435 22:13:03.271980 220 : 4361, 4138
7436 22:13:03.272080 224 : 4250, 4027
7437 22:13:03.272177 228 : 4250, 4027
7438 22:13:03.275573 232 : 4363, 4140
7439 22:13:03.275688 236 : 4250, 4026
7440 22:13:03.279021 240 : 4250, 4027
7441 22:13:03.279131 244 : 4253, 4027
7442 22:13:03.282204 248 : 4252, 4029
7443 22:13:03.282290 252 : 4250, 4026
7444 22:13:03.285448 256 : 4250, 4027
7445 22:13:03.285571 260 : 4361, 4138
7446 22:13:03.289034 264 : 4249, 4027
7447 22:13:03.289144 268 : 4250, 4026
7448 22:13:03.292158 272 : 4361, 4137
7449 22:13:03.292241 276 : 4250, 4027
7450 22:13:03.295246 280 : 4250, 4027
7451 22:13:03.295328 284 : 4363, 4140
7452 22:13:03.298810 288 : 4250, 4026
7453 22:13:03.298926 292 : 4250, 4027
7454 22:13:03.299030 296 : 4250, 4027
7455 22:13:03.301848 300 : 4252, 4029
7456 22:13:03.301931 304 : 4250, 4026
7457 22:13:03.305337 308 : 4250, 3923
7458 22:13:03.305419 312 : 4360, 1993
7459 22:13:03.305484
7460 22:13:03.308944 MIOCK jitter meter ch=0
7461 22:13:03.309025
7462 22:13:03.312540 1T = (312-88) = 224 dly cells
7463 22:13:03.319231 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7464 22:13:03.319313 ==
7465 22:13:03.322148 Dram Type= 6, Freq= 0, CH_0, rank 0
7466 22:13:03.325129 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7467 22:13:03.325211 ==
7468 22:13:03.332237 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7469 22:13:03.335946 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7470 22:13:03.338823 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7471 22:13:03.345492 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7472 22:13:03.354024 [CA 0] Center 43 (13~74) winsize 62
7473 22:13:03.357189 [CA 1] Center 43 (13~74) winsize 62
7474 22:13:03.360476 [CA 2] Center 38 (9~68) winsize 60
7475 22:13:03.363818 [CA 3] Center 38 (8~68) winsize 61
7476 22:13:03.367568 [CA 4] Center 37 (7~67) winsize 61
7477 22:13:03.370508 [CA 5] Center 36 (7~65) winsize 59
7478 22:13:03.370588
7479 22:13:03.373745 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7480 22:13:03.373826
7481 22:13:03.377416 [CATrainingPosCal] consider 1 rank data
7482 22:13:03.380468 u2DelayCellTimex100 = 290/100 ps
7483 22:13:03.383690 CA0 delay=43 (13~74),Diff = 7 PI (23 cell)
7484 22:13:03.390568 CA1 delay=43 (13~74),Diff = 7 PI (23 cell)
7485 22:13:03.393695 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
7486 22:13:03.396862 CA3 delay=38 (8~68),Diff = 2 PI (6 cell)
7487 22:13:03.400401 CA4 delay=37 (7~67),Diff = 1 PI (3 cell)
7488 22:13:03.404191 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
7489 22:13:03.404309
7490 22:13:03.407126 CA PerBit enable=1, Macro0, CA PI delay=36
7491 22:13:03.407247
7492 22:13:03.410122 [CBTSetCACLKResult] CA Dly = 36
7493 22:13:03.413838 CS Dly: 9 (0~40)
7494 22:13:03.416905 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7495 22:13:03.419997 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7496 22:13:03.420110 ==
7497 22:13:03.423418 Dram Type= 6, Freq= 0, CH_0, rank 1
7498 22:13:03.427171 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7499 22:13:03.430164 ==
7500 22:13:03.433496 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7501 22:13:03.436732 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7502 22:13:03.443527 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7503 22:13:03.446593 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7504 22:13:03.457134 [CA 0] Center 42 (12~73) winsize 62
7505 22:13:03.460680 [CA 1] Center 42 (12~73) winsize 62
7506 22:13:03.463788 [CA 2] Center 37 (7~67) winsize 61
7507 22:13:03.467513 [CA 3] Center 38 (8~68) winsize 61
7508 22:13:03.470512 [CA 4] Center 35 (5~65) winsize 61
7509 22:13:03.473764 [CA 5] Center 35 (5~65) winsize 61
7510 22:13:03.473845
7511 22:13:03.476865 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7512 22:13:03.476946
7513 22:13:03.480617 [CATrainingPosCal] consider 2 rank data
7514 22:13:03.483749 u2DelayCellTimex100 = 290/100 ps
7515 22:13:03.487318 CA0 delay=43 (13~73),Diff = 7 PI (23 cell)
7516 22:13:03.493497 CA1 delay=43 (13~73),Diff = 7 PI (23 cell)
7517 22:13:03.497060 CA2 delay=38 (9~67),Diff = 2 PI (6 cell)
7518 22:13:03.500592 CA3 delay=38 (8~68),Diff = 2 PI (6 cell)
7519 22:13:03.503409 CA4 delay=36 (7~65),Diff = 0 PI (0 cell)
7520 22:13:03.506757 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
7521 22:13:03.506839
7522 22:13:03.510309 CA PerBit enable=1, Macro0, CA PI delay=36
7523 22:13:03.510390
7524 22:13:03.513217 [CBTSetCACLKResult] CA Dly = 36
7525 22:13:03.516642 CS Dly: 10 (0~42)
7526 22:13:03.520043 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7527 22:13:03.523798 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7528 22:13:03.523879
7529 22:13:03.527008 ----->DramcWriteLeveling(PI) begin...
7530 22:13:03.527090 ==
7531 22:13:03.530567 Dram Type= 6, Freq= 0, CH_0, rank 0
7532 22:13:03.533468 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7533 22:13:03.536652 ==
7534 22:13:03.536734 Write leveling (Byte 0): 37 => 37
7535 22:13:03.540298 Write leveling (Byte 1): 30 => 30
7536 22:13:03.543461 DramcWriteLeveling(PI) end<-----
7537 22:13:03.543544
7538 22:13:03.543609 ==
7539 22:13:03.547257 Dram Type= 6, Freq= 0, CH_0, rank 0
7540 22:13:03.553909 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7541 22:13:03.553992 ==
7542 22:13:03.557108 [Gating] SW mode calibration
7543 22:13:03.563770 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7544 22:13:03.566844 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7545 22:13:03.573685 1 4 0 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
7546 22:13:03.576769 1 4 4 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
7547 22:13:03.580104 1 4 8 | B1->B0 | 2323 2524 | 0 1 | (0 0) (0 0)
7548 22:13:03.586764 1 4 12 | B1->B0 | 2323 3636 | 0 1 | (0 0) (0 0)
7549 22:13:03.589870 1 4 16 | B1->B0 | 2323 3635 | 1 1 | (0 0) (1 1)
7550 22:13:03.593499 1 4 20 | B1->B0 | 3434 3837 | 1 1 | (1 1) (1 1)
7551 22:13:03.599906 1 4 24 | B1->B0 | 3434 3737 | 1 1 | (1 1) (0 0)
7552 22:13:03.603348 1 4 28 | B1->B0 | 3434 3636 | 1 1 | (1 1) (1 1)
7553 22:13:03.606918 1 5 0 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
7554 22:13:03.609884 1 5 4 | B1->B0 | 3434 3636 | 1 0 | (1 1) (0 0)
7555 22:13:03.616497 1 5 8 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
7556 22:13:03.619980 1 5 12 | B1->B0 | 3434 2828 | 1 0 | (1 1) (1 0)
7557 22:13:03.623554 1 5 16 | B1->B0 | 3434 2625 | 0 1 | (0 0) (0 0)
7558 22:13:03.630039 1 5 20 | B1->B0 | 2929 2727 | 0 0 | (1 0) (0 0)
7559 22:13:03.633193 1 5 24 | B1->B0 | 2323 302f | 0 1 | (0 0) (1 1)
7560 22:13:03.636728 1 5 28 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
7561 22:13:03.642854 1 6 0 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
7562 22:13:03.646628 1 6 4 | B1->B0 | 2323 2928 | 0 1 | (0 0) (1 1)
7563 22:13:03.649883 1 6 8 | B1->B0 | 2323 3130 | 0 1 | (0 0) (0 0)
7564 22:13:03.656784 1 6 12 | B1->B0 | 2323 4645 | 0 1 | (0 0) (0 0)
7565 22:13:03.659741 1 6 16 | B1->B0 | 2727 4646 | 0 0 | (0 0) (0 0)
7566 22:13:03.662922 1 6 20 | B1->B0 | 4444 4646 | 0 1 | (0 0) (1 1)
7567 22:13:03.669669 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7568 22:13:03.672956 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7569 22:13:03.676005 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7570 22:13:03.682878 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7571 22:13:03.686353 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7572 22:13:03.689268 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7573 22:13:03.696259 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7574 22:13:03.699325 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7575 22:13:03.702896 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7576 22:13:03.709693 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7577 22:13:03.712968 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7578 22:13:03.716405 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7579 22:13:03.722893 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7580 22:13:03.726013 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7581 22:13:03.729584 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7582 22:13:03.735928 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7583 22:13:03.739158 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7584 22:13:03.742575 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7585 22:13:03.749436 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7586 22:13:03.752549 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7587 22:13:03.755789 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7588 22:13:03.759279 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7589 22:13:03.766199 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7590 22:13:03.768982 Total UI for P1: 0, mck2ui 16
7591 22:13:03.772803 best dqsien dly found for B0: ( 1, 9, 10)
7592 22:13:03.776046 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7593 22:13:03.779063 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7594 22:13:03.782890 Total UI for P1: 0, mck2ui 16
7595 22:13:03.786182 best dqsien dly found for B1: ( 1, 9, 18)
7596 22:13:03.789156 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7597 22:13:03.792371 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7598 22:13:03.792478
7599 22:13:03.799656 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7600 22:13:03.802700 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7601 22:13:03.805768 [Gating] SW calibration Done
7602 22:13:03.805850 ==
7603 22:13:03.809438 Dram Type= 6, Freq= 0, CH_0, rank 0
7604 22:13:03.812562 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7605 22:13:03.812645 ==
7606 22:13:03.812710 RX Vref Scan: 0
7607 22:13:03.812769
7608 22:13:03.816044 RX Vref 0 -> 0, step: 1
7609 22:13:03.816127
7610 22:13:03.818997 RX Delay 0 -> 252, step: 8
7611 22:13:03.822512 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7612 22:13:03.826052 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7613 22:13:03.832266 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
7614 22:13:03.835913 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7615 22:13:03.839378 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7616 22:13:03.842498 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7617 22:13:03.846094 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
7618 22:13:03.849057 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7619 22:13:03.855949 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7620 22:13:03.859345 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
7621 22:13:03.862552 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7622 22:13:03.865666 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7623 22:13:03.868927 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
7624 22:13:03.875625 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7625 22:13:03.879210 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7626 22:13:03.882562 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7627 22:13:03.882645 ==
7628 22:13:03.886101 Dram Type= 6, Freq= 0, CH_0, rank 0
7629 22:13:03.889261 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7630 22:13:03.889344 ==
7631 22:13:03.892342 DQS Delay:
7632 22:13:03.892425 DQS0 = 0, DQS1 = 0
7633 22:13:03.896060 DQM Delay:
7634 22:13:03.896142 DQM0 = 136, DQM1 = 129
7635 22:13:03.899075 DQ Delay:
7636 22:13:03.902676 DQ0 =135, DQ1 =143, DQ2 =135, DQ3 =131
7637 22:13:03.905889 DQ4 =139, DQ5 =123, DQ6 =143, DQ7 =143
7638 22:13:03.908807 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
7639 22:13:03.912002 DQ12 =135, DQ13 =135, DQ14 =139, DQ15 =135
7640 22:13:03.912084
7641 22:13:03.912149
7642 22:13:03.912210 ==
7643 22:13:03.915605 Dram Type= 6, Freq= 0, CH_0, rank 0
7644 22:13:03.918935 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7645 22:13:03.919017 ==
7646 22:13:03.919082
7647 22:13:03.919141
7648 22:13:03.922519 TX Vref Scan disable
7649 22:13:03.926046 == TX Byte 0 ==
7650 22:13:03.928600 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
7651 22:13:03.932126 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7652 22:13:03.935787 == TX Byte 1 ==
7653 22:13:03.938758 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7654 22:13:03.942312 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7655 22:13:03.942395 ==
7656 22:13:03.945226 Dram Type= 6, Freq= 0, CH_0, rank 0
7657 22:13:03.951764 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7658 22:13:03.951847 ==
7659 22:13:03.963952
7660 22:13:03.967636 TX Vref early break, caculate TX vref
7661 22:13:03.970975 TX Vref=16, minBit 1, minWin=22, winSum=376
7662 22:13:03.974251 TX Vref=18, minBit 4, minWin=23, winSum=385
7663 22:13:03.977341 TX Vref=20, minBit 0, minWin=23, winSum=393
7664 22:13:03.981102 TX Vref=22, minBit 3, minWin=24, winSum=405
7665 22:13:03.984074 TX Vref=24, minBit 2, minWin=24, winSum=411
7666 22:13:03.990502 TX Vref=26, minBit 0, minWin=25, winSum=422
7667 22:13:03.993958 TX Vref=28, minBit 0, minWin=24, winSum=418
7668 22:13:03.997097 TX Vref=30, minBit 8, minWin=24, winSum=413
7669 22:13:04.000862 TX Vref=32, minBit 6, minWin=23, winSum=402
7670 22:13:04.004103 TX Vref=34, minBit 1, minWin=23, winSum=393
7671 22:13:04.010746 [TxChooseVref] Worse bit 0, Min win 25, Win sum 422, Final Vref 26
7672 22:13:04.010830
7673 22:13:04.013790 Final TX Range 0 Vref 26
7674 22:13:04.013873
7675 22:13:04.013938 ==
7676 22:13:04.017328 Dram Type= 6, Freq= 0, CH_0, rank 0
7677 22:13:04.020530 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7678 22:13:04.020613 ==
7679 22:13:04.020678
7680 22:13:04.020736
7681 22:13:04.023784 TX Vref Scan disable
7682 22:13:04.030507 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7683 22:13:04.030590 == TX Byte 0 ==
7684 22:13:04.033578 u2DelayCellOfst[0]=13 cells (4 PI)
7685 22:13:04.037422 u2DelayCellOfst[1]=16 cells (5 PI)
7686 22:13:04.040321 u2DelayCellOfst[2]=13 cells (4 PI)
7687 22:13:04.043856 u2DelayCellOfst[3]=10 cells (3 PI)
7688 22:13:04.047259 u2DelayCellOfst[4]=10 cells (3 PI)
7689 22:13:04.050300 u2DelayCellOfst[5]=0 cells (0 PI)
7690 22:13:04.053775 u2DelayCellOfst[6]=16 cells (5 PI)
7691 22:13:04.057285 u2DelayCellOfst[7]=16 cells (5 PI)
7692 22:13:04.060704 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7693 22:13:04.063525 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7694 22:13:04.067112 == TX Byte 1 ==
7695 22:13:04.067195 u2DelayCellOfst[8]=0 cells (0 PI)
7696 22:13:04.070309 u2DelayCellOfst[9]=0 cells (0 PI)
7697 22:13:04.073547 u2DelayCellOfst[10]=6 cells (2 PI)
7698 22:13:04.077111 u2DelayCellOfst[11]=6 cells (2 PI)
7699 22:13:04.080090 u2DelayCellOfst[12]=10 cells (3 PI)
7700 22:13:04.083752 u2DelayCellOfst[13]=10 cells (3 PI)
7701 22:13:04.086895 u2DelayCellOfst[14]=13 cells (4 PI)
7702 22:13:04.090057 u2DelayCellOfst[15]=10 cells (3 PI)
7703 22:13:04.093904 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7704 22:13:04.099950 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7705 22:13:04.100033 DramC Write-DBI on
7706 22:13:04.100099 ==
7707 22:13:04.103792 Dram Type= 6, Freq= 0, CH_0, rank 0
7708 22:13:04.106753 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7709 22:13:04.109880 ==
7710 22:13:04.109963
7711 22:13:04.110028
7712 22:13:04.110086 TX Vref Scan disable
7713 22:13:04.113593 == TX Byte 0 ==
7714 22:13:04.117213 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7715 22:13:04.120637 == TX Byte 1 ==
7716 22:13:04.123825 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7717 22:13:04.126990 DramC Write-DBI off
7718 22:13:04.127093
7719 22:13:04.127185 [DATLAT]
7720 22:13:04.127273 Freq=1600, CH0 RK0
7721 22:13:04.127365
7722 22:13:04.130649 DATLAT Default: 0xf
7723 22:13:04.130746 0, 0xFFFF, sum = 0
7724 22:13:04.133751 1, 0xFFFF, sum = 0
7725 22:13:04.133856 2, 0xFFFF, sum = 0
7726 22:13:04.137013 3, 0xFFFF, sum = 0
7727 22:13:04.140114 4, 0xFFFF, sum = 0
7728 22:13:04.140216 5, 0xFFFF, sum = 0
7729 22:13:04.143845 6, 0xFFFF, sum = 0
7730 22:13:04.143951 7, 0xFFFF, sum = 0
7731 22:13:04.146585 8, 0xFFFF, sum = 0
7732 22:13:04.146693 9, 0xFFFF, sum = 0
7733 22:13:04.150005 10, 0xFFFF, sum = 0
7734 22:13:04.150120 11, 0xFFFF, sum = 0
7735 22:13:04.153426 12, 0xFFFF, sum = 0
7736 22:13:04.153551 13, 0xFFFF, sum = 0
7737 22:13:04.157236 14, 0x0, sum = 1
7738 22:13:04.157338 15, 0x0, sum = 2
7739 22:13:04.160625 16, 0x0, sum = 3
7740 22:13:04.160714 17, 0x0, sum = 4
7741 22:13:04.163505 best_step = 15
7742 22:13:04.163602
7743 22:13:04.163694 ==
7744 22:13:04.167096 Dram Type= 6, Freq= 0, CH_0, rank 0
7745 22:13:04.170465 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7746 22:13:04.170567 ==
7747 22:13:04.170661 RX Vref Scan: 1
7748 22:13:04.173360
7749 22:13:04.173456 Set Vref Range= 24 -> 127
7750 22:13:04.173584
7751 22:13:04.176773 RX Vref 24 -> 127, step: 1
7752 22:13:04.176875
7753 22:13:04.179964 RX Delay 19 -> 252, step: 4
7754 22:13:04.180066
7755 22:13:04.183577 Set Vref, RX VrefLevel [Byte0]: 24
7756 22:13:04.187091 [Byte1]: 24
7757 22:13:04.187195
7758 22:13:04.189893 Set Vref, RX VrefLevel [Byte0]: 25
7759 22:13:04.193017 [Byte1]: 25
7760 22:13:04.193114
7761 22:13:04.196556 Set Vref, RX VrefLevel [Byte0]: 26
7762 22:13:04.199897 [Byte1]: 26
7763 22:13:04.203729
7764 22:13:04.203826 Set Vref, RX VrefLevel [Byte0]: 27
7765 22:13:04.207513 [Byte1]: 27
7766 22:13:04.211189
7767 22:13:04.211287 Set Vref, RX VrefLevel [Byte0]: 28
7768 22:13:04.214493 [Byte1]: 28
7769 22:13:04.218862
7770 22:13:04.218961 Set Vref, RX VrefLevel [Byte0]: 29
7771 22:13:04.222320 [Byte1]: 29
7772 22:13:04.226601
7773 22:13:04.226705 Set Vref, RX VrefLevel [Byte0]: 30
7774 22:13:04.232754 [Byte1]: 30
7775 22:13:04.232853
7776 22:13:04.236517 Set Vref, RX VrefLevel [Byte0]: 31
7777 22:13:04.239727 [Byte1]: 31
7778 22:13:04.239827
7779 22:13:04.242776 Set Vref, RX VrefLevel [Byte0]: 32
7780 22:13:04.246321 [Byte1]: 32
7781 22:13:04.246419
7782 22:13:04.249908 Set Vref, RX VrefLevel [Byte0]: 33
7783 22:13:04.253042 [Byte1]: 33
7784 22:13:04.256937
7785 22:13:04.257045 Set Vref, RX VrefLevel [Byte0]: 34
7786 22:13:04.259950 [Byte1]: 34
7787 22:13:04.264833
7788 22:13:04.264927 Set Vref, RX VrefLevel [Byte0]: 35
7789 22:13:04.267813 [Byte1]: 35
7790 22:13:04.272121
7791 22:13:04.272217 Set Vref, RX VrefLevel [Byte0]: 36
7792 22:13:04.275550 [Byte1]: 36
7793 22:13:04.279573
7794 22:13:04.279672 Set Vref, RX VrefLevel [Byte0]: 37
7795 22:13:04.283015 [Byte1]: 37
7796 22:13:04.286960
7797 22:13:04.287059 Set Vref, RX VrefLevel [Byte0]: 38
7798 22:13:04.290591 [Byte1]: 38
7799 22:13:04.294699
7800 22:13:04.294801 Set Vref, RX VrefLevel [Byte0]: 39
7801 22:13:04.298104 [Byte1]: 39
7802 22:13:04.302476
7803 22:13:04.302575 Set Vref, RX VrefLevel [Byte0]: 40
7804 22:13:04.305481 [Byte1]: 40
7805 22:13:04.310002
7806 22:13:04.310104 Set Vref, RX VrefLevel [Byte0]: 41
7807 22:13:04.312992 [Byte1]: 41
7808 22:13:04.317389
7809 22:13:04.317485 Set Vref, RX VrefLevel [Byte0]: 42
7810 22:13:04.321087 [Byte1]: 42
7811 22:13:04.325278
7812 22:13:04.325376 Set Vref, RX VrefLevel [Byte0]: 43
7813 22:13:04.328493 [Byte1]: 43
7814 22:13:04.332531
7815 22:13:04.332608 Set Vref, RX VrefLevel [Byte0]: 44
7816 22:13:04.336079 [Byte1]: 44
7817 22:13:04.340457
7818 22:13:04.340553 Set Vref, RX VrefLevel [Byte0]: 45
7819 22:13:04.343583 [Byte1]: 45
7820 22:13:04.347857
7821 22:13:04.347955 Set Vref, RX VrefLevel [Byte0]: 46
7822 22:13:04.350861 [Byte1]: 46
7823 22:13:04.355306
7824 22:13:04.355403 Set Vref, RX VrefLevel [Byte0]: 47
7825 22:13:04.358554 [Byte1]: 47
7826 22:13:04.363138
7827 22:13:04.363236 Set Vref, RX VrefLevel [Byte0]: 48
7828 22:13:04.366023 [Byte1]: 48
7829 22:13:04.370642
7830 22:13:04.370743 Set Vref, RX VrefLevel [Byte0]: 49
7831 22:13:04.373731 [Byte1]: 49
7832 22:13:04.377906
7833 22:13:04.377976 Set Vref, RX VrefLevel [Byte0]: 50
7834 22:13:04.381269 [Byte1]: 50
7835 22:13:04.385800
7836 22:13:04.385898 Set Vref, RX VrefLevel [Byte0]: 51
7837 22:13:04.388791 [Byte1]: 51
7838 22:13:04.393409
7839 22:13:04.393514 Set Vref, RX VrefLevel [Byte0]: 52
7840 22:13:04.397088 [Byte1]: 52
7841 22:13:04.401048
7842 22:13:04.401153 Set Vref, RX VrefLevel [Byte0]: 53
7843 22:13:04.404553 [Byte1]: 53
7844 22:13:04.408362
7845 22:13:04.408461 Set Vref, RX VrefLevel [Byte0]: 54
7846 22:13:04.412092 [Byte1]: 54
7847 22:13:04.415816
7848 22:13:04.415911 Set Vref, RX VrefLevel [Byte0]: 55
7849 22:13:04.419046 [Byte1]: 55
7850 22:13:04.423927
7851 22:13:04.424021 Set Vref, RX VrefLevel [Byte0]: 56
7852 22:13:04.426927 [Byte1]: 56
7853 22:13:04.430797
7854 22:13:04.430896 Set Vref, RX VrefLevel [Byte0]: 57
7855 22:13:04.434371 [Byte1]: 57
7856 22:13:04.438667
7857 22:13:04.438767 Set Vref, RX VrefLevel [Byte0]: 58
7858 22:13:04.442285 [Byte1]: 58
7859 22:13:04.445985
7860 22:13:04.446083 Set Vref, RX VrefLevel [Byte0]: 59
7861 22:13:04.449661 [Byte1]: 59
7862 22:13:04.453803
7863 22:13:04.453899 Set Vref, RX VrefLevel [Byte0]: 60
7864 22:13:04.456981 [Byte1]: 60
7865 22:13:04.461170
7866 22:13:04.461269 Set Vref, RX VrefLevel [Byte0]: 61
7867 22:13:04.464807 [Byte1]: 61
7868 22:13:04.469159
7869 22:13:04.469261 Set Vref, RX VrefLevel [Byte0]: 62
7870 22:13:04.472046 [Byte1]: 62
7871 22:13:04.476819
7872 22:13:04.476916 Set Vref, RX VrefLevel [Byte0]: 63
7873 22:13:04.479732 [Byte1]: 63
7874 22:13:04.483943
7875 22:13:04.484041 Set Vref, RX VrefLevel [Byte0]: 64
7876 22:13:04.487557 [Byte1]: 64
7877 22:13:04.491467
7878 22:13:04.491565 Set Vref, RX VrefLevel [Byte0]: 65
7879 22:13:04.494823 [Byte1]: 65
7880 22:13:04.499591
7881 22:13:04.499693 Set Vref, RX VrefLevel [Byte0]: 66
7882 22:13:04.502303 [Byte1]: 66
7883 22:13:04.506589
7884 22:13:04.506687 Set Vref, RX VrefLevel [Byte0]: 67
7885 22:13:04.510025 [Byte1]: 67
7886 22:13:04.514809
7887 22:13:04.514912 Set Vref, RX VrefLevel [Byte0]: 68
7888 22:13:04.517715 [Byte1]: 68
7889 22:13:04.522071
7890 22:13:04.522167 Set Vref, RX VrefLevel [Byte0]: 69
7891 22:13:04.524962 [Byte1]: 69
7892 22:13:04.530029
7893 22:13:04.530102 Set Vref, RX VrefLevel [Byte0]: 70
7894 22:13:04.532990 [Byte1]: 70
7895 22:13:04.537169
7896 22:13:04.537266 Set Vref, RX VrefLevel [Byte0]: 71
7897 22:13:04.540396 [Byte1]: 71
7898 22:13:04.544655
7899 22:13:04.544730 Set Vref, RX VrefLevel [Byte0]: 72
7900 22:13:04.548139 [Byte1]: 72
7901 22:13:04.551952
7902 22:13:04.552050 Set Vref, RX VrefLevel [Byte0]: 73
7903 22:13:04.555759 [Byte1]: 73
7904 22:13:04.559627
7905 22:13:04.559723 Set Vref, RX VrefLevel [Byte0]: 74
7906 22:13:04.562950 [Byte1]: 74
7907 22:13:04.567155
7908 22:13:04.567226 Final RX Vref Byte 0 = 58 to rank0
7909 22:13:04.570501 Final RX Vref Byte 1 = 58 to rank0
7910 22:13:04.574050 Final RX Vref Byte 0 = 58 to rank1
7911 22:13:04.577484 Final RX Vref Byte 1 = 58 to rank1==
7912 22:13:04.580603 Dram Type= 6, Freq= 0, CH_0, rank 0
7913 22:13:04.587414 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7914 22:13:04.587518 ==
7915 22:13:04.587611 DQS Delay:
7916 22:13:04.587698 DQS0 = 0, DQS1 = 0
7917 22:13:04.590863 DQM Delay:
7918 22:13:04.590934 DQM0 = 134, DQM1 = 127
7919 22:13:04.594069 DQ Delay:
7920 22:13:04.597430 DQ0 =134, DQ1 =138, DQ2 =134, DQ3 =134
7921 22:13:04.600601 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =140
7922 22:13:04.604037 DQ8 =116, DQ9 =118, DQ10 =128, DQ11 =120
7923 22:13:04.607633 DQ12 =130, DQ13 =134, DQ14 =138, DQ15 =134
7924 22:13:04.607734
7925 22:13:04.607825
7926 22:13:04.607910
7927 22:13:04.610884 [DramC_TX_OE_Calibration] TA2
7928 22:13:04.613961 Original DQ_B0 (3 6) =30, OEN = 27
7929 22:13:04.617651 Original DQ_B1 (3 6) =30, OEN = 27
7930 22:13:04.620428 24, 0x0, End_B0=24 End_B1=24
7931 22:13:04.620529 25, 0x0, End_B0=25 End_B1=25
7932 22:13:04.624101 26, 0x0, End_B0=26 End_B1=26
7933 22:13:04.627219 27, 0x0, End_B0=27 End_B1=27
7934 22:13:04.630491 28, 0x0, End_B0=28 End_B1=28
7935 22:13:04.630589 29, 0x0, End_B0=29 End_B1=29
7936 22:13:04.634152 30, 0x0, End_B0=30 End_B1=30
7937 22:13:04.637155 31, 0x4141, End_B0=30 End_B1=30
7938 22:13:04.640375 Byte0 end_step=30 best_step=27
7939 22:13:04.644135 Byte1 end_step=30 best_step=27
7940 22:13:04.647145 Byte0 TX OE(2T, 0.5T) = (3, 3)
7941 22:13:04.647242 Byte1 TX OE(2T, 0.5T) = (3, 3)
7942 22:13:04.650729
7943 22:13:04.650822
7944 22:13:04.657486 [DQSOSCAuto] RK0, (LSB)MR18= 0x2722, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 390 ps
7945 22:13:04.660791 CH0 RK0: MR19=303, MR18=2722
7946 22:13:04.667589 CH0_RK0: MR19=0x303, MR18=0x2722, DQSOSC=390, MR23=63, INC=24, DEC=16
7947 22:13:04.667685
7948 22:13:04.670509 ----->DramcWriteLeveling(PI) begin...
7949 22:13:04.670606 ==
7950 22:13:04.674276 Dram Type= 6, Freq= 0, CH_0, rank 1
7951 22:13:04.677267 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7952 22:13:04.677365 ==
7953 22:13:04.680461 Write leveling (Byte 0): 37 => 37
7954 22:13:04.684059 Write leveling (Byte 1): 29 => 29
7955 22:13:04.686962 DramcWriteLeveling(PI) end<-----
7956 22:13:04.687058
7957 22:13:04.687150 ==
7958 22:13:04.690484 Dram Type= 6, Freq= 0, CH_0, rank 1
7959 22:13:04.694320 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7960 22:13:04.694402 ==
7961 22:13:04.697168 [Gating] SW mode calibration
7962 22:13:04.704209 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7963 22:13:04.710516 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7964 22:13:04.713879 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7965 22:13:04.717468 1 4 4 | B1->B0 | 2323 2423 | 0 1 | (0 0) (1 1)
7966 22:13:04.724025 1 4 8 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
7967 22:13:04.727442 1 4 12 | B1->B0 | 2323 2929 | 0 1 | (0 0) (0 0)
7968 22:13:04.730300 1 4 16 | B1->B0 | 3434 3737 | 0 0 | (0 0) (0 0)
7969 22:13:04.736695 1 4 20 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7970 22:13:04.740535 1 4 24 | B1->B0 | 3434 3a3a | 1 1 | (1 1) (1 1)
7971 22:13:04.743732 1 4 28 | B1->B0 | 3434 3736 | 1 1 | (1 1) (1 1)
7972 22:13:04.750448 1 5 0 | B1->B0 | 3434 3838 | 1 0 | (1 1) (1 1)
7973 22:13:04.753540 1 5 4 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7974 22:13:04.757212 1 5 8 | B1->B0 | 3434 3838 | 1 0 | (1 0) (0 0)
7975 22:13:04.763745 1 5 12 | B1->B0 | 3434 3635 | 1 1 | (1 0) (0 0)
7976 22:13:04.766872 1 5 16 | B1->B0 | 2f2f 2827 | 0 1 | (0 0) (0 0)
7977 22:13:04.770647 1 5 20 | B1->B0 | 2323 2726 | 0 1 | (0 0) (0 0)
7978 22:13:04.776692 1 5 24 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
7979 22:13:04.780276 1 5 28 | B1->B0 | 2323 2a29 | 0 1 | (0 0) (0 0)
7980 22:13:04.783477 1 6 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7981 22:13:04.790062 1 6 4 | B1->B0 | 2323 2726 | 0 1 | (0 0) (0 0)
7982 22:13:04.793177 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7983 22:13:04.796815 1 6 12 | B1->B0 | 2323 3333 | 0 1 | (0 0) (0 0)
7984 22:13:04.803365 1 6 16 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
7985 22:13:04.806711 1 6 20 | B1->B0 | 4646 4545 | 0 1 | (0 0) (0 0)
7986 22:13:04.809837 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7987 22:13:04.813762 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7988 22:13:04.820327 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7989 22:13:04.823344 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7990 22:13:04.826600 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7991 22:13:04.833025 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7992 22:13:04.836316 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7993 22:13:04.839992 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7994 22:13:04.846354 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7995 22:13:04.849901 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7996 22:13:04.853010 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7997 22:13:04.859804 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7998 22:13:04.863021 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7999 22:13:04.866428 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8000 22:13:04.873260 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8001 22:13:04.876443 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8002 22:13:04.879707 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8003 22:13:04.886473 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8004 22:13:04.889674 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8005 22:13:04.893202 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8006 22:13:04.900179 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8007 22:13:04.902916 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8008 22:13:04.906028 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8009 22:13:04.912709 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8010 22:13:04.912796 Total UI for P1: 0, mck2ui 16
8011 22:13:04.919679 best dqsien dly found for B0: ( 1, 9, 14)
8012 22:13:04.919762 Total UI for P1: 0, mck2ui 16
8013 22:13:04.926477 best dqsien dly found for B1: ( 1, 9, 14)
8014 22:13:04.929729 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8015 22:13:04.932904 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8016 22:13:04.932995
8017 22:13:04.936405 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8018 22:13:04.939248 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8019 22:13:04.942798 [Gating] SW calibration Done
8020 22:13:04.942881 ==
8021 22:13:04.945840 Dram Type= 6, Freq= 0, CH_0, rank 1
8022 22:13:04.949342 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8023 22:13:04.949426 ==
8024 22:13:04.952614 RX Vref Scan: 0
8025 22:13:04.952697
8026 22:13:04.952762 RX Vref 0 -> 0, step: 1
8027 22:13:04.952822
8028 22:13:04.956154 RX Delay 0 -> 252, step: 8
8029 22:13:04.959730 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8030 22:13:04.965799 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8031 22:13:04.969080 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8032 22:13:04.972653 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8033 22:13:04.976175 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8034 22:13:04.979372 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8035 22:13:04.985471 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8036 22:13:04.989345 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8037 22:13:04.992330 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8038 22:13:04.996115 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8039 22:13:04.999164 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8040 22:13:05.006107 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8041 22:13:05.009184 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8042 22:13:05.012793 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8043 22:13:05.015836 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8044 22:13:05.022128 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8045 22:13:05.022211 ==
8046 22:13:05.025726 Dram Type= 6, Freq= 0, CH_0, rank 1
8047 22:13:05.028932 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8048 22:13:05.029024 ==
8049 22:13:05.029090 DQS Delay:
8050 22:13:05.032208 DQS0 = 0, DQS1 = 0
8051 22:13:05.032290 DQM Delay:
8052 22:13:05.035796 DQM0 = 137, DQM1 = 128
8053 22:13:05.035878 DQ Delay:
8054 22:13:05.038796 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8055 22:13:05.042138 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8056 22:13:05.045225 DQ8 =119, DQ9 =119, DQ10 =127, DQ11 =119
8057 22:13:05.048586 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8058 22:13:05.048669
8059 22:13:05.048733
8060 22:13:05.048792 ==
8061 22:13:05.052068 Dram Type= 6, Freq= 0, CH_0, rank 1
8062 22:13:05.058783 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8063 22:13:05.058866 ==
8064 22:13:05.058932
8065 22:13:05.058992
8066 22:13:05.061687 TX Vref Scan disable
8067 22:13:05.061770 == TX Byte 0 ==
8068 22:13:05.065393 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
8069 22:13:05.071801 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8070 22:13:05.071884 == TX Byte 1 ==
8071 22:13:05.075102 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8072 22:13:05.082010 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8073 22:13:05.082093 ==
8074 22:13:05.085211 Dram Type= 6, Freq= 0, CH_0, rank 1
8075 22:13:05.088918 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8076 22:13:05.089002 ==
8077 22:13:05.102556
8078 22:13:05.105651 TX Vref early break, caculate TX vref
8079 22:13:05.109471 TX Vref=16, minBit 1, minWin=23, winSum=384
8080 22:13:05.112512 TX Vref=18, minBit 4, minWin=23, winSum=394
8081 22:13:05.116323 TX Vref=20, minBit 0, minWin=24, winSum=402
8082 22:13:05.119349 TX Vref=22, minBit 1, minWin=24, winSum=410
8083 22:13:05.122277 TX Vref=24, minBit 1, minWin=25, winSum=417
8084 22:13:05.129018 TX Vref=26, minBit 1, minWin=25, winSum=424
8085 22:13:05.132498 TX Vref=28, minBit 4, minWin=25, winSum=422
8086 22:13:05.135613 TX Vref=30, minBit 4, minWin=24, winSum=418
8087 22:13:05.139269 TX Vref=32, minBit 4, minWin=24, winSum=406
8088 22:13:05.142295 TX Vref=34, minBit 0, minWin=24, winSum=399
8089 22:13:05.148937 [TxChooseVref] Worse bit 1, Min win 25, Win sum 424, Final Vref 26
8090 22:13:05.149021
8091 22:13:05.152564 Final TX Range 0 Vref 26
8092 22:13:05.152678
8093 22:13:05.152772 ==
8094 22:13:05.156166 Dram Type= 6, Freq= 0, CH_0, rank 1
8095 22:13:05.158863 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8096 22:13:05.158962 ==
8097 22:13:05.159061
8098 22:13:05.159147
8099 22:13:05.162451 TX Vref Scan disable
8100 22:13:05.169199 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8101 22:13:05.169298 == TX Byte 0 ==
8102 22:13:05.172332 u2DelayCellOfst[0]=10 cells (3 PI)
8103 22:13:05.175500 u2DelayCellOfst[1]=13 cells (4 PI)
8104 22:13:05.179289 u2DelayCellOfst[2]=10 cells (3 PI)
8105 22:13:05.182668 u2DelayCellOfst[3]=6 cells (2 PI)
8106 22:13:05.185419 u2DelayCellOfst[4]=6 cells (2 PI)
8107 22:13:05.188981 u2DelayCellOfst[5]=0 cells (0 PI)
8108 22:13:05.192509 u2DelayCellOfst[6]=13 cells (4 PI)
8109 22:13:05.192582 u2DelayCellOfst[7]=13 cells (4 PI)
8110 22:13:05.198612 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8111 22:13:05.202206 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8112 22:13:05.202281 == TX Byte 1 ==
8113 22:13:05.205348 u2DelayCellOfst[8]=3 cells (1 PI)
8114 22:13:05.208516 u2DelayCellOfst[9]=0 cells (0 PI)
8115 22:13:05.212225 u2DelayCellOfst[10]=6 cells (2 PI)
8116 22:13:05.215570 u2DelayCellOfst[11]=3 cells (1 PI)
8117 22:13:05.218584 u2DelayCellOfst[12]=10 cells (3 PI)
8118 22:13:05.221946 u2DelayCellOfst[13]=13 cells (4 PI)
8119 22:13:05.225086 u2DelayCellOfst[14]=13 cells (4 PI)
8120 22:13:05.228846 u2DelayCellOfst[15]=10 cells (3 PI)
8121 22:13:05.232013 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8122 22:13:05.238831 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8123 22:13:05.238914 DramC Write-DBI on
8124 22:13:05.238979 ==
8125 22:13:05.242146 Dram Type= 6, Freq= 0, CH_0, rank 1
8126 22:13:05.245223 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8127 22:13:05.245306 ==
8128 22:13:05.248689
8129 22:13:05.248772
8130 22:13:05.248836 TX Vref Scan disable
8131 22:13:05.252232 == TX Byte 0 ==
8132 22:13:05.255291 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
8133 22:13:05.258817 == TX Byte 1 ==
8134 22:13:05.262144 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8135 22:13:05.262228 DramC Write-DBI off
8136 22:13:05.265107
8137 22:13:05.265183 [DATLAT]
8138 22:13:05.265253 Freq=1600, CH0 RK1
8139 22:13:05.265312
8140 22:13:05.268202 DATLAT Default: 0xf
8141 22:13:05.268277 0, 0xFFFF, sum = 0
8142 22:13:05.271901 1, 0xFFFF, sum = 0
8143 22:13:05.271983 2, 0xFFFF, sum = 0
8144 22:13:05.274979 3, 0xFFFF, sum = 0
8145 22:13:05.278618 4, 0xFFFF, sum = 0
8146 22:13:05.278699 5, 0xFFFF, sum = 0
8147 22:13:05.281890 6, 0xFFFF, sum = 0
8148 22:13:05.281965 7, 0xFFFF, sum = 0
8149 22:13:05.285050 8, 0xFFFF, sum = 0
8150 22:13:05.285129 9, 0xFFFF, sum = 0
8151 22:13:05.288797 10, 0xFFFF, sum = 0
8152 22:13:05.288875 11, 0xFFFF, sum = 0
8153 22:13:05.291784 12, 0xFFFF, sum = 0
8154 22:13:05.291870 13, 0xFFFF, sum = 0
8155 22:13:05.295349 14, 0x0, sum = 1
8156 22:13:05.295438 15, 0x0, sum = 2
8157 22:13:05.298214 16, 0x0, sum = 3
8158 22:13:05.298297 17, 0x0, sum = 4
8159 22:13:05.301790 best_step = 15
8160 22:13:05.301871
8161 22:13:05.301934 ==
8162 22:13:05.305200 Dram Type= 6, Freq= 0, CH_0, rank 1
8163 22:13:05.308372 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8164 22:13:05.308453 ==
8165 22:13:05.308517 RX Vref Scan: 0
8166 22:13:05.308575
8167 22:13:05.311866 RX Vref 0 -> 0, step: 1
8168 22:13:05.311952
8169 22:13:05.315174 RX Delay 19 -> 252, step: 4
8170 22:13:05.318222 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8171 22:13:05.325008 iDelay=191, Bit 1, Center 138 (91 ~ 186) 96
8172 22:13:05.328589 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8173 22:13:05.331750 iDelay=191, Bit 3, Center 134 (83 ~ 186) 104
8174 22:13:05.335269 iDelay=191, Bit 4, Center 136 (87 ~ 186) 100
8175 22:13:05.338344 iDelay=191, Bit 5, Center 126 (75 ~ 178) 104
8176 22:13:05.341624 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8177 22:13:05.348576 iDelay=191, Bit 7, Center 142 (95 ~ 190) 96
8178 22:13:05.351915 iDelay=191, Bit 8, Center 118 (67 ~ 170) 104
8179 22:13:05.354966 iDelay=191, Bit 9, Center 116 (63 ~ 170) 108
8180 22:13:05.358173 iDelay=191, Bit 10, Center 126 (75 ~ 178) 104
8181 22:13:05.361631 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8182 22:13:05.368758 iDelay=191, Bit 12, Center 132 (83 ~ 182) 100
8183 22:13:05.371623 iDelay=191, Bit 13, Center 134 (83 ~ 186) 104
8184 22:13:05.375224 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8185 22:13:05.378293 iDelay=191, Bit 15, Center 134 (83 ~ 186) 104
8186 22:13:05.378374 ==
8187 22:13:05.381453 Dram Type= 6, Freq= 0, CH_0, rank 1
8188 22:13:05.388274 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8189 22:13:05.388355 ==
8190 22:13:05.388419 DQS Delay:
8191 22:13:05.391989 DQS0 = 0, DQS1 = 0
8192 22:13:05.392071 DQM Delay:
8193 22:13:05.395225 DQM0 = 135, DQM1 = 126
8194 22:13:05.395306 DQ Delay:
8195 22:13:05.398072 DQ0 =134, DQ1 =138, DQ2 =130, DQ3 =134
8196 22:13:05.401744 DQ4 =136, DQ5 =126, DQ6 =140, DQ7 =142
8197 22:13:05.404765 DQ8 =118, DQ9 =116, DQ10 =126, DQ11 =118
8198 22:13:05.408319 DQ12 =132, DQ13 =134, DQ14 =136, DQ15 =134
8199 22:13:05.408401
8200 22:13:05.408464
8201 22:13:05.408521
8202 22:13:05.411910 [DramC_TX_OE_Calibration] TA2
8203 22:13:05.415013 Original DQ_B0 (3 6) =30, OEN = 27
8204 22:13:05.418684 Original DQ_B1 (3 6) =30, OEN = 27
8205 22:13:05.421977 24, 0x0, End_B0=24 End_B1=24
8206 22:13:05.422059 25, 0x0, End_B0=25 End_B1=25
8207 22:13:05.424983 26, 0x0, End_B0=26 End_B1=26
8208 22:13:05.428081 27, 0x0, End_B0=27 End_B1=27
8209 22:13:05.431835 28, 0x0, End_B0=28 End_B1=28
8210 22:13:05.435197 29, 0x0, End_B0=29 End_B1=29
8211 22:13:05.435297 30, 0x0, End_B0=30 End_B1=30
8212 22:13:05.438320 31, 0x5151, End_B0=30 End_B1=30
8213 22:13:05.441943 Byte0 end_step=30 best_step=27
8214 22:13:05.445047 Byte1 end_step=30 best_step=27
8215 22:13:05.448169 Byte0 TX OE(2T, 0.5T) = (3, 3)
8216 22:13:05.451621 Byte1 TX OE(2T, 0.5T) = (3, 3)
8217 22:13:05.451704
8218 22:13:05.451787
8219 22:13:05.458189 [DQSOSCAuto] RK1, (LSB)MR18= 0x210a, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 393 ps
8220 22:13:05.461674 CH0 RK1: MR19=303, MR18=210A
8221 22:13:05.467931 CH0_RK1: MR19=0x303, MR18=0x210A, DQSOSC=393, MR23=63, INC=23, DEC=15
8222 22:13:05.471716 [RxdqsGatingPostProcess] freq 1600
8223 22:13:05.475021 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8224 22:13:05.477914 best DQS0 dly(2T, 0.5T) = (1, 1)
8225 22:13:05.481329 best DQS1 dly(2T, 0.5T) = (1, 1)
8226 22:13:05.484983 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8227 22:13:05.488040 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8228 22:13:05.491329 best DQS0 dly(2T, 0.5T) = (1, 1)
8229 22:13:05.494985 best DQS1 dly(2T, 0.5T) = (1, 1)
8230 22:13:05.498063 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8231 22:13:05.501269 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8232 22:13:05.504732 Pre-setting of DQS Precalculation
8233 22:13:05.507878 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8234 22:13:05.507961 ==
8235 22:13:05.511540 Dram Type= 6, Freq= 0, CH_1, rank 0
8236 22:13:05.514480 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8237 22:13:05.518198 ==
8238 22:13:05.521188 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8239 22:13:05.524997 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8240 22:13:05.531269 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8241 22:13:05.534448 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8242 22:13:05.544744 [CA 0] Center 41 (12~71) winsize 60
8243 22:13:05.547854 [CA 1] Center 41 (12~71) winsize 60
8244 22:13:05.551367 [CA 2] Center 38 (9~68) winsize 60
8245 22:13:05.554608 [CA 3] Center 37 (8~66) winsize 59
8246 22:13:05.557847 [CA 4] Center 38 (9~67) winsize 59
8247 22:13:05.561235 [CA 5] Center 36 (7~66) winsize 60
8248 22:13:05.561317
8249 22:13:05.564685 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8250 22:13:05.564768
8251 22:13:05.567903 [CATrainingPosCal] consider 1 rank data
8252 22:13:05.571412 u2DelayCellTimex100 = 290/100 ps
8253 22:13:05.574631 CA0 delay=41 (12~71),Diff = 5 PI (16 cell)
8254 22:13:05.581011 CA1 delay=41 (12~71),Diff = 5 PI (16 cell)
8255 22:13:05.584581 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
8256 22:13:05.588004 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8257 22:13:05.590855 CA4 delay=38 (9~67),Diff = 2 PI (6 cell)
8258 22:13:05.594647 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8259 22:13:05.594730
8260 22:13:05.597900 CA PerBit enable=1, Macro0, CA PI delay=36
8261 22:13:05.597983
8262 22:13:05.600870 [CBTSetCACLKResult] CA Dly = 36
8263 22:13:05.604747 CS Dly: 10 (0~41)
8264 22:13:05.607787 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8265 22:13:05.610886 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8266 22:13:05.610969 ==
8267 22:13:05.614551 Dram Type= 6, Freq= 0, CH_1, rank 1
8268 22:13:05.617433 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8269 22:13:05.621002 ==
8270 22:13:05.623898 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8271 22:13:05.627553 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8272 22:13:05.634059 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8273 22:13:05.640968 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8274 22:13:05.647718 [CA 0] Center 42 (12~72) winsize 61
8275 22:13:05.651567 [CA 1] Center 41 (12~71) winsize 60
8276 22:13:05.654459 [CA 2] Center 38 (9~68) winsize 60
8277 22:13:05.658066 [CA 3] Center 37 (8~67) winsize 60
8278 22:13:05.661207 [CA 4] Center 38 (8~68) winsize 61
8279 22:13:05.664226 [CA 5] Center 37 (8~67) winsize 60
8280 22:13:05.664363
8281 22:13:05.667518 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8282 22:13:05.667643
8283 22:13:05.671016 [CATrainingPosCal] consider 2 rank data
8284 22:13:05.674317 u2DelayCellTimex100 = 290/100 ps
8285 22:13:05.677702 CA0 delay=41 (12~71),Diff = 4 PI (13 cell)
8286 22:13:05.684186 CA1 delay=41 (12~71),Diff = 4 PI (13 cell)
8287 22:13:05.687693 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8288 22:13:05.691299 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8289 22:13:05.694690 CA4 delay=38 (9~67),Diff = 1 PI (3 cell)
8290 22:13:05.697602 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8291 22:13:05.697677
8292 22:13:05.700736 CA PerBit enable=1, Macro0, CA PI delay=37
8293 22:13:05.700834
8294 22:13:05.704483 [CBTSetCACLKResult] CA Dly = 37
8295 22:13:05.707603 CS Dly: 11 (0~44)
8296 22:13:05.710653 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8297 22:13:05.714337 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8298 22:13:05.714413
8299 22:13:05.717514 ----->DramcWriteLeveling(PI) begin...
8300 22:13:05.717631 ==
8301 22:13:05.720725 Dram Type= 6, Freq= 0, CH_1, rank 0
8302 22:13:05.727262 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8303 22:13:05.727342 ==
8304 22:13:05.730794 Write leveling (Byte 0): 25 => 25
8305 22:13:05.730882 Write leveling (Byte 1): 27 => 27
8306 22:13:05.734393 DramcWriteLeveling(PI) end<-----
8307 22:13:05.734488
8308 22:13:05.734567 ==
8309 22:13:05.737519 Dram Type= 6, Freq= 0, CH_1, rank 0
8310 22:13:05.743812 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8311 22:13:05.743892 ==
8312 22:13:05.747442 [Gating] SW mode calibration
8313 22:13:05.753813 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8314 22:13:05.757468 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8315 22:13:05.763667 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8316 22:13:05.767226 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8317 22:13:05.770281 1 4 8 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (0 0)
8318 22:13:05.777328 1 4 12 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
8319 22:13:05.780358 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8320 22:13:05.783777 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8321 22:13:05.790267 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8322 22:13:05.793704 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8323 22:13:05.797488 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8324 22:13:05.803451 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8325 22:13:05.807380 1 5 8 | B1->B0 | 3434 3030 | 1 0 | (1 0) (0 1)
8326 22:13:05.810488 1 5 12 | B1->B0 | 2b2b 2323 | 0 0 | (1 0) (0 0)
8327 22:13:05.817211 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8328 22:13:05.820230 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8329 22:13:05.823493 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8330 22:13:05.826700 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8331 22:13:05.833408 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8332 22:13:05.836902 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8333 22:13:05.840510 1 6 8 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)
8334 22:13:05.846960 1 6 12 | B1->B0 | 4141 4646 | 1 0 | (0 0) (0 0)
8335 22:13:05.850595 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8336 22:13:05.853778 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8337 22:13:05.860290 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8338 22:13:05.863548 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8339 22:13:05.866533 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8340 22:13:05.873277 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8341 22:13:05.877195 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8342 22:13:05.880733 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8343 22:13:05.886832 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8344 22:13:05.889902 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8345 22:13:05.893348 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8346 22:13:05.900323 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8347 22:13:05.903380 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8348 22:13:05.906715 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8349 22:13:05.913520 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8350 22:13:05.916488 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8351 22:13:05.919594 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8352 22:13:05.926541 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8353 22:13:05.929605 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8354 22:13:05.933358 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8355 22:13:05.940051 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8356 22:13:05.943177 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8357 22:13:05.946511 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8358 22:13:05.952968 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8359 22:13:05.956728 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8360 22:13:05.959891 Total UI for P1: 0, mck2ui 16
8361 22:13:05.962935 best dqsien dly found for B0: ( 1, 9, 10)
8362 22:13:05.966552 Total UI for P1: 0, mck2ui 16
8363 22:13:05.970287 best dqsien dly found for B1: ( 1, 9, 10)
8364 22:13:05.973259 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8365 22:13:05.976419 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8366 22:13:05.976531
8367 22:13:05.979437 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8368 22:13:05.982898 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8369 22:13:05.986383 [Gating] SW calibration Done
8370 22:13:05.986461 ==
8371 22:13:05.989685 Dram Type= 6, Freq= 0, CH_1, rank 0
8372 22:13:05.993101 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8373 22:13:05.993238 ==
8374 22:13:05.996396 RX Vref Scan: 0
8375 22:13:05.996507
8376 22:13:05.999400 RX Vref 0 -> 0, step: 1
8377 22:13:05.999502
8378 22:13:05.999564 RX Delay 0 -> 252, step: 8
8379 22:13:06.006376 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8380 22:13:06.009346 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8381 22:13:06.012872 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8382 22:13:06.016440 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8383 22:13:06.020030 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8384 22:13:06.026107 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8385 22:13:06.029931 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8386 22:13:06.032845 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8387 22:13:06.035868 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8388 22:13:06.039621 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8389 22:13:06.045799 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8390 22:13:06.049430 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8391 22:13:06.052593 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8392 22:13:06.056253 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
8393 22:13:06.059546 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8394 22:13:06.065737 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8395 22:13:06.065822 ==
8396 22:13:06.069366 Dram Type= 6, Freq= 0, CH_1, rank 0
8397 22:13:06.073119 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8398 22:13:06.073225 ==
8399 22:13:06.073315 DQS Delay:
8400 22:13:06.075873 DQS0 = 0, DQS1 = 0
8401 22:13:06.075959 DQM Delay:
8402 22:13:06.079375 DQM0 = 135, DQM1 = 132
8403 22:13:06.079468 DQ Delay:
8404 22:13:06.082566 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8405 22:13:06.086088 DQ4 =131, DQ5 =147, DQ6 =143, DQ7 =135
8406 22:13:06.089150 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8407 22:13:06.092915 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =139
8408 22:13:06.093011
8409 22:13:06.093075
8410 22:13:06.095927 ==
8411 22:13:06.099678 Dram Type= 6, Freq= 0, CH_1, rank 0
8412 22:13:06.102500 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8413 22:13:06.102588 ==
8414 22:13:06.102650
8415 22:13:06.102715
8416 22:13:06.106130 TX Vref Scan disable
8417 22:13:06.106201 == TX Byte 0 ==
8418 22:13:06.109011 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8419 22:13:06.115926 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8420 22:13:06.116029 == TX Byte 1 ==
8421 22:13:06.122097 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8422 22:13:06.125556 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8423 22:13:06.125630 ==
8424 22:13:06.129224 Dram Type= 6, Freq= 0, CH_1, rank 0
8425 22:13:06.132154 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8426 22:13:06.132251 ==
8427 22:13:06.145106
8428 22:13:06.148993 TX Vref early break, caculate TX vref
8429 22:13:06.152025 TX Vref=16, minBit 9, minWin=22, winSum=378
8430 22:13:06.155241 TX Vref=18, minBit 1, minWin=23, winSum=386
8431 22:13:06.158791 TX Vref=20, minBit 1, minWin=24, winSum=400
8432 22:13:06.161899 TX Vref=22, minBit 1, minWin=24, winSum=404
8433 22:13:06.165113 TX Vref=24, minBit 1, minWin=25, winSum=419
8434 22:13:06.171690 TX Vref=26, minBit 1, minWin=25, winSum=426
8435 22:13:06.175449 TX Vref=28, minBit 0, minWin=25, winSum=429
8436 22:13:06.178541 TX Vref=30, minBit 6, minWin=24, winSum=419
8437 22:13:06.181764 TX Vref=32, minBit 0, minWin=24, winSum=415
8438 22:13:06.185127 TX Vref=34, minBit 6, minWin=23, winSum=402
8439 22:13:06.191592 [TxChooseVref] Worse bit 0, Min win 25, Win sum 429, Final Vref 28
8440 22:13:06.191709
8441 22:13:06.194875 Final TX Range 0 Vref 28
8442 22:13:06.195006
8443 22:13:06.195146 ==
8444 22:13:06.198702 Dram Type= 6, Freq= 0, CH_1, rank 0
8445 22:13:06.202099 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8446 22:13:06.202200 ==
8447 22:13:06.202289
8448 22:13:06.202379
8449 22:13:06.205003 TX Vref Scan disable
8450 22:13:06.211636 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8451 22:13:06.211739 == TX Byte 0 ==
8452 22:13:06.214918 u2DelayCellOfst[0]=16 cells (5 PI)
8453 22:13:06.218172 u2DelayCellOfst[1]=10 cells (3 PI)
8454 22:13:06.221527 u2DelayCellOfst[2]=0 cells (0 PI)
8455 22:13:06.224876 u2DelayCellOfst[3]=6 cells (2 PI)
8456 22:13:06.228473 u2DelayCellOfst[4]=6 cells (2 PI)
8457 22:13:06.231760 u2DelayCellOfst[5]=16 cells (5 PI)
8458 22:13:06.234583 u2DelayCellOfst[6]=16 cells (5 PI)
8459 22:13:06.234681 u2DelayCellOfst[7]=3 cells (1 PI)
8460 22:13:06.241923 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8461 22:13:06.244948 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8462 22:13:06.245044 == TX Byte 1 ==
8463 22:13:06.248185 u2DelayCellOfst[8]=0 cells (0 PI)
8464 22:13:06.251787 u2DelayCellOfst[9]=3 cells (1 PI)
8465 22:13:06.255072 u2DelayCellOfst[10]=10 cells (3 PI)
8466 22:13:06.257982 u2DelayCellOfst[11]=3 cells (1 PI)
8467 22:13:06.261662 u2DelayCellOfst[12]=16 cells (5 PI)
8468 22:13:06.265335 u2DelayCellOfst[13]=16 cells (5 PI)
8469 22:13:06.268437 u2DelayCellOfst[14]=16 cells (5 PI)
8470 22:13:06.271675 u2DelayCellOfst[15]=16 cells (5 PI)
8471 22:13:06.274888 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8472 22:13:06.281696 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8473 22:13:06.281800 DramC Write-DBI on
8474 22:13:06.281889 ==
8475 22:13:06.284738 Dram Type= 6, Freq= 0, CH_1, rank 0
8476 22:13:06.288518 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8477 22:13:06.288616 ==
8478 22:13:06.288683
8479 22:13:06.291416
8480 22:13:06.291553 TX Vref Scan disable
8481 22:13:06.295077 == TX Byte 0 ==
8482 22:13:06.298193 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8483 22:13:06.301408 == TX Byte 1 ==
8484 22:13:06.304902 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8485 22:13:06.305001 DramC Write-DBI off
8486 22:13:06.305098
8487 22:13:06.308516 [DATLAT]
8488 22:13:06.308616 Freq=1600, CH1 RK0
8489 22:13:06.308712
8490 22:13:06.311417 DATLAT Default: 0xf
8491 22:13:06.311516 0, 0xFFFF, sum = 0
8492 22:13:06.314934 1, 0xFFFF, sum = 0
8493 22:13:06.315034 2, 0xFFFF, sum = 0
8494 22:13:06.317950 3, 0xFFFF, sum = 0
8495 22:13:06.318025 4, 0xFFFF, sum = 0
8496 22:13:06.321451 5, 0xFFFF, sum = 0
8497 22:13:06.321573 6, 0xFFFF, sum = 0
8498 22:13:06.324407 7, 0xFFFF, sum = 0
8499 22:13:06.327927 8, 0xFFFF, sum = 0
8500 22:13:06.328025 9, 0xFFFF, sum = 0
8501 22:13:06.331587 10, 0xFFFF, sum = 0
8502 22:13:06.331715 11, 0xFFFF, sum = 0
8503 22:13:06.334885 12, 0xFFFF, sum = 0
8504 22:13:06.334997 13, 0xFFFF, sum = 0
8505 22:13:06.337972 14, 0x0, sum = 1
8506 22:13:06.338080 15, 0x0, sum = 2
8507 22:13:06.341499 16, 0x0, sum = 3
8508 22:13:06.341630 17, 0x0, sum = 4
8509 22:13:06.344457 best_step = 15
8510 22:13:06.344552
8511 22:13:06.344645 ==
8512 22:13:06.347590 Dram Type= 6, Freq= 0, CH_1, rank 0
8513 22:13:06.351119 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8514 22:13:06.351223 ==
8515 22:13:06.351318 RX Vref Scan: 1
8516 22:13:06.354755
8517 22:13:06.354851 Set Vref Range= 24 -> 127
8518 22:13:06.354938
8519 22:13:06.357907 RX Vref 24 -> 127, step: 1
8520 22:13:06.358002
8521 22:13:06.360989 RX Delay 27 -> 252, step: 4
8522 22:13:06.361092
8523 22:13:06.364782 Set Vref, RX VrefLevel [Byte0]: 24
8524 22:13:06.367789 [Byte1]: 24
8525 22:13:06.367890
8526 22:13:06.370832 Set Vref, RX VrefLevel [Byte0]: 25
8527 22:13:06.374476 [Byte1]: 25
8528 22:13:06.374549
8529 22:13:06.377836 Set Vref, RX VrefLevel [Byte0]: 26
8530 22:13:06.380952 [Byte1]: 26
8531 22:13:06.384554
8532 22:13:06.384659 Set Vref, RX VrefLevel [Byte0]: 27
8533 22:13:06.387807 [Byte1]: 27
8534 22:13:06.392080
8535 22:13:06.392191 Set Vref, RX VrefLevel [Byte0]: 28
8536 22:13:06.395502 [Byte1]: 28
8537 22:13:06.399821
8538 22:13:06.399924 Set Vref, RX VrefLevel [Byte0]: 29
8539 22:13:06.403362 [Byte1]: 29
8540 22:13:06.407070
8541 22:13:06.407169 Set Vref, RX VrefLevel [Byte0]: 30
8542 22:13:06.410722 [Byte1]: 30
8543 22:13:06.414967
8544 22:13:06.415048 Set Vref, RX VrefLevel [Byte0]: 31
8545 22:13:06.418044 [Byte1]: 31
8546 22:13:06.422108
8547 22:13:06.422205 Set Vref, RX VrefLevel [Byte0]: 32
8548 22:13:06.425778 [Byte1]: 32
8549 22:13:06.429666
8550 22:13:06.429746 Set Vref, RX VrefLevel [Byte0]: 33
8551 22:13:06.433167 [Byte1]: 33
8552 22:13:06.437298
8553 22:13:06.437379 Set Vref, RX VrefLevel [Byte0]: 34
8554 22:13:06.440971 [Byte1]: 34
8555 22:13:06.445177
8556 22:13:06.445276 Set Vref, RX VrefLevel [Byte0]: 35
8557 22:13:06.448075 [Byte1]: 35
8558 22:13:06.452244
8559 22:13:06.452348 Set Vref, RX VrefLevel [Byte0]: 36
8560 22:13:06.456076 [Byte1]: 36
8561 22:13:06.460300
8562 22:13:06.460408 Set Vref, RX VrefLevel [Byte0]: 37
8563 22:13:06.463478 [Byte1]: 37
8564 22:13:06.467721
8565 22:13:06.467819 Set Vref, RX VrefLevel [Byte0]: 38
8566 22:13:06.470867 [Byte1]: 38
8567 22:13:06.475163
8568 22:13:06.475262 Set Vref, RX VrefLevel [Byte0]: 39
8569 22:13:06.478218 [Byte1]: 39
8570 22:13:06.482583
8571 22:13:06.482657 Set Vref, RX VrefLevel [Byte0]: 40
8572 22:13:06.485546 [Byte1]: 40
8573 22:13:06.489924
8574 22:13:06.489997 Set Vref, RX VrefLevel [Byte0]: 41
8575 22:13:06.493770 [Byte1]: 41
8576 22:13:06.497423
8577 22:13:06.497527 Set Vref, RX VrefLevel [Byte0]: 42
8578 22:13:06.500773 [Byte1]: 42
8579 22:13:06.505318
8580 22:13:06.505414 Set Vref, RX VrefLevel [Byte0]: 43
8581 22:13:06.508347 [Byte1]: 43
8582 22:13:06.512634
8583 22:13:06.512736 Set Vref, RX VrefLevel [Byte0]: 44
8584 22:13:06.516095 [Byte1]: 44
8585 22:13:06.520463
8586 22:13:06.520543 Set Vref, RX VrefLevel [Byte0]: 45
8587 22:13:06.523605 [Byte1]: 45
8588 22:13:06.527728
8589 22:13:06.527840 Set Vref, RX VrefLevel [Byte0]: 46
8590 22:13:06.531369 [Byte1]: 46
8591 22:13:06.535349
8592 22:13:06.535430 Set Vref, RX VrefLevel [Byte0]: 47
8593 22:13:06.538474 [Byte1]: 47
8594 22:13:06.543034
8595 22:13:06.543115 Set Vref, RX VrefLevel [Byte0]: 48
8596 22:13:06.546098 [Byte1]: 48
8597 22:13:06.550132
8598 22:13:06.550213 Set Vref, RX VrefLevel [Byte0]: 49
8599 22:13:06.553622 [Byte1]: 49
8600 22:13:06.558351
8601 22:13:06.558432 Set Vref, RX VrefLevel [Byte0]: 50
8602 22:13:06.561269 [Byte1]: 50
8603 22:13:06.565440
8604 22:13:06.565546 Set Vref, RX VrefLevel [Byte0]: 51
8605 22:13:06.568767 [Byte1]: 51
8606 22:13:06.573056
8607 22:13:06.573159 Set Vref, RX VrefLevel [Byte0]: 52
8608 22:13:06.576120 [Byte1]: 52
8609 22:13:06.580366
8610 22:13:06.580440 Set Vref, RX VrefLevel [Byte0]: 53
8611 22:13:06.583780 [Byte1]: 53
8612 22:13:06.588214
8613 22:13:06.588295 Set Vref, RX VrefLevel [Byte0]: 54
8614 22:13:06.591291 [Byte1]: 54
8615 22:13:06.595588
8616 22:13:06.595685 Set Vref, RX VrefLevel [Byte0]: 55
8617 22:13:06.598837 [Byte1]: 55
8618 22:13:06.603140
8619 22:13:06.603225 Set Vref, RX VrefLevel [Byte0]: 56
8620 22:13:06.606509 [Byte1]: 56
8621 22:13:06.610474
8622 22:13:06.610565 Set Vref, RX VrefLevel [Byte0]: 57
8623 22:13:06.613744 [Byte1]: 57
8624 22:13:06.618147
8625 22:13:06.618224 Set Vref, RX VrefLevel [Byte0]: 58
8626 22:13:06.621174 [Byte1]: 58
8627 22:13:06.625816
8628 22:13:06.625904 Set Vref, RX VrefLevel [Byte0]: 59
8629 22:13:06.628796 [Byte1]: 59
8630 22:13:06.633187
8631 22:13:06.633282 Set Vref, RX VrefLevel [Byte0]: 60
8632 22:13:06.636537 [Byte1]: 60
8633 22:13:06.640820
8634 22:13:06.640912 Set Vref, RX VrefLevel [Byte0]: 61
8635 22:13:06.644236 [Byte1]: 61
8636 22:13:06.648544
8637 22:13:06.648666 Set Vref, RX VrefLevel [Byte0]: 62
8638 22:13:06.651475 [Byte1]: 62
8639 22:13:06.656075
8640 22:13:06.656260 Set Vref, RX VrefLevel [Byte0]: 63
8641 22:13:06.658949 [Byte1]: 63
8642 22:13:06.663228
8643 22:13:06.663301 Set Vref, RX VrefLevel [Byte0]: 64
8644 22:13:06.666815 [Byte1]: 64
8645 22:13:06.671319
8646 22:13:06.671392 Set Vref, RX VrefLevel [Byte0]: 65
8647 22:13:06.673880 [Byte1]: 65
8648 22:13:06.678284
8649 22:13:06.678355 Set Vref, RX VrefLevel [Byte0]: 66
8650 22:13:06.681430 [Byte1]: 66
8651 22:13:06.685775
8652 22:13:06.685853 Set Vref, RX VrefLevel [Byte0]: 67
8653 22:13:06.689226 [Byte1]: 67
8654 22:13:06.693583
8655 22:13:06.693658 Set Vref, RX VrefLevel [Byte0]: 68
8656 22:13:06.696609 [Byte1]: 68
8657 22:13:06.701004
8658 22:13:06.701082 Set Vref, RX VrefLevel [Byte0]: 69
8659 22:13:06.704483 [Byte1]: 69
8660 22:13:06.708381
8661 22:13:06.708459 Set Vref, RX VrefLevel [Byte0]: 70
8662 22:13:06.712122 [Byte1]: 70
8663 22:13:06.716157
8664 22:13:06.716235 Set Vref, RX VrefLevel [Byte0]: 71
8665 22:13:06.719735 [Byte1]: 71
8666 22:13:06.723701
8667 22:13:06.723803 Set Vref, RX VrefLevel [Byte0]: 72
8668 22:13:06.726742 [Byte1]: 72
8669 22:13:06.731178
8670 22:13:06.731277 Set Vref, RX VrefLevel [Byte0]: 73
8671 22:13:06.734902 [Byte1]: 73
8672 22:13:06.738888
8673 22:13:06.738991 Set Vref, RX VrefLevel [Byte0]: 74
8674 22:13:06.741999 [Byte1]: 74
8675 22:13:06.745936
8676 22:13:06.746038 Set Vref, RX VrefLevel [Byte0]: 75
8677 22:13:06.749586 [Byte1]: 75
8678 22:13:06.753826
8679 22:13:06.753900 Set Vref, RX VrefLevel [Byte0]: 76
8680 22:13:06.757298 [Byte1]: 76
8681 22:13:06.761311
8682 22:13:06.761412 Set Vref, RX VrefLevel [Byte0]: 77
8683 22:13:06.764328 [Byte1]: 77
8684 22:13:06.768739
8685 22:13:06.768838 Final RX Vref Byte 0 = 67 to rank0
8686 22:13:06.772176 Final RX Vref Byte 1 = 56 to rank0
8687 22:13:06.775261 Final RX Vref Byte 0 = 67 to rank1
8688 22:13:06.778437 Final RX Vref Byte 1 = 56 to rank1==
8689 22:13:06.782230 Dram Type= 6, Freq= 0, CH_1, rank 0
8690 22:13:06.788507 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8691 22:13:06.788596 ==
8692 22:13:06.788659 DQS Delay:
8693 22:13:06.788718 DQS0 = 0, DQS1 = 0
8694 22:13:06.792114 DQM Delay:
8695 22:13:06.792183 DQM0 = 134, DQM1 = 131
8696 22:13:06.795358 DQ Delay:
8697 22:13:06.798995 DQ0 =140, DQ1 =128, DQ2 =122, DQ3 =130
8698 22:13:06.801937 DQ4 =134, DQ5 =146, DQ6 =144, DQ7 =134
8699 22:13:06.805167 DQ8 =116, DQ9 =122, DQ10 =132, DQ11 =124
8700 22:13:06.808445 DQ12 =138, DQ13 =140, DQ14 =140, DQ15 =140
8701 22:13:06.808518
8702 22:13:06.808579
8703 22:13:06.808637
8704 22:13:06.812095 [DramC_TX_OE_Calibration] TA2
8705 22:13:06.815069 Original DQ_B0 (3 6) =30, OEN = 27
8706 22:13:06.818737 Original DQ_B1 (3 6) =30, OEN = 27
8707 22:13:06.821760 24, 0x0, End_B0=24 End_B1=24
8708 22:13:06.821836 25, 0x0, End_B0=25 End_B1=25
8709 22:13:06.825359 26, 0x0, End_B0=26 End_B1=26
8710 22:13:06.828621 27, 0x0, End_B0=27 End_B1=27
8711 22:13:06.832074 28, 0x0, End_B0=28 End_B1=28
8712 22:13:06.835159 29, 0x0, End_B0=29 End_B1=29
8713 22:13:06.835265 30, 0x0, End_B0=30 End_B1=30
8714 22:13:06.838928 31, 0x4141, End_B0=30 End_B1=30
8715 22:13:06.842055 Byte0 end_step=30 best_step=27
8716 22:13:06.844917 Byte1 end_step=30 best_step=27
8717 22:13:06.848413 Byte0 TX OE(2T, 0.5T) = (3, 3)
8718 22:13:06.851533 Byte1 TX OE(2T, 0.5T) = (3, 3)
8719 22:13:06.851630
8720 22:13:06.851730
8721 22:13:06.858027 [DQSOSCAuto] RK0, (LSB)MR18= 0x1927, (MSB)MR19= 0x303, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
8722 22:13:06.861629 CH1 RK0: MR19=303, MR18=1927
8723 22:13:06.868233 CH1_RK0: MR19=0x303, MR18=0x1927, DQSOSC=390, MR23=63, INC=24, DEC=16
8724 22:13:06.868332
8725 22:13:06.871543 ----->DramcWriteLeveling(PI) begin...
8726 22:13:06.871643 ==
8727 22:13:06.874718 Dram Type= 6, Freq= 0, CH_1, rank 1
8728 22:13:06.878140 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8729 22:13:06.878209 ==
8730 22:13:06.881219 Write leveling (Byte 0): 25 => 25
8731 22:13:06.885005 Write leveling (Byte 1): 28 => 28
8732 22:13:06.888185 DramcWriteLeveling(PI) end<-----
8733 22:13:06.888279
8734 22:13:06.888366 ==
8735 22:13:06.891102 Dram Type= 6, Freq= 0, CH_1, rank 1
8736 22:13:06.894967 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8737 22:13:06.895051 ==
8738 22:13:06.898123 [Gating] SW mode calibration
8739 22:13:06.904700 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8740 22:13:06.911478 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8741 22:13:06.914655 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8742 22:13:06.920999 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8743 22:13:06.925038 1 4 8 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
8744 22:13:06.927954 1 4 12 | B1->B0 | 3434 2e2d | 0 1 | (0 0) (1 1)
8745 22:13:06.931503 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8746 22:13:06.937931 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8747 22:13:06.941193 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8748 22:13:06.944945 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8749 22:13:06.951048 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8750 22:13:06.954328 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8751 22:13:06.957808 1 5 8 | B1->B0 | 3030 3434 | 0 1 | (0 1) (1 0)
8752 22:13:06.964379 1 5 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8753 22:13:06.967942 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8754 22:13:06.970920 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8755 22:13:06.978123 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8756 22:13:06.981045 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8757 22:13:06.984551 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8758 22:13:06.990835 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8759 22:13:06.994673 1 6 8 | B1->B0 | 3333 2424 | 1 0 | (0 0) (0 0)
8760 22:13:06.997823 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8761 22:13:07.004144 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8762 22:13:07.007676 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8763 22:13:07.011089 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8764 22:13:07.017216 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8765 22:13:07.020446 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8766 22:13:07.024001 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8767 22:13:07.030502 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8768 22:13:07.034193 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8769 22:13:07.037061 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8770 22:13:07.044157 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8771 22:13:07.047310 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8772 22:13:07.050667 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8773 22:13:07.057222 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8774 22:13:07.060220 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8775 22:13:07.063687 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8776 22:13:07.070661 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8777 22:13:07.073437 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8778 22:13:07.076903 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8779 22:13:07.083474 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8780 22:13:07.086791 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8781 22:13:07.090318 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8782 22:13:07.096877 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8783 22:13:07.099910 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8784 22:13:07.103111 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8785 22:13:07.106968 Total UI for P1: 0, mck2ui 16
8786 22:13:07.110108 best dqsien dly found for B1: ( 1, 9, 8)
8787 22:13:07.116617 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8788 22:13:07.116744 Total UI for P1: 0, mck2ui 16
8789 22:13:07.119626 best dqsien dly found for B0: ( 1, 9, 12)
8790 22:13:07.126412 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8791 22:13:07.130035 best DQS1 dly(MCK, UI, PI) = (1, 9, 8)
8792 22:13:07.130112
8793 22:13:07.133206 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8794 22:13:07.136358 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 8)
8795 22:13:07.140011 [Gating] SW calibration Done
8796 22:13:07.140117 ==
8797 22:13:07.143099 Dram Type= 6, Freq= 0, CH_1, rank 1
8798 22:13:07.146871 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8799 22:13:07.146976 ==
8800 22:13:07.149812 RX Vref Scan: 0
8801 22:13:07.149884
8802 22:13:07.149947 RX Vref 0 -> 0, step: 1
8803 22:13:07.150008
8804 22:13:07.153390 RX Delay 0 -> 252, step: 8
8805 22:13:07.156323 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8806 22:13:07.159905 iDelay=208, Bit 1, Center 131 (80 ~ 183) 104
8807 22:13:07.166315 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8808 22:13:07.169781 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8809 22:13:07.172795 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8810 22:13:07.176107 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8811 22:13:07.179721 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8812 22:13:07.186189 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8813 22:13:07.189779 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8814 22:13:07.192998 iDelay=208, Bit 9, Center 123 (64 ~ 183) 120
8815 22:13:07.196060 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8816 22:13:07.202886 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8817 22:13:07.206618 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8818 22:13:07.209948 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8819 22:13:07.213127 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8820 22:13:07.216207 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8821 22:13:07.219443 ==
8822 22:13:07.219527 Dram Type= 6, Freq= 0, CH_1, rank 1
8823 22:13:07.225925 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8824 22:13:07.226009 ==
8825 22:13:07.226075 DQS Delay:
8826 22:13:07.229328 DQS0 = 0, DQS1 = 0
8827 22:13:07.229410 DQM Delay:
8828 22:13:07.232929 DQM0 = 136, DQM1 = 134
8829 22:13:07.233021 DQ Delay:
8830 22:13:07.236039 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =131
8831 22:13:07.239269 DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135
8832 22:13:07.242835 DQ8 =119, DQ9 =123, DQ10 =135, DQ11 =127
8833 22:13:07.246025 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8834 22:13:07.246107
8835 22:13:07.246171
8836 22:13:07.246231 ==
8837 22:13:07.249084 Dram Type= 6, Freq= 0, CH_1, rank 1
8838 22:13:07.255746 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8839 22:13:07.255849 ==
8840 22:13:07.255955
8841 22:13:07.256049
8842 22:13:07.256144 TX Vref Scan disable
8843 22:13:07.259777 == TX Byte 0 ==
8844 22:13:07.263001 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8845 22:13:07.265974 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8846 22:13:07.269197 == TX Byte 1 ==
8847 22:13:07.272739 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8848 22:13:07.279032 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8849 22:13:07.279116 ==
8850 22:13:07.282349 Dram Type= 6, Freq= 0, CH_1, rank 1
8851 22:13:07.286109 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8852 22:13:07.286191 ==
8853 22:13:07.299114
8854 22:13:07.302744 TX Vref early break, caculate TX vref
8855 22:13:07.305898 TX Vref=16, minBit 0, minWin=23, winSum=381
8856 22:13:07.309479 TX Vref=18, minBit 0, minWin=23, winSum=393
8857 22:13:07.312253 TX Vref=20, minBit 0, minWin=24, winSum=400
8858 22:13:07.315585 TX Vref=22, minBit 0, minWin=24, winSum=410
8859 22:13:07.319227 TX Vref=24, minBit 0, minWin=25, winSum=422
8860 22:13:07.325682 TX Vref=26, minBit 0, minWin=25, winSum=426
8861 22:13:07.328814 TX Vref=28, minBit 0, minWin=25, winSum=423
8862 22:13:07.332452 TX Vref=30, minBit 6, minWin=25, winSum=422
8863 22:13:07.335954 TX Vref=32, minBit 0, minWin=24, winSum=412
8864 22:13:07.338897 TX Vref=34, minBit 0, minWin=24, winSum=407
8865 22:13:07.342203 TX Vref=36, minBit 6, minWin=23, winSum=397
8866 22:13:07.349391 [TxChooseVref] Worse bit 0, Min win 25, Win sum 426, Final Vref 26
8867 22:13:07.349516
8868 22:13:07.352643 Final TX Range 0 Vref 26
8869 22:13:07.352727
8870 22:13:07.352809 ==
8871 22:13:07.355809 Dram Type= 6, Freq= 0, CH_1, rank 1
8872 22:13:07.359167 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8873 22:13:07.359275 ==
8874 22:13:07.359376
8875 22:13:07.359502
8876 22:13:07.362503 TX Vref Scan disable
8877 22:13:07.368765 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8878 22:13:07.368859 == TX Byte 0 ==
8879 22:13:07.372084 u2DelayCellOfst[0]=16 cells (5 PI)
8880 22:13:07.375251 u2DelayCellOfst[1]=10 cells (3 PI)
8881 22:13:07.378962 u2DelayCellOfst[2]=0 cells (0 PI)
8882 22:13:07.382025 u2DelayCellOfst[3]=6 cells (2 PI)
8883 22:13:07.385438 u2DelayCellOfst[4]=6 cells (2 PI)
8884 22:13:07.388567 u2DelayCellOfst[5]=16 cells (5 PI)
8885 22:13:07.392135 u2DelayCellOfst[6]=16 cells (5 PI)
8886 22:13:07.395446 u2DelayCellOfst[7]=6 cells (2 PI)
8887 22:13:07.398673 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8888 22:13:07.402063 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8889 22:13:07.405411 == TX Byte 1 ==
8890 22:13:07.408462 u2DelayCellOfst[8]=0 cells (0 PI)
8891 22:13:07.411951 u2DelayCellOfst[9]=6 cells (2 PI)
8892 22:13:07.412032 u2DelayCellOfst[10]=13 cells (4 PI)
8893 22:13:07.415534 u2DelayCellOfst[11]=6 cells (2 PI)
8894 22:13:07.418642 u2DelayCellOfst[12]=16 cells (5 PI)
8895 22:13:07.422227 u2DelayCellOfst[13]=16 cells (5 PI)
8896 22:13:07.425455 u2DelayCellOfst[14]=20 cells (6 PI)
8897 22:13:07.428505 u2DelayCellOfst[15]=20 cells (6 PI)
8898 22:13:07.432420 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8899 22:13:07.438468 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8900 22:13:07.438604 DramC Write-DBI on
8901 22:13:07.438709 ==
8902 22:13:07.441987 Dram Type= 6, Freq= 0, CH_1, rank 1
8903 22:13:07.448649 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8904 22:13:07.448732 ==
8905 22:13:07.448797
8906 22:13:07.448855
8907 22:13:07.448926 TX Vref Scan disable
8908 22:13:07.452320 == TX Byte 0 ==
8909 22:13:07.455540 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8910 22:13:07.458703 == TX Byte 1 ==
8911 22:13:07.462224 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8912 22:13:07.465470 DramC Write-DBI off
8913 22:13:07.465601
8914 22:13:07.465665 [DATLAT]
8915 22:13:07.465723 Freq=1600, CH1 RK1
8916 22:13:07.465780
8917 22:13:07.468561 DATLAT Default: 0xf
8918 22:13:07.472231 0, 0xFFFF, sum = 0
8919 22:13:07.472317 1, 0xFFFF, sum = 0
8920 22:13:07.475118 2, 0xFFFF, sum = 0
8921 22:13:07.475202 3, 0xFFFF, sum = 0
8922 22:13:07.478558 4, 0xFFFF, sum = 0
8923 22:13:07.478643 5, 0xFFFF, sum = 0
8924 22:13:07.482479 6, 0xFFFF, sum = 0
8925 22:13:07.482563 7, 0xFFFF, sum = 0
8926 22:13:07.485442 8, 0xFFFF, sum = 0
8927 22:13:07.485574 9, 0xFFFF, sum = 0
8928 22:13:07.488807 10, 0xFFFF, sum = 0
8929 22:13:07.488892 11, 0xFFFF, sum = 0
8930 22:13:07.491659 12, 0xFFFF, sum = 0
8931 22:13:07.491756 13, 0xFFFF, sum = 0
8932 22:13:07.495085 14, 0x0, sum = 1
8933 22:13:07.495183 15, 0x0, sum = 2
8934 22:13:07.498471 16, 0x0, sum = 3
8935 22:13:07.498559 17, 0x0, sum = 4
8936 22:13:07.502051 best_step = 15
8937 22:13:07.502137
8938 22:13:07.502219 ==
8939 22:13:07.504955 Dram Type= 6, Freq= 0, CH_1, rank 1
8940 22:13:07.508366 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8941 22:13:07.508450 ==
8942 22:13:07.511882 RX Vref Scan: 0
8943 22:13:07.511990
8944 22:13:07.512072 RX Vref 0 -> 0, step: 1
8945 22:13:07.512150
8946 22:13:07.515341 RX Delay 19 -> 252, step: 4
8947 22:13:07.521920 iDelay=199, Bit 0, Center 140 (91 ~ 190) 100
8948 22:13:07.525001 iDelay=199, Bit 1, Center 130 (83 ~ 178) 96
8949 22:13:07.528266 iDelay=199, Bit 2, Center 122 (75 ~ 170) 96
8950 22:13:07.532041 iDelay=199, Bit 3, Center 128 (83 ~ 174) 92
8951 22:13:07.535130 iDelay=199, Bit 4, Center 132 (83 ~ 182) 100
8952 22:13:07.538681 iDelay=199, Bit 5, Center 148 (99 ~ 198) 100
8953 22:13:07.545039 iDelay=199, Bit 6, Center 144 (95 ~ 194) 100
8954 22:13:07.548556 iDelay=199, Bit 7, Center 132 (83 ~ 182) 100
8955 22:13:07.551636 iDelay=199, Bit 8, Center 118 (67 ~ 170) 104
8956 22:13:07.555276 iDelay=199, Bit 9, Center 118 (67 ~ 170) 104
8957 22:13:07.558337 iDelay=199, Bit 10, Center 132 (83 ~ 182) 100
8958 22:13:07.565340 iDelay=199, Bit 11, Center 124 (71 ~ 178) 108
8959 22:13:07.568796 iDelay=199, Bit 12, Center 140 (87 ~ 194) 108
8960 22:13:07.571846 iDelay=199, Bit 13, Center 138 (87 ~ 190) 104
8961 22:13:07.575126 iDelay=199, Bit 14, Center 136 (87 ~ 186) 100
8962 22:13:07.578133 iDelay=199, Bit 15, Center 138 (87 ~ 190) 104
8963 22:13:07.581740 ==
8964 22:13:07.585231 Dram Type= 6, Freq= 0, CH_1, rank 1
8965 22:13:07.588060 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8966 22:13:07.588168 ==
8967 22:13:07.588265 DQS Delay:
8968 22:13:07.591870 DQS0 = 0, DQS1 = 0
8969 22:13:07.591980 DQM Delay:
8970 22:13:07.594902 DQM0 = 134, DQM1 = 130
8971 22:13:07.595001 DQ Delay:
8972 22:13:07.598580 DQ0 =140, DQ1 =130, DQ2 =122, DQ3 =128
8973 22:13:07.601450 DQ4 =132, DQ5 =148, DQ6 =144, DQ7 =132
8974 22:13:07.604823 DQ8 =118, DQ9 =118, DQ10 =132, DQ11 =124
8975 22:13:07.608405 DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =138
8976 22:13:07.608501
8977 22:13:07.608600
8978 22:13:07.608687
8979 22:13:07.611709 [DramC_TX_OE_Calibration] TA2
8980 22:13:07.615207 Original DQ_B0 (3 6) =30, OEN = 27
8981 22:13:07.618197 Original DQ_B1 (3 6) =30, OEN = 27
8982 22:13:07.621489 24, 0x0, End_B0=24 End_B1=24
8983 22:13:07.624890 25, 0x0, End_B0=25 End_B1=25
8984 22:13:07.624992 26, 0x0, End_B0=26 End_B1=26
8985 22:13:07.628477 27, 0x0, End_B0=27 End_B1=27
8986 22:13:07.631332 28, 0x0, End_B0=28 End_B1=28
8987 22:13:07.634994 29, 0x0, End_B0=29 End_B1=29
8988 22:13:07.638325 30, 0x0, End_B0=30 End_B1=30
8989 22:13:07.638452 31, 0x5151, End_B0=30 End_B1=30
8990 22:13:07.641407 Byte0 end_step=30 best_step=27
8991 22:13:07.644511 Byte1 end_step=30 best_step=27
8992 22:13:07.648072 Byte0 TX OE(2T, 0.5T) = (3, 3)
8993 22:13:07.651198 Byte1 TX OE(2T, 0.5T) = (3, 3)
8994 22:13:07.651279
8995 22:13:07.651344
8996 22:13:07.657903 [DQSOSCAuto] RK1, (LSB)MR18= 0x2209, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 392 ps
8997 22:13:07.661467 CH1 RK1: MR19=303, MR18=2209
8998 22:13:07.667728 CH1_RK1: MR19=0x303, MR18=0x2209, DQSOSC=392, MR23=63, INC=24, DEC=16
8999 22:13:07.671408 [RxdqsGatingPostProcess] freq 1600
9000 22:13:07.678021 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9001 22:13:07.678103 best DQS0 dly(2T, 0.5T) = (1, 1)
9002 22:13:07.681147 best DQS1 dly(2T, 0.5T) = (1, 1)
9003 22:13:07.684383 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9004 22:13:07.687822 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9005 22:13:07.691394 best DQS0 dly(2T, 0.5T) = (1, 1)
9006 22:13:07.694773 best DQS1 dly(2T, 0.5T) = (1, 1)
9007 22:13:07.697645 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9008 22:13:07.701094 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9009 22:13:07.704768 Pre-setting of DQS Precalculation
9010 22:13:07.707754 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9011 22:13:07.718041 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9012 22:13:07.724471 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9013 22:13:07.724550
9014 22:13:07.724618
9015 22:13:07.727984 [Calibration Summary] 3200 Mbps
9016 22:13:07.728069 CH 0, Rank 0
9017 22:13:07.730993 SW Impedance : PASS
9018 22:13:07.731082 DUTY Scan : NO K
9019 22:13:07.734522 ZQ Calibration : PASS
9020 22:13:07.737943 Jitter Meter : NO K
9021 22:13:07.738020 CBT Training : PASS
9022 22:13:07.741339 Write leveling : PASS
9023 22:13:07.744394 RX DQS gating : PASS
9024 22:13:07.744469 RX DQ/DQS(RDDQC) : PASS
9025 22:13:07.747473 TX DQ/DQS : PASS
9026 22:13:07.747545 RX DATLAT : PASS
9027 22:13:07.751283 RX DQ/DQS(Engine): PASS
9028 22:13:07.754241 TX OE : PASS
9029 22:13:07.754311 All Pass.
9030 22:13:07.754372
9031 22:13:07.754434 CH 0, Rank 1
9032 22:13:07.757666 SW Impedance : PASS
9033 22:13:07.760655 DUTY Scan : NO K
9034 22:13:07.760725 ZQ Calibration : PASS
9035 22:13:07.764059 Jitter Meter : NO K
9036 22:13:07.767725 CBT Training : PASS
9037 22:13:07.767801 Write leveling : PASS
9038 22:13:07.770934 RX DQS gating : PASS
9039 22:13:07.774355 RX DQ/DQS(RDDQC) : PASS
9040 22:13:07.774435 TX DQ/DQS : PASS
9041 22:13:07.777484 RX DATLAT : PASS
9042 22:13:07.780825 RX DQ/DQS(Engine): PASS
9043 22:13:07.780903 TX OE : PASS
9044 22:13:07.784009 All Pass.
9045 22:13:07.784088
9046 22:13:07.784153 CH 1, Rank 0
9047 22:13:07.787932 SW Impedance : PASS
9048 22:13:07.788009 DUTY Scan : NO K
9049 22:13:07.790845 ZQ Calibration : PASS
9050 22:13:07.794005 Jitter Meter : NO K
9051 22:13:07.794080 CBT Training : PASS
9052 22:13:07.797732 Write leveling : PASS
9053 22:13:07.800823 RX DQS gating : PASS
9054 22:13:07.800900 RX DQ/DQS(RDDQC) : PASS
9055 22:13:07.804345 TX DQ/DQS : PASS
9056 22:13:07.804419 RX DATLAT : PASS
9057 22:13:07.807380 RX DQ/DQS(Engine): PASS
9058 22:13:07.810961 TX OE : PASS
9059 22:13:07.811038 All Pass.
9060 22:13:07.811105
9061 22:13:07.811165 CH 1, Rank 1
9062 22:13:07.814103 SW Impedance : PASS
9063 22:13:07.817697 DUTY Scan : NO K
9064 22:13:07.817776 ZQ Calibration : PASS
9065 22:13:07.820753 Jitter Meter : NO K
9066 22:13:07.824482 CBT Training : PASS
9067 22:13:07.824560 Write leveling : PASS
9068 22:13:07.827663 RX DQS gating : PASS
9069 22:13:07.830455 RX DQ/DQS(RDDQC) : PASS
9070 22:13:07.830529 TX DQ/DQS : PASS
9071 22:13:07.833963 RX DATLAT : PASS
9072 22:13:07.837405 RX DQ/DQS(Engine): PASS
9073 22:13:07.837521 TX OE : PASS
9074 22:13:07.840382 All Pass.
9075 22:13:07.840455
9076 22:13:07.840518 DramC Write-DBI on
9077 22:13:07.843832 PER_BANK_REFRESH: Hybrid Mode
9078 22:13:07.843907 TX_TRACKING: ON
9079 22:13:07.854100 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9080 22:13:07.860906 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9081 22:13:07.870758 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9082 22:13:07.874021 [FAST_K] Save calibration result to emmc
9083 22:13:07.877506 sync common calibartion params.
9084 22:13:07.877592 sync cbt_mode0:1, 1:1
9085 22:13:07.880831 dram_init: ddr_geometry: 2
9086 22:13:07.883883 dram_init: ddr_geometry: 2
9087 22:13:07.883958 dram_init: ddr_geometry: 2
9088 22:13:07.887623 0:dram_rank_size:100000000
9089 22:13:07.890860 1:dram_rank_size:100000000
9090 22:13:07.893947 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9091 22:13:07.897737 DFS_SHUFFLE_HW_MODE: ON
9092 22:13:07.900735 dramc_set_vcore_voltage set vcore to 725000
9093 22:13:07.903828 Read voltage for 1600, 0
9094 22:13:07.903896 Vio18 = 0
9095 22:13:07.907262 Vcore = 725000
9096 22:13:07.907329 Vdram = 0
9097 22:13:07.907388 Vddq = 0
9098 22:13:07.907450 Vmddr = 0
9099 22:13:07.910931 switch to 3200 Mbps bootup
9100 22:13:07.913882 [DramcRunTimeConfig]
9101 22:13:07.913957 PHYPLL
9102 22:13:07.917125 DPM_CONTROL_AFTERK: ON
9103 22:13:07.917201 PER_BANK_REFRESH: ON
9104 22:13:07.920602 REFRESH_OVERHEAD_REDUCTION: ON
9105 22:13:07.923773 CMD_PICG_NEW_MODE: OFF
9106 22:13:07.923848 XRTWTW_NEW_MODE: ON
9107 22:13:07.927332 XRTRTR_NEW_MODE: ON
9108 22:13:07.927407 TX_TRACKING: ON
9109 22:13:07.930600 RDSEL_TRACKING: OFF
9110 22:13:07.933494 DQS Precalculation for DVFS: ON
9111 22:13:07.933596 RX_TRACKING: OFF
9112 22:13:07.937205 HW_GATING DBG: ON
9113 22:13:07.937281 ZQCS_ENABLE_LP4: ON
9114 22:13:07.940648 RX_PICG_NEW_MODE: ON
9115 22:13:07.940728 TX_PICG_NEW_MODE: ON
9116 22:13:07.943603 ENABLE_RX_DCM_DPHY: ON
9117 22:13:07.947055 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9118 22:13:07.950244 DUMMY_READ_FOR_TRACKING: OFF
9119 22:13:07.950323 !!! SPM_CONTROL_AFTERK: OFF
9120 22:13:07.953535 !!! SPM could not control APHY
9121 22:13:07.957150 IMPEDANCE_TRACKING: ON
9122 22:13:07.957224 TEMP_SENSOR: ON
9123 22:13:07.960316 HW_SAVE_FOR_SR: OFF
9124 22:13:07.963411 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9125 22:13:07.967008 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9126 22:13:07.967083 Read ODT Tracking: ON
9127 22:13:07.970132 Refresh Rate DeBounce: ON
9128 22:13:07.973405 DFS_NO_QUEUE_FLUSH: ON
9129 22:13:07.976997 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9130 22:13:07.977076 ENABLE_DFS_RUNTIME_MRW: OFF
9131 22:13:07.980687 DDR_RESERVE_NEW_MODE: ON
9132 22:13:07.983489 MR_CBT_SWITCH_FREQ: ON
9133 22:13:07.983567 =========================
9134 22:13:08.003512 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9135 22:13:08.006559 dram_init: ddr_geometry: 2
9136 22:13:08.025108 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9137 22:13:08.028228 dram_init: dram init end (result: 0)
9138 22:13:08.035581 DRAM-K: Full calibration passed in 24461 msecs
9139 22:13:08.038611 MRC: failed to locate region type 0.
9140 22:13:08.038694 DRAM rank0 size:0x100000000,
9141 22:13:08.041699 DRAM rank1 size=0x100000000
9142 22:13:08.051853 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9143 22:13:08.058354 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9144 22:13:08.064930 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9145 22:13:08.071766 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9146 22:13:08.075524 DRAM rank0 size:0x100000000,
9147 22:13:08.078650 DRAM rank1 size=0x100000000
9148 22:13:08.078729 CBMEM:
9149 22:13:08.081465 IMD: root @ 0xfffff000 254 entries.
9150 22:13:08.085261 IMD: root @ 0xffffec00 62 entries.
9151 22:13:08.088124 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9152 22:13:08.091686 WARNING: RO_VPD is uninitialized or empty.
9153 22:13:08.098448 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9154 22:13:08.105051 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9155 22:13:08.117399 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9156 22:13:08.129215 BS: romstage times (exec / console): total (unknown) / 23991 ms
9157 22:13:08.129296
9158 22:13:08.129361
9159 22:13:08.139235 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9160 22:13:08.142533 ARM64: Exception handlers installed.
9161 22:13:08.146158 ARM64: Testing exception
9162 22:13:08.149095 ARM64: Done test exception
9163 22:13:08.149170 Enumerating buses...
9164 22:13:08.152711 Show all devs... Before device enumeration.
9165 22:13:08.155640 Root Device: enabled 1
9166 22:13:08.158905 CPU_CLUSTER: 0: enabled 1
9167 22:13:08.158982 CPU: 00: enabled 1
9168 22:13:08.162483 Compare with tree...
9169 22:13:08.162562 Root Device: enabled 1
9170 22:13:08.165990 CPU_CLUSTER: 0: enabled 1
9171 22:13:08.169542 CPU: 00: enabled 1
9172 22:13:08.169667 Root Device scanning...
9173 22:13:08.172589 scan_static_bus for Root Device
9174 22:13:08.175898 CPU_CLUSTER: 0 enabled
9175 22:13:08.179123 scan_static_bus for Root Device done
9176 22:13:08.182678 scan_bus: bus Root Device finished in 8 msecs
9177 22:13:08.182753 done
9178 22:13:08.189297 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9179 22:13:08.192383 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9180 22:13:08.199287 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9181 22:13:08.202306 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9182 22:13:08.205733 Allocating resources...
9183 22:13:08.205814 Reading resources...
9184 22:13:08.212597 Root Device read_resources bus 0 link: 0
9185 22:13:08.212696 DRAM rank0 size:0x100000000,
9186 22:13:08.215674 DRAM rank1 size=0x100000000
9187 22:13:08.218890 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9188 22:13:08.222189 CPU: 00 missing read_resources
9189 22:13:08.225954 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9190 22:13:08.232397 Root Device read_resources bus 0 link: 0 done
9191 22:13:08.232478 Done reading resources.
9192 22:13:08.239112 Show resources in subtree (Root Device)...After reading.
9193 22:13:08.242411 Root Device child on link 0 CPU_CLUSTER: 0
9194 22:13:08.245606 CPU_CLUSTER: 0 child on link 0 CPU: 00
9195 22:13:08.255483 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9196 22:13:08.255583 CPU: 00
9197 22:13:08.259051 Root Device assign_resources, bus 0 link: 0
9198 22:13:08.261907 CPU_CLUSTER: 0 missing set_resources
9199 22:13:08.265551 Root Device assign_resources, bus 0 link: 0 done
9200 22:13:08.269057 Done setting resources.
9201 22:13:08.275496 Show resources in subtree (Root Device)...After assigning values.
9202 22:13:08.278727 Root Device child on link 0 CPU_CLUSTER: 0
9203 22:13:08.282399 CPU_CLUSTER: 0 child on link 0 CPU: 00
9204 22:13:08.292249 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9205 22:13:08.292331 CPU: 00
9206 22:13:08.295944 Done allocating resources.
9207 22:13:08.299092 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9208 22:13:08.302538 Enabling resources...
9209 22:13:08.302611 done.
9210 22:13:08.305784 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9211 22:13:08.308989 Initializing devices...
9212 22:13:08.312460 Root Device init
9213 22:13:08.312564 init hardware done!
9214 22:13:08.315503 0x00000018: ctrlr->caps
9215 22:13:08.318547 52.000 MHz: ctrlr->f_max
9216 22:13:08.318624 0.400 MHz: ctrlr->f_min
9217 22:13:08.321678 0x40ff8080: ctrlr->voltages
9218 22:13:08.321778 sclk: 390625
9219 22:13:08.325507 Bus Width = 1
9220 22:13:08.325625 sclk: 390625
9221 22:13:08.328619 Bus Width = 1
9222 22:13:08.328694 Early init status = 3
9223 22:13:08.334766 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9224 22:13:08.338408 in-header: 03 fc 00 00 01 00 00 00
9225 22:13:08.338507 in-data: 00
9226 22:13:08.344875 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9227 22:13:08.348407 in-header: 03 fd 00 00 00 00 00 00
9228 22:13:08.351358 in-data:
9229 22:13:08.354705 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9230 22:13:08.358376 in-header: 03 fc 00 00 01 00 00 00
9231 22:13:08.361666 in-data: 00
9232 22:13:08.365026 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9233 22:13:08.370593 in-header: 03 fd 00 00 00 00 00 00
9234 22:13:08.373592 in-data:
9235 22:13:08.377098 [SSUSB] Setting up USB HOST controller...
9236 22:13:08.380666 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9237 22:13:08.383589 [SSUSB] phy power-on done.
9238 22:13:08.387231 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9239 22:13:08.393447 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9240 22:13:08.397333 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9241 22:13:08.403306 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9242 22:13:08.410815 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9243 22:13:08.416870 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9244 22:13:08.423557 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9245 22:13:08.429939 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9246 22:13:08.433490 SPM: binary array size = 0x9dc
9247 22:13:08.436572 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9248 22:13:08.443354 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9249 22:13:08.450250 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9250 22:13:08.453880 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9251 22:13:08.460213 configure_display: Starting display init
9252 22:13:08.493899 anx7625_power_on_init: Init interface.
9253 22:13:08.496936 anx7625_disable_pd_protocol: Disabled PD feature.
9254 22:13:08.500631 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9255 22:13:08.528118 anx7625_start_dp_work: Secure OCM version=00
9256 22:13:08.531132 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9257 22:13:08.546040 sp_tx_get_edid_block: EDID Block = 1
9258 22:13:08.648960 Extracted contents:
9259 22:13:08.652059 header: 00 ff ff ff ff ff ff 00
9260 22:13:08.655804 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9261 22:13:08.659017 version: 01 04
9262 22:13:08.662198 basic params: 95 1f 11 78 0a
9263 22:13:08.665817 chroma info: 76 90 94 55 54 90 27 21 50 54
9264 22:13:08.668917 established: 00 00 00
9265 22:13:08.675599 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9266 22:13:08.678895 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9267 22:13:08.685615 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9268 22:13:08.691909 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9269 22:13:08.698815 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9270 22:13:08.702412 extensions: 00
9271 22:13:08.702501 checksum: fb
9272 22:13:08.702568
9273 22:13:08.705166 Manufacturer: IVO Model 57d Serial Number 0
9274 22:13:08.708849 Made week 0 of 2020
9275 22:13:08.708923 EDID version: 1.4
9276 22:13:08.711721 Digital display
9277 22:13:08.715516 6 bits per primary color channel
9278 22:13:08.715604 DisplayPort interface
9279 22:13:08.718794 Maximum image size: 31 cm x 17 cm
9280 22:13:08.722013 Gamma: 220%
9281 22:13:08.722094 Check DPMS levels
9282 22:13:08.725070 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9283 22:13:08.729022 First detailed timing is preferred timing
9284 22:13:08.731978 Established timings supported:
9285 22:13:08.734969 Standard timings supported:
9286 22:13:08.735051 Detailed timings
9287 22:13:08.742085 Hex of detail: 383680a07038204018303c0035ae10000019
9288 22:13:08.745398 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9289 22:13:08.751663 0780 0798 07c8 0820 hborder 0
9290 22:13:08.755249 0438 043b 0447 0458 vborder 0
9291 22:13:08.755326 -hsync -vsync
9292 22:13:08.758343 Did detailed timing
9293 22:13:08.761971 Hex of detail: 000000000000000000000000000000000000
9294 22:13:08.765200 Manufacturer-specified data, tag 0
9295 22:13:08.771857 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9296 22:13:08.771930 ASCII string: InfoVision
9297 22:13:08.778539 Hex of detail: 000000fe00523134304e574635205248200a
9298 22:13:08.781863 ASCII string: R140NWF5 RH
9299 22:13:08.781937 Checksum
9300 22:13:08.781999 Checksum: 0xfb (valid)
9301 22:13:08.788153 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9302 22:13:08.791947 DSI data_rate: 832800000 bps
9303 22:13:08.794839 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9304 22:13:08.798308 anx7625_parse_edid: pixelclock(138800).
9305 22:13:08.805413 hactive(1920), hsync(48), hfp(24), hbp(88)
9306 22:13:08.808077 vactive(1080), vsync(12), vfp(3), vbp(17)
9307 22:13:08.811768 anx7625_dsi_config: config dsi.
9308 22:13:08.818041 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9309 22:13:08.830870 anx7625_dsi_config: success to config DSI
9310 22:13:08.834212 anx7625_dp_start: MIPI phy setup OK.
9311 22:13:08.837864 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9312 22:13:08.840895 mtk_ddp_mode_set invalid vrefresh 60
9313 22:13:08.843942 main_disp_path_setup
9314 22:13:08.844023 ovl_layer_smi_id_en
9315 22:13:08.847679 ovl_layer_smi_id_en
9316 22:13:08.847752 ccorr_config
9317 22:13:08.847820 aal_config
9318 22:13:08.851255 gamma_config
9319 22:13:08.851332 postmask_config
9320 22:13:08.854203 dither_config
9321 22:13:08.857451 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9322 22:13:08.864030 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9323 22:13:08.867239 Root Device init finished in 552 msecs
9324 22:13:08.867311 CPU_CLUSTER: 0 init
9325 22:13:08.877491 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9326 22:13:08.880715 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9327 22:13:08.883698 APU_MBOX 0x190000b0 = 0x10001
9328 22:13:08.887408 APU_MBOX 0x190001b0 = 0x10001
9329 22:13:08.890430 APU_MBOX 0x190005b0 = 0x10001
9330 22:13:08.894065 APU_MBOX 0x190006b0 = 0x10001
9331 22:13:08.897193 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9332 22:13:08.909689 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9333 22:13:08.922121 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9334 22:13:08.928909 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9335 22:13:08.940777 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9336 22:13:08.949401 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9337 22:13:08.953186 CPU_CLUSTER: 0 init finished in 81 msecs
9338 22:13:08.956150 Devices initialized
9339 22:13:08.959244 Show all devs... After init.
9340 22:13:08.959325 Root Device: enabled 1
9341 22:13:08.962742 CPU_CLUSTER: 0: enabled 1
9342 22:13:08.965822 CPU: 00: enabled 1
9343 22:13:08.969557 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms
9344 22:13:08.972681 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9345 22:13:08.976573 ELOG: NV offset 0x57f000 size 0x1000
9346 22:13:08.982575 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9347 22:13:08.989232 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9348 22:13:08.993173 ELOG: Event(17) added with size 13 at 2023-06-04 22:13:21 UTC
9349 22:13:08.998903 out: cmd=0x121: 03 db 21 01 00 00 00 00
9350 22:13:09.002496 in-header: 03 d8 00 00 2c 00 00 00
9351 22:13:09.012886 in-data: 87 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9352 22:13:09.019016 ELOG: Event(A1) added with size 10 at 2023-06-04 22:13:21 UTC
9353 22:13:09.026109 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9354 22:13:09.032250 ELOG: Event(A0) added with size 9 at 2023-06-04 22:13:21 UTC
9355 22:13:09.035642 elog_add_boot_reason: Logged dev mode boot
9356 22:13:09.042526 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9357 22:13:09.042609 Finalize devices...
9358 22:13:09.045479 Devices finalized
9359 22:13:09.048990 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9360 22:13:09.051839 Writing coreboot table at 0xffe64000
9361 22:13:09.055712 0. 000000000010a000-0000000000113fff: RAMSTAGE
9362 22:13:09.058746 1. 0000000040000000-00000000400fffff: RAM
9363 22:13:09.065339 2. 0000000040100000-000000004032afff: RAMSTAGE
9364 22:13:09.068948 3. 000000004032b000-00000000545fffff: RAM
9365 22:13:09.072632 4. 0000000054600000-000000005465ffff: BL31
9366 22:13:09.075665 5. 0000000054660000-00000000ffe63fff: RAM
9367 22:13:09.082501 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9368 22:13:09.085416 7. 0000000100000000-000000023fffffff: RAM
9369 22:13:09.089032 Passing 5 GPIOs to payload:
9370 22:13:09.092235 NAME | PORT | POLARITY | VALUE
9371 22:13:09.095374 EC in RW | 0x000000aa | low | undefined
9372 22:13:09.102061 EC interrupt | 0x00000005 | low | undefined
9373 22:13:09.105391 TPM interrupt | 0x000000ab | high | undefined
9374 22:13:09.112074 SD card detect | 0x00000011 | high | undefined
9375 22:13:09.115260 speaker enable | 0x00000093 | high | undefined
9376 22:13:09.118895 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9377 22:13:09.122044 in-header: 03 f9 00 00 02 00 00 00
9378 22:13:09.125402 in-data: 02 00
9379 22:13:09.125485 ADC[4]: Raw value=905096 ID=7
9380 22:13:09.128822 ADC[3]: Raw value=213441 ID=1
9381 22:13:09.131821 RAM Code: 0x71
9382 22:13:09.131918 ADC[6]: Raw value=75332 ID=0
9383 22:13:09.135260 ADC[5]: Raw value=212703 ID=1
9384 22:13:09.138263 SKU Code: 0x1
9385 22:13:09.141588 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum d697
9386 22:13:09.145045 coreboot table: 964 bytes.
9387 22:13:09.148221 IMD ROOT 0. 0xfffff000 0x00001000
9388 22:13:09.151777 IMD SMALL 1. 0xffffe000 0x00001000
9389 22:13:09.155058 RO MCACHE 2. 0xffffc000 0x00001104
9390 22:13:09.158399 CONSOLE 3. 0xfff7c000 0x00080000
9391 22:13:09.161689 FMAP 4. 0xfff7b000 0x00000452
9392 22:13:09.164727 TIME STAMP 5. 0xfff7a000 0x00000910
9393 22:13:09.168484 VBOOT WORK 6. 0xfff66000 0x00014000
9394 22:13:09.171979 RAMOOPS 7. 0xffe66000 0x00100000
9395 22:13:09.175171 COREBOOT 8. 0xffe64000 0x00002000
9396 22:13:09.178228 IMD small region:
9397 22:13:09.181618 IMD ROOT 0. 0xffffec00 0x00000400
9398 22:13:09.184693 VPD 1. 0xffffeba0 0x0000004c
9399 22:13:09.188015 MMC STATUS 2. 0xffffeb80 0x00000004
9400 22:13:09.191402 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9401 22:13:09.194681 Probing TPM: done!
9402 22:13:09.198388 Connected to device vid:did:rid of 1ae0:0028:00
9403 22:13:09.208877 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.153/cr50_v3.94_pp.113-620c9b9523
9404 22:13:09.212406 Initialized TPM device CR50 revision 0
9405 22:13:09.215483 Checking cr50 for pending updates
9406 22:13:09.219821 Reading cr50 TPM mode
9407 22:13:09.228092 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9408 22:13:09.234964 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9409 22:13:09.275129 read SPI 0x3990ec 0x4f1b0: 34846 us, 9298 KB/s, 74.384 Mbps
9410 22:13:09.278281 Checking segment from ROM address 0x40100000
9411 22:13:09.281481 Checking segment from ROM address 0x4010001c
9412 22:13:09.288091 Loading segment from ROM address 0x40100000
9413 22:13:09.288199 code (compression=0)
9414 22:13:09.298220 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9415 22:13:09.304938 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9416 22:13:09.305034 it's not compressed!
9417 22:13:09.311807 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9418 22:13:09.315424 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9419 22:13:09.335301 Loading segment from ROM address 0x4010001c
9420 22:13:09.335387 Entry Point 0x80000000
9421 22:13:09.338632 Loaded segments
9422 22:13:09.342110 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9423 22:13:09.348530 Jumping to boot code at 0x80000000(0xffe64000)
9424 22:13:09.355510 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9425 22:13:09.361895 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9426 22:13:09.370029 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9427 22:13:09.373293 Checking segment from ROM address 0x40100000
9428 22:13:09.376270 Checking segment from ROM address 0x4010001c
9429 22:13:09.383079 Loading segment from ROM address 0x40100000
9430 22:13:09.383181 code (compression=1)
9431 22:13:09.389631 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9432 22:13:09.399875 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9433 22:13:09.399978 using LZMA
9434 22:13:09.407979 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9435 22:13:09.414694 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9436 22:13:09.417915 Loading segment from ROM address 0x4010001c
9437 22:13:09.418015 Entry Point 0x54601000
9438 22:13:09.421407 Loaded segments
9439 22:13:09.425201 NOTICE: MT8192 bl31_setup
9440 22:13:09.431556 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9441 22:13:09.435349 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9442 22:13:09.438423 WARNING: region 0:
9443 22:13:09.441743 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9444 22:13:09.441825 WARNING: region 1:
9445 22:13:09.448586 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9446 22:13:09.448668 WARNING: region 2:
9447 22:13:09.455514 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9448 22:13:09.458481 WARNING: region 3:
9449 22:13:09.461987 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9450 22:13:09.465652 WARNING: region 4:
9451 22:13:09.468417 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9452 22:13:09.471929 WARNING: region 5:
9453 22:13:09.475009 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9454 22:13:09.478387 WARNING: region 6:
9455 22:13:09.481553 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9456 22:13:09.481675 WARNING: region 7:
9457 22:13:09.488463 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9458 22:13:09.495326 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9459 22:13:09.498274 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9460 22:13:09.501671 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9461 22:13:09.508833 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9462 22:13:09.512026 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9463 22:13:09.515217 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9464 22:13:09.521826 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9465 22:13:09.524943 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9466 22:13:09.528572 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9467 22:13:09.535157 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9468 22:13:09.538708 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9469 22:13:09.545233 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9470 22:13:09.548400 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9471 22:13:09.551700 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9472 22:13:09.558743 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9473 22:13:09.561907 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9474 22:13:09.565257 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9475 22:13:09.572197 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9476 22:13:09.575561 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9477 22:13:09.578682 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9478 22:13:09.585678 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9479 22:13:09.588680 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9480 22:13:09.595505 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9481 22:13:09.598727 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9482 22:13:09.601939 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9483 22:13:09.609044 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9484 22:13:09.611844 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9485 22:13:09.618381 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9486 22:13:09.622243 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9487 22:13:09.625414 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9488 22:13:09.632039 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9489 22:13:09.635187 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9490 22:13:09.638863 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9491 22:13:09.645793 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9492 22:13:09.648847 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9493 22:13:09.651931 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9494 22:13:09.655553 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9495 22:13:09.662198 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9496 22:13:09.665436 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9497 22:13:09.668536 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9498 22:13:09.672080 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9499 22:13:09.678934 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9500 22:13:09.682067 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9501 22:13:09.685421 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9502 22:13:09.688888 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9503 22:13:09.695234 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9504 22:13:09.698950 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9505 22:13:09.702659 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9506 22:13:09.708862 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9507 22:13:09.712408 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9508 22:13:09.715604 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9509 22:13:09.722448 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9510 22:13:09.725699 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9511 22:13:09.732479 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9512 22:13:09.735793 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9513 22:13:09.739040 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9514 22:13:09.745994 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9515 22:13:09.749154 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9516 22:13:09.755494 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9517 22:13:09.759433 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9518 22:13:09.765252 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9519 22:13:09.769215 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9520 22:13:09.775366 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9521 22:13:09.779047 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9522 22:13:09.782030 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9523 22:13:09.789022 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9524 22:13:09.792372 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9525 22:13:09.799323 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9526 22:13:09.802582 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9527 22:13:09.809422 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9528 22:13:09.812128 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9529 22:13:09.815604 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9530 22:13:09.822227 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9531 22:13:09.825822 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9532 22:13:09.832390 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9533 22:13:09.835674 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9534 22:13:09.842140 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9535 22:13:09.845978 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9536 22:13:09.849113 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9537 22:13:09.855420 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9538 22:13:09.859413 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9539 22:13:09.866085 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9540 22:13:09.869137 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9541 22:13:09.875847 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9542 22:13:09.879030 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9543 22:13:09.882795 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9544 22:13:09.889479 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9545 22:13:09.892490 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9546 22:13:09.899461 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9547 22:13:09.902401 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9548 22:13:09.909623 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9549 22:13:09.912576 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9550 22:13:09.915981 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9551 22:13:09.922890 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9552 22:13:09.925979 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9553 22:13:09.932599 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9554 22:13:09.936282 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9555 22:13:09.939109 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9556 22:13:09.943039 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9557 22:13:09.949299 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9558 22:13:09.953020 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9559 22:13:09.956116 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9560 22:13:09.962770 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9561 22:13:09.966255 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9562 22:13:09.972703 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9563 22:13:09.976078 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9564 22:13:09.979882 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9565 22:13:09.986149 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9566 22:13:09.989456 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9567 22:13:09.992912 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9568 22:13:09.999532 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9569 22:13:10.003059 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9570 22:13:10.009730 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9571 22:13:10.013347 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9572 22:13:10.016640 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9573 22:13:10.023073 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9574 22:13:10.026837 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9575 22:13:10.029651 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9576 22:13:10.036309 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9577 22:13:10.040016 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9578 22:13:10.043395 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9579 22:13:10.046232 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9580 22:13:10.052875 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9581 22:13:10.056426 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9582 22:13:10.060162 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9583 22:13:10.066399 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9584 22:13:10.069624 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9585 22:13:10.072996 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9586 22:13:10.079927 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9587 22:13:10.082776 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9588 22:13:10.089486 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9589 22:13:10.093291 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9590 22:13:10.096483 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9591 22:13:10.103154 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9592 22:13:10.107021 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9593 22:13:10.113335 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9594 22:13:10.116316 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9595 22:13:10.119823 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9596 22:13:10.126578 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9597 22:13:10.129546 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9598 22:13:10.132967 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9599 22:13:10.140018 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9600 22:13:10.143077 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9601 22:13:10.150033 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9602 22:13:10.153068 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9603 22:13:10.157069 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9604 22:13:10.163379 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9605 22:13:10.166548 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9606 22:13:10.170477 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9607 22:13:10.176622 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9608 22:13:10.180241 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9609 22:13:10.186824 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9610 22:13:10.190236 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9611 22:13:10.193294 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9612 22:13:10.200233 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9613 22:13:10.203464 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9614 22:13:10.206557 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9615 22:13:10.213264 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9616 22:13:10.216902 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9617 22:13:10.223444 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9618 22:13:10.226483 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9619 22:13:10.229938 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9620 22:13:10.236701 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9621 22:13:10.239792 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9622 22:13:10.246744 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9623 22:13:10.250280 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9624 22:13:10.253449 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9625 22:13:10.260070 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9626 22:13:10.263035 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9627 22:13:10.269897 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9628 22:13:10.273097 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9629 22:13:10.276947 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9630 22:13:10.283201 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9631 22:13:10.286761 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9632 22:13:10.289867 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9633 22:13:10.296375 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9634 22:13:10.299492 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9635 22:13:10.306248 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9636 22:13:10.309421 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9637 22:13:10.313139 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9638 22:13:10.319360 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9639 22:13:10.322955 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9640 22:13:10.329634 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9641 22:13:10.333036 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9642 22:13:10.336455 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9643 22:13:10.343027 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9644 22:13:10.345882 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9645 22:13:10.352913 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9646 22:13:10.356494 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9647 22:13:10.359583 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9648 22:13:10.366179 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9649 22:13:10.369846 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9650 22:13:10.376646 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9651 22:13:10.379609 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9652 22:13:10.382891 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9653 22:13:10.389431 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9654 22:13:10.393270 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9655 22:13:10.399387 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9656 22:13:10.402984 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9657 22:13:10.409667 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9658 22:13:10.412713 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9659 22:13:10.416238 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9660 22:13:10.422645 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9661 22:13:10.425859 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9662 22:13:10.432413 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9663 22:13:10.436023 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9664 22:13:10.439694 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9665 22:13:10.445938 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9666 22:13:10.449142 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9667 22:13:10.455547 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9668 22:13:10.458963 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9669 22:13:10.465574 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9670 22:13:10.469450 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9671 22:13:10.472356 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9672 22:13:10.479440 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9673 22:13:10.482613 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9674 22:13:10.489295 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9675 22:13:10.492479 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9676 22:13:10.496122 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9677 22:13:10.502890 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9678 22:13:10.505833 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9679 22:13:10.512458 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9680 22:13:10.515928 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9681 22:13:10.519159 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9682 22:13:10.525768 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9683 22:13:10.529047 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9684 22:13:10.535798 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9685 22:13:10.538819 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9686 22:13:10.545380 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9687 22:13:10.548724 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9688 22:13:10.552309 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9689 22:13:10.555895 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9690 22:13:10.559318 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9691 22:13:10.565473 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9692 22:13:10.568623 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9693 22:13:10.572519 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9694 22:13:10.578771 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9695 22:13:10.582350 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9696 22:13:10.585810 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9697 22:13:10.592598 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9698 22:13:10.595655 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9699 22:13:10.602588 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9700 22:13:10.605597 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9701 22:13:10.609187 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9702 22:13:10.615219 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9703 22:13:10.618839 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9704 22:13:10.622403 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9705 22:13:10.628688 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9706 22:13:10.632291 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9707 22:13:10.638654 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9708 22:13:10.641862 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9709 22:13:10.645398 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9710 22:13:10.651820 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9711 22:13:10.655095 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9712 22:13:10.658256 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9713 22:13:10.664948 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9714 22:13:10.668582 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9715 22:13:10.674984 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9716 22:13:10.678681 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9717 22:13:10.681719 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9718 22:13:10.688500 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9719 22:13:10.692091 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9720 22:13:10.695166 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9721 22:13:10.701828 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9722 22:13:10.704974 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9723 22:13:10.708706 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9724 22:13:10.715453 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9725 22:13:10.718685 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9726 22:13:10.721553 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9727 22:13:10.728797 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9728 22:13:10.731899 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9729 22:13:10.735108 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9730 22:13:10.738268 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9731 22:13:10.741548 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9732 22:13:10.748108 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9733 22:13:10.751648 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9734 22:13:10.754919 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9735 22:13:10.758251 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9736 22:13:10.764649 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9737 22:13:10.768234 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9738 22:13:10.771860 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9739 22:13:10.778347 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9740 22:13:10.781327 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9741 22:13:10.785278 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9742 22:13:10.791822 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9743 22:13:10.794915 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9744 22:13:10.801606 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9745 22:13:10.804653 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9746 22:13:10.810988 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9747 22:13:10.814282 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9748 22:13:10.818126 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9749 22:13:10.824402 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9750 22:13:10.827990 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9751 22:13:10.834465 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9752 22:13:10.837564 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9753 22:13:10.844594 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9754 22:13:10.847676 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9755 22:13:10.850752 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9756 22:13:10.857415 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9757 22:13:10.861140 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9758 22:13:10.864619 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9759 22:13:10.871064 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9760 22:13:10.874111 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9761 22:13:10.880568 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9762 22:13:10.884334 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9763 22:13:10.887636 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9764 22:13:10.893921 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9765 22:13:10.897638 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9766 22:13:10.904177 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9767 22:13:10.907803 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9768 22:13:10.914038 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9769 22:13:10.917670 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9770 22:13:10.920566 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9771 22:13:10.927427 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9772 22:13:10.931284 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9773 22:13:10.937229 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9774 22:13:10.940688 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9775 22:13:10.943718 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9776 22:13:10.950569 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9777 22:13:10.953732 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9778 22:13:10.960515 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9779 22:13:10.964052 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9780 22:13:10.967129 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9781 22:13:10.973664 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9782 22:13:10.977141 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9783 22:13:10.983720 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9784 22:13:10.987233 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9785 22:13:10.993798 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9786 22:13:10.997443 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9787 22:13:11.000386 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9788 22:13:11.007250 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9789 22:13:11.010267 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9790 22:13:11.017399 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9791 22:13:11.020531 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9792 22:13:11.023548 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9793 22:13:11.030315 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9794 22:13:11.033431 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9795 22:13:11.040372 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9796 22:13:11.043309 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9797 22:13:11.046891 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9798 22:13:11.053628 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9799 22:13:11.057378 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9800 22:13:11.063545 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9801 22:13:11.066885 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9802 22:13:11.070540 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9803 22:13:11.077114 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9804 22:13:11.080574 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9805 22:13:11.086730 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9806 22:13:11.089954 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9807 22:13:11.093399 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9808 22:13:11.099909 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9809 22:13:11.103606 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9810 22:13:11.110561 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9811 22:13:11.113659 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9812 22:13:11.116677 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9813 22:13:11.123180 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9814 22:13:11.126280 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9815 22:13:11.133491 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9816 22:13:11.136848 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9817 22:13:11.143019 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9818 22:13:11.146737 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9819 22:13:11.149830 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9820 22:13:11.156900 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9821 22:13:11.160020 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9822 22:13:11.166871 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9823 22:13:11.170054 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9824 22:13:11.176675 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9825 22:13:11.179814 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9826 22:13:11.186314 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9827 22:13:11.189740 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9828 22:13:11.193607 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9829 22:13:11.199866 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9830 22:13:11.203528 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9831 22:13:11.210107 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9832 22:13:11.213165 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9833 22:13:11.220022 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9834 22:13:11.222984 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9835 22:13:11.226474 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9836 22:13:11.232828 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9837 22:13:11.236519 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9838 22:13:11.243519 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9839 22:13:11.246515 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9840 22:13:11.253367 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9841 22:13:11.256466 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9842 22:13:11.260265 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9843 22:13:11.266274 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9844 22:13:11.270167 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9845 22:13:11.277006 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9846 22:13:11.279834 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9847 22:13:11.286233 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9848 22:13:11.289985 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9849 22:13:11.293411 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9850 22:13:11.299609 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9851 22:13:11.303238 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9852 22:13:11.309696 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9853 22:13:11.313026 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9854 22:13:11.319730 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9855 22:13:11.322907 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9856 22:13:11.326120 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9857 22:13:11.333217 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9858 22:13:11.336257 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9859 22:13:11.342783 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9860 22:13:11.346532 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9861 22:13:11.349490 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9862 22:13:11.356452 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9863 22:13:11.359568 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9864 22:13:11.366308 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9865 22:13:11.369969 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9866 22:13:11.376257 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9867 22:13:11.380093 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9868 22:13:11.386272 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9869 22:13:11.389960 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9870 22:13:11.396225 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9871 22:13:11.399785 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9872 22:13:11.406657 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9873 22:13:11.409738 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9874 22:13:11.416357 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9875 22:13:11.419688 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9876 22:13:11.426252 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9877 22:13:11.429279 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9878 22:13:11.435986 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9879 22:13:11.439203 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9880 22:13:11.445878 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9881 22:13:11.449431 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9882 22:13:11.456123 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9883 22:13:11.459468 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9884 22:13:11.466207 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9885 22:13:11.469341 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9886 22:13:11.476183 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9887 22:13:11.479802 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9888 22:13:11.486068 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9889 22:13:11.489139 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9890 22:13:11.496005 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9891 22:13:11.499531 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9892 22:13:11.502436 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9893 22:13:11.506095 INFO: [APUAPC] vio 0
9894 22:13:11.509445 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9895 22:13:11.515829 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9896 22:13:11.519288 INFO: [APUAPC] D0_APC_0: 0x400510
9897 22:13:11.522825 INFO: [APUAPC] D0_APC_1: 0x0
9898 22:13:11.525908 INFO: [APUAPC] D0_APC_2: 0x1540
9899 22:13:11.526012 INFO: [APUAPC] D0_APC_3: 0x0
9900 22:13:11.529015 INFO: [APUAPC] D1_APC_0: 0xffffffff
9901 22:13:11.536133 INFO: [APUAPC] D1_APC_1: 0xffffffff
9902 22:13:11.536239 INFO: [APUAPC] D1_APC_2: 0x3fffff
9903 22:13:11.539060 INFO: [APUAPC] D1_APC_3: 0x0
9904 22:13:11.542840 INFO: [APUAPC] D2_APC_0: 0xffffffff
9905 22:13:11.545969 INFO: [APUAPC] D2_APC_1: 0xffffffff
9906 22:13:11.549430 INFO: [APUAPC] D2_APC_2: 0x3fffff
9907 22:13:11.552542 INFO: [APUAPC] D2_APC_3: 0x0
9908 22:13:11.555706 INFO: [APUAPC] D3_APC_0: 0xffffffff
9909 22:13:11.559080 INFO: [APUAPC] D3_APC_1: 0xffffffff
9910 22:13:11.562354 INFO: [APUAPC] D3_APC_2: 0x3fffff
9911 22:13:11.565864 INFO: [APUAPC] D3_APC_3: 0x0
9912 22:13:11.568985 INFO: [APUAPC] D4_APC_0: 0xffffffff
9913 22:13:11.572628 INFO: [APUAPC] D4_APC_1: 0xffffffff
9914 22:13:11.575892 INFO: [APUAPC] D4_APC_2: 0x3fffff
9915 22:13:11.578911 INFO: [APUAPC] D4_APC_3: 0x0
9916 22:13:11.582464 INFO: [APUAPC] D5_APC_0: 0xffffffff
9917 22:13:11.585844 INFO: [APUAPC] D5_APC_1: 0xffffffff
9918 22:13:11.589015 INFO: [APUAPC] D5_APC_2: 0x3fffff
9919 22:13:11.592894 INFO: [APUAPC] D5_APC_3: 0x0
9920 22:13:11.595377 INFO: [APUAPC] D6_APC_0: 0xffffffff
9921 22:13:11.599045 INFO: [APUAPC] D6_APC_1: 0xffffffff
9922 22:13:11.602047 INFO: [APUAPC] D6_APC_2: 0x3fffff
9923 22:13:11.605386 INFO: [APUAPC] D6_APC_3: 0x0
9924 22:13:11.608864 INFO: [APUAPC] D7_APC_0: 0xffffffff
9925 22:13:11.612458 INFO: [APUAPC] D7_APC_1: 0xffffffff
9926 22:13:11.615881 INFO: [APUAPC] D7_APC_2: 0x3fffff
9927 22:13:11.618739 INFO: [APUAPC] D7_APC_3: 0x0
9928 22:13:11.622363 INFO: [APUAPC] D8_APC_0: 0xffffffff
9929 22:13:11.625408 INFO: [APUAPC] D8_APC_1: 0xffffffff
9930 22:13:11.628843 INFO: [APUAPC] D8_APC_2: 0x3fffff
9931 22:13:11.632408 INFO: [APUAPC] D8_APC_3: 0x0
9932 22:13:11.635586 INFO: [APUAPC] D9_APC_0: 0xffffffff
9933 22:13:11.639016 INFO: [APUAPC] D9_APC_1: 0xffffffff
9934 22:13:11.642066 INFO: [APUAPC] D9_APC_2: 0x3fffff
9935 22:13:11.645828 INFO: [APUAPC] D9_APC_3: 0x0
9936 22:13:11.649033 INFO: [APUAPC] D10_APC_0: 0xffffffff
9937 22:13:11.652079 INFO: [APUAPC] D10_APC_1: 0xffffffff
9938 22:13:11.655747 INFO: [APUAPC] D10_APC_2: 0x3fffff
9939 22:13:11.658769 INFO: [APUAPC] D10_APC_3: 0x0
9940 22:13:11.661945 INFO: [APUAPC] D11_APC_0: 0xffffffff
9941 22:13:11.665674 INFO: [APUAPC] D11_APC_1: 0xffffffff
9942 22:13:11.668473 INFO: [APUAPC] D11_APC_2: 0x3fffff
9943 22:13:11.672014 INFO: [APUAPC] D11_APC_3: 0x0
9944 22:13:11.675445 INFO: [APUAPC] D12_APC_0: 0xffffffff
9945 22:13:11.679021 INFO: [APUAPC] D12_APC_1: 0xffffffff
9946 22:13:11.682177 INFO: [APUAPC] D12_APC_2: 0x3fffff
9947 22:13:11.685118 INFO: [APUAPC] D12_APC_3: 0x0
9948 22:13:11.688908 INFO: [APUAPC] D13_APC_0: 0xffffffff
9949 22:13:11.691923 INFO: [APUAPC] D13_APC_1: 0xffffffff
9950 22:13:11.695089 INFO: [APUAPC] D13_APC_2: 0x3fffff
9951 22:13:11.698701 INFO: [APUAPC] D13_APC_3: 0x0
9952 22:13:11.701792 INFO: [APUAPC] D14_APC_0: 0xffffffff
9953 22:13:11.705777 INFO: [APUAPC] D14_APC_1: 0xffffffff
9954 22:13:11.708691 INFO: [APUAPC] D14_APC_2: 0x3fffff
9955 22:13:11.711761 INFO: [APUAPC] D14_APC_3: 0x0
9956 22:13:11.715449 INFO: [APUAPC] D15_APC_0: 0xffffffff
9957 22:13:11.718575 INFO: [APUAPC] D15_APC_1: 0xffffffff
9958 22:13:11.721874 INFO: [APUAPC] D15_APC_2: 0x3fffff
9959 22:13:11.724978 INFO: [APUAPC] D15_APC_3: 0x0
9960 22:13:11.728398 INFO: [APUAPC] APC_CON: 0x4
9961 22:13:11.732018 INFO: [NOCDAPC] D0_APC_0: 0x0
9962 22:13:11.732102 INFO: [NOCDAPC] D0_APC_1: 0x0
9963 22:13:11.734921 INFO: [NOCDAPC] D1_APC_0: 0x0
9964 22:13:11.738359 INFO: [NOCDAPC] D1_APC_1: 0xfff
9965 22:13:11.741921 INFO: [NOCDAPC] D2_APC_0: 0x0
9966 22:13:11.744932 INFO: [NOCDAPC] D2_APC_1: 0xfff
9967 22:13:11.748319 INFO: [NOCDAPC] D3_APC_0: 0x0
9968 22:13:11.751610 INFO: [NOCDAPC] D3_APC_1: 0xfff
9969 22:13:11.755321 INFO: [NOCDAPC] D4_APC_0: 0x0
9970 22:13:11.758486 INFO: [NOCDAPC] D4_APC_1: 0xfff
9971 22:13:11.761398 INFO: [NOCDAPC] D5_APC_0: 0x0
9972 22:13:11.761479 INFO: [NOCDAPC] D5_APC_1: 0xfff
9973 22:13:11.765277 INFO: [NOCDAPC] D6_APC_0: 0x0
9974 22:13:11.768403 INFO: [NOCDAPC] D6_APC_1: 0xfff
9975 22:13:11.771443 INFO: [NOCDAPC] D7_APC_0: 0x0
9976 22:13:11.775075 INFO: [NOCDAPC] D7_APC_1: 0xfff
9977 22:13:11.778277 INFO: [NOCDAPC] D8_APC_0: 0x0
9978 22:13:11.782067 INFO: [NOCDAPC] D8_APC_1: 0xfff
9979 22:13:11.785146 INFO: [NOCDAPC] D9_APC_0: 0x0
9980 22:13:11.788166 INFO: [NOCDAPC] D9_APC_1: 0xfff
9981 22:13:11.791985 INFO: [NOCDAPC] D10_APC_0: 0x0
9982 22:13:11.794987 INFO: [NOCDAPC] D10_APC_1: 0xfff
9983 22:13:11.795087 INFO: [NOCDAPC] D11_APC_0: 0x0
9984 22:13:11.798757 INFO: [NOCDAPC] D11_APC_1: 0xfff
9985 22:13:11.801805 INFO: [NOCDAPC] D12_APC_0: 0x0
9986 22:13:11.805010 INFO: [NOCDAPC] D12_APC_1: 0xfff
9987 22:13:11.808288 INFO: [NOCDAPC] D13_APC_0: 0x0
9988 22:13:11.811291 INFO: [NOCDAPC] D13_APC_1: 0xfff
9989 22:13:11.814979 INFO: [NOCDAPC] D14_APC_0: 0x0
9990 22:13:11.818075 INFO: [NOCDAPC] D14_APC_1: 0xfff
9991 22:13:11.821330 INFO: [NOCDAPC] D15_APC_0: 0x0
9992 22:13:11.824816 INFO: [NOCDAPC] D15_APC_1: 0xfff
9993 22:13:11.827956 INFO: [NOCDAPC] APC_CON: 0x4
9994 22:13:11.831221 INFO: [APUAPC] set_apusys_apc done
9995 22:13:11.834460 INFO: [DEVAPC] devapc_init done
9996 22:13:11.837950 INFO: GICv3 without legacy support detected.
9997 22:13:11.841269 INFO: ARM GICv3 driver initialized in EL3
9998 22:13:11.844847 INFO: Maximum SPI INTID supported: 639
9999 22:13:11.851004 INFO: BL31: Initializing runtime services
10000 22:13:11.854511 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10001 22:13:11.858047 INFO: SPM: enable CPC mode
10002 22:13:11.864427 INFO: mcdi ready for mcusys-off-idle and system suspend
10003 22:13:11.867525 INFO: BL31: Preparing for EL3 exit to normal world
10004 22:13:11.871199 INFO: Entry point address = 0x80000000
10005 22:13:11.874392 INFO: SPSR = 0x8
10006 22:13:11.879618
10007 22:13:11.879705
10008 22:13:11.879780
10009 22:13:11.882822 Starting depthcharge on Spherion...
10010 22:13:11.882905
10011 22:13:11.882969 Wipe memory regions:
10012 22:13:11.883030
10013 22:13:11.883840 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10014 22:13:11.883976 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10015 22:13:11.884095 Setting prompt string to ['asurada:']
10016 22:13:11.884206 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10017 22:13:11.886394 [0x00000040000000, 0x00000054600000)
10018 22:13:12.008552
10019 22:13:12.008706 [0x00000054660000, 0x00000080000000)
10020 22:13:12.269233
10021 22:13:12.269398 [0x000000821a7280, 0x000000ffe64000)
10022 22:13:13.013629
10023 22:13:13.013763 [0x00000100000000, 0x00000240000000)
10024 22:13:14.902464
10025 22:13:14.905340 Initializing XHCI USB controller at 0x11200000.
10026 22:13:15.943632
10027 22:13:15.947000 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10028 22:13:15.947084
10029 22:13:15.947167
10030 22:13:15.947230
10031 22:13:15.947519 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10033 22:13:16.047887 asurada: tftpboot 192.168.201.1 10583861/tftp-deploy-vhgxdhl0/kernel/image.itb 10583861/tftp-deploy-vhgxdhl0/kernel/cmdline
10034 22:13:16.048097 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10035 22:13:16.048257 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10036 22:13:16.052635 tftpboot 192.168.201.1 10583861/tftp-deploy-vhgxdhl0/kernel/image.ittp-deploy-vhgxdhl0/kernel/cmdline
10037 22:13:16.052719
10038 22:13:16.052783 Waiting for link
10039 22:13:16.213292
10040 22:13:16.213425 R8152: Initializing
10041 22:13:16.213548
10042 22:13:16.216222 Version 9 (ocp_data = 6010)
10043 22:13:16.216323
10044 22:13:16.219273 R8152: Done initializing
10045 22:13:16.219371
10046 22:13:16.219461 Adding net device
10047 22:13:18.165565
10048 22:13:18.165724 done.
10049 22:13:18.165819
10050 22:13:18.165908 MAC: 00:e0:4c:78:7a:aa
10051 22:13:18.166005
10052 22:13:18.168577 Sending DHCP discover... done.
10053 22:13:18.168659
10054 22:13:18.172200 Waiting for reply... done.
10055 22:13:18.172283
10056 22:13:18.175108 Sending DHCP request... done.
10057 22:13:18.175191
10058 22:13:18.175256 Waiting for reply... done.
10059 22:13:18.175316
10060 22:13:18.178660 My ip is 192.168.201.12
10061 22:13:18.178741
10062 22:13:18.181691 The DHCP server ip is 192.168.201.1
10063 22:13:18.181773
10064 22:13:18.185489 TFTP server IP predefined by user: 192.168.201.1
10065 22:13:18.185631
10066 22:13:18.191587 Bootfile predefined by user: 10583861/tftp-deploy-vhgxdhl0/kernel/image.itb
10067 22:13:18.191670
10068 22:13:18.195127 Sending tftp read request... done.
10069 22:13:18.195208
10070 22:13:18.198489 Waiting for the transfer...
10071 22:13:18.198572
10072 22:13:18.445379 00000000 ################################################################
10073 22:13:18.445578
10074 22:13:18.689904 00080000 ################################################################
10075 22:13:18.690040
10076 22:13:18.943199 00100000 ################################################################
10077 22:13:18.943332
10078 22:13:19.204425 00180000 ################################################################
10079 22:13:19.204559
10080 22:13:19.456743 00200000 ################################################################
10081 22:13:19.456875
10082 22:13:19.720350 00280000 ################################################################
10083 22:13:19.720480
10084 22:13:19.993661 00300000 ################################################################
10085 22:13:19.993792
10086 22:13:20.275946 00380000 ################################################################
10087 22:13:20.276080
10088 22:13:20.553712 00400000 ################################################################
10089 22:13:20.553874
10090 22:13:20.848189 00480000 ################################################################
10091 22:13:20.848326
10092 22:13:21.142418 00500000 ################################################################
10093 22:13:21.142548
10094 22:13:21.426524 00580000 ################################################################
10095 22:13:21.426684
10096 22:13:21.687834 00600000 ################################################################
10097 22:13:21.687996
10098 22:13:21.948742 00680000 ################################################################
10099 22:13:21.948872
10100 22:13:22.204263 00700000 ################################################################
10101 22:13:22.204400
10102 22:13:22.461921 00780000 ################################################################
10103 22:13:22.462070
10104 22:13:22.715214 00800000 ################################################################
10105 22:13:22.715377
10106 22:13:22.977552 00880000 ################################################################
10107 22:13:22.977684
10108 22:13:23.237811 00900000 ################################################################
10109 22:13:23.237945
10110 22:13:23.496972 00980000 ################################################################
10111 22:13:23.497109
10112 22:13:23.765763 00a00000 ################################################################
10113 22:13:23.765892
10114 22:13:24.020654 00a80000 ################################################################
10115 22:13:24.020811
10116 22:13:24.269859 00b00000 ################################################################
10117 22:13:24.269997
10118 22:13:24.537050 00b80000 ################################################################
10119 22:13:24.537216
10120 22:13:24.818088 00c00000 ################################################################
10121 22:13:24.818217
10122 22:13:25.096921 00c80000 ################################################################
10123 22:13:25.097085
10124 22:13:25.360179 00d00000 ################################################################
10125 22:13:25.360330
10126 22:13:25.643930 00d80000 ################################################################
10127 22:13:25.644064
10128 22:13:25.907984 00e00000 ################################################################
10129 22:13:25.908116
10130 22:13:26.183938 00e80000 ################################################################
10131 22:13:26.184073
10132 22:13:26.448719 00f00000 ################################################################
10133 22:13:26.448848
10134 22:13:26.701000 00f80000 ################################################################
10135 22:13:26.701127
10136 22:13:26.980734 01000000 ################################################################
10137 22:13:26.980891
10138 22:13:27.271740 01080000 ################################################################
10139 22:13:27.271877
10140 22:13:27.563058 01100000 ################################################################
10141 22:13:27.563193
10142 22:13:27.852088 01180000 ################################################################
10143 22:13:27.852220
10144 22:13:28.144750 01200000 ################################################################
10145 22:13:28.144884
10146 22:13:28.429811 01280000 ################################################################
10147 22:13:28.429940
10148 22:13:28.721715 01300000 ################################################################
10149 22:13:28.721876
10150 22:13:29.000584 01380000 ################################################################
10151 22:13:29.000716
10152 22:13:29.263648 01400000 ################################################################
10153 22:13:29.263778
10154 22:13:29.529405 01480000 ################################################################
10155 22:13:29.529590
10156 22:13:29.809049 01500000 ################################################################
10157 22:13:29.809181
10158 22:13:30.096612 01580000 ################################################################
10159 22:13:30.096746
10160 22:13:30.391348 01600000 ################################################################
10161 22:13:30.391483
10162 22:13:30.686494 01680000 ################################################################
10163 22:13:30.686629
10164 22:13:30.942892 01700000 ################################################################
10165 22:13:30.943028
10166 22:13:31.198717 01780000 ################################################################
10167 22:13:31.198879
10168 22:13:31.473473 01800000 ################################################################
10169 22:13:31.473638
10170 22:13:31.758560 01880000 ################################################################
10171 22:13:31.758695
10172 22:13:32.044436 01900000 ################################################################
10173 22:13:32.044569
10174 22:13:32.326444 01980000 ################################################################
10175 22:13:32.326591
10176 22:13:32.595344 01a00000 ################################################################
10177 22:13:32.595480
10178 22:13:32.851963 01a80000 ################################################################
10179 22:13:32.852095
10180 22:13:33.103750 01b00000 ################################################################
10181 22:13:33.103885
10182 22:13:33.380527 01b80000 ################################################################
10183 22:13:33.380662
10184 22:13:33.638029 01c00000 ################################################################
10185 22:13:33.638165
10186 22:13:33.909403 01c80000 ################################################################
10187 22:13:33.909599
10188 22:13:34.161097 01d00000 ################################################################
10189 22:13:34.161230
10190 22:13:34.443841 01d80000 ################################################################
10191 22:13:34.443980
10192 22:13:34.704685 01e00000 ################################################################
10193 22:13:34.704816
10194 22:13:34.971067 01e80000 ################################################################
10195 22:13:34.971196
10196 22:13:35.255946 01f00000 ################################################################
10197 22:13:35.256082
10198 22:13:35.549401 01f80000 ################################################################
10199 22:13:35.549568
10200 22:13:35.824212 02000000 ################################################################
10201 22:13:35.824348
10202 22:13:36.084218 02080000 ################################################################
10203 22:13:36.084349
10204 22:13:36.376539 02100000 ################################################################
10205 22:13:36.376676
10206 22:13:36.658477 02180000 ################################################################
10207 22:13:36.658613
10208 22:13:36.952302 02200000 ################################################################
10209 22:13:36.952439
10210 22:13:37.214929 02280000 ################################################################
10211 22:13:37.215063
10212 22:13:37.504518 02300000 ################################################################
10213 22:13:37.504649
10214 22:13:37.766398 02380000 ################################################################
10215 22:13:37.766532
10216 22:13:38.028110 02400000 ################################################################
10217 22:13:38.028249
10218 22:13:38.295334 02480000 ################################################################
10219 22:13:38.295484
10220 22:13:38.566879 02500000 ################################################################
10221 22:13:38.567012
10222 22:13:38.847284 02580000 ################################################################
10223 22:13:38.847417
10224 22:13:39.141197 02600000 ################################################################
10225 22:13:39.141332
10226 22:13:39.427472 02680000 ################################################################
10227 22:13:39.427609
10228 22:13:39.691387 02700000 ################################################################
10229 22:13:39.691527
10230 22:13:39.968187 02780000 ################################################################
10231 22:13:39.968320
10232 22:13:40.257068 02800000 ################################################################
10233 22:13:40.257199
10234 22:13:40.536390 02880000 ################################################################
10235 22:13:40.536526
10236 22:13:40.824094 02900000 ################################################################
10237 22:13:40.824228
10238 22:13:41.118509 02980000 ################################################################
10239 22:13:41.118646
10240 22:13:41.387571 02a00000 ################################################################
10241 22:13:41.387706
10242 22:13:41.660740 02a80000 ################################################################
10243 22:13:41.660874
10244 22:13:41.914161 02b00000 ################################################################
10245 22:13:41.914297
10246 22:13:42.185396 02b80000 ################################################################
10247 22:13:42.185569
10248 22:13:42.438972 02c00000 ################################################################
10249 22:13:42.439107
10250 22:13:42.692917 02c80000 ################################################################
10251 22:13:42.693053
10252 22:13:42.947954 02d00000 ################################################################
10253 22:13:42.948112
10254 22:13:43.214664 02d80000 ################################################################
10255 22:13:43.214796
10256 22:13:43.492447 02e00000 ################################################################
10257 22:13:43.492585
10258 22:13:43.770197 02e80000 ################################################################
10259 22:13:43.770328
10260 22:13:44.060818 02f00000 ################################################################
10261 22:13:44.060957
10262 22:13:44.306213 02f80000 ####################################################### done.
10263 22:13:44.306345
10264 22:13:44.309953 The bootfile was 50253454 bytes long.
10265 22:13:44.310027
10266 22:13:44.313206 Sending tftp read request... done.
10267 22:13:44.313294
10268 22:13:44.316525 Waiting for the transfer...
10269 22:13:44.316619
10270 22:13:44.320016 00000000 # done.
10271 22:13:44.320113
10272 22:13:44.326840 Command line loaded dynamically from TFTP file: 10583861/tftp-deploy-vhgxdhl0/kernel/cmdline
10273 22:13:44.326962
10274 22:13:44.336527 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10275 22:13:44.336667
10276 22:13:44.339980 Loading FIT.
10277 22:13:44.340208
10278 22:13:44.343324 Image ramdisk-1 has 40122768 bytes.
10279 22:13:44.343485
10280 22:13:44.343607 Image fdt-1 has 46924 bytes.
10281 22:13:44.343721
10282 22:13:44.346327 Image kernel-1 has 10081729 bytes.
10283 22:13:44.346501
10284 22:13:44.356561 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10285 22:13:44.356807
10286 22:13:44.373271 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10287 22:13:44.373792
10288 22:13:44.380204 Choosing best match conf-1 for compat google,spherion-rev2.
10289 22:13:44.384695
10290 22:13:44.388529 Connected to device vid:did:rid of 1ae0:0028:00
10291 22:13:44.395525
10292 22:13:44.399122 tpm_get_response: command 0x17b, return code 0x0
10293 22:13:44.399650
10294 22:13:44.402150 ec_init: CrosEC protocol v3 supported (256, 248)
10295 22:13:44.406004
10296 22:13:44.409616 tpm_cleanup: add release locality here.
10297 22:13:44.410092
10298 22:13:44.410427 Shutting down all USB controllers.
10299 22:13:44.410740
10300 22:13:44.412609 Removing current net device
10301 22:13:44.413028
10302 22:13:44.419870 Exiting depthcharge with code 4 at timestamp: 61821288
10303 22:13:44.420398
10304 22:13:44.422483 LZMA decompressing kernel-1 to 0x821a6718
10305 22:13:44.422956
10306 22:13:44.425948 LZMA decompressing kernel-1 to 0x40000000
10307 22:13:45.693671
10308 22:13:45.694222 jumping to kernel
10309 22:13:45.696554 end: 2.2.4 bootloader-commands (duration 00:00:34) [common]
10310 22:13:45.697127 start: 2.2.5 auto-login-action (timeout 00:03:51) [common]
10311 22:13:45.697559 Setting prompt string to ['Linux version [0-9]']
10312 22:13:45.697920 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10313 22:13:45.698276 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10314 22:13:45.775396
10315 22:13:45.778861 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10316 22:13:45.782558 start: 2.2.5.1 login-action (timeout 00:03:51) [common]
10317 22:13:45.783034 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10318 22:13:45.783460 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10319 22:13:45.783859 Using line separator: #'\n'#
10320 22:13:45.784186 No login prompt set.
10321 22:13:45.784630 Parsing kernel messages
10322 22:13:45.785095 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10323 22:13:45.786001 [login-action] Waiting for messages, (timeout 00:03:51)
10324 22:13:45.802058 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j1606555-arm64-gcc-10-defconfig-arm64-chromebook-vtq55) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sun Jun 4 21:56:05 UTC 2023
10325 22:13:45.805765 [ 0.000000] random: crng init done
10326 22:13:45.808733 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10327 22:13:45.812211 [ 0.000000] efi: UEFI not found.
10328 22:13:45.822366 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10329 22:13:45.829095 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10330 22:13:45.839186 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10331 22:13:45.848801 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10332 22:13:45.855543 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10333 22:13:45.858671 [ 0.000000] printk: bootconsole [mtk8250] enabled
10334 22:13:45.867290 [ 0.000000] NUMA: No NUMA configuration found
10335 22:13:45.874128 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10336 22:13:45.880082 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcda00-0x23efcffff]
10337 22:13:45.880555 [ 0.000000] Zone ranges:
10338 22:13:45.886934 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10339 22:13:45.890627 [ 0.000000] DMA32 empty
10340 22:13:45.896773 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10341 22:13:45.900265 [ 0.000000] Movable zone start for each node
10342 22:13:45.903246 [ 0.000000] Early memory node ranges
10343 22:13:45.909977 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10344 22:13:45.917057 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10345 22:13:45.922994 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10346 22:13:45.930093 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10347 22:13:45.936353 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10348 22:13:45.943014 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10349 22:13:45.999564 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10350 22:13:46.006791 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10351 22:13:46.012598 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10352 22:13:46.015834 [ 0.000000] psci: probing for conduit method from DT.
10353 22:13:46.023098 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10354 22:13:46.026090 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10355 22:13:46.032895 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10356 22:13:46.036107 [ 0.000000] psci: SMC Calling Convention v1.2
10357 22:13:46.042847 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10358 22:13:46.046264 [ 0.000000] Detected VIPT I-cache on CPU0
10359 22:13:46.052396 [ 0.000000] CPU features: detected: GIC system register CPU interface
10360 22:13:46.059028 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10361 22:13:46.065704 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10362 22:13:46.073107 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10363 22:13:46.079086 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10364 22:13:46.085820 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10365 22:13:46.092676 [ 0.000000] alternatives: applying boot alternatives
10366 22:13:46.095724 [ 0.000000] Fallback order for Node 0: 0
10367 22:13:46.106037 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10368 22:13:46.106546 [ 0.000000] Policy zone: Normal
10369 22:13:46.119467 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10370 22:13:46.129106 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10371 22:13:46.141648 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10372 22:13:46.151848 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10373 22:13:46.157925 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10374 22:13:46.161634 <6>[ 0.000000] software IO TLB: area num 8.
10375 22:13:46.217863 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10376 22:13:46.367307 <6>[ 0.000000] Memory: 7933756K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 419012K reserved, 32768K cma-reserved)
10377 22:13:46.373727 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10378 22:13:46.380716 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10379 22:13:46.383739 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10380 22:13:46.390991 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10381 22:13:46.397245 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10382 22:13:46.400836 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10383 22:13:46.410580 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10384 22:13:46.417566 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10385 22:13:46.420594 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10386 22:13:46.428447 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10387 22:13:46.431629 <6>[ 0.000000] GICv3: 608 SPIs implemented
10388 22:13:46.438405 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10389 22:13:46.441437 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10390 22:13:46.444491 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10391 22:13:46.454632 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10392 22:13:46.464541 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10393 22:13:46.478002 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10394 22:13:46.484502 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10395 22:13:46.493446 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10396 22:13:46.506947 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10397 22:13:46.513623 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10398 22:13:46.520067 <6>[ 0.009178] Console: colour dummy device 80x25
10399 22:13:46.530117 <6>[ 0.013907] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10400 22:13:46.537069 <6>[ 0.024414] pid_max: default: 32768 minimum: 301
10401 22:13:46.540051 <6>[ 0.029317] LSM: Security Framework initializing
10402 22:13:46.546579 <6>[ 0.034255] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10403 22:13:46.556743 <6>[ 0.042070] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10404 22:13:46.562832 <6>[ 0.051503] cblist_init_generic: Setting adjustable number of callback queues.
10405 22:13:46.569634 <6>[ 0.059001] cblist_init_generic: Setting shift to 3 and lim to 1.
10406 22:13:46.576589 <6>[ 0.065340] cblist_init_generic: Setting shift to 3 and lim to 1.
10407 22:13:46.583256 <6>[ 0.071748] rcu: Hierarchical SRCU implementation.
10408 22:13:46.586144 <6>[ 0.076793] rcu: Max phase no-delay instances is 1000.
10409 22:13:46.594787 <6>[ 0.083815] EFI services will not be available.
10410 22:13:46.597620 <6>[ 0.088811] smp: Bringing up secondary CPUs ...
10411 22:13:46.607095 <6>[ 0.093893] Detected VIPT I-cache on CPU1
10412 22:13:46.613749 <6>[ 0.093965] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10413 22:13:46.620547 <6>[ 0.093995] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10414 22:13:46.623388 <6>[ 0.094325] Detected VIPT I-cache on CPU2
10415 22:13:46.630369 <6>[ 0.094373] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10416 22:13:46.636793 <6>[ 0.094388] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10417 22:13:46.643150 <6>[ 0.094645] Detected VIPT I-cache on CPU3
10418 22:13:46.650165 <6>[ 0.094692] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10419 22:13:46.656729 <6>[ 0.094706] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10420 22:13:46.659921 <6>[ 0.095012] CPU features: detected: Spectre-v4
10421 22:13:46.666646 <6>[ 0.095018] CPU features: detected: Spectre-BHB
10422 22:13:46.670233 <6>[ 0.095024] Detected PIPT I-cache on CPU4
10423 22:13:46.676641 <6>[ 0.095083] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10424 22:13:46.683835 <6>[ 0.095099] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10425 22:13:46.686596 <6>[ 0.095392] Detected PIPT I-cache on CPU5
10426 22:13:46.696478 <6>[ 0.095455] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10427 22:13:46.703660 <6>[ 0.095472] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10428 22:13:46.706568 <6>[ 0.095754] Detected PIPT I-cache on CPU6
10429 22:13:46.713438 <6>[ 0.095817] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10430 22:13:46.719713 <6>[ 0.095833] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10431 22:13:46.726410 <6>[ 0.096132] Detected PIPT I-cache on CPU7
10432 22:13:46.733221 <6>[ 0.096199] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10433 22:13:46.739711 <6>[ 0.096215] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10434 22:13:46.743151 <6>[ 0.096263] smp: Brought up 1 node, 8 CPUs
10435 22:13:46.749809 <6>[ 0.237602] SMP: Total of 8 processors activated.
10436 22:13:46.752775 <6>[ 0.242523] CPU features: detected: 32-bit EL0 Support
10437 22:13:46.762810 <6>[ 0.247885] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10438 22:13:46.769575 <6>[ 0.256685] CPU features: detected: Common not Private translations
10439 22:13:46.772887 <6>[ 0.263201] CPU features: detected: CRC32 instructions
10440 22:13:46.779236 <6>[ 0.268552] CPU features: detected: RCpc load-acquire (LDAPR)
10441 22:13:46.785911 <6>[ 0.274511] CPU features: detected: LSE atomic instructions
10442 22:13:46.792763 <6>[ 0.280292] CPU features: detected: Privileged Access Never
10443 22:13:46.796039 <6>[ 0.286072] CPU features: detected: RAS Extension Support
10444 22:13:46.805784 <6>[ 0.291681] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10445 22:13:46.809018 <6>[ 0.298945] CPU: All CPU(s) started at EL2
10446 22:13:46.815501 <6>[ 0.303262] alternatives: applying system-wide alternatives
10447 22:13:46.824462 <6>[ 0.313966] devtmpfs: initialized
10448 22:13:46.836484 <6>[ 0.322791] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10449 22:13:46.846513 <6>[ 0.332755] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10450 22:13:46.853392 <6>[ 0.340669] pinctrl core: initialized pinctrl subsystem
10451 22:13:46.856210 <6>[ 0.347317] DMI not present or invalid.
10452 22:13:46.863259 <6>[ 0.351739] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10453 22:13:46.872748 <6>[ 0.358627] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10454 22:13:46.879301 <6>[ 0.366216] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10455 22:13:46.889712 <6>[ 0.374431] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10456 22:13:46.892765 <6>[ 0.382685] audit: initializing netlink subsys (disabled)
10457 22:13:46.903121 <5>[ 0.388387] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10458 22:13:46.909815 <6>[ 0.389102] thermal_sys: Registered thermal governor 'step_wise'
10459 22:13:46.916473 <6>[ 0.396354] thermal_sys: Registered thermal governor 'power_allocator'
10460 22:13:46.919231 <6>[ 0.402610] cpuidle: using governor menu
10461 22:13:46.926402 <6>[ 0.413579] NET: Registered PF_QIPCRTR protocol family
10462 22:13:46.932826 <6>[ 0.419092] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10463 22:13:46.935732 <6>[ 0.426197] ASID allocator initialised with 32768 entries
10464 22:13:46.943556 <6>[ 0.432764] Serial: AMBA PL011 UART driver
10465 22:13:46.952558 <4>[ 0.441450] Trying to register duplicate clock ID: 134
10466 22:13:47.005844 <6>[ 0.498759] KASLR enabled
10467 22:13:47.020439 <6>[ 0.506435] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10468 22:13:47.027272 <6>[ 0.513449] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10469 22:13:47.033868 <6>[ 0.519940] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10470 22:13:47.040231 <6>[ 0.526944] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10471 22:13:47.046808 <6>[ 0.533433] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10472 22:13:47.053215 <6>[ 0.540438] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10473 22:13:47.060309 <6>[ 0.546924] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10474 22:13:47.067119 <6>[ 0.553930] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10475 22:13:47.070081 <6>[ 0.561411] ACPI: Interpreter disabled.
10476 22:13:47.078641 <6>[ 0.567846] iommu: Default domain type: Translated
10477 22:13:47.085033 <6>[ 0.572960] iommu: DMA domain TLB invalidation policy: strict mode
10478 22:13:47.088087 <5>[ 0.579622] SCSI subsystem initialized
10479 22:13:47.094940 <6>[ 0.583863] usbcore: registered new interface driver usbfs
10480 22:13:47.101846 <6>[ 0.589594] usbcore: registered new interface driver hub
10481 22:13:47.104533 <6>[ 0.595148] usbcore: registered new device driver usb
10482 22:13:47.112165 <6>[ 0.601251] pps_core: LinuxPPS API ver. 1 registered
10483 22:13:47.121795 <6>[ 0.606443] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10484 22:13:47.125689 <6>[ 0.615788] PTP clock support registered
10485 22:13:47.128846 <6>[ 0.620028] EDAC MC: Ver: 3.0.0
10486 22:13:47.136149 <6>[ 0.625219] FPGA manager framework
10487 22:13:47.139772 <6>[ 0.628898] Advanced Linux Sound Architecture Driver Initialized.
10488 22:13:47.142888 <6>[ 0.635655] vgaarb: loaded
10489 22:13:47.149245 <6>[ 0.638818] clocksource: Switched to clocksource arch_sys_counter
10490 22:13:47.156464 <5>[ 0.645266] VFS: Disk quotas dquot_6.6.0
10491 22:13:47.162887 <6>[ 0.649455] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10492 22:13:47.166305 <6>[ 0.656647] pnp: PnP ACPI: disabled
10493 22:13:47.173888 <6>[ 0.663293] NET: Registered PF_INET protocol family
10494 22:13:47.183360 <6>[ 0.668880] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10495 22:13:47.195077 <6>[ 0.681171] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10496 22:13:47.204936 <6>[ 0.689985] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10497 22:13:47.211691 <6>[ 0.697957] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10498 22:13:47.218238 <6>[ 0.706656] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10499 22:13:47.230389 <6>[ 0.716398] TCP: Hash tables configured (established 65536 bind 65536)
10500 22:13:47.236502 <6>[ 0.723264] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10501 22:13:47.243181 <6>[ 0.730459] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10502 22:13:47.249778 <6>[ 0.738163] NET: Registered PF_UNIX/PF_LOCAL protocol family
10503 22:13:47.256430 <6>[ 0.744329] RPC: Registered named UNIX socket transport module.
10504 22:13:47.259544 <6>[ 0.750483] RPC: Registered udp transport module.
10505 22:13:47.266357 <6>[ 0.755416] RPC: Registered tcp transport module.
10506 22:13:47.272969 <6>[ 0.760348] RPC: Registered tcp NFSv4.1 backchannel transport module.
10507 22:13:47.276221 <6>[ 0.767017] PCI: CLS 0 bytes, default 64
10508 22:13:47.279635 <6>[ 0.771407] Unpacking initramfs...
10509 22:13:47.297245 <6>[ 0.783383] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10510 22:13:47.307319 <6>[ 0.792044] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10511 22:13:47.310577 <6>[ 0.800885] kvm [1]: IPA Size Limit: 40 bits
10512 22:13:47.317320 <6>[ 0.805417] kvm [1]: GICv3: no GICV resource entry
10513 22:13:47.320482 <6>[ 0.810438] kvm [1]: disabling GICv2 emulation
10514 22:13:47.327308 <6>[ 0.815125] kvm [1]: GIC system register CPU interface enabled
10515 22:13:47.330280 <6>[ 0.821287] kvm [1]: vgic interrupt IRQ18
10516 22:13:47.337285 <6>[ 0.826908] kvm [1]: VHE mode initialized successfully
10517 22:13:47.344222 <5>[ 0.833329] Initialise system trusted keyrings
10518 22:13:47.350883 <6>[ 0.838131] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10519 22:13:47.358847 <6>[ 0.848314] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10520 22:13:47.365979 <5>[ 0.854700] NFS: Registering the id_resolver key type
10521 22:13:47.368880 <5>[ 0.859996] Key type id_resolver registered
10522 22:13:47.375540 <5>[ 0.864410] Key type id_legacy registered
10523 22:13:47.382110 <6>[ 0.868693] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10524 22:13:47.389234 <6>[ 0.875618] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10525 22:13:47.395510 <6>[ 0.883336] 9p: Installing v9fs 9p2000 file system support
10526 22:13:47.432867 <5>[ 0.922135] Key type asymmetric registered
10527 22:13:47.436415 <5>[ 0.926470] Asymmetric key parser 'x509' registered
10528 22:13:47.446611 <6>[ 0.931619] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10529 22:13:47.449579 <6>[ 0.939250] io scheduler mq-deadline registered
10530 22:13:47.453165 <6>[ 0.944014] io scheduler kyber registered
10531 22:13:47.471842 <6>[ 0.960999] EINJ: ACPI disabled.
10532 22:13:47.504010 <4>[ 0.986583] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10533 22:13:47.513920 <4>[ 0.997209] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10534 22:13:47.528501 <6>[ 1.017762] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10535 22:13:47.536634 <6>[ 1.025787] printk: console [ttyS0] disabled
10536 22:13:47.564545 <6>[ 1.050436] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10537 22:13:47.570751 <6>[ 1.059910] printk: console [ttyS0] enabled
10538 22:13:47.574188 <6>[ 1.059910] printk: console [ttyS0] enabled
10539 22:13:47.580675 <6>[ 1.068802] printk: bootconsole [mtk8250] disabled
10540 22:13:47.584056 <6>[ 1.068802] printk: bootconsole [mtk8250] disabled
10541 22:13:47.590696 <6>[ 1.080144] SuperH (H)SCI(F) driver initialized
10542 22:13:47.594275 <6>[ 1.085419] msm_serial: driver initialized
10543 22:13:47.608135 <6>[ 1.094422] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10544 22:13:47.618458 <6>[ 1.102981] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10545 22:13:47.624798 <6>[ 1.111526] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10546 22:13:47.634700 <6>[ 1.120156] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10547 22:13:47.641737 <6>[ 1.128862] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10548 22:13:47.651289 <6>[ 1.137584] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10549 22:13:47.661344 <6>[ 1.146127] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10550 22:13:47.667814 <6>[ 1.154930] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10551 22:13:47.677948 <6>[ 1.163473] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10552 22:13:47.689108 <6>[ 1.178847] loop: module loaded
10553 22:13:47.695689 <6>[ 1.184838] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10554 22:13:47.718832 <4>[ 1.208167] mtk-pmic-keys: Failed to locate of_node [id: -1]
10555 22:13:47.725415 <6>[ 1.215005] megasas: 07.719.03.00-rc1
10556 22:13:47.735252 <6>[ 1.224592] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10557 22:13:47.744578 <6>[ 1.234208] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10558 22:13:47.761394 <6>[ 1.251044] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10559 22:13:47.818530 <6>[ 1.301620] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.153/cr50_v3.94_pp.113-620c9
10560 22:13:48.885738 <6>[ 2.375371] Freeing initrd memory: 39180K
10561 22:13:48.895540 <6>[ 2.385473] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10562 22:13:48.906707 <6>[ 2.396485] tun: Universal TUN/TAP device driver, 1.6
10563 22:13:48.910122 <6>[ 2.402517] thunder_xcv, ver 1.0
10564 22:13:48.913794 <6>[ 2.406019] thunder_bgx, ver 1.0
10565 22:13:48.916875 <6>[ 2.409514] nicpf, ver 1.0
10566 22:13:48.927671 <6>[ 2.413513] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10567 22:13:48.930525 <6>[ 2.420990] hns3: Copyright (c) 2017 Huawei Corporation.
10568 22:13:48.937346 <6>[ 2.426574] hclge is initializing
10569 22:13:48.941096 <6>[ 2.430155] e1000: Intel(R) PRO/1000 Network Driver
10570 22:13:48.947669 <6>[ 2.435284] e1000: Copyright (c) 1999-2006 Intel Corporation.
10571 22:13:48.950991 <6>[ 2.441300] e1000e: Intel(R) PRO/1000 Network Driver
10572 22:13:48.957552 <6>[ 2.446515] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10573 22:13:48.964040 <6>[ 2.452702] igb: Intel(R) Gigabit Ethernet Network Driver
10574 22:13:48.970747 <6>[ 2.458351] igb: Copyright (c) 2007-2014 Intel Corporation.
10575 22:13:48.977206 <6>[ 2.464187] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10576 22:13:48.984022 <6>[ 2.470704] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10577 22:13:48.987477 <6>[ 2.477161] sky2: driver version 1.30
10578 22:13:48.993468 <6>[ 2.482137] VFIO - User Level meta-driver version: 0.3
10579 22:13:49.001476 <6>[ 2.490274] usbcore: registered new interface driver usb-storage
10580 22:13:49.007822 <6>[ 2.496721] usbcore: registered new device driver onboard-usb-hub
10581 22:13:49.016814 <6>[ 2.505762] mt6397-rtc mt6359-rtc: registered as rtc0
10582 22:13:49.026517 <6>[ 2.511227] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-04T22:14:01 UTC (1685916841)
10583 22:13:49.029562 <6>[ 2.520783] i2c_dev: i2c /dev entries driver
10584 22:13:49.046355 <6>[ 2.532417] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10585 22:13:49.053665 <6>[ 2.542634] sdhci: Secure Digital Host Controller Interface driver
10586 22:13:49.059676 <6>[ 2.549073] sdhci: Copyright(c) Pierre Ossman
10587 22:13:49.066771 <6>[ 2.554466] Synopsys Designware Multimedia Card Interface Driver
10588 22:13:49.069895 <6>[ 2.561086] mmc0: CQHCI version 5.10
10589 22:13:49.076528 <6>[ 2.561617] sdhci-pltfm: SDHCI platform and OF driver helper
10590 22:13:49.083198 <6>[ 2.572966] ledtrig-cpu: registered to indicate activity on CPUs
10591 22:13:49.093861 <6>[ 2.580322] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10592 22:13:49.097515 <6>[ 2.587713] usbcore: registered new interface driver usbhid
10593 22:13:49.103808 <6>[ 2.593541] usbhid: USB HID core driver
10594 22:13:49.110470 <6>[ 2.597781] spi_master spi0: will run message pump with realtime priority
10595 22:13:49.157324 <6>[ 2.640569] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10596 22:13:49.177099 <6>[ 2.656520] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10597 22:13:49.180499 <6>[ 2.670036] mmc0: Command Queue Engine enabled
10598 22:13:49.187510 <6>[ 2.671983] cros-ec-spi spi0.0: Chrome EC device registered
10599 22:13:49.190720 <6>[ 2.674762] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10600 22:13:49.198392 <6>[ 2.687843] mmcblk0: mmc0:0001 DA4128 116 GiB
10601 22:13:49.211851 <6>[ 2.697720] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10602 22:13:49.218033 <6>[ 2.698526] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10603 22:13:49.224953 <6>[ 2.709254] NET: Registered PF_PACKET protocol family
10604 22:13:49.227974 <6>[ 2.714317] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10605 22:13:49.234379 <6>[ 2.718396] 9pnet: Installing 9P2000 support
10606 22:13:49.238233 <6>[ 2.724176] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10607 22:13:49.244784 <5>[ 2.728059] Key type dns_resolver registered
10608 22:13:49.251436 <6>[ 2.733913] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10609 22:13:49.254768 <6>[ 2.738351] registered taskstats version 1
10610 22:13:49.258127 <5>[ 2.748669] Loading compiled-in X.509 certificates
10611 22:13:49.292565 <4>[ 2.775552] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10612 22:13:49.303261 <4>[ 2.786241] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10613 22:13:49.313207 <3>[ 2.799145] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10614 22:13:49.325406 <6>[ 2.814569] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10615 22:13:49.332142 <6>[ 2.821348] xhci-mtk 11200000.usb: xHCI Host Controller
10616 22:13:49.338736 <6>[ 2.826855] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10617 22:13:49.348363 <6>[ 2.834713] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10618 22:13:49.355556 <6>[ 2.844177] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10619 22:13:49.361888 <6>[ 2.850377] xhci-mtk 11200000.usb: xHCI Host Controller
10620 22:13:49.368332 <6>[ 2.855877] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10621 22:13:49.374937 <6>[ 2.863534] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10622 22:13:49.382337 <6>[ 2.871335] hub 1-0:1.0: USB hub found
10623 22:13:49.385587 <6>[ 2.875372] hub 1-0:1.0: 1 port detected
10624 22:13:49.395383 <6>[ 2.879730] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10625 22:13:49.398764 <6>[ 2.888506] hub 2-0:1.0: USB hub found
10626 22:13:49.401501 <6>[ 2.892541] hub 2-0:1.0: 1 port detected
10627 22:13:49.410491 <6>[ 2.899786] mtk-msdc 11f70000.mmc: Got CD GPIO
10628 22:13:49.427221 <6>[ 2.913211] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10629 22:13:49.433902 <6>[ 2.921247] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10630 22:13:49.443814 <4>[ 2.929230] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10631 22:13:49.453797 <6>[ 2.938905] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10632 22:13:49.460468 <6>[ 2.946988] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10633 22:13:49.466978 <6>[ 2.954990] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10634 22:13:49.477032 <6>[ 2.962910] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10635 22:13:49.483691 <6>[ 2.970732] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10636 22:13:49.493584 <6>[ 2.978555] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10637 22:13:49.503671 <6>[ 2.989141] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10638 22:13:49.510474 <6>[ 2.997514] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10639 22:13:49.520467 <6>[ 3.005867] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10640 22:13:49.526963 <6>[ 3.014211] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10641 22:13:49.537037 <6>[ 3.022554] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10642 22:13:49.543715 <6>[ 3.030898] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10643 22:13:49.553587 <6>[ 3.039241] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10644 22:13:49.560169 <6>[ 3.047584] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10645 22:13:49.569826 <6>[ 3.055927] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10646 22:13:49.576840 <6>[ 3.064271] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10647 22:13:49.586840 <6>[ 3.072615] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10648 22:13:49.596504 <6>[ 3.080958] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10649 22:13:49.603070 <6>[ 3.089301] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10650 22:13:49.613114 <6>[ 3.097644] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10651 22:13:49.620027 <6>[ 3.105995] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10652 22:13:49.626318 <6>[ 3.114947] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10653 22:13:49.632984 <6>[ 3.122426] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10654 22:13:49.640154 <6>[ 3.129551] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10655 22:13:49.650602 <6>[ 3.136717] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10656 22:13:49.656985 <6>[ 3.144058] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10657 22:13:49.667510 <6>[ 3.151047] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10658 22:13:49.674018 <6>[ 3.160208] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10659 22:13:49.683358 <6>[ 3.169336] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10660 22:13:49.693776 <6>[ 3.178638] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10661 22:13:49.703319 <6>[ 3.188115] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10662 22:13:49.713385 <6>[ 3.197590] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10663 22:13:49.720328 <6>[ 3.206717] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10664 22:13:49.730068 <6>[ 3.216191] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10665 22:13:49.740099 <6>[ 3.225319] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10666 22:13:49.749951 <6>[ 3.234620] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10667 22:13:49.759955 <6>[ 3.244794] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10668 22:13:49.770692 <6>[ 3.256662] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10669 22:13:49.793606 <6>[ 3.279267] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10670 22:13:49.822023 <6>[ 3.311292] hub 2-1:1.0: USB hub found
10671 22:13:49.825023 <6>[ 3.315833] hub 2-1:1.0: 3 ports detected
10672 22:13:49.944741 <6>[ 3.431063] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10673 22:13:50.097967 <6>[ 3.587436] hub 1-1:1.0: USB hub found
10674 22:13:50.101594 <6>[ 3.591806] hub 1-1:1.0: 4 ports detected
10675 22:13:50.181171 <6>[ 3.667347] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10676 22:13:50.420621 <6>[ 3.907122] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10677 22:13:50.554383 <6>[ 4.043378] hub 1-1.4:1.0: USB hub found
10678 22:13:50.557244 <6>[ 4.048030] hub 1-1.4:1.0: 2 ports detected
10679 22:13:50.852918 <6>[ 4.339056] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10680 22:13:51.044813 <6>[ 4.531088] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10681 22:14:02.069847 <6>[ 15.563641] ALSA device list:
10682 22:14:02.076811 <6>[ 15.566897] No soundcards found.
10683 22:14:02.089150 <6>[ 15.579323] Freeing unused kernel memory: 8384K
10684 22:14:02.092397 <6>[ 15.584253] Run /init as init process
10685 22:14:02.121905 <6>[ 15.612293] NET: Registered PF_INET6 protocol family
10686 22:14:02.128642 <6>[ 15.618751] Segment Routing with IPv6
10687 22:14:02.131127 <6>[ 15.622709] In-situ OAM (IOAM) with IPv6
10688 22:14:02.166728 <30>[ 15.637189] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10689 22:14:02.169574 <30>[ 15.661295] systemd[1]: Detected architecture arm64.
10690 22:14:02.172949
10691 22:14:02.176672 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10692 22:14:02.177236
10693 22:14:02.192555 <30>[ 15.683189] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10694 22:14:02.335990 <30>[ 15.823059] systemd[1]: Queued start job for default target Graphical Interface.
10695 22:14:02.374125 <30>[ 15.864543] systemd[1]: Created slice system-getty.slice.
10696 22:14:02.380600 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10697 22:14:02.397630 <30>[ 15.887660] systemd[1]: Created slice system-modprobe.slice.
10698 22:14:02.403504 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10699 22:14:02.421498 <30>[ 15.912221] systemd[1]: Created slice system-serial\x2dgetty.slice.
10700 22:14:02.431483 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10701 22:14:02.444966 <30>[ 15.935603] systemd[1]: Created slice User and Session Slice.
10702 22:14:02.451560 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10703 22:14:02.472255 <30>[ 15.959637] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10704 22:14:02.482149 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10705 22:14:02.500129 <30>[ 15.987598] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10706 22:14:02.506525 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10707 22:14:02.527126 <30>[ 16.011200] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10708 22:14:02.533929 <30>[ 16.023247] systemd[1]: Reached target Local Encrypted Volumes.
10709 22:14:02.540041 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10710 22:14:02.556359 <30>[ 16.047439] systemd[1]: Reached target Paths.
10711 22:14:02.560274 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10712 22:14:02.576645 <30>[ 16.067147] systemd[1]: Reached target Remote File Systems.
10713 22:14:02.582568 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10714 22:14:02.600559 <30>[ 16.091357] systemd[1]: Reached target Slices.
10715 22:14:02.606816 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10716 22:14:02.620577 <30>[ 16.111173] systemd[1]: Reached target Swap.
10717 22:14:02.623486 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10718 22:14:02.643369 <30>[ 16.131448] systemd[1]: Listening on initctl Compatibility Named Pipe.
10719 22:14:02.650011 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10720 22:14:02.656849 <30>[ 16.146178] systemd[1]: Listening on Journal Audit Socket.
10721 22:14:02.663836 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10722 22:14:02.676560 <30>[ 16.167415] systemd[1]: Listening on Journal Socket (/dev/log).
10723 22:14:02.682820 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10724 22:14:02.700619 <30>[ 16.191875] systemd[1]: Listening on Journal Socket.
10725 22:14:02.707317 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10726 22:14:02.721153 <30>[ 16.211525] systemd[1]: Listening on Network Service Netlink Socket.
10727 22:14:02.730590 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10728 22:14:02.745196 <30>[ 16.235861] systemd[1]: Listening on udev Control Socket.
10729 22:14:02.751962 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10730 22:14:02.768962 <30>[ 16.259798] systemd[1]: Listening on udev Kernel Socket.
10731 22:14:02.775686 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10732 22:14:02.812763 <30>[ 16.303485] systemd[1]: Mounting Huge Pages File System...
10733 22:14:02.819491 Mounting [0;1;39mHuge Pages File System[0m...
10734 22:14:02.834637 <30>[ 16.325376] systemd[1]: Mounting POSIX Message Queue File System...
10735 22:14:02.841263 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10736 22:14:02.858832 <30>[ 16.349278] systemd[1]: Mounting Kernel Debug File System...
10737 22:14:02.865396 Mounting [0;1;39mKernel Debug File System[0m...
10738 22:14:02.883838 <30>[ 16.371421] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10739 22:14:02.894959 <30>[ 16.382386] systemd[1]: Starting Create list of static device nodes for the current kernel...
10740 22:14:02.901295 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10741 22:14:02.919069 <30>[ 16.409355] systemd[1]: Starting Load Kernel Module configfs...
10742 22:14:02.925239 Starting [0;1;39mLoad Kernel Module configfs[0m...
10743 22:14:02.942843 <30>[ 16.433446] systemd[1]: Starting Load Kernel Module drm...
10744 22:14:02.949372 Starting [0;1;39mLoad Kernel Module drm[0m...
10745 22:14:02.968066 <30>[ 16.455326] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10746 22:14:02.978718 <30>[ 16.469150] systemd[1]: Starting Journal Service...
10747 22:14:02.981884 Starting [0;1;39mJournal Service[0m...
10748 22:14:02.998937 <30>[ 16.489816] systemd[1]: Starting Load Kernel Modules...
10749 22:14:03.005866 Starting [0;1;39mLoad Kernel Modules[0m...
10750 22:14:03.026983 <30>[ 16.513925] systemd[1]: Starting Remount Root and Kernel File Systems...
10751 22:14:03.033297 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10752 22:14:03.051619 <30>[ 16.541856] systemd[1]: Starting Coldplug All udev Devices...
10753 22:14:03.058085 Starting [0;1;39mColdplug All udev Devices[0m...
10754 22:14:03.074867 <30>[ 16.565812] systemd[1]: Mounted Huge Pages File System.
10755 22:14:03.081641 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10756 22:14:03.096363 <30>[ 16.587577] systemd[1]: Started Journal Service.
10757 22:14:03.103829 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10758 22:14:03.118116 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10759 22:14:03.137558 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10760 22:14:03.157093 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10761 22:14:03.174060 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10762 22:14:03.190048 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10763 22:14:03.205500 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10764 22:14:03.225086 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10765 22:14:03.240973 See 'systemctl status systemd-remount-fs.service' for details.
10766 22:14:03.289584 Mounting [0;1;39mKernel Configuration File System[0m...
10767 22:14:03.306615 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10768 22:14:03.325020 <46>[ 16.812153] systemd-journald[177]: Received client request to flush runtime journal.
10769 22:14:03.333004 Starting [0;1;39mLoad/Save Random Seed[0m...
10770 22:14:03.351385 Starting [0;1;39mApply Kernel Variables[0m...
10771 22:14:03.367654 Starting [0;1;39mCreate System Users[0m...
10772 22:14:03.385459 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10773 22:14:03.405209 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10774 22:14:03.417387 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10775 22:14:03.433646 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10776 22:14:03.450168 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10777 22:14:03.465504 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10778 22:14:03.521472 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10779 22:14:03.543934 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10780 22:14:03.561035 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10781 22:14:03.576370 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10782 22:14:03.633194 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10783 22:14:03.656267 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10784 22:14:03.673256 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10785 22:14:03.693328 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10786 22:14:03.749814 Starting [0;1;39mNetwork Service[0m...
10787 22:14:03.770165 Starting [0;1;39mNetwork Time Synchronization[0m...
10788 22:14:03.789629 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10789 22:14:03.820717 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10790 22:14:03.836749 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10791 22:14:03.872203 <6>[ 17.359990] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10792 22:14:03.878919 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10793 22:14:03.886076 <6>[ 17.376600] remoteproc remoteproc0: scp is available
10794 22:14:03.895150 <6>[ 17.385853] remoteproc remoteproc0: powering up scp
10795 22:14:03.904691 [[0;32m OK [<6>[ 17.392419] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10796 22:14:03.911387 0m] Started [0;<6>[ 17.402468] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10797 22:14:03.917821 1;39mNetwork Time Synchronization[0m.
10798 22:14:03.930960 <3>[ 17.418994] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10799 22:14:03.937624 <3>[ 17.427426] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10800 22:14:03.947472 <3>[ 17.435678] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10801 22:14:03.960705 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m<6>[ 17.450580] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10802 22:14:03.970936 <3>[ 17.455493] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10803 22:14:03.971057 .
10804 22:14:03.977725 <6>[ 17.458670] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10805 22:14:03.987539 <3>[ 17.470040] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10806 22:14:03.997352 <6>[ 17.475525] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10807 22:14:04.004293 <3>[ 17.483908] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10808 22:14:04.011174 <3>[ 17.500653] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10809 22:14:04.021095 [[0;32m OK [<3>[ 17.508757] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10810 22:14:04.027471 0m] Reached target [0;1;39mSystem Time Set[0m.
10811 22:14:04.034618 <3>[ 17.523273] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10812 22:14:04.043927 <4>[ 17.525704] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10813 22:14:04.050579 <6>[ 17.534394] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10814 22:14:04.057115 <6>[ 17.534401] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10815 22:14:04.067530 <3>[ 17.542826] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10816 22:14:04.073962 <4>[ 17.542855] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10817 22:14:04.080792 <6>[ 17.547320] remoteproc remoteproc0: remote processor scp is now up
10818 22:14:04.086986 <3>[ 17.554533] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10819 22:14:04.097054 <3>[ 17.584596] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10820 22:14:04.103979 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10821 22:14:04.110330 <3>[ 17.599939] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10822 22:14:04.117542 <6>[ 17.605846] mc: Linux media interface: v0.10
10823 22:14:04.124088 <3>[ 17.608246] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10824 22:14:04.134072 <3>[ 17.620756] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10825 22:14:04.140781 <6>[ 17.621570] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10826 22:14:04.147216 <3>[ 17.628892] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10827 22:14:04.153903 <6>[ 17.631637] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10828 22:14:04.160398 <6>[ 17.631647] pci_bus 0000:00: root bus resource [bus 00-ff]
10829 22:14:04.166897 <6>[ 17.631656] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10830 22:14:04.177377 <6>[ 17.631661] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10831 22:14:04.183467 <6>[ 17.631706] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10832 22:14:04.190569 <6>[ 17.631731] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10833 22:14:04.196760 <6>[ 17.631833] pci 0000:00:00.0: supports D1 D2
10834 22:14:04.203831 <6>[ 17.631839] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10835 22:14:04.210980 <6>[ 17.639308] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10836 22:14:04.220506 <6>[ 17.639595] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10837 22:14:04.230375 <6>[ 17.641354] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10838 22:14:04.237713 <3>[ 17.644618] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10839 22:14:04.247913 <3>[ 17.644703] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10840 22:14:04.251151 <6>[ 17.647453] usbcore: registered new interface driver r8152
10841 22:14:04.257824 <6>[ 17.651692] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10842 22:14:04.267987 <4>[ 17.679384] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10843 22:14:04.271344 <4>[ 17.679384] Fallback method does not support PEC.
10844 22:14:04.281003 <6>[ 17.680662] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10845 22:14:04.287541 <6>[ 17.683109] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10846 22:14:04.297783 <3>[ 17.704433] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10847 22:14:04.304986 <6>[ 17.708346] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10848 22:14:04.311743 <6>[ 17.743737] videodev: Linux video capture interface: v2.00
10849 22:14:04.321905 <3>[ 17.748247] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10850 22:14:04.328265 <6>[ 17.749639] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10851 22:14:04.334540 <3>[ 17.802153] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10852 22:14:04.341437 <6>[ 17.807913] pci 0000:01:00.0: supports D1 D2
10853 22:14:04.347828 <6>[ 17.837200] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10854 22:14:04.354794 <6>[ 17.837496] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10855 22:14:04.364462 Starting [0;1;39mLoad/Save Screen …o<6>[ 17.854525] usbcore: registered new interface driver cdc_ether
10856 22:14:04.367865 f leds:white:kbd_backlight[0m...
10857 22:14:04.370902 <6>[ 17.865299] Bluetooth: Core ver 2.22
10858 22:14:04.378207 <6>[ 17.869577] NET: Registered PF_BLUETOOTH protocol family
10859 22:14:04.385000 <6>[ 17.875186] Bluetooth: HCI device and connection manager initialized
10860 22:14:04.391358 <6>[ 17.877231] usbcore: registered new interface driver r8153_ecm
10861 22:14:04.398369 <6>[ 17.878943] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10862 22:14:04.404895 <6>[ 17.878989] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10863 22:14:04.415534 <6>[ 17.878997] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10864 22:14:04.422574 <6>[ 17.879011] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10865 22:14:04.429258 <6>[ 17.879028] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10866 22:14:04.439161 <6>[ 17.879044] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10867 22:14:04.442379 <6>[ 17.879060] pci 0000:00:00.0: PCI bridge to [bus 01]
10868 22:14:04.452707 <6>[ 17.879067] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10869 22:14:04.459461 <6>[ 17.879313] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10870 22:14:04.466140 <6>[ 17.880535] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10871 22:14:04.469464 <6>[ 17.880767] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10872 22:14:04.475971 <6>[ 17.881806] Bluetooth: HCI socket layer initialized
10873 22:14:04.479565 <6>[ 17.881817] Bluetooth: L2CAP socket layer initialized
10874 22:14:04.488808 <4>[ 17.903399] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10875 22:14:04.499068 <3>[ 17.909614] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10876 22:14:04.502751 <6>[ 17.910882] Bluetooth: SCO socket layer initialized
10877 22:14:04.512547 <6>[ 17.921458] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10878 22:14:04.518935 <4>[ 17.926963] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10879 22:14:04.529934 <3>[ 17.931648] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10880 22:14:04.533443 <6>[ 17.963550] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10881 22:14:04.547557 <6>[ 17.976240] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10882 22:14:04.553959 <5>[ 17.990335] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10883 22:14:04.560980 <6>[ 17.996148] usbcore: registered new interface driver uvcvideo
10884 22:14:04.567645 <6>[ 17.997009] usbcore: registered new interface driver btusb
10885 22:14:04.574022 <5>[ 18.012265] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10886 22:14:04.582038 <6>[ 18.015697] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10887 22:14:04.591886 <4>[ 18.016032] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10888 22:14:04.599024 <3>[ 18.016048] Bluetooth: hci0: Failed to load firmware file (-2)
10889 22:14:04.606035 <3>[ 18.016054] Bluetooth: hci0: Failed to set up firmware (-2)
10890 22:14:04.616161 <4>[ 18.016061] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10891 22:14:04.623235 <4>[ 18.024578] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10892 22:14:04.633040 <3>[ 18.033629] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10893 22:14:04.642368 <6>[ 18.033790] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10894 22:14:04.649099 <3>[ 18.035312] power_supply sbs-5-000b: driver failed to report `cycle_count' property: -6
10895 22:14:04.655658 <6>[ 18.043331] cfg80211: failed to load regulatory.db
10896 22:14:04.662243 <3>[ 18.043956] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10897 22:14:04.669350 <6>[ 18.070256] r8152 2-1.3:1.0 eth0: v1.12.13
10898 22:14:04.675594 <3>[ 18.077421] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10899 22:14:04.685995 <3>[ 18.100227] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10900 22:14:04.692708 <6>[ 18.113195] r8152 2-1.3:1.0 enx00e04c787aaa: renamed from eth0
10901 22:14:04.699532 <6>[ 18.147738] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10902 22:14:04.706771 <6>[ 18.194864] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10903 22:14:04.709689 Starting [0;1;39mNetwork Name Resolution[0m...
10904 22:14:04.733085 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of l<6>[ 18.221669] mt7921e 0000:01:00.0: ASIC revision: 79610010
10905 22:14:04.735864 eds:white:kbd_backlight[0m.
10906 22:14:04.775999 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10907 22:14:04.838563 <4>[ 18.322896] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10908 22:14:04.934020 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10909 22:14:04.958969 [[0;32m OK [0m] Reached targ<4>[ 18.441487] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10910 22:14:04.959467 et [0;1;39mNetwork[0m.
10911 22:14:04.980701 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10912 22:14:04.992185 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10913 22:14:05.011549 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10914 22:14:05.027552 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10915 22:14:05.040506 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10916 22:14:05.060628 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10917 22:14:05.078127 <4>[ 18.562382] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10918 22:14:05.084470 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10919 22:14:05.100008 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10920 22:14:05.119960 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10921 22:14:05.160364 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10922 22:14:05.198064 <4>[ 18.682283] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10923 22:14:05.202658 Starting [0;1;39mUser Login Management[0m...
10924 22:14:05.220812 Starting [0;1;39mPermit User Sessions[0m...
10925 22:14:05.238387 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10926 22:14:05.255499 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10927 22:14:05.272893 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10928 22:14:05.288810 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10929 22:14:05.317154 Startin<4>[ 18.802127] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10930 22:14:05.324129 g [0;1;39mLoad/Save RF Kill Switch Status[0m...
10931 22:14:05.340844 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10932 22:14:05.361211 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10933 22:14:05.376956 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10934 22:14:05.392075 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10935 22:14:05.436779 <4>[ 18.921495] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10936 22:14:05.452070 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10937 22:14:05.480611 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10938 22:14:05.494828
10939 22:14:05.495372
10940 22:14:05.497888 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10941 22:14:05.498332
10942 22:14:05.501199 debian-bullseye-arm64 login: root (automatic login)
10943 22:14:05.501784
10944 22:14:05.502152
10945 22:14:05.519075 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Sun Jun 4 21:56:05 UTC 2023 aarch64
10946 22:14:05.519613
10947 22:14:05.525296 The programs included with the Debian GNU/Linux system are free software;
10948 22:14:05.532249 the exact distribution terms for each program are described in the
10949 22:14:05.535307 individual files in /usr/share/doc/*/copyright.
10950 22:14:05.535738
10951 22:14:05.541612 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10952 22:14:05.542043 permitted by applicable law.
10953 22:14:05.545784 Matched prompt #10: / #
10955 22:14:05.546946 Setting prompt string to ['/ #']
10956 22:14:05.547386 end: 2.2.5.1 login-action (duration 00:00:20) [common]
10958 22:14:05.548561 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
10959 22:14:05.549025 start: 2.2.6 expect-shell-connection (timeout 00:03:32) [common]
10960 22:14:05.549400 Setting prompt string to ['/ #']
10961 22:14:05.549744 Forcing a shell prompt, looking for ['/ #']
10963 22:14:05.600685 / # <4>[ 19.0415
10964 22:14:05.601305 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10965 22:14:05.601903 Waiting using forced prompt support (timeout 00:02:30)
10966 22:14:05.602399 06] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10967 22:14:05.606882
10968 22:14:05.607645 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10969 22:14:05.608125 start: 2.2.7 export-device-env (timeout 00:03:32) [common]
10970 22:14:05.608599 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10971 22:14:05.609036 end: 2.2 depthcharge-retry (duration 00:01:28) [common]
10972 22:14:05.609463 end: 2 depthcharge-action (duration 00:01:28) [common]
10973 22:14:05.609940 start: 3 lava-test-retry (timeout 00:08:12) [common]
10974 22:14:05.610362 start: 3.1 lava-test-shell (timeout 00:08:12) [common]
10975 22:14:05.610740 Using namespace: common
10977 22:14:05.711927 / # #
10978 22:14:05.712551 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
10979 22:14:05.713227 <4>[ 19.161520] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10980 22:14:05.718014 #
10981 22:14:05.718855 Using /lava-10583861
10983 22:14:05.820030 / # export SHELL=/bin/sh
10984 22:14:05.820809 export SHELL=/bin/sh<4>[ 19.281522] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10985 22:14:05.826432
10987 22:14:05.927979 / # . /lava-10583861/environment
10988 22:14:05.928728 . /lava-10583861/environment<4>[ 19.401384] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10989 22:14:05.934059
10991 22:14:06.035784 / # /lava-10583861/bin/lava-test-runner /lava-10583861/0
10992 22:14:06.036392 Test shell timeout: 10s (minimum of the action and connection timeout)
10993 22:14:06.038085 /lava-10583861/bin/lava-test-runner /lava-10583861/0<3>[ 19.519216] mt7921e 0000:01:00.0: hardware init failed
10994 22:14:06.042065
10995 22:14:06.089862 + export TESTRUN_ID=0_v4l2-compliance-uvc
10996 22:14:06.090362 + cd /lava-10583861/0/tests/0_v4l2-compliance-uvc
10997 22:14:06.090708 + cat uuid
10998 22:14:06.091027 + UUID=10583861_1.5.2.3.1
10999 22:14:06.091335 + set +x
11000 22:14:06.091640 <LAVA_SIGNAL_STARTRUN 0_v4l2-compliance-uvc 10583861_1.5.2.3.1>
11001 22:14:06.092219 Received signal: <STARTRUN> 0_v4l2-compliance-uvc 10583861_1.5.2.3.1
11002 22:14:06.092560 Starting test lava.0_v4l2-compliance-uvc (10583861_1.5.2.3.1)
11003 22:14:06.092948 Skipping test definition patterns.
11004 22:14:06.093432 + /usr/bin/v4l2-parser.sh -d uvcvideo
11005 22:14:06.093836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=device-presence RESULT=pass>
11006 22:14:06.094147 device: /dev/video0
11007 22:14:06.094754 Received signal: <TESTCASE> TEST_CASE_ID=device-presence RESULT=pass
11009 22:14:06.235658 <6>[ 19.723321] IPv6: ADDRCONF(NETDEV_CHANGE): enx00e04c787aaa: link becomes ready
11010 22:14:06.242263 <6>[ 19.731402] r8152 2-1.3:1.0 enx00e04c787aaa: carrier on
11011 22:14:10.140415 <4>[ 23.631934] ------------[ cut here ]------------
11012 22:14:10.146790 <4>[ 23.636864] get_vaddr_frames() cannot follow VM_IO mapping
11013 22:14:10.157200 <4>[ 23.637008] WARNING: CPU: 3 PID: 304 at drivers/media/common/videobuf2/frame_vector.c:59 get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11014 22:14:10.206741 <4>[ 23.655111] Modules linked in: mt7921e mt7921_common mt76_connac_lib mt76 mac80211 libarc4 btusb cfg80211 btintel cros_ec_rpmsg btmtk mtk_vcodec_enc mtk_vcodec_common mtk_vpu btrtl btbcm uvcvideo v4l2_mem2mem videobuf2_vmalloc videobuf2_dma_contig r8153_ecm videobuf2_memops bluetooth videobuf2_v4l2 videobuf2_common cdc_ether ecdh_generic ecc usbnet videodev r8152 crct10dif_ce mc rfkill elants_i2c elan_i2c sbs_battery hid_google_hammer pcie_mediatek_gen3 hid_vivaldi_common cros_ec_chardev cros_ec_typec mtk_scp mtk_rpmsg mtk_scp_ipi ip_tables x_tables ipv6
11015 22:14:10.213193 <4>[ 23.704496] CPU: 3 PID: 304 Comm: v4l2-compliance Not tainted 6.1.31 #1
11016 22:14:10.220417 <4>[ 23.711360] Hardware name: Google Spherion (rev0 - 3) (DT)
11017 22:14:10.226817 <4>[ 23.717095] pstate: 60400009 (nZCv daif +PAN -UAO -TCO -DIT -SSBS BTYPE=--)
11018 22:14:10.233491 <4>[ 23.724306] pc : get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11019 22:14:10.239963 <4>[ 23.730398] lr : get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11020 22:14:10.243313 <4>[ 23.736489] sp : ffff8000091cb810
11021 22:14:10.250075 <4>[ 23.740052] x29: ffff8000091cb810 x28: ffffaf7110fd2000 x27: ffffaf7110fce238
11022 22:14:10.259653 <4>[ 23.747439] x26: 0000000000000000 x25: ffffaf7110fd24c0 x24: ffff1268002d4538
11023 22:14:10.266463 <4>[ 23.754826] x23: 00000000001c2000 x22: 0000000000000000 x21: 0000000000000000
11024 22:14:10.273015 <4>[ 23.762213] x20: 00000000fffffff2 x19: ffff12680e543000 x18: fffffffffffe9530
11025 22:14:10.279826 <4>[ 23.769599] x17: 0000000000000000 x16: ffffaf714c68bb60 x15: 0000000000000038
11026 22:14:10.289422 <4>[ 23.776985] x14: ffffaf714edc34a8 x13: 0000000000000636 x12: 0000000000000212
11027 22:14:10.296581 <4>[ 23.784371] x11: fffffffffffe9530 x10: fffffffffffe94f8 x9 : 00000000fffff212
11028 22:14:10.302898 <4>[ 23.791758] x8 : ffffaf714edc34a8 x7 : ffffaf714ee1b4a8 x6 : 00000000000018d8
11029 22:14:10.309201 <4>[ 23.799144] x5 : ffff12693ef51a18 x4 : 00000000fffff212 x3 : ffff62f7f084f000
11030 22:14:10.315709 <4>[ 23.806530] x2 : 0000000000000000 x1 : 0000000000000000 x0 : ffff126809fac9c0
11031 22:14:10.319551 <4>[ 23.813918] Call trace:
11032 22:14:10.325970 <4>[ 23.816613] get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11033 22:14:10.332289 <4>[ 23.822357] vb2_create_framevec+0x50/0xac [videobuf2_memops]
11034 22:14:10.339178 <4>[ 23.828363] vb2_vmalloc_get_userptr+0x60/0x1a0 [videobuf2_vmalloc]
11035 22:14:10.345910 <4>[ 23.834891] __prepare_userptr+0x280/0x410 [videobuf2_common]
11036 22:14:10.348826 <4>[ 23.840895] __buf_prepare+0x1a0/0x244 [videobuf2_common]
11037 22:14:10.355939 <4>[ 23.846551] vb2_core_qbuf+0x3c8/0x5e0 [videobuf2_common]
11038 22:14:10.359272 <4>[ 23.852207] vb2_qbuf+0x90/0xf0 [videobuf2_v4l2]
11039 22:14:10.365794 <4>[ 23.857102] uvc_queue_buffer+0x3c/0x60 [uvcvideo]
11040 22:14:10.369129 <4>[ 23.862167] uvc_ioctl_qbuf+0x2c/0x40 [uvcvideo]
11041 22:14:10.375595 <4>[ 23.867044] v4l_qbuf+0x48/0x60 [videodev]
11042 22:14:10.379160 <4>[ 23.871463] __video_do_ioctl+0x184/0x3d0 [videodev]
11043 22:14:10.385972 <4>[ 23.876708] video_usercopy+0x358/0x680 [videodev]
11044 22:14:10.389217 <4>[ 23.881778] video_ioctl2+0x18/0x30 [videodev]
11045 22:14:10.395856 <4>[ 23.886501] v4l2_ioctl+0x40/0x60 [videodev]
11046 22:14:10.399299 <4>[ 23.891050] __arm64_sys_ioctl+0xa8/0xf0
11047 22:14:10.402771 <4>[ 23.895231] invoke_syscall+0x48/0x114
11048 22:14:10.408959 <4>[ 23.899235] el0_svc_common.constprop.0+0x44/0xec
11049 22:14:10.412350 <4>[ 23.904191] do_el0_svc+0x2c/0xd0
11050 22:14:10.415356 <4>[ 23.907756] el0_svc+0x2c/0x84
11051 22:14:10.418623 <4>[ 23.911067] el0t_64_sync_handler+0xb8/0xc0
11052 22:14:10.422763 <4>[ 23.915502] el0t_64_sync+0x18c/0x190
11053 22:14:10.429264 <4>[ 23.919414] ---[ end trace 0000000000000000 ]---
11054 22:14:12.848310 v4l2-compliance 1.25.0-1, 64 bits, 64-bit time_t
11055 22:14:12.859019 v4l2-compliance SHA: 52926c1f2f03 2023-05-25 13:56:39
11056 22:14:12.866116
11057 22:14:12.879944 Compliance test for uvcvideo device /dev/video0:
11058 22:14:12.887417
11059 22:14:12.897673 Driver Info:
11060 22:14:12.908727 Driver name : uvcvideo
11061 22:14:12.922466 Card type : HD User Facing: HD User Facing
11062 22:14:12.933046 Bus info : usb-11200000.usb-1.4.1
11063 22:14:12.939335 Driver version : 6.1.31
11064 22:14:12.949995 Capabilities : 0x84a00001
11065 22:14:12.962807 Metadata Capture
11066 22:14:12.973732 Streaming
11067 22:14:12.983595 Extended Pix Format
11068 22:14:12.993347 Device Capabilities
11069 22:14:13.003533 Device Caps : 0x04200001
11070 22:14:13.017250 Streaming
11071 22:14:13.027892 Extended Pix Format
11072 22:14:13.038471 Media Driver Info:
11073 22:14:13.049101 Driver name : uvcvideo
11074 22:14:13.062473 Model : HD User Facing: HD User Facing
11075 22:14:13.070086 Serial : 200901010001
11076 22:14:13.082911 Bus info : usb-11200000.usb-1.4.1
11077 22:14:13.090341 Media version : 6.1.31
11078 22:14:13.103383 Hardware revision: 0x00009758 (38744)
11079 22:14:13.111141 Driver version : 6.1.31
11080 22:14:13.120826 Interface Info:
11081 22:14:13.135764 <LAVA_SIGNAL_TESTSET START Interface-Info>
11082 22:14:13.136331 ID : 0x03000002
11083 22:14:13.137038 Received signal: <TESTSET> START Interface-Info
11084 22:14:13.137453 Starting test_set Interface-Info
11085 22:14:13.146373 Type : V4L Video
11086 22:14:13.156935 Entity Info:
11087 22:14:13.163283 <LAVA_SIGNAL_TESTSET STOP>
11088 22:14:13.164107 Received signal: <TESTSET> STOP
11089 22:14:13.164514 Closing test_set Interface-Info
11090 22:14:13.172860 <LAVA_SIGNAL_TESTSET START Entity-Info>
11091 22:14:13.173697 Received signal: <TESTSET> START Entity-Info
11092 22:14:13.174099 Starting test_set Entity-Info
11093 22:14:13.175567 ID : 0x00000001 (1)
11094 22:14:13.185994 Name : HD User Facing: HD User Facing
11095 22:14:13.193956 Function : V4L2 I/O
11096 22:14:13.204016 Flags : default
11097 22:14:13.214269 Pad 0x01000007 : 0: Sink
11098 22:14:13.234503 Link 0x02000013: from remote pad 0x100000a of entity 'Realtek Extended Controls Unit' (Video Pixel Formatter): Data, Enabled, Immutable
11099 22:14:13.235072
11100 22:14:13.246003 Required ioctls:
11101 22:14:13.253301 <LAVA_SIGNAL_TESTSET STOP>
11102 22:14:13.254184 Received signal: <TESTSET> STOP
11103 22:14:13.254579 Closing test_set Entity-Info
11104 22:14:13.262227 <LAVA_SIGNAL_TESTSET START Required-ioctls>
11105 22:14:13.263060 Received signal: <TESTSET> START Required-ioctls
11106 22:14:13.263457 Starting test_set Required-ioctls
11107 22:14:13.265435 test MC information (see 'Media Driver Info' above): OK
11108 22:14:13.290516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MC-information-see-Media-Driver-Info-above RESULT=pass>
11109 22:14:13.291276 Received signal: <TESTCASE> TEST_CASE_ID=MC-information-see-Media-Driver-Info-above RESULT=pass
11111 22:14:13.293486 test VIDIOC_QUERYCAP: OK
11112 22:14:13.312860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11113 22:14:13.313643 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11115 22:14:13.315797 test invalid ioctls: OK
11116 22:14:13.337784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-ioctls RESULT=pass>
11117 22:14:13.338371
11118 22:14:13.339130 Received signal: <TESTCASE> TEST_CASE_ID=invalid-ioctls RESULT=pass
11120 22:14:13.348348 Allow for multiple opens:
11121 22:14:13.355761 <LAVA_SIGNAL_TESTSET STOP>
11122 22:14:13.356655 Received signal: <TESTSET> STOP
11123 22:14:13.357168 Closing test_set Required-ioctls
11124 22:14:13.364916 <LAVA_SIGNAL_TESTSET START Allow-for-multiple-opens>
11125 22:14:13.365750 Received signal: <TESTSET> START Allow-for-multiple-opens
11126 22:14:13.366212 Starting test_set Allow-for-multiple-opens
11127 22:14:13.368053 test second /dev/video0 open: OK
11128 22:14:13.389601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=second-/dev/video0-open RESULT=pass>
11129 22:14:13.390422 Received signal: <TESTCASE> TEST_CASE_ID=second-/dev/video0-open RESULT=pass
11131 22:14:13.392548 test VIDIOC_QUERYCAP: OK
11132 22:14:13.413812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11133 22:14:13.414591 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11135 22:14:13.417645 test VIDIOC_G/S_PRIORITY: OK
11136 22:14:13.437494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass>
11137 22:14:13.438294 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass
11139 22:14:13.441087 test for unlimited opens: OK
11140 22:14:13.461303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=for-unlimited-opens RESULT=pass>
11141 22:14:13.461874
11142 22:14:13.462513 Received signal: <TESTCASE> TEST_CASE_ID=for-unlimited-opens RESULT=pass
11144 22:14:13.472494 Debug ioctls:
11145 22:14:13.479981 <LAVA_SIGNAL_TESTSET STOP>
11146 22:14:13.480789 Received signal: <TESTSET> STOP
11147 22:14:13.481153 Closing test_set Allow-for-multiple-opens
11148 22:14:13.488795 <LAVA_SIGNAL_TESTSET START Debug-ioctls>
11149 22:14:13.489647 Received signal: <TESTSET> START Debug-ioctls
11150 22:14:13.490060 Starting test_set Debug-ioctls
11151 22:14:13.491768 test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
11152 22:14:13.513224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass>
11153 22:14:13.514081 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass
11155 22:14:13.519747 test VIDIOC_LOG_STATUS: OK (Not Supported)
11156 22:14:13.537950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass>
11157 22:14:13.538471
11158 22:14:13.539106 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass
11160 22:14:13.548028 Input ioctls:
11161 22:14:13.554598 <LAVA_SIGNAL_TESTSET STOP>
11162 22:14:13.555382 Received signal: <TESTSET> STOP
11163 22:14:13.555752 Closing test_set Debug-ioctls
11164 22:14:13.563314 <LAVA_SIGNAL_TESTSET START Input-ioctls>
11165 22:14:13.563986 Received signal: <TESTSET> START Input-ioctls
11166 22:14:13.564353 Starting test_set Input-ioctls
11167 22:14:13.566721 test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
11168 22:14:13.591789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass>
11169 22:14:13.592546 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass
11171 22:14:13.595503 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11172 22:14:13.614693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11173 22:14:13.615608 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11175 22:14:13.621328 test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
11176 22:14:13.639107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass>
11177 22:14:13.639953 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass
11179 22:14:13.645182 test VIDIOC_ENUMAUDIO: OK (Not Supported)
11180 22:14:13.664770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass>
11181 22:14:13.665637 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass
11183 22:14:13.668004 test VIDIOC_G/S/ENUMINPUT: OK
11184 22:14:13.689970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass>
11185 22:14:13.690805 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass
11187 22:14:13.693414 test VIDIOC_G/S_AUDIO: OK (Not Supported)
11188 22:14:13.714105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass>
11189 22:14:13.714940 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass
11191 22:14:13.717132 Inputs: 1 Audio Inputs: 0 Tuners: 0
11192 22:14:13.723926
11193 22:14:13.740699 test VIDIOC_G/S_MODULATOR: OK (Not Supported)
11194 22:14:13.762638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass>
11195 22:14:13.763493 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass
11197 22:14:13.769283 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11198 22:14:13.788475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11199 22:14:13.789314 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11201 22:14:13.791065 test VIDIOC_ENUMAUDOUT: OK (Not Supported)
11202 22:14:13.811605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass>
11203 22:14:13.812422 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass
11205 22:14:13.817930 test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
11206 22:14:13.837396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass>
11207 22:14:13.838239 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass
11209 22:14:13.843772 test VIDIOC_G/S_AUDOUT: OK (Not Supported)
11210 22:14:13.861570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass>
11211 22:14:13.862121
11212 22:14:13.862751 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass
11214 22:14:13.881239 test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
11215 22:14:13.904485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass>
11216 22:14:13.905319 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass
11218 22:14:13.910500 test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
11219 22:14:13.932801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass>
11220 22:14:13.933640 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass
11222 22:14:13.936487 test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
11223 22:14:13.953675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass>
11224 22:14:13.954495 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass
11226 22:14:13.957194 test VIDIOC_G/S_EDID: OK (Not Supported)
11227 22:14:13.977540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass>
11228 22:14:13.978109
11229 22:14:13.978744 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass
11231 22:14:13.988514 Control ioctls (Input 0):
11232 22:14:13.995187 <LAVA_SIGNAL_TESTSET STOP>
11233 22:14:13.996020 Received signal: <TESTSET> STOP
11234 22:14:13.996411 Closing test_set Input-ioctls
11235 22:14:14.004483 <LAVA_SIGNAL_TESTSET START Control-ioctls-Input-0>
11236 22:14:14.005321 Received signal: <TESTSET> START Control-ioctls-Input-0
11237 22:14:14.005746 Starting test_set Control-ioctls-Input-0
11238 22:14:14.006912 test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
11239 22:14:14.029879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass>
11240 22:14:14.030473 test VIDIOC_QUERYCTRL: OK
11241 22:14:14.031117 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass
11243 22:14:14.049885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass>
11244 22:14:14.050736 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass
11246 22:14:14.053384 test VIDIOC_G/S_CTRL: OK
11247 22:14:14.074050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass>
11248 22:14:14.074884 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass
11250 22:14:14.077657 test VIDIOC_G/S/TRY_EXT_CTRLS: OK
11251 22:14:14.098427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass>
11252 22:14:14.099252 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass
11254 22:14:14.104851 test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK
11255 22:14:14.125256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=pass>
11256 22:14:14.126141 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=pass
11258 22:14:14.128104 test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
11259 22:14:14.148172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass>
11260 22:14:14.149014 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass
11262 22:14:14.151075 Standard Controls: 16 Private Controls: 0
11263 22:14:14.158904
11264 22:14:14.168604 Format ioctls (Input 0):
11265 22:14:14.174779 <LAVA_SIGNAL_TESTSET STOP>
11266 22:14:14.175596 Received signal: <TESTSET> STOP
11267 22:14:14.175987 Closing test_set Control-ioctls-Input-0
11268 22:14:14.184130 <LAVA_SIGNAL_TESTSET START Format-ioctls-Input-0>
11269 22:14:14.184910 Received signal: <TESTSET> START Format-ioctls-Input-0
11270 22:14:14.185298 Starting test_set Format-ioctls-Input-0
11271 22:14:14.187723 test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
11272 22:14:14.212792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass>
11273 22:14:14.213663 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass
11275 22:14:14.215877 test VIDIOC_G/S_PARM: OK
11276 22:14:14.232868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass>
11277 22:14:14.233708 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass
11279 22:14:14.235304 test VIDIOC_G_FBUF: OK (Not Supported)
11280 22:14:14.255293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass>
11281 22:14:14.256137 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass
11283 22:14:14.258479 test VIDIOC_G_FMT: OK
11284 22:14:14.277868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass>
11285 22:14:14.278707 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass
11287 22:14:14.281335 test VIDIOC_TRY_FMT: OK
11288 22:14:14.301626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass>
11289 22:14:14.302496 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass
11291 22:14:14.308229 warn: ../utils/v4l2-compliance/v4l2-test-formats.cpp(1046): Could not set fmt2
11292 22:14:14.310915 test VIDIOC_S_FMT: OK
11293 22:14:14.334527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_FMT RESULT=pass>
11294 22:14:14.335357 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_FMT RESULT=pass
11296 22:14:14.338302 test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
11297 22:14:14.359306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass>
11298 22:14:14.360148 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass
11300 22:14:14.362460 test Cropping: OK (Not Supported)
11301 22:14:14.385161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Cropping RESULT=pass>
11302 22:14:14.386043 Received signal: <TESTCASE> TEST_CASE_ID=Cropping RESULT=pass
11304 22:14:14.388001 test Composing: OK (Not Supported)
11305 22:14:14.410048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Composing RESULT=pass>
11306 22:14:14.410863 Received signal: <TESTCASE> TEST_CASE_ID=Composing RESULT=pass
11308 22:14:14.413261 test Scaling: OK (Not Supported)
11309 22:14:14.436126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Scaling RESULT=pass>
11310 22:14:14.436693
11311 22:14:14.437323 Received signal: <TESTCASE> TEST_CASE_ID=Scaling RESULT=pass
11313 22:14:14.446065 Codec ioctls (Input 0):
11314 22:14:14.453671 <LAVA_SIGNAL_TESTSET STOP>
11315 22:14:14.454447 Received signal: <TESTSET> STOP
11316 22:14:14.454806 Closing test_set Format-ioctls-Input-0
11317 22:14:14.462633 <LAVA_SIGNAL_TESTSET START Codec-ioctls-Input-0>
11318 22:14:14.463486 Received signal: <TESTSET> START Codec-ioctls-Input-0
11319 22:14:14.463913 Starting test_set Codec-ioctls-Input-0
11320 22:14:14.465923 test VIDIOC_(TRY_)ENCODER_CMD: OK (Not Supported)
11321 22:14:14.488518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass>
11322 22:14:14.489352 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass
11324 22:14:14.494319 test VIDIOC_G_ENC_INDEX: OK (Not Supported)
11325 22:14:14.513545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass>
11326 22:14:14.514293 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass
11328 22:14:14.519801 test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
11329 22:14:14.537911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass>
11330 22:14:14.538432
11331 22:14:14.539027 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass
11333 22:14:14.547614 Buffer ioctls (Input 0):
11334 22:14:14.554570 <LAVA_SIGNAL_TESTSET STOP>
11335 22:14:14.555389 Received signal: <TESTSET> STOP
11336 22:14:14.555785 Closing test_set Codec-ioctls-Input-0
11337 22:14:14.563707 <LAVA_SIGNAL_TESTSET START Buffer-ioctls-Input-0>
11338 22:14:14.564413 Received signal: <TESTSET> START Buffer-ioctls-Input-0
11339 22:14:14.564779 Starting test_set Buffer-ioctls-Input-0
11340 22:14:14.566750 test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
11341 22:14:14.590200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass>
11342 22:14:14.590729 test VIDIOC_EXPBUF: OK
11343 22:14:14.591330 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass
11345 22:14:14.611138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass>
11346 22:14:14.611946 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass
11348 22:14:14.614286 test Requests: OK (Not Supported)
11349 22:14:14.633797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Requests RESULT=pass>
11350 22:14:14.634377
11351 22:14:14.635010 Received signal: <TESTCASE> TEST_CASE_ID=Requests RESULT=pass
11353 22:14:14.643514 Test input 0:
11354 22:14:14.653757
11355 22:14:14.663407 Streaming ioctls:
11356 22:14:14.670958 <LAVA_SIGNAL_TESTSET STOP>
11357 22:14:14.671793 Received signal: <TESTSET> STOP
11358 22:14:14.672186 Closing test_set Buffer-ioctls-Input-0
11359 22:14:14.680771 <LAVA_SIGNAL_TESTSET START Streaming-ioctls_Test-input-0>
11360 22:14:14.681634 Received signal: <TESTSET> START Streaming-ioctls_Test-input-0
11361 22:14:14.682047 Starting test_set Streaming-ioctls_Test-input-0
11362 22:14:14.683740 test read/write: OK (Not Supported)
11363 22:14:14.706267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=read/write RESULT=pass>
11364 22:14:14.707100 Received signal: <TESTCASE> TEST_CASE_ID=read/write RESULT=pass
11366 22:14:14.708821 test blocking wait: OK
11367 22:14:14.729466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blocking-wait RESULT=pass>
11368 22:14:14.730287 Received signal: <TESTCASE> TEST_CASE_ID=blocking-wait RESULT=pass
11370 22:14:14.739854 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1346): node->streamon(q.g_type()) != EINVAL
11371 22:14:14.740426 test MMAP (no poll): FAIL
11372 22:14:14.764533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-no-poll RESULT=fail>
11373 22:14:14.765355 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-no-poll RESULT=fail
11375 22:14:14.775009 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1346): node->streamon(q.g_type()) != EINVAL
11376 22:14:14.775577 test MMAP (select): FAIL
11377 22:14:14.801042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-select RESULT=fail>
11378 22:14:14.801915 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-select RESULT=fail
11380 22:14:14.810372 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1346): node->streamon(q.g_type()) != EINVAL
11381 22:14:14.810898 test MMAP (epoll): FAIL
11382 22:14:14.839717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-epoll RESULT=fail>
11383 22:14:14.840251
11384 22:14:14.840852 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-epoll RESULT=fail
11386 22:14:14.852805
11387 22:14:15.021356
11388 22:14:15.028274 test USERPTR (no poll): OK
11389 22:14:15.052929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-no-poll RESULT=pass>
11390 22:14:15.053443
11391 22:14:15.054079 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-no-poll RESULT=pass
11393 22:14:15.065241
11394 22:14:15.229195
11395 22:14:15.236171 test USERPTR (select): OK
11396 22:14:15.261343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-select RESULT=pass>
11397 22:14:15.262218 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-select RESULT=pass
11399 22:14:15.267377 test DMABUF: Cannot test, specify --expbuf-device
11400 22:14:15.271708
11401 22:14:15.289412 Total for uvcvideo device /dev/video0: 53, Succeeded: 50, Failed: 3, Warnings: 3
11402 22:14:15.292281 <LAVA_TEST_RUNNER EXIT>
11403 22:14:15.292983 ok: lava_test_shell seems to have completed
11404 22:14:15.293365 Marking unfinished test run as failed
11406 22:14:15.298124 Composing:
result: pass
set: Format-ioctls-Input-0
Cropping:
result: pass
set: Format-ioctls-Input-0
MC-information-see-Media-Driver-Info-above:
result: pass
set: Required-ioctls
MMAP-epoll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-no-poll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-select:
result: fail
set: Streaming-ioctls_Test-input-0
Requests:
result: pass
set: Buffer-ioctls-Input-0
Scaling:
result: pass
set: Format-ioctls-Input-0
USERPTR-no-poll:
result: pass
set: Streaming-ioctls_Test-input-0
USERPTR-select:
result: pass
set: Streaming-ioctls_Test-input-0
VIDIOC_DBG_G/S_REGISTER:
result: pass
set: Debug-ioctls
VIDIOC_DV_TIMINGS_CAP:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_STD:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDIO:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDOUT:
result: pass
set: Input-ioctls
VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS:
result: pass
set: Format-ioctls-Input-0
VIDIOC_EXPBUF:
result: pass
set: Buffer-ioctls-Input-0
VIDIOC_G/S/ENUMINPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/ENUMOUTPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/TRY_EXT_CTRLS:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_AUDIO:
result: pass
set: Input-ioctls
VIDIOC_G/S_AUDOUT:
result: pass
set: Input-ioctls
VIDIOC_G/S_CTRL:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_EDID:
result: pass
set: Input-ioctls
VIDIOC_G/S_FREQUENCY:
result: pass
set: Input-ioctls
VIDIOC_G/S_JPEGCOMP:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_MODULATOR:
result: pass
set: Input-ioctls
VIDIOC_G/S_PARM:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G/S_PRIORITY:
result: pass
set: Allow-for-multiple-opens
VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS:
result: pass
set: Input-ioctls
VIDIOC_G_ENC_INDEX:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_G_FBUF:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G_SLICED_VBI_CAP:
result: pass
set: Format-ioctls-Input-0
VIDIOC_LOG_STATUS:
result: pass
set: Debug-ioctls
VIDIOC_QUERYCAP:
result: pass
set: Allow-for-multiple-opens
VIDIOC_QUERYCTRL:
result: pass
set: Control-ioctls-Input-0
VIDIOC_QUERY_EXT_CTRL/QUERYMENU:
result: pass
set: Control-ioctls-Input-0
VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF:
result: pass
set: Buffer-ioctls-Input-0
VIDIOC_S_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_S_HW_FREQ_SEEK:
result: pass
set: Input-ioctls
VIDIOC_TRY_DECODER_CMD:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_TRY_ENCODER_CMD:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_TRY_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT:
result: pass
set: Control-ioctls-Input-0
blocking-wait:
result: pass
set: Streaming-ioctls_Test-input-0
device-presence: pass
for-unlimited-opens:
result: pass
set: Allow-for-multiple-opens
invalid-ioctls:
result: pass
set: Required-ioctls
read/write:
result: pass
set: Streaming-ioctls_Test-input-0
second-/dev/video0-open:
result: pass
set: Allow-for-multiple-opens
11407 22:14:15.298718 end: 3.1 lava-test-shell (duration 00:00:10) [common]
11408 22:14:15.299131 end: 3 lava-test-retry (duration 00:00:10) [common]
11409 22:14:15.299560 start: 4 finalize (timeout 00:08:02) [common]
11410 22:14:15.299998 start: 4.1 power-off (timeout 00:00:30) [common]
11411 22:14:15.300733 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=off'
11412 22:14:15.378817 >> Command sent successfully.
11413 22:14:15.382683 Returned 0 in 0 seconds
11414 22:14:15.483601 end: 4.1 power-off (duration 00:00:00) [common]
11416 22:14:15.485050 start: 4.2 read-feedback (timeout 00:08:02) [common]
11417 22:14:15.486249 Listened to connection for namespace 'common' for up to 1s
11418 22:14:16.486890 Finalising connection for namespace 'common'
11419 22:14:16.487558 Disconnecting from shell: Finalise
11420 22:14:16.487946 / #
11421 22:14:16.588950 end: 4.2 read-feedback (duration 00:00:01) [common]
11422 22:14:16.589888 end: 4 finalize (duration 00:00:01) [common]
11423 22:14:16.590448 Cleaning after the job
11424 22:14:16.590929 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10583861/tftp-deploy-vhgxdhl0/ramdisk
11425 22:14:16.610157 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10583861/tftp-deploy-vhgxdhl0/kernel
11426 22:14:16.630445 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10583861/tftp-deploy-vhgxdhl0/dtb
11427 22:14:16.630894 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10583861/tftp-deploy-vhgxdhl0/modules
11428 22:14:16.640523 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10583861
11429 22:14:16.698907 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10583861
11430 22:14:16.699080 Job finished correctly