Boot log: mt8192-asurada-spherion-r0
- Errors: 2
- Kernel Errors: 37
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 30
1 22:11:48.252275 lava-dispatcher, installed at version: 2023.03
2 22:11:48.252481 start: 0 validate
3 22:11:48.252615 Start time: 2023-06-04 22:11:48.252608+00:00 (UTC)
4 22:11:48.252736 Using caching service: 'http://localhost/cache/?uri=%s'
5 22:11:48.252863 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230527.0%2Farm64%2Finitrd.cpio.gz exists
6 22:11:48.547966 Using caching service: 'http://localhost/cache/?uri=%s'
7 22:11:48.548844 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1281-g84d5372e0f314%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 22:12:14.060968 Using caching service: 'http://localhost/cache/?uri=%s'
9 22:12:14.061428 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1281-g84d5372e0f314%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 22:12:14.356187 Using caching service: 'http://localhost/cache/?uri=%s'
11 22:12:14.356887 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230527.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 22:12:14.931971 Using caching service: 'http://localhost/cache/?uri=%s'
13 22:12:14.932663 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1281-g84d5372e0f314%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 22:12:16.946250 validate duration: 28.69
16 22:12:16.946500 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 22:12:16.946598 start: 1.1 download-retry (timeout 00:10:00) [common]
18 22:12:16.946683 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 22:12:16.946796 Not decompressing ramdisk as can be used compressed.
20 22:12:16.946878 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230527.0/arm64/initrd.cpio.gz
21 22:12:16.946939 saving as /var/lib/lava/dispatcher/tmp/10583854/tftp-deploy-86gyr5tv/ramdisk/initrd.cpio.gz
22 22:12:16.946996 total size: 4665395 (4MB)
23 22:12:17.227815 progress 0% (0MB)
24 22:12:17.229229 progress 5% (0MB)
25 22:12:17.230455 progress 10% (0MB)
26 22:12:17.231705 progress 15% (0MB)
27 22:12:17.232909 progress 20% (0MB)
28 22:12:17.234117 progress 25% (1MB)
29 22:12:17.235306 progress 30% (1MB)
30 22:12:17.236533 progress 35% (1MB)
31 22:12:17.237717 progress 40% (1MB)
32 22:12:17.239056 progress 45% (2MB)
33 22:12:17.240278 progress 50% (2MB)
34 22:12:17.241466 progress 55% (2MB)
35 22:12:17.242655 progress 60% (2MB)
36 22:12:17.243879 progress 65% (2MB)
37 22:12:17.245063 progress 70% (3MB)
38 22:12:17.246242 progress 75% (3MB)
39 22:12:17.247424 progress 80% (3MB)
40 22:12:17.248771 progress 85% (3MB)
41 22:12:17.249953 progress 90% (4MB)
42 22:12:17.251137 progress 95% (4MB)
43 22:12:17.252385 progress 100% (4MB)
44 22:12:17.252540 4MB downloaded in 0.31s (14.56MB/s)
45 22:12:17.252688 end: 1.1.1 http-download (duration 00:00:00) [common]
47 22:12:17.252926 end: 1.1 download-retry (duration 00:00:00) [common]
48 22:12:17.253013 start: 1.2 download-retry (timeout 00:10:00) [common]
49 22:12:17.253097 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 22:12:17.253212 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1281-g84d5372e0f314/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 22:12:17.253282 saving as /var/lib/lava/dispatcher/tmp/10583854/tftp-deploy-86gyr5tv/kernel/Image
52 22:12:17.253342 total size: 45746688 (43MB)
53 22:12:17.253401 No compression specified
54 22:12:17.254451 progress 0% (0MB)
55 22:12:17.265967 progress 5% (2MB)
56 22:12:17.277492 progress 10% (4MB)
57 22:12:17.288978 progress 15% (6MB)
58 22:12:17.300400 progress 20% (8MB)
59 22:12:17.312103 progress 25% (10MB)
60 22:12:17.323362 progress 30% (13MB)
61 22:12:17.334865 progress 35% (15MB)
62 22:12:17.346310 progress 40% (17MB)
63 22:12:17.357746 progress 45% (19MB)
64 22:12:17.369390 progress 50% (21MB)
65 22:12:17.380936 progress 55% (24MB)
66 22:12:17.392444 progress 60% (26MB)
67 22:12:17.404126 progress 65% (28MB)
68 22:12:17.415695 progress 70% (30MB)
69 22:12:17.427209 progress 75% (32MB)
70 22:12:17.438490 progress 80% (34MB)
71 22:12:17.449897 progress 85% (37MB)
72 22:12:17.461423 progress 90% (39MB)
73 22:12:17.472979 progress 95% (41MB)
74 22:12:17.484781 progress 100% (43MB)
75 22:12:17.484954 43MB downloaded in 0.23s (188.37MB/s)
76 22:12:17.485107 end: 1.2.1 http-download (duration 00:00:00) [common]
78 22:12:17.485346 end: 1.2 download-retry (duration 00:00:00) [common]
79 22:12:17.485433 start: 1.3 download-retry (timeout 00:09:59) [common]
80 22:12:17.485522 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 22:12:17.485727 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1281-g84d5372e0f314/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 22:12:17.485801 saving as /var/lib/lava/dispatcher/tmp/10583854/tftp-deploy-86gyr5tv/dtb/mt8192-asurada-spherion-r0.dtb
83 22:12:17.485877 total size: 46924 (0MB)
84 22:12:17.485937 No compression specified
85 22:12:17.487048 progress 69% (0MB)
86 22:12:17.487318 progress 100% (0MB)
87 22:12:17.487468 0MB downloaded in 0.00s (28.17MB/s)
88 22:12:17.487600 end: 1.3.1 http-download (duration 00:00:00) [common]
90 22:12:17.487894 end: 1.3 download-retry (duration 00:00:00) [common]
91 22:12:17.487978 start: 1.4 download-retry (timeout 00:09:59) [common]
92 22:12:17.488059 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 22:12:17.488172 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230527.0/arm64/full.rootfs.tar.xz
94 22:12:17.488239 saving as /var/lib/lava/dispatcher/tmp/10583854/tftp-deploy-86gyr5tv/nfsrootfs/full.rootfs.tar
95 22:12:17.488298 total size: 125267308 (119MB)
96 22:12:17.488371 Using unxz to decompress xz
97 22:12:17.491907 progress 0% (0MB)
98 22:12:17.812108 progress 5% (6MB)
99 22:12:18.141319 progress 10% (11MB)
100 22:12:18.465811 progress 15% (17MB)
101 22:12:18.658980 progress 20% (23MB)
102 22:12:18.841716 progress 25% (29MB)
103 22:12:19.200975 progress 30% (35MB)
104 22:12:19.563210 progress 35% (41MB)
105 22:12:19.941984 progress 40% (47MB)
106 22:12:20.319502 progress 45% (53MB)
107 22:12:20.695673 progress 50% (59MB)
108 22:12:21.043958 progress 55% (65MB)
109 22:12:21.403537 progress 60% (71MB)
110 22:12:21.745271 progress 65% (77MB)
111 22:12:22.118136 progress 70% (83MB)
112 22:12:22.497964 progress 75% (89MB)
113 22:12:22.915490 progress 80% (95MB)
114 22:12:23.332895 progress 85% (101MB)
115 22:12:23.573694 progress 90% (107MB)
116 22:12:23.911257 progress 95% (113MB)
117 22:12:24.280609 progress 100% (119MB)
118 22:12:24.286798 119MB downloaded in 6.80s (17.57MB/s)
119 22:12:24.287145 end: 1.4.1 http-download (duration 00:00:07) [common]
121 22:12:24.287416 end: 1.4 download-retry (duration 00:00:07) [common]
122 22:12:24.287506 start: 1.5 download-retry (timeout 00:09:53) [common]
123 22:12:24.287621 start: 1.5.1 http-download (timeout 00:09:53) [common]
124 22:12:24.287782 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1281-g84d5372e0f314/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 22:12:24.287852 saving as /var/lib/lava/dispatcher/tmp/10583854/tftp-deploy-86gyr5tv/modules/modules.tar
126 22:12:24.287911 total size: 8541948 (8MB)
127 22:12:24.287972 Using unxz to decompress xz
128 22:12:24.291867 progress 0% (0MB)
129 22:12:24.313755 progress 5% (0MB)
130 22:12:24.339426 progress 10% (0MB)
131 22:12:24.365182 progress 15% (1MB)
132 22:12:24.390744 progress 20% (1MB)
133 22:12:24.414395 progress 25% (2MB)
134 22:12:24.441470 progress 30% (2MB)
135 22:12:24.466735 progress 35% (2MB)
136 22:12:24.491424 progress 40% (3MB)
137 22:12:24.515648 progress 45% (3MB)
138 22:12:24.540909 progress 50% (4MB)
139 22:12:24.564665 progress 55% (4MB)
140 22:12:24.589321 progress 60% (4MB)
141 22:12:24.615071 progress 65% (5MB)
142 22:12:24.640323 progress 70% (5MB)
143 22:12:24.663832 progress 75% (6MB)
144 22:12:24.688129 progress 80% (6MB)
145 22:12:24.713218 progress 85% (6MB)
146 22:12:24.742575 progress 90% (7MB)
147 22:12:24.768082 progress 95% (7MB)
148 22:12:24.792273 progress 100% (8MB)
149 22:12:24.798098 8MB downloaded in 0.51s (15.97MB/s)
150 22:12:24.798453 end: 1.5.1 http-download (duration 00:00:01) [common]
152 22:12:24.798866 end: 1.5 download-retry (duration 00:00:01) [common]
153 22:12:24.798992 start: 1.6 prepare-tftp-overlay (timeout 00:09:52) [common]
154 22:12:24.799124 start: 1.6.1 extract-nfsrootfs (timeout 00:09:52) [common]
155 22:12:26.768492 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/10583854/extract-nfsrootfs-3sh0d8r1
156 22:12:26.768706 end: 1.6.1 extract-nfsrootfs (duration 00:00:02) [common]
157 22:12:26.768812 start: 1.6.2 lava-overlay (timeout 00:09:50) [common]
158 22:12:26.768987 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10583854/lava-overlay-liir9qan
159 22:12:26.769112 makedir: /var/lib/lava/dispatcher/tmp/10583854/lava-overlay-liir9qan/lava-10583854/bin
160 22:12:26.769209 makedir: /var/lib/lava/dispatcher/tmp/10583854/lava-overlay-liir9qan/lava-10583854/tests
161 22:12:26.769304 makedir: /var/lib/lava/dispatcher/tmp/10583854/lava-overlay-liir9qan/lava-10583854/results
162 22:12:26.769407 Creating /var/lib/lava/dispatcher/tmp/10583854/lava-overlay-liir9qan/lava-10583854/bin/lava-add-keys
163 22:12:26.769550 Creating /var/lib/lava/dispatcher/tmp/10583854/lava-overlay-liir9qan/lava-10583854/bin/lava-add-sources
164 22:12:26.769676 Creating /var/lib/lava/dispatcher/tmp/10583854/lava-overlay-liir9qan/lava-10583854/bin/lava-background-process-start
165 22:12:26.769801 Creating /var/lib/lava/dispatcher/tmp/10583854/lava-overlay-liir9qan/lava-10583854/bin/lava-background-process-stop
166 22:12:26.769923 Creating /var/lib/lava/dispatcher/tmp/10583854/lava-overlay-liir9qan/lava-10583854/bin/lava-common-functions
167 22:12:26.770044 Creating /var/lib/lava/dispatcher/tmp/10583854/lava-overlay-liir9qan/lava-10583854/bin/lava-echo-ipv4
168 22:12:26.770166 Creating /var/lib/lava/dispatcher/tmp/10583854/lava-overlay-liir9qan/lava-10583854/bin/lava-install-packages
169 22:12:26.770289 Creating /var/lib/lava/dispatcher/tmp/10583854/lava-overlay-liir9qan/lava-10583854/bin/lava-installed-packages
170 22:12:26.770415 Creating /var/lib/lava/dispatcher/tmp/10583854/lava-overlay-liir9qan/lava-10583854/bin/lava-os-build
171 22:12:26.770537 Creating /var/lib/lava/dispatcher/tmp/10583854/lava-overlay-liir9qan/lava-10583854/bin/lava-probe-channel
172 22:12:26.770659 Creating /var/lib/lava/dispatcher/tmp/10583854/lava-overlay-liir9qan/lava-10583854/bin/lava-probe-ip
173 22:12:26.770785 Creating /var/lib/lava/dispatcher/tmp/10583854/lava-overlay-liir9qan/lava-10583854/bin/lava-target-ip
174 22:12:26.770907 Creating /var/lib/lava/dispatcher/tmp/10583854/lava-overlay-liir9qan/lava-10583854/bin/lava-target-mac
175 22:12:26.771029 Creating /var/lib/lava/dispatcher/tmp/10583854/lava-overlay-liir9qan/lava-10583854/bin/lava-target-storage
176 22:12:26.771153 Creating /var/lib/lava/dispatcher/tmp/10583854/lava-overlay-liir9qan/lava-10583854/bin/lava-test-case
177 22:12:26.771277 Creating /var/lib/lava/dispatcher/tmp/10583854/lava-overlay-liir9qan/lava-10583854/bin/lava-test-event
178 22:12:26.771398 Creating /var/lib/lava/dispatcher/tmp/10583854/lava-overlay-liir9qan/lava-10583854/bin/lava-test-feedback
179 22:12:26.771519 Creating /var/lib/lava/dispatcher/tmp/10583854/lava-overlay-liir9qan/lava-10583854/bin/lava-test-raise
180 22:12:26.771863 Creating /var/lib/lava/dispatcher/tmp/10583854/lava-overlay-liir9qan/lava-10583854/bin/lava-test-reference
181 22:12:26.771990 Creating /var/lib/lava/dispatcher/tmp/10583854/lava-overlay-liir9qan/lava-10583854/bin/lava-test-runner
182 22:12:26.772113 Creating /var/lib/lava/dispatcher/tmp/10583854/lava-overlay-liir9qan/lava-10583854/bin/lava-test-set
183 22:12:26.772233 Creating /var/lib/lava/dispatcher/tmp/10583854/lava-overlay-liir9qan/lava-10583854/bin/lava-test-shell
184 22:12:26.772375 Updating /var/lib/lava/dispatcher/tmp/10583854/lava-overlay-liir9qan/lava-10583854/bin/lava-install-packages (oe)
185 22:12:26.772545 Updating /var/lib/lava/dispatcher/tmp/10583854/lava-overlay-liir9qan/lava-10583854/bin/lava-installed-packages (oe)
186 22:12:26.772672 Creating /var/lib/lava/dispatcher/tmp/10583854/lava-overlay-liir9qan/lava-10583854/environment
187 22:12:26.772771 LAVA metadata
188 22:12:26.772842 - LAVA_JOB_ID=10583854
189 22:12:26.772906 - LAVA_DISPATCHER_IP=192.168.201.1
190 22:12:26.773010 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:50) [common]
191 22:12:26.773077 skipped lava-vland-overlay
192 22:12:26.773152 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
193 22:12:26.773234 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:50) [common]
194 22:12:26.773346 skipped lava-multinode-overlay
195 22:12:26.773423 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
196 22:12:26.773503 start: 1.6.2.3 test-definition (timeout 00:09:50) [common]
197 22:12:26.773578 Loading test definitions
198 22:12:26.773672 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:50) [common]
199 22:12:26.773744 Using /lava-10583854 at stage 0
200 22:12:26.774038 uuid=10583854_1.6.2.3.1 testdef=None
201 22:12:26.774128 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
202 22:12:26.774216 start: 1.6.2.3.2 test-overlay (timeout 00:09:50) [common]
203 22:12:26.774706 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
205 22:12:26.774933 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:50) [common]
206 22:12:26.775552 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
208 22:12:26.775827 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:50) [common]
209 22:12:26.776435 runner path: /var/lib/lava/dispatcher/tmp/10583854/lava-overlay-liir9qan/lava-10583854/0/tests/0_dmesg test_uuid 10583854_1.6.2.3.1
210 22:12:26.776588 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
212 22:12:26.776814 start: 1.6.2.3.5 inline-repo-action (timeout 00:09:50) [common]
213 22:12:26.776887 Using /lava-10583854 at stage 1
214 22:12:26.777175 uuid=10583854_1.6.2.3.5 testdef=None
215 22:12:26.777264 end: 1.6.2.3.5 inline-repo-action (duration 00:00:00) [common]
216 22:12:26.777349 start: 1.6.2.3.6 test-overlay (timeout 00:09:50) [common]
217 22:12:26.777807 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
219 22:12:26.778023 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:50) [common]
220 22:12:26.778644 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
222 22:12:26.778874 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:50) [common]
223 22:12:26.779475 runner path: /var/lib/lava/dispatcher/tmp/10583854/lava-overlay-liir9qan/lava-10583854/1/tests/1_bootrr test_uuid 10583854_1.6.2.3.5
224 22:12:26.779704 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
226 22:12:26.779913 Creating lava-test-runner.conf files
227 22:12:26.779977 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10583854/lava-overlay-liir9qan/lava-10583854/0 for stage 0
228 22:12:26.780068 - 0_dmesg
229 22:12:26.780147 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10583854/lava-overlay-liir9qan/lava-10583854/1 for stage 1
230 22:12:26.780238 - 1_bootrr
231 22:12:26.780332 end: 1.6.2.3 test-definition (duration 00:00:00) [common]
232 22:12:26.780417 start: 1.6.2.4 compress-overlay (timeout 00:09:50) [common]
233 22:12:26.787540 end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
234 22:12:26.787850 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:50) [common]
235 22:12:26.787941 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
236 22:12:26.788029 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
237 22:12:26.788122 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:50) [common]
238 22:12:26.902229 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
239 22:12:26.902586 start: 1.6.4 extract-modules (timeout 00:09:50) [common]
240 22:12:26.902709 extracting modules file /var/lib/lava/dispatcher/tmp/10583854/tftp-deploy-86gyr5tv/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10583854/extract-nfsrootfs-3sh0d8r1
241 22:12:27.109397 extracting modules file /var/lib/lava/dispatcher/tmp/10583854/tftp-deploy-86gyr5tv/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10583854/extract-overlay-ramdisk-l0d39290/ramdisk
242 22:12:27.318841 end: 1.6.4 extract-modules (duration 00:00:00) [common]
243 22:12:27.319028 start: 1.6.5 apply-overlay-tftp (timeout 00:09:50) [common]
244 22:12:27.319135 [common] Applying overlay to NFS
245 22:12:27.319207 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10583854/compress-overlay-ydm2sv0g/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10583854/extract-nfsrootfs-3sh0d8r1
246 22:12:27.327716 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
247 22:12:27.327875 start: 1.6.6 configure-preseed-file (timeout 00:09:50) [common]
248 22:12:27.328007 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
249 22:12:27.328099 start: 1.6.7 compress-ramdisk (timeout 00:09:50) [common]
250 22:12:27.328182 Building ramdisk /var/lib/lava/dispatcher/tmp/10583854/extract-overlay-ramdisk-l0d39290/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10583854/extract-overlay-ramdisk-l0d39290/ramdisk
251 22:12:27.636113 >> 117799 blocks
252 22:12:29.532106 rename /var/lib/lava/dispatcher/tmp/10583854/extract-overlay-ramdisk-l0d39290/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10583854/tftp-deploy-86gyr5tv/ramdisk/ramdisk.cpio.gz
253 22:12:29.532540 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
254 22:12:29.532666 start: 1.6.8 prepare-kernel (timeout 00:09:47) [common]
255 22:12:29.532769 start: 1.6.8.1 prepare-fit (timeout 00:09:47) [common]
256 22:12:29.532873 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10583854/tftp-deploy-86gyr5tv/kernel/Image'
257 22:12:41.678350 Returned 0 in 12 seconds
258 22:12:41.779305 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10583854/tftp-deploy-86gyr5tv/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10583854/tftp-deploy-86gyr5tv/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10583854/tftp-deploy-86gyr5tv/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10583854/tftp-deploy-86gyr5tv/kernel/image.itb
259 22:12:42.177282 output: FIT description: Kernel Image image with one or more FDT blobs
260 22:12:42.177647 output: Created: Sun Jun 4 23:12:42 2023
261 22:12:42.177725 output: Image 0 (kernel-1)
262 22:12:42.177795 output: Description:
263 22:12:42.177858 output: Created: Sun Jun 4 23:12:42 2023
264 22:12:42.177922 output: Type: Kernel Image
265 22:12:42.177982 output: Compression: lzma compressed
266 22:12:42.178043 output: Data Size: 10081729 Bytes = 9845.44 KiB = 9.61 MiB
267 22:12:42.178105 output: Architecture: AArch64
268 22:12:42.178165 output: OS: Linux
269 22:12:42.178227 output: Load Address: 0x00000000
270 22:12:42.178288 output: Entry Point: 0x00000000
271 22:12:42.178349 output: Hash algo: crc32
272 22:12:42.178408 output: Hash value: 3b3111d8
273 22:12:42.178464 output: Image 1 (fdt-1)
274 22:12:42.178518 output: Description: mt8192-asurada-spherion-r0
275 22:12:42.178572 output: Created: Sun Jun 4 23:12:42 2023
276 22:12:42.178626 output: Type: Flat Device Tree
277 22:12:42.178681 output: Compression: uncompressed
278 22:12:42.178735 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
279 22:12:42.178789 output: Architecture: AArch64
280 22:12:42.178844 output: Hash algo: crc32
281 22:12:42.178898 output: Hash value: 1df858fa
282 22:12:42.178951 output: Image 2 (ramdisk-1)
283 22:12:42.179007 output: Description: unavailable
284 22:12:42.179069 output: Created: Sun Jun 4 23:12:42 2023
285 22:12:42.179152 output: Type: RAMDisk Image
286 22:12:42.179258 output: Compression: Unknown Compression
287 22:12:42.179367 output: Data Size: 17643592 Bytes = 17230.07 KiB = 16.83 MiB
288 22:12:42.179468 output: Architecture: AArch64
289 22:12:42.179575 output: OS: Linux
290 22:12:42.179721 output: Load Address: unavailable
291 22:12:42.179814 output: Entry Point: unavailable
292 22:12:42.179914 output: Hash algo: crc32
293 22:12:42.180011 output: Hash value: 5932c7ac
294 22:12:42.180108 output: Default Configuration: 'conf-1'
295 22:12:42.180207 output: Configuration 0 (conf-1)
296 22:12:42.180304 output: Description: mt8192-asurada-spherion-r0
297 22:12:42.180402 output: Kernel: kernel-1
298 22:12:42.180498 output: Init Ramdisk: ramdisk-1
299 22:12:42.180594 output: FDT: fdt-1
300 22:12:42.180692 output: Loadables: kernel-1
301 22:12:42.180787 output:
302 22:12:42.181058 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
303 22:12:42.181208 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
304 22:12:42.181350 end: 1.6 prepare-tftp-overlay (duration 00:00:17) [common]
305 22:12:42.181500 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:35) [common]
306 22:12:42.181620 No LXC device requested
307 22:12:42.181744 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
308 22:12:42.181880 start: 1.8 deploy-device-env (timeout 00:09:35) [common]
309 22:12:42.182009 end: 1.8 deploy-device-env (duration 00:00:00) [common]
310 22:12:42.182110 Checking files for TFTP limit of 4294967296 bytes.
311 22:12:42.182832 end: 1 tftp-deploy (duration 00:00:25) [common]
312 22:12:42.182984 start: 2 depthcharge-action (timeout 00:05:00) [common]
313 22:12:42.183124 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
314 22:12:42.183312 substitutions:
315 22:12:42.183418 - {DTB}: 10583854/tftp-deploy-86gyr5tv/dtb/mt8192-asurada-spherion-r0.dtb
316 22:12:42.183527 - {INITRD}: 10583854/tftp-deploy-86gyr5tv/ramdisk/ramdisk.cpio.gz
317 22:12:42.183663 - {KERNEL}: 10583854/tftp-deploy-86gyr5tv/kernel/Image
318 22:12:42.183763 - {LAVA_MAC}: None
319 22:12:42.183859 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/10583854/extract-nfsrootfs-3sh0d8r1
320 22:12:42.183954 - {NFS_SERVER_IP}: 192.168.201.1
321 22:12:42.184072 - {PRESEED_CONFIG}: None
322 22:12:42.184177 - {PRESEED_LOCAL}: None
323 22:12:42.184282 - {RAMDISK}: 10583854/tftp-deploy-86gyr5tv/ramdisk/ramdisk.cpio.gz
324 22:12:42.184377 - {ROOT_PART}: None
325 22:12:42.184484 - {ROOT}: None
326 22:12:42.184586 - {SERVER_IP}: 192.168.201.1
327 22:12:42.184680 - {TEE}: None
328 22:12:42.184783 Parsed boot commands:
329 22:12:42.184881 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
330 22:12:42.185145 Parsed boot commands: tftpboot 192.168.201.1 10583854/tftp-deploy-86gyr5tv/kernel/image.itb 10583854/tftp-deploy-86gyr5tv/kernel/cmdline
331 22:12:42.185282 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
332 22:12:42.185435 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
333 22:12:42.185590 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
334 22:12:42.185745 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
335 22:12:42.185870 Not connected, no need to disconnect.
336 22:12:42.186005 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
337 22:12:42.186143 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
338 22:12:42.186262 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-8'
339 22:12:42.190352 Setting prompt string to ['lava-test: # ']
340 22:12:42.190788 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
341 22:12:42.190906 end: 2.2.1 reset-connection (duration 00:00:00) [common]
342 22:12:42.191009 start: 2.2.2 reset-device (timeout 00:05:00) [common]
343 22:12:42.191101 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
344 22:12:42.191296 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=reboot'
345 22:12:47.328507 >> Command sent successfully.
346 22:12:47.330913 Returned 0 in 5 seconds
347 22:12:47.431325 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
349 22:12:47.431681 end: 2.2.2 reset-device (duration 00:00:05) [common]
350 22:12:47.431791 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
351 22:12:47.431894 Setting prompt string to 'Starting depthcharge on Spherion...'
352 22:12:47.431966 Changing prompt to 'Starting depthcharge on Spherion...'
353 22:12:47.432037 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
354 22:12:47.432319 [Enter `^Ec?' for help]
355 22:12:47.604180
356 22:12:47.604334
357 22:12:47.604405 F0: 102B 0000
358 22:12:47.604469
359 22:12:47.604529 F3: 1001 0000 [0200]
360 22:12:47.604589
361 22:12:47.607616 F3: 1001 0000
362 22:12:47.607700
363 22:12:47.607767 F7: 102D 0000
364 22:12:47.607830
365 22:12:47.611668 F1: 0000 0000
366 22:12:47.611761
367 22:12:47.611828 V0: 0000 0000 [0001]
368 22:12:47.611893
369 22:12:47.611953 00: 0007 8000
370 22:12:47.612015
371 22:12:47.615022 01: 0000 0000
372 22:12:47.615108
373 22:12:47.615174 BP: 0C00 0209 [0000]
374 22:12:47.615237
375 22:12:47.618938 G0: 1182 0000
376 22:12:47.619021
377 22:12:47.619087 EC: 0000 0021 [4000]
378 22:12:47.619149
379 22:12:47.622411 S7: 0000 0000 [0000]
380 22:12:47.622520
381 22:12:47.622631 CC: 0000 0000 [0001]
382 22:12:47.622694
383 22:12:47.626117 T0: 0000 0040 [010F]
384 22:12:47.626256
385 22:12:47.626337 Jump to BL
386 22:12:47.626415
387 22:12:47.650436
388 22:12:47.650560
389 22:12:47.650657
390 22:12:47.657870 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
391 22:12:47.661064 ARM64: Exception handlers installed.
392 22:12:47.664827 ARM64: Testing exception
393 22:12:47.668247 ARM64: Done test exception
394 22:12:47.675532 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
395 22:12:47.686284 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
396 22:12:47.693117 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
397 22:12:47.702836 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
398 22:12:47.709411 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
399 22:12:47.716217 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
400 22:12:47.727939 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
401 22:12:47.734770 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
402 22:12:47.754152 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
403 22:12:47.757386 WDT: Last reset was cold boot
404 22:12:47.760345 SPI1(PAD0) initialized at 2873684 Hz
405 22:12:47.764033 SPI5(PAD0) initialized at 992727 Hz
406 22:12:47.767075 VBOOT: Loading verstage.
407 22:12:47.773764 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
408 22:12:47.777504 FMAP: Found "FLASH" version 1.1 at 0x20000.
409 22:12:47.780586 FMAP: base = 0x0 size = 0x800000 #areas = 25
410 22:12:47.783681 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
411 22:12:47.790882 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
412 22:12:47.797716 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
413 22:12:47.808693 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
414 22:12:47.808815
415 22:12:47.808917
416 22:12:47.818614 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
417 22:12:47.822013 ARM64: Exception handlers installed.
418 22:12:47.825376 ARM64: Testing exception
419 22:12:47.828630 ARM64: Done test exception
420 22:12:47.832996 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
421 22:12:47.836035 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 22:12:47.849894 Probing TPM: . done!
423 22:12:47.849979 TPM ready after 0 ms
424 22:12:47.856792 Connected to device vid:did:rid of 1ae0:0028:00
425 22:12:47.863634 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
426 22:12:47.905647 Initialized TPM device CR50 revision 0
427 22:12:47.917523 tlcl_send_startup: Startup return code is 0
428 22:12:47.917621 TPM: setup succeeded
429 22:12:47.928876 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
430 22:12:47.937845 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
431 22:12:47.949869 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
432 22:12:47.960498 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
433 22:12:47.964177 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
434 22:12:47.967092 in-header: 03 07 00 00 08 00 00 00
435 22:12:47.970837 in-data: aa e4 47 04 13 02 00 00
436 22:12:47.970924 Chrome EC: UHEPI supported
437 22:12:47.977673 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
438 22:12:47.985484 in-header: 03 9d 00 00 08 00 00 00
439 22:12:47.985571 in-data: 10 20 20 08 00 00 00 00
440 22:12:47.989161 Phase 1
441 22:12:47.993392 FMAP: area GBB found @ 3f5000 (12032 bytes)
442 22:12:47.996771 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
443 22:12:48.004154 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
444 22:12:48.007504 Recovery requested (1009000e)
445 22:12:48.013717 TPM: Extending digest for VBOOT: boot mode into PCR 0
446 22:12:48.018796 tlcl_extend: response is 0
447 22:12:48.027108 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
448 22:12:48.032278 tlcl_extend: response is 0
449 22:12:48.038936 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
450 22:12:48.060205 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
451 22:12:48.067162 BS: bootblock times (exec / console): total (unknown) / 148 ms
452 22:12:48.067278
453 22:12:48.067376
454 22:12:48.074849 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
455 22:12:48.078718 ARM64: Exception handlers installed.
456 22:12:48.081940 ARM64: Testing exception
457 22:12:48.085570 ARM64: Done test exception
458 22:12:48.105292 pmic_efuse_setting: Set efuses in 11 msecs
459 22:12:48.108831 pmwrap_interface_init: Select PMIF_VLD_RDY
460 22:12:48.112789 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
461 22:12:48.120223 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
462 22:12:48.123689 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
463 22:12:48.127353 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
464 22:12:48.134592 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
465 22:12:48.138333 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
466 22:12:48.141964 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
467 22:12:48.149311 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
468 22:12:48.152279 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
469 22:12:48.155851 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
470 22:12:48.162459 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
471 22:12:48.165545 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
472 22:12:48.172332 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
473 22:12:48.178903 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
474 22:12:48.181950 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
475 22:12:48.188497 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
476 22:12:48.195197 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
477 22:12:48.198678 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
478 22:12:48.205517 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
479 22:12:48.213649 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
480 22:12:48.216778 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
481 22:12:48.223660 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
482 22:12:48.227088 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
483 22:12:48.233873 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
484 22:12:48.237642 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
485 22:12:48.244050 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
486 22:12:48.250807 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
487 22:12:48.254211 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
488 22:12:48.257751 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
489 22:12:48.264581 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
490 22:12:48.268518 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
491 22:12:48.275380 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
492 22:12:48.279003 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
493 22:12:48.282531 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
494 22:12:48.290143 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
495 22:12:48.293691 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
496 22:12:48.300401 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
497 22:12:48.303566 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
498 22:12:48.307477 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
499 22:12:48.313935 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
500 22:12:48.316713 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
501 22:12:48.321281 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
502 22:12:48.326878 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
503 22:12:48.330181 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
504 22:12:48.333834 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
505 22:12:48.340282 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
506 22:12:48.343699 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
507 22:12:48.347227 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
508 22:12:48.350438 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
509 22:12:48.357055 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
510 22:12:48.360054 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
511 22:12:48.366812 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
512 22:12:48.376925 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
513 22:12:48.380237 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
514 22:12:48.389804 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
515 22:12:48.396946 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
516 22:12:48.403600 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
517 22:12:48.406625 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
518 22:12:48.409608 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
519 22:12:48.417637 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x20
520 22:12:48.424281 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
521 22:12:48.427409 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
522 22:12:48.433927 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
523 22:12:48.441633 [RTC]rtc_get_frequency_meter,154: input=15, output=793
524 22:12:48.445049 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
525 22:12:48.451510 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
526 22:12:48.455113 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
527 22:12:48.458498 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
528 22:12:48.464835 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
529 22:12:48.464949 ADC[4]: Raw value=898150 ID=7
530 22:12:48.468723 ADC[3]: Raw value=213440 ID=1
531 22:12:48.472185 RAM Code: 0x71
532 22:12:48.475223 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
533 22:12:48.481656 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
534 22:12:48.488775 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
535 22:12:48.495603 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
536 22:12:48.498586 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
537 22:12:48.502281 in-header: 03 07 00 00 08 00 00 00
538 22:12:48.505259 in-data: aa e4 47 04 13 02 00 00
539 22:12:48.509758 Chrome EC: UHEPI supported
540 22:12:48.512598 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
541 22:12:48.520585 in-header: 03 d5 00 00 08 00 00 00
542 22:12:48.520667 in-data: 98 20 60 08 00 00 00 00
543 22:12:48.524095 MRC: failed to locate region type 0.
544 22:12:48.531477 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
545 22:12:48.534595 DRAM-K: Running full calibration
546 22:12:48.540880 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
547 22:12:48.540986 header.status = 0x0
548 22:12:48.544429 header.version = 0x6 (expected: 0x6)
549 22:12:48.547760 header.size = 0xd00 (expected: 0xd00)
550 22:12:48.551153 header.flags = 0x0
551 22:12:48.558150 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
552 22:12:48.574592 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
553 22:12:48.581330 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
554 22:12:48.584374 dram_init: ddr_geometry: 2
555 22:12:48.587666 [EMI] MDL number = 2
556 22:12:48.587771 [EMI] Get MDL freq = 0
557 22:12:48.591089 dram_init: ddr_type: 0
558 22:12:48.591189 is_discrete_lpddr4: 1
559 22:12:48.594894 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
560 22:12:48.594983
561 22:12:48.595072
562 22:12:48.598051 [Bian_co] ETT version 0.0.0.1
563 22:12:48.604471 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
564 22:12:48.604556
565 22:12:48.607887 dramc_set_vcore_voltage set vcore to 650000
566 22:12:48.607971 Read voltage for 800, 4
567 22:12:48.611438 Vio18 = 0
568 22:12:48.611522 Vcore = 650000
569 22:12:48.611654 Vdram = 0
570 22:12:48.614723 Vddq = 0
571 22:12:48.614802 Vmddr = 0
572 22:12:48.618846 dram_init: config_dvfs: 1
573 22:12:48.622742 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
574 22:12:48.625834 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
575 22:12:48.630008 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=9
576 22:12:48.633708 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=9
577 22:12:48.637370 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
578 22:12:48.641359 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
579 22:12:48.644775 MEM_TYPE=3, freq_sel=18
580 22:12:48.648446 sv_algorithm_assistance_LP4_1600
581 22:12:48.651875 ============ PULL DRAM RESETB DOWN ============
582 22:12:48.655780 ========== PULL DRAM RESETB DOWN end =========
583 22:12:48.659256 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
584 22:12:48.662652 ===================================
585 22:12:48.666303 LPDDR4 DRAM CONFIGURATION
586 22:12:48.669921 ===================================
587 22:12:48.670007 EX_ROW_EN[0] = 0x0
588 22:12:48.674054 EX_ROW_EN[1] = 0x0
589 22:12:48.674168 LP4Y_EN = 0x0
590 22:12:48.677502 WORK_FSP = 0x0
591 22:12:48.677589 WL = 0x2
592 22:12:48.681797 RL = 0x2
593 22:12:48.681947 BL = 0x2
594 22:12:48.685430 RPST = 0x0
595 22:12:48.685528 RD_PRE = 0x0
596 22:12:48.689283 WR_PRE = 0x1
597 22:12:48.689383 WR_PST = 0x0
598 22:12:48.692497 DBI_WR = 0x0
599 22:12:48.692573 DBI_RD = 0x0
600 22:12:48.692636 OTF = 0x1
601 22:12:48.696243 ===================================
602 22:12:48.699329 ===================================
603 22:12:48.702513 ANA top config
604 22:12:48.706396 ===================================
605 22:12:48.709726 DLL_ASYNC_EN = 0
606 22:12:48.709857 ALL_SLAVE_EN = 1
607 22:12:48.712940 NEW_RANK_MODE = 1
608 22:12:48.716496 DLL_IDLE_MODE = 1
609 22:12:48.719509 LP45_APHY_COMB_EN = 1
610 22:12:48.719600 TX_ODT_DIS = 1
611 22:12:48.722699 NEW_8X_MODE = 1
612 22:12:48.725764 ===================================
613 22:12:48.729266 ===================================
614 22:12:48.732932 data_rate = 1600
615 22:12:48.736020 CKR = 1
616 22:12:48.739118 DQ_P2S_RATIO = 8
617 22:12:48.742315 ===================================
618 22:12:48.745913 CA_P2S_RATIO = 8
619 22:12:48.745998 DQ_CA_OPEN = 0
620 22:12:48.749126 DQ_SEMI_OPEN = 0
621 22:12:48.752484 CA_SEMI_OPEN = 0
622 22:12:48.755841 CA_FULL_RATE = 0
623 22:12:48.759334 DQ_CKDIV4_EN = 1
624 22:12:48.762386 CA_CKDIV4_EN = 1
625 22:12:48.762472 CA_PREDIV_EN = 0
626 22:12:48.765857 PH8_DLY = 0
627 22:12:48.769118 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
628 22:12:48.772962 DQ_AAMCK_DIV = 4
629 22:12:48.775822 CA_AAMCK_DIV = 4
630 22:12:48.775902 CA_ADMCK_DIV = 4
631 22:12:48.779460 DQ_TRACK_CA_EN = 0
632 22:12:48.782402 CA_PICK = 800
633 22:12:48.785919 CA_MCKIO = 800
634 22:12:48.789523 MCKIO_SEMI = 0
635 22:12:48.792640 PLL_FREQ = 3068
636 22:12:48.795849 DQ_UI_PI_RATIO = 32
637 22:12:48.799707 CA_UI_PI_RATIO = 0
638 22:12:48.802304 ===================================
639 22:12:48.802384 ===================================
640 22:12:48.805667 memory_type:LPDDR4
641 22:12:48.809291 GP_NUM : 10
642 22:12:48.809370 SRAM_EN : 1
643 22:12:48.812044 MD32_EN : 0
644 22:12:48.815604 ===================================
645 22:12:48.818811 [ANA_INIT] >>>>>>>>>>>>>>
646 22:12:48.822231 <<<<<< [CONFIGURE PHASE]: ANA_TX
647 22:12:48.826014 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
648 22:12:48.828975 ===================================
649 22:12:48.829061 data_rate = 1600,PCW = 0X7600
650 22:12:48.832579 ===================================
651 22:12:48.839368 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
652 22:12:48.842644 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
653 22:12:48.848822 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
654 22:12:48.852325 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
655 22:12:48.855403 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
656 22:12:48.859286 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
657 22:12:48.862874 [ANA_INIT] flow start
658 22:12:48.862959 [ANA_INIT] PLL >>>>>>>>
659 22:12:48.866566 [ANA_INIT] PLL <<<<<<<<
660 22:12:48.869946 [ANA_INIT] MIDPI >>>>>>>>
661 22:12:48.870033 [ANA_INIT] MIDPI <<<<<<<<
662 22:12:48.873322 [ANA_INIT] DLL >>>>>>>>
663 22:12:48.876904 [ANA_INIT] flow end
664 22:12:48.880978 ============ LP4 DIFF to SE enter ============
665 22:12:48.884715 ============ LP4 DIFF to SE exit ============
666 22:12:48.884802 [ANA_INIT] <<<<<<<<<<<<<
667 22:12:48.887951 [Flow] Enable top DCM control >>>>>
668 22:12:48.892106 [Flow] Enable top DCM control <<<<<
669 22:12:48.895355 Enable DLL master slave shuffle
670 22:12:48.902363 ==============================================================
671 22:12:48.902450 Gating Mode config
672 22:12:48.909585 ==============================================================
673 22:12:48.909700 Config description:
674 22:12:48.919262 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
675 22:12:48.925916 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
676 22:12:48.932610 SELPH_MODE 0: By rank 1: By Phase
677 22:12:48.935758 ==============================================================
678 22:12:48.938655 GAT_TRACK_EN = 1
679 22:12:48.942331 RX_GATING_MODE = 2
680 22:12:48.945594 RX_GATING_TRACK_MODE = 2
681 22:12:48.948827 SELPH_MODE = 1
682 22:12:48.952237 PICG_EARLY_EN = 1
683 22:12:48.955470 VALID_LAT_VALUE = 1
684 22:12:48.958628 ==============================================================
685 22:12:48.965738 Enter into Gating configuration >>>>
686 22:12:48.965824 Exit from Gating configuration <<<<
687 22:12:48.968849 Enter into DVFS_PRE_config >>>>>
688 22:12:48.982349 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
689 22:12:48.985767 Exit from DVFS_PRE_config <<<<<
690 22:12:48.989376 Enter into PICG configuration >>>>
691 22:12:48.992141 Exit from PICG configuration <<<<
692 22:12:48.992233 [RX_INPUT] configuration >>>>>
693 22:12:48.995522 [RX_INPUT] configuration <<<<<
694 22:12:49.002265 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
695 22:12:49.005272 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
696 22:12:49.012096 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
697 22:12:49.018265 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
698 22:12:49.025482 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
699 22:12:49.031641 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
700 22:12:49.035206 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
701 22:12:49.038293 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
702 22:12:49.045086 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
703 22:12:49.048281 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
704 22:12:49.051402 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
705 22:12:49.055640 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
706 22:12:49.058909 ===================================
707 22:12:49.062448 LPDDR4 DRAM CONFIGURATION
708 22:12:49.066112 ===================================
709 22:12:49.066219 EX_ROW_EN[0] = 0x0
710 22:12:49.069558 EX_ROW_EN[1] = 0x0
711 22:12:49.069666 LP4Y_EN = 0x0
712 22:12:49.072971 WORK_FSP = 0x0
713 22:12:49.073058 WL = 0x2
714 22:12:49.076585 RL = 0x2
715 22:12:49.076668 BL = 0x2
716 22:12:49.080399 RPST = 0x0
717 22:12:49.080509 RD_PRE = 0x0
718 22:12:49.084275 WR_PRE = 0x1
719 22:12:49.084383 WR_PST = 0x0
720 22:12:49.087494 DBI_WR = 0x0
721 22:12:49.087608 DBI_RD = 0x0
722 22:12:49.091522 OTF = 0x1
723 22:12:49.094922 ===================================
724 22:12:49.098576 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
725 22:12:49.102271 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
726 22:12:49.105532 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 22:12:49.109154 ===================================
728 22:12:49.112726 LPDDR4 DRAM CONFIGURATION
729 22:12:49.116715 ===================================
730 22:12:49.116803 EX_ROW_EN[0] = 0x10
731 22:12:49.120143 EX_ROW_EN[1] = 0x0
732 22:12:49.120230 LP4Y_EN = 0x0
733 22:12:49.123855 WORK_FSP = 0x0
734 22:12:49.123943 WL = 0x2
735 22:12:49.127542 RL = 0x2
736 22:12:49.127674 BL = 0x2
737 22:12:49.131130 RPST = 0x0
738 22:12:49.131244 RD_PRE = 0x0
739 22:12:49.131349 WR_PRE = 0x1
740 22:12:49.134890 WR_PST = 0x0
741 22:12:49.134975 DBI_WR = 0x0
742 22:12:49.138650 DBI_RD = 0x0
743 22:12:49.138739 OTF = 0x1
744 22:12:49.142412 ===================================
745 22:12:49.149191 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
746 22:12:49.152839 nWR fixed to 40
747 22:12:49.156653 [ModeRegInit_LP4] CH0 RK0
748 22:12:49.156739 [ModeRegInit_LP4] CH0 RK1
749 22:12:49.160279 [ModeRegInit_LP4] CH1 RK0
750 22:12:49.160367 [ModeRegInit_LP4] CH1 RK1
751 22:12:49.164043 match AC timing 13
752 22:12:49.167488 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
753 22:12:49.171899 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
754 22:12:49.175286 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
755 22:12:49.182574 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
756 22:12:49.186594 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
757 22:12:49.186683 [EMI DOE] emi_dcm 0
758 22:12:49.193548 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
759 22:12:49.193635 ==
760 22:12:49.197633 Dram Type= 6, Freq= 0, CH_0, rank 0
761 22:12:49.200868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
762 22:12:49.200950 ==
763 22:12:49.204654 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
764 22:12:49.211822 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
765 22:12:49.220405 [CA 0] Center 38 (7~69) winsize 63
766 22:12:49.223716 [CA 1] Center 37 (7~68) winsize 62
767 22:12:49.227243 [CA 2] Center 35 (5~66) winsize 62
768 22:12:49.230078 [CA 3] Center 35 (5~66) winsize 62
769 22:12:49.234003 [CA 4] Center 34 (4~65) winsize 62
770 22:12:49.237382 [CA 5] Center 33 (3~64) winsize 62
771 22:12:49.237474
772 22:12:49.241007 [CmdBusTrainingLP45] Vref(ca) range 1: 34
773 22:12:49.241095
774 22:12:49.244809 [CATrainingPosCal] consider 1 rank data
775 22:12:49.249093 u2DelayCellTimex100 = 270/100 ps
776 22:12:49.252405 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
777 22:12:49.256046 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
778 22:12:49.259879 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
779 22:12:49.263419 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
780 22:12:49.267864 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
781 22:12:49.270939 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
782 22:12:49.271026
783 22:12:49.274443 CA PerBit enable=1, Macro0, CA PI delay=33
784 22:12:49.274529
785 22:12:49.278240 [CBTSetCACLKResult] CA Dly = 33
786 22:12:49.278343 CS Dly: 5 (0~36)
787 22:12:49.278411 ==
788 22:12:49.281963 Dram Type= 6, Freq= 0, CH_0, rank 1
789 22:12:49.285503 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
790 22:12:49.285589 ==
791 22:12:49.292657 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
792 22:12:49.296206 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
793 22:12:49.307201 [CA 0] Center 38 (7~69) winsize 63
794 22:12:49.311185 [CA 1] Center 38 (7~69) winsize 63
795 22:12:49.314793 [CA 2] Center 35 (5~66) winsize 62
796 22:12:49.318597 [CA 3] Center 35 (5~66) winsize 62
797 22:12:49.321819 [CA 4] Center 34 (4~65) winsize 62
798 22:12:49.325244 [CA 5] Center 34 (4~64) winsize 61
799 22:12:49.325329
800 22:12:49.328698 [CmdBusTrainingLP45] Vref(ca) range 1: 32
801 22:12:49.328783
802 22:12:49.332892 [CATrainingPosCal] consider 2 rank data
803 22:12:49.333012 u2DelayCellTimex100 = 270/100 ps
804 22:12:49.340022 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
805 22:12:49.343508 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
806 22:12:49.347166 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
807 22:12:49.350624 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
808 22:12:49.354339 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
809 22:12:49.357404 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
810 22:12:49.357489
811 22:12:49.361310 CA PerBit enable=1, Macro0, CA PI delay=34
812 22:12:49.361387
813 22:12:49.364231 [CBTSetCACLKResult] CA Dly = 34
814 22:12:49.364422 CS Dly: 5 (0~37)
815 22:12:49.364551
816 22:12:49.367479 ----->DramcWriteLeveling(PI) begin...
817 22:12:49.367624 ==
818 22:12:49.370559 Dram Type= 6, Freq= 0, CH_0, rank 0
819 22:12:49.377131 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
820 22:12:49.377217 ==
821 22:12:49.380864 Write leveling (Byte 0): 32 => 32
822 22:12:49.380952 Write leveling (Byte 1): 32 => 32
823 22:12:49.383953 DramcWriteLeveling(PI) end<-----
824 22:12:49.384134
825 22:12:49.384216 ==
826 22:12:49.387062 Dram Type= 6, Freq= 0, CH_0, rank 0
827 22:12:49.394053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
828 22:12:49.394135 ==
829 22:12:49.397444 [Gating] SW mode calibration
830 22:12:49.404173 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
831 22:12:49.407165 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
832 22:12:49.413965 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
833 22:12:49.417397 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
834 22:12:49.420662 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
835 22:12:49.427410 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
836 22:12:49.430519 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
837 22:12:49.434123 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
838 22:12:49.440519 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
839 22:12:49.444238 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
840 22:12:49.448234 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
841 22:12:49.451615 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
842 22:12:49.455436 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
843 22:12:49.459286 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
844 22:12:49.466014 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
845 22:12:49.469105 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
846 22:12:49.472754 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
847 22:12:49.480069 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
848 22:12:49.483000 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
849 22:12:49.486190 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
850 22:12:49.492812 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
851 22:12:49.496510 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
852 22:12:49.499438 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
853 22:12:49.506441 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
854 22:12:49.509606 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 22:12:49.513034 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 22:12:49.519794 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 22:12:49.523193 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 22:12:49.526366 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 22:12:49.529410 0 9 12 | B1->B0 | 2929 3232 | 1 0 | (0 0) (0 0)
860 22:12:49.536266 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
861 22:12:49.539545 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
862 22:12:49.542866 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
863 22:12:49.549840 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
864 22:12:49.552716 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
865 22:12:49.556040 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
866 22:12:49.562491 0 10 8 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 1)
867 22:12:49.566035 0 10 12 | B1->B0 | 2e2e 2424 | 1 1 | (1 1) (1 0)
868 22:12:49.569060 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 22:12:49.575691 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 22:12:49.579426 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
871 22:12:49.582452 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
872 22:12:49.589126 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 22:12:49.592224 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 22:12:49.595945 0 11 8 | B1->B0 | 2424 2e2e | 0 0 | (0 0) (0 0)
875 22:12:49.602252 0 11 12 | B1->B0 | 3434 4242 | 1 0 | (0 0) (0 0)
876 22:12:49.605835 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
877 22:12:49.608760 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
878 22:12:49.615816 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
879 22:12:49.618803 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
880 22:12:49.621946 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
881 22:12:49.628663 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
882 22:12:49.632026 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
883 22:12:49.635818 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
884 22:12:49.642344 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
885 22:12:49.645573 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
886 22:12:49.648469 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
887 22:12:49.655635 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
888 22:12:49.658493 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
889 22:12:49.662168 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
890 22:12:49.668515 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
891 22:12:49.672078 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
892 22:12:49.675329 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
893 22:12:49.681757 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
894 22:12:49.685515 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
895 22:12:49.688247 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
896 22:12:49.695024 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
897 22:12:49.698584 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
898 22:12:49.701772 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
899 22:12:49.708163 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
900 22:12:49.711743 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 22:12:49.715465 Total UI for P1: 0, mck2ui 16
902 22:12:49.718600 best dqsien dly found for B0: ( 0, 14, 12)
903 22:12:49.721644 Total UI for P1: 0, mck2ui 16
904 22:12:49.725349 best dqsien dly found for B1: ( 0, 14, 12)
905 22:12:49.728659 best DQS0 dly(MCK, UI, PI) = (0, 14, 12)
906 22:12:49.732069 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
907 22:12:49.732144
908 22:12:49.735035 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 12)
909 22:12:49.738610 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
910 22:12:49.742151 [Gating] SW calibration Done
911 22:12:49.742251 ==
912 22:12:49.745021 Dram Type= 6, Freq= 0, CH_0, rank 0
913 22:12:49.748464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
914 22:12:49.748567 ==
915 22:12:49.751632 RX Vref Scan: 0
916 22:12:49.751706
917 22:12:49.754897 RX Vref 0 -> 0, step: 1
918 22:12:49.754993
919 22:12:49.755086 RX Delay -130 -> 252, step: 16
920 22:12:49.761622 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
921 22:12:49.765272 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
922 22:12:49.768234 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
923 22:12:49.771859 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
924 22:12:49.774790 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
925 22:12:49.781468 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
926 22:12:49.785063 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
927 22:12:49.788203 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
928 22:12:49.791623 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
929 22:12:49.794641 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
930 22:12:49.801446 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
931 22:12:49.804606 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
932 22:12:49.808156 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
933 22:12:49.811503 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
934 22:12:49.818287 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
935 22:12:49.821216 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
936 22:12:49.821300 ==
937 22:12:49.824784 Dram Type= 6, Freq= 0, CH_0, rank 0
938 22:12:49.828106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
939 22:12:49.828190 ==
940 22:12:49.828257 DQS Delay:
941 22:12:49.831116 DQS0 = 0, DQS1 = 0
942 22:12:49.831200 DQM Delay:
943 22:12:49.834844 DQM0 = 79, DQM1 = 70
944 22:12:49.834926 DQ Delay:
945 22:12:49.838199 DQ0 =77, DQ1 =77, DQ2 =77, DQ3 =77
946 22:12:49.841260 DQ4 =77, DQ5 =69, DQ6 =85, DQ7 =93
947 22:12:49.844946 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
948 22:12:49.848255 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
949 22:12:49.848358
950 22:12:49.848450
951 22:12:49.848547 ==
952 22:12:49.851389 Dram Type= 6, Freq= 0, CH_0, rank 0
953 22:12:49.855597 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
954 22:12:49.855711 ==
955 22:12:49.855776
956 22:12:49.855833
957 22:12:49.858643 TX Vref Scan disable
958 22:12:49.862096 == TX Byte 0 ==
959 22:12:49.865562 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
960 22:12:49.868949 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
961 22:12:49.872082 == TX Byte 1 ==
962 22:12:49.875121 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
963 22:12:49.878552 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
964 22:12:49.878625 ==
965 22:12:49.881941 Dram Type= 6, Freq= 0, CH_0, rank 0
966 22:12:49.888713 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
967 22:12:49.888790 ==
968 22:12:49.900010 TX Vref=22, minBit 0, minWin=27, winSum=433
969 22:12:49.903041 TX Vref=24, minBit 5, minWin=26, winSum=433
970 22:12:49.906704 TX Vref=26, minBit 0, minWin=27, winSum=436
971 22:12:49.909741 TX Vref=28, minBit 9, minWin=27, winSum=444
972 22:12:49.913527 TX Vref=30, minBit 2, minWin=27, winSum=445
973 22:12:49.920046 TX Vref=32, minBit 12, minWin=26, winSum=438
974 22:12:49.923063 [TxChooseVref] Worse bit 2, Min win 27, Win sum 445, Final Vref 30
975 22:12:49.923138
976 22:12:49.926798 Final TX Range 1 Vref 30
977 22:12:49.926869
978 22:12:49.926932 ==
979 22:12:49.929495 Dram Type= 6, Freq= 0, CH_0, rank 0
980 22:12:49.933104 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
981 22:12:49.933175 ==
982 22:12:49.936763
983 22:12:49.936838
984 22:12:49.936904 TX Vref Scan disable
985 22:12:49.940270 == TX Byte 0 ==
986 22:12:49.943172 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
987 22:12:49.949728 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
988 22:12:49.949805 == TX Byte 1 ==
989 22:12:49.953188 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
990 22:12:49.959962 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
991 22:12:49.960040
992 22:12:49.960105 [DATLAT]
993 22:12:49.960169 Freq=800, CH0 RK0
994 22:12:49.960230
995 22:12:49.963077 DATLAT Default: 0xa
996 22:12:49.963146 0, 0xFFFF, sum = 0
997 22:12:49.966786 1, 0xFFFF, sum = 0
998 22:12:49.966866 2, 0xFFFF, sum = 0
999 22:12:49.969711 3, 0xFFFF, sum = 0
1000 22:12:49.969788 4, 0xFFFF, sum = 0
1001 22:12:49.972963 5, 0xFFFF, sum = 0
1002 22:12:49.976791 6, 0xFFFF, sum = 0
1003 22:12:49.976874 7, 0xFFFF, sum = 0
1004 22:12:49.979974 8, 0xFFFF, sum = 0
1005 22:12:49.980059 9, 0x0, sum = 1
1006 22:12:49.980127 10, 0x0, sum = 2
1007 22:12:49.983006 11, 0x0, sum = 3
1008 22:12:49.983080 12, 0x0, sum = 4
1009 22:12:49.986348 best_step = 10
1010 22:12:49.986421
1011 22:12:49.986483 ==
1012 22:12:49.989869 Dram Type= 6, Freq= 0, CH_0, rank 0
1013 22:12:49.993008 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1014 22:12:49.993084 ==
1015 22:12:49.996692 RX Vref Scan: 1
1016 22:12:49.996767
1017 22:12:49.996829 Set Vref Range= 32 -> 127
1018 22:12:49.999592
1019 22:12:49.999699 RX Vref 32 -> 127, step: 1
1020 22:12:49.999759
1021 22:12:50.003194 RX Delay -111 -> 252, step: 8
1022 22:12:50.003269
1023 22:12:50.006891 Set Vref, RX VrefLevel [Byte0]: 32
1024 22:12:50.009872 [Byte1]: 32
1025 22:12:50.009955
1026 22:12:50.012932 Set Vref, RX VrefLevel [Byte0]: 33
1027 22:12:50.016692 [Byte1]: 33
1028 22:12:50.020077
1029 22:12:50.020151 Set Vref, RX VrefLevel [Byte0]: 34
1030 22:12:50.023480 [Byte1]: 34
1031 22:12:50.028283
1032 22:12:50.028357 Set Vref, RX VrefLevel [Byte0]: 35
1033 22:12:50.031200 [Byte1]: 35
1034 22:12:50.035840
1035 22:12:50.035917 Set Vref, RX VrefLevel [Byte0]: 36
1036 22:12:50.039378 [Byte1]: 36
1037 22:12:50.043431
1038 22:12:50.043498 Set Vref, RX VrefLevel [Byte0]: 37
1039 22:12:50.046312 [Byte1]: 37
1040 22:12:50.050933
1041 22:12:50.051002 Set Vref, RX VrefLevel [Byte0]: 38
1042 22:12:50.054344 [Byte1]: 38
1043 22:12:50.058803
1044 22:12:50.058873 Set Vref, RX VrefLevel [Byte0]: 39
1045 22:12:50.061631 [Byte1]: 39
1046 22:12:50.066149
1047 22:12:50.066216 Set Vref, RX VrefLevel [Byte0]: 40
1048 22:12:50.069505 [Byte1]: 40
1049 22:12:50.074069
1050 22:12:50.074147 Set Vref, RX VrefLevel [Byte0]: 41
1051 22:12:50.077268 [Byte1]: 41
1052 22:12:50.081556
1053 22:12:50.081631 Set Vref, RX VrefLevel [Byte0]: 42
1054 22:12:50.084551 [Byte1]: 42
1055 22:12:50.088871
1056 22:12:50.088942 Set Vref, RX VrefLevel [Byte0]: 43
1057 22:12:50.092416 [Byte1]: 43
1058 22:12:50.096540
1059 22:12:50.096606 Set Vref, RX VrefLevel [Byte0]: 44
1060 22:12:50.100200 [Byte1]: 44
1061 22:12:50.105069
1062 22:12:50.105137 Set Vref, RX VrefLevel [Byte0]: 45
1063 22:12:50.108317 [Byte1]: 45
1064 22:12:50.112498
1065 22:12:50.112570 Set Vref, RX VrefLevel [Byte0]: 46
1066 22:12:50.116273 [Byte1]: 46
1067 22:12:50.119983
1068 22:12:50.120055 Set Vref, RX VrefLevel [Byte0]: 47
1069 22:12:50.123507 [Byte1]: 47
1070 22:12:50.128109
1071 22:12:50.128182 Set Vref, RX VrefLevel [Byte0]: 48
1072 22:12:50.131071 [Byte1]: 48
1073 22:12:50.135415
1074 22:12:50.135483 Set Vref, RX VrefLevel [Byte0]: 49
1075 22:12:50.138835 [Byte1]: 49
1076 22:12:50.142394
1077 22:12:50.146097 Set Vref, RX VrefLevel [Byte0]: 50
1078 22:12:50.149103 [Byte1]: 50
1079 22:12:50.149170
1080 22:12:50.152577 Set Vref, RX VrefLevel [Byte0]: 51
1081 22:12:50.155836 [Byte1]: 51
1082 22:12:50.155905
1083 22:12:50.159279 Set Vref, RX VrefLevel [Byte0]: 52
1084 22:12:50.162142 [Byte1]: 52
1085 22:12:50.162214
1086 22:12:50.165515 Set Vref, RX VrefLevel [Byte0]: 53
1087 22:12:50.168973 [Byte1]: 53
1088 22:12:50.173510
1089 22:12:50.173585 Set Vref, RX VrefLevel [Byte0]: 54
1090 22:12:50.176286 [Byte1]: 54
1091 22:12:50.180976
1092 22:12:50.181058 Set Vref, RX VrefLevel [Byte0]: 55
1093 22:12:50.184590 [Byte1]: 55
1094 22:12:50.188445
1095 22:12:50.188527 Set Vref, RX VrefLevel [Byte0]: 56
1096 22:12:50.192125 [Byte1]: 56
1097 22:12:50.196390
1098 22:12:50.196472 Set Vref, RX VrefLevel [Byte0]: 57
1099 22:12:50.199440 [Byte1]: 57
1100 22:12:50.203792
1101 22:12:50.203874 Set Vref, RX VrefLevel [Byte0]: 58
1102 22:12:50.207433 [Byte1]: 58
1103 22:12:50.211574
1104 22:12:50.211694 Set Vref, RX VrefLevel [Byte0]: 59
1105 22:12:50.214694 [Byte1]: 59
1106 22:12:50.219306
1107 22:12:50.219388 Set Vref, RX VrefLevel [Byte0]: 60
1108 22:12:50.222424 [Byte1]: 60
1109 22:12:50.227039
1110 22:12:50.227121 Set Vref, RX VrefLevel [Byte0]: 61
1111 22:12:50.233419 [Byte1]: 61
1112 22:12:50.233501
1113 22:12:50.236498 Set Vref, RX VrefLevel [Byte0]: 62
1114 22:12:50.240022 [Byte1]: 62
1115 22:12:50.240105
1116 22:12:50.242891 Set Vref, RX VrefLevel [Byte0]: 63
1117 22:12:50.246069 [Byte1]: 63
1118 22:12:50.249419
1119 22:12:50.249500 Set Vref, RX VrefLevel [Byte0]: 64
1120 22:12:50.252898 [Byte1]: 64
1121 22:12:50.257151
1122 22:12:50.257233 Set Vref, RX VrefLevel [Byte0]: 65
1123 22:12:50.260727 [Byte1]: 65
1124 22:12:50.265333
1125 22:12:50.265415 Set Vref, RX VrefLevel [Byte0]: 66
1126 22:12:50.268314 [Byte1]: 66
1127 22:12:50.272889
1128 22:12:50.272971 Set Vref, RX VrefLevel [Byte0]: 67
1129 22:12:50.275769 [Byte1]: 67
1130 22:12:50.280006
1131 22:12:50.280087 Set Vref, RX VrefLevel [Byte0]: 68
1132 22:12:50.283560 [Byte1]: 68
1133 22:12:50.287676
1134 22:12:50.287784 Set Vref, RX VrefLevel [Byte0]: 69
1135 22:12:50.291109 [Byte1]: 69
1136 22:12:50.295504
1137 22:12:50.295645 Set Vref, RX VrefLevel [Byte0]: 70
1138 22:12:50.298677 [Byte1]: 70
1139 22:12:50.303303
1140 22:12:50.303385 Set Vref, RX VrefLevel [Byte0]: 71
1141 22:12:50.306296 [Byte1]: 71
1142 22:12:50.310647
1143 22:12:50.310729 Set Vref, RX VrefLevel [Byte0]: 72
1144 22:12:50.314072 [Byte1]: 72
1145 22:12:50.318392
1146 22:12:50.318473 Set Vref, RX VrefLevel [Byte0]: 73
1147 22:12:50.321496 [Byte1]: 73
1148 22:12:50.325902
1149 22:12:50.325986 Set Vref, RX VrefLevel [Byte0]: 74
1150 22:12:50.332326 [Byte1]: 74
1151 22:12:50.332408
1152 22:12:50.336272 Set Vref, RX VrefLevel [Byte0]: 75
1153 22:12:50.339113 [Byte1]: 75
1154 22:12:50.339194
1155 22:12:50.342687 Set Vref, RX VrefLevel [Byte0]: 76
1156 22:12:50.345833 [Byte1]: 76
1157 22:12:50.349292
1158 22:12:50.349373 Set Vref, RX VrefLevel [Byte0]: 77
1159 22:12:50.352543 [Byte1]: 77
1160 22:12:50.356681
1161 22:12:50.356762 Set Vref, RX VrefLevel [Byte0]: 78
1162 22:12:50.359781 [Byte1]: 78
1163 22:12:50.364219
1164 22:12:50.364300 Set Vref, RX VrefLevel [Byte0]: 79
1165 22:12:50.367558 [Byte1]: 79
1166 22:12:50.372264
1167 22:12:50.372371 Final RX Vref Byte 0 = 59 to rank0
1168 22:12:50.375142 Final RX Vref Byte 1 = 58 to rank0
1169 22:12:50.378438 Final RX Vref Byte 0 = 59 to rank1
1170 22:12:50.381976 Final RX Vref Byte 1 = 58 to rank1==
1171 22:12:50.385715 Dram Type= 6, Freq= 0, CH_0, rank 0
1172 22:12:50.391967 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1173 22:12:50.392057 ==
1174 22:12:50.392191 DQS Delay:
1175 22:12:50.392252 DQS0 = 0, DQS1 = 0
1176 22:12:50.395059 DQM Delay:
1177 22:12:50.395141 DQM0 = 81, DQM1 = 68
1178 22:12:50.398711 DQ Delay:
1179 22:12:50.401640 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1180 22:12:50.405462 DQ4 =80, DQ5 =68, DQ6 =88, DQ7 =92
1181 22:12:50.405545 DQ8 =60, DQ9 =56, DQ10 =68, DQ11 =60
1182 22:12:50.412174 DQ12 =76, DQ13 =72, DQ14 =76, DQ15 =76
1183 22:12:50.412256
1184 22:12:50.412321
1185 22:12:50.418904 [DQSOSCAuto] RK0, (LSB)MR18= 0x2726, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 400 ps
1186 22:12:50.421750 CH0 RK0: MR19=606, MR18=2726
1187 22:12:50.428505 CH0_RK0: MR19=0x606, MR18=0x2726, DQSOSC=400, MR23=63, INC=92, DEC=61
1188 22:12:50.428588
1189 22:12:50.431532 ----->DramcWriteLeveling(PI) begin...
1190 22:12:50.431672 ==
1191 22:12:50.435135 Dram Type= 6, Freq= 0, CH_0, rank 1
1192 22:12:50.438285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1193 22:12:50.438368 ==
1194 22:12:50.441985 Write leveling (Byte 0): 32 => 32
1195 22:12:50.445474 Write leveling (Byte 1): 30 => 30
1196 22:12:50.448476 DramcWriteLeveling(PI) end<-----
1197 22:12:50.448558
1198 22:12:50.448623 ==
1199 22:12:50.452057 Dram Type= 6, Freq= 0, CH_0, rank 1
1200 22:12:50.455415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1201 22:12:50.455498 ==
1202 22:12:50.458393 [Gating] SW mode calibration
1203 22:12:50.464889 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1204 22:12:50.471457 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1205 22:12:50.474973 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1206 22:12:50.478426 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1207 22:12:50.485211 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1208 22:12:50.488638 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1209 22:12:50.491325 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1210 22:12:50.498091 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1211 22:12:50.501521 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1212 22:12:50.504739 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1213 22:12:50.511304 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1214 22:12:50.514875 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1215 22:12:50.517646 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1216 22:12:50.524283 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1217 22:12:50.527967 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1218 22:12:50.571751 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1219 22:12:50.572357 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 22:12:50.573248 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 22:12:50.573388 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 22:12:50.573674 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1223 22:12:50.573740 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1224 22:12:50.574134 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 22:12:50.574998 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 22:12:50.575080 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 22:12:50.575325 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 22:12:50.592230 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 22:12:50.592819 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 22:12:50.593077 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 22:12:50.593148 0 9 8 | B1->B0 | 2424 302f | 0 1 | (0 0) (0 0)
1232 22:12:50.595755 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1233 22:12:50.598927 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1234 22:12:50.602298 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1235 22:12:50.605670 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1236 22:12:50.612504 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1237 22:12:50.615985 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1238 22:12:50.619253 0 10 4 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 1)
1239 22:12:50.625898 0 10 8 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (1 0)
1240 22:12:50.628988 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 22:12:50.632044 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 22:12:50.638706 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 22:12:50.642400 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 22:12:50.645405 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 22:12:50.652054 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1246 22:12:50.655721 0 11 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1247 22:12:50.658736 0 11 8 | B1->B0 | 2f2f 3939 | 1 1 | (0 0) (0 0)
1248 22:12:50.665239 0 11 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
1249 22:12:50.668745 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1250 22:12:50.671879 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1251 22:12:50.678424 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1252 22:12:50.682222 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1253 22:12:50.685629 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1254 22:12:50.692475 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1255 22:12:50.695879 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1256 22:12:50.699335 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1257 22:12:50.702534 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1258 22:12:50.709391 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1259 22:12:50.712544 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1260 22:12:50.715887 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1261 22:12:50.722709 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1262 22:12:50.726358 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1263 22:12:50.729543 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1264 22:12:50.736068 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1265 22:12:50.739136 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1266 22:12:50.742799 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1267 22:12:50.748982 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1268 22:12:50.752267 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1269 22:12:50.755698 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1270 22:12:50.762413 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1271 22:12:50.765773 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1272 22:12:50.768791 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1273 22:12:50.772241 Total UI for P1: 0, mck2ui 16
1274 22:12:50.775855 best dqsien dly found for B0: ( 0, 14, 8)
1275 22:12:50.778814 Total UI for P1: 0, mck2ui 16
1276 22:12:50.782485 best dqsien dly found for B1: ( 0, 14, 8)
1277 22:12:50.785435 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1278 22:12:50.789080 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1279 22:12:50.789163
1280 22:12:50.795353 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1281 22:12:50.798796 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1282 22:12:50.798878 [Gating] SW calibration Done
1283 22:12:50.802038 ==
1284 22:12:50.802121 Dram Type= 6, Freq= 0, CH_0, rank 1
1285 22:12:50.808282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1286 22:12:50.808365 ==
1287 22:12:50.808430 RX Vref Scan: 0
1288 22:12:50.808491
1289 22:12:50.811736 RX Vref 0 -> 0, step: 1
1290 22:12:50.811819
1291 22:12:50.815250 RX Delay -130 -> 252, step: 16
1292 22:12:50.818223 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1293 22:12:50.821985 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1294 22:12:50.824794 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1295 22:12:50.831743 iDelay=222, Bit 3, Center 69 (-50 ~ 189) 240
1296 22:12:50.835024 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1297 22:12:50.838485 iDelay=222, Bit 5, Center 61 (-66 ~ 189) 256
1298 22:12:50.841685 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1299 22:12:50.844603 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1300 22:12:50.851360 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1301 22:12:50.854727 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1302 22:12:50.858145 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1303 22:12:50.861737 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1304 22:12:50.867857 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1305 22:12:50.871366 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1306 22:12:50.874993 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1307 22:12:50.877957 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1308 22:12:50.878059 ==
1309 22:12:50.881467 Dram Type= 6, Freq= 0, CH_0, rank 1
1310 22:12:50.888200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1311 22:12:50.888286 ==
1312 22:12:50.888372 DQS Delay:
1313 22:12:50.888453 DQS0 = 0, DQS1 = 0
1314 22:12:50.891347 DQM Delay:
1315 22:12:50.891432 DQM0 = 77, DQM1 = 70
1316 22:12:50.894957 DQ Delay:
1317 22:12:50.897853 DQ0 =77, DQ1 =85, DQ2 =69, DQ3 =69
1318 22:12:50.897938 DQ4 =77, DQ5 =61, DQ6 =85, DQ7 =93
1319 22:12:50.901483 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
1320 22:12:50.908046 DQ12 =77, DQ13 =77, DQ14 =85, DQ15 =77
1321 22:12:50.908132
1322 22:12:50.908217
1323 22:12:50.908298 ==
1324 22:12:50.911315 Dram Type= 6, Freq= 0, CH_0, rank 1
1325 22:12:50.914594 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1326 22:12:50.914680 ==
1327 22:12:50.914768
1328 22:12:50.914849
1329 22:12:50.917829 TX Vref Scan disable
1330 22:12:50.917916 == TX Byte 0 ==
1331 22:12:50.924234 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1332 22:12:50.927469 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1333 22:12:50.927569 == TX Byte 1 ==
1334 22:12:50.934144 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1335 22:12:50.937674 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1336 22:12:50.937779 ==
1337 22:12:50.941050 Dram Type= 6, Freq= 0, CH_0, rank 1
1338 22:12:50.944342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1339 22:12:50.944475 ==
1340 22:12:50.957866 TX Vref=22, minBit 12, minWin=26, winSum=436
1341 22:12:50.961437 TX Vref=24, minBit 11, minWin=26, winSum=435
1342 22:12:50.965024 TX Vref=26, minBit 1, minWin=27, winSum=440
1343 22:12:50.967746 TX Vref=28, minBit 1, minWin=27, winSum=440
1344 22:12:50.971496 TX Vref=30, minBit 1, minWin=27, winSum=443
1345 22:12:50.977900 TX Vref=32, minBit 11, minWin=26, winSum=440
1346 22:12:50.981019 [TxChooseVref] Worse bit 1, Min win 27, Win sum 443, Final Vref 30
1347 22:12:50.981122
1348 22:12:50.984459 Final TX Range 1 Vref 30
1349 22:12:50.984528
1350 22:12:50.984588 ==
1351 22:12:50.988303 Dram Type= 6, Freq= 0, CH_0, rank 1
1352 22:12:50.991292 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1353 22:12:50.994864 ==
1354 22:12:50.994951
1355 22:12:50.995042
1356 22:12:50.995127 TX Vref Scan disable
1357 22:12:50.998582 == TX Byte 0 ==
1358 22:12:51.001441 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1359 22:12:51.008304 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1360 22:12:51.008383 == TX Byte 1 ==
1361 22:12:51.011687 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1362 22:12:51.018188 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1363 22:12:51.018286
1364 22:12:51.018373 [DATLAT]
1365 22:12:51.018461 Freq=800, CH0 RK1
1366 22:12:51.018546
1367 22:12:51.021471 DATLAT Default: 0xa
1368 22:12:51.021553 0, 0xFFFF, sum = 0
1369 22:12:51.025069 1, 0xFFFF, sum = 0
1370 22:12:51.028171 2, 0xFFFF, sum = 0
1371 22:12:51.028246 3, 0xFFFF, sum = 0
1372 22:12:51.031725 4, 0xFFFF, sum = 0
1373 22:12:51.031818 5, 0xFFFF, sum = 0
1374 22:12:51.034519 6, 0xFFFF, sum = 0
1375 22:12:51.034614 7, 0xFFFF, sum = 0
1376 22:12:51.038276 8, 0xFFFF, sum = 0
1377 22:12:51.038394 9, 0x0, sum = 1
1378 22:12:51.041651 10, 0x0, sum = 2
1379 22:12:51.041760 11, 0x0, sum = 3
1380 22:12:51.041863 12, 0x0, sum = 4
1381 22:12:51.044593 best_step = 10
1382 22:12:51.044689
1383 22:12:51.044784 ==
1384 22:12:51.048169 Dram Type= 6, Freq= 0, CH_0, rank 1
1385 22:12:51.051410 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1386 22:12:51.051521 ==
1387 22:12:51.054496 RX Vref Scan: 0
1388 22:12:51.054617
1389 22:12:51.057970 RX Vref 0 -> 0, step: 1
1390 22:12:51.058082
1391 22:12:51.058188 RX Delay -111 -> 252, step: 8
1392 22:12:51.064895 iDelay=209, Bit 0, Center 76 (-39 ~ 192) 232
1393 22:12:51.068647 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1394 22:12:51.071574 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1395 22:12:51.075268 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1396 22:12:51.078422 iDelay=209, Bit 4, Center 80 (-39 ~ 200) 240
1397 22:12:51.084931 iDelay=209, Bit 5, Center 64 (-55 ~ 184) 240
1398 22:12:51.088486 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
1399 22:12:51.091487 iDelay=209, Bit 7, Center 88 (-31 ~ 208) 240
1400 22:12:51.095131 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
1401 22:12:51.098276 iDelay=209, Bit 9, Center 56 (-63 ~ 176) 240
1402 22:12:51.105292 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1403 22:12:51.108245 iDelay=209, Bit 11, Center 64 (-55 ~ 184) 240
1404 22:12:51.111247 iDelay=209, Bit 12, Center 76 (-47 ~ 200) 248
1405 22:12:51.114740 iDelay=209, Bit 13, Center 76 (-39 ~ 192) 232
1406 22:12:51.121479 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1407 22:12:51.124684 iDelay=209, Bit 15, Center 76 (-39 ~ 192) 232
1408 22:12:51.124758 ==
1409 22:12:51.128429 Dram Type= 6, Freq= 0, CH_0, rank 1
1410 22:12:51.131430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1411 22:12:51.131536 ==
1412 22:12:51.134725 DQS Delay:
1413 22:12:51.134825 DQS0 = 0, DQS1 = 0
1414 22:12:51.134973 DQM Delay:
1415 22:12:51.137913 DQM0 = 78, DQM1 = 70
1416 22:12:51.137986 DQ Delay:
1417 22:12:51.141339 DQ0 =76, DQ1 =84, DQ2 =76, DQ3 =72
1418 22:12:51.144657 DQ4 =80, DQ5 =64, DQ6 =88, DQ7 =88
1419 22:12:51.147793 DQ8 =64, DQ9 =56, DQ10 =72, DQ11 =64
1420 22:12:51.151403 DQ12 =76, DQ13 =76, DQ14 =80, DQ15 =76
1421 22:12:51.151503
1422 22:12:51.151603
1423 22:12:51.161495 [DQSOSCAuto] RK1, (LSB)MR18= 0x4823, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 391 ps
1424 22:12:51.161577 CH0 RK1: MR19=606, MR18=4823
1425 22:12:51.167917 CH0_RK1: MR19=0x606, MR18=0x4823, DQSOSC=391, MR23=63, INC=96, DEC=64
1426 22:12:51.171296 [RxdqsGatingPostProcess] freq 800
1427 22:12:51.177676 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1428 22:12:51.181444 Pre-setting of DQS Precalculation
1429 22:12:51.184471 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1430 22:12:51.184556 ==
1431 22:12:51.187902 Dram Type= 6, Freq= 0, CH_1, rank 0
1432 22:12:51.194483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1433 22:12:51.194592 ==
1434 22:12:51.197550 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1435 22:12:51.204548 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1436 22:12:51.213767 [CA 0] Center 36 (6~66) winsize 61
1437 22:12:51.216634 [CA 1] Center 36 (6~67) winsize 62
1438 22:12:51.220378 [CA 2] Center 34 (4~64) winsize 61
1439 22:12:51.223454 [CA 3] Center 34 (4~64) winsize 61
1440 22:12:51.226766 [CA 4] Center 34 (4~64) winsize 61
1441 22:12:51.230390 [CA 5] Center 33 (4~63) winsize 60
1442 22:12:51.230489
1443 22:12:51.233300 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1444 22:12:51.233398
1445 22:12:51.236982 [CATrainingPosCal] consider 1 rank data
1446 22:12:51.240552 u2DelayCellTimex100 = 270/100 ps
1447 22:12:51.243709 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1448 22:12:51.246593 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1449 22:12:51.253591 CA2 delay=34 (4~64),Diff = 1 PI (7 cell)
1450 22:12:51.256840 CA3 delay=34 (4~64),Diff = 1 PI (7 cell)
1451 22:12:51.260249 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
1452 22:12:51.263245 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
1453 22:12:51.263345
1454 22:12:51.266823 CA PerBit enable=1, Macro0, CA PI delay=33
1455 22:12:51.266923
1456 22:12:51.270144 [CBTSetCACLKResult] CA Dly = 33
1457 22:12:51.270243 CS Dly: 5 (0~36)
1458 22:12:51.273449 ==
1459 22:12:51.273621 Dram Type= 6, Freq= 0, CH_1, rank 1
1460 22:12:51.279779 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1461 22:12:51.279853 ==
1462 22:12:51.283572 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1463 22:12:51.289572 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1464 22:12:51.299667 [CA 0] Center 36 (6~66) winsize 61
1465 22:12:51.302741 [CA 1] Center 36 (6~67) winsize 62
1466 22:12:51.306108 [CA 2] Center 34 (4~65) winsize 62
1467 22:12:51.309517 [CA 3] Center 33 (3~64) winsize 62
1468 22:12:51.313133 [CA 4] Center 34 (4~65) winsize 62
1469 22:12:51.315975 [CA 5] Center 33 (3~64) winsize 62
1470 22:12:51.316068
1471 22:12:51.319722 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1472 22:12:51.319792
1473 22:12:51.322540 [CATrainingPosCal] consider 2 rank data
1474 22:12:51.326367 u2DelayCellTimex100 = 270/100 ps
1475 22:12:51.329514 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1476 22:12:51.335987 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1477 22:12:51.339565 CA2 delay=34 (4~64),Diff = 1 PI (7 cell)
1478 22:12:51.342858 CA3 delay=34 (4~64),Diff = 1 PI (7 cell)
1479 22:12:51.346192 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
1480 22:12:51.349670 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
1481 22:12:51.349772
1482 22:12:51.353291 CA PerBit enable=1, Macro0, CA PI delay=33
1483 22:12:51.353427
1484 22:12:51.357156 [CBTSetCACLKResult] CA Dly = 33
1485 22:12:51.357255 CS Dly: 5 (0~37)
1486 22:12:51.357376
1487 22:12:51.360993 ----->DramcWriteLeveling(PI) begin...
1488 22:12:51.361065 ==
1489 22:12:51.364403 Dram Type= 6, Freq= 0, CH_1, rank 0
1490 22:12:51.368444 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1491 22:12:51.368531 ==
1492 22:12:51.371687 Write leveling (Byte 0): 29 => 29
1493 22:12:51.375491 Write leveling (Byte 1): 29 => 29
1494 22:12:51.379226 DramcWriteLeveling(PI) end<-----
1495 22:12:51.379301
1496 22:12:51.379365 ==
1497 22:12:51.382765 Dram Type= 6, Freq= 0, CH_1, rank 0
1498 22:12:51.385957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1499 22:12:51.386055 ==
1500 22:12:51.389112 [Gating] SW mode calibration
1501 22:12:51.395535 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1502 22:12:51.402143 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1503 22:12:51.405742 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1504 22:12:51.409277 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1505 22:12:51.415829 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1506 22:12:51.418942 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1507 22:12:51.422666 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1508 22:12:51.429339 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1509 22:12:51.432217 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1510 22:12:51.435749 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1511 22:12:51.438741 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1512 22:12:51.445419 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1513 22:12:51.448951 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1514 22:12:51.452196 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1515 22:12:51.458556 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1516 22:12:51.462027 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 22:12:51.465322 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 22:12:51.471749 0 7 28 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
1519 22:12:51.475110 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 22:12:51.478472 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 22:12:51.484938 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1522 22:12:51.488419 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 22:12:51.491930 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 22:12:51.498478 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 22:12:51.501811 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 22:12:51.504854 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 22:12:51.511525 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 22:12:51.514590 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 22:12:51.518173 0 9 8 | B1->B0 | 2f2f 2d2d | 1 1 | (1 1) (1 1)
1530 22:12:51.524820 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1531 22:12:51.527830 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1532 22:12:51.531682 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1533 22:12:51.538260 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1534 22:12:51.541612 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1535 22:12:51.544618 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1536 22:12:51.551364 0 10 4 | B1->B0 | 3131 3434 | 1 0 | (1 1) (0 0)
1537 22:12:51.554502 0 10 8 | B1->B0 | 2828 3030 | 0 1 | (1 0) (1 0)
1538 22:12:51.557824 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 22:12:51.564608 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 22:12:51.568137 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 22:12:51.571259 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 22:12:51.578283 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 22:12:51.581581 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1544 22:12:51.584625 0 11 4 | B1->B0 | 2424 2626 | 0 0 | (0 0) (0 0)
1545 22:12:51.591037 0 11 8 | B1->B0 | 3c3c 3938 | 0 1 | (0 0) (0 0)
1546 22:12:51.594719 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1547 22:12:51.598343 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1548 22:12:51.604297 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1549 22:12:51.607837 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1550 22:12:51.611490 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1551 22:12:51.617295 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1552 22:12:51.621119 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1553 22:12:51.624215 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1554 22:12:51.630849 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1555 22:12:51.634532 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1556 22:12:51.637507 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1557 22:12:51.644289 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1558 22:12:51.647700 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1559 22:12:51.650720 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1560 22:12:51.657474 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1561 22:12:51.660425 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1562 22:12:51.663937 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1563 22:12:51.671037 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1564 22:12:51.673813 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1565 22:12:51.677312 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1566 22:12:51.680532 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1567 22:12:51.687078 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 22:12:51.690600 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1569 22:12:51.694170 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1570 22:12:51.700799 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1571 22:12:51.704021 Total UI for P1: 0, mck2ui 16
1572 22:12:51.707458 best dqsien dly found for B0: ( 0, 14, 6)
1573 22:12:51.710992 Total UI for P1: 0, mck2ui 16
1574 22:12:51.714290 best dqsien dly found for B1: ( 0, 14, 8)
1575 22:12:51.717498 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1576 22:12:51.720566 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1577 22:12:51.720649
1578 22:12:51.723727 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1579 22:12:51.727228 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1580 22:12:51.730410 [Gating] SW calibration Done
1581 22:12:51.730494 ==
1582 22:12:51.734072 Dram Type= 6, Freq= 0, CH_1, rank 0
1583 22:12:51.737011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1584 22:12:51.737094 ==
1585 22:12:51.740598 RX Vref Scan: 0
1586 22:12:51.740681
1587 22:12:51.740748 RX Vref 0 -> 0, step: 1
1588 22:12:51.740812
1589 22:12:51.743696 RX Delay -130 -> 252, step: 16
1590 22:12:51.750239 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1591 22:12:51.753804 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1592 22:12:51.756871 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1593 22:12:51.760312 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1594 22:12:51.763385 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1595 22:12:51.770082 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1596 22:12:51.773603 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1597 22:12:51.776717 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1598 22:12:51.780061 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1599 22:12:51.783503 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1600 22:12:51.790044 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1601 22:12:51.793493 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1602 22:12:51.796338 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1603 22:12:51.799956 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1604 22:12:51.803292 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1605 22:12:51.809911 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1606 22:12:51.809994 ==
1607 22:12:51.813319 Dram Type= 6, Freq= 0, CH_1, rank 0
1608 22:12:51.816686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1609 22:12:51.816770 ==
1610 22:12:51.816836 DQS Delay:
1611 22:12:51.820319 DQS0 = 0, DQS1 = 0
1612 22:12:51.820401 DQM Delay:
1613 22:12:51.823315 DQM0 = 81, DQM1 = 73
1614 22:12:51.823398 DQ Delay:
1615 22:12:51.826496 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1616 22:12:51.829810 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1617 22:12:51.833333 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
1618 22:12:51.836248 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1619 22:12:51.836330
1620 22:12:51.836396
1621 22:12:51.836458 ==
1622 22:12:51.840046 Dram Type= 6, Freq= 0, CH_1, rank 0
1623 22:12:51.843102 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1624 22:12:51.843186 ==
1625 22:12:51.846609
1626 22:12:51.846692
1627 22:12:51.846758 TX Vref Scan disable
1628 22:12:51.849613 == TX Byte 0 ==
1629 22:12:51.853126 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1630 22:12:51.856162 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1631 22:12:51.859754 == TX Byte 1 ==
1632 22:12:51.862766 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1633 22:12:51.866462 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1634 22:12:51.866545 ==
1635 22:12:51.869339 Dram Type= 6, Freq= 0, CH_1, rank 0
1636 22:12:51.876552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1637 22:12:51.876651 ==
1638 22:12:51.887816 TX Vref=22, minBit 8, minWin=27, winSum=444
1639 22:12:51.891103 TX Vref=24, minBit 8, minWin=27, winSum=447
1640 22:12:51.894658 TX Vref=26, minBit 8, minWin=27, winSum=450
1641 22:12:51.898202 TX Vref=28, minBit 11, minWin=27, winSum=452
1642 22:12:51.901098 TX Vref=30, minBit 9, minWin=27, winSum=455
1643 22:12:51.907766 TX Vref=32, minBit 9, minWin=27, winSum=453
1644 22:12:51.910987 [TxChooseVref] Worse bit 9, Min win 27, Win sum 455, Final Vref 30
1645 22:12:51.911071
1646 22:12:51.914580 Final TX Range 1 Vref 30
1647 22:12:51.914664
1648 22:12:51.914730 ==
1649 22:12:51.918197 Dram Type= 6, Freq= 0, CH_1, rank 0
1650 22:12:51.921573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1651 22:12:51.921657 ==
1652 22:12:51.924245
1653 22:12:51.924351
1654 22:12:51.924457 TX Vref Scan disable
1655 22:12:51.928189 == TX Byte 0 ==
1656 22:12:51.931348 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1657 22:12:51.937804 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1658 22:12:51.937892 == TX Byte 1 ==
1659 22:12:51.941580 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1660 22:12:51.947717 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1661 22:12:51.947800
1662 22:12:51.947867 [DATLAT]
1663 22:12:51.947928 Freq=800, CH1 RK0
1664 22:12:51.947988
1665 22:12:51.951249 DATLAT Default: 0xa
1666 22:12:51.951332 0, 0xFFFF, sum = 0
1667 22:12:51.954208 1, 0xFFFF, sum = 0
1668 22:12:51.957688 2, 0xFFFF, sum = 0
1669 22:12:51.957772 3, 0xFFFF, sum = 0
1670 22:12:51.961223 4, 0xFFFF, sum = 0
1671 22:12:51.961307 5, 0xFFFF, sum = 0
1672 22:12:51.964550 6, 0xFFFF, sum = 0
1673 22:12:51.964634 7, 0xFFFF, sum = 0
1674 22:12:51.967880 8, 0xFFFF, sum = 0
1675 22:12:51.967964 9, 0x0, sum = 1
1676 22:12:51.970914 10, 0x0, sum = 2
1677 22:12:51.970999 11, 0x0, sum = 3
1678 22:12:51.971066 12, 0x0, sum = 4
1679 22:12:51.974440 best_step = 10
1680 22:12:51.974523
1681 22:12:51.974588 ==
1682 22:12:51.977829 Dram Type= 6, Freq= 0, CH_1, rank 0
1683 22:12:51.980844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1684 22:12:51.980921 ==
1685 22:12:51.983876 RX Vref Scan: 1
1686 22:12:51.983971
1687 22:12:51.987332 Set Vref Range= 32 -> 127
1688 22:12:51.987413
1689 22:12:51.987478 RX Vref 32 -> 127, step: 1
1690 22:12:51.987538
1691 22:12:51.990481 RX Delay -95 -> 252, step: 8
1692 22:12:51.990562
1693 22:12:51.994106 Set Vref, RX VrefLevel [Byte0]: 32
1694 22:12:51.997609 [Byte1]: 32
1695 22:12:52.001011
1696 22:12:52.001092 Set Vref, RX VrefLevel [Byte0]: 33
1697 22:12:52.004201 [Byte1]: 33
1698 22:12:52.008001
1699 22:12:52.008081 Set Vref, RX VrefLevel [Byte0]: 34
1700 22:12:52.011622 [Byte1]: 34
1701 22:12:52.016291
1702 22:12:52.016382 Set Vref, RX VrefLevel [Byte0]: 35
1703 22:12:52.019364 [Byte1]: 35
1704 22:12:52.023312
1705 22:12:52.023393 Set Vref, RX VrefLevel [Byte0]: 36
1706 22:12:52.026637 [Byte1]: 36
1707 22:12:52.030809
1708 22:12:52.030889 Set Vref, RX VrefLevel [Byte0]: 37
1709 22:12:52.034402 [Byte1]: 37
1710 22:12:52.038755
1711 22:12:52.038830 Set Vref, RX VrefLevel [Byte0]: 38
1712 22:12:52.042157 [Byte1]: 38
1713 22:12:52.045984
1714 22:12:52.046068 Set Vref, RX VrefLevel [Byte0]: 39
1715 22:12:52.049676 [Byte1]: 39
1716 22:12:52.053963
1717 22:12:52.054037 Set Vref, RX VrefLevel [Byte0]: 40
1718 22:12:52.056991 [Byte1]: 40
1719 22:12:52.061251
1720 22:12:52.061331 Set Vref, RX VrefLevel [Byte0]: 41
1721 22:12:52.064632 [Byte1]: 41
1722 22:12:52.068885
1723 22:12:52.068966 Set Vref, RX VrefLevel [Byte0]: 42
1724 22:12:52.072527 [Byte1]: 42
1725 22:12:52.076749
1726 22:12:52.076831 Set Vref, RX VrefLevel [Byte0]: 43
1727 22:12:52.080064 [Byte1]: 43
1728 22:12:52.084362
1729 22:12:52.084443 Set Vref, RX VrefLevel [Byte0]: 44
1730 22:12:52.087813 [Byte1]: 44
1731 22:12:52.092179
1732 22:12:52.092260 Set Vref, RX VrefLevel [Byte0]: 45
1733 22:12:52.095403 [Byte1]: 45
1734 22:12:52.099719
1735 22:12:52.099812 Set Vref, RX VrefLevel [Byte0]: 46
1736 22:12:52.102602 [Byte1]: 46
1737 22:12:52.107236
1738 22:12:52.107317 Set Vref, RX VrefLevel [Byte0]: 47
1739 22:12:52.110425 [Byte1]: 47
1740 22:12:52.114911
1741 22:12:52.114992 Set Vref, RX VrefLevel [Byte0]: 48
1742 22:12:52.118180 [Byte1]: 48
1743 22:12:52.122073
1744 22:12:52.122154 Set Vref, RX VrefLevel [Byte0]: 49
1745 22:12:52.125969 [Byte1]: 49
1746 22:12:52.130233
1747 22:12:52.130317 Set Vref, RX VrefLevel [Byte0]: 50
1748 22:12:52.133336 [Byte1]: 50
1749 22:12:52.137383
1750 22:12:52.137463 Set Vref, RX VrefLevel [Byte0]: 51
1751 22:12:52.141234 [Byte1]: 51
1752 22:12:52.144906
1753 22:12:52.144990 Set Vref, RX VrefLevel [Byte0]: 52
1754 22:12:52.148341 [Byte1]: 52
1755 22:12:52.152719
1756 22:12:52.152799 Set Vref, RX VrefLevel [Byte0]: 53
1757 22:12:52.156228 [Byte1]: 53
1758 22:12:52.160570
1759 22:12:52.160677 Set Vref, RX VrefLevel [Byte0]: 54
1760 22:12:52.163298 [Byte1]: 54
1761 22:12:52.167581
1762 22:12:52.167689 Set Vref, RX VrefLevel [Byte0]: 55
1763 22:12:52.171160 [Byte1]: 55
1764 22:12:52.175234
1765 22:12:52.175316 Set Vref, RX VrefLevel [Byte0]: 56
1766 22:12:52.178976 [Byte1]: 56
1767 22:12:52.182944
1768 22:12:52.183026 Set Vref, RX VrefLevel [Byte0]: 57
1769 22:12:52.186620 [Byte1]: 57
1770 22:12:52.190823
1771 22:12:52.190904 Set Vref, RX VrefLevel [Byte0]: 58
1772 22:12:52.193789 [Byte1]: 58
1773 22:12:52.198061
1774 22:12:52.198142 Set Vref, RX VrefLevel [Byte0]: 59
1775 22:12:52.202021 [Byte1]: 59
1776 22:12:52.205871
1777 22:12:52.205953 Set Vref, RX VrefLevel [Byte0]: 60
1778 22:12:52.209156 [Byte1]: 60
1779 22:12:52.213282
1780 22:12:52.213364 Set Vref, RX VrefLevel [Byte0]: 61
1781 22:12:52.216698 [Byte1]: 61
1782 22:12:52.221222
1783 22:12:52.221303 Set Vref, RX VrefLevel [Byte0]: 62
1784 22:12:52.224550 [Byte1]: 62
1785 22:12:52.228510
1786 22:12:52.228591 Set Vref, RX VrefLevel [Byte0]: 63
1787 22:12:52.231860 [Byte1]: 63
1788 22:12:52.236341
1789 22:12:52.236428 Set Vref, RX VrefLevel [Byte0]: 64
1790 22:12:52.239669 [Byte1]: 64
1791 22:12:52.244245
1792 22:12:52.244325 Set Vref, RX VrefLevel [Byte0]: 65
1793 22:12:52.247229 [Byte1]: 65
1794 22:12:52.251796
1795 22:12:52.251893 Set Vref, RX VrefLevel [Byte0]: 66
1796 22:12:52.254420 [Byte1]: 66
1797 22:12:52.259015
1798 22:12:52.259114 Set Vref, RX VrefLevel [Byte0]: 67
1799 22:12:52.262175 [Byte1]: 67
1800 22:12:52.266390
1801 22:12:52.266472 Set Vref, RX VrefLevel [Byte0]: 68
1802 22:12:52.269839 [Byte1]: 68
1803 22:12:52.274211
1804 22:12:52.274323 Set Vref, RX VrefLevel [Byte0]: 69
1805 22:12:52.277756 [Byte1]: 69
1806 22:12:52.282195
1807 22:12:52.282292 Set Vref, RX VrefLevel [Byte0]: 70
1808 22:12:52.285264 [Byte1]: 70
1809 22:12:52.289226
1810 22:12:52.289324 Set Vref, RX VrefLevel [Byte0]: 71
1811 22:12:52.292708 [Byte1]: 71
1812 22:12:52.296920
1813 22:12:52.297001 Set Vref, RX VrefLevel [Byte0]: 72
1814 22:12:52.300631 [Byte1]: 72
1815 22:12:52.304824
1816 22:12:52.304899 Set Vref, RX VrefLevel [Byte0]: 73
1817 22:12:52.307659 [Byte1]: 73
1818 22:12:52.312052
1819 22:12:52.312122 Set Vref, RX VrefLevel [Byte0]: 74
1820 22:12:52.315414 [Byte1]: 74
1821 22:12:52.319595
1822 22:12:52.319670 Set Vref, RX VrefLevel [Byte0]: 75
1823 22:12:52.323257 [Byte1]: 75
1824 22:12:52.327385
1825 22:12:52.327485 Set Vref, RX VrefLevel [Byte0]: 76
1826 22:12:52.330711 [Byte1]: 76
1827 22:12:52.335145
1828 22:12:52.335250 Final RX Vref Byte 0 = 56 to rank0
1829 22:12:52.338612 Final RX Vref Byte 1 = 56 to rank0
1830 22:12:52.341687 Final RX Vref Byte 0 = 56 to rank1
1831 22:12:52.344873 Final RX Vref Byte 1 = 56 to rank1==
1832 22:12:52.348309 Dram Type= 6, Freq= 0, CH_1, rank 0
1833 22:12:52.354685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1834 22:12:52.354773 ==
1835 22:12:52.354840 DQS Delay:
1836 22:12:52.354931 DQS0 = 0, DQS1 = 0
1837 22:12:52.358154 DQM Delay:
1838 22:12:52.358237 DQM0 = 80, DQM1 = 70
1839 22:12:52.361586 DQ Delay:
1840 22:12:52.364877 DQ0 =84, DQ1 =76, DQ2 =68, DQ3 =76
1841 22:12:52.364956 DQ4 =76, DQ5 =92, DQ6 =92, DQ7 =76
1842 22:12:52.368403 DQ8 =60, DQ9 =64, DQ10 =72, DQ11 =64
1843 22:12:52.374528 DQ12 =76, DQ13 =76, DQ14 =76, DQ15 =76
1844 22:12:52.374674
1845 22:12:52.374757
1846 22:12:52.381362 [DQSOSCAuto] RK0, (LSB)MR18= 0x121c, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 405 ps
1847 22:12:52.384889 CH1 RK0: MR19=606, MR18=121C
1848 22:12:52.391664 CH1_RK0: MR19=0x606, MR18=0x121C, DQSOSC=402, MR23=63, INC=91, DEC=60
1849 22:12:52.391749
1850 22:12:52.395125 ----->DramcWriteLeveling(PI) begin...
1851 22:12:52.395199 ==
1852 22:12:52.398133 Dram Type= 6, Freq= 0, CH_1, rank 1
1853 22:12:52.401326 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1854 22:12:52.401398 ==
1855 22:12:52.404854 Write leveling (Byte 0): 28 => 28
1856 22:12:52.407991 Write leveling (Byte 1): 29 => 29
1857 22:12:52.411609 DramcWriteLeveling(PI) end<-----
1858 22:12:52.411699
1859 22:12:52.411772 ==
1860 22:12:52.414532 Dram Type= 6, Freq= 0, CH_1, rank 1
1861 22:12:52.417771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1862 22:12:52.417852 ==
1863 22:12:52.421240 [Gating] SW mode calibration
1864 22:12:52.427961 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1865 22:12:52.434473 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1866 22:12:52.437857 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1867 22:12:52.444427 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1868 22:12:52.447919 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1869 22:12:52.451050 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1870 22:12:52.454318 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 22:12:52.461280 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 22:12:52.463996 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 22:12:52.467572 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 22:12:52.474027 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 22:12:52.477210 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 22:12:52.480593 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 22:12:52.487677 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 22:12:52.490671 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 22:12:52.494149 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 22:12:52.500879 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 22:12:52.503750 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 22:12:52.507427 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 22:12:52.514237 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1884 22:12:52.517236 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1885 22:12:52.520887 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 22:12:52.527317 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 22:12:52.530386 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 22:12:52.533549 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 22:12:52.540469 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 22:12:52.544118 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 22:12:52.547053 0 9 4 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (0 0)
1892 22:12:52.553744 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1893 22:12:52.557146 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1894 22:12:52.560584 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1895 22:12:52.566741 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1896 22:12:52.570116 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1897 22:12:52.573212 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1898 22:12:52.580511 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1899 22:12:52.583188 0 10 4 | B1->B0 | 3232 2c2c | 0 0 | (0 1) (0 1)
1900 22:12:52.586914 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
1901 22:12:52.593420 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 22:12:52.596817 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1903 22:12:52.600262 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1904 22:12:52.606491 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1905 22:12:52.610038 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1906 22:12:52.613182 0 11 0 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
1907 22:12:52.620292 0 11 4 | B1->B0 | 2b2b 3c3c | 0 0 | (0 0) (0 0)
1908 22:12:52.623322 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1909 22:12:52.626923 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1910 22:12:52.633525 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1911 22:12:52.636658 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1912 22:12:52.640270 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1913 22:12:52.643348 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1914 22:12:52.649842 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1915 22:12:52.653115 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1916 22:12:52.656634 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1917 22:12:52.663270 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1918 22:12:52.666582 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1919 22:12:52.669743 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1920 22:12:52.676307 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1921 22:12:52.679768 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1922 22:12:52.683414 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1923 22:12:52.689662 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1924 22:12:52.693143 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1925 22:12:52.696537 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1926 22:12:52.702916 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1927 22:12:52.706637 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1928 22:12:52.709568 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1929 22:12:52.716102 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1930 22:12:52.719633 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1931 22:12:52.722759 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1932 22:12:52.729230 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1933 22:12:52.729314 Total UI for P1: 0, mck2ui 16
1934 22:12:52.736550 best dqsien dly found for B0: ( 0, 14, 4)
1935 22:12:52.736634 Total UI for P1: 0, mck2ui 16
1936 22:12:52.743150 best dqsien dly found for B1: ( 0, 14, 6)
1937 22:12:52.746310 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1938 22:12:52.749713 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1939 22:12:52.749796
1940 22:12:52.752622 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1941 22:12:52.756358 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1942 22:12:52.759457 [Gating] SW calibration Done
1943 22:12:52.759540 ==
1944 22:12:52.762490 Dram Type= 6, Freq= 0, CH_1, rank 1
1945 22:12:52.765818 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1946 22:12:52.765902 ==
1947 22:12:52.769615 RX Vref Scan: 0
1948 22:12:52.769715
1949 22:12:52.769795 RX Vref 0 -> 0, step: 1
1950 22:12:52.769871
1951 22:12:52.772786 RX Delay -130 -> 252, step: 16
1952 22:12:52.776307 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1953 22:12:52.782367 iDelay=222, Bit 1, Center 69 (-50 ~ 189) 240
1954 22:12:52.785578 iDelay=222, Bit 2, Center 61 (-66 ~ 189) 256
1955 22:12:52.789273 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1956 22:12:52.792751 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1957 22:12:52.795535 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1958 22:12:52.802657 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1959 22:12:52.805474 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1960 22:12:52.809290 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1961 22:12:52.812333 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1962 22:12:52.815700 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1963 22:12:52.822477 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1964 22:12:52.826046 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1965 22:12:52.829061 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1966 22:12:52.832455 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1967 22:12:52.835476 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1968 22:12:52.839240 ==
1969 22:12:52.842169 Dram Type= 6, Freq= 0, CH_1, rank 1
1970 22:12:52.845780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1971 22:12:52.845864 ==
1972 22:12:52.845930 DQS Delay:
1973 22:12:52.848865 DQS0 = 0, DQS1 = 0
1974 22:12:52.848948 DQM Delay:
1975 22:12:52.852416 DQM0 = 79, DQM1 = 74
1976 22:12:52.852498 DQ Delay:
1977 22:12:52.855903 DQ0 =85, DQ1 =69, DQ2 =61, DQ3 =77
1978 22:12:52.858820 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1979 22:12:52.861909 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =61
1980 22:12:52.865326 DQ12 =85, DQ13 =77, DQ14 =85, DQ15 =85
1981 22:12:52.865408
1982 22:12:52.865512
1983 22:12:52.865573 ==
1984 22:12:52.868634 Dram Type= 6, Freq= 0, CH_1, rank 1
1985 22:12:52.872149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1986 22:12:52.872232 ==
1987 22:12:52.872298
1988 22:12:52.872358
1989 22:12:52.875496 TX Vref Scan disable
1990 22:12:52.878922 == TX Byte 0 ==
1991 22:12:52.882312 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1992 22:12:52.884951 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1993 22:12:52.888347 == TX Byte 1 ==
1994 22:12:52.891596 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1995 22:12:52.895344 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1996 22:12:52.895443 ==
1997 22:12:52.898352 Dram Type= 6, Freq= 0, CH_1, rank 1
1998 22:12:52.905021 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1999 22:12:52.905121 ==
2000 22:12:52.917223 TX Vref=22, minBit 0, minWin=28, winSum=451
2001 22:12:52.919757 TX Vref=24, minBit 11, minWin=27, winSum=453
2002 22:12:52.923229 TX Vref=26, minBit 0, minWin=28, winSum=457
2003 22:12:52.926749 TX Vref=28, minBit 6, minWin=28, winSum=460
2004 22:12:52.929782 TX Vref=30, minBit 13, minWin=28, winSum=464
2005 22:12:52.936536 TX Vref=32, minBit 2, minWin=28, winSum=455
2006 22:12:52.940157 [TxChooseVref] Worse bit 13, Min win 28, Win sum 464, Final Vref 30
2007 22:12:52.940249
2008 22:12:52.943079 Final TX Range 1 Vref 30
2009 22:12:52.943161
2010 22:12:52.943226 ==
2011 22:12:52.946615 Dram Type= 6, Freq= 0, CH_1, rank 1
2012 22:12:52.949736 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2013 22:12:52.953230 ==
2014 22:12:52.953311
2015 22:12:52.953377
2016 22:12:52.953437 TX Vref Scan disable
2017 22:12:52.956962 == TX Byte 0 ==
2018 22:12:52.959962 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2019 22:12:52.966886 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2020 22:12:52.966968 == TX Byte 1 ==
2021 22:12:52.970105 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2022 22:12:52.976781 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2023 22:12:52.976865
2024 22:12:52.976930 [DATLAT]
2025 22:12:52.976990 Freq=800, CH1 RK1
2026 22:12:52.977050
2027 22:12:52.979800 DATLAT Default: 0xa
2028 22:12:52.979882 0, 0xFFFF, sum = 0
2029 22:12:52.983538 1, 0xFFFF, sum = 0
2030 22:12:52.983647 2, 0xFFFF, sum = 0
2031 22:12:52.986599 3, 0xFFFF, sum = 0
2032 22:12:52.990035 4, 0xFFFF, sum = 0
2033 22:12:52.990118 5, 0xFFFF, sum = 0
2034 22:12:52.993362 6, 0xFFFF, sum = 0
2035 22:12:52.993445 7, 0xFFFF, sum = 0
2036 22:12:52.996744 8, 0xFFFF, sum = 0
2037 22:12:52.996828 9, 0x0, sum = 1
2038 22:12:52.999668 10, 0x0, sum = 2
2039 22:12:52.999751 11, 0x0, sum = 3
2040 22:12:52.999818 12, 0x0, sum = 4
2041 22:12:53.003404 best_step = 10
2042 22:12:53.003486
2043 22:12:53.003550 ==
2044 22:12:53.006329 Dram Type= 6, Freq= 0, CH_1, rank 1
2045 22:12:53.009603 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2046 22:12:53.009686 ==
2047 22:12:53.013169 RX Vref Scan: 0
2048 22:12:53.013250
2049 22:12:53.016292 RX Vref 0 -> 0, step: 1
2050 22:12:53.016373
2051 22:12:53.016439 RX Delay -111 -> 252, step: 8
2052 22:12:53.023544 iDelay=209, Bit 0, Center 80 (-39 ~ 200) 240
2053 22:12:53.027066 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
2054 22:12:53.030225 iDelay=209, Bit 2, Center 64 (-55 ~ 184) 240
2055 22:12:53.033421 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
2056 22:12:53.039971 iDelay=209, Bit 4, Center 76 (-47 ~ 200) 248
2057 22:12:53.043010 iDelay=209, Bit 5, Center 88 (-31 ~ 208) 240
2058 22:12:53.046846 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
2059 22:12:53.049917 iDelay=209, Bit 7, Center 76 (-47 ~ 200) 248
2060 22:12:53.053559 iDelay=209, Bit 8, Center 60 (-63 ~ 184) 248
2061 22:12:53.059732 iDelay=209, Bit 9, Center 60 (-63 ~ 184) 248
2062 22:12:53.063250 iDelay=209, Bit 10, Center 80 (-39 ~ 200) 240
2063 22:12:53.066688 iDelay=209, Bit 11, Center 64 (-55 ~ 184) 240
2064 22:12:53.069775 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
2065 22:12:53.073452 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
2066 22:12:53.080075 iDelay=209, Bit 14, Center 76 (-47 ~ 200) 248
2067 22:12:53.083404 iDelay=209, Bit 15, Center 76 (-47 ~ 200) 248
2068 22:12:53.083511 ==
2069 22:12:53.086252 Dram Type= 6, Freq= 0, CH_1, rank 1
2070 22:12:53.089764 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2071 22:12:53.089847 ==
2072 22:12:53.093020 DQS Delay:
2073 22:12:53.093102 DQS0 = 0, DQS1 = 0
2074 22:12:53.093168 DQM Delay:
2075 22:12:53.096403 DQM0 = 77, DQM1 = 72
2076 22:12:53.096485 DQ Delay:
2077 22:12:53.099778 DQ0 =80, DQ1 =72, DQ2 =64, DQ3 =72
2078 22:12:53.102901 DQ4 =76, DQ5 =88, DQ6 =88, DQ7 =76
2079 22:12:53.106592 DQ8 =60, DQ9 =60, DQ10 =80, DQ11 =64
2080 22:12:53.109418 DQ12 =80, DQ13 =80, DQ14 =76, DQ15 =76
2081 22:12:53.109535
2082 22:12:53.109629
2083 22:12:53.119318 [DQSOSCAuto] RK1, (LSB)MR18= 0x233c, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 401 ps
2084 22:12:53.119456 CH1 RK1: MR19=606, MR18=233C
2085 22:12:53.126325 CH1_RK1: MR19=0x606, MR18=0x233C, DQSOSC=394, MR23=63, INC=95, DEC=63
2086 22:12:53.129483 [RxdqsGatingPostProcess] freq 800
2087 22:12:53.136145 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2088 22:12:53.139172 Pre-setting of DQS Precalculation
2089 22:12:53.142380 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2090 22:12:53.152625 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2091 22:12:53.159174 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2092 22:12:53.159283
2093 22:12:53.159378
2094 22:12:53.162224 [Calibration Summary] 1600 Mbps
2095 22:12:53.162326 CH 0, Rank 0
2096 22:12:53.165978 SW Impedance : PASS
2097 22:12:53.166078 DUTY Scan : NO K
2098 22:12:53.169518 ZQ Calibration : PASS
2099 22:12:53.172232 Jitter Meter : NO K
2100 22:12:53.172322 CBT Training : PASS
2101 22:12:53.175735 Write leveling : PASS
2102 22:12:53.178795 RX DQS gating : PASS
2103 22:12:53.178878 RX DQ/DQS(RDDQC) : PASS
2104 22:12:53.182595 TX DQ/DQS : PASS
2105 22:12:53.185455 RX DATLAT : PASS
2106 22:12:53.185585 RX DQ/DQS(Engine): PASS
2107 22:12:53.188896 TX OE : NO K
2108 22:12:53.188978 All Pass.
2109 22:12:53.189091
2110 22:12:53.192243 CH 0, Rank 1
2111 22:12:53.192324 SW Impedance : PASS
2112 22:12:53.195798 DUTY Scan : NO K
2113 22:12:53.199076 ZQ Calibration : PASS
2114 22:12:53.199157 Jitter Meter : NO K
2115 22:12:53.201850 CBT Training : PASS
2116 22:12:53.201931 Write leveling : PASS
2117 22:12:53.205111 RX DQS gating : PASS
2118 22:12:53.208477 RX DQ/DQS(RDDQC) : PASS
2119 22:12:53.208572 TX DQ/DQS : PASS
2120 22:12:53.211862 RX DATLAT : PASS
2121 22:12:53.215318 RX DQ/DQS(Engine): PASS
2122 22:12:53.215399 TX OE : NO K
2123 22:12:53.218327 All Pass.
2124 22:12:53.218408
2125 22:12:53.218473 CH 1, Rank 0
2126 22:12:53.221847 SW Impedance : PASS
2127 22:12:53.221929 DUTY Scan : NO K
2128 22:12:53.225416 ZQ Calibration : PASS
2129 22:12:53.228690 Jitter Meter : NO K
2130 22:12:53.228798 CBT Training : PASS
2131 22:12:53.232172 Write leveling : PASS
2132 22:12:53.235034 RX DQS gating : PASS
2133 22:12:53.235131 RX DQ/DQS(RDDQC) : PASS
2134 22:12:53.238258 TX DQ/DQS : PASS
2135 22:12:53.242074 RX DATLAT : PASS
2136 22:12:53.242174 RX DQ/DQS(Engine): PASS
2137 22:12:53.244928 TX OE : NO K
2138 22:12:53.245024 All Pass.
2139 22:12:53.245120
2140 22:12:53.248509 CH 1, Rank 1
2141 22:12:53.248610 SW Impedance : PASS
2142 22:12:53.251461 DUTY Scan : NO K
2143 22:12:53.255216 ZQ Calibration : PASS
2144 22:12:53.255286 Jitter Meter : NO K
2145 22:12:53.258190 CBT Training : PASS
2146 22:12:53.258284 Write leveling : PASS
2147 22:12:53.261770 RX DQS gating : PASS
2148 22:12:53.264796 RX DQ/DQS(RDDQC) : PASS
2149 22:12:53.264896 TX DQ/DQS : PASS
2150 22:12:53.268512 RX DATLAT : PASS
2151 22:12:53.271751 RX DQ/DQS(Engine): PASS
2152 22:12:53.271857 TX OE : NO K
2153 22:12:53.274834 All Pass.
2154 22:12:53.274909
2155 22:12:53.274972 DramC Write-DBI off
2156 22:12:53.278268 PER_BANK_REFRESH: Hybrid Mode
2157 22:12:53.281277 TX_TRACKING: ON
2158 22:12:53.285048 [GetDramInforAfterCalByMRR] Vendor 6.
2159 22:12:53.288195 [GetDramInforAfterCalByMRR] Revision 606.
2160 22:12:53.291777 [GetDramInforAfterCalByMRR] Revision 2 0.
2161 22:12:53.291881 MR0 0x3b3b
2162 22:12:53.291980 MR8 0x5151
2163 22:12:53.298038 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2164 22:12:53.298145
2165 22:12:53.298243 MR0 0x3b3b
2166 22:12:53.298339 MR8 0x5151
2167 22:12:53.301353 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2168 22:12:53.301451
2169 22:12:53.311351 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2170 22:12:53.314509 [FAST_K] Save calibration result to emmc
2171 22:12:53.318131 [FAST_K] Save calibration result to emmc
2172 22:12:53.321484 dram_init: config_dvfs: 1
2173 22:12:53.324462 dramc_set_vcore_voltage set vcore to 662500
2174 22:12:53.328156 Read voltage for 1200, 2
2175 22:12:53.328262 Vio18 = 0
2176 22:12:53.328353 Vcore = 662500
2177 22:12:53.331451 Vdram = 0
2178 22:12:53.331547 Vddq = 0
2179 22:12:53.331675 Vmddr = 0
2180 22:12:53.337716 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2181 22:12:53.340943 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2182 22:12:53.344235 MEM_TYPE=3, freq_sel=15
2183 22:12:53.347571 sv_algorithm_assistance_LP4_1600
2184 22:12:53.350892 ============ PULL DRAM RESETB DOWN ============
2185 22:12:53.357595 ========== PULL DRAM RESETB DOWN end =========
2186 22:12:53.360999 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2187 22:12:53.364107 ===================================
2188 22:12:53.367872 LPDDR4 DRAM CONFIGURATION
2189 22:12:53.370872 ===================================
2190 22:12:53.370976 EX_ROW_EN[0] = 0x0
2191 22:12:53.374531 EX_ROW_EN[1] = 0x0
2192 22:12:53.374635 LP4Y_EN = 0x0
2193 22:12:53.377401 WORK_FSP = 0x0
2194 22:12:53.377498 WL = 0x4
2195 22:12:53.380890 RL = 0x4
2196 22:12:53.380974 BL = 0x2
2197 22:12:53.383964 RPST = 0x0
2198 22:12:53.384046 RD_PRE = 0x0
2199 22:12:53.387725 WR_PRE = 0x1
2200 22:12:53.387808 WR_PST = 0x0
2201 22:12:53.390831 DBI_WR = 0x0
2202 22:12:53.394223 DBI_RD = 0x0
2203 22:12:53.394305 OTF = 0x1
2204 22:12:53.398026 ===================================
2205 22:12:53.400860 ===================================
2206 22:12:53.400943 ANA top config
2207 22:12:53.404161 ===================================
2208 22:12:53.407469 DLL_ASYNC_EN = 0
2209 22:12:53.410678 ALL_SLAVE_EN = 0
2210 22:12:53.414141 NEW_RANK_MODE = 1
2211 22:12:53.414240 DLL_IDLE_MODE = 1
2212 22:12:53.417441 LP45_APHY_COMB_EN = 1
2213 22:12:53.420633 TX_ODT_DIS = 1
2214 22:12:53.424168 NEW_8X_MODE = 1
2215 22:12:53.427571 ===================================
2216 22:12:53.430989 ===================================
2217 22:12:53.433883 data_rate = 2400
2218 22:12:53.437597 CKR = 1
2219 22:12:53.437679 DQ_P2S_RATIO = 8
2220 22:12:53.440462 ===================================
2221 22:12:53.443818 CA_P2S_RATIO = 8
2222 22:12:53.447515 DQ_CA_OPEN = 0
2223 22:12:53.450506 DQ_SEMI_OPEN = 0
2224 22:12:53.454114 CA_SEMI_OPEN = 0
2225 22:12:53.457457 CA_FULL_RATE = 0
2226 22:12:53.457540 DQ_CKDIV4_EN = 0
2227 22:12:53.460666 CA_CKDIV4_EN = 0
2228 22:12:53.464217 CA_PREDIV_EN = 0
2229 22:12:53.467319 PH8_DLY = 17
2230 22:12:53.470590 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2231 22:12:53.474374 DQ_AAMCK_DIV = 4
2232 22:12:53.474457 CA_AAMCK_DIV = 4
2233 22:12:53.477063 CA_ADMCK_DIV = 4
2234 22:12:53.480788 DQ_TRACK_CA_EN = 0
2235 22:12:53.484047 CA_PICK = 1200
2236 22:12:53.487021 CA_MCKIO = 1200
2237 22:12:53.490647 MCKIO_SEMI = 0
2238 22:12:53.493859 PLL_FREQ = 2366
2239 22:12:53.493942 DQ_UI_PI_RATIO = 32
2240 22:12:53.496970 CA_UI_PI_RATIO = 0
2241 22:12:53.500255 ===================================
2242 22:12:53.503897 ===================================
2243 22:12:53.506984 memory_type:LPDDR4
2244 22:12:53.510672 GP_NUM : 10
2245 22:12:53.510756 SRAM_EN : 1
2246 22:12:53.514106 MD32_EN : 0
2247 22:12:53.517318 ===================================
2248 22:12:53.520140 [ANA_INIT] >>>>>>>>>>>>>>
2249 22:12:53.520224 <<<<<< [CONFIGURE PHASE]: ANA_TX
2250 22:12:53.523544 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2251 22:12:53.526883 ===================================
2252 22:12:53.530565 data_rate = 2400,PCW = 0X5b00
2253 22:12:53.533390 ===================================
2254 22:12:53.537031 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2255 22:12:53.543704 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2256 22:12:53.549936 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2257 22:12:53.553233 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2258 22:12:53.556855 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2259 22:12:53.560259 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2260 22:12:53.563730 [ANA_INIT] flow start
2261 22:12:53.563814 [ANA_INIT] PLL >>>>>>>>
2262 22:12:53.566588 [ANA_INIT] PLL <<<<<<<<
2263 22:12:53.570305 [ANA_INIT] MIDPI >>>>>>>>
2264 22:12:53.573237 [ANA_INIT] MIDPI <<<<<<<<
2265 22:12:53.573321 [ANA_INIT] DLL >>>>>>>>
2266 22:12:53.576906 [ANA_INIT] DLL <<<<<<<<
2267 22:12:53.576990 [ANA_INIT] flow end
2268 22:12:53.583488 ============ LP4 DIFF to SE enter ============
2269 22:12:53.586592 ============ LP4 DIFF to SE exit ============
2270 22:12:53.589991 [ANA_INIT] <<<<<<<<<<<<<
2271 22:12:53.593022 [Flow] Enable top DCM control >>>>>
2272 22:12:53.596613 [Flow] Enable top DCM control <<<<<
2273 22:12:53.599821 Enable DLL master slave shuffle
2274 22:12:53.603502 ==============================================================
2275 22:12:53.606386 Gating Mode config
2276 22:12:53.609573 ==============================================================
2277 22:12:53.612828 Config description:
2278 22:12:53.622814 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2279 22:12:53.629617 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2280 22:12:53.632756 SELPH_MODE 0: By rank 1: By Phase
2281 22:12:53.639458 ==============================================================
2282 22:12:53.642598 GAT_TRACK_EN = 1
2283 22:12:53.646401 RX_GATING_MODE = 2
2284 22:12:53.649156 RX_GATING_TRACK_MODE = 2
2285 22:12:53.652757 SELPH_MODE = 1
2286 22:12:53.656345 PICG_EARLY_EN = 1
2287 22:12:53.656453 VALID_LAT_VALUE = 1
2288 22:12:53.662628 ==============================================================
2289 22:12:53.666128 Enter into Gating configuration >>>>
2290 22:12:53.669260 Exit from Gating configuration <<<<
2291 22:12:53.672798 Enter into DVFS_PRE_config >>>>>
2292 22:12:53.682520 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2293 22:12:53.685875 Exit from DVFS_PRE_config <<<<<
2294 22:12:53.689040 Enter into PICG configuration >>>>
2295 22:12:53.692520 Exit from PICG configuration <<<<
2296 22:12:53.696165 [RX_INPUT] configuration >>>>>
2297 22:12:53.699129 [RX_INPUT] configuration <<<<<
2298 22:12:53.705846 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2299 22:12:53.708946 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2300 22:12:53.715716 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2301 22:12:53.722476 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2302 22:12:53.729172 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2303 22:12:53.735406 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2304 22:12:53.738585 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2305 22:12:53.741901 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2306 22:12:53.745188 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2307 22:12:53.751838 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2308 22:12:53.755485 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2309 22:12:53.758990 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2310 22:12:53.761901 ===================================
2311 22:12:53.765310 LPDDR4 DRAM CONFIGURATION
2312 22:12:53.768619 ===================================
2313 22:12:53.768703 EX_ROW_EN[0] = 0x0
2314 22:12:53.771974 EX_ROW_EN[1] = 0x0
2315 22:12:53.775315 LP4Y_EN = 0x0
2316 22:12:53.775399 WORK_FSP = 0x0
2317 22:12:53.778883 WL = 0x4
2318 22:12:53.778968 RL = 0x4
2319 22:12:53.781831 BL = 0x2
2320 22:12:53.781920 RPST = 0x0
2321 22:12:53.785084 RD_PRE = 0x0
2322 22:12:53.785168 WR_PRE = 0x1
2323 22:12:53.788276 WR_PST = 0x0
2324 22:12:53.788361 DBI_WR = 0x0
2325 22:12:53.791808 DBI_RD = 0x0
2326 22:12:53.791892 OTF = 0x1
2327 22:12:53.795466 ===================================
2328 22:12:53.798484 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2329 22:12:53.805505 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2330 22:12:53.808539 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2331 22:12:53.812218 ===================================
2332 22:12:53.815217 LPDDR4 DRAM CONFIGURATION
2333 22:12:53.818714 ===================================
2334 22:12:53.818799 EX_ROW_EN[0] = 0x10
2335 22:12:53.821778 EX_ROW_EN[1] = 0x0
2336 22:12:53.821863 LP4Y_EN = 0x0
2337 22:12:53.825203 WORK_FSP = 0x0
2338 22:12:53.828643 WL = 0x4
2339 22:12:53.828728 RL = 0x4
2340 22:12:53.831877 BL = 0x2
2341 22:12:53.831961 RPST = 0x0
2342 22:12:53.835234 RD_PRE = 0x0
2343 22:12:53.835318 WR_PRE = 0x1
2344 22:12:53.838294 WR_PST = 0x0
2345 22:12:53.838377 DBI_WR = 0x0
2346 22:12:53.841835 DBI_RD = 0x0
2347 22:12:53.841953 OTF = 0x1
2348 22:12:53.845299 ===================================
2349 22:12:53.851734 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2350 22:12:53.851811 ==
2351 22:12:53.855334 Dram Type= 6, Freq= 0, CH_0, rank 0
2352 22:12:53.858243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2353 22:12:53.858321 ==
2354 22:12:53.861303 [Duty_Offset_Calibration]
2355 22:12:53.865035 B0:2 B1:0 CA:3
2356 22:12:53.865107
2357 22:12:53.868095 [DutyScan_Calibration_Flow] k_type=0
2358 22:12:53.876743
2359 22:12:53.876825 ==CLK 0==
2360 22:12:53.879397 Final CLK duty delay cell = 0
2361 22:12:53.882817 [0] MAX Duty = 5062%(X100), DQS PI = 28
2362 22:12:53.886210 [0] MIN Duty = 4906%(X100), DQS PI = 54
2363 22:12:53.886289 [0] AVG Duty = 4984%(X100)
2364 22:12:53.889537
2365 22:12:53.892646 CH0 CLK Duty spec in!! Max-Min= 156%
2366 22:12:53.896317 [DutyScan_Calibration_Flow] ====Done====
2367 22:12:53.896396
2368 22:12:53.899131 [DutyScan_Calibration_Flow] k_type=1
2369 22:12:53.914863
2370 22:12:53.914947 ==DQS 0 ==
2371 22:12:53.917939 Final DQS duty delay cell = 0
2372 22:12:53.921193 [0] MAX Duty = 5062%(X100), DQS PI = 12
2373 22:12:53.924786 [0] MIN Duty = 4907%(X100), DQS PI = 2
2374 22:12:53.924852 [0] AVG Duty = 4984%(X100)
2375 22:12:53.928421
2376 22:12:53.928496 ==DQS 1 ==
2377 22:12:53.931238 Final DQS duty delay cell = -4
2378 22:12:53.934595 [-4] MAX Duty = 5000%(X100), DQS PI = 36
2379 22:12:53.937905 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2380 22:12:53.941131 [-4] AVG Duty = 4937%(X100)
2381 22:12:53.941205
2382 22:12:53.944399 CH0 DQS 0 Duty spec in!! Max-Min= 155%
2383 22:12:53.944489
2384 22:12:53.947873 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2385 22:12:53.951085 [DutyScan_Calibration_Flow] ====Done====
2386 22:12:53.951159
2387 22:12:53.954377 [DutyScan_Calibration_Flow] k_type=3
2388 22:12:53.972391
2389 22:12:53.972472 ==DQM 0 ==
2390 22:12:53.975225 Final DQM duty delay cell = 0
2391 22:12:53.978484 [0] MAX Duty = 5124%(X100), DQS PI = 28
2392 22:12:53.982192 [0] MIN Duty = 4876%(X100), DQS PI = 0
2393 22:12:53.982271 [0] AVG Duty = 5000%(X100)
2394 22:12:53.985725
2395 22:12:53.985798 ==DQM 1 ==
2396 22:12:53.988957 Final DQM duty delay cell = 4
2397 22:12:53.991803 [4] MAX Duty = 5124%(X100), DQS PI = 0
2398 22:12:53.995428 [4] MIN Duty = 5031%(X100), DQS PI = 12
2399 22:12:53.995528 [4] AVG Duty = 5077%(X100)
2400 22:12:53.998571
2401 22:12:54.002156 CH0 DQM 0 Duty spec in!! Max-Min= 248%
2402 22:12:54.002224
2403 22:12:54.005769 CH0 DQM 1 Duty spec in!! Max-Min= 93%
2404 22:12:54.008737 [DutyScan_Calibration_Flow] ====Done====
2405 22:12:54.008818
2406 22:12:54.012421 [DutyScan_Calibration_Flow] k_type=2
2407 22:12:54.026870
2408 22:12:54.026948 ==DQ 0 ==
2409 22:12:54.029964 Final DQ duty delay cell = -4
2410 22:12:54.034227 [-4] MAX Duty = 5000%(X100), DQS PI = 8
2411 22:12:54.036810 [-4] MIN Duty = 4907%(X100), DQS PI = 54
2412 22:12:54.040201 [-4] AVG Duty = 4953%(X100)
2413 22:12:54.040271
2414 22:12:54.040339 ==DQ 1 ==
2415 22:12:54.043444 Final DQ duty delay cell = -4
2416 22:12:54.046735 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2417 22:12:54.050011 [-4] MIN Duty = 4876%(X100), DQS PI = 18
2418 22:12:54.053346 [-4] AVG Duty = 4938%(X100)
2419 22:12:54.053421
2420 22:12:54.056706 CH0 DQ 0 Duty spec in!! Max-Min= 93%
2421 22:12:54.056777
2422 22:12:54.060013 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2423 22:12:54.063517 [DutyScan_Calibration_Flow] ====Done====
2424 22:12:54.063636 ==
2425 22:12:54.066573 Dram Type= 6, Freq= 0, CH_1, rank 0
2426 22:12:54.069718 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2427 22:12:54.069786 ==
2428 22:12:54.073341 [Duty_Offset_Calibration]
2429 22:12:54.073411 B0:1 B1:-2 CA:0
2430 22:12:54.073474
2431 22:12:54.076530 [DutyScan_Calibration_Flow] k_type=0
2432 22:12:54.087644
2433 22:12:54.087720 ==CLK 0==
2434 22:12:54.090646 Final CLK duty delay cell = 0
2435 22:12:54.094201 [0] MAX Duty = 5031%(X100), DQS PI = 18
2436 22:12:54.096997 [0] MIN Duty = 4907%(X100), DQS PI = 0
2437 22:12:54.097086 [0] AVG Duty = 4969%(X100)
2438 22:12:54.100896
2439 22:12:54.103652 CH1 CLK Duty spec in!! Max-Min= 124%
2440 22:12:54.107243 [DutyScan_Calibration_Flow] ====Done====
2441 22:12:54.107320
2442 22:12:54.110104 [DutyScan_Calibration_Flow] k_type=1
2443 22:12:54.125943
2444 22:12:54.126017 ==DQS 0 ==
2445 22:12:54.128947 Final DQS duty delay cell = -4
2446 22:12:54.132535 [-4] MAX Duty = 5000%(X100), DQS PI = 24
2447 22:12:54.135728 [-4] MIN Duty = 4907%(X100), DQS PI = 4
2448 22:12:54.139220 [-4] AVG Duty = 4953%(X100)
2449 22:12:54.139293
2450 22:12:54.139354 ==DQS 1 ==
2451 22:12:54.142115 Final DQS duty delay cell = 0
2452 22:12:54.145458 [0] MAX Duty = 5093%(X100), DQS PI = 0
2453 22:12:54.149085 [0] MIN Duty = 4875%(X100), DQS PI = 26
2454 22:12:54.152311 [0] AVG Duty = 4984%(X100)
2455 22:12:54.152396
2456 22:12:54.155739 CH1 DQS 0 Duty spec in!! Max-Min= 93%
2457 22:12:54.155821
2458 22:12:54.159054 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2459 22:12:54.162327 [DutyScan_Calibration_Flow] ====Done====
2460 22:12:54.162400
2461 22:12:54.165615 [DutyScan_Calibration_Flow] k_type=3
2462 22:12:54.182481
2463 22:12:54.182564 ==DQM 0 ==
2464 22:12:54.185451 Final DQM duty delay cell = 0
2465 22:12:54.189108 [0] MAX Duty = 5031%(X100), DQS PI = 24
2466 22:12:54.192469 [0] MIN Duty = 4844%(X100), DQS PI = 52
2467 22:12:54.195593 [0] AVG Duty = 4937%(X100)
2468 22:12:54.195688
2469 22:12:54.195752 ==DQM 1 ==
2470 22:12:54.199018 Final DQM duty delay cell = 0
2471 22:12:54.202518 [0] MAX Duty = 5031%(X100), DQS PI = 36
2472 22:12:54.205427 [0] MIN Duty = 4907%(X100), DQS PI = 0
2473 22:12:54.208899 [0] AVG Duty = 4969%(X100)
2474 22:12:54.208994
2475 22:12:54.212206 CH1 DQM 0 Duty spec in!! Max-Min= 187%
2476 22:12:54.212287
2477 22:12:54.215728 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2478 22:12:54.218863 [DutyScan_Calibration_Flow] ====Done====
2479 22:12:54.218945
2480 22:12:54.221896 [DutyScan_Calibration_Flow] k_type=2
2481 22:12:54.238898
2482 22:12:54.238975 ==DQ 0 ==
2483 22:12:54.241954 Final DQ duty delay cell = 0
2484 22:12:54.245605 [0] MAX Duty = 5093%(X100), DQS PI = 20
2485 22:12:54.248424 [0] MIN Duty = 4938%(X100), DQS PI = 56
2486 22:12:54.248507 [0] AVG Duty = 5015%(X100)
2487 22:12:54.251818
2488 22:12:54.251893 ==DQ 1 ==
2489 22:12:54.255242 Final DQ duty delay cell = 0
2490 22:12:54.258376 [0] MAX Duty = 5125%(X100), DQS PI = 36
2491 22:12:54.262048 [0] MIN Duty = 4969%(X100), DQS PI = 26
2492 22:12:54.262144 [0] AVG Duty = 5047%(X100)
2493 22:12:54.262234
2494 22:12:54.265403 CH1 DQ 0 Duty spec in!! Max-Min= 155%
2495 22:12:54.268852
2496 22:12:54.272294 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2497 22:12:54.275384 [DutyScan_Calibration_Flow] ====Done====
2498 22:12:54.278705 nWR fixed to 30
2499 22:12:54.278785 [ModeRegInit_LP4] CH0 RK0
2500 22:12:54.281693 [ModeRegInit_LP4] CH0 RK1
2501 22:12:54.285244 [ModeRegInit_LP4] CH1 RK0
2502 22:12:54.288878 [ModeRegInit_LP4] CH1 RK1
2503 22:12:54.288956 match AC timing 7
2504 22:12:54.292247 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2505 22:12:54.298262 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2506 22:12:54.301763 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2507 22:12:54.308318 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2508 22:12:54.311907 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2509 22:12:54.311990 ==
2510 22:12:54.315180 Dram Type= 6, Freq= 0, CH_0, rank 0
2511 22:12:54.318771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2512 22:12:54.318863 ==
2513 22:12:54.325134 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2514 22:12:54.331417 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2515 22:12:54.338664 [CA 0] Center 40 (10~71) winsize 62
2516 22:12:54.342410 [CA 1] Center 40 (10~70) winsize 61
2517 22:12:54.345411 [CA 2] Center 36 (6~66) winsize 61
2518 22:12:54.349120 [CA 3] Center 35 (5~66) winsize 62
2519 22:12:54.352090 [CA 4] Center 34 (4~65) winsize 62
2520 22:12:54.355170 [CA 5] Center 33 (3~64) winsize 62
2521 22:12:54.355276
2522 22:12:54.358403 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2523 22:12:54.358486
2524 22:12:54.361893 [CATrainingPosCal] consider 1 rank data
2525 22:12:54.365142 u2DelayCellTimex100 = 270/100 ps
2526 22:12:54.368618 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2527 22:12:54.375175 CA1 delay=40 (10~70),Diff = 7 PI (33 cell)
2528 22:12:54.378507 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2529 22:12:54.381777 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2530 22:12:54.385140 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2531 22:12:54.388349 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2532 22:12:54.388425
2533 22:12:54.391942 CA PerBit enable=1, Macro0, CA PI delay=33
2534 22:12:54.392026
2535 22:12:54.395417 [CBTSetCACLKResult] CA Dly = 33
2536 22:12:54.398436 CS Dly: 7 (0~38)
2537 22:12:54.398517 ==
2538 22:12:54.402009 Dram Type= 6, Freq= 0, CH_0, rank 1
2539 22:12:54.404853 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2540 22:12:54.404924 ==
2541 22:12:54.411559 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2542 22:12:54.415074 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2543 22:12:54.424766 [CA 0] Center 40 (10~70) winsize 61
2544 22:12:54.428341 [CA 1] Center 40 (10~70) winsize 61
2545 22:12:54.431563 [CA 2] Center 35 (5~66) winsize 62
2546 22:12:54.435273 [CA 3] Center 35 (5~66) winsize 62
2547 22:12:54.438197 [CA 4] Center 34 (3~65) winsize 63
2548 22:12:54.441330 [CA 5] Center 33 (3~64) winsize 62
2549 22:12:54.441418
2550 22:12:54.444776 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2551 22:12:54.444855
2552 22:12:54.447812 [CATrainingPosCal] consider 2 rank data
2553 22:12:54.451546 u2DelayCellTimex100 = 270/100 ps
2554 22:12:54.458020 CA0 delay=40 (10~70),Diff = 7 PI (33 cell)
2555 22:12:54.461508 CA1 delay=40 (10~70),Diff = 7 PI (33 cell)
2556 22:12:54.464833 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2557 22:12:54.468246 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2558 22:12:54.471007 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2559 22:12:54.474331 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2560 22:12:54.474410
2561 22:12:54.478118 CA PerBit enable=1, Macro0, CA PI delay=33
2562 22:12:54.478204
2563 22:12:54.481517 [CBTSetCACLKResult] CA Dly = 33
2564 22:12:54.484681 CS Dly: 7 (0~39)
2565 22:12:54.484756
2566 22:12:54.488132 ----->DramcWriteLeveling(PI) begin...
2567 22:12:54.488214 ==
2568 22:12:54.490872 Dram Type= 6, Freq= 0, CH_0, rank 0
2569 22:12:54.494483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2570 22:12:54.494558 ==
2571 22:12:54.497844 Write leveling (Byte 0): 33 => 33
2572 22:12:54.501164 Write leveling (Byte 1): 29 => 29
2573 22:12:54.504582 DramcWriteLeveling(PI) end<-----
2574 22:12:54.504658
2575 22:12:54.504785 ==
2576 22:12:54.507682 Dram Type= 6, Freq= 0, CH_0, rank 0
2577 22:12:54.511388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2578 22:12:54.511461 ==
2579 22:12:54.514591 [Gating] SW mode calibration
2580 22:12:54.521016 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2581 22:12:54.527615 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2582 22:12:54.531169 0 15 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
2583 22:12:54.534100 0 15 4 | B1->B0 | 2626 3232 | 0 1 | (0 0) (1 1)
2584 22:12:54.540718 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2585 22:12:54.544352 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2586 22:12:54.547300 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2587 22:12:54.553954 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2588 22:12:54.557478 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2589 22:12:54.561096 0 15 28 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
2590 22:12:54.567687 1 0 0 | B1->B0 | 3232 2525 | 1 0 | (1 0) (1 0)
2591 22:12:54.570471 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2592 22:12:54.573697 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2593 22:12:54.580372 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2594 22:12:54.583931 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2595 22:12:54.587276 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2596 22:12:54.594192 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2597 22:12:54.597395 1 0 28 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
2598 22:12:54.600652 1 1 0 | B1->B0 | 2a2a 3838 | 0 0 | (0 0) (0 0)
2599 22:12:54.607273 1 1 4 | B1->B0 | 4141 4646 | 1 0 | (0 0) (0 0)
2600 22:12:54.610585 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2601 22:12:54.614345 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2602 22:12:54.620285 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2603 22:12:54.623746 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2604 22:12:54.627294 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2605 22:12:54.633695 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2606 22:12:54.637015 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2607 22:12:54.640339 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2608 22:12:54.647056 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2609 22:12:54.650203 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2610 22:12:54.653904 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2611 22:12:54.659928 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2612 22:12:54.663478 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2613 22:12:54.667112 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2614 22:12:54.673533 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2615 22:12:54.676607 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2616 22:12:54.679900 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2617 22:12:54.686707 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2618 22:12:54.690255 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2619 22:12:54.693230 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2620 22:12:54.699941 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2621 22:12:54.703492 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2622 22:12:54.706707 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2623 22:12:54.712843 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2624 22:12:54.712926 Total UI for P1: 0, mck2ui 16
2625 22:12:54.716145 best dqsien dly found for B0: ( 1, 3, 30)
2626 22:12:54.723101 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2627 22:12:54.726123 Total UI for P1: 0, mck2ui 16
2628 22:12:54.729536 best dqsien dly found for B1: ( 1, 4, 2)
2629 22:12:54.732931 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2630 22:12:54.736424 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2631 22:12:54.736506
2632 22:12:54.739481 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2633 22:12:54.742673 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2634 22:12:54.746277 [Gating] SW calibration Done
2635 22:12:54.746359 ==
2636 22:12:54.749718 Dram Type= 6, Freq= 0, CH_0, rank 0
2637 22:12:54.752468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2638 22:12:54.752549 ==
2639 22:12:54.756292 RX Vref Scan: 0
2640 22:12:54.756380
2641 22:12:54.759194 RX Vref 0 -> 0, step: 1
2642 22:12:54.759300
2643 22:12:54.759393 RX Delay -40 -> 252, step: 8
2644 22:12:54.765954 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
2645 22:12:54.769441 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2646 22:12:54.772472 iDelay=200, Bit 2, Center 111 (32 ~ 191) 160
2647 22:12:54.775740 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2648 22:12:54.779304 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2649 22:12:54.785640 iDelay=200, Bit 5, Center 99 (24 ~ 175) 152
2650 22:12:54.789222 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2651 22:12:54.792595 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2652 22:12:54.795683 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2653 22:12:54.799121 iDelay=200, Bit 9, Center 87 (8 ~ 167) 160
2654 22:12:54.805483 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2655 22:12:54.809113 iDelay=200, Bit 11, Center 99 (24 ~ 175) 152
2656 22:12:54.812141 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2657 22:12:54.815593 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
2658 22:12:54.818757 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
2659 22:12:54.825732 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2660 22:12:54.825814 ==
2661 22:12:54.829357 Dram Type= 6, Freq= 0, CH_0, rank 0
2662 22:12:54.832511 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2663 22:12:54.832591 ==
2664 22:12:54.832657 DQS Delay:
2665 22:12:54.835946 DQS0 = 0, DQS1 = 0
2666 22:12:54.836021 DQM Delay:
2667 22:12:54.838802 DQM0 = 112, DQM1 = 103
2668 22:12:54.838880 DQ Delay:
2669 22:12:54.842662 DQ0 =111, DQ1 =115, DQ2 =111, DQ3 =107
2670 22:12:54.845598 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2671 22:12:54.848930 DQ8 =95, DQ9 =87, DQ10 =103, DQ11 =99
2672 22:12:54.851975 DQ12 =111, DQ13 =107, DQ14 =115, DQ15 =111
2673 22:12:54.852052
2674 22:12:54.852120
2675 22:12:54.852179 ==
2676 22:12:54.855226 Dram Type= 6, Freq= 0, CH_0, rank 0
2677 22:12:54.861853 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2678 22:12:54.861931 ==
2679 22:12:54.862015
2680 22:12:54.862135
2681 22:12:54.862225 TX Vref Scan disable
2682 22:12:54.865664 == TX Byte 0 ==
2683 22:12:54.869278 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2684 22:12:54.872797 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2685 22:12:54.875836 == TX Byte 1 ==
2686 22:12:54.879510 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2687 22:12:54.882591 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2688 22:12:54.886244 ==
2689 22:12:54.889271 Dram Type= 6, Freq= 0, CH_0, rank 0
2690 22:12:54.892612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2691 22:12:54.892687 ==
2692 22:12:54.904034 TX Vref=22, minBit 6, minWin=25, winSum=418
2693 22:12:54.907220 TX Vref=24, minBit 6, minWin=25, winSum=421
2694 22:12:54.910637 TX Vref=26, minBit 2, minWin=26, winSum=426
2695 22:12:54.914057 TX Vref=28, minBit 3, minWin=26, winSum=432
2696 22:12:54.917328 TX Vref=30, minBit 10, minWin=26, winSum=433
2697 22:12:54.923950 TX Vref=32, minBit 1, minWin=26, winSum=430
2698 22:12:54.927405 [TxChooseVref] Worse bit 10, Min win 26, Win sum 433, Final Vref 30
2699 22:12:54.927481
2700 22:12:54.930664 Final TX Range 1 Vref 30
2701 22:12:54.930737
2702 22:12:54.930802 ==
2703 22:12:54.934068 Dram Type= 6, Freq= 0, CH_0, rank 0
2704 22:12:54.937113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2705 22:12:54.937187 ==
2706 22:12:54.940749
2707 22:12:54.940825
2708 22:12:54.940889 TX Vref Scan disable
2709 22:12:54.943725 == TX Byte 0 ==
2710 22:12:54.947088 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2711 22:12:54.953869 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2712 22:12:54.953947 == TX Byte 1 ==
2713 22:12:54.957521 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2714 22:12:54.963513 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2715 22:12:54.963636
2716 22:12:54.963702 [DATLAT]
2717 22:12:54.963763 Freq=1200, CH0 RK0
2718 22:12:54.963825
2719 22:12:54.967125 DATLAT Default: 0xd
2720 22:12:54.967203 0, 0xFFFF, sum = 0
2721 22:12:54.970788 1, 0xFFFF, sum = 0
2722 22:12:54.970874 2, 0xFFFF, sum = 0
2723 22:12:54.973889 3, 0xFFFF, sum = 0
2724 22:12:54.977505 4, 0xFFFF, sum = 0
2725 22:12:54.977583 5, 0xFFFF, sum = 0
2726 22:12:54.980336 6, 0xFFFF, sum = 0
2727 22:12:54.980414 7, 0xFFFF, sum = 0
2728 22:12:54.984083 8, 0xFFFF, sum = 0
2729 22:12:54.984159 9, 0xFFFF, sum = 0
2730 22:12:54.987229 10, 0xFFFF, sum = 0
2731 22:12:54.987307 11, 0xFFFF, sum = 0
2732 22:12:54.990747 12, 0x0, sum = 1
2733 22:12:54.990823 13, 0x0, sum = 2
2734 22:12:54.993712 14, 0x0, sum = 3
2735 22:12:54.993789 15, 0x0, sum = 4
2736 22:12:54.997097 best_step = 13
2737 22:12:54.997170
2738 22:12:54.997235 ==
2739 22:12:55.000075 Dram Type= 6, Freq= 0, CH_0, rank 0
2740 22:12:55.003554 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2741 22:12:55.003653 ==
2742 22:12:55.003721 RX Vref Scan: 1
2743 22:12:55.003784
2744 22:12:55.007262 Set Vref Range= 32 -> 127
2745 22:12:55.007335
2746 22:12:55.009976 RX Vref 32 -> 127, step: 1
2747 22:12:55.010056
2748 22:12:55.013615 RX Delay -37 -> 252, step: 4
2749 22:12:55.013689
2750 22:12:55.016971 Set Vref, RX VrefLevel [Byte0]: 32
2751 22:12:55.020378 [Byte1]: 32
2752 22:12:55.020454
2753 22:12:55.023304 Set Vref, RX VrefLevel [Byte0]: 33
2754 22:12:55.026426 [Byte1]: 33
2755 22:12:55.030706
2756 22:12:55.030783 Set Vref, RX VrefLevel [Byte0]: 34
2757 22:12:55.033763 [Byte1]: 34
2758 22:12:55.038529
2759 22:12:55.038603 Set Vref, RX VrefLevel [Byte0]: 35
2760 22:12:55.041608 [Byte1]: 35
2761 22:12:55.046542
2762 22:12:55.046616 Set Vref, RX VrefLevel [Byte0]: 36
2763 22:12:55.050204 [Byte1]: 36
2764 22:12:55.054802
2765 22:12:55.054883 Set Vref, RX VrefLevel [Byte0]: 37
2766 22:12:55.057544 [Byte1]: 37
2767 22:12:55.062463
2768 22:12:55.062538 Set Vref, RX VrefLevel [Byte0]: 38
2769 22:12:55.065996 [Byte1]: 38
2770 22:12:55.070652
2771 22:12:55.070736 Set Vref, RX VrefLevel [Byte0]: 39
2772 22:12:55.073786 [Byte1]: 39
2773 22:12:55.078553
2774 22:12:55.078637 Set Vref, RX VrefLevel [Byte0]: 40
2775 22:12:55.082132 [Byte1]: 40
2776 22:12:55.086344
2777 22:12:55.086428 Set Vref, RX VrefLevel [Byte0]: 41
2778 22:12:55.090074 [Byte1]: 41
2779 22:12:55.094337
2780 22:12:55.094421 Set Vref, RX VrefLevel [Byte0]: 42
2781 22:12:55.097992 [Byte1]: 42
2782 22:12:55.102702
2783 22:12:55.102785 Set Vref, RX VrefLevel [Byte0]: 43
2784 22:12:55.105561 [Byte1]: 43
2785 22:12:55.110769
2786 22:12:55.110853 Set Vref, RX VrefLevel [Byte0]: 44
2787 22:12:55.114000 [Byte1]: 44
2788 22:12:55.118524
2789 22:12:55.118606 Set Vref, RX VrefLevel [Byte0]: 45
2790 22:12:55.121725 [Byte1]: 45
2791 22:12:55.126414
2792 22:12:55.126496 Set Vref, RX VrefLevel [Byte0]: 46
2793 22:12:55.129848 [Byte1]: 46
2794 22:12:55.134282
2795 22:12:55.134363 Set Vref, RX VrefLevel [Byte0]: 47
2796 22:12:55.138036 [Byte1]: 47
2797 22:12:55.142650
2798 22:12:55.142732 Set Vref, RX VrefLevel [Byte0]: 48
2799 22:12:55.146218 [Byte1]: 48
2800 22:12:55.150272
2801 22:12:55.150353 Set Vref, RX VrefLevel [Byte0]: 49
2802 22:12:55.153914 [Byte1]: 49
2803 22:12:55.158724
2804 22:12:55.158806 Set Vref, RX VrefLevel [Byte0]: 50
2805 22:12:55.161643 [Byte1]: 50
2806 22:12:55.166412
2807 22:12:55.166494 Set Vref, RX VrefLevel [Byte0]: 51
2808 22:12:55.170153 [Byte1]: 51
2809 22:12:55.174587
2810 22:12:55.174668 Set Vref, RX VrefLevel [Byte0]: 52
2811 22:12:55.178272 [Byte1]: 52
2812 22:12:55.182308
2813 22:12:55.182391 Set Vref, RX VrefLevel [Byte0]: 53
2814 22:12:55.186196 [Byte1]: 53
2815 22:12:55.190433
2816 22:12:55.193978 Set Vref, RX VrefLevel [Byte0]: 54
2817 22:12:55.194060 [Byte1]: 54
2818 22:12:55.198412
2819 22:12:55.198494 Set Vref, RX VrefLevel [Byte0]: 55
2820 22:12:55.201953 [Byte1]: 55
2821 22:12:55.206312
2822 22:12:55.206393 Set Vref, RX VrefLevel [Byte0]: 56
2823 22:12:55.210017 [Byte1]: 56
2824 22:12:55.214709
2825 22:12:55.214790 Set Vref, RX VrefLevel [Byte0]: 57
2826 22:12:55.217798 [Byte1]: 57
2827 22:12:55.222401
2828 22:12:55.222514 Set Vref, RX VrefLevel [Byte0]: 58
2829 22:12:55.225622 [Byte1]: 58
2830 22:12:55.230709
2831 22:12:55.230790 Set Vref, RX VrefLevel [Byte0]: 59
2832 22:12:55.234052 [Byte1]: 59
2833 22:12:55.238638
2834 22:12:55.238739 Set Vref, RX VrefLevel [Byte0]: 60
2835 22:12:55.241973 [Byte1]: 60
2836 22:12:55.246327
2837 22:12:55.246474 Set Vref, RX VrefLevel [Byte0]: 61
2838 22:12:55.249630 [Byte1]: 61
2839 22:12:55.254471
2840 22:12:55.254621 Set Vref, RX VrefLevel [Byte0]: 62
2841 22:12:55.257545 [Byte1]: 62
2842 22:12:55.262321
2843 22:12:55.262403 Set Vref, RX VrefLevel [Byte0]: 63
2844 22:12:55.265883 [Byte1]: 63
2845 22:12:55.270807
2846 22:12:55.270887 Set Vref, RX VrefLevel [Byte0]: 64
2847 22:12:55.273768 [Byte1]: 64
2848 22:12:55.278723
2849 22:12:55.278805 Set Vref, RX VrefLevel [Byte0]: 65
2850 22:12:55.281964 [Byte1]: 65
2851 22:12:55.286815
2852 22:12:55.286897 Set Vref, RX VrefLevel [Byte0]: 66
2853 22:12:55.292685 [Byte1]: 66
2854 22:12:55.292767
2855 22:12:55.296468 Set Vref, RX VrefLevel [Byte0]: 67
2856 22:12:55.299397 [Byte1]: 67
2857 22:12:55.299478
2858 22:12:55.303056 Set Vref, RX VrefLevel [Byte0]: 68
2859 22:12:55.306056 [Byte1]: 68
2860 22:12:55.310627
2861 22:12:55.310709 Set Vref, RX VrefLevel [Byte0]: 69
2862 22:12:55.313735 [Byte1]: 69
2863 22:12:55.318553
2864 22:12:55.318693 Set Vref, RX VrefLevel [Byte0]: 70
2865 22:12:55.322296 [Byte1]: 70
2866 22:12:55.326741
2867 22:12:55.326822 Set Vref, RX VrefLevel [Byte0]: 71
2868 22:12:55.329556 [Byte1]: 71
2869 22:12:55.334396
2870 22:12:55.334525 Set Vref, RX VrefLevel [Byte0]: 72
2871 22:12:55.337614 [Byte1]: 72
2872 22:12:55.342840
2873 22:12:55.342921 Set Vref, RX VrefLevel [Byte0]: 73
2874 22:12:55.346276 [Byte1]: 73
2875 22:12:55.350673
2876 22:12:55.350755 Set Vref, RX VrefLevel [Byte0]: 74
2877 22:12:55.354067 [Byte1]: 74
2878 22:12:55.358570
2879 22:12:55.358652 Final RX Vref Byte 0 = 61 to rank0
2880 22:12:55.362160 Final RX Vref Byte 1 = 53 to rank0
2881 22:12:55.365172 Final RX Vref Byte 0 = 61 to rank1
2882 22:12:55.368160 Final RX Vref Byte 1 = 53 to rank1==
2883 22:12:55.371659 Dram Type= 6, Freq= 0, CH_0, rank 0
2884 22:12:55.378587 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2885 22:12:55.378673 ==
2886 22:12:55.378740 DQS Delay:
2887 22:12:55.378802 DQS0 = 0, DQS1 = 0
2888 22:12:55.381461 DQM Delay:
2889 22:12:55.381543 DQM0 = 111, DQM1 = 101
2890 22:12:55.384898 DQ Delay:
2891 22:12:55.388700 DQ0 =112, DQ1 =110, DQ2 =110, DQ3 =108
2892 22:12:55.391620 DQ4 =112, DQ5 =104, DQ6 =118, DQ7 =120
2893 22:12:55.394809 DQ8 =92, DQ9 =84, DQ10 =104, DQ11 =94
2894 22:12:55.398333 DQ12 =106, DQ13 =106, DQ14 =116, DQ15 =110
2895 22:12:55.398418
2896 22:12:55.398483
2897 22:12:55.408185 [DQSOSCAuto] RK0, (LSB)MR18= 0xfafa, (MSB)MR19= 0x303, tDQSOscB0 = 412 ps tDQSOscB1 = 412 ps
2898 22:12:55.408279 CH0 RK0: MR19=303, MR18=FAFA
2899 22:12:55.414681 CH0_RK0: MR19=0x303, MR18=0xFAFA, DQSOSC=412, MR23=63, INC=38, DEC=25
2900 22:12:55.414764
2901 22:12:55.418101 ----->DramcWriteLeveling(PI) begin...
2902 22:12:55.418185 ==
2903 22:12:55.421298 Dram Type= 6, Freq= 0, CH_0, rank 1
2904 22:12:55.427825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2905 22:12:55.427908 ==
2906 22:12:55.431324 Write leveling (Byte 0): 33 => 33
2907 22:12:55.431406 Write leveling (Byte 1): 28 => 28
2908 22:12:55.434538 DramcWriteLeveling(PI) end<-----
2909 22:12:55.434620
2910 22:12:55.437793 ==
2911 22:12:55.437875 Dram Type= 6, Freq= 0, CH_0, rank 1
2912 22:12:55.445077 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2913 22:12:55.445160 ==
2914 22:12:55.447922 [Gating] SW mode calibration
2915 22:12:55.454906 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2916 22:12:55.457813 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2917 22:12:55.464632 0 15 0 | B1->B0 | 2c2c 3434 | 1 1 | (0 0) (1 1)
2918 22:12:55.467683 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2919 22:12:55.471484 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2920 22:12:55.477960 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2921 22:12:55.481027 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2922 22:12:55.484585 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2923 22:12:55.490781 0 15 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
2924 22:12:55.494183 0 15 28 | B1->B0 | 3434 2424 | 1 0 | (1 1) (0 0)
2925 22:12:55.497674 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2926 22:12:55.504435 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2927 22:12:55.507542 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2928 22:12:55.510933 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2929 22:12:55.517544 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2930 22:12:55.520889 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2931 22:12:55.523921 1 0 24 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
2932 22:12:55.530842 1 0 28 | B1->B0 | 2323 4444 | 0 0 | (0 0) (0 0)
2933 22:12:55.534277 1 1 0 | B1->B0 | 4141 4646 | 1 0 | (0 0) (0 0)
2934 22:12:55.537330 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2935 22:12:55.544154 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2936 22:12:55.547263 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2937 22:12:55.550728 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2938 22:12:55.554205 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2939 22:12:55.560652 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2940 22:12:55.564090 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2941 22:12:55.567249 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2942 22:12:55.573624 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2943 22:12:55.577344 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2944 22:12:55.580432 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2945 22:12:55.586935 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2946 22:12:55.590311 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2947 22:12:55.593774 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2948 22:12:55.600088 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2949 22:12:55.603665 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2950 22:12:55.606574 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2951 22:12:55.613427 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2952 22:12:55.616966 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2953 22:12:55.620245 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2954 22:12:55.626818 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2955 22:12:55.629899 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2956 22:12:55.632907 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2957 22:12:55.639679 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2958 22:12:55.643031 Total UI for P1: 0, mck2ui 16
2959 22:12:55.646478 best dqsien dly found for B0: ( 1, 3, 28)
2960 22:12:55.649754 Total UI for P1: 0, mck2ui 16
2961 22:12:55.652861 best dqsien dly found for B1: ( 1, 3, 30)
2962 22:12:55.656368 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2963 22:12:55.659639 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2964 22:12:55.659721
2965 22:12:55.662908 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2966 22:12:55.666304 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2967 22:12:55.669633 [Gating] SW calibration Done
2968 22:12:55.669714 ==
2969 22:12:55.672940 Dram Type= 6, Freq= 0, CH_0, rank 1
2970 22:12:55.676258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2971 22:12:55.676341 ==
2972 22:12:55.679292 RX Vref Scan: 0
2973 22:12:55.679374
2974 22:12:55.679439 RX Vref 0 -> 0, step: 1
2975 22:12:55.682891
2976 22:12:55.682973 RX Delay -40 -> 252, step: 8
2977 22:12:55.689589 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2978 22:12:55.692524 iDelay=200, Bit 1, Center 111 (32 ~ 191) 160
2979 22:12:55.696009 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2980 22:12:55.699488 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2981 22:12:55.702986 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2982 22:12:55.709291 iDelay=200, Bit 5, Center 99 (32 ~ 167) 136
2983 22:12:55.712825 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
2984 22:12:55.716663 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2985 22:12:55.719652 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2986 22:12:55.722653 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
2987 22:12:55.725721 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2988 22:12:55.732808 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2989 22:12:55.735773 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2990 22:12:55.739333 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2991 22:12:55.742459 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
2992 22:12:55.745773 iDelay=200, Bit 15, Center 107 (32 ~ 183) 152
2993 22:12:55.749367 ==
2994 22:12:55.752754 Dram Type= 6, Freq= 0, CH_0, rank 1
2995 22:12:55.756142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2996 22:12:55.756238 ==
2997 22:12:55.756303 DQS Delay:
2998 22:12:55.758892 DQS0 = 0, DQS1 = 0
2999 22:12:55.758973 DQM Delay:
3000 22:12:55.762559 DQM0 = 112, DQM1 = 101
3001 22:12:55.762645 DQ Delay:
3002 22:12:55.765612 DQ0 =111, DQ1 =111, DQ2 =111, DQ3 =107
3003 22:12:55.768909 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
3004 22:12:55.772194 DQ8 =91, DQ9 =83, DQ10 =103, DQ11 =95
3005 22:12:55.775820 DQ12 =111, DQ13 =111, DQ14 =111, DQ15 =107
3006 22:12:55.775902
3007 22:12:55.775967
3008 22:12:55.776026 ==
3009 22:12:55.779094 Dram Type= 6, Freq= 0, CH_0, rank 1
3010 22:12:55.785822 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3011 22:12:55.785905 ==
3012 22:12:55.785970
3013 22:12:55.786031
3014 22:12:55.786089 TX Vref Scan disable
3015 22:12:55.789509 == TX Byte 0 ==
3016 22:12:55.792282 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3017 22:12:55.798820 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3018 22:12:55.798902 == TX Byte 1 ==
3019 22:12:55.802196 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3020 22:12:55.809012 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3021 22:12:55.809094 ==
3022 22:12:55.812364 Dram Type= 6, Freq= 0, CH_0, rank 1
3023 22:12:55.815418 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3024 22:12:55.815501 ==
3025 22:12:55.827423 TX Vref=22, minBit 1, minWin=26, winSum=422
3026 22:12:55.830428 TX Vref=24, minBit 9, minWin=25, winSum=428
3027 22:12:55.833937 TX Vref=26, minBit 9, minWin=26, winSum=431
3028 22:12:55.837521 TX Vref=28, minBit 8, minWin=25, winSum=435
3029 22:12:55.840610 TX Vref=30, minBit 8, minWin=25, winSum=436
3030 22:12:55.847308 TX Vref=32, minBit 8, minWin=26, winSum=436
3031 22:12:55.850936 [TxChooseVref] Worse bit 8, Min win 26, Win sum 436, Final Vref 32
3032 22:12:55.851019
3033 22:12:55.854055 Final TX Range 1 Vref 32
3034 22:12:55.854138
3035 22:12:55.854205 ==
3036 22:12:55.857284 Dram Type= 6, Freq= 0, CH_0, rank 1
3037 22:12:55.860763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3038 22:12:55.860846 ==
3039 22:12:55.863765
3040 22:12:55.863846
3041 22:12:55.863912 TX Vref Scan disable
3042 22:12:55.867534 == TX Byte 0 ==
3043 22:12:55.871037 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3044 22:12:55.877409 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3045 22:12:55.877491 == TX Byte 1 ==
3046 22:12:55.880280 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3047 22:12:55.886921 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3048 22:12:55.887035
3049 22:12:55.887132 [DATLAT]
3050 22:12:55.887225 Freq=1200, CH0 RK1
3051 22:12:55.887321
3052 22:12:55.890218 DATLAT Default: 0xd
3053 22:12:55.890324 0, 0xFFFF, sum = 0
3054 22:12:55.893996 1, 0xFFFF, sum = 0
3055 22:12:55.897028 2, 0xFFFF, sum = 0
3056 22:12:55.897135 3, 0xFFFF, sum = 0
3057 22:12:55.900055 4, 0xFFFF, sum = 0
3058 22:12:55.900154 5, 0xFFFF, sum = 0
3059 22:12:55.903547 6, 0xFFFF, sum = 0
3060 22:12:55.903637 7, 0xFFFF, sum = 0
3061 22:12:55.906978 8, 0xFFFF, sum = 0
3062 22:12:55.907077 9, 0xFFFF, sum = 0
3063 22:12:55.910392 10, 0xFFFF, sum = 0
3064 22:12:55.910501 11, 0xFFFF, sum = 0
3065 22:12:55.913534 12, 0x0, sum = 1
3066 22:12:55.913640 13, 0x0, sum = 2
3067 22:12:55.917284 14, 0x0, sum = 3
3068 22:12:55.917396 15, 0x0, sum = 4
3069 22:12:55.917493 best_step = 13
3070 22:12:55.920296
3071 22:12:55.920398 ==
3072 22:12:55.923831 Dram Type= 6, Freq= 0, CH_0, rank 1
3073 22:12:55.926714 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3074 22:12:55.926813 ==
3075 22:12:55.926903 RX Vref Scan: 0
3076 22:12:55.927002
3077 22:12:55.930509 RX Vref 0 -> 0, step: 1
3078 22:12:55.930614
3079 22:12:55.933619 RX Delay -37 -> 252, step: 4
3080 22:12:55.937082 iDelay=195, Bit 0, Center 108 (39 ~ 178) 140
3081 22:12:55.943495 iDelay=195, Bit 1, Center 112 (43 ~ 182) 140
3082 22:12:55.946816 iDelay=195, Bit 2, Center 108 (39 ~ 178) 140
3083 22:12:55.950292 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3084 22:12:55.953283 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3085 22:12:55.956777 iDelay=195, Bit 5, Center 100 (35 ~ 166) 132
3086 22:12:55.963446 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3087 22:12:55.966966 iDelay=195, Bit 7, Center 118 (47 ~ 190) 144
3088 22:12:55.970230 iDelay=195, Bit 8, Center 90 (19 ~ 162) 144
3089 22:12:55.973468 iDelay=195, Bit 9, Center 84 (15 ~ 154) 140
3090 22:12:55.976913 iDelay=195, Bit 10, Center 104 (35 ~ 174) 140
3091 22:12:55.983379 iDelay=195, Bit 11, Center 94 (27 ~ 162) 136
3092 22:12:55.986650 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3093 22:12:55.990084 iDelay=195, Bit 13, Center 108 (39 ~ 178) 140
3094 22:12:55.993300 iDelay=195, Bit 14, Center 114 (47 ~ 182) 136
3095 22:12:55.996994 iDelay=195, Bit 15, Center 110 (43 ~ 178) 136
3096 22:12:55.999983 ==
3097 22:12:56.002990 Dram Type= 6, Freq= 0, CH_0, rank 1
3098 22:12:56.006439 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3099 22:12:56.006547 ==
3100 22:12:56.006639 DQS Delay:
3101 22:12:56.009522 DQS0 = 0, DQS1 = 0
3102 22:12:56.009632 DQM Delay:
3103 22:12:56.013207 DQM0 = 110, DQM1 = 101
3104 22:12:56.013304 DQ Delay:
3105 22:12:56.016187 DQ0 =108, DQ1 =112, DQ2 =108, DQ3 =108
3106 22:12:56.023434 DQ4 =112, DQ5 =100, DQ6 =120, DQ7 =118
3107 22:12:56.023562 DQ8 =90, DQ9 =84, DQ10 =104, DQ11 =94
3108 22:12:56.026057 DQ12 =110, DQ13 =108, DQ14 =114, DQ15 =110
3109 22:12:56.026158
3110 22:12:56.026248
3111 22:12:56.036399 [DQSOSCAuto] RK1, (LSB)MR18= 0x17fe, (MSB)MR19= 0x403, tDQSOscB0 = 410 ps tDQSOscB1 = 401 ps
3112 22:12:56.040012 CH0 RK1: MR19=403, MR18=17FE
3113 22:12:56.042852 CH0_RK1: MR19=0x403, MR18=0x17FE, DQSOSC=401, MR23=63, INC=40, DEC=27
3114 22:12:56.046600 [RxdqsGatingPostProcess] freq 1200
3115 22:12:56.053194 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3116 22:12:56.056153 best DQS0 dly(2T, 0.5T) = (0, 11)
3117 22:12:56.059166 best DQS1 dly(2T, 0.5T) = (0, 12)
3118 22:12:56.062842 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3119 22:12:56.065947 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3120 22:12:56.069411 best DQS0 dly(2T, 0.5T) = (0, 11)
3121 22:12:56.072710 best DQS1 dly(2T, 0.5T) = (0, 11)
3122 22:12:56.076296 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3123 22:12:56.079539 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3124 22:12:56.082298 Pre-setting of DQS Precalculation
3125 22:12:56.085816 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3126 22:12:56.085918 ==
3127 22:12:56.089094 Dram Type= 6, Freq= 0, CH_1, rank 0
3128 22:12:56.092539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3129 22:12:56.092638 ==
3130 22:12:56.099059 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3131 22:12:56.105620 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3132 22:12:56.113438 [CA 0] Center 37 (7~67) winsize 61
3133 22:12:56.116609 [CA 1] Center 37 (7~68) winsize 62
3134 22:12:56.120210 [CA 2] Center 34 (4~64) winsize 61
3135 22:12:56.123394 [CA 3] Center 34 (4~64) winsize 61
3136 22:12:56.126982 [CA 4] Center 34 (4~64) winsize 61
3137 22:12:56.130305 [CA 5] Center 33 (3~63) winsize 61
3138 22:12:56.130405
3139 22:12:56.133431 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3140 22:12:56.133531
3141 22:12:56.136488 [CATrainingPosCal] consider 1 rank data
3142 22:12:56.140382 u2DelayCellTimex100 = 270/100 ps
3143 22:12:56.143309 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3144 22:12:56.149682 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3145 22:12:56.153025 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3146 22:12:56.156279 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3147 22:12:56.159849 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3148 22:12:56.162811 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3149 22:12:56.162908
3150 22:12:56.166500 CA PerBit enable=1, Macro0, CA PI delay=33
3151 22:12:56.166604
3152 22:12:56.169452 [CBTSetCACLKResult] CA Dly = 33
3153 22:12:56.172951 CS Dly: 5 (0~36)
3154 22:12:56.173056 ==
3155 22:12:56.176467 Dram Type= 6, Freq= 0, CH_1, rank 1
3156 22:12:56.179437 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3157 22:12:56.179544 ==
3158 22:12:56.185850 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3159 22:12:56.189137 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3160 22:12:56.199360 [CA 0] Center 37 (7~67) winsize 61
3161 22:12:56.202095 [CA 1] Center 37 (7~68) winsize 62
3162 22:12:56.205478 [CA 2] Center 34 (4~65) winsize 62
3163 22:12:56.208970 [CA 3] Center 33 (3~64) winsize 62
3164 22:12:56.212580 [CA 4] Center 34 (4~65) winsize 62
3165 22:12:56.215562 [CA 5] Center 32 (2~63) winsize 62
3166 22:12:56.215705
3167 22:12:56.218625 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3168 22:12:56.218731
3169 22:12:56.222397 [CATrainingPosCal] consider 2 rank data
3170 22:12:56.225943 u2DelayCellTimex100 = 270/100 ps
3171 22:12:56.228768 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3172 22:12:56.235732 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3173 22:12:56.238708 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3174 22:12:56.241943 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3175 22:12:56.245654 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3176 22:12:56.248510 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3177 22:12:56.248617
3178 22:12:56.252020 CA PerBit enable=1, Macro0, CA PI delay=33
3179 22:12:56.252126
3180 22:12:56.255209 [CBTSetCACLKResult] CA Dly = 33
3181 22:12:56.258728 CS Dly: 6 (0~39)
3182 22:12:56.258833
3183 22:12:56.261882 ----->DramcWriteLeveling(PI) begin...
3184 22:12:56.261989 ==
3185 22:12:56.265539 Dram Type= 6, Freq= 0, CH_1, rank 0
3186 22:12:56.268520 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3187 22:12:56.268628 ==
3188 22:12:56.271677 Write leveling (Byte 0): 25 => 25
3189 22:12:56.275423 Write leveling (Byte 1): 28 => 28
3190 22:12:56.278308 DramcWriteLeveling(PI) end<-----
3191 22:12:56.278413
3192 22:12:56.278504 ==
3193 22:12:56.281660 Dram Type= 6, Freq= 0, CH_1, rank 0
3194 22:12:56.285134 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3195 22:12:56.285219 ==
3196 22:12:56.288534 [Gating] SW mode calibration
3197 22:12:56.295248 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3198 22:12:56.301738 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3199 22:12:56.304997 0 15 0 | B1->B0 | 3131 2f2f | 0 1 | (0 0) (1 1)
3200 22:12:56.307926 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3201 22:12:56.314661 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3202 22:12:56.317872 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3203 22:12:56.321494 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3204 22:12:56.328059 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3205 22:12:56.330981 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3206 22:12:56.334554 0 15 28 | B1->B0 | 2c2c 2d2d | 1 1 | (1 1) (1 0)
3207 22:12:56.341347 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3208 22:12:56.344245 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3209 22:12:56.347685 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3210 22:12:56.354219 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3211 22:12:56.357271 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3212 22:12:56.360567 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3213 22:12:56.367469 1 0 24 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
3214 22:12:56.370458 1 0 28 | B1->B0 | 4242 4343 | 0 0 | (0 0) (0 0)
3215 22:12:56.373766 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3216 22:12:56.380399 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3217 22:12:56.383909 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3218 22:12:56.386934 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3219 22:12:56.393874 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3220 22:12:56.397194 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3221 22:12:56.400825 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3222 22:12:56.406727 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3223 22:12:56.410195 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3224 22:12:56.414127 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3225 22:12:56.420486 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3226 22:12:56.423782 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3227 22:12:56.426700 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3228 22:12:56.433300 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3229 22:12:56.436959 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3230 22:12:56.440080 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3231 22:12:56.446862 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3232 22:12:56.450349 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3233 22:12:56.453450 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3234 22:12:56.459626 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3235 22:12:56.463093 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3236 22:12:56.466712 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3237 22:12:56.473387 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3238 22:12:56.476380 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3239 22:12:56.480092 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3240 22:12:56.483135 Total UI for P1: 0, mck2ui 16
3241 22:12:56.486261 best dqsien dly found for B0: ( 1, 3, 28)
3242 22:12:56.489767 Total UI for P1: 0, mck2ui 16
3243 22:12:56.492668 best dqsien dly found for B1: ( 1, 3, 28)
3244 22:12:56.496305 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3245 22:12:56.499414 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3246 22:12:56.499493
3247 22:12:56.506459 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3248 22:12:56.509711 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3249 22:12:56.509811 [Gating] SW calibration Done
3250 22:12:56.513019 ==
3251 22:12:56.513116 Dram Type= 6, Freq= 0, CH_1, rank 0
3252 22:12:56.519636 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3253 22:12:56.519718 ==
3254 22:12:56.519792 RX Vref Scan: 0
3255 22:12:56.519883
3256 22:12:56.522644 RX Vref 0 -> 0, step: 1
3257 22:12:56.522718
3258 22:12:56.526252 RX Delay -40 -> 252, step: 8
3259 22:12:56.529638 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3260 22:12:56.532476 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3261 22:12:56.535998 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3262 22:12:56.542728 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3263 22:12:56.546360 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3264 22:12:56.549344 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3265 22:12:56.552671 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3266 22:12:56.556215 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3267 22:12:56.563135 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3268 22:12:56.565914 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3269 22:12:56.569506 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
3270 22:12:56.572669 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
3271 22:12:56.576354 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3272 22:12:56.582593 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
3273 22:12:56.586116 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3274 22:12:56.589175 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3275 22:12:56.589285 ==
3276 22:12:56.592771 Dram Type= 6, Freq= 0, CH_1, rank 0
3277 22:12:56.595920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3278 22:12:56.596033 ==
3279 22:12:56.598919 DQS Delay:
3280 22:12:56.599022 DQS0 = 0, DQS1 = 0
3281 22:12:56.602386 DQM Delay:
3282 22:12:56.602489 DQM0 = 114, DQM1 = 105
3283 22:12:56.602584 DQ Delay:
3284 22:12:56.608881 DQ0 =115, DQ1 =111, DQ2 =99, DQ3 =115
3285 22:12:56.612544 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =115
3286 22:12:56.616057 DQ8 =95, DQ9 =99, DQ10 =103, DQ11 =99
3287 22:12:56.618812 DQ12 =111, DQ13 =111, DQ14 =111, DQ15 =111
3288 22:12:56.618922
3289 22:12:56.619014
3290 22:12:56.619102 ==
3291 22:12:56.622410 Dram Type= 6, Freq= 0, CH_1, rank 0
3292 22:12:56.625880 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3293 22:12:56.625964 ==
3294 22:12:56.626030
3295 22:12:56.626090
3296 22:12:56.629089 TX Vref Scan disable
3297 22:12:56.632373 == TX Byte 0 ==
3298 22:12:56.635895 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3299 22:12:56.638725 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3300 22:12:56.642179 == TX Byte 1 ==
3301 22:12:56.645619 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3302 22:12:56.649314 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3303 22:12:56.649459 ==
3304 22:12:56.652168 Dram Type= 6, Freq= 0, CH_1, rank 0
3305 22:12:56.655193 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3306 22:12:56.658510 ==
3307 22:12:56.668914 TX Vref=22, minBit 10, minWin=24, winSum=409
3308 22:12:56.672215 TX Vref=24, minBit 8, minWin=24, winSum=409
3309 22:12:56.675394 TX Vref=26, minBit 10, minWin=24, winSum=418
3310 22:12:56.679188 TX Vref=28, minBit 10, minWin=25, winSum=422
3311 22:12:56.682185 TX Vref=30, minBit 9, minWin=25, winSum=423
3312 22:12:56.688801 TX Vref=32, minBit 9, minWin=25, winSum=425
3313 22:12:56.691937 [TxChooseVref] Worse bit 9, Min win 25, Win sum 425, Final Vref 32
3314 22:12:56.692019
3315 22:12:56.695506 Final TX Range 1 Vref 32
3316 22:12:56.695634
3317 22:12:56.695702 ==
3318 22:12:56.698475 Dram Type= 6, Freq= 0, CH_1, rank 0
3319 22:12:56.702025 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3320 22:12:56.705182 ==
3321 22:12:56.705257
3322 22:12:56.705319
3323 22:12:56.705379 TX Vref Scan disable
3324 22:12:56.708745 == TX Byte 0 ==
3325 22:12:56.712222 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3326 22:12:56.718410 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3327 22:12:56.718513 == TX Byte 1 ==
3328 22:12:56.721591 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3329 22:12:56.728187 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3330 22:12:56.728298
3331 22:12:56.728387 [DATLAT]
3332 22:12:56.728468 Freq=1200, CH1 RK0
3333 22:12:56.728546
3334 22:12:56.731515 DATLAT Default: 0xd
3335 22:12:56.735177 0, 0xFFFF, sum = 0
3336 22:12:56.735287 1, 0xFFFF, sum = 0
3337 22:12:56.738464 2, 0xFFFF, sum = 0
3338 22:12:56.738589 3, 0xFFFF, sum = 0
3339 22:12:56.741800 4, 0xFFFF, sum = 0
3340 22:12:56.741920 5, 0xFFFF, sum = 0
3341 22:12:56.745028 6, 0xFFFF, sum = 0
3342 22:12:56.745116 7, 0xFFFF, sum = 0
3343 22:12:56.748322 8, 0xFFFF, sum = 0
3344 22:12:56.748411 9, 0xFFFF, sum = 0
3345 22:12:56.751677 10, 0xFFFF, sum = 0
3346 22:12:56.751792 11, 0xFFFF, sum = 0
3347 22:12:56.754636 12, 0x0, sum = 1
3348 22:12:56.754745 13, 0x0, sum = 2
3349 22:12:56.758540 14, 0x0, sum = 3
3350 22:12:56.758624 15, 0x0, sum = 4
3351 22:12:56.761320 best_step = 13
3352 22:12:56.761402
3353 22:12:56.761467 ==
3354 22:12:56.764696 Dram Type= 6, Freq= 0, CH_1, rank 0
3355 22:12:56.768499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3356 22:12:56.768608 ==
3357 22:12:56.771744 RX Vref Scan: 1
3358 22:12:56.771843
3359 22:12:56.771938 Set Vref Range= 32 -> 127
3360 22:12:56.772028
3361 22:12:56.774547 RX Vref 32 -> 127, step: 1
3362 22:12:56.774660
3363 22:12:56.778420 RX Delay -21 -> 252, step: 4
3364 22:12:56.778512
3365 22:12:56.781422 Set Vref, RX VrefLevel [Byte0]: 32
3366 22:12:56.784492 [Byte1]: 32
3367 22:12:56.784620
3368 22:12:56.788105 Set Vref, RX VrefLevel [Byte0]: 33
3369 22:12:56.791070 [Byte1]: 33
3370 22:12:56.795386
3371 22:12:56.795491 Set Vref, RX VrefLevel [Byte0]: 34
3372 22:12:56.798480 [Byte1]: 34
3373 22:12:56.803245
3374 22:12:56.803354 Set Vref, RX VrefLevel [Byte0]: 35
3375 22:12:56.806487 [Byte1]: 35
3376 22:12:56.811493
3377 22:12:56.811575 Set Vref, RX VrefLevel [Byte0]: 36
3378 22:12:56.814162 [Byte1]: 36
3379 22:12:56.819028
3380 22:12:56.819110 Set Vref, RX VrefLevel [Byte0]: 37
3381 22:12:56.822525 [Byte1]: 37
3382 22:12:56.826761
3383 22:12:56.826845 Set Vref, RX VrefLevel [Byte0]: 38
3384 22:12:56.830009 [Byte1]: 38
3385 22:12:56.835102
3386 22:12:56.835192 Set Vref, RX VrefLevel [Byte0]: 39
3387 22:12:56.838333 [Byte1]: 39
3388 22:12:56.842487
3389 22:12:56.842561 Set Vref, RX VrefLevel [Byte0]: 40
3390 22:12:56.845830 [Byte1]: 40
3391 22:12:56.850547
3392 22:12:56.850621 Set Vref, RX VrefLevel [Byte0]: 41
3393 22:12:56.853887 [Byte1]: 41
3394 22:12:56.858915
3395 22:12:56.859017 Set Vref, RX VrefLevel [Byte0]: 42
3396 22:12:56.861942 [Byte1]: 42
3397 22:12:56.866904
3398 22:12:56.867019 Set Vref, RX VrefLevel [Byte0]: 43
3399 22:12:56.869996 [Byte1]: 43
3400 22:12:56.874276
3401 22:12:56.874393 Set Vref, RX VrefLevel [Byte0]: 44
3402 22:12:56.880746 [Byte1]: 44
3403 22:12:56.880890
3404 22:12:56.884040 Set Vref, RX VrefLevel [Byte0]: 45
3405 22:12:56.887500 [Byte1]: 45
3406 22:12:56.887632
3407 22:12:56.890466 Set Vref, RX VrefLevel [Byte0]: 46
3408 22:12:56.894087 [Byte1]: 46
3409 22:12:56.898382
3410 22:12:56.898462 Set Vref, RX VrefLevel [Byte0]: 47
3411 22:12:56.901564 [Byte1]: 47
3412 22:12:56.906297
3413 22:12:56.906376 Set Vref, RX VrefLevel [Byte0]: 48
3414 22:12:56.909267 [Byte1]: 48
3415 22:12:56.914250
3416 22:12:56.914330 Set Vref, RX VrefLevel [Byte0]: 49
3417 22:12:56.917574 [Byte1]: 49
3418 22:12:56.921871
3419 22:12:56.921951 Set Vref, RX VrefLevel [Byte0]: 50
3420 22:12:56.925415 [Byte1]: 50
3421 22:12:56.929643
3422 22:12:56.929721 Set Vref, RX VrefLevel [Byte0]: 51
3423 22:12:56.933059 [Byte1]: 51
3424 22:12:56.937953
3425 22:12:56.938057 Set Vref, RX VrefLevel [Byte0]: 52
3426 22:12:56.941281 [Byte1]: 52
3427 22:12:56.945653
3428 22:12:56.945732 Set Vref, RX VrefLevel [Byte0]: 53
3429 22:12:56.948993 [Byte1]: 53
3430 22:12:56.953724
3431 22:12:56.953807 Set Vref, RX VrefLevel [Byte0]: 54
3432 22:12:56.957012 [Byte1]: 54
3433 22:12:56.961642
3434 22:12:56.961723 Set Vref, RX VrefLevel [Byte0]: 55
3435 22:12:56.965013 [Byte1]: 55
3436 22:12:56.969806
3437 22:12:56.969887 Set Vref, RX VrefLevel [Byte0]: 56
3438 22:12:56.972760 [Byte1]: 56
3439 22:12:56.977344
3440 22:12:56.980968 Set Vref, RX VrefLevel [Byte0]: 57
3441 22:12:56.981049 [Byte1]: 57
3442 22:12:56.985121
3443 22:12:56.985212 Set Vref, RX VrefLevel [Byte0]: 58
3444 22:12:56.988697 [Byte1]: 58
3445 22:12:56.993064
3446 22:12:56.993145 Set Vref, RX VrefLevel [Byte0]: 59
3447 22:12:56.996511 [Byte1]: 59
3448 22:12:57.001414
3449 22:12:57.001495 Set Vref, RX VrefLevel [Byte0]: 60
3450 22:12:57.004423 [Byte1]: 60
3451 22:12:57.009261
3452 22:12:57.009346 Set Vref, RX VrefLevel [Byte0]: 61
3453 22:12:57.012336 [Byte1]: 61
3454 22:12:57.017096
3455 22:12:57.017180 Set Vref, RX VrefLevel [Byte0]: 62
3456 22:12:57.020216 [Byte1]: 62
3457 22:12:57.024648
3458 22:12:57.024731 Set Vref, RX VrefLevel [Byte0]: 63
3459 22:12:57.028148 [Byte1]: 63
3460 22:12:57.032991
3461 22:12:57.033075 Set Vref, RX VrefLevel [Byte0]: 64
3462 22:12:57.035786 [Byte1]: 64
3463 22:12:57.040533
3464 22:12:57.040617 Set Vref, RX VrefLevel [Byte0]: 65
3465 22:12:57.044021 [Byte1]: 65
3466 22:12:57.048438
3467 22:12:57.048533 Set Vref, RX VrefLevel [Byte0]: 66
3468 22:12:57.052036 [Byte1]: 66
3469 22:12:57.056937
3470 22:12:57.057036 Set Vref, RX VrefLevel [Byte0]: 67
3471 22:12:57.060240 [Byte1]: 67
3472 22:12:57.064487
3473 22:12:57.064572 Final RX Vref Byte 0 = 52 to rank0
3474 22:12:57.067835 Final RX Vref Byte 1 = 53 to rank0
3475 22:12:57.071096 Final RX Vref Byte 0 = 52 to rank1
3476 22:12:57.074222 Final RX Vref Byte 1 = 53 to rank1==
3477 22:12:57.077653 Dram Type= 6, Freq= 0, CH_1, rank 0
3478 22:12:57.084603 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3479 22:12:57.084720 ==
3480 22:12:57.084787 DQS Delay:
3481 22:12:57.084849 DQS0 = 0, DQS1 = 0
3482 22:12:57.087542 DQM Delay:
3483 22:12:57.087647 DQM0 = 113, DQM1 = 106
3484 22:12:57.091191 DQ Delay:
3485 22:12:57.094082 DQ0 =118, DQ1 =108, DQ2 =104, DQ3 =110
3486 22:12:57.097448 DQ4 =110, DQ5 =122, DQ6 =124, DQ7 =110
3487 22:12:57.100879 DQ8 =92, DQ9 =98, DQ10 =104, DQ11 =102
3488 22:12:57.104515 DQ12 =116, DQ13 =114, DQ14 =114, DQ15 =114
3489 22:12:57.104597
3490 22:12:57.104662
3491 22:12:57.114154 [DQSOSCAuto] RK0, (LSB)MR18= 0xedf3, (MSB)MR19= 0x303, tDQSOscB0 = 415 ps tDQSOscB1 = 417 ps
3492 22:12:57.114237 CH1 RK0: MR19=303, MR18=EDF3
3493 22:12:57.120946 CH1_RK0: MR19=0x303, MR18=0xEDF3, DQSOSC=415, MR23=63, INC=38, DEC=25
3494 22:12:57.121029
3495 22:12:57.123943 ----->DramcWriteLeveling(PI) begin...
3496 22:12:57.124026 ==
3497 22:12:57.127247 Dram Type= 6, Freq= 0, CH_1, rank 1
3498 22:12:57.133808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3499 22:12:57.133891 ==
3500 22:12:57.137463 Write leveling (Byte 0): 25 => 25
3501 22:12:57.140592 Write leveling (Byte 1): 27 => 27
3502 22:12:57.140673 DramcWriteLeveling(PI) end<-----
3503 22:12:57.140739
3504 22:12:57.143540 ==
3505 22:12:57.147100 Dram Type= 6, Freq= 0, CH_1, rank 1
3506 22:12:57.150146 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3507 22:12:57.150228 ==
3508 22:12:57.153525 [Gating] SW mode calibration
3509 22:12:57.160506 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3510 22:12:57.163363 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3511 22:12:57.170013 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3512 22:12:57.173384 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3513 22:12:57.177482 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3514 22:12:57.183591 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3515 22:12:57.186692 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3516 22:12:57.190052 0 15 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
3517 22:12:57.196631 0 15 24 | B1->B0 | 3131 2424 | 1 0 | (1 0) (1 0)
3518 22:12:57.199889 0 15 28 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
3519 22:12:57.203553 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3520 22:12:57.210211 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3521 22:12:57.213045 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3522 22:12:57.216596 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3523 22:12:57.223293 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3524 22:12:57.226404 1 0 20 | B1->B0 | 2424 2827 | 0 1 | (0 0) (0 0)
3525 22:12:57.229856 1 0 24 | B1->B0 | 2c2c 4646 | 1 0 | (1 1) (0 0)
3526 22:12:57.236232 1 0 28 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
3527 22:12:57.239812 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3528 22:12:57.243427 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3529 22:12:57.249955 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3530 22:12:57.252692 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3531 22:12:57.256425 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3532 22:12:57.262708 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3533 22:12:57.266458 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3534 22:12:57.269563 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3535 22:12:57.276229 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3536 22:12:57.279322 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3537 22:12:57.282666 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3538 22:12:57.289498 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3539 22:12:57.292557 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3540 22:12:57.295852 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3541 22:12:57.302407 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3542 22:12:57.305814 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3543 22:12:57.308968 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3544 22:12:57.315338 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3545 22:12:57.318869 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3546 22:12:57.321832 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3547 22:12:57.328496 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3548 22:12:57.332016 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3549 22:12:57.335378 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3550 22:12:57.341956 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3551 22:12:57.342068 Total UI for P1: 0, mck2ui 16
3552 22:12:57.348519 best dqsien dly found for B0: ( 1, 3, 24)
3553 22:12:57.351448 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3554 22:12:57.354923 Total UI for P1: 0, mck2ui 16
3555 22:12:57.358537 best dqsien dly found for B1: ( 1, 3, 26)
3556 22:12:57.361636 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3557 22:12:57.364669 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3558 22:12:57.364741
3559 22:12:57.368020 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3560 22:12:57.371268 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3561 22:12:57.374588 [Gating] SW calibration Done
3562 22:12:57.374673 ==
3563 22:12:57.377998 Dram Type= 6, Freq= 0, CH_1, rank 1
3564 22:12:57.384484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3565 22:12:57.384566 ==
3566 22:12:57.384632 RX Vref Scan: 0
3567 22:12:57.384693
3568 22:12:57.387819 RX Vref 0 -> 0, step: 1
3569 22:12:57.387888
3570 22:12:57.391213 RX Delay -40 -> 252, step: 8
3571 22:12:57.394775 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3572 22:12:57.397621 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3573 22:12:57.401275 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3574 22:12:57.404154 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
3575 22:12:57.410701 iDelay=200, Bit 4, Center 107 (32 ~ 183) 152
3576 22:12:57.414421 iDelay=200, Bit 5, Center 119 (40 ~ 199) 160
3577 22:12:57.417704 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
3578 22:12:57.420656 iDelay=200, Bit 7, Center 107 (32 ~ 183) 152
3579 22:12:57.424358 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3580 22:12:57.430436 iDelay=200, Bit 9, Center 99 (24 ~ 175) 152
3581 22:12:57.433945 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3582 22:12:57.437392 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3583 22:12:57.440362 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
3584 22:12:57.447260 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3585 22:12:57.450336 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3586 22:12:57.453826 iDelay=200, Bit 15, Center 115 (40 ~ 191) 152
3587 22:12:57.453907 ==
3588 22:12:57.456838 Dram Type= 6, Freq= 0, CH_1, rank 1
3589 22:12:57.460426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3590 22:12:57.460508 ==
3591 22:12:57.463489 DQS Delay:
3592 22:12:57.463629 DQS0 = 0, DQS1 = 0
3593 22:12:57.467284 DQM Delay:
3594 22:12:57.467365 DQM0 = 110, DQM1 = 108
3595 22:12:57.470199 DQ Delay:
3596 22:12:57.473515 DQ0 =115, DQ1 =107, DQ2 =99, DQ3 =107
3597 22:12:57.476746 DQ4 =107, DQ5 =119, DQ6 =119, DQ7 =107
3598 22:12:57.480348 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =103
3599 22:12:57.483446 DQ12 =115, DQ13 =115, DQ14 =115, DQ15 =115
3600 22:12:57.483553
3601 22:12:57.483666
3602 22:12:57.483727 ==
3603 22:12:57.486842 Dram Type= 6, Freq= 0, CH_1, rank 1
3604 22:12:57.489714 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3605 22:12:57.489805 ==
3606 22:12:57.489899
3607 22:12:57.489988
3608 22:12:57.493569 TX Vref Scan disable
3609 22:12:57.496781 == TX Byte 0 ==
3610 22:12:57.499778 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3611 22:12:57.503359 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3612 22:12:57.506476 == TX Byte 1 ==
3613 22:12:57.509693 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3614 22:12:57.512898 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3615 22:12:57.512997 ==
3616 22:12:57.516400 Dram Type= 6, Freq= 0, CH_1, rank 1
3617 22:12:57.522959 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3618 22:12:57.523051 ==
3619 22:12:57.533144 TX Vref=22, minBit 0, minWin=25, winSum=418
3620 22:12:57.537035 TX Vref=24, minBit 9, minWin=25, winSum=421
3621 22:12:57.540188 TX Vref=26, minBit 8, minWin=26, winSum=432
3622 22:12:57.543438 TX Vref=28, minBit 9, minWin=26, winSum=434
3623 22:12:57.546401 TX Vref=30, minBit 9, minWin=26, winSum=433
3624 22:12:57.553507 TX Vref=32, minBit 1, minWin=25, winSum=427
3625 22:12:57.556454 [TxChooseVref] Worse bit 9, Min win 26, Win sum 434, Final Vref 28
3626 22:12:57.556537
3627 22:12:57.560095 Final TX Range 1 Vref 28
3628 22:12:57.560177
3629 22:12:57.560275 ==
3630 22:12:57.563093 Dram Type= 6, Freq= 0, CH_1, rank 1
3631 22:12:57.566485 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3632 22:12:57.569482 ==
3633 22:12:57.569563
3634 22:12:57.569628
3635 22:12:57.569688 TX Vref Scan disable
3636 22:12:57.573040 == TX Byte 0 ==
3637 22:12:57.576287 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3638 22:12:57.579601 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3639 22:12:57.583198 == TX Byte 1 ==
3640 22:12:57.586278 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3641 22:12:57.589665 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3642 22:12:57.592947
3643 22:12:57.593021 [DATLAT]
3644 22:12:57.593083 Freq=1200, CH1 RK1
3645 22:12:57.593154
3646 22:12:57.596382 DATLAT Default: 0xd
3647 22:12:57.596456 0, 0xFFFF, sum = 0
3648 22:12:57.599688 1, 0xFFFF, sum = 0
3649 22:12:57.602983 2, 0xFFFF, sum = 0
3650 22:12:57.603054 3, 0xFFFF, sum = 0
3651 22:12:57.606359 4, 0xFFFF, sum = 0
3652 22:12:57.606431 5, 0xFFFF, sum = 0
3653 22:12:57.609316 6, 0xFFFF, sum = 0
3654 22:12:57.609386 7, 0xFFFF, sum = 0
3655 22:12:57.613058 8, 0xFFFF, sum = 0
3656 22:12:57.613133 9, 0xFFFF, sum = 0
3657 22:12:57.615939 10, 0xFFFF, sum = 0
3658 22:12:57.616009 11, 0xFFFF, sum = 0
3659 22:12:57.619677 12, 0x0, sum = 1
3660 22:12:57.619749 13, 0x0, sum = 2
3661 22:12:57.622808 14, 0x0, sum = 3
3662 22:12:57.622909 15, 0x0, sum = 4
3663 22:12:57.625929 best_step = 13
3664 22:12:57.625999
3665 22:12:57.626075 ==
3666 22:12:57.629090 Dram Type= 6, Freq= 0, CH_1, rank 1
3667 22:12:57.632970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3668 22:12:57.633060 ==
3669 22:12:57.633123 RX Vref Scan: 0
3670 22:12:57.635961
3671 22:12:57.636062 RX Vref 0 -> 0, step: 1
3672 22:12:57.636150
3673 22:12:57.638924 RX Delay -21 -> 252, step: 4
3674 22:12:57.645512 iDelay=195, Bit 0, Center 112 (39 ~ 186) 148
3675 22:12:57.649254 iDelay=195, Bit 1, Center 108 (39 ~ 178) 140
3676 22:12:57.652044 iDelay=195, Bit 2, Center 100 (31 ~ 170) 140
3677 22:12:57.655570 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3678 22:12:57.659023 iDelay=195, Bit 4, Center 108 (39 ~ 178) 140
3679 22:12:57.665645 iDelay=195, Bit 5, Center 118 (47 ~ 190) 144
3680 22:12:57.668702 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3681 22:12:57.672106 iDelay=195, Bit 7, Center 110 (43 ~ 178) 136
3682 22:12:57.675696 iDelay=195, Bit 8, Center 96 (31 ~ 162) 132
3683 22:12:57.678632 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3684 22:12:57.685366 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3685 22:12:57.688356 iDelay=195, Bit 11, Center 104 (39 ~ 170) 132
3686 22:12:57.692161 iDelay=195, Bit 12, Center 116 (51 ~ 182) 132
3687 22:12:57.695460 iDelay=195, Bit 13, Center 116 (51 ~ 182) 132
3688 22:12:57.698369 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3689 22:12:57.705146 iDelay=195, Bit 15, Center 118 (51 ~ 186) 136
3690 22:12:57.705222 ==
3691 22:12:57.708625 Dram Type= 6, Freq= 0, CH_1, rank 1
3692 22:12:57.711873 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3693 22:12:57.711944 ==
3694 22:12:57.712005 DQS Delay:
3695 22:12:57.714931 DQS0 = 0, DQS1 = 0
3696 22:12:57.714999 DQM Delay:
3697 22:12:57.718586 DQM0 = 110, DQM1 = 109
3698 22:12:57.718659 DQ Delay:
3699 22:12:57.721427 DQ0 =112, DQ1 =108, DQ2 =100, DQ3 =108
3700 22:12:57.724826 DQ4 =108, DQ5 =118, DQ6 =120, DQ7 =110
3701 22:12:57.728175 DQ8 =96, DQ9 =102, DQ10 =110, DQ11 =104
3702 22:12:57.734394 DQ12 =116, DQ13 =116, DQ14 =116, DQ15 =118
3703 22:12:57.734467
3704 22:12:57.734543
3705 22:12:57.741374 [DQSOSCAuto] RK1, (LSB)MR18= 0xfa09, (MSB)MR19= 0x304, tDQSOscB0 = 406 ps tDQSOscB1 = 412 ps
3706 22:12:57.744469 CH1 RK1: MR19=304, MR18=FA09
3707 22:12:57.751228 CH1_RK1: MR19=0x304, MR18=0xFA09, DQSOSC=406, MR23=63, INC=39, DEC=26
3708 22:12:57.754682 [RxdqsGatingPostProcess] freq 1200
3709 22:12:57.758147 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3710 22:12:57.761031 best DQS0 dly(2T, 0.5T) = (0, 11)
3711 22:12:57.764662 best DQS1 dly(2T, 0.5T) = (0, 11)
3712 22:12:57.767680 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3713 22:12:57.771261 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3714 22:12:57.774101 best DQS0 dly(2T, 0.5T) = (0, 11)
3715 22:12:57.777667 best DQS1 dly(2T, 0.5T) = (0, 11)
3716 22:12:57.780650 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3717 22:12:57.784298 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3718 22:12:57.787236 Pre-setting of DQS Precalculation
3719 22:12:57.790963 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3720 22:12:57.800660 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3721 22:12:57.806675 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3722 22:12:57.806757
3723 22:12:57.806869
3724 22:12:57.809986 [Calibration Summary] 2400 Mbps
3725 22:12:57.810092 CH 0, Rank 0
3726 22:12:57.813343 SW Impedance : PASS
3727 22:12:57.816985 DUTY Scan : NO K
3728 22:12:57.817085 ZQ Calibration : PASS
3729 22:12:57.819863 Jitter Meter : NO K
3730 22:12:57.823272 CBT Training : PASS
3731 22:12:57.823344 Write leveling : PASS
3732 22:12:57.826915 RX DQS gating : PASS
3733 22:12:57.826987 RX DQ/DQS(RDDQC) : PASS
3734 22:12:57.829874 TX DQ/DQS : PASS
3735 22:12:57.833109 RX DATLAT : PASS
3736 22:12:57.833180 RX DQ/DQS(Engine): PASS
3737 22:12:57.836702 TX OE : NO K
3738 22:12:57.836772 All Pass.
3739 22:12:57.836831
3740 22:12:57.839508 CH 0, Rank 1
3741 22:12:57.839644 SW Impedance : PASS
3742 22:12:57.843035 DUTY Scan : NO K
3743 22:12:57.846667 ZQ Calibration : PASS
3744 22:12:57.846741 Jitter Meter : NO K
3745 22:12:57.849574 CBT Training : PASS
3746 22:12:57.853304 Write leveling : PASS
3747 22:12:57.853375 RX DQS gating : PASS
3748 22:12:57.856394 RX DQ/DQS(RDDQC) : PASS
3749 22:12:57.859444 TX DQ/DQS : PASS
3750 22:12:57.859554 RX DATLAT : PASS
3751 22:12:57.863138 RX DQ/DQS(Engine): PASS
3752 22:12:57.865999 TX OE : NO K
3753 22:12:57.866080 All Pass.
3754 22:12:57.866145
3755 22:12:57.866205 CH 1, Rank 0
3756 22:12:57.869504 SW Impedance : PASS
3757 22:12:57.872511 DUTY Scan : NO K
3758 22:12:57.872591 ZQ Calibration : PASS
3759 22:12:57.876055 Jitter Meter : NO K
3760 22:12:57.879452 CBT Training : PASS
3761 22:12:57.879544 Write leveling : PASS
3762 22:12:57.882470 RX DQS gating : PASS
3763 22:12:57.885984 RX DQ/DQS(RDDQC) : PASS
3764 22:12:57.886066 TX DQ/DQS : PASS
3765 22:12:57.889205 RX DATLAT : PASS
3766 22:12:57.892814 RX DQ/DQS(Engine): PASS
3767 22:12:57.892895 TX OE : NO K
3768 22:12:57.895815 All Pass.
3769 22:12:57.895895
3770 22:12:57.895960 CH 1, Rank 1
3771 22:12:57.898889 SW Impedance : PASS
3772 22:12:57.898970 DUTY Scan : NO K
3773 22:12:57.902672 ZQ Calibration : PASS
3774 22:12:57.906181 Jitter Meter : NO K
3775 22:12:57.906262 CBT Training : PASS
3776 22:12:57.908935 Write leveling : PASS
3777 22:12:57.912294 RX DQS gating : PASS
3778 22:12:57.912375 RX DQ/DQS(RDDQC) : PASS
3779 22:12:57.915531 TX DQ/DQS : PASS
3780 22:12:57.915637 RX DATLAT : PASS
3781 22:12:57.919098 RX DQ/DQS(Engine): PASS
3782 22:12:57.922304 TX OE : NO K
3783 22:12:57.922386 All Pass.
3784 22:12:57.922450
3785 22:12:57.925602 DramC Write-DBI off
3786 22:12:57.928473 PER_BANK_REFRESH: Hybrid Mode
3787 22:12:57.928554 TX_TRACKING: ON
3788 22:12:57.938986 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3789 22:12:57.941883 [FAST_K] Save calibration result to emmc
3790 22:12:57.945418 dramc_set_vcore_voltage set vcore to 650000
3791 22:12:57.948811 Read voltage for 600, 5
3792 22:12:57.948893 Vio18 = 0
3793 22:12:57.948957 Vcore = 650000
3794 22:12:57.951614 Vdram = 0
3795 22:12:57.951694 Vddq = 0
3796 22:12:57.951759 Vmddr = 0
3797 22:12:57.958293 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3798 22:12:57.961747 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3799 22:12:57.965053 MEM_TYPE=3, freq_sel=19
3800 22:12:57.967920 sv_algorithm_assistance_LP4_1600
3801 22:12:57.971451 ============ PULL DRAM RESETB DOWN ============
3802 22:12:57.974513 ========== PULL DRAM RESETB DOWN end =========
3803 22:12:57.981481 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3804 22:12:57.984971 ===================================
3805 22:12:57.987872 LPDDR4 DRAM CONFIGURATION
3806 22:12:57.991574 ===================================
3807 22:12:57.991694 EX_ROW_EN[0] = 0x0
3808 22:12:57.994674 EX_ROW_EN[1] = 0x0
3809 22:12:57.994757 LP4Y_EN = 0x0
3810 22:12:57.997768 WORK_FSP = 0x0
3811 22:12:57.997850 WL = 0x2
3812 22:12:58.001256 RL = 0x2
3813 22:12:58.001338 BL = 0x2
3814 22:12:58.004185 RPST = 0x0
3815 22:12:58.004267 RD_PRE = 0x0
3816 22:12:58.007865 WR_PRE = 0x1
3817 22:12:58.007946 WR_PST = 0x0
3818 22:12:58.011297 DBI_WR = 0x0
3819 22:12:58.011403 DBI_RD = 0x0
3820 22:12:58.014196 OTF = 0x1
3821 22:12:58.017703 ===================================
3822 22:12:58.021235 ===================================
3823 22:12:58.021337 ANA top config
3824 22:12:58.024042 ===================================
3825 22:12:58.027420 DLL_ASYNC_EN = 0
3826 22:12:58.030539 ALL_SLAVE_EN = 1
3827 22:12:58.033830 NEW_RANK_MODE = 1
3828 22:12:58.037281 DLL_IDLE_MODE = 1
3829 22:12:58.037382 LP45_APHY_COMB_EN = 1
3830 22:12:58.040822 TX_ODT_DIS = 1
3831 22:12:58.043894 NEW_8X_MODE = 1
3832 22:12:58.047305 ===================================
3833 22:12:58.050804 ===================================
3834 22:12:58.053728 data_rate = 1200
3835 22:12:58.057051 CKR = 1
3836 22:12:58.057133 DQ_P2S_RATIO = 8
3837 22:12:58.060265 ===================================
3838 22:12:58.063591 CA_P2S_RATIO = 8
3839 22:12:58.066992 DQ_CA_OPEN = 0
3840 22:12:58.070112 DQ_SEMI_OPEN = 0
3841 22:12:58.073525 CA_SEMI_OPEN = 0
3842 22:12:58.076585 CA_FULL_RATE = 0
3843 22:12:58.076668 DQ_CKDIV4_EN = 1
3844 22:12:58.080352 CA_CKDIV4_EN = 1
3845 22:12:58.083822 CA_PREDIV_EN = 0
3846 22:12:58.086563 PH8_DLY = 0
3847 22:12:58.089823 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3848 22:12:58.093660 DQ_AAMCK_DIV = 4
3849 22:12:58.093742 CA_AAMCK_DIV = 4
3850 22:12:58.096650 CA_ADMCK_DIV = 4
3851 22:12:58.099875 DQ_TRACK_CA_EN = 0
3852 22:12:58.103388 CA_PICK = 600
3853 22:12:58.106555 CA_MCKIO = 600
3854 22:12:58.109636 MCKIO_SEMI = 0
3855 22:12:58.113251 PLL_FREQ = 2288
3856 22:12:58.116596 DQ_UI_PI_RATIO = 32
3857 22:12:58.116679 CA_UI_PI_RATIO = 0
3858 22:12:58.119634 ===================================
3859 22:12:58.123018 ===================================
3860 22:12:58.126393 memory_type:LPDDR4
3861 22:12:58.129949 GP_NUM : 10
3862 22:12:58.130030 SRAM_EN : 1
3863 22:12:58.132726 MD32_EN : 0
3864 22:12:58.136227 ===================================
3865 22:12:58.139374 [ANA_INIT] >>>>>>>>>>>>>>
3866 22:12:58.142644 <<<<<< [CONFIGURE PHASE]: ANA_TX
3867 22:12:58.146196 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3868 22:12:58.149019 ===================================
3869 22:12:58.149101 data_rate = 1200,PCW = 0X5800
3870 22:12:58.152594 ===================================
3871 22:12:58.159292 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3872 22:12:58.162475 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3873 22:12:58.169551 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3874 22:12:58.172331 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3875 22:12:58.176009 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3876 22:12:58.178714 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3877 22:12:58.182289 [ANA_INIT] flow start
3878 22:12:58.185409 [ANA_INIT] PLL >>>>>>>>
3879 22:12:58.185484 [ANA_INIT] PLL <<<<<<<<
3880 22:12:58.188794 [ANA_INIT] MIDPI >>>>>>>>
3881 22:12:58.192412 [ANA_INIT] MIDPI <<<<<<<<
3882 22:12:58.192494 [ANA_INIT] DLL >>>>>>>>
3883 22:12:58.195856 [ANA_INIT] flow end
3884 22:12:58.198752 ============ LP4 DIFF to SE enter ============
3885 22:12:58.205333 ============ LP4 DIFF to SE exit ============
3886 22:12:58.205416 [ANA_INIT] <<<<<<<<<<<<<
3887 22:12:58.208555 [Flow] Enable top DCM control >>>>>
3888 22:12:58.211896 [Flow] Enable top DCM control <<<<<
3889 22:12:58.215558 Enable DLL master slave shuffle
3890 22:12:58.221655 ==============================================================
3891 22:12:58.221737 Gating Mode config
3892 22:12:58.228333 ==============================================================
3893 22:12:58.231698 Config description:
3894 22:12:58.241870 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3895 22:12:58.248142 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3896 22:12:58.251524 SELPH_MODE 0: By rank 1: By Phase
3897 22:12:58.258078 ==============================================================
3898 22:12:58.261353 GAT_TRACK_EN = 1
3899 22:12:58.264523 RX_GATING_MODE = 2
3900 22:12:58.264606 RX_GATING_TRACK_MODE = 2
3901 22:12:58.267611 SELPH_MODE = 1
3902 22:12:58.271104 PICG_EARLY_EN = 1
3903 22:12:58.274374 VALID_LAT_VALUE = 1
3904 22:12:58.281080 ==============================================================
3905 22:12:58.284714 Enter into Gating configuration >>>>
3906 22:12:58.287708 Exit from Gating configuration <<<<
3907 22:12:58.291253 Enter into DVFS_PRE_config >>>>>
3908 22:12:58.301139 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3909 22:12:58.304052 Exit from DVFS_PRE_config <<<<<
3910 22:12:58.307240 Enter into PICG configuration >>>>
3911 22:12:58.310815 Exit from PICG configuration <<<<
3912 22:12:58.313960 [RX_INPUT] configuration >>>>>
3913 22:12:58.317428 [RX_INPUT] configuration <<<<<
3914 22:12:58.320548 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3915 22:12:58.327006 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3916 22:12:58.333760 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3917 22:12:58.340021 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3918 22:12:58.347236 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3919 22:12:58.349941 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3920 22:12:58.356682 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3921 22:12:58.360283 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3922 22:12:58.363218 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3923 22:12:58.366566 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3924 22:12:58.372879 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3925 22:12:58.376265 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3926 22:12:58.379516 ===================================
3927 22:12:58.383226 LPDDR4 DRAM CONFIGURATION
3928 22:12:58.386676 ===================================
3929 22:12:58.386764 EX_ROW_EN[0] = 0x0
3930 22:12:58.389712 EX_ROW_EN[1] = 0x0
3931 22:12:58.389795 LP4Y_EN = 0x0
3932 22:12:58.393206 WORK_FSP = 0x0
3933 22:12:58.393289 WL = 0x2
3934 22:12:58.396204 RL = 0x2
3935 22:12:58.399834 BL = 0x2
3936 22:12:58.399909 RPST = 0x0
3937 22:12:58.403016 RD_PRE = 0x0
3938 22:12:58.403093 WR_PRE = 0x1
3939 22:12:58.406124 WR_PST = 0x0
3940 22:12:58.406195 DBI_WR = 0x0
3941 22:12:58.409760 DBI_RD = 0x0
3942 22:12:58.409838 OTF = 0x1
3943 22:12:58.412742 ===================================
3944 22:12:58.416265 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3945 22:12:58.422963 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3946 22:12:58.426046 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3947 22:12:58.429528 ===================================
3948 22:12:58.432432 LPDDR4 DRAM CONFIGURATION
3949 22:12:58.436338 ===================================
3950 22:12:58.436419 EX_ROW_EN[0] = 0x10
3951 22:12:58.439241 EX_ROW_EN[1] = 0x0
3952 22:12:58.439311 LP4Y_EN = 0x0
3953 22:12:58.442936 WORK_FSP = 0x0
3954 22:12:58.443016 WL = 0x2
3955 22:12:58.445757 RL = 0x2
3956 22:12:58.449636 BL = 0x2
3957 22:12:58.449715 RPST = 0x0
3958 22:12:58.452882 RD_PRE = 0x0
3959 22:12:58.452962 WR_PRE = 0x1
3960 22:12:58.455783 WR_PST = 0x0
3961 22:12:58.455859 DBI_WR = 0x0
3962 22:12:58.458985 DBI_RD = 0x0
3963 22:12:58.459064 OTF = 0x1
3964 22:12:58.462475 ===================================
3965 22:12:58.468907 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3966 22:12:58.472964 nWR fixed to 30
3967 22:12:58.476571 [ModeRegInit_LP4] CH0 RK0
3968 22:12:58.476653 [ModeRegInit_LP4] CH0 RK1
3969 22:12:58.479417 [ModeRegInit_LP4] CH1 RK0
3970 22:12:58.482581 [ModeRegInit_LP4] CH1 RK1
3971 22:12:58.482661 match AC timing 17
3972 22:12:58.489319 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3973 22:12:58.492766 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3974 22:12:58.496409 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3975 22:12:58.502487 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3976 22:12:58.505763 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3977 22:12:58.505839 ==
3978 22:12:58.509478 Dram Type= 6, Freq= 0, CH_0, rank 0
3979 22:12:58.512469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3980 22:12:58.512553 ==
3981 22:12:58.519266 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3982 22:12:58.525954 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3983 22:12:58.528972 [CA 0] Center 37 (7~67) winsize 61
3984 22:12:58.532534 [CA 1] Center 36 (6~67) winsize 62
3985 22:12:58.535537 [CA 2] Center 35 (5~65) winsize 61
3986 22:12:58.539047 [CA 3] Center 35 (5~65) winsize 61
3987 22:12:58.542149 [CA 4] Center 34 (4~64) winsize 61
3988 22:12:58.545789 [CA 5] Center 34 (4~64) winsize 61
3989 22:12:58.545868
3990 22:12:58.548664 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3991 22:12:58.548736
3992 22:12:58.552066 [CATrainingPosCal] consider 1 rank data
3993 22:12:58.555476 u2DelayCellTimex100 = 270/100 ps
3994 22:12:58.558674 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
3995 22:12:58.562075 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
3996 22:12:58.565378 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
3997 22:12:58.571806 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
3998 22:12:58.575225 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
3999 22:12:58.578702 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4000 22:12:58.578782
4001 22:12:58.581555 CA PerBit enable=1, Macro0, CA PI delay=34
4002 22:12:58.581632
4003 22:12:58.585014 [CBTSetCACLKResult] CA Dly = 34
4004 22:12:58.585098 CS Dly: 4 (0~35)
4005 22:12:58.585167 ==
4006 22:12:58.588619 Dram Type= 6, Freq= 0, CH_0, rank 1
4007 22:12:58.595140 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4008 22:12:58.595222 ==
4009 22:12:58.598373 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4010 22:12:58.604934 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4011 22:12:58.608501 [CA 0] Center 37 (7~67) winsize 61
4012 22:12:58.611861 [CA 1] Center 36 (6~67) winsize 62
4013 22:12:58.614896 [CA 2] Center 34 (4~65) winsize 62
4014 22:12:58.618478 [CA 3] Center 34 (4~65) winsize 62
4015 22:12:58.621347 [CA 4] Center 34 (4~65) winsize 62
4016 22:12:58.625121 [CA 5] Center 33 (3~64) winsize 62
4017 22:12:58.625235
4018 22:12:58.628038 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4019 22:12:58.628142
4020 22:12:58.631312 [CATrainingPosCal] consider 2 rank data
4021 22:12:58.634906 u2DelayCellTimex100 = 270/100 ps
4022 22:12:58.638316 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
4023 22:12:58.644400 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
4024 22:12:58.648048 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
4025 22:12:58.651052 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
4026 22:12:58.654608 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
4027 22:12:58.657693 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4028 22:12:58.657764
4029 22:12:58.661195 CA PerBit enable=1, Macro0, CA PI delay=34
4030 22:12:58.661275
4031 22:12:58.664335 [CBTSetCACLKResult] CA Dly = 34
4032 22:12:58.667875 CS Dly: 5 (0~38)
4033 22:12:58.667947
4034 22:12:58.671213 ----->DramcWriteLeveling(PI) begin...
4035 22:12:58.671310 ==
4036 22:12:58.674069 Dram Type= 6, Freq= 0, CH_0, rank 0
4037 22:12:58.677595 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4038 22:12:58.677686 ==
4039 22:12:58.680679 Write leveling (Byte 0): 34 => 34
4040 22:12:58.683950 Write leveling (Byte 1): 34 => 34
4041 22:12:58.687455 DramcWriteLeveling(PI) end<-----
4042 22:12:58.687556
4043 22:12:58.687672 ==
4044 22:12:58.691036 Dram Type= 6, Freq= 0, CH_0, rank 0
4045 22:12:58.693892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4046 22:12:58.693964 ==
4047 22:12:58.697447 [Gating] SW mode calibration
4048 22:12:58.703935 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4049 22:12:58.710460 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4050 22:12:58.714103 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4051 22:12:58.716838 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4052 22:12:58.723416 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4053 22:12:58.726640 0 9 12 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
4054 22:12:58.730026 0 9 16 | B1->B0 | 3030 2929 | 0 0 | (0 0) (1 1)
4055 22:12:58.737079 0 9 20 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
4056 22:12:58.740064 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4057 22:12:58.743381 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4058 22:12:58.750208 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4059 22:12:58.753307 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4060 22:12:58.756887 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4061 22:12:58.763115 0 10 12 | B1->B0 | 2727 2b2b | 0 1 | (0 0) (0 0)
4062 22:12:58.766591 0 10 16 | B1->B0 | 3232 3c3c | 0 0 | (0 0) (0 0)
4063 22:12:58.769908 0 10 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4064 22:12:58.776368 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4065 22:12:58.779799 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4066 22:12:58.782536 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4067 22:12:58.789795 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4068 22:12:58.792613 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4069 22:12:58.796176 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4070 22:12:58.802599 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4071 22:12:58.806245 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4072 22:12:58.812622 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4073 22:12:58.815488 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4074 22:12:58.819146 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4075 22:12:58.825830 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4076 22:12:58.828899 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4077 22:12:58.832391 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4078 22:12:58.839416 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4079 22:12:58.842359 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4080 22:12:58.845227 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4081 22:12:58.848473 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4082 22:12:58.855424 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4083 22:12:58.859095 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4084 22:12:58.862127 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4085 22:12:58.868512 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4086 22:12:58.871896 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4087 22:12:58.875187 Total UI for P1: 0, mck2ui 16
4088 22:12:58.878554 best dqsien dly found for B0: ( 0, 13, 12)
4089 22:12:58.882019 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4090 22:12:58.884842 Total UI for P1: 0, mck2ui 16
4091 22:12:58.888341 best dqsien dly found for B1: ( 0, 13, 18)
4092 22:12:58.891817 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4093 22:12:58.898384 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4094 22:12:58.898466
4095 22:12:58.901948 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4096 22:12:58.905176 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4097 22:12:58.908325 [Gating] SW calibration Done
4098 22:12:58.908407 ==
4099 22:12:58.911777 Dram Type= 6, Freq= 0, CH_0, rank 0
4100 22:12:58.915131 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4101 22:12:58.915214 ==
4102 22:12:58.918131 RX Vref Scan: 0
4103 22:12:58.918213
4104 22:12:58.918278 RX Vref 0 -> 0, step: 1
4105 22:12:58.918340
4106 22:12:58.921573 RX Delay -230 -> 252, step: 16
4107 22:12:58.924979 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4108 22:12:58.931499 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4109 22:12:58.934953 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4110 22:12:58.937901 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4111 22:12:58.940903 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4112 22:12:58.947545 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4113 22:12:58.951325 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4114 22:12:58.954249 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4115 22:12:58.957747 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4116 22:12:58.963831 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4117 22:12:58.967444 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4118 22:12:58.970465 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4119 22:12:58.974079 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4120 22:12:58.980495 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4121 22:12:58.983584 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4122 22:12:58.987183 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4123 22:12:58.987294 ==
4124 22:12:58.990502 Dram Type= 6, Freq= 0, CH_0, rank 0
4125 22:12:58.993504 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4126 22:12:58.996773 ==
4127 22:12:58.996859 DQS Delay:
4128 22:12:58.996934 DQS0 = 0, DQS1 = 0
4129 22:12:59.000406 DQM Delay:
4130 22:12:59.000487 DQM0 = 38, DQM1 = 28
4131 22:12:59.003863 DQ Delay:
4132 22:12:59.003945 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
4133 22:12:59.006700 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4134 22:12:59.010133 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4135 22:12:59.013287 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4136 22:12:59.013369
4137 22:12:59.016959
4138 22:12:59.017040 ==
4139 22:12:59.020116 Dram Type= 6, Freq= 0, CH_0, rank 0
4140 22:12:59.023493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4141 22:12:59.023637 ==
4142 22:12:59.023732
4143 22:12:59.023793
4144 22:12:59.027155 TX Vref Scan disable
4145 22:12:59.027237 == TX Byte 0 ==
4146 22:12:59.033593 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4147 22:12:59.036402 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4148 22:12:59.036484 == TX Byte 1 ==
4149 22:12:59.043331 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4150 22:12:59.046912 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4151 22:12:59.046994 ==
4152 22:12:59.050043 Dram Type= 6, Freq= 0, CH_0, rank 0
4153 22:12:59.053555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4154 22:12:59.053643 ==
4155 22:12:59.053710
4156 22:12:59.053809
4157 22:12:59.056577 TX Vref Scan disable
4158 22:12:59.059660 == TX Byte 0 ==
4159 22:12:59.063521 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4160 22:12:59.069248 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4161 22:12:59.069331 == TX Byte 1 ==
4162 22:12:59.072793 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4163 22:12:59.079276 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4164 22:12:59.079358
4165 22:12:59.079431 [DATLAT]
4166 22:12:59.079521 Freq=600, CH0 RK0
4167 22:12:59.079640
4168 22:12:59.082797 DATLAT Default: 0x9
4169 22:12:59.082879 0, 0xFFFF, sum = 0
4170 22:12:59.086231 1, 0xFFFF, sum = 0
4171 22:12:59.089534 2, 0xFFFF, sum = 0
4172 22:12:59.089620 3, 0xFFFF, sum = 0
4173 22:12:59.092745 4, 0xFFFF, sum = 0
4174 22:12:59.092824 5, 0xFFFF, sum = 0
4175 22:12:59.095990 6, 0xFFFF, sum = 0
4176 22:12:59.096067 7, 0xFFFF, sum = 0
4177 22:12:59.099114 8, 0x0, sum = 1
4178 22:12:59.099198 9, 0x0, sum = 2
4179 22:12:59.102411 10, 0x0, sum = 3
4180 22:12:59.102491 11, 0x0, sum = 4
4181 22:12:59.102559 best_step = 9
4182 22:12:59.102624
4183 22:12:59.105968 ==
4184 22:12:59.108803 Dram Type= 6, Freq= 0, CH_0, rank 0
4185 22:12:59.112345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4186 22:12:59.112426 ==
4187 22:12:59.112493 RX Vref Scan: 1
4188 22:12:59.112556
4189 22:12:59.115734 RX Vref 0 -> 0, step: 1
4190 22:12:59.115842
4191 22:12:59.118824 RX Delay -195 -> 252, step: 8
4192 22:12:59.118902
4193 22:12:59.122435 Set Vref, RX VrefLevel [Byte0]: 61
4194 22:12:59.125573 [Byte1]: 53
4195 22:12:59.125651
4196 22:12:59.128953 Final RX Vref Byte 0 = 61 to rank0
4197 22:12:59.132454 Final RX Vref Byte 1 = 53 to rank0
4198 22:12:59.135437 Final RX Vref Byte 0 = 61 to rank1
4199 22:12:59.139274 Final RX Vref Byte 1 = 53 to rank1==
4200 22:12:59.142062 Dram Type= 6, Freq= 0, CH_0, rank 0
4201 22:12:59.145471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4202 22:12:59.148922 ==
4203 22:12:59.149001 DQS Delay:
4204 22:12:59.149063 DQS0 = 0, DQS1 = 0
4205 22:12:59.151886 DQM Delay:
4206 22:12:59.151962 DQM0 = 35, DQM1 = 29
4207 22:12:59.155418 DQ Delay:
4208 22:12:59.155492 DQ0 =32, DQ1 =40, DQ2 =36, DQ3 =32
4209 22:12:59.158436 DQ4 =32, DQ5 =20, DQ6 =40, DQ7 =48
4210 22:12:59.162035 DQ8 =20, DQ9 =16, DQ10 =28, DQ11 =20
4211 22:12:59.165193 DQ12 =36, DQ13 =36, DQ14 =40, DQ15 =36
4212 22:12:59.168213
4213 22:12:59.168291
4214 22:12:59.174929 [DQSOSCAuto] RK0, (LSB)MR18= 0x3e3e, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 398 ps
4215 22:12:59.178229 CH0 RK0: MR19=808, MR18=3E3E
4216 22:12:59.185053 CH0_RK0: MR19=0x808, MR18=0x3E3E, DQSOSC=398, MR23=63, INC=165, DEC=110
4217 22:12:59.185138
4218 22:12:59.188548 ----->DramcWriteLeveling(PI) begin...
4219 22:12:59.188627 ==
4220 22:12:59.191903 Dram Type= 6, Freq= 0, CH_0, rank 1
4221 22:12:59.195175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4222 22:12:59.195263 ==
4223 22:12:59.197989 Write leveling (Byte 0): 32 => 32
4224 22:12:59.201959 Write leveling (Byte 1): 31 => 31
4225 22:12:59.204629 DramcWriteLeveling(PI) end<-----
4226 22:12:59.204701
4227 22:12:59.204774 ==
4228 22:12:59.208013 Dram Type= 6, Freq= 0, CH_0, rank 1
4229 22:12:59.211550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4230 22:12:59.211663 ==
4231 22:12:59.215024 [Gating] SW mode calibration
4232 22:12:59.221313 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4233 22:12:59.227773 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4234 22:12:59.231454 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4235 22:12:59.237610 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4236 22:12:59.241357 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4237 22:12:59.244190 0 9 12 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 0)
4238 22:12:59.251190 0 9 16 | B1->B0 | 2f2f 2323 | 1 0 | (1 1) (1 0)
4239 22:12:59.254190 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4240 22:12:59.257749 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4241 22:12:59.264255 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4242 22:12:59.267370 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4243 22:12:59.270940 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4244 22:12:59.277599 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4245 22:12:59.281219 0 10 12 | B1->B0 | 2727 3434 | 0 0 | (0 0) (0 0)
4246 22:12:59.284297 0 10 16 | B1->B0 | 3636 4646 | 1 0 | (0 0) (0 0)
4247 22:12:59.290524 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4248 22:12:59.293908 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4249 22:12:59.297433 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4250 22:12:59.303849 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4251 22:12:59.307250 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4252 22:12:59.310329 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4253 22:12:59.317095 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4254 22:12:59.319994 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4255 22:12:59.323452 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4256 22:12:59.330189 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4257 22:12:59.333425 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4258 22:12:59.337172 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4259 22:12:59.343498 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4260 22:12:59.346543 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4261 22:12:59.350106 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4262 22:12:59.356893 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4263 22:12:59.360063 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4264 22:12:59.363344 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4265 22:12:59.369715 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4266 22:12:59.372795 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4267 22:12:59.376498 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4268 22:12:59.383249 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4269 22:12:59.385980 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4270 22:12:59.389162 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4271 22:12:59.392934 Total UI for P1: 0, mck2ui 16
4272 22:12:59.395931 best dqsien dly found for B0: ( 0, 13, 14)
4273 22:12:59.399418 Total UI for P1: 0, mck2ui 16
4274 22:12:59.402454 best dqsien dly found for B1: ( 0, 13, 14)
4275 22:12:59.405846 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4276 22:12:59.409180 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4277 22:12:59.409269
4278 22:12:59.415957 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4279 22:12:59.419234 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4280 22:12:59.419309 [Gating] SW calibration Done
4281 22:12:59.422536 ==
4282 22:12:59.425500 Dram Type= 6, Freq= 0, CH_0, rank 1
4283 22:12:59.429239 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4284 22:12:59.429327 ==
4285 22:12:59.429392 RX Vref Scan: 0
4286 22:12:59.429453
4287 22:12:59.432287 RX Vref 0 -> 0, step: 1
4288 22:12:59.432358
4289 22:12:59.435540 RX Delay -230 -> 252, step: 16
4290 22:12:59.438883 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4291 22:12:59.442260 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4292 22:12:59.448589 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4293 22:12:59.452261 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4294 22:12:59.455792 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4295 22:12:59.458823 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4296 22:12:59.465385 iDelay=218, Bit 6, Center 41 (-134 ~ 217) 352
4297 22:12:59.468862 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4298 22:12:59.472213 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4299 22:12:59.475280 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4300 22:12:59.481700 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4301 22:12:59.485383 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4302 22:12:59.488298 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4303 22:12:59.491499 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4304 22:12:59.498150 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4305 22:12:59.501704 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4306 22:12:59.501800 ==
4307 22:12:59.505197 Dram Type= 6, Freq= 0, CH_0, rank 1
4308 22:12:59.507928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4309 22:12:59.508010 ==
4310 22:12:59.511208 DQS Delay:
4311 22:12:59.511290 DQS0 = 0, DQS1 = 0
4312 22:12:59.511356 DQM Delay:
4313 22:12:59.515047 DQM0 = 35, DQM1 = 28
4314 22:12:59.515128 DQ Delay:
4315 22:12:59.518056 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
4316 22:12:59.521319 DQ4 =33, DQ5 =25, DQ6 =41, DQ7 =49
4317 22:12:59.524527 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =17
4318 22:12:59.528072 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4319 22:12:59.528154
4320 22:12:59.528219
4321 22:12:59.528278 ==
4322 22:12:59.531224 Dram Type= 6, Freq= 0, CH_0, rank 1
4323 22:12:59.537829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4324 22:12:59.537911 ==
4325 22:12:59.537976
4326 22:12:59.538034
4327 22:12:59.538092 TX Vref Scan disable
4328 22:12:59.541691 == TX Byte 0 ==
4329 22:12:59.544438 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4330 22:12:59.551352 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4331 22:12:59.551434 == TX Byte 1 ==
4332 22:12:59.554676 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4333 22:12:59.561197 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4334 22:12:59.561308 ==
4335 22:12:59.564714 Dram Type= 6, Freq= 0, CH_0, rank 1
4336 22:12:59.567683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4337 22:12:59.567766 ==
4338 22:12:59.567832
4339 22:12:59.567892
4340 22:12:59.571239 TX Vref Scan disable
4341 22:12:59.574294 == TX Byte 0 ==
4342 22:12:59.577992 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4343 22:12:59.580960 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4344 22:12:59.584501 == TX Byte 1 ==
4345 22:12:59.587477 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4346 22:12:59.591175 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4347 22:12:59.591256
4348 22:12:59.591334 [DATLAT]
4349 22:12:59.594188 Freq=600, CH0 RK1
4350 22:12:59.594269
4351 22:12:59.597289 DATLAT Default: 0x9
4352 22:12:59.597368 0, 0xFFFF, sum = 0
4353 22:12:59.600933 1, 0xFFFF, sum = 0
4354 22:12:59.601014 2, 0xFFFF, sum = 0
4355 22:12:59.604025 3, 0xFFFF, sum = 0
4356 22:12:59.604107 4, 0xFFFF, sum = 0
4357 22:12:59.607541 5, 0xFFFF, sum = 0
4358 22:12:59.607654 6, 0xFFFF, sum = 0
4359 22:12:59.610879 7, 0xFFFF, sum = 0
4360 22:12:59.610960 8, 0x0, sum = 1
4361 22:12:59.613720 9, 0x0, sum = 2
4362 22:12:59.613802 10, 0x0, sum = 3
4363 22:12:59.617227 11, 0x0, sum = 4
4364 22:12:59.617307 best_step = 9
4365 22:12:59.617371
4366 22:12:59.617430 ==
4367 22:12:59.620625 Dram Type= 6, Freq= 0, CH_0, rank 1
4368 22:12:59.623583 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4369 22:12:59.623679 ==
4370 22:12:59.627473 RX Vref Scan: 0
4371 22:12:59.627601
4372 22:12:59.630211 RX Vref 0 -> 0, step: 1
4373 22:12:59.630291
4374 22:12:59.633659 RX Delay -195 -> 252, step: 8
4375 22:12:59.636722 iDelay=205, Bit 0, Center 32 (-123 ~ 188) 312
4376 22:12:59.640227 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4377 22:12:59.646749 iDelay=205, Bit 2, Center 32 (-123 ~ 188) 312
4378 22:12:59.650049 iDelay=205, Bit 3, Center 28 (-131 ~ 188) 320
4379 22:12:59.653245 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4380 22:12:59.656638 iDelay=205, Bit 5, Center 20 (-139 ~ 180) 320
4381 22:12:59.662995 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4382 22:12:59.666289 iDelay=205, Bit 7, Center 44 (-115 ~ 204) 320
4383 22:12:59.669923 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4384 22:12:59.673528 iDelay=205, Bit 9, Center 12 (-147 ~ 172) 320
4385 22:12:59.679989 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4386 22:12:59.683119 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4387 22:12:59.685914 iDelay=205, Bit 12, Center 32 (-131 ~ 196) 328
4388 22:12:59.689563 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4389 22:12:59.695751 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4390 22:12:59.699296 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4391 22:12:59.699376 ==
4392 22:12:59.702420 Dram Type= 6, Freq= 0, CH_0, rank 1
4393 22:12:59.706118 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4394 22:12:59.706198 ==
4395 22:12:59.709219 DQS Delay:
4396 22:12:59.709298 DQS0 = 0, DQS1 = 0
4397 22:12:59.709361 DQM Delay:
4398 22:12:59.712930 DQM0 = 33, DQM1 = 27
4399 22:12:59.713010 DQ Delay:
4400 22:12:59.715822 DQ0 =32, DQ1 =36, DQ2 =32, DQ3 =28
4401 22:12:59.718905 DQ4 =32, DQ5 =20, DQ6 =44, DQ7 =44
4402 22:12:59.722396 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
4403 22:12:59.725538 DQ12 =32, DQ13 =36, DQ14 =36, DQ15 =36
4404 22:12:59.725620
4405 22:12:59.725706
4406 22:12:59.735300 [DQSOSCAuto] RK1, (LSB)MR18= 0x7240, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 388 ps
4407 22:12:59.738573 CH0 RK1: MR19=808, MR18=7240
4408 22:12:59.745535 CH0_RK1: MR19=0x808, MR18=0x7240, DQSOSC=388, MR23=63, INC=174, DEC=116
4409 22:12:59.745619 [RxdqsGatingPostProcess] freq 600
4410 22:12:59.751712 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4411 22:12:59.755306 Pre-setting of DQS Precalculation
4412 22:12:59.758417 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4413 22:12:59.761492 ==
4414 22:12:59.764858 Dram Type= 6, Freq= 0, CH_1, rank 0
4415 22:12:59.768193 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4416 22:12:59.768276 ==
4417 22:12:59.771596 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4418 22:12:59.778184 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4419 22:12:59.782494 [CA 0] Center 35 (5~66) winsize 62
4420 22:12:59.785422 [CA 1] Center 35 (5~66) winsize 62
4421 22:12:59.788777 [CA 2] Center 34 (4~65) winsize 62
4422 22:12:59.791747 [CA 3] Center 34 (3~65) winsize 63
4423 22:12:59.795314 [CA 4] Center 34 (4~65) winsize 62
4424 22:12:59.798295 [CA 5] Center 33 (3~64) winsize 62
4425 22:12:59.798376
4426 22:12:59.801784 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4427 22:12:59.801865
4428 22:12:59.805489 [CATrainingPosCal] consider 1 rank data
4429 22:12:59.808412 u2DelayCellTimex100 = 270/100 ps
4430 22:12:59.811452 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4431 22:12:59.818081 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4432 22:12:59.821791 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4433 22:12:59.824657 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4434 22:12:59.827901 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4435 22:12:59.831041 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4436 22:12:59.831123
4437 22:12:59.834466 CA PerBit enable=1, Macro0, CA PI delay=33
4438 22:12:59.834548
4439 22:12:59.837668 [CBTSetCACLKResult] CA Dly = 33
4440 22:12:59.841034 CS Dly: 4 (0~35)
4441 22:12:59.841115 ==
4442 22:12:59.844400 Dram Type= 6, Freq= 0, CH_1, rank 1
4443 22:12:59.847888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4444 22:12:59.847992 ==
4445 22:12:59.854633 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4446 22:12:59.857506 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4447 22:12:59.862505 [CA 0] Center 35 (5~66) winsize 62
4448 22:12:59.865557 [CA 1] Center 35 (5~66) winsize 62
4449 22:12:59.868926 [CA 2] Center 34 (4~65) winsize 62
4450 22:12:59.871850 [CA 3] Center 34 (3~65) winsize 63
4451 22:12:59.875500 [CA 4] Center 34 (4~65) winsize 62
4452 22:12:59.878993 [CA 5] Center 33 (3~64) winsize 62
4453 22:12:59.879075
4454 22:12:59.882315 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4455 22:12:59.882415
4456 22:12:59.885496 [CATrainingPosCal] consider 2 rank data
4457 22:12:59.888503 u2DelayCellTimex100 = 270/100 ps
4458 22:12:59.892110 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4459 22:12:59.898353 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4460 22:12:59.901663 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4461 22:12:59.905444 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4462 22:12:59.908469 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4463 22:12:59.911568 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4464 22:12:59.911657
4465 22:12:59.915116 CA PerBit enable=1, Macro0, CA PI delay=33
4466 22:12:59.915198
4467 22:12:59.918032 [CBTSetCACLKResult] CA Dly = 33
4468 22:12:59.921491 CS Dly: 4 (0~36)
4469 22:12:59.921572
4470 22:12:59.924699 ----->DramcWriteLeveling(PI) begin...
4471 22:12:59.924783 ==
4472 22:12:59.928329 Dram Type= 6, Freq= 0, CH_1, rank 0
4473 22:12:59.931640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4474 22:12:59.931722 ==
4475 22:12:59.935141 Write leveling (Byte 0): 29 => 29
4476 22:12:59.937804 Write leveling (Byte 1): 29 => 29
4477 22:12:59.941707 DramcWriteLeveling(PI) end<-----
4478 22:12:59.941790
4479 22:12:59.941855 ==
4480 22:12:59.944532 Dram Type= 6, Freq= 0, CH_1, rank 0
4481 22:12:59.947891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4482 22:12:59.947979 ==
4483 22:12:59.951412 [Gating] SW mode calibration
4484 22:12:59.958182 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4485 22:12:59.964519 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4486 22:12:59.968181 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4487 22:12:59.971251 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4488 22:12:59.977692 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4489 22:12:59.981184 0 9 12 | B1->B0 | 2f2f 2f2f | 1 1 | (1 0) (1 1)
4490 22:12:59.984315 0 9 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4491 22:12:59.991003 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4492 22:12:59.994494 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4493 22:12:59.997675 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4494 22:13:00.004694 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4495 22:13:00.007168 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4496 22:13:00.010814 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4497 22:13:00.017471 0 10 12 | B1->B0 | 2c2c 3131 | 0 0 | (0 0) (0 0)
4498 22:13:00.020375 0 10 16 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
4499 22:13:00.023959 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4500 22:13:00.030664 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4501 22:13:00.034015 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4502 22:13:00.037663 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4503 22:13:00.043748 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4504 22:13:00.046949 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4505 22:13:00.050665 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4506 22:13:00.056887 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4507 22:13:00.060186 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4508 22:13:00.063483 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4509 22:13:00.070083 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4510 22:13:00.073273 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4511 22:13:00.076803 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4512 22:13:00.083316 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4513 22:13:00.086513 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4514 22:13:00.090038 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4515 22:13:00.096825 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4516 22:13:00.099758 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4517 22:13:00.103387 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4518 22:13:00.110046 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4519 22:13:00.112820 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4520 22:13:00.116353 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4521 22:13:00.123012 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4522 22:13:00.126590 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4523 22:13:00.129622 Total UI for P1: 0, mck2ui 16
4524 22:13:00.133264 best dqsien dly found for B0: ( 0, 13, 12)
4525 22:13:00.136208 Total UI for P1: 0, mck2ui 16
4526 22:13:00.139795 best dqsien dly found for B1: ( 0, 13, 14)
4527 22:13:00.142818 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4528 22:13:00.146173 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4529 22:13:00.146248
4530 22:13:00.149869 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4531 22:13:00.153216 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4532 22:13:00.156471 [Gating] SW calibration Done
4533 22:13:00.156552 ==
4534 22:13:00.159399 Dram Type= 6, Freq= 0, CH_1, rank 0
4535 22:13:00.162500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4536 22:13:00.166071 ==
4537 22:13:00.166172 RX Vref Scan: 0
4538 22:13:00.166274
4539 22:13:00.169257 RX Vref 0 -> 0, step: 1
4540 22:13:00.169342
4541 22:13:00.172561 RX Delay -230 -> 252, step: 16
4542 22:13:00.175815 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4543 22:13:00.179003 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4544 22:13:00.182399 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4545 22:13:00.189138 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4546 22:13:00.192217 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4547 22:13:00.195690 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4548 22:13:00.199072 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4549 22:13:00.205510 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4550 22:13:00.208876 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4551 22:13:00.211986 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4552 22:13:00.215693 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4553 22:13:00.222053 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4554 22:13:00.224871 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4555 22:13:00.228586 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4556 22:13:00.231627 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4557 22:13:00.238411 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4558 22:13:00.238484 ==
4559 22:13:00.241977 Dram Type= 6, Freq= 0, CH_1, rank 0
4560 22:13:00.245007 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4561 22:13:00.245080 ==
4562 22:13:00.245177 DQS Delay:
4563 22:13:00.248392 DQS0 = 0, DQS1 = 0
4564 22:13:00.248487 DQM Delay:
4565 22:13:00.251941 DQM0 = 39, DQM1 = 27
4566 22:13:00.252010 DQ Delay:
4567 22:13:00.255263 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =33
4568 22:13:00.258142 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4569 22:13:00.261340 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4570 22:13:00.264664 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4571 22:13:00.264742
4572 22:13:00.264805
4573 22:13:00.264862 ==
4574 22:13:00.267896 Dram Type= 6, Freq= 0, CH_1, rank 0
4575 22:13:00.271295 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4576 22:13:00.271390 ==
4577 22:13:00.274557
4578 22:13:00.274651
4579 22:13:00.274738 TX Vref Scan disable
4580 22:13:00.278006 == TX Byte 0 ==
4581 22:13:00.281203 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4582 22:13:00.284296 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4583 22:13:00.287833 == TX Byte 1 ==
4584 22:13:00.290913 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4585 22:13:00.294420 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4586 22:13:00.297573 ==
4587 22:13:00.300552 Dram Type= 6, Freq= 0, CH_1, rank 0
4588 22:13:00.303891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4589 22:13:00.303961 ==
4590 22:13:00.304022
4591 22:13:00.304079
4592 22:13:00.307438 TX Vref Scan disable
4593 22:13:00.310527 == TX Byte 0 ==
4594 22:13:00.313568 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4595 22:13:00.317489 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4596 22:13:00.320380 == TX Byte 1 ==
4597 22:13:00.323922 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4598 22:13:00.326826 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4599 22:13:00.326906
4600 22:13:00.326968 [DATLAT]
4601 22:13:00.330549 Freq=600, CH1 RK0
4602 22:13:00.330617
4603 22:13:00.333503 DATLAT Default: 0x9
4604 22:13:00.333573 0, 0xFFFF, sum = 0
4605 22:13:00.337245 1, 0xFFFF, sum = 0
4606 22:13:00.337316 2, 0xFFFF, sum = 0
4607 22:13:00.340168 3, 0xFFFF, sum = 0
4608 22:13:00.340271 4, 0xFFFF, sum = 0
4609 22:13:00.343192 5, 0xFFFF, sum = 0
4610 22:13:00.343262 6, 0xFFFF, sum = 0
4611 22:13:00.346766 7, 0xFFFF, sum = 0
4612 22:13:00.346863 8, 0x0, sum = 1
4613 22:13:00.349716 9, 0x0, sum = 2
4614 22:13:00.349799 10, 0x0, sum = 3
4615 22:13:00.353442 11, 0x0, sum = 4
4616 22:13:00.353525 best_step = 9
4617 22:13:00.353596
4618 22:13:00.353664 ==
4619 22:13:00.356343 Dram Type= 6, Freq= 0, CH_1, rank 0
4620 22:13:00.359660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4621 22:13:00.359742 ==
4622 22:13:00.362918 RX Vref Scan: 1
4623 22:13:00.362998
4624 22:13:00.366598 RX Vref 0 -> 0, step: 1
4625 22:13:00.366704
4626 22:13:00.366797 RX Delay -195 -> 252, step: 8
4627 22:13:00.369882
4628 22:13:00.369964 Set Vref, RX VrefLevel [Byte0]: 52
4629 22:13:00.372703 [Byte1]: 53
4630 22:13:00.378239
4631 22:13:00.378320 Final RX Vref Byte 0 = 52 to rank0
4632 22:13:00.381005 Final RX Vref Byte 1 = 53 to rank0
4633 22:13:00.384378 Final RX Vref Byte 0 = 52 to rank1
4634 22:13:00.387756 Final RX Vref Byte 1 = 53 to rank1==
4635 22:13:00.391307 Dram Type= 6, Freq= 0, CH_1, rank 0
4636 22:13:00.397942 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4637 22:13:00.398019 ==
4638 22:13:00.398083 DQS Delay:
4639 22:13:00.400912 DQS0 = 0, DQS1 = 0
4640 22:13:00.400993 DQM Delay:
4641 22:13:00.401083 DQM0 = 37, DQM1 = 28
4642 22:13:00.404711 DQ Delay:
4643 22:13:00.407475 DQ0 =44, DQ1 =32, DQ2 =24, DQ3 =36
4644 22:13:00.410891 DQ4 =32, DQ5 =48, DQ6 =48, DQ7 =36
4645 22:13:00.414076 DQ8 =12, DQ9 =16, DQ10 =28, DQ11 =20
4646 22:13:00.417496 DQ12 =40, DQ13 =36, DQ14 =36, DQ15 =36
4647 22:13:00.417567
4648 22:13:00.417626
4649 22:13:00.424290 [DQSOSCAuto] RK0, (LSB)MR18= 0x2330, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 403 ps
4650 22:13:00.427573 CH1 RK0: MR19=808, MR18=2330
4651 22:13:00.433804 CH1_RK0: MR19=0x808, MR18=0x2330, DQSOSC=400, MR23=63, INC=163, DEC=109
4652 22:13:00.433876
4653 22:13:00.437281 ----->DramcWriteLeveling(PI) begin...
4654 22:13:00.437360 ==
4655 22:13:00.440860 Dram Type= 6, Freq= 0, CH_1, rank 1
4656 22:13:00.443874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4657 22:13:00.443950 ==
4658 22:13:00.447571 Write leveling (Byte 0): 31 => 31
4659 22:13:00.450621 Write leveling (Byte 1): 31 => 31
4660 22:13:00.453509 DramcWriteLeveling(PI) end<-----
4661 22:13:00.453580
4662 22:13:00.453641 ==
4663 22:13:00.457229 Dram Type= 6, Freq= 0, CH_1, rank 1
4664 22:13:00.460183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4665 22:13:00.463763 ==
4666 22:13:00.463845 [Gating] SW mode calibration
4667 22:13:00.473509 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4668 22:13:00.476771 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4669 22:13:00.479944 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4670 22:13:00.486798 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4671 22:13:00.490078 0 9 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
4672 22:13:00.493352 0 9 12 | B1->B0 | 3030 2f2f | 0 1 | (0 0) (1 0)
4673 22:13:00.500258 0 9 16 | B1->B0 | 2929 2323 | 1 0 | (1 0) (0 0)
4674 22:13:00.503152 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4675 22:13:00.506781 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4676 22:13:00.513158 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4677 22:13:00.516812 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4678 22:13:00.519922 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4679 22:13:00.526326 0 10 8 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (1 1)
4680 22:13:00.529640 0 10 12 | B1->B0 | 3131 3c3c | 0 0 | (0 0) (0 0)
4681 22:13:00.532901 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4682 22:13:00.539711 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4683 22:13:00.542631 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4684 22:13:00.546246 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4685 22:13:00.552960 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4686 22:13:00.556487 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4687 22:13:00.559654 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4688 22:13:00.566224 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4689 22:13:00.569213 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4690 22:13:00.572429 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4691 22:13:00.579056 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4692 22:13:00.582419 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4693 22:13:00.585471 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4694 22:13:00.592623 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4695 22:13:00.595351 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4696 22:13:00.598609 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4697 22:13:00.605446 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4698 22:13:00.609025 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4699 22:13:00.612097 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4700 22:13:00.618998 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4701 22:13:00.622056 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4702 22:13:00.625566 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4703 22:13:00.632079 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4704 22:13:00.635021 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4705 22:13:00.638810 Total UI for P1: 0, mck2ui 16
4706 22:13:00.641738 best dqsien dly found for B0: ( 0, 13, 10)
4707 22:13:00.645304 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4708 22:13:00.648883 Total UI for P1: 0, mck2ui 16
4709 22:13:00.652061 best dqsien dly found for B1: ( 0, 13, 12)
4710 22:13:00.654817 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4711 22:13:00.658534 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4712 22:13:00.661440
4713 22:13:00.664999 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4714 22:13:00.668011 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4715 22:13:00.671711 [Gating] SW calibration Done
4716 22:13:00.671793 ==
4717 22:13:00.674553 Dram Type= 6, Freq= 0, CH_1, rank 1
4718 22:13:00.678096 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4719 22:13:00.678179 ==
4720 22:13:00.680924 RX Vref Scan: 0
4721 22:13:00.681007
4722 22:13:00.681072 RX Vref 0 -> 0, step: 1
4723 22:13:00.681133
4724 22:13:00.684161 RX Delay -230 -> 252, step: 16
4725 22:13:00.687462 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4726 22:13:00.694323 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4727 22:13:00.697702 iDelay=218, Bit 2, Center 17 (-150 ~ 185) 336
4728 22:13:00.700612 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4729 22:13:00.703968 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4730 22:13:00.710389 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4731 22:13:00.713886 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4732 22:13:00.716915 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4733 22:13:00.720315 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4734 22:13:00.727046 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4735 22:13:00.730583 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4736 22:13:00.733593 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4737 22:13:00.737223 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4738 22:13:00.743473 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4739 22:13:00.746976 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4740 22:13:00.749769 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4741 22:13:00.749851 ==
4742 22:13:00.753126 Dram Type= 6, Freq= 0, CH_1, rank 1
4743 22:13:00.756837 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4744 22:13:00.759714 ==
4745 22:13:00.759796 DQS Delay:
4746 22:13:00.759860 DQS0 = 0, DQS1 = 0
4747 22:13:00.763332 DQM Delay:
4748 22:13:00.763414 DQM0 = 35, DQM1 = 29
4749 22:13:00.766463 DQ Delay:
4750 22:13:00.770088 DQ0 =33, DQ1 =33, DQ2 =17, DQ3 =33
4751 22:13:00.770170 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4752 22:13:00.773176 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4753 22:13:00.776252 DQ12 =33, DQ13 =41, DQ14 =33, DQ15 =33
4754 22:13:00.779846
4755 22:13:00.779928
4756 22:13:00.779992 ==
4757 22:13:00.782710 Dram Type= 6, Freq= 0, CH_1, rank 1
4758 22:13:00.786324 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4759 22:13:00.786406 ==
4760 22:13:00.786472
4761 22:13:00.786532
4762 22:13:00.789611 TX Vref Scan disable
4763 22:13:00.789693 == TX Byte 0 ==
4764 22:13:00.796397 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4765 22:13:00.799377 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4766 22:13:00.799485 == TX Byte 1 ==
4767 22:13:00.806248 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4768 22:13:00.809175 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4769 22:13:00.809257 ==
4770 22:13:00.812437 Dram Type= 6, Freq= 0, CH_1, rank 1
4771 22:13:00.815572 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4772 22:13:00.815662 ==
4773 22:13:00.815727
4774 22:13:00.819359
4775 22:13:00.819440 TX Vref Scan disable
4776 22:13:00.822365 == TX Byte 0 ==
4777 22:13:00.825744 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4778 22:13:00.832543 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4779 22:13:00.832626 == TX Byte 1 ==
4780 22:13:00.835910 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4781 22:13:00.842249 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4782 22:13:00.842331
4783 22:13:00.842396 [DATLAT]
4784 22:13:00.842455 Freq=600, CH1 RK1
4785 22:13:00.842514
4786 22:13:00.845953 DATLAT Default: 0x9
4787 22:13:00.848798 0, 0xFFFF, sum = 0
4788 22:13:00.848882 1, 0xFFFF, sum = 0
4789 22:13:00.852322 2, 0xFFFF, sum = 0
4790 22:13:00.852404 3, 0xFFFF, sum = 0
4791 22:13:00.855942 4, 0xFFFF, sum = 0
4792 22:13:00.856026 5, 0xFFFF, sum = 0
4793 22:13:00.859164 6, 0xFFFF, sum = 0
4794 22:13:00.859247 7, 0xFFFF, sum = 0
4795 22:13:00.862158 8, 0x0, sum = 1
4796 22:13:00.862241 9, 0x0, sum = 2
4797 22:13:00.865622 10, 0x0, sum = 3
4798 22:13:00.865705 11, 0x0, sum = 4
4799 22:13:00.865772 best_step = 9
4800 22:13:00.865831
4801 22:13:00.868782 ==
4802 22:13:00.871591 Dram Type= 6, Freq= 0, CH_1, rank 1
4803 22:13:00.875295 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4804 22:13:00.875378 ==
4805 22:13:00.875443 RX Vref Scan: 0
4806 22:13:00.875504
4807 22:13:00.878461 RX Vref 0 -> 0, step: 1
4808 22:13:00.878543
4809 22:13:00.881912 RX Delay -195 -> 252, step: 8
4810 22:13:00.888723 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4811 22:13:00.892029 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4812 22:13:00.894911 iDelay=205, Bit 2, Center 20 (-139 ~ 180) 320
4813 22:13:00.898276 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4814 22:13:00.901587 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4815 22:13:00.908242 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4816 22:13:00.911481 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4817 22:13:00.914699 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4818 22:13:00.918188 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4819 22:13:00.925090 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4820 22:13:00.927861 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4821 22:13:00.931498 iDelay=205, Bit 11, Center 24 (-139 ~ 188) 328
4822 22:13:00.934759 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4823 22:13:00.940878 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4824 22:13:00.944760 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4825 22:13:00.947530 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4826 22:13:00.947624 ==
4827 22:13:00.951289 Dram Type= 6, Freq= 0, CH_1, rank 1
4828 22:13:00.957484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4829 22:13:00.957557 ==
4830 22:13:00.957620 DQS Delay:
4831 22:13:00.957702 DQS0 = 0, DQS1 = 0
4832 22:13:00.960790 DQM Delay:
4833 22:13:00.960861 DQM0 = 35, DQM1 = 30
4834 22:13:00.964018 DQ Delay:
4835 22:13:00.967195 DQ0 =40, DQ1 =32, DQ2 =20, DQ3 =32
4836 22:13:00.970949 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =32
4837 22:13:00.971019 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =24
4838 22:13:00.977541 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4839 22:13:00.977625
4840 22:13:00.977687
4841 22:13:00.983797 [DQSOSCAuto] RK1, (LSB)MR18= 0x3e5e, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 398 ps
4842 22:13:00.987245 CH1 RK1: MR19=808, MR18=3E5E
4843 22:13:00.993854 CH1_RK1: MR19=0x808, MR18=0x3E5E, DQSOSC=392, MR23=63, INC=170, DEC=113
4844 22:13:00.996940 [RxdqsGatingPostProcess] freq 600
4845 22:13:01.000271 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4846 22:13:01.003533 Pre-setting of DQS Precalculation
4847 22:13:01.010131 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4848 22:13:01.017011 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4849 22:13:01.024364 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4850 22:13:01.024449
4851 22:13:01.024514
4852 22:13:01.026715 [Calibration Summary] 1200 Mbps
4853 22:13:01.026797 CH 0, Rank 0
4854 22:13:01.030282 SW Impedance : PASS
4855 22:13:01.033720 DUTY Scan : NO K
4856 22:13:01.033802 ZQ Calibration : PASS
4857 22:13:01.036852 Jitter Meter : NO K
4858 22:13:01.039739 CBT Training : PASS
4859 22:13:01.039821 Write leveling : PASS
4860 22:13:01.043266 RX DQS gating : PASS
4861 22:13:01.046633 RX DQ/DQS(RDDQC) : PASS
4862 22:13:01.046715 TX DQ/DQS : PASS
4863 22:13:01.050025 RX DATLAT : PASS
4864 22:13:01.053556 RX DQ/DQS(Engine): PASS
4865 22:13:01.053638 TX OE : NO K
4866 22:13:01.056606 All Pass.
4867 22:13:01.056688
4868 22:13:01.056752 CH 0, Rank 1
4869 22:13:01.059726 SW Impedance : PASS
4870 22:13:01.059815 DUTY Scan : NO K
4871 22:13:01.063213 ZQ Calibration : PASS
4872 22:13:01.066581 Jitter Meter : NO K
4873 22:13:01.066663 CBT Training : PASS
4874 22:13:01.070030 Write leveling : PASS
4875 22:13:01.073366 RX DQS gating : PASS
4876 22:13:01.073447 RX DQ/DQS(RDDQC) : PASS
4877 22:13:01.076431 TX DQ/DQS : PASS
4878 22:13:01.080027 RX DATLAT : PASS
4879 22:13:01.080109 RX DQ/DQS(Engine): PASS
4880 22:13:01.083120 TX OE : NO K
4881 22:13:01.083203 All Pass.
4882 22:13:01.083268
4883 22:13:01.086001 CH 1, Rank 0
4884 22:13:01.086083 SW Impedance : PASS
4885 22:13:01.089633 DUTY Scan : NO K
4886 22:13:01.089716 ZQ Calibration : PASS
4887 22:13:01.092546 Jitter Meter : NO K
4888 22:13:01.096311 CBT Training : PASS
4889 22:13:01.096393 Write leveling : PASS
4890 22:13:01.099299 RX DQS gating : PASS
4891 22:13:01.102782 RX DQ/DQS(RDDQC) : PASS
4892 22:13:01.102864 TX DQ/DQS : PASS
4893 22:13:01.105991 RX DATLAT : PASS
4894 22:13:01.109414 RX DQ/DQS(Engine): PASS
4895 22:13:01.109496 TX OE : NO K
4896 22:13:01.112724 All Pass.
4897 22:13:01.112806
4898 22:13:01.112872 CH 1, Rank 1
4899 22:13:01.116212 SW Impedance : PASS
4900 22:13:01.116294 DUTY Scan : NO K
4901 22:13:01.119239 ZQ Calibration : PASS
4902 22:13:01.122525 Jitter Meter : NO K
4903 22:13:01.122607 CBT Training : PASS
4904 22:13:01.125988 Write leveling : PASS
4905 22:13:01.129181 RX DQS gating : PASS
4906 22:13:01.129262 RX DQ/DQS(RDDQC) : PASS
4907 22:13:01.132402 TX DQ/DQS : PASS
4908 22:13:01.135727 RX DATLAT : PASS
4909 22:13:01.135809 RX DQ/DQS(Engine): PASS
4910 22:13:01.139082 TX OE : NO K
4911 22:13:01.139165 All Pass.
4912 22:13:01.139230
4913 22:13:01.142622 DramC Write-DBI off
4914 22:13:01.145581 PER_BANK_REFRESH: Hybrid Mode
4915 22:13:01.145662 TX_TRACKING: ON
4916 22:13:01.155505 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4917 22:13:01.159173 [FAST_K] Save calibration result to emmc
4918 22:13:01.162270 dramc_set_vcore_voltage set vcore to 662500
4919 22:13:01.165792 Read voltage for 933, 3
4920 22:13:01.165887 Vio18 = 0
4921 22:13:01.165954 Vcore = 662500
4922 22:13:01.168765 Vdram = 0
4923 22:13:01.168847 Vddq = 0
4924 22:13:01.168912 Vmddr = 0
4925 22:13:01.175373 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4926 22:13:01.179056 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4927 22:13:01.181861 MEM_TYPE=3, freq_sel=17
4928 22:13:01.185642 sv_algorithm_assistance_LP4_1600
4929 22:13:01.188741 ============ PULL DRAM RESETB DOWN ============
4930 22:13:01.191756 ========== PULL DRAM RESETB DOWN end =========
4931 22:13:01.198594 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4932 22:13:01.202189 ===================================
4933 22:13:01.202272 LPDDR4 DRAM CONFIGURATION
4934 22:13:01.205161 ===================================
4935 22:13:01.208245 EX_ROW_EN[0] = 0x0
4936 22:13:01.211515 EX_ROW_EN[1] = 0x0
4937 22:13:01.211605 LP4Y_EN = 0x0
4938 22:13:01.215245 WORK_FSP = 0x0
4939 22:13:01.215327 WL = 0x3
4940 22:13:01.218691 RL = 0x3
4941 22:13:01.218774 BL = 0x2
4942 22:13:01.221715 RPST = 0x0
4943 22:13:01.221797 RD_PRE = 0x0
4944 22:13:01.224920 WR_PRE = 0x1
4945 22:13:01.225003 WR_PST = 0x0
4946 22:13:01.228397 DBI_WR = 0x0
4947 22:13:01.228479 DBI_RD = 0x0
4948 22:13:01.231178 OTF = 0x1
4949 22:13:01.234648 ===================================
4950 22:13:01.237858 ===================================
4951 22:13:01.237940 ANA top config
4952 22:13:01.241345 ===================================
4953 22:13:01.244713 DLL_ASYNC_EN = 0
4954 22:13:01.247831 ALL_SLAVE_EN = 1
4955 22:13:01.251304 NEW_RANK_MODE = 1
4956 22:13:01.254406 DLL_IDLE_MODE = 1
4957 22:13:01.254488 LP45_APHY_COMB_EN = 1
4958 22:13:01.257997 TX_ODT_DIS = 1
4959 22:13:01.260859 NEW_8X_MODE = 1
4960 22:13:01.264464 ===================================
4961 22:13:01.267495 ===================================
4962 22:13:01.270917 data_rate = 1866
4963 22:13:01.273944 CKR = 1
4964 22:13:01.274052 DQ_P2S_RATIO = 8
4965 22:13:01.277362 ===================================
4966 22:13:01.280988 CA_P2S_RATIO = 8
4967 22:13:01.284330 DQ_CA_OPEN = 0
4968 22:13:01.287385 DQ_SEMI_OPEN = 0
4969 22:13:01.290266 CA_SEMI_OPEN = 0
4970 22:13:01.294185 CA_FULL_RATE = 0
4971 22:13:01.294277 DQ_CKDIV4_EN = 1
4972 22:13:01.297170 CA_CKDIV4_EN = 1
4973 22:13:01.300158 CA_PREDIV_EN = 0
4974 22:13:01.303968 PH8_DLY = 0
4975 22:13:01.307271 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4976 22:13:01.310355 DQ_AAMCK_DIV = 4
4977 22:13:01.313457 CA_AAMCK_DIV = 4
4978 22:13:01.313533 CA_ADMCK_DIV = 4
4979 22:13:01.316974 DQ_TRACK_CA_EN = 0
4980 22:13:01.319837 CA_PICK = 933
4981 22:13:01.323206 CA_MCKIO = 933
4982 22:13:01.326533 MCKIO_SEMI = 0
4983 22:13:01.329927 PLL_FREQ = 3732
4984 22:13:01.333366 DQ_UI_PI_RATIO = 32
4985 22:13:01.333439 CA_UI_PI_RATIO = 0
4986 22:13:01.336623 ===================================
4987 22:13:01.340251 ===================================
4988 22:13:01.343089 memory_type:LPDDR4
4989 22:13:01.346227 GP_NUM : 10
4990 22:13:01.346306 SRAM_EN : 1
4991 22:13:01.349780 MD32_EN : 0
4992 22:13:01.352918 ===================================
4993 22:13:01.356162 [ANA_INIT] >>>>>>>>>>>>>>
4994 22:13:01.359895 <<<<<< [CONFIGURE PHASE]: ANA_TX
4995 22:13:01.363188 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4996 22:13:01.366348 ===================================
4997 22:13:01.366424 data_rate = 1866,PCW = 0X8f00
4998 22:13:01.369640 ===================================
4999 22:13:01.373363 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5000 22:13:01.379371 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5001 22:13:01.386297 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5002 22:13:01.389801 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5003 22:13:01.393284 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5004 22:13:01.396496 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5005 22:13:01.399427 [ANA_INIT] flow start
5006 22:13:01.402548 [ANA_INIT] PLL >>>>>>>>
5007 22:13:01.402629 [ANA_INIT] PLL <<<<<<<<
5008 22:13:01.406347 [ANA_INIT] MIDPI >>>>>>>>
5009 22:13:01.409164 [ANA_INIT] MIDPI <<<<<<<<
5010 22:13:01.409234 [ANA_INIT] DLL >>>>>>>>
5011 22:13:01.412595 [ANA_INIT] flow end
5012 22:13:01.416240 ============ LP4 DIFF to SE enter ============
5013 22:13:01.419025 ============ LP4 DIFF to SE exit ============
5014 22:13:01.422379 [ANA_INIT] <<<<<<<<<<<<<
5015 22:13:01.425930 [Flow] Enable top DCM control >>>>>
5016 22:13:01.429394 [Flow] Enable top DCM control <<<<<
5017 22:13:01.432320 Enable DLL master slave shuffle
5018 22:13:01.439039 ==============================================================
5019 22:13:01.439146 Gating Mode config
5020 22:13:01.445768 ==============================================================
5021 22:13:01.449309 Config description:
5022 22:13:01.455368 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5023 22:13:01.465627 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5024 22:13:01.468636 SELPH_MODE 0: By rank 1: By Phase
5025 22:13:01.475147 ==============================================================
5026 22:13:01.478337 GAT_TRACK_EN = 1
5027 22:13:01.478419 RX_GATING_MODE = 2
5028 22:13:01.482026 RX_GATING_TRACK_MODE = 2
5029 22:13:01.485114 SELPH_MODE = 1
5030 22:13:01.488095 PICG_EARLY_EN = 1
5031 22:13:01.491876 VALID_LAT_VALUE = 1
5032 22:13:01.498264 ==============================================================
5033 22:13:01.501260 Enter into Gating configuration >>>>
5034 22:13:01.504446 Exit from Gating configuration <<<<
5035 22:13:01.507989 Enter into DVFS_PRE_config >>>>>
5036 22:13:01.517731 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5037 22:13:01.521680 Exit from DVFS_PRE_config <<<<<
5038 22:13:01.524509 Enter into PICG configuration >>>>
5039 22:13:01.527466 Exit from PICG configuration <<<<
5040 22:13:01.530844 [RX_INPUT] configuration >>>>>
5041 22:13:01.534113 [RX_INPUT] configuration <<<<<
5042 22:13:01.537591 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5043 22:13:01.544422 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5044 22:13:01.550872 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5045 22:13:01.557464 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5046 22:13:01.564252 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5047 22:13:01.567559 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5048 22:13:01.573709 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5049 22:13:01.577195 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5050 22:13:01.580822 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5051 22:13:01.583859 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5052 22:13:01.590519 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5053 22:13:01.593716 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5054 22:13:01.597287 ===================================
5055 22:13:01.599968 LPDDR4 DRAM CONFIGURATION
5056 22:13:01.603145 ===================================
5057 22:13:01.603229 EX_ROW_EN[0] = 0x0
5058 22:13:01.607017 EX_ROW_EN[1] = 0x0
5059 22:13:01.607099 LP4Y_EN = 0x0
5060 22:13:01.609940 WORK_FSP = 0x0
5061 22:13:01.613651 WL = 0x3
5062 22:13:01.613733 RL = 0x3
5063 22:13:01.616582 BL = 0x2
5064 22:13:01.616665 RPST = 0x0
5065 22:13:01.620027 RD_PRE = 0x0
5066 22:13:01.620110 WR_PRE = 0x1
5067 22:13:01.623215 WR_PST = 0x0
5068 22:13:01.623298 DBI_WR = 0x0
5069 22:13:01.626219 DBI_RD = 0x0
5070 22:13:01.626342 OTF = 0x1
5071 22:13:01.630047 ===================================
5072 22:13:01.632872 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5073 22:13:01.639541 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5074 22:13:01.642674 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5075 22:13:01.646051 ===================================
5076 22:13:01.649554 LPDDR4 DRAM CONFIGURATION
5077 22:13:01.652773 ===================================
5078 22:13:01.652849 EX_ROW_EN[0] = 0x10
5079 22:13:01.656257 EX_ROW_EN[1] = 0x0
5080 22:13:01.659312 LP4Y_EN = 0x0
5081 22:13:01.659385 WORK_FSP = 0x0
5082 22:13:01.662531 WL = 0x3
5083 22:13:01.662605 RL = 0x3
5084 22:13:01.665745 BL = 0x2
5085 22:13:01.665826 RPST = 0x0
5086 22:13:01.668955 RD_PRE = 0x0
5087 22:13:01.669031 WR_PRE = 0x1
5088 22:13:01.672224 WR_PST = 0x0
5089 22:13:01.672325 DBI_WR = 0x0
5090 22:13:01.675684 DBI_RD = 0x0
5091 22:13:01.675791 OTF = 0x1
5092 22:13:01.678901 ===================================
5093 22:13:01.685662 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5094 22:13:01.690323 nWR fixed to 30
5095 22:13:01.693488 [ModeRegInit_LP4] CH0 RK0
5096 22:13:01.693571 [ModeRegInit_LP4] CH0 RK1
5097 22:13:01.696487 [ModeRegInit_LP4] CH1 RK0
5098 22:13:01.700205 [ModeRegInit_LP4] CH1 RK1
5099 22:13:01.700293 match AC timing 9
5100 22:13:01.706643 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5101 22:13:01.710072 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5102 22:13:01.712739 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5103 22:13:01.719931 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5104 22:13:01.722959 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5105 22:13:01.723067 ==
5106 22:13:01.726596 Dram Type= 6, Freq= 0, CH_0, rank 0
5107 22:13:01.729616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5108 22:13:01.729700 ==
5109 22:13:01.736106 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5110 22:13:01.742763 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5111 22:13:01.745852 [CA 0] Center 38 (8~69) winsize 62
5112 22:13:01.749293 [CA 1] Center 38 (8~68) winsize 61
5113 22:13:01.752294 [CA 2] Center 35 (5~65) winsize 61
5114 22:13:01.756229 [CA 3] Center 35 (5~65) winsize 61
5115 22:13:01.758973 [CA 4] Center 34 (4~65) winsize 62
5116 22:13:01.762406 [CA 5] Center 33 (3~64) winsize 62
5117 22:13:01.762492
5118 22:13:01.765654 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5119 22:13:01.765740
5120 22:13:01.768840 [CATrainingPosCal] consider 1 rank data
5121 22:13:01.772525 u2DelayCellTimex100 = 270/100 ps
5122 22:13:01.775992 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5123 22:13:01.778702 CA1 delay=38 (8~68),Diff = 5 PI (31 cell)
5124 22:13:01.782077 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5125 22:13:01.788590 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5126 22:13:01.791920 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5127 22:13:01.795258 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5128 22:13:01.795340
5129 22:13:01.798863 CA PerBit enable=1, Macro0, CA PI delay=33
5130 22:13:01.798940
5131 22:13:01.802047 [CBTSetCACLKResult] CA Dly = 33
5132 22:13:01.802152 CS Dly: 7 (0~38)
5133 22:13:01.805232 ==
5134 22:13:01.805316 Dram Type= 6, Freq= 0, CH_0, rank 1
5135 22:13:01.811585 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5136 22:13:01.811691 ==
5137 22:13:01.815175 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5138 22:13:01.821513 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5139 22:13:01.825290 [CA 0] Center 38 (8~69) winsize 62
5140 22:13:01.828489 [CA 1] Center 38 (8~69) winsize 62
5141 22:13:01.831468 [CA 2] Center 35 (5~66) winsize 62
5142 22:13:01.835182 [CA 3] Center 34 (4~65) winsize 62
5143 22:13:01.838127 [CA 4] Center 33 (3~64) winsize 62
5144 22:13:01.841616 [CA 5] Center 33 (3~64) winsize 62
5145 22:13:01.841708
5146 22:13:01.844697 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5147 22:13:01.844771
5148 22:13:01.848527 [CATrainingPosCal] consider 2 rank data
5149 22:13:01.851499 u2DelayCellTimex100 = 270/100 ps
5150 22:13:01.855059 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5151 22:13:01.861849 CA1 delay=38 (8~68),Diff = 5 PI (31 cell)
5152 22:13:01.864749 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5153 22:13:01.868695 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5154 22:13:01.871425 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5155 22:13:01.875010 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5156 22:13:01.875109
5157 22:13:01.878009 CA PerBit enable=1, Macro0, CA PI delay=33
5158 22:13:01.878097
5159 22:13:01.881622 [CBTSetCACLKResult] CA Dly = 33
5160 22:13:01.884534 CS Dly: 7 (0~38)
5161 22:13:01.884622
5162 22:13:01.888262 ----->DramcWriteLeveling(PI) begin...
5163 22:13:01.888355 ==
5164 22:13:01.891109 Dram Type= 6, Freq= 0, CH_0, rank 0
5165 22:13:01.894364 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5166 22:13:01.894543 ==
5167 22:13:01.897939 Write leveling (Byte 0): 30 => 30
5168 22:13:01.901095 Write leveling (Byte 1): 30 => 30
5169 22:13:01.904702 DramcWriteLeveling(PI) end<-----
5170 22:13:01.904776
5171 22:13:01.904839 ==
5172 22:13:01.907768 Dram Type= 6, Freq= 0, CH_0, rank 0
5173 22:13:01.911024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5174 22:13:01.911099 ==
5175 22:13:01.914332 [Gating] SW mode calibration
5176 22:13:01.921154 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5177 22:13:01.927550 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5178 22:13:01.930807 0 14 0 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (1 1)
5179 22:13:01.933938 0 14 4 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
5180 22:13:01.940657 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5181 22:13:01.943879 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5182 22:13:01.947506 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5183 22:13:01.953623 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5184 22:13:01.957160 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5185 22:13:01.960641 0 14 28 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
5186 22:13:01.967461 0 15 0 | B1->B0 | 3333 2e2e | 1 0 | (1 1) (1 1)
5187 22:13:01.970735 0 15 4 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
5188 22:13:01.973718 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5189 22:13:01.980009 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5190 22:13:01.984061 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5191 22:13:01.987281 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5192 22:13:01.993346 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5193 22:13:01.996668 0 15 28 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
5194 22:13:02.000145 1 0 0 | B1->B0 | 2f2f 4545 | 0 0 | (0 0) (0 0)
5195 22:13:02.006750 1 0 4 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
5196 22:13:02.009860 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5197 22:13:02.013207 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5198 22:13:02.019909 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5199 22:13:02.022810 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5200 22:13:02.026242 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5201 22:13:02.032932 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5202 22:13:02.036458 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5203 22:13:02.039575 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5204 22:13:02.046196 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5205 22:13:02.049267 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5206 22:13:02.052881 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5207 22:13:02.059603 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5208 22:13:02.062710 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5209 22:13:02.065850 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5210 22:13:02.072560 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5211 22:13:02.075857 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5212 22:13:02.079373 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5213 22:13:02.085718 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5214 22:13:02.089160 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5215 22:13:02.092313 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5216 22:13:02.098440 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5217 22:13:02.101864 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5218 22:13:02.108551 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5219 22:13:02.112002 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5220 22:13:02.114933 Total UI for P1: 0, mck2ui 16
5221 22:13:02.118192 best dqsien dly found for B0: ( 1, 2, 30)
5222 22:13:02.121708 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5223 22:13:02.124783 Total UI for P1: 0, mck2ui 16
5224 22:13:02.128344 best dqsien dly found for B1: ( 1, 3, 4)
5225 22:13:02.131697 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5226 22:13:02.134761 best DQS1 dly(MCK, UI, PI) = (1, 3, 4)
5227 22:13:02.134845
5228 22:13:02.138016 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5229 22:13:02.144620 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 4)
5230 22:13:02.144700 [Gating] SW calibration Done
5231 22:13:02.144769 ==
5232 22:13:02.147778 Dram Type= 6, Freq= 0, CH_0, rank 0
5233 22:13:02.154323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5234 22:13:02.154425 ==
5235 22:13:02.154518 RX Vref Scan: 0
5236 22:13:02.154606
5237 22:13:02.157894 RX Vref 0 -> 0, step: 1
5238 22:13:02.157983
5239 22:13:02.161040 RX Delay -80 -> 252, step: 8
5240 22:13:02.164120 iDelay=208, Bit 0, Center 99 (8 ~ 191) 184
5241 22:13:02.167733 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5242 22:13:02.171458 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5243 22:13:02.177609 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5244 22:13:02.181046 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5245 22:13:02.184169 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5246 22:13:02.187800 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5247 22:13:02.190968 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5248 22:13:02.193860 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5249 22:13:02.200730 iDelay=208, Bit 9, Center 67 (-32 ~ 167) 200
5250 22:13:02.204393 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5251 22:13:02.207324 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5252 22:13:02.210570 iDelay=208, Bit 12, Center 87 (-16 ~ 191) 208
5253 22:13:02.217246 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5254 22:13:02.220333 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5255 22:13:02.223657 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5256 22:13:02.223751 ==
5257 22:13:02.226773 Dram Type= 6, Freq= 0, CH_0, rank 0
5258 22:13:02.230029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5259 22:13:02.230131 ==
5260 22:13:02.233737 DQS Delay:
5261 22:13:02.233872 DQS0 = 0, DQS1 = 0
5262 22:13:02.236738 DQM Delay:
5263 22:13:02.236871 DQM0 = 95, DQM1 = 82
5264 22:13:02.236965 DQ Delay:
5265 22:13:02.240094 DQ0 =99, DQ1 =95, DQ2 =91, DQ3 =91
5266 22:13:02.243291 DQ4 =99, DQ5 =79, DQ6 =103, DQ7 =107
5267 22:13:02.246375 DQ8 =75, DQ9 =67, DQ10 =83, DQ11 =75
5268 22:13:02.250222 DQ12 =87, DQ13 =91, DQ14 =91, DQ15 =91
5269 22:13:02.250313
5270 22:13:02.253275
5271 22:13:02.253360 ==
5272 22:13:02.256740 Dram Type= 6, Freq= 0, CH_0, rank 0
5273 22:13:02.259536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5274 22:13:02.259628 ==
5275 22:13:02.259698
5276 22:13:02.259760
5277 22:13:02.263201 TX Vref Scan disable
5278 22:13:02.263287 == TX Byte 0 ==
5279 22:13:02.270275 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5280 22:13:02.273076 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5281 22:13:02.273174 == TX Byte 1 ==
5282 22:13:02.280056 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5283 22:13:02.283080 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5284 22:13:02.283190 ==
5285 22:13:02.286026 Dram Type= 6, Freq= 0, CH_0, rank 0
5286 22:13:02.289509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5287 22:13:02.289621 ==
5288 22:13:02.289724
5289 22:13:02.289824
5290 22:13:02.292743 TX Vref Scan disable
5291 22:13:02.296486 == TX Byte 0 ==
5292 22:13:02.299316 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5293 22:13:02.302889 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5294 22:13:02.306129 == TX Byte 1 ==
5295 22:13:02.309701 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5296 22:13:02.312585 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5297 22:13:02.312670
5298 22:13:02.316023 [DATLAT]
5299 22:13:02.316133 Freq=933, CH0 RK0
5300 22:13:02.316218
5301 22:13:02.319114 DATLAT Default: 0xd
5302 22:13:02.319224 0, 0xFFFF, sum = 0
5303 22:13:02.322347 1, 0xFFFF, sum = 0
5304 22:13:02.322433 2, 0xFFFF, sum = 0
5305 22:13:02.325456 3, 0xFFFF, sum = 0
5306 22:13:02.325543 4, 0xFFFF, sum = 0
5307 22:13:02.328931 5, 0xFFFF, sum = 0
5308 22:13:02.329018 6, 0xFFFF, sum = 0
5309 22:13:02.332072 7, 0xFFFF, sum = 0
5310 22:13:02.335416 8, 0xFFFF, sum = 0
5311 22:13:02.335528 9, 0xFFFF, sum = 0
5312 22:13:02.338784 10, 0x0, sum = 1
5313 22:13:02.338872 11, 0x0, sum = 2
5314 22:13:02.338941 12, 0x0, sum = 3
5315 22:13:02.342380 13, 0x0, sum = 4
5316 22:13:02.342475 best_step = 11
5317 22:13:02.342571
5318 22:13:02.345163 ==
5319 22:13:02.348422 Dram Type= 6, Freq= 0, CH_0, rank 0
5320 22:13:02.352158 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5321 22:13:02.352241 ==
5322 22:13:02.352307 RX Vref Scan: 1
5323 22:13:02.352369
5324 22:13:02.355330 RX Vref 0 -> 0, step: 1
5325 22:13:02.355413
5326 22:13:02.358300 RX Delay -77 -> 252, step: 4
5327 22:13:02.358384
5328 22:13:02.362011 Set Vref, RX VrefLevel [Byte0]: 61
5329 22:13:02.364808 [Byte1]: 53
5330 22:13:02.364891
5331 22:13:02.368676 Final RX Vref Byte 0 = 61 to rank0
5332 22:13:02.371607 Final RX Vref Byte 1 = 53 to rank0
5333 22:13:02.375422 Final RX Vref Byte 0 = 61 to rank1
5334 22:13:02.378332 Final RX Vref Byte 1 = 53 to rank1==
5335 22:13:02.381417 Dram Type= 6, Freq= 0, CH_0, rank 0
5336 22:13:02.388292 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5337 22:13:02.388413 ==
5338 22:13:02.388508 DQS Delay:
5339 22:13:02.388598 DQS0 = 0, DQS1 = 0
5340 22:13:02.391420 DQM Delay:
5341 22:13:02.391537 DQM0 = 95, DQM1 = 83
5342 22:13:02.395036 DQ Delay:
5343 22:13:02.398295 DQ0 =94, DQ1 =96, DQ2 =92, DQ3 =92
5344 22:13:02.401399 DQ4 =96, DQ5 =84, DQ6 =102, DQ7 =106
5345 22:13:02.404383 DQ8 =76, DQ9 =72, DQ10 =82, DQ11 =78
5346 22:13:02.407810 DQ12 =86, DQ13 =88, DQ14 =96, DQ15 =90
5347 22:13:02.407890
5348 22:13:02.407961
5349 22:13:02.414578 [DQSOSCAuto] RK0, (LSB)MR18= 0x1413, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 415 ps
5350 22:13:02.417784 CH0 RK0: MR19=505, MR18=1413
5351 22:13:02.424414 CH0_RK0: MR19=0x505, MR18=0x1413, DQSOSC=415, MR23=63, INC=62, DEC=41
5352 22:13:02.424497
5353 22:13:02.427443 ----->DramcWriteLeveling(PI) begin...
5354 22:13:02.427526 ==
5355 22:13:02.431237 Dram Type= 6, Freq= 0, CH_0, rank 1
5356 22:13:02.434423 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5357 22:13:02.434504 ==
5358 22:13:02.437357 Write leveling (Byte 0): 31 => 31
5359 22:13:02.440553 Write leveling (Byte 1): 29 => 29
5360 22:13:02.444005 DramcWriteLeveling(PI) end<-----
5361 22:13:02.444081
5362 22:13:02.444159 ==
5363 22:13:02.447678 Dram Type= 6, Freq= 0, CH_0, rank 1
5364 22:13:02.450440 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5365 22:13:02.454116 ==
5366 22:13:02.454222 [Gating] SW mode calibration
5367 22:13:02.463436 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5368 22:13:02.466974 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5369 22:13:02.470159 0 14 0 | B1->B0 | 2828 3434 | 1 1 | (1 1) (1 1)
5370 22:13:02.476730 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5371 22:13:02.480277 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5372 22:13:02.483398 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5373 22:13:02.490106 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5374 22:13:02.493138 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5375 22:13:02.496804 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5376 22:13:02.503542 0 14 28 | B1->B0 | 3333 2f2f | 1 1 | (1 1) (1 1)
5377 22:13:02.506776 0 15 0 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (0 0)
5378 22:13:02.510385 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5379 22:13:02.516559 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5380 22:13:02.519852 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5381 22:13:02.522937 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5382 22:13:02.529877 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5383 22:13:02.533323 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5384 22:13:02.536562 0 15 28 | B1->B0 | 2727 3838 | 0 0 | (0 0) (0 0)
5385 22:13:02.543002 1 0 0 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
5386 22:13:02.546062 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5387 22:13:02.549215 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5388 22:13:02.556142 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5389 22:13:02.559565 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5390 22:13:02.562464 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5391 22:13:02.568860 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5392 22:13:02.572420 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5393 22:13:02.575922 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5394 22:13:02.582444 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5395 22:13:02.585758 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5396 22:13:02.589218 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5397 22:13:02.595576 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5398 22:13:02.598822 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5399 22:13:02.601930 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5400 22:13:02.608677 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5401 22:13:02.611707 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5402 22:13:02.615115 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5403 22:13:02.621777 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5404 22:13:02.625560 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5405 22:13:02.628562 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5406 22:13:02.635153 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5407 22:13:02.638697 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5408 22:13:02.641703 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5409 22:13:02.647932 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5410 22:13:02.651219 Total UI for P1: 0, mck2ui 16
5411 22:13:02.655084 best dqsien dly found for B0: ( 1, 2, 28)
5412 22:13:02.658362 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5413 22:13:02.661083 Total UI for P1: 0, mck2ui 16
5414 22:13:02.664556 best dqsien dly found for B1: ( 1, 3, 0)
5415 22:13:02.667628 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5416 22:13:02.671339 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5417 22:13:02.671423
5418 22:13:02.674582 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5419 22:13:02.681206 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5420 22:13:02.681283 [Gating] SW calibration Done
5421 22:13:02.681355 ==
5422 22:13:02.684301 Dram Type= 6, Freq= 0, CH_0, rank 1
5423 22:13:02.690968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5424 22:13:02.691049 ==
5425 22:13:02.691163 RX Vref Scan: 0
5426 22:13:02.691224
5427 22:13:02.694149 RX Vref 0 -> 0, step: 1
5428 22:13:02.694223
5429 22:13:02.697471 RX Delay -80 -> 252, step: 8
5430 22:13:02.700690 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5431 22:13:02.704257 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5432 22:13:02.707273 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5433 22:13:02.710948 iDelay=208, Bit 3, Center 87 (-16 ~ 191) 208
5434 22:13:02.717261 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5435 22:13:02.720837 iDelay=208, Bit 5, Center 75 (-24 ~ 175) 200
5436 22:13:02.723761 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5437 22:13:02.727397 iDelay=208, Bit 7, Center 103 (0 ~ 207) 208
5438 22:13:02.730719 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5439 22:13:02.736930 iDelay=208, Bit 9, Center 67 (-32 ~ 167) 200
5440 22:13:02.740617 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5441 22:13:02.744162 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5442 22:13:02.746904 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5443 22:13:02.753853 iDelay=208, Bit 13, Center 87 (-16 ~ 191) 208
5444 22:13:02.756698 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5445 22:13:02.759932 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5446 22:13:02.760014 ==
5447 22:13:02.763236 Dram Type= 6, Freq= 0, CH_0, rank 1
5448 22:13:02.766570 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5449 22:13:02.766653 ==
5450 22:13:02.770039 DQS Delay:
5451 22:13:02.770121 DQS0 = 0, DQS1 = 0
5452 22:13:02.773295 DQM Delay:
5453 22:13:02.773377 DQM0 = 91, DQM1 = 83
5454 22:13:02.773496 DQ Delay:
5455 22:13:02.776532 DQ0 =91, DQ1 =95, DQ2 =87, DQ3 =87
5456 22:13:02.779744 DQ4 =91, DQ5 =75, DQ6 =103, DQ7 =103
5457 22:13:02.782875 DQ8 =75, DQ9 =67, DQ10 =83, DQ11 =75
5458 22:13:02.786020 DQ12 =91, DQ13 =87, DQ14 =95, DQ15 =91
5459 22:13:02.786101
5460 22:13:02.789722
5461 22:13:02.789804 ==
5462 22:13:02.792774 Dram Type= 6, Freq= 0, CH_0, rank 1
5463 22:13:02.796396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5464 22:13:02.796479 ==
5465 22:13:02.796543
5466 22:13:02.796603
5467 22:13:02.799625 TX Vref Scan disable
5468 22:13:02.799707 == TX Byte 0 ==
5469 22:13:02.806530 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5470 22:13:02.809523 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5471 22:13:02.809605 == TX Byte 1 ==
5472 22:13:02.816113 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5473 22:13:02.819275 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5474 22:13:02.819358 ==
5475 22:13:02.822718 Dram Type= 6, Freq= 0, CH_0, rank 1
5476 22:13:02.825645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5477 22:13:02.825749 ==
5478 22:13:02.825844
5479 22:13:02.825909
5480 22:13:02.829171 TX Vref Scan disable
5481 22:13:02.832364 == TX Byte 0 ==
5482 22:13:02.835953 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5483 22:13:02.839136 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5484 22:13:02.842821 == TX Byte 1 ==
5485 22:13:02.845660 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5486 22:13:02.848806 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5487 22:13:02.848889
5488 22:13:02.852234 [DATLAT]
5489 22:13:02.852317 Freq=933, CH0 RK1
5490 22:13:02.852383
5491 22:13:02.855769 DATLAT Default: 0xb
5492 22:13:02.855878 0, 0xFFFF, sum = 0
5493 22:13:02.858687 1, 0xFFFF, sum = 0
5494 22:13:02.858770 2, 0xFFFF, sum = 0
5495 22:13:02.861920 3, 0xFFFF, sum = 0
5496 22:13:02.862004 4, 0xFFFF, sum = 0
5497 22:13:02.865387 5, 0xFFFF, sum = 0
5498 22:13:02.865471 6, 0xFFFF, sum = 0
5499 22:13:02.868725 7, 0xFFFF, sum = 0
5500 22:13:02.871881 8, 0xFFFF, sum = 0
5501 22:13:02.871965 9, 0xFFFF, sum = 0
5502 22:13:02.872032 10, 0x0, sum = 1
5503 22:13:02.875365 11, 0x0, sum = 2
5504 22:13:02.875452 12, 0x0, sum = 3
5505 22:13:02.878660 13, 0x0, sum = 4
5506 22:13:02.878744 best_step = 11
5507 22:13:02.878811
5508 22:13:02.878871 ==
5509 22:13:02.881994 Dram Type= 6, Freq= 0, CH_0, rank 1
5510 22:13:02.888222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5511 22:13:02.888305 ==
5512 22:13:02.888371 RX Vref Scan: 0
5513 22:13:02.888433
5514 22:13:02.891567 RX Vref 0 -> 0, step: 1
5515 22:13:02.891711
5516 22:13:02.895525 RX Delay -77 -> 252, step: 4
5517 22:13:02.898240 iDelay=199, Bit 0, Center 88 (-5 ~ 182) 188
5518 22:13:02.904811 iDelay=199, Bit 1, Center 94 (3 ~ 186) 184
5519 22:13:02.908422 iDelay=199, Bit 2, Center 88 (-5 ~ 182) 188
5520 22:13:02.911399 iDelay=199, Bit 3, Center 88 (-9 ~ 186) 196
5521 22:13:02.915047 iDelay=199, Bit 4, Center 90 (-5 ~ 186) 192
5522 22:13:02.918065 iDelay=199, Bit 5, Center 82 (-9 ~ 174) 184
5523 22:13:02.924807 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5524 22:13:02.928360 iDelay=199, Bit 7, Center 104 (11 ~ 198) 188
5525 22:13:02.931662 iDelay=199, Bit 8, Center 78 (-13 ~ 170) 184
5526 22:13:02.934701 iDelay=199, Bit 9, Center 68 (-21 ~ 158) 180
5527 22:13:02.937693 iDelay=199, Bit 10, Center 86 (-5 ~ 178) 184
5528 22:13:02.944462 iDelay=199, Bit 11, Center 78 (-13 ~ 170) 184
5529 22:13:02.948039 iDelay=199, Bit 12, Center 92 (-1 ~ 186) 188
5530 22:13:02.951145 iDelay=199, Bit 13, Center 90 (-5 ~ 186) 192
5531 22:13:02.955053 iDelay=199, Bit 14, Center 96 (7 ~ 186) 180
5532 22:13:02.957781 iDelay=199, Bit 15, Center 90 (-1 ~ 182) 184
5533 22:13:02.957878 ==
5534 22:13:02.961329 Dram Type= 6, Freq= 0, CH_0, rank 1
5535 22:13:02.967524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5536 22:13:02.967612 ==
5537 22:13:02.967680 DQS Delay:
5538 22:13:02.971063 DQS0 = 0, DQS1 = 0
5539 22:13:02.971145 DQM Delay:
5540 22:13:02.971211 DQM0 = 92, DQM1 = 84
5541 22:13:02.974215 DQ Delay:
5542 22:13:02.977579 DQ0 =88, DQ1 =94, DQ2 =88, DQ3 =88
5543 22:13:02.981054 DQ4 =90, DQ5 =82, DQ6 =104, DQ7 =104
5544 22:13:02.984359 DQ8 =78, DQ9 =68, DQ10 =86, DQ11 =78
5545 22:13:02.987762 DQ12 =92, DQ13 =90, DQ14 =96, DQ15 =90
5546 22:13:02.987845
5547 22:13:02.987910
5548 22:13:02.994112 [DQSOSCAuto] RK1, (LSB)MR18= 0x3213, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 406 ps
5549 22:13:02.997296 CH0 RK1: MR19=505, MR18=3213
5550 22:13:03.003920 CH0_RK1: MR19=0x505, MR18=0x3213, DQSOSC=406, MR23=63, INC=65, DEC=43
5551 22:13:03.007205 [RxdqsGatingPostProcess] freq 933
5552 22:13:03.013581 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5553 22:13:03.013664 best DQS0 dly(2T, 0.5T) = (0, 10)
5554 22:13:03.017336 best DQS1 dly(2T, 0.5T) = (0, 11)
5555 22:13:03.020245 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5556 22:13:03.023889 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5557 22:13:03.026764 best DQS0 dly(2T, 0.5T) = (0, 10)
5558 22:13:03.030611 best DQS1 dly(2T, 0.5T) = (0, 11)
5559 22:13:03.033363 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5560 22:13:03.036810 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5561 22:13:03.040540 Pre-setting of DQS Precalculation
5562 22:13:03.046532 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5563 22:13:03.046615 ==
5564 22:13:03.050214 Dram Type= 6, Freq= 0, CH_1, rank 0
5565 22:13:03.053120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5566 22:13:03.053202 ==
5567 22:13:03.059745 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5568 22:13:03.063195 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5569 22:13:03.067299 [CA 0] Center 36 (7~66) winsize 60
5570 22:13:03.070426 [CA 1] Center 37 (7~68) winsize 62
5571 22:13:03.073727 [CA 2] Center 34 (5~64) winsize 60
5572 22:13:03.077283 [CA 3] Center 34 (4~64) winsize 61
5573 22:13:03.080619 [CA 4] Center 34 (5~64) winsize 60
5574 22:13:03.083849 [CA 5] Center 33 (3~63) winsize 61
5575 22:13:03.083945
5576 22:13:03.087416 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5577 22:13:03.087498
5578 22:13:03.090776 [CATrainingPosCal] consider 1 rank data
5579 22:13:03.093879 u2DelayCellTimex100 = 270/100 ps
5580 22:13:03.097215 CA0 delay=36 (7~66),Diff = 3 PI (18 cell)
5581 22:13:03.103531 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5582 22:13:03.107276 CA2 delay=34 (5~64),Diff = 1 PI (6 cell)
5583 22:13:03.109976 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5584 22:13:03.113310 CA4 delay=34 (5~64),Diff = 1 PI (6 cell)
5585 22:13:03.116623 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5586 22:13:03.116719
5587 22:13:03.120271 CA PerBit enable=1, Macro0, CA PI delay=33
5588 22:13:03.120353
5589 22:13:03.123380 [CBTSetCACLKResult] CA Dly = 33
5590 22:13:03.127161 CS Dly: 6 (0~37)
5591 22:13:03.127242 ==
5592 22:13:03.129852 Dram Type= 6, Freq= 0, CH_1, rank 1
5593 22:13:03.133668 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5594 22:13:03.133750 ==
5595 22:13:03.139916 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5596 22:13:03.143008 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5597 22:13:03.147150 [CA 0] Center 37 (7~67) winsize 61
5598 22:13:03.150756 [CA 1] Center 37 (7~68) winsize 62
5599 22:13:03.153787 [CA 2] Center 35 (5~65) winsize 61
5600 22:13:03.156888 [CA 3] Center 33 (3~64) winsize 62
5601 22:13:03.160240 [CA 4] Center 34 (4~64) winsize 61
5602 22:13:03.163950 [CA 5] Center 33 (3~64) winsize 62
5603 22:13:03.164032
5604 22:13:03.166943 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5605 22:13:03.167026
5606 22:13:03.170521 [CATrainingPosCal] consider 2 rank data
5607 22:13:03.173637 u2DelayCellTimex100 = 270/100 ps
5608 22:13:03.177314 CA0 delay=36 (7~66),Diff = 3 PI (18 cell)
5609 22:13:03.183290 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5610 22:13:03.186729 CA2 delay=34 (5~64),Diff = 1 PI (6 cell)
5611 22:13:03.190478 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5612 22:13:03.193465 CA4 delay=34 (5~64),Diff = 1 PI (6 cell)
5613 22:13:03.196803 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5614 22:13:03.196910
5615 22:13:03.200392 CA PerBit enable=1, Macro0, CA PI delay=33
5616 22:13:03.200485
5617 22:13:03.203181 [CBTSetCACLKResult] CA Dly = 33
5618 22:13:03.206448 CS Dly: 7 (0~39)
5619 22:13:03.206557
5620 22:13:03.210234 ----->DramcWriteLeveling(PI) begin...
5621 22:13:03.210317 ==
5622 22:13:03.213076 Dram Type= 6, Freq= 0, CH_1, rank 0
5623 22:13:03.216586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5624 22:13:03.216671 ==
5625 22:13:03.219667 Write leveling (Byte 0): 26 => 26
5626 22:13:03.223146 Write leveling (Byte 1): 30 => 30
5627 22:13:03.226260 DramcWriteLeveling(PI) end<-----
5628 22:13:03.226380
5629 22:13:03.226464 ==
5630 22:13:03.229735 Dram Type= 6, Freq= 0, CH_1, rank 0
5631 22:13:03.232786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5632 22:13:03.232871 ==
5633 22:13:03.236392 [Gating] SW mode calibration
5634 22:13:03.243189 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5635 22:13:03.249817 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5636 22:13:03.252936 0 14 0 | B1->B0 | 3434 3130 | 1 1 | (0 0) (0 0)
5637 22:13:03.255959 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5638 22:13:03.262651 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5639 22:13:03.266371 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5640 22:13:03.269319 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5641 22:13:03.275772 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5642 22:13:03.278994 0 14 24 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5643 22:13:03.282683 0 14 28 | B1->B0 | 3030 3030 | 0 0 | (0 1) (0 1)
5644 22:13:03.288736 0 15 0 | B1->B0 | 2424 2424 | 0 0 | (0 0) (0 0)
5645 22:13:03.292293 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5646 22:13:03.295701 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5647 22:13:03.302092 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5648 22:13:03.305368 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5649 22:13:03.309028 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5650 22:13:03.315227 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5651 22:13:03.318926 0 15 28 | B1->B0 | 3232 3131 | 0 0 | (0 0) (0 0)
5652 22:13:03.321916 1 0 0 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
5653 22:13:03.328467 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5654 22:13:03.331676 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5655 22:13:03.335168 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5656 22:13:03.341604 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5657 22:13:03.345213 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5658 22:13:03.351601 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5659 22:13:03.354706 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5660 22:13:03.358306 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5661 22:13:03.361406 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5662 22:13:03.368064 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5663 22:13:03.371740 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5664 22:13:03.374789 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5665 22:13:03.381235 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5666 22:13:03.384605 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5667 22:13:03.387726 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5668 22:13:03.394588 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5669 22:13:03.397967 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5670 22:13:03.401293 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5671 22:13:03.407546 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5672 22:13:03.410995 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5673 22:13:03.414262 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5674 22:13:03.421363 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5675 22:13:03.424090 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5676 22:13:03.427629 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5677 22:13:03.430661 Total UI for P1: 0, mck2ui 16
5678 22:13:03.434063 best dqsien dly found for B0: ( 1, 2, 28)
5679 22:13:03.437587 Total UI for P1: 0, mck2ui 16
5680 22:13:03.441208 best dqsien dly found for B1: ( 1, 2, 26)
5681 22:13:03.444202 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5682 22:13:03.450793 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5683 22:13:03.450870
5684 22:13:03.453908 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5685 22:13:03.456866 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5686 22:13:03.460466 [Gating] SW calibration Done
5687 22:13:03.460566 ==
5688 22:13:03.463548 Dram Type= 6, Freq= 0, CH_1, rank 0
5689 22:13:03.467050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5690 22:13:03.467150 ==
5691 22:13:03.470184 RX Vref Scan: 0
5692 22:13:03.470286
5693 22:13:03.470352 RX Vref 0 -> 0, step: 1
5694 22:13:03.470412
5695 22:13:03.473653 RX Delay -80 -> 252, step: 8
5696 22:13:03.476700 iDelay=208, Bit 0, Center 103 (0 ~ 207) 208
5697 22:13:03.483181 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5698 22:13:03.486941 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5699 22:13:03.490181 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5700 22:13:03.493183 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5701 22:13:03.496671 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5702 22:13:03.500249 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5703 22:13:03.506394 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5704 22:13:03.509609 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5705 22:13:03.513134 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5706 22:13:03.516567 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5707 22:13:03.519537 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5708 22:13:03.526231 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5709 22:13:03.529456 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5710 22:13:03.532869 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5711 22:13:03.536592 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5712 22:13:03.536675 ==
5713 22:13:03.539589 Dram Type= 6, Freq= 0, CH_1, rank 0
5714 22:13:03.546222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5715 22:13:03.546334 ==
5716 22:13:03.546464 DQS Delay:
5717 22:13:03.546557 DQS0 = 0, DQS1 = 0
5718 22:13:03.549254 DQM Delay:
5719 22:13:03.549409 DQM0 = 95, DQM1 = 86
5720 22:13:03.552963 DQ Delay:
5721 22:13:03.555856 DQ0 =103, DQ1 =91, DQ2 =83, DQ3 =91
5722 22:13:03.559477 DQ4 =91, DQ5 =107, DQ6 =103, DQ7 =91
5723 22:13:03.562404 DQ8 =75, DQ9 =79, DQ10 =87, DQ11 =83
5724 22:13:03.565690 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5725 22:13:03.565799
5726 22:13:03.565897
5727 22:13:03.565969 ==
5728 22:13:03.569294 Dram Type= 6, Freq= 0, CH_1, rank 0
5729 22:13:03.572318 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5730 22:13:03.572396 ==
5731 22:13:03.572460
5732 22:13:03.572519
5733 22:13:03.576070 TX Vref Scan disable
5734 22:13:03.579209 == TX Byte 0 ==
5735 22:13:03.582118 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5736 22:13:03.585727 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5737 22:13:03.588788 == TX Byte 1 ==
5738 22:13:03.592377 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5739 22:13:03.595407 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5740 22:13:03.595486 ==
5741 22:13:03.599150 Dram Type= 6, Freq= 0, CH_1, rank 0
5742 22:13:03.601907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5743 22:13:03.605579 ==
5744 22:13:03.605696
5745 22:13:03.605802
5746 22:13:03.605890 TX Vref Scan disable
5747 22:13:03.608946 == TX Byte 0 ==
5748 22:13:03.612192 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5749 22:13:03.618970 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5750 22:13:03.619080 == TX Byte 1 ==
5751 22:13:03.622389 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5752 22:13:03.629116 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5753 22:13:03.629198
5754 22:13:03.629263 [DATLAT]
5755 22:13:03.629322 Freq=933, CH1 RK0
5756 22:13:03.629381
5757 22:13:03.632332 DATLAT Default: 0xd
5758 22:13:03.632413 0, 0xFFFF, sum = 0
5759 22:13:03.635212 1, 0xFFFF, sum = 0
5760 22:13:03.638858 2, 0xFFFF, sum = 0
5761 22:13:03.638941 3, 0xFFFF, sum = 0
5762 22:13:03.642049 4, 0xFFFF, sum = 0
5763 22:13:03.642133 5, 0xFFFF, sum = 0
5764 22:13:03.645196 6, 0xFFFF, sum = 0
5765 22:13:03.645280 7, 0xFFFF, sum = 0
5766 22:13:03.648505 8, 0xFFFF, sum = 0
5767 22:13:03.648594 9, 0xFFFF, sum = 0
5768 22:13:03.651916 10, 0x0, sum = 1
5769 22:13:03.651998 11, 0x0, sum = 2
5770 22:13:03.655510 12, 0x0, sum = 3
5771 22:13:03.655649 13, 0x0, sum = 4
5772 22:13:03.658396 best_step = 11
5773 22:13:03.658477
5774 22:13:03.658542 ==
5775 22:13:03.661895 Dram Type= 6, Freq= 0, CH_1, rank 0
5776 22:13:03.664950 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5777 22:13:03.665033 ==
5778 22:13:03.665098 RX Vref Scan: 1
5779 22:13:03.668297
5780 22:13:03.668378 RX Vref 0 -> 0, step: 1
5781 22:13:03.668444
5782 22:13:03.671858 RX Delay -69 -> 252, step: 4
5783 22:13:03.671965
5784 22:13:03.674906 Set Vref, RX VrefLevel [Byte0]: 52
5785 22:13:03.678562 [Byte1]: 53
5786 22:13:03.681698
5787 22:13:03.681783 Final RX Vref Byte 0 = 52 to rank0
5788 22:13:03.684761 Final RX Vref Byte 1 = 53 to rank0
5789 22:13:03.688184 Final RX Vref Byte 0 = 52 to rank1
5790 22:13:03.691826 Final RX Vref Byte 1 = 53 to rank1==
5791 22:13:03.694802 Dram Type= 6, Freq= 0, CH_1, rank 0
5792 22:13:03.701401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5793 22:13:03.701486 ==
5794 22:13:03.701552 DQS Delay:
5795 22:13:03.704737 DQS0 = 0, DQS1 = 0
5796 22:13:03.704811 DQM Delay:
5797 22:13:03.704874 DQM0 = 95, DQM1 = 88
5798 22:13:03.707934 DQ Delay:
5799 22:13:03.711242 DQ0 =100, DQ1 =90, DQ2 =84, DQ3 =92
5800 22:13:03.714688 DQ4 =92, DQ5 =106, DQ6 =106, DQ7 =92
5801 22:13:03.717991 DQ8 =76, DQ9 =78, DQ10 =88, DQ11 =82
5802 22:13:03.721304 DQ12 =96, DQ13 =94, DQ14 =96, DQ15 =94
5803 22:13:03.721411
5804 22:13:03.721503
5805 22:13:03.727811 [DQSOSCAuto] RK0, (LSB)MR18= 0x40c, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 420 ps
5806 22:13:03.731327 CH1 RK0: MR19=505, MR18=40C
5807 22:13:03.737783 CH1_RK0: MR19=0x505, MR18=0x40C, DQSOSC=418, MR23=63, INC=62, DEC=41
5808 22:13:03.737887
5809 22:13:03.740796 ----->DramcWriteLeveling(PI) begin...
5810 22:13:03.740898 ==
5811 22:13:03.744461 Dram Type= 6, Freq= 0, CH_1, rank 1
5812 22:13:03.747397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5813 22:13:03.747498 ==
5814 22:13:03.750824 Write leveling (Byte 0): 26 => 26
5815 22:13:03.754436 Write leveling (Byte 1): 26 => 26
5816 22:13:03.757521 DramcWriteLeveling(PI) end<-----
5817 22:13:03.757659
5818 22:13:03.757750 ==
5819 22:13:03.760764 Dram Type= 6, Freq= 0, CH_1, rank 1
5820 22:13:03.764055 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5821 22:13:03.767197 ==
5822 22:13:03.767298 [Gating] SW mode calibration
5823 22:13:03.777196 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5824 22:13:03.780611 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5825 22:13:03.783628 0 14 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
5826 22:13:03.790712 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5827 22:13:03.793620 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5828 22:13:03.797355 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5829 22:13:03.803945 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5830 22:13:03.806920 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5831 22:13:03.810686 0 14 24 | B1->B0 | 3333 3131 | 0 0 | (0 0) (0 0)
5832 22:13:03.816770 0 14 28 | B1->B0 | 2c2c 2323 | 0 0 | (1 1) (0 0)
5833 22:13:03.820188 0 15 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5834 22:13:03.823480 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5835 22:13:03.830120 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5836 22:13:03.833483 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5837 22:13:03.836444 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5838 22:13:03.843529 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5839 22:13:03.846302 0 15 24 | B1->B0 | 2929 3535 | 0 0 | (0 0) (0 0)
5840 22:13:03.849959 0 15 28 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
5841 22:13:03.856314 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5842 22:13:03.859853 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5843 22:13:03.863221 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5844 22:13:03.869415 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5845 22:13:03.872877 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5846 22:13:03.876539 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5847 22:13:03.882627 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5848 22:13:03.886207 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5849 22:13:03.889604 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5850 22:13:03.896339 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5851 22:13:03.899335 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5852 22:13:03.902810 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5853 22:13:03.909394 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5854 22:13:03.912554 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5855 22:13:03.916232 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5856 22:13:03.922721 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5857 22:13:03.925679 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5858 22:13:03.928911 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5859 22:13:03.935565 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5860 22:13:03.938929 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5861 22:13:03.942397 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5862 22:13:03.948562 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5863 22:13:03.951976 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5864 22:13:03.955047 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5865 22:13:03.958473 Total UI for P1: 0, mck2ui 16
5866 22:13:03.961926 best dqsien dly found for B0: ( 1, 2, 26)
5867 22:13:03.965105 Total UI for P1: 0, mck2ui 16
5868 22:13:03.968713 best dqsien dly found for B1: ( 1, 2, 26)
5869 22:13:03.971967 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5870 22:13:03.974851 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5871 22:13:03.974933
5872 22:13:03.981482 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5873 22:13:03.984959 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5874 22:13:03.988725 [Gating] SW calibration Done
5875 22:13:03.988807 ==
5876 22:13:03.991697 Dram Type= 6, Freq= 0, CH_1, rank 1
5877 22:13:03.995122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5878 22:13:03.995205 ==
5879 22:13:03.995272 RX Vref Scan: 0
5880 22:13:03.995334
5881 22:13:03.998127 RX Vref 0 -> 0, step: 1
5882 22:13:03.998210
5883 22:13:04.001687 RX Delay -80 -> 252, step: 8
5884 22:13:04.004754 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5885 22:13:04.008409 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5886 22:13:04.014743 iDelay=208, Bit 2, Center 79 (-16 ~ 175) 192
5887 22:13:04.018073 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5888 22:13:04.021092 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5889 22:13:04.024684 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5890 22:13:04.027615 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5891 22:13:04.031077 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5892 22:13:04.037623 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5893 22:13:04.040745 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5894 22:13:04.044270 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5895 22:13:04.047182 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5896 22:13:04.053902 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5897 22:13:04.057205 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5898 22:13:04.060565 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5899 22:13:04.064310 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5900 22:13:04.064393 ==
5901 22:13:04.067133 Dram Type= 6, Freq= 0, CH_1, rank 1
5902 22:13:04.070921 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5903 22:13:04.071004 ==
5904 22:13:04.073725 DQS Delay:
5905 22:13:04.073807 DQS0 = 0, DQS1 = 0
5906 22:13:04.077299 DQM Delay:
5907 22:13:04.077381 DQM0 = 94, DQM1 = 89
5908 22:13:04.077447 DQ Delay:
5909 22:13:04.080335 DQ0 =99, DQ1 =91, DQ2 =79, DQ3 =91
5910 22:13:04.083775 DQ4 =91, DQ5 =107, DQ6 =103, DQ7 =91
5911 22:13:04.087088 DQ8 =79, DQ9 =79, DQ10 =95, DQ11 =83
5912 22:13:04.090355 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5913 22:13:04.090466
5914 22:13:04.093379
5915 22:13:04.093493 ==
5916 22:13:04.096795 Dram Type= 6, Freq= 0, CH_1, rank 1
5917 22:13:04.100477 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5918 22:13:04.100560 ==
5919 22:13:04.100628
5920 22:13:04.100689
5921 22:13:04.103417 TX Vref Scan disable
5922 22:13:04.103499 == TX Byte 0 ==
5923 22:13:04.110006 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5924 22:13:04.113169 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5925 22:13:04.113252 == TX Byte 1 ==
5926 22:13:04.119641 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5927 22:13:04.123218 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5928 22:13:04.123302 ==
5929 22:13:04.126267 Dram Type= 6, Freq= 0, CH_1, rank 1
5930 22:13:04.130000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5931 22:13:04.130084 ==
5932 22:13:04.130149
5933 22:13:04.130210
5934 22:13:04.133420 TX Vref Scan disable
5935 22:13:04.136582 == TX Byte 0 ==
5936 22:13:04.139790 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5937 22:13:04.143182 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5938 22:13:04.146225 == TX Byte 1 ==
5939 22:13:04.149731 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5940 22:13:04.153163 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5941 22:13:04.153246
5942 22:13:04.156106 [DATLAT]
5943 22:13:04.156189 Freq=933, CH1 RK1
5944 22:13:04.156255
5945 22:13:04.159416 DATLAT Default: 0xb
5946 22:13:04.159498 0, 0xFFFF, sum = 0
5947 22:13:04.162657 1, 0xFFFF, sum = 0
5948 22:13:04.162741 2, 0xFFFF, sum = 0
5949 22:13:04.166208 3, 0xFFFF, sum = 0
5950 22:13:04.166321 4, 0xFFFF, sum = 0
5951 22:13:04.169647 5, 0xFFFF, sum = 0
5952 22:13:04.172741 6, 0xFFFF, sum = 0
5953 22:13:04.172839 7, 0xFFFF, sum = 0
5954 22:13:04.175969 8, 0xFFFF, sum = 0
5955 22:13:04.176053 9, 0xFFFF, sum = 0
5956 22:13:04.179241 10, 0x0, sum = 1
5957 22:13:04.179325 11, 0x0, sum = 2
5958 22:13:04.179393 12, 0x0, sum = 3
5959 22:13:04.182402 13, 0x0, sum = 4
5960 22:13:04.182492 best_step = 11
5961 22:13:04.182582
5962 22:13:04.186021 ==
5963 22:13:04.186104 Dram Type= 6, Freq= 0, CH_1, rank 1
5964 22:13:04.192539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5965 22:13:04.192651 ==
5966 22:13:04.192718 RX Vref Scan: 0
5967 22:13:04.192780
5968 22:13:04.195362 RX Vref 0 -> 0, step: 1
5969 22:13:04.195479
5970 22:13:04.199006 RX Delay -61 -> 252, step: 4
5971 22:13:04.202711 iDelay=203, Bit 0, Center 98 (3 ~ 194) 192
5972 22:13:04.208590 iDelay=203, Bit 1, Center 90 (-5 ~ 186) 192
5973 22:13:04.212316 iDelay=203, Bit 2, Center 84 (-9 ~ 178) 188
5974 22:13:04.215228 iDelay=203, Bit 3, Center 88 (-9 ~ 186) 196
5975 22:13:04.218931 iDelay=203, Bit 4, Center 90 (-5 ~ 186) 192
5976 22:13:04.222221 iDelay=203, Bit 5, Center 102 (7 ~ 198) 192
5977 22:13:04.228782 iDelay=203, Bit 6, Center 104 (7 ~ 202) 196
5978 22:13:04.232019 iDelay=203, Bit 7, Center 90 (-5 ~ 186) 192
5979 22:13:04.235141 iDelay=203, Bit 8, Center 76 (-17 ~ 170) 188
5980 22:13:04.238732 iDelay=203, Bit 9, Center 80 (-13 ~ 174) 188
5981 22:13:04.242130 iDelay=203, Bit 10, Center 92 (-1 ~ 186) 188
5982 22:13:04.248336 iDelay=203, Bit 11, Center 84 (-9 ~ 178) 188
5983 22:13:04.251604 iDelay=203, Bit 12, Center 98 (7 ~ 190) 184
5984 22:13:04.255047 iDelay=203, Bit 13, Center 94 (-1 ~ 190) 192
5985 22:13:04.258575 iDelay=203, Bit 14, Center 94 (-1 ~ 190) 192
5986 22:13:04.262058 iDelay=203, Bit 15, Center 94 (-1 ~ 190) 192
5987 22:13:04.262141 ==
5988 22:13:04.264810 Dram Type= 6, Freq= 0, CH_1, rank 1
5989 22:13:04.271492 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5990 22:13:04.271626 ==
5991 22:13:04.271740 DQS Delay:
5992 22:13:04.274618 DQS0 = 0, DQS1 = 0
5993 22:13:04.274726 DQM Delay:
5994 22:13:04.274827 DQM0 = 93, DQM1 = 89
5995 22:13:04.278279 DQ Delay:
5996 22:13:04.281231 DQ0 =98, DQ1 =90, DQ2 =84, DQ3 =88
5997 22:13:04.284906 DQ4 =90, DQ5 =102, DQ6 =104, DQ7 =90
5998 22:13:04.288306 DQ8 =76, DQ9 =80, DQ10 =92, DQ11 =84
5999 22:13:04.291265 DQ12 =98, DQ13 =94, DQ14 =94, DQ15 =94
6000 22:13:04.291366
6001 22:13:04.291485
6002 22:13:04.298312 [DQSOSCAuto] RK1, (LSB)MR18= 0xe22, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 417 ps
6003 22:13:04.301175 CH1 RK1: MR19=505, MR18=E22
6004 22:13:04.307538 CH1_RK1: MR19=0x505, MR18=0xE22, DQSOSC=411, MR23=63, INC=64, DEC=42
6005 22:13:04.310968 [RxdqsGatingPostProcess] freq 933
6006 22:13:04.314421 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6007 22:13:04.317558 best DQS0 dly(2T, 0.5T) = (0, 10)
6008 22:13:04.321413 best DQS1 dly(2T, 0.5T) = (0, 10)
6009 22:13:04.324544 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6010 22:13:04.327561 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6011 22:13:04.331040 best DQS0 dly(2T, 0.5T) = (0, 10)
6012 22:13:04.334614 best DQS1 dly(2T, 0.5T) = (0, 10)
6013 22:13:04.337490 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6014 22:13:04.340735 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6015 22:13:04.343808 Pre-setting of DQS Precalculation
6016 22:13:04.347110 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6017 22:13:04.357674 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6018 22:13:04.363707 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6019 22:13:04.363803
6020 22:13:04.363944
6021 22:13:04.367569 [Calibration Summary] 1866 Mbps
6022 22:13:04.367671 CH 0, Rank 0
6023 22:13:04.370401 SW Impedance : PASS
6024 22:13:04.370501 DUTY Scan : NO K
6025 22:13:04.374048 ZQ Calibration : PASS
6026 22:13:04.376818 Jitter Meter : NO K
6027 22:13:04.376918 CBT Training : PASS
6028 22:13:04.380337 Write leveling : PASS
6029 22:13:04.383965 RX DQS gating : PASS
6030 22:13:04.384074 RX DQ/DQS(RDDQC) : PASS
6031 22:13:04.386915 TX DQ/DQS : PASS
6032 22:13:04.390349 RX DATLAT : PASS
6033 22:13:04.390461 RX DQ/DQS(Engine): PASS
6034 22:13:04.393941 TX OE : NO K
6035 22:13:04.394045 All Pass.
6036 22:13:04.394112
6037 22:13:04.396910 CH 0, Rank 1
6038 22:13:04.396992 SW Impedance : PASS
6039 22:13:04.399956 DUTY Scan : NO K
6040 22:13:04.403814 ZQ Calibration : PASS
6041 22:13:04.403922 Jitter Meter : NO K
6042 22:13:04.406638 CBT Training : PASS
6043 22:13:04.410387 Write leveling : PASS
6044 22:13:04.410469 RX DQS gating : PASS
6045 22:13:04.413183 RX DQ/DQS(RDDQC) : PASS
6046 22:13:04.416725 TX DQ/DQS : PASS
6047 22:13:04.416808 RX DATLAT : PASS
6048 22:13:04.419963 RX DQ/DQS(Engine): PASS
6049 22:13:04.422834 TX OE : NO K
6050 22:13:04.422915 All Pass.
6051 22:13:04.422981
6052 22:13:04.423041 CH 1, Rank 0
6053 22:13:04.426430 SW Impedance : PASS
6054 22:13:04.429471 DUTY Scan : NO K
6055 22:13:04.429553 ZQ Calibration : PASS
6056 22:13:04.432713 Jitter Meter : NO K
6057 22:13:04.436186 CBT Training : PASS
6058 22:13:04.436268 Write leveling : PASS
6059 22:13:04.439743 RX DQS gating : PASS
6060 22:13:04.442834 RX DQ/DQS(RDDQC) : PASS
6061 22:13:04.442916 TX DQ/DQS : PASS
6062 22:13:04.446542 RX DATLAT : PASS
6063 22:13:04.446624 RX DQ/DQS(Engine): PASS
6064 22:13:04.449400 TX OE : NO K
6065 22:13:04.449482 All Pass.
6066 22:13:04.449547
6067 22:13:04.452812 CH 1, Rank 1
6068 22:13:04.452894 SW Impedance : PASS
6069 22:13:04.456335 DUTY Scan : NO K
6070 22:13:04.459693 ZQ Calibration : PASS
6071 22:13:04.459775 Jitter Meter : NO K
6072 22:13:04.462747 CBT Training : PASS
6073 22:13:04.466366 Write leveling : PASS
6074 22:13:04.466447 RX DQS gating : PASS
6075 22:13:04.469592 RX DQ/DQS(RDDQC) : PASS
6076 22:13:04.472803 TX DQ/DQS : PASS
6077 22:13:04.472891 RX DATLAT : PASS
6078 22:13:04.475707 RX DQ/DQS(Engine): PASS
6079 22:13:04.479587 TX OE : NO K
6080 22:13:04.479713 All Pass.
6081 22:13:04.479813
6082 22:13:04.482964 DramC Write-DBI off
6083 22:13:04.483046 PER_BANK_REFRESH: Hybrid Mode
6084 22:13:04.485615 TX_TRACKING: ON
6085 22:13:04.492291 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6086 22:13:04.498983 [FAST_K] Save calibration result to emmc
6087 22:13:04.502045 dramc_set_vcore_voltage set vcore to 650000
6088 22:13:04.502153 Read voltage for 400, 6
6089 22:13:04.505905 Vio18 = 0
6090 22:13:04.506016 Vcore = 650000
6091 22:13:04.506115 Vdram = 0
6092 22:13:04.508807 Vddq = 0
6093 22:13:04.508917 Vmddr = 0
6094 22:13:04.512331 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6095 22:13:04.519049 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6096 22:13:04.522488 MEM_TYPE=3, freq_sel=20
6097 22:13:04.525904 sv_algorithm_assistance_LP4_800
6098 22:13:04.528540 ============ PULL DRAM RESETB DOWN ============
6099 22:13:04.532217 ========== PULL DRAM RESETB DOWN end =========
6100 22:13:04.538379 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6101 22:13:04.542168 ===================================
6102 22:13:04.542278 LPDDR4 DRAM CONFIGURATION
6103 22:13:04.545279 ===================================
6104 22:13:04.548872 EX_ROW_EN[0] = 0x0
6105 22:13:04.548954 EX_ROW_EN[1] = 0x0
6106 22:13:04.551914 LP4Y_EN = 0x0
6107 22:13:04.554778 WORK_FSP = 0x0
6108 22:13:04.554860 WL = 0x2
6109 22:13:04.558510 RL = 0x2
6110 22:13:04.558627 BL = 0x2
6111 22:13:04.561911 RPST = 0x0
6112 22:13:04.561999 RD_PRE = 0x0
6113 22:13:04.564838 WR_PRE = 0x1
6114 22:13:04.564947 WR_PST = 0x0
6115 22:13:04.568310 DBI_WR = 0x0
6116 22:13:04.568423 DBI_RD = 0x0
6117 22:13:04.571473 OTF = 0x1
6118 22:13:04.574878 ===================================
6119 22:13:04.577783 ===================================
6120 22:13:04.577865 ANA top config
6121 22:13:04.581475 ===================================
6122 22:13:04.584692 DLL_ASYNC_EN = 0
6123 22:13:04.588264 ALL_SLAVE_EN = 1
6124 22:13:04.591540 NEW_RANK_MODE = 1
6125 22:13:04.591673 DLL_IDLE_MODE = 1
6126 22:13:04.594893 LP45_APHY_COMB_EN = 1
6127 22:13:04.597656 TX_ODT_DIS = 1
6128 22:13:04.601374 NEW_8X_MODE = 1
6129 22:13:04.604547 ===================================
6130 22:13:04.607667 ===================================
6131 22:13:04.611425 data_rate = 800
6132 22:13:04.611524 CKR = 1
6133 22:13:04.614435 DQ_P2S_RATIO = 4
6134 22:13:04.617867 ===================================
6135 22:13:04.620974 CA_P2S_RATIO = 4
6136 22:13:04.624629 DQ_CA_OPEN = 0
6137 22:13:04.627774 DQ_SEMI_OPEN = 1
6138 22:13:04.631209 CA_SEMI_OPEN = 1
6139 22:13:04.631312 CA_FULL_RATE = 0
6140 22:13:04.634060 DQ_CKDIV4_EN = 0
6141 22:13:04.637353 CA_CKDIV4_EN = 1
6142 22:13:04.641060 CA_PREDIV_EN = 0
6143 22:13:04.644082 PH8_DLY = 0
6144 22:13:04.647718 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6145 22:13:04.647818 DQ_AAMCK_DIV = 0
6146 22:13:04.650797 CA_AAMCK_DIV = 0
6147 22:13:04.653866 CA_ADMCK_DIV = 4
6148 22:13:04.657753 DQ_TRACK_CA_EN = 0
6149 22:13:04.660777 CA_PICK = 800
6150 22:13:04.664214 CA_MCKIO = 400
6151 22:13:04.666987 MCKIO_SEMI = 400
6152 22:13:04.667087 PLL_FREQ = 3016
6153 22:13:04.670573 DQ_UI_PI_RATIO = 32
6154 22:13:04.673895 CA_UI_PI_RATIO = 32
6155 22:13:04.676900 ===================================
6156 22:13:04.680156 ===================================
6157 22:13:04.683615 memory_type:LPDDR4
6158 22:13:04.687149 GP_NUM : 10
6159 22:13:04.687228 SRAM_EN : 1
6160 22:13:04.690679 MD32_EN : 0
6161 22:13:04.693483 ===================================
6162 22:13:04.696753 [ANA_INIT] >>>>>>>>>>>>>>
6163 22:13:04.696830 <<<<<< [CONFIGURE PHASE]: ANA_TX
6164 22:13:04.700174 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6165 22:13:04.703475 ===================================
6166 22:13:04.707081 data_rate = 800,PCW = 0X7400
6167 22:13:04.710204 ===================================
6168 22:13:04.713125 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6169 22:13:04.720036 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6170 22:13:04.730044 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6171 22:13:04.736555 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6172 22:13:04.739731 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6173 22:13:04.743044 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6174 22:13:04.746419 [ANA_INIT] flow start
6175 22:13:04.746508 [ANA_INIT] PLL >>>>>>>>
6176 22:13:04.749835 [ANA_INIT] PLL <<<<<<<<
6177 22:13:04.752899 [ANA_INIT] MIDPI >>>>>>>>
6178 22:13:04.752980 [ANA_INIT] MIDPI <<<<<<<<
6179 22:13:04.756145 [ANA_INIT] DLL >>>>>>>>
6180 22:13:04.759696 [ANA_INIT] flow end
6181 22:13:04.762783 ============ LP4 DIFF to SE enter ============
6182 22:13:04.766217 ============ LP4 DIFF to SE exit ============
6183 22:13:04.769746 [ANA_INIT] <<<<<<<<<<<<<
6184 22:13:04.772733 [Flow] Enable top DCM control >>>>>
6185 22:13:04.776220 [Flow] Enable top DCM control <<<<<
6186 22:13:04.779331 Enable DLL master slave shuffle
6187 22:13:04.782731 ==============================================================
6188 22:13:04.786114 Gating Mode config
6189 22:13:04.792326 ==============================================================
6190 22:13:04.792434 Config description:
6191 22:13:04.802547 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6192 22:13:04.809560 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6193 22:13:04.815378 SELPH_MODE 0: By rank 1: By Phase
6194 22:13:04.819042 ==============================================================
6195 22:13:04.822282 GAT_TRACK_EN = 0
6196 22:13:04.825276 RX_GATING_MODE = 2
6197 22:13:04.828988 RX_GATING_TRACK_MODE = 2
6198 22:13:04.831955 SELPH_MODE = 1
6199 22:13:04.835855 PICG_EARLY_EN = 1
6200 22:13:04.838683 VALID_LAT_VALUE = 1
6201 22:13:04.842138 ==============================================================
6202 22:13:04.845366 Enter into Gating configuration >>>>
6203 22:13:04.848640 Exit from Gating configuration <<<<
6204 22:13:04.851964 Enter into DVFS_PRE_config >>>>>
6205 22:13:04.864933 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6206 22:13:04.868519 Exit from DVFS_PRE_config <<<<<
6207 22:13:04.871467 Enter into PICG configuration >>>>
6208 22:13:04.875019 Exit from PICG configuration <<<<
6209 22:13:04.875100 [RX_INPUT] configuration >>>>>
6210 22:13:04.878078 [RX_INPUT] configuration <<<<<
6211 22:13:04.884604 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6212 22:13:04.887962 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6213 22:13:04.894604 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6214 22:13:04.901005 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6215 22:13:04.908001 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6216 22:13:04.914235 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6217 22:13:04.917711 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6218 22:13:04.921395 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6219 22:13:04.927863 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6220 22:13:04.930759 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6221 22:13:04.934460 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6222 22:13:04.941214 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6223 22:13:04.944066 ===================================
6224 22:13:04.944149 LPDDR4 DRAM CONFIGURATION
6225 22:13:04.947764 ===================================
6226 22:13:04.950720 EX_ROW_EN[0] = 0x0
6227 22:13:04.950802 EX_ROW_EN[1] = 0x0
6228 22:13:04.954232 LP4Y_EN = 0x0
6229 22:13:04.954314 WORK_FSP = 0x0
6230 22:13:04.957068 WL = 0x2
6231 22:13:04.960392 RL = 0x2
6232 22:13:04.960506 BL = 0x2
6233 22:13:04.964009 RPST = 0x0
6234 22:13:04.964097 RD_PRE = 0x0
6235 22:13:04.967020 WR_PRE = 0x1
6236 22:13:04.967127 WR_PST = 0x0
6237 22:13:04.970736 DBI_WR = 0x0
6238 22:13:04.970818 DBI_RD = 0x0
6239 22:13:04.973784 OTF = 0x1
6240 22:13:04.977387 ===================================
6241 22:13:04.980352 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6242 22:13:04.983756 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6243 22:13:04.990608 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6244 22:13:04.993731 ===================================
6245 22:13:04.993808 LPDDR4 DRAM CONFIGURATION
6246 22:13:04.996603 ===================================
6247 22:13:04.999919 EX_ROW_EN[0] = 0x10
6248 22:13:04.999992 EX_ROW_EN[1] = 0x0
6249 22:13:05.003192 LP4Y_EN = 0x0
6250 22:13:05.006827 WORK_FSP = 0x0
6251 22:13:05.006909 WL = 0x2
6252 22:13:05.010352 RL = 0x2
6253 22:13:05.010434 BL = 0x2
6254 22:13:05.013623 RPST = 0x0
6255 22:13:05.013704 RD_PRE = 0x0
6256 22:13:05.016853 WR_PRE = 0x1
6257 22:13:05.016935 WR_PST = 0x0
6258 22:13:05.020288 DBI_WR = 0x0
6259 22:13:05.020369 DBI_RD = 0x0
6260 22:13:05.023112 OTF = 0x1
6261 22:13:05.026234 ===================================
6262 22:13:05.032900 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6263 22:13:05.036249 nWR fixed to 30
6264 22:13:05.036331 [ModeRegInit_LP4] CH0 RK0
6265 22:13:05.039453 [ModeRegInit_LP4] CH0 RK1
6266 22:13:05.043237 [ModeRegInit_LP4] CH1 RK0
6267 22:13:05.046121 [ModeRegInit_LP4] CH1 RK1
6268 22:13:05.046225 match AC timing 19
6269 22:13:05.049786 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6270 22:13:05.056305 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6271 22:13:05.059688 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6272 22:13:05.066365 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6273 22:13:05.069152 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6274 22:13:05.069252 ==
6275 22:13:05.072941 Dram Type= 6, Freq= 0, CH_0, rank 0
6276 22:13:05.075716 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6277 22:13:05.075797 ==
6278 22:13:05.082433 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6279 22:13:05.088855 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6280 22:13:05.092292 [CA 0] Center 36 (8~64) winsize 57
6281 22:13:05.095758 [CA 1] Center 36 (8~64) winsize 57
6282 22:13:05.099244 [CA 2] Center 36 (8~64) winsize 57
6283 22:13:05.099346 [CA 3] Center 36 (8~64) winsize 57
6284 22:13:05.102442 [CA 4] Center 36 (8~64) winsize 57
6285 22:13:05.105388 [CA 5] Center 36 (8~64) winsize 57
6286 22:13:05.105491
6287 22:13:05.112107 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6288 22:13:05.112185
6289 22:13:05.115516 [CATrainingPosCal] consider 1 rank data
6290 22:13:05.118786 u2DelayCellTimex100 = 270/100 ps
6291 22:13:05.122072 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6292 22:13:05.125493 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6293 22:13:05.129041 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6294 22:13:05.131973 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6295 22:13:05.135212 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6296 22:13:05.138354 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6297 22:13:05.138452
6298 22:13:05.141845 CA PerBit enable=1, Macro0, CA PI delay=36
6299 22:13:05.141934
6300 22:13:05.145080 [CBTSetCACLKResult] CA Dly = 36
6301 22:13:05.148522 CS Dly: 1 (0~32)
6302 22:13:05.148594 ==
6303 22:13:05.151433 Dram Type= 6, Freq= 0, CH_0, rank 1
6304 22:13:05.155421 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6305 22:13:05.155493 ==
6306 22:13:05.161602 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6307 22:13:05.168061 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6308 22:13:05.168135 [CA 0] Center 36 (8~64) winsize 57
6309 22:13:05.171588 [CA 1] Center 36 (8~64) winsize 57
6310 22:13:05.175231 [CA 2] Center 36 (8~64) winsize 57
6311 22:13:05.178166 [CA 3] Center 36 (8~64) winsize 57
6312 22:13:05.181222 [CA 4] Center 36 (8~64) winsize 57
6313 22:13:05.184980 [CA 5] Center 36 (8~64) winsize 57
6314 22:13:05.185061
6315 22:13:05.188001 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6316 22:13:05.188081
6317 22:13:05.191450 [CATrainingPosCal] consider 2 rank data
6318 22:13:05.194960 u2DelayCellTimex100 = 270/100 ps
6319 22:13:05.198223 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6320 22:13:05.204522 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6321 22:13:05.207650 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6322 22:13:05.211229 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6323 22:13:05.214477 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6324 22:13:05.217978 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6325 22:13:05.218059
6326 22:13:05.221218 CA PerBit enable=1, Macro0, CA PI delay=36
6327 22:13:05.221303
6328 22:13:05.224190 [CBTSetCACLKResult] CA Dly = 36
6329 22:13:05.227480 CS Dly: 1 (0~32)
6330 22:13:05.227560
6331 22:13:05.230704 ----->DramcWriteLeveling(PI) begin...
6332 22:13:05.230787 ==
6333 22:13:05.234181 Dram Type= 6, Freq= 0, CH_0, rank 0
6334 22:13:05.237654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6335 22:13:05.237736 ==
6336 22:13:05.241252 Write leveling (Byte 0): 40 => 8
6337 22:13:05.244133 Write leveling (Byte 1): 40 => 8
6338 22:13:05.247604 DramcWriteLeveling(PI) end<-----
6339 22:13:05.247699
6340 22:13:05.247763 ==
6341 22:13:05.250595 Dram Type= 6, Freq= 0, CH_0, rank 0
6342 22:13:05.254208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6343 22:13:05.254291 ==
6344 22:13:05.257354 [Gating] SW mode calibration
6345 22:13:05.263863 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6346 22:13:05.270297 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6347 22:13:05.273923 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6348 22:13:05.277313 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6349 22:13:05.283930 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6350 22:13:05.286799 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6351 22:13:05.290500 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6352 22:13:05.296597 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6353 22:13:05.299952 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6354 22:13:05.303483 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6355 22:13:05.309981 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6356 22:13:05.313219 Total UI for P1: 0, mck2ui 16
6357 22:13:05.316663 best dqsien dly found for B0: ( 0, 14, 24)
6358 22:13:05.316734 Total UI for P1: 0, mck2ui 16
6359 22:13:05.323240 best dqsien dly found for B1: ( 0, 14, 24)
6360 22:13:05.326649 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6361 22:13:05.329925 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6362 22:13:05.329997
6363 22:13:05.333425 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6364 22:13:05.336523 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6365 22:13:05.339803 [Gating] SW calibration Done
6366 22:13:05.339906 ==
6367 22:13:05.343499 Dram Type= 6, Freq= 0, CH_0, rank 0
6368 22:13:05.346674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6369 22:13:05.346770 ==
6370 22:13:05.349474 RX Vref Scan: 0
6371 22:13:05.349543
6372 22:13:05.352986 RX Vref 0 -> 0, step: 1
6373 22:13:05.353056
6374 22:13:05.353118 RX Delay -410 -> 252, step: 16
6375 22:13:05.359571 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6376 22:13:05.362647 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6377 22:13:05.366284 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6378 22:13:05.372162 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6379 22:13:05.375920 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6380 22:13:05.379081 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6381 22:13:05.382602 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6382 22:13:05.388926 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6383 22:13:05.392487 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6384 22:13:05.395611 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6385 22:13:05.398663 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6386 22:13:05.405287 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6387 22:13:05.408391 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6388 22:13:05.411783 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6389 22:13:05.418639 iDelay=230, Bit 14, Center -35 (-298 ~ 229) 528
6390 22:13:05.421818 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6391 22:13:05.421917 ==
6392 22:13:05.425238 Dram Type= 6, Freq= 0, CH_0, rank 0
6393 22:13:05.428370 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6394 22:13:05.428443 ==
6395 22:13:05.431775 DQS Delay:
6396 22:13:05.431848 DQS0 = 59, DQS1 = 59
6397 22:13:05.431909 DQM Delay:
6398 22:13:05.435049 DQM0 = 18, DQM1 = 10
6399 22:13:05.435122 DQ Delay:
6400 22:13:05.438398 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6401 22:13:05.441725 DQ4 =16, DQ5 =0, DQ6 =32, DQ7 =32
6402 22:13:05.444972 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6403 22:13:05.448204 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6404 22:13:05.448288
6405 22:13:05.448354
6406 22:13:05.448414 ==
6407 22:13:05.451563 Dram Type= 6, Freq= 0, CH_0, rank 0
6408 22:13:05.458219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6409 22:13:05.458302 ==
6410 22:13:05.458369
6411 22:13:05.458429
6412 22:13:05.458487 TX Vref Scan disable
6413 22:13:05.461415 == TX Byte 0 ==
6414 22:13:05.464714 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6415 22:13:05.467909 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6416 22:13:05.471347 == TX Byte 1 ==
6417 22:13:05.474328 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6418 22:13:05.478012 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6419 22:13:05.478095 ==
6420 22:13:05.480977 Dram Type= 6, Freq= 0, CH_0, rank 0
6421 22:13:05.487495 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6422 22:13:05.487643 ==
6423 22:13:05.487711
6424 22:13:05.487773
6425 22:13:05.487832 TX Vref Scan disable
6426 22:13:05.491036 == TX Byte 0 ==
6427 22:13:05.494666 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6428 22:13:05.497596 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6429 22:13:05.500812 == TX Byte 1 ==
6430 22:13:05.504319 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6431 22:13:05.507287 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6432 22:13:05.510937
6433 22:13:05.511019 [DATLAT]
6434 22:13:05.511084 Freq=400, CH0 RK0
6435 22:13:05.511144
6436 22:13:05.514312 DATLAT Default: 0xf
6437 22:13:05.514394 0, 0xFFFF, sum = 0
6438 22:13:05.517356 1, 0xFFFF, sum = 0
6439 22:13:05.517440 2, 0xFFFF, sum = 0
6440 22:13:05.520578 3, 0xFFFF, sum = 0
6441 22:13:05.520662 4, 0xFFFF, sum = 0
6442 22:13:05.524224 5, 0xFFFF, sum = 0
6443 22:13:05.527209 6, 0xFFFF, sum = 0
6444 22:13:05.527294 7, 0xFFFF, sum = 0
6445 22:13:05.530689 8, 0xFFFF, sum = 0
6446 22:13:05.530774 9, 0xFFFF, sum = 0
6447 22:13:05.533777 10, 0xFFFF, sum = 0
6448 22:13:05.533861 11, 0xFFFF, sum = 0
6449 22:13:05.537228 12, 0xFFFF, sum = 0
6450 22:13:05.537312 13, 0x0, sum = 1
6451 22:13:05.540555 14, 0x0, sum = 2
6452 22:13:05.540639 15, 0x0, sum = 3
6453 22:13:05.544009 16, 0x0, sum = 4
6454 22:13:05.544093 best_step = 14
6455 22:13:05.544159
6456 22:13:05.544218 ==
6457 22:13:05.546730 Dram Type= 6, Freq= 0, CH_0, rank 0
6458 22:13:05.550190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6459 22:13:05.553311 ==
6460 22:13:05.553394 RX Vref Scan: 1
6461 22:13:05.553459
6462 22:13:05.556552 RX Vref 0 -> 0, step: 1
6463 22:13:05.556634
6464 22:13:05.559864 RX Delay -359 -> 252, step: 8
6465 22:13:05.559947
6466 22:13:05.563268 Set Vref, RX VrefLevel [Byte0]: 61
6467 22:13:05.566593 [Byte1]: 53
6468 22:13:05.566676
6469 22:13:05.570016 Final RX Vref Byte 0 = 61 to rank0
6470 22:13:05.573072 Final RX Vref Byte 1 = 53 to rank0
6471 22:13:05.576768 Final RX Vref Byte 0 = 61 to rank1
6472 22:13:05.579541 Final RX Vref Byte 1 = 53 to rank1==
6473 22:13:05.583170 Dram Type= 6, Freq= 0, CH_0, rank 0
6474 22:13:05.586657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6475 22:13:05.589700 ==
6476 22:13:05.589782 DQS Delay:
6477 22:13:05.589848 DQS0 = 60, DQS1 = 68
6478 22:13:05.592851 DQM Delay:
6479 22:13:05.592934 DQM0 = 15, DQM1 = 13
6480 22:13:05.596108 DQ Delay:
6481 22:13:05.599530 DQ0 =12, DQ1 =16, DQ2 =16, DQ3 =12
6482 22:13:05.599650 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6483 22:13:05.602740 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6484 22:13:05.606333 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6485 22:13:05.606415
6486 22:13:05.609297
6487 22:13:05.616143 [DQSOSCAuto] RK0, (LSB)MR18= 0x8180, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
6488 22:13:05.619547 CH0 RK0: MR19=C0C, MR18=8180
6489 22:13:05.626441 CH0_RK0: MR19=0xC0C, MR18=0x8180, DQSOSC=393, MR23=63, INC=382, DEC=254
6490 22:13:05.626524 ==
6491 22:13:05.629243 Dram Type= 6, Freq= 0, CH_0, rank 1
6492 22:13:05.632447 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6493 22:13:05.632534 ==
6494 22:13:05.636112 [Gating] SW mode calibration
6495 22:13:05.642457 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6496 22:13:05.648771 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6497 22:13:05.652188 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6498 22:13:05.655420 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6499 22:13:05.662241 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6500 22:13:05.665475 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6501 22:13:05.668752 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6502 22:13:05.675587 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6503 22:13:05.678698 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6504 22:13:05.682304 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6505 22:13:05.688739 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6506 22:13:05.688821 Total UI for P1: 0, mck2ui 16
6507 22:13:05.695441 best dqsien dly found for B0: ( 0, 14, 24)
6508 22:13:05.695552 Total UI for P1: 0, mck2ui 16
6509 22:13:05.702048 best dqsien dly found for B1: ( 0, 14, 24)
6510 22:13:05.704859 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6511 22:13:05.708558 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6512 22:13:05.708639
6513 22:13:05.711753 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6514 22:13:05.715113 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6515 22:13:05.718180 [Gating] SW calibration Done
6516 22:13:05.718261 ==
6517 22:13:05.721917 Dram Type= 6, Freq= 0, CH_0, rank 1
6518 22:13:05.724608 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6519 22:13:05.724690 ==
6520 22:13:05.727985 RX Vref Scan: 0
6521 22:13:05.728066
6522 22:13:05.728132 RX Vref 0 -> 0, step: 1
6523 22:13:05.728192
6524 22:13:05.731547 RX Delay -410 -> 252, step: 16
6525 22:13:05.738049 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6526 22:13:05.741237 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6527 22:13:05.744667 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6528 22:13:05.747929 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6529 22:13:05.754742 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6530 22:13:05.757622 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6531 22:13:05.761135 iDelay=230, Bit 6, Center -35 (-298 ~ 229) 528
6532 22:13:05.764408 iDelay=230, Bit 7, Center -35 (-298 ~ 229) 528
6533 22:13:05.770951 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6534 22:13:05.773954 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6535 22:13:05.777310 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6536 22:13:05.784603 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6537 22:13:05.787352 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6538 22:13:05.790809 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6539 22:13:05.793870 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6540 22:13:05.800725 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6541 22:13:05.800811 ==
6542 22:13:05.804350 Dram Type= 6, Freq= 0, CH_0, rank 1
6543 22:13:05.807312 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6544 22:13:05.807397 ==
6545 22:13:05.807499 DQS Delay:
6546 22:13:05.810779 DQS0 = 59, DQS1 = 59
6547 22:13:05.810864 DQM Delay:
6548 22:13:05.813798 DQM0 = 16, DQM1 = 10
6549 22:13:05.813884 DQ Delay:
6550 22:13:05.817649 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6551 22:13:05.820480 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6552 22:13:05.823748 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6553 22:13:05.827134 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6554 22:13:05.827217
6555 22:13:05.827282
6556 22:13:05.827343 ==
6557 22:13:05.830238 Dram Type= 6, Freq= 0, CH_0, rank 1
6558 22:13:05.833641 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6559 22:13:05.836871 ==
6560 22:13:05.836954
6561 22:13:05.837019
6562 22:13:05.837080 TX Vref Scan disable
6563 22:13:05.840484 == TX Byte 0 ==
6564 22:13:05.843477 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6565 22:13:05.846588 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6566 22:13:05.850232 == TX Byte 1 ==
6567 22:13:05.853549 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6568 22:13:05.856444 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6569 22:13:05.856529 ==
6570 22:13:05.860336 Dram Type= 6, Freq= 0, CH_0, rank 1
6571 22:13:05.866642 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6572 22:13:05.866728 ==
6573 22:13:05.866814
6574 22:13:05.866894
6575 22:13:05.866973 TX Vref Scan disable
6576 22:13:05.869901 == TX Byte 0 ==
6577 22:13:05.873192 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6578 22:13:05.876536 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6579 22:13:05.879853 == TX Byte 1 ==
6580 22:13:05.882816 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6581 22:13:05.886819 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6582 22:13:05.886904
6583 22:13:05.889547 [DATLAT]
6584 22:13:05.889632 Freq=400, CH0 RK1
6585 22:13:05.889718
6586 22:13:05.892877 DATLAT Default: 0xe
6587 22:13:05.892961 0, 0xFFFF, sum = 0
6588 22:13:05.896430 1, 0xFFFF, sum = 0
6589 22:13:05.896516 2, 0xFFFF, sum = 0
6590 22:13:05.899459 3, 0xFFFF, sum = 0
6591 22:13:05.899546 4, 0xFFFF, sum = 0
6592 22:13:05.903269 5, 0xFFFF, sum = 0
6593 22:13:05.903356 6, 0xFFFF, sum = 0
6594 22:13:05.906262 7, 0xFFFF, sum = 0
6595 22:13:05.906349 8, 0xFFFF, sum = 0
6596 22:13:05.909612 9, 0xFFFF, sum = 0
6597 22:13:05.909699 10, 0xFFFF, sum = 0
6598 22:13:05.912685 11, 0xFFFF, sum = 0
6599 22:13:05.916046 12, 0xFFFF, sum = 0
6600 22:13:05.916132 13, 0x0, sum = 1
6601 22:13:05.919051 14, 0x0, sum = 2
6602 22:13:05.919137 15, 0x0, sum = 3
6603 22:13:05.919224 16, 0x0, sum = 4
6604 22:13:05.922599 best_step = 14
6605 22:13:05.922684
6606 22:13:05.922768 ==
6607 22:13:05.925790 Dram Type= 6, Freq= 0, CH_0, rank 1
6608 22:13:05.929226 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6609 22:13:05.929313 ==
6610 22:13:05.932361 RX Vref Scan: 0
6611 22:13:05.932445
6612 22:13:05.935780 RX Vref 0 -> 0, step: 1
6613 22:13:05.935865
6614 22:13:05.935950 RX Delay -359 -> 252, step: 8
6615 22:13:05.944473 iDelay=217, Bit 0, Center -52 (-303 ~ 200) 504
6616 22:13:05.947558 iDelay=217, Bit 1, Center -44 (-295 ~ 208) 504
6617 22:13:05.951104 iDelay=217, Bit 2, Center -52 (-303 ~ 200) 504
6618 22:13:05.957609 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6619 22:13:05.960633 iDelay=217, Bit 4, Center -52 (-303 ~ 200) 504
6620 22:13:05.964002 iDelay=217, Bit 5, Center -60 (-311 ~ 192) 504
6621 22:13:05.967531 iDelay=217, Bit 6, Center -40 (-295 ~ 216) 512
6622 22:13:05.973769 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6623 22:13:05.977053 iDelay=217, Bit 8, Center -60 (-311 ~ 192) 504
6624 22:13:05.980661 iDelay=217, Bit 9, Center -72 (-319 ~ 176) 496
6625 22:13:05.983804 iDelay=217, Bit 10, Center -52 (-303 ~ 200) 504
6626 22:13:05.990135 iDelay=217, Bit 11, Center -64 (-311 ~ 184) 496
6627 22:13:05.993895 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6628 22:13:05.996826 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
6629 22:13:06.000800 iDelay=217, Bit 14, Center -44 (-295 ~ 208) 504
6630 22:13:06.006673 iDelay=217, Bit 15, Center -48 (-295 ~ 200) 496
6631 22:13:06.006757 ==
6632 22:13:06.009872 Dram Type= 6, Freq= 0, CH_0, rank 1
6633 22:13:06.013506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6634 22:13:06.013592 ==
6635 22:13:06.016918 DQS Delay:
6636 22:13:06.017003 DQS0 = 60, DQS1 = 72
6637 22:13:06.017088 DQM Delay:
6638 22:13:06.020415 DQM0 = 11, DQM1 = 17
6639 22:13:06.020500 DQ Delay:
6640 22:13:06.023360 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6641 22:13:06.026852 DQ4 =8, DQ5 =0, DQ6 =20, DQ7 =24
6642 22:13:06.030057 DQ8 =12, DQ9 =0, DQ10 =20, DQ11 =8
6643 22:13:06.033371 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =24
6644 22:13:06.033452
6645 22:13:06.033517
6646 22:13:06.042940 [DQSOSCAuto] RK1, (LSB)MR18= 0xc67c, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 385 ps
6647 22:13:06.043047 CH0 RK1: MR19=C0C, MR18=C67C
6648 22:13:06.049767 CH0_RK1: MR19=0xC0C, MR18=0xC67C, DQSOSC=385, MR23=63, INC=398, DEC=265
6649 22:13:06.053326 [RxdqsGatingPostProcess] freq 400
6650 22:13:06.059820 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6651 22:13:06.062628 best DQS0 dly(2T, 0.5T) = (0, 10)
6652 22:13:06.066443 best DQS1 dly(2T, 0.5T) = (0, 10)
6653 22:13:06.069729 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6654 22:13:06.073011 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6655 22:13:06.076255 best DQS0 dly(2T, 0.5T) = (0, 10)
6656 22:13:06.079555 best DQS1 dly(2T, 0.5T) = (0, 10)
6657 22:13:06.079677 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6658 22:13:06.082959 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6659 22:13:06.086250 Pre-setting of DQS Precalculation
6660 22:13:06.092976 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6661 22:13:06.093057 ==
6662 22:13:06.095689 Dram Type= 6, Freq= 0, CH_1, rank 0
6663 22:13:06.099231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6664 22:13:06.099313 ==
6665 22:13:06.105656 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6666 22:13:06.112913 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6667 22:13:06.115780 [CA 0] Center 36 (8~64) winsize 57
6668 22:13:06.118831 [CA 1] Center 36 (8~64) winsize 57
6669 22:13:06.122398 [CA 2] Center 36 (8~64) winsize 57
6670 22:13:06.125791 [CA 3] Center 36 (8~64) winsize 57
6671 22:13:06.125873 [CA 4] Center 36 (8~64) winsize 57
6672 22:13:06.128702 [CA 5] Center 36 (8~64) winsize 57
6673 22:13:06.128785
6674 22:13:06.135304 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6675 22:13:06.135387
6676 22:13:06.138972 [CATrainingPosCal] consider 1 rank data
6677 22:13:06.142378 u2DelayCellTimex100 = 270/100 ps
6678 22:13:06.145248 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6679 22:13:06.148692 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6680 22:13:06.152349 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6681 22:13:06.155379 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6682 22:13:06.158396 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6683 22:13:06.161592 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6684 22:13:06.161675
6685 22:13:06.164973 CA PerBit enable=1, Macro0, CA PI delay=36
6686 22:13:06.165056
6687 22:13:06.168513 [CBTSetCACLKResult] CA Dly = 36
6688 22:13:06.171494 CS Dly: 1 (0~32)
6689 22:13:06.171581 ==
6690 22:13:06.175305 Dram Type= 6, Freq= 0, CH_1, rank 1
6691 22:13:06.178479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6692 22:13:06.178562 ==
6693 22:13:06.185058 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6694 22:13:06.191327 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6695 22:13:06.194523 [CA 0] Center 36 (8~64) winsize 57
6696 22:13:06.197792 [CA 1] Center 36 (8~64) winsize 57
6697 22:13:06.201180 [CA 2] Center 36 (8~64) winsize 57
6698 22:13:06.201264 [CA 3] Center 36 (8~64) winsize 57
6699 22:13:06.204680 [CA 4] Center 36 (8~64) winsize 57
6700 22:13:06.207776 [CA 5] Center 36 (8~64) winsize 57
6701 22:13:06.207859
6702 22:13:06.211197 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6703 22:13:06.214596
6704 22:13:06.217540 [CATrainingPosCal] consider 2 rank data
6705 22:13:06.217625 u2DelayCellTimex100 = 270/100 ps
6706 22:13:06.224400 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6707 22:13:06.227471 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6708 22:13:06.231350 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6709 22:13:06.234590 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6710 22:13:06.237742 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6711 22:13:06.241366 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6712 22:13:06.241447
6713 22:13:06.244289 CA PerBit enable=1, Macro0, CA PI delay=36
6714 22:13:06.244371
6715 22:13:06.247464 [CBTSetCACLKResult] CA Dly = 36
6716 22:13:06.250768 CS Dly: 1 (0~32)
6717 22:13:06.250850
6718 22:13:06.253790 ----->DramcWriteLeveling(PI) begin...
6719 22:13:06.253873 ==
6720 22:13:06.257594 Dram Type= 6, Freq= 0, CH_1, rank 0
6721 22:13:06.260567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6722 22:13:06.260650 ==
6723 22:13:06.263548 Write leveling (Byte 0): 40 => 8
6724 22:13:06.267155 Write leveling (Byte 1): 40 => 8
6725 22:13:06.270098 DramcWriteLeveling(PI) end<-----
6726 22:13:06.270180
6727 22:13:06.270246 ==
6728 22:13:06.273853 Dram Type= 6, Freq= 0, CH_1, rank 0
6729 22:13:06.276844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6730 22:13:06.276927 ==
6731 22:13:06.280499 [Gating] SW mode calibration
6732 22:13:06.286786 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6733 22:13:06.293356 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6734 22:13:06.296538 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6735 22:13:06.303084 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6736 22:13:06.306445 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6737 22:13:06.309672 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6738 22:13:06.316367 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6739 22:13:06.319546 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6740 22:13:06.323167 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6741 22:13:06.329732 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6742 22:13:06.332619 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6743 22:13:06.336321 Total UI for P1: 0, mck2ui 16
6744 22:13:06.339439 best dqsien dly found for B0: ( 0, 14, 24)
6745 22:13:06.342881 Total UI for P1: 0, mck2ui 16
6746 22:13:06.345622 best dqsien dly found for B1: ( 0, 14, 24)
6747 22:13:06.349412 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6748 22:13:06.352407 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6749 22:13:06.352489
6750 22:13:06.355767 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6751 22:13:06.359385 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6752 22:13:06.362266 [Gating] SW calibration Done
6753 22:13:06.362348 ==
6754 22:13:06.365842 Dram Type= 6, Freq= 0, CH_1, rank 0
6755 22:13:06.372619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6756 22:13:06.372701 ==
6757 22:13:06.372767 RX Vref Scan: 0
6758 22:13:06.372828
6759 22:13:06.375539 RX Vref 0 -> 0, step: 1
6760 22:13:06.375639
6761 22:13:06.379233 RX Delay -410 -> 252, step: 16
6762 22:13:06.382219 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6763 22:13:06.385822 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6764 22:13:06.392168 iDelay=230, Bit 2, Center -51 (-314 ~ 213) 528
6765 22:13:06.395586 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6766 22:13:06.398906 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6767 22:13:06.401865 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6768 22:13:06.408305 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6769 22:13:06.411788 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6770 22:13:06.415758 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6771 22:13:06.418359 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6772 22:13:06.424857 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6773 22:13:06.428213 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6774 22:13:06.431712 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6775 22:13:06.434661 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6776 22:13:06.441892 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6777 22:13:06.444988 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6778 22:13:06.445071 ==
6779 22:13:06.448464 Dram Type= 6, Freq= 0, CH_1, rank 0
6780 22:13:06.451375 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6781 22:13:06.451457 ==
6782 22:13:06.454719 DQS Delay:
6783 22:13:06.454802 DQS0 = 51, DQS1 = 67
6784 22:13:06.458379 DQM Delay:
6785 22:13:06.458461 DQM0 = 12, DQM1 = 18
6786 22:13:06.461296 DQ Delay:
6787 22:13:06.461378 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6788 22:13:06.464412 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6789 22:13:06.467929 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6790 22:13:06.470994 DQ12 =24, DQ13 =32, DQ14 =24, DQ15 =24
6791 22:13:06.471076
6792 22:13:06.471141
6793 22:13:06.471201 ==
6794 22:13:06.474663 Dram Type= 6, Freq= 0, CH_1, rank 0
6795 22:13:06.481192 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6796 22:13:06.481275 ==
6797 22:13:06.481340
6798 22:13:06.481403
6799 22:13:06.484240 TX Vref Scan disable
6800 22:13:06.484322 == TX Byte 0 ==
6801 22:13:06.487334 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6802 22:13:06.494202 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6803 22:13:06.494287 == TX Byte 1 ==
6804 22:13:06.497333 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6805 22:13:06.503878 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6806 22:13:06.503960 ==
6807 22:13:06.507367 Dram Type= 6, Freq= 0, CH_1, rank 0
6808 22:13:06.510975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6809 22:13:06.511059 ==
6810 22:13:06.511124
6811 22:13:06.511185
6812 22:13:06.513718 TX Vref Scan disable
6813 22:13:06.513800 == TX Byte 0 ==
6814 22:13:06.517029 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6815 22:13:06.523895 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6816 22:13:06.523977 == TX Byte 1 ==
6817 22:13:06.526811 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6818 22:13:06.534074 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6819 22:13:06.534156
6820 22:13:06.534221 [DATLAT]
6821 22:13:06.534281 Freq=400, CH1 RK0
6822 22:13:06.537389
6823 22:13:06.537470 DATLAT Default: 0xf
6824 22:13:06.539996 0, 0xFFFF, sum = 0
6825 22:13:06.540079 1, 0xFFFF, sum = 0
6826 22:13:06.543529 2, 0xFFFF, sum = 0
6827 22:13:06.543621 3, 0xFFFF, sum = 0
6828 22:13:06.546546 4, 0xFFFF, sum = 0
6829 22:13:06.546621 5, 0xFFFF, sum = 0
6830 22:13:06.550291 6, 0xFFFF, sum = 0
6831 22:13:06.550380 7, 0xFFFF, sum = 0
6832 22:13:06.553365 8, 0xFFFF, sum = 0
6833 22:13:06.553448 9, 0xFFFF, sum = 0
6834 22:13:06.556665 10, 0xFFFF, sum = 0
6835 22:13:06.556749 11, 0xFFFF, sum = 0
6836 22:13:06.560161 12, 0xFFFF, sum = 0
6837 22:13:06.560244 13, 0x0, sum = 1
6838 22:13:06.563506 14, 0x0, sum = 2
6839 22:13:06.563610 15, 0x0, sum = 3
6840 22:13:06.566536 16, 0x0, sum = 4
6841 22:13:06.566618 best_step = 14
6842 22:13:06.566682
6843 22:13:06.566741 ==
6844 22:13:06.569647 Dram Type= 6, Freq= 0, CH_1, rank 0
6845 22:13:06.576714 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6846 22:13:06.576796 ==
6847 22:13:06.576861 RX Vref Scan: 1
6848 22:13:06.576921
6849 22:13:06.579711 RX Vref 0 -> 0, step: 1
6850 22:13:06.579791
6851 22:13:06.583290 RX Delay -375 -> 252, step: 8
6852 22:13:06.583371
6853 22:13:06.586382 Set Vref, RX VrefLevel [Byte0]: 52
6854 22:13:06.590034 [Byte1]: 53
6855 22:13:06.593007
6856 22:13:06.593088 Final RX Vref Byte 0 = 52 to rank0
6857 22:13:06.595942 Final RX Vref Byte 1 = 53 to rank0
6858 22:13:06.599481 Final RX Vref Byte 0 = 52 to rank1
6859 22:13:06.603070 Final RX Vref Byte 1 = 53 to rank1==
6860 22:13:06.606155 Dram Type= 6, Freq= 0, CH_1, rank 0
6861 22:13:06.612559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6862 22:13:06.612640 ==
6863 22:13:06.612705 DQS Delay:
6864 22:13:06.615983 DQS0 = 56, DQS1 = 64
6865 22:13:06.616064 DQM Delay:
6866 22:13:06.618962 DQM0 = 13, DQM1 = 10
6867 22:13:06.619043 DQ Delay:
6868 22:13:06.622776 DQ0 =20, DQ1 =4, DQ2 =0, DQ3 =12
6869 22:13:06.626053 DQ4 =12, DQ5 =20, DQ6 =24, DQ7 =12
6870 22:13:06.628888 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
6871 22:13:06.632292 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6872 22:13:06.632373
6873 22:13:06.632437
6874 22:13:06.638963 [DQSOSCAuto] RK0, (LSB)MR18= 0x5669, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 398 ps
6875 22:13:06.642361 CH1 RK0: MR19=C0C, MR18=5669
6876 22:13:06.648689 CH1_RK0: MR19=0xC0C, MR18=0x5669, DQSOSC=396, MR23=63, INC=376, DEC=251
6877 22:13:06.648771 ==
6878 22:13:06.652111 Dram Type= 6, Freq= 0, CH_1, rank 1
6879 22:13:06.655869 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6880 22:13:06.655958 ==
6881 22:13:06.658763 [Gating] SW mode calibration
6882 22:13:06.665283 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6883 22:13:06.671681 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6884 22:13:06.675151 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6885 22:13:06.678786 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6886 22:13:06.685288 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6887 22:13:06.688638 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6888 22:13:06.691734 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6889 22:13:06.698693 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6890 22:13:06.701645 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6891 22:13:06.705139 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6892 22:13:06.711197 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6893 22:13:06.714647 Total UI for P1: 0, mck2ui 16
6894 22:13:06.718222 best dqsien dly found for B0: ( 0, 14, 24)
6895 22:13:06.721632 Total UI for P1: 0, mck2ui 16
6896 22:13:06.724423 best dqsien dly found for B1: ( 0, 14, 24)
6897 22:13:06.727792 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6898 22:13:06.731163 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6899 22:13:06.731301
6900 22:13:06.734319 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6901 22:13:06.737670 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6902 22:13:06.741338 [Gating] SW calibration Done
6903 22:13:06.741886 ==
6904 22:13:06.744860 Dram Type= 6, Freq= 0, CH_1, rank 1
6905 22:13:06.747767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6906 22:13:06.751095 ==
6907 22:13:06.751511 RX Vref Scan: 0
6908 22:13:06.751891
6909 22:13:06.754563 RX Vref 0 -> 0, step: 1
6910 22:13:06.754993
6911 22:13:06.757780 RX Delay -410 -> 252, step: 16
6912 22:13:06.761092 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6913 22:13:06.764569 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6914 22:13:06.767448 iDelay=230, Bit 2, Center -59 (-314 ~ 197) 512
6915 22:13:06.774079 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6916 22:13:06.777516 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6917 22:13:06.780767 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6918 22:13:06.784298 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6919 22:13:06.790758 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6920 22:13:06.794535 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6921 22:13:06.797469 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6922 22:13:06.800926 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6923 22:13:06.807726 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6924 22:13:06.810717 iDelay=230, Bit 12, Center -35 (-298 ~ 229) 528
6925 22:13:06.814334 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6926 22:13:06.820752 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6927 22:13:06.824071 iDelay=230, Bit 15, Center -35 (-298 ~ 229) 528
6928 22:13:06.824545 ==
6929 22:13:06.827483 Dram Type= 6, Freq= 0, CH_1, rank 1
6930 22:13:06.830573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6931 22:13:06.831043 ==
6932 22:13:06.834205 DQS Delay:
6933 22:13:06.834669 DQS0 = 59, DQS1 = 67
6934 22:13:06.835043 DQM Delay:
6935 22:13:06.837357 DQM0 = 19, DQM1 = 21
6936 22:13:06.837925 DQ Delay:
6937 22:13:06.840229 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6938 22:13:06.843799 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6939 22:13:06.847215 DQ8 =0, DQ9 =8, DQ10 =24, DQ11 =16
6940 22:13:06.850664 DQ12 =32, DQ13 =32, DQ14 =24, DQ15 =32
6941 22:13:06.851230
6942 22:13:06.851643
6943 22:13:06.852003 ==
6944 22:13:06.853646 Dram Type= 6, Freq= 0, CH_1, rank 1
6945 22:13:06.860269 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6946 22:13:06.860736 ==
6947 22:13:06.861103
6948 22:13:06.861506
6949 22:13:06.861851 TX Vref Scan disable
6950 22:13:06.863163 == TX Byte 0 ==
6951 22:13:06.867154 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6952 22:13:06.869754 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6953 22:13:06.873226 == TX Byte 1 ==
6954 22:13:06.876914 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6955 22:13:06.880041 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6956 22:13:06.883666 ==
6957 22:13:06.884378 Dram Type= 6, Freq= 0, CH_1, rank 1
6958 22:13:06.889986 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6959 22:13:06.890569 ==
6960 22:13:06.890947
6961 22:13:06.891295
6962 22:13:06.892810 TX Vref Scan disable
6963 22:13:06.893279 == TX Byte 0 ==
6964 22:13:06.896240 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6965 22:13:06.903021 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6966 22:13:06.903626 == TX Byte 1 ==
6967 22:13:06.906181 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6968 22:13:06.912398 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6969 22:13:06.913020
6970 22:13:06.913402 [DATLAT]
6971 22:13:06.913751 Freq=400, CH1 RK1
6972 22:13:06.914090
6973 22:13:06.916111 DATLAT Default: 0xe
6974 22:13:06.916582 0, 0xFFFF, sum = 0
6975 22:13:06.919333 1, 0xFFFF, sum = 0
6976 22:13:06.923037 2, 0xFFFF, sum = 0
6977 22:13:06.923646 3, 0xFFFF, sum = 0
6978 22:13:06.926424 4, 0xFFFF, sum = 0
6979 22:13:06.927015 5, 0xFFFF, sum = 0
6980 22:13:06.929251 6, 0xFFFF, sum = 0
6981 22:13:06.929840 7, 0xFFFF, sum = 0
6982 22:13:06.933002 8, 0xFFFF, sum = 0
6983 22:13:06.933608 9, 0xFFFF, sum = 0
6984 22:13:06.935875 10, 0xFFFF, sum = 0
6985 22:13:06.936619 11, 0xFFFF, sum = 0
6986 22:13:06.939460 12, 0xFFFF, sum = 0
6987 22:13:06.940092 13, 0x0, sum = 1
6988 22:13:06.942183 14, 0x0, sum = 2
6989 22:13:06.942658 15, 0x0, sum = 3
6990 22:13:06.946076 16, 0x0, sum = 4
6991 22:13:06.946657 best_step = 14
6992 22:13:06.947039
6993 22:13:06.947392 ==
6994 22:13:06.949246 Dram Type= 6, Freq= 0, CH_1, rank 1
6995 22:13:06.955726 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6996 22:13:06.956435 ==
6997 22:13:06.956989 RX Vref Scan: 0
6998 22:13:06.957363
6999 22:13:06.958851 RX Vref 0 -> 0, step: 1
7000 22:13:06.959319
7001 22:13:06.962330 RX Delay -375 -> 252, step: 8
7002 22:13:06.969041 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
7003 22:13:06.972118 iDelay=217, Bit 1, Center -52 (-303 ~ 200) 504
7004 22:13:06.975614 iDelay=217, Bit 2, Center -56 (-303 ~ 192) 496
7005 22:13:06.978863 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
7006 22:13:06.985297 iDelay=217, Bit 4, Center -44 (-295 ~ 208) 504
7007 22:13:06.988514 iDelay=217, Bit 5, Center -36 (-287 ~ 216) 504
7008 22:13:06.992526 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
7009 22:13:06.995111 iDelay=217, Bit 7, Center -52 (-303 ~ 200) 504
7010 22:13:07.001456 iDelay=217, Bit 8, Center -64 (-319 ~ 192) 512
7011 22:13:07.005059 iDelay=217, Bit 9, Center -64 (-319 ~ 192) 512
7012 22:13:07.007992 iDelay=217, Bit 10, Center -48 (-303 ~ 208) 512
7013 22:13:07.014942 iDelay=217, Bit 11, Center -64 (-319 ~ 192) 512
7014 22:13:07.018392 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
7015 22:13:07.021195 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
7016 22:13:07.025248 iDelay=217, Bit 14, Center -48 (-303 ~ 208) 512
7017 22:13:07.031465 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
7018 22:13:07.032080 ==
7019 22:13:07.034354 Dram Type= 6, Freq= 0, CH_1, rank 1
7020 22:13:07.038224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7021 22:13:07.038828 ==
7022 22:13:07.039207 DQS Delay:
7023 22:13:07.041207 DQS0 = 56, DQS1 = 64
7024 22:13:07.041807 DQM Delay:
7025 22:13:07.044583 DQM0 = 9, DQM1 = 10
7026 22:13:07.045158 DQ Delay:
7027 22:13:07.047898 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
7028 22:13:07.051201 DQ4 =12, DQ5 =20, DQ6 =20, DQ7 =4
7029 22:13:07.054279 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
7030 22:13:07.057349 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
7031 22:13:07.057822
7032 22:13:07.058198
7033 22:13:07.063986 [DQSOSCAuto] RK1, (LSB)MR18= 0x78aa, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 394 ps
7034 22:13:07.067348 CH1 RK1: MR19=C0C, MR18=78AA
7035 22:13:07.073951 CH1_RK1: MR19=0xC0C, MR18=0x78AA, DQSOSC=388, MR23=63, INC=392, DEC=261
7036 22:13:07.077539 [RxdqsGatingPostProcess] freq 400
7037 22:13:07.083985 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7038 22:13:07.087090 best DQS0 dly(2T, 0.5T) = (0, 10)
7039 22:13:07.090568 best DQS1 dly(2T, 0.5T) = (0, 10)
7040 22:13:07.094010 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7041 22:13:07.096588 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7042 22:13:07.100487 best DQS0 dly(2T, 0.5T) = (0, 10)
7043 22:13:07.100962 best DQS1 dly(2T, 0.5T) = (0, 10)
7044 22:13:07.103272 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7045 22:13:07.106914 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7046 22:13:07.110134 Pre-setting of DQS Precalculation
7047 22:13:07.116573 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7048 22:13:07.123265 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7049 22:13:07.129902 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7050 22:13:07.130489
7051 22:13:07.130909
7052 22:13:07.133175 [Calibration Summary] 800 Mbps
7053 22:13:07.136274 CH 0, Rank 0
7054 22:13:07.136846 SW Impedance : PASS
7055 22:13:07.140206 DUTY Scan : NO K
7056 22:13:07.143195 ZQ Calibration : PASS
7057 22:13:07.143812 Jitter Meter : NO K
7058 22:13:07.146564 CBT Training : PASS
7059 22:13:07.147134 Write leveling : PASS
7060 22:13:07.149647 RX DQS gating : PASS
7061 22:13:07.153102 RX DQ/DQS(RDDQC) : PASS
7062 22:13:07.153676 TX DQ/DQS : PASS
7063 22:13:07.156215 RX DATLAT : PASS
7064 22:13:07.160018 RX DQ/DQS(Engine): PASS
7065 22:13:07.160596 TX OE : NO K
7066 22:13:07.162785 All Pass.
7067 22:13:07.163358
7068 22:13:07.163787 CH 0, Rank 1
7069 22:13:07.166170 SW Impedance : PASS
7070 22:13:07.166750 DUTY Scan : NO K
7071 22:13:07.169197 ZQ Calibration : PASS
7072 22:13:07.172330 Jitter Meter : NO K
7073 22:13:07.172799 CBT Training : PASS
7074 22:13:07.175674 Write leveling : NO K
7075 22:13:07.179291 RX DQS gating : PASS
7076 22:13:07.179793 RX DQ/DQS(RDDQC) : PASS
7077 22:13:07.182285 TX DQ/DQS : PASS
7078 22:13:07.185716 RX DATLAT : PASS
7079 22:13:07.186292 RX DQ/DQS(Engine): PASS
7080 22:13:07.189015 TX OE : NO K
7081 22:13:07.189595 All Pass.
7082 22:13:07.189978
7083 22:13:07.192193 CH 1, Rank 0
7084 22:13:07.192664 SW Impedance : PASS
7085 22:13:07.195529 DUTY Scan : NO K
7086 22:13:07.198746 ZQ Calibration : PASS
7087 22:13:07.199217 Jitter Meter : NO K
7088 22:13:07.202323 CBT Training : PASS
7089 22:13:07.205965 Write leveling : PASS
7090 22:13:07.206547 RX DQS gating : PASS
7091 22:13:07.208836 RX DQ/DQS(RDDQC) : PASS
7092 22:13:07.212275 TX DQ/DQS : PASS
7093 22:13:07.212749 RX DATLAT : PASS
7094 22:13:07.215571 RX DQ/DQS(Engine): PASS
7095 22:13:07.216181 TX OE : NO K
7096 22:13:07.219374 All Pass.
7097 22:13:07.220000
7098 22:13:07.220381 CH 1, Rank 1
7099 22:13:07.222276 SW Impedance : PASS
7100 22:13:07.225889 DUTY Scan : NO K
7101 22:13:07.226476 ZQ Calibration : PASS
7102 22:13:07.228512 Jitter Meter : NO K
7103 22:13:07.228983 CBT Training : PASS
7104 22:13:07.232383 Write leveling : NO K
7105 22:13:07.235378 RX DQS gating : PASS
7106 22:13:07.236003 RX DQ/DQS(RDDQC) : PASS
7107 22:13:07.239082 TX DQ/DQS : PASS
7108 22:13:07.241775 RX DATLAT : PASS
7109 22:13:07.242348 RX DQ/DQS(Engine): PASS
7110 22:13:07.245240 TX OE : NO K
7111 22:13:07.245713 All Pass.
7112 22:13:07.246088
7113 22:13:07.248458 DramC Write-DBI off
7114 22:13:07.251881 PER_BANK_REFRESH: Hybrid Mode
7115 22:13:07.252455 TX_TRACKING: ON
7116 22:13:07.261626 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7117 22:13:07.265302 [FAST_K] Save calibration result to emmc
7118 22:13:07.268343 dramc_set_vcore_voltage set vcore to 725000
7119 22:13:07.271868 Read voltage for 1600, 0
7120 22:13:07.272446 Vio18 = 0
7121 22:13:07.274813 Vcore = 725000
7122 22:13:07.275389 Vdram = 0
7123 22:13:07.275830 Vddq = 0
7124 22:13:07.276194 Vmddr = 0
7125 22:13:07.281762 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7126 22:13:07.287748 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7127 22:13:07.288306 MEM_TYPE=3, freq_sel=13
7128 22:13:07.291294 sv_algorithm_assistance_LP4_3733
7129 22:13:07.294504 ============ PULL DRAM RESETB DOWN ============
7130 22:13:07.301154 ========== PULL DRAM RESETB DOWN end =========
7131 22:13:07.304203 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7132 22:13:07.307858 ===================================
7133 22:13:07.311122 LPDDR4 DRAM CONFIGURATION
7134 22:13:07.314669 ===================================
7135 22:13:07.315251 EX_ROW_EN[0] = 0x0
7136 22:13:07.317801 EX_ROW_EN[1] = 0x0
7137 22:13:07.318272 LP4Y_EN = 0x0
7138 22:13:07.321331 WORK_FSP = 0x1
7139 22:13:07.324049 WL = 0x5
7140 22:13:07.324542 RL = 0x5
7141 22:13:07.327793 BL = 0x2
7142 22:13:07.328253 RPST = 0x0
7143 22:13:07.331344 RD_PRE = 0x0
7144 22:13:07.332027 WR_PRE = 0x1
7145 22:13:07.334077 WR_PST = 0x1
7146 22:13:07.334548 DBI_WR = 0x0
7147 22:13:07.337987 DBI_RD = 0x0
7148 22:13:07.338549 OTF = 0x1
7149 22:13:07.340729 ===================================
7150 22:13:07.343971 ===================================
7151 22:13:07.347935 ANA top config
7152 22:13:07.351059 ===================================
7153 22:13:07.351658 DLL_ASYNC_EN = 0
7154 22:13:07.353801 ALL_SLAVE_EN = 0
7155 22:13:07.357245 NEW_RANK_MODE = 1
7156 22:13:07.361009 DLL_IDLE_MODE = 1
7157 22:13:07.363834 LP45_APHY_COMB_EN = 1
7158 22:13:07.364400 TX_ODT_DIS = 0
7159 22:13:07.367109 NEW_8X_MODE = 1
7160 22:13:07.370598 ===================================
7161 22:13:07.373378 ===================================
7162 22:13:07.377046 data_rate = 3200
7163 22:13:07.380207 CKR = 1
7164 22:13:07.383502 DQ_P2S_RATIO = 8
7165 22:13:07.386739 ===================================
7166 22:13:07.390160 CA_P2S_RATIO = 8
7167 22:13:07.390730 DQ_CA_OPEN = 0
7168 22:13:07.393446 DQ_SEMI_OPEN = 0
7169 22:13:07.396666 CA_SEMI_OPEN = 0
7170 22:13:07.400113 CA_FULL_RATE = 0
7171 22:13:07.403346 DQ_CKDIV4_EN = 0
7172 22:13:07.407034 CA_CKDIV4_EN = 0
7173 22:13:07.407655 CA_PREDIV_EN = 0
7174 22:13:07.410082 PH8_DLY = 12
7175 22:13:07.413404 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7176 22:13:07.416406 DQ_AAMCK_DIV = 4
7177 22:13:07.419552 CA_AAMCK_DIV = 4
7178 22:13:07.423281 CA_ADMCK_DIV = 4
7179 22:13:07.423980 DQ_TRACK_CA_EN = 0
7180 22:13:07.426591 CA_PICK = 1600
7181 22:13:07.429965 CA_MCKIO = 1600
7182 22:13:07.432923 MCKIO_SEMI = 0
7183 22:13:07.436344 PLL_FREQ = 3068
7184 22:13:07.440145 DQ_UI_PI_RATIO = 32
7185 22:13:07.442953 CA_UI_PI_RATIO = 0
7186 22:13:07.446595 ===================================
7187 22:13:07.449641 ===================================
7188 22:13:07.450230 memory_type:LPDDR4
7189 22:13:07.452798 GP_NUM : 10
7190 22:13:07.456334 SRAM_EN : 1
7191 22:13:07.456911 MD32_EN : 0
7192 22:13:07.459729 ===================================
7193 22:13:07.463159 [ANA_INIT] >>>>>>>>>>>>>>
7194 22:13:07.466165 <<<<<< [CONFIGURE PHASE]: ANA_TX
7195 22:13:07.469241 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7196 22:13:07.472959 ===================================
7197 22:13:07.476025 data_rate = 3200,PCW = 0X7600
7198 22:13:07.479236 ===================================
7199 22:13:07.482937 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7200 22:13:07.485655 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7201 22:13:07.492210 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7202 22:13:07.498854 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7203 22:13:07.502224 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7204 22:13:07.505436 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7205 22:13:07.506015 [ANA_INIT] flow start
7206 22:13:07.508736 [ANA_INIT] PLL >>>>>>>>
7207 22:13:07.512210 [ANA_INIT] PLL <<<<<<<<
7208 22:13:07.512670 [ANA_INIT] MIDPI >>>>>>>>
7209 22:13:07.515301 [ANA_INIT] MIDPI <<<<<<<<
7210 22:13:07.519091 [ANA_INIT] DLL >>>>>>>>
7211 22:13:07.519689 [ANA_INIT] DLL <<<<<<<<
7212 22:13:07.522470 [ANA_INIT] flow end
7213 22:13:07.525043 ============ LP4 DIFF to SE enter ============
7214 22:13:07.528648 ============ LP4 DIFF to SE exit ============
7215 22:13:07.531539 [ANA_INIT] <<<<<<<<<<<<<
7216 22:13:07.534838 [Flow] Enable top DCM control >>>>>
7217 22:13:07.538587 [Flow] Enable top DCM control <<<<<
7218 22:13:07.542057 Enable DLL master slave shuffle
7219 22:13:07.548861 ==============================================================
7220 22:13:07.549437 Gating Mode config
7221 22:13:07.554971 ==============================================================
7222 22:13:07.558440 Config description:
7223 22:13:07.565154 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7224 22:13:07.574501 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7225 22:13:07.577740 SELPH_MODE 0: By rank 1: By Phase
7226 22:13:07.585056 ==============================================================
7227 22:13:07.588026 GAT_TRACK_EN = 1
7228 22:13:07.588602 RX_GATING_MODE = 2
7229 22:13:07.590962 RX_GATING_TRACK_MODE = 2
7230 22:13:07.594586 SELPH_MODE = 1
7231 22:13:07.598032 PICG_EARLY_EN = 1
7232 22:13:07.600747 VALID_LAT_VALUE = 1
7233 22:13:07.607741 ==============================================================
7234 22:13:07.610460 Enter into Gating configuration >>>>
7235 22:13:07.614408 Exit from Gating configuration <<<<
7236 22:13:07.617160 Enter into DVFS_PRE_config >>>>>
7237 22:13:07.627186 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7238 22:13:07.630777 Exit from DVFS_PRE_config <<<<<
7239 22:13:07.634053 Enter into PICG configuration >>>>
7240 22:13:07.637038 Exit from PICG configuration <<<<
7241 22:13:07.640298 [RX_INPUT] configuration >>>>>
7242 22:13:07.643557 [RX_INPUT] configuration <<<<<
7243 22:13:07.646967 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7244 22:13:07.653973 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7245 22:13:07.660469 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7246 22:13:07.666584 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7247 22:13:07.673492 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7248 22:13:07.676391 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7249 22:13:07.683023 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7250 22:13:07.686860 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7251 22:13:07.690120 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7252 22:13:07.693368 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7253 22:13:07.699664 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7254 22:13:07.703070 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7255 22:13:07.706781 ===================================
7256 22:13:07.710295 LPDDR4 DRAM CONFIGURATION
7257 22:13:07.713118 ===================================
7258 22:13:07.713697 EX_ROW_EN[0] = 0x0
7259 22:13:07.716111 EX_ROW_EN[1] = 0x0
7260 22:13:07.716617 LP4Y_EN = 0x0
7261 22:13:07.719462 WORK_FSP = 0x1
7262 22:13:07.719975 WL = 0x5
7263 22:13:07.723228 RL = 0x5
7264 22:13:07.723754 BL = 0x2
7265 22:13:07.726048 RPST = 0x0
7266 22:13:07.729416 RD_PRE = 0x0
7267 22:13:07.729964 WR_PRE = 0x1
7268 22:13:07.733054 WR_PST = 0x1
7269 22:13:07.733528 DBI_WR = 0x0
7270 22:13:07.736247 DBI_RD = 0x0
7271 22:13:07.736720 OTF = 0x1
7272 22:13:07.739081 ===================================
7273 22:13:07.742354 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7274 22:13:07.749680 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7275 22:13:07.752855 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7276 22:13:07.755874 ===================================
7277 22:13:07.759365 LPDDR4 DRAM CONFIGURATION
7278 22:13:07.762627 ===================================
7279 22:13:07.763194 EX_ROW_EN[0] = 0x10
7280 22:13:07.765967 EX_ROW_EN[1] = 0x0
7281 22:13:07.766535 LP4Y_EN = 0x0
7282 22:13:07.768825 WORK_FSP = 0x1
7283 22:13:07.769296 WL = 0x5
7284 22:13:07.772506 RL = 0x5
7285 22:13:07.776321 BL = 0x2
7286 22:13:07.776889 RPST = 0x0
7287 22:13:07.779173 RD_PRE = 0x0
7288 22:13:07.779782 WR_PRE = 0x1
7289 22:13:07.782380 WR_PST = 0x1
7290 22:13:07.782947 DBI_WR = 0x0
7291 22:13:07.785754 DBI_RD = 0x0
7292 22:13:07.786220 OTF = 0x1
7293 22:13:07.788690 ===================================
7294 22:13:07.795709 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7295 22:13:07.796277 ==
7296 22:13:07.798764 Dram Type= 6, Freq= 0, CH_0, rank 0
7297 22:13:07.801984 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7298 22:13:07.802637 ==
7299 22:13:07.805445 [Duty_Offset_Calibration]
7300 22:13:07.808509 B0:2 B1:0 CA:3
7301 22:13:07.809036
7302 22:13:07.811635 [DutyScan_Calibration_Flow] k_type=0
7303 22:13:07.820353
7304 22:13:07.820921 ==CLK 0==
7305 22:13:07.823702 Final CLK duty delay cell = 0
7306 22:13:07.827152 [0] MAX Duty = 5031%(X100), DQS PI = 12
7307 22:13:07.830334 [0] MIN Duty = 4875%(X100), DQS PI = 54
7308 22:13:07.833787 [0] AVG Duty = 4953%(X100)
7309 22:13:07.834351
7310 22:13:07.836731 CH0 CLK Duty spec in!! Max-Min= 156%
7311 22:13:07.840243 [DutyScan_Calibration_Flow] ====Done====
7312 22:13:07.840714
7313 22:13:07.844057 [DutyScan_Calibration_Flow] k_type=1
7314 22:13:07.860898
7315 22:13:07.861470 ==DQS 0 ==
7316 22:13:07.864141 Final DQS duty delay cell = 0
7317 22:13:07.867072 [0] MAX Duty = 5094%(X100), DQS PI = 14
7318 22:13:07.870715 [0] MIN Duty = 4906%(X100), DQS PI = 52
7319 22:13:07.873873 [0] AVG Duty = 5000%(X100)
7320 22:13:07.874365
7321 22:13:07.874745 ==DQS 1 ==
7322 22:13:07.876930 Final DQS duty delay cell = 0
7323 22:13:07.880199 [0] MAX Duty = 5156%(X100), DQS PI = 32
7324 22:13:07.884149 [0] MIN Duty = 5031%(X100), DQS PI = 14
7325 22:13:07.887126 [0] AVG Duty = 5093%(X100)
7326 22:13:07.887744
7327 22:13:07.890640 CH0 DQS 0 Duty spec in!! Max-Min= 188%
7328 22:13:07.891218
7329 22:13:07.893856 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7330 22:13:07.897032 [DutyScan_Calibration_Flow] ====Done====
7331 22:13:07.897507
7332 22:13:07.900224 [DutyScan_Calibration_Flow] k_type=3
7333 22:13:07.917665
7334 22:13:07.918245 ==DQM 0 ==
7335 22:13:07.921374 Final DQM duty delay cell = 0
7336 22:13:07.924104 [0] MAX Duty = 5156%(X100), DQS PI = 30
7337 22:13:07.927527 [0] MIN Duty = 4844%(X100), DQS PI = 50
7338 22:13:07.930922 [0] AVG Duty = 5000%(X100)
7339 22:13:07.931494
7340 22:13:07.931938 ==DQM 1 ==
7341 22:13:07.934036 Final DQM duty delay cell = 0
7342 22:13:07.937505 [0] MAX Duty = 4969%(X100), DQS PI = 0
7343 22:13:07.941279 [0] MIN Duty = 4813%(X100), DQS PI = 14
7344 22:13:07.944039 [0] AVG Duty = 4891%(X100)
7345 22:13:07.944618
7346 22:13:07.947646 CH0 DQM 0 Duty spec in!! Max-Min= 312%
7347 22:13:07.948111
7348 22:13:07.950458 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7349 22:13:07.953969 [DutyScan_Calibration_Flow] ====Done====
7350 22:13:07.954430
7351 22:13:07.957055 [DutyScan_Calibration_Flow] k_type=2
7352 22:13:07.973961
7353 22:13:07.974461 ==DQ 0 ==
7354 22:13:07.977429 Final DQ duty delay cell = -4
7355 22:13:07.980724 [-4] MAX Duty = 5000%(X100), DQS PI = 14
7356 22:13:07.984001 [-4] MIN Duty = 4876%(X100), DQS PI = 0
7357 22:13:07.987534 [-4] AVG Duty = 4938%(X100)
7358 22:13:07.988024
7359 22:13:07.988391 ==DQ 1 ==
7360 22:13:07.990738 Final DQ duty delay cell = 0
7361 22:13:07.993609 [0] MAX Duty = 5156%(X100), DQS PI = 60
7362 22:13:07.997049 [0] MIN Duty = 5000%(X100), DQS PI = 16
7363 22:13:08.000817 [0] AVG Duty = 5078%(X100)
7364 22:13:08.001382
7365 22:13:08.003773 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7366 22:13:08.004392
7367 22:13:08.007121 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7368 22:13:08.010370 [DutyScan_Calibration_Flow] ====Done====
7369 22:13:08.010926 ==
7370 22:13:08.014089 Dram Type= 6, Freq= 0, CH_1, rank 0
7371 22:13:08.017075 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7372 22:13:08.017541 ==
7373 22:13:08.020128 [Duty_Offset_Calibration]
7374 22:13:08.020587 B0:1 B1:-2 CA:1
7375 22:13:08.020955
7376 22:13:08.023112 [DutyScan_Calibration_Flow] k_type=0
7377 22:13:08.034714
7378 22:13:08.035262 ==CLK 0==
7379 22:13:08.038337 Final CLK duty delay cell = 0
7380 22:13:08.041522 [0] MAX Duty = 5031%(X100), DQS PI = 50
7381 22:13:08.044457 [0] MIN Duty = 4875%(X100), DQS PI = 26
7382 22:13:08.047646 [0] AVG Duty = 4953%(X100)
7383 22:13:08.048122
7384 22:13:08.051091 CH1 CLK Duty spec in!! Max-Min= 156%
7385 22:13:08.054216 [DutyScan_Calibration_Flow] ====Done====
7386 22:13:08.054675
7387 22:13:08.057814 [DutyScan_Calibration_Flow] k_type=1
7388 22:13:08.073794
7389 22:13:08.074376 ==DQS 0 ==
7390 22:13:08.076727 Final DQS duty delay cell = -4
7391 22:13:08.080306 [-4] MAX Duty = 4969%(X100), DQS PI = 58
7392 22:13:08.083935 [-4] MIN Duty = 4844%(X100), DQS PI = 12
7393 22:13:08.086449 [-4] AVG Duty = 4906%(X100)
7394 22:13:08.086914
7395 22:13:08.087280 ==DQS 1 ==
7396 22:13:08.090626 Final DQS duty delay cell = 0
7397 22:13:08.093568 [0] MAX Duty = 5124%(X100), DQS PI = 30
7398 22:13:08.096583 [0] MIN Duty = 4813%(X100), DQS PI = 58
7399 22:13:08.099882 [0] AVG Duty = 4968%(X100)
7400 22:13:08.100436
7401 22:13:08.103330 CH1 DQS 0 Duty spec in!! Max-Min= 125%
7402 22:13:08.104116
7403 22:13:08.106906 CH1 DQS 1 Duty spec in!! Max-Min= 311%
7404 22:13:08.110036 [DutyScan_Calibration_Flow] ====Done====
7405 22:13:08.110591
7406 22:13:08.113085 [DutyScan_Calibration_Flow] k_type=3
7407 22:13:08.130814
7408 22:13:08.131427 ==DQM 0 ==
7409 22:13:08.134267 Final DQM duty delay cell = 0
7410 22:13:08.137637 [0] MAX Duty = 5000%(X100), DQS PI = 0
7411 22:13:08.140999 [0] MIN Duty = 4844%(X100), DQS PI = 20
7412 22:13:08.143998 [0] AVG Duty = 4922%(X100)
7413 22:13:08.144553
7414 22:13:08.144920 ==DQM 1 ==
7415 22:13:08.147755 Final DQM duty delay cell = 0
7416 22:13:08.151122 [0] MAX Duty = 5062%(X100), DQS PI = 4
7417 22:13:08.153898 [0] MIN Duty = 4875%(X100), DQS PI = 36
7418 22:13:08.156929 [0] AVG Duty = 4968%(X100)
7419 22:13:08.157394
7420 22:13:08.160311 CH1 DQM 0 Duty spec in!! Max-Min= 156%
7421 22:13:08.160775
7422 22:13:08.163816 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7423 22:13:08.167229 [DutyScan_Calibration_Flow] ====Done====
7424 22:13:08.167816
7425 22:13:08.170693 [DutyScan_Calibration_Flow] k_type=2
7426 22:13:08.187968
7427 22:13:08.188521 ==DQ 0 ==
7428 22:13:08.191411 Final DQ duty delay cell = 0
7429 22:13:08.194489 [0] MAX Duty = 5093%(X100), DQS PI = 62
7430 22:13:08.197481 [0] MIN Duty = 4938%(X100), DQS PI = 24
7431 22:13:08.201153 [0] AVG Duty = 5015%(X100)
7432 22:13:08.201730
7433 22:13:08.202104 ==DQ 1 ==
7434 22:13:08.203853 Final DQ duty delay cell = 0
7435 22:13:08.207319 [0] MAX Duty = 5156%(X100), DQS PI = 26
7436 22:13:08.211260 [0] MIN Duty = 4938%(X100), DQS PI = 56
7437 22:13:08.211890 [0] AVG Duty = 5047%(X100)
7438 22:13:08.214147
7439 22:13:08.217719 CH1 DQ 0 Duty spec in!! Max-Min= 155%
7440 22:13:08.218273
7441 22:13:08.220464 CH1 DQ 1 Duty spec in!! Max-Min= 218%
7442 22:13:08.224208 [DutyScan_Calibration_Flow] ====Done====
7443 22:13:08.226917 nWR fixed to 30
7444 22:13:08.230750 [ModeRegInit_LP4] CH0 RK0
7445 22:13:08.231359 [ModeRegInit_LP4] CH0 RK1
7446 22:13:08.233755 [ModeRegInit_LP4] CH1 RK0
7447 22:13:08.237227 [ModeRegInit_LP4] CH1 RK1
7448 22:13:08.237690 match AC timing 5
7449 22:13:08.243777 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7450 22:13:08.247450 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7451 22:13:08.250526 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7452 22:13:08.257069 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7453 22:13:08.260474 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7454 22:13:08.261027 [MiockJmeterHQA]
7455 22:13:08.261398
7456 22:13:08.263516 [DramcMiockJmeter] u1RxGatingPI = 0
7457 22:13:08.266823 0 : 4368, 4140
7458 22:13:08.267292 4 : 4253, 4026
7459 22:13:08.269960 8 : 4255, 4029
7460 22:13:08.270451 12 : 4368, 4140
7461 22:13:08.273329 16 : 4252, 4027
7462 22:13:08.273821 20 : 4253, 4027
7463 22:13:08.274204 24 : 4252, 4027
7464 22:13:08.276502 28 : 4255, 4029
7465 22:13:08.276978 32 : 4253, 4027
7466 22:13:08.279936 36 : 4252, 4027
7467 22:13:08.280409 40 : 4365, 4140
7468 22:13:08.283570 44 : 4253, 4027
7469 22:13:08.284171 48 : 4255, 4029
7470 22:13:08.286668 52 : 4252, 4027
7471 22:13:08.287276 56 : 4361, 4138
7472 22:13:08.287724 60 : 4253, 4029
7473 22:13:08.290101 64 : 4361, 4137
7474 22:13:08.290684 68 : 4250, 4027
7475 22:13:08.293105 72 : 4250, 4027
7476 22:13:08.293598 76 : 4250, 4026
7477 22:13:08.296417 80 : 4252, 4029
7478 22:13:08.297042 84 : 4250, 4027
7479 22:13:08.299750 88 : 4253, 4030
7480 22:13:08.300236 92 : 4363, 4140
7481 22:13:08.300646 96 : 4250, 4027
7482 22:13:08.302708 100 : 4252, 4029
7483 22:13:08.303178 104 : 4360, 3869
7484 22:13:08.306144 108 : 4250, 8
7485 22:13:08.306699 112 : 4250, 0
7486 22:13:08.309409 116 : 4361, 0
7487 22:13:08.309823 120 : 4250, 0
7488 22:13:08.310198 124 : 4250, 0
7489 22:13:08.312623 128 : 4252, 0
7490 22:13:08.313194 132 : 4363, 0
7491 22:13:08.316094 136 : 4360, 0
7492 22:13:08.316567 140 : 4250, 0
7493 22:13:08.316946 144 : 4250, 0
7494 22:13:08.319416 148 : 4250, 0
7495 22:13:08.320035 152 : 4250, 0
7496 22:13:08.322953 156 : 4361, 0
7497 22:13:08.323529 160 : 4250, 0
7498 22:13:08.323969 164 : 4250, 0
7499 22:13:08.325616 168 : 4250, 0
7500 22:13:08.326083 172 : 4250, 0
7501 22:13:08.329295 176 : 4250, 0
7502 22:13:08.329868 180 : 4250, 0
7503 22:13:08.330253 184 : 4252, 0
7504 22:13:08.332289 188 : 4360, 0
7505 22:13:08.332760 192 : 4361, 0
7506 22:13:08.333159 196 : 4250, 0
7507 22:13:08.335839 200 : 4250, 0
7508 22:13:08.336396 204 : 4250, 0
7509 22:13:08.339105 208 : 4361, 0
7510 22:13:08.339740 212 : 4250, 0
7511 22:13:08.340134 216 : 4250, 0
7512 22:13:08.342816 220 : 4250, 0
7513 22:13:08.343388 224 : 4250, 0
7514 22:13:08.345632 228 : 4250, 0
7515 22:13:08.346219 232 : 4250, 0
7516 22:13:08.348701 236 : 4361, 1032
7517 22:13:08.349171 240 : 4250, 4027
7518 22:13:08.349549 244 : 4250, 4027
7519 22:13:08.352539 248 : 4250, 4027
7520 22:13:08.353096 252 : 4361, 4137
7521 22:13:08.355797 256 : 4361, 4138
7522 22:13:08.356364 260 : 4250, 4027
7523 22:13:08.358493 264 : 4360, 4138
7524 22:13:08.358965 268 : 4250, 4027
7525 22:13:08.361988 272 : 4250, 4027
7526 22:13:08.362562 276 : 4250, 4027
7527 22:13:08.365709 280 : 4252, 4029
7528 22:13:08.366281 284 : 4250, 4027
7529 22:13:08.368813 288 : 4250, 4027
7530 22:13:08.369384 292 : 4250, 4027
7531 22:13:08.372158 296 : 4252, 4029
7532 22:13:08.372732 300 : 4250, 4027
7533 22:13:08.375028 304 : 4360, 4138
7534 22:13:08.375497 308 : 4361, 4138
7535 22:13:08.375930 312 : 4250, 4027
7536 22:13:08.378216 316 : 4363, 4140
7537 22:13:08.378686 320 : 4361, 4138
7538 22:13:08.381864 324 : 4250, 4027
7539 22:13:08.382439 328 : 4250, 4027
7540 22:13:08.384748 332 : 4252, 4029
7541 22:13:08.385221 336 : 4250, 4027
7542 22:13:08.388375 340 : 4250, 4027
7543 22:13:08.388945 344 : 4250, 4027
7544 22:13:08.391747 348 : 4252, 4029
7545 22:13:08.392237 352 : 4250, 4023
7546 22:13:08.395013 356 : 4361, 2805
7547 22:13:08.395736 360 : 4361, 3
7548 22:13:08.396136
7549 22:13:08.398027 MIOCK jitter meter ch=0
7550 22:13:08.398488
7551 22:13:08.402230 1T = (360-108) = 252 dly cells
7552 22:13:08.404709 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7553 22:13:08.405186 ==
7554 22:13:08.408006 Dram Type= 6, Freq= 0, CH_0, rank 0
7555 22:13:08.414892 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7556 22:13:08.415471 ==
7557 22:13:08.418152 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7558 22:13:08.424489 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7559 22:13:08.427699 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7560 22:13:08.434627 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7561 22:13:08.443056 [CA 0] Center 43 (13~74) winsize 62
7562 22:13:08.445915 [CA 1] Center 43 (13~74) winsize 62
7563 22:13:08.448827 [CA 2] Center 39 (10~68) winsize 59
7564 22:13:08.452178 [CA 3] Center 39 (10~68) winsize 59
7565 22:13:08.456236 [CA 4] Center 36 (7~66) winsize 60
7566 22:13:08.459057 [CA 5] Center 36 (7~66) winsize 60
7567 22:13:08.459634
7568 22:13:08.462126 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7569 22:13:08.465646
7570 22:13:08.469188 [CATrainingPosCal] consider 1 rank data
7571 22:13:08.469657 u2DelayCellTimex100 = 258/100 ps
7572 22:13:08.475169 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7573 22:13:08.478694 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7574 22:13:08.482408 CA2 delay=39 (10~68),Diff = 3 PI (11 cell)
7575 22:13:08.485471 CA3 delay=39 (10~68),Diff = 3 PI (11 cell)
7576 22:13:08.489257 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7577 22:13:08.491893 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7578 22:13:08.492366
7579 22:13:08.495058 CA PerBit enable=1, Macro0, CA PI delay=36
7580 22:13:08.498334
7581 22:13:08.498806 [CBTSetCACLKResult] CA Dly = 36
7582 22:13:08.502001 CS Dly: 11 (0~42)
7583 22:13:08.505054 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7584 22:13:08.508302 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7585 22:13:08.511473 ==
7586 22:13:08.515628 Dram Type= 6, Freq= 0, CH_0, rank 1
7587 22:13:08.518359 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7588 22:13:08.518952 ==
7589 22:13:08.521732 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7590 22:13:08.528553 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7591 22:13:08.531369 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7592 22:13:08.538527 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7593 22:13:08.546808 [CA 0] Center 44 (13~75) winsize 63
7594 22:13:08.549872 [CA 1] Center 43 (13~74) winsize 62
7595 22:13:08.553363 [CA 2] Center 39 (10~69) winsize 60
7596 22:13:08.556892 [CA 3] Center 39 (10~68) winsize 59
7597 22:13:08.559800 [CA 4] Center 37 (8~67) winsize 60
7598 22:13:08.563046 [CA 5] Center 36 (7~66) winsize 60
7599 22:13:08.563652
7600 22:13:08.566759 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7601 22:13:08.567332
7602 22:13:08.572934 [CATrainingPosCal] consider 2 rank data
7603 22:13:08.573493 u2DelayCellTimex100 = 258/100 ps
7604 22:13:08.579799 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7605 22:13:08.582872 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7606 22:13:08.585991 CA2 delay=39 (10~68),Diff = 3 PI (11 cell)
7607 22:13:08.589681 CA3 delay=39 (10~68),Diff = 3 PI (11 cell)
7608 22:13:08.592295 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
7609 22:13:08.596264 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7610 22:13:08.596938
7611 22:13:08.602725 CA PerBit enable=1, Macro0, CA PI delay=36
7612 22:13:08.603309
7613 22:13:08.603745 [CBTSetCACLKResult] CA Dly = 36
7614 22:13:08.605467 CS Dly: 11 (0~43)
7615 22:13:08.609248 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7616 22:13:08.612035 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7617 22:13:08.615321
7618 22:13:08.618688 ----->DramcWriteLeveling(PI) begin...
7619 22:13:08.619254 ==
7620 22:13:08.621917 Dram Type= 6, Freq= 0, CH_0, rank 0
7621 22:13:08.625159 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7622 22:13:08.625763 ==
7623 22:13:08.628682 Write leveling (Byte 0): 36 => 36
7624 22:13:08.631686 Write leveling (Byte 1): 29 => 29
7625 22:13:08.635118 DramcWriteLeveling(PI) end<-----
7626 22:13:08.635613
7627 22:13:08.636004 ==
7628 22:13:08.638623 Dram Type= 6, Freq= 0, CH_0, rank 0
7629 22:13:08.641763 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7630 22:13:08.642331 ==
7631 22:13:08.645011 [Gating] SW mode calibration
7632 22:13:08.651945 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7633 22:13:08.658356 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7634 22:13:08.661886 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7635 22:13:08.664912 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7636 22:13:08.671663 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7637 22:13:08.674835 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7638 22:13:08.677932 1 4 16 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
7639 22:13:08.684465 1 4 20 | B1->B0 | 2626 3434 | 1 1 | (0 0) (1 1)
7640 22:13:08.687999 1 4 24 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
7641 22:13:08.691194 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7642 22:13:08.697479 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7643 22:13:08.700984 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7644 22:13:08.704130 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7645 22:13:08.711053 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7646 22:13:08.714148 1 5 16 | B1->B0 | 3434 2d2d | 1 0 | (1 1) (0 1)
7647 22:13:08.717336 1 5 20 | B1->B0 | 3434 2323 | 0 0 | (0 0) (1 0)
7648 22:13:08.723668 1 5 24 | B1->B0 | 2929 2323 | 0 0 | (1 0) (0 0)
7649 22:13:08.727257 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7650 22:13:08.730434 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7651 22:13:08.737110 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7652 22:13:08.740525 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7653 22:13:08.743683 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7654 22:13:08.749996 1 6 16 | B1->B0 | 2323 4141 | 0 1 | (0 0) (0 0)
7655 22:13:08.753592 1 6 20 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)
7656 22:13:08.760150 1 6 24 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
7657 22:13:08.763346 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7658 22:13:08.766605 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7659 22:13:08.773107 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7660 22:13:08.776854 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7661 22:13:08.779786 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7662 22:13:08.786169 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7663 22:13:08.789831 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7664 22:13:08.792850 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7665 22:13:08.800027 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7666 22:13:08.803051 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7667 22:13:08.805859 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7668 22:13:08.812972 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7669 22:13:08.816119 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7670 22:13:08.819308 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7671 22:13:08.825761 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7672 22:13:08.829081 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7673 22:13:08.832641 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7674 22:13:08.839127 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7675 22:13:08.842305 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7676 22:13:08.845678 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7677 22:13:08.852285 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7678 22:13:08.855662 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7679 22:13:08.858661 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7680 22:13:08.865584 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7681 22:13:08.866053 Total UI for P1: 0, mck2ui 16
7682 22:13:08.872162 best dqsien dly found for B0: ( 1, 9, 18)
7683 22:13:08.872589 Total UI for P1: 0, mck2ui 16
7684 22:13:08.874985 best dqsien dly found for B1: ( 1, 9, 22)
7685 22:13:08.881983 best DQS0 dly(MCK, UI, PI) = (1, 9, 18)
7686 22:13:08.884708 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7687 22:13:08.885133
7688 22:13:08.888540 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 18)
7689 22:13:08.891550 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7690 22:13:08.894786 [Gating] SW calibration Done
7691 22:13:08.895206 ==
7692 22:13:08.898259 Dram Type= 6, Freq= 0, CH_0, rank 0
7693 22:13:08.901625 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7694 22:13:08.902050 ==
7695 22:13:08.904822 RX Vref Scan: 0
7696 22:13:08.905361
7697 22:13:08.905704 RX Vref 0 -> 0, step: 1
7698 22:13:08.906020
7699 22:13:08.908117 RX Delay 0 -> 252, step: 8
7700 22:13:08.911265 iDelay=192, Bit 0, Center 127 (72 ~ 183) 112
7701 22:13:08.917858 iDelay=192, Bit 1, Center 131 (80 ~ 183) 104
7702 22:13:08.921132 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7703 22:13:08.924628 iDelay=192, Bit 3, Center 127 (72 ~ 183) 112
7704 22:13:08.928097 iDelay=192, Bit 4, Center 127 (72 ~ 183) 112
7705 22:13:08.930903 iDelay=192, Bit 5, Center 111 (56 ~ 167) 112
7706 22:13:08.937662 iDelay=192, Bit 6, Center 135 (80 ~ 191) 112
7707 22:13:08.940933 iDelay=192, Bit 7, Center 135 (80 ~ 191) 112
7708 22:13:08.944408 iDelay=192, Bit 8, Center 115 (56 ~ 175) 120
7709 22:13:08.947990 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7710 22:13:08.951017 iDelay=192, Bit 10, Center 123 (64 ~ 183) 120
7711 22:13:08.957519 iDelay=192, Bit 11, Center 115 (56 ~ 175) 120
7712 22:13:08.960709 iDelay=192, Bit 12, Center 127 (72 ~ 183) 112
7713 22:13:08.963971 iDelay=192, Bit 13, Center 127 (72 ~ 183) 112
7714 22:13:08.967705 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7715 22:13:08.974299 iDelay=192, Bit 15, Center 131 (72 ~ 191) 120
7716 22:13:08.974841 ==
7717 22:13:08.977136 Dram Type= 6, Freq= 0, CH_0, rank 0
7718 22:13:08.980850 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7719 22:13:08.981277 ==
7720 22:13:08.981613 DQS Delay:
7721 22:13:08.983962 DQS0 = 0, DQS1 = 0
7722 22:13:08.984380 DQM Delay:
7723 22:13:08.987563 DQM0 = 127, DQM1 = 123
7724 22:13:08.988168 DQ Delay:
7725 22:13:08.990279 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =127
7726 22:13:08.993913 DQ4 =127, DQ5 =111, DQ6 =135, DQ7 =135
7727 22:13:08.996661 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =115
7728 22:13:09.000554 DQ12 =127, DQ13 =127, DQ14 =135, DQ15 =131
7729 22:13:09.003436
7730 22:13:09.003891
7731 22:13:09.004251 ==
7732 22:13:09.007168 Dram Type= 6, Freq= 0, CH_0, rank 0
7733 22:13:09.010333 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7734 22:13:09.010755 ==
7735 22:13:09.011314
7736 22:13:09.011813
7737 22:13:09.013187 TX Vref Scan disable
7738 22:13:09.013733 == TX Byte 0 ==
7739 22:13:09.020257 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
7740 22:13:09.023364 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7741 22:13:09.023880 == TX Byte 1 ==
7742 22:13:09.029744 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7743 22:13:09.033046 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7744 22:13:09.033528 ==
7745 22:13:09.036458 Dram Type= 6, Freq= 0, CH_0, rank 0
7746 22:13:09.039628 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7747 22:13:09.040053 ==
7748 22:13:09.054356
7749 22:13:09.057677 TX Vref early break, caculate TX vref
7750 22:13:09.060856 TX Vref=16, minBit 8, minWin=21, winSum=360
7751 22:13:09.064202 TX Vref=18, minBit 8, minWin=22, winSum=373
7752 22:13:09.067536 TX Vref=20, minBit 8, minWin=23, winSum=388
7753 22:13:09.070840 TX Vref=22, minBit 13, minWin=23, winSum=394
7754 22:13:09.074576 TX Vref=24, minBit 4, minWin=24, winSum=402
7755 22:13:09.080846 TX Vref=26, minBit 4, minWin=25, winSum=413
7756 22:13:09.083968 TX Vref=28, minBit 4, minWin=25, winSum=415
7757 22:13:09.087850 TX Vref=30, minBit 4, minWin=24, winSum=402
7758 22:13:09.090824 TX Vref=32, minBit 8, minWin=24, winSum=397
7759 22:13:09.093978 TX Vref=34, minBit 8, minWin=23, winSum=389
7760 22:13:09.100595 [TxChooseVref] Worse bit 4, Min win 25, Win sum 415, Final Vref 28
7761 22:13:09.101079
7762 22:13:09.104321 Final TX Range 0 Vref 28
7763 22:13:09.104752
7764 22:13:09.105094 ==
7765 22:13:09.107277 Dram Type= 6, Freq= 0, CH_0, rank 0
7766 22:13:09.110266 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7767 22:13:09.110872 ==
7768 22:13:09.111313
7769 22:13:09.111686
7770 22:13:09.113457 TX Vref Scan disable
7771 22:13:09.120721 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7772 22:13:09.121407 == TX Byte 0 ==
7773 22:13:09.123755 u2DelayCellOfst[0]=15 cells (4 PI)
7774 22:13:09.126923 u2DelayCellOfst[1]=18 cells (5 PI)
7775 22:13:09.130242 u2DelayCellOfst[2]=11 cells (3 PI)
7776 22:13:09.133298 u2DelayCellOfst[3]=15 cells (4 PI)
7777 22:13:09.136837 u2DelayCellOfst[4]=7 cells (2 PI)
7778 22:13:09.140369 u2DelayCellOfst[5]=0 cells (0 PI)
7779 22:13:09.143543 u2DelayCellOfst[6]=22 cells (6 PI)
7780 22:13:09.147057 u2DelayCellOfst[7]=18 cells (5 PI)
7781 22:13:09.150168 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7782 22:13:09.154013 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7783 22:13:09.156779 == TX Byte 1 ==
7784 22:13:09.160223 u2DelayCellOfst[8]=0 cells (0 PI)
7785 22:13:09.163833 u2DelayCellOfst[9]=3 cells (1 PI)
7786 22:13:09.164365 u2DelayCellOfst[10]=7 cells (2 PI)
7787 22:13:09.167045 u2DelayCellOfst[11]=3 cells (1 PI)
7788 22:13:09.170229 u2DelayCellOfst[12]=15 cells (4 PI)
7789 22:13:09.173371 u2DelayCellOfst[13]=11 cells (3 PI)
7790 22:13:09.176609 u2DelayCellOfst[14]=15 cells (4 PI)
7791 22:13:09.179978 u2DelayCellOfst[15]=11 cells (3 PI)
7792 22:13:09.186573 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7793 22:13:09.190241 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7794 22:13:09.190767 DramC Write-DBI on
7795 22:13:09.191114 ==
7796 22:13:09.193115 Dram Type= 6, Freq= 0, CH_0, rank 0
7797 22:13:09.199323 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7798 22:13:09.199939 ==
7799 22:13:09.200381
7800 22:13:09.200730
7801 22:13:09.202982 TX Vref Scan disable
7802 22:13:09.203431 == TX Byte 0 ==
7803 22:13:09.209057 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
7804 22:13:09.209505 == TX Byte 1 ==
7805 22:13:09.212732 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
7806 22:13:09.216255 DramC Write-DBI off
7807 22:13:09.216682
7808 22:13:09.217024 [DATLAT]
7809 22:13:09.219393 Freq=1600, CH0 RK0
7810 22:13:09.219854
7811 22:13:09.220199 DATLAT Default: 0xf
7812 22:13:09.222506 0, 0xFFFF, sum = 0
7813 22:13:09.222938 1, 0xFFFF, sum = 0
7814 22:13:09.225941 2, 0xFFFF, sum = 0
7815 22:13:09.226377 3, 0xFFFF, sum = 0
7816 22:13:09.229094 4, 0xFFFF, sum = 0
7817 22:13:09.229527 5, 0xFFFF, sum = 0
7818 22:13:09.232594 6, 0xFFFF, sum = 0
7819 22:13:09.233069 7, 0xFFFF, sum = 0
7820 22:13:09.235825 8, 0xFFFF, sum = 0
7821 22:13:09.239083 9, 0xFFFF, sum = 0
7822 22:13:09.239512 10, 0xFFFF, sum = 0
7823 22:13:09.242164 11, 0xFFFF, sum = 0
7824 22:13:09.242695 12, 0xFFFF, sum = 0
7825 22:13:09.245792 13, 0xCFFF, sum = 0
7826 22:13:09.246316 14, 0x0, sum = 1
7827 22:13:09.248951 15, 0x0, sum = 2
7828 22:13:09.249433 16, 0x0, sum = 3
7829 22:13:09.252208 17, 0x0, sum = 4
7830 22:13:09.252748 best_step = 15
7831 22:13:09.253089
7832 22:13:09.253460 ==
7833 22:13:09.255651 Dram Type= 6, Freq= 0, CH_0, rank 0
7834 22:13:09.259205 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7835 22:13:09.261989 ==
7836 22:13:09.262610 RX Vref Scan: 1
7837 22:13:09.262959
7838 22:13:09.265164 Set Vref Range= 24 -> 127
7839 22:13:09.265708
7840 22:13:09.268819 RX Vref 24 -> 127, step: 1
7841 22:13:09.269461
7842 22:13:09.269815 RX Delay 11 -> 252, step: 4
7843 22:13:09.270246
7844 22:13:09.271958 Set Vref, RX VrefLevel [Byte0]: 24
7845 22:13:09.275030 [Byte1]: 24
7846 22:13:09.279645
7847 22:13:09.280253 Set Vref, RX VrefLevel [Byte0]: 25
7848 22:13:09.282415 [Byte1]: 25
7849 22:13:09.286828
7850 22:13:09.287371 Set Vref, RX VrefLevel [Byte0]: 26
7851 22:13:09.289837 [Byte1]: 26
7852 22:13:09.294459
7853 22:13:09.294876 Set Vref, RX VrefLevel [Byte0]: 27
7854 22:13:09.297875 [Byte1]: 27
7855 22:13:09.301961
7856 22:13:09.302384 Set Vref, RX VrefLevel [Byte0]: 28
7857 22:13:09.305062 [Byte1]: 28
7858 22:13:09.309790
7859 22:13:09.310424 Set Vref, RX VrefLevel [Byte0]: 29
7860 22:13:09.312983 [Byte1]: 29
7861 22:13:09.317419
7862 22:13:09.317838 Set Vref, RX VrefLevel [Byte0]: 30
7863 22:13:09.320395 [Byte1]: 30
7864 22:13:09.324692
7865 22:13:09.325110 Set Vref, RX VrefLevel [Byte0]: 31
7866 22:13:09.327736 [Byte1]: 31
7867 22:13:09.332519
7868 22:13:09.332940 Set Vref, RX VrefLevel [Byte0]: 32
7869 22:13:09.335564 [Byte1]: 32
7870 22:13:09.340161
7871 22:13:09.340591 Set Vref, RX VrefLevel [Byte0]: 33
7872 22:13:09.343316 [Byte1]: 33
7873 22:13:09.347535
7874 22:13:09.348016 Set Vref, RX VrefLevel [Byte0]: 34
7875 22:13:09.350761 [Byte1]: 34
7876 22:13:09.355509
7877 22:13:09.355858 Set Vref, RX VrefLevel [Byte0]: 35
7878 22:13:09.358215 [Byte1]: 35
7879 22:13:09.362594
7880 22:13:09.362833 Set Vref, RX VrefLevel [Byte0]: 36
7881 22:13:09.369358 [Byte1]: 36
7882 22:13:09.369549
7883 22:13:09.372148 Set Vref, RX VrefLevel [Byte0]: 37
7884 22:13:09.375354 [Byte1]: 37
7885 22:13:09.375538
7886 22:13:09.378981 Set Vref, RX VrefLevel [Byte0]: 38
7887 22:13:09.382145 [Byte1]: 38
7888 22:13:09.385853
7889 22:13:09.386034 Set Vref, RX VrefLevel [Byte0]: 39
7890 22:13:09.388989 [Byte1]: 39
7891 22:13:09.393331
7892 22:13:09.393566 Set Vref, RX VrefLevel [Byte0]: 40
7893 22:13:09.396138 [Byte1]: 40
7894 22:13:09.400716
7895 22:13:09.400907 Set Vref, RX VrefLevel [Byte0]: 41
7896 22:13:09.403949 [Byte1]: 41
7897 22:13:09.408193
7898 22:13:09.408692 Set Vref, RX VrefLevel [Byte0]: 42
7899 22:13:09.411779 [Byte1]: 42
7900 22:13:09.416099
7901 22:13:09.416523 Set Vref, RX VrefLevel [Byte0]: 43
7902 22:13:09.419505 [Byte1]: 43
7903 22:13:09.423915
7904 22:13:09.424388 Set Vref, RX VrefLevel [Byte0]: 44
7905 22:13:09.427304 [Byte1]: 44
7906 22:13:09.431603
7907 22:13:09.432198 Set Vref, RX VrefLevel [Byte0]: 45
7908 22:13:09.434719 [Byte1]: 45
7909 22:13:09.438829
7910 22:13:09.439321 Set Vref, RX VrefLevel [Byte0]: 46
7911 22:13:09.442424 [Byte1]: 46
7912 22:13:09.446701
7913 22:13:09.447121 Set Vref, RX VrefLevel [Byte0]: 47
7914 22:13:09.449824 [Byte1]: 47
7915 22:13:09.454061
7916 22:13:09.454480 Set Vref, RX VrefLevel [Byte0]: 48
7917 22:13:09.457367 [Byte1]: 48
7918 22:13:09.461782
7919 22:13:09.462199 Set Vref, RX VrefLevel [Byte0]: 49
7920 22:13:09.468261 [Byte1]: 49
7921 22:13:09.468682
7922 22:13:09.471492 Set Vref, RX VrefLevel [Byte0]: 50
7923 22:13:09.474692 [Byte1]: 50
7924 22:13:09.475130
7925 22:13:09.477973 Set Vref, RX VrefLevel [Byte0]: 51
7926 22:13:09.481773 [Byte1]: 51
7927 22:13:09.484678
7928 22:13:09.485093 Set Vref, RX VrefLevel [Byte0]: 52
7929 22:13:09.488050 [Byte1]: 52
7930 22:13:09.492045
7931 22:13:09.492467 Set Vref, RX VrefLevel [Byte0]: 53
7932 22:13:09.495640 [Byte1]: 53
7933 22:13:09.499859
7934 22:13:09.500444 Set Vref, RX VrefLevel [Byte0]: 54
7935 22:13:09.503002 [Byte1]: 54
7936 22:13:09.507673
7937 22:13:09.508107 Set Vref, RX VrefLevel [Byte0]: 55
7938 22:13:09.510469 [Byte1]: 55
7939 22:13:09.515366
7940 22:13:09.515883 Set Vref, RX VrefLevel [Byte0]: 56
7941 22:13:09.518345 [Byte1]: 56
7942 22:13:09.522607
7943 22:13:09.523002 Set Vref, RX VrefLevel [Byte0]: 57
7944 22:13:09.526235 [Byte1]: 57
7945 22:13:09.530028
7946 22:13:09.530332 Set Vref, RX VrefLevel [Byte0]: 58
7947 22:13:09.533716 [Byte1]: 58
7948 22:13:09.537416
7949 22:13:09.537645 Set Vref, RX VrefLevel [Byte0]: 59
7950 22:13:09.541275 [Byte1]: 59
7951 22:13:09.545451
7952 22:13:09.545606 Set Vref, RX VrefLevel [Byte0]: 60
7953 22:13:09.548374 [Byte1]: 60
7954 22:13:09.552797
7955 22:13:09.552934 Set Vref, RX VrefLevel [Byte0]: 61
7956 22:13:09.556131 [Byte1]: 61
7957 22:13:09.560197
7958 22:13:09.560334 Set Vref, RX VrefLevel [Byte0]: 62
7959 22:13:09.566954 [Byte1]: 62
7960 22:13:09.567086
7961 22:13:09.570244 Set Vref, RX VrefLevel [Byte0]: 63
7962 22:13:09.573231 [Byte1]: 63
7963 22:13:09.573400
7964 22:13:09.576720 Set Vref, RX VrefLevel [Byte0]: 64
7965 22:13:09.580318 [Byte1]: 64
7966 22:13:09.583221
7967 22:13:09.583382 Set Vref, RX VrefLevel [Byte0]: 65
7968 22:13:09.586666 [Byte1]: 65
7969 22:13:09.590753
7970 22:13:09.590943 Set Vref, RX VrefLevel [Byte0]: 66
7971 22:13:09.594171 [Byte1]: 66
7972 22:13:09.598422
7973 22:13:09.598660 Set Vref, RX VrefLevel [Byte0]: 67
7974 22:13:09.602242 [Byte1]: 67
7975 22:13:09.606040
7976 22:13:09.606268 Set Vref, RX VrefLevel [Byte0]: 68
7977 22:13:09.609701 [Byte1]: 68
7978 22:13:09.613733
7979 22:13:09.613944 Set Vref, RX VrefLevel [Byte0]: 69
7980 22:13:09.617162 [Byte1]: 69
7981 22:13:09.621311
7982 22:13:09.621525 Set Vref, RX VrefLevel [Byte0]: 70
7983 22:13:09.624786 [Byte1]: 70
7984 22:13:09.629256
7985 22:13:09.629474 Set Vref, RX VrefLevel [Byte0]: 71
7986 22:13:09.632462 [Byte1]: 71
7987 22:13:09.636674
7988 22:13:09.636864 Set Vref, RX VrefLevel [Byte0]: 72
7989 22:13:09.640046 [Byte1]: 72
7990 22:13:09.644569
7991 22:13:09.644888 Set Vref, RX VrefLevel [Byte0]: 73
7992 22:13:09.647797 [Byte1]: 73
7993 22:13:09.651815
7994 22:13:09.652348 Set Vref, RX VrefLevel [Byte0]: 74
7995 22:13:09.655377 [Byte1]: 74
7996 22:13:09.659670
7997 22:13:09.660270 Set Vref, RX VrefLevel [Byte0]: 75
7998 22:13:09.666306 [Byte1]: 75
7999 22:13:09.666907
8000 22:13:09.669442 Set Vref, RX VrefLevel [Byte0]: 76
8001 22:13:09.672491 [Byte1]: 76
8002 22:13:09.672929
8003 22:13:09.675889 Set Vref, RX VrefLevel [Byte0]: 77
8004 22:13:09.679271 [Byte1]: 77
8005 22:13:09.682442
8006 22:13:09.682914 Final RX Vref Byte 0 = 64 to rank0
8007 22:13:09.685776 Final RX Vref Byte 1 = 62 to rank0
8008 22:13:09.689471 Final RX Vref Byte 0 = 64 to rank1
8009 22:13:09.692429 Final RX Vref Byte 1 = 62 to rank1==
8010 22:13:09.695291 Dram Type= 6, Freq= 0, CH_0, rank 0
8011 22:13:09.702513 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8012 22:13:09.702956 ==
8013 22:13:09.703294 DQS Delay:
8014 22:13:09.705935 DQS0 = 0, DQS1 = 0
8015 22:13:09.706368 DQM Delay:
8016 22:13:09.706816 DQM0 = 126, DQM1 = 119
8017 22:13:09.708845 DQ Delay:
8018 22:13:09.712599 DQ0 =126, DQ1 =128, DQ2 =126, DQ3 =122
8019 22:13:09.715103 DQ4 =126, DQ5 =114, DQ6 =134, DQ7 =138
8020 22:13:09.718628 DQ8 =112, DQ9 =106, DQ10 =120, DQ11 =114
8021 22:13:09.721684 DQ12 =124, DQ13 =124, DQ14 =130, DQ15 =126
8022 22:13:09.721914
8023 22:13:09.722098
8024 22:13:09.722268
8025 22:13:09.725043 [DramC_TX_OE_Calibration] TA2
8026 22:13:09.728533 Original DQ_B0 (3 6) =30, OEN = 27
8027 22:13:09.732253 Original DQ_B1 (3 6) =30, OEN = 27
8028 22:13:09.734671 24, 0x0, End_B0=24 End_B1=24
8029 22:13:09.738095 25, 0x0, End_B0=25 End_B1=25
8030 22:13:09.738329 26, 0x0, End_B0=26 End_B1=26
8031 22:13:09.741864 27, 0x0, End_B0=27 End_B1=27
8032 22:13:09.744857 28, 0x0, End_B0=28 End_B1=28
8033 22:13:09.747927 29, 0x0, End_B0=29 End_B1=29
8034 22:13:09.748159 30, 0x0, End_B0=30 End_B1=30
8035 22:13:09.751312 31, 0x5151, End_B0=30 End_B1=30
8036 22:13:09.754683 Byte0 end_step=30 best_step=27
8037 22:13:09.757747 Byte1 end_step=30 best_step=27
8038 22:13:09.761487 Byte0 TX OE(2T, 0.5T) = (3, 3)
8039 22:13:09.764479 Byte1 TX OE(2T, 0.5T) = (3, 3)
8040 22:13:09.764709
8041 22:13:09.764892
8042 22:13:09.771066 [DQSOSCAuto] RK0, (LSB)MR18= 0x1212, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 400 ps
8043 22:13:09.774246 CH0 RK0: MR19=303, MR18=1212
8044 22:13:09.780862 CH0_RK0: MR19=0x303, MR18=0x1212, DQSOSC=400, MR23=63, INC=23, DEC=15
8045 22:13:09.781095
8046 22:13:09.784013 ----->DramcWriteLeveling(PI) begin...
8047 22:13:09.784249 ==
8048 22:13:09.787243 Dram Type= 6, Freq= 0, CH_0, rank 1
8049 22:13:09.790503 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8050 22:13:09.793976 ==
8051 22:13:09.794205 Write leveling (Byte 0): 34 => 34
8052 22:13:09.797105 Write leveling (Byte 1): 28 => 28
8053 22:13:09.800607 DramcWriteLeveling(PI) end<-----
8054 22:13:09.800838
8055 22:13:09.801022 ==
8056 22:13:09.804370 Dram Type= 6, Freq= 0, CH_0, rank 1
8057 22:13:09.810983 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8058 22:13:09.811290 ==
8059 22:13:09.813994 [Gating] SW mode calibration
8060 22:13:09.820355 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8061 22:13:09.823545 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8062 22:13:09.830552 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8063 22:13:09.833540 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8064 22:13:09.836944 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8065 22:13:09.843347 1 4 12 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (1 1)
8066 22:13:09.847049 1 4 16 | B1->B0 | 2828 3434 | 0 1 | (1 1) (1 1)
8067 22:13:09.850168 1 4 20 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
8068 22:13:09.856797 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8069 22:13:09.859893 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8070 22:13:09.863443 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8071 22:13:09.869981 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8072 22:13:09.873125 1 5 8 | B1->B0 | 3434 3333 | 1 0 | (1 1) (1 0)
8073 22:13:09.876483 1 5 12 | B1->B0 | 3434 2626 | 1 0 | (1 1) (0 0)
8074 22:13:09.882541 1 5 16 | B1->B0 | 3333 2323 | 0 0 | (0 1) (0 0)
8075 22:13:09.886126 1 5 20 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
8076 22:13:09.889261 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8077 22:13:09.895573 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8078 22:13:09.899488 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8079 22:13:09.902684 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8080 22:13:09.909084 1 6 8 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
8081 22:13:09.912668 1 6 12 | B1->B0 | 2323 4040 | 0 0 | (0 0) (0 0)
8082 22:13:09.915757 1 6 16 | B1->B0 | 3232 4646 | 1 0 | (0 0) (0 0)
8083 22:13:09.922254 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8084 22:13:09.925684 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8085 22:13:09.928789 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8086 22:13:09.935162 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8087 22:13:09.938600 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8088 22:13:09.941932 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8089 22:13:09.948832 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8090 22:13:09.951799 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8091 22:13:09.955141 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8092 22:13:09.961838 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8093 22:13:09.964820 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8094 22:13:09.968422 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8095 22:13:09.974396 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8096 22:13:09.977842 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8097 22:13:09.981602 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8098 22:13:09.987476 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8099 22:13:09.991418 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8100 22:13:09.994463 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8101 22:13:10.001165 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8102 22:13:10.003932 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8103 22:13:10.007591 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8104 22:13:10.014122 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8105 22:13:10.017497 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8106 22:13:10.020545 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8107 22:13:10.024226 Total UI for P1: 0, mck2ui 16
8108 22:13:10.027590 best dqsien dly found for B0: ( 1, 9, 10)
8109 22:13:10.034451 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8110 22:13:10.037187 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8111 22:13:10.040539 Total UI for P1: 0, mck2ui 16
8112 22:13:10.043884 best dqsien dly found for B1: ( 1, 9, 16)
8113 22:13:10.047321 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8114 22:13:10.050887 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8115 22:13:10.050970
8116 22:13:10.053905 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8117 22:13:10.060745 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8118 22:13:10.060920 [Gating] SW calibration Done
8119 22:13:10.061008 ==
8120 22:13:10.064034 Dram Type= 6, Freq= 0, CH_0, rank 1
8121 22:13:10.070365 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8122 22:13:10.070544 ==
8123 22:13:10.070635 RX Vref Scan: 0
8124 22:13:10.070718
8125 22:13:10.073421 RX Vref 0 -> 0, step: 1
8126 22:13:10.073532
8127 22:13:10.076966 RX Delay 0 -> 252, step: 8
8128 22:13:10.080311 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8129 22:13:10.083595 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8130 22:13:10.086636 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8131 22:13:10.093625 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8132 22:13:10.096836 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8133 22:13:10.099710 iDelay=200, Bit 5, Center 111 (56 ~ 167) 112
8134 22:13:10.103317 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8135 22:13:10.106461 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8136 22:13:10.113067 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8137 22:13:10.116518 iDelay=200, Bit 9, Center 107 (48 ~ 167) 120
8138 22:13:10.119733 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8139 22:13:10.123355 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8140 22:13:10.126669 iDelay=200, Bit 12, Center 127 (64 ~ 191) 128
8141 22:13:10.133442 iDelay=200, Bit 13, Center 127 (72 ~ 183) 112
8142 22:13:10.136909 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8143 22:13:10.139449 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
8144 22:13:10.139974 ==
8145 22:13:10.142905 Dram Type= 6, Freq= 0, CH_0, rank 1
8146 22:13:10.146385 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8147 22:13:10.149919 ==
8148 22:13:10.150431 DQS Delay:
8149 22:13:10.150902 DQS0 = 0, DQS1 = 0
8150 22:13:10.153229 DQM Delay:
8151 22:13:10.153650 DQM0 = 127, DQM1 = 121
8152 22:13:10.156206 DQ Delay:
8153 22:13:10.160048 DQ0 =127, DQ1 =131, DQ2 =123, DQ3 =123
8154 22:13:10.162759 DQ4 =127, DQ5 =111, DQ6 =139, DQ7 =139
8155 22:13:10.166702 DQ8 =115, DQ9 =107, DQ10 =123, DQ11 =115
8156 22:13:10.169692 DQ12 =127, DQ13 =127, DQ14 =131, DQ15 =127
8157 22:13:10.170112
8158 22:13:10.170449
8159 22:13:10.170759 ==
8160 22:13:10.172674 Dram Type= 6, Freq= 0, CH_0, rank 1
8161 22:13:10.176058 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8162 22:13:10.176481 ==
8163 22:13:10.176840
8164 22:13:10.180051
8165 22:13:10.180469 TX Vref Scan disable
8166 22:13:10.183048 == TX Byte 0 ==
8167 22:13:10.186153 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8168 22:13:10.189443 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8169 22:13:10.192686 == TX Byte 1 ==
8170 22:13:10.196002 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8171 22:13:10.199618 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8172 22:13:10.200039 ==
8173 22:13:10.202720 Dram Type= 6, Freq= 0, CH_0, rank 1
8174 22:13:10.209170 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8175 22:13:10.209761 ==
8176 22:13:10.222445
8177 22:13:10.225577 TX Vref early break, caculate TX vref
8178 22:13:10.229226 TX Vref=16, minBit 9, minWin=21, winSum=365
8179 22:13:10.232352 TX Vref=18, minBit 8, minWin=22, winSum=374
8180 22:13:10.235950 TX Vref=20, minBit 8, minWin=22, winSum=384
8181 22:13:10.239669 TX Vref=22, minBit 8, minWin=23, winSum=394
8182 22:13:10.242647 TX Vref=24, minBit 8, minWin=24, winSum=399
8183 22:13:10.248914 TX Vref=26, minBit 8, minWin=24, winSum=407
8184 22:13:10.252437 TX Vref=28, minBit 8, minWin=24, winSum=407
8185 22:13:10.255688 TX Vref=30, minBit 8, minWin=23, winSum=402
8186 22:13:10.259168 TX Vref=32, minBit 8, minWin=22, winSum=390
8187 22:13:10.262504 TX Vref=34, minBit 8, minWin=23, winSum=388
8188 22:13:10.269154 TX Vref=36, minBit 8, minWin=22, winSum=380
8189 22:13:10.272210 [TxChooseVref] Worse bit 8, Min win 24, Win sum 407, Final Vref 26
8190 22:13:10.272839
8191 22:13:10.275185 Final TX Range 0 Vref 26
8192 22:13:10.275676
8193 22:13:10.276268 ==
8194 22:13:10.278562 Dram Type= 6, Freq= 0, CH_0, rank 1
8195 22:13:10.282296 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8196 22:13:10.282909 ==
8197 22:13:10.285371
8198 22:13:10.285971
8199 22:13:10.286332 TX Vref Scan disable
8200 22:13:10.292022 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8201 22:13:10.292451 == TX Byte 0 ==
8202 22:13:10.295102 u2DelayCellOfst[0]=15 cells (4 PI)
8203 22:13:10.298790 u2DelayCellOfst[1]=22 cells (6 PI)
8204 22:13:10.301817 u2DelayCellOfst[2]=15 cells (4 PI)
8205 22:13:10.305240 u2DelayCellOfst[3]=15 cells (4 PI)
8206 22:13:10.308220 u2DelayCellOfst[4]=11 cells (3 PI)
8207 22:13:10.311644 u2DelayCellOfst[5]=0 cells (0 PI)
8208 22:13:10.315363 u2DelayCellOfst[6]=22 cells (6 PI)
8209 22:13:10.318175 u2DelayCellOfst[7]=18 cells (5 PI)
8210 22:13:10.321271 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
8211 22:13:10.325020 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8212 22:13:10.328427 == TX Byte 1 ==
8213 22:13:10.331302 u2DelayCellOfst[8]=0 cells (0 PI)
8214 22:13:10.334490 u2DelayCellOfst[9]=0 cells (0 PI)
8215 22:13:10.338072 u2DelayCellOfst[10]=7 cells (2 PI)
8216 22:13:10.341463 u2DelayCellOfst[11]=3 cells (1 PI)
8217 22:13:10.344507 u2DelayCellOfst[12]=11 cells (3 PI)
8218 22:13:10.347788 u2DelayCellOfst[13]=7 cells (2 PI)
8219 22:13:10.350798 u2DelayCellOfst[14]=11 cells (3 PI)
8220 22:13:10.354409 u2DelayCellOfst[15]=7 cells (2 PI)
8221 22:13:10.357262 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8222 22:13:10.360557 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8223 22:13:10.363886 DramC Write-DBI on
8224 22:13:10.364036 ==
8225 22:13:10.367074 Dram Type= 6, Freq= 0, CH_0, rank 1
8226 22:13:10.370672 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8227 22:13:10.370754 ==
8228 22:13:10.370819
8229 22:13:10.370879
8230 22:13:10.373702 TX Vref Scan disable
8231 22:13:10.377416 == TX Byte 0 ==
8232 22:13:10.380379 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
8233 22:13:10.380461 == TX Byte 1 ==
8234 22:13:10.386791 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8235 22:13:10.386872 DramC Write-DBI off
8236 22:13:10.386937
8237 22:13:10.386995 [DATLAT]
8238 22:13:10.390297 Freq=1600, CH0 RK1
8239 22:13:10.390378
8240 22:13:10.393626 DATLAT Default: 0xf
8241 22:13:10.393707 0, 0xFFFF, sum = 0
8242 22:13:10.396887 1, 0xFFFF, sum = 0
8243 22:13:10.396970 2, 0xFFFF, sum = 0
8244 22:13:10.399905 3, 0xFFFF, sum = 0
8245 22:13:10.399987 4, 0xFFFF, sum = 0
8246 22:13:10.403708 5, 0xFFFF, sum = 0
8247 22:13:10.403794 6, 0xFFFF, sum = 0
8248 22:13:10.406719 7, 0xFFFF, sum = 0
8249 22:13:10.406802 8, 0xFFFF, sum = 0
8250 22:13:10.409821 9, 0xFFFF, sum = 0
8251 22:13:10.409904 10, 0xFFFF, sum = 0
8252 22:13:10.412875 11, 0xFFFF, sum = 0
8253 22:13:10.412958 12, 0xFFFF, sum = 0
8254 22:13:10.416640 13, 0xCFFF, sum = 0
8255 22:13:10.416730 14, 0x0, sum = 1
8256 22:13:10.419800 15, 0x0, sum = 2
8257 22:13:10.419889 16, 0x0, sum = 3
8258 22:13:10.422963 17, 0x0, sum = 4
8259 22:13:10.423068 best_step = 15
8260 22:13:10.423143
8261 22:13:10.423213 ==
8262 22:13:10.426224 Dram Type= 6, Freq= 0, CH_0, rank 1
8263 22:13:10.433105 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8264 22:13:10.433219 ==
8265 22:13:10.433309 RX Vref Scan: 0
8266 22:13:10.433392
8267 22:13:10.436236 RX Vref 0 -> 0, step: 1
8268 22:13:10.436393
8269 22:13:10.439734 RX Delay 3 -> 252, step: 4
8270 22:13:10.443295 iDelay=191, Bit 0, Center 124 (71 ~ 178) 108
8271 22:13:10.446241 iDelay=191, Bit 1, Center 128 (75 ~ 182) 108
8272 22:13:10.452643 iDelay=191, Bit 2, Center 122 (71 ~ 174) 104
8273 22:13:10.456188 iDelay=191, Bit 3, Center 122 (67 ~ 178) 112
8274 22:13:10.459232 iDelay=191, Bit 4, Center 124 (71 ~ 178) 108
8275 22:13:10.462774 iDelay=191, Bit 5, Center 112 (59 ~ 166) 108
8276 22:13:10.466096 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8277 22:13:10.472889 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8278 22:13:10.475981 iDelay=191, Bit 8, Center 110 (55 ~ 166) 112
8279 22:13:10.479567 iDelay=191, Bit 9, Center 106 (51 ~ 162) 112
8280 22:13:10.482592 iDelay=191, Bit 10, Center 118 (63 ~ 174) 112
8281 22:13:10.486159 iDelay=191, Bit 11, Center 112 (55 ~ 170) 116
8282 22:13:10.492526 iDelay=191, Bit 12, Center 122 (67 ~ 178) 112
8283 22:13:10.495628 iDelay=191, Bit 13, Center 122 (67 ~ 178) 112
8284 22:13:10.499296 iDelay=191, Bit 14, Center 128 (71 ~ 186) 116
8285 22:13:10.502794 iDelay=191, Bit 15, Center 124 (67 ~ 182) 116
8286 22:13:10.503215 ==
8287 22:13:10.506069 Dram Type= 6, Freq= 0, CH_0, rank 1
8288 22:13:10.512074 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8289 22:13:10.512496 ==
8290 22:13:10.512830 DQS Delay:
8291 22:13:10.515176 DQS0 = 0, DQS1 = 0
8292 22:13:10.515637 DQM Delay:
8293 22:13:10.518937 DQM0 = 125, DQM1 = 117
8294 22:13:10.519481 DQ Delay:
8295 22:13:10.522114 DQ0 =124, DQ1 =128, DQ2 =122, DQ3 =122
8296 22:13:10.525424 DQ4 =124, DQ5 =112, DQ6 =134, DQ7 =134
8297 22:13:10.528493 DQ8 =110, DQ9 =106, DQ10 =118, DQ11 =112
8298 22:13:10.532074 DQ12 =122, DQ13 =122, DQ14 =128, DQ15 =124
8299 22:13:10.532256
8300 22:13:10.532400
8301 22:13:10.532533
8302 22:13:10.535205 [DramC_TX_OE_Calibration] TA2
8303 22:13:10.538516 Original DQ_B0 (3 6) =30, OEN = 27
8304 22:13:10.541374 Original DQ_B1 (3 6) =30, OEN = 27
8305 22:13:10.544876 24, 0x0, End_B0=24 End_B1=24
8306 22:13:10.548238 25, 0x0, End_B0=25 End_B1=25
8307 22:13:10.548500 26, 0x0, End_B0=26 End_B1=26
8308 22:13:10.551625 27, 0x0, End_B0=27 End_B1=27
8309 22:13:10.555209 28, 0x0, End_B0=28 End_B1=28
8310 22:13:10.558102 29, 0x0, End_B0=29 End_B1=29
8311 22:13:10.561612 30, 0x0, End_B0=30 End_B1=30
8312 22:13:10.561795 31, 0x4141, End_B0=30 End_B1=30
8313 22:13:10.565476 Byte0 end_step=30 best_step=27
8314 22:13:10.567948 Byte1 end_step=30 best_step=27
8315 22:13:10.571329 Byte0 TX OE(2T, 0.5T) = (3, 3)
8316 22:13:10.574845 Byte1 TX OE(2T, 0.5T) = (3, 3)
8317 22:13:10.575065
8318 22:13:10.575232
8319 22:13:10.581235 [DQSOSCAuto] RK1, (LSB)MR18= 0x2614, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 390 ps
8320 22:13:10.584627 CH0 RK1: MR19=303, MR18=2614
8321 22:13:10.591392 CH0_RK1: MR19=0x303, MR18=0x2614, DQSOSC=390, MR23=63, INC=24, DEC=16
8322 22:13:10.594963 [RxdqsGatingPostProcess] freq 1600
8323 22:13:10.601458 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8324 22:13:10.604498 best DQS0 dly(2T, 0.5T) = (1, 1)
8325 22:13:10.605094 best DQS1 dly(2T, 0.5T) = (1, 1)
8326 22:13:10.607968 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8327 22:13:10.611555 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8328 22:13:10.614611 best DQS0 dly(2T, 0.5T) = (1, 1)
8329 22:13:10.618180 best DQS1 dly(2T, 0.5T) = (1, 1)
8330 22:13:10.621370 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8331 22:13:10.625074 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8332 22:13:10.628325 Pre-setting of DQS Precalculation
8333 22:13:10.631468 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8334 22:13:10.634666 ==
8335 22:13:10.638156 Dram Type= 6, Freq= 0, CH_1, rank 0
8336 22:13:10.640930 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8337 22:13:10.641401 ==
8338 22:13:10.644486 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8339 22:13:10.650766 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8340 22:13:10.654303 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8341 22:13:10.660416 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8342 22:13:10.668999 [CA 0] Center 41 (13~70) winsize 58
8343 22:13:10.672848 [CA 1] Center 41 (11~72) winsize 62
8344 22:13:10.675649 [CA 2] Center 37 (8~66) winsize 59
8345 22:13:10.679279 [CA 3] Center 37 (8~66) winsize 59
8346 22:13:10.682639 [CA 4] Center 37 (8~67) winsize 60
8347 22:13:10.685850 [CA 5] Center 35 (6~65) winsize 60
8348 22:13:10.686309
8349 22:13:10.689235 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8350 22:13:10.689692
8351 22:13:10.691953 [CATrainingPosCal] consider 1 rank data
8352 22:13:10.695574 u2DelayCellTimex100 = 258/100 ps
8353 22:13:10.701799 CA0 delay=41 (13~70),Diff = 6 PI (22 cell)
8354 22:13:10.705387 CA1 delay=41 (11~72),Diff = 6 PI (22 cell)
8355 22:13:10.708985 CA2 delay=37 (8~66),Diff = 2 PI (7 cell)
8356 22:13:10.712190 CA3 delay=37 (8~66),Diff = 2 PI (7 cell)
8357 22:13:10.714975 CA4 delay=37 (8~67),Diff = 2 PI (7 cell)
8358 22:13:10.719053 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
8359 22:13:10.719482
8360 22:13:10.721683 CA PerBit enable=1, Macro0, CA PI delay=35
8361 22:13:10.722004
8362 22:13:10.725221 [CBTSetCACLKResult] CA Dly = 35
8363 22:13:10.728235 CS Dly: 10 (0~41)
8364 22:13:10.731606 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8365 22:13:10.734732 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8366 22:13:10.735049 ==
8367 22:13:10.738430 Dram Type= 6, Freq= 0, CH_1, rank 1
8368 22:13:10.745153 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8369 22:13:10.745587 ==
8370 22:13:10.748078 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8371 22:13:10.754595 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8372 22:13:10.757855 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8373 22:13:10.764150 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8374 22:13:10.771810 [CA 0] Center 41 (12~71) winsize 60
8375 22:13:10.775653 [CA 1] Center 42 (13~72) winsize 60
8376 22:13:10.778442 [CA 2] Center 37 (8~67) winsize 60
8377 22:13:10.781937 [CA 3] Center 37 (8~66) winsize 59
8378 22:13:10.785405 [CA 4] Center 38 (8~68) winsize 61
8379 22:13:10.788626 [CA 5] Center 36 (6~67) winsize 62
8380 22:13:10.789085
8381 22:13:10.792041 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8382 22:13:10.792544
8383 22:13:10.798756 [CATrainingPosCal] consider 2 rank data
8384 22:13:10.799370 u2DelayCellTimex100 = 258/100 ps
8385 22:13:10.805067 CA0 delay=41 (13~70),Diff = 6 PI (22 cell)
8386 22:13:10.808383 CA1 delay=42 (13~72),Diff = 7 PI (26 cell)
8387 22:13:10.811868 CA2 delay=37 (8~66),Diff = 2 PI (7 cell)
8388 22:13:10.814662 CA3 delay=37 (8~66),Diff = 2 PI (7 cell)
8389 22:13:10.818081 CA4 delay=37 (8~67),Diff = 2 PI (7 cell)
8390 22:13:10.821316 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
8391 22:13:10.821777
8392 22:13:10.824944 CA PerBit enable=1, Macro0, CA PI delay=35
8393 22:13:10.825404
8394 22:13:10.828130 [CBTSetCACLKResult] CA Dly = 35
8395 22:13:10.831213 CS Dly: 11 (0~44)
8396 22:13:10.834540 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8397 22:13:10.838147 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8398 22:13:10.838613
8399 22:13:10.841146 ----->DramcWriteLeveling(PI) begin...
8400 22:13:10.844724 ==
8401 22:13:10.845138 Dram Type= 6, Freq= 0, CH_1, rank 0
8402 22:13:10.851682 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8403 22:13:10.852104 ==
8404 22:13:10.854640 Write leveling (Byte 0): 25 => 25
8405 22:13:10.857672 Write leveling (Byte 1): 28 => 28
8406 22:13:10.861015 DramcWriteLeveling(PI) end<-----
8407 22:13:10.861504
8408 22:13:10.861996 ==
8409 22:13:10.864024 Dram Type= 6, Freq= 0, CH_1, rank 0
8410 22:13:10.867288 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8411 22:13:10.867758 ==
8412 22:13:10.870574 [Gating] SW mode calibration
8413 22:13:10.877285 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8414 22:13:10.884344 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8415 22:13:10.887231 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8416 22:13:10.890735 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8417 22:13:10.897148 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8418 22:13:10.900627 1 4 12 | B1->B0 | 2423 2322 | 1 1 | (0 0) (0 0)
8419 22:13:10.904036 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8420 22:13:10.910830 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8421 22:13:10.913621 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8422 22:13:10.916859 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8423 22:13:10.923659 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8424 22:13:10.927444 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8425 22:13:10.930432 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8426 22:13:10.936881 1 5 12 | B1->B0 | 3333 3434 | 1 1 | (1 0) (1 0)
8427 22:13:10.940176 1 5 16 | B1->B0 | 2626 2828 | 1 0 | (1 0) (0 1)
8428 22:13:10.943846 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8429 22:13:10.949989 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8430 22:13:10.953544 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8431 22:13:10.956355 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8432 22:13:10.962990 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8433 22:13:10.966669 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8434 22:13:10.969620 1 6 12 | B1->B0 | 3232 2a2a | 1 0 | (0 0) (0 0)
8435 22:13:10.976481 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8436 22:13:10.979535 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8437 22:13:10.982870 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8438 22:13:10.989300 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8439 22:13:10.992920 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8440 22:13:10.996498 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8441 22:13:11.002972 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8442 22:13:11.006502 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8443 22:13:11.009817 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8444 22:13:11.015710 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8445 22:13:11.019015 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8446 22:13:11.022711 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8447 22:13:11.029007 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8448 22:13:11.032191 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8449 22:13:11.035890 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8450 22:13:11.042173 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8451 22:13:11.045652 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8452 22:13:11.048525 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8453 22:13:11.055453 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8454 22:13:11.058556 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8455 22:13:11.062055 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8456 22:13:11.068493 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8457 22:13:11.071910 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8458 22:13:11.075157 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8459 22:13:11.081481 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8460 22:13:11.084994 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8461 22:13:11.088111 Total UI for P1: 0, mck2ui 16
8462 22:13:11.091399 best dqsien dly found for B0: ( 1, 9, 16)
8463 22:13:11.095161 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8464 22:13:11.098302 Total UI for P1: 0, mck2ui 16
8465 22:13:11.101688 best dqsien dly found for B1: ( 1, 9, 16)
8466 22:13:11.104992 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
8467 22:13:11.108243 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8468 22:13:11.108808
8469 22:13:11.114649 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
8470 22:13:11.117673 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8471 22:13:11.121373 [Gating] SW calibration Done
8472 22:13:11.121840 ==
8473 22:13:11.124716 Dram Type= 6, Freq= 0, CH_1, rank 0
8474 22:13:11.127609 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8475 22:13:11.128089 ==
8476 22:13:11.128523 RX Vref Scan: 0
8477 22:13:11.130807
8478 22:13:11.131271 RX Vref 0 -> 0, step: 1
8479 22:13:11.131704
8480 22:13:11.134407 RX Delay 0 -> 252, step: 8
8481 22:13:11.137704 iDelay=208, Bit 0, Center 135 (80 ~ 191) 112
8482 22:13:11.141209 iDelay=208, Bit 1, Center 131 (72 ~ 191) 120
8483 22:13:11.147511 iDelay=208, Bit 2, Center 119 (64 ~ 175) 112
8484 22:13:11.151209 iDelay=208, Bit 3, Center 131 (72 ~ 191) 120
8485 22:13:11.154383 iDelay=208, Bit 4, Center 127 (72 ~ 183) 112
8486 22:13:11.157315 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8487 22:13:11.160895 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8488 22:13:11.166926 iDelay=208, Bit 7, Center 131 (72 ~ 191) 120
8489 22:13:11.170464 iDelay=208, Bit 8, Center 111 (56 ~ 167) 112
8490 22:13:11.173694 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8491 22:13:11.177062 iDelay=208, Bit 10, Center 127 (80 ~ 175) 96
8492 22:13:11.180083 iDelay=208, Bit 11, Center 119 (64 ~ 175) 112
8493 22:13:11.186752 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8494 22:13:11.189838 iDelay=208, Bit 13, Center 135 (80 ~ 191) 112
8495 22:13:11.193146 iDelay=208, Bit 14, Center 131 (80 ~ 183) 104
8496 22:13:11.196241 iDelay=208, Bit 15, Center 135 (80 ~ 191) 112
8497 22:13:11.199624 ==
8498 22:13:11.199798 Dram Type= 6, Freq= 0, CH_1, rank 0
8499 22:13:11.206410 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8500 22:13:11.206546 ==
8501 22:13:11.206653 DQS Delay:
8502 22:13:11.209493 DQS0 = 0, DQS1 = 0
8503 22:13:11.209635 DQM Delay:
8504 22:13:11.212577 DQM0 = 133, DQM1 = 126
8505 22:13:11.212756 DQ Delay:
8506 22:13:11.216369 DQ0 =135, DQ1 =131, DQ2 =119, DQ3 =131
8507 22:13:11.219246 DQ4 =127, DQ5 =147, DQ6 =143, DQ7 =131
8508 22:13:11.222921 DQ8 =111, DQ9 =115, DQ10 =127, DQ11 =119
8509 22:13:11.226134 DQ12 =135, DQ13 =135, DQ14 =131, DQ15 =135
8510 22:13:11.226270
8511 22:13:11.226377
8512 22:13:11.226475 ==
8513 22:13:11.229345 Dram Type= 6, Freq= 0, CH_1, rank 0
8514 22:13:11.235623 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8515 22:13:11.235760 ==
8516 22:13:11.235869
8517 22:13:11.235970
8518 22:13:11.239597 TX Vref Scan disable
8519 22:13:11.239734 == TX Byte 0 ==
8520 22:13:11.242504 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8521 22:13:11.248791 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8522 22:13:11.248950 == TX Byte 1 ==
8523 22:13:11.252292 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8524 22:13:11.258846 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8525 22:13:11.259058 ==
8526 22:13:11.262082 Dram Type= 6, Freq= 0, CH_1, rank 0
8527 22:13:11.265381 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8528 22:13:11.265698 ==
8529 22:13:11.280046
8530 22:13:11.283215 TX Vref early break, caculate TX vref
8531 22:13:11.286385 TX Vref=16, minBit 11, minWin=21, winSum=364
8532 22:13:11.290115 TX Vref=18, minBit 11, minWin=21, winSum=373
8533 22:13:11.293170 TX Vref=20, minBit 5, minWin=23, winSum=382
8534 22:13:11.296198 TX Vref=22, minBit 9, minWin=23, winSum=389
8535 22:13:11.300044 TX Vref=24, minBit 1, minWin=24, winSum=404
8536 22:13:11.306155 TX Vref=26, minBit 13, minWin=24, winSum=408
8537 22:13:11.309780 TX Vref=28, minBit 0, minWin=25, winSum=414
8538 22:13:11.312849 TX Vref=30, minBit 6, minWin=24, winSum=412
8539 22:13:11.316136 TX Vref=32, minBit 6, minWin=23, winSum=400
8540 22:13:11.319536 TX Vref=34, minBit 1, minWin=23, winSum=395
8541 22:13:11.326030 TX Vref=36, minBit 1, minWin=22, winSum=377
8542 22:13:11.329011 [TxChooseVref] Worse bit 0, Min win 25, Win sum 414, Final Vref 28
8543 22:13:11.329312
8544 22:13:11.332571 Final TX Range 0 Vref 28
8545 22:13:11.332901
8546 22:13:11.333146 ==
8547 22:13:11.336138 Dram Type= 6, Freq= 0, CH_1, rank 0
8548 22:13:11.338852 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8549 22:13:11.342398 ==
8550 22:13:11.342771
8551 22:13:11.343040
8552 22:13:11.343269 TX Vref Scan disable
8553 22:13:11.349177 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8554 22:13:11.349538 == TX Byte 0 ==
8555 22:13:11.352412 u2DelayCellOfst[0]=18 cells (5 PI)
8556 22:13:11.355838 u2DelayCellOfst[1]=15 cells (4 PI)
8557 22:13:11.358581 u2DelayCellOfst[2]=0 cells (0 PI)
8558 22:13:11.361960 u2DelayCellOfst[3]=7 cells (2 PI)
8559 22:13:11.365088 u2DelayCellOfst[4]=11 cells (3 PI)
8560 22:13:11.368937 u2DelayCellOfst[5]=26 cells (7 PI)
8561 22:13:11.371881 u2DelayCellOfst[6]=22 cells (6 PI)
8562 22:13:11.375189 u2DelayCellOfst[7]=7 cells (2 PI)
8563 22:13:11.378857 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8564 22:13:11.382088 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8565 22:13:11.385459 == TX Byte 1 ==
8566 22:13:11.388781 u2DelayCellOfst[8]=0 cells (0 PI)
8567 22:13:11.391715 u2DelayCellOfst[9]=3 cells (1 PI)
8568 22:13:11.394782 u2DelayCellOfst[10]=15 cells (4 PI)
8569 22:13:11.398119 u2DelayCellOfst[11]=7 cells (2 PI)
8570 22:13:11.401690 u2DelayCellOfst[12]=15 cells (4 PI)
8571 22:13:11.405409 u2DelayCellOfst[13]=18 cells (5 PI)
8572 22:13:11.408231 u2DelayCellOfst[14]=18 cells (5 PI)
8573 22:13:11.411794 u2DelayCellOfst[15]=18 cells (5 PI)
8574 22:13:11.414714 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8575 22:13:11.418153 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8576 22:13:11.421546 DramC Write-DBI on
8577 22:13:11.421645 ==
8578 22:13:11.424829 Dram Type= 6, Freq= 0, CH_1, rank 0
8579 22:13:11.428308 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8580 22:13:11.428401 ==
8581 22:13:11.428465
8582 22:13:11.428524
8583 22:13:11.431174 TX Vref Scan disable
8584 22:13:11.431244 == TX Byte 0 ==
8585 22:13:11.437906 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8586 22:13:11.437989 == TX Byte 1 ==
8587 22:13:11.444481 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8588 22:13:11.444589 DramC Write-DBI off
8589 22:13:11.444682
8590 22:13:11.444771 [DATLAT]
8591 22:13:11.447785 Freq=1600, CH1 RK0
8592 22:13:11.447877
8593 22:13:11.451161 DATLAT Default: 0xf
8594 22:13:11.451246 0, 0xFFFF, sum = 0
8595 22:13:11.454191 1, 0xFFFF, sum = 0
8596 22:13:11.454274 2, 0xFFFF, sum = 0
8597 22:13:11.457570 3, 0xFFFF, sum = 0
8598 22:13:11.457654 4, 0xFFFF, sum = 0
8599 22:13:11.461240 5, 0xFFFF, sum = 0
8600 22:13:11.461324 6, 0xFFFF, sum = 0
8601 22:13:11.464696 7, 0xFFFF, sum = 0
8602 22:13:11.464778 8, 0xFFFF, sum = 0
8603 22:13:11.467392 9, 0xFFFF, sum = 0
8604 22:13:11.467475 10, 0xFFFF, sum = 0
8605 22:13:11.470624 11, 0xFFFF, sum = 0
8606 22:13:11.470708 12, 0xFFFF, sum = 0
8607 22:13:11.473864 13, 0x8FFF, sum = 0
8608 22:13:11.473947 14, 0x0, sum = 1
8609 22:13:11.477587 15, 0x0, sum = 2
8610 22:13:11.477676 16, 0x0, sum = 3
8611 22:13:11.480740 17, 0x0, sum = 4
8612 22:13:11.480836 best_step = 15
8613 22:13:11.480911
8614 22:13:11.480982 ==
8615 22:13:11.484321 Dram Type= 6, Freq= 0, CH_1, rank 0
8616 22:13:11.490862 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8617 22:13:11.491008 ==
8618 22:13:11.491134 RX Vref Scan: 1
8619 22:13:11.491255
8620 22:13:11.494146 Set Vref Range= 24 -> 127
8621 22:13:11.494258
8622 22:13:11.497329 RX Vref 24 -> 127, step: 1
8623 22:13:11.497456
8624 22:13:11.500478 RX Delay 11 -> 252, step: 4
8625 22:13:11.500615
8626 22:13:11.504209 Set Vref, RX VrefLevel [Byte0]: 24
8627 22:13:11.507159 [Byte1]: 24
8628 22:13:11.507357
8629 22:13:11.510186 Set Vref, RX VrefLevel [Byte0]: 25
8630 22:13:11.514015 [Byte1]: 25
8631 22:13:11.514241
8632 22:13:11.517012 Set Vref, RX VrefLevel [Byte0]: 26
8633 22:13:11.520473 [Byte1]: 26
8634 22:13:11.523461
8635 22:13:11.523733 Set Vref, RX VrefLevel [Byte0]: 27
8636 22:13:11.527220 [Byte1]: 27
8637 22:13:11.531428
8638 22:13:11.532058 Set Vref, RX VrefLevel [Byte0]: 28
8639 22:13:11.534854 [Byte1]: 28
8640 22:13:11.538936
8641 22:13:11.539538 Set Vref, RX VrefLevel [Byte0]: 29
8642 22:13:11.542525 [Byte1]: 29
8643 22:13:11.546316
8644 22:13:11.546738 Set Vref, RX VrefLevel [Byte0]: 30
8645 22:13:11.549757 [Byte1]: 30
8646 22:13:11.554125
8647 22:13:11.554683 Set Vref, RX VrefLevel [Byte0]: 31
8648 22:13:11.557698 [Byte1]: 31
8649 22:13:11.561667
8650 22:13:11.562090 Set Vref, RX VrefLevel [Byte0]: 32
8651 22:13:11.564878 [Byte1]: 32
8652 22:13:11.569651
8653 22:13:11.570076 Set Vref, RX VrefLevel [Byte0]: 33
8654 22:13:11.572588 [Byte1]: 33
8655 22:13:11.576982
8656 22:13:11.577407 Set Vref, RX VrefLevel [Byte0]: 34
8657 22:13:11.580155 [Byte1]: 34
8658 22:13:11.584414
8659 22:13:11.585030 Set Vref, RX VrefLevel [Byte0]: 35
8660 22:13:11.587999 [Byte1]: 35
8661 22:13:11.592350
8662 22:13:11.592795 Set Vref, RX VrefLevel [Byte0]: 36
8663 22:13:11.595620 [Byte1]: 36
8664 22:13:11.599952
8665 22:13:11.600611 Set Vref, RX VrefLevel [Byte0]: 37
8666 22:13:11.602875 [Byte1]: 37
8667 22:13:11.607673
8668 22:13:11.608096 Set Vref, RX VrefLevel [Byte0]: 38
8669 22:13:11.610727 [Byte1]: 38
8670 22:13:11.615020
8671 22:13:11.615447 Set Vref, RX VrefLevel [Byte0]: 39
8672 22:13:11.618551 [Byte1]: 39
8673 22:13:11.622629
8674 22:13:11.623053 Set Vref, RX VrefLevel [Byte0]: 40
8675 22:13:11.626315 [Byte1]: 40
8676 22:13:11.630634
8677 22:13:11.631058 Set Vref, RX VrefLevel [Byte0]: 41
8678 22:13:11.633996 [Byte1]: 41
8679 22:13:11.638419
8680 22:13:11.638991 Set Vref, RX VrefLevel [Byte0]: 42
8681 22:13:11.641536 [Byte1]: 42
8682 22:13:11.645443
8683 22:13:11.645861 Set Vref, RX VrefLevel [Byte0]: 43
8684 22:13:11.648961 [Byte1]: 43
8685 22:13:11.653380
8686 22:13:11.653799 Set Vref, RX VrefLevel [Byte0]: 44
8687 22:13:11.656154 [Byte1]: 44
8688 22:13:11.660972
8689 22:13:11.661394 Set Vref, RX VrefLevel [Byte0]: 45
8690 22:13:11.664078 [Byte1]: 45
8691 22:13:11.668125
8692 22:13:11.668701 Set Vref, RX VrefLevel [Byte0]: 46
8693 22:13:11.671547 [Byte1]: 46
8694 22:13:11.676347
8695 22:13:11.676771 Set Vref, RX VrefLevel [Byte0]: 47
8696 22:13:11.679764 [Byte1]: 47
8697 22:13:11.683695
8698 22:13:11.684194 Set Vref, RX VrefLevel [Byte0]: 48
8699 22:13:11.686773 [Byte1]: 48
8700 22:13:11.691165
8701 22:13:11.691633 Set Vref, RX VrefLevel [Byte0]: 49
8702 22:13:11.694854 [Byte1]: 49
8703 22:13:11.698976
8704 22:13:11.699681 Set Vref, RX VrefLevel [Byte0]: 50
8705 22:13:11.702044 [Byte1]: 50
8706 22:13:11.706148
8707 22:13:11.706576 Set Vref, RX VrefLevel [Byte0]: 51
8708 22:13:11.710061 [Byte1]: 51
8709 22:13:11.714321
8710 22:13:11.714919 Set Vref, RX VrefLevel [Byte0]: 52
8711 22:13:11.717221 [Byte1]: 52
8712 22:13:11.721397
8713 22:13:11.721924 Set Vref, RX VrefLevel [Byte0]: 53
8714 22:13:11.725027 [Byte1]: 53
8715 22:13:11.729644
8716 22:13:11.730144 Set Vref, RX VrefLevel [Byte0]: 54
8717 22:13:11.732262 [Byte1]: 54
8718 22:13:11.737192
8719 22:13:11.737611 Set Vref, RX VrefLevel [Byte0]: 55
8720 22:13:11.740531 [Byte1]: 55
8721 22:13:11.744368
8722 22:13:11.744781 Set Vref, RX VrefLevel [Byte0]: 56
8723 22:13:11.747713 [Byte1]: 56
8724 22:13:11.752103
8725 22:13:11.752517 Set Vref, RX VrefLevel [Byte0]: 57
8726 22:13:11.755825 [Byte1]: 57
8727 22:13:11.760127
8728 22:13:11.760690 Set Vref, RX VrefLevel [Byte0]: 58
8729 22:13:11.763330 [Byte1]: 58
8730 22:13:11.767647
8731 22:13:11.768227 Set Vref, RX VrefLevel [Byte0]: 59
8732 22:13:11.770634 [Byte1]: 59
8733 22:13:11.775181
8734 22:13:11.775811 Set Vref, RX VrefLevel [Byte0]: 60
8735 22:13:11.778172 [Byte1]: 60
8736 22:13:11.782664
8737 22:13:11.783125 Set Vref, RX VrefLevel [Byte0]: 61
8738 22:13:11.786216 [Byte1]: 61
8739 22:13:11.790337
8740 22:13:11.790799 Set Vref, RX VrefLevel [Byte0]: 62
8741 22:13:11.793562 [Byte1]: 62
8742 22:13:11.797633
8743 22:13:11.798093 Set Vref, RX VrefLevel [Byte0]: 63
8744 22:13:11.801223 [Byte1]: 63
8745 22:13:11.805393
8746 22:13:11.805856 Set Vref, RX VrefLevel [Byte0]: 64
8747 22:13:11.808480 [Byte1]: 64
8748 22:13:11.813522
8749 22:13:11.813982 Set Vref, RX VrefLevel [Byte0]: 65
8750 22:13:11.816580 [Byte1]: 65
8751 22:13:11.820734
8752 22:13:11.821380 Set Vref, RX VrefLevel [Byte0]: 66
8753 22:13:11.823750 [Byte1]: 66
8754 22:13:11.828157
8755 22:13:11.828617 Set Vref, RX VrefLevel [Byte0]: 67
8756 22:13:11.831756 [Byte1]: 67
8757 22:13:11.836215
8758 22:13:11.836722 Set Vref, RX VrefLevel [Byte0]: 68
8759 22:13:11.838923 [Byte1]: 68
8760 22:13:11.843643
8761 22:13:11.844119 Set Vref, RX VrefLevel [Byte0]: 69
8762 22:13:11.846736 [Byte1]: 69
8763 22:13:11.851213
8764 22:13:11.851731 Set Vref, RX VrefLevel [Byte0]: 70
8765 22:13:11.854787 [Byte1]: 70
8766 22:13:11.858633
8767 22:13:11.858965 Set Vref, RX VrefLevel [Byte0]: 71
8768 22:13:11.861520 [Byte1]: 71
8769 22:13:11.866567
8770 22:13:11.866852 Final RX Vref Byte 0 = 59 to rank0
8771 22:13:11.869423 Final RX Vref Byte 1 = 51 to rank0
8772 22:13:11.872558 Final RX Vref Byte 0 = 59 to rank1
8773 22:13:11.875810 Final RX Vref Byte 1 = 51 to rank1==
8774 22:13:11.879534 Dram Type= 6, Freq= 0, CH_1, rank 0
8775 22:13:11.886095 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8776 22:13:11.886346 ==
8777 22:13:11.886598 DQS Delay:
8778 22:13:11.888848 DQS0 = 0, DQS1 = 0
8779 22:13:11.889099 DQM Delay:
8780 22:13:11.889350 DQM0 = 131, DQM1 = 124
8781 22:13:11.892369 DQ Delay:
8782 22:13:11.895970 DQ0 =136, DQ1 =126, DQ2 =120, DQ3 =126
8783 22:13:11.898917 DQ4 =130, DQ5 =142, DQ6 =142, DQ7 =128
8784 22:13:11.902714 DQ8 =112, DQ9 =114, DQ10 =122, DQ11 =118
8785 22:13:11.905653 DQ12 =134, DQ13 =130, DQ14 =134, DQ15 =134
8786 22:13:11.905897
8787 22:13:11.906091
8788 22:13:11.906271
8789 22:13:11.908659 [DramC_TX_OE_Calibration] TA2
8790 22:13:11.912178 Original DQ_B0 (3 6) =30, OEN = 27
8791 22:13:11.915395 Original DQ_B1 (3 6) =30, OEN = 27
8792 22:13:11.918900 24, 0x0, End_B0=24 End_B1=24
8793 22:13:11.922171 25, 0x0, End_B0=25 End_B1=25
8794 22:13:11.922418 26, 0x0, End_B0=26 End_B1=26
8795 22:13:11.925433 27, 0x0, End_B0=27 End_B1=27
8796 22:13:11.929272 28, 0x0, End_B0=28 End_B1=28
8797 22:13:11.931800 29, 0x0, End_B0=29 End_B1=29
8798 22:13:11.932047 30, 0x0, End_B0=30 End_B1=30
8799 22:13:11.935363 31, 0x4141, End_B0=30 End_B1=30
8800 22:13:11.938511 Byte0 end_step=30 best_step=27
8801 22:13:11.941650 Byte1 end_step=30 best_step=27
8802 22:13:11.945202 Byte0 TX OE(2T, 0.5T) = (3, 3)
8803 22:13:11.948421 Byte1 TX OE(2T, 0.5T) = (3, 3)
8804 22:13:11.948666
8805 22:13:11.948860
8806 22:13:11.954848 [DQSOSCAuto] RK0, (LSB)MR18= 0x80d, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 405 ps
8807 22:13:11.958127 CH1 RK0: MR19=303, MR18=80D
8808 22:13:11.965028 CH1_RK0: MR19=0x303, MR18=0x80D, DQSOSC=403, MR23=63, INC=22, DEC=15
8809 22:13:11.965412
8810 22:13:11.968024 ----->DramcWriteLeveling(PI) begin...
8811 22:13:11.968299 ==
8812 22:13:11.971650 Dram Type= 6, Freq= 0, CH_1, rank 1
8813 22:13:11.974837 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8814 22:13:11.975148 ==
8815 22:13:11.977925 Write leveling (Byte 0): 23 => 23
8816 22:13:11.981465 Write leveling (Byte 1): 27 => 27
8817 22:13:11.984689 DramcWriteLeveling(PI) end<-----
8818 22:13:11.985017
8819 22:13:11.985297 ==
8820 22:13:11.988318 Dram Type= 6, Freq= 0, CH_1, rank 1
8821 22:13:11.991258 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8822 22:13:11.994608 ==
8823 22:13:11.994980 [Gating] SW mode calibration
8824 22:13:12.004932 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8825 22:13:12.008042 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8826 22:13:12.010972 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8827 22:13:12.017823 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8828 22:13:12.020732 1 4 8 | B1->B0 | 2323 3433 | 0 1 | (0 0) (0 0)
8829 22:13:12.024669 1 4 12 | B1->B0 | 2f2e 3434 | 1 1 | (0 0) (1 1)
8830 22:13:12.031189 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8831 22:13:12.034342 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8832 22:13:12.037233 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8833 22:13:12.044217 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8834 22:13:12.047191 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8835 22:13:12.050757 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8836 22:13:12.057144 1 5 8 | B1->B0 | 3434 2d2d | 1 0 | (1 0) (0 1)
8837 22:13:12.060376 1 5 12 | B1->B0 | 2929 2424 | 0 0 | (1 0) (0 0)
8838 22:13:12.063707 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8839 22:13:12.070285 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8840 22:13:12.073770 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8841 22:13:12.077561 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8842 22:13:12.083656 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8843 22:13:12.087026 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8844 22:13:12.090924 1 6 8 | B1->B0 | 2b2b 4545 | 0 0 | (0 0) (0 0)
8845 22:13:12.096688 1 6 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
8846 22:13:12.099876 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8847 22:13:12.103318 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8848 22:13:12.110496 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8849 22:13:12.113476 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8850 22:13:12.117089 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8851 22:13:12.123648 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8852 22:13:12.126872 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8853 22:13:12.129982 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8854 22:13:12.136994 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8855 22:13:12.140172 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8856 22:13:12.143365 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8857 22:13:12.150057 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8858 22:13:12.153700 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8859 22:13:12.156610 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8860 22:13:12.163255 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8861 22:13:12.166806 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8862 22:13:12.170130 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8863 22:13:12.176296 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8864 22:13:12.179747 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8865 22:13:12.182459 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8866 22:13:12.189658 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8867 22:13:12.192718 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8868 22:13:12.196408 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8869 22:13:12.202663 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8870 22:13:12.205703 Total UI for P1: 0, mck2ui 16
8871 22:13:12.208829 best dqsien dly found for B0: ( 1, 9, 8)
8872 22:13:12.212109 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8873 22:13:12.215940 Total UI for P1: 0, mck2ui 16
8874 22:13:12.219078 best dqsien dly found for B1: ( 1, 9, 10)
8875 22:13:12.221921 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8876 22:13:12.225951 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8877 22:13:12.226515
8878 22:13:12.228994 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8879 22:13:12.235621 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8880 22:13:12.236092 [Gating] SW calibration Done
8881 22:13:12.236465 ==
8882 22:13:12.239068 Dram Type= 6, Freq= 0, CH_1, rank 1
8883 22:13:12.245158 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8884 22:13:12.245629 ==
8885 22:13:12.245999 RX Vref Scan: 0
8886 22:13:12.246349
8887 22:13:12.248806 RX Vref 0 -> 0, step: 1
8888 22:13:12.249267
8889 22:13:12.251880 RX Delay 0 -> 252, step: 8
8890 22:13:12.255629 iDelay=200, Bit 0, Center 135 (72 ~ 199) 128
8891 22:13:12.258588 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8892 22:13:12.261804 iDelay=200, Bit 2, Center 115 (56 ~ 175) 120
8893 22:13:12.268104 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8894 22:13:12.271707 iDelay=200, Bit 4, Center 123 (64 ~ 183) 120
8895 22:13:12.274693 iDelay=200, Bit 5, Center 139 (80 ~ 199) 120
8896 22:13:12.278208 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8897 22:13:12.281372 iDelay=200, Bit 7, Center 127 (64 ~ 191) 128
8898 22:13:12.288171 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8899 22:13:12.290983 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8900 22:13:12.294395 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8901 22:13:12.298237 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8902 22:13:12.301139 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8903 22:13:12.307795 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8904 22:13:12.311173 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8905 22:13:12.314567 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8906 22:13:12.315151 ==
8907 22:13:12.317822 Dram Type= 6, Freq= 0, CH_1, rank 1
8908 22:13:12.320977 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8909 22:13:12.324425 ==
8910 22:13:12.324893 DQS Delay:
8911 22:13:12.325263 DQS0 = 0, DQS1 = 0
8912 22:13:12.327667 DQM Delay:
8913 22:13:12.328132 DQM0 = 129, DQM1 = 127
8914 22:13:12.330984 DQ Delay:
8915 22:13:12.333834 DQ0 =135, DQ1 =127, DQ2 =115, DQ3 =131
8916 22:13:12.337734 DQ4 =123, DQ5 =139, DQ6 =139, DQ7 =127
8917 22:13:12.340589 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8918 22:13:12.344430 DQ12 =131, DQ13 =139, DQ14 =131, DQ15 =135
8919 22:13:12.345022
8920 22:13:12.345402
8921 22:13:12.345747 ==
8922 22:13:12.347365 Dram Type= 6, Freq= 0, CH_1, rank 1
8923 22:13:12.350731 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8924 22:13:12.351202 ==
8925 22:13:12.353681
8926 22:13:12.354139
8927 22:13:12.354507 TX Vref Scan disable
8928 22:13:12.357548 == TX Byte 0 ==
8929 22:13:12.360610 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8930 22:13:12.364265 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8931 22:13:12.367065 == TX Byte 1 ==
8932 22:13:12.370663 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8933 22:13:12.373940 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8934 22:13:12.376997 ==
8935 22:13:12.377564 Dram Type= 6, Freq= 0, CH_1, rank 1
8936 22:13:12.383421 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8937 22:13:12.383932 ==
8938 22:13:12.397142
8939 22:13:12.400407 TX Vref early break, caculate TX vref
8940 22:13:12.403556 TX Vref=16, minBit 0, minWin=23, winSum=384
8941 22:13:12.407307 TX Vref=18, minBit 0, minWin=22, winSum=391
8942 22:13:12.410234 TX Vref=20, minBit 0, minWin=23, winSum=403
8943 22:13:12.413306 TX Vref=22, minBit 0, minWin=24, winSum=408
8944 22:13:12.417089 TX Vref=24, minBit 0, minWin=24, winSum=418
8945 22:13:12.423449 TX Vref=26, minBit 0, minWin=25, winSum=422
8946 22:13:12.426744 TX Vref=28, minBit 5, minWin=24, winSum=422
8947 22:13:12.430351 TX Vref=30, minBit 0, minWin=24, winSum=418
8948 22:13:12.433474 TX Vref=32, minBit 5, minWin=23, winSum=407
8949 22:13:12.436518 TX Vref=34, minBit 5, minWin=22, winSum=402
8950 22:13:12.443327 TX Vref=36, minBit 0, minWin=23, winSum=393
8951 22:13:12.446351 [TxChooseVref] Worse bit 0, Min win 25, Win sum 422, Final Vref 26
8952 22:13:12.446826
8953 22:13:12.449920 Final TX Range 0 Vref 26
8954 22:13:12.450471
8955 22:13:12.450845 ==
8956 22:13:12.452652 Dram Type= 6, Freq= 0, CH_1, rank 1
8957 22:13:12.456529 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8958 22:13:12.459713 ==
8959 22:13:12.460267
8960 22:13:12.460636
8961 22:13:12.460981 TX Vref Scan disable
8962 22:13:12.466331 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8963 22:13:12.466894 == TX Byte 0 ==
8964 22:13:12.469420 u2DelayCellOfst[0]=18 cells (5 PI)
8965 22:13:12.473058 u2DelayCellOfst[1]=11 cells (3 PI)
8966 22:13:12.476100 u2DelayCellOfst[2]=0 cells (0 PI)
8967 22:13:12.479549 u2DelayCellOfst[3]=7 cells (2 PI)
8968 22:13:12.482541 u2DelayCellOfst[4]=7 cells (2 PI)
8969 22:13:12.485920 u2DelayCellOfst[5]=26 cells (7 PI)
8970 22:13:12.489373 u2DelayCellOfst[6]=18 cells (5 PI)
8971 22:13:12.492520 u2DelayCellOfst[7]=7 cells (2 PI)
8972 22:13:12.495940 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8973 22:13:12.499455 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8974 22:13:12.502685 == TX Byte 1 ==
8975 22:13:12.505922 u2DelayCellOfst[8]=0 cells (0 PI)
8976 22:13:12.508879 u2DelayCellOfst[9]=7 cells (2 PI)
8977 22:13:12.512851 u2DelayCellOfst[10]=15 cells (4 PI)
8978 22:13:12.515679 u2DelayCellOfst[11]=7 cells (2 PI)
8979 22:13:12.519100 u2DelayCellOfst[12]=15 cells (4 PI)
8980 22:13:12.522397 u2DelayCellOfst[13]=18 cells (5 PI)
8981 22:13:12.525702 u2DelayCellOfst[14]=22 cells (6 PI)
8982 22:13:12.526179 u2DelayCellOfst[15]=18 cells (5 PI)
8983 22:13:12.531760 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8984 22:13:12.535440 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8985 22:13:12.538747 DramC Write-DBI on
8986 22:13:12.539309 ==
8987 22:13:12.541933 Dram Type= 6, Freq= 0, CH_1, rank 1
8988 22:13:12.545023 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8989 22:13:12.545491 ==
8990 22:13:12.545862
8991 22:13:12.546205
8992 22:13:12.548733 TX Vref Scan disable
8993 22:13:12.549300 == TX Byte 0 ==
8994 22:13:12.555052 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8995 22:13:12.555519 == TX Byte 1 ==
8996 22:13:12.558636 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8997 22:13:12.561740 DramC Write-DBI off
8998 22:13:12.562299
8999 22:13:12.562730 [DATLAT]
9000 22:13:12.564575 Freq=1600, CH1 RK1
9001 22:13:12.565075
9002 22:13:12.565489 DATLAT Default: 0xf
9003 22:13:12.568190 0, 0xFFFF, sum = 0
9004 22:13:12.572092 1, 0xFFFF, sum = 0
9005 22:13:12.572656 2, 0xFFFF, sum = 0
9006 22:13:12.575022 3, 0xFFFF, sum = 0
9007 22:13:12.575622 4, 0xFFFF, sum = 0
9008 22:13:12.578052 5, 0xFFFF, sum = 0
9009 22:13:12.578616 6, 0xFFFF, sum = 0
9010 22:13:12.581440 7, 0xFFFF, sum = 0
9011 22:13:12.581991 8, 0xFFFF, sum = 0
9012 22:13:12.584659 9, 0xFFFF, sum = 0
9013 22:13:12.585224 10, 0xFFFF, sum = 0
9014 22:13:12.587879 11, 0xFFFF, sum = 0
9015 22:13:12.588353 12, 0xFFFF, sum = 0
9016 22:13:12.591175 13, 0x8FFF, sum = 0
9017 22:13:12.591686 14, 0x0, sum = 1
9018 22:13:12.594625 15, 0x0, sum = 2
9019 22:13:12.595094 16, 0x0, sum = 3
9020 22:13:12.598301 17, 0x0, sum = 4
9021 22:13:12.598868 best_step = 15
9022 22:13:12.599237
9023 22:13:12.599617 ==
9024 22:13:12.601295 Dram Type= 6, Freq= 0, CH_1, rank 1
9025 22:13:12.607942 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9026 22:13:12.608469 ==
9027 22:13:12.608842 RX Vref Scan: 0
9028 22:13:12.609189
9029 22:13:12.610787 RX Vref 0 -> 0, step: 1
9030 22:13:12.611269
9031 22:13:12.614553 RX Delay 11 -> 252, step: 4
9032 22:13:12.617557 iDelay=195, Bit 0, Center 134 (79 ~ 190) 112
9033 22:13:12.621055 iDelay=195, Bit 1, Center 126 (75 ~ 178) 104
9034 22:13:12.627409 iDelay=195, Bit 2, Center 114 (59 ~ 170) 112
9035 22:13:12.630685 iDelay=195, Bit 3, Center 126 (71 ~ 182) 112
9036 22:13:12.633833 iDelay=195, Bit 4, Center 124 (67 ~ 182) 116
9037 22:13:12.637147 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
9038 22:13:12.640838 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
9039 22:13:12.647378 iDelay=195, Bit 7, Center 124 (67 ~ 182) 116
9040 22:13:12.650289 iDelay=195, Bit 8, Center 110 (55 ~ 166) 112
9041 22:13:12.654164 iDelay=195, Bit 9, Center 114 (59 ~ 170) 112
9042 22:13:12.656985 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
9043 22:13:12.660719 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
9044 22:13:12.667008 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
9045 22:13:12.670557 iDelay=195, Bit 13, Center 134 (79 ~ 190) 112
9046 22:13:12.673813 iDelay=195, Bit 14, Center 130 (75 ~ 186) 112
9047 22:13:12.676761 iDelay=195, Bit 15, Center 134 (79 ~ 190) 112
9048 22:13:12.677335 ==
9049 22:13:12.680530 Dram Type= 6, Freq= 0, CH_1, rank 1
9050 22:13:12.686856 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9051 22:13:12.687335 ==
9052 22:13:12.687742 DQS Delay:
9053 22:13:12.690175 DQS0 = 0, DQS1 = 0
9054 22:13:12.690644 DQM Delay:
9055 22:13:12.691065 DQM0 = 128, DQM1 = 125
9056 22:13:12.693445 DQ Delay:
9057 22:13:12.696717 DQ0 =134, DQ1 =126, DQ2 =114, DQ3 =126
9058 22:13:12.700131 DQ4 =124, DQ5 =138, DQ6 =138, DQ7 =124
9059 22:13:12.703488 DQ8 =110, DQ9 =114, DQ10 =128, DQ11 =120
9060 22:13:12.706807 DQ12 =132, DQ13 =134, DQ14 =130, DQ15 =134
9061 22:13:12.707278
9062 22:13:12.707699
9063 22:13:12.708060
9064 22:13:12.709810 [DramC_TX_OE_Calibration] TA2
9065 22:13:12.713395 Original DQ_B0 (3 6) =30, OEN = 27
9066 22:13:12.717019 Original DQ_B1 (3 6) =30, OEN = 27
9067 22:13:12.719529 24, 0x0, End_B0=24 End_B1=24
9068 22:13:12.723144 25, 0x0, End_B0=25 End_B1=25
9069 22:13:12.723760 26, 0x0, End_B0=26 End_B1=26
9070 22:13:12.726729 27, 0x0, End_B0=27 End_B1=27
9071 22:13:12.729833 28, 0x0, End_B0=28 End_B1=28
9072 22:13:12.733056 29, 0x0, End_B0=29 End_B1=29
9073 22:13:12.733568 30, 0x0, End_B0=30 End_B1=30
9074 22:13:12.736325 31, 0x4141, End_B0=30 End_B1=30
9075 22:13:12.739980 Byte0 end_step=30 best_step=27
9076 22:13:12.743122 Byte1 end_step=30 best_step=27
9077 22:13:12.746417 Byte0 TX OE(2T, 0.5T) = (3, 3)
9078 22:13:12.749861 Byte1 TX OE(2T, 0.5T) = (3, 3)
9079 22:13:12.750510
9080 22:13:12.750893
9081 22:13:12.756465 [DQSOSCAuto] RK1, (LSB)MR18= 0x121f, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 400 ps
9082 22:13:12.760002 CH1 RK1: MR19=303, MR18=121F
9083 22:13:12.766178 CH1_RK1: MR19=0x303, MR18=0x121F, DQSOSC=394, MR23=63, INC=23, DEC=15
9084 22:13:12.769242 [RxdqsGatingPostProcess] freq 1600
9085 22:13:12.776031 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9086 22:13:12.776600 best DQS0 dly(2T, 0.5T) = (1, 1)
9087 22:13:12.779489 best DQS1 dly(2T, 0.5T) = (1, 1)
9088 22:13:12.782332 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9089 22:13:12.786038 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9090 22:13:12.789167 best DQS0 dly(2T, 0.5T) = (1, 1)
9091 22:13:12.792576 best DQS1 dly(2T, 0.5T) = (1, 1)
9092 22:13:12.795747 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9093 22:13:12.798852 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9094 22:13:12.802252 Pre-setting of DQS Precalculation
9095 22:13:12.805307 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9096 22:13:12.815446 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9097 22:13:12.822044 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9098 22:13:12.822606
9099 22:13:12.822974
9100 22:13:12.825083 [Calibration Summary] 3200 Mbps
9101 22:13:12.825591 CH 0, Rank 0
9102 22:13:12.828501 SW Impedance : PASS
9103 22:13:12.829019 DUTY Scan : NO K
9104 22:13:12.832182 ZQ Calibration : PASS
9105 22:13:12.835227 Jitter Meter : NO K
9106 22:13:12.835829 CBT Training : PASS
9107 22:13:12.839027 Write leveling : PASS
9108 22:13:12.841940 RX DQS gating : PASS
9109 22:13:12.842415 RX DQ/DQS(RDDQC) : PASS
9110 22:13:12.845179 TX DQ/DQS : PASS
9111 22:13:12.848648 RX DATLAT : PASS
9112 22:13:12.849117 RX DQ/DQS(Engine): PASS
9113 22:13:12.851971 TX OE : PASS
9114 22:13:12.852442 All Pass.
9115 22:13:12.852819
9116 22:13:12.855329 CH 0, Rank 1
9117 22:13:12.855846 SW Impedance : PASS
9118 22:13:12.858111 DUTY Scan : NO K
9119 22:13:12.862173 ZQ Calibration : PASS
9120 22:13:12.862756 Jitter Meter : NO K
9121 22:13:12.865244 CBT Training : PASS
9122 22:13:12.868043 Write leveling : PASS
9123 22:13:12.868514 RX DQS gating : PASS
9124 22:13:12.871886 RX DQ/DQS(RDDQC) : PASS
9125 22:13:12.872570 TX DQ/DQS : PASS
9126 22:13:12.875515 RX DATLAT : PASS
9127 22:13:12.878558 RX DQ/DQS(Engine): PASS
9128 22:13:12.879136 TX OE : PASS
9129 22:13:12.882032 All Pass.
9130 22:13:12.882523
9131 22:13:12.882900 CH 1, Rank 0
9132 22:13:12.884896 SW Impedance : PASS
9133 22:13:12.885368 DUTY Scan : NO K
9134 22:13:12.888775 ZQ Calibration : PASS
9135 22:13:12.891972 Jitter Meter : NO K
9136 22:13:12.892550 CBT Training : PASS
9137 22:13:12.894919 Write leveling : PASS
9138 22:13:12.898454 RX DQS gating : PASS
9139 22:13:12.899029 RX DQ/DQS(RDDQC) : PASS
9140 22:13:12.901325 TX DQ/DQS : PASS
9141 22:13:12.904527 RX DATLAT : PASS
9142 22:13:12.905112 RX DQ/DQS(Engine): PASS
9143 22:13:12.907923 TX OE : PASS
9144 22:13:12.908523 All Pass.
9145 22:13:12.908906
9146 22:13:12.911241 CH 1, Rank 1
9147 22:13:12.911830 SW Impedance : PASS
9148 22:13:12.914767 DUTY Scan : NO K
9149 22:13:12.917990 ZQ Calibration : PASS
9150 22:13:12.918552 Jitter Meter : NO K
9151 22:13:12.921176 CBT Training : PASS
9152 22:13:12.924144 Write leveling : PASS
9153 22:13:12.924625 RX DQS gating : PASS
9154 22:13:12.927795 RX DQ/DQS(RDDQC) : PASS
9155 22:13:12.930760 TX DQ/DQS : PASS
9156 22:13:12.931228 RX DATLAT : PASS
9157 22:13:12.933990 RX DQ/DQS(Engine): PASS
9158 22:13:12.937904 TX OE : PASS
9159 22:13:12.938372 All Pass.
9160 22:13:12.938742
9161 22:13:12.939085 DramC Write-DBI on
9162 22:13:12.940973 PER_BANK_REFRESH: Hybrid Mode
9163 22:13:12.944061 TX_TRACKING: ON
9164 22:13:12.951707 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9165 22:13:12.961122 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9166 22:13:12.967727 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9167 22:13:12.971250 [FAST_K] Save calibration result to emmc
9168 22:13:12.974087 sync common calibartion params.
9169 22:13:12.977556 sync cbt_mode0:1, 1:1
9170 22:13:12.978134 dram_init: ddr_geometry: 2
9171 22:13:12.980457 dram_init: ddr_geometry: 2
9172 22:13:12.984082 dram_init: ddr_geometry: 2
9173 22:13:12.984551 0:dram_rank_size:100000000
9174 22:13:12.987280 1:dram_rank_size:100000000
9175 22:13:12.993984 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9176 22:13:12.997052 DFS_SHUFFLE_HW_MODE: ON
9177 22:13:13.000480 dramc_set_vcore_voltage set vcore to 725000
9178 22:13:13.001058 Read voltage for 1600, 0
9179 22:13:13.003748 Vio18 = 0
9180 22:13:13.004325 Vcore = 725000
9181 22:13:13.004705 Vdram = 0
9182 22:13:13.006675 Vddq = 0
9183 22:13:13.007168 Vmddr = 0
9184 22:13:13.010069 switch to 3200 Mbps bootup
9185 22:13:13.010539 [DramcRunTimeConfig]
9186 22:13:13.010912 PHYPLL
9187 22:13:13.013779 DPM_CONTROL_AFTERK: ON
9188 22:13:13.016609 PER_BANK_REFRESH: ON
9189 22:13:13.020037 REFRESH_OVERHEAD_REDUCTION: ON
9190 22:13:13.020615 CMD_PICG_NEW_MODE: OFF
9191 22:13:13.023268 XRTWTW_NEW_MODE: ON
9192 22:13:13.023879 XRTRTR_NEW_MODE: ON
9193 22:13:13.026517 TX_TRACKING: ON
9194 22:13:13.027001 RDSEL_TRACKING: OFF
9195 22:13:13.030139 DQS Precalculation for DVFS: ON
9196 22:13:13.033190 RX_TRACKING: OFF
9197 22:13:13.033678 HW_GATING DBG: ON
9198 22:13:13.036411 ZQCS_ENABLE_LP4: ON
9199 22:13:13.036897 RX_PICG_NEW_MODE: ON
9200 22:13:13.039694 TX_PICG_NEW_MODE: ON
9201 22:13:13.040182 ENABLE_RX_DCM_DPHY: ON
9202 22:13:13.043129 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9203 22:13:13.046279 DUMMY_READ_FOR_TRACKING: OFF
9204 22:13:13.050056 !!! SPM_CONTROL_AFTERK: OFF
9205 22:13:13.053398 !!! SPM could not control APHY
9206 22:13:13.053982 IMPEDANCE_TRACKING: ON
9207 22:13:13.056541 TEMP_SENSOR: ON
9208 22:13:13.057028 HW_SAVE_FOR_SR: OFF
9209 22:13:13.059259 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9210 22:13:13.062583 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9211 22:13:13.066173 Read ODT Tracking: ON
9212 22:13:13.069479 Refresh Rate DeBounce: ON
9213 22:13:13.070064 DFS_NO_QUEUE_FLUSH: ON
9214 22:13:13.072878 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9215 22:13:13.076481 ENABLE_DFS_RUNTIME_MRW: OFF
9216 22:13:13.079066 DDR_RESERVE_NEW_MODE: ON
9217 22:13:13.079607 MR_CBT_SWITCH_FREQ: ON
9218 22:13:13.082499 =========================
9219 22:13:13.101747 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9220 22:13:13.104502 dram_init: ddr_geometry: 2
9221 22:13:13.123125 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9222 22:13:13.126362 dram_init: dram init end (result: 0)
9223 22:13:13.133184 DRAM-K: Full calibration passed in 24586 msecs
9224 22:13:13.136204 MRC: failed to locate region type 0.
9225 22:13:13.136678 DRAM rank0 size:0x100000000,
9226 22:13:13.139317 DRAM rank1 size=0x100000000
9227 22:13:13.149360 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9228 22:13:13.156179 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9229 22:13:13.163002 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9230 22:13:13.172557 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9231 22:13:13.173117 DRAM rank0 size:0x100000000,
9232 22:13:13.176114 DRAM rank1 size=0x100000000
9233 22:13:13.176669 CBMEM:
9234 22:13:13.179554 IMD: root @ 0xfffff000 254 entries.
9235 22:13:13.182127 IMD: root @ 0xffffec00 62 entries.
9236 22:13:13.185716 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9237 22:13:13.192252 WARNING: RO_VPD is uninitialized or empty.
9238 22:13:13.195690 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9239 22:13:13.203621 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9240 22:13:13.216454 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9241 22:13:13.227425 BS: romstage times (exec / console): total (unknown) / 24049 ms
9242 22:13:13.228074
9243 22:13:13.228453
9244 22:13:13.237208 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9245 22:13:13.240714 ARM64: Exception handlers installed.
9246 22:13:13.243872 ARM64: Testing exception
9247 22:13:13.247157 ARM64: Done test exception
9248 22:13:13.247668 Enumerating buses...
9249 22:13:13.250590 Show all devs... Before device enumeration.
9250 22:13:13.254026 Root Device: enabled 1
9251 22:13:13.257671 CPU_CLUSTER: 0: enabled 1
9252 22:13:13.258246 CPU: 00: enabled 1
9253 22:13:13.260265 Compare with tree...
9254 22:13:13.260737 Root Device: enabled 1
9255 22:13:13.264195 CPU_CLUSTER: 0: enabled 1
9256 22:13:13.266725 CPU: 00: enabled 1
9257 22:13:13.267200 Root Device scanning...
9258 22:13:13.270150 scan_static_bus for Root Device
9259 22:13:13.273500 CPU_CLUSTER: 0 enabled
9260 22:13:13.277184 scan_static_bus for Root Device done
9261 22:13:13.280345 scan_bus: bus Root Device finished in 8 msecs
9262 22:13:13.280924 done
9263 22:13:13.286899 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9264 22:13:13.290484 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9265 22:13:13.296778 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9266 22:13:13.303385 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9267 22:13:13.304016 Allocating resources...
9268 22:13:13.306240 Reading resources...
9269 22:13:13.310255 Root Device read_resources bus 0 link: 0
9270 22:13:13.313220 DRAM rank0 size:0x100000000,
9271 22:13:13.313793 DRAM rank1 size=0x100000000
9272 22:13:13.319960 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9273 22:13:13.320541 CPU: 00 missing read_resources
9274 22:13:13.326505 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9275 22:13:13.329514 Root Device read_resources bus 0 link: 0 done
9276 22:13:13.333071 Done reading resources.
9277 22:13:13.335778 Show resources in subtree (Root Device)...After reading.
9278 22:13:13.339199 Root Device child on link 0 CPU_CLUSTER: 0
9279 22:13:13.342561 CPU_CLUSTER: 0 child on link 0 CPU: 00
9280 22:13:13.352439 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9281 22:13:13.353191 CPU: 00
9282 22:13:13.359193 Root Device assign_resources, bus 0 link: 0
9283 22:13:13.362783 CPU_CLUSTER: 0 missing set_resources
9284 22:13:13.365441 Root Device assign_resources, bus 0 link: 0 done
9285 22:13:13.368754 Done setting resources.
9286 22:13:13.372396 Show resources in subtree (Root Device)...After assigning values.
9287 22:13:13.375653 Root Device child on link 0 CPU_CLUSTER: 0
9288 22:13:13.382212 CPU_CLUSTER: 0 child on link 0 CPU: 00
9289 22:13:13.388598 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9290 22:13:13.392265 CPU: 00
9291 22:13:13.392982 Done allocating resources.
9292 22:13:13.399020 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9293 22:13:13.399642 Enabling resources...
9294 22:13:13.401884 done.
9295 22:13:13.404799 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9296 22:13:13.407950 Initializing devices...
9297 22:13:13.408422 Root Device init
9298 22:13:13.411241 init hardware done!
9299 22:13:13.414959 0x00000018: ctrlr->caps
9300 22:13:13.415544 52.000 MHz: ctrlr->f_max
9301 22:13:13.417849 0.400 MHz: ctrlr->f_min
9302 22:13:13.421621 0x40ff8080: ctrlr->voltages
9303 22:13:13.422206 sclk: 390625
9304 22:13:13.422586 Bus Width = 1
9305 22:13:13.424391 sclk: 390625
9306 22:13:13.424861 Bus Width = 1
9307 22:13:13.428223 Early init status = 3
9308 22:13:13.431142 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9309 22:13:13.435687 in-header: 03 fc 00 00 01 00 00 00
9310 22:13:13.439041 in-data: 00
9311 22:13:13.441976 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9312 22:13:13.447678 in-header: 03 fd 00 00 00 00 00 00
9313 22:13:13.451288 in-data:
9314 22:13:13.454204 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9315 22:13:13.458700 in-header: 03 fc 00 00 01 00 00 00
9316 22:13:13.462081 in-data: 00
9317 22:13:13.465561 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9318 22:13:13.471235 in-header: 03 fd 00 00 00 00 00 00
9319 22:13:13.474349 in-data:
9320 22:13:13.477349 [SSUSB] Setting up USB HOST controller...
9321 22:13:13.480954 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9322 22:13:13.484010 [SSUSB] phy power-on done.
9323 22:13:13.487750 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9324 22:13:13.493931 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9325 22:13:13.497194 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9326 22:13:13.503778 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9327 22:13:13.510468 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9328 22:13:13.517192 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9329 22:13:13.523570 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9330 22:13:13.529878 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9331 22:13:13.533456 SPM: binary array size = 0x9dc
9332 22:13:13.536622 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9333 22:13:13.543455 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9334 22:13:13.550058 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9335 22:13:13.556705 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9336 22:13:13.559540 configure_display: Starting display init
9337 22:13:13.594012 anx7625_power_on_init: Init interface.
9338 22:13:13.597351 anx7625_disable_pd_protocol: Disabled PD feature.
9339 22:13:13.600864 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9340 22:13:13.628296 anx7625_start_dp_work: Secure OCM version=00
9341 22:13:13.632020 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9342 22:13:13.646478 sp_tx_get_edid_block: EDID Block = 1
9343 22:13:13.749042 Extracted contents:
9344 22:13:13.752099 header: 00 ff ff ff ff ff ff 00
9345 22:13:13.755853 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9346 22:13:13.758680 version: 01 04
9347 22:13:13.762241 basic params: 95 1f 11 78 0a
9348 22:13:13.765474 chroma info: 76 90 94 55 54 90 27 21 50 54
9349 22:13:13.769023 established: 00 00 00
9350 22:13:13.775371 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9351 22:13:13.781973 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9352 22:13:13.785504 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9353 22:13:13.791884 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9354 22:13:13.798420 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9355 22:13:13.801368 extensions: 00
9356 22:13:13.801820 checksum: fb
9357 22:13:13.802182
9358 22:13:13.808079 Manufacturer: IVO Model 57d Serial Number 0
9359 22:13:13.808492 Made week 0 of 2020
9360 22:13:13.811377 EDID version: 1.4
9361 22:13:13.811819 Digital display
9362 22:13:13.814705 6 bits per primary color channel
9363 22:13:13.817927 DisplayPort interface
9364 22:13:13.818355 Maximum image size: 31 cm x 17 cm
9365 22:13:13.821196 Gamma: 220%
9366 22:13:13.821604 Check DPMS levels
9367 22:13:13.827746 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9368 22:13:13.830858 First detailed timing is preferred timing
9369 22:13:13.834169 Established timings supported:
9370 22:13:13.834626 Standard timings supported:
9371 22:13:13.837554 Detailed timings
9372 22:13:13.840648 Hex of detail: 383680a07038204018303c0035ae10000019
9373 22:13:13.847098 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9374 22:13:13.850606 0780 0798 07c8 0820 hborder 0
9375 22:13:13.853719 0438 043b 0447 0458 vborder 0
9376 22:13:13.857325 -hsync -vsync
9377 22:13:13.860096 Did detailed timing
9378 22:13:13.863563 Hex of detail: 000000000000000000000000000000000000
9379 22:13:13.867015 Manufacturer-specified data, tag 0
9380 22:13:13.870417 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9381 22:13:13.874017 ASCII string: InfoVision
9382 22:13:13.876831 Hex of detail: 000000fe00523134304e574635205248200a
9383 22:13:13.880442 ASCII string: R140NWF5 RH
9384 22:13:13.880947 Checksum
9385 22:13:13.883348 Checksum: 0xfb (valid)
9386 22:13:13.886586 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9387 22:13:13.889921 DSI data_rate: 832800000 bps
9388 22:13:13.896789 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9389 22:13:13.900033 anx7625_parse_edid: pixelclock(138800).
9390 22:13:13.903674 hactive(1920), hsync(48), hfp(24), hbp(88)
9391 22:13:13.906476 vactive(1080), vsync(12), vfp(3), vbp(17)
9392 22:13:13.909950 anx7625_dsi_config: config dsi.
9393 22:13:13.916780 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9394 22:13:13.931312 anx7625_dsi_config: success to config DSI
9395 22:13:13.934364 anx7625_dp_start: MIPI phy setup OK.
9396 22:13:13.938231 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9397 22:13:13.941246 mtk_ddp_mode_set invalid vrefresh 60
9398 22:13:13.944306 main_disp_path_setup
9399 22:13:13.944934 ovl_layer_smi_id_en
9400 22:13:13.947942 ovl_layer_smi_id_en
9401 22:13:13.948407 ccorr_config
9402 22:13:13.948798 aal_config
9403 22:13:13.951212 gamma_config
9404 22:13:13.951824 postmask_config
9405 22:13:13.954706 dither_config
9406 22:13:13.957705 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9407 22:13:13.964039 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9408 22:13:13.967566 Root Device init finished in 554 msecs
9409 22:13:13.970554 CPU_CLUSTER: 0 init
9410 22:13:13.977647 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9411 22:13:13.983980 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9412 22:13:13.984560 APU_MBOX 0x190000b0 = 0x10001
9413 22:13:13.987050 APU_MBOX 0x190001b0 = 0x10001
9414 22:13:13.990391 APU_MBOX 0x190005b0 = 0x10001
9415 22:13:13.993654 APU_MBOX 0x190006b0 = 0x10001
9416 22:13:14.000499 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9417 22:13:14.010698 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9418 22:13:14.022589 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9419 22:13:14.029149 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9420 22:13:14.040563 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9421 22:13:14.050359 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9422 22:13:14.053173 CPU_CLUSTER: 0 init finished in 81 msecs
9423 22:13:14.056400 Devices initialized
9424 22:13:14.059408 Show all devs... After init.
9425 22:13:14.059963 Root Device: enabled 1
9426 22:13:14.063389 CPU_CLUSTER: 0: enabled 1
9427 22:13:14.066509 CPU: 00: enabled 1
9428 22:13:14.069260 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9429 22:13:14.073220 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9430 22:13:14.076121 ELOG: NV offset 0x57f000 size 0x1000
9431 22:13:14.083083 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9432 22:13:14.089458 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9433 22:13:14.093194 ELOG: Event(17) added with size 13 at 2023-06-04 22:13:26 UTC
9434 22:13:14.099177 out: cmd=0x121: 03 db 21 01 00 00 00 00
9435 22:13:14.102842 in-header: 03 48 00 00 2c 00 00 00
9436 22:13:14.112404 in-data: 16 69 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9437 22:13:14.119003 ELOG: Event(A1) added with size 10 at 2023-06-04 22:13:26 UTC
9438 22:13:14.125387 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9439 22:13:14.132387 ELOG: Event(A0) added with size 9 at 2023-06-04 22:13:26 UTC
9440 22:13:14.135702 elog_add_boot_reason: Logged dev mode boot
9441 22:13:14.142218 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9442 22:13:14.142683 Finalize devices...
9443 22:13:14.145390 Devices finalized
9444 22:13:14.148499 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9445 22:13:14.152099 Writing coreboot table at 0xffe64000
9446 22:13:14.155708 0. 000000000010a000-0000000000113fff: RAMSTAGE
9447 22:13:14.162223 1. 0000000040000000-00000000400fffff: RAM
9448 22:13:14.165712 2. 0000000040100000-000000004032afff: RAMSTAGE
9449 22:13:14.168394 3. 000000004032b000-00000000545fffff: RAM
9450 22:13:14.171967 4. 0000000054600000-000000005465ffff: BL31
9451 22:13:14.175335 5. 0000000054660000-00000000ffe63fff: RAM
9452 22:13:14.182098 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9453 22:13:14.185470 7. 0000000100000000-000000023fffffff: RAM
9454 22:13:14.188464 Passing 5 GPIOs to payload:
9455 22:13:14.192004 NAME | PORT | POLARITY | VALUE
9456 22:13:14.197948 EC in RW | 0x000000aa | low | undefined
9457 22:13:14.201290 EC interrupt | 0x00000005 | low | undefined
9458 22:13:14.207857 TPM interrupt | 0x000000ab | high | undefined
9459 22:13:14.211397 SD card detect | 0x00000011 | high | undefined
9460 22:13:14.215345 speaker enable | 0x00000093 | high | undefined
9461 22:13:14.218220 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9462 22:13:14.221893 in-header: 03 f9 00 00 02 00 00 00
9463 22:13:14.224830 in-data: 02 00
9464 22:13:14.228381 ADC[4]: Raw value=897040 ID=7
9465 22:13:14.231205 ADC[3]: Raw value=213070 ID=1
9466 22:13:14.231788 RAM Code: 0x71
9467 22:13:14.234370 ADC[6]: Raw value=74722 ID=0
9468 22:13:14.238232 ADC[5]: Raw value=212330 ID=1
9469 22:13:14.238696 SKU Code: 0x1
9470 22:13:14.244678 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 7dbf
9471 22:13:14.245232 coreboot table: 964 bytes.
9472 22:13:14.247755 IMD ROOT 0. 0xfffff000 0x00001000
9473 22:13:14.250809 IMD SMALL 1. 0xffffe000 0x00001000
9474 22:13:14.254592 RO MCACHE 2. 0xffffc000 0x00001104
9475 22:13:14.258067 CONSOLE 3. 0xfff7c000 0x00080000
9476 22:13:14.260843 FMAP 4. 0xfff7b000 0x00000452
9477 22:13:14.264488 TIME STAMP 5. 0xfff7a000 0x00000910
9478 22:13:14.267389 VBOOT WORK 6. 0xfff66000 0x00014000
9479 22:13:14.271083 RAMOOPS 7. 0xffe66000 0x00100000
9480 22:13:14.274077 COREBOOT 8. 0xffe64000 0x00002000
9481 22:13:14.277466 IMD small region:
9482 22:13:14.280297 IMD ROOT 0. 0xffffec00 0x00000400
9483 22:13:14.283959 VPD 1. 0xffffeba0 0x0000004c
9484 22:13:14.287215 MMC STATUS 2. 0xffffeb80 0x00000004
9485 22:13:14.293840 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9486 22:13:14.294452 Probing TPM: done!
9487 22:13:14.300948 Connected to device vid:did:rid of 1ae0:0028:00
9488 22:13:14.307320 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9489 22:13:14.311048 Initialized TPM device CR50 revision 0
9490 22:13:14.314069 Checking cr50 for pending updates
9491 22:13:14.319961 Reading cr50 TPM mode
9492 22:13:14.328432 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9493 22:13:14.335181 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9494 22:13:14.375060 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9495 22:13:14.378338 Checking segment from ROM address 0x40100000
9496 22:13:14.381926 Checking segment from ROM address 0x4010001c
9497 22:13:14.388530 Loading segment from ROM address 0x40100000
9498 22:13:14.389096 code (compression=0)
9499 22:13:14.398280 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9500 22:13:14.404737 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9501 22:13:14.405306 it's not compressed!
9502 22:13:14.411316 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9503 22:13:14.418141 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9504 22:13:14.435207 Loading segment from ROM address 0x4010001c
9505 22:13:14.435825 Entry Point 0x80000000
9506 22:13:14.438530 Loaded segments
9507 22:13:14.441694 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9508 22:13:14.448369 Jumping to boot code at 0x80000000(0xffe64000)
9509 22:13:14.455666 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9510 22:13:14.461602 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9511 22:13:14.469482 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9512 22:13:14.473342 Checking segment from ROM address 0x40100000
9513 22:13:14.476707 Checking segment from ROM address 0x4010001c
9514 22:13:14.483285 Loading segment from ROM address 0x40100000
9515 22:13:14.483891 code (compression=1)
9516 22:13:14.490196 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9517 22:13:14.500095 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9518 22:13:14.500664 using LZMA
9519 22:13:14.508454 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9520 22:13:14.514785 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9521 22:13:14.518297 Loading segment from ROM address 0x4010001c
9522 22:13:14.518866 Entry Point 0x54601000
9523 22:13:14.521162 Loaded segments
9524 22:13:14.524750 NOTICE: MT8192 bl31_setup
9525 22:13:14.531800 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9526 22:13:14.534801 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9527 22:13:14.538321 WARNING: region 0:
9528 22:13:14.542036 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9529 22:13:14.542504 WARNING: region 1:
9530 22:13:14.548137 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9531 22:13:14.551700 WARNING: region 2:
9532 22:13:14.555106 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9533 22:13:14.558521 WARNING: region 3:
9534 22:13:14.561535 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9535 22:13:14.564777 WARNING: region 4:
9536 22:13:14.571718 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9537 22:13:14.572294 WARNING: region 5:
9538 22:13:14.575057 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9539 22:13:14.577922 WARNING: region 6:
9540 22:13:14.581805 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9541 22:13:14.584570 WARNING: region 7:
9542 22:13:14.587775 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9543 22:13:14.595258 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9544 22:13:14.598444 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9545 22:13:14.601288 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9546 22:13:14.608025 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9547 22:13:14.611731 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9548 22:13:14.618246 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9549 22:13:14.621364 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9550 22:13:14.624486 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9551 22:13:14.631230 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9552 22:13:14.634350 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9553 22:13:14.637999 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9554 22:13:14.644735 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9555 22:13:14.647985 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9556 22:13:14.654844 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9557 22:13:14.657670 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9558 22:13:14.661430 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9559 22:13:14.667409 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9560 22:13:14.670847 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9561 22:13:14.674262 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9562 22:13:14.681055 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9563 22:13:14.684556 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9564 22:13:14.690527 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9565 22:13:14.693950 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9566 22:13:14.697906 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9567 22:13:14.704489 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9568 22:13:14.707061 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9569 22:13:14.714158 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9570 22:13:14.717859 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9571 22:13:14.723739 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9572 22:13:14.727181 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9573 22:13:14.730428 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9574 22:13:14.736959 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9575 22:13:14.740266 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9576 22:13:14.743541 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9577 22:13:14.746948 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9578 22:13:14.753607 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9579 22:13:14.756831 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9580 22:13:14.760632 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9581 22:13:14.763541 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9582 22:13:14.770300 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9583 22:13:14.773630 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9584 22:13:14.777322 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9585 22:13:14.780275 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9586 22:13:14.786491 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9587 22:13:14.790140 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9588 22:13:14.793448 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9589 22:13:14.800443 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9590 22:13:14.803281 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9591 22:13:14.806739 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9592 22:13:14.813680 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9593 22:13:14.816572 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9594 22:13:14.823530 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9595 22:13:14.827181 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9596 22:13:14.830078 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9597 22:13:14.836529 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9598 22:13:14.840121 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9599 22:13:14.846757 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9600 22:13:14.849436 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9601 22:13:14.856196 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9602 22:13:14.859534 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9603 22:13:14.863232 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9604 22:13:14.869717 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9605 22:13:14.872782 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9606 22:13:14.879610 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9607 22:13:14.883103 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9608 22:13:14.889425 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9609 22:13:14.893013 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9610 22:13:14.899519 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9611 22:13:14.903096 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9612 22:13:14.905939 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9613 22:13:14.912811 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9614 22:13:14.915982 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9615 22:13:14.922615 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9616 22:13:14.926194 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9617 22:13:14.932843 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9618 22:13:14.935752 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9619 22:13:14.942508 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9620 22:13:14.945971 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9621 22:13:14.949042 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9622 22:13:14.955833 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9623 22:13:14.959350 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9624 22:13:14.965817 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9625 22:13:14.968783 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9626 22:13:14.975639 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9627 22:13:14.978987 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9628 22:13:14.982281 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9629 22:13:14.988804 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9630 22:13:14.992260 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9631 22:13:14.998963 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9632 22:13:15.002341 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9633 22:13:15.008950 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9634 22:13:15.012689 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9635 22:13:15.018979 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9636 22:13:15.022044 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9637 22:13:15.025263 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9638 22:13:15.032157 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9639 22:13:15.035785 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9640 22:13:15.038854 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9641 22:13:15.045410 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9642 22:13:15.048580 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9643 22:13:15.051918 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9644 22:13:15.058475 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9645 22:13:15.061846 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9646 22:13:15.064951 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9647 22:13:15.072259 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9648 22:13:15.075221 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9649 22:13:15.081850 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9650 22:13:15.084997 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9651 22:13:15.088296 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9652 22:13:15.095071 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9653 22:13:15.098222 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9654 22:13:15.105437 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9655 22:13:15.108576 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9656 22:13:15.111865 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9657 22:13:15.118228 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9658 22:13:15.121682 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9659 22:13:15.125128 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9660 22:13:15.131995 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9661 22:13:15.134850 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9662 22:13:15.138304 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9663 22:13:15.144518 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9664 22:13:15.148239 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9665 22:13:15.151339 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9666 22:13:15.154913 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9667 22:13:15.161483 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9668 22:13:15.164612 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9669 22:13:15.171124 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9670 22:13:15.175019 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9671 22:13:15.177925 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9672 22:13:15.184793 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9673 22:13:15.188151 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9674 22:13:15.194574 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9675 22:13:15.197902 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9676 22:13:15.201409 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9677 22:13:15.207951 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9678 22:13:15.211280 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9679 22:13:15.217862 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9680 22:13:15.221355 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9681 22:13:15.224844 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9682 22:13:15.231203 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9683 22:13:15.234318 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9684 22:13:15.237646 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9685 22:13:15.244401 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9686 22:13:15.247573 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9687 22:13:15.254436 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9688 22:13:15.258003 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9689 22:13:15.260395 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9690 22:13:15.267528 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9691 22:13:15.270843 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9692 22:13:15.277237 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9693 22:13:15.280805 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9694 22:13:15.284147 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9695 22:13:15.290730 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9696 22:13:15.294302 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9697 22:13:15.300444 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9698 22:13:15.303963 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9699 22:13:15.307091 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9700 22:13:15.313650 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9701 22:13:15.317357 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9702 22:13:15.323792 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9703 22:13:15.327518 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9704 22:13:15.330251 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9705 22:13:15.336477 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9706 22:13:15.340177 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9707 22:13:15.347001 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9708 22:13:15.349985 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9709 22:13:15.353804 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9710 22:13:15.359786 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9711 22:13:15.363301 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9712 22:13:15.369634 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9713 22:13:15.372867 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9714 22:13:15.376267 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9715 22:13:15.383311 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9716 22:13:15.386344 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9717 22:13:15.393132 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9718 22:13:15.396317 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9719 22:13:15.399658 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9720 22:13:15.406280 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9721 22:13:15.409278 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9722 22:13:15.415735 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9723 22:13:15.419357 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9724 22:13:15.422533 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9725 22:13:15.429001 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9726 22:13:15.432671 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9727 22:13:15.438864 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9728 22:13:15.442244 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9729 22:13:15.446092 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9730 22:13:15.452273 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9731 22:13:15.455375 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9732 22:13:15.461883 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9733 22:13:15.465678 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9734 22:13:15.472125 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9735 22:13:15.475729 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9736 22:13:15.478223 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9737 22:13:15.485511 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9738 22:13:15.488112 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9739 22:13:15.495140 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9740 22:13:15.498126 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9741 22:13:15.504785 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9742 22:13:15.508278 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9743 22:13:15.511083 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9744 22:13:15.518234 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9745 22:13:15.521412 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9746 22:13:15.527828 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9747 22:13:15.531013 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9748 22:13:15.534536 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9749 22:13:15.541002 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9750 22:13:15.544588 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9751 22:13:15.551254 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9752 22:13:15.554486 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9753 22:13:15.560897 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9754 22:13:15.564563 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9755 22:13:15.567459 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9756 22:13:15.574210 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9757 22:13:15.577362 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9758 22:13:15.584282 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9759 22:13:15.587172 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9760 22:13:15.594253 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9761 22:13:15.597746 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9762 22:13:15.600703 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9763 22:13:15.607114 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9764 22:13:15.610741 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9765 22:13:15.616773 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9766 22:13:15.620416 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9767 22:13:15.626727 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9768 22:13:15.630262 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9769 22:13:15.633927 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9770 22:13:15.640013 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9771 22:13:15.643345 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9772 22:13:15.649929 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9773 22:13:15.653440 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9774 22:13:15.656115 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9775 22:13:15.659771 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9776 22:13:15.663534 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9777 22:13:15.669541 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9778 22:13:15.673060 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9779 22:13:15.679347 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9780 22:13:15.682581 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9781 22:13:15.686131 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9782 22:13:15.692589 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9783 22:13:15.696012 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9784 22:13:15.702406 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9785 22:13:15.705949 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9786 22:13:15.708614 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9787 22:13:15.715691 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9788 22:13:15.718986 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9789 22:13:15.722184 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9790 22:13:15.728961 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9791 22:13:15.732296 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9792 22:13:15.738718 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9793 22:13:15.742079 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9794 22:13:15.744755 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9795 22:13:15.752129 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9796 22:13:15.755070 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9797 22:13:15.758586 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9798 22:13:15.765113 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9799 22:13:15.767988 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9800 22:13:15.775301 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9801 22:13:15.778163 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9802 22:13:15.782146 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9803 22:13:15.788050 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9804 22:13:15.791772 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9805 22:13:15.794920 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9806 22:13:15.801824 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9807 22:13:15.804663 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9808 22:13:15.810983 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9809 22:13:15.814247 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9810 22:13:15.817449 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9811 22:13:15.824538 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9812 22:13:15.827618 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9813 22:13:15.830984 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9814 22:13:15.833901 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9815 22:13:15.840842 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9816 22:13:15.843634 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9817 22:13:15.847453 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9818 22:13:15.850707 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9819 22:13:15.857474 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9820 22:13:15.860414 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9821 22:13:15.864043 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9822 22:13:15.866738 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9823 22:13:15.873818 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9824 22:13:15.876541 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9825 22:13:15.880281 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9826 22:13:15.886674 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9827 22:13:15.889580 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9828 22:13:15.896432 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9829 22:13:15.900009 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9830 22:13:15.906054 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9831 22:13:15.909734 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9832 22:13:15.912718 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9833 22:13:15.919375 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9834 22:13:15.922782 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9835 22:13:15.929507 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9836 22:13:15.932472 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9837 22:13:15.938984 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9838 22:13:15.942358 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9839 22:13:15.945847 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9840 22:13:15.952482 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9841 22:13:15.955703 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9842 22:13:15.962319 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9843 22:13:15.965910 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9844 22:13:15.972321 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9845 22:13:15.975643 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9846 22:13:15.978957 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9847 22:13:15.985648 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9848 22:13:15.988458 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9849 22:13:15.995464 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9850 22:13:15.998677 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9851 22:13:16.001967 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9852 22:13:16.008246 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9853 22:13:16.011731 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9854 22:13:16.017930 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9855 22:13:16.021842 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9856 22:13:16.024818 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9857 22:13:16.031418 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9858 22:13:16.034712 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9859 22:13:16.041017 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9860 22:13:16.044909 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9861 22:13:16.050895 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9862 22:13:16.054685 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9863 22:13:16.060970 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9864 22:13:16.064790 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9865 22:13:16.067515 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9866 22:13:16.073860 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9867 22:13:16.077636 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9868 22:13:16.084104 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9869 22:13:16.087547 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9870 22:13:16.090558 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9871 22:13:16.097328 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9872 22:13:16.100499 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9873 22:13:16.107307 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9874 22:13:16.110330 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9875 22:13:16.117143 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9876 22:13:16.120316 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9877 22:13:16.123403 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9878 22:13:16.129959 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9879 22:13:16.133096 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9880 22:13:16.140186 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9881 22:13:16.143241 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9882 22:13:16.146277 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9883 22:13:16.153248 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9884 22:13:16.156362 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9885 22:13:16.163288 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9886 22:13:16.166359 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9887 22:13:16.172812 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9888 22:13:16.176286 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9889 22:13:16.179551 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9890 22:13:16.186046 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9891 22:13:16.189192 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9892 22:13:16.196217 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9893 22:13:16.199741 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9894 22:13:16.206285 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9895 22:13:16.209123 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9896 22:13:16.212890 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9897 22:13:16.219640 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9898 22:13:16.222722 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9899 22:13:16.229303 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9900 22:13:16.232553 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9901 22:13:16.239404 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9902 22:13:16.242713 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9903 22:13:16.246106 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9904 22:13:16.252141 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9905 22:13:16.255556 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9906 22:13:16.262242 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9907 22:13:16.265715 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9908 22:13:16.272106 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9909 22:13:16.275420 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9910 22:13:16.282039 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9911 22:13:16.285273 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9912 22:13:16.288610 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9913 22:13:16.295388 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9914 22:13:16.298404 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9915 22:13:16.305458 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9916 22:13:16.308509 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9917 22:13:16.315270 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9918 22:13:16.318285 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9919 22:13:16.324704 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9920 22:13:16.328481 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9921 22:13:16.331164 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9922 22:13:16.338181 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9923 22:13:16.341287 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9924 22:13:16.347948 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9925 22:13:16.350675 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9926 22:13:16.357249 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9927 22:13:16.361095 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9928 22:13:16.364263 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9929 22:13:16.370687 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9930 22:13:16.373678 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9931 22:13:16.381085 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9932 22:13:16.383843 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9933 22:13:16.390621 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9934 22:13:16.393598 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9935 22:13:16.400334 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9936 22:13:16.403950 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9937 22:13:16.410264 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9938 22:13:16.413890 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9939 22:13:16.416808 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9940 22:13:16.423831 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9941 22:13:16.426949 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9942 22:13:16.433415 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9943 22:13:16.436379 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9944 22:13:16.442720 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9945 22:13:16.446745 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9946 22:13:16.449621 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9947 22:13:16.456337 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9948 22:13:16.459953 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9949 22:13:16.466654 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9950 22:13:16.469503 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9951 22:13:16.476091 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9952 22:13:16.479478 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9953 22:13:16.485789 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9954 22:13:16.489203 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9955 22:13:16.495960 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9956 22:13:16.499304 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9957 22:13:16.505993 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9958 22:13:16.508996 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9959 22:13:16.515969 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9960 22:13:16.519097 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9961 22:13:16.525395 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9962 22:13:16.528926 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9963 22:13:16.535739 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9964 22:13:16.538680 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9965 22:13:16.545583 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9966 22:13:16.548377 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9967 22:13:16.555235 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9968 22:13:16.558871 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9969 22:13:16.565483 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9970 22:13:16.568833 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9971 22:13:16.575165 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9972 22:13:16.578226 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9973 22:13:16.585129 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9974 22:13:16.588451 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9975 22:13:16.594908 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9976 22:13:16.598359 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9977 22:13:16.605153 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9978 22:13:16.605729 INFO: [APUAPC] vio 0
9979 22:13:16.611842 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9980 22:13:16.614897 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9981 22:13:16.618034 INFO: [APUAPC] D0_APC_0: 0x400510
9982 22:13:16.621623 INFO: [APUAPC] D0_APC_1: 0x0
9983 22:13:16.624725 INFO: [APUAPC] D0_APC_2: 0x1540
9984 22:13:16.628487 INFO: [APUAPC] D0_APC_3: 0x0
9985 22:13:16.631555 INFO: [APUAPC] D1_APC_0: 0xffffffff
9986 22:13:16.634501 INFO: [APUAPC] D1_APC_1: 0xffffffff
9987 22:13:16.638219 INFO: [APUAPC] D1_APC_2: 0x3fffff
9988 22:13:16.641122 INFO: [APUAPC] D1_APC_3: 0x0
9989 22:13:16.644659 INFO: [APUAPC] D2_APC_0: 0xffffffff
9990 22:13:16.647557 INFO: [APUAPC] D2_APC_1: 0xffffffff
9991 22:13:16.651163 INFO: [APUAPC] D2_APC_2: 0x3fffff
9992 22:13:16.654634 INFO: [APUAPC] D2_APC_3: 0x0
9993 22:13:16.658108 INFO: [APUAPC] D3_APC_0: 0xffffffff
9994 22:13:16.660765 INFO: [APUAPC] D3_APC_1: 0xffffffff
9995 22:13:16.663899 INFO: [APUAPC] D3_APC_2: 0x3fffff
9996 22:13:16.667457 INFO: [APUAPC] D3_APC_3: 0x0
9997 22:13:16.670463 INFO: [APUAPC] D4_APC_0: 0xffffffff
9998 22:13:16.674014 INFO: [APUAPC] D4_APC_1: 0xffffffff
9999 22:13:16.677451 INFO: [APUAPC] D4_APC_2: 0x3fffff
10000 22:13:16.681000 INFO: [APUAPC] D4_APC_3: 0x0
10001 22:13:16.683839 INFO: [APUAPC] D5_APC_0: 0xffffffff
10002 22:13:16.687043 INFO: [APUAPC] D5_APC_1: 0xffffffff
10003 22:13:16.690219 INFO: [APUAPC] D5_APC_2: 0x3fffff
10004 22:13:16.693759 INFO: [APUAPC] D5_APC_3: 0x0
10005 22:13:16.697390 INFO: [APUAPC] D6_APC_0: 0xffffffff
10006 22:13:16.700158 INFO: [APUAPC] D6_APC_1: 0xffffffff
10007 22:13:16.703642 INFO: [APUAPC] D6_APC_2: 0x3fffff
10008 22:13:16.704151 INFO: [APUAPC] D6_APC_3: 0x0
10009 22:13:16.710077 INFO: [APUAPC] D7_APC_0: 0xffffffff
10010 22:13:16.713604 INFO: [APUAPC] D7_APC_1: 0xffffffff
10011 22:13:16.717278 INFO: [APUAPC] D7_APC_2: 0x3fffff
10012 22:13:16.717764 INFO: [APUAPC] D7_APC_3: 0x0
10013 22:13:16.720142 INFO: [APUAPC] D8_APC_0: 0xffffffff
10014 22:13:16.726794 INFO: [APUAPC] D8_APC_1: 0xffffffff
10015 22:13:16.730136 INFO: [APUAPC] D8_APC_2: 0x3fffff
10016 22:13:16.730630 INFO: [APUAPC] D8_APC_3: 0x0
10017 22:13:16.733174 INFO: [APUAPC] D9_APC_0: 0xffffffff
10018 22:13:16.736874 INFO: [APUAPC] D9_APC_1: 0xffffffff
10019 22:13:16.740105 INFO: [APUAPC] D9_APC_2: 0x3fffff
10020 22:13:16.743634 INFO: [APUAPC] D9_APC_3: 0x0
10021 22:13:16.746568 INFO: [APUAPC] D10_APC_0: 0xffffffff
10022 22:13:16.750153 INFO: [APUAPC] D10_APC_1: 0xffffffff
10023 22:13:16.756408 INFO: [APUAPC] D10_APC_2: 0x3fffff
10024 22:13:16.756957 INFO: [APUAPC] D10_APC_3: 0x0
10025 22:13:16.759940 INFO: [APUAPC] D11_APC_0: 0xffffffff
10026 22:13:16.766424 INFO: [APUAPC] D11_APC_1: 0xffffffff
10027 22:13:16.770220 INFO: [APUAPC] D11_APC_2: 0x3fffff
10028 22:13:16.770779 INFO: [APUAPC] D11_APC_3: 0x0
10029 22:13:16.776142 INFO: [APUAPC] D12_APC_0: 0xffffffff
10030 22:13:16.779513 INFO: [APUAPC] D12_APC_1: 0xffffffff
10031 22:13:16.782928 INFO: [APUAPC] D12_APC_2: 0x3fffff
10032 22:13:16.783497 INFO: [APUAPC] D12_APC_3: 0x0
10033 22:13:16.789204 INFO: [APUAPC] D13_APC_0: 0xffffffff
10034 22:13:16.792976 INFO: [APUAPC] D13_APC_1: 0xffffffff
10035 22:13:16.796025 INFO: [APUAPC] D13_APC_2: 0x3fffff
10036 22:13:16.799074 INFO: [APUAPC] D13_APC_3: 0x0
10037 22:13:16.802383 INFO: [APUAPC] D14_APC_0: 0xffffffff
10038 22:13:16.805646 INFO: [APUAPC] D14_APC_1: 0xffffffff
10039 22:13:16.809313 INFO: [APUAPC] D14_APC_2: 0x3fffff
10040 22:13:16.812179 INFO: [APUAPC] D14_APC_3: 0x0
10041 22:13:16.815601 INFO: [APUAPC] D15_APC_0: 0xffffffff
10042 22:13:16.819023 INFO: [APUAPC] D15_APC_1: 0xffffffff
10043 22:13:16.822311 INFO: [APUAPC] D15_APC_2: 0x3fffff
10044 22:13:16.825596 INFO: [APUAPC] D15_APC_3: 0x0
10045 22:13:16.826162 INFO: [APUAPC] APC_CON: 0x4
10046 22:13:16.829066 INFO: [NOCDAPC] D0_APC_0: 0x0
10047 22:13:16.832196 INFO: [NOCDAPC] D0_APC_1: 0x0
10048 22:13:16.835516 INFO: [NOCDAPC] D1_APC_0: 0x0
10049 22:13:16.839252 INFO: [NOCDAPC] D1_APC_1: 0xfff
10050 22:13:16.842218 INFO: [NOCDAPC] D2_APC_0: 0x0
10051 22:13:16.845537 INFO: [NOCDAPC] D2_APC_1: 0xfff
10052 22:13:16.848530 INFO: [NOCDAPC] D3_APC_0: 0x0
10053 22:13:16.852162 INFO: [NOCDAPC] D3_APC_1: 0xfff
10054 22:13:16.855061 INFO: [NOCDAPC] D4_APC_0: 0x0
10055 22:13:16.858550 INFO: [NOCDAPC] D4_APC_1: 0xfff
10056 22:13:16.859118 INFO: [NOCDAPC] D5_APC_0: 0x0
10057 22:13:16.862228 INFO: [NOCDAPC] D5_APC_1: 0xfff
10058 22:13:16.865187 INFO: [NOCDAPC] D6_APC_0: 0x0
10059 22:13:16.868188 INFO: [NOCDAPC] D6_APC_1: 0xfff
10060 22:13:16.871952 INFO: [NOCDAPC] D7_APC_0: 0x0
10061 22:13:16.875057 INFO: [NOCDAPC] D7_APC_1: 0xfff
10062 22:13:16.878549 INFO: [NOCDAPC] D8_APC_0: 0x0
10063 22:13:16.881796 INFO: [NOCDAPC] D8_APC_1: 0xfff
10064 22:13:16.884775 INFO: [NOCDAPC] D9_APC_0: 0x0
10065 22:13:16.888694 INFO: [NOCDAPC] D9_APC_1: 0xfff
10066 22:13:16.891503 INFO: [NOCDAPC] D10_APC_0: 0x0
10067 22:13:16.895179 INFO: [NOCDAPC] D10_APC_1: 0xfff
10068 22:13:16.898364 INFO: [NOCDAPC] D11_APC_0: 0x0
10069 22:13:16.901935 INFO: [NOCDAPC] D11_APC_1: 0xfff
10070 22:13:16.902556 INFO: [NOCDAPC] D12_APC_0: 0x0
10071 22:13:16.905144 INFO: [NOCDAPC] D12_APC_1: 0xfff
10072 22:13:16.907997 INFO: [NOCDAPC] D13_APC_0: 0x0
10073 22:13:16.911307 INFO: [NOCDAPC] D13_APC_1: 0xfff
10074 22:13:16.914483 INFO: [NOCDAPC] D14_APC_0: 0x0
10075 22:13:16.917820 INFO: [NOCDAPC] D14_APC_1: 0xfff
10076 22:13:16.921663 INFO: [NOCDAPC] D15_APC_0: 0x0
10077 22:13:16.925218 INFO: [NOCDAPC] D15_APC_1: 0xfff
10078 22:13:16.927905 INFO: [NOCDAPC] APC_CON: 0x4
10079 22:13:16.931405 INFO: [APUAPC] set_apusys_apc done
10080 22:13:16.934366 INFO: [DEVAPC] devapc_init done
10081 22:13:16.938038 INFO: GICv3 without legacy support detected.
10082 22:13:16.941551 INFO: ARM GICv3 driver initialized in EL3
10083 22:13:16.944318 INFO: Maximum SPI INTID supported: 639
10084 22:13:16.951194 INFO: BL31: Initializing runtime services
10085 22:13:16.954993 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10086 22:13:16.957775 INFO: SPM: enable CPC mode
10087 22:13:16.964670 INFO: mcdi ready for mcusys-off-idle and system suspend
10088 22:13:16.967509 INFO: BL31: Preparing for EL3 exit to normal world
10089 22:13:16.970684 INFO: Entry point address = 0x80000000
10090 22:13:16.974106 INFO: SPSR = 0x8
10091 22:13:16.979887
10092 22:13:16.980487
10093 22:13:16.980866
10094 22:13:16.982942 Starting depthcharge on Spherion...
10095 22:13:16.983502
10096 22:13:16.983938 Wipe memory regions:
10097 22:13:16.984397
10098 22:13:16.987053 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10099 22:13:16.987657 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10100 22:13:16.988137 Setting prompt string to ['asurada:']
10101 22:13:16.989750 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10102 22:13:16.990592 [0x00000040000000, 0x00000054600000)
10103 22:13:17.108869
10104 22:13:17.109431 [0x00000054660000, 0x00000080000000)
10105 22:13:17.369360
10106 22:13:17.369929 [0x000000821a7280, 0x000000ffe64000)
10107 22:13:18.114383
10108 22:13:18.114946 [0x00000100000000, 0x00000240000000)
10109 22:13:20.004447
10110 22:13:20.007791 Initializing XHCI USB controller at 0x11200000.
10111 22:13:21.045988
10112 22:13:21.048686 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10113 22:13:21.049159
10114 22:13:21.049536
10115 22:13:21.049945
10116 22:13:21.050728 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10118 22:13:21.151947 asurada: tftpboot 192.168.201.1 10583854/tftp-deploy-86gyr5tv/kernel/image.itb 10583854/tftp-deploy-86gyr5tv/kernel/cmdline
10119 22:13:21.152660 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10120 22:13:21.153115 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10121 22:13:21.157485 tftpboot 192.168.201.1 10583854/tftp-deploy-86gyr5tv/kernel/image.itp-deploy-86gyr5tv/kernel/cmdline
10122 22:13:21.157956
10123 22:13:21.158320 Waiting for link
10124 22:13:21.316175
10125 22:13:21.316792 R8152: Initializing
10126 22:13:21.317176
10127 22:13:21.319564 Version 6 (ocp_data = 5c30)
10128 22:13:21.320172
10129 22:13:21.323013 R8152: Done initializing
10130 22:13:21.323573
10131 22:13:21.323986 Adding net device
10132 22:13:23.350705
10133 22:13:23.351265 done.
10134 22:13:23.351634
10135 22:13:23.351953 MAC: 00:24:32:30:78:ff
10136 22:13:23.352260
10137 22:13:23.354004 Sending DHCP discover... done.
10138 22:13:23.354438
10139 22:13:28.083440 Waiting for reply... done.
10140 22:13:28.083665
10141 22:13:28.083784 Sending DHCP request... done.
10142 22:13:28.087036
10143 22:13:28.087199 Waiting for reply... done.
10144 22:13:28.087326
10145 22:13:28.090002 My ip is 192.168.201.21
10146 22:13:28.090189
10147 22:13:28.093263 The DHCP server ip is 192.168.201.1
10148 22:13:28.093344
10149 22:13:28.096585 TFTP server IP predefined by user: 192.168.201.1
10150 22:13:28.096665
10151 22:13:28.103273 Bootfile predefined by user: 10583854/tftp-deploy-86gyr5tv/kernel/image.itb
10152 22:13:28.103352
10153 22:13:28.106357 Sending tftp read request... done.
10154 22:13:28.106468
10155 22:13:28.109994 Waiting for the transfer...
10156 22:13:28.110129
10157 22:13:28.750043 00000000 ################################################################
10158 22:13:28.750184
10159 22:13:29.350426 00080000 ################################################################
10160 22:13:29.350965
10161 22:13:30.020376 00100000 ################################################################
10162 22:13:30.020943
10163 22:13:30.633238 00180000 ################################################################
10164 22:13:30.633390
10165 22:13:31.192773 00200000 ################################################################
10166 22:13:31.192912
10167 22:13:31.751641 00280000 ################################################################
10168 22:13:31.751774
10169 22:13:32.342449 00300000 ################################################################
10170 22:13:32.342594
10171 22:13:32.901553 00380000 ################################################################
10172 22:13:32.901707
10173 22:13:33.460873 00400000 ################################################################
10174 22:13:33.461185
10175 22:13:34.060713 00480000 ################################################################
10176 22:13:34.060844
10177 22:13:34.619379 00500000 ################################################################
10178 22:13:34.619513
10179 22:13:35.189090 00580000 ################################################################
10180 22:13:35.189249
10181 22:13:35.758634 00600000 ################################################################
10182 22:13:35.759169
10183 22:13:36.338440 00680000 ################################################################
10184 22:13:36.338573
10185 22:13:37.010069 00700000 ################################################################
10186 22:13:37.010608
10187 22:13:37.678557 00780000 ################################################################
10188 22:13:37.679178
10189 22:13:38.335864 00800000 ################################################################
10190 22:13:38.336420
10191 22:13:38.943391 00880000 ################################################################
10192 22:13:38.943553
10193 22:13:39.504433 00900000 ################################################################
10194 22:13:39.504591
10195 22:13:40.070816 00980000 ################################################################
10196 22:13:40.070948
10197 22:13:40.637236 00a00000 ################################################################
10198 22:13:40.637368
10199 22:13:41.221931 00a80000 ################################################################
10200 22:13:41.222494
10201 22:13:41.839100 00b00000 ################################################################
10202 22:13:41.839238
10203 22:13:42.396842 00b80000 ################################################################
10204 22:13:42.396975
10205 22:13:42.972078 00c00000 ################################################################
10206 22:13:42.972238
10207 22:13:43.542877 00c80000 ################################################################
10208 22:13:43.543011
10209 22:13:44.177818 00d00000 ################################################################
10210 22:13:44.178374
10211 22:13:44.812294 00d80000 ################################################################
10212 22:13:44.812446
10213 22:13:45.449575 00e00000 ################################################################
10214 22:13:45.449720
10215 22:13:46.045953 00e80000 ################################################################
10216 22:13:46.046564
10217 22:13:46.726777 00f00000 ################################################################
10218 22:13:46.727302
10219 22:13:47.390524 00f80000 ################################################################
10220 22:13:47.391079
10221 22:13:48.067822 01000000 ################################################################
10222 22:13:48.068365
10223 22:13:48.710722 01080000 ################################################################
10224 22:13:48.711302
10225 22:13:49.402905 01100000 ################################################################
10226 22:13:49.403461
10227 22:13:50.085733 01180000 ################################################################
10228 22:13:50.086289
10229 22:13:50.775934 01200000 ################################################################
10230 22:13:50.776489
10231 22:13:51.464281 01280000 ################################################################
10232 22:13:51.464812
10233 22:13:52.146540 01300000 ################################################################
10234 22:13:52.147104
10235 22:13:52.838422 01380000 ################################################################
10236 22:13:52.838991
10237 22:13:53.523556 01400000 ################################################################
10238 22:13:53.524153
10239 22:13:54.227089 01480000 ################################################################
10240 22:13:54.227828
10241 22:13:54.917022 01500000 ################################################################
10242 22:13:54.917625
10243 22:13:55.602863 01580000 ################################################################
10244 22:13:55.603419
10245 22:13:56.245208 01600000 ################################################################
10246 22:13:56.245768
10247 22:13:56.924629 01680000 ################################################################
10248 22:13:56.925187
10249 22:13:57.607669 01700000 ################################################################
10250 22:13:57.608231
10251 22:13:58.295454 01780000 ################################################################
10252 22:13:58.296126
10253 22:13:58.977528 01800000 ################################################################
10254 22:13:58.977680
10255 22:13:59.576841 01880000 ################################################################
10256 22:13:59.576994
10257 22:14:00.220635 01900000 ################################################################
10258 22:14:00.220781
10259 22:14:00.903352 01980000 ################################################################
10260 22:14:00.903949
10261 22:14:01.566178 01a00000 ############################################################### done.
10262 22:14:01.566738
10263 22:14:01.569755 The bootfile was 27774278 bytes long.
10264 22:14:01.570230
10265 22:14:01.572754 Sending tftp read request... done.
10266 22:14:01.573228
10267 22:14:01.577126 Waiting for the transfer...
10268 22:14:01.577596
10269 22:14:01.577969 00000000 # done.
10270 22:14:01.578327
10271 22:14:01.583660 Command line loaded dynamically from TFTP file: 10583854/tftp-deploy-86gyr5tv/kernel/cmdline
10272 22:14:01.586860
10273 22:14:01.603539 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10583854/extract-nfsrootfs-3sh0d8r1,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10274 22:14:01.606838
10275 22:14:01.607306 Loading FIT.
10276 22:14:01.607725
10277 22:14:01.610134 Image ramdisk-1 has 17643592 bytes.
10278 22:14:01.610723
10279 22:14:01.613056 Image fdt-1 has 46924 bytes.
10280 22:14:01.613629
10281 22:14:01.616373 Image kernel-1 has 10081729 bytes.
10282 22:14:01.616845
10283 22:14:01.623225 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10284 22:14:01.623778
10285 22:14:01.643292 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10286 22:14:01.643927
10287 22:14:01.645430 Choosing best match conf-1 for compat google,spherion-rev2.
10288 22:14:01.650710
10289 22:14:01.654840 Connected to device vid:did:rid of 1ae0:0028:00
10290 22:14:01.662350
10291 22:14:01.665624 tpm_get_response: command 0x17b, return code 0x0
10292 22:14:01.666099
10293 22:14:01.672178 ec_init: CrosEC protocol v3 supported (256, 248)
10294 22:14:01.672806
10295 22:14:01.675227 tpm_cleanup: add release locality here.
10296 22:14:01.675733
10297 22:14:01.678589 Shutting down all USB controllers.
10298 22:14:01.679058
10299 22:14:01.681881 Removing current net device
10300 22:14:01.682452
10301 22:14:01.685608 Exiting depthcharge with code 4 at timestamp: 74032427
10302 22:14:01.686188
10303 22:14:01.691953 LZMA decompressing kernel-1 to 0x821a6718
10304 22:14:01.692531
10305 22:14:01.695210 LZMA decompressing kernel-1 to 0x40000000
10306 22:14:02.962271
10307 22:14:02.962845 jumping to kernel
10308 22:14:02.964373 end: 2.2.4 bootloader-commands (duration 00:00:46) [common]
10309 22:14:02.964918 start: 2.2.5 auto-login-action (timeout 00:03:39) [common]
10310 22:14:02.965357 Setting prompt string to ['Linux version [0-9]']
10311 22:14:02.965759 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10312 22:14:02.966151 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10313 22:14:03.043827
10314 22:14:03.046636 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10315 22:14:03.050944 start: 2.2.5.1 login-action (timeout 00:03:39) [common]
10316 22:14:03.051544 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10317 22:14:03.052075 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10318 22:14:03.052481 Using line separator: #'\n'#
10319 22:14:03.052904 No login prompt set.
10320 22:14:03.053263 Parsing kernel messages
10321 22:14:03.053581 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10322 22:14:03.054156 [login-action] Waiting for messages, (timeout 00:03:39)
10323 22:14:03.069914 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j1606555-arm64-gcc-10-defconfig-arm64-chromebook-vtq55) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sun Jun 4 21:56:05 UTC 2023
10324 22:14:03.073219 [ 0.000000] random: crng init done
10325 22:14:03.079562 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10326 22:14:03.080161 [ 0.000000] efi: UEFI not found.
10327 22:14:03.089668 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10328 22:14:03.096221 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10329 22:14:03.106217 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10330 22:14:03.116098 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10331 22:14:03.122862 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10332 22:14:03.129246 [ 0.000000] printk: bootconsole [mtk8250] enabled
10333 22:14:03.135498 [ 0.000000] NUMA: No NUMA configuration found
10334 22:14:03.142130 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10335 22:14:03.145332 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcda00-0x23efcffff]
10336 22:14:03.149069 [ 0.000000] Zone ranges:
10337 22:14:03.155717 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10338 22:14:03.158511 [ 0.000000] DMA32 empty
10339 22:14:03.165056 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10340 22:14:03.168222 [ 0.000000] Movable zone start for each node
10341 22:14:03.171964 [ 0.000000] Early memory node ranges
10342 22:14:03.178495 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10343 22:14:03.184576 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10344 22:14:03.191063 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10345 22:14:03.198200 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10346 22:14:03.204651 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10347 22:14:03.211038 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10348 22:14:03.267762 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10349 22:14:03.274072 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10350 22:14:03.280806 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10351 22:14:03.284125 [ 0.000000] psci: probing for conduit method from DT.
10352 22:14:03.290313 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10353 22:14:03.293800 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10354 22:14:03.299971 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10355 22:14:03.303381 [ 0.000000] psci: SMC Calling Convention v1.2
10356 22:14:03.310182 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10357 22:14:03.313982 [ 0.000000] Detected VIPT I-cache on CPU0
10358 22:14:03.320175 [ 0.000000] CPU features: detected: GIC system register CPU interface
10359 22:14:03.326892 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10360 22:14:03.333131 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10361 22:14:03.340298 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10362 22:14:03.349873 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10363 22:14:03.356127 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10364 22:14:03.359699 [ 0.000000] alternatives: applying boot alternatives
10365 22:14:03.366515 [ 0.000000] Fallback order for Node 0: 0
10366 22:14:03.372897 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10367 22:14:03.376478 [ 0.000000] Policy zone: Normal
10368 22:14:03.396568 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10583854/extract-nfsrootfs-3sh0d8r1,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10369 22:14:03.405845 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10370 22:14:03.417155 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10371 22:14:03.426928 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10372 22:14:03.433122 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10373 22:14:03.436963 <6>[ 0.000000] software IO TLB: area num 8.
10374 22:14:03.493027 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10375 22:14:03.641805 <6>[ 0.000000] Memory: 7955712K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 397056K reserved, 32768K cma-reserved)
10376 22:14:03.648926 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10377 22:14:03.655913 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10378 22:14:03.658552 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10379 22:14:03.665736 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10380 22:14:03.671921 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10381 22:14:03.678704 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10382 22:14:03.685607 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10383 22:14:03.692124 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10384 22:14:03.698208 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10385 22:14:03.704835 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10386 22:14:03.707840 <6>[ 0.000000] GICv3: 608 SPIs implemented
10387 22:14:03.711229 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10388 22:14:03.718053 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10389 22:14:03.721394 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10390 22:14:03.727623 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10391 22:14:03.741057 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10392 22:14:03.754256 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10393 22:14:03.761538 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10394 22:14:03.769322 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10395 22:14:03.782609 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10396 22:14:03.788814 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10397 22:14:03.795701 <6>[ 0.009181] Console: colour dummy device 80x25
10398 22:14:03.805312 <6>[ 0.013938] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10399 22:14:03.812263 <6>[ 0.024381] pid_max: default: 32768 minimum: 301
10400 22:14:03.815682 <6>[ 0.029285] LSM: Security Framework initializing
10401 22:14:03.822230 <6>[ 0.034254] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10402 22:14:03.831752 <6>[ 0.042117] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10403 22:14:03.841781 <6>[ 0.051545] cblist_init_generic: Setting adjustable number of callback queues.
10404 22:14:03.848263 <6>[ 0.058998] cblist_init_generic: Setting shift to 3 and lim to 1.
10405 22:14:03.851377 <6>[ 0.065376] cblist_init_generic: Setting shift to 3 and lim to 1.
10406 22:14:03.858442 <6>[ 0.071782] rcu: Hierarchical SRCU implementation.
10407 22:14:03.864759 <6>[ 0.076796] rcu: Max phase no-delay instances is 1000.
10408 22:14:03.871632 <6>[ 0.083813] EFI services will not be available.
10409 22:14:03.874462 <6>[ 0.088785] smp: Bringing up secondary CPUs ...
10410 22:14:03.883052 <6>[ 0.093835] Detected VIPT I-cache on CPU1
10411 22:14:03.889778 <6>[ 0.093906] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10412 22:14:03.896731 <6>[ 0.093936] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10413 22:14:03.898877 <6>[ 0.094275] Detected VIPT I-cache on CPU2
10414 22:14:03.908764 <6>[ 0.094327] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10415 22:14:03.915786 <6>[ 0.094344] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10416 22:14:03.919305 <6>[ 0.094606] Detected VIPT I-cache on CPU3
10417 22:14:03.925583 <6>[ 0.094653] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10418 22:14:03.931987 <6>[ 0.094668] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10419 22:14:03.938680 <6>[ 0.094974] CPU features: detected: Spectre-v4
10420 22:14:03.941909 <6>[ 0.094980] CPU features: detected: Spectre-BHB
10421 22:14:03.945802 <6>[ 0.094987] Detected PIPT I-cache on CPU4
10422 22:14:03.951692 <6>[ 0.095044] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10423 22:14:03.958516 <6>[ 0.095061] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10424 22:14:03.965198 <6>[ 0.095357] Detected PIPT I-cache on CPU5
10425 22:14:03.971477 <6>[ 0.095419] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10426 22:14:03.978250 <6>[ 0.095435] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10427 22:14:03.981705 <6>[ 0.095719] Detected PIPT I-cache on CPU6
10428 22:14:03.988169 <6>[ 0.095783] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10429 22:14:03.997934 <6>[ 0.095799] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10430 22:14:04.001529 <6>[ 0.096084] Detected PIPT I-cache on CPU7
10431 22:14:04.007947 <6>[ 0.096142] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10432 22:14:04.014944 <6>[ 0.096158] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10433 22:14:04.018253 <6>[ 0.096205] smp: Brought up 1 node, 8 CPUs
10434 22:14:04.024541 <6>[ 0.237559] SMP: Total of 8 processors activated.
10435 22:14:04.028134 <6>[ 0.242481] CPU features: detected: 32-bit EL0 Support
10436 22:14:04.037883 <6>[ 0.247841] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10437 22:14:04.044266 <6>[ 0.256692] CPU features: detected: Common not Private translations
10438 22:14:04.050721 <6>[ 0.263171] CPU features: detected: CRC32 instructions
10439 22:14:04.057398 <6>[ 0.268524] CPU features: detected: RCpc load-acquire (LDAPR)
10440 22:14:04.060918 <6>[ 0.274482] CPU features: detected: LSE atomic instructions
10441 22:14:04.067359 <6>[ 0.280263] CPU features: detected: Privileged Access Never
10442 22:14:04.073943 <6>[ 0.286050] CPU features: detected: RAS Extension Support
10443 22:14:04.080727 <6>[ 0.291660] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10444 22:14:04.083849 <6>[ 0.298879] CPU: All CPU(s) started at EL2
10445 22:14:04.090831 <6>[ 0.303196] alternatives: applying system-wide alternatives
10446 22:14:04.100318 <6>[ 0.313858] devtmpfs: initialized
10447 22:14:04.115684 <6>[ 0.322799] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10448 22:14:04.123005 <6>[ 0.332763] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10449 22:14:04.129027 <6>[ 0.340998] pinctrl core: initialized pinctrl subsystem
10450 22:14:04.132380 <6>[ 0.347610] DMI not present or invalid.
10451 22:14:04.138829 <6>[ 0.352031] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10452 22:14:04.148593 <6>[ 0.358936] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10453 22:14:04.155326 <6>[ 0.366521] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10454 22:14:04.165211 <6>[ 0.374751] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10455 22:14:04.168406 <6>[ 0.383003] audit: initializing netlink subsys (disabled)
10456 22:14:04.178274 <5>[ 0.388702] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10457 22:14:04.184960 <6>[ 0.389423] thermal_sys: Registered thermal governor 'step_wise'
10458 22:14:04.192007 <6>[ 0.396672] thermal_sys: Registered thermal governor 'power_allocator'
10459 22:14:04.194917 <6>[ 0.402930] cpuidle: using governor menu
10460 22:14:04.201834 <6>[ 0.413895] NET: Registered PF_QIPCRTR protocol family
10461 22:14:04.208074 <6>[ 0.419422] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10462 22:14:04.215007 <6>[ 0.426525] ASID allocator initialised with 32768 entries
10463 22:14:04.218145 <6>[ 0.433108] Serial: AMBA PL011 UART driver
10464 22:14:04.228643 <4>[ 0.441861] Trying to register duplicate clock ID: 134
10465 22:14:04.284749 <6>[ 0.501407] KASLR enabled
10466 22:14:04.299246 <6>[ 0.509187] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10467 22:14:04.305862 <6>[ 0.516200] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10468 22:14:04.311864 <6>[ 0.522690] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10469 22:14:04.318576 <6>[ 0.529693] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10470 22:14:04.324856 <6>[ 0.536180] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10471 22:14:04.331793 <6>[ 0.543187] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10472 22:14:04.338409 <6>[ 0.549675] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10473 22:14:04.344873 <6>[ 0.556681] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10474 22:14:04.348090 <6>[ 0.564205] ACPI: Interpreter disabled.
10475 22:14:04.356972 <6>[ 0.570619] iommu: Default domain type: Translated
10476 22:14:04.363817 <6>[ 0.575733] iommu: DMA domain TLB invalidation policy: strict mode
10477 22:14:04.366719 <5>[ 0.582390] SCSI subsystem initialized
10478 22:14:04.373066 <6>[ 0.586557] usbcore: registered new interface driver usbfs
10479 22:14:04.380215 <6>[ 0.592292] usbcore: registered new interface driver hub
10480 22:14:04.383311 <6>[ 0.597845] usbcore: registered new device driver usb
10481 22:14:04.390559 <6>[ 0.603925] pps_core: LinuxPPS API ver. 1 registered
10482 22:14:04.400198 <6>[ 0.609120] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10483 22:14:04.403698 <6>[ 0.618466] PTP clock support registered
10484 22:14:04.407136 <6>[ 0.622710] EDAC MC: Ver: 3.0.0
10485 22:14:04.414367 <6>[ 0.627855] FPGA manager framework
10486 22:14:04.420594 <6>[ 0.631537] Advanced Linux Sound Architecture Driver Initialized.
10487 22:14:04.424538 <6>[ 0.638313] vgaarb: loaded
10488 22:14:04.430967 <6>[ 0.641487] clocksource: Switched to clocksource arch_sys_counter
10489 22:14:04.434009 <5>[ 0.647924] VFS: Disk quotas dquot_6.6.0
10490 22:14:04.441140 <6>[ 0.652109] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10491 22:14:04.443770 <6>[ 0.659300] pnp: PnP ACPI: disabled
10492 22:14:04.452502 <6>[ 0.666042] NET: Registered PF_INET protocol family
10493 22:14:04.461911 <6>[ 0.671641] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10494 22:14:04.473471 <6>[ 0.683950] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10495 22:14:04.483305 <6>[ 0.692766] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10496 22:14:04.490292 <6>[ 0.700738] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10497 22:14:04.499939 <6>[ 0.709438] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10498 22:14:04.506445 <6>[ 0.719181] TCP: Hash tables configured (established 65536 bind 65536)
10499 22:14:04.513211 <6>[ 0.726040] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10500 22:14:04.523046 <6>[ 0.733238] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10501 22:14:04.529963 <6>[ 0.740943] NET: Registered PF_UNIX/PF_LOCAL protocol family
10502 22:14:04.536173 <6>[ 0.747109] RPC: Registered named UNIX socket transport module.
10503 22:14:04.539501 <6>[ 0.753265] RPC: Registered udp transport module.
10504 22:14:04.546178 <6>[ 0.758201] RPC: Registered tcp transport module.
10505 22:14:04.552611 <6>[ 0.763134] RPC: Registered tcp NFSv4.1 backchannel transport module.
10506 22:14:04.556341 <6>[ 0.769802] PCI: CLS 0 bytes, default 64
10507 22:14:04.559097 <6>[ 0.774160] Unpacking initramfs...
10508 22:14:04.575895 <6>[ 0.786107] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10509 22:14:04.585522 <6>[ 0.794769] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10510 22:14:04.589126 <6>[ 0.803617] kvm [1]: IPA Size Limit: 40 bits
10511 22:14:04.595890 <6>[ 0.808145] kvm [1]: GICv3: no GICV resource entry
10512 22:14:04.599387 <6>[ 0.813167] kvm [1]: disabling GICv2 emulation
10513 22:14:04.605515 <6>[ 0.817853] kvm [1]: GIC system register CPU interface enabled
10514 22:14:04.608805 <6>[ 0.824019] kvm [1]: vgic interrupt IRQ18
10515 22:14:04.615320 <6>[ 0.828396] kvm [1]: VHE mode initialized successfully
10516 22:14:04.622144 <5>[ 0.834804] Initialise system trusted keyrings
10517 22:14:04.628449 <6>[ 0.839631] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10518 22:14:04.636506 <6>[ 0.849673] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10519 22:14:04.642327 <5>[ 0.856071] NFS: Registering the id_resolver key type
10520 22:14:04.646096 <5>[ 0.861377] Key type id_resolver registered
10521 22:14:04.652300 <5>[ 0.865794] Key type id_legacy registered
10522 22:14:04.659435 <6>[ 0.870092] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10523 22:14:04.665563 <6>[ 0.877015] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10524 22:14:04.672014 <6>[ 0.884759] 9p: Installing v9fs 9p2000 file system support
10525 22:14:04.709290 <5>[ 0.922975] Key type asymmetric registered
10526 22:14:04.712318 <5>[ 0.927308] Asymmetric key parser 'x509' registered
10527 22:14:04.722806 <6>[ 0.932462] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10528 22:14:04.725527 <6>[ 0.940099] io scheduler mq-deadline registered
10529 22:14:04.729136 <6>[ 0.944870] io scheduler kyber registered
10530 22:14:04.748040 <6>[ 0.961739] EINJ: ACPI disabled.
10531 22:14:04.780474 <4>[ 0.987406] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10532 22:14:04.790230 <4>[ 0.998042] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10533 22:14:04.805387 <6>[ 1.018705] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10534 22:14:04.813144 <6>[ 1.026796] printk: console [ttyS0] disabled
10535 22:14:04.840793 <6>[ 1.051447] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10536 22:14:04.847963 <6>[ 1.060942] printk: console [ttyS0] enabled
10537 22:14:04.850999 <6>[ 1.060942] printk: console [ttyS0] enabled
10538 22:14:04.857300 <6>[ 1.069841] printk: bootconsole [mtk8250] disabled
10539 22:14:04.860527 <6>[ 1.069841] printk: bootconsole [mtk8250] disabled
10540 22:14:04.867641 <6>[ 1.081141] SuperH (H)SCI(F) driver initialized
10541 22:14:04.871157 <6>[ 1.086403] msm_serial: driver initialized
10542 22:14:04.885156 <6>[ 1.095309] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10543 22:14:04.894959 <6>[ 1.103863] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10544 22:14:04.901298 <6>[ 1.112406] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10545 22:14:04.910973 <6>[ 1.121036] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10546 22:14:04.921392 <6>[ 1.129741] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10547 22:14:04.927622 <6>[ 1.138457] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10548 22:14:04.937703 <6>[ 1.147002] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10549 22:14:04.944437 <6>[ 1.155813] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10550 22:14:04.954161 <6>[ 1.164356] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10551 22:14:04.966021 <6>[ 1.179982] loop: module loaded
10552 22:14:04.972683 <6>[ 1.186069] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10553 22:14:04.996000 <4>[ 1.209577] mtk-pmic-keys: Failed to locate of_node [id: -1]
10554 22:14:05.002765 <6>[ 1.216385] megasas: 07.719.03.00-rc1
10555 22:14:05.012485 <6>[ 1.226019] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10556 22:14:05.019642 <6>[ 1.232883] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10557 22:14:05.035724 <6>[ 1.249446] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10558 22:14:05.096470 <6>[ 1.303408] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10559 22:14:05.282283 <6>[ 1.496058] Freeing initrd memory: 17228K
10560 22:14:05.291842 <6>[ 1.506196] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10561 22:14:05.303015 <6>[ 1.517100] tun: Universal TUN/TAP device driver, 1.6
10562 22:14:05.306639 <6>[ 1.523145] thunder_xcv, ver 1.0
10563 22:14:05.310133 <6>[ 1.526655] thunder_bgx, ver 1.0
10564 22:14:05.312935 <6>[ 1.530150] nicpf, ver 1.0
10565 22:14:05.323536 <6>[ 1.534158] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10566 22:14:05.327317 <6>[ 1.541637] hns3: Copyright (c) 2017 Huawei Corporation.
10567 22:14:05.330035 <6>[ 1.547227] hclge is initializing
10568 22:14:05.336724 <6>[ 1.550809] e1000: Intel(R) PRO/1000 Network Driver
10569 22:14:05.343815 <6>[ 1.555938] e1000: Copyright (c) 1999-2006 Intel Corporation.
10570 22:14:05.347426 <6>[ 1.561952] e1000e: Intel(R) PRO/1000 Network Driver
10571 22:14:05.353411 <6>[ 1.567168] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10572 22:14:05.360294 <6>[ 1.573353] igb: Intel(R) Gigabit Ethernet Network Driver
10573 22:14:05.367310 <6>[ 1.579002] igb: Copyright (c) 2007-2014 Intel Corporation.
10574 22:14:05.373376 <6>[ 1.584838] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10575 22:14:05.380023 <6>[ 1.591357] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10576 22:14:05.383628 <6>[ 1.597817] sky2: driver version 1.30
10577 22:14:05.390225 <6>[ 1.602796] VFIO - User Level meta-driver version: 0.3
10578 22:14:05.397658 <6>[ 1.610929] usbcore: registered new interface driver usb-storage
10579 22:14:05.404105 <6>[ 1.617376] usbcore: registered new device driver onboard-usb-hub
10580 22:14:05.412422 <6>[ 1.626415] mt6397-rtc mt6359-rtc: registered as rtc0
10581 22:14:05.423501 <6>[ 1.631895] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-04T22:14:17 UTC (1685916857)
10582 22:14:05.425633 <6>[ 1.641500] i2c_dev: i2c /dev entries driver
10583 22:14:05.442637 <6>[ 1.653124] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10584 22:14:05.449854 <6>[ 1.663320] sdhci: Secure Digital Host Controller Interface driver
10585 22:14:05.456074 <6>[ 1.669757] sdhci: Copyright(c) Pierre Ossman
10586 22:14:05.462963 <6>[ 1.675151] Synopsys Designware Multimedia Card Interface Driver
10587 22:14:05.466422 <6>[ 1.681761] mmc0: CQHCI version 5.10
10588 22:14:05.472874 <6>[ 1.682304] sdhci-pltfm: SDHCI platform and OF driver helper
10589 22:14:05.480023 <6>[ 1.693623] ledtrig-cpu: registered to indicate activity on CPUs
10590 22:14:05.491026 <6>[ 1.700971] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10591 22:14:05.494236 <6>[ 1.708353] usbcore: registered new interface driver usbhid
10592 22:14:05.500550 <6>[ 1.714182] usbhid: USB HID core driver
10593 22:14:05.507510 <6>[ 1.718456] spi_master spi0: will run message pump with realtime priority
10594 22:14:05.553493 <6>[ 1.760390] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10595 22:14:05.568425 <6>[ 1.775668] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10596 22:14:05.575881 <6>[ 1.789234] mmc0: Command Queue Engine enabled
10597 22:14:05.583133 <6>[ 1.790658] cros-ec-spi spi0.0: Chrome EC device registered
10598 22:14:05.585935 <6>[ 1.793976] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10599 22:14:05.593615 <6>[ 1.807123] mmcblk0: mmc0:0001 DA4128 116 GiB
10600 22:14:05.603300 <6>[ 1.816699] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10601 22:14:05.612868 <6>[ 1.817599] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10602 22:14:05.619518 <6>[ 1.824080] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10603 22:14:05.622987 <6>[ 1.834076] NET: Registered PF_PACKET protocol family
10604 22:14:05.629033 <6>[ 1.837802] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10605 22:14:05.632713 <6>[ 1.842579] 9pnet: Installing 9P2000 support
10606 22:14:05.639183 <6>[ 1.848337] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10607 22:14:05.646383 <5>[ 1.852254] Key type dns_resolver registered
10608 22:14:05.649311 <6>[ 1.863863] registered taskstats version 1
10609 22:14:05.655759 <5>[ 1.868303] Loading compiled-in X.509 certificates
10610 22:14:05.689063 <4>[ 1.895854] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10611 22:14:05.698908 <4>[ 1.906520] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10612 22:14:05.708518 <3>[ 1.919212] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10613 22:14:05.721226 <6>[ 1.934802] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10614 22:14:05.728160 <6>[ 1.941559] xhci-mtk 11200000.usb: xHCI Host Controller
10615 22:14:05.734478 <6>[ 1.947073] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10616 22:14:05.744815 <6>[ 1.954930] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10617 22:14:05.752082 <6>[ 1.964356] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10618 22:14:05.757734 <6>[ 1.970436] xhci-mtk 11200000.usb: xHCI Host Controller
10619 22:14:05.764105 <6>[ 1.975917] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10620 22:14:05.770718 <6>[ 1.983567] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10621 22:14:05.777812 <6>[ 1.991272] hub 1-0:1.0: USB hub found
10622 22:14:05.780849 <6>[ 1.995292] hub 1-0:1.0: 1 port detected
10623 22:14:05.790798 <6>[ 1.999629] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10624 22:14:05.794631 <6>[ 2.008216] hub 2-0:1.0: USB hub found
10625 22:14:05.797398 <6>[ 2.012233] hub 2-0:1.0: 1 port detected
10626 22:14:05.806138 <6>[ 2.019600] mtk-msdc 11f70000.mmc: Got CD GPIO
10627 22:14:05.824211 <6>[ 2.034621] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10628 22:14:05.830716 <6>[ 2.042786] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10629 22:14:05.840355 <4>[ 2.050768] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10630 22:14:05.850717 <6>[ 2.060460] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10631 22:14:05.857191 <6>[ 2.068553] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10632 22:14:05.867390 <6>[ 2.076603] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10633 22:14:05.873915 <6>[ 2.084521] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10634 22:14:05.880159 <6>[ 2.092379] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10635 22:14:05.890392 <6>[ 2.100203] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10636 22:14:05.900531 <6>[ 2.110960] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10637 22:14:05.910515 <6>[ 2.119329] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10638 22:14:05.916904 <6>[ 2.127719] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10639 22:14:05.927203 <6>[ 2.136064] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10640 22:14:05.933570 <6>[ 2.144438] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10641 22:14:05.943455 <6>[ 2.152782] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10642 22:14:05.950318 <6>[ 2.161152] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10643 22:14:05.959820 <6>[ 2.169497] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10644 22:14:05.967178 <6>[ 2.177862] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10645 22:14:05.976663 <6>[ 2.186206] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10646 22:14:05.983446 <6>[ 2.194549] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10647 22:14:05.993399 <6>[ 2.202892] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10648 22:14:05.999777 <6>[ 2.211235] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10649 22:14:06.009691 <6>[ 2.219579] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10650 22:14:06.016848 <6>[ 2.227923] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10651 22:14:06.023402 <6>[ 2.236828] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10652 22:14:06.030500 <6>[ 2.244265] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10653 22:14:06.037441 <6>[ 2.251296] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10654 22:14:06.047639 <6>[ 2.258379] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10655 22:14:06.054730 <6>[ 2.265654] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10656 22:14:06.064385 <6>[ 2.272558] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10657 22:14:06.070926 <6>[ 2.281705] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10658 22:14:06.080874 <6>[ 2.290865] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10659 22:14:06.090905 <6>[ 2.300181] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10660 22:14:06.100647 <6>[ 2.309657] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10661 22:14:06.110995 <6>[ 2.319131] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10662 22:14:06.117199 <6>[ 2.328258] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10663 22:14:06.127749 <6>[ 2.337732] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10664 22:14:06.136977 <6>[ 2.346859] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10665 22:14:06.146979 <6>[ 2.356161] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10666 22:14:06.157093 <6>[ 2.366327] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10667 22:14:06.167514 <6>[ 2.377790] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10668 22:14:06.173691 <6>[ 2.387724] Trying to probe devices needed for running init ...
10669 22:14:06.187354 <6>[ 2.397874] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10670 22:14:06.214645 <6>[ 2.428300] hub 2-1:1.0: USB hub found
10671 22:14:06.217527 <6>[ 2.432703] hub 2-1:1.0: 3 ports detected
10672 22:14:06.339207 <6>[ 2.549761] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10673 22:14:06.493869 <6>[ 2.707471] hub 1-1:1.0: USB hub found
10674 22:14:06.496926 <6>[ 2.711922] hub 1-1:1.0: 4 ports detected
10675 22:14:06.571362 <6>[ 2.782004] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10676 22:14:06.819032 <6>[ 3.029762] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10677 22:14:06.951939 <6>[ 3.165973] hub 1-1.4:1.0: USB hub found
10678 22:14:06.955106 <6>[ 3.170622] hub 1-1.4:1.0: 2 ports detected
10679 22:14:07.251160 <6>[ 3.461760] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10680 22:14:07.442971 <6>[ 3.653762] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10681 22:14:18.447912 <6>[ 14.666323] ALSA device list:
10682 22:14:18.454140 <6>[ 14.669578] No soundcards found.
10683 22:14:18.466821 <6>[ 14.681965] Freeing unused kernel memory: 8384K
10684 22:14:18.470028 <6>[ 14.686898] Run /init as init process
10685 22:14:18.480659 Loading, please wait...
10686 22:14:18.500188 Starting version 247.3-7+deb11u2
10687 22:14:18.818499 <6>[ 15.030137] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10688 22:14:18.831235 <6>[ 15.046310] remoteproc remoteproc0: scp is available
10689 22:14:18.842774 <4>[ 15.054788] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10690 22:14:18.849658 <6>[ 15.065030] remoteproc remoteproc0: powering up scp
10691 22:14:18.859661 <4>[ 15.070918] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10692 22:14:18.866320 <3>[ 15.080786] remoteproc remoteproc0: request_firmware failed: -2
10693 22:14:18.875964 <3>[ 15.088087] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10694 22:14:18.883004 <3>[ 15.096303] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10695 22:14:18.892425 <3>[ 15.104398] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10696 22:14:18.926345 <3>[ 15.138261] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10697 22:14:18.932746 <4>[ 15.141735] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10698 22:14:18.942791 <3>[ 15.146520] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10699 22:14:18.949913 <6>[ 15.149293] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10700 22:14:18.959615 <6>[ 15.149320] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10701 22:14:18.965867 <6>[ 15.149330] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10702 22:14:18.972573 <6>[ 15.150720] mc: Linux media interface: v0.10
10703 22:14:18.979487 <4>[ 15.156117] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10704 22:14:18.986141 <3>[ 15.161853] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10705 22:14:18.992630 <6>[ 15.165696] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10706 22:14:18.999698 <6>[ 15.172161] usbcore: registered new interface driver r8152
10707 22:14:19.009213 <3>[ 15.178298] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10708 22:14:19.012567 <6>[ 15.188266] videodev: Linux video capture interface: v2.00
10709 22:14:19.022634 <4>[ 15.191426] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10710 22:14:19.028980 <4>[ 15.191426] Fallback method does not support PEC.
10711 22:14:19.035984 <3>[ 15.191489] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10712 22:14:19.045970 <3>[ 15.206552] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10713 22:14:19.052535 <3>[ 15.207063] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10714 22:14:19.059013 <6>[ 15.270015] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10715 22:14:19.068781 <3>[ 15.273015] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10716 22:14:19.075870 <6>[ 15.274915] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10717 22:14:19.081957 <6>[ 15.274925] pci_bus 0000:00: root bus resource [bus 00-ff]
10718 22:14:19.088835 <6>[ 15.274934] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10719 22:14:19.098845 <6>[ 15.274940] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10720 22:14:19.104992 <6>[ 15.274989] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10721 22:14:19.112110 <6>[ 15.275015] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10722 22:14:19.114829 <6>[ 15.275117] pci 0000:00:00.0: supports D1 D2
10723 22:14:19.121611 <6>[ 15.275120] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10724 22:14:19.131441 <6>[ 15.276848] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10725 22:14:19.138174 <6>[ 15.276978] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10726 22:14:19.144906 <6>[ 15.277010] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10727 22:14:19.151372 <6>[ 15.277031] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10728 22:14:19.161213 <6>[ 15.277060] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10729 22:14:19.164757 <6>[ 15.277183] pci 0000:01:00.0: supports D1 D2
10730 22:14:19.171680 <6>[ 15.277186] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10731 22:14:19.181735 <6>[ 15.278704] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10732 22:14:19.191232 <6>[ 15.279096] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10733 22:14:19.200794 <6>[ 15.281758] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10734 22:14:19.207366 <3>[ 15.288231] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10735 22:14:19.214345 <6>[ 15.289571] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10736 22:14:19.224029 <6>[ 15.289634] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10737 22:14:19.231045 <6>[ 15.289642] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10738 22:14:19.237115 <6>[ 15.289656] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10739 22:14:19.247328 <6>[ 15.289673] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10740 22:14:19.253591 <6>[ 15.289689] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10741 22:14:19.260808 <6>[ 15.289707] pci 0000:00:00.0: PCI bridge to [bus 01]
10742 22:14:19.267240 <6>[ 15.289717] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10743 22:14:19.273679 <6>[ 15.289866] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10744 22:14:19.280326 <6>[ 15.290847] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10745 22:14:19.286833 <6>[ 15.291216] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10746 22:14:19.296787 <4>[ 15.300963] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10747 22:14:19.303542 <3>[ 15.308096] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10748 22:14:19.309611 <4>[ 15.317925] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10749 22:14:19.316217 <6>[ 15.319053] usbcore: registered new interface driver cdc_ether
10750 22:14:19.326573 <3>[ 15.324292] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10751 22:14:19.332974 <5>[ 15.329178] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10752 22:14:19.339687 <6>[ 15.332290] usbcore: registered new interface driver r8153_ecm
10753 22:14:19.345910 <3>[ 15.336216] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10754 22:14:19.352744 <6>[ 15.337476] Bluetooth: Core ver 2.22
10755 22:14:19.356196 <6>[ 15.337640] NET: Registered PF_BLUETOOTH protocol family
10756 22:14:19.362808 <6>[ 15.337644] Bluetooth: HCI device and connection manager initialized
10757 22:14:19.368980 <6>[ 15.337680] Bluetooth: HCI socket layer initialized
10758 22:14:19.372693 <6>[ 15.337686] Bluetooth: L2CAP socket layer initialized
10759 22:14:19.379662 <6>[ 15.337701] Bluetooth: SCO socket layer initialized
10760 22:14:19.385815 <5>[ 15.345181] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10761 22:14:19.392484 <3>[ 15.351332] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10762 22:14:19.402208 <6>[ 15.352571] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10763 22:14:19.412321 <6>[ 15.353836] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10764 22:14:19.419080 <6>[ 15.353981] usbcore: registered new interface driver uvcvideo
10765 22:14:19.428385 <4>[ 15.358086] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10766 22:14:19.435436 <3>[ 15.365090] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10767 22:14:19.441611 <6>[ 15.372552] cfg80211: failed to load regulatory.db
10768 22:14:19.448734 <6>[ 15.375652] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10769 22:14:19.451799 <6>[ 15.377703] r8152 2-1.3:1.0 eth0: v1.12.13
10770 22:14:19.461678 <3>[ 15.380089] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10771 22:14:19.464932 <6>[ 15.385932] usbcore: registered new interface driver btusb
10772 22:14:19.477748 <4>[ 15.386294] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10773 22:14:19.481269 <3>[ 15.386304] Bluetooth: hci0: Failed to load firmware file (-2)
10774 22:14:19.488249 <3>[ 15.386308] Bluetooth: hci0: Failed to set up firmware (-2)
10775 22:14:19.497992 <4>[ 15.386311] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10776 22:14:19.504321 <6>[ 15.388024] r8152 2-1.3:1.0 enx0024323078ff: renamed from eth0
10777 22:14:19.514017 <3>[ 15.391514] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10778 22:14:19.553993 <3>[ 15.766329] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10779 22:14:19.580954 <6>[ 15.793039] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10780 22:14:19.587744 <6>[ 15.800556] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10781 22:14:19.612124 <6>[ 15.827340] mt7921e 0000:01:00.0: ASIC revision: 79610010
10782 22:14:19.717185 <4>[ 15.925807] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10783 22:14:19.720811 Begin: Loading essential drivers ... done.
10784 22:14:19.726602 Begin: Running /scripts/init-premount ... done.
10785 22:14:19.733699 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10786 22:14:19.740401 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10787 22:14:19.747105 Device /sys/class/net/enx0024323078ff found
10788 22:14:19.747724 done.
10789 22:14:19.809686 IP-Config: enx0024323078ff hardware address 00:24:32:30:78:ff mtu 1500 DHCP
10790 22:14:19.839669 <4>[ 16.047893] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10791 22:14:19.958585 <4>[ 16.167406] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10792 22:14:20.074744 <4>[ 16.283193] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10793 22:14:20.190395 <4>[ 16.399147] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10794 22:14:20.306340 <4>[ 16.514996] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10795 22:14:20.422009 <4>[ 16.631051] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10796 22:14:20.538108 <4>[ 16.746924] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10797 22:14:20.654083 <4>[ 16.862990] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10798 22:14:20.770327 <4>[ 16.978937] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10799 22:14:20.802273 <6>[ 17.017832] r8152 2-1.3:1.0 enx0024323078ff: carrier on
10800 22:14:20.876992 <3>[ 17.092881] mt7921e 0000:01:00.0: hardware init failed
10801 22:14:20.916460 IP-Config: no response after 2 secs - giving up
10802 22:14:20.957466 IP-Config: enx0024323078ff hardware address 00:24:32:30:78:ff mtu 1500 DHCP
10803 22:14:20.960698 IP-Config: enx0024323078ff complete (dhcp from 192.168.201.1):
10804 22:14:20.970897 address: 192.168.201.21 broadcast: 192.168.201.255 netmask: 255.255.255.0
10805 22:14:20.977095 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10806 22:14:20.983764 host : mt8192-asurada-spherion-r0-cbg-8
10807 22:14:20.990575 domain : lava-rack
10808 22:14:20.993430 rootserver: 192.168.201.1 rootpath:
10809 22:14:20.993959 filename :
10810 22:14:21.068885 done.
10811 22:14:21.078455 Begin: Running /scripts/nfs-bottom ... done.
10812 22:14:21.097160 Begin: Running /scripts/init-bottom ... done.
10813 22:14:22.278994 <6>[ 18.494799] NET: Registered PF_INET6 protocol family
10814 22:14:22.285908 <6>[ 18.501560] Segment Routing with IPv6
10815 22:14:22.288662 <6>[ 18.505537] In-situ OAM (IOAM) with IPv6
10816 22:14:22.422998 <30>[ 18.618858] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10817 22:14:22.426159 <30>[ 18.642631] systemd[1]: Detected architecture arm64.
10818 22:14:22.449678
10819 22:14:22.452981 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10820 22:14:22.453447
10821 22:14:22.469193 <30>[ 18.684988] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10822 22:14:23.201688 <30>[ 19.414300] systemd[1]: Queued start job for default target Graphical Interface.
10823 22:14:23.227456 <30>[ 19.442964] systemd[1]: Created slice system-getty.slice.
10824 22:14:23.233850 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10825 22:14:23.250657 <30>[ 19.466502] systemd[1]: Created slice system-modprobe.slice.
10826 22:14:23.256966 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10827 22:14:23.274682 <30>[ 19.490511] systemd[1]: Created slice system-serial\x2dgetty.slice.
10828 22:14:23.284966 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10829 22:14:23.298720 <30>[ 19.514712] systemd[1]: Created slice User and Session Slice.
10830 22:14:23.305579 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10831 22:14:23.325916 <30>[ 19.538334] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10832 22:14:23.335651 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10833 22:14:23.353962 <30>[ 19.566271] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10834 22:14:23.360038 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10835 22:14:23.380517 <30>[ 19.589910] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10836 22:14:23.387282 <30>[ 19.601946] systemd[1]: Reached target Local Encrypted Volumes.
10837 22:14:23.394196 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10838 22:14:23.410271 <30>[ 19.626128] systemd[1]: Reached target Paths.
10839 22:14:23.413585 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10840 22:14:23.430329 <30>[ 19.645822] systemd[1]: Reached target Remote File Systems.
10841 22:14:23.436688 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10842 22:14:23.454189 <30>[ 19.670033] systemd[1]: Reached target Slices.
10843 22:14:23.460617 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10844 22:14:23.474208 <30>[ 19.689829] systemd[1]: Reached target Swap.
10845 22:14:23.477342 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10846 22:14:23.497544 <30>[ 19.710155] systemd[1]: Listening on initctl Compatibility Named Pipe.
10847 22:14:23.504503 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10848 22:14:23.511174 <30>[ 19.726067] systemd[1]: Listening on Journal Audit Socket.
10849 22:14:23.517676 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10850 22:14:23.535454 <30>[ 19.751191] systemd[1]: Listening on Journal Socket (/dev/log).
10851 22:14:23.541860 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10852 22:14:23.558342 <30>[ 19.774102] systemd[1]: Listening on Journal Socket.
10853 22:14:23.564718 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10854 22:14:23.582492 <30>[ 19.795075] systemd[1]: Listening on Network Service Netlink Socket.
10855 22:14:23.589138 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10856 22:14:23.605178 <30>[ 19.820956] systemd[1]: Listening on udev Control Socket.
10857 22:14:23.611805 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10858 22:14:23.626572 <30>[ 19.842064] systemd[1]: Listening on udev Kernel Socket.
10859 22:14:23.633009 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10860 22:14:23.670649 <30>[ 19.886115] systemd[1]: Mounting Huge Pages File System...
10861 22:14:23.677013 Mounting [0;1;39mHuge Pages File System[0m...
10862 22:14:23.692447 <30>[ 19.908396] systemd[1]: Mounting POSIX Message Queue File System...
10863 22:14:23.699277 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10864 22:14:23.716646 <30>[ 19.932140] systemd[1]: Mounting Kernel Debug File System...
10865 22:14:23.722990 Mounting [0;1;39mKernel Debug File System[0m...
10866 22:14:23.741376 <30>[ 19.954042] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10867 22:14:23.769519 <30>[ 19.982332] systemd[1]: Starting Create list of static device nodes for the current kernel...
10868 22:14:23.776430 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10869 22:14:23.796484 <30>[ 20.012561] systemd[1]: Starting Load Kernel Module configfs...
10870 22:14:23.803233 Starting [0;1;39mLoad Kernel Module configfs[0m...
10871 22:14:23.820249 <30>[ 20.036374] systemd[1]: Starting Load Kernel Module drm...
10872 22:14:23.827100 Starting [0;1;39mLoad Kernel Module drm[0m...
10873 22:14:23.844111 <30>[ 20.060201] systemd[1]: Starting Load Kernel Module fuse...
10874 22:14:23.850777 Starting [0;1;39mLoad Kernel Module fuse[0m...
10875 22:14:23.890143 <30>[ 20.102725] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10876 22:14:23.896519 <6>[ 20.103308] fuse: init (API version 7.37)
10877 22:14:23.918646 <30>[ 20.134443] systemd[1]: Starting Journal Service...
10878 22:14:23.924991 Starting [0;1;39mJournal Service[0m...
10879 22:14:23.948281 <30>[ 20.164116] systemd[1]: Starting Load Kernel Modules...
10880 22:14:23.954750 Starting [0;1;39mLoad Kernel Modules[0m...
10881 22:14:23.976260 <30>[ 20.188752] systemd[1]: Starting Remount Root and Kernel File Systems...
10882 22:14:23.982397 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10883 22:14:24.001480 <30>[ 20.217353] systemd[1]: Starting Coldplug All udev Devices...
10884 22:14:24.007827 Starting [0;1;39mColdplug All udev Devices[0m...
10885 22:14:24.025022 <30>[ 20.240557] systemd[1]: Mounted Huge Pages File System.
10886 22:14:24.031138 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10887 22:14:24.046079 <30>[ 20.262393] systemd[1]: Mounted POSIX Message Queue File System.
10888 22:14:24.053241 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10889 22:14:24.070670 <30>[ 20.286092] systemd[1]: Mounted Kernel Debug File System.
10890 22:14:24.080418 [[0;32m OK [<3>[ 20.293232] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10891 22:14:24.087280 0m] Mounted [0;1;39mKernel Debug File System[0m.
10892 22:14:24.106885 <30>[ 20.319382] systemd[1]: Finished Create list of static device nodes for the current kernel.
10893 22:14:24.116964 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10894 22:14:24.130073 <3>[ 20.341990] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10895 22:14:24.136412 <30>[ 20.352030] systemd[1]: modprobe@configfs.service: Succeeded.
10896 22:14:24.143142 <30>[ 20.358956] systemd[1]: Finished Load Kernel Module configfs.
10897 22:14:24.149701 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10898 22:14:24.165212 <3>[ 20.377147] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10899 22:14:24.171163 <30>[ 20.387125] systemd[1]: modprobe@drm.service: Succeeded.
10900 22:14:24.178113 <30>[ 20.393800] systemd[1]: Finished Load Kernel Module drm.
10901 22:14:24.184650 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10902 22:14:24.196806 <3>[ 20.409592] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10903 22:14:24.204036 <30>[ 20.419588] systemd[1]: modprobe@fuse.service: Succeeded.
10904 22:14:24.210575 <30>[ 20.426281] systemd[1]: Finished Load Kernel Module fuse.
10905 22:14:24.217416 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10906 22:14:24.229217 <3>[ 20.441789] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10907 22:14:24.239063 <30>[ 20.454930] systemd[1]: Finished Load Kernel Modules.
10908 22:14:24.245451 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10909 22:14:24.261369 <3>[ 20.474049] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10910 22:14:24.271691 <30>[ 20.484472] systemd[1]: Finished Remount Root and Kernel File Systems.
10911 22:14:24.278650 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10912 22:14:24.297474 <3>[ 20.510496] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10913 22:14:24.327276 <3>[ 20.539723] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10914 22:14:24.336726 <30>[ 20.553078] systemd[1]: Mounting FUSE Control File System...
10915 22:14:24.343259 Mounting [0;1;39mFUSE Control File System[0m...
10916 22:14:24.356976 <3>[ 20.569766] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10917 22:14:24.371526 <30>[ 20.584533] systemd[1]: Mounting Kernel Configuration File System...
10918 22:14:24.375553 Mounting [0;1;39mKernel Configuration File System[0m...
10919 22:14:24.389449 <3>[ 20.602108] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10920 22:14:24.405293 <30>[ 20.617732] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10921 22:14:24.415067 <30>[ 20.626857] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10922 22:14:24.454326 <30>[ 20.670332] systemd[1]: Starting Load/Save Random Seed...
10923 22:14:24.461077 Starting [0;1;39mLoad/Save Random Seed[0m...
10924 22:14:24.480715 <30>[ 20.696613] systemd[1]: Starting Apply Kernel Variables...
10925 22:14:24.487643 Starting [0;1;39mApply Kernel Variables[0m...
10926 22:14:24.510933 <30>[ 20.726739] systemd[1]: Starting Create System Users...
10927 22:14:24.517266 Starting [0;1;39mCreate System Users[0m...
10928 22:14:24.536124 <30>[ 20.752144] systemd[1]: Started Journal Service.
10929 22:14:24.552709 <4>[ 20.755582] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10930 22:14:24.559120 <3>[ 20.772774] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10931 22:14:24.565891 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10932 22:14:24.581095 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10933 22:14:24.601572 See 'systemctl status systemd-udev-trigger.service' for details.
10934 22:14:24.622095 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10935 22:14:24.638221 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10936 22:14:24.654596 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10937 22:14:24.671174 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10938 22:14:24.686430 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10939 22:14:24.734888 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10940 22:14:24.751816 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10941 22:14:24.798470 <46>[ 21.011252] systemd-journald[300]: Received client request to flush runtime journal.
10942 22:14:25.565478 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10943 22:14:25.577381 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10944 22:14:25.593180 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10945 22:14:25.629460 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10946 22:14:26.189127 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10947 22:14:26.230687 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10948 22:14:26.303156 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10949 22:14:26.366666 Starting [0;1;39mNetwork Service[0m...
10950 22:14:26.637109 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10951 22:14:26.657202 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10952 22:14:26.709210 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10953 22:14:26.915883 <6>[ 23.132642] remoteproc remoteproc0: powering up scp
10954 22:14:26.944714 <4>[ 23.157955] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10955 22:14:26.951256 <3>[ 23.167832] remoteproc remoteproc0: request_firmware failed: -2
10956 22:14:26.961123 <3>[ 23.174016] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
10957 22:14:27.099153 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10958 22:14:27.117788 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10959 22:14:27.134446 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10960 22:14:27.155414 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10961 22:14:27.173433 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10962 22:14:27.222153 Starting [0;1;39mNetwork Name Resolution[0m...
10963 22:14:27.248883 Starting [0;1;39mNetwork Time Synchronization[0m...
10964 22:14:27.267988 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10965 22:14:27.289650 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10966 22:14:27.318963 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10967 22:14:27.347735 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10968 22:14:27.520825 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10969 22:14:27.541859 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10970 22:14:27.560716 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10971 22:14:27.573236 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10972 22:14:27.593138 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10973 22:14:27.698706 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10974 22:14:27.731109 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10975 22:14:27.755460 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10976 22:14:27.805009 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10977 22:14:27.818071 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10978 22:14:28.187511 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10979 22:14:28.201042 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10980 22:14:28.217217 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10981 22:14:28.261403 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10982 22:14:28.581765 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10983 22:14:28.945835 Starting [0;1;39mUser Login Management[0m...
10984 22:14:28.962245 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10985 22:14:28.978755 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10986 22:14:28.996162 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10987 22:14:29.050024 Starting [0;1;39mPermit User Sessions[0m...
10988 22:14:29.147408 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10989 22:14:29.171032 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10990 22:14:29.209708 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10991 22:14:29.228456 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10992 22:14:29.245379 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10993 22:14:29.265518 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10994 22:14:29.282750 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10995 22:14:29.298246 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10996 22:14:29.353425 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10997 22:14:29.398320 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10998 22:14:29.458072
10999 22:14:29.458725
11000 22:14:29.461473 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11001 22:14:29.462009
11002 22:14:29.464102 debian-bullseye-arm64 login: root (automatic login)
11003 22:14:29.464716
11004 22:14:29.465277
11005 22:14:29.809909 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Sun Jun 4 21:56:05 UTC 2023 aarch64
11006 22:14:29.810083
11007 22:14:29.816721 The programs included with the Debian GNU/Linux system are free software;
11008 22:14:29.823211 the exact distribution terms for each program are described in the
11009 22:14:29.826460 individual files in /usr/share/doc/*/copyright.
11010 22:14:29.826539
11011 22:14:29.832810 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11012 22:14:29.836247 permitted by applicable law.
11013 22:14:29.914347 Matched prompt #10: / #
11015 22:14:29.914619 Setting prompt string to ['/ #']
11016 22:14:29.914715 end: 2.2.5.1 login-action (duration 00:00:27) [common]
11018 22:14:29.914917 end: 2.2.5 auto-login-action (duration 00:00:27) [common]
11019 22:14:29.915010 start: 2.2.6 expect-shell-connection (timeout 00:03:12) [common]
11020 22:14:29.915084 Setting prompt string to ['/ #']
11021 22:14:29.915147 Forcing a shell prompt, looking for ['/ #']
11023 22:14:29.965377 / #
11024 22:14:29.965547 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11025 22:14:29.965652 Waiting using forced prompt support (timeout 00:02:30)
11026 22:14:29.970304
11027 22:14:29.970644 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11028 22:14:29.970779 start: 2.2.7 export-device-env (timeout 00:03:12) [common]
11030 22:14:30.071219 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10583854/extract-nfsrootfs-3sh0d8r1'
11031 22:14:30.076476 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10583854/extract-nfsrootfs-3sh0d8r1'
11033 22:14:30.177070 / # export NFS_SERVER_IP='192.168.201.1'
11034 22:14:30.182654 export NFS_SERVER_IP='192.168.201.1'
11035 22:14:30.182955 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11036 22:14:30.183057 end: 2.2 depthcharge-retry (duration 00:01:48) [common]
11037 22:14:30.183150 end: 2 depthcharge-action (duration 00:01:48) [common]
11038 22:14:30.183242 start: 3 lava-test-retry (timeout 00:01:00) [common]
11039 22:14:30.183328 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
11040 22:14:30.183402 Using namespace: common
11042 22:14:30.283769 / # #
11043 22:14:30.283984 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
11044 22:14:30.288810 #
11045 22:14:30.289084 Using /lava-10583854
11047 22:14:30.389498 / # export SHELL=/bin/sh
11048 22:14:30.394539 export SHELL=/bin/sh
11050 22:14:30.495118 / # . /lava-10583854/environment
11051 22:14:30.500092 . /lava-10583854/environment
11053 22:14:30.605929 / # /lava-10583854/bin/lava-test-runner /lava-10583854/0
11054 22:14:30.606106 Test shell timeout: 10s (minimum of the action and connection timeout)
11055 22:14:30.611430 /lava-10583854/bin/lava-test-runner /lava-10583854/0
11056 22:14:30.850880 + export TESTRUN_ID=0_dmesg
11057 22:14:30.853600 + cd /lava-10583854/0/tests/0_dmesg
11058 22:14:30.857138 + cat uuid
11059 22:14:30.871682 + UUID=10583854_1.<8>[ 27.085776] <LAVA_SIGNAL_STARTRUN 0_dmesg 10583854_1.6.2.3.1>
11060 22:14:30.871819 6.2.3.1
11061 22:14:30.871889 + set +x
11062 22:14:30.872134 Received signal: <STARTRUN> 0_dmesg 10583854_1.6.2.3.1
11063 22:14:30.872211 Starting test lava.0_dmesg (10583854_1.6.2.3.1)
11064 22:14:30.872300 Skipping test definition patterns.
11065 22:14:30.878239 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
11066 22:14:30.981770 <8>[ 27.195502] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
11067 22:14:30.982098 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
11069 22:14:31.062463 <8>[ 27.276228] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
11070 22:14:31.062792 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
11072 22:14:31.150812 <8>[ 27.364657] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
11073 22:14:31.151139 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
11075 22:14:31.154091 + set +x
11076 22:14:31.157400 <8>[ 27.374345] <LAVA_SIGNAL_ENDRUN 0_dmesg 10583854_1.6.2.3.1>
11077 22:14:31.157668 Received signal: <ENDRUN> 0_dmesg 10583854_1.6.2.3.1
11078 22:14:31.157759 Ending use of test pattern.
11079 22:14:31.157857 Ending test lava.0_dmesg (10583854_1.6.2.3.1), duration 0.29
11081 22:14:31.162945 <LAVA_TEST_RUNNER EXIT>
11082 22:14:31.163263 ok: lava_test_shell seems to have completed
11083 22:14:31.163396 alert: pass
crit: pass
emerg: pass
11084 22:14:31.163502 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11085 22:14:31.163665 end: 3 lava-test-retry (duration 00:00:01) [common]
11086 22:14:31.163765 start: 4 lava-test-retry (timeout 00:01:00) [common]
11087 22:14:31.163864 start: 4.1 lava-test-shell (timeout 00:01:00) [common]
11088 22:14:31.163964 Using namespace: common
11090 22:14:31.264397 / # #
11091 22:14:31.264580 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
11092 22:14:31.264725 Using /lava-10583854
11094 22:14:31.365074 export SHELL=/bin/sh
11095 22:14:31.365304 #
11097 22:14:31.465834 / # export SHELL=/bin/sh. /lava-10583854/environment
11098 22:14:31.466058
11100 22:14:31.566633 / # . /lava-10583854/environment/lava-10583854/bin/lava-test-runner /lava-10583854/1
11101 22:14:31.566816 Test shell timeout: 10s (minimum of the action and connection timeout)
11102 22:14:31.566970
11103 22:14:31.571881 / # /lava-10583854/bin/lava-test-runner /lava-10583854/1
11104 22:14:31.683901 + export TESTRUN_ID=1_bootrr
11105 22:14:31.687244 + cd /lava-10583854/1/tests/1_bootrr
11106 22:14:31.689935 + cat uuid
11107 22:14:31.702718 + UUID=10583854_1.<8>[ 27.916628] <LAVA_SIGNAL_STARTRUN 1_bootrr 10583854_1.6.2.3.5>
11108 22:14:31.702849 6.2.3.5
11109 22:14:31.702920 + set +x
11110 22:14:31.703162 Received signal: <STARTRUN> 1_bootrr 10583854_1.6.2.3.5
11111 22:14:31.703235 Starting test lava.1_bootrr (10583854_1.6.2.3.5)
11112 22:14:31.703314 Skipping test definition patterns.
11113 22:14:31.716231 + export PATH=/opt/bootrr/libexec/bootrr/helpers:/lava-10583854/1/../bin:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin
11114 22:14:31.718820 + cd /opt/bootrr/libexec/bootrr
11115 22:14:31.718921 + sh helpers/bootrr-auto
11116 22:14:31.781843 /lava-10583854/1/../bin/lava-test-case
11117 22:14:31.889329 <8>[ 28.102774] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=deferred-probe-empty RESULT=pass>
11118 22:14:31.889670 Received signal: <TESTCASE> TEST_CASE_ID=deferred-probe-empty RESULT=pass
11120 22:14:31.942002 /lava-10583854/1/../bin/lava-test-case
11121 22:14:31.983839 <8>[ 28.197636] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=all-cpus-are-online RESULT=pass>
11122 22:14:31.984215 Received signal: <TESTCASE> TEST_CASE_ID=all-cpus-are-online RESULT=pass
11124 22:14:32.012757 /lava-10583854/1/../bin/lava-test-case
11125 22:14:32.090264 <8>[ 28.304421] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm-chip-is-online RESULT=skip>
11126 22:14:32.090593 Received signal: <TESTCASE> TEST_CASE_ID=tpm-chip-is-online RESULT=skip
11128 22:14:32.152256 /lava-10583854/1/../bin/lava-test-case
11129 22:14:32.181478 <8>[ 28.395517] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass>
11130 22:14:32.181788 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass
11132 22:14:32.219829 /lava-10583854/1/../bin/lava-test-case
11133 22:14:32.249424 <8>[ 28.463469] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass>
11134 22:14:32.249744 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass
11136 22:14:32.289053 /lava-10583854/1/../bin/lava-test-case
11137 22:14:32.333525 <8>[ 28.547426] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass>
11138 22:14:32.333852 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass
11140 22:14:32.377130 /lava-10583854/1/../bin/lava-test-case
11141 22:14:32.404733 <8>[ 28.618808] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass>
11142 22:14:32.405061 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass
11144 22:14:32.444658 /lava-10583854/1/../bin/lava-test-case
11145 22:14:32.473757 <8>[ 28.687754] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass>
11146 22:14:32.474083 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass
11148 22:14:32.497398 /lava-10583854/1/../bin/lava-test-case
11149 22:14:32.525036 <8>[ 28.739068] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass>
11150 22:14:32.525396 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass
11152 22:14:32.565828 /lava-10583854/1/../bin/lava-test-case
11153 22:14:32.595882 <8>[ 28.809890] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass>
11154 22:14:32.596205 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass
11156 22:14:32.619103 /lava-10583854/1/../bin/lava-test-case
11157 22:14:32.647924 <8>[ 28.861866] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass>
11158 22:14:32.648261 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass
11160 22:14:32.695393 /lava-10583854/1/../bin/lava-test-case
11161 22:14:32.725237 <8>[ 28.939609] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass>
11162 22:14:32.725586 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass
11164 22:14:32.761667 /lava-10583854/1/../bin/lava-test-case
11165 22:14:32.790087 <8>[ 29.003452] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass>
11166 22:14:32.790404 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass
11168 22:14:32.827052 /lava-10583854/1/../bin/lava-test-case
11169 22:14:32.858834 <8>[ 29.073270] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass>
11170 22:14:32.859155 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass
11172 22:14:32.895690 /lava-10583854/1/../bin/lava-test-case
11173 22:14:32.925133 <8>[ 29.139253] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass>
11174 22:14:32.925454 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass
11176 22:14:32.949765 /lava-10583854/1/../bin/lava-test-case
11177 22:14:32.985583 <8>[ 29.199801] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass>
11178 22:14:32.985922 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass
11180 22:14:33.026530 /lava-10583854/1/../bin/lava-test-case
11181 22:14:33.055846 <8>[ 29.270132] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass>
11182 22:14:33.056201 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass
11184 22:14:33.079808 /lava-10583854/1/../bin/lava-test-case
11185 22:14:33.112839 <8>[ 29.326648] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass>
11186 22:14:33.113162 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass
11188 22:14:33.151203 /lava-10583854/1/../bin/lava-test-case
11189 22:14:33.182332 <8>[ 29.396267] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass>
11190 22:14:33.182655 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass
11192 22:14:33.206496 /lava-10583854/1/../bin/lava-test-case
11193 22:14:33.233536 <8>[ 29.447741] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass>
11194 22:14:33.233847 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass
11196 22:14:33.269329 /lava-10583854/1/../bin/lava-test-case
11197 22:14:33.297860 <8>[ 29.512134] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-probed RESULT=pass>
11198 22:14:33.298185 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-probed RESULT=pass
11200 22:14:33.327234 /lava-10583854/1/../bin/lava-test-case
11201 22:14:33.355298 <8>[ 29.569665] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass>
11202 22:14:33.355622 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass
11204 22:14:33.388723 /lava-10583854/1/../bin/lava-test-case
11205 22:14:33.414308 <8>[ 29.628472] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass>
11206 22:14:33.414627 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass
11208 22:14:33.439132 /lava-10583854/1/../bin/lava-test-case
11209 22:14:33.468448 <8>[ 29.682707] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass>
11210 22:14:33.468785 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass
11212 22:14:33.501335 /lava-10583854/1/../bin/lava-test-case
11213 22:14:33.528261 <8>[ 29.741975] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass>
11214 22:14:33.528580 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass
11216 22:14:33.568025 /lava-10583854/1/../bin/lava-test-case
11217 22:14:33.600579 <8>[ 29.814664] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass>
11218 22:14:33.600893 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass
11220 22:14:33.630171 /lava-10583854/1/../bin/lava-test-case
11221 22:14:33.662691 <8>[ 29.876802] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass>
11222 22:14:33.663000 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass
11224 22:14:33.703176 /lava-10583854/1/../bin/lava-test-case
11225 22:14:33.733765 <8>[ 29.947770] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass>
11226 22:14:33.734087 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass
11228 22:14:33.756014 /lava-10583854/1/../bin/lava-test-case
11229 22:14:33.786351 <8>[ 30.000403] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass>
11230 22:14:33.786671 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass
11232 22:14:33.826576 /lava-10583854/1/../bin/lava-test-case
11233 22:14:33.855571 <8>[ 30.069472] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass>
11234 22:14:33.855914 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass
11236 22:14:33.894039 /lava-10583854/1/../bin/lava-test-case
11237 22:14:33.927696 <8>[ 30.142022] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass>
11238 22:14:33.928037 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass
11240 22:14:33.963296 /lava-10583854/1/../bin/lava-test-case
11241 22:14:33.990458 <8>[ 30.204678] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass>
11242 22:14:33.990782 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass
11244 22:14:34.030155 /lava-10583854/1/../bin/lava-test-case
11245 22:14:34.055461 <8>[ 30.270070] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass>
11246 22:14:34.055818 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass
11248 22:14:34.077272 /lava-10583854/1/../bin/lava-test-case
11249 22:14:34.104222 <8>[ 30.318186] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass>
11250 22:14:34.104548 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass
11252 22:14:34.138317 /lava-10583854/1/../bin/lava-test-case
11253 22:14:34.169419 <8>[ 30.383874] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass>
11254 22:14:34.169742 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass
11256 22:14:34.207515 /lava-10583854/1/../bin/lava-test-case
11257 22:14:34.236451 <8>[ 30.450937] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass>
11258 22:14:34.236771 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass
11260 22:14:34.260133 /lava-10583854/1/../bin/lava-test-case
11261 22:14:34.291379 <8>[ 30.505751] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass>
11262 22:14:34.291729 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass
11264 22:14:34.335971 /lava-10583854/1/../bin/lava-test-case
11265 22:14:34.366202 <8>[ 30.580541] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass>
11266 22:14:34.366517 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass
11268 22:14:34.387979 /lava-10583854/1/../bin/lava-test-case
11269 22:14:34.417732 <8>[ 30.631843] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass>
11270 22:14:34.418059 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass
11272 22:14:34.452557 /lava-10583854/1/../bin/lava-test-case
11273 22:14:34.479347 <8>[ 30.693859] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass>
11274 22:14:34.479714 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass
11276 22:14:34.501607 /lava-10583854/1/../bin/lava-test-case
11277 22:14:34.528203 <8>[ 30.742620] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass>
11278 22:14:34.528527 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass
11280 22:14:34.566606 /lava-10583854/1/../bin/lava-test-case
11281 22:14:34.593288 <8>[ 30.807532] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass>
11282 22:14:34.593609 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass
11284 22:14:34.615500 /lava-10583854/1/../bin/lava-test-case
11285 22:14:34.647000 <8>[ 30.861137] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass>
11286 22:14:34.647324 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass
11288 22:14:34.691418 /lava-10583854/1/../bin/lava-test-case
11289 22:14:34.722274 <8>[ 30.936878] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-probed RESULT=pass>
11290 22:14:34.722597 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-probed RESULT=pass
11292 22:14:34.746055 /lava-10583854/1/../bin/lava-test-case
11293 22:14:34.772408 <8>[ 30.986809] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass>
11294 22:14:34.772724 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass
11296 22:14:34.808328 /lava-10583854/1/../bin/lava-test-case
11297 22:14:34.835878 <8>[ 31.050193] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass>
11298 22:14:34.836200 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass
11300 22:14:34.858819 /lava-10583854/1/../bin/lava-test-case
11301 22:14:34.889315 <8>[ 31.103499] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass>
11302 22:14:34.889636 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass
11304 22:14:34.926199 /lava-10583854/1/../bin/lava-test-case
11305 22:14:34.955550 <8>[ 31.170158] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-probed RESULT=pass>
11306 22:14:34.955918 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-probed RESULT=pass
11308 22:14:34.980959 /lava-10583854/1/../bin/lava-test-case
11309 22:14:35.013625 <8>[ 31.227662] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass>
11310 22:14:35.013953 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass
11312 22:14:35.054877 /lava-10583854/1/../bin/lava-test-case
11313 22:14:35.089844 <8>[ 31.304011] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass>
11314 22:14:35.090164 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass
11316 22:14:35.123734 /lava-10583854/1/../bin/lava-test-case
11317 22:14:35.152850 <8>[ 31.367253] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass>
11318 22:14:35.153172 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass
11320 22:14:36.194632 /lava-10583854/1/../bin/lava-test-case
11321 22:14:36.222604 <8>[ 32.436572] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=fail>
11322 22:14:36.222986 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=fail
11324 22:14:37.258277 /lava-10583854/1/../bin/lava-test-case
11325 22:14:37.285534 <8>[ 33.500266] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=blocked>
11326 22:14:37.285864 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=blocked
11327 22:14:37.285988 Bad test result: blocked
11328 22:14:37.309938 /lava-10583854/1/../bin/lava-test-case
11329 22:14:37.393905 <8>[ 33.608250] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass>
11330 22:14:37.394344 Received signal: <TESTCASE> TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass
11332 22:14:37.426651 /lava-10583854/1/../bin/lava-test-case
11333 22:14:37.470557 <8>[ 33.685158] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass>
11334 22:14:37.470877 Received signal: <TESTCASE> TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass
11336 22:14:37.504098 /lava-10583854/1/../bin/lava-test-case
11337 22:14:37.533295 <8>[ 33.747938] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass>
11338 22:14:37.533614 Received signal: <TESTCASE> TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass
11340 22:14:37.575129 /lava-10583854/1/../bin/lava-test-case
11341 22:14:37.602412 <8>[ 33.817002] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass>
11342 22:14:37.602749 Received signal: <TESTCASE> TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass
11344 22:14:37.638694 /lava-10583854/1/../bin/lava-test-case
11345 22:14:37.674266 <8>[ 33.888980] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass>
11346 22:14:37.674587 Received signal: <TESTCASE> TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass
11348 22:14:37.712113 /lava-10583854/1/../bin/lava-test-case
11349 22:14:37.741131 <8>[ 33.955949] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass>
11350 22:14:37.741448 Received signal: <TESTCASE> TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass
11352 22:14:37.765078 /lava-10583854/1/../bin/lava-test-case
11353 22:14:37.794490 <8>[ 34.009116] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-driver-present RESULT=pass>
11354 22:14:37.794803 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-driver-present RESULT=pass
11356 22:14:37.828991 /lava-10583854/1/../bin/lava-test-case
11357 22:14:37.854485 <8>[ 34.069405] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi1-probed RESULT=pass>
11358 22:14:37.854853 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi1-probed RESULT=pass
11360 22:14:37.897716 /lava-10583854/1/../bin/lava-test-case
11361 22:14:37.926328 <8>[ 34.140958] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi5-probed RESULT=pass>
11362 22:14:37.926662 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi5-probed RESULT=pass
11364 22:14:37.948570 /lava-10583854/1/../bin/lava-test-case
11365 22:14:37.976401 <8>[ 34.191292] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass>
11366 22:14:37.976699 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass
11368 22:14:38.014766 /lava-10583854/1/../bin/lava-test-case
11369 22:14:38.048322 <8>[ 34.262885] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-probed RESULT=pass>
11370 22:14:38.048646 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-probed RESULT=pass
11372 22:14:38.070660 /lava-10583854/1/../bin/lava-test-case
11373 22:14:38.100824 <8>[ 34.315675] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass>
11374 22:14:38.101131 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass
11376 22:14:38.140749 /lava-10583854/1/../bin/lava-test-case
11377 22:14:38.169155 <8>[ 34.383856] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-probed RESULT=pass>
11378 22:14:38.169459 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-probed RESULT=pass
11380 22:14:38.191387 /lava-10583854/1/../bin/lava-test-case
11381 22:14:38.219025 <8>[ 34.433849] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass>
11382 22:14:38.219332 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass
11384 22:14:38.263237 /lava-10583854/1/../bin/lava-test-case
11385 22:14:38.292537 <8>[ 34.506943] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass>
11386 22:14:38.292846 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass
11388 22:14:38.329096 /lava-10583854/1/../bin/lava-test-case
11389 22:14:38.358073 <8>[ 34.572883] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass>
11390 22:14:38.358379 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass
11392 22:14:38.393841 /lava-10583854/1/../bin/lava-test-case
11393 22:14:38.423542 <8>[ 34.638142] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass>
11394 22:14:38.423921 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass
11396 22:14:38.459740 /lava-10583854/1/../bin/lava-test-case
11397 22:14:38.489988 <8>[ 34.704610] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass>
11398 22:14:38.490306 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass
11400 22:14:38.527462 /lava-10583854/1/../bin/lava-test-case
11401 22:14:38.554508 <8>[ 34.769454] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass>
11402 22:14:38.554826 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass
11404 22:14:38.597877 /lava-10583854/1/../bin/lava-test-case
11405 22:14:38.630609 <8>[ 34.845372] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass>
11406 22:14:38.630936 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass
11408 22:14:38.666065 /lava-10583854/1/../bin/lava-test-case
11409 22:14:38.695796 <8>[ 34.910587] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass>
11410 22:14:38.696118 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass
11412 22:14:38.735531 /lava-10583854/1/../bin/lava-test-case
11413 22:14:38.764919 <8>[ 34.979462] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass>
11414 22:14:38.765247 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass
11416 22:14:38.803999 /lava-10583854/1/../bin/lava-test-case
11417 22:14:38.836485 <8>[ 35.051506] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass>
11418 22:14:38.836816 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass
11420 22:14:38.876191 /lava-10583854/1/../bin/lava-test-case
11421 22:14:38.909267 <8>[ 35.123956] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass>
11422 22:14:38.909651 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass
11424 22:14:38.951492 /lava-10583854/1/../bin/lava-test-case
11425 22:14:38.979092 <8>[ 35.193959] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass>
11426 22:14:38.979459 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass
11428 22:14:39.014578 /lava-10583854/1/../bin/lava-test-case
11429 22:14:39.041924 <8>[ 35.256982] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass>
11430 22:14:39.042309 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass
11432 22:14:39.075526 /lava-10583854/1/../bin/lava-test-case
11433 22:14:39.103556 <8>[ 35.318050] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass>
11434 22:14:39.103961 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass
11436 22:14:39.144247 /lava-10583854/1/../bin/lava-test-case
11437 22:14:39.174097 <8>[ 35.389119] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass>
11438 22:14:39.174465 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass
11440 22:14:39.207708 /lava-10583854/1/../bin/lava-test-case
11441 22:14:39.233636 <8>[ 35.448620] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass>
11442 22:14:39.234004 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass
11444 22:14:39.263519 /lava-10583854/1/../bin/lava-test-case
11445 22:14:39.288891 <8>[ 35.503707] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass>
11446 22:14:39.289279 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass
11448 22:14:39.326065 /lava-10583854/1/../bin/lava-test-case
11449 22:14:39.354475 <8>[ 35.569329] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-probed RESULT=pass>
11450 22:14:39.354863 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-probed RESULT=pass
11452 22:14:39.376600 /lava-10583854/1/../bin/lava-test-case
11453 22:14:39.404654 <8>[ 35.619468] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass>
11454 22:14:39.405050 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass
11456 22:14:39.437466 /lava-10583854/1/../bin/lava-test-case
11457 22:14:39.468433 <8>[ 35.683387] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-probed RESULT=pass>
11458 22:14:39.468824 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-probed RESULT=pass
11460 22:14:39.492481 /lava-10583854/1/../bin/lava-test-case
11461 22:14:39.522036 <8>[ 35.736744] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass>
11462 22:14:39.522432 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass
11464 22:14:39.560755 /lava-10583854/1/../bin/lava-test-case
11465 22:14:39.592919 <8>[ 35.807983] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass>
11466 22:14:39.593311 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass
11468 22:14:39.616715 /lava-10583854/1/../bin/lava-test-case
11469 22:14:39.645012 <8>[ 35.859837] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass>
11470 22:14:39.645412 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass
11472 22:14:39.684218 /lava-10583854/1/../bin/lava-test-case
11473 22:14:39.713416 <8>[ 35.928446] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-probed RESULT=pass>
11474 22:14:39.713807 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-probed RESULT=pass
11476 22:14:39.737901 /lava-10583854/1/../bin/lava-test-case
11477 22:14:39.766053 <8>[ 35.980971] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass>
11478 22:14:39.766445 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass
11480 22:14:39.804592 /lava-10583854/1/../bin/lava-test-case
11481 22:14:39.834174 <8>[ 36.049375] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass>
11482 22:14:39.834555 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass
11484 22:14:39.857164 /lava-10583854/1/../bin/lava-test-case
11485 22:14:39.888134 <8>[ 36.103354] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass>
11486 22:14:39.888501 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass
11488 22:14:39.930489 /lava-10583854/1/../bin/lava-test-case
11489 22:14:39.962446 <8>[ 36.177151] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass>
11490 22:14:39.962771 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass
11492 22:14:39.998747 /lava-10583854/1/../bin/lava-test-case
11493 22:14:40.027173 <8>[ 36.241901] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass>
11494 22:14:40.027487 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass
11496 22:14:40.052020 /lava-10583854/1/../bin/lava-test-case
11497 22:14:40.080395 <8>[ 36.295522] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass>
11498 22:14:40.080706 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass
11500 22:14:40.117169 /lava-10583854/1/../bin/lava-test-case
11501 22:14:40.146897 <8>[ 36.361862] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass>
11502 22:14:40.147214 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass
11504 22:14:40.172360 /lava-10583854/1/../bin/lava-test-case
11505 22:14:40.201315 <8>[ 36.416263] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-driver-present RESULT=pass>
11506 22:14:40.201627 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-driver-present RESULT=pass
11508 22:14:40.237455 /lava-10583854/1/../bin/lava-test-case
11509 22:14:40.267451 <8>[ 36.482362] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-probed RESULT=pass>
11510 22:14:40.267746 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-probed RESULT=pass
11512 22:14:40.296460 /lava-10583854/1/../bin/lava-test-case
11513 22:14:40.329122 <8>[ 36.543936] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-driver-present RESULT=pass>
11514 22:14:40.329385 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-driver-present RESULT=pass
11516 22:14:41.379773 /lava-10583854/1/../bin/lava-test-case
11517 22:14:41.412189 <8>[ 37.627521] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-probed RESULT=fail>
11518 22:14:41.412517 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-probed RESULT=fail
11520 22:14:41.436415 /lava-10583854/1/../bin/lava-test-case
11521 22:14:41.466908 <8>[ 37.681691] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-driver-present RESULT=pass>
11522 22:14:41.467232 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-driver-present RESULT=pass
11524 22:14:42.515270 /lava-10583854/1/../bin/lava-test-case
11525 22:14:42.555984 <8>[ 38.770738] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-probed RESULT=fail>
11526 22:14:42.556836 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-probed RESULT=fail
11528 22:14:42.582398 /lava-10583854/1/../bin/lava-test-case
11529 22:14:42.622615 <8>[ 38.837649] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass>
11530 22:14:42.623318 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass
11532 22:14:43.684437 /lava-10583854/1/../bin/lava-test-case
11533 22:14:43.722494 <8>[ 39.937548] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail>
11534 22:14:43.723217 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail
11536 22:14:43.750783 /lava-10583854/1/../bin/lava-test-case
11537 22:14:43.784884 <8>[ 39.999685] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass>
11538 22:14:43.785690 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass
11540 22:14:44.843821 /lava-10583854/1/../bin/lava-test-case
11541 22:14:44.885809 <8>[ 41.101156] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-probed RESULT=fail>
11542 22:14:44.886414 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-probed RESULT=fail
11544 22:14:44.912759 /lava-10583854/1/../bin/lava-test-case
11545 22:14:44.947072 <8>[ 41.162327] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-driver-present RESULT=pass>
11546 22:14:44.947664 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-driver-present RESULT=pass
11548 22:14:46.001649 /lava-10583854/1/../bin/lava-test-case
11549 22:14:46.043548 <8>[ 42.258797] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-3-probed RESULT=fail>
11550 22:14:46.044287 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-3-probed RESULT=fail
11552 22:14:46.070270 /lava-10583854/1/../bin/lava-test-case
11553 22:14:46.107679 <8>[ 42.323041] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass>
11554 22:14:46.108600 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass
11556 22:14:47.165318 /lava-10583854/1/../bin/lava-test-case
11557 22:14:47.209243 <8>[ 43.424701] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail>
11558 22:14:47.210022 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail
11560 22:14:47.237942 /lava-10583854/1/../bin/lava-test-case
11561 22:14:47.276946 <8>[ 43.492364] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass>
11562 22:14:47.277645 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass
11564 22:14:48.333522 /lava-10583854/1/../bin/lava-test-case
11565 22:14:48.368264 <8>[ 44.584041] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-probed RESULT=fail>
11566 22:14:48.368881 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-probed RESULT=fail
11568 22:14:48.394853 /lava-10583854/1/../bin/lava-test-case
11569 22:14:48.428109 <8>[ 44.643728] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-edp-driver-present RESULT=pass>
11570 22:14:48.428676 Received signal: <TESTCASE> TEST_CASE_ID=panel-edp-driver-present RESULT=pass
11572 22:14:48.453210 /lava-10583854/1/../bin/lava-test-case
11573 22:14:48.484905 <8>[ 44.700768] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass>
11574 22:14:48.485187 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass
11576 22:14:49.538740 /lava-10583854/1/../bin/lava-test-case
11577 22:14:49.575544 <8>[ 45.791666] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail>
11578 22:14:49.576392 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail
11580 22:14:49.602500 /lava-10583854/1/../bin/lava-test-case
11581 22:14:49.639434 <8>[ 45.855183] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass>
11582 22:14:49.639918 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass
11584 22:14:49.680883 /lava-10583854/1/../bin/lava-test-case
11585 22:14:49.712757 <8>[ 45.929043] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-probed RESULT=pass>
11586 22:14:49.713240 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-probed RESULT=pass
11588 22:14:49.736262 /lava-10583854/1/../bin/lava-test-case
11589 22:14:49.765090 <8>[ 45.981095] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass>
11590 22:14:49.765441 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass
11592 22:14:49.800963 /lava-10583854/1/../bin/lava-test-case
11593 22:14:49.833578 <8>[ 46.049649] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass>
11594 22:14:49.834366 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass
11596 22:14:49.882097 /lava-10583854/1/../bin/lava-test-case
11597 22:14:49.915270 <8>[ 46.130948] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass>
11598 22:14:49.916042 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass
11600 22:14:49.931204 <6>[ 46.153648] vpu: disabling
11601 22:14:49.935056 <6>[ 46.156714] vproc2: disabling
11602 22:14:49.937669 <6>[ 46.159982] vproc1: disabling
11603 22:14:49.940925 <6>[ 46.163242] vaud18: disabling
11604 22:14:49.947634 <6>[ 46.166654] vsram_others: disabling
11605 22:14:49.950628 <6>[ 46.170526] va09: disabling
11606 22:14:49.954628 <6>[ 46.173629] vsram_md: disabling
11607 22:14:49.957611 /lava-10583854/1<6>[ 46.177117] Vgpu: disabling
11608 22:14:49.960552 /../bin/lava-test-case
11609 22:14:49.988187 <8>[ 46.204340] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass>
11610 22:14:49.988542 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass
11612 22:14:50.014143 /lava-10583854/1/../bin/lava-test-case
11613 22:14:50.047889 <8>[ 46.263752] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass>
11614 22:14:50.048273 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass
11616 22:14:50.081564 /lava-10583854/1/../bin/lava-test-case
11617 22:14:50.109645 <8>[ 46.325359] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass>
11618 22:14:50.109997 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass
11620 22:14:50.147188 /lava-10583854/1/../bin/lava-test-case
11621 22:14:50.179720 <8>[ 46.395108] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass>
11622 22:14:50.180563 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass
11624 22:14:50.219252 /lava-10583854/1/../bin/lava-test-case
11625 22:14:50.251988 <8>[ 46.467871] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass>
11626 22:14:50.252809 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass
11628 22:14:50.294018 /lava-10583854/1/../bin/lava-test-case
11629 22:14:50.331292 <8>[ 46.546903] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass>
11630 22:14:50.332171 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass
11632 22:14:50.357373 /lava-10583854/1/../bin/lava-test-case
11633 22:14:50.389498 <8>[ 46.605062] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass>
11634 22:14:50.390349 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass
11636 22:14:50.432028 /lava-10583854/1/../bin/lava-test-case
11637 22:14:50.468908 <8>[ 46.684166] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass>
11638 22:14:50.469785 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass
11640 22:14:50.494488 /lava-10583854/1/../bin/lava-test-case
11641 22:14:50.524713 <8>[ 46.740808] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass>
11642 22:14:50.525023 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass
11644 22:14:50.570836 /lava-10583854/1/../bin/lava-test-case
11645 22:14:50.600951 <8>[ 46.816938] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass>
11646 22:14:50.601279 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass
11648 22:14:50.624330 /lava-10583854/1/../bin/lava-test-case
11649 22:14:50.652717 <8>[ 46.868657] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass>
11650 22:14:50.653150 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass
11652 22:14:50.690901 /lava-10583854/1/../bin/lava-test-case
11653 22:14:50.719782 <8>[ 46.935833] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass>
11654 22:14:50.720164 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass
11656 22:14:50.743449 /lava-10583854/1/../bin/lava-test-case
11657 22:14:50.773820 <8>[ 46.990241] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass>
11658 22:14:50.774142 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass
11660 22:14:50.808886 /lava-10583854/1/../bin/lava-test-case
11661 22:14:50.842457 <8>[ 47.058485] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-probed RESULT=pass>
11662 22:14:50.842759 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-probed RESULT=pass
11664 22:14:50.864562 /lava-10583854/1/../bin/lava-test-case
11665 22:14:50.894478 <8>[ 47.110775] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass>
11666 22:14:50.894776 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass
11668 22:14:51.950746 /lava-10583854/1/../bin/lava-test-case
11669 22:14:51.982360 <8>[ 48.198643] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-probed RESULT=fail>
11670 22:14:51.982642 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-probed RESULT=fail
11672 22:14:53.028719 /lava-10583854/1/../bin/lava-test-case
11673 22:14:53.057080 <8>[ 49.273457] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-7-probed RESULT=fail>
11674 22:14:53.057374 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-7-probed RESULT=fail
11676 22:14:53.081551 /lava-10583854/1/../bin/lava-test-case
11677 22:14:53.114377 <8>[ 49.330681] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-driver-present RESULT=pass>
11678 22:14:53.114635 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-driver-present RESULT=pass
11680 22:14:53.151239 /lava-10583854/1/../bin/lava-test-case
11681 22:14:53.185115 <8>[ 49.401721] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-probed RESULT=pass>
11682 22:14:53.185381 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-probed RESULT=pass
11684 22:14:53.208610 /lava-10583854/1/../bin/lava-test-case
11685 22:14:53.238360 <8>[ 49.454778] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass>
11686 22:14:53.238618 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass
11688 22:14:53.279079 /lava-10583854/1/../bin/lava-test-case
11689 22:14:53.313754 <8>[ 49.530172] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass>
11690 22:14:53.314021 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass
11692 22:14:53.336400 /lava-10583854/1/../bin/lava-test-case
11693 22:14:53.364116 <8>[ 49.580922] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-driver-present RESULT=pass>
11694 22:14:53.364377 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-driver-present RESULT=pass
11696 22:14:53.402524 /lava-10583854/1/../bin/lava-test-case
11697 22:14:53.434099 <8>[ 49.650440] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-probed RESULT=pass>
11698 22:14:53.434392 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-probed RESULT=pass
11700 22:14:53.456253 /lava-10583854/1/../bin/lava-test-case
11701 22:14:53.488243 <8>[ 49.704852] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass>
11702 22:14:53.488502 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass
11704 22:14:53.526042 /lava-10583854/1/../bin/lava-test-case
11705 22:14:53.558256 <8>[ 49.774780] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass>
11706 22:14:53.558529 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass
11708 22:14:53.581072 /lava-10583854/1/../bin/lava-test-case
11709 22:14:53.613704 <8>[ 49.829976] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass>
11710 22:14:53.613962 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass
11712 22:14:53.655485 /lava-10583854/1/../bin/lava-test-case
11713 22:14:53.683106 <8>[ 49.899622] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-probed RESULT=pass>
11714 22:14:53.683369 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-probed RESULT=pass
11716 22:14:53.705630 /lava-10583854/1/../bin/lava-test-case
11717 22:14:53.736309 <8>[ 49.952510] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass>
11718 22:14:53.736592 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass
11720 22:14:53.772404 /lava-10583854/1/../bin/lava-test-case
11721 22:14:53.804311 <8>[ 50.020819] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass>
11722 22:14:53.804594 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass
11724 22:14:53.828133 /lava-10583854/1/../bin/lava-test-case
11725 22:14:53.857920 <8>[ 50.074827] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass>
11726 22:14:53.858190 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass
11728 22:14:53.891892 /lava-10583854/1/../bin/lava-test-case
11729 22:14:53.922531 <8>[ 50.138938] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-probed RESULT=pass>
11730 22:14:53.922790 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-probed RESULT=pass
11732 22:14:53.943872 /lava-10583854/1/../bin/lava-test-case
11733 22:14:53.977435 <8>[ 50.194030] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass>
11734 22:14:53.977714 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass
11736 22:14:54.021170 /lava-10583854/1/../bin/lava-test-case
11737 22:14:54.053877 <8>[ 50.270229] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-probed RESULT=pass>
11738 22:14:54.054155 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-probed RESULT=pass
11740 22:14:54.076928 /lava-10583854/1/../bin/lava-test-case
11741 22:14:54.108775 <8>[ 50.324931] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-driver-present RESULT=pass>
11742 22:14:54.109033 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-driver-present RESULT=pass
11744 22:14:54.146319 /lava-10583854/1/../bin/lava-test-case
11745 22:14:54.176575 <8>[ 50.393056] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-probed RESULT=pass>
11746 22:14:54.176860 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-probed RESULT=pass
11748 22:14:54.199270 /lava-10583854/1/../bin/lava-test-case
11749 22:14:54.232508 <8>[ 50.449023] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass>
11750 22:14:54.232772 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass
11752 22:14:54.269781 /lava-10583854/1/../bin/lava-test-case
11753 22:14:54.302283 <8>[ 50.518755] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass>
11754 22:14:54.302550 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass
11756 22:14:55.342102 /lava-10583854/1/../bin/lava-test-case
11757 22:14:55.371905 <8>[ 51.588928] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail>
11758 22:14:55.372193 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail
11760 22:14:56.409680 /lava-10583854/1/../bin/lava-test-case
11761 22:14:56.438504 <8>[ 52.655451] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked>
11762 22:14:56.438797 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked
11763 22:14:56.438882 Bad test result: blocked
11764 22:14:56.462979 /lava-10583854/1/../bin/lava-test-case
11765 22:14:56.501231 <8>[ 52.718244] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-driver-present RESULT=pass>
11766 22:14:56.501493 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-driver-present RESULT=pass
11768 22:14:57.549623 /lava-10583854/1/../bin/lava-test-case
11769 22:14:57.578165 <8>[ 53.795179] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-probed RESULT=fail>
11770 22:14:57.578449 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-probed RESULT=fail
11772 22:14:57.601991 /lava-10583854/1/../bin/lava-test-case
11773 22:14:57.630187 <8>[ 53.846965] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo-driver-present RESULT=pass>
11774 22:14:57.630443 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo-driver-present RESULT=pass
11776 22:14:57.670712 /lava-10583854/1/../bin/lava-test-case
11777 22:14:57.700442 <8>[ 53.917403] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo0-probed RESULT=pass>
11778 22:14:57.700709 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo0-probed RESULT=pass
11780 22:14:57.736151 /lava-10583854/1/../bin/lava-test-case
11781 22:14:57.768637 <8>[ 53.985430] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo1-probed RESULT=pass>
11782 22:14:57.768908 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo1-probed RESULT=pass
11784 22:14:57.792478 /lava-10583854/1/../bin/lava-test-case
11785 22:14:57.827700 <8>[ 54.044880] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass>
11786 22:14:57.827969 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass
11788 22:14:57.865546 /lava-10583854/1/../bin/lava-test-case
11789 22:14:57.895820 <8>[ 54.112810] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-probed RESULT=pass>
11790 22:14:57.896091 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-probed RESULT=pass
11792 22:14:57.926258 /lava-10583854/1/../bin/lava-test-case
11793 22:14:57.963920 <8>[ 54.180686] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-driver-present RESULT=pass>
11794 22:14:57.964201 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-driver-present RESULT=pass
11796 22:14:59.014355 /lava-10583854/1/../bin/lava-test-case
11797 22:14:59.043542 <8>[ 55.260537] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-probed RESULT=fail>
11798 22:14:59.043909 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-probed RESULT=fail
11800 22:14:59.067015 /lava-10583854/1/../bin/lava-test-case
11801 22:14:59.099217 <8>[ 55.316439] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-driver-present RESULT=pass>
11802 22:14:59.099520 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-driver-present RESULT=pass
11804 22:15:00.145723 /lava-10583854/1/../bin/lava-test-case
11805 22:15:00.177666 <8>[ 56.394888] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-probed RESULT=fail>
11806 22:15:00.177988 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-probed RESULT=fail
11808 22:15:00.200679 /lava-10583854/1/../bin/lava-test-case
11809 22:15:00.229980 <8>[ 56.447292] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-driver-present RESULT=pass>
11810 22:15:00.230295 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-driver-present RESULT=pass
11812 22:15:01.279241 /lava-10583854/1/../bin/lava-test-case
11813 22:15:01.311235 <8>[ 57.528515] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-probed RESULT=fail>
11814 22:15:01.311539 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-probed RESULT=fail
11816 22:15:01.332971 /lava-10583854/1/../bin/lava-test-case
11817 22:15:01.360312 <8>[ 57.577922] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass>
11818 22:15:01.360575 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass
11820 22:15:02.409984 /lava-10583854/1/../bin/lava-test-case
11821 22:15:02.439533 <8>[ 58.657252] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail>
11822 22:15:02.439912 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail
11824 22:15:02.460740 /lava-10583854/1/../bin/lava-test-case
11825 22:15:02.490566 <8>[ 58.708078] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb-driver-present RESULT=pass>
11826 22:15:02.490902 Received signal: <TESTCASE> TEST_CASE_ID=btusb-driver-present RESULT=pass
11828 22:15:02.523128 /lava-10583854/1/../bin/lava-test-case
11829 22:15:02.552197 <8>[ 58.769872] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb0-probed RESULT=pass>
11830 22:15:02.552535 Received signal: <TESTCASE> TEST_CASE_ID=btusb0-probed RESULT=pass
11832 22:15:02.584729 /lava-10583854/1/../bin/lava-test-case
11833 22:15:02.609983 <8>[ 58.827563] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb1-probed RESULT=pass>
11834 22:15:02.610322 Received signal: <TESTCASE> TEST_CASE_ID=btusb1-probed RESULT=pass
11836 22:15:02.632505 /lava-10583854/1/../bin/lava-test-case
11837 22:15:02.661619 <8>[ 58.879169] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass>
11838 22:15:02.661956 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass
11840 22:15:02.696246 /lava-10583854/1/../bin/lava-test-case
11841 22:15:02.726442 <8>[ 58.943932] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-probed RESULT=pass>
11842 22:15:02.726778 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-probed RESULT=pass
11844 22:15:02.755349 /lava-10583854/1/../bin/lava-test-case
11845 22:15:02.780178 <8>[ 58.997727] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass>
11846 22:15:02.780517 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass
11848 22:15:02.815458 /lava-10583854/1/../bin/lava-test-case
11849 22:15:02.840748 <8>[ 59.058020] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-probed RESULT=pass>
11850 22:15:02.841090 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-probed RESULT=pass
11852 22:15:02.865562 /lava-10583854/1/../bin/lava-test-case
11853 22:15:02.893534 <8>[ 59.110984] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass>
11854 22:15:02.893873 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass
11856 22:15:03.939492 /lava-10583854/1/../bin/lava-test-case
11857 22:15:03.970338 <8>[ 60.188053] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=fail>
11858 22:15:03.970672 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=fail
11860 22:15:03.976388 + set +x
11861 22:15:03.979503 Received signal: <ENDRUN> 1_bootrr 10583854_1.6.2.3.5
11862 22:15:03.979694 Ending use of test pattern.
11863 22:15:03.979787 Ending test lava.1_bootrr (10583854_1.6.2.3.5), duration 32.28
11865 22:15:03.982676 <8>[ 60.200585] <LAVA_SIGNAL_ENDRUN 1_bootrr 10583854_1.6.2.3.5>
11866 22:15:03.988051 <LAVA_TEST_RUNNER EXIT>
11867 22:15:03.988358 ok: lava_test_shell seems to have completed
11868 22:15:03.989379 all-cpus-are-online: pass
anx7625-3-probed: fail
anx7625-7-probed: fail
anx7625-driver-present: pass
btusb-driver-present: pass
btusb0-probed: pass
btusb1-probed: pass
clk-mt8192-apmixedsys-probed: pass
clk-mt8192-aud-driver-present: pass
clk-mt8192-aud-probed: pass
clk-mt8192-cam-driver-present: pass
clk-mt8192-cam-probed: pass
clk-mt8192-cam_rawa-probed: pass
clk-mt8192-cam_rawb-probed: pass
clk-mt8192-cam_rawc-probed: pass
clk-mt8192-driver-present: pass
clk-mt8192-img-driver-present: pass
clk-mt8192-img-probed: pass
clk-mt8192-img2-probed: pass
clk-mt8192-imp_iic_wrap-driver-present: pass
clk-mt8192-imp_iic_wrap_e-probed: pass
clk-mt8192-imp_iic_wrap_n-probed: pass
clk-mt8192-imp_iic_wrap_s-probed: pass
clk-mt8192-imp_iic_wrap_ws-probed: pass
clk-mt8192-infracfg-probed: pass
clk-mt8192-ipe-driver-present: pass
clk-mt8192-ipe-probed: pass
clk-mt8192-mdp-driver-present: pass
clk-mt8192-mdp-probed: pass
clk-mt8192-mfg-driver-present: pass
clk-mt8192-mfg-probed: pass
clk-mt8192-mm-driver-present: pass
clk-mt8192-mm-probed: pass
clk-mt8192-msdc-driver-present: pass
clk-mt8192-msdc-probed: pass
clk-mt8192-pericfg-probed: pass
clk-mt8192-topckgen-probed: pass
clk-mt8192-vdec-driver-present: pass
clk-mt8192-vdec-probed: pass
clk-mt8192-vdec_soc-probed: pass
clk-mt8192-venc-driver-present: pass
clk-mt8192-venc-probed: pass
cros-ec-i2c-tunnel-driver-present: pass
cros-ec-i2c-tunnel-probed: pass
cros-ec-keyb-driver-present: pass
cros-ec-keyb-probed: pass
cros-ec-pwm-driver-present: pass
cros-ec-pwm-probed: pass
cros-ec-regulator-driver-present: pass
cros-ec-regulator0-probed: pass
cros-ec-regulator1-probed: pass
cros-ec-rpmsg-driver-present: fail
cros-ec-spi-driver-present: pass
cros-ec-spi-probed: pass
cros-ec-typec-driver-present: pass
cros-ec-typec-probed: pass
deferred-probe-empty: pass
dmic-codec-driver-present: pass
dmic-codec-probed: fail
elan_i2c-driver-present: pass
elan_i2c-probed: fail
elants_i2c-driver-present: pass
elants_i2c-probed: fail
i2c-mt65xx-driver-present: pass
i2c0-mt65xx-probed: pass
i2c1-mt65xx-probed: pass
i2c2-mt65xx-probed: pass
i2c3-mt65xx-probed: pass
i2c7-mt65xx-probed: pass
leds_pwm-driver-present: pass
leds_pwm-probed: pass
mediatek,efuse-driver-present: pass
mediatek,efuse-probed: pass
mediatek-disp-aal-driver-present: pass
mediatek-disp-aal-probed: pass
mediatek-disp-ccorr-driver-present: pass
mediatek-disp-ccorr-probed: pass
mediatek-disp-color-driver-present: pass
mediatek-disp-color-probed: pass
mediatek-disp-gamma-driver-present: pass
mediatek-disp-gamma-probed: pass
mediatek-disp-ovl-driver-present: pass
mediatek-disp-ovl0-probed: pass
mediatek-disp-ovl2l0-probed: pass
mediatek-disp-ovl2l2-probed: pass
mediatek-disp-pwm-driver-present: pass
mediatek-disp-pwm-probed: fail
mediatek-disp-rdma-driver-present: pass
mediatek-disp-rdma0-probed: pass
mediatek-disp-rdma4-probed: pass
mediatek-dpi-driver-present: pass
mediatek-dpi-probed: fail
mediatek-drm-driver-present: pass
mediatek-drm-probed: pass
mediatek-mipi-tx-driver-present: pass
mediatek-mipi-tx-probed: fail
mediatek-mutex-driver-present: pass
mediatek-mutex-probed: pass
mt-pmic-pwrap-driver-present: pass
mt-pmic-pwrap-probed: pass
mt6315-regulator-driver-present: pass
mt6315-regulator6-probed: pass
mt6315-regulator7-probed: pass
mt6577-uart-driver-present: pass
mt6577-uart-probed: pass
mt7921e-driver-present: pass
mt7921e-probed: pass
mt8192-audio-driver-present: pass
mt8192-audio-probed: pass
mt8192-pinctrl-driver-present: pass
mt8192-pinctrl-probed: pass
mt8192_mt6359-driver-present: pass
mt8192_mt6359-probed: fail
mtk-cpufreq-hw-driver-present: pass
mtk-cpufreq-hw-probed: fail
mtk-dsi-driver-present: pass
mtk-dsi-probed: fail
mtk-iommu-driver-present: pass
mtk-iommu-probed: pass
mtk-mmsys-driver-present: pass
mtk-mmsys-probed: pass
mtk-msdc-driver-present: pass
mtk-msdc-probed: pass
mtk-pcie-gen3-driver-present: pass
mtk-pcie-gen3-probed: pass
mtk-power-controller-driver-present: pass
mtk-power-controller-probed: pass
mtk-scp-driver-present: pass
mtk-scp-probed: pass
mtk-smi-common-driver-present: pass
mtk-smi-common-probed: pass
mtk-smi-larb-driver-present: pass
mtk-smi-larb0-probed: pass
mtk-smi-larb1-probed: pass
mtk-smi-larb11-probed: pass
mtk-smi-larb13-probed: pass
mtk-smi-larb14-probed: pass
mtk-smi-larb16-probed: pass
mtk-smi-larb17-probed: pass
mtk-smi-larb18-probed: pass
mtk-smi-larb19-probed: pass
mtk-smi-larb2-probed: pass
mtk-smi-larb20-probed: pass
mtk-smi-larb4-probed: pass
mtk-smi-larb5-probed: pass
mtk-smi-larb7-probed: pass
mtk-smi-larb9-probed: pass
mtk-spi-driver-present: pass
mtk-spi-nor-driver-present: pass
mtk-spi-nor-probed: pass
mtk-spi1-probed: pass
mtk-spi5-probed: pass
mtk-tphy-driver-present: pass
mtk-tphy-probed: pass
mtk-vcodec-dec-driver-present: fail
mtk-vcodec-enc-driver-present: pass
mtk-vcodec-enc-probed: pass
mtk-wdt-driver-present: pass
mtk-wdt-probed: pass
panel-edp-driver-present: pass
panel-simple-dp-aux-driver-present: pass
panel-simple-dp-aux-probed: fail
panfrost-driver-present: pass
panfrost-probed: fail
pwm-backlight-driver-present: pass
pwm-backlight-probed: fail
rt1015p-driver-present: pass
rt1015p-probed: fail
rt5682-driver-present: pass
rt5682-probed: fail
sbs-battery-driver-present: pass
sbs-battery-probed: pass
spmi-mtk-driver-present: pass
spmi-mtk-probed: pass
tpm-chip-is-online: skip
tpm_tis_spi-driver-present: pass
tpm_tis_spi-probed: pass
uvcvideo-driver-present: pass
uvcvideo0-probed: pass
uvcvideo1-probed: pass
xhci-mtk-driver-present: pass
xhci-mtk-probed: pass
11869 22:15:03.989539 end: 4.1 lava-test-shell (duration 00:00:33) [common]
11870 22:15:03.989641 end: 4 lava-test-retry (duration 00:00:33) [common]
11871 22:15:03.989746 start: 5 finalize (timeout 00:07:13) [common]
11872 22:15:03.989849 start: 5.1 power-off (timeout 00:00:30) [common]
11873 22:15:03.990118 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=off'
11874 22:15:04.066042 >> Command sent successfully.
11875 22:15:04.068613 Returned 0 in 0 seconds
11876 22:15:04.169042 end: 5.1 power-off (duration 00:00:00) [common]
11878 22:15:04.169422 start: 5.2 read-feedback (timeout 00:07:13) [common]
11879 22:15:04.169699 Listened to connection for namespace 'common' for up to 1s
11880 22:15:05.170377 Finalising connection for namespace 'common'
11881 22:15:05.170571 Disconnecting from shell: Finalise
11882 22:15:05.170656 / #
11883 22:15:05.271017 end: 5.2 read-feedback (duration 00:00:01) [common]
11884 22:15:05.271207 end: 5 finalize (duration 00:00:01) [common]
11885 22:15:05.271328 Cleaning after the job
11886 22:15:05.271438 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10583854/tftp-deploy-86gyr5tv/ramdisk
11887 22:15:05.273462 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10583854/tftp-deploy-86gyr5tv/kernel
11888 22:15:05.282200 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10583854/tftp-deploy-86gyr5tv/dtb
11889 22:15:05.282435 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10583854/tftp-deploy-86gyr5tv/nfsrootfs
11890 22:15:05.337035 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10583854/tftp-deploy-86gyr5tv/modules
11891 22:15:05.342370 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10583854
11892 22:15:05.650615 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10583854
11893 22:15:05.650815 Job finished correctly