Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 30
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 25
1 22:11:48.570689 lava-dispatcher, installed at version: 2023.03
2 22:11:48.570917 start: 0 validate
3 22:11:48.571052 Start time: 2023-06-04 22:11:48.571045+00:00 (UTC)
4 22:11:48.571174 Using caching service: 'http://localhost/cache/?uri=%s'
5 22:11:48.571303 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-cros-ec%2F20230527.0%2Farm64%2Frootfs.cpio.gz exists
6 22:11:48.861548 Using caching service: 'http://localhost/cache/?uri=%s'
7 22:11:48.862363 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1281-g84d5372e0f314%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 22:12:10.880403 Using caching service: 'http://localhost/cache/?uri=%s'
9 22:12:10.881168 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1281-g84d5372e0f314%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 22:12:11.175246 Using caching service: 'http://localhost/cache/?uri=%s'
11 22:12:11.176011 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1281-g84d5372e0f314%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 22:12:14.962186 validate duration: 26.39
14 22:12:14.962461 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 22:12:14.962560 start: 1.1 download-retry (timeout 00:10:00) [common]
16 22:12:14.962647 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 22:12:14.962773 Not decompressing ramdisk as can be used compressed.
18 22:12:14.962861 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-cros-ec/20230527.0/arm64/rootfs.cpio.gz
19 22:12:14.962928 saving as /var/lib/lava/dispatcher/tmp/10583887/tftp-deploy-bh6vuykx/ramdisk/rootfs.cpio.gz
20 22:12:14.962990 total size: 34405874 (32MB)
21 22:12:15.297367 progress 0% (0MB)
22 22:12:15.306216 progress 5% (1MB)
23 22:12:15.314887 progress 10% (3MB)
24 22:12:15.324032 progress 15% (4MB)
25 22:12:15.333317 progress 20% (6MB)
26 22:12:15.342775 progress 25% (8MB)
27 22:12:15.351939 progress 30% (9MB)
28 22:12:15.361233 progress 35% (11MB)
29 22:12:15.370195 progress 40% (13MB)
30 22:12:15.379135 progress 45% (14MB)
31 22:12:15.387864 progress 50% (16MB)
32 22:12:15.396628 progress 55% (18MB)
33 22:12:15.405273 progress 60% (19MB)
34 22:12:15.414018 progress 65% (21MB)
35 22:12:15.422684 progress 70% (22MB)
36 22:12:15.431897 progress 75% (24MB)
37 22:12:15.440914 progress 80% (26MB)
38 22:12:15.450028 progress 85% (27MB)
39 22:12:15.458892 progress 90% (29MB)
40 22:12:15.467806 progress 95% (31MB)
41 22:12:15.476635 progress 100% (32MB)
42 22:12:15.476947 32MB downloaded in 0.51s (63.84MB/s)
43 22:12:15.477111 end: 1.1.1 http-download (duration 00:00:01) [common]
45 22:12:15.477351 end: 1.1 download-retry (duration 00:00:01) [common]
46 22:12:15.477437 start: 1.2 download-retry (timeout 00:09:59) [common]
47 22:12:15.477521 start: 1.2.1 http-download (timeout 00:09:59) [common]
48 22:12:15.477709 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1281-g84d5372e0f314/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 22:12:15.477795 saving as /var/lib/lava/dispatcher/tmp/10583887/tftp-deploy-bh6vuykx/kernel/Image
50 22:12:15.477858 total size: 45746688 (43MB)
51 22:12:15.477919 No compression specified
52 22:12:15.479027 progress 0% (0MB)
53 22:12:15.490532 progress 5% (2MB)
54 22:12:15.502077 progress 10% (4MB)
55 22:12:15.513685 progress 15% (6MB)
56 22:12:15.525205 progress 20% (8MB)
57 22:12:15.537186 progress 25% (10MB)
58 22:12:15.548886 progress 30% (13MB)
59 22:12:15.561242 progress 35% (15MB)
60 22:12:15.573612 progress 40% (17MB)
61 22:12:15.586207 progress 45% (19MB)
62 22:12:15.597808 progress 50% (21MB)
63 22:12:15.609170 progress 55% (24MB)
64 22:12:15.620674 progress 60% (26MB)
65 22:12:15.633324 progress 65% (28MB)
66 22:12:15.645834 progress 70% (30MB)
67 22:12:15.658823 progress 75% (32MB)
68 22:12:15.671389 progress 80% (34MB)
69 22:12:15.684390 progress 85% (37MB)
70 22:12:15.697289 progress 90% (39MB)
71 22:12:15.709785 progress 95% (41MB)
72 22:12:15.722188 progress 100% (43MB)
73 22:12:15.722358 43MB downloaded in 0.24s (178.44MB/s)
74 22:12:15.722514 end: 1.2.1 http-download (duration 00:00:00) [common]
76 22:12:15.722754 end: 1.2 download-retry (duration 00:00:00) [common]
77 22:12:15.722843 start: 1.3 download-retry (timeout 00:09:59) [common]
78 22:12:15.722936 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 22:12:15.723079 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1281-g84d5372e0f314/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 22:12:15.723157 saving as /var/lib/lava/dispatcher/tmp/10583887/tftp-deploy-bh6vuykx/dtb/mt8192-asurada-spherion-r0.dtb
81 22:12:15.723222 total size: 46924 (0MB)
82 22:12:15.723284 No compression specified
83 22:12:15.724593 progress 69% (0MB)
84 22:12:15.724868 progress 100% (0MB)
85 22:12:15.725032 0MB downloaded in 0.00s (24.76MB/s)
86 22:12:15.725155 end: 1.3.1 http-download (duration 00:00:00) [common]
88 22:12:15.725393 end: 1.3 download-retry (duration 00:00:00) [common]
89 22:12:15.725514 start: 1.4 download-retry (timeout 00:09:59) [common]
90 22:12:15.725625 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 22:12:15.725739 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1281-g84d5372e0f314/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 22:12:15.725813 saving as /var/lib/lava/dispatcher/tmp/10583887/tftp-deploy-bh6vuykx/modules/modules.tar
93 22:12:15.725877 total size: 8541948 (8MB)
94 22:12:15.725939 Using unxz to decompress xz
95 22:12:15.729598 progress 0% (0MB)
96 22:12:15.751872 progress 5% (0MB)
97 22:12:15.777705 progress 10% (0MB)
98 22:12:15.804615 progress 15% (1MB)
99 22:12:15.831635 progress 20% (1MB)
100 22:12:15.856760 progress 25% (2MB)
101 22:12:15.885608 progress 30% (2MB)
102 22:12:15.912274 progress 35% (2MB)
103 22:12:15.938453 progress 40% (3MB)
104 22:12:15.964235 progress 45% (3MB)
105 22:12:15.990696 progress 50% (4MB)
106 22:12:16.015484 progress 55% (4MB)
107 22:12:16.040618 progress 60% (4MB)
108 22:12:16.066245 progress 65% (5MB)
109 22:12:16.091841 progress 70% (5MB)
110 22:12:16.116710 progress 75% (6MB)
111 22:12:16.141225 progress 80% (6MB)
112 22:12:16.166439 progress 85% (6MB)
113 22:12:16.196536 progress 90% (7MB)
114 22:12:16.223242 progress 95% (7MB)
115 22:12:16.248950 progress 100% (8MB)
116 22:12:16.255075 8MB downloaded in 0.53s (15.39MB/s)
117 22:12:16.255364 end: 1.4.1 http-download (duration 00:00:01) [common]
119 22:12:16.255632 end: 1.4 download-retry (duration 00:00:01) [common]
120 22:12:16.255732 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 22:12:16.255831 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 22:12:16.255915 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 22:12:16.256050 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 22:12:16.256269 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10583887/lava-overlay-1o7hamik
125 22:12:16.256399 makedir: /var/lib/lava/dispatcher/tmp/10583887/lava-overlay-1o7hamik/lava-10583887/bin
126 22:12:16.256501 makedir: /var/lib/lava/dispatcher/tmp/10583887/lava-overlay-1o7hamik/lava-10583887/tests
127 22:12:16.256599 makedir: /var/lib/lava/dispatcher/tmp/10583887/lava-overlay-1o7hamik/lava-10583887/results
128 22:12:16.256717 Creating /var/lib/lava/dispatcher/tmp/10583887/lava-overlay-1o7hamik/lava-10583887/bin/lava-add-keys
129 22:12:16.256857 Creating /var/lib/lava/dispatcher/tmp/10583887/lava-overlay-1o7hamik/lava-10583887/bin/lava-add-sources
130 22:12:16.256985 Creating /var/lib/lava/dispatcher/tmp/10583887/lava-overlay-1o7hamik/lava-10583887/bin/lava-background-process-start
131 22:12:16.257111 Creating /var/lib/lava/dispatcher/tmp/10583887/lava-overlay-1o7hamik/lava-10583887/bin/lava-background-process-stop
132 22:12:16.257234 Creating /var/lib/lava/dispatcher/tmp/10583887/lava-overlay-1o7hamik/lava-10583887/bin/lava-common-functions
133 22:12:16.257356 Creating /var/lib/lava/dispatcher/tmp/10583887/lava-overlay-1o7hamik/lava-10583887/bin/lava-echo-ipv4
134 22:12:16.257479 Creating /var/lib/lava/dispatcher/tmp/10583887/lava-overlay-1o7hamik/lava-10583887/bin/lava-install-packages
135 22:12:16.257600 Creating /var/lib/lava/dispatcher/tmp/10583887/lava-overlay-1o7hamik/lava-10583887/bin/lava-installed-packages
136 22:12:16.257723 Creating /var/lib/lava/dispatcher/tmp/10583887/lava-overlay-1o7hamik/lava-10583887/bin/lava-os-build
137 22:12:16.257844 Creating /var/lib/lava/dispatcher/tmp/10583887/lava-overlay-1o7hamik/lava-10583887/bin/lava-probe-channel
138 22:12:16.257999 Creating /var/lib/lava/dispatcher/tmp/10583887/lava-overlay-1o7hamik/lava-10583887/bin/lava-probe-ip
139 22:12:16.258120 Creating /var/lib/lava/dispatcher/tmp/10583887/lava-overlay-1o7hamik/lava-10583887/bin/lava-target-ip
140 22:12:16.258242 Creating /var/lib/lava/dispatcher/tmp/10583887/lava-overlay-1o7hamik/lava-10583887/bin/lava-target-mac
141 22:12:16.258361 Creating /var/lib/lava/dispatcher/tmp/10583887/lava-overlay-1o7hamik/lava-10583887/bin/lava-target-storage
142 22:12:16.258486 Creating /var/lib/lava/dispatcher/tmp/10583887/lava-overlay-1o7hamik/lava-10583887/bin/lava-test-case
143 22:12:16.258607 Creating /var/lib/lava/dispatcher/tmp/10583887/lava-overlay-1o7hamik/lava-10583887/bin/lava-test-event
144 22:12:16.258726 Creating /var/lib/lava/dispatcher/tmp/10583887/lava-overlay-1o7hamik/lava-10583887/bin/lava-test-feedback
145 22:12:16.258845 Creating /var/lib/lava/dispatcher/tmp/10583887/lava-overlay-1o7hamik/lava-10583887/bin/lava-test-raise
146 22:12:16.258968 Creating /var/lib/lava/dispatcher/tmp/10583887/lava-overlay-1o7hamik/lava-10583887/bin/lava-test-reference
147 22:12:16.259090 Creating /var/lib/lava/dispatcher/tmp/10583887/lava-overlay-1o7hamik/lava-10583887/bin/lava-test-runner
148 22:12:16.259210 Creating /var/lib/lava/dispatcher/tmp/10583887/lava-overlay-1o7hamik/lava-10583887/bin/lava-test-set
149 22:12:16.259332 Creating /var/lib/lava/dispatcher/tmp/10583887/lava-overlay-1o7hamik/lava-10583887/bin/lava-test-shell
150 22:12:16.259456 Updating /var/lib/lava/dispatcher/tmp/10583887/lava-overlay-1o7hamik/lava-10583887/bin/lava-install-packages (oe)
151 22:12:16.259608 Updating /var/lib/lava/dispatcher/tmp/10583887/lava-overlay-1o7hamik/lava-10583887/bin/lava-installed-packages (oe)
152 22:12:16.259729 Creating /var/lib/lava/dispatcher/tmp/10583887/lava-overlay-1o7hamik/lava-10583887/environment
153 22:12:16.259859 LAVA metadata
154 22:12:16.259936 - LAVA_JOB_ID=10583887
155 22:12:16.260028 - LAVA_DISPATCHER_IP=192.168.201.1
156 22:12:16.260134 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 22:12:16.260205 skipped lava-vland-overlay
158 22:12:16.260282 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 22:12:16.260365 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 22:12:16.260431 skipped lava-multinode-overlay
161 22:12:16.260505 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 22:12:16.260590 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 22:12:16.260671 Loading test definitions
164 22:12:16.260766 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 22:12:16.260843 Using /lava-10583887 at stage 0
166 22:12:16.261133 uuid=10583887_1.5.2.3.1 testdef=None
167 22:12:16.261222 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 22:12:16.261310 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 22:12:16.261853 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 22:12:16.262168 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 22:12:16.262815 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 22:12:16.263047 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 22:12:16.263633 runner path: /var/lib/lava/dispatcher/tmp/10583887/lava-overlay-1o7hamik/lava-10583887/0/tests/0_cros-ec test_uuid 10583887_1.5.2.3.1
176 22:12:16.263786 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 22:12:16.264034 Creating lava-test-runner.conf files
179 22:12:16.264100 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10583887/lava-overlay-1o7hamik/lava-10583887/0 for stage 0
180 22:12:16.264189 - 0_cros-ec
181 22:12:16.264289 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 22:12:16.264375 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 22:12:16.270910 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 22:12:16.271024 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 22:12:16.271114 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 22:12:16.271201 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 22:12:16.271291 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 22:12:17.235373 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 22:12:17.235768 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 22:12:17.235935 extracting modules file /var/lib/lava/dispatcher/tmp/10583887/tftp-deploy-bh6vuykx/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10583887/extract-overlay-ramdisk-xz8hel9v/ramdisk
191 22:12:17.458111 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 22:12:17.458291 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 22:12:17.458392 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10583887/compress-overlay-qpv7l0q2/overlay-1.5.2.4.tar.gz to ramdisk
194 22:12:17.458469 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10583887/compress-overlay-qpv7l0q2/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10583887/extract-overlay-ramdisk-xz8hel9v/ramdisk
195 22:12:17.464886 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 22:12:17.465008 start: 1.5.6 configure-preseed-file (timeout 00:09:57) [common]
197 22:12:17.465107 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 22:12:17.465199 start: 1.5.7 compress-ramdisk (timeout 00:09:57) [common]
199 22:12:17.465283 Building ramdisk /var/lib/lava/dispatcher/tmp/10583887/extract-overlay-ramdisk-xz8hel9v/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10583887/extract-overlay-ramdisk-xz8hel9v/ramdisk
200 22:12:18.139187 >> 269468 blocks
201 22:12:23.045216 rename /var/lib/lava/dispatcher/tmp/10583887/extract-overlay-ramdisk-xz8hel9v/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10583887/tftp-deploy-bh6vuykx/ramdisk/ramdisk.cpio.gz
202 22:12:23.045653 end: 1.5.7 compress-ramdisk (duration 00:00:06) [common]
203 22:12:23.045793 start: 1.5.8 prepare-kernel (timeout 00:09:52) [common]
204 22:12:23.045960 start: 1.5.8.1 prepare-fit (timeout 00:09:52) [common]
205 22:12:23.046083 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10583887/tftp-deploy-bh6vuykx/kernel/Image'
206 22:12:35.674460 Returned 0 in 12 seconds
207 22:12:35.775087 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10583887/tftp-deploy-bh6vuykx/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10583887/tftp-deploy-bh6vuykx/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10583887/tftp-deploy-bh6vuykx/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10583887/tftp-deploy-bh6vuykx/kernel/image.itb
208 22:12:36.470192 output: FIT description: Kernel Image image with one or more FDT blobs
209 22:12:36.470570 output: Created: Sun Jun 4 23:12:36 2023
210 22:12:36.470663 output: Image 0 (kernel-1)
211 22:12:36.470728 output: Description:
212 22:12:36.470791 output: Created: Sun Jun 4 23:12:36 2023
213 22:12:36.470853 output: Type: Kernel Image
214 22:12:36.470914 output: Compression: lzma compressed
215 22:12:36.470973 output: Data Size: 10081729 Bytes = 9845.44 KiB = 9.61 MiB
216 22:12:36.471032 output: Architecture: AArch64
217 22:12:36.471089 output: OS: Linux
218 22:12:36.471149 output: Load Address: 0x00000000
219 22:12:36.471206 output: Entry Point: 0x00000000
220 22:12:36.471263 output: Hash algo: crc32
221 22:12:36.471318 output: Hash value: 3b3111d8
222 22:12:36.471371 output: Image 1 (fdt-1)
223 22:12:36.471425 output: Description: mt8192-asurada-spherion-r0
224 22:12:36.471478 output: Created: Sun Jun 4 23:12:36 2023
225 22:12:36.471531 output: Type: Flat Device Tree
226 22:12:36.471583 output: Compression: uncompressed
227 22:12:36.471637 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
228 22:12:36.471690 output: Architecture: AArch64
229 22:12:36.471743 output: Hash algo: crc32
230 22:12:36.471795 output: Hash value: 1df858fa
231 22:12:36.471847 output: Image 2 (ramdisk-1)
232 22:12:36.471900 output: Description: unavailable
233 22:12:36.471952 output: Created: Sun Jun 4 23:12:36 2023
234 22:12:36.472012 output: Type: RAMDisk Image
235 22:12:36.472066 output: Compression: Unknown Compression
236 22:12:36.472118 output: Data Size: 47379547 Bytes = 46269.09 KiB = 45.18 MiB
237 22:12:36.472171 output: Architecture: AArch64
238 22:12:36.472224 output: OS: Linux
239 22:12:36.472277 output: Load Address: unavailable
240 22:12:36.472330 output: Entry Point: unavailable
241 22:12:36.472383 output: Hash algo: crc32
242 22:12:36.472435 output: Hash value: 7f4bd361
243 22:12:36.472487 output: Default Configuration: 'conf-1'
244 22:12:36.472540 output: Configuration 0 (conf-1)
245 22:12:36.472601 output: Description: mt8192-asurada-spherion-r0
246 22:12:36.472685 output: Kernel: kernel-1
247 22:12:36.472761 output: Init Ramdisk: ramdisk-1
248 22:12:36.472816 output: FDT: fdt-1
249 22:12:36.472870 output: Loadables: kernel-1
250 22:12:36.472923 output:
251 22:12:36.473115 end: 1.5.8.1 prepare-fit (duration 00:00:13) [common]
252 22:12:36.473213 end: 1.5.8 prepare-kernel (duration 00:00:13) [common]
253 22:12:36.473315 end: 1.5 prepare-tftp-overlay (duration 00:00:20) [common]
254 22:12:36.473438 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:38) [common]
255 22:12:36.473565 No LXC device requested
256 22:12:36.473695 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 22:12:36.473809 start: 1.7 deploy-device-env (timeout 00:09:38) [common]
258 22:12:36.473893 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 22:12:36.473966 Checking files for TFTP limit of 4294967296 bytes.
260 22:12:36.474488 end: 1 tftp-deploy (duration 00:00:22) [common]
261 22:12:36.474601 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 22:12:36.474724 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 22:12:36.474946 substitutions:
264 22:12:36.475052 - {DTB}: 10583887/tftp-deploy-bh6vuykx/dtb/mt8192-asurada-spherion-r0.dtb
265 22:12:36.475136 - {INITRD}: 10583887/tftp-deploy-bh6vuykx/ramdisk/ramdisk.cpio.gz
266 22:12:36.475197 - {KERNEL}: 10583887/tftp-deploy-bh6vuykx/kernel/Image
267 22:12:36.475256 - {LAVA_MAC}: None
268 22:12:36.475315 - {PRESEED_CONFIG}: None
269 22:12:36.475370 - {PRESEED_LOCAL}: None
270 22:12:36.475424 - {RAMDISK}: 10583887/tftp-deploy-bh6vuykx/ramdisk/ramdisk.cpio.gz
271 22:12:36.475479 - {ROOT_PART}: None
272 22:12:36.475533 - {ROOT}: None
273 22:12:36.475588 - {SERVER_IP}: 192.168.201.1
274 22:12:36.475642 - {TEE}: None
275 22:12:36.475696 Parsed boot commands:
276 22:12:36.475750 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 22:12:36.475924 Parsed boot commands: tftpboot 192.168.201.1 10583887/tftp-deploy-bh6vuykx/kernel/image.itb 10583887/tftp-deploy-bh6vuykx/kernel/cmdline
278 22:12:36.476055 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 22:12:36.476143 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 22:12:36.476235 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 22:12:36.476320 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 22:12:36.476393 Not connected, no need to disconnect.
283 22:12:36.476466 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 22:12:36.476545 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 22:12:36.476621 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-3'
286 22:12:36.480109 Setting prompt string to ['lava-test: # ']
287 22:12:36.480446 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 22:12:36.480556 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 22:12:36.480718 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 22:12:36.480827 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 22:12:36.481017 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=reboot'
292 22:12:41.611413 >> Command sent successfully.
293 22:12:41.613791 Returned 0 in 5 seconds
294 22:12:41.714193 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 22:12:41.714787 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 22:12:41.714885 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 22:12:41.714977 Setting prompt string to 'Starting depthcharge on Spherion...'
299 22:12:41.715044 Changing prompt to 'Starting depthcharge on Spherion...'
300 22:12:41.715116 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 22:12:41.715366 [Enter `^Ec?' for help]
302 22:12:41.887661
303 22:12:41.887810
304 22:12:41.887882 F0: 102B 0000
305 22:12:41.887945
306 22:12:41.888044 F3: 1001 0000 [0200]
307 22:12:41.891532
308 22:12:41.891617 F3: 1001 0000
309 22:12:41.891700
310 22:12:41.891843 F7: 102D 0000
311 22:12:41.891935
312 22:12:41.894491 F1: 0000 0000
313 22:12:41.894576
314 22:12:41.894642 V0: 0000 0000 [0001]
315 22:12:41.894707
316 22:12:41.897673 00: 0007 8000
317 22:12:41.897780
318 22:12:41.897849 01: 0000 0000
319 22:12:41.897916
320 22:12:41.901200 BP: 0C00 0209 [0000]
321 22:12:41.901301
322 22:12:41.901381 G0: 1182 0000
323 22:12:41.901444
324 22:12:41.904335 EC: 0000 0021 [4000]
325 22:12:41.904420
326 22:12:41.904488 S7: 0000 0000 [0000]
327 22:12:41.904551
328 22:12:41.907590 CC: 0000 0000 [0001]
329 22:12:41.907693
330 22:12:41.907780 T0: 0000 0040 [010F]
331 22:12:41.907885
332 22:12:41.910682 Jump to BL
333 22:12:41.910766
334 22:12:41.935360
335 22:12:41.935503
336 22:12:41.935572
337 22:12:41.942227 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 22:12:41.946034 ARM64: Exception handlers installed.
339 22:12:41.949497 ARM64: Testing exception
340 22:12:41.953251 ARM64: Done test exception
341 22:12:41.959587 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 22:12:41.970957 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 22:12:41.977624 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 22:12:41.986720 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 22:12:41.994026 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 22:12:42.000260 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 22:12:42.011702 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 22:12:42.018717 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 22:12:42.037688 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 22:12:42.041491 WDT: Last reset was cold boot
351 22:12:42.044029 SPI1(PAD0) initialized at 2873684 Hz
352 22:12:42.047675 SPI5(PAD0) initialized at 992727 Hz
353 22:12:42.051136 VBOOT: Loading verstage.
354 22:12:42.057466 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 22:12:42.060818 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 22:12:42.064700 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 22:12:42.067851 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 22:12:42.075353 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 22:12:42.081476 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 22:12:42.092573 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
361 22:12:42.092686
362 22:12:42.092768
363 22:12:42.102495 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 22:12:42.106306 ARM64: Exception handlers installed.
365 22:12:42.109368 ARM64: Testing exception
366 22:12:42.109452 ARM64: Done test exception
367 22:12:42.116830 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 22:12:42.119537 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 22:12:42.133474 Probing TPM: . done!
370 22:12:42.133585 TPM ready after 0 ms
371 22:12:42.140434 Connected to device vid:did:rid of 1ae0:0028:00
372 22:12:42.147403 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
373 22:12:42.207417 Initialized TPM device CR50 revision 0
374 22:12:42.218156 tlcl_send_startup: Startup return code is 0
375 22:12:42.218274 TPM: setup succeeded
376 22:12:42.229825 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 22:12:42.238617 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 22:12:42.249923 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 22:12:42.259355 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 22:12:42.262560 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 22:12:42.269449 in-header: 03 07 00 00 08 00 00 00
382 22:12:42.273585 in-data: aa e4 47 04 13 02 00 00
383 22:12:42.276912 Chrome EC: UHEPI supported
384 22:12:42.284111 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 22:12:42.287671 in-header: 03 ad 00 00 08 00 00 00
386 22:12:42.291634 in-data: 00 20 20 08 00 00 00 00
387 22:12:42.291726 Phase 1
388 22:12:42.295370 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 22:12:42.302700 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 22:12:42.307022 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 22:12:42.309675 Recovery requested (1009000e)
392 22:12:42.320672 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 22:12:42.324680 tlcl_extend: response is 0
394 22:12:42.333693 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 22:12:42.339797 tlcl_extend: response is 0
396 22:12:42.347289 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 22:12:42.366867 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
398 22:12:42.373599 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 22:12:42.373702
400 22:12:42.373771
401 22:12:42.384329 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 22:12:42.388187 ARM64: Exception handlers installed.
403 22:12:42.388310 ARM64: Testing exception
404 22:12:42.391504 ARM64: Done test exception
405 22:12:42.411812 pmic_efuse_setting: Set efuses in 11 msecs
406 22:12:42.415402 pmwrap_interface_init: Select PMIF_VLD_RDY
407 22:12:42.422359 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 22:12:42.425333 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 22:12:42.432791 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 22:12:42.435728 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 22:12:42.439462 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 22:12:42.446678 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 22:12:42.450066 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 22:12:42.453661 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 22:12:42.461038 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 22:12:42.464389 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 22:12:42.468674 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 22:12:42.475297 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 22:12:42.478526 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 22:12:42.486955 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 22:12:42.490217 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 22:12:42.497321 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 22:12:42.501484 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 22:12:42.508407 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 22:12:42.512133 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 22:12:42.519835 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 22:12:42.523919 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 22:12:42.530729 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 22:12:42.534697 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 22:12:42.541280 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 22:12:42.545380 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 22:12:42.552680 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 22:12:42.556205 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 22:12:42.563412 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 22:12:42.566927 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 22:12:42.570904 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 22:12:42.577860 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 22:12:42.581616 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 22:12:42.585846 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 22:12:42.592666 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 22:12:42.596639 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 22:12:42.600514 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 22:12:42.608229 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 22:12:42.611366 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 22:12:42.615440 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 22:12:42.618258 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 22:12:42.625992 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 22:12:42.629931 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 22:12:42.633180 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 22:12:42.637151 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 22:12:42.644168 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 22:12:42.647661 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 22:12:42.651174 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 22:12:42.655007 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 22:12:42.659352 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 22:12:42.662372 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 22:12:42.666639 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 22:12:42.676792 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 22:12:42.683807 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 22:12:42.687724 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 22:12:42.694936 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 22:12:42.706117 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 22:12:42.709681 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 22:12:42.712841 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 22:12:42.716371 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 22:12:42.725638 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x0
467 22:12:42.729100 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 22:12:42.737660 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
469 22:12:42.740852 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 22:12:42.750092 [RTC]rtc_get_frequency_meter,154: input=15, output=790
471 22:12:42.759314 [RTC]rtc_get_frequency_meter,154: input=23, output=978
472 22:12:42.768794 [RTC]rtc_get_frequency_meter,154: input=19, output=884
473 22:12:42.778257 [RTC]rtc_get_frequency_meter,154: input=17, output=836
474 22:12:42.788496 [RTC]rtc_get_frequency_meter,154: input=16, output=813
475 22:12:42.797287 [RTC]rtc_get_frequency_meter,154: input=15, output=789
476 22:12:42.807049 [RTC]rtc_get_frequency_meter,154: input=16, output=813
477 22:12:42.810252 [RTC]rtc_eosc_cali,47: left: 15, middle: 15, right: 16
478 22:12:42.817381 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
479 22:12:42.820776 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 22:12:42.824944 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
481 22:12:42.828809 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 22:12:42.831745 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
483 22:12:42.835753 ADC[4]: Raw value=902066 ID=7
484 22:12:42.838721 ADC[3]: Raw value=213336 ID=1
485 22:12:42.838824 RAM Code: 0x71
486 22:12:42.846084 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 22:12:42.849251 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 22:12:42.857128 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 22:12:42.864438 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 22:12:42.868204 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 22:12:42.872324 in-header: 03 07 00 00 08 00 00 00
492 22:12:42.875721 in-data: aa e4 47 04 13 02 00 00
493 22:12:42.879924 Chrome EC: UHEPI supported
494 22:12:42.883364 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 22:12:42.886834 in-header: 03 ed 00 00 08 00 00 00
496 22:12:42.890910 in-data: 80 20 60 08 00 00 00 00
497 22:12:42.894836 MRC: failed to locate region type 0.
498 22:12:42.901952 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 22:12:42.905806 DRAM-K: Running full calibration
500 22:12:42.909632 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 22:12:42.913139 header.status = 0x0
502 22:12:42.916938 header.version = 0x6 (expected: 0x6)
503 22:12:42.920691 header.size = 0xd00 (expected: 0xd00)
504 22:12:42.920768 header.flags = 0x0
505 22:12:42.927715 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 22:12:42.945298 read SPI 0x72590 0x1c583: 12500 us, 9287 KB/s, 74.296 Mbps
507 22:12:42.951925 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 22:12:42.955842 dram_init: ddr_geometry: 2
509 22:12:42.955926 [EMI] MDL number = 2
510 22:12:42.959443 [EMI] Get MDL freq = 0
511 22:12:42.959526 dram_init: ddr_type: 0
512 22:12:42.963105 is_discrete_lpddr4: 1
513 22:12:42.966991 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 22:12:42.967091
515 22:12:42.967174
516 22:12:42.970724 [Bian_co] ETT version 0.0.0.1
517 22:12:42.974329 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 22:12:42.974413
519 22:12:42.977550 dramc_set_vcore_voltage set vcore to 650000
520 22:12:42.977633 Read voltage for 800, 4
521 22:12:42.981230 Vio18 = 0
522 22:12:42.981312 Vcore = 650000
523 22:12:42.981379 Vdram = 0
524 22:12:42.985111 Vddq = 0
525 22:12:42.985194 Vmddr = 0
526 22:12:42.988857 dram_init: config_dvfs: 1
527 22:12:42.992767 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 22:12:42.995933 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 22:12:43.000182 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=10
530 22:12:43.003577 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=10
531 22:12:43.010102 [SwImpedanceCal] DRVP=12, DRVN=25, ODTN=9
532 22:12:43.013892 freq_region=1, Reg: DRVP=12, DRVN=25, ODTN=9
533 22:12:43.013976 MEM_TYPE=3, freq_sel=18
534 22:12:43.016498 sv_algorithm_assistance_LP4_1600
535 22:12:43.023850 ============ PULL DRAM RESETB DOWN ============
536 22:12:43.026997 ========== PULL DRAM RESETB DOWN end =========
537 22:12:43.030402 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 22:12:43.033949 ===================================
539 22:12:43.036921 LPDDR4 DRAM CONFIGURATION
540 22:12:43.040325 ===================================
541 22:12:43.040409 EX_ROW_EN[0] = 0x0
542 22:12:43.043674 EX_ROW_EN[1] = 0x0
543 22:12:43.046931 LP4Y_EN = 0x0
544 22:12:43.047014 WORK_FSP = 0x0
545 22:12:43.050608 WL = 0x2
546 22:12:43.050752 RL = 0x2
547 22:12:43.053795 BL = 0x2
548 22:12:43.053878 RPST = 0x0
549 22:12:43.057001 RD_PRE = 0x0
550 22:12:43.057083 WR_PRE = 0x1
551 22:12:43.060136 WR_PST = 0x0
552 22:12:43.060219 DBI_WR = 0x0
553 22:12:43.063643 DBI_RD = 0x0
554 22:12:43.063725 OTF = 0x1
555 22:12:43.067145 ===================================
556 22:12:43.070399 ===================================
557 22:12:43.073287 ANA top config
558 22:12:43.076664 ===================================
559 22:12:43.076747 DLL_ASYNC_EN = 0
560 22:12:43.080289 ALL_SLAVE_EN = 1
561 22:12:43.083447 NEW_RANK_MODE = 1
562 22:12:43.086863 DLL_IDLE_MODE = 1
563 22:12:43.086947 LP45_APHY_COMB_EN = 1
564 22:12:43.090094 TX_ODT_DIS = 1
565 22:12:43.094039 NEW_8X_MODE = 1
566 22:12:43.096835 ===================================
567 22:12:43.100485 ===================================
568 22:12:43.104146 data_rate = 1600
569 22:12:43.107187 CKR = 1
570 22:12:43.107270 DQ_P2S_RATIO = 8
571 22:12:43.110583 ===================================
572 22:12:43.113769 CA_P2S_RATIO = 8
573 22:12:43.117123 DQ_CA_OPEN = 0
574 22:12:43.120424 DQ_SEMI_OPEN = 0
575 22:12:43.123975 CA_SEMI_OPEN = 0
576 22:12:43.127473 CA_FULL_RATE = 0
577 22:12:43.127567 DQ_CKDIV4_EN = 1
578 22:12:43.130379 CA_CKDIV4_EN = 1
579 22:12:43.134510 CA_PREDIV_EN = 0
580 22:12:43.137095 PH8_DLY = 0
581 22:12:43.140166 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 22:12:43.143913 DQ_AAMCK_DIV = 4
583 22:12:43.144038 CA_AAMCK_DIV = 4
584 22:12:43.146982 CA_ADMCK_DIV = 4
585 22:12:43.150686 DQ_TRACK_CA_EN = 0
586 22:12:43.153541 CA_PICK = 800
587 22:12:43.157206 CA_MCKIO = 800
588 22:12:43.160649 MCKIO_SEMI = 0
589 22:12:43.160735 PLL_FREQ = 3068
590 22:12:43.164043 DQ_UI_PI_RATIO = 32
591 22:12:43.168244 CA_UI_PI_RATIO = 0
592 22:12:43.171325 ===================================
593 22:12:43.175714 ===================================
594 22:12:43.178841 memory_type:LPDDR4
595 22:12:43.178935 GP_NUM : 10
596 22:12:43.182378 SRAM_EN : 1
597 22:12:43.182461 MD32_EN : 0
598 22:12:43.185751 ===================================
599 22:12:43.189584 [ANA_INIT] >>>>>>>>>>>>>>
600 22:12:43.192956 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 22:12:43.193056 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 22:12:43.196992 ===================================
603 22:12:43.200581 data_rate = 1600,PCW = 0X7600
604 22:12:43.203994 ===================================
605 22:12:43.207082 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 22:12:43.213523 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 22:12:43.216630 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 22:12:43.223846 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 22:12:43.226961 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 22:12:43.230854 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 22:12:43.233426 [ANA_INIT] flow start
612 22:12:43.233510 [ANA_INIT] PLL >>>>>>>>
613 22:12:43.237126 [ANA_INIT] PLL <<<<<<<<
614 22:12:43.240307 [ANA_INIT] MIDPI >>>>>>>>
615 22:12:43.240391 [ANA_INIT] MIDPI <<<<<<<<
616 22:12:43.243734 [ANA_INIT] DLL >>>>>>>>
617 22:12:43.246877 [ANA_INIT] flow end
618 22:12:43.250502 ============ LP4 DIFF to SE enter ============
619 22:12:43.253817 ============ LP4 DIFF to SE exit ============
620 22:12:43.257665 [ANA_INIT] <<<<<<<<<<<<<
621 22:12:43.260727 [Flow] Enable top DCM control >>>>>
622 22:12:43.263972 [Flow] Enable top DCM control <<<<<
623 22:12:43.267311 Enable DLL master slave shuffle
624 22:12:43.270471 ==============================================================
625 22:12:43.274335 Gating Mode config
626 22:12:43.276959 ==============================================================
627 22:12:43.280968 Config description:
628 22:12:43.291329 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 22:12:43.297566 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 22:12:43.300562 SELPH_MODE 0: By rank 1: By Phase
631 22:12:43.307260 ==============================================================
632 22:12:43.310274 GAT_TRACK_EN = 1
633 22:12:43.314117 RX_GATING_MODE = 2
634 22:12:43.317367 RX_GATING_TRACK_MODE = 2
635 22:12:43.320291 SELPH_MODE = 1
636 22:12:43.320391 PICG_EARLY_EN = 1
637 22:12:43.323877 VALID_LAT_VALUE = 1
638 22:12:43.331031 ==============================================================
639 22:12:43.333958 Enter into Gating configuration >>>>
640 22:12:43.337192 Exit from Gating configuration <<<<
641 22:12:43.340292 Enter into DVFS_PRE_config >>>>>
642 22:12:43.350638 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 22:12:43.354286 Exit from DVFS_PRE_config <<<<<
644 22:12:43.357562 Enter into PICG configuration >>>>
645 22:12:43.360685 Exit from PICG configuration <<<<
646 22:12:43.363904 [RX_INPUT] configuration >>>>>
647 22:12:43.367189 [RX_INPUT] configuration <<<<<
648 22:12:43.370443 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 22:12:43.377420 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 22:12:43.384960 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 22:12:43.388195 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 22:12:43.394562 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 22:12:43.401310 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 22:12:43.404721 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 22:12:43.408116 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 22:12:43.414846 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 22:12:43.418066 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 22:12:43.421359 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 22:12:43.427814 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 22:12:43.431564 ===================================
661 22:12:43.431728 LPDDR4 DRAM CONFIGURATION
662 22:12:43.434924 ===================================
663 22:12:43.438048 EX_ROW_EN[0] = 0x0
664 22:12:43.438164 EX_ROW_EN[1] = 0x0
665 22:12:43.441951 LP4Y_EN = 0x0
666 22:12:43.442079 WORK_FSP = 0x0
667 22:12:43.444855 WL = 0x2
668 22:12:43.444938 RL = 0x2
669 22:12:43.447721 BL = 0x2
670 22:12:43.451074 RPST = 0x0
671 22:12:43.451206 RD_PRE = 0x0
672 22:12:43.454507 WR_PRE = 0x1
673 22:12:43.454591 WR_PST = 0x0
674 22:12:43.457836 DBI_WR = 0x0
675 22:12:43.457967 DBI_RD = 0x0
676 22:12:43.461000 OTF = 0x1
677 22:12:43.464459 ===================================
678 22:12:43.467693 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 22:12:43.471106 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 22:12:43.474589 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 22:12:43.478142 ===================================
682 22:12:43.481432 LPDDR4 DRAM CONFIGURATION
683 22:12:43.484245 ===================================
684 22:12:43.488162 EX_ROW_EN[0] = 0x10
685 22:12:43.488279 EX_ROW_EN[1] = 0x0
686 22:12:43.490826 LP4Y_EN = 0x0
687 22:12:43.490909 WORK_FSP = 0x0
688 22:12:43.494939 WL = 0x2
689 22:12:43.495022 RL = 0x2
690 22:12:43.497921 BL = 0x2
691 22:12:43.498004 RPST = 0x0
692 22:12:43.500995 RD_PRE = 0x0
693 22:12:43.504167 WR_PRE = 0x1
694 22:12:43.504250 WR_PST = 0x0
695 22:12:43.507726 DBI_WR = 0x0
696 22:12:43.507809 DBI_RD = 0x0
697 22:12:43.511244 OTF = 0x1
698 22:12:43.514877 ===================================
699 22:12:43.518079 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 22:12:43.523472 nWR fixed to 40
701 22:12:43.526674 [ModeRegInit_LP4] CH0 RK0
702 22:12:43.526763 [ModeRegInit_LP4] CH0 RK1
703 22:12:43.529622 [ModeRegInit_LP4] CH1 RK0
704 22:12:43.532724 [ModeRegInit_LP4] CH1 RK1
705 22:12:43.532808 match AC timing 13
706 22:12:43.539878 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 22:12:43.543219 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 22:12:43.546471 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 22:12:43.553236 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 22:12:43.556633 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 22:12:43.556716 [EMI DOE] emi_dcm 0
712 22:12:43.563116 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 22:12:43.563200 ==
714 22:12:43.566591 Dram Type= 6, Freq= 0, CH_0, rank 0
715 22:12:43.569743 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 22:12:43.569828 ==
717 22:12:43.576354 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 22:12:43.579833 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 22:12:43.590816 [CA 0] Center 37 (7~68) winsize 62
720 22:12:43.593790 [CA 1] Center 37 (6~68) winsize 63
721 22:12:43.597019 [CA 2] Center 35 (5~66) winsize 62
722 22:12:43.600298 [CA 3] Center 34 (4~65) winsize 62
723 22:12:43.603698 [CA 4] Center 33 (3~64) winsize 62
724 22:12:43.607011 [CA 5] Center 33 (3~64) winsize 62
725 22:12:43.607114
726 22:12:43.610719 [CmdBusTrainingLP45] Vref(ca) range 1: 34
727 22:12:43.610801
728 22:12:43.613906 [CATrainingPosCal] consider 1 rank data
729 22:12:43.616951 u2DelayCellTimex100 = 270/100 ps
730 22:12:43.620640 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
731 22:12:43.623712 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
732 22:12:43.631467 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
733 22:12:43.634345 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
734 22:12:43.637415 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
735 22:12:43.640439 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
736 22:12:43.640541
737 22:12:43.643629 CA PerBit enable=1, Macro0, CA PI delay=33
738 22:12:43.643709
739 22:12:43.647048 [CBTSetCACLKResult] CA Dly = 33
740 22:12:43.647152 CS Dly: 5 (0~36)
741 22:12:43.647250 ==
742 22:12:43.650524 Dram Type= 6, Freq= 0, CH_0, rank 1
743 22:12:43.657602 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 22:12:43.657713 ==
745 22:12:43.660429 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 22:12:43.667142 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 22:12:43.676723 [CA 0] Center 37 (7~68) winsize 62
748 22:12:43.679879 [CA 1] Center 37 (7~68) winsize 62
749 22:12:43.683071 [CA 2] Center 35 (4~66) winsize 63
750 22:12:43.686684 [CA 3] Center 35 (4~66) winsize 63
751 22:12:43.689666 [CA 4] Center 34 (4~65) winsize 62
752 22:12:43.693823 [CA 5] Center 33 (3~64) winsize 62
753 22:12:43.693932
754 22:12:43.696709 [CmdBusTrainingLP45] Vref(ca) range 1: 34
755 22:12:43.696785
756 22:12:43.700068 [CATrainingPosCal] consider 2 rank data
757 22:12:43.703771 u2DelayCellTimex100 = 270/100 ps
758 22:12:43.706538 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
759 22:12:43.709835 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
760 22:12:43.717214 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
761 22:12:43.719949 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
762 22:12:43.724102 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
763 22:12:43.726728 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
764 22:12:43.726811
765 22:12:43.729900 CA PerBit enable=1, Macro0, CA PI delay=33
766 22:12:43.729984
767 22:12:43.733478 [CBTSetCACLKResult] CA Dly = 33
768 22:12:43.733562 CS Dly: 6 (0~38)
769 22:12:43.733629
770 22:12:43.736934 ----->DramcWriteLeveling(PI) begin...
771 22:12:43.740406 ==
772 22:12:43.740506 Dram Type= 6, Freq= 0, CH_0, rank 0
773 22:12:43.746814 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 22:12:43.746899 ==
775 22:12:43.750351 Write leveling (Byte 0): 30 => 30
776 22:12:43.750461 Write leveling (Byte 1): 30 => 30
777 22:12:43.754858 DramcWriteLeveling(PI) end<-----
778 22:12:43.754959
779 22:12:43.755051 ==
780 22:12:43.757557 Dram Type= 6, Freq= 0, CH_0, rank 0
781 22:12:43.761168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 22:12:43.764663 ==
783 22:12:43.764778 [Gating] SW mode calibration
784 22:12:43.775622 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 22:12:43.779032 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 22:12:43.782219 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 22:12:43.785474 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
788 22:12:43.792342 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
789 22:12:43.796054 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
790 22:12:43.798932 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 22:12:43.805543 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 22:12:43.808960 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 22:12:43.812157 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 22:12:43.818696 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 22:12:43.822117 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 22:12:43.825394 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 22:12:43.832504 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 22:12:43.835554 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 22:12:43.839338 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 22:12:43.845935 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 22:12:43.848996 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 22:12:43.852090 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 22:12:43.855553 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 22:12:43.862434 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
805 22:12:43.865562 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 22:12:43.869463 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 22:12:43.875967 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 22:12:43.879374 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 22:12:43.882415 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 22:12:43.888944 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 22:12:43.892082 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 22:12:43.895517 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
813 22:12:43.902324 0 9 12 | B1->B0 | 2b2b 3030 | 0 1 | (0 0) (1 1)
814 22:12:43.905621 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 22:12:43.909010 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 22:12:43.916068 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 22:12:43.919699 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 22:12:43.922635 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 22:12:43.925925 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
820 22:12:43.932578 0 10 8 | B1->B0 | 3333 3030 | 0 0 | (0 0) (0 1)
821 22:12:43.935976 0 10 12 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
822 22:12:43.939039 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 22:12:43.945797 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 22:12:43.948933 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 22:12:43.952440 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 22:12:43.959208 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 22:12:43.962812 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 22:12:43.965605 0 11 8 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
829 22:12:43.973399 0 11 12 | B1->B0 | 3737 4242 | 1 1 | (0 0) (0 0)
830 22:12:43.976161 0 11 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
831 22:12:43.979364 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 22:12:43.986643 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 22:12:43.989612 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 22:12:43.993006 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 22:12:43.998975 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
836 22:12:44.002978 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
837 22:12:44.006446 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
838 22:12:44.012702 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 22:12:44.016061 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 22:12:44.019113 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 22:12:44.022681 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 22:12:44.029225 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 22:12:44.032833 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 22:12:44.036043 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 22:12:44.042941 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 22:12:44.046282 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 22:12:44.049609 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 22:12:44.055850 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 22:12:44.059255 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 22:12:44.063093 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 22:12:44.069529 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
852 22:12:44.072812 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
853 22:12:44.076299 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
854 22:12:44.079404 Total UI for P1: 0, mck2ui 16
855 22:12:44.082594 best dqsien dly found for B0: ( 0, 14, 8)
856 22:12:44.086168 Total UI for P1: 0, mck2ui 16
857 22:12:44.089624 best dqsien dly found for B1: ( 0, 14, 8)
858 22:12:44.092957 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
859 22:12:44.096569 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
860 22:12:44.096654
861 22:12:44.099434 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
862 22:12:44.106371 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
863 22:12:44.106456 [Gating] SW calibration Done
864 22:12:44.106524 ==
865 22:12:44.109157 Dram Type= 6, Freq= 0, CH_0, rank 0
866 22:12:44.115794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
867 22:12:44.115881 ==
868 22:12:44.115949 RX Vref Scan: 0
869 22:12:44.116055
870 22:12:44.119514 RX Vref 0 -> 0, step: 1
871 22:12:44.119599
872 22:12:44.122429 RX Delay -130 -> 252, step: 16
873 22:12:44.125848 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
874 22:12:44.129844 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
875 22:12:44.132462 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
876 22:12:44.139151 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
877 22:12:44.142559 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
878 22:12:44.146452 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
879 22:12:44.149837 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
880 22:12:44.152557 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
881 22:12:44.159020 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
882 22:12:44.163604 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
883 22:12:44.165800 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
884 22:12:44.169274 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
885 22:12:44.172446 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
886 22:12:44.179233 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
887 22:12:44.182854 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
888 22:12:44.185785 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
889 22:12:44.185870 ==
890 22:12:44.188982 Dram Type= 6, Freq= 0, CH_0, rank 0
891 22:12:44.192468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
892 22:12:44.192554 ==
893 22:12:44.195910 DQS Delay:
894 22:12:44.196019 DQS0 = 0, DQS1 = 0
895 22:12:44.199751 DQM Delay:
896 22:12:44.199834 DQM0 = 87, DQM1 = 79
897 22:12:44.199903 DQ Delay:
898 22:12:44.202301 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
899 22:12:44.206495 DQ4 =85, DQ5 =77, DQ6 =101, DQ7 =93
900 22:12:44.209387 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
901 22:12:44.213184 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
902 22:12:44.213268
903 22:12:44.213337
904 22:12:44.215878 ==
905 22:12:44.215978 Dram Type= 6, Freq= 0, CH_0, rank 0
906 22:12:44.222517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
907 22:12:44.222600 ==
908 22:12:44.222667
909 22:12:44.222738
910 22:12:44.225875 TX Vref Scan disable
911 22:12:44.225953 == TX Byte 0 ==
912 22:12:44.228979 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
913 22:12:44.235894 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
914 22:12:44.235983 == TX Byte 1 ==
915 22:12:44.239300 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
916 22:12:44.245841 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
917 22:12:44.245921 ==
918 22:12:44.249065 Dram Type= 6, Freq= 0, CH_0, rank 0
919 22:12:44.252402 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
920 22:12:44.252486 ==
921 22:12:44.265753 TX Vref=22, minBit 0, minWin=27, winSum=440
922 22:12:44.268759 TX Vref=24, minBit 5, minWin=27, winSum=442
923 22:12:44.272409 TX Vref=26, minBit 5, minWin=27, winSum=448
924 22:12:44.276074 TX Vref=28, minBit 5, minWin=27, winSum=451
925 22:12:44.279228 TX Vref=30, minBit 12, minWin=27, winSum=452
926 22:12:44.283129 TX Vref=32, minBit 1, minWin=28, winSum=453
927 22:12:44.288865 [TxChooseVref] Worse bit 1, Min win 28, Win sum 453, Final Vref 32
928 22:12:44.288952
929 22:12:44.292459 Final TX Range 1 Vref 32
930 22:12:44.292544
931 22:12:44.292612 ==
932 22:12:44.295620 Dram Type= 6, Freq= 0, CH_0, rank 0
933 22:12:44.299111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 22:12:44.299196 ==
935 22:12:44.299264
936 22:12:44.302447
937 22:12:44.302531 TX Vref Scan disable
938 22:12:44.306012 == TX Byte 0 ==
939 22:12:44.308899 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
940 22:12:44.313190 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
941 22:12:44.316084 == TX Byte 1 ==
942 22:12:44.319487 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
943 22:12:44.322466 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
944 22:12:44.325520
945 22:12:44.325636 [DATLAT]
946 22:12:44.325733 Freq=800, CH0 RK0
947 22:12:44.325827
948 22:12:44.329267 DATLAT Default: 0xa
949 22:12:44.329393 0, 0xFFFF, sum = 0
950 22:12:44.332366 1, 0xFFFF, sum = 0
951 22:12:44.332475 2, 0xFFFF, sum = 0
952 22:12:44.335540 3, 0xFFFF, sum = 0
953 22:12:44.335643 4, 0xFFFF, sum = 0
954 22:12:44.339200 5, 0xFFFF, sum = 0
955 22:12:44.339312 6, 0xFFFF, sum = 0
956 22:12:44.342298 7, 0xFFFF, sum = 0
957 22:12:44.342408 8, 0xFFFF, sum = 0
958 22:12:44.345457 9, 0x0, sum = 1
959 22:12:44.345536 10, 0x0, sum = 2
960 22:12:44.348670 11, 0x0, sum = 3
961 22:12:44.348775 12, 0x0, sum = 4
962 22:12:44.352898 best_step = 10
963 22:12:44.353000
964 22:12:44.353068 ==
965 22:12:44.355418 Dram Type= 6, Freq= 0, CH_0, rank 0
966 22:12:44.358950 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
967 22:12:44.359079 ==
968 22:12:44.362903 RX Vref Scan: 1
969 22:12:44.362986
970 22:12:44.363052 Set Vref Range= 32 -> 127
971 22:12:44.363114
972 22:12:44.366092 RX Vref 32 -> 127, step: 1
973 22:12:44.366189
974 22:12:44.369454 RX Delay -95 -> 252, step: 8
975 22:12:44.369551
976 22:12:44.372771 Set Vref, RX VrefLevel [Byte0]: 32
977 22:12:44.376204 [Byte1]: 32
978 22:12:44.376288
979 22:12:44.379038 Set Vref, RX VrefLevel [Byte0]: 33
980 22:12:44.382411 [Byte1]: 33
981 22:12:44.386693
982 22:12:44.386776 Set Vref, RX VrefLevel [Byte0]: 34
983 22:12:44.389405 [Byte1]: 34
984 22:12:44.393319
985 22:12:44.393402 Set Vref, RX VrefLevel [Byte0]: 35
986 22:12:44.396861 [Byte1]: 35
987 22:12:44.401164
988 22:12:44.401246 Set Vref, RX VrefLevel [Byte0]: 36
989 22:12:44.404261 [Byte1]: 36
990 22:12:44.409217
991 22:12:44.409300 Set Vref, RX VrefLevel [Byte0]: 37
992 22:12:44.411820 [Byte1]: 37
993 22:12:44.416484
994 22:12:44.416568 Set Vref, RX VrefLevel [Byte0]: 38
995 22:12:44.419806 [Byte1]: 38
996 22:12:44.423859
997 22:12:44.423996 Set Vref, RX VrefLevel [Byte0]: 39
998 22:12:44.427500 [Byte1]: 39
999 22:12:44.431856
1000 22:12:44.432009 Set Vref, RX VrefLevel [Byte0]: 40
1001 22:12:44.435172 [Byte1]: 40
1002 22:12:44.439173
1003 22:12:44.439294 Set Vref, RX VrefLevel [Byte0]: 41
1004 22:12:44.442471 [Byte1]: 41
1005 22:12:44.446652
1006 22:12:44.446736 Set Vref, RX VrefLevel [Byte0]: 42
1007 22:12:44.449959 [Byte1]: 42
1008 22:12:44.454033
1009 22:12:44.454118 Set Vref, RX VrefLevel [Byte0]: 43
1010 22:12:44.457526 [Byte1]: 43
1011 22:12:44.461712
1012 22:12:44.461797 Set Vref, RX VrefLevel [Byte0]: 44
1013 22:12:44.465315 [Byte1]: 44
1014 22:12:44.469249
1015 22:12:44.469353 Set Vref, RX VrefLevel [Byte0]: 45
1016 22:12:44.473490 [Byte1]: 45
1017 22:12:44.477046
1018 22:12:44.477130 Set Vref, RX VrefLevel [Byte0]: 46
1019 22:12:44.484084 [Byte1]: 46
1020 22:12:44.484168
1021 22:12:44.486838 Set Vref, RX VrefLevel [Byte0]: 47
1022 22:12:44.490448 [Byte1]: 47
1023 22:12:44.490533
1024 22:12:44.493267 Set Vref, RX VrefLevel [Byte0]: 48
1025 22:12:44.497239 [Byte1]: 48
1026 22:12:44.497323
1027 22:12:44.500822 Set Vref, RX VrefLevel [Byte0]: 49
1028 22:12:44.503358 [Byte1]: 49
1029 22:12:44.507134
1030 22:12:44.507218 Set Vref, RX VrefLevel [Byte0]: 50
1031 22:12:44.510889 [Byte1]: 50
1032 22:12:44.515157
1033 22:12:44.515240 Set Vref, RX VrefLevel [Byte0]: 51
1034 22:12:44.518186 [Byte1]: 51
1035 22:12:44.522489
1036 22:12:44.522572 Set Vref, RX VrefLevel [Byte0]: 52
1037 22:12:44.526128 [Byte1]: 52
1038 22:12:44.530169
1039 22:12:44.530252 Set Vref, RX VrefLevel [Byte0]: 53
1040 22:12:44.533850 [Byte1]: 53
1041 22:12:44.537383
1042 22:12:44.537466 Set Vref, RX VrefLevel [Byte0]: 54
1043 22:12:44.541113 [Byte1]: 54
1044 22:12:44.545247
1045 22:12:44.545330 Set Vref, RX VrefLevel [Byte0]: 55
1046 22:12:44.548889 [Byte1]: 55
1047 22:12:44.552800
1048 22:12:44.552883 Set Vref, RX VrefLevel [Byte0]: 56
1049 22:12:44.556573 [Byte1]: 56
1050 22:12:44.560325
1051 22:12:44.560408 Set Vref, RX VrefLevel [Byte0]: 57
1052 22:12:44.563819 [Byte1]: 57
1053 22:12:44.568042
1054 22:12:44.568128 Set Vref, RX VrefLevel [Byte0]: 58
1055 22:12:44.571228 [Byte1]: 58
1056 22:12:44.576088
1057 22:12:44.576167 Set Vref, RX VrefLevel [Byte0]: 59
1058 22:12:44.581870 [Byte1]: 59
1059 22:12:44.581960
1060 22:12:44.585503 Set Vref, RX VrefLevel [Byte0]: 60
1061 22:12:44.588823 [Byte1]: 60
1062 22:12:44.588951
1063 22:12:44.592180 Set Vref, RX VrefLevel [Byte0]: 61
1064 22:12:44.595138 [Byte1]: 61
1065 22:12:44.595236
1066 22:12:44.599370 Set Vref, RX VrefLevel [Byte0]: 62
1067 22:12:44.602410 [Byte1]: 62
1068 22:12:44.605934
1069 22:12:44.606020 Set Vref, RX VrefLevel [Byte0]: 63
1070 22:12:44.609375 [Byte1]: 63
1071 22:12:44.613530
1072 22:12:44.613617 Set Vref, RX VrefLevel [Byte0]: 64
1073 22:12:44.616965 [Byte1]: 64
1074 22:12:44.621327
1075 22:12:44.621411 Set Vref, RX VrefLevel [Byte0]: 65
1076 22:12:44.624438 [Byte1]: 65
1077 22:12:44.628980
1078 22:12:44.629063 Set Vref, RX VrefLevel [Byte0]: 66
1079 22:12:44.632305 [Byte1]: 66
1080 22:12:44.636476
1081 22:12:44.636558 Set Vref, RX VrefLevel [Byte0]: 67
1082 22:12:44.640304 [Byte1]: 67
1083 22:12:44.644243
1084 22:12:44.644328 Set Vref, RX VrefLevel [Byte0]: 68
1085 22:12:44.647484 [Byte1]: 68
1086 22:12:44.651800
1087 22:12:44.651915 Set Vref, RX VrefLevel [Byte0]: 69
1088 22:12:44.655280 [Byte1]: 69
1089 22:12:44.659009
1090 22:12:44.659092 Set Vref, RX VrefLevel [Byte0]: 70
1091 22:12:44.662765 [Byte1]: 70
1092 22:12:44.667294
1093 22:12:44.667382 Set Vref, RX VrefLevel [Byte0]: 71
1094 22:12:44.670565 [Byte1]: 71
1095 22:12:44.674606
1096 22:12:44.674708 Set Vref, RX VrefLevel [Byte0]: 72
1097 22:12:44.677796 [Byte1]: 72
1098 22:12:44.682370
1099 22:12:44.682473 Set Vref, RX VrefLevel [Byte0]: 73
1100 22:12:44.685195 [Byte1]: 73
1101 22:12:44.689704
1102 22:12:44.689792 Set Vref, RX VrefLevel [Byte0]: 74
1103 22:12:44.693194 [Byte1]: 74
1104 22:12:44.697370
1105 22:12:44.697454 Set Vref, RX VrefLevel [Byte0]: 75
1106 22:12:44.700574 [Byte1]: 75
1107 22:12:44.704695
1108 22:12:44.704779 Set Vref, RX VrefLevel [Byte0]: 76
1109 22:12:44.708106 [Byte1]: 76
1110 22:12:44.712280
1111 22:12:44.712369 Final RX Vref Byte 0 = 63 to rank0
1112 22:12:44.715762 Final RX Vref Byte 1 = 57 to rank0
1113 22:12:44.719694 Final RX Vref Byte 0 = 63 to rank1
1114 22:12:44.722814 Final RX Vref Byte 1 = 57 to rank1==
1115 22:12:44.725612 Dram Type= 6, Freq= 0, CH_0, rank 0
1116 22:12:44.732871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1117 22:12:44.732967 ==
1118 22:12:44.733035 DQS Delay:
1119 22:12:44.733096 DQS0 = 0, DQS1 = 0
1120 22:12:44.735856 DQM Delay:
1121 22:12:44.735990 DQM0 = 87, DQM1 = 80
1122 22:12:44.739080 DQ Delay:
1123 22:12:44.742865 DQ0 =88, DQ1 =92, DQ2 =84, DQ3 =84
1124 22:12:44.742949 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =92
1125 22:12:44.745924 DQ8 =68, DQ9 =68, DQ10 =84, DQ11 =76
1126 22:12:44.749267 DQ12 =84, DQ13 =80, DQ14 =92, DQ15 =88
1127 22:12:44.752377
1128 22:12:44.752463
1129 22:12:44.759511 [DQSOSCAuto] RK0, (LSB)MR18= 0x260d, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 400 ps
1130 22:12:44.762665 CH0 RK0: MR19=606, MR18=260D
1131 22:12:44.768953 CH0_RK0: MR19=0x606, MR18=0x260D, DQSOSC=400, MR23=63, INC=92, DEC=61
1132 22:12:44.769049
1133 22:12:44.772471 ----->DramcWriteLeveling(PI) begin...
1134 22:12:44.772559 ==
1135 22:12:44.775950 Dram Type= 6, Freq= 0, CH_0, rank 1
1136 22:12:44.779710 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1137 22:12:44.779797 ==
1138 22:12:44.782871 Write leveling (Byte 0): 28 => 28
1139 22:12:44.785859 Write leveling (Byte 1): 31 => 31
1140 22:12:44.789330 DramcWriteLeveling(PI) end<-----
1141 22:12:44.789425
1142 22:12:44.789492 ==
1143 22:12:44.793247 Dram Type= 6, Freq= 0, CH_0, rank 1
1144 22:12:44.795911 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1145 22:12:44.796045 ==
1146 22:12:44.799321 [Gating] SW mode calibration
1147 22:12:44.806348 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1148 22:12:44.812466 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1149 22:12:44.815941 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1150 22:12:44.819184 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1151 22:12:44.866683 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1152 22:12:44.866830 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1153 22:12:44.867090 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1154 22:12:44.867718 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 22:12:44.868003 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 22:12:44.868268 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 22:12:44.868340 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 22:12:44.868808 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 22:12:44.869124 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 22:12:44.869216 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 22:12:44.892823 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 22:12:44.893022 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 22:12:44.893286 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 22:12:44.893654 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 22:12:44.894023 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 22:12:44.894106 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
1167 22:12:44.896566 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1168 22:12:44.899813 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 22:12:44.903242 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 22:12:44.906579 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 22:12:44.913517 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 22:12:44.916677 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 22:12:44.919763 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 22:12:44.926528 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 22:12:44.929846 0 9 8 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
1176 22:12:44.933015 0 9 12 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
1177 22:12:44.939882 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1178 22:12:44.943477 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1179 22:12:44.946575 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1180 22:12:44.954090 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 22:12:44.956627 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1182 22:12:44.959619 0 10 4 | B1->B0 | 3434 3232 | 1 0 | (1 0) (0 1)
1183 22:12:44.966065 0 10 8 | B1->B0 | 3434 2929 | 0 0 | (0 1) (1 1)
1184 22:12:44.969725 0 10 12 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
1185 22:12:44.973310 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 22:12:44.980357 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 22:12:44.982824 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 22:12:44.986351 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 22:12:44.993036 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 22:12:44.996501 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 22:12:44.999916 0 11 8 | B1->B0 | 2f2f 3e3e | 0 0 | (0 0) (0 0)
1192 22:12:45.003364 0 11 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
1193 22:12:45.010703 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1194 22:12:45.014524 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1195 22:12:45.017459 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1196 22:12:45.021078 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 22:12:45.027718 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 22:12:45.031000 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 22:12:45.034322 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1200 22:12:45.041128 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1201 22:12:45.044707 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 22:12:45.047780 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 22:12:45.055184 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 22:12:45.057757 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 22:12:45.060993 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 22:12:45.064783 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 22:12:45.071472 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 22:12:45.074646 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 22:12:45.077975 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 22:12:45.084746 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 22:12:45.088022 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 22:12:45.091508 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 22:12:45.098534 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 22:12:45.101402 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 22:12:45.104309 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1216 22:12:45.111518 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1217 22:12:45.111615 Total UI for P1: 0, mck2ui 16
1218 22:12:45.118111 best dqsien dly found for B0: ( 0, 14, 8)
1219 22:12:45.118200 Total UI for P1: 0, mck2ui 16
1220 22:12:45.124852 best dqsien dly found for B1: ( 0, 14, 10)
1221 22:12:45.128096 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1222 22:12:45.131644 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1223 22:12:45.131731
1224 22:12:45.134239 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1225 22:12:45.138019 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1226 22:12:45.141125 [Gating] SW calibration Done
1227 22:12:45.141204 ==
1228 22:12:45.144433 Dram Type= 6, Freq= 0, CH_0, rank 1
1229 22:12:45.147661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1230 22:12:45.147742 ==
1231 22:12:45.150998 RX Vref Scan: 0
1232 22:12:45.151073
1233 22:12:45.151134 RX Vref 0 -> 0, step: 1
1234 22:12:45.151193
1235 22:12:45.154419 RX Delay -130 -> 252, step: 16
1236 22:12:45.158054 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1237 22:12:45.164729 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1238 22:12:45.167745 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
1239 22:12:45.171603 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1240 22:12:45.174936 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1241 22:12:45.178115 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1242 22:12:45.184658 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1243 22:12:45.188172 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1244 22:12:45.191072 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1245 22:12:45.194779 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1246 22:12:45.198197 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1247 22:12:45.204490 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1248 22:12:45.208506 iDelay=222, Bit 12, Center 69 (-50 ~ 189) 240
1249 22:12:45.211127 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1250 22:12:45.214463 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1251 22:12:45.218247 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1252 22:12:45.221660 ==
1253 22:12:45.221757 Dram Type= 6, Freq= 0, CH_0, rank 1
1254 22:12:45.228439 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1255 22:12:45.228542 ==
1256 22:12:45.228610 DQS Delay:
1257 22:12:45.231286 DQS0 = 0, DQS1 = 0
1258 22:12:45.231373 DQM Delay:
1259 22:12:45.235001 DQM0 = 90, DQM1 = 78
1260 22:12:45.235087 DQ Delay:
1261 22:12:45.238039 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =85
1262 22:12:45.241286 DQ4 =93, DQ5 =69, DQ6 =101, DQ7 =93
1263 22:12:45.244764 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
1264 22:12:45.248532 DQ12 =69, DQ13 =93, DQ14 =93, DQ15 =93
1265 22:12:45.248624
1266 22:12:45.248692
1267 22:12:45.248753 ==
1268 22:12:45.251355 Dram Type= 6, Freq= 0, CH_0, rank 1
1269 22:12:45.254849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1270 22:12:45.254937 ==
1271 22:12:45.255004
1272 22:12:45.255064
1273 22:12:45.258426 TX Vref Scan disable
1274 22:12:45.261776 == TX Byte 0 ==
1275 22:12:45.265720 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1276 22:12:45.268294 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1277 22:12:45.268381 == TX Byte 1 ==
1278 22:12:45.274561 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1279 22:12:45.278271 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1280 22:12:45.278361 ==
1281 22:12:45.281679 Dram Type= 6, Freq= 0, CH_0, rank 1
1282 22:12:45.284620 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1283 22:12:45.284710 ==
1284 22:12:45.298984 TX Vref=22, minBit 0, minWin=27, winSum=442
1285 22:12:45.302100 TX Vref=24, minBit 3, minWin=27, winSum=447
1286 22:12:45.306032 TX Vref=26, minBit 3, minWin=27, winSum=446
1287 22:12:45.309156 TX Vref=28, minBit 7, minWin=27, winSum=450
1288 22:12:45.312386 TX Vref=30, minBit 0, minWin=28, winSum=452
1289 22:12:45.316417 TX Vref=32, minBit 0, minWin=28, winSum=451
1290 22:12:45.322620 [TxChooseVref] Worse bit 0, Min win 28, Win sum 452, Final Vref 30
1291 22:12:45.322738
1292 22:12:45.326183 Final TX Range 1 Vref 30
1293 22:12:45.326278
1294 22:12:45.326344 ==
1295 22:12:45.328969 Dram Type= 6, Freq= 0, CH_0, rank 1
1296 22:12:45.332503 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1297 22:12:45.332594 ==
1298 22:12:45.332659
1299 22:12:45.335743
1300 22:12:45.335825 TX Vref Scan disable
1301 22:12:45.339314 == TX Byte 0 ==
1302 22:12:45.342024 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1303 22:12:45.349201 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1304 22:12:45.349299 == TX Byte 1 ==
1305 22:12:45.352409 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1306 22:12:45.359105 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1307 22:12:45.359202
1308 22:12:45.359267 [DATLAT]
1309 22:12:45.359327 Freq=800, CH0 RK1
1310 22:12:45.359385
1311 22:12:45.362290 DATLAT Default: 0xa
1312 22:12:45.362374 0, 0xFFFF, sum = 0
1313 22:12:45.365605 1, 0xFFFF, sum = 0
1314 22:12:45.365689 2, 0xFFFF, sum = 0
1315 22:12:45.368931 3, 0xFFFF, sum = 0
1316 22:12:45.369016 4, 0xFFFF, sum = 0
1317 22:12:45.372267 5, 0xFFFF, sum = 0
1318 22:12:45.375723 6, 0xFFFF, sum = 0
1319 22:12:45.375808 7, 0xFFFF, sum = 0
1320 22:12:45.378876 8, 0xFFFF, sum = 0
1321 22:12:45.378960 9, 0x0, sum = 1
1322 22:12:45.379025 10, 0x0, sum = 2
1323 22:12:45.382334 11, 0x0, sum = 3
1324 22:12:45.382420 12, 0x0, sum = 4
1325 22:12:45.385547 best_step = 10
1326 22:12:45.385630
1327 22:12:45.385693 ==
1328 22:12:45.389096 Dram Type= 6, Freq= 0, CH_0, rank 1
1329 22:12:45.391900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1330 22:12:45.392051 ==
1331 22:12:45.395178 RX Vref Scan: 0
1332 22:12:45.395261
1333 22:12:45.395325 RX Vref 0 -> 0, step: 1
1334 22:12:45.395385
1335 22:12:45.398522 RX Delay -95 -> 252, step: 8
1336 22:12:45.405380 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1337 22:12:45.408840 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1338 22:12:45.412158 iDelay=209, Bit 2, Center 84 (-31 ~ 200) 232
1339 22:12:45.416110 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1340 22:12:45.419039 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1341 22:12:45.425962 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1342 22:12:45.428991 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1343 22:12:45.431877 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1344 22:12:45.435723 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1345 22:12:45.439423 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1346 22:12:45.445311 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1347 22:12:45.449430 iDelay=209, Bit 11, Center 68 (-39 ~ 176) 216
1348 22:12:45.452728 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1349 22:12:45.455579 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1350 22:12:45.459124 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1351 22:12:45.465436 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1352 22:12:45.465540 ==
1353 22:12:45.468905 Dram Type= 6, Freq= 0, CH_0, rank 1
1354 22:12:45.472973 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1355 22:12:45.473065 ==
1356 22:12:45.473130 DQS Delay:
1357 22:12:45.475829 DQS0 = 0, DQS1 = 0
1358 22:12:45.475912 DQM Delay:
1359 22:12:45.478938 DQM0 = 87, DQM1 = 78
1360 22:12:45.479020 DQ Delay:
1361 22:12:45.482088 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1362 22:12:45.485459 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1363 22:12:45.489203 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1364 22:12:45.491949 DQ12 =80, DQ13 =84, DQ14 =88, DQ15 =88
1365 22:12:45.492101
1366 22:12:45.492195
1367 22:12:45.502037 [DQSOSCAuto] RK1, (LSB)MR18= 0x311b, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 397 ps
1368 22:12:45.502152 CH0 RK1: MR19=606, MR18=311B
1369 22:12:45.508455 CH0_RK1: MR19=0x606, MR18=0x311B, DQSOSC=397, MR23=63, INC=93, DEC=62
1370 22:12:45.511991 [RxdqsGatingPostProcess] freq 800
1371 22:12:45.518464 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1372 22:12:45.522102 Pre-setting of DQS Precalculation
1373 22:12:45.525099 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1374 22:12:45.525191 ==
1375 22:12:45.528481 Dram Type= 6, Freq= 0, CH_1, rank 0
1376 22:12:45.532328 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1377 22:12:45.535477 ==
1378 22:12:45.538607 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1379 22:12:45.545120 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1380 22:12:45.554118 [CA 0] Center 36 (6~67) winsize 62
1381 22:12:45.557094 [CA 1] Center 36 (6~67) winsize 62
1382 22:12:45.560124 [CA 2] Center 34 (4~64) winsize 61
1383 22:12:45.563713 [CA 3] Center 33 (3~64) winsize 62
1384 22:12:45.566915 [CA 4] Center 34 (3~65) winsize 63
1385 22:12:45.570417 [CA 5] Center 33 (3~64) winsize 62
1386 22:12:45.570511
1387 22:12:45.574171 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1388 22:12:45.574258
1389 22:12:45.577380 [CATrainingPosCal] consider 1 rank data
1390 22:12:45.580732 u2DelayCellTimex100 = 270/100 ps
1391 22:12:45.584112 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1392 22:12:45.587287 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1393 22:12:45.593503 CA2 delay=34 (4~64),Diff = 1 PI (7 cell)
1394 22:12:45.597126 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1395 22:12:45.600422 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
1396 22:12:45.603709 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1397 22:12:45.603841
1398 22:12:45.607051 CA PerBit enable=1, Macro0, CA PI delay=33
1399 22:12:45.607138
1400 22:12:45.610727 [CBTSetCACLKResult] CA Dly = 33
1401 22:12:45.610814 CS Dly: 4 (0~35)
1402 22:12:45.610881 ==
1403 22:12:45.614464 Dram Type= 6, Freq= 0, CH_1, rank 1
1404 22:12:45.620538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1405 22:12:45.620645 ==
1406 22:12:45.623464 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1407 22:12:45.630931 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1408 22:12:45.639615 [CA 0] Center 36 (5~67) winsize 63
1409 22:12:45.643154 [CA 1] Center 36 (6~67) winsize 62
1410 22:12:45.646639 [CA 2] Center 34 (3~65) winsize 63
1411 22:12:45.649581 [CA 3] Center 33 (3~64) winsize 62
1412 22:12:45.653364 [CA 4] Center 33 (3~64) winsize 62
1413 22:12:45.656463 [CA 5] Center 33 (3~64) winsize 62
1414 22:12:45.656554
1415 22:12:45.660471 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1416 22:12:45.660561
1417 22:12:45.663801 [CATrainingPosCal] consider 2 rank data
1418 22:12:45.667429 u2DelayCellTimex100 = 270/100 ps
1419 22:12:45.670217 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1420 22:12:45.674025 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1421 22:12:45.678189 CA2 delay=34 (4~64),Diff = 1 PI (7 cell)
1422 22:12:45.681991 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1423 22:12:45.685258 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1424 22:12:45.688961 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1425 22:12:45.689060
1426 22:12:45.691973 CA PerBit enable=1, Macro0, CA PI delay=33
1427 22:12:45.692087
1428 22:12:45.695851 [CBTSetCACLKResult] CA Dly = 33
1429 22:12:45.699018 CS Dly: 4 (0~36)
1430 22:12:45.699116
1431 22:12:45.702166 ----->DramcWriteLeveling(PI) begin...
1432 22:12:45.702255 ==
1433 22:12:45.705750 Dram Type= 6, Freq= 0, CH_1, rank 0
1434 22:12:45.709216 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1435 22:12:45.709330 ==
1436 22:12:45.712234 Write leveling (Byte 0): 27 => 27
1437 22:12:45.716134 Write leveling (Byte 1): 28 => 28
1438 22:12:45.719572 DramcWriteLeveling(PI) end<-----
1439 22:12:45.719665
1440 22:12:45.719733 ==
1441 22:12:45.722444 Dram Type= 6, Freq= 0, CH_1, rank 0
1442 22:12:45.725834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1443 22:12:45.725929 ==
1444 22:12:45.728777 [Gating] SW mode calibration
1445 22:12:45.735467 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1446 22:12:45.742333 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1447 22:12:45.745827 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1448 22:12:45.749123 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1449 22:12:45.755679 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1450 22:12:45.758737 0 6 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1451 22:12:45.762373 0 6 16 | B1->B0 | 2322 2323 | 1 0 | (0 0) (0 0)
1452 22:12:45.768477 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 22:12:45.771848 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 22:12:45.775427 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 22:12:45.781923 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 22:12:45.784945 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 22:12:45.788727 0 7 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1458 22:12:45.795405 0 7 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1459 22:12:45.798844 0 7 16 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1460 22:12:45.801961 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 22:12:45.808557 0 7 24 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1462 22:12:45.811632 0 7 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1463 22:12:45.815141 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 22:12:45.821709 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1465 22:12:45.825822 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1466 22:12:45.828512 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 22:12:45.834975 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 22:12:45.838391 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 22:12:45.842100 0 8 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1470 22:12:45.845201 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 22:12:45.852115 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 22:12:45.855162 0 9 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
1473 22:12:45.859002 0 9 8 | B1->B0 | 2626 2525 | 1 1 | (1 1) (1 1)
1474 22:12:45.865242 0 9 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1475 22:12:45.868282 0 9 16 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1476 22:12:45.872277 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1477 22:12:45.878398 0 9 24 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1478 22:12:45.881601 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1479 22:12:45.885330 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1480 22:12:45.891860 0 10 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 0)
1481 22:12:45.895258 0 10 8 | B1->B0 | 3030 2f2f | 1 0 | (1 0) (1 0)
1482 22:12:45.898223 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 22:12:45.905399 0 10 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1484 22:12:45.908832 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 22:12:45.911576 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 22:12:45.918546 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 22:12:45.921549 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 22:12:45.925688 0 11 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1489 22:12:45.931848 0 11 8 | B1->B0 | 3636 3333 | 1 1 | (0 0) (1 1)
1490 22:12:45.934764 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1491 22:12:45.938558 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1492 22:12:45.945011 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1493 22:12:45.948594 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1494 22:12:45.951454 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 22:12:45.955515 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 22:12:45.961927 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1497 22:12:45.964855 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1498 22:12:45.968011 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1499 22:12:45.975348 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 22:12:45.978385 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 22:12:45.981771 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 22:12:45.988106 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 22:12:45.991291 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 22:12:45.995054 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 22:12:46.002330 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 22:12:46.005294 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 22:12:46.008526 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 22:12:46.015097 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 22:12:46.018060 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 22:12:46.021691 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 22:12:46.028682 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 22:12:46.031768 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 22:12:46.034664 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1514 22:12:46.041458 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1515 22:12:46.041570 Total UI for P1: 0, mck2ui 16
1516 22:12:46.044667 best dqsien dly found for B0: ( 0, 14, 8)
1517 22:12:46.048282 Total UI for P1: 0, mck2ui 16
1518 22:12:46.051284 best dqsien dly found for B1: ( 0, 14, 10)
1519 22:12:46.058090 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1520 22:12:46.061638 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1521 22:12:46.061741
1522 22:12:46.064987 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1523 22:12:46.067950 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1524 22:12:46.071213 [Gating] SW calibration Done
1525 22:12:46.071304 ==
1526 22:12:46.074791 Dram Type= 6, Freq= 0, CH_1, rank 0
1527 22:12:46.078060 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1528 22:12:46.078152 ==
1529 22:12:46.078220 RX Vref Scan: 0
1530 22:12:46.081406
1531 22:12:46.081493 RX Vref 0 -> 0, step: 1
1532 22:12:46.081560
1533 22:12:46.084548 RX Delay -130 -> 252, step: 16
1534 22:12:46.088206 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1535 22:12:46.094543 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1536 22:12:46.098066 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1537 22:12:46.101189 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1538 22:12:46.104626 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1539 22:12:46.108531 iDelay=206, Bit 5, Center 85 (-34 ~ 205) 240
1540 22:12:46.111222 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1541 22:12:46.118092 iDelay=206, Bit 7, Center 69 (-50 ~ 189) 240
1542 22:12:46.121442 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
1543 22:12:46.124684 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1544 22:12:46.128251 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1545 22:12:46.131447 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1546 22:12:46.137651 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1547 22:12:46.141562 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1548 22:12:46.144590 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1549 22:12:46.148181 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1550 22:12:46.148271 ==
1551 22:12:46.151610 Dram Type= 6, Freq= 0, CH_1, rank 0
1552 22:12:46.158580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1553 22:12:46.158707 ==
1554 22:12:46.158807 DQS Delay:
1555 22:12:46.161331 DQS0 = 0, DQS1 = 0
1556 22:12:46.161410 DQM Delay:
1557 22:12:46.161474 DQM0 = 80, DQM1 = 75
1558 22:12:46.164776 DQ Delay:
1559 22:12:46.167801 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =85
1560 22:12:46.171249 DQ4 =85, DQ5 =85, DQ6 =93, DQ7 =69
1561 22:12:46.174406 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
1562 22:12:46.178000 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1563 22:12:46.178112
1564 22:12:46.178206
1565 22:12:46.178299 ==
1566 22:12:46.181055 Dram Type= 6, Freq= 0, CH_1, rank 0
1567 22:12:46.184971 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1568 22:12:46.185050 ==
1569 22:12:46.185118
1570 22:12:46.185208
1571 22:12:46.187754 TX Vref Scan disable
1572 22:12:46.187850 == TX Byte 0 ==
1573 22:12:46.194608 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1574 22:12:46.197979 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1575 22:12:46.198105 == TX Byte 1 ==
1576 22:12:46.204585 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1577 22:12:46.207946 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1578 22:12:46.208067 ==
1579 22:12:46.211048 Dram Type= 6, Freq= 0, CH_1, rank 0
1580 22:12:46.214633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1581 22:12:46.214743 ==
1582 22:12:46.228924 TX Vref=22, minBit 9, minWin=26, winSum=435
1583 22:12:46.232678 TX Vref=24, minBit 11, minWin=26, winSum=435
1584 22:12:46.235267 TX Vref=26, minBit 4, minWin=27, winSum=441
1585 22:12:46.238466 TX Vref=28, minBit 10, minWin=27, winSum=448
1586 22:12:46.242569 TX Vref=30, minBit 13, minWin=27, winSum=451
1587 22:12:46.246229 TX Vref=32, minBit 15, minWin=27, winSum=453
1588 22:12:46.252833 [TxChooseVref] Worse bit 15, Min win 27, Win sum 453, Final Vref 32
1589 22:12:46.252943
1590 22:12:46.255893 Final TX Range 1 Vref 32
1591 22:12:46.256022
1592 22:12:46.256114 ==
1593 22:12:46.259521 Dram Type= 6, Freq= 0, CH_1, rank 0
1594 22:12:46.263521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1595 22:12:46.263630 ==
1596 22:12:46.263744
1597 22:12:46.263806
1598 22:12:46.265926 TX Vref Scan disable
1599 22:12:46.268968 == TX Byte 0 ==
1600 22:12:46.272698 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1601 22:12:46.276513 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1602 22:12:46.279336 == TX Byte 1 ==
1603 22:12:46.282825 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1604 22:12:46.286359 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1605 22:12:46.286471
1606 22:12:46.289160 [DATLAT]
1607 22:12:46.289260 Freq=800, CH1 RK0
1608 22:12:46.289353
1609 22:12:46.293276 DATLAT Default: 0xa
1610 22:12:46.293382 0, 0xFFFF, sum = 0
1611 22:12:46.296398 1, 0xFFFF, sum = 0
1612 22:12:46.296478 2, 0xFFFF, sum = 0
1613 22:12:46.299881 3, 0xFFFF, sum = 0
1614 22:12:46.300008 4, 0xFFFF, sum = 0
1615 22:12:46.302467 5, 0xFFFF, sum = 0
1616 22:12:46.302567 6, 0xFFFF, sum = 0
1617 22:12:46.305982 7, 0xFFFF, sum = 0
1618 22:12:46.306084 8, 0xFFFF, sum = 0
1619 22:12:46.309098 9, 0x0, sum = 1
1620 22:12:46.309199 10, 0x0, sum = 2
1621 22:12:46.312354 11, 0x0, sum = 3
1622 22:12:46.312455 12, 0x0, sum = 4
1623 22:12:46.316185 best_step = 10
1624 22:12:46.316269
1625 22:12:46.316339 ==
1626 22:12:46.319548 Dram Type= 6, Freq= 0, CH_1, rank 0
1627 22:12:46.322501 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1628 22:12:46.322612 ==
1629 22:12:46.326072 RX Vref Scan: 1
1630 22:12:46.326147
1631 22:12:46.326209 Set Vref Range= 32 -> 127
1632 22:12:46.326286
1633 22:12:46.329608 RX Vref 32 -> 127, step: 1
1634 22:12:46.329713
1635 22:12:46.332701 RX Delay -111 -> 252, step: 8
1636 22:12:46.332796
1637 22:12:46.335901 Set Vref, RX VrefLevel [Byte0]: 32
1638 22:12:46.339248 [Byte1]: 32
1639 22:12:46.339351
1640 22:12:46.342505 Set Vref, RX VrefLevel [Byte0]: 33
1641 22:12:46.345844 [Byte1]: 33
1642 22:12:46.349863
1643 22:12:46.349967 Set Vref, RX VrefLevel [Byte0]: 34
1644 22:12:46.352717 [Byte1]: 34
1645 22:12:46.356949
1646 22:12:46.357043 Set Vref, RX VrefLevel [Byte0]: 35
1647 22:12:46.360645 [Byte1]: 35
1648 22:12:46.364635
1649 22:12:46.364746 Set Vref, RX VrefLevel [Byte0]: 36
1650 22:12:46.368077 [Byte1]: 36
1651 22:12:46.372191
1652 22:12:46.372270 Set Vref, RX VrefLevel [Byte0]: 37
1653 22:12:46.375895 [Byte1]: 37
1654 22:12:46.379759
1655 22:12:46.379873 Set Vref, RX VrefLevel [Byte0]: 38
1656 22:12:46.383625 [Byte1]: 38
1657 22:12:46.387836
1658 22:12:46.387928 Set Vref, RX VrefLevel [Byte0]: 39
1659 22:12:46.390755 [Byte1]: 39
1660 22:12:46.395381
1661 22:12:46.395486 Set Vref, RX VrefLevel [Byte0]: 40
1662 22:12:46.398822 [Byte1]: 40
1663 22:12:46.402777
1664 22:12:46.402888 Set Vref, RX VrefLevel [Byte0]: 41
1665 22:12:46.406666 [Byte1]: 41
1666 22:12:46.410471
1667 22:12:46.410560 Set Vref, RX VrefLevel [Byte0]: 42
1668 22:12:46.413857 [Byte1]: 42
1669 22:12:46.418069
1670 22:12:46.418156 Set Vref, RX VrefLevel [Byte0]: 43
1671 22:12:46.421749 [Byte1]: 43
1672 22:12:46.426279
1673 22:12:46.426377 Set Vref, RX VrefLevel [Byte0]: 44
1674 22:12:46.428890 [Byte1]: 44
1675 22:12:46.433476
1676 22:12:46.433570 Set Vref, RX VrefLevel [Byte0]: 45
1677 22:12:46.437195 [Byte1]: 45
1678 22:12:46.441370
1679 22:12:46.441461 Set Vref, RX VrefLevel [Byte0]: 46
1680 22:12:46.444949 [Byte1]: 46
1681 22:12:46.449561
1682 22:12:46.449652 Set Vref, RX VrefLevel [Byte0]: 47
1683 22:12:46.452104 [Byte1]: 47
1684 22:12:46.456252
1685 22:12:46.456340 Set Vref, RX VrefLevel [Byte0]: 48
1686 22:12:46.460378 [Byte1]: 48
1687 22:12:46.464025
1688 22:12:46.464114 Set Vref, RX VrefLevel [Byte0]: 49
1689 22:12:46.467423 [Byte1]: 49
1690 22:12:46.472251
1691 22:12:46.472361 Set Vref, RX VrefLevel [Byte0]: 50
1692 22:12:46.475230 [Byte1]: 50
1693 22:12:46.479203
1694 22:12:46.479292 Set Vref, RX VrefLevel [Byte0]: 51
1695 22:12:46.482768 [Byte1]: 51
1696 22:12:46.487146
1697 22:12:46.487241 Set Vref, RX VrefLevel [Byte0]: 52
1698 22:12:46.489985 [Byte1]: 52
1699 22:12:46.494601
1700 22:12:46.494735 Set Vref, RX VrefLevel [Byte0]: 53
1701 22:12:46.498082 [Byte1]: 53
1702 22:12:46.502937
1703 22:12:46.503035 Set Vref, RX VrefLevel [Byte0]: 54
1704 22:12:46.505616 [Byte1]: 54
1705 22:12:46.510076
1706 22:12:46.510168 Set Vref, RX VrefLevel [Byte0]: 55
1707 22:12:46.513229 [Byte1]: 55
1708 22:12:46.517711
1709 22:12:46.517807 Set Vref, RX VrefLevel [Byte0]: 56
1710 22:12:46.520870 [Byte1]: 56
1711 22:12:46.525303
1712 22:12:46.525397 Set Vref, RX VrefLevel [Byte0]: 57
1713 22:12:46.529002 [Byte1]: 57
1714 22:12:46.532689
1715 22:12:46.532854 Set Vref, RX VrefLevel [Byte0]: 58
1716 22:12:46.536392 [Byte1]: 58
1717 22:12:46.540445
1718 22:12:46.540534 Set Vref, RX VrefLevel [Byte0]: 59
1719 22:12:46.543597 [Byte1]: 59
1720 22:12:46.548151
1721 22:12:46.548278 Set Vref, RX VrefLevel [Byte0]: 60
1722 22:12:46.551517 [Byte1]: 60
1723 22:12:46.555799
1724 22:12:46.555924 Set Vref, RX VrefLevel [Byte0]: 61
1725 22:12:46.559414 [Byte1]: 61
1726 22:12:46.563616
1727 22:12:46.563696 Set Vref, RX VrefLevel [Byte0]: 62
1728 22:12:46.566978 [Byte1]: 62
1729 22:12:46.570803
1730 22:12:46.570890 Set Vref, RX VrefLevel [Byte0]: 63
1731 22:12:46.574173 [Byte1]: 63
1732 22:12:46.578911
1733 22:12:46.578988 Set Vref, RX VrefLevel [Byte0]: 64
1734 22:12:46.582142 [Byte1]: 64
1735 22:12:46.586465
1736 22:12:46.586550 Set Vref, RX VrefLevel [Byte0]: 65
1737 22:12:46.589507 [Byte1]: 65
1738 22:12:46.593929
1739 22:12:46.594034 Set Vref, RX VrefLevel [Byte0]: 66
1740 22:12:46.600247 [Byte1]: 66
1741 22:12:46.601459
1742 22:12:46.601582 Set Vref, RX VrefLevel [Byte0]: 67
1743 22:12:46.605155 [Byte1]: 67
1744 22:12:46.609138
1745 22:12:46.609218 Set Vref, RX VrefLevel [Byte0]: 68
1746 22:12:46.612697 [Byte1]: 68
1747 22:12:46.616952
1748 22:12:46.617045 Set Vref, RX VrefLevel [Byte0]: 69
1749 22:12:46.620508 [Byte1]: 69
1750 22:12:46.624441
1751 22:12:46.624535 Set Vref, RX VrefLevel [Byte0]: 70
1752 22:12:46.628809 [Byte1]: 70
1753 22:12:46.632137
1754 22:12:46.632226 Set Vref, RX VrefLevel [Byte0]: 71
1755 22:12:46.635658 [Byte1]: 71
1756 22:12:46.639863
1757 22:12:46.640020 Set Vref, RX VrefLevel [Byte0]: 72
1758 22:12:46.643803 [Byte1]: 72
1759 22:12:46.647867
1760 22:12:46.647979 Set Vref, RX VrefLevel [Byte0]: 73
1761 22:12:46.650914 [Byte1]: 73
1762 22:12:46.655357
1763 22:12:46.655445 Set Vref, RX VrefLevel [Byte0]: 74
1764 22:12:46.658406 [Byte1]: 74
1765 22:12:46.663310
1766 22:12:46.663398 Set Vref, RX VrefLevel [Byte0]: 75
1767 22:12:46.665954 [Byte1]: 75
1768 22:12:46.670839
1769 22:12:46.670928 Set Vref, RX VrefLevel [Byte0]: 76
1770 22:12:46.674190 [Byte1]: 76
1771 22:12:46.678223
1772 22:12:46.678318 Set Vref, RX VrefLevel [Byte0]: 77
1773 22:12:46.681387 [Byte1]: 77
1774 22:12:46.685676
1775 22:12:46.685766 Final RX Vref Byte 0 = 63 to rank0
1776 22:12:46.689416 Final RX Vref Byte 1 = 56 to rank0
1777 22:12:46.692653 Final RX Vref Byte 0 = 63 to rank1
1778 22:12:46.696109 Final RX Vref Byte 1 = 56 to rank1==
1779 22:12:46.699482 Dram Type= 6, Freq= 0, CH_1, rank 0
1780 22:12:46.706221 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1781 22:12:46.706334 ==
1782 22:12:46.706406 DQS Delay:
1783 22:12:46.709053 DQS0 = 0, DQS1 = 0
1784 22:12:46.709139 DQM Delay:
1785 22:12:46.709205 DQM0 = 83, DQM1 = 73
1786 22:12:46.712686 DQ Delay:
1787 22:12:46.715750 DQ0 =88, DQ1 =76, DQ2 =72, DQ3 =84
1788 22:12:46.719080 DQ4 =80, DQ5 =92, DQ6 =96, DQ7 =80
1789 22:12:46.722109 DQ8 =60, DQ9 =60, DQ10 =76, DQ11 =68
1790 22:12:46.725652 DQ12 =84, DQ13 =80, DQ14 =84, DQ15 =76
1791 22:12:46.725748
1792 22:12:46.725814
1793 22:12:46.732312 [DQSOSCAuto] RK0, (LSB)MR18= 0x25fa, (MSB)MR19= 0x605, tDQSOscB0 = 411 ps tDQSOscB1 = 400 ps
1794 22:12:46.735580 CH1 RK0: MR19=605, MR18=25FA
1795 22:12:46.742059 CH1_RK0: MR19=0x605, MR18=0x25FA, DQSOSC=400, MR23=63, INC=92, DEC=61
1796 22:12:46.742164
1797 22:12:46.745782 ----->DramcWriteLeveling(PI) begin...
1798 22:12:46.745874 ==
1799 22:12:46.749005 Dram Type= 6, Freq= 0, CH_1, rank 1
1800 22:12:46.752078 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1801 22:12:46.752171 ==
1802 22:12:46.755724 Write leveling (Byte 0): 28 => 28
1803 22:12:46.759411 Write leveling (Byte 1): 29 => 29
1804 22:12:46.761852 DramcWriteLeveling(PI) end<-----
1805 22:12:46.761939
1806 22:12:46.762008 ==
1807 22:12:46.766093 Dram Type= 6, Freq= 0, CH_1, rank 1
1808 22:12:46.768602 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1809 22:12:46.768688 ==
1810 22:12:46.772173 [Gating] SW mode calibration
1811 22:12:46.778746 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1812 22:12:46.785310 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1813 22:12:46.788731 0 6 0 | B1->B0 | 2423 2323 | 1 0 | (1 1) (1 1)
1814 22:12:46.792965 0 6 4 | B1->B0 | 2423 2323 | 1 0 | (1 1) (1 0)
1815 22:12:46.798881 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 22:12:46.801715 0 6 12 | B1->B0 | 2423 2323 | 1 0 | (0 0) (0 0)
1817 22:12:46.806227 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 22:12:46.812121 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 22:12:46.815798 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 22:12:46.818548 0 6 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1821 22:12:46.825474 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 22:12:46.828557 0 7 4 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1823 22:12:46.832217 0 7 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1824 22:12:46.838767 0 7 12 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1825 22:12:46.842041 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 22:12:46.845396 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 22:12:46.852056 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 22:12:46.855332 0 7 28 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1829 22:12:46.858792 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1830 22:12:46.865824 0 8 4 | B1->B0 | 2424 2323 | 0 0 | (0 1) (1 0)
1831 22:12:46.868688 0 8 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1832 22:12:46.871737 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 22:12:46.878405 0 8 16 | B1->B0 | 2322 2323 | 1 0 | (0 0) (0 0)
1834 22:12:46.881764 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 22:12:46.884897 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 22:12:46.891784 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 22:12:46.895252 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 22:12:46.898606 0 9 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
1839 22:12:46.901986 0 9 8 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
1840 22:12:46.908532 0 9 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1841 22:12:46.912025 0 9 16 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1842 22:12:46.915183 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1843 22:12:46.922068 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1844 22:12:46.925430 0 9 28 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1845 22:12:46.928694 0 10 0 | B1->B0 | 3534 3434 | 1 1 | (1 1) (1 1)
1846 22:12:46.934827 0 10 4 | B1->B0 | 3131 2c2c | 0 1 | (0 1) (1 0)
1847 22:12:46.938565 0 10 8 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
1848 22:12:46.941539 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1849 22:12:46.948556 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 22:12:46.951621 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 22:12:46.955209 0 10 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1852 22:12:46.961573 0 10 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1853 22:12:46.964839 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 22:12:46.968248 0 11 4 | B1->B0 | 2929 3030 | 0 0 | (0 0) (0 0)
1855 22:12:46.975082 0 11 8 | B1->B0 | 3f3f 4646 | 1 0 | (0 0) (0 0)
1856 22:12:46.977960 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1857 22:12:46.981693 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1858 22:12:46.988570 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1859 22:12:46.991657 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1860 22:12:46.994549 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1861 22:12:47.001276 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1862 22:12:47.004395 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1863 22:12:47.007879 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 22:12:47.014352 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 22:12:47.017699 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 22:12:47.021398 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 22:12:47.027817 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 22:12:47.031325 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 22:12:47.034281 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 22:12:47.041032 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 22:12:47.044248 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 22:12:47.047950 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 22:12:47.054604 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 22:12:47.057731 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 22:12:47.061039 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 22:12:47.064863 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 22:12:47.071153 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1878 22:12:47.074331 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1879 22:12:47.077997 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1880 22:12:47.080970 Total UI for P1: 0, mck2ui 16
1881 22:12:47.084527 best dqsien dly found for B0: ( 0, 14, 2)
1882 22:12:47.087392 Total UI for P1: 0, mck2ui 16
1883 22:12:47.091044 best dqsien dly found for B1: ( 0, 14, 4)
1884 22:12:47.094206 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1885 22:12:47.098289 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1886 22:12:47.100783
1887 22:12:47.104273 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1888 22:12:47.107745 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1889 22:12:47.110740 [Gating] SW calibration Done
1890 22:12:47.110844 ==
1891 22:12:47.115255 Dram Type= 6, Freq= 0, CH_1, rank 1
1892 22:12:47.117703 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1893 22:12:47.117808 ==
1894 22:12:47.117905 RX Vref Scan: 0
1895 22:12:47.117998
1896 22:12:47.120571 RX Vref 0 -> 0, step: 1
1897 22:12:47.120654
1898 22:12:47.124317 RX Delay -130 -> 252, step: 16
1899 22:12:47.127702 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1900 22:12:47.131245 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1901 22:12:47.137462 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1902 22:12:47.140714 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1903 22:12:47.144324 iDelay=206, Bit 4, Center 77 (-50 ~ 205) 256
1904 22:12:47.147490 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1905 22:12:47.151099 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1906 22:12:47.154547 iDelay=206, Bit 7, Center 69 (-50 ~ 189) 240
1907 22:12:47.161252 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
1908 22:12:47.164389 iDelay=206, Bit 9, Center 61 (-66 ~ 189) 256
1909 22:12:47.167413 iDelay=206, Bit 10, Center 77 (-50 ~ 205) 256
1910 22:12:47.170935 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1911 22:12:47.174693 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1912 22:12:47.180830 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1913 22:12:47.184234 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1914 22:12:47.187648 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1915 22:12:47.187738 ==
1916 22:12:47.191218 Dram Type= 6, Freq= 0, CH_1, rank 1
1917 22:12:47.194571 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1918 22:12:47.197759 ==
1919 22:12:47.197855 DQS Delay:
1920 22:12:47.197922 DQS0 = 0, DQS1 = 0
1921 22:12:47.201658 DQM Delay:
1922 22:12:47.201759 DQM0 = 79, DQM1 = 76
1923 22:12:47.204724 DQ Delay:
1924 22:12:47.204808 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =85
1925 22:12:47.207498 DQ4 =77, DQ5 =93, DQ6 =85, DQ7 =69
1926 22:12:47.210877 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =69
1927 22:12:47.214239 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1928 22:12:47.214327
1929 22:12:47.214393
1930 22:12:47.217460 ==
1931 22:12:47.221329 Dram Type= 6, Freq= 0, CH_1, rank 1
1932 22:12:47.224392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1933 22:12:47.224482 ==
1934 22:12:47.224576
1935 22:12:47.224637
1936 22:12:47.227663 TX Vref Scan disable
1937 22:12:47.227749 == TX Byte 0 ==
1938 22:12:47.234350 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1939 22:12:47.237947 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1940 22:12:47.238050 == TX Byte 1 ==
1941 22:12:47.244663 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1942 22:12:47.247708 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1943 22:12:47.247805 ==
1944 22:12:47.251283 Dram Type= 6, Freq= 0, CH_1, rank 1
1945 22:12:47.253985 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1946 22:12:47.254073 ==
1947 22:12:47.267346 TX Vref=22, minBit 10, minWin=26, winSum=440
1948 22:12:47.271070 TX Vref=24, minBit 11, minWin=27, winSum=446
1949 22:12:47.274209 TX Vref=26, minBit 11, minWin=27, winSum=449
1950 22:12:47.277917 TX Vref=28, minBit 2, minWin=28, winSum=454
1951 22:12:47.281307 TX Vref=30, minBit 1, minWin=28, winSum=454
1952 22:12:47.287685 TX Vref=32, minBit 11, minWin=27, winSum=455
1953 22:12:47.290765 [TxChooseVref] Worse bit 2, Min win 28, Win sum 454, Final Vref 28
1954 22:12:47.290895
1955 22:12:47.294211 Final TX Range 1 Vref 28
1956 22:12:47.294318
1957 22:12:47.294433 ==
1958 22:12:47.297558 Dram Type= 6, Freq= 0, CH_1, rank 1
1959 22:12:47.301141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1960 22:12:47.301263 ==
1961 22:12:47.304147
1962 22:12:47.304247
1963 22:12:47.304344 TX Vref Scan disable
1964 22:12:47.307975 == TX Byte 0 ==
1965 22:12:47.311164 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1966 22:12:47.314518 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1967 22:12:47.317649 == TX Byte 1 ==
1968 22:12:47.321240 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1969 22:12:47.324493 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1970 22:12:47.328257
1971 22:12:47.328363 [DATLAT]
1972 22:12:47.328461 Freq=800, CH1 RK1
1973 22:12:47.328554
1974 22:12:47.331556 DATLAT Default: 0xa
1975 22:12:47.331658 0, 0xFFFF, sum = 0
1976 22:12:47.335349 1, 0xFFFF, sum = 0
1977 22:12:47.335454 2, 0xFFFF, sum = 0
1978 22:12:47.338135 3, 0xFFFF, sum = 0
1979 22:12:47.338222 4, 0xFFFF, sum = 0
1980 22:12:47.341120 5, 0xFFFF, sum = 0
1981 22:12:47.341206 6, 0xFFFF, sum = 0
1982 22:12:47.344661 7, 0xFFFF, sum = 0
1983 22:12:47.348127 8, 0xFFFF, sum = 0
1984 22:12:47.348217 9, 0x0, sum = 1
1985 22:12:47.348285 10, 0x0, sum = 2
1986 22:12:47.351123 11, 0x0, sum = 3
1987 22:12:47.351210 12, 0x0, sum = 4
1988 22:12:47.354719 best_step = 10
1989 22:12:47.354805
1990 22:12:47.354872 ==
1991 22:12:47.357913 Dram Type= 6, Freq= 0, CH_1, rank 1
1992 22:12:47.361030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1993 22:12:47.361114 ==
1994 22:12:47.364846 RX Vref Scan: 0
1995 22:12:47.364924
1996 22:12:47.364990 RX Vref 0 -> 0, step: 1
1997 22:12:47.365051
1998 22:12:47.367566 RX Delay -111 -> 252, step: 8
1999 22:12:47.374440 iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232
2000 22:12:47.378102 iDelay=209, Bit 1, Center 76 (-39 ~ 192) 232
2001 22:12:47.380967 iDelay=209, Bit 2, Center 68 (-47 ~ 184) 232
2002 22:12:47.384360 iDelay=209, Bit 3, Center 76 (-39 ~ 192) 232
2003 22:12:47.388080 iDelay=209, Bit 4, Center 80 (-31 ~ 192) 224
2004 22:12:47.394267 iDelay=209, Bit 5, Center 88 (-23 ~ 200) 224
2005 22:12:47.397454 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
2006 22:12:47.401029 iDelay=209, Bit 7, Center 76 (-39 ~ 192) 232
2007 22:12:47.404377 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
2008 22:12:47.407992 iDelay=209, Bit 9, Center 60 (-55 ~ 176) 232
2009 22:12:47.414431 iDelay=209, Bit 10, Center 76 (-39 ~ 192) 232
2010 22:12:47.417764 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
2011 22:12:47.420693 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
2012 22:12:47.424348 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
2013 22:12:47.430880 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
2014 22:12:47.434574 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
2015 22:12:47.434704 ==
2016 22:12:47.437464 Dram Type= 6, Freq= 0, CH_1, rank 1
2017 22:12:47.441434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2018 22:12:47.441630 ==
2019 22:12:47.441758 DQS Delay:
2020 22:12:47.444063 DQS0 = 0, DQS1 = 0
2021 22:12:47.444180 DQM Delay:
2022 22:12:47.447930 DQM0 = 80, DQM1 = 74
2023 22:12:47.448070 DQ Delay:
2024 22:12:47.451330 DQ0 =84, DQ1 =76, DQ2 =68, DQ3 =76
2025 22:12:47.454033 DQ4 =80, DQ5 =88, DQ6 =92, DQ7 =76
2026 22:12:47.457492 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =68
2027 22:12:47.460652 DQ12 =80, DQ13 =80, DQ14 =80, DQ15 =84
2028 22:12:47.460770
2029 22:12:47.460849
2030 22:12:47.471348 [DQSOSCAuto] RK1, (LSB)MR18= 0x232e, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 401 ps
2031 22:12:47.471507 CH1 RK1: MR19=606, MR18=232E
2032 22:12:47.477464 CH1_RK1: MR19=0x606, MR18=0x232E, DQSOSC=398, MR23=63, INC=93, DEC=62
2033 22:12:47.480723 [RxdqsGatingPostProcess] freq 800
2034 22:12:47.487764 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2035 22:12:47.490895 Pre-setting of DQS Precalculation
2036 22:12:47.494167 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2037 22:12:47.500597 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2038 22:12:47.507633 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2039 22:12:47.510668
2040 22:12:47.510794
2041 22:12:47.510888 [Calibration Summary] 1600 Mbps
2042 22:12:47.514246 CH 0, Rank 0
2043 22:12:47.514344 SW Impedance : PASS
2044 22:12:47.518011 DUTY Scan : NO K
2045 22:12:47.520919 ZQ Calibration : PASS
2046 22:12:47.520997 Jitter Meter : NO K
2047 22:12:47.524165 CBT Training : PASS
2048 22:12:47.527817 Write leveling : PASS
2049 22:12:47.527964 RX DQS gating : PASS
2050 22:12:47.530963 RX DQ/DQS(RDDQC) : PASS
2051 22:12:47.534177 TX DQ/DQS : PASS
2052 22:12:47.534291 RX DATLAT : PASS
2053 22:12:47.537125 RX DQ/DQS(Engine): PASS
2054 22:12:47.540765 TX OE : NO K
2055 22:12:47.540845 All Pass.
2056 22:12:47.540909
2057 22:12:47.540987 CH 0, Rank 1
2058 22:12:47.544451 SW Impedance : PASS
2059 22:12:47.547343 DUTY Scan : NO K
2060 22:12:47.547457 ZQ Calibration : PASS
2061 22:12:47.550592 Jitter Meter : NO K
2062 22:12:47.550694 CBT Training : PASS
2063 22:12:47.554310 Write leveling : PASS
2064 22:12:47.557576 RX DQS gating : PASS
2065 22:12:47.557658 RX DQ/DQS(RDDQC) : PASS
2066 22:12:47.560726 TX DQ/DQS : PASS
2067 22:12:47.564286 RX DATLAT : PASS
2068 22:12:47.564398 RX DQ/DQS(Engine): PASS
2069 22:12:47.567608 TX OE : NO K
2070 22:12:47.567714 All Pass.
2071 22:12:47.567815
2072 22:12:47.570386 CH 1, Rank 0
2073 22:12:47.570489 SW Impedance : PASS
2074 22:12:47.574369 DUTY Scan : NO K
2075 22:12:47.577108 ZQ Calibration : PASS
2076 22:12:47.577219 Jitter Meter : NO K
2077 22:12:47.580804 CBT Training : PASS
2078 22:12:47.584350 Write leveling : PASS
2079 22:12:47.584466 RX DQS gating : PASS
2080 22:12:47.587493 RX DQ/DQS(RDDQC) : PASS
2081 22:12:47.590549 TX DQ/DQS : PASS
2082 22:12:47.590656 RX DATLAT : PASS
2083 22:12:47.594525 RX DQ/DQS(Engine): PASS
2084 22:12:47.597363 TX OE : NO K
2085 22:12:47.597479 All Pass.
2086 22:12:47.597573
2087 22:12:47.597663 CH 1, Rank 1
2088 22:12:47.600431 SW Impedance : PASS
2089 22:12:47.600508 DUTY Scan : NO K
2090 22:12:47.603878 ZQ Calibration : PASS
2091 22:12:47.607264 Jitter Meter : NO K
2092 22:12:47.607379 CBT Training : PASS
2093 22:12:47.610673 Write leveling : PASS
2094 22:12:47.614009 RX DQS gating : PASS
2095 22:12:47.614129 RX DQ/DQS(RDDQC) : PASS
2096 22:12:47.617316 TX DQ/DQS : PASS
2097 22:12:47.620328 RX DATLAT : PASS
2098 22:12:47.620415 RX DQ/DQS(Engine): PASS
2099 22:12:47.624036 TX OE : NO K
2100 22:12:47.624156 All Pass.
2101 22:12:47.624239
2102 22:12:47.628091 DramC Write-DBI off
2103 22:12:47.630570 PER_BANK_REFRESH: Hybrid Mode
2104 22:12:47.630695 TX_TRACKING: ON
2105 22:12:47.633712 [GetDramInforAfterCalByMRR] Vendor 6.
2106 22:12:47.637300 [GetDramInforAfterCalByMRR] Revision 606.
2107 22:12:47.640506 [GetDramInforAfterCalByMRR] Revision 2 0.
2108 22:12:47.643936 MR0 0x3b3b
2109 22:12:47.644087 MR8 0x5151
2110 22:12:47.647680 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2111 22:12:47.647771
2112 22:12:47.647840 MR0 0x3b3b
2113 22:12:47.650702 MR8 0x5151
2114 22:12:47.653922 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2115 22:12:47.654029
2116 22:12:47.663897 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2117 22:12:47.667378 [FAST_K] Save calibration result to emmc
2118 22:12:47.670719 [FAST_K] Save calibration result to emmc
2119 22:12:47.670819 dram_init: config_dvfs: 1
2120 22:12:47.677606 dramc_set_vcore_voltage set vcore to 662500
2121 22:12:47.677740 Read voltage for 1200, 2
2122 22:12:47.677848 Vio18 = 0
2123 22:12:47.681196 Vcore = 662500
2124 22:12:47.681281 Vdram = 0
2125 22:12:47.681348 Vddq = 0
2126 22:12:47.684714 Vmddr = 0
2127 22:12:47.687607 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2128 22:12:47.694241 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2129 22:12:47.694384 MEM_TYPE=3, freq_sel=15
2130 22:12:47.697609 sv_algorithm_assistance_LP4_1600
2131 22:12:47.704301 ============ PULL DRAM RESETB DOWN ============
2132 22:12:47.708028 ========== PULL DRAM RESETB DOWN end =========
2133 22:12:47.710850 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2134 22:12:47.713983 ===================================
2135 22:12:47.717826 LPDDR4 DRAM CONFIGURATION
2136 22:12:47.720976 ===================================
2137 22:12:47.724317 EX_ROW_EN[0] = 0x0
2138 22:12:47.724413 EX_ROW_EN[1] = 0x0
2139 22:12:47.727263 LP4Y_EN = 0x0
2140 22:12:47.727351 WORK_FSP = 0x0
2141 22:12:47.730773 WL = 0x4
2142 22:12:47.730891 RL = 0x4
2143 22:12:47.734335 BL = 0x2
2144 22:12:47.734464 RPST = 0x0
2145 22:12:47.737510 RD_PRE = 0x0
2146 22:12:47.737616 WR_PRE = 0x1
2147 22:12:47.741353 WR_PST = 0x0
2148 22:12:47.741452 DBI_WR = 0x0
2149 22:12:47.744661 DBI_RD = 0x0
2150 22:12:47.744753 OTF = 0x1
2151 22:12:47.747470 ===================================
2152 22:12:47.750923 ===================================
2153 22:12:47.754295 ANA top config
2154 22:12:47.757815 ===================================
2155 22:12:47.761280 DLL_ASYNC_EN = 0
2156 22:12:47.761389 ALL_SLAVE_EN = 0
2157 22:12:47.764060 NEW_RANK_MODE = 1
2158 22:12:47.767767 DLL_IDLE_MODE = 1
2159 22:12:47.770735 LP45_APHY_COMB_EN = 1
2160 22:12:47.770836 TX_ODT_DIS = 1
2161 22:12:47.774415 NEW_8X_MODE = 1
2162 22:12:47.777394 ===================================
2163 22:12:47.781087 ===================================
2164 22:12:47.783947 data_rate = 2400
2165 22:12:47.787839 CKR = 1
2166 22:12:47.790933 DQ_P2S_RATIO = 8
2167 22:12:47.793833 ===================================
2168 22:12:47.798314 CA_P2S_RATIO = 8
2169 22:12:47.798460 DQ_CA_OPEN = 0
2170 22:12:47.800900 DQ_SEMI_OPEN = 0
2171 22:12:47.804323 CA_SEMI_OPEN = 0
2172 22:12:47.807450 CA_FULL_RATE = 0
2173 22:12:47.810974 DQ_CKDIV4_EN = 0
2174 22:12:47.811085 CA_CKDIV4_EN = 0
2175 22:12:47.814308 CA_PREDIV_EN = 0
2176 22:12:47.817226 PH8_DLY = 17
2177 22:12:47.820792 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2178 22:12:47.823822 DQ_AAMCK_DIV = 4
2179 22:12:47.827506 CA_AAMCK_DIV = 4
2180 22:12:47.827604 CA_ADMCK_DIV = 4
2181 22:12:47.830568 DQ_TRACK_CA_EN = 0
2182 22:12:47.833905 CA_PICK = 1200
2183 22:12:47.837569 CA_MCKIO = 1200
2184 22:12:47.840414 MCKIO_SEMI = 0
2185 22:12:47.844290 PLL_FREQ = 2366
2186 22:12:47.847349 DQ_UI_PI_RATIO = 32
2187 22:12:47.850545 CA_UI_PI_RATIO = 0
2188 22:12:47.854073 ===================================
2189 22:12:47.857493 ===================================
2190 22:12:47.857588 memory_type:LPDDR4
2191 22:12:47.860590 GP_NUM : 10
2192 22:12:47.860677 SRAM_EN : 1
2193 22:12:47.863912 MD32_EN : 0
2194 22:12:47.867635 ===================================
2195 22:12:47.870428 [ANA_INIT] >>>>>>>>>>>>>>
2196 22:12:47.873878 <<<<<< [CONFIGURE PHASE]: ANA_TX
2197 22:12:47.877571 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2198 22:12:47.880873 ===================================
2199 22:12:47.880971 data_rate = 2400,PCW = 0X5b00
2200 22:12:47.884340 ===================================
2201 22:12:47.887356 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2202 22:12:47.893929 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2203 22:12:47.900430 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2204 22:12:47.903880 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2205 22:12:47.907341 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2206 22:12:47.910525 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2207 22:12:47.914350 [ANA_INIT] flow start
2208 22:12:47.917156 [ANA_INIT] PLL >>>>>>>>
2209 22:12:47.917252 [ANA_INIT] PLL <<<<<<<<
2210 22:12:47.920404 [ANA_INIT] MIDPI >>>>>>>>
2211 22:12:47.923915 [ANA_INIT] MIDPI <<<<<<<<
2212 22:12:47.924036 [ANA_INIT] DLL >>>>>>>>
2213 22:12:47.927329 [ANA_INIT] DLL <<<<<<<<
2214 22:12:47.930592 [ANA_INIT] flow end
2215 22:12:47.933889 ============ LP4 DIFF to SE enter ============
2216 22:12:47.937271 ============ LP4 DIFF to SE exit ============
2217 22:12:47.940533 [ANA_INIT] <<<<<<<<<<<<<
2218 22:12:47.944229 [Flow] Enable top DCM control >>>>>
2219 22:12:47.946961 [Flow] Enable top DCM control <<<<<
2220 22:12:47.950598 Enable DLL master slave shuffle
2221 22:12:47.953764 ==============================================================
2222 22:12:47.957294 Gating Mode config
2223 22:12:47.963778 ==============================================================
2224 22:12:47.963926 Config description:
2225 22:12:47.974259 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2226 22:12:47.980631 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2227 22:12:47.983474 SELPH_MODE 0: By rank 1: By Phase
2228 22:12:47.990235 ==============================================================
2229 22:12:47.994080 GAT_TRACK_EN = 1
2230 22:12:47.997598 RX_GATING_MODE = 2
2231 22:12:48.000609 RX_GATING_TRACK_MODE = 2
2232 22:12:48.003502 SELPH_MODE = 1
2233 22:12:48.007126 PICG_EARLY_EN = 1
2234 22:12:48.007271 VALID_LAT_VALUE = 1
2235 22:12:48.013767 ==============================================================
2236 22:12:48.017144 Enter into Gating configuration >>>>
2237 22:12:48.020335 Exit from Gating configuration <<<<
2238 22:12:48.023709 Enter into DVFS_PRE_config >>>>>
2239 22:12:48.033832 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2240 22:12:48.037086 Exit from DVFS_PRE_config <<<<<
2241 22:12:48.040051 Enter into PICG configuration >>>>
2242 22:12:48.043494 Exit from PICG configuration <<<<
2243 22:12:48.046905 [RX_INPUT] configuration >>>>>
2244 22:12:48.050645 [RX_INPUT] configuration <<<<<
2245 22:12:48.053386 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2246 22:12:48.060495 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2247 22:12:48.066946 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2248 22:12:48.074169 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2249 22:12:48.080253 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2250 22:12:48.087165 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2251 22:12:48.090526 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2252 22:12:48.094004 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2253 22:12:48.097655 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2254 22:12:48.100486 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2255 22:12:48.106847 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2256 22:12:48.110380 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2257 22:12:48.114290 ===================================
2258 22:12:48.117059 LPDDR4 DRAM CONFIGURATION
2259 22:12:48.120309 ===================================
2260 22:12:48.120400 EX_ROW_EN[0] = 0x0
2261 22:12:48.123619 EX_ROW_EN[1] = 0x0
2262 22:12:48.123724 LP4Y_EN = 0x0
2263 22:12:48.126950 WORK_FSP = 0x0
2264 22:12:48.127053 WL = 0x4
2265 22:12:48.130352 RL = 0x4
2266 22:12:48.130456 BL = 0x2
2267 22:12:48.133694 RPST = 0x0
2268 22:12:48.133797 RD_PRE = 0x0
2269 22:12:48.136727 WR_PRE = 0x1
2270 22:12:48.140490 WR_PST = 0x0
2271 22:12:48.140569 DBI_WR = 0x0
2272 22:12:48.143745 DBI_RD = 0x0
2273 22:12:48.143846 OTF = 0x1
2274 22:12:48.147063 ===================================
2275 22:12:48.150381 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2276 22:12:48.153397 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2277 22:12:48.160428 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2278 22:12:48.163483 ===================================
2279 22:12:48.167132 LPDDR4 DRAM CONFIGURATION
2280 22:12:48.169823 ===================================
2281 22:12:48.169904 EX_ROW_EN[0] = 0x10
2282 22:12:48.173972 EX_ROW_EN[1] = 0x0
2283 22:12:48.174082 LP4Y_EN = 0x0
2284 22:12:48.176780 WORK_FSP = 0x0
2285 22:12:48.176858 WL = 0x4
2286 22:12:48.180392 RL = 0x4
2287 22:12:48.180470 BL = 0x2
2288 22:12:48.183142 RPST = 0x0
2289 22:12:48.183242 RD_PRE = 0x0
2290 22:12:48.186895 WR_PRE = 0x1
2291 22:12:48.186974 WR_PST = 0x0
2292 22:12:48.190277 DBI_WR = 0x0
2293 22:12:48.190355 DBI_RD = 0x0
2294 22:12:48.193756 OTF = 0x1
2295 22:12:48.196762 ===================================
2296 22:12:48.203458 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2297 22:12:48.203580 ==
2298 22:12:48.206416 Dram Type= 6, Freq= 0, CH_0, rank 0
2299 22:12:48.209788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2300 22:12:48.209900 ==
2301 22:12:48.213477 [Duty_Offset_Calibration]
2302 22:12:48.213585 B0:2 B1:-1 CA:1
2303 22:12:48.213680
2304 22:12:48.216487 [DutyScan_Calibration_Flow] k_type=0
2305 22:12:48.226698
2306 22:12:48.226839 ==CLK 0==
2307 22:12:48.229858 Final CLK duty delay cell = -4
2308 22:12:48.233118 [-4] MAX Duty = 5031%(X100), DQS PI = 4
2309 22:12:48.236661 [-4] MIN Duty = 4875%(X100), DQS PI = 32
2310 22:12:48.239810 [-4] AVG Duty = 4953%(X100)
2311 22:12:48.239899
2312 22:12:48.243385 CH0 CLK Duty spec in!! Max-Min= 156%
2313 22:12:48.246555 [DutyScan_Calibration_Flow] ====Done====
2314 22:12:48.246658
2315 22:12:48.250175 [DutyScan_Calibration_Flow] k_type=1
2316 22:12:48.265402
2317 22:12:48.265539 ==DQS 0 ==
2318 22:12:48.268581 Final DQS duty delay cell = 0
2319 22:12:48.272138 [0] MAX Duty = 5125%(X100), DQS PI = 48
2320 22:12:48.275413 [0] MIN Duty = 5000%(X100), DQS PI = 12
2321 22:12:48.278555 [0] AVG Duty = 5062%(X100)
2322 22:12:48.278640
2323 22:12:48.278702 ==DQS 1 ==
2324 22:12:48.282271 Final DQS duty delay cell = -4
2325 22:12:48.285552 [-4] MAX Duty = 5124%(X100), DQS PI = 6
2326 22:12:48.288676 [-4] MIN Duty = 5000%(X100), DQS PI = 50
2327 22:12:48.291827 [-4] AVG Duty = 5062%(X100)
2328 22:12:48.291933
2329 22:12:48.295625 CH0 DQS 0 Duty spec in!! Max-Min= 125%
2330 22:12:48.295736
2331 22:12:48.298639 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2332 22:12:48.301699 [DutyScan_Calibration_Flow] ====Done====
2333 22:12:48.301808
2334 22:12:48.305537 [DutyScan_Calibration_Flow] k_type=3
2335 22:12:48.322451
2336 22:12:48.322630 ==DQM 0 ==
2337 22:12:48.325629 Final DQM duty delay cell = 0
2338 22:12:48.328713 [0] MAX Duty = 5000%(X100), DQS PI = 54
2339 22:12:48.332330 [0] MIN Duty = 4907%(X100), DQS PI = 2
2340 22:12:48.332441 [0] AVG Duty = 4953%(X100)
2341 22:12:48.335781
2342 22:12:48.335863 ==DQM 1 ==
2343 22:12:48.338671 Final DQM duty delay cell = 0
2344 22:12:48.341969 [0] MAX Duty = 5124%(X100), DQS PI = 32
2345 22:12:48.345437 [0] MIN Duty = 4969%(X100), DQS PI = 10
2346 22:12:48.345520 [0] AVG Duty = 5046%(X100)
2347 22:12:48.349522
2348 22:12:48.352414 CH0 DQM 0 Duty spec in!! Max-Min= 93%
2349 22:12:48.352490
2350 22:12:48.355657 CH0 DQM 1 Duty spec in!! Max-Min= 155%
2351 22:12:48.359193 [DutyScan_Calibration_Flow] ====Done====
2352 22:12:48.359268
2353 22:12:48.362829 [DutyScan_Calibration_Flow] k_type=2
2354 22:12:48.378247
2355 22:12:48.378383 ==DQ 0 ==
2356 22:12:48.381484 Final DQ duty delay cell = -4
2357 22:12:48.384689 [-4] MAX Duty = 5062%(X100), DQS PI = 54
2358 22:12:48.388296 [-4] MIN Duty = 4907%(X100), DQS PI = 10
2359 22:12:48.391523 [-4] AVG Duty = 4984%(X100)
2360 22:12:48.391630
2361 22:12:48.391719 ==DQ 1 ==
2362 22:12:48.394632 Final DQ duty delay cell = 0
2363 22:12:48.398205 [0] MAX Duty = 5031%(X100), DQS PI = 18
2364 22:12:48.401125 [0] MIN Duty = 4907%(X100), DQS PI = 46
2365 22:12:48.401210 [0] AVG Duty = 4969%(X100)
2366 22:12:48.404587
2367 22:12:48.408305 CH0 DQ 0 Duty spec in!! Max-Min= 155%
2368 22:12:48.408387
2369 22:12:48.412107 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2370 22:12:48.414542 [DutyScan_Calibration_Flow] ====Done====
2371 22:12:48.414642 ==
2372 22:12:48.417850 Dram Type= 6, Freq= 0, CH_1, rank 0
2373 22:12:48.421398 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2374 22:12:48.421484 ==
2375 22:12:48.424475 [Duty_Offset_Calibration]
2376 22:12:48.424552 B0:1 B1:1 CA:2
2377 22:12:48.424614
2378 22:12:48.427741 [DutyScan_Calibration_Flow] k_type=0
2379 22:12:48.438191
2380 22:12:48.438346 ==CLK 0==
2381 22:12:48.441453 Final CLK duty delay cell = 0
2382 22:12:48.445293 [0] MAX Duty = 5125%(X100), DQS PI = 24
2383 22:12:48.448606 [0] MIN Duty = 4969%(X100), DQS PI = 40
2384 22:12:48.448696 [0] AVG Duty = 5047%(X100)
2385 22:12:48.451325
2386 22:12:48.454600 CH1 CLK Duty spec in!! Max-Min= 156%
2387 22:12:48.458536 [DutyScan_Calibration_Flow] ====Done====
2388 22:12:48.458640
2389 22:12:48.461286 [DutyScan_Calibration_Flow] k_type=1
2390 22:12:48.477508
2391 22:12:48.477670 ==DQS 0 ==
2392 22:12:48.481006 Final DQS duty delay cell = 0
2393 22:12:48.484060 [0] MAX Duty = 5031%(X100), DQS PI = 18
2394 22:12:48.487834 [0] MIN Duty = 4844%(X100), DQS PI = 50
2395 22:12:48.487938 [0] AVG Duty = 4937%(X100)
2396 22:12:48.490898
2397 22:12:48.490995 ==DQS 1 ==
2398 22:12:48.494139 Final DQS duty delay cell = 0
2399 22:12:48.497484 [0] MAX Duty = 5062%(X100), DQS PI = 36
2400 22:12:48.500786 [0] MIN Duty = 4907%(X100), DQS PI = 2
2401 22:12:48.500868 [0] AVG Duty = 4984%(X100)
2402 22:12:48.504633
2403 22:12:48.507520 CH1 DQS 0 Duty spec in!! Max-Min= 187%
2404 22:12:48.507591
2405 22:12:48.511319 CH1 DQS 1 Duty spec in!! Max-Min= 155%
2406 22:12:48.513956 [DutyScan_Calibration_Flow] ====Done====
2407 22:12:48.514034
2408 22:12:48.517899 [DutyScan_Calibration_Flow] k_type=3
2409 22:12:48.533803
2410 22:12:48.533945 ==DQM 0 ==
2411 22:12:48.537393 Final DQM duty delay cell = 0
2412 22:12:48.540966 [0] MAX Duty = 5093%(X100), DQS PI = 18
2413 22:12:48.544145 [0] MIN Duty = 4907%(X100), DQS PI = 48
2414 22:12:48.547213 [0] AVG Duty = 5000%(X100)
2415 22:12:48.547298
2416 22:12:48.547394 ==DQM 1 ==
2417 22:12:48.550391 Final DQM duty delay cell = 0
2418 22:12:48.553709 [0] MAX Duty = 5156%(X100), DQS PI = 60
2419 22:12:48.557249 [0] MIN Duty = 4938%(X100), DQS PI = 22
2420 22:12:48.560750 [0] AVG Duty = 5047%(X100)
2421 22:12:48.560828
2422 22:12:48.563877 CH1 DQM 0 Duty spec in!! Max-Min= 186%
2423 22:12:48.564010
2424 22:12:48.567285 CH1 DQM 1 Duty spec in!! Max-Min= 218%
2425 22:12:48.570940 [DutyScan_Calibration_Flow] ====Done====
2426 22:12:48.571039
2427 22:12:48.573578 [DutyScan_Calibration_Flow] k_type=2
2428 22:12:48.590608
2429 22:12:48.590769 ==DQ 0 ==
2430 22:12:48.593794 Final DQ duty delay cell = 0
2431 22:12:48.598121 [0] MAX Duty = 5093%(X100), DQS PI = 18
2432 22:12:48.601242 [0] MIN Duty = 4969%(X100), DQS PI = 14
2433 22:12:48.601329 [0] AVG Duty = 5031%(X100)
2434 22:12:48.601420
2435 22:12:48.603868 ==DQ 1 ==
2436 22:12:48.607361 Final DQ duty delay cell = 0
2437 22:12:48.610719 [0] MAX Duty = 5093%(X100), DQS PI = 10
2438 22:12:48.614022 [0] MIN Duty = 5031%(X100), DQS PI = 2
2439 22:12:48.614127 [0] AVG Duty = 5062%(X100)
2440 22:12:48.614217
2441 22:12:48.617851 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2442 22:12:48.617951
2443 22:12:48.620720 CH1 DQ 1 Duty spec in!! Max-Min= 62%
2444 22:12:48.627228 [DutyScan_Calibration_Flow] ====Done====
2445 22:12:48.630642 nWR fixed to 30
2446 22:12:48.630756 [ModeRegInit_LP4] CH0 RK0
2447 22:12:48.634143 [ModeRegInit_LP4] CH0 RK1
2448 22:12:48.637501 [ModeRegInit_LP4] CH1 RK0
2449 22:12:48.637592 [ModeRegInit_LP4] CH1 RK1
2450 22:12:48.640607 match AC timing 7
2451 22:12:48.644220 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2452 22:12:48.647523 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2453 22:12:48.654110 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2454 22:12:48.657272 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2455 22:12:48.663939 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2456 22:12:48.664078 ==
2457 22:12:48.667381 Dram Type= 6, Freq= 0, CH_0, rank 0
2458 22:12:48.671015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2459 22:12:48.671106 ==
2460 22:12:48.677182 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2461 22:12:48.680317 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2462 22:12:48.690581 [CA 0] Center 40 (10~71) winsize 62
2463 22:12:48.694298 [CA 1] Center 39 (9~70) winsize 62
2464 22:12:48.697080 [CA 2] Center 36 (6~67) winsize 62
2465 22:12:48.700564 [CA 3] Center 36 (6~66) winsize 61
2466 22:12:48.703621 [CA 4] Center 34 (4~65) winsize 62
2467 22:12:48.707084 [CA 5] Center 34 (4~64) winsize 61
2468 22:12:48.707173
2469 22:12:48.710321 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2470 22:12:48.710411
2471 22:12:48.713535 [CATrainingPosCal] consider 1 rank data
2472 22:12:48.717011 u2DelayCellTimex100 = 270/100 ps
2473 22:12:48.720786 CA0 delay=40 (10~71),Diff = 6 PI (28 cell)
2474 22:12:48.727229 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2475 22:12:48.731079 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2476 22:12:48.733723 CA3 delay=36 (6~66),Diff = 2 PI (9 cell)
2477 22:12:48.737095 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
2478 22:12:48.740239 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2479 22:12:48.740332
2480 22:12:48.743561 CA PerBit enable=1, Macro0, CA PI delay=34
2481 22:12:48.743648
2482 22:12:48.746944 [CBTSetCACLKResult] CA Dly = 34
2483 22:12:48.747032 CS Dly: 7 (0~38)
2484 22:12:48.750841 ==
2485 22:12:48.753897 Dram Type= 6, Freq= 0, CH_0, rank 1
2486 22:12:48.757160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2487 22:12:48.757271 ==
2488 22:12:48.760700 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2489 22:12:48.767396 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2490 22:12:48.776739 [CA 0] Center 39 (9~70) winsize 62
2491 22:12:48.780071 [CA 1] Center 39 (9~70) winsize 62
2492 22:12:48.783205 [CA 2] Center 36 (6~67) winsize 62
2493 22:12:48.786551 [CA 3] Center 36 (5~67) winsize 63
2494 22:12:48.790029 [CA 4] Center 34 (4~65) winsize 62
2495 22:12:48.792937 [CA 5] Center 34 (4~64) winsize 61
2496 22:12:48.793027
2497 22:12:48.796780 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2498 22:12:48.796876
2499 22:12:48.800178 [CATrainingPosCal] consider 2 rank data
2500 22:12:48.803676 u2DelayCellTimex100 = 270/100 ps
2501 22:12:48.806127 CA0 delay=40 (10~70),Diff = 6 PI (28 cell)
2502 22:12:48.810034 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2503 22:12:48.816151 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2504 22:12:48.820071 CA3 delay=36 (6~66),Diff = 2 PI (9 cell)
2505 22:12:48.822760 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
2506 22:12:48.826150 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2507 22:12:48.826244
2508 22:12:48.829717 CA PerBit enable=1, Macro0, CA PI delay=34
2509 22:12:48.829807
2510 22:12:48.832860 [CBTSetCACLKResult] CA Dly = 34
2511 22:12:48.832949 CS Dly: 8 (0~41)
2512 22:12:48.833035
2513 22:12:48.836734 ----->DramcWriteLeveling(PI) begin...
2514 22:12:48.840354 ==
2515 22:12:48.843445 Dram Type= 6, Freq= 0, CH_0, rank 0
2516 22:12:48.846640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2517 22:12:48.846731 ==
2518 22:12:48.850186 Write leveling (Byte 0): 31 => 31
2519 22:12:48.853215 Write leveling (Byte 1): 29 => 29
2520 22:12:48.856514 DramcWriteLeveling(PI) end<-----
2521 22:12:48.856603
2522 22:12:48.856688 ==
2523 22:12:48.859526 Dram Type= 6, Freq= 0, CH_0, rank 0
2524 22:12:48.863542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2525 22:12:48.863632 ==
2526 22:12:48.866656 [Gating] SW mode calibration
2527 22:12:48.873414 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2528 22:12:48.876415 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2529 22:12:48.883371 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2530 22:12:48.886608 0 15 4 | B1->B0 | 2423 3232 | 1 0 | (0 0) (0 0)
2531 22:12:48.890084 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2532 22:12:48.896189 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2533 22:12:48.900170 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2534 22:12:48.903179 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2535 22:12:48.910130 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2536 22:12:48.913479 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2537 22:12:48.916552 1 0 0 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
2538 22:12:48.923251 1 0 4 | B1->B0 | 2b2b 2323 | 0 0 | (1 0) (0 0)
2539 22:12:48.926687 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2540 22:12:48.930414 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2541 22:12:48.936388 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2542 22:12:48.939756 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2543 22:12:48.943726 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2544 22:12:48.950280 1 0 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2545 22:12:48.953545 1 1 0 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
2546 22:12:48.956396 1 1 4 | B1->B0 | 3e3e 4545 | 0 0 | (1 1) (0 0)
2547 22:12:48.963350 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2548 22:12:48.966136 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2549 22:12:48.969711 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2550 22:12:48.972856 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2551 22:12:48.979601 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2552 22:12:48.982959 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2553 22:12:48.986494 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2554 22:12:48.993077 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2555 22:12:48.996591 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 22:12:48.999576 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 22:12:49.006798 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 22:12:49.010340 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 22:12:49.013566 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 22:12:49.019596 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 22:12:49.023230 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 22:12:49.026396 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 22:12:49.033039 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 22:12:49.036825 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 22:12:49.039824 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 22:12:49.047245 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 22:12:49.049482 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 22:12:49.053284 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 22:12:49.059700 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2570 22:12:49.062958 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2571 22:12:49.066989 Total UI for P1: 0, mck2ui 16
2572 22:12:49.069894 best dqsien dly found for B0: ( 1, 4, 0)
2573 22:12:49.073485 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2574 22:12:49.076783 Total UI for P1: 0, mck2ui 16
2575 22:12:49.079668 best dqsien dly found for B1: ( 1, 4, 2)
2576 22:12:49.083106 best DQS0 dly(MCK, UI, PI) = (1, 4, 0)
2577 22:12:49.086542 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2578 22:12:49.086661
2579 22:12:49.089641 best DQS0 P1 dly(MCK, UI, PI) = (1, 8, 0)
2580 22:12:49.092794 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2581 22:12:49.096574 [Gating] SW calibration Done
2582 22:12:49.096693 ==
2583 22:12:49.099795 Dram Type= 6, Freq= 0, CH_0, rank 0
2584 22:12:49.103412 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2585 22:12:49.106213 ==
2586 22:12:49.106316 RX Vref Scan: 0
2587 22:12:49.106408
2588 22:12:49.109884 RX Vref 0 -> 0, step: 1
2589 22:12:49.109984
2590 22:12:49.112807 RX Delay -40 -> 252, step: 8
2591 22:12:49.116776 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2592 22:12:49.119947 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2593 22:12:49.123005 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2594 22:12:49.126584 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2595 22:12:49.133055 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2596 22:12:49.136318 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2597 22:12:49.140244 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2598 22:12:49.143194 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2599 22:12:49.147101 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2600 22:12:49.150271 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2601 22:12:49.156230 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2602 22:12:49.159523 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2603 22:12:49.163005 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2604 22:12:49.166810 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2605 22:12:49.169857 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2606 22:12:49.176311 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2607 22:12:49.176424 ==
2608 22:12:49.179778 Dram Type= 6, Freq= 0, CH_0, rank 0
2609 22:12:49.183306 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2610 22:12:49.183392 ==
2611 22:12:49.183460 DQS Delay:
2612 22:12:49.186464 DQS0 = 0, DQS1 = 0
2613 22:12:49.186567 DQM Delay:
2614 22:12:49.189888 DQM0 = 115, DQM1 = 107
2615 22:12:49.189968 DQ Delay:
2616 22:12:49.193054 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =111
2617 22:12:49.196213 DQ4 =115, DQ5 =111, DQ6 =123, DQ7 =123
2618 22:12:49.200166 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =99
2619 22:12:49.203269 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115
2620 22:12:49.203381
2621 22:12:49.203480
2622 22:12:49.206599 ==
2623 22:12:49.209809 Dram Type= 6, Freq= 0, CH_0, rank 0
2624 22:12:49.213042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2625 22:12:49.213130 ==
2626 22:12:49.213196
2627 22:12:49.213256
2628 22:12:49.215853 TX Vref Scan disable
2629 22:12:49.216039 == TX Byte 0 ==
2630 22:12:49.219326 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2631 22:12:49.226281 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2632 22:12:49.226382 == TX Byte 1 ==
2633 22:12:49.229488 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2634 22:12:49.235868 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2635 22:12:49.235991 ==
2636 22:12:49.239702 Dram Type= 6, Freq= 0, CH_0, rank 0
2637 22:12:49.242936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2638 22:12:49.243022 ==
2639 22:12:49.255019 TX Vref=22, minBit 1, minWin=25, winSum=420
2640 22:12:49.258183 TX Vref=24, minBit 1, minWin=25, winSum=423
2641 22:12:49.261524 TX Vref=26, minBit 12, minWin=25, winSum=428
2642 22:12:49.265763 TX Vref=28, minBit 0, minWin=26, winSum=433
2643 22:12:49.268354 TX Vref=30, minBit 1, minWin=26, winSum=436
2644 22:12:49.272103 TX Vref=32, minBit 0, minWin=26, winSum=436
2645 22:12:49.278069 [TxChooseVref] Worse bit 1, Min win 26, Win sum 436, Final Vref 30
2646 22:12:49.278194
2647 22:12:49.281848 Final TX Range 1 Vref 30
2648 22:12:49.281940
2649 22:12:49.282042 ==
2650 22:12:49.285466 Dram Type= 6, Freq= 0, CH_0, rank 0
2651 22:12:49.288967 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2652 22:12:49.289064 ==
2653 22:12:49.289151
2654 22:12:49.291525
2655 22:12:49.291611 TX Vref Scan disable
2656 22:12:49.295269 == TX Byte 0 ==
2657 22:12:49.298618 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2658 22:12:49.301542 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2659 22:12:49.304939 == TX Byte 1 ==
2660 22:12:49.308877 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2661 22:12:49.311442 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2662 22:12:49.311532
2663 22:12:49.315246 [DATLAT]
2664 22:12:49.315333 Freq=1200, CH0 RK0
2665 22:12:49.315401
2666 22:12:49.318334 DATLAT Default: 0xd
2667 22:12:49.318418 0, 0xFFFF, sum = 0
2668 22:12:49.321567 1, 0xFFFF, sum = 0
2669 22:12:49.321653 2, 0xFFFF, sum = 0
2670 22:12:49.325217 3, 0xFFFF, sum = 0
2671 22:12:49.325307 4, 0xFFFF, sum = 0
2672 22:12:49.328541 5, 0xFFFF, sum = 0
2673 22:12:49.328628 6, 0xFFFF, sum = 0
2674 22:12:49.331642 7, 0xFFFF, sum = 0
2675 22:12:49.331727 8, 0xFFFF, sum = 0
2676 22:12:49.335197 9, 0xFFFF, sum = 0
2677 22:12:49.338733 10, 0xFFFF, sum = 0
2678 22:12:49.338823 11, 0xFFFF, sum = 0
2679 22:12:49.342241 12, 0x0, sum = 1
2680 22:12:49.342330 13, 0x0, sum = 2
2681 22:12:49.342397 14, 0x0, sum = 3
2682 22:12:49.345077 15, 0x0, sum = 4
2683 22:12:49.345163 best_step = 13
2684 22:12:49.345230
2685 22:12:49.348402 ==
2686 22:12:49.348486 Dram Type= 6, Freq= 0, CH_0, rank 0
2687 22:12:49.355500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2688 22:12:49.355660 ==
2689 22:12:49.355778 RX Vref Scan: 1
2690 22:12:49.355842
2691 22:12:49.358683 Set Vref Range= 32 -> 127
2692 22:12:49.358766
2693 22:12:49.362216 RX Vref 32 -> 127, step: 1
2694 22:12:49.362301
2695 22:12:49.365273 RX Delay -21 -> 252, step: 4
2696 22:12:49.365358
2697 22:12:49.368604 Set Vref, RX VrefLevel [Byte0]: 32
2698 22:12:49.371849 [Byte1]: 32
2699 22:12:49.371937
2700 22:12:49.375041 Set Vref, RX VrefLevel [Byte0]: 33
2701 22:12:49.378583 [Byte1]: 33
2702 22:12:49.378683
2703 22:12:49.381642 Set Vref, RX VrefLevel [Byte0]: 34
2704 22:12:49.385570 [Byte1]: 34
2705 22:12:49.389164
2706 22:12:49.389258 Set Vref, RX VrefLevel [Byte0]: 35
2707 22:12:49.392384 [Byte1]: 35
2708 22:12:49.397123
2709 22:12:49.397254 Set Vref, RX VrefLevel [Byte0]: 36
2710 22:12:49.400398 [Byte1]: 36
2711 22:12:49.404893
2712 22:12:49.404991 Set Vref, RX VrefLevel [Byte0]: 37
2713 22:12:49.408250 [Byte1]: 37
2714 22:12:49.412715
2715 22:12:49.412835 Set Vref, RX VrefLevel [Byte0]: 38
2716 22:12:49.416012 [Byte1]: 38
2717 22:12:49.420706
2718 22:12:49.420797 Set Vref, RX VrefLevel [Byte0]: 39
2719 22:12:49.424079 [Byte1]: 39
2720 22:12:49.428796
2721 22:12:49.428889 Set Vref, RX VrefLevel [Byte0]: 40
2722 22:12:49.432118 [Byte1]: 40
2723 22:12:49.436758
2724 22:12:49.436850 Set Vref, RX VrefLevel [Byte0]: 41
2725 22:12:49.440190 [Byte1]: 41
2726 22:12:49.444695
2727 22:12:49.444785 Set Vref, RX VrefLevel [Byte0]: 42
2728 22:12:49.448164 [Byte1]: 42
2729 22:12:49.452752
2730 22:12:49.452842 Set Vref, RX VrefLevel [Byte0]: 43
2731 22:12:49.455911 [Byte1]: 43
2732 22:12:49.460827
2733 22:12:49.460925 Set Vref, RX VrefLevel [Byte0]: 44
2734 22:12:49.463767 [Byte1]: 44
2735 22:12:49.468383
2736 22:12:49.468473 Set Vref, RX VrefLevel [Byte0]: 45
2737 22:12:49.471859 [Byte1]: 45
2738 22:12:49.476660
2739 22:12:49.476750 Set Vref, RX VrefLevel [Byte0]: 46
2740 22:12:49.479644 [Byte1]: 46
2741 22:12:49.484487
2742 22:12:49.484580 Set Vref, RX VrefLevel [Byte0]: 47
2743 22:12:49.487439 [Byte1]: 47
2744 22:12:49.492255
2745 22:12:49.492350 Set Vref, RX VrefLevel [Byte0]: 48
2746 22:12:49.495502 [Byte1]: 48
2747 22:12:49.499912
2748 22:12:49.500060 Set Vref, RX VrefLevel [Byte0]: 49
2749 22:12:49.503214 [Byte1]: 49
2750 22:12:49.508093
2751 22:12:49.508192 Set Vref, RX VrefLevel [Byte0]: 50
2752 22:12:49.511005 [Byte1]: 50
2753 22:12:49.515664
2754 22:12:49.515757 Set Vref, RX VrefLevel [Byte0]: 51
2755 22:12:49.519027 [Byte1]: 51
2756 22:12:49.523698
2757 22:12:49.523794 Set Vref, RX VrefLevel [Byte0]: 52
2758 22:12:49.527429 [Byte1]: 52
2759 22:12:49.531488
2760 22:12:49.531581 Set Vref, RX VrefLevel [Byte0]: 53
2761 22:12:49.535296 [Byte1]: 53
2762 22:12:49.540302
2763 22:12:49.540400 Set Vref, RX VrefLevel [Byte0]: 54
2764 22:12:49.542819 [Byte1]: 54
2765 22:12:49.547781
2766 22:12:49.547873 Set Vref, RX VrefLevel [Byte0]: 55
2767 22:12:49.551266 [Byte1]: 55
2768 22:12:49.555474
2769 22:12:49.555566 Set Vref, RX VrefLevel [Byte0]: 56
2770 22:12:49.558949 [Byte1]: 56
2771 22:12:49.564029
2772 22:12:49.564123 Set Vref, RX VrefLevel [Byte0]: 57
2773 22:12:49.567092 [Byte1]: 57
2774 22:12:49.571693
2775 22:12:49.571784 Set Vref, RX VrefLevel [Byte0]: 58
2776 22:12:49.574885 [Byte1]: 58
2777 22:12:49.579386
2778 22:12:49.579481 Set Vref, RX VrefLevel [Byte0]: 59
2779 22:12:49.582774 [Byte1]: 59
2780 22:12:49.587172
2781 22:12:49.587268 Set Vref, RX VrefLevel [Byte0]: 60
2782 22:12:49.591601 [Byte1]: 60
2783 22:12:49.595462
2784 22:12:49.595556 Set Vref, RX VrefLevel [Byte0]: 61
2785 22:12:49.598845 [Byte1]: 61
2786 22:12:49.603187
2787 22:12:49.603295 Set Vref, RX VrefLevel [Byte0]: 62
2788 22:12:49.606676 [Byte1]: 62
2789 22:12:49.610776
2790 22:12:49.610871 Set Vref, RX VrefLevel [Byte0]: 63
2791 22:12:49.614431 [Byte1]: 63
2792 22:12:49.619205
2793 22:12:49.619308 Set Vref, RX VrefLevel [Byte0]: 64
2794 22:12:49.622388 [Byte1]: 64
2795 22:12:49.627086
2796 22:12:49.627180 Set Vref, RX VrefLevel [Byte0]: 65
2797 22:12:49.630310 [Byte1]: 65
2798 22:12:49.635053
2799 22:12:49.635151 Set Vref, RX VrefLevel [Byte0]: 66
2800 22:12:49.638409 [Byte1]: 66
2801 22:12:49.642947
2802 22:12:49.643040 Set Vref, RX VrefLevel [Byte0]: 67
2803 22:12:49.646771 [Byte1]: 67
2804 22:12:49.650657
2805 22:12:49.650746 Set Vref, RX VrefLevel [Byte0]: 68
2806 22:12:49.654206 [Byte1]: 68
2807 22:12:49.658461
2808 22:12:49.658551 Set Vref, RX VrefLevel [Byte0]: 69
2809 22:12:49.662473 [Byte1]: 69
2810 22:12:49.667521
2811 22:12:49.667616 Final RX Vref Byte 0 = 52 to rank0
2812 22:12:49.669748 Final RX Vref Byte 1 = 50 to rank0
2813 22:12:49.673369 Final RX Vref Byte 0 = 52 to rank1
2814 22:12:49.677252 Final RX Vref Byte 1 = 50 to rank1==
2815 22:12:49.680114 Dram Type= 6, Freq= 0, CH_0, rank 0
2816 22:12:49.686779 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2817 22:12:49.686910 ==
2818 22:12:49.687024 DQS Delay:
2819 22:12:49.687118 DQS0 = 0, DQS1 = 0
2820 22:12:49.690298 DQM Delay:
2821 22:12:49.690377 DQM0 = 115, DQM1 = 104
2822 22:12:49.693709 DQ Delay:
2823 22:12:49.696897 DQ0 =116, DQ1 =114, DQ2 =112, DQ3 =114
2824 22:12:49.700402 DQ4 =116, DQ5 =108, DQ6 =122, DQ7 =122
2825 22:12:49.703646 DQ8 =92, DQ9 =90, DQ10 =104, DQ11 =96
2826 22:12:49.706481 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =112
2827 22:12:49.706594
2828 22:12:49.706688
2829 22:12:49.713334 [DQSOSCAuto] RK0, (LSB)MR18= 0xfceb, (MSB)MR19= 0x303, tDQSOscB0 = 418 ps tDQSOscB1 = 411 ps
2830 22:12:49.717054 CH0 RK0: MR19=303, MR18=FCEB
2831 22:12:49.723203 CH0_RK0: MR19=0x303, MR18=0xFCEB, DQSOSC=411, MR23=63, INC=38, DEC=25
2832 22:12:49.723317
2833 22:12:49.727022 ----->DramcWriteLeveling(PI) begin...
2834 22:12:49.727149 ==
2835 22:12:49.729730 Dram Type= 6, Freq= 0, CH_0, rank 1
2836 22:12:49.733665 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2837 22:12:49.736369 ==
2838 22:12:49.736460 Write leveling (Byte 0): 31 => 31
2839 22:12:49.740133 Write leveling (Byte 1): 28 => 28
2840 22:12:49.743222 DramcWriteLeveling(PI) end<-----
2841 22:12:49.743310
2842 22:12:49.743377 ==
2843 22:12:49.746692 Dram Type= 6, Freq= 0, CH_0, rank 1
2844 22:12:49.753437 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2845 22:12:49.753547 ==
2846 22:12:49.753619 [Gating] SW mode calibration
2847 22:12:49.762980 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2848 22:12:49.766522 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2849 22:12:49.769636 0 15 0 | B1->B0 | 2323 2828 | 0 1 | (0 0) (0 0)
2850 22:12:49.777091 0 15 4 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 1)
2851 22:12:49.780092 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2852 22:12:49.783249 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2853 22:12:49.789922 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2854 22:12:49.793279 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2855 22:12:49.796531 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2856 22:12:49.803792 0 15 28 | B1->B0 | 3434 2a2a | 1 0 | (1 0) (1 0)
2857 22:12:49.807219 1 0 0 | B1->B0 | 2f2f 2424 | 0 1 | (0 1) (0 0)
2858 22:12:49.809897 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2859 22:12:49.816346 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2860 22:12:49.819889 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2861 22:12:49.822872 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2862 22:12:49.830070 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2863 22:12:49.832929 1 0 24 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
2864 22:12:49.836452 1 0 28 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
2865 22:12:49.842989 1 1 0 | B1->B0 | 3b3b 4444 | 0 0 | (0 0) (0 0)
2866 22:12:49.846456 1 1 4 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
2867 22:12:49.849796 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2868 22:12:49.856287 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2869 22:12:49.859826 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2870 22:12:49.863297 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2871 22:12:49.866789 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2872 22:12:49.873199 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2873 22:12:49.876354 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2874 22:12:49.879830 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2875 22:12:49.886561 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2876 22:12:49.889804 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2877 22:12:49.892866 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2878 22:12:49.900159 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2879 22:12:49.903323 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2880 22:12:49.906567 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2881 22:12:49.912649 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2882 22:12:49.916268 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2883 22:12:49.919729 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 22:12:49.926417 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 22:12:49.929443 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 22:12:49.932775 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 22:12:49.939419 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2888 22:12:49.942659 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2889 22:12:49.946316 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2890 22:12:49.950197 Total UI for P1: 0, mck2ui 16
2891 22:12:49.952647 best dqsien dly found for B0: ( 1, 3, 26)
2892 22:12:49.959682 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2893 22:12:49.959791 Total UI for P1: 0, mck2ui 16
2894 22:12:49.962917 best dqsien dly found for B1: ( 1, 4, 0)
2895 22:12:49.966084 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2896 22:12:49.973000 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2897 22:12:49.973104
2898 22:12:49.976159 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2899 22:12:49.979865 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2900 22:12:49.983649 [Gating] SW calibration Done
2901 22:12:49.983736 ==
2902 22:12:49.986423 Dram Type= 6, Freq= 0, CH_0, rank 1
2903 22:12:49.989425 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2904 22:12:49.989515 ==
2905 22:12:49.989600 RX Vref Scan: 0
2906 22:12:49.993416
2907 22:12:49.993495 RX Vref 0 -> 0, step: 1
2908 22:12:49.993578
2909 22:12:49.996505 RX Delay -40 -> 252, step: 8
2910 22:12:49.999360 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2911 22:12:50.003247 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2912 22:12:50.009584 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2913 22:12:50.013041 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2914 22:12:50.016488 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2915 22:12:50.020302 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2916 22:12:50.023664 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2917 22:12:50.029953 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2918 22:12:50.033029 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2919 22:12:50.035916 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2920 22:12:50.039671 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2921 22:12:50.042620 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2922 22:12:50.049497 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2923 22:12:50.052828 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2924 22:12:50.056505 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2925 22:12:50.059342 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2926 22:12:50.059424 ==
2927 22:12:50.062776 Dram Type= 6, Freq= 0, CH_0, rank 1
2928 22:12:50.066387 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2929 22:12:50.069748 ==
2930 22:12:50.069861 DQS Delay:
2931 22:12:50.069927 DQS0 = 0, DQS1 = 0
2932 22:12:50.073187 DQM Delay:
2933 22:12:50.073261 DQM0 = 115, DQM1 = 105
2934 22:12:50.076307 DQ Delay:
2935 22:12:50.079627 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =115
2936 22:12:50.082844 DQ4 =115, DQ5 =103, DQ6 =123, DQ7 =123
2937 22:12:50.086076 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =99
2938 22:12:50.089935 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2939 22:12:50.090017
2940 22:12:50.090085
2941 22:12:50.090147 ==
2942 22:12:50.093055 Dram Type= 6, Freq= 0, CH_0, rank 1
2943 22:12:50.096127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2944 22:12:50.096230 ==
2945 22:12:50.096322
2946 22:12:50.096409
2947 22:12:50.099897 TX Vref Scan disable
2948 22:12:50.102589 == TX Byte 0 ==
2949 22:12:50.106727 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2950 22:12:50.109527 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2951 22:12:50.112638 == TX Byte 1 ==
2952 22:12:50.116282 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2953 22:12:50.119478 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2954 22:12:50.119586 ==
2955 22:12:50.122832 Dram Type= 6, Freq= 0, CH_0, rank 1
2956 22:12:50.126533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2957 22:12:50.129466 ==
2958 22:12:50.139841 TX Vref=22, minBit 0, minWin=26, winSum=427
2959 22:12:50.143310 TX Vref=24, minBit 1, minWin=25, winSum=432
2960 22:12:50.146408 TX Vref=26, minBit 0, minWin=26, winSum=431
2961 22:12:50.149423 TX Vref=28, minBit 7, minWin=26, winSum=437
2962 22:12:50.153146 TX Vref=30, minBit 0, minWin=27, winSum=439
2963 22:12:50.160081 TX Vref=32, minBit 13, minWin=26, winSum=440
2964 22:12:50.163351 [TxChooseVref] Worse bit 0, Min win 27, Win sum 439, Final Vref 30
2965 22:12:50.163469
2966 22:12:50.166372 Final TX Range 1 Vref 30
2967 22:12:50.166456
2968 22:12:50.166522 ==
2969 22:12:50.169848 Dram Type= 6, Freq= 0, CH_0, rank 1
2970 22:12:50.173425 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2971 22:12:50.173530 ==
2972 22:12:50.175944
2973 22:12:50.176045
2974 22:12:50.176110 TX Vref Scan disable
2975 22:12:50.179553 == TX Byte 0 ==
2976 22:12:50.182832 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2977 22:12:50.186485 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2978 22:12:50.189683 == TX Byte 1 ==
2979 22:12:50.192989 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2980 22:12:50.197084 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2981 22:12:50.199448
2982 22:12:50.199548 [DATLAT]
2983 22:12:50.199634 Freq=1200, CH0 RK1
2984 22:12:50.199728
2985 22:12:50.203192 DATLAT Default: 0xd
2986 22:12:50.203300 0, 0xFFFF, sum = 0
2987 22:12:50.206408 1, 0xFFFF, sum = 0
2988 22:12:50.206516 2, 0xFFFF, sum = 0
2989 22:12:50.209517 3, 0xFFFF, sum = 0
2990 22:12:50.213046 4, 0xFFFF, sum = 0
2991 22:12:50.213142 5, 0xFFFF, sum = 0
2992 22:12:50.216397 6, 0xFFFF, sum = 0
2993 22:12:50.216473 7, 0xFFFF, sum = 0
2994 22:12:50.219841 8, 0xFFFF, sum = 0
2995 22:12:50.219947 9, 0xFFFF, sum = 0
2996 22:12:50.222874 10, 0xFFFF, sum = 0
2997 22:12:50.222983 11, 0xFFFF, sum = 0
2998 22:12:50.226040 12, 0x0, sum = 1
2999 22:12:50.226151 13, 0x0, sum = 2
3000 22:12:50.230115 14, 0x0, sum = 3
3001 22:12:50.230193 15, 0x0, sum = 4
3002 22:12:50.230257 best_step = 13
3003 22:12:50.230317
3004 22:12:50.233178 ==
3005 22:12:50.236124 Dram Type= 6, Freq= 0, CH_0, rank 1
3006 22:12:50.239441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3007 22:12:50.239539 ==
3008 22:12:50.239607 RX Vref Scan: 0
3009 22:12:50.239669
3010 22:12:50.243256 RX Vref 0 -> 0, step: 1
3011 22:12:50.243359
3012 22:12:50.246724 RX Delay -21 -> 252, step: 4
3013 22:12:50.249811 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3014 22:12:50.256822 iDelay=195, Bit 1, Center 114 (43 ~ 186) 144
3015 22:12:50.259464 iDelay=195, Bit 2, Center 110 (39 ~ 182) 144
3016 22:12:50.263022 iDelay=195, Bit 3, Center 114 (43 ~ 186) 144
3017 22:12:50.266661 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3018 22:12:50.269788 iDelay=195, Bit 5, Center 104 (35 ~ 174) 140
3019 22:12:50.276270 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3020 22:12:50.279263 iDelay=195, Bit 7, Center 120 (51 ~ 190) 140
3021 22:12:50.283185 iDelay=195, Bit 8, Center 94 (27 ~ 162) 136
3022 22:12:50.286253 iDelay=195, Bit 9, Center 92 (23 ~ 162) 140
3023 22:12:50.289595 iDelay=195, Bit 10, Center 106 (39 ~ 174) 136
3024 22:12:50.293266 iDelay=195, Bit 11, Center 94 (27 ~ 162) 136
3025 22:12:50.299634 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3026 22:12:50.303215 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3027 22:12:50.306360 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3028 22:12:50.310201 iDelay=195, Bit 15, Center 114 (47 ~ 182) 136
3029 22:12:50.310310 ==
3030 22:12:50.314703 Dram Type= 6, Freq= 0, CH_0, rank 1
3031 22:12:50.319741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3032 22:12:50.319839 ==
3033 22:12:50.319909 DQS Delay:
3034 22:12:50.320004 DQS0 = 0, DQS1 = 0
3035 22:12:50.323011 DQM Delay:
3036 22:12:50.323112 DQM0 = 113, DQM1 = 104
3037 22:12:50.326434 DQ Delay:
3038 22:12:50.330007 DQ0 =114, DQ1 =114, DQ2 =110, DQ3 =114
3039 22:12:50.333269 DQ4 =112, DQ5 =104, DQ6 =122, DQ7 =120
3040 22:12:50.336415 DQ8 =94, DQ9 =92, DQ10 =106, DQ11 =94
3041 22:12:50.340257 DQ12 =110, DQ13 =110, DQ14 =116, DQ15 =114
3042 22:12:50.340345
3043 22:12:50.340413
3044 22:12:50.346257 [DQSOSCAuto] RK1, (LSB)MR18= 0x2f4, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 409 ps
3045 22:12:50.349919 CH0 RK1: MR19=403, MR18=2F4
3046 22:12:50.356534 CH0_RK1: MR19=0x403, MR18=0x2F4, DQSOSC=409, MR23=63, INC=39, DEC=26
3047 22:12:50.359460 [RxdqsGatingPostProcess] freq 1200
3048 22:12:50.366813 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3049 22:12:50.366929 best DQS0 dly(2T, 0.5T) = (0, 12)
3050 22:12:50.369375 best DQS1 dly(2T, 0.5T) = (0, 12)
3051 22:12:50.373279 best DQS0 P1 dly(2T, 0.5T) = (1, 0)
3052 22:12:50.376193 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3053 22:12:50.380110 best DQS0 dly(2T, 0.5T) = (0, 11)
3054 22:12:50.383115 best DQS1 dly(2T, 0.5T) = (0, 12)
3055 22:12:50.386225 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3056 22:12:50.389662 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3057 22:12:50.393075 Pre-setting of DQS Precalculation
3058 22:12:50.396187 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3059 22:12:50.400446 ==
3060 22:12:50.403325 Dram Type= 6, Freq= 0, CH_1, rank 0
3061 22:12:50.406164 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3062 22:12:50.406271 ==
3063 22:12:50.409597 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3064 22:12:50.416240 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3065 22:12:50.425792 [CA 0] Center 38 (9~68) winsize 60
3066 22:12:50.428727 [CA 1] Center 38 (8~68) winsize 61
3067 22:12:50.432388 [CA 2] Center 35 (5~65) winsize 61
3068 22:12:50.435527 [CA 3] Center 34 (4~65) winsize 62
3069 22:12:50.438719 [CA 4] Center 34 (4~65) winsize 62
3070 22:12:50.442171 [CA 5] Center 34 (4~64) winsize 61
3071 22:12:50.442253
3072 22:12:50.445445 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3073 22:12:50.445546
3074 22:12:50.448797 [CATrainingPosCal] consider 1 rank data
3075 22:12:50.452155 u2DelayCellTimex100 = 270/100 ps
3076 22:12:50.455549 CA0 delay=38 (9~68),Diff = 4 PI (19 cell)
3077 22:12:50.458850 CA1 delay=38 (8~68),Diff = 4 PI (19 cell)
3078 22:12:50.465292 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3079 22:12:50.468376 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3080 22:12:50.472251 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3081 22:12:50.474877 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3082 22:12:50.474960
3083 22:12:50.478261 CA PerBit enable=1, Macro0, CA PI delay=34
3084 22:12:50.478366
3085 22:12:50.481690 [CBTSetCACLKResult] CA Dly = 34
3086 22:12:50.481802 CS Dly: 6 (0~37)
3087 22:12:50.484916 ==
3088 22:12:50.488458 Dram Type= 6, Freq= 0, CH_1, rank 1
3089 22:12:50.491569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3090 22:12:50.491677 ==
3091 22:12:50.495168 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3092 22:12:50.502311 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3093 22:12:50.510931 [CA 0] Center 38 (8~68) winsize 61
3094 22:12:50.514575 [CA 1] Center 38 (9~68) winsize 60
3095 22:12:50.518101 [CA 2] Center 34 (4~65) winsize 62
3096 22:12:50.520857 [CA 3] Center 34 (4~65) winsize 62
3097 22:12:50.524599 [CA 4] Center 34 (4~65) winsize 62
3098 22:12:50.528476 [CA 5] Center 33 (3~63) winsize 61
3099 22:12:50.528574
3100 22:12:50.531191 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3101 22:12:50.531275
3102 22:12:50.534985 [CATrainingPosCal] consider 2 rank data
3103 22:12:50.537712 u2DelayCellTimex100 = 270/100 ps
3104 22:12:50.540790 CA0 delay=38 (9~68),Diff = 5 PI (24 cell)
3105 22:12:50.544872 CA1 delay=38 (9~68),Diff = 5 PI (24 cell)
3106 22:12:50.551295 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3107 22:12:50.554365 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3108 22:12:50.557580 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3109 22:12:50.561368 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3110 22:12:50.561460
3111 22:12:50.564939 CA PerBit enable=1, Macro0, CA PI delay=33
3112 22:12:50.565026
3113 22:12:50.568073 [CBTSetCACLKResult] CA Dly = 33
3114 22:12:50.568157 CS Dly: 7 (0~40)
3115 22:12:50.568224
3116 22:12:50.571664 ----->DramcWriteLeveling(PI) begin...
3117 22:12:50.574409 ==
3118 22:12:50.574496 Dram Type= 6, Freq= 0, CH_1, rank 0
3119 22:12:50.580932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3120 22:12:50.581036 ==
3121 22:12:50.584252 Write leveling (Byte 0): 26 => 26
3122 22:12:50.587761 Write leveling (Byte 1): 29 => 29
3123 22:12:50.591226 DramcWriteLeveling(PI) end<-----
3124 22:12:50.591319
3125 22:12:50.591388 ==
3126 22:12:50.594364 Dram Type= 6, Freq= 0, CH_1, rank 0
3127 22:12:50.597333 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3128 22:12:50.597417 ==
3129 22:12:50.601268 [Gating] SW mode calibration
3130 22:12:50.607801 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3131 22:12:50.610989 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3132 22:12:50.618107 0 15 0 | B1->B0 | 2b2b 2323 | 0 1 | (0 0) (1 1)
3133 22:12:50.621095 0 15 4 | B1->B0 | 3434 3434 | 0 0 | (0 0) (0 0)
3134 22:12:50.624634 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3135 22:12:50.631091 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3136 22:12:50.634443 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3137 22:12:50.638152 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3138 22:12:50.644661 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3139 22:12:50.647807 0 15 28 | B1->B0 | 3434 3434 | 0 0 | (0 0) (0 1)
3140 22:12:50.651849 1 0 0 | B1->B0 | 2424 2727 | 0 0 | (0 0) (1 0)
3141 22:12:50.657787 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3142 22:12:50.661696 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3143 22:12:50.665419 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3144 22:12:50.668120 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3145 22:12:50.674956 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3146 22:12:50.678063 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3147 22:12:50.681160 1 0 28 | B1->B0 | 2929 2525 | 0 0 | (0 0) (0 0)
3148 22:12:50.688008 1 1 0 | B1->B0 | 4242 3434 | 0 0 | (1 1) (0 0)
3149 22:12:50.691173 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3150 22:12:50.694630 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3151 22:12:50.701764 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3152 22:12:50.705081 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3153 22:12:50.707575 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3154 22:12:50.714664 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3155 22:12:50.717628 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3156 22:12:50.720808 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3157 22:12:50.727391 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3158 22:12:50.731089 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3159 22:12:50.734278 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3160 22:12:50.740865 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3161 22:12:50.743844 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3162 22:12:50.747478 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3163 22:12:50.754308 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3164 22:12:50.757789 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3165 22:12:50.761002 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3166 22:12:50.767145 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 22:12:50.770986 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 22:12:50.774716 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 22:12:50.781577 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 22:12:50.783870 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 22:12:50.787199 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3172 22:12:50.793852 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3173 22:12:50.793967 Total UI for P1: 0, mck2ui 16
3174 22:12:50.797526 best dqsien dly found for B1: ( 1, 3, 30)
3175 22:12:50.803832 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3176 22:12:50.807474 Total UI for P1: 0, mck2ui 16
3177 22:12:50.810436 best dqsien dly found for B0: ( 1, 3, 30)
3178 22:12:50.814248 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
3179 22:12:50.817751 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
3180 22:12:50.817845
3181 22:12:50.820938 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
3182 22:12:50.824185 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
3183 22:12:50.827455 [Gating] SW calibration Done
3184 22:12:50.827546 ==
3185 22:12:50.830748 Dram Type= 6, Freq= 0, CH_1, rank 0
3186 22:12:50.834823 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3187 22:12:50.834916 ==
3188 22:12:50.837491 RX Vref Scan: 0
3189 22:12:50.837576
3190 22:12:50.840224 RX Vref 0 -> 0, step: 1
3191 22:12:50.840310
3192 22:12:50.840377 RX Delay -40 -> 252, step: 8
3193 22:12:50.847041 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3194 22:12:50.850602 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3195 22:12:50.853610 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3196 22:12:50.857114 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3197 22:12:50.860825 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3198 22:12:50.866596 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3199 22:12:50.870207 iDelay=200, Bit 6, Center 127 (64 ~ 191) 128
3200 22:12:50.874008 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3201 22:12:50.876753 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3202 22:12:50.880367 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3203 22:12:50.886935 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3204 22:12:50.890425 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3205 22:12:50.893488 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3206 22:12:50.896818 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
3207 22:12:50.903210 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3208 22:12:50.906710 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3209 22:12:50.906834 ==
3210 22:12:50.910275 Dram Type= 6, Freq= 0, CH_1, rank 0
3211 22:12:50.913822 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3212 22:12:50.913933 ==
3213 22:12:50.914026 DQS Delay:
3214 22:12:50.916670 DQS0 = 0, DQS1 = 0
3215 22:12:50.916768 DQM Delay:
3216 22:12:50.919841 DQM0 = 116, DQM1 = 108
3217 22:12:50.919961 DQ Delay:
3218 22:12:50.923545 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =115
3219 22:12:50.926456 DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =111
3220 22:12:50.929835 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =107
3221 22:12:50.933336 DQ12 =119, DQ13 =115, DQ14 =111, DQ15 =111
3222 22:12:50.933431
3223 22:12:50.936824
3224 22:12:50.936908 ==
3225 22:12:50.939994 Dram Type= 6, Freq= 0, CH_1, rank 0
3226 22:12:50.943672 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3227 22:12:50.943754 ==
3228 22:12:50.943820
3229 22:12:50.943890
3230 22:12:50.946829 TX Vref Scan disable
3231 22:12:50.946906 == TX Byte 0 ==
3232 22:12:50.950350 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3233 22:12:50.956922 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3234 22:12:50.957021 == TX Byte 1 ==
3235 22:12:50.959922 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3236 22:12:50.967172 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3237 22:12:50.967266 ==
3238 22:12:50.970101 Dram Type= 6, Freq= 0, CH_1, rank 0
3239 22:12:50.973586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3240 22:12:50.973675 ==
3241 22:12:50.985575 TX Vref=22, minBit 4, minWin=25, winSum=413
3242 22:12:50.988860 TX Vref=24, minBit 1, minWin=24, winSum=412
3243 22:12:50.992581 TX Vref=26, minBit 0, minWin=26, winSum=423
3244 22:12:50.995406 TX Vref=28, minBit 0, minWin=26, winSum=426
3245 22:12:50.999838 TX Vref=30, minBit 1, minWin=26, winSum=429
3246 22:12:51.002314 TX Vref=32, minBit 3, minWin=26, winSum=429
3247 22:12:51.009034 [TxChooseVref] Worse bit 1, Min win 26, Win sum 429, Final Vref 30
3248 22:12:51.009149
3249 22:12:51.012366 Final TX Range 1 Vref 30
3250 22:12:51.012457
3251 22:12:51.012543 ==
3252 22:12:51.015655 Dram Type= 6, Freq= 0, CH_1, rank 0
3253 22:12:51.019274 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3254 22:12:51.019367 ==
3255 22:12:51.019454
3256 22:12:51.019535
3257 22:12:51.022630 TX Vref Scan disable
3258 22:12:51.025897 == TX Byte 0 ==
3259 22:12:51.029402 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3260 22:12:51.032435 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3261 22:12:51.035613 == TX Byte 1 ==
3262 22:12:51.039343 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3263 22:12:51.042427 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3264 22:12:51.042520
3265 22:12:51.045913 [DATLAT]
3266 22:12:51.046001 Freq=1200, CH1 RK0
3267 22:12:51.046087
3268 22:12:51.048889 DATLAT Default: 0xd
3269 22:12:51.048974 0, 0xFFFF, sum = 0
3270 22:12:51.052498 1, 0xFFFF, sum = 0
3271 22:12:51.052586 2, 0xFFFF, sum = 0
3272 22:12:51.055884 3, 0xFFFF, sum = 0
3273 22:12:51.055996 4, 0xFFFF, sum = 0
3274 22:12:51.058872 5, 0xFFFF, sum = 0
3275 22:12:51.058960 6, 0xFFFF, sum = 0
3276 22:12:51.062324 7, 0xFFFF, sum = 0
3277 22:12:51.062412 8, 0xFFFF, sum = 0
3278 22:12:51.065847 9, 0xFFFF, sum = 0
3279 22:12:51.068850 10, 0xFFFF, sum = 0
3280 22:12:51.068939 11, 0xFFFF, sum = 0
3281 22:12:51.072155 12, 0x0, sum = 1
3282 22:12:51.072242 13, 0x0, sum = 2
3283 22:12:51.072330 14, 0x0, sum = 3
3284 22:12:51.075687 15, 0x0, sum = 4
3285 22:12:51.075776 best_step = 13
3286 22:12:51.075879
3287 22:12:51.076008 ==
3288 22:12:51.079059 Dram Type= 6, Freq= 0, CH_1, rank 0
3289 22:12:51.086253 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3290 22:12:51.086356 ==
3291 22:12:51.086446 RX Vref Scan: 1
3292 22:12:51.086527
3293 22:12:51.089380 Set Vref Range= 32 -> 127
3294 22:12:51.089488
3295 22:12:51.092598 RX Vref 32 -> 127, step: 1
3296 22:12:51.092685
3297 22:12:51.096080 RX Delay -21 -> 252, step: 4
3298 22:12:51.096166
3299 22:12:51.098806 Set Vref, RX VrefLevel [Byte0]: 32
3300 22:12:51.102100 [Byte1]: 32
3301 22:12:51.102221
3302 22:12:51.105682 Set Vref, RX VrefLevel [Byte0]: 33
3303 22:12:51.108635 [Byte1]: 33
3304 22:12:51.108719
3305 22:12:51.112133 Set Vref, RX VrefLevel [Byte0]: 34
3306 22:12:51.115829 [Byte1]: 34
3307 22:12:51.119577
3308 22:12:51.119690 Set Vref, RX VrefLevel [Byte0]: 35
3309 22:12:51.123000 [Byte1]: 35
3310 22:12:51.127305
3311 22:12:51.127400 Set Vref, RX VrefLevel [Byte0]: 36
3312 22:12:51.131050 [Byte1]: 36
3313 22:12:51.135724
3314 22:12:51.135815 Set Vref, RX VrefLevel [Byte0]: 37
3315 22:12:51.138799 [Byte1]: 37
3316 22:12:51.143648
3317 22:12:51.143745 Set Vref, RX VrefLevel [Byte0]: 38
3318 22:12:51.146879 [Byte1]: 38
3319 22:12:51.151129
3320 22:12:51.151218 Set Vref, RX VrefLevel [Byte0]: 39
3321 22:12:51.155045 [Byte1]: 39
3322 22:12:51.160393
3323 22:12:51.160489 Set Vref, RX VrefLevel [Byte0]: 40
3324 22:12:51.163441 [Byte1]: 40
3325 22:12:51.167197
3326 22:12:51.167284 Set Vref, RX VrefLevel [Byte0]: 41
3327 22:12:51.170839 [Byte1]: 41
3328 22:12:51.175042
3329 22:12:51.175169 Set Vref, RX VrefLevel [Byte0]: 42
3330 22:12:51.178847 [Byte1]: 42
3331 22:12:51.183053
3332 22:12:51.183141 Set Vref, RX VrefLevel [Byte0]: 43
3333 22:12:51.186265 [Byte1]: 43
3334 22:12:51.190694
3335 22:12:51.190781 Set Vref, RX VrefLevel [Byte0]: 44
3336 22:12:51.194413 [Byte1]: 44
3337 22:12:51.199027
3338 22:12:51.199118 Set Vref, RX VrefLevel [Byte0]: 45
3339 22:12:51.202639 [Byte1]: 45
3340 22:12:51.206859
3341 22:12:51.206950 Set Vref, RX VrefLevel [Byte0]: 46
3342 22:12:51.209724 [Byte1]: 46
3343 22:12:51.214740
3344 22:12:51.214859 Set Vref, RX VrefLevel [Byte0]: 47
3345 22:12:51.218368 [Byte1]: 47
3346 22:12:51.222907
3347 22:12:51.223000 Set Vref, RX VrefLevel [Byte0]: 48
3348 22:12:51.226060 [Byte1]: 48
3349 22:12:51.230477
3350 22:12:51.230568 Set Vref, RX VrefLevel [Byte0]: 49
3351 22:12:51.234318 [Byte1]: 49
3352 22:12:51.238261
3353 22:12:51.241799 Set Vref, RX VrefLevel [Byte0]: 50
3354 22:12:51.244675 [Byte1]: 50
3355 22:12:51.244762
3356 22:12:51.248344 Set Vref, RX VrefLevel [Byte0]: 51
3357 22:12:51.251503 [Byte1]: 51
3358 22:12:51.251589
3359 22:12:51.254889 Set Vref, RX VrefLevel [Byte0]: 52
3360 22:12:51.258256 [Byte1]: 52
3361 22:12:51.262016
3362 22:12:51.262111 Set Vref, RX VrefLevel [Byte0]: 53
3363 22:12:51.265636 [Byte1]: 53
3364 22:12:51.269884
3365 22:12:51.269984 Set Vref, RX VrefLevel [Byte0]: 54
3366 22:12:51.273454 [Byte1]: 54
3367 22:12:51.278099
3368 22:12:51.278193 Set Vref, RX VrefLevel [Byte0]: 55
3369 22:12:51.281462 [Byte1]: 55
3370 22:12:51.286042
3371 22:12:51.286130 Set Vref, RX VrefLevel [Byte0]: 56
3372 22:12:51.289587 [Byte1]: 56
3373 22:12:51.294021
3374 22:12:51.294108 Set Vref, RX VrefLevel [Byte0]: 57
3375 22:12:51.297004 [Byte1]: 57
3376 22:12:51.302209
3377 22:12:51.302315 Set Vref, RX VrefLevel [Byte0]: 58
3378 22:12:51.305798 [Byte1]: 58
3379 22:12:51.309799
3380 22:12:51.309886 Set Vref, RX VrefLevel [Byte0]: 59
3381 22:12:51.313748 [Byte1]: 59
3382 22:12:51.317554
3383 22:12:51.317681 Set Vref, RX VrefLevel [Byte0]: 60
3384 22:12:51.320922 [Byte1]: 60
3385 22:12:51.325683
3386 22:12:51.325776 Set Vref, RX VrefLevel [Byte0]: 61
3387 22:12:51.328677 [Byte1]: 61
3388 22:12:51.333355
3389 22:12:51.333479 Set Vref, RX VrefLevel [Byte0]: 62
3390 22:12:51.337002 [Byte1]: 62
3391 22:12:51.341147
3392 22:12:51.341243 Set Vref, RX VrefLevel [Byte0]: 63
3393 22:12:51.344567 [Byte1]: 63
3394 22:12:51.349641
3395 22:12:51.349739 Set Vref, RX VrefLevel [Byte0]: 64
3396 22:12:51.352865 [Byte1]: 64
3397 22:12:51.357089
3398 22:12:51.357184 Set Vref, RX VrefLevel [Byte0]: 65
3399 22:12:51.360405 [Byte1]: 65
3400 22:12:51.365199
3401 22:12:51.365293 Set Vref, RX VrefLevel [Byte0]: 66
3402 22:12:51.368449 [Byte1]: 66
3403 22:12:51.373481
3404 22:12:51.373577 Set Vref, RX VrefLevel [Byte0]: 67
3405 22:12:51.376908 [Byte1]: 67
3406 22:12:51.380723
3407 22:12:51.380815 Set Vref, RX VrefLevel [Byte0]: 68
3408 22:12:51.384079 [Byte1]: 68
3409 22:12:51.388715
3410 22:12:51.388811 Set Vref, RX VrefLevel [Byte0]: 69
3411 22:12:51.391878 [Byte1]: 69
3412 22:12:51.396909
3413 22:12:51.397002 Final RX Vref Byte 0 = 60 to rank0
3414 22:12:51.399832 Final RX Vref Byte 1 = 54 to rank0
3415 22:12:51.403630 Final RX Vref Byte 0 = 60 to rank1
3416 22:12:51.406977 Final RX Vref Byte 1 = 54 to rank1==
3417 22:12:51.409834 Dram Type= 6, Freq= 0, CH_1, rank 0
3418 22:12:51.417678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3419 22:12:51.417793 ==
3420 22:12:51.417883 DQS Delay:
3421 22:12:51.417964 DQS0 = 0, DQS1 = 0
3422 22:12:51.419903 DQM Delay:
3423 22:12:51.420037 DQM0 = 116, DQM1 = 109
3424 22:12:51.423727 DQ Delay:
3425 22:12:51.426559 DQ0 =118, DQ1 =110, DQ2 =106, DQ3 =116
3426 22:12:51.430060 DQ4 =116, DQ5 =122, DQ6 =128, DQ7 =114
3427 22:12:51.433421 DQ8 =98, DQ9 =98, DQ10 =112, DQ11 =104
3428 22:12:51.436661 DQ12 =118, DQ13 =116, DQ14 =116, DQ15 =114
3429 22:12:51.436777
3430 22:12:51.436878
3431 22:12:51.443172 [DQSOSCAuto] RK0, (LSB)MR18= 0xfde2, (MSB)MR19= 0x303, tDQSOscB0 = 422 ps tDQSOscB1 = 411 ps
3432 22:12:51.446692 CH1 RK0: MR19=303, MR18=FDE2
3433 22:12:51.453259 CH1_RK0: MR19=0x303, MR18=0xFDE2, DQSOSC=411, MR23=63, INC=38, DEC=25
3434 22:12:51.453392
3435 22:12:51.456544 ----->DramcWriteLeveling(PI) begin...
3436 22:12:51.456636 ==
3437 22:12:51.460129 Dram Type= 6, Freq= 0, CH_1, rank 1
3438 22:12:51.463504 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3439 22:12:51.466941 ==
3440 22:12:51.467036 Write leveling (Byte 0): 24 => 24
3441 22:12:51.470236 Write leveling (Byte 1): 30 => 30
3442 22:12:51.474025 DramcWriteLeveling(PI) end<-----
3443 22:12:51.474115
3444 22:12:51.474216 ==
3445 22:12:51.477123 Dram Type= 6, Freq= 0, CH_1, rank 1
3446 22:12:51.483273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3447 22:12:51.483374 ==
3448 22:12:51.483464 [Gating] SW mode calibration
3449 22:12:51.493468 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3450 22:12:51.496817 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3451 22:12:51.500785 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3452 22:12:51.506659 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3453 22:12:51.510217 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3454 22:12:51.513116 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3455 22:12:51.520067 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3456 22:12:51.523482 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3457 22:12:51.527126 0 15 24 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (0 0)
3458 22:12:51.533860 0 15 28 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
3459 22:12:51.536827 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3460 22:12:51.539960 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3461 22:12:51.546547 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3462 22:12:51.550043 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3463 22:12:51.553145 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3464 22:12:51.559869 1 0 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3465 22:12:51.563234 1 0 24 | B1->B0 | 2626 4141 | 1 0 | (0 0) (0 0)
3466 22:12:51.566538 1 0 28 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
3467 22:12:51.573381 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3468 22:12:51.576767 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3469 22:12:51.579616 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3470 22:12:51.586208 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3471 22:12:51.589787 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3472 22:12:51.593055 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3473 22:12:51.600104 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3474 22:12:51.603149 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3475 22:12:51.606734 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3476 22:12:51.613183 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3477 22:12:51.616589 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3478 22:12:51.619424 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3479 22:12:51.626135 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3480 22:12:51.629756 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3481 22:12:51.633081 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3482 22:12:51.636388 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3483 22:12:51.642654 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3484 22:12:51.646032 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3485 22:12:51.649902 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3486 22:12:51.656109 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3487 22:12:51.659495 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3488 22:12:51.662788 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3489 22:12:51.669134 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3490 22:12:51.672630 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3491 22:12:51.676419 Total UI for P1: 0, mck2ui 16
3492 22:12:51.679627 best dqsien dly found for B0: ( 1, 3, 22)
3493 22:12:51.682561 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3494 22:12:51.685880 Total UI for P1: 0, mck2ui 16
3495 22:12:51.688973 best dqsien dly found for B1: ( 1, 3, 26)
3496 22:12:51.692263 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3497 22:12:51.695593 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3498 22:12:51.695675
3499 22:12:51.702753 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3500 22:12:51.705764 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3501 22:12:51.709205 [Gating] SW calibration Done
3502 22:12:51.709287 ==
3503 22:12:51.712610 Dram Type= 6, Freq= 0, CH_1, rank 1
3504 22:12:51.715406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3505 22:12:51.715489 ==
3506 22:12:51.715554 RX Vref Scan: 0
3507 22:12:51.715616
3508 22:12:51.719852 RX Vref 0 -> 0, step: 1
3509 22:12:51.719936
3510 22:12:51.722078 RX Delay -40 -> 252, step: 8
3511 22:12:51.725776 iDelay=192, Bit 0, Center 115 (40 ~ 191) 152
3512 22:12:51.729603 iDelay=192, Bit 1, Center 111 (40 ~ 183) 144
3513 22:12:51.735653 iDelay=192, Bit 2, Center 103 (32 ~ 175) 144
3514 22:12:51.739621 iDelay=192, Bit 3, Center 115 (48 ~ 183) 136
3515 22:12:51.741976 iDelay=192, Bit 4, Center 111 (40 ~ 183) 144
3516 22:12:51.745604 iDelay=192, Bit 5, Center 123 (56 ~ 191) 136
3517 22:12:51.748664 iDelay=192, Bit 6, Center 119 (48 ~ 191) 144
3518 22:12:51.755443 iDelay=192, Bit 7, Center 111 (48 ~ 175) 128
3519 22:12:51.758790 iDelay=192, Bit 8, Center 103 (32 ~ 175) 144
3520 22:12:51.762144 iDelay=192, Bit 9, Center 95 (24 ~ 167) 144
3521 22:12:51.766209 iDelay=192, Bit 10, Center 111 (40 ~ 183) 144
3522 22:12:51.768430 iDelay=192, Bit 11, Center 103 (32 ~ 175) 144
3523 22:12:51.775038 iDelay=192, Bit 12, Center 115 (48 ~ 183) 136
3524 22:12:51.778648 iDelay=192, Bit 13, Center 119 (48 ~ 191) 144
3525 22:12:51.782429 iDelay=192, Bit 14, Center 119 (48 ~ 191) 144
3526 22:12:51.785486 iDelay=192, Bit 15, Center 119 (48 ~ 191) 144
3527 22:12:51.785569 ==
3528 22:12:51.788640 Dram Type= 6, Freq= 0, CH_1, rank 1
3529 22:12:51.795484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3530 22:12:51.795567 ==
3531 22:12:51.795634 DQS Delay:
3532 22:12:51.798679 DQS0 = 0, DQS1 = 0
3533 22:12:51.798761 DQM Delay:
3534 22:12:51.798827 DQM0 = 113, DQM1 = 110
3535 22:12:51.802360 DQ Delay:
3536 22:12:51.805272 DQ0 =115, DQ1 =111, DQ2 =103, DQ3 =115
3537 22:12:51.808761 DQ4 =111, DQ5 =123, DQ6 =119, DQ7 =111
3538 22:12:51.812142 DQ8 =103, DQ9 =95, DQ10 =111, DQ11 =103
3539 22:12:51.815149 DQ12 =115, DQ13 =119, DQ14 =119, DQ15 =119
3540 22:12:51.815232
3541 22:12:51.815297
3542 22:12:51.815356 ==
3543 22:12:51.818914 Dram Type= 6, Freq= 0, CH_1, rank 1
3544 22:12:51.822163 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3545 22:12:51.825553 ==
3546 22:12:51.825634
3547 22:12:51.825700
3548 22:12:51.825758 TX Vref Scan disable
3549 22:12:51.828393 == TX Byte 0 ==
3550 22:12:51.832553 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3551 22:12:51.835476 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3552 22:12:51.838147 == TX Byte 1 ==
3553 22:12:51.841588 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3554 22:12:51.845454 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3555 22:12:51.848716 ==
3556 22:12:51.848798 Dram Type= 6, Freq= 0, CH_1, rank 1
3557 22:12:51.855082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3558 22:12:51.855164 ==
3559 22:12:51.866338 TX Vref=22, minBit 1, minWin=25, winSum=418
3560 22:12:51.870357 TX Vref=24, minBit 0, minWin=26, winSum=420
3561 22:12:51.872925 TX Vref=26, minBit 1, minWin=25, winSum=424
3562 22:12:51.875949 TX Vref=28, minBit 3, minWin=26, winSum=429
3563 22:12:51.879397 TX Vref=30, minBit 15, minWin=25, winSum=428
3564 22:12:51.886233 TX Vref=32, minBit 15, minWin=25, winSum=430
3565 22:12:51.889645 [TxChooseVref] Worse bit 3, Min win 26, Win sum 429, Final Vref 28
3566 22:12:51.889728
3567 22:12:51.892997 Final TX Range 1 Vref 28
3568 22:12:51.893080
3569 22:12:51.893145 ==
3570 22:12:51.896781 Dram Type= 6, Freq= 0, CH_1, rank 1
3571 22:12:51.899514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3572 22:12:51.902412 ==
3573 22:12:51.902495
3574 22:12:51.902577
3575 22:12:51.902668 TX Vref Scan disable
3576 22:12:51.905943 == TX Byte 0 ==
3577 22:12:51.909764 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3578 22:12:51.915899 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3579 22:12:51.916017 == TX Byte 1 ==
3580 22:12:51.919467 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3581 22:12:51.926292 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3582 22:12:51.926376
3583 22:12:51.926442 [DATLAT]
3584 22:12:51.926503 Freq=1200, CH1 RK1
3585 22:12:51.926563
3586 22:12:51.929678 DATLAT Default: 0xd
3587 22:12:51.929760 0, 0xFFFF, sum = 0
3588 22:12:51.932818 1, 0xFFFF, sum = 0
3589 22:12:51.932901 2, 0xFFFF, sum = 0
3590 22:12:51.936386 3, 0xFFFF, sum = 0
3591 22:12:51.939630 4, 0xFFFF, sum = 0
3592 22:12:51.939713 5, 0xFFFF, sum = 0
3593 22:12:51.942823 6, 0xFFFF, sum = 0
3594 22:12:51.942906 7, 0xFFFF, sum = 0
3595 22:12:51.946208 8, 0xFFFF, sum = 0
3596 22:12:51.946291 9, 0xFFFF, sum = 0
3597 22:12:51.949249 10, 0xFFFF, sum = 0
3598 22:12:51.949332 11, 0xFFFF, sum = 0
3599 22:12:51.952397 12, 0x0, sum = 1
3600 22:12:51.952479 13, 0x0, sum = 2
3601 22:12:51.955783 14, 0x0, sum = 3
3602 22:12:51.955865 15, 0x0, sum = 4
3603 22:12:51.959208 best_step = 13
3604 22:12:51.959289
3605 22:12:51.959353 ==
3606 22:12:51.963184 Dram Type= 6, Freq= 0, CH_1, rank 1
3607 22:12:51.965947 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3608 22:12:51.966030 ==
3609 22:12:51.966096 RX Vref Scan: 0
3610 22:12:51.966157
3611 22:12:51.969093 RX Vref 0 -> 0, step: 1
3612 22:12:51.969175
3613 22:12:51.972456 RX Delay -21 -> 252, step: 4
3614 22:12:51.976095 iDelay=191, Bit 0, Center 114 (47 ~ 182) 136
3615 22:12:51.982684 iDelay=191, Bit 1, Center 108 (43 ~ 174) 132
3616 22:12:51.985681 iDelay=191, Bit 2, Center 106 (43 ~ 170) 128
3617 22:12:51.989857 iDelay=191, Bit 3, Center 112 (47 ~ 178) 132
3618 22:12:51.992291 iDelay=191, Bit 4, Center 114 (47 ~ 182) 136
3619 22:12:51.996013 iDelay=191, Bit 5, Center 124 (59 ~ 190) 132
3620 22:12:52.002833 iDelay=191, Bit 6, Center 120 (55 ~ 186) 132
3621 22:12:52.006091 iDelay=191, Bit 7, Center 110 (47 ~ 174) 128
3622 22:12:52.009254 iDelay=191, Bit 8, Center 98 (31 ~ 166) 136
3623 22:12:52.012805 iDelay=191, Bit 9, Center 98 (35 ~ 162) 128
3624 22:12:52.015914 iDelay=191, Bit 10, Center 110 (43 ~ 178) 136
3625 22:12:52.022421 iDelay=191, Bit 11, Center 102 (35 ~ 170) 136
3626 22:12:52.025626 iDelay=191, Bit 12, Center 114 (51 ~ 178) 128
3627 22:12:52.028815 iDelay=191, Bit 13, Center 120 (55 ~ 186) 132
3628 22:12:52.031922 iDelay=191, Bit 14, Center 118 (55 ~ 182) 128
3629 22:12:52.036269 iDelay=191, Bit 15, Center 120 (55 ~ 186) 132
3630 22:12:52.039503 ==
3631 22:12:52.042209 Dram Type= 6, Freq= 0, CH_1, rank 1
3632 22:12:52.045602 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3633 22:12:52.045685 ==
3634 22:12:52.045751 DQS Delay:
3635 22:12:52.048694 DQS0 = 0, DQS1 = 0
3636 22:12:52.048776 DQM Delay:
3637 22:12:52.052318 DQM0 = 113, DQM1 = 110
3638 22:12:52.052400 DQ Delay:
3639 22:12:52.055410 DQ0 =114, DQ1 =108, DQ2 =106, DQ3 =112
3640 22:12:52.058613 DQ4 =114, DQ5 =124, DQ6 =120, DQ7 =110
3641 22:12:52.061770 DQ8 =98, DQ9 =98, DQ10 =110, DQ11 =102
3642 22:12:52.065333 DQ12 =114, DQ13 =120, DQ14 =118, DQ15 =120
3643 22:12:52.065415
3644 22:12:52.065480
3645 22:12:52.075640 [DQSOSCAuto] RK1, (LSB)MR18= 0xf7fe, (MSB)MR19= 0x303, tDQSOscB0 = 410 ps tDQSOscB1 = 413 ps
3646 22:12:52.078534 CH1 RK1: MR19=303, MR18=F7FE
3647 22:12:52.082172 CH1_RK1: MR19=0x303, MR18=0xF7FE, DQSOSC=410, MR23=63, INC=39, DEC=26
3648 22:12:52.085223 [RxdqsGatingPostProcess] freq 1200
3649 22:12:52.092082 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3650 22:12:52.095120 best DQS0 dly(2T, 0.5T) = (0, 11)
3651 22:12:52.098341 best DQS1 dly(2T, 0.5T) = (0, 11)
3652 22:12:52.102331 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3653 22:12:52.105545 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3654 22:12:52.108962 best DQS0 dly(2T, 0.5T) = (0, 11)
3655 22:12:52.112163 best DQS1 dly(2T, 0.5T) = (0, 11)
3656 22:12:52.115414 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3657 22:12:52.118676 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3658 22:12:52.118759 Pre-setting of DQS Precalculation
3659 22:12:52.125501 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3660 22:12:52.131540 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3661 22:12:52.139003 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3662 22:12:52.139096
3663 22:12:52.139164
3664 22:12:52.141712 [Calibration Summary] 2400 Mbps
3665 22:12:52.145338 CH 0, Rank 0
3666 22:12:52.145421 SW Impedance : PASS
3667 22:12:52.148848 DUTY Scan : NO K
3668 22:12:52.151932 ZQ Calibration : PASS
3669 22:12:52.152055 Jitter Meter : NO K
3670 22:12:52.155049 CBT Training : PASS
3671 22:12:52.158274 Write leveling : PASS
3672 22:12:52.158356 RX DQS gating : PASS
3673 22:12:52.161890 RX DQ/DQS(RDDQC) : PASS
3674 22:12:52.161971 TX DQ/DQS : PASS
3675 22:12:52.165404 RX DATLAT : PASS
3676 22:12:52.168417 RX DQ/DQS(Engine): PASS
3677 22:12:52.168499 TX OE : NO K
3678 22:12:52.172064 All Pass.
3679 22:12:52.172145
3680 22:12:52.172210 CH 0, Rank 1
3681 22:12:52.175233 SW Impedance : PASS
3682 22:12:52.175314 DUTY Scan : NO K
3683 22:12:52.178356 ZQ Calibration : PASS
3684 22:12:52.182221 Jitter Meter : NO K
3685 22:12:52.182303 CBT Training : PASS
3686 22:12:52.185102 Write leveling : PASS
3687 22:12:52.188371 RX DQS gating : PASS
3688 22:12:52.188452 RX DQ/DQS(RDDQC) : PASS
3689 22:12:52.191790 TX DQ/DQS : PASS
3690 22:12:52.195402 RX DATLAT : PASS
3691 22:12:52.195484 RX DQ/DQS(Engine): PASS
3692 22:12:52.198402 TX OE : NO K
3693 22:12:52.198485 All Pass.
3694 22:12:52.198614
3695 22:12:52.201824 CH 1, Rank 0
3696 22:12:52.201923 SW Impedance : PASS
3697 22:12:52.204900 DUTY Scan : NO K
3698 22:12:52.208172 ZQ Calibration : PASS
3699 22:12:52.208253 Jitter Meter : NO K
3700 22:12:52.211826 CBT Training : PASS
3701 22:12:52.211951 Write leveling : PASS
3702 22:12:52.214923 RX DQS gating : PASS
3703 22:12:52.218350 RX DQ/DQS(RDDQC) : PASS
3704 22:12:52.218430 TX DQ/DQS : PASS
3705 22:12:52.222067 RX DATLAT : PASS
3706 22:12:52.225684 RX DQ/DQS(Engine): PASS
3707 22:12:52.225767 TX OE : NO K
3708 22:12:52.229033 All Pass.
3709 22:12:52.229114
3710 22:12:52.229180 CH 1, Rank 1
3711 22:12:52.231486 SW Impedance : PASS
3712 22:12:52.231566 DUTY Scan : NO K
3713 22:12:52.235211 ZQ Calibration : PASS
3714 22:12:52.238099 Jitter Meter : NO K
3715 22:12:52.238181 CBT Training : PASS
3716 22:12:52.241850 Write leveling : PASS
3717 22:12:52.244678 RX DQS gating : PASS
3718 22:12:52.244760 RX DQ/DQS(RDDQC) : PASS
3719 22:12:52.248459 TX DQ/DQS : PASS
3720 22:12:52.252114 RX DATLAT : PASS
3721 22:12:52.252197 RX DQ/DQS(Engine): PASS
3722 22:12:52.255397 TX OE : NO K
3723 22:12:52.255478 All Pass.
3724 22:12:52.255544
3725 22:12:52.257912 DramC Write-DBI off
3726 22:12:52.261741 PER_BANK_REFRESH: Hybrid Mode
3727 22:12:52.261823 TX_TRACKING: ON
3728 22:12:52.271208 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3729 22:12:52.274439 [FAST_K] Save calibration result to emmc
3730 22:12:52.278012 dramc_set_vcore_voltage set vcore to 650000
3731 22:12:52.281422 Read voltage for 600, 5
3732 22:12:52.281504 Vio18 = 0
3733 22:12:52.281570 Vcore = 650000
3734 22:12:52.284397 Vdram = 0
3735 22:12:52.284478 Vddq = 0
3736 22:12:52.284543 Vmddr = 0
3737 22:12:52.291144 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3738 22:12:52.294512 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3739 22:12:52.297733 MEM_TYPE=3, freq_sel=19
3740 22:12:52.301068 sv_algorithm_assistance_LP4_1600
3741 22:12:52.304554 ============ PULL DRAM RESETB DOWN ============
3742 22:12:52.307908 ========== PULL DRAM RESETB DOWN end =========
3743 22:12:52.314545 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3744 22:12:52.317779 ===================================
3745 22:12:52.317869 LPDDR4 DRAM CONFIGURATION
3746 22:12:52.320930 ===================================
3747 22:12:52.324202 EX_ROW_EN[0] = 0x0
3748 22:12:52.327788 EX_ROW_EN[1] = 0x0
3749 22:12:52.327922 LP4Y_EN = 0x0
3750 22:12:52.331413 WORK_FSP = 0x0
3751 22:12:52.331495 WL = 0x2
3752 22:12:52.334352 RL = 0x2
3753 22:12:52.334434 BL = 0x2
3754 22:12:52.337385 RPST = 0x0
3755 22:12:52.337466 RD_PRE = 0x0
3756 22:12:52.341163 WR_PRE = 0x1
3757 22:12:52.341245 WR_PST = 0x0
3758 22:12:52.344063 DBI_WR = 0x0
3759 22:12:52.344144 DBI_RD = 0x0
3760 22:12:52.347631 OTF = 0x1
3761 22:12:52.350668 ===================================
3762 22:12:52.353979 ===================================
3763 22:12:52.354062 ANA top config
3764 22:12:52.357430 ===================================
3765 22:12:52.361254 DLL_ASYNC_EN = 0
3766 22:12:52.363998 ALL_SLAVE_EN = 1
3767 22:12:52.367354 NEW_RANK_MODE = 1
3768 22:12:52.367437 DLL_IDLE_MODE = 1
3769 22:12:52.371263 LP45_APHY_COMB_EN = 1
3770 22:12:52.373951 TX_ODT_DIS = 1
3771 22:12:52.377755 NEW_8X_MODE = 1
3772 22:12:52.380495 ===================================
3773 22:12:52.384465 ===================================
3774 22:12:52.387323 data_rate = 1200
3775 22:12:52.387405 CKR = 1
3776 22:12:52.390513 DQ_P2S_RATIO = 8
3777 22:12:52.393809 ===================================
3778 22:12:52.397652 CA_P2S_RATIO = 8
3779 22:12:52.400543 DQ_CA_OPEN = 0
3780 22:12:52.404160 DQ_SEMI_OPEN = 0
3781 22:12:52.407681 CA_SEMI_OPEN = 0
3782 22:12:52.407767 CA_FULL_RATE = 0
3783 22:12:52.410277 DQ_CKDIV4_EN = 1
3784 22:12:52.413945 CA_CKDIV4_EN = 1
3785 22:12:52.417763 CA_PREDIV_EN = 0
3786 22:12:52.420890 PH8_DLY = 0
3787 22:12:52.423901 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3788 22:12:52.424036 DQ_AAMCK_DIV = 4
3789 22:12:52.426982 CA_AAMCK_DIV = 4
3790 22:12:52.431090 CA_ADMCK_DIV = 4
3791 22:12:52.434474 DQ_TRACK_CA_EN = 0
3792 22:12:52.436950 CA_PICK = 600
3793 22:12:52.440640 CA_MCKIO = 600
3794 22:12:52.440724 MCKIO_SEMI = 0
3795 22:12:52.444460 PLL_FREQ = 2288
3796 22:12:52.447056 DQ_UI_PI_RATIO = 32
3797 22:12:52.450904 CA_UI_PI_RATIO = 0
3798 22:12:52.454007 ===================================
3799 22:12:52.457320 ===================================
3800 22:12:52.460429 memory_type:LPDDR4
3801 22:12:52.460510 GP_NUM : 10
3802 22:12:52.463893 SRAM_EN : 1
3803 22:12:52.467636 MD32_EN : 0
3804 22:12:52.471033 ===================================
3805 22:12:52.471117 [ANA_INIT] >>>>>>>>>>>>>>
3806 22:12:52.473897 <<<<<< [CONFIGURE PHASE]: ANA_TX
3807 22:12:52.477055 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3808 22:12:52.480203 ===================================
3809 22:12:52.483883 data_rate = 1200,PCW = 0X5800
3810 22:12:52.487171 ===================================
3811 22:12:52.490450 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3812 22:12:52.496732 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3813 22:12:52.500397 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3814 22:12:52.506821 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3815 22:12:52.509795 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3816 22:12:52.513120 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3817 22:12:52.516616 [ANA_INIT] flow start
3818 22:12:52.516699 [ANA_INIT] PLL >>>>>>>>
3819 22:12:52.519947 [ANA_INIT] PLL <<<<<<<<
3820 22:12:52.523263 [ANA_INIT] MIDPI >>>>>>>>
3821 22:12:52.523346 [ANA_INIT] MIDPI <<<<<<<<
3822 22:12:52.527067 [ANA_INIT] DLL >>>>>>>>
3823 22:12:52.529927 [ANA_INIT] flow end
3824 22:12:52.533327 ============ LP4 DIFF to SE enter ============
3825 22:12:52.536454 ============ LP4 DIFF to SE exit ============
3826 22:12:52.539715 [ANA_INIT] <<<<<<<<<<<<<
3827 22:12:52.544269 [Flow] Enable top DCM control >>>>>
3828 22:12:52.546565 [Flow] Enable top DCM control <<<<<
3829 22:12:52.549624 Enable DLL master slave shuffle
3830 22:12:52.553508 ==============================================================
3831 22:12:52.556806 Gating Mode config
3832 22:12:52.563609 ==============================================================
3833 22:12:52.563694 Config description:
3834 22:12:52.573331 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3835 22:12:52.579874 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3836 22:12:52.583053 SELPH_MODE 0: By rank 1: By Phase
3837 22:12:52.589626 ==============================================================
3838 22:12:52.593690 GAT_TRACK_EN = 1
3839 22:12:52.596573 RX_GATING_MODE = 2
3840 22:12:52.599726 RX_GATING_TRACK_MODE = 2
3841 22:12:52.602909 SELPH_MODE = 1
3842 22:12:52.606587 PICG_EARLY_EN = 1
3843 22:12:52.606675 VALID_LAT_VALUE = 1
3844 22:12:52.612906 ==============================================================
3845 22:12:52.616554 Enter into Gating configuration >>>>
3846 22:12:52.619979 Exit from Gating configuration <<<<
3847 22:12:52.623339 Enter into DVFS_PRE_config >>>>>
3848 22:12:52.633458 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3849 22:12:52.636264 Exit from DVFS_PRE_config <<<<<
3850 22:12:52.639560 Enter into PICG configuration >>>>
3851 22:12:52.643558 Exit from PICG configuration <<<<
3852 22:12:52.646882 [RX_INPUT] configuration >>>>>
3853 22:12:52.649579 [RX_INPUT] configuration <<<<<
3854 22:12:52.656353 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3855 22:12:52.659882 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3856 22:12:52.666687 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3857 22:12:52.673011 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3858 22:12:52.679234 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3859 22:12:52.686191 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3860 22:12:52.689354 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3861 22:12:52.693284 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3862 22:12:52.695825 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3863 22:12:52.702987 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3864 22:12:52.706139 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3865 22:12:52.709657 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3866 22:12:52.713213 ===================================
3867 22:12:52.715920 LPDDR4 DRAM CONFIGURATION
3868 22:12:52.719583 ===================================
3869 22:12:52.719667 EX_ROW_EN[0] = 0x0
3870 22:12:52.722507 EX_ROW_EN[1] = 0x0
3871 22:12:52.722589 LP4Y_EN = 0x0
3872 22:12:52.726058 WORK_FSP = 0x0
3873 22:12:52.729091 WL = 0x2
3874 22:12:52.729209 RL = 0x2
3875 22:12:52.732012 BL = 0x2
3876 22:12:52.732108 RPST = 0x0
3877 22:12:52.735991 RD_PRE = 0x0
3878 22:12:52.736075 WR_PRE = 0x1
3879 22:12:52.738873 WR_PST = 0x0
3880 22:12:52.738955 DBI_WR = 0x0
3881 22:12:52.742255 DBI_RD = 0x0
3882 22:12:52.742339 OTF = 0x1
3883 22:12:52.745797 ===================================
3884 22:12:52.749094 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3885 22:12:52.755304 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3886 22:12:52.759823 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3887 22:12:52.762755 ===================================
3888 22:12:52.765415 LPDDR4 DRAM CONFIGURATION
3889 22:12:52.769020 ===================================
3890 22:12:52.769104 EX_ROW_EN[0] = 0x10
3891 22:12:52.772639 EX_ROW_EN[1] = 0x0
3892 22:12:52.772722 LP4Y_EN = 0x0
3893 22:12:52.775761 WORK_FSP = 0x0
3894 22:12:52.775844 WL = 0x2
3895 22:12:52.779069 RL = 0x2
3896 22:12:52.779152 BL = 0x2
3897 22:12:52.782368 RPST = 0x0
3898 22:12:52.785588 RD_PRE = 0x0
3899 22:12:52.785671 WR_PRE = 0x1
3900 22:12:52.789579 WR_PST = 0x0
3901 22:12:52.789663 DBI_WR = 0x0
3902 22:12:52.792248 DBI_RD = 0x0
3903 22:12:52.792333 OTF = 0x1
3904 22:12:52.796153 ===================================
3905 22:12:52.802433 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3906 22:12:52.805835 nWR fixed to 30
3907 22:12:52.809349 [ModeRegInit_LP4] CH0 RK0
3908 22:12:52.809437 [ModeRegInit_LP4] CH0 RK1
3909 22:12:52.812576 [ModeRegInit_LP4] CH1 RK0
3910 22:12:52.816561 [ModeRegInit_LP4] CH1 RK1
3911 22:12:52.816645 match AC timing 17
3912 22:12:52.823286 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3913 22:12:52.826181 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3914 22:12:52.829296 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3915 22:12:52.836226 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3916 22:12:52.839234 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3917 22:12:52.839377 ==
3918 22:12:52.842405 Dram Type= 6, Freq= 0, CH_0, rank 0
3919 22:12:52.845558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3920 22:12:52.845642 ==
3921 22:12:52.853006 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3922 22:12:52.859485 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3923 22:12:52.862729 [CA 0] Center 36 (6~67) winsize 62
3924 22:12:52.865813 [CA 1] Center 36 (6~66) winsize 61
3925 22:12:52.869064 [CA 2] Center 34 (4~65) winsize 62
3926 22:12:52.872532 [CA 3] Center 34 (4~64) winsize 61
3927 22:12:52.875432 [CA 4] Center 33 (3~64) winsize 62
3928 22:12:52.878910 [CA 5] Center 33 (3~64) winsize 62
3929 22:12:52.878993
3930 22:12:52.882358 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3931 22:12:52.882441
3932 22:12:52.885500 [CATrainingPosCal] consider 1 rank data
3933 22:12:52.888715 u2DelayCellTimex100 = 270/100 ps
3934 22:12:52.891931 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3935 22:12:52.895786 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3936 22:12:52.898850 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3937 22:12:52.902055 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
3938 22:12:52.906043 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3939 22:12:52.911800 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3940 22:12:52.911931
3941 22:12:52.916091 CA PerBit enable=1, Macro0, CA PI delay=33
3942 22:12:52.916217
3943 22:12:52.919316 [CBTSetCACLKResult] CA Dly = 33
3944 22:12:52.919398 CS Dly: 4 (0~35)
3945 22:12:52.919465 ==
3946 22:12:52.922646 Dram Type= 6, Freq= 0, CH_0, rank 1
3947 22:12:52.925864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3948 22:12:52.925947 ==
3949 22:12:52.932862 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3950 22:12:52.938905 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3951 22:12:52.942587 [CA 0] Center 36 (6~66) winsize 61
3952 22:12:52.945339 [CA 1] Center 36 (6~66) winsize 61
3953 22:12:52.948975 [CA 2] Center 35 (5~65) winsize 61
3954 22:12:52.951834 [CA 3] Center 34 (4~65) winsize 62
3955 22:12:52.955688 [CA 4] Center 33 (3~64) winsize 62
3956 22:12:52.958870 [CA 5] Center 33 (3~64) winsize 62
3957 22:12:52.958954
3958 22:12:52.962286 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3959 22:12:52.962370
3960 22:12:52.965303 [CATrainingPosCal] consider 2 rank data
3961 22:12:52.968675 u2DelayCellTimex100 = 270/100 ps
3962 22:12:52.972450 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3963 22:12:52.975113 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3964 22:12:52.978782 CA2 delay=35 (5~65),Diff = 2 PI (19 cell)
3965 22:12:52.982742 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
3966 22:12:52.988595 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3967 22:12:52.991818 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3968 22:12:52.991901
3969 22:12:52.995294 CA PerBit enable=1, Macro0, CA PI delay=33
3970 22:12:52.995377
3971 22:12:52.998799 [CBTSetCACLKResult] CA Dly = 33
3972 22:12:52.998906 CS Dly: 4 (0~36)
3973 22:12:52.999003
3974 22:12:53.002239 ----->DramcWriteLeveling(PI) begin...
3975 22:12:53.002324 ==
3976 22:12:53.005165 Dram Type= 6, Freq= 0, CH_0, rank 0
3977 22:12:53.011799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3978 22:12:53.011932 ==
3979 22:12:53.015308 Write leveling (Byte 0): 30 => 30
3980 22:12:53.018418 Write leveling (Byte 1): 31 => 31
3981 22:12:53.018528 DramcWriteLeveling(PI) end<-----
3982 22:12:53.018649
3983 22:12:53.021810 ==
3984 22:12:53.024928 Dram Type= 6, Freq= 0, CH_0, rank 0
3985 22:12:53.028202 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3986 22:12:53.028311 ==
3987 22:12:53.031669 [Gating] SW mode calibration
3988 22:12:53.037990 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3989 22:12:53.041282 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3990 22:12:53.048224 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3991 22:12:53.051340 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3992 22:12:53.054450 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3993 22:12:53.061316 0 9 12 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
3994 22:12:53.064694 0 9 16 | B1->B0 | 3131 2e2e | 0 0 | (0 0) (0 0)
3995 22:12:53.068680 0 9 20 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
3996 22:12:53.074548 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3997 22:12:53.078062 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3998 22:12:53.080987 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3999 22:12:53.088098 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4000 22:12:53.091846 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4001 22:12:53.094276 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4002 22:12:53.101009 0 10 16 | B1->B0 | 2f2f 3b3b | 0 0 | (0 0) (0 0)
4003 22:12:53.104495 0 10 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4004 22:12:53.107831 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4005 22:12:53.114149 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4006 22:12:53.118040 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4007 22:12:53.120842 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4008 22:12:53.128077 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4009 22:12:53.131567 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4010 22:12:53.134413 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4011 22:12:53.140973 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4012 22:12:53.144480 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4013 22:12:53.147621 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4014 22:12:53.151156 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4015 22:12:53.157662 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4016 22:12:53.160773 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4017 22:12:53.164459 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4018 22:12:53.171086 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4019 22:12:53.174274 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4020 22:12:53.177389 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4021 22:12:53.184245 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4022 22:12:53.187887 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4023 22:12:53.190665 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4024 22:12:53.197724 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4025 22:12:53.200580 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4026 22:12:53.204657 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4027 22:12:53.207434 Total UI for P1: 0, mck2ui 16
4028 22:12:53.210656 best dqsien dly found for B0: ( 0, 13, 12)
4029 22:12:53.217325 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4030 22:12:53.217420 Total UI for P1: 0, mck2ui 16
4031 22:12:53.223903 best dqsien dly found for B1: ( 0, 13, 16)
4032 22:12:53.227126 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4033 22:12:53.230817 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4034 22:12:53.230904
4035 22:12:53.234022 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4036 22:12:53.237293 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4037 22:12:53.240633 [Gating] SW calibration Done
4038 22:12:53.240718 ==
4039 22:12:53.244670 Dram Type= 6, Freq= 0, CH_0, rank 0
4040 22:12:53.247512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4041 22:12:53.247597 ==
4042 22:12:53.251024 RX Vref Scan: 0
4043 22:12:53.251110
4044 22:12:53.251177 RX Vref 0 -> 0, step: 1
4045 22:12:53.251240
4046 22:12:53.253992 RX Delay -230 -> 252, step: 16
4047 22:12:53.260995 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4048 22:12:53.264555 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4049 22:12:53.267452 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4050 22:12:53.271308 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4051 22:12:53.273945 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4052 22:12:53.281886 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4053 22:12:53.283654 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4054 22:12:53.287129 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4055 22:12:53.291134 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4056 22:12:53.297009 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4057 22:12:53.300432 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4058 22:12:53.304838 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4059 22:12:53.307348 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4060 22:12:53.313989 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4061 22:12:53.316995 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4062 22:12:53.320576 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4063 22:12:53.320664 ==
4064 22:12:53.323872 Dram Type= 6, Freq= 0, CH_0, rank 0
4065 22:12:53.326772 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4066 22:12:53.326856 ==
4067 22:12:53.329991 DQS Delay:
4068 22:12:53.330077 DQS0 = 0, DQS1 = 0
4069 22:12:53.333578 DQM Delay:
4070 22:12:53.333662 DQM0 = 40, DQM1 = 33
4071 22:12:53.333729 DQ Delay:
4072 22:12:53.336849 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4073 22:12:53.340696 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4074 22:12:53.343812 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =25
4075 22:12:53.346862 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =41
4076 22:12:53.346949
4077 22:12:53.347017
4078 22:12:53.350287 ==
4079 22:12:53.350371 Dram Type= 6, Freq= 0, CH_0, rank 0
4080 22:12:53.357073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4081 22:12:53.357231 ==
4082 22:12:53.357358
4083 22:12:53.357449
4084 22:12:53.360269 TX Vref Scan disable
4085 22:12:53.360394 == TX Byte 0 ==
4086 22:12:53.363225 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4087 22:12:53.370031 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4088 22:12:53.370126 == TX Byte 1 ==
4089 22:12:53.373705 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4090 22:12:53.380559 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4091 22:12:53.380686 ==
4092 22:12:53.383442 Dram Type= 6, Freq= 0, CH_0, rank 0
4093 22:12:53.386690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4094 22:12:53.386778 ==
4095 22:12:53.386847
4096 22:12:53.386909
4097 22:12:53.390287 TX Vref Scan disable
4098 22:12:53.393692 == TX Byte 0 ==
4099 22:12:53.396712 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4100 22:12:53.399813 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4101 22:12:53.403914 == TX Byte 1 ==
4102 22:12:53.406826 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4103 22:12:53.410061 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4104 22:12:53.410148
4105 22:12:53.413708 [DATLAT]
4106 22:12:53.413791 Freq=600, CH0 RK0
4107 22:12:53.413858
4108 22:12:53.416500 DATLAT Default: 0x9
4109 22:12:53.416583 0, 0xFFFF, sum = 0
4110 22:12:53.420586 1, 0xFFFF, sum = 0
4111 22:12:53.420671 2, 0xFFFF, sum = 0
4112 22:12:53.422914 3, 0xFFFF, sum = 0
4113 22:12:53.422999 4, 0xFFFF, sum = 0
4114 22:12:53.426924 5, 0xFFFF, sum = 0
4115 22:12:53.427008 6, 0xFFFF, sum = 0
4116 22:12:53.429821 7, 0xFFFF, sum = 0
4117 22:12:53.429906 8, 0x0, sum = 1
4118 22:12:53.433485 9, 0x0, sum = 2
4119 22:12:53.433570 10, 0x0, sum = 3
4120 22:12:53.436645 11, 0x0, sum = 4
4121 22:12:53.436730 best_step = 9
4122 22:12:53.436796
4123 22:12:53.436858 ==
4124 22:12:53.439982 Dram Type= 6, Freq= 0, CH_0, rank 0
4125 22:12:53.442775 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4126 22:12:53.446503 ==
4127 22:12:53.446587 RX Vref Scan: 1
4128 22:12:53.446654
4129 22:12:53.449916 RX Vref 0 -> 0, step: 1
4130 22:12:53.450000
4131 22:12:53.452747 RX Delay -179 -> 252, step: 8
4132 22:12:53.452830
4133 22:12:53.456265 Set Vref, RX VrefLevel [Byte0]: 52
4134 22:12:53.459659 [Byte1]: 50
4135 22:12:53.459747
4136 22:12:53.462791 Final RX Vref Byte 0 = 52 to rank0
4137 22:12:53.465916 Final RX Vref Byte 1 = 50 to rank0
4138 22:12:53.469289 Final RX Vref Byte 0 = 52 to rank1
4139 22:12:53.472855 Final RX Vref Byte 1 = 50 to rank1==
4140 22:12:53.476049 Dram Type= 6, Freq= 0, CH_0, rank 0
4141 22:12:53.479473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4142 22:12:53.479563 ==
4143 22:12:53.483379 DQS Delay:
4144 22:12:53.483464 DQS0 = 0, DQS1 = 0
4145 22:12:53.483531 DQM Delay:
4146 22:12:53.486229 DQM0 = 42, DQM1 = 33
4147 22:12:53.486312 DQ Delay:
4148 22:12:53.489030 DQ0 =44, DQ1 =40, DQ2 =36, DQ3 =40
4149 22:12:53.492554 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =48
4150 22:12:53.496450 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =28
4151 22:12:53.499484 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44
4152 22:12:53.499577
4153 22:12:53.499646
4154 22:12:53.509398 [DQSOSCAuto] RK0, (LSB)MR18= 0x401d, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 397 ps
4155 22:12:53.509520 CH0 RK0: MR19=808, MR18=401D
4156 22:12:53.515704 CH0_RK0: MR19=0x808, MR18=0x401D, DQSOSC=397, MR23=63, INC=166, DEC=110
4157 22:12:53.515816
4158 22:12:53.518789 ----->DramcWriteLeveling(PI) begin...
4159 22:12:53.522234 ==
4160 22:12:53.525433 Dram Type= 6, Freq= 0, CH_0, rank 1
4161 22:12:53.529594 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4162 22:12:53.529680 ==
4163 22:12:53.532487 Write leveling (Byte 0): 31 => 31
4164 22:12:53.535395 Write leveling (Byte 1): 31 => 31
4165 22:12:53.538999 DramcWriteLeveling(PI) end<-----
4166 22:12:53.539082
4167 22:12:53.539149 ==
4168 22:12:53.542810 Dram Type= 6, Freq= 0, CH_0, rank 1
4169 22:12:53.545731 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4170 22:12:53.545815 ==
4171 22:12:53.549718 [Gating] SW mode calibration
4172 22:12:53.555570 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4173 22:12:53.559158 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4174 22:12:53.566338 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4175 22:12:53.569022 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4176 22:12:53.572359 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4177 22:12:53.579262 0 9 12 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
4178 22:12:53.582665 0 9 16 | B1->B0 | 3030 2323 | 0 0 | (1 0) (0 0)
4179 22:12:53.585647 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
4180 22:12:53.592273 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4181 22:12:53.595565 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4182 22:12:53.599048 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4183 22:12:53.605347 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4184 22:12:53.608992 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4185 22:12:53.612077 0 10 12 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
4186 22:12:53.618869 0 10 16 | B1->B0 | 3838 4646 | 1 0 | (0 0) (0 0)
4187 22:12:53.622053 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4188 22:12:53.625146 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4189 22:12:53.632296 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4190 22:12:53.635395 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4191 22:12:53.638675 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4192 22:12:53.645120 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4193 22:12:53.648815 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4194 22:12:53.652277 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4195 22:12:53.658642 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4196 22:12:53.661996 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4197 22:12:53.665225 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4198 22:12:53.672053 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4199 22:12:53.675434 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4200 22:12:53.678716 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4201 22:12:53.685188 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4202 22:12:53.688346 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4203 22:12:53.691936 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4204 22:12:53.695274 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4205 22:12:53.701588 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4206 22:12:53.705204 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4207 22:12:53.708202 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4208 22:12:53.715103 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4209 22:12:53.718446 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4210 22:12:53.722102 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4211 22:12:53.725232 Total UI for P1: 0, mck2ui 16
4212 22:12:53.728298 best dqsien dly found for B0: ( 0, 13, 10)
4213 22:12:53.734658 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4214 22:12:53.738488 Total UI for P1: 0, mck2ui 16
4215 22:12:53.741769 best dqsien dly found for B1: ( 0, 13, 16)
4216 22:12:53.744849 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4217 22:12:53.748394 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4218 22:12:53.748466
4219 22:12:53.752095 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4220 22:12:53.754564 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4221 22:12:53.758553 [Gating] SW calibration Done
4222 22:12:53.758652 ==
4223 22:12:53.761441 Dram Type= 6, Freq= 0, CH_0, rank 1
4224 22:12:53.765049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4225 22:12:53.765148 ==
4226 22:12:53.768134 RX Vref Scan: 0
4227 22:12:53.768203
4228 22:12:53.771560 RX Vref 0 -> 0, step: 1
4229 22:12:53.771653
4230 22:12:53.771742 RX Delay -230 -> 252, step: 16
4231 22:12:53.777850 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4232 22:12:53.781178 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4233 22:12:53.784322 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4234 22:12:53.787711 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4235 22:12:53.794283 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4236 22:12:53.797717 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4237 22:12:53.801218 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4238 22:12:53.804574 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4239 22:12:53.807778 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4240 22:12:53.814718 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4241 22:12:53.817649 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4242 22:12:53.821572 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4243 22:12:53.824543 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4244 22:12:53.830967 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4245 22:12:53.834088 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4246 22:12:53.837296 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4247 22:12:53.837406 ==
4248 22:12:53.841219 Dram Type= 6, Freq= 0, CH_0, rank 1
4249 22:12:53.844870 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4250 22:12:53.847765 ==
4251 22:12:53.847870 DQS Delay:
4252 22:12:53.848000 DQS0 = 0, DQS1 = 0
4253 22:12:53.851032 DQM Delay:
4254 22:12:53.851127 DQM0 = 39, DQM1 = 31
4255 22:12:53.854121 DQ Delay:
4256 22:12:53.857598 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4257 22:12:53.857673 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4258 22:12:53.860733 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4259 22:12:53.867604 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =41
4260 22:12:53.867702
4261 22:12:53.867793
4262 22:12:53.867891 ==
4263 22:12:53.871153 Dram Type= 6, Freq= 0, CH_0, rank 1
4264 22:12:53.874053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4265 22:12:53.874156 ==
4266 22:12:53.874246
4267 22:12:53.874343
4268 22:12:53.877564 TX Vref Scan disable
4269 22:12:53.877635 == TX Byte 0 ==
4270 22:12:53.884303 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4271 22:12:53.887174 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4272 22:12:53.887281 == TX Byte 1 ==
4273 22:12:53.894157 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4274 22:12:53.897517 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4275 22:12:53.897621 ==
4276 22:12:53.900819 Dram Type= 6, Freq= 0, CH_0, rank 1
4277 22:12:53.904212 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4278 22:12:53.904292 ==
4279 22:12:53.904387
4280 22:12:53.904485
4281 22:12:53.907804 TX Vref Scan disable
4282 22:12:53.911665 == TX Byte 0 ==
4283 22:12:53.914209 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4284 22:12:53.917073 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4285 22:12:53.921515 == TX Byte 1 ==
4286 22:12:53.923668 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4287 22:12:53.927504 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4288 22:12:53.927587
4289 22:12:53.930966 [DATLAT]
4290 22:12:53.931048 Freq=600, CH0 RK1
4291 22:12:53.931114
4292 22:12:53.933948 DATLAT Default: 0x9
4293 22:12:53.934029 0, 0xFFFF, sum = 0
4294 22:12:53.937424 1, 0xFFFF, sum = 0
4295 22:12:53.937507 2, 0xFFFF, sum = 0
4296 22:12:53.940843 3, 0xFFFF, sum = 0
4297 22:12:53.940926 4, 0xFFFF, sum = 0
4298 22:12:53.943903 5, 0xFFFF, sum = 0
4299 22:12:53.944006 6, 0xFFFF, sum = 0
4300 22:12:53.947490 7, 0xFFFF, sum = 0
4301 22:12:53.947572 8, 0x0, sum = 1
4302 22:12:53.950383 9, 0x0, sum = 2
4303 22:12:53.950465 10, 0x0, sum = 3
4304 22:12:53.953985 11, 0x0, sum = 4
4305 22:12:53.954067 best_step = 9
4306 22:12:53.954131
4307 22:12:53.954190 ==
4308 22:12:53.957278 Dram Type= 6, Freq= 0, CH_0, rank 1
4309 22:12:53.963834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4310 22:12:53.963941 ==
4311 22:12:53.964018 RX Vref Scan: 0
4312 22:12:53.964080
4313 22:12:53.967841 RX Vref 0 -> 0, step: 1
4314 22:12:53.967921
4315 22:12:53.970355 RX Delay -195 -> 252, step: 8
4316 22:12:53.973742 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4317 22:12:53.980424 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4318 22:12:53.983968 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4319 22:12:53.987032 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4320 22:12:53.990536 iDelay=205, Bit 4, Center 36 (-115 ~ 188) 304
4321 22:12:53.993688 iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304
4322 22:12:54.000237 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4323 22:12:54.003381 iDelay=205, Bit 7, Center 44 (-107 ~ 196) 304
4324 22:12:54.006915 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4325 22:12:54.010386 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4326 22:12:54.016947 iDelay=205, Bit 10, Center 36 (-115 ~ 188) 304
4327 22:12:54.020132 iDelay=205, Bit 11, Center 24 (-123 ~ 172) 296
4328 22:12:54.024071 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4329 22:12:54.026947 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4330 22:12:54.033753 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4331 22:12:54.037277 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4332 22:12:54.037358 ==
4333 22:12:54.040187 Dram Type= 6, Freq= 0, CH_0, rank 1
4334 22:12:54.043860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4335 22:12:54.043942 ==
4336 22:12:54.046744 DQS Delay:
4337 22:12:54.046824 DQS0 = 0, DQS1 = 0
4338 22:12:54.046887 DQM Delay:
4339 22:12:54.049899 DQM0 = 39, DQM1 = 33
4340 22:12:54.049979 DQ Delay:
4341 22:12:54.053586 DQ0 =40, DQ1 =40, DQ2 =36, DQ3 =40
4342 22:12:54.056538 DQ4 =36, DQ5 =28, DQ6 =48, DQ7 =44
4343 22:12:54.060468 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =24
4344 22:12:54.063442 DQ12 =36, DQ13 =40, DQ14 =44, DQ15 =40
4345 22:12:54.063522
4346 22:12:54.063586
4347 22:12:54.073363 [DQSOSCAuto] RK1, (LSB)MR18= 0x4729, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 396 ps
4348 22:12:54.073446 CH0 RK1: MR19=808, MR18=4729
4349 22:12:54.080904 CH0_RK1: MR19=0x808, MR18=0x4729, DQSOSC=396, MR23=63, INC=167, DEC=111
4350 22:12:54.083398 [RxdqsGatingPostProcess] freq 600
4351 22:12:54.090476 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4352 22:12:54.093405 Pre-setting of DQS Precalculation
4353 22:12:54.097091 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4354 22:12:54.097174 ==
4355 22:12:54.100192 Dram Type= 6, Freq= 0, CH_1, rank 0
4356 22:12:54.103403 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4357 22:12:54.106674 ==
4358 22:12:54.110168 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4359 22:12:54.116613 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4360 22:12:54.120208 [CA 0] Center 35 (5~66) winsize 62
4361 22:12:54.123687 [CA 1] Center 35 (5~66) winsize 62
4362 22:12:54.126649 [CA 2] Center 34 (3~65) winsize 63
4363 22:12:54.130770 [CA 3] Center 33 (3~64) winsize 62
4364 22:12:54.133387 [CA 4] Center 34 (3~65) winsize 63
4365 22:12:54.138027 [CA 5] Center 33 (2~64) winsize 63
4366 22:12:54.138110
4367 22:12:54.140232 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4368 22:12:54.140315
4369 22:12:54.143567 [CATrainingPosCal] consider 1 rank data
4370 22:12:54.146769 u2DelayCellTimex100 = 270/100 ps
4371 22:12:54.149955 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4372 22:12:54.153152 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4373 22:12:54.156765 CA2 delay=34 (3~65),Diff = 1 PI (9 cell)
4374 22:12:54.160063 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4375 22:12:54.166511 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4376 22:12:54.169874 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4377 22:12:54.169957
4378 22:12:54.173685 CA PerBit enable=1, Macro0, CA PI delay=33
4379 22:12:54.173768
4380 22:12:54.176899 [CBTSetCACLKResult] CA Dly = 33
4381 22:12:54.176982 CS Dly: 6 (0~37)
4382 22:12:54.177049 ==
4383 22:12:54.179669 Dram Type= 6, Freq= 0, CH_1, rank 1
4384 22:12:54.186808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4385 22:12:54.186893 ==
4386 22:12:54.190983 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4387 22:12:54.196415 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4388 22:12:54.199769 [CA 0] Center 35 (5~66) winsize 62
4389 22:12:54.203368 [CA 1] Center 36 (6~66) winsize 61
4390 22:12:54.206538 [CA 2] Center 34 (4~65) winsize 62
4391 22:12:54.210243 [CA 3] Center 34 (3~65) winsize 63
4392 22:12:54.213328 [CA 4] Center 34 (3~65) winsize 63
4393 22:12:54.216479 [CA 5] Center 33 (3~64) winsize 62
4394 22:12:54.216563
4395 22:12:54.219656 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4396 22:12:54.219740
4397 22:12:54.223170 [CATrainingPosCal] consider 2 rank data
4398 22:12:54.226288 u2DelayCellTimex100 = 270/100 ps
4399 22:12:54.229366 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4400 22:12:54.232948 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4401 22:12:54.239702 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4402 22:12:54.243146 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4403 22:12:54.246555 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4404 22:12:54.249892 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4405 22:12:54.249976
4406 22:12:54.253213 CA PerBit enable=1, Macro0, CA PI delay=33
4407 22:12:54.253296
4408 22:12:54.256108 [CBTSetCACLKResult] CA Dly = 33
4409 22:12:54.256192 CS Dly: 5 (0~36)
4410 22:12:54.256258
4411 22:12:54.259121 ----->DramcWriteLeveling(PI) begin...
4412 22:12:54.262955 ==
4413 22:12:54.265874 Dram Type= 6, Freq= 0, CH_1, rank 0
4414 22:12:54.269291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4415 22:12:54.269375 ==
4416 22:12:54.272611 Write leveling (Byte 0): 28 => 28
4417 22:12:54.275782 Write leveling (Byte 1): 32 => 32
4418 22:12:54.279296 DramcWriteLeveling(PI) end<-----
4419 22:12:54.279411
4420 22:12:54.279478 ==
4421 22:12:54.282527 Dram Type= 6, Freq= 0, CH_1, rank 0
4422 22:12:54.286330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4423 22:12:54.286413 ==
4424 22:12:54.289142 [Gating] SW mode calibration
4425 22:12:54.295621 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4426 22:12:54.302953 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4427 22:12:54.305914 0 9 0 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
4428 22:12:54.308994 0 9 4 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
4429 22:12:54.312954 0 9 8 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
4430 22:12:54.319189 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4431 22:12:54.322490 0 9 16 | B1->B0 | 2a2a 2626 | 0 0 | (1 1) (0 0)
4432 22:12:54.325875 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4433 22:12:54.332518 0 9 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4434 22:12:54.335925 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4435 22:12:54.339600 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4436 22:12:54.346184 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4437 22:12:54.349162 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4438 22:12:54.352492 0 10 12 | B1->B0 | 2626 2c2c | 1 0 | (0 0) (0 0)
4439 22:12:54.359090 0 10 16 | B1->B0 | 3c3c 4141 | 0 0 | (0 0) (0 0)
4440 22:12:54.362298 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4441 22:12:54.365689 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4442 22:12:54.372302 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4443 22:12:54.375322 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4444 22:12:54.378877 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4445 22:12:54.385303 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4446 22:12:54.388701 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4447 22:12:54.391872 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4448 22:12:54.398943 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4449 22:12:54.402432 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4450 22:12:54.405695 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4451 22:12:54.412130 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4452 22:12:54.415661 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4453 22:12:54.418931 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4454 22:12:54.425576 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4455 22:12:54.428995 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4456 22:12:54.432095 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4457 22:12:54.438561 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4458 22:12:54.442462 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4459 22:12:54.445555 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4460 22:12:54.448587 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4461 22:12:54.455385 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4462 22:12:54.458429 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4463 22:12:54.461904 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4464 22:12:54.465295 Total UI for P1: 0, mck2ui 16
4465 22:12:54.468384 best dqsien dly found for B0: ( 0, 13, 12)
4466 22:12:54.471672 Total UI for P1: 0, mck2ui 16
4467 22:12:54.475304 best dqsien dly found for B1: ( 0, 13, 14)
4468 22:12:54.478346 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4469 22:12:54.484897 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4470 22:12:54.484982
4471 22:12:54.488270 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4472 22:12:54.491554 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4473 22:12:54.495066 [Gating] SW calibration Done
4474 22:12:54.495170 ==
4475 22:12:54.498838 Dram Type= 6, Freq= 0, CH_1, rank 0
4476 22:12:54.501768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4477 22:12:54.501842 ==
4478 22:12:54.505317 RX Vref Scan: 0
4479 22:12:54.505389
4480 22:12:54.505458 RX Vref 0 -> 0, step: 1
4481 22:12:54.505518
4482 22:12:54.508570 RX Delay -230 -> 252, step: 16
4483 22:12:54.511708 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4484 22:12:54.518729 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4485 22:12:54.521749 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4486 22:12:54.524965 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4487 22:12:54.528475 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4488 22:12:54.531989 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4489 22:12:54.538514 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4490 22:12:54.542031 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4491 22:12:54.545178 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4492 22:12:54.548925 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4493 22:12:54.554917 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4494 22:12:54.558171 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4495 22:12:54.561519 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4496 22:12:54.565550 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4497 22:12:54.571420 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4498 22:12:54.574867 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4499 22:12:54.574944 ==
4500 22:12:54.578105 Dram Type= 6, Freq= 0, CH_1, rank 0
4501 22:12:54.581557 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4502 22:12:54.581635 ==
4503 22:12:54.584996 DQS Delay:
4504 22:12:54.585071 DQS0 = 0, DQS1 = 0
4505 22:12:54.585134 DQM Delay:
4506 22:12:54.587981 DQM0 = 44, DQM1 = 35
4507 22:12:54.588064 DQ Delay:
4508 22:12:54.591147 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4509 22:12:54.594743 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4510 22:12:54.597827 DQ8 =17, DQ9 =17, DQ10 =41, DQ11 =33
4511 22:12:54.600839 DQ12 =49, DQ13 =41, DQ14 =41, DQ15 =41
4512 22:12:54.600911
4513 22:12:54.600974
4514 22:12:54.601032 ==
4515 22:12:54.604943 Dram Type= 6, Freq= 0, CH_1, rank 0
4516 22:12:54.610966 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4517 22:12:54.611051 ==
4518 22:12:54.611121
4519 22:12:54.611182
4520 22:12:54.611240 TX Vref Scan disable
4521 22:12:54.614820 == TX Byte 0 ==
4522 22:12:54.617804 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4523 22:12:54.624582 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4524 22:12:54.624677 == TX Byte 1 ==
4525 22:12:54.627933 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4526 22:12:54.634819 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4527 22:12:54.634899 ==
4528 22:12:54.637712 Dram Type= 6, Freq= 0, CH_1, rank 0
4529 22:12:54.641434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4530 22:12:54.641510 ==
4531 22:12:54.641576
4532 22:12:54.641641
4533 22:12:54.644548 TX Vref Scan disable
4534 22:12:54.647605 == TX Byte 0 ==
4535 22:12:54.650960 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4536 22:12:54.654490 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4537 22:12:54.657921 == TX Byte 1 ==
4538 22:12:54.661135 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4539 22:12:54.664876 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4540 22:12:54.664958
4541 22:12:54.665022 [DATLAT]
4542 22:12:54.667637 Freq=600, CH1 RK0
4543 22:12:54.667706
4544 22:12:54.671015 DATLAT Default: 0x9
4545 22:12:54.671090 0, 0xFFFF, sum = 0
4546 22:12:54.674281 1, 0xFFFF, sum = 0
4547 22:12:54.674354 2, 0xFFFF, sum = 0
4548 22:12:54.677647 3, 0xFFFF, sum = 0
4549 22:12:54.677766 4, 0xFFFF, sum = 0
4550 22:12:54.681101 5, 0xFFFF, sum = 0
4551 22:12:54.681174 6, 0xFFFF, sum = 0
4552 22:12:54.684640 7, 0xFFFF, sum = 0
4553 22:12:54.684735 8, 0x0, sum = 1
4554 22:12:54.687686 9, 0x0, sum = 2
4555 22:12:54.687759 10, 0x0, sum = 3
4556 22:12:54.687821 11, 0x0, sum = 4
4557 22:12:54.691256 best_step = 9
4558 22:12:54.691324
4559 22:12:54.691383 ==
4560 22:12:54.694502 Dram Type= 6, Freq= 0, CH_1, rank 0
4561 22:12:54.697634 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4562 22:12:54.697704 ==
4563 22:12:54.701086 RX Vref Scan: 1
4564 22:12:54.701158
4565 22:12:54.701219 RX Vref 0 -> 0, step: 1
4566 22:12:54.704021
4567 22:12:54.704093 RX Delay -195 -> 252, step: 8
4568 22:12:54.704153
4569 22:12:54.707960 Set Vref, RX VrefLevel [Byte0]: 60
4570 22:12:54.711139 [Byte1]: 54
4571 22:12:54.715772
4572 22:12:54.715848 Final RX Vref Byte 0 = 60 to rank0
4573 22:12:54.718804 Final RX Vref Byte 1 = 54 to rank0
4574 22:12:54.721986 Final RX Vref Byte 0 = 60 to rank1
4575 22:12:54.725345 Final RX Vref Byte 1 = 54 to rank1==
4576 22:12:54.728529 Dram Type= 6, Freq= 0, CH_1, rank 0
4577 22:12:54.735302 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4578 22:12:54.735379 ==
4579 22:12:54.735447 DQS Delay:
4580 22:12:54.735507 DQS0 = 0, DQS1 = 0
4581 22:12:54.738294 DQM Delay:
4582 22:12:54.738366 DQM0 = 40, DQM1 = 33
4583 22:12:54.741748 DQ Delay:
4584 22:12:54.744930 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =40
4585 22:12:54.748292 DQ4 =36, DQ5 =48, DQ6 =52, DQ7 =36
4586 22:12:54.751944 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =32
4587 22:12:54.755061 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4588 22:12:54.755140
4589 22:12:54.755203
4590 22:12:54.761506 [DQSOSCAuto] RK0, (LSB)MR18= 0x3e04, (MSB)MR19= 0x808, tDQSOscB0 = 409 ps tDQSOscB1 = 398 ps
4591 22:12:54.765090 CH1 RK0: MR19=808, MR18=3E04
4592 22:12:54.771579 CH1_RK0: MR19=0x808, MR18=0x3E04, DQSOSC=398, MR23=63, INC=165, DEC=110
4593 22:12:54.771661
4594 22:12:54.775741 ----->DramcWriteLeveling(PI) begin...
4595 22:12:54.775844 ==
4596 22:12:54.778074 Dram Type= 6, Freq= 0, CH_1, rank 1
4597 22:12:54.781481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4598 22:12:54.781569 ==
4599 22:12:54.784836 Write leveling (Byte 0): 29 => 29
4600 22:12:54.788417 Write leveling (Byte 1): 29 => 29
4601 22:12:54.791428 DramcWriteLeveling(PI) end<-----
4602 22:12:54.791502
4603 22:12:54.791565 ==
4604 22:12:54.795106 Dram Type= 6, Freq= 0, CH_1, rank 1
4605 22:12:54.798567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4606 22:12:54.798640 ==
4607 22:12:54.801607 [Gating] SW mode calibration
4608 22:12:54.808332 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4609 22:12:54.815425 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4610 22:12:54.818054 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4611 22:12:54.825112 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4612 22:12:54.828289 0 9 8 | B1->B0 | 3535 3434 | 0 0 | (0 0) (0 0)
4613 22:12:54.831479 0 9 12 | B1->B0 | 2f2f 2b2b | 1 0 | (1 1) (0 0)
4614 22:12:54.835039 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4615 22:12:54.841713 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4616 22:12:54.844685 0 9 24 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
4617 22:12:54.848048 0 9 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4618 22:12:54.854914 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4619 22:12:54.858604 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4620 22:12:54.861553 0 10 8 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
4621 22:12:54.867831 0 10 12 | B1->B0 | 3030 3a3a | 0 0 | (0 0) (1 1)
4622 22:12:54.871429 0 10 16 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
4623 22:12:54.874500 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4624 22:12:54.881586 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4625 22:12:54.884543 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4626 22:12:54.887762 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4627 22:12:54.894444 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4628 22:12:54.898006 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4629 22:12:54.901240 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4630 22:12:54.907870 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4631 22:12:54.911272 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4632 22:12:54.914733 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4633 22:12:54.921033 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4634 22:12:54.924663 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4635 22:12:54.928048 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4636 22:12:54.934522 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4637 22:12:54.937521 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4638 22:12:54.940944 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4639 22:12:54.947641 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4640 22:12:54.951026 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4641 22:12:54.954784 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4642 22:12:54.961353 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4643 22:12:54.964428 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4644 22:12:54.967881 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4645 22:12:54.974257 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4646 22:12:54.974373 Total UI for P1: 0, mck2ui 16
4647 22:12:54.977289 best dqsien dly found for B0: ( 0, 13, 8)
4648 22:12:54.984076 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4649 22:12:54.987893 Total UI for P1: 0, mck2ui 16
4650 22:12:54.991033 best dqsien dly found for B1: ( 0, 13, 12)
4651 22:12:54.994201 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4652 22:12:54.997285 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4653 22:12:54.997368
4654 22:12:55.000564 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4655 22:12:55.004532 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4656 22:12:55.007786 [Gating] SW calibration Done
4657 22:12:55.007872 ==
4658 22:12:55.010414 Dram Type= 6, Freq= 0, CH_1, rank 1
4659 22:12:55.013689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4660 22:12:55.013780 ==
4661 22:12:55.017586 RX Vref Scan: 0
4662 22:12:55.017669
4663 22:12:55.020741 RX Vref 0 -> 0, step: 1
4664 22:12:55.020824
4665 22:12:55.020891 RX Delay -230 -> 252, step: 16
4666 22:12:55.027399 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4667 22:12:55.030722 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4668 22:12:55.033932 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4669 22:12:55.037446 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4670 22:12:55.043756 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4671 22:12:55.047154 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4672 22:12:55.050866 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4673 22:12:55.053936 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4674 22:12:55.057616 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4675 22:12:55.063909 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4676 22:12:55.067282 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4677 22:12:55.070299 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4678 22:12:55.073879 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4679 22:12:55.080237 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4680 22:12:55.083751 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4681 22:12:55.087234 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4682 22:12:55.087323 ==
4683 22:12:55.090130 Dram Type= 6, Freq= 0, CH_1, rank 1
4684 22:12:55.093482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4685 22:12:55.097423 ==
4686 22:12:55.097508 DQS Delay:
4687 22:12:55.097575 DQS0 = 0, DQS1 = 0
4688 22:12:55.100184 DQM Delay:
4689 22:12:55.100314 DQM0 = 43, DQM1 = 38
4690 22:12:55.103593 DQ Delay:
4691 22:12:55.107267 DQ0 =41, DQ1 =41, DQ2 =25, DQ3 =41
4692 22:12:55.107359 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4693 22:12:55.110190 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4694 22:12:55.113716 DQ12 =41, DQ13 =49, DQ14 =49, DQ15 =41
4695 22:12:55.117020
4696 22:12:55.117107
4697 22:12:55.117203 ==
4698 22:12:55.120535 Dram Type= 6, Freq= 0, CH_1, rank 1
4699 22:12:55.123491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4700 22:12:55.123591 ==
4701 22:12:55.123658
4702 22:12:55.123719
4703 22:12:55.126946 TX Vref Scan disable
4704 22:12:55.127030 == TX Byte 0 ==
4705 22:12:55.133486 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4706 22:12:55.136921 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4707 22:12:55.137026 == TX Byte 1 ==
4708 22:12:55.143710 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4709 22:12:55.147012 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4710 22:12:55.147099 ==
4711 22:12:55.150306 Dram Type= 6, Freq= 0, CH_1, rank 1
4712 22:12:55.153702 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4713 22:12:55.153788 ==
4714 22:12:55.153855
4715 22:12:55.153918
4716 22:12:55.156803 TX Vref Scan disable
4717 22:12:55.159790 == TX Byte 0 ==
4718 22:12:55.163436 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4719 22:12:55.166844 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4720 22:12:55.169791 == TX Byte 1 ==
4721 22:12:55.173421 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4722 22:12:55.176555 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4723 22:12:55.179760
4724 22:12:55.179842 [DATLAT]
4725 22:12:55.179907 Freq=600, CH1 RK1
4726 22:12:55.179995
4727 22:12:55.182879 DATLAT Default: 0x9
4728 22:12:55.182962 0, 0xFFFF, sum = 0
4729 22:12:55.186300 1, 0xFFFF, sum = 0
4730 22:12:55.186415 2, 0xFFFF, sum = 0
4731 22:12:55.189780 3, 0xFFFF, sum = 0
4732 22:12:55.189863 4, 0xFFFF, sum = 0
4733 22:12:55.192928 5, 0xFFFF, sum = 0
4734 22:12:55.197006 6, 0xFFFF, sum = 0
4735 22:12:55.197092 7, 0xFFFF, sum = 0
4736 22:12:55.197159 8, 0x0, sum = 1
4737 22:12:55.199621 9, 0x0, sum = 2
4738 22:12:55.199705 10, 0x0, sum = 3
4739 22:12:55.203549 11, 0x0, sum = 4
4740 22:12:55.203633 best_step = 9
4741 22:12:55.203698
4742 22:12:55.203759 ==
4743 22:12:55.206075 Dram Type= 6, Freq= 0, CH_1, rank 1
4744 22:12:55.213020 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4745 22:12:55.213126 ==
4746 22:12:55.213194 RX Vref Scan: 0
4747 22:12:55.213256
4748 22:12:55.215942 RX Vref 0 -> 0, step: 1
4749 22:12:55.216070
4750 22:12:55.219350 RX Delay -179 -> 252, step: 8
4751 22:12:55.223040 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4752 22:12:55.229221 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4753 22:12:55.232987 iDelay=205, Bit 2, Center 28 (-123 ~ 180) 304
4754 22:12:55.236437 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4755 22:12:55.239204 iDelay=205, Bit 4, Center 36 (-115 ~ 188) 304
4756 22:12:55.245952 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4757 22:12:55.249558 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4758 22:12:55.252554 iDelay=205, Bit 7, Center 32 (-115 ~ 180) 296
4759 22:12:55.255888 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4760 22:12:55.259401 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4761 22:12:55.266572 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4762 22:12:55.269326 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4763 22:12:55.272668 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4764 22:12:55.275854 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4765 22:12:55.282929 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4766 22:12:55.285960 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4767 22:12:55.286049 ==
4768 22:12:55.288777 Dram Type= 6, Freq= 0, CH_1, rank 1
4769 22:12:55.292245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4770 22:12:55.292335 ==
4771 22:12:55.295453 DQS Delay:
4772 22:12:55.295537 DQS0 = 0, DQS1 = 0
4773 22:12:55.295605 DQM Delay:
4774 22:12:55.298959 DQM0 = 37, DQM1 = 32
4775 22:12:55.299044 DQ Delay:
4776 22:12:55.302432 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =36
4777 22:12:55.305515 DQ4 =36, DQ5 =48, DQ6 =48, DQ7 =32
4778 22:12:55.308893 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =24
4779 22:12:55.312582 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4780 22:12:55.312669
4781 22:12:55.312754
4782 22:12:55.321964 [DQSOSCAuto] RK1, (LSB)MR18= 0x3342, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 400 ps
4783 22:12:55.325299 CH1 RK1: MR19=808, MR18=3342
4784 22:12:55.328561 CH1_RK1: MR19=0x808, MR18=0x3342, DQSOSC=397, MR23=63, INC=166, DEC=110
4785 22:12:55.331864 [RxdqsGatingPostProcess] freq 600
4786 22:12:55.338447 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4787 22:12:55.342189 Pre-setting of DQS Precalculation
4788 22:12:55.345352 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4789 22:12:55.355291 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4790 22:12:55.361806 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4791 22:12:55.361893
4792 22:12:55.361976
4793 22:12:55.364989 [Calibration Summary] 1200 Mbps
4794 22:12:55.365065 CH 0, Rank 0
4795 22:12:55.368599 SW Impedance : PASS
4796 22:12:55.368675 DUTY Scan : NO K
4797 22:12:55.371825 ZQ Calibration : PASS
4798 22:12:55.375731 Jitter Meter : NO K
4799 22:12:55.375808 CBT Training : PASS
4800 22:12:55.378534 Write leveling : PASS
4801 22:12:55.381891 RX DQS gating : PASS
4802 22:12:55.381970 RX DQ/DQS(RDDQC) : PASS
4803 22:12:55.385707 TX DQ/DQS : PASS
4804 22:12:55.388717 RX DATLAT : PASS
4805 22:12:55.388794 RX DQ/DQS(Engine): PASS
4806 22:12:55.391778 TX OE : NO K
4807 22:12:55.391888 All Pass.
4808 22:12:55.391994
4809 22:12:55.395365 CH 0, Rank 1
4810 22:12:55.395446 SW Impedance : PASS
4811 22:12:55.398688 DUTY Scan : NO K
4812 22:12:55.398767 ZQ Calibration : PASS
4813 22:12:55.402108 Jitter Meter : NO K
4814 22:12:55.405272 CBT Training : PASS
4815 22:12:55.405351 Write leveling : PASS
4816 22:12:55.409156 RX DQS gating : PASS
4817 22:12:55.412146 RX DQ/DQS(RDDQC) : PASS
4818 22:12:55.412230 TX DQ/DQS : PASS
4819 22:12:55.415582 RX DATLAT : PASS
4820 22:12:55.419072 RX DQ/DQS(Engine): PASS
4821 22:12:55.419153 TX OE : NO K
4822 22:12:55.421766 All Pass.
4823 22:12:55.421843
4824 22:12:55.421927 CH 1, Rank 0
4825 22:12:55.424955 SW Impedance : PASS
4826 22:12:55.425038 DUTY Scan : NO K
4827 22:12:55.428533 ZQ Calibration : PASS
4828 22:12:55.431816 Jitter Meter : NO K
4829 22:12:55.431939 CBT Training : PASS
4830 22:12:55.435034 Write leveling : PASS
4831 22:12:55.438612 RX DQS gating : PASS
4832 22:12:55.438689 RX DQ/DQS(RDDQC) : PASS
4833 22:12:55.441789 TX DQ/DQS : PASS
4834 22:12:55.441869 RX DATLAT : PASS
4835 22:12:55.444869 RX DQ/DQS(Engine): PASS
4836 22:12:55.448257 TX OE : NO K
4837 22:12:55.448338 All Pass.
4838 22:12:55.448419
4839 22:12:55.448500 CH 1, Rank 1
4840 22:12:55.451837 SW Impedance : PASS
4841 22:12:55.454854 DUTY Scan : NO K
4842 22:12:55.454945 ZQ Calibration : PASS
4843 22:12:55.458167 Jitter Meter : NO K
4844 22:12:55.462088 CBT Training : PASS
4845 22:12:55.462181 Write leveling : PASS
4846 22:12:55.464995 RX DQS gating : PASS
4847 22:12:55.468279 RX DQ/DQS(RDDQC) : PASS
4848 22:12:55.468362 TX DQ/DQS : PASS
4849 22:12:55.471554 RX DATLAT : PASS
4850 22:12:55.474799 RX DQ/DQS(Engine): PASS
4851 22:12:55.474881 TX OE : NO K
4852 22:12:55.477837 All Pass.
4853 22:12:55.477915
4854 22:12:55.478002 DramC Write-DBI off
4855 22:12:55.481381 PER_BANK_REFRESH: Hybrid Mode
4856 22:12:55.481462 TX_TRACKING: ON
4857 22:12:55.492082 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4858 22:12:55.494816 [FAST_K] Save calibration result to emmc
4859 22:12:55.498553 dramc_set_vcore_voltage set vcore to 662500
4860 22:12:55.501454 Read voltage for 933, 3
4861 22:12:55.501536 Vio18 = 0
4862 22:12:55.504933 Vcore = 662500
4863 22:12:55.505035 Vdram = 0
4864 22:12:55.505131 Vddq = 0
4865 22:12:55.505220 Vmddr = 0
4866 22:12:55.511357 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4867 22:12:55.518176 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4868 22:12:55.518318 MEM_TYPE=3, freq_sel=17
4869 22:12:55.521594 sv_algorithm_assistance_LP4_1600
4870 22:12:55.525293 ============ PULL DRAM RESETB DOWN ============
4871 22:12:55.531180 ========== PULL DRAM RESETB DOWN end =========
4872 22:12:55.534840 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4873 22:12:55.537899 ===================================
4874 22:12:55.541737 LPDDR4 DRAM CONFIGURATION
4875 22:12:55.545064 ===================================
4876 22:12:55.545174 EX_ROW_EN[0] = 0x0
4877 22:12:55.548377 EX_ROW_EN[1] = 0x0
4878 22:12:55.548456 LP4Y_EN = 0x0
4879 22:12:55.551659 WORK_FSP = 0x0
4880 22:12:55.551762 WL = 0x3
4881 22:12:55.554516 RL = 0x3
4882 22:12:55.554614 BL = 0x2
4883 22:12:55.557913 RPST = 0x0
4884 22:12:55.561550 RD_PRE = 0x0
4885 22:12:55.561627 WR_PRE = 0x1
4886 22:12:55.564754 WR_PST = 0x0
4887 22:12:55.564828 DBI_WR = 0x0
4888 22:12:55.568313 DBI_RD = 0x0
4889 22:12:55.568413 OTF = 0x1
4890 22:12:55.571795 ===================================
4891 22:12:55.574861 ===================================
4892 22:12:55.574936 ANA top config
4893 22:12:55.578138 ===================================
4894 22:12:55.581321 DLL_ASYNC_EN = 0
4895 22:12:55.584747 ALL_SLAVE_EN = 1
4896 22:12:55.588284 NEW_RANK_MODE = 1
4897 22:12:55.591689 DLL_IDLE_MODE = 1
4898 22:12:55.591792 LP45_APHY_COMB_EN = 1
4899 22:12:55.594396 TX_ODT_DIS = 1
4900 22:12:55.597683 NEW_8X_MODE = 1
4901 22:12:55.600954 ===================================
4902 22:12:55.604363 ===================================
4903 22:12:55.608129 data_rate = 1866
4904 22:12:55.610973 CKR = 1
4905 22:12:55.611084 DQ_P2S_RATIO = 8
4906 22:12:55.614315 ===================================
4907 22:12:55.617848 CA_P2S_RATIO = 8
4908 22:12:55.621139 DQ_CA_OPEN = 0
4909 22:12:55.624673 DQ_SEMI_OPEN = 0
4910 22:12:55.628365 CA_SEMI_OPEN = 0
4911 22:12:55.631414 CA_FULL_RATE = 0
4912 22:12:55.631489 DQ_CKDIV4_EN = 1
4913 22:12:55.635177 CA_CKDIV4_EN = 1
4914 22:12:55.637943 CA_PREDIV_EN = 0
4915 22:12:55.641026 PH8_DLY = 0
4916 22:12:55.644310 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4917 22:12:55.647732 DQ_AAMCK_DIV = 4
4918 22:12:55.647853 CA_AAMCK_DIV = 4
4919 22:12:55.651203 CA_ADMCK_DIV = 4
4920 22:12:55.654657 DQ_TRACK_CA_EN = 0
4921 22:12:55.657819 CA_PICK = 933
4922 22:12:55.661061 CA_MCKIO = 933
4923 22:12:55.664346 MCKIO_SEMI = 0
4924 22:12:55.667759 PLL_FREQ = 3732
4925 22:12:55.667883 DQ_UI_PI_RATIO = 32
4926 22:12:55.671131 CA_UI_PI_RATIO = 0
4927 22:12:55.674670 ===================================
4928 22:12:55.677460 ===================================
4929 22:12:55.680929 memory_type:LPDDR4
4930 22:12:55.684459 GP_NUM : 10
4931 22:12:55.684594 SRAM_EN : 1
4932 22:12:55.687735 MD32_EN : 0
4933 22:12:55.691229 ===================================
4934 22:12:55.693862 [ANA_INIT] >>>>>>>>>>>>>>
4935 22:12:55.693971 <<<<<< [CONFIGURE PHASE]: ANA_TX
4936 22:12:55.697855 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4937 22:12:55.700464 ===================================
4938 22:12:55.704209 data_rate = 1866,PCW = 0X8f00
4939 22:12:55.707860 ===================================
4940 22:12:55.710885 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4941 22:12:55.717913 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4942 22:12:55.724086 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4943 22:12:55.727098 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4944 22:12:55.730932 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4945 22:12:55.733814 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4946 22:12:55.737402 [ANA_INIT] flow start
4947 22:12:55.737480 [ANA_INIT] PLL >>>>>>>>
4948 22:12:55.740487 [ANA_INIT] PLL <<<<<<<<
4949 22:12:55.743840 [ANA_INIT] MIDPI >>>>>>>>
4950 22:12:55.746953 [ANA_INIT] MIDPI <<<<<<<<
4951 22:12:55.747073 [ANA_INIT] DLL >>>>>>>>
4952 22:12:55.750926 [ANA_INIT] flow end
4953 22:12:55.754030 ============ LP4 DIFF to SE enter ============
4954 22:12:55.757063 ============ LP4 DIFF to SE exit ============
4955 22:12:55.760287 [ANA_INIT] <<<<<<<<<<<<<
4956 22:12:55.763524 [Flow] Enable top DCM control >>>>>
4957 22:12:55.767280 [Flow] Enable top DCM control <<<<<
4958 22:12:55.770684 Enable DLL master slave shuffle
4959 22:12:55.777187 ==============================================================
4960 22:12:55.777266 Gating Mode config
4961 22:12:55.783470 ==============================================================
4962 22:12:55.783558 Config description:
4963 22:12:55.793790 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4964 22:12:55.800207 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4965 22:12:55.806569 SELPH_MODE 0: By rank 1: By Phase
4966 22:12:55.810375 ==============================================================
4967 22:12:55.813466 GAT_TRACK_EN = 1
4968 22:12:55.816641 RX_GATING_MODE = 2
4969 22:12:55.820329 RX_GATING_TRACK_MODE = 2
4970 22:12:55.823655 SELPH_MODE = 1
4971 22:12:55.826387 PICG_EARLY_EN = 1
4972 22:12:55.830233 VALID_LAT_VALUE = 1
4973 22:12:55.833431 ==============================================================
4974 22:12:55.836958 Enter into Gating configuration >>>>
4975 22:12:55.839898 Exit from Gating configuration <<<<
4976 22:12:55.843406 Enter into DVFS_PRE_config >>>>>
4977 22:12:55.856787 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4978 22:12:55.859810 Exit from DVFS_PRE_config <<<<<
4979 22:12:55.863347 Enter into PICG configuration >>>>
4980 22:12:55.866295 Exit from PICG configuration <<<<
4981 22:12:55.866381 [RX_INPUT] configuration >>>>>
4982 22:12:55.870277 [RX_INPUT] configuration <<<<<
4983 22:12:55.876580 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4984 22:12:55.879720 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4985 22:12:55.886590 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4986 22:12:55.892902 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4987 22:12:55.899687 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4988 22:12:55.906128 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4989 22:12:55.909640 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4990 22:12:55.912888 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4991 22:12:55.916947 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4992 22:12:55.922835 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4993 22:12:55.926138 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4994 22:12:55.929443 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4995 22:12:55.933413 ===================================
4996 22:12:55.936545 LPDDR4 DRAM CONFIGURATION
4997 22:12:55.939835 ===================================
4998 22:12:55.943153 EX_ROW_EN[0] = 0x0
4999 22:12:55.943250 EX_ROW_EN[1] = 0x0
5000 22:12:55.946370 LP4Y_EN = 0x0
5001 22:12:55.946451 WORK_FSP = 0x0
5002 22:12:55.949949 WL = 0x3
5003 22:12:55.950052 RL = 0x3
5004 22:12:55.952841 BL = 0x2
5005 22:12:55.952947 RPST = 0x0
5006 22:12:55.956864 RD_PRE = 0x0
5007 22:12:55.956977 WR_PRE = 0x1
5008 22:12:55.959213 WR_PST = 0x0
5009 22:12:55.959302 DBI_WR = 0x0
5010 22:12:55.962506 DBI_RD = 0x0
5011 22:12:55.962591 OTF = 0x1
5012 22:12:55.965909 ===================================
5013 22:12:55.972609 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5014 22:12:55.976164 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5015 22:12:55.979232 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5016 22:12:55.982512 ===================================
5017 22:12:55.985751 LPDDR4 DRAM CONFIGURATION
5018 22:12:55.989630 ===================================
5019 22:12:55.992639 EX_ROW_EN[0] = 0x10
5020 22:12:55.992724 EX_ROW_EN[1] = 0x0
5021 22:12:55.995729 LP4Y_EN = 0x0
5022 22:12:55.995813 WORK_FSP = 0x0
5023 22:12:55.999071 WL = 0x3
5024 22:12:55.999155 RL = 0x3
5025 22:12:56.003062 BL = 0x2
5026 22:12:56.003172 RPST = 0x0
5027 22:12:56.006446 RD_PRE = 0x0
5028 22:12:56.006538 WR_PRE = 0x1
5029 22:12:56.009086 WR_PST = 0x0
5030 22:12:56.009173 DBI_WR = 0x0
5031 22:12:56.012793 DBI_RD = 0x0
5032 22:12:56.012913 OTF = 0x1
5033 22:12:56.015697 ===================================
5034 22:12:56.022580 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5035 22:12:56.027129 nWR fixed to 30
5036 22:12:56.030958 [ModeRegInit_LP4] CH0 RK0
5037 22:12:56.031044 [ModeRegInit_LP4] CH0 RK1
5038 22:12:56.033761 [ModeRegInit_LP4] CH1 RK0
5039 22:12:56.037589 [ModeRegInit_LP4] CH1 RK1
5040 22:12:56.037682 match AC timing 9
5041 22:12:56.044194 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5042 22:12:56.047089 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5043 22:12:56.050244 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5044 22:12:56.056722 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5045 22:12:56.060674 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5046 22:12:56.060760 ==
5047 22:12:56.063486 Dram Type= 6, Freq= 0, CH_0, rank 0
5048 22:12:56.066916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5049 22:12:56.067001 ==
5050 22:12:56.073996 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5051 22:12:56.080513 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5052 22:12:56.083283 [CA 0] Center 38 (8~69) winsize 62
5053 22:12:56.086583 [CA 1] Center 38 (7~69) winsize 63
5054 22:12:56.089910 [CA 2] Center 35 (5~66) winsize 62
5055 22:12:56.093794 [CA 3] Center 35 (5~65) winsize 61
5056 22:12:56.096730 [CA 4] Center 34 (4~65) winsize 62
5057 22:12:56.100418 [CA 5] Center 33 (3~64) winsize 62
5058 22:12:56.100493
5059 22:12:56.103235 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5060 22:12:56.103337
5061 22:12:56.107221 [CATrainingPosCal] consider 1 rank data
5062 22:12:56.110179 u2DelayCellTimex100 = 270/100 ps
5063 22:12:56.113514 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5064 22:12:56.116677 CA1 delay=38 (7~69),Diff = 5 PI (31 cell)
5065 22:12:56.120011 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5066 22:12:56.123309 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5067 22:12:56.126589 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5068 22:12:56.130765 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5069 22:12:56.133757
5070 22:12:56.137451 CA PerBit enable=1, Macro0, CA PI delay=33
5071 22:12:56.137559
5072 22:12:56.140107 [CBTSetCACLKResult] CA Dly = 33
5073 22:12:56.140187 CS Dly: 6 (0~37)
5074 22:12:56.140252 ==
5075 22:12:56.143685 Dram Type= 6, Freq= 0, CH_0, rank 1
5076 22:12:56.146897 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5077 22:12:56.147009 ==
5078 22:12:56.153614 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5079 22:12:56.160029 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5080 22:12:56.163244 [CA 0] Center 38 (7~69) winsize 63
5081 22:12:56.166963 [CA 1] Center 38 (7~69) winsize 63
5082 22:12:56.169749 [CA 2] Center 35 (5~66) winsize 62
5083 22:12:56.173642 [CA 3] Center 35 (4~66) winsize 63
5084 22:12:56.176744 [CA 4] Center 33 (3~64) winsize 62
5085 22:12:56.179744 [CA 5] Center 33 (3~64) winsize 62
5086 22:12:56.179847
5087 22:12:56.183108 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5088 22:12:56.183213
5089 22:12:56.186258 [CATrainingPosCal] consider 2 rank data
5090 22:12:56.189779 u2DelayCellTimex100 = 270/100 ps
5091 22:12:56.193709 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5092 22:12:56.196886 CA1 delay=38 (7~69),Diff = 5 PI (31 cell)
5093 22:12:56.199864 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5094 22:12:56.202972 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5095 22:12:56.209973 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5096 22:12:56.213598 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5097 22:12:56.213681
5098 22:12:56.216888 CA PerBit enable=1, Macro0, CA PI delay=33
5099 22:12:56.217002
5100 22:12:56.220276 [CBTSetCACLKResult] CA Dly = 33
5101 22:12:56.220369 CS Dly: 7 (0~39)
5102 22:12:56.220454
5103 22:12:56.222896 ----->DramcWriteLeveling(PI) begin...
5104 22:12:56.223004 ==
5105 22:12:56.226949 Dram Type= 6, Freq= 0, CH_0, rank 0
5106 22:12:56.233216 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5107 22:12:56.233304 ==
5108 22:12:56.236642 Write leveling (Byte 0): 32 => 32
5109 22:12:56.236746 Write leveling (Byte 1): 27 => 27
5110 22:12:56.239666 DramcWriteLeveling(PI) end<-----
5111 22:12:56.239766
5112 22:12:56.243145 ==
5113 22:12:56.243246 Dram Type= 6, Freq= 0, CH_0, rank 0
5114 22:12:56.249790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5115 22:12:56.249875 ==
5116 22:12:56.253260 [Gating] SW mode calibration
5117 22:12:56.259473 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5118 22:12:56.262822 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5119 22:12:56.269518 0 14 0 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
5120 22:12:56.272696 0 14 4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
5121 22:12:56.276435 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5122 22:12:56.282723 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5123 22:12:56.286602 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5124 22:12:56.289669 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5125 22:12:56.296023 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5126 22:12:56.299368 0 14 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5127 22:12:56.302741 0 15 0 | B1->B0 | 3030 2727 | 1 0 | (1 1) (0 0)
5128 22:12:56.309601 0 15 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5129 22:12:56.313029 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5130 22:12:56.316364 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5131 22:12:56.322784 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5132 22:12:56.325934 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5133 22:12:56.329126 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5134 22:12:56.332819 0 15 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5135 22:12:56.339339 1 0 0 | B1->B0 | 3030 3d3d | 0 0 | (0 0) (0 0)
5136 22:12:56.342851 1 0 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5137 22:12:56.346212 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5138 22:12:56.352397 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5139 22:12:56.355611 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5140 22:12:56.358918 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5141 22:12:56.365708 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5142 22:12:56.369224 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5143 22:12:56.372620 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5144 22:12:56.379125 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5145 22:12:56.382844 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5146 22:12:56.386209 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5147 22:12:56.392434 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5148 22:12:56.395539 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5149 22:12:56.398743 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5150 22:12:56.405533 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5151 22:12:56.408696 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5152 22:12:56.412299 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5153 22:12:56.418768 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5154 22:12:56.422664 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5155 22:12:56.425670 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5156 22:12:56.432986 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5157 22:12:56.435679 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5158 22:12:56.439223 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5159 22:12:56.445635 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5160 22:12:56.448543 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5161 22:12:56.451715 Total UI for P1: 0, mck2ui 16
5162 22:12:56.454905 best dqsien dly found for B0: ( 1, 3, 0)
5163 22:12:56.458397 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5164 22:12:56.461759 Total UI for P1: 0, mck2ui 16
5165 22:12:56.465055 best dqsien dly found for B1: ( 1, 3, 2)
5166 22:12:56.468087 best DQS0 dly(MCK, UI, PI) = (1, 3, 0)
5167 22:12:56.471699 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5168 22:12:56.471796
5169 22:12:56.478391 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 0)
5170 22:12:56.481540 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5171 22:12:56.481613 [Gating] SW calibration Done
5172 22:12:56.481677 ==
5173 22:12:56.485616 Dram Type= 6, Freq= 0, CH_0, rank 0
5174 22:12:56.491483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5175 22:12:56.491560 ==
5176 22:12:56.491625 RX Vref Scan: 0
5177 22:12:56.491686
5178 22:12:56.494840 RX Vref 0 -> 0, step: 1
5179 22:12:56.494935
5180 22:12:56.498414 RX Delay -80 -> 252, step: 8
5181 22:12:56.502023 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5182 22:12:56.504919 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5183 22:12:56.508513 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5184 22:12:56.511276 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5185 22:12:56.519091 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5186 22:12:56.521557 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5187 22:12:56.524790 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5188 22:12:56.528400 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5189 22:12:56.531572 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5190 22:12:56.535336 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5191 22:12:56.541890 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5192 22:12:56.545038 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5193 22:12:56.548262 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5194 22:12:56.551245 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5195 22:12:56.554964 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5196 22:12:56.561350 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5197 22:12:56.561515 ==
5198 22:12:56.565127 Dram Type= 6, Freq= 0, CH_0, rank 0
5199 22:12:56.567739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5200 22:12:56.567846 ==
5201 22:12:56.567996 DQS Delay:
5202 22:12:56.571414 DQS0 = 0, DQS1 = 0
5203 22:12:56.571523 DQM Delay:
5204 22:12:56.574458 DQM0 = 98, DQM1 = 87
5205 22:12:56.574573 DQ Delay:
5206 22:12:56.578120 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =95
5207 22:12:56.581692 DQ4 =99, DQ5 =87, DQ6 =111, DQ7 =103
5208 22:12:56.584445 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =79
5209 22:12:56.587904 DQ12 =91, DQ13 =95, DQ14 =95, DQ15 =95
5210 22:12:56.588042
5211 22:12:56.588137
5212 22:12:56.588225 ==
5213 22:12:56.591248 Dram Type= 6, Freq= 0, CH_0, rank 0
5214 22:12:56.594673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5215 22:12:56.594779 ==
5216 22:12:56.594859
5217 22:12:56.598349
5218 22:12:56.598449 TX Vref Scan disable
5219 22:12:56.601676 == TX Byte 0 ==
5220 22:12:56.604455 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5221 22:12:56.608114 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5222 22:12:56.611064 == TX Byte 1 ==
5223 22:12:56.614507 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5224 22:12:56.617571 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5225 22:12:56.617648 ==
5226 22:12:56.620973 Dram Type= 6, Freq= 0, CH_0, rank 0
5227 22:12:56.627683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5228 22:12:56.627762 ==
5229 22:12:56.627828
5230 22:12:56.627897
5231 22:12:56.627996 TX Vref Scan disable
5232 22:12:56.632257 == TX Byte 0 ==
5233 22:12:56.635157 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5234 22:12:56.642557 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5235 22:12:56.642648 == TX Byte 1 ==
5236 22:12:56.645361 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5237 22:12:56.648969 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5238 22:12:56.652331
5239 22:12:56.652411 [DATLAT]
5240 22:12:56.652479 Freq=933, CH0 RK0
5241 22:12:56.652543
5242 22:12:56.655302 DATLAT Default: 0xd
5243 22:12:56.655383 0, 0xFFFF, sum = 0
5244 22:12:56.659439 1, 0xFFFF, sum = 0
5245 22:12:56.659523 2, 0xFFFF, sum = 0
5246 22:12:56.662289 3, 0xFFFF, sum = 0
5247 22:12:56.665642 4, 0xFFFF, sum = 0
5248 22:12:56.665753 5, 0xFFFF, sum = 0
5249 22:12:56.668543 6, 0xFFFF, sum = 0
5250 22:12:56.668624 7, 0xFFFF, sum = 0
5251 22:12:56.671728 8, 0xFFFF, sum = 0
5252 22:12:56.671806 9, 0xFFFF, sum = 0
5253 22:12:56.675028 10, 0x0, sum = 1
5254 22:12:56.675104 11, 0x0, sum = 2
5255 22:12:56.678289 12, 0x0, sum = 3
5256 22:12:56.678368 13, 0x0, sum = 4
5257 22:12:56.678434 best_step = 11
5258 22:12:56.678495
5259 22:12:56.682323 ==
5260 22:12:56.685564 Dram Type= 6, Freq= 0, CH_0, rank 0
5261 22:12:56.688610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5262 22:12:56.688690 ==
5263 22:12:56.688760 RX Vref Scan: 1
5264 22:12:56.688822
5265 22:12:56.691781 RX Vref 0 -> 0, step: 1
5266 22:12:56.691865
5267 22:12:56.695288 RX Delay -61 -> 252, step: 4
5268 22:12:56.695367
5269 22:12:56.698981 Set Vref, RX VrefLevel [Byte0]: 52
5270 22:12:56.702490 [Byte1]: 50
5271 22:12:56.702571
5272 22:12:56.704947 Final RX Vref Byte 0 = 52 to rank0
5273 22:12:56.708825 Final RX Vref Byte 1 = 50 to rank0
5274 22:12:56.711933 Final RX Vref Byte 0 = 52 to rank1
5275 22:12:56.714630 Final RX Vref Byte 1 = 50 to rank1==
5276 22:12:56.717901 Dram Type= 6, Freq= 0, CH_0, rank 0
5277 22:12:56.721737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5278 22:12:56.724485 ==
5279 22:12:56.724572 DQS Delay:
5280 22:12:56.724638 DQS0 = 0, DQS1 = 0
5281 22:12:56.728538 DQM Delay:
5282 22:12:56.728645 DQM0 = 96, DQM1 = 88
5283 22:12:56.731657 DQ Delay:
5284 22:12:56.735299 DQ0 =96, DQ1 =98, DQ2 =92, DQ3 =94
5285 22:12:56.735380 DQ4 =98, DQ5 =88, DQ6 =104, DQ7 =102
5286 22:12:56.738357 DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =80
5287 22:12:56.744780 DQ12 =96, DQ13 =88, DQ14 =98, DQ15 =98
5288 22:12:56.744858
5289 22:12:56.744962
5290 22:12:56.751823 [DQSOSCAuto] RK0, (LSB)MR18= 0x13fe, (MSB)MR19= 0x504, tDQSOscB0 = 422 ps tDQSOscB1 = 415 ps
5291 22:12:56.754535 CH0 RK0: MR19=504, MR18=13FE
5292 22:12:56.761117 CH0_RK0: MR19=0x504, MR18=0x13FE, DQSOSC=415, MR23=63, INC=62, DEC=41
5293 22:12:56.761209
5294 22:12:56.764624 ----->DramcWriteLeveling(PI) begin...
5295 22:12:56.764734 ==
5296 22:12:56.768048 Dram Type= 6, Freq= 0, CH_0, rank 1
5297 22:12:56.771307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5298 22:12:56.771390 ==
5299 22:12:56.774246 Write leveling (Byte 0): 32 => 32
5300 22:12:56.777449 Write leveling (Byte 1): 32 => 32
5301 22:12:56.780767 DramcWriteLeveling(PI) end<-----
5302 22:12:56.780847
5303 22:12:56.780909 ==
5304 22:12:56.784536 Dram Type= 6, Freq= 0, CH_0, rank 1
5305 22:12:56.788064 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5306 22:12:56.788139 ==
5307 22:12:56.791260 [Gating] SW mode calibration
5308 22:12:56.797523 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5309 22:12:56.804076 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5310 22:12:56.807931 0 14 0 | B1->B0 | 2525 3434 | 1 1 | (1 1) (1 1)
5311 22:12:56.814275 0 14 4 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
5312 22:12:56.817555 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5313 22:12:56.820990 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5314 22:12:56.824457 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5315 22:12:56.831103 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5316 22:12:56.834723 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5317 22:12:56.838253 0 14 28 | B1->B0 | 3333 2c2c | 0 1 | (0 1) (1 0)
5318 22:12:56.844711 0 15 0 | B1->B0 | 2f2f 2323 | 0 0 | (1 0) (0 0)
5319 22:12:56.848170 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5320 22:12:56.850691 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5321 22:12:56.857241 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5322 22:12:56.860808 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5323 22:12:56.864046 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5324 22:12:56.870951 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5325 22:12:56.874074 0 15 28 | B1->B0 | 2a2a 3a3a | 0 0 | (0 0) (0 0)
5326 22:12:56.877173 1 0 0 | B1->B0 | 3838 4646 | 1 0 | (0 0) (0 0)
5327 22:12:56.883705 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5328 22:12:56.887501 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5329 22:12:56.890771 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5330 22:12:56.897115 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5331 22:12:56.900215 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5332 22:12:56.904311 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5333 22:12:56.910262 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5334 22:12:56.913389 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5335 22:12:56.917189 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5336 22:12:56.923383 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5337 22:12:56.926658 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5338 22:12:56.930031 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5339 22:12:56.936629 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5340 22:12:56.940277 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5341 22:12:56.943123 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5342 22:12:56.949710 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5343 22:12:56.953002 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5344 22:12:56.956314 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5345 22:12:56.963198 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5346 22:12:56.966359 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5347 22:12:56.969644 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5348 22:12:56.976892 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5349 22:12:56.980056 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5350 22:12:56.983116 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5351 22:12:56.989630 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5352 22:12:56.989704 Total UI for P1: 0, mck2ui 16
5353 22:12:56.996232 best dqsien dly found for B0: ( 1, 2, 30)
5354 22:12:56.999860 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5355 22:12:57.003087 Total UI for P1: 0, mck2ui 16
5356 22:12:57.006223 best dqsien dly found for B1: ( 1, 3, 4)
5357 22:12:57.009469 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5358 22:12:57.012717 best DQS1 dly(MCK, UI, PI) = (1, 3, 4)
5359 22:12:57.012803
5360 22:12:57.016103 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5361 22:12:57.019186 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 4)
5362 22:12:57.023228 [Gating] SW calibration Done
5363 22:12:57.023300 ==
5364 22:12:57.026307 Dram Type= 6, Freq= 0, CH_0, rank 1
5365 22:12:57.029490 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5366 22:12:57.029565 ==
5367 22:12:57.033100 RX Vref Scan: 0
5368 22:12:57.033175
5369 22:12:57.036101 RX Vref 0 -> 0, step: 1
5370 22:12:57.036174
5371 22:12:57.036236 RX Delay -80 -> 252, step: 8
5372 22:12:57.043256 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5373 22:12:57.046160 iDelay=200, Bit 1, Center 99 (0 ~ 199) 200
5374 22:12:57.049605 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5375 22:12:57.052736 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5376 22:12:57.056179 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5377 22:12:57.059426 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5378 22:12:57.066227 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5379 22:12:57.069068 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5380 22:12:57.073090 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5381 22:12:57.076197 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5382 22:12:57.079318 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5383 22:12:57.082908 iDelay=200, Bit 11, Center 75 (-16 ~ 167) 184
5384 22:12:57.089235 iDelay=200, Bit 12, Center 91 (0 ~ 183) 184
5385 22:12:57.092666 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5386 22:12:57.095885 iDelay=200, Bit 14, Center 99 (8 ~ 191) 184
5387 22:12:57.099192 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5388 22:12:57.099297 ==
5389 22:12:57.102276 Dram Type= 6, Freq= 0, CH_0, rank 1
5390 22:12:57.106171 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5391 22:12:57.109217 ==
5392 22:12:57.109293 DQS Delay:
5393 22:12:57.109355 DQS0 = 0, DQS1 = 0
5394 22:12:57.112449 DQM Delay:
5395 22:12:57.112555 DQM0 = 96, DQM1 = 87
5396 22:12:57.115521 DQ Delay:
5397 22:12:57.118865 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =95
5398 22:12:57.122124 DQ4 =95, DQ5 =87, DQ6 =103, DQ7 =103
5399 22:12:57.125433 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =75
5400 22:12:57.129330 DQ12 =91, DQ13 =95, DQ14 =99, DQ15 =95
5401 22:12:57.129407
5402 22:12:57.129472
5403 22:12:57.129539 ==
5404 22:12:57.133045 Dram Type= 6, Freq= 0, CH_0, rank 1
5405 22:12:57.135542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5406 22:12:57.135619 ==
5407 22:12:57.135684
5408 22:12:57.135742
5409 22:12:57.139077 TX Vref Scan disable
5410 22:12:57.139162 == TX Byte 0 ==
5411 22:12:57.145661 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5412 22:12:57.149228 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5413 22:12:57.149311 == TX Byte 1 ==
5414 22:12:57.156177 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5415 22:12:57.158581 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5416 22:12:57.158667 ==
5417 22:12:57.162198 Dram Type= 6, Freq= 0, CH_0, rank 1
5418 22:12:57.165401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5419 22:12:57.165483 ==
5420 22:12:57.165548
5421 22:12:57.165608
5422 22:12:57.168709 TX Vref Scan disable
5423 22:12:57.172177 == TX Byte 0 ==
5424 22:12:57.175619 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5425 22:12:57.178526 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5426 22:12:57.182034 == TX Byte 1 ==
5427 22:12:57.185888 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5428 22:12:57.188891 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5429 22:12:57.188964
5430 22:12:57.192506 [DATLAT]
5431 22:12:57.192577 Freq=933, CH0 RK1
5432 22:12:57.192639
5433 22:12:57.195339 DATLAT Default: 0xb
5434 22:12:57.195406 0, 0xFFFF, sum = 0
5435 22:12:57.198554 1, 0xFFFF, sum = 0
5436 22:12:57.198650 2, 0xFFFF, sum = 0
5437 22:12:57.202051 3, 0xFFFF, sum = 0
5438 22:12:57.202122 4, 0xFFFF, sum = 0
5439 22:12:57.205727 5, 0xFFFF, sum = 0
5440 22:12:57.205810 6, 0xFFFF, sum = 0
5441 22:12:57.209265 7, 0xFFFF, sum = 0
5442 22:12:57.209347 8, 0xFFFF, sum = 0
5443 22:12:57.211692 9, 0xFFFF, sum = 0
5444 22:12:57.211774 10, 0x0, sum = 1
5445 22:12:57.215578 11, 0x0, sum = 2
5446 22:12:57.215661 12, 0x0, sum = 3
5447 22:12:57.218573 13, 0x0, sum = 4
5448 22:12:57.218676 best_step = 11
5449 22:12:57.218769
5450 22:12:57.218862 ==
5451 22:12:57.221815 Dram Type= 6, Freq= 0, CH_0, rank 1
5452 22:12:57.228619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5453 22:12:57.228702 ==
5454 22:12:57.228767 RX Vref Scan: 0
5455 22:12:57.228844
5456 22:12:57.231559 RX Vref 0 -> 0, step: 1
5457 22:12:57.231640
5458 22:12:57.235107 RX Delay -61 -> 252, step: 4
5459 22:12:57.238608 iDelay=199, Bit 0, Center 96 (3 ~ 190) 188
5460 22:12:57.241618 iDelay=199, Bit 1, Center 96 (3 ~ 190) 188
5461 22:12:57.248751 iDelay=199, Bit 2, Center 94 (3 ~ 186) 184
5462 22:12:57.251902 iDelay=199, Bit 3, Center 94 (-1 ~ 190) 192
5463 22:12:57.254849 iDelay=199, Bit 4, Center 96 (7 ~ 186) 180
5464 22:12:57.258473 iDelay=199, Bit 5, Center 84 (-9 ~ 178) 188
5465 22:12:57.261957 iDelay=199, Bit 6, Center 106 (15 ~ 198) 184
5466 22:12:57.268238 iDelay=199, Bit 7, Center 102 (11 ~ 194) 184
5467 22:12:57.271716 iDelay=199, Bit 8, Center 82 (-5 ~ 170) 176
5468 22:12:57.274854 iDelay=199, Bit 9, Center 78 (-13 ~ 170) 184
5469 22:12:57.278624 iDelay=199, Bit 10, Center 88 (-1 ~ 178) 180
5470 22:12:57.281556 iDelay=199, Bit 11, Center 80 (-5 ~ 166) 172
5471 22:12:57.285375 iDelay=199, Bit 12, Center 92 (3 ~ 182) 180
5472 22:12:57.291635 iDelay=199, Bit 13, Center 92 (3 ~ 182) 180
5473 22:12:57.294916 iDelay=199, Bit 14, Center 100 (15 ~ 186) 172
5474 22:12:57.298006 iDelay=199, Bit 15, Center 96 (7 ~ 186) 180
5475 22:12:57.298081 ==
5476 22:12:57.301334 Dram Type= 6, Freq= 0, CH_0, rank 1
5477 22:12:57.304277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5478 22:12:57.304352 ==
5479 22:12:57.307661 DQS Delay:
5480 22:12:57.307735 DQS0 = 0, DQS1 = 0
5481 22:12:57.311407 DQM Delay:
5482 22:12:57.311482 DQM0 = 96, DQM1 = 88
5483 22:12:57.311545 DQ Delay:
5484 22:12:57.314584 DQ0 =96, DQ1 =96, DQ2 =94, DQ3 =94
5485 22:12:57.317624 DQ4 =96, DQ5 =84, DQ6 =106, DQ7 =102
5486 22:12:57.321020 DQ8 =82, DQ9 =78, DQ10 =88, DQ11 =80
5487 22:12:57.324367 DQ12 =92, DQ13 =92, DQ14 =100, DQ15 =96
5488 22:12:57.324448
5489 22:12:57.327629
5490 22:12:57.334366 [DQSOSCAuto] RK1, (LSB)MR18= 0x1806, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 414 ps
5491 22:12:57.337565 CH0 RK1: MR19=505, MR18=1806
5492 22:12:57.344507 CH0_RK1: MR19=0x505, MR18=0x1806, DQSOSC=414, MR23=63, INC=63, DEC=42
5493 22:12:57.347778 [RxdqsGatingPostProcess] freq 933
5494 22:12:57.351064 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5495 22:12:57.354712 best DQS0 dly(2T, 0.5T) = (0, 11)
5496 22:12:57.357232 best DQS1 dly(2T, 0.5T) = (0, 11)
5497 22:12:57.360845 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
5498 22:12:57.363765 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5499 22:12:57.367570 best DQS0 dly(2T, 0.5T) = (0, 10)
5500 22:12:57.370661 best DQS1 dly(2T, 0.5T) = (0, 11)
5501 22:12:57.374076 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5502 22:12:57.377566 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5503 22:12:57.380834 Pre-setting of DQS Precalculation
5504 22:12:57.384340 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5505 22:12:57.384417 ==
5506 22:12:57.387495 Dram Type= 6, Freq= 0, CH_1, rank 0
5507 22:12:57.393723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5508 22:12:57.393807 ==
5509 22:12:57.397441 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5510 22:12:57.404041 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5511 22:12:57.407145 [CA 0] Center 36 (6~67) winsize 62
5512 22:12:57.410790 [CA 1] Center 36 (6~67) winsize 62
5513 22:12:57.413685 [CA 2] Center 34 (4~64) winsize 61
5514 22:12:57.417365 [CA 3] Center 33 (3~64) winsize 62
5515 22:12:57.420569 [CA 4] Center 34 (4~64) winsize 61
5516 22:12:57.424119 [CA 5] Center 33 (3~63) winsize 61
5517 22:12:57.424194
5518 22:12:57.427115 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5519 22:12:57.427189
5520 22:12:57.430545 [CATrainingPosCal] consider 1 rank data
5521 22:12:57.433815 u2DelayCellTimex100 = 270/100 ps
5522 22:12:57.437415 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5523 22:12:57.441053 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5524 22:12:57.443830 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5525 22:12:57.450384 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5526 22:12:57.453526 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5527 22:12:57.457136 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5528 22:12:57.457218
5529 22:12:57.460361 CA PerBit enable=1, Macro0, CA PI delay=33
5530 22:12:57.460442
5531 22:12:57.463743 [CBTSetCACLKResult] CA Dly = 33
5532 22:12:57.463824 CS Dly: 4 (0~35)
5533 22:12:57.463890 ==
5534 22:12:57.466818 Dram Type= 6, Freq= 0, CH_1, rank 1
5535 22:12:57.473739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5536 22:12:57.473822 ==
5537 22:12:57.476909 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5538 22:12:57.483735 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5539 22:12:57.487004 [CA 0] Center 36 (6~67) winsize 62
5540 22:12:57.490460 [CA 1] Center 36 (6~67) winsize 62
5541 22:12:57.493379 [CA 2] Center 33 (3~64) winsize 62
5542 22:12:57.497305 [CA 3] Center 33 (3~64) winsize 62
5543 22:12:57.500171 [CA 4] Center 34 (4~65) winsize 62
5544 22:12:57.503345 [CA 5] Center 33 (3~63) winsize 61
5545 22:12:57.503429
5546 22:12:57.506778 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5547 22:12:57.506861
5548 22:12:57.510178 [CATrainingPosCal] consider 2 rank data
5549 22:12:57.513399 u2DelayCellTimex100 = 270/100 ps
5550 22:12:57.516817 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5551 22:12:57.520000 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5552 22:12:57.526946 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5553 22:12:57.530151 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5554 22:12:57.533488 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5555 22:12:57.536538 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5556 22:12:57.536646
5557 22:12:57.540437 CA PerBit enable=1, Macro0, CA PI delay=33
5558 22:12:57.540521
5559 22:12:57.543346 [CBTSetCACLKResult] CA Dly = 33
5560 22:12:57.543429 CS Dly: 5 (0~37)
5561 22:12:57.543495
5562 22:12:57.546484 ----->DramcWriteLeveling(PI) begin...
5563 22:12:57.550188 ==
5564 22:12:57.550271 Dram Type= 6, Freq= 0, CH_1, rank 0
5565 22:12:57.556980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5566 22:12:57.557065 ==
5567 22:12:57.560461 Write leveling (Byte 0): 28 => 28
5568 22:12:57.563578 Write leveling (Byte 1): 29 => 29
5569 22:12:57.566795 DramcWriteLeveling(PI) end<-----
5570 22:12:57.566878
5571 22:12:57.566945 ==
5572 22:12:57.569984 Dram Type= 6, Freq= 0, CH_1, rank 0
5573 22:12:57.573555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5574 22:12:57.573639 ==
5575 22:12:57.576531 [Gating] SW mode calibration
5576 22:12:57.583271 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5577 22:12:57.586703 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5578 22:12:57.593134 0 14 0 | B1->B0 | 2f2f 3232 | 1 0 | (1 1) (0 0)
5579 22:12:57.596623 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5580 22:12:57.599965 0 14 8 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5581 22:12:57.606607 0 14 12 | B1->B0 | 3535 3434 | 1 1 | (0 0) (1 1)
5582 22:12:57.609955 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5583 22:12:57.613198 0 14 20 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5584 22:12:57.620156 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5585 22:12:57.623031 0 14 28 | B1->B0 | 3131 3232 | 0 0 | (0 1) (0 1)
5586 22:12:57.626186 0 15 0 | B1->B0 | 2828 2c2c | 0 0 | (1 1) (0 1)
5587 22:12:57.633341 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5588 22:12:57.636347 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5589 22:12:57.639730 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5590 22:12:57.646096 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5591 22:12:57.649781 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5592 22:12:57.653279 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5593 22:12:57.660055 0 15 28 | B1->B0 | 2828 2d2d | 0 0 | (0 0) (0 0)
5594 22:12:57.662849 1 0 0 | B1->B0 | 4444 4444 | 0 0 | (1 1) (1 1)
5595 22:12:57.665889 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5596 22:12:57.672899 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5597 22:12:57.676815 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5598 22:12:57.679564 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5599 22:12:57.686204 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5600 22:12:57.689386 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5601 22:12:57.692555 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5602 22:12:57.699440 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5603 22:12:57.702772 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5604 22:12:57.706152 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5605 22:12:57.712508 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5606 22:12:57.715841 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5607 22:12:57.719070 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5608 22:12:57.725934 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5609 22:12:57.729137 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5610 22:12:57.732372 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5611 22:12:57.736076 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5612 22:12:57.742754 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5613 22:12:57.746347 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5614 22:12:57.749144 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5615 22:12:57.755702 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5616 22:12:57.759547 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5617 22:12:57.763103 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5618 22:12:57.766555 Total UI for P1: 0, mck2ui 16
5619 22:12:57.769080 best dqsien dly found for B1: ( 1, 2, 24)
5620 22:12:57.775673 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5621 22:12:57.779239 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5622 22:12:57.782642 Total UI for P1: 0, mck2ui 16
5623 22:12:57.785765 best dqsien dly found for B0: ( 1, 2, 28)
5624 22:12:57.789230 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5625 22:12:57.792254 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5626 22:12:57.792330
5627 22:12:57.796069 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5628 22:12:57.799207 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5629 22:12:57.802240 [Gating] SW calibration Done
5630 22:12:57.802312 ==
5631 22:12:57.805843 Dram Type= 6, Freq= 0, CH_1, rank 0
5632 22:12:57.812231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5633 22:12:57.812312 ==
5634 22:12:57.812378 RX Vref Scan: 0
5635 22:12:57.812438
5636 22:12:57.815286 RX Vref 0 -> 0, step: 1
5637 22:12:57.815358
5638 22:12:57.819091 RX Delay -80 -> 252, step: 8
5639 22:12:57.822740 iDelay=200, Bit 0, Center 99 (8 ~ 191) 184
5640 22:12:57.825240 iDelay=200, Bit 1, Center 91 (-8 ~ 191) 200
5641 22:12:57.829482 iDelay=200, Bit 2, Center 83 (-8 ~ 175) 184
5642 22:12:57.832429 iDelay=200, Bit 3, Center 99 (8 ~ 191) 184
5643 22:12:57.835339 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5644 22:12:57.841944 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5645 22:12:57.845305 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5646 22:12:57.848815 iDelay=200, Bit 7, Center 91 (-8 ~ 191) 200
5647 22:12:57.852103 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5648 22:12:57.855877 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5649 22:12:57.858689 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5650 22:12:57.865446 iDelay=200, Bit 11, Center 83 (-16 ~ 183) 200
5651 22:12:57.868800 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5652 22:12:57.872101 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5653 22:12:57.875158 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5654 22:12:57.879118 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5655 22:12:57.881927 ==
5656 22:12:57.881999 Dram Type= 6, Freq= 0, CH_1, rank 0
5657 22:12:57.888400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5658 22:12:57.888477 ==
5659 22:12:57.888542 DQS Delay:
5660 22:12:57.892304 DQS0 = 0, DQS1 = 0
5661 22:12:57.892378 DQM Delay:
5662 22:12:57.895235 DQM0 = 96, DQM1 = 88
5663 22:12:57.895309 DQ Delay:
5664 22:12:57.898858 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =99
5665 22:12:57.901892 DQ4 =95, DQ5 =103, DQ6 =107, DQ7 =91
5666 22:12:57.905353 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =83
5667 22:12:57.908411 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5668 22:12:57.908479
5669 22:12:57.908541
5670 22:12:57.908603 ==
5671 22:12:57.912312 Dram Type= 6, Freq= 0, CH_1, rank 0
5672 22:12:57.915361 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5673 22:12:57.915433 ==
5674 22:12:57.915496
5675 22:12:57.915558
5676 22:12:57.918459 TX Vref Scan disable
5677 22:12:57.921655 == TX Byte 0 ==
5678 22:12:57.925115 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5679 22:12:57.928317 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5680 22:12:57.931631 == TX Byte 1 ==
5681 22:12:57.935631 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5682 22:12:57.938620 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5683 22:12:57.938696 ==
5684 22:12:57.941777 Dram Type= 6, Freq= 0, CH_1, rank 0
5685 22:12:57.944967 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5686 22:12:57.948673 ==
5687 22:12:57.948748
5688 22:12:57.948820
5689 22:12:57.948879 TX Vref Scan disable
5690 22:12:57.952191 == TX Byte 0 ==
5691 22:12:57.955462 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5692 22:12:57.961928 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5693 22:12:57.962003 == TX Byte 1 ==
5694 22:12:57.965047 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5695 22:12:57.971725 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5696 22:12:57.971836
5697 22:12:57.971930 [DATLAT]
5698 22:12:57.972033 Freq=933, CH1 RK0
5699 22:12:57.972121
5700 22:12:57.975708 DATLAT Default: 0xd
5701 22:12:57.975788 0, 0xFFFF, sum = 0
5702 22:12:57.978557 1, 0xFFFF, sum = 0
5703 22:12:57.978633 2, 0xFFFF, sum = 0
5704 22:12:57.982306 3, 0xFFFF, sum = 0
5705 22:12:57.985068 4, 0xFFFF, sum = 0
5706 22:12:57.985141 5, 0xFFFF, sum = 0
5707 22:12:57.988696 6, 0xFFFF, sum = 0
5708 22:12:57.988769 7, 0xFFFF, sum = 0
5709 22:12:57.992047 8, 0xFFFF, sum = 0
5710 22:12:57.992148 9, 0xFFFF, sum = 0
5711 22:12:57.995164 10, 0x0, sum = 1
5712 22:12:57.995237 11, 0x0, sum = 2
5713 22:12:57.995308 12, 0x0, sum = 3
5714 22:12:57.998321 13, 0x0, sum = 4
5715 22:12:57.998394 best_step = 11
5716 22:12:57.998455
5717 22:12:58.001924 ==
5718 22:12:58.004926 Dram Type= 6, Freq= 0, CH_1, rank 0
5719 22:12:58.008413 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5720 22:12:58.008488 ==
5721 22:12:58.008560 RX Vref Scan: 1
5722 22:12:58.008620
5723 22:12:58.012094 RX Vref 0 -> 0, step: 1
5724 22:12:58.012183
5725 22:12:58.014987 RX Delay -61 -> 252, step: 4
5726 22:12:58.015069
5727 22:12:58.018791 Set Vref, RX VrefLevel [Byte0]: 60
5728 22:12:58.022151 [Byte1]: 54
5729 22:12:58.022224
5730 22:12:58.025417 Final RX Vref Byte 0 = 60 to rank0
5731 22:12:58.028709 Final RX Vref Byte 1 = 54 to rank0
5732 22:12:58.031618 Final RX Vref Byte 0 = 60 to rank1
5733 22:12:58.034826 Final RX Vref Byte 1 = 54 to rank1==
5734 22:12:58.038053 Dram Type= 6, Freq= 0, CH_1, rank 0
5735 22:12:58.041943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5736 22:12:58.044714 ==
5737 22:12:58.044791 DQS Delay:
5738 22:12:58.044853 DQS0 = 0, DQS1 = 0
5739 22:12:58.048550 DQM Delay:
5740 22:12:58.048622 DQM0 = 97, DQM1 = 91
5741 22:12:58.051532 DQ Delay:
5742 22:12:58.051602 DQ0 =100, DQ1 =92, DQ2 =86, DQ3 =98
5743 22:12:58.054562 DQ4 =96, DQ5 =106, DQ6 =110, DQ7 =94
5744 22:12:58.058331 DQ8 =82, DQ9 =82, DQ10 =90, DQ11 =86
5745 22:12:58.061378 DQ12 =98, DQ13 =98, DQ14 =98, DQ15 =96
5746 22:12:58.064558
5747 22:12:58.064628
5748 22:12:58.071352 [DQSOSCAuto] RK0, (LSB)MR18= 0x11ee, (MSB)MR19= 0x504, tDQSOscB0 = 428 ps tDQSOscB1 = 416 ps
5749 22:12:58.074560 CH1 RK0: MR19=504, MR18=11EE
5750 22:12:58.081309 CH1_RK0: MR19=0x504, MR18=0x11EE, DQSOSC=416, MR23=63, INC=62, DEC=41
5751 22:12:58.081385
5752 22:12:58.084736 ----->DramcWriteLeveling(PI) begin...
5753 22:12:58.084822 ==
5754 22:12:58.088379 Dram Type= 6, Freq= 0, CH_1, rank 1
5755 22:12:58.091985 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5756 22:12:58.092079 ==
5757 22:12:58.094621 Write leveling (Byte 0): 27 => 27
5758 22:12:58.097936 Write leveling (Byte 1): 29 => 29
5759 22:12:58.101169 DramcWriteLeveling(PI) end<-----
5760 22:12:58.101243
5761 22:12:58.101314 ==
5762 22:12:58.104440 Dram Type= 6, Freq= 0, CH_1, rank 1
5763 22:12:58.107952 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5764 22:12:58.108071 ==
5765 22:12:58.110972 [Gating] SW mode calibration
5766 22:12:58.117860 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5767 22:12:58.124637 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5768 22:12:58.127981 0 14 0 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5769 22:12:58.131673 0 14 4 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5770 22:12:58.138165 0 14 8 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5771 22:12:58.141291 0 14 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5772 22:12:58.145085 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5773 22:12:58.150914 0 14 20 | B1->B0 | 3535 3434 | 0 0 | (0 0) (0 1)
5774 22:12:58.154720 0 14 24 | B1->B0 | 3131 2f2f | 1 1 | (1 1) (1 0)
5775 22:12:58.157951 0 14 28 | B1->B0 | 2828 2323 | 1 0 | (1 0) (0 0)
5776 22:12:58.164811 0 15 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5777 22:12:58.167652 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5778 22:12:58.171356 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5779 22:12:58.177463 0 15 12 | B1->B0 | 2423 2323 | 1 0 | (0 0) (0 0)
5780 22:12:58.181361 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5781 22:12:58.184340 0 15 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5782 22:12:58.191287 0 15 24 | B1->B0 | 2929 3535 | 0 0 | (0 0) (0 0)
5783 22:12:58.194203 0 15 28 | B1->B0 | 3737 4141 | 0 1 | (0 0) (0 0)
5784 22:12:58.198004 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5785 22:12:58.204111 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5786 22:12:58.207692 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5787 22:12:58.211076 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5788 22:12:58.217480 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5789 22:12:58.220615 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5790 22:12:58.224340 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5791 22:12:58.230578 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5792 22:12:58.234456 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5793 22:12:58.237250 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5794 22:12:58.243900 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5795 22:12:58.247235 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5796 22:12:58.250599 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5797 22:12:58.253855 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5798 22:12:58.260296 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5799 22:12:58.263888 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5800 22:12:58.267257 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5801 22:12:58.273969 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5802 22:12:58.277162 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5803 22:12:58.280495 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5804 22:12:58.287493 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5805 22:12:58.290338 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5806 22:12:58.293877 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5807 22:12:58.300028 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5808 22:12:58.303441 Total UI for P1: 0, mck2ui 16
5809 22:12:58.307010 best dqsien dly found for B0: ( 1, 2, 22)
5810 22:12:58.310442 Total UI for P1: 0, mck2ui 16
5811 22:12:58.314054 best dqsien dly found for B1: ( 1, 2, 26)
5812 22:12:58.316825 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5813 22:12:58.320323 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5814 22:12:58.320409
5815 22:12:58.323468 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5816 22:12:58.326612 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5817 22:12:58.330296 [Gating] SW calibration Done
5818 22:12:58.330378 ==
5819 22:12:58.333174 Dram Type= 6, Freq= 0, CH_1, rank 1
5820 22:12:58.336517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5821 22:12:58.336621 ==
5822 22:12:58.340613 RX Vref Scan: 0
5823 22:12:58.340729
5824 22:12:58.340829 RX Vref 0 -> 0, step: 1
5825 22:12:58.343738
5826 22:12:58.343848 RX Delay -80 -> 252, step: 8
5827 22:12:58.350279 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5828 22:12:58.353846 iDelay=200, Bit 1, Center 87 (-8 ~ 183) 192
5829 22:12:58.356560 iDelay=200, Bit 2, Center 87 (-8 ~ 183) 192
5830 22:12:58.360049 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5831 22:12:58.363341 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5832 22:12:58.366805 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5833 22:12:58.373324 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5834 22:12:58.376608 iDelay=200, Bit 7, Center 91 (0 ~ 183) 184
5835 22:12:58.379935 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5836 22:12:58.383134 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5837 22:12:58.386447 iDelay=200, Bit 10, Center 91 (-8 ~ 191) 200
5838 22:12:58.389790 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5839 22:12:58.396781 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5840 22:12:58.400099 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5841 22:12:58.403458 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5842 22:12:58.406733 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5843 22:12:58.406843 ==
5844 22:12:58.410087 Dram Type= 6, Freq= 0, CH_1, rank 1
5845 22:12:58.413293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5846 22:12:58.413383 ==
5847 22:12:58.417038 DQS Delay:
5848 22:12:58.417122 DQS0 = 0, DQS1 = 0
5849 22:12:58.419748 DQM Delay:
5850 22:12:58.419832 DQM0 = 94, DQM1 = 89
5851 22:12:58.419899 DQ Delay:
5852 22:12:58.422928 DQ0 =95, DQ1 =87, DQ2 =87, DQ3 =95
5853 22:12:58.426496 DQ4 =95, DQ5 =103, DQ6 =103, DQ7 =91
5854 22:12:58.430023 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5855 22:12:58.432831 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5856 22:12:58.432915
5857 22:12:58.436187
5858 22:12:58.436269 ==
5859 22:12:58.440068 Dram Type= 6, Freq= 0, CH_1, rank 1
5860 22:12:58.442930 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5861 22:12:58.443015 ==
5862 22:12:58.443083
5863 22:12:58.443145
5864 22:12:58.446307 TX Vref Scan disable
5865 22:12:58.446390 == TX Byte 0 ==
5866 22:12:58.454061 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5867 22:12:58.456731 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5868 22:12:58.456815 == TX Byte 1 ==
5869 22:12:58.462890 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5870 22:12:58.466629 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5871 22:12:58.466717 ==
5872 22:12:58.469601 Dram Type= 6, Freq= 0, CH_1, rank 1
5873 22:12:58.473276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5874 22:12:58.473362 ==
5875 22:12:58.473430
5876 22:12:58.473492
5877 22:12:58.476605 TX Vref Scan disable
5878 22:12:58.479515 == TX Byte 0 ==
5879 22:12:58.482907 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5880 22:12:58.486618 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5881 22:12:58.489633 == TX Byte 1 ==
5882 22:12:58.492621 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5883 22:12:58.496215 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5884 22:12:58.496303
5885 22:12:58.499365 [DATLAT]
5886 22:12:58.499448 Freq=933, CH1 RK1
5887 22:12:58.499515
5888 22:12:58.502913 DATLAT Default: 0xb
5889 22:12:58.502996 0, 0xFFFF, sum = 0
5890 22:12:58.506106 1, 0xFFFF, sum = 0
5891 22:12:58.506190 2, 0xFFFF, sum = 0
5892 22:12:58.509278 3, 0xFFFF, sum = 0
5893 22:12:58.509364 4, 0xFFFF, sum = 0
5894 22:12:58.512693 5, 0xFFFF, sum = 0
5895 22:12:58.512783 6, 0xFFFF, sum = 0
5896 22:12:58.515813 7, 0xFFFF, sum = 0
5897 22:12:58.515904 8, 0xFFFF, sum = 0
5898 22:12:58.519330 9, 0xFFFF, sum = 0
5899 22:12:58.519419 10, 0x0, sum = 1
5900 22:12:58.522671 11, 0x0, sum = 2
5901 22:12:58.522769 12, 0x0, sum = 3
5902 22:12:58.526468 13, 0x0, sum = 4
5903 22:12:58.526567 best_step = 11
5904 22:12:58.526634
5905 22:12:58.526699 ==
5906 22:12:58.529472 Dram Type= 6, Freq= 0, CH_1, rank 1
5907 22:12:58.536255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5908 22:12:58.536371 ==
5909 22:12:58.536466 RX Vref Scan: 0
5910 22:12:58.536564
5911 22:12:58.539237 RX Vref 0 -> 0, step: 1
5912 22:12:58.539341
5913 22:12:58.542471 RX Delay -61 -> 252, step: 4
5914 22:12:58.545600 iDelay=195, Bit 0, Center 96 (7 ~ 186) 180
5915 22:12:58.548763 iDelay=195, Bit 1, Center 90 (-1 ~ 182) 184
5916 22:12:58.555776 iDelay=195, Bit 2, Center 86 (-5 ~ 178) 184
5917 22:12:58.558822 iDelay=195, Bit 3, Center 96 (7 ~ 186) 180
5918 22:12:58.562719 iDelay=195, Bit 4, Center 96 (7 ~ 186) 180
5919 22:12:58.565523 iDelay=195, Bit 5, Center 104 (15 ~ 194) 180
5920 22:12:58.568801 iDelay=195, Bit 6, Center 102 (11 ~ 194) 184
5921 22:12:58.572193 iDelay=195, Bit 7, Center 90 (3 ~ 178) 176
5922 22:12:58.578964 iDelay=195, Bit 8, Center 82 (-9 ~ 174) 184
5923 22:12:58.582267 iDelay=195, Bit 9, Center 80 (-9 ~ 170) 180
5924 22:12:58.585688 iDelay=195, Bit 10, Center 90 (-5 ~ 186) 192
5925 22:12:58.588884 iDelay=195, Bit 11, Center 82 (-9 ~ 174) 184
5926 22:12:58.592129 iDelay=195, Bit 12, Center 96 (7 ~ 186) 180
5927 22:12:58.595594 iDelay=195, Bit 13, Center 98 (7 ~ 190) 184
5928 22:12:58.601921 iDelay=195, Bit 14, Center 98 (7 ~ 190) 184
5929 22:12:58.605386 iDelay=195, Bit 15, Center 98 (7 ~ 190) 184
5930 22:12:58.605470 ==
5931 22:12:58.608694 Dram Type= 6, Freq= 0, CH_1, rank 1
5932 22:12:58.611688 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5933 22:12:58.611773 ==
5934 22:12:58.615309 DQS Delay:
5935 22:12:58.615393 DQS0 = 0, DQS1 = 0
5936 22:12:58.615461 DQM Delay:
5937 22:12:58.618390 DQM0 = 95, DQM1 = 90
5938 22:12:58.618475 DQ Delay:
5939 22:12:58.621932 DQ0 =96, DQ1 =90, DQ2 =86, DQ3 =96
5940 22:12:58.625175 DQ4 =96, DQ5 =104, DQ6 =102, DQ7 =90
5941 22:12:58.628338 DQ8 =82, DQ9 =80, DQ10 =90, DQ11 =82
5942 22:12:58.632228 DQ12 =96, DQ13 =98, DQ14 =98, DQ15 =98
5943 22:12:58.632313
5944 22:12:58.632379
5945 22:12:58.641438 [DQSOSCAuto] RK1, (LSB)MR18= 0x1019, (MSB)MR19= 0x505, tDQSOscB0 = 413 ps tDQSOscB1 = 416 ps
5946 22:12:58.645113 CH1 RK1: MR19=505, MR18=1019
5947 22:12:58.648465 CH1_RK1: MR19=0x505, MR18=0x1019, DQSOSC=413, MR23=63, INC=63, DEC=42
5948 22:12:58.651596 [RxdqsGatingPostProcess] freq 933
5949 22:12:58.658541 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5950 22:12:58.661828 best DQS0 dly(2T, 0.5T) = (0, 10)
5951 22:12:58.664801 best DQS1 dly(2T, 0.5T) = (0, 10)
5952 22:12:58.668567 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5953 22:12:58.671528 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5954 22:12:58.674981 best DQS0 dly(2T, 0.5T) = (0, 10)
5955 22:12:58.678682 best DQS1 dly(2T, 0.5T) = (0, 10)
5956 22:12:58.681317 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5957 22:12:58.684851 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5958 22:12:58.684930 Pre-setting of DQS Precalculation
5959 22:12:58.691675 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5960 22:12:58.698260 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5961 22:12:58.704758 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5962 22:12:58.704840
5963 22:12:58.704922
5964 22:12:58.708222 [Calibration Summary] 1866 Mbps
5965 22:12:58.711574 CH 0, Rank 0
5966 22:12:58.711648 SW Impedance : PASS
5967 22:12:58.714861 DUTY Scan : NO K
5968 22:12:58.717956 ZQ Calibration : PASS
5969 22:12:58.718034 Jitter Meter : NO K
5970 22:12:58.721477 CBT Training : PASS
5971 22:12:58.724501 Write leveling : PASS
5972 22:12:58.724580 RX DQS gating : PASS
5973 22:12:58.727828 RX DQ/DQS(RDDQC) : PASS
5974 22:12:58.727932 TX DQ/DQS : PASS
5975 22:12:58.732107 RX DATLAT : PASS
5976 22:12:58.734695 RX DQ/DQS(Engine): PASS
5977 22:12:58.734775 TX OE : NO K
5978 22:12:58.737900 All Pass.
5979 22:12:58.737976
5980 22:12:58.738056 CH 0, Rank 1
5981 22:12:58.741401 SW Impedance : PASS
5982 22:12:58.741481 DUTY Scan : NO K
5983 22:12:58.744881 ZQ Calibration : PASS
5984 22:12:58.748446 Jitter Meter : NO K
5985 22:12:58.748526 CBT Training : PASS
5986 22:12:58.751442 Write leveling : PASS
5987 22:12:58.754551 RX DQS gating : PASS
5988 22:12:58.754633 RX DQ/DQS(RDDQC) : PASS
5989 22:12:58.758407 TX DQ/DQS : PASS
5990 22:12:58.761373 RX DATLAT : PASS
5991 22:12:58.761455 RX DQ/DQS(Engine): PASS
5992 22:12:58.764801 TX OE : NO K
5993 22:12:58.764899 All Pass.
5994 22:12:58.764982
5995 22:12:58.768085 CH 1, Rank 0
5996 22:12:58.768162 SW Impedance : PASS
5997 22:12:58.771493 DUTY Scan : NO K
5998 22:12:58.774537 ZQ Calibration : PASS
5999 22:12:58.774617 Jitter Meter : NO K
6000 22:12:58.778399 CBT Training : PASS
6001 22:12:58.778474 Write leveling : PASS
6002 22:12:58.781771 RX DQS gating : PASS
6003 22:12:58.784348 RX DQ/DQS(RDDQC) : PASS
6004 22:12:58.784424 TX DQ/DQS : PASS
6005 22:12:58.787591 RX DATLAT : PASS
6006 22:12:58.790961 RX DQ/DQS(Engine): PASS
6007 22:12:58.791038 TX OE : NO K
6008 22:12:58.794481 All Pass.
6009 22:12:58.794563
6010 22:12:58.794644 CH 1, Rank 1
6011 22:12:58.798001 SW Impedance : PASS
6012 22:12:58.798082 DUTY Scan : NO K
6013 22:12:58.800889 ZQ Calibration : PASS
6014 22:12:58.804685 Jitter Meter : NO K
6015 22:12:58.804761 CBT Training : PASS
6016 22:12:58.807690 Write leveling : PASS
6017 22:12:58.811197 RX DQS gating : PASS
6018 22:12:58.811280 RX DQ/DQS(RDDQC) : PASS
6019 22:12:58.814173 TX DQ/DQS : PASS
6020 22:12:58.817369 RX DATLAT : PASS
6021 22:12:58.817451 RX DQ/DQS(Engine): PASS
6022 22:12:58.821188 TX OE : NO K
6023 22:12:58.821270 All Pass.
6024 22:12:58.821334
6025 22:12:58.824194 DramC Write-DBI off
6026 22:12:58.827465 PER_BANK_REFRESH: Hybrid Mode
6027 22:12:58.827547 TX_TRACKING: ON
6028 22:12:58.837622 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6029 22:12:58.840798 [FAST_K] Save calibration result to emmc
6030 22:12:58.843876 dramc_set_vcore_voltage set vcore to 650000
6031 22:12:58.847760 Read voltage for 400, 6
6032 22:12:58.847841 Vio18 = 0
6033 22:12:58.847907 Vcore = 650000
6034 22:12:58.851183 Vdram = 0
6035 22:12:58.851264 Vddq = 0
6036 22:12:58.851329 Vmddr = 0
6037 22:12:58.857588 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6038 22:12:58.860483 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6039 22:12:58.863683 MEM_TYPE=3, freq_sel=20
6040 22:12:58.867194 sv_algorithm_assistance_LP4_800
6041 22:12:58.870742 ============ PULL DRAM RESETB DOWN ============
6042 22:12:58.874253 ========== PULL DRAM RESETB DOWN end =========
6043 22:12:58.880947 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6044 22:12:58.884236 ===================================
6045 22:12:58.884321 LPDDR4 DRAM CONFIGURATION
6046 22:12:58.887313 ===================================
6047 22:12:58.890627 EX_ROW_EN[0] = 0x0
6048 22:12:58.893716 EX_ROW_EN[1] = 0x0
6049 22:12:58.893799 LP4Y_EN = 0x0
6050 22:12:58.897174 WORK_FSP = 0x0
6051 22:12:58.897257 WL = 0x2
6052 22:12:58.900604 RL = 0x2
6053 22:12:58.900687 BL = 0x2
6054 22:12:58.904260 RPST = 0x0
6055 22:12:58.904343 RD_PRE = 0x0
6056 22:12:58.906984 WR_PRE = 0x1
6057 22:12:58.907069 WR_PST = 0x0
6058 22:12:58.910360 DBI_WR = 0x0
6059 22:12:58.910443 DBI_RD = 0x0
6060 22:12:58.914143 OTF = 0x1
6061 22:12:58.916900 ===================================
6062 22:12:58.920665 ===================================
6063 22:12:58.920749 ANA top config
6064 22:12:58.923611 ===================================
6065 22:12:58.926818 DLL_ASYNC_EN = 0
6066 22:12:58.930182 ALL_SLAVE_EN = 1
6067 22:12:58.933506 NEW_RANK_MODE = 1
6068 22:12:58.933591 DLL_IDLE_MODE = 1
6069 22:12:58.936967 LP45_APHY_COMB_EN = 1
6070 22:12:58.940268 TX_ODT_DIS = 1
6071 22:12:58.943934 NEW_8X_MODE = 1
6072 22:12:58.946743 ===================================
6073 22:12:58.951173 ===================================
6074 22:12:58.953458 data_rate = 800
6075 22:12:58.953542 CKR = 1
6076 22:12:58.956845 DQ_P2S_RATIO = 4
6077 22:12:58.960233 ===================================
6078 22:12:58.963297 CA_P2S_RATIO = 4
6079 22:12:58.967104 DQ_CA_OPEN = 0
6080 22:12:58.969942 DQ_SEMI_OPEN = 1
6081 22:12:58.973502 CA_SEMI_OPEN = 1
6082 22:12:58.973585 CA_FULL_RATE = 0
6083 22:12:58.976690 DQ_CKDIV4_EN = 0
6084 22:12:58.979712 CA_CKDIV4_EN = 1
6085 22:12:58.983511 CA_PREDIV_EN = 0
6086 22:12:58.986679 PH8_DLY = 0
6087 22:12:58.990254 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6088 22:12:58.990337 DQ_AAMCK_DIV = 0
6089 22:12:58.993124 CA_AAMCK_DIV = 0
6090 22:12:58.996756 CA_ADMCK_DIV = 4
6091 22:12:59.000176 DQ_TRACK_CA_EN = 0
6092 22:12:59.003820 CA_PICK = 800
6093 22:12:59.007123 CA_MCKIO = 400
6094 22:12:59.010268 MCKIO_SEMI = 400
6095 22:12:59.010352 PLL_FREQ = 3016
6096 22:12:59.013001 DQ_UI_PI_RATIO = 32
6097 22:12:59.016597 CA_UI_PI_RATIO = 32
6098 22:12:59.019617 ===================================
6099 22:12:59.023055 ===================================
6100 22:12:59.026101 memory_type:LPDDR4
6101 22:12:59.029656 GP_NUM : 10
6102 22:12:59.029739 SRAM_EN : 1
6103 22:12:59.032741 MD32_EN : 0
6104 22:12:59.036309 ===================================
6105 22:12:59.036392 [ANA_INIT] >>>>>>>>>>>>>>
6106 22:12:59.039527 <<<<<< [CONFIGURE PHASE]: ANA_TX
6107 22:12:59.043128 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6108 22:12:59.046123 ===================================
6109 22:12:59.049517 data_rate = 800,PCW = 0X7400
6110 22:12:59.053227 ===================================
6111 22:12:59.055950 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6112 22:12:59.064267 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6113 22:12:59.072575 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6114 22:12:59.079217 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6115 22:12:59.082812 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6116 22:12:59.086140 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6117 22:12:59.086223 [ANA_INIT] flow start
6118 22:12:59.089171 [ANA_INIT] PLL >>>>>>>>
6119 22:12:59.092738 [ANA_INIT] PLL <<<<<<<<
6120 22:12:59.092821 [ANA_INIT] MIDPI >>>>>>>>
6121 22:12:59.096547 [ANA_INIT] MIDPI <<<<<<<<
6122 22:12:59.099341 [ANA_INIT] DLL >>>>>>>>
6123 22:12:59.099427 [ANA_INIT] flow end
6124 22:12:59.106293 ============ LP4 DIFF to SE enter ============
6125 22:12:59.109575 ============ LP4 DIFF to SE exit ============
6126 22:12:59.112954 [ANA_INIT] <<<<<<<<<<<<<
6127 22:12:59.116435 [Flow] Enable top DCM control >>>>>
6128 22:12:59.119747 [Flow] Enable top DCM control <<<<<
6129 22:12:59.119856 Enable DLL master slave shuffle
6130 22:12:59.125877 ==============================================================
6131 22:12:59.129295 Gating Mode config
6132 22:12:59.132807 ==============================================================
6133 22:12:59.136480 Config description:
6134 22:12:59.146399 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6135 22:12:59.152346 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6136 22:12:59.156227 SELPH_MODE 0: By rank 1: By Phase
6137 22:12:59.162948 ==============================================================
6138 22:12:59.165872 GAT_TRACK_EN = 0
6139 22:12:59.169260 RX_GATING_MODE = 2
6140 22:12:59.173249 RX_GATING_TRACK_MODE = 2
6141 22:12:59.173352 SELPH_MODE = 1
6142 22:12:59.175639 PICG_EARLY_EN = 1
6143 22:12:59.179295 VALID_LAT_VALUE = 1
6144 22:12:59.185970 ==============================================================
6145 22:12:59.189282 Enter into Gating configuration >>>>
6146 22:12:59.192338 Exit from Gating configuration <<<<
6147 22:12:59.195839 Enter into DVFS_PRE_config >>>>>
6148 22:12:59.206137 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6149 22:12:59.209034 Exit from DVFS_PRE_config <<<<<
6150 22:12:59.212254 Enter into PICG configuration >>>>
6151 22:12:59.215882 Exit from PICG configuration <<<<
6152 22:12:59.218823 [RX_INPUT] configuration >>>>>
6153 22:12:59.222104 [RX_INPUT] configuration <<<<<
6154 22:12:59.225491 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6155 22:12:59.232802 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6156 22:12:59.238699 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6157 22:12:59.245679 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6158 22:12:59.252208 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6159 22:12:59.255417 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6160 22:12:59.262269 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6161 22:12:59.265589 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6162 22:12:59.268688 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6163 22:12:59.272580 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6164 22:12:59.279645 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6165 22:12:59.282259 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6166 22:12:59.285411 ===================================
6167 22:12:59.288790 LPDDR4 DRAM CONFIGURATION
6168 22:12:59.291897 ===================================
6169 22:12:59.292012 EX_ROW_EN[0] = 0x0
6170 22:12:59.295058 EX_ROW_EN[1] = 0x0
6171 22:12:59.295141 LP4Y_EN = 0x0
6172 22:12:59.298644 WORK_FSP = 0x0
6173 22:12:59.298727 WL = 0x2
6174 22:12:59.301733 RL = 0x2
6175 22:12:59.301817 BL = 0x2
6176 22:12:59.304899 RPST = 0x0
6177 22:12:59.304982 RD_PRE = 0x0
6178 22:12:59.308554 WR_PRE = 0x1
6179 22:12:59.308654 WR_PST = 0x0
6180 22:12:59.311860 DBI_WR = 0x0
6181 22:12:59.311942 DBI_RD = 0x0
6182 22:12:59.315049 OTF = 0x1
6183 22:12:59.318642 ===================================
6184 22:12:59.321947 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6185 22:12:59.325167 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6186 22:12:59.332105 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6187 22:12:59.335054 ===================================
6188 22:12:59.338722 LPDDR4 DRAM CONFIGURATION
6189 22:12:59.341915 ===================================
6190 22:12:59.341998 EX_ROW_EN[0] = 0x10
6191 22:12:59.344877 EX_ROW_EN[1] = 0x0
6192 22:12:59.344960 LP4Y_EN = 0x0
6193 22:12:59.348356 WORK_FSP = 0x0
6194 22:12:59.348439 WL = 0x2
6195 22:12:59.351748 RL = 0x2
6196 22:12:59.351831 BL = 0x2
6197 22:12:59.354785 RPST = 0x0
6198 22:12:59.354868 RD_PRE = 0x0
6199 22:12:59.358223 WR_PRE = 0x1
6200 22:12:59.358306 WR_PST = 0x0
6201 22:12:59.361516 DBI_WR = 0x0
6202 22:12:59.361598 DBI_RD = 0x0
6203 22:12:59.364869 OTF = 0x1
6204 22:12:59.368109 ===================================
6205 22:12:59.374663 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6206 22:12:59.378127 nWR fixed to 30
6207 22:12:59.381484 [ModeRegInit_LP4] CH0 RK0
6208 22:12:59.381567 [ModeRegInit_LP4] CH0 RK1
6209 22:12:59.384787 [ModeRegInit_LP4] CH1 RK0
6210 22:12:59.387905 [ModeRegInit_LP4] CH1 RK1
6211 22:12:59.388027 match AC timing 19
6212 22:12:59.394802 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6213 22:12:59.398349 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6214 22:12:59.401806 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6215 22:12:59.408144 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6216 22:12:59.411448 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6217 22:12:59.411532 ==
6218 22:12:59.414426 Dram Type= 6, Freq= 0, CH_0, rank 0
6219 22:12:59.418207 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6220 22:12:59.418291 ==
6221 22:12:59.424852 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6222 22:12:59.431769 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6223 22:12:59.434767 [CA 0] Center 36 (8~64) winsize 57
6224 22:12:59.437999 [CA 1] Center 36 (8~64) winsize 57
6225 22:12:59.441184 [CA 2] Center 36 (8~64) winsize 57
6226 22:12:59.441267 [CA 3] Center 36 (8~64) winsize 57
6227 22:12:59.444600 [CA 4] Center 36 (8~64) winsize 57
6228 22:12:59.447753 [CA 5] Center 36 (8~64) winsize 57
6229 22:12:59.447837
6230 22:12:59.454515 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6231 22:12:59.454599
6232 22:12:59.457737 [CATrainingPosCal] consider 1 rank data
6233 22:12:59.461741 u2DelayCellTimex100 = 270/100 ps
6234 22:12:59.464845 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6235 22:12:59.468109 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6236 22:12:59.471356 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6237 22:12:59.474233 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6238 22:12:59.477620 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6239 22:12:59.481433 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6240 22:12:59.481516
6241 22:12:59.484557 CA PerBit enable=1, Macro0, CA PI delay=36
6242 22:12:59.484640
6243 22:12:59.487855 [CBTSetCACLKResult] CA Dly = 36
6244 22:12:59.490914 CS Dly: 1 (0~32)
6245 22:12:59.490997 ==
6246 22:12:59.494594 Dram Type= 6, Freq= 0, CH_0, rank 1
6247 22:12:59.497742 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6248 22:12:59.497826 ==
6249 22:12:59.504545 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6250 22:12:59.507894 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6251 22:12:59.510767 [CA 0] Center 36 (8~64) winsize 57
6252 22:12:59.513893 [CA 1] Center 36 (8~64) winsize 57
6253 22:12:59.517488 [CA 2] Center 36 (8~64) winsize 57
6254 22:12:59.521119 [CA 3] Center 36 (8~64) winsize 57
6255 22:12:59.523729 [CA 4] Center 36 (8~64) winsize 57
6256 22:12:59.527639 [CA 5] Center 36 (8~64) winsize 57
6257 22:12:59.527759
6258 22:12:59.530414 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6259 22:12:59.530498
6260 22:12:59.534023 [CATrainingPosCal] consider 2 rank data
6261 22:12:59.537272 u2DelayCellTimex100 = 270/100 ps
6262 22:12:59.540545 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6263 22:12:59.543914 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6264 22:12:59.551047 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6265 22:12:59.553697 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6266 22:12:59.557531 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6267 22:12:59.560370 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6268 22:12:59.560453
6269 22:12:59.563988 CA PerBit enable=1, Macro0, CA PI delay=36
6270 22:12:59.564085
6271 22:12:59.567327 [CBTSetCACLKResult] CA Dly = 36
6272 22:12:59.567409 CS Dly: 1 (0~32)
6273 22:12:59.567476
6274 22:12:59.573559 ----->DramcWriteLeveling(PI) begin...
6275 22:12:59.573643 ==
6276 22:12:59.577101 Dram Type= 6, Freq= 0, CH_0, rank 0
6277 22:12:59.580425 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6278 22:12:59.580509 ==
6279 22:12:59.583479 Write leveling (Byte 0): 40 => 8
6280 22:12:59.586760 Write leveling (Byte 1): 32 => 0
6281 22:12:59.590205 DramcWriteLeveling(PI) end<-----
6282 22:12:59.590288
6283 22:12:59.590355 ==
6284 22:12:59.593636 Dram Type= 6, Freq= 0, CH_0, rank 0
6285 22:12:59.596861 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6286 22:12:59.596945 ==
6287 22:12:59.600573 [Gating] SW mode calibration
6288 22:12:59.606887 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6289 22:12:59.613387 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6290 22:12:59.616711 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6291 22:12:59.620646 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6292 22:12:59.623790 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6293 22:12:59.630232 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6294 22:12:59.633302 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6295 22:12:59.636683 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6296 22:12:59.643298 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6297 22:12:59.646985 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6298 22:12:59.650150 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6299 22:12:59.653703 Total UI for P1: 0, mck2ui 16
6300 22:12:59.656901 best dqsien dly found for B0: ( 0, 14, 24)
6301 22:12:59.659874 Total UI for P1: 0, mck2ui 16
6302 22:12:59.663426 best dqsien dly found for B1: ( 0, 14, 24)
6303 22:12:59.667023 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6304 22:12:59.670436 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6305 22:12:59.673499
6306 22:12:59.676432 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6307 22:12:59.680100 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6308 22:12:59.683300 [Gating] SW calibration Done
6309 22:12:59.683380 ==
6310 22:12:59.686678 Dram Type= 6, Freq= 0, CH_0, rank 0
6311 22:12:59.689794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6312 22:12:59.689876 ==
6313 22:12:59.689941 RX Vref Scan: 0
6314 22:12:59.693221
6315 22:12:59.693302 RX Vref 0 -> 0, step: 1
6316 22:12:59.693367
6317 22:12:59.696337 RX Delay -410 -> 252, step: 16
6318 22:12:59.699551 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6319 22:12:59.706118 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6320 22:12:59.709759 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6321 22:12:59.713752 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6322 22:12:59.716411 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6323 22:12:59.723404 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6324 22:12:59.726307 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6325 22:12:59.729454 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6326 22:12:59.733253 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6327 22:12:59.740087 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6328 22:12:59.742767 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6329 22:12:59.746306 iDelay=230, Bit 11, Center -43 (-282 ~ 197) 480
6330 22:12:59.749372 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6331 22:12:59.756530 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6332 22:12:59.759234 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6333 22:12:59.762598 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6334 22:12:59.762679 ==
6335 22:12:59.766393 Dram Type= 6, Freq= 0, CH_0, rank 0
6336 22:12:59.773098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6337 22:12:59.773180 ==
6338 22:12:59.773245 DQS Delay:
6339 22:12:59.776303 DQS0 = 35, DQS1 = 51
6340 22:12:59.776385 DQM Delay:
6341 22:12:59.776453 DQM0 = 6, DQM1 = 11
6342 22:12:59.780063 DQ Delay:
6343 22:12:59.782802 DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0
6344 22:12:59.782885 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6345 22:12:59.786007 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6346 22:12:59.789294 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6347 22:12:59.789376
6348 22:12:59.789442
6349 22:12:59.792351 ==
6350 22:12:59.795798 Dram Type= 6, Freq= 0, CH_0, rank 0
6351 22:12:59.799213 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6352 22:12:59.799296 ==
6353 22:12:59.799363
6354 22:12:59.799443
6355 22:12:59.802443 TX Vref Scan disable
6356 22:12:59.802526 == TX Byte 0 ==
6357 22:12:59.805703 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6358 22:12:59.812148 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6359 22:12:59.812232 == TX Byte 1 ==
6360 22:12:59.815660 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6361 22:12:59.823105 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6362 22:12:59.823189 ==
6363 22:12:59.825787 Dram Type= 6, Freq= 0, CH_0, rank 0
6364 22:12:59.828931 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6365 22:12:59.829015 ==
6366 22:12:59.829082
6367 22:12:59.829143
6368 22:12:59.832396 TX Vref Scan disable
6369 22:12:59.832479 == TX Byte 0 ==
6370 22:12:59.838546 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6371 22:12:59.842333 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6372 22:12:59.842417 == TX Byte 1 ==
6373 22:12:59.848738 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6374 22:12:59.852223 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6375 22:12:59.852308
6376 22:12:59.852374 [DATLAT]
6377 22:12:59.855295 Freq=400, CH0 RK0
6378 22:12:59.855379
6379 22:12:59.855445 DATLAT Default: 0xf
6380 22:12:59.858397 0, 0xFFFF, sum = 0
6381 22:12:59.858483 1, 0xFFFF, sum = 0
6382 22:12:59.861890 2, 0xFFFF, sum = 0
6383 22:12:59.861981 3, 0xFFFF, sum = 0
6384 22:12:59.865277 4, 0xFFFF, sum = 0
6385 22:12:59.865361 5, 0xFFFF, sum = 0
6386 22:12:59.868838 6, 0xFFFF, sum = 0
6387 22:12:59.868923 7, 0xFFFF, sum = 0
6388 22:12:59.871931 8, 0xFFFF, sum = 0
6389 22:12:59.872025 9, 0xFFFF, sum = 0
6390 22:12:59.875349 10, 0xFFFF, sum = 0
6391 22:12:59.878502 11, 0xFFFF, sum = 0
6392 22:12:59.878586 12, 0xFFFF, sum = 0
6393 22:12:59.881821 13, 0x0, sum = 1
6394 22:12:59.881905 14, 0x0, sum = 2
6395 22:12:59.881973 15, 0x0, sum = 3
6396 22:12:59.885543 16, 0x0, sum = 4
6397 22:12:59.885628 best_step = 14
6398 22:12:59.885694
6399 22:12:59.885756 ==
6400 22:12:59.889536 Dram Type= 6, Freq= 0, CH_0, rank 0
6401 22:12:59.895286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6402 22:12:59.895370 ==
6403 22:12:59.895438 RX Vref Scan: 1
6404 22:12:59.895501
6405 22:12:59.898293 RX Vref 0 -> 0, step: 1
6406 22:12:59.898376
6407 22:12:59.901592 RX Delay -343 -> 252, step: 8
6408 22:12:59.901676
6409 22:12:59.905129 Set Vref, RX VrefLevel [Byte0]: 52
6410 22:12:59.908204 [Byte1]: 50
6411 22:12:59.912158
6412 22:12:59.912240 Final RX Vref Byte 0 = 52 to rank0
6413 22:12:59.915110 Final RX Vref Byte 1 = 50 to rank0
6414 22:12:59.918306 Final RX Vref Byte 0 = 52 to rank1
6415 22:12:59.921638 Final RX Vref Byte 1 = 50 to rank1==
6416 22:12:59.925278 Dram Type= 6, Freq= 0, CH_0, rank 0
6417 22:12:59.931552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6418 22:12:59.931636 ==
6419 22:12:59.931703 DQS Delay:
6420 22:12:59.934725 DQS0 = 44, DQS1 = 56
6421 22:12:59.934808 DQM Delay:
6422 22:12:59.934873 DQM0 = 11, DQM1 = 11
6423 22:12:59.938630 DQ Delay:
6424 22:12:59.941544 DQ0 =12, DQ1 =12, DQ2 =4, DQ3 =8
6425 22:12:59.945145 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6426 22:12:59.945228 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6427 22:12:59.948437 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6428 22:12:59.951528
6429 22:12:59.951610
6430 22:12:59.958050 [DQSOSCAuto] RK0, (LSB)MR18= 0x8755, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 392 ps
6431 22:12:59.961477 CH0 RK0: MR19=C0C, MR18=8755
6432 22:12:59.968107 CH0_RK0: MR19=0xC0C, MR18=0x8755, DQSOSC=392, MR23=63, INC=384, DEC=256
6433 22:12:59.968192 ==
6434 22:12:59.971176 Dram Type= 6, Freq= 0, CH_0, rank 1
6435 22:12:59.974640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6436 22:12:59.974724 ==
6437 22:12:59.978324 [Gating] SW mode calibration
6438 22:12:59.984581 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6439 22:12:59.990879 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6440 22:12:59.994634 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6441 22:12:59.997818 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6442 22:13:00.004562 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6443 22:13:00.008128 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6444 22:13:00.010973 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6445 22:13:00.017618 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6446 22:13:00.021363 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6447 22:13:00.024905 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6448 22:13:00.031064 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6449 22:13:00.031142 Total UI for P1: 0, mck2ui 16
6450 22:13:00.037489 best dqsien dly found for B0: ( 0, 14, 24)
6451 22:13:00.037578 Total UI for P1: 0, mck2ui 16
6452 22:13:00.044243 best dqsien dly found for B1: ( 0, 14, 24)
6453 22:13:00.047133 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6454 22:13:00.050635 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6455 22:13:00.050718
6456 22:13:00.053762 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6457 22:13:00.057160 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6458 22:13:00.060676 [Gating] SW calibration Done
6459 22:13:00.060758 ==
6460 22:13:00.064547 Dram Type= 6, Freq= 0, CH_0, rank 1
6461 22:13:00.067391 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6462 22:13:00.067474 ==
6463 22:13:00.070522 RX Vref Scan: 0
6464 22:13:00.070604
6465 22:13:00.070669 RX Vref 0 -> 0, step: 1
6466 22:13:00.070730
6467 22:13:00.074034 RX Delay -410 -> 252, step: 16
6468 22:13:00.081139 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6469 22:13:00.084189 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6470 22:13:00.087541 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6471 22:13:00.090463 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6472 22:13:00.097656 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6473 22:13:00.100789 iDelay=230, Bit 5, Center -43 (-282 ~ 197) 480
6474 22:13:00.104169 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6475 22:13:00.107470 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6476 22:13:00.114230 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6477 22:13:00.117079 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6478 22:13:00.120400 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6479 22:13:00.124744 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6480 22:13:00.130281 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6481 22:13:00.133735 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6482 22:13:00.136891 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6483 22:13:00.139887 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6484 22:13:00.143328 ==
6485 22:13:00.146761 Dram Type= 6, Freq= 0, CH_0, rank 1
6486 22:13:00.149952 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6487 22:13:00.150036 ==
6488 22:13:00.150103 DQS Delay:
6489 22:13:00.153298 DQS0 = 43, DQS1 = 51
6490 22:13:00.153380 DQM Delay:
6491 22:13:00.156962 DQM0 = 11, DQM1 = 10
6492 22:13:00.157045 DQ Delay:
6493 22:13:00.160242 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6494 22:13:00.163713 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =24
6495 22:13:00.166691 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6496 22:13:00.169990 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6497 22:13:00.170073
6498 22:13:00.170139
6499 22:13:00.170202 ==
6500 22:13:00.173444 Dram Type= 6, Freq= 0, CH_0, rank 1
6501 22:13:00.176499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6502 22:13:00.176583 ==
6503 22:13:00.176650
6504 22:13:00.176712
6505 22:13:00.180196 TX Vref Scan disable
6506 22:13:00.180279 == TX Byte 0 ==
6507 22:13:00.186733 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6508 22:13:00.189777 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6509 22:13:00.189861 == TX Byte 1 ==
6510 22:13:00.196678 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6511 22:13:00.200165 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6512 22:13:00.200247 ==
6513 22:13:00.203689 Dram Type= 6, Freq= 0, CH_0, rank 1
6514 22:13:00.206596 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6515 22:13:00.206679 ==
6516 22:13:00.206746
6517 22:13:00.206808
6518 22:13:00.210059 TX Vref Scan disable
6519 22:13:00.210142 == TX Byte 0 ==
6520 22:13:00.216839 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6521 22:13:00.219883 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6522 22:13:00.219993 == TX Byte 1 ==
6523 22:13:00.226265 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6524 22:13:00.229893 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6525 22:13:00.229978
6526 22:13:00.230044 [DATLAT]
6527 22:13:00.233431 Freq=400, CH0 RK1
6528 22:13:00.233514
6529 22:13:00.233580 DATLAT Default: 0xe
6530 22:13:00.236664 0, 0xFFFF, sum = 0
6531 22:13:00.236749 1, 0xFFFF, sum = 0
6532 22:13:00.239648 2, 0xFFFF, sum = 0
6533 22:13:00.239732 3, 0xFFFF, sum = 0
6534 22:13:00.243203 4, 0xFFFF, sum = 0
6535 22:13:00.243287 5, 0xFFFF, sum = 0
6536 22:13:00.246414 6, 0xFFFF, sum = 0
6537 22:13:00.246499 7, 0xFFFF, sum = 0
6538 22:13:00.249789 8, 0xFFFF, sum = 0
6539 22:13:00.249873 9, 0xFFFF, sum = 0
6540 22:13:00.253306 10, 0xFFFF, sum = 0
6541 22:13:00.253399 11, 0xFFFF, sum = 0
6542 22:13:00.256596 12, 0xFFFF, sum = 0
6543 22:13:00.256681 13, 0x0, sum = 1
6544 22:13:00.259771 14, 0x0, sum = 2
6545 22:13:00.259885 15, 0x0, sum = 3
6546 22:13:00.263580 16, 0x0, sum = 4
6547 22:13:00.263664 best_step = 14
6548 22:13:00.263731
6549 22:13:00.263793 ==
6550 22:13:00.266488 Dram Type= 6, Freq= 0, CH_0, rank 1
6551 22:13:00.272711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6552 22:13:00.272795 ==
6553 22:13:00.272862 RX Vref Scan: 0
6554 22:13:00.272924
6555 22:13:00.276157 RX Vref 0 -> 0, step: 1
6556 22:13:00.276240
6557 22:13:00.279740 RX Delay -343 -> 252, step: 8
6558 22:13:00.286066 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6559 22:13:00.289283 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6560 22:13:00.292694 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6561 22:13:00.296207 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6562 22:13:00.302882 iDelay=217, Bit 4, Center -36 (-271 ~ 200) 472
6563 22:13:00.305933 iDelay=217, Bit 5, Center -48 (-287 ~ 192) 480
6564 22:13:00.309459 iDelay=217, Bit 6, Center -24 (-263 ~ 216) 480
6565 22:13:00.312513 iDelay=217, Bit 7, Center -28 (-263 ~ 208) 472
6566 22:13:00.319296 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6567 22:13:00.322890 iDelay=217, Bit 9, Center -56 (-295 ~ 184) 480
6568 22:13:00.326102 iDelay=217, Bit 10, Center -40 (-279 ~ 200) 480
6569 22:13:00.332122 iDelay=217, Bit 11, Center -56 (-295 ~ 184) 480
6570 22:13:00.335754 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6571 22:13:00.338970 iDelay=217, Bit 13, Center -40 (-279 ~ 200) 480
6572 22:13:00.342193 iDelay=217, Bit 14, Center -32 (-271 ~ 208) 480
6573 22:13:00.349159 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6574 22:13:00.349243 ==
6575 22:13:00.352816 Dram Type= 6, Freq= 0, CH_0, rank 1
6576 22:13:00.355945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6577 22:13:00.356034 ==
6578 22:13:00.356102 DQS Delay:
6579 22:13:00.359181 DQS0 = 48, DQS1 = 60
6580 22:13:00.359264 DQM Delay:
6581 22:13:00.362493 DQM0 = 13, DQM1 = 14
6582 22:13:00.362580 DQ Delay:
6583 22:13:00.365648 DQ0 =16, DQ1 =16, DQ2 =8, DQ3 =12
6584 22:13:00.369019 DQ4 =12, DQ5 =0, DQ6 =24, DQ7 =20
6585 22:13:00.372256 DQ8 =0, DQ9 =4, DQ10 =20, DQ11 =4
6586 22:13:00.375546 DQ12 =16, DQ13 =20, DQ14 =28, DQ15 =24
6587 22:13:00.375630
6588 22:13:00.375696
6589 22:13:00.382079 [DQSOSCAuto] RK1, (LSB)MR18= 0x966a, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 391 ps
6590 22:13:00.385220 CH0 RK1: MR19=C0C, MR18=966A
6591 22:13:00.392246 CH0_RK1: MR19=0xC0C, MR18=0x966A, DQSOSC=391, MR23=63, INC=386, DEC=257
6592 22:13:00.395483 [RxdqsGatingPostProcess] freq 400
6593 22:13:00.402017 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6594 22:13:00.405247 best DQS0 dly(2T, 0.5T) = (0, 10)
6595 22:13:00.405336 best DQS1 dly(2T, 0.5T) = (0, 10)
6596 22:13:00.408664 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6597 22:13:00.412123 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6598 22:13:00.415465 best DQS0 dly(2T, 0.5T) = (0, 10)
6599 22:13:00.419022 best DQS1 dly(2T, 0.5T) = (0, 10)
6600 22:13:00.421851 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6601 22:13:00.425268 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6602 22:13:00.428762 Pre-setting of DQS Precalculation
6603 22:13:00.435812 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6604 22:13:00.435896 ==
6605 22:13:00.438579 Dram Type= 6, Freq= 0, CH_1, rank 0
6606 22:13:00.441932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6607 22:13:00.442016 ==
6608 22:13:00.448275 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6609 22:13:00.452257 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6610 22:13:00.455114 [CA 0] Center 36 (8~64) winsize 57
6611 22:13:00.458228 [CA 1] Center 36 (8~64) winsize 57
6612 22:13:00.461523 [CA 2] Center 36 (8~64) winsize 57
6613 22:13:00.465080 [CA 3] Center 36 (8~64) winsize 57
6614 22:13:00.468653 [CA 4] Center 36 (8~64) winsize 57
6615 22:13:00.471658 [CA 5] Center 36 (8~64) winsize 57
6616 22:13:00.471741
6617 22:13:00.474983 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6618 22:13:00.475066
6619 22:13:00.479361 [CATrainingPosCal] consider 1 rank data
6620 22:13:00.481543 u2DelayCellTimex100 = 270/100 ps
6621 22:13:00.485151 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6622 22:13:00.488478 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6623 22:13:00.495165 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6624 22:13:00.498304 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6625 22:13:00.501649 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6626 22:13:00.505261 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6627 22:13:00.505344
6628 22:13:00.508366 CA PerBit enable=1, Macro0, CA PI delay=36
6629 22:13:00.508450
6630 22:13:00.511491 [CBTSetCACLKResult] CA Dly = 36
6631 22:13:00.511574 CS Dly: 1 (0~32)
6632 22:13:00.511641 ==
6633 22:13:00.514868 Dram Type= 6, Freq= 0, CH_1, rank 1
6634 22:13:00.521657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6635 22:13:00.521742 ==
6636 22:13:00.525080 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6637 22:13:00.531391 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6638 22:13:00.535335 [CA 0] Center 36 (8~64) winsize 57
6639 22:13:00.538094 [CA 1] Center 36 (8~64) winsize 57
6640 22:13:00.541723 [CA 2] Center 36 (8~64) winsize 57
6641 22:13:00.544746 [CA 3] Center 36 (8~64) winsize 57
6642 22:13:00.548193 [CA 4] Center 36 (8~64) winsize 57
6643 22:13:00.551635 [CA 5] Center 36 (8~64) winsize 57
6644 22:13:00.551719
6645 22:13:00.555056 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6646 22:13:00.555139
6647 22:13:00.558127 [CATrainingPosCal] consider 2 rank data
6648 22:13:00.561952 u2DelayCellTimex100 = 270/100 ps
6649 22:13:00.565012 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6650 22:13:00.568589 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6651 22:13:00.571445 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6652 22:13:00.574891 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6653 22:13:00.578338 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6654 22:13:00.581094 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6655 22:13:00.584583
6656 22:13:00.588126 CA PerBit enable=1, Macro0, CA PI delay=36
6657 22:13:00.588205
6658 22:13:00.591463 [CBTSetCACLKResult] CA Dly = 36
6659 22:13:00.591538 CS Dly: 1 (0~32)
6660 22:13:00.591602
6661 22:13:00.594896 ----->DramcWriteLeveling(PI) begin...
6662 22:13:00.594974 ==
6663 22:13:00.598040 Dram Type= 6, Freq= 0, CH_1, rank 0
6664 22:13:00.601308 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6665 22:13:00.604541 ==
6666 22:13:00.604616 Write leveling (Byte 0): 40 => 8
6667 22:13:00.607859 Write leveling (Byte 1): 40 => 8
6668 22:13:00.610920 DramcWriteLeveling(PI) end<-----
6669 22:13:00.610999
6670 22:13:00.611061 ==
6671 22:13:00.614128 Dram Type= 6, Freq= 0, CH_1, rank 0
6672 22:13:00.621061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6673 22:13:00.621142 ==
6674 22:13:00.624193 [Gating] SW mode calibration
6675 22:13:00.631386 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6676 22:13:00.634140 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6677 22:13:00.640541 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6678 22:13:00.644339 0 11 16 | B1->B0 | 2423 2323 | 1 0 | (0 0) (0 0)
6679 22:13:00.647473 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6680 22:13:00.653938 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6681 22:13:00.657400 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6682 22:13:00.660754 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6683 22:13:00.664134 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6684 22:13:00.670647 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6685 22:13:00.674604 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6686 22:13:00.677509 Total UI for P1: 0, mck2ui 16
6687 22:13:00.680925 best dqsien dly found for B0: ( 0, 14, 24)
6688 22:13:00.683891 Total UI for P1: 0, mck2ui 16
6689 22:13:00.687234 best dqsien dly found for B1: ( 0, 14, 24)
6690 22:13:00.690689 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6691 22:13:00.693891 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6692 22:13:00.693961
6693 22:13:00.697001 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6694 22:13:00.703619 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6695 22:13:00.703692 [Gating] SW calibration Done
6696 22:13:00.703758 ==
6697 22:13:00.707732 Dram Type= 6, Freq= 0, CH_1, rank 0
6698 22:13:00.713611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6699 22:13:00.713681 ==
6700 22:13:00.713745 RX Vref Scan: 0
6701 22:13:00.713802
6702 22:13:00.716853 RX Vref 0 -> 0, step: 1
6703 22:13:00.716926
6704 22:13:00.720087 RX Delay -410 -> 252, step: 16
6705 22:13:00.723829 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6706 22:13:00.727223 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6707 22:13:00.733746 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6708 22:13:00.737024 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6709 22:13:00.741608 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6710 22:13:00.743689 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6711 22:13:00.749878 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6712 22:13:00.753279 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6713 22:13:00.756535 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6714 22:13:00.760636 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6715 22:13:00.766537 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6716 22:13:00.770366 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6717 22:13:00.773525 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6718 22:13:00.780172 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6719 22:13:00.782935 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6720 22:13:00.786243 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6721 22:13:00.786317 ==
6722 22:13:00.789611 Dram Type= 6, Freq= 0, CH_1, rank 0
6723 22:13:00.793108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6724 22:13:00.793183 ==
6725 22:13:00.797243 DQS Delay:
6726 22:13:00.797314 DQS0 = 51, DQS1 = 59
6727 22:13:00.799551 DQM Delay:
6728 22:13:00.799621 DQM0 = 19, DQM1 = 16
6729 22:13:00.803092 DQ Delay:
6730 22:13:00.803164 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6731 22:13:00.806468 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6732 22:13:00.809549 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6733 22:13:00.812887 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6734 22:13:00.812962
6735 22:13:00.813024
6736 22:13:00.816084 ==
6737 22:13:00.819360 Dram Type= 6, Freq= 0, CH_1, rank 0
6738 22:13:00.823082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6739 22:13:00.823155 ==
6740 22:13:00.823223
6741 22:13:00.823281
6742 22:13:00.826308 TX Vref Scan disable
6743 22:13:00.826378 == TX Byte 0 ==
6744 22:13:00.829424 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6745 22:13:00.836168 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6746 22:13:00.836246 == TX Byte 1 ==
6747 22:13:00.839762 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6748 22:13:00.846449 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6749 22:13:00.846525 ==
6750 22:13:00.849178 Dram Type= 6, Freq= 0, CH_1, rank 0
6751 22:13:00.853070 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6752 22:13:00.853144 ==
6753 22:13:00.853211
6754 22:13:00.853270
6755 22:13:00.856123 TX Vref Scan disable
6756 22:13:00.856197 == TX Byte 0 ==
6757 22:13:00.859538 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6758 22:13:00.865902 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6759 22:13:00.865980 == TX Byte 1 ==
6760 22:13:00.869144 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6761 22:13:00.876263 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6762 22:13:00.876338
6763 22:13:00.876401 [DATLAT]
6764 22:13:00.876463 Freq=400, CH1 RK0
6765 22:13:00.876522
6766 22:13:00.879400 DATLAT Default: 0xf
6767 22:13:00.883142 0, 0xFFFF, sum = 0
6768 22:13:00.883222 1, 0xFFFF, sum = 0
6769 22:13:00.886148 2, 0xFFFF, sum = 0
6770 22:13:00.886253 3, 0xFFFF, sum = 0
6771 22:13:00.889668 4, 0xFFFF, sum = 0
6772 22:13:00.889748 5, 0xFFFF, sum = 0
6773 22:13:00.892387 6, 0xFFFF, sum = 0
6774 22:13:00.892464 7, 0xFFFF, sum = 0
6775 22:13:00.895577 8, 0xFFFF, sum = 0
6776 22:13:00.895648 9, 0xFFFF, sum = 0
6777 22:13:00.898979 10, 0xFFFF, sum = 0
6778 22:13:00.899055 11, 0xFFFF, sum = 0
6779 22:13:00.902268 12, 0xFFFF, sum = 0
6780 22:13:00.902345 13, 0x0, sum = 1
6781 22:13:00.905857 14, 0x0, sum = 2
6782 22:13:00.905937 15, 0x0, sum = 3
6783 22:13:00.909543 16, 0x0, sum = 4
6784 22:13:00.909619 best_step = 14
6785 22:13:00.909686
6786 22:13:00.909745 ==
6787 22:13:00.912291 Dram Type= 6, Freq= 0, CH_1, rank 0
6788 22:13:00.915926 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6789 22:13:00.919159 ==
6790 22:13:00.919241 RX Vref Scan: 1
6791 22:13:00.919306
6792 22:13:00.922606 RX Vref 0 -> 0, step: 1
6793 22:13:00.922686
6794 22:13:00.925527 RX Delay -359 -> 252, step: 8
6795 22:13:00.925604
6796 22:13:00.929339 Set Vref, RX VrefLevel [Byte0]: 60
6797 22:13:00.932148 [Byte1]: 54
6798 22:13:00.932232
6799 22:13:00.935888 Final RX Vref Byte 0 = 60 to rank0
6800 22:13:00.938915 Final RX Vref Byte 1 = 54 to rank0
6801 22:13:00.942086 Final RX Vref Byte 0 = 60 to rank1
6802 22:13:00.945159 Final RX Vref Byte 1 = 54 to rank1==
6803 22:13:00.948588 Dram Type= 6, Freq= 0, CH_1, rank 0
6804 22:13:00.951875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6805 22:13:00.955190 ==
6806 22:13:00.955267 DQS Delay:
6807 22:13:00.955335 DQS0 = 48, DQS1 = 60
6808 22:13:00.958773 DQM Delay:
6809 22:13:00.958852 DQM0 = 11, DQM1 = 13
6810 22:13:00.962645 DQ Delay:
6811 22:13:00.962721 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =12
6812 22:13:00.965490 DQ4 =8, DQ5 =20, DQ6 =24, DQ7 =8
6813 22:13:00.968792 DQ8 =0, DQ9 =4, DQ10 =12, DQ11 =12
6814 22:13:00.972556 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6815 22:13:00.972633
6816 22:13:00.972697
6817 22:13:00.981670 [DQSOSCAuto] RK0, (LSB)MR18= 0x8d35, (MSB)MR19= 0xc0c, tDQSOscB0 = 403 ps tDQSOscB1 = 392 ps
6818 22:13:00.985479 CH1 RK0: MR19=C0C, MR18=8D35
6819 22:13:00.991685 CH1_RK0: MR19=0xC0C, MR18=0x8D35, DQSOSC=392, MR23=63, INC=384, DEC=256
6820 22:13:00.991763 ==
6821 22:13:00.995175 Dram Type= 6, Freq= 0, CH_1, rank 1
6822 22:13:00.998635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6823 22:13:00.998713 ==
6824 22:13:01.001991 [Gating] SW mode calibration
6825 22:13:01.008193 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6826 22:13:01.011797 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6827 22:13:01.018357 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6828 22:13:01.021455 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6829 22:13:01.025135 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6830 22:13:01.031637 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6831 22:13:01.035141 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6832 22:13:01.038187 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6833 22:13:01.044919 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6834 22:13:01.048448 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6835 22:13:01.052753 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6836 22:13:01.055187 Total UI for P1: 0, mck2ui 16
6837 22:13:01.058083 best dqsien dly found for B0: ( 0, 14, 24)
6838 22:13:01.061802 Total UI for P1: 0, mck2ui 16
6839 22:13:01.064973 best dqsien dly found for B1: ( 0, 14, 24)
6840 22:13:01.068258 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6841 22:13:01.071698 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6842 22:13:01.071782
6843 22:13:01.078243 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6844 22:13:01.081648 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6845 22:13:01.084845 [Gating] SW calibration Done
6846 22:13:01.084928 ==
6847 22:13:01.088010 Dram Type= 6, Freq= 0, CH_1, rank 1
6848 22:13:01.092018 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6849 22:13:01.092102 ==
6850 22:13:01.092186 RX Vref Scan: 0
6851 22:13:01.092266
6852 22:13:01.094861 RX Vref 0 -> 0, step: 1
6853 22:13:01.094959
6854 22:13:01.098172 RX Delay -410 -> 252, step: 16
6855 22:13:01.101231 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6856 22:13:01.108624 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6857 22:13:01.111407 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6858 22:13:01.115384 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6859 22:13:01.118271 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6860 22:13:01.124775 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6861 22:13:01.127790 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6862 22:13:01.131455 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6863 22:13:01.134597 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6864 22:13:01.138058 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6865 22:13:01.145091 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6866 22:13:01.148081 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6867 22:13:01.151498 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6868 22:13:01.158197 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6869 22:13:01.162028 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6870 22:13:01.164871 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6871 22:13:01.164954 ==
6872 22:13:01.168358 Dram Type= 6, Freq= 0, CH_1, rank 1
6873 22:13:01.171130 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6874 22:13:01.174935 ==
6875 22:13:01.175018 DQS Delay:
6876 22:13:01.175102 DQS0 = 51, DQS1 = 59
6877 22:13:01.177538 DQM Delay:
6878 22:13:01.177620 DQM0 = 18, DQM1 = 19
6879 22:13:01.181344 DQ Delay:
6880 22:13:01.184801 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6881 22:13:01.184885 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6882 22:13:01.188397 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6883 22:13:01.190836 DQ12 =24, DQ13 =24, DQ14 =32, DQ15 =32
6884 22:13:01.190919
6885 22:13:01.194612
6886 22:13:01.194695 ==
6887 22:13:01.197697 Dram Type= 6, Freq= 0, CH_1, rank 1
6888 22:13:01.200867 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6889 22:13:01.200950 ==
6890 22:13:01.201034
6891 22:13:01.201113
6892 22:13:01.205020 TX Vref Scan disable
6893 22:13:01.205103 == TX Byte 0 ==
6894 22:13:01.207702 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6895 22:13:01.214586 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6896 22:13:01.214670 == TX Byte 1 ==
6897 22:13:01.217897 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6898 22:13:01.224265 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6899 22:13:01.224349 ==
6900 22:13:01.227838 Dram Type= 6, Freq= 0, CH_1, rank 1
6901 22:13:01.231434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6902 22:13:01.231518 ==
6903 22:13:01.231622
6904 22:13:01.231721
6905 22:13:01.234400 TX Vref Scan disable
6906 22:13:01.234483 == TX Byte 0 ==
6907 22:13:01.237828 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6908 22:13:01.244414 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6909 22:13:01.244499 == TX Byte 1 ==
6910 22:13:01.247607 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6911 22:13:01.254111 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6912 22:13:01.254195
6913 22:13:01.254279 [DATLAT]
6914 22:13:01.254358 Freq=400, CH1 RK1
6915 22:13:01.254436
6916 22:13:01.257571 DATLAT Default: 0xe
6917 22:13:01.257654 0, 0xFFFF, sum = 0
6918 22:13:01.260825 1, 0xFFFF, sum = 0
6919 22:13:01.264388 2, 0xFFFF, sum = 0
6920 22:13:01.264472 3, 0xFFFF, sum = 0
6921 22:13:01.267831 4, 0xFFFF, sum = 0
6922 22:13:01.267940 5, 0xFFFF, sum = 0
6923 22:13:01.270885 6, 0xFFFF, sum = 0
6924 22:13:01.270970 7, 0xFFFF, sum = 0
6925 22:13:01.274459 8, 0xFFFF, sum = 0
6926 22:13:01.274543 9, 0xFFFF, sum = 0
6927 22:13:01.277685 10, 0xFFFF, sum = 0
6928 22:13:01.277770 11, 0xFFFF, sum = 0
6929 22:13:01.280953 12, 0xFFFF, sum = 0
6930 22:13:01.281037 13, 0x0, sum = 1
6931 22:13:01.284359 14, 0x0, sum = 2
6932 22:13:01.284443 15, 0x0, sum = 3
6933 22:13:01.287290 16, 0x0, sum = 4
6934 22:13:01.287379 best_step = 14
6935 22:13:01.287463
6936 22:13:01.287542 ==
6937 22:13:01.290663 Dram Type= 6, Freq= 0, CH_1, rank 1
6938 22:13:01.294142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6939 22:13:01.297206 ==
6940 22:13:01.297289 RX Vref Scan: 0
6941 22:13:01.297372
6942 22:13:01.300511 RX Vref 0 -> 0, step: 1
6943 22:13:01.300594
6944 22:13:01.303939 RX Delay -359 -> 252, step: 8
6945 22:13:01.310742 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6946 22:13:01.314422 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
6947 22:13:01.317283 iDelay=217, Bit 2, Center -52 (-295 ~ 192) 488
6948 22:13:01.320815 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6949 22:13:01.327173 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6950 22:13:01.330338 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6951 22:13:01.333835 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6952 22:13:01.337084 iDelay=217, Bit 7, Center -44 (-287 ~ 200) 488
6953 22:13:01.343812 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6954 22:13:01.347182 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
6955 22:13:01.350255 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6956 22:13:01.353975 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6957 22:13:01.360389 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6958 22:13:01.363853 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6959 22:13:01.366869 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6960 22:13:01.370725 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6961 22:13:01.370808 ==
6962 22:13:01.373807 Dram Type= 6, Freq= 0, CH_1, rank 1
6963 22:13:01.380202 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6964 22:13:01.380285 ==
6965 22:13:01.380352 DQS Delay:
6966 22:13:01.383891 DQS0 = 52, DQS1 = 56
6967 22:13:01.384013 DQM Delay:
6968 22:13:01.387090 DQM0 = 14, DQM1 = 9
6969 22:13:01.387172 DQ Delay:
6970 22:13:01.390213 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =16
6971 22:13:01.393768 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =8
6972 22:13:01.393856 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
6973 22:13:01.400191 DQ12 =12, DQ13 =16, DQ14 =16, DQ15 =16
6974 22:13:01.400273
6975 22:13:01.400339
6976 22:13:01.406714 [DQSOSCAuto] RK1, (LSB)MR18= 0x7186, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 395 ps
6977 22:13:01.410264 CH1 RK1: MR19=C0C, MR18=7186
6978 22:13:01.416980 CH1_RK1: MR19=0xC0C, MR18=0x7186, DQSOSC=393, MR23=63, INC=382, DEC=254
6979 22:13:01.419976 [RxdqsGatingPostProcess] freq 400
6980 22:13:01.423258 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6981 22:13:01.427005 best DQS0 dly(2T, 0.5T) = (0, 10)
6982 22:13:01.430138 best DQS1 dly(2T, 0.5T) = (0, 10)
6983 22:13:01.433785 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6984 22:13:01.436658 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6985 22:13:01.440173 best DQS0 dly(2T, 0.5T) = (0, 10)
6986 22:13:01.443269 best DQS1 dly(2T, 0.5T) = (0, 10)
6987 22:13:01.446712 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6988 22:13:01.449855 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6989 22:13:01.453479 Pre-setting of DQS Precalculation
6990 22:13:01.456682 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6991 22:13:01.466507 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6992 22:13:01.472977 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6993 22:13:01.473061
6994 22:13:01.473126
6995 22:13:01.476241 [Calibration Summary] 800 Mbps
6996 22:13:01.476323 CH 0, Rank 0
6997 22:13:01.480228 SW Impedance : PASS
6998 22:13:01.480310 DUTY Scan : NO K
6999 22:13:01.483323 ZQ Calibration : PASS
7000 22:13:01.486477 Jitter Meter : NO K
7001 22:13:01.486559 CBT Training : PASS
7002 22:13:01.490150 Write leveling : PASS
7003 22:13:01.493140 RX DQS gating : PASS
7004 22:13:01.493222 RX DQ/DQS(RDDQC) : PASS
7005 22:13:01.496346 TX DQ/DQS : PASS
7006 22:13:01.496429 RX DATLAT : PASS
7007 22:13:01.499700 RX DQ/DQS(Engine): PASS
7008 22:13:01.502861 TX OE : NO K
7009 22:13:01.502944 All Pass.
7010 22:13:01.503009
7011 22:13:01.503068 CH 0, Rank 1
7012 22:13:01.507067 SW Impedance : PASS
7013 22:13:01.509770 DUTY Scan : NO K
7014 22:13:01.509852 ZQ Calibration : PASS
7015 22:13:01.513283 Jitter Meter : NO K
7016 22:13:01.516607 CBT Training : PASS
7017 22:13:01.516689 Write leveling : NO K
7018 22:13:01.520122 RX DQS gating : PASS
7019 22:13:01.522780 RX DQ/DQS(RDDQC) : PASS
7020 22:13:01.522862 TX DQ/DQS : PASS
7021 22:13:01.526173 RX DATLAT : PASS
7022 22:13:01.529427 RX DQ/DQS(Engine): PASS
7023 22:13:01.529510 TX OE : NO K
7024 22:13:01.532709 All Pass.
7025 22:13:01.532792
7026 22:13:01.532858 CH 1, Rank 0
7027 22:13:01.536288 SW Impedance : PASS
7028 22:13:01.536371 DUTY Scan : NO K
7029 22:13:01.539686 ZQ Calibration : PASS
7030 22:13:01.543006 Jitter Meter : NO K
7031 22:13:01.543109 CBT Training : PASS
7032 22:13:01.546352 Write leveling : PASS
7033 22:13:01.549621 RX DQS gating : PASS
7034 22:13:01.549706 RX DQ/DQS(RDDQC) : PASS
7035 22:13:01.552864 TX DQ/DQS : PASS
7036 22:13:01.552946 RX DATLAT : PASS
7037 22:13:01.556013 RX DQ/DQS(Engine): PASS
7038 22:13:01.559484 TX OE : NO K
7039 22:13:01.559567 All Pass.
7040 22:13:01.559632
7041 22:13:01.562609 CH 1, Rank 1
7042 22:13:01.562691 SW Impedance : PASS
7043 22:13:01.565974 DUTY Scan : NO K
7044 22:13:01.566056 ZQ Calibration : PASS
7045 22:13:01.569572 Jitter Meter : NO K
7046 22:13:01.572776 CBT Training : PASS
7047 22:13:01.572858 Write leveling : NO K
7048 22:13:01.576285 RX DQS gating : PASS
7049 22:13:01.579033 RX DQ/DQS(RDDQC) : PASS
7050 22:13:01.579114 TX DQ/DQS : PASS
7051 22:13:01.582623 RX DATLAT : PASS
7052 22:13:01.586434 RX DQ/DQS(Engine): PASS
7053 22:13:01.586517 TX OE : NO K
7054 22:13:01.589350 All Pass.
7055 22:13:01.589432
7056 22:13:01.589498 DramC Write-DBI off
7057 22:13:01.592804 PER_BANK_REFRESH: Hybrid Mode
7058 22:13:01.592886 TX_TRACKING: ON
7059 22:13:01.602590 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7060 22:13:01.606114 [FAST_K] Save calibration result to emmc
7061 22:13:01.608893 dramc_set_vcore_voltage set vcore to 725000
7062 22:13:01.612641 Read voltage for 1600, 0
7063 22:13:01.612723 Vio18 = 0
7064 22:13:01.616106 Vcore = 725000
7065 22:13:01.616188 Vdram = 0
7066 22:13:01.616254 Vddq = 0
7067 22:13:01.619034 Vmddr = 0
7068 22:13:01.622397 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7069 22:13:01.629968 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7070 22:13:01.630053 MEM_TYPE=3, freq_sel=13
7071 22:13:01.632267 sv_algorithm_assistance_LP4_3733
7072 22:13:01.639102 ============ PULL DRAM RESETB DOWN ============
7073 22:13:01.642802 ========== PULL DRAM RESETB DOWN end =========
7074 22:13:01.645660 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7075 22:13:01.649199 ===================================
7076 22:13:01.652243 LPDDR4 DRAM CONFIGURATION
7077 22:13:01.655474 ===================================
7078 22:13:01.655588 EX_ROW_EN[0] = 0x0
7079 22:13:01.658992 EX_ROW_EN[1] = 0x0
7080 22:13:01.662566 LP4Y_EN = 0x0
7081 22:13:01.662648 WORK_FSP = 0x1
7082 22:13:01.665764 WL = 0x5
7083 22:13:01.665846 RL = 0x5
7084 22:13:01.668918 BL = 0x2
7085 22:13:01.669000 RPST = 0x0
7086 22:13:01.672111 RD_PRE = 0x0
7087 22:13:01.672193 WR_PRE = 0x1
7088 22:13:01.675645 WR_PST = 0x1
7089 22:13:01.675727 DBI_WR = 0x0
7090 22:13:01.678927 DBI_RD = 0x0
7091 22:13:01.679009 OTF = 0x1
7092 22:13:01.682300 ===================================
7093 22:13:01.685341 ===================================
7094 22:13:01.688667 ANA top config
7095 22:13:01.692014 ===================================
7096 22:13:01.692117 DLL_ASYNC_EN = 0
7097 22:13:01.695505 ALL_SLAVE_EN = 0
7098 22:13:01.698798 NEW_RANK_MODE = 1
7099 22:13:01.701895 DLL_IDLE_MODE = 1
7100 22:13:01.705583 LP45_APHY_COMB_EN = 1
7101 22:13:01.705665 TX_ODT_DIS = 0
7102 22:13:01.709043 NEW_8X_MODE = 1
7103 22:13:01.712222 ===================================
7104 22:13:01.716032 ===================================
7105 22:13:01.718619 data_rate = 3200
7106 22:13:01.721870 CKR = 1
7107 22:13:01.725216 DQ_P2S_RATIO = 8
7108 22:13:01.728458 ===================================
7109 22:13:01.728545 CA_P2S_RATIO = 8
7110 22:13:01.731835 DQ_CA_OPEN = 0
7111 22:13:01.735124 DQ_SEMI_OPEN = 0
7112 22:13:01.738352 CA_SEMI_OPEN = 0
7113 22:13:01.741657 CA_FULL_RATE = 0
7114 22:13:01.745283 DQ_CKDIV4_EN = 0
7115 22:13:01.745365 CA_CKDIV4_EN = 0
7116 22:13:01.748407 CA_PREDIV_EN = 0
7117 22:13:01.751665 PH8_DLY = 12
7118 22:13:01.754874 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7119 22:13:01.758472 DQ_AAMCK_DIV = 4
7120 22:13:01.761410 CA_AAMCK_DIV = 4
7121 22:13:01.765127 CA_ADMCK_DIV = 4
7122 22:13:01.765213 DQ_TRACK_CA_EN = 0
7123 22:13:01.768365 CA_PICK = 1600
7124 22:13:01.771828 CA_MCKIO = 1600
7125 22:13:01.774808 MCKIO_SEMI = 0
7126 22:13:01.778471 PLL_FREQ = 3068
7127 22:13:01.781377 DQ_UI_PI_RATIO = 32
7128 22:13:01.784651 CA_UI_PI_RATIO = 0
7129 22:13:01.788451 ===================================
7130 22:13:01.791516 ===================================
7131 22:13:01.791599 memory_type:LPDDR4
7132 22:13:01.794650 GP_NUM : 10
7133 22:13:01.797812 SRAM_EN : 1
7134 22:13:01.797896 MD32_EN : 0
7135 22:13:01.801207 ===================================
7136 22:13:01.804746 [ANA_INIT] >>>>>>>>>>>>>>
7137 22:13:01.807808 <<<<<< [CONFIGURE PHASE]: ANA_TX
7138 22:13:01.811061 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7139 22:13:01.814419 ===================================
7140 22:13:01.818241 data_rate = 3200,PCW = 0X7600
7141 22:13:01.821519 ===================================
7142 22:13:01.824599 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7143 22:13:01.827819 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7144 22:13:01.834204 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7145 22:13:01.837542 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7146 22:13:01.841287 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7147 22:13:01.844618 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7148 22:13:01.847730 [ANA_INIT] flow start
7149 22:13:01.851159 [ANA_INIT] PLL >>>>>>>>
7150 22:13:01.851243 [ANA_INIT] PLL <<<<<<<<
7151 22:13:01.854410 [ANA_INIT] MIDPI >>>>>>>>
7152 22:13:01.857556 [ANA_INIT] MIDPI <<<<<<<<
7153 22:13:01.857638 [ANA_INIT] DLL >>>>>>>>
7154 22:13:01.861784 [ANA_INIT] DLL <<<<<<<<
7155 22:13:01.864848 [ANA_INIT] flow end
7156 22:13:01.867746 ============ LP4 DIFF to SE enter ============
7157 22:13:01.871445 ============ LP4 DIFF to SE exit ============
7158 22:13:01.874590 [ANA_INIT] <<<<<<<<<<<<<
7159 22:13:01.877789 [Flow] Enable top DCM control >>>>>
7160 22:13:01.880644 [Flow] Enable top DCM control <<<<<
7161 22:13:01.884179 Enable DLL master slave shuffle
7162 22:13:01.887739 ==============================================================
7163 22:13:01.890848 Gating Mode config
7164 22:13:01.897797 ==============================================================
7165 22:13:01.897881 Config description:
7166 22:13:01.907871 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7167 22:13:01.914553 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7168 22:13:01.920888 SELPH_MODE 0: By rank 1: By Phase
7169 22:13:01.923862 ==============================================================
7170 22:13:01.927118 GAT_TRACK_EN = 1
7171 22:13:01.931107 RX_GATING_MODE = 2
7172 22:13:01.933669 RX_GATING_TRACK_MODE = 2
7173 22:13:01.937761 SELPH_MODE = 1
7174 22:13:01.940390 PICG_EARLY_EN = 1
7175 22:13:01.943814 VALID_LAT_VALUE = 1
7176 22:13:01.947507 ==============================================================
7177 22:13:01.950463 Enter into Gating configuration >>>>
7178 22:13:01.953757 Exit from Gating configuration <<<<
7179 22:13:01.957267 Enter into DVFS_PRE_config >>>>>
7180 22:13:01.970622 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7181 22:13:01.973456 Exit from DVFS_PRE_config <<<<<
7182 22:13:01.977098 Enter into PICG configuration >>>>
7183 22:13:01.980374 Exit from PICG configuration <<<<
7184 22:13:01.980462 [RX_INPUT] configuration >>>>>
7185 22:13:01.983697 [RX_INPUT] configuration <<<<<
7186 22:13:01.990022 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7187 22:13:01.993468 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7188 22:13:02.000350 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7189 22:13:02.006614 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7190 22:13:02.013269 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7191 22:13:02.020133 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7192 22:13:02.023590 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7193 22:13:02.026576 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7194 22:13:02.029960 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7195 22:13:02.036651 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7196 22:13:02.039760 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7197 22:13:02.043073 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7198 22:13:02.046692 ===================================
7199 22:13:02.050127 LPDDR4 DRAM CONFIGURATION
7200 22:13:02.053259 ===================================
7201 22:13:02.056610 EX_ROW_EN[0] = 0x0
7202 22:13:02.056693 EX_ROW_EN[1] = 0x0
7203 22:13:02.059698 LP4Y_EN = 0x0
7204 22:13:02.059781 WORK_FSP = 0x1
7205 22:13:02.063327 WL = 0x5
7206 22:13:02.063410 RL = 0x5
7207 22:13:02.066435 BL = 0x2
7208 22:13:02.066518 RPST = 0x0
7209 22:13:02.069858 RD_PRE = 0x0
7210 22:13:02.069941 WR_PRE = 0x1
7211 22:13:02.073135 WR_PST = 0x1
7212 22:13:02.073218 DBI_WR = 0x0
7213 22:13:02.076746 DBI_RD = 0x0
7214 22:13:02.076829 OTF = 0x1
7215 22:13:02.080719 ===================================
7216 22:13:02.087032 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7217 22:13:02.089925 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7218 22:13:02.093092 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7219 22:13:02.096455 ===================================
7220 22:13:02.099622 LPDDR4 DRAM CONFIGURATION
7221 22:13:02.103240 ===================================
7222 22:13:02.106349 EX_ROW_EN[0] = 0x10
7223 22:13:02.106424 EX_ROW_EN[1] = 0x0
7224 22:13:02.109527 LP4Y_EN = 0x0
7225 22:13:02.109598 WORK_FSP = 0x1
7226 22:13:02.112732 WL = 0x5
7227 22:13:02.112827 RL = 0x5
7228 22:13:02.116253 BL = 0x2
7229 22:13:02.116323 RPST = 0x0
7230 22:13:02.119705 RD_PRE = 0x0
7231 22:13:02.119810 WR_PRE = 0x1
7232 22:13:02.123374 WR_PST = 0x1
7233 22:13:02.123452 DBI_WR = 0x0
7234 22:13:02.126140 DBI_RD = 0x0
7235 22:13:02.126238 OTF = 0x1
7236 22:13:02.129733 ===================================
7237 22:13:02.136070 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7238 22:13:02.136158 ==
7239 22:13:02.139319 Dram Type= 6, Freq= 0, CH_0, rank 0
7240 22:13:02.146782 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7241 22:13:02.146861 ==
7242 22:13:02.146938 [Duty_Offset_Calibration]
7243 22:13:02.149692 B0:2 B1:-1 CA:1
7244 22:13:02.149793
7245 22:13:02.152586 [DutyScan_Calibration_Flow] k_type=0
7246 22:13:02.161048
7247 22:13:02.161124 ==CLK 0==
7248 22:13:02.164339 Final CLK duty delay cell = -4
7249 22:13:02.168144 [-4] MAX Duty = 5031%(X100), DQS PI = 22
7250 22:13:02.171383 [-4] MIN Duty = 4844%(X100), DQS PI = 32
7251 22:13:02.174526 [-4] AVG Duty = 4937%(X100)
7252 22:13:02.174632
7253 22:13:02.177957 CH0 CLK Duty spec in!! Max-Min= 187%
7254 22:13:02.181545 [DutyScan_Calibration_Flow] ====Done====
7255 22:13:02.181642
7256 22:13:02.184764 [DutyScan_Calibration_Flow] k_type=1
7257 22:13:02.200943
7258 22:13:02.201021 ==DQS 0 ==
7259 22:13:02.204081 Final DQS duty delay cell = 0
7260 22:13:02.207512 [0] MAX Duty = 5125%(X100), DQS PI = 20
7261 22:13:02.210596 [0] MIN Duty = 5000%(X100), DQS PI = 14
7262 22:13:02.214333 [0] AVG Duty = 5062%(X100)
7263 22:13:02.214405
7264 22:13:02.214465 ==DQS 1 ==
7265 22:13:02.217186 Final DQS duty delay cell = -4
7266 22:13:02.220900 [-4] MAX Duty = 5093%(X100), DQS PI = 0
7267 22:13:02.223796 [-4] MIN Duty = 5000%(X100), DQS PI = 42
7268 22:13:02.227246 [-4] AVG Duty = 5046%(X100)
7269 22:13:02.227330
7270 22:13:02.230718 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7271 22:13:02.230804
7272 22:13:02.234298 CH0 DQS 1 Duty spec in!! Max-Min= 93%
7273 22:13:02.237164 [DutyScan_Calibration_Flow] ====Done====
7274 22:13:02.237249
7275 22:13:02.240643 [DutyScan_Calibration_Flow] k_type=3
7276 22:13:02.258002
7277 22:13:02.258087 ==DQM 0 ==
7278 22:13:02.261401 Final DQM duty delay cell = 0
7279 22:13:02.265054 [0] MAX Duty = 5000%(X100), DQS PI = 20
7280 22:13:02.268203 [0] MIN Duty = 4875%(X100), DQS PI = 6
7281 22:13:02.268289 [0] AVG Duty = 4937%(X100)
7282 22:13:02.271637
7283 22:13:02.271722 ==DQM 1 ==
7284 22:13:02.274555 Final DQM duty delay cell = 0
7285 22:13:02.278255 [0] MAX Duty = 5218%(X100), DQS PI = 60
7286 22:13:02.281490 [0] MIN Duty = 4969%(X100), DQS PI = 18
7287 22:13:02.284853 [0] AVG Duty = 5093%(X100)
7288 22:13:02.284938
7289 22:13:02.287924 CH0 DQM 0 Duty spec in!! Max-Min= 125%
7290 22:13:02.288050
7291 22:13:02.291473 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7292 22:13:02.294404 [DutyScan_Calibration_Flow] ====Done====
7293 22:13:02.294511
7294 22:13:02.297821 [DutyScan_Calibration_Flow] k_type=2
7295 22:13:02.314456
7296 22:13:02.314538 ==DQ 0 ==
7297 22:13:02.318206 Final DQ duty delay cell = -4
7298 22:13:02.321266 [-4] MAX Duty = 5000%(X100), DQS PI = 0
7299 22:13:02.324265 [-4] MIN Duty = 4844%(X100), DQS PI = 28
7300 22:13:02.327791 [-4] AVG Duty = 4922%(X100)
7301 22:13:02.327872
7302 22:13:02.327937 ==DQ 1 ==
7303 22:13:02.331554 Final DQ duty delay cell = 0
7304 22:13:02.334766 [0] MAX Duty = 5031%(X100), DQS PI = 14
7305 22:13:02.337935 [0] MIN Duty = 4938%(X100), DQS PI = 8
7306 22:13:02.338016 [0] AVG Duty = 4984%(X100)
7307 22:13:02.340917
7308 22:13:02.344791 CH0 DQ 0 Duty spec in!! Max-Min= 156%
7309 22:13:02.344873
7310 22:13:02.347995 CH0 DQ 1 Duty spec in!! Max-Min= 93%
7311 22:13:02.350989 [DutyScan_Calibration_Flow] ====Done====
7312 22:13:02.351070 ==
7313 22:13:02.354531 Dram Type= 6, Freq= 0, CH_1, rank 0
7314 22:13:02.357888 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7315 22:13:02.357970 ==
7316 22:13:02.360837 [Duty_Offset_Calibration]
7317 22:13:02.360918 B0:1 B1:1 CA:2
7318 22:13:02.360983
7319 22:13:02.364558 [DutyScan_Calibration_Flow] k_type=0
7320 22:13:02.374701
7321 22:13:02.374781 ==CLK 0==
7322 22:13:02.378505 Final CLK duty delay cell = 0
7323 22:13:02.381166 [0] MAX Duty = 5187%(X100), DQS PI = 24
7324 22:13:02.384680 [0] MIN Duty = 4938%(X100), DQS PI = 50
7325 22:13:02.387914 [0] AVG Duty = 5062%(X100)
7326 22:13:02.388002
7327 22:13:02.391711 CH1 CLK Duty spec in!! Max-Min= 249%
7328 22:13:02.394801 [DutyScan_Calibration_Flow] ====Done====
7329 22:13:02.394881
7330 22:13:02.397988 [DutyScan_Calibration_Flow] k_type=1
7331 22:13:02.414581
7332 22:13:02.414662 ==DQS 0 ==
7333 22:13:02.417717 Final DQS duty delay cell = 0
7334 22:13:02.421242 [0] MAX Duty = 5062%(X100), DQS PI = 22
7335 22:13:02.424558 [0] MIN Duty = 4813%(X100), DQS PI = 52
7336 22:13:02.428501 [0] AVG Duty = 4937%(X100)
7337 22:13:02.428572
7338 22:13:02.428637 ==DQS 1 ==
7339 22:13:02.431159 Final DQS duty delay cell = 0
7340 22:13:02.434238 [0] MAX Duty = 5031%(X100), DQS PI = 34
7341 22:13:02.437460 [0] MIN Duty = 4938%(X100), DQS PI = 12
7342 22:13:02.440752 [0] AVG Duty = 4984%(X100)
7343 22:13:02.440833
7344 22:13:02.444855 CH1 DQS 0 Duty spec in!! Max-Min= 249%
7345 22:13:02.444936
7346 22:13:02.447521 CH1 DQS 1 Duty spec in!! Max-Min= 93%
7347 22:13:02.451106 [DutyScan_Calibration_Flow] ====Done====
7348 22:13:02.451187
7349 22:13:02.454692 [DutyScan_Calibration_Flow] k_type=3
7350 22:13:02.472088
7351 22:13:02.472173 ==DQM 0 ==
7352 22:13:02.474906 Final DQM duty delay cell = 0
7353 22:13:02.478224 [0] MAX Duty = 5156%(X100), DQS PI = 22
7354 22:13:02.481563 [0] MIN Duty = 4844%(X100), DQS PI = 52
7355 22:13:02.484595 [0] AVG Duty = 5000%(X100)
7356 22:13:02.484680
7357 22:13:02.484765 ==DQM 1 ==
7358 22:13:02.487889 Final DQM duty delay cell = 0
7359 22:13:02.491378 [0] MAX Duty = 5156%(X100), DQS PI = 62
7360 22:13:02.494443 [0] MIN Duty = 4875%(X100), DQS PI = 22
7361 22:13:02.497642 [0] AVG Duty = 5015%(X100)
7362 22:13:02.497727
7363 22:13:02.500648 CH1 DQM 0 Duty spec in!! Max-Min= 312%
7364 22:13:02.500733
7365 22:13:02.504025 CH1 DQM 1 Duty spec in!! Max-Min= 281%
7366 22:13:02.507315 [DutyScan_Calibration_Flow] ====Done====
7367 22:13:02.507396
7368 22:13:02.511147 [DutyScan_Calibration_Flow] k_type=2
7369 22:13:02.528041
7370 22:13:02.528129 ==DQ 0 ==
7371 22:13:02.531504 Final DQ duty delay cell = 0
7372 22:13:02.534559 [0] MAX Duty = 5156%(X100), DQS PI = 20
7373 22:13:02.537977 [0] MIN Duty = 4907%(X100), DQS PI = 52
7374 22:13:02.538058 [0] AVG Duty = 5031%(X100)
7375 22:13:02.541548
7376 22:13:02.541629 ==DQ 1 ==
7377 22:13:02.544405 Final DQ duty delay cell = 0
7378 22:13:02.548128 [0] MAX Duty = 5093%(X100), DQS PI = 8
7379 22:13:02.551087 [0] MIN Duty = 5031%(X100), DQS PI = 0
7380 22:13:02.551168 [0] AVG Duty = 5062%(X100)
7381 22:13:02.554461
7382 22:13:02.557781 CH1 DQ 0 Duty spec in!! Max-Min= 249%
7383 22:13:02.557862
7384 22:13:02.560915 CH1 DQ 1 Duty spec in!! Max-Min= 62%
7385 22:13:02.564572 [DutyScan_Calibration_Flow] ====Done====
7386 22:13:02.568302 nWR fixed to 30
7387 22:13:02.568384 [ModeRegInit_LP4] CH0 RK0
7388 22:13:02.571166 [ModeRegInit_LP4] CH0 RK1
7389 22:13:02.574439 [ModeRegInit_LP4] CH1 RK0
7390 22:13:02.577746 [ModeRegInit_LP4] CH1 RK1
7391 22:13:02.577845 match AC timing 5
7392 22:13:02.584815 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7393 22:13:02.587368 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7394 22:13:02.590826 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7395 22:13:02.597455 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7396 22:13:02.600905 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7397 22:13:02.600987 [MiockJmeterHQA]
7398 22:13:02.601052
7399 22:13:02.604341 [DramcMiockJmeter] u1RxGatingPI = 0
7400 22:13:02.607485 0 : 4252, 4027
7401 22:13:02.607572 4 : 4363, 4137
7402 22:13:02.607672 8 : 4253, 4026
7403 22:13:02.610812 12 : 4253, 4027
7404 22:13:02.610895 16 : 4255, 4029
7405 22:13:02.614099 20 : 4252, 4027
7406 22:13:02.614181 24 : 4363, 4137
7407 22:13:02.617375 28 : 4363, 4138
7408 22:13:02.617477 32 : 4252, 4026
7409 22:13:02.620699 36 : 4252, 4027
7410 22:13:02.620781 40 : 4252, 4027
7411 22:13:02.620848 44 : 4252, 4026
7412 22:13:02.623901 48 : 4255, 4029
7413 22:13:02.624019 52 : 4363, 4137
7414 22:13:02.627557 56 : 4250, 4027
7415 22:13:02.627640 60 : 4250, 4027
7416 22:13:02.631104 64 : 4250, 4026
7417 22:13:02.631186 68 : 4253, 4029
7418 22:13:02.634229 72 : 4250, 4027
7419 22:13:02.634313 76 : 4361, 4137
7420 22:13:02.634380 80 : 4361, 4137
7421 22:13:02.637596 84 : 4252, 4026
7422 22:13:02.637671 88 : 4252, 4027
7423 22:13:02.640868 92 : 4250, 4027
7424 22:13:02.640951 96 : 4250, 3204
7425 22:13:02.643906 100 : 4253, 0
7426 22:13:02.644028 104 : 4250, 0
7427 22:13:02.644096 108 : 4361, 0
7428 22:13:02.647246 112 : 4360, 0
7429 22:13:02.647334 116 : 4250, 0
7430 22:13:02.650622 120 : 4250, 0
7431 22:13:02.650706 124 : 4250, 0
7432 22:13:02.650773 128 : 4250, 0
7433 22:13:02.654029 132 : 4250, 0
7434 22:13:02.654112 136 : 4249, 0
7435 22:13:02.657088 140 : 4253, 0
7436 22:13:02.657171 144 : 4250, 0
7437 22:13:02.657237 148 : 4249, 0
7438 22:13:02.660528 152 : 4253, 0
7439 22:13:02.660611 156 : 4361, 0
7440 22:13:02.663876 160 : 4360, 0
7441 22:13:02.664004 164 : 4363, 0
7442 22:13:02.664101 168 : 4250, 0
7443 22:13:02.666882 172 : 4250, 0
7444 22:13:02.666965 176 : 4250, 0
7445 22:13:02.667033 180 : 4250, 0
7446 22:13:02.670587 184 : 4250, 0
7447 22:13:02.670670 188 : 4250, 0
7448 22:13:02.673507 192 : 4252, 0
7449 22:13:02.673590 196 : 4250, 0
7450 22:13:02.673657 200 : 4249, 0
7451 22:13:02.677145 204 : 4252, 0
7452 22:13:02.677228 208 : 4361, 0
7453 22:13:02.680772 212 : 4360, 231
7454 22:13:02.680854 216 : 4250, 3860
7455 22:13:02.683212 220 : 4250, 4027
7456 22:13:02.683295 224 : 4250, 4027
7457 22:13:02.687147 228 : 4250, 4027
7458 22:13:02.687230 232 : 4363, 4137
7459 22:13:02.690291 236 : 4250, 4027
7460 22:13:02.690375 240 : 4250, 4027
7461 22:13:02.690442 244 : 4361, 4137
7462 22:13:02.693744 248 : 4250, 4026
7463 22:13:02.693827 252 : 4250, 4027
7464 22:13:02.696554 256 : 4363, 4140
7465 22:13:02.696637 260 : 4249, 4027
7466 22:13:02.700119 264 : 4252, 4026
7467 22:13:02.700202 268 : 4250, 4027
7468 22:13:02.703318 272 : 4252, 4029
7469 22:13:02.703401 276 : 4249, 4027
7470 22:13:02.706588 280 : 4250, 4027
7471 22:13:02.706670 284 : 4361, 4137
7472 22:13:02.709770 288 : 4250, 4027
7473 22:13:02.709853 292 : 4250, 4027
7474 22:13:02.713270 296 : 4361, 4137
7475 22:13:02.713353 300 : 4252, 4029
7476 22:13:02.713421 304 : 4250, 4027
7477 22:13:02.716721 308 : 4363, 4140
7478 22:13:02.716804 312 : 4250, 4027
7479 22:13:02.720094 316 : 4250, 4026
7480 22:13:02.720178 320 : 4250, 4027
7481 22:13:02.723088 324 : 4252, 4029
7482 22:13:02.723171 328 : 4249, 4027
7483 22:13:02.726910 332 : 4250, 3035
7484 22:13:02.726993 336 : 4361, 59
7485 22:13:02.727060
7486 22:13:02.729880 MIOCK jitter meter ch=0
7487 22:13:02.729962
7488 22:13:02.733433 1T = (336-100) = 236 dly cells
7489 22:13:02.736599 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7490 22:13:02.739997 ==
7491 22:13:02.740095 Dram Type= 6, Freq= 0, CH_0, rank 0
7492 22:13:02.746209 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7493 22:13:02.746293 ==
7494 22:13:02.749600 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7495 22:13:02.756651 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7496 22:13:02.760100 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7497 22:13:02.765884 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7498 22:13:02.774553 [CA 0] Center 44 (14~75) winsize 62
7499 22:13:02.777819 [CA 1] Center 44 (13~75) winsize 63
7500 22:13:02.781521 [CA 2] Center 40 (11~69) winsize 59
7501 22:13:02.784942 [CA 3] Center 39 (10~69) winsize 60
7502 22:13:02.787818 [CA 4] Center 38 (8~68) winsize 61
7503 22:13:02.791005 [CA 5] Center 37 (7~67) winsize 61
7504 22:13:02.791087
7505 22:13:02.794781 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7506 22:13:02.794863
7507 22:13:02.798180 [CATrainingPosCal] consider 1 rank data
7508 22:13:02.801657 u2DelayCellTimex100 = 275/100 ps
7509 22:13:02.807732 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7510 22:13:02.811186 CA1 delay=44 (13~75),Diff = 7 PI (24 cell)
7511 22:13:02.814474 CA2 delay=40 (11~69),Diff = 3 PI (10 cell)
7512 22:13:02.817795 CA3 delay=39 (10~69),Diff = 2 PI (7 cell)
7513 22:13:02.821262 CA4 delay=38 (8~68),Diff = 1 PI (3 cell)
7514 22:13:02.824502 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7515 22:13:02.824584
7516 22:13:02.828075 CA PerBit enable=1, Macro0, CA PI delay=37
7517 22:13:02.828157
7518 22:13:02.830987 [CBTSetCACLKResult] CA Dly = 37
7519 22:13:02.834441 CS Dly: 10 (0~41)
7520 22:13:02.837490 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7521 22:13:02.841129 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7522 22:13:02.841212 ==
7523 22:13:02.844162 Dram Type= 6, Freq= 0, CH_0, rank 1
7524 22:13:02.850786 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7525 22:13:02.850868 ==
7526 22:13:02.854194 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7527 22:13:02.861153 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7528 22:13:02.864159 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7529 22:13:02.870993 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7530 22:13:02.878472 [CA 0] Center 44 (13~75) winsize 63
7531 22:13:02.881909 [CA 1] Center 43 (13~74) winsize 62
7532 22:13:02.884964 [CA 2] Center 39 (10~69) winsize 60
7533 22:13:02.888341 [CA 3] Center 39 (9~69) winsize 61
7534 22:13:02.891708 [CA 4] Center 37 (7~67) winsize 61
7535 22:13:02.895271 [CA 5] Center 37 (7~67) winsize 61
7536 22:13:02.895353
7537 22:13:02.898596 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7538 22:13:02.898678
7539 22:13:02.901916 [CATrainingPosCal] consider 2 rank data
7540 22:13:02.905629 u2DelayCellTimex100 = 275/100 ps
7541 22:13:02.911498 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7542 22:13:02.914990 CA1 delay=43 (13~74),Diff = 6 PI (21 cell)
7543 22:13:02.918309 CA2 delay=40 (11~69),Diff = 3 PI (10 cell)
7544 22:13:02.921506 CA3 delay=39 (10~69),Diff = 2 PI (7 cell)
7545 22:13:02.924755 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7546 22:13:02.928563 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7547 22:13:02.928645
7548 22:13:02.931387 CA PerBit enable=1, Macro0, CA PI delay=37
7549 22:13:02.931469
7550 22:13:02.934906 [CBTSetCACLKResult] CA Dly = 37
7551 22:13:02.938349 CS Dly: 11 (0~44)
7552 22:13:02.941682 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7553 22:13:02.945148 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7554 22:13:02.945230
7555 22:13:02.948326 ----->DramcWriteLeveling(PI) begin...
7556 22:13:02.948409 ==
7557 22:13:02.951481 Dram Type= 6, Freq= 0, CH_0, rank 0
7558 22:13:02.958029 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7559 22:13:02.958112 ==
7560 22:13:02.961301 Write leveling (Byte 0): 33 => 33
7561 22:13:02.964651 Write leveling (Byte 1): 27 => 27
7562 22:13:02.964763 DramcWriteLeveling(PI) end<-----
7563 22:13:02.964878
7564 22:13:02.968026 ==
7565 22:13:02.971041 Dram Type= 6, Freq= 0, CH_0, rank 0
7566 22:13:02.974379 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7567 22:13:02.974462 ==
7568 22:13:02.977844 [Gating] SW mode calibration
7569 22:13:02.985066 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7570 22:13:02.987816 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7571 22:13:02.994629 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7572 22:13:02.997988 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7573 22:13:03.001167 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7574 22:13:03.007737 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7575 22:13:03.010925 1 4 16 | B1->B0 | 2323 2727 | 0 1 | (0 0) (1 1)
7576 22:13:03.014135 1 4 20 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
7577 22:13:03.020694 1 4 24 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
7578 22:13:03.023890 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7579 22:13:03.027372 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7580 22:13:03.034070 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7581 22:13:03.037252 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7582 22:13:03.040539 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7583 22:13:03.047616 1 5 16 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 1)
7584 22:13:03.050527 1 5 20 | B1->B0 | 3434 2424 | 1 0 | (1 0) (0 0)
7585 22:13:03.054099 1 5 24 | B1->B0 | 2e2e 2323 | 0 0 | (0 1) (0 0)
7586 22:13:03.060863 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7587 22:13:03.064375 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7588 22:13:03.067330 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7589 22:13:03.074015 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7590 22:13:03.077136 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7591 22:13:03.080586 1 6 16 | B1->B0 | 2323 3d3c | 0 1 | (0 0) (0 0)
7592 22:13:03.087040 1 6 20 | B1->B0 | 2424 4545 | 1 0 | (0 0) (0 0)
7593 22:13:03.090606 1 6 24 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
7594 22:13:03.093720 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7595 22:13:03.100360 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7596 22:13:03.103534 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7597 22:13:03.107132 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7598 22:13:03.113989 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7599 22:13:03.117224 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7600 22:13:03.120596 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7601 22:13:03.127270 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7602 22:13:03.130309 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7603 22:13:03.133688 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7604 22:13:03.140274 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7605 22:13:03.143565 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7606 22:13:03.146786 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7607 22:13:03.150049 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7608 22:13:03.156709 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7609 22:13:03.160548 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7610 22:13:03.163264 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7611 22:13:03.170365 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7612 22:13:03.173591 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7613 22:13:03.176879 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7614 22:13:03.183219 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7615 22:13:03.186777 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7616 22:13:03.190545 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7617 22:13:03.193443 Total UI for P1: 0, mck2ui 16
7618 22:13:03.197063 best dqsien dly found for B0: ( 1, 9, 16)
7619 22:13:03.203731 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7620 22:13:03.203816 Total UI for P1: 0, mck2ui 16
7621 22:13:03.210399 best dqsien dly found for B1: ( 1, 9, 20)
7622 22:13:03.213796 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
7623 22:13:03.216749 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7624 22:13:03.216834
7625 22:13:03.219858 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
7626 22:13:03.223884 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7627 22:13:03.226890 [Gating] SW calibration Done
7628 22:13:03.226975 ==
7629 22:13:03.229792 Dram Type= 6, Freq= 0, CH_0, rank 0
7630 22:13:03.233568 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7631 22:13:03.233653 ==
7632 22:13:03.236615 RX Vref Scan: 0
7633 22:13:03.236728
7634 22:13:03.236800 RX Vref 0 -> 0, step: 1
7635 22:13:03.236895
7636 22:13:03.240333 RX Delay 0 -> 252, step: 8
7637 22:13:03.243440 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
7638 22:13:03.250795 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7639 22:13:03.253251 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7640 22:13:03.256401 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7641 22:13:03.259762 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7642 22:13:03.263186 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7643 22:13:03.269777 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7644 22:13:03.273205 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
7645 22:13:03.276162 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7646 22:13:03.279782 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7647 22:13:03.282877 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7648 22:13:03.289814 iDelay=200, Bit 11, Center 119 (72 ~ 167) 96
7649 22:13:03.293093 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7650 22:13:03.296056 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7651 22:13:03.299338 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7652 22:13:03.306387 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7653 22:13:03.306466 ==
7654 22:13:03.309597 Dram Type= 6, Freq= 0, CH_0, rank 0
7655 22:13:03.312786 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7656 22:13:03.312859 ==
7657 22:13:03.312923 DQS Delay:
7658 22:13:03.316084 DQS0 = 0, DQS1 = 0
7659 22:13:03.316178 DQM Delay:
7660 22:13:03.319419 DQM0 = 132, DQM1 = 125
7661 22:13:03.319520 DQ Delay:
7662 22:13:03.322778 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7663 22:13:03.326592 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
7664 22:13:03.329377 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =119
7665 22:13:03.332534 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7666 22:13:03.332639
7667 22:13:03.332730
7668 22:13:03.332819 ==
7669 22:13:03.335898 Dram Type= 6, Freq= 0, CH_0, rank 0
7670 22:13:03.342537 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7671 22:13:03.342636 ==
7672 22:13:03.342727
7673 22:13:03.342813
7674 22:13:03.345778 TX Vref Scan disable
7675 22:13:03.345873 == TX Byte 0 ==
7676 22:13:03.349803 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7677 22:13:03.356310 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7678 22:13:03.356387 == TX Byte 1 ==
7679 22:13:03.359062 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7680 22:13:03.365951 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7681 22:13:03.366049 ==
7682 22:13:03.369542 Dram Type= 6, Freq= 0, CH_0, rank 0
7683 22:13:03.372651 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7684 22:13:03.372721 ==
7685 22:13:03.387116
7686 22:13:03.390377 TX Vref early break, caculate TX vref
7687 22:13:03.393811 TX Vref=16, minBit 4, minWin=21, winSum=358
7688 22:13:03.397261 TX Vref=18, minBit 7, minWin=21, winSum=363
7689 22:13:03.400677 TX Vref=20, minBit 1, minWin=23, winSum=380
7690 22:13:03.403580 TX Vref=22, minBit 1, minWin=22, winSum=387
7691 22:13:03.407260 TX Vref=24, minBit 7, minWin=23, winSum=398
7692 22:13:03.413711 TX Vref=26, minBit 1, minWin=24, winSum=405
7693 22:13:03.417390 TX Vref=28, minBit 4, minWin=24, winSum=414
7694 22:13:03.420475 TX Vref=30, minBit 0, minWin=25, winSum=414
7695 22:13:03.424070 TX Vref=32, minBit 4, minWin=24, winSum=408
7696 22:13:03.427063 TX Vref=34, minBit 4, minWin=23, winSum=394
7697 22:13:03.430162 TX Vref=36, minBit 0, minWin=23, winSum=390
7698 22:13:03.437253 [TxChooseVref] Worse bit 0, Min win 25, Win sum 414, Final Vref 30
7699 22:13:03.437364
7700 22:13:03.440723 Final TX Range 0 Vref 30
7701 22:13:03.440828
7702 22:13:03.440928 ==
7703 22:13:03.443570 Dram Type= 6, Freq= 0, CH_0, rank 0
7704 22:13:03.446907 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7705 22:13:03.447032 ==
7706 22:13:03.447136
7707 22:13:03.447229
7708 22:13:03.450398 TX Vref Scan disable
7709 22:13:03.456796 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7710 22:13:03.456889 == TX Byte 0 ==
7711 22:13:03.461000 u2DelayCellOfst[0]=14 cells (4 PI)
7712 22:13:03.463907 u2DelayCellOfst[1]=17 cells (5 PI)
7713 22:13:03.467100 u2DelayCellOfst[2]=10 cells (3 PI)
7714 22:13:03.470458 u2DelayCellOfst[3]=14 cells (4 PI)
7715 22:13:03.473556 u2DelayCellOfst[4]=7 cells (2 PI)
7716 22:13:03.476989 u2DelayCellOfst[5]=0 cells (0 PI)
7717 22:13:03.480081 u2DelayCellOfst[6]=17 cells (5 PI)
7718 22:13:03.483340 u2DelayCellOfst[7]=17 cells (5 PI)
7719 22:13:03.487193 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7720 22:13:03.490440 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7721 22:13:03.493434 == TX Byte 1 ==
7722 22:13:03.496485 u2DelayCellOfst[8]=0 cells (0 PI)
7723 22:13:03.499926 u2DelayCellOfst[9]=0 cells (0 PI)
7724 22:13:03.500032 u2DelayCellOfst[10]=7 cells (2 PI)
7725 22:13:03.503748 u2DelayCellOfst[11]=0 cells (0 PI)
7726 22:13:03.506885 u2DelayCellOfst[12]=10 cells (3 PI)
7727 22:13:03.510179 u2DelayCellOfst[13]=10 cells (3 PI)
7728 22:13:03.513086 u2DelayCellOfst[14]=17 cells (5 PI)
7729 22:13:03.517085 u2DelayCellOfst[15]=10 cells (3 PI)
7730 22:13:03.520100 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7731 22:13:03.526854 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7732 22:13:03.526958 DramC Write-DBI on
7733 22:13:03.527039 ==
7734 22:13:03.530050 Dram Type= 6, Freq= 0, CH_0, rank 0
7735 22:13:03.536597 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7736 22:13:03.536703 ==
7737 22:13:03.536798
7738 22:13:03.536895
7739 22:13:03.536993 TX Vref Scan disable
7740 22:13:03.540842 == TX Byte 0 ==
7741 22:13:03.543928 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7742 22:13:03.547481 == TX Byte 1 ==
7743 22:13:03.550428 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
7744 22:13:03.553671 DramC Write-DBI off
7745 22:13:03.553777
7746 22:13:03.553868 [DATLAT]
7747 22:13:03.553958 Freq=1600, CH0 RK0
7748 22:13:03.554047
7749 22:13:03.557409 DATLAT Default: 0xf
7750 22:13:03.557517 0, 0xFFFF, sum = 0
7751 22:13:03.560474 1, 0xFFFF, sum = 0
7752 22:13:03.563743 2, 0xFFFF, sum = 0
7753 22:13:03.563867 3, 0xFFFF, sum = 0
7754 22:13:03.566990 4, 0xFFFF, sum = 0
7755 22:13:03.567120 5, 0xFFFF, sum = 0
7756 22:13:03.570727 6, 0xFFFF, sum = 0
7757 22:13:03.570828 7, 0xFFFF, sum = 0
7758 22:13:03.573928 8, 0xFFFF, sum = 0
7759 22:13:03.574029 9, 0xFFFF, sum = 0
7760 22:13:03.576872 10, 0xFFFF, sum = 0
7761 22:13:03.576951 11, 0xFFFF, sum = 0
7762 22:13:03.580482 12, 0xFFFF, sum = 0
7763 22:13:03.580556 13, 0xFFFF, sum = 0
7764 22:13:03.583616 14, 0x0, sum = 1
7765 22:13:03.583728 15, 0x0, sum = 2
7766 22:13:03.587272 16, 0x0, sum = 3
7767 22:13:03.587373 17, 0x0, sum = 4
7768 22:13:03.591087 best_step = 15
7769 22:13:03.591168
7770 22:13:03.591231 ==
7771 22:13:03.594089 Dram Type= 6, Freq= 0, CH_0, rank 0
7772 22:13:03.597062 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7773 22:13:03.597162 ==
7774 22:13:03.597253 RX Vref Scan: 1
7775 22:13:03.601037
7776 22:13:03.601139 Set Vref Range= 24 -> 127
7777 22:13:03.601233
7778 22:13:03.603763 RX Vref 24 -> 127, step: 1
7779 22:13:03.603859
7780 22:13:03.607277 RX Delay 11 -> 252, step: 4
7781 22:13:03.607376
7782 22:13:03.610562 Set Vref, RX VrefLevel [Byte0]: 24
7783 22:13:03.613639 [Byte1]: 24
7784 22:13:03.613739
7785 22:13:03.617100 Set Vref, RX VrefLevel [Byte0]: 25
7786 22:13:03.620600 [Byte1]: 25
7787 22:13:03.620706
7788 22:13:03.624271 Set Vref, RX VrefLevel [Byte0]: 26
7789 22:13:03.626906 [Byte1]: 26
7790 22:13:03.630997
7791 22:13:03.631084 Set Vref, RX VrefLevel [Byte0]: 27
7792 22:13:03.634288 [Byte1]: 27
7793 22:13:03.638631
7794 22:13:03.638739 Set Vref, RX VrefLevel [Byte0]: 28
7795 22:13:03.645002 [Byte1]: 28
7796 22:13:03.645106
7797 22:13:03.648263 Set Vref, RX VrefLevel [Byte0]: 29
7798 22:13:03.651728 [Byte1]: 29
7799 22:13:03.651828
7800 22:13:03.654773 Set Vref, RX VrefLevel [Byte0]: 30
7801 22:13:03.658413 [Byte1]: 30
7802 22:13:03.658485
7803 22:13:03.661674 Set Vref, RX VrefLevel [Byte0]: 31
7804 22:13:03.665105 [Byte1]: 31
7805 22:13:03.669452
7806 22:13:03.669525 Set Vref, RX VrefLevel [Byte0]: 32
7807 22:13:03.672871 [Byte1]: 32
7808 22:13:03.676729
7809 22:13:03.676801 Set Vref, RX VrefLevel [Byte0]: 33
7810 22:13:03.679915 [Byte1]: 33
7811 22:13:03.684158
7812 22:13:03.684255 Set Vref, RX VrefLevel [Byte0]: 34
7813 22:13:03.687696 [Byte1]: 34
7814 22:13:03.692222
7815 22:13:03.692295 Set Vref, RX VrefLevel [Byte0]: 35
7816 22:13:03.695248 [Byte1]: 35
7817 22:13:03.699749
7818 22:13:03.699849 Set Vref, RX VrefLevel [Byte0]: 36
7819 22:13:03.702782 [Byte1]: 36
7820 22:13:03.707090
7821 22:13:03.707165 Set Vref, RX VrefLevel [Byte0]: 37
7822 22:13:03.710510 [Byte1]: 37
7823 22:13:03.714719
7824 22:13:03.714821 Set Vref, RX VrefLevel [Byte0]: 38
7825 22:13:03.718220 [Byte1]: 38
7826 22:13:03.722659
7827 22:13:03.722769 Set Vref, RX VrefLevel [Byte0]: 39
7828 22:13:03.725466 [Byte1]: 39
7829 22:13:03.729982
7830 22:13:03.730098 Set Vref, RX VrefLevel [Byte0]: 40
7831 22:13:03.733214 [Byte1]: 40
7832 22:13:03.737685
7833 22:13:03.737789 Set Vref, RX VrefLevel [Byte0]: 41
7834 22:13:03.741146 [Byte1]: 41
7835 22:13:03.745000
7836 22:13:03.745109 Set Vref, RX VrefLevel [Byte0]: 42
7837 22:13:03.748798 [Byte1]: 42
7838 22:13:03.752752
7839 22:13:03.752865 Set Vref, RX VrefLevel [Byte0]: 43
7840 22:13:03.756339 [Byte1]: 43
7841 22:13:03.760375
7842 22:13:03.760459 Set Vref, RX VrefLevel [Byte0]: 44
7843 22:13:03.763783 [Byte1]: 44
7844 22:13:03.767824
7845 22:13:03.767936 Set Vref, RX VrefLevel [Byte0]: 45
7846 22:13:03.771364 [Byte1]: 45
7847 22:13:03.775750
7848 22:13:03.775849 Set Vref, RX VrefLevel [Byte0]: 46
7849 22:13:03.779064 [Byte1]: 46
7850 22:13:03.783369
7851 22:13:03.783470 Set Vref, RX VrefLevel [Byte0]: 47
7852 22:13:03.786442 [Byte1]: 47
7853 22:13:03.790999
7854 22:13:03.791102 Set Vref, RX VrefLevel [Byte0]: 48
7855 22:13:03.794529 [Byte1]: 48
7856 22:13:03.798415
7857 22:13:03.798515 Set Vref, RX VrefLevel [Byte0]: 49
7858 22:13:03.801690 [Byte1]: 49
7859 22:13:03.805964
7860 22:13:03.806066 Set Vref, RX VrefLevel [Byte0]: 50
7861 22:13:03.809130 [Byte1]: 50
7862 22:13:03.813789
7863 22:13:03.813889 Set Vref, RX VrefLevel [Byte0]: 51
7864 22:13:03.817306 [Byte1]: 51
7865 22:13:03.821870
7866 22:13:03.821982 Set Vref, RX VrefLevel [Byte0]: 52
7867 22:13:03.824898 [Byte1]: 52
7868 22:13:03.829423
7869 22:13:03.829532 Set Vref, RX VrefLevel [Byte0]: 53
7870 22:13:03.832205 [Byte1]: 53
7871 22:13:03.837091
7872 22:13:03.837174 Set Vref, RX VrefLevel [Byte0]: 54
7873 22:13:03.840071 [Byte1]: 54
7874 22:13:03.844260
7875 22:13:03.844370 Set Vref, RX VrefLevel [Byte0]: 55
7876 22:13:03.847373 [Byte1]: 55
7877 22:13:03.852230
7878 22:13:03.852342 Set Vref, RX VrefLevel [Byte0]: 56
7879 22:13:03.855547 [Byte1]: 56
7880 22:13:03.859713
7881 22:13:03.859796 Set Vref, RX VrefLevel [Byte0]: 57
7882 22:13:03.863115 [Byte1]: 57
7883 22:13:03.866892
7884 22:13:03.866979 Set Vref, RX VrefLevel [Byte0]: 58
7885 22:13:03.870237 [Byte1]: 58
7886 22:13:03.874598
7887 22:13:03.874698 Set Vref, RX VrefLevel [Byte0]: 59
7888 22:13:03.878126 [Byte1]: 59
7889 22:13:03.882420
7890 22:13:03.882503 Set Vref, RX VrefLevel [Byte0]: 60
7891 22:13:03.885329 [Byte1]: 60
7892 22:13:03.889948
7893 22:13:03.890031 Set Vref, RX VrefLevel [Byte0]: 61
7894 22:13:03.893310 [Byte1]: 61
7895 22:13:03.898042
7896 22:13:03.898126 Set Vref, RX VrefLevel [Byte0]: 62
7897 22:13:03.900816 [Byte1]: 62
7898 22:13:03.905475
7899 22:13:03.905558 Set Vref, RX VrefLevel [Byte0]: 63
7900 22:13:03.908160 [Byte1]: 63
7901 22:13:03.912591
7902 22:13:03.912690 Set Vref, RX VrefLevel [Byte0]: 64
7903 22:13:03.916072 [Byte1]: 64
7904 22:13:03.920240
7905 22:13:03.920360 Set Vref, RX VrefLevel [Byte0]: 65
7906 22:13:03.923455 [Byte1]: 65
7907 22:13:03.928237
7908 22:13:03.928326 Set Vref, RX VrefLevel [Byte0]: 66
7909 22:13:03.931434 [Byte1]: 66
7910 22:13:03.935457
7911 22:13:03.935540 Set Vref, RX VrefLevel [Byte0]: 67
7912 22:13:03.938899 [Byte1]: 67
7913 22:13:03.943304
7914 22:13:03.943386 Set Vref, RX VrefLevel [Byte0]: 68
7915 22:13:03.946791 [Byte1]: 68
7916 22:13:03.950834
7917 22:13:03.950932 Set Vref, RX VrefLevel [Byte0]: 69
7918 22:13:03.954093 [Byte1]: 69
7919 22:13:03.958920
7920 22:13:03.959003 Set Vref, RX VrefLevel [Byte0]: 70
7921 22:13:03.962025 [Byte1]: 70
7922 22:13:03.965990
7923 22:13:03.966073 Set Vref, RX VrefLevel [Byte0]: 71
7924 22:13:03.969363 [Byte1]: 71
7925 22:13:03.973453
7926 22:13:03.977198 Set Vref, RX VrefLevel [Byte0]: 72
7927 22:13:03.977281 [Byte1]: 72
7928 22:13:03.981129
7929 22:13:03.981273 Set Vref, RX VrefLevel [Byte0]: 73
7930 22:13:03.984661 [Byte1]: 73
7931 22:13:03.988808
7932 22:13:03.988919 Set Vref, RX VrefLevel [Byte0]: 74
7933 22:13:03.992143 [Byte1]: 74
7934 22:13:03.996776
7935 22:13:03.996859 Set Vref, RX VrefLevel [Byte0]: 75
7936 22:13:03.999870 [Byte1]: 75
7937 22:13:04.003852
7938 22:13:04.003934 Set Vref, RX VrefLevel [Byte0]: 76
7939 22:13:04.007111 [Byte1]: 76
7940 22:13:04.011457
7941 22:13:04.011540 Set Vref, RX VrefLevel [Byte0]: 77
7942 22:13:04.014958 [Byte1]: 77
7943 22:13:04.019329
7944 22:13:04.019411 Final RX Vref Byte 0 = 61 to rank0
7945 22:13:04.022514 Final RX Vref Byte 1 = 63 to rank0
7946 22:13:04.025789 Final RX Vref Byte 0 = 61 to rank1
7947 22:13:04.029157 Final RX Vref Byte 1 = 63 to rank1==
7948 22:13:04.032505 Dram Type= 6, Freq= 0, CH_0, rank 0
7949 22:13:04.039363 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7950 22:13:04.039449 ==
7951 22:13:04.039557 DQS Delay:
7952 22:13:04.042671 DQS0 = 0, DQS1 = 0
7953 22:13:04.042754 DQM Delay:
7954 22:13:04.042820 DQM0 = 129, DQM1 = 123
7955 22:13:04.045956 DQ Delay:
7956 22:13:04.048897 DQ0 =130, DQ1 =132, DQ2 =126, DQ3 =126
7957 22:13:04.052357 DQ4 =132, DQ5 =118, DQ6 =136, DQ7 =138
7958 22:13:04.055976 DQ8 =112, DQ9 =110, DQ10 =122, DQ11 =116
7959 22:13:04.059154 DQ12 =128, DQ13 =128, DQ14 =134, DQ15 =134
7960 22:13:04.059239
7961 22:13:04.059307
7962 22:13:04.059369
7963 22:13:04.062693 [DramC_TX_OE_Calibration] TA2
7964 22:13:04.065932 Original DQ_B0 (3 6) =30, OEN = 27
7965 22:13:04.068757 Original DQ_B1 (3 6) =30, OEN = 27
7966 22:13:04.072159 24, 0x0, End_B0=24 End_B1=24
7967 22:13:04.072243 25, 0x0, End_B0=25 End_B1=25
7968 22:13:04.075601 26, 0x0, End_B0=26 End_B1=26
7969 22:13:04.079399 27, 0x0, End_B0=27 End_B1=27
7970 22:13:04.082508 28, 0x0, End_B0=28 End_B1=28
7971 22:13:04.085382 29, 0x0, End_B0=29 End_B1=29
7972 22:13:04.085466 30, 0x0, End_B0=30 End_B1=30
7973 22:13:04.088908 31, 0x4141, End_B0=30 End_B1=30
7974 22:13:04.092148 Byte0 end_step=30 best_step=27
7975 22:13:04.095360 Byte1 end_step=30 best_step=27
7976 22:13:04.098510 Byte0 TX OE(2T, 0.5T) = (3, 3)
7977 22:13:04.102258 Byte1 TX OE(2T, 0.5T) = (3, 3)
7978 22:13:04.102386
7979 22:13:04.102502
7980 22:13:04.108648 [DQSOSCAuto] RK0, (LSB)MR18= 0x1509, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 399 ps
7981 22:13:04.111769 CH0 RK0: MR19=303, MR18=1509
7982 22:13:04.118563 CH0_RK0: MR19=0x303, MR18=0x1509, DQSOSC=399, MR23=63, INC=23, DEC=15
7983 22:13:04.118648
7984 22:13:04.122068 ----->DramcWriteLeveling(PI) begin...
7985 22:13:04.122154 ==
7986 22:13:04.125760 Dram Type= 6, Freq= 0, CH_0, rank 1
7987 22:13:04.128710 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7988 22:13:04.128787 ==
7989 22:13:04.131906 Write leveling (Byte 0): 32 => 32
7990 22:13:04.135351 Write leveling (Byte 1): 25 => 25
7991 22:13:04.138926 DramcWriteLeveling(PI) end<-----
7992 22:13:04.139027
7993 22:13:04.139118 ==
7994 22:13:04.141757 Dram Type= 6, Freq= 0, CH_0, rank 1
7995 22:13:04.145364 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7996 22:13:04.145456 ==
7997 22:13:04.148343 [Gating] SW mode calibration
7998 22:13:04.155347 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7999 22:13:04.162201 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8000 22:13:04.165150 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8001 22:13:04.171911 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8002 22:13:04.175088 1 4 8 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
8003 22:13:04.178211 1 4 12 | B1->B0 | 2323 3131 | 0 1 | (0 0) (0 0)
8004 22:13:04.181705 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8005 22:13:04.188415 1 4 20 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
8006 22:13:04.191594 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8007 22:13:04.195058 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8008 22:13:04.201554 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8009 22:13:04.204989 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8010 22:13:04.208360 1 5 8 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
8011 22:13:04.214739 1 5 12 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (1 0)
8012 22:13:04.218708 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8013 22:13:04.221235 1 5 20 | B1->B0 | 3232 2323 | 0 0 | (1 0) (0 0)
8014 22:13:04.228161 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8015 22:13:04.231796 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8016 22:13:04.234895 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8017 22:13:04.241360 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8018 22:13:04.244938 1 6 8 | B1->B0 | 2323 3737 | 0 1 | (0 0) (0 0)
8019 22:13:04.248559 1 6 12 | B1->B0 | 2323 4242 | 0 0 | (0 0) (0 0)
8020 22:13:04.255068 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8021 22:13:04.258113 1 6 20 | B1->B0 | 3232 4646 | 0 0 | (0 0) (0 0)
8022 22:13:04.261398 1 6 24 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8023 22:13:04.268189 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8024 22:13:04.271151 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8025 22:13:04.275059 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8026 22:13:04.281379 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8027 22:13:04.284551 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8028 22:13:04.288377 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8029 22:13:04.294600 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8030 22:13:04.298135 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8031 22:13:04.301048 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8032 22:13:04.308160 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8033 22:13:04.310993 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8034 22:13:04.314443 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8035 22:13:04.321279 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8036 22:13:04.324379 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8037 22:13:04.327690 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8038 22:13:04.334246 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8039 22:13:04.337800 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8040 22:13:04.341487 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8041 22:13:04.344464 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8042 22:13:04.351699 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8043 22:13:04.354259 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8044 22:13:04.357783 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8045 22:13:04.361053 Total UI for P1: 0, mck2ui 16
8046 22:13:04.364176 best dqsien dly found for B0: ( 1, 9, 10)
8047 22:13:04.371017 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8048 22:13:04.374256 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8049 22:13:04.377353 Total UI for P1: 0, mck2ui 16
8050 22:13:04.380862 best dqsien dly found for B1: ( 1, 9, 18)
8051 22:13:04.383931 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8052 22:13:04.387601 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8053 22:13:04.387683
8054 22:13:04.390852 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8055 22:13:04.397644 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8056 22:13:04.397727 [Gating] SW calibration Done
8057 22:13:04.397794 ==
8058 22:13:04.401108 Dram Type= 6, Freq= 0, CH_0, rank 1
8059 22:13:04.407245 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8060 22:13:04.407328 ==
8061 22:13:04.407395 RX Vref Scan: 0
8062 22:13:04.407457
8063 22:13:04.410649 RX Vref 0 -> 0, step: 1
8064 22:13:04.410731
8065 22:13:04.414524 RX Delay 0 -> 252, step: 8
8066 22:13:04.417272 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8067 22:13:04.420367 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8068 22:13:04.423709 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8069 22:13:04.427100 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8070 22:13:04.433974 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8071 22:13:04.437123 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8072 22:13:04.440243 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8073 22:13:04.443922 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8074 22:13:04.446821 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8075 22:13:04.453940 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8076 22:13:04.457179 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8077 22:13:04.460523 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8078 22:13:04.463812 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8079 22:13:04.470434 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8080 22:13:04.473724 iDelay=200, Bit 14, Center 135 (72 ~ 199) 128
8081 22:13:04.476876 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8082 22:13:04.476960 ==
8083 22:13:04.480112 Dram Type= 6, Freq= 0, CH_0, rank 1
8084 22:13:04.483599 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8085 22:13:04.483682 ==
8086 22:13:04.486700 DQS Delay:
8087 22:13:04.486782 DQS0 = 0, DQS1 = 0
8088 22:13:04.490095 DQM Delay:
8089 22:13:04.490177 DQM0 = 131, DQM1 = 124
8090 22:13:04.490244 DQ Delay:
8091 22:13:04.493726 DQ0 =131, DQ1 =131, DQ2 =127, DQ3 =131
8092 22:13:04.500591 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
8093 22:13:04.504173 DQ8 =115, DQ9 =115, DQ10 =123, DQ11 =119
8094 22:13:04.507135 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
8095 22:13:04.507218
8096 22:13:04.507284
8097 22:13:04.507346 ==
8098 22:13:04.510404 Dram Type= 6, Freq= 0, CH_0, rank 1
8099 22:13:04.513644 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8100 22:13:04.513727 ==
8101 22:13:04.513793
8102 22:13:04.513853
8103 22:13:04.516889 TX Vref Scan disable
8104 22:13:04.519678 == TX Byte 0 ==
8105 22:13:04.523354 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8106 22:13:04.526388 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8107 22:13:04.530066 == TX Byte 1 ==
8108 22:13:04.533528 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8109 22:13:04.536680 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8110 22:13:04.536763 ==
8111 22:13:04.540238 Dram Type= 6, Freq= 0, CH_0, rank 1
8112 22:13:04.543179 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8113 22:13:04.546559 ==
8114 22:13:04.559820
8115 22:13:04.563505 TX Vref early break, caculate TX vref
8116 22:13:04.566506 TX Vref=16, minBit 1, minWin=22, winSum=366
8117 22:13:04.569431 TX Vref=18, minBit 9, minWin=22, winSum=377
8118 22:13:04.572736 TX Vref=20, minBit 0, minWin=23, winSum=385
8119 22:13:04.576077 TX Vref=22, minBit 1, minWin=24, winSum=396
8120 22:13:04.579553 TX Vref=24, minBit 9, minWin=24, winSum=405
8121 22:13:04.586142 TX Vref=26, minBit 0, minWin=25, winSum=413
8122 22:13:04.589337 TX Vref=28, minBit 4, minWin=25, winSum=414
8123 22:13:04.592747 TX Vref=30, minBit 0, minWin=25, winSum=415
8124 22:13:04.596176 TX Vref=32, minBit 1, minWin=24, winSum=407
8125 22:13:04.599591 TX Vref=34, minBit 1, minWin=23, winSum=399
8126 22:13:04.603479 TX Vref=36, minBit 4, minWin=23, winSum=389
8127 22:13:04.609152 [TxChooseVref] Worse bit 0, Min win 25, Win sum 415, Final Vref 30
8128 22:13:04.609236
8129 22:13:04.612807 Final TX Range 0 Vref 30
8130 22:13:04.612890
8131 22:13:04.612956 ==
8132 22:13:04.615795 Dram Type= 6, Freq= 0, CH_0, rank 1
8133 22:13:04.619153 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8134 22:13:04.619237 ==
8135 22:13:04.619303
8136 22:13:04.619366
8137 22:13:04.622573 TX Vref Scan disable
8138 22:13:04.629603 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8139 22:13:04.629687 == TX Byte 0 ==
8140 22:13:04.632709 u2DelayCellOfst[0]=14 cells (4 PI)
8141 22:13:04.635790 u2DelayCellOfst[1]=21 cells (6 PI)
8142 22:13:04.639259 u2DelayCellOfst[2]=10 cells (3 PI)
8143 22:13:04.642789 u2DelayCellOfst[3]=10 cells (3 PI)
8144 22:13:04.646122 u2DelayCellOfst[4]=10 cells (3 PI)
8145 22:13:04.649096 u2DelayCellOfst[5]=0 cells (0 PI)
8146 22:13:04.652366 u2DelayCellOfst[6]=17 cells (5 PI)
8147 22:13:04.656274 u2DelayCellOfst[7]=21 cells (6 PI)
8148 22:13:04.659098 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
8149 22:13:04.662953 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8150 22:13:04.666240 == TX Byte 1 ==
8151 22:13:04.669685 u2DelayCellOfst[8]=0 cells (0 PI)
8152 22:13:04.672401 u2DelayCellOfst[9]=0 cells (0 PI)
8153 22:13:04.672484 u2DelayCellOfst[10]=3 cells (1 PI)
8154 22:13:04.675559 u2DelayCellOfst[11]=0 cells (0 PI)
8155 22:13:04.679168 u2DelayCellOfst[12]=10 cells (3 PI)
8156 22:13:04.682254 u2DelayCellOfst[13]=10 cells (3 PI)
8157 22:13:04.685845 u2DelayCellOfst[14]=14 cells (4 PI)
8158 22:13:04.689296 u2DelayCellOfst[15]=10 cells (3 PI)
8159 22:13:04.696511 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8160 22:13:04.699218 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8161 22:13:04.699301 DramC Write-DBI on
8162 22:13:04.699378 ==
8163 22:13:04.702418 Dram Type= 6, Freq= 0, CH_0, rank 1
8164 22:13:04.708775 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8165 22:13:04.708874 ==
8166 22:13:04.708943
8167 22:13:04.709006
8168 22:13:04.709065 TX Vref Scan disable
8169 22:13:04.712958 == TX Byte 0 ==
8170 22:13:04.716164 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
8171 22:13:04.719897 == TX Byte 1 ==
8172 22:13:04.723362 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8173 22:13:04.726709 DramC Write-DBI off
8174 22:13:04.726796
8175 22:13:04.726865 [DATLAT]
8176 22:13:04.726926 Freq=1600, CH0 RK1
8177 22:13:04.727007
8178 22:13:04.729959 DATLAT Default: 0xf
8179 22:13:04.730095 0, 0xFFFF, sum = 0
8180 22:13:04.732845 1, 0xFFFF, sum = 0
8181 22:13:04.736472 2, 0xFFFF, sum = 0
8182 22:13:04.736552 3, 0xFFFF, sum = 0
8183 22:13:04.739563 4, 0xFFFF, sum = 0
8184 22:13:04.739637 5, 0xFFFF, sum = 0
8185 22:13:04.742881 6, 0xFFFF, sum = 0
8186 22:13:04.742955 7, 0xFFFF, sum = 0
8187 22:13:04.746798 8, 0xFFFF, sum = 0
8188 22:13:04.746873 9, 0xFFFF, sum = 0
8189 22:13:04.749390 10, 0xFFFF, sum = 0
8190 22:13:04.749464 11, 0xFFFF, sum = 0
8191 22:13:04.753016 12, 0xFFFF, sum = 0
8192 22:13:04.753096 13, 0xFFFF, sum = 0
8193 22:13:04.756848 14, 0x0, sum = 1
8194 22:13:04.756925 15, 0x0, sum = 2
8195 22:13:04.759781 16, 0x0, sum = 3
8196 22:13:04.759919 17, 0x0, sum = 4
8197 22:13:04.762850 best_step = 15
8198 22:13:04.762932
8199 22:13:04.763040 ==
8200 22:13:04.766065 Dram Type= 6, Freq= 0, CH_0, rank 1
8201 22:13:04.769289 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8202 22:13:04.769374 ==
8203 22:13:04.772710 RX Vref Scan: 0
8204 22:13:04.772806
8205 22:13:04.772877 RX Vref 0 -> 0, step: 1
8206 22:13:04.772967
8207 22:13:04.776236 RX Delay 11 -> 252, step: 4
8208 22:13:04.782623 iDelay=195, Bit 0, Center 126 (71 ~ 182) 112
8209 22:13:04.786179 iDelay=195, Bit 1, Center 130 (75 ~ 186) 112
8210 22:13:04.789413 iDelay=195, Bit 2, Center 124 (67 ~ 182) 116
8211 22:13:04.792539 iDelay=195, Bit 3, Center 126 (71 ~ 182) 112
8212 22:13:04.796362 iDelay=195, Bit 4, Center 128 (75 ~ 182) 108
8213 22:13:04.799517 iDelay=195, Bit 5, Center 114 (59 ~ 170) 112
8214 22:13:04.805588 iDelay=195, Bit 6, Center 136 (79 ~ 194) 116
8215 22:13:04.808857 iDelay=195, Bit 7, Center 134 (79 ~ 190) 112
8216 22:13:04.812364 iDelay=195, Bit 8, Center 112 (59 ~ 166) 108
8217 22:13:04.815432 iDelay=195, Bit 9, Center 110 (55 ~ 166) 112
8218 22:13:04.822958 iDelay=195, Bit 10, Center 122 (67 ~ 178) 112
8219 22:13:04.825534 iDelay=195, Bit 11, Center 116 (63 ~ 170) 108
8220 22:13:04.828735 iDelay=195, Bit 12, Center 126 (75 ~ 178) 104
8221 22:13:04.832838 iDelay=195, Bit 13, Center 128 (71 ~ 186) 116
8222 22:13:04.835611 iDelay=195, Bit 14, Center 134 (79 ~ 190) 112
8223 22:13:04.842456 iDelay=195, Bit 15, Center 132 (75 ~ 190) 116
8224 22:13:04.842535 ==
8225 22:13:04.845803 Dram Type= 6, Freq= 0, CH_0, rank 1
8226 22:13:04.848845 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8227 22:13:04.848947 ==
8228 22:13:04.849039 DQS Delay:
8229 22:13:04.852285 DQS0 = 0, DQS1 = 0
8230 22:13:04.852358 DQM Delay:
8231 22:13:04.855385 DQM0 = 127, DQM1 = 122
8232 22:13:04.855457 DQ Delay:
8233 22:13:04.858390 DQ0 =126, DQ1 =130, DQ2 =124, DQ3 =126
8234 22:13:04.862202 DQ4 =128, DQ5 =114, DQ6 =136, DQ7 =134
8235 22:13:04.865572 DQ8 =112, DQ9 =110, DQ10 =122, DQ11 =116
8236 22:13:04.868529 DQ12 =126, DQ13 =128, DQ14 =134, DQ15 =132
8237 22:13:04.872560
8238 22:13:04.872635
8239 22:13:04.872699
8240 22:13:04.872759 [DramC_TX_OE_Calibration] TA2
8241 22:13:04.875222 Original DQ_B0 (3 6) =30, OEN = 27
8242 22:13:04.878465 Original DQ_B1 (3 6) =30, OEN = 27
8243 22:13:04.881734 24, 0x0, End_B0=24 End_B1=24
8244 22:13:04.884739 25, 0x0, End_B0=25 End_B1=25
8245 22:13:04.888655 26, 0x0, End_B0=26 End_B1=26
8246 22:13:04.888741 27, 0x0, End_B0=27 End_B1=27
8247 22:13:04.892216 28, 0x0, End_B0=28 End_B1=28
8248 22:13:04.894836 29, 0x0, End_B0=29 End_B1=29
8249 22:13:04.898145 30, 0x0, End_B0=30 End_B1=30
8250 22:13:04.901678 31, 0x4141, End_B0=30 End_B1=30
8251 22:13:04.904829 Byte0 end_step=30 best_step=27
8252 22:13:04.904936 Byte1 end_step=30 best_step=27
8253 22:13:04.908169 Byte0 TX OE(2T, 0.5T) = (3, 3)
8254 22:13:04.911348 Byte1 TX OE(2T, 0.5T) = (3, 3)
8255 22:13:04.911431
8256 22:13:04.911497
8257 22:13:04.921594 [DQSOSCAuto] RK1, (LSB)MR18= 0x160b, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 398 ps
8258 22:13:04.921679 CH0 RK1: MR19=303, MR18=160B
8259 22:13:04.928585 CH0_RK1: MR19=0x303, MR18=0x160B, DQSOSC=398, MR23=63, INC=23, DEC=15
8260 22:13:04.931819 [RxdqsGatingPostProcess] freq 1600
8261 22:13:04.938026 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8262 22:13:04.941273 best DQS0 dly(2T, 0.5T) = (1, 1)
8263 22:13:04.944933 best DQS1 dly(2T, 0.5T) = (1, 1)
8264 22:13:04.948142 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8265 22:13:04.950864 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8266 22:13:04.950938 best DQS0 dly(2T, 0.5T) = (1, 1)
8267 22:13:04.954202 best DQS1 dly(2T, 0.5T) = (1, 1)
8268 22:13:04.957955 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8269 22:13:04.961692 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8270 22:13:04.964227 Pre-setting of DQS Precalculation
8271 22:13:04.971457 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8272 22:13:04.971541 ==
8273 22:13:04.974703 Dram Type= 6, Freq= 0, CH_1, rank 0
8274 22:13:04.977915 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8275 22:13:04.978000 ==
8276 22:13:04.984330 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8277 22:13:04.987884 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8278 22:13:04.991140 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8279 22:13:04.998108 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8280 22:13:05.006024 [CA 0] Center 42 (14~71) winsize 58
8281 22:13:05.009371 [CA 1] Center 42 (13~71) winsize 59
8282 22:13:05.013037 [CA 2] Center 37 (8~66) winsize 59
8283 22:13:05.015883 [CA 3] Center 35 (6~65) winsize 60
8284 22:13:05.019319 [CA 4] Center 37 (8~67) winsize 60
8285 22:13:05.022995 [CA 5] Center 36 (7~66) winsize 60
8286 22:13:05.023078
8287 22:13:05.026202 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8288 22:13:05.026284
8289 22:13:05.029848 [CATrainingPosCal] consider 1 rank data
8290 22:13:05.032785 u2DelayCellTimex100 = 275/100 ps
8291 22:13:05.036472 CA0 delay=42 (14~71),Diff = 7 PI (24 cell)
8292 22:13:05.042560 CA1 delay=42 (13~71),Diff = 7 PI (24 cell)
8293 22:13:05.046489 CA2 delay=37 (8~66),Diff = 2 PI (7 cell)
8294 22:13:05.049523 CA3 delay=35 (6~65),Diff = 0 PI (0 cell)
8295 22:13:05.052595 CA4 delay=37 (8~67),Diff = 2 PI (7 cell)
8296 22:13:05.056195 CA5 delay=36 (7~66),Diff = 1 PI (3 cell)
8297 22:13:05.056294
8298 22:13:05.059435 CA PerBit enable=1, Macro0, CA PI delay=35
8299 22:13:05.059507
8300 22:13:05.062757 [CBTSetCACLKResult] CA Dly = 35
8301 22:13:05.066177 CS Dly: 9 (0~40)
8302 22:13:05.069177 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8303 22:13:05.072619 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8304 22:13:05.072704 ==
8305 22:13:05.075861 Dram Type= 6, Freq= 0, CH_1, rank 1
8306 22:13:05.079797 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8307 22:13:05.079870 ==
8308 22:13:05.086144 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8309 22:13:05.089928 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8310 22:13:05.095841 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8311 22:13:05.099323 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8312 22:13:05.109363 [CA 0] Center 43 (14~73) winsize 60
8313 22:13:05.112761 [CA 1] Center 43 (15~72) winsize 58
8314 22:13:05.115683 [CA 2] Center 38 (9~67) winsize 59
8315 22:13:05.119155 [CA 3] Center 37 (8~66) winsize 59
8316 22:13:05.122908 [CA 4] Center 38 (9~68) winsize 60
8317 22:13:05.125995 [CA 5] Center 37 (8~66) winsize 59
8318 22:13:05.126089
8319 22:13:05.129005 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8320 22:13:05.129087
8321 22:13:05.132759 [CATrainingPosCal] consider 2 rank data
8322 22:13:05.136331 u2DelayCellTimex100 = 275/100 ps
8323 22:13:05.139215 CA0 delay=42 (14~71),Diff = 6 PI (21 cell)
8324 22:13:05.146085 CA1 delay=43 (15~71),Diff = 7 PI (24 cell)
8325 22:13:05.149649 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8326 22:13:05.152322 CA3 delay=36 (8~65),Diff = 0 PI (0 cell)
8327 22:13:05.155644 CA4 delay=38 (9~67),Diff = 2 PI (7 cell)
8328 22:13:05.159102 CA5 delay=37 (8~66),Diff = 1 PI (3 cell)
8329 22:13:05.159228
8330 22:13:05.162132 CA PerBit enable=1, Macro0, CA PI delay=36
8331 22:13:05.162215
8332 22:13:05.166147 [CBTSetCACLKResult] CA Dly = 36
8333 22:13:05.169495 CS Dly: 11 (0~45)
8334 22:13:05.172109 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8335 22:13:05.176036 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8336 22:13:05.176116
8337 22:13:05.179442 ----->DramcWriteLeveling(PI) begin...
8338 22:13:05.179534 ==
8339 22:13:05.182487 Dram Type= 6, Freq= 0, CH_1, rank 0
8340 22:13:05.185669 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8341 22:13:05.188937 ==
8342 22:13:05.192110 Write leveling (Byte 0): 22 => 22
8343 22:13:05.192192 Write leveling (Byte 1): 31 => 31
8344 22:13:05.195480 DramcWriteLeveling(PI) end<-----
8345 22:13:05.195550
8346 22:13:05.195610 ==
8347 22:13:05.198911 Dram Type= 6, Freq= 0, CH_1, rank 0
8348 22:13:05.205806 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8349 22:13:05.205886 ==
8350 22:13:05.209045 [Gating] SW mode calibration
8351 22:13:05.215638 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8352 22:13:05.218963 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8353 22:13:05.225303 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8354 22:13:05.228563 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8355 22:13:05.232106 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8356 22:13:05.238785 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8357 22:13:05.242695 1 4 16 | B1->B0 | 3131 2f2f | 1 1 | (0 0) (0 0)
8358 22:13:05.245573 1 4 20 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8359 22:13:05.252175 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8360 22:13:05.255800 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8361 22:13:05.258703 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8362 22:13:05.265168 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8363 22:13:05.268930 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8364 22:13:05.271848 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8365 22:13:05.278477 1 5 16 | B1->B0 | 2c2c 3131 | 0 0 | (0 1) (1 0)
8366 22:13:05.281792 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8367 22:13:05.284913 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8368 22:13:05.288350 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8369 22:13:05.294858 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8370 22:13:05.298164 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8371 22:13:05.302072 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8372 22:13:05.308336 1 6 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8373 22:13:05.311478 1 6 16 | B1->B0 | 3535 2929 | 0 0 | (0 0) (0 0)
8374 22:13:05.314810 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8375 22:13:05.321995 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8376 22:13:05.324750 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8377 22:13:05.328538 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8378 22:13:05.334711 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8379 22:13:05.338285 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8380 22:13:05.341854 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8381 22:13:05.347946 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8382 22:13:05.351163 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8383 22:13:05.354457 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8384 22:13:05.361528 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8385 22:13:05.364703 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8386 22:13:05.367943 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8387 22:13:05.374826 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8388 22:13:05.378112 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8389 22:13:05.381247 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8390 22:13:05.388112 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8391 22:13:05.391326 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8392 22:13:05.394897 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8393 22:13:05.401461 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8394 22:13:05.404657 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8395 22:13:05.408082 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8396 22:13:05.414443 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8397 22:13:05.417839 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8398 22:13:05.421275 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8399 22:13:05.424426 Total UI for P1: 0, mck2ui 16
8400 22:13:05.428343 best dqsien dly found for B0: ( 1, 9, 16)
8401 22:13:05.431105 Total UI for P1: 0, mck2ui 16
8402 22:13:05.434958 best dqsien dly found for B1: ( 1, 9, 16)
8403 22:13:05.437861 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
8404 22:13:05.441811 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8405 22:13:05.441894
8406 22:13:05.444838 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
8407 22:13:05.450943 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8408 22:13:05.451027 [Gating] SW calibration Done
8409 22:13:05.451093 ==
8410 22:13:05.454774 Dram Type= 6, Freq= 0, CH_1, rank 0
8411 22:13:05.460960 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8412 22:13:05.461044 ==
8413 22:13:05.461111 RX Vref Scan: 0
8414 22:13:05.461173
8415 22:13:05.464683 RX Vref 0 -> 0, step: 1
8416 22:13:05.464766
8417 22:13:05.467726 RX Delay 0 -> 252, step: 8
8418 22:13:05.470989 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8419 22:13:05.474565 iDelay=208, Bit 1, Center 127 (72 ~ 183) 112
8420 22:13:05.477735 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8421 22:13:05.481647 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8422 22:13:05.488055 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8423 22:13:05.490931 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8424 22:13:05.494670 iDelay=208, Bit 6, Center 143 (96 ~ 191) 96
8425 22:13:05.498036 iDelay=208, Bit 7, Center 127 (72 ~ 183) 112
8426 22:13:05.501465 iDelay=208, Bit 8, Center 115 (64 ~ 167) 104
8427 22:13:05.507486 iDelay=208, Bit 9, Center 115 (64 ~ 167) 104
8428 22:13:05.511264 iDelay=208, Bit 10, Center 127 (72 ~ 183) 112
8429 22:13:05.514399 iDelay=208, Bit 11, Center 123 (72 ~ 175) 104
8430 22:13:05.517913 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8431 22:13:05.521051 iDelay=208, Bit 13, Center 131 (72 ~ 191) 120
8432 22:13:05.528098 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8433 22:13:05.531025 iDelay=208, Bit 15, Center 131 (80 ~ 183) 104
8434 22:13:05.531108 ==
8435 22:13:05.534103 Dram Type= 6, Freq= 0, CH_1, rank 0
8436 22:13:05.537623 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8437 22:13:05.537706 ==
8438 22:13:05.540877 DQS Delay:
8439 22:13:05.540959 DQS0 = 0, DQS1 = 0
8440 22:13:05.541025 DQM Delay:
8441 22:13:05.544072 DQM0 = 134, DQM1 = 126
8442 22:13:05.544155 DQ Delay:
8443 22:13:05.547414 DQ0 =139, DQ1 =127, DQ2 =123, DQ3 =135
8444 22:13:05.551166 DQ4 =135, DQ5 =147, DQ6 =143, DQ7 =127
8445 22:13:05.557734 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =123
8446 22:13:05.560999 DQ12 =135, DQ13 =131, DQ14 =135, DQ15 =131
8447 22:13:05.561100
8448 22:13:05.561167
8449 22:13:05.561228 ==
8450 22:13:05.564006 Dram Type= 6, Freq= 0, CH_1, rank 0
8451 22:13:05.567805 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8452 22:13:05.567888 ==
8453 22:13:05.567961
8454 22:13:05.568026
8455 22:13:05.570977 TX Vref Scan disable
8456 22:13:05.574286 == TX Byte 0 ==
8457 22:13:05.577278 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8458 22:13:05.580871 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8459 22:13:05.584156 == TX Byte 1 ==
8460 22:13:05.587235 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
8461 22:13:05.590440 Update DQM dly =987 (3 ,6, 27) DQM OEN =(3 ,3)
8462 22:13:05.590522 ==
8463 22:13:05.594461 Dram Type= 6, Freq= 0, CH_1, rank 0
8464 22:13:05.597448 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8465 22:13:05.600637 ==
8466 22:13:05.612135
8467 22:13:05.615902 TX Vref early break, caculate TX vref
8468 22:13:05.619197 TX Vref=16, minBit 0, minWin=21, winSum=360
8469 22:13:05.622282 TX Vref=18, minBit 8, minWin=22, winSum=369
8470 22:13:05.625594 TX Vref=20, minBit 8, minWin=22, winSum=380
8471 22:13:05.629004 TX Vref=22, minBit 8, minWin=23, winSum=391
8472 22:13:05.632460 TX Vref=24, minBit 8, minWin=23, winSum=396
8473 22:13:05.639741 TX Vref=26, minBit 15, minWin=24, winSum=414
8474 22:13:05.642424 TX Vref=28, minBit 8, minWin=25, winSum=417
8475 22:13:05.645352 TX Vref=30, minBit 1, minWin=25, winSum=416
8476 22:13:05.648986 TX Vref=32, minBit 12, minWin=24, winSum=405
8477 22:13:05.652672 TX Vref=34, minBit 0, minWin=24, winSum=394
8478 22:13:05.658655 [TxChooseVref] Worse bit 8, Min win 25, Win sum 417, Final Vref 28
8479 22:13:05.658738
8480 22:13:05.662286 Final TX Range 0 Vref 28
8481 22:13:05.662369
8482 22:13:05.662435 ==
8483 22:13:05.665574 Dram Type= 6, Freq= 0, CH_1, rank 0
8484 22:13:05.668891 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8485 22:13:05.668975 ==
8486 22:13:05.669060
8487 22:13:05.669166
8488 22:13:05.672424 TX Vref Scan disable
8489 22:13:05.678777 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8490 22:13:05.678861 == TX Byte 0 ==
8491 22:13:05.682292 u2DelayCellOfst[0]=17 cells (5 PI)
8492 22:13:05.686101 u2DelayCellOfst[1]=14 cells (4 PI)
8493 22:13:05.689046 u2DelayCellOfst[2]=0 cells (0 PI)
8494 22:13:05.691868 u2DelayCellOfst[3]=7 cells (2 PI)
8495 22:13:05.695701 u2DelayCellOfst[4]=7 cells (2 PI)
8496 22:13:05.698747 u2DelayCellOfst[5]=21 cells (6 PI)
8497 22:13:05.701863 u2DelayCellOfst[6]=17 cells (5 PI)
8498 22:13:05.705149 u2DelayCellOfst[7]=7 cells (2 PI)
8499 22:13:05.708639 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8500 22:13:05.711828 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8501 22:13:05.715899 == TX Byte 1 ==
8502 22:13:05.716005 u2DelayCellOfst[8]=0 cells (0 PI)
8503 22:13:05.719083 u2DelayCellOfst[9]=3 cells (1 PI)
8504 22:13:05.722341 u2DelayCellOfst[10]=10 cells (3 PI)
8505 22:13:05.725744 u2DelayCellOfst[11]=7 cells (2 PI)
8506 22:13:05.729202 u2DelayCellOfst[12]=10 cells (3 PI)
8507 22:13:05.731761 u2DelayCellOfst[13]=14 cells (4 PI)
8508 22:13:05.735657 u2DelayCellOfst[14]=17 cells (5 PI)
8509 22:13:05.738767 u2DelayCellOfst[15]=17 cells (5 PI)
8510 22:13:05.741572 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8511 22:13:05.748454 Update DQM dly =987 (3 ,6, 27) DQM OEN =(3 ,3)
8512 22:13:05.748552 DramC Write-DBI on
8513 22:13:05.748620 ==
8514 22:13:05.751810 Dram Type= 6, Freq= 0, CH_1, rank 0
8515 22:13:05.755577 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8516 22:13:05.759035 ==
8517 22:13:05.759117
8518 22:13:05.759184
8519 22:13:05.759246 TX Vref Scan disable
8520 22:13:05.761921 == TX Byte 0 ==
8521 22:13:05.765357 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8522 22:13:05.768498 == TX Byte 1 ==
8523 22:13:05.772444 Update DQM dly =728 (2 ,6, 24) DQM OEN =(3 ,3)
8524 22:13:05.775285 DramC Write-DBI off
8525 22:13:05.775368
8526 22:13:05.775434 [DATLAT]
8527 22:13:05.775495 Freq=1600, CH1 RK0
8528 22:13:05.775554
8529 22:13:05.778297 DATLAT Default: 0xf
8530 22:13:05.782329 0, 0xFFFF, sum = 0
8531 22:13:05.782414 1, 0xFFFF, sum = 0
8532 22:13:05.785483 2, 0xFFFF, sum = 0
8533 22:13:05.785567 3, 0xFFFF, sum = 0
8534 22:13:05.788497 4, 0xFFFF, sum = 0
8535 22:13:05.788585 5, 0xFFFF, sum = 0
8536 22:13:05.791579 6, 0xFFFF, sum = 0
8537 22:13:05.791663 7, 0xFFFF, sum = 0
8538 22:13:05.795680 8, 0xFFFF, sum = 0
8539 22:13:05.795764 9, 0xFFFF, sum = 0
8540 22:13:05.798655 10, 0xFFFF, sum = 0
8541 22:13:05.798740 11, 0xFFFF, sum = 0
8542 22:13:05.801902 12, 0xFFFF, sum = 0
8543 22:13:05.801986 13, 0xFFFF, sum = 0
8544 22:13:05.806010 14, 0x0, sum = 1
8545 22:13:05.806095 15, 0x0, sum = 2
8546 22:13:05.808428 16, 0x0, sum = 3
8547 22:13:05.808512 17, 0x0, sum = 4
8548 22:13:05.811800 best_step = 15
8549 22:13:05.811883
8550 22:13:05.811949 ==
8551 22:13:05.815031 Dram Type= 6, Freq= 0, CH_1, rank 0
8552 22:13:05.818244 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8553 22:13:05.818328 ==
8554 22:13:05.821594 RX Vref Scan: 1
8555 22:13:05.821680
8556 22:13:05.821746 Set Vref Range= 24 -> 127
8557 22:13:05.821808
8558 22:13:05.825262 RX Vref 24 -> 127, step: 1
8559 22:13:05.825349
8560 22:13:05.828807 RX Delay 19 -> 252, step: 4
8561 22:13:05.828890
8562 22:13:05.831729 Set Vref, RX VrefLevel [Byte0]: 24
8563 22:13:05.834772 [Byte1]: 24
8564 22:13:05.834855
8565 22:13:05.838548 Set Vref, RX VrefLevel [Byte0]: 25
8566 22:13:05.841620 [Byte1]: 25
8567 22:13:05.841704
8568 22:13:05.844773 Set Vref, RX VrefLevel [Byte0]: 26
8569 22:13:05.848149 [Byte1]: 26
8570 22:13:05.852740
8571 22:13:05.852822 Set Vref, RX VrefLevel [Byte0]: 27
8572 22:13:05.856105 [Byte1]: 27
8573 22:13:05.859939
8574 22:13:05.860066 Set Vref, RX VrefLevel [Byte0]: 28
8575 22:13:05.863626 [Byte1]: 28
8576 22:13:05.867437
8577 22:13:05.867520 Set Vref, RX VrefLevel [Byte0]: 29
8578 22:13:05.870654 [Byte1]: 29
8579 22:13:05.875063
8580 22:13:05.875145 Set Vref, RX VrefLevel [Byte0]: 30
8581 22:13:05.878180 [Byte1]: 30
8582 22:13:05.882414
8583 22:13:05.882497 Set Vref, RX VrefLevel [Byte0]: 31
8584 22:13:05.885823 [Byte1]: 31
8585 22:13:05.889925
8586 22:13:05.890007 Set Vref, RX VrefLevel [Byte0]: 32
8587 22:13:05.893469 [Byte1]: 32
8588 22:13:05.898067
8589 22:13:05.898149 Set Vref, RX VrefLevel [Byte0]: 33
8590 22:13:05.901180 [Byte1]: 33
8591 22:13:05.905268
8592 22:13:05.905351 Set Vref, RX VrefLevel [Byte0]: 34
8593 22:13:05.908270 [Byte1]: 34
8594 22:13:05.912653
8595 22:13:05.912736 Set Vref, RX VrefLevel [Byte0]: 35
8596 22:13:05.916037 [Byte1]: 35
8597 22:13:05.920717
8598 22:13:05.920799 Set Vref, RX VrefLevel [Byte0]: 36
8599 22:13:05.923873 [Byte1]: 36
8600 22:13:05.927722
8601 22:13:05.927805 Set Vref, RX VrefLevel [Byte0]: 37
8602 22:13:05.931288 [Byte1]: 37
8603 22:13:05.935624
8604 22:13:05.935707 Set Vref, RX VrefLevel [Byte0]: 38
8605 22:13:05.939101 [Byte1]: 38
8606 22:13:05.942972
8607 22:13:05.943055 Set Vref, RX VrefLevel [Byte0]: 39
8608 22:13:05.946546 [Byte1]: 39
8609 22:13:05.950581
8610 22:13:05.950663 Set Vref, RX VrefLevel [Byte0]: 40
8611 22:13:05.954265 [Byte1]: 40
8612 22:13:05.958247
8613 22:13:05.958329 Set Vref, RX VrefLevel [Byte0]: 41
8614 22:13:05.961779 [Byte1]: 41
8615 22:13:05.966140
8616 22:13:05.966225 Set Vref, RX VrefLevel [Byte0]: 42
8617 22:13:05.969245 [Byte1]: 42
8618 22:13:05.973777
8619 22:13:05.973860 Set Vref, RX VrefLevel [Byte0]: 43
8620 22:13:05.976501 [Byte1]: 43
8621 22:13:05.981279
8622 22:13:05.981361 Set Vref, RX VrefLevel [Byte0]: 44
8623 22:13:05.984335 [Byte1]: 44
8624 22:13:05.989008
8625 22:13:05.989091 Set Vref, RX VrefLevel [Byte0]: 45
8626 22:13:05.991923 [Byte1]: 45
8627 22:13:05.996218
8628 22:13:05.996300 Set Vref, RX VrefLevel [Byte0]: 46
8629 22:13:05.999852 [Byte1]: 46
8630 22:13:06.003467
8631 22:13:06.003556 Set Vref, RX VrefLevel [Byte0]: 47
8632 22:13:06.007157 [Byte1]: 47
8633 22:13:06.011352
8634 22:13:06.011435 Set Vref, RX VrefLevel [Byte0]: 48
8635 22:13:06.014575 [Byte1]: 48
8636 22:13:06.018744
8637 22:13:06.018826 Set Vref, RX VrefLevel [Byte0]: 49
8638 22:13:06.022079 [Byte1]: 49
8639 22:13:06.026425
8640 22:13:06.026522 Set Vref, RX VrefLevel [Byte0]: 50
8641 22:13:06.029533 [Byte1]: 50
8642 22:13:06.034098
8643 22:13:06.034181 Set Vref, RX VrefLevel [Byte0]: 51
8644 22:13:06.038218 [Byte1]: 51
8645 22:13:06.041390
8646 22:13:06.041480 Set Vref, RX VrefLevel [Byte0]: 52
8647 22:13:06.044759 [Byte1]: 52
8648 22:13:06.049219
8649 22:13:06.049302 Set Vref, RX VrefLevel [Byte0]: 53
8650 22:13:06.052213 [Byte1]: 53
8651 22:13:06.056510
8652 22:13:06.056593 Set Vref, RX VrefLevel [Byte0]: 54
8653 22:13:06.060618 [Byte1]: 54
8654 22:13:06.064649
8655 22:13:06.064732 Set Vref, RX VrefLevel [Byte0]: 55
8656 22:13:06.067707 [Byte1]: 55
8657 22:13:06.072487
8658 22:13:06.072570 Set Vref, RX VrefLevel [Byte0]: 56
8659 22:13:06.075241 [Byte1]: 56
8660 22:13:06.079547
8661 22:13:06.079629 Set Vref, RX VrefLevel [Byte0]: 57
8662 22:13:06.082787 [Byte1]: 57
8663 22:13:06.087085
8664 22:13:06.087167 Set Vref, RX VrefLevel [Byte0]: 58
8665 22:13:06.090616 [Byte1]: 58
8666 22:13:06.094738
8667 22:13:06.094847 Set Vref, RX VrefLevel [Byte0]: 59
8668 22:13:06.098138 [Byte1]: 59
8669 22:13:06.102682
8670 22:13:06.102764 Set Vref, RX VrefLevel [Byte0]: 60
8671 22:13:06.105219 [Byte1]: 60
8672 22:13:06.109973
8673 22:13:06.110056 Set Vref, RX VrefLevel [Byte0]: 61
8674 22:13:06.113300 [Byte1]: 61
8675 22:13:06.117156
8676 22:13:06.117239 Set Vref, RX VrefLevel [Byte0]: 62
8677 22:13:06.120478 [Byte1]: 62
8678 22:13:06.124988
8679 22:13:06.125074 Set Vref, RX VrefLevel [Byte0]: 63
8680 22:13:06.131085 [Byte1]: 63
8681 22:13:06.131168
8682 22:13:06.134990 Set Vref, RX VrefLevel [Byte0]: 64
8683 22:13:06.137714 [Byte1]: 64
8684 22:13:06.137797
8685 22:13:06.141305 Set Vref, RX VrefLevel [Byte0]: 65
8686 22:13:06.144734 [Byte1]: 65
8687 22:13:06.144817
8688 22:13:06.148039 Set Vref, RX VrefLevel [Byte0]: 66
8689 22:13:06.151411 [Byte1]: 66
8690 22:13:06.155310
8691 22:13:06.155393 Set Vref, RX VrefLevel [Byte0]: 67
8692 22:13:06.158410 [Byte1]: 67
8693 22:13:06.162522
8694 22:13:06.162605 Set Vref, RX VrefLevel [Byte0]: 68
8695 22:13:06.165782 [Byte1]: 68
8696 22:13:06.170598
8697 22:13:06.170681 Set Vref, RX VrefLevel [Byte0]: 69
8698 22:13:06.173359 [Byte1]: 69
8699 22:13:06.177878
8700 22:13:06.177961 Set Vref, RX VrefLevel [Byte0]: 70
8701 22:13:06.180874 [Byte1]: 70
8702 22:13:06.185416
8703 22:13:06.185499 Set Vref, RX VrefLevel [Byte0]: 71
8704 22:13:06.188871 [Byte1]: 71
8705 22:13:06.193295
8706 22:13:06.193378 Set Vref, RX VrefLevel [Byte0]: 72
8707 22:13:06.196179 [Byte1]: 72
8708 22:13:06.200819
8709 22:13:06.200901 Set Vref, RX VrefLevel [Byte0]: 73
8710 22:13:06.203615 [Byte1]: 73
8711 22:13:06.208135
8712 22:13:06.208217 Set Vref, RX VrefLevel [Byte0]: 74
8713 22:13:06.211741 [Byte1]: 74
8714 22:13:06.215546
8715 22:13:06.215629 Set Vref, RX VrefLevel [Byte0]: 75
8716 22:13:06.218946 [Byte1]: 75
8717 22:13:06.223683
8718 22:13:06.223787 Final RX Vref Byte 0 = 52 to rank0
8719 22:13:06.226408 Final RX Vref Byte 1 = 55 to rank0
8720 22:13:06.230011 Final RX Vref Byte 0 = 52 to rank1
8721 22:13:06.233069 Final RX Vref Byte 1 = 55 to rank1==
8722 22:13:06.236510 Dram Type= 6, Freq= 0, CH_1, rank 0
8723 22:13:06.243738 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8724 22:13:06.243822 ==
8725 22:13:06.243889 DQS Delay:
8726 22:13:06.243951 DQS0 = 0, DQS1 = 0
8727 22:13:06.246746 DQM Delay:
8728 22:13:06.246829 DQM0 = 131, DQM1 = 124
8729 22:13:06.249628 DQ Delay:
8730 22:13:06.253428 DQ0 =136, DQ1 =124, DQ2 =118, DQ3 =130
8731 22:13:06.256694 DQ4 =132, DQ5 =142, DQ6 =142, DQ7 =126
8732 22:13:06.260051 DQ8 =110, DQ9 =112, DQ10 =126, DQ11 =120
8733 22:13:06.262909 DQ12 =132, DQ13 =132, DQ14 =130, DQ15 =132
8734 22:13:06.262992
8735 22:13:06.263058
8736 22:13:06.263119
8737 22:13:06.266603 [DramC_TX_OE_Calibration] TA2
8738 22:13:06.269830 Original DQ_B0 (3 6) =30, OEN = 27
8739 22:13:06.272895 Original DQ_B1 (3 6) =30, OEN = 27
8740 22:13:06.276250 24, 0x0, End_B0=24 End_B1=24
8741 22:13:06.276334 25, 0x0, End_B0=25 End_B1=25
8742 22:13:06.279968 26, 0x0, End_B0=26 End_B1=26
8743 22:13:06.283195 27, 0x0, End_B0=27 End_B1=27
8744 22:13:06.286508 28, 0x0, End_B0=28 End_B1=28
8745 22:13:06.289327 29, 0x0, End_B0=29 End_B1=29
8746 22:13:06.289411 30, 0x0, End_B0=30 End_B1=30
8747 22:13:06.292789 31, 0x4141, End_B0=30 End_B1=30
8748 22:13:06.296075 Byte0 end_step=30 best_step=27
8749 22:13:06.299784 Byte1 end_step=30 best_step=27
8750 22:13:06.302637 Byte0 TX OE(2T, 0.5T) = (3, 3)
8751 22:13:06.306229 Byte1 TX OE(2T, 0.5T) = (3, 3)
8752 22:13:06.306312
8753 22:13:06.306378
8754 22:13:06.312531 [DQSOSCAuto] RK0, (LSB)MR18= 0x13fe, (MSB)MR19= 0x302, tDQSOscB0 = 411 ps tDQSOscB1 = 400 ps
8755 22:13:06.315866 CH1 RK0: MR19=302, MR18=13FE
8756 22:13:06.323063 CH1_RK0: MR19=0x302, MR18=0x13FE, DQSOSC=400, MR23=63, INC=23, DEC=15
8757 22:13:06.323148
8758 22:13:06.326158 ----->DramcWriteLeveling(PI) begin...
8759 22:13:06.326242 ==
8760 22:13:06.329422 Dram Type= 6, Freq= 0, CH_1, rank 1
8761 22:13:06.332396 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8762 22:13:06.332482 ==
8763 22:13:06.336160 Write leveling (Byte 0): 27 => 27
8764 22:13:06.339790 Write leveling (Byte 1): 27 => 27
8765 22:13:06.342786 DramcWriteLeveling(PI) end<-----
8766 22:13:06.342885
8767 22:13:06.342977 ==
8768 22:13:06.346177 Dram Type= 6, Freq= 0, CH_1, rank 1
8769 22:13:06.349156 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8770 22:13:06.349233 ==
8771 22:13:06.352746 [Gating] SW mode calibration
8772 22:13:06.359093 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8773 22:13:06.365718 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8774 22:13:06.369423 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8775 22:13:06.376031 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8776 22:13:06.379460 1 4 8 | B1->B0 | 2323 2828 | 0 1 | (0 0) (1 1)
8777 22:13:06.382284 1 4 12 | B1->B0 | 2424 3434 | 0 0 | (0 0) (0 0)
8778 22:13:06.385550 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8779 22:13:06.392297 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8780 22:13:06.396018 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8781 22:13:06.399175 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8782 22:13:06.405691 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8783 22:13:06.409241 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8784 22:13:06.412129 1 5 8 | B1->B0 | 3434 2c2c | 1 1 | (1 1) (1 0)
8785 22:13:06.419092 1 5 12 | B1->B0 | 2c2c 2424 | 0 0 | (1 0) (0 0)
8786 22:13:06.422202 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8787 22:13:06.426114 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8788 22:13:06.432179 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8789 22:13:06.436047 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8790 22:13:06.438838 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8791 22:13:06.445871 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8792 22:13:06.449030 1 6 8 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
8793 22:13:06.452298 1 6 12 | B1->B0 | 3535 4646 | 1 0 | (0 0) (0 0)
8794 22:13:06.458650 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8795 22:13:06.462061 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8796 22:13:06.465986 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8797 22:13:06.472532 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8798 22:13:06.475574 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8799 22:13:06.478885 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8800 22:13:06.485543 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8801 22:13:06.488665 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8802 22:13:06.492016 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8803 22:13:06.498660 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8804 22:13:06.502413 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8805 22:13:06.505493 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8806 22:13:06.512188 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8807 22:13:06.515842 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8808 22:13:06.518683 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8809 22:13:06.522358 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8810 22:13:06.529433 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8811 22:13:06.532353 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8812 22:13:06.535390 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8813 22:13:06.542163 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8814 22:13:06.545320 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8815 22:13:06.549229 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8816 22:13:06.555201 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8817 22:13:06.558882 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8818 22:13:06.562255 Total UI for P1: 0, mck2ui 16
8819 22:13:06.564937 best dqsien dly found for B0: ( 1, 9, 8)
8820 22:13:06.568260 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8821 22:13:06.575004 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8822 22:13:06.578631 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8823 22:13:06.581871 Total UI for P1: 0, mck2ui 16
8824 22:13:06.585203 best dqsien dly found for B1: ( 1, 9, 16)
8825 22:13:06.588488 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8826 22:13:06.591695 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8827 22:13:06.591792
8828 22:13:06.595013 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8829 22:13:06.598155 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8830 22:13:06.601565 [Gating] SW calibration Done
8831 22:13:06.601664 ==
8832 22:13:06.605015 Dram Type= 6, Freq= 0, CH_1, rank 1
8833 22:13:06.611565 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8834 22:13:06.611669 ==
8835 22:13:06.611762 RX Vref Scan: 0
8836 22:13:06.611853
8837 22:13:06.614758 RX Vref 0 -> 0, step: 1
8838 22:13:06.614859
8839 22:13:06.618066 RX Delay 0 -> 252, step: 8
8840 22:13:06.621436 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8841 22:13:06.625038 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8842 22:13:06.628454 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8843 22:13:06.631944 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8844 22:13:06.637827 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8845 22:13:06.642004 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8846 22:13:06.644975 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8847 22:13:06.647886 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8848 22:13:06.651182 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8849 22:13:06.658457 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8850 22:13:06.661000 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8851 22:13:06.664960 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8852 22:13:06.667852 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8853 22:13:06.671037 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8854 22:13:06.677562 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8855 22:13:06.681096 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8856 22:13:06.681199 ==
8857 22:13:06.684607 Dram Type= 6, Freq= 0, CH_1, rank 1
8858 22:13:06.687680 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8859 22:13:06.687778 ==
8860 22:13:06.691776 DQS Delay:
8861 22:13:06.691875 DQS0 = 0, DQS1 = 0
8862 22:13:06.691970 DQM Delay:
8863 22:13:06.694783 DQM0 = 132, DQM1 = 128
8864 22:13:06.694857 DQ Delay:
8865 22:13:06.697847 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =135
8866 22:13:06.701313 DQ4 =131, DQ5 =143, DQ6 =139, DQ7 =127
8867 22:13:06.707663 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =119
8868 22:13:06.710785 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8869 22:13:06.710877
8870 22:13:06.710967
8871 22:13:06.711054 ==
8872 22:13:06.714430 Dram Type= 6, Freq= 0, CH_1, rank 1
8873 22:13:06.717658 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8874 22:13:06.717756 ==
8875 22:13:06.717847
8876 22:13:06.717933
8877 22:13:06.721032 TX Vref Scan disable
8878 22:13:06.721106 == TX Byte 0 ==
8879 22:13:06.727488 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8880 22:13:06.731019 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8881 22:13:06.734237 == TX Byte 1 ==
8882 22:13:06.737701 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8883 22:13:06.740580 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8884 22:13:06.740655 ==
8885 22:13:06.744294 Dram Type= 6, Freq= 0, CH_1, rank 1
8886 22:13:06.747560 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8887 22:13:06.747661 ==
8888 22:13:06.762845
8889 22:13:06.765844 TX Vref early break, caculate TX vref
8890 22:13:06.769112 TX Vref=16, minBit 0, minWin=22, winSum=375
8891 22:13:06.772420 TX Vref=18, minBit 0, minWin=23, winSum=383
8892 22:13:06.776301 TX Vref=20, minBit 5, minWin=23, winSum=392
8893 22:13:06.779155 TX Vref=22, minBit 5, minWin=24, winSum=402
8894 22:13:06.782385 TX Vref=24, minBit 5, minWin=25, winSum=413
8895 22:13:06.788837 TX Vref=26, minBit 6, minWin=25, winSum=415
8896 22:13:06.792469 TX Vref=28, minBit 0, minWin=25, winSum=422
8897 22:13:06.795698 TX Vref=30, minBit 0, minWin=25, winSum=425
8898 22:13:06.798764 TX Vref=32, minBit 0, minWin=25, winSum=416
8899 22:13:06.802286 TX Vref=34, minBit 0, minWin=24, winSum=406
8900 22:13:06.805217 TX Vref=36, minBit 0, minWin=23, winSum=398
8901 22:13:06.812399 [TxChooseVref] Worse bit 0, Min win 25, Win sum 425, Final Vref 30
8902 22:13:06.812475
8903 22:13:06.815443 Final TX Range 0 Vref 30
8904 22:13:06.815540
8905 22:13:06.815630 ==
8906 22:13:06.818543 Dram Type= 6, Freq= 0, CH_1, rank 1
8907 22:13:06.822014 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8908 22:13:06.822086 ==
8909 22:13:06.822153
8910 22:13:06.822212
8911 22:13:06.825682 TX Vref Scan disable
8912 22:13:06.832480 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8913 22:13:06.832557 == TX Byte 0 ==
8914 22:13:06.835058 u2DelayCellOfst[0]=17 cells (5 PI)
8915 22:13:06.838768 u2DelayCellOfst[1]=10 cells (3 PI)
8916 22:13:06.841582 u2DelayCellOfst[2]=0 cells (0 PI)
8917 22:13:06.845679 u2DelayCellOfst[3]=7 cells (2 PI)
8918 22:13:06.848791 u2DelayCellOfst[4]=7 cells (2 PI)
8919 22:13:06.851571 u2DelayCellOfst[5]=21 cells (6 PI)
8920 22:13:06.855029 u2DelayCellOfst[6]=17 cells (5 PI)
8921 22:13:06.858324 u2DelayCellOfst[7]=7 cells (2 PI)
8922 22:13:06.862010 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8923 22:13:06.865106 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8924 22:13:06.868237 == TX Byte 1 ==
8925 22:13:06.871783 u2DelayCellOfst[8]=0 cells (0 PI)
8926 22:13:06.871858 u2DelayCellOfst[9]=3 cells (1 PI)
8927 22:13:06.875102 u2DelayCellOfst[10]=10 cells (3 PI)
8928 22:13:06.878969 u2DelayCellOfst[11]=7 cells (2 PI)
8929 22:13:06.881529 u2DelayCellOfst[12]=14 cells (4 PI)
8930 22:13:06.885102 u2DelayCellOfst[13]=14 cells (4 PI)
8931 22:13:06.888305 u2DelayCellOfst[14]=17 cells (5 PI)
8932 22:13:06.891535 u2DelayCellOfst[15]=14 cells (4 PI)
8933 22:13:06.894813 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8934 22:13:06.901734 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8935 22:13:06.901834 DramC Write-DBI on
8936 22:13:06.901925 ==
8937 22:13:06.904906 Dram Type= 6, Freq= 0, CH_1, rank 1
8938 22:13:06.911443 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8939 22:13:06.911526 ==
8940 22:13:06.911618
8941 22:13:06.911707
8942 22:13:06.911794 TX Vref Scan disable
8943 22:13:06.915865 == TX Byte 0 ==
8944 22:13:06.919264 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8945 22:13:06.922145 == TX Byte 1 ==
8946 22:13:06.925381 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8947 22:13:06.928983 DramC Write-DBI off
8948 22:13:06.929075
8949 22:13:06.929139 [DATLAT]
8950 22:13:06.929204 Freq=1600, CH1 RK1
8951 22:13:06.929292
8952 22:13:06.932392 DATLAT Default: 0xf
8953 22:13:06.935510 0, 0xFFFF, sum = 0
8954 22:13:06.935610 1, 0xFFFF, sum = 0
8955 22:13:06.938659 2, 0xFFFF, sum = 0
8956 22:13:06.938759 3, 0xFFFF, sum = 0
8957 22:13:06.941978 4, 0xFFFF, sum = 0
8958 22:13:06.942082 5, 0xFFFF, sum = 0
8959 22:13:06.945221 6, 0xFFFF, sum = 0
8960 22:13:06.945296 7, 0xFFFF, sum = 0
8961 22:13:06.948385 8, 0xFFFF, sum = 0
8962 22:13:06.948463 9, 0xFFFF, sum = 0
8963 22:13:06.951918 10, 0xFFFF, sum = 0
8964 22:13:06.952042 11, 0xFFFF, sum = 0
8965 22:13:06.954966 12, 0xFFFF, sum = 0
8966 22:13:06.955065 13, 0xFFFF, sum = 0
8967 22:13:06.958559 14, 0x0, sum = 1
8968 22:13:06.958659 15, 0x0, sum = 2
8969 22:13:06.961426 16, 0x0, sum = 3
8970 22:13:06.961500 17, 0x0, sum = 4
8971 22:13:06.965083 best_step = 15
8972 22:13:06.965157
8973 22:13:06.965219 ==
8974 22:13:06.968274 Dram Type= 6, Freq= 0, CH_1, rank 1
8975 22:13:06.971828 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8976 22:13:06.971926 ==
8977 22:13:06.975244 RX Vref Scan: 0
8978 22:13:06.975318
8979 22:13:06.975381 RX Vref 0 -> 0, step: 1
8980 22:13:06.975440
8981 22:13:06.978379 RX Delay 11 -> 252, step: 4
8982 22:13:06.984862 iDelay=195, Bit 0, Center 132 (83 ~ 182) 100
8983 22:13:06.988606 iDelay=195, Bit 1, Center 124 (71 ~ 178) 108
8984 22:13:06.991403 iDelay=195, Bit 2, Center 118 (67 ~ 170) 104
8985 22:13:06.994999 iDelay=195, Bit 3, Center 128 (79 ~ 178) 100
8986 22:13:06.998218 iDelay=195, Bit 4, Center 128 (75 ~ 182) 108
8987 22:13:07.001760 iDelay=195, Bit 5, Center 142 (91 ~ 194) 104
8988 22:13:07.007818 iDelay=195, Bit 6, Center 138 (87 ~ 190) 104
8989 22:13:07.011567 iDelay=195, Bit 7, Center 124 (71 ~ 178) 108
8990 22:13:07.014819 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
8991 22:13:07.018492 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8992 22:13:07.024497 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8993 22:13:07.027911 iDelay=195, Bit 11, Center 118 (67 ~ 170) 104
8994 22:13:07.031099 iDelay=195, Bit 12, Center 134 (83 ~ 186) 104
8995 22:13:07.034899 iDelay=195, Bit 13, Center 134 (83 ~ 186) 104
8996 22:13:07.038265 iDelay=195, Bit 14, Center 134 (83 ~ 186) 104
8997 22:13:07.044521 iDelay=195, Bit 15, Center 134 (83 ~ 186) 104
8998 22:13:07.044619 ==
8999 22:13:07.048188 Dram Type= 6, Freq= 0, CH_1, rank 1
9000 22:13:07.051663 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9001 22:13:07.051762 ==
9002 22:13:07.051852 DQS Delay:
9003 22:13:07.054970 DQS0 = 0, DQS1 = 0
9004 22:13:07.055068 DQM Delay:
9005 22:13:07.058004 DQM0 = 129, DQM1 = 126
9006 22:13:07.058099 DQ Delay:
9007 22:13:07.061302 DQ0 =132, DQ1 =124, DQ2 =118, DQ3 =128
9008 22:13:07.065064 DQ4 =128, DQ5 =142, DQ6 =138, DQ7 =124
9009 22:13:07.068011 DQ8 =114, DQ9 =112, DQ10 =128, DQ11 =118
9010 22:13:07.071254 DQ12 =134, DQ13 =134, DQ14 =134, DQ15 =134
9011 22:13:07.071323
9012 22:13:07.071384
9013 22:13:07.071446
9014 22:13:07.075355 [DramC_TX_OE_Calibration] TA2
9015 22:13:07.078057 Original DQ_B0 (3 6) =30, OEN = 27
9016 22:13:07.081296 Original DQ_B1 (3 6) =30, OEN = 27
9017 22:13:07.085157 24, 0x0, End_B0=24 End_B1=24
9018 22:13:07.088698 25, 0x0, End_B0=25 End_B1=25
9019 22:13:07.088799 26, 0x0, End_B0=26 End_B1=26
9020 22:13:07.091269 27, 0x0, End_B0=27 End_B1=27
9021 22:13:07.094443 28, 0x0, End_B0=28 End_B1=28
9022 22:13:07.097877 29, 0x0, End_B0=29 End_B1=29
9023 22:13:07.101058 30, 0x0, End_B0=30 End_B1=30
9024 22:13:07.101131 31, 0x5151, End_B0=30 End_B1=30
9025 22:13:07.104248 Byte0 end_step=30 best_step=27
9026 22:13:07.107622 Byte1 end_step=30 best_step=27
9027 22:13:07.111596 Byte0 TX OE(2T, 0.5T) = (3, 3)
9028 22:13:07.114763 Byte1 TX OE(2T, 0.5T) = (3, 3)
9029 22:13:07.114838
9030 22:13:07.114927
9031 22:13:07.120965 [DQSOSCAuto] RK1, (LSB)MR18= 0xe14, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 402 ps
9032 22:13:07.124409 CH1 RK1: MR19=303, MR18=E14
9033 22:13:07.131328 CH1_RK1: MR19=0x303, MR18=0xE14, DQSOSC=399, MR23=63, INC=23, DEC=15
9034 22:13:07.134551 [RxdqsGatingPostProcess] freq 1600
9035 22:13:07.140896 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9036 22:13:07.140980 best DQS0 dly(2T, 0.5T) = (1, 1)
9037 22:13:07.144206 best DQS1 dly(2T, 0.5T) = (1, 1)
9038 22:13:07.147643 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9039 22:13:07.150817 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9040 22:13:07.154206 best DQS0 dly(2T, 0.5T) = (1, 1)
9041 22:13:07.157460 best DQS1 dly(2T, 0.5T) = (1, 1)
9042 22:13:07.161199 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9043 22:13:07.163990 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9044 22:13:07.167551 Pre-setting of DQS Precalculation
9045 22:13:07.170593 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9046 22:13:07.181310 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9047 22:13:07.187831 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9048 22:13:07.187914
9049 22:13:07.187988
9050 22:13:07.190671 [Calibration Summary] 3200 Mbps
9051 22:13:07.190753 CH 0, Rank 0
9052 22:13:07.194293 SW Impedance : PASS
9053 22:13:07.194376 DUTY Scan : NO K
9054 22:13:07.197284 ZQ Calibration : PASS
9055 22:13:07.200462 Jitter Meter : NO K
9056 22:13:07.200544 CBT Training : PASS
9057 22:13:07.204570 Write leveling : PASS
9058 22:13:07.207187 RX DQS gating : PASS
9059 22:13:07.207269 RX DQ/DQS(RDDQC) : PASS
9060 22:13:07.210513 TX DQ/DQS : PASS
9061 22:13:07.214043 RX DATLAT : PASS
9062 22:13:07.214124 RX DQ/DQS(Engine): PASS
9063 22:13:07.217036 TX OE : PASS
9064 22:13:07.217118 All Pass.
9065 22:13:07.217184
9066 22:13:07.220426 CH 0, Rank 1
9067 22:13:07.220508 SW Impedance : PASS
9068 22:13:07.224070 DUTY Scan : NO K
9069 22:13:07.227351 ZQ Calibration : PASS
9070 22:13:07.227433 Jitter Meter : NO K
9071 22:13:07.230469 CBT Training : PASS
9072 22:13:07.230551 Write leveling : PASS
9073 22:13:07.233862 RX DQS gating : PASS
9074 22:13:07.237549 RX DQ/DQS(RDDQC) : PASS
9075 22:13:07.237631 TX DQ/DQS : PASS
9076 22:13:07.240340 RX DATLAT : PASS
9077 22:13:07.243699 RX DQ/DQS(Engine): PASS
9078 22:13:07.243781 TX OE : PASS
9079 22:13:07.246830 All Pass.
9080 22:13:07.246912
9081 22:13:07.246977 CH 1, Rank 0
9082 22:13:07.250238 SW Impedance : PASS
9083 22:13:07.250319 DUTY Scan : NO K
9084 22:13:07.253685 ZQ Calibration : PASS
9085 22:13:07.257492 Jitter Meter : NO K
9086 22:13:07.257574 CBT Training : PASS
9087 22:13:07.260375 Write leveling : PASS
9088 22:13:07.263644 RX DQS gating : PASS
9089 22:13:07.263726 RX DQ/DQS(RDDQC) : PASS
9090 22:13:07.267313 TX DQ/DQS : PASS
9091 22:13:07.270478 RX DATLAT : PASS
9092 22:13:07.270560 RX DQ/DQS(Engine): PASS
9093 22:13:07.274049 TX OE : PASS
9094 22:13:07.274131 All Pass.
9095 22:13:07.274197
9096 22:13:07.274258 CH 1, Rank 1
9097 22:13:07.277114 SW Impedance : PASS
9098 22:13:07.280651 DUTY Scan : NO K
9099 22:13:07.280734 ZQ Calibration : PASS
9100 22:13:07.283808 Jitter Meter : NO K
9101 22:13:07.287271 CBT Training : PASS
9102 22:13:07.287358 Write leveling : PASS
9103 22:13:07.291047 RX DQS gating : PASS
9104 22:13:07.294066 RX DQ/DQS(RDDQC) : PASS
9105 22:13:07.294186 TX DQ/DQS : PASS
9106 22:13:07.297220 RX DATLAT : PASS
9107 22:13:07.300624 RX DQ/DQS(Engine): PASS
9108 22:13:07.300706 TX OE : PASS
9109 22:13:07.303737 All Pass.
9110 22:13:07.303818
9111 22:13:07.303903 DramC Write-DBI on
9112 22:13:07.307347 PER_BANK_REFRESH: Hybrid Mode
9113 22:13:07.307429 TX_TRACKING: ON
9114 22:13:07.317413 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9115 22:13:07.324110 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9116 22:13:07.333741 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9117 22:13:07.337607 [FAST_K] Save calibration result to emmc
9118 22:13:07.337687 sync common calibartion params.
9119 22:13:07.340778 sync cbt_mode0:1, 1:1
9120 22:13:07.343767 dram_init: ddr_geometry: 2
9121 22:13:07.347358 dram_init: ddr_geometry: 2
9122 22:13:07.347441 dram_init: ddr_geometry: 2
9123 22:13:07.350282 0:dram_rank_size:100000000
9124 22:13:07.353889 1:dram_rank_size:100000000
9125 22:13:07.357232 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9126 22:13:07.360399 DFS_SHUFFLE_HW_MODE: ON
9127 22:13:07.363735 dramc_set_vcore_voltage set vcore to 725000
9128 22:13:07.367118 Read voltage for 1600, 0
9129 22:13:07.367201 Vio18 = 0
9130 22:13:07.370382 Vcore = 725000
9131 22:13:07.370464 Vdram = 0
9132 22:13:07.370530 Vddq = 0
9133 22:13:07.370591 Vmddr = 0
9134 22:13:07.373997 switch to 3200 Mbps bootup
9135 22:13:07.377478 [DramcRunTimeConfig]
9136 22:13:07.377560 PHYPLL
9137 22:13:07.380804 DPM_CONTROL_AFTERK: ON
9138 22:13:07.380887 PER_BANK_REFRESH: ON
9139 22:13:07.383434 REFRESH_OVERHEAD_REDUCTION: ON
9140 22:13:07.386642 CMD_PICG_NEW_MODE: OFF
9141 22:13:07.386725 XRTWTW_NEW_MODE: ON
9142 22:13:07.390087 XRTRTR_NEW_MODE: ON
9143 22:13:07.390170 TX_TRACKING: ON
9144 22:13:07.394113 RDSEL_TRACKING: OFF
9145 22:13:07.397233 DQS Precalculation for DVFS: ON
9146 22:13:07.397316 RX_TRACKING: OFF
9147 22:13:07.400258 HW_GATING DBG: ON
9148 22:13:07.400341 ZQCS_ENABLE_LP4: ON
9149 22:13:07.403488 RX_PICG_NEW_MODE: ON
9150 22:13:07.403570 TX_PICG_NEW_MODE: ON
9151 22:13:07.406409 ENABLE_RX_DCM_DPHY: ON
9152 22:13:07.410055 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9153 22:13:07.413101 DUMMY_READ_FOR_TRACKING: OFF
9154 22:13:07.413183 !!! SPM_CONTROL_AFTERK: OFF
9155 22:13:07.416517 !!! SPM could not control APHY
9156 22:13:07.419597 IMPEDANCE_TRACKING: ON
9157 22:13:07.419680 TEMP_SENSOR: ON
9158 22:13:07.423808 HW_SAVE_FOR_SR: OFF
9159 22:13:07.426765 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9160 22:13:07.429951 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9161 22:13:07.430035 Read ODT Tracking: ON
9162 22:13:07.433370 Refresh Rate DeBounce: ON
9163 22:13:07.436453 DFS_NO_QUEUE_FLUSH: ON
9164 22:13:07.439751 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9165 22:13:07.439880 ENABLE_DFS_RUNTIME_MRW: OFF
9166 22:13:07.443307 DDR_RESERVE_NEW_MODE: ON
9167 22:13:07.446610 MR_CBT_SWITCH_FREQ: ON
9168 22:13:07.446693 =========================
9169 22:13:07.466752 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9170 22:13:07.470274 dram_init: ddr_geometry: 2
9171 22:13:07.488337 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9172 22:13:07.491526 dram_init: dram init end (result: 0)
9173 22:13:07.498747 DRAM-K: Full calibration passed in 24582 msecs
9174 22:13:07.501323 MRC: failed to locate region type 0.
9175 22:13:07.501407 DRAM rank0 size:0x100000000,
9176 22:13:07.505336 DRAM rank1 size=0x100000000
9177 22:13:07.515440 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9178 22:13:07.521579 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9179 22:13:07.528595 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9180 22:13:07.534521 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9181 22:13:07.538281 DRAM rank0 size:0x100000000,
9182 22:13:07.541136 DRAM rank1 size=0x100000000
9183 22:13:07.541238 CBMEM:
9184 22:13:07.544775 IMD: root @ 0xfffff000 254 entries.
9185 22:13:07.548050 IMD: root @ 0xffffec00 62 entries.
9186 22:13:07.551174 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9187 22:13:07.554562 WARNING: RO_VPD is uninitialized or empty.
9188 22:13:07.561363 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9189 22:13:07.568701 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9190 22:13:07.581083 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9191 22:13:07.592503 BS: romstage times (exec / console): total (unknown) / 24087 ms
9192 22:13:07.592592
9193 22:13:07.592675
9194 22:13:07.602297 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9195 22:13:07.605919 ARM64: Exception handlers installed.
9196 22:13:07.609154 ARM64: Testing exception
9197 22:13:07.612711 ARM64: Done test exception
9198 22:13:07.612787 Enumerating buses...
9199 22:13:07.615861 Show all devs... Before device enumeration.
9200 22:13:07.619190 Root Device: enabled 1
9201 22:13:07.622661 CPU_CLUSTER: 0: enabled 1
9202 22:13:07.622739 CPU: 00: enabled 1
9203 22:13:07.625973 Compare with tree...
9204 22:13:07.626053 Root Device: enabled 1
9205 22:13:07.628949 CPU_CLUSTER: 0: enabled 1
9206 22:13:07.632205 CPU: 00: enabled 1
9207 22:13:07.632278 Root Device scanning...
9208 22:13:07.635856 scan_static_bus for Root Device
9209 22:13:07.639164 CPU_CLUSTER: 0 enabled
9210 22:13:07.642971 scan_static_bus for Root Device done
9211 22:13:07.645902 scan_bus: bus Root Device finished in 8 msecs
9212 22:13:07.645973 done
9213 22:13:07.652780 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9214 22:13:07.655691 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9215 22:13:07.662733 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9216 22:13:07.666106 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9217 22:13:07.669000 Allocating resources...
9218 22:13:07.672216 Reading resources...
9219 22:13:07.675466 Root Device read_resources bus 0 link: 0
9220 22:13:07.675537 DRAM rank0 size:0x100000000,
9221 22:13:07.679060 DRAM rank1 size=0x100000000
9222 22:13:07.682195 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9223 22:13:07.685935 CPU: 00 missing read_resources
9224 22:13:07.688907 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9225 22:13:07.695260 Root Device read_resources bus 0 link: 0 done
9226 22:13:07.695339 Done reading resources.
9227 22:13:07.702141 Show resources in subtree (Root Device)...After reading.
9228 22:13:07.705231 Root Device child on link 0 CPU_CLUSTER: 0
9229 22:13:07.708756 CPU_CLUSTER: 0 child on link 0 CPU: 00
9230 22:13:07.718666 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9231 22:13:07.718837 CPU: 00
9232 22:13:07.722068 Root Device assign_resources, bus 0 link: 0
9233 22:13:07.725336 CPU_CLUSTER: 0 missing set_resources
9234 22:13:07.731813 Root Device assign_resources, bus 0 link: 0 done
9235 22:13:07.731895 Done setting resources.
9236 22:13:07.738439 Show resources in subtree (Root Device)...After assigning values.
9237 22:13:07.741874 Root Device child on link 0 CPU_CLUSTER: 0
9238 22:13:07.745590 CPU_CLUSTER: 0 child on link 0 CPU: 00
9239 22:13:07.755261 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9240 22:13:07.755339 CPU: 00
9241 22:13:07.758223 Done allocating resources.
9242 22:13:07.761516 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9243 22:13:07.764795 Enabling resources...
9244 22:13:07.764873 done.
9245 22:13:07.771796 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9246 22:13:07.771917 Initializing devices...
9247 22:13:07.774628 Root Device init
9248 22:13:07.774695 init hardware done!
9249 22:13:07.777920 0x00000018: ctrlr->caps
9250 22:13:07.781231 52.000 MHz: ctrlr->f_max
9251 22:13:07.781304 0.400 MHz: ctrlr->f_min
9252 22:13:07.784813 0x40ff8080: ctrlr->voltages
9253 22:13:07.784899 sclk: 390625
9254 22:13:07.788291 Bus Width = 1
9255 22:13:07.788364 sclk: 390625
9256 22:13:07.791506 Bus Width = 1
9257 22:13:07.791617 Early init status = 3
9258 22:13:07.798226 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9259 22:13:07.801369 in-header: 03 fb 00 00 01 00 00 00
9260 22:13:07.801445 in-data: 01
9261 22:13:07.807849 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9262 22:13:07.811808 in-header: 03 fb 00 00 01 00 00 00
9263 22:13:07.814901 in-data: 01
9264 22:13:07.817873 [SSUSB] Setting up USB HOST controller...
9265 22:13:07.821245 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9266 22:13:07.821324 [SSUSB] phy power-on done.
9267 22:13:07.827728 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9268 22:13:07.831092 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9269 22:13:07.837774 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9270 22:13:07.844989 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9271 22:13:07.851240 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9272 22:13:07.857490 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9273 22:13:07.864368 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9274 22:13:07.870734 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9275 22:13:07.870816 SPM: binary array size = 0x9dc
9276 22:13:07.877478 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9277 22:13:07.884063 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9278 22:13:07.890986 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9279 22:13:07.894233 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9280 22:13:07.897023 configure_display: Starting display init
9281 22:13:07.933879 anx7625_power_on_init: Init interface.
9282 22:13:07.937234 anx7625_disable_pd_protocol: Disabled PD feature.
9283 22:13:07.940559 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9284 22:13:07.968878 anx7625_start_dp_work: Secure OCM version=00
9285 22:13:07.971693 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9286 22:13:07.986207 sp_tx_get_edid_block: EDID Block = 1
9287 22:13:08.088935 Extracted contents:
9288 22:13:08.093007 header: 00 ff ff ff ff ff ff 00
9289 22:13:08.095622 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9290 22:13:08.099060 version: 01 04
9291 22:13:08.102094 basic params: 95 1f 11 78 0a
9292 22:13:08.105577 chroma info: 76 90 94 55 54 90 27 21 50 54
9293 22:13:08.108943 established: 00 00 00
9294 22:13:08.115225 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9295 22:13:08.119108 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9296 22:13:08.125708 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9297 22:13:08.132143 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9298 22:13:08.138458 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9299 22:13:08.141627 extensions: 00
9300 22:13:08.141702 checksum: fb
9301 22:13:08.141766
9302 22:13:08.145164 Manufacturer: IVO Model 57d Serial Number 0
9303 22:13:08.148428 Made week 0 of 2020
9304 22:13:08.148501 EDID version: 1.4
9305 22:13:08.151884 Digital display
9306 22:13:08.155359 6 bits per primary color channel
9307 22:13:08.155458 DisplayPort interface
9308 22:13:08.158532 Maximum image size: 31 cm x 17 cm
9309 22:13:08.161835 Gamma: 220%
9310 22:13:08.161908 Check DPMS levels
9311 22:13:08.165058 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9312 22:13:08.171819 First detailed timing is preferred timing
9313 22:13:08.171936 Established timings supported:
9314 22:13:08.174853 Standard timings supported:
9315 22:13:08.178368 Detailed timings
9316 22:13:08.181991 Hex of detail: 383680a07038204018303c0035ae10000019
9317 22:13:08.184935 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9318 22:13:08.191604 0780 0798 07c8 0820 hborder 0
9319 22:13:08.194948 0438 043b 0447 0458 vborder 0
9320 22:13:08.198300 -hsync -vsync
9321 22:13:08.198403 Did detailed timing
9322 22:13:08.201937 Hex of detail: 000000000000000000000000000000000000
9323 22:13:08.205067 Manufacturer-specified data, tag 0
9324 22:13:08.211466 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9325 22:13:08.211570 ASCII string: InfoVision
9326 22:13:08.218064 Hex of detail: 000000fe00523134304e574635205248200a
9327 22:13:08.222334 ASCII string: R140NWF5 RH
9328 22:13:08.222432 Checksum
9329 22:13:08.222522 Checksum: 0xfb (valid)
9330 22:13:08.228254 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9331 22:13:08.231751 DSI data_rate: 832800000 bps
9332 22:13:08.235197 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9333 22:13:08.241885 anx7625_parse_edid: pixelclock(138800).
9334 22:13:08.244880 hactive(1920), hsync(48), hfp(24), hbp(88)
9335 22:13:08.248599 vactive(1080), vsync(12), vfp(3), vbp(17)
9336 22:13:08.251390 anx7625_dsi_config: config dsi.
9337 22:13:08.258280 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9338 22:13:08.270723 anx7625_dsi_config: success to config DSI
9339 22:13:08.274428 anx7625_dp_start: MIPI phy setup OK.
9340 22:13:08.277628 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9341 22:13:08.281270 mtk_ddp_mode_set invalid vrefresh 60
9342 22:13:08.284054 main_disp_path_setup
9343 22:13:08.284136 ovl_layer_smi_id_en
9344 22:13:08.288011 ovl_layer_smi_id_en
9345 22:13:08.288093 ccorr_config
9346 22:13:08.288172 aal_config
9347 22:13:08.290890 gamma_config
9348 22:13:08.290986 postmask_config
9349 22:13:08.294474 dither_config
9350 22:13:08.297740 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9351 22:13:08.304088 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9352 22:13:08.307585 Root Device init finished in 529 msecs
9353 22:13:08.307682 CPU_CLUSTER: 0 init
9354 22:13:08.317403 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9355 22:13:08.321024 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9356 22:13:08.324316 APU_MBOX 0x190000b0 = 0x10001
9357 22:13:08.327149 APU_MBOX 0x190001b0 = 0x10001
9358 22:13:08.331258 APU_MBOX 0x190005b0 = 0x10001
9359 22:13:08.333846 APU_MBOX 0x190006b0 = 0x10001
9360 22:13:08.337972 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9361 22:13:08.349801 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9362 22:13:08.362610 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9363 22:13:08.368671 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9364 22:13:08.381002 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9365 22:13:08.389942 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9366 22:13:08.393204 CPU_CLUSTER: 0 init finished in 81 msecs
9367 22:13:08.396579 Devices initialized
9368 22:13:08.399805 Show all devs... After init.
9369 22:13:08.399913 Root Device: enabled 1
9370 22:13:08.403057 CPU_CLUSTER: 0: enabled 1
9371 22:13:08.406317 CPU: 00: enabled 1
9372 22:13:08.409976 BS: BS_DEV_INIT run times (exec / console): 206 / 428 ms
9373 22:13:08.413143 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9374 22:13:08.416512 ELOG: NV offset 0x57f000 size 0x1000
9375 22:13:08.422842 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9376 22:13:08.430063 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9377 22:13:08.432931 ELOG: Event(17) added with size 13 at 2023-06-04 22:13:21 UTC
9378 22:13:08.436059 out: cmd=0x121: 03 db 21 01 00 00 00 00
9379 22:13:08.439959 in-header: 03 e6 00 00 2c 00 00 00
9380 22:13:08.453286 in-data: 79 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9381 22:13:08.460146 ELOG: Event(A1) added with size 10 at 2023-06-04 22:13:21 UTC
9382 22:13:08.466897 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9383 22:13:08.473293 ELOG: Event(A0) added with size 9 at 2023-06-04 22:13:21 UTC
9384 22:13:08.476550 elog_add_boot_reason: Logged dev mode boot
9385 22:13:08.479664 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9386 22:13:08.483019 Finalize devices...
9387 22:13:08.483092 Devices finalized
9388 22:13:08.489637 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9389 22:13:08.493182 Writing coreboot table at 0xffe64000
9390 22:13:08.496594 0. 000000000010a000-0000000000113fff: RAMSTAGE
9391 22:13:08.499672 1. 0000000040000000-00000000400fffff: RAM
9392 22:13:08.506643 2. 0000000040100000-000000004032afff: RAMSTAGE
9393 22:13:08.509750 3. 000000004032b000-00000000545fffff: RAM
9394 22:13:08.513244 4. 0000000054600000-000000005465ffff: BL31
9395 22:13:08.516112 5. 0000000054660000-00000000ffe63fff: RAM
9396 22:13:08.522767 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9397 22:13:08.526156 7. 0000000100000000-000000023fffffff: RAM
9398 22:13:08.526254 Passing 5 GPIOs to payload:
9399 22:13:08.532855 NAME | PORT | POLARITY | VALUE
9400 22:13:08.536363 EC in RW | 0x000000aa | low | undefined
9401 22:13:08.542944 EC interrupt | 0x00000005 | low | undefined
9402 22:13:08.546386 TPM interrupt | 0x000000ab | high | undefined
9403 22:13:08.552552 SD card detect | 0x00000011 | high | undefined
9404 22:13:08.556346 speaker enable | 0x00000093 | high | undefined
9405 22:13:08.559551 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9406 22:13:08.562802 in-header: 03 f9 00 00 02 00 00 00
9407 22:13:08.566121 in-data: 02 00
9408 22:13:08.569325 ADC[4]: Raw value=899852 ID=7
9409 22:13:08.569400 ADC[3]: Raw value=213336 ID=1
9410 22:13:08.572758 RAM Code: 0x71
9411 22:13:08.575749 ADC[6]: Raw value=74557 ID=0
9412 22:13:08.575848 ADC[5]: Raw value=211860 ID=1
9413 22:13:08.579420 SKU Code: 0x1
9414 22:13:08.586375 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum ded1
9415 22:13:08.586455 coreboot table: 964 bytes.
9416 22:13:08.589571 IMD ROOT 0. 0xfffff000 0x00001000
9417 22:13:08.592897 IMD SMALL 1. 0xffffe000 0x00001000
9418 22:13:08.596407 RO MCACHE 2. 0xffffc000 0x00001104
9419 22:13:08.599522 CONSOLE 3. 0xfff7c000 0x00080000
9420 22:13:08.602549 FMAP 4. 0xfff7b000 0x00000452
9421 22:13:08.606300 TIME STAMP 5. 0xfff7a000 0x00000910
9422 22:13:08.609071 VBOOT WORK 6. 0xfff66000 0x00014000
9423 22:13:08.612750 RAMOOPS 7. 0xffe66000 0x00100000
9424 22:13:08.615673 COREBOOT 8. 0xffe64000 0x00002000
9425 22:13:08.619411 IMD small region:
9426 22:13:08.622543 IMD ROOT 0. 0xffffec00 0x00000400
9427 22:13:08.626341 VPD 1. 0xffffeba0 0x0000004c
9428 22:13:08.629006 MMC STATUS 2. 0xffffeb80 0x00000004
9429 22:13:08.632266 BS: BS_WRITE_TABLES run times (exec / console): 2 / 137 ms
9430 22:13:08.635744 Probing TPM: done!
9431 22:13:08.639062 Connected to device vid:did:rid of 1ae0:0028:00
9432 22:13:08.649725 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9433 22:13:08.653273 Initialized TPM device CR50 revision 0
9434 22:13:08.657361 Checking cr50 for pending updates
9435 22:13:08.660743 Reading cr50 TPM mode
9436 22:13:08.669370 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9437 22:13:08.676062 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9438 22:13:08.716141 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9439 22:13:08.719352 Checking segment from ROM address 0x40100000
9440 22:13:08.723021 Checking segment from ROM address 0x4010001c
9441 22:13:08.729202 Loading segment from ROM address 0x40100000
9442 22:13:08.729304 code (compression=0)
9443 22:13:08.735748 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9444 22:13:08.746199 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9445 22:13:08.746306 it's not compressed!
9446 22:13:08.752889 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9447 22:13:08.755905 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9448 22:13:08.776368 Loading segment from ROM address 0x4010001c
9449 22:13:08.776465 Entry Point 0x80000000
9450 22:13:08.779202 Loaded segments
9451 22:13:08.782795 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9452 22:13:08.789618 Jumping to boot code at 0x80000000(0xffe64000)
9453 22:13:08.796430 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9454 22:13:08.802454 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9455 22:13:08.810695 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9456 22:13:08.814269 Checking segment from ROM address 0x40100000
9457 22:13:08.817402 Checking segment from ROM address 0x4010001c
9458 22:13:08.824049 Loading segment from ROM address 0x40100000
9459 22:13:08.824153 code (compression=1)
9460 22:13:08.830558 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9461 22:13:08.840885 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9462 22:13:08.841030 using LZMA
9463 22:13:08.849343 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9464 22:13:08.855908 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9465 22:13:08.858711 Loading segment from ROM address 0x4010001c
9466 22:13:08.858792 Entry Point 0x54601000
9467 22:13:08.862104 Loaded segments
9468 22:13:08.865258 NOTICE: MT8192 bl31_setup
9469 22:13:08.872660 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9470 22:13:08.875941 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9471 22:13:08.879341 WARNING: region 0:
9472 22:13:08.882797 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9473 22:13:08.882900 WARNING: region 1:
9474 22:13:08.889364 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9475 22:13:08.892644 WARNING: region 2:
9476 22:13:08.896182 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9477 22:13:08.899047 WARNING: region 3:
9478 22:13:08.902575 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9479 22:13:08.906394 WARNING: region 4:
9480 22:13:08.913088 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9481 22:13:08.913225 WARNING: region 5:
9482 22:13:08.916140 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9483 22:13:08.919574 WARNING: region 6:
9484 22:13:08.922963 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9485 22:13:08.925991 WARNING: region 7:
9486 22:13:08.929281 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9487 22:13:08.936190 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9488 22:13:08.939454 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9489 22:13:08.942681 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9490 22:13:08.949100 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9491 22:13:08.952617 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9492 22:13:08.955798 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9493 22:13:08.962359 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9494 22:13:08.965962 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9495 22:13:08.972376 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9496 22:13:08.975943 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9497 22:13:08.979222 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9498 22:13:08.986292 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9499 22:13:08.988872 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9500 22:13:08.992660 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9501 22:13:08.999137 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9502 22:13:09.002327 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9503 22:13:09.009328 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9504 22:13:09.012787 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9505 22:13:09.015917 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9506 22:13:09.022447 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9507 22:13:09.026207 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9508 22:13:09.029484 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9509 22:13:09.036331 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9510 22:13:09.039466 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9511 22:13:09.045815 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9512 22:13:09.049402 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9513 22:13:09.052552 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9514 22:13:09.059244 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9515 22:13:09.062883 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9516 22:13:09.066219 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9517 22:13:09.073041 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9518 22:13:09.076086 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9519 22:13:09.082697 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9520 22:13:09.085956 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9521 22:13:09.089369 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9522 22:13:09.092765 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9523 22:13:09.096288 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9524 22:13:09.103280 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9525 22:13:09.106156 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9526 22:13:09.109865 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9527 22:13:09.113029 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9528 22:13:09.119409 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9529 22:13:09.122930 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9530 22:13:09.126671 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9531 22:13:09.129391 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9532 22:13:09.136383 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9533 22:13:09.140082 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9534 22:13:09.143186 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9535 22:13:09.149812 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9536 22:13:09.153201 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9537 22:13:09.156406 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9538 22:13:09.162793 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9539 22:13:09.166193 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9540 22:13:09.173063 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9541 22:13:09.176363 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9542 22:13:09.183033 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9543 22:13:09.186300 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9544 22:13:09.189838 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9545 22:13:09.196175 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9546 22:13:09.199877 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9547 22:13:09.206228 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9548 22:13:09.210272 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9549 22:13:09.217010 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9550 22:13:09.219557 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9551 22:13:09.223211 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9552 22:13:09.230030 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9553 22:13:09.233357 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9554 22:13:09.240285 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9555 22:13:09.243293 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9556 22:13:09.250668 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9557 22:13:09.253385 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9558 22:13:09.256474 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9559 22:13:09.263315 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9560 22:13:09.266603 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9561 22:13:09.273456 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9562 22:13:09.277010 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9563 22:13:09.283005 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9564 22:13:09.286713 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9565 22:13:09.293183 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9566 22:13:09.296592 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9567 22:13:09.300271 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9568 22:13:09.306424 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9569 22:13:09.310027 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9570 22:13:09.316752 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9571 22:13:09.319583 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9572 22:13:09.322998 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9573 22:13:09.329717 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9574 22:13:09.333447 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9575 22:13:09.339626 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9576 22:13:09.343405 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9577 22:13:09.350478 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9578 22:13:09.352980 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9579 22:13:09.356364 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9580 22:13:09.363295 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9581 22:13:09.366736 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9582 22:13:09.373065 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9583 22:13:09.376772 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9584 22:13:09.380065 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9585 22:13:09.386637 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9586 22:13:09.390253 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9587 22:13:09.393640 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9588 22:13:09.397105 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9589 22:13:09.403591 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9590 22:13:09.407406 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9591 22:13:09.413473 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9592 22:13:09.416891 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9593 22:13:09.420065 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9594 22:13:09.426456 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9595 22:13:09.429748 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9596 22:13:09.436930 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9597 22:13:09.440143 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9598 22:13:09.443347 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9599 22:13:09.449938 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9600 22:13:09.453307 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9601 22:13:09.459917 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9602 22:13:09.463024 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9603 22:13:09.467060 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9604 22:13:09.473319 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9605 22:13:09.476340 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9606 22:13:09.480386 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9607 22:13:09.483438 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9608 22:13:09.490006 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9609 22:13:09.493177 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9610 22:13:09.496477 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9611 22:13:09.503646 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9612 22:13:09.506370 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9613 22:13:09.509739 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9614 22:13:09.516552 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9615 22:13:09.519924 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9616 22:13:09.526737 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9617 22:13:09.529697 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9618 22:13:09.532967 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9619 22:13:09.539723 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9620 22:13:09.542792 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9621 22:13:09.546070 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9622 22:13:09.552809 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9623 22:13:09.556587 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9624 22:13:09.562843 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9625 22:13:09.566318 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9626 22:13:09.569883 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9627 22:13:09.576489 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9628 22:13:09.579860 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9629 22:13:09.586524 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9630 22:13:09.590009 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9631 22:13:09.592765 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9632 22:13:09.599469 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9633 22:13:09.602846 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9634 22:13:09.606166 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9635 22:13:09.612824 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9636 22:13:09.616465 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9637 22:13:09.623367 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9638 22:13:09.626275 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9639 22:13:09.629733 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9640 22:13:09.636467 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9641 22:13:09.639633 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9642 22:13:09.645864 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9643 22:13:09.649455 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9644 22:13:09.652975 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9645 22:13:09.659472 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9646 22:13:09.662962 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9647 22:13:09.669220 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9648 22:13:09.672791 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9649 22:13:09.676248 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9650 22:13:09.682642 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9651 22:13:09.685898 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9652 22:13:09.689138 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9653 22:13:09.696194 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9654 22:13:09.698996 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9655 22:13:09.705626 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9656 22:13:09.708859 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9657 22:13:09.712645 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9658 22:13:09.719254 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9659 22:13:09.722355 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9660 22:13:09.729427 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9661 22:13:09.732380 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9662 22:13:09.735544 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9663 22:13:09.742251 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9664 22:13:09.745450 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9665 22:13:09.752349 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9666 22:13:09.755573 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9667 22:13:09.758734 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9668 22:13:09.765551 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9669 22:13:09.768545 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9670 22:13:09.775535 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9671 22:13:09.778208 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9672 22:13:09.781861 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9673 22:13:09.788194 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9674 22:13:09.791904 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9675 22:13:09.798496 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9676 22:13:09.801993 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9677 22:13:09.804976 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9678 22:13:09.811516 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9679 22:13:09.815020 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9680 22:13:09.821838 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9681 22:13:09.825401 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9682 22:13:09.828461 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9683 22:13:09.835103 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9684 22:13:09.838230 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9685 22:13:09.845026 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9686 22:13:09.848345 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9687 22:13:09.854767 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9688 22:13:09.858041 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9689 22:13:09.861527 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9690 22:13:09.868206 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9691 22:13:09.871302 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9692 22:13:09.878263 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9693 22:13:09.881343 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9694 22:13:09.884625 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9695 22:13:09.891648 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9696 22:13:09.895022 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9697 22:13:09.901600 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9698 22:13:09.904480 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9699 22:13:09.911049 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9700 22:13:09.915059 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9701 22:13:09.918076 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9702 22:13:09.924402 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9703 22:13:09.927568 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9704 22:13:09.934232 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9705 22:13:09.937789 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9706 22:13:09.944079 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9707 22:13:09.947462 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9708 22:13:09.950807 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9709 22:13:09.957793 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9710 22:13:09.961540 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9711 22:13:09.967913 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9712 22:13:09.971046 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9713 22:13:09.977499 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9714 22:13:09.980700 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9715 22:13:09.984025 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9716 22:13:09.990576 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9717 22:13:09.993874 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9718 22:13:09.997512 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9719 22:13:10.000561 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9720 22:13:10.004209 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9721 22:13:10.010683 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9722 22:13:10.013722 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9723 22:13:10.020572 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9724 22:13:10.024126 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9725 22:13:10.027374 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9726 22:13:10.034314 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9727 22:13:10.037021 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9728 22:13:10.041151 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9729 22:13:10.047071 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9730 22:13:10.050287 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9731 22:13:10.054026 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9732 22:13:10.060835 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9733 22:13:10.064259 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9734 22:13:10.070147 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9735 22:13:10.073611 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9736 22:13:10.077011 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9737 22:13:10.083838 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9738 22:13:10.086902 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9739 22:13:10.094023 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9740 22:13:10.096784 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9741 22:13:10.100240 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9742 22:13:10.107104 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9743 22:13:10.110055 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9744 22:13:10.113676 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9745 22:13:10.120127 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9746 22:13:10.123151 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9747 22:13:10.126762 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9748 22:13:10.133292 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9749 22:13:10.136831 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9750 22:13:10.140043 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9751 22:13:10.146590 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9752 22:13:10.150562 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9753 22:13:10.156447 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9754 22:13:10.160054 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9755 22:13:10.163248 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9756 22:13:10.166388 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9757 22:13:10.173434 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9758 22:13:10.176800 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9759 22:13:10.180654 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9760 22:13:10.182946 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9761 22:13:10.189645 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9762 22:13:10.192878 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9763 22:13:10.196149 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9764 22:13:10.199787 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9765 22:13:10.206098 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9766 22:13:10.209820 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9767 22:13:10.213069 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9768 22:13:10.216382 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9769 22:13:10.222979 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9770 22:13:10.226144 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9771 22:13:10.233238 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9772 22:13:10.236391 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9773 22:13:10.243061 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9774 22:13:10.246121 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9775 22:13:10.250022 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9776 22:13:10.256006 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9777 22:13:10.259589 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9778 22:13:10.265999 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9779 22:13:10.269607 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9780 22:13:10.272855 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9781 22:13:10.279270 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9782 22:13:10.282860 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9783 22:13:10.289224 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9784 22:13:10.292619 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9785 22:13:10.295750 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9786 22:13:10.302522 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9787 22:13:10.305797 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9788 22:13:10.312353 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9789 22:13:10.315877 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9790 22:13:10.322375 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9791 22:13:10.325599 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9792 22:13:10.329072 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9793 22:13:10.335990 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9794 22:13:10.339019 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9795 22:13:10.345866 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9796 22:13:10.349012 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9797 22:13:10.352333 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9798 22:13:10.358821 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9799 22:13:10.362349 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9800 22:13:10.369115 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9801 22:13:10.372606 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9802 22:13:10.375554 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9803 22:13:10.382352 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9804 22:13:10.385344 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9805 22:13:10.392069 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9806 22:13:10.395632 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9807 22:13:10.402012 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9808 22:13:10.405634 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9809 22:13:10.408657 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9810 22:13:10.415363 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9811 22:13:10.419037 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9812 22:13:10.425292 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9813 22:13:10.428472 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9814 22:13:10.431867 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9815 22:13:10.438749 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9816 22:13:10.442082 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9817 22:13:10.445399 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9818 22:13:10.451844 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9819 22:13:10.455554 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9820 22:13:10.462132 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9821 22:13:10.465466 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9822 22:13:10.472324 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9823 22:13:10.475239 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9824 22:13:10.478588 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9825 22:13:10.484812 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9826 22:13:10.488404 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9827 22:13:10.495226 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9828 22:13:10.498886 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9829 22:13:10.501477 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9830 22:13:10.508575 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9831 22:13:10.512015 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9832 22:13:10.518213 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9833 22:13:10.521571 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9834 22:13:10.525079 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9835 22:13:10.531643 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9836 22:13:10.535454 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9837 22:13:10.541429 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9838 22:13:10.545112 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9839 22:13:10.551690 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9840 22:13:10.555244 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9841 22:13:10.558154 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9842 22:13:10.564754 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9843 22:13:10.567843 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9844 22:13:10.574893 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9845 22:13:10.578009 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9846 22:13:10.584525 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9847 22:13:10.588406 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9848 22:13:10.591043 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9849 22:13:10.597794 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9850 22:13:10.601157 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9851 22:13:10.607887 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9852 22:13:10.611379 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9853 22:13:10.617663 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9854 22:13:10.620719 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9855 22:13:10.627638 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9856 22:13:10.630968 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9857 22:13:10.634519 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9858 22:13:10.641006 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9859 22:13:10.644509 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9860 22:13:10.650808 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9861 22:13:10.654073 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9862 22:13:10.660690 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9863 22:13:10.664080 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9864 22:13:10.667457 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9865 22:13:10.674986 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9866 22:13:10.677148 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9867 22:13:10.683818 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9868 22:13:10.687234 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9869 22:13:10.694111 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9870 22:13:10.697420 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9871 22:13:10.704048 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9872 22:13:10.706772 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9873 22:13:10.710392 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9874 22:13:10.717252 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9875 22:13:10.720250 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9876 22:13:10.726863 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9877 22:13:10.730141 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9878 22:13:10.736817 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9879 22:13:10.740011 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9880 22:13:10.743952 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9881 22:13:10.749785 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9882 22:13:10.753252 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9883 22:13:10.759729 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9884 22:13:10.763465 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9885 22:13:10.770139 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9886 22:13:10.773432 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9887 22:13:10.780085 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9888 22:13:10.783513 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9889 22:13:10.786934 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9890 22:13:10.793149 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9891 22:13:10.796370 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9892 22:13:10.802851 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9893 22:13:10.806274 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9894 22:13:10.812947 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9895 22:13:10.817081 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9896 22:13:10.819692 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9897 22:13:10.826375 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9898 22:13:10.829678 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9899 22:13:10.836570 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9900 22:13:10.839651 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9901 22:13:10.846305 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9902 22:13:10.849360 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9903 22:13:10.856473 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9904 22:13:10.859197 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9905 22:13:10.866032 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9906 22:13:10.869587 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9907 22:13:10.876287 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9908 22:13:10.879532 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9909 22:13:10.886515 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9910 22:13:10.889138 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9911 22:13:10.896127 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9912 22:13:10.899409 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9913 22:13:10.905821 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9914 22:13:10.909252 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9915 22:13:10.915805 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9916 22:13:10.919222 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9917 22:13:10.925715 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9918 22:13:10.929017 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9919 22:13:10.936043 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9920 22:13:10.939235 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9921 22:13:10.945954 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9922 22:13:10.946034 INFO: [APUAPC] vio 0
9923 22:13:10.952418 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9924 22:13:10.956315 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9925 22:13:10.959487 INFO: [APUAPC] D0_APC_0: 0x400510
9926 22:13:10.962572 INFO: [APUAPC] D0_APC_1: 0x0
9927 22:13:10.965852 INFO: [APUAPC] D0_APC_2: 0x1540
9928 22:13:10.969224 INFO: [APUAPC] D0_APC_3: 0x0
9929 22:13:10.972241 INFO: [APUAPC] D1_APC_0: 0xffffffff
9930 22:13:10.975603 INFO: [APUAPC] D1_APC_1: 0xffffffff
9931 22:13:10.979117 INFO: [APUAPC] D1_APC_2: 0x3fffff
9932 22:13:10.982482 INFO: [APUAPC] D1_APC_3: 0x0
9933 22:13:10.985657 INFO: [APUAPC] D2_APC_0: 0xffffffff
9934 22:13:10.988971 INFO: [APUAPC] D2_APC_1: 0xffffffff
9935 22:13:10.992254 INFO: [APUAPC] D2_APC_2: 0x3fffff
9936 22:13:10.995835 INFO: [APUAPC] D2_APC_3: 0x0
9937 22:13:10.998647 INFO: [APUAPC] D3_APC_0: 0xffffffff
9938 22:13:11.002394 INFO: [APUAPC] D3_APC_1: 0xffffffff
9939 22:13:11.006489 INFO: [APUAPC] D3_APC_2: 0x3fffff
9940 22:13:11.009014 INFO: [APUAPC] D3_APC_3: 0x0
9941 22:13:11.011957 INFO: [APUAPC] D4_APC_0: 0xffffffff
9942 22:13:11.015493 INFO: [APUAPC] D4_APC_1: 0xffffffff
9943 22:13:11.018832 INFO: [APUAPC] D4_APC_2: 0x3fffff
9944 22:13:11.018907 INFO: [APUAPC] D4_APC_3: 0x0
9945 22:13:11.022451 INFO: [APUAPC] D5_APC_0: 0xffffffff
9946 22:13:11.028903 INFO: [APUAPC] D5_APC_1: 0xffffffff
9947 22:13:11.028979 INFO: [APUAPC] D5_APC_2: 0x3fffff
9948 22:13:11.032479 INFO: [APUAPC] D5_APC_3: 0x0
9949 22:13:11.035585 INFO: [APUAPC] D6_APC_0: 0xffffffff
9950 22:13:11.039120 INFO: [APUAPC] D6_APC_1: 0xffffffff
9951 22:13:11.042319 INFO: [APUAPC] D6_APC_2: 0x3fffff
9952 22:13:11.045816 INFO: [APUAPC] D6_APC_3: 0x0
9953 22:13:11.048727 INFO: [APUAPC] D7_APC_0: 0xffffffff
9954 22:13:11.052201 INFO: [APUAPC] D7_APC_1: 0xffffffff
9955 22:13:11.055642 INFO: [APUAPC] D7_APC_2: 0x3fffff
9956 22:13:11.059140 INFO: [APUAPC] D7_APC_3: 0x0
9957 22:13:11.062389 INFO: [APUAPC] D8_APC_0: 0xffffffff
9958 22:13:11.065785 INFO: [APUAPC] D8_APC_1: 0xffffffff
9959 22:13:11.069034 INFO: [APUAPC] D8_APC_2: 0x3fffff
9960 22:13:11.072165 INFO: [APUAPC] D8_APC_3: 0x0
9961 22:13:11.075373 INFO: [APUAPC] D9_APC_0: 0xffffffff
9962 22:13:11.078696 INFO: [APUAPC] D9_APC_1: 0xffffffff
9963 22:13:11.082284 INFO: [APUAPC] D9_APC_2: 0x3fffff
9964 22:13:11.085657 INFO: [APUAPC] D9_APC_3: 0x0
9965 22:13:11.088972 INFO: [APUAPC] D10_APC_0: 0xffffffff
9966 22:13:11.092196 INFO: [APUAPC] D10_APC_1: 0xffffffff
9967 22:13:11.095287 INFO: [APUAPC] D10_APC_2: 0x3fffff
9968 22:13:11.098489 INFO: [APUAPC] D10_APC_3: 0x0
9969 22:13:11.102288 INFO: [APUAPC] D11_APC_0: 0xffffffff
9970 22:13:11.105156 INFO: [APUAPC] D11_APC_1: 0xffffffff
9971 22:13:11.108658 INFO: [APUAPC] D11_APC_2: 0x3fffff
9972 22:13:11.112137 INFO: [APUAPC] D11_APC_3: 0x0
9973 22:13:11.115380 INFO: [APUAPC] D12_APC_0: 0xffffffff
9974 22:13:11.118705 INFO: [APUAPC] D12_APC_1: 0xffffffff
9975 22:13:11.122439 INFO: [APUAPC] D12_APC_2: 0x3fffff
9976 22:13:11.125752 INFO: [APUAPC] D12_APC_3: 0x0
9977 22:13:11.128415 INFO: [APUAPC] D13_APC_0: 0xffffffff
9978 22:13:11.131593 INFO: [APUAPC] D13_APC_1: 0xffffffff
9979 22:13:11.135492 INFO: [APUAPC] D13_APC_2: 0x3fffff
9980 22:13:11.138702 INFO: [APUAPC] D13_APC_3: 0x0
9981 22:13:11.142011 INFO: [APUAPC] D14_APC_0: 0xffffffff
9982 22:13:11.145326 INFO: [APUAPC] D14_APC_1: 0xffffffff
9983 22:13:11.148165 INFO: [APUAPC] D14_APC_2: 0x3fffff
9984 22:13:11.151740 INFO: [APUAPC] D14_APC_3: 0x0
9985 22:13:11.154942 INFO: [APUAPC] D15_APC_0: 0xffffffff
9986 22:13:11.158659 INFO: [APUAPC] D15_APC_1: 0xffffffff
9987 22:13:11.161645 INFO: [APUAPC] D15_APC_2: 0x3fffff
9988 22:13:11.164870 INFO: [APUAPC] D15_APC_3: 0x0
9989 22:13:11.168069 INFO: [APUAPC] APC_CON: 0x4
9990 22:13:11.171860 INFO: [NOCDAPC] D0_APC_0: 0x0
9991 22:13:11.174621 INFO: [NOCDAPC] D0_APC_1: 0x0
9992 22:13:11.178412 INFO: [NOCDAPC] D1_APC_0: 0x0
9993 22:13:11.181816 INFO: [NOCDAPC] D1_APC_1: 0xfff
9994 22:13:11.181890 INFO: [NOCDAPC] D2_APC_0: 0x0
9995 22:13:11.185134 INFO: [NOCDAPC] D2_APC_1: 0xfff
9996 22:13:11.187838 INFO: [NOCDAPC] D3_APC_0: 0x0
9997 22:13:11.191468 INFO: [NOCDAPC] D3_APC_1: 0xfff
9998 22:13:11.194754 INFO: [NOCDAPC] D4_APC_0: 0x0
9999 22:13:11.198270 INFO: [NOCDAPC] D4_APC_1: 0xfff
10000 22:13:11.201580 INFO: [NOCDAPC] D5_APC_0: 0x0
10001 22:13:11.204508 INFO: [NOCDAPC] D5_APC_1: 0xfff
10002 22:13:11.208621 INFO: [NOCDAPC] D6_APC_0: 0x0
10003 22:13:11.211937 INFO: [NOCDAPC] D6_APC_1: 0xfff
10004 22:13:11.214470 INFO: [NOCDAPC] D7_APC_0: 0x0
10005 22:13:11.218076 INFO: [NOCDAPC] D7_APC_1: 0xfff
10006 22:13:11.218153 INFO: [NOCDAPC] D8_APC_0: 0x0
10007 22:13:11.220963 INFO: [NOCDAPC] D8_APC_1: 0xfff
10008 22:13:11.224904 INFO: [NOCDAPC] D9_APC_0: 0x0
10009 22:13:11.228139 INFO: [NOCDAPC] D9_APC_1: 0xfff
10010 22:13:11.231328 INFO: [NOCDAPC] D10_APC_0: 0x0
10011 22:13:11.234426 INFO: [NOCDAPC] D10_APC_1: 0xfff
10012 22:13:11.238320 INFO: [NOCDAPC] D11_APC_0: 0x0
10013 22:13:11.241142 INFO: [NOCDAPC] D11_APC_1: 0xfff
10014 22:13:11.245112 INFO: [NOCDAPC] D12_APC_0: 0x0
10015 22:13:11.247883 INFO: [NOCDAPC] D12_APC_1: 0xfff
10016 22:13:11.251358 INFO: [NOCDAPC] D13_APC_0: 0x0
10017 22:13:11.255138 INFO: [NOCDAPC] D13_APC_1: 0xfff
10018 22:13:11.258254 INFO: [NOCDAPC] D14_APC_0: 0x0
10019 22:13:11.258393 INFO: [NOCDAPC] D14_APC_1: 0xfff
10020 22:13:11.261108 INFO: [NOCDAPC] D15_APC_0: 0x0
10021 22:13:11.264934 INFO: [NOCDAPC] D15_APC_1: 0xfff
10022 22:13:11.267763 INFO: [NOCDAPC] APC_CON: 0x4
10023 22:13:11.271033 INFO: [APUAPC] set_apusys_apc done
10024 22:13:11.274666 INFO: [DEVAPC] devapc_init done
10025 22:13:11.277636 INFO: GICv3 without legacy support detected.
10026 22:13:11.284534 INFO: ARM GICv3 driver initialized in EL3
10027 22:13:11.287784 INFO: Maximum SPI INTID supported: 639
10028 22:13:11.291333 INFO: BL31: Initializing runtime services
10029 22:13:11.297533 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10030 22:13:11.301612 INFO: SPM: enable CPC mode
10031 22:13:11.304587 INFO: mcdi ready for mcusys-off-idle and system suspend
10032 22:13:11.311320 INFO: BL31: Preparing for EL3 exit to normal world
10033 22:13:11.314397 INFO: Entry point address = 0x80000000
10034 22:13:11.314497 INFO: SPSR = 0x8
10035 22:13:11.320883
10036 22:13:11.320984
10037 22:13:11.321084
10038 22:13:11.323820 Starting depthcharge on Spherion...
10039 22:13:11.323917
10040 22:13:11.324067 Wipe memory regions:
10041 22:13:11.324145
10042 22:13:11.324784 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10043 22:13:11.324923 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10044 22:13:11.325008 Setting prompt string to ['asurada:']
10045 22:13:11.325109 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10046 22:13:11.326983 [0x00000040000000, 0x00000054600000)
10047 22:13:11.450665
10048 22:13:11.450820 [0x00000054660000, 0x00000080000000)
10049 22:13:11.710155
10050 22:13:11.710293 [0x000000821a7280, 0x000000ffe64000)
10051 22:13:12.455140
10052 22:13:12.455281 [0x00000100000000, 0x00000240000000)
10053 22:13:14.345338
10054 22:13:14.348622 Initializing XHCI USB controller at 0x11200000.
10055 22:13:15.387657
10056 22:13:15.390829 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10057 22:13:15.390928
10058 22:13:15.390995
10059 22:13:15.391058
10060 22:13:15.391337 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10062 22:13:15.491688 asurada: tftpboot 192.168.201.1 10583887/tftp-deploy-bh6vuykx/kernel/image.itb 10583887/tftp-deploy-bh6vuykx/kernel/cmdline
10063 22:13:15.491827 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10064 22:13:15.491936 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10065 22:13:15.496065 tftpboot 192.168.201.1 10583887/tftp-deploy-bh6vuykx/kernel/image.ittp-deploy-bh6vuykx/kernel/cmdline
10066 22:13:15.496186
10067 22:13:15.496257 Waiting for link
10068 22:13:15.656554
10069 22:13:15.656688 R8152: Initializing
10070 22:13:15.656760
10071 22:13:15.659886 Version 6 (ocp_data = 5c30)
10072 22:13:15.659979
10073 22:13:15.663193 R8152: Done initializing
10074 22:13:15.663318
10075 22:13:15.663385 Adding net device
10076 22:13:17.812537
10077 22:13:17.812677 done.
10078 22:13:17.812747
10079 22:13:17.812811 MAC: 00:24:32:30:78:52
10080 22:13:17.812872
10081 22:13:17.816351 Sending DHCP discover... done.
10082 22:13:17.816436
10083 22:13:23.803087 Waiting for reply... done.
10084 22:13:23.803477
10085 22:13:23.803737 Sending DHCP request... done.
10086 22:13:23.806195
10087 22:13:23.809755 Waiting for reply... done.
10088 22:13:23.810119
10089 22:13:23.810364 My ip is 192.168.201.14
10090 22:13:23.810588
10091 22:13:23.813590 The DHCP server ip is 192.168.201.1
10092 22:13:23.813899
10093 22:13:23.819425 TFTP server IP predefined by user: 192.168.201.1
10094 22:13:23.819782
10095 22:13:23.826398 Bootfile predefined by user: 10583887/tftp-deploy-bh6vuykx/kernel/image.itb
10096 22:13:23.826738
10097 22:13:23.827110 Sending tftp read request... done.
10098 22:13:23.829675
10099 22:13:23.834639 Waiting for the transfer...
10100 22:13:23.834972
10101 22:13:24.458848 00000000 ################################################################
10102 22:13:24.459421
10103 22:13:25.080615 00080000 ################################################################
10104 22:13:25.081119
10105 22:13:25.735922 00100000 ################################################################
10106 22:13:25.736102
10107 22:13:26.376202 00180000 ################################################################
10108 22:13:26.376724
10109 22:13:27.068472 00200000 ################################################################
10110 22:13:27.068966
10111 22:13:27.775992 00280000 ################################################################
10112 22:13:27.776509
10113 22:13:28.463206 00300000 ################################################################
10114 22:13:28.463360
10115 22:13:29.158677 00380000 ################################################################
10116 22:13:29.159215
10117 22:13:29.859721 00400000 ################################################################
10118 22:13:29.860283
10119 22:13:30.573779 00480000 ################################################################
10120 22:13:30.574300
10121 22:13:31.298504 00500000 ################################################################
10122 22:13:31.299084
10123 22:13:32.040190 00580000 ################################################################
10124 22:13:32.040732
10125 22:13:32.760127 00600000 ################################################################
10126 22:13:32.760694
10127 22:13:33.489160 00680000 ################################################################
10128 22:13:33.489741
10129 22:13:34.218041 00700000 ################################################################
10130 22:13:34.218577
10131 22:13:34.945026 00780000 ################################################################
10132 22:13:34.945560
10133 22:13:35.670594 00800000 ################################################################
10134 22:13:35.671203
10135 22:13:36.388201 00880000 ################################################################
10136 22:13:36.388751
10137 22:13:37.109477 00900000 ################################################################
10138 22:13:37.110048
10139 22:13:37.820545 00980000 ################################################################
10140 22:13:37.821066
10141 22:13:38.545422 00a00000 ################################################################
10142 22:13:38.545948
10143 22:13:39.262796 00a80000 ################################################################
10144 22:13:39.263314
10145 22:13:39.971293 00b00000 ################################################################
10146 22:13:39.972017
10147 22:13:40.613479 00b80000 ################################################################
10148 22:13:40.614020
10149 22:13:41.321763 00c00000 ################################################################
10150 22:13:41.322325
10151 22:13:42.027816 00c80000 ################################################################
10152 22:13:42.028378
10153 22:13:42.699510 00d00000 ################################################################
10154 22:13:42.700033
10155 22:13:43.333575 00d80000 ################################################################
10156 22:13:43.333711
10157 22:13:43.906583 00e00000 ################################################################
10158 22:13:43.906722
10159 22:13:44.526759 00e80000 ################################################################
10160 22:13:44.527326
10161 22:13:45.190435 00f00000 ################################################################
10162 22:13:45.191041
10163 22:13:45.827557 00f80000 ################################################################
10164 22:13:45.828077
10165 22:13:46.426622 01000000 ################################################################
10166 22:13:46.426774
10167 22:13:46.970057 01080000 ################################################################
10168 22:13:46.970203
10169 22:13:47.505045 01100000 ################################################################
10170 22:13:47.505200
10171 22:13:48.115833 01180000 ################################################################
10172 22:13:48.116417
10173 22:13:48.664934 01200000 ################################################################
10174 22:13:48.665075
10175 22:13:49.229454 01280000 ################################################################
10176 22:13:49.229593
10177 22:13:49.876636 01300000 ################################################################
10178 22:13:49.877156
10179 22:13:50.448575 01380000 ################################################################
10180 22:13:50.449097
10181 22:13:51.135300 01400000 ################################################################
10182 22:13:51.135810
10183 22:13:51.807588 01480000 ################################################################
10184 22:13:51.808064
10185 22:13:52.493479 01500000 ################################################################
10186 22:13:52.494025
10187 22:13:53.192223 01580000 ################################################################
10188 22:13:53.192766
10189 22:13:53.805407 01600000 ################################################################
10190 22:13:53.805542
10191 22:13:54.489334 01680000 ################################################################
10192 22:13:54.489865
10193 22:13:55.176897 01700000 ################################################################
10194 22:13:55.177436
10195 22:13:55.787950 01780000 ################################################################
10196 22:13:55.788118
10197 22:13:56.372669 01800000 ################################################################
10198 22:13:56.372822
10199 22:13:56.967827 01880000 ################################################################
10200 22:13:56.968013
10201 22:13:57.551846 01900000 ################################################################
10202 22:13:57.552019
10203 22:13:58.145466 01980000 ################################################################
10204 22:13:58.145620
10205 22:13:58.742533 01a00000 ################################################################
10206 22:13:58.742688
10207 22:13:59.307772 01a80000 ################################################################
10208 22:13:59.307928
10209 22:13:59.901284 01b00000 ################################################################
10210 22:13:59.901811
10211 22:14:00.511610 01b80000 ################################################################
10212 22:14:00.511761
10213 22:14:01.117304 01c00000 ################################################################
10214 22:14:01.117862
10215 22:14:01.715745 01c80000 ################################################################
10216 22:14:01.715950
10217 22:14:02.304883 01d00000 ################################################################
10218 22:14:02.305039
10219 22:14:02.866472 01d80000 ################################################################
10220 22:14:02.866610
10221 22:14:03.458277 01e00000 ################################################################
10222 22:14:03.458790
10223 22:14:04.139102 01e80000 ################################################################
10224 22:14:04.139604
10225 22:14:04.850307 01f00000 ################################################################
10226 22:14:04.850830
10227 22:14:05.554941 01f80000 ################################################################
10228 22:14:05.555113
10229 22:14:06.138337 02000000 ################################################################
10230 22:14:06.138615
10231 22:14:06.815650 02080000 ################################################################
10232 22:14:06.816283
10233 22:14:07.539280 02100000 ################################################################
10234 22:14:07.539838
10235 22:14:08.244618 02180000 ################################################################
10236 22:14:08.245145
10237 22:14:08.959665 02200000 ################################################################
10238 22:14:08.960290
10239 22:14:09.671095 02280000 ################################################################
10240 22:14:09.671768
10241 22:14:10.381635 02300000 ################################################################
10242 22:14:10.382189
10243 22:14:11.077032 02380000 ################################################################
10244 22:14:11.077591
10245 22:14:11.774958 02400000 ################################################################
10246 22:14:11.775530
10247 22:14:12.482880 02480000 ################################################################
10248 22:14:12.483447
10249 22:14:13.183339 02500000 ################################################################
10250 22:14:13.183867
10251 22:14:13.898901 02580000 ################################################################
10252 22:14:13.899423
10253 22:14:14.612176 02600000 ################################################################
10254 22:14:14.612689
10255 22:14:15.343379 02680000 ################################################################
10256 22:14:15.344015
10257 22:14:16.053240 02700000 ################################################################
10258 22:14:16.053812
10259 22:14:16.789512 02780000 ################################################################
10260 22:14:16.790096
10261 22:14:17.493735 02800000 ################################################################
10262 22:14:17.494252
10263 22:14:18.225911 02880000 ################################################################
10264 22:14:18.226495
10265 22:14:18.944177 02900000 ################################################################
10266 22:14:18.944804
10267 22:14:19.665088 02980000 ################################################################
10268 22:14:19.665672
10269 22:14:20.395239 02a00000 ################################################################
10270 22:14:20.395762
10271 22:14:21.120422 02a80000 ################################################################
10272 22:14:21.121047
10273 22:14:21.834835 02b00000 ################################################################
10274 22:14:21.835355
10275 22:14:22.554418 02b80000 ################################################################
10276 22:14:22.554958
10277 22:14:23.276449 02c00000 ################################################################
10278 22:14:23.276967
10279 22:14:24.006909 02c80000 ################################################################
10280 22:14:24.007507
10281 22:14:24.737128 02d00000 ################################################################
10282 22:14:24.737719
10283 22:14:25.470159 02d80000 ################################################################
10284 22:14:25.470811
10285 22:14:26.219326 02e00000 ################################################################
10286 22:14:26.219855
10287 22:14:26.939761 02e80000 ################################################################
10288 22:14:26.940389
10289 22:14:27.661963 02f00000 ################################################################
10290 22:14:27.662505
10291 22:14:28.339231 02f80000 ################################################################
10292 22:14:28.339751
10293 22:14:29.055789 03000000 ################################################################
10294 22:14:29.056337
10295 22:14:29.754800 03080000 ################################################################
10296 22:14:29.754938
10297 22:14:30.348761 03100000 ################################################################
10298 22:14:30.348916
10299 22:14:30.939258 03180000 ################################################################
10300 22:14:30.939409
10301 22:14:31.533294 03200000 ################################################################
10302 22:14:31.533448
10303 22:14:32.127359 03280000 ################################################################
10304 22:14:32.127510
10305 22:14:32.674085 03300000 ################################################################
10306 22:14:32.674235
10307 22:14:33.209949 03380000 ################################################################
10308 22:14:33.210104
10309 22:14:33.760062 03400000 ################################################################
10310 22:14:33.760217
10311 22:14:34.310107 03480000 ################################################################
10312 22:14:34.310260
10313 22:14:34.859945 03500000 ################################################################
10314 22:14:34.860120
10315 22:14:35.402817 03580000 ################################################################
10316 22:14:35.402971
10317 22:14:35.929139 03600000 ################################################################
10318 22:14:35.929293
10319 22:14:36.299109 03680000 ############################################# done.
10320 22:14:36.299260
10321 22:14:36.303255 The bootfile was 57510234 bytes long.
10322 22:14:36.303341
10323 22:14:36.305781 Sending tftp read request... done.
10324 22:14:36.305867
10325 22:14:36.309384 Waiting for the transfer...
10326 22:14:36.309469
10327 22:14:36.312835 00000000 # done.
10328 22:14:36.312921
10329 22:14:36.319580 Command line loaded dynamically from TFTP file: 10583887/tftp-deploy-bh6vuykx/kernel/cmdline
10330 22:14:36.319664
10331 22:14:36.329467 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10332 22:14:36.329554
10333 22:14:36.332152 Loading FIT.
10334 22:14:36.332235
10335 22:14:36.336169 Image ramdisk-1 has 47379547 bytes.
10336 22:14:36.336252
10337 22:14:36.338831 Image fdt-1 has 46924 bytes.
10338 22:14:36.338915
10339 22:14:36.338981 Image kernel-1 has 10081729 bytes.
10340 22:14:36.339044
10341 22:14:36.348844 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10342 22:14:36.348934
10343 22:14:36.366011 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10344 22:14:36.366105
10345 22:14:36.372614 Choosing best match conf-1 for compat google,spherion-rev2.
10346 22:14:36.375935
10347 22:14:36.380462 Connected to device vid:did:rid of 1ae0:0028:00
10348 22:14:36.387616
10349 22:14:36.390995 tpm_get_response: command 0x17b, return code 0x0
10350 22:14:36.391079
10351 22:14:36.394555 ec_init: CrosEC protocol v3 supported (256, 248)
10352 22:14:36.398473
10353 22:14:36.401767 tpm_cleanup: add release locality here.
10354 22:14:36.401852
10355 22:14:36.401919 Shutting down all USB controllers.
10356 22:14:36.405631
10357 22:14:36.405715 Removing current net device
10358 22:14:36.405782
10359 22:14:36.411824 Exiting depthcharge with code 4 at timestamp: 114473605
10360 22:14:36.411908
10361 22:14:36.415344 LZMA decompressing kernel-1 to 0x821a6718
10362 22:14:36.415428
10363 22:14:36.418233 LZMA decompressing kernel-1 to 0x40000000
10364 22:14:37.685892
10365 22:14:37.686048 jumping to kernel
10366 22:14:37.686547 end: 2.2.4 bootloader-commands (duration 00:01:26) [common]
10367 22:14:37.686661 start: 2.2.5 auto-login-action (timeout 00:02:59) [common]
10368 22:14:37.686752 Setting prompt string to ['Linux version [0-9]']
10369 22:14:37.686819 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10370 22:14:37.686887 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10371 22:14:37.767484
10372 22:14:37.771191 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10373 22:14:37.774588 start: 2.2.5.1 login-action (timeout 00:02:59) [common]
10374 22:14:37.774683 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10375 22:14:37.774772 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10376 22:14:37.774853 Using line separator: #'\n'#
10377 22:14:37.774916 No login prompt set.
10378 22:14:37.774977 Parsing kernel messages
10379 22:14:37.775034 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10380 22:14:37.775141 [login-action] Waiting for messages, (timeout 00:02:59)
10381 22:14:37.794115 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j1606555-arm64-gcc-10-defconfig-arm64-chromebook-vtq55) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sun Jun 4 21:56:05 UTC 2023
10382 22:14:37.797912 [ 0.000000] random: crng init done
10383 22:14:37.801069 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10384 22:14:37.803867 [ 0.000000] efi: UEFI not found.
10385 22:14:37.813620 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10386 22:14:37.820866 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10387 22:14:37.830559 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10388 22:14:37.840664 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10389 22:14:37.846860 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10390 22:14:37.850171 [ 0.000000] printk: bootconsole [mtk8250] enabled
10391 22:14:37.859243 [ 0.000000] NUMA: No NUMA configuration found
10392 22:14:37.865139 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10393 22:14:37.871927 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcda00-0x23efcffff]
10394 22:14:37.872055 [ 0.000000] Zone ranges:
10395 22:14:37.878347 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10396 22:14:37.882652 [ 0.000000] DMA32 empty
10397 22:14:37.888587 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10398 22:14:37.891595 [ 0.000000] Movable zone start for each node
10399 22:14:37.894946 [ 0.000000] Early memory node ranges
10400 22:14:37.902079 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10401 22:14:37.908450 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10402 22:14:37.914940 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10403 22:14:37.921786 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10404 22:14:37.928389 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10405 22:14:37.935347 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10406 22:14:37.991216 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10407 22:14:37.997600 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10408 22:14:38.004983 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10409 22:14:38.007578 [ 0.000000] psci: probing for conduit method from DT.
10410 22:14:38.015053 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10411 22:14:38.017858 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10412 22:14:38.024733 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10413 22:14:38.027919 [ 0.000000] psci: SMC Calling Convention v1.2
10414 22:14:38.034366 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10415 22:14:38.038003 [ 0.000000] Detected VIPT I-cache on CPU0
10416 22:14:38.044580 [ 0.000000] CPU features: detected: GIC system register CPU interface
10417 22:14:38.051259 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10418 22:14:38.057384 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10419 22:14:38.064311 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10420 22:14:38.073769 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10421 22:14:38.080647 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10422 22:14:38.084411 [ 0.000000] alternatives: applying boot alternatives
10423 22:14:38.090686 [ 0.000000] Fallback order for Node 0: 0
10424 22:14:38.096923 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10425 22:14:38.100477 [ 0.000000] Policy zone: Normal
10426 22:14:38.110743 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10427 22:14:38.120945 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10428 22:14:38.133053 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10429 22:14:38.143352 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10430 22:14:38.149754 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10431 22:14:38.153216 <6>[ 0.000000] software IO TLB: area num 8.
10432 22:14:38.210081 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10433 22:14:38.359038 <6>[ 0.000000] Memory: 7926664K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 426104K reserved, 32768K cma-reserved)
10434 22:14:38.365274 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10435 22:14:38.372217 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10436 22:14:38.375371 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10437 22:14:38.381851 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10438 22:14:38.388810 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10439 22:14:38.391855 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10440 22:14:38.401855 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10441 22:14:38.408710 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10442 22:14:38.415522 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10443 22:14:38.421846 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10444 22:14:38.425271 <6>[ 0.000000] GICv3: 608 SPIs implemented
10445 22:14:38.428423 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10446 22:14:38.434883 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10447 22:14:38.438652 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10448 22:14:38.445114 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10449 22:14:38.458018 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10450 22:14:38.468173 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10451 22:14:38.478272 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10452 22:14:38.485982 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10453 22:14:38.498762 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10454 22:14:38.505015 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10455 22:14:38.512005 <6>[ 0.009228] Console: colour dummy device 80x25
10456 22:14:38.521603 <6>[ 0.013959] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10457 22:14:38.528544 <6>[ 0.024401] pid_max: default: 32768 minimum: 301
10458 22:14:38.531778 <6>[ 0.029274] LSM: Security Framework initializing
10459 22:14:38.538243 <6>[ 0.034214] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10460 22:14:38.548676 <6>[ 0.042027] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10461 22:14:38.557816 <6>[ 0.051455] cblist_init_generic: Setting adjustable number of callback queues.
10462 22:14:38.562027 <6>[ 0.058957] cblist_init_generic: Setting shift to 3 and lim to 1.
10463 22:14:38.567828 <6>[ 0.065296] cblist_init_generic: Setting shift to 3 and lim to 1.
10464 22:14:38.574863 <6>[ 0.071703] rcu: Hierarchical SRCU implementation.
10465 22:14:38.581067 <6>[ 0.076716] rcu: Max phase no-delay instances is 1000.
10466 22:14:38.587475 <6>[ 0.083737] EFI services will not be available.
10467 22:14:38.591256 <6>[ 0.088710] smp: Bringing up secondary CPUs ...
10468 22:14:38.599226 <6>[ 0.093761] Detected VIPT I-cache on CPU1
10469 22:14:38.605843 <6>[ 0.093835] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10470 22:14:38.612023 <6>[ 0.093864] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10471 22:14:38.615704 <6>[ 0.094199] Detected VIPT I-cache on CPU2
10472 22:14:38.621900 <6>[ 0.094249] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10473 22:14:38.632212 <6>[ 0.094266] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10474 22:14:38.634906 <6>[ 0.094525] Detected VIPT I-cache on CPU3
10475 22:14:38.641836 <6>[ 0.094571] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10476 22:14:38.648328 <6>[ 0.094585] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10477 22:14:38.651612 <6>[ 0.094894] CPU features: detected: Spectre-v4
10478 22:14:38.659175 <6>[ 0.094900] CPU features: detected: Spectre-BHB
10479 22:14:38.661575 <6>[ 0.094906] Detected PIPT I-cache on CPU4
10480 22:14:38.668436 <6>[ 0.094963] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10481 22:14:38.675051 <6>[ 0.094980] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10482 22:14:38.681404 <6>[ 0.095270] Detected PIPT I-cache on CPU5
10483 22:14:38.688758 <6>[ 0.095333] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10484 22:14:38.694588 <6>[ 0.095349] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10485 22:14:38.698030 <6>[ 0.095632] Detected PIPT I-cache on CPU6
10486 22:14:38.705183 <6>[ 0.095696] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10487 22:14:38.711089 <6>[ 0.095712] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10488 22:14:38.717944 <6>[ 0.096009] Detected PIPT I-cache on CPU7
10489 22:14:38.724451 <6>[ 0.096074] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10490 22:14:38.731483 <6>[ 0.096090] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10491 22:14:38.734903 <6>[ 0.096137] smp: Brought up 1 node, 8 CPUs
10492 22:14:38.741617 <6>[ 0.237404] SMP: Total of 8 processors activated.
10493 22:14:38.744908 <6>[ 0.242325] CPU features: detected: 32-bit EL0 Support
10494 22:14:38.754661 <6>[ 0.247721] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10495 22:14:38.761399 <6>[ 0.256521] CPU features: detected: Common not Private translations
10496 22:14:38.764605 <6>[ 0.262996] CPU features: detected: CRC32 instructions
10497 22:14:38.771211 <6>[ 0.268347] CPU features: detected: RCpc load-acquire (LDAPR)
10498 22:14:38.778662 <6>[ 0.274307] CPU features: detected: LSE atomic instructions
10499 22:14:38.784961 <6>[ 0.280124] CPU features: detected: Privileged Access Never
10500 22:14:38.787676 <6>[ 0.285903] CPU features: detected: RAS Extension Support
10501 22:14:38.797684 <6>[ 0.291546] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10502 22:14:38.801783 <6>[ 0.298770] CPU: All CPU(s) started at EL2
10503 22:14:38.807771 <6>[ 0.303113] alternatives: applying system-wide alternatives
10504 22:14:38.816246 <6>[ 0.313820] devtmpfs: initialized
10505 22:14:38.831791 <6>[ 0.322564] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10506 22:14:38.838354 <6>[ 0.332526] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10507 22:14:38.844993 <6>[ 0.340752] pinctrl core: initialized pinctrl subsystem
10508 22:14:38.848405 <6>[ 0.347402] DMI not present or invalid.
10509 22:14:38.855069 <6>[ 0.351807] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10510 22:14:38.864775 <6>[ 0.358678] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10511 22:14:38.871682 <6>[ 0.366260] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10512 22:14:38.881677 <6>[ 0.374488] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10513 22:14:38.884902 <6>[ 0.382731] audit: initializing netlink subsys (disabled)
10514 22:14:38.894336 <5>[ 0.388424] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10515 22:14:38.900855 <6>[ 0.389118] thermal_sys: Registered thermal governor 'step_wise'
10516 22:14:38.907680 <6>[ 0.396390] thermal_sys: Registered thermal governor 'power_allocator'
10517 22:14:38.910946 <6>[ 0.402644] cpuidle: using governor menu
10518 22:14:38.917625 <6>[ 0.413607] NET: Registered PF_QIPCRTR protocol family
10519 22:14:38.924798 <6>[ 0.419087] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10520 22:14:38.930612 <6>[ 0.426191] ASID allocator initialised with 32768 entries
10521 22:14:38.934386 <6>[ 0.432744] Serial: AMBA PL011 UART driver
10522 22:14:38.944051 <4>[ 0.441370] Trying to register duplicate clock ID: 134
10523 22:14:38.997616 <6>[ 0.498616] KASLR enabled
10524 22:14:39.012655 <6>[ 0.506286] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10525 22:14:39.018684 <6>[ 0.513300] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10526 22:14:39.025877 <6>[ 0.519793] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10527 22:14:39.031777 <6>[ 0.526797] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10528 22:14:39.038689 <6>[ 0.533283] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10529 22:14:39.045136 <6>[ 0.540286] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10530 22:14:39.051815 <6>[ 0.546776] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10531 22:14:39.058830 <6>[ 0.553782] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10532 22:14:39.061752 <6>[ 0.561258] ACPI: Interpreter disabled.
10533 22:14:39.070700 <6>[ 0.567685] iommu: Default domain type: Translated
10534 22:14:39.077017 <6>[ 0.572800] iommu: DMA domain TLB invalidation policy: strict mode
10535 22:14:39.080407 <5>[ 0.579462] SCSI subsystem initialized
10536 22:14:39.086517 <6>[ 0.583699] usbcore: registered new interface driver usbfs
10537 22:14:39.093483 <6>[ 0.589429] usbcore: registered new interface driver hub
10538 22:14:39.096412 <6>[ 0.594983] usbcore: registered new device driver usb
10539 22:14:39.103632 <6>[ 0.601087] pps_core: LinuxPPS API ver. 1 registered
10540 22:14:39.113914 <6>[ 0.606280] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10541 22:14:39.117439 <6>[ 0.615624] PTP clock support registered
10542 22:14:39.120429 <6>[ 0.619865] EDAC MC: Ver: 3.0.0
10543 22:14:39.127596 <6>[ 0.625061] FPGA manager framework
10544 22:14:39.130651 <6>[ 0.628740] Advanced Linux Sound Architecture Driver Initialized.
10545 22:14:39.135004 <6>[ 0.635509] vgaarb: loaded
10546 22:14:39.141707 <6>[ 0.638660] clocksource: Switched to clocksource arch_sys_counter
10547 22:14:39.147790 <5>[ 0.645113] VFS: Disk quotas dquot_6.6.0
10548 22:14:39.154818 <6>[ 0.649300] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10549 22:14:39.157743 <6>[ 0.656476] pnp: PnP ACPI: disabled
10550 22:14:39.166011 <6>[ 0.663136] NET: Registered PF_INET protocol family
10551 22:14:39.175584 <6>[ 0.668724] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10552 22:14:39.186524 <6>[ 0.680996] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10553 22:14:39.196546 <6>[ 0.689808] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10554 22:14:39.203413 <6>[ 0.697778] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10555 22:14:39.209997 <6>[ 0.706434] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10556 22:14:39.221991 <6>[ 0.716180] TCP: Hash tables configured (established 65536 bind 65536)
10557 22:14:39.228676 <6>[ 0.723038] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10558 22:14:39.235371 <6>[ 0.730238] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10559 22:14:39.242767 <6>[ 0.737939] NET: Registered PF_UNIX/PF_LOCAL protocol family
10560 22:14:39.248211 <6>[ 0.744102] RPC: Registered named UNIX socket transport module.
10561 22:14:39.251896 <6>[ 0.750256] RPC: Registered udp transport module.
10562 22:14:39.259170 <6>[ 0.755187] RPC: Registered tcp transport module.
10563 22:14:39.264750 <6>[ 0.760119] RPC: Registered tcp NFSv4.1 backchannel transport module.
10564 22:14:39.268466 <6>[ 0.766787] PCI: CLS 0 bytes, default 64
10565 22:14:39.271473 <6>[ 0.771173] Unpacking initramfs...
10566 22:14:39.288774 <6>[ 0.783248] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10567 22:14:39.298788 <6>[ 0.791916] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10568 22:14:39.302246 <6>[ 0.800751] kvm [1]: IPA Size Limit: 40 bits
10569 22:14:39.308992 <6>[ 0.805279] kvm [1]: GICv3: no GICV resource entry
10570 22:14:39.311873 <6>[ 0.810303] kvm [1]: disabling GICv2 emulation
10571 22:14:39.318636 <6>[ 0.814989] kvm [1]: GIC system register CPU interface enabled
10572 22:14:39.322400 <6>[ 0.821156] kvm [1]: vgic interrupt IRQ18
10573 22:14:39.329373 <6>[ 0.827046] kvm [1]: VHE mode initialized successfully
10574 22:14:39.336321 <5>[ 0.833462] Initialise system trusted keyrings
10575 22:14:39.342966 <6>[ 0.838259] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10576 22:14:39.350875 <6>[ 0.848458] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10577 22:14:39.357632 <5>[ 0.854892] NFS: Registering the id_resolver key type
10578 22:14:39.360910 <5>[ 0.860193] Key type id_resolver registered
10579 22:14:39.367855 <5>[ 0.864609] Key type id_legacy registered
10580 22:14:39.374025 <6>[ 0.868891] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10581 22:14:39.381157 <6>[ 0.875815] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10582 22:14:39.387234 <6>[ 0.883551] 9p: Installing v9fs 9p2000 file system support
10583 22:14:39.424321 <5>[ 0.922081] Key type asymmetric registered
10584 22:14:39.427738 <5>[ 0.926411] Asymmetric key parser 'x509' registered
10585 22:14:39.437550 <6>[ 0.931556] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10586 22:14:39.441492 <6>[ 0.939185] io scheduler mq-deadline registered
10587 22:14:39.444940 <6>[ 0.943951] io scheduler kyber registered
10588 22:14:39.463441 <6>[ 0.960796] EINJ: ACPI disabled.
10589 22:14:39.495207 <4>[ 0.986196] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10590 22:14:39.506174 <4>[ 0.996839] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10591 22:14:39.519697 <6>[ 1.017237] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10592 22:14:39.527286 <6>[ 1.025189] printk: console [ttyS0] disabled
10593 22:14:39.556246 <6>[ 1.049837] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10594 22:14:39.562102 <6>[ 1.059310] printk: console [ttyS0] enabled
10595 22:14:39.565628 <6>[ 1.059310] printk: console [ttyS0] enabled
10596 22:14:39.571964 <6>[ 1.068206] printk: bootconsole [mtk8250] disabled
10597 22:14:39.575643 <6>[ 1.068206] printk: bootconsole [mtk8250] disabled
10598 22:14:39.582129 <6>[ 1.079478] SuperH (H)SCI(F) driver initialized
10599 22:14:39.585262 <6>[ 1.084733] msm_serial: driver initialized
10600 22:14:39.599823 <6>[ 1.093640] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10601 22:14:39.609191 <6>[ 1.102187] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10602 22:14:39.616150 <6>[ 1.110729] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10603 22:14:39.625789 <6>[ 1.119358] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10604 22:14:39.635918 <6>[ 1.128063] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10605 22:14:39.642567 <6>[ 1.136783] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10606 22:14:39.652399 <6>[ 1.145324] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10607 22:14:39.658988 <6>[ 1.154128] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10608 22:14:39.668723 <6>[ 1.162673] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10609 22:14:39.680484 <6>[ 1.178053] loop: module loaded
10610 22:14:39.687603 <6>[ 1.184036] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10611 22:14:39.709849 <4>[ 1.207448] mtk-pmic-keys: Failed to locate of_node [id: -1]
10612 22:14:39.716994 <6>[ 1.214281] megasas: 07.719.03.00-rc1
10613 22:14:39.726542 <6>[ 1.224266] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10614 22:14:39.733967 <6>[ 1.226201] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10615 22:14:39.749250 <6>[ 1.246038] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10616 22:14:39.809338 <6>[ 1.300382] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10617 22:14:41.295286 <6>[ 2.792582] Freeing initrd memory: 46268K
10618 22:14:41.305839 <6>[ 2.802911] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10619 22:14:41.316308 <6>[ 2.813888] tun: Universal TUN/TAP device driver, 1.6
10620 22:14:41.319293 <6>[ 2.819950] thunder_xcv, ver 1.0
10621 22:14:41.323173 <6>[ 2.823456] thunder_bgx, ver 1.0
10622 22:14:41.326528 <6>[ 2.826949] nicpf, ver 1.0
10623 22:14:41.337186 <6>[ 2.830973] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10624 22:14:41.339614 <6>[ 2.838447] hns3: Copyright (c) 2017 Huawei Corporation.
10625 22:14:41.346537 <6>[ 2.844036] hclge is initializing
10626 22:14:41.349731 <6>[ 2.847611] e1000: Intel(R) PRO/1000 Network Driver
10627 22:14:41.357083 <6>[ 2.852739] e1000: Copyright (c) 1999-2006 Intel Corporation.
10628 22:14:41.359943 <6>[ 2.858754] e1000e: Intel(R) PRO/1000 Network Driver
10629 22:14:41.366551 <6>[ 2.863970] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10630 22:14:41.373235 <6>[ 2.870155] igb: Intel(R) Gigabit Ethernet Network Driver
10631 22:14:41.379781 <6>[ 2.875805] igb: Copyright (c) 2007-2014 Intel Corporation.
10632 22:14:41.386237 <6>[ 2.881640] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10633 22:14:41.392726 <6>[ 2.888158] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10634 22:14:41.395967 <6>[ 2.894620] sky2: driver version 1.30
10635 22:14:41.402771 <6>[ 2.899612] VFIO - User Level meta-driver version: 0.3
10636 22:14:41.409738 <6>[ 2.907793] usbcore: registered new interface driver usb-storage
10637 22:14:41.416989 <6>[ 2.914241] usbcore: registered new device driver onboard-usb-hub
10638 22:14:41.425842 <6>[ 2.923300] mt6397-rtc mt6359-rtc: registered as rtc0
10639 22:14:41.436094 <6>[ 2.928765] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-04T22:14:54 UTC (1685916894)
10640 22:14:41.438940 <6>[ 2.938326] i2c_dev: i2c /dev entries driver
10641 22:14:41.455944 <6>[ 2.950117] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10642 22:14:41.462677 <6>[ 2.960410] sdhci: Secure Digital Host Controller Interface driver
10643 22:14:41.469277 <6>[ 2.966849] sdhci: Copyright(c) Pierre Ossman
10644 22:14:41.475910 <6>[ 2.972246] Synopsys Designware Multimedia Card Interface Driver
10645 22:14:41.479171 <6>[ 2.978838] mmc0: CQHCI version 5.10
10646 22:14:41.485908 <6>[ 2.979404] sdhci-pltfm: SDHCI platform and OF driver helper
10647 22:14:41.493376 <6>[ 2.990715] ledtrig-cpu: registered to indicate activity on CPUs
10648 22:14:41.504262 <6>[ 2.998115] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10649 22:14:41.507071 <6>[ 3.005508] usbcore: registered new interface driver usbhid
10650 22:14:41.514015 <6>[ 3.011338] usbhid: USB HID core driver
10651 22:14:41.520594 <6>[ 3.015575] spi_master spi0: will run message pump with realtime priority
10652 22:14:41.564337 <6>[ 3.055597] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10653 22:14:41.584109 <6>[ 3.070972] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10654 22:14:41.587145 <6>[ 3.084559] mmc0: Command Queue Engine enabled
10655 22:14:41.594451 <6>[ 3.086122] cros-ec-spi spi0.0: Chrome EC device registered
10656 22:14:41.601067 <6>[ 3.089314] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10657 22:14:41.604246 <6>[ 3.102385] mmcblk0: mmc0:0001 DA4128 116 GiB
10658 22:14:41.619600 <6>[ 3.113418] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10659 22:14:41.626140 <6>[ 3.113948] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10660 22:14:41.632315 <6>[ 3.124938] NET: Registered PF_PACKET protocol family
10661 22:14:41.635800 <6>[ 3.129543] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10662 22:14:41.642835 <6>[ 3.134110] 9pnet: Installing 9P2000 support
10663 22:14:41.645821 <6>[ 3.139817] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10664 22:14:41.652023 <5>[ 3.143801] Key type dns_resolver registered
10665 22:14:41.659628 <6>[ 3.149490] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10666 22:14:41.662588 <6>[ 3.154084] registered taskstats version 1
10667 22:14:41.665829 <5>[ 3.164404] Loading compiled-in X.509 certificates
10668 22:14:41.702325 <4>[ 3.192440] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10669 22:14:41.712026 <4>[ 3.203108] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10670 22:14:41.722001 <3>[ 3.215833] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10671 22:14:41.734017 <6>[ 3.231430] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10672 22:14:41.740898 <6>[ 3.238206] xhci-mtk 11200000.usb: xHCI Host Controller
10673 22:14:41.747425 <6>[ 3.243705] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10674 22:14:41.758280 <6>[ 3.251645] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10675 22:14:41.764188 <6>[ 3.261092] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10676 22:14:41.771590 <6>[ 3.267198] xhci-mtk 11200000.usb: xHCI Host Controller
10677 22:14:41.777450 <6>[ 3.272685] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10678 22:14:41.784128 <6>[ 3.280338] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10679 22:14:41.790904 <6>[ 3.288231] hub 1-0:1.0: USB hub found
10680 22:14:41.794682 <6>[ 3.292288] hub 1-0:1.0: 1 port detected
10681 22:14:41.803989 <6>[ 3.296632] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10682 22:14:41.807403 <6>[ 3.305421] hub 2-0:1.0: USB hub found
10683 22:14:41.810571 <6>[ 3.309469] hub 2-0:1.0: 1 port detected
10684 22:14:41.819183 <6>[ 3.316815] mtk-msdc 11f70000.mmc: Got CD GPIO
10685 22:14:41.838102 <6>[ 3.332101] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10686 22:14:41.844784 <6>[ 3.340135] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10687 22:14:41.854497 <4>[ 3.348107] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10688 22:14:41.864858 <6>[ 3.357769] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10689 22:14:41.871547 <6>[ 3.365852] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10690 22:14:41.878667 <6>[ 3.373870] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10691 22:14:41.887827 <6>[ 3.381790] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10692 22:14:41.894325 <6>[ 3.389612] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10693 22:14:41.904442 <6>[ 3.397434] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10694 22:14:41.914673 <6>[ 3.408109] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10695 22:14:41.921344 <6>[ 3.416485] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10696 22:14:41.930967 <6>[ 3.424829] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10697 22:14:41.940856 <6>[ 3.433172] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10698 22:14:41.947442 <6>[ 3.441515] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10699 22:14:41.956882 <6>[ 3.449857] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10700 22:14:41.963775 <6>[ 3.458199] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10701 22:14:41.974429 <6>[ 3.466542] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10702 22:14:41.980040 <6>[ 3.474886] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10703 22:14:41.990348 <6>[ 3.483230] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10704 22:14:41.996512 <6>[ 3.491580] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10705 22:14:42.006841 <6>[ 3.499924] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10706 22:14:42.013650 <6>[ 3.508273] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10707 22:14:42.023490 <6>[ 3.516619] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10708 22:14:42.029699 <6>[ 3.524967] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10709 22:14:42.036223 <6>[ 3.533898] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10710 22:14:42.044132 <6>[ 3.541392] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10711 22:14:42.051621 <6>[ 3.548508] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10712 22:14:42.061422 <6>[ 3.555652] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10713 22:14:42.069019 <6>[ 3.563000] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10714 22:14:42.078312 <6>[ 3.569913] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10715 22:14:42.084854 <6>[ 3.579057] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10716 22:14:42.094340 <6>[ 3.588184] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10717 22:14:42.104711 <6>[ 3.597485] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10718 22:14:42.114243 <6>[ 3.606960] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10719 22:14:42.124694 <6>[ 3.616433] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10720 22:14:42.130712 <6>[ 3.625561] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10721 22:14:42.140574 <6>[ 3.635034] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10722 22:14:42.150650 <6>[ 3.644161] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10723 22:14:42.160618 <6>[ 3.653462] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10724 22:14:42.170199 <6>[ 3.663629] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10725 22:14:42.181234 <6>[ 3.675524] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10726 22:14:42.204290 <6>[ 3.699089] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10727 22:14:42.231777 <6>[ 3.728959] hub 2-1:1.0: USB hub found
10728 22:14:42.234865 <6>[ 3.733336] hub 2-1:1.0: 3 ports detected
10729 22:14:42.356189 <6>[ 3.850866] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10730 22:14:42.510917 <6>[ 4.008122] hub 1-1:1.0: USB hub found
10731 22:14:42.513942 <6>[ 4.012606] hub 1-1:1.0: 4 ports detected
10732 22:14:42.588424 <6>[ 4.083182] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10733 22:14:42.836066 <6>[ 4.330930] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10734 22:14:42.970027 <6>[ 4.467227] hub 1-1.4:1.0: USB hub found
10735 22:14:42.972548 <6>[ 4.471900] hub 1-1.4:1.0: 2 ports detected
10736 22:14:43.268357 <6>[ 4.762931] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10737 22:14:43.460496 <6>[ 4.954930] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10738 22:14:54.477246 <6>[ 15.979477] ALSA device list:
10739 22:14:54.483665 <6>[ 15.982734] No soundcards found.
10740 22:14:54.495992 <6>[ 15.995187] Freeing unused kernel memory: 8384K
10741 22:14:54.499806 <6>[ 16.000119] Run /init as init process
10742 22:14:54.529336 <6>[ 16.028288] NET: Registered PF_INET6 protocol family
10743 22:14:54.535685 <6>[ 16.034750] Segment Routing with IPv6
10744 22:14:54.538920 <6>[ 16.038684] In-situ OAM (IOAM) with IPv6
10745 22:14:54.573542 <30>[ 16.052916] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10746 22:14:54.576757 <30>[ 16.076659] systemd[1]: Detected architecture arm64.
10747 22:14:54.576874
10748 22:14:54.583080 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10749 22:14:54.583203
10750 22:14:54.596351 <30>[ 16.095095] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10751 22:14:54.751716 <30>[ 16.247249] systemd[1]: Queued start job for default target Graphical Interface.
10752 22:14:54.785144 <30>[ 16.284240] systemd[1]: Created slice system-getty.slice.
10753 22:14:54.791218 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10754 22:14:54.808577 <30>[ 16.307515] systemd[1]: Created slice system-modprobe.slice.
10755 22:14:54.814944 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10756 22:14:54.832481 <30>[ 16.331484] systemd[1]: Created slice system-serial\x2dgetty.slice.
10757 22:14:54.841813 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10758 22:14:54.856451 <30>[ 16.355993] systemd[1]: Created slice User and Session Slice.
10759 22:14:54.863377 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10760 22:14:54.883436 <30>[ 16.379484] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10761 22:14:54.893685 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10762 22:14:54.910833 <30>[ 16.407080] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10763 22:14:54.917423 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10764 22:14:54.938168 <30>[ 16.431015] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10765 22:14:54.944915 <30>[ 16.443049] systemd[1]: Reached target Local Encrypted Volumes.
10766 22:14:54.951299 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10767 22:14:54.967701 <30>[ 16.467023] systemd[1]: Reached target Paths.
10768 22:14:54.970801 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10769 22:14:54.987437 <30>[ 16.486963] systemd[1]: Reached target Remote File Systems.
10770 22:14:54.993967 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10771 22:14:55.011832 <30>[ 16.511207] systemd[1]: Reached target Slices.
10772 22:14:55.018866 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10773 22:14:55.032021 <30>[ 16.530985] systemd[1]: Reached target Swap.
10774 22:14:55.034799 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10775 22:14:55.055475 <30>[ 16.551288] systemd[1]: Listening on initctl Compatibility Named Pipe.
10776 22:14:55.062108 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10777 22:14:55.068631 <30>[ 16.566054] systemd[1]: Listening on Journal Audit Socket.
10778 22:14:55.075252 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10779 22:14:55.087892 <30>[ 16.587227] systemd[1]: Listening on Journal Socket (/dev/log).
10780 22:14:55.094647 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10781 22:14:55.111731 <30>[ 16.611235] systemd[1]: Listening on Journal Socket.
10782 22:14:55.118833 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10783 22:14:55.135310 <30>[ 16.631285] systemd[1]: Listening on Network Service Netlink Socket.
10784 22:14:55.141767 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10785 22:14:55.156668 <30>[ 16.655710] systemd[1]: Listening on udev Control Socket.
10786 22:14:55.162857 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10787 22:14:55.179950 <30>[ 16.679642] systemd[1]: Listening on udev Kernel Socket.
10788 22:14:55.186738 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10789 22:14:55.223594 <30>[ 16.723168] systemd[1]: Mounting Huge Pages File System...
10790 22:14:55.230589 Mounting [0;1;39mHuge Pages File System[0m...
10791 22:14:55.245279 <30>[ 16.744900] systemd[1]: Mounting POSIX Message Queue File System...
10792 22:14:55.252231 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10793 22:14:55.269776 <30>[ 16.768898] systemd[1]: Mounting Kernel Debug File System...
10794 22:14:55.275860 Mounting [0;1;39mKernel Debug File System[0m...
10795 22:14:55.294751 <30>[ 16.791134] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10796 22:14:55.305760 <30>[ 16.801925] systemd[1]: Starting Create list of static device nodes for the current kernel...
10797 22:14:55.312418 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10798 22:14:55.329528 <30>[ 16.829094] systemd[1]: Starting Load Kernel Module configfs...
10799 22:14:55.336239 Starting [0;1;39mLoad Kernel Module configfs[0m...
10800 22:14:55.353478 <30>[ 16.853103] systemd[1]: Starting Load Kernel Module drm...
10801 22:14:55.360575 Starting [0;1;39mLoad Kernel Module drm[0m...
10802 22:14:55.379409 <30>[ 16.875065] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10803 22:14:55.389345 <30>[ 16.888588] systemd[1]: Starting Journal Service...
10804 22:14:55.392392 Starting [0;1;39mJournal Service[0m...
10805 22:14:55.410196 <30>[ 16.909506] systemd[1]: Starting Load Kernel Modules...
10806 22:14:55.416561 Starting [0;1;39mLoad Kernel Modules[0m...
10807 22:14:55.437878 <30>[ 16.933861] systemd[1]: Starting Remount Root and Kernel File Systems...
10808 22:14:55.444536 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10809 22:14:55.462086 <30>[ 16.961386] systemd[1]: Starting Coldplug All udev Devices...
10810 22:14:55.468614 Starting [0;1;39mColdplug All udev Devices[0m...
10811 22:14:55.487031 <30>[ 16.985919] systemd[1]: Mounted Huge Pages File System.
10812 22:14:55.493368 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10813 22:14:55.507869 <30>[ 17.007650] systemd[1]: Started Journal Service.
10814 22:14:55.514536 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10815 22:14:55.529396 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10816 22:14:55.544403 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10817 22:14:55.564369 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10818 22:14:55.581121 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10819 22:14:55.597526 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10820 22:14:55.613050 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10821 22:14:55.632330 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10822 22:14:55.648405 See 'systemctl status systemd-remount-fs.service' for details.
10823 22:14:55.692437 Mounting [0;1;39mKernel Configuration File System[0m...
10824 22:14:55.710008 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10825 22:14:55.728216 <46>[ 17.224336] systemd-journald[181]: Received client request to flush runtime journal.
10826 22:14:55.736484 Starting [0;1;39mLoad/Save Random Seed[0m...
10827 22:14:55.758593 Starting [0;1;39mApply Kernel Variables[0m...
10828 22:14:55.774508 Starting [0;1;39mCreate System Users[0m...
10829 22:14:55.795703 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10830 22:14:55.816750 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10831 22:14:55.828511 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10832 22:14:55.848506 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10833 22:14:55.868650 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10834 22:14:55.888836 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10835 22:14:55.936099 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10836 22:14:55.959874 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10837 22:14:55.976338 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10838 22:14:55.991671 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10839 22:14:56.036208 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10840 22:14:56.059180 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10841 22:14:56.076726 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10842 22:14:56.097061 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10843 22:14:56.144997 Starting [0;1;39mNetwork Service[0m...
10844 22:14:56.170822 Starting [0;1;39mNetwork Time Synchronization[0m...
10845 22:14:56.190639 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10846 22:14:56.222366 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10847 22:14:56.241817 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10848 22:14:56.263914 Starting [0;1;39mNetwork Name Resolution[0m...
10849 22:14:56.292970 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10850 22:14:56.312534 <6>[ 17.807976] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10851 22:14:56.314908 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10852 22:14:56.329035 <6>[ 17.828478] remoteproc remoteproc0: scp is available
10853 22:14:56.339433 <4>[ 17.833974] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10854 22:14:56.348798 <3>[ 17.838817] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10855 22:14:56.352319 <6>[ 17.845782] remoteproc remoteproc0: powering up scp
10856 22:14:56.362172 <3>[ 17.852228] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10857 22:14:56.371824 <4>[ 17.857249] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10858 22:14:56.379673 <3>[ 17.865424] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10859 22:14:56.385285 <3>[ 17.875106] remoteproc remoteproc0: request_firmware failed: -2
10860 22:14:56.394965 [[0;32m OK [<3>[ 17.890698] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10861 22:14:56.405194 0m] Created slic<3>[ 17.899590] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10862 22:14:56.414810 e [0;1;39msyste<3>[ 17.909108] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10863 22:14:56.421737 m-systemd\x2dbac<6>[ 17.910005] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10864 22:14:56.431671 klight.slice[0m<3>[ 17.918582] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10865 22:14:56.431764 .
10866 22:14:56.441533 <6>[ 17.927583] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10867 22:14:56.448118 <3>[ 17.936856] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10868 22:14:56.458347 <6>[ 17.945812] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10869 22:14:56.464506 <4>[ 17.952861] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10870 22:14:56.471716 <4>[ 17.952980] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10871 22:14:56.482486 <3>[ 17.953943] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10872 22:14:56.487548 <6>[ 17.979358] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10873 22:14:56.498179 <3>[ 17.988814] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10874 22:14:56.503943 <3>[ 18.001091] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10875 22:14:56.507864 <6>[ 18.002703] mc: Linux media interface: v0.10
10876 22:14:56.517511 <3>[ 18.009190] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10877 22:14:56.527378 [[0;32m OK [<4>[ 18.012955] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10878 22:14:56.531133 <4>[ 18.012955] Fallback method does not support PEC.
10879 22:14:56.540714 <3>[ 18.024825] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10880 22:14:56.548911 0m] Reached targ<6>[ 18.041351] usbcore: registered new interface driver r8152
10881 22:14:56.558471 et [0;1;39mSyst<3>[ 18.045079] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10882 22:14:56.564766 em Time Set[0m.<6>[ 18.045983] videodev: Linux video capture interface: v2.00
10883 22:14:56.564863
10884 22:14:56.575098 <3>[ 18.054210] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10885 22:14:56.581166 <3>[ 18.061620] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10886 22:14:56.588538 <3>[ 18.061632] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10887 22:14:56.598023 <3>[ 18.061640] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10888 22:14:56.604640 <3>[ 18.070228] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10889 22:14:56.614706 <6>[ 18.083200] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10890 22:14:56.621085 <6>[ 18.087272] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10891 22:14:56.627625 [[0;32m OK [<6>[ 18.127052] pci_bus 0000:00: root bus resource [bus 00-ff]
10892 22:14:56.637932 0m] Reached targ<6>[ 18.134144] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10893 22:14:56.647682 et [0;1;39mSyst<6>[ 18.142534] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10894 22:14:56.660879 em Time Synchron<6>[ 18.151103] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10895 22:14:56.667498 <6>[ 18.153872] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10896 22:14:56.667620 ized[0m.
10897 22:14:56.674100 <6>[ 18.165678] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10898 22:14:56.684045 <6>[ 18.165744] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10899 22:14:56.690798 <6>[ 18.171578] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10900 22:14:56.697062 <6>[ 18.171702] pci 0000:00:00.0: supports D1 D2
10901 22:14:56.700634 <6>[ 18.189451] usbcore: registered new interface driver cdc_ether
10902 22:14:56.710958 <6>[ 18.196173] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10903 22:14:56.713889 <6>[ 18.201672] Bluetooth: Core ver 2.22
10904 22:14:56.720282 <6>[ 18.207697] usbcore: registered new interface driver r8153_ecm
10905 22:14:56.727571 <6>[ 18.208636] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10906 22:14:56.734118 <6>[ 18.209494] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10907 22:14:56.740457 <6>[ 18.209912] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10908 22:14:56.746929 <6>[ 18.209943] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10909 22:14:56.757585 <6>[ 18.209964] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10910 22:14:56.763701 <6>[ 18.209982] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10911 22:14:56.767057 <6>[ 18.210130] pci 0000:01:00.0: supports D1 D2
10912 22:14:56.773961 <6>[ 18.210135] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10913 22:14:56.787022 <6>[ 18.210173] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10914 22:14:56.794648 <6>[ 18.210350] usbcore: registered new interface driver uvcvideo
10915 22:14:56.798012 <6>[ 18.213941] NET: Registered PF_BLUETOOTH protocol family
10916 22:14:56.805686 <6>[ 18.218880] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10917 22:14:56.811312 <6>[ 18.223706] Bluetooth: HCI device and connection manager initialized
10918 22:14:56.817882 <6>[ 18.223747] Bluetooth: HCI socket layer initialized
10919 22:14:56.824767 <6>[ 18.230815] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10920 22:14:56.831777 <6>[ 18.239061] Bluetooth: L2CAP socket layer initialized
10921 22:14:56.838971 <6>[ 18.240008] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10922 22:14:56.841573 <6>[ 18.244200] remoteproc remoteproc0: powering up scp
10923 22:14:56.852926 <4>[ 18.244246] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10924 22:14:56.858611 <3>[ 18.244254] remoteproc remoteproc0: request_firmware failed: -2
10925 22:14:56.865536 <3>[ 18.244257] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
10926 22:14:56.872319 <6>[ 18.245291] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10927 22:14:56.878613 <6>[ 18.252811] Bluetooth: SCO socket layer initialized
10928 22:14:56.886064 <6>[ 18.260246] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10929 22:14:56.895798 <6>[ 18.260263] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10930 22:14:56.902966 <6>[ 18.260279] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10931 22:14:56.912636 <4>[ 18.271133] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10932 22:14:56.916206 <6>[ 18.272284] pci 0000:00:00.0: PCI bridge to [bus 01]
10933 22:14:56.926887 <4>[ 18.279146] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10934 22:14:56.933444 <6>[ 18.291558] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10935 22:14:56.943291 <3>[ 18.298891] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10936 22:14:56.953145 <3>[ 18.299648] power_supply sbs-5-000b: driver failed to report `capacity_error_margin' property: -6
10937 22:14:56.956687 <6>[ 18.303324] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10938 22:14:56.966596 <3>[ 18.305891] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10939 22:14:56.972897 <3>[ 18.306709] power_supply sbs-5-000b: driver failed to report `temp' property: -6
10940 22:14:56.979451 <6>[ 18.310996] usbcore: registered new interface driver btusb
10941 22:14:56.989287 <4>[ 18.311640] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10942 22:14:56.996268 <3>[ 18.311651] Bluetooth: hci0: Failed to load firmware file (-2)
10943 22:14:57.002536 <3>[ 18.311655] Bluetooth: hci0: Failed to set up firmware (-2)
10944 22:14:57.013218 <4>[ 18.311659] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10945 22:14:57.019467 <6>[ 18.317710] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10946 22:14:57.028952 <3>[ 18.341522] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10947 22:14:57.032657 <6>[ 18.342006] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10948 22:14:57.039409 <6>[ 18.346990] r8152 2-1.3:1.0 eth0: v1.12.13
10949 22:14:57.045700 <3>[ 18.367358] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10950 22:14:57.055722 <5>[ 18.381828] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10951 22:14:57.062089 <6>[ 18.385127] r8152 2-1.3:1.0 enx002432307852: renamed from eth0
10952 22:14:57.069309 <5>[ 18.402703] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10953 22:14:57.075478 <3>[ 18.406018] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10954 22:14:57.085703 <3>[ 18.427596] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10955 22:14:57.092437 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10956 22:14:57.104173 <4>[ 18.600582] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10957 22:14:57.111264 <6>[ 18.609497] cfg80211: failed to load regulatory.db
10958 22:14:57.117809 <3>[ 18.612602] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10959 22:14:57.124061 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10960 22:14:57.149473 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10961 22:14:57.159851 <6>[ 18.655911] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10962 22:14:57.163304 <6>[ 18.663454] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10963 22:14:57.190513 <6>[ 18.690145] mt7921e 0000:01:00.0: ASIC revision: 79610010
10964 22:14:57.297660 <4>[ 18.790587] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10965 22:14:57.333288 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10966 22:14:57.352165 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10967 22:14:57.374895 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10968 22:14:57.387713 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10969 22:14:57.408928 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10970 22:14:57.422251 <4>[ 18.914049] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10971 22:14:57.429066 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10972 22:14:57.435889 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10973 22:14:57.455291 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10974 22:14:57.467472 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10975 22:14:57.483966 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10976 22:14:57.502538 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10977 22:14:57.540510 <4>[ 19.033297] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10978 22:14:57.554158 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10979 22:14:57.582077 Starting [0;1;39mUser Login Management[0m...
10980 22:14:57.598149 Starting [0;1;39mPermit User Sessions[0m...
10981 22:14:57.615547 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10982 22:14:57.631912 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10983 22:14:57.664246 [[0;32m OK [0m] Finished [0<4>[ 19.155492] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10984 22:14:57.666909 ;1;39mPermit User Sessions[0m.
10985 22:14:57.708494 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10986 22:14:57.726492 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10987 22:14:57.743472 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10988 22:14:57.760873 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10989 22:14:57.767878 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10990 22:14:57.776786 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10991 22:14:57.790285 <4>[ 19.282533] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10992 22:14:57.828852 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10993 22:14:57.855716 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10994 22:14:57.874273
10995 22:14:57.874424
10996 22:14:57.877120 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10997 22:14:57.877207
10998 22:14:57.880420 debian-bullseye-arm64 login: root (automatic login)
10999 22:14:57.880509
11000 22:14:57.880576
11001 22:14:57.908868 Linux debian-bul<4>[ 19.402370] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11002 22:14:57.915452 lseye-arm64 6.1.31 #1 SMP PREEMPT Sun Jun 4 21:56:05 UTC 2023 aarch64
11003 22:14:57.915582
11004 22:14:57.922240 The programs included with the Debian GNU/Linux system are free software;
11005 22:14:57.929198 the exact distribution terms for each program are described in the
11006 22:14:57.932441 individual files in /usr/share/doc/*/copyright.
11007 22:14:57.932549
11008 22:14:57.938708 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11009 22:14:57.941533 permitted by applicable law.
11010 22:14:57.941922 Matched prompt #10: / #
11012 22:14:57.942134 Setting prompt string to ['/ #']
11013 22:14:57.942230 end: 2.2.5.1 login-action (duration 00:00:20) [common]
11015 22:14:57.942422 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
11016 22:14:57.942508 start: 2.2.6 expect-shell-connection (timeout 00:02:39) [common]
11017 22:14:57.942581 Setting prompt string to ['/ #']
11018 22:14:57.942642 Forcing a shell prompt, looking for ['/ #']
11020 22:14:57.992870 / #
11021 22:14:57.993064 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11022 22:14:57.993198 Waiting using forced prompt support (timeout 00:02:30)
11023 22:14:57.998081
11024 22:14:57.998458 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11025 22:14:57.998566 start: 2.2.7 export-device-env (timeout 00:02:38) [common]
11026 22:14:57.998667 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11027 22:14:57.998755 end: 2.2 depthcharge-retry (duration 00:02:22) [common]
11028 22:14:57.998839 end: 2 depthcharge-action (duration 00:02:22) [common]
11029 22:14:57.998924 start: 3 lava-test-retry (timeout 00:05:00) [common]
11030 22:14:57.999008 start: 3.1 lava-test-shell (timeout 00:05:00) [common]
11031 22:14:57.999082 Using namespace: common
11033 22:14:58.099450 / # #
11034 22:14:58.099639 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:05:00)
11035 22:14:58.099828 <4>[ 19.525107] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11036 22:14:58.104681 #
11037 22:14:58.105023 Using /lava-10583887
11039 22:14:58.205425 / # export SHELL=/bin/sh
11040 22:14:58.205716 <4>[ 19.645012] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11041 22:14:58.210686 export SHELL=/bin/sh
11043 22:14:58.311343 / # . /lava-10583887/environment
11044 22:14:58.311618 <4>[ 19.764937] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11045 22:14:58.316934 . /lava-10583887/environment
11047 22:14:58.417573 / # /lava-10583887/bin/lava-test-runner /lava-10583887/0
11048 22:14:58.417772 Test shell timeout: 10s (minimum of the action and connection timeout)
11049 22:14:58.418262 /lava-10583887/bin/lava-test-runner /lava-10583887/0<4>[ 19.885467] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11050 22:14:58.423134
11051 22:14:58.464130 + export TESTRUN_ID=0_cros-ec
11052 22:14:58.464333 +<8>[ 19.947642] <LAVA_SIGNAL_STARTRUN 0_cros-ec 10583887_1.5.2.3.1>
11053 22:14:58.464447 cd /lava-10583887/0/tests/0_cros-ec
11054 22:14:58.464546 + cat uuid
11055 22:14:58.464644 + UUID=10583887_1.5.2.3.1
11056 22:14:58.464742 + set +x
11057 22:14:58.465070 Received signal: <STARTRUN> 0_cros-ec 10583887_1.5.2.3.1
11058 22:14:58.465167 Starting test lava.0_cros-ec (10583887_1.5.2.3.1)
11059 22:14:58.465281 Skipping test definition patterns.
11060 22:14:58.465431 + python3 -m cros.runners.lava_runner -v
11061 22:14:58.501689 <6>[ 19.997311] IPv6: ADDRCONF(NETDEV_CHANGE): enx002432307852: link becomes ready
11062 22:14:58.504520 <3>[ 20.005276] mt7921e 0000:01:00.0: hardware init failed
11063 22:14:58.510714 <6>[ 20.005962] r8152 2-1.3:1.0 enx002432307852: carrier on
11064 22:14:59.163269 test_cros_ec_accel_iio_abi (cros.tests.cros_ec_accel.TestCrosECAccel)
11065 22:14:59.172883 Checks the cros-ec accelerometer IIO ABI. ... skipped 'No cros-ec-accel found'
11066 22:14:59.173026
11067 22:14:59.179374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_accel_iio_abi RESULT=skip>
11068 22:14:59.179665 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_accel_iio_abi RESULT=skip
11070 22:14:59.186175 test_cros_ec_accel_iio_data_is_valid (cros.tests.cros_ec_accel.TestCrosECAccel)
11071 22:14:59.192545 Validates accelerometer data by computing the magnitude. If the ... skipped 'No accelerometer found'
11072 22:14:59.192665
11073 22:14:59.202567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_accel_iio_data_is_valid RESULT=skip>
11074 22:14:59.202887 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_accel_iio_data_is_valid RESULT=skip
11076 22:14:59.205899 test_cros_ec_gyro_iio_abi (cros.tests.cros_ec_gyro.TestCrosECGyro)
11077 22:14:59.215781 Checks the cros-ec gyros<8>[ 20.713039] <LAVA_SIGNAL_ENDRUN 0_cros-ec 10583887_1.5.2.3.1>
11078 22:14:59.216087 Received signal: <ENDRUN> 0_cros-ec 10583887_1.5.2.3.1
11079 22:14:59.216187 Ending use of test pattern.
11080 22:14:59.216252 Ending test lava.0_cros-ec (10583887_1.5.2.3.1), duration 0.75
11082 22:14:59.219018 cope IIO ABI. ... skipped 'No cros-ec-gyro found'
11083 22:14:59.219103
11084 22:14:59.225822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_gyro_iio_abi RESULT=skip>
11085 22:14:59.226104 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_gyro_iio_abi RESULT=skip
11087 22:14:59.232194 test_cros_ec_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11088 22:14:59.238844 Checks the standard ABI for the main Embedded Controller. ... ok
11089 22:14:59.238959
11090 22:14:59.242799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_abi RESULT=pass>
11091 22:14:59.243067 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_abi RESULT=pass
11093 22:14:59.248698 test_cros_ec_chardev (cros.tests.cros_ec_mcu.TestCrosECMCU)
11094 22:14:59.255838 Checks the main Embedded controller character device. ... ok
11095 22:14:59.255968
11096 22:14:59.258687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_chardev RESULT=pass>
11097 22:14:59.258951 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_chardev RESULT=pass
11099 22:14:59.265730 test_cros_ec_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11100 22:14:59.271796 Checks basic comunication with the main Embedded controller. ... ok
11101 22:14:59.271909
11102 22:14:59.278584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_hello RESULT=pass>
11103 22:14:59.278907 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_hello RESULT=pass
11105 22:14:59.281781 test_cros_fp_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11106 22:14:59.288461 Checks the standard ABI for the Fingerprint EC. ... skipped 'MCU cros_fp not supported'
11107 22:14:59.291856
11108 22:14:59.295545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_abi RESULT=skip>
11109 22:14:59.295833 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_abi RESULT=skip
11111 22:14:59.302081 test_cros_fp_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11112 22:14:59.308291 Checks basic comunication with the fingerprint controller. ... skipped 'MCU cros_fp not found'
11113 22:14:59.308403
11114 22:14:59.314788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_hello RESULT=skip>
11115 22:14:59.315072 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_hello RESULT=skip
11117 22:14:59.321629 test_cros_fp_reboot (cros.tests.cros_ec_mcu.TestCrosECMCU)
11118 22:14:59.328395 Test reboot command on Fingerprint MCU. ... skipped 'MCU cros_fp not found'
11119 22:14:59.328507
11120 22:14:59.334782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_reboot RESULT=skip>
11121 22:14:59.335061 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_reboot RESULT=skip
11123 22:14:59.338821 test_cros_pd_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11124 22:14:59.348144 Checks the standard ABI for the Power Delivery EC. ... skipped 'MCU cros_pd not supported'
11125 22:14:59.348260
11126 22:14:59.352285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_pd_abi RESULT=skip>
11127 22:14:59.352552 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_pd_abi RESULT=skip
11129 22:14:59.357781 test_cros_pd_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11130 22:14:59.364773 Checks basic comunication with the power delivery controller. ... skipped 'MCU cros_pd not found'
11131 22:14:59.364883
11132 22:14:59.371232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_pd_hello RESULT=skip>
11133 22:14:59.371527 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_pd_hello RESULT=skip
11135 22:14:59.377732 test_cros_tp_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11136 22:14:59.384560 Checks the standard ABI for the Touchpad EC. ... skipped 'MCU cros_tp not supported'
11137 22:14:59.384671
11138 22:14:59.391685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_tp_abi RESULT=skip>
11139 22:14:59.391993 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_tp_abi RESULT=skip
11141 22:14:59.394641 test_cros_tp_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11142 22:14:59.403970 Checks basic comunication with the touchpad controller. ... skipped 'MCU cros_tp not found'
11143 22:14:59.404114
11144 22:14:59.411011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_tp_hello RESULT=skip>
11145 22:14:59.411363 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_tp_hello RESULT=skip
11147 22:14:59.414250 test_cros_ec_pwm_backlight (cros.tests.cros_ec_pwm.TestCrosECPWM)
11148 22:14:59.424485 Check that the backlight is connected to a pwm of the EC and that ... skipped 'No backlight pwm found'
11149 22:14:59.424616
11150 22:14:59.431221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_pwm_backlight RESULT=skip>
11151 22:14:59.431503 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_pwm_backlight RESULT=skip
11153 22:14:59.437948 test_cros_ec_battery_abi (cros.tests.cros_ec_power.TestCrosECPower)
11154 22:14:59.440721 Check the cros battery ABI. ... skipped 'No BAT found'
11155 22:14:59.443873
11156 22:14:59.447696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_battery_abi RESULT=skip>
11157 22:14:59.448014 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_battery_abi RESULT=skip
11159 22:14:59.453872 test_cros_ec_usbpd_charger_abi (cros.tests.cros_ec_power.TestCrosECPower)
11160 22:14:59.460574 Check the cros USBPD charger ABI. ... skipped 'No CROS_USBPD_CHARGER found'
11161 22:14:59.463511
11162 22:14:59.470691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_usbpd_charger_abi RESULT=skip>
11163 22:14:59.470999 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_usbpd_charger_abi RESULT=skip
11165 22:14:59.473419 test_cros_ec_rtc_abi (cros.tests.cros_ec_rtc.TestCrosECRTC)
11166 22:14:59.479911 Check the cros RTC ABI. ... skipped 'EC_FEATURE_RTC not supported, skipping'
11167 22:14:59.480047
11168 22:14:59.487010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_rtc_abi RESULT=skip>
11169 22:14:59.487318 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_rtc_abi RESULT=skip
11171 22:14:59.493250 test_cros_ec_extcon_usbc_abi (cros.tests.cros_ec_extcon.TestCrosECextcon)
11172 22:14:59.499798 Checks the cros-ec extcon ABI. ... skipped 'No extcon device found'
11173 22:14:59.499992
11174 22:14:59.506827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_extcon_usbc_abi RESULT=skip>
11175 22:14:59.506961
11176 22:14:59.507246 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_extcon_usbc_abi RESULT=skip
11178 22:14:59.513174 ----------------------------------------------------------------------
11179 22:14:59.516741 Ran 18 tests in 0.010s
11180 22:14:59.516836
11181 22:14:59.516907 OK (skipped=15)
11182 22:14:59.516998 + set +x
11183 22:14:59.520091 <LAVA_TEST_RUNNER EXIT>
11184 22:14:59.520350 ok: lava_test_shell seems to have completed
11185 22:14:59.520528 test_cros_ec_abi: pass
test_cros_ec_accel_iio_abi: skip
test_cros_ec_accel_iio_data_is_valid: skip
test_cros_ec_battery_abi: skip
test_cros_ec_chardev: pass
test_cros_ec_extcon_usbc_abi: skip
test_cros_ec_gyro_iio_abi: skip
test_cros_ec_hello: pass
test_cros_ec_pwm_backlight: skip
test_cros_ec_rtc_abi: skip
test_cros_ec_usbpd_charger_abi: skip
test_cros_fp_abi: skip
test_cros_fp_hello: skip
test_cros_fp_reboot: skip
test_cros_pd_abi: skip
test_cros_pd_hello: skip
test_cros_tp_abi: skip
test_cros_tp_hello: skip
11186 22:14:59.520626 end: 3.1 lava-test-shell (duration 00:00:02) [common]
11187 22:14:59.520714 end: 3 lava-test-retry (duration 00:00:02) [common]
11188 22:14:59.520799 start: 4 finalize (timeout 00:07:15) [common]
11189 22:14:59.520884 start: 4.1 power-off (timeout 00:00:30) [common]
11190 22:14:59.521041 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=off'
11191 22:14:59.598440 >> Command sent successfully.
11192 22:14:59.601598 Returned 0 in 0 seconds
11193 22:14:59.702014 end: 4.1 power-off (duration 00:00:00) [common]
11195 22:14:59.702360 start: 4.2 read-feedback (timeout 00:07:15) [common]
11196 22:14:59.702618 Listened to connection for namespace 'common' for up to 1s
11197 22:15:00.703573 Finalising connection for namespace 'common'
11198 22:15:00.703836 Disconnecting from shell: Finalise
11199 22:15:00.704061 / #
11200 22:15:00.804464 end: 4.2 read-feedback (duration 00:00:01) [common]
11201 22:15:00.804735 end: 4 finalize (duration 00:00:01) [common]
11202 22:15:00.804926 Cleaning after the job
11203 22:15:00.805089 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10583887/tftp-deploy-bh6vuykx/ramdisk
11204 22:15:00.812551 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10583887/tftp-deploy-bh6vuykx/kernel
11205 22:15:00.821352 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10583887/tftp-deploy-bh6vuykx/dtb
11206 22:15:00.821696 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10583887/tftp-deploy-bh6vuykx/modules
11207 22:15:00.829777 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10583887
11208 22:15:00.939591 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10583887
11209 22:15:00.939774 Job finished correctly