Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 29
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 23
1 22:17:49.102550 lava-dispatcher, installed at version: 2023.03
2 22:17:49.102789 start: 0 validate
3 22:17:49.102925 Start time: 2023-06-04 22:17:49.102917+00:00 (UTC)
4 22:17:49.103062 Using caching service: 'http://localhost/cache/?uri=%s'
5 22:17:49.103202 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-igt%2F20230527.0%2Farm64%2Frootfs.cpio.gz exists
6 22:17:49.388935 Using caching service: 'http://localhost/cache/?uri=%s'
7 22:17:49.389124 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1281-g84d5372e0f314%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 22:17:49.679195 Using caching service: 'http://localhost/cache/?uri=%s'
9 22:17:49.679388 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1281-g84d5372e0f314%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 22:17:49.965242 Using caching service: 'http://localhost/cache/?uri=%s'
11 22:17:49.965424 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1281-g84d5372e0f314%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 22:17:50.251790 validate duration: 1.15
14 22:17:50.252059 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 22:17:50.252159 start: 1.1 download-retry (timeout 00:10:00) [common]
16 22:17:50.252254 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 22:17:50.252383 Not decompressing ramdisk as can be used compressed.
18 22:17:50.252467 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-igt/20230527.0/arm64/rootfs.cpio.gz
19 22:17:50.252539 saving as /var/lib/lava/dispatcher/tmp/10583924/tftp-deploy-7_wm5peu/ramdisk/rootfs.cpio.gz
20 22:17:50.252654 total size: 43394293 (41MB)
21 22:17:50.253783 progress 0% (0MB)
22 22:17:50.264796 progress 5% (2MB)
23 22:17:50.275809 progress 10% (4MB)
24 22:17:50.286699 progress 15% (6MB)
25 22:17:50.297600 progress 20% (8MB)
26 22:17:50.308718 progress 25% (10MB)
27 22:17:50.319761 progress 30% (12MB)
28 22:17:50.330888 progress 35% (14MB)
29 22:17:50.341824 progress 40% (16MB)
30 22:17:50.352708 progress 45% (18MB)
31 22:17:50.363911 progress 50% (20MB)
32 22:17:50.374895 progress 55% (22MB)
33 22:17:50.385871 progress 60% (24MB)
34 22:17:50.396827 progress 65% (26MB)
35 22:17:50.407939 progress 70% (29MB)
36 22:17:50.418969 progress 75% (31MB)
37 22:17:50.429939 progress 80% (33MB)
38 22:17:50.440858 progress 85% (35MB)
39 22:17:50.451721 progress 90% (37MB)
40 22:17:50.462634 progress 95% (39MB)
41 22:17:50.473362 progress 100% (41MB)
42 22:17:50.473601 41MB downloaded in 0.22s (187.31MB/s)
43 22:17:50.473770 end: 1.1.1 http-download (duration 00:00:00) [common]
45 22:17:50.474007 end: 1.1 download-retry (duration 00:00:00) [common]
46 22:17:50.474095 start: 1.2 download-retry (timeout 00:10:00) [common]
47 22:17:50.474179 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 22:17:50.474312 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1281-g84d5372e0f314/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 22:17:50.474386 saving as /var/lib/lava/dispatcher/tmp/10583924/tftp-deploy-7_wm5peu/kernel/Image
50 22:17:50.474448 total size: 45746688 (43MB)
51 22:17:50.474509 No compression specified
52 22:17:50.475618 progress 0% (0MB)
53 22:17:50.487016 progress 5% (2MB)
54 22:17:50.498600 progress 10% (4MB)
55 22:17:50.510202 progress 15% (6MB)
56 22:17:50.521901 progress 20% (8MB)
57 22:17:50.533558 progress 25% (10MB)
58 22:17:50.545069 progress 30% (13MB)
59 22:17:50.556616 progress 35% (15MB)
60 22:17:50.568168 progress 40% (17MB)
61 22:17:50.579730 progress 45% (19MB)
62 22:17:50.591288 progress 50% (21MB)
63 22:17:50.602685 progress 55% (24MB)
64 22:17:50.614248 progress 60% (26MB)
65 22:17:50.625858 progress 65% (28MB)
66 22:17:50.637422 progress 70% (30MB)
67 22:17:50.649276 progress 75% (32MB)
68 22:17:50.660726 progress 80% (34MB)
69 22:17:50.672294 progress 85% (37MB)
70 22:17:50.683861 progress 90% (39MB)
71 22:17:50.695217 progress 95% (41MB)
72 22:17:50.706596 progress 100% (43MB)
73 22:17:50.706769 43MB downloaded in 0.23s (187.79MB/s)
74 22:17:50.706929 end: 1.2.1 http-download (duration 00:00:00) [common]
76 22:17:50.707155 end: 1.2 download-retry (duration 00:00:00) [common]
77 22:17:50.707240 start: 1.3 download-retry (timeout 00:10:00) [common]
78 22:17:50.707323 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 22:17:50.707464 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1281-g84d5372e0f314/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 22:17:50.707539 saving as /var/lib/lava/dispatcher/tmp/10583924/tftp-deploy-7_wm5peu/dtb/mt8192-asurada-spherion-r0.dtb
81 22:17:50.707601 total size: 46924 (0MB)
82 22:17:50.707661 No compression specified
83 22:17:50.708795 progress 69% (0MB)
84 22:17:50.709070 progress 100% (0MB)
85 22:17:50.709222 0MB downloaded in 0.00s (27.65MB/s)
86 22:17:50.709342 end: 1.3.1 http-download (duration 00:00:00) [common]
88 22:17:50.709601 end: 1.3 download-retry (duration 00:00:00) [common]
89 22:17:50.709685 start: 1.4 download-retry (timeout 00:10:00) [common]
90 22:17:50.709767 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 22:17:50.709875 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1281-g84d5372e0f314/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 22:17:50.709945 saving as /var/lib/lava/dispatcher/tmp/10583924/tftp-deploy-7_wm5peu/modules/modules.tar
93 22:17:50.710005 total size: 8541948 (8MB)
94 22:17:50.710065 Using unxz to decompress xz
95 22:17:50.713804 progress 0% (0MB)
96 22:17:50.735439 progress 5% (0MB)
97 22:17:50.761358 progress 10% (0MB)
98 22:17:50.787710 progress 15% (1MB)
99 22:17:50.813337 progress 20% (1MB)
100 22:17:50.836839 progress 25% (2MB)
101 22:17:50.863781 progress 30% (2MB)
102 22:17:50.889182 progress 35% (2MB)
103 22:17:50.913618 progress 40% (3MB)
104 22:17:50.937520 progress 45% (3MB)
105 22:17:50.962610 progress 50% (4MB)
106 22:17:50.986445 progress 55% (4MB)
107 22:17:51.011076 progress 60% (4MB)
108 22:17:51.036090 progress 65% (5MB)
109 22:17:51.060847 progress 70% (5MB)
110 22:17:51.084509 progress 75% (6MB)
111 22:17:51.109178 progress 80% (6MB)
112 22:17:51.133944 progress 85% (6MB)
113 22:17:51.162730 progress 90% (7MB)
114 22:17:51.188393 progress 95% (7MB)
115 22:17:51.212917 progress 100% (8MB)
116 22:17:51.218701 8MB downloaded in 0.51s (16.01MB/s)
117 22:17:51.219004 end: 1.4.1 http-download (duration 00:00:01) [common]
119 22:17:51.219272 end: 1.4 download-retry (duration 00:00:01) [common]
120 22:17:51.219366 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 22:17:51.219465 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 22:17:51.219547 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 22:17:51.219634 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 22:17:51.219868 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10583924/lava-overlay-t_h14y2o
125 22:17:51.219998 makedir: /var/lib/lava/dispatcher/tmp/10583924/lava-overlay-t_h14y2o/lava-10583924/bin
126 22:17:51.220107 makedir: /var/lib/lava/dispatcher/tmp/10583924/lava-overlay-t_h14y2o/lava-10583924/tests
127 22:17:51.220204 makedir: /var/lib/lava/dispatcher/tmp/10583924/lava-overlay-t_h14y2o/lava-10583924/results
128 22:17:51.220320 Creating /var/lib/lava/dispatcher/tmp/10583924/lava-overlay-t_h14y2o/lava-10583924/bin/lava-add-keys
129 22:17:51.220465 Creating /var/lib/lava/dispatcher/tmp/10583924/lava-overlay-t_h14y2o/lava-10583924/bin/lava-add-sources
130 22:17:51.220595 Creating /var/lib/lava/dispatcher/tmp/10583924/lava-overlay-t_h14y2o/lava-10583924/bin/lava-background-process-start
131 22:17:51.220721 Creating /var/lib/lava/dispatcher/tmp/10583924/lava-overlay-t_h14y2o/lava-10583924/bin/lava-background-process-stop
132 22:17:51.220844 Creating /var/lib/lava/dispatcher/tmp/10583924/lava-overlay-t_h14y2o/lava-10583924/bin/lava-common-functions
133 22:17:51.220965 Creating /var/lib/lava/dispatcher/tmp/10583924/lava-overlay-t_h14y2o/lava-10583924/bin/lava-echo-ipv4
134 22:17:51.221092 Creating /var/lib/lava/dispatcher/tmp/10583924/lava-overlay-t_h14y2o/lava-10583924/bin/lava-install-packages
135 22:17:51.221213 Creating /var/lib/lava/dispatcher/tmp/10583924/lava-overlay-t_h14y2o/lava-10583924/bin/lava-installed-packages
136 22:17:51.221333 Creating /var/lib/lava/dispatcher/tmp/10583924/lava-overlay-t_h14y2o/lava-10583924/bin/lava-os-build
137 22:17:51.221453 Creating /var/lib/lava/dispatcher/tmp/10583924/lava-overlay-t_h14y2o/lava-10583924/bin/lava-probe-channel
138 22:17:51.221650 Creating /var/lib/lava/dispatcher/tmp/10583924/lava-overlay-t_h14y2o/lava-10583924/bin/lava-probe-ip
139 22:17:51.221773 Creating /var/lib/lava/dispatcher/tmp/10583924/lava-overlay-t_h14y2o/lava-10583924/bin/lava-target-ip
140 22:17:51.221897 Creating /var/lib/lava/dispatcher/tmp/10583924/lava-overlay-t_h14y2o/lava-10583924/bin/lava-target-mac
141 22:17:51.222018 Creating /var/lib/lava/dispatcher/tmp/10583924/lava-overlay-t_h14y2o/lava-10583924/bin/lava-target-storage
142 22:17:51.222143 Creating /var/lib/lava/dispatcher/tmp/10583924/lava-overlay-t_h14y2o/lava-10583924/bin/lava-test-case
143 22:17:51.222265 Creating /var/lib/lava/dispatcher/tmp/10583924/lava-overlay-t_h14y2o/lava-10583924/bin/lava-test-event
144 22:17:51.222384 Creating /var/lib/lava/dispatcher/tmp/10583924/lava-overlay-t_h14y2o/lava-10583924/bin/lava-test-feedback
145 22:17:51.222505 Creating /var/lib/lava/dispatcher/tmp/10583924/lava-overlay-t_h14y2o/lava-10583924/bin/lava-test-raise
146 22:17:51.222630 Creating /var/lib/lava/dispatcher/tmp/10583924/lava-overlay-t_h14y2o/lava-10583924/bin/lava-test-reference
147 22:17:51.222761 Creating /var/lib/lava/dispatcher/tmp/10583924/lava-overlay-t_h14y2o/lava-10583924/bin/lava-test-runner
148 22:17:51.222884 Creating /var/lib/lava/dispatcher/tmp/10583924/lava-overlay-t_h14y2o/lava-10583924/bin/lava-test-set
149 22:17:51.223007 Creating /var/lib/lava/dispatcher/tmp/10583924/lava-overlay-t_h14y2o/lava-10583924/bin/lava-test-shell
150 22:17:51.223132 Updating /var/lib/lava/dispatcher/tmp/10583924/lava-overlay-t_h14y2o/lava-10583924/bin/lava-install-packages (oe)
151 22:17:51.223283 Updating /var/lib/lava/dispatcher/tmp/10583924/lava-overlay-t_h14y2o/lava-10583924/bin/lava-installed-packages (oe)
152 22:17:51.223403 Creating /var/lib/lava/dispatcher/tmp/10583924/lava-overlay-t_h14y2o/lava-10583924/environment
153 22:17:51.223503 LAVA metadata
154 22:17:51.223578 - LAVA_JOB_ID=10583924
155 22:17:51.223643 - LAVA_DISPATCHER_IP=192.168.201.1
156 22:17:51.223746 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 22:17:51.223834 skipped lava-vland-overlay
158 22:17:51.223946 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 22:17:51.224044 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 22:17:51.224107 skipped lava-multinode-overlay
161 22:17:51.224190 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 22:17:51.224275 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 22:17:51.224354 Loading test definitions
164 22:17:51.224448 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 22:17:51.224522 Using /lava-10583924 at stage 0
166 22:17:51.224821 uuid=10583924_1.5.2.3.1 testdef=None
167 22:17:51.224909 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 22:17:51.224994 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 22:17:51.225500 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 22:17:51.225761 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 22:17:51.226365 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 22:17:51.226597 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 22:17:51.227184 runner path: /var/lib/lava/dispatcher/tmp/10583924/lava-overlay-t_h14y2o/lava-10583924/0/tests/0_igt-gpu-panfrost test_uuid 10583924_1.5.2.3.1
176 22:17:51.227338 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 22:17:51.227542 Creating lava-test-runner.conf files
179 22:17:51.227605 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10583924/lava-overlay-t_h14y2o/lava-10583924/0 for stage 0
180 22:17:51.227693 - 0_igt-gpu-panfrost
181 22:17:51.227788 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 22:17:51.227872 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 22:17:51.234427 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 22:17:51.234542 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 22:17:51.234630 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 22:17:51.234717 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 22:17:51.234803 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 22:17:52.575039 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 22:17:52.575419 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 22:17:52.575536 extracting modules file /var/lib/lava/dispatcher/tmp/10583924/tftp-deploy-7_wm5peu/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10583924/extract-overlay-ramdisk-0ntghslw/ramdisk
191 22:17:52.787705 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 22:17:52.787879 start: 1.5.5 apply-overlay-tftp (timeout 00:09:57) [common]
193 22:17:52.787974 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10583924/compress-overlay-qln_u1ld/overlay-1.5.2.4.tar.gz to ramdisk
194 22:17:52.788048 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10583924/compress-overlay-qln_u1ld/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10583924/extract-overlay-ramdisk-0ntghslw/ramdisk
195 22:17:52.794367 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 22:17:52.794487 start: 1.5.6 configure-preseed-file (timeout 00:09:57) [common]
197 22:17:52.794579 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 22:17:52.794669 start: 1.5.7 compress-ramdisk (timeout 00:09:57) [common]
199 22:17:52.794750 Building ramdisk /var/lib/lava/dispatcher/tmp/10583924/extract-overlay-ramdisk-0ntghslw/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10583924/extract-overlay-ramdisk-0ntghslw/ramdisk
200 22:17:53.776013 >> 369037 blocks
201 22:17:59.489761 rename /var/lib/lava/dispatcher/tmp/10583924/extract-overlay-ramdisk-0ntghslw/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10583924/tftp-deploy-7_wm5peu/ramdisk/ramdisk.cpio.gz
202 22:17:59.490160 end: 1.5.7 compress-ramdisk (duration 00:00:07) [common]
203 22:17:59.490283 start: 1.5.8 prepare-kernel (timeout 00:09:51) [common]
204 22:17:59.490393 start: 1.5.8.1 prepare-fit (timeout 00:09:51) [common]
205 22:17:59.490500 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10583924/tftp-deploy-7_wm5peu/kernel/Image'
206 22:18:10.990168 Returned 0 in 11 seconds
207 22:18:11.090776 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10583924/tftp-deploy-7_wm5peu/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10583924/tftp-deploy-7_wm5peu/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10583924/tftp-deploy-7_wm5peu/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10583924/tftp-deploy-7_wm5peu/kernel/image.itb
208 22:18:11.881588 output: FIT description: Kernel Image image with one or more FDT blobs
209 22:18:11.881965 output: Created: Sun Jun 4 23:18:11 2023
210 22:18:11.882043 output: Image 0 (kernel-1)
211 22:18:11.882112 output: Description:
212 22:18:11.882190 output: Created: Sun Jun 4 23:18:11 2023
213 22:18:11.882257 output: Type: Kernel Image
214 22:18:11.882317 output: Compression: lzma compressed
215 22:18:11.882377 output: Data Size: 10081729 Bytes = 9845.44 KiB = 9.61 MiB
216 22:18:11.882483 output: Architecture: AArch64
217 22:18:11.882544 output: OS: Linux
218 22:18:11.882632 output: Load Address: 0x00000000
219 22:18:11.882707 output: Entry Point: 0x00000000
220 22:18:11.882767 output: Hash algo: crc32
221 22:18:11.882852 output: Hash value: 3b3111d8
222 22:18:11.882947 output: Image 1 (fdt-1)
223 22:18:11.883005 output: Description: mt8192-asurada-spherion-r0
224 22:18:11.883059 output: Created: Sun Jun 4 23:18:11 2023
225 22:18:11.883115 output: Type: Flat Device Tree
226 22:18:11.883179 output: Compression: uncompressed
227 22:18:11.883236 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
228 22:18:11.883291 output: Architecture: AArch64
229 22:18:11.883345 output: Hash algo: crc32
230 22:18:11.883399 output: Hash value: 1df858fa
231 22:18:11.883468 output: Image 2 (ramdisk-1)
232 22:18:11.883522 output: Description: unavailable
233 22:18:11.883576 output: Created: Sun Jun 4 23:18:11 2023
234 22:18:11.883630 output: Type: RAMDisk Image
235 22:18:11.883708 output: Compression: Unknown Compression
236 22:18:11.883792 output: Data Size: 56367037 Bytes = 55045.93 KiB = 53.76 MiB
237 22:18:11.883875 output: Architecture: AArch64
238 22:18:11.883967 output: OS: Linux
239 22:18:11.884051 output: Load Address: unavailable
240 22:18:11.884138 output: Entry Point: unavailable
241 22:18:11.884229 output: Hash algo: crc32
242 22:18:11.884313 output: Hash value: 4e8bdfed
243 22:18:11.884396 output: Default Configuration: 'conf-1'
244 22:18:11.884488 output: Configuration 0 (conf-1)
245 22:18:11.884572 output: Description: mt8192-asurada-spherion-r0
246 22:18:11.884656 output: Kernel: kernel-1
247 22:18:11.884746 output: Init Ramdisk: ramdisk-1
248 22:18:11.884829 output: FDT: fdt-1
249 22:18:11.884917 output: Loadables: kernel-1
250 22:18:11.885004 output:
251 22:18:11.885237 end: 1.5.8.1 prepare-fit (duration 00:00:12) [common]
252 22:18:11.885365 end: 1.5.8 prepare-kernel (duration 00:00:12) [common]
253 22:18:11.885517 end: 1.5 prepare-tftp-overlay (duration 00:00:21) [common]
254 22:18:11.885683 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:38) [common]
255 22:18:11.885794 No LXC device requested
256 22:18:11.885907 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 22:18:11.886034 start: 1.7 deploy-device-env (timeout 00:09:38) [common]
258 22:18:11.886140 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 22:18:11.886248 Checking files for TFTP limit of 4294967296 bytes.
260 22:18:11.886849 end: 1 tftp-deploy (duration 00:00:22) [common]
261 22:18:11.887033 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 22:18:11.887126 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 22:18:11.887284 substitutions:
264 22:18:11.887379 - {DTB}: 10583924/tftp-deploy-7_wm5peu/dtb/mt8192-asurada-spherion-r0.dtb
265 22:18:11.887487 - {INITRD}: 10583924/tftp-deploy-7_wm5peu/ramdisk/ramdisk.cpio.gz
266 22:18:11.887552 - {KERNEL}: 10583924/tftp-deploy-7_wm5peu/kernel/Image
267 22:18:11.887613 - {LAVA_MAC}: None
268 22:18:11.887683 - {PRESEED_CONFIG}: None
269 22:18:11.887744 - {PRESEED_LOCAL}: None
270 22:18:11.887801 - {RAMDISK}: 10583924/tftp-deploy-7_wm5peu/ramdisk/ramdisk.cpio.gz
271 22:18:11.887858 - {ROOT_PART}: None
272 22:18:11.887929 - {ROOT}: None
273 22:18:11.887989 - {SERVER_IP}: 192.168.201.1
274 22:18:11.888044 - {TEE}: None
275 22:18:11.888118 Parsed boot commands:
276 22:18:11.888188 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 22:18:11.888394 Parsed boot commands: tftpboot 192.168.201.1 10583924/tftp-deploy-7_wm5peu/kernel/image.itb 10583924/tftp-deploy-7_wm5peu/kernel/cmdline
278 22:18:11.888525 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 22:18:11.888643 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 22:18:11.888775 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 22:18:11.888893 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 22:18:11.889005 Not connected, no need to disconnect.
283 22:18:11.889114 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 22:18:11.889228 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 22:18:11.889297 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-0'
286 22:18:11.892818 Setting prompt string to ['lava-test: # ']
287 22:18:11.893211 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 22:18:11.893354 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 22:18:11.893491 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 22:18:11.893670 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 22:18:11.894008 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=reboot'
292 22:18:17.030442 >> Command sent successfully.
293 22:18:17.032871 Returned 0 in 5 seconds
294 22:18:17.133243 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 22:18:17.133853 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 22:18:17.133956 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 22:18:17.134047 Setting prompt string to 'Starting depthcharge on Spherion...'
299 22:18:17.134114 Changing prompt to 'Starting depthcharge on Spherion...'
300 22:18:17.134186 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 22:18:17.134447 [Enter `^Ec?' for help]
302 22:18:17.309298
303 22:18:17.309483
304 22:18:17.309626 F0: 102B 0000
305 22:18:17.309717
306 22:18:17.309780 F3: 1001 0000 [0200]
307 22:18:17.312693
308 22:18:17.312766 F3: 1001 0000
309 22:18:17.312829
310 22:18:17.312889 F7: 102D 0000
311 22:18:17.312964
312 22:18:17.316074 F1: 0000 0000
313 22:18:17.316175
314 22:18:17.316270 V0: 0000 0000 [0001]
315 22:18:17.316361
316 22:18:17.319702 00: 0007 8000
317 22:18:17.319805
318 22:18:17.319894 01: 0000 0000
319 22:18:17.319992
320 22:18:17.323405 BP: 0C00 0209 [0000]
321 22:18:17.323508
322 22:18:17.323598 G0: 1182 0000
323 22:18:17.323692
324 22:18:17.323781 EC: 0000 0021 [4000]
325 22:18:17.326389
326 22:18:17.326492 S7: 0000 0000 [0000]
327 22:18:17.326580
328 22:18:17.329907 CC: 0000 0000 [0001]
329 22:18:17.330013
330 22:18:17.330102 T0: 0000 0040 [010F]
331 22:18:17.330198
332 22:18:17.330287 Jump to BL
333 22:18:17.330373
334 22:18:17.356587
335 22:18:17.356712
336 22:18:17.356809
337 22:18:17.364592 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 22:18:17.367934 ARM64: Exception handlers installed.
339 22:18:17.371896 ARM64: Testing exception
340 22:18:17.371996 ARM64: Done test exception
341 22:18:17.381711 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 22:18:17.392249 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 22:18:17.398870 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 22:18:17.408864 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 22:18:17.415487 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 22:18:17.422327 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 22:18:17.433659 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 22:18:17.439889 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 22:18:17.458862 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 22:18:17.462300 WDT: Last reset was cold boot
351 22:18:17.466093 SPI1(PAD0) initialized at 2873684 Hz
352 22:18:17.469016 SPI5(PAD0) initialized at 992727 Hz
353 22:18:17.472422 VBOOT: Loading verstage.
354 22:18:17.478800 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 22:18:17.482324 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 22:18:17.485428 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 22:18:17.488779 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 22:18:17.496512 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 22:18:17.503168 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 22:18:17.513767 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
361 22:18:17.513874
362 22:18:17.513973
363 22:18:17.524642 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 22:18:17.527877 ARM64: Exception handlers installed.
365 22:18:17.530784 ARM64: Testing exception
366 22:18:17.530863 ARM64: Done test exception
367 22:18:17.537765 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 22:18:17.541108 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 22:18:17.554939 Probing TPM: . done!
370 22:18:17.555026 TPM ready after 0 ms
371 22:18:17.562600 Connected to device vid:did:rid of 1ae0:0028:00
372 22:18:17.570320 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.153/cr50_v3.94_pp.113-620c9b9523
373 22:18:17.628879 Initialized TPM device CR50 revision 0
374 22:18:17.640827 tlcl_send_startup: Startup return code is 0
375 22:18:17.640929 TPM: setup succeeded
376 22:18:17.651991 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 22:18:17.661289 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 22:18:17.673322 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 22:18:17.683964 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 22:18:17.687341 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 22:18:17.691047 in-header: 03 07 00 00 08 00 00 00
382 22:18:17.694996 in-data: aa e4 47 04 13 02 00 00
383 22:18:17.695084 Chrome EC: UHEPI supported
384 22:18:17.702185 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 22:18:17.706680 in-header: 03 95 00 00 08 00 00 00
386 22:18:17.710048 in-data: 18 20 20 08 00 00 00 00
387 22:18:17.710130 Phase 1
388 22:18:17.713699 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 22:18:17.721140 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 22:18:17.729053 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 22:18:17.729138 Recovery requested (1009000e)
392 22:18:17.741468 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 22:18:17.745317 tlcl_extend: response is 0
394 22:18:17.753845 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 22:18:17.759786 tlcl_extend: response is 0
396 22:18:17.766786 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 22:18:17.786320 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
398 22:18:17.793353 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 22:18:17.793465
400 22:18:17.793594
401 22:18:17.803332 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 22:18:17.806962 ARM64: Exception handlers installed.
403 22:18:17.809502 ARM64: Testing exception
404 22:18:17.809599 ARM64: Done test exception
405 22:18:17.832048 pmic_efuse_setting: Set efuses in 11 msecs
406 22:18:17.835267 pmwrap_interface_init: Select PMIF_VLD_RDY
407 22:18:17.841737 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 22:18:17.845283 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 22:18:17.849502 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 22:18:17.856583 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 22:18:17.860599 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 22:18:17.863865 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 22:18:17.871157 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 22:18:17.874768 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 22:18:17.878647 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 22:18:17.885972 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 22:18:17.890072 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 22:18:17.893464 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 22:18:17.897158 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 22:18:17.904828 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 22:18:17.912040 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 22:18:17.915678 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 22:18:17.922949 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 22:18:17.926640 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 22:18:17.933828 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 22:18:17.937340 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 22:18:17.944647 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 22:18:17.948486 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 22:18:17.956089 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 22:18:17.959685 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 22:18:17.967287 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 22:18:17.971047 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 22:18:17.974645 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 22:18:17.982269 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 22:18:17.986249 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 22:18:17.990133 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 22:18:17.997570 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 22:18:18.001148 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 22:18:18.004149 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 22:18:18.011966 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 22:18:18.015782 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 22:18:18.023106 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 22:18:18.026923 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 22:18:18.030990 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 22:18:18.034508 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 22:18:18.038164 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 22:18:18.045314 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 22:18:18.049467 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 22:18:18.053068 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 22:18:18.056781 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 22:18:18.060452 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 22:18:18.068316 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 22:18:18.071810 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 22:18:18.075552 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 22:18:18.079385 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 22:18:18.082776 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 22:18:18.086084 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 22:18:18.094380 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 22:18:18.105376 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 22:18:18.108746 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 22:18:18.116285 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 22:18:18.123479 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 22:18:18.127708 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 22:18:18.135094 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 22:18:18.138710 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 22:18:18.145988 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x0
467 22:18:18.149753 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 22:18:18.156783 [RTC]rtc_osc_init,62: osc32con val = 0xde70
469 22:18:18.160458 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 22:18:18.169469 [RTC]rtc_get_frequency_meter,154: input=15, output=759
471 22:18:18.178556 [RTC]rtc_get_frequency_meter,154: input=23, output=941
472 22:18:18.188387 [RTC]rtc_get_frequency_meter,154: input=19, output=849
473 22:18:18.198111 [RTC]rtc_get_frequency_meter,154: input=17, output=805
474 22:18:18.207686 [RTC]rtc_get_frequency_meter,154: input=16, output=782
475 22:18:18.216818 [RTC]rtc_get_frequency_meter,154: input=16, output=783
476 22:18:18.227373 [RTC]rtc_get_frequency_meter,154: input=17, output=805
477 22:18:18.231344 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
478 22:18:18.234766 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
479 22:18:18.238990 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 22:18:18.242769 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
481 22:18:18.250067 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 22:18:18.253239 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
483 22:18:18.257449 ADC[4]: Raw value=906203 ID=7
484 22:18:18.257557 ADC[3]: Raw value=213810 ID=1
485 22:18:18.261436 RAM Code: 0x71
486 22:18:18.265654 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 22:18:18.269196 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 22:18:18.276848 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 22:18:18.284759 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 22:18:18.287995 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 22:18:18.291595 in-header: 03 07 00 00 08 00 00 00
492 22:18:18.295400 in-data: aa e4 47 04 13 02 00 00
493 22:18:18.295484 Chrome EC: UHEPI supported
494 22:18:18.302851 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 22:18:18.307220 in-header: 03 95 00 00 08 00 00 00
496 22:18:18.311104 in-data: 18 20 20 08 00 00 00 00
497 22:18:18.315009 MRC: failed to locate region type 0.
498 22:18:18.321772 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 22:18:18.325344 DRAM-K: Running full calibration
500 22:18:18.328968 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 22:18:18.332942 header.status = 0x0
502 22:18:18.336352 header.version = 0x6 (expected: 0x6)
503 22:18:18.340228 header.size = 0xd00 (expected: 0xd00)
504 22:18:18.340313 header.flags = 0x0
505 22:18:18.347524 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 22:18:18.365433 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
507 22:18:18.373078 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 22:18:18.373191 dram_init: ddr_geometry: 2
509 22:18:18.377219 [EMI] MDL number = 2
510 22:18:18.377320 [EMI] Get MDL freq = 0
511 22:18:18.380722 dram_init: ddr_type: 0
512 22:18:18.384441 is_discrete_lpddr4: 1
513 22:18:18.384543 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 22:18:18.384635
515 22:18:18.387922
516 22:18:18.388022 [Bian_co] ETT version 0.0.0.1
517 22:18:18.392222 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 22:18:18.392307
519 22:18:18.399297 dramc_set_vcore_voltage set vcore to 650000
520 22:18:18.399409 Read voltage for 800, 4
521 22:18:18.399505 Vio18 = 0
522 22:18:18.403205 Vcore = 650000
523 22:18:18.403308 Vdram = 0
524 22:18:18.403405 Vddq = 0
525 22:18:18.403497 Vmddr = 0
526 22:18:18.407011 dram_init: config_dvfs: 1
527 22:18:18.410970 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 22:18:18.418262 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 22:18:18.421655 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
530 22:18:18.425468 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
531 22:18:18.428933 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
532 22:18:18.432963 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
533 22:18:18.436212 MEM_TYPE=3, freq_sel=18
534 22:18:18.436297 sv_algorithm_assistance_LP4_1600
535 22:18:18.442892 ============ PULL DRAM RESETB DOWN ============
536 22:18:18.446474 ========== PULL DRAM RESETB DOWN end =========
537 22:18:18.449917 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 22:18:18.453118 ===================================
539 22:18:18.457031 LPDDR4 DRAM CONFIGURATION
540 22:18:18.461033 ===================================
541 22:18:18.461118 EX_ROW_EN[0] = 0x0
542 22:18:18.464608 EX_ROW_EN[1] = 0x0
543 22:18:18.464696 LP4Y_EN = 0x0
544 22:18:18.468117 WORK_FSP = 0x0
545 22:18:18.468215 WL = 0x2
546 22:18:18.471581 RL = 0x2
547 22:18:18.471719 BL = 0x2
548 22:18:18.475767 RPST = 0x0
549 22:18:18.475851 RD_PRE = 0x0
550 22:18:18.475918 WR_PRE = 0x1
551 22:18:18.478776 WR_PST = 0x0
552 22:18:18.482445 DBI_WR = 0x0
553 22:18:18.482530 DBI_RD = 0x0
554 22:18:18.485991 OTF = 0x1
555 22:18:18.488968 ===================================
556 22:18:18.492495 ===================================
557 22:18:18.492579 ANA top config
558 22:18:18.495626 ===================================
559 22:18:18.499411 DLL_ASYNC_EN = 0
560 22:18:18.499513 ALL_SLAVE_EN = 1
561 22:18:18.502286 NEW_RANK_MODE = 1
562 22:18:18.505687 DLL_IDLE_MODE = 1
563 22:18:18.509345 LP45_APHY_COMB_EN = 1
564 22:18:18.512830 TX_ODT_DIS = 1
565 22:18:18.512916 NEW_8X_MODE = 1
566 22:18:18.516881 ===================================
567 22:18:18.520087 ===================================
568 22:18:18.523546 data_rate = 1600
569 22:18:18.526493 CKR = 1
570 22:18:18.530034 DQ_P2S_RATIO = 8
571 22:18:18.533665 ===================================
572 22:18:18.533749 CA_P2S_RATIO = 8
573 22:18:18.536686 DQ_CA_OPEN = 0
574 22:18:18.540319 DQ_SEMI_OPEN = 0
575 22:18:18.543757 CA_SEMI_OPEN = 0
576 22:18:18.546880 CA_FULL_RATE = 0
577 22:18:18.546968 DQ_CKDIV4_EN = 1
578 22:18:18.549994 CA_CKDIV4_EN = 1
579 22:18:18.553470 CA_PREDIV_EN = 0
580 22:18:18.557173 PH8_DLY = 0
581 22:18:18.560147 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 22:18:18.563726 DQ_AAMCK_DIV = 4
583 22:18:18.563826 CA_AAMCK_DIV = 4
584 22:18:18.566845 CA_ADMCK_DIV = 4
585 22:18:18.570194 DQ_TRACK_CA_EN = 0
586 22:18:18.573936 CA_PICK = 800
587 22:18:18.577384 CA_MCKIO = 800
588 22:18:18.577525 MCKIO_SEMI = 0
589 22:18:18.581767 PLL_FREQ = 3068
590 22:18:18.585182 DQ_UI_PI_RATIO = 32
591 22:18:18.588932 CA_UI_PI_RATIO = 0
592 22:18:18.592683 ===================================
593 22:18:18.592784 ===================================
594 22:18:18.596742 memory_type:LPDDR4
595 22:18:18.600282 GP_NUM : 10
596 22:18:18.600394 SRAM_EN : 1
597 22:18:18.603998 MD32_EN : 0
598 22:18:18.607469 ===================================
599 22:18:18.607582 [ANA_INIT] >>>>>>>>>>>>>>
600 22:18:18.611565 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 22:18:18.614842 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 22:18:18.618095 ===================================
603 22:18:18.621278 data_rate = 1600,PCW = 0X7600
604 22:18:18.624862 ===================================
605 22:18:18.627960 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 22:18:18.631257 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 22:18:18.637959 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 22:18:18.641314 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 22:18:18.647962 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 22:18:18.651146 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 22:18:18.651255 [ANA_INIT] flow start
612 22:18:18.654614 [ANA_INIT] PLL >>>>>>>>
613 22:18:18.658427 [ANA_INIT] PLL <<<<<<<<
614 22:18:18.658511 [ANA_INIT] MIDPI >>>>>>>>
615 22:18:18.661507 [ANA_INIT] MIDPI <<<<<<<<
616 22:18:18.664988 [ANA_INIT] DLL >>>>>>>>
617 22:18:18.665074 [ANA_INIT] flow end
618 22:18:18.668050 ============ LP4 DIFF to SE enter ============
619 22:18:18.675224 ============ LP4 DIFF to SE exit ============
620 22:18:18.675309 [ANA_INIT] <<<<<<<<<<<<<
621 22:18:18.678065 [Flow] Enable top DCM control >>>>>
622 22:18:18.681472 [Flow] Enable top DCM control <<<<<
623 22:18:18.685049 Enable DLL master slave shuffle
624 22:18:18.691714 ==============================================================
625 22:18:18.691799 Gating Mode config
626 22:18:18.698281 ==============================================================
627 22:18:18.701414 Config description:
628 22:18:18.711868 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 22:18:18.714868 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 22:18:18.722162 SELPH_MODE 0: By rank 1: By Phase
631 22:18:18.728608 ==============================================================
632 22:18:18.728698 GAT_TRACK_EN = 1
633 22:18:18.731520 RX_GATING_MODE = 2
634 22:18:18.735015 RX_GATING_TRACK_MODE = 2
635 22:18:18.738633 SELPH_MODE = 1
636 22:18:18.741502 PICG_EARLY_EN = 1
637 22:18:18.745074 VALID_LAT_VALUE = 1
638 22:18:18.751550 ==============================================================
639 22:18:18.754926 Enter into Gating configuration >>>>
640 22:18:18.758736 Exit from Gating configuration <<<<
641 22:18:18.761710 Enter into DVFS_PRE_config >>>>>
642 22:18:18.772247 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 22:18:18.775097 Exit from DVFS_PRE_config <<<<<
644 22:18:18.778514 Enter into PICG configuration >>>>
645 22:18:18.781857 Exit from PICG configuration <<<<
646 22:18:18.781942 [RX_INPUT] configuration >>>>>
647 22:18:18.785230 [RX_INPUT] configuration <<<<<
648 22:18:18.792618 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 22:18:18.795536 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 22:18:18.802567 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 22:18:18.808662 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 22:18:18.815850 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 22:18:18.822400 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 22:18:18.825428 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 22:18:18.829090 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 22:18:18.832418 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 22:18:18.838898 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 22:18:18.842260 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 22:18:18.845439 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 22:18:18.848867 ===================================
661 22:18:18.852045 LPDDR4 DRAM CONFIGURATION
662 22:18:18.855558 ===================================
663 22:18:18.859015 EX_ROW_EN[0] = 0x0
664 22:18:18.859099 EX_ROW_EN[1] = 0x0
665 22:18:18.862015 LP4Y_EN = 0x0
666 22:18:18.862099 WORK_FSP = 0x0
667 22:18:18.865396 WL = 0x2
668 22:18:18.865480 RL = 0x2
669 22:18:18.868868 BL = 0x2
670 22:18:18.868987 RPST = 0x0
671 22:18:18.872631 RD_PRE = 0x0
672 22:18:18.872715 WR_PRE = 0x1
673 22:18:18.875649 WR_PST = 0x0
674 22:18:18.875732 DBI_WR = 0x0
675 22:18:18.878718 DBI_RD = 0x0
676 22:18:18.878802 OTF = 0x1
677 22:18:18.882454 ===================================
678 22:18:18.885771 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 22:18:18.892639 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 22:18:18.895756 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 22:18:18.899374 ===================================
682 22:18:18.902109 LPDDR4 DRAM CONFIGURATION
683 22:18:18.905551 ===================================
684 22:18:18.905648 EX_ROW_EN[0] = 0x10
685 22:18:18.909317 EX_ROW_EN[1] = 0x0
686 22:18:18.912245 LP4Y_EN = 0x0
687 22:18:18.912345 WORK_FSP = 0x0
688 22:18:18.915755 WL = 0x2
689 22:18:18.915839 RL = 0x2
690 22:18:18.918907 BL = 0x2
691 22:18:18.918992 RPST = 0x0
692 22:18:18.922418 RD_PRE = 0x0
693 22:18:18.922501 WR_PRE = 0x1
694 22:18:18.925782 WR_PST = 0x0
695 22:18:18.925865 DBI_WR = 0x0
696 22:18:18.928778 DBI_RD = 0x0
697 22:18:18.928861 OTF = 0x1
698 22:18:18.932512 ===================================
699 22:18:18.938850 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 22:18:18.942777 nWR fixed to 40
701 22:18:18.946723 [ModeRegInit_LP4] CH0 RK0
702 22:18:18.946806 [ModeRegInit_LP4] CH0 RK1
703 22:18:18.949381 [ModeRegInit_LP4] CH1 RK0
704 22:18:18.952793 [ModeRegInit_LP4] CH1 RK1
705 22:18:18.952880 match AC timing 13
706 22:18:18.959816 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 22:18:18.963454 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 22:18:18.966066 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 22:18:18.973284 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 22:18:18.976591 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 22:18:18.976675 [EMI DOE] emi_dcm 0
712 22:18:18.983230 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 22:18:18.983313 ==
714 22:18:18.986205 Dram Type= 6, Freq= 0, CH_0, rank 0
715 22:18:18.989780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 22:18:18.989865 ==
717 22:18:18.996345 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 22:18:18.999687 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 22:18:19.010354 [CA 0] Center 36 (6~67) winsize 62
720 22:18:19.013444 [CA 1] Center 36 (6~67) winsize 62
721 22:18:19.016893 [CA 2] Center 34 (4~65) winsize 62
722 22:18:19.020574 [CA 3] Center 34 (4~64) winsize 61
723 22:18:19.024244 [CA 4] Center 33 (3~64) winsize 62
724 22:18:19.027250 [CA 5] Center 32 (2~62) winsize 61
725 22:18:19.027333
726 22:18:19.030692 [CmdBusTrainingLP45] Vref(ca) range 1: 34
727 22:18:19.030776
728 22:18:19.033904 [CATrainingPosCal] consider 1 rank data
729 22:18:19.037424 u2DelayCellTimex100 = 270/100 ps
730 22:18:19.040462 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
731 22:18:19.044088 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
732 22:18:19.050304 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
733 22:18:19.053810 CA3 delay=34 (4~64),Diff = 2 PI (14 cell)
734 22:18:19.057158 CA4 delay=33 (3~64),Diff = 1 PI (7 cell)
735 22:18:19.060356 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
736 22:18:19.060440
737 22:18:19.063977 CA PerBit enable=1, Macro0, CA PI delay=32
738 22:18:19.064068
739 22:18:19.067163 [CBTSetCACLKResult] CA Dly = 32
740 22:18:19.067237 CS Dly: 4 (0~35)
741 22:18:19.067308 ==
742 22:18:19.070695 Dram Type= 6, Freq= 0, CH_0, rank 1
743 22:18:19.077646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 22:18:19.077750 ==
745 22:18:19.080606 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 22:18:19.087320 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 22:18:19.096724 [CA 0] Center 36 (6~67) winsize 62
748 22:18:19.100206 [CA 1] Center 36 (6~67) winsize 62
749 22:18:19.103101 [CA 2] Center 34 (4~64) winsize 61
750 22:18:19.106533 [CA 3] Center 33 (3~64) winsize 62
751 22:18:19.109898 [CA 4] Center 32 (2~63) winsize 62
752 22:18:19.113704 [CA 5] Center 32 (2~63) winsize 62
753 22:18:19.113810
754 22:18:19.116677 [CmdBusTrainingLP45] Vref(ca) range 1: 32
755 22:18:19.116776
756 22:18:19.120141 [CATrainingPosCal] consider 2 rank data
757 22:18:19.123148 u2DelayCellTimex100 = 270/100 ps
758 22:18:19.126916 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
759 22:18:19.129892 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
760 22:18:19.136995 CA2 delay=34 (4~64),Diff = 2 PI (14 cell)
761 22:18:19.139919 CA3 delay=34 (4~64),Diff = 2 PI (14 cell)
762 22:18:19.143162 CA4 delay=33 (3~63),Diff = 1 PI (7 cell)
763 22:18:19.146743 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
764 22:18:19.146828
765 22:18:19.150395 CA PerBit enable=1, Macro0, CA PI delay=32
766 22:18:19.150480
767 22:18:19.153327 [CBTSetCACLKResult] CA Dly = 32
768 22:18:19.153411 CS Dly: 4 (0~36)
769 22:18:19.153478
770 22:18:19.156752 ----->DramcWriteLeveling(PI) begin...
771 22:18:19.161016 ==
772 22:18:19.161104 Dram Type= 6, Freq= 0, CH_0, rank 0
773 22:18:19.165300 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 22:18:19.165386 ==
775 22:18:19.168407 Write leveling (Byte 0): 35 => 35
776 22:18:19.171853 Write leveling (Byte 1): 29 => 29
777 22:18:19.175437 DramcWriteLeveling(PI) end<-----
778 22:18:19.175521
779 22:18:19.175588 ==
780 22:18:19.178541 Dram Type= 6, Freq= 0, CH_0, rank 0
781 22:18:19.181833 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 22:18:19.181918 ==
783 22:18:19.186279 [Gating] SW mode calibration
784 22:18:19.192303 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 22:18:19.199157 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 22:18:19.202665 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 22:18:19.205762 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
788 22:18:19.212556 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
789 22:18:19.215960 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 22:18:19.219630 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 22:18:19.226429 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 22:18:19.229278 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 22:18:19.232790 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 22:18:19.239048 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 22:18:19.242667 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 22:18:19.246263 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 22:18:19.249363 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 22:18:19.255891 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 22:18:19.259570 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 22:18:19.263199 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 22:18:19.269530 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 22:18:19.272749 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
803 22:18:19.276574 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
804 22:18:19.282818 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
805 22:18:19.286103 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 22:18:19.289448 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 22:18:19.296298 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 22:18:19.299638 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 22:18:19.302860 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 22:18:19.309461 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 22:18:19.312968 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 22:18:19.316277 0 9 8 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
813 22:18:19.319767 0 9 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
814 22:18:19.326368 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 22:18:19.330021 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 22:18:19.332850 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 22:18:19.340219 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 22:18:19.342974 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 22:18:19.346724 0 10 4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
820 22:18:19.353177 0 10 8 | B1->B0 | 2e2e 2424 | 1 0 | (1 1) (1 0)
821 22:18:19.356922 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
822 22:18:19.359828 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 22:18:19.366966 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 22:18:19.370097 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 22:18:19.373212 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 22:18:19.380283 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 22:18:19.383589 0 11 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
828 22:18:19.386799 0 11 8 | B1->B0 | 2a2a 3d3c | 0 1 | (0 0) (1 1)
829 22:18:19.389828 0 11 12 | B1->B0 | 4444 4646 | 1 0 | (0 0) (0 0)
830 22:18:19.396785 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 22:18:19.400051 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 22:18:19.403471 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 22:18:19.410321 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 22:18:19.413472 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 22:18:19.416940 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
836 22:18:19.423478 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
837 22:18:19.426902 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
838 22:18:19.430410 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 22:18:19.436890 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 22:18:19.440468 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 22:18:19.443903 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 22:18:19.449933 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 22:18:19.453423 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 22:18:19.457036 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 22:18:19.460302 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 22:18:19.467350 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 22:18:19.470166 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 22:18:19.473799 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 22:18:19.480929 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 22:18:19.483761 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 22:18:19.487147 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
852 22:18:19.493826 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
853 22:18:19.493941 Total UI for P1: 0, mck2ui 16
854 22:18:19.500398 best dqsien dly found for B0: ( 0, 14, 4)
855 22:18:19.503723 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
856 22:18:19.506958 Total UI for P1: 0, mck2ui 16
857 22:18:19.510756 best dqsien dly found for B1: ( 0, 14, 8)
858 22:18:19.514410 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
859 22:18:19.517254 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
860 22:18:19.517360
861 22:18:19.520695 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
862 22:18:19.524140 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
863 22:18:19.527328 [Gating] SW calibration Done
864 22:18:19.527435 ==
865 22:18:19.530807 Dram Type= 6, Freq= 0, CH_0, rank 0
866 22:18:19.533977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
867 22:18:19.534088 ==
868 22:18:19.537488 RX Vref Scan: 0
869 22:18:19.537641
870 22:18:19.537735 RX Vref 0 -> 0, step: 1
871 22:18:19.537834
872 22:18:19.540802 RX Delay -130 -> 252, step: 16
873 22:18:19.547266 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
874 22:18:19.550714 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
875 22:18:19.554237 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
876 22:18:19.557207 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
877 22:18:19.560794 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
878 22:18:19.563967 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
879 22:18:19.571134 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
880 22:18:19.574451 iDelay=222, Bit 7, Center 109 (-2 ~ 221) 224
881 22:18:19.577544 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
882 22:18:19.580811 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
883 22:18:19.584328 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
884 22:18:19.591182 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
885 22:18:19.594000 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
886 22:18:19.597450 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
887 22:18:19.600861 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
888 22:18:19.607649 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
889 22:18:19.607761 ==
890 22:18:19.610810 Dram Type= 6, Freq= 0, CH_0, rank 0
891 22:18:19.614266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
892 22:18:19.614372 ==
893 22:18:19.614477 DQS Delay:
894 22:18:19.617667 DQS0 = 0, DQS1 = 0
895 22:18:19.617767 DQM Delay:
896 22:18:19.620964 DQM0 = 91, DQM1 = 83
897 22:18:19.621070 DQ Delay:
898 22:18:19.623902 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
899 22:18:19.627604 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =109
900 22:18:19.630621 DQ8 =77, DQ9 =77, DQ10 =77, DQ11 =77
901 22:18:19.634209 DQ12 =85, DQ13 =93, DQ14 =93, DQ15 =85
902 22:18:19.634311
903 22:18:19.634403
904 22:18:19.634493 ==
905 22:18:19.637784 Dram Type= 6, Freq= 0, CH_0, rank 0
906 22:18:19.641024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
907 22:18:19.641125 ==
908 22:18:19.641219
909 22:18:19.641309
910 22:18:19.644211 TX Vref Scan disable
911 22:18:19.647752 == TX Byte 0 ==
912 22:18:19.650757 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
913 22:18:19.653889 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
914 22:18:19.657540 == TX Byte 1 ==
915 22:18:19.661204 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
916 22:18:19.664048 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
917 22:18:19.664152 ==
918 22:18:19.667914 Dram Type= 6, Freq= 0, CH_0, rank 0
919 22:18:19.674247 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
920 22:18:19.674352 ==
921 22:18:19.686021 TX Vref=22, minBit 8, minWin=27, winSum=445
922 22:18:19.689614 TX Vref=24, minBit 4, minWin=28, winSum=453
923 22:18:19.692768 TX Vref=26, minBit 4, minWin=28, winSum=454
924 22:18:19.696408 TX Vref=28, minBit 5, minWin=28, winSum=457
925 22:18:19.699887 TX Vref=30, minBit 5, minWin=28, winSum=458
926 22:18:19.703114 TX Vref=32, minBit 1, minWin=28, winSum=451
927 22:18:19.709586 [TxChooseVref] Worse bit 5, Min win 28, Win sum 458, Final Vref 30
928 22:18:19.709697
929 22:18:19.713154 Final TX Range 1 Vref 30
930 22:18:19.713254
931 22:18:19.713355 ==
932 22:18:19.716418 Dram Type= 6, Freq= 0, CH_0, rank 0
933 22:18:19.719654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 22:18:19.719756 ==
935 22:18:19.719857
936 22:18:19.719951
937 22:18:19.723096 TX Vref Scan disable
938 22:18:19.726606 == TX Byte 0 ==
939 22:18:19.730222 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
940 22:18:19.732980 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
941 22:18:19.736902 == TX Byte 1 ==
942 22:18:19.740506 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
943 22:18:19.743347 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
944 22:18:19.743456
945 22:18:19.746824 [DATLAT]
946 22:18:19.746933 Freq=800, CH0 RK0
947 22:18:19.747031
948 22:18:19.750105 DATLAT Default: 0xa
949 22:18:19.750213 0, 0xFFFF, sum = 0
950 22:18:19.753521 1, 0xFFFF, sum = 0
951 22:18:19.753649 2, 0xFFFF, sum = 0
952 22:18:19.756600 3, 0xFFFF, sum = 0
953 22:18:19.756704 4, 0xFFFF, sum = 0
954 22:18:19.760112 5, 0xFFFF, sum = 0
955 22:18:19.760219 6, 0xFFFF, sum = 0
956 22:18:19.763640 7, 0xFFFF, sum = 0
957 22:18:19.763744 8, 0xFFFF, sum = 0
958 22:18:19.766651 9, 0x0, sum = 1
959 22:18:19.766753 10, 0x0, sum = 2
960 22:18:19.770205 11, 0x0, sum = 3
961 22:18:19.770315 12, 0x0, sum = 4
962 22:18:19.773455 best_step = 10
963 22:18:19.773596
964 22:18:19.773690 ==
965 22:18:19.776542 Dram Type= 6, Freq= 0, CH_0, rank 0
966 22:18:19.780113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
967 22:18:19.780214 ==
968 22:18:19.783535 RX Vref Scan: 1
969 22:18:19.783634
970 22:18:19.783728 Set Vref Range= 32 -> 127
971 22:18:19.783817
972 22:18:19.786399 RX Vref 32 -> 127, step: 1
973 22:18:19.786497
974 22:18:19.790123 RX Delay -79 -> 252, step: 8
975 22:18:19.790219
976 22:18:19.793611 Set Vref, RX VrefLevel [Byte0]: 32
977 22:18:19.796565 [Byte1]: 32
978 22:18:19.796666
979 22:18:19.800305 Set Vref, RX VrefLevel [Byte0]: 33
980 22:18:19.803328 [Byte1]: 33
981 22:18:19.803426
982 22:18:19.806794 Set Vref, RX VrefLevel [Byte0]: 34
983 22:18:19.810217 [Byte1]: 34
984 22:18:19.814035
985 22:18:19.816970 Set Vref, RX VrefLevel [Byte0]: 35
986 22:18:19.817069 [Byte1]: 35
987 22:18:19.822162
988 22:18:19.822277 Set Vref, RX VrefLevel [Byte0]: 36
989 22:18:19.825814 [Byte1]: 36
990 22:18:19.829147
991 22:18:19.829293 Set Vref, RX VrefLevel [Byte0]: 37
992 22:18:19.832718 [Byte1]: 37
993 22:18:19.837222
994 22:18:19.837330 Set Vref, RX VrefLevel [Byte0]: 38
995 22:18:19.840290 [Byte1]: 38
996 22:18:19.844548
997 22:18:19.844672 Set Vref, RX VrefLevel [Byte0]: 39
998 22:18:19.847973 [Byte1]: 39
999 22:18:19.852282
1000 22:18:19.852384 Set Vref, RX VrefLevel [Byte0]: 40
1001 22:18:19.855640 [Byte1]: 40
1002 22:18:19.859081
1003 22:18:19.859188 Set Vref, RX VrefLevel [Byte0]: 41
1004 22:18:19.862383 [Byte1]: 41
1005 22:18:19.866821
1006 22:18:19.866923 Set Vref, RX VrefLevel [Byte0]: 42
1007 22:18:19.870294 [Byte1]: 42
1008 22:18:19.874484
1009 22:18:19.874587 Set Vref, RX VrefLevel [Byte0]: 43
1010 22:18:19.877560 [Byte1]: 43
1011 22:18:19.882166
1012 22:18:19.882268 Set Vref, RX VrefLevel [Byte0]: 44
1013 22:18:19.885621 [Byte1]: 44
1014 22:18:19.889530
1015 22:18:19.889646 Set Vref, RX VrefLevel [Byte0]: 45
1016 22:18:19.892682 [Byte1]: 45
1017 22:18:19.896836
1018 22:18:19.896940 Set Vref, RX VrefLevel [Byte0]: 46
1019 22:18:19.900516 [Byte1]: 46
1020 22:18:19.904883
1021 22:18:19.904986 Set Vref, RX VrefLevel [Byte0]: 47
1022 22:18:19.907756 [Byte1]: 47
1023 22:18:19.911916
1024 22:18:19.912019 Set Vref, RX VrefLevel [Byte0]: 48
1025 22:18:19.915180 [Byte1]: 48
1026 22:18:19.919639
1027 22:18:19.919740 Set Vref, RX VrefLevel [Byte0]: 49
1028 22:18:19.923045 [Byte1]: 49
1029 22:18:19.927403
1030 22:18:19.927508 Set Vref, RX VrefLevel [Byte0]: 50
1031 22:18:19.930287 [Byte1]: 50
1032 22:18:19.934914
1033 22:18:19.935017 Set Vref, RX VrefLevel [Byte0]: 51
1034 22:18:19.937974 [Byte1]: 51
1035 22:18:19.942557
1036 22:18:19.942656 Set Vref, RX VrefLevel [Byte0]: 52
1037 22:18:19.945637 [Byte1]: 52
1038 22:18:19.949975
1039 22:18:19.950053 Set Vref, RX VrefLevel [Byte0]: 53
1040 22:18:19.953667 [Byte1]: 53
1041 22:18:19.957889
1042 22:18:19.957971 Set Vref, RX VrefLevel [Byte0]: 54
1043 22:18:19.960829 [Byte1]: 54
1044 22:18:19.964843
1045 22:18:19.964924 Set Vref, RX VrefLevel [Byte0]: 55
1046 22:18:19.968148 [Byte1]: 55
1047 22:18:19.972626
1048 22:18:19.972707 Set Vref, RX VrefLevel [Byte0]: 56
1049 22:18:19.975917 [Byte1]: 56
1050 22:18:19.980108
1051 22:18:19.980213 Set Vref, RX VrefLevel [Byte0]: 57
1052 22:18:19.983514 [Byte1]: 57
1053 22:18:19.987357
1054 22:18:19.987429 Set Vref, RX VrefLevel [Byte0]: 58
1055 22:18:19.991020 [Byte1]: 58
1056 22:18:19.995276
1057 22:18:19.995363 Set Vref, RX VrefLevel [Byte0]: 59
1058 22:18:19.998345 [Byte1]: 59
1059 22:18:20.002528
1060 22:18:20.002609 Set Vref, RX VrefLevel [Byte0]: 60
1061 22:18:20.006138 [Byte1]: 60
1062 22:18:20.010339
1063 22:18:20.010484 Set Vref, RX VrefLevel [Byte0]: 61
1064 22:18:20.013687 [Byte1]: 61
1065 22:18:20.017624
1066 22:18:20.017705 Set Vref, RX VrefLevel [Byte0]: 62
1067 22:18:20.021383 [Byte1]: 62
1068 22:18:20.025301
1069 22:18:20.025384 Set Vref, RX VrefLevel [Byte0]: 63
1070 22:18:20.028836 [Byte1]: 63
1071 22:18:20.032978
1072 22:18:20.033062 Set Vref, RX VrefLevel [Byte0]: 64
1073 22:18:20.036069 [Byte1]: 64
1074 22:18:20.040227
1075 22:18:20.040310 Set Vref, RX VrefLevel [Byte0]: 65
1076 22:18:20.043559 [Byte1]: 65
1077 22:18:20.048309
1078 22:18:20.048388 Set Vref, RX VrefLevel [Byte0]: 66
1079 22:18:20.051053 [Byte1]: 66
1080 22:18:20.055562
1081 22:18:20.055640 Set Vref, RX VrefLevel [Byte0]: 67
1082 22:18:20.058640 [Byte1]: 67
1083 22:18:20.062765
1084 22:18:20.062843 Set Vref, RX VrefLevel [Byte0]: 68
1085 22:18:20.066548 [Byte1]: 68
1086 22:18:20.070699
1087 22:18:20.070773 Set Vref, RX VrefLevel [Byte0]: 69
1088 22:18:20.074105 [Byte1]: 69
1089 22:18:20.077860
1090 22:18:20.077937 Set Vref, RX VrefLevel [Byte0]: 70
1091 22:18:20.081794 [Byte1]: 70
1092 22:18:20.085914
1093 22:18:20.085992 Set Vref, RX VrefLevel [Byte0]: 71
1094 22:18:20.088773 [Byte1]: 71
1095 22:18:20.093284
1096 22:18:20.093356 Set Vref, RX VrefLevel [Byte0]: 72
1097 22:18:20.096796 [Byte1]: 72
1098 22:18:20.101131
1099 22:18:20.101207 Set Vref, RX VrefLevel [Byte0]: 73
1100 22:18:20.104262 [Byte1]: 73
1101 22:18:20.108431
1102 22:18:20.108502 Set Vref, RX VrefLevel [Byte0]: 74
1103 22:18:20.111402 [Byte1]: 74
1104 22:18:20.116187
1105 22:18:20.116255 Set Vref, RX VrefLevel [Byte0]: 75
1106 22:18:20.119654 [Byte1]: 75
1107 22:18:20.123828
1108 22:18:20.123909 Set Vref, RX VrefLevel [Byte0]: 76
1109 22:18:20.126804 [Byte1]: 76
1110 22:18:20.130942
1111 22:18:20.131024 Set Vref, RX VrefLevel [Byte0]: 77
1112 22:18:20.135032 [Byte1]: 77
1113 22:18:20.138865
1114 22:18:20.138973 Final RX Vref Byte 0 = 57 to rank0
1115 22:18:20.142137 Final RX Vref Byte 1 = 55 to rank0
1116 22:18:20.145358 Final RX Vref Byte 0 = 57 to rank1
1117 22:18:20.148470 Final RX Vref Byte 1 = 55 to rank1==
1118 22:18:20.151802 Dram Type= 6, Freq= 0, CH_0, rank 0
1119 22:18:20.158810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1120 22:18:20.158892 ==
1121 22:18:20.158957 DQS Delay:
1122 22:18:20.159017 DQS0 = 0, DQS1 = 0
1123 22:18:20.162113 DQM Delay:
1124 22:18:20.162200 DQM0 = 92, DQM1 = 85
1125 22:18:20.165217 DQ Delay:
1126 22:18:20.168720 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1127 22:18:20.168801 DQ4 =96, DQ5 =80, DQ6 =100, DQ7 =100
1128 22:18:20.172161 DQ8 =72, DQ9 =76, DQ10 =88, DQ11 =76
1129 22:18:20.178823 DQ12 =92, DQ13 =92, DQ14 =92, DQ15 =92
1130 22:18:20.178904
1131 22:18:20.178967
1132 22:18:20.185553 [DQSOSCAuto] RK0, (LSB)MR18= 0x4e44, (MSB)MR19= 0x606, tDQSOscB0 = 392 ps tDQSOscB1 = 390 ps
1133 22:18:20.189093 CH0 RK0: MR19=606, MR18=4E44
1134 22:18:20.195767 CH0_RK0: MR19=0x606, MR18=0x4E44, DQSOSC=390, MR23=63, INC=97, DEC=64
1135 22:18:20.195851
1136 22:18:20.198900 ----->DramcWriteLeveling(PI) begin...
1137 22:18:20.198988 ==
1138 22:18:20.202480 Dram Type= 6, Freq= 0, CH_0, rank 1
1139 22:18:20.206014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1140 22:18:20.206097 ==
1141 22:18:20.209221 Write leveling (Byte 0): 32 => 32
1142 22:18:20.212912 Write leveling (Byte 1): 32 => 32
1143 22:18:20.215805 DramcWriteLeveling(PI) end<-----
1144 22:18:20.215888
1145 22:18:20.215952 ==
1146 22:18:20.218983 Dram Type= 6, Freq= 0, CH_0, rank 1
1147 22:18:20.222536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1148 22:18:20.222619 ==
1149 22:18:20.225583 [Gating] SW mode calibration
1150 22:18:20.273069 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1151 22:18:20.273706 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1152 22:18:20.273966 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1153 22:18:20.274050 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1154 22:18:20.274122 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1155 22:18:20.274198 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 22:18:20.274486 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 22:18:20.274599 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 22:18:20.274729 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 22:18:20.274801 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 22:18:20.316914 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 22:18:20.317179 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 22:18:20.317549 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 22:18:20.317651 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 22:18:20.317920 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 22:18:20.318012 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 22:18:20.318279 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 22:18:20.318345 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 22:18:20.318410 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 22:18:20.318659 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1170 22:18:20.337484 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1171 22:18:20.337754 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 22:18:20.337835 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 22:18:20.337907 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 22:18:20.341096 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 22:18:20.344690 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 22:18:20.347678 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 22:18:20.351433 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 22:18:20.358098 0 9 8 | B1->B0 | 2f2f 2e2d | 0 1 | (0 0) (0 0)
1179 22:18:20.361021 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1180 22:18:20.364633 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 22:18:20.367716 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1182 22:18:20.374628 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1183 22:18:20.377792 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1184 22:18:20.381067 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1185 22:18:20.388189 0 10 4 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
1186 22:18:20.391155 0 10 8 | B1->B0 | 2626 2929 | 0 0 | (0 0) (0 0)
1187 22:18:20.394783 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 22:18:20.401852 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 22:18:20.405849 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 22:18:20.408980 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 22:18:20.412803 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 22:18:20.416901 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 22:18:20.423630 0 11 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1194 22:18:20.426525 0 11 8 | B1->B0 | 4141 3f3f | 0 1 | (0 0) (0 0)
1195 22:18:20.430519 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1196 22:18:20.434203 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 22:18:20.440820 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 22:18:20.443857 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 22:18:20.447563 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 22:18:20.454025 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1201 22:18:20.457546 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1202 22:18:20.460963 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1203 22:18:20.467581 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1204 22:18:20.470979 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 22:18:20.474320 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 22:18:20.481102 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 22:18:20.484641 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 22:18:20.487614 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 22:18:20.490888 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 22:18:20.497691 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 22:18:20.501047 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 22:18:20.504192 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 22:18:20.510761 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 22:18:20.514426 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 22:18:20.517704 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 22:18:20.524218 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 22:18:20.528025 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 22:18:20.530855 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1219 22:18:20.537737 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1220 22:18:20.537823 Total UI for P1: 0, mck2ui 16
1221 22:18:20.544449 best dqsien dly found for B0: ( 0, 14, 10)
1222 22:18:20.544530 Total UI for P1: 0, mck2ui 16
1223 22:18:20.551321 best dqsien dly found for B1: ( 0, 14, 8)
1224 22:18:20.554249 best DQS0 dly(MCK, UI, PI) = (0, 14, 10)
1225 22:18:20.557659 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1226 22:18:20.557741
1227 22:18:20.561189 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 10)
1228 22:18:20.564280 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1229 22:18:20.567954 [Gating] SW calibration Done
1230 22:18:20.568036 ==
1231 22:18:20.571013 Dram Type= 6, Freq= 0, CH_0, rank 1
1232 22:18:20.574235 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1233 22:18:20.574373 ==
1234 22:18:20.577639 RX Vref Scan: 0
1235 22:18:20.577720
1236 22:18:20.577785 RX Vref 0 -> 0, step: 1
1237 22:18:20.577844
1238 22:18:20.580900 RX Delay -130 -> 252, step: 16
1239 22:18:20.584002 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1240 22:18:20.591459 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1241 22:18:20.594386 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
1242 22:18:20.597849 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1243 22:18:20.601460 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1244 22:18:20.604178 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1245 22:18:20.611416 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1246 22:18:20.614285 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1247 22:18:20.617740 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1248 22:18:20.621225 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1249 22:18:20.624422 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1250 22:18:20.630915 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1251 22:18:20.634599 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1252 22:18:20.638220 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1253 22:18:20.641701 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1254 22:18:20.644622 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1255 22:18:20.644704 ==
1256 22:18:20.647953 Dram Type= 6, Freq= 0, CH_0, rank 1
1257 22:18:20.654558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1258 22:18:20.654666 ==
1259 22:18:20.654750 DQS Delay:
1260 22:18:20.658180 DQS0 = 0, DQS1 = 0
1261 22:18:20.658261 DQM Delay:
1262 22:18:20.658326 DQM0 = 93, DQM1 = 84
1263 22:18:20.661254 DQ Delay:
1264 22:18:20.664710 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =93
1265 22:18:20.668203 DQ4 =93, DQ5 =85, DQ6 =93, DQ7 =101
1266 22:18:20.671205 DQ8 =77, DQ9 =69, DQ10 =77, DQ11 =77
1267 22:18:20.674735 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1268 22:18:20.674816
1269 22:18:20.674879
1270 22:18:20.674938 ==
1271 22:18:20.678141 Dram Type= 6, Freq= 0, CH_0, rank 1
1272 22:18:20.681333 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1273 22:18:20.681418 ==
1274 22:18:20.681483
1275 22:18:20.681614
1276 22:18:20.685024 TX Vref Scan disable
1277 22:18:20.685114 == TX Byte 0 ==
1278 22:18:20.691063 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1279 22:18:20.694717 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1280 22:18:20.694800 == TX Byte 1 ==
1281 22:18:20.701350 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1282 22:18:20.704481 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1283 22:18:20.704563 ==
1284 22:18:20.707740 Dram Type= 6, Freq= 0, CH_0, rank 1
1285 22:18:20.711717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1286 22:18:20.711799 ==
1287 22:18:20.725522 TX Vref=22, minBit 9, minWin=27, winSum=449
1288 22:18:20.728654 TX Vref=24, minBit 1, minWin=28, winSum=454
1289 22:18:20.732091 TX Vref=26, minBit 1, minWin=28, winSum=455
1290 22:18:20.735520 TX Vref=28, minBit 7, minWin=28, winSum=456
1291 22:18:20.738561 TX Vref=30, minBit 7, minWin=28, winSum=456
1292 22:18:20.741946 TX Vref=32, minBit 10, minWin=27, winSum=453
1293 22:18:20.748695 [TxChooseVref] Worse bit 7, Min win 28, Win sum 456, Final Vref 28
1294 22:18:20.748780
1295 22:18:20.752309 Final TX Range 1 Vref 28
1296 22:18:20.752379
1297 22:18:20.752438 ==
1298 22:18:20.755326 Dram Type= 6, Freq= 0, CH_0, rank 1
1299 22:18:20.759020 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1300 22:18:20.759100 ==
1301 22:18:20.759163
1302 22:18:20.762167
1303 22:18:20.762246 TX Vref Scan disable
1304 22:18:20.765385 == TX Byte 0 ==
1305 22:18:20.768865 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1306 22:18:20.771972 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1307 22:18:20.775139 == TX Byte 1 ==
1308 22:18:20.778622 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1309 22:18:20.782058 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1310 22:18:20.782137
1311 22:18:20.785254 [DATLAT]
1312 22:18:20.785360 Freq=800, CH0 RK1
1313 22:18:20.785450
1314 22:18:20.788681 DATLAT Default: 0xa
1315 22:18:20.788760 0, 0xFFFF, sum = 0
1316 22:18:20.791968 1, 0xFFFF, sum = 0
1317 22:18:20.792066 2, 0xFFFF, sum = 0
1318 22:18:20.795444 3, 0xFFFF, sum = 0
1319 22:18:20.795526 4, 0xFFFF, sum = 0
1320 22:18:20.798823 5, 0xFFFF, sum = 0
1321 22:18:20.798904 6, 0xFFFF, sum = 0
1322 22:18:20.802251 7, 0xFFFF, sum = 0
1323 22:18:20.802359 8, 0xFFFF, sum = 0
1324 22:18:20.805360 9, 0x0, sum = 1
1325 22:18:20.805467 10, 0x0, sum = 2
1326 22:18:20.808965 11, 0x0, sum = 3
1327 22:18:20.809073 12, 0x0, sum = 4
1328 22:18:20.812255 best_step = 10
1329 22:18:20.812334
1330 22:18:20.812397 ==
1331 22:18:20.815486 Dram Type= 6, Freq= 0, CH_0, rank 1
1332 22:18:20.818732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1333 22:18:20.818812 ==
1334 22:18:20.822306 RX Vref Scan: 0
1335 22:18:20.822385
1336 22:18:20.822447 RX Vref 0 -> 0, step: 1
1337 22:18:20.822507
1338 22:18:20.825223 RX Delay -95 -> 252, step: 8
1339 22:18:20.831885 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1340 22:18:20.835375 iDelay=209, Bit 1, Center 96 (-7 ~ 200) 208
1341 22:18:20.838906 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1342 22:18:20.842423 iDelay=209, Bit 3, Center 88 (-23 ~ 200) 224
1343 22:18:20.845453 iDelay=209, Bit 4, Center 96 (-15 ~ 208) 224
1344 22:18:20.852204 iDelay=209, Bit 5, Center 88 (-23 ~ 200) 224
1345 22:18:20.855385 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1346 22:18:20.858883 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1347 22:18:20.862101 iDelay=209, Bit 8, Center 72 (-39 ~ 184) 224
1348 22:18:20.865507 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
1349 22:18:20.869270 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1350 22:18:20.875433 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1351 22:18:20.879027 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1352 22:18:20.882781 iDelay=209, Bit 13, Center 92 (-15 ~ 200) 216
1353 22:18:20.885543 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1354 22:18:20.892517 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
1355 22:18:20.892599 ==
1356 22:18:20.895717 Dram Type= 6, Freq= 0, CH_0, rank 1
1357 22:18:20.898857 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1358 22:18:20.898939 ==
1359 22:18:20.899004 DQS Delay:
1360 22:18:20.902503 DQS0 = 0, DQS1 = 0
1361 22:18:20.902602 DQM Delay:
1362 22:18:20.905630 DQM0 = 93, DQM1 = 83
1363 22:18:20.905712 DQ Delay:
1364 22:18:20.908619 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1365 22:18:20.912325 DQ4 =96, DQ5 =88, DQ6 =100, DQ7 =100
1366 22:18:20.915718 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =76
1367 22:18:20.919006 DQ12 =84, DQ13 =92, DQ14 =92, DQ15 =92
1368 22:18:20.919091
1369 22:18:20.919176
1370 22:18:20.925523 [DQSOSCAuto] RK1, (LSB)MR18= 0x4516, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 392 ps
1371 22:18:20.929470 CH0 RK1: MR19=606, MR18=4516
1372 22:18:20.935709 CH0_RK1: MR19=0x606, MR18=0x4516, DQSOSC=392, MR23=63, INC=96, DEC=64
1373 22:18:20.939005 [RxdqsGatingPostProcess] freq 800
1374 22:18:20.945453 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1375 22:18:20.945588 Pre-setting of DQS Precalculation
1376 22:18:20.952253 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1377 22:18:20.952360 ==
1378 22:18:20.955858 Dram Type= 6, Freq= 0, CH_1, rank 0
1379 22:18:20.958642 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1380 22:18:20.958744 ==
1381 22:18:20.965226 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1382 22:18:20.971927 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1383 22:18:20.980360 [CA 0] Center 36 (6~67) winsize 62
1384 22:18:20.983937 [CA 1] Center 36 (6~67) winsize 62
1385 22:18:20.986911 [CA 2] Center 35 (4~66) winsize 63
1386 22:18:20.990601 [CA 3] Center 34 (4~65) winsize 62
1387 22:18:20.993330 [CA 4] Center 34 (4~65) winsize 62
1388 22:18:20.996810 [CA 5] Center 34 (4~64) winsize 61
1389 22:18:20.996883
1390 22:18:21.000389 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1391 22:18:21.000491
1392 22:18:21.003706 [CATrainingPosCal] consider 1 rank data
1393 22:18:21.007093 u2DelayCellTimex100 = 270/100 ps
1394 22:18:21.010350 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1395 22:18:21.013664 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1396 22:18:21.020280 CA2 delay=35 (4~66),Diff = 1 PI (7 cell)
1397 22:18:21.023644 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1398 22:18:21.026755 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1399 22:18:21.030223 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1400 22:18:21.030328
1401 22:18:21.033857 CA PerBit enable=1, Macro0, CA PI delay=34
1402 22:18:21.033931
1403 22:18:21.037285 [CBTSetCACLKResult] CA Dly = 34
1404 22:18:21.037392 CS Dly: 6 (0~37)
1405 22:18:21.037494 ==
1406 22:18:21.040548 Dram Type= 6, Freq= 0, CH_1, rank 1
1407 22:18:21.047497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1408 22:18:21.047616 ==
1409 22:18:21.050558 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1410 22:18:21.057601 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1411 22:18:21.066476 [CA 0] Center 36 (6~67) winsize 62
1412 22:18:21.070247 [CA 1] Center 37 (6~68) winsize 63
1413 22:18:21.073867 [CA 2] Center 35 (4~66) winsize 63
1414 22:18:21.077711 [CA 3] Center 34 (4~65) winsize 62
1415 22:18:21.081752 [CA 4] Center 35 (4~66) winsize 63
1416 22:18:21.085522 [CA 5] Center 34 (4~65) winsize 62
1417 22:18:21.085656
1418 22:18:21.088492 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1419 22:18:21.088593
1420 22:18:21.092758 [CATrainingPosCal] consider 2 rank data
1421 22:18:21.092847 u2DelayCellTimex100 = 270/100 ps
1422 22:18:21.096224 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1423 22:18:21.099775 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1424 22:18:21.106879 CA2 delay=35 (4~66),Diff = 1 PI (7 cell)
1425 22:18:21.110079 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1426 22:18:21.112909 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1427 22:18:21.116247 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1428 22:18:21.116345
1429 22:18:21.119679 CA PerBit enable=1, Macro0, CA PI delay=34
1430 22:18:21.119777
1431 22:18:21.123172 [CBTSetCACLKResult] CA Dly = 34
1432 22:18:21.123259 CS Dly: 6 (0~38)
1433 22:18:21.123325
1434 22:18:21.126482 ----->DramcWriteLeveling(PI) begin...
1435 22:18:21.126579 ==
1436 22:18:21.130135 Dram Type= 6, Freq= 0, CH_1, rank 0
1437 22:18:21.136951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1438 22:18:21.137056 ==
1439 22:18:21.140271 Write leveling (Byte 0): 27 => 27
1440 22:18:21.143699 Write leveling (Byte 1): 27 => 27
1441 22:18:21.143775 DramcWriteLeveling(PI) end<-----
1442 22:18:21.143842
1443 22:18:21.146821 ==
1444 22:18:21.150215 Dram Type= 6, Freq= 0, CH_1, rank 0
1445 22:18:21.153543 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1446 22:18:21.153661 ==
1447 22:18:21.156720 [Gating] SW mode calibration
1448 22:18:21.163243 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1449 22:18:21.166628 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1450 22:18:21.173345 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1451 22:18:21.176466 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1452 22:18:21.179861 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 22:18:21.186874 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 22:18:21.190020 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 22:18:21.193103 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 22:18:21.200095 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 22:18:21.203225 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 22:18:21.206699 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 22:18:21.213477 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 22:18:21.216385 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 22:18:21.219896 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 22:18:21.223438 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 22:18:21.229723 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 22:18:21.233418 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 22:18:21.237094 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 22:18:21.243215 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1467 22:18:21.246784 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 22:18:21.250522 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1469 22:18:21.256657 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 22:18:21.260340 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 22:18:21.263559 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 22:18:21.270260 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 22:18:21.273883 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 22:18:21.276731 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 22:18:21.283993 0 9 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (1 1)
1476 22:18:21.286848 0 9 8 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
1477 22:18:21.290527 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1478 22:18:21.293472 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1479 22:18:21.300187 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1480 22:18:21.303566 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1481 22:18:21.307080 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1482 22:18:21.313881 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1483 22:18:21.317217 0 10 4 | B1->B0 | 3131 2d2d | 0 0 | (0 1) (0 0)
1484 22:18:21.320402 0 10 8 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
1485 22:18:21.326623 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 22:18:21.330189 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 22:18:21.333428 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 22:18:21.340564 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 22:18:21.343283 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 22:18:21.346596 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 22:18:21.353310 0 11 4 | B1->B0 | 2828 3333 | 0 0 | (0 0) (0 0)
1492 22:18:21.356873 0 11 8 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
1493 22:18:21.359912 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1494 22:18:21.366857 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 22:18:21.369938 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 22:18:21.373308 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 22:18:21.380089 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 22:18:21.383231 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1499 22:18:21.386939 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1500 22:18:21.393440 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 22:18:21.397085 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 22:18:21.400662 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 22:18:21.403747 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 22:18:21.410965 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 22:18:21.413724 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 22:18:21.417378 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 22:18:21.423966 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 22:18:21.426794 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 22:18:21.430343 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 22:18:21.437287 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 22:18:21.440242 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 22:18:21.443702 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 22:18:21.450615 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 22:18:21.453586 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1515 22:18:21.457240 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1516 22:18:21.464021 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1517 22:18:21.464103 Total UI for P1: 0, mck2ui 16
1518 22:18:21.467378 best dqsien dly found for B0: ( 0, 14, 2)
1519 22:18:21.470322 Total UI for P1: 0, mck2ui 16
1520 22:18:21.473637 best dqsien dly found for B1: ( 0, 14, 2)
1521 22:18:21.476994 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1522 22:18:21.483571 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1523 22:18:21.483675
1524 22:18:21.487293 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1525 22:18:21.490771 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1526 22:18:21.493724 [Gating] SW calibration Done
1527 22:18:21.493797 ==
1528 22:18:21.497256 Dram Type= 6, Freq= 0, CH_1, rank 0
1529 22:18:21.500305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1530 22:18:21.500406 ==
1531 22:18:21.500497 RX Vref Scan: 0
1532 22:18:21.500585
1533 22:18:21.503876 RX Vref 0 -> 0, step: 1
1534 22:18:21.503948
1535 22:18:21.506912 RX Delay -130 -> 252, step: 16
1536 22:18:21.510621 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1537 22:18:21.514023 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1538 22:18:21.520710 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1539 22:18:21.524412 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1540 22:18:21.527340 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1541 22:18:21.530773 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1542 22:18:21.533687 iDelay=222, Bit 6, Center 109 (-2 ~ 221) 224
1543 22:18:21.537651 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1544 22:18:21.543894 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1545 22:18:21.547256 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1546 22:18:21.550886 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1547 22:18:21.554162 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1548 22:18:21.557569 iDelay=222, Bit 12, Center 101 (-2 ~ 205) 208
1549 22:18:21.563953 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1550 22:18:21.567443 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1551 22:18:21.570766 iDelay=222, Bit 15, Center 101 (-2 ~ 205) 208
1552 22:18:21.570868 ==
1553 22:18:21.573867 Dram Type= 6, Freq= 0, CH_1, rank 0
1554 22:18:21.577209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1555 22:18:21.580760 ==
1556 22:18:21.580865 DQS Delay:
1557 22:18:21.580958 DQS0 = 0, DQS1 = 0
1558 22:18:21.583794 DQM Delay:
1559 22:18:21.583890 DQM0 = 94, DQM1 = 89
1560 22:18:21.587245 DQ Delay:
1561 22:18:21.587318 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1562 22:18:21.591149 DQ4 =93, DQ5 =109, DQ6 =109, DQ7 =93
1563 22:18:21.593763 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =85
1564 22:18:21.597231 DQ12 =101, DQ13 =93, DQ14 =93, DQ15 =101
1565 22:18:21.600571
1566 22:18:21.600643
1567 22:18:21.600704 ==
1568 22:18:21.604180 Dram Type= 6, Freq= 0, CH_1, rank 0
1569 22:18:21.607515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1570 22:18:21.607627 ==
1571 22:18:21.607721
1572 22:18:21.607810
1573 22:18:21.611020 TX Vref Scan disable
1574 22:18:21.611131 == TX Byte 0 ==
1575 22:18:21.617703 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1576 22:18:21.620580 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1577 22:18:21.620681 == TX Byte 1 ==
1578 22:18:21.627889 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1579 22:18:21.630807 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1580 22:18:21.630907 ==
1581 22:18:21.634675 Dram Type= 6, Freq= 0, CH_1, rank 0
1582 22:18:21.637493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1583 22:18:21.637634 ==
1584 22:18:21.651306 TX Vref=22, minBit 3, minWin=26, winSum=436
1585 22:18:21.655003 TX Vref=24, minBit 3, minWin=26, winSum=439
1586 22:18:21.658375 TX Vref=26, minBit 0, minWin=27, winSum=445
1587 22:18:21.661781 TX Vref=28, minBit 3, minWin=26, winSum=442
1588 22:18:21.665092 TX Vref=30, minBit 0, minWin=27, winSum=445
1589 22:18:21.668101 TX Vref=32, minBit 3, minWin=26, winSum=443
1590 22:18:21.674981 [TxChooseVref] Worse bit 0, Min win 27, Win sum 445, Final Vref 26
1591 22:18:21.675085
1592 22:18:21.678347 Final TX Range 1 Vref 26
1593 22:18:21.678447
1594 22:18:21.678538 ==
1595 22:18:21.681699 Dram Type= 6, Freq= 0, CH_1, rank 0
1596 22:18:21.684983 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1597 22:18:21.685084 ==
1598 22:18:21.685175
1599 22:18:21.685267
1600 22:18:21.688056 TX Vref Scan disable
1601 22:18:21.691654 == TX Byte 0 ==
1602 22:18:21.695277 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1603 22:18:21.698245 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1604 22:18:21.701451 == TX Byte 1 ==
1605 22:18:21.705232 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1606 22:18:21.708164 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1607 22:18:21.708246
1608 22:18:21.711841 [DATLAT]
1609 22:18:21.711910 Freq=800, CH1 RK0
1610 22:18:21.711976
1611 22:18:21.714913 DATLAT Default: 0xa
1612 22:18:21.714987 0, 0xFFFF, sum = 0
1613 22:18:21.718425 1, 0xFFFF, sum = 0
1614 22:18:21.718511 2, 0xFFFF, sum = 0
1615 22:18:21.722019 3, 0xFFFF, sum = 0
1616 22:18:21.722093 4, 0xFFFF, sum = 0
1617 22:18:21.725087 5, 0xFFFF, sum = 0
1618 22:18:21.725157 6, 0xFFFF, sum = 0
1619 22:18:21.728791 7, 0xFFFF, sum = 0
1620 22:18:21.728879 8, 0xFFFF, sum = 0
1621 22:18:21.731705 9, 0x0, sum = 1
1622 22:18:21.731779 10, 0x0, sum = 2
1623 22:18:21.735436 11, 0x0, sum = 3
1624 22:18:21.735510 12, 0x0, sum = 4
1625 22:18:21.735612 best_step = 10
1626 22:18:21.735701
1627 22:18:21.738670 ==
1628 22:18:21.742305 Dram Type= 6, Freq= 0, CH_1, rank 0
1629 22:18:21.745293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1630 22:18:21.745389 ==
1631 22:18:21.745487 RX Vref Scan: 1
1632 22:18:21.745616
1633 22:18:21.748861 Set Vref Range= 32 -> 127
1634 22:18:21.748965
1635 22:18:21.752391 RX Vref 32 -> 127, step: 1
1636 22:18:21.752503
1637 22:18:21.755857 RX Delay -79 -> 252, step: 8
1638 22:18:21.755959
1639 22:18:21.758756 Set Vref, RX VrefLevel [Byte0]: 32
1640 22:18:21.762112 [Byte1]: 32
1641 22:18:21.762183
1642 22:18:21.765565 Set Vref, RX VrefLevel [Byte0]: 33
1643 22:18:21.768770 [Byte1]: 33
1644 22:18:21.768849
1645 22:18:21.772104 Set Vref, RX VrefLevel [Byte0]: 34
1646 22:18:21.775395 [Byte1]: 34
1647 22:18:21.775483
1648 22:18:21.779123 Set Vref, RX VrefLevel [Byte0]: 35
1649 22:18:21.782156 [Byte1]: 35
1650 22:18:21.786102
1651 22:18:21.786207 Set Vref, RX VrefLevel [Byte0]: 36
1652 22:18:21.789418 [Byte1]: 36
1653 22:18:21.793433
1654 22:18:21.793565 Set Vref, RX VrefLevel [Byte0]: 37
1655 22:18:21.796696 [Byte1]: 37
1656 22:18:21.801262
1657 22:18:21.801358 Set Vref, RX VrefLevel [Byte0]: 38
1658 22:18:21.804279 [Byte1]: 38
1659 22:18:21.809156
1660 22:18:21.809255 Set Vref, RX VrefLevel [Byte0]: 39
1661 22:18:21.812102 [Byte1]: 39
1662 22:18:21.816353
1663 22:18:21.816464 Set Vref, RX VrefLevel [Byte0]: 40
1664 22:18:21.819550 [Byte1]: 40
1665 22:18:21.824076
1666 22:18:21.824150 Set Vref, RX VrefLevel [Byte0]: 41
1667 22:18:21.827281 [Byte1]: 41
1668 22:18:21.831464
1669 22:18:21.831535 Set Vref, RX VrefLevel [Byte0]: 42
1670 22:18:21.835087 [Byte1]: 42
1671 22:18:21.839283
1672 22:18:21.839354 Set Vref, RX VrefLevel [Byte0]: 43
1673 22:18:21.842228 [Byte1]: 43
1674 22:18:21.846468
1675 22:18:21.846540 Set Vref, RX VrefLevel [Byte0]: 44
1676 22:18:21.849995 [Byte1]: 44
1677 22:18:21.854462
1678 22:18:21.854547 Set Vref, RX VrefLevel [Byte0]: 45
1679 22:18:21.857437 [Byte1]: 45
1680 22:18:21.861364
1681 22:18:21.861487 Set Vref, RX VrefLevel [Byte0]: 46
1682 22:18:21.865236 [Byte1]: 46
1683 22:18:21.869009
1684 22:18:21.869116 Set Vref, RX VrefLevel [Byte0]: 47
1685 22:18:21.872419 [Byte1]: 47
1686 22:18:21.876642
1687 22:18:21.876752 Set Vref, RX VrefLevel [Byte0]: 48
1688 22:18:21.879987 [Byte1]: 48
1689 22:18:21.884157
1690 22:18:21.884241 Set Vref, RX VrefLevel [Byte0]: 49
1691 22:18:21.887613 [Byte1]: 49
1692 22:18:21.891911
1693 22:18:21.891993 Set Vref, RX VrefLevel [Byte0]: 50
1694 22:18:21.895075 [Byte1]: 50
1695 22:18:21.899494
1696 22:18:21.899566 Set Vref, RX VrefLevel [Byte0]: 51
1697 22:18:21.902832 [Byte1]: 51
1698 22:18:21.906813
1699 22:18:21.906883 Set Vref, RX VrefLevel [Byte0]: 52
1700 22:18:21.910462 [Byte1]: 52
1701 22:18:21.914546
1702 22:18:21.914614 Set Vref, RX VrefLevel [Byte0]: 53
1703 22:18:21.917500 [Byte1]: 53
1704 22:18:21.922003
1705 22:18:21.922073 Set Vref, RX VrefLevel [Byte0]: 54
1706 22:18:21.925062 [Byte1]: 54
1707 22:18:21.929679
1708 22:18:21.929760 Set Vref, RX VrefLevel [Byte0]: 55
1709 22:18:21.932637 [Byte1]: 55
1710 22:18:21.936953
1711 22:18:21.937025 Set Vref, RX VrefLevel [Byte0]: 56
1712 22:18:21.940362 [Byte1]: 56
1713 22:18:21.944873
1714 22:18:21.944956 Set Vref, RX VrefLevel [Byte0]: 57
1715 22:18:21.947898 [Byte1]: 57
1716 22:18:21.952600
1717 22:18:21.952681 Set Vref, RX VrefLevel [Byte0]: 58
1718 22:18:21.955201 [Byte1]: 58
1719 22:18:21.959987
1720 22:18:21.960068 Set Vref, RX VrefLevel [Byte0]: 59
1721 22:18:21.963161 [Byte1]: 59
1722 22:18:21.967279
1723 22:18:21.967362 Set Vref, RX VrefLevel [Byte0]: 60
1724 22:18:21.970578 [Byte1]: 60
1725 22:18:21.974580
1726 22:18:21.974662 Set Vref, RX VrefLevel [Byte0]: 61
1727 22:18:21.978591 [Byte1]: 61
1728 22:18:21.982274
1729 22:18:21.982356 Set Vref, RX VrefLevel [Byte0]: 62
1730 22:18:21.985441 [Byte1]: 62
1731 22:18:21.989666
1732 22:18:21.989747 Set Vref, RX VrefLevel [Byte0]: 63
1733 22:18:21.993100 [Byte1]: 63
1734 22:18:21.997567
1735 22:18:21.997649 Set Vref, RX VrefLevel [Byte0]: 64
1736 22:18:22.000762 [Byte1]: 64
1737 22:18:22.004992
1738 22:18:22.005089 Set Vref, RX VrefLevel [Byte0]: 65
1739 22:18:22.008200 [Byte1]: 65
1740 22:18:22.012939
1741 22:18:22.013018 Set Vref, RX VrefLevel [Byte0]: 66
1742 22:18:22.016079 [Byte1]: 66
1743 22:18:22.020223
1744 22:18:22.020293 Set Vref, RX VrefLevel [Byte0]: 67
1745 22:18:22.023757 [Byte1]: 67
1746 22:18:22.027888
1747 22:18:22.027957 Set Vref, RX VrefLevel [Byte0]: 68
1748 22:18:22.031260 [Byte1]: 68
1749 22:18:22.035314
1750 22:18:22.035384 Set Vref, RX VrefLevel [Byte0]: 69
1751 22:18:22.038932 [Byte1]: 69
1752 22:18:22.042974
1753 22:18:22.043057 Set Vref, RX VrefLevel [Byte0]: 70
1754 22:18:22.046097 [Byte1]: 70
1755 22:18:22.050322
1756 22:18:22.050405 Set Vref, RX VrefLevel [Byte0]: 71
1757 22:18:22.053317 [Byte1]: 71
1758 22:18:22.057846
1759 22:18:22.057927 Set Vref, RX VrefLevel [Byte0]: 72
1760 22:18:22.061439 [Byte1]: 72
1761 22:18:22.065491
1762 22:18:22.065612 Final RX Vref Byte 0 = 55 to rank0
1763 22:18:22.068601 Final RX Vref Byte 1 = 54 to rank0
1764 22:18:22.071911 Final RX Vref Byte 0 = 55 to rank1
1765 22:18:22.075743 Final RX Vref Byte 1 = 54 to rank1==
1766 22:18:22.078998 Dram Type= 6, Freq= 0, CH_1, rank 0
1767 22:18:22.085284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1768 22:18:22.085366 ==
1769 22:18:22.085431 DQS Delay:
1770 22:18:22.085490 DQS0 = 0, DQS1 = 0
1771 22:18:22.088611 DQM Delay:
1772 22:18:22.088705 DQM0 = 95, DQM1 = 90
1773 22:18:22.092260 DQ Delay:
1774 22:18:22.092341 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =92
1775 22:18:22.095586 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =92
1776 22:18:22.098991 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =84
1777 22:18:22.102240 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =100
1778 22:18:22.105942
1779 22:18:22.106049
1780 22:18:22.112429 [DQSOSCAuto] RK0, (LSB)MR18= 0x2b47, (MSB)MR19= 0x606, tDQSOscB0 = 392 ps tDQSOscB1 = 398 ps
1781 22:18:22.115565 CH1 RK0: MR19=606, MR18=2B47
1782 22:18:22.122661 CH1_RK0: MR19=0x606, MR18=0x2B47, DQSOSC=392, MR23=63, INC=96, DEC=64
1783 22:18:22.122741
1784 22:18:22.125427 ----->DramcWriteLeveling(PI) begin...
1785 22:18:22.125501 ==
1786 22:18:22.129068 Dram Type= 6, Freq= 0, CH_1, rank 1
1787 22:18:22.132468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1788 22:18:22.132543 ==
1789 22:18:22.136096 Write leveling (Byte 0): 27 => 27
1790 22:18:22.139278 Write leveling (Byte 1): 27 => 27
1791 22:18:22.142392 DramcWriteLeveling(PI) end<-----
1792 22:18:22.142470
1793 22:18:22.142534 ==
1794 22:18:22.145982 Dram Type= 6, Freq= 0, CH_1, rank 1
1795 22:18:22.149069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1796 22:18:22.149145 ==
1797 22:18:22.152763 [Gating] SW mode calibration
1798 22:18:22.159436 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1799 22:18:22.165713 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1800 22:18:22.168987 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1801 22:18:22.172810 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1802 22:18:22.179379 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1803 22:18:22.182760 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1804 22:18:22.185794 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1805 22:18:22.189325 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1806 22:18:22.195634 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1807 22:18:22.199403 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1808 22:18:22.202947 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1809 22:18:22.209279 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1810 22:18:22.212675 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 22:18:22.216291 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 22:18:22.222776 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 22:18:22.226324 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 22:18:22.229430 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 22:18:22.236300 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 22:18:22.239399 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1817 22:18:22.242784 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 1)
1818 22:18:22.249598 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 22:18:22.252617 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 22:18:22.256354 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 22:18:22.262612 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 22:18:22.266281 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 22:18:22.269244 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 22:18:22.272959 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 22:18:22.279559 0 9 4 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
1826 22:18:22.282643 0 9 8 | B1->B0 | 3434 3433 | 1 1 | (1 1) (1 1)
1827 22:18:22.286293 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1828 22:18:22.292839 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1829 22:18:22.296219 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1830 22:18:22.300189 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1831 22:18:22.306344 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1832 22:18:22.309419 0 10 0 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 0)
1833 22:18:22.312844 0 10 4 | B1->B0 | 2c2c 3232 | 0 1 | (0 0) (1 0)
1834 22:18:22.319862 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1835 22:18:22.322946 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 22:18:22.326663 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 22:18:22.332889 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 22:18:22.336309 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 22:18:22.339590 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 22:18:22.346844 0 11 0 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1841 22:18:22.350130 0 11 4 | B1->B0 | 3f3f 2c2c | 1 0 | (0 0) (0 0)
1842 22:18:22.353329 0 11 8 | B1->B0 | 4646 4141 | 0 0 | (0 0) (0 0)
1843 22:18:22.356439 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1844 22:18:22.363437 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1845 22:18:22.366823 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1846 22:18:22.370088 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1847 22:18:22.376652 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1848 22:18:22.379983 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1849 22:18:22.383160 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1850 22:18:22.389902 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1851 22:18:22.393612 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1852 22:18:22.396247 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1853 22:18:22.403286 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1854 22:18:22.406552 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1855 22:18:22.409967 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1856 22:18:22.416306 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1857 22:18:22.420041 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1858 22:18:22.423344 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 22:18:22.426450 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1860 22:18:22.433654 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 22:18:22.436517 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 22:18:22.440076 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 22:18:22.447032 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 22:18:22.449961 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 22:18:22.453368 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1866 22:18:22.456515 Total UI for P1: 0, mck2ui 16
1867 22:18:22.459802 best dqsien dly found for B0: ( 0, 14, 2)
1868 22:18:22.463332 Total UI for P1: 0, mck2ui 16
1869 22:18:22.467026 best dqsien dly found for B1: ( 0, 14, 2)
1870 22:18:22.469956 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1871 22:18:22.473232 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1872 22:18:22.473306
1873 22:18:22.480114 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1874 22:18:22.483567 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1875 22:18:22.483651 [Gating] SW calibration Done
1876 22:18:22.486751 ==
1877 22:18:22.486834 Dram Type= 6, Freq= 0, CH_1, rank 1
1878 22:18:22.493811 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1879 22:18:22.493895 ==
1880 22:18:22.493961 RX Vref Scan: 0
1881 22:18:22.494021
1882 22:18:22.496944 RX Vref 0 -> 0, step: 1
1883 22:18:22.497028
1884 22:18:22.499856 RX Delay -130 -> 252, step: 16
1885 22:18:22.503180 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1886 22:18:22.506898 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1887 22:18:22.510355 iDelay=222, Bit 2, Center 85 (-18 ~ 189) 208
1888 22:18:22.516423 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1889 22:18:22.519760 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1890 22:18:22.523266 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1891 22:18:22.526585 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1892 22:18:22.529874 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1893 22:18:22.536993 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1894 22:18:22.539909 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1895 22:18:22.543445 iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224
1896 22:18:22.546627 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1897 22:18:22.550006 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1898 22:18:22.556502 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1899 22:18:22.559885 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1900 22:18:22.563594 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1901 22:18:22.563677 ==
1902 22:18:22.566882 Dram Type= 6, Freq= 0, CH_1, rank 1
1903 22:18:22.570075 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1904 22:18:22.570160 ==
1905 22:18:22.573821 DQS Delay:
1906 22:18:22.573904 DQS0 = 0, DQS1 = 0
1907 22:18:22.573970 DQM Delay:
1908 22:18:22.576717 DQM0 = 93, DQM1 = 89
1909 22:18:22.576800 DQ Delay:
1910 22:18:22.580117 DQ0 =101, DQ1 =85, DQ2 =85, DQ3 =85
1911 22:18:22.583869 DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93
1912 22:18:22.587270 DQ8 =77, DQ9 =77, DQ10 =93, DQ11 =85
1913 22:18:22.590682 DQ12 =93, DQ13 =101, DQ14 =93, DQ15 =93
1914 22:18:22.590768
1915 22:18:22.590833
1916 22:18:22.593899 ==
1917 22:18:22.593983 Dram Type= 6, Freq= 0, CH_1, rank 1
1918 22:18:22.600400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1919 22:18:22.600483 ==
1920 22:18:22.600549
1921 22:18:22.600608
1922 22:18:22.603879 TX Vref Scan disable
1923 22:18:22.603963 == TX Byte 0 ==
1924 22:18:22.607028 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1925 22:18:22.613845 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1926 22:18:22.613928 == TX Byte 1 ==
1927 22:18:22.617535 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1928 22:18:22.624227 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1929 22:18:22.624347 ==
1930 22:18:22.627388 Dram Type= 6, Freq= 0, CH_1, rank 1
1931 22:18:22.630824 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1932 22:18:22.630909 ==
1933 22:18:22.643584 TX Vref=22, minBit 3, minWin=26, winSum=439
1934 22:18:22.647375 TX Vref=24, minBit 3, minWin=25, winSum=442
1935 22:18:22.650328 TX Vref=26, minBit 7, minWin=26, winSum=446
1936 22:18:22.653297 TX Vref=28, minBit 1, minWin=27, winSum=449
1937 22:18:22.656780 TX Vref=30, minBit 1, minWin=27, winSum=449
1938 22:18:22.660429 TX Vref=32, minBit 0, minWin=27, winSum=446
1939 22:18:22.666962 [TxChooseVref] Worse bit 1, Min win 27, Win sum 449, Final Vref 28
1940 22:18:22.667046
1941 22:18:22.670117 Final TX Range 1 Vref 28
1942 22:18:22.670201
1943 22:18:22.670267 ==
1944 22:18:22.673783 Dram Type= 6, Freq= 0, CH_1, rank 1
1945 22:18:22.676829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1946 22:18:22.676912 ==
1947 22:18:22.676978
1948 22:18:22.677039
1949 22:18:22.680587 TX Vref Scan disable
1950 22:18:22.683485 == TX Byte 0 ==
1951 22:18:22.687074 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1952 22:18:22.690474 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1953 22:18:22.693555 == TX Byte 1 ==
1954 22:18:22.697128 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1955 22:18:22.700351 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1956 22:18:22.700434
1957 22:18:22.703479 [DATLAT]
1958 22:18:22.703573 Freq=800, CH1 RK1
1959 22:18:22.703643
1960 22:18:22.707125 DATLAT Default: 0xa
1961 22:18:22.707204 0, 0xFFFF, sum = 0
1962 22:18:22.710320 1, 0xFFFF, sum = 0
1963 22:18:22.710403 2, 0xFFFF, sum = 0
1964 22:18:22.713737 3, 0xFFFF, sum = 0
1965 22:18:22.713813 4, 0xFFFF, sum = 0
1966 22:18:22.716858 5, 0xFFFF, sum = 0
1967 22:18:22.716941 6, 0xFFFF, sum = 0
1968 22:18:22.720137 7, 0xFFFF, sum = 0
1969 22:18:22.720216 8, 0xFFFF, sum = 0
1970 22:18:22.723687 9, 0x0, sum = 1
1971 22:18:22.723787 10, 0x0, sum = 2
1972 22:18:22.727063 11, 0x0, sum = 3
1973 22:18:22.727148 12, 0x0, sum = 4
1974 22:18:22.730224 best_step = 10
1975 22:18:22.730301
1976 22:18:22.730363 ==
1977 22:18:22.733395 Dram Type= 6, Freq= 0, CH_1, rank 1
1978 22:18:22.736838 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1979 22:18:22.736915 ==
1980 22:18:22.740085 RX Vref Scan: 0
1981 22:18:22.740162
1982 22:18:22.740227 RX Vref 0 -> 0, step: 1
1983 22:18:22.740289
1984 22:18:22.743682 RX Delay -79 -> 252, step: 8
1985 22:18:22.746855 iDelay=209, Bit 0, Center 104 (9 ~ 200) 192
1986 22:18:22.753839 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
1987 22:18:22.757045 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
1988 22:18:22.760690 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
1989 22:18:22.763440 iDelay=209, Bit 4, Center 96 (1 ~ 192) 192
1990 22:18:22.766962 iDelay=209, Bit 5, Center 112 (17 ~ 208) 192
1991 22:18:22.770541 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
1992 22:18:22.777064 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
1993 22:18:22.780549 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
1994 22:18:22.783624 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
1995 22:18:22.787250 iDelay=209, Bit 10, Center 96 (-7 ~ 200) 208
1996 22:18:22.790764 iDelay=209, Bit 11, Center 84 (-23 ~ 192) 216
1997 22:18:22.797298 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
1998 22:18:22.800867 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
1999 22:18:22.803916 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
2000 22:18:22.807684 iDelay=209, Bit 15, Center 96 (-7 ~ 200) 208
2001 22:18:22.807767 ==
2002 22:18:22.810594 Dram Type= 6, Freq= 0, CH_1, rank 1
2003 22:18:22.813790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2004 22:18:22.817367 ==
2005 22:18:22.817449 DQS Delay:
2006 22:18:22.817520 DQS0 = 0, DQS1 = 0
2007 22:18:22.820736 DQM Delay:
2008 22:18:22.820818 DQM0 = 98, DQM1 = 91
2009 22:18:22.823979 DQ Delay:
2010 22:18:22.824060 DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92
2011 22:18:22.827509 DQ4 =96, DQ5 =112, DQ6 =108, DQ7 =96
2012 22:18:22.830866 DQ8 =80, DQ9 =80, DQ10 =96, DQ11 =84
2013 22:18:22.834245 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =96
2014 22:18:22.837203
2015 22:18:22.837304
2016 22:18:22.844064 [DQSOSCAuto] RK1, (LSB)MR18= 0x4610, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 392 ps
2017 22:18:22.847607 CH1 RK1: MR19=606, MR18=4610
2018 22:18:22.854293 CH1_RK1: MR19=0x606, MR18=0x4610, DQSOSC=392, MR23=63, INC=96, DEC=64
2019 22:18:22.857192 [RxdqsGatingPostProcess] freq 800
2020 22:18:22.860720 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2021 22:18:22.864177 Pre-setting of DQS Precalculation
2022 22:18:22.870952 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2023 22:18:22.877884 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2024 22:18:22.884521 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2025 22:18:22.884635
2026 22:18:22.884728
2027 22:18:22.887622 [Calibration Summary] 1600 Mbps
2028 22:18:22.887724 CH 0, Rank 0
2029 22:18:22.891003 SW Impedance : PASS
2030 22:18:22.891078 DUTY Scan : NO K
2031 22:18:22.894094 ZQ Calibration : PASS
2032 22:18:22.897550 Jitter Meter : NO K
2033 22:18:22.897640 CBT Training : PASS
2034 22:18:22.900899 Write leveling : PASS
2035 22:18:22.904637 RX DQS gating : PASS
2036 22:18:22.904777 RX DQ/DQS(RDDQC) : PASS
2037 22:18:22.907685 TX DQ/DQS : PASS
2038 22:18:22.911315 RX DATLAT : PASS
2039 22:18:22.911414 RX DQ/DQS(Engine): PASS
2040 22:18:22.914427 TX OE : NO K
2041 22:18:22.914508 All Pass.
2042 22:18:22.914569
2043 22:18:22.917447 CH 0, Rank 1
2044 22:18:22.917580 SW Impedance : PASS
2045 22:18:22.921288 DUTY Scan : NO K
2046 22:18:22.924542 ZQ Calibration : PASS
2047 22:18:22.924641 Jitter Meter : NO K
2048 22:18:22.927995 CBT Training : PASS
2049 22:18:22.928091 Write leveling : PASS
2050 22:18:22.931015 RX DQS gating : PASS
2051 22:18:22.934619 RX DQ/DQS(RDDQC) : PASS
2052 22:18:22.934692 TX DQ/DQS : PASS
2053 22:18:22.937846 RX DATLAT : PASS
2054 22:18:22.941149 RX DQ/DQS(Engine): PASS
2055 22:18:22.941246 TX OE : NO K
2056 22:18:22.944637 All Pass.
2057 22:18:22.944768
2058 22:18:22.944929 CH 1, Rank 0
2059 22:18:22.947639 SW Impedance : PASS
2060 22:18:22.947735 DUTY Scan : NO K
2061 22:18:22.950990 ZQ Calibration : PASS
2062 22:18:22.954276 Jitter Meter : NO K
2063 22:18:22.954360 CBT Training : PASS
2064 22:18:22.957651 Write leveling : PASS
2065 22:18:22.961414 RX DQS gating : PASS
2066 22:18:22.961534 RX DQ/DQS(RDDQC) : PASS
2067 22:18:22.964442 TX DQ/DQS : PASS
2068 22:18:22.964583 RX DATLAT : PASS
2069 22:18:22.967914 RX DQ/DQS(Engine): PASS
2070 22:18:22.970984 TX OE : NO K
2071 22:18:22.971068 All Pass.
2072 22:18:22.971133
2073 22:18:22.971194 CH 1, Rank 1
2074 22:18:22.974729 SW Impedance : PASS
2075 22:18:22.977825 DUTY Scan : NO K
2076 22:18:22.977907 ZQ Calibration : PASS
2077 22:18:22.981247 Jitter Meter : NO K
2078 22:18:22.984561 CBT Training : PASS
2079 22:18:22.984643 Write leveling : PASS
2080 22:18:22.988118 RX DQS gating : PASS
2081 22:18:22.991317 RX DQ/DQS(RDDQC) : PASS
2082 22:18:22.991400 TX DQ/DQS : PASS
2083 22:18:22.994801 RX DATLAT : PASS
2084 22:18:22.998279 RX DQ/DQS(Engine): PASS
2085 22:18:22.998362 TX OE : NO K
2086 22:18:22.998428 All Pass.
2087 22:18:23.001073
2088 22:18:23.001187 DramC Write-DBI off
2089 22:18:23.004462 PER_BANK_REFRESH: Hybrid Mode
2090 22:18:23.004545 TX_TRACKING: ON
2091 22:18:23.008113 [GetDramInforAfterCalByMRR] Vendor 6.
2092 22:18:23.011342 [GetDramInforAfterCalByMRR] Revision 606.
2093 22:18:23.017944 [GetDramInforAfterCalByMRR] Revision 2 0.
2094 22:18:23.018027 MR0 0x3b3b
2095 22:18:23.018093 MR8 0x5151
2096 22:18:23.021060 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2097 22:18:23.021143
2098 22:18:23.024849 MR0 0x3b3b
2099 22:18:23.024931 MR8 0x5151
2100 22:18:23.028221 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2101 22:18:23.028305
2102 22:18:23.038352 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2103 22:18:23.041691 [FAST_K] Save calibration result to emmc
2104 22:18:23.044834 [FAST_K] Save calibration result to emmc
2105 22:18:23.048332 dram_init: config_dvfs: 1
2106 22:18:23.051703 dramc_set_vcore_voltage set vcore to 662500
2107 22:18:23.051806 Read voltage for 1200, 2
2108 22:18:23.055013 Vio18 = 0
2109 22:18:23.055087 Vcore = 662500
2110 22:18:23.055149 Vdram = 0
2111 22:18:23.057963 Vddq = 0
2112 22:18:23.058037 Vmddr = 0
2113 22:18:23.061461 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2114 22:18:23.068252 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2115 22:18:23.071227 MEM_TYPE=3, freq_sel=15
2116 22:18:23.074793 sv_algorithm_assistance_LP4_1600
2117 22:18:23.078522 ============ PULL DRAM RESETB DOWN ============
2118 22:18:23.081432 ========== PULL DRAM RESETB DOWN end =========
2119 22:18:23.084957 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2120 22:18:23.088116 ===================================
2121 22:18:23.091368 LPDDR4 DRAM CONFIGURATION
2122 22:18:23.095323 ===================================
2123 22:18:23.098055 EX_ROW_EN[0] = 0x0
2124 22:18:23.098168 EX_ROW_EN[1] = 0x0
2125 22:18:23.101383 LP4Y_EN = 0x0
2126 22:18:23.101480 WORK_FSP = 0x0
2127 22:18:23.105047 WL = 0x4
2128 22:18:23.105151 RL = 0x4
2129 22:18:23.108280 BL = 0x2
2130 22:18:23.108363 RPST = 0x0
2131 22:18:23.111703 RD_PRE = 0x0
2132 22:18:23.111785 WR_PRE = 0x1
2133 22:18:23.115098 WR_PST = 0x0
2134 22:18:23.115181 DBI_WR = 0x0
2135 22:18:23.118501 DBI_RD = 0x0
2136 22:18:23.118583 OTF = 0x1
2137 22:18:23.121424 ===================================
2138 22:18:23.124825 ===================================
2139 22:18:23.128325 ANA top config
2140 22:18:23.131551 ===================================
2141 22:18:23.134976 DLL_ASYNC_EN = 0
2142 22:18:23.135059 ALL_SLAVE_EN = 0
2143 22:18:23.138574 NEW_RANK_MODE = 1
2144 22:18:23.141657 DLL_IDLE_MODE = 1
2145 22:18:23.145661 LP45_APHY_COMB_EN = 1
2146 22:18:23.148547 TX_ODT_DIS = 1
2147 22:18:23.148630 NEW_8X_MODE = 1
2148 22:18:23.151405 ===================================
2149 22:18:23.154846 ===================================
2150 22:18:23.158484 data_rate = 2400
2151 22:18:23.161964 CKR = 1
2152 22:18:23.165214 DQ_P2S_RATIO = 8
2153 22:18:23.168329 ===================================
2154 22:18:23.171621 CA_P2S_RATIO = 8
2155 22:18:23.171705 DQ_CA_OPEN = 0
2156 22:18:23.175441 DQ_SEMI_OPEN = 0
2157 22:18:23.178180 CA_SEMI_OPEN = 0
2158 22:18:23.181723 CA_FULL_RATE = 0
2159 22:18:23.185241 DQ_CKDIV4_EN = 0
2160 22:18:23.188330 CA_CKDIV4_EN = 0
2161 22:18:23.188416 CA_PREDIV_EN = 0
2162 22:18:23.191973 PH8_DLY = 17
2163 22:18:23.195597 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2164 22:18:23.198663 DQ_AAMCK_DIV = 4
2165 22:18:23.202217 CA_AAMCK_DIV = 4
2166 22:18:23.205409 CA_ADMCK_DIV = 4
2167 22:18:23.205491 DQ_TRACK_CA_EN = 0
2168 22:18:23.208338 CA_PICK = 1200
2169 22:18:23.211886 CA_MCKIO = 1200
2170 22:18:23.215262 MCKIO_SEMI = 0
2171 22:18:23.218519 PLL_FREQ = 2366
2172 22:18:23.221658 DQ_UI_PI_RATIO = 32
2173 22:18:23.225088 CA_UI_PI_RATIO = 0
2174 22:18:23.228684 ===================================
2175 22:18:23.231834 ===================================
2176 22:18:23.231921 memory_type:LPDDR4
2177 22:18:23.235323 GP_NUM : 10
2178 22:18:23.238321 SRAM_EN : 1
2179 22:18:23.238404 MD32_EN : 0
2180 22:18:23.242097 ===================================
2181 22:18:23.245263 [ANA_INIT] >>>>>>>>>>>>>>
2182 22:18:23.248432 <<<<<< [CONFIGURE PHASE]: ANA_TX
2183 22:18:23.251841 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2184 22:18:23.255613 ===================================
2185 22:18:23.258344 data_rate = 2400,PCW = 0X5b00
2186 22:18:23.258455 ===================================
2187 22:18:23.265335 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2188 22:18:23.268660 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2189 22:18:23.274991 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2190 22:18:23.278876 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2191 22:18:23.282080 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2192 22:18:23.285658 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2193 22:18:23.289178 [ANA_INIT] flow start
2194 22:18:23.292200 [ANA_INIT] PLL >>>>>>>>
2195 22:18:23.292300 [ANA_INIT] PLL <<<<<<<<
2196 22:18:23.294996 [ANA_INIT] MIDPI >>>>>>>>
2197 22:18:23.298449 [ANA_INIT] MIDPI <<<<<<<<
2198 22:18:23.298523 [ANA_INIT] DLL >>>>>>>>
2199 22:18:23.301957 [ANA_INIT] DLL <<<<<<<<
2200 22:18:23.305192 [ANA_INIT] flow end
2201 22:18:23.308636 ============ LP4 DIFF to SE enter ============
2202 22:18:23.312119 ============ LP4 DIFF to SE exit ============
2203 22:18:23.315437 [ANA_INIT] <<<<<<<<<<<<<
2204 22:18:23.318443 [Flow] Enable top DCM control >>>>>
2205 22:18:23.321709 [Flow] Enable top DCM control <<<<<
2206 22:18:23.325009 Enable DLL master slave shuffle
2207 22:18:23.328825 ==============================================================
2208 22:18:23.331909 Gating Mode config
2209 22:18:23.335287 ==============================================================
2210 22:18:23.339155 Config description:
2211 22:18:23.348699 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2212 22:18:23.355351 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2213 22:18:23.358583 SELPH_MODE 0: By rank 1: By Phase
2214 22:18:23.365262 ==============================================================
2215 22:18:23.368537 GAT_TRACK_EN = 1
2216 22:18:23.372338 RX_GATING_MODE = 2
2217 22:18:23.375263 RX_GATING_TRACK_MODE = 2
2218 22:18:23.378910 SELPH_MODE = 1
2219 22:18:23.378991 PICG_EARLY_EN = 1
2220 22:18:23.382182 VALID_LAT_VALUE = 1
2221 22:18:23.388818 ==============================================================
2222 22:18:23.392325 Enter into Gating configuration >>>>
2223 22:18:23.395748 Exit from Gating configuration <<<<
2224 22:18:23.399214 Enter into DVFS_PRE_config >>>>>
2225 22:18:23.409064 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2226 22:18:23.412167 Exit from DVFS_PRE_config <<<<<
2227 22:18:23.415621 Enter into PICG configuration >>>>
2228 22:18:23.419147 Exit from PICG configuration <<<<
2229 22:18:23.422320 [RX_INPUT] configuration >>>>>
2230 22:18:23.425486 [RX_INPUT] configuration <<<<<
2231 22:18:23.429320 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2232 22:18:23.435989 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2233 22:18:23.442524 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2234 22:18:23.449406 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2235 22:18:23.452562 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2236 22:18:23.459210 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2237 22:18:23.462642 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2238 22:18:23.469300 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2239 22:18:23.472862 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2240 22:18:23.475752 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2241 22:18:23.479363 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2242 22:18:23.485812 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2243 22:18:23.489244 ===================================
2244 22:18:23.489328 LPDDR4 DRAM CONFIGURATION
2245 22:18:23.492442 ===================================
2246 22:18:23.495895 EX_ROW_EN[0] = 0x0
2247 22:18:23.499127 EX_ROW_EN[1] = 0x0
2248 22:18:23.499210 LP4Y_EN = 0x0
2249 22:18:23.502730 WORK_FSP = 0x0
2250 22:18:23.502843 WL = 0x4
2251 22:18:23.505601 RL = 0x4
2252 22:18:23.505704 BL = 0x2
2253 22:18:23.509345 RPST = 0x0
2254 22:18:23.509445 RD_PRE = 0x0
2255 22:18:23.512476 WR_PRE = 0x1
2256 22:18:23.512583 WR_PST = 0x0
2257 22:18:23.515608 DBI_WR = 0x0
2258 22:18:23.515707 DBI_RD = 0x0
2259 22:18:23.518998 OTF = 0x1
2260 22:18:23.522269 ===================================
2261 22:18:23.526168 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2262 22:18:23.528964 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2263 22:18:23.535523 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2264 22:18:23.538942 ===================================
2265 22:18:23.539045 LPDDR4 DRAM CONFIGURATION
2266 22:18:23.542408 ===================================
2267 22:18:23.545672 EX_ROW_EN[0] = 0x10
2268 22:18:23.545774 EX_ROW_EN[1] = 0x0
2269 22:18:23.549160 LP4Y_EN = 0x0
2270 22:18:23.549261 WORK_FSP = 0x0
2271 22:18:23.552240 WL = 0x4
2272 22:18:23.552343 RL = 0x4
2273 22:18:23.555951 BL = 0x2
2274 22:18:23.558923 RPST = 0x0
2275 22:18:23.559022 RD_PRE = 0x0
2276 22:18:23.562478 WR_PRE = 0x1
2277 22:18:23.562577 WR_PST = 0x0
2278 22:18:23.565664 DBI_WR = 0x0
2279 22:18:23.565765 DBI_RD = 0x0
2280 22:18:23.569326 OTF = 0x1
2281 22:18:23.572324 ===================================
2282 22:18:23.575653 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2283 22:18:23.579058 ==
2284 22:18:23.579160 Dram Type= 6, Freq= 0, CH_0, rank 0
2285 22:18:23.585562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2286 22:18:23.585643 ==
2287 22:18:23.589036 [Duty_Offset_Calibration]
2288 22:18:23.589136 B0:2 B1:1 CA:1
2289 22:18:23.589231
2290 22:18:23.592370 [DutyScan_Calibration_Flow] k_type=0
2291 22:18:23.602198
2292 22:18:23.602300 ==CLK 0==
2293 22:18:23.605432 Final CLK duty delay cell = 0
2294 22:18:23.608438 [0] MAX Duty = 5187%(X100), DQS PI = 24
2295 22:18:23.611973 [0] MIN Duty = 4875%(X100), DQS PI = 0
2296 22:18:23.612086 [0] AVG Duty = 5031%(X100)
2297 22:18:23.612177
2298 22:18:23.615002 CH0 CLK Duty spec in!! Max-Min= 312%
2299 22:18:23.622088 [DutyScan_Calibration_Flow] ====Done====
2300 22:18:23.622168
2301 22:18:23.625710 [DutyScan_Calibration_Flow] k_type=1
2302 22:18:23.639824
2303 22:18:23.639934 ==DQS 0 ==
2304 22:18:23.642773 Final DQS duty delay cell = -4
2305 22:18:23.646268 [-4] MAX Duty = 5124%(X100), DQS PI = 22
2306 22:18:23.649384 [-4] MIN Duty = 4751%(X100), DQS PI = 0
2307 22:18:23.653134 [-4] AVG Duty = 4937%(X100)
2308 22:18:23.653229
2309 22:18:23.653294 ==DQS 1 ==
2310 22:18:23.656146 Final DQS duty delay cell = -4
2311 22:18:23.659586 [-4] MAX Duty = 4969%(X100), DQS PI = 0
2312 22:18:23.662765 [-4] MIN Duty = 4844%(X100), DQS PI = 32
2313 22:18:23.666267 [-4] AVG Duty = 4906%(X100)
2314 22:18:23.666347
2315 22:18:23.669883 CH0 DQS 0 Duty spec in!! Max-Min= 373%
2316 22:18:23.669963
2317 22:18:23.672826 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2318 22:18:23.676221 [DutyScan_Calibration_Flow] ====Done====
2319 22:18:23.676301
2320 22:18:23.679326 [DutyScan_Calibration_Flow] k_type=3
2321 22:18:23.696651
2322 22:18:23.696730 ==DQM 0 ==
2323 22:18:23.700038 Final DQM duty delay cell = 0
2324 22:18:23.703521 [0] MAX Duty = 5156%(X100), DQS PI = 30
2325 22:18:23.707262 [0] MIN Duty = 4907%(X100), DQS PI = 58
2326 22:18:23.710044 [0] AVG Duty = 5031%(X100)
2327 22:18:23.710124
2328 22:18:23.710187 ==DQM 1 ==
2329 22:18:23.713259 Final DQM duty delay cell = 0
2330 22:18:23.716919 [0] MAX Duty = 5093%(X100), DQS PI = 0
2331 22:18:23.720794 [0] MIN Duty = 5031%(X100), DQS PI = 14
2332 22:18:23.720875 [0] AVG Duty = 5062%(X100)
2333 22:18:23.723542
2334 22:18:23.726692 CH0 DQM 0 Duty spec in!! Max-Min= 249%
2335 22:18:23.726811
2336 22:18:23.730224 CH0 DQM 1 Duty spec in!! Max-Min= 62%
2337 22:18:23.733754 [DutyScan_Calibration_Flow] ====Done====
2338 22:18:23.733833
2339 22:18:23.736823 [DutyScan_Calibration_Flow] k_type=2
2340 22:18:23.753150
2341 22:18:23.753233 ==DQ 0 ==
2342 22:18:23.756645 Final DQ duty delay cell = 0
2343 22:18:23.760276 [0] MAX Duty = 5062%(X100), DQS PI = 32
2344 22:18:23.763070 [0] MIN Duty = 4875%(X100), DQS PI = 62
2345 22:18:23.763184 [0] AVG Duty = 4968%(X100)
2346 22:18:23.763277
2347 22:18:23.766475 ==DQ 1 ==
2348 22:18:23.770186 Final DQ duty delay cell = 0
2349 22:18:23.773192 [0] MAX Duty = 5093%(X100), DQS PI = 24
2350 22:18:23.776831 [0] MIN Duty = 4938%(X100), DQS PI = 36
2351 22:18:23.776935 [0] AVG Duty = 5015%(X100)
2352 22:18:23.777025
2353 22:18:23.779952 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2354 22:18:23.780047
2355 22:18:23.786521 CH0 DQ 1 Duty spec in!! Max-Min= 155%
2356 22:18:23.789982 [DutyScan_Calibration_Flow] ====Done====
2357 22:18:23.790095 ==
2358 22:18:23.793121 Dram Type= 6, Freq= 0, CH_1, rank 0
2359 22:18:23.796744 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2360 22:18:23.796826 ==
2361 22:18:23.799846 [Duty_Offset_Calibration]
2362 22:18:23.799928 B0:1 B1:0 CA:0
2363 22:18:23.799992
2364 22:18:23.803262 [DutyScan_Calibration_Flow] k_type=0
2365 22:18:23.812561
2366 22:18:23.812642 ==CLK 0==
2367 22:18:23.815740 Final CLK duty delay cell = -4
2368 22:18:23.819083 [-4] MAX Duty = 5000%(X100), DQS PI = 18
2369 22:18:23.822646 [-4] MIN Duty = 4907%(X100), DQS PI = 12
2370 22:18:23.825815 [-4] AVG Duty = 4953%(X100)
2371 22:18:23.825897
2372 22:18:23.828878 CH1 CLK Duty spec in!! Max-Min= 93%
2373 22:18:23.832418 [DutyScan_Calibration_Flow] ====Done====
2374 22:18:23.832497
2375 22:18:23.835866 [DutyScan_Calibration_Flow] k_type=1
2376 22:18:23.851948
2377 22:18:23.852027 ==DQS 0 ==
2378 22:18:23.855417 Final DQS duty delay cell = 0
2379 22:18:23.858851 [0] MAX Duty = 5094%(X100), DQS PI = 24
2380 22:18:23.862077 [0] MIN Duty = 4875%(X100), DQS PI = 0
2381 22:18:23.862163 [0] AVG Duty = 4984%(X100)
2382 22:18:23.865809
2383 22:18:23.865884 ==DQS 1 ==
2384 22:18:23.869138 Final DQS duty delay cell = 0
2385 22:18:23.872300 [0] MAX Duty = 5187%(X100), DQS PI = 18
2386 22:18:23.875419 [0] MIN Duty = 4969%(X100), DQS PI = 10
2387 22:18:23.875495 [0] AVG Duty = 5078%(X100)
2388 22:18:23.879083
2389 22:18:23.881994 CH1 DQS 0 Duty spec in!! Max-Min= 219%
2390 22:18:23.882070
2391 22:18:23.885228 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2392 22:18:23.888744 [DutyScan_Calibration_Flow] ====Done====
2393 22:18:23.888839
2394 22:18:23.892337 [DutyScan_Calibration_Flow] k_type=3
2395 22:18:23.908976
2396 22:18:23.909058 ==DQM 0 ==
2397 22:18:23.912261 Final DQM duty delay cell = 0
2398 22:18:23.915695 [0] MAX Duty = 5156%(X100), DQS PI = 8
2399 22:18:23.919074 [0] MIN Duty = 5031%(X100), DQS PI = 0
2400 22:18:23.919158 [0] AVG Duty = 5093%(X100)
2401 22:18:23.919236
2402 22:18:23.922335 ==DQM 1 ==
2403 22:18:23.925420 Final DQM duty delay cell = 0
2404 22:18:23.928750 [0] MAX Duty = 5031%(X100), DQS PI = 14
2405 22:18:23.932169 [0] MIN Duty = 4907%(X100), DQS PI = 36
2406 22:18:23.932248 [0] AVG Duty = 4969%(X100)
2407 22:18:23.932336
2408 22:18:23.935596 CH1 DQM 0 Duty spec in!! Max-Min= 125%
2409 22:18:23.939448
2410 22:18:23.942652 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2411 22:18:23.945478 [DutyScan_Calibration_Flow] ====Done====
2412 22:18:23.945605
2413 22:18:23.949295 [DutyScan_Calibration_Flow] k_type=2
2414 22:18:23.965041
2415 22:18:23.965122 ==DQ 0 ==
2416 22:18:23.968092 Final DQ duty delay cell = -4
2417 22:18:23.971243 [-4] MAX Duty = 5062%(X100), DQS PI = 8
2418 22:18:23.974873 [-4] MIN Duty = 4938%(X100), DQS PI = 0
2419 22:18:23.977933 [-4] AVG Duty = 5000%(X100)
2420 22:18:23.978012
2421 22:18:23.978098 ==DQ 1 ==
2422 22:18:23.981219 Final DQ duty delay cell = 0
2423 22:18:23.984816 [0] MAX Duty = 5125%(X100), DQS PI = 20
2424 22:18:23.988424 [0] MIN Duty = 4969%(X100), DQS PI = 12
2425 22:18:23.988534 [0] AVG Duty = 5047%(X100)
2426 22:18:23.988627
2427 22:18:23.991399 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2428 22:18:23.994945
2429 22:18:23.997897 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2430 22:18:24.001662 [DutyScan_Calibration_Flow] ====Done====
2431 22:18:24.004677 nWR fixed to 30
2432 22:18:24.004779 [ModeRegInit_LP4] CH0 RK0
2433 22:18:24.007834 [ModeRegInit_LP4] CH0 RK1
2434 22:18:24.012081 [ModeRegInit_LP4] CH1 RK0
2435 22:18:24.012163 [ModeRegInit_LP4] CH1 RK1
2436 22:18:24.014950 match AC timing 7
2437 22:18:24.018377 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2438 22:18:24.021764 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2439 22:18:24.027764 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2440 22:18:24.034372 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2441 22:18:24.037660 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2442 22:18:24.037788 ==
2443 22:18:24.041052 Dram Type= 6, Freq= 0, CH_0, rank 0
2444 22:18:24.044431 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2445 22:18:24.044534 ==
2446 22:18:24.051276 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2447 22:18:24.057377 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2448 22:18:24.064661 [CA 0] Center 39 (8~70) winsize 63
2449 22:18:24.068101 [CA 1] Center 39 (8~70) winsize 63
2450 22:18:24.071578 [CA 2] Center 35 (5~66) winsize 62
2451 22:18:24.074785 [CA 3] Center 34 (4~65) winsize 62
2452 22:18:24.078165 [CA 4] Center 33 (3~64) winsize 62
2453 22:18:24.081407 [CA 5] Center 32 (3~62) winsize 60
2454 22:18:24.081561
2455 22:18:24.084910 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2456 22:18:24.084989
2457 22:18:24.088234 [CATrainingPosCal] consider 1 rank data
2458 22:18:24.091125 u2DelayCellTimex100 = 270/100 ps
2459 22:18:24.094614 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2460 22:18:24.098248 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2461 22:18:24.104828 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2462 22:18:24.108273 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2463 22:18:24.111925 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2464 22:18:24.114641 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2465 22:18:24.114720
2466 22:18:24.118175 CA PerBit enable=1, Macro0, CA PI delay=32
2467 22:18:24.118250
2468 22:18:24.121220 [CBTSetCACLKResult] CA Dly = 32
2469 22:18:24.121311 CS Dly: 6 (0~37)
2470 22:18:24.124422 ==
2471 22:18:24.124515 Dram Type= 6, Freq= 0, CH_0, rank 1
2472 22:18:24.131314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2473 22:18:24.131403 ==
2474 22:18:24.134614 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2475 22:18:24.141774 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2476 22:18:24.150202 [CA 0] Center 38 (8~69) winsize 62
2477 22:18:24.153807 [CA 1] Center 38 (8~69) winsize 62
2478 22:18:24.157352 [CA 2] Center 35 (4~66) winsize 63
2479 22:18:24.160382 [CA 3] Center 34 (4~65) winsize 62
2480 22:18:24.164042 [CA 4] Center 33 (3~64) winsize 62
2481 22:18:24.166842 [CA 5] Center 32 (3~62) winsize 60
2482 22:18:24.166928
2483 22:18:24.170616 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2484 22:18:24.170701
2485 22:18:24.174031 [CATrainingPosCal] consider 2 rank data
2486 22:18:24.176985 u2DelayCellTimex100 = 270/100 ps
2487 22:18:24.180717 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2488 22:18:24.184034 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2489 22:18:24.190654 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2490 22:18:24.193772 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2491 22:18:24.196978 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2492 22:18:24.200945 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2493 22:18:24.201058
2494 22:18:24.203964 CA PerBit enable=1, Macro0, CA PI delay=32
2495 22:18:24.204052
2496 22:18:24.206936 [CBTSetCACLKResult] CA Dly = 32
2497 22:18:24.207046 CS Dly: 6 (0~38)
2498 22:18:24.207115
2499 22:18:24.210752 ----->DramcWriteLeveling(PI) begin...
2500 22:18:24.213532 ==
2501 22:18:24.217206 Dram Type= 6, Freq= 0, CH_0, rank 0
2502 22:18:24.220791 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2503 22:18:24.220871 ==
2504 22:18:24.223886 Write leveling (Byte 0): 32 => 32
2505 22:18:24.226892 Write leveling (Byte 1): 29 => 29
2506 22:18:24.230308 DramcWriteLeveling(PI) end<-----
2507 22:18:24.230388
2508 22:18:24.230469 ==
2509 22:18:24.233815 Dram Type= 6, Freq= 0, CH_0, rank 0
2510 22:18:24.237119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2511 22:18:24.237199 ==
2512 22:18:24.240082 [Gating] SW mode calibration
2513 22:18:24.246815 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2514 22:18:24.250136 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2515 22:18:24.257071 0 15 0 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
2516 22:18:24.260269 0 15 4 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
2517 22:18:24.263901 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2518 22:18:24.270320 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2519 22:18:24.273813 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2520 22:18:24.276988 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2521 22:18:24.283594 0 15 24 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
2522 22:18:24.287234 0 15 28 | B1->B0 | 3333 2525 | 1 0 | (1 1) (0 0)
2523 22:18:24.290780 1 0 0 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
2524 22:18:24.296966 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2525 22:18:24.300594 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2526 22:18:24.303569 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2527 22:18:24.310740 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2528 22:18:24.313746 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2529 22:18:24.317312 1 0 24 | B1->B0 | 2323 2d2c | 0 1 | (0 0) (1 1)
2530 22:18:24.323920 1 0 28 | B1->B0 | 2525 4444 | 0 1 | (0 0) (0 0)
2531 22:18:24.327504 1 1 0 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
2532 22:18:24.330498 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2533 22:18:24.333648 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2534 22:18:24.340346 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2535 22:18:24.344277 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2536 22:18:24.347660 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2537 22:18:24.354004 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2538 22:18:24.357278 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2539 22:18:24.360672 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2540 22:18:24.367286 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2541 22:18:24.370555 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2542 22:18:24.374369 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2543 22:18:24.381211 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2544 22:18:24.384120 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2545 22:18:24.387808 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2546 22:18:24.393978 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2547 22:18:24.397659 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2548 22:18:24.401175 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2549 22:18:24.404208 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2550 22:18:24.410926 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2551 22:18:24.414611 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2552 22:18:24.417444 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2553 22:18:24.424144 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 22:18:24.427872 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2555 22:18:24.430643 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2556 22:18:24.434121 Total UI for P1: 0, mck2ui 16
2557 22:18:24.437601 best dqsien dly found for B0: ( 1, 3, 28)
2558 22:18:24.444240 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2559 22:18:24.444322 Total UI for P1: 0, mck2ui 16
2560 22:18:24.451001 best dqsien dly found for B1: ( 1, 4, 0)
2561 22:18:24.454110 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2562 22:18:24.457636 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2563 22:18:24.457718
2564 22:18:24.460820 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2565 22:18:24.464204 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2566 22:18:24.467305 [Gating] SW calibration Done
2567 22:18:24.467419 ==
2568 22:18:24.470631 Dram Type= 6, Freq= 0, CH_0, rank 0
2569 22:18:24.474105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2570 22:18:24.474187 ==
2571 22:18:24.477376 RX Vref Scan: 0
2572 22:18:24.477481
2573 22:18:24.477567 RX Vref 0 -> 0, step: 1
2574 22:18:24.477628
2575 22:18:24.480930 RX Delay -40 -> 252, step: 8
2576 22:18:24.484054 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2577 22:18:24.487606 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2578 22:18:24.494692 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2579 22:18:24.497440 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2580 22:18:24.501123 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2581 22:18:24.504678 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2582 22:18:24.507637 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2583 22:18:24.514472 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2584 22:18:24.517934 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2585 22:18:24.520898 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
2586 22:18:24.524202 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
2587 22:18:24.527828 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2588 22:18:24.534570 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2589 22:18:24.537979 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2590 22:18:24.540901 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2591 22:18:24.544519 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2592 22:18:24.544626 ==
2593 22:18:24.548173 Dram Type= 6, Freq= 0, CH_0, rank 0
2594 22:18:24.554520 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2595 22:18:24.554604 ==
2596 22:18:24.554677 DQS Delay:
2597 22:18:24.554744 DQS0 = 0, DQS1 = 0
2598 22:18:24.557975 DQM Delay:
2599 22:18:24.558084 DQM0 = 121, DQM1 = 114
2600 22:18:24.560971 DQ Delay:
2601 22:18:24.564348 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2602 22:18:24.567800 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2603 22:18:24.571402 DQ8 =99, DQ9 =107, DQ10 =115, DQ11 =107
2604 22:18:24.574532 DQ12 =119, DQ13 =123, DQ14 =123, DQ15 =119
2605 22:18:24.574633
2606 22:18:24.574753
2607 22:18:24.574849 ==
2608 22:18:24.577722 Dram Type= 6, Freq= 0, CH_0, rank 0
2609 22:18:24.581052 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2610 22:18:24.581123 ==
2611 22:18:24.581197
2612 22:18:24.584323
2613 22:18:24.584425 TX Vref Scan disable
2614 22:18:24.587691 == TX Byte 0 ==
2615 22:18:24.591467 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2616 22:18:24.594608 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2617 22:18:24.598560 == TX Byte 1 ==
2618 22:18:24.601383 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2619 22:18:24.604445 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2620 22:18:24.604564 ==
2621 22:18:24.608392 Dram Type= 6, Freq= 0, CH_0, rank 0
2622 22:18:24.614440 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2623 22:18:24.614540 ==
2624 22:18:24.624865 TX Vref=22, minBit 0, minWin=25, winSum=410
2625 22:18:24.628530 TX Vref=24, minBit 0, minWin=25, winSum=414
2626 22:18:24.632229 TX Vref=26, minBit 1, minWin=25, winSum=421
2627 22:18:24.635162 TX Vref=28, minBit 0, minWin=26, winSum=426
2628 22:18:24.638599 TX Vref=30, minBit 10, minWin=26, winSum=429
2629 22:18:24.641622 TX Vref=32, minBit 0, minWin=26, winSum=422
2630 22:18:24.648732 [TxChooseVref] Worse bit 10, Min win 26, Win sum 429, Final Vref 30
2631 22:18:24.648871
2632 22:18:24.652245 Final TX Range 1 Vref 30
2633 22:18:24.652348
2634 22:18:24.652436 ==
2635 22:18:24.655421 Dram Type= 6, Freq= 0, CH_0, rank 0
2636 22:18:24.658587 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2637 22:18:24.658684 ==
2638 22:18:24.658773
2639 22:18:24.658861
2640 22:18:24.661853 TX Vref Scan disable
2641 22:18:24.665695 == TX Byte 0 ==
2642 22:18:24.668899 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2643 22:18:24.672138 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2644 22:18:24.675598 == TX Byte 1 ==
2645 22:18:24.678676 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2646 22:18:24.682118 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2647 22:18:24.682197
2648 22:18:24.685354 [DATLAT]
2649 22:18:24.685427 Freq=1200, CH0 RK0
2650 22:18:24.685489
2651 22:18:24.688574 DATLAT Default: 0xd
2652 22:18:24.688653 0, 0xFFFF, sum = 0
2653 22:18:24.691922 1, 0xFFFF, sum = 0
2654 22:18:24.691995 2, 0xFFFF, sum = 0
2655 22:18:24.695209 3, 0xFFFF, sum = 0
2656 22:18:24.695287 4, 0xFFFF, sum = 0
2657 22:18:24.698860 5, 0xFFFF, sum = 0
2658 22:18:24.698942 6, 0xFFFF, sum = 0
2659 22:18:24.701874 7, 0xFFFF, sum = 0
2660 22:18:24.701953 8, 0xFFFF, sum = 0
2661 22:18:24.705545 9, 0xFFFF, sum = 0
2662 22:18:24.708432 10, 0xFFFF, sum = 0
2663 22:18:24.708548 11, 0xFFFF, sum = 0
2664 22:18:24.711974 12, 0x0, sum = 1
2665 22:18:24.712057 13, 0x0, sum = 2
2666 22:18:24.712123 14, 0x0, sum = 3
2667 22:18:24.715258 15, 0x0, sum = 4
2668 22:18:24.715340 best_step = 13
2669 22:18:24.715404
2670 22:18:24.718760 ==
2671 22:18:24.718841 Dram Type= 6, Freq= 0, CH_0, rank 0
2672 22:18:24.725673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2673 22:18:24.725768 ==
2674 22:18:24.725832 RX Vref Scan: 1
2675 22:18:24.725892
2676 22:18:24.728602 Set Vref Range= 32 -> 127
2677 22:18:24.728683
2678 22:18:24.731816 RX Vref 32 -> 127, step: 1
2679 22:18:24.731897
2680 22:18:24.735551 RX Delay -13 -> 252, step: 4
2681 22:18:24.735632
2682 22:18:24.738610 Set Vref, RX VrefLevel [Byte0]: 32
2683 22:18:24.742139 [Byte1]: 32
2684 22:18:24.742220
2685 22:18:24.745315 Set Vref, RX VrefLevel [Byte0]: 33
2686 22:18:24.748487 [Byte1]: 33
2687 22:18:24.748577
2688 22:18:24.752034 Set Vref, RX VrefLevel [Byte0]: 34
2689 22:18:24.755164 [Byte1]: 34
2690 22:18:24.759175
2691 22:18:24.759256 Set Vref, RX VrefLevel [Byte0]: 35
2692 22:18:24.762363 [Byte1]: 35
2693 22:18:24.767107
2694 22:18:24.767204 Set Vref, RX VrefLevel [Byte0]: 36
2695 22:18:24.770991 [Byte1]: 36
2696 22:18:24.775244
2697 22:18:24.775325 Set Vref, RX VrefLevel [Byte0]: 37
2698 22:18:24.778462 [Byte1]: 37
2699 22:18:24.783049
2700 22:18:24.783130 Set Vref, RX VrefLevel [Byte0]: 38
2701 22:18:24.786074 [Byte1]: 38
2702 22:18:24.790515
2703 22:18:24.790597 Set Vref, RX VrefLevel [Byte0]: 39
2704 22:18:24.793838 [Byte1]: 39
2705 22:18:24.798866
2706 22:18:24.798947 Set Vref, RX VrefLevel [Byte0]: 40
2707 22:18:24.802246 [Byte1]: 40
2708 22:18:24.806558
2709 22:18:24.806639 Set Vref, RX VrefLevel [Byte0]: 41
2710 22:18:24.809659 [Byte1]: 41
2711 22:18:24.814750
2712 22:18:24.814831 Set Vref, RX VrefLevel [Byte0]: 42
2713 22:18:24.817676 [Byte1]: 42
2714 22:18:24.822167
2715 22:18:24.825692 Set Vref, RX VrefLevel [Byte0]: 43
2716 22:18:24.828741 [Byte1]: 43
2717 22:18:24.828822
2718 22:18:24.832172 Set Vref, RX VrefLevel [Byte0]: 44
2719 22:18:24.835515 [Byte1]: 44
2720 22:18:24.835596
2721 22:18:24.838979 Set Vref, RX VrefLevel [Byte0]: 45
2722 22:18:24.842423 [Byte1]: 45
2723 22:18:24.846055
2724 22:18:24.846135 Set Vref, RX VrefLevel [Byte0]: 46
2725 22:18:24.849453 [Byte1]: 46
2726 22:18:24.854092
2727 22:18:24.854176 Set Vref, RX VrefLevel [Byte0]: 47
2728 22:18:24.857140 [Byte1]: 47
2729 22:18:24.861796
2730 22:18:24.861877 Set Vref, RX VrefLevel [Byte0]: 48
2731 22:18:24.865325 [Byte1]: 48
2732 22:18:24.869678
2733 22:18:24.869760 Set Vref, RX VrefLevel [Byte0]: 49
2734 22:18:24.872948 [Byte1]: 49
2735 22:18:24.877524
2736 22:18:24.877622 Set Vref, RX VrefLevel [Byte0]: 50
2737 22:18:24.881129 [Byte1]: 50
2738 22:18:24.885503
2739 22:18:24.885633 Set Vref, RX VrefLevel [Byte0]: 51
2740 22:18:24.888937 [Byte1]: 51
2741 22:18:24.893247
2742 22:18:24.893355 Set Vref, RX VrefLevel [Byte0]: 52
2743 22:18:24.896662 [Byte1]: 52
2744 22:18:24.901619
2745 22:18:24.901727 Set Vref, RX VrefLevel [Byte0]: 53
2746 22:18:24.904547 [Byte1]: 53
2747 22:18:24.908995
2748 22:18:24.909099 Set Vref, RX VrefLevel [Byte0]: 54
2749 22:18:24.912153 [Byte1]: 54
2750 22:18:24.916992
2751 22:18:24.917094 Set Vref, RX VrefLevel [Byte0]: 55
2752 22:18:24.920850 [Byte1]: 55
2753 22:18:24.924892
2754 22:18:24.924995 Set Vref, RX VrefLevel [Byte0]: 56
2755 22:18:24.928431 [Byte1]: 56
2756 22:18:24.933032
2757 22:18:24.933134 Set Vref, RX VrefLevel [Byte0]: 57
2758 22:18:24.936031 [Byte1]: 57
2759 22:18:24.940641
2760 22:18:24.940743 Set Vref, RX VrefLevel [Byte0]: 58
2761 22:18:24.943872 [Byte1]: 58
2762 22:18:24.948335
2763 22:18:24.948443 Set Vref, RX VrefLevel [Byte0]: 59
2764 22:18:24.952047 [Byte1]: 59
2765 22:18:24.956794
2766 22:18:24.956901 Set Vref, RX VrefLevel [Byte0]: 60
2767 22:18:24.960008 [Byte1]: 60
2768 22:18:24.964522
2769 22:18:24.964625 Set Vref, RX VrefLevel [Byte0]: 61
2770 22:18:24.967455 [Byte1]: 61
2771 22:18:24.972336
2772 22:18:24.972440 Set Vref, RX VrefLevel [Byte0]: 62
2773 22:18:24.975843 [Byte1]: 62
2774 22:18:24.980302
2775 22:18:24.980409 Set Vref, RX VrefLevel [Byte0]: 63
2776 22:18:24.983815 [Byte1]: 63
2777 22:18:24.988241
2778 22:18:24.988338 Set Vref, RX VrefLevel [Byte0]: 64
2779 22:18:24.991280 [Byte1]: 64
2780 22:18:24.995739
2781 22:18:24.995881 Set Vref, RX VrefLevel [Byte0]: 65
2782 22:18:24.999278 [Byte1]: 65
2783 22:18:25.003667
2784 22:18:25.003765 Set Vref, RX VrefLevel [Byte0]: 66
2785 22:18:25.007024 [Byte1]: 66
2786 22:18:25.011710
2787 22:18:25.011808 Set Vref, RX VrefLevel [Byte0]: 67
2788 22:18:25.014698 [Byte1]: 67
2789 22:18:25.019875
2790 22:18:25.019954 Set Vref, RX VrefLevel [Byte0]: 68
2791 22:18:25.023115 [Byte1]: 68
2792 22:18:25.027743
2793 22:18:25.027819 Set Vref, RX VrefLevel [Byte0]: 69
2794 22:18:25.030712 [Byte1]: 69
2795 22:18:25.036013
2796 22:18:25.036083 Final RX Vref Byte 0 = 56 to rank0
2797 22:18:25.038814 Final RX Vref Byte 1 = 47 to rank0
2798 22:18:25.042186 Final RX Vref Byte 0 = 56 to rank1
2799 22:18:25.045278 Final RX Vref Byte 1 = 47 to rank1==
2800 22:18:25.048725 Dram Type= 6, Freq= 0, CH_0, rank 0
2801 22:18:25.052060 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2802 22:18:25.055367 ==
2803 22:18:25.055449 DQS Delay:
2804 22:18:25.055532 DQS0 = 0, DQS1 = 0
2805 22:18:25.059031 DQM Delay:
2806 22:18:25.059116 DQM0 = 120, DQM1 = 110
2807 22:18:25.062533 DQ Delay:
2808 22:18:25.065486 DQ0 =120, DQ1 =122, DQ2 =118, DQ3 =118
2809 22:18:25.068852 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =126
2810 22:18:25.071879 DQ8 =96, DQ9 =100, DQ10 =112, DQ11 =104
2811 22:18:25.075466 DQ12 =116, DQ13 =116, DQ14 =124, DQ15 =118
2812 22:18:25.075551
2813 22:18:25.075636
2814 22:18:25.082194 [DQSOSCAuto] RK0, (LSB)MR18= 0x1710, (MSB)MR19= 0x404, tDQSOscB0 = 403 ps tDQSOscB1 = 401 ps
2815 22:18:25.085480 CH0 RK0: MR19=404, MR18=1710
2816 22:18:25.092114 CH0_RK0: MR19=0x404, MR18=0x1710, DQSOSC=401, MR23=63, INC=40, DEC=27
2817 22:18:25.092200
2818 22:18:25.095493 ----->DramcWriteLeveling(PI) begin...
2819 22:18:25.095580 ==
2820 22:18:25.098883 Dram Type= 6, Freq= 0, CH_0, rank 1
2821 22:18:25.102147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2822 22:18:25.102232 ==
2823 22:18:25.105684 Write leveling (Byte 0): 35 => 35
2824 22:18:25.109138 Write leveling (Byte 1): 27 => 27
2825 22:18:25.112544 DramcWriteLeveling(PI) end<-----
2826 22:18:25.112629
2827 22:18:25.112715 ==
2828 22:18:25.115805 Dram Type= 6, Freq= 0, CH_0, rank 1
2829 22:18:25.122237 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2830 22:18:25.122323 ==
2831 22:18:25.122409 [Gating] SW mode calibration
2832 22:18:25.131728 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2833 22:18:25.135554 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2834 22:18:25.139030 0 15 0 | B1->B0 | 3333 2f2f | 0 0 | (0 0) (0 0)
2835 22:18:25.145298 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2836 22:18:25.148981 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2837 22:18:25.151922 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2838 22:18:25.158464 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2839 22:18:25.162127 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2840 22:18:25.165435 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2841 22:18:25.172294 0 15 28 | B1->B0 | 2f2f 2f2f | 1 1 | (1 0) (0 0)
2842 22:18:25.175406 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2843 22:18:25.178584 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2844 22:18:25.185275 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2845 22:18:25.188934 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2846 22:18:25.191874 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2847 22:18:25.198887 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2848 22:18:25.202566 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2849 22:18:25.205307 1 0 28 | B1->B0 | 3737 3a3a | 0 0 | (1 1) (0 0)
2850 22:18:25.212373 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2851 22:18:25.215576 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2852 22:18:25.218985 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2853 22:18:25.221962 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2854 22:18:25.228913 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2855 22:18:25.232504 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2856 22:18:25.235836 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2857 22:18:25.242081 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2858 22:18:25.245454 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2859 22:18:25.248612 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2860 22:18:25.255241 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2861 22:18:25.258594 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2862 22:18:25.262402 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2863 22:18:25.268532 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2864 22:18:25.272260 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2865 22:18:25.275638 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2866 22:18:25.282187 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2867 22:18:25.285785 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2868 22:18:25.288864 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2869 22:18:25.295660 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2870 22:18:25.299134 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2871 22:18:25.302095 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2872 22:18:25.308615 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2873 22:18:25.312484 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2874 22:18:25.315702 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
2875 22:18:25.318513 Total UI for P1: 0, mck2ui 16
2876 22:18:25.322491 best dqsien dly found for B1: ( 1, 3, 28)
2877 22:18:25.325842 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2878 22:18:25.328472 Total UI for P1: 0, mck2ui 16
2879 22:18:25.332263 best dqsien dly found for B0: ( 1, 3, 30)
2880 22:18:25.335608 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2881 22:18:25.338751 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2882 22:18:25.342119
2883 22:18:25.345359 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2884 22:18:25.348984 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2885 22:18:25.352022 [Gating] SW calibration Done
2886 22:18:25.352107 ==
2887 22:18:25.355262 Dram Type= 6, Freq= 0, CH_0, rank 1
2888 22:18:25.359049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2889 22:18:25.359134 ==
2890 22:18:25.359202 RX Vref Scan: 0
2891 22:18:25.359262
2892 22:18:25.362025 RX Vref 0 -> 0, step: 1
2893 22:18:25.362110
2894 22:18:25.365452 RX Delay -40 -> 252, step: 8
2895 22:18:25.368987 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2896 22:18:25.372637 iDelay=200, Bit 1, Center 123 (56 ~ 191) 136
2897 22:18:25.379442 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2898 22:18:25.382147 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2899 22:18:25.385307 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2900 22:18:25.388860 iDelay=200, Bit 5, Center 119 (48 ~ 191) 144
2901 22:18:25.392618 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2902 22:18:25.399102 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2903 22:18:25.401942 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2904 22:18:25.405562 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2905 22:18:25.409166 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2906 22:18:25.411993 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2907 22:18:25.418859 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2908 22:18:25.422167 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2909 22:18:25.425345 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2910 22:18:25.428761 iDelay=200, Bit 15, Center 119 (56 ~ 183) 128
2911 22:18:25.428841 ==
2912 22:18:25.431989 Dram Type= 6, Freq= 0, CH_0, rank 1
2913 22:18:25.435372 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2914 22:18:25.439287 ==
2915 22:18:25.439373 DQS Delay:
2916 22:18:25.439442 DQS0 = 0, DQS1 = 0
2917 22:18:25.442462 DQM Delay:
2918 22:18:25.442536 DQM0 = 122, DQM1 = 112
2919 22:18:25.445370 DQ Delay:
2920 22:18:25.448994 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2921 22:18:25.452529 DQ4 =127, DQ5 =119, DQ6 =127, DQ7 =127
2922 22:18:25.455492 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
2923 22:18:25.459247 DQ12 =115, DQ13 =119, DQ14 =123, DQ15 =119
2924 22:18:25.459330
2925 22:18:25.459396
2926 22:18:25.459481 ==
2927 22:18:25.462328 Dram Type= 6, Freq= 0, CH_0, rank 1
2928 22:18:25.465940 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2929 22:18:25.466024 ==
2930 22:18:25.466089
2931 22:18:25.466148
2932 22:18:25.469284 TX Vref Scan disable
2933 22:18:25.472945 == TX Byte 0 ==
2934 22:18:25.476050 Update DQ dly =855 (3 ,2, 23) DQ OEN =(2 ,7)
2935 22:18:25.479027 Update DQM dly =855 (3 ,2, 23) DQM OEN =(2 ,7)
2936 22:18:25.482422 == TX Byte 1 ==
2937 22:18:25.485847 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2938 22:18:25.489177 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2939 22:18:25.489258 ==
2940 22:18:25.492805 Dram Type= 6, Freq= 0, CH_0, rank 1
2941 22:18:25.495878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2942 22:18:25.499210 ==
2943 22:18:25.509779 TX Vref=22, minBit 3, minWin=25, winSum=415
2944 22:18:25.513596 TX Vref=24, minBit 0, minWin=26, winSum=424
2945 22:18:25.516568 TX Vref=26, minBit 0, minWin=26, winSum=421
2946 22:18:25.519924 TX Vref=28, minBit 5, minWin=25, winSum=427
2947 22:18:25.523327 TX Vref=30, minBit 0, minWin=26, winSum=425
2948 22:18:25.526865 TX Vref=32, minBit 1, minWin=26, winSum=426
2949 22:18:25.533350 [TxChooseVref] Worse bit 1, Min win 26, Win sum 426, Final Vref 32
2950 22:18:25.533449
2951 22:18:25.537011 Final TX Range 1 Vref 32
2952 22:18:25.537094
2953 22:18:25.537160 ==
2954 22:18:25.540117 Dram Type= 6, Freq= 0, CH_0, rank 1
2955 22:18:25.543612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2956 22:18:25.543695 ==
2957 22:18:25.543761
2958 22:18:25.543820
2959 22:18:25.546961 TX Vref Scan disable
2960 22:18:25.550420 == TX Byte 0 ==
2961 22:18:25.553570 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2962 22:18:25.557156 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2963 22:18:25.560258 == TX Byte 1 ==
2964 22:18:25.563655 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2965 22:18:25.566803 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2966 22:18:25.566941
2967 22:18:25.570031 [DATLAT]
2968 22:18:25.570107 Freq=1200, CH0 RK1
2969 22:18:25.570170
2970 22:18:25.573788 DATLAT Default: 0xd
2971 22:18:25.573861 0, 0xFFFF, sum = 0
2972 22:18:25.576912 1, 0xFFFF, sum = 0
2973 22:18:25.577048 2, 0xFFFF, sum = 0
2974 22:18:25.580017 3, 0xFFFF, sum = 0
2975 22:18:25.580116 4, 0xFFFF, sum = 0
2976 22:18:25.583610 5, 0xFFFF, sum = 0
2977 22:18:25.583709 6, 0xFFFF, sum = 0
2978 22:18:25.586949 7, 0xFFFF, sum = 0
2979 22:18:25.587032 8, 0xFFFF, sum = 0
2980 22:18:25.590138 9, 0xFFFF, sum = 0
2981 22:18:25.593429 10, 0xFFFF, sum = 0
2982 22:18:25.593533 11, 0xFFFF, sum = 0
2983 22:18:25.597128 12, 0x0, sum = 1
2984 22:18:25.597228 13, 0x0, sum = 2
2985 22:18:25.597329 14, 0x0, sum = 3
2986 22:18:25.600166 15, 0x0, sum = 4
2987 22:18:25.600272 best_step = 13
2988 22:18:25.600361
2989 22:18:25.600446 ==
2990 22:18:25.603636 Dram Type= 6, Freq= 0, CH_0, rank 1
2991 22:18:25.610275 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2992 22:18:25.610376 ==
2993 22:18:25.610509 RX Vref Scan: 0
2994 22:18:25.610601
2995 22:18:25.613296 RX Vref 0 -> 0, step: 1
2996 22:18:25.613369
2997 22:18:25.616920 RX Delay -13 -> 252, step: 4
2998 22:18:25.619782 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
2999 22:18:25.623356 iDelay=195, Bit 1, Center 120 (55 ~ 186) 132
3000 22:18:25.629944 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3001 22:18:25.633310 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
3002 22:18:25.636516 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3003 22:18:25.639958 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3004 22:18:25.643153 iDelay=195, Bit 6, Center 128 (63 ~ 194) 132
3005 22:18:25.650235 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3006 22:18:25.653606 iDelay=195, Bit 8, Center 100 (35 ~ 166) 132
3007 22:18:25.656948 iDelay=195, Bit 9, Center 96 (31 ~ 162) 132
3008 22:18:25.660343 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3009 22:18:25.663304 iDelay=195, Bit 11, Center 100 (35 ~ 166) 132
3010 22:18:25.670559 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3011 22:18:25.673618 iDelay=195, Bit 13, Center 116 (55 ~ 178) 124
3012 22:18:25.677086 iDelay=195, Bit 14, Center 120 (59 ~ 182) 124
3013 22:18:25.680532 iDelay=195, Bit 15, Center 118 (55 ~ 182) 128
3014 22:18:25.680615 ==
3015 22:18:25.683731 Dram Type= 6, Freq= 0, CH_0, rank 1
3016 22:18:25.687291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3017 22:18:25.690309 ==
3018 22:18:25.690392 DQS Delay:
3019 22:18:25.690460 DQS0 = 0, DQS1 = 0
3020 22:18:25.693807 DQM Delay:
3021 22:18:25.693889 DQM0 = 120, DQM1 = 109
3022 22:18:25.696975 DQ Delay:
3023 22:18:25.700564 DQ0 =118, DQ1 =120, DQ2 =118, DQ3 =118
3024 22:18:25.703958 DQ4 =122, DQ5 =116, DQ6 =128, DQ7 =126
3025 22:18:25.706992 DQ8 =100, DQ9 =96, DQ10 =110, DQ11 =100
3026 22:18:25.710642 DQ12 =114, DQ13 =116, DQ14 =120, DQ15 =118
3027 22:18:25.710742
3028 22:18:25.710843
3029 22:18:25.717109 [DQSOSCAuto] RK1, (LSB)MR18= 0x10f2, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 403 ps
3030 22:18:25.720163 CH0 RK1: MR19=403, MR18=10F2
3031 22:18:25.727341 CH0_RK1: MR19=0x403, MR18=0x10F2, DQSOSC=403, MR23=63, INC=40, DEC=26
3032 22:18:25.730198 [RxdqsGatingPostProcess] freq 1200
3033 22:18:25.737224 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3034 22:18:25.740654 best DQS0 dly(2T, 0.5T) = (0, 11)
3035 22:18:25.740759 best DQS1 dly(2T, 0.5T) = (0, 12)
3036 22:18:25.743414 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3037 22:18:25.747145 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3038 22:18:25.750545 best DQS0 dly(2T, 0.5T) = (0, 11)
3039 22:18:25.753320 best DQS1 dly(2T, 0.5T) = (0, 11)
3040 22:18:25.756911 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3041 22:18:25.760204 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3042 22:18:25.763643 Pre-setting of DQS Precalculation
3043 22:18:25.770619 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3044 22:18:25.770735 ==
3045 22:18:25.773505 Dram Type= 6, Freq= 0, CH_1, rank 0
3046 22:18:25.777209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3047 22:18:25.777308 ==
3048 22:18:25.780269 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3049 22:18:25.786908 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3050 22:18:25.796366 [CA 0] Center 37 (7~68) winsize 62
3051 22:18:25.799592 [CA 1] Center 37 (7~68) winsize 62
3052 22:18:25.802948 [CA 2] Center 35 (5~65) winsize 61
3053 22:18:25.806271 [CA 3] Center 34 (4~65) winsize 62
3054 22:18:25.809551 [CA 4] Center 34 (5~64) winsize 60
3055 22:18:25.812840 [CA 5] Center 33 (3~63) winsize 61
3056 22:18:25.812937
3057 22:18:25.816409 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3058 22:18:25.816511
3059 22:18:25.819893 [CATrainingPosCal] consider 1 rank data
3060 22:18:25.822975 u2DelayCellTimex100 = 270/100 ps
3061 22:18:25.826600 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3062 22:18:25.829432 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3063 22:18:25.836086 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3064 22:18:25.839637 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3065 22:18:25.842759 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3066 22:18:25.846199 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3067 22:18:25.846305
3068 22:18:25.849545 CA PerBit enable=1, Macro0, CA PI delay=33
3069 22:18:25.849640
3070 22:18:25.852787 [CBTSetCACLKResult] CA Dly = 33
3071 22:18:25.852886 CS Dly: 7 (0~38)
3072 22:18:25.852976 ==
3073 22:18:25.856500 Dram Type= 6, Freq= 0, CH_1, rank 1
3074 22:18:25.862792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3075 22:18:25.862898 ==
3076 22:18:25.866271 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3077 22:18:25.872876 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3078 22:18:25.882163 [CA 0] Center 37 (7~68) winsize 62
3079 22:18:25.885205 [CA 1] Center 37 (7~68) winsize 62
3080 22:18:25.888983 [CA 2] Center 35 (5~65) winsize 61
3081 22:18:25.891681 [CA 3] Center 34 (4~65) winsize 62
3082 22:18:25.895355 [CA 4] Center 34 (4~65) winsize 62
3083 22:18:25.898839 [CA 5] Center 34 (4~64) winsize 61
3084 22:18:25.898942
3085 22:18:25.901603 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3086 22:18:25.901704
3087 22:18:25.905232 [CATrainingPosCal] consider 2 rank data
3088 22:18:25.908631 u2DelayCellTimex100 = 270/100 ps
3089 22:18:25.911854 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3090 22:18:25.915260 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3091 22:18:25.921764 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3092 22:18:25.925467 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3093 22:18:25.928529 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3094 22:18:25.931889 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3095 22:18:25.931994
3096 22:18:25.935036 CA PerBit enable=1, Macro0, CA PI delay=33
3097 22:18:25.935138
3098 22:18:25.938756 [CBTSetCACLKResult] CA Dly = 33
3099 22:18:25.938853 CS Dly: 8 (0~41)
3100 22:18:25.938951
3101 22:18:25.942235 ----->DramcWriteLeveling(PI) begin...
3102 22:18:25.942334 ==
3103 22:18:25.945736 Dram Type= 6, Freq= 0, CH_1, rank 0
3104 22:18:25.952251 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3105 22:18:25.952351 ==
3106 22:18:25.955698 Write leveling (Byte 0): 26 => 26
3107 22:18:25.958825 Write leveling (Byte 1): 28 => 28
3108 22:18:25.958933 DramcWriteLeveling(PI) end<-----
3109 22:18:25.959035
3110 22:18:25.962248 ==
3111 22:18:25.965749 Dram Type= 6, Freq= 0, CH_1, rank 0
3112 22:18:25.969118 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3113 22:18:25.969229 ==
3114 22:18:25.971998 [Gating] SW mode calibration
3115 22:18:25.978879 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3116 22:18:25.982213 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3117 22:18:25.988614 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3118 22:18:25.992384 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3119 22:18:25.995908 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3120 22:18:26.002403 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3121 22:18:26.005491 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3122 22:18:26.009361 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 0)
3123 22:18:26.015674 0 15 24 | B1->B0 | 3434 3030 | 1 0 | (1 0) (0 0)
3124 22:18:26.019325 0 15 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (1 0)
3125 22:18:26.022129 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3126 22:18:26.029238 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3127 22:18:26.032808 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3128 22:18:26.035750 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3129 22:18:26.039206 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3130 22:18:26.045959 1 0 20 | B1->B0 | 2323 2424 | 0 1 | (0 0) (0 0)
3131 22:18:26.048908 1 0 24 | B1->B0 | 2e2e 3b3b | 1 1 | (1 1) (0 0)
3132 22:18:26.052475 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3133 22:18:26.058806 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3134 22:18:26.062290 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3135 22:18:26.065860 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3136 22:18:26.072550 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3137 22:18:26.075944 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3138 22:18:26.079182 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3139 22:18:26.085657 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3140 22:18:26.089166 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3141 22:18:26.092218 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3142 22:18:26.099685 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3143 22:18:26.102553 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3144 22:18:26.106093 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3145 22:18:26.112341 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3146 22:18:26.116001 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3147 22:18:26.118991 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3148 22:18:26.122309 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3149 22:18:26.128993 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3150 22:18:26.132776 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3151 22:18:26.135787 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3152 22:18:26.142269 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3153 22:18:26.146055 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3154 22:18:26.149011 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3155 22:18:26.155680 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3156 22:18:26.158873 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3157 22:18:26.162753 Total UI for P1: 0, mck2ui 16
3158 22:18:26.166312 best dqsien dly found for B0: ( 1, 3, 24)
3159 22:18:26.169008 Total UI for P1: 0, mck2ui 16
3160 22:18:26.173078 best dqsien dly found for B1: ( 1, 3, 24)
3161 22:18:26.175902 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3162 22:18:26.179306 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3163 22:18:26.179387
3164 22:18:26.182667 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3165 22:18:26.186100 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3166 22:18:26.189288 [Gating] SW calibration Done
3167 22:18:26.189369 ==
3168 22:18:26.192787 Dram Type= 6, Freq= 0, CH_1, rank 0
3169 22:18:26.196310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3170 22:18:26.196417 ==
3171 22:18:26.199772 RX Vref Scan: 0
3172 22:18:26.199854
3173 22:18:26.202801 RX Vref 0 -> 0, step: 1
3174 22:18:26.202882
3175 22:18:26.202947 RX Delay -40 -> 252, step: 8
3176 22:18:26.209491 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3177 22:18:26.212423 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3178 22:18:26.215994 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3179 22:18:26.219232 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3180 22:18:26.222674 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3181 22:18:26.229594 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3182 22:18:26.233246 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3183 22:18:26.236316 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3184 22:18:26.239450 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3185 22:18:26.242811 iDelay=200, Bit 9, Center 103 (40 ~ 167) 128
3186 22:18:26.249286 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3187 22:18:26.252976 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3188 22:18:26.256118 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3189 22:18:26.259798 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3190 22:18:26.262871 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3191 22:18:26.269292 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3192 22:18:26.269370 ==
3193 22:18:26.272797 Dram Type= 6, Freq= 0, CH_1, rank 0
3194 22:18:26.276296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3195 22:18:26.276382 ==
3196 22:18:26.276448 DQS Delay:
3197 22:18:26.279258 DQS0 = 0, DQS1 = 0
3198 22:18:26.279341 DQM Delay:
3199 22:18:26.282631 DQM0 = 120, DQM1 = 116
3200 22:18:26.282715 DQ Delay:
3201 22:18:26.286130 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3202 22:18:26.289306 DQ4 =119, DQ5 =127, DQ6 =131, DQ7 =119
3203 22:18:26.292698 DQ8 =103, DQ9 =103, DQ10 =115, DQ11 =111
3204 22:18:26.295929 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3205 22:18:26.296012
3206 22:18:26.296078
3207 22:18:26.299357 ==
3208 22:18:26.302483 Dram Type= 6, Freq= 0, CH_1, rank 0
3209 22:18:26.305924 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3210 22:18:26.306007 ==
3211 22:18:26.306073
3212 22:18:26.306133
3213 22:18:26.309571 TX Vref Scan disable
3214 22:18:26.309653 == TX Byte 0 ==
3215 22:18:26.312688 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3216 22:18:26.319514 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3217 22:18:26.319597 == TX Byte 1 ==
3218 22:18:26.323395 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3219 22:18:26.329828 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3220 22:18:26.329911 ==
3221 22:18:26.332916 Dram Type= 6, Freq= 0, CH_1, rank 0
3222 22:18:26.336644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3223 22:18:26.336729 ==
3224 22:18:26.347720 TX Vref=22, minBit 11, minWin=24, winSum=414
3225 22:18:26.351199 TX Vref=24, minBit 9, minWin=25, winSum=419
3226 22:18:26.354200 TX Vref=26, minBit 1, minWin=26, winSum=424
3227 22:18:26.357912 TX Vref=28, minBit 9, minWin=25, winSum=428
3228 22:18:26.361240 TX Vref=30, minBit 2, minWin=26, winSum=432
3229 22:18:26.367930 TX Vref=32, minBit 10, minWin=26, winSum=431
3230 22:18:26.371084 [TxChooseVref] Worse bit 2, Min win 26, Win sum 432, Final Vref 30
3231 22:18:26.371168
3232 22:18:26.374391 Final TX Range 1 Vref 30
3233 22:18:26.374475
3234 22:18:26.374540 ==
3235 22:18:26.377920 Dram Type= 6, Freq= 0, CH_1, rank 0
3236 22:18:26.381281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3237 22:18:26.381364 ==
3238 22:18:26.381429
3239 22:18:26.384763
3240 22:18:26.384846 TX Vref Scan disable
3241 22:18:26.387757 == TX Byte 0 ==
3242 22:18:26.391299 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3243 22:18:26.394565 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3244 22:18:26.397754 == TX Byte 1 ==
3245 22:18:26.401224 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3246 22:18:26.404388 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3247 22:18:26.404472
3248 22:18:26.407879 [DATLAT]
3249 22:18:26.407966 Freq=1200, CH1 RK0
3250 22:18:26.408031
3251 22:18:26.411270 DATLAT Default: 0xd
3252 22:18:26.411352 0, 0xFFFF, sum = 0
3253 22:18:26.414790 1, 0xFFFF, sum = 0
3254 22:18:26.414874 2, 0xFFFF, sum = 0
3255 22:18:26.417826 3, 0xFFFF, sum = 0
3256 22:18:26.417910 4, 0xFFFF, sum = 0
3257 22:18:26.421258 5, 0xFFFF, sum = 0
3258 22:18:26.421342 6, 0xFFFF, sum = 0
3259 22:18:26.424714 7, 0xFFFF, sum = 0
3260 22:18:26.424798 8, 0xFFFF, sum = 0
3261 22:18:26.427708 9, 0xFFFF, sum = 0
3262 22:18:26.431575 10, 0xFFFF, sum = 0
3263 22:18:26.431660 11, 0xFFFF, sum = 0
3264 22:18:26.434640 12, 0x0, sum = 1
3265 22:18:26.434724 13, 0x0, sum = 2
3266 22:18:26.434791 14, 0x0, sum = 3
3267 22:18:26.438360 15, 0x0, sum = 4
3268 22:18:26.438444 best_step = 13
3269 22:18:26.438509
3270 22:18:26.438570 ==
3271 22:18:26.441326 Dram Type= 6, Freq= 0, CH_1, rank 0
3272 22:18:26.448232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3273 22:18:26.448316 ==
3274 22:18:26.448381 RX Vref Scan: 1
3275 22:18:26.448442
3276 22:18:26.451663 Set Vref Range= 32 -> 127
3277 22:18:26.451746
3278 22:18:26.455125 RX Vref 32 -> 127, step: 1
3279 22:18:26.455239
3280 22:18:26.458211 RX Delay -5 -> 252, step: 4
3281 22:18:26.458294
3282 22:18:26.461155 Set Vref, RX VrefLevel [Byte0]: 32
3283 22:18:26.464632 [Byte1]: 32
3284 22:18:26.464715
3285 22:18:26.468326 Set Vref, RX VrefLevel [Byte0]: 33
3286 22:18:26.471375 [Byte1]: 33
3287 22:18:26.471457
3288 22:18:26.474312 Set Vref, RX VrefLevel [Byte0]: 34
3289 22:18:26.477803 [Byte1]: 34
3290 22:18:26.481880
3291 22:18:26.481962 Set Vref, RX VrefLevel [Byte0]: 35
3292 22:18:26.484995 [Byte1]: 35
3293 22:18:26.489822
3294 22:18:26.489908 Set Vref, RX VrefLevel [Byte0]: 36
3295 22:18:26.492971 [Byte1]: 36
3296 22:18:26.497453
3297 22:18:26.497568 Set Vref, RX VrefLevel [Byte0]: 37
3298 22:18:26.500458 [Byte1]: 37
3299 22:18:26.505141
3300 22:18:26.505216 Set Vref, RX VrefLevel [Byte0]: 38
3301 22:18:26.508476 [Byte1]: 38
3302 22:18:26.513104
3303 22:18:26.513196 Set Vref, RX VrefLevel [Byte0]: 39
3304 22:18:26.516670 [Byte1]: 39
3305 22:18:26.520766
3306 22:18:26.520858 Set Vref, RX VrefLevel [Byte0]: 40
3307 22:18:26.524798 [Byte1]: 40
3308 22:18:26.529049
3309 22:18:26.529129 Set Vref, RX VrefLevel [Byte0]: 41
3310 22:18:26.532067 [Byte1]: 41
3311 22:18:26.536936
3312 22:18:26.537042 Set Vref, RX VrefLevel [Byte0]: 42
3313 22:18:26.540044 [Byte1]: 42
3314 22:18:26.544506
3315 22:18:26.544585 Set Vref, RX VrefLevel [Byte0]: 43
3316 22:18:26.547829 [Byte1]: 43
3317 22:18:26.552629
3318 22:18:26.552708 Set Vref, RX VrefLevel [Byte0]: 44
3319 22:18:26.555512 [Byte1]: 44
3320 22:18:26.560004
3321 22:18:26.560083 Set Vref, RX VrefLevel [Byte0]: 45
3322 22:18:26.563565 [Byte1]: 45
3323 22:18:26.568239
3324 22:18:26.568353 Set Vref, RX VrefLevel [Byte0]: 46
3325 22:18:26.571422 [Byte1]: 46
3326 22:18:26.576307
3327 22:18:26.576387 Set Vref, RX VrefLevel [Byte0]: 47
3328 22:18:26.579335 [Byte1]: 47
3329 22:18:26.583559
3330 22:18:26.583638 Set Vref, RX VrefLevel [Byte0]: 48
3331 22:18:26.587120 [Byte1]: 48
3332 22:18:26.591778
3333 22:18:26.591857 Set Vref, RX VrefLevel [Byte0]: 49
3334 22:18:26.595270 [Byte1]: 49
3335 22:18:26.599854
3336 22:18:26.599933 Set Vref, RX VrefLevel [Byte0]: 50
3337 22:18:26.602637 [Byte1]: 50
3338 22:18:26.607800
3339 22:18:26.607879 Set Vref, RX VrefLevel [Byte0]: 51
3340 22:18:26.611135 [Byte1]: 51
3341 22:18:26.615067
3342 22:18:26.615146 Set Vref, RX VrefLevel [Byte0]: 52
3343 22:18:26.618390 [Byte1]: 52
3344 22:18:26.622871
3345 22:18:26.622950 Set Vref, RX VrefLevel [Byte0]: 53
3346 22:18:26.626320 [Byte1]: 53
3347 22:18:26.631257
3348 22:18:26.631336 Set Vref, RX VrefLevel [Byte0]: 54
3349 22:18:26.634372 [Byte1]: 54
3350 22:18:26.638527
3351 22:18:26.638609 Set Vref, RX VrefLevel [Byte0]: 55
3352 22:18:26.642116 [Byte1]: 55
3353 22:18:26.646766
3354 22:18:26.646874 Set Vref, RX VrefLevel [Byte0]: 56
3355 22:18:26.649683 [Byte1]: 56
3356 22:18:26.654397
3357 22:18:26.654516 Set Vref, RX VrefLevel [Byte0]: 57
3358 22:18:26.658012 [Byte1]: 57
3359 22:18:26.662265
3360 22:18:26.662352 Set Vref, RX VrefLevel [Byte0]: 58
3361 22:18:26.665635 [Byte1]: 58
3362 22:18:26.670011
3363 22:18:26.670093 Set Vref, RX VrefLevel [Byte0]: 59
3364 22:18:26.673427 [Byte1]: 59
3365 22:18:26.677851
3366 22:18:26.677931 Set Vref, RX VrefLevel [Byte0]: 60
3367 22:18:26.681339 [Byte1]: 60
3368 22:18:26.685668
3369 22:18:26.685749 Set Vref, RX VrefLevel [Byte0]: 61
3370 22:18:26.689300 [Byte1]: 61
3371 22:18:26.693327
3372 22:18:26.693407 Set Vref, RX VrefLevel [Byte0]: 62
3373 22:18:26.697024 [Byte1]: 62
3374 22:18:26.701266
3375 22:18:26.701373 Set Vref, RX VrefLevel [Byte0]: 63
3376 22:18:26.705183 [Byte1]: 63
3377 22:18:26.709467
3378 22:18:26.709606 Set Vref, RX VrefLevel [Byte0]: 64
3379 22:18:26.712534 [Byte1]: 64
3380 22:18:26.717376
3381 22:18:26.717457 Set Vref, RX VrefLevel [Byte0]: 65
3382 22:18:26.720447 [Byte1]: 65
3383 22:18:26.725356
3384 22:18:26.725463 Set Vref, RX VrefLevel [Byte0]: 66
3385 22:18:26.728668 [Byte1]: 66
3386 22:18:26.733040
3387 22:18:26.736307 Set Vref, RX VrefLevel [Byte0]: 67
3388 22:18:26.736389 [Byte1]: 67
3389 22:18:26.740999
3390 22:18:26.741105 Set Vref, RX VrefLevel [Byte0]: 68
3391 22:18:26.744057 [Byte1]: 68
3392 22:18:26.748891
3393 22:18:26.748973 Final RX Vref Byte 0 = 56 to rank0
3394 22:18:26.752109 Final RX Vref Byte 1 = 52 to rank0
3395 22:18:26.755295 Final RX Vref Byte 0 = 56 to rank1
3396 22:18:26.759055 Final RX Vref Byte 1 = 52 to rank1==
3397 22:18:26.762042 Dram Type= 6, Freq= 0, CH_1, rank 0
3398 22:18:26.768900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3399 22:18:26.768982 ==
3400 22:18:26.769047 DQS Delay:
3401 22:18:26.769106 DQS0 = 0, DQS1 = 0
3402 22:18:26.772333 DQM Delay:
3403 22:18:26.772491 DQM0 = 120, DQM1 = 117
3404 22:18:26.775450 DQ Delay:
3405 22:18:26.779007 DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =118
3406 22:18:26.782319 DQ4 =122, DQ5 =128, DQ6 =128, DQ7 =120
3407 22:18:26.785305 DQ8 =104, DQ9 =106, DQ10 =118, DQ11 =112
3408 22:18:26.788948 DQ12 =124, DQ13 =124, DQ14 =124, DQ15 =126
3409 22:18:26.789060
3410 22:18:26.789124
3411 22:18:26.795528 [DQSOSCAuto] RK0, (LSB)MR18= 0x316, (MSB)MR19= 0x404, tDQSOscB0 = 401 ps tDQSOscB1 = 408 ps
3412 22:18:26.799085 CH1 RK0: MR19=404, MR18=316
3413 22:18:26.805444 CH1_RK0: MR19=0x404, MR18=0x316, DQSOSC=401, MR23=63, INC=40, DEC=27
3414 22:18:26.805546
3415 22:18:26.809001 ----->DramcWriteLeveling(PI) begin...
3416 22:18:26.809084 ==
3417 22:18:26.812217 Dram Type= 6, Freq= 0, CH_1, rank 1
3418 22:18:26.815902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3419 22:18:26.815984 ==
3420 22:18:26.819319 Write leveling (Byte 0): 25 => 25
3421 22:18:26.822219 Write leveling (Byte 1): 28 => 28
3422 22:18:26.825464 DramcWriteLeveling(PI) end<-----
3423 22:18:26.825585
3424 22:18:26.825650 ==
3425 22:18:26.829031 Dram Type= 6, Freq= 0, CH_1, rank 1
3426 22:18:26.835250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3427 22:18:26.835331 ==
3428 22:18:26.835404 [Gating] SW mode calibration
3429 22:18:26.845280 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3430 22:18:26.848689 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3431 22:18:26.852008 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3432 22:18:26.859208 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3433 22:18:26.862212 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3434 22:18:26.865549 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3435 22:18:26.872293 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3436 22:18:26.875317 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3437 22:18:26.878878 0 15 24 | B1->B0 | 2a2a 3434 | 0 0 | (1 0) (0 1)
3438 22:18:26.885291 0 15 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (1 0)
3439 22:18:26.888898 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3440 22:18:26.892372 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3441 22:18:26.895399 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3442 22:18:26.902600 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3443 22:18:26.905738 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3444 22:18:26.909001 1 0 20 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
3445 22:18:26.915523 1 0 24 | B1->B0 | 4040 2626 | 0 0 | (0 0) (0 0)
3446 22:18:26.919162 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3447 22:18:26.922247 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3448 22:18:26.928756 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3449 22:18:26.932389 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3450 22:18:26.935723 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3451 22:18:26.942319 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3452 22:18:26.945827 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3453 22:18:26.949395 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3454 22:18:26.955925 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3455 22:18:26.958849 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3456 22:18:26.962460 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3457 22:18:26.969038 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3458 22:18:26.972304 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3459 22:18:26.975478 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3460 22:18:26.982613 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3461 22:18:26.985518 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3462 22:18:26.989146 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3463 22:18:26.992072 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3464 22:18:26.998974 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3465 22:18:27.002325 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3466 22:18:27.005624 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3467 22:18:27.012122 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3468 22:18:27.015504 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3469 22:18:27.018467 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3470 22:18:27.025209 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3471 22:18:27.028847 Total UI for P1: 0, mck2ui 16
3472 22:18:27.031839 best dqsien dly found for B1: ( 1, 3, 24)
3473 22:18:27.035361 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3474 22:18:27.038538 Total UI for P1: 0, mck2ui 16
3475 22:18:27.041899 best dqsien dly found for B0: ( 1, 3, 26)
3476 22:18:27.045644 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3477 22:18:27.048604 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3478 22:18:27.048679
3479 22:18:27.052112 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3480 22:18:27.055480 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3481 22:18:27.058786 [Gating] SW calibration Done
3482 22:18:27.058864 ==
3483 22:18:27.062274 Dram Type= 6, Freq= 0, CH_1, rank 1
3484 22:18:27.065609 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3485 22:18:27.068705 ==
3486 22:18:27.068787 RX Vref Scan: 0
3487 22:18:27.068851
3488 22:18:27.072311 RX Vref 0 -> 0, step: 1
3489 22:18:27.072383
3490 22:18:27.075494 RX Delay -40 -> 252, step: 8
3491 22:18:27.078571 iDelay=208, Bit 0, Center 123 (56 ~ 191) 136
3492 22:18:27.081937 iDelay=208, Bit 1, Center 119 (56 ~ 183) 128
3493 22:18:27.085501 iDelay=208, Bit 2, Center 107 (40 ~ 175) 136
3494 22:18:27.088531 iDelay=208, Bit 3, Center 119 (56 ~ 183) 128
3495 22:18:27.095615 iDelay=208, Bit 4, Center 119 (56 ~ 183) 128
3496 22:18:27.098787 iDelay=208, Bit 5, Center 135 (64 ~ 207) 144
3497 22:18:27.102181 iDelay=208, Bit 6, Center 131 (64 ~ 199) 136
3498 22:18:27.105080 iDelay=208, Bit 7, Center 123 (56 ~ 191) 136
3499 22:18:27.108570 iDelay=208, Bit 8, Center 103 (40 ~ 167) 128
3500 22:18:27.115146 iDelay=208, Bit 9, Center 107 (40 ~ 175) 136
3501 22:18:27.118378 iDelay=208, Bit 10, Center 119 (48 ~ 191) 144
3502 22:18:27.121665 iDelay=208, Bit 11, Center 115 (48 ~ 183) 136
3503 22:18:27.125338 iDelay=208, Bit 12, Center 127 (56 ~ 199) 144
3504 22:18:27.128269 iDelay=208, Bit 13, Center 127 (64 ~ 191) 128
3505 22:18:27.134898 iDelay=208, Bit 14, Center 123 (56 ~ 191) 136
3506 22:18:27.138502 iDelay=208, Bit 15, Center 123 (56 ~ 191) 136
3507 22:18:27.138577 ==
3508 22:18:27.141558 Dram Type= 6, Freq= 0, CH_1, rank 1
3509 22:18:27.145206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3510 22:18:27.145283 ==
3511 22:18:27.148241 DQS Delay:
3512 22:18:27.148313 DQS0 = 0, DQS1 = 0
3513 22:18:27.148375 DQM Delay:
3514 22:18:27.151428 DQM0 = 122, DQM1 = 118
3515 22:18:27.151533 DQ Delay:
3516 22:18:27.155030 DQ0 =123, DQ1 =119, DQ2 =107, DQ3 =119
3517 22:18:27.158262 DQ4 =119, DQ5 =135, DQ6 =131, DQ7 =123
3518 22:18:27.165006 DQ8 =103, DQ9 =107, DQ10 =119, DQ11 =115
3519 22:18:27.168104 DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =123
3520 22:18:27.168179
3521 22:18:27.168249
3522 22:18:27.168311 ==
3523 22:18:27.171406 Dram Type= 6, Freq= 0, CH_1, rank 1
3524 22:18:27.175109 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3525 22:18:27.175193 ==
3526 22:18:27.175259
3527 22:18:27.175320
3528 22:18:27.178113 TX Vref Scan disable
3529 22:18:27.181889 == TX Byte 0 ==
3530 22:18:27.184724 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3531 22:18:27.188106 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3532 22:18:27.191379 == TX Byte 1 ==
3533 22:18:27.195008 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3534 22:18:27.198675 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3535 22:18:27.198759 ==
3536 22:18:27.201485 Dram Type= 6, Freq= 0, CH_1, rank 1
3537 22:18:27.204949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3538 22:18:27.205033 ==
3539 22:18:27.217852 TX Vref=22, minBit 9, minWin=25, winSum=421
3540 22:18:27.221206 TX Vref=24, minBit 2, minWin=26, winSum=425
3541 22:18:27.224862 TX Vref=26, minBit 10, minWin=25, winSum=428
3542 22:18:27.227674 TX Vref=28, minBit 2, minWin=26, winSum=433
3543 22:18:27.231253 TX Vref=30, minBit 9, minWin=26, winSum=435
3544 22:18:27.238183 TX Vref=32, minBit 9, minWin=26, winSum=435
3545 22:18:27.241009 [TxChooseVref] Worse bit 9, Min win 26, Win sum 435, Final Vref 30
3546 22:18:27.241093
3547 22:18:27.244559 Final TX Range 1 Vref 30
3548 22:18:27.244643
3549 22:18:27.244709 ==
3550 22:18:27.247496 Dram Type= 6, Freq= 0, CH_1, rank 1
3551 22:18:27.250733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3552 22:18:27.250810 ==
3553 22:18:27.254113
3554 22:18:27.254183
3555 22:18:27.254253 TX Vref Scan disable
3556 22:18:27.257739 == TX Byte 0 ==
3557 22:18:27.261167 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3558 22:18:27.267440 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3559 22:18:27.267514 == TX Byte 1 ==
3560 22:18:27.270918 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3561 22:18:27.277768 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3562 22:18:27.277843
3563 22:18:27.277906 [DATLAT]
3564 22:18:27.277975 Freq=1200, CH1 RK1
3565 22:18:27.278038
3566 22:18:27.280621 DATLAT Default: 0xd
3567 22:18:27.280690 0, 0xFFFF, sum = 0
3568 22:18:27.284411 1, 0xFFFF, sum = 0
3569 22:18:27.287380 2, 0xFFFF, sum = 0
3570 22:18:27.287456 3, 0xFFFF, sum = 0
3571 22:18:27.290765 4, 0xFFFF, sum = 0
3572 22:18:27.290842 5, 0xFFFF, sum = 0
3573 22:18:27.294408 6, 0xFFFF, sum = 0
3574 22:18:27.294479 7, 0xFFFF, sum = 0
3575 22:18:27.297559 8, 0xFFFF, sum = 0
3576 22:18:27.297631 9, 0xFFFF, sum = 0
3577 22:18:27.300576 10, 0xFFFF, sum = 0
3578 22:18:27.300646 11, 0xFFFF, sum = 0
3579 22:18:27.304002 12, 0x0, sum = 1
3580 22:18:27.304080 13, 0x0, sum = 2
3581 22:18:27.307177 14, 0x0, sum = 3
3582 22:18:27.307246 15, 0x0, sum = 4
3583 22:18:27.310707 best_step = 13
3584 22:18:27.310778
3585 22:18:27.310842 ==
3586 22:18:27.314138 Dram Type= 6, Freq= 0, CH_1, rank 1
3587 22:18:27.317099 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3588 22:18:27.317177 ==
3589 22:18:27.317239 RX Vref Scan: 0
3590 22:18:27.317301
3591 22:18:27.320837 RX Vref 0 -> 0, step: 1
3592 22:18:27.320904
3593 22:18:27.323915 RX Delay -5 -> 252, step: 4
3594 22:18:27.327433 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3595 22:18:27.333760 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3596 22:18:27.337582 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3597 22:18:27.340509 iDelay=195, Bit 3, Center 116 (59 ~ 174) 116
3598 22:18:27.344146 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3599 22:18:27.347221 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3600 22:18:27.353780 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3601 22:18:27.357247 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3602 22:18:27.360807 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
3603 22:18:27.364203 iDelay=195, Bit 9, Center 108 (47 ~ 170) 124
3604 22:18:27.367423 iDelay=195, Bit 10, Center 116 (55 ~ 178) 124
3605 22:18:27.373529 iDelay=195, Bit 11, Center 112 (51 ~ 174) 124
3606 22:18:27.376917 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3607 22:18:27.380845 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3608 22:18:27.383817 iDelay=195, Bit 14, Center 124 (67 ~ 182) 116
3609 22:18:27.390598 iDelay=195, Bit 15, Center 128 (67 ~ 190) 124
3610 22:18:27.390680 ==
3611 22:18:27.393705 Dram Type= 6, Freq= 0, CH_1, rank 1
3612 22:18:27.397430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3613 22:18:27.397573 ==
3614 22:18:27.397669 DQS Delay:
3615 22:18:27.400106 DQS0 = 0, DQS1 = 0
3616 22:18:27.400187 DQM Delay:
3617 22:18:27.403615 DQM0 = 120, DQM1 = 118
3618 22:18:27.403696 DQ Delay:
3619 22:18:27.406671 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =116
3620 22:18:27.410340 DQ4 =116, DQ5 =130, DQ6 =130, DQ7 =120
3621 22:18:27.413664 DQ8 =106, DQ9 =108, DQ10 =116, DQ11 =112
3622 22:18:27.416729 DQ12 =126, DQ13 =124, DQ14 =124, DQ15 =128
3623 22:18:27.416810
3624 22:18:27.416874
3625 22:18:27.427040 [DQSOSCAuto] RK1, (LSB)MR18= 0xfed, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 404 ps
3626 22:18:27.430120 CH1 RK1: MR19=403, MR18=FED
3627 22:18:27.433427 CH1_RK1: MR19=0x403, MR18=0xFED, DQSOSC=404, MR23=63, INC=40, DEC=26
3628 22:18:27.436593 [RxdqsGatingPostProcess] freq 1200
3629 22:18:27.443668 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3630 22:18:27.446933 best DQS0 dly(2T, 0.5T) = (0, 11)
3631 22:18:27.449967 best DQS1 dly(2T, 0.5T) = (0, 11)
3632 22:18:27.453762 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3633 22:18:27.456633 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3634 22:18:27.460164 best DQS0 dly(2T, 0.5T) = (0, 11)
3635 22:18:27.463184 best DQS1 dly(2T, 0.5T) = (0, 11)
3636 22:18:27.467123 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3637 22:18:27.469912 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3638 22:18:27.469993 Pre-setting of DQS Precalculation
3639 22:18:27.477035 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3640 22:18:27.483292 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3641 22:18:27.489851 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3642 22:18:27.489933
3643 22:18:27.489997
3644 22:18:27.493600 [Calibration Summary] 2400 Mbps
3645 22:18:27.497106 CH 0, Rank 0
3646 22:18:27.497187 SW Impedance : PASS
3647 22:18:27.500187 DUTY Scan : NO K
3648 22:18:27.503138 ZQ Calibration : PASS
3649 22:18:27.503219 Jitter Meter : NO K
3650 22:18:27.506700 CBT Training : PASS
3651 22:18:27.506782 Write leveling : PASS
3652 22:18:27.510364 RX DQS gating : PASS
3653 22:18:27.513448 RX DQ/DQS(RDDQC) : PASS
3654 22:18:27.513536 TX DQ/DQS : PASS
3655 22:18:27.516780 RX DATLAT : PASS
3656 22:18:27.519796 RX DQ/DQS(Engine): PASS
3657 22:18:27.519878 TX OE : NO K
3658 22:18:27.523247 All Pass.
3659 22:18:27.523328
3660 22:18:27.523391 CH 0, Rank 1
3661 22:18:27.526681 SW Impedance : PASS
3662 22:18:27.526762 DUTY Scan : NO K
3663 22:18:27.529870 ZQ Calibration : PASS
3664 22:18:27.533167 Jitter Meter : NO K
3665 22:18:27.533274 CBT Training : PASS
3666 22:18:27.536999 Write leveling : PASS
3667 22:18:27.539796 RX DQS gating : PASS
3668 22:18:27.539877 RX DQ/DQS(RDDQC) : PASS
3669 22:18:27.543441 TX DQ/DQS : PASS
3670 22:18:27.546439 RX DATLAT : PASS
3671 22:18:27.546520 RX DQ/DQS(Engine): PASS
3672 22:18:27.550080 TX OE : NO K
3673 22:18:27.550161 All Pass.
3674 22:18:27.550225
3675 22:18:27.553003 CH 1, Rank 0
3676 22:18:27.553084 SW Impedance : PASS
3677 22:18:27.556675 DUTY Scan : NO K
3678 22:18:27.556793 ZQ Calibration : PASS
3679 22:18:27.560310 Jitter Meter : NO K
3680 22:18:27.563243 CBT Training : PASS
3681 22:18:27.563324 Write leveling : PASS
3682 22:18:27.566444 RX DQS gating : PASS
3683 22:18:27.569784 RX DQ/DQS(RDDQC) : PASS
3684 22:18:27.569889 TX DQ/DQS : PASS
3685 22:18:27.573120 RX DATLAT : PASS
3686 22:18:27.576490 RX DQ/DQS(Engine): PASS
3687 22:18:27.576572 TX OE : NO K
3688 22:18:27.579947 All Pass.
3689 22:18:27.580028
3690 22:18:27.580091 CH 1, Rank 1
3691 22:18:27.583376 SW Impedance : PASS
3692 22:18:27.583456 DUTY Scan : NO K
3693 22:18:27.586840 ZQ Calibration : PASS
3694 22:18:27.590473 Jitter Meter : NO K
3695 22:18:27.590554 CBT Training : PASS
3696 22:18:27.593086 Write leveling : PASS
3697 22:18:27.596511 RX DQS gating : PASS
3698 22:18:27.596593 RX DQ/DQS(RDDQC) : PASS
3699 22:18:27.600111 TX DQ/DQS : PASS
3700 22:18:27.600192 RX DATLAT : PASS
3701 22:18:27.603331 RX DQ/DQS(Engine): PASS
3702 22:18:27.606275 TX OE : NO K
3703 22:18:27.606362 All Pass.
3704 22:18:27.606427
3705 22:18:27.609917 DramC Write-DBI off
3706 22:18:27.612944 PER_BANK_REFRESH: Hybrid Mode
3707 22:18:27.613028 TX_TRACKING: ON
3708 22:18:27.623233 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3709 22:18:27.626651 [FAST_K] Save calibration result to emmc
3710 22:18:27.630176 dramc_set_vcore_voltage set vcore to 650000
3711 22:18:27.630257 Read voltage for 600, 5
3712 22:18:27.632924 Vio18 = 0
3713 22:18:27.633005 Vcore = 650000
3714 22:18:27.633069 Vdram = 0
3715 22:18:27.636722 Vddq = 0
3716 22:18:27.636821 Vmddr = 0
3717 22:18:27.639824 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3718 22:18:27.647010 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3719 22:18:27.649770 MEM_TYPE=3, freq_sel=19
3720 22:18:27.653403 sv_algorithm_assistance_LP4_1600
3721 22:18:27.656469 ============ PULL DRAM RESETB DOWN ============
3722 22:18:27.659814 ========== PULL DRAM RESETB DOWN end =========
3723 22:18:27.666394 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3724 22:18:27.669767 ===================================
3725 22:18:27.669849 LPDDR4 DRAM CONFIGURATION
3726 22:18:27.673226 ===================================
3727 22:18:27.676482 EX_ROW_EN[0] = 0x0
3728 22:18:27.676564 EX_ROW_EN[1] = 0x0
3729 22:18:27.679771 LP4Y_EN = 0x0
3730 22:18:27.679852 WORK_FSP = 0x0
3731 22:18:27.683321 WL = 0x2
3732 22:18:27.686648 RL = 0x2
3733 22:18:27.686730 BL = 0x2
3734 22:18:27.689755 RPST = 0x0
3735 22:18:27.689836 RD_PRE = 0x0
3736 22:18:27.692760 WR_PRE = 0x1
3737 22:18:27.692840 WR_PST = 0x0
3738 22:18:27.696879 DBI_WR = 0x0
3739 22:18:27.696961 DBI_RD = 0x0
3740 22:18:27.699588 OTF = 0x1
3741 22:18:27.703004 ===================================
3742 22:18:27.706546 ===================================
3743 22:18:27.706633 ANA top config
3744 22:18:27.709620 ===================================
3745 22:18:27.712703 DLL_ASYNC_EN = 0
3746 22:18:27.716315 ALL_SLAVE_EN = 1
3747 22:18:27.716396 NEW_RANK_MODE = 1
3748 22:18:27.719695 DLL_IDLE_MODE = 1
3749 22:18:27.723216 LP45_APHY_COMB_EN = 1
3750 22:18:27.726127 TX_ODT_DIS = 1
3751 22:18:27.726209 NEW_8X_MODE = 1
3752 22:18:27.729986 ===================================
3753 22:18:27.732865 ===================================
3754 22:18:27.736224 data_rate = 1200
3755 22:18:27.739795 CKR = 1
3756 22:18:27.742656 DQ_P2S_RATIO = 8
3757 22:18:27.746030 ===================================
3758 22:18:27.749400 CA_P2S_RATIO = 8
3759 22:18:27.752768 DQ_CA_OPEN = 0
3760 22:18:27.752877 DQ_SEMI_OPEN = 0
3761 22:18:27.756482 CA_SEMI_OPEN = 0
3762 22:18:27.759286 CA_FULL_RATE = 0
3763 22:18:27.763148 DQ_CKDIV4_EN = 1
3764 22:18:27.766005 CA_CKDIV4_EN = 1
3765 22:18:27.769517 CA_PREDIV_EN = 0
3766 22:18:27.769609 PH8_DLY = 0
3767 22:18:27.773220 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3768 22:18:27.776495 DQ_AAMCK_DIV = 4
3769 22:18:27.778989 CA_AAMCK_DIV = 4
3770 22:18:27.782366 CA_ADMCK_DIV = 4
3771 22:18:27.785784 DQ_TRACK_CA_EN = 0
3772 22:18:27.789152 CA_PICK = 600
3773 22:18:27.789254 CA_MCKIO = 600
3774 22:18:27.792477 MCKIO_SEMI = 0
3775 22:18:27.796190 PLL_FREQ = 2288
3776 22:18:27.799403 DQ_UI_PI_RATIO = 32
3777 22:18:27.802490 CA_UI_PI_RATIO = 0
3778 22:18:27.805931 ===================================
3779 22:18:27.809268 ===================================
3780 22:18:27.812759 memory_type:LPDDR4
3781 22:18:27.812866 GP_NUM : 10
3782 22:18:27.815823 SRAM_EN : 1
3783 22:18:27.815926 MD32_EN : 0
3784 22:18:27.819463 ===================================
3785 22:18:27.822436 [ANA_INIT] >>>>>>>>>>>>>>
3786 22:18:27.826085 <<<<<< [CONFIGURE PHASE]: ANA_TX
3787 22:18:27.829270 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3788 22:18:27.832730 ===================================
3789 22:18:27.835659 data_rate = 1200,PCW = 0X5800
3790 22:18:27.838963 ===================================
3791 22:18:27.842507 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3792 22:18:27.845520 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3793 22:18:27.852375 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3794 22:18:27.859232 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3795 22:18:27.862383 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3796 22:18:27.865682 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3797 22:18:27.865763 [ANA_INIT] flow start
3798 22:18:27.869439 [ANA_INIT] PLL >>>>>>>>
3799 22:18:27.872588 [ANA_INIT] PLL <<<<<<<<
3800 22:18:27.872660 [ANA_INIT] MIDPI >>>>>>>>
3801 22:18:27.875826 [ANA_INIT] MIDPI <<<<<<<<
3802 22:18:27.879287 [ANA_INIT] DLL >>>>>>>>
3803 22:18:27.879361 [ANA_INIT] flow end
3804 22:18:27.885500 ============ LP4 DIFF to SE enter ============
3805 22:18:27.888904 ============ LP4 DIFF to SE exit ============
3806 22:18:27.888985 [ANA_INIT] <<<<<<<<<<<<<
3807 22:18:27.892002 [Flow] Enable top DCM control >>>>>
3808 22:18:27.895712 [Flow] Enable top DCM control <<<<<
3809 22:18:27.898899 Enable DLL master slave shuffle
3810 22:18:27.905921 ==============================================================
3811 22:18:27.906003 Gating Mode config
3812 22:18:27.912597 ==============================================================
3813 22:18:27.915524 Config description:
3814 22:18:27.925705 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3815 22:18:27.932313 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3816 22:18:27.935832 SELPH_MODE 0: By rank 1: By Phase
3817 22:18:27.942535 ==============================================================
3818 22:18:27.945275 GAT_TRACK_EN = 1
3819 22:18:27.948869 RX_GATING_MODE = 2
3820 22:18:27.948950 RX_GATING_TRACK_MODE = 2
3821 22:18:27.952140 SELPH_MODE = 1
3822 22:18:27.955650 PICG_EARLY_EN = 1
3823 22:18:27.959201 VALID_LAT_VALUE = 1
3824 22:18:27.965337 ==============================================================
3825 22:18:27.969028 Enter into Gating configuration >>>>
3826 22:18:27.971836 Exit from Gating configuration <<<<
3827 22:18:27.975518 Enter into DVFS_PRE_config >>>>>
3828 22:18:27.985478 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3829 22:18:27.988607 Exit from DVFS_PRE_config <<<<<
3830 22:18:27.992148 Enter into PICG configuration >>>>
3831 22:18:27.995396 Exit from PICG configuration <<<<
3832 22:18:27.998992 [RX_INPUT] configuration >>>>>
3833 22:18:28.001987 [RX_INPUT] configuration <<<<<
3834 22:18:28.005498 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3835 22:18:28.012256 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3836 22:18:28.018516 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3837 22:18:28.024976 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3838 22:18:28.028576 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3839 22:18:28.035011 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3840 22:18:28.038512 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3841 22:18:28.045092 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3842 22:18:28.048771 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3843 22:18:28.051576 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3844 22:18:28.055679 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3845 22:18:28.062039 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3846 22:18:28.065281 ===================================
3847 22:18:28.065363 LPDDR4 DRAM CONFIGURATION
3848 22:18:28.068408 ===================================
3849 22:18:28.072049 EX_ROW_EN[0] = 0x0
3850 22:18:28.074874 EX_ROW_EN[1] = 0x0
3851 22:18:28.074983 LP4Y_EN = 0x0
3852 22:18:28.078405 WORK_FSP = 0x0
3853 22:18:28.078484 WL = 0x2
3854 22:18:28.081453 RL = 0x2
3855 22:18:28.081582 BL = 0x2
3856 22:18:28.085124 RPST = 0x0
3857 22:18:28.085206 RD_PRE = 0x0
3858 22:18:28.088091 WR_PRE = 0x1
3859 22:18:28.088162 WR_PST = 0x0
3860 22:18:28.091731 DBI_WR = 0x0
3861 22:18:28.091803 DBI_RD = 0x0
3862 22:18:28.094824 OTF = 0x1
3863 22:18:28.098360 ===================================
3864 22:18:28.101919 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3865 22:18:28.104766 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3866 22:18:28.111526 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3867 22:18:28.114868 ===================================
3868 22:18:28.114948 LPDDR4 DRAM CONFIGURATION
3869 22:18:28.118288 ===================================
3870 22:18:28.121412 EX_ROW_EN[0] = 0x10
3871 22:18:28.124745 EX_ROW_EN[1] = 0x0
3872 22:18:28.124819 LP4Y_EN = 0x0
3873 22:18:28.128055 WORK_FSP = 0x0
3874 22:18:28.128128 WL = 0x2
3875 22:18:28.131621 RL = 0x2
3876 22:18:28.131705 BL = 0x2
3877 22:18:28.135002 RPST = 0x0
3878 22:18:28.135077 RD_PRE = 0x0
3879 22:18:28.138002 WR_PRE = 0x1
3880 22:18:28.138076 WR_PST = 0x0
3881 22:18:28.141235 DBI_WR = 0x0
3882 22:18:28.141308 DBI_RD = 0x0
3883 22:18:28.144723 OTF = 0x1
3884 22:18:28.147866 ===================================
3885 22:18:28.154529 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3886 22:18:28.157911 nWR fixed to 30
3887 22:18:28.158017 [ModeRegInit_LP4] CH0 RK0
3888 22:18:28.161709 [ModeRegInit_LP4] CH0 RK1
3889 22:18:28.164535 [ModeRegInit_LP4] CH1 RK0
3890 22:18:28.164626 [ModeRegInit_LP4] CH1 RK1
3891 22:18:28.167967 match AC timing 17
3892 22:18:28.171422 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3893 22:18:28.177935 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3894 22:18:28.181037 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3895 22:18:28.184912 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3896 22:18:28.191003 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3897 22:18:28.191080 ==
3898 22:18:28.194578 Dram Type= 6, Freq= 0, CH_0, rank 0
3899 22:18:28.198055 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3900 22:18:28.198155 ==
3901 22:18:28.204310 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3902 22:18:28.211095 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3903 22:18:28.214261 [CA 0] Center 35 (5~66) winsize 62
3904 22:18:28.218254 [CA 1] Center 35 (5~66) winsize 62
3905 22:18:28.221373 [CA 2] Center 33 (3~64) winsize 62
3906 22:18:28.224431 [CA 3] Center 33 (2~64) winsize 63
3907 22:18:28.227758 [CA 4] Center 33 (2~64) winsize 63
3908 22:18:28.227850 [CA 5] Center 32 (2~63) winsize 62
3909 22:18:28.231340
3910 22:18:28.234418 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3911 22:18:28.234510
3912 22:18:28.237911 [CATrainingPosCal] consider 1 rank data
3913 22:18:28.241421 u2DelayCellTimex100 = 270/100 ps
3914 22:18:28.244456 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3915 22:18:28.248029 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3916 22:18:28.250991 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3917 22:18:28.254501 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
3918 22:18:28.257621 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3919 22:18:28.261062 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3920 22:18:28.261165
3921 22:18:28.264485 CA PerBit enable=1, Macro0, CA PI delay=32
3922 22:18:28.264582
3923 22:18:28.267562 [CBTSetCACLKResult] CA Dly = 32
3924 22:18:28.270851 CS Dly: 5 (0~36)
3925 22:18:28.270949 ==
3926 22:18:28.274335 Dram Type= 6, Freq= 0, CH_0, rank 1
3927 22:18:28.277605 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3928 22:18:28.277678 ==
3929 22:18:28.284377 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3930 22:18:28.290880 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3931 22:18:28.294152 [CA 0] Center 35 (5~66) winsize 62
3932 22:18:28.297560 [CA 1] Center 35 (5~66) winsize 62
3933 22:18:28.300636 [CA 2] Center 34 (3~65) winsize 63
3934 22:18:28.304100 [CA 3] Center 33 (3~64) winsize 62
3935 22:18:28.307214 [CA 4] Center 32 (2~63) winsize 62
3936 22:18:28.311014 [CA 5] Center 32 (2~63) winsize 62
3937 22:18:28.311120
3938 22:18:28.314495 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3939 22:18:28.314569
3940 22:18:28.317702 [CATrainingPosCal] consider 2 rank data
3941 22:18:28.320511 u2DelayCellTimex100 = 270/100 ps
3942 22:18:28.324299 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3943 22:18:28.327504 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3944 22:18:28.330714 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3945 22:18:28.333905 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
3946 22:18:28.337402 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
3947 22:18:28.340579 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3948 22:18:28.340680
3949 22:18:28.348010 CA PerBit enable=1, Macro0, CA PI delay=32
3950 22:18:28.348112
3951 22:18:28.348208 [CBTSetCACLKResult] CA Dly = 32
3952 22:18:28.350619 CS Dly: 4 (0~35)
3953 22:18:28.350719
3954 22:18:28.354040 ----->DramcWriteLeveling(PI) begin...
3955 22:18:28.354143 ==
3956 22:18:28.357649 Dram Type= 6, Freq= 0, CH_0, rank 0
3957 22:18:28.360753 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3958 22:18:28.360835 ==
3959 22:18:28.364480 Write leveling (Byte 0): 33 => 33
3960 22:18:28.367535 Write leveling (Byte 1): 32 => 32
3961 22:18:28.371116 DramcWriteLeveling(PI) end<-----
3962 22:18:28.371197
3963 22:18:28.371262 ==
3964 22:18:28.373999 Dram Type= 6, Freq= 0, CH_0, rank 0
3965 22:18:28.377281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3966 22:18:28.380650 ==
3967 22:18:28.380732 [Gating] SW mode calibration
3968 22:18:28.390418 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3969 22:18:28.394009 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3970 22:18:28.396997 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3971 22:18:28.403698 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3972 22:18:28.406757 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
3973 22:18:28.410269 0 9 12 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 1)
3974 22:18:28.416863 0 9 16 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
3975 22:18:28.420354 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3976 22:18:28.423886 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3977 22:18:28.430109 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3978 22:18:28.433443 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3979 22:18:28.436746 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3980 22:18:28.444077 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3981 22:18:28.446879 0 10 12 | B1->B0 | 2323 3938 | 0 1 | (0 0) (0 0)
3982 22:18:28.450355 0 10 16 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
3983 22:18:28.457196 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3984 22:18:28.460031 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3985 22:18:28.463634 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3986 22:18:28.470113 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3987 22:18:28.473914 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3988 22:18:28.476787 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3989 22:18:28.483474 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3990 22:18:28.486716 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3991 22:18:28.489948 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3992 22:18:28.493285 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3993 22:18:28.500456 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3994 22:18:28.503301 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3995 22:18:28.506467 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3996 22:18:28.513146 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3997 22:18:28.516721 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3998 22:18:28.520154 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3999 22:18:28.526807 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4000 22:18:28.530174 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4001 22:18:28.533467 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4002 22:18:28.540078 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 22:18:28.543569 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 22:18:28.546379 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 22:18:28.553062 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4006 22:18:28.556748 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4007 22:18:28.559979 Total UI for P1: 0, mck2ui 16
4008 22:18:28.563143 best dqsien dly found for B0: ( 0, 13, 12)
4009 22:18:28.566490 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4010 22:18:28.569648 Total UI for P1: 0, mck2ui 16
4011 22:18:28.573274 best dqsien dly found for B1: ( 0, 13, 14)
4012 22:18:28.576406 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4013 22:18:28.579895 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4014 22:18:28.579976
4015 22:18:28.586257 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4016 22:18:28.590058 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4017 22:18:28.590140 [Gating] SW calibration Done
4018 22:18:28.593432 ==
4019 22:18:28.596563 Dram Type= 6, Freq= 0, CH_0, rank 0
4020 22:18:28.599635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4021 22:18:28.599707 ==
4022 22:18:28.599769 RX Vref Scan: 0
4023 22:18:28.599827
4024 22:18:28.603163 RX Vref 0 -> 0, step: 1
4025 22:18:28.603235
4026 22:18:28.606284 RX Delay -230 -> 252, step: 16
4027 22:18:28.609921 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4028 22:18:28.612979 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4029 22:18:28.619542 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4030 22:18:28.623200 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4031 22:18:28.626300 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4032 22:18:28.629694 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4033 22:18:28.636116 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4034 22:18:28.639816 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4035 22:18:28.642877 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4036 22:18:28.646274 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4037 22:18:28.649547 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4038 22:18:28.656794 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4039 22:18:28.659497 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4040 22:18:28.662875 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4041 22:18:28.666413 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4042 22:18:28.673387 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4043 22:18:28.673472 ==
4044 22:18:28.676273 Dram Type= 6, Freq= 0, CH_0, rank 0
4045 22:18:28.679850 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4046 22:18:28.679937 ==
4047 22:18:28.680019 DQS Delay:
4048 22:18:28.682969 DQS0 = 0, DQS1 = 0
4049 22:18:28.683050 DQM Delay:
4050 22:18:28.686417 DQM0 = 52, DQM1 = 46
4051 22:18:28.686498 DQ Delay:
4052 22:18:28.689831 DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =49
4053 22:18:28.692916 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57
4054 22:18:28.696091 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4055 22:18:28.699861 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =57
4056 22:18:28.699943
4057 22:18:28.700006
4058 22:18:28.700068 ==
4059 22:18:28.702819 Dram Type= 6, Freq= 0, CH_0, rank 0
4060 22:18:28.706081 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4061 22:18:28.706163 ==
4062 22:18:28.709196
4063 22:18:28.709277
4064 22:18:28.709340 TX Vref Scan disable
4065 22:18:28.712787 == TX Byte 0 ==
4066 22:18:28.715900 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4067 22:18:28.719246 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4068 22:18:28.722944 == TX Byte 1 ==
4069 22:18:28.726021 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4070 22:18:28.729788 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4071 22:18:28.729870 ==
4072 22:18:28.732714 Dram Type= 6, Freq= 0, CH_0, rank 0
4073 22:18:28.739321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4074 22:18:28.739404 ==
4075 22:18:28.739469
4076 22:18:28.739528
4077 22:18:28.739586 TX Vref Scan disable
4078 22:18:28.743860 == TX Byte 0 ==
4079 22:18:28.747043 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4080 22:18:28.753683 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4081 22:18:28.753765 == TX Byte 1 ==
4082 22:18:28.757243 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4083 22:18:28.763822 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4084 22:18:28.763906
4085 22:18:28.763972 [DATLAT]
4086 22:18:28.764032 Freq=600, CH0 RK0
4087 22:18:28.764092
4088 22:18:28.767063 DATLAT Default: 0x9
4089 22:18:28.767145 0, 0xFFFF, sum = 0
4090 22:18:28.770433 1, 0xFFFF, sum = 0
4091 22:18:28.773686 2, 0xFFFF, sum = 0
4092 22:18:28.773775 3, 0xFFFF, sum = 0
4093 22:18:28.777194 4, 0xFFFF, sum = 0
4094 22:18:28.777278 5, 0xFFFF, sum = 0
4095 22:18:28.780251 6, 0xFFFF, sum = 0
4096 22:18:28.780345 7, 0xFFFF, sum = 0
4097 22:18:28.783595 8, 0x0, sum = 1
4098 22:18:28.783707 9, 0x0, sum = 2
4099 22:18:28.783807 10, 0x0, sum = 3
4100 22:18:28.787246 11, 0x0, sum = 4
4101 22:18:28.787341 best_step = 9
4102 22:18:28.787409
4103 22:18:28.787470 ==
4104 22:18:28.790235 Dram Type= 6, Freq= 0, CH_0, rank 0
4105 22:18:28.796679 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4106 22:18:28.796779 ==
4107 22:18:28.796878 RX Vref Scan: 1
4108 22:18:28.796966
4109 22:18:28.800083 RX Vref 0 -> 0, step: 1
4110 22:18:28.800156
4111 22:18:28.803813 RX Delay -163 -> 252, step: 8
4112 22:18:28.803929
4113 22:18:28.806558 Set Vref, RX VrefLevel [Byte0]: 56
4114 22:18:28.809955 [Byte1]: 47
4115 22:18:28.810053
4116 22:18:28.813951 Final RX Vref Byte 0 = 56 to rank0
4117 22:18:28.816457 Final RX Vref Byte 1 = 47 to rank0
4118 22:18:28.820026 Final RX Vref Byte 0 = 56 to rank1
4119 22:18:28.823612 Final RX Vref Byte 1 = 47 to rank1==
4120 22:18:28.826756 Dram Type= 6, Freq= 0, CH_0, rank 0
4121 22:18:28.829695 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4122 22:18:28.829769 ==
4123 22:18:28.833123 DQS Delay:
4124 22:18:28.833222 DQS0 = 0, DQS1 = 0
4125 22:18:28.836296 DQM Delay:
4126 22:18:28.836404 DQM0 = 54, DQM1 = 46
4127 22:18:28.836496 DQ Delay:
4128 22:18:28.840135 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4129 22:18:28.843154 DQ4 =56, DQ5 =44, DQ6 =60, DQ7 =64
4130 22:18:28.847031 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40
4131 22:18:28.849720 DQ12 =56, DQ13 =48, DQ14 =56, DQ15 =52
4132 22:18:28.849818
4133 22:18:28.849887
4134 22:18:28.859924 [DQSOSCAuto] RK0, (LSB)MR18= 0x6e61, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 389 ps
4135 22:18:28.863616 CH0 RK0: MR19=808, MR18=6E61
4136 22:18:28.869666 CH0_RK0: MR19=0x808, MR18=0x6E61, DQSOSC=389, MR23=63, INC=173, DEC=115
4137 22:18:28.869774
4138 22:18:28.873339 ----->DramcWriteLeveling(PI) begin...
4139 22:18:28.873459 ==
4140 22:18:28.876754 Dram Type= 6, Freq= 0, CH_0, rank 1
4141 22:18:28.880097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4142 22:18:28.880202 ==
4143 22:18:28.882912 Write leveling (Byte 0): 36 => 36
4144 22:18:28.886417 Write leveling (Byte 1): 32 => 32
4145 22:18:28.889718 DramcWriteLeveling(PI) end<-----
4146 22:18:28.889820
4147 22:18:28.889913 ==
4148 22:18:28.893258 Dram Type= 6, Freq= 0, CH_0, rank 1
4149 22:18:28.896445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4150 22:18:28.896549 ==
4151 22:18:28.899937 [Gating] SW mode calibration
4152 22:18:28.906509 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4153 22:18:28.912915 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4154 22:18:28.916152 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4155 22:18:28.919673 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4156 22:18:28.926246 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4157 22:18:28.930171 0 9 12 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 0)
4158 22:18:28.933404 0 9 16 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
4159 22:18:28.939739 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4160 22:18:28.943123 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4161 22:18:28.946199 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4162 22:18:28.949434 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4163 22:18:28.956877 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4164 22:18:28.959644 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4165 22:18:28.963056 0 10 12 | B1->B0 | 2424 2d2d | 0 0 | (0 0) (1 1)
4166 22:18:28.970056 0 10 16 | B1->B0 | 4343 4242 | 0 0 | (0 0) (0 0)
4167 22:18:28.973061 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4168 22:18:28.976228 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4169 22:18:28.983020 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4170 22:18:28.986497 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4171 22:18:28.989773 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4172 22:18:28.996529 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4173 22:18:28.999827 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4174 22:18:29.002663 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4175 22:18:29.009431 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4176 22:18:29.012731 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4177 22:18:29.016192 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4178 22:18:29.022911 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4179 22:18:29.026472 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4180 22:18:29.030119 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4181 22:18:29.036533 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4182 22:18:29.039719 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4183 22:18:29.042637 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4184 22:18:29.049797 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4185 22:18:29.052978 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4186 22:18:29.055910 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4187 22:18:29.059610 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4188 22:18:29.066550 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4189 22:18:29.069754 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4190 22:18:29.072807 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4191 22:18:29.076193 Total UI for P1: 0, mck2ui 16
4192 22:18:29.079525 best dqsien dly found for B1: ( 0, 13, 14)
4193 22:18:29.086108 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4194 22:18:29.086212 Total UI for P1: 0, mck2ui 16
4195 22:18:29.092711 best dqsien dly found for B0: ( 0, 13, 14)
4196 22:18:29.095977 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4197 22:18:29.099821 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4198 22:18:29.099924
4199 22:18:29.102710 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4200 22:18:29.105734 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4201 22:18:29.109274 [Gating] SW calibration Done
4202 22:18:29.109381 ==
4203 22:18:29.112875 Dram Type= 6, Freq= 0, CH_0, rank 1
4204 22:18:29.116167 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4205 22:18:29.116269 ==
4206 22:18:29.119391 RX Vref Scan: 0
4207 22:18:29.119501
4208 22:18:29.119594 RX Vref 0 -> 0, step: 1
4209 22:18:29.122875
4210 22:18:29.122978 RX Delay -230 -> 252, step: 16
4211 22:18:29.129257 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4212 22:18:29.132841 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4213 22:18:29.135809 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4214 22:18:29.139336 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4215 22:18:29.145712 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4216 22:18:29.149174 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4217 22:18:29.152897 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4218 22:18:29.155908 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4219 22:18:29.159134 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4220 22:18:29.165824 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4221 22:18:29.169016 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4222 22:18:29.172544 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4223 22:18:29.175681 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4224 22:18:29.182702 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4225 22:18:29.186226 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4226 22:18:29.189498 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4227 22:18:29.189607 ==
4228 22:18:29.192430 Dram Type= 6, Freq= 0, CH_0, rank 1
4229 22:18:29.195785 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4230 22:18:29.195887 ==
4231 22:18:29.199183 DQS Delay:
4232 22:18:29.199281 DQS0 = 0, DQS1 = 0
4233 22:18:29.202444 DQM Delay:
4234 22:18:29.202539 DQM0 = 51, DQM1 = 43
4235 22:18:29.202615 DQ Delay:
4236 22:18:29.205460 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4237 22:18:29.208895 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57
4238 22:18:29.212438 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =33
4239 22:18:29.215483 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4240 22:18:29.215583
4241 22:18:29.219117
4242 22:18:29.219219 ==
4243 22:18:29.222224 Dram Type= 6, Freq= 0, CH_0, rank 1
4244 22:18:29.225449 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4245 22:18:29.225556 ==
4246 22:18:29.225651
4247 22:18:29.225740
4248 22:18:29.228876 TX Vref Scan disable
4249 22:18:29.228976 == TX Byte 0 ==
4250 22:18:29.235745 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
4251 22:18:29.238874 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
4252 22:18:29.238945 == TX Byte 1 ==
4253 22:18:29.245215 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4254 22:18:29.248633 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4255 22:18:29.248735 ==
4256 22:18:29.252238 Dram Type= 6, Freq= 0, CH_0, rank 1
4257 22:18:29.255255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4258 22:18:29.255353 ==
4259 22:18:29.255447
4260 22:18:29.255536
4261 22:18:29.258636 TX Vref Scan disable
4262 22:18:29.261936 == TX Byte 0 ==
4263 22:18:29.265204 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4264 22:18:29.268752 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4265 22:18:29.271779 == TX Byte 1 ==
4266 22:18:29.275362 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4267 22:18:29.278696 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4268 22:18:29.278795
4269 22:18:29.282286 [DATLAT]
4270 22:18:29.282386 Freq=600, CH0 RK1
4271 22:18:29.282478
4272 22:18:29.285015 DATLAT Default: 0x9
4273 22:18:29.285113 0, 0xFFFF, sum = 0
4274 22:18:29.288733 1, 0xFFFF, sum = 0
4275 22:18:29.288835 2, 0xFFFF, sum = 0
4276 22:18:29.292550 3, 0xFFFF, sum = 0
4277 22:18:29.292652 4, 0xFFFF, sum = 0
4278 22:18:29.295220 5, 0xFFFF, sum = 0
4279 22:18:29.295324 6, 0xFFFF, sum = 0
4280 22:18:29.298519 7, 0xFFFF, sum = 0
4281 22:18:29.298620 8, 0x0, sum = 1
4282 22:18:29.301909 9, 0x0, sum = 2
4283 22:18:29.302012 10, 0x0, sum = 3
4284 22:18:29.305491 11, 0x0, sum = 4
4285 22:18:29.305632 best_step = 9
4286 22:18:29.305720
4287 22:18:29.305781 ==
4288 22:18:29.308678 Dram Type= 6, Freq= 0, CH_0, rank 1
4289 22:18:29.315239 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4290 22:18:29.315343 ==
4291 22:18:29.315436 RX Vref Scan: 0
4292 22:18:29.315525
4293 22:18:29.318791 RX Vref 0 -> 0, step: 1
4294 22:18:29.318891
4295 22:18:29.321991 RX Delay -163 -> 252, step: 8
4296 22:18:29.324858 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4297 22:18:29.328297 iDelay=205, Bit 1, Center 56 (-83 ~ 196) 280
4298 22:18:29.335097 iDelay=205, Bit 2, Center 52 (-91 ~ 196) 288
4299 22:18:29.338314 iDelay=205, Bit 3, Center 52 (-91 ~ 196) 288
4300 22:18:29.341493 iDelay=205, Bit 4, Center 56 (-83 ~ 196) 280
4301 22:18:29.344923 iDelay=205, Bit 5, Center 44 (-99 ~ 188) 288
4302 22:18:29.348373 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4303 22:18:29.354688 iDelay=205, Bit 7, Center 60 (-83 ~ 204) 288
4304 22:18:29.358456 iDelay=205, Bit 8, Center 36 (-107 ~ 180) 288
4305 22:18:29.361309 iDelay=205, Bit 9, Center 32 (-107 ~ 172) 280
4306 22:18:29.364515 iDelay=205, Bit 10, Center 48 (-91 ~ 188) 280
4307 22:18:29.371749 iDelay=205, Bit 11, Center 40 (-99 ~ 180) 280
4308 22:18:29.374552 iDelay=205, Bit 12, Center 48 (-91 ~ 188) 280
4309 22:18:29.378249 iDelay=205, Bit 13, Center 52 (-83 ~ 188) 272
4310 22:18:29.381752 iDelay=205, Bit 14, Center 56 (-83 ~ 196) 280
4311 22:18:29.384724 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4312 22:18:29.388270 ==
4313 22:18:29.388370 Dram Type= 6, Freq= 0, CH_0, rank 1
4314 22:18:29.394615 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4315 22:18:29.394716 ==
4316 22:18:29.394810 DQS Delay:
4317 22:18:29.398119 DQS0 = 0, DQS1 = 0
4318 22:18:29.398221 DQM Delay:
4319 22:18:29.401266 DQM0 = 53, DQM1 = 45
4320 22:18:29.401367 DQ Delay:
4321 22:18:29.404986 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4322 22:18:29.407892 DQ4 =56, DQ5 =44, DQ6 =56, DQ7 =60
4323 22:18:29.411471 DQ8 =36, DQ9 =32, DQ10 =48, DQ11 =40
4324 22:18:29.414760 DQ12 =48, DQ13 =52, DQ14 =56, DQ15 =52
4325 22:18:29.414861
4326 22:18:29.414949
4327 22:18:29.421309 [DQSOSCAuto] RK1, (LSB)MR18= 0x6122, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 391 ps
4328 22:18:29.424625 CH0 RK1: MR19=808, MR18=6122
4329 22:18:29.431165 CH0_RK1: MR19=0x808, MR18=0x6122, DQSOSC=391, MR23=63, INC=171, DEC=114
4330 22:18:29.434855 [RxdqsGatingPostProcess] freq 600
4331 22:18:29.437678 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4332 22:18:29.441214 Pre-setting of DQS Precalculation
4333 22:18:29.447922 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4334 22:18:29.448023 ==
4335 22:18:29.451349 Dram Type= 6, Freq= 0, CH_1, rank 0
4336 22:18:29.454902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4337 22:18:29.455000 ==
4338 22:18:29.461412 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4339 22:18:29.467600 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4340 22:18:29.471125 [CA 0] Center 36 (5~67) winsize 63
4341 22:18:29.474269 [CA 1] Center 36 (6~67) winsize 62
4342 22:18:29.477906 [CA 2] Center 35 (4~66) winsize 63
4343 22:18:29.480878 [CA 3] Center 34 (4~65) winsize 62
4344 22:18:29.484506 [CA 4] Center 34 (4~65) winsize 62
4345 22:18:29.487930 [CA 5] Center 34 (4~65) winsize 62
4346 22:18:29.488009
4347 22:18:29.490949 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4348 22:18:29.491028
4349 22:18:29.494541 [CATrainingPosCal] consider 1 rank data
4350 22:18:29.497736 u2DelayCellTimex100 = 270/100 ps
4351 22:18:29.501247 CA0 delay=36 (5~67),Diff = 2 PI (19 cell)
4352 22:18:29.504064 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
4353 22:18:29.507719 CA2 delay=35 (4~66),Diff = 1 PI (9 cell)
4354 22:18:29.511008 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4355 22:18:29.514209 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4356 22:18:29.518007 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4357 22:18:29.518145
4358 22:18:29.524231 CA PerBit enable=1, Macro0, CA PI delay=34
4359 22:18:29.524349
4360 22:18:29.524442 [CBTSetCACLKResult] CA Dly = 34
4361 22:18:29.527557 CS Dly: 5 (0~36)
4362 22:18:29.527662 ==
4363 22:18:29.530829 Dram Type= 6, Freq= 0, CH_1, rank 1
4364 22:18:29.534304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4365 22:18:29.534403 ==
4366 22:18:29.540926 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4367 22:18:29.547883 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4368 22:18:29.551162 [CA 0] Center 36 (5~67) winsize 63
4369 22:18:29.554193 [CA 1] Center 36 (6~67) winsize 62
4370 22:18:29.557653 [CA 2] Center 35 (4~66) winsize 63
4371 22:18:29.560949 [CA 3] Center 35 (4~66) winsize 63
4372 22:18:29.564113 [CA 4] Center 34 (4~65) winsize 62
4373 22:18:29.567569 [CA 5] Center 34 (4~65) winsize 62
4374 22:18:29.567671
4375 22:18:29.570778 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4376 22:18:29.570873
4377 22:18:29.573846 [CATrainingPosCal] consider 2 rank data
4378 22:18:29.577353 u2DelayCellTimex100 = 270/100 ps
4379 22:18:29.581203 CA0 delay=36 (5~67),Diff = 2 PI (19 cell)
4380 22:18:29.584065 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
4381 22:18:29.587223 CA2 delay=35 (4~66),Diff = 1 PI (9 cell)
4382 22:18:29.590569 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4383 22:18:29.594458 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4384 22:18:29.597977 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4385 22:18:29.598056
4386 22:18:29.604164 CA PerBit enable=1, Macro0, CA PI delay=34
4387 22:18:29.604272
4388 22:18:29.604367 [CBTSetCACLKResult] CA Dly = 34
4389 22:18:29.607212 CS Dly: 6 (0~38)
4390 22:18:29.607283
4391 22:18:29.610771 ----->DramcWriteLeveling(PI) begin...
4392 22:18:29.610855 ==
4393 22:18:29.614146 Dram Type= 6, Freq= 0, CH_1, rank 0
4394 22:18:29.617524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4395 22:18:29.617633 ==
4396 22:18:29.621077 Write leveling (Byte 0): 30 => 30
4397 22:18:29.623934 Write leveling (Byte 1): 32 => 32
4398 22:18:29.627282 DramcWriteLeveling(PI) end<-----
4399 22:18:29.627365
4400 22:18:29.627431 ==
4401 22:18:29.630568 Dram Type= 6, Freq= 0, CH_1, rank 0
4402 22:18:29.634020 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4403 22:18:29.637410 ==
4404 22:18:29.637494 [Gating] SW mode calibration
4405 22:18:29.647279 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4406 22:18:29.650854 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4407 22:18:29.654044 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4408 22:18:29.660518 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4409 22:18:29.663891 0 9 8 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
4410 22:18:29.667650 0 9 12 | B1->B0 | 2f2f 2f2f | 0 0 | (1 1) (1 1)
4411 22:18:29.673709 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4412 22:18:29.677341 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4413 22:18:29.680253 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4414 22:18:29.687457 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4415 22:18:29.690450 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4416 22:18:29.693866 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4417 22:18:29.700319 0 10 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
4418 22:18:29.703996 0 10 12 | B1->B0 | 3434 3737 | 0 1 | (0 0) (0 0)
4419 22:18:29.707449 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4420 22:18:29.714094 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4421 22:18:29.717001 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4422 22:18:29.720667 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4423 22:18:29.726920 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4424 22:18:29.730555 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4425 22:18:29.733825 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4426 22:18:29.740131 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4427 22:18:29.743579 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4428 22:18:29.747108 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4429 22:18:29.750427 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4430 22:18:29.756883 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4431 22:18:29.760150 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4432 22:18:29.763353 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4433 22:18:29.770149 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4434 22:18:29.773732 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4435 22:18:29.776815 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4436 22:18:29.783590 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4437 22:18:29.786811 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4438 22:18:29.790322 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 22:18:29.796870 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4440 22:18:29.800321 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4441 22:18:29.803753 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4442 22:18:29.810244 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4443 22:18:29.810349 Total UI for P1: 0, mck2ui 16
4444 22:18:29.816893 best dqsien dly found for B0: ( 0, 13, 10)
4445 22:18:29.816996 Total UI for P1: 0, mck2ui 16
4446 22:18:29.823570 best dqsien dly found for B1: ( 0, 13, 10)
4447 22:18:29.826707 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4448 22:18:29.829967 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4449 22:18:29.830068
4450 22:18:29.833312 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4451 22:18:29.836248 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4452 22:18:29.839991 [Gating] SW calibration Done
4453 22:18:29.840067 ==
4454 22:18:29.843459 Dram Type= 6, Freq= 0, CH_1, rank 0
4455 22:18:29.846881 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4456 22:18:29.846983 ==
4457 22:18:29.849630 RX Vref Scan: 0
4458 22:18:29.849723
4459 22:18:29.849808 RX Vref 0 -> 0, step: 1
4460 22:18:29.853399
4461 22:18:29.853497 RX Delay -230 -> 252, step: 16
4462 22:18:29.859793 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4463 22:18:29.863536 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4464 22:18:29.866280 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4465 22:18:29.870045 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4466 22:18:29.872865 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4467 22:18:29.879879 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4468 22:18:29.883242 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4469 22:18:29.886528 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4470 22:18:29.889771 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4471 22:18:29.896315 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4472 22:18:29.899768 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4473 22:18:29.903280 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4474 22:18:29.906174 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4475 22:18:29.913181 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4476 22:18:29.916153 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4477 22:18:29.919880 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4478 22:18:29.919971 ==
4479 22:18:29.922694 Dram Type= 6, Freq= 0, CH_1, rank 0
4480 22:18:29.926179 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4481 22:18:29.929190 ==
4482 22:18:29.929290 DQS Delay:
4483 22:18:29.929381 DQS0 = 0, DQS1 = 0
4484 22:18:29.932902 DQM Delay:
4485 22:18:29.933006 DQM0 = 49, DQM1 = 45
4486 22:18:29.936097 DQ Delay:
4487 22:18:29.936201 DQ0 =57, DQ1 =41, DQ2 =41, DQ3 =49
4488 22:18:29.939417 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =41
4489 22:18:29.942961 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4490 22:18:29.946326 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =49
4491 22:18:29.946429
4492 22:18:29.946522
4493 22:18:29.949644 ==
4494 22:18:29.952984 Dram Type= 6, Freq= 0, CH_1, rank 0
4495 22:18:29.956479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4496 22:18:29.956584 ==
4497 22:18:29.956675
4498 22:18:29.956766
4499 22:18:29.959270 TX Vref Scan disable
4500 22:18:29.959367 == TX Byte 0 ==
4501 22:18:29.966071 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4502 22:18:29.969644 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4503 22:18:29.969724 == TX Byte 1 ==
4504 22:18:29.976158 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4505 22:18:29.979307 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4506 22:18:29.979407 ==
4507 22:18:29.982734 Dram Type= 6, Freq= 0, CH_1, rank 0
4508 22:18:29.986394 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4509 22:18:29.986494 ==
4510 22:18:29.986589
4511 22:18:29.986677
4512 22:18:29.989847 TX Vref Scan disable
4513 22:18:29.992762 == TX Byte 0 ==
4514 22:18:29.996145 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4515 22:18:29.999185 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4516 22:18:30.002823 == TX Byte 1 ==
4517 22:18:30.005832 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4518 22:18:30.009663 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4519 22:18:30.009739
4520 22:18:30.012723 [DATLAT]
4521 22:18:30.012823 Freq=600, CH1 RK0
4522 22:18:30.012913
4523 22:18:30.015740 DATLAT Default: 0x9
4524 22:18:30.015839 0, 0xFFFF, sum = 0
4525 22:18:30.019032 1, 0xFFFF, sum = 0
4526 22:18:30.019133 2, 0xFFFF, sum = 0
4527 22:18:30.022748 3, 0xFFFF, sum = 0
4528 22:18:30.022846 4, 0xFFFF, sum = 0
4529 22:18:30.026046 5, 0xFFFF, sum = 0
4530 22:18:30.026143 6, 0xFFFF, sum = 0
4531 22:18:30.028998 7, 0xFFFF, sum = 0
4532 22:18:30.029104 8, 0x0, sum = 1
4533 22:18:30.032622 9, 0x0, sum = 2
4534 22:18:30.032722 10, 0x0, sum = 3
4535 22:18:30.036069 11, 0x0, sum = 4
4536 22:18:30.036168 best_step = 9
4537 22:18:30.036262
4538 22:18:30.036357 ==
4539 22:18:30.039284 Dram Type= 6, Freq= 0, CH_1, rank 0
4540 22:18:30.042946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4541 22:18:30.045981 ==
4542 22:18:30.046092 RX Vref Scan: 1
4543 22:18:30.046184
4544 22:18:30.049475 RX Vref 0 -> 0, step: 1
4545 22:18:30.049598
4546 22:18:30.052352 RX Delay -163 -> 252, step: 8
4547 22:18:30.052449
4548 22:18:30.056124 Set Vref, RX VrefLevel [Byte0]: 56
4549 22:18:30.056224 [Byte1]: 52
4550 22:18:30.060646
4551 22:18:30.060753 Final RX Vref Byte 0 = 56 to rank0
4552 22:18:30.064023 Final RX Vref Byte 1 = 52 to rank0
4553 22:18:30.067519 Final RX Vref Byte 0 = 56 to rank1
4554 22:18:30.070653 Final RX Vref Byte 1 = 52 to rank1==
4555 22:18:30.073937 Dram Type= 6, Freq= 0, CH_1, rank 0
4556 22:18:30.080528 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4557 22:18:30.080636 ==
4558 22:18:30.080727 DQS Delay:
4559 22:18:30.083666 DQS0 = 0, DQS1 = 0
4560 22:18:30.083763 DQM Delay:
4561 22:18:30.083854 DQM0 = 49, DQM1 = 44
4562 22:18:30.087303 DQ Delay:
4563 22:18:30.090307 DQ0 =52, DQ1 =44, DQ2 =40, DQ3 =48
4564 22:18:30.093791 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4565 22:18:30.097352 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =36
4566 22:18:30.100170 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =52
4567 22:18:30.100265
4568 22:18:30.100355
4569 22:18:30.106989 [DQSOSCAuto] RK0, (LSB)MR18= 0x4a70, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps
4570 22:18:30.110696 CH1 RK0: MR19=808, MR18=4A70
4571 22:18:30.116906 CH1_RK0: MR19=0x808, MR18=0x4A70, DQSOSC=388, MR23=63, INC=174, DEC=116
4572 22:18:30.117016
4573 22:18:30.120453 ----->DramcWriteLeveling(PI) begin...
4574 22:18:30.120555 ==
4575 22:18:30.123826 Dram Type= 6, Freq= 0, CH_1, rank 1
4576 22:18:30.126990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4577 22:18:30.127091 ==
4578 22:18:30.130498 Write leveling (Byte 0): 29 => 29
4579 22:18:30.133466 Write leveling (Byte 1): 29 => 29
4580 22:18:30.137144 DramcWriteLeveling(PI) end<-----
4581 22:18:30.137246
4582 22:18:30.137337 ==
4583 22:18:30.140686 Dram Type= 6, Freq= 0, CH_1, rank 1
4584 22:18:30.143743 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4585 22:18:30.143844 ==
4586 22:18:30.147075 [Gating] SW mode calibration
4587 22:18:30.153401 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4588 22:18:30.160162 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4589 22:18:30.163562 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4590 22:18:30.170393 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4591 22:18:30.173294 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4592 22:18:30.176561 0 9 12 | B1->B0 | 2f2f 2f2f | 1 1 | (1 0) (1 1)
4593 22:18:30.183562 0 9 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4594 22:18:30.186675 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4595 22:18:30.190478 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4596 22:18:30.193845 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4597 22:18:30.200435 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4598 22:18:30.203516 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4599 22:18:30.206564 0 10 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
4600 22:18:30.213316 0 10 12 | B1->B0 | 4141 3636 | 0 1 | (0 0) (0 0)
4601 22:18:30.216966 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4602 22:18:30.219974 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4603 22:18:30.226552 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4604 22:18:30.230368 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4605 22:18:30.233464 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4606 22:18:30.239966 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4607 22:18:30.243626 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4608 22:18:30.246783 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4609 22:18:30.253471 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4610 22:18:30.256407 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4611 22:18:30.260322 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4612 22:18:30.266280 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4613 22:18:30.269466 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4614 22:18:30.272768 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4615 22:18:30.279591 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4616 22:18:30.283003 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4617 22:18:30.286315 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4618 22:18:30.292822 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4619 22:18:30.296443 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4620 22:18:30.299489 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4621 22:18:30.306026 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4622 22:18:30.309934 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4623 22:18:30.313197 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4624 22:18:30.319341 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4625 22:18:30.319416 Total UI for P1: 0, mck2ui 16
4626 22:18:30.325955 best dqsien dly found for B0: ( 0, 13, 10)
4627 22:18:30.326037 Total UI for P1: 0, mck2ui 16
4628 22:18:30.329664 best dqsien dly found for B1: ( 0, 13, 10)
4629 22:18:30.336308 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4630 22:18:30.339261 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4631 22:18:30.339342
4632 22:18:30.342620 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4633 22:18:30.346241 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4634 22:18:30.349381 [Gating] SW calibration Done
4635 22:18:30.349480 ==
4636 22:18:30.352951 Dram Type= 6, Freq= 0, CH_1, rank 1
4637 22:18:30.356049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4638 22:18:30.356148 ==
4639 22:18:30.359022 RX Vref Scan: 0
4640 22:18:30.359118
4641 22:18:30.359205 RX Vref 0 -> 0, step: 1
4642 22:18:30.359281
4643 22:18:30.362207 RX Delay -230 -> 252, step: 16
4644 22:18:30.369025 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4645 22:18:30.372160 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4646 22:18:30.375554 iDelay=218, Bit 2, Center 41 (-102 ~ 185) 288
4647 22:18:30.379059 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4648 22:18:30.382510 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4649 22:18:30.389167 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4650 22:18:30.392244 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4651 22:18:30.395845 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4652 22:18:30.398897 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4653 22:18:30.402580 iDelay=218, Bit 9, Center 49 (-102 ~ 201) 304
4654 22:18:30.409130 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4655 22:18:30.412157 iDelay=218, Bit 11, Center 49 (-102 ~ 201) 304
4656 22:18:30.415685 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4657 22:18:30.419153 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4658 22:18:30.425356 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4659 22:18:30.428433 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4660 22:18:30.428533 ==
4661 22:18:30.432031 Dram Type= 6, Freq= 0, CH_1, rank 1
4662 22:18:30.435144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4663 22:18:30.435220 ==
4664 22:18:30.438550 DQS Delay:
4665 22:18:30.438622 DQS0 = 0, DQS1 = 0
4666 22:18:30.438685 DQM Delay:
4667 22:18:30.442039 DQM0 = 52, DQM1 = 50
4668 22:18:30.442111 DQ Delay:
4669 22:18:30.445631 DQ0 =49, DQ1 =49, DQ2 =41, DQ3 =49
4670 22:18:30.448984 DQ4 =49, DQ5 =65, DQ6 =65, DQ7 =49
4671 22:18:30.451883 DQ8 =33, DQ9 =49, DQ10 =49, DQ11 =49
4672 22:18:30.455524 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4673 22:18:30.455599
4674 22:18:30.455661
4675 22:18:30.455721 ==
4676 22:18:30.458754 Dram Type= 6, Freq= 0, CH_1, rank 1
4677 22:18:30.465208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4678 22:18:30.465295 ==
4679 22:18:30.465361
4680 22:18:30.465422
4681 22:18:30.468533 TX Vref Scan disable
4682 22:18:30.468607 == TX Byte 0 ==
4683 22:18:30.472121 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4684 22:18:30.478221 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4685 22:18:30.478307 == TX Byte 1 ==
4686 22:18:30.481715 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4687 22:18:30.488055 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4688 22:18:30.488132 ==
4689 22:18:30.491455 Dram Type= 6, Freq= 0, CH_1, rank 1
4690 22:18:30.494917 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4691 22:18:30.494992 ==
4692 22:18:30.495056
4693 22:18:30.495114
4694 22:18:30.498639 TX Vref Scan disable
4695 22:18:30.501656 == TX Byte 0 ==
4696 22:18:30.504838 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4697 22:18:30.508426 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4698 22:18:30.511577 == TX Byte 1 ==
4699 22:18:30.515156 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4700 22:18:30.518341 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4701 22:18:30.518432
4702 22:18:30.521173 [DATLAT]
4703 22:18:30.521253 Freq=600, CH1 RK1
4704 22:18:30.521320
4705 22:18:30.525005 DATLAT Default: 0x9
4706 22:18:30.525075 0, 0xFFFF, sum = 0
4707 22:18:30.528401 1, 0xFFFF, sum = 0
4708 22:18:30.528477 2, 0xFFFF, sum = 0
4709 22:18:30.531186 3, 0xFFFF, sum = 0
4710 22:18:30.531274 4, 0xFFFF, sum = 0
4711 22:18:30.534546 5, 0xFFFF, sum = 0
4712 22:18:30.534618 6, 0xFFFF, sum = 0
4713 22:18:30.538187 7, 0xFFFF, sum = 0
4714 22:18:30.538274 8, 0x0, sum = 1
4715 22:18:30.541087 9, 0x0, sum = 2
4716 22:18:30.541184 10, 0x0, sum = 3
4717 22:18:30.544680 11, 0x0, sum = 4
4718 22:18:30.544770 best_step = 9
4719 22:18:30.544850
4720 22:18:30.544948 ==
4721 22:18:30.547780 Dram Type= 6, Freq= 0, CH_1, rank 1
4722 22:18:30.551502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4723 22:18:30.554907 ==
4724 22:18:30.554980 RX Vref Scan: 0
4725 22:18:30.555061
4726 22:18:30.558053 RX Vref 0 -> 0, step: 1
4727 22:18:30.558126
4728 22:18:30.558185 RX Delay -163 -> 252, step: 8
4729 22:18:30.566311 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4730 22:18:30.569170 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4731 22:18:30.572571 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4732 22:18:30.575904 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4733 22:18:30.579378 iDelay=205, Bit 4, Center 44 (-99 ~ 188) 288
4734 22:18:30.586000 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4735 22:18:30.589435 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4736 22:18:30.592344 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4737 22:18:30.596131 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4738 22:18:30.602190 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4739 22:18:30.605895 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4740 22:18:30.609122 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4741 22:18:30.612242 iDelay=205, Bit 12, Center 52 (-99 ~ 204) 304
4742 22:18:30.615576 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4743 22:18:30.622682 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4744 22:18:30.625748 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4745 22:18:30.625849 ==
4746 22:18:30.628779 Dram Type= 6, Freq= 0, CH_1, rank 1
4747 22:18:30.632530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4748 22:18:30.632633 ==
4749 22:18:30.635536 DQS Delay:
4750 22:18:30.635637 DQS0 = 0, DQS1 = 0
4751 22:18:30.635728 DQM Delay:
4752 22:18:30.638657 DQM0 = 48, DQM1 = 45
4753 22:18:30.638789 DQ Delay:
4754 22:18:30.642380 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4755 22:18:30.645442 DQ4 =44, DQ5 =60, DQ6 =60, DQ7 =48
4756 22:18:30.649198 DQ8 =32, DQ9 =32, DQ10 =48, DQ11 =40
4757 22:18:30.652490 DQ12 =52, DQ13 =52, DQ14 =48, DQ15 =56
4758 22:18:30.652590
4759 22:18:30.652685
4760 22:18:30.662167 [DQSOSCAuto] RK1, (LSB)MR18= 0x6921, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 390 ps
4761 22:18:30.665064 CH1 RK1: MR19=808, MR18=6921
4762 22:18:30.668721 CH1_RK1: MR19=0x808, MR18=0x6921, DQSOSC=390, MR23=63, INC=172, DEC=114
4763 22:18:30.672507 [RxdqsGatingPostProcess] freq 600
4764 22:18:30.679070 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4765 22:18:30.682374 Pre-setting of DQS Precalculation
4766 22:18:30.685089 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4767 22:18:30.695395 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4768 22:18:30.701807 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4769 22:18:30.701915
4770 22:18:30.702009
4771 22:18:30.705063 [Calibration Summary] 1200 Mbps
4772 22:18:30.705165 CH 0, Rank 0
4773 22:18:30.708572 SW Impedance : PASS
4774 22:18:30.708674 DUTY Scan : NO K
4775 22:18:30.712033 ZQ Calibration : PASS
4776 22:18:30.715209 Jitter Meter : NO K
4777 22:18:30.715312 CBT Training : PASS
4778 22:18:30.718797 Write leveling : PASS
4779 22:18:30.722348 RX DQS gating : PASS
4780 22:18:30.722425 RX DQ/DQS(RDDQC) : PASS
4781 22:18:30.725352 TX DQ/DQS : PASS
4782 22:18:30.725452 RX DATLAT : PASS
4783 22:18:30.728872 RX DQ/DQS(Engine): PASS
4784 22:18:30.731620 TX OE : NO K
4785 22:18:30.731695 All Pass.
4786 22:18:30.731764
4787 22:18:30.731825 CH 0, Rank 1
4788 22:18:30.735426 SW Impedance : PASS
4789 22:18:30.738747 DUTY Scan : NO K
4790 22:18:30.738838 ZQ Calibration : PASS
4791 22:18:30.741768 Jitter Meter : NO K
4792 22:18:30.745077 CBT Training : PASS
4793 22:18:30.745179 Write leveling : PASS
4794 22:18:30.748646 RX DQS gating : PASS
4795 22:18:30.751844 RX DQ/DQS(RDDQC) : PASS
4796 22:18:30.751947 TX DQ/DQS : PASS
4797 22:18:30.755363 RX DATLAT : PASS
4798 22:18:30.758350 RX DQ/DQS(Engine): PASS
4799 22:18:30.758450 TX OE : NO K
4800 22:18:30.762251 All Pass.
4801 22:18:30.762357
4802 22:18:30.762486 CH 1, Rank 0
4803 22:18:30.765259 SW Impedance : PASS
4804 22:18:30.765362 DUTY Scan : NO K
4805 22:18:30.768578 ZQ Calibration : PASS
4806 22:18:30.772001 Jitter Meter : NO K
4807 22:18:30.772106 CBT Training : PASS
4808 22:18:30.775043 Write leveling : PASS
4809 22:18:30.775143 RX DQS gating : PASS
4810 22:18:30.778589 RX DQ/DQS(RDDQC) : PASS
4811 22:18:30.781649 TX DQ/DQS : PASS
4812 22:18:30.781751 RX DATLAT : PASS
4813 22:18:30.785081 RX DQ/DQS(Engine): PASS
4814 22:18:30.788668 TX OE : NO K
4815 22:18:30.788771 All Pass.
4816 22:18:30.788865
4817 22:18:30.788952 CH 1, Rank 1
4818 22:18:30.792033 SW Impedance : PASS
4819 22:18:30.795535 DUTY Scan : NO K
4820 22:18:30.795636 ZQ Calibration : PASS
4821 22:18:30.798465 Jitter Meter : NO K
4822 22:18:30.802024 CBT Training : PASS
4823 22:18:30.802125 Write leveling : PASS
4824 22:18:30.805513 RX DQS gating : PASS
4825 22:18:30.808418 RX DQ/DQS(RDDQC) : PASS
4826 22:18:30.808520 TX DQ/DQS : PASS
4827 22:18:30.811773 RX DATLAT : PASS
4828 22:18:30.811891 RX DQ/DQS(Engine): PASS
4829 22:18:30.815170 TX OE : NO K
4830 22:18:30.815272 All Pass.
4831 22:18:30.815368
4832 22:18:30.818326 DramC Write-DBI off
4833 22:18:30.821975 PER_BANK_REFRESH: Hybrid Mode
4834 22:18:30.822077 TX_TRACKING: ON
4835 22:18:30.831455 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4836 22:18:30.835256 [FAST_K] Save calibration result to emmc
4837 22:18:30.838261 dramc_set_vcore_voltage set vcore to 662500
4838 22:18:30.841593 Read voltage for 933, 3
4839 22:18:30.841696 Vio18 = 0
4840 22:18:30.845078 Vcore = 662500
4841 22:18:30.845174 Vdram = 0
4842 22:18:30.845265 Vddq = 0
4843 22:18:30.845356 Vmddr = 0
4844 22:18:30.851731 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4845 22:18:30.858275 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4846 22:18:30.858380 MEM_TYPE=3, freq_sel=17
4847 22:18:30.861238 sv_algorithm_assistance_LP4_1600
4848 22:18:30.864481 ============ PULL DRAM RESETB DOWN ============
4849 22:18:30.871619 ========== PULL DRAM RESETB DOWN end =========
4850 22:18:30.874618 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4851 22:18:30.878292 ===================================
4852 22:18:30.881460 LPDDR4 DRAM CONFIGURATION
4853 22:18:30.884533 ===================================
4854 22:18:30.884614 EX_ROW_EN[0] = 0x0
4855 22:18:30.887954 EX_ROW_EN[1] = 0x0
4856 22:18:30.888036 LP4Y_EN = 0x0
4857 22:18:30.891603 WORK_FSP = 0x0
4858 22:18:30.891717 WL = 0x3
4859 22:18:30.894930 RL = 0x3
4860 22:18:30.895011 BL = 0x2
4861 22:18:30.897792 RPST = 0x0
4862 22:18:30.901756 RD_PRE = 0x0
4863 22:18:30.901837 WR_PRE = 0x1
4864 22:18:30.904634 WR_PST = 0x0
4865 22:18:30.904716 DBI_WR = 0x0
4866 22:18:30.907924 DBI_RD = 0x0
4867 22:18:30.908005 OTF = 0x1
4868 22:18:30.911418 ===================================
4869 22:18:30.914658 ===================================
4870 22:18:30.914745 ANA top config
4871 22:18:30.918331 ===================================
4872 22:18:30.921504 DLL_ASYNC_EN = 0
4873 22:18:30.924492 ALL_SLAVE_EN = 1
4874 22:18:30.927875 NEW_RANK_MODE = 1
4875 22:18:30.931224 DLL_IDLE_MODE = 1
4876 22:18:30.931306 LP45_APHY_COMB_EN = 1
4877 22:18:30.934212 TX_ODT_DIS = 1
4878 22:18:30.938121 NEW_8X_MODE = 1
4879 22:18:30.941288 ===================================
4880 22:18:30.944471 ===================================
4881 22:18:30.948011 data_rate = 1866
4882 22:18:30.951342 CKR = 1
4883 22:18:30.951449 DQ_P2S_RATIO = 8
4884 22:18:30.954827 ===================================
4885 22:18:30.957653 CA_P2S_RATIO = 8
4886 22:18:30.960831 DQ_CA_OPEN = 0
4887 22:18:30.964436 DQ_SEMI_OPEN = 0
4888 22:18:30.967739 CA_SEMI_OPEN = 0
4889 22:18:30.971058 CA_FULL_RATE = 0
4890 22:18:30.971139 DQ_CKDIV4_EN = 1
4891 22:18:30.974739 CA_CKDIV4_EN = 1
4892 22:18:30.977810 CA_PREDIV_EN = 0
4893 22:18:30.981413 PH8_DLY = 0
4894 22:18:30.984416 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4895 22:18:30.988224 DQ_AAMCK_DIV = 4
4896 22:18:30.988306 CA_AAMCK_DIV = 4
4897 22:18:30.990984 CA_ADMCK_DIV = 4
4898 22:18:30.994587 DQ_TRACK_CA_EN = 0
4899 22:18:30.997452 CA_PICK = 933
4900 22:18:31.001007 CA_MCKIO = 933
4901 22:18:31.004553 MCKIO_SEMI = 0
4902 22:18:31.007620 PLL_FREQ = 3732
4903 22:18:31.007698 DQ_UI_PI_RATIO = 32
4904 22:18:31.011150 CA_UI_PI_RATIO = 0
4905 22:18:31.014502 ===================================
4906 22:18:31.017764 ===================================
4907 22:18:31.020910 memory_type:LPDDR4
4908 22:18:31.024359 GP_NUM : 10
4909 22:18:31.024435 SRAM_EN : 1
4910 22:18:31.027795 MD32_EN : 0
4911 22:18:31.031237 ===================================
4912 22:18:31.031348 [ANA_INIT] >>>>>>>>>>>>>>
4913 22:18:31.034625 <<<<<< [CONFIGURE PHASE]: ANA_TX
4914 22:18:31.038085 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4915 22:18:31.040874 ===================================
4916 22:18:31.044548 data_rate = 1866,PCW = 0X8f00
4917 22:18:31.047609 ===================================
4918 22:18:31.051121 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4919 22:18:31.057489 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4920 22:18:31.064278 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4921 22:18:31.067420 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4922 22:18:31.070799 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4923 22:18:31.074239 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4924 22:18:31.077624 [ANA_INIT] flow start
4925 22:18:31.077756 [ANA_INIT] PLL >>>>>>>>
4926 22:18:31.080566 [ANA_INIT] PLL <<<<<<<<
4927 22:18:31.084325 [ANA_INIT] MIDPI >>>>>>>>
4928 22:18:31.084410 [ANA_INIT] MIDPI <<<<<<<<
4929 22:18:31.087304 [ANA_INIT] DLL >>>>>>>>
4930 22:18:31.090832 [ANA_INIT] flow end
4931 22:18:31.093863 ============ LP4 DIFF to SE enter ============
4932 22:18:31.097260 ============ LP4 DIFF to SE exit ============
4933 22:18:31.100456 [ANA_INIT] <<<<<<<<<<<<<
4934 22:18:31.104012 [Flow] Enable top DCM control >>>>>
4935 22:18:31.107194 [Flow] Enable top DCM control <<<<<
4936 22:18:31.110939 Enable DLL master slave shuffle
4937 22:18:31.114239 ==============================================================
4938 22:18:31.117553 Gating Mode config
4939 22:18:31.124002 ==============================================================
4940 22:18:31.124154 Config description:
4941 22:18:31.133987 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4942 22:18:31.140783 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4943 22:18:31.144025 SELPH_MODE 0: By rank 1: By Phase
4944 22:18:31.150291 ==============================================================
4945 22:18:31.153964 GAT_TRACK_EN = 1
4946 22:18:31.157216 RX_GATING_MODE = 2
4947 22:18:31.160635 RX_GATING_TRACK_MODE = 2
4948 22:18:31.164124 SELPH_MODE = 1
4949 22:18:31.167083 PICG_EARLY_EN = 1
4950 22:18:31.170488 VALID_LAT_VALUE = 1
4951 22:18:31.173934 ==============================================================
4952 22:18:31.177233 Enter into Gating configuration >>>>
4953 22:18:31.180406 Exit from Gating configuration <<<<
4954 22:18:31.183629 Enter into DVFS_PRE_config >>>>>
4955 22:18:31.197265 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4956 22:18:31.197366 Exit from DVFS_PRE_config <<<<<
4957 22:18:31.200232 Enter into PICG configuration >>>>
4958 22:18:31.203994 Exit from PICG configuration <<<<
4959 22:18:31.207407 [RX_INPUT] configuration >>>>>
4960 22:18:31.210228 [RX_INPUT] configuration <<<<<
4961 22:18:31.216949 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4962 22:18:31.220761 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4963 22:18:31.226722 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4964 22:18:31.233612 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4965 22:18:31.240182 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4966 22:18:31.246657 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4967 22:18:31.249879 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4968 22:18:31.253389 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4969 22:18:31.256710 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4970 22:18:31.263083 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4971 22:18:31.266536 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4972 22:18:31.269838 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4973 22:18:31.273445 ===================================
4974 22:18:31.276646 LPDDR4 DRAM CONFIGURATION
4975 22:18:31.280112 ===================================
4976 22:18:31.280194 EX_ROW_EN[0] = 0x0
4977 22:18:31.283190 EX_ROW_EN[1] = 0x0
4978 22:18:31.286675 LP4Y_EN = 0x0
4979 22:18:31.286754 WORK_FSP = 0x0
4980 22:18:31.290217 WL = 0x3
4981 22:18:31.290292 RL = 0x3
4982 22:18:31.293272 BL = 0x2
4983 22:18:31.293433 RPST = 0x0
4984 22:18:31.296697 RD_PRE = 0x0
4985 22:18:31.296800 WR_PRE = 0x1
4986 22:18:31.299814 WR_PST = 0x0
4987 22:18:31.299896 DBI_WR = 0x0
4988 22:18:31.303458 DBI_RD = 0x0
4989 22:18:31.303534 OTF = 0x1
4990 22:18:31.306534 ===================================
4991 22:18:31.309643 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4992 22:18:31.316353 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4993 22:18:31.320042 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4994 22:18:31.323046 ===================================
4995 22:18:31.326774 LPDDR4 DRAM CONFIGURATION
4996 22:18:31.329715 ===================================
4997 22:18:31.329790 EX_ROW_EN[0] = 0x10
4998 22:18:31.332887 EX_ROW_EN[1] = 0x0
4999 22:18:31.336277 LP4Y_EN = 0x0
5000 22:18:31.336366 WORK_FSP = 0x0
5001 22:18:31.339945 WL = 0x3
5002 22:18:31.340019 RL = 0x3
5003 22:18:31.343298 BL = 0x2
5004 22:18:31.343377 RPST = 0x0
5005 22:18:31.346337 RD_PRE = 0x0
5006 22:18:31.346432 WR_PRE = 0x1
5007 22:18:31.349525 WR_PST = 0x0
5008 22:18:31.349615 DBI_WR = 0x0
5009 22:18:31.352810 DBI_RD = 0x0
5010 22:18:31.352893 OTF = 0x1
5011 22:18:31.356382 ===================================
5012 22:18:31.362893 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5013 22:18:31.367313 nWR fixed to 30
5014 22:18:31.370425 [ModeRegInit_LP4] CH0 RK0
5015 22:18:31.370508 [ModeRegInit_LP4] CH0 RK1
5016 22:18:31.373972 [ModeRegInit_LP4] CH1 RK0
5017 22:18:31.377382 [ModeRegInit_LP4] CH1 RK1
5018 22:18:31.377461 match AC timing 9
5019 22:18:31.383551 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5020 22:18:31.387172 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5021 22:18:31.390701 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5022 22:18:31.396995 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5023 22:18:31.400374 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5024 22:18:31.400453 ==
5025 22:18:31.404215 Dram Type= 6, Freq= 0, CH_0, rank 0
5026 22:18:31.407175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5027 22:18:31.407252 ==
5028 22:18:31.413941 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5029 22:18:31.420173 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5030 22:18:31.423673 [CA 0] Center 37 (6~68) winsize 63
5031 22:18:31.426883 [CA 1] Center 37 (7~68) winsize 62
5032 22:18:31.430501 [CA 2] Center 34 (4~65) winsize 62
5033 22:18:31.433483 [CA 3] Center 34 (3~65) winsize 63
5034 22:18:31.437036 [CA 4] Center 33 (3~64) winsize 62
5035 22:18:31.440859 [CA 5] Center 32 (2~63) winsize 62
5036 22:18:31.440941
5037 22:18:31.443312 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5038 22:18:31.443392
5039 22:18:31.447168 [CATrainingPosCal] consider 1 rank data
5040 22:18:31.450316 u2DelayCellTimex100 = 270/100 ps
5041 22:18:31.453682 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5042 22:18:31.456948 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5043 22:18:31.460541 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5044 22:18:31.463527 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5045 22:18:31.466941 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5046 22:18:31.470228 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5047 22:18:31.473480
5048 22:18:31.477157 CA PerBit enable=1, Macro0, CA PI delay=32
5049 22:18:31.477257
5050 22:18:31.480329 [CBTSetCACLKResult] CA Dly = 32
5051 22:18:31.480444 CS Dly: 5 (0~36)
5052 22:18:31.480538 ==
5053 22:18:31.483178 Dram Type= 6, Freq= 0, CH_0, rank 1
5054 22:18:31.486979 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5055 22:18:31.487063 ==
5056 22:18:31.493153 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5057 22:18:31.500258 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5058 22:18:31.503057 [CA 0] Center 37 (7~68) winsize 62
5059 22:18:31.506696 [CA 1] Center 37 (7~68) winsize 62
5060 22:18:31.510114 [CA 2] Center 34 (4~65) winsize 62
5061 22:18:31.513662 [CA 3] Center 34 (4~65) winsize 62
5062 22:18:31.516745 [CA 4] Center 32 (2~63) winsize 62
5063 22:18:31.520340 [CA 5] Center 32 (2~62) winsize 61
5064 22:18:31.520425
5065 22:18:31.523217 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5066 22:18:31.523304
5067 22:18:31.526921 [CATrainingPosCal] consider 2 rank data
5068 22:18:31.529799 u2DelayCellTimex100 = 270/100 ps
5069 22:18:31.533637 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5070 22:18:31.536619 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5071 22:18:31.540268 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5072 22:18:31.543159 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5073 22:18:31.546726 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5074 22:18:31.553007 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5075 22:18:31.553089
5076 22:18:31.556461 CA PerBit enable=1, Macro0, CA PI delay=32
5077 22:18:31.556587
5078 22:18:31.559942 [CBTSetCACLKResult] CA Dly = 32
5079 22:18:31.560023 CS Dly: 5 (0~37)
5080 22:18:31.560087
5081 22:18:31.562834 ----->DramcWriteLeveling(PI) begin...
5082 22:18:31.562978 ==
5083 22:18:31.566262 Dram Type= 6, Freq= 0, CH_0, rank 0
5084 22:18:31.573237 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5085 22:18:31.573374 ==
5086 22:18:31.576026 Write leveling (Byte 0): 31 => 31
5087 22:18:31.576108 Write leveling (Byte 1): 30 => 30
5088 22:18:31.579811 DramcWriteLeveling(PI) end<-----
5089 22:18:31.579893
5090 22:18:31.582675 ==
5091 22:18:31.582756 Dram Type= 6, Freq= 0, CH_0, rank 0
5092 22:18:31.589406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5093 22:18:31.589547 ==
5094 22:18:31.593102 [Gating] SW mode calibration
5095 22:18:31.599383 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5096 22:18:31.602874 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5097 22:18:31.609705 0 14 0 | B1->B0 | 2828 3434 | 1 1 | (1 1) (1 1)
5098 22:18:31.612812 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5099 22:18:31.615990 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5100 22:18:31.622718 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5101 22:18:31.626388 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5102 22:18:31.629560 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5103 22:18:31.636254 0 14 24 | B1->B0 | 3434 3131 | 1 0 | (1 1) (1 0)
5104 22:18:31.639335 0 14 28 | B1->B0 | 3434 2626 | 1 0 | (1 1) (0 0)
5105 22:18:31.642403 0 15 0 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (1 0)
5106 22:18:31.649300 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5107 22:18:31.652209 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5108 22:18:31.655843 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5109 22:18:31.662341 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5110 22:18:31.665661 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5111 22:18:31.669219 0 15 24 | B1->B0 | 2323 2928 | 0 1 | (0 0) (0 0)
5112 22:18:31.675810 0 15 28 | B1->B0 | 2828 4141 | 0 0 | (0 0) (0 0)
5113 22:18:31.679022 1 0 0 | B1->B0 | 3a3a 4646 | 0 0 | (1 1) (0 0)
5114 22:18:31.682515 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5115 22:18:31.688855 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5116 22:18:31.692327 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5117 22:18:31.695511 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5118 22:18:31.698936 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5119 22:18:31.705608 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5120 22:18:31.708710 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
5121 22:18:31.712188 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5122 22:18:31.718813 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5123 22:18:31.722240 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5124 22:18:31.725286 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5125 22:18:31.732091 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5126 22:18:31.735273 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5127 22:18:31.738882 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5128 22:18:31.745621 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5129 22:18:31.748531 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5130 22:18:31.751744 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5131 22:18:31.758704 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5132 22:18:31.762187 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5133 22:18:31.765267 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5134 22:18:31.772114 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5135 22:18:31.775647 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5136 22:18:31.778394 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5137 22:18:31.785389 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5138 22:18:31.785477 Total UI for P1: 0, mck2ui 16
5139 22:18:31.791641 best dqsien dly found for B0: ( 1, 2, 26)
5140 22:18:31.791725 Total UI for P1: 0, mck2ui 16
5141 22:18:31.798263 best dqsien dly found for B1: ( 1, 2, 30)
5142 22:18:31.801891 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5143 22:18:31.805347 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5144 22:18:31.805431
5145 22:18:31.808361 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5146 22:18:31.811866 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5147 22:18:31.815308 [Gating] SW calibration Done
5148 22:18:31.815392 ==
5149 22:18:31.818813 Dram Type= 6, Freq= 0, CH_0, rank 0
5150 22:18:31.821671 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5151 22:18:31.821756 ==
5152 22:18:31.824977 RX Vref Scan: 0
5153 22:18:31.825060
5154 22:18:31.825145 RX Vref 0 -> 0, step: 1
5155 22:18:31.825224
5156 22:18:31.828698 RX Delay -80 -> 252, step: 8
5157 22:18:31.831776 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5158 22:18:31.838400 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5159 22:18:31.841952 iDelay=208, Bit 2, Center 103 (16 ~ 191) 176
5160 22:18:31.845095 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5161 22:18:31.848383 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5162 22:18:31.851726 iDelay=208, Bit 5, Center 95 (8 ~ 183) 176
5163 22:18:31.855260 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5164 22:18:31.861365 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5165 22:18:31.864778 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5166 22:18:31.868129 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5167 22:18:31.871422 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5168 22:18:31.874852 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5169 22:18:31.881175 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5170 22:18:31.884505 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5171 22:18:31.887786 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5172 22:18:31.891502 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5173 22:18:31.891585 ==
5174 22:18:31.894383 Dram Type= 6, Freq= 0, CH_0, rank 0
5175 22:18:31.898265 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5176 22:18:31.901716 ==
5177 22:18:31.901798 DQS Delay:
5178 22:18:31.901878 DQS0 = 0, DQS1 = 0
5179 22:18:31.905168 DQM Delay:
5180 22:18:31.905266 DQM0 = 106, DQM1 = 95
5181 22:18:31.908111 DQ Delay:
5182 22:18:31.911020 DQ0 =107, DQ1 =107, DQ2 =103, DQ3 =99
5183 22:18:31.914819 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =115
5184 22:18:31.917649 DQ8 =87, DQ9 =83, DQ10 =95, DQ11 =91
5185 22:18:31.921527 DQ12 =99, DQ13 =103, DQ14 =103, DQ15 =99
5186 22:18:31.921622
5187 22:18:31.921724
5188 22:18:31.921783 ==
5189 22:18:31.924702 Dram Type= 6, Freq= 0, CH_0, rank 0
5190 22:18:31.927802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5191 22:18:31.927908 ==
5192 22:18:31.927988
5193 22:18:31.928049
5194 22:18:31.931096 TX Vref Scan disable
5195 22:18:31.931178 == TX Byte 0 ==
5196 22:18:31.937990 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5197 22:18:31.941657 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5198 22:18:31.941739 == TX Byte 1 ==
5199 22:18:31.947737 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5200 22:18:31.951329 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5201 22:18:31.951411 ==
5202 22:18:31.954374 Dram Type= 6, Freq= 0, CH_0, rank 0
5203 22:18:31.957879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5204 22:18:31.957961 ==
5205 22:18:31.958026
5206 22:18:31.961367
5207 22:18:31.961492 TX Vref Scan disable
5208 22:18:31.964977 == TX Byte 0 ==
5209 22:18:31.967992 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5210 22:18:31.971314 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5211 22:18:31.974955 == TX Byte 1 ==
5212 22:18:31.977842 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5213 22:18:31.981656 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5214 22:18:31.981739
5215 22:18:31.984738 [DATLAT]
5216 22:18:31.984837 Freq=933, CH0 RK0
5217 22:18:31.984904
5218 22:18:31.988362 DATLAT Default: 0xd
5219 22:18:31.988444 0, 0xFFFF, sum = 0
5220 22:18:31.991471 1, 0xFFFF, sum = 0
5221 22:18:31.991554 2, 0xFFFF, sum = 0
5222 22:18:31.994798 3, 0xFFFF, sum = 0
5223 22:18:31.994898 4, 0xFFFF, sum = 0
5224 22:18:31.998274 5, 0xFFFF, sum = 0
5225 22:18:31.998358 6, 0xFFFF, sum = 0
5226 22:18:32.001914 7, 0xFFFF, sum = 0
5227 22:18:32.002013 8, 0xFFFF, sum = 0
5228 22:18:32.005020 9, 0xFFFF, sum = 0
5229 22:18:32.005128 10, 0x0, sum = 1
5230 22:18:32.008319 11, 0x0, sum = 2
5231 22:18:32.008418 12, 0x0, sum = 3
5232 22:18:32.011285 13, 0x0, sum = 4
5233 22:18:32.011368 best_step = 11
5234 22:18:32.011433
5235 22:18:32.011509 ==
5236 22:18:32.014986 Dram Type= 6, Freq= 0, CH_0, rank 0
5237 22:18:32.021233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5238 22:18:32.021317 ==
5239 22:18:32.021382 RX Vref Scan: 1
5240 22:18:32.021442
5241 22:18:32.024797 RX Vref 0 -> 0, step: 1
5242 22:18:32.024878
5243 22:18:32.028420 RX Delay -53 -> 252, step: 4
5244 22:18:32.028554
5245 22:18:32.031451 Set Vref, RX VrefLevel [Byte0]: 56
5246 22:18:32.034690 [Byte1]: 47
5247 22:18:32.034787
5248 22:18:32.037849 Final RX Vref Byte 0 = 56 to rank0
5249 22:18:32.041384 Final RX Vref Byte 1 = 47 to rank0
5250 22:18:32.044382 Final RX Vref Byte 0 = 56 to rank1
5251 22:18:32.048112 Final RX Vref Byte 1 = 47 to rank1==
5252 22:18:32.051054 Dram Type= 6, Freq= 0, CH_0, rank 0
5253 22:18:32.054296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5254 22:18:32.054380 ==
5255 22:18:32.057818 DQS Delay:
5256 22:18:32.057900 DQS0 = 0, DQS1 = 0
5257 22:18:32.057965 DQM Delay:
5258 22:18:32.061281 DQM0 = 105, DQM1 = 95
5259 22:18:32.061395 DQ Delay:
5260 22:18:32.064555 DQ0 =104, DQ1 =106, DQ2 =104, DQ3 =102
5261 22:18:32.067804 DQ4 =104, DQ5 =96, DQ6 =114, DQ7 =110
5262 22:18:32.070936 DQ8 =84, DQ9 =84, DQ10 =96, DQ11 =88
5263 22:18:32.078020 DQ12 =102, DQ13 =102, DQ14 =104, DQ15 =102
5264 22:18:32.078102
5265 22:18:32.078167
5266 22:18:32.084161 [DQSOSCAuto] RK0, (LSB)MR18= 0x2f27, (MSB)MR19= 0x505, tDQSOscB0 = 409 ps tDQSOscB1 = 407 ps
5267 22:18:32.087567 CH0 RK0: MR19=505, MR18=2F27
5268 22:18:32.094525 CH0_RK0: MR19=0x505, MR18=0x2F27, DQSOSC=407, MR23=63, INC=65, DEC=43
5269 22:18:32.094622
5270 22:18:32.097486 ----->DramcWriteLeveling(PI) begin...
5271 22:18:32.097595 ==
5272 22:18:32.100963 Dram Type= 6, Freq= 0, CH_0, rank 1
5273 22:18:32.104366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5274 22:18:32.104449 ==
5275 22:18:32.107648 Write leveling (Byte 0): 34 => 34
5276 22:18:32.110943 Write leveling (Byte 1): 28 => 28
5277 22:18:32.114467 DramcWriteLeveling(PI) end<-----
5278 22:18:32.114565
5279 22:18:32.114662 ==
5280 22:18:32.117371 Dram Type= 6, Freq= 0, CH_0, rank 1
5281 22:18:32.120746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5282 22:18:32.120828 ==
5283 22:18:32.124158 [Gating] SW mode calibration
5284 22:18:32.130898 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5285 22:18:32.137048 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5286 22:18:32.141038 0 14 0 | B1->B0 | 3434 3434 | 0 0 | (0 0) (0 0)
5287 22:18:32.147147 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5288 22:18:32.150766 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5289 22:18:32.153757 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5290 22:18:32.160580 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5291 22:18:32.164058 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5292 22:18:32.167616 0 14 24 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5293 22:18:32.170724 0 14 28 | B1->B0 | 2b2b 2a2a | 0 1 | (0 1) (1 0)
5294 22:18:32.177214 0 15 0 | B1->B0 | 2424 2424 | 0 0 | (0 0) (1 1)
5295 22:18:32.180292 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5296 22:18:32.183812 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5297 22:18:32.190939 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5298 22:18:32.194085 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5299 22:18:32.197318 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5300 22:18:32.204194 0 15 24 | B1->B0 | 2525 2424 | 0 0 | (0 0) (0 0)
5301 22:18:32.207404 0 15 28 | B1->B0 | 4242 3b3b | 0 0 | (1 1) (0 0)
5302 22:18:32.210264 1 0 0 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
5303 22:18:32.216914 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5304 22:18:32.220331 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5305 22:18:32.223815 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5306 22:18:32.230294 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5307 22:18:32.233923 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5308 22:18:32.237307 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5309 22:18:32.243894 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5310 22:18:32.247142 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5311 22:18:32.250499 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5312 22:18:32.256905 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5313 22:18:32.260748 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5314 22:18:32.263589 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5315 22:18:32.270973 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5316 22:18:32.273991 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5317 22:18:32.276897 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5318 22:18:32.280177 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5319 22:18:32.287238 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5320 22:18:32.290656 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5321 22:18:32.293771 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5322 22:18:32.300414 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5323 22:18:32.303693 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5324 22:18:32.307071 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5325 22:18:32.313898 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5326 22:18:32.316835 Total UI for P1: 0, mck2ui 16
5327 22:18:32.320516 best dqsien dly found for B0: ( 1, 2, 26)
5328 22:18:32.323501 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5329 22:18:32.326830 Total UI for P1: 0, mck2ui 16
5330 22:18:32.330242 best dqsien dly found for B1: ( 1, 2, 28)
5331 22:18:32.333722 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5332 22:18:32.336671 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5333 22:18:32.336752
5334 22:18:32.340263 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5335 22:18:32.343355 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5336 22:18:32.346697 [Gating] SW calibration Done
5337 22:18:32.346793 ==
5338 22:18:32.350469 Dram Type= 6, Freq= 0, CH_0, rank 1
5339 22:18:32.353630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5340 22:18:32.357095 ==
5341 22:18:32.357205 RX Vref Scan: 0
5342 22:18:32.357269
5343 22:18:32.360634 RX Vref 0 -> 0, step: 1
5344 22:18:32.360717
5345 22:18:32.363444 RX Delay -80 -> 252, step: 8
5346 22:18:32.366844 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5347 22:18:32.369929 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5348 22:18:32.373495 iDelay=208, Bit 2, Center 103 (8 ~ 199) 192
5349 22:18:32.377141 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5350 22:18:32.383396 iDelay=208, Bit 4, Center 111 (24 ~ 199) 176
5351 22:18:32.386688 iDelay=208, Bit 5, Center 99 (8 ~ 191) 184
5352 22:18:32.390470 iDelay=208, Bit 6, Center 111 (24 ~ 199) 176
5353 22:18:32.393299 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5354 22:18:32.397013 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5355 22:18:32.400009 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5356 22:18:32.406454 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5357 22:18:32.410034 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5358 22:18:32.413062 iDelay=208, Bit 12, Center 95 (8 ~ 183) 176
5359 22:18:32.416725 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5360 22:18:32.420192 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5361 22:18:32.423716 iDelay=208, Bit 15, Center 103 (16 ~ 191) 176
5362 22:18:32.427026 ==
5363 22:18:32.429665 Dram Type= 6, Freq= 0, CH_0, rank 1
5364 22:18:32.433409 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5365 22:18:32.433493 ==
5366 22:18:32.433603 DQS Delay:
5367 22:18:32.436652 DQS0 = 0, DQS1 = 0
5368 22:18:32.436739 DQM Delay:
5369 22:18:32.439863 DQM0 = 106, DQM1 = 94
5370 22:18:32.439940 DQ Delay:
5371 22:18:32.443237 DQ0 =103, DQ1 =107, DQ2 =103, DQ3 =99
5372 22:18:32.446279 DQ4 =111, DQ5 =99, DQ6 =111, DQ7 =115
5373 22:18:32.449831 DQ8 =87, DQ9 =83, DQ10 =95, DQ11 =87
5374 22:18:32.453068 DQ12 =95, DQ13 =99, DQ14 =103, DQ15 =103
5375 22:18:32.453141
5376 22:18:32.453207
5377 22:18:32.453308 ==
5378 22:18:32.456420 Dram Type= 6, Freq= 0, CH_0, rank 1
5379 22:18:32.459982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5380 22:18:32.463197 ==
5381 22:18:32.463279
5382 22:18:32.463346
5383 22:18:32.463409 TX Vref Scan disable
5384 22:18:32.466251 == TX Byte 0 ==
5385 22:18:32.469795 Update DQ dly =719 (2 ,6, 15) DQ OEN =(2 ,3)
5386 22:18:32.473345 Update DQM dly =719 (2 ,6, 15) DQM OEN =(2 ,3)
5387 22:18:32.476388 == TX Byte 1 ==
5388 22:18:32.480018 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5389 22:18:32.483404 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5390 22:18:32.483480 ==
5391 22:18:32.486471 Dram Type= 6, Freq= 0, CH_0, rank 1
5392 22:18:32.493428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5393 22:18:32.493526 ==
5394 22:18:32.493613
5395 22:18:32.493675
5396 22:18:32.493732 TX Vref Scan disable
5397 22:18:32.497679 == TX Byte 0 ==
5398 22:18:32.501195 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5399 22:18:32.504190 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5400 22:18:32.507470 == TX Byte 1 ==
5401 22:18:32.511293 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5402 22:18:32.514249 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5403 22:18:32.517565
5404 22:18:32.517648 [DATLAT]
5405 22:18:32.517712 Freq=933, CH0 RK1
5406 22:18:32.517773
5407 22:18:32.520734 DATLAT Default: 0xb
5408 22:18:32.520813 0, 0xFFFF, sum = 0
5409 22:18:32.524648 1, 0xFFFF, sum = 0
5410 22:18:32.524721 2, 0xFFFF, sum = 0
5411 22:18:32.527891 3, 0xFFFF, sum = 0
5412 22:18:32.527962 4, 0xFFFF, sum = 0
5413 22:18:32.531422 5, 0xFFFF, sum = 0
5414 22:18:32.531507 6, 0xFFFF, sum = 0
5415 22:18:32.534469 7, 0xFFFF, sum = 0
5416 22:18:32.537689 8, 0xFFFF, sum = 0
5417 22:18:32.537769 9, 0xFFFF, sum = 0
5418 22:18:32.537834 10, 0x0, sum = 1
5419 22:18:32.541116 11, 0x0, sum = 2
5420 22:18:32.541189 12, 0x0, sum = 3
5421 22:18:32.544286 13, 0x0, sum = 4
5422 22:18:32.544362 best_step = 11
5423 22:18:32.544426
5424 22:18:32.544482 ==
5425 22:18:32.547605 Dram Type= 6, Freq= 0, CH_0, rank 1
5426 22:18:32.554106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5427 22:18:32.554207 ==
5428 22:18:32.554299 RX Vref Scan: 0
5429 22:18:32.554371
5430 22:18:32.557407 RX Vref 0 -> 0, step: 1
5431 22:18:32.557497
5432 22:18:32.560757 RX Delay -53 -> 252, step: 4
5433 22:18:32.564308 iDelay=199, Bit 0, Center 102 (11 ~ 194) 184
5434 22:18:32.570899 iDelay=199, Bit 1, Center 104 (19 ~ 190) 172
5435 22:18:32.573974 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5436 22:18:32.577704 iDelay=199, Bit 3, Center 102 (15 ~ 190) 176
5437 22:18:32.580971 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176
5438 22:18:32.584341 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5439 22:18:32.590436 iDelay=199, Bit 6, Center 110 (27 ~ 194) 168
5440 22:18:32.594136 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5441 22:18:32.597560 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5442 22:18:32.600619 iDelay=199, Bit 9, Center 82 (-1 ~ 166) 168
5443 22:18:32.604366 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5444 22:18:32.606986 iDelay=199, Bit 11, Center 86 (3 ~ 170) 168
5445 22:18:32.613582 iDelay=199, Bit 12, Center 100 (19 ~ 182) 164
5446 22:18:32.617170 iDelay=199, Bit 13, Center 100 (19 ~ 182) 164
5447 22:18:32.620646 iDelay=199, Bit 14, Center 102 (19 ~ 186) 168
5448 22:18:32.624406 iDelay=199, Bit 15, Center 102 (19 ~ 186) 168
5449 22:18:32.624489 ==
5450 22:18:32.627329 Dram Type= 6, Freq= 0, CH_0, rank 1
5451 22:18:32.633966 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5452 22:18:32.634051 ==
5453 22:18:32.634116 DQS Delay:
5454 22:18:32.637182 DQS0 = 0, DQS1 = 0
5455 22:18:32.637263 DQM Delay:
5456 22:18:32.637327 DQM0 = 104, DQM1 = 93
5457 22:18:32.640642 DQ Delay:
5458 22:18:32.643745 DQ0 =102, DQ1 =104, DQ2 =102, DQ3 =102
5459 22:18:32.646988 DQ4 =106, DQ5 =98, DQ6 =110, DQ7 =112
5460 22:18:32.650487 DQ8 =84, DQ9 =82, DQ10 =94, DQ11 =86
5461 22:18:32.653631 DQ12 =100, DQ13 =100, DQ14 =102, DQ15 =102
5462 22:18:32.653712
5463 22:18:32.653777
5464 22:18:32.660470 [DQSOSCAuto] RK1, (LSB)MR18= 0x2901, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 408 ps
5465 22:18:32.663926 CH0 RK1: MR19=505, MR18=2901
5466 22:18:32.670668 CH0_RK1: MR19=0x505, MR18=0x2901, DQSOSC=408, MR23=63, INC=65, DEC=43
5467 22:18:32.673792 [RxdqsGatingPostProcess] freq 933
5468 22:18:32.680430 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5469 22:18:32.683586 best DQS0 dly(2T, 0.5T) = (0, 10)
5470 22:18:32.683669 best DQS1 dly(2T, 0.5T) = (0, 10)
5471 22:18:32.687330 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5472 22:18:32.690770 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5473 22:18:32.693645 best DQS0 dly(2T, 0.5T) = (0, 10)
5474 22:18:32.697249 best DQS1 dly(2T, 0.5T) = (0, 10)
5475 22:18:32.700735 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5476 22:18:32.703657 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5477 22:18:32.707269 Pre-setting of DQS Precalculation
5478 22:18:32.713884 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5479 22:18:32.713967 ==
5480 22:18:32.717433 Dram Type= 6, Freq= 0, CH_1, rank 0
5481 22:18:32.720564 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5482 22:18:32.720645 ==
5483 22:18:32.726846 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5484 22:18:32.729962 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5485 22:18:32.734106 [CA 0] Center 36 (6~67) winsize 62
5486 22:18:32.737712 [CA 1] Center 37 (6~68) winsize 63
5487 22:18:32.741029 [CA 2] Center 34 (4~65) winsize 62
5488 22:18:32.744362 [CA 3] Center 34 (4~65) winsize 62
5489 22:18:32.747579 [CA 4] Center 34 (4~65) winsize 62
5490 22:18:32.750647 [CA 5] Center 33 (3~64) winsize 62
5491 22:18:32.750731
5492 22:18:32.754538 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5493 22:18:32.754623
5494 22:18:32.757866 [CATrainingPosCal] consider 1 rank data
5495 22:18:32.761319 u2DelayCellTimex100 = 270/100 ps
5496 22:18:32.763961 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5497 22:18:32.767788 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5498 22:18:32.774271 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5499 22:18:32.777482 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5500 22:18:32.780780 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5501 22:18:32.784302 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5502 22:18:32.784398
5503 22:18:32.787241 CA PerBit enable=1, Macro0, CA PI delay=33
5504 22:18:32.787330
5505 22:18:32.791058 [CBTSetCACLKResult] CA Dly = 33
5506 22:18:32.791133 CS Dly: 7 (0~38)
5507 22:18:32.794025 ==
5508 22:18:32.794114 Dram Type= 6, Freq= 0, CH_1, rank 1
5509 22:18:32.801102 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5510 22:18:32.801189 ==
5511 22:18:32.804035 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5512 22:18:32.810747 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5513 22:18:32.814255 [CA 0] Center 36 (6~67) winsize 62
5514 22:18:32.817745 [CA 1] Center 37 (7~68) winsize 62
5515 22:18:32.820772 [CA 2] Center 35 (5~65) winsize 61
5516 22:18:32.824256 [CA 3] Center 34 (4~65) winsize 62
5517 22:18:32.827543 [CA 4] Center 34 (4~65) winsize 62
5518 22:18:32.831064 [CA 5] Center 33 (3~64) winsize 62
5519 22:18:32.831149
5520 22:18:32.834043 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5521 22:18:32.834127
5522 22:18:32.838132 [CATrainingPosCal] consider 2 rank data
5523 22:18:32.840857 u2DelayCellTimex100 = 270/100 ps
5524 22:18:32.844437 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5525 22:18:32.847426 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5526 22:18:32.854077 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5527 22:18:32.857758 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5528 22:18:32.861026 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5529 22:18:32.864215 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5530 22:18:32.864324
5531 22:18:32.867438 CA PerBit enable=1, Macro0, CA PI delay=33
5532 22:18:32.867514
5533 22:18:32.870756 [CBTSetCACLKResult] CA Dly = 33
5534 22:18:32.870830 CS Dly: 8 (0~40)
5535 22:18:32.870892
5536 22:18:32.874209 ----->DramcWriteLeveling(PI) begin...
5537 22:18:32.877359 ==
5538 22:18:32.880599 Dram Type= 6, Freq= 0, CH_1, rank 0
5539 22:18:32.884649 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5540 22:18:32.884741 ==
5541 22:18:32.887214 Write leveling (Byte 0): 27 => 27
5542 22:18:32.890805 Write leveling (Byte 1): 28 => 28
5543 22:18:32.893761 DramcWriteLeveling(PI) end<-----
5544 22:18:32.893846
5545 22:18:32.893915 ==
5546 22:18:32.897121 Dram Type= 6, Freq= 0, CH_1, rank 0
5547 22:18:32.900473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5548 22:18:32.900558 ==
5549 22:18:32.903948 [Gating] SW mode calibration
5550 22:18:32.910392 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5551 22:18:32.917344 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5552 22:18:32.920373 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5553 22:18:32.924140 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5554 22:18:32.930892 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5555 22:18:32.933819 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5556 22:18:32.936796 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5557 22:18:32.943545 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5558 22:18:32.947136 0 14 24 | B1->B0 | 3333 2c2c | 0 0 | (0 1) (0 0)
5559 22:18:32.950291 0 14 28 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
5560 22:18:32.956946 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5561 22:18:32.960337 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5562 22:18:32.963683 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5563 22:18:32.966975 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5564 22:18:32.973507 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5565 22:18:32.976836 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5566 22:18:32.980114 0 15 24 | B1->B0 | 2323 3131 | 0 1 | (0 0) (0 0)
5567 22:18:32.987048 0 15 28 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5568 22:18:32.990364 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5569 22:18:32.993814 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5570 22:18:33.000530 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5571 22:18:33.003425 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5572 22:18:33.006776 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5573 22:18:33.013473 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5574 22:18:33.016740 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5575 22:18:33.020092 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5576 22:18:33.026689 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5577 22:18:33.030361 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5578 22:18:33.033303 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5579 22:18:33.040384 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5580 22:18:33.043385 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5581 22:18:33.046891 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5582 22:18:33.053150 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5583 22:18:33.056821 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5584 22:18:33.059854 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5585 22:18:33.066589 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5586 22:18:33.070043 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5587 22:18:33.073478 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5588 22:18:33.079527 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5589 22:18:33.083145 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5590 22:18:33.086389 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5591 22:18:33.093025 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5592 22:18:33.096295 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5593 22:18:33.099338 Total UI for P1: 0, mck2ui 16
5594 22:18:33.102994 best dqsien dly found for B0: ( 1, 2, 24)
5595 22:18:33.106503 Total UI for P1: 0, mck2ui 16
5596 22:18:33.109909 best dqsien dly found for B1: ( 1, 2, 24)
5597 22:18:33.113100 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5598 22:18:33.116013 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5599 22:18:33.116096
5600 22:18:33.119724 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5601 22:18:33.122914 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5602 22:18:33.126116 [Gating] SW calibration Done
5603 22:18:33.126195 ==
5604 22:18:33.129690 Dram Type= 6, Freq= 0, CH_1, rank 0
5605 22:18:33.133287 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5606 22:18:33.133368 ==
5607 22:18:33.136172 RX Vref Scan: 0
5608 22:18:33.136247
5609 22:18:33.139209 RX Vref 0 -> 0, step: 1
5610 22:18:33.139287
5611 22:18:33.139352 RX Delay -80 -> 252, step: 8
5612 22:18:33.146851 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5613 22:18:33.149616 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5614 22:18:33.153030 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5615 22:18:33.156632 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5616 22:18:33.159754 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5617 22:18:33.162936 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5618 22:18:33.169302 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5619 22:18:33.172958 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5620 22:18:33.176073 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5621 22:18:33.179462 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5622 22:18:33.182594 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5623 22:18:33.186005 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5624 22:18:33.193005 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5625 22:18:33.196418 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5626 22:18:33.199661 iDelay=208, Bit 14, Center 107 (16 ~ 199) 184
5627 22:18:33.203030 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5628 22:18:33.203111 ==
5629 22:18:33.206170 Dram Type= 6, Freq= 0, CH_1, rank 0
5630 22:18:33.212615 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5631 22:18:33.212752 ==
5632 22:18:33.212878 DQS Delay:
5633 22:18:33.212990 DQS0 = 0, DQS1 = 0
5634 22:18:33.216353 DQM Delay:
5635 22:18:33.216435 DQM0 = 102, DQM1 = 99
5636 22:18:33.219536 DQ Delay:
5637 22:18:33.222825 DQ0 =107, DQ1 =99, DQ2 =91, DQ3 =99
5638 22:18:33.226344 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =103
5639 22:18:33.229544 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =91
5640 22:18:33.232832 DQ12 =107, DQ13 =107, DQ14 =107, DQ15 =107
5641 22:18:33.232913
5642 22:18:33.232989
5643 22:18:33.233081 ==
5644 22:18:33.236400 Dram Type= 6, Freq= 0, CH_1, rank 0
5645 22:18:33.239572 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5646 22:18:33.239655 ==
5647 22:18:33.239719
5648 22:18:33.239777
5649 22:18:33.243136 TX Vref Scan disable
5650 22:18:33.246523 == TX Byte 0 ==
5651 22:18:33.249659 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5652 22:18:33.253371 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5653 22:18:33.256235 == TX Byte 1 ==
5654 22:18:33.259761 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5655 22:18:33.263133 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5656 22:18:33.263215 ==
5657 22:18:33.266554 Dram Type= 6, Freq= 0, CH_1, rank 0
5658 22:18:33.269415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5659 22:18:33.269546 ==
5660 22:18:33.273220
5661 22:18:33.273302
5662 22:18:33.273367 TX Vref Scan disable
5663 22:18:33.276063 == TX Byte 0 ==
5664 22:18:33.279681 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5665 22:18:33.286287 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5666 22:18:33.286370 == TX Byte 1 ==
5667 22:18:33.289390 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5668 22:18:33.296067 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5669 22:18:33.296152
5670 22:18:33.296217 [DATLAT]
5671 22:18:33.296277 Freq=933, CH1 RK0
5672 22:18:33.296341
5673 22:18:33.299779 DATLAT Default: 0xd
5674 22:18:33.299856 0, 0xFFFF, sum = 0
5675 22:18:33.302767 1, 0xFFFF, sum = 0
5676 22:18:33.302846 2, 0xFFFF, sum = 0
5677 22:18:33.306135 3, 0xFFFF, sum = 0
5678 22:18:33.309233 4, 0xFFFF, sum = 0
5679 22:18:33.309311 5, 0xFFFF, sum = 0
5680 22:18:33.312857 6, 0xFFFF, sum = 0
5681 22:18:33.312931 7, 0xFFFF, sum = 0
5682 22:18:33.316301 8, 0xFFFF, sum = 0
5683 22:18:33.316378 9, 0xFFFF, sum = 0
5684 22:18:33.319220 10, 0x0, sum = 1
5685 22:18:33.319299 11, 0x0, sum = 2
5686 22:18:33.322841 12, 0x0, sum = 3
5687 22:18:33.322917 13, 0x0, sum = 4
5688 22:18:33.322982 best_step = 11
5689 22:18:33.323041
5690 22:18:33.326249 ==
5691 22:18:33.329246 Dram Type= 6, Freq= 0, CH_1, rank 0
5692 22:18:33.332376 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5693 22:18:33.332451 ==
5694 22:18:33.332540 RX Vref Scan: 1
5695 22:18:33.332639
5696 22:18:33.335792 RX Vref 0 -> 0, step: 1
5697 22:18:33.335872
5698 22:18:33.339032 RX Delay -45 -> 252, step: 4
5699 22:18:33.339116
5700 22:18:33.342456 Set Vref, RX VrefLevel [Byte0]: 56
5701 22:18:33.345597 [Byte1]: 52
5702 22:18:33.345673
5703 22:18:33.349201 Final RX Vref Byte 0 = 56 to rank0
5704 22:18:33.352715 Final RX Vref Byte 1 = 52 to rank0
5705 22:18:33.355837 Final RX Vref Byte 0 = 56 to rank1
5706 22:18:33.358910 Final RX Vref Byte 1 = 52 to rank1==
5707 22:18:33.362401 Dram Type= 6, Freq= 0, CH_1, rank 0
5708 22:18:33.365434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5709 22:18:33.369122 ==
5710 22:18:33.369205 DQS Delay:
5711 22:18:33.369270 DQS0 = 0, DQS1 = 0
5712 22:18:33.372085 DQM Delay:
5713 22:18:33.372168 DQM0 = 104, DQM1 = 98
5714 22:18:33.375907 DQ Delay:
5715 22:18:33.378857 DQ0 =106, DQ1 =98, DQ2 =94, DQ3 =102
5716 22:18:33.382521 DQ4 =102, DQ5 =114, DQ6 =112, DQ7 =104
5717 22:18:33.385426 DQ8 =90, DQ9 =92, DQ10 =100, DQ11 =94
5718 22:18:33.389002 DQ12 =104, DQ13 =102, DQ14 =104, DQ15 =104
5719 22:18:33.389076
5720 22:18:33.389142
5721 22:18:33.395927 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a31, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 413 ps
5722 22:18:33.399141 CH1 RK0: MR19=505, MR18=1A31
5723 22:18:33.405364 CH1_RK0: MR19=0x505, MR18=0x1A31, DQSOSC=406, MR23=63, INC=65, DEC=43
5724 22:18:33.405462
5725 22:18:33.408722 ----->DramcWriteLeveling(PI) begin...
5726 22:18:33.408800 ==
5727 22:18:33.412125 Dram Type= 6, Freq= 0, CH_1, rank 1
5728 22:18:33.415536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5729 22:18:33.415615 ==
5730 22:18:33.418951 Write leveling (Byte 0): 28 => 28
5731 22:18:33.421943 Write leveling (Byte 1): 28 => 28
5732 22:18:33.425457 DramcWriteLeveling(PI) end<-----
5733 22:18:33.425572
5734 22:18:33.425643 ==
5735 22:18:33.428939 Dram Type= 6, Freq= 0, CH_1, rank 1
5736 22:18:33.432129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5737 22:18:33.432211 ==
5738 22:18:33.435766 [Gating] SW mode calibration
5739 22:18:33.442289 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5740 22:18:33.448582 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5741 22:18:33.452553 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5742 22:18:33.458731 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5743 22:18:33.461852 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5744 22:18:33.465451 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5745 22:18:33.472284 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5746 22:18:33.475321 0 14 20 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5747 22:18:33.478896 0 14 24 | B1->B0 | 2f2f 3131 | 0 1 | (0 1) (0 1)
5748 22:18:33.485410 0 14 28 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
5749 22:18:33.488917 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5750 22:18:33.491912 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5751 22:18:33.498484 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5752 22:18:33.502352 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5753 22:18:33.505213 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5754 22:18:33.511717 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5755 22:18:33.515336 0 15 24 | B1->B0 | 3636 2b2b | 1 0 | (0 0) (0 0)
5756 22:18:33.518524 0 15 28 | B1->B0 | 4646 4343 | 0 1 | (0 0) (0 0)
5757 22:18:33.524905 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5758 22:18:33.527996 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5759 22:18:33.531233 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5760 22:18:33.538517 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5761 22:18:33.541184 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5762 22:18:33.544782 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5763 22:18:33.551758 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5764 22:18:33.554459 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5765 22:18:33.557738 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5766 22:18:33.564426 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5767 22:18:33.567967 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5768 22:18:33.571007 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5769 22:18:33.574715 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5770 22:18:33.581275 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5771 22:18:33.584171 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5772 22:18:33.587774 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5773 22:18:33.594517 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5774 22:18:33.597841 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5775 22:18:33.600923 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5776 22:18:33.607707 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5777 22:18:33.611047 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5778 22:18:33.614126 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5779 22:18:33.620792 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5780 22:18:33.623621 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5781 22:18:33.627632 Total UI for P1: 0, mck2ui 16
5782 22:18:33.630857 best dqsien dly found for B0: ( 1, 2, 26)
5783 22:18:33.633970 Total UI for P1: 0, mck2ui 16
5784 22:18:33.637150 best dqsien dly found for B1: ( 1, 2, 24)
5785 22:18:33.640647 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5786 22:18:33.644039 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5787 22:18:33.644118
5788 22:18:33.647479 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5789 22:18:33.654236 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5790 22:18:33.654325 [Gating] SW calibration Done
5791 22:18:33.654393 ==
5792 22:18:33.657788 Dram Type= 6, Freq= 0, CH_1, rank 1
5793 22:18:33.663715 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5794 22:18:33.663828 ==
5795 22:18:33.663896 RX Vref Scan: 0
5796 22:18:33.663965
5797 22:18:33.666977 RX Vref 0 -> 0, step: 1
5798 22:18:33.667052
5799 22:18:33.670251 RX Delay -80 -> 252, step: 8
5800 22:18:33.673344 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5801 22:18:33.677287 iDelay=208, Bit 1, Center 103 (16 ~ 191) 176
5802 22:18:33.680133 iDelay=208, Bit 2, Center 95 (8 ~ 183) 176
5803 22:18:33.683707 iDelay=208, Bit 3, Center 99 (16 ~ 183) 168
5804 22:18:33.690147 iDelay=208, Bit 4, Center 99 (16 ~ 183) 168
5805 22:18:33.693649 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5806 22:18:33.696704 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5807 22:18:33.700161 iDelay=208, Bit 7, Center 103 (16 ~ 191) 176
5808 22:18:33.703323 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5809 22:18:33.709917 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184
5810 22:18:33.713724 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5811 22:18:33.716982 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5812 22:18:33.720660 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5813 22:18:33.723826 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5814 22:18:33.730442 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5815 22:18:33.733332 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5816 22:18:33.733403 ==
5817 22:18:33.736585 Dram Type= 6, Freq= 0, CH_1, rank 1
5818 22:18:33.740240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5819 22:18:33.740318 ==
5820 22:18:33.740383 DQS Delay:
5821 22:18:33.743626 DQS0 = 0, DQS1 = 0
5822 22:18:33.743710 DQM Delay:
5823 22:18:33.746867 DQM0 = 104, DQM1 = 99
5824 22:18:33.746950 DQ Delay:
5825 22:18:33.750152 DQ0 =107, DQ1 =103, DQ2 =95, DQ3 =99
5826 22:18:33.753034 DQ4 =99, DQ5 =115, DQ6 =115, DQ7 =103
5827 22:18:33.756772 DQ8 =87, DQ9 =91, DQ10 =99, DQ11 =91
5828 22:18:33.759688 DQ12 =107, DQ13 =107, DQ14 =103, DQ15 =107
5829 22:18:33.759772
5830 22:18:33.759846
5831 22:18:33.762953 ==
5832 22:18:33.763031 Dram Type= 6, Freq= 0, CH_1, rank 1
5833 22:18:33.770298 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5834 22:18:33.770381 ==
5835 22:18:33.770446
5836 22:18:33.770504
5837 22:18:33.770561 TX Vref Scan disable
5838 22:18:33.773688 == TX Byte 0 ==
5839 22:18:33.777168 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5840 22:18:33.783661 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5841 22:18:33.783744 == TX Byte 1 ==
5842 22:18:33.787472 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5843 22:18:33.790317 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5844 22:18:33.794008 ==
5845 22:18:33.797053 Dram Type= 6, Freq= 0, CH_1, rank 1
5846 22:18:33.800141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5847 22:18:33.800223 ==
5848 22:18:33.800289
5849 22:18:33.800347
5850 22:18:33.803520 TX Vref Scan disable
5851 22:18:33.803626 == TX Byte 0 ==
5852 22:18:33.810191 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5853 22:18:33.813368 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5854 22:18:33.813472 == TX Byte 1 ==
5855 22:18:33.820015 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5856 22:18:33.823561 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5857 22:18:33.823670
5858 22:18:33.823765 [DATLAT]
5859 22:18:33.826837 Freq=933, CH1 RK1
5860 22:18:33.826941
5861 22:18:33.827033 DATLAT Default: 0xb
5862 22:18:33.830064 0, 0xFFFF, sum = 0
5863 22:18:33.830170 1, 0xFFFF, sum = 0
5864 22:18:33.833363 2, 0xFFFF, sum = 0
5865 22:18:33.833464 3, 0xFFFF, sum = 0
5866 22:18:33.836715 4, 0xFFFF, sum = 0
5867 22:18:33.840182 5, 0xFFFF, sum = 0
5868 22:18:33.840259 6, 0xFFFF, sum = 0
5869 22:18:33.843461 7, 0xFFFF, sum = 0
5870 22:18:33.843538 8, 0xFFFF, sum = 0
5871 22:18:33.846763 9, 0xFFFF, sum = 0
5872 22:18:33.846865 10, 0x0, sum = 1
5873 22:18:33.850221 11, 0x0, sum = 2
5874 22:18:33.850298 12, 0x0, sum = 3
5875 22:18:33.850375 13, 0x0, sum = 4
5876 22:18:33.853159 best_step = 11
5877 22:18:33.853257
5878 22:18:33.853371 ==
5879 22:18:33.856583 Dram Type= 6, Freq= 0, CH_1, rank 1
5880 22:18:33.860186 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5881 22:18:33.860268 ==
5882 22:18:33.863125 RX Vref Scan: 0
5883 22:18:33.863207
5884 22:18:33.866443 RX Vref 0 -> 0, step: 1
5885 22:18:33.866550
5886 22:18:33.866642 RX Delay -45 -> 252, step: 4
5887 22:18:33.874083 iDelay=203, Bit 0, Center 110 (27 ~ 194) 168
5888 22:18:33.877285 iDelay=203, Bit 1, Center 102 (19 ~ 186) 168
5889 22:18:33.880822 iDelay=203, Bit 2, Center 94 (11 ~ 178) 168
5890 22:18:33.884025 iDelay=203, Bit 3, Center 98 (19 ~ 178) 160
5891 22:18:33.887167 iDelay=203, Bit 4, Center 100 (19 ~ 182) 164
5892 22:18:33.893768 iDelay=203, Bit 5, Center 118 (35 ~ 202) 168
5893 22:18:33.897471 iDelay=203, Bit 6, Center 112 (27 ~ 198) 172
5894 22:18:33.900521 iDelay=203, Bit 7, Center 104 (19 ~ 190) 172
5895 22:18:33.903913 iDelay=203, Bit 8, Center 90 (7 ~ 174) 168
5896 22:18:33.907482 iDelay=203, Bit 9, Center 92 (7 ~ 178) 172
5897 22:18:33.910514 iDelay=203, Bit 10, Center 98 (11 ~ 186) 176
5898 22:18:33.917447 iDelay=203, Bit 11, Center 92 (7 ~ 178) 172
5899 22:18:33.920525 iDelay=203, Bit 12, Center 110 (23 ~ 198) 176
5900 22:18:33.924107 iDelay=203, Bit 13, Center 106 (23 ~ 190) 168
5901 22:18:33.927514 iDelay=203, Bit 14, Center 104 (23 ~ 186) 164
5902 22:18:33.933643 iDelay=203, Bit 15, Center 108 (23 ~ 194) 172
5903 22:18:33.933752 ==
5904 22:18:33.937172 Dram Type= 6, Freq= 0, CH_1, rank 1
5905 22:18:33.940304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5906 22:18:33.940419 ==
5907 22:18:33.940548 DQS Delay:
5908 22:18:33.943718 DQS0 = 0, DQS1 = 0
5909 22:18:33.943832 DQM Delay:
5910 22:18:33.947381 DQM0 = 104, DQM1 = 100
5911 22:18:33.947475 DQ Delay:
5912 22:18:33.950142 DQ0 =110, DQ1 =102, DQ2 =94, DQ3 =98
5913 22:18:33.953734 DQ4 =100, DQ5 =118, DQ6 =112, DQ7 =104
5914 22:18:33.956976 DQ8 =90, DQ9 =92, DQ10 =98, DQ11 =92
5915 22:18:33.960369 DQ12 =110, DQ13 =106, DQ14 =104, DQ15 =108
5916 22:18:33.960475
5917 22:18:33.960564
5918 22:18:33.970399 [DQSOSCAuto] RK1, (LSB)MR18= 0x2c00, (MSB)MR19= 0x505, tDQSOscB0 = 422 ps tDQSOscB1 = 408 ps
5919 22:18:33.970488 CH1 RK1: MR19=505, MR18=2C00
5920 22:18:33.976827 CH1_RK1: MR19=0x505, MR18=0x2C00, DQSOSC=408, MR23=63, INC=65, DEC=43
5921 22:18:33.980008 [RxdqsGatingPostProcess] freq 933
5922 22:18:33.986638 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5923 22:18:33.990316 best DQS0 dly(2T, 0.5T) = (0, 10)
5924 22:18:33.993618 best DQS1 dly(2T, 0.5T) = (0, 10)
5925 22:18:33.996577 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5926 22:18:34.000098 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5927 22:18:34.003237 best DQS0 dly(2T, 0.5T) = (0, 10)
5928 22:18:34.006840 best DQS1 dly(2T, 0.5T) = (0, 10)
5929 22:18:34.010443 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5930 22:18:34.010527 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5931 22:18:34.013418 Pre-setting of DQS Precalculation
5932 22:18:34.019909 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5933 22:18:34.026733 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5934 22:18:34.033403 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5935 22:18:34.033544
5936 22:18:34.033642
5937 22:18:34.036375 [Calibration Summary] 1866 Mbps
5938 22:18:34.039749 CH 0, Rank 0
5939 22:18:34.039833 SW Impedance : PASS
5940 22:18:34.043240 DUTY Scan : NO K
5941 22:18:34.046621 ZQ Calibration : PASS
5942 22:18:34.046705 Jitter Meter : NO K
5943 22:18:34.049733 CBT Training : PASS
5944 22:18:34.053294 Write leveling : PASS
5945 22:18:34.053377 RX DQS gating : PASS
5946 22:18:34.056144 RX DQ/DQS(RDDQC) : PASS
5947 22:18:34.056225 TX DQ/DQS : PASS
5948 22:18:34.059837 RX DATLAT : PASS
5949 22:18:34.062988 RX DQ/DQS(Engine): PASS
5950 22:18:34.063069 TX OE : NO K
5951 22:18:34.066313 All Pass.
5952 22:18:34.066430
5953 22:18:34.066499 CH 0, Rank 1
5954 22:18:34.069450 SW Impedance : PASS
5955 22:18:34.069586 DUTY Scan : NO K
5956 22:18:34.073173 ZQ Calibration : PASS
5957 22:18:34.076180 Jitter Meter : NO K
5958 22:18:34.076262 CBT Training : PASS
5959 22:18:34.079560 Write leveling : PASS
5960 22:18:34.082985 RX DQS gating : PASS
5961 22:18:34.083066 RX DQ/DQS(RDDQC) : PASS
5962 22:18:34.086431 TX DQ/DQS : PASS
5963 22:18:34.089811 RX DATLAT : PASS
5964 22:18:34.089892 RX DQ/DQS(Engine): PASS
5965 22:18:34.092718 TX OE : NO K
5966 22:18:34.092799 All Pass.
5967 22:18:34.092863
5968 22:18:34.096003 CH 1, Rank 0
5969 22:18:34.096092 SW Impedance : PASS
5970 22:18:34.099659 DUTY Scan : NO K
5971 22:18:34.102733 ZQ Calibration : PASS
5972 22:18:34.102809 Jitter Meter : NO K
5973 22:18:34.106184 CBT Training : PASS
5974 22:18:34.109366 Write leveling : PASS
5975 22:18:34.109464 RX DQS gating : PASS
5976 22:18:34.113023 RX DQ/DQS(RDDQC) : PASS
5977 22:18:34.113102 TX DQ/DQS : PASS
5978 22:18:34.115963 RX DATLAT : PASS
5979 22:18:34.119529 RX DQ/DQS(Engine): PASS
5980 22:18:34.119628 TX OE : NO K
5981 22:18:34.122511 All Pass.
5982 22:18:34.122583
5983 22:18:34.122646 CH 1, Rank 1
5984 22:18:34.125676 SW Impedance : PASS
5985 22:18:34.125754 DUTY Scan : NO K
5986 22:18:34.129073 ZQ Calibration : PASS
5987 22:18:34.132866 Jitter Meter : NO K
5988 22:18:34.132939 CBT Training : PASS
5989 22:18:34.136025 Write leveling : PASS
5990 22:18:34.139536 RX DQS gating : PASS
5991 22:18:34.139611 RX DQ/DQS(RDDQC) : PASS
5992 22:18:34.142469 TX DQ/DQS : PASS
5993 22:18:34.145769 RX DATLAT : PASS
5994 22:18:34.145847 RX DQ/DQS(Engine): PASS
5995 22:18:34.149199 TX OE : NO K
5996 22:18:34.149275 All Pass.
5997 22:18:34.149345
5998 22:18:34.152674 DramC Write-DBI off
5999 22:18:34.155728 PER_BANK_REFRESH: Hybrid Mode
6000 22:18:34.155800 TX_TRACKING: ON
6001 22:18:34.165998 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6002 22:18:34.169266 [FAST_K] Save calibration result to emmc
6003 22:18:34.172199 dramc_set_vcore_voltage set vcore to 650000
6004 22:18:34.175655 Read voltage for 400, 6
6005 22:18:34.175730 Vio18 = 0
6006 22:18:34.175793 Vcore = 650000
6007 22:18:34.179206 Vdram = 0
6008 22:18:34.179277 Vddq = 0
6009 22:18:34.179344 Vmddr = 0
6010 22:18:34.185696 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6011 22:18:34.189289 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6012 22:18:34.192610 MEM_TYPE=3, freq_sel=20
6013 22:18:34.195793 sv_algorithm_assistance_LP4_800
6014 22:18:34.199383 ============ PULL DRAM RESETB DOWN ============
6015 22:18:34.202345 ========== PULL DRAM RESETB DOWN end =========
6016 22:18:34.209262 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6017 22:18:34.212527 ===================================
6018 22:18:34.212604 LPDDR4 DRAM CONFIGURATION
6019 22:18:34.215372 ===================================
6020 22:18:34.219151 EX_ROW_EN[0] = 0x0
6021 22:18:34.222204 EX_ROW_EN[1] = 0x0
6022 22:18:34.222279 LP4Y_EN = 0x0
6023 22:18:34.225758 WORK_FSP = 0x0
6024 22:18:34.225836 WL = 0x2
6025 22:18:34.228836 RL = 0x2
6026 22:18:34.228906 BL = 0x2
6027 22:18:34.232575 RPST = 0x0
6028 22:18:34.232646 RD_PRE = 0x0
6029 22:18:34.235297 WR_PRE = 0x1
6030 22:18:34.235369 WR_PST = 0x0
6031 22:18:34.238839 DBI_WR = 0x0
6032 22:18:34.238909 DBI_RD = 0x0
6033 22:18:34.242673 OTF = 0x1
6034 22:18:34.245580 ===================================
6035 22:18:34.248731 ===================================
6036 22:18:34.248802 ANA top config
6037 22:18:34.252043 ===================================
6038 22:18:34.255770 DLL_ASYNC_EN = 0
6039 22:18:34.258941 ALL_SLAVE_EN = 1
6040 22:18:34.262330 NEW_RANK_MODE = 1
6041 22:18:34.262408 DLL_IDLE_MODE = 1
6042 22:18:34.265329 LP45_APHY_COMB_EN = 1
6043 22:18:34.268630 TX_ODT_DIS = 1
6044 22:18:34.271895 NEW_8X_MODE = 1
6045 22:18:34.275249 ===================================
6046 22:18:34.278701 ===================================
6047 22:18:34.282399 data_rate = 800
6048 22:18:34.282473 CKR = 1
6049 22:18:34.285155 DQ_P2S_RATIO = 4
6050 22:18:34.288838 ===================================
6051 22:18:34.292329 CA_P2S_RATIO = 4
6052 22:18:34.295318 DQ_CA_OPEN = 0
6053 22:18:34.298424 DQ_SEMI_OPEN = 1
6054 22:18:34.301870 CA_SEMI_OPEN = 1
6055 22:18:34.301943 CA_FULL_RATE = 0
6056 22:18:34.305127 DQ_CKDIV4_EN = 0
6057 22:18:34.308354 CA_CKDIV4_EN = 1
6058 22:18:34.312001 CA_PREDIV_EN = 0
6059 22:18:34.314792 PH8_DLY = 0
6060 22:18:34.318392 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6061 22:18:34.318464 DQ_AAMCK_DIV = 0
6062 22:18:34.321619 CA_AAMCK_DIV = 0
6063 22:18:34.324915 CA_ADMCK_DIV = 4
6064 22:18:34.328574 DQ_TRACK_CA_EN = 0
6065 22:18:34.331617 CA_PICK = 800
6066 22:18:34.334863 CA_MCKIO = 400
6067 22:18:34.334935 MCKIO_SEMI = 400
6068 22:18:34.338321 PLL_FREQ = 3016
6069 22:18:34.342079 DQ_UI_PI_RATIO = 32
6070 22:18:34.345278 CA_UI_PI_RATIO = 32
6071 22:18:34.348110 ===================================
6072 22:18:34.351674 ===================================
6073 22:18:34.355162 memory_type:LPDDR4
6074 22:18:34.355236 GP_NUM : 10
6075 22:18:34.358121 SRAM_EN : 1
6076 22:18:34.361470 MD32_EN : 0
6077 22:18:34.364977 ===================================
6078 22:18:34.365053 [ANA_INIT] >>>>>>>>>>>>>>
6079 22:18:34.368169 <<<<<< [CONFIGURE PHASE]: ANA_TX
6080 22:18:34.371865 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6081 22:18:34.374808 ===================================
6082 22:18:34.377973 data_rate = 800,PCW = 0X7400
6083 22:18:34.381672 ===================================
6084 22:18:34.384809 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6085 22:18:34.391653 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6086 22:18:34.401703 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6087 22:18:34.407804 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6088 22:18:34.411397 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6089 22:18:34.414905 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6090 22:18:34.414990 [ANA_INIT] flow start
6091 22:18:34.418553 [ANA_INIT] PLL >>>>>>>>
6092 22:18:34.421471 [ANA_INIT] PLL <<<<<<<<
6093 22:18:34.421602 [ANA_INIT] MIDPI >>>>>>>>
6094 22:18:34.425045 [ANA_INIT] MIDPI <<<<<<<<
6095 22:18:34.428169 [ANA_INIT] DLL >>>>>>>>
6096 22:18:34.428275 [ANA_INIT] flow end
6097 22:18:34.431641 ============ LP4 DIFF to SE enter ============
6098 22:18:34.438165 ============ LP4 DIFF to SE exit ============
6099 22:18:34.438267 [ANA_INIT] <<<<<<<<<<<<<
6100 22:18:34.441216 [Flow] Enable top DCM control >>>>>
6101 22:18:34.444456 [Flow] Enable top DCM control <<<<<
6102 22:18:34.447931 Enable DLL master slave shuffle
6103 22:18:34.454514 ==============================================================
6104 22:18:34.457609 Gating Mode config
6105 22:18:34.461041 ==============================================================
6106 22:18:34.464616 Config description:
6107 22:18:34.474586 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6108 22:18:34.480900 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6109 22:18:34.484406 SELPH_MODE 0: By rank 1: By Phase
6110 22:18:34.490728 ==============================================================
6111 22:18:34.494567 GAT_TRACK_EN = 0
6112 22:18:34.497968 RX_GATING_MODE = 2
6113 22:18:34.501032 RX_GATING_TRACK_MODE = 2
6114 22:18:34.501132 SELPH_MODE = 1
6115 22:18:34.504578 PICG_EARLY_EN = 1
6116 22:18:34.507396 VALID_LAT_VALUE = 1
6117 22:18:34.514230 ==============================================================
6118 22:18:34.517278 Enter into Gating configuration >>>>
6119 22:18:34.521201 Exit from Gating configuration <<<<
6120 22:18:34.525065 Enter into DVFS_PRE_config >>>>>
6121 22:18:34.533869 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6122 22:18:34.537540 Exit from DVFS_PRE_config <<<<<
6123 22:18:34.540899 Enter into PICG configuration >>>>
6124 22:18:34.544154 Exit from PICG configuration <<<<
6125 22:18:34.547724 [RX_INPUT] configuration >>>>>
6126 22:18:34.550676 [RX_INPUT] configuration <<<<<
6127 22:18:34.553865 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6128 22:18:34.560871 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6129 22:18:34.567437 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6130 22:18:34.574184 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6131 22:18:34.577733 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6132 22:18:34.583867 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6133 22:18:34.587307 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6134 22:18:34.593931 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6135 22:18:34.597746 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6136 22:18:34.600444 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6137 22:18:34.603870 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6138 22:18:34.610308 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6139 22:18:34.613761 ===================================
6140 22:18:34.617352 LPDDR4 DRAM CONFIGURATION
6141 22:18:34.620666 ===================================
6142 22:18:34.620748 EX_ROW_EN[0] = 0x0
6143 22:18:34.624187 EX_ROW_EN[1] = 0x0
6144 22:18:34.624268 LP4Y_EN = 0x0
6145 22:18:34.626954 WORK_FSP = 0x0
6146 22:18:34.627035 WL = 0x2
6147 22:18:34.630469 RL = 0x2
6148 22:18:34.630550 BL = 0x2
6149 22:18:34.633948 RPST = 0x0
6150 22:18:34.634029 RD_PRE = 0x0
6151 22:18:34.637119 WR_PRE = 0x1
6152 22:18:34.637199 WR_PST = 0x0
6153 22:18:34.640584 DBI_WR = 0x0
6154 22:18:34.640668 DBI_RD = 0x0
6155 22:18:34.644249 OTF = 0x1
6156 22:18:34.647170 ===================================
6157 22:18:34.650605 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6158 22:18:34.653713 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6159 22:18:34.660374 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6160 22:18:34.663854 ===================================
6161 22:18:34.663935 LPDDR4 DRAM CONFIGURATION
6162 22:18:34.667406 ===================================
6163 22:18:34.670294 EX_ROW_EN[0] = 0x10
6164 22:18:34.673927 EX_ROW_EN[1] = 0x0
6165 22:18:34.674008 LP4Y_EN = 0x0
6166 22:18:34.677313 WORK_FSP = 0x0
6167 22:18:34.677395 WL = 0x2
6168 22:18:34.680300 RL = 0x2
6169 22:18:34.680381 BL = 0x2
6170 22:18:34.683433 RPST = 0x0
6171 22:18:34.683528 RD_PRE = 0x0
6172 22:18:34.686778 WR_PRE = 0x1
6173 22:18:34.686892 WR_PST = 0x0
6174 22:18:34.690224 DBI_WR = 0x0
6175 22:18:34.690305 DBI_RD = 0x0
6176 22:18:34.693410 OTF = 0x1
6177 22:18:34.696992 ===================================
6178 22:18:34.703599 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6179 22:18:34.707036 nWR fixed to 30
6180 22:18:34.707118 [ModeRegInit_LP4] CH0 RK0
6181 22:18:34.709986 [ModeRegInit_LP4] CH0 RK1
6182 22:18:34.713463 [ModeRegInit_LP4] CH1 RK0
6183 22:18:34.716925 [ModeRegInit_LP4] CH1 RK1
6184 22:18:34.717006 match AC timing 19
6185 22:18:34.723833 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6186 22:18:34.726691 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6187 22:18:34.730244 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6188 22:18:34.733701 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6189 22:18:34.740174 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6190 22:18:34.740256 ==
6191 22:18:34.743550 Dram Type= 6, Freq= 0, CH_0, rank 0
6192 22:18:34.746902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6193 22:18:34.747016 ==
6194 22:18:34.753336 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6195 22:18:34.760208 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6196 22:18:34.760292 [CA 0] Center 36 (8~64) winsize 57
6197 22:18:34.763617 [CA 1] Center 36 (8~64) winsize 57
6198 22:18:34.767153 [CA 2] Center 36 (8~64) winsize 57
6199 22:18:34.770258 [CA 3] Center 36 (8~64) winsize 57
6200 22:18:34.773688 [CA 4] Center 36 (8~64) winsize 57
6201 22:18:34.777409 [CA 5] Center 36 (8~64) winsize 57
6202 22:18:34.777492
6203 22:18:34.780459 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6204 22:18:34.780542
6205 22:18:34.783681 [CATrainingPosCal] consider 1 rank data
6206 22:18:34.786752 u2DelayCellTimex100 = 270/100 ps
6207 22:18:34.790288 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6208 22:18:34.793500 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6209 22:18:34.800184 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6210 22:18:34.803439 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6211 22:18:34.806778 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6212 22:18:34.810110 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6213 22:18:34.810194
6214 22:18:34.813479 CA PerBit enable=1, Macro0, CA PI delay=36
6215 22:18:34.813583
6216 22:18:34.816762 [CBTSetCACLKResult] CA Dly = 36
6217 22:18:34.816844 CS Dly: 1 (0~32)
6218 22:18:34.816910 ==
6219 22:18:34.820782 Dram Type= 6, Freq= 0, CH_0, rank 1
6220 22:18:34.826615 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6221 22:18:34.826699 ==
6222 22:18:34.829945 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6223 22:18:34.836744 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6224 22:18:34.840089 [CA 0] Center 36 (8~64) winsize 57
6225 22:18:34.843366 [CA 1] Center 36 (8~64) winsize 57
6226 22:18:34.846706 [CA 2] Center 36 (8~64) winsize 57
6227 22:18:34.849751 [CA 3] Center 36 (8~64) winsize 57
6228 22:18:34.853387 [CA 4] Center 36 (8~64) winsize 57
6229 22:18:34.857161 [CA 5] Center 36 (8~64) winsize 57
6230 22:18:34.857240
6231 22:18:34.860024 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6232 22:18:34.860099
6233 22:18:34.863676 [CATrainingPosCal] consider 2 rank data
6234 22:18:34.866617 u2DelayCellTimex100 = 270/100 ps
6235 22:18:34.869992 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6236 22:18:34.873668 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6237 22:18:34.876522 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6238 22:18:34.880031 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6239 22:18:34.883618 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6240 22:18:34.889665 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6241 22:18:34.889741
6242 22:18:34.893238 CA PerBit enable=1, Macro0, CA PI delay=36
6243 22:18:34.893320
6244 22:18:34.896395 [CBTSetCACLKResult] CA Dly = 36
6245 22:18:34.896469 CS Dly: 1 (0~32)
6246 22:18:34.896531
6247 22:18:34.900135 ----->DramcWriteLeveling(PI) begin...
6248 22:18:34.900208 ==
6249 22:18:34.903241 Dram Type= 6, Freq= 0, CH_0, rank 0
6250 22:18:34.909864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6251 22:18:34.909943 ==
6252 22:18:34.910007 Write leveling (Byte 0): 40 => 8
6253 22:18:34.913428 Write leveling (Byte 1): 40 => 8
6254 22:18:34.916746 DramcWriteLeveling(PI) end<-----
6255 22:18:34.916819
6256 22:18:34.916881 ==
6257 22:18:34.919569 Dram Type= 6, Freq= 0, CH_0, rank 0
6258 22:18:34.926323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6259 22:18:34.926402 ==
6260 22:18:34.929939 [Gating] SW mode calibration
6261 22:18:34.936217 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6262 22:18:34.939576 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6263 22:18:34.945902 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6264 22:18:34.949440 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6265 22:18:34.953069 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6266 22:18:34.959563 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6267 22:18:34.962393 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6268 22:18:34.966391 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6269 22:18:34.969461 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6270 22:18:34.976008 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6271 22:18:34.979741 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6272 22:18:34.982505 Total UI for P1: 0, mck2ui 16
6273 22:18:34.985730 best dqsien dly found for B0: ( 0, 14, 24)
6274 22:18:34.989381 Total UI for P1: 0, mck2ui 16
6275 22:18:34.992922 best dqsien dly found for B1: ( 0, 14, 24)
6276 22:18:34.996091 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6277 22:18:34.999786 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6278 22:18:34.999867
6279 22:18:35.002507 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6280 22:18:35.009400 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6281 22:18:35.009496 [Gating] SW calibration Done
6282 22:18:35.009608 ==
6283 22:18:35.012652 Dram Type= 6, Freq= 0, CH_0, rank 0
6284 22:18:35.019377 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6285 22:18:35.019484 ==
6286 22:18:35.019577 RX Vref Scan: 0
6287 22:18:35.019665
6288 22:18:35.022900 RX Vref 0 -> 0, step: 1
6289 22:18:35.022981
6290 22:18:35.025693 RX Delay -410 -> 252, step: 16
6291 22:18:35.028997 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6292 22:18:35.032494 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6293 22:18:35.039096 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6294 22:18:35.042568 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6295 22:18:35.045957 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6296 22:18:35.049297 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6297 22:18:35.056039 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6298 22:18:35.059290 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6299 22:18:35.062963 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6300 22:18:35.066337 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6301 22:18:35.069338 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6302 22:18:35.076403 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6303 22:18:35.079277 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6304 22:18:35.083014 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6305 22:18:35.089554 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6306 22:18:35.092483 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6307 22:18:35.092563 ==
6308 22:18:35.096164 Dram Type= 6, Freq= 0, CH_0, rank 0
6309 22:18:35.099130 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6310 22:18:35.099210 ==
6311 22:18:35.102630 DQS Delay:
6312 22:18:35.102709 DQS0 = 27, DQS1 = 35
6313 22:18:35.102771 DQM Delay:
6314 22:18:35.106266 DQM0 = 9, DQM1 = 11
6315 22:18:35.106346 DQ Delay:
6316 22:18:35.109362 DQ0 =8, DQ1 =16, DQ2 =0, DQ3 =8
6317 22:18:35.112741 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6318 22:18:35.115989 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6319 22:18:35.119757 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6320 22:18:35.119837
6321 22:18:35.119899
6322 22:18:35.119957 ==
6323 22:18:35.122682 Dram Type= 6, Freq= 0, CH_0, rank 0
6324 22:18:35.126012 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6325 22:18:35.126093 ==
6326 22:18:35.126156
6327 22:18:35.129359
6328 22:18:35.129470 TX Vref Scan disable
6329 22:18:35.132607 == TX Byte 0 ==
6330 22:18:35.135897 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6331 22:18:35.139264 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6332 22:18:35.142510 == TX Byte 1 ==
6333 22:18:35.146109 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6334 22:18:35.149469 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6335 22:18:35.149574 ==
6336 22:18:35.152473 Dram Type= 6, Freq= 0, CH_0, rank 0
6337 22:18:35.155733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6338 22:18:35.155815 ==
6339 22:18:35.155879
6340 22:18:35.159218
6341 22:18:35.159298 TX Vref Scan disable
6342 22:18:35.162808 == TX Byte 0 ==
6343 22:18:35.166122 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6344 22:18:35.169378 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6345 22:18:35.173128 == TX Byte 1 ==
6346 22:18:35.176522 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6347 22:18:35.179521 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6348 22:18:35.179628
6349 22:18:35.179720 [DATLAT]
6350 22:18:35.182696 Freq=400, CH0 RK0
6351 22:18:35.182769
6352 22:18:35.182856 DATLAT Default: 0xf
6353 22:18:35.186328 0, 0xFFFF, sum = 0
6354 22:18:35.186402 1, 0xFFFF, sum = 0
6355 22:18:35.189477 2, 0xFFFF, sum = 0
6356 22:18:35.189598 3, 0xFFFF, sum = 0
6357 22:18:35.193216 4, 0xFFFF, sum = 0
6358 22:18:35.193286 5, 0xFFFF, sum = 0
6359 22:18:35.196250 6, 0xFFFF, sum = 0
6360 22:18:35.199306 7, 0xFFFF, sum = 0
6361 22:18:35.199408 8, 0xFFFF, sum = 0
6362 22:18:35.202430 9, 0xFFFF, sum = 0
6363 22:18:35.202499 10, 0xFFFF, sum = 0
6364 22:18:35.205965 11, 0xFFFF, sum = 0
6365 22:18:35.206035 12, 0xFFFF, sum = 0
6366 22:18:35.209462 13, 0x0, sum = 1
6367 22:18:35.209582 14, 0x0, sum = 2
6368 22:18:35.212466 15, 0x0, sum = 3
6369 22:18:35.212562 16, 0x0, sum = 4
6370 22:18:35.215818 best_step = 14
6371 22:18:35.215910
6372 22:18:35.216005 ==
6373 22:18:35.219488 Dram Type= 6, Freq= 0, CH_0, rank 0
6374 22:18:35.222398 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6375 22:18:35.222481 ==
6376 22:18:35.222542 RX Vref Scan: 1
6377 22:18:35.222602
6378 22:18:35.225787 RX Vref 0 -> 0, step: 1
6379 22:18:35.225881
6380 22:18:35.229053 RX Delay -311 -> 252, step: 8
6381 22:18:35.229147
6382 22:18:35.232752 Set Vref, RX VrefLevel [Byte0]: 56
6383 22:18:35.235650 [Byte1]: 47
6384 22:18:35.239452
6385 22:18:35.239525 Final RX Vref Byte 0 = 56 to rank0
6386 22:18:35.242759 Final RX Vref Byte 1 = 47 to rank0
6387 22:18:35.246708 Final RX Vref Byte 0 = 56 to rank1
6388 22:18:35.249493 Final RX Vref Byte 1 = 47 to rank1==
6389 22:18:35.252878 Dram Type= 6, Freq= 0, CH_0, rank 0
6390 22:18:35.259785 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6391 22:18:35.259895 ==
6392 22:18:35.259976 DQS Delay:
6393 22:18:35.263060 DQS0 = 28, DQS1 = 36
6394 22:18:35.263163 DQM Delay:
6395 22:18:35.263236 DQM0 = 10, DQM1 = 12
6396 22:18:35.266214 DQ Delay:
6397 22:18:35.269428 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6398 22:18:35.269569 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6399 22:18:35.272918 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
6400 22:18:35.276182 DQ12 =20, DQ13 =16, DQ14 =24, DQ15 =20
6401 22:18:35.276282
6402 22:18:35.279640
6403 22:18:35.286575 [DQSOSCAuto] RK0, (LSB)MR18= 0xccba, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 384 ps
6404 22:18:35.289373 CH0 RK0: MR19=C0C, MR18=CCBA
6405 22:18:35.295970 CH0_RK0: MR19=0xC0C, MR18=0xCCBA, DQSOSC=384, MR23=63, INC=400, DEC=267
6406 22:18:35.296071 ==
6407 22:18:35.299610 Dram Type= 6, Freq= 0, CH_0, rank 1
6408 22:18:35.302824 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6409 22:18:35.302923 ==
6410 22:18:35.306213 [Gating] SW mode calibration
6411 22:18:35.312576 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6412 22:18:35.319138 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6413 22:18:35.322713 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6414 22:18:35.325717 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6415 22:18:35.329270 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6416 22:18:35.335942 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6417 22:18:35.339648 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6418 22:18:35.342376 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6419 22:18:35.349281 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6420 22:18:35.352550 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6421 22:18:35.355784 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6422 22:18:35.359381 Total UI for P1: 0, mck2ui 16
6423 22:18:35.362561 best dqsien dly found for B0: ( 0, 14, 24)
6424 22:18:35.366108 Total UI for P1: 0, mck2ui 16
6425 22:18:35.369458 best dqsien dly found for B1: ( 0, 14, 24)
6426 22:18:35.372558 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6427 22:18:35.376414 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6428 22:18:35.376517
6429 22:18:35.382629 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6430 22:18:35.386115 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6431 22:18:35.389496 [Gating] SW calibration Done
6432 22:18:35.389622 ==
6433 22:18:35.392602 Dram Type= 6, Freq= 0, CH_0, rank 1
6434 22:18:35.396316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6435 22:18:35.396389 ==
6436 22:18:35.396466 RX Vref Scan: 0
6437 22:18:35.396527
6438 22:18:35.399611 RX Vref 0 -> 0, step: 1
6439 22:18:35.399691
6440 22:18:35.402957 RX Delay -410 -> 252, step: 16
6441 22:18:35.405966 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6442 22:18:35.412499 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6443 22:18:35.416206 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6444 22:18:35.419255 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6445 22:18:35.422683 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6446 22:18:35.425796 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6447 22:18:35.433102 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6448 22:18:35.436247 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6449 22:18:35.439858 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6450 22:18:35.442978 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6451 22:18:35.449392 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6452 22:18:35.452560 iDelay=230, Bit 11, Center -27 (-250 ~ 197) 448
6453 22:18:35.455858 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6454 22:18:35.462281 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6455 22:18:35.465766 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6456 22:18:35.469499 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6457 22:18:35.469640 ==
6458 22:18:35.472585 Dram Type= 6, Freq= 0, CH_0, rank 1
6459 22:18:35.475698 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6460 22:18:35.475776 ==
6461 22:18:35.479217 DQS Delay:
6462 22:18:35.479317 DQS0 = 27, DQS1 = 35
6463 22:18:35.482584 DQM Delay:
6464 22:18:35.482657 DQM0 = 12, DQM1 = 12
6465 22:18:35.482733 DQ Delay:
6466 22:18:35.485749 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6467 22:18:35.489197 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6468 22:18:35.492542 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6469 22:18:35.495538 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6470 22:18:35.495619
6471 22:18:35.495708
6472 22:18:35.495786 ==
6473 22:18:35.499242 Dram Type= 6, Freq= 0, CH_0, rank 1
6474 22:18:35.505677 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6475 22:18:35.505754 ==
6476 22:18:35.505838
6477 22:18:35.505920
6478 22:18:35.505998 TX Vref Scan disable
6479 22:18:35.508828 == TX Byte 0 ==
6480 22:18:35.512271 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6481 22:18:35.515851 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6482 22:18:35.518942 == TX Byte 1 ==
6483 22:18:35.522428 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6484 22:18:35.525389 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6485 22:18:35.525474 ==
6486 22:18:35.528992 Dram Type= 6, Freq= 0, CH_0, rank 1
6487 22:18:35.535645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6488 22:18:35.535728 ==
6489 22:18:35.535794
6490 22:18:35.535855
6491 22:18:35.535913 TX Vref Scan disable
6492 22:18:35.538683 == TX Byte 0 ==
6493 22:18:35.542436 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6494 22:18:35.545836 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6495 22:18:35.548748 == TX Byte 1 ==
6496 22:18:35.552290 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6497 22:18:35.555360 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6498 22:18:35.555436
6499 22:18:35.558735 [DATLAT]
6500 22:18:35.558812 Freq=400, CH0 RK1
6501 22:18:35.558877
6502 22:18:35.562172 DATLAT Default: 0xe
6503 22:18:35.562242 0, 0xFFFF, sum = 0
6504 22:18:35.565505 1, 0xFFFF, sum = 0
6505 22:18:35.565623 2, 0xFFFF, sum = 0
6506 22:18:35.568716 3, 0xFFFF, sum = 0
6507 22:18:35.568802 4, 0xFFFF, sum = 0
6508 22:18:35.572052 5, 0xFFFF, sum = 0
6509 22:18:35.572137 6, 0xFFFF, sum = 0
6510 22:18:35.575352 7, 0xFFFF, sum = 0
6511 22:18:35.575437 8, 0xFFFF, sum = 0
6512 22:18:35.578676 9, 0xFFFF, sum = 0
6513 22:18:35.582127 10, 0xFFFF, sum = 0
6514 22:18:35.582216 11, 0xFFFF, sum = 0
6515 22:18:35.585222 12, 0xFFFF, sum = 0
6516 22:18:35.585337 13, 0x0, sum = 1
6517 22:18:35.588734 14, 0x0, sum = 2
6518 22:18:35.588819 15, 0x0, sum = 3
6519 22:18:35.591844 16, 0x0, sum = 4
6520 22:18:35.591930 best_step = 14
6521 22:18:35.591996
6522 22:18:35.592058 ==
6523 22:18:35.595228 Dram Type= 6, Freq= 0, CH_0, rank 1
6524 22:18:35.598594 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6525 22:18:35.598678 ==
6526 22:18:35.601870 RX Vref Scan: 0
6527 22:18:35.601954
6528 22:18:35.605000 RX Vref 0 -> 0, step: 1
6529 22:18:35.605083
6530 22:18:35.605149 RX Delay -311 -> 252, step: 8
6531 22:18:35.614070 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6532 22:18:35.617109 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6533 22:18:35.620571 iDelay=217, Bit 2, Center -20 (-247 ~ 208) 456
6534 22:18:35.623546 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6535 22:18:35.630094 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6536 22:18:35.633643 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6537 22:18:35.637288 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6538 22:18:35.640168 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6539 22:18:35.647010 iDelay=217, Bit 8, Center -28 (-247 ~ 192) 440
6540 22:18:35.649890 iDelay=217, Bit 9, Center -36 (-255 ~ 184) 440
6541 22:18:35.653639 iDelay=217, Bit 10, Center -24 (-239 ~ 192) 432
6542 22:18:35.656931 iDelay=217, Bit 11, Center -28 (-247 ~ 192) 440
6543 22:18:35.663398 iDelay=217, Bit 12, Center -20 (-239 ~ 200) 440
6544 22:18:35.666821 iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440
6545 22:18:35.670153 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440
6546 22:18:35.676422 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6547 22:18:35.676503 ==
6548 22:18:35.679947 Dram Type= 6, Freq= 0, CH_0, rank 1
6549 22:18:35.683234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6550 22:18:35.683320 ==
6551 22:18:35.683385 DQS Delay:
6552 22:18:35.686734 DQS0 = 24, DQS1 = 36
6553 22:18:35.686823 DQM Delay:
6554 22:18:35.689617 DQM0 = 8, DQM1 = 13
6555 22:18:35.689686 DQ Delay:
6556 22:18:35.693341 DQ0 =8, DQ1 =8, DQ2 =4, DQ3 =8
6557 22:18:35.696944 DQ4 =8, DQ5 =0, DQ6 =12, DQ7 =16
6558 22:18:35.700215 DQ8 =8, DQ9 =0, DQ10 =12, DQ11 =8
6559 22:18:35.702965 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6560 22:18:35.703042
6561 22:18:35.703106
6562 22:18:35.710040 [DQSOSCAuto] RK1, (LSB)MR18= 0xb756, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 387 ps
6563 22:18:35.713549 CH0 RK1: MR19=C0C, MR18=B756
6564 22:18:35.719665 CH0_RK1: MR19=0xC0C, MR18=0xB756, DQSOSC=387, MR23=63, INC=394, DEC=262
6565 22:18:35.723363 [RxdqsGatingPostProcess] freq 400
6566 22:18:35.726763 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6567 22:18:35.729668 best DQS0 dly(2T, 0.5T) = (0, 10)
6568 22:18:35.733230 best DQS1 dly(2T, 0.5T) = (0, 10)
6569 22:18:35.736669 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6570 22:18:35.739690 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6571 22:18:35.742797 best DQS0 dly(2T, 0.5T) = (0, 10)
6572 22:18:35.746340 best DQS1 dly(2T, 0.5T) = (0, 10)
6573 22:18:35.749866 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6574 22:18:35.752821 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6575 22:18:35.756556 Pre-setting of DQS Precalculation
6576 22:18:35.759399 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6577 22:18:35.763074 ==
6578 22:18:35.766578 Dram Type= 6, Freq= 0, CH_1, rank 0
6579 22:18:35.769632 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6580 22:18:35.769708 ==
6581 22:18:35.772875 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6582 22:18:35.779556 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6583 22:18:35.782705 [CA 0] Center 36 (8~64) winsize 57
6584 22:18:35.786014 [CA 1] Center 36 (8~64) winsize 57
6585 22:18:35.789436 [CA 2] Center 36 (8~64) winsize 57
6586 22:18:35.792671 [CA 3] Center 36 (8~64) winsize 57
6587 22:18:35.796081 [CA 4] Center 36 (8~64) winsize 57
6588 22:18:35.799352 [CA 5] Center 36 (8~64) winsize 57
6589 22:18:35.799440
6590 22:18:35.802532 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6591 22:18:35.802611
6592 22:18:35.805754 [CATrainingPosCal] consider 1 rank data
6593 22:18:35.809737 u2DelayCellTimex100 = 270/100 ps
6594 22:18:35.812675 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6595 22:18:35.816268 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6596 22:18:35.819261 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6597 22:18:35.822346 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6598 22:18:35.828955 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6599 22:18:35.832621 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6600 22:18:35.832703
6601 22:18:35.835752 CA PerBit enable=1, Macro0, CA PI delay=36
6602 22:18:35.835834
6603 22:18:35.839043 [CBTSetCACLKResult] CA Dly = 36
6604 22:18:35.839125 CS Dly: 1 (0~32)
6605 22:18:35.839194 ==
6606 22:18:35.842675 Dram Type= 6, Freq= 0, CH_1, rank 1
6607 22:18:35.849441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6608 22:18:35.849548 ==
6609 22:18:35.852540 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6610 22:18:35.858794 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6611 22:18:35.862491 [CA 0] Center 36 (8~64) winsize 57
6612 22:18:35.865868 [CA 1] Center 36 (8~64) winsize 57
6613 22:18:35.868917 [CA 2] Center 36 (8~64) winsize 57
6614 22:18:35.872295 [CA 3] Center 36 (8~64) winsize 57
6615 22:18:35.875177 [CA 4] Center 36 (8~64) winsize 57
6616 22:18:35.878884 [CA 5] Center 36 (8~64) winsize 57
6617 22:18:35.878970
6618 22:18:35.882353 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6619 22:18:35.882434
6620 22:18:35.885336 [CATrainingPosCal] consider 2 rank data
6621 22:18:35.888718 u2DelayCellTimex100 = 270/100 ps
6622 22:18:35.892139 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6623 22:18:35.895233 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6624 22:18:35.898691 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6625 22:18:35.902148 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6626 22:18:35.905090 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6627 22:18:35.908827 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6628 22:18:35.908909
6629 22:18:35.915001 CA PerBit enable=1, Macro0, CA PI delay=36
6630 22:18:35.915092
6631 22:18:35.918964 [CBTSetCACLKResult] CA Dly = 36
6632 22:18:35.919064 CS Dly: 1 (0~32)
6633 22:18:35.919154
6634 22:18:35.921532 ----->DramcWriteLeveling(PI) begin...
6635 22:18:35.921624 ==
6636 22:18:35.925084 Dram Type= 6, Freq= 0, CH_1, rank 0
6637 22:18:35.928696 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6638 22:18:35.931687 ==
6639 22:18:35.931800 Write leveling (Byte 0): 40 => 8
6640 22:18:35.935174 Write leveling (Byte 1): 40 => 8
6641 22:18:35.938504 DramcWriteLeveling(PI) end<-----
6642 22:18:35.938584
6643 22:18:35.938650 ==
6644 22:18:35.941711 Dram Type= 6, Freq= 0, CH_1, rank 0
6645 22:18:35.948306 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6646 22:18:35.948392 ==
6647 22:18:35.948459 [Gating] SW mode calibration
6648 22:18:35.958517 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6649 22:18:35.961923 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6650 22:18:35.964925 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6651 22:18:35.971836 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6652 22:18:35.975169 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6653 22:18:35.978393 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6654 22:18:35.984793 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6655 22:18:35.988668 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6656 22:18:35.991655 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6657 22:18:35.998248 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6658 22:18:36.001381 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6659 22:18:36.004845 Total UI for P1: 0, mck2ui 16
6660 22:18:36.008216 best dqsien dly found for B0: ( 0, 14, 24)
6661 22:18:36.011589 Total UI for P1: 0, mck2ui 16
6662 22:18:36.015199 best dqsien dly found for B1: ( 0, 14, 24)
6663 22:18:36.017988 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6664 22:18:36.021413 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6665 22:18:36.021542
6666 22:18:36.024931 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6667 22:18:36.028137 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6668 22:18:36.031592 [Gating] SW calibration Done
6669 22:18:36.031669 ==
6670 22:18:36.034636 Dram Type= 6, Freq= 0, CH_1, rank 0
6671 22:18:36.038160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6672 22:18:36.041078 ==
6673 22:18:36.041154 RX Vref Scan: 0
6674 22:18:36.041240
6675 22:18:36.044674 RX Vref 0 -> 0, step: 1
6676 22:18:36.044751
6677 22:18:36.047668 RX Delay -410 -> 252, step: 16
6678 22:18:36.051292 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6679 22:18:36.054459 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6680 22:18:36.058319 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6681 22:18:36.064659 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6682 22:18:36.068114 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6683 22:18:36.071394 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6684 22:18:36.074977 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6685 22:18:36.081492 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6686 22:18:36.084723 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6687 22:18:36.088030 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6688 22:18:36.091145 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6689 22:18:36.098051 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6690 22:18:36.101407 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6691 22:18:36.104719 iDelay=230, Bit 13, Center -11 (-234 ~ 213) 448
6692 22:18:36.107813 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6693 22:18:36.114787 iDelay=230, Bit 15, Center -3 (-234 ~ 229) 464
6694 22:18:36.114869 ==
6695 22:18:36.118323 Dram Type= 6, Freq= 0, CH_1, rank 0
6696 22:18:36.121191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6697 22:18:36.121267 ==
6698 22:18:36.121355 DQS Delay:
6699 22:18:36.124499 DQS0 = 27, DQS1 = 35
6700 22:18:36.124583 DQM Delay:
6701 22:18:36.127639 DQM0 = 10, DQM1 = 15
6702 22:18:36.127718 DQ Delay:
6703 22:18:36.131159 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =8
6704 22:18:36.134685 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6705 22:18:36.137520 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6706 22:18:36.141103 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =32
6707 22:18:36.141189
6708 22:18:36.141273
6709 22:18:36.141350 ==
6710 22:18:36.144743 Dram Type= 6, Freq= 0, CH_1, rank 0
6711 22:18:36.147805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6712 22:18:36.147884 ==
6713 22:18:36.147971
6714 22:18:36.148051
6715 22:18:36.151249 TX Vref Scan disable
6716 22:18:36.154393 == TX Byte 0 ==
6717 22:18:36.157569 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6718 22:18:36.160976 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6719 22:18:36.161061 == TX Byte 1 ==
6720 22:18:36.167682 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6721 22:18:36.171167 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6722 22:18:36.171254 ==
6723 22:18:36.174092 Dram Type= 6, Freq= 0, CH_1, rank 0
6724 22:18:36.177647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6725 22:18:36.177727 ==
6726 22:18:36.177815
6727 22:18:36.180976
6728 22:18:36.181056 TX Vref Scan disable
6729 22:18:36.184255 == TX Byte 0 ==
6730 22:18:36.187644 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6731 22:18:36.191421 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6732 22:18:36.191500 == TX Byte 1 ==
6733 22:18:36.197660 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6734 22:18:36.201203 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6735 22:18:36.201283
6736 22:18:36.201373 [DATLAT]
6737 22:18:36.204851 Freq=400, CH1 RK0
6738 22:18:36.204931
6739 22:18:36.205019 DATLAT Default: 0xf
6740 22:18:36.208208 0, 0xFFFF, sum = 0
6741 22:18:36.208289 1, 0xFFFF, sum = 0
6742 22:18:36.211268 2, 0xFFFF, sum = 0
6743 22:18:36.211348 3, 0xFFFF, sum = 0
6744 22:18:36.214740 4, 0xFFFF, sum = 0
6745 22:18:36.214818 5, 0xFFFF, sum = 0
6746 22:18:36.217633 6, 0xFFFF, sum = 0
6747 22:18:36.221179 7, 0xFFFF, sum = 0
6748 22:18:36.221261 8, 0xFFFF, sum = 0
6749 22:18:36.224479 9, 0xFFFF, sum = 0
6750 22:18:36.224560 10, 0xFFFF, sum = 0
6751 22:18:36.227928 11, 0xFFFF, sum = 0
6752 22:18:36.228009 12, 0xFFFF, sum = 0
6753 22:18:36.230856 13, 0x0, sum = 1
6754 22:18:36.230937 14, 0x0, sum = 2
6755 22:18:36.234481 15, 0x0, sum = 3
6756 22:18:36.234561 16, 0x0, sum = 4
6757 22:18:36.234651 best_step = 14
6758 22:18:36.237928
6759 22:18:36.238006 ==
6760 22:18:36.240840 Dram Type= 6, Freq= 0, CH_1, rank 0
6761 22:18:36.244056 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6762 22:18:36.244136 ==
6763 22:18:36.244221 RX Vref Scan: 1
6764 22:18:36.244307
6765 22:18:36.247736 RX Vref 0 -> 0, step: 1
6766 22:18:36.247815
6767 22:18:36.250748 RX Delay -311 -> 252, step: 8
6768 22:18:36.250827
6769 22:18:36.254368 Set Vref, RX VrefLevel [Byte0]: 56
6770 22:18:36.257238 [Byte1]: 52
6771 22:18:36.261634
6772 22:18:36.261709 Final RX Vref Byte 0 = 56 to rank0
6773 22:18:36.264455 Final RX Vref Byte 1 = 52 to rank0
6774 22:18:36.268202 Final RX Vref Byte 0 = 56 to rank1
6775 22:18:36.271250 Final RX Vref Byte 1 = 52 to rank1==
6776 22:18:36.274509 Dram Type= 6, Freq= 0, CH_1, rank 0
6777 22:18:36.281232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6778 22:18:36.281315 ==
6779 22:18:36.281420 DQS Delay:
6780 22:18:36.284297 DQS0 = 28, DQS1 = 32
6781 22:18:36.284373 DQM Delay:
6782 22:18:36.284455 DQM0 = 9, DQM1 = 10
6783 22:18:36.288335 DQ Delay:
6784 22:18:36.290789 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
6785 22:18:36.290877 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =8
6786 22:18:36.294333 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
6787 22:18:36.297463 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =20
6788 22:18:36.297579
6789 22:18:36.297645
6790 22:18:36.307677 [DQSOSCAuto] RK0, (LSB)MR18= 0x8dc6, (MSB)MR19= 0xc0c, tDQSOscB0 = 385 ps tDQSOscB1 = 392 ps
6791 22:18:36.311115 CH1 RK0: MR19=C0C, MR18=8DC6
6792 22:18:36.317648 CH1_RK0: MR19=0xC0C, MR18=0x8DC6, DQSOSC=385, MR23=63, INC=398, DEC=265
6793 22:18:36.317763 ==
6794 22:18:36.321302 Dram Type= 6, Freq= 0, CH_1, rank 1
6795 22:18:36.324707 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6796 22:18:36.324810 ==
6797 22:18:36.327769 [Gating] SW mode calibration
6798 22:18:36.334162 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6799 22:18:36.337577 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6800 22:18:36.344297 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6801 22:18:36.347621 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6802 22:18:36.350867 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6803 22:18:36.357820 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6804 22:18:36.361217 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6805 22:18:36.364294 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6806 22:18:36.370876 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6807 22:18:36.374502 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6808 22:18:36.377481 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6809 22:18:36.381066 Total UI for P1: 0, mck2ui 16
6810 22:18:36.384232 best dqsien dly found for B0: ( 0, 14, 24)
6811 22:18:36.387879 Total UI for P1: 0, mck2ui 16
6812 22:18:36.390705 best dqsien dly found for B1: ( 0, 14, 24)
6813 22:18:36.393815 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6814 22:18:36.397340 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6815 22:18:36.397439
6816 22:18:36.404313 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6817 22:18:36.407415 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6818 22:18:36.410780 [Gating] SW calibration Done
6819 22:18:36.410855 ==
6820 22:18:36.414043 Dram Type= 6, Freq= 0, CH_1, rank 1
6821 22:18:36.417483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6822 22:18:36.417620 ==
6823 22:18:36.417711 RX Vref Scan: 0
6824 22:18:36.417799
6825 22:18:36.420636 RX Vref 0 -> 0, step: 1
6826 22:18:36.420736
6827 22:18:36.424173 RX Delay -410 -> 252, step: 16
6828 22:18:36.427256 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6829 22:18:36.433884 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6830 22:18:36.437297 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6831 22:18:36.440598 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6832 22:18:36.443840 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6833 22:18:36.450707 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6834 22:18:36.453700 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6835 22:18:36.457460 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6836 22:18:36.460413 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6837 22:18:36.463879 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6838 22:18:36.470336 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6839 22:18:36.473876 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6840 22:18:36.476920 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6841 22:18:36.484223 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6842 22:18:36.487305 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6843 22:18:36.490264 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6844 22:18:36.490340 ==
6845 22:18:36.493997 Dram Type= 6, Freq= 0, CH_1, rank 1
6846 22:18:36.496909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6847 22:18:36.497006 ==
6848 22:18:36.500673 DQS Delay:
6849 22:18:36.500770 DQS0 = 35, DQS1 = 35
6850 22:18:36.503782 DQM Delay:
6851 22:18:36.503856 DQM0 = 18, DQM1 = 13
6852 22:18:36.507300 DQ Delay:
6853 22:18:36.507371 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6854 22:18:36.510664 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6855 22:18:36.513555 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6856 22:18:36.516939 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6857 22:18:36.517044
6858 22:18:36.517137
6859 22:18:36.520282 ==
6860 22:18:36.520380 Dram Type= 6, Freq= 0, CH_1, rank 1
6861 22:18:36.526866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6862 22:18:36.526944 ==
6863 22:18:36.527008
6864 22:18:36.527069
6865 22:18:36.530315 TX Vref Scan disable
6866 22:18:36.530391 == TX Byte 0 ==
6867 22:18:36.533787 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6868 22:18:36.536997 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6869 22:18:36.540356 == TX Byte 1 ==
6870 22:18:36.543785 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6871 22:18:36.547080 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6872 22:18:36.550674 ==
6873 22:18:36.550774 Dram Type= 6, Freq= 0, CH_1, rank 1
6874 22:18:36.556731 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6875 22:18:36.556808 ==
6876 22:18:36.556873
6877 22:18:36.556933
6878 22:18:36.560105 TX Vref Scan disable
6879 22:18:36.560202 == TX Byte 0 ==
6880 22:18:36.564113 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6881 22:18:36.570219 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6882 22:18:36.570298 == TX Byte 1 ==
6883 22:18:36.573649 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6884 22:18:36.577138 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6885 22:18:36.580193
6886 22:18:36.580289 [DATLAT]
6887 22:18:36.580382 Freq=400, CH1 RK1
6888 22:18:36.580471
6889 22:18:36.583716 DATLAT Default: 0xe
6890 22:18:36.583814 0, 0xFFFF, sum = 0
6891 22:18:36.586707 1, 0xFFFF, sum = 0
6892 22:18:36.586805 2, 0xFFFF, sum = 0
6893 22:18:36.590365 3, 0xFFFF, sum = 0
6894 22:18:36.590444 4, 0xFFFF, sum = 0
6895 22:18:36.593752 5, 0xFFFF, sum = 0
6896 22:18:36.596788 6, 0xFFFF, sum = 0
6897 22:18:36.596892 7, 0xFFFF, sum = 0
6898 22:18:36.600448 8, 0xFFFF, sum = 0
6899 22:18:36.600520 9, 0xFFFF, sum = 0
6900 22:18:36.603439 10, 0xFFFF, sum = 0
6901 22:18:36.603510 11, 0xFFFF, sum = 0
6902 22:18:36.606899 12, 0xFFFF, sum = 0
6903 22:18:36.606970 13, 0x0, sum = 1
6904 22:18:36.609896 14, 0x0, sum = 2
6905 22:18:36.609970 15, 0x0, sum = 3
6906 22:18:36.613443 16, 0x0, sum = 4
6907 22:18:36.613581 best_step = 14
6908 22:18:36.613671
6909 22:18:36.613759 ==
6910 22:18:36.616463 Dram Type= 6, Freq= 0, CH_1, rank 1
6911 22:18:36.620387 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6912 22:18:36.620484 ==
6913 22:18:36.623573 RX Vref Scan: 0
6914 22:18:36.623672
6915 22:18:36.626470 RX Vref 0 -> 0, step: 1
6916 22:18:36.626567
6917 22:18:36.626659 RX Delay -311 -> 252, step: 8
6918 22:18:36.635284 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6919 22:18:36.638774 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
6920 22:18:36.641927 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6921 22:18:36.645967 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6922 22:18:36.651915 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6923 22:18:36.655460 iDelay=217, Bit 5, Center -4 (-223 ~ 216) 440
6924 22:18:36.658941 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6925 22:18:36.661842 iDelay=217, Bit 7, Center -16 (-239 ~ 208) 448
6926 22:18:36.668638 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6927 22:18:36.672052 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6928 22:18:36.675293 iDelay=217, Bit 10, Center -20 (-247 ~ 208) 456
6929 22:18:36.678632 iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456
6930 22:18:36.685165 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
6931 22:18:36.688970 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6932 22:18:36.692041 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6933 22:18:36.695189 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
6934 22:18:36.698610 ==
6935 22:18:36.701713 Dram Type= 6, Freq= 0, CH_1, rank 1
6936 22:18:36.705310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6937 22:18:36.705409 ==
6938 22:18:36.705499 DQS Delay:
6939 22:18:36.708352 DQS0 = 28, DQS1 = 32
6940 22:18:36.708448 DQM Delay:
6941 22:18:36.712161 DQM0 = 11, DQM1 = 11
6942 22:18:36.712255 DQ Delay:
6943 22:18:36.715114 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8
6944 22:18:36.718422 DQ4 =8, DQ5 =24, DQ6 =20, DQ7 =12
6945 22:18:36.721954 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6946 22:18:36.725126 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
6947 22:18:36.725226
6948 22:18:36.725317
6949 22:18:36.731564 [DQSOSCAuto] RK1, (LSB)MR18= 0xc456, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 385 ps
6950 22:18:36.734836 CH1 RK1: MR19=C0C, MR18=C456
6951 22:18:36.741483 CH1_RK1: MR19=0xC0C, MR18=0xC456, DQSOSC=385, MR23=63, INC=398, DEC=265
6952 22:18:36.744934 [RxdqsGatingPostProcess] freq 400
6953 22:18:36.748119 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6954 22:18:36.751585 best DQS0 dly(2T, 0.5T) = (0, 10)
6955 22:18:36.755167 best DQS1 dly(2T, 0.5T) = (0, 10)
6956 22:18:36.758067 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6957 22:18:36.761662 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6958 22:18:36.765159 best DQS0 dly(2T, 0.5T) = (0, 10)
6959 22:18:36.768435 best DQS1 dly(2T, 0.5T) = (0, 10)
6960 22:18:36.771702 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6961 22:18:36.774592 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6962 22:18:36.777962 Pre-setting of DQS Precalculation
6963 22:18:36.781177 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6964 22:18:36.791182 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6965 22:18:36.797965 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6966 22:18:36.798067
6967 22:18:36.798158
6968 22:18:36.801807 [Calibration Summary] 800 Mbps
6969 22:18:36.801885 CH 0, Rank 0
6970 22:18:36.804877 SW Impedance : PASS
6971 22:18:36.804947 DUTY Scan : NO K
6972 22:18:36.807832 ZQ Calibration : PASS
6973 22:18:36.811249 Jitter Meter : NO K
6974 22:18:36.811345 CBT Training : PASS
6975 22:18:36.815131 Write leveling : PASS
6976 22:18:36.818236 RX DQS gating : PASS
6977 22:18:36.818307 RX DQ/DQS(RDDQC) : PASS
6978 22:18:36.821337 TX DQ/DQS : PASS
6979 22:18:36.825001 RX DATLAT : PASS
6980 22:18:36.825073 RX DQ/DQS(Engine): PASS
6981 22:18:36.827784 TX OE : NO K
6982 22:18:36.827883 All Pass.
6983 22:18:36.827974
6984 22:18:36.831421 CH 0, Rank 1
6985 22:18:36.831518 SW Impedance : PASS
6986 22:18:36.834903 DUTY Scan : NO K
6987 22:18:36.837940 ZQ Calibration : PASS
6988 22:18:36.838037 Jitter Meter : NO K
6989 22:18:36.841477 CBT Training : PASS
6990 22:18:36.841596 Write leveling : NO K
6991 22:18:36.844509 RX DQS gating : PASS
6992 22:18:36.847924 RX DQ/DQS(RDDQC) : PASS
6993 22:18:36.848023 TX DQ/DQS : PASS
6994 22:18:36.851205 RX DATLAT : PASS
6995 22:18:36.854342 RX DQ/DQS(Engine): PASS
6996 22:18:36.854441 TX OE : NO K
6997 22:18:36.857838 All Pass.
6998 22:18:36.857938
6999 22:18:36.858025 CH 1, Rank 0
7000 22:18:36.861283 SW Impedance : PASS
7001 22:18:36.861353 DUTY Scan : NO K
7002 22:18:36.864104 ZQ Calibration : PASS
7003 22:18:36.867604 Jitter Meter : NO K
7004 22:18:36.867704 CBT Training : PASS
7005 22:18:36.871102 Write leveling : PASS
7006 22:18:36.874432 RX DQS gating : PASS
7007 22:18:36.874533 RX DQ/DQS(RDDQC) : PASS
7008 22:18:36.877652 TX DQ/DQS : PASS
7009 22:18:36.881213 RX DATLAT : PASS
7010 22:18:36.881310 RX DQ/DQS(Engine): PASS
7011 22:18:36.884382 TX OE : NO K
7012 22:18:36.884459 All Pass.
7013 22:18:36.884523
7014 22:18:36.887904 CH 1, Rank 1
7015 22:18:36.887978 SW Impedance : PASS
7016 22:18:36.890785 DUTY Scan : NO K
7017 22:18:36.894456 ZQ Calibration : PASS
7018 22:18:36.894530 Jitter Meter : NO K
7019 22:18:36.897816 CBT Training : PASS
7020 22:18:36.897887 Write leveling : NO K
7021 22:18:36.900725 RX DQS gating : PASS
7022 22:18:36.904305 RX DQ/DQS(RDDQC) : PASS
7023 22:18:36.904376 TX DQ/DQS : PASS
7024 22:18:36.907501 RX DATLAT : PASS
7025 22:18:36.911051 RX DQ/DQS(Engine): PASS
7026 22:18:36.911123 TX OE : NO K
7027 22:18:36.914071 All Pass.
7028 22:18:36.914142
7029 22:18:36.914207 DramC Write-DBI off
7030 22:18:36.917714 PER_BANK_REFRESH: Hybrid Mode
7031 22:18:36.920877 TX_TRACKING: ON
7032 22:18:36.927498 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7033 22:18:36.930493 [FAST_K] Save calibration result to emmc
7034 22:18:36.933926 dramc_set_vcore_voltage set vcore to 725000
7035 22:18:36.937605 Read voltage for 1600, 0
7036 22:18:36.937682 Vio18 = 0
7037 22:18:36.940622 Vcore = 725000
7038 22:18:36.940696 Vdram = 0
7039 22:18:36.940757 Vddq = 0
7040 22:18:36.944258 Vmddr = 0
7041 22:18:36.947195 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7042 22:18:36.954151 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7043 22:18:36.954234 MEM_TYPE=3, freq_sel=13
7044 22:18:36.957519 sv_algorithm_assistance_LP4_3733
7045 22:18:36.963832 ============ PULL DRAM RESETB DOWN ============
7046 22:18:36.967426 ========== PULL DRAM RESETB DOWN end =========
7047 22:18:36.970597 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7048 22:18:36.973952 ===================================
7049 22:18:36.977204 LPDDR4 DRAM CONFIGURATION
7050 22:18:36.981032 ===================================
7051 22:18:36.983813 EX_ROW_EN[0] = 0x0
7052 22:18:36.983895 EX_ROW_EN[1] = 0x0
7053 22:18:36.987074 LP4Y_EN = 0x0
7054 22:18:36.987155 WORK_FSP = 0x1
7055 22:18:36.990914 WL = 0x5
7056 22:18:36.990996 RL = 0x5
7057 22:18:36.994360 BL = 0x2
7058 22:18:36.994485 RPST = 0x0
7059 22:18:36.997202 RD_PRE = 0x0
7060 22:18:36.997312 WR_PRE = 0x1
7061 22:18:37.000636 WR_PST = 0x1
7062 22:18:37.000707 DBI_WR = 0x0
7063 22:18:37.003798 DBI_RD = 0x0
7064 22:18:37.003870 OTF = 0x1
7065 22:18:37.007273 ===================================
7066 22:18:37.010420 ===================================
7067 22:18:37.014276 ANA top config
7068 22:18:37.017204 ===================================
7069 22:18:37.017276 DLL_ASYNC_EN = 0
7070 22:18:37.020743 ALL_SLAVE_EN = 0
7071 22:18:37.023830 NEW_RANK_MODE = 1
7072 22:18:37.027136 DLL_IDLE_MODE = 1
7073 22:18:37.030549 LP45_APHY_COMB_EN = 1
7074 22:18:37.030618 TX_ODT_DIS = 0
7075 22:18:37.033972 NEW_8X_MODE = 1
7076 22:18:37.037157 ===================================
7077 22:18:37.040730 ===================================
7078 22:18:37.043733 data_rate = 3200
7079 22:18:37.047451 CKR = 1
7080 22:18:37.050464 DQ_P2S_RATIO = 8
7081 22:18:37.054069 ===================================
7082 22:18:37.054139 CA_P2S_RATIO = 8
7083 22:18:37.057079 DQ_CA_OPEN = 0
7084 22:18:37.060388 DQ_SEMI_OPEN = 0
7085 22:18:37.063838 CA_SEMI_OPEN = 0
7086 22:18:37.067106 CA_FULL_RATE = 0
7087 22:18:37.070615 DQ_CKDIV4_EN = 0
7088 22:18:37.070716 CA_CKDIV4_EN = 0
7089 22:18:37.073859 CA_PREDIV_EN = 0
7090 22:18:37.077640 PH8_DLY = 12
7091 22:18:37.080818 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7092 22:18:37.083647 DQ_AAMCK_DIV = 4
7093 22:18:37.086941 CA_AAMCK_DIV = 4
7094 22:18:37.087048 CA_ADMCK_DIV = 4
7095 22:18:37.090493 DQ_TRACK_CA_EN = 0
7096 22:18:37.093835 CA_PICK = 1600
7097 22:18:37.097195 CA_MCKIO = 1600
7098 22:18:37.100629 MCKIO_SEMI = 0
7099 22:18:37.103895 PLL_FREQ = 3068
7100 22:18:37.107404 DQ_UI_PI_RATIO = 32
7101 22:18:37.107487 CA_UI_PI_RATIO = 0
7102 22:18:37.110720 ===================================
7103 22:18:37.113548 ===================================
7104 22:18:37.116991 memory_type:LPDDR4
7105 22:18:37.120877 GP_NUM : 10
7106 22:18:37.120973 SRAM_EN : 1
7107 22:18:37.123943 MD32_EN : 0
7108 22:18:37.127193 ===================================
7109 22:18:37.130189 [ANA_INIT] >>>>>>>>>>>>>>
7110 22:18:37.134236 <<<<<< [CONFIGURE PHASE]: ANA_TX
7111 22:18:37.137016 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7112 22:18:37.140647 ===================================
7113 22:18:37.140742 data_rate = 3200,PCW = 0X7600
7114 22:18:37.143762 ===================================
7115 22:18:37.146869 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7116 22:18:37.153940 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7117 22:18:37.160395 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7118 22:18:37.163855 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7119 22:18:37.166867 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7120 22:18:37.170430 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7121 22:18:37.173569 [ANA_INIT] flow start
7122 22:18:37.177383 [ANA_INIT] PLL >>>>>>>>
7123 22:18:37.177484 [ANA_INIT] PLL <<<<<<<<
7124 22:18:37.180175 [ANA_INIT] MIDPI >>>>>>>>
7125 22:18:37.183347 [ANA_INIT] MIDPI <<<<<<<<
7126 22:18:37.183423 [ANA_INIT] DLL >>>>>>>>
7127 22:18:37.186892 [ANA_INIT] DLL <<<<<<<<
7128 22:18:37.190493 [ANA_INIT] flow end
7129 22:18:37.193112 ============ LP4 DIFF to SE enter ============
7130 22:18:37.196529 ============ LP4 DIFF to SE exit ============
7131 22:18:37.199808 [ANA_INIT] <<<<<<<<<<<<<
7132 22:18:37.203333 [Flow] Enable top DCM control >>>>>
7133 22:18:37.206575 [Flow] Enable top DCM control <<<<<
7134 22:18:37.209997 Enable DLL master slave shuffle
7135 22:18:37.213305 ==============================================================
7136 22:18:37.216651 Gating Mode config
7137 22:18:37.223576 ==============================================================
7138 22:18:37.223679 Config description:
7139 22:18:37.233488 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7140 22:18:37.240411 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7141 22:18:37.243245 SELPH_MODE 0: By rank 1: By Phase
7142 22:18:37.250164 ==============================================================
7143 22:18:37.253352 GAT_TRACK_EN = 1
7144 22:18:37.256783 RX_GATING_MODE = 2
7145 22:18:37.259902 RX_GATING_TRACK_MODE = 2
7146 22:18:37.263458 SELPH_MODE = 1
7147 22:18:37.267014 PICG_EARLY_EN = 1
7148 22:18:37.270172 VALID_LAT_VALUE = 1
7149 22:18:37.272995 ==============================================================
7150 22:18:37.276472 Enter into Gating configuration >>>>
7151 22:18:37.280203 Exit from Gating configuration <<<<
7152 22:18:37.283287 Enter into DVFS_PRE_config >>>>>
7153 22:18:37.293352 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7154 22:18:37.296164 Exit from DVFS_PRE_config <<<<<
7155 22:18:37.300023 Enter into PICG configuration >>>>
7156 22:18:37.303344 Exit from PICG configuration <<<<
7157 22:18:37.306341 [RX_INPUT] configuration >>>>>
7158 22:18:37.309603 [RX_INPUT] configuration <<<<<
7159 22:18:37.316443 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7160 22:18:37.319688 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7161 22:18:37.326151 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7162 22:18:37.333123 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7163 22:18:37.339918 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7164 22:18:37.346461 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7165 22:18:37.349463 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7166 22:18:37.352876 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7167 22:18:37.356135 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7168 22:18:37.363232 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7169 22:18:37.366319 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7170 22:18:37.369383 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7171 22:18:37.372834 ===================================
7172 22:18:37.376521 LPDDR4 DRAM CONFIGURATION
7173 22:18:37.379310 ===================================
7174 22:18:37.379421 EX_ROW_EN[0] = 0x0
7175 22:18:37.382899 EX_ROW_EN[1] = 0x0
7176 22:18:37.385878 LP4Y_EN = 0x0
7177 22:18:37.385961 WORK_FSP = 0x1
7178 22:18:37.389346 WL = 0x5
7179 22:18:37.389429 RL = 0x5
7180 22:18:37.392528 BL = 0x2
7181 22:18:37.392611 RPST = 0x0
7182 22:18:37.395907 RD_PRE = 0x0
7183 22:18:37.396021 WR_PRE = 0x1
7184 22:18:37.399558 WR_PST = 0x1
7185 22:18:37.399669 DBI_WR = 0x0
7186 22:18:37.402695 DBI_RD = 0x0
7187 22:18:37.402779 OTF = 0x1
7188 22:18:37.405882 ===================================
7189 22:18:37.409263 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7190 22:18:37.415879 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7191 22:18:37.419190 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7192 22:18:37.422682 ===================================
7193 22:18:37.426185 LPDDR4 DRAM CONFIGURATION
7194 22:18:37.429017 ===================================
7195 22:18:37.429101 EX_ROW_EN[0] = 0x10
7196 22:18:37.432558 EX_ROW_EN[1] = 0x0
7197 22:18:37.432641 LP4Y_EN = 0x0
7198 22:18:37.435953 WORK_FSP = 0x1
7199 22:18:37.439208 WL = 0x5
7200 22:18:37.439291 RL = 0x5
7201 22:18:37.442501 BL = 0x2
7202 22:18:37.442584 RPST = 0x0
7203 22:18:37.446173 RD_PRE = 0x0
7204 22:18:37.446255 WR_PRE = 0x1
7205 22:18:37.449299 WR_PST = 0x1
7206 22:18:37.449381 DBI_WR = 0x0
7207 22:18:37.452929 DBI_RD = 0x0
7208 22:18:37.453012 OTF = 0x1
7209 22:18:37.455838 ===================================
7210 22:18:37.462683 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7211 22:18:37.462766 ==
7212 22:18:37.466116 Dram Type= 6, Freq= 0, CH_0, rank 0
7213 22:18:37.469291 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7214 22:18:37.469375 ==
7215 22:18:37.472251 [Duty_Offset_Calibration]
7216 22:18:37.475766 B0:2 B1:1 CA:1
7217 22:18:37.475848
7218 22:18:37.479457 [DutyScan_Calibration_Flow] k_type=0
7219 22:18:37.487577
7220 22:18:37.487660 ==CLK 0==
7221 22:18:37.490521 Final CLK duty delay cell = 0
7222 22:18:37.494043 [0] MAX Duty = 5156%(X100), DQS PI = 22
7223 22:18:37.497413 [0] MIN Duty = 4875%(X100), DQS PI = 0
7224 22:18:37.497497 [0] AVG Duty = 5015%(X100)
7225 22:18:37.500721
7226 22:18:37.500804 CH0 CLK Duty spec in!! Max-Min= 281%
7227 22:18:37.507472 [DutyScan_Calibration_Flow] ====Done====
7228 22:18:37.507582
7229 22:18:37.510671 [DutyScan_Calibration_Flow] k_type=1
7230 22:18:37.526630
7231 22:18:37.526713 ==DQS 0 ==
7232 22:18:37.529498 Final DQS duty delay cell = -4
7233 22:18:37.533348 [-4] MAX Duty = 5125%(X100), DQS PI = 24
7234 22:18:37.536140 [-4] MIN Duty = 4657%(X100), DQS PI = 0
7235 22:18:37.539850 [-4] AVG Duty = 4891%(X100)
7236 22:18:37.539933
7237 22:18:37.540000 ==DQS 1 ==
7238 22:18:37.542960 Final DQS duty delay cell = 0
7239 22:18:37.546193 [0] MAX Duty = 5187%(X100), DQS PI = 4
7240 22:18:37.550145 [0] MIN Duty = 5062%(X100), DQS PI = 32
7241 22:18:37.552857 [0] AVG Duty = 5124%(X100)
7242 22:18:37.552940
7243 22:18:37.556525 CH0 DQS 0 Duty spec in!! Max-Min= 468%
7244 22:18:37.556608
7245 22:18:37.559629 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7246 22:18:37.563323 [DutyScan_Calibration_Flow] ====Done====
7247 22:18:37.563407
7248 22:18:37.566325 [DutyScan_Calibration_Flow] k_type=3
7249 22:18:37.582949
7250 22:18:37.583032 ==DQM 0 ==
7251 22:18:37.586748 Final DQM duty delay cell = 0
7252 22:18:37.589422 [0] MAX Duty = 5218%(X100), DQS PI = 34
7253 22:18:37.593215 [0] MIN Duty = 4875%(X100), DQS PI = 60
7254 22:18:37.596128 [0] AVG Duty = 5046%(X100)
7255 22:18:37.596210
7256 22:18:37.596275 ==DQM 1 ==
7257 22:18:37.599696 Final DQM duty delay cell = -4
7258 22:18:37.602896 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7259 22:18:37.606336 [-4] MIN Duty = 4844%(X100), DQS PI = 12
7260 22:18:37.609864 [-4] AVG Duty = 4922%(X100)
7261 22:18:37.609947
7262 22:18:37.613203 CH0 DQM 0 Duty spec in!! Max-Min= 343%
7263 22:18:37.613287
7264 22:18:37.616113 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7265 22:18:37.619550 [DutyScan_Calibration_Flow] ====Done====
7266 22:18:37.619633
7267 22:18:37.622649 [DutyScan_Calibration_Flow] k_type=2
7268 22:18:37.640420
7269 22:18:37.640513 ==DQ 0 ==
7270 22:18:37.644122 Final DQ duty delay cell = 0
7271 22:18:37.647594 [0] MAX Duty = 5062%(X100), DQS PI = 26
7272 22:18:37.650455 [0] MIN Duty = 4907%(X100), DQS PI = 0
7273 22:18:37.650533 [0] AVG Duty = 4984%(X100)
7274 22:18:37.650597
7275 22:18:37.653909 ==DQ 1 ==
7276 22:18:37.657652 Final DQ duty delay cell = 0
7277 22:18:37.660498 [0] MAX Duty = 5156%(X100), DQS PI = 22
7278 22:18:37.664336 [0] MIN Duty = 4938%(X100), DQS PI = 34
7279 22:18:37.664447 [0] AVG Duty = 5047%(X100)
7280 22:18:37.664546
7281 22:18:37.667271 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7282 22:18:37.670734
7283 22:18:37.674226 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7284 22:18:37.677231 [DutyScan_Calibration_Flow] ====Done====
7285 22:18:37.677340 ==
7286 22:18:37.680316 Dram Type= 6, Freq= 0, CH_1, rank 0
7287 22:18:37.683550 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7288 22:18:37.683634 ==
7289 22:18:37.687242 [Duty_Offset_Calibration]
7290 22:18:37.687326 B0:1 B1:0 CA:0
7291 22:18:37.687392
7292 22:18:37.690567 [DutyScan_Calibration_Flow] k_type=0
7293 22:18:37.700106
7294 22:18:37.700187 ==CLK 0==
7295 22:18:37.703193 Final CLK duty delay cell = -4
7296 22:18:37.706642 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7297 22:18:37.709847 [-4] MIN Duty = 4844%(X100), DQS PI = 50
7298 22:18:37.713582 [-4] AVG Duty = 4922%(X100)
7299 22:18:37.713663
7300 22:18:37.716389 CH1 CLK Duty spec in!! Max-Min= 156%
7301 22:18:37.720119 [DutyScan_Calibration_Flow] ====Done====
7302 22:18:37.720200
7303 22:18:37.722909 [DutyScan_Calibration_Flow] k_type=1
7304 22:18:37.739280
7305 22:18:37.739362 ==DQS 0 ==
7306 22:18:37.742810 Final DQS duty delay cell = 0
7307 22:18:37.746082 [0] MAX Duty = 5094%(X100), DQS PI = 24
7308 22:18:37.749051 [0] MIN Duty = 4844%(X100), DQS PI = 44
7309 22:18:37.752883 [0] AVG Duty = 4969%(X100)
7310 22:18:37.752964
7311 22:18:37.753045 ==DQS 1 ==
7312 22:18:37.755857 Final DQS duty delay cell = -4
7313 22:18:37.759093 [-4] MAX Duty = 4969%(X100), DQS PI = 18
7314 22:18:37.762433 [-4] MIN Duty = 4750%(X100), DQS PI = 8
7315 22:18:37.766010 [-4] AVG Duty = 4859%(X100)
7316 22:18:37.766092
7317 22:18:37.769139 CH1 DQS 0 Duty spec in!! Max-Min= 250%
7318 22:18:37.769222
7319 22:18:37.772371 CH1 DQS 1 Duty spec in!! Max-Min= 219%
7320 22:18:37.775743 [DutyScan_Calibration_Flow] ====Done====
7321 22:18:37.775825
7322 22:18:37.779444 [DutyScan_Calibration_Flow] k_type=3
7323 22:18:37.796885
7324 22:18:37.796968 ==DQM 0 ==
7325 22:18:37.799824 Final DQM duty delay cell = 0
7326 22:18:37.802943 [0] MAX Duty = 5218%(X100), DQS PI = 20
7327 22:18:37.806322 [0] MIN Duty = 5000%(X100), DQS PI = 48
7328 22:18:37.809979 [0] AVG Duty = 5109%(X100)
7329 22:18:37.810062
7330 22:18:37.810128 ==DQM 1 ==
7331 22:18:37.812933 Final DQM duty delay cell = 0
7332 22:18:37.816674 [0] MAX Duty = 5093%(X100), DQS PI = 18
7333 22:18:37.819462 [0] MIN Duty = 4907%(X100), DQS PI = 50
7334 22:18:37.822767 [0] AVG Duty = 5000%(X100)
7335 22:18:37.822850
7336 22:18:37.826453 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7337 22:18:37.826537
7338 22:18:37.829385 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7339 22:18:37.832919 [DutyScan_Calibration_Flow] ====Done====
7340 22:18:37.833002
7341 22:18:37.836575 [DutyScan_Calibration_Flow] k_type=2
7342 22:18:37.852571
7343 22:18:37.852654 ==DQ 0 ==
7344 22:18:37.856376 Final DQ duty delay cell = -4
7345 22:18:37.859277 [-4] MAX Duty = 5062%(X100), DQS PI = 12
7346 22:18:37.862784 [-4] MIN Duty = 4875%(X100), DQS PI = 46
7347 22:18:37.865516 [-4] AVG Duty = 4968%(X100)
7348 22:18:37.865615
7349 22:18:37.865681 ==DQ 1 ==
7350 22:18:37.868989 Final DQ duty delay cell = 0
7351 22:18:37.872665 [0] MAX Duty = 5124%(X100), DQS PI = 16
7352 22:18:37.876169 [0] MIN Duty = 4969%(X100), DQS PI = 8
7353 22:18:37.879280 [0] AVG Duty = 5046%(X100)
7354 22:18:37.879363
7355 22:18:37.882736 CH1 DQ 0 Duty spec in!! Max-Min= 187%
7356 22:18:37.882820
7357 22:18:37.885850 CH1 DQ 1 Duty spec in!! Max-Min= 155%
7358 22:18:37.889177 [DutyScan_Calibration_Flow] ====Done====
7359 22:18:37.892516 nWR fixed to 30
7360 22:18:37.896065 [ModeRegInit_LP4] CH0 RK0
7361 22:18:37.896148 [ModeRegInit_LP4] CH0 RK1
7362 22:18:37.899036 [ModeRegInit_LP4] CH1 RK0
7363 22:18:37.902625 [ModeRegInit_LP4] CH1 RK1
7364 22:18:37.902707 match AC timing 5
7365 22:18:37.909150 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7366 22:18:37.912769 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7367 22:18:37.915959 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7368 22:18:37.922562 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7369 22:18:37.925861 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7370 22:18:37.925944 [MiockJmeterHQA]
7371 22:18:37.926011
7372 22:18:37.929274 [DramcMiockJmeter] u1RxGatingPI = 0
7373 22:18:37.932196 0 : 4255, 4029
7374 22:18:37.932280 4 : 4252, 4027
7375 22:18:37.935885 8 : 4252, 4027
7376 22:18:37.935969 12 : 4252, 4027
7377 22:18:37.936037 16 : 4366, 4139
7378 22:18:37.939269 20 : 4252, 4027
7379 22:18:37.939353 24 : 4255, 4029
7380 22:18:37.942580 28 : 4253, 4027
7381 22:18:37.942665 32 : 4363, 4138
7382 22:18:37.945450 36 : 4363, 4138
7383 22:18:37.945577 40 : 4253, 4027
7384 22:18:37.949465 44 : 4252, 4027
7385 22:18:37.949582 48 : 4252, 4027
7386 22:18:37.949668 52 : 4252, 4027
7387 22:18:37.952171 56 : 4255, 4029
7388 22:18:37.952256 60 : 4363, 4138
7389 22:18:37.955651 64 : 4250, 4027
7390 22:18:37.955737 68 : 4250, 4027
7391 22:18:37.959187 72 : 4250, 4027
7392 22:18:37.959272 76 : 4253, 4029
7393 22:18:37.959356 80 : 4250, 4027
7394 22:18:37.962378 84 : 4361, 4138
7395 22:18:37.962463 88 : 4361, 190
7396 22:18:37.965780 92 : 4250, 0
7397 22:18:37.965865 96 : 4361, 0
7398 22:18:37.965950 100 : 4253, 0
7399 22:18:37.968632 104 : 4250, 0
7400 22:18:37.968745 108 : 4361, 0
7401 22:18:37.972539 112 : 4250, 0
7402 22:18:37.972619 116 : 4361, 0
7403 22:18:37.972689 120 : 4360, 0
7404 22:18:37.976019 124 : 4361, 0
7405 22:18:37.976094 128 : 4250, 0
7406 22:18:37.979148 132 : 4250, 0
7407 22:18:37.979224 136 : 4250, 0
7408 22:18:37.979287 140 : 4250, 0
7409 22:18:37.982259 144 : 4250, 0
7410 22:18:37.982332 148 : 4250, 0
7411 22:18:37.982394 152 : 4250, 0
7412 22:18:37.985761 156 : 4253, 0
7413 22:18:37.985834 160 : 4361, 0
7414 22:18:37.989351 164 : 4361, 0
7415 22:18:37.989436 168 : 4363, 0
7416 22:18:37.989502 172 : 4250, 0
7417 22:18:37.992315 176 : 4250, 0
7418 22:18:37.992439 180 : 4250, 0
7419 22:18:37.995687 184 : 4250, 0
7420 22:18:37.995788 188 : 4250, 0
7421 22:18:37.995879 192 : 4249, 0
7422 22:18:37.998811 196 : 4253, 0
7423 22:18:37.998894 200 : 4250, 0
7424 22:18:38.002218 204 : 4250, 1313
7425 22:18:38.002301 208 : 4250, 3980
7426 22:18:38.005701 212 : 4250, 4027
7427 22:18:38.005784 216 : 4250, 4027
7428 22:18:38.005849 220 : 4252, 4030
7429 22:18:38.008693 224 : 4250, 4026
7430 22:18:38.008775 228 : 4361, 4138
7431 22:18:38.012454 232 : 4250, 4027
7432 22:18:38.012537 236 : 4250, 4027
7433 22:18:38.015213 240 : 4361, 4138
7434 22:18:38.015297 244 : 4250, 4027
7435 22:18:38.018858 248 : 4249, 4027
7436 22:18:38.018941 252 : 4363, 4140
7437 22:18:38.021986 256 : 4250, 4027
7438 22:18:38.022069 260 : 4250, 4027
7439 22:18:38.025673 264 : 4250, 4027
7440 22:18:38.025756 268 : 4253, 4029
7441 22:18:38.029086 272 : 4250, 4027
7442 22:18:38.029169 276 : 4250, 4026
7443 22:18:38.029234 280 : 4361, 4138
7444 22:18:38.032277 284 : 4250, 4027
7445 22:18:38.032360 288 : 4250, 4027
7446 22:18:38.035951 292 : 4363, 4140
7447 22:18:38.036034 296 : 4250, 4027
7448 22:18:38.039112 300 : 4250, 4027
7449 22:18:38.039196 304 : 4363, 4140
7450 22:18:38.042005 308 : 4250, 4007
7451 22:18:38.042087 312 : 4250, 2240
7452 22:18:38.045257 316 : 4250, 18
7453 22:18:38.045340
7454 22:18:38.045404 MIOCK jitter meter ch=0
7455 22:18:38.045464
7456 22:18:38.048775 1T = (316-88) = 228 dly cells
7457 22:18:38.055350 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 285/100 ps
7458 22:18:38.055433 ==
7459 22:18:38.058621 Dram Type= 6, Freq= 0, CH_0, rank 0
7460 22:18:38.061931 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7461 22:18:38.062014 ==
7462 22:18:38.068604 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7463 22:18:38.072066 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7464 22:18:38.075456 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7465 22:18:38.082176 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7466 22:18:38.091683 [CA 0] Center 42 (12~73) winsize 62
7467 22:18:38.094918 [CA 1] Center 43 (12~74) winsize 63
7468 22:18:38.098272 [CA 2] Center 38 (8~68) winsize 61
7469 22:18:38.102395 [CA 3] Center 37 (8~67) winsize 60
7470 22:18:38.104895 [CA 4] Center 36 (7~66) winsize 60
7471 22:18:38.108300 [CA 5] Center 35 (6~65) winsize 60
7472 22:18:38.108411
7473 22:18:38.111988 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7474 22:18:38.112070
7475 22:18:38.115051 [CATrainingPosCal] consider 1 rank data
7476 22:18:38.118648 u2DelayCellTimex100 = 285/100 ps
7477 22:18:38.122173 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7478 22:18:38.128138 CA1 delay=43 (12~74),Diff = 8 PI (27 cell)
7479 22:18:38.131938 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7480 22:18:38.134859 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7481 22:18:38.138163 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7482 22:18:38.141791 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7483 22:18:38.141873
7484 22:18:38.144816 CA PerBit enable=1, Macro0, CA PI delay=35
7485 22:18:38.144898
7486 22:18:38.148219 [CBTSetCACLKResult] CA Dly = 35
7487 22:18:38.151914 CS Dly: 9 (0~40)
7488 22:18:38.154657 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7489 22:18:38.158571 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7490 22:18:38.158651 ==
7491 22:18:38.161636 Dram Type= 6, Freq= 0, CH_0, rank 1
7492 22:18:38.164871 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7493 22:18:38.168139 ==
7494 22:18:38.171445 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7495 22:18:38.174419 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7496 22:18:38.181005 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7497 22:18:38.184484 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7498 22:18:38.195276 [CA 0] Center 42 (12~73) winsize 62
7499 22:18:38.198089 [CA 1] Center 42 (12~73) winsize 62
7500 22:18:38.201963 [CA 2] Center 38 (8~68) winsize 61
7501 22:18:38.205474 [CA 3] Center 37 (7~67) winsize 61
7502 22:18:38.208196 [CA 4] Center 36 (6~66) winsize 61
7503 22:18:38.211710 [CA 5] Center 35 (5~65) winsize 61
7504 22:18:38.211792
7505 22:18:38.215297 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7506 22:18:38.215388
7507 22:18:38.218366 [CATrainingPosCal] consider 2 rank data
7508 22:18:38.221923 u2DelayCellTimex100 = 285/100 ps
7509 22:18:38.224892 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7510 22:18:38.231480 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7511 22:18:38.235132 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7512 22:18:38.238129 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7513 22:18:38.241775 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7514 22:18:38.244590 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7515 22:18:38.244672
7516 22:18:38.248023 CA PerBit enable=1, Macro0, CA PI delay=35
7517 22:18:38.248105
7518 22:18:38.251219 [CBTSetCACLKResult] CA Dly = 35
7519 22:18:38.255222 CS Dly: 10 (0~42)
7520 22:18:38.258148 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7521 22:18:38.261387 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7522 22:18:38.261471
7523 22:18:38.264859 ----->DramcWriteLeveling(PI) begin...
7524 22:18:38.264942 ==
7525 22:18:38.267889 Dram Type= 6, Freq= 0, CH_0, rank 0
7526 22:18:38.271349 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7527 22:18:38.274741 ==
7528 22:18:38.278306 Write leveling (Byte 0): 34 => 34
7529 22:18:38.278390 Write leveling (Byte 1): 28 => 28
7530 22:18:38.281381 DramcWriteLeveling(PI) end<-----
7531 22:18:38.281464
7532 22:18:38.281570 ==
7533 22:18:38.284385 Dram Type= 6, Freq= 0, CH_0, rank 0
7534 22:18:38.290994 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7535 22:18:38.291078 ==
7536 22:18:38.294538 [Gating] SW mode calibration
7537 22:18:38.301024 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7538 22:18:38.304665 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7539 22:18:38.311114 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7540 22:18:38.314800 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7541 22:18:38.317629 1 4 8 | B1->B0 | 2323 2424 | 0 1 | (0 0) (1 1)
7542 22:18:38.324515 1 4 12 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
7543 22:18:38.327315 1 4 16 | B1->B0 | 2424 3b3a | 0 1 | (0 0) (0 0)
7544 22:18:38.330915 1 4 20 | B1->B0 | 3232 3534 | 0 1 | (0 0) (1 1)
7545 22:18:38.337482 1 4 24 | B1->B0 | 3434 3636 | 1 1 | (1 1) (1 1)
7546 22:18:38.341188 1 4 28 | B1->B0 | 3434 3636 | 1 0 | (1 1) (0 0)
7547 22:18:38.344260 1 5 0 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
7548 22:18:38.351192 1 5 4 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7549 22:18:38.354251 1 5 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (0 0)
7550 22:18:38.357461 1 5 12 | B1->B0 | 3434 2525 | 1 0 | (1 1) (1 0)
7551 22:18:38.364287 1 5 16 | B1->B0 | 3232 2c2b | 1 1 | (1 0) (0 0)
7552 22:18:38.367051 1 5 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
7553 22:18:38.370585 1 5 24 | B1->B0 | 2323 2726 | 0 1 | (0 0) (0 0)
7554 22:18:38.377398 1 5 28 | B1->B0 | 2323 2928 | 0 1 | (0 0) (0 0)
7555 22:18:38.380483 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7556 22:18:38.383551 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7557 22:18:38.390399 1 6 8 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
7558 22:18:38.394008 1 6 12 | B1->B0 | 2323 4544 | 0 1 | (0 0) (0 0)
7559 22:18:38.396863 1 6 16 | B1->B0 | 2727 4646 | 0 0 | (0 0) (0 0)
7560 22:18:38.400336 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7561 22:18:38.406811 1 6 24 | B1->B0 | 4646 4545 | 0 1 | (0 0) (0 0)
7562 22:18:38.410445 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7563 22:18:38.413891 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7564 22:18:38.420214 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7565 22:18:38.423896 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7566 22:18:38.427450 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7567 22:18:38.433355 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7568 22:18:38.437209 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7569 22:18:38.440287 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7570 22:18:38.447346 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7571 22:18:38.450463 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7572 22:18:38.453973 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7573 22:18:38.460311 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7574 22:18:38.463515 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7575 22:18:38.466931 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7576 22:18:38.473470 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7577 22:18:38.477004 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7578 22:18:38.480454 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7579 22:18:38.486626 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7580 22:18:38.489967 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7581 22:18:38.493326 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7582 22:18:38.499980 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7583 22:18:38.503532 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7584 22:18:38.506934 Total UI for P1: 0, mck2ui 16
7585 22:18:38.510317 best dqsien dly found for B0: ( 1, 9, 10)
7586 22:18:38.513421 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7587 22:18:38.516803 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7588 22:18:38.520444 Total UI for P1: 0, mck2ui 16
7589 22:18:38.523339 best dqsien dly found for B1: ( 1, 9, 20)
7590 22:18:38.526741 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7591 22:18:38.533506 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7592 22:18:38.533605
7593 22:18:38.536824 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7594 22:18:38.539839 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7595 22:18:38.543194 [Gating] SW calibration Done
7596 22:18:38.543264 ==
7597 22:18:38.546379 Dram Type= 6, Freq= 0, CH_0, rank 0
7598 22:18:38.549946 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7599 22:18:38.550016 ==
7600 22:18:38.553094 RX Vref Scan: 0
7601 22:18:38.553160
7602 22:18:38.553219 RX Vref 0 -> 0, step: 1
7603 22:18:38.553278
7604 22:18:38.556825 RX Delay 0 -> 252, step: 8
7605 22:18:38.560396 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7606 22:18:38.563219 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7607 22:18:38.570234 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
7608 22:18:38.573319 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
7609 22:18:38.576752 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7610 22:18:38.580032 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7611 22:18:38.582905 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7612 22:18:38.589886 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7613 22:18:38.593213 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7614 22:18:38.596156 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
7615 22:18:38.599518 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7616 22:18:38.602667 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7617 22:18:38.609676 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
7618 22:18:38.612818 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
7619 22:18:38.616137 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7620 22:18:38.619259 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7621 22:18:38.619331 ==
7622 22:18:38.622775 Dram Type= 6, Freq= 0, CH_0, rank 0
7623 22:18:38.629500 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7624 22:18:38.629619 ==
7625 22:18:38.629684 DQS Delay:
7626 22:18:38.632999 DQS0 = 0, DQS1 = 0
7627 22:18:38.633069 DQM Delay:
7628 22:18:38.636045 DQM0 = 137, DQM1 = 130
7629 22:18:38.636111 DQ Delay:
7630 22:18:38.639531 DQ0 =135, DQ1 =143, DQ2 =135, DQ3 =135
7631 22:18:38.643300 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =143
7632 22:18:38.646175 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
7633 22:18:38.649292 DQ12 =135, DQ13 =139, DQ14 =139, DQ15 =135
7634 22:18:38.649361
7635 22:18:38.649422
7636 22:18:38.649481 ==
7637 22:18:38.652842 Dram Type= 6, Freq= 0, CH_0, rank 0
7638 22:18:38.656532 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7639 22:18:38.659489 ==
7640 22:18:38.659558
7641 22:18:38.659618
7642 22:18:38.659675 TX Vref Scan disable
7643 22:18:38.662437 == TX Byte 0 ==
7644 22:18:38.665918 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7645 22:18:38.669416 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7646 22:18:38.672592 == TX Byte 1 ==
7647 22:18:38.675966 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7648 22:18:38.682433 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7649 22:18:38.682506 ==
7650 22:18:38.685759 Dram Type= 6, Freq= 0, CH_0, rank 0
7651 22:18:38.689285 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7652 22:18:38.689394 ==
7653 22:18:38.700909
7654 22:18:38.704169 TX Vref early break, caculate TX vref
7655 22:18:38.707395 TX Vref=16, minBit 0, minWin=23, winSum=382
7656 22:18:38.710694 TX Vref=18, minBit 0, minWin=24, winSum=392
7657 22:18:38.714263 TX Vref=20, minBit 0, minWin=24, winSum=402
7658 22:18:38.717703 TX Vref=22, minBit 7, minWin=24, winSum=410
7659 22:18:38.720840 TX Vref=24, minBit 8, minWin=25, winSum=422
7660 22:18:38.727716 TX Vref=26, minBit 2, minWin=24, winSum=427
7661 22:18:38.730724 TX Vref=28, minBit 6, minWin=24, winSum=425
7662 22:18:38.734124 TX Vref=30, minBit 1, minWin=24, winSum=411
7663 22:18:38.737215 TX Vref=32, minBit 8, minWin=23, winSum=402
7664 22:18:38.743813 [TxChooseVref] Worse bit 8, Min win 25, Win sum 422, Final Vref 24
7665 22:18:38.743896
7666 22:18:38.746958 Final TX Range 0 Vref 24
7667 22:18:38.747040
7668 22:18:38.747105 ==
7669 22:18:38.750768 Dram Type= 6, Freq= 0, CH_0, rank 0
7670 22:18:38.753670 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7671 22:18:38.753753 ==
7672 22:18:38.753817
7673 22:18:38.753878
7674 22:18:38.757051 TX Vref Scan disable
7675 22:18:38.764031 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
7676 22:18:38.764113 == TX Byte 0 ==
7677 22:18:38.767003 u2DelayCellOfst[0]=10 cells (3 PI)
7678 22:18:38.770523 u2DelayCellOfst[1]=13 cells (4 PI)
7679 22:18:38.773977 u2DelayCellOfst[2]=6 cells (2 PI)
7680 22:18:38.777201 u2DelayCellOfst[3]=10 cells (3 PI)
7681 22:18:38.780800 u2DelayCellOfst[4]=6 cells (2 PI)
7682 22:18:38.780881 u2DelayCellOfst[5]=0 cells (0 PI)
7683 22:18:38.783930 u2DelayCellOfst[6]=17 cells (5 PI)
7684 22:18:38.787327 u2DelayCellOfst[7]=17 cells (5 PI)
7685 22:18:38.794043 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7686 22:18:38.796841 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7687 22:18:38.796926 == TX Byte 1 ==
7688 22:18:38.800925 u2DelayCellOfst[8]=0 cells (0 PI)
7689 22:18:38.803598 u2DelayCellOfst[9]=0 cells (0 PI)
7690 22:18:38.807458 u2DelayCellOfst[10]=6 cells (2 PI)
7691 22:18:38.810479 u2DelayCellOfst[11]=3 cells (1 PI)
7692 22:18:38.813828 u2DelayCellOfst[12]=10 cells (3 PI)
7693 22:18:38.817426 u2DelayCellOfst[13]=10 cells (3 PI)
7694 22:18:38.820802 u2DelayCellOfst[14]=13 cells (4 PI)
7695 22:18:38.823426 u2DelayCellOfst[15]=10 cells (3 PI)
7696 22:18:38.827012 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7697 22:18:38.830281 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7698 22:18:38.833484 DramC Write-DBI on
7699 22:18:38.833623 ==
7700 22:18:38.836944 Dram Type= 6, Freq= 0, CH_0, rank 0
7701 22:18:38.840013 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7702 22:18:38.840095 ==
7703 22:18:38.840160
7704 22:18:38.840218
7705 22:18:38.843757 TX Vref Scan disable
7706 22:18:38.847090 == TX Byte 0 ==
7707 22:18:38.850138 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7708 22:18:38.853717 == TX Byte 1 ==
7709 22:18:38.856646 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7710 22:18:38.856753 DramC Write-DBI off
7711 22:18:38.856845
7712 22:18:38.860283 [DATLAT]
7713 22:18:38.860365 Freq=1600, CH0 RK0
7714 22:18:38.860429
7715 22:18:38.863478 DATLAT Default: 0xf
7716 22:18:38.863560 0, 0xFFFF, sum = 0
7717 22:18:38.866563 1, 0xFFFF, sum = 0
7718 22:18:38.866646 2, 0xFFFF, sum = 0
7719 22:18:38.870098 3, 0xFFFF, sum = 0
7720 22:18:38.870180 4, 0xFFFF, sum = 0
7721 22:18:38.873192 5, 0xFFFF, sum = 0
7722 22:18:38.873274 6, 0xFFFF, sum = 0
7723 22:18:38.876826 7, 0xFFFF, sum = 0
7724 22:18:38.879745 8, 0xFFFF, sum = 0
7725 22:18:38.879828 9, 0xFFFF, sum = 0
7726 22:18:38.883267 10, 0xFFFF, sum = 0
7727 22:18:38.883350 11, 0xFFFF, sum = 0
7728 22:18:38.886472 12, 0xFFFF, sum = 0
7729 22:18:38.886554 13, 0xFFFF, sum = 0
7730 22:18:38.889654 14, 0x0, sum = 1
7731 22:18:38.889737 15, 0x0, sum = 2
7732 22:18:38.893456 16, 0x0, sum = 3
7733 22:18:38.893591 17, 0x0, sum = 4
7734 22:18:38.896640 best_step = 15
7735 22:18:38.896721
7736 22:18:38.896784 ==
7737 22:18:38.899711 Dram Type= 6, Freq= 0, CH_0, rank 0
7738 22:18:38.903200 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7739 22:18:38.903282 ==
7740 22:18:38.903346 RX Vref Scan: 1
7741 22:18:38.906373
7742 22:18:38.906456 Set Vref Range= 24 -> 127
7743 22:18:38.906522
7744 22:18:38.909691 RX Vref 24 -> 127, step: 1
7745 22:18:38.909774
7746 22:18:38.912822 RX Delay 19 -> 252, step: 4
7747 22:18:38.912904
7748 22:18:38.916298 Set Vref, RX VrefLevel [Byte0]: 24
7749 22:18:38.919522 [Byte1]: 24
7750 22:18:38.919604
7751 22:18:38.922966 Set Vref, RX VrefLevel [Byte0]: 25
7752 22:18:38.926248 [Byte1]: 25
7753 22:18:38.926331
7754 22:18:38.929377 Set Vref, RX VrefLevel [Byte0]: 26
7755 22:18:38.932648 [Byte1]: 26
7756 22:18:38.936679
7757 22:18:38.936761 Set Vref, RX VrefLevel [Byte0]: 27
7758 22:18:38.939793 [Byte1]: 27
7759 22:18:38.944110
7760 22:18:38.944192 Set Vref, RX VrefLevel [Byte0]: 28
7761 22:18:38.947384 [Byte1]: 28
7762 22:18:38.951679
7763 22:18:38.951766 Set Vref, RX VrefLevel [Byte0]: 29
7764 22:18:38.955181 [Byte1]: 29
7765 22:18:38.959555
7766 22:18:38.959637 Set Vref, RX VrefLevel [Byte0]: 30
7767 22:18:38.962416 [Byte1]: 30
7768 22:18:38.966790
7769 22:18:38.966871 Set Vref, RX VrefLevel [Byte0]: 31
7770 22:18:38.970522 [Byte1]: 31
7771 22:18:38.974692
7772 22:18:38.974773 Set Vref, RX VrefLevel [Byte0]: 32
7773 22:18:38.977662 [Byte1]: 32
7774 22:18:38.981946
7775 22:18:38.982028 Set Vref, RX VrefLevel [Byte0]: 33
7776 22:18:38.985798 [Byte1]: 33
7777 22:18:38.989541
7778 22:18:38.989653 Set Vref, RX VrefLevel [Byte0]: 34
7779 22:18:38.993190 [Byte1]: 34
7780 22:18:38.997317
7781 22:18:38.997398 Set Vref, RX VrefLevel [Byte0]: 35
7782 22:18:39.000227 [Byte1]: 35
7783 22:18:39.004908
7784 22:18:39.004990 Set Vref, RX VrefLevel [Byte0]: 36
7785 22:18:39.007846 [Byte1]: 36
7786 22:18:39.012470
7787 22:18:39.012552 Set Vref, RX VrefLevel [Byte0]: 37
7788 22:18:39.015874 [Byte1]: 37
7789 22:18:39.019802
7790 22:18:39.019883 Set Vref, RX VrefLevel [Byte0]: 38
7791 22:18:39.023047 [Byte1]: 38
7792 22:18:39.027498
7793 22:18:39.027580 Set Vref, RX VrefLevel [Byte0]: 39
7794 22:18:39.030779 [Byte1]: 39
7795 22:18:39.034963
7796 22:18:39.035045 Set Vref, RX VrefLevel [Byte0]: 40
7797 22:18:39.038282 [Byte1]: 40
7798 22:18:39.042827
7799 22:18:39.042909 Set Vref, RX VrefLevel [Byte0]: 41
7800 22:18:39.046098 [Byte1]: 41
7801 22:18:39.050569
7802 22:18:39.050650 Set Vref, RX VrefLevel [Byte0]: 42
7803 22:18:39.053274 [Byte1]: 42
7804 22:18:39.057685
7805 22:18:39.057767 Set Vref, RX VrefLevel [Byte0]: 43
7806 22:18:39.061318 [Byte1]: 43
7807 22:18:39.065676
7808 22:18:39.065758 Set Vref, RX VrefLevel [Byte0]: 44
7809 22:18:39.068737 [Byte1]: 44
7810 22:18:39.072967
7811 22:18:39.073049 Set Vref, RX VrefLevel [Byte0]: 45
7812 22:18:39.076534 [Byte1]: 45
7813 22:18:39.080884
7814 22:18:39.080966 Set Vref, RX VrefLevel [Byte0]: 46
7815 22:18:39.083902 [Byte1]: 46
7816 22:18:39.088003
7817 22:18:39.088085 Set Vref, RX VrefLevel [Byte0]: 47
7818 22:18:39.091296 [Byte1]: 47
7819 22:18:39.096074
7820 22:18:39.096156 Set Vref, RX VrefLevel [Byte0]: 48
7821 22:18:39.099028 [Byte1]: 48
7822 22:18:39.103473
7823 22:18:39.103555 Set Vref, RX VrefLevel [Byte0]: 49
7824 22:18:39.106463 [Byte1]: 49
7825 22:18:39.111251
7826 22:18:39.111333 Set Vref, RX VrefLevel [Byte0]: 50
7827 22:18:39.114173 [Byte1]: 50
7828 22:18:39.118453
7829 22:18:39.118535 Set Vref, RX VrefLevel [Byte0]: 51
7830 22:18:39.121894 [Byte1]: 51
7831 22:18:39.126194
7832 22:18:39.126276 Set Vref, RX VrefLevel [Byte0]: 52
7833 22:18:39.129407 [Byte1]: 52
7834 22:18:39.133350
7835 22:18:39.133432 Set Vref, RX VrefLevel [Byte0]: 53
7836 22:18:39.136748 [Byte1]: 53
7837 22:18:39.140959
7838 22:18:39.141045 Set Vref, RX VrefLevel [Byte0]: 54
7839 22:18:39.144223 [Byte1]: 54
7840 22:18:39.148810
7841 22:18:39.148892 Set Vref, RX VrefLevel [Byte0]: 55
7842 22:18:39.152249 [Byte1]: 55
7843 22:18:39.156471
7844 22:18:39.156553 Set Vref, RX VrefLevel [Byte0]: 56
7845 22:18:39.159685 [Byte1]: 56
7846 22:18:39.163886
7847 22:18:39.163969 Set Vref, RX VrefLevel [Byte0]: 57
7848 22:18:39.167299 [Byte1]: 57
7849 22:18:39.171377
7850 22:18:39.171459 Set Vref, RX VrefLevel [Byte0]: 58
7851 22:18:39.175096 [Byte1]: 58
7852 22:18:39.179272
7853 22:18:39.179354 Set Vref, RX VrefLevel [Byte0]: 59
7854 22:18:39.182387 [Byte1]: 59
7855 22:18:39.186537
7856 22:18:39.186619 Set Vref, RX VrefLevel [Byte0]: 60
7857 22:18:39.193259 [Byte1]: 60
7858 22:18:39.193341
7859 22:18:39.196220 Set Vref, RX VrefLevel [Byte0]: 61
7860 22:18:39.199822 [Byte1]: 61
7861 22:18:39.199905
7862 22:18:39.203262 Set Vref, RX VrefLevel [Byte0]: 62
7863 22:18:39.206120 [Byte1]: 62
7864 22:18:39.206201
7865 22:18:39.209353 Set Vref, RX VrefLevel [Byte0]: 63
7866 22:18:39.212639 [Byte1]: 63
7867 22:18:39.216955
7868 22:18:39.217037 Set Vref, RX VrefLevel [Byte0]: 64
7869 22:18:39.220505 [Byte1]: 64
7870 22:18:39.224350
7871 22:18:39.224432 Set Vref, RX VrefLevel [Byte0]: 65
7872 22:18:39.227593 [Byte1]: 65
7873 22:18:39.232292
7874 22:18:39.232373 Set Vref, RX VrefLevel [Byte0]: 66
7875 22:18:39.235602 [Byte1]: 66
7876 22:18:39.239673
7877 22:18:39.239754 Set Vref, RX VrefLevel [Byte0]: 67
7878 22:18:39.242914 [Byte1]: 67
7879 22:18:39.247060
7880 22:18:39.247142 Set Vref, RX VrefLevel [Byte0]: 68
7881 22:18:39.250193 [Byte1]: 68
7882 22:18:39.254770
7883 22:18:39.254852 Set Vref, RX VrefLevel [Byte0]: 69
7884 22:18:39.258075 [Byte1]: 69
7885 22:18:39.262203
7886 22:18:39.262284 Set Vref, RX VrefLevel [Byte0]: 70
7887 22:18:39.265427 [Byte1]: 70
7888 22:18:39.269641
7889 22:18:39.269721 Set Vref, RX VrefLevel [Byte0]: 71
7890 22:18:39.272892 [Byte1]: 71
7891 22:18:39.277489
7892 22:18:39.277614 Set Vref, RX VrefLevel [Byte0]: 72
7893 22:18:39.280534 [Byte1]: 72
7894 22:18:39.284871
7895 22:18:39.284948 Set Vref, RX VrefLevel [Byte0]: 73
7896 22:18:39.288320 [Byte1]: 73
7897 22:18:39.292541
7898 22:18:39.292616 Set Vref, RX VrefLevel [Byte0]: 74
7899 22:18:39.296029 [Byte1]: 74
7900 22:18:39.300179
7901 22:18:39.300294 Set Vref, RX VrefLevel [Byte0]: 75
7902 22:18:39.303316 [Byte1]: 75
7903 22:18:39.307632
7904 22:18:39.307765 Set Vref, RX VrefLevel [Byte0]: 76
7905 22:18:39.310843 [Byte1]: 76
7906 22:18:39.315126
7907 22:18:39.315201 Set Vref, RX VrefLevel [Byte0]: 77
7908 22:18:39.318684 [Byte1]: 77
7909 22:18:39.322619
7910 22:18:39.322690 Final RX Vref Byte 0 = 56 to rank0
7911 22:18:39.325981 Final RX Vref Byte 1 = 60 to rank0
7912 22:18:39.329545 Final RX Vref Byte 0 = 56 to rank1
7913 22:18:39.332614 Final RX Vref Byte 1 = 60 to rank1==
7914 22:18:39.336275 Dram Type= 6, Freq= 0, CH_0, rank 0
7915 22:18:39.342579 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7916 22:18:39.342666 ==
7917 22:18:39.342731 DQS Delay:
7918 22:18:39.342791 DQS0 = 0, DQS1 = 0
7919 22:18:39.345853 DQM Delay:
7920 22:18:39.345925 DQM0 = 134, DQM1 = 127
7921 22:18:39.349623 DQ Delay:
7922 22:18:39.352647 DQ0 =134, DQ1 =138, DQ2 =134, DQ3 =132
7923 22:18:39.355978 DQ4 =132, DQ5 =124, DQ6 =140, DQ7 =138
7924 22:18:39.359337 DQ8 =116, DQ9 =118, DQ10 =128, DQ11 =120
7925 22:18:39.362721 DQ12 =132, DQ13 =134, DQ14 =138, DQ15 =134
7926 22:18:39.362800
7927 22:18:39.362864
7928 22:18:39.362923
7929 22:18:39.366045 [DramC_TX_OE_Calibration] TA2
7930 22:18:39.369390 Original DQ_B0 (3 6) =30, OEN = 27
7931 22:18:39.372660 Original DQ_B1 (3 6) =30, OEN = 27
7932 22:18:39.376246 24, 0x0, End_B0=24 End_B1=24
7933 22:18:39.376331 25, 0x0, End_B0=25 End_B1=25
7934 22:18:39.379517 26, 0x0, End_B0=26 End_B1=26
7935 22:18:39.383231 27, 0x0, End_B0=27 End_B1=27
7936 22:18:39.386109 28, 0x0, End_B0=28 End_B1=28
7937 22:18:39.386193 29, 0x0, End_B0=29 End_B1=29
7938 22:18:39.389933 30, 0x0, End_B0=30 End_B1=30
7939 22:18:39.392931 31, 0x4141, End_B0=30 End_B1=30
7940 22:18:39.395871 Byte0 end_step=30 best_step=27
7941 22:18:39.399319 Byte1 end_step=30 best_step=27
7942 22:18:39.402882 Byte0 TX OE(2T, 0.5T) = (3, 3)
7943 22:18:39.402957 Byte1 TX OE(2T, 0.5T) = (3, 3)
7944 22:18:39.403020
7945 22:18:39.405880
7946 22:18:39.412780 [DQSOSCAuto] RK0, (LSB)MR18= 0x2722, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 390 ps
7947 22:18:39.416323 CH0 RK0: MR19=303, MR18=2722
7948 22:18:39.422999 CH0_RK0: MR19=0x303, MR18=0x2722, DQSOSC=390, MR23=63, INC=24, DEC=16
7949 22:18:39.423078
7950 22:18:39.425881 ----->DramcWriteLeveling(PI) begin...
7951 22:18:39.425956 ==
7952 22:18:39.429496 Dram Type= 6, Freq= 0, CH_0, rank 1
7953 22:18:39.432509 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7954 22:18:39.432614 ==
7955 22:18:39.436126 Write leveling (Byte 0): 35 => 35
7956 22:18:39.440035 Write leveling (Byte 1): 27 => 27
7957 22:18:39.442810 DramcWriteLeveling(PI) end<-----
7958 22:18:39.442894
7959 22:18:39.442957 ==
7960 22:18:39.445489 Dram Type= 6, Freq= 0, CH_0, rank 1
7961 22:18:39.448982 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7962 22:18:39.449084 ==
7963 22:18:39.452418 [Gating] SW mode calibration
7964 22:18:39.458820 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7965 22:18:39.465763 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7966 22:18:39.469084 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7967 22:18:39.472656 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7968 22:18:39.478945 1 4 8 | B1->B0 | 2323 2625 | 0 1 | (0 0) (1 1)
7969 22:18:39.482381 1 4 12 | B1->B0 | 2424 2a2a | 0 0 | (0 0) (0 0)
7970 22:18:39.485584 1 4 16 | B1->B0 | 2e2e 3535 | 1 0 | (1 1) (0 0)
7971 22:18:39.492284 1 4 20 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7972 22:18:39.495490 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7973 22:18:39.499004 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7974 22:18:39.505717 1 5 0 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
7975 22:18:39.509428 1 5 4 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7976 22:18:39.512366 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7977 22:18:39.519331 1 5 12 | B1->B0 | 3434 3131 | 1 0 | (1 0) (0 0)
7978 22:18:39.522374 1 5 16 | B1->B0 | 2d2d 2424 | 1 0 | (1 0) (1 0)
7979 22:18:39.525883 1 5 20 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7980 22:18:39.532446 1 5 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7981 22:18:39.535957 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7982 22:18:39.538883 1 6 0 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7983 22:18:39.545378 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7984 22:18:39.549129 1 6 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7985 22:18:39.552233 1 6 12 | B1->B0 | 2323 3a3a | 0 1 | (0 0) (0 0)
7986 22:18:39.558774 1 6 16 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
7987 22:18:39.561875 1 6 20 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
7988 22:18:39.565494 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7989 22:18:39.572053 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7990 22:18:39.575267 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7991 22:18:39.578467 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7992 22:18:39.585103 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7993 22:18:39.588555 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7994 22:18:39.591837 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7995 22:18:39.594952 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7996 22:18:39.602143 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7997 22:18:39.605304 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7998 22:18:39.608161 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7999 22:18:39.614838 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8000 22:18:39.618321 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8001 22:18:39.621945 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8002 22:18:39.628193 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8003 22:18:39.631783 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8004 22:18:39.634824 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8005 22:18:39.641437 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8006 22:18:39.645013 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8007 22:18:39.648162 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8008 22:18:39.654780 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8009 22:18:39.657929 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8010 22:18:39.661224 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8011 22:18:39.667842 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8012 22:18:39.671376 Total UI for P1: 0, mck2ui 16
8013 22:18:39.674405 best dqsien dly found for B0: ( 1, 9, 14)
8014 22:18:39.674483 Total UI for P1: 0, mck2ui 16
8015 22:18:39.681593 best dqsien dly found for B1: ( 1, 9, 14)
8016 22:18:39.684511 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8017 22:18:39.687723 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8018 22:18:39.687820
8019 22:18:39.691750 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8020 22:18:39.694861 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8021 22:18:39.698207 [Gating] SW calibration Done
8022 22:18:39.698277 ==
8023 22:18:39.701697 Dram Type= 6, Freq= 0, CH_0, rank 1
8024 22:18:39.704533 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8025 22:18:39.704606 ==
8026 22:18:39.708134 RX Vref Scan: 0
8027 22:18:39.708202
8028 22:18:39.708261 RX Vref 0 -> 0, step: 1
8029 22:18:39.708323
8030 22:18:39.711227 RX Delay 0 -> 252, step: 8
8031 22:18:39.714775 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8032 22:18:39.721525 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8033 22:18:39.724469 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8034 22:18:39.728122 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8035 22:18:39.731607 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8036 22:18:39.734575 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8037 22:18:39.741338 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8038 22:18:39.744444 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8039 22:18:39.747827 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8040 22:18:39.751550 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8041 22:18:39.754555 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8042 22:18:39.761106 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8043 22:18:39.764305 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8044 22:18:39.767968 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8045 22:18:39.771182 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8046 22:18:39.774495 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8047 22:18:39.777980 ==
8048 22:18:39.778124 Dram Type= 6, Freq= 0, CH_0, rank 1
8049 22:18:39.784461 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8050 22:18:39.784594 ==
8051 22:18:39.784709 DQS Delay:
8052 22:18:39.788104 DQS0 = 0, DQS1 = 0
8053 22:18:39.788227 DQM Delay:
8054 22:18:39.791544 DQM0 = 137, DQM1 = 128
8055 22:18:39.791667 DQ Delay:
8056 22:18:39.794324 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8057 22:18:39.797736 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8058 22:18:39.801258 DQ8 =119, DQ9 =119, DQ10 =127, DQ11 =119
8059 22:18:39.804822 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8060 22:18:39.804935
8061 22:18:39.805030
8062 22:18:39.805124 ==
8063 22:18:39.807732 Dram Type= 6, Freq= 0, CH_0, rank 1
8064 22:18:39.814557 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8065 22:18:39.814674 ==
8066 22:18:39.814769
8067 22:18:39.814861
8068 22:18:39.814956 TX Vref Scan disable
8069 22:18:39.818140 == TX Byte 0 ==
8070 22:18:39.821170 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8071 22:18:39.827809 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8072 22:18:39.827968 == TX Byte 1 ==
8073 22:18:39.830956 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8074 22:18:39.837922 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8075 22:18:39.838051 ==
8076 22:18:39.841500 Dram Type= 6, Freq= 0, CH_0, rank 1
8077 22:18:39.844331 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8078 22:18:39.844457 ==
8079 22:18:39.857807
8080 22:18:39.861402 TX Vref early break, caculate TX vref
8081 22:18:39.864349 TX Vref=16, minBit 0, minWin=23, winSum=386
8082 22:18:39.868105 TX Vref=18, minBit 1, minWin=23, winSum=394
8083 22:18:39.871170 TX Vref=20, minBit 1, minWin=24, winSum=407
8084 22:18:39.874524 TX Vref=22, minBit 1, minWin=25, winSum=414
8085 22:18:39.878012 TX Vref=24, minBit 1, minWin=25, winSum=424
8086 22:18:39.884758 TX Vref=26, minBit 3, minWin=25, winSum=427
8087 22:18:39.887889 TX Vref=28, minBit 1, minWin=26, winSum=427
8088 22:18:39.890982 TX Vref=30, minBit 0, minWin=25, winSum=418
8089 22:18:39.894266 TX Vref=32, minBit 4, minWin=24, winSum=411
8090 22:18:39.897760 TX Vref=34, minBit 0, minWin=23, winSum=397
8091 22:18:39.904338 [TxChooseVref] Worse bit 1, Min win 26, Win sum 427, Final Vref 28
8092 22:18:39.904450
8093 22:18:39.907841 Final TX Range 0 Vref 28
8094 22:18:39.907952
8095 22:18:39.908054 ==
8096 22:18:39.911392 Dram Type= 6, Freq= 0, CH_0, rank 1
8097 22:18:39.914132 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8098 22:18:39.914244 ==
8099 22:18:39.914341
8100 22:18:39.914454
8101 22:18:39.917617 TX Vref Scan disable
8102 22:18:39.924260 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8103 22:18:39.924376 == TX Byte 0 ==
8104 22:18:39.927734 u2DelayCellOfst[0]=13 cells (4 PI)
8105 22:18:39.931286 u2DelayCellOfst[1]=13 cells (4 PI)
8106 22:18:39.934336 u2DelayCellOfst[2]=10 cells (3 PI)
8107 22:18:39.937634 u2DelayCellOfst[3]=10 cells (3 PI)
8108 22:18:39.941140 u2DelayCellOfst[4]=6 cells (2 PI)
8109 22:18:39.944283 u2DelayCellOfst[5]=0 cells (0 PI)
8110 22:18:39.947426 u2DelayCellOfst[6]=17 cells (5 PI)
8111 22:18:39.950882 u2DelayCellOfst[7]=17 cells (5 PI)
8112 22:18:39.954010 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8113 22:18:39.957497 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8114 22:18:39.960599 == TX Byte 1 ==
8115 22:18:39.963676 u2DelayCellOfst[8]=3 cells (1 PI)
8116 22:18:39.963796 u2DelayCellOfst[9]=0 cells (0 PI)
8117 22:18:39.967158 u2DelayCellOfst[10]=6 cells (2 PI)
8118 22:18:39.970870 u2DelayCellOfst[11]=3 cells (1 PI)
8119 22:18:39.973863 u2DelayCellOfst[12]=10 cells (3 PI)
8120 22:18:39.977472 u2DelayCellOfst[13]=10 cells (3 PI)
8121 22:18:39.980276 u2DelayCellOfst[14]=13 cells (4 PI)
8122 22:18:39.983721 u2DelayCellOfst[15]=10 cells (3 PI)
8123 22:18:39.986762 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8124 22:18:39.993964 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8125 22:18:39.994089 DramC Write-DBI on
8126 22:18:39.994188 ==
8127 22:18:39.996869 Dram Type= 6, Freq= 0, CH_0, rank 1
8128 22:18:40.004025 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8129 22:18:40.004144 ==
8130 22:18:40.004242
8131 22:18:40.004339
8132 22:18:40.004464 TX Vref Scan disable
8133 22:18:40.007547 == TX Byte 0 ==
8134 22:18:40.010488 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8135 22:18:40.014075 == TX Byte 1 ==
8136 22:18:40.017350 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8137 22:18:40.020958 DramC Write-DBI off
8138 22:18:40.021080
8139 22:18:40.021193 [DATLAT]
8140 22:18:40.021304 Freq=1600, CH0 RK1
8141 22:18:40.021400
8142 22:18:40.024187 DATLAT Default: 0xf
8143 22:18:40.024309 0, 0xFFFF, sum = 0
8144 22:18:40.027240 1, 0xFFFF, sum = 0
8145 22:18:40.030351 2, 0xFFFF, sum = 0
8146 22:18:40.030499 3, 0xFFFF, sum = 0
8147 22:18:40.034146 4, 0xFFFF, sum = 0
8148 22:18:40.034239 5, 0xFFFF, sum = 0
8149 22:18:40.037399 6, 0xFFFF, sum = 0
8150 22:18:40.037520 7, 0xFFFF, sum = 0
8151 22:18:40.040542 8, 0xFFFF, sum = 0
8152 22:18:40.040652 9, 0xFFFF, sum = 0
8153 22:18:40.044020 10, 0xFFFF, sum = 0
8154 22:18:40.044130 11, 0xFFFF, sum = 0
8155 22:18:40.047285 12, 0xFFFF, sum = 0
8156 22:18:40.047385 13, 0xFFFF, sum = 0
8157 22:18:40.050617 14, 0x0, sum = 1
8158 22:18:40.050718 15, 0x0, sum = 2
8159 22:18:40.053760 16, 0x0, sum = 3
8160 22:18:40.053835 17, 0x0, sum = 4
8161 22:18:40.057015 best_step = 15
8162 22:18:40.057110
8163 22:18:40.057200 ==
8164 22:18:40.060737 Dram Type= 6, Freq= 0, CH_0, rank 1
8165 22:18:40.063860 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8166 22:18:40.063968 ==
8167 22:18:40.067601 RX Vref Scan: 0
8168 22:18:40.067708
8169 22:18:40.067808 RX Vref 0 -> 0, step: 1
8170 22:18:40.067897
8171 22:18:40.070423 RX Delay 19 -> 252, step: 4
8172 22:18:40.074246 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8173 22:18:40.080582 iDelay=191, Bit 1, Center 138 (91 ~ 186) 96
8174 22:18:40.083829 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8175 22:18:40.087311 iDelay=191, Bit 3, Center 132 (79 ~ 186) 108
8176 22:18:40.090458 iDelay=191, Bit 4, Center 134 (83 ~ 186) 104
8177 22:18:40.094175 iDelay=191, Bit 5, Center 124 (71 ~ 178) 108
8178 22:18:40.100364 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8179 22:18:40.103832 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8180 22:18:40.107136 iDelay=191, Bit 8, Center 118 (67 ~ 170) 104
8181 22:18:40.110453 iDelay=191, Bit 9, Center 116 (67 ~ 166) 100
8182 22:18:40.114043 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
8183 22:18:40.120216 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8184 22:18:40.123597 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8185 22:18:40.126850 iDelay=191, Bit 13, Center 134 (83 ~ 186) 104
8186 22:18:40.130210 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8187 22:18:40.133580 iDelay=191, Bit 15, Center 134 (83 ~ 186) 104
8188 22:18:40.137324 ==
8189 22:18:40.137405 Dram Type= 6, Freq= 0, CH_0, rank 1
8190 22:18:40.143395 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8191 22:18:40.143477 ==
8192 22:18:40.143542 DQS Delay:
8193 22:18:40.147179 DQS0 = 0, DQS1 = 0
8194 22:18:40.147260 DQM Delay:
8195 22:18:40.150166 DQM0 = 134, DQM1 = 127
8196 22:18:40.150248 DQ Delay:
8197 22:18:40.153459 DQ0 =134, DQ1 =138, DQ2 =130, DQ3 =132
8198 22:18:40.157010 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =140
8199 22:18:40.160088 DQ8 =118, DQ9 =116, DQ10 =128, DQ11 =118
8200 22:18:40.163673 DQ12 =134, DQ13 =134, DQ14 =136, DQ15 =134
8201 22:18:40.163753
8202 22:18:40.163817
8203 22:18:40.163875
8204 22:18:40.166880 [DramC_TX_OE_Calibration] TA2
8205 22:18:40.170329 Original DQ_B0 (3 6) =30, OEN = 27
8206 22:18:40.173257 Original DQ_B1 (3 6) =30, OEN = 27
8207 22:18:40.176923 24, 0x0, End_B0=24 End_B1=24
8208 22:18:40.180527 25, 0x0, End_B0=25 End_B1=25
8209 22:18:40.180610 26, 0x0, End_B0=26 End_B1=26
8210 22:18:40.183466 27, 0x0, End_B0=27 End_B1=27
8211 22:18:40.187120 28, 0x0, End_B0=28 End_B1=28
8212 22:18:40.190318 29, 0x0, End_B0=29 End_B1=29
8213 22:18:40.190401 30, 0x0, End_B0=30 End_B1=30
8214 22:18:40.193207 31, 0x4141, End_B0=30 End_B1=30
8215 22:18:40.196712 Byte0 end_step=30 best_step=27
8216 22:18:40.199807 Byte1 end_step=30 best_step=27
8217 22:18:40.203192 Byte0 TX OE(2T, 0.5T) = (3, 3)
8218 22:18:40.206492 Byte1 TX OE(2T, 0.5T) = (3, 3)
8219 22:18:40.206573
8220 22:18:40.206638
8221 22:18:40.213537 [DQSOSCAuto] RK1, (LSB)MR18= 0x2109, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 393 ps
8222 22:18:40.216620 CH0 RK1: MR19=303, MR18=2109
8223 22:18:40.223438 CH0_RK1: MR19=0x303, MR18=0x2109, DQSOSC=393, MR23=63, INC=23, DEC=15
8224 22:18:40.226478 [RxdqsGatingPostProcess] freq 1600
8225 22:18:40.229691 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8226 22:18:40.233381 best DQS0 dly(2T, 0.5T) = (1, 1)
8227 22:18:40.236611 best DQS1 dly(2T, 0.5T) = (1, 1)
8228 22:18:40.239694 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8229 22:18:40.243203 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8230 22:18:40.246392 best DQS0 dly(2T, 0.5T) = (1, 1)
8231 22:18:40.249826 best DQS1 dly(2T, 0.5T) = (1, 1)
8232 22:18:40.253123 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8233 22:18:40.256618 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8234 22:18:40.260200 Pre-setting of DQS Precalculation
8235 22:18:40.263678 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8236 22:18:40.263760 ==
8237 22:18:40.266767 Dram Type= 6, Freq= 0, CH_1, rank 0
8238 22:18:40.273077 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8239 22:18:40.273160 ==
8240 22:18:40.276222 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8241 22:18:40.283145 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8242 22:18:40.286157 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8243 22:18:40.292773 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8244 22:18:40.300302 [CA 0] Center 42 (13~72) winsize 60
8245 22:18:40.303463 [CA 1] Center 42 (13~72) winsize 60
8246 22:18:40.306968 [CA 2] Center 38 (9~68) winsize 60
8247 22:18:40.310354 [CA 3] Center 39 (10~68) winsize 59
8248 22:18:40.313825 [CA 4] Center 38 (9~68) winsize 60
8249 22:18:40.316768 [CA 5] Center 37 (8~67) winsize 60
8250 22:18:40.316850
8251 22:18:40.320560 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8252 22:18:40.320642
8253 22:18:40.323397 [CATrainingPosCal] consider 1 rank data
8254 22:18:40.326709 u2DelayCellTimex100 = 285/100 ps
8255 22:18:40.333625 CA0 delay=42 (13~72),Diff = 5 PI (17 cell)
8256 22:18:40.337179 CA1 delay=42 (13~72),Diff = 5 PI (17 cell)
8257 22:18:40.340117 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8258 22:18:40.343491 CA3 delay=39 (10~68),Diff = 2 PI (6 cell)
8259 22:18:40.346516 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8260 22:18:40.350146 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8261 22:18:40.350228
8262 22:18:40.353709 CA PerBit enable=1, Macro0, CA PI delay=37
8263 22:18:40.353791
8264 22:18:40.356780 [CBTSetCACLKResult] CA Dly = 37
8265 22:18:40.360315 CS Dly: 10 (0~41)
8266 22:18:40.363328 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8267 22:18:40.366504 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8268 22:18:40.366587 ==
8269 22:18:40.369993 Dram Type= 6, Freq= 0, CH_1, rank 1
8270 22:18:40.373466 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8271 22:18:40.376498 ==
8272 22:18:40.380096 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8273 22:18:40.382949 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8274 22:18:40.389864 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8275 22:18:40.396487 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8276 22:18:40.403613 [CA 0] Center 42 (12~72) winsize 61
8277 22:18:40.407244 [CA 1] Center 42 (12~72) winsize 61
8278 22:18:40.410353 [CA 2] Center 38 (9~68) winsize 60
8279 22:18:40.413890 [CA 3] Center 38 (8~68) winsize 61
8280 22:18:40.417657 [CA 4] Center 38 (8~69) winsize 62
8281 22:18:40.420584 [CA 5] Center 36 (7~66) winsize 60
8282 22:18:40.420666
8283 22:18:40.423750 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8284 22:18:40.423833
8285 22:18:40.427081 [CATrainingPosCal] consider 2 rank data
8286 22:18:40.430307 u2DelayCellTimex100 = 285/100 ps
8287 22:18:40.433626 CA0 delay=42 (13~72),Diff = 5 PI (17 cell)
8288 22:18:40.440515 CA1 delay=42 (13~72),Diff = 5 PI (17 cell)
8289 22:18:40.443852 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8290 22:18:40.446967 CA3 delay=39 (10~68),Diff = 2 PI (6 cell)
8291 22:18:40.450315 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8292 22:18:40.453860 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8293 22:18:40.453932
8294 22:18:40.456902 CA PerBit enable=1, Macro0, CA PI delay=37
8295 22:18:40.456979
8296 22:18:40.460134 [CBTSetCACLKResult] CA Dly = 37
8297 22:18:40.463648 CS Dly: 11 (0~44)
8298 22:18:40.467292 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8299 22:18:40.470300 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8300 22:18:40.470374
8301 22:18:40.473784 ----->DramcWriteLeveling(PI) begin...
8302 22:18:40.473860 ==
8303 22:18:40.477387 Dram Type= 6, Freq= 0, CH_1, rank 0
8304 22:18:40.480377 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8305 22:18:40.484158 ==
8306 22:18:40.484233 Write leveling (Byte 0): 26 => 26
8307 22:18:40.487224 Write leveling (Byte 1): 28 => 28
8308 22:18:40.490373 DramcWriteLeveling(PI) end<-----
8309 22:18:40.490444
8310 22:18:40.490508 ==
8311 22:18:40.493855 Dram Type= 6, Freq= 0, CH_1, rank 0
8312 22:18:40.500307 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8313 22:18:40.500381 ==
8314 22:18:40.500442 [Gating] SW mode calibration
8315 22:18:40.510366 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8316 22:18:40.513618 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8317 22:18:40.520223 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8318 22:18:40.523289 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8319 22:18:40.527028 1 4 8 | B1->B0 | 2323 2828 | 0 1 | (0 0) (0 0)
8320 22:18:40.533254 1 4 12 | B1->B0 | 3131 3434 | 0 1 | (1 1) (1 1)
8321 22:18:40.536748 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8322 22:18:40.539751 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8323 22:18:40.546513 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8324 22:18:40.549879 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8325 22:18:40.553264 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8326 22:18:40.556547 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8327 22:18:40.563160 1 5 8 | B1->B0 | 3434 3232 | 0 0 | (0 1) (0 1)
8328 22:18:40.566303 1 5 12 | B1->B0 | 2929 2323 | 0 0 | (1 0) (0 0)
8329 22:18:40.570061 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8330 22:18:40.576598 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8331 22:18:40.579518 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8332 22:18:40.583262 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8333 22:18:40.589930 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8334 22:18:40.592928 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8335 22:18:40.596366 1 6 8 | B1->B0 | 2828 3c3c | 0 1 | (1 1) (0 0)
8336 22:18:40.602939 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8337 22:18:40.605892 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8338 22:18:40.609643 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8339 22:18:40.616184 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8340 22:18:40.619791 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8341 22:18:40.623172 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8342 22:18:40.629573 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8343 22:18:40.633101 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8344 22:18:40.636172 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8345 22:18:40.642690 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8346 22:18:40.645941 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8347 22:18:40.649285 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8348 22:18:40.656109 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8349 22:18:40.659513 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8350 22:18:40.662743 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8351 22:18:40.669691 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8352 22:18:40.672835 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8353 22:18:40.676426 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8354 22:18:40.682611 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8355 22:18:40.686207 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8356 22:18:40.689197 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8357 22:18:40.692615 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8358 22:18:40.699235 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8359 22:18:40.702845 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8360 22:18:40.705830 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8361 22:18:40.712818 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8362 22:18:40.716538 Total UI for P1: 0, mck2ui 16
8363 22:18:40.719141 best dqsien dly found for B0: ( 1, 9, 10)
8364 22:18:40.722729 Total UI for P1: 0, mck2ui 16
8365 22:18:40.726228 best dqsien dly found for B1: ( 1, 9, 10)
8366 22:18:40.729194 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8367 22:18:40.732638 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8368 22:18:40.732709
8369 22:18:40.735666 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8370 22:18:40.738974 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8371 22:18:40.742330 [Gating] SW calibration Done
8372 22:18:40.742400 ==
8373 22:18:40.745500 Dram Type= 6, Freq= 0, CH_1, rank 0
8374 22:18:40.749107 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8375 22:18:40.749196 ==
8376 22:18:40.752382 RX Vref Scan: 0
8377 22:18:40.752452
8378 22:18:40.755740 RX Vref 0 -> 0, step: 1
8379 22:18:40.755805
8380 22:18:40.755868 RX Delay 0 -> 252, step: 8
8381 22:18:40.762174 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8382 22:18:40.765763 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8383 22:18:40.769294 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8384 22:18:40.772376 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8385 22:18:40.775633 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8386 22:18:40.782071 iDelay=200, Bit 5, Center 151 (104 ~ 199) 96
8387 22:18:40.785703 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8388 22:18:40.788660 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8389 22:18:40.792265 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8390 22:18:40.795398 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8391 22:18:40.798962 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8392 22:18:40.805400 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8393 22:18:40.808419 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8394 22:18:40.811949 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
8395 22:18:40.815412 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8396 22:18:40.822091 iDelay=200, Bit 15, Center 143 (96 ~ 191) 96
8397 22:18:40.822168 ==
8398 22:18:40.825474 Dram Type= 6, Freq= 0, CH_1, rank 0
8399 22:18:40.828543 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8400 22:18:40.828649 ==
8401 22:18:40.828741 DQS Delay:
8402 22:18:40.831950 DQS0 = 0, DQS1 = 0
8403 22:18:40.832050 DQM Delay:
8404 22:18:40.835520 DQM0 = 137, DQM1 = 132
8405 22:18:40.835622 DQ Delay:
8406 22:18:40.838469 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8407 22:18:40.842361 DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135
8408 22:18:40.845278 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8409 22:18:40.849088 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =143
8410 22:18:40.849185
8411 22:18:40.849274
8412 22:18:40.849369 ==
8413 22:18:40.852244 Dram Type= 6, Freq= 0, CH_1, rank 0
8414 22:18:40.858947 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8415 22:18:40.859026 ==
8416 22:18:40.859091
8417 22:18:40.859152
8418 22:18:40.861749 TX Vref Scan disable
8419 22:18:40.861817 == TX Byte 0 ==
8420 22:18:40.865175 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8421 22:18:40.871833 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8422 22:18:40.871933 == TX Byte 1 ==
8423 22:18:40.875062 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8424 22:18:40.881982 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8425 22:18:40.882067 ==
8426 22:18:40.885114 Dram Type= 6, Freq= 0, CH_1, rank 0
8427 22:18:40.888509 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8428 22:18:40.888579 ==
8429 22:18:40.901117
8430 22:18:40.904242 TX Vref early break, caculate TX vref
8431 22:18:40.907757 TX Vref=16, minBit 11, minWin=22, winSum=370
8432 22:18:40.911492 TX Vref=18, minBit 0, minWin=23, winSum=382
8433 22:18:40.914505 TX Vref=20, minBit 0, minWin=24, winSum=390
8434 22:18:40.917723 TX Vref=22, minBit 0, minWin=24, winSum=402
8435 22:18:40.921154 TX Vref=24, minBit 0, minWin=25, winSum=413
8436 22:18:40.927704 TX Vref=26, minBit 0, minWin=25, winSum=421
8437 22:18:40.930964 TX Vref=28, minBit 0, minWin=25, winSum=423
8438 22:18:40.934511 TX Vref=30, minBit 0, minWin=25, winSum=416
8439 22:18:40.937921 TX Vref=32, minBit 6, minWin=24, winSum=411
8440 22:18:40.940789 TX Vref=34, minBit 6, minWin=23, winSum=394
8441 22:18:40.948085 [TxChooseVref] Worse bit 0, Min win 25, Win sum 423, Final Vref 28
8442 22:18:40.948183
8443 22:18:40.950804 Final TX Range 0 Vref 28
8444 22:18:40.950887
8445 22:18:40.950952 ==
8446 22:18:40.954434 Dram Type= 6, Freq= 0, CH_1, rank 0
8447 22:18:40.957550 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8448 22:18:40.957647 ==
8449 22:18:40.957712
8450 22:18:40.957773
8451 22:18:40.960906 TX Vref Scan disable
8452 22:18:40.967910 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8453 22:18:40.967992 == TX Byte 0 ==
8454 22:18:40.971570 u2DelayCellOfst[0]=17 cells (5 PI)
8455 22:18:40.974574 u2DelayCellOfst[1]=10 cells (3 PI)
8456 22:18:40.978125 u2DelayCellOfst[2]=0 cells (0 PI)
8457 22:18:40.981543 u2DelayCellOfst[3]=3 cells (1 PI)
8458 22:18:40.984810 u2DelayCellOfst[4]=6 cells (2 PI)
8459 22:18:40.984891 u2DelayCellOfst[5]=17 cells (5 PI)
8460 22:18:40.987903 u2DelayCellOfst[6]=20 cells (6 PI)
8461 22:18:40.991250 u2DelayCellOfst[7]=3 cells (1 PI)
8462 22:18:40.998294 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8463 22:18:41.001280 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8464 22:18:41.001362 == TX Byte 1 ==
8465 22:18:41.004695 u2DelayCellOfst[8]=0 cells (0 PI)
8466 22:18:41.008250 u2DelayCellOfst[9]=0 cells (0 PI)
8467 22:18:41.011271 u2DelayCellOfst[10]=10 cells (3 PI)
8468 22:18:41.014622 u2DelayCellOfst[11]=3 cells (1 PI)
8469 22:18:41.017700 u2DelayCellOfst[12]=13 cells (4 PI)
8470 22:18:41.020968 u2DelayCellOfst[13]=17 cells (5 PI)
8471 22:18:41.024816 u2DelayCellOfst[14]=17 cells (5 PI)
8472 22:18:41.027996 u2DelayCellOfst[15]=17 cells (5 PI)
8473 22:18:41.031452 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8474 22:18:41.035010 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8475 22:18:41.037856 DramC Write-DBI on
8476 22:18:41.037943 ==
8477 22:18:41.041409 Dram Type= 6, Freq= 0, CH_1, rank 0
8478 22:18:41.044846 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8479 22:18:41.044928 ==
8480 22:18:41.044992
8481 22:18:41.045051
8482 22:18:41.047765 TX Vref Scan disable
8483 22:18:41.051531 == TX Byte 0 ==
8484 22:18:41.054586 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8485 22:18:41.057789 == TX Byte 1 ==
8486 22:18:41.061171 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8487 22:18:41.061252 DramC Write-DBI off
8488 22:18:41.061317
8489 22:18:41.064714 [DATLAT]
8490 22:18:41.064796 Freq=1600, CH1 RK0
8491 22:18:41.064860
8492 22:18:41.067545 DATLAT Default: 0xf
8493 22:18:41.067644 0, 0xFFFF, sum = 0
8494 22:18:41.070864 1, 0xFFFF, sum = 0
8495 22:18:41.070947 2, 0xFFFF, sum = 0
8496 22:18:41.074141 3, 0xFFFF, sum = 0
8497 22:18:41.074224 4, 0xFFFF, sum = 0
8498 22:18:41.077740 5, 0xFFFF, sum = 0
8499 22:18:41.077823 6, 0xFFFF, sum = 0
8500 22:18:41.081116 7, 0xFFFF, sum = 0
8501 22:18:41.081199 8, 0xFFFF, sum = 0
8502 22:18:41.084490 9, 0xFFFF, sum = 0
8503 22:18:41.084573 10, 0xFFFF, sum = 0
8504 22:18:41.088114 11, 0xFFFF, sum = 0
8505 22:18:41.090822 12, 0xFFFF, sum = 0
8506 22:18:41.090922 13, 0xFFFF, sum = 0
8507 22:18:41.094432 14, 0x0, sum = 1
8508 22:18:41.094516 15, 0x0, sum = 2
8509 22:18:41.094581 16, 0x0, sum = 3
8510 22:18:41.097855 17, 0x0, sum = 4
8511 22:18:41.097937 best_step = 15
8512 22:18:41.098002
8513 22:18:41.100787 ==
8514 22:18:41.100868 Dram Type= 6, Freq= 0, CH_1, rank 0
8515 22:18:41.107701 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8516 22:18:41.107783 ==
8517 22:18:41.107848 RX Vref Scan: 1
8518 22:18:41.107909
8519 22:18:41.111247 Set Vref Range= 24 -> 127
8520 22:18:41.111329
8521 22:18:41.114303 RX Vref 24 -> 127, step: 1
8522 22:18:41.114384
8523 22:18:41.117667 RX Delay 27 -> 252, step: 4
8524 22:18:41.117748
8525 22:18:41.121022 Set Vref, RX VrefLevel [Byte0]: 24
8526 22:18:41.123944 [Byte1]: 24
8527 22:18:41.124026
8528 22:18:41.127705 Set Vref, RX VrefLevel [Byte0]: 25
8529 22:18:41.130801 [Byte1]: 25
8530 22:18:41.130883
8531 22:18:41.134017 Set Vref, RX VrefLevel [Byte0]: 26
8532 22:18:41.137810 [Byte1]: 26
8533 22:18:41.137892
8534 22:18:41.140825 Set Vref, RX VrefLevel [Byte0]: 27
8535 22:18:41.143928 [Byte1]: 27
8536 22:18:41.148197
8537 22:18:41.148278 Set Vref, RX VrefLevel [Byte0]: 28
8538 22:18:41.151476 [Byte1]: 28
8539 22:18:41.155595
8540 22:18:41.155677 Set Vref, RX VrefLevel [Byte0]: 29
8541 22:18:41.159003 [Byte1]: 29
8542 22:18:41.163227
8543 22:18:41.163309 Set Vref, RX VrefLevel [Byte0]: 30
8544 22:18:41.166427 [Byte1]: 30
8545 22:18:41.171056
8546 22:18:41.171138 Set Vref, RX VrefLevel [Byte0]: 31
8547 22:18:41.173885 [Byte1]: 31
8548 22:18:41.178351
8549 22:18:41.178443 Set Vref, RX VrefLevel [Byte0]: 32
8550 22:18:41.181265 [Byte1]: 32
8551 22:18:41.185710
8552 22:18:41.185792 Set Vref, RX VrefLevel [Byte0]: 33
8553 22:18:41.189006 [Byte1]: 33
8554 22:18:41.193107
8555 22:18:41.193188 Set Vref, RX VrefLevel [Byte0]: 34
8556 22:18:41.196714 [Byte1]: 34
8557 22:18:41.201212
8558 22:18:41.201294 Set Vref, RX VrefLevel [Byte0]: 35
8559 22:18:41.204249 [Byte1]: 35
8560 22:18:41.208492
8561 22:18:41.208574 Set Vref, RX VrefLevel [Byte0]: 36
8562 22:18:41.212124 [Byte1]: 36
8563 22:18:41.215628
8564 22:18:41.215709 Set Vref, RX VrefLevel [Byte0]: 37
8565 22:18:41.219253 [Byte1]: 37
8566 22:18:41.223741
8567 22:18:41.223822 Set Vref, RX VrefLevel [Byte0]: 38
8568 22:18:41.227113 [Byte1]: 38
8569 22:18:41.230780
8570 22:18:41.230861 Set Vref, RX VrefLevel [Byte0]: 39
8571 22:18:41.234626 [Byte1]: 39
8572 22:18:41.238441
8573 22:18:41.238523 Set Vref, RX VrefLevel [Byte0]: 40
8574 22:18:41.241919 [Byte1]: 40
8575 22:18:41.246126
8576 22:18:41.246208 Set Vref, RX VrefLevel [Byte0]: 41
8577 22:18:41.249118 [Byte1]: 41
8578 22:18:41.253445
8579 22:18:41.253564 Set Vref, RX VrefLevel [Byte0]: 42
8580 22:18:41.256945 [Byte1]: 42
8581 22:18:41.261363
8582 22:18:41.261444 Set Vref, RX VrefLevel [Byte0]: 43
8583 22:18:41.264248 [Byte1]: 43
8584 22:18:41.268808
8585 22:18:41.268889 Set Vref, RX VrefLevel [Byte0]: 44
8586 22:18:41.271811 [Byte1]: 44
8587 22:18:41.275965
8588 22:18:41.276047 Set Vref, RX VrefLevel [Byte0]: 45
8589 22:18:41.279364 [Byte1]: 45
8590 22:18:41.283792
8591 22:18:41.283874 Set Vref, RX VrefLevel [Byte0]: 46
8592 22:18:41.287305 [Byte1]: 46
8593 22:18:41.291277
8594 22:18:41.291358 Set Vref, RX VrefLevel [Byte0]: 47
8595 22:18:41.294673 [Byte1]: 47
8596 22:18:41.298517
8597 22:18:41.298599 Set Vref, RX VrefLevel [Byte0]: 48
8598 22:18:41.301857 [Byte1]: 48
8599 22:18:41.306233
8600 22:18:41.306315 Set Vref, RX VrefLevel [Byte0]: 49
8601 22:18:41.309752 [Byte1]: 49
8602 22:18:41.313692
8603 22:18:41.313773 Set Vref, RX VrefLevel [Byte0]: 50
8604 22:18:41.317247 [Byte1]: 50
8605 22:18:41.321530
8606 22:18:41.321626 Set Vref, RX VrefLevel [Byte0]: 51
8607 22:18:41.324443 [Byte1]: 51
8608 22:18:41.328680
8609 22:18:41.328762 Set Vref, RX VrefLevel [Byte0]: 52
8610 22:18:41.332416 [Byte1]: 52
8611 22:18:41.336353
8612 22:18:41.336435 Set Vref, RX VrefLevel [Byte0]: 53
8613 22:18:41.339881 [Byte1]: 53
8614 22:18:41.343994
8615 22:18:41.344075 Set Vref, RX VrefLevel [Byte0]: 54
8616 22:18:41.347277 [Byte1]: 54
8617 22:18:41.351979
8618 22:18:41.352060 Set Vref, RX VrefLevel [Byte0]: 55
8619 22:18:41.355031 [Byte1]: 55
8620 22:18:41.359107
8621 22:18:41.359189 Set Vref, RX VrefLevel [Byte0]: 56
8622 22:18:41.362181 [Byte1]: 56
8623 22:18:41.367116
8624 22:18:41.367198 Set Vref, RX VrefLevel [Byte0]: 57
8625 22:18:41.370159 [Byte1]: 57
8626 22:18:41.374322
8627 22:18:41.374404 Set Vref, RX VrefLevel [Byte0]: 58
8628 22:18:41.377627 [Byte1]: 58
8629 22:18:41.381436
8630 22:18:41.381540 Set Vref, RX VrefLevel [Byte0]: 59
8631 22:18:41.385235 [Byte1]: 59
8632 22:18:41.389305
8633 22:18:41.389387 Set Vref, RX VrefLevel [Byte0]: 60
8634 22:18:41.392637 [Byte1]: 60
8635 22:18:41.396393
8636 22:18:41.396465 Set Vref, RX VrefLevel [Byte0]: 61
8637 22:18:41.400325 [Byte1]: 61
8638 22:18:41.404154
8639 22:18:41.404224 Set Vref, RX VrefLevel [Byte0]: 62
8640 22:18:41.407646 [Byte1]: 62
8641 22:18:41.412243
8642 22:18:41.412314 Set Vref, RX VrefLevel [Byte0]: 63
8643 22:18:41.414966 [Byte1]: 63
8644 22:18:41.419512
8645 22:18:41.419657 Set Vref, RX VrefLevel [Byte0]: 64
8646 22:18:41.422472 [Byte1]: 64
8647 22:18:41.426799
8648 22:18:41.426868 Set Vref, RX VrefLevel [Byte0]: 65
8649 22:18:41.430368 [Byte1]: 65
8650 22:18:41.434515
8651 22:18:41.434585 Set Vref, RX VrefLevel [Byte0]: 66
8652 22:18:41.437467 [Byte1]: 66
8653 22:18:41.441968
8654 22:18:41.442035 Set Vref, RX VrefLevel [Byte0]: 67
8655 22:18:41.445441 [Byte1]: 67
8656 22:18:41.449088
8657 22:18:41.449157 Set Vref, RX VrefLevel [Byte0]: 68
8658 22:18:41.452641 [Byte1]: 68
8659 22:18:41.457089
8660 22:18:41.457157 Set Vref, RX VrefLevel [Byte0]: 69
8661 22:18:41.460250 [Byte1]: 69
8662 22:18:41.464456
8663 22:18:41.464529 Set Vref, RX VrefLevel [Byte0]: 70
8664 22:18:41.468028 [Byte1]: 70
8665 22:18:41.472295
8666 22:18:41.472363 Set Vref, RX VrefLevel [Byte0]: 71
8667 22:18:41.475298 [Byte1]: 71
8668 22:18:41.479726
8669 22:18:41.479808 Set Vref, RX VrefLevel [Byte0]: 72
8670 22:18:41.482709 [Byte1]: 72
8671 22:18:41.486928
8672 22:18:41.487009 Final RX Vref Byte 0 = 58 to rank0
8673 22:18:41.490382 Final RX Vref Byte 1 = 58 to rank0
8674 22:18:41.493718 Final RX Vref Byte 0 = 58 to rank1
8675 22:18:41.496777 Final RX Vref Byte 1 = 58 to rank1==
8676 22:18:41.500001 Dram Type= 6, Freq= 0, CH_1, rank 0
8677 22:18:41.507270 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8678 22:18:41.507353 ==
8679 22:18:41.507417 DQS Delay:
8680 22:18:41.507476 DQS0 = 0, DQS1 = 0
8681 22:18:41.510436 DQM Delay:
8682 22:18:41.510547 DQM0 = 134, DQM1 = 131
8683 22:18:41.513911 DQ Delay:
8684 22:18:41.517295 DQ0 =140, DQ1 =128, DQ2 =122, DQ3 =130
8685 22:18:41.520504 DQ4 =134, DQ5 =144, DQ6 =142, DQ7 =132
8686 22:18:41.523683 DQ8 =116, DQ9 =122, DQ10 =132, DQ11 =122
8687 22:18:41.527062 DQ12 =140, DQ13 =140, DQ14 =138, DQ15 =140
8688 22:18:41.527170
8689 22:18:41.527262
8690 22:18:41.527349
8691 22:18:41.530505 [DramC_TX_OE_Calibration] TA2
8692 22:18:41.533909 Original DQ_B0 (3 6) =30, OEN = 27
8693 22:18:41.537002 Original DQ_B1 (3 6) =30, OEN = 27
8694 22:18:41.540105 24, 0x0, End_B0=24 End_B1=24
8695 22:18:41.540189 25, 0x0, End_B0=25 End_B1=25
8696 22:18:41.543841 26, 0x0, End_B0=26 End_B1=26
8697 22:18:41.546787 27, 0x0, End_B0=27 End_B1=27
8698 22:18:41.550555 28, 0x0, End_B0=28 End_B1=28
8699 22:18:41.550638 29, 0x0, End_B0=29 End_B1=29
8700 22:18:41.553452 30, 0x0, End_B0=30 End_B1=30
8701 22:18:41.556948 31, 0x4141, End_B0=30 End_B1=30
8702 22:18:41.560010 Byte0 end_step=30 best_step=27
8703 22:18:41.563568 Byte1 end_step=30 best_step=27
8704 22:18:41.567045 Byte0 TX OE(2T, 0.5T) = (3, 3)
8705 22:18:41.567131 Byte1 TX OE(2T, 0.5T) = (3, 3)
8706 22:18:41.570249
8707 22:18:41.570330
8708 22:18:41.576675 [DQSOSCAuto] RK0, (LSB)MR18= 0x1725, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
8709 22:18:41.580293 CH1 RK0: MR19=303, MR18=1725
8710 22:18:41.586455 CH1_RK0: MR19=0x303, MR18=0x1725, DQSOSC=391, MR23=63, INC=24, DEC=16
8711 22:18:41.586537
8712 22:18:41.590163 ----->DramcWriteLeveling(PI) begin...
8713 22:18:41.590246 ==
8714 22:18:41.593661 Dram Type= 6, Freq= 0, CH_1, rank 1
8715 22:18:41.597007 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8716 22:18:41.597089 ==
8717 22:18:41.600194 Write leveling (Byte 0): 27 => 27
8718 22:18:41.603432 Write leveling (Byte 1): 30 => 30
8719 22:18:41.606845 DramcWriteLeveling(PI) end<-----
8720 22:18:41.606927
8721 22:18:41.606992 ==
8722 22:18:41.609789 Dram Type= 6, Freq= 0, CH_1, rank 1
8723 22:18:41.613134 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8724 22:18:41.613246 ==
8725 22:18:41.616837 [Gating] SW mode calibration
8726 22:18:41.623317 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8727 22:18:41.630136 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8728 22:18:41.633367 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8729 22:18:41.636310 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8730 22:18:41.643337 1 4 8 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
8731 22:18:41.646388 1 4 12 | B1->B0 | 3434 302f | 1 1 | (1 1) (0 0)
8732 22:18:41.650053 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8733 22:18:41.656136 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8734 22:18:41.659735 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8735 22:18:41.663245 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8736 22:18:41.669458 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8737 22:18:41.672984 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8738 22:18:41.676356 1 5 8 | B1->B0 | 3232 3434 | 1 1 | (0 0) (1 0)
8739 22:18:41.682792 1 5 12 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
8740 22:18:41.686243 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8741 22:18:41.689820 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8742 22:18:41.696208 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8743 22:18:41.699725 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8744 22:18:41.702555 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8745 22:18:41.709125 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8746 22:18:41.712503 1 6 8 | B1->B0 | 2c2c 2323 | 1 0 | (0 0) (0 0)
8747 22:18:41.715909 1 6 12 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
8748 22:18:41.722720 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8749 22:18:41.726066 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8750 22:18:41.729061 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8751 22:18:41.735667 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8752 22:18:41.739126 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8753 22:18:41.742496 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8754 22:18:41.749501 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8755 22:18:41.752657 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8756 22:18:41.756246 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8757 22:18:41.762236 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8758 22:18:41.765687 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8759 22:18:41.769138 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8760 22:18:41.776010 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8761 22:18:41.779145 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8762 22:18:41.781995 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8763 22:18:41.788969 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8764 22:18:41.792505 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8765 22:18:41.795447 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8766 22:18:41.802169 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8767 22:18:41.805087 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8768 22:18:41.808522 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8769 22:18:41.815424 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8770 22:18:41.818676 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8771 22:18:41.822238 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8772 22:18:41.825080 Total UI for P1: 0, mck2ui 16
8773 22:18:41.828446 best dqsien dly found for B1: ( 1, 9, 6)
8774 22:18:41.835184 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8775 22:18:41.838361 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8776 22:18:41.841903 Total UI for P1: 0, mck2ui 16
8777 22:18:41.845263 best dqsien dly found for B0: ( 1, 9, 12)
8778 22:18:41.847989 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8779 22:18:41.851431 best DQS1 dly(MCK, UI, PI) = (1, 9, 6)
8780 22:18:41.851513
8781 22:18:41.855031 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8782 22:18:41.858116 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 6)
8783 22:18:41.861750 [Gating] SW calibration Done
8784 22:18:41.861831 ==
8785 22:18:41.864613 Dram Type= 6, Freq= 0, CH_1, rank 1
8786 22:18:41.868162 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8787 22:18:41.868244 ==
8788 22:18:41.871701 RX Vref Scan: 0
8789 22:18:41.871782
8790 22:18:41.875136 RX Vref 0 -> 0, step: 1
8791 22:18:41.875218
8792 22:18:41.875283 RX Delay 0 -> 252, step: 8
8793 22:18:41.881304 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8794 22:18:41.884654 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8795 22:18:41.888327 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8796 22:18:41.891608 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8797 22:18:41.894598 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8798 22:18:41.901195 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8799 22:18:41.904828 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8800 22:18:41.907715 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8801 22:18:41.911318 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8802 22:18:41.914825 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8803 22:18:41.921084 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8804 22:18:41.924327 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8805 22:18:41.927741 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8806 22:18:41.931592 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8807 22:18:41.934772 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8808 22:18:41.941129 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8809 22:18:41.941211 ==
8810 22:18:41.944426 Dram Type= 6, Freq= 0, CH_1, rank 1
8811 22:18:41.948006 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8812 22:18:41.948088 ==
8813 22:18:41.948153 DQS Delay:
8814 22:18:41.951158 DQS0 = 0, DQS1 = 0
8815 22:18:41.951240 DQM Delay:
8816 22:18:41.954935 DQM0 = 136, DQM1 = 133
8817 22:18:41.955042 DQ Delay:
8818 22:18:41.957855 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8819 22:18:41.961530 DQ4 =131, DQ5 =151, DQ6 =143, DQ7 =135
8820 22:18:41.964586 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =127
8821 22:18:41.968577 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8822 22:18:41.968658
8823 22:18:41.971077
8824 22:18:41.971158 ==
8825 22:18:41.974706 Dram Type= 6, Freq= 0, CH_1, rank 1
8826 22:18:41.977911 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8827 22:18:41.977994 ==
8828 22:18:41.978058
8829 22:18:41.978117
8830 22:18:41.981528 TX Vref Scan disable
8831 22:18:41.981624 == TX Byte 0 ==
8832 22:18:41.987848 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8833 22:18:41.991156 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8834 22:18:41.991237 == TX Byte 1 ==
8835 22:18:41.998005 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8836 22:18:42.001201 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8837 22:18:42.001283 ==
8838 22:18:42.004227 Dram Type= 6, Freq= 0, CH_1, rank 1
8839 22:18:42.007966 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8840 22:18:42.008048 ==
8841 22:18:42.022183
8842 22:18:42.025568 TX Vref early break, caculate TX vref
8843 22:18:42.028548 TX Vref=16, minBit 1, minWin=23, winSum=383
8844 22:18:42.032115 TX Vref=18, minBit 1, minWin=23, winSum=387
8845 22:18:42.035307 TX Vref=20, minBit 0, minWin=24, winSum=398
8846 22:18:42.038543 TX Vref=22, minBit 0, minWin=25, winSum=410
8847 22:18:42.042114 TX Vref=24, minBit 0, minWin=25, winSum=416
8848 22:18:42.048596 TX Vref=26, minBit 0, minWin=25, winSum=421
8849 22:18:42.052094 TX Vref=28, minBit 0, minWin=25, winSum=418
8850 22:18:42.055236 TX Vref=30, minBit 15, minWin=24, winSum=418
8851 22:18:42.058745 TX Vref=32, minBit 0, minWin=24, winSum=415
8852 22:18:42.061868 TX Vref=34, minBit 0, minWin=24, winSum=401
8853 22:18:42.065280 TX Vref=36, minBit 14, minWin=23, winSum=389
8854 22:18:42.071973 [TxChooseVref] Worse bit 0, Min win 25, Win sum 421, Final Vref 26
8855 22:18:42.072059
8856 22:18:42.075506 Final TX Range 0 Vref 26
8857 22:18:42.075589
8858 22:18:42.075653 ==
8859 22:18:42.078461 Dram Type= 6, Freq= 0, CH_1, rank 1
8860 22:18:42.081655 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8861 22:18:42.081738 ==
8862 22:18:42.081802
8863 22:18:42.081862
8864 22:18:42.085347 TX Vref Scan disable
8865 22:18:42.091644 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8866 22:18:42.091727 == TX Byte 0 ==
8867 22:18:42.095215 u2DelayCellOfst[0]=17 cells (5 PI)
8868 22:18:42.098226 u2DelayCellOfst[1]=10 cells (3 PI)
8869 22:18:42.101876 u2DelayCellOfst[2]=0 cells (0 PI)
8870 22:18:42.105032 u2DelayCellOfst[3]=6 cells (2 PI)
8871 22:18:42.108575 u2DelayCellOfst[4]=6 cells (2 PI)
8872 22:18:42.111757 u2DelayCellOfst[5]=17 cells (5 PI)
8873 22:18:42.115105 u2DelayCellOfst[6]=17 cells (5 PI)
8874 22:18:42.118158 u2DelayCellOfst[7]=6 cells (2 PI)
8875 22:18:42.121097 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8876 22:18:42.124554 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8877 22:18:42.128150 == TX Byte 1 ==
8878 22:18:42.131086 u2DelayCellOfst[8]=0 cells (0 PI)
8879 22:18:42.134961 u2DelayCellOfst[9]=3 cells (1 PI)
8880 22:18:42.137825 u2DelayCellOfst[10]=10 cells (3 PI)
8881 22:18:42.137958 u2DelayCellOfst[11]=6 cells (2 PI)
8882 22:18:42.141131 u2DelayCellOfst[12]=13 cells (4 PI)
8883 22:18:42.144483 u2DelayCellOfst[13]=17 cells (5 PI)
8884 22:18:42.147972 u2DelayCellOfst[14]=17 cells (5 PI)
8885 22:18:42.151331 u2DelayCellOfst[15]=20 cells (6 PI)
8886 22:18:42.158359 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8887 22:18:42.161634 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8888 22:18:42.161757 DramC Write-DBI on
8889 22:18:42.161894 ==
8890 22:18:42.164536 Dram Type= 6, Freq= 0, CH_1, rank 1
8891 22:18:42.170925 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8892 22:18:42.171008 ==
8893 22:18:42.171074
8894 22:18:42.171134
8895 22:18:42.171191 TX Vref Scan disable
8896 22:18:42.175095 == TX Byte 0 ==
8897 22:18:42.178562 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8898 22:18:42.181974 == TX Byte 1 ==
8899 22:18:42.185689 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8900 22:18:42.188583 DramC Write-DBI off
8901 22:18:42.188665
8902 22:18:42.188729 [DATLAT]
8903 22:18:42.188789 Freq=1600, CH1 RK1
8904 22:18:42.188847
8905 22:18:42.191663 DATLAT Default: 0xf
8906 22:18:42.191744 0, 0xFFFF, sum = 0
8907 22:18:42.195049 1, 0xFFFF, sum = 0
8908 22:18:42.195134 2, 0xFFFF, sum = 0
8909 22:18:42.198775 3, 0xFFFF, sum = 0
8910 22:18:42.202266 4, 0xFFFF, sum = 0
8911 22:18:42.202349 5, 0xFFFF, sum = 0
8912 22:18:42.205046 6, 0xFFFF, sum = 0
8913 22:18:42.205130 7, 0xFFFF, sum = 0
8914 22:18:42.208628 8, 0xFFFF, sum = 0
8915 22:18:42.208711 9, 0xFFFF, sum = 0
8916 22:18:42.211867 10, 0xFFFF, sum = 0
8917 22:18:42.211979 11, 0xFFFF, sum = 0
8918 22:18:42.215473 12, 0xFFFF, sum = 0
8919 22:18:42.215557 13, 0xFFFF, sum = 0
8920 22:18:42.218500 14, 0x0, sum = 1
8921 22:18:42.218584 15, 0x0, sum = 2
8922 22:18:42.222206 16, 0x0, sum = 3
8923 22:18:42.222290 17, 0x0, sum = 4
8924 22:18:42.225134 best_step = 15
8925 22:18:42.225216
8926 22:18:42.225280 ==
8927 22:18:42.228744 Dram Type= 6, Freq= 0, CH_1, rank 1
8928 22:18:42.232116 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8929 22:18:42.232199 ==
8930 22:18:42.232264 RX Vref Scan: 0
8931 22:18:42.232324
8932 22:18:42.235041 RX Vref 0 -> 0, step: 1
8933 22:18:42.235123
8934 22:18:42.238445 RX Delay 19 -> 252, step: 4
8935 22:18:42.241986 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
8936 22:18:42.248241 iDelay=195, Bit 1, Center 130 (79 ~ 182) 104
8937 22:18:42.251655 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
8938 22:18:42.255527 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
8939 22:18:42.258324 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
8940 22:18:42.261762 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
8941 22:18:42.265000 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
8942 22:18:42.271589 iDelay=195, Bit 7, Center 134 (83 ~ 186) 104
8943 22:18:42.275728 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8944 22:18:42.278391 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8945 22:18:42.281730 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
8946 22:18:42.285261 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
8947 22:18:42.291696 iDelay=195, Bit 12, Center 140 (87 ~ 194) 108
8948 22:18:42.295249 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
8949 22:18:42.298205 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
8950 22:18:42.301676 iDelay=195, Bit 15, Center 140 (91 ~ 190) 100
8951 22:18:42.301788 ==
8952 22:18:42.305186 Dram Type= 6, Freq= 0, CH_1, rank 1
8953 22:18:42.311822 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8954 22:18:42.311904 ==
8955 22:18:42.311969 DQS Delay:
8956 22:18:42.314947 DQS0 = 0, DQS1 = 0
8957 22:18:42.315030 DQM Delay:
8958 22:18:42.318256 DQM0 = 134, DQM1 = 130
8959 22:18:42.318338 DQ Delay:
8960 22:18:42.321733 DQ0 =138, DQ1 =130, DQ2 =122, DQ3 =130
8961 22:18:42.324686 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =134
8962 22:18:42.328382 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =124
8963 22:18:42.331200 DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =140
8964 22:18:42.331282
8965 22:18:42.331347
8966 22:18:42.331407
8967 22:18:42.334419 [DramC_TX_OE_Calibration] TA2
8968 22:18:42.338025 Original DQ_B0 (3 6) =30, OEN = 27
8969 22:18:42.341238 Original DQ_B1 (3 6) =30, OEN = 27
8970 22:18:42.344804 24, 0x0, End_B0=24 End_B1=24
8971 22:18:42.348331 25, 0x0, End_B0=25 End_B1=25
8972 22:18:42.348414 26, 0x0, End_B0=26 End_B1=26
8973 22:18:42.351280 27, 0x0, End_B0=27 End_B1=27
8974 22:18:42.354708 28, 0x0, End_B0=28 End_B1=28
8975 22:18:42.358008 29, 0x0, End_B0=29 End_B1=29
8976 22:18:42.358101 30, 0x0, End_B0=30 End_B1=30
8977 22:18:42.361636 31, 0x5151, End_B0=30 End_B1=30
8978 22:18:42.365010 Byte0 end_step=30 best_step=27
8979 22:18:42.367869 Byte1 end_step=30 best_step=27
8980 22:18:42.371014 Byte0 TX OE(2T, 0.5T) = (3, 3)
8981 22:18:42.374432 Byte1 TX OE(2T, 0.5T) = (3, 3)
8982 22:18:42.374514
8983 22:18:42.374578
8984 22:18:42.381326 [DQSOSCAuto] RK1, (LSB)MR18= 0x2207, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 392 ps
8985 22:18:42.384501 CH1 RK1: MR19=303, MR18=2207
8986 22:18:42.391208 CH1_RK1: MR19=0x303, MR18=0x2207, DQSOSC=392, MR23=63, INC=24, DEC=16
8987 22:18:42.394445 [RxdqsGatingPostProcess] freq 1600
8988 22:18:42.398148 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8989 22:18:42.401235 best DQS0 dly(2T, 0.5T) = (1, 1)
8990 22:18:42.404592 best DQS1 dly(2T, 0.5T) = (1, 1)
8991 22:18:42.407996 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8992 22:18:42.411077 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8993 22:18:42.414583 best DQS0 dly(2T, 0.5T) = (1, 1)
8994 22:18:42.418198 best DQS1 dly(2T, 0.5T) = (1, 1)
8995 22:18:42.420973 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8996 22:18:42.424498 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8997 22:18:42.427911 Pre-setting of DQS Precalculation
8998 22:18:42.430832 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8999 22:18:42.437482 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9000 22:18:42.447787 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9001 22:18:42.447870
9002 22:18:42.447934
9003 22:18:42.451078 [Calibration Summary] 3200 Mbps
9004 22:18:42.451160 CH 0, Rank 0
9005 22:18:42.454559 SW Impedance : PASS
9006 22:18:42.454671 DUTY Scan : NO K
9007 22:18:42.457530 ZQ Calibration : PASS
9008 22:18:42.457625 Jitter Meter : NO K
9009 22:18:42.460936 CBT Training : PASS
9010 22:18:42.464151 Write leveling : PASS
9011 22:18:42.464233 RX DQS gating : PASS
9012 22:18:42.467491 RX DQ/DQS(RDDQC) : PASS
9013 22:18:42.470794 TX DQ/DQS : PASS
9014 22:18:42.470909 RX DATLAT : PASS
9015 22:18:42.474103 RX DQ/DQS(Engine): PASS
9016 22:18:42.477548 TX OE : PASS
9017 22:18:42.477657 All Pass.
9018 22:18:42.477750
9019 22:18:42.477831 CH 0, Rank 1
9020 22:18:42.481168 SW Impedance : PASS
9021 22:18:42.483960 DUTY Scan : NO K
9022 22:18:42.484043 ZQ Calibration : PASS
9023 22:18:42.487289 Jitter Meter : NO K
9024 22:18:42.490708 CBT Training : PASS
9025 22:18:42.490823 Write leveling : PASS
9026 22:18:42.494073 RX DQS gating : PASS
9027 22:18:42.497414 RX DQ/DQS(RDDQC) : PASS
9028 22:18:42.497498 TX DQ/DQS : PASS
9029 22:18:42.500965 RX DATLAT : PASS
9030 22:18:42.504363 RX DQ/DQS(Engine): PASS
9031 22:18:42.504445 TX OE : PASS
9032 22:18:42.504510 All Pass.
9033 22:18:42.504571
9034 22:18:42.507376 CH 1, Rank 0
9035 22:18:42.510606 SW Impedance : PASS
9036 22:18:42.510688 DUTY Scan : NO K
9037 22:18:42.514552 ZQ Calibration : PASS
9038 22:18:42.514634 Jitter Meter : NO K
9039 22:18:42.517460 CBT Training : PASS
9040 22:18:42.520575 Write leveling : PASS
9041 22:18:42.520657 RX DQS gating : PASS
9042 22:18:42.524128 RX DQ/DQS(RDDQC) : PASS
9043 22:18:42.527589 TX DQ/DQS : PASS
9044 22:18:42.527671 RX DATLAT : PASS
9045 22:18:42.530923 RX DQ/DQS(Engine): PASS
9046 22:18:42.533744 TX OE : PASS
9047 22:18:42.533827 All Pass.
9048 22:18:42.533892
9049 22:18:42.533952 CH 1, Rank 1
9050 22:18:42.537259 SW Impedance : PASS
9051 22:18:42.540495 DUTY Scan : NO K
9052 22:18:42.540577 ZQ Calibration : PASS
9053 22:18:42.544027 Jitter Meter : NO K
9054 22:18:42.547097 CBT Training : PASS
9055 22:18:42.547179 Write leveling : PASS
9056 22:18:42.550291 RX DQS gating : PASS
9057 22:18:42.554474 RX DQ/DQS(RDDQC) : PASS
9058 22:18:42.554564 TX DQ/DQS : PASS
9059 22:18:42.557248 RX DATLAT : PASS
9060 22:18:42.557367 RX DQ/DQS(Engine): PASS
9061 22:18:42.560280 TX OE : PASS
9062 22:18:42.560362 All Pass.
9063 22:18:42.560427
9064 22:18:42.563708 DramC Write-DBI on
9065 22:18:42.567295 PER_BANK_REFRESH: Hybrid Mode
9066 22:18:42.567377 TX_TRACKING: ON
9067 22:18:42.577008 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9068 22:18:42.583768 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9069 22:18:42.593533 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9070 22:18:42.596889 [FAST_K] Save calibration result to emmc
9071 22:18:42.596972 sync common calibartion params.
9072 22:18:42.600117 sync cbt_mode0:1, 1:1
9073 22:18:42.603422 dram_init: ddr_geometry: 2
9074 22:18:42.606702 dram_init: ddr_geometry: 2
9075 22:18:42.606778 dram_init: ddr_geometry: 2
9076 22:18:42.610306 0:dram_rank_size:100000000
9077 22:18:42.613479 1:dram_rank_size:100000000
9078 22:18:42.616632 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9079 22:18:42.620290 DFS_SHUFFLE_HW_MODE: ON
9080 22:18:42.623380 dramc_set_vcore_voltage set vcore to 725000
9081 22:18:42.626842 Read voltage for 1600, 0
9082 22:18:42.626918 Vio18 = 0
9083 22:18:42.630557 Vcore = 725000
9084 22:18:42.630630 Vdram = 0
9085 22:18:42.630699 Vddq = 0
9086 22:18:42.630757 Vmddr = 0
9087 22:18:42.633591 switch to 3200 Mbps bootup
9088 22:18:42.636778 [DramcRunTimeConfig]
9089 22:18:42.636850 PHYPLL
9090 22:18:42.640322 DPM_CONTROL_AFTERK: ON
9091 22:18:42.640399 PER_BANK_REFRESH: ON
9092 22:18:42.643794 REFRESH_OVERHEAD_REDUCTION: ON
9093 22:18:42.646858 CMD_PICG_NEW_MODE: OFF
9094 22:18:42.646942 XRTWTW_NEW_MODE: ON
9095 22:18:42.650640 XRTRTR_NEW_MODE: ON
9096 22:18:42.650716 TX_TRACKING: ON
9097 22:18:42.653431 RDSEL_TRACKING: OFF
9098 22:18:42.653503 DQS Precalculation for DVFS: ON
9099 22:18:42.656617 RX_TRACKING: OFF
9100 22:18:42.656690 HW_GATING DBG: ON
9101 22:18:42.660105 ZQCS_ENABLE_LP4: ON
9102 22:18:42.663513 RX_PICG_NEW_MODE: ON
9103 22:18:42.663596 TX_PICG_NEW_MODE: ON
9104 22:18:42.666850 ENABLE_RX_DCM_DPHY: ON
9105 22:18:42.670198 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9106 22:18:42.670273 DUMMY_READ_FOR_TRACKING: OFF
9107 22:18:42.673269 !!! SPM_CONTROL_AFTERK: OFF
9108 22:18:42.676971 !!! SPM could not control APHY
9109 22:18:42.680455 IMPEDANCE_TRACKING: ON
9110 22:18:42.680537 TEMP_SENSOR: ON
9111 22:18:42.683243 HW_SAVE_FOR_SR: OFF
9112 22:18:42.686550 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9113 22:18:42.689839 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9114 22:18:42.689918 Read ODT Tracking: ON
9115 22:18:42.693281 Refresh Rate DeBounce: ON
9116 22:18:42.696548 DFS_NO_QUEUE_FLUSH: ON
9117 22:18:42.700392 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9118 22:18:42.700465 ENABLE_DFS_RUNTIME_MRW: OFF
9119 22:18:42.703182 DDR_RESERVE_NEW_MODE: ON
9120 22:18:42.706620 MR_CBT_SWITCH_FREQ: ON
9121 22:18:42.706699 =========================
9122 22:18:42.726753 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9123 22:18:42.729999 dram_init: ddr_geometry: 2
9124 22:18:42.748094 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9125 22:18:42.751165 dram_init: dram init end (result: 0)
9126 22:18:42.758190 DRAM-K: Full calibration passed in 24421 msecs
9127 22:18:42.761288 MRC: failed to locate region type 0.
9128 22:18:42.761359 DRAM rank0 size:0x100000000,
9129 22:18:42.764629 DRAM rank1 size=0x100000000
9130 22:18:42.774754 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9131 22:18:42.781260 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9132 22:18:42.787908 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9133 22:18:42.794804 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9134 22:18:42.798151 DRAM rank0 size:0x100000000,
9135 22:18:42.801388 DRAM rank1 size=0x100000000
9136 22:18:42.801465 CBMEM:
9137 22:18:42.804411 IMD: root @ 0xfffff000 254 entries.
9138 22:18:42.807711 IMD: root @ 0xffffec00 62 entries.
9139 22:18:42.811232 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9140 22:18:42.814662 WARNING: RO_VPD is uninitialized or empty.
9141 22:18:42.821115 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9142 22:18:42.828117 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9143 22:18:42.840942 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9144 22:18:42.852156 BS: romstage times (exec / console): total (unknown) / 23959 ms
9145 22:18:42.852232
9146 22:18:42.852296
9147 22:18:42.862312 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9148 22:18:42.865483 ARM64: Exception handlers installed.
9149 22:18:42.868952 ARM64: Testing exception
9150 22:18:42.871982 ARM64: Done test exception
9151 22:18:42.872053 Enumerating buses...
9152 22:18:42.875405 Show all devs... Before device enumeration.
9153 22:18:42.878720 Root Device: enabled 1
9154 22:18:42.882207 CPU_CLUSTER: 0: enabled 1
9155 22:18:42.882281 CPU: 00: enabled 1
9156 22:18:42.885747 Compare with tree...
9157 22:18:42.885819 Root Device: enabled 1
9158 22:18:42.888756 CPU_CLUSTER: 0: enabled 1
9159 22:18:42.891814 CPU: 00: enabled 1
9160 22:18:42.891891 Root Device scanning...
9161 22:18:42.895296 scan_static_bus for Root Device
9162 22:18:42.898997 CPU_CLUSTER: 0 enabled
9163 22:18:42.902335 scan_static_bus for Root Device done
9164 22:18:42.905191 scan_bus: bus Root Device finished in 8 msecs
9165 22:18:42.905263 done
9166 22:18:42.911991 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9167 22:18:42.915412 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9168 22:18:42.922209 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9169 22:18:42.925448 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9170 22:18:42.928937 Allocating resources...
9171 22:18:42.929019 Reading resources...
9172 22:18:42.935692 Root Device read_resources bus 0 link: 0
9173 22:18:42.935775 DRAM rank0 size:0x100000000,
9174 22:18:42.938768 DRAM rank1 size=0x100000000
9175 22:18:42.942369 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9176 22:18:42.945863 CPU: 00 missing read_resources
9177 22:18:42.948751 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9178 22:18:42.954890 Root Device read_resources bus 0 link: 0 done
9179 22:18:42.954973 Done reading resources.
9180 22:18:42.961869 Show resources in subtree (Root Device)...After reading.
9181 22:18:42.964987 Root Device child on link 0 CPU_CLUSTER: 0
9182 22:18:42.968567 CPU_CLUSTER: 0 child on link 0 CPU: 00
9183 22:18:42.978337 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9184 22:18:42.978425 CPU: 00
9185 22:18:42.981455 Root Device assign_resources, bus 0 link: 0
9186 22:18:42.984825 CPU_CLUSTER: 0 missing set_resources
9187 22:18:42.991613 Root Device assign_resources, bus 0 link: 0 done
9188 22:18:42.991697 Done setting resources.
9189 22:18:42.998434 Show resources in subtree (Root Device)...After assigning values.
9190 22:18:43.001478 Root Device child on link 0 CPU_CLUSTER: 0
9191 22:18:43.004852 CPU_CLUSTER: 0 child on link 0 CPU: 00
9192 22:18:43.014570 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9193 22:18:43.014655 CPU: 00
9194 22:18:43.017957 Done allocating resources.
9195 22:18:43.021369 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9196 22:18:43.024281 Enabling resources...
9197 22:18:43.024366 done.
9198 22:18:43.031142 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9199 22:18:43.031219 Initializing devices...
9200 22:18:43.034574 Root Device init
9201 22:18:43.034645 init hardware done!
9202 22:18:43.037926 0x00000018: ctrlr->caps
9203 22:18:43.041709 52.000 MHz: ctrlr->f_max
9204 22:18:43.041781 0.400 MHz: ctrlr->f_min
9205 22:18:43.044553 0x40ff8080: ctrlr->voltages
9206 22:18:43.047846 sclk: 390625
9207 22:18:43.047929 Bus Width = 1
9208 22:18:43.047993 sclk: 390625
9209 22:18:43.051234 Bus Width = 1
9210 22:18:43.051314 Early init status = 3
9211 22:18:43.057921 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9212 22:18:43.061138 in-header: 03 fc 00 00 01 00 00 00
9213 22:18:43.061221 in-data: 00
9214 22:18:43.067595 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9215 22:18:43.071135 in-header: 03 fd 00 00 00 00 00 00
9216 22:18:43.074245 in-data:
9217 22:18:43.077250 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9218 22:18:43.081382 in-header: 03 fc 00 00 01 00 00 00
9219 22:18:43.084777 in-data: 00
9220 22:18:43.087951 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9221 22:18:43.092993 in-header: 03 fd 00 00 00 00 00 00
9222 22:18:43.096513 in-data:
9223 22:18:43.099599 [SSUSB] Setting up USB HOST controller...
9224 22:18:43.103079 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9225 22:18:43.106675 [SSUSB] phy power-on done.
9226 22:18:43.109871 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9227 22:18:43.116556 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9228 22:18:43.120220 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9229 22:18:43.126721 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9230 22:18:43.133457 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9231 22:18:43.140220 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9232 22:18:43.146447 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9233 22:18:43.153160 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9234 22:18:43.153268 SPM: binary array size = 0x9dc
9235 22:18:43.160114 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9236 22:18:43.166465 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9237 22:18:43.172831 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9238 22:18:43.176296 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9239 22:18:43.183070 configure_display: Starting display init
9240 22:18:43.216589 anx7625_power_on_init: Init interface.
9241 22:18:43.219901 anx7625_disable_pd_protocol: Disabled PD feature.
9242 22:18:43.222954 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9243 22:18:43.250993 anx7625_start_dp_work: Secure OCM version=00
9244 22:18:43.253875 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9245 22:18:43.268791 sp_tx_get_edid_block: EDID Block = 1
9246 22:18:43.371448 Extracted contents:
9247 22:18:43.374575 header: 00 ff ff ff ff ff ff 00
9248 22:18:43.378222 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9249 22:18:43.381237 version: 01 04
9250 22:18:43.384660 basic params: 95 1f 11 78 0a
9251 22:18:43.387772 chroma info: 76 90 94 55 54 90 27 21 50 54
9252 22:18:43.391854 established: 00 00 00
9253 22:18:43.397924 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9254 22:18:43.401318 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9255 22:18:43.408023 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9256 22:18:43.414482 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9257 22:18:43.421374 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9258 22:18:43.424524 extensions: 00
9259 22:18:43.424607 checksum: fb
9260 22:18:43.424673
9261 22:18:43.427934 Manufacturer: IVO Model 57d Serial Number 0
9262 22:18:43.431380 Made week 0 of 2020
9263 22:18:43.431479 EDID version: 1.4
9264 22:18:43.434504 Digital display
9265 22:18:43.437686 6 bits per primary color channel
9266 22:18:43.437770 DisplayPort interface
9267 22:18:43.440896 Maximum image size: 31 cm x 17 cm
9268 22:18:43.444429 Gamma: 220%
9269 22:18:43.444511 Check DPMS levels
9270 22:18:43.447564 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9271 22:18:43.450851 First detailed timing is preferred timing
9272 22:18:43.454187 Established timings supported:
9273 22:18:43.457756 Standard timings supported:
9274 22:18:43.457838 Detailed timings
9275 22:18:43.464592 Hex of detail: 383680a07038204018303c0035ae10000019
9276 22:18:43.467630 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9277 22:18:43.474628 0780 0798 07c8 0820 hborder 0
9278 22:18:43.477631 0438 043b 0447 0458 vborder 0
9279 22:18:43.481276 -hsync -vsync
9280 22:18:43.481385 Did detailed timing
9281 22:18:43.487709 Hex of detail: 000000000000000000000000000000000000
9282 22:18:43.487793 Manufacturer-specified data, tag 0
9283 22:18:43.494320 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9284 22:18:43.494403 ASCII string: InfoVision
9285 22:18:43.501010 Hex of detail: 000000fe00523134304e574635205248200a
9286 22:18:43.504323 ASCII string: R140NWF5 RH
9287 22:18:43.504406 Checksum
9288 22:18:43.504472 Checksum: 0xfb (valid)
9289 22:18:43.510704 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9290 22:18:43.514186 DSI data_rate: 832800000 bps
9291 22:18:43.517380 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9292 22:18:43.524090 anx7625_parse_edid: pixelclock(138800).
9293 22:18:43.527560 hactive(1920), hsync(48), hfp(24), hbp(88)
9294 22:18:43.530720 vactive(1080), vsync(12), vfp(3), vbp(17)
9295 22:18:43.534212 anx7625_dsi_config: config dsi.
9296 22:18:43.540939 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9297 22:18:43.553613 anx7625_dsi_config: success to config DSI
9298 22:18:43.556547 anx7625_dp_start: MIPI phy setup OK.
9299 22:18:43.560090 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9300 22:18:43.563780 mtk_ddp_mode_set invalid vrefresh 60
9301 22:18:43.566537 main_disp_path_setup
9302 22:18:43.566618 ovl_layer_smi_id_en
9303 22:18:43.570452 ovl_layer_smi_id_en
9304 22:18:43.570533 ccorr_config
9305 22:18:43.570596 aal_config
9306 22:18:43.573461 gamma_config
9307 22:18:43.573577 postmask_config
9308 22:18:43.576590 dither_config
9309 22:18:43.580358 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9310 22:18:43.586350 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9311 22:18:43.589787 Root Device init finished in 552 msecs
9312 22:18:43.593387 CPU_CLUSTER: 0 init
9313 22:18:43.599805 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9314 22:18:43.603301 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9315 22:18:43.606437 APU_MBOX 0x190000b0 = 0x10001
9316 22:18:43.610069 APU_MBOX 0x190001b0 = 0x10001
9317 22:18:43.613198 APU_MBOX 0x190005b0 = 0x10001
9318 22:18:43.616394 APU_MBOX 0x190006b0 = 0x10001
9319 22:18:43.619844 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9320 22:18:43.632806 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9321 22:18:43.644831 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9322 22:18:43.651323 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9323 22:18:43.662848 read SPI 0x61c74 0xe8ef: 6408 us, 9305 KB/s, 74.440 Mbps
9324 22:18:43.672387 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9325 22:18:43.675967 CPU_CLUSTER: 0 init finished in 81 msecs
9326 22:18:43.679014 Devices initialized
9327 22:18:43.682631 Show all devs... After init.
9328 22:18:43.682769 Root Device: enabled 1
9329 22:18:43.685481 CPU_CLUSTER: 0: enabled 1
9330 22:18:43.689310 CPU: 00: enabled 1
9331 22:18:43.692300 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms
9332 22:18:43.695726 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9333 22:18:43.699174 ELOG: NV offset 0x57f000 size 0x1000
9334 22:18:43.705393 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9335 22:18:43.712280 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9336 22:18:43.715402 ELOG: Event(17) added with size 13 at 2023-06-04 22:18:44 UTC
9337 22:18:43.718873 out: cmd=0x121: 03 db 21 01 00 00 00 00
9338 22:18:43.722538 in-header: 03 fb 00 00 2c 00 00 00
9339 22:18:43.736250 in-data: 64 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9340 22:18:43.742788 ELOG: Event(A1) added with size 10 at 2023-06-04 22:18:44 UTC
9341 22:18:43.749481 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9342 22:18:43.755710 ELOG: Event(A0) added with size 9 at 2023-06-04 22:18:44 UTC
9343 22:18:43.759179 elog_add_boot_reason: Logged dev mode boot
9344 22:18:43.762581 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9345 22:18:43.766161 Finalize devices...
9346 22:18:43.766585 Devices finalized
9347 22:18:43.772716 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9348 22:18:43.776000 Writing coreboot table at 0xffe64000
9349 22:18:43.779214 0. 000000000010a000-0000000000113fff: RAMSTAGE
9350 22:18:43.782339 1. 0000000040000000-00000000400fffff: RAM
9351 22:18:43.789316 2. 0000000040100000-000000004032afff: RAMSTAGE
9352 22:18:43.792957 3. 000000004032b000-00000000545fffff: RAM
9353 22:18:43.796172 4. 0000000054600000-000000005465ffff: BL31
9354 22:18:43.799696 5. 0000000054660000-00000000ffe63fff: RAM
9355 22:18:43.806183 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9356 22:18:43.809927 7. 0000000100000000-000000023fffffff: RAM
9357 22:18:43.810492 Passing 5 GPIOs to payload:
9358 22:18:43.816136 NAME | PORT | POLARITY | VALUE
9359 22:18:43.819554 EC in RW | 0x000000aa | low | undefined
9360 22:18:43.825981 EC interrupt | 0x00000005 | low | undefined
9361 22:18:43.829302 TPM interrupt | 0x000000ab | high | undefined
9362 22:18:43.832196 SD card detect | 0x00000011 | high | undefined
9363 22:18:43.839312 speaker enable | 0x00000093 | high | undefined
9364 22:18:43.842141 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9365 22:18:43.845922 in-header: 03 f9 00 00 02 00 00 00
9366 22:18:43.846489 in-data: 02 00
9367 22:18:43.849188 ADC[4]: Raw value=904357 ID=7
9368 22:18:43.852498 ADC[3]: Raw value=213441 ID=1
9369 22:18:43.853065 RAM Code: 0x71
9370 22:18:43.855383 ADC[6]: Raw value=75701 ID=0
9371 22:18:43.858801 ADC[5]: Raw value=213072 ID=1
9372 22:18:43.859357 SKU Code: 0x1
9373 22:18:43.865604 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum d697
9374 22:18:43.868863 coreboot table: 964 bytes.
9375 22:18:43.872172 IMD ROOT 0. 0xfffff000 0x00001000
9376 22:18:43.875607 IMD SMALL 1. 0xffffe000 0x00001000
9377 22:18:43.879050 RO MCACHE 2. 0xffffc000 0x00001104
9378 22:18:43.881883 CONSOLE 3. 0xfff7c000 0x00080000
9379 22:18:43.885163 FMAP 4. 0xfff7b000 0x00000452
9380 22:18:43.888936 TIME STAMP 5. 0xfff7a000 0x00000910
9381 22:18:43.892342 VBOOT WORK 6. 0xfff66000 0x00014000
9382 22:18:43.895584 RAMOOPS 7. 0xffe66000 0x00100000
9383 22:18:43.898457 COREBOOT 8. 0xffe64000 0x00002000
9384 22:18:43.898974 IMD small region:
9385 22:18:43.902149 IMD ROOT 0. 0xffffec00 0x00000400
9386 22:18:43.905569 VPD 1. 0xffffeba0 0x0000004c
9387 22:18:43.909195 MMC STATUS 2. 0xffffeb80 0x00000004
9388 22:18:43.915286 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9389 22:18:43.919047 Probing TPM: done!
9390 22:18:43.922555 Connected to device vid:did:rid of 1ae0:0028:00
9391 22:18:43.931736 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.153/cr50_v3.94_pp.113-620c9b9523
9392 22:18:43.935473 Initialized TPM device CR50 revision 0
9393 22:18:43.939475 Checking cr50 for pending updates
9394 22:18:43.942635 Reading cr50 TPM mode
9395 22:18:43.951236 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9396 22:18:43.957893 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9397 22:18:43.997739 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9398 22:18:44.001574 Checking segment from ROM address 0x40100000
9399 22:18:44.005135 Checking segment from ROM address 0x4010001c
9400 22:18:44.011204 Loading segment from ROM address 0x40100000
9401 22:18:44.011774 code (compression=0)
9402 22:18:44.018199 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9403 22:18:44.028306 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9404 22:18:44.028879 it's not compressed!
9405 22:18:44.034648 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9406 22:18:44.038360 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9407 22:18:44.058372 Loading segment from ROM address 0x4010001c
9408 22:18:44.059105 Entry Point 0x80000000
9409 22:18:44.061910 Loaded segments
9410 22:18:44.065315 BS: BS_PAYLOAD_LOAD run times (exec / console): 49 / 61 ms
9411 22:18:44.071883 Jumping to boot code at 0x80000000(0xffe64000)
9412 22:18:44.077806 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9413 22:18:44.084647 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9414 22:18:44.092567 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9415 22:18:44.096080 Checking segment from ROM address 0x40100000
9416 22:18:44.099570 Checking segment from ROM address 0x4010001c
9417 22:18:44.105758 Loading segment from ROM address 0x40100000
9418 22:18:44.106314 code (compression=1)
9419 22:18:44.113161 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9420 22:18:44.122842 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9421 22:18:44.123415 using LZMA
9422 22:18:44.131462 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9423 22:18:44.138073 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9424 22:18:44.140907 Loading segment from ROM address 0x4010001c
9425 22:18:44.141374 Entry Point 0x54601000
9426 22:18:44.144773 Loaded segments
9427 22:18:44.147910 NOTICE: MT8192 bl31_setup
9428 22:18:44.154598 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9429 22:18:44.157999 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9430 22:18:44.161205 WARNING: region 0:
9431 22:18:44.165215 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9432 22:18:44.165836 WARNING: region 1:
9433 22:18:44.171445 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9434 22:18:44.174656 WARNING: region 2:
9435 22:18:44.177909 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9436 22:18:44.181606 WARNING: region 3:
9437 22:18:44.184703 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9438 22:18:44.188217 WARNING: region 4:
9439 22:18:44.191622 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9440 22:18:44.195089 WARNING: region 5:
9441 22:18:44.198048 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9442 22:18:44.201612 WARNING: region 6:
9443 22:18:44.205653 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9444 22:18:44.206223 WARNING: region 7:
9445 22:18:44.211777 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9446 22:18:44.218394 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9447 22:18:44.222072 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9448 22:18:44.224984 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9449 22:18:44.231807 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9450 22:18:44.234359 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9451 22:18:44.238449 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9452 22:18:44.245458 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9453 22:18:44.248183 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9454 22:18:44.251952 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9455 22:18:44.258443 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9456 22:18:44.261772 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9457 22:18:44.264485 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9458 22:18:44.271872 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9459 22:18:44.274728 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9460 22:18:44.281925 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9461 22:18:44.284998 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9462 22:18:44.288030 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9463 22:18:44.294702 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9464 22:18:44.298207 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9465 22:18:44.301672 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9466 22:18:44.308449 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9467 22:18:44.311810 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9468 22:18:44.318195 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9469 22:18:44.321731 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9470 22:18:44.328435 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9471 22:18:44.331510 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9472 22:18:44.334961 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9473 22:18:44.341343 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9474 22:18:44.344952 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9475 22:18:44.348014 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9476 22:18:44.354504 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9477 22:18:44.358230 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9478 22:18:44.361434 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9479 22:18:44.368361 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9480 22:18:44.371559 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9481 22:18:44.374821 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9482 22:18:44.378510 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9483 22:18:44.385215 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9484 22:18:44.387906 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9485 22:18:44.391722 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9486 22:18:44.395003 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9487 22:18:44.401336 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9488 22:18:44.405383 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9489 22:18:44.407928 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9490 22:18:44.411536 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9491 22:18:44.418001 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9492 22:18:44.421560 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9493 22:18:44.424737 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9494 22:18:44.431505 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9495 22:18:44.434876 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9496 22:18:44.441459 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9497 22:18:44.445006 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9498 22:18:44.448071 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9499 22:18:44.454928 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9500 22:18:44.458678 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9501 22:18:44.465653 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9502 22:18:44.468386 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9503 22:18:44.471795 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9504 22:18:44.478766 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9505 22:18:44.481594 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9506 22:18:44.487836 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9507 22:18:44.491668 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9508 22:18:44.498266 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9509 22:18:44.501654 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9510 22:18:44.507986 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9511 22:18:44.511692 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9512 22:18:44.515064 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9513 22:18:44.521868 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9514 22:18:44.524738 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9515 22:18:44.531690 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9516 22:18:44.534655 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9517 22:18:44.538372 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9518 22:18:44.545169 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9519 22:18:44.548737 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9520 22:18:44.555311 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9521 22:18:44.558238 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9522 22:18:44.564879 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9523 22:18:44.568701 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9524 22:18:44.574878 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9525 22:18:44.578087 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9526 22:18:44.581851 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9527 22:18:44.588220 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9528 22:18:44.592034 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9529 22:18:44.598345 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9530 22:18:44.602097 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9531 22:18:44.605214 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9532 22:18:44.611596 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9533 22:18:44.615513 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9534 22:18:44.621869 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9535 22:18:44.624897 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9536 22:18:44.631786 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9537 22:18:44.635160 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9538 22:18:44.638198 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9539 22:18:44.645115 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9540 22:18:44.648786 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9541 22:18:44.655267 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9542 22:18:44.658985 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9543 22:18:44.662346 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9544 22:18:44.668955 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9545 22:18:44.672611 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9546 22:18:44.675637 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9547 22:18:44.678748 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9548 22:18:44.685123 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9549 22:18:44.688647 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9550 22:18:44.695435 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9551 22:18:44.699116 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9552 22:18:44.701994 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9553 22:18:44.708903 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9554 22:18:44.712087 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9555 22:18:44.719066 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9556 22:18:44.722211 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9557 22:18:44.725474 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9558 22:18:44.731749 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9559 22:18:44.735433 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9560 22:18:44.741659 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9561 22:18:44.745058 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9562 22:18:44.748596 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9563 22:18:44.751884 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9564 22:18:44.758569 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9565 22:18:44.762311 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9566 22:18:44.765235 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9567 22:18:44.768795 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9568 22:18:44.775227 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9569 22:18:44.778950 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9570 22:18:44.782341 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9571 22:18:44.789159 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9572 22:18:44.792289 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9573 22:18:44.799223 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9574 22:18:44.802760 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9575 22:18:44.805760 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9576 22:18:44.812977 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9577 22:18:44.815999 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9578 22:18:44.819294 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9579 22:18:44.826105 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9580 22:18:44.829247 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9581 22:18:44.835898 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9582 22:18:44.838769 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9583 22:18:44.842380 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9584 22:18:44.849270 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9585 22:18:44.852615 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9586 22:18:44.856209 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9587 22:18:44.862446 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9588 22:18:44.866361 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9589 22:18:44.872707 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9590 22:18:44.876507 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9591 22:18:44.879188 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9592 22:18:44.886074 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9593 22:18:44.889950 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9594 22:18:44.893143 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9595 22:18:44.899878 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9596 22:18:44.902964 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9597 22:18:44.909329 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9598 22:18:44.912691 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9599 22:18:44.916231 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9600 22:18:44.922581 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9601 22:18:44.926325 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9602 22:18:44.932949 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9603 22:18:44.936411 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9604 22:18:44.939425 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9605 22:18:44.946054 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9606 22:18:44.949751 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9607 22:18:44.952895 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9608 22:18:44.959131 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9609 22:18:44.962845 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9610 22:18:44.969683 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9611 22:18:44.973040 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9612 22:18:44.975947 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9613 22:18:44.983518 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9614 22:18:44.986346 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9615 22:18:44.992415 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9616 22:18:44.996419 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9617 22:18:44.999759 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9618 22:18:45.006378 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9619 22:18:45.009692 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9620 22:18:45.012893 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9621 22:18:45.018974 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9622 22:18:45.022614 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9623 22:18:45.029330 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9624 22:18:45.032787 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9625 22:18:45.035645 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9626 22:18:45.042904 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9627 22:18:45.046202 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9628 22:18:45.052728 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9629 22:18:45.055675 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9630 22:18:45.058845 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9631 22:18:45.065501 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9632 22:18:45.068849 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9633 22:18:45.075616 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9634 22:18:45.079217 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9635 22:18:45.082294 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9636 22:18:45.088719 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9637 22:18:45.092357 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9638 22:18:45.098883 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9639 22:18:45.102257 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9640 22:18:45.108939 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9641 22:18:45.111971 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9642 22:18:45.115649 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9643 22:18:45.122186 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9644 22:18:45.125355 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9645 22:18:45.132434 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9646 22:18:45.135310 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9647 22:18:45.138669 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9648 22:18:45.145886 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9649 22:18:45.149039 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9650 22:18:45.155596 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9651 22:18:45.159290 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9652 22:18:45.165181 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9653 22:18:45.169023 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9654 22:18:45.171994 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9655 22:18:45.178383 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9656 22:18:45.181630 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9657 22:18:45.188555 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9658 22:18:45.191503 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9659 22:18:45.195455 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9660 22:18:45.202239 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9661 22:18:45.204961 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9662 22:18:45.212024 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9663 22:18:45.215587 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9664 22:18:45.222012 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9665 22:18:45.225038 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9666 22:18:45.228524 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9667 22:18:45.235023 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9668 22:18:45.238219 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9669 22:18:45.244661 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9670 22:18:45.248487 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9671 22:18:45.251370 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9672 22:18:45.258680 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9673 22:18:45.261697 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9674 22:18:45.268328 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9675 22:18:45.271557 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9676 22:18:45.275068 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9677 22:18:45.278216 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9678 22:18:45.284635 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9679 22:18:45.287874 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9680 22:18:45.291222 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9681 22:18:45.297947 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9682 22:18:45.301451 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9683 22:18:45.305226 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9684 22:18:45.312051 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9685 22:18:45.315077 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9686 22:18:45.318596 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9687 22:18:45.324824 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9688 22:18:45.328226 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9689 22:18:45.331380 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9690 22:18:45.337941 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9691 22:18:45.341635 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9692 22:18:45.348120 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9693 22:18:45.351529 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9694 22:18:45.355064 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9695 22:18:45.361008 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9696 22:18:45.364901 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9697 22:18:45.368255 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9698 22:18:45.374841 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9699 22:18:45.378039 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9700 22:18:45.381098 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9701 22:18:45.387486 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9702 22:18:45.390932 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9703 22:18:45.397224 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9704 22:18:45.400743 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9705 22:18:45.404406 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9706 22:18:45.410797 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9707 22:18:45.414465 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9708 22:18:45.420827 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9709 22:18:45.423831 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9710 22:18:45.427402 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9711 22:18:45.434102 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9712 22:18:45.437451 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9713 22:18:45.440677 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9714 22:18:45.447917 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9715 22:18:45.450733 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9716 22:18:45.453746 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9717 22:18:45.457313 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9718 22:18:45.460650 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9719 22:18:45.467088 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9720 22:18:45.471184 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9721 22:18:45.474072 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9722 22:18:45.476962 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9723 22:18:45.483561 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9724 22:18:45.486845 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9725 22:18:45.490165 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9726 22:18:45.497312 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9727 22:18:45.500466 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9728 22:18:45.503563 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9729 22:18:45.510405 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9730 22:18:45.514053 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9731 22:18:45.517321 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9732 22:18:45.523702 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9733 22:18:45.527506 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9734 22:18:45.533992 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9735 22:18:45.536661 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9736 22:18:45.540483 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9737 22:18:45.546974 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9738 22:18:45.550612 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9739 22:18:45.557278 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9740 22:18:45.560631 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9741 22:18:45.567285 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9742 22:18:45.570134 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9743 22:18:45.573488 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9744 22:18:45.580319 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9745 22:18:45.583269 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9746 22:18:45.589976 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9747 22:18:45.593680 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9748 22:18:45.596852 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9749 22:18:45.603725 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9750 22:18:45.607378 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9751 22:18:45.610248 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9752 22:18:45.617087 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9753 22:18:45.620495 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9754 22:18:45.626799 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9755 22:18:45.630248 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9756 22:18:45.637130 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9757 22:18:45.640190 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9758 22:18:45.646985 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9759 22:18:45.650208 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9760 22:18:45.653492 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9761 22:18:45.660004 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9762 22:18:45.663112 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9763 22:18:45.670204 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9764 22:18:45.673432 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9765 22:18:45.676662 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9766 22:18:45.683110 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9767 22:18:45.686723 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9768 22:18:45.693157 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9769 22:18:45.696456 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9770 22:18:45.700319 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9771 22:18:45.706123 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9772 22:18:45.709369 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9773 22:18:45.716123 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9774 22:18:45.719872 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9775 22:18:45.722894 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9776 22:18:45.729364 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9777 22:18:45.732531 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9778 22:18:45.739463 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9779 22:18:45.742782 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9780 22:18:45.746052 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9781 22:18:45.752635 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9782 22:18:45.756719 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9783 22:18:45.763038 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9784 22:18:45.765970 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9785 22:18:45.769681 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9786 22:18:45.776045 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9787 22:18:45.780366 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9788 22:18:45.785913 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9789 22:18:45.789463 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9790 22:18:45.796422 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9791 22:18:45.799546 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9792 22:18:45.803037 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9793 22:18:45.809586 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9794 22:18:45.812849 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9795 22:18:45.816117 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9796 22:18:45.822957 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9797 22:18:45.826162 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9798 22:18:45.833130 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9799 22:18:45.836153 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9800 22:18:45.839502 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9801 22:18:45.846562 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9802 22:18:45.849133 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9803 22:18:45.855933 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9804 22:18:45.858986 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9805 22:18:45.866038 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9806 22:18:45.869058 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9807 22:18:45.875638 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9808 22:18:45.879098 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9809 22:18:45.882089 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9810 22:18:45.888513 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9811 22:18:45.892095 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9812 22:18:45.899010 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9813 22:18:45.902489 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9814 22:18:45.909229 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9815 22:18:45.912379 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9816 22:18:45.915226 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9817 22:18:45.922512 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9818 22:18:45.925416 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9819 22:18:45.932181 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9820 22:18:45.935611 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9821 22:18:45.942367 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9822 22:18:45.945554 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9823 22:18:45.948675 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9824 22:18:45.955249 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9825 22:18:45.958609 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9826 22:18:45.965812 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9827 22:18:45.968692 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9828 22:18:45.975724 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9829 22:18:45.978691 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9830 22:18:45.985221 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9831 22:18:45.988480 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9832 22:18:45.992049 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9833 22:18:45.999175 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9834 22:18:46.001738 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9835 22:18:46.008671 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9836 22:18:46.012126 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9837 22:18:46.018840 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9838 22:18:46.021994 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9839 22:18:46.025120 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9840 22:18:46.032261 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9841 22:18:46.034957 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9842 22:18:46.042132 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9843 22:18:46.045618 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9844 22:18:46.052099 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9845 22:18:46.055021 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9846 22:18:46.061610 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9847 22:18:46.064858 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9848 22:18:46.068293 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9849 22:18:46.074938 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9850 22:18:46.078666 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9851 22:18:46.084883 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9852 22:18:46.088752 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9853 22:18:46.094830 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9854 22:18:46.097939 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9855 22:18:46.101628 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9856 22:18:46.108197 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9857 22:18:46.111205 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9858 22:18:46.117898 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9859 22:18:46.121023 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9860 22:18:46.128441 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9861 22:18:46.131674 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9862 22:18:46.137985 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9863 22:18:46.141632 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9864 22:18:46.148008 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9865 22:18:46.151350 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9866 22:18:46.158125 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9867 22:18:46.161467 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9868 22:18:46.168064 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9869 22:18:46.171376 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9870 22:18:46.178052 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9871 22:18:46.181789 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9872 22:18:46.188253 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9873 22:18:46.191498 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9874 22:18:46.197904 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9875 22:18:46.201613 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9876 22:18:46.208623 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9877 22:18:46.211783 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9878 22:18:46.217998 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9879 22:18:46.221485 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9880 22:18:46.224787 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9881 22:18:46.228516 INFO: [APUAPC] vio 0
9882 22:18:46.234824 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9883 22:18:46.238226 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9884 22:18:46.241942 INFO: [APUAPC] D0_APC_0: 0x400510
9885 22:18:46.244971 INFO: [APUAPC] D0_APC_1: 0x0
9886 22:18:46.248085 INFO: [APUAPC] D0_APC_2: 0x1540
9887 22:18:46.251357 INFO: [APUAPC] D0_APC_3: 0x0
9888 22:18:46.254809 INFO: [APUAPC] D1_APC_0: 0xffffffff
9889 22:18:46.258417 INFO: [APUAPC] D1_APC_1: 0xffffffff
9890 22:18:46.261567 INFO: [APUAPC] D1_APC_2: 0x3fffff
9891 22:18:46.262079 INFO: [APUAPC] D1_APC_3: 0x0
9892 22:18:46.264666 INFO: [APUAPC] D2_APC_0: 0xffffffff
9893 22:18:46.271383 INFO: [APUAPC] D2_APC_1: 0xffffffff
9894 22:18:46.274744 INFO: [APUAPC] D2_APC_2: 0x3fffff
9895 22:18:46.275205 INFO: [APUAPC] D2_APC_3: 0x0
9896 22:18:46.278197 INFO: [APUAPC] D3_APC_0: 0xffffffff
9897 22:18:46.281423 INFO: [APUAPC] D3_APC_1: 0xffffffff
9898 22:18:46.284744 INFO: [APUAPC] D3_APC_2: 0x3fffff
9899 22:18:46.288148 INFO: [APUAPC] D3_APC_3: 0x0
9900 22:18:46.291214 INFO: [APUAPC] D4_APC_0: 0xffffffff
9901 22:18:46.294635 INFO: [APUAPC] D4_APC_1: 0xffffffff
9902 22:18:46.297895 INFO: [APUAPC] D4_APC_2: 0x3fffff
9903 22:18:46.301245 INFO: [APUAPC] D4_APC_3: 0x0
9904 22:18:46.305097 INFO: [APUAPC] D5_APC_0: 0xffffffff
9905 22:18:46.308372 INFO: [APUAPC] D5_APC_1: 0xffffffff
9906 22:18:46.311325 INFO: [APUAPC] D5_APC_2: 0x3fffff
9907 22:18:46.315085 INFO: [APUAPC] D5_APC_3: 0x0
9908 22:18:46.318101 INFO: [APUAPC] D6_APC_0: 0xffffffff
9909 22:18:46.321212 INFO: [APUAPC] D6_APC_1: 0xffffffff
9910 22:18:46.324856 INFO: [APUAPC] D6_APC_2: 0x3fffff
9911 22:18:46.327843 INFO: [APUAPC] D6_APC_3: 0x0
9912 22:18:46.331603 INFO: [APUAPC] D7_APC_0: 0xffffffff
9913 22:18:46.334299 INFO: [APUAPC] D7_APC_1: 0xffffffff
9914 22:18:46.337821 INFO: [APUAPC] D7_APC_2: 0x3fffff
9915 22:18:46.341176 INFO: [APUAPC] D7_APC_3: 0x0
9916 22:18:46.344515 INFO: [APUAPC] D8_APC_0: 0xffffffff
9917 22:18:46.348060 INFO: [APUAPC] D8_APC_1: 0xffffffff
9918 22:18:46.351512 INFO: [APUAPC] D8_APC_2: 0x3fffff
9919 22:18:46.354530 INFO: [APUAPC] D8_APC_3: 0x0
9920 22:18:46.357555 INFO: [APUAPC] D9_APC_0: 0xffffffff
9921 22:18:46.361161 INFO: [APUAPC] D9_APC_1: 0xffffffff
9922 22:18:46.364347 INFO: [APUAPC] D9_APC_2: 0x3fffff
9923 22:18:46.367533 INFO: [APUAPC] D9_APC_3: 0x0
9924 22:18:46.371536 INFO: [APUAPC] D10_APC_0: 0xffffffff
9925 22:18:46.374465 INFO: [APUAPC] D10_APC_1: 0xffffffff
9926 22:18:46.378038 INFO: [APUAPC] D10_APC_2: 0x3fffff
9927 22:18:46.381118 INFO: [APUAPC] D10_APC_3: 0x0
9928 22:18:46.384607 INFO: [APUAPC] D11_APC_0: 0xffffffff
9929 22:18:46.388260 INFO: [APUAPC] D11_APC_1: 0xffffffff
9930 22:18:46.391711 INFO: [APUAPC] D11_APC_2: 0x3fffff
9931 22:18:46.394721 INFO: [APUAPC] D11_APC_3: 0x0
9932 22:18:46.397659 INFO: [APUAPC] D12_APC_0: 0xffffffff
9933 22:18:46.401624 INFO: [APUAPC] D12_APC_1: 0xffffffff
9934 22:18:46.405071 INFO: [APUAPC] D12_APC_2: 0x3fffff
9935 22:18:46.407909 INFO: [APUAPC] D12_APC_3: 0x0
9936 22:18:46.411466 INFO: [APUAPC] D13_APC_0: 0xffffffff
9937 22:18:46.414778 INFO: [APUAPC] D13_APC_1: 0xffffffff
9938 22:18:46.417711 INFO: [APUAPC] D13_APC_2: 0x3fffff
9939 22:18:46.421135 INFO: [APUAPC] D13_APC_3: 0x0
9940 22:18:46.424348 INFO: [APUAPC] D14_APC_0: 0xffffffff
9941 22:18:46.428113 INFO: [APUAPC] D14_APC_1: 0xffffffff
9942 22:18:46.431845 INFO: [APUAPC] D14_APC_2: 0x3fffff
9943 22:18:46.434472 INFO: [APUAPC] D14_APC_3: 0x0
9944 22:18:46.437791 INFO: [APUAPC] D15_APC_0: 0xffffffff
9945 22:18:46.441140 INFO: [APUAPC] D15_APC_1: 0xffffffff
9946 22:18:46.445060 INFO: [APUAPC] D15_APC_2: 0x3fffff
9947 22:18:46.448008 INFO: [APUAPC] D15_APC_3: 0x0
9948 22:18:46.451344 INFO: [APUAPC] APC_CON: 0x4
9949 22:18:46.454439 INFO: [NOCDAPC] D0_APC_0: 0x0
9950 22:18:46.454955 INFO: [NOCDAPC] D0_APC_1: 0x0
9951 22:18:46.458093 INFO: [NOCDAPC] D1_APC_0: 0x0
9952 22:18:46.461120 INFO: [NOCDAPC] D1_APC_1: 0xfff
9953 22:18:46.464609 INFO: [NOCDAPC] D2_APC_0: 0x0
9954 22:18:46.468036 INFO: [NOCDAPC] D2_APC_1: 0xfff
9955 22:18:46.471146 INFO: [NOCDAPC] D3_APC_0: 0x0
9956 22:18:46.474418 INFO: [NOCDAPC] D3_APC_1: 0xfff
9957 22:18:46.477216 INFO: [NOCDAPC] D4_APC_0: 0x0
9958 22:18:46.480412 INFO: [NOCDAPC] D4_APC_1: 0xfff
9959 22:18:46.484161 INFO: [NOCDAPC] D5_APC_0: 0x0
9960 22:18:46.487078 INFO: [NOCDAPC] D5_APC_1: 0xfff
9961 22:18:46.487529 INFO: [NOCDAPC] D6_APC_0: 0x0
9962 22:18:46.490534 INFO: [NOCDAPC] D6_APC_1: 0xfff
9963 22:18:46.493875 INFO: [NOCDAPC] D7_APC_0: 0x0
9964 22:18:46.497602 INFO: [NOCDAPC] D7_APC_1: 0xfff
9965 22:18:46.500501 INFO: [NOCDAPC] D8_APC_0: 0x0
9966 22:18:46.503862 INFO: [NOCDAPC] D8_APC_1: 0xfff
9967 22:18:46.507130 INFO: [NOCDAPC] D9_APC_0: 0x0
9968 22:18:46.510550 INFO: [NOCDAPC] D9_APC_1: 0xfff
9969 22:18:46.514276 INFO: [NOCDAPC] D10_APC_0: 0x0
9970 22:18:46.517848 INFO: [NOCDAPC] D10_APC_1: 0xfff
9971 22:18:46.520714 INFO: [NOCDAPC] D11_APC_0: 0x0
9972 22:18:46.524029 INFO: [NOCDAPC] D11_APC_1: 0xfff
9973 22:18:46.524456 INFO: [NOCDAPC] D12_APC_0: 0x0
9974 22:18:46.527542 INFO: [NOCDAPC] D12_APC_1: 0xfff
9975 22:18:46.530500 INFO: [NOCDAPC] D13_APC_0: 0x0
9976 22:18:46.534132 INFO: [NOCDAPC] D13_APC_1: 0xfff
9977 22:18:46.537311 INFO: [NOCDAPC] D14_APC_0: 0x0
9978 22:18:46.540400 INFO: [NOCDAPC] D14_APC_1: 0xfff
9979 22:18:46.543937 INFO: [NOCDAPC] D15_APC_0: 0x0
9980 22:18:46.547103 INFO: [NOCDAPC] D15_APC_1: 0xfff
9981 22:18:46.550683 INFO: [NOCDAPC] APC_CON: 0x4
9982 22:18:46.553738 INFO: [APUAPC] set_apusys_apc done
9983 22:18:46.557411 INFO: [DEVAPC] devapc_init done
9984 22:18:46.560486 INFO: GICv3 without legacy support detected.
9985 22:18:46.563430 INFO: ARM GICv3 driver initialized in EL3
9986 22:18:46.566932 INFO: Maximum SPI INTID supported: 639
9987 22:18:46.573706 INFO: BL31: Initializing runtime services
9988 22:18:46.576698 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9989 22:18:46.580448 INFO: SPM: enable CPC mode
9990 22:18:46.586779 INFO: mcdi ready for mcusys-off-idle and system suspend
9991 22:18:46.590246 INFO: BL31: Preparing for EL3 exit to normal world
9992 22:18:46.593463 INFO: Entry point address = 0x80000000
9993 22:18:46.596462 INFO: SPSR = 0x8
9994 22:18:46.602109
9995 22:18:46.602536
9996 22:18:46.602871
9997 22:18:46.605446 Starting depthcharge on Spherion...
9998 22:18:46.605913
9999 22:18:46.606253 Wipe memory regions:
10000 22:18:46.606569
10001 22:18:46.608890 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10002 22:18:46.609397 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10003 22:18:46.609847 Setting prompt string to ['asurada:']
10004 22:18:46.610233 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10005 22:18:46.610895 [0x00000040000000, 0x00000054600000)
10006 22:18:46.730724
10007 22:18:46.730944 [0x00000054660000, 0x00000080000000)
10008 22:18:46.991598
10009 22:18:46.991982 [0x000000821a7280, 0x000000ffe64000)
10010 22:18:47.736192
10011 22:18:47.736676 [0x00000100000000, 0x00000240000000)
10012 22:18:49.625873
10013 22:18:49.629483 Initializing XHCI USB controller at 0x11200000.
10014 22:18:50.667680
10015 22:18:50.670568 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10016 22:18:50.671009
10017 22:18:50.671340
10018 22:18:50.671645
10019 22:18:50.672350 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10021 22:18:50.773860 asurada: tftpboot 192.168.201.1 10583924/tftp-deploy-7_wm5peu/kernel/image.itb 10583924/tftp-deploy-7_wm5peu/kernel/cmdline
10022 22:18:50.774512 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10023 22:18:50.775066 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10024 22:18:50.780007 tftpboot 192.168.201.1 10583924/tftp-deploy-7_wm5peu/kernel/image.ittp-deploy-7_wm5peu/kernel/cmdline
10025 22:18:50.780460
10026 22:18:50.780800 Waiting for link
10027 22:18:50.939924
10028 22:18:50.940447 R8152: Initializing
10029 22:18:50.940785
10030 22:18:50.943746 Version 9 (ocp_data = 6010)
10031 22:18:50.944272
10032 22:18:50.946796 R8152: Done initializing
10033 22:18:50.947289
10034 22:18:50.947635 Adding net device
10035 22:18:52.889250
10036 22:18:52.889821 done.
10037 22:18:52.890170
10038 22:18:52.890482 MAC: 00:e0:4c:78:7a:aa
10039 22:18:52.890785
10040 22:18:52.892607 Sending DHCP discover... done.
10041 22:18:52.893025
10042 22:18:52.895298 Waiting for reply... done.
10043 22:18:52.895720
10044 22:18:52.899150 Sending DHCP request... done.
10045 22:18:52.899671
10046 22:18:52.902220 Waiting for reply... done.
10047 22:18:52.902640
10048 22:18:52.902972 My ip is 192.168.201.12
10049 22:18:52.903283
10050 22:18:52.905849 The DHCP server ip is 192.168.201.1
10051 22:18:52.906289
10052 22:18:52.912265 TFTP server IP predefined by user: 192.168.201.1
10053 22:18:52.912792
10054 22:18:52.918933 Bootfile predefined by user: 10583924/tftp-deploy-7_wm5peu/kernel/image.itb
10055 22:18:52.919470
10056 22:18:52.919814 Sending tftp read request... done.
10057 22:18:52.920127
10058 22:18:52.927651 Waiting for the transfer...
10059 22:18:52.928085
10060 22:18:53.349030 00000000 ################################################################
10061 22:18:53.349693
10062 22:18:53.747927 00080000 ################################################################
10063 22:18:53.748409
10064 22:18:54.156408 00100000 ################################################################
10065 22:18:54.156923
10066 22:18:54.566481 00180000 ################################################################
10067 22:18:54.567007
10068 22:18:54.974168 00200000 ################################################################
10069 22:18:54.974693
10070 22:18:55.387225 00280000 ################################################################
10071 22:18:55.387750
10072 22:18:55.777715 00300000 ################################################################
10073 22:18:55.778238
10074 22:18:56.177137 00380000 ################################################################
10075 22:18:56.177667
10076 22:18:56.567019 00400000 ################################################################
10077 22:18:56.567523
10078 22:18:56.959715 00480000 ################################################################
10079 22:18:56.960178
10080 22:18:57.372434 00500000 ################################################################
10081 22:18:57.372935
10082 22:18:57.772148 00580000 ################################################################
10083 22:18:57.772641
10084 22:18:58.175926 00600000 ################################################################
10085 22:18:58.176418
10086 22:18:58.581242 00680000 ################################################################
10087 22:18:58.581863
10088 22:18:58.886804 00700000 ################################################################
10089 22:18:58.886938
10090 22:18:59.180425 00780000 ################################################################
10091 22:18:59.180570
10092 22:18:59.471448 00800000 ################################################################
10093 22:18:59.471580
10094 22:18:59.756356 00880000 ################################################################
10095 22:18:59.756496
10096 22:19:00.048272 00900000 ################################################################
10097 22:19:00.048403
10098 22:19:00.324586 00980000 ################################################################
10099 22:19:00.324723
10100 22:19:00.598563 00a00000 ################################################################
10101 22:19:00.598695
10102 22:19:00.894744 00a80000 ################################################################
10103 22:19:00.894880
10104 22:19:01.172681 00b00000 ################################################################
10105 22:19:01.172819
10106 22:19:01.438487 00b80000 ################################################################
10107 22:19:01.438621
10108 22:19:01.689966 00c00000 ################################################################
10109 22:19:01.690115
10110 22:19:01.984743 00c80000 ################################################################
10111 22:19:01.984891
10112 22:19:02.280493 00d00000 ################################################################
10113 22:19:02.280642
10114 22:19:02.562512 00d80000 ################################################################
10115 22:19:02.562648
10116 22:19:02.817699 00e00000 ################################################################
10117 22:19:02.817832
10118 22:19:03.103923 00e80000 ################################################################
10119 22:19:03.104060
10120 22:19:03.378949 00f00000 ################################################################
10121 22:19:03.379090
10122 22:19:03.673818 00f80000 ################################################################
10123 22:19:03.673967
10124 22:19:03.957647 01000000 ################################################################
10125 22:19:03.957789
10126 22:19:04.252802 01080000 ################################################################
10127 22:19:04.252949
10128 22:19:04.539436 01100000 ################################################################
10129 22:19:04.539582
10130 22:19:04.832510 01180000 ################################################################
10131 22:19:04.832654
10132 22:19:05.126639 01200000 ################################################################
10133 22:19:05.126785
10134 22:19:05.409753 01280000 ################################################################
10135 22:19:05.409899
10136 22:19:05.705407 01300000 ################################################################
10137 22:19:05.705585
10138 22:19:05.984680 01380000 ################################################################
10139 22:19:05.984824
10140 22:19:06.265059 01400000 ################################################################
10141 22:19:06.265205
10142 22:19:06.559491 01480000 ################################################################
10143 22:19:06.559635
10144 22:19:06.853367 01500000 ################################################################
10145 22:19:06.853518
10146 22:19:07.148337 01580000 ################################################################
10147 22:19:07.148481
10148 22:19:07.443354 01600000 ################################################################
10149 22:19:07.443500
10150 22:19:07.738900 01680000 ################################################################
10151 22:19:07.739040
10152 22:19:08.024682 01700000 ################################################################
10153 22:19:08.024829
10154 22:19:08.274324 01780000 ################################################################
10155 22:19:08.274470
10156 22:19:08.529636 01800000 ################################################################
10157 22:19:08.529776
10158 22:19:08.786664 01880000 ################################################################
10159 22:19:08.786804
10160 22:19:09.044461 01900000 ################################################################
10161 22:19:09.044606
10162 22:19:09.293398 01980000 ################################################################
10163 22:19:09.293546
10164 22:19:09.545810 01a00000 ################################################################
10165 22:19:09.545949
10166 22:19:09.839605 01a80000 ################################################################
10167 22:19:09.839750
10168 22:19:10.134864 01b00000 ################################################################
10169 22:19:10.135009
10170 22:19:10.429092 01b80000 ################################################################
10171 22:19:10.429239
10172 22:19:10.722961 01c00000 ################################################################
10173 22:19:10.723111
10174 22:19:11.013254 01c80000 ################################################################
10175 22:19:11.013402
10176 22:19:11.270830 01d00000 ################################################################
10177 22:19:11.270971
10178 22:19:11.556997 01d80000 ################################################################
10179 22:19:11.557142
10180 22:19:11.852576 01e00000 ################################################################
10181 22:19:11.852720
10182 22:19:12.146395 01e80000 ################################################################
10183 22:19:12.146541
10184 22:19:12.441849 01f00000 ################################################################
10185 22:19:12.441995
10186 22:19:12.736680 01f80000 ################################################################
10187 22:19:12.736826
10188 22:19:13.027392 02000000 ################################################################
10189 22:19:13.027536
10190 22:19:13.316209 02080000 ################################################################
10191 22:19:13.316358
10192 22:19:13.611035 02100000 ################################################################
10193 22:19:13.611178
10194 22:19:13.879877 02180000 ################################################################
10195 22:19:13.880013
10196 22:19:14.133547 02200000 ################################################################
10197 22:19:14.133688
10198 22:19:14.399684 02280000 ################################################################
10199 22:19:14.399819
10200 22:19:14.651965 02300000 ################################################################
10201 22:19:14.652100
10202 22:19:14.939009 02380000 ################################################################
10203 22:19:14.939141
10204 22:19:15.226972 02400000 ################################################################
10205 22:19:15.227109
10206 22:19:15.492730 02480000 ################################################################
10207 22:19:15.492871
10208 22:19:15.758002 02500000 ################################################################
10209 22:19:15.758165
10210 22:19:16.016062 02580000 ################################################################
10211 22:19:16.016196
10212 22:19:16.279048 02600000 ################################################################
10213 22:19:16.279244
10214 22:19:16.532136 02680000 ################################################################
10215 22:19:16.532296
10216 22:19:16.787365 02700000 ################################################################
10217 22:19:16.787500
10218 22:19:17.036586 02780000 ################################################################
10219 22:19:17.036722
10220 22:19:17.299437 02800000 ################################################################
10221 22:19:17.299574
10222 22:19:17.556897 02880000 ################################################################
10223 22:19:17.557034
10224 22:19:17.835186 02900000 ################################################################
10225 22:19:17.835321
10226 22:19:18.108535 02980000 ################################################################
10227 22:19:18.108677
10228 22:19:18.388103 02a00000 ################################################################
10229 22:19:18.388265
10230 22:19:18.636290 02a80000 ################################################################
10231 22:19:18.636422
10232 22:19:18.923385 02b00000 ################################################################
10233 22:19:18.923522
10234 22:19:19.183002 02b80000 ################################################################
10235 22:19:19.183140
10236 22:19:19.437141 02c00000 ################################################################
10237 22:19:19.437274
10238 22:19:19.708101 02c80000 ################################################################
10239 22:19:19.708233
10240 22:19:19.961670 02d00000 ################################################################
10241 22:19:19.961801
10242 22:19:20.221902 02d80000 ################################################################
10243 22:19:20.222039
10244 22:19:20.493247 02e00000 ################################################################
10245 22:19:20.493390
10246 22:19:20.742508 02e80000 ################################################################
10247 22:19:20.742651
10248 22:19:21.000635 02f00000 ################################################################
10249 22:19:21.000780
10250 22:19:21.288826 02f80000 ################################################################
10251 22:19:21.288972
10252 22:19:21.538196 03000000 ################################################################
10253 22:19:21.538329
10254 22:19:21.801545 03080000 ################################################################
10255 22:19:21.801690
10256 22:19:22.051055 03100000 ################################################################
10257 22:19:22.051199
10258 22:19:22.306340 03180000 ################################################################
10259 22:19:22.306478
10260 22:19:22.565343 03200000 ################################################################
10261 22:19:22.565480
10262 22:19:22.859796 03280000 ################################################################
10263 22:19:22.859937
10264 22:19:23.133927 03300000 ################################################################
10265 22:19:23.134067
10266 22:19:23.406048 03380000 ################################################################
10267 22:19:23.406183
10268 22:19:23.664672 03400000 ################################################################
10269 22:19:23.664809
10270 22:19:23.919761 03480000 ################################################################
10271 22:19:23.919919
10272 22:19:24.182042 03500000 ################################################################
10273 22:19:24.182179
10274 22:19:24.453272 03580000 ################################################################
10275 22:19:24.453408
10276 22:19:24.718649 03600000 ################################################################
10277 22:19:24.718781
10278 22:19:24.994381 03680000 ################################################################
10279 22:19:24.994560
10280 22:19:25.243130 03700000 ################################################################
10281 22:19:25.243265
10282 22:19:25.497095 03780000 ################################################################
10283 22:19:25.497255
10284 22:19:25.755485 03800000 ################################################################
10285 22:19:25.755620
10286 22:19:26.013203 03880000 ################################################################
10287 22:19:26.013337
10288 22:19:26.270317 03900000 ################################################################
10289 22:19:26.270448
10290 22:19:26.530986 03980000 ################################################################
10291 22:19:26.531116
10292 22:19:26.785020 03a00000 ################################################################
10293 22:19:26.785151
10294 22:19:27.049319 03a80000 ################################################################
10295 22:19:27.049450
10296 22:19:27.327835 03b00000 ################################################################
10297 22:19:27.327992
10298 22:19:27.605634 03b80000 ################################################################
10299 22:19:27.605774
10300 22:19:27.881058 03c00000 ################################################################
10301 22:19:27.881192
10302 22:19:28.156627 03c80000 ################################################################
10303 22:19:28.156762
10304 22:19:28.406612 03d00000 ################################################################
10305 22:19:28.406767
10306 22:19:28.659187 03d80000 ################################################################
10307 22:19:28.659331
10308 22:19:28.915889 03e00000 ################################################################
10309 22:19:28.916050
10310 22:19:29.170456 03e80000 ################################################################
10311 22:19:29.170606
10312 22:19:29.385248 03f00000 ###################################################### done.
10313 22:19:29.385434
10314 22:19:29.388220 The bootfile was 66497726 bytes long.
10315 22:19:29.388308
10316 22:19:29.391580 Sending tftp read request... done.
10317 22:19:29.391666
10318 22:19:29.395499 Waiting for the transfer...
10319 22:19:29.395586
10320 22:19:29.395653 00000000 # done.
10321 22:19:29.395717
10322 22:19:29.405029 Command line loaded dynamically from TFTP file: 10583924/tftp-deploy-7_wm5peu/kernel/cmdline
10323 22:19:29.405119
10324 22:19:29.415220 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10325 22:19:29.415330
10326 22:19:29.418411 Loading FIT.
10327 22:19:29.418503
10328 22:19:29.421351 Image ramdisk-1 has 56367037 bytes.
10329 22:19:29.421489
10330 22:19:29.421588 Image fdt-1 has 46924 bytes.
10331 22:19:29.421652
10332 22:19:29.424925 Image kernel-1 has 10081729 bytes.
10333 22:19:29.425036
10334 22:19:29.434747 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10335 22:19:29.434834
10336 22:19:29.451304 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10337 22:19:29.451400
10338 22:19:29.457751 Choosing best match conf-1 for compat google,spherion-rev2.
10339 22:19:29.461431
10340 22:19:29.466205 Connected to device vid:did:rid of 1ae0:0028:00
10341 22:19:29.474044
10342 22:19:29.477416 tpm_get_response: command 0x17b, return code 0x0
10343 22:19:29.477504
10344 22:19:29.480821 ec_init: CrosEC protocol v3 supported (256, 248)
10345 22:19:29.484665
10346 22:19:29.488328 tpm_cleanup: add release locality here.
10347 22:19:29.488407
10348 22:19:29.488472 Shutting down all USB controllers.
10349 22:19:29.491450
10350 22:19:29.491527 Removing current net device
10351 22:19:29.491591
10352 22:19:29.498424 Exiting depthcharge with code 4 at timestamp: 72138163
10353 22:19:29.498606
10354 22:19:29.501229 LZMA decompressing kernel-1 to 0x821a6718
10355 22:19:29.501356
10356 22:19:29.504639 LZMA decompressing kernel-1 to 0x40000000
10357 22:19:30.772439
10358 22:19:30.772578 jumping to kernel
10359 22:19:30.773064 end: 2.2.4 bootloader-commands (duration 00:00:44) [common]
10360 22:19:30.773192 start: 2.2.5 auto-login-action (timeout 00:03:41) [common]
10361 22:19:30.773266 Setting prompt string to ['Linux version [0-9]']
10362 22:19:30.773357 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10363 22:19:30.773427 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10364 22:19:30.853767
10365 22:19:30.857446 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10366 22:19:30.860666 start: 2.2.5.1 login-action (timeout 00:03:41) [common]
10367 22:19:30.860777 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10368 22:19:30.860868 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10369 22:19:30.860945 Using line separator: #'\n'#
10370 22:19:30.861006 No login prompt set.
10371 22:19:30.861067 Parsing kernel messages
10372 22:19:30.861123 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10373 22:19:30.861231 [login-action] Waiting for messages, (timeout 00:03:41)
10374 22:19:30.880647 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j1606555-arm64-gcc-10-defconfig-arm64-chromebook-vtq55) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sun Jun 4 21:56:05 UTC 2023
10375 22:19:30.883851 [ 0.000000] random: crng init done
10376 22:19:30.887113 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10377 22:19:30.890540 [ 0.000000] efi: UEFI not found.
10378 22:19:30.900420 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10379 22:19:30.907142 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10380 22:19:30.917086 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10381 22:19:30.926660 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10382 22:19:30.933183 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10383 22:19:30.936558 [ 0.000000] printk: bootconsole [mtk8250] enabled
10384 22:19:30.945269 [ 0.000000] NUMA: No NUMA configuration found
10385 22:19:30.951788 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10386 22:19:30.958670 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcda00-0x23efcffff]
10387 22:19:30.958819 [ 0.000000] Zone ranges:
10388 22:19:30.965244 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10389 22:19:30.968427 [ 0.000000] DMA32 empty
10390 22:19:30.974915 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10391 22:19:30.979009 [ 0.000000] Movable zone start for each node
10392 22:19:30.981896 [ 0.000000] Early memory node ranges
10393 22:19:30.988372 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10394 22:19:30.995139 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10395 22:19:31.002082 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10396 22:19:31.008279 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10397 22:19:31.015115 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10398 22:19:31.021507 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10399 22:19:31.078255 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10400 22:19:31.084190 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10401 22:19:31.091058 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10402 22:19:31.094738 [ 0.000000] psci: probing for conduit method from DT.
10403 22:19:31.101640 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10404 22:19:31.104299 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10405 22:19:31.111084 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10406 22:19:31.114481 [ 0.000000] psci: SMC Calling Convention v1.2
10407 22:19:31.120683 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10408 22:19:31.124016 [ 0.000000] Detected VIPT I-cache on CPU0
10409 22:19:31.131141 [ 0.000000] CPU features: detected: GIC system register CPU interface
10410 22:19:31.137381 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10411 22:19:31.144410 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10412 22:19:31.150961 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10413 22:19:31.160367 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10414 22:19:31.167048 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10415 22:19:31.170676 [ 0.000000] alternatives: applying boot alternatives
10416 22:19:31.177362 [ 0.000000] Fallback order for Node 0: 0
10417 22:19:31.183932 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10418 22:19:31.187350 [ 0.000000] Policy zone: Normal
10419 22:19:31.196966 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10420 22:19:31.206984 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10421 22:19:31.220479 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10422 22:19:31.230094 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10423 22:19:31.236698 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10424 22:19:31.240294 <6>[ 0.000000] software IO TLB: area num 8.
10425 22:19:31.296471 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10426 22:19:31.445437 <6>[ 0.000000] Memory: 7917892K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 434876K reserved, 32768K cma-reserved)
10427 22:19:31.452299 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10428 22:19:31.458714 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10429 22:19:31.461549 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10430 22:19:31.468554 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10431 22:19:31.475086 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10432 22:19:31.478877 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10433 22:19:31.488433 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10434 22:19:31.495095 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10435 22:19:31.498150 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10436 22:19:31.505967 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10437 22:19:31.509629 <6>[ 0.000000] GICv3: 608 SPIs implemented
10438 22:19:31.515976 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10439 22:19:31.519380 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10440 22:19:31.522788 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10441 22:19:31.532308 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10442 22:19:31.542747 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10443 22:19:31.555805 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10444 22:19:31.562563 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10445 22:19:31.571938 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10446 22:19:31.584651 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10447 22:19:31.591446 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10448 22:19:31.598080 <6>[ 0.009179] Console: colour dummy device 80x25
10449 22:19:31.608307 <6>[ 0.013937] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10450 22:19:31.614632 <6>[ 0.024379] pid_max: default: 32768 minimum: 301
10451 22:19:31.617938 <6>[ 0.029252] LSM: Security Framework initializing
10452 22:19:31.624999 <6>[ 0.034190] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10453 22:19:31.634920 <6>[ 0.042004] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10454 22:19:31.641222 <6>[ 0.051431] cblist_init_generic: Setting adjustable number of callback queues.
10455 22:19:31.647969 <6>[ 0.058887] cblist_init_generic: Setting shift to 3 and lim to 1.
10456 22:19:31.654405 <6>[ 0.065265] cblist_init_generic: Setting shift to 3 and lim to 1.
10457 22:19:31.661122 <6>[ 0.071712] rcu: Hierarchical SRCU implementation.
10458 22:19:31.667693 <6>[ 0.076757] rcu: Max phase no-delay instances is 1000.
10459 22:19:31.671230 <6>[ 0.083776] EFI services will not be available.
10460 22:19:31.677412 <6>[ 0.088746] smp: Bringing up secondary CPUs ...
10461 22:19:31.685120 <6>[ 0.093798] Detected VIPT I-cache on CPU1
10462 22:19:31.692137 <6>[ 0.093870] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10463 22:19:31.698894 <6>[ 0.093899] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10464 22:19:31.702459 <6>[ 0.094236] Detected VIPT I-cache on CPU2
10465 22:19:31.708352 <6>[ 0.094284] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10466 22:19:31.715099 <6>[ 0.094299] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10467 22:19:31.722153 <6>[ 0.094558] Detected VIPT I-cache on CPU3
10468 22:19:31.728369 <6>[ 0.094604] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10469 22:19:31.734937 <6>[ 0.094618] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10470 22:19:31.738280 <6>[ 0.094926] CPU features: detected: Spectre-v4
10471 22:19:31.745200 <6>[ 0.094932] CPU features: detected: Spectre-BHB
10472 22:19:31.747975 <6>[ 0.094937] Detected PIPT I-cache on CPU4
10473 22:19:31.754888 <6>[ 0.094994] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10474 22:19:31.761629 <6>[ 0.095012] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10475 22:19:31.768002 <6>[ 0.095305] Detected PIPT I-cache on CPU5
10476 22:19:31.774690 <6>[ 0.095367] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10477 22:19:31.781301 <6>[ 0.095384] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10478 22:19:31.784555 <6>[ 0.095671] Detected PIPT I-cache on CPU6
10479 22:19:31.791293 <6>[ 0.095737] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10480 22:19:31.797826 <6>[ 0.095753] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10481 22:19:31.803854 <6>[ 0.096052] Detected PIPT I-cache on CPU7
10482 22:19:31.810647 <6>[ 0.096116] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10483 22:19:31.818016 <6>[ 0.096133] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10484 22:19:31.821106 <6>[ 0.096180] smp: Brought up 1 node, 8 CPUs
10485 22:19:31.827512 <6>[ 0.237499] SMP: Total of 8 processors activated.
10486 22:19:31.830828 <6>[ 0.242420] CPU features: detected: 32-bit EL0 Support
10487 22:19:31.840868 <6>[ 0.247782] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10488 22:19:31.847426 <6>[ 0.256636] CPU features: detected: Common not Private translations
10489 22:19:31.854263 <6>[ 0.263112] CPU features: detected: CRC32 instructions
10490 22:19:31.857345 <6>[ 0.268463] CPU features: detected: RCpc load-acquire (LDAPR)
10491 22:19:31.863795 <6>[ 0.274460] CPU features: detected: LSE atomic instructions
10492 22:19:31.870242 <6>[ 0.280241] CPU features: detected: Privileged Access Never
10493 22:19:31.876926 <6>[ 0.286021] CPU features: detected: RAS Extension Support
10494 22:19:31.883653 <6>[ 0.291630] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10495 22:19:31.887013 <6>[ 0.298849] CPU: All CPU(s) started at EL2
10496 22:19:31.893579 <6>[ 0.303165] alternatives: applying system-wide alternatives
10497 22:19:31.902430 <6>[ 0.313867] devtmpfs: initialized
10498 22:19:31.915156 <6>[ 0.322663] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10499 22:19:31.924720 <6>[ 0.332627] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10500 22:19:31.931378 <6>[ 0.340585] pinctrl core: initialized pinctrl subsystem
10501 22:19:31.934804 <6>[ 0.347261] DMI not present or invalid.
10502 22:19:31.941915 <6>[ 0.351681] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10503 22:19:31.951480 <6>[ 0.358558] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10504 22:19:31.958114 <6>[ 0.366145] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10505 22:19:31.968418 <6>[ 0.374360] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10506 22:19:31.971487 <6>[ 0.382610] audit: initializing netlink subsys (disabled)
10507 22:19:31.981281 <5>[ 0.388310] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10508 22:19:31.987974 <6>[ 0.389042] thermal_sys: Registered thermal governor 'step_wise'
10509 22:19:31.994391 <6>[ 0.396278] thermal_sys: Registered thermal governor 'power_allocator'
10510 22:19:31.997761 <6>[ 0.402536] cpuidle: using governor menu
10511 22:19:32.004542 <6>[ 0.413502] NET: Registered PF_QIPCRTR protocol family
10512 22:19:32.010837 <6>[ 0.419015] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10513 22:19:32.014363 <6>[ 0.426120] ASID allocator initialised with 32768 entries
10514 22:19:32.021767 <6>[ 0.432705] Serial: AMBA PL011 UART driver
10515 22:19:32.030420 <4>[ 0.441365] Trying to register duplicate clock ID: 134
10516 22:19:32.084531 <6>[ 0.498657] KASLR enabled
10517 22:19:32.098472 <6>[ 0.506344] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10518 22:19:32.105464 <6>[ 0.513358] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10519 22:19:32.112075 <6>[ 0.519847] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10520 22:19:32.118750 <6>[ 0.526852] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10521 22:19:32.125450 <6>[ 0.533341] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10522 22:19:32.131811 <6>[ 0.540347] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10523 22:19:32.138176 <6>[ 0.546837] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10524 22:19:32.145361 <6>[ 0.553842] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10525 22:19:32.148264 <6>[ 0.561320] ACPI: Interpreter disabled.
10526 22:19:32.156691 <6>[ 0.567753] iommu: Default domain type: Translated
10527 22:19:32.163014 <6>[ 0.572868] iommu: DMA domain TLB invalidation policy: strict mode
10528 22:19:32.166321 <5>[ 0.579526] SCSI subsystem initialized
10529 22:19:32.172933 <6>[ 0.583767] usbcore: registered new interface driver usbfs
10530 22:19:32.179511 <6>[ 0.589498] usbcore: registered new interface driver hub
10531 22:19:32.182957 <6>[ 0.595052] usbcore: registered new device driver usb
10532 22:19:32.190106 <6>[ 0.601152] pps_core: LinuxPPS API ver. 1 registered
10533 22:19:32.199784 <6>[ 0.606348] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10534 22:19:32.203362 <6>[ 0.615694] PTP clock support registered
10535 22:19:32.206957 <6>[ 0.619935] EDAC MC: Ver: 3.0.0
10536 22:19:32.213961 <6>[ 0.625129] FPGA manager framework
10537 22:19:32.217344 <6>[ 0.628808] Advanced Linux Sound Architecture Driver Initialized.
10538 22:19:32.221232 <6>[ 0.635577] vgaarb: loaded
10539 22:19:32.227846 <6>[ 0.638736] clocksource: Switched to clocksource arch_sys_counter
10540 22:19:32.234538 <5>[ 0.645186] VFS: Disk quotas dquot_6.6.0
10541 22:19:32.241016 <6>[ 0.649373] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10542 22:19:32.244200 <6>[ 0.656566] pnp: PnP ACPI: disabled
10543 22:19:32.252441 <6>[ 0.663240] NET: Registered PF_INET protocol family
10544 22:19:32.261703 <6>[ 0.668824] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10545 22:19:32.273660 <6>[ 0.681113] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10546 22:19:32.283200 <6>[ 0.689928] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10547 22:19:32.290102 <6>[ 0.697899] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10548 22:19:32.296443 <6>[ 0.706600] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10549 22:19:32.308531 <6>[ 0.716352] TCP: Hash tables configured (established 65536 bind 65536)
10550 22:19:32.314988 <6>[ 0.723213] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10551 22:19:32.321831 <6>[ 0.730415] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10552 22:19:32.328192 <6>[ 0.738117] NET: Registered PF_UNIX/PF_LOCAL protocol family
10553 22:19:32.335178 <6>[ 0.744277] RPC: Registered named UNIX socket transport module.
10554 22:19:32.338107 <6>[ 0.750429] RPC: Registered udp transport module.
10555 22:19:32.344939 <6>[ 0.755364] RPC: Registered tcp transport module.
10556 22:19:32.351296 <6>[ 0.760298] RPC: Registered tcp NFSv4.1 backchannel transport module.
10557 22:19:32.354562 <6>[ 0.766970] PCI: CLS 0 bytes, default 64
10558 22:19:32.358092 <6>[ 0.771357] Unpacking initramfs...
10559 22:19:32.383166 <6>[ 0.790844] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10560 22:19:32.393019 <6>[ 0.799511] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10561 22:19:32.396315 <6>[ 0.808342] kvm [1]: IPA Size Limit: 40 bits
10562 22:19:32.403020 <6>[ 0.812869] kvm [1]: GICv3: no GICV resource entry
10563 22:19:32.406587 <6>[ 0.817892] kvm [1]: disabling GICv2 emulation
10564 22:19:32.413075 <6>[ 0.822577] kvm [1]: GIC system register CPU interface enabled
10565 22:19:32.416443 <6>[ 0.828737] kvm [1]: vgic interrupt IRQ18
10566 22:19:32.423398 <6>[ 0.833110] kvm [1]: VHE mode initialized successfully
10567 22:19:32.429683 <5>[ 0.839607] Initialise system trusted keyrings
10568 22:19:32.436406 <6>[ 0.844399] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10569 22:19:32.443536 <6>[ 0.854600] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10570 22:19:32.450083 <5>[ 0.861000] NFS: Registering the id_resolver key type
10571 22:19:32.453630 <5>[ 0.866304] Key type id_resolver registered
10572 22:19:32.460294 <5>[ 0.870719] Key type id_legacy registered
10573 22:19:32.466769 <6>[ 0.875002] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10574 22:19:32.473409 <6>[ 0.881925] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10575 22:19:32.479616 <6>[ 0.889635] 9p: Installing v9fs 9p2000 file system support
10576 22:19:32.516424 <5>[ 0.927171] Key type asymmetric registered
10577 22:19:32.519440 <5>[ 0.931503] Asymmetric key parser 'x509' registered
10578 22:19:32.529393 <6>[ 0.936646] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10579 22:19:32.532945 <6>[ 0.944261] io scheduler mq-deadline registered
10580 22:19:32.535795 <6>[ 0.949021] io scheduler kyber registered
10581 22:19:32.554829 <6>[ 0.965839] EINJ: ACPI disabled.
10582 22:19:32.586818 <4>[ 0.991104] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10583 22:19:32.596626 <4>[ 1.001720] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10584 22:19:32.611762 <6>[ 1.022539] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10585 22:19:32.619014 <6>[ 1.030524] printk: console [ttyS0] disabled
10586 22:19:32.647325 <6>[ 1.055179] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10587 22:19:32.654186 <6>[ 1.064656] printk: console [ttyS0] enabled
10588 22:19:32.657115 <6>[ 1.064656] printk: console [ttyS0] enabled
10589 22:19:32.664248 <6>[ 1.073551] printk: bootconsole [mtk8250] disabled
10590 22:19:32.667085 <6>[ 1.073551] printk: bootconsole [mtk8250] disabled
10591 22:19:32.674029 <6>[ 1.084788] SuperH (H)SCI(F) driver initialized
10592 22:19:32.677171 <6>[ 1.090052] msm_serial: driver initialized
10593 22:19:32.691227 <6>[ 1.098931] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10594 22:19:32.701444 <6>[ 1.107483] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10595 22:19:32.708304 <6>[ 1.116025] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10596 22:19:32.717658 <6>[ 1.124653] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10597 22:19:32.724555 <6>[ 1.133358] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10598 22:19:32.734239 <6>[ 1.142078] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10599 22:19:32.744382 <6>[ 1.150621] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10600 22:19:32.750812 <6>[ 1.159425] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10601 22:19:32.761153 <6>[ 1.167966] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10602 22:19:32.772614 <6>[ 1.183592] loop: module loaded
10603 22:19:32.779137 <6>[ 1.189594] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10604 22:19:32.801176 <4>[ 1.212325] mtk-pmic-keys: Failed to locate of_node [id: -1]
10605 22:19:32.807845 <6>[ 1.219122] megasas: 07.719.03.00-rc1
10606 22:19:32.817372 <6>[ 1.228625] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10607 22:19:32.831004 <6>[ 1.242123] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10608 22:19:32.848558 <6>[ 1.259021] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10609 22:19:32.905105 <6>[ 1.309760] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.153/cr50_v3.94_pp.113-620c9
10610 22:19:34.737506 <6>[ 3.148442] Freeing initrd memory: 55044K
10611 22:19:34.747392 <6>[ 3.158670] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10612 22:19:34.758205 <6>[ 3.169575] tun: Universal TUN/TAP device driver, 1.6
10613 22:19:34.761443 <6>[ 3.175620] thunder_xcv, ver 1.0
10614 22:19:34.764824 <6>[ 3.179123] thunder_bgx, ver 1.0
10615 22:19:34.768247 <6>[ 3.182613] nicpf, ver 1.0
10616 22:19:34.778469 <6>[ 3.186609] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10617 22:19:34.781791 <6>[ 3.194085] hns3: Copyright (c) 2017 Huawei Corporation.
10618 22:19:34.788613 <6>[ 3.199669] hclge is initializing
10619 22:19:34.792150 <6>[ 3.203249] e1000: Intel(R) PRO/1000 Network Driver
10620 22:19:34.798663 <6>[ 3.208377] e1000: Copyright (c) 1999-2006 Intel Corporation.
10621 22:19:34.801942 <6>[ 3.214390] e1000e: Intel(R) PRO/1000 Network Driver
10622 22:19:34.808249 <6>[ 3.219605] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10623 22:19:34.814737 <6>[ 3.225793] igb: Intel(R) Gigabit Ethernet Network Driver
10624 22:19:34.821790 <6>[ 3.231442] igb: Copyright (c) 2007-2014 Intel Corporation.
10625 22:19:34.828283 <6>[ 3.237281] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10626 22:19:34.834852 <6>[ 3.243799] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10627 22:19:34.838521 <6>[ 3.250255] sky2: driver version 1.30
10628 22:19:34.845032 <6>[ 3.255233] VFIO - User Level meta-driver version: 0.3
10629 22:19:34.852026 <6>[ 3.263378] usbcore: registered new interface driver usb-storage
10630 22:19:34.858853 <6>[ 3.269823] usbcore: registered new device driver onboard-usb-hub
10631 22:19:34.867536 <6>[ 3.278874] mt6397-rtc mt6359-rtc: registered as rtc0
10632 22:19:34.877295 <6>[ 3.284338] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-04T22:19:35 UTC (1685917175)
10633 22:19:34.880738 <6>[ 3.293894] i2c_dev: i2c /dev entries driver
10634 22:19:34.897299 <6>[ 3.305621] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10635 22:19:34.904623 <6>[ 3.315811] sdhci: Secure Digital Host Controller Interface driver
10636 22:19:34.910870 <6>[ 3.322249] sdhci: Copyright(c) Pierre Ossman
10637 22:19:34.917837 <6>[ 3.327641] Synopsys Designware Multimedia Card Interface Driver
10638 22:19:34.920989 <6>[ 3.334255] mmc0: CQHCI version 5.10
10639 22:19:34.927689 <6>[ 3.334803] sdhci-pltfm: SDHCI platform and OF driver helper
10640 22:19:34.934800 <6>[ 3.346110] ledtrig-cpu: registered to indicate activity on CPUs
10641 22:19:34.945196 <6>[ 3.353414] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10642 22:19:34.948683 <6>[ 3.360799] usbcore: registered new interface driver usbhid
10643 22:19:34.955358 <6>[ 3.366626] usbhid: USB HID core driver
10644 22:19:34.961954 <6>[ 3.370880] spi_master spi0: will run message pump with realtime priority
10645 22:19:35.007430 <6>[ 3.411804] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10646 22:19:35.025823 <6>[ 3.426967] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10647 22:19:35.029326 <6>[ 3.440538] mmc0: Command Queue Engine enabled
10648 22:19:35.036005 <6>[ 3.445293] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10649 22:19:35.042677 <6>[ 3.452444] cros-ec-spi spi0.0: Chrome EC device registered
10650 22:19:35.045530 <6>[ 3.452663] mmcblk0: mmc0:0001 DA4128 116 GiB
10651 22:19:35.057131 <6>[ 3.468439] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10652 22:19:35.064468 <6>[ 3.475687] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10653 22:19:35.071204 <6>[ 3.481583] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10654 22:19:35.077395 <6>[ 3.487655] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10655 22:19:35.094510 <6>[ 3.502632] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10656 22:19:35.102528 <6>[ 3.514088] NET: Registered PF_PACKET protocol family
10657 22:19:35.109451 <6>[ 3.519553] 9pnet: Installing 9P2000 support
10658 22:19:35.112631 <5>[ 3.524139] Key type dns_resolver registered
10659 22:19:35.115656 <6>[ 3.529301] registered taskstats version 1
10660 22:19:35.122105 <5>[ 3.533725] Loading compiled-in X.509 certificates
10661 22:19:35.157838 <4>[ 3.562417] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10662 22:19:35.167780 <4>[ 3.573223] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10663 22:19:35.177392 <3>[ 3.585771] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10664 22:19:35.189932 <6>[ 3.601328] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10665 22:19:35.196880 <6>[ 3.608075] xhci-mtk 11200000.usb: xHCI Host Controller
10666 22:19:35.202994 <6>[ 3.613569] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10667 22:19:35.213458 <6>[ 3.621425] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10668 22:19:35.219732 <6>[ 3.630883] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10669 22:19:35.226542 <6>[ 3.636971] xhci-mtk 11200000.usb: xHCI Host Controller
10670 22:19:35.233384 <6>[ 3.642456] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10671 22:19:35.239849 <6>[ 3.650239] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10672 22:19:35.246813 <6>[ 3.658156] hub 1-0:1.0: USB hub found
10673 22:19:35.250311 <6>[ 3.662193] hub 1-0:1.0: 1 port detected
10674 22:19:35.259986 <6>[ 3.666550] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10675 22:19:35.263106 <6>[ 3.675365] hub 2-0:1.0: USB hub found
10676 22:19:35.266868 <6>[ 3.679399] hub 2-0:1.0: 1 port detected
10677 22:19:35.274983 <6>[ 3.686592] mtk-msdc 11f70000.mmc: Got CD GPIO
10678 22:19:35.291972 <6>[ 3.700180] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10679 22:19:35.299252 <6>[ 3.708208] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10680 22:19:35.308687 <4>[ 3.716179] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10681 22:19:35.318877 <6>[ 3.725842] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10682 22:19:35.325467 <6>[ 3.733925] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10683 22:19:35.332047 <6>[ 3.741949] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10684 22:19:35.341725 <6>[ 3.749866] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10685 22:19:35.348773 <6>[ 3.757686] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10686 22:19:35.358671 <6>[ 3.765511] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10687 22:19:35.368266 <6>[ 3.776122] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10688 22:19:35.375085 <6>[ 3.784490] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10689 22:19:35.384726 <6>[ 3.792840] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10690 22:19:35.391835 <6>[ 3.801183] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10691 22:19:35.401504 <6>[ 3.809525] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10692 22:19:35.408305 <6>[ 3.817867] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10693 22:19:35.418302 <6>[ 3.826210] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10694 22:19:35.428259 <6>[ 3.834552] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10695 22:19:35.434744 <6>[ 3.842895] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10696 22:19:35.444771 <6>[ 3.851239] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10697 22:19:35.451684 <6>[ 3.859581] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10698 22:19:35.461532 <6>[ 3.867924] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10699 22:19:35.468411 <6>[ 3.876268] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10700 22:19:35.477971 <6>[ 3.884612] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10701 22:19:35.484541 <6>[ 3.892959] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10702 22:19:35.491225 <6>[ 3.901874] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10703 22:19:35.498016 <6>[ 3.909345] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10704 22:19:35.505278 <6>[ 3.916454] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10705 22:19:35.515530 <6>[ 3.923615] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10706 22:19:35.522413 <6>[ 3.930966] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10707 22:19:35.532328 <6>[ 3.937910] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10708 22:19:35.538768 <6>[ 3.947050] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10709 22:19:35.549044 <6>[ 3.956180] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10710 22:19:35.558974 <6>[ 3.965483] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10711 22:19:35.568433 <6>[ 3.974958] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10712 22:19:35.578472 <6>[ 3.984433] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10713 22:19:35.584817 <6>[ 3.993561] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10714 22:19:35.595339 <6>[ 4.003035] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10715 22:19:35.604576 <6>[ 4.012162] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10716 22:19:35.615075 <6>[ 4.021464] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10717 22:19:35.624863 <6>[ 4.031628] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10718 22:19:35.634841 <6>[ 4.042979] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10719 22:19:35.678907 <6>[ 4.087013] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10720 22:19:35.833016 <6>[ 4.244315] hub 1-1:1.0: USB hub found
10721 22:19:35.835986 <6>[ 4.248737] hub 1-1:1.0: 4 ports detected
10722 22:19:35.958938 <6>[ 4.367204] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10723 22:19:35.984265 <6>[ 4.395537] hub 2-1:1.0: USB hub found
10724 22:19:35.987308 <6>[ 4.399934] hub 2-1:1.0: 3 ports detected
10725 22:19:36.158719 <6>[ 4.567006] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10726 22:19:36.290962 <6>[ 4.702563] hub 1-1.4:1.0: USB hub found
10727 22:19:36.294435 <6>[ 4.707233] hub 1-1.4:1.0: 2 ports detected
10728 22:19:36.370984 <6>[ 4.779265] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10729 22:19:36.590941 <6>[ 4.999008] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10730 22:19:36.782676 <6>[ 5.191010] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10731 22:19:47.915415 <6>[ 16.331560] ALSA device list:
10732 22:19:47.922116 <6>[ 16.334815] No soundcards found.
10733 22:19:47.934548 <6>[ 16.347288] Freeing unused kernel memory: 8384K
10734 22:19:47.937752 <6>[ 16.352215] Run /init as init process
10735 22:19:47.967976 <6>[ 16.380975] NET: Registered PF_INET6 protocol family
10736 22:19:47.975186 <6>[ 16.387164] Segment Routing with IPv6
10737 22:19:47.978689 <6>[ 16.391100] In-situ OAM (IOAM) with IPv6
10738 22:19:48.012324 <30>[ 16.405349] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10739 22:19:48.016042 <30>[ 16.429160] systemd[1]: Detected architecture arm64.
10740 22:19:48.016144
10741 22:19:48.022414 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10742 22:19:48.022517
10743 22:19:48.038346 <30>[ 16.451161] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10744 22:19:48.175813 <30>[ 16.585601] systemd[1]: Queued start job for default target Graphical Interface.
10745 22:19:48.211362 <30>[ 16.624419] systemd[1]: Created slice system-getty.slice.
10746 22:19:48.218369 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10747 22:19:48.234691 <30>[ 16.647583] systemd[1]: Created slice system-modprobe.slice.
10748 22:19:48.241068 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10749 22:19:48.259285 <30>[ 16.672152] systemd[1]: Created slice system-serial\x2dgetty.slice.
10750 22:19:48.269453 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10751 22:19:48.282414 <30>[ 16.695493] systemd[1]: Created slice User and Session Slice.
10752 22:19:48.289047 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10753 22:19:48.310295 <30>[ 16.719561] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10754 22:19:48.320098 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10755 22:19:48.337416 <30>[ 16.747184] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10756 22:19:48.344364 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10757 22:19:48.365092 <30>[ 16.771092] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10758 22:19:48.371654 <30>[ 16.783126] systemd[1]: Reached target Local Encrypted Volumes.
10759 22:19:48.378307 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10760 22:19:48.394067 <30>[ 16.807096] systemd[1]: Reached target Paths.
10761 22:19:48.397701 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10762 22:19:48.414414 <30>[ 16.827039] systemd[1]: Reached target Remote File Systems.
10763 22:19:48.420584 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10764 22:19:48.438207 <30>[ 16.851273] systemd[1]: Reached target Slices.
10765 22:19:48.445229 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10766 22:19:48.458110 <30>[ 16.871068] systemd[1]: Reached target Swap.
10767 22:19:48.461525 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10768 22:19:48.481558 <30>[ 16.891371] systemd[1]: Listening on initctl Compatibility Named Pipe.
10769 22:19:48.488625 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10770 22:19:48.495449 <30>[ 16.906119] systemd[1]: Listening on Journal Audit Socket.
10771 22:19:48.501525 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10772 22:19:48.514753 <30>[ 16.927304] systemd[1]: Listening on Journal Socket (/dev/log).
10773 22:19:48.521282 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10774 22:19:48.538306 <30>[ 16.951319] systemd[1]: Listening on Journal Socket.
10775 22:19:48.544562 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10776 22:19:48.558417 <30>[ 16.971314] systemd[1]: Listening on udev Control Socket.
10777 22:19:48.564771 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10778 22:19:48.582644 <30>[ 16.995673] systemd[1]: Listening on udev Kernel Socket.
10779 22:19:48.589481 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10780 22:19:48.622397 <30>[ 17.035196] systemd[1]: Mounting Huge Pages File System...
10781 22:19:48.628786 Mounting [0;1;39mHuge Pages File System[0m...
10782 22:19:48.644361 <30>[ 17.057126] systemd[1]: Mounting POSIX Message Queue File System...
10783 22:19:48.650881 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10784 22:19:48.668239 <30>[ 17.081060] systemd[1]: Mounting Kernel Debug File System...
10785 22:19:48.674696 Mounting [0;1;39mKernel Debug File System[0m...
10786 22:19:48.693362 <30>[ 17.103236] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10787 22:19:48.704381 <30>[ 17.114111] systemd[1]: Starting Create list of static device nodes for the current kernel...
10788 22:19:48.711079 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10789 22:19:48.728233 <30>[ 17.141220] systemd[1]: Starting Load Kernel Module configfs...
10790 22:19:48.734711 Starting [0;1;39mLoad Kernel Module configfs[0m...
10791 22:19:48.752359 <30>[ 17.165160] systemd[1]: Starting Load Kernel Module drm...
10792 22:19:48.758674 Starting [0;1;39mLoad Kernel Module drm[0m...
10793 22:19:48.777452 <30>[ 17.187236] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10794 22:19:48.810818 <30>[ 17.223541] systemd[1]: Starting Journal Service...
10795 22:19:48.814006 Starting [0;1;39mJournal Service[0m...
10796 22:19:48.832954 <30>[ 17.245681] systemd[1]: Starting Load Kernel Modules...
10797 22:19:48.839670 Starting [0;1;39mLoad Kernel Modules[0m...
10798 22:19:48.859998 <30>[ 17.269664] systemd[1]: Starting Remount Root and Kernel File Systems...
10799 22:19:48.866657 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10800 22:19:48.906976 <30>[ 17.319656] systemd[1]: Starting Coldplug All udev Devices...
10801 22:19:48.913439 Starting [0;1;39mColdplug All udev Devices[0m...
10802 22:19:48.928753 <30>[ 17.341521] systemd[1]: Started Journal Service.
10803 22:19:48.934951 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10804 22:19:48.952221 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10805 22:19:48.967552 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10806 22:19:48.982624 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10807 22:19:49.003761 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10808 22:19:49.020032 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10809 22:19:49.035885 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10810 22:19:49.051637 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10811 22:19:49.071324 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10812 22:19:49.086287 See 'systemctl status systemd-remount-fs.service' for details.
10813 22:19:49.135406 Mounting [0;1;39mKernel Configuration File System[0m...
10814 22:19:49.157111 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10815 22:19:49.173641 <46>[ 17.583244] systemd-journald[177]: Received client request to flush runtime journal.
10816 22:19:49.181458 Starting [0;1;39mLoad/Save Random Seed[0m...
10817 22:19:49.200664 Starting [0;1;39mApply Kernel Variables[0m...
10818 22:19:49.217162 Starting [0;1;39mCreate System Users[0m...
10819 22:19:49.232452 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10820 22:19:49.254526 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10821 22:19:49.271025 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10822 22:19:49.291397 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10823 22:19:49.307085 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10824 22:19:49.323027 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10825 22:19:49.367456 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10826 22:19:49.389068 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10827 22:19:49.402386 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10828 22:19:49.418315 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10829 22:19:49.470391 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10830 22:19:49.493918 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10831 22:19:49.515217 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10832 22:19:49.535500 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10833 22:19:49.571498 Starting [0;1;39mNetwork Time Synchronization[0m...
10834 22:19:49.590701 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10835 22:19:49.622609 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10836 22:19:49.681935 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10837 22:19:49.696710 <6>[ 18.106067] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10838 22:19:49.711340 <3>[ 18.120811] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10839 22:19:49.717784 <6>[ 18.123392] remoteproc remoteproc0: scp is available
10840 22:19:49.724407 <3>[ 18.130678] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10841 22:19:49.734593 <4>[ 18.136736] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10842 22:19:49.744181 <3>[ 18.143019] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10843 22:19:49.748041 <6>[ 18.152954] remoteproc remoteproc0: powering up scp
10844 22:19:49.757401 <4>[ 18.166146] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10845 22:19:49.767555 <3>[ 18.173775] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10846 22:19:49.771113 <3>[ 18.176029] remoteproc remoteproc0: request_firmware failed: -2
10847 22:19:49.781170 <3>[ 18.184106] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10848 22:19:49.791280 [[0;32m OK [<3>[ 18.198351] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10849 22:19:49.797286 0m] Found device<6>[ 18.201260] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10850 22:19:49.807040 [0;1;39m/dev/t<3>[ 18.207824] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10851 22:19:49.810702 tyS0[0m.
10852 22:19:49.817348 <3>[ 18.207833] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10853 22:19:49.824280 <3>[ 18.221561] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10854 22:19:49.833856 <6>[ 18.226462] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10855 22:19:49.840459 <6>[ 18.239185] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10856 22:19:49.850192 <6>[ 18.243588] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10857 22:19:49.860455 <4>[ 18.265084] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10858 22:19:49.863592 <4>[ 18.265084] Fallback method does not support PEC.
10859 22:19:49.873676 <3>[ 18.270649] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10860 22:19:49.876754 <6>[ 18.278891] usbcore: registered new interface driver r8152
10861 22:19:49.886998 <3>[ 18.296195] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10862 22:19:49.893664 <3>[ 18.304379] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10863 22:19:49.899859 <4>[ 18.305256] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10864 22:19:49.916607 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m<4>[ 18.325550] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10865 22:19:49.916718 .
10866 22:19:49.927181 <3>[ 18.335006] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10867 22:19:49.933422 <3>[ 18.343222] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10868 22:19:49.940171 <3>[ 18.351427] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10869 22:19:49.949766 <3>[ 18.359662] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10870 22:19:49.956902 <3>[ 18.367795] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10871 22:19:49.964122 [[0;32m OK [<6>[ 18.368263] mc: Linux media interface: v0.10
10872 22:19:49.974113 0m] Reached targ<3>[ 18.382329] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10873 22:19:49.984800 et [0;1;39mSyst<3>[ 18.382562] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10874 22:19:49.984924 em Time Set[0m.
10875 22:19:49.990859 <6>[ 18.402708] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10876 22:19:49.997856 <6>[ 18.410419] pci_bus 0000:00: root bus resource [bus 00-ff]
10877 22:19:50.004366 <6>[ 18.416241] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10878 22:19:50.014400 <6>[ 18.416250] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10879 22:19:50.020525 <6>[ 18.416337] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10880 22:19:50.027384 <6>[ 18.427156] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10881 22:19:50.037622 <6>[ 18.433327] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10882 22:19:50.047744 [[0;32m OK [<6>[ 18.443801] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10883 22:19:50.053911 0m] Reached targ<6>[ 18.446831] pci 0000:00:00.0: supports D1 D2
10884 22:19:50.064180 et [0;1;39mSyst<4>[ 18.462226] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10885 22:19:50.073922 em Time Synchron<6>[ 18.462910] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10886 22:19:50.074069 ized[0m.
10887 22:19:50.084050 <6>[ 18.465868] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10888 22:19:50.090254 <4>[ 18.471226] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10889 22:19:50.100601 <6>[ 18.471796] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10890 22:19:50.107397 <6>[ 18.485176] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10891 22:19:50.114250 <6>[ 18.494530] videodev: Linux video capture interface: v2.00
10892 22:19:50.121334 <6>[ 18.494644] usbcore: registered new interface driver cdc_ether
10893 22:19:50.124407 <6>[ 18.500909] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10894 22:19:50.131262 <6>[ 18.509243] usbcore: registered new interface driver r8153_ecm
10895 22:19:50.140681 <6>[ 18.517730] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10896 22:19:50.144491 <6>[ 18.532622] Bluetooth: Core ver 2.22
10897 22:19:50.151018 <6>[ 18.537891] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10898 22:19:50.157415 <6>[ 18.544235] NET: Registered PF_BLUETOOTH protocol family
10899 22:19:50.164395 <6>[ 18.550256] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10900 22:19:50.174153 <3>[ 18.550764] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10901 22:19:50.181008 <3>[ 18.551529] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10902 22:19:50.188032 <6>[ 18.557717] Bluetooth: HCI device and connection manager initialized
10903 22:19:50.194411 <6>[ 18.557743] Bluetooth: HCI socket layer initialized
10904 22:19:50.200562 <6>[ 18.558450] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10905 22:19:50.213883 <6>[ 18.560097] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10906 22:19:50.217633 <6>[ 18.560303] usbcore: registered new interface driver uvcvideo
10907 22:19:50.223957 <6>[ 18.561678] pci 0000:01:00.0: supports D1 D2
10908 22:19:50.227576 <6>[ 18.569120] Bluetooth: L2CAP socket layer initialized
10909 22:19:50.237181 <6>[ 18.574618] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10910 22:19:50.241054 <6>[ 18.578947] r8152 2-1.3:1.0 eth0: v1.12.13
10911 22:19:50.243818 <6>[ 18.582157] Bluetooth: SCO socket layer initialized
10912 22:19:50.250215 <6>[ 18.590572] r8152 2-1.3:1.0 enx00e04c787aaa: renamed from eth0
10913 22:19:50.256907 <6>[ 18.600558] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10914 22:19:50.263668 <6>[ 18.606930] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10915 22:19:50.270234 <6>[ 18.616811] remoteproc remoteproc0: powering up scp
10916 22:19:50.277130 <6>[ 18.618585] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10917 22:19:50.287125 <4>[ 18.631021] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10918 22:19:50.296843 <6>[ 18.637055] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10919 22:19:50.303367 <6>[ 18.637081] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10920 22:19:50.313148 <6>[ 18.637099] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10921 22:19:50.319843 <6>[ 18.637115] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10922 22:19:50.326809 <3>[ 18.641777] remoteproc remoteproc0: request_firmware failed: -2
10923 22:19:50.329702 <6>[ 18.647026] pci 0000:00:00.0: PCI bridge to [bus 01]
10924 22:19:50.336221 <6>[ 18.648192] usbcore: registered new interface driver btusb
10925 22:19:50.346428 <4>[ 18.650120] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10926 22:19:50.353117 <3>[ 18.650132] Bluetooth: hci0: Failed to load firmware file (-2)
10927 22:19:50.359562 <3>[ 18.650137] Bluetooth: hci0: Failed to set up firmware (-2)
10928 22:19:50.369171 <4>[ 18.650142] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10929 22:19:50.376107 <3>[ 18.653895] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
10930 22:19:50.386168 <6>[ 18.658272] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10931 22:19:50.392544 <6>[ 18.803704] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10932 22:19:50.399488 Starting [0;1;39mLoad/<6>[ 18.811538] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10933 22:19:50.406809 Save Screen …o<6>[ 18.819493] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10934 22:19:50.410154 f leds:white:kbd_backlight[0m...
10935 22:19:50.420680 <3>[ 18.829046] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10936 22:19:50.430490 <3>[ 18.838780] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10937 22:19:50.437710 <5>[ 18.841471] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10938 22:19:50.447549 <3>[ 18.852213] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10939 22:19:50.457912 [[0;32m OK [0m] Finished [0<5>[ 18.866547] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10940 22:19:50.467946 ;1;39mLoad/Save <4>[ 18.874418] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10941 22:19:50.471164 Screen …s of l<6>[ 18.884596] cfg80211: failed to load regulatory.db
10942 22:19:50.484637 eds:white:kbd_ba<3>[ 18.885136] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10943 22:19:50.484749 cklight[0m.
10944 22:19:50.521908 <3>[ 18.931799] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10945 22:19:50.528616 <6>[ 18.938124] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10946 22:19:50.535068 <6>[ 18.948091] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10947 22:19:50.550826 <3>[ 18.960883] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10948 22:19:50.557970 <6>[ 18.970987] mt7921e 0000:01:00.0: ASIC revision: 79610010
10949 22:19:50.580136 <3>[ 18.990304] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10950 22:19:50.665363 <4>[ 19.071427] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10951 22:19:50.679078 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10952 22:19:50.697960 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10953 22:19:50.717501 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10954 22:19:50.733176 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10955 22:19:50.749889 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10956 22:19:50.774226 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10957 22:19:50.790916 <4>[ 19.197684] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10958 22:19:50.799816 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10959 22:19:50.818068 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10960 22:19:50.841210 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10961 22:19:50.874455 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10962 22:19:50.911414 <4>[ 19.318182] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10963 22:19:50.924186 Starting [0;1;39mUser Login Management[0m...
10964 22:19:50.940632 Starting [0;1;39mPermit User Sessions[0m...
10965 22:19:50.958869 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10966 22:19:50.974306 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10967 22:19:50.991434 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10968 22:19:51.030864 <4>[ 19.437290] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10969 22:19:51.038444 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10970 22:19:51.056842 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10971 22:19:51.074007 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10972 22:19:51.090902 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10973 22:19:51.106906 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10974 22:19:51.122160 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10975 22:19:51.151260 <4>[ 19.557968] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10976 22:19:51.190625 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10977 22:19:51.214387 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10978 22:19:51.232687
10979 22:19:51.232839
10980 22:19:51.235464 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10981 22:19:51.235549
10982 22:19:51.239045 debian-bullseye-arm64 login: root (automatic login)
10983 22:19:51.239131
10984 22:19:51.239197
10985 22:19:51.272728 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Sun Jun 4 21:56:05 UTC 2023 a<4>[ 19.679137] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10986 22:19:51.272857 arch64
10987 22:19:51.272926
10988 22:19:51.279261 The programs included with the Debian GNU/Linux system are free software;
10989 22:19:51.285882 the exact distribution terms for each program are described in the
10990 22:19:51.289624 individual files in /usr/share/doc/*/copyright.
10991 22:19:51.289765
10992 22:19:51.295845 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10993 22:19:51.298965 permitted by applicable law.
10994 22:19:51.299310 Matched prompt #10: / #
10996 22:19:51.299517 Setting prompt string to ['/ #']
10997 22:19:51.299607 end: 2.2.5.1 login-action (duration 00:00:20) [common]
10999 22:19:51.299799 end: 2.2.5 auto-login-action (duration 00:00:21) [common]
11000 22:19:51.299904 start: 2.2.6 expect-shell-connection (timeout 00:03:21) [common]
11001 22:19:51.299988 Setting prompt string to ['/ #']
11002 22:19:51.300047 Forcing a shell prompt, looking for ['/ #']
11004 22:19:51.350241 / #
11005 22:19:51.350419 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11006 22:19:51.350503 Waiting using forced prompt support (timeout 00:02:30)
11007 22:19:51.355311
11008 22:19:51.355595 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11009 22:19:51.355690 start: 2.2.7 export-device-env (timeout 00:03:21) [common]
11010 22:19:51.355805 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11011 22:19:51.355921 end: 2.2 depthcharge-retry (duration 00:01:39) [common]
11012 22:19:51.356020 end: 2 depthcharge-action (duration 00:01:39) [common]
11013 22:19:51.356108 start: 3 lava-test-retry (timeout 00:07:59) [common]
11014 22:19:51.356222 start: 3.1 lava-test-shell (timeout 00:07:59) [common]
11015 22:19:51.356296 Using namespace: common
11017 22:19:51.456620 / # #
11018 22:19:51.456809 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11019 22:19:51.456953 <4>[ 19.801410] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11020 22:19:51.461606 #
11021 22:19:51.461903 Using /lava-10583924
11023 22:19:51.562268 / # export SHELL=/bin/sh
11024 22:19:51.562506 <4>[ 19.921374] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11025 22:19:51.567749 export SHELL=/bin/sh
11027 22:19:51.668316 / # . /lava-10583924/environment
11028 22:19:51.668527 . /lava-10583924<4>[ 20.041052] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11029 22:19:51.673434 /environment
11031 22:19:51.773999 / # /lava-10583924/bin/lava-test-runner /lava-10583924/0
11032 22:19:51.774157 Test shell timeout: 10s (minimum of the action and connection timeout)
11033 22:19:51.774516 /lava-10583924/bin/lava-test-runner /lava-10583924/0<4>[ 20.161203] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11034 22:19:51.779044
11035 22:19:51.821609 + export TESTRUN_ID=0_igt-gpu-panf<8>[ 20.216072] <LAVA_SIGNAL_STARTRUN 0_igt-gpu-panfrost 10583924_1.5.2.3.1>
11036 22:19:51.821844 rost
11037 22:19:51.822197 Received signal: <STARTRUN> 0_igt-gpu-panfrost 10583924_1.5.2.3.1
11038 22:19:51.822285 Starting test lava.0_igt-gpu-panfrost (10583924_1.5.2.3.1)
11039 22:19:51.822394 Skipping test definition patterns.
11040 22:19:51.822548 + cd /lava-10583924/0/tests/0_igt-gpu-panfrost
11041 22:19:51.822616 + cat uuid
11042 22:19:51.822678 + UUID=10583924_1.5.2.3.1
11043 22:19:51.822738 + set +x
11044 22:19:51.824366 + IGT_FORCE_DRIVER=panfrost /usr/bin/igt-parser.sh panfrost_gem_new panfrost_get_param panfrost_prime panfrost_submit
11045 22:19:51.833777 <8>[ 20.247168] <LAVA_SIGNAL_TESTSET START panfrost_gem_new>
11046 22:19:51.834041 Received signal: <TESTSET> START panfrost_gem_new
11047 22:19:51.834116 Starting test_set panfrost_gem_new
11048 22:19:51.861533 <14>[ 20.274615] [IGT] panfrost_gem_new: executing
11049 22:19:51.868180 IGT-Version: 1.2<3>[ 20.280860] mt7921e 0000:01:00.0: hardware init failed
11050 22:19:51.874783 7.1-g766edf9 (aa<14>[ 20.287594] [IGT] panfrost_gem_new: exiting, ret=77
11051 22:19:51.877902 rch64) (Linux: 6.1.31 aarch64)
11052 22:19:51.891016 Test requirement not met in function drm_open_dr<8>[ 20.300560] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-4096 RESULT=skip>
11053 22:19:51.891119 iver, file ../lib/drmtest.c:621:
11054 22:19:51.891389 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-4096 RESULT=skip
11056 22:19:51.894318 Test requirement: !(fd<0)
11057 22:19:51.901446 No known gpu found for chipset flags 0x32 (panfrost)
11058 22:19:51.904733 Last errno: 2, No such file or directory
11059 22:19:51.907543 [1mSubtest gem-new-4096: SKIP (0.000s)[0m
11060 22:19:51.911077 <14>[ 20.325497] [IGT] panfrost_gem_new: executing
11061 22:19:51.920818 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 20.333629] [IGT] panfrost_gem_new: exiting, ret=77
11062 22:19:51.923820 .1.31 aarch64)
11063 22:19:51.933689 Test requirement not met in function drm_open_driver, file ../li<8>[ 20.345775] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-0 RESULT=skip>
11064 22:19:51.933968 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-0 RESULT=skip
11066 22:19:51.937253 b/drmtest.c:621:
11067 22:19:51.940570 Test requirement: !(fd<0)
11068 22:19:51.943762 No known gpu found for chipset flags 0x32 (panfrost)
11069 22:19:51.946940 Last errno: 2, No such file or directory
11070 22:19:51.950609 [1mSubtest gem-new-0: SKIP (0.000s)[0m
11071 22:19:51.958571 <14>[ 20.371689] [IGT] panfrost_gem_new: executing
11072 22:19:51.968700 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 20.379811] [IGT] panfrost_gem_new: exiting, ret=77
11073 22:19:51.968819 .1.31 aarch64)
11074 22:19:51.981910 Test requirement not met in function drm_open_driver, file ../li<8>[ 20.392267] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-zeroed RESULT=skip>
11075 22:19:51.982209 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-zeroed RESULT=skip
11077 22:19:51.985273 b/drmtest.c:621:
11078 22:19:51.988287 Test requireme<8>[ 20.402286] <LAVA_SIGNAL_TESTSET STOP>
11079 22:19:51.988396 nt: !(fd<0)
11080 22:19:51.988663 Received signal: <TESTSET> STOP
11081 22:19:51.988763 Closing test_set panfrost_gem_new
11082 22:19:51.995123 No known gpu found for chipset flags 0x32 (panfrost)
11083 22:19:51.998118 Last errno: 2, No such file or directory
11084 22:19:52.001276 [1mSubtest gem-new-zeroed: SKIP (0.000s)[0m
11085 22:19:52.015630 <8>[ 20.428894] <LAVA_SIGNAL_TESTSET START panfrost_get_param>
11086 22:19:52.015912 Received signal: <TESTSET> START panfrost_get_param
11087 22:19:52.015988 Starting test_set panfrost_get_param
11088 22:19:52.039282 <14>[ 20.452870] [IGT] panfrost_get_param: executing
11089 22:19:52.049512 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 20.461257] [IGT] panfrost_get_param: exiting, ret=77
11090 22:19:52.049652 .1.31 aarch64)
11091 22:19:52.062635 Test requirement not met in function drm_open_driver, file ../li<8>[ 20.473797] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=base-params RESULT=skip>
11092 22:19:52.062904 Received signal: <TESTCASE> TEST_CASE_ID=base-params RESULT=skip
11094 22:19:52.066168 b/drmtest.c:621:
11095 22:19:52.066252 Test requirement: !(fd<0)
11096 22:19:52.072783 No known gpu found for chipset flags 0x32 (panfrost)
11097 22:19:52.075853 Last errno: 2, No such file or directory
11098 22:19:52.079222 [1mSubtest base-params: SKIP (0.000s)[0m
11099 22:19:52.086656 <14>[ 20.499840] [IGT] panfrost_get_param: executing
11100 22:19:52.096251 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 20.508475] [IGT] panfrost_get_param: exiting, ret=77
11101 22:19:52.096339 .1.31 aarch64)
11102 22:19:52.109499 Test requirement not met in function drm_open_driver, file ../li<8>[ 20.520470] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=get-bad-param RESULT=skip>
11103 22:19:52.109774 Received signal: <TESTCASE> TEST_CASE_ID=get-bad-param RESULT=skip
11105 22:19:52.113231 b/drmtest.c:621:
11106 22:19:52.113315 Test requirement: !(fd<0)
11107 22:19:52.119943 No known gpu found for chipset flags 0x32 (panfrost)
11108 22:19:52.123337 Last errno: 2, No such file or directory
11109 22:19:52.126564 [1mSubtest get-bad-param: SKIP (0.000s)[0m
11110 22:19:52.133131 <14>[ 20.545726] [IGT] panfrost_get_param: executing
11111 22:19:52.142710 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 20.553977] [IGT] panfrost_get_param: exiting, ret=77
11112 22:19:52.142803 .1.31 aarch64)
11113 22:19:52.156146 Test requirement not met in function drm_open_driver, file ../li<8>[ 20.566504] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=get-bad-padding RESULT=skip>
11114 22:19:52.156415 Received signal: <TESTCASE> TEST_CASE_ID=get-bad-padding RESULT=skip
11116 22:19:52.159474 b/drmtest.c:621:
11117 22:19:52.162547 Test requireme<8>[ 20.576236] <LAVA_SIGNAL_TESTSET STOP>
11118 22:19:52.162800 Received signal: <TESTSET> STOP
11119 22:19:52.162869 Closing test_set panfrost_get_param
11120 22:19:52.166003 nt: !(fd<0)
11121 22:19:52.169039 No known gpu found for chipset flags 0x32 (panfrost)
11122 22:19:52.172480 Last errno: 2, No such file or directory
11123 22:19:52.176086 [1mSubtest get-bad-padding: SKIP (0.000s)[0m
11124 22:19:52.188585 <8>[ 20.602190] <LAVA_SIGNAL_TESTSET START panfrost_prime>
11125 22:19:52.188852 Received signal: <TESTSET> START panfrost_prime
11126 22:19:52.188927 Starting test_set panfrost_prime
11127 22:19:52.212635 <14>[ 20.625753] [IGT] panfrost_prime: executing
11128 22:19:52.222260 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 20.633928] [IGT] panfrost_prime: exiting, ret=77
11129 22:19:52.222373 .1.31 aarch64)
11130 22:19:52.235926 Test requirement not met in function drm_open_driver, file ../li<8>[ 20.646216] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-prime-import RESULT=skip>
11131 22:19:52.236031 b/drmtest.c:621:
11132 22:19:52.236276 Received signal: <TESTCASE> TEST_CASE_ID=gem-prime-import RESULT=skip
11134 22:19:52.242251 Test requireme<8>[ 20.655797] <LAVA_SIGNAL_TESTSET STOP>
11135 22:19:52.242338 nt: !(fd<0)
11136 22:19:52.242575 Received signal: <TESTSET> STOP
11137 22:19:52.242642 Closing test_set panfrost_prime
11138 22:19:52.248912 No known gpu found for chipset flags 0x32 (panfrost)
11139 22:19:52.252405 Last errno: 2, No such file or directory
11140 22:19:52.255400 [1mSubtest gem-prime-import: SKIP (0.000s)[0m
11141 22:19:52.268440 <8>[ 20.681825] <LAVA_SIGNAL_TESTSET START panfrost_submit>
11142 22:19:52.268708 Received signal: <TESTSET> START panfrost_submit
11143 22:19:52.268784 Starting test_set panfrost_submit
11144 22:19:52.292237 <14>[ 20.705403] [IGT] panfrost_submit: executing
11145 22:19:52.301963 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 20.713726] [IGT] panfrost_submit: exiting, ret=77
11146 22:19:52.302088 .1.31 aarch64)
11147 22:19:52.315214 Test requirement not met in function drm_open_driver, file ../li<8>[ 20.725861] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit RESULT=skip>
11148 22:19:52.315342 b/drmtest.c:621:
11149 22:19:52.315616 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit RESULT=skip
11151 22:19:52.318368 Test requirement: !(fd<0)
11152 22:19:52.321738 No known gpu found for chipset flags 0x32 (panfrost)
11153 22:19:52.328582 Last errno: 2, No such file or directory
11154 22:19:52.332172 [1mSubtest pan-submit: SKIP (0.000s)[0m
11155 22:19:52.338914 <14>[ 20.751673] [IGT] panfrost_submit: executing
11156 22:19:52.348478 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 20.760038] [IGT] panfrost_submit: exiting, ret=77
11157 22:19:52.348579 .1.31 aarch64)
11158 22:19:52.361890 Test requirement not met in function drm_open_driver, file ../li<8>[ 20.772340] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-no-jc RESULT=skip>
11159 22:19:52.362165 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-no-jc RESULT=skip
11161 22:19:52.365083 b/drmtest.c:621:
11162 22:19:52.365196 Test requirement: !(fd<0)
11163 22:19:52.371765 No known gpu found for chipset flags 0x32 (panfrost)
11164 22:19:52.374907 Last errno: 2, No such file or directory
11165 22:19:52.378175 [1mSubtest pan-submit-error-no-jc: SKIP (0.000s)[0m
11166 22:19:52.385917 <14>[ 20.799095] [IGT] panfrost_submit: executing
11167 22:19:52.395694 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 20.807224] [IGT] panfrost_submit: exiting, ret=77
11168 22:19:52.395780 .1.31 aarch64)
11169 22:19:52.409264 Test requirement not met in function drm_open_driver, file ../li<8>[ 20.819658] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-in-syncs RESULT=skip>
11170 22:19:52.409534 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-in-syncs RESULT=skip
11172 22:19:52.412684 b/drmtest.c:621:
11173 22:19:52.415314 Test requirement: !(fd<0)
11174 22:19:52.419038 No known gpu found for chipset flags 0x32 (panfrost)
11175 22:19:52.422088 Last errno: 2, No such file or directory
11176 22:19:52.429155 [1mSubtest pan-submit-error-bad-in-syncs: SKIP (0.000s)[0m
11177 22:19:52.432233 <14>[ 20.847287] [IGT] panfrost_submit: executing
11178 22:19:52.441960 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 20.855238] [IGT] panfrost_submit: exiting, ret=77
11179 22:19:52.445927 .1.31 aarch64)
11180 22:19:52.458911 Test requirement not met in function drm_open_driver, file ../li<8>[ 20.867727] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-bo-handles RESULT=skip>
11181 22:19:52.458996 b/drmtest.c:621:
11182 22:19:52.459233 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-bo-handles RESULT=skip
11184 22:19:52.462036 Test requirement: !(fd<0)
11185 22:19:52.468688 No known gpu found for chipset flags 0x32 (panfrost)
11186 22:19:52.472283 Last errno: 2, No such file or directory
11187 22:19:52.475346 [1mSubtest pan-submit-error-bad-bo-handles: SKIP (0.000s)[0m
11188 22:19:52.482363 <14>[ 20.895650] [IGT] panfrost_submit: executing
11189 22:19:52.492045 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 20.903943] [IGT] panfrost_submit: exiting, ret=77
11190 22:19:52.492154 .1.31 aarch64)
11191 22:19:52.505700 Test requirement not met in function drm_open_driver, file ../li<8>[ 20.915607] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-requirements RESULT=skip>
11192 22:19:52.505962 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-requirements RESULT=skip
11194 22:19:52.508660 b/drmtest.c:621:
11195 22:19:52.512226 Test requirement: !(fd<0)
11196 22:19:52.515495 No known gpu found for chipset flags 0x32 (panfrost)
11197 22:19:52.518634 Last errno: 2, No such file or directory
11198 22:19:52.525309 [1mSubtest pan-submit-error-bad-requirements: SKIP (0.000s)[0m
11199 22:19:52.528664 <14>[ 20.943636] [IGT] panfrost_submit: executing
11200 22:19:52.538811 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 20.951704] [IGT] panfrost_submit: exiting, ret=77
11201 22:19:52.542175 .1.31 aarch64)
11202 22:19:52.555323 Test requirement not met in function drm_open_driver, file ../li<8>[ 20.964136] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-out-sync RESULT=skip>
11203 22:19:52.555433 b/drmtest.c:621:
11204 22:19:52.555676 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-out-sync RESULT=skip
11206 22:19:52.558734 Test requirement: !(fd<0)
11207 22:19:52.561613 No known gpu found for chipset flags 0x32 (panfrost)
11208 22:19:52.568438 Last errno: 2, No such file or directory
11209 22:19:52.572013 [1mSubtest pan-submit-error-bad-out-sync: SKIP (0.000s)[0m
11210 22:19:52.578538 <14>[ 20.991677] [IGT] panfrost_submit: executing
11211 22:19:52.588539 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 20.999719] [IGT] panfrost_submit: exiting, ret=77
11212 22:19:52.588625 .1.31 aarch64)
11213 22:19:52.602040 Test requirement not met in function drm_open_driver, file ../li<8>[ 21.012188] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-reset RESULT=skip>
11214 22:19:52.602129 b/drmtest.c:621:
11215 22:19:52.602367 Received signal: <TESTCASE> TEST_CASE_ID=pan-reset RESULT=skip
11217 22:19:52.604863 Test requirement: !(fd<0)
11218 22:19:52.608578 No known gpu found for chipset flags 0x32 (panfrost)
11219 22:19:52.612072 Last errno: 2, No such file or directory
11220 22:19:52.618567 [1mSubtest pan-reset: SKIP (0.000s)[0m
11221 22:19:52.624970 <14>[ 21.038072] [IGT] panfrost_submit: executing
11222 22:19:52.635327 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 21.046147] [IGT] panfrost_submit: exiting, ret=77
11223 22:19:52.635440 .1.31 aarch64)
11224 22:19:52.648558 Test requirement not met in function drm_open_driver, file ../li<8>[ 21.058346] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-and-close RESULT=skip>
11225 22:19:52.648848 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-and-close RESULT=skip
11227 22:19:52.651776 b/drmtest.c:621:
11228 22:19:52.651882 Test requirement: !(fd<0)
11229 22:19:52.658374 No known gpu found for chipset flags 0x32 (panfrost)
11230 22:19:52.661407 Last errno: 2, No such file or directory
11231 22:19:52.665059 [1mSubtest pan-submit-and-close: SKIP (0.000s)[0m
11232 22:19:52.671420 <14>[ 21.084200] [IGT] panfrost_submit: executing
11233 22:19:52.681319 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 21.092068] [IGT] panfrost_submit: exiting, ret=77
11234 22:19:52.681402 .1.31 aarch64)
11235 22:19:52.694694 Test requirement not met in function drm_open_driver, file ../li<8>[ 21.104730] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-unhandled-pagefault RESULT=skip>
11236 22:19:52.694813 b/drmtest.c:621:
11237 22:19:52.695094 Received signal: <TESTCASE> TEST_CASE_ID=pan-unhandled-pagefault RESULT=skip
11239 22:19:52.701405 Test requireme<8>[ 21.114988] <LAVA_SIGNAL_TESTSET STOP>
11240 22:19:52.701519 nt: !(fd<0)
11241 22:19:52.701759 Received signal: <TESTSET> STOP
11242 22:19:52.701839 Closing test_set panfrost_submit
11243 22:19:52.708404 Received signal: <ENDRUN> 0_igt-gpu-panfrost 10583924_1.5.2.3.1
11244 22:19:52.708529 Ending use of test pattern.
11245 22:19:52.708624 Ending test lava.0_igt-gpu-panfrost (10583924_1.5.2.3.1), duration 0.89
11247 22:19:52.710887 No <8>[ 21.120773] <LAVA_SIGNAL_ENDRUN 0_igt-gpu-panfrost 10583924_1.5.2.3.1>
11248 22:19:52.714928 known gpu found for chipset flags 0x32 (panfrost)
11249 22:19:52.717992 Last errno: 2, No such file or directory
11250 22:19:52.721103 [1mSubtest pan-unhandled-pagefault: SKIP (0.000s)[0m
11251 22:19:52.724597 + set +x
11252 22:19:52.724675 <LAVA_TEST_RUNNER EXIT>
11253 22:19:52.724930 ok: lava_test_shell seems to have completed
11254 22:19:52.725583 base-params:
result: skip
set: panfrost_get_param
gem-new-0:
result: skip
set: panfrost_gem_new
gem-new-4096:
result: skip
set: panfrost_gem_new
gem-new-zeroed:
result: skip
set: panfrost_gem_new
gem-prime-import:
result: skip
set: panfrost_prime
get-bad-padding:
result: skip
set: panfrost_get_param
get-bad-param:
result: skip
set: panfrost_get_param
pan-reset:
result: skip
set: panfrost_submit
pan-submit:
result: skip
set: panfrost_submit
pan-submit-and-close:
result: skip
set: panfrost_submit
pan-submit-error-bad-bo-handles:
result: skip
set: panfrost_submit
pan-submit-error-bad-in-syncs:
result: skip
set: panfrost_submit
pan-submit-error-bad-out-sync:
result: skip
set: panfrost_submit
pan-submit-error-bad-requirements:
result: skip
set: panfrost_submit
pan-submit-error-no-jc:
result: skip
set: panfrost_submit
pan-unhandled-pagefault:
result: skip
set: panfrost_submit
11255 22:19:52.725686 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11256 22:19:52.725775 end: 3 lava-test-retry (duration 00:00:01) [common]
11257 22:19:52.725883 start: 4 finalize (timeout 00:07:58) [common]
11258 22:19:52.725983 start: 4.1 power-off (timeout 00:00:30) [common]
11259 22:19:52.726133 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=off'
11260 22:19:52.803631 >> Command sent successfully.
11261 22:19:52.806141 Returned 0 in 0 seconds
11262 22:19:52.906587 end: 4.1 power-off (duration 00:00:00) [common]
11264 22:19:52.907021 start: 4.2 read-feedback (timeout 00:07:57) [common]
11265 22:19:52.907322 Listened to connection for namespace 'common' for up to 1s
11266 22:19:53.908396 Finalising connection for namespace 'common'
11267 22:19:53.908959 Disconnecting from shell: Finalise
11268 22:19:53.909302 / #
11269 22:19:54.010214 end: 4.2 read-feedback (duration 00:00:01) [common]
11270 22:19:54.010847 end: 4 finalize (duration 00:00:01) [common]
11271 22:19:54.011597 Cleaning after the job
11272 22:19:54.012205 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10583924/tftp-deploy-7_wm5peu/ramdisk
11273 22:19:54.037969 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10583924/tftp-deploy-7_wm5peu/kernel
11274 22:19:54.050367 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10583924/tftp-deploy-7_wm5peu/dtb
11275 22:19:54.050753 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10583924/tftp-deploy-7_wm5peu/modules
11276 22:19:54.059014 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10583924
11277 22:19:54.160304 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10583924
11278 22:19:54.160467 Job finished correctly