Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 41
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 33
1 22:11:50.319101 lava-dispatcher, installed at version: 2023.03
2 22:11:50.319339 start: 0 validate
3 22:11:50.319467 Start time: 2023-06-04 22:11:50.319460+00:00 (UTC)
4 22:11:50.319596 Using caching service: 'http://localhost/cache/?uri=%s'
5 22:11:50.319724 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230527.0%2Farm64%2Finitrd.cpio.gz exists
6 22:11:50.612965 Using caching service: 'http://localhost/cache/?uri=%s'
7 22:11:50.613770 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1281-g84d5372e0f314%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 22:12:21.920761 Using caching service: 'http://localhost/cache/?uri=%s'
9 22:12:21.921506 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1281-g84d5372e0f314%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 22:12:22.207050 Using caching service: 'http://localhost/cache/?uri=%s'
11 22:12:22.207803 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230527.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 22:12:22.770692 Using caching service: 'http://localhost/cache/?uri=%s'
13 22:12:22.771433 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1281-g84d5372e0f314%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 22:12:25.774227 validate duration: 35.45
16 22:12:25.774484 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 22:12:25.774581 start: 1.1 download-retry (timeout 00:10:00) [common]
18 22:12:25.774667 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 22:12:25.774790 Not decompressing ramdisk as can be used compressed.
20 22:12:25.774874 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230527.0/arm64/initrd.cpio.gz
21 22:12:25.774937 saving as /var/lib/lava/dispatcher/tmp/10583852/tftp-deploy-8m8yc9em/ramdisk/initrd.cpio.gz
22 22:12:25.774998 total size: 4665601 (4MB)
23 22:12:26.056160 progress 0% (0MB)
24 22:12:26.057592 progress 5% (0MB)
25 22:12:26.058837 progress 10% (0MB)
26 22:12:26.060105 progress 15% (0MB)
27 22:12:26.061322 progress 20% (0MB)
28 22:12:26.062535 progress 25% (1MB)
29 22:12:26.063829 progress 30% (1MB)
30 22:12:26.065043 progress 35% (1MB)
31 22:12:26.066269 progress 40% (1MB)
32 22:12:26.067671 progress 45% (2MB)
33 22:12:26.068897 progress 50% (2MB)
34 22:12:26.070149 progress 55% (2MB)
35 22:12:26.071470 progress 60% (2MB)
36 22:12:26.072697 progress 65% (2MB)
37 22:12:26.073912 progress 70% (3MB)
38 22:12:26.075170 progress 75% (3MB)
39 22:12:26.076426 progress 80% (3MB)
40 22:12:26.077782 progress 85% (3MB)
41 22:12:26.079094 progress 90% (4MB)
42 22:12:26.080332 progress 95% (4MB)
43 22:12:26.081542 progress 100% (4MB)
44 22:12:26.081697 4MB downloaded in 0.31s (14.51MB/s)
45 22:12:26.081846 end: 1.1.1 http-download (duration 00:00:00) [common]
47 22:12:26.082079 end: 1.1 download-retry (duration 00:00:00) [common]
48 22:12:26.082217 start: 1.2 download-retry (timeout 00:10:00) [common]
49 22:12:26.082316 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 22:12:26.082449 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1281-g84d5372e0f314/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 22:12:26.082518 saving as /var/lib/lava/dispatcher/tmp/10583852/tftp-deploy-8m8yc9em/kernel/Image
52 22:12:26.082578 total size: 45746688 (43MB)
53 22:12:26.082636 No compression specified
54 22:12:26.083760 progress 0% (0MB)
55 22:12:26.095480 progress 5% (2MB)
56 22:12:26.107285 progress 10% (4MB)
57 22:12:26.119033 progress 15% (6MB)
58 22:12:26.130673 progress 20% (8MB)
59 22:12:26.142192 progress 25% (10MB)
60 22:12:26.153497 progress 30% (13MB)
61 22:12:26.165081 progress 35% (15MB)
62 22:12:26.176764 progress 40% (17MB)
63 22:12:26.188490 progress 45% (19MB)
64 22:12:26.200409 progress 50% (21MB)
65 22:12:26.211988 progress 55% (24MB)
66 22:12:26.223786 progress 60% (26MB)
67 22:12:26.235585 progress 65% (28MB)
68 22:12:26.247043 progress 70% (30MB)
69 22:12:26.258521 progress 75% (32MB)
70 22:12:26.269986 progress 80% (34MB)
71 22:12:26.281599 progress 85% (37MB)
72 22:12:26.293379 progress 90% (39MB)
73 22:12:26.304995 progress 95% (41MB)
74 22:12:26.316580 progress 100% (43MB)
75 22:12:26.316764 43MB downloaded in 0.23s (186.30MB/s)
76 22:12:26.316919 end: 1.2.1 http-download (duration 00:00:00) [common]
78 22:12:26.317144 end: 1.2 download-retry (duration 00:00:00) [common]
79 22:12:26.317231 start: 1.3 download-retry (timeout 00:09:59) [common]
80 22:12:26.317323 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 22:12:26.317462 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1281-g84d5372e0f314/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 22:12:26.317531 saving as /var/lib/lava/dispatcher/tmp/10583852/tftp-deploy-8m8yc9em/dtb/mt8192-asurada-spherion-r0.dtb
83 22:12:26.317591 total size: 46924 (0MB)
84 22:12:26.317650 No compression specified
85 22:12:26.318831 progress 69% (0MB)
86 22:12:26.319139 progress 100% (0MB)
87 22:12:26.319291 0MB downloaded in 0.00s (26.38MB/s)
88 22:12:26.319409 end: 1.3.1 http-download (duration 00:00:00) [common]
90 22:12:26.319630 end: 1.3 download-retry (duration 00:00:00) [common]
91 22:12:26.319714 start: 1.4 download-retry (timeout 00:09:59) [common]
92 22:12:26.319794 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 22:12:26.319903 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230527.0/arm64/full.rootfs.tar.xz
94 22:12:26.319970 saving as /var/lib/lava/dispatcher/tmp/10583852/tftp-deploy-8m8yc9em/nfsrootfs/full.rootfs.tar
95 22:12:26.320029 total size: 200770336 (191MB)
96 22:12:26.320088 Using unxz to decompress xz
97 22:12:26.323914 progress 0% (0MB)
98 22:12:26.867849 progress 5% (9MB)
99 22:12:27.403258 progress 10% (19MB)
100 22:12:27.997645 progress 15% (28MB)
101 22:12:28.365820 progress 20% (38MB)
102 22:12:28.692318 progress 25% (47MB)
103 22:12:29.300992 progress 30% (57MB)
104 22:12:29.870096 progress 35% (67MB)
105 22:12:30.466409 progress 40% (76MB)
106 22:12:31.051577 progress 45% (86MB)
107 22:12:31.637258 progress 50% (95MB)
108 22:12:32.278070 progress 55% (105MB)
109 22:12:32.936449 progress 60% (114MB)
110 22:12:33.054379 progress 65% (124MB)
111 22:12:33.194927 progress 70% (134MB)
112 22:12:33.290759 progress 75% (143MB)
113 22:12:33.365535 progress 80% (153MB)
114 22:12:33.435162 progress 85% (162MB)
115 22:12:33.533674 progress 90% (172MB)
116 22:12:33.806320 progress 95% (181MB)
117 22:12:34.371796 progress 100% (191MB)
118 22:12:34.376444 191MB downloaded in 8.06s (23.77MB/s)
119 22:12:34.376746 end: 1.4.1 http-download (duration 00:00:08) [common]
121 22:12:34.377011 end: 1.4 download-retry (duration 00:00:08) [common]
122 22:12:34.377101 start: 1.5 download-retry (timeout 00:09:51) [common]
123 22:12:34.377191 start: 1.5.1 http-download (timeout 00:09:51) [common]
124 22:12:34.377329 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1281-g84d5372e0f314/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 22:12:34.377401 saving as /var/lib/lava/dispatcher/tmp/10583852/tftp-deploy-8m8yc9em/modules/modules.tar
126 22:12:34.377463 total size: 8541948 (8MB)
127 22:12:34.377524 Using unxz to decompress xz
128 22:12:34.666708 progress 0% (0MB)
129 22:12:34.689115 progress 5% (0MB)
130 22:12:34.714923 progress 10% (0MB)
131 22:12:34.740751 progress 15% (1MB)
132 22:12:34.766049 progress 20% (1MB)
133 22:12:34.790171 progress 25% (2MB)
134 22:12:34.817300 progress 30% (2MB)
135 22:12:34.842688 progress 35% (2MB)
136 22:12:34.867347 progress 40% (3MB)
137 22:12:34.892003 progress 45% (3MB)
138 22:12:34.917570 progress 50% (4MB)
139 22:12:34.941514 progress 55% (4MB)
140 22:12:34.966311 progress 60% (4MB)
141 22:12:34.992171 progress 65% (5MB)
142 22:12:35.017253 progress 70% (5MB)
143 22:12:35.041056 progress 75% (6MB)
144 22:12:35.065086 progress 80% (6MB)
145 22:12:35.089990 progress 85% (6MB)
146 22:12:35.119443 progress 90% (7MB)
147 22:12:35.144970 progress 95% (7MB)
148 22:12:35.168843 progress 100% (8MB)
149 22:12:35.174585 8MB downloaded in 0.80s (10.22MB/s)
150 22:12:35.174883 end: 1.5.1 http-download (duration 00:00:01) [common]
152 22:12:35.175257 end: 1.5 download-retry (duration 00:00:01) [common]
153 22:12:35.175368 start: 1.6 prepare-tftp-overlay (timeout 00:09:51) [common]
154 22:12:35.175477 start: 1.6.1 extract-nfsrootfs (timeout 00:09:51) [common]
155 22:12:38.417083 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/10583852/extract-nfsrootfs-_32h7bf0
156 22:12:38.417300 end: 1.6.1 extract-nfsrootfs (duration 00:00:03) [common]
157 22:12:38.417405 start: 1.6.2 lava-overlay (timeout 00:09:47) [common]
158 22:12:38.417604 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10583852/lava-overlay-yg69uq3l
159 22:12:38.417728 makedir: /var/lib/lava/dispatcher/tmp/10583852/lava-overlay-yg69uq3l/lava-10583852/bin
160 22:12:38.417843 makedir: /var/lib/lava/dispatcher/tmp/10583852/lava-overlay-yg69uq3l/lava-10583852/tests
161 22:12:38.417940 makedir: /var/lib/lava/dispatcher/tmp/10583852/lava-overlay-yg69uq3l/lava-10583852/results
162 22:12:38.418042 Creating /var/lib/lava/dispatcher/tmp/10583852/lava-overlay-yg69uq3l/lava-10583852/bin/lava-add-keys
163 22:12:38.418198 Creating /var/lib/lava/dispatcher/tmp/10583852/lava-overlay-yg69uq3l/lava-10583852/bin/lava-add-sources
164 22:12:38.418339 Creating /var/lib/lava/dispatcher/tmp/10583852/lava-overlay-yg69uq3l/lava-10583852/bin/lava-background-process-start
165 22:12:38.418476 Creating /var/lib/lava/dispatcher/tmp/10583852/lava-overlay-yg69uq3l/lava-10583852/bin/lava-background-process-stop
166 22:12:38.418597 Creating /var/lib/lava/dispatcher/tmp/10583852/lava-overlay-yg69uq3l/lava-10583852/bin/lava-common-functions
167 22:12:38.418717 Creating /var/lib/lava/dispatcher/tmp/10583852/lava-overlay-yg69uq3l/lava-10583852/bin/lava-echo-ipv4
168 22:12:38.418838 Creating /var/lib/lava/dispatcher/tmp/10583852/lava-overlay-yg69uq3l/lava-10583852/bin/lava-install-packages
169 22:12:38.418957 Creating /var/lib/lava/dispatcher/tmp/10583852/lava-overlay-yg69uq3l/lava-10583852/bin/lava-installed-packages
170 22:12:38.419113 Creating /var/lib/lava/dispatcher/tmp/10583852/lava-overlay-yg69uq3l/lava-10583852/bin/lava-os-build
171 22:12:38.419235 Creating /var/lib/lava/dispatcher/tmp/10583852/lava-overlay-yg69uq3l/lava-10583852/bin/lava-probe-channel
172 22:12:38.419354 Creating /var/lib/lava/dispatcher/tmp/10583852/lava-overlay-yg69uq3l/lava-10583852/bin/lava-probe-ip
173 22:12:38.419474 Creating /var/lib/lava/dispatcher/tmp/10583852/lava-overlay-yg69uq3l/lava-10583852/bin/lava-target-ip
174 22:12:38.419595 Creating /var/lib/lava/dispatcher/tmp/10583852/lava-overlay-yg69uq3l/lava-10583852/bin/lava-target-mac
175 22:12:38.419716 Creating /var/lib/lava/dispatcher/tmp/10583852/lava-overlay-yg69uq3l/lava-10583852/bin/lava-target-storage
176 22:12:38.419838 Creating /var/lib/lava/dispatcher/tmp/10583852/lava-overlay-yg69uq3l/lava-10583852/bin/lava-test-case
177 22:12:38.419962 Creating /var/lib/lava/dispatcher/tmp/10583852/lava-overlay-yg69uq3l/lava-10583852/bin/lava-test-event
178 22:12:38.420080 Creating /var/lib/lava/dispatcher/tmp/10583852/lava-overlay-yg69uq3l/lava-10583852/bin/lava-test-feedback
179 22:12:38.420199 Creating /var/lib/lava/dispatcher/tmp/10583852/lava-overlay-yg69uq3l/lava-10583852/bin/lava-test-raise
180 22:12:38.420318 Creating /var/lib/lava/dispatcher/tmp/10583852/lava-overlay-yg69uq3l/lava-10583852/bin/lava-test-reference
181 22:12:38.420438 Creating /var/lib/lava/dispatcher/tmp/10583852/lava-overlay-yg69uq3l/lava-10583852/bin/lava-test-runner
182 22:12:38.420557 Creating /var/lib/lava/dispatcher/tmp/10583852/lava-overlay-yg69uq3l/lava-10583852/bin/lava-test-set
183 22:12:38.420678 Creating /var/lib/lava/dispatcher/tmp/10583852/lava-overlay-yg69uq3l/lava-10583852/bin/lava-test-shell
184 22:12:38.420799 Updating /var/lib/lava/dispatcher/tmp/10583852/lava-overlay-yg69uq3l/lava-10583852/bin/lava-add-keys (debian)
185 22:12:38.439886 Updating /var/lib/lava/dispatcher/tmp/10583852/lava-overlay-yg69uq3l/lava-10583852/bin/lava-add-sources (debian)
186 22:12:38.440118 Updating /var/lib/lava/dispatcher/tmp/10583852/lava-overlay-yg69uq3l/lava-10583852/bin/lava-install-packages (debian)
187 22:12:38.440267 Updating /var/lib/lava/dispatcher/tmp/10583852/lava-overlay-yg69uq3l/lava-10583852/bin/lava-installed-packages (debian)
188 22:12:38.440407 Updating /var/lib/lava/dispatcher/tmp/10583852/lava-overlay-yg69uq3l/lava-10583852/bin/lava-os-build (debian)
189 22:12:38.440526 Creating /var/lib/lava/dispatcher/tmp/10583852/lava-overlay-yg69uq3l/lava-10583852/environment
190 22:12:38.440629 LAVA metadata
191 22:12:38.440702 - LAVA_JOB_ID=10583852
192 22:12:38.440767 - LAVA_DISPATCHER_IP=192.168.201.1
193 22:12:38.440886 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:47) [common]
194 22:12:38.440956 skipped lava-vland-overlay
195 22:12:38.441032 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 22:12:38.441112 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:47) [common]
197 22:12:38.441173 skipped lava-multinode-overlay
198 22:12:38.441244 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 22:12:38.441321 start: 1.6.2.3 test-definition (timeout 00:09:47) [common]
200 22:12:38.441411 Loading test definitions
201 22:12:38.441534 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:47) [common]
202 22:12:38.441621 Using /lava-10583852 at stage 0
203 22:12:38.441943 uuid=10583852_1.6.2.3.1 testdef=None
204 22:12:38.442032 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 22:12:38.442154 start: 1.6.2.3.2 test-overlay (timeout 00:09:47) [common]
206 22:12:38.442655 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 22:12:38.442873 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:47) [common]
209 22:12:38.483505 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 22:12:38.483786 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:47) [common]
212 22:12:38.491102 runner path: /var/lib/lava/dispatcher/tmp/10583852/lava-overlay-yg69uq3l/lava-10583852/0/tests/0_timesync-off test_uuid 10583852_1.6.2.3.1
213 22:12:38.491297 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 22:12:38.491532 start: 1.6.2.3.5 git-repo-action (timeout 00:09:47) [common]
216 22:12:38.491609 Using /lava-10583852 at stage 0
217 22:12:38.491715 Fetching tests from https://github.com/kernelci/test-definitions.git
218 22:12:38.491797 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/10583852/lava-overlay-yg69uq3l/lava-10583852/0/tests/1_kselftest-arm64'
219 22:12:41.992652 Running '/usr/bin/git checkout kernelci.org
220 22:12:42.136893 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/10583852/lava-overlay-yg69uq3l/lava-10583852/0/tests/1_kselftest-arm64/automated/linux/kselftest/kselftest.yaml
221 22:12:42.137779 uuid=10583852_1.6.2.3.5 testdef=None
222 22:12:42.137954 end: 1.6.2.3.5 git-repo-action (duration 00:00:04) [common]
224 22:12:42.138229 start: 1.6.2.3.6 test-overlay (timeout 00:09:44) [common]
225 22:12:42.138984 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 22:12:42.139290 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:44) [common]
228 22:12:42.140258 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 22:12:42.140517 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:44) [common]
231 22:12:42.142089 runner path: /var/lib/lava/dispatcher/tmp/10583852/lava-overlay-yg69uq3l/lava-10583852/0/tests/1_kselftest-arm64 test_uuid 10583852_1.6.2.3.5
232 22:12:42.142213 BOARD='mt8192-asurada-spherion-r0'
233 22:12:42.142289 BRANCH='cip'
234 22:12:42.142369 SKIPFILE='/dev/null'
235 22:12:42.142446 SKIP_INSTALL='True'
236 22:12:42.142541 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1281-g84d5372e0f314/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 22:12:42.142636 TST_CASENAME=''
238 22:12:42.142729 TST_CMDFILES='arm64'
239 22:12:42.142925 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 22:12:42.143324 Creating lava-test-runner.conf files
242 22:12:42.143428 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10583852/lava-overlay-yg69uq3l/lava-10583852/0 for stage 0
243 22:12:42.143568 - 0_timesync-off
244 22:12:42.143644 - 1_kselftest-arm64
245 22:12:42.143785 end: 1.6.2.3 test-definition (duration 00:00:04) [common]
246 22:12:42.143889 start: 1.6.2.4 compress-overlay (timeout 00:09:44) [common]
247 22:12:49.608623 end: 1.6.2.4 compress-overlay (duration 00:00:07) [common]
248 22:12:49.608793 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:36) [common]
249 22:12:49.608883 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 22:12:49.608982 end: 1.6.2 lava-overlay (duration 00:00:11) [common]
251 22:12:49.609078 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:36) [common]
252 22:12:49.723684 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 22:12:49.724037 start: 1.6.4 extract-modules (timeout 00:09:36) [common]
254 22:12:49.724145 extracting modules file /var/lib/lava/dispatcher/tmp/10583852/tftp-deploy-8m8yc9em/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10583852/extract-nfsrootfs-_32h7bf0
255 22:12:49.925427 extracting modules file /var/lib/lava/dispatcher/tmp/10583852/tftp-deploy-8m8yc9em/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10583852/extract-overlay-ramdisk-6q939twt/ramdisk
256 22:12:50.130509 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 22:12:50.130688 start: 1.6.5 apply-overlay-tftp (timeout 00:09:36) [common]
258 22:12:50.130785 [common] Applying overlay to NFS
259 22:12:50.130857 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10583852/compress-overlay-xx1pgbcz/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10583852/extract-nfsrootfs-_32h7bf0
260 22:12:51.022503 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 22:12:51.022673 start: 1.6.6 configure-preseed-file (timeout 00:09:35) [common]
262 22:12:51.022771 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 22:12:51.022868 start: 1.6.7 compress-ramdisk (timeout 00:09:35) [common]
264 22:12:51.022953 Building ramdisk /var/lib/lava/dispatcher/tmp/10583852/extract-overlay-ramdisk-6q939twt/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10583852/extract-overlay-ramdisk-6q939twt/ramdisk
265 22:12:51.364380 >> 117799 blocks
266 22:12:53.282112 rename /var/lib/lava/dispatcher/tmp/10583852/extract-overlay-ramdisk-6q939twt/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10583852/tftp-deploy-8m8yc9em/ramdisk/ramdisk.cpio.gz
267 22:12:53.282553 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 22:12:53.282673 start: 1.6.8 prepare-kernel (timeout 00:09:32) [common]
269 22:12:53.282774 start: 1.6.8.1 prepare-fit (timeout 00:09:32) [common]
270 22:12:53.282880 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10583852/tftp-deploy-8m8yc9em/kernel/Image'
271 22:13:05.210947 Returned 0 in 11 seconds
272 22:13:05.311877 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10583852/tftp-deploy-8m8yc9em/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10583852/tftp-deploy-8m8yc9em/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10583852/tftp-deploy-8m8yc9em/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10583852/tftp-deploy-8m8yc9em/kernel/image.itb
273 22:13:05.681811 output: FIT description: Kernel Image image with one or more FDT blobs
274 22:13:05.682173 output: Created: Sun Jun 4 23:13:05 2023
275 22:13:05.682245 output: Image 0 (kernel-1)
276 22:13:05.682311 output: Description:
277 22:13:05.682374 output: Created: Sun Jun 4 23:13:05 2023
278 22:13:05.682433 output: Type: Kernel Image
279 22:13:05.682493 output: Compression: lzma compressed
280 22:13:05.682551 output: Data Size: 10081729 Bytes = 9845.44 KiB = 9.61 MiB
281 22:13:05.682611 output: Architecture: AArch64
282 22:13:05.682668 output: OS: Linux
283 22:13:05.682725 output: Load Address: 0x00000000
284 22:13:05.682783 output: Entry Point: 0x00000000
285 22:13:05.682838 output: Hash algo: crc32
286 22:13:05.682890 output: Hash value: 3b3111d8
287 22:13:05.682942 output: Image 1 (fdt-1)
288 22:13:05.682994 output: Description: mt8192-asurada-spherion-r0
289 22:13:05.683046 output: Created: Sun Jun 4 23:13:05 2023
290 22:13:05.683142 output: Type: Flat Device Tree
291 22:13:05.683194 output: Compression: uncompressed
292 22:13:05.683246 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
293 22:13:05.683298 output: Architecture: AArch64
294 22:13:05.683350 output: Hash algo: crc32
295 22:13:05.683401 output: Hash value: 1df858fa
296 22:13:05.683453 output: Image 2 (ramdisk-1)
297 22:13:05.683505 output: Description: unavailable
298 22:13:05.683557 output: Created: Sun Jun 4 23:13:05 2023
299 22:13:05.683609 output: Type: RAMDisk Image
300 22:13:05.683661 output: Compression: Unknown Compression
301 22:13:05.683713 output: Data Size: 17643968 Bytes = 17230.44 KiB = 16.83 MiB
302 22:13:05.683765 output: Architecture: AArch64
303 22:13:05.683816 output: OS: Linux
304 22:13:05.683868 output: Load Address: unavailable
305 22:13:05.683920 output: Entry Point: unavailable
306 22:13:05.683971 output: Hash algo: crc32
307 22:13:05.684023 output: Hash value: 7f10d825
308 22:13:05.684074 output: Default Configuration: 'conf-1'
309 22:13:05.684126 output: Configuration 0 (conf-1)
310 22:13:05.684178 output: Description: mt8192-asurada-spherion-r0
311 22:13:05.684229 output: Kernel: kernel-1
312 22:13:05.684281 output: Init Ramdisk: ramdisk-1
313 22:13:05.684332 output: FDT: fdt-1
314 22:13:05.684384 output: Loadables: kernel-1
315 22:13:05.684435 output:
316 22:13:05.684626 end: 1.6.8.1 prepare-fit (duration 00:00:12) [common]
317 22:13:05.684720 end: 1.6.8 prepare-kernel (duration 00:00:12) [common]
318 22:13:05.684827 end: 1.6 prepare-tftp-overlay (duration 00:00:31) [common]
319 22:13:05.684920 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:20) [common]
320 22:13:05.684995 No LXC device requested
321 22:13:05.685074 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 22:13:05.685156 start: 1.8 deploy-device-env (timeout 00:09:20) [common]
323 22:13:05.685233 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 22:13:05.685301 Checking files for TFTP limit of 4294967296 bytes.
325 22:13:05.685788 end: 1 tftp-deploy (duration 00:00:40) [common]
326 22:13:05.685895 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 22:13:05.685988 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 22:13:05.686113 substitutions:
329 22:13:05.686182 - {DTB}: 10583852/tftp-deploy-8m8yc9em/dtb/mt8192-asurada-spherion-r0.dtb
330 22:13:05.686246 - {INITRD}: 10583852/tftp-deploy-8m8yc9em/ramdisk/ramdisk.cpio.gz
331 22:13:05.686305 - {KERNEL}: 10583852/tftp-deploy-8m8yc9em/kernel/Image
332 22:13:05.686362 - {LAVA_MAC}: None
333 22:13:05.686418 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/10583852/extract-nfsrootfs-_32h7bf0
334 22:13:05.686473 - {NFS_SERVER_IP}: 192.168.201.1
335 22:13:05.686528 - {PRESEED_CONFIG}: None
336 22:13:05.686582 - {PRESEED_LOCAL}: None
337 22:13:05.686635 - {RAMDISK}: 10583852/tftp-deploy-8m8yc9em/ramdisk/ramdisk.cpio.gz
338 22:13:05.686690 - {ROOT_PART}: None
339 22:13:05.686743 - {ROOT}: None
340 22:13:05.686796 - {SERVER_IP}: 192.168.201.1
341 22:13:05.686849 - {TEE}: None
342 22:13:05.686903 Parsed boot commands:
343 22:13:05.686956 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 22:13:05.687173 Parsed boot commands: tftpboot 192.168.201.1 10583852/tftp-deploy-8m8yc9em/kernel/image.itb 10583852/tftp-deploy-8m8yc9em/kernel/cmdline
345 22:13:05.687262 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 22:13:05.687344 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 22:13:05.687438 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 22:13:05.687521 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 22:13:05.687593 Not connected, no need to disconnect.
350 22:13:05.687666 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 22:13:05.687746 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 22:13:05.687811 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-9'
353 22:13:05.691226 Setting prompt string to ['lava-test: # ']
354 22:13:05.691579 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 22:13:05.691685 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 22:13:05.691785 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 22:13:05.691876 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 22:13:05.692070 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=reboot'
359 22:13:10.823419 >> Command sent successfully.
360 22:13:10.826636 Returned 0 in 5 seconds
361 22:13:10.927032 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 22:13:10.927406 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 22:13:10.927514 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 22:13:10.927605 Setting prompt string to 'Starting depthcharge on Spherion...'
366 22:13:10.927675 Changing prompt to 'Starting depthcharge on Spherion...'
367 22:13:10.927746 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 22:13:10.928015 [Enter `^Ec?' for help]
369 22:13:11.099222
370 22:13:11.099373
371 22:13:11.099441 F0: 102B 0000
372 22:13:11.099509
373 22:13:11.099570 F3: 1001 0000 [0200]
374 22:13:11.099628
375 22:13:11.102546 F3: 1001 0000
376 22:13:11.102631
377 22:13:11.102698 F7: 102D 0000
378 22:13:11.102760
379 22:13:11.102820 F1: 0000 0000
380 22:13:11.106381
381 22:13:11.106465 V0: 0000 0000 [0001]
382 22:13:11.106532
383 22:13:11.106594 00: 0007 8000
384 22:13:11.106659
385 22:13:11.110440 01: 0000 0000
386 22:13:11.110525
387 22:13:11.110592 BP: 0C00 0209 [0000]
388 22:13:11.110654
389 22:13:11.113888 G0: 1182 0000
390 22:13:11.113972
391 22:13:11.114039 EC: 0000 0021 [4000]
392 22:13:11.114100
393 22:13:11.117218 S7: 0000 0000 [0000]
394 22:13:11.117301
395 22:13:11.117368 CC: 0000 0000 [0001]
396 22:13:11.117431
397 22:13:11.119957 T0: 0000 0040 [010F]
398 22:13:11.120044
399 22:13:11.120111 Jump to BL
400 22:13:11.120172
401 22:13:11.145766
402 22:13:11.145856
403 22:13:11.145923
404 22:13:11.153423 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 22:13:11.157372 ARM64: Exception handlers installed.
406 22:13:11.160472 ARM64: Testing exception
407 22:13:11.163649 ARM64: Done test exception
408 22:13:11.171189 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 22:13:11.182007 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 22:13:11.185517 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 22:13:11.197924 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 22:13:11.204298 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 22:13:11.210967 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 22:13:11.222171 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 22:13:11.228826 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 22:13:11.248792 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 22:13:11.252063 WDT: Last reset was cold boot
418 22:13:11.255534 SPI1(PAD0) initialized at 2873684 Hz
419 22:13:11.258557 SPI5(PAD0) initialized at 992727 Hz
420 22:13:11.261697 VBOOT: Loading verstage.
421 22:13:11.268471 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 22:13:11.272031 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 22:13:11.275270 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 22:13:11.278344 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 22:13:11.286112 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 22:13:11.292453 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 22:13:11.303766 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
428 22:13:11.303848
429 22:13:11.303919
430 22:13:11.313635 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 22:13:11.316762 ARM64: Exception handlers installed.
432 22:13:11.320356 ARM64: Testing exception
433 22:13:11.320432 ARM64: Done test exception
434 22:13:11.327353 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 22:13:11.329907 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 22:13:11.344557 Probing TPM: . done!
437 22:13:11.344642 TPM ready after 0 ms
438 22:13:11.351181 Connected to device vid:did:rid of 1ae0:0028:00
439 22:13:11.361419 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
440 22:13:11.399430 Initialized TPM device CR50 revision 0
441 22:13:11.411473 tlcl_send_startup: Startup return code is 0
442 22:13:11.411561 TPM: setup succeeded
443 22:13:11.423828 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 22:13:11.432374 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 22:13:11.439637 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 22:13:11.452514 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 22:13:11.455868 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 22:13:11.459520 in-header: 03 07 00 00 08 00 00 00
449 22:13:11.462812 in-data: aa e4 47 04 13 02 00 00
450 22:13:11.465758 Chrome EC: UHEPI supported
451 22:13:11.472545 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 22:13:11.475726 in-header: 03 ad 00 00 08 00 00 00
453 22:13:11.478987 in-data: 00 20 20 08 00 00 00 00
454 22:13:11.479134 Phase 1
455 22:13:11.482461 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 22:13:11.489211 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 22:13:11.495689 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 22:13:11.498941 Recovery requested (1009000e)
459 22:13:11.502772 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 22:13:11.511290 tlcl_extend: response is 0
461 22:13:11.519635 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 22:13:11.524903 tlcl_extend: response is 0
463 22:13:11.531481 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 22:13:11.552000 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
465 22:13:11.559259 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 22:13:11.559344
467 22:13:11.559409
468 22:13:11.569286 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 22:13:11.572586 ARM64: Exception handlers installed.
470 22:13:11.575956 ARM64: Testing exception
471 22:13:11.576065 ARM64: Done test exception
472 22:13:11.598296 pmic_efuse_setting: Set efuses in 11 msecs
473 22:13:11.602095 pmwrap_interface_init: Select PMIF_VLD_RDY
474 22:13:11.605687 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 22:13:11.612183 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 22:13:11.615725 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 22:13:11.621940 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 22:13:11.625144 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 22:13:11.632487 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 22:13:11.635375 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 22:13:11.639042 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 22:13:11.645682 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 22:13:11.648952 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 22:13:11.655701 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 22:13:11.658821 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 22:13:11.662410 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 22:13:11.669520 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 22:13:11.675689 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 22:13:11.682191 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 22:13:11.685619 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 22:13:11.692531 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 22:13:11.699047 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 22:13:11.702186 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 22:13:11.709754 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 22:13:11.716711 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 22:13:11.720846 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 22:13:11.724222 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 22:13:11.730830 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 22:13:11.737712 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 22:13:11.741260 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 22:13:11.747933 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 22:13:11.751970 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 22:13:11.754808 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 22:13:11.761622 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 22:13:11.765726 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 22:13:11.772426 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 22:13:11.775581 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 22:13:11.782246 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 22:13:11.785954 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 22:13:11.792301 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 22:13:11.796052 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 22:13:11.799512 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 22:13:11.806326 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 22:13:11.810547 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 22:13:11.813938 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 22:13:11.817008 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 22:13:11.824254 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 22:13:11.827448 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 22:13:11.830749 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 22:13:11.834205 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 22:13:11.840216 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 22:13:11.844047 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 22:13:11.846952 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 22:13:11.853730 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 22:13:11.860072 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 22:13:11.870567 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 22:13:11.873589 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 22:13:11.880345 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 22:13:11.890281 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 22:13:11.893719 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 22:13:11.900420 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 22:13:11.903651 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 22:13:11.910162 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6c, sec=0x2e
534 22:13:11.916714 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 22:13:11.920172 [RTC]rtc_osc_init,62: osc32con val = 0xde6c
536 22:13:11.926311 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 22:13:11.934606 [RTC]rtc_get_frequency_meter,154: input=15, output=835
538 22:13:11.943935 [RTC]rtc_get_frequency_meter,154: input=7, output=709
539 22:13:11.954117 [RTC]rtc_get_frequency_meter,154: input=11, output=773
540 22:13:11.963137 [RTC]rtc_get_frequency_meter,154: input=13, output=803
541 22:13:11.973194 [RTC]rtc_get_frequency_meter,154: input=12, output=788
542 22:13:11.982251 [RTC]rtc_get_frequency_meter,154: input=12, output=788
543 22:13:11.991699 [RTC]rtc_get_frequency_meter,154: input=13, output=803
544 22:13:11.995379 [RTC]rtc_eosc_cali,47: left: 12, middle: 12, right: 13
545 22:13:12.002196 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6c
546 22:13:12.005425 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 22:13:12.008560 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
548 22:13:12.015430 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 22:13:12.018699 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
550 22:13:12.021866 ADC[4]: Raw value=905988 ID=7
551 22:13:12.021939 ADC[3]: Raw value=213282 ID=1
552 22:13:12.025332 RAM Code: 0x71
553 22:13:12.028709 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 22:13:12.035036 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 22:13:12.041950 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
556 22:13:12.048571 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
557 22:13:12.051598 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 22:13:12.055260 in-header: 03 07 00 00 08 00 00 00
559 22:13:12.058232 in-data: aa e4 47 04 13 02 00 00
560 22:13:12.062025 Chrome EC: UHEPI supported
561 22:13:12.068229 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 22:13:12.071158 in-header: 03 dd 00 00 08 00 00 00
563 22:13:12.075041 in-data: 90 20 60 08 00 00 00 00
564 22:13:12.078029 MRC: failed to locate region type 0.
565 22:13:12.084777 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 22:13:12.088137 DRAM-K: Running full calibration
567 22:13:12.095006 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
568 22:13:12.098364 header.status = 0x0
569 22:13:12.098467 header.version = 0x6 (expected: 0x6)
570 22:13:12.104371 header.size = 0xd00 (expected: 0xd00)
571 22:13:12.104476 header.flags = 0x0
572 22:13:12.110766 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 22:13:12.128907 read SPI 0x72590 0x1c583: 12497 us, 9290 KB/s, 74.320 Mbps
574 22:13:12.135292 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 22:13:12.138893 dram_init: ddr_geometry: 2
576 22:13:12.141623 [EMI] MDL number = 2
577 22:13:12.141728 [EMI] Get MDL freq = 0
578 22:13:12.144875 dram_init: ddr_type: 0
579 22:13:12.144947 is_discrete_lpddr4: 1
580 22:13:12.148485 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 22:13:12.148583
582 22:13:12.148674
583 22:13:12.151464 [Bian_co] ETT version 0.0.0.1
584 22:13:12.158447 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
585 22:13:12.158556
586 22:13:12.161767 dramc_set_vcore_voltage set vcore to 650000
587 22:13:12.161866 Read voltage for 800, 4
588 22:13:12.165053 Vio18 = 0
589 22:13:12.165127 Vcore = 650000
590 22:13:12.165189 Vdram = 0
591 22:13:12.168193 Vddq = 0
592 22:13:12.168264 Vmddr = 0
593 22:13:12.171645 dram_init: config_dvfs: 1
594 22:13:12.174692 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 22:13:12.181839 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 22:13:12.184726 [SwImpedanceCal] DRVP=8, DRVN=16, ODTN=9
597 22:13:12.188208 freq_region=0, Reg: DRVP=8, DRVN=16, ODTN=9
598 22:13:12.191347 [SwImpedanceCal] DRVP=14, DRVN=24, ODTN=9
599 22:13:12.195462 freq_region=1, Reg: DRVP=14, DRVN=24, ODTN=9
600 22:13:12.198115 MEM_TYPE=3, freq_sel=18
601 22:13:12.201266 sv_algorithm_assistance_LP4_1600
602 22:13:12.204841 ============ PULL DRAM RESETB DOWN ============
603 22:13:12.211335 ========== PULL DRAM RESETB DOWN end =========
604 22:13:12.214917 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 22:13:12.218113 ===================================
606 22:13:12.221767 LPDDR4 DRAM CONFIGURATION
607 22:13:12.224792 ===================================
608 22:13:12.224867 EX_ROW_EN[0] = 0x0
609 22:13:12.228736 EX_ROW_EN[1] = 0x0
610 22:13:12.228834 LP4Y_EN = 0x0
611 22:13:12.231501 WORK_FSP = 0x0
612 22:13:12.231600 WL = 0x2
613 22:13:12.234602 RL = 0x2
614 22:13:12.234671 BL = 0x2
615 22:13:12.237851 RPST = 0x0
616 22:13:12.237945 RD_PRE = 0x0
617 22:13:12.241076 WR_PRE = 0x1
618 22:13:12.241143 WR_PST = 0x0
619 22:13:12.244515 DBI_WR = 0x0
620 22:13:12.247968 DBI_RD = 0x0
621 22:13:12.248054 OTF = 0x1
622 22:13:12.250989 ===================================
623 22:13:12.255001 ===================================
624 22:13:12.255123 ANA top config
625 22:13:12.258322 ===================================
626 22:13:12.261639 DLL_ASYNC_EN = 0
627 22:13:12.264582 ALL_SLAVE_EN = 1
628 22:13:12.267748 NEW_RANK_MODE = 1
629 22:13:12.267835 DLL_IDLE_MODE = 1
630 22:13:12.271506 LP45_APHY_COMB_EN = 1
631 22:13:12.275167 TX_ODT_DIS = 1
632 22:13:12.278300 NEW_8X_MODE = 1
633 22:13:12.281430 ===================================
634 22:13:12.284830 ===================================
635 22:13:12.288065 data_rate = 1600
636 22:13:12.288151 CKR = 1
637 22:13:12.291605 DQ_P2S_RATIO = 8
638 22:13:12.294877 ===================================
639 22:13:12.297925 CA_P2S_RATIO = 8
640 22:13:12.301251 DQ_CA_OPEN = 0
641 22:13:12.304944 DQ_SEMI_OPEN = 0
642 22:13:12.308038 CA_SEMI_OPEN = 0
643 22:13:12.308124 CA_FULL_RATE = 0
644 22:13:12.311420 DQ_CKDIV4_EN = 1
645 22:13:12.317335 CA_CKDIV4_EN = 1
646 22:13:12.317847 CA_PREDIV_EN = 0
647 22:13:12.321284 PH8_DLY = 0
648 22:13:12.324859 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 22:13:12.324945 DQ_AAMCK_DIV = 4
650 22:13:12.328539 CA_AAMCK_DIV = 4
651 22:13:12.331229 CA_ADMCK_DIV = 4
652 22:13:12.334741 DQ_TRACK_CA_EN = 0
653 22:13:12.337954 CA_PICK = 800
654 22:13:12.340928 CA_MCKIO = 800
655 22:13:12.344466 MCKIO_SEMI = 0
656 22:13:12.344552 PLL_FREQ = 3068
657 22:13:12.347680 DQ_UI_PI_RATIO = 32
658 22:13:12.351185 CA_UI_PI_RATIO = 0
659 22:13:12.354418 ===================================
660 22:13:12.357678 ===================================
661 22:13:12.361131 memory_type:LPDDR4
662 22:13:12.361216 GP_NUM : 10
663 22:13:12.364011 SRAM_EN : 1
664 22:13:12.367570 MD32_EN : 0
665 22:13:12.371040 ===================================
666 22:13:12.371165 [ANA_INIT] >>>>>>>>>>>>>>
667 22:13:12.374237 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 22:13:12.378071 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 22:13:12.380805 ===================================
670 22:13:12.384733 data_rate = 1600,PCW = 0X7600
671 22:13:12.387405 ===================================
672 22:13:12.391256 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 22:13:12.397941 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 22:13:12.401249 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 22:13:12.407746 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 22:13:12.410697 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 22:13:12.413945 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 22:13:12.417269 [ANA_INIT] flow start
679 22:13:12.417355 [ANA_INIT] PLL >>>>>>>>
680 22:13:12.420660 [ANA_INIT] PLL <<<<<<<<
681 22:13:12.424141 [ANA_INIT] MIDPI >>>>>>>>
682 22:13:12.424227 [ANA_INIT] MIDPI <<<<<<<<
683 22:13:12.427247 [ANA_INIT] DLL >>>>>>>>
684 22:13:12.431040 [ANA_INIT] flow end
685 22:13:12.433761 ============ LP4 DIFF to SE enter ============
686 22:13:12.437308 ============ LP4 DIFF to SE exit ============
687 22:13:12.440620 [ANA_INIT] <<<<<<<<<<<<<
688 22:13:12.443850 [Flow] Enable top DCM control >>>>>
689 22:13:12.447272 [Flow] Enable top DCM control <<<<<
690 22:13:12.450492 Enable DLL master slave shuffle
691 22:13:12.454033 ==============================================================
692 22:13:12.457317 Gating Mode config
693 22:13:12.464258 ==============================================================
694 22:13:12.464344 Config description:
695 22:13:12.474127 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 22:13:12.480567 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 22:13:12.484012 SELPH_MODE 0: By rank 1: By Phase
698 22:13:12.490533 ==============================================================
699 22:13:12.493298 GAT_TRACK_EN = 1
700 22:13:12.497183 RX_GATING_MODE = 2
701 22:13:12.499989 RX_GATING_TRACK_MODE = 2
702 22:13:12.503622 SELPH_MODE = 1
703 22:13:12.507233 PICG_EARLY_EN = 1
704 22:13:12.510550 VALID_LAT_VALUE = 1
705 22:13:12.514216 ==============================================================
706 22:13:12.516858 Enter into Gating configuration >>>>
707 22:13:12.520471 Exit from Gating configuration <<<<
708 22:13:12.523471 Enter into DVFS_PRE_config >>>>>
709 22:13:12.536720 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 22:13:12.536810 Exit from DVFS_PRE_config <<<<<
711 22:13:12.540389 Enter into PICG configuration >>>>
712 22:13:12.543198 Exit from PICG configuration <<<<
713 22:13:12.546683 [RX_INPUT] configuration >>>>>
714 22:13:12.549978 [RX_INPUT] configuration <<<<<
715 22:13:12.556984 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 22:13:12.560080 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 22:13:12.567892 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 22:13:12.574958 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 22:13:12.579144 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 22:13:12.585440 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 22:13:12.589372 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 22:13:12.592600 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 22:13:12.596468 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 22:13:12.603369 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 22:13:12.607714 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 22:13:12.611245 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 22:13:12.614725 ===================================
728 22:13:12.614876 LPDDR4 DRAM CONFIGURATION
729 22:13:12.618187 ===================================
730 22:13:12.622152 EX_ROW_EN[0] = 0x0
731 22:13:12.622234 EX_ROW_EN[1] = 0x0
732 22:13:12.625566 LP4Y_EN = 0x0
733 22:13:12.625642 WORK_FSP = 0x0
734 22:13:12.629636 WL = 0x2
735 22:13:12.629728 RL = 0x2
736 22:13:12.632934 BL = 0x2
737 22:13:12.633020 RPST = 0x0
738 22:13:12.637157 RD_PRE = 0x0
739 22:13:12.637249 WR_PRE = 0x1
740 22:13:12.640179 WR_PST = 0x0
741 22:13:12.640275 DBI_WR = 0x0
742 22:13:12.643994 DBI_RD = 0x0
743 22:13:12.644088 OTF = 0x1
744 22:13:12.647701 ===================================
745 22:13:12.651494 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 22:13:12.654816 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 22:13:12.658153 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 22:13:12.661983 ===================================
749 22:13:12.665580 LPDDR4 DRAM CONFIGURATION
750 22:13:12.669174 ===================================
751 22:13:12.669265 EX_ROW_EN[0] = 0x10
752 22:13:12.672586 EX_ROW_EN[1] = 0x0
753 22:13:12.672675 LP4Y_EN = 0x0
754 22:13:12.676583 WORK_FSP = 0x0
755 22:13:12.676673 WL = 0x2
756 22:13:12.680339 RL = 0x2
757 22:13:12.680429 BL = 0x2
758 22:13:12.684348 RPST = 0x0
759 22:13:12.684436 RD_PRE = 0x0
760 22:13:12.687827 WR_PRE = 0x1
761 22:13:12.687915 WR_PST = 0x0
762 22:13:12.691486 DBI_WR = 0x0
763 22:13:12.691574 DBI_RD = 0x0
764 22:13:12.694891 OTF = 0x1
765 22:13:12.699188 ===================================
766 22:13:12.701760 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 22:13:12.706605 nWR fixed to 40
768 22:13:12.710181 [ModeRegInit_LP4] CH0 RK0
769 22:13:12.710305 [ModeRegInit_LP4] CH0 RK1
770 22:13:12.714262 [ModeRegInit_LP4] CH1 RK0
771 22:13:12.717469 [ModeRegInit_LP4] CH1 RK1
772 22:13:12.717555 match AC timing 13
773 22:13:12.720924 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
774 22:13:12.724920 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 22:13:12.731185 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 22:13:12.734677 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 22:13:12.738513 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 22:13:12.741392 [EMI DOE] emi_dcm 0
779 22:13:12.744690 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 22:13:12.744776 ==
781 22:13:12.748264 Dram Type= 6, Freq= 0, CH_0, rank 0
782 22:13:12.754867 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
783 22:13:12.754956 ==
784 22:13:12.758095 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 22:13:12.764622 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 22:13:12.773925 [CA 0] Center 37 (7~68) winsize 62
787 22:13:12.777157 [CA 1] Center 37 (6~68) winsize 63
788 22:13:12.781264 [CA 2] Center 34 (4~65) winsize 62
789 22:13:12.784150 [CA 3] Center 34 (4~65) winsize 62
790 22:13:12.788307 [CA 4] Center 33 (3~64) winsize 62
791 22:13:12.791107 [CA 5] Center 33 (3~64) winsize 62
792 22:13:12.791213
793 22:13:12.794203 [CmdBusTrainingLP45] Vref(ca) range 1: 34
794 22:13:12.794299
795 22:13:12.797621 [CATrainingPosCal] consider 1 rank data
796 22:13:12.801024 u2DelayCellTimex100 = 270/100 ps
797 22:13:12.804409 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
798 22:13:12.807714 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
799 22:13:12.814121 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
800 22:13:12.817339 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
801 22:13:12.820972 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
802 22:13:12.824045 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
803 22:13:12.824142
804 22:13:12.827590 CA PerBit enable=1, Macro0, CA PI delay=33
805 22:13:12.827705
806 22:13:12.830878 [CBTSetCACLKResult] CA Dly = 33
807 22:13:12.830991 CS Dly: 7 (0~38)
808 22:13:12.831101 ==
809 22:13:12.834598 Dram Type= 6, Freq= 0, CH_0, rank 1
810 22:13:12.840636 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 22:13:12.840724 ==
812 22:13:12.844686 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 22:13:12.850659 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 22:13:12.860167 [CA 0] Center 36 (6~67) winsize 62
815 22:13:12.863728 [CA 1] Center 37 (7~68) winsize 62
816 22:13:12.866889 [CA 2] Center 34 (4~65) winsize 62
817 22:13:12.870396 [CA 3] Center 34 (4~65) winsize 62
818 22:13:12.873594 [CA 4] Center 33 (3~64) winsize 62
819 22:13:12.876870 [CA 5] Center 33 (2~64) winsize 63
820 22:13:12.876957
821 22:13:12.880349 [CmdBusTrainingLP45] Vref(ca) range 1: 34
822 22:13:12.880436
823 22:13:12.883578 [CATrainingPosCal] consider 2 rank data
824 22:13:12.886884 u2DelayCellTimex100 = 270/100 ps
825 22:13:12.890414 CA0 delay=37 (7~67),Diff = 4 PI (28 cell)
826 22:13:12.894068 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
827 22:13:12.897235 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
828 22:13:12.900814 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
829 22:13:12.907984 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
830 22:13:12.911744 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
831 22:13:12.911873
832 22:13:12.915304 CA PerBit enable=1, Macro0, CA PI delay=33
833 22:13:12.915391
834 22:13:12.915459 [CBTSetCACLKResult] CA Dly = 33
835 22:13:12.918390 CS Dly: 7 (0~38)
836 22:13:12.918478
837 22:13:12.922199 ----->DramcWriteLeveling(PI) begin...
838 22:13:12.922290 ==
839 22:13:12.925396 Dram Type= 6, Freq= 0, CH_0, rank 0
840 22:13:12.929343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
841 22:13:12.929449 ==
842 22:13:12.932396 Write leveling (Byte 0): 32 => 32
843 22:13:12.935679 Write leveling (Byte 1): 31 => 31
844 22:13:12.938973 DramcWriteLeveling(PI) end<-----
845 22:13:12.939094
846 22:13:12.939166 ==
847 22:13:12.942485 Dram Type= 6, Freq= 0, CH_0, rank 0
848 22:13:12.945455 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
849 22:13:12.945564 ==
850 22:13:12.949488 [Gating] SW mode calibration
851 22:13:12.955415 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 22:13:12.962056 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 22:13:12.965661 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
854 22:13:12.969107 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
855 22:13:12.975654 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
856 22:13:12.978934 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
857 22:13:12.982426 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 22:13:12.988798 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 22:13:12.992504 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 22:13:12.995848 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 22:13:13.002516 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 22:13:13.005732 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 22:13:13.008772 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 22:13:13.015365 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 22:13:13.019067 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 22:13:13.022866 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 22:13:13.029362 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 22:13:13.032059 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 22:13:13.036034 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 22:13:13.042397 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
871 22:13:13.045388 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
872 22:13:13.049043 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
873 22:13:13.055490 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 22:13:13.058616 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 22:13:13.062295 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 22:13:13.068926 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 22:13:13.072374 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 22:13:13.075706 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
879 22:13:13.082160 0 9 8 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (1 1)
880 22:13:13.085426 0 9 12 | B1->B0 | 2929 3434 | 1 1 | (1 1) (1 1)
881 22:13:13.088892 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 22:13:13.091856 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 22:13:13.098504 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 22:13:13.102253 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 22:13:13.105409 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
886 22:13:13.112049 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
887 22:13:13.115001 0 10 8 | B1->B0 | 3333 2b2b | 0 1 | (0 0) (1 0)
888 22:13:13.118593 0 10 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
889 22:13:13.124938 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 22:13:13.128749 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 22:13:13.131718 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 22:13:13.138687 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 22:13:13.141742 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
894 22:13:13.145167 0 11 4 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
895 22:13:13.151627 0 11 8 | B1->B0 | 2524 3d3d | 1 0 | (0 0) (0 0)
896 22:13:13.155026 0 11 12 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
897 22:13:13.158409 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 22:13:13.165338 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 22:13:13.168575 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 22:13:13.171820 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 22:13:13.178317 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
902 22:13:13.181610 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
903 22:13:13.184922 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
904 22:13:13.191455 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 22:13:13.194541 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 22:13:13.198414 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 22:13:13.204666 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 22:13:13.208064 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 22:13:13.211304 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 22:13:13.217879 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 22:13:13.221118 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 22:13:13.224330 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 22:13:13.230872 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 22:13:13.234411 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 22:13:13.238386 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 22:13:13.244441 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 22:13:13.247595 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
918 22:13:13.251159 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
919 22:13:13.254450 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
920 22:13:13.261082 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
921 22:13:13.264455 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
922 22:13:13.268263 Total UI for P1: 0, mck2ui 16
923 22:13:13.271427 best dqsien dly found for B0: ( 0, 14, 8)
924 22:13:13.274398 Total UI for P1: 0, mck2ui 16
925 22:13:13.277511 best dqsien dly found for B1: ( 0, 14, 10)
926 22:13:13.280884 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
927 22:13:13.284101 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
928 22:13:13.284175
929 22:13:13.287734 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
930 22:13:13.291436 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
931 22:13:13.294572 [Gating] SW calibration Done
932 22:13:13.294684 ==
933 22:13:13.298489 Dram Type= 6, Freq= 0, CH_0, rank 0
934 22:13:13.301664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
935 22:13:13.301773 ==
936 22:13:13.305216 RX Vref Scan: 0
937 22:13:13.305295
938 22:13:13.308490 RX Vref 0 -> 0, step: 1
939 22:13:13.308562
940 22:13:13.308651 RX Delay -130 -> 252, step: 16
941 22:13:13.315215 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
942 22:13:13.318814 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
943 22:13:13.321631 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
944 22:13:13.324872 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
945 22:13:13.331510 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
946 22:13:13.334980 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
947 22:13:13.338393 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
948 22:13:13.341186 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
949 22:13:13.345333 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
950 22:13:13.351596 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
951 22:13:13.354555 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
952 22:13:13.358359 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
953 22:13:13.360955 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
954 22:13:13.364572 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
955 22:13:13.371071 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
956 22:13:13.374359 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
957 22:13:13.374471 ==
958 22:13:13.378046 Dram Type= 6, Freq= 0, CH_0, rank 0
959 22:13:13.381194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
960 22:13:13.381277 ==
961 22:13:13.384610 DQS Delay:
962 22:13:13.384693 DQS0 = 0, DQS1 = 0
963 22:13:13.384758 DQM Delay:
964 22:13:13.387761 DQM0 = 86, DQM1 = 73
965 22:13:13.387843 DQ Delay:
966 22:13:13.391380 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
967 22:13:13.394524 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =93
968 22:13:13.397804 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
969 22:13:13.401810 DQ12 =77, DQ13 =77, DQ14 =85, DQ15 =85
970 22:13:13.401892
971 22:13:13.401957
972 22:13:13.402016 ==
973 22:13:13.404750 Dram Type= 6, Freq= 0, CH_0, rank 0
974 22:13:13.408104 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
975 22:13:13.411838 ==
976 22:13:13.411919
977 22:13:13.411984
978 22:13:13.412043 TX Vref Scan disable
979 22:13:13.415193 == TX Byte 0 ==
980 22:13:13.418588 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
981 22:13:13.421970 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
982 22:13:13.425584 == TX Byte 1 ==
983 22:13:13.429101 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
984 22:13:13.432643 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
985 22:13:13.432732 ==
986 22:13:13.436261 Dram Type= 6, Freq= 0, CH_0, rank 0
987 22:13:13.439639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
988 22:13:13.439722 ==
989 22:13:13.453716 TX Vref=22, minBit 5, minWin=27, winSum=445
990 22:13:13.457461 TX Vref=24, minBit 5, minWin=27, winSum=446
991 22:13:13.460885 TX Vref=26, minBit 1, minWin=28, winSum=449
992 22:13:13.464729 TX Vref=28, minBit 10, minWin=27, winSum=449
993 22:13:13.468156 TX Vref=30, minBit 10, minWin=27, winSum=448
994 22:13:13.471473 TX Vref=32, minBit 13, minWin=26, winSum=445
995 22:13:13.478925 [TxChooseVref] Worse bit 1, Min win 28, Win sum 449, Final Vref 26
996 22:13:13.479010
997 22:13:13.479111 Final TX Range 1 Vref 26
998 22:13:13.479174
999 22:13:13.482316 ==
1000 22:13:13.482399 Dram Type= 6, Freq= 0, CH_0, rank 0
1001 22:13:13.489885 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1002 22:13:13.489969 ==
1003 22:13:13.490037
1004 22:13:13.490114
1005 22:13:13.490186 TX Vref Scan disable
1006 22:13:13.493523 == TX Byte 0 ==
1007 22:13:13.497194 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1008 22:13:13.501319 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1009 22:13:13.504992 == TX Byte 1 ==
1010 22:13:13.508510 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1011 22:13:13.512444 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1012 22:13:13.512529
1013 22:13:13.512594 [DATLAT]
1014 22:13:13.515856 Freq=800, CH0 RK0
1015 22:13:13.515939
1016 22:13:13.516004 DATLAT Default: 0xa
1017 22:13:13.519522 0, 0xFFFF, sum = 0
1018 22:13:13.519606 1, 0xFFFF, sum = 0
1019 22:13:13.523040 2, 0xFFFF, sum = 0
1020 22:13:13.523144 3, 0xFFFF, sum = 0
1021 22:13:13.526426 4, 0xFFFF, sum = 0
1022 22:13:13.526510 5, 0xFFFF, sum = 0
1023 22:13:13.530580 6, 0xFFFF, sum = 0
1024 22:13:13.530664 7, 0xFFFF, sum = 0
1025 22:13:13.534247 8, 0xFFFF, sum = 0
1026 22:13:13.534329 9, 0x0, sum = 1
1027 22:13:13.534400 10, 0x0, sum = 2
1028 22:13:13.537946 11, 0x0, sum = 3
1029 22:13:13.538029 12, 0x0, sum = 4
1030 22:13:13.541420 best_step = 10
1031 22:13:13.541537
1032 22:13:13.541602 ==
1033 22:13:13.545103 Dram Type= 6, Freq= 0, CH_0, rank 0
1034 22:13:13.548716 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1035 22:13:13.548799 ==
1036 22:13:13.548864 RX Vref Scan: 1
1037 22:13:13.548924
1038 22:13:13.552125 Set Vref Range= 32 -> 127
1039 22:13:13.552206
1040 22:13:13.555815 RX Vref 32 -> 127, step: 1
1041 22:13:13.555896
1042 22:13:13.555961 RX Delay -111 -> 252, step: 8
1043 22:13:13.558920
1044 22:13:13.559027 Set Vref, RX VrefLevel [Byte0]: 32
1045 22:13:13.562752 [Byte1]: 32
1046 22:13:13.566757
1047 22:13:13.566857 Set Vref, RX VrefLevel [Byte0]: 33
1048 22:13:13.570341 [Byte1]: 33
1049 22:13:13.574674
1050 22:13:13.574758 Set Vref, RX VrefLevel [Byte0]: 34
1051 22:13:13.577968 [Byte1]: 34
1052 22:13:13.581878
1053 22:13:13.581959 Set Vref, RX VrefLevel [Byte0]: 35
1054 22:13:13.585102 [Byte1]: 35
1055 22:13:13.589505
1056 22:13:13.589586 Set Vref, RX VrefLevel [Byte0]: 36
1057 22:13:13.592669 [Byte1]: 36
1058 22:13:13.597250
1059 22:13:13.597332 Set Vref, RX VrefLevel [Byte0]: 37
1060 22:13:13.600783 [Byte1]: 37
1061 22:13:13.604959
1062 22:13:13.605040 Set Vref, RX VrefLevel [Byte0]: 38
1063 22:13:13.608991 [Byte1]: 38
1064 22:13:13.613032
1065 22:13:13.613137 Set Vref, RX VrefLevel [Byte0]: 39
1066 22:13:13.616391 [Byte1]: 39
1067 22:13:13.620287
1068 22:13:13.620392 Set Vref, RX VrefLevel [Byte0]: 40
1069 22:13:13.623706 [Byte1]: 40
1070 22:13:13.628120
1071 22:13:13.628204 Set Vref, RX VrefLevel [Byte0]: 41
1072 22:13:13.631399 [Byte1]: 41
1073 22:13:13.635242
1074 22:13:13.635353 Set Vref, RX VrefLevel [Byte0]: 42
1075 22:13:13.639403 [Byte1]: 42
1076 22:13:13.642978
1077 22:13:13.643083 Set Vref, RX VrefLevel [Byte0]: 43
1078 22:13:13.646524 [Byte1]: 43
1079 22:13:13.650374
1080 22:13:13.650489 Set Vref, RX VrefLevel [Byte0]: 44
1081 22:13:13.653787 [Byte1]: 44
1082 22:13:13.658384
1083 22:13:13.658465 Set Vref, RX VrefLevel [Byte0]: 45
1084 22:13:13.661918 [Byte1]: 45
1085 22:13:13.666334
1086 22:13:13.666416 Set Vref, RX VrefLevel [Byte0]: 46
1087 22:13:13.669180 [Byte1]: 46
1088 22:13:13.673618
1089 22:13:13.673746 Set Vref, RX VrefLevel [Byte0]: 47
1090 22:13:13.676621 [Byte1]: 47
1091 22:13:13.681310
1092 22:13:13.681388 Set Vref, RX VrefLevel [Byte0]: 48
1093 22:13:13.684686 [Byte1]: 48
1094 22:13:13.689222
1095 22:13:13.689303 Set Vref, RX VrefLevel [Byte0]: 49
1096 22:13:13.692056 [Byte1]: 49
1097 22:13:13.696626
1098 22:13:13.696708 Set Vref, RX VrefLevel [Byte0]: 50
1099 22:13:13.700097 [Byte1]: 50
1100 22:13:13.704512
1101 22:13:13.704593 Set Vref, RX VrefLevel [Byte0]: 51
1102 22:13:13.707619 [Byte1]: 51
1103 22:13:13.712075
1104 22:13:13.712168 Set Vref, RX VrefLevel [Byte0]: 52
1105 22:13:13.715465 [Byte1]: 52
1106 22:13:13.719836
1107 22:13:13.719944 Set Vref, RX VrefLevel [Byte0]: 53
1108 22:13:13.722827 [Byte1]: 53
1109 22:13:13.727584
1110 22:13:13.727668 Set Vref, RX VrefLevel [Byte0]: 54
1111 22:13:13.730507 [Byte1]: 54
1112 22:13:13.734923
1113 22:13:13.735015 Set Vref, RX VrefLevel [Byte0]: 55
1114 22:13:13.738231 [Byte1]: 55
1115 22:13:13.742293
1116 22:13:13.742380 Set Vref, RX VrefLevel [Byte0]: 56
1117 22:13:13.745681 [Byte1]: 56
1118 22:13:13.749835
1119 22:13:13.749924 Set Vref, RX VrefLevel [Byte0]: 57
1120 22:13:13.753228 [Byte1]: 57
1121 22:13:13.757831
1122 22:13:13.757916 Set Vref, RX VrefLevel [Byte0]: 58
1123 22:13:13.761138 [Byte1]: 58
1124 22:13:13.765242
1125 22:13:13.765323 Set Vref, RX VrefLevel [Byte0]: 59
1126 22:13:13.768679 [Byte1]: 59
1127 22:13:13.773170
1128 22:13:13.773251 Set Vref, RX VrefLevel [Byte0]: 60
1129 22:13:13.776067 [Byte1]: 60
1130 22:13:13.781379
1131 22:13:13.781460 Set Vref, RX VrefLevel [Byte0]: 61
1132 22:13:13.783928 [Byte1]: 61
1133 22:13:13.787859
1134 22:13:13.787939 Set Vref, RX VrefLevel [Byte0]: 62
1135 22:13:13.791757 [Byte1]: 62
1136 22:13:13.795731
1137 22:13:13.795811 Set Vref, RX VrefLevel [Byte0]: 63
1138 22:13:13.799210 [Byte1]: 63
1139 22:13:13.803384
1140 22:13:13.803466 Set Vref, RX VrefLevel [Byte0]: 64
1141 22:13:13.806491 [Byte1]: 64
1142 22:13:13.810837
1143 22:13:13.810957 Set Vref, RX VrefLevel [Byte0]: 65
1144 22:13:13.814486 [Byte1]: 65
1145 22:13:13.818642
1146 22:13:13.818743 Set Vref, RX VrefLevel [Byte0]: 66
1147 22:13:13.822622 [Byte1]: 66
1148 22:13:13.826866
1149 22:13:13.826963 Set Vref, RX VrefLevel [Byte0]: 67
1150 22:13:13.829971 [Byte1]: 67
1151 22:13:13.833867
1152 22:13:13.833976 Set Vref, RX VrefLevel [Byte0]: 68
1153 22:13:13.837491 [Byte1]: 68
1154 22:13:13.841963
1155 22:13:13.842071 Set Vref, RX VrefLevel [Byte0]: 69
1156 22:13:13.845319 [Byte1]: 69
1157 22:13:13.849104
1158 22:13:13.849204 Set Vref, RX VrefLevel [Byte0]: 70
1159 22:13:13.853160 [Byte1]: 70
1160 22:13:13.857062
1161 22:13:13.857163 Set Vref, RX VrefLevel [Byte0]: 71
1162 22:13:13.860544 [Byte1]: 71
1163 22:13:13.864700
1164 22:13:13.864801 Set Vref, RX VrefLevel [Byte0]: 72
1165 22:13:13.867908 [Byte1]: 72
1166 22:13:13.872501
1167 22:13:13.872602 Set Vref, RX VrefLevel [Byte0]: 73
1168 22:13:13.876018 [Byte1]: 73
1169 22:13:13.880011
1170 22:13:13.880117 Set Vref, RX VrefLevel [Byte0]: 74
1171 22:13:13.883256 [Byte1]: 74
1172 22:13:13.888056
1173 22:13:13.888155 Set Vref, RX VrefLevel [Byte0]: 75
1174 22:13:13.890879 [Byte1]: 75
1175 22:13:13.895130
1176 22:13:13.895233 Set Vref, RX VrefLevel [Byte0]: 76
1177 22:13:13.898626 [Byte1]: 76
1178 22:13:13.902956
1179 22:13:13.903086 Set Vref, RX VrefLevel [Byte0]: 77
1180 22:13:13.906364 [Byte1]: 77
1181 22:13:13.910425
1182 22:13:13.910527 Set Vref, RX VrefLevel [Byte0]: 78
1183 22:13:13.914003 [Byte1]: 78
1184 22:13:13.917949
1185 22:13:13.918052 Set Vref, RX VrefLevel [Byte0]: 79
1186 22:13:13.921755 [Byte1]: 79
1187 22:13:13.925410
1188 22:13:13.929208 Final RX Vref Byte 0 = 69 to rank0
1189 22:13:13.929332 Final RX Vref Byte 1 = 58 to rank0
1190 22:13:13.932551 Final RX Vref Byte 0 = 69 to rank1
1191 22:13:13.936461 Final RX Vref Byte 1 = 58 to rank1==
1192 22:13:13.940011 Dram Type= 6, Freq= 0, CH_0, rank 0
1193 22:13:13.943332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1194 22:13:13.943407 ==
1195 22:13:13.946754 DQS Delay:
1196 22:13:13.946849 DQS0 = 0, DQS1 = 0
1197 22:13:13.950468 DQM Delay:
1198 22:13:13.950561 DQM0 = 88, DQM1 = 75
1199 22:13:13.950651 DQ Delay:
1200 22:13:13.953293 DQ0 =88, DQ1 =92, DQ2 =84, DQ3 =84
1201 22:13:13.956935 DQ4 =88, DQ5 =76, DQ6 =100, DQ7 =96
1202 22:13:13.960646 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =68
1203 22:13:13.964581 DQ12 =80, DQ13 =76, DQ14 =88, DQ15 =84
1204 22:13:13.964680
1205 22:13:13.964771
1206 22:13:13.971449 [DQSOSCAuto] RK0, (LSB)MR18= 0x4325, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 393 ps
1207 22:13:13.974889 CH0 RK0: MR19=606, MR18=4325
1208 22:13:13.982562 CH0_RK0: MR19=0x606, MR18=0x4325, DQSOSC=393, MR23=63, INC=95, DEC=63
1209 22:13:13.982671
1210 22:13:13.985734 ----->DramcWriteLeveling(PI) begin...
1211 22:13:13.985811 ==
1212 22:13:13.989531 Dram Type= 6, Freq= 0, CH_0, rank 1
1213 22:13:13.993244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1214 22:13:13.993344 ==
1215 22:13:13.996753 Write leveling (Byte 0): 33 => 33
1216 22:13:14.000507 Write leveling (Byte 1): 32 => 32
1217 22:13:14.000579 DramcWriteLeveling(PI) end<-----
1218 22:13:14.000641
1219 22:13:14.000716 ==
1220 22:13:14.004442 Dram Type= 6, Freq= 0, CH_0, rank 1
1221 22:13:14.011640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1222 22:13:14.011812 ==
1223 22:13:14.011970 [Gating] SW mode calibration
1224 22:13:14.018832 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1225 22:13:14.065816 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1226 22:13:14.065954 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1227 22:13:14.066696 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1228 22:13:14.067121 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1229 22:13:14.067535 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 22:13:14.067789 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 22:13:14.067855 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 22:13:14.068099 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 22:13:14.068346 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 22:13:14.068626 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 22:13:14.110126 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 22:13:14.110246 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 22:13:14.110532 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 22:13:14.111035 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 22:13:14.111325 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 22:13:14.111778 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 22:13:14.111877 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 22:13:14.112169 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 22:13:14.112280 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1244 22:13:14.112556 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1245 22:13:14.154373 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1246 22:13:14.154483 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1247 22:13:14.154754 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1248 22:13:14.154839 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1249 22:13:14.155384 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1250 22:13:14.155765 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1251 22:13:14.155873 0 9 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
1252 22:13:14.156341 0 9 8 | B1->B0 | 2323 2e2e | 0 0 | (1 1) (0 0)
1253 22:13:14.156636 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (0 0) (1 1)
1254 22:13:14.156892 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1255 22:13:14.198474 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1256 22:13:14.198569 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1257 22:13:14.198831 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1258 22:13:14.199308 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1259 22:13:14.200417 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1260 22:13:14.201023 0 10 8 | B1->B0 | 2f2f 2929 | 0 0 | (1 0) (0 0)
1261 22:13:14.201105 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
1262 22:13:14.201348 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1263 22:13:14.201413 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1264 22:13:14.201482 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1265 22:13:14.242377 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1266 22:13:14.242461 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1267 22:13:14.242708 0 11 4 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
1268 22:13:14.242962 0 11 8 | B1->B0 | 2e2d 3939 | 1 0 | (0 0) (0 0)
1269 22:13:14.243027 0 11 12 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
1270 22:13:14.243119 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1271 22:13:14.243179 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1272 22:13:14.243285 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1273 22:13:14.243814 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1274 22:13:14.244451 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1275 22:13:14.273001 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1276 22:13:14.273113 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1277 22:13:14.273732 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 22:13:14.274004 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 22:13:14.274113 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1280 22:13:14.274374 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1281 22:13:14.274442 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1282 22:13:14.277377 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1283 22:13:14.280532 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1284 22:13:14.283704 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1285 22:13:14.287208 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1286 22:13:14.293945 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1287 22:13:14.296882 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1288 22:13:14.300196 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1289 22:13:14.307202 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1290 22:13:14.310570 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1291 22:13:14.313523 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1292 22:13:14.320349 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1293 22:13:14.320431 Total UI for P1: 0, mck2ui 16
1294 22:13:14.327176 best dqsien dly found for B0: ( 0, 14, 4)
1295 22:13:14.330264 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1296 22:13:14.333466 Total UI for P1: 0, mck2ui 16
1297 22:13:14.336585 best dqsien dly found for B1: ( 0, 14, 8)
1298 22:13:14.340103 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1299 22:13:14.343231 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1300 22:13:14.343313
1301 22:13:14.346843 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1302 22:13:14.350173 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1303 22:13:14.353156 [Gating] SW calibration Done
1304 22:13:14.353238 ==
1305 22:13:14.356914 Dram Type= 6, Freq= 0, CH_0, rank 1
1306 22:13:14.359796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1307 22:13:14.363626 ==
1308 22:13:14.363707 RX Vref Scan: 0
1309 22:13:14.363771
1310 22:13:14.366461 RX Vref 0 -> 0, step: 1
1311 22:13:14.366543
1312 22:13:14.370085 RX Delay -130 -> 252, step: 16
1313 22:13:14.373098 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1314 22:13:14.376751 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1315 22:13:14.380135 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1316 22:13:14.383178 iDelay=222, Bit 3, Center 69 (-50 ~ 189) 240
1317 22:13:14.389793 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1318 22:13:14.393064 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1319 22:13:14.396633 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1320 22:13:14.399909 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1321 22:13:14.403131 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1322 22:13:14.406412 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1323 22:13:14.413568 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1324 22:13:14.416676 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1325 22:13:14.420041 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1326 22:13:14.423258 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1327 22:13:14.429630 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1328 22:13:14.433100 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1329 22:13:14.433182 ==
1330 22:13:14.436540 Dram Type= 6, Freq= 0, CH_0, rank 1
1331 22:13:14.439838 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1332 22:13:14.439920 ==
1333 22:13:14.443113 DQS Delay:
1334 22:13:14.443193 DQS0 = 0, DQS1 = 0
1335 22:13:14.443258 DQM Delay:
1336 22:13:14.446464 DQM0 = 83, DQM1 = 76
1337 22:13:14.446545 DQ Delay:
1338 22:13:14.449877 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =69
1339 22:13:14.452880 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1340 22:13:14.456770 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =69
1341 22:13:14.459424 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1342 22:13:14.459505
1343 22:13:14.459569
1344 22:13:14.459627 ==
1345 22:13:14.462601 Dram Type= 6, Freq= 0, CH_0, rank 1
1346 22:13:14.469681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1347 22:13:14.469762 ==
1348 22:13:14.469827
1349 22:13:14.469885
1350 22:13:14.469956 TX Vref Scan disable
1351 22:13:14.472973 == TX Byte 0 ==
1352 22:13:14.475981 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1353 22:13:14.479925 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1354 22:13:14.482976 == TX Byte 1 ==
1355 22:13:14.486365 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1356 22:13:14.492620 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1357 22:13:14.492701 ==
1358 22:13:14.496217 Dram Type= 6, Freq= 0, CH_0, rank 1
1359 22:13:14.499568 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1360 22:13:14.499650 ==
1361 22:13:14.512219 TX Vref=22, minBit 5, minWin=27, winSum=444
1362 22:13:14.515334 TX Vref=24, minBit 11, minWin=27, winSum=446
1363 22:13:14.518570 TX Vref=26, minBit 9, minWin=27, winSum=445
1364 22:13:14.521597 TX Vref=28, minBit 9, minWin=27, winSum=445
1365 22:13:14.525084 TX Vref=30, minBit 9, minWin=27, winSum=447
1366 22:13:14.532265 TX Vref=32, minBit 9, minWin=27, winSum=444
1367 22:13:14.535254 [TxChooseVref] Worse bit 9, Min win 27, Win sum 447, Final Vref 30
1368 22:13:14.535336
1369 22:13:14.538651 Final TX Range 1 Vref 30
1370 22:13:14.538731
1371 22:13:14.538795 ==
1372 22:13:14.542104 Dram Type= 6, Freq= 0, CH_0, rank 1
1373 22:13:14.545295 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1374 22:13:14.545384 ==
1375 22:13:14.548447
1376 22:13:14.548526
1377 22:13:14.548588 TX Vref Scan disable
1378 22:13:14.551709 == TX Byte 0 ==
1379 22:13:14.555330 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1380 22:13:14.558450 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1381 22:13:14.561759 == TX Byte 1 ==
1382 22:13:14.565434 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1383 22:13:14.568605 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1384 22:13:14.571979
1385 22:13:14.572057 [DATLAT]
1386 22:13:14.572120 Freq=800, CH0 RK1
1387 22:13:14.572179
1388 22:13:14.575418 DATLAT Default: 0xa
1389 22:13:14.575497 0, 0xFFFF, sum = 0
1390 22:13:14.578496 1, 0xFFFF, sum = 0
1391 22:13:14.578576 2, 0xFFFF, sum = 0
1392 22:13:14.581658 3, 0xFFFF, sum = 0
1393 22:13:14.581740 4, 0xFFFF, sum = 0
1394 22:13:14.585298 5, 0xFFFF, sum = 0
1395 22:13:14.588744 6, 0xFFFF, sum = 0
1396 22:13:14.588824 7, 0xFFFF, sum = 0
1397 22:13:14.591838 8, 0xFFFF, sum = 0
1398 22:13:14.591921 9, 0x0, sum = 1
1399 22:13:14.591985 10, 0x0, sum = 2
1400 22:13:14.595375 11, 0x0, sum = 3
1401 22:13:14.595456 12, 0x0, sum = 4
1402 22:13:14.598457 best_step = 10
1403 22:13:14.598537
1404 22:13:14.598600 ==
1405 22:13:14.602153 Dram Type= 6, Freq= 0, CH_0, rank 1
1406 22:13:14.605381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1407 22:13:14.605463 ==
1408 22:13:14.608563 RX Vref Scan: 0
1409 22:13:14.608642
1410 22:13:14.608705 RX Vref 0 -> 0, step: 1
1411 22:13:14.608762
1412 22:13:14.611657 RX Delay -111 -> 252, step: 8
1413 22:13:14.618661 iDelay=217, Bit 0, Center 84 (-31 ~ 200) 232
1414 22:13:14.622237 iDelay=217, Bit 1, Center 88 (-23 ~ 200) 224
1415 22:13:14.625496 iDelay=217, Bit 2, Center 80 (-39 ~ 200) 240
1416 22:13:14.628698 iDelay=217, Bit 3, Center 80 (-39 ~ 200) 240
1417 22:13:14.631850 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
1418 22:13:14.638514 iDelay=217, Bit 5, Center 76 (-39 ~ 192) 232
1419 22:13:14.641695 iDelay=217, Bit 6, Center 96 (-15 ~ 208) 224
1420 22:13:14.645516 iDelay=217, Bit 7, Center 96 (-23 ~ 216) 240
1421 22:13:14.648690 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
1422 22:13:14.651749 iDelay=217, Bit 9, Center 64 (-47 ~ 176) 224
1423 22:13:14.658427 iDelay=217, Bit 10, Center 80 (-39 ~ 200) 240
1424 22:13:14.661857 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
1425 22:13:14.665310 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
1426 22:13:14.668605 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1427 22:13:14.675619 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
1428 22:13:14.678267 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1429 22:13:14.678346 ==
1430 22:13:14.681623 Dram Type= 6, Freq= 0, CH_0, rank 1
1431 22:13:14.685283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1432 22:13:14.685364 ==
1433 22:13:14.685427 DQS Delay:
1434 22:13:14.688729 DQS0 = 0, DQS1 = 0
1435 22:13:14.688814 DQM Delay:
1436 22:13:14.691689 DQM0 = 85, DQM1 = 77
1437 22:13:14.691768 DQ Delay:
1438 22:13:14.694782 DQ0 =84, DQ1 =88, DQ2 =80, DQ3 =80
1439 22:13:14.698257 DQ4 =84, DQ5 =76, DQ6 =96, DQ7 =96
1440 22:13:14.701490 DQ8 =68, DQ9 =64, DQ10 =80, DQ11 =68
1441 22:13:14.705171 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
1442 22:13:14.705251
1443 22:13:14.705315
1444 22:13:14.714657 [DQSOSCAuto] RK1, (LSB)MR18= 0x4005, (MSB)MR19= 0x606, tDQSOscB0 = 408 ps tDQSOscB1 = 393 ps
1445 22:13:14.714739 CH0 RK1: MR19=606, MR18=4005
1446 22:13:14.721436 CH0_RK1: MR19=0x606, MR18=0x4005, DQSOSC=393, MR23=63, INC=95, DEC=63
1447 22:13:14.724526 [RxdqsGatingPostProcess] freq 800
1448 22:13:14.731206 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1449 22:13:14.734729 Pre-setting of DQS Precalculation
1450 22:13:14.738098 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1451 22:13:14.738180 ==
1452 22:13:14.741288 Dram Type= 6, Freq= 0, CH_1, rank 0
1453 22:13:14.748044 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1454 22:13:14.748126 ==
1455 22:13:14.751035 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1456 22:13:14.757830 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1457 22:13:14.767632 [CA 0] Center 36 (6~67) winsize 62
1458 22:13:14.770307 [CA 1] Center 36 (6~67) winsize 62
1459 22:13:14.773936 [CA 2] Center 34 (4~65) winsize 62
1460 22:13:14.777223 [CA 3] Center 34 (3~65) winsize 63
1461 22:13:14.780406 [CA 4] Center 34 (4~65) winsize 62
1462 22:13:14.783534 [CA 5] Center 34 (3~65) winsize 63
1463 22:13:14.783615
1464 22:13:14.787177 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1465 22:13:14.787259
1466 22:13:14.790052 [CATrainingPosCal] consider 1 rank data
1467 22:13:14.793756 u2DelayCellTimex100 = 270/100 ps
1468 22:13:14.796925 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1469 22:13:14.803660 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1470 22:13:14.806816 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1471 22:13:14.809908 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1472 22:13:14.813445 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1473 22:13:14.817094 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1474 22:13:14.817171
1475 22:13:14.820009 CA PerBit enable=1, Macro0, CA PI delay=34
1476 22:13:14.820112
1477 22:13:14.823812 [CBTSetCACLKResult] CA Dly = 34
1478 22:13:14.823947 CS Dly: 5 (0~36)
1479 22:13:14.826649 ==
1480 22:13:14.830014 Dram Type= 6, Freq= 0, CH_1, rank 1
1481 22:13:14.833785 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1482 22:13:14.833868 ==
1483 22:13:14.836730 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1484 22:13:14.843915 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1485 22:13:14.853123 [CA 0] Center 36 (6~67) winsize 62
1486 22:13:14.856237 [CA 1] Center 37 (6~68) winsize 63
1487 22:13:14.859686 [CA 2] Center 34 (4~65) winsize 62
1488 22:13:14.863459 [CA 3] Center 34 (3~65) winsize 63
1489 22:13:14.866960 [CA 4] Center 34 (4~65) winsize 62
1490 22:13:14.869726 [CA 5] Center 33 (3~64) winsize 62
1491 22:13:14.869811
1492 22:13:14.873497 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1493 22:13:14.873582
1494 22:13:14.876140 [CATrainingPosCal] consider 2 rank data
1495 22:13:14.879770 u2DelayCellTimex100 = 270/100 ps
1496 22:13:14.883202 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1497 22:13:14.889802 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1498 22:13:14.892715 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1499 22:13:14.896658 CA3 delay=34 (3~65),Diff = 1 PI (7 cell)
1500 22:13:14.899457 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1501 22:13:14.902917 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1502 22:13:14.903017
1503 22:13:14.906149 CA PerBit enable=1, Macro0, CA PI delay=33
1504 22:13:14.906263
1505 22:13:14.909341 [CBTSetCACLKResult] CA Dly = 33
1506 22:13:14.909426 CS Dly: 5 (0~37)
1507 22:13:14.913054
1508 22:13:14.916119 ----->DramcWriteLeveling(PI) begin...
1509 22:13:14.916205 ==
1510 22:13:14.919649 Dram Type= 6, Freq= 0, CH_1, rank 0
1511 22:13:14.922839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1512 22:13:14.922924 ==
1513 22:13:14.926313 Write leveling (Byte 0): 28 => 28
1514 22:13:14.929328 Write leveling (Byte 1): 30 => 30
1515 22:13:14.932892 DramcWriteLeveling(PI) end<-----
1516 22:13:14.932977
1517 22:13:14.933061 ==
1518 22:13:14.936104 Dram Type= 6, Freq= 0, CH_1, rank 0
1519 22:13:14.939270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1520 22:13:14.939355 ==
1521 22:13:14.942384 [Gating] SW mode calibration
1522 22:13:14.949243 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1523 22:13:14.955803 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1524 22:13:14.959096 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1525 22:13:14.962607 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1526 22:13:14.969317 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1527 22:13:14.972457 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 22:13:14.976391 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 22:13:14.979707 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 22:13:14.986246 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 22:13:14.989460 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 22:13:14.992528 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 22:13:14.999195 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 22:13:15.002972 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 22:13:15.005886 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 22:13:15.013001 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 22:13:15.016072 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 22:13:15.019342 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 22:13:15.026357 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 22:13:15.029184 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1541 22:13:15.032459 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1542 22:13:15.039213 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 22:13:15.042518 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1544 22:13:15.045703 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1545 22:13:15.052636 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1546 22:13:15.055706 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1547 22:13:15.059358 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1548 22:13:15.065623 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1549 22:13:15.069180 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1550 22:13:15.072235 0 9 8 | B1->B0 | 2b2b 3131 | 1 0 | (1 1) (0 0)
1551 22:13:15.079260 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1552 22:13:15.082240 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1553 22:13:15.085978 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1554 22:13:15.092587 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1555 22:13:15.095509 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1556 22:13:15.098689 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1557 22:13:15.105901 0 10 4 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
1558 22:13:15.108752 0 10 8 | B1->B0 | 2d2d 2525 | 0 0 | (0 0) (0 0)
1559 22:13:15.112231 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1560 22:13:15.119171 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1561 22:13:15.122305 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1562 22:13:15.125502 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1563 22:13:15.129191 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1564 22:13:15.135639 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1565 22:13:15.138618 0 11 4 | B1->B0 | 2929 2828 | 0 0 | (1 1) (0 0)
1566 22:13:15.142157 0 11 8 | B1->B0 | 3838 3c3c | 0 0 | (0 0) (1 1)
1567 22:13:15.148542 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1568 22:13:15.152028 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1569 22:13:15.155243 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1570 22:13:15.161678 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1571 22:13:15.165215 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1572 22:13:15.168537 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1573 22:13:15.175215 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1574 22:13:15.178229 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1575 22:13:15.181520 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 22:13:15.188213 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1577 22:13:15.191633 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1578 22:13:15.195150 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1579 22:13:15.201444 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1580 22:13:15.204807 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1581 22:13:15.208088 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1582 22:13:15.214998 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1583 22:13:15.218077 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1584 22:13:15.221454 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1585 22:13:15.228129 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1586 22:13:15.231236 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1587 22:13:15.234615 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1588 22:13:15.241477 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1589 22:13:15.244746 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1590 22:13:15.247850 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1591 22:13:15.251319 Total UI for P1: 0, mck2ui 16
1592 22:13:15.254631 best dqsien dly found for B0: ( 0, 14, 4)
1593 22:13:15.258566 Total UI for P1: 0, mck2ui 16
1594 22:13:15.261464 best dqsien dly found for B1: ( 0, 14, 6)
1595 22:13:15.264789 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1596 22:13:15.268378 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1597 22:13:15.268461
1598 22:13:15.274676 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1599 22:13:15.277951 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1600 22:13:15.278034 [Gating] SW calibration Done
1601 22:13:15.281328 ==
1602 22:13:15.281409 Dram Type= 6, Freq= 0, CH_1, rank 0
1603 22:13:15.287779 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1604 22:13:15.287862 ==
1605 22:13:15.287928 RX Vref Scan: 0
1606 22:13:15.287988
1607 22:13:15.290936 RX Vref 0 -> 0, step: 1
1608 22:13:15.291043
1609 22:13:15.294211 RX Delay -130 -> 252, step: 16
1610 22:13:15.297671 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1611 22:13:15.301284 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1612 22:13:15.304643 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1613 22:13:15.310955 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1614 22:13:15.314306 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1615 22:13:15.317214 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1616 22:13:15.320610 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1617 22:13:15.327298 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1618 22:13:15.330561 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1619 22:13:15.333919 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1620 22:13:15.337522 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1621 22:13:15.340395 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1622 22:13:15.347676 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1623 22:13:15.351127 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1624 22:13:15.353729 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1625 22:13:15.357836 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1626 22:13:15.357919 ==
1627 22:13:15.360393 Dram Type= 6, Freq= 0, CH_1, rank 0
1628 22:13:15.367004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1629 22:13:15.367126 ==
1630 22:13:15.367192 DQS Delay:
1631 22:13:15.370522 DQS0 = 0, DQS1 = 0
1632 22:13:15.370604 DQM Delay:
1633 22:13:15.370670 DQM0 = 89, DQM1 = 78
1634 22:13:15.374095 DQ Delay:
1635 22:13:15.377357 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =85
1636 22:13:15.380283 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1637 22:13:15.383948 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1638 22:13:15.387206 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1639 22:13:15.387304
1640 22:13:15.387369
1641 22:13:15.387429 ==
1642 22:13:15.390639 Dram Type= 6, Freq= 0, CH_1, rank 0
1643 22:13:15.393982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1644 22:13:15.394065 ==
1645 22:13:15.394132
1646 22:13:15.394192
1647 22:13:15.397082 TX Vref Scan disable
1648 22:13:15.397165 == TX Byte 0 ==
1649 22:13:15.404014 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1650 22:13:15.407188 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1651 22:13:15.407270 == TX Byte 1 ==
1652 22:13:15.413580 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1653 22:13:15.416912 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1654 22:13:15.416995 ==
1655 22:13:15.420879 Dram Type= 6, Freq= 0, CH_1, rank 0
1656 22:13:15.423695 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1657 22:13:15.423793 ==
1658 22:13:15.437643 TX Vref=22, minBit 10, minWin=26, winSum=442
1659 22:13:15.441103 TX Vref=24, minBit 9, minWin=27, winSum=450
1660 22:13:15.444361 TX Vref=26, minBit 8, minWin=27, winSum=447
1661 22:13:15.447702 TX Vref=28, minBit 9, minWin=27, winSum=451
1662 22:13:15.451425 TX Vref=30, minBit 8, minWin=27, winSum=448
1663 22:13:15.457365 TX Vref=32, minBit 8, minWin=27, winSum=448
1664 22:13:15.461073 [TxChooseVref] Worse bit 9, Min win 27, Win sum 451, Final Vref 28
1665 22:13:15.461155
1666 22:13:15.464345 Final TX Range 1 Vref 28
1667 22:13:15.464425
1668 22:13:15.464493 ==
1669 22:13:15.467526 Dram Type= 6, Freq= 0, CH_1, rank 0
1670 22:13:15.471035 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1671 22:13:15.471162 ==
1672 22:13:15.474060
1673 22:13:15.474131
1674 22:13:15.474192 TX Vref Scan disable
1675 22:13:15.477409 == TX Byte 0 ==
1676 22:13:15.480747 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1677 22:13:15.484169 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1678 22:13:15.488018 == TX Byte 1 ==
1679 22:13:15.490962 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1680 22:13:15.494252 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1681 22:13:15.497845
1682 22:13:15.497920 [DATLAT]
1683 22:13:15.497981 Freq=800, CH1 RK0
1684 22:13:15.498040
1685 22:13:15.500887 DATLAT Default: 0xa
1686 22:13:15.500954 0, 0xFFFF, sum = 0
1687 22:13:15.504411 1, 0xFFFF, sum = 0
1688 22:13:15.504480 2, 0xFFFF, sum = 0
1689 22:13:15.507262 3, 0xFFFF, sum = 0
1690 22:13:15.510645 4, 0xFFFF, sum = 0
1691 22:13:15.510721 5, 0xFFFF, sum = 0
1692 22:13:15.513927 6, 0xFFFF, sum = 0
1693 22:13:15.514001 7, 0xFFFF, sum = 0
1694 22:13:15.518126 8, 0xFFFF, sum = 0
1695 22:13:15.518195 9, 0x0, sum = 1
1696 22:13:15.520821 10, 0x0, sum = 2
1697 22:13:15.520890 11, 0x0, sum = 3
1698 22:13:15.520957 12, 0x0, sum = 4
1699 22:13:15.523849 best_step = 10
1700 22:13:15.523918
1701 22:13:15.523977 ==
1702 22:13:15.527470 Dram Type= 6, Freq= 0, CH_1, rank 0
1703 22:13:15.530379 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1704 22:13:15.530460 ==
1705 22:13:15.534343 RX Vref Scan: 1
1706 22:13:15.534419
1707 22:13:15.537490 Set Vref Range= 32 -> 127
1708 22:13:15.537558
1709 22:13:15.537617 RX Vref 32 -> 127, step: 1
1710 22:13:15.537674
1711 22:13:15.540543 RX Delay -95 -> 252, step: 8
1712 22:13:15.540609
1713 22:13:15.544012 Set Vref, RX VrefLevel [Byte0]: 32
1714 22:13:15.547509 [Byte1]: 32
1715 22:13:15.547579
1716 22:13:15.550464 Set Vref, RX VrefLevel [Byte0]: 33
1717 22:13:15.553881 [Byte1]: 33
1718 22:13:15.558339
1719 22:13:15.558410 Set Vref, RX VrefLevel [Byte0]: 34
1720 22:13:15.561361 [Byte1]: 34
1721 22:13:15.565619
1722 22:13:15.565693 Set Vref, RX VrefLevel [Byte0]: 35
1723 22:13:15.569211 [Byte1]: 35
1724 22:13:15.573663
1725 22:13:15.573736 Set Vref, RX VrefLevel [Byte0]: 36
1726 22:13:15.576715 [Byte1]: 36
1727 22:13:15.580832
1728 22:13:15.580908 Set Vref, RX VrefLevel [Byte0]: 37
1729 22:13:15.584308 [Byte1]: 37
1730 22:13:15.588276
1731 22:13:15.588344 Set Vref, RX VrefLevel [Byte0]: 38
1732 22:13:15.591450 [Byte1]: 38
1733 22:13:15.595831
1734 22:13:15.595899 Set Vref, RX VrefLevel [Byte0]: 39
1735 22:13:15.599454 [Byte1]: 39
1736 22:13:15.603468
1737 22:13:15.603536 Set Vref, RX VrefLevel [Byte0]: 40
1738 22:13:15.607146 [Byte1]: 40
1739 22:13:15.611145
1740 22:13:15.611215 Set Vref, RX VrefLevel [Byte0]: 41
1741 22:13:15.614294 [Byte1]: 41
1742 22:13:15.618586
1743 22:13:15.618653 Set Vref, RX VrefLevel [Byte0]: 42
1744 22:13:15.622141 [Byte1]: 42
1745 22:13:15.626912
1746 22:13:15.626981 Set Vref, RX VrefLevel [Byte0]: 43
1747 22:13:15.629618 [Byte1]: 43
1748 22:13:15.634087
1749 22:13:15.634171 Set Vref, RX VrefLevel [Byte0]: 44
1750 22:13:15.637291 [Byte1]: 44
1751 22:13:15.641897
1752 22:13:15.641965 Set Vref, RX VrefLevel [Byte0]: 45
1753 22:13:15.645336 [Byte1]: 45
1754 22:13:15.649502
1755 22:13:15.649572 Set Vref, RX VrefLevel [Byte0]: 46
1756 22:13:15.652339 [Byte1]: 46
1757 22:13:15.656854
1758 22:13:15.656931 Set Vref, RX VrefLevel [Byte0]: 47
1759 22:13:15.659819 [Byte1]: 47
1760 22:13:15.664896
1761 22:13:15.664979 Set Vref, RX VrefLevel [Byte0]: 48
1762 22:13:15.667953 [Byte1]: 48
1763 22:13:15.672035
1764 22:13:15.672114 Set Vref, RX VrefLevel [Byte0]: 49
1765 22:13:15.674980 [Byte1]: 49
1766 22:13:15.679395
1767 22:13:15.679476 Set Vref, RX VrefLevel [Byte0]: 50
1768 22:13:15.682827 [Byte1]: 50
1769 22:13:15.687353
1770 22:13:15.687434 Set Vref, RX VrefLevel [Byte0]: 51
1771 22:13:15.690511 [Byte1]: 51
1772 22:13:15.694565
1773 22:13:15.694673 Set Vref, RX VrefLevel [Byte0]: 52
1774 22:13:15.698222 [Byte1]: 52
1775 22:13:15.702052
1776 22:13:15.702162 Set Vref, RX VrefLevel [Byte0]: 53
1777 22:13:15.705685 [Byte1]: 53
1778 22:13:15.709725
1779 22:13:15.709794 Set Vref, RX VrefLevel [Byte0]: 54
1780 22:13:15.713415 [Byte1]: 54
1781 22:13:15.717178
1782 22:13:15.717249 Set Vref, RX VrefLevel [Byte0]: 55
1783 22:13:15.721267 [Byte1]: 55
1784 22:13:15.724950
1785 22:13:15.725019 Set Vref, RX VrefLevel [Byte0]: 56
1786 22:13:15.728510 [Byte1]: 56
1787 22:13:15.732803
1788 22:13:15.732879 Set Vref, RX VrefLevel [Byte0]: 57
1789 22:13:15.735797 [Byte1]: 57
1790 22:13:15.740466
1791 22:13:15.740537 Set Vref, RX VrefLevel [Byte0]: 58
1792 22:13:15.743583 [Byte1]: 58
1793 22:13:15.748144
1794 22:13:15.748220 Set Vref, RX VrefLevel [Byte0]: 59
1795 22:13:15.751460 [Byte1]: 59
1796 22:13:15.755211
1797 22:13:15.755283 Set Vref, RX VrefLevel [Byte0]: 60
1798 22:13:15.758491 [Byte1]: 60
1799 22:13:15.762868
1800 22:13:15.762970 Set Vref, RX VrefLevel [Byte0]: 61
1801 22:13:15.766160 [Byte1]: 61
1802 22:13:15.770601
1803 22:13:15.770706 Set Vref, RX VrefLevel [Byte0]: 62
1804 22:13:15.773967 [Byte1]: 62
1805 22:13:15.777945
1806 22:13:15.778030 Set Vref, RX VrefLevel [Byte0]: 63
1807 22:13:15.781838 [Byte1]: 63
1808 22:13:15.785972
1809 22:13:15.786055 Set Vref, RX VrefLevel [Byte0]: 64
1810 22:13:15.789017 [Byte1]: 64
1811 22:13:15.793373
1812 22:13:15.797202 Set Vref, RX VrefLevel [Byte0]: 65
1813 22:13:15.800118 [Byte1]: 65
1814 22:13:15.800214
1815 22:13:15.803026 Set Vref, RX VrefLevel [Byte0]: 66
1816 22:13:15.806982 [Byte1]: 66
1817 22:13:15.807124
1818 22:13:15.810058 Set Vref, RX VrefLevel [Byte0]: 67
1819 22:13:15.813090 [Byte1]: 67
1820 22:13:15.813188
1821 22:13:15.816499 Set Vref, RX VrefLevel [Byte0]: 68
1822 22:13:15.819954 [Byte1]: 68
1823 22:13:15.823887
1824 22:13:15.823972 Set Vref, RX VrefLevel [Byte0]: 69
1825 22:13:15.827606 [Byte1]: 69
1826 22:13:15.831865
1827 22:13:15.831947 Set Vref, RX VrefLevel [Byte0]: 70
1828 22:13:15.835005 [Byte1]: 70
1829 22:13:15.839510
1830 22:13:15.839583 Set Vref, RX VrefLevel [Byte0]: 71
1831 22:13:15.842413 [Byte1]: 71
1832 22:13:15.846745
1833 22:13:15.846820 Set Vref, RX VrefLevel [Byte0]: 72
1834 22:13:15.850459 [Byte1]: 72
1835 22:13:15.854426
1836 22:13:15.854531 Set Vref, RX VrefLevel [Byte0]: 73
1837 22:13:15.857460 [Byte1]: 73
1838 22:13:15.862011
1839 22:13:15.862117 Set Vref, RX VrefLevel [Byte0]: 74
1840 22:13:15.865043 [Byte1]: 74
1841 22:13:15.869557
1842 22:13:15.869661 Final RX Vref Byte 0 = 56 to rank0
1843 22:13:15.872734 Final RX Vref Byte 1 = 65 to rank0
1844 22:13:15.875995 Final RX Vref Byte 0 = 56 to rank1
1845 22:13:15.879167 Final RX Vref Byte 1 = 65 to rank1==
1846 22:13:15.882780 Dram Type= 6, Freq= 0, CH_1, rank 0
1847 22:13:15.889237 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1848 22:13:15.889322 ==
1849 22:13:15.889387 DQS Delay:
1850 22:13:15.892864 DQS0 = 0, DQS1 = 0
1851 22:13:15.892941 DQM Delay:
1852 22:13:15.893002 DQM0 = 87, DQM1 = 79
1853 22:13:15.895955 DQ Delay:
1854 22:13:15.899191 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1855 22:13:15.902503 DQ4 =84, DQ5 =100, DQ6 =100, DQ7 =80
1856 22:13:15.905623 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1857 22:13:15.909163 DQ12 =88, DQ13 =84, DQ14 =88, DQ15 =88
1858 22:13:15.909244
1859 22:13:15.909308
1860 22:13:15.915942 [DQSOSCAuto] RK0, (LSB)MR18= 0x3622, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 396 ps
1861 22:13:15.919373 CH1 RK0: MR19=606, MR18=3622
1862 22:13:15.925641 CH1_RK0: MR19=0x606, MR18=0x3622, DQSOSC=396, MR23=63, INC=94, DEC=62
1863 22:13:15.925727
1864 22:13:15.929129 ----->DramcWriteLeveling(PI) begin...
1865 22:13:15.929211 ==
1866 22:13:15.932376 Dram Type= 6, Freq= 0, CH_1, rank 1
1867 22:13:15.935797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1868 22:13:15.935902 ==
1869 22:13:15.939185 Write leveling (Byte 0): 25 => 25
1870 22:13:15.942173 Write leveling (Byte 1): 28 => 28
1871 22:13:15.945706 DramcWriteLeveling(PI) end<-----
1872 22:13:15.945786
1873 22:13:15.945850 ==
1874 22:13:15.948958 Dram Type= 6, Freq= 0, CH_1, rank 1
1875 22:13:15.952235 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1876 22:13:15.952316 ==
1877 22:13:15.955767 [Gating] SW mode calibration
1878 22:13:15.962083 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1879 22:13:15.968914 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1880 22:13:15.972441 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1881 22:13:15.979036 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1882 22:13:15.981979 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1883 22:13:15.985388 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 22:13:15.991999 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 22:13:15.995290 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 22:13:15.998535 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 22:13:16.005483 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 22:13:16.009291 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 22:13:16.012182 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 22:13:16.015461 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 22:13:16.021963 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 22:13:16.025342 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 22:13:16.028500 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 22:13:16.035006 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 22:13:16.038686 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 22:13:16.041689 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 22:13:16.048210 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 1)
1898 22:13:16.051645 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
1899 22:13:16.055270 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 22:13:16.061507 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1901 22:13:16.065090 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 22:13:16.068157 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1903 22:13:16.074868 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1904 22:13:16.078464 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1905 22:13:16.081569 0 9 4 | B1->B0 | 2322 2323 | 1 0 | (0 0) (0 0)
1906 22:13:16.088449 0 9 8 | B1->B0 | 3232 2828 | 0 1 | (0 0) (1 1)
1907 22:13:16.091270 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1908 22:13:16.094940 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1909 22:13:16.101956 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1910 22:13:16.104875 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1911 22:13:16.107995 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1912 22:13:16.114693 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
1913 22:13:16.118111 0 10 4 | B1->B0 | 3131 3434 | 1 0 | (0 0) (0 0)
1914 22:13:16.121619 0 10 8 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
1915 22:13:16.127798 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1916 22:13:16.131104 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1917 22:13:16.134615 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1918 22:13:16.141637 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1919 22:13:16.144487 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1920 22:13:16.148493 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1921 22:13:16.154366 0 11 4 | B1->B0 | 2d2d 2424 | 1 0 | (0 0) (0 0)
1922 22:13:16.158114 0 11 8 | B1->B0 | 3e3e 3636 | 0 1 | (0 0) (0 0)
1923 22:13:16.161178 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1924 22:13:16.167851 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1925 22:13:16.171039 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1926 22:13:16.174308 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1927 22:13:16.181043 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1928 22:13:16.184382 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1929 22:13:16.187686 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1930 22:13:16.194125 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1931 22:13:16.197293 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1932 22:13:16.200822 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1933 22:13:16.207166 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1934 22:13:16.210524 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1935 22:13:16.213918 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1936 22:13:16.220696 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1937 22:13:16.223694 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1938 22:13:16.227030 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1939 22:13:16.233920 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1940 22:13:16.236876 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1941 22:13:16.240520 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1942 22:13:16.246965 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1943 22:13:16.250657 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1944 22:13:16.253783 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1945 22:13:16.257198 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1946 22:13:16.264143 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1947 22:13:16.266936 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1948 22:13:16.270197 Total UI for P1: 0, mck2ui 16
1949 22:13:16.273356 best dqsien dly found for B0: ( 0, 14, 6)
1950 22:13:16.277154 Total UI for P1: 0, mck2ui 16
1951 22:13:16.280767 best dqsien dly found for B1: ( 0, 14, 6)
1952 22:13:16.283436 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1953 22:13:16.286910 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1954 22:13:16.286991
1955 22:13:16.290269 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1956 22:13:16.293516 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1957 22:13:16.296765 [Gating] SW calibration Done
1958 22:13:16.296845 ==
1959 22:13:16.300264 Dram Type= 6, Freq= 0, CH_1, rank 1
1960 22:13:16.306685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1961 22:13:16.306766 ==
1962 22:13:16.306831 RX Vref Scan: 0
1963 22:13:16.306890
1964 22:13:16.309993 RX Vref 0 -> 0, step: 1
1965 22:13:16.310074
1966 22:13:16.313353 RX Delay -130 -> 252, step: 16
1967 22:13:16.316702 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1968 22:13:16.320346 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1969 22:13:16.323614 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1970 22:13:16.326761 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1971 22:13:16.333271 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1972 22:13:16.336690 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1973 22:13:16.340343 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1974 22:13:16.343668 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1975 22:13:16.346779 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1976 22:13:16.353499 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1977 22:13:16.356843 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1978 22:13:16.360099 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1979 22:13:16.362906 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1980 22:13:16.369631 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1981 22:13:16.373440 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1982 22:13:16.376318 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1983 22:13:16.376399 ==
1984 22:13:16.379388 Dram Type= 6, Freq= 0, CH_1, rank 1
1985 22:13:16.383332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1986 22:13:16.383413 ==
1987 22:13:16.386231 DQS Delay:
1988 22:13:16.386304 DQS0 = 0, DQS1 = 0
1989 22:13:16.389888 DQM Delay:
1990 22:13:16.389982 DQM0 = 87, DQM1 = 78
1991 22:13:16.390075 DQ Delay:
1992 22:13:16.392808 DQ0 =85, DQ1 =77, DQ2 =77, DQ3 =85
1993 22:13:16.396041 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1994 22:13:16.399477 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1995 22:13:16.402758 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1996 22:13:16.402827
1997 22:13:16.406413
1998 22:13:16.406493 ==
1999 22:13:16.409693 Dram Type= 6, Freq= 0, CH_1, rank 1
2000 22:13:16.412779 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2001 22:13:16.412892 ==
2002 22:13:16.412956
2003 22:13:16.413015
2004 22:13:16.416370 TX Vref Scan disable
2005 22:13:16.416450 == TX Byte 0 ==
2006 22:13:16.422916 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
2007 22:13:16.426285 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
2008 22:13:16.426359 == TX Byte 1 ==
2009 22:13:16.432864 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2010 22:13:16.436464 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2011 22:13:16.436546 ==
2012 22:13:16.439262 Dram Type= 6, Freq= 0, CH_1, rank 1
2013 22:13:16.442733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2014 22:13:16.442814 ==
2015 22:13:16.455914 TX Vref=22, minBit 9, minWin=26, winSum=438
2016 22:13:16.460350 TX Vref=24, minBit 9, minWin=27, winSum=445
2017 22:13:16.463208 TX Vref=26, minBit 3, minWin=27, winSum=445
2018 22:13:16.465896 TX Vref=28, minBit 8, minWin=27, winSum=449
2019 22:13:16.469414 TX Vref=30, minBit 8, minWin=27, winSum=448
2020 22:13:16.476049 TX Vref=32, minBit 8, minWin=27, winSum=446
2021 22:13:16.479550 [TxChooseVref] Worse bit 8, Min win 27, Win sum 449, Final Vref 28
2022 22:13:16.479635
2023 22:13:16.482431 Final TX Range 1 Vref 28
2024 22:13:16.482512
2025 22:13:16.482576 ==
2026 22:13:16.485887 Dram Type= 6, Freq= 0, CH_1, rank 1
2027 22:13:16.492524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2028 22:13:16.492605 ==
2029 22:13:16.492670
2030 22:13:16.492728
2031 22:13:16.492785 TX Vref Scan disable
2032 22:13:16.496819 == TX Byte 0 ==
2033 22:13:16.499332 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
2034 22:13:16.505976 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
2035 22:13:16.506057 == TX Byte 1 ==
2036 22:13:16.510002 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
2037 22:13:16.516442 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
2038 22:13:16.516578
2039 22:13:16.516685 [DATLAT]
2040 22:13:16.516772 Freq=800, CH1 RK1
2041 22:13:16.516857
2042 22:13:16.519300 DATLAT Default: 0xa
2043 22:13:16.519380 0, 0xFFFF, sum = 0
2044 22:13:16.522848 1, 0xFFFF, sum = 0
2045 22:13:16.526004 2, 0xFFFF, sum = 0
2046 22:13:16.526125 3, 0xFFFF, sum = 0
2047 22:13:16.529508 4, 0xFFFF, sum = 0
2048 22:13:16.529590 5, 0xFFFF, sum = 0
2049 22:13:16.532899 6, 0xFFFF, sum = 0
2050 22:13:16.532980 7, 0xFFFF, sum = 0
2051 22:13:16.536160 8, 0xFFFF, sum = 0
2052 22:13:16.536242 9, 0x0, sum = 1
2053 22:13:16.539327 10, 0x0, sum = 2
2054 22:13:16.539409 11, 0x0, sum = 3
2055 22:13:16.539474 12, 0x0, sum = 4
2056 22:13:16.542768 best_step = 10
2057 22:13:16.542849
2058 22:13:16.542912 ==
2059 22:13:16.546265 Dram Type= 6, Freq= 0, CH_1, rank 1
2060 22:13:16.549438 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2061 22:13:16.549519 ==
2062 22:13:16.552570 RX Vref Scan: 0
2063 22:13:16.552664
2064 22:13:16.552728 RX Vref 0 -> 0, step: 1
2065 22:13:16.555883
2066 22:13:16.555970 RX Delay -95 -> 252, step: 8
2067 22:13:16.562983 iDelay=217, Bit 0, Center 92 (-23 ~ 208) 232
2068 22:13:16.566280 iDelay=217, Bit 1, Center 80 (-31 ~ 192) 224
2069 22:13:16.569317 iDelay=217, Bit 2, Center 80 (-31 ~ 192) 224
2070 22:13:16.572909 iDelay=217, Bit 3, Center 84 (-23 ~ 192) 216
2071 22:13:16.576371 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
2072 22:13:16.582834 iDelay=217, Bit 5, Center 96 (-15 ~ 208) 224
2073 22:13:16.585961 iDelay=217, Bit 6, Center 100 (-15 ~ 216) 232
2074 22:13:16.589324 iDelay=217, Bit 7, Center 84 (-31 ~ 200) 232
2075 22:13:16.592754 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
2076 22:13:16.596150 iDelay=217, Bit 9, Center 68 (-47 ~ 184) 232
2077 22:13:16.603064 iDelay=217, Bit 10, Center 80 (-39 ~ 200) 240
2078 22:13:16.606088 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
2079 22:13:16.609232 iDelay=217, Bit 12, Center 88 (-23 ~ 200) 224
2080 22:13:16.612397 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
2081 22:13:16.619025 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
2082 22:13:16.622363 iDelay=217, Bit 15, Center 88 (-31 ~ 208) 240
2083 22:13:16.622445 ==
2084 22:13:16.625922 Dram Type= 6, Freq= 0, CH_1, rank 1
2085 22:13:16.629241 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2086 22:13:16.629337 ==
2087 22:13:16.632431 DQS Delay:
2088 22:13:16.632513 DQS0 = 0, DQS1 = 0
2089 22:13:16.632578 DQM Delay:
2090 22:13:16.635499 DQM0 = 87, DQM1 = 78
2091 22:13:16.635580 DQ Delay:
2092 22:13:16.638917 DQ0 =92, DQ1 =80, DQ2 =80, DQ3 =84
2093 22:13:16.642021 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =84
2094 22:13:16.645366 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
2095 22:13:16.648936 DQ12 =88, DQ13 =84, DQ14 =84, DQ15 =88
2096 22:13:16.649018
2097 22:13:16.649083
2098 22:13:16.659302 [DQSOSCAuto] RK1, (LSB)MR18= 0x1a12, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 403 ps
2099 22:13:16.662262 CH1 RK1: MR19=606, MR18=1A12
2100 22:13:16.665290 CH1_RK1: MR19=0x606, MR18=0x1A12, DQSOSC=403, MR23=63, INC=90, DEC=60
2101 22:13:16.668969 [RxdqsGatingPostProcess] freq 800
2102 22:13:16.675548 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2103 22:13:16.678802 Pre-setting of DQS Precalculation
2104 22:13:16.682092 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2105 22:13:16.691907 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2106 22:13:16.698462 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2107 22:13:16.698544
2108 22:13:16.698609
2109 22:13:16.702301 [Calibration Summary] 1600 Mbps
2110 22:13:16.702383 CH 0, Rank 0
2111 22:13:16.705159 SW Impedance : PASS
2112 22:13:16.705241 DUTY Scan : NO K
2113 22:13:16.708717 ZQ Calibration : PASS
2114 22:13:16.711948 Jitter Meter : NO K
2115 22:13:16.712029 CBT Training : PASS
2116 22:13:16.715381 Write leveling : PASS
2117 22:13:16.718612 RX DQS gating : PASS
2118 22:13:16.718693 RX DQ/DQS(RDDQC) : PASS
2119 22:13:16.721630 TX DQ/DQS : PASS
2120 22:13:16.724783 RX DATLAT : PASS
2121 22:13:16.724864 RX DQ/DQS(Engine): PASS
2122 22:13:16.728293 TX OE : NO K
2123 22:13:16.728375 All Pass.
2124 22:13:16.728440
2125 22:13:16.731476 CH 0, Rank 1
2126 22:13:16.731557 SW Impedance : PASS
2127 22:13:16.735430 DUTY Scan : NO K
2128 22:13:16.738178 ZQ Calibration : PASS
2129 22:13:16.738260 Jitter Meter : NO K
2130 22:13:16.741416 CBT Training : PASS
2131 22:13:16.741498 Write leveling : PASS
2132 22:13:16.744871 RX DQS gating : PASS
2133 22:13:16.748020 RX DQ/DQS(RDDQC) : PASS
2134 22:13:16.748102 TX DQ/DQS : PASS
2135 22:13:16.752003 RX DATLAT : PASS
2136 22:13:16.754524 RX DQ/DQS(Engine): PASS
2137 22:13:16.754607 TX OE : NO K
2138 22:13:16.758520 All Pass.
2139 22:13:16.758609
2140 22:13:16.758674 CH 1, Rank 0
2141 22:13:16.761238 SW Impedance : PASS
2142 22:13:16.761320 DUTY Scan : NO K
2143 22:13:16.765026 ZQ Calibration : PASS
2144 22:13:16.767926 Jitter Meter : NO K
2145 22:13:16.768008 CBT Training : PASS
2146 22:13:16.771309 Write leveling : PASS
2147 22:13:16.774601 RX DQS gating : PASS
2148 22:13:16.774682 RX DQ/DQS(RDDQC) : PASS
2149 22:13:16.778124 TX DQ/DQS : PASS
2150 22:13:16.781557 RX DATLAT : PASS
2151 22:13:16.781639 RX DQ/DQS(Engine): PASS
2152 22:13:16.784562 TX OE : NO K
2153 22:13:16.784643 All Pass.
2154 22:13:16.784708
2155 22:13:16.788045 CH 1, Rank 1
2156 22:13:16.788190 SW Impedance : PASS
2157 22:13:16.790954 DUTY Scan : NO K
2158 22:13:16.794597 ZQ Calibration : PASS
2159 22:13:16.794679 Jitter Meter : NO K
2160 22:13:16.797712 CBT Training : PASS
2161 22:13:16.797793 Write leveling : PASS
2162 22:13:16.801131 RX DQS gating : PASS
2163 22:13:16.804348 RX DQ/DQS(RDDQC) : PASS
2164 22:13:16.804429 TX DQ/DQS : PASS
2165 22:13:16.807924 RX DATLAT : PASS
2166 22:13:16.811481 RX DQ/DQS(Engine): PASS
2167 22:13:16.811562 TX OE : NO K
2168 22:13:16.814399 All Pass.
2169 22:13:16.814481
2170 22:13:16.814545 DramC Write-DBI off
2171 22:13:16.817952 PER_BANK_REFRESH: Hybrid Mode
2172 22:13:16.818033 TX_TRACKING: ON
2173 22:13:16.824722 [GetDramInforAfterCalByMRR] Vendor 6.
2174 22:13:16.827930 [GetDramInforAfterCalByMRR] Revision 606.
2175 22:13:16.831479 [GetDramInforAfterCalByMRR] Revision 2 0.
2176 22:13:16.831561 MR0 0x3b3b
2177 22:13:16.831626 MR8 0x5151
2178 22:13:16.834502 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2179 22:13:16.837855
2180 22:13:16.837936 MR0 0x3b3b
2181 22:13:16.838001 MR8 0x5151
2182 22:13:16.841227 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2183 22:13:16.841309
2184 22:13:16.851419 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2185 22:13:16.854526 [FAST_K] Save calibration result to emmc
2186 22:13:16.857737 [FAST_K] Save calibration result to emmc
2187 22:13:16.860774 dram_init: config_dvfs: 1
2188 22:13:16.864219 dramc_set_vcore_voltage set vcore to 662500
2189 22:13:16.867919 Read voltage for 1200, 2
2190 22:13:16.868068 Vio18 = 0
2191 22:13:16.868175 Vcore = 662500
2192 22:13:16.870639 Vdram = 0
2193 22:13:16.870721 Vddq = 0
2194 22:13:16.870786 Vmddr = 0
2195 22:13:16.878068 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2196 22:13:16.881413 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2197 22:13:16.884267 MEM_TYPE=3, freq_sel=15
2198 22:13:16.887325 sv_algorithm_assistance_LP4_1600
2199 22:13:16.890990 ============ PULL DRAM RESETB DOWN ============
2200 22:13:16.894110 ========== PULL DRAM RESETB DOWN end =========
2201 22:13:16.900494 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2202 22:13:16.904113 ===================================
2203 22:13:16.907455 LPDDR4 DRAM CONFIGURATION
2204 22:13:16.911013 ===================================
2205 22:13:16.911146 EX_ROW_EN[0] = 0x0
2206 22:13:16.913942 EX_ROW_EN[1] = 0x0
2207 22:13:16.914041 LP4Y_EN = 0x0
2208 22:13:16.917217 WORK_FSP = 0x0
2209 22:13:16.917315 WL = 0x4
2210 22:13:16.920764 RL = 0x4
2211 22:13:16.920861 BL = 0x2
2212 22:13:16.924123 RPST = 0x0
2213 22:13:16.924222 RD_PRE = 0x0
2214 22:13:16.927116 WR_PRE = 0x1
2215 22:13:16.927197 WR_PST = 0x0
2216 22:13:16.930669 DBI_WR = 0x0
2217 22:13:16.930767 DBI_RD = 0x0
2218 22:13:16.934072 OTF = 0x1
2219 22:13:16.937347 ===================================
2220 22:13:16.940785 ===================================
2221 22:13:16.940868 ANA top config
2222 22:13:16.943848 ===================================
2223 22:13:16.946864 DLL_ASYNC_EN = 0
2224 22:13:16.950421 ALL_SLAVE_EN = 0
2225 22:13:16.953616 NEW_RANK_MODE = 1
2226 22:13:16.953693 DLL_IDLE_MODE = 1
2227 22:13:16.957276 LP45_APHY_COMB_EN = 1
2228 22:13:16.960506 TX_ODT_DIS = 1
2229 22:13:16.963851 NEW_8X_MODE = 1
2230 22:13:16.967076 ===================================
2231 22:13:16.970485 ===================================
2232 22:13:16.973370 data_rate = 2400
2233 22:13:16.976776 CKR = 1
2234 22:13:16.976860 DQ_P2S_RATIO = 8
2235 22:13:16.980115 ===================================
2236 22:13:16.983530 CA_P2S_RATIO = 8
2237 22:13:16.986695 DQ_CA_OPEN = 0
2238 22:13:16.990067 DQ_SEMI_OPEN = 0
2239 22:13:16.993141 CA_SEMI_OPEN = 0
2240 22:13:16.996578 CA_FULL_RATE = 0
2241 22:13:16.996662 DQ_CKDIV4_EN = 0
2242 22:13:17.000176 CA_CKDIV4_EN = 0
2243 22:13:17.003295 CA_PREDIV_EN = 0
2244 22:13:17.006543 PH8_DLY = 17
2245 22:13:17.010364 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2246 22:13:17.013403 DQ_AAMCK_DIV = 4
2247 22:13:17.013486 CA_AAMCK_DIV = 4
2248 22:13:17.016868 CA_ADMCK_DIV = 4
2249 22:13:17.020045 DQ_TRACK_CA_EN = 0
2250 22:13:17.023257 CA_PICK = 1200
2251 22:13:17.026818 CA_MCKIO = 1200
2252 22:13:17.029792 MCKIO_SEMI = 0
2253 22:13:17.033338 PLL_FREQ = 2366
2254 22:13:17.033421 DQ_UI_PI_RATIO = 32
2255 22:13:17.036414 CA_UI_PI_RATIO = 0
2256 22:13:17.040130 ===================================
2257 22:13:17.043391 ===================================
2258 22:13:17.046449 memory_type:LPDDR4
2259 22:13:17.050197 GP_NUM : 10
2260 22:13:17.050279 SRAM_EN : 1
2261 22:13:17.053777 MD32_EN : 0
2262 22:13:17.056440 ===================================
2263 22:13:17.059765 [ANA_INIT] >>>>>>>>>>>>>>
2264 22:13:17.059848 <<<<<< [CONFIGURE PHASE]: ANA_TX
2265 22:13:17.063001 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2266 22:13:17.066130 ===================================
2267 22:13:17.069476 data_rate = 2400,PCW = 0X5b00
2268 22:13:17.073036 ===================================
2269 22:13:17.076197 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2270 22:13:17.082986 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2271 22:13:17.089927 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2272 22:13:17.092685 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2273 22:13:17.096299 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2274 22:13:17.099822 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2275 22:13:17.103019 [ANA_INIT] flow start
2276 22:13:17.103156 [ANA_INIT] PLL >>>>>>>>
2277 22:13:17.106130 [ANA_INIT] PLL <<<<<<<<
2278 22:13:17.109485 [ANA_INIT] MIDPI >>>>>>>>
2279 22:13:17.112572 [ANA_INIT] MIDPI <<<<<<<<
2280 22:13:17.112672 [ANA_INIT] DLL >>>>>>>>
2281 22:13:17.116040 [ANA_INIT] DLL <<<<<<<<
2282 22:13:17.116113 [ANA_INIT] flow end
2283 22:13:17.122584 ============ LP4 DIFF to SE enter ============
2284 22:13:17.125918 ============ LP4 DIFF to SE exit ============
2285 22:13:17.129042 [ANA_INIT] <<<<<<<<<<<<<
2286 22:13:17.132265 [Flow] Enable top DCM control >>>>>
2287 22:13:17.135906 [Flow] Enable top DCM control <<<<<
2288 22:13:17.139356 Enable DLL master slave shuffle
2289 22:13:17.142504 ==============================================================
2290 22:13:17.146097 Gating Mode config
2291 22:13:17.149413 ==============================================================
2292 22:13:17.152236 Config description:
2293 22:13:17.162308 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2294 22:13:17.169254 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2295 22:13:17.172395 SELPH_MODE 0: By rank 1: By Phase
2296 22:13:17.179018 ==============================================================
2297 22:13:17.182543 GAT_TRACK_EN = 1
2298 22:13:17.185418 RX_GATING_MODE = 2
2299 22:13:17.189111 RX_GATING_TRACK_MODE = 2
2300 22:13:17.192245 SELPH_MODE = 1
2301 22:13:17.195783 PICG_EARLY_EN = 1
2302 22:13:17.195855 VALID_LAT_VALUE = 1
2303 22:13:17.202024 ==============================================================
2304 22:13:17.205701 Enter into Gating configuration >>>>
2305 22:13:17.208853 Exit from Gating configuration <<<<
2306 22:13:17.212045 Enter into DVFS_PRE_config >>>>>
2307 22:13:17.222623 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2308 22:13:17.225504 Exit from DVFS_PRE_config <<<<<
2309 22:13:17.228732 Enter into PICG configuration >>>>
2310 22:13:17.232040 Exit from PICG configuration <<<<
2311 22:13:17.235996 [RX_INPUT] configuration >>>>>
2312 22:13:17.238509 [RX_INPUT] configuration <<<<<
2313 22:13:17.245336 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2314 22:13:17.248976 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2315 22:13:17.255449 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2316 22:13:17.262212 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2317 22:13:17.268763 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2318 22:13:17.275437 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2319 22:13:17.278586 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2320 22:13:17.282159 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2321 22:13:17.285778 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2322 22:13:17.288583 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2323 22:13:17.295146 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2324 22:13:17.299264 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2325 22:13:17.302441 ===================================
2326 22:13:17.305246 LPDDR4 DRAM CONFIGURATION
2327 22:13:17.308815 ===================================
2328 22:13:17.308885 EX_ROW_EN[0] = 0x0
2329 22:13:17.311697 EX_ROW_EN[1] = 0x0
2330 22:13:17.311763 LP4Y_EN = 0x0
2331 22:13:17.315371 WORK_FSP = 0x0
2332 22:13:17.315443 WL = 0x4
2333 22:13:17.318668 RL = 0x4
2334 22:13:17.318780 BL = 0x2
2335 22:13:17.321868 RPST = 0x0
2336 22:13:17.325647 RD_PRE = 0x0
2337 22:13:17.325716 WR_PRE = 0x1
2338 22:13:17.328288 WR_PST = 0x0
2339 22:13:17.328356 DBI_WR = 0x0
2340 22:13:17.332185 DBI_RD = 0x0
2341 22:13:17.332251 OTF = 0x1
2342 22:13:17.334914 ===================================
2343 22:13:17.338366 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2344 22:13:17.341869 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2345 22:13:17.348429 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2346 22:13:17.351451 ===================================
2347 22:13:17.355467 LPDDR4 DRAM CONFIGURATION
2348 22:13:17.358151 ===================================
2349 22:13:17.358246 EX_ROW_EN[0] = 0x10
2350 22:13:17.361868 EX_ROW_EN[1] = 0x0
2351 22:13:17.361960 LP4Y_EN = 0x0
2352 22:13:17.365033 WORK_FSP = 0x0
2353 22:13:17.365127 WL = 0x4
2354 22:13:17.368743 RL = 0x4
2355 22:13:17.368846 BL = 0x2
2356 22:13:17.371848 RPST = 0x0
2357 22:13:17.371919 RD_PRE = 0x0
2358 22:13:17.375285 WR_PRE = 0x1
2359 22:13:17.378440 WR_PST = 0x0
2360 22:13:17.378512 DBI_WR = 0x0
2361 22:13:17.381318 DBI_RD = 0x0
2362 22:13:17.381392 OTF = 0x1
2363 22:13:17.385080 ===================================
2364 22:13:17.391909 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2365 22:13:17.392012 ==
2366 22:13:17.394800 Dram Type= 6, Freq= 0, CH_0, rank 0
2367 22:13:17.397924 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2368 22:13:17.397996 ==
2369 22:13:17.401686 [Duty_Offset_Calibration]
2370 22:13:17.404602 B0:1 B1:-1 CA:0
2371 22:13:17.404671
2372 22:13:17.407907 [DutyScan_Calibration_Flow] k_type=0
2373 22:13:17.415700
2374 22:13:17.415771 ==CLK 0==
2375 22:13:17.418933 Final CLK duty delay cell = 0
2376 22:13:17.422368 [0] MAX Duty = 5125%(X100), DQS PI = 24
2377 22:13:17.425642 [0] MIN Duty = 4907%(X100), DQS PI = 10
2378 22:13:17.428854 [0] AVG Duty = 5016%(X100)
2379 22:13:17.428947
2380 22:13:17.432181 CH0 CLK Duty spec in!! Max-Min= 218%
2381 22:13:17.435531 [DutyScan_Calibration_Flow] ====Done====
2382 22:13:17.435600
2383 22:13:17.438876 [DutyScan_Calibration_Flow] k_type=1
2384 22:13:17.453392
2385 22:13:17.453467 ==DQS 0 ==
2386 22:13:17.457299 Final DQS duty delay cell = -4
2387 22:13:17.460127 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2388 22:13:17.463451 [-4] MIN Duty = 4875%(X100), DQS PI = 56
2389 22:13:17.466845 [-4] AVG Duty = 4968%(X100)
2390 22:13:17.466944
2391 22:13:17.467033 ==DQS 1 ==
2392 22:13:17.469894 Final DQS duty delay cell = -4
2393 22:13:17.473385 [-4] MAX Duty = 5000%(X100), DQS PI = 6
2394 22:13:17.476648 [-4] MIN Duty = 4876%(X100), DQS PI = 22
2395 22:13:17.479781 [-4] AVG Duty = 4938%(X100)
2396 22:13:17.479864
2397 22:13:17.483245 CH0 DQS 0 Duty spec in!! Max-Min= 187%
2398 22:13:17.483317
2399 22:13:17.486897 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2400 22:13:17.490113 [DutyScan_Calibration_Flow] ====Done====
2401 22:13:17.490207
2402 22:13:17.493240 [DutyScan_Calibration_Flow] k_type=3
2403 22:13:17.511340
2404 22:13:17.511420 ==DQM 0 ==
2405 22:13:17.514953 Final DQM duty delay cell = 0
2406 22:13:17.518212 [0] MAX Duty = 5062%(X100), DQS PI = 24
2407 22:13:17.521494 [0] MIN Duty = 4875%(X100), DQS PI = 8
2408 22:13:17.521565 [0] AVG Duty = 4968%(X100)
2409 22:13:17.524931
2410 22:13:17.525000 ==DQM 1 ==
2411 22:13:17.527842 Final DQM duty delay cell = 4
2412 22:13:17.531448 [4] MAX Duty = 5187%(X100), DQS PI = 14
2413 22:13:17.534958 [4] MIN Duty = 5000%(X100), DQS PI = 24
2414 22:13:17.537939 [4] AVG Duty = 5093%(X100)
2415 22:13:17.538066
2416 22:13:17.541330 CH0 DQM 0 Duty spec in!! Max-Min= 187%
2417 22:13:17.541424
2418 22:13:17.544748 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2419 22:13:17.548045 [DutyScan_Calibration_Flow] ====Done====
2420 22:13:17.548118
2421 22:13:17.551194 [DutyScan_Calibration_Flow] k_type=2
2422 22:13:17.566414
2423 22:13:17.566493 ==DQ 0 ==
2424 22:13:17.569976 Final DQ duty delay cell = -4
2425 22:13:17.573296 [-4] MAX Duty = 5031%(X100), DQS PI = 24
2426 22:13:17.576321 [-4] MIN Duty = 4907%(X100), DQS PI = 48
2427 22:13:17.579565 [-4] AVG Duty = 4969%(X100)
2428 22:13:17.579636
2429 22:13:17.579698 ==DQ 1 ==
2430 22:13:17.583339 Final DQ duty delay cell = -4
2431 22:13:17.586295 [-4] MAX Duty = 5000%(X100), DQS PI = 56
2432 22:13:17.589724 [-4] MIN Duty = 4876%(X100), DQS PI = 40
2433 22:13:17.592994 [-4] AVG Duty = 4938%(X100)
2434 22:13:17.593100
2435 22:13:17.596116 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2436 22:13:17.596190
2437 22:13:17.599426 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2438 22:13:17.603019 [DutyScan_Calibration_Flow] ====Done====
2439 22:13:17.603142 ==
2440 22:13:17.606276 Dram Type= 6, Freq= 0, CH_1, rank 0
2441 22:13:17.609450 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2442 22:13:17.609526 ==
2443 22:13:17.613053 [Duty_Offset_Calibration]
2444 22:13:17.613129 B0:-1 B1:1 CA:2
2445 22:13:17.616332
2446 22:13:17.619583 [DutyScan_Calibration_Flow] k_type=0
2447 22:13:17.627160
2448 22:13:17.627236 ==CLK 0==
2449 22:13:17.630362 Final CLK duty delay cell = 0
2450 22:13:17.634025 [0] MAX Duty = 5156%(X100), DQS PI = 20
2451 22:13:17.636979 [0] MIN Duty = 4969%(X100), DQS PI = 60
2452 22:13:17.637078 [0] AVG Duty = 5062%(X100)
2453 22:13:17.640346
2454 22:13:17.643938 CH1 CLK Duty spec in!! Max-Min= 187%
2455 22:13:17.646938 [DutyScan_Calibration_Flow] ====Done====
2456 22:13:17.647038
2457 22:13:17.650517 [DutyScan_Calibration_Flow] k_type=1
2458 22:13:17.666615
2459 22:13:17.666697 ==DQS 0 ==
2460 22:13:17.669505 Final DQS duty delay cell = 0
2461 22:13:17.673171 [0] MAX Duty = 5156%(X100), DQS PI = 48
2462 22:13:17.676525 [0] MIN Duty = 4907%(X100), DQS PI = 8
2463 22:13:17.679682 [0] AVG Duty = 5031%(X100)
2464 22:13:17.679788
2465 22:13:17.679887 ==DQS 1 ==
2466 22:13:17.683178 Final DQS duty delay cell = 0
2467 22:13:17.686030 [0] MAX Duty = 5094%(X100), DQS PI = 12
2468 22:13:17.689638 [0] MIN Duty = 4969%(X100), DQS PI = 56
2469 22:13:17.692644 [0] AVG Duty = 5031%(X100)
2470 22:13:17.692746
2471 22:13:17.696163 CH1 DQS 0 Duty spec in!! Max-Min= 249%
2472 22:13:17.696264
2473 22:13:17.699234 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2474 22:13:17.702498 [DutyScan_Calibration_Flow] ====Done====
2475 22:13:17.702608
2476 22:13:17.706047 [DutyScan_Calibration_Flow] k_type=3
2477 22:13:17.722495
2478 22:13:17.722603 ==DQM 0 ==
2479 22:13:17.725744 Final DQM duty delay cell = -4
2480 22:13:17.728979 [-4] MAX Duty = 5062%(X100), DQS PI = 32
2481 22:13:17.732536 [-4] MIN Duty = 4876%(X100), DQS PI = 6
2482 22:13:17.735819 [-4] AVG Duty = 4969%(X100)
2483 22:13:17.735894
2484 22:13:17.735956 ==DQM 1 ==
2485 22:13:17.738594 Final DQM duty delay cell = 0
2486 22:13:17.742328 [0] MAX Duty = 5187%(X100), DQS PI = 8
2487 22:13:17.745239 [0] MIN Duty = 5000%(X100), DQS PI = 28
2488 22:13:17.748245 [0] AVG Duty = 5093%(X100)
2489 22:13:17.748348
2490 22:13:17.751601 CH1 DQM 0 Duty spec in!! Max-Min= 186%
2491 22:13:17.751676
2492 22:13:17.755460 CH1 DQM 1 Duty spec in!! Max-Min= 187%
2493 22:13:17.758214 [DutyScan_Calibration_Flow] ====Done====
2494 22:13:17.758324
2495 22:13:17.761667 [DutyScan_Calibration_Flow] k_type=2
2496 22:13:17.778757
2497 22:13:17.778876 ==DQ 0 ==
2498 22:13:17.782229 Final DQ duty delay cell = 0
2499 22:13:17.785368 [0] MAX Duty = 5187%(X100), DQS PI = 28
2500 22:13:17.788594 [0] MIN Duty = 4907%(X100), DQS PI = 8
2501 22:13:17.792162 [0] AVG Duty = 5047%(X100)
2502 22:13:17.792236
2503 22:13:17.792301 ==DQ 1 ==
2504 22:13:17.795478 Final DQ duty delay cell = 0
2505 22:13:17.798476 [0] MAX Duty = 5124%(X100), DQS PI = 10
2506 22:13:17.802260 [0] MIN Duty = 4969%(X100), DQS PI = 58
2507 22:13:17.802331 [0] AVG Duty = 5046%(X100)
2508 22:13:17.805437
2509 22:13:17.808750 CH1 DQ 0 Duty spec in!! Max-Min= 280%
2510 22:13:17.808840
2511 22:13:17.811961 CH1 DQ 1 Duty spec in!! Max-Min= 155%
2512 22:13:17.815051 [DutyScan_Calibration_Flow] ====Done====
2513 22:13:17.818932 nWR fixed to 30
2514 22:13:17.819037 [ModeRegInit_LP4] CH0 RK0
2515 22:13:17.822209 [ModeRegInit_LP4] CH0 RK1
2516 22:13:17.825040 [ModeRegInit_LP4] CH1 RK0
2517 22:13:17.828296 [ModeRegInit_LP4] CH1 RK1
2518 22:13:17.828368 match AC timing 7
2519 22:13:17.832064 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2520 22:13:17.838313 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2521 22:13:17.841836 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2522 22:13:17.848652 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2523 22:13:17.851516 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2524 22:13:17.851604 ==
2525 22:13:17.855012 Dram Type= 6, Freq= 0, CH_0, rank 0
2526 22:13:17.858910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2527 22:13:17.859032 ==
2528 22:13:17.865008 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2529 22:13:17.871374 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2530 22:13:17.878657 [CA 0] Center 39 (9~70) winsize 62
2531 22:13:17.882170 [CA 1] Center 39 (9~69) winsize 61
2532 22:13:17.885312 [CA 2] Center 35 (5~66) winsize 62
2533 22:13:17.889201 [CA 3] Center 35 (4~66) winsize 63
2534 22:13:17.892456 [CA 4] Center 33 (4~63) winsize 60
2535 22:13:17.895652 [CA 5] Center 33 (3~63) winsize 61
2536 22:13:17.895740
2537 22:13:17.899047 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2538 22:13:17.899155
2539 22:13:17.902008 [CATrainingPosCal] consider 1 rank data
2540 22:13:17.905246 u2DelayCellTimex100 = 270/100 ps
2541 22:13:17.908939 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2542 22:13:17.912145 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2543 22:13:17.918819 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2544 22:13:17.921827 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2545 22:13:17.925698 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
2546 22:13:17.928399 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2547 22:13:17.928498
2548 22:13:17.932036 CA PerBit enable=1, Macro0, CA PI delay=33
2549 22:13:17.932115
2550 22:13:17.935488 [CBTSetCACLKResult] CA Dly = 33
2551 22:13:17.935586 CS Dly: 8 (0~39)
2552 22:13:17.938857 ==
2553 22:13:17.941639 Dram Type= 6, Freq= 0, CH_0, rank 1
2554 22:13:17.945164 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2555 22:13:17.945247 ==
2556 22:13:17.948532 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2557 22:13:17.955077 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2558 22:13:17.964537 [CA 0] Center 39 (9~70) winsize 62
2559 22:13:17.968225 [CA 1] Center 39 (9~70) winsize 62
2560 22:13:17.971115 [CA 2] Center 35 (5~66) winsize 62
2561 22:13:17.974897 [CA 3] Center 34 (4~65) winsize 62
2562 22:13:17.977940 [CA 4] Center 33 (3~64) winsize 62
2563 22:13:17.981162 [CA 5] Center 33 (3~63) winsize 61
2564 22:13:17.981261
2565 22:13:17.984402 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2566 22:13:17.984499
2567 22:13:17.988298 [CATrainingPosCal] consider 2 rank data
2568 22:13:17.991265 u2DelayCellTimex100 = 270/100 ps
2569 22:13:17.994790 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2570 22:13:17.998204 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2571 22:13:18.004658 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2572 22:13:18.007698 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
2573 22:13:18.011381 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
2574 22:13:18.014615 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2575 22:13:18.014699
2576 22:13:18.018275 CA PerBit enable=1, Macro0, CA PI delay=33
2577 22:13:18.018359
2578 22:13:18.020924 [CBTSetCACLKResult] CA Dly = 33
2579 22:13:18.021006 CS Dly: 9 (0~41)
2580 22:13:18.021073
2581 22:13:18.024573 ----->DramcWriteLeveling(PI) begin...
2582 22:13:18.028199 ==
2583 22:13:18.030804 Dram Type= 6, Freq= 0, CH_0, rank 0
2584 22:13:18.033999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2585 22:13:18.034083 ==
2586 22:13:18.037913 Write leveling (Byte 0): 35 => 35
2587 22:13:18.040706 Write leveling (Byte 1): 28 => 28
2588 22:13:18.044465 DramcWriteLeveling(PI) end<-----
2589 22:13:18.044548
2590 22:13:18.044613 ==
2591 22:13:18.047401 Dram Type= 6, Freq= 0, CH_0, rank 0
2592 22:13:18.051115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2593 22:13:18.051227 ==
2594 22:13:18.054491 [Gating] SW mode calibration
2595 22:13:18.060937 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2596 22:13:18.067589 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2597 22:13:18.070795 0 15 0 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
2598 22:13:18.074028 0 15 4 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2599 22:13:18.080891 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2600 22:13:18.083937 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2601 22:13:18.087766 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2602 22:13:18.094128 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2603 22:13:18.097491 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2604 22:13:18.100551 0 15 28 | B1->B0 | 3434 2e2e | 1 1 | (1 0) (0 1)
2605 22:13:18.107211 1 0 0 | B1->B0 | 3333 2323 | 1 0 | (1 1) (0 0)
2606 22:13:18.110415 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2607 22:13:18.113888 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2608 22:13:18.120319 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2609 22:13:18.123638 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2610 22:13:18.127184 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2611 22:13:18.133483 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2612 22:13:18.137232 1 0 28 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
2613 22:13:18.140215 1 1 0 | B1->B0 | 2828 4646 | 0 0 | (0 0) (0 0)
2614 22:13:18.146867 1 1 4 | B1->B0 | 3d3d 4646 | 1 0 | (0 0) (0 0)
2615 22:13:18.150494 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2616 22:13:18.153422 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2617 22:13:18.156829 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2618 22:13:18.163267 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2619 22:13:18.166902 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2620 22:13:18.169874 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2621 22:13:18.176727 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2622 22:13:18.179757 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2623 22:13:18.183206 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2624 22:13:18.189701 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2625 22:13:18.192903 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2626 22:13:18.196508 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2627 22:13:18.203229 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2628 22:13:18.206200 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2629 22:13:18.209584 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2630 22:13:18.216483 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2631 22:13:18.219708 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2632 22:13:18.223408 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2633 22:13:18.229948 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2634 22:13:18.233035 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2635 22:13:18.236405 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2636 22:13:18.242691 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2637 22:13:18.246077 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2638 22:13:18.249528 Total UI for P1: 0, mck2ui 16
2639 22:13:18.253236 best dqsien dly found for B0: ( 1, 3, 26)
2640 22:13:18.256021 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2641 22:13:18.259918 Total UI for P1: 0, mck2ui 16
2642 22:13:18.262308 best dqsien dly found for B1: ( 1, 4, 0)
2643 22:13:18.266178 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2644 22:13:18.269659 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2645 22:13:18.272444
2646 22:13:18.275517 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2647 22:13:18.278894 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2648 22:13:18.282480 [Gating] SW calibration Done
2649 22:13:18.282558 ==
2650 22:13:18.285949 Dram Type= 6, Freq= 0, CH_0, rank 0
2651 22:13:18.289046 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2652 22:13:18.289126 ==
2653 22:13:18.289208 RX Vref Scan: 0
2654 22:13:18.289298
2655 22:13:18.292825 RX Vref 0 -> 0, step: 1
2656 22:13:18.292933
2657 22:13:18.296147 RX Delay -40 -> 252, step: 8
2658 22:13:18.298704 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2659 22:13:18.302279 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2660 22:13:18.308796 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2661 22:13:18.312051 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2662 22:13:18.316081 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2663 22:13:18.318945 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2664 22:13:18.321979 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2665 22:13:18.328911 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2666 22:13:18.331925 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2667 22:13:18.335634 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2668 22:13:18.338684 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2669 22:13:18.341798 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2670 22:13:18.348872 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2671 22:13:18.351762 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2672 22:13:18.355154 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2673 22:13:18.358672 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2674 22:13:18.358744 ==
2675 22:13:18.362292 Dram Type= 6, Freq= 0, CH_0, rank 0
2676 22:13:18.368333 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2677 22:13:18.368425 ==
2678 22:13:18.368490 DQS Delay:
2679 22:13:18.368550 DQS0 = 0, DQS1 = 0
2680 22:13:18.371838 DQM Delay:
2681 22:13:18.371914 DQM0 = 119, DQM1 = 107
2682 22:13:18.375508 DQ Delay:
2683 22:13:18.378268 DQ0 =119, DQ1 =119, DQ2 =115, DQ3 =115
2684 22:13:18.381780 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =127
2685 22:13:18.385206 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
2686 22:13:18.388526 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2687 22:13:18.388611
2688 22:13:18.388672
2689 22:13:18.388730 ==
2690 22:13:18.391761 Dram Type= 6, Freq= 0, CH_0, rank 0
2691 22:13:18.394879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2692 22:13:18.394978 ==
2693 22:13:18.398795
2694 22:13:18.398890
2695 22:13:18.398986 TX Vref Scan disable
2696 22:13:18.401398 == TX Byte 0 ==
2697 22:13:18.405101 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2698 22:13:18.408246 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2699 22:13:18.411431 == TX Byte 1 ==
2700 22:13:18.414991 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2701 22:13:18.418021 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2702 22:13:18.418117 ==
2703 22:13:18.421862 Dram Type= 6, Freq= 0, CH_0, rank 0
2704 22:13:18.428142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2705 22:13:18.428241 ==
2706 22:13:18.440143 TX Vref=22, minBit 5, minWin=25, winSum=416
2707 22:13:18.442761 TX Vref=24, minBit 1, minWin=26, winSum=422
2708 22:13:18.446197 TX Vref=26, minBit 4, minWin=26, winSum=427
2709 22:13:18.449106 TX Vref=28, minBit 8, minWin=26, winSum=430
2710 22:13:18.452833 TX Vref=30, minBit 10, minWin=26, winSum=431
2711 22:13:18.459031 TX Vref=32, minBit 4, minWin=26, winSum=427
2712 22:13:18.462626 [TxChooseVref] Worse bit 10, Min win 26, Win sum 431, Final Vref 30
2713 22:13:18.462727
2714 22:13:18.466011 Final TX Range 1 Vref 30
2715 22:13:18.466084
2716 22:13:18.466158 ==
2717 22:13:18.469419 Dram Type= 6, Freq= 0, CH_0, rank 0
2718 22:13:18.472486 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2719 22:13:18.476087 ==
2720 22:13:18.476192
2721 22:13:18.476283
2722 22:13:18.476369 TX Vref Scan disable
2723 22:13:18.479539 == TX Byte 0 ==
2724 22:13:18.482482 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2725 22:13:18.489372 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2726 22:13:18.489456 == TX Byte 1 ==
2727 22:13:18.492476 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2728 22:13:18.499269 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2729 22:13:18.499378
2730 22:13:18.499474 [DATLAT]
2731 22:13:18.499563 Freq=1200, CH0 RK0
2732 22:13:18.499625
2733 22:13:18.502335 DATLAT Default: 0xd
2734 22:13:18.505586 0, 0xFFFF, sum = 0
2735 22:13:18.505661 1, 0xFFFF, sum = 0
2736 22:13:18.508849 2, 0xFFFF, sum = 0
2737 22:13:18.508930 3, 0xFFFF, sum = 0
2738 22:13:18.511995 4, 0xFFFF, sum = 0
2739 22:13:18.512110 5, 0xFFFF, sum = 0
2740 22:13:18.515567 6, 0xFFFF, sum = 0
2741 22:13:18.515655 7, 0xFFFF, sum = 0
2742 22:13:18.518901 8, 0xFFFF, sum = 0
2743 22:13:18.519002 9, 0xFFFF, sum = 0
2744 22:13:18.521982 10, 0xFFFF, sum = 0
2745 22:13:18.522066 11, 0xFFFF, sum = 0
2746 22:13:18.525430 12, 0x0, sum = 1
2747 22:13:18.525520 13, 0x0, sum = 2
2748 22:13:18.529366 14, 0x0, sum = 3
2749 22:13:18.529460 15, 0x0, sum = 4
2750 22:13:18.532067 best_step = 13
2751 22:13:18.532151
2752 22:13:18.532217 ==
2753 22:13:18.535621 Dram Type= 6, Freq= 0, CH_0, rank 0
2754 22:13:18.538852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2755 22:13:18.538942 ==
2756 22:13:18.542122 RX Vref Scan: 1
2757 22:13:18.542239
2758 22:13:18.542314 Set Vref Range= 32 -> 127
2759 22:13:18.542388
2760 22:13:18.545427 RX Vref 32 -> 127, step: 1
2761 22:13:18.545539
2762 22:13:18.548457 RX Delay -21 -> 252, step: 4
2763 22:13:18.548569
2764 22:13:18.551905 Set Vref, RX VrefLevel [Byte0]: 32
2765 22:13:18.555049 [Byte1]: 32
2766 22:13:18.555163
2767 22:13:18.558619 Set Vref, RX VrefLevel [Byte0]: 33
2768 22:13:18.562228 [Byte1]: 33
2769 22:13:18.566206
2770 22:13:18.566312 Set Vref, RX VrefLevel [Byte0]: 34
2771 22:13:18.568987 [Byte1]: 34
2772 22:13:18.573636
2773 22:13:18.573787 Set Vref, RX VrefLevel [Byte0]: 35
2774 22:13:18.576859 [Byte1]: 35
2775 22:13:18.581896
2776 22:13:18.582030 Set Vref, RX VrefLevel [Byte0]: 36
2777 22:13:18.585052 [Byte1]: 36
2778 22:13:18.589481
2779 22:13:18.589590 Set Vref, RX VrefLevel [Byte0]: 37
2780 22:13:18.592640 [Byte1]: 37
2781 22:13:18.597644
2782 22:13:18.597750 Set Vref, RX VrefLevel [Byte0]: 38
2783 22:13:18.600747 [Byte1]: 38
2784 22:13:18.605566
2785 22:13:18.605675 Set Vref, RX VrefLevel [Byte0]: 39
2786 22:13:18.608641 [Byte1]: 39
2787 22:13:18.613470
2788 22:13:18.613573 Set Vref, RX VrefLevel [Byte0]: 40
2789 22:13:18.616475 [Byte1]: 40
2790 22:13:18.621693
2791 22:13:18.621792 Set Vref, RX VrefLevel [Byte0]: 41
2792 22:13:18.624720 [Byte1]: 41
2793 22:13:18.629590
2794 22:13:18.629699 Set Vref, RX VrefLevel [Byte0]: 42
2795 22:13:18.632482 [Byte1]: 42
2796 22:13:18.637165
2797 22:13:18.637236 Set Vref, RX VrefLevel [Byte0]: 43
2798 22:13:18.640426 [Byte1]: 43
2799 22:13:18.645384
2800 22:13:18.645457 Set Vref, RX VrefLevel [Byte0]: 44
2801 22:13:18.648382 [Byte1]: 44
2802 22:13:18.653118
2803 22:13:18.653200 Set Vref, RX VrefLevel [Byte0]: 45
2804 22:13:18.656322 [Byte1]: 45
2805 22:13:18.661396
2806 22:13:18.661471 Set Vref, RX VrefLevel [Byte0]: 46
2807 22:13:18.664449 [Byte1]: 46
2808 22:13:18.669175
2809 22:13:18.669256 Set Vref, RX VrefLevel [Byte0]: 47
2810 22:13:18.672389 [Byte1]: 47
2811 22:13:18.676809
2812 22:13:18.676886 Set Vref, RX VrefLevel [Byte0]: 48
2813 22:13:18.680382 [Byte1]: 48
2814 22:13:18.684861
2815 22:13:18.684944 Set Vref, RX VrefLevel [Byte0]: 49
2816 22:13:18.687832 [Byte1]: 49
2817 22:13:18.692756
2818 22:13:18.692839 Set Vref, RX VrefLevel [Byte0]: 50
2819 22:13:18.696553 [Byte1]: 50
2820 22:13:18.700937
2821 22:13:18.701020 Set Vref, RX VrefLevel [Byte0]: 51
2822 22:13:18.704018 [Byte1]: 51
2823 22:13:18.708431
2824 22:13:18.708513 Set Vref, RX VrefLevel [Byte0]: 52
2825 22:13:18.711709 [Byte1]: 52
2826 22:13:18.716406
2827 22:13:18.716489 Set Vref, RX VrefLevel [Byte0]: 53
2828 22:13:18.719735 [Byte1]: 53
2829 22:13:18.724404
2830 22:13:18.724488 Set Vref, RX VrefLevel [Byte0]: 54
2831 22:13:18.727834 [Byte1]: 54
2832 22:13:18.732154
2833 22:13:18.732237 Set Vref, RX VrefLevel [Byte0]: 55
2834 22:13:18.735345 [Byte1]: 55
2835 22:13:18.740231
2836 22:13:18.740312 Set Vref, RX VrefLevel [Byte0]: 56
2837 22:13:18.743919 [Byte1]: 56
2838 22:13:18.748226
2839 22:13:18.748307 Set Vref, RX VrefLevel [Byte0]: 57
2840 22:13:18.751839 [Byte1]: 57
2841 22:13:18.755900
2842 22:13:18.755981 Set Vref, RX VrefLevel [Byte0]: 58
2843 22:13:18.759442 [Byte1]: 58
2844 22:13:18.763845
2845 22:13:18.763926 Set Vref, RX VrefLevel [Byte0]: 59
2846 22:13:18.767208 [Byte1]: 59
2847 22:13:18.772566
2848 22:13:18.772647 Set Vref, RX VrefLevel [Byte0]: 60
2849 22:13:18.775135 [Byte1]: 60
2850 22:13:18.779760
2851 22:13:18.779844 Set Vref, RX VrefLevel [Byte0]: 61
2852 22:13:18.783511 [Byte1]: 61
2853 22:13:18.788424
2854 22:13:18.788505 Set Vref, RX VrefLevel [Byte0]: 62
2855 22:13:18.791131 [Byte1]: 62
2856 22:13:18.795843
2857 22:13:18.795965 Set Vref, RX VrefLevel [Byte0]: 63
2858 22:13:18.799128 [Byte1]: 63
2859 22:13:18.803594
2860 22:13:18.803676 Set Vref, RX VrefLevel [Byte0]: 64
2861 22:13:18.807196 [Byte1]: 64
2862 22:13:18.811850
2863 22:13:18.811949 Set Vref, RX VrefLevel [Byte0]: 65
2864 22:13:18.814920 [Byte1]: 65
2865 22:13:18.819643
2866 22:13:18.819723 Set Vref, RX VrefLevel [Byte0]: 66
2867 22:13:18.822695 [Byte1]: 66
2868 22:13:18.827230
2869 22:13:18.827311 Set Vref, RX VrefLevel [Byte0]: 67
2870 22:13:18.830765 [Byte1]: 67
2871 22:13:18.835180
2872 22:13:18.835260 Set Vref, RX VrefLevel [Byte0]: 68
2873 22:13:18.838403 [Byte1]: 68
2874 22:13:18.843126
2875 22:13:18.843207 Set Vref, RX VrefLevel [Byte0]: 69
2876 22:13:18.846622 [Byte1]: 69
2877 22:13:18.851219
2878 22:13:18.851300 Set Vref, RX VrefLevel [Byte0]: 70
2879 22:13:18.854564 [Byte1]: 70
2880 22:13:18.858945
2881 22:13:18.859051 Set Vref, RX VrefLevel [Byte0]: 71
2882 22:13:18.862417 [Byte1]: 71
2883 22:13:18.867341
2884 22:13:18.867422 Set Vref, RX VrefLevel [Byte0]: 72
2885 22:13:18.870087 [Byte1]: 72
2886 22:13:18.875165
2887 22:13:18.875246 Set Vref, RX VrefLevel [Byte0]: 73
2888 22:13:18.878178 [Byte1]: 73
2889 22:13:18.883012
2890 22:13:18.883147 Set Vref, RX VrefLevel [Byte0]: 74
2891 22:13:18.886219 [Byte1]: 74
2892 22:13:18.890609
2893 22:13:18.890690 Set Vref, RX VrefLevel [Byte0]: 75
2894 22:13:18.894268 [Byte1]: 75
2895 22:13:18.898951
2896 22:13:18.899066 Set Vref, RX VrefLevel [Byte0]: 76
2897 22:13:18.901902 [Byte1]: 76
2898 22:13:18.906467
2899 22:13:18.906573 Set Vref, RX VrefLevel [Byte0]: 77
2900 22:13:18.910185 [Byte1]: 77
2901 22:13:18.914402
2902 22:13:18.914499 Set Vref, RX VrefLevel [Byte0]: 78
2903 22:13:18.917643 [Byte1]: 78
2904 22:13:18.922904
2905 22:13:18.922986 Final RX Vref Byte 0 = 61 to rank0
2906 22:13:18.925852 Final RX Vref Byte 1 = 51 to rank0
2907 22:13:18.928845 Final RX Vref Byte 0 = 61 to rank1
2908 22:13:18.932510 Final RX Vref Byte 1 = 51 to rank1==
2909 22:13:18.935617 Dram Type= 6, Freq= 0, CH_0, rank 0
2910 22:13:18.942471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2911 22:13:18.942573 ==
2912 22:13:18.942672 DQS Delay:
2913 22:13:18.942749 DQS0 = 0, DQS1 = 0
2914 22:13:18.945618 DQM Delay:
2915 22:13:18.945701 DQM0 = 119, DQM1 = 107
2916 22:13:18.948977 DQ Delay:
2917 22:13:18.952284 DQ0 =116, DQ1 =120, DQ2 =116, DQ3 =116
2918 22:13:18.955669 DQ4 =120, DQ5 =114, DQ6 =128, DQ7 =126
2919 22:13:18.959244 DQ8 =98, DQ9 =94, DQ10 =110, DQ11 =100
2920 22:13:18.962441 DQ12 =112, DQ13 =110, DQ14 =120, DQ15 =116
2921 22:13:18.962540
2922 22:13:18.962636
2923 22:13:18.972312 [DQSOSCAuto] RK0, (LSB)MR18= 0x1400, (MSB)MR19= 0x404, tDQSOscB0 = 410 ps tDQSOscB1 = 402 ps
2924 22:13:18.972429 CH0 RK0: MR19=404, MR18=1400
2925 22:13:18.979065 CH0_RK0: MR19=0x404, MR18=0x1400, DQSOSC=402, MR23=63, INC=40, DEC=27
2926 22:13:18.979182
2927 22:13:18.981970 ----->DramcWriteLeveling(PI) begin...
2928 22:13:18.982071 ==
2929 22:13:18.985392 Dram Type= 6, Freq= 0, CH_0, rank 1
2930 22:13:18.992270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2931 22:13:18.992369 ==
2932 22:13:18.995985 Write leveling (Byte 0): 34 => 34
2933 22:13:18.996066 Write leveling (Byte 1): 30 => 30
2934 22:13:18.998574 DramcWriteLeveling(PI) end<-----
2935 22:13:18.998673
2936 22:13:19.002003 ==
2937 22:13:19.005392 Dram Type= 6, Freq= 0, CH_0, rank 1
2938 22:13:19.008465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2939 22:13:19.008548 ==
2940 22:13:19.011653 [Gating] SW mode calibration
2941 22:13:19.018486 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2942 22:13:19.021627 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2943 22:13:19.028201 0 15 0 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
2944 22:13:19.031901 0 15 4 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
2945 22:13:19.034703 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2946 22:13:19.041361 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2947 22:13:19.044839 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2948 22:13:19.048130 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2949 22:13:19.054580 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2950 22:13:19.057868 0 15 28 | B1->B0 | 3434 3232 | 1 1 | (1 0) (1 0)
2951 22:13:19.061612 1 0 0 | B1->B0 | 2c2c 2323 | 0 0 | (1 0) (0 0)
2952 22:13:19.067826 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2953 22:13:19.071535 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2954 22:13:19.074879 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2955 22:13:19.081165 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2956 22:13:19.084408 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2957 22:13:19.087814 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2958 22:13:19.094397 1 0 28 | B1->B0 | 2424 2f2f | 0 0 | (0 0) (0 0)
2959 22:13:19.097671 1 1 0 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
2960 22:13:19.101444 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2961 22:13:19.107756 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2962 22:13:19.110968 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2963 22:13:19.114439 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2964 22:13:19.121070 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2965 22:13:19.124389 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2966 22:13:19.127993 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2967 22:13:19.134341 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2968 22:13:19.137846 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2969 22:13:19.141010 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2970 22:13:19.147396 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2971 22:13:19.151404 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2972 22:13:19.154779 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2973 22:13:19.157462 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2974 22:13:19.164216 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2975 22:13:19.167481 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2976 22:13:19.174018 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2977 22:13:19.177530 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2978 22:13:19.180669 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2979 22:13:19.184634 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2980 22:13:19.190531 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2981 22:13:19.193851 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2982 22:13:19.197407 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2983 22:13:19.204260 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2984 22:13:19.207559 Total UI for P1: 0, mck2ui 16
2985 22:13:19.210807 best dqsien dly found for B0: ( 1, 3, 28)
2986 22:13:19.214234 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2987 22:13:19.217092 Total UI for P1: 0, mck2ui 16
2988 22:13:19.220787 best dqsien dly found for B1: ( 1, 4, 0)
2989 22:13:19.223704 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2990 22:13:19.227014 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2991 22:13:19.227107
2992 22:13:19.230532 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2993 22:13:19.234126 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2994 22:13:19.237368 [Gating] SW calibration Done
2995 22:13:19.237452 ==
2996 22:13:19.240968 Dram Type= 6, Freq= 0, CH_0, rank 1
2997 22:13:19.243769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2998 22:13:19.247203 ==
2999 22:13:19.247287 RX Vref Scan: 0
3000 22:13:19.247354
3001 22:13:19.250617 RX Vref 0 -> 0, step: 1
3002 22:13:19.250702
3003 22:13:19.253719 RX Delay -40 -> 252, step: 8
3004 22:13:19.257349 iDelay=200, Bit 0, Center 115 (48 ~ 183) 136
3005 22:13:19.260440 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
3006 22:13:19.263763 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
3007 22:13:19.266912 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3008 22:13:19.273673 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3009 22:13:19.276952 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
3010 22:13:19.280372 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3011 22:13:19.283236 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
3012 22:13:19.286617 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3013 22:13:19.293248 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3014 22:13:19.296244 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3015 22:13:19.299970 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3016 22:13:19.302945 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3017 22:13:19.306348 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3018 22:13:19.313283 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3019 22:13:19.316495 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3020 22:13:19.316578 ==
3021 22:13:19.319605 Dram Type= 6, Freq= 0, CH_0, rank 1
3022 22:13:19.323629 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3023 22:13:19.323739 ==
3024 22:13:19.326411 DQS Delay:
3025 22:13:19.326557 DQS0 = 0, DQS1 = 0
3026 22:13:19.326686 DQM Delay:
3027 22:13:19.329662 DQM0 = 117, DQM1 = 108
3028 22:13:19.329758 DQ Delay:
3029 22:13:19.333145 DQ0 =115, DQ1 =119, DQ2 =111, DQ3 =115
3030 22:13:19.336559 DQ4 =119, DQ5 =111, DQ6 =123, DQ7 =123
3031 22:13:19.339622 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
3032 22:13:19.346774 DQ12 =111, DQ13 =119, DQ14 =119, DQ15 =111
3033 22:13:19.346884
3034 22:13:19.346978
3035 22:13:19.347073 ==
3036 22:13:19.349590 Dram Type= 6, Freq= 0, CH_0, rank 1
3037 22:13:19.352827 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3038 22:13:19.352932 ==
3039 22:13:19.353028
3040 22:13:19.353151
3041 22:13:19.356612 TX Vref Scan disable
3042 22:13:19.356745 == TX Byte 0 ==
3043 22:13:19.363244 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
3044 22:13:19.366380 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
3045 22:13:19.366464 == TX Byte 1 ==
3046 22:13:19.372856 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3047 22:13:19.376022 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3048 22:13:19.376107 ==
3049 22:13:19.379181 Dram Type= 6, Freq= 0, CH_0, rank 1
3050 22:13:19.382581 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3051 22:13:19.382665 ==
3052 22:13:19.395981 TX Vref=22, minBit 0, minWin=26, winSum=418
3053 22:13:19.399854 TX Vref=24, minBit 1, minWin=26, winSum=421
3054 22:13:19.402816 TX Vref=26, minBit 1, minWin=26, winSum=429
3055 22:13:19.406348 TX Vref=28, minBit 13, minWin=25, winSum=428
3056 22:13:19.409268 TX Vref=30, minBit 10, minWin=26, winSum=432
3057 22:13:19.416045 TX Vref=32, minBit 4, minWin=26, winSum=429
3058 22:13:19.419253 [TxChooseVref] Worse bit 10, Min win 26, Win sum 432, Final Vref 30
3059 22:13:19.419351
3060 22:13:19.422388 Final TX Range 1 Vref 30
3061 22:13:19.422468
3062 22:13:19.422565 ==
3063 22:13:19.426224 Dram Type= 6, Freq= 0, CH_0, rank 1
3064 22:13:19.429057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3065 22:13:19.432631 ==
3066 22:13:19.432707
3067 22:13:19.432771
3068 22:13:19.432849 TX Vref Scan disable
3069 22:13:19.435899 == TX Byte 0 ==
3070 22:13:19.439251 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
3071 22:13:19.446198 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
3072 22:13:19.446283 == TX Byte 1 ==
3073 22:13:19.449444 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3074 22:13:19.455901 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3075 22:13:19.455986
3076 22:13:19.456053 [DATLAT]
3077 22:13:19.456116 Freq=1200, CH0 RK1
3078 22:13:19.456176
3079 22:13:19.459658 DATLAT Default: 0xd
3080 22:13:19.459743 0, 0xFFFF, sum = 0
3081 22:13:19.462900 1, 0xFFFF, sum = 0
3082 22:13:19.466589 2, 0xFFFF, sum = 0
3083 22:13:19.466674 3, 0xFFFF, sum = 0
3084 22:13:19.469727 4, 0xFFFF, sum = 0
3085 22:13:19.469835 5, 0xFFFF, sum = 0
3086 22:13:19.472577 6, 0xFFFF, sum = 0
3087 22:13:19.472689 7, 0xFFFF, sum = 0
3088 22:13:19.476242 8, 0xFFFF, sum = 0
3089 22:13:19.476350 9, 0xFFFF, sum = 0
3090 22:13:19.479221 10, 0xFFFF, sum = 0
3091 22:13:19.479327 11, 0xFFFF, sum = 0
3092 22:13:19.482757 12, 0x0, sum = 1
3093 22:13:19.482872 13, 0x0, sum = 2
3094 22:13:19.485889 14, 0x0, sum = 3
3095 22:13:19.485989 15, 0x0, sum = 4
3096 22:13:19.488865 best_step = 13
3097 22:13:19.488974
3098 22:13:19.489072 ==
3099 22:13:19.492507 Dram Type= 6, Freq= 0, CH_0, rank 1
3100 22:13:19.495590 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3101 22:13:19.495692 ==
3102 22:13:19.495786 RX Vref Scan: 0
3103 22:13:19.499093
3104 22:13:19.499189 RX Vref 0 -> 0, step: 1
3105 22:13:19.499279
3106 22:13:19.502963 RX Delay -21 -> 252, step: 4
3107 22:13:19.509701 iDelay=195, Bit 0, Center 114 (47 ~ 182) 136
3108 22:13:19.512120 iDelay=195, Bit 1, Center 118 (47 ~ 190) 144
3109 22:13:19.516008 iDelay=195, Bit 2, Center 110 (43 ~ 178) 136
3110 22:13:19.519425 iDelay=195, Bit 3, Center 112 (43 ~ 182) 140
3111 22:13:19.522301 iDelay=195, Bit 4, Center 116 (47 ~ 186) 140
3112 22:13:19.525323 iDelay=195, Bit 5, Center 110 (43 ~ 178) 136
3113 22:13:19.531894 iDelay=195, Bit 6, Center 124 (55 ~ 194) 140
3114 22:13:19.535455 iDelay=195, Bit 7, Center 124 (55 ~ 194) 140
3115 22:13:19.538598 iDelay=195, Bit 8, Center 96 (27 ~ 166) 140
3116 22:13:19.542246 iDelay=195, Bit 9, Center 94 (27 ~ 162) 136
3117 22:13:19.545218 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3118 22:13:19.551927 iDelay=195, Bit 11, Center 100 (35 ~ 166) 132
3119 22:13:19.555495 iDelay=195, Bit 12, Center 114 (47 ~ 182) 136
3120 22:13:19.558775 iDelay=195, Bit 13, Center 114 (47 ~ 182) 136
3121 22:13:19.562244 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3122 22:13:19.568506 iDelay=195, Bit 15, Center 116 (51 ~ 182) 132
3123 22:13:19.568618 ==
3124 22:13:19.572175 Dram Type= 6, Freq= 0, CH_0, rank 1
3125 22:13:19.575502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3126 22:13:19.575603 ==
3127 22:13:19.575692 DQS Delay:
3128 22:13:19.578718 DQS0 = 0, DQS1 = 0
3129 22:13:19.578811 DQM Delay:
3130 22:13:19.581721 DQM0 = 116, DQM1 = 107
3131 22:13:19.581820 DQ Delay:
3132 22:13:19.585432 DQ0 =114, DQ1 =118, DQ2 =110, DQ3 =112
3133 22:13:19.588893 DQ4 =116, DQ5 =110, DQ6 =124, DQ7 =124
3134 22:13:19.591940 DQ8 =96, DQ9 =94, DQ10 =110, DQ11 =100
3135 22:13:19.595065 DQ12 =114, DQ13 =114, DQ14 =118, DQ15 =116
3136 22:13:19.595158
3137 22:13:19.595222
3138 22:13:19.605492 [DQSOSCAuto] RK1, (LSB)MR18= 0xbe5, (MSB)MR19= 0x403, tDQSOscB0 = 421 ps tDQSOscB1 = 405 ps
3139 22:13:19.609490 CH0 RK1: MR19=403, MR18=BE5
3140 22:13:19.612238 CH0_RK1: MR19=0x403, MR18=0xBE5, DQSOSC=405, MR23=63, INC=39, DEC=26
3141 22:13:19.615272 [RxdqsGatingPostProcess] freq 1200
3142 22:13:19.621747 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3143 22:13:19.625277 best DQS0 dly(2T, 0.5T) = (0, 11)
3144 22:13:19.628495 best DQS1 dly(2T, 0.5T) = (0, 12)
3145 22:13:19.631880 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3146 22:13:19.635424 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3147 22:13:19.638286 best DQS0 dly(2T, 0.5T) = (0, 11)
3148 22:13:19.641902 best DQS1 dly(2T, 0.5T) = (0, 12)
3149 22:13:19.644922 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3150 22:13:19.645007 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3151 22:13:19.648495 Pre-setting of DQS Precalculation
3152 22:13:19.654951 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3153 22:13:19.655088 ==
3154 22:13:19.658467 Dram Type= 6, Freq= 0, CH_1, rank 0
3155 22:13:19.661568 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3156 22:13:19.661671 ==
3157 22:13:19.668441 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3158 22:13:19.674560 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3159 22:13:19.681915 [CA 0] Center 37 (7~67) winsize 61
3160 22:13:19.685610 [CA 1] Center 38 (8~68) winsize 61
3161 22:13:19.688804 [CA 2] Center 34 (4~64) winsize 61
3162 22:13:19.692061 [CA 3] Center 33 (3~64) winsize 62
3163 22:13:19.695482 [CA 4] Center 34 (4~64) winsize 61
3164 22:13:19.699334 [CA 5] Center 33 (3~64) winsize 62
3165 22:13:19.699414
3166 22:13:19.702306 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3167 22:13:19.702404
3168 22:13:19.705509 [CATrainingPosCal] consider 1 rank data
3169 22:13:19.708844 u2DelayCellTimex100 = 270/100 ps
3170 22:13:19.712232 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3171 22:13:19.715831 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3172 22:13:19.721909 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3173 22:13:19.725613 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3174 22:13:19.728709 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3175 22:13:19.731856 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3176 22:13:19.731933
3177 22:13:19.735486 CA PerBit enable=1, Macro0, CA PI delay=33
3178 22:13:19.735568
3179 22:13:19.738477 [CBTSetCACLKResult] CA Dly = 33
3180 22:13:19.738576 CS Dly: 5 (0~36)
3181 22:13:19.742114 ==
3182 22:13:19.745366 Dram Type= 6, Freq= 0, CH_1, rank 1
3183 22:13:19.748572 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3184 22:13:19.748681 ==
3185 22:13:19.752117 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3186 22:13:19.758909 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3187 22:13:19.768032 [CA 0] Center 37 (7~67) winsize 61
3188 22:13:19.771533 [CA 1] Center 38 (8~68) winsize 61
3189 22:13:19.774581 [CA 2] Center 34 (4~65) winsize 62
3190 22:13:19.777888 [CA 3] Center 33 (3~64) winsize 62
3191 22:13:19.781040 [CA 4] Center 34 (3~65) winsize 63
3192 22:13:19.784439 [CA 5] Center 33 (3~64) winsize 62
3193 22:13:19.784523
3194 22:13:19.787880 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3195 22:13:19.787963
3196 22:13:19.790874 [CATrainingPosCal] consider 2 rank data
3197 22:13:19.794721 u2DelayCellTimex100 = 270/100 ps
3198 22:13:19.797432 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3199 22:13:19.804529 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3200 22:13:19.807860 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3201 22:13:19.810773 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3202 22:13:19.814402 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3203 22:13:19.817342 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3204 22:13:19.817425
3205 22:13:19.821056 CA PerBit enable=1, Macro0, CA PI delay=33
3206 22:13:19.821139
3207 22:13:19.824054 [CBTSetCACLKResult] CA Dly = 33
3208 22:13:19.824137 CS Dly: 7 (0~40)
3209 22:13:19.827991
3210 22:13:19.831223 ----->DramcWriteLeveling(PI) begin...
3211 22:13:19.831307 ==
3212 22:13:19.834228 Dram Type= 6, Freq= 0, CH_1, rank 0
3213 22:13:19.837319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3214 22:13:19.837402 ==
3215 22:13:19.840980 Write leveling (Byte 0): 23 => 23
3216 22:13:19.844152 Write leveling (Byte 1): 30 => 30
3217 22:13:19.847458 DramcWriteLeveling(PI) end<-----
3218 22:13:19.847540
3219 22:13:19.847604 ==
3220 22:13:19.850986 Dram Type= 6, Freq= 0, CH_1, rank 0
3221 22:13:19.854095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3222 22:13:19.854177 ==
3223 22:13:19.857178 [Gating] SW mode calibration
3224 22:13:19.864163 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3225 22:13:19.870626 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3226 22:13:19.873834 0 15 0 | B1->B0 | 3030 3434 | 1 0 | (1 1) (0 0)
3227 22:13:19.877083 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3228 22:13:19.883487 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3229 22:13:19.887279 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3230 22:13:19.890495 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3231 22:13:19.896925 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3232 22:13:19.900530 0 15 24 | B1->B0 | 3434 3232 | 1 1 | (1 0) (0 0)
3233 22:13:19.903462 0 15 28 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
3234 22:13:19.910170 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3235 22:13:19.913501 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3236 22:13:19.917126 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3237 22:13:19.923785 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3238 22:13:19.926566 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3239 22:13:19.930310 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3240 22:13:19.936733 1 0 24 | B1->B0 | 2929 3f3f | 0 1 | (0 0) (0 0)
3241 22:13:19.940442 1 0 28 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
3242 22:13:19.943600 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3243 22:13:19.946982 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3244 22:13:19.953512 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3245 22:13:19.956822 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3246 22:13:19.960209 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3247 22:13:19.966709 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3248 22:13:19.969652 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3249 22:13:19.973065 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3250 22:13:19.979979 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3251 22:13:19.982996 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3252 22:13:19.986355 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3253 22:13:19.993010 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3254 22:13:19.996570 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3255 22:13:19.999656 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3256 22:13:20.006526 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3257 22:13:20.009891 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3258 22:13:20.012971 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3259 22:13:20.019845 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3260 22:13:20.022820 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3261 22:13:20.026067 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3262 22:13:20.032527 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3263 22:13:20.035898 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3264 22:13:20.039636 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3265 22:13:20.046176 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3266 22:13:20.049157 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3267 22:13:20.052759 Total UI for P1: 0, mck2ui 16
3268 22:13:20.056167 best dqsien dly found for B0: ( 1, 3, 26)
3269 22:13:20.058993 Total UI for P1: 0, mck2ui 16
3270 22:13:20.062699 best dqsien dly found for B1: ( 1, 3, 28)
3271 22:13:20.065898 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3272 22:13:20.069291 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3273 22:13:20.069394
3274 22:13:20.072782 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3275 22:13:20.075897 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3276 22:13:20.079280 [Gating] SW calibration Done
3277 22:13:20.079368 ==
3278 22:13:20.082642 Dram Type= 6, Freq= 0, CH_1, rank 0
3279 22:13:20.085748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3280 22:13:20.089233 ==
3281 22:13:20.089337 RX Vref Scan: 0
3282 22:13:20.089459
3283 22:13:20.092552 RX Vref 0 -> 0, step: 1
3284 22:13:20.092646
3285 22:13:20.095788 RX Delay -40 -> 252, step: 8
3286 22:13:20.098922 iDelay=208, Bit 0, Center 123 (48 ~ 199) 152
3287 22:13:20.102222 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3288 22:13:20.105593 iDelay=208, Bit 2, Center 111 (40 ~ 183) 144
3289 22:13:20.109098 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3290 22:13:20.115873 iDelay=208, Bit 4, Center 111 (40 ~ 183) 144
3291 22:13:20.118935 iDelay=208, Bit 5, Center 131 (56 ~ 207) 152
3292 22:13:20.122469 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3293 22:13:20.125765 iDelay=208, Bit 7, Center 115 (48 ~ 183) 136
3294 22:13:20.128692 iDelay=208, Bit 8, Center 95 (24 ~ 167) 144
3295 22:13:20.135322 iDelay=208, Bit 9, Center 99 (24 ~ 175) 152
3296 22:13:20.138956 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3297 22:13:20.142108 iDelay=208, Bit 11, Center 95 (24 ~ 167) 144
3298 22:13:20.145781 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3299 22:13:20.148560 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3300 22:13:20.156057 iDelay=208, Bit 14, Center 119 (48 ~ 191) 144
3301 22:13:20.158999 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3302 22:13:20.159125 ==
3303 22:13:20.162260 Dram Type= 6, Freq= 0, CH_1, rank 0
3304 22:13:20.165230 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3305 22:13:20.165302 ==
3306 22:13:20.168781 DQS Delay:
3307 22:13:20.168905 DQS0 = 0, DQS1 = 0
3308 22:13:20.169039 DQM Delay:
3309 22:13:20.172238 DQM0 = 117, DQM1 = 109
3310 22:13:20.172320 DQ Delay:
3311 22:13:20.175497 DQ0 =123, DQ1 =111, DQ2 =111, DQ3 =115
3312 22:13:20.178477 DQ4 =111, DQ5 =131, DQ6 =123, DQ7 =115
3313 22:13:20.182088 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =95
3314 22:13:20.188366 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3315 22:13:20.188445
3316 22:13:20.188514
3317 22:13:20.188572 ==
3318 22:13:20.191814 Dram Type= 6, Freq= 0, CH_1, rank 0
3319 22:13:20.195333 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3320 22:13:20.195418 ==
3321 22:13:20.195484
3322 22:13:20.195544
3323 22:13:20.198744 TX Vref Scan disable
3324 22:13:20.198847 == TX Byte 0 ==
3325 22:13:20.205241 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
3326 22:13:20.208322 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
3327 22:13:20.208393 == TX Byte 1 ==
3328 22:13:20.215260 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3329 22:13:20.218553 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3330 22:13:20.218626 ==
3331 22:13:20.222059 Dram Type= 6, Freq= 0, CH_1, rank 0
3332 22:13:20.225188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3333 22:13:20.225265 ==
3334 22:13:20.237924 TX Vref=22, minBit 8, minWin=25, winSum=416
3335 22:13:20.241375 TX Vref=24, minBit 10, minWin=25, winSum=422
3336 22:13:20.244877 TX Vref=26, minBit 8, minWin=25, winSum=426
3337 22:13:20.247848 TX Vref=28, minBit 9, minWin=25, winSum=432
3338 22:13:20.251171 TX Vref=30, minBit 9, minWin=25, winSum=431
3339 22:13:20.258041 TX Vref=32, minBit 9, minWin=25, winSum=426
3340 22:13:20.261734 [TxChooseVref] Worse bit 9, Min win 25, Win sum 432, Final Vref 28
3341 22:13:20.261816
3342 22:13:20.264544 Final TX Range 1 Vref 28
3343 22:13:20.264615
3344 22:13:20.264675 ==
3345 22:13:20.267807 Dram Type= 6, Freq= 0, CH_1, rank 0
3346 22:13:20.271176 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3347 22:13:20.271254 ==
3348 22:13:20.274588
3349 22:13:20.274661
3350 22:13:20.274724 TX Vref Scan disable
3351 22:13:20.277876 == TX Byte 0 ==
3352 22:13:20.281536 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
3353 22:13:20.284502 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
3354 22:13:20.288002 == TX Byte 1 ==
3355 22:13:20.291001 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3356 22:13:20.297881 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3357 22:13:20.297965
3358 22:13:20.298029 [DATLAT]
3359 22:13:20.298089 Freq=1200, CH1 RK0
3360 22:13:20.298155
3361 22:13:20.301118 DATLAT Default: 0xd
3362 22:13:20.301198 0, 0xFFFF, sum = 0
3363 22:13:20.304969 1, 0xFFFF, sum = 0
3364 22:13:20.305092 2, 0xFFFF, sum = 0
3365 22:13:20.307883 3, 0xFFFF, sum = 0
3366 22:13:20.311421 4, 0xFFFF, sum = 0
3367 22:13:20.311500 5, 0xFFFF, sum = 0
3368 22:13:20.314595 6, 0xFFFF, sum = 0
3369 22:13:20.314693 7, 0xFFFF, sum = 0
3370 22:13:20.317800 8, 0xFFFF, sum = 0
3371 22:13:20.317900 9, 0xFFFF, sum = 0
3372 22:13:20.321990 10, 0xFFFF, sum = 0
3373 22:13:20.322062 11, 0xFFFF, sum = 0
3374 22:13:20.324508 12, 0x0, sum = 1
3375 22:13:20.324609 13, 0x0, sum = 2
3376 22:13:20.327568 14, 0x0, sum = 3
3377 22:13:20.327639 15, 0x0, sum = 4
3378 22:13:20.327699 best_step = 13
3379 22:13:20.331190
3380 22:13:20.331263 ==
3381 22:13:20.334498 Dram Type= 6, Freq= 0, CH_1, rank 0
3382 22:13:20.337623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3383 22:13:20.337722 ==
3384 22:13:20.337809 RX Vref Scan: 1
3385 22:13:20.337898
3386 22:13:20.341233 Set Vref Range= 32 -> 127
3387 22:13:20.341305
3388 22:13:20.344075 RX Vref 32 -> 127, step: 1
3389 22:13:20.344145
3390 22:13:20.347701 RX Delay -21 -> 252, step: 4
3391 22:13:20.347771
3392 22:13:20.350847 Set Vref, RX VrefLevel [Byte0]: 32
3393 22:13:20.354506 [Byte1]: 32
3394 22:13:20.354604
3395 22:13:20.357320 Set Vref, RX VrefLevel [Byte0]: 33
3396 22:13:20.360937 [Byte1]: 33
3397 22:13:20.364314
3398 22:13:20.364403 Set Vref, RX VrefLevel [Byte0]: 34
3399 22:13:20.367667 [Byte1]: 34
3400 22:13:20.372364
3401 22:13:20.372464 Set Vref, RX VrefLevel [Byte0]: 35
3402 22:13:20.375578 [Byte1]: 35
3403 22:13:20.380715
3404 22:13:20.380813 Set Vref, RX VrefLevel [Byte0]: 36
3405 22:13:20.383365 [Byte1]: 36
3406 22:13:20.388167
3407 22:13:20.388266 Set Vref, RX VrefLevel [Byte0]: 37
3408 22:13:20.394502 [Byte1]: 37
3409 22:13:20.394603
3410 22:13:20.397820 Set Vref, RX VrefLevel [Byte0]: 38
3411 22:13:20.400841 [Byte1]: 38
3412 22:13:20.400939
3413 22:13:20.404739 Set Vref, RX VrefLevel [Byte0]: 39
3414 22:13:20.407948 [Byte1]: 39
3415 22:13:20.412064
3416 22:13:20.412138 Set Vref, RX VrefLevel [Byte0]: 40
3417 22:13:20.415159 [Byte1]: 40
3418 22:13:20.419998
3419 22:13:20.420110 Set Vref, RX VrefLevel [Byte0]: 41
3420 22:13:20.422939 [Byte1]: 41
3421 22:13:20.428631
3422 22:13:20.428741 Set Vref, RX VrefLevel [Byte0]: 42
3423 22:13:20.431194 [Byte1]: 42
3424 22:13:20.435434
3425 22:13:20.435504 Set Vref, RX VrefLevel [Byte0]: 43
3426 22:13:20.439235 [Byte1]: 43
3427 22:13:20.443961
3428 22:13:20.444060 Set Vref, RX VrefLevel [Byte0]: 44
3429 22:13:20.447130 [Byte1]: 44
3430 22:13:20.451426
3431 22:13:20.451522 Set Vref, RX VrefLevel [Byte0]: 45
3432 22:13:20.454929 [Byte1]: 45
3433 22:13:20.459277
3434 22:13:20.459350 Set Vref, RX VrefLevel [Byte0]: 46
3435 22:13:20.462953 [Byte1]: 46
3436 22:13:20.467380
3437 22:13:20.467453 Set Vref, RX VrefLevel [Byte0]: 47
3438 22:13:20.470607 [Byte1]: 47
3439 22:13:20.475666
3440 22:13:20.475744 Set Vref, RX VrefLevel [Byte0]: 48
3441 22:13:20.478598 [Byte1]: 48
3442 22:13:20.483250
3443 22:13:20.483349 Set Vref, RX VrefLevel [Byte0]: 49
3444 22:13:20.486765 [Byte1]: 49
3445 22:13:20.490929
3446 22:13:20.491025 Set Vref, RX VrefLevel [Byte0]: 50
3447 22:13:20.494377 [Byte1]: 50
3448 22:13:20.499344
3449 22:13:20.499440 Set Vref, RX VrefLevel [Byte0]: 51
3450 22:13:20.502397 [Byte1]: 51
3451 22:13:20.506932
3452 22:13:20.507028 Set Vref, RX VrefLevel [Byte0]: 52
3453 22:13:20.510392 [Byte1]: 52
3454 22:13:20.514779
3455 22:13:20.514877 Set Vref, RX VrefLevel [Byte0]: 53
3456 22:13:20.518009 [Byte1]: 53
3457 22:13:20.522397
3458 22:13:20.526037 Set Vref, RX VrefLevel [Byte0]: 54
3459 22:13:20.526135 [Byte1]: 54
3460 22:13:20.530370
3461 22:13:20.530466 Set Vref, RX VrefLevel [Byte0]: 55
3462 22:13:20.533996 [Byte1]: 55
3463 22:13:20.538509
3464 22:13:20.538607 Set Vref, RX VrefLevel [Byte0]: 56
3465 22:13:20.541669 [Byte1]: 56
3466 22:13:20.546370
3467 22:13:20.546452 Set Vref, RX VrefLevel [Byte0]: 57
3468 22:13:20.550015 [Byte1]: 57
3469 22:13:20.554755
3470 22:13:20.554852 Set Vref, RX VrefLevel [Byte0]: 58
3471 22:13:20.557655 [Byte1]: 58
3472 22:13:20.562503
3473 22:13:20.562585 Set Vref, RX VrefLevel [Byte0]: 59
3474 22:13:20.565829 [Byte1]: 59
3475 22:13:20.570482
3476 22:13:20.570580 Set Vref, RX VrefLevel [Byte0]: 60
3477 22:13:20.573347 [Byte1]: 60
3478 22:13:20.578077
3479 22:13:20.578174 Set Vref, RX VrefLevel [Byte0]: 61
3480 22:13:20.581609 [Byte1]: 61
3481 22:13:20.586366
3482 22:13:20.586464 Set Vref, RX VrefLevel [Byte0]: 62
3483 22:13:20.589506 [Byte1]: 62
3484 22:13:20.594076
3485 22:13:20.594156 Set Vref, RX VrefLevel [Byte0]: 63
3486 22:13:20.597661 [Byte1]: 63
3487 22:13:20.602145
3488 22:13:20.602248 Set Vref, RX VrefLevel [Byte0]: 64
3489 22:13:20.605235 [Byte1]: 64
3490 22:13:20.609933
3491 22:13:20.610015 Set Vref, RX VrefLevel [Byte0]: 65
3492 22:13:20.613214 [Byte1]: 65
3493 22:13:20.617926
3494 22:13:20.618065 Set Vref, RX VrefLevel [Byte0]: 66
3495 22:13:20.621025 [Byte1]: 66
3496 22:13:20.625837
3497 22:13:20.625933 Set Vref, RX VrefLevel [Byte0]: 67
3498 22:13:20.629223 [Byte1]: 67
3499 22:13:20.633766
3500 22:13:20.633866 Set Vref, RX VrefLevel [Byte0]: 68
3501 22:13:20.636800 [Byte1]: 68
3502 22:13:20.641631
3503 22:13:20.641728 Final RX Vref Byte 0 = 48 to rank0
3504 22:13:20.644851 Final RX Vref Byte 1 = 57 to rank0
3505 22:13:20.648258 Final RX Vref Byte 0 = 48 to rank1
3506 22:13:20.651669 Final RX Vref Byte 1 = 57 to rank1==
3507 22:13:20.654606 Dram Type= 6, Freq= 0, CH_1, rank 0
3508 22:13:20.661292 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3509 22:13:20.661375 ==
3510 22:13:20.661442 DQS Delay:
3511 22:13:20.664589 DQS0 = 0, DQS1 = 0
3512 22:13:20.664661 DQM Delay:
3513 22:13:20.664722 DQM0 = 115, DQM1 = 111
3514 22:13:20.668250 DQ Delay:
3515 22:13:20.671101 DQ0 =118, DQ1 =110, DQ2 =108, DQ3 =112
3516 22:13:20.674568 DQ4 =114, DQ5 =126, DQ6 =124, DQ7 =114
3517 22:13:20.677750 DQ8 =100, DQ9 =102, DQ10 =116, DQ11 =100
3518 22:13:20.681154 DQ12 =118, DQ13 =120, DQ14 =120, DQ15 =118
3519 22:13:20.681237
3520 22:13:20.681335
3521 22:13:20.691284 [DQSOSCAuto] RK0, (LSB)MR18= 0x7fa, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 407 ps
3522 22:13:20.691367 CH1 RK0: MR19=403, MR18=7FA
3523 22:13:20.697662 CH1_RK0: MR19=0x403, MR18=0x7FA, DQSOSC=407, MR23=63, INC=39, DEC=26
3524 22:13:20.697748
3525 22:13:20.700961 ----->DramcWriteLeveling(PI) begin...
3526 22:13:20.701045 ==
3527 22:13:20.704501 Dram Type= 6, Freq= 0, CH_1, rank 1
3528 22:13:20.711174 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3529 22:13:20.711257 ==
3530 22:13:20.714356 Write leveling (Byte 0): 23 => 23
3531 22:13:20.714437 Write leveling (Byte 1): 27 => 27
3532 22:13:20.717777 DramcWriteLeveling(PI) end<-----
3533 22:13:20.717858
3534 22:13:20.717923 ==
3535 22:13:20.720847 Dram Type= 6, Freq= 0, CH_1, rank 1
3536 22:13:20.727819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3537 22:13:20.727902 ==
3538 22:13:20.731065 [Gating] SW mode calibration
3539 22:13:20.737450 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3540 22:13:20.741125 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3541 22:13:20.747594 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3542 22:13:20.750871 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3543 22:13:20.754352 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3544 22:13:20.760845 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3545 22:13:20.764106 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3546 22:13:20.767758 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3547 22:13:20.774212 0 15 24 | B1->B0 | 2a2a 3434 | 1 0 | (1 0) (0 1)
3548 22:13:20.777536 0 15 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 0)
3549 22:13:20.780533 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3550 22:13:20.787361 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3551 22:13:20.791031 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3552 22:13:20.794392 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3553 22:13:20.800642 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3554 22:13:20.803957 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3555 22:13:20.806970 1 0 24 | B1->B0 | 3c3c 2c2c | 0 1 | (0 0) (0 0)
3556 22:13:20.813700 1 0 28 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
3557 22:13:20.817265 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3558 22:13:20.820096 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3559 22:13:20.826915 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3560 22:13:20.830036 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3561 22:13:20.833975 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3562 22:13:20.840032 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3563 22:13:20.843322 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3564 22:13:20.846824 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3565 22:13:20.852927 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3566 22:13:20.856228 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3567 22:13:20.859875 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3568 22:13:20.866273 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3569 22:13:20.869948 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3570 22:13:20.873146 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3571 22:13:20.879947 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3572 22:13:20.882836 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3573 22:13:20.886050 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3574 22:13:20.892856 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3575 22:13:20.896628 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3576 22:13:20.899563 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3577 22:13:20.906285 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3578 22:13:20.909152 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3579 22:13:20.912479 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3580 22:13:20.919386 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3581 22:13:20.922274 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3582 22:13:20.925926 Total UI for P1: 0, mck2ui 16
3583 22:13:20.929414 best dqsien dly found for B0: ( 1, 3, 26)
3584 22:13:20.932272 Total UI for P1: 0, mck2ui 16
3585 22:13:20.935874 best dqsien dly found for B1: ( 1, 3, 26)
3586 22:13:20.939136 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3587 22:13:20.941974 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3588 22:13:20.942058
3589 22:13:20.945400 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3590 22:13:20.948867 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3591 22:13:20.952337 [Gating] SW calibration Done
3592 22:13:20.952439 ==
3593 22:13:20.955606 Dram Type= 6, Freq= 0, CH_1, rank 1
3594 22:13:20.958658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3595 22:13:20.962003 ==
3596 22:13:20.962110 RX Vref Scan: 0
3597 22:13:20.962202
3598 22:13:20.965504 RX Vref 0 -> 0, step: 1
3599 22:13:20.965585
3600 22:13:20.968427 RX Delay -40 -> 252, step: 8
3601 22:13:20.971758 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3602 22:13:20.975320 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3603 22:13:20.978932 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3604 22:13:20.981562 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3605 22:13:20.988180 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3606 22:13:20.991389 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3607 22:13:20.994664 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3608 22:13:20.998101 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3609 22:13:21.001510 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3610 22:13:21.008425 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3611 22:13:21.011840 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3612 22:13:21.014778 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3613 22:13:21.017886 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3614 22:13:21.021457 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3615 22:13:21.028271 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3616 22:13:21.031507 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3617 22:13:21.031589 ==
3618 22:13:21.034495 Dram Type= 6, Freq= 0, CH_1, rank 1
3619 22:13:21.038085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3620 22:13:21.038167 ==
3621 22:13:21.041235 DQS Delay:
3622 22:13:21.041317 DQS0 = 0, DQS1 = 0
3623 22:13:21.041382 DQM Delay:
3624 22:13:21.044569 DQM0 = 117, DQM1 = 110
3625 22:13:21.044650 DQ Delay:
3626 22:13:21.047752 DQ0 =123, DQ1 =111, DQ2 =107, DQ3 =111
3627 22:13:21.050795 DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =115
3628 22:13:21.057478 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =103
3629 22:13:21.060827 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3630 22:13:21.060909
3631 22:13:21.060972
3632 22:13:21.061032 ==
3633 22:13:21.064277 Dram Type= 6, Freq= 0, CH_1, rank 1
3634 22:13:21.067455 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3635 22:13:21.067537 ==
3636 22:13:21.067602
3637 22:13:21.067661
3638 22:13:21.070966 TX Vref Scan disable
3639 22:13:21.073944 == TX Byte 0 ==
3640 22:13:21.077222 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3641 22:13:21.080751 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3642 22:13:21.084073 == TX Byte 1 ==
3643 22:13:21.087520 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3644 22:13:21.090507 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3645 22:13:21.090588 ==
3646 22:13:21.093906 Dram Type= 6, Freq= 0, CH_1, rank 1
3647 22:13:21.097449 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3648 22:13:21.100459 ==
3649 22:13:21.110542 TX Vref=22, minBit 1, minWin=26, winSum=430
3650 22:13:21.114085 TX Vref=24, minBit 9, minWin=25, winSum=432
3651 22:13:21.117366 TX Vref=26, minBit 9, minWin=26, winSum=434
3652 22:13:21.120731 TX Vref=28, minBit 9, minWin=26, winSum=439
3653 22:13:21.123622 TX Vref=30, minBit 9, minWin=26, winSum=435
3654 22:13:21.130183 TX Vref=32, minBit 7, minWin=26, winSum=434
3655 22:13:21.133650 [TxChooseVref] Worse bit 9, Min win 26, Win sum 439, Final Vref 28
3656 22:13:21.133735
3657 22:13:21.137568 Final TX Range 1 Vref 28
3658 22:13:21.137650
3659 22:13:21.137716 ==
3660 22:13:21.139866 Dram Type= 6, Freq= 0, CH_1, rank 1
3661 22:13:21.143507 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3662 22:13:21.146377 ==
3663 22:13:21.146459
3664 22:13:21.146524
3665 22:13:21.146583 TX Vref Scan disable
3666 22:13:21.150478 == TX Byte 0 ==
3667 22:13:21.153428 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3668 22:13:21.160066 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3669 22:13:21.160149 == TX Byte 1 ==
3670 22:13:21.163521 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3671 22:13:21.170283 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3672 22:13:21.170366
3673 22:13:21.170430 [DATLAT]
3674 22:13:21.170490 Freq=1200, CH1 RK1
3675 22:13:21.170548
3676 22:13:21.173251 DATLAT Default: 0xd
3677 22:13:21.176513 0, 0xFFFF, sum = 0
3678 22:13:21.176596 1, 0xFFFF, sum = 0
3679 22:13:21.179954 2, 0xFFFF, sum = 0
3680 22:13:21.180038 3, 0xFFFF, sum = 0
3681 22:13:21.183442 4, 0xFFFF, sum = 0
3682 22:13:21.183525 5, 0xFFFF, sum = 0
3683 22:13:21.186713 6, 0xFFFF, sum = 0
3684 22:13:21.186797 7, 0xFFFF, sum = 0
3685 22:13:21.189723 8, 0xFFFF, sum = 0
3686 22:13:21.189806 9, 0xFFFF, sum = 0
3687 22:13:21.193204 10, 0xFFFF, sum = 0
3688 22:13:21.193288 11, 0xFFFF, sum = 0
3689 22:13:21.196666 12, 0x0, sum = 1
3690 22:13:21.196750 13, 0x0, sum = 2
3691 22:13:21.199655 14, 0x0, sum = 3
3692 22:13:21.199738 15, 0x0, sum = 4
3693 22:13:21.203464 best_step = 13
3694 22:13:21.203546
3695 22:13:21.203610 ==
3696 22:13:21.206743 Dram Type= 6, Freq= 0, CH_1, rank 1
3697 22:13:21.209760 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3698 22:13:21.209843 ==
3699 22:13:21.212948 RX Vref Scan: 0
3700 22:13:21.213031
3701 22:13:21.213128 RX Vref 0 -> 0, step: 1
3702 22:13:21.213190
3703 22:13:21.216384 RX Delay -21 -> 252, step: 4
3704 22:13:21.222878 iDelay=199, Bit 0, Center 118 (51 ~ 186) 136
3705 22:13:21.226103 iDelay=199, Bit 1, Center 112 (47 ~ 178) 132
3706 22:13:21.229408 iDelay=199, Bit 2, Center 106 (43 ~ 170) 128
3707 22:13:21.232606 iDelay=199, Bit 3, Center 112 (47 ~ 178) 132
3708 22:13:21.235664 iDelay=199, Bit 4, Center 114 (47 ~ 182) 136
3709 22:13:21.242885 iDelay=199, Bit 5, Center 128 (63 ~ 194) 132
3710 22:13:21.246129 iDelay=199, Bit 6, Center 130 (63 ~ 198) 136
3711 22:13:21.249374 iDelay=199, Bit 7, Center 114 (47 ~ 182) 136
3712 22:13:21.252667 iDelay=199, Bit 8, Center 100 (35 ~ 166) 132
3713 22:13:21.255623 iDelay=199, Bit 9, Center 100 (35 ~ 166) 132
3714 22:13:21.262608 iDelay=199, Bit 10, Center 112 (47 ~ 178) 132
3715 22:13:21.265750 iDelay=199, Bit 11, Center 100 (35 ~ 166) 132
3716 22:13:21.269002 iDelay=199, Bit 12, Center 120 (55 ~ 186) 132
3717 22:13:21.272854 iDelay=199, Bit 13, Center 118 (51 ~ 186) 136
3718 22:13:21.279611 iDelay=199, Bit 14, Center 118 (51 ~ 186) 136
3719 22:13:21.282813 iDelay=199, Bit 15, Center 120 (51 ~ 190) 140
3720 22:13:21.282899 ==
3721 22:13:21.285558 Dram Type= 6, Freq= 0, CH_1, rank 1
3722 22:13:21.289297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3723 22:13:21.289380 ==
3724 22:13:21.292428 DQS Delay:
3725 22:13:21.292511 DQS0 = 0, DQS1 = 0
3726 22:13:21.292576 DQM Delay:
3727 22:13:21.295667 DQM0 = 116, DQM1 = 111
3728 22:13:21.295749 DQ Delay:
3729 22:13:21.298884 DQ0 =118, DQ1 =112, DQ2 =106, DQ3 =112
3730 22:13:21.302083 DQ4 =114, DQ5 =128, DQ6 =130, DQ7 =114
3731 22:13:21.305415 DQ8 =100, DQ9 =100, DQ10 =112, DQ11 =100
3732 22:13:21.311936 DQ12 =120, DQ13 =118, DQ14 =118, DQ15 =120
3733 22:13:21.312018
3734 22:13:21.312083
3735 22:13:21.318930 [DQSOSCAuto] RK1, (LSB)MR18= 0xf3ed, (MSB)MR19= 0x303, tDQSOscB0 = 417 ps tDQSOscB1 = 415 ps
3736 22:13:21.322008 CH1 RK1: MR19=303, MR18=F3ED
3737 22:13:21.328501 CH1_RK1: MR19=0x303, MR18=0xF3ED, DQSOSC=415, MR23=63, INC=38, DEC=25
3738 22:13:21.332049 [RxdqsGatingPostProcess] freq 1200
3739 22:13:21.335049 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3740 22:13:21.338289 best DQS0 dly(2T, 0.5T) = (0, 11)
3741 22:13:21.341783 best DQS1 dly(2T, 0.5T) = (0, 11)
3742 22:13:21.344687 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3743 22:13:21.348197 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3744 22:13:21.351947 best DQS0 dly(2T, 0.5T) = (0, 11)
3745 22:13:21.354898 best DQS1 dly(2T, 0.5T) = (0, 11)
3746 22:13:21.358103 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3747 22:13:21.361550 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3748 22:13:21.365076 Pre-setting of DQS Precalculation
3749 22:13:21.368018 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3750 22:13:21.378142 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3751 22:13:21.384493 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3752 22:13:21.384576
3753 22:13:21.384642
3754 22:13:21.387889 [Calibration Summary] 2400 Mbps
3755 22:13:21.387972 CH 0, Rank 0
3756 22:13:21.390961 SW Impedance : PASS
3757 22:13:21.394538 DUTY Scan : NO K
3758 22:13:21.394621 ZQ Calibration : PASS
3759 22:13:21.397526 Jitter Meter : NO K
3760 22:13:21.397609 CBT Training : PASS
3761 22:13:21.401288 Write leveling : PASS
3762 22:13:21.404847 RX DQS gating : PASS
3763 22:13:21.404929 RX DQ/DQS(RDDQC) : PASS
3764 22:13:21.407814 TX DQ/DQS : PASS
3765 22:13:21.410950 RX DATLAT : PASS
3766 22:13:21.411032 RX DQ/DQS(Engine): PASS
3767 22:13:21.414151 TX OE : NO K
3768 22:13:21.414234 All Pass.
3769 22:13:21.414299
3770 22:13:21.417543 CH 0, Rank 1
3771 22:13:21.417625 SW Impedance : PASS
3772 22:13:21.421484 DUTY Scan : NO K
3773 22:13:21.424071 ZQ Calibration : PASS
3774 22:13:21.424154 Jitter Meter : NO K
3775 22:13:21.427695 CBT Training : PASS
3776 22:13:21.430779 Write leveling : PASS
3777 22:13:21.430860 RX DQS gating : PASS
3778 22:13:21.434311 RX DQ/DQS(RDDQC) : PASS
3779 22:13:21.437698 TX DQ/DQS : PASS
3780 22:13:21.437780 RX DATLAT : PASS
3781 22:13:21.440801 RX DQ/DQS(Engine): PASS
3782 22:13:21.443697 TX OE : NO K
3783 22:13:21.443780 All Pass.
3784 22:13:21.443845
3785 22:13:21.443905 CH 1, Rank 0
3786 22:13:21.447191 SW Impedance : PASS
3787 22:13:21.451176 DUTY Scan : NO K
3788 22:13:21.451259 ZQ Calibration : PASS
3789 22:13:21.453698 Jitter Meter : NO K
3790 22:13:21.457032 CBT Training : PASS
3791 22:13:21.457115 Write leveling : PASS
3792 22:13:21.460549 RX DQS gating : PASS
3793 22:13:21.463816 RX DQ/DQS(RDDQC) : PASS
3794 22:13:21.463898 TX DQ/DQS : PASS
3795 22:13:21.467301 RX DATLAT : PASS
3796 22:13:21.470293 RX DQ/DQS(Engine): PASS
3797 22:13:21.470401 TX OE : NO K
3798 22:13:21.470495 All Pass.
3799 22:13:21.473318
3800 22:13:21.473400 CH 1, Rank 1
3801 22:13:21.476966 SW Impedance : PASS
3802 22:13:21.477049 DUTY Scan : NO K
3803 22:13:21.480295 ZQ Calibration : PASS
3804 22:13:21.480378 Jitter Meter : NO K
3805 22:13:21.483509 CBT Training : PASS
3806 22:13:21.486904 Write leveling : PASS
3807 22:13:21.486987 RX DQS gating : PASS
3808 22:13:21.490236 RX DQ/DQS(RDDQC) : PASS
3809 22:13:21.493873 TX DQ/DQS : PASS
3810 22:13:21.493955 RX DATLAT : PASS
3811 22:13:21.496680 RX DQ/DQS(Engine): PASS
3812 22:13:21.499981 TX OE : NO K
3813 22:13:21.500063 All Pass.
3814 22:13:21.500128
3815 22:13:21.503178 DramC Write-DBI off
3816 22:13:21.503260 PER_BANK_REFRESH: Hybrid Mode
3817 22:13:21.506852 TX_TRACKING: ON
3818 22:13:21.516405 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3819 22:13:21.519796 [FAST_K] Save calibration result to emmc
3820 22:13:21.523256 dramc_set_vcore_voltage set vcore to 650000
3821 22:13:21.523342 Read voltage for 600, 5
3822 22:13:21.526168 Vio18 = 0
3823 22:13:21.526250 Vcore = 650000
3824 22:13:21.526316 Vdram = 0
3825 22:13:21.529386 Vddq = 0
3826 22:13:21.529468 Vmddr = 0
3827 22:13:21.536190 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3828 22:13:21.539506 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3829 22:13:21.542821 MEM_TYPE=3, freq_sel=19
3830 22:13:21.546158 sv_algorithm_assistance_LP4_1600
3831 22:13:21.549400 ============ PULL DRAM RESETB DOWN ============
3832 22:13:21.552554 ========== PULL DRAM RESETB DOWN end =========
3833 22:13:21.559243 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3834 22:13:21.562832 ===================================
3835 22:13:21.562914 LPDDR4 DRAM CONFIGURATION
3836 22:13:21.565998 ===================================
3837 22:13:21.568976 EX_ROW_EN[0] = 0x0
3838 22:13:21.572522 EX_ROW_EN[1] = 0x0
3839 22:13:21.572605 LP4Y_EN = 0x0
3840 22:13:21.575949 WORK_FSP = 0x0
3841 22:13:21.576032 WL = 0x2
3842 22:13:21.579023 RL = 0x2
3843 22:13:21.579146 BL = 0x2
3844 22:13:21.582270 RPST = 0x0
3845 22:13:21.582353 RD_PRE = 0x0
3846 22:13:21.585894 WR_PRE = 0x1
3847 22:13:21.585976 WR_PST = 0x0
3848 22:13:21.589078 DBI_WR = 0x0
3849 22:13:21.589160 DBI_RD = 0x0
3850 22:13:21.592518 OTF = 0x1
3851 22:13:21.595736 ===================================
3852 22:13:21.598963 ===================================
3853 22:13:21.599046 ANA top config
3854 22:13:21.602269 ===================================
3855 22:13:21.605492 DLL_ASYNC_EN = 0
3856 22:13:21.608871 ALL_SLAVE_EN = 1
3857 22:13:21.612635 NEW_RANK_MODE = 1
3858 22:13:21.612718 DLL_IDLE_MODE = 1
3859 22:13:21.615394 LP45_APHY_COMB_EN = 1
3860 22:13:21.618934 TX_ODT_DIS = 1
3861 22:13:21.622006 NEW_8X_MODE = 1
3862 22:13:21.625793 ===================================
3863 22:13:21.628467 ===================================
3864 22:13:21.632328 data_rate = 1200
3865 22:13:21.632411 CKR = 1
3866 22:13:21.635726 DQ_P2S_RATIO = 8
3867 22:13:21.638417 ===================================
3868 22:13:21.642108 CA_P2S_RATIO = 8
3869 22:13:21.645083 DQ_CA_OPEN = 0
3870 22:13:21.648191 DQ_SEMI_OPEN = 0
3871 22:13:21.651784 CA_SEMI_OPEN = 0
3872 22:13:21.651866 CA_FULL_RATE = 0
3873 22:13:21.655535 DQ_CKDIV4_EN = 1
3874 22:13:21.659208 CA_CKDIV4_EN = 1
3875 22:13:21.661428 CA_PREDIV_EN = 0
3876 22:13:21.664820 PH8_DLY = 0
3877 22:13:21.668375 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3878 22:13:21.668457 DQ_AAMCK_DIV = 4
3879 22:13:21.671824 CA_AAMCK_DIV = 4
3880 22:13:21.674579 CA_ADMCK_DIV = 4
3881 22:13:21.677851 DQ_TRACK_CA_EN = 0
3882 22:13:21.681562 CA_PICK = 600
3883 22:13:21.684503 CA_MCKIO = 600
3884 22:13:21.688213 MCKIO_SEMI = 0
3885 22:13:21.691333 PLL_FREQ = 2288
3886 22:13:21.691415 DQ_UI_PI_RATIO = 32
3887 22:13:21.694563 CA_UI_PI_RATIO = 0
3888 22:13:21.697882 ===================================
3889 22:13:21.701208 ===================================
3890 22:13:21.704505 memory_type:LPDDR4
3891 22:13:21.707888 GP_NUM : 10
3892 22:13:21.707971 SRAM_EN : 1
3893 22:13:21.711011 MD32_EN : 0
3894 22:13:21.714660 ===================================
3895 22:13:21.714742 [ANA_INIT] >>>>>>>>>>>>>>
3896 22:13:21.717569 <<<<<< [CONFIGURE PHASE]: ANA_TX
3897 22:13:21.721368 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3898 22:13:21.724230 ===================================
3899 22:13:21.727468 data_rate = 1200,PCW = 0X5800
3900 22:13:21.731113 ===================================
3901 22:13:21.734008 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3902 22:13:21.740645 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3903 22:13:21.747622 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3904 22:13:21.750770 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3905 22:13:21.754222 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3906 22:13:21.757283 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3907 22:13:21.760680 [ANA_INIT] flow start
3908 22:13:21.760767 [ANA_INIT] PLL >>>>>>>>
3909 22:13:21.764019 [ANA_INIT] PLL <<<<<<<<
3910 22:13:21.767180 [ANA_INIT] MIDPI >>>>>>>>
3911 22:13:21.770480 [ANA_INIT] MIDPI <<<<<<<<
3912 22:13:21.770562 [ANA_INIT] DLL >>>>>>>>
3913 22:13:21.773563 [ANA_INIT] flow end
3914 22:13:21.777132 ============ LP4 DIFF to SE enter ============
3915 22:13:21.780489 ============ LP4 DIFF to SE exit ============
3916 22:13:21.784008 [ANA_INIT] <<<<<<<<<<<<<
3917 22:13:21.786901 [Flow] Enable top DCM control >>>>>
3918 22:13:21.790054 [Flow] Enable top DCM control <<<<<
3919 22:13:21.793720 Enable DLL master slave shuffle
3920 22:13:21.800193 ==============================================================
3921 22:13:21.800276 Gating Mode config
3922 22:13:21.806972 ==============================================================
3923 22:13:21.807076 Config description:
3924 22:13:21.816824 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3925 22:13:21.823708 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3926 22:13:21.829948 SELPH_MODE 0: By rank 1: By Phase
3927 22:13:21.832908 ==============================================================
3928 22:13:21.836697 GAT_TRACK_EN = 1
3929 22:13:21.839846 RX_GATING_MODE = 2
3930 22:13:21.842929 RX_GATING_TRACK_MODE = 2
3931 22:13:21.846715 SELPH_MODE = 1
3932 22:13:21.849842 PICG_EARLY_EN = 1
3933 22:13:21.853049 VALID_LAT_VALUE = 1
3934 22:13:21.859632 ==============================================================
3935 22:13:21.862943 Enter into Gating configuration >>>>
3936 22:13:21.866449 Exit from Gating configuration <<<<
3937 22:13:21.869807 Enter into DVFS_PRE_config >>>>>
3938 22:13:21.879476 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3939 22:13:21.882527 Exit from DVFS_PRE_config <<<<<
3940 22:13:21.885691 Enter into PICG configuration >>>>
3941 22:13:21.889814 Exit from PICG configuration <<<<
3942 22:13:21.892314 [RX_INPUT] configuration >>>>>
3943 22:13:21.892396 [RX_INPUT] configuration <<<<<
3944 22:13:21.899180 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3945 22:13:21.905796 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3946 22:13:21.909076 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3947 22:13:21.915571 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3948 22:13:21.922936 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3949 22:13:21.928627 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3950 22:13:21.932289 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3951 22:13:21.935603 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3952 22:13:21.942101 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3953 22:13:21.945114 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3954 22:13:21.948702 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3955 22:13:21.955045 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3956 22:13:21.958174 ===================================
3957 22:13:21.958257 LPDDR4 DRAM CONFIGURATION
3958 22:13:21.961625 ===================================
3959 22:13:21.964953 EX_ROW_EN[0] = 0x0
3960 22:13:21.968239 EX_ROW_EN[1] = 0x0
3961 22:13:21.968322 LP4Y_EN = 0x0
3962 22:13:21.971435 WORK_FSP = 0x0
3963 22:13:21.971517 WL = 0x2
3964 22:13:21.974819 RL = 0x2
3965 22:13:21.974902 BL = 0x2
3966 22:13:21.977915 RPST = 0x0
3967 22:13:21.977997 RD_PRE = 0x0
3968 22:13:21.981643 WR_PRE = 0x1
3969 22:13:21.981726 WR_PST = 0x0
3970 22:13:21.984952 DBI_WR = 0x0
3971 22:13:21.985034 DBI_RD = 0x0
3972 22:13:21.988099 OTF = 0x1
3973 22:13:21.991831 ===================================
3974 22:13:21.994849 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3975 22:13:21.997918 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3976 22:13:22.004405 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3977 22:13:22.007726 ===================================
3978 22:13:22.007809 LPDDR4 DRAM CONFIGURATION
3979 22:13:22.011372 ===================================
3980 22:13:22.014386 EX_ROW_EN[0] = 0x10
3981 22:13:22.017782 EX_ROW_EN[1] = 0x0
3982 22:13:22.017864 LP4Y_EN = 0x0
3983 22:13:22.021111 WORK_FSP = 0x0
3984 22:13:22.021193 WL = 0x2
3985 22:13:22.024404 RL = 0x2
3986 22:13:22.024486 BL = 0x2
3987 22:13:22.027470 RPST = 0x0
3988 22:13:22.027553 RD_PRE = 0x0
3989 22:13:22.031144 WR_PRE = 0x1
3990 22:13:22.031227 WR_PST = 0x0
3991 22:13:22.034378 DBI_WR = 0x0
3992 22:13:22.034460 DBI_RD = 0x0
3993 22:13:22.037353 OTF = 0x1
3994 22:13:22.040866 ===================================
3995 22:13:22.047614 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3996 22:13:22.050955 nWR fixed to 30
3997 22:13:22.054147 [ModeRegInit_LP4] CH0 RK0
3998 22:13:22.054229 [ModeRegInit_LP4] CH0 RK1
3999 22:13:22.057526 [ModeRegInit_LP4] CH1 RK0
4000 22:13:22.060755 [ModeRegInit_LP4] CH1 RK1
4001 22:13:22.060835 match AC timing 17
4002 22:13:22.067169 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
4003 22:13:22.070207 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4004 22:13:22.073976 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
4005 22:13:22.080908 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
4006 22:13:22.083427 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
4007 22:13:22.083508 ==
4008 22:13:22.087177 Dram Type= 6, Freq= 0, CH_0, rank 0
4009 22:13:22.090171 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4010 22:13:22.090253 ==
4011 22:13:22.096883 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4012 22:13:22.103748 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4013 22:13:22.107120 [CA 0] Center 36 (6~66) winsize 61
4014 22:13:22.110071 [CA 1] Center 36 (6~66) winsize 61
4015 22:13:22.113546 [CA 2] Center 34 (3~65) winsize 63
4016 22:13:22.116527 [CA 3] Center 34 (4~65) winsize 62
4017 22:13:22.120241 [CA 4] Center 33 (3~64) winsize 62
4018 22:13:22.123565 [CA 5] Center 33 (3~64) winsize 62
4019 22:13:22.123646
4020 22:13:22.126596 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4021 22:13:22.126677
4022 22:13:22.129700 [CATrainingPosCal] consider 1 rank data
4023 22:13:22.133147 u2DelayCellTimex100 = 270/100 ps
4024 22:13:22.136340 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4025 22:13:22.139568 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4026 22:13:22.143086 CA2 delay=34 (3~65),Diff = 1 PI (9 cell)
4027 22:13:22.146264 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4028 22:13:22.152723 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4029 22:13:22.156212 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4030 22:13:22.156292
4031 22:13:22.159593 CA PerBit enable=1, Macro0, CA PI delay=33
4032 22:13:22.159674
4033 22:13:22.162597 [CBTSetCACLKResult] CA Dly = 33
4034 22:13:22.162677 CS Dly: 6 (0~37)
4035 22:13:22.162745 ==
4036 22:13:22.166287 Dram Type= 6, Freq= 0, CH_0, rank 1
4037 22:13:22.172649 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4038 22:13:22.172731 ==
4039 22:13:22.175709 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4040 22:13:22.182616 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4041 22:13:22.185867 [CA 0] Center 36 (6~66) winsize 61
4042 22:13:22.189097 [CA 1] Center 36 (6~66) winsize 61
4043 22:13:22.192294 [CA 2] Center 33 (3~64) winsize 62
4044 22:13:22.195646 [CA 3] Center 33 (3~64) winsize 62
4045 22:13:22.198783 [CA 4] Center 33 (3~64) winsize 62
4046 22:13:22.202458 [CA 5] Center 33 (2~64) winsize 63
4047 22:13:22.202539
4048 22:13:22.205675 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4049 22:13:22.205755
4050 22:13:22.208611 [CATrainingPosCal] consider 2 rank data
4051 22:13:22.212024 u2DelayCellTimex100 = 270/100 ps
4052 22:13:22.215547 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4053 22:13:22.222178 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4054 22:13:22.225340 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4055 22:13:22.228879 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4056 22:13:22.231893 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4057 22:13:22.235451 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4058 22:13:22.235532
4059 22:13:22.238853 CA PerBit enable=1, Macro0, CA PI delay=33
4060 22:13:22.238934
4061 22:13:22.242025 [CBTSetCACLKResult] CA Dly = 33
4062 22:13:22.245029 CS Dly: 6 (0~37)
4063 22:13:22.245111
4064 22:13:22.248582 ----->DramcWriteLeveling(PI) begin...
4065 22:13:22.248666 ==
4066 22:13:22.252078 Dram Type= 6, Freq= 0, CH_0, rank 0
4067 22:13:22.254941 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4068 22:13:22.255024 ==
4069 22:13:22.258155 Write leveling (Byte 0): 33 => 33
4070 22:13:22.261783 Write leveling (Byte 1): 29 => 29
4071 22:13:22.265172 DramcWriteLeveling(PI) end<-----
4072 22:13:22.265254
4073 22:13:22.265319 ==
4074 22:13:22.268496 Dram Type= 6, Freq= 0, CH_0, rank 0
4075 22:13:22.271606 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4076 22:13:22.271688 ==
4077 22:13:22.274939 [Gating] SW mode calibration
4078 22:13:22.281625 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4079 22:13:22.288066 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4080 22:13:22.291422 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4081 22:13:22.294681 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4082 22:13:22.301473 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4083 22:13:22.304659 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4084 22:13:22.307703 0 9 16 | B1->B0 | 2f2f 2828 | 1 1 | (1 0) (0 0)
4085 22:13:22.315024 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4086 22:13:22.317886 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4087 22:13:22.321144 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4088 22:13:22.327739 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4089 22:13:22.331170 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4090 22:13:22.334224 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4091 22:13:22.340769 0 10 12 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
4092 22:13:22.343937 0 10 16 | B1->B0 | 3737 4141 | 0 0 | (0 0) (0 0)
4093 22:13:22.347704 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4094 22:13:22.354014 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4095 22:13:22.357320 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4096 22:13:22.360681 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4097 22:13:22.367520 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4098 22:13:22.370308 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4099 22:13:22.373843 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4100 22:13:22.380612 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4101 22:13:22.383851 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4102 22:13:22.387399 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4103 22:13:22.393465 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4104 22:13:22.397237 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4105 22:13:22.400252 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4106 22:13:22.406756 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4107 22:13:22.410058 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4108 22:13:22.413870 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4109 22:13:22.420502 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4110 22:13:22.423032 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4111 22:13:22.427096 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4112 22:13:22.433134 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4113 22:13:22.436287 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4114 22:13:22.439923 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4115 22:13:22.446298 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4116 22:13:22.449966 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4117 22:13:22.453317 Total UI for P1: 0, mck2ui 16
4118 22:13:22.457133 best dqsien dly found for B0: ( 0, 13, 12)
4119 22:13:22.459520 Total UI for P1: 0, mck2ui 16
4120 22:13:22.463009 best dqsien dly found for B1: ( 0, 13, 14)
4121 22:13:22.466127 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4122 22:13:22.469763 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4123 22:13:22.469871
4124 22:13:22.472708 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4125 22:13:22.475958 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4126 22:13:22.479348 [Gating] SW calibration Done
4127 22:13:22.479433 ==
4128 22:13:22.483040 Dram Type= 6, Freq= 0, CH_0, rank 0
4129 22:13:22.489240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4130 22:13:22.489326 ==
4131 22:13:22.489412 RX Vref Scan: 0
4132 22:13:22.489493
4133 22:13:22.492782 RX Vref 0 -> 0, step: 1
4134 22:13:22.492868
4135 22:13:22.496090 RX Delay -230 -> 252, step: 16
4136 22:13:22.499537 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4137 22:13:22.502838 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4138 22:13:22.506141 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4139 22:13:22.512790 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4140 22:13:22.515913 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4141 22:13:22.519012 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4142 22:13:22.522518 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4143 22:13:22.528932 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4144 22:13:22.532493 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4145 22:13:22.535506 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4146 22:13:22.538897 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4147 22:13:22.542395 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4148 22:13:22.549109 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4149 22:13:22.552540 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4150 22:13:22.555483 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4151 22:13:22.558965 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4152 22:13:22.562232 ==
4153 22:13:22.565513 Dram Type= 6, Freq= 0, CH_0, rank 0
4154 22:13:22.568408 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4155 22:13:22.568509 ==
4156 22:13:22.568573 DQS Delay:
4157 22:13:22.571900 DQS0 = 0, DQS1 = 0
4158 22:13:22.571971 DQM Delay:
4159 22:13:22.575162 DQM0 = 42, DQM1 = 30
4160 22:13:22.575257 DQ Delay:
4161 22:13:22.578293 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4162 22:13:22.582004 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49
4163 22:13:22.585097 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4164 22:13:22.588283 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4165 22:13:22.588353
4166 22:13:22.588439
4167 22:13:22.588513 ==
4168 22:13:22.591714 Dram Type= 6, Freq= 0, CH_0, rank 0
4169 22:13:22.594766 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4170 22:13:22.594875 ==
4171 22:13:22.598290
4172 22:13:22.598371
4173 22:13:22.598435 TX Vref Scan disable
4174 22:13:22.601577 == TX Byte 0 ==
4175 22:13:22.605042 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4176 22:13:22.607954 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4177 22:13:22.611492 == TX Byte 1 ==
4178 22:13:22.614932 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4179 22:13:22.618063 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4180 22:13:22.621325 ==
4181 22:13:22.621406 Dram Type= 6, Freq= 0, CH_0, rank 0
4182 22:13:22.628105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4183 22:13:22.628188 ==
4184 22:13:22.628252
4185 22:13:22.628310
4186 22:13:22.631800 TX Vref Scan disable
4187 22:13:22.631881 == TX Byte 0 ==
4188 22:13:22.637875 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4189 22:13:22.641212 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4190 22:13:22.641294 == TX Byte 1 ==
4191 22:13:22.648062 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4192 22:13:22.651029 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4193 22:13:22.651153
4194 22:13:22.651219 [DATLAT]
4195 22:13:22.654787 Freq=600, CH0 RK0
4196 22:13:22.654869
4197 22:13:22.654934 DATLAT Default: 0x9
4198 22:13:22.657675 0, 0xFFFF, sum = 0
4199 22:13:22.657759 1, 0xFFFF, sum = 0
4200 22:13:22.661122 2, 0xFFFF, sum = 0
4201 22:13:22.664569 3, 0xFFFF, sum = 0
4202 22:13:22.664652 4, 0xFFFF, sum = 0
4203 22:13:22.667982 5, 0xFFFF, sum = 0
4204 22:13:22.668065 6, 0xFFFF, sum = 0
4205 22:13:22.670835 7, 0xFFFF, sum = 0
4206 22:13:22.670918 8, 0x0, sum = 1
4207 22:13:22.674401 9, 0x0, sum = 2
4208 22:13:22.674485 10, 0x0, sum = 3
4209 22:13:22.674551 11, 0x0, sum = 4
4210 22:13:22.677693 best_step = 9
4211 22:13:22.677775
4212 22:13:22.677840 ==
4213 22:13:22.680884 Dram Type= 6, Freq= 0, CH_0, rank 0
4214 22:13:22.684233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4215 22:13:22.684315 ==
4216 22:13:22.687308 RX Vref Scan: 1
4217 22:13:22.687390
4218 22:13:22.690503 RX Vref 0 -> 0, step: 1
4219 22:13:22.690585
4220 22:13:22.690649 RX Delay -195 -> 252, step: 8
4221 22:13:22.690711
4222 22:13:22.693623 Set Vref, RX VrefLevel [Byte0]: 61
4223 22:13:22.697459 [Byte1]: 51
4224 22:13:22.701484
4225 22:13:22.701566 Final RX Vref Byte 0 = 61 to rank0
4226 22:13:22.704968 Final RX Vref Byte 1 = 51 to rank0
4227 22:13:22.708506 Final RX Vref Byte 0 = 61 to rank1
4228 22:13:22.711543 Final RX Vref Byte 1 = 51 to rank1==
4229 22:13:22.714803 Dram Type= 6, Freq= 0, CH_0, rank 0
4230 22:13:22.721579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4231 22:13:22.721662 ==
4232 22:13:22.721728 DQS Delay:
4233 22:13:22.724857 DQS0 = 0, DQS1 = 0
4234 22:13:22.724943 DQM Delay:
4235 22:13:22.725009 DQM0 = 44, DQM1 = 32
4236 22:13:22.728071 DQ Delay:
4237 22:13:22.731430 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =44
4238 22:13:22.734782 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =52
4239 22:13:22.738055 DQ8 =24, DQ9 =20, DQ10 =32, DQ11 =24
4240 22:13:22.741828 DQ12 =36, DQ13 =36, DQ14 =44, DQ15 =40
4241 22:13:22.741910
4242 22:13:22.741976
4243 22:13:22.748226 [DQSOSCAuto] RK0, (LSB)MR18= 0x6d44, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 389 ps
4244 22:13:22.751346 CH0 RK0: MR19=808, MR18=6D44
4245 22:13:22.757950 CH0_RK0: MR19=0x808, MR18=0x6D44, DQSOSC=389, MR23=63, INC=173, DEC=115
4246 22:13:22.758038
4247 22:13:22.761410 ----->DramcWriteLeveling(PI) begin...
4248 22:13:22.761494 ==
4249 22:13:22.764716 Dram Type= 6, Freq= 0, CH_0, rank 1
4250 22:13:22.768228 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4251 22:13:22.768312 ==
4252 22:13:22.770889 Write leveling (Byte 0): 33 => 33
4253 22:13:22.774530 Write leveling (Byte 1): 29 => 29
4254 22:13:22.778059 DramcWriteLeveling(PI) end<-----
4255 22:13:22.778141
4256 22:13:22.778206 ==
4257 22:13:22.781211 Dram Type= 6, Freq= 0, CH_0, rank 1
4258 22:13:22.784363 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4259 22:13:22.784446 ==
4260 22:13:22.787493 [Gating] SW mode calibration
4261 22:13:22.794510 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4262 22:13:22.800617 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4263 22:13:22.804049 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4264 22:13:22.810843 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4265 22:13:22.814304 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4266 22:13:22.817500 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4267 22:13:22.824073 0 9 16 | B1->B0 | 2d2d 2424 | 1 0 | (1 0) (0 0)
4268 22:13:22.827824 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4269 22:13:22.830455 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4270 22:13:22.837006 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4271 22:13:22.840576 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4272 22:13:22.844316 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4273 22:13:22.850601 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4274 22:13:22.853583 0 10 12 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
4275 22:13:22.857089 0 10 16 | B1->B0 | 3e3e 4343 | 0 0 | (0 0) (0 0)
4276 22:13:22.863497 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4277 22:13:22.867200 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4278 22:13:22.870286 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4279 22:13:22.877017 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4280 22:13:22.880466 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4281 22:13:22.883819 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4282 22:13:22.890816 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4283 22:13:22.893884 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4284 22:13:22.897130 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4285 22:13:22.903650 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4286 22:13:22.906676 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4287 22:13:22.909985 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4288 22:13:22.916749 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4289 22:13:22.920599 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4290 22:13:22.923046 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4291 22:13:22.929976 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4292 22:13:22.932807 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4293 22:13:22.936203 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4294 22:13:22.943040 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4295 22:13:22.946163 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4296 22:13:22.949443 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4297 22:13:22.956181 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4298 22:13:22.959305 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4299 22:13:22.962606 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4300 22:13:22.965903 Total UI for P1: 0, mck2ui 16
4301 22:13:22.969362 best dqsien dly found for B0: ( 0, 13, 14)
4302 22:13:22.972425 Total UI for P1: 0, mck2ui 16
4303 22:13:22.975956 best dqsien dly found for B1: ( 0, 13, 14)
4304 22:13:22.979360 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4305 22:13:22.982513 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4306 22:13:22.982619
4307 22:13:22.988982 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4308 22:13:22.992584 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4309 22:13:22.992686 [Gating] SW calibration Done
4310 22:13:22.995602 ==
4311 22:13:22.998873 Dram Type= 6, Freq= 0, CH_0, rank 1
4312 22:13:23.001895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4313 22:13:23.001969 ==
4314 22:13:23.002032 RX Vref Scan: 0
4315 22:13:23.002090
4316 22:13:23.005725 RX Vref 0 -> 0, step: 1
4317 22:13:23.005794
4318 22:13:23.009161 RX Delay -230 -> 252, step: 16
4319 22:13:23.012159 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4320 22:13:23.015536 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4321 22:13:23.022202 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4322 22:13:23.025502 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4323 22:13:23.028473 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4324 22:13:23.032370 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4325 22:13:23.038862 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4326 22:13:23.041728 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4327 22:13:23.045017 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4328 22:13:23.048118 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4329 22:13:23.055234 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4330 22:13:23.058266 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4331 22:13:23.061484 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4332 22:13:23.064634 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4333 22:13:23.071694 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4334 22:13:23.074877 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4335 22:13:23.074953 ==
4336 22:13:23.078308 Dram Type= 6, Freq= 0, CH_0, rank 1
4337 22:13:23.081680 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4338 22:13:23.081763 ==
4339 22:13:23.081828 DQS Delay:
4340 22:13:23.085287 DQS0 = 0, DQS1 = 0
4341 22:13:23.085370 DQM Delay:
4342 22:13:23.088083 DQM0 = 42, DQM1 = 35
4343 22:13:23.088194 DQ Delay:
4344 22:13:23.091552 DQ0 =41, DQ1 =49, DQ2 =33, DQ3 =41
4345 22:13:23.094806 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4346 22:13:23.098075 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =33
4347 22:13:23.101593 DQ12 =41, DQ13 =49, DQ14 =49, DQ15 =41
4348 22:13:23.101699
4349 22:13:23.101790
4350 22:13:23.101881 ==
4351 22:13:23.104629 Dram Type= 6, Freq= 0, CH_0, rank 1
4352 22:13:23.111082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4353 22:13:23.111157 ==
4354 22:13:23.111220
4355 22:13:23.111279
4356 22:13:23.111349 TX Vref Scan disable
4357 22:13:23.114988 == TX Byte 0 ==
4358 22:13:23.118095 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4359 22:13:23.124445 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4360 22:13:23.124544 == TX Byte 1 ==
4361 22:13:23.128261 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4362 22:13:23.134425 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4363 22:13:23.134497 ==
4364 22:13:23.138019 Dram Type= 6, Freq= 0, CH_0, rank 1
4365 22:13:23.141037 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4366 22:13:23.141106 ==
4367 22:13:23.141165
4368 22:13:23.141221
4369 22:13:23.144319 TX Vref Scan disable
4370 22:13:23.147582 == TX Byte 0 ==
4371 22:13:23.150915 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4372 22:13:23.154273 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4373 22:13:23.157649 == TX Byte 1 ==
4374 22:13:23.160795 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4375 22:13:23.164793 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4376 22:13:23.164888
4377 22:13:23.164952 [DATLAT]
4378 22:13:23.167624 Freq=600, CH0 RK1
4379 22:13:23.167698
4380 22:13:23.170926 DATLAT Default: 0x9
4381 22:13:23.171024 0, 0xFFFF, sum = 0
4382 22:13:23.173935 1, 0xFFFF, sum = 0
4383 22:13:23.174049 2, 0xFFFF, sum = 0
4384 22:13:23.177491 3, 0xFFFF, sum = 0
4385 22:13:23.177600 4, 0xFFFF, sum = 0
4386 22:13:23.180496 5, 0xFFFF, sum = 0
4387 22:13:23.180598 6, 0xFFFF, sum = 0
4388 22:13:23.183811 7, 0xFFFF, sum = 0
4389 22:13:23.183909 8, 0x0, sum = 1
4390 22:13:23.187095 9, 0x0, sum = 2
4391 22:13:23.187181 10, 0x0, sum = 3
4392 22:13:23.190422 11, 0x0, sum = 4
4393 22:13:23.190495 best_step = 9
4394 22:13:23.190555
4395 22:13:23.190611 ==
4396 22:13:23.194435 Dram Type= 6, Freq= 0, CH_0, rank 1
4397 22:13:23.197258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4398 22:13:23.200312 ==
4399 22:13:23.200384 RX Vref Scan: 0
4400 22:13:23.200442
4401 22:13:23.203938 RX Vref 0 -> 0, step: 1
4402 22:13:23.204033
4403 22:13:23.206835 RX Delay -195 -> 252, step: 8
4404 22:13:23.209978 iDelay=205, Bit 0, Center 36 (-115 ~ 188) 304
4405 22:13:23.213733 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4406 22:13:23.219871 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4407 22:13:23.223275 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4408 22:13:23.226838 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4409 22:13:23.230210 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4410 22:13:23.237044 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4411 22:13:23.240196 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4412 22:13:23.243202 iDelay=205, Bit 8, Center 28 (-123 ~ 180) 304
4413 22:13:23.246592 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4414 22:13:23.250455 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4415 22:13:23.256601 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4416 22:13:23.259975 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4417 22:13:23.263313 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4418 22:13:23.266714 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4419 22:13:23.273469 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4420 22:13:23.273550 ==
4421 22:13:23.276525 Dram Type= 6, Freq= 0, CH_0, rank 1
4422 22:13:23.279673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4423 22:13:23.279754 ==
4424 22:13:23.279819 DQS Delay:
4425 22:13:23.283093 DQS0 = 0, DQS1 = 0
4426 22:13:23.283173 DQM Delay:
4427 22:13:23.286369 DQM0 = 41, DQM1 = 37
4428 22:13:23.286449 DQ Delay:
4429 22:13:23.289700 DQ0 =36, DQ1 =44, DQ2 =36, DQ3 =40
4430 22:13:23.292812 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4431 22:13:23.296312 DQ8 =28, DQ9 =24, DQ10 =40, DQ11 =28
4432 22:13:23.299825 DQ12 =44, DQ13 =44, DQ14 =48, DQ15 =44
4433 22:13:23.299906
4434 22:13:23.299971
4435 22:13:23.309192 [DQSOSCAuto] RK1, (LSB)MR18= 0x6013, (MSB)MR19= 0x808, tDQSOscB0 = 406 ps tDQSOscB1 = 391 ps
4436 22:13:23.309274 CH0 RK1: MR19=808, MR18=6013
4437 22:13:23.316093 CH0_RK1: MR19=0x808, MR18=0x6013, DQSOSC=391, MR23=63, INC=171, DEC=114
4438 22:13:23.319479 [RxdqsGatingPostProcess] freq 600
4439 22:13:23.325821 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4440 22:13:23.329283 Pre-setting of DQS Precalculation
4441 22:13:23.332497 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4442 22:13:23.332578 ==
4443 22:13:23.335873 Dram Type= 6, Freq= 0, CH_1, rank 0
4444 22:13:23.342645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4445 22:13:23.342726 ==
4446 22:13:23.345760 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4447 22:13:23.352443 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4448 22:13:23.355517 [CA 0] Center 35 (5~66) winsize 62
4449 22:13:23.359182 [CA 1] Center 35 (5~66) winsize 62
4450 22:13:23.362598 [CA 2] Center 34 (4~65) winsize 62
4451 22:13:23.365666 [CA 3] Center 33 (3~64) winsize 62
4452 22:13:23.368506 [CA 4] Center 34 (3~65) winsize 63
4453 22:13:23.372158 [CA 5] Center 33 (3~64) winsize 62
4454 22:13:23.372265
4455 22:13:23.375490 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4456 22:13:23.375573
4457 22:13:23.378825 [CATrainingPosCal] consider 1 rank data
4458 22:13:23.381924 u2DelayCellTimex100 = 270/100 ps
4459 22:13:23.384997 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4460 22:13:23.392373 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4461 22:13:23.395509 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4462 22:13:23.398641 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4463 22:13:23.401962 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4464 22:13:23.405286 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4465 22:13:23.405369
4466 22:13:23.408442 CA PerBit enable=1, Macro0, CA PI delay=33
4467 22:13:23.408525
4468 22:13:23.411984 [CBTSetCACLKResult] CA Dly = 33
4469 22:13:23.412066 CS Dly: 3 (0~34)
4470 22:13:23.415080 ==
4471 22:13:23.418487 Dram Type= 6, Freq= 0, CH_1, rank 1
4472 22:13:23.421650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4473 22:13:23.421734 ==
4474 22:13:23.428399 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4475 22:13:23.431294 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4476 22:13:23.435390 [CA 0] Center 35 (5~66) winsize 62
4477 22:13:23.438578 [CA 1] Center 36 (6~66) winsize 61
4478 22:13:23.441947 [CA 2] Center 34 (4~65) winsize 62
4479 22:13:23.445703 [CA 3] Center 34 (3~65) winsize 63
4480 22:13:23.448783 [CA 4] Center 34 (3~65) winsize 63
4481 22:13:23.452072 [CA 5] Center 34 (3~65) winsize 63
4482 22:13:23.452154
4483 22:13:23.455010 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4484 22:13:23.455133
4485 22:13:23.458881 [CATrainingPosCal] consider 2 rank data
4486 22:13:23.461670 u2DelayCellTimex100 = 270/100 ps
4487 22:13:23.465481 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4488 22:13:23.471937 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4489 22:13:23.474994 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4490 22:13:23.478446 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4491 22:13:23.481956 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4492 22:13:23.485095 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4493 22:13:23.485178
4494 22:13:23.488517 CA PerBit enable=1, Macro0, CA PI delay=33
4495 22:13:23.488600
4496 22:13:23.491446 [CBTSetCACLKResult] CA Dly = 33
4497 22:13:23.494870 CS Dly: 4 (0~36)
4498 22:13:23.494956
4499 22:13:23.498548 ----->DramcWriteLeveling(PI) begin...
4500 22:13:23.498631 ==
4501 22:13:23.501269 Dram Type= 6, Freq= 0, CH_1, rank 0
4502 22:13:23.505015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4503 22:13:23.505098 ==
4504 22:13:23.508369 Write leveling (Byte 0): 29 => 29
4505 22:13:23.511452 Write leveling (Byte 1): 31 => 31
4506 22:13:23.514970 DramcWriteLeveling(PI) end<-----
4507 22:13:23.515053
4508 22:13:23.515158 ==
4509 22:13:23.517913 Dram Type= 6, Freq= 0, CH_1, rank 0
4510 22:13:23.521284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4511 22:13:23.521367 ==
4512 22:13:23.524435 [Gating] SW mode calibration
4513 22:13:23.531216 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4514 22:13:23.537818 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4515 22:13:23.541016 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4516 22:13:23.544457 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4517 22:13:23.551416 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4518 22:13:23.554282 0 9 12 | B1->B0 | 3030 2e2e | 1 0 | (1 0) (0 0)
4519 22:13:23.557457 0 9 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4520 22:13:23.564164 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4521 22:13:23.567224 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4522 22:13:23.570616 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4523 22:13:23.577001 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4524 22:13:23.580377 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4525 22:13:23.583963 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4526 22:13:23.590532 0 10 12 | B1->B0 | 2e2e 3535 | 0 1 | (0 0) (0 0)
4527 22:13:23.593925 0 10 16 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
4528 22:13:23.596809 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4529 22:13:23.603760 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4530 22:13:23.606894 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4531 22:13:23.610531 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4532 22:13:23.616889 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4533 22:13:23.620228 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4534 22:13:23.623394 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4535 22:13:23.629843 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4536 22:13:23.633263 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4537 22:13:23.636505 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4538 22:13:23.642964 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4539 22:13:23.646643 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4540 22:13:23.650056 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4541 22:13:23.656511 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4542 22:13:23.659707 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4543 22:13:23.663251 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4544 22:13:23.669970 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4545 22:13:23.672990 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4546 22:13:23.676298 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4547 22:13:23.683006 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4548 22:13:23.686740 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4549 22:13:23.689935 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4550 22:13:23.695929 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4551 22:13:23.699696 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4552 22:13:23.703031 Total UI for P1: 0, mck2ui 16
4553 22:13:23.706184 best dqsien dly found for B0: ( 0, 13, 14)
4554 22:13:23.709150 Total UI for P1: 0, mck2ui 16
4555 22:13:23.712443 best dqsien dly found for B1: ( 0, 13, 14)
4556 22:13:23.715752 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4557 22:13:23.719266 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4558 22:13:23.719340
4559 22:13:23.722313 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4560 22:13:23.725997 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4561 22:13:23.729078 [Gating] SW calibration Done
4562 22:13:23.729177 ==
4563 22:13:23.732225 Dram Type= 6, Freq= 0, CH_1, rank 0
4564 22:13:23.738932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4565 22:13:23.739042 ==
4566 22:13:23.739119 RX Vref Scan: 0
4567 22:13:23.739181
4568 22:13:23.741959 RX Vref 0 -> 0, step: 1
4569 22:13:23.742055
4570 22:13:23.745436 RX Delay -230 -> 252, step: 16
4571 22:13:23.748748 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4572 22:13:23.752034 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4573 22:13:23.755729 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4574 22:13:23.762426 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4575 22:13:23.765477 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4576 22:13:23.768495 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4577 22:13:23.772330 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4578 22:13:23.778790 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4579 22:13:23.781679 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4580 22:13:23.785444 iDelay=218, Bit 9, Center 33 (-134 ~ 201) 336
4581 22:13:23.788673 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4582 22:13:23.795414 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4583 22:13:23.798552 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4584 22:13:23.801780 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4585 22:13:23.805229 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4586 22:13:23.811594 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4587 22:13:23.811677 ==
4588 22:13:23.814786 Dram Type= 6, Freq= 0, CH_1, rank 0
4589 22:13:23.817978 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4590 22:13:23.818061 ==
4591 22:13:23.818127 DQS Delay:
4592 22:13:23.821715 DQS0 = 0, DQS1 = 0
4593 22:13:23.821798 DQM Delay:
4594 22:13:23.824651 DQM0 = 45, DQM1 = 36
4595 22:13:23.824733 DQ Delay:
4596 22:13:23.828046 DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =41
4597 22:13:23.831446 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4598 22:13:23.834737 DQ8 =17, DQ9 =33, DQ10 =33, DQ11 =25
4599 22:13:23.838220 DQ12 =49, DQ13 =41, DQ14 =41, DQ15 =49
4600 22:13:23.838303
4601 22:13:23.838368
4602 22:13:23.838428 ==
4603 22:13:23.841055 Dram Type= 6, Freq= 0, CH_1, rank 0
4604 22:13:23.844694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4605 22:13:23.844777 ==
4606 22:13:23.847962
4607 22:13:23.848044
4608 22:13:23.848109 TX Vref Scan disable
4609 22:13:23.851182 == TX Byte 0 ==
4610 22:13:23.854303 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4611 22:13:23.857683 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4612 22:13:23.860827 == TX Byte 1 ==
4613 22:13:23.864142 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4614 22:13:23.868062 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4615 22:13:23.870935 ==
4616 22:13:23.874631 Dram Type= 6, Freq= 0, CH_1, rank 0
4617 22:13:23.877509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4618 22:13:23.877591 ==
4619 22:13:23.877658
4620 22:13:23.877717
4621 22:13:23.880834 TX Vref Scan disable
4622 22:13:23.880916 == TX Byte 0 ==
4623 22:13:23.887845 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4624 22:13:23.890580 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4625 22:13:23.893909 == TX Byte 1 ==
4626 22:13:23.897103 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4627 22:13:23.900564 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4628 22:13:23.900634
4629 22:13:23.900694 [DATLAT]
4630 22:13:23.903834 Freq=600, CH1 RK0
4631 22:13:23.903903
4632 22:13:23.903968 DATLAT Default: 0x9
4633 22:13:23.907009 0, 0xFFFF, sum = 0
4634 22:13:23.910259 1, 0xFFFF, sum = 0
4635 22:13:23.910334 2, 0xFFFF, sum = 0
4636 22:13:23.913412 3, 0xFFFF, sum = 0
4637 22:13:23.913479 4, 0xFFFF, sum = 0
4638 22:13:23.917296 5, 0xFFFF, sum = 0
4639 22:13:23.917366 6, 0xFFFF, sum = 0
4640 22:13:23.920640 7, 0xFFFF, sum = 0
4641 22:13:23.920708 8, 0x0, sum = 1
4642 22:13:23.923409 9, 0x0, sum = 2
4643 22:13:23.923477 10, 0x0, sum = 3
4644 22:13:23.926910 11, 0x0, sum = 4
4645 22:13:23.926988 best_step = 9
4646 22:13:23.927049
4647 22:13:23.927143 ==
4648 22:13:23.930330 Dram Type= 6, Freq= 0, CH_1, rank 0
4649 22:13:23.933511 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4650 22:13:23.933593 ==
4651 22:13:23.937302 RX Vref Scan: 1
4652 22:13:23.937378
4653 22:13:23.940268 RX Vref 0 -> 0, step: 1
4654 22:13:23.940341
4655 22:13:23.940411 RX Delay -195 -> 252, step: 8
4656 22:13:23.940470
4657 22:13:23.943193 Set Vref, RX VrefLevel [Byte0]: 48
4658 22:13:23.946436 [Byte1]: 57
4659 22:13:23.951289
4660 22:13:23.951363 Final RX Vref Byte 0 = 48 to rank0
4661 22:13:23.954499 Final RX Vref Byte 1 = 57 to rank0
4662 22:13:23.957878 Final RX Vref Byte 0 = 48 to rank1
4663 22:13:23.961497 Final RX Vref Byte 1 = 57 to rank1==
4664 22:13:23.964367 Dram Type= 6, Freq= 0, CH_1, rank 0
4665 22:13:23.971067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4666 22:13:23.971186 ==
4667 22:13:23.971250 DQS Delay:
4668 22:13:23.974406 DQS0 = 0, DQS1 = 0
4669 22:13:23.974481 DQM Delay:
4670 22:13:23.974543 DQM0 = 48, DQM1 = 37
4671 22:13:23.977563 DQ Delay:
4672 22:13:23.981138 DQ0 =56, DQ1 =44, DQ2 =40, DQ3 =44
4673 22:13:23.984304 DQ4 =44, DQ5 =60, DQ6 =56, DQ7 =44
4674 22:13:23.984384 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =28
4675 22:13:23.991835 DQ12 =48, DQ13 =44, DQ14 =48, DQ15 =48
4676 22:13:23.991919
4677 22:13:23.991985
4678 22:13:23.997834 [DQSOSCAuto] RK0, (LSB)MR18= 0x5237, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 394 ps
4679 22:13:24.000964 CH1 RK0: MR19=808, MR18=5237
4680 22:13:24.007653 CH1_RK0: MR19=0x808, MR18=0x5237, DQSOSC=394, MR23=63, INC=168, DEC=112
4681 22:13:24.007738
4682 22:13:24.010722 ----->DramcWriteLeveling(PI) begin...
4683 22:13:24.010796 ==
4684 22:13:24.014440 Dram Type= 6, Freq= 0, CH_1, rank 1
4685 22:13:24.017739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4686 22:13:24.017841 ==
4687 22:13:24.020770 Write leveling (Byte 0): 29 => 29
4688 22:13:24.024337 Write leveling (Byte 1): 29 => 29
4689 22:13:24.027536 DramcWriteLeveling(PI) end<-----
4690 22:13:24.027608
4691 22:13:24.027668 ==
4692 22:13:24.030500 Dram Type= 6, Freq= 0, CH_1, rank 1
4693 22:13:24.034312 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4694 22:13:24.034387 ==
4695 22:13:24.037471 [Gating] SW mode calibration
4696 22:13:24.044470 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4697 22:13:24.050591 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4698 22:13:24.053700 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4699 22:13:24.060176 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4700 22:13:24.063713 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4701 22:13:24.067004 0 9 12 | B1->B0 | 3232 3333 | 1 0 | (1 0) (0 1)
4702 22:13:24.073655 0 9 16 | B1->B0 | 2424 2929 | 0 0 | (0 0) (1 0)
4703 22:13:24.077046 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4704 22:13:24.080032 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4705 22:13:24.086604 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4706 22:13:24.090148 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4707 22:13:24.093749 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4708 22:13:24.099945 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4709 22:13:24.103322 0 10 12 | B1->B0 | 3737 302f | 0 1 | (1 1) (0 0)
4710 22:13:24.106434 0 10 16 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
4711 22:13:24.112992 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4712 22:13:24.116842 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4713 22:13:24.119736 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4714 22:13:24.126497 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4715 22:13:24.129675 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4716 22:13:24.132951 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4717 22:13:24.139775 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4718 22:13:24.142650 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4719 22:13:24.146535 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4720 22:13:24.152424 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4721 22:13:24.156504 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4722 22:13:24.159111 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4723 22:13:24.165855 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4724 22:13:24.169039 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4725 22:13:24.172526 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4726 22:13:24.178882 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4727 22:13:24.182322 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4728 22:13:24.186109 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4729 22:13:24.192750 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4730 22:13:24.195652 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4731 22:13:24.198917 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4732 22:13:24.205410 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4733 22:13:24.209465 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4734 22:13:24.212112 Total UI for P1: 0, mck2ui 16
4735 22:13:24.215632 best dqsien dly found for B1: ( 0, 13, 10)
4736 22:13:24.219179 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4737 22:13:24.222020 Total UI for P1: 0, mck2ui 16
4738 22:13:24.225180 best dqsien dly found for B0: ( 0, 13, 14)
4739 22:13:24.228631 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4740 22:13:24.232402 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4741 22:13:24.232484
4742 22:13:24.238870 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4743 22:13:24.241932 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4744 22:13:24.242015 [Gating] SW calibration Done
4745 22:13:24.245400 ==
4746 22:13:24.248369 Dram Type= 6, Freq= 0, CH_1, rank 1
4747 22:13:24.251751 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4748 22:13:24.251834 ==
4749 22:13:24.251900 RX Vref Scan: 0
4750 22:13:24.251960
4751 22:13:24.254987 RX Vref 0 -> 0, step: 1
4752 22:13:24.255094
4753 22:13:24.258650 RX Delay -230 -> 252, step: 16
4754 22:13:24.261630 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4755 22:13:24.264741 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4756 22:13:24.271729 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4757 22:13:24.274963 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4758 22:13:24.278221 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4759 22:13:24.281637 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4760 22:13:24.287945 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4761 22:13:24.291063 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4762 22:13:24.294779 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4763 22:13:24.298077 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4764 22:13:24.301291 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4765 22:13:24.307550 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4766 22:13:24.311250 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4767 22:13:24.314327 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4768 22:13:24.321135 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4769 22:13:24.324286 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4770 22:13:24.324360 ==
4771 22:13:24.327896 Dram Type= 6, Freq= 0, CH_1, rank 1
4772 22:13:24.330715 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4773 22:13:24.330821 ==
4774 22:13:24.334308 DQS Delay:
4775 22:13:24.334402 DQS0 = 0, DQS1 = 0
4776 22:13:24.334500 DQM Delay:
4777 22:13:24.337196 DQM0 = 45, DQM1 = 38
4778 22:13:24.337292 DQ Delay:
4779 22:13:24.340488 DQ0 =57, DQ1 =41, DQ2 =25, DQ3 =41
4780 22:13:24.344309 DQ4 =41, DQ5 =57, DQ6 =65, DQ7 =33
4781 22:13:24.347512 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =33
4782 22:13:24.350830 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4783 22:13:24.350928
4784 22:13:24.351027
4785 22:13:24.351111 ==
4786 22:13:24.354083 Dram Type= 6, Freq= 0, CH_1, rank 1
4787 22:13:24.360549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4788 22:13:24.360633 ==
4789 22:13:24.360714
4790 22:13:24.360790
4791 22:13:24.360863 TX Vref Scan disable
4792 22:13:24.364001 == TX Byte 0 ==
4793 22:13:24.367173 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4794 22:13:24.373781 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4795 22:13:24.373884 == TX Byte 1 ==
4796 22:13:24.377590 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4797 22:13:24.383828 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4798 22:13:24.383909 ==
4799 22:13:24.387022 Dram Type= 6, Freq= 0, CH_1, rank 1
4800 22:13:24.390533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4801 22:13:24.390609 ==
4802 22:13:24.390713
4803 22:13:24.390814
4804 22:13:24.393402 TX Vref Scan disable
4805 22:13:24.397095 == TX Byte 0 ==
4806 22:13:24.400055 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4807 22:13:24.403665 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4808 22:13:24.406825 == TX Byte 1 ==
4809 22:13:24.409988 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4810 22:13:24.413437 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4811 22:13:24.413539
4812 22:13:24.413638 [DATLAT]
4813 22:13:24.416858 Freq=600, CH1 RK1
4814 22:13:24.416941
4815 22:13:24.420461 DATLAT Default: 0x9
4816 22:13:24.420562 0, 0xFFFF, sum = 0
4817 22:13:24.423537 1, 0xFFFF, sum = 0
4818 22:13:24.423617 2, 0xFFFF, sum = 0
4819 22:13:24.426823 3, 0xFFFF, sum = 0
4820 22:13:24.426900 4, 0xFFFF, sum = 0
4821 22:13:24.429848 5, 0xFFFF, sum = 0
4822 22:13:24.429939 6, 0xFFFF, sum = 0
4823 22:13:24.433421 7, 0xFFFF, sum = 0
4824 22:13:24.433500 8, 0x0, sum = 1
4825 22:13:24.436630 9, 0x0, sum = 2
4826 22:13:24.436709 10, 0x0, sum = 3
4827 22:13:24.439912 11, 0x0, sum = 4
4828 22:13:24.440018 best_step = 9
4829 22:13:24.440097
4830 22:13:24.440182 ==
4831 22:13:24.443224 Dram Type= 6, Freq= 0, CH_1, rank 1
4832 22:13:24.446161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4833 22:13:24.446249 ==
4834 22:13:24.449920 RX Vref Scan: 0
4835 22:13:24.450024
4836 22:13:24.452960 RX Vref 0 -> 0, step: 1
4837 22:13:24.453073
4838 22:13:24.453171 RX Delay -195 -> 252, step: 8
4839 22:13:24.461143 iDelay=213, Bit 0, Center 48 (-99 ~ 196) 296
4840 22:13:24.464428 iDelay=213, Bit 1, Center 40 (-107 ~ 188) 296
4841 22:13:24.467769 iDelay=213, Bit 2, Center 32 (-115 ~ 180) 296
4842 22:13:24.470926 iDelay=213, Bit 3, Center 40 (-107 ~ 188) 296
4843 22:13:24.478097 iDelay=213, Bit 4, Center 44 (-107 ~ 196) 304
4844 22:13:24.480724 iDelay=213, Bit 5, Center 56 (-91 ~ 204) 296
4845 22:13:24.484398 iDelay=213, Bit 6, Center 60 (-91 ~ 212) 304
4846 22:13:24.487466 iDelay=213, Bit 7, Center 44 (-107 ~ 196) 304
4847 22:13:24.490886 iDelay=213, Bit 8, Center 24 (-131 ~ 180) 312
4848 22:13:24.497718 iDelay=213, Bit 9, Center 24 (-131 ~ 180) 312
4849 22:13:24.500483 iDelay=213, Bit 10, Center 40 (-115 ~ 196) 312
4850 22:13:24.503834 iDelay=213, Bit 11, Center 24 (-131 ~ 180) 312
4851 22:13:24.507478 iDelay=213, Bit 12, Center 48 (-107 ~ 204) 312
4852 22:13:24.514162 iDelay=213, Bit 13, Center 48 (-107 ~ 204) 312
4853 22:13:24.517976 iDelay=213, Bit 14, Center 44 (-107 ~ 196) 304
4854 22:13:24.520479 iDelay=213, Bit 15, Center 48 (-107 ~ 204) 312
4855 22:13:24.520612 ==
4856 22:13:24.524331 Dram Type= 6, Freq= 0, CH_1, rank 1
4857 22:13:24.527215 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4858 22:13:24.530567 ==
4859 22:13:24.530670 DQS Delay:
4860 22:13:24.530761 DQS0 = 0, DQS1 = 0
4861 22:13:24.534008 DQM Delay:
4862 22:13:24.534104 DQM0 = 45, DQM1 = 37
4863 22:13:24.537072 DQ Delay:
4864 22:13:24.540596 DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =40
4865 22:13:24.540735 DQ4 =44, DQ5 =56, DQ6 =60, DQ7 =44
4866 22:13:24.543677 DQ8 =24, DQ9 =24, DQ10 =40, DQ11 =24
4867 22:13:24.550558 DQ12 =48, DQ13 =48, DQ14 =44, DQ15 =48
4868 22:13:24.550671
4869 22:13:24.550765
4870 22:13:24.556733 [DQSOSCAuto] RK1, (LSB)MR18= 0x3529, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 399 ps
4871 22:13:24.560539 CH1 RK1: MR19=808, MR18=3529
4872 22:13:24.566856 CH1_RK1: MR19=0x808, MR18=0x3529, DQSOSC=399, MR23=63, INC=164, DEC=109
4873 22:13:24.569738 [RxdqsGatingPostProcess] freq 600
4874 22:13:24.573389 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4875 22:13:24.577524 Pre-setting of DQS Precalculation
4876 22:13:24.583016 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4877 22:13:24.589900 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4878 22:13:24.596445 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4879 22:13:24.596562
4880 22:13:24.596663
4881 22:13:24.599721 [Calibration Summary] 1200 Mbps
4882 22:13:24.599821 CH 0, Rank 0
4883 22:13:24.602819 SW Impedance : PASS
4884 22:13:24.606553 DUTY Scan : NO K
4885 22:13:24.606654 ZQ Calibration : PASS
4886 22:13:24.609726 Jitter Meter : NO K
4887 22:13:24.613123 CBT Training : PASS
4888 22:13:24.613209 Write leveling : PASS
4889 22:13:24.616175 RX DQS gating : PASS
4890 22:13:24.619299 RX DQ/DQS(RDDQC) : PASS
4891 22:13:24.619380 TX DQ/DQS : PASS
4892 22:13:24.622732 RX DATLAT : PASS
4893 22:13:24.625952 RX DQ/DQS(Engine): PASS
4894 22:13:24.626034 TX OE : NO K
4895 22:13:24.629240 All Pass.
4896 22:13:24.629322
4897 22:13:24.629386 CH 0, Rank 1
4898 22:13:24.632862 SW Impedance : PASS
4899 22:13:24.632947 DUTY Scan : NO K
4900 22:13:24.636176 ZQ Calibration : PASS
4901 22:13:24.639247 Jitter Meter : NO K
4902 22:13:24.639329 CBT Training : PASS
4903 22:13:24.642537 Write leveling : PASS
4904 22:13:24.645632 RX DQS gating : PASS
4905 22:13:24.645716 RX DQ/DQS(RDDQC) : PASS
4906 22:13:24.649240 TX DQ/DQS : PASS
4907 22:13:24.651997 RX DATLAT : PASS
4908 22:13:24.652082 RX DQ/DQS(Engine): PASS
4909 22:13:24.655853 TX OE : NO K
4910 22:13:24.655935 All Pass.
4911 22:13:24.656000
4912 22:13:24.658769 CH 1, Rank 0
4913 22:13:24.658854 SW Impedance : PASS
4914 22:13:24.662288 DUTY Scan : NO K
4915 22:13:24.665359 ZQ Calibration : PASS
4916 22:13:24.665441 Jitter Meter : NO K
4917 22:13:24.668858 CBT Training : PASS
4918 22:13:24.668941 Write leveling : PASS
4919 22:13:24.672183 RX DQS gating : PASS
4920 22:13:24.675593 RX DQ/DQS(RDDQC) : PASS
4921 22:13:24.675676 TX DQ/DQS : PASS
4922 22:13:24.678389 RX DATLAT : PASS
4923 22:13:24.682172 RX DQ/DQS(Engine): PASS
4924 22:13:24.682270 TX OE : NO K
4925 22:13:24.684982 All Pass.
4926 22:13:24.685065
4927 22:13:24.685176 CH 1, Rank 1
4928 22:13:24.688583 SW Impedance : PASS
4929 22:13:24.688665 DUTY Scan : NO K
4930 22:13:24.692019 ZQ Calibration : PASS
4931 22:13:24.694975 Jitter Meter : NO K
4932 22:13:24.695124 CBT Training : PASS
4933 22:13:24.698426 Write leveling : PASS
4934 22:13:24.702130 RX DQS gating : PASS
4935 22:13:24.702215 RX DQ/DQS(RDDQC) : PASS
4936 22:13:24.705228 TX DQ/DQS : PASS
4937 22:13:24.708342 RX DATLAT : PASS
4938 22:13:24.708425 RX DQ/DQS(Engine): PASS
4939 22:13:24.711427 TX OE : NO K
4940 22:13:24.711510 All Pass.
4941 22:13:24.711577
4942 22:13:24.714934 DramC Write-DBI off
4943 22:13:24.718015 PER_BANK_REFRESH: Hybrid Mode
4944 22:13:24.718097 TX_TRACKING: ON
4945 22:13:24.728574 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4946 22:13:24.731552 [FAST_K] Save calibration result to emmc
4947 22:13:24.734577 dramc_set_vcore_voltage set vcore to 662500
4948 22:13:24.738139 Read voltage for 933, 3
4949 22:13:24.738222 Vio18 = 0
4950 22:13:24.738287 Vcore = 662500
4951 22:13:24.741431 Vdram = 0
4952 22:13:24.741522 Vddq = 0
4953 22:13:24.741588 Vmddr = 0
4954 22:13:24.747875 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4955 22:13:24.751110 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4956 22:13:24.754589 MEM_TYPE=3, freq_sel=17
4957 22:13:24.757728 sv_algorithm_assistance_LP4_1600
4958 22:13:24.760969 ============ PULL DRAM RESETB DOWN ============
4959 22:13:24.767588 ========== PULL DRAM RESETB DOWN end =========
4960 22:13:24.770994 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4961 22:13:24.774431 ===================================
4962 22:13:24.777687 LPDDR4 DRAM CONFIGURATION
4963 22:13:24.781128 ===================================
4964 22:13:24.781212 EX_ROW_EN[0] = 0x0
4965 22:13:24.784039 EX_ROW_EN[1] = 0x0
4966 22:13:24.784121 LP4Y_EN = 0x0
4967 22:13:24.787414 WORK_FSP = 0x0
4968 22:13:24.787496 WL = 0x3
4969 22:13:24.790828 RL = 0x3
4970 22:13:24.790937 BL = 0x2
4971 22:13:24.794060 RPST = 0x0
4972 22:13:24.794143 RD_PRE = 0x0
4973 22:13:24.797701 WR_PRE = 0x1
4974 22:13:24.797784 WR_PST = 0x0
4975 22:13:24.801566 DBI_WR = 0x0
4976 22:13:24.803804 DBI_RD = 0x0
4977 22:13:24.803887 OTF = 0x1
4978 22:13:24.807109 ===================================
4979 22:13:24.810667 ===================================
4980 22:13:24.810750 ANA top config
4981 22:13:24.814061 ===================================
4982 22:13:24.817219 DLL_ASYNC_EN = 0
4983 22:13:24.820177 ALL_SLAVE_EN = 1
4984 22:13:24.823477 NEW_RANK_MODE = 1
4985 22:13:24.826896 DLL_IDLE_MODE = 1
4986 22:13:24.826970 LP45_APHY_COMB_EN = 1
4987 22:13:24.830243 TX_ODT_DIS = 1
4988 22:13:24.833512 NEW_8X_MODE = 1
4989 22:13:24.836629 ===================================
4990 22:13:24.840013 ===================================
4991 22:13:24.843788 data_rate = 1866
4992 22:13:24.846851 CKR = 1
4993 22:13:24.850124 DQ_P2S_RATIO = 8
4994 22:13:24.853649 ===================================
4995 22:13:24.853748 CA_P2S_RATIO = 8
4996 22:13:24.856462 DQ_CA_OPEN = 0
4997 22:13:24.860425 DQ_SEMI_OPEN = 0
4998 22:13:24.863298 CA_SEMI_OPEN = 0
4999 22:13:24.866657 CA_FULL_RATE = 0
5000 22:13:24.869775 DQ_CKDIV4_EN = 1
5001 22:13:24.869880 CA_CKDIV4_EN = 1
5002 22:13:24.873140 CA_PREDIV_EN = 0
5003 22:13:24.876420 PH8_DLY = 0
5004 22:13:24.879845 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
5005 22:13:24.882887 DQ_AAMCK_DIV = 4
5006 22:13:24.886356 CA_AAMCK_DIV = 4
5007 22:13:24.886433 CA_ADMCK_DIV = 4
5008 22:13:24.889855 DQ_TRACK_CA_EN = 0
5009 22:13:24.893217 CA_PICK = 933
5010 22:13:24.896356 CA_MCKIO = 933
5011 22:13:24.899547 MCKIO_SEMI = 0
5012 22:13:24.903159 PLL_FREQ = 3732
5013 22:13:24.905847 DQ_UI_PI_RATIO = 32
5014 22:13:24.905951 CA_UI_PI_RATIO = 0
5015 22:13:24.909145 ===================================
5016 22:13:24.912564 ===================================
5017 22:13:24.915784 memory_type:LPDDR4
5018 22:13:24.919003 GP_NUM : 10
5019 22:13:24.919137 SRAM_EN : 1
5020 22:13:24.922767 MD32_EN : 0
5021 22:13:24.925550 ===================================
5022 22:13:24.929364 [ANA_INIT] >>>>>>>>>>>>>>
5023 22:13:24.932551 <<<<<< [CONFIGURE PHASE]: ANA_TX
5024 22:13:24.936046 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5025 22:13:24.939290 ===================================
5026 22:13:24.942138 data_rate = 1866,PCW = 0X8f00
5027 22:13:24.945522 ===================================
5028 22:13:24.948979 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5029 22:13:24.952027 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5030 22:13:24.958630 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5031 22:13:24.962371 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5032 22:13:24.965611 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5033 22:13:24.968425 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5034 22:13:24.972067 [ANA_INIT] flow start
5035 22:13:24.975093 [ANA_INIT] PLL >>>>>>>>
5036 22:13:24.975169 [ANA_INIT] PLL <<<<<<<<
5037 22:13:24.978581 [ANA_INIT] MIDPI >>>>>>>>
5038 22:13:24.981576 [ANA_INIT] MIDPI <<<<<<<<
5039 22:13:24.985663 [ANA_INIT] DLL >>>>>>>>
5040 22:13:24.985805 [ANA_INIT] flow end
5041 22:13:24.988262 ============ LP4 DIFF to SE enter ============
5042 22:13:24.994940 ============ LP4 DIFF to SE exit ============
5043 22:13:24.995048 [ANA_INIT] <<<<<<<<<<<<<
5044 22:13:24.998296 [Flow] Enable top DCM control >>>>>
5045 22:13:25.002100 [Flow] Enable top DCM control <<<<<
5046 22:13:25.005380 Enable DLL master slave shuffle
5047 22:13:25.011353 ==============================================================
5048 22:13:25.011435 Gating Mode config
5049 22:13:25.018165 ==============================================================
5050 22:13:25.021212 Config description:
5051 22:13:25.031879 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5052 22:13:25.038175 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5053 22:13:25.041191 SELPH_MODE 0: By rank 1: By Phase
5054 22:13:25.048083 ==============================================================
5055 22:13:25.051344 GAT_TRACK_EN = 1
5056 22:13:25.054562 RX_GATING_MODE = 2
5057 22:13:25.054643 RX_GATING_TRACK_MODE = 2
5058 22:13:25.057540 SELPH_MODE = 1
5059 22:13:25.061754 PICG_EARLY_EN = 1
5060 22:13:25.064366 VALID_LAT_VALUE = 1
5061 22:13:25.071123 ==============================================================
5062 22:13:25.074665 Enter into Gating configuration >>>>
5063 22:13:25.077387 Exit from Gating configuration <<<<
5064 22:13:25.080696 Enter into DVFS_PRE_config >>>>>
5065 22:13:25.090779 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5066 22:13:25.094580 Exit from DVFS_PRE_config <<<<<
5067 22:13:25.097450 Enter into PICG configuration >>>>
5068 22:13:25.100555 Exit from PICG configuration <<<<
5069 22:13:25.103741 [RX_INPUT] configuration >>>>>
5070 22:13:25.107356 [RX_INPUT] configuration <<<<<
5071 22:13:25.110617 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5072 22:13:25.116749 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5073 22:13:25.123653 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5074 22:13:25.130292 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5075 22:13:25.136843 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5076 22:13:25.140405 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5077 22:13:25.146848 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5078 22:13:25.149882 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5079 22:13:25.153405 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5080 22:13:25.156439 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5081 22:13:25.162939 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5082 22:13:25.166563 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5083 22:13:25.169936 ===================================
5084 22:13:25.172933 LPDDR4 DRAM CONFIGURATION
5085 22:13:25.176258 ===================================
5086 22:13:25.176358 EX_ROW_EN[0] = 0x0
5087 22:13:25.179545 EX_ROW_EN[1] = 0x0
5088 22:13:25.179618 LP4Y_EN = 0x0
5089 22:13:25.182794 WORK_FSP = 0x0
5090 22:13:25.186746 WL = 0x3
5091 22:13:25.186848 RL = 0x3
5092 22:13:25.189352 BL = 0x2
5093 22:13:25.189429 RPST = 0x0
5094 22:13:25.192899 RD_PRE = 0x0
5095 22:13:25.192972 WR_PRE = 0x1
5096 22:13:25.195840 WR_PST = 0x0
5097 22:13:25.195914 DBI_WR = 0x0
5098 22:13:25.199369 DBI_RD = 0x0
5099 22:13:25.199466 OTF = 0x1
5100 22:13:25.202542 ===================================
5101 22:13:25.205827 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5102 22:13:25.212553 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5103 22:13:25.216004 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5104 22:13:25.219096 ===================================
5105 22:13:25.222432 LPDDR4 DRAM CONFIGURATION
5106 22:13:25.225441 ===================================
5107 22:13:25.225519 EX_ROW_EN[0] = 0x10
5108 22:13:25.228958 EX_ROW_EN[1] = 0x0
5109 22:13:25.232137 LP4Y_EN = 0x0
5110 22:13:25.232217 WORK_FSP = 0x0
5111 22:13:25.235496 WL = 0x3
5112 22:13:25.235571 RL = 0x3
5113 22:13:25.238691 BL = 0x2
5114 22:13:25.238794 RPST = 0x0
5115 22:13:25.242069 RD_PRE = 0x0
5116 22:13:25.242193 WR_PRE = 0x1
5117 22:13:25.245595 WR_PST = 0x0
5118 22:13:25.245678 DBI_WR = 0x0
5119 22:13:25.248754 DBI_RD = 0x0
5120 22:13:25.248836 OTF = 0x1
5121 22:13:25.252203 ===================================
5122 22:13:25.258726 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5123 22:13:25.263474 nWR fixed to 30
5124 22:13:25.266467 [ModeRegInit_LP4] CH0 RK0
5125 22:13:25.266548 [ModeRegInit_LP4] CH0 RK1
5126 22:13:25.269521 [ModeRegInit_LP4] CH1 RK0
5127 22:13:25.272739 [ModeRegInit_LP4] CH1 RK1
5128 22:13:25.272821 match AC timing 9
5129 22:13:25.279043 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5130 22:13:25.282783 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5131 22:13:25.285774 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5132 22:13:25.292355 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5133 22:13:25.295674 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5134 22:13:25.295756 ==
5135 22:13:25.299202 Dram Type= 6, Freq= 0, CH_0, rank 0
5136 22:13:25.302474 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5137 22:13:25.302556 ==
5138 22:13:25.309361 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5139 22:13:25.315170 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5140 22:13:25.318602 [CA 0] Center 37 (7~68) winsize 62
5141 22:13:25.321796 [CA 1] Center 37 (7~68) winsize 62
5142 22:13:25.325093 [CA 2] Center 34 (4~65) winsize 62
5143 22:13:25.328313 [CA 3] Center 35 (5~65) winsize 61
5144 22:13:25.331589 [CA 4] Center 33 (3~64) winsize 62
5145 22:13:25.334979 [CA 5] Center 33 (3~64) winsize 62
5146 22:13:25.335068
5147 22:13:25.338362 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5148 22:13:25.338444
5149 22:13:25.341624 [CATrainingPosCal] consider 1 rank data
5150 22:13:25.344928 u2DelayCellTimex100 = 270/100 ps
5151 22:13:25.348814 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5152 22:13:25.351382 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5153 22:13:25.355351 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5154 22:13:25.361397 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5155 22:13:25.364880 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5156 22:13:25.367865 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5157 22:13:25.367948
5158 22:13:25.371706 CA PerBit enable=1, Macro0, CA PI delay=33
5159 22:13:25.371789
5160 22:13:25.374718 [CBTSetCACLKResult] CA Dly = 33
5161 22:13:25.374827 CS Dly: 7 (0~38)
5162 22:13:25.374925 ==
5163 22:13:25.377866 Dram Type= 6, Freq= 0, CH_0, rank 1
5164 22:13:25.384372 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5165 22:13:25.384455 ==
5166 22:13:25.387898 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5167 22:13:25.394549 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5168 22:13:25.398164 [CA 0] Center 37 (7~68) winsize 62
5169 22:13:25.401134 [CA 1] Center 37 (7~68) winsize 62
5170 22:13:25.404619 [CA 2] Center 34 (4~65) winsize 62
5171 22:13:25.407967 [CA 3] Center 34 (4~65) winsize 62
5172 22:13:25.411121 [CA 4] Center 33 (3~64) winsize 62
5173 22:13:25.414711 [CA 5] Center 33 (3~63) winsize 61
5174 22:13:25.414793
5175 22:13:25.417862 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5176 22:13:25.417944
5177 22:13:25.421456 [CATrainingPosCal] consider 2 rank data
5178 22:13:25.424390 u2DelayCellTimex100 = 270/100 ps
5179 22:13:25.428003 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5180 22:13:25.434150 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5181 22:13:25.437428 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5182 22:13:25.440713 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5183 22:13:25.444183 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5184 22:13:25.447140 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5185 22:13:25.447223
5186 22:13:25.450735 CA PerBit enable=1, Macro0, CA PI delay=33
5187 22:13:25.450818
5188 22:13:25.454476 [CBTSetCACLKResult] CA Dly = 33
5189 22:13:25.457475 CS Dly: 7 (0~39)
5190 22:13:25.457557
5191 22:13:25.460994 ----->DramcWriteLeveling(PI) begin...
5192 22:13:25.461077 ==
5193 22:13:25.464041 Dram Type= 6, Freq= 0, CH_0, rank 0
5194 22:13:25.467387 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5195 22:13:25.467470 ==
5196 22:13:25.470551 Write leveling (Byte 0): 33 => 33
5197 22:13:25.473926 Write leveling (Byte 1): 28 => 28
5198 22:13:25.477398 DramcWriteLeveling(PI) end<-----
5199 22:13:25.477515
5200 22:13:25.477614 ==
5201 22:13:25.480668 Dram Type= 6, Freq= 0, CH_0, rank 0
5202 22:13:25.484201 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5203 22:13:25.484284 ==
5204 22:13:25.487115 [Gating] SW mode calibration
5205 22:13:25.493560 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5206 22:13:25.500144 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5207 22:13:25.503608 0 14 0 | B1->B0 | 2323 3434 | 1 0 | (1 1) (0 0)
5208 22:13:25.506801 0 14 4 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
5209 22:13:25.513222 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5210 22:13:25.516894 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5211 22:13:25.520520 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5212 22:13:25.526877 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5213 22:13:25.530383 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5214 22:13:25.534139 0 14 28 | B1->B0 | 3434 2a2a | 1 1 | (1 1) (1 0)
5215 22:13:25.539684 0 15 0 | B1->B0 | 2f2f 2a2a | 1 0 | (1 0) (1 0)
5216 22:13:25.543236 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5217 22:13:25.546511 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5218 22:13:25.552982 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5219 22:13:25.556532 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5220 22:13:25.559666 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5221 22:13:25.566038 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5222 22:13:25.569689 0 15 28 | B1->B0 | 2524 3232 | 1 0 | (0 0) (1 1)
5223 22:13:25.572839 1 0 0 | B1->B0 | 3232 4545 | 0 0 | (0 0) (1 1)
5224 22:13:25.579412 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5225 22:13:25.582614 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5226 22:13:25.586308 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5227 22:13:25.592810 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5228 22:13:25.596497 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5229 22:13:25.599666 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5230 22:13:25.606444 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5231 22:13:25.609677 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5232 22:13:25.612640 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5233 22:13:25.619368 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5234 22:13:25.622942 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5235 22:13:25.626208 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5236 22:13:25.632451 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5237 22:13:25.635874 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5238 22:13:25.639463 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5239 22:13:25.645570 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5240 22:13:25.649065 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5241 22:13:25.652149 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5242 22:13:25.658935 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5243 22:13:25.662191 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5244 22:13:25.665513 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5245 22:13:25.672011 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5246 22:13:25.675179 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5247 22:13:25.678705 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5248 22:13:25.681949 Total UI for P1: 0, mck2ui 16
5249 22:13:25.685166 best dqsien dly found for B0: ( 1, 2, 28)
5250 22:13:25.691748 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5251 22:13:25.691831 Total UI for P1: 0, mck2ui 16
5252 22:13:25.698293 best dqsien dly found for B1: ( 1, 3, 0)
5253 22:13:25.702097 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5254 22:13:25.705311 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5255 22:13:25.705393
5256 22:13:25.708734 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5257 22:13:25.711658 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5258 22:13:25.714973 [Gating] SW calibration Done
5259 22:13:25.715055 ==
5260 22:13:25.718227 Dram Type= 6, Freq= 0, CH_0, rank 0
5261 22:13:25.722203 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5262 22:13:25.722317 ==
5263 22:13:25.724667 RX Vref Scan: 0
5264 22:13:25.724748
5265 22:13:25.724819 RX Vref 0 -> 0, step: 1
5266 22:13:25.724881
5267 22:13:25.728165 RX Delay -80 -> 252, step: 8
5268 22:13:25.731526 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5269 22:13:25.738061 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5270 22:13:25.741485 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5271 22:13:25.744568 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5272 22:13:25.747688 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5273 22:13:25.751006 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
5274 22:13:25.754640 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5275 22:13:25.761211 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5276 22:13:25.764681 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5277 22:13:25.767959 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5278 22:13:25.771083 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5279 22:13:25.773925 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5280 22:13:25.780704 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5281 22:13:25.784382 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5282 22:13:25.787450 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5283 22:13:25.790714 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5284 22:13:25.790789 ==
5285 22:13:25.794433 Dram Type= 6, Freq= 0, CH_0, rank 0
5286 22:13:25.801426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5287 22:13:25.801509 ==
5288 22:13:25.801573 DQS Delay:
5289 22:13:25.801631 DQS0 = 0, DQS1 = 0
5290 22:13:25.804333 DQM Delay:
5291 22:13:25.804407 DQM0 = 97, DQM1 = 86
5292 22:13:25.807568 DQ Delay:
5293 22:13:25.810859 DQ0 =99, DQ1 =99, DQ2 =91, DQ3 =91
5294 22:13:25.814036 DQ4 =99, DQ5 =83, DQ6 =107, DQ7 =107
5295 22:13:25.817163 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =79
5296 22:13:25.820421 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5297 22:13:25.820493
5298 22:13:25.820565
5299 22:13:25.820623 ==
5300 22:13:25.824076 Dram Type= 6, Freq= 0, CH_0, rank 0
5301 22:13:25.827644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5302 22:13:25.827714 ==
5303 22:13:25.827774
5304 22:13:25.827829
5305 22:13:25.830875 TX Vref Scan disable
5306 22:13:25.833878 == TX Byte 0 ==
5307 22:13:25.837183 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5308 22:13:25.840718 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5309 22:13:25.843988 == TX Byte 1 ==
5310 22:13:25.847161 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5311 22:13:25.850503 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5312 22:13:25.850573 ==
5313 22:13:25.853853 Dram Type= 6, Freq= 0, CH_0, rank 0
5314 22:13:25.856912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5315 22:13:25.856988 ==
5316 22:13:25.860616
5317 22:13:25.860693
5318 22:13:25.860787 TX Vref Scan disable
5319 22:13:25.863773 == TX Byte 0 ==
5320 22:13:25.867289 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5321 22:13:25.873563 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5322 22:13:25.873642 == TX Byte 1 ==
5323 22:13:25.876891 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5324 22:13:25.883578 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5325 22:13:25.883658
5326 22:13:25.883720 [DATLAT]
5327 22:13:25.883778 Freq=933, CH0 RK0
5328 22:13:25.883835
5329 22:13:25.886791 DATLAT Default: 0xd
5330 22:13:25.886858 0, 0xFFFF, sum = 0
5331 22:13:25.890049 1, 0xFFFF, sum = 0
5332 22:13:25.893224 2, 0xFFFF, sum = 0
5333 22:13:25.893311 3, 0xFFFF, sum = 0
5334 22:13:25.896888 4, 0xFFFF, sum = 0
5335 22:13:25.896992 5, 0xFFFF, sum = 0
5336 22:13:25.900152 6, 0xFFFF, sum = 0
5337 22:13:25.900223 7, 0xFFFF, sum = 0
5338 22:13:25.903660 8, 0xFFFF, sum = 0
5339 22:13:25.903735 9, 0xFFFF, sum = 0
5340 22:13:25.906601 10, 0x0, sum = 1
5341 22:13:25.906669 11, 0x0, sum = 2
5342 22:13:25.909889 12, 0x0, sum = 3
5343 22:13:25.909956 13, 0x0, sum = 4
5344 22:13:25.913275 best_step = 11
5345 22:13:25.913344
5346 22:13:25.913401 ==
5347 22:13:25.916678 Dram Type= 6, Freq= 0, CH_0, rank 0
5348 22:13:25.920119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5349 22:13:25.920203 ==
5350 22:13:25.920287 RX Vref Scan: 1
5351 22:13:25.920366
5352 22:13:25.923323 RX Vref 0 -> 0, step: 1
5353 22:13:25.923407
5354 22:13:25.926565 RX Delay -61 -> 252, step: 4
5355 22:13:25.926648
5356 22:13:25.929658 Set Vref, RX VrefLevel [Byte0]: 61
5357 22:13:25.933021 [Byte1]: 51
5358 22:13:25.936208
5359 22:13:25.936291 Final RX Vref Byte 0 = 61 to rank0
5360 22:13:25.939327 Final RX Vref Byte 1 = 51 to rank0
5361 22:13:25.942623 Final RX Vref Byte 0 = 61 to rank1
5362 22:13:25.946520 Final RX Vref Byte 1 = 51 to rank1==
5363 22:13:25.949561 Dram Type= 6, Freq= 0, CH_0, rank 0
5364 22:13:25.956091 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5365 22:13:25.956171 ==
5366 22:13:25.956233 DQS Delay:
5367 22:13:25.959357 DQS0 = 0, DQS1 = 0
5368 22:13:25.959436 DQM Delay:
5369 22:13:25.959499 DQM0 = 97, DQM1 = 86
5370 22:13:25.962505 DQ Delay:
5371 22:13:25.965908 DQ0 =98, DQ1 =98, DQ2 =94, DQ3 =94
5372 22:13:25.969147 DQ4 =98, DQ5 =88, DQ6 =106, DQ7 =106
5373 22:13:25.972472 DQ8 =78, DQ9 =74, DQ10 =86, DQ11 =82
5374 22:13:25.975847 DQ12 =92, DQ13 =88, DQ14 =94, DQ15 =94
5375 22:13:25.975926
5376 22:13:25.975988
5377 22:13:25.982922 [DQSOSCAuto] RK0, (LSB)MR18= 0x2a10, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 408 ps
5378 22:13:25.986074 CH0 RK0: MR19=505, MR18=2A10
5379 22:13:25.992333 CH0_RK0: MR19=0x505, MR18=0x2A10, DQSOSC=408, MR23=63, INC=65, DEC=43
5380 22:13:25.992415
5381 22:13:25.995630 ----->DramcWriteLeveling(PI) begin...
5382 22:13:25.995710 ==
5383 22:13:25.998939 Dram Type= 6, Freq= 0, CH_0, rank 1
5384 22:13:26.002476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5385 22:13:26.002555 ==
5386 22:13:26.005588 Write leveling (Byte 0): 32 => 32
5387 22:13:26.008738 Write leveling (Byte 1): 31 => 31
5388 22:13:26.012112 DramcWriteLeveling(PI) end<-----
5389 22:13:26.012191
5390 22:13:26.012253 ==
5391 22:13:26.015683 Dram Type= 6, Freq= 0, CH_0, rank 1
5392 22:13:26.018762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5393 22:13:26.022600 ==
5394 22:13:26.022682 [Gating] SW mode calibration
5395 22:13:26.031897 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5396 22:13:26.035162 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5397 22:13:26.038852 0 14 0 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
5398 22:13:26.045423 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5399 22:13:26.049126 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5400 22:13:26.051859 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5401 22:13:26.058605 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5402 22:13:26.061678 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5403 22:13:26.065095 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5404 22:13:26.071833 0 14 28 | B1->B0 | 3434 2828 | 1 0 | (1 0) (0 0)
5405 22:13:26.074883 0 15 0 | B1->B0 | 2c2c 2323 | 0 0 | (1 0) (0 0)
5406 22:13:26.078189 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5407 22:13:26.084720 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5408 22:13:26.088072 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5409 22:13:26.091338 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5410 22:13:26.097914 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5411 22:13:26.101367 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5412 22:13:26.104711 0 15 28 | B1->B0 | 2323 3232 | 0 1 | (0 0) (0 0)
5413 22:13:26.111184 1 0 0 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
5414 22:13:26.114342 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5415 22:13:26.117752 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5416 22:13:26.124036 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5417 22:13:26.127458 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5418 22:13:26.130900 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5419 22:13:26.138004 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5420 22:13:26.141087 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5421 22:13:26.143865 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5422 22:13:26.150614 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5423 22:13:26.154148 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5424 22:13:26.157522 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5425 22:13:26.164502 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5426 22:13:26.167123 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5427 22:13:26.171285 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5428 22:13:26.176934 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5429 22:13:26.180843 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5430 22:13:26.183567 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5431 22:13:26.190426 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5432 22:13:26.193626 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5433 22:13:26.197115 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5434 22:13:26.203357 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5435 22:13:26.207321 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5436 22:13:26.210297 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5437 22:13:26.217238 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5438 22:13:26.220425 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5439 22:13:26.223180 Total UI for P1: 0, mck2ui 16
5440 22:13:26.226892 best dqsien dly found for B0: ( 1, 2, 30)
5441 22:13:26.230204 Total UI for P1: 0, mck2ui 16
5442 22:13:26.233252 best dqsien dly found for B1: ( 1, 2, 30)
5443 22:13:26.236921 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5444 22:13:26.240264 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5445 22:13:26.240338
5446 22:13:26.243455 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5447 22:13:26.246781 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5448 22:13:26.249981 [Gating] SW calibration Done
5449 22:13:26.250052 ==
5450 22:13:26.253178 Dram Type= 6, Freq= 0, CH_0, rank 1
5451 22:13:26.256787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5452 22:13:26.259981 ==
5453 22:13:26.260054 RX Vref Scan: 0
5454 22:13:26.260115
5455 22:13:26.263161 RX Vref 0 -> 0, step: 1
5456 22:13:26.263227
5457 22:13:26.266405 RX Delay -80 -> 252, step: 8
5458 22:13:26.269787 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5459 22:13:26.273375 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5460 22:13:26.276414 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5461 22:13:26.279562 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5462 22:13:26.283329 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5463 22:13:26.289467 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5464 22:13:26.293068 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5465 22:13:26.296514 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5466 22:13:26.299363 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5467 22:13:26.302772 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5468 22:13:26.309413 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5469 22:13:26.312716 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5470 22:13:26.315966 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5471 22:13:26.319579 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5472 22:13:26.322958 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5473 22:13:26.326047 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5474 22:13:26.329299 ==
5475 22:13:26.332758 Dram Type= 6, Freq= 0, CH_0, rank 1
5476 22:13:26.335805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5477 22:13:26.335881 ==
5478 22:13:26.335945 DQS Delay:
5479 22:13:26.339423 DQS0 = 0, DQS1 = 0
5480 22:13:26.339489 DQM Delay:
5481 22:13:26.342682 DQM0 = 97, DQM1 = 88
5482 22:13:26.342773 DQ Delay:
5483 22:13:26.345644 DQ0 =95, DQ1 =99, DQ2 =91, DQ3 =91
5484 22:13:26.349157 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =107
5485 22:13:26.352266 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =87
5486 22:13:26.355874 DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =91
5487 22:13:26.355941
5488 22:13:26.356005
5489 22:13:26.356061 ==
5490 22:13:26.359025 Dram Type= 6, Freq= 0, CH_0, rank 1
5491 22:13:26.362061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5492 22:13:26.362157 ==
5493 22:13:26.362244
5494 22:13:26.365801
5495 22:13:26.365892 TX Vref Scan disable
5496 22:13:26.368740 == TX Byte 0 ==
5497 22:13:26.371933 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5498 22:13:26.375692 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5499 22:13:26.378782 == TX Byte 1 ==
5500 22:13:26.382218 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5501 22:13:26.385682 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5502 22:13:26.385774 ==
5503 22:13:26.388880 Dram Type= 6, Freq= 0, CH_0, rank 1
5504 22:13:26.395363 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5505 22:13:26.395436 ==
5506 22:13:26.395498
5507 22:13:26.395561
5508 22:13:26.395617 TX Vref Scan disable
5509 22:13:26.399512 == TX Byte 0 ==
5510 22:13:26.402829 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5511 22:13:26.409379 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5512 22:13:26.409453 == TX Byte 1 ==
5513 22:13:26.412884 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5514 22:13:26.419669 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5515 22:13:26.419744
5516 22:13:26.419806 [DATLAT]
5517 22:13:26.419863 Freq=933, CH0 RK1
5518 22:13:26.419955
5519 22:13:26.422948 DATLAT Default: 0xb
5520 22:13:26.426377 0, 0xFFFF, sum = 0
5521 22:13:26.426472 1, 0xFFFF, sum = 0
5522 22:13:26.429158 2, 0xFFFF, sum = 0
5523 22:13:26.429258 3, 0xFFFF, sum = 0
5524 22:13:26.432514 4, 0xFFFF, sum = 0
5525 22:13:26.432581 5, 0xFFFF, sum = 0
5526 22:13:26.435501 6, 0xFFFF, sum = 0
5527 22:13:26.435568 7, 0xFFFF, sum = 0
5528 22:13:26.438985 8, 0xFFFF, sum = 0
5529 22:13:26.439088 9, 0xFFFF, sum = 0
5530 22:13:26.442528 10, 0x0, sum = 1
5531 22:13:26.442626 11, 0x0, sum = 2
5532 22:13:26.445578 12, 0x0, sum = 3
5533 22:13:26.445675 13, 0x0, sum = 4
5534 22:13:26.448739 best_step = 11
5535 22:13:26.448835
5536 22:13:26.448921 ==
5537 22:13:26.452034 Dram Type= 6, Freq= 0, CH_0, rank 1
5538 22:13:26.455225 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5539 22:13:26.455318 ==
5540 22:13:26.458759 RX Vref Scan: 0
5541 22:13:26.458828
5542 22:13:26.458887 RX Vref 0 -> 0, step: 1
5543 22:13:26.458943
5544 22:13:26.461701 RX Delay -61 -> 252, step: 4
5545 22:13:26.468304 iDelay=203, Bit 0, Center 92 (-1 ~ 186) 188
5546 22:13:26.471599 iDelay=203, Bit 1, Center 98 (3 ~ 194) 192
5547 22:13:26.474912 iDelay=203, Bit 2, Center 90 (-1 ~ 182) 184
5548 22:13:26.478723 iDelay=203, Bit 3, Center 94 (-1 ~ 190) 192
5549 22:13:26.482239 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5550 22:13:26.485062 iDelay=203, Bit 5, Center 88 (-9 ~ 186) 196
5551 22:13:26.491772 iDelay=203, Bit 6, Center 106 (11 ~ 202) 192
5552 22:13:26.494825 iDelay=203, Bit 7, Center 104 (11 ~ 198) 188
5553 22:13:26.498518 iDelay=203, Bit 8, Center 78 (-13 ~ 170) 184
5554 22:13:26.501371 iDelay=203, Bit 9, Center 76 (-17 ~ 170) 188
5555 22:13:26.507730 iDelay=203, Bit 10, Center 90 (-5 ~ 186) 192
5556 22:13:26.511403 iDelay=203, Bit 11, Center 80 (-13 ~ 174) 188
5557 22:13:26.514815 iDelay=203, Bit 12, Center 92 (-1 ~ 186) 188
5558 22:13:26.518372 iDelay=203, Bit 13, Center 94 (-1 ~ 190) 192
5559 22:13:26.521085 iDelay=203, Bit 14, Center 100 (11 ~ 190) 180
5560 22:13:26.528154 iDelay=203, Bit 15, Center 92 (-1 ~ 186) 188
5561 22:13:26.528229 ==
5562 22:13:26.531232 Dram Type= 6, Freq= 0, CH_0, rank 1
5563 22:13:26.534371 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5564 22:13:26.534470 ==
5565 22:13:26.534559 DQS Delay:
5566 22:13:26.537667 DQS0 = 0, DQS1 = 0
5567 22:13:26.537760 DQM Delay:
5568 22:13:26.540735 DQM0 = 96, DQM1 = 87
5569 22:13:26.540805 DQ Delay:
5570 22:13:26.543904 DQ0 =92, DQ1 =98, DQ2 =90, DQ3 =94
5571 22:13:26.547260 DQ4 =96, DQ5 =88, DQ6 =106, DQ7 =104
5572 22:13:26.550657 DQ8 =78, DQ9 =76, DQ10 =90, DQ11 =80
5573 22:13:26.554202 DQ12 =92, DQ13 =94, DQ14 =100, DQ15 =92
5574 22:13:26.554273
5575 22:13:26.554333
5576 22:13:26.563730 [DQSOSCAuto] RK1, (LSB)MR18= 0x27f7, (MSB)MR19= 0x504, tDQSOscB0 = 425 ps tDQSOscB1 = 409 ps
5577 22:13:26.563839 CH0 RK1: MR19=504, MR18=27F7
5578 22:13:26.570378 CH0_RK1: MR19=0x504, MR18=0x27F7, DQSOSC=409, MR23=63, INC=64, DEC=43
5579 22:13:26.573556 [RxdqsGatingPostProcess] freq 933
5580 22:13:26.580464 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5581 22:13:26.583920 best DQS0 dly(2T, 0.5T) = (0, 10)
5582 22:13:26.587239 best DQS1 dly(2T, 0.5T) = (0, 11)
5583 22:13:26.590882 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5584 22:13:26.593591 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5585 22:13:26.597002 best DQS0 dly(2T, 0.5T) = (0, 10)
5586 22:13:26.600027 best DQS1 dly(2T, 0.5T) = (0, 10)
5587 22:13:26.603783 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5588 22:13:26.606828 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5589 22:13:26.606908 Pre-setting of DQS Precalculation
5590 22:13:26.613505 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5591 22:13:26.613587 ==
5592 22:13:26.616928 Dram Type= 6, Freq= 0, CH_1, rank 0
5593 22:13:26.619875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5594 22:13:26.619963 ==
5595 22:13:26.626531 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5596 22:13:26.633549 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5597 22:13:26.636497 [CA 0] Center 36 (6~67) winsize 62
5598 22:13:26.639769 [CA 1] Center 37 (7~68) winsize 62
5599 22:13:26.643497 [CA 2] Center 34 (4~65) winsize 62
5600 22:13:26.646379 [CA 3] Center 34 (3~65) winsize 63
5601 22:13:26.650534 [CA 4] Center 34 (4~65) winsize 62
5602 22:13:26.653173 [CA 5] Center 33 (3~64) winsize 62
5603 22:13:26.653273
5604 22:13:26.656280 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5605 22:13:26.656349
5606 22:13:26.659706 [CATrainingPosCal] consider 1 rank data
5607 22:13:26.663011 u2DelayCellTimex100 = 270/100 ps
5608 22:13:26.666127 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5609 22:13:26.669530 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5610 22:13:26.672788 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5611 22:13:26.676493 CA3 delay=34 (3~65),Diff = 1 PI (6 cell)
5612 22:13:26.679669 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5613 22:13:26.685964 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5614 22:13:26.686060
5615 22:13:26.689295 CA PerBit enable=1, Macro0, CA PI delay=33
5616 22:13:26.689391
5617 22:13:26.692799 [CBTSetCACLKResult] CA Dly = 33
5618 22:13:26.692893 CS Dly: 6 (0~37)
5619 22:13:26.692989 ==
5620 22:13:26.696455 Dram Type= 6, Freq= 0, CH_1, rank 1
5621 22:13:26.699531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5622 22:13:26.699600 ==
5623 22:13:26.705902 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5624 22:13:26.713109 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5625 22:13:26.715635 [CA 0] Center 36 (6~67) winsize 62
5626 22:13:26.718974 [CA 1] Center 37 (7~67) winsize 61
5627 22:13:26.722538 [CA 2] Center 34 (4~65) winsize 62
5628 22:13:26.726203 [CA 3] Center 34 (4~65) winsize 62
5629 22:13:26.729138 [CA 4] Center 34 (3~65) winsize 63
5630 22:13:26.732592 [CA 5] Center 33 (3~64) winsize 62
5631 22:13:26.732707
5632 22:13:26.735960 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5633 22:13:26.736042
5634 22:13:26.738997 [CATrainingPosCal] consider 2 rank data
5635 22:13:26.742229 u2DelayCellTimex100 = 270/100 ps
5636 22:13:26.745434 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5637 22:13:26.749134 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5638 22:13:26.752004 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5639 22:13:26.758501 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5640 22:13:26.762042 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5641 22:13:26.765173 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5642 22:13:26.765262
5643 22:13:26.768413 CA PerBit enable=1, Macro0, CA PI delay=33
5644 22:13:26.768495
5645 22:13:26.772295 [CBTSetCACLKResult] CA Dly = 33
5646 22:13:26.772376 CS Dly: 7 (0~39)
5647 22:13:26.772440
5648 22:13:26.775319 ----->DramcWriteLeveling(PI) begin...
5649 22:13:26.775401 ==
5650 22:13:26.778918 Dram Type= 6, Freq= 0, CH_1, rank 0
5651 22:13:26.785430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5652 22:13:26.785518 ==
5653 22:13:26.788557 Write leveling (Byte 0): 23 => 23
5654 22:13:26.791745 Write leveling (Byte 1): 29 => 29
5655 22:13:26.795171 DramcWriteLeveling(PI) end<-----
5656 22:13:26.795253
5657 22:13:26.795318 ==
5658 22:13:26.798243 Dram Type= 6, Freq= 0, CH_1, rank 0
5659 22:13:26.801456 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5660 22:13:26.801538 ==
5661 22:13:26.804749 [Gating] SW mode calibration
5662 22:13:26.811545 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5663 22:13:26.818541 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5664 22:13:26.821428 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5665 22:13:26.825039 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5666 22:13:26.831695 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5667 22:13:26.834845 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5668 22:13:26.838495 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5669 22:13:26.844524 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5670 22:13:26.848217 0 14 24 | B1->B0 | 3333 3232 | 1 0 | (1 1) (0 1)
5671 22:13:26.851001 0 14 28 | B1->B0 | 2b2b 2929 | 1 1 | (1 0) (0 0)
5672 22:13:26.858049 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5673 22:13:26.861307 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5674 22:13:26.864453 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5675 22:13:26.871014 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5676 22:13:26.874276 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5677 22:13:26.877719 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5678 22:13:26.881109 0 15 24 | B1->B0 | 2929 2626 | 0 1 | (0 0) (1 1)
5679 22:13:26.887671 0 15 28 | B1->B0 | 3838 3939 | 0 0 | (0 0) (0 0)
5680 22:13:26.891136 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5681 22:13:26.894463 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5682 22:13:26.900858 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5683 22:13:26.904202 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5684 22:13:26.907266 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5685 22:13:26.914070 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5686 22:13:26.917100 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5687 22:13:26.920439 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5688 22:13:26.927212 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5689 22:13:26.930300 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5690 22:13:26.934176 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5691 22:13:26.940370 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5692 22:13:26.944111 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5693 22:13:26.947146 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5694 22:13:26.953577 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5695 22:13:26.956799 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5696 22:13:26.960015 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5697 22:13:26.966660 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5698 22:13:26.970111 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5699 22:13:26.973186 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5700 22:13:26.980182 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5701 22:13:26.983124 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5702 22:13:26.986779 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5703 22:13:26.993313 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5704 22:13:26.996460 Total UI for P1: 0, mck2ui 16
5705 22:13:26.999976 best dqsien dly found for B0: ( 1, 2, 24)
5706 22:13:27.003213 Total UI for P1: 0, mck2ui 16
5707 22:13:27.006331 best dqsien dly found for B1: ( 1, 2, 26)
5708 22:13:27.009972 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5709 22:13:27.013109 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5710 22:13:27.013185
5711 22:13:27.016862 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5712 22:13:27.019536 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5713 22:13:27.023463 [Gating] SW calibration Done
5714 22:13:27.023535 ==
5715 22:13:27.026163 Dram Type= 6, Freq= 0, CH_1, rank 0
5716 22:13:27.029531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5717 22:13:27.029631 ==
5718 22:13:27.032985 RX Vref Scan: 0
5719 22:13:27.033083
5720 22:13:27.033171 RX Vref 0 -> 0, step: 1
5721 22:13:27.033256
5722 22:13:27.036325 RX Delay -80 -> 252, step: 8
5723 22:13:27.042644 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5724 22:13:27.046353 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5725 22:13:27.049422 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5726 22:13:27.052655 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5727 22:13:27.056169 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5728 22:13:27.059528 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5729 22:13:27.066134 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5730 22:13:27.069580 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5731 22:13:27.072694 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5732 22:13:27.075993 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5733 22:13:27.079185 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5734 22:13:27.082526 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5735 22:13:27.089088 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5736 22:13:27.092393 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5737 22:13:27.095779 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5738 22:13:27.099207 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5739 22:13:27.099276 ==
5740 22:13:27.102481 Dram Type= 6, Freq= 0, CH_1, rank 0
5741 22:13:27.105706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5742 22:13:27.109173 ==
5743 22:13:27.109240 DQS Delay:
5744 22:13:27.109298 DQS0 = 0, DQS1 = 0
5745 22:13:27.112244 DQM Delay:
5746 22:13:27.112312 DQM0 = 101, DQM1 = 91
5747 22:13:27.115598 DQ Delay:
5748 22:13:27.118792 DQ0 =103, DQ1 =99, DQ2 =95, DQ3 =99
5749 22:13:27.122549 DQ4 =99, DQ5 =111, DQ6 =107, DQ7 =99
5750 22:13:27.125563 DQ8 =75, DQ9 =83, DQ10 =91, DQ11 =83
5751 22:13:27.128864 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =103
5752 22:13:27.128934
5753 22:13:27.128995
5754 22:13:27.129050 ==
5755 22:13:27.131947 Dram Type= 6, Freq= 0, CH_1, rank 0
5756 22:13:27.135663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5757 22:13:27.135740 ==
5758 22:13:27.135802
5759 22:13:27.135859
5760 22:13:27.138665 TX Vref Scan disable
5761 22:13:27.141878 == TX Byte 0 ==
5762 22:13:27.145370 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5763 22:13:27.148482 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5764 22:13:27.152132 == TX Byte 1 ==
5765 22:13:27.155365 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5766 22:13:27.158547 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5767 22:13:27.158620 ==
5768 22:13:27.162208 Dram Type= 6, Freq= 0, CH_1, rank 0
5769 22:13:27.165317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5770 22:13:27.168903 ==
5771 22:13:27.168974
5772 22:13:27.169035
5773 22:13:27.169091 TX Vref Scan disable
5774 22:13:27.171977 == TX Byte 0 ==
5775 22:13:27.175723 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5776 22:13:27.181813 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5777 22:13:27.181891 == TX Byte 1 ==
5778 22:13:27.184957 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5779 22:13:27.191520 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5780 22:13:27.191597
5781 22:13:27.191659 [DATLAT]
5782 22:13:27.191718 Freq=933, CH1 RK0
5783 22:13:27.191777
5784 22:13:27.195144 DATLAT Default: 0xd
5785 22:13:27.195220 0, 0xFFFF, sum = 0
5786 22:13:27.198189 1, 0xFFFF, sum = 0
5787 22:13:27.201458 2, 0xFFFF, sum = 0
5788 22:13:27.201526 3, 0xFFFF, sum = 0
5789 22:13:27.205018 4, 0xFFFF, sum = 0
5790 22:13:27.205087 5, 0xFFFF, sum = 0
5791 22:13:27.208069 6, 0xFFFF, sum = 0
5792 22:13:27.208136 7, 0xFFFF, sum = 0
5793 22:13:27.211686 8, 0xFFFF, sum = 0
5794 22:13:27.211753 9, 0xFFFF, sum = 0
5795 22:13:27.215027 10, 0x0, sum = 1
5796 22:13:27.215146 11, 0x0, sum = 2
5797 22:13:27.218416 12, 0x0, sum = 3
5798 22:13:27.218511 13, 0x0, sum = 4
5799 22:13:27.218599 best_step = 11
5800 22:13:27.221374
5801 22:13:27.221443 ==
5802 22:13:27.225000 Dram Type= 6, Freq= 0, CH_1, rank 0
5803 22:13:27.228362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5804 22:13:27.228432 ==
5805 22:13:27.228491 RX Vref Scan: 1
5806 22:13:27.228547
5807 22:13:27.231482 RX Vref 0 -> 0, step: 1
5808 22:13:27.231550
5809 22:13:27.234826 RX Delay -69 -> 252, step: 4
5810 22:13:27.234921
5811 22:13:27.238209 Set Vref, RX VrefLevel [Byte0]: 48
5812 22:13:27.241492 [Byte1]: 57
5813 22:13:27.244855
5814 22:13:27.244925 Final RX Vref Byte 0 = 48 to rank0
5815 22:13:27.247726 Final RX Vref Byte 1 = 57 to rank0
5816 22:13:27.250883 Final RX Vref Byte 0 = 48 to rank1
5817 22:13:27.254635 Final RX Vref Byte 1 = 57 to rank1==
5818 22:13:27.258061 Dram Type= 6, Freq= 0, CH_1, rank 0
5819 22:13:27.264061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5820 22:13:27.264165 ==
5821 22:13:27.264255 DQS Delay:
5822 22:13:27.267813 DQS0 = 0, DQS1 = 0
5823 22:13:27.267910 DQM Delay:
5824 22:13:27.267997 DQM0 = 101, DQM1 = 94
5825 22:13:27.271108 DQ Delay:
5826 22:13:27.274397 DQ0 =106, DQ1 =96, DQ2 =92, DQ3 =98
5827 22:13:27.277715 DQ4 =98, DQ5 =112, DQ6 =110, DQ7 =98
5828 22:13:27.280789 DQ8 =82, DQ9 =86, DQ10 =98, DQ11 =84
5829 22:13:27.284136 DQ12 =100, DQ13 =100, DQ14 =100, DQ15 =104
5830 22:13:27.284219
5831 22:13:27.284301
5832 22:13:27.290559 [DQSOSCAuto] RK0, (LSB)MR18= 0x1b0b, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 413 ps
5833 22:13:27.293792 CH1 RK0: MR19=505, MR18=1B0B
5834 22:13:27.300973 CH1_RK0: MR19=0x505, MR18=0x1B0B, DQSOSC=413, MR23=63, INC=63, DEC=42
5835 22:13:27.301057
5836 22:13:27.303806 ----->DramcWriteLeveling(PI) begin...
5837 22:13:27.303888 ==
5838 22:13:27.307191 Dram Type= 6, Freq= 0, CH_1, rank 1
5839 22:13:27.310405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5840 22:13:27.313511 ==
5841 22:13:27.313591 Write leveling (Byte 0): 30 => 30
5842 22:13:27.316976 Write leveling (Byte 1): 30 => 30
5843 22:13:27.320008 DramcWriteLeveling(PI) end<-----
5844 22:13:27.320088
5845 22:13:27.320152 ==
5846 22:13:27.324001 Dram Type= 6, Freq= 0, CH_1, rank 1
5847 22:13:27.330666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5848 22:13:27.330748 ==
5849 22:13:27.333574 [Gating] SW mode calibration
5850 22:13:27.341009 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5851 22:13:27.343338 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5852 22:13:27.349827 0 14 0 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 0)
5853 22:13:27.353588 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5854 22:13:27.356312 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5855 22:13:27.363041 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5856 22:13:27.366475 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5857 22:13:27.369649 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
5858 22:13:27.376449 0 14 24 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
5859 22:13:27.379884 0 14 28 | B1->B0 | 2929 2f2f | 0 0 | (0 0) (0 1)
5860 22:13:27.383237 0 15 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5861 22:13:27.389688 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5862 22:13:27.392873 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5863 22:13:27.396533 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5864 22:13:27.402836 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5865 22:13:27.406400 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5866 22:13:27.409867 0 15 24 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
5867 22:13:27.416108 0 15 28 | B1->B0 | 3c3c 3131 | 0 0 | (0 0) (0 0)
5868 22:13:27.419624 1 0 0 | B1->B0 | 4646 3c3c | 0 1 | (0 0) (0 0)
5869 22:13:27.422913 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5870 22:13:27.429192 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5871 22:13:27.432454 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5872 22:13:27.435991 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5873 22:13:27.442426 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5874 22:13:27.445475 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5875 22:13:27.449162 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5876 22:13:27.455543 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5877 22:13:27.459006 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5878 22:13:27.462199 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5879 22:13:27.468962 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5880 22:13:27.472339 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5881 22:13:27.475214 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5882 22:13:27.482616 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5883 22:13:27.485575 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5884 22:13:27.488474 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5885 22:13:27.495381 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5886 22:13:27.498665 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5887 22:13:27.502039 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5888 22:13:27.508687 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5889 22:13:27.511774 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5890 22:13:27.515035 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5891 22:13:27.521536 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5892 22:13:27.524730 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5893 22:13:27.528250 Total UI for P1: 0, mck2ui 16
5894 22:13:27.531493 best dqsien dly found for B0: ( 1, 2, 28)
5895 22:13:27.534650 Total UI for P1: 0, mck2ui 16
5896 22:13:27.537825 best dqsien dly found for B1: ( 1, 2, 26)
5897 22:13:27.541085 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5898 22:13:27.544683 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5899 22:13:27.544766
5900 22:13:27.548097 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5901 22:13:27.550903 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5902 22:13:27.554662 [Gating] SW calibration Done
5903 22:13:27.554770 ==
5904 22:13:27.558018 Dram Type= 6, Freq= 0, CH_1, rank 1
5905 22:13:27.561475 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5906 22:13:27.561559 ==
5907 22:13:27.564595 RX Vref Scan: 0
5908 22:13:27.564680
5909 22:13:27.568333 RX Vref 0 -> 0, step: 1
5910 22:13:27.568414
5911 22:13:27.568479 RX Delay -80 -> 252, step: 8
5912 22:13:27.574645 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5913 22:13:27.577653 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5914 22:13:27.581611 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5915 22:13:27.584425 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5916 22:13:27.587618 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5917 22:13:27.590992 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5918 22:13:27.597421 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5919 22:13:27.600947 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5920 22:13:27.604172 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5921 22:13:27.607416 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5922 22:13:27.610683 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5923 22:13:27.617661 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5924 22:13:27.621104 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5925 22:13:27.624020 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5926 22:13:27.627292 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5927 22:13:27.630975 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5928 22:13:27.631081 ==
5929 22:13:27.634119 Dram Type= 6, Freq= 0, CH_1, rank 1
5930 22:13:27.641426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5931 22:13:27.641509 ==
5932 22:13:27.641574 DQS Delay:
5933 22:13:27.643796 DQS0 = 0, DQS1 = 0
5934 22:13:27.643878 DQM Delay:
5935 22:13:27.647090 DQM0 = 101, DQM1 = 93
5936 22:13:27.647186 DQ Delay:
5937 22:13:27.650526 DQ0 =107, DQ1 =99, DQ2 =91, DQ3 =99
5938 22:13:27.653659 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =95
5939 22:13:27.657505 DQ8 =79, DQ9 =83, DQ10 =95, DQ11 =83
5940 22:13:27.660706 DQ12 =103, DQ13 =99, DQ14 =99, DQ15 =103
5941 22:13:27.660827
5942 22:13:27.660960
5943 22:13:27.661019 ==
5944 22:13:27.663824 Dram Type= 6, Freq= 0, CH_1, rank 1
5945 22:13:27.666969 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5946 22:13:27.667052 ==
5947 22:13:27.667157
5948 22:13:27.667218
5949 22:13:27.670534 TX Vref Scan disable
5950 22:13:27.673511 == TX Byte 0 ==
5951 22:13:27.677042 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5952 22:13:27.680276 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5953 22:13:27.683461 == TX Byte 1 ==
5954 22:13:27.686720 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5955 22:13:27.690172 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5956 22:13:27.690255 ==
5957 22:13:27.693353 Dram Type= 6, Freq= 0, CH_1, rank 1
5958 22:13:27.700020 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5959 22:13:27.700103 ==
5960 22:13:27.700170
5961 22:13:27.700230
5962 22:13:27.700287 TX Vref Scan disable
5963 22:13:27.704370 == TX Byte 0 ==
5964 22:13:27.707585 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5965 22:13:27.713836 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5966 22:13:27.713919 == TX Byte 1 ==
5967 22:13:27.717522 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5968 22:13:27.724141 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5969 22:13:27.724224
5970 22:13:27.724289 [DATLAT]
5971 22:13:27.724349 Freq=933, CH1 RK1
5972 22:13:27.724406
5973 22:13:27.727534 DATLAT Default: 0xb
5974 22:13:27.730556 0, 0xFFFF, sum = 0
5975 22:13:27.730640 1, 0xFFFF, sum = 0
5976 22:13:27.733898 2, 0xFFFF, sum = 0
5977 22:13:27.733981 3, 0xFFFF, sum = 0
5978 22:13:27.736928 4, 0xFFFF, sum = 0
5979 22:13:27.737011 5, 0xFFFF, sum = 0
5980 22:13:27.740525 6, 0xFFFF, sum = 0
5981 22:13:27.740608 7, 0xFFFF, sum = 0
5982 22:13:27.744056 8, 0xFFFF, sum = 0
5983 22:13:27.744140 9, 0xFFFF, sum = 0
5984 22:13:27.747069 10, 0x0, sum = 1
5985 22:13:27.747152 11, 0x0, sum = 2
5986 22:13:27.750615 12, 0x0, sum = 3
5987 22:13:27.750698 13, 0x0, sum = 4
5988 22:13:27.750765 best_step = 11
5989 22:13:27.753912
5990 22:13:27.753994 ==
5991 22:13:27.757006 Dram Type= 6, Freq= 0, CH_1, rank 1
5992 22:13:27.760440 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5993 22:13:27.760547 ==
5994 22:13:27.760643 RX Vref Scan: 0
5995 22:13:27.760730
5996 22:13:27.763583 RX Vref 0 -> 0, step: 1
5997 22:13:27.763672
5998 22:13:27.767086 RX Delay -61 -> 252, step: 4
5999 22:13:27.773591 iDelay=207, Bit 0, Center 106 (19 ~ 194) 176
6000 22:13:27.776915 iDelay=207, Bit 1, Center 96 (11 ~ 182) 172
6001 22:13:27.780001 iDelay=207, Bit 2, Center 90 (3 ~ 178) 176
6002 22:13:27.783217 iDelay=207, Bit 3, Center 98 (15 ~ 182) 168
6003 22:13:27.786613 iDelay=207, Bit 4, Center 100 (11 ~ 190) 180
6004 22:13:27.793138 iDelay=207, Bit 5, Center 112 (27 ~ 198) 172
6005 22:13:27.796238 iDelay=207, Bit 6, Center 116 (27 ~ 206) 180
6006 22:13:27.799700 iDelay=207, Bit 7, Center 98 (7 ~ 190) 184
6007 22:13:27.802813 iDelay=207, Bit 8, Center 82 (-9 ~ 174) 184
6008 22:13:27.806498 iDelay=207, Bit 9, Center 82 (-9 ~ 174) 184
6009 22:13:27.809479 iDelay=207, Bit 10, Center 92 (-1 ~ 186) 188
6010 22:13:27.815961 iDelay=207, Bit 11, Center 82 (-9 ~ 174) 184
6011 22:13:27.819301 iDelay=207, Bit 12, Center 102 (11 ~ 194) 184
6012 22:13:27.822536 iDelay=207, Bit 13, Center 102 (11 ~ 194) 184
6013 22:13:27.825853 iDelay=207, Bit 14, Center 102 (11 ~ 194) 184
6014 22:13:27.832481 iDelay=207, Bit 15, Center 102 (11 ~ 194) 184
6015 22:13:27.832564 ==
6016 22:13:27.835531 Dram Type= 6, Freq= 0, CH_1, rank 1
6017 22:13:27.839119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
6018 22:13:27.839202 ==
6019 22:13:27.839268 DQS Delay:
6020 22:13:27.842701 DQS0 = 0, DQS1 = 0
6021 22:13:27.842783 DQM Delay:
6022 22:13:27.845492 DQM0 = 102, DQM1 = 93
6023 22:13:27.845574 DQ Delay:
6024 22:13:27.848729 DQ0 =106, DQ1 =96, DQ2 =90, DQ3 =98
6025 22:13:27.852465 DQ4 =100, DQ5 =112, DQ6 =116, DQ7 =98
6026 22:13:27.855452 DQ8 =82, DQ9 =82, DQ10 =92, DQ11 =82
6027 22:13:27.859020 DQ12 =102, DQ13 =102, DQ14 =102, DQ15 =102
6028 22:13:27.859142
6029 22:13:27.859208
6030 22:13:27.868525 [DQSOSCAuto] RK1, (LSB)MR18= 0xa02, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 418 ps
6031 22:13:27.872556 CH1 RK1: MR19=505, MR18=A02
6032 22:13:27.875184 CH1_RK1: MR19=0x505, MR18=0xA02, DQSOSC=418, MR23=63, INC=62, DEC=41
6033 22:13:27.878800 [RxdqsGatingPostProcess] freq 933
6034 22:13:27.885832 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6035 22:13:27.888504 best DQS0 dly(2T, 0.5T) = (0, 10)
6036 22:13:27.891856 best DQS1 dly(2T, 0.5T) = (0, 10)
6037 22:13:27.895253 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6038 22:13:27.898483 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6039 22:13:27.901955 best DQS0 dly(2T, 0.5T) = (0, 10)
6040 22:13:27.904824 best DQS1 dly(2T, 0.5T) = (0, 10)
6041 22:13:27.908164 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6042 22:13:27.911556 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6043 22:13:27.914805 Pre-setting of DQS Precalculation
6044 22:13:27.918335 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6045 22:13:27.924890 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6046 22:13:27.931441 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6047 22:13:27.931524
6048 22:13:27.931589
6049 22:13:27.934915 [Calibration Summary] 1866 Mbps
6050 22:13:27.938013 CH 0, Rank 0
6051 22:13:27.938095 SW Impedance : PASS
6052 22:13:27.941087 DUTY Scan : NO K
6053 22:13:27.944406 ZQ Calibration : PASS
6054 22:13:27.944488 Jitter Meter : NO K
6055 22:13:27.948324 CBT Training : PASS
6056 22:13:27.951764 Write leveling : PASS
6057 22:13:27.951846 RX DQS gating : PASS
6058 22:13:27.954444 RX DQ/DQS(RDDQC) : PASS
6059 22:13:27.958032 TX DQ/DQS : PASS
6060 22:13:27.958114 RX DATLAT : PASS
6061 22:13:27.960834 RX DQ/DQS(Engine): PASS
6062 22:13:27.964250 TX OE : NO K
6063 22:13:27.964332 All Pass.
6064 22:13:27.964399
6065 22:13:27.964457 CH 0, Rank 1
6066 22:13:27.967691 SW Impedance : PASS
6067 22:13:27.970935 DUTY Scan : NO K
6068 22:13:27.971043 ZQ Calibration : PASS
6069 22:13:27.974216 Jitter Meter : NO K
6070 22:13:27.977956 CBT Training : PASS
6071 22:13:27.978038 Write leveling : PASS
6072 22:13:27.981127 RX DQS gating : PASS
6073 22:13:27.981235 RX DQ/DQS(RDDQC) : PASS
6074 22:13:27.984269 TX DQ/DQS : PASS
6075 22:13:27.987963 RX DATLAT : PASS
6076 22:13:27.988045 RX DQ/DQS(Engine): PASS
6077 22:13:27.990805 TX OE : NO K
6078 22:13:27.990913 All Pass.
6079 22:13:27.991006
6080 22:13:27.994359 CH 1, Rank 0
6081 22:13:27.994440 SW Impedance : PASS
6082 22:13:27.997593 DUTY Scan : NO K
6083 22:13:28.000493 ZQ Calibration : PASS
6084 22:13:28.000600 Jitter Meter : NO K
6085 22:13:28.004264 CBT Training : PASS
6086 22:13:28.006990 Write leveling : PASS
6087 22:13:28.007088 RX DQS gating : PASS
6088 22:13:28.010384 RX DQ/DQS(RDDQC) : PASS
6089 22:13:28.013934 TX DQ/DQS : PASS
6090 22:13:28.014007 RX DATLAT : PASS
6091 22:13:28.017177 RX DQ/DQS(Engine): PASS
6092 22:13:28.020448 TX OE : NO K
6093 22:13:28.020524 All Pass.
6094 22:13:28.020587
6095 22:13:28.020651 CH 1, Rank 1
6096 22:13:28.023798 SW Impedance : PASS
6097 22:13:28.026909 DUTY Scan : NO K
6098 22:13:28.026980 ZQ Calibration : PASS
6099 22:13:28.030361 Jitter Meter : NO K
6100 22:13:28.033626 CBT Training : PASS
6101 22:13:28.033694 Write leveling : PASS
6102 22:13:28.036707 RX DQS gating : PASS
6103 22:13:28.040501 RX DQ/DQS(RDDQC) : PASS
6104 22:13:28.040569 TX DQ/DQS : PASS
6105 22:13:28.043393 RX DATLAT : PASS
6106 22:13:28.046857 RX DQ/DQS(Engine): PASS
6107 22:13:28.046925 TX OE : NO K
6108 22:13:28.046985 All Pass.
6109 22:13:28.050329
6110 22:13:28.050398 DramC Write-DBI off
6111 22:13:28.053357 PER_BANK_REFRESH: Hybrid Mode
6112 22:13:28.053425 TX_TRACKING: ON
6113 22:13:28.063261 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6114 22:13:28.067210 [FAST_K] Save calibration result to emmc
6115 22:13:28.070035 dramc_set_vcore_voltage set vcore to 650000
6116 22:13:28.073220 Read voltage for 400, 6
6117 22:13:28.073288 Vio18 = 0
6118 22:13:28.076903 Vcore = 650000
6119 22:13:28.076976 Vdram = 0
6120 22:13:28.077037 Vddq = 0
6121 22:13:28.077095 Vmddr = 0
6122 22:13:28.083585 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6123 22:13:28.089944 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6124 22:13:28.090022 MEM_TYPE=3, freq_sel=20
6125 22:13:28.093269 sv_algorithm_assistance_LP4_800
6126 22:13:28.096426 ============ PULL DRAM RESETB DOWN ============
6127 22:13:28.102967 ========== PULL DRAM RESETB DOWN end =========
6128 22:13:28.106557 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6129 22:13:28.109441 ===================================
6130 22:13:28.113036 LPDDR4 DRAM CONFIGURATION
6131 22:13:28.117013 ===================================
6132 22:13:28.117084 EX_ROW_EN[0] = 0x0
6133 22:13:28.119459 EX_ROW_EN[1] = 0x0
6134 22:13:28.123014 LP4Y_EN = 0x0
6135 22:13:28.123126 WORK_FSP = 0x0
6136 22:13:28.126334 WL = 0x2
6137 22:13:28.126403 RL = 0x2
6138 22:13:28.129339 BL = 0x2
6139 22:13:28.129407 RPST = 0x0
6140 22:13:28.132809 RD_PRE = 0x0
6141 22:13:28.132882 WR_PRE = 0x1
6142 22:13:28.136202 WR_PST = 0x0
6143 22:13:28.136275 DBI_WR = 0x0
6144 22:13:28.139527 DBI_RD = 0x0
6145 22:13:28.139593 OTF = 0x1
6146 22:13:28.142589 ===================================
6147 22:13:28.145848 ===================================
6148 22:13:28.149128 ANA top config
6149 22:13:28.152321 ===================================
6150 22:13:28.152405 DLL_ASYNC_EN = 0
6151 22:13:28.156059 ALL_SLAVE_EN = 1
6152 22:13:28.159318 NEW_RANK_MODE = 1
6153 22:13:28.162425 DLL_IDLE_MODE = 1
6154 22:13:28.165982 LP45_APHY_COMB_EN = 1
6155 22:13:28.166052 TX_ODT_DIS = 1
6156 22:13:28.169217 NEW_8X_MODE = 1
6157 22:13:28.172146 ===================================
6158 22:13:28.175313 ===================================
6159 22:13:28.178998 data_rate = 800
6160 22:13:28.182419 CKR = 1
6161 22:13:28.185605 DQ_P2S_RATIO = 4
6162 22:13:28.188645 ===================================
6163 22:13:28.192120 CA_P2S_RATIO = 4
6164 22:13:28.192195 DQ_CA_OPEN = 0
6165 22:13:28.195538 DQ_SEMI_OPEN = 1
6166 22:13:28.198819 CA_SEMI_OPEN = 1
6167 22:13:28.202646 CA_FULL_RATE = 0
6168 22:13:28.205159 DQ_CKDIV4_EN = 0
6169 22:13:28.208461 CA_CKDIV4_EN = 1
6170 22:13:28.208533 CA_PREDIV_EN = 0
6171 22:13:28.212291 PH8_DLY = 0
6172 22:13:28.215339 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6173 22:13:28.218585 DQ_AAMCK_DIV = 0
6174 22:13:28.222058 CA_AAMCK_DIV = 0
6175 22:13:28.225533 CA_ADMCK_DIV = 4
6176 22:13:28.225604 DQ_TRACK_CA_EN = 0
6177 22:13:28.228629 CA_PICK = 800
6178 22:13:28.231715 CA_MCKIO = 400
6179 22:13:28.234857 MCKIO_SEMI = 400
6180 22:13:28.238283 PLL_FREQ = 3016
6181 22:13:28.241897 DQ_UI_PI_RATIO = 32
6182 22:13:28.245063 CA_UI_PI_RATIO = 32
6183 22:13:28.248366 ===================================
6184 22:13:28.251522 ===================================
6185 22:13:28.251605 memory_type:LPDDR4
6186 22:13:28.254963 GP_NUM : 10
6187 22:13:28.258088 SRAM_EN : 1
6188 22:13:28.258161 MD32_EN : 0
6189 22:13:28.261835 ===================================
6190 22:13:28.264407 [ANA_INIT] >>>>>>>>>>>>>>
6191 22:13:28.268068 <<<<<< [CONFIGURE PHASE]: ANA_TX
6192 22:13:28.271215 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6193 22:13:28.274255 ===================================
6194 22:13:28.278008 data_rate = 800,PCW = 0X7400
6195 22:13:28.281464 ===================================
6196 22:13:28.284721 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6197 22:13:28.287957 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6198 22:13:28.301051 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6199 22:13:28.304236 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6200 22:13:28.307678 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6201 22:13:28.311003 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6202 22:13:28.314082 [ANA_INIT] flow start
6203 22:13:28.317328 [ANA_INIT] PLL >>>>>>>>
6204 22:13:28.317411 [ANA_INIT] PLL <<<<<<<<
6205 22:13:28.320582 [ANA_INIT] MIDPI >>>>>>>>
6206 22:13:28.324054 [ANA_INIT] MIDPI <<<<<<<<
6207 22:13:28.324138 [ANA_INIT] DLL >>>>>>>>
6208 22:13:28.327348 [ANA_INIT] flow end
6209 22:13:28.330618 ============ LP4 DIFF to SE enter ============
6210 22:13:28.337089 ============ LP4 DIFF to SE exit ============
6211 22:13:28.337173 [ANA_INIT] <<<<<<<<<<<<<
6212 22:13:28.340261 [Flow] Enable top DCM control >>>>>
6213 22:13:28.343710 [Flow] Enable top DCM control <<<<<
6214 22:13:28.347235 Enable DLL master slave shuffle
6215 22:13:28.353856 ==============================================================
6216 22:13:28.353940 Gating Mode config
6217 22:13:28.360233 ==============================================================
6218 22:13:28.363738 Config description:
6219 22:13:28.373589 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6220 22:13:28.380367 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6221 22:13:28.383310 SELPH_MODE 0: By rank 1: By Phase
6222 22:13:28.390529 ==============================================================
6223 22:13:28.393796 GAT_TRACK_EN = 0
6224 22:13:28.396692 RX_GATING_MODE = 2
6225 22:13:28.396775 RX_GATING_TRACK_MODE = 2
6226 22:13:28.399683 SELPH_MODE = 1
6227 22:13:28.403219 PICG_EARLY_EN = 1
6228 22:13:28.406478 VALID_LAT_VALUE = 1
6229 22:13:28.412826 ==============================================================
6230 22:13:28.416021 Enter into Gating configuration >>>>
6231 22:13:28.419999 Exit from Gating configuration <<<<
6232 22:13:28.422746 Enter into DVFS_PRE_config >>>>>
6233 22:13:28.432798 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6234 22:13:28.435902 Exit from DVFS_PRE_config <<<<<
6235 22:13:28.439530 Enter into PICG configuration >>>>
6236 22:13:28.442277 Exit from PICG configuration <<<<
6237 22:13:28.445687 [RX_INPUT] configuration >>>>>
6238 22:13:28.449060 [RX_INPUT] configuration <<<<<
6239 22:13:28.453138 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6240 22:13:28.459341 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6241 22:13:28.465573 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6242 22:13:28.472493 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6243 22:13:28.478874 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6244 22:13:28.482639 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6245 22:13:28.489219 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6246 22:13:28.492552 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6247 22:13:28.495494 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6248 22:13:28.499002 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6249 22:13:28.505798 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6250 22:13:28.508931 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6251 22:13:28.512600 ===================================
6252 22:13:28.515567 LPDDR4 DRAM CONFIGURATION
6253 22:13:28.518496 ===================================
6254 22:13:28.518578 EX_ROW_EN[0] = 0x0
6255 22:13:28.521869 EX_ROW_EN[1] = 0x0
6256 22:13:28.521975 LP4Y_EN = 0x0
6257 22:13:28.525451 WORK_FSP = 0x0
6258 22:13:28.525532 WL = 0x2
6259 22:13:28.529037 RL = 0x2
6260 22:13:28.529118 BL = 0x2
6261 22:13:28.531872 RPST = 0x0
6262 22:13:28.535333 RD_PRE = 0x0
6263 22:13:28.535417 WR_PRE = 0x1
6264 22:13:28.538264 WR_PST = 0x0
6265 22:13:28.538348 DBI_WR = 0x0
6266 22:13:28.541713 DBI_RD = 0x0
6267 22:13:28.541797 OTF = 0x1
6268 22:13:28.544999 ===================================
6269 22:13:28.548200 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6270 22:13:28.555015 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6271 22:13:28.558383 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6272 22:13:28.561316 ===================================
6273 22:13:28.565111 LPDDR4 DRAM CONFIGURATION
6274 22:13:28.568106 ===================================
6275 22:13:28.568191 EX_ROW_EN[0] = 0x10
6276 22:13:28.571643 EX_ROW_EN[1] = 0x0
6277 22:13:28.571728 LP4Y_EN = 0x0
6278 22:13:28.574680 WORK_FSP = 0x0
6279 22:13:28.574764 WL = 0x2
6280 22:13:28.577769 RL = 0x2
6281 22:13:28.581716 BL = 0x2
6282 22:13:28.581800 RPST = 0x0
6283 22:13:28.584706 RD_PRE = 0x0
6284 22:13:28.584790 WR_PRE = 0x1
6285 22:13:28.588029 WR_PST = 0x0
6286 22:13:28.588112 DBI_WR = 0x0
6287 22:13:28.591085 DBI_RD = 0x0
6288 22:13:28.591182 OTF = 0x1
6289 22:13:28.594401 ===================================
6290 22:13:28.601700 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6291 22:13:28.604859 nWR fixed to 30
6292 22:13:28.608521 [ModeRegInit_LP4] CH0 RK0
6293 22:13:28.608604 [ModeRegInit_LP4] CH0 RK1
6294 22:13:28.611495 [ModeRegInit_LP4] CH1 RK0
6295 22:13:28.614763 [ModeRegInit_LP4] CH1 RK1
6296 22:13:28.614846 match AC timing 19
6297 22:13:28.621407 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6298 22:13:28.624802 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6299 22:13:28.628120 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6300 22:13:28.634611 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6301 22:13:28.637960 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6302 22:13:28.638047 ==
6303 22:13:28.641236 Dram Type= 6, Freq= 0, CH_0, rank 0
6304 22:13:28.644330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6305 22:13:28.644414 ==
6306 22:13:28.651309 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6307 22:13:28.657658 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6308 22:13:28.661046 [CA 0] Center 36 (8~64) winsize 57
6309 22:13:28.664041 [CA 1] Center 36 (8~64) winsize 57
6310 22:13:28.667418 [CA 2] Center 36 (8~64) winsize 57
6311 22:13:28.670642 [CA 3] Center 36 (8~64) winsize 57
6312 22:13:28.674241 [CA 4] Center 36 (8~64) winsize 57
6313 22:13:28.677291 [CA 5] Center 36 (8~64) winsize 57
6314 22:13:28.677391
6315 22:13:28.680842 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6316 22:13:28.680942
6317 22:13:28.683618 [CATrainingPosCal] consider 1 rank data
6318 22:13:28.687528 u2DelayCellTimex100 = 270/100 ps
6319 22:13:28.690625 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6320 22:13:28.693692 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6321 22:13:28.697177 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6322 22:13:28.700581 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6323 22:13:28.704978 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6324 22:13:28.707234 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6325 22:13:28.707318
6326 22:13:28.713476 CA PerBit enable=1, Macro0, CA PI delay=36
6327 22:13:28.713596
6328 22:13:28.713680 [CBTSetCACLKResult] CA Dly = 36
6329 22:13:28.717007 CS Dly: 1 (0~32)
6330 22:13:28.717090 ==
6331 22:13:28.720213 Dram Type= 6, Freq= 0, CH_0, rank 1
6332 22:13:28.724198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6333 22:13:28.724638 ==
6334 22:13:28.730532 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6335 22:13:28.737139 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6336 22:13:28.740700 [CA 0] Center 36 (8~64) winsize 57
6337 22:13:28.744434 [CA 1] Center 36 (8~64) winsize 57
6338 22:13:28.746997 [CA 2] Center 36 (8~64) winsize 57
6339 22:13:28.750688 [CA 3] Center 36 (8~64) winsize 57
6340 22:13:28.753471 [CA 4] Center 36 (8~64) winsize 57
6341 22:13:28.753954 [CA 5] Center 36 (8~64) winsize 57
6342 22:13:28.757685
6343 22:13:28.760578 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6344 22:13:28.761148
6345 22:13:28.763584 [CATrainingPosCal] consider 2 rank data
6346 22:13:28.766881 u2DelayCellTimex100 = 270/100 ps
6347 22:13:28.770333 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6348 22:13:28.774061 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6349 22:13:28.776813 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6350 22:13:28.779864 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6351 22:13:28.783043 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6352 22:13:28.786878 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6353 22:13:28.787509
6354 22:13:28.790265 CA PerBit enable=1, Macro0, CA PI delay=36
6355 22:13:28.793090
6356 22:13:28.793567 [CBTSetCACLKResult] CA Dly = 36
6357 22:13:28.796468 CS Dly: 1 (0~32)
6358 22:13:28.796944
6359 22:13:28.799783 ----->DramcWriteLeveling(PI) begin...
6360 22:13:28.800385 ==
6361 22:13:28.802712 Dram Type= 6, Freq= 0, CH_0, rank 0
6362 22:13:28.806510 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6363 22:13:28.807088 ==
6364 22:13:28.809835 Write leveling (Byte 0): 40 => 8
6365 22:13:28.813461 Write leveling (Byte 1): 32 => 0
6366 22:13:28.816102 DramcWriteLeveling(PI) end<-----
6367 22:13:28.816487
6368 22:13:28.816795 ==
6369 22:13:28.819234 Dram Type= 6, Freq= 0, CH_0, rank 0
6370 22:13:28.822554 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6371 22:13:28.825708 ==
6372 22:13:28.825928 [Gating] SW mode calibration
6373 22:13:28.835748 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6374 22:13:28.839364 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6375 22:13:28.842733 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6376 22:13:28.849259 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6377 22:13:28.852642 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6378 22:13:28.855852 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6379 22:13:28.862499 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6380 22:13:28.865694 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6381 22:13:28.869306 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6382 22:13:28.876114 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6383 22:13:28.879240 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6384 22:13:28.882230 Total UI for P1: 0, mck2ui 16
6385 22:13:28.885992 best dqsien dly found for B0: ( 0, 14, 24)
6386 22:13:28.889088 Total UI for P1: 0, mck2ui 16
6387 22:13:28.892889 best dqsien dly found for B1: ( 0, 14, 24)
6388 22:13:28.895974 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6389 22:13:28.898974 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6390 22:13:28.899455
6391 22:13:28.902888 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6392 22:13:28.906441 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6393 22:13:28.908865 [Gating] SW calibration Done
6394 22:13:28.909320 ==
6395 22:13:28.912935 Dram Type= 6, Freq= 0, CH_0, rank 0
6396 22:13:28.916091 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6397 22:13:28.918999 ==
6398 22:13:28.919610 RX Vref Scan: 0
6399 22:13:28.919978
6400 22:13:28.922576 RX Vref 0 -> 0, step: 1
6401 22:13:28.923029
6402 22:13:28.925800 RX Delay -410 -> 252, step: 16
6403 22:13:28.929026 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6404 22:13:28.931957 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6405 22:13:28.935405 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6406 22:13:28.942154 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6407 22:13:28.945554 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6408 22:13:28.948829 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6409 22:13:28.951864 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6410 22:13:28.958989 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6411 22:13:28.962079 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6412 22:13:28.965671 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6413 22:13:28.968802 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6414 22:13:28.975303 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6415 22:13:28.978277 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6416 22:13:28.981565 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6417 22:13:28.989286 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6418 22:13:28.991983 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6419 22:13:28.992466 ==
6420 22:13:28.995171 Dram Type= 6, Freq= 0, CH_0, rank 0
6421 22:13:28.998494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6422 22:13:28.998943 ==
6423 22:13:29.001724 DQS Delay:
6424 22:13:29.002198 DQS0 = 43, DQS1 = 59
6425 22:13:29.002678 DQM Delay:
6426 22:13:29.004932 DQM0 = 9, DQM1 = 12
6427 22:13:29.005410 DQ Delay:
6428 22:13:29.008356 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =0
6429 22:13:29.011439 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6430 22:13:29.014996 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6431 22:13:29.018529 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6432 22:13:29.019143
6433 22:13:29.019629
6434 22:13:29.020081 ==
6435 22:13:29.021787 Dram Type= 6, Freq= 0, CH_0, rank 0
6436 22:13:29.024615 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6437 22:13:29.025095 ==
6438 22:13:29.028204
6439 22:13:29.028679
6440 22:13:29.029152 TX Vref Scan disable
6441 22:13:29.031551 == TX Byte 0 ==
6442 22:13:29.034500 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6443 22:13:29.038472 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6444 22:13:29.041341 == TX Byte 1 ==
6445 22:13:29.045081 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6446 22:13:29.047946 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6447 22:13:29.048492 ==
6448 22:13:29.050987 Dram Type= 6, Freq= 0, CH_0, rank 0
6449 22:13:29.058387 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6450 22:13:29.058974 ==
6451 22:13:29.059502
6452 22:13:29.059954
6453 22:13:29.060395 TX Vref Scan disable
6454 22:13:29.061159 == TX Byte 0 ==
6455 22:13:29.064154 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6456 22:13:29.067807 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6457 22:13:29.071336 == TX Byte 1 ==
6458 22:13:29.074010 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6459 22:13:29.077537 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6460 22:13:29.080901
6461 22:13:29.081377 [DATLAT]
6462 22:13:29.081853 Freq=400, CH0 RK0
6463 22:13:29.082306
6464 22:13:29.083858 DATLAT Default: 0xf
6465 22:13:29.084337 0, 0xFFFF, sum = 0
6466 22:13:29.087666 1, 0xFFFF, sum = 0
6467 22:13:29.088154 2, 0xFFFF, sum = 0
6468 22:13:29.090862 3, 0xFFFF, sum = 0
6469 22:13:29.091487 4, 0xFFFF, sum = 0
6470 22:13:29.094469 5, 0xFFFF, sum = 0
6471 22:13:29.097025 6, 0xFFFF, sum = 0
6472 22:13:29.097512 7, 0xFFFF, sum = 0
6473 22:13:29.100898 8, 0xFFFF, sum = 0
6474 22:13:29.101366 9, 0xFFFF, sum = 0
6475 22:13:29.103909 10, 0xFFFF, sum = 0
6476 22:13:29.104389 11, 0xFFFF, sum = 0
6477 22:13:29.107221 12, 0xFFFF, sum = 0
6478 22:13:29.107799 13, 0x0, sum = 1
6479 22:13:29.110555 14, 0x0, sum = 2
6480 22:13:29.111171 15, 0x0, sum = 3
6481 22:13:29.114259 16, 0x0, sum = 4
6482 22:13:29.114832 best_step = 14
6483 22:13:29.115242
6484 22:13:29.115588 ==
6485 22:13:29.116937 Dram Type= 6, Freq= 0, CH_0, rank 0
6486 22:13:29.120770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6487 22:13:29.123573 ==
6488 22:13:29.124037 RX Vref Scan: 1
6489 22:13:29.124407
6490 22:13:29.127167 RX Vref 0 -> 0, step: 1
6491 22:13:29.127632
6492 22:13:29.130233 RX Delay -359 -> 252, step: 8
6493 22:13:29.130718
6494 22:13:29.131113 Set Vref, RX VrefLevel [Byte0]: 61
6495 22:13:29.133330 [Byte1]: 51
6496 22:13:29.139767
6497 22:13:29.140343 Final RX Vref Byte 0 = 61 to rank0
6498 22:13:29.142566 Final RX Vref Byte 1 = 51 to rank0
6499 22:13:29.145951 Final RX Vref Byte 0 = 61 to rank1
6500 22:13:29.149615 Final RX Vref Byte 1 = 51 to rank1==
6501 22:13:29.152366 Dram Type= 6, Freq= 0, CH_0, rank 0
6502 22:13:29.159666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6503 22:13:29.160233 ==
6504 22:13:29.160608 DQS Delay:
6505 22:13:29.162581 DQS0 = 48, DQS1 = 60
6506 22:13:29.163187 DQM Delay:
6507 22:13:29.163738 DQM0 = 11, DQM1 = 12
6508 22:13:29.166124 DQ Delay:
6509 22:13:29.169289 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6510 22:13:29.172066 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6511 22:13:29.172540 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6512 22:13:29.179262 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6513 22:13:29.179826
6514 22:13:29.180200
6515 22:13:29.185274 [DQSOSCAuto] RK0, (LSB)MR18= 0xc083, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 386 ps
6516 22:13:29.188752 CH0 RK0: MR19=C0C, MR18=C083
6517 22:13:29.195788 CH0_RK0: MR19=0xC0C, MR18=0xC083, DQSOSC=386, MR23=63, INC=396, DEC=264
6518 22:13:29.196360 ==
6519 22:13:29.198894 Dram Type= 6, Freq= 0, CH_0, rank 1
6520 22:13:29.202087 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6521 22:13:29.202557 ==
6522 22:13:29.205595 [Gating] SW mode calibration
6523 22:13:29.212201 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6524 22:13:29.218586 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6525 22:13:29.222002 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6526 22:13:29.225151 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6527 22:13:29.232024 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6528 22:13:29.235002 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6529 22:13:29.238470 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6530 22:13:29.244976 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6531 22:13:29.249190 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6532 22:13:29.251858 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6533 22:13:29.258702 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6534 22:13:29.259309 Total UI for P1: 0, mck2ui 16
6535 22:13:29.264744 best dqsien dly found for B0: ( 0, 14, 24)
6536 22:13:29.265234 Total UI for P1: 0, mck2ui 16
6537 22:13:29.271930 best dqsien dly found for B1: ( 0, 14, 24)
6538 22:13:29.275635 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6539 22:13:29.278693 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6540 22:13:29.279296
6541 22:13:29.281725 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6542 22:13:29.284794 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6543 22:13:29.288411 [Gating] SW calibration Done
6544 22:13:29.288879 ==
6545 22:13:29.291419 Dram Type= 6, Freq= 0, CH_0, rank 1
6546 22:13:29.294599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6547 22:13:29.295218 ==
6548 22:13:29.298171 RX Vref Scan: 0
6549 22:13:29.298746
6550 22:13:29.299180 RX Vref 0 -> 0, step: 1
6551 22:13:29.301372
6552 22:13:29.301837 RX Delay -410 -> 252, step: 16
6553 22:13:29.307955 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6554 22:13:29.311320 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6555 22:13:29.314399 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6556 22:13:29.317867 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6557 22:13:29.324216 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6558 22:13:29.327833 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6559 22:13:29.331216 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6560 22:13:29.334522 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6561 22:13:29.340549 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6562 22:13:29.344311 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6563 22:13:29.347337 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6564 22:13:29.354001 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6565 22:13:29.358324 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6566 22:13:29.360767 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6567 22:13:29.364256 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6568 22:13:29.370396 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6569 22:13:29.370867 ==
6570 22:13:29.373748 Dram Type= 6, Freq= 0, CH_0, rank 1
6571 22:13:29.377892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6572 22:13:29.378603 ==
6573 22:13:29.379147 DQS Delay:
6574 22:13:29.381288 DQS0 = 43, DQS1 = 59
6575 22:13:29.381753 DQM Delay:
6576 22:13:29.383843 DQM0 = 9, DQM1 = 16
6577 22:13:29.384311 DQ Delay:
6578 22:13:29.387425 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =0
6579 22:13:29.390850 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6580 22:13:29.394287 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6581 22:13:29.397298 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6582 22:13:29.397867
6583 22:13:29.398239
6584 22:13:29.398584 ==
6585 22:13:29.400460 Dram Type= 6, Freq= 0, CH_0, rank 1
6586 22:13:29.403954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6587 22:13:29.404538 ==
6588 22:13:29.404918
6589 22:13:29.405261
6590 22:13:29.406991 TX Vref Scan disable
6591 22:13:29.407504 == TX Byte 0 ==
6592 22:13:29.414098 Update DQ dly =586 (4 ,2, 10) DQ OEN =(3 ,3)
6593 22:13:29.416805 Update DQM dly =586 (4 ,2, 10) DQM OEN =(3 ,3)
6594 22:13:29.417300 == TX Byte 1 ==
6595 22:13:29.423617 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6596 22:13:29.427176 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6597 22:13:29.427740 ==
6598 22:13:29.430044 Dram Type= 6, Freq= 0, CH_0, rank 1
6599 22:13:29.433875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6600 22:13:29.434441 ==
6601 22:13:29.434817
6602 22:13:29.437015
6603 22:13:29.437476 TX Vref Scan disable
6604 22:13:29.439918 == TX Byte 0 ==
6605 22:13:29.443608 Update DQ dly =586 (4 ,2, 10) DQ OEN =(3 ,3)
6606 22:13:29.446466 Update DQM dly =586 (4 ,2, 10) DQM OEN =(3 ,3)
6607 22:13:29.449972 == TX Byte 1 ==
6608 22:13:29.452769 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6609 22:13:29.456565 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6610 22:13:29.457133
6611 22:13:29.457502 [DATLAT]
6612 22:13:29.459815 Freq=400, CH0 RK1
6613 22:13:29.460276
6614 22:13:29.463414 DATLAT Default: 0xe
6615 22:13:29.463976 0, 0xFFFF, sum = 0
6616 22:13:29.466691 1, 0xFFFF, sum = 0
6617 22:13:29.467179 2, 0xFFFF, sum = 0
6618 22:13:29.469878 3, 0xFFFF, sum = 0
6619 22:13:29.470388 4, 0xFFFF, sum = 0
6620 22:13:29.473135 5, 0xFFFF, sum = 0
6621 22:13:29.473604 6, 0xFFFF, sum = 0
6622 22:13:29.476521 7, 0xFFFF, sum = 0
6623 22:13:29.476992 8, 0xFFFF, sum = 0
6624 22:13:29.479650 9, 0xFFFF, sum = 0
6625 22:13:29.480122 10, 0xFFFF, sum = 0
6626 22:13:29.483255 11, 0xFFFF, sum = 0
6627 22:13:29.483832 12, 0xFFFF, sum = 0
6628 22:13:29.485977 13, 0x0, sum = 1
6629 22:13:29.486455 14, 0x0, sum = 2
6630 22:13:29.489767 15, 0x0, sum = 3
6631 22:13:29.490293 16, 0x0, sum = 4
6632 22:13:29.492938 best_step = 14
6633 22:13:29.493507
6634 22:13:29.493875 ==
6635 22:13:29.496516 Dram Type= 6, Freq= 0, CH_0, rank 1
6636 22:13:29.499285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6637 22:13:29.499764 ==
6638 22:13:29.502299 RX Vref Scan: 0
6639 22:13:29.502765
6640 22:13:29.503167 RX Vref 0 -> 0, step: 1
6641 22:13:29.503524
6642 22:13:29.505861 RX Delay -359 -> 252, step: 8
6643 22:13:29.514175 iDelay=217, Bit 0, Center -40 (-279 ~ 200) 480
6644 22:13:29.517607 iDelay=217, Bit 1, Center -36 (-279 ~ 208) 488
6645 22:13:29.520555 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6646 22:13:29.527347 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6647 22:13:29.530498 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6648 22:13:29.534009 iDelay=217, Bit 5, Center -44 (-287 ~ 200) 488
6649 22:13:29.537000 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6650 22:13:29.543919 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6651 22:13:29.547000 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6652 22:13:29.550334 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6653 22:13:29.553574 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
6654 22:13:29.560277 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6655 22:13:29.563414 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6656 22:13:29.566536 iDelay=217, Bit 13, Center -36 (-279 ~ 208) 488
6657 22:13:29.570129 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6658 22:13:29.576522 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6659 22:13:29.577088 ==
6660 22:13:29.579821 Dram Type= 6, Freq= 0, CH_0, rank 1
6661 22:13:29.583409 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6662 22:13:29.583987 ==
6663 22:13:29.586346 DQS Delay:
6664 22:13:29.586850 DQS0 = 44, DQS1 = 60
6665 22:13:29.587306 DQM Delay:
6666 22:13:29.589683 DQM0 = 7, DQM1 = 16
6667 22:13:29.590146 DQ Delay:
6668 22:13:29.593265 DQ0 =4, DQ1 =8, DQ2 =4, DQ3 =4
6669 22:13:29.596177 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6670 22:13:29.599713 DQ8 =8, DQ9 =0, DQ10 =20, DQ11 =8
6671 22:13:29.602970 DQ12 =20, DQ13 =24, DQ14 =24, DQ15 =24
6672 22:13:29.603574
6673 22:13:29.603946
6674 22:13:29.609711 [DQSOSCAuto] RK1, (LSB)MR18= 0xbc47, (MSB)MR19= 0xc0c, tDQSOscB0 = 400 ps tDQSOscB1 = 386 ps
6675 22:13:29.613260 CH0 RK1: MR19=C0C, MR18=BC47
6676 22:13:29.619806 CH0_RK1: MR19=0xC0C, MR18=0xBC47, DQSOSC=386, MR23=63, INC=396, DEC=264
6677 22:13:29.622728 [RxdqsGatingPostProcess] freq 400
6678 22:13:29.629515 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6679 22:13:29.632943 best DQS0 dly(2T, 0.5T) = (0, 10)
6680 22:13:29.636164 best DQS1 dly(2T, 0.5T) = (0, 10)
6681 22:13:29.639560 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6682 22:13:29.642530 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6683 22:13:29.645446 best DQS0 dly(2T, 0.5T) = (0, 10)
6684 22:13:29.645914 best DQS1 dly(2T, 0.5T) = (0, 10)
6685 22:13:29.649092 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6686 22:13:29.652669 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6687 22:13:29.655682 Pre-setting of DQS Precalculation
6688 22:13:29.662252 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6689 22:13:29.662823 ==
6690 22:13:29.666225 Dram Type= 6, Freq= 0, CH_1, rank 0
6691 22:13:29.669217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6692 22:13:29.669797 ==
6693 22:13:29.675820 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6694 22:13:29.682288 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6695 22:13:29.685498 [CA 0] Center 36 (8~64) winsize 57
6696 22:13:29.688599 [CA 1] Center 36 (8~64) winsize 57
6697 22:13:29.692261 [CA 2] Center 36 (8~64) winsize 57
6698 22:13:29.692728 [CA 3] Center 36 (8~64) winsize 57
6699 22:13:29.695433 [CA 4] Center 36 (8~64) winsize 57
6700 22:13:29.698990 [CA 5] Center 36 (8~64) winsize 57
6701 22:13:29.699649
6702 22:13:29.705463 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6703 22:13:29.706033
6704 22:13:29.708498 [CATrainingPosCal] consider 1 rank data
6705 22:13:29.711589 u2DelayCellTimex100 = 270/100 ps
6706 22:13:29.714798 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6707 22:13:29.718350 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6708 22:13:29.721687 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6709 22:13:29.724574 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6710 22:13:29.728198 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6711 22:13:29.731700 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6712 22:13:29.732329
6713 22:13:29.734558 CA PerBit enable=1, Macro0, CA PI delay=36
6714 22:13:29.735022
6715 22:13:29.738153 [CBTSetCACLKResult] CA Dly = 36
6716 22:13:29.742000 CS Dly: 1 (0~32)
6717 22:13:29.742569 ==
6718 22:13:29.744823 Dram Type= 6, Freq= 0, CH_1, rank 1
6719 22:13:29.747809 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6720 22:13:29.748277 ==
6721 22:13:29.754785 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6722 22:13:29.761344 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6723 22:13:29.764301 [CA 0] Center 36 (8~64) winsize 57
6724 22:13:29.767529 [CA 1] Center 36 (8~64) winsize 57
6725 22:13:29.767998 [CA 2] Center 36 (8~64) winsize 57
6726 22:13:29.771376 [CA 3] Center 36 (8~64) winsize 57
6727 22:13:29.774175 [CA 4] Center 36 (8~64) winsize 57
6728 22:13:29.777700 [CA 5] Center 36 (8~64) winsize 57
6729 22:13:29.778271
6730 22:13:29.780657 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6731 22:13:29.783948
6732 22:13:29.787757 [CATrainingPosCal] consider 2 rank data
6733 22:13:29.788419 u2DelayCellTimex100 = 270/100 ps
6734 22:13:29.793749 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6735 22:13:29.797144 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6736 22:13:29.800554 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6737 22:13:29.803635 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6738 22:13:29.807506 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6739 22:13:29.810503 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6740 22:13:29.810967
6741 22:13:29.813981 CA PerBit enable=1, Macro0, CA PI delay=36
6742 22:13:29.814445
6743 22:13:29.816939 [CBTSetCACLKResult] CA Dly = 36
6744 22:13:29.820174 CS Dly: 1 (0~32)
6745 22:13:29.820637
6746 22:13:29.823704 ----->DramcWriteLeveling(PI) begin...
6747 22:13:29.824173 ==
6748 22:13:29.826775 Dram Type= 6, Freq= 0, CH_1, rank 0
6749 22:13:29.829904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6750 22:13:29.830374 ==
6751 22:13:29.833643 Write leveling (Byte 0): 40 => 8
6752 22:13:29.837217 Write leveling (Byte 1): 40 => 8
6753 22:13:29.839939 DramcWriteLeveling(PI) end<-----
6754 22:13:29.840399
6755 22:13:29.840786 ==
6756 22:13:29.843111 Dram Type= 6, Freq= 0, CH_1, rank 0
6757 22:13:29.846788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6758 22:13:29.847418 ==
6759 22:13:29.849859 [Gating] SW mode calibration
6760 22:13:29.856895 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6761 22:13:29.863121 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6762 22:13:29.866092 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6763 22:13:29.872704 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6764 22:13:29.876242 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6765 22:13:29.879841 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6766 22:13:29.886142 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6767 22:13:29.889599 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6768 22:13:29.892681 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6769 22:13:29.895843 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6770 22:13:29.902653 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6771 22:13:29.906302 Total UI for P1: 0, mck2ui 16
6772 22:13:29.909550 best dqsien dly found for B0: ( 0, 14, 24)
6773 22:13:29.912880 Total UI for P1: 0, mck2ui 16
6774 22:13:29.915798 best dqsien dly found for B1: ( 0, 14, 24)
6775 22:13:29.919175 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6776 22:13:29.922699 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6777 22:13:29.923204
6778 22:13:29.926231 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6779 22:13:29.929555 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6780 22:13:29.932571 [Gating] SW calibration Done
6781 22:13:29.933034 ==
6782 22:13:29.935807 Dram Type= 6, Freq= 0, CH_1, rank 0
6783 22:13:29.939032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6784 22:13:29.939649 ==
6785 22:13:29.942753 RX Vref Scan: 0
6786 22:13:29.943361
6787 22:13:29.945992 RX Vref 0 -> 0, step: 1
6788 22:13:29.946567
6789 22:13:29.946942 RX Delay -410 -> 252, step: 16
6790 22:13:29.952873 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6791 22:13:29.955756 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6792 22:13:29.959912 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6793 22:13:29.965447 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6794 22:13:29.969372 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6795 22:13:29.972109 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6796 22:13:29.975499 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6797 22:13:29.982549 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6798 22:13:29.985878 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6799 22:13:29.989467 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6800 22:13:29.992272 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6801 22:13:29.998947 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6802 22:13:30.002108 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6803 22:13:30.005515 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6804 22:13:30.008529 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6805 22:13:30.015199 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6806 22:13:30.015669 ==
6807 22:13:30.018475 Dram Type= 6, Freq= 0, CH_1, rank 0
6808 22:13:30.022188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6809 22:13:30.022657 ==
6810 22:13:30.023028 DQS Delay:
6811 22:13:30.025065 DQS0 = 43, DQS1 = 51
6812 22:13:30.025526 DQM Delay:
6813 22:13:30.028848 DQM0 = 12, DQM1 = 15
6814 22:13:30.029415 DQ Delay:
6815 22:13:30.032191 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6816 22:13:30.035596 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6817 22:13:30.038237 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =0
6818 22:13:30.041836 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6819 22:13:30.042409
6820 22:13:30.042779
6821 22:13:30.043159 ==
6822 22:13:30.045559 Dram Type= 6, Freq= 0, CH_1, rank 0
6823 22:13:30.048640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6824 22:13:30.049226 ==
6825 22:13:30.049608
6826 22:13:30.049946
6827 22:13:30.051969 TX Vref Scan disable
6828 22:13:30.055201 == TX Byte 0 ==
6829 22:13:30.058650 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6830 22:13:30.061876 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6831 22:13:30.065458 == TX Byte 1 ==
6832 22:13:30.068165 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6833 22:13:30.072557 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6834 22:13:30.073126 ==
6835 22:13:30.075011 Dram Type= 6, Freq= 0, CH_1, rank 0
6836 22:13:30.078446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6837 22:13:30.078913 ==
6838 22:13:30.079360
6839 22:13:30.081861
6840 22:13:30.082427 TX Vref Scan disable
6841 22:13:30.085302 == TX Byte 0 ==
6842 22:13:30.088206 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6843 22:13:30.091561 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6844 22:13:30.095015 == TX Byte 1 ==
6845 22:13:30.098346 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6846 22:13:30.101418 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6847 22:13:30.101984
6848 22:13:30.102358 [DATLAT]
6849 22:13:30.104836 Freq=400, CH1 RK0
6850 22:13:30.105401
6851 22:13:30.107926 DATLAT Default: 0xf
6852 22:13:30.108391 0, 0xFFFF, sum = 0
6853 22:13:30.110964 1, 0xFFFF, sum = 0
6854 22:13:30.111467 2, 0xFFFF, sum = 0
6855 22:13:30.114566 3, 0xFFFF, sum = 0
6856 22:13:30.115169 4, 0xFFFF, sum = 0
6857 22:13:30.117546 5, 0xFFFF, sum = 0
6858 22:13:30.118016 6, 0xFFFF, sum = 0
6859 22:13:30.121138 7, 0xFFFF, sum = 0
6860 22:13:30.121715 8, 0xFFFF, sum = 0
6861 22:13:30.124581 9, 0xFFFF, sum = 0
6862 22:13:30.125049 10, 0xFFFF, sum = 0
6863 22:13:30.128046 11, 0xFFFF, sum = 0
6864 22:13:30.128619 12, 0xFFFF, sum = 0
6865 22:13:30.131053 13, 0x0, sum = 1
6866 22:13:30.131563 14, 0x0, sum = 2
6867 22:13:30.134807 15, 0x0, sum = 3
6868 22:13:30.135442 16, 0x0, sum = 4
6869 22:13:30.137531 best_step = 14
6870 22:13:30.138089
6871 22:13:30.138460 ==
6872 22:13:30.141029 Dram Type= 6, Freq= 0, CH_1, rank 0
6873 22:13:30.144295 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6874 22:13:30.144862 ==
6875 22:13:30.147628 RX Vref Scan: 1
6876 22:13:30.148087
6877 22:13:30.148458 RX Vref 0 -> 0, step: 1
6878 22:13:30.148804
6879 22:13:30.150888 RX Delay -343 -> 252, step: 8
6880 22:13:30.151510
6881 22:13:30.154355 Set Vref, RX VrefLevel [Byte0]: 48
6882 22:13:30.157642 [Byte1]: 57
6883 22:13:30.162102
6884 22:13:30.162661 Final RX Vref Byte 0 = 48 to rank0
6885 22:13:30.165604 Final RX Vref Byte 1 = 57 to rank0
6886 22:13:30.168591 Final RX Vref Byte 0 = 48 to rank1
6887 22:13:30.171905 Final RX Vref Byte 1 = 57 to rank1==
6888 22:13:30.175467 Dram Type= 6, Freq= 0, CH_1, rank 0
6889 22:13:30.182039 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6890 22:13:30.182629 ==
6891 22:13:30.183008 DQS Delay:
6892 22:13:30.185191 DQS0 = 44, DQS1 = 56
6893 22:13:30.185755 DQM Delay:
6894 22:13:30.186128 DQM0 = 8, DQM1 = 13
6895 22:13:30.188873 DQ Delay:
6896 22:13:30.191924 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6897 22:13:30.192388 DQ4 =4, DQ5 =20, DQ6 =16, DQ7 =4
6898 22:13:30.194977 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6899 22:13:30.198675 DQ12 =24, DQ13 =16, DQ14 =20, DQ15 =24
6900 22:13:30.199297
6901 22:13:30.201471
6902 22:13:30.208227 [DQSOSCAuto] RK0, (LSB)MR18= 0x966d, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 391 ps
6903 22:13:30.211669 CH1 RK0: MR19=C0C, MR18=966D
6904 22:13:30.218259 CH1_RK0: MR19=0xC0C, MR18=0x966D, DQSOSC=391, MR23=63, INC=386, DEC=257
6905 22:13:30.218853 ==
6906 22:13:30.221594 Dram Type= 6, Freq= 0, CH_1, rank 1
6907 22:13:30.224552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6908 22:13:30.225077 ==
6909 22:13:30.228485 [Gating] SW mode calibration
6910 22:13:30.234475 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6911 22:13:30.241658 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6912 22:13:30.244257 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6913 22:13:30.247716 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6914 22:13:30.254293 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6915 22:13:30.257602 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6916 22:13:30.261321 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6917 22:13:30.267646 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6918 22:13:30.270714 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6919 22:13:30.273640 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6920 22:13:30.280775 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6921 22:13:30.283578 Total UI for P1: 0, mck2ui 16
6922 22:13:30.287210 best dqsien dly found for B0: ( 0, 14, 24)
6923 22:13:30.290135 Total UI for P1: 0, mck2ui 16
6924 22:13:30.293792 best dqsien dly found for B1: ( 0, 14, 24)
6925 22:13:30.297040 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6926 22:13:30.300014 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6927 22:13:30.300479
6928 22:13:30.303443 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6929 22:13:30.306629 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6930 22:13:30.309927 [Gating] SW calibration Done
6931 22:13:30.310487 ==
6932 22:13:30.313914 Dram Type= 6, Freq= 0, CH_1, rank 1
6933 22:13:30.316401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6934 22:13:30.316918 ==
6935 22:13:30.319842 RX Vref Scan: 0
6936 22:13:30.320307
6937 22:13:30.323408 RX Vref 0 -> 0, step: 1
6938 22:13:30.323969
6939 22:13:30.326306 RX Delay -410 -> 252, step: 16
6940 22:13:30.329803 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6941 22:13:30.333172 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6942 22:13:30.336314 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6943 22:13:30.343096 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6944 22:13:30.346435 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6945 22:13:30.349886 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6946 22:13:30.353298 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6947 22:13:30.359523 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6948 22:13:30.362801 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6949 22:13:30.365804 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6950 22:13:30.369434 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6951 22:13:30.375653 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6952 22:13:30.378987 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6953 22:13:30.382268 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6954 22:13:30.389247 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6955 22:13:30.392239 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6956 22:13:30.392708 ==
6957 22:13:30.395862 Dram Type= 6, Freq= 0, CH_1, rank 1
6958 22:13:30.398844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6959 22:13:30.399453 ==
6960 22:13:30.402324 DQS Delay:
6961 22:13:30.402890 DQS0 = 51, DQS1 = 59
6962 22:13:30.405131 DQM Delay:
6963 22:13:30.405596 DQM0 = 19, DQM1 = 22
6964 22:13:30.405964 DQ Delay:
6965 22:13:30.408808 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6966 22:13:30.412279 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6967 22:13:30.415831 DQ8 =0, DQ9 =16, DQ10 =16, DQ11 =16
6968 22:13:30.418891 DQ12 =32, DQ13 =32, DQ14 =32, DQ15 =32
6969 22:13:30.419527
6970 22:13:30.419901
6971 22:13:30.420243 ==
6972 22:13:30.422486 Dram Type= 6, Freq= 0, CH_1, rank 1
6973 22:13:30.428737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6974 22:13:30.429310 ==
6975 22:13:30.429680
6976 22:13:30.430019
6977 22:13:30.430339 TX Vref Scan disable
6978 22:13:30.431941 == TX Byte 0 ==
6979 22:13:30.435274 Update DQ dly =586 (4 ,2, 10) DQ OEN =(3 ,3)
6980 22:13:30.442096 Update DQM dly =586 (4 ,2, 10) DQM OEN =(3 ,3)
6981 22:13:30.442668 == TX Byte 1 ==
6982 22:13:30.445237 Update DQ dly =586 (4 ,2, 10) DQ OEN =(3 ,3)
6983 22:13:30.451723 Update DQM dly =586 (4 ,2, 10) DQM OEN =(3 ,3)
6984 22:13:30.452293 ==
6985 22:13:30.455723 Dram Type= 6, Freq= 0, CH_1, rank 1
6986 22:13:30.458588 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6987 22:13:30.459088 ==
6988 22:13:30.459484
6989 22:13:30.459824
6990 22:13:30.461619 TX Vref Scan disable
6991 22:13:30.462079 == TX Byte 0 ==
6992 22:13:30.465421 Update DQ dly =586 (4 ,2, 10) DQ OEN =(3 ,3)
6993 22:13:30.471328 Update DQM dly =586 (4 ,2, 10) DQM OEN =(3 ,3)
6994 22:13:30.471956 == TX Byte 1 ==
6995 22:13:30.474674 Update DQ dly =586 (4 ,2, 10) DQ OEN =(3 ,3)
6996 22:13:30.481344 Update DQM dly =586 (4 ,2, 10) DQM OEN =(3 ,3)
6997 22:13:30.481896
6998 22:13:30.482269 [DATLAT]
6999 22:13:30.484831 Freq=400, CH1 RK1
7000 22:13:30.485398
7001 22:13:30.485772 DATLAT Default: 0xe
7002 22:13:30.488444 0, 0xFFFF, sum = 0
7003 22:13:30.489023 1, 0xFFFF, sum = 0
7004 22:13:30.491482 2, 0xFFFF, sum = 0
7005 22:13:30.492014 3, 0xFFFF, sum = 0
7006 22:13:30.494327 4, 0xFFFF, sum = 0
7007 22:13:30.494800 5, 0xFFFF, sum = 0
7008 22:13:30.497692 6, 0xFFFF, sum = 0
7009 22:13:30.498162 7, 0xFFFF, sum = 0
7010 22:13:30.501310 8, 0xFFFF, sum = 0
7011 22:13:30.501940 9, 0xFFFF, sum = 0
7012 22:13:30.504539 10, 0xFFFF, sum = 0
7013 22:13:30.507767 11, 0xFFFF, sum = 0
7014 22:13:30.508349 12, 0xFFFF, sum = 0
7015 22:13:30.511133 13, 0x0, sum = 1
7016 22:13:30.511722 14, 0x0, sum = 2
7017 22:13:30.512102 15, 0x0, sum = 3
7018 22:13:30.514104 16, 0x0, sum = 4
7019 22:13:30.514577 best_step = 14
7020 22:13:30.514946
7021 22:13:30.517416 ==
7022 22:13:30.517891 Dram Type= 6, Freq= 0, CH_1, rank 1
7023 22:13:30.524039 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7024 22:13:30.524626 ==
7025 22:13:30.525005 RX Vref Scan: 0
7026 22:13:30.525345
7027 22:13:30.527180 RX Vref 0 -> 0, step: 1
7028 22:13:30.527644
7029 22:13:30.530679 RX Delay -359 -> 252, step: 8
7030 22:13:30.537424 iDelay=225, Bit 0, Center -32 (-271 ~ 208) 480
7031 22:13:30.540857 iDelay=225, Bit 1, Center -40 (-279 ~ 200) 480
7032 22:13:30.543897 iDelay=225, Bit 2, Center -48 (-287 ~ 192) 480
7033 22:13:30.551133 iDelay=225, Bit 3, Center -40 (-279 ~ 200) 480
7034 22:13:30.553911 iDelay=225, Bit 4, Center -36 (-279 ~ 208) 488
7035 22:13:30.556962 iDelay=225, Bit 5, Center -24 (-263 ~ 216) 480
7036 22:13:30.560175 iDelay=225, Bit 6, Center -20 (-263 ~ 224) 488
7037 22:13:30.566824 iDelay=225, Bit 7, Center -36 (-279 ~ 208) 488
7038 22:13:30.570344 iDelay=225, Bit 8, Center -56 (-303 ~ 192) 496
7039 22:13:30.573961 iDelay=225, Bit 9, Center -56 (-303 ~ 192) 496
7040 22:13:30.576774 iDelay=225, Bit 10, Center -40 (-287 ~ 208) 496
7041 22:13:30.583730 iDelay=225, Bit 11, Center -56 (-303 ~ 192) 496
7042 22:13:30.586575 iDelay=225, Bit 12, Center -36 (-287 ~ 216) 504
7043 22:13:30.590342 iDelay=225, Bit 13, Center -40 (-287 ~ 208) 496
7044 22:13:30.593349 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
7045 22:13:30.599960 iDelay=225, Bit 15, Center -36 (-287 ~ 216) 504
7046 22:13:30.600463 ==
7047 22:13:30.603162 Dram Type= 6, Freq= 0, CH_1, rank 1
7048 22:13:30.606816 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7049 22:13:30.607333 ==
7050 22:13:30.607802 DQS Delay:
7051 22:13:30.610031 DQS0 = 48, DQS1 = 56
7052 22:13:30.610638 DQM Delay:
7053 22:13:30.612864 DQM0 = 13, DQM1 = 11
7054 22:13:30.613439 DQ Delay:
7055 22:13:30.616429 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
7056 22:13:30.619754 DQ4 =12, DQ5 =24, DQ6 =28, DQ7 =12
7057 22:13:30.623332 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
7058 22:13:30.626701 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
7059 22:13:30.627184
7060 22:13:30.627704
7061 22:13:30.636774 [DQSOSCAuto] RK1, (LSB)MR18= 0x6f5d, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 395 ps
7062 22:13:30.637354 CH1 RK1: MR19=C0C, MR18=6F5D
7063 22:13:30.642894 CH1_RK1: MR19=0xC0C, MR18=0x6F5D, DQSOSC=395, MR23=63, INC=378, DEC=252
7064 22:13:30.646678 [RxdqsGatingPostProcess] freq 400
7065 22:13:30.653229 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7066 22:13:30.656134 best DQS0 dly(2T, 0.5T) = (0, 10)
7067 22:13:30.659586 best DQS1 dly(2T, 0.5T) = (0, 10)
7068 22:13:30.662730 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7069 22:13:30.666366 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7070 22:13:30.669350 best DQS0 dly(2T, 0.5T) = (0, 10)
7071 22:13:30.669810 best DQS1 dly(2T, 0.5T) = (0, 10)
7072 22:13:30.673379 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7073 22:13:30.676099 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7074 22:13:30.679247 Pre-setting of DQS Precalculation
7075 22:13:30.685894 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7076 22:13:30.692856 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7077 22:13:30.699002 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7078 22:13:30.699600
7079 22:13:30.699964
7080 22:13:30.702200 [Calibration Summary] 800 Mbps
7081 22:13:30.705896 CH 0, Rank 0
7082 22:13:30.706445 SW Impedance : PASS
7083 22:13:30.709104 DUTY Scan : NO K
7084 22:13:30.709526 ZQ Calibration : PASS
7085 22:13:30.712274 Jitter Meter : NO K
7086 22:13:30.715413 CBT Training : PASS
7087 22:13:30.715834 Write leveling : PASS
7088 22:13:30.719364 RX DQS gating : PASS
7089 22:13:30.721973 RX DQ/DQS(RDDQC) : PASS
7090 22:13:30.722444 TX DQ/DQS : PASS
7091 22:13:30.725427 RX DATLAT : PASS
7092 22:13:30.729081 RX DQ/DQS(Engine): PASS
7093 22:13:30.729530 TX OE : NO K
7094 22:13:30.732061 All Pass.
7095 22:13:30.732480
7096 22:13:30.733056 CH 0, Rank 1
7097 22:13:30.735630 SW Impedance : PASS
7098 22:13:30.736051 DUTY Scan : NO K
7099 22:13:30.738813 ZQ Calibration : PASS
7100 22:13:30.742424 Jitter Meter : NO K
7101 22:13:30.742847 CBT Training : PASS
7102 22:13:30.745394 Write leveling : NO K
7103 22:13:30.748566 RX DQS gating : PASS
7104 22:13:30.748985 RX DQ/DQS(RDDQC) : PASS
7105 22:13:30.751738 TX DQ/DQS : PASS
7106 22:13:30.755005 RX DATLAT : PASS
7107 22:13:30.755471 RX DQ/DQS(Engine): PASS
7108 22:13:30.758647 TX OE : NO K
7109 22:13:30.759213 All Pass.
7110 22:13:30.759677
7111 22:13:30.761587 CH 1, Rank 0
7112 22:13:30.762146 SW Impedance : PASS
7113 22:13:30.765607 DUTY Scan : NO K
7114 22:13:30.768955 ZQ Calibration : PASS
7115 22:13:30.769380 Jitter Meter : NO K
7116 22:13:30.772282 CBT Training : PASS
7117 22:13:30.772796 Write leveling : PASS
7118 22:13:30.775391 RX DQS gating : PASS
7119 22:13:30.778698 RX DQ/DQS(RDDQC) : PASS
7120 22:13:30.779298 TX DQ/DQS : PASS
7121 22:13:30.782061 RX DATLAT : PASS
7122 22:13:30.785268 RX DQ/DQS(Engine): PASS
7123 22:13:30.785758 TX OE : NO K
7124 22:13:30.788291 All Pass.
7125 22:13:30.788830
7126 22:13:30.789243 CH 1, Rank 1
7127 22:13:30.791285 SW Impedance : PASS
7128 22:13:30.791820 DUTY Scan : NO K
7129 22:13:30.794696 ZQ Calibration : PASS
7130 22:13:30.798270 Jitter Meter : NO K
7131 22:13:30.798801 CBT Training : PASS
7132 22:13:30.801769 Write leveling : NO K
7133 22:13:30.804557 RX DQS gating : PASS
7134 22:13:30.804978 RX DQ/DQS(RDDQC) : PASS
7135 22:13:30.808286 TX DQ/DQS : PASS
7136 22:13:30.811343 RX DATLAT : PASS
7137 22:13:30.811766 RX DQ/DQS(Engine): PASS
7138 22:13:30.814606 TX OE : NO K
7139 22:13:30.815026 All Pass.
7140 22:13:30.815395
7141 22:13:30.818049 DramC Write-DBI off
7142 22:13:30.821017 PER_BANK_REFRESH: Hybrid Mode
7143 22:13:30.821438 TX_TRACKING: ON
7144 22:13:30.831005 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7145 22:13:30.834307 [FAST_K] Save calibration result to emmc
7146 22:13:30.837744 dramc_set_vcore_voltage set vcore to 725000
7147 22:13:30.841332 Read voltage for 1600, 0
7148 22:13:30.841753 Vio18 = 0
7149 22:13:30.842087 Vcore = 725000
7150 22:13:30.844364 Vdram = 0
7151 22:13:30.844780 Vddq = 0
7152 22:13:30.845109 Vmddr = 0
7153 22:13:30.850999 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7154 22:13:30.854521 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7155 22:13:30.857419 MEM_TYPE=3, freq_sel=13
7156 22:13:30.861303 sv_algorithm_assistance_LP4_3733
7157 22:13:30.864390 ============ PULL DRAM RESETB DOWN ============
7158 22:13:30.868126 ========== PULL DRAM RESETB DOWN end =========
7159 22:13:30.874189 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7160 22:13:30.877709 ===================================
7161 22:13:30.881273 LPDDR4 DRAM CONFIGURATION
7162 22:13:30.883946 ===================================
7163 22:13:30.884467 EX_ROW_EN[0] = 0x0
7164 22:13:30.887506 EX_ROW_EN[1] = 0x0
7165 22:13:30.888019 LP4Y_EN = 0x0
7166 22:13:30.891365 WORK_FSP = 0x1
7167 22:13:30.891888 WL = 0x5
7168 22:13:30.893982 RL = 0x5
7169 22:13:30.894578 BL = 0x2
7170 22:13:30.897273 RPST = 0x0
7171 22:13:30.897692 RD_PRE = 0x0
7172 22:13:30.900237 WR_PRE = 0x1
7173 22:13:30.904102 WR_PST = 0x1
7174 22:13:30.904520 DBI_WR = 0x0
7175 22:13:30.907102 DBI_RD = 0x0
7176 22:13:30.907521 OTF = 0x1
7177 22:13:30.910536 ===================================
7178 22:13:30.914665 ===================================
7179 22:13:30.915121 ANA top config
7180 22:13:30.917207 ===================================
7181 22:13:30.920393 DLL_ASYNC_EN = 0
7182 22:13:30.923946 ALL_SLAVE_EN = 0
7183 22:13:30.927033 NEW_RANK_MODE = 1
7184 22:13:30.930231 DLL_IDLE_MODE = 1
7185 22:13:30.930755 LP45_APHY_COMB_EN = 1
7186 22:13:30.933269 TX_ODT_DIS = 0
7187 22:13:30.937021 NEW_8X_MODE = 1
7188 22:13:30.940257 ===================================
7189 22:13:30.943527 ===================================
7190 22:13:30.947011 data_rate = 3200
7191 22:13:30.949725 CKR = 1
7192 22:13:30.953046 DQ_P2S_RATIO = 8
7193 22:13:30.956385 ===================================
7194 22:13:30.956832 CA_P2S_RATIO = 8
7195 22:13:30.960119 DQ_CA_OPEN = 0
7196 22:13:30.963521 DQ_SEMI_OPEN = 0
7197 22:13:30.966237 CA_SEMI_OPEN = 0
7198 22:13:30.969823 CA_FULL_RATE = 0
7199 22:13:30.973025 DQ_CKDIV4_EN = 0
7200 22:13:30.973575 CA_CKDIV4_EN = 0
7201 22:13:30.976128 CA_PREDIV_EN = 0
7202 22:13:30.979677 PH8_DLY = 12
7203 22:13:30.982977 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7204 22:13:30.986196 DQ_AAMCK_DIV = 4
7205 22:13:30.989467 CA_AAMCK_DIV = 4
7206 22:13:30.990006 CA_ADMCK_DIV = 4
7207 22:13:30.992501 DQ_TRACK_CA_EN = 0
7208 22:13:30.996955 CA_PICK = 1600
7209 22:13:30.999302 CA_MCKIO = 1600
7210 22:13:31.002769 MCKIO_SEMI = 0
7211 22:13:31.005901 PLL_FREQ = 3068
7212 22:13:31.009357 DQ_UI_PI_RATIO = 32
7213 22:13:31.012691 CA_UI_PI_RATIO = 0
7214 22:13:31.016136 ===================================
7215 22:13:31.016655 ===================================
7216 22:13:31.019525 memory_type:LPDDR4
7217 22:13:31.022552 GP_NUM : 10
7218 22:13:31.022965 SRAM_EN : 1
7219 22:13:31.026071 MD32_EN : 0
7220 22:13:31.029199 ===================================
7221 22:13:31.032831 [ANA_INIT] >>>>>>>>>>>>>>
7222 22:13:31.035862 <<<<<< [CONFIGURE PHASE]: ANA_TX
7223 22:13:31.039161 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7224 22:13:31.042305 ===================================
7225 22:13:31.045716 data_rate = 3200,PCW = 0X7600
7226 22:13:31.048856 ===================================
7227 22:13:31.052831 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7228 22:13:31.055738 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7229 22:13:31.062373 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7230 22:13:31.065401 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7231 22:13:31.069137 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7232 22:13:31.072396 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7233 22:13:31.075091 [ANA_INIT] flow start
7234 22:13:31.078874 [ANA_INIT] PLL >>>>>>>>
7235 22:13:31.079397 [ANA_INIT] PLL <<<<<<<<
7236 22:13:31.082176 [ANA_INIT] MIDPI >>>>>>>>
7237 22:13:31.085661 [ANA_INIT] MIDPI <<<<<<<<
7238 22:13:31.086100 [ANA_INIT] DLL >>>>>>>>
7239 22:13:31.088912 [ANA_INIT] DLL <<<<<<<<
7240 22:13:31.091817 [ANA_INIT] flow end
7241 22:13:31.095261 ============ LP4 DIFF to SE enter ============
7242 22:13:31.098626 ============ LP4 DIFF to SE exit ============
7243 22:13:31.102165 [ANA_INIT] <<<<<<<<<<<<<
7244 22:13:31.105306 [Flow] Enable top DCM control >>>>>
7245 22:13:31.108685 [Flow] Enable top DCM control <<<<<
7246 22:13:31.112355 Enable DLL master slave shuffle
7247 22:13:31.118555 ==============================================================
7248 22:13:31.119126 Gating Mode config
7249 22:13:31.125731 ==============================================================
7250 22:13:31.126160 Config description:
7251 22:13:31.134748 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7252 22:13:31.141371 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7253 22:13:31.147890 SELPH_MODE 0: By rank 1: By Phase
7254 22:13:31.151340 ==============================================================
7255 22:13:31.154385 GAT_TRACK_EN = 1
7256 22:13:31.157623 RX_GATING_MODE = 2
7257 22:13:31.161035 RX_GATING_TRACK_MODE = 2
7258 22:13:31.164238 SELPH_MODE = 1
7259 22:13:31.167795 PICG_EARLY_EN = 1
7260 22:13:31.171274 VALID_LAT_VALUE = 1
7261 22:13:31.177887 ==============================================================
7262 22:13:31.181009 Enter into Gating configuration >>>>
7263 22:13:31.184053 Exit from Gating configuration <<<<
7264 22:13:31.184166 Enter into DVFS_PRE_config >>>>>
7265 22:13:31.197318 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7266 22:13:31.200535 Exit from DVFS_PRE_config <<<<<
7267 22:13:31.204233 Enter into PICG configuration >>>>
7268 22:13:31.207446 Exit from PICG configuration <<<<
7269 22:13:31.210527 [RX_INPUT] configuration >>>>>
7270 22:13:31.210649 [RX_INPUT] configuration <<<<<
7271 22:13:31.216810 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7272 22:13:31.224014 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7273 22:13:31.226979 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7274 22:13:31.233959 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7275 22:13:31.239966 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7276 22:13:31.246642 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7277 22:13:31.250089 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7278 22:13:31.253251 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7279 22:13:31.259835 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7280 22:13:31.263413 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7281 22:13:31.266402 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7282 22:13:31.273169 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7283 22:13:31.276469 ===================================
7284 22:13:31.276848 LPDDR4 DRAM CONFIGURATION
7285 22:13:31.280402 ===================================
7286 22:13:31.283439 EX_ROW_EN[0] = 0x0
7287 22:13:31.286344 EX_ROW_EN[1] = 0x0
7288 22:13:31.286655 LP4Y_EN = 0x0
7289 22:13:31.289369 WORK_FSP = 0x1
7290 22:13:31.289670 WL = 0x5
7291 22:13:31.292793 RL = 0x5
7292 22:13:31.293135 BL = 0x2
7293 22:13:31.296521 RPST = 0x0
7294 22:13:31.296821 RD_PRE = 0x0
7295 22:13:31.300037 WR_PRE = 0x1
7296 22:13:31.300339 WR_PST = 0x1
7297 22:13:31.303036 DBI_WR = 0x0
7298 22:13:31.303390 DBI_RD = 0x0
7299 22:13:31.306839 OTF = 0x1
7300 22:13:31.309355 ===================================
7301 22:13:31.312492 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7302 22:13:31.315984 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7303 22:13:31.322535 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7304 22:13:31.325646 ===================================
7305 22:13:31.325951 LPDDR4 DRAM CONFIGURATION
7306 22:13:31.329087 ===================================
7307 22:13:31.332454 EX_ROW_EN[0] = 0x10
7308 22:13:31.335967 EX_ROW_EN[1] = 0x0
7309 22:13:31.336270 LP4Y_EN = 0x0
7310 22:13:31.339418 WORK_FSP = 0x1
7311 22:13:31.339722 WL = 0x5
7312 22:13:31.342426 RL = 0x5
7313 22:13:31.342829 BL = 0x2
7314 22:13:31.345955 RPST = 0x0
7315 22:13:31.346258 RD_PRE = 0x0
7316 22:13:31.348747 WR_PRE = 0x1
7317 22:13:31.349050 WR_PST = 0x1
7318 22:13:31.352233 DBI_WR = 0x0
7319 22:13:31.352604 DBI_RD = 0x0
7320 22:13:31.355554 OTF = 0x1
7321 22:13:31.358607 ===================================
7322 22:13:31.365561 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7323 22:13:31.365926 ==
7324 22:13:31.368485 Dram Type= 6, Freq= 0, CH_0, rank 0
7325 22:13:31.372883 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7326 22:13:31.373065 ==
7327 22:13:31.375002 [Duty_Offset_Calibration]
7328 22:13:31.375234 B0:1 B1:-1 CA:0
7329 22:13:31.375383
7330 22:13:31.378828 [DutyScan_Calibration_Flow] k_type=0
7331 22:13:31.389582
7332 22:13:31.389762 ==CLK 0==
7333 22:13:31.392513 Final CLK duty delay cell = 0
7334 22:13:31.396030 [0] MAX Duty = 5125%(X100), DQS PI = 20
7335 22:13:31.399191 [0] MIN Duty = 4907%(X100), DQS PI = 6
7336 22:13:31.402342 [0] AVG Duty = 5016%(X100)
7337 22:13:31.402525
7338 22:13:31.406308 CH0 CLK Duty spec in!! Max-Min= 218%
7339 22:13:31.409313 [DutyScan_Calibration_Flow] ====Done====
7340 22:13:31.409494
7341 22:13:31.412482 [DutyScan_Calibration_Flow] k_type=1
7342 22:13:31.429173
7343 22:13:31.429445 ==DQS 0 ==
7344 22:13:31.432466 Final DQS duty delay cell = -4
7345 22:13:31.435347 [-4] MAX Duty = 4969%(X100), DQS PI = 18
7346 22:13:31.438843 [-4] MIN Duty = 4844%(X100), DQS PI = 58
7347 22:13:31.441613 [-4] AVG Duty = 4906%(X100)
7348 22:13:31.441796
7349 22:13:31.441941 ==DQS 1 ==
7350 22:13:31.445149 Final DQS duty delay cell = 0
7351 22:13:31.448248 [0] MAX Duty = 5187%(X100), DQS PI = 4
7352 22:13:31.451725 [0] MIN Duty = 5031%(X100), DQS PI = 18
7353 22:13:31.455103 [0] AVG Duty = 5109%(X100)
7354 22:13:31.455290
7355 22:13:31.458748 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7356 22:13:31.458918
7357 22:13:31.461585 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7358 22:13:31.464744 [DutyScan_Calibration_Flow] ====Done====
7359 22:13:31.464898
7360 22:13:31.468149 [DutyScan_Calibration_Flow] k_type=3
7361 22:13:31.486504
7362 22:13:31.486931 ==DQM 0 ==
7363 22:13:31.489615 Final DQM duty delay cell = 0
7364 22:13:31.492776 [0] MAX Duty = 5124%(X100), DQS PI = 20
7365 22:13:31.496663 [0] MIN Duty = 4907%(X100), DQS PI = 8
7366 22:13:31.499455 [0] AVG Duty = 5015%(X100)
7367 22:13:31.499869
7368 22:13:31.500193 ==DQM 1 ==
7369 22:13:31.502852 Final DQM duty delay cell = 0
7370 22:13:31.506275 [0] MAX Duty = 5000%(X100), DQS PI = 4
7371 22:13:31.509468 [0] MIN Duty = 4813%(X100), DQS PI = 20
7372 22:13:31.512796 [0] AVG Duty = 4906%(X100)
7373 22:13:31.513227
7374 22:13:31.515892 CH0 DQM 0 Duty spec in!! Max-Min= 217%
7375 22:13:31.516303
7376 22:13:31.519742 CH0 DQM 1 Duty spec in!! Max-Min= 187%
7377 22:13:31.522851 [DutyScan_Calibration_Flow] ====Done====
7378 22:13:31.523314
7379 22:13:31.525922 [DutyScan_Calibration_Flow] k_type=2
7380 22:13:31.542412
7381 22:13:31.542819 ==DQ 0 ==
7382 22:13:31.545644 Final DQ duty delay cell = -4
7383 22:13:31.549420 [-4] MAX Duty = 5031%(X100), DQS PI = 24
7384 22:13:31.553151 [-4] MIN Duty = 4876%(X100), DQS PI = 52
7385 22:13:31.555900 [-4] AVG Duty = 4953%(X100)
7386 22:13:31.556315
7387 22:13:31.556644 ==DQ 1 ==
7388 22:13:31.559384 Final DQ duty delay cell = 0
7389 22:13:31.562346 [0] MAX Duty = 5125%(X100), DQS PI = 2
7390 22:13:31.565987 [0] MIN Duty = 5000%(X100), DQS PI = 36
7391 22:13:31.568667 [0] AVG Duty = 5062%(X100)
7392 22:13:31.569081
7393 22:13:31.572324 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7394 22:13:31.572737
7395 22:13:31.575644 CH0 DQ 1 Duty spec in!! Max-Min= 125%
7396 22:13:31.579457 [DutyScan_Calibration_Flow] ====Done====
7397 22:13:31.579872 ==
7398 22:13:31.582366 Dram Type= 6, Freq= 0, CH_1, rank 0
7399 22:13:31.585463 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7400 22:13:31.585881 ==
7401 22:13:31.588729 [Duty_Offset_Calibration]
7402 22:13:31.589140 B0:-1 B1:1 CA:2
7403 22:13:31.589477
7404 22:13:31.592325 [DutyScan_Calibration_Flow] k_type=0
7405 22:13:31.603325
7406 22:13:31.603903 ==CLK 0==
7407 22:13:31.606388 Final CLK duty delay cell = 0
7408 22:13:31.609525 [0] MAX Duty = 5187%(X100), DQS PI = 22
7409 22:13:31.612829 [0] MIN Duty = 4969%(X100), DQS PI = 0
7410 22:13:31.616466 [0] AVG Duty = 5078%(X100)
7411 22:13:31.617026
7412 22:13:31.619833 CH1 CLK Duty spec in!! Max-Min= 218%
7413 22:13:31.623524 [DutyScan_Calibration_Flow] ====Done====
7414 22:13:31.623936
7415 22:13:31.625920 [DutyScan_Calibration_Flow] k_type=1
7416 22:13:31.642611
7417 22:13:31.643129 ==DQS 0 ==
7418 22:13:31.646180 Final DQS duty delay cell = 0
7419 22:13:31.649514 [0] MAX Duty = 5124%(X100), DQS PI = 18
7420 22:13:31.652703 [0] MIN Duty = 4907%(X100), DQS PI = 10
7421 22:13:31.655677 [0] AVG Duty = 5015%(X100)
7422 22:13:31.656094
7423 22:13:31.656468 ==DQS 1 ==
7424 22:13:31.659107 Final DQS duty delay cell = 0
7425 22:13:31.662591 [0] MAX Duty = 5093%(X100), DQS PI = 24
7426 22:13:31.665880 [0] MIN Duty = 4969%(X100), DQS PI = 56
7427 22:13:31.669152 [0] AVG Duty = 5031%(X100)
7428 22:13:31.669517
7429 22:13:31.672483 CH1 DQS 0 Duty spec in!! Max-Min= 217%
7430 22:13:31.672826
7431 22:13:31.676410 CH1 DQS 1 Duty spec in!! Max-Min= 124%
7432 22:13:31.679279 [DutyScan_Calibration_Flow] ====Done====
7433 22:13:31.679632
7434 22:13:31.682240 [DutyScan_Calibration_Flow] k_type=3
7435 22:13:31.698930
7436 22:13:31.699335 ==DQM 0 ==
7437 22:13:31.702075 Final DQM duty delay cell = -4
7438 22:13:31.705986 [-4] MAX Duty = 5062%(X100), DQS PI = 34
7439 22:13:31.708905 [-4] MIN Duty = 4813%(X100), DQS PI = 8
7440 22:13:31.712193 [-4] AVG Duty = 4937%(X100)
7441 22:13:31.712489
7442 22:13:31.712724 ==DQM 1 ==
7443 22:13:31.715113 Final DQM duty delay cell = 0
7444 22:13:31.719101 [0] MAX Duty = 5187%(X100), DQS PI = 8
7445 22:13:31.721939 [0] MIN Duty = 5000%(X100), DQS PI = 28
7446 22:13:31.725567 [0] AVG Duty = 5093%(X100)
7447 22:13:31.725864
7448 22:13:31.728569 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7449 22:13:31.728862
7450 22:13:31.731804 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7451 22:13:31.735380 [DutyScan_Calibration_Flow] ====Done====
7452 22:13:31.735678
7453 22:13:31.738412 [DutyScan_Calibration_Flow] k_type=2
7454 22:13:31.756147
7455 22:13:31.756450 ==DQ 0 ==
7456 22:13:31.759405 Final DQ duty delay cell = 0
7457 22:13:31.762566 [0] MAX Duty = 5187%(X100), DQS PI = 34
7458 22:13:31.766052 [0] MIN Duty = 4906%(X100), DQS PI = 8
7459 22:13:31.766378 [0] AVG Duty = 5046%(X100)
7460 22:13:31.769155
7461 22:13:31.769454 ==DQ 1 ==
7462 22:13:31.772465 Final DQ duty delay cell = 0
7463 22:13:31.775645 [0] MAX Duty = 5156%(X100), DQS PI = 8
7464 22:13:31.778976 [0] MIN Duty = 4969%(X100), DQS PI = 56
7465 22:13:31.779347 [0] AVG Duty = 5062%(X100)
7466 22:13:31.779589
7467 22:13:31.782676 CH1 DQ 0 Duty spec in!! Max-Min= 281%
7468 22:13:31.785940
7469 22:13:31.788740 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7470 22:13:31.792200 [DutyScan_Calibration_Flow] ====Done====
7471 22:13:31.795800 nWR fixed to 30
7472 22:13:31.796099 [ModeRegInit_LP4] CH0 RK0
7473 22:13:31.798806 [ModeRegInit_LP4] CH0 RK1
7474 22:13:31.802205 [ModeRegInit_LP4] CH1 RK0
7475 22:13:31.806574 [ModeRegInit_LP4] CH1 RK1
7476 22:13:31.806871 match AC timing 5
7477 22:13:31.812013 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7478 22:13:31.815480 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7479 22:13:31.818179 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7480 22:13:31.825061 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7481 22:13:31.828313 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7482 22:13:31.828612 [MiockJmeterHQA]
7483 22:13:31.828847
7484 22:13:31.832076 [DramcMiockJmeter] u1RxGatingPI = 0
7485 22:13:31.834931 0 : 4255, 4029
7486 22:13:31.835275 4 : 4363, 4138
7487 22:13:31.838021 8 : 4252, 4027
7488 22:13:31.838323 12 : 4363, 4137
7489 22:13:31.841585 16 : 4363, 4137
7490 22:13:31.841886 20 : 4255, 4029
7491 22:13:31.842129 24 : 4252, 4027
7492 22:13:31.844777 28 : 4253, 4027
7493 22:13:31.845081 32 : 4363, 4138
7494 22:13:31.847939 36 : 4252, 4027
7495 22:13:31.848241 40 : 4363, 4137
7496 22:13:31.851466 44 : 4252, 4027
7497 22:13:31.851767 48 : 4252, 4027
7498 22:13:31.854792 52 : 4252, 4027
7499 22:13:31.855120 56 : 4255, 4029
7500 22:13:31.855367 60 : 4363, 4138
7501 22:13:31.858191 64 : 4250, 4027
7502 22:13:31.858492 68 : 4361, 4137
7503 22:13:31.861127 72 : 4250, 4027
7504 22:13:31.861428 76 : 4250, 4026
7505 22:13:31.864692 80 : 4250, 4027
7506 22:13:31.864992 84 : 4361, 4138
7507 22:13:31.867885 88 : 4250, 4026
7508 22:13:31.868281 92 : 4360, 907
7509 22:13:31.868535 96 : 4253, 0
7510 22:13:31.871707 100 : 4253, 0
7511 22:13:31.872012 104 : 4360, 0
7512 22:13:31.874774 108 : 4250, 0
7513 22:13:31.875102 112 : 4250, 0
7514 22:13:31.875351 116 : 4249, 0
7515 22:13:31.877767 120 : 4250, 0
7516 22:13:31.878070 124 : 4253, 0
7517 22:13:31.881171 128 : 4249, 0
7518 22:13:31.881486 132 : 4250, 0
7519 22:13:31.881736 136 : 4253, 0
7520 22:13:31.884043 140 : 4252, 0
7521 22:13:31.884346 144 : 4361, 0
7522 22:13:31.884584 148 : 4250, 0
7523 22:13:31.887632 152 : 4253, 0
7524 22:13:31.887935 156 : 4361, 0
7525 22:13:31.890900 160 : 4361, 0
7526 22:13:31.891235 164 : 4253, 0
7527 22:13:31.891479 168 : 4254, 0
7528 22:13:31.893992 172 : 4250, 0
7529 22:13:31.894295 176 : 4252, 0
7530 22:13:31.897603 180 : 4252, 0
7531 22:13:31.897938 184 : 4250, 0
7532 22:13:31.898182 188 : 4253, 0
7533 22:13:31.900829 192 : 4363, 0
7534 22:13:31.901131 196 : 4361, 0
7535 22:13:31.904091 200 : 4250, 0
7536 22:13:31.904399 204 : 4250, 0
7537 22:13:31.904644 208 : 4361, 0
7538 22:13:31.907253 212 : 4250, 0
7539 22:13:31.907584 216 : 4253, 0
7540 22:13:31.910655 220 : 4252, 0
7541 22:13:31.911130 224 : 4250, 103
7542 22:13:31.911452 228 : 4363, 3595
7543 22:13:31.914089 232 : 4250, 4027
7544 22:13:31.914461 236 : 4360, 4137
7545 22:13:31.917219 240 : 4252, 4029
7546 22:13:31.917561 244 : 4250, 4027
7547 22:13:31.920488 248 : 4250, 4027
7548 22:13:31.920922 252 : 4250, 4027
7549 22:13:31.924322 256 : 4250, 4027
7550 22:13:31.924626 260 : 4250, 4027
7551 22:13:31.927122 264 : 4249, 4027
7552 22:13:31.927432 268 : 4250, 4027
7553 22:13:31.930762 272 : 4250, 4027
7554 22:13:31.931093 276 : 4360, 4138
7555 22:13:31.931346 280 : 4361, 4138
7556 22:13:31.934159 284 : 4250, 4027
7557 22:13:31.934607 288 : 4360, 4138
7558 22:13:31.937613 292 : 4360, 4138
7559 22:13:31.937922 296 : 4250, 4027
7560 22:13:31.940717 300 : 4250, 4027
7561 22:13:31.941025 304 : 4250, 4027
7562 22:13:31.944099 308 : 4250, 4027
7563 22:13:31.944405 312 : 4250, 4027
7564 22:13:31.947851 316 : 4249, 4027
7565 22:13:31.948251 320 : 4250, 4026
7566 22:13:31.950634 324 : 4250, 4027
7567 22:13:31.951032 328 : 4360, 4138
7568 22:13:31.954066 332 : 4361, 4138
7569 22:13:31.954590 336 : 4250, 3792
7570 22:13:31.957172 340 : 4361, 2205
7571 22:13:31.957618 344 : 4360, 52
7572 22:13:31.957989
7573 22:13:31.961053 MIOCK jitter meter ch=0
7574 22:13:31.961353
7575 22:13:31.963781 1T = (344-92) = 252 dly cells
7576 22:13:31.966999 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7577 22:13:31.967330 ==
7578 22:13:31.970501 Dram Type= 6, Freq= 0, CH_0, rank 0
7579 22:13:31.977054 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7580 22:13:31.977559 ==
7581 22:13:31.980471 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7582 22:13:31.987149 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7583 22:13:31.990252 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7584 22:13:31.997055 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7585 22:13:32.004765 [CA 0] Center 43 (13~74) winsize 62
7586 22:13:32.008023 [CA 1] Center 43 (13~74) winsize 62
7587 22:13:32.011623 [CA 2] Center 39 (10~69) winsize 60
7588 22:13:32.014127 [CA 3] Center 39 (9~69) winsize 61
7589 22:13:32.017626 [CA 4] Center 37 (8~66) winsize 59
7590 22:13:32.020858 [CA 5] Center 36 (7~66) winsize 60
7591 22:13:32.021318
7592 22:13:32.023883 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7593 22:13:32.024320
7594 22:13:32.031287 [CATrainingPosCal] consider 1 rank data
7595 22:13:32.031729 u2DelayCellTimex100 = 258/100 ps
7596 22:13:32.037481 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7597 22:13:32.040747 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7598 22:13:32.043503 CA2 delay=39 (10~69),Diff = 3 PI (11 cell)
7599 22:13:32.047272 CA3 delay=39 (9~69),Diff = 3 PI (11 cell)
7600 22:13:32.050236 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
7601 22:13:32.053749 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7602 22:13:32.054077
7603 22:13:32.056865 CA PerBit enable=1, Macro0, CA PI delay=36
7604 22:13:32.060327
7605 22:13:32.060639 [CBTSetCACLKResult] CA Dly = 36
7606 22:13:32.063832 CS Dly: 11 (0~42)
7607 22:13:32.066811 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7608 22:13:32.070069 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7609 22:13:32.073357 ==
7610 22:13:32.073669 Dram Type= 6, Freq= 0, CH_0, rank 1
7611 22:13:32.080226 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7612 22:13:32.080543 ==
7613 22:13:32.083183 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7614 22:13:32.089885 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7615 22:13:32.092790 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7616 22:13:32.099286 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7617 22:13:32.108409 [CA 0] Center 43 (13~74) winsize 62
7618 22:13:32.111247 [CA 1] Center 44 (14~74) winsize 61
7619 22:13:32.114503 [CA 2] Center 38 (9~68) winsize 60
7620 22:13:32.118321 [CA 3] Center 38 (9~68) winsize 60
7621 22:13:32.121265 [CA 4] Center 36 (7~66) winsize 60
7622 22:13:32.124720 [CA 5] Center 36 (7~66) winsize 60
7623 22:13:32.125031
7624 22:13:32.128340 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7625 22:13:32.128642
7626 22:13:32.131827 [CATrainingPosCal] consider 2 rank data
7627 22:13:32.134415 u2DelayCellTimex100 = 258/100 ps
7628 22:13:32.141415 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7629 22:13:32.145056 CA1 delay=44 (14~74),Diff = 8 PI (30 cell)
7630 22:13:32.148034 CA2 delay=39 (10~68),Diff = 3 PI (11 cell)
7631 22:13:32.151383 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7632 22:13:32.154730 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
7633 22:13:32.157621 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7634 22:13:32.158089
7635 22:13:32.161382 CA PerBit enable=1, Macro0, CA PI delay=36
7636 22:13:32.161944
7637 22:13:32.164388 [CBTSetCACLKResult] CA Dly = 36
7638 22:13:32.167807 CS Dly: 11 (0~43)
7639 22:13:32.171571 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7640 22:13:32.174625 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7641 22:13:32.175227
7642 22:13:32.177237 ----->DramcWriteLeveling(PI) begin...
7643 22:13:32.177711 ==
7644 22:13:32.181525 Dram Type= 6, Freq= 0, CH_0, rank 0
7645 22:13:32.187263 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7646 22:13:32.187844 ==
7647 22:13:32.190898 Write leveling (Byte 0): 36 => 36
7648 22:13:32.194198 Write leveling (Byte 1): 28 => 28
7649 22:13:32.197513 DramcWriteLeveling(PI) end<-----
7650 22:13:32.197984
7651 22:13:32.198351 ==
7652 22:13:32.200487 Dram Type= 6, Freq= 0, CH_0, rank 0
7653 22:13:32.203889 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7654 22:13:32.204362 ==
7655 22:13:32.206989 [Gating] SW mode calibration
7656 22:13:32.213881 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7657 22:13:32.217202 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7658 22:13:32.223698 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7659 22:13:32.227093 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7660 22:13:32.233929 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7661 22:13:32.236914 1 4 12 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (1 1)
7662 22:13:32.239975 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7663 22:13:32.246943 1 4 20 | B1->B0 | 2626 3434 | 0 1 | (0 0) (1 1)
7664 22:13:32.250494 1 4 24 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
7665 22:13:32.253675 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7666 22:13:32.256618 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7667 22:13:32.263418 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7668 22:13:32.267297 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7669 22:13:32.270296 1 5 12 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (0 0)
7670 22:13:32.276790 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7671 22:13:32.279885 1 5 20 | B1->B0 | 3434 2323 | 0 0 | (0 1) (0 0)
7672 22:13:32.283506 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7673 22:13:32.290370 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7674 22:13:32.293888 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7675 22:13:32.296576 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7676 22:13:32.303185 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7677 22:13:32.306395 1 6 12 | B1->B0 | 2323 3d3d | 0 0 | (0 0) (0 0)
7678 22:13:32.309688 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7679 22:13:32.316312 1 6 20 | B1->B0 | 2827 4646 | 1 0 | (0 0) (0 0)
7680 22:13:32.319404 1 6 24 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
7681 22:13:32.322823 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7682 22:13:32.329554 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7683 22:13:32.332384 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7684 22:13:32.336313 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7685 22:13:32.342668 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7686 22:13:32.346073 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7687 22:13:32.349510 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7688 22:13:32.355948 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7689 22:13:32.359458 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7690 22:13:32.362585 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7691 22:13:32.369254 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7692 22:13:32.372297 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7693 22:13:32.375169 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7694 22:13:32.382097 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7695 22:13:32.385463 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7696 22:13:32.388541 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7697 22:13:32.394977 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7698 22:13:32.398808 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7699 22:13:32.402147 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7700 22:13:32.408207 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7701 22:13:32.411755 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7702 22:13:32.414853 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7703 22:13:32.418337 Total UI for P1: 0, mck2ui 16
7704 22:13:32.421700 best dqsien dly found for B0: ( 1, 9, 10)
7705 22:13:32.428553 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7706 22:13:32.431542 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7707 22:13:32.434987 Total UI for P1: 0, mck2ui 16
7708 22:13:32.438250 best dqsien dly found for B1: ( 1, 9, 18)
7709 22:13:32.441596 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7710 22:13:32.445002 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7711 22:13:32.445301
7712 22:13:32.448566 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7713 22:13:32.451154 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7714 22:13:32.454603 [Gating] SW calibration Done
7715 22:13:32.455018 ==
7716 22:13:32.457851 Dram Type= 6, Freq= 0, CH_0, rank 0
7717 22:13:32.464679 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7718 22:13:32.464973 ==
7719 22:13:32.465208 RX Vref Scan: 0
7720 22:13:32.465425
7721 22:13:32.467921 RX Vref 0 -> 0, step: 1
7722 22:13:32.468216
7723 22:13:32.471188 RX Delay 0 -> 252, step: 8
7724 22:13:32.475035 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
7725 22:13:32.477645 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7726 22:13:32.480848 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7727 22:13:32.484660 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7728 22:13:32.491225 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7729 22:13:32.494256 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7730 22:13:32.497730 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7731 22:13:32.501284 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7732 22:13:32.505197 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7733 22:13:32.511249 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7734 22:13:32.514496 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
7735 22:13:32.517651 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7736 22:13:32.521875 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7737 22:13:32.527450 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7738 22:13:32.530965 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7739 22:13:32.534338 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7740 22:13:32.534901 ==
7741 22:13:32.537869 Dram Type= 6, Freq= 0, CH_0, rank 0
7742 22:13:32.540771 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7743 22:13:32.541235 ==
7744 22:13:32.544134 DQS Delay:
7745 22:13:32.544591 DQS0 = 0, DQS1 = 0
7746 22:13:32.547604 DQM Delay:
7747 22:13:32.548061 DQM0 = 134, DQM1 = 127
7748 22:13:32.548424 DQ Delay:
7749 22:13:32.554283 DQ0 =131, DQ1 =139, DQ2 =131, DQ3 =131
7750 22:13:32.558268 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =147
7751 22:13:32.560912 DQ8 =119, DQ9 =115, DQ10 =127, DQ11 =119
7752 22:13:32.564235 DQ12 =131, DQ13 =135, DQ14 =139, DQ15 =131
7753 22:13:32.564802
7754 22:13:32.565166
7755 22:13:32.565499 ==
7756 22:13:32.567463 Dram Type= 6, Freq= 0, CH_0, rank 0
7757 22:13:32.570895 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7758 22:13:32.571503 ==
7759 22:13:32.571966
7760 22:13:32.572317
7761 22:13:32.573905 TX Vref Scan disable
7762 22:13:32.577054 == TX Byte 0 ==
7763 22:13:32.580359 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7764 22:13:32.583898 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7765 22:13:32.587049 == TX Byte 1 ==
7766 22:13:32.590591 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7767 22:13:32.593666 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7768 22:13:32.594238 ==
7769 22:13:32.596934 Dram Type= 6, Freq= 0, CH_0, rank 0
7770 22:13:32.603216 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7771 22:13:32.603895 ==
7772 22:13:32.615622
7773 22:13:32.618799 TX Vref early break, caculate TX vref
7774 22:13:32.622383 TX Vref=16, minBit 4, minWin=22, winSum=373
7775 22:13:32.625805 TX Vref=18, minBit 0, minWin=23, winSum=380
7776 22:13:32.628804 TX Vref=20, minBit 1, minWin=23, winSum=388
7777 22:13:32.632035 TX Vref=22, minBit 3, minWin=24, winSum=404
7778 22:13:32.635115 TX Vref=24, minBit 4, minWin=24, winSum=408
7779 22:13:32.641847 TX Vref=26, minBit 0, minWin=24, winSum=418
7780 22:13:32.644942 TX Vref=28, minBit 5, minWin=25, winSum=420
7781 22:13:32.648558 TX Vref=30, minBit 4, minWin=24, winSum=413
7782 22:13:32.652061 TX Vref=32, minBit 7, minWin=23, winSum=403
7783 22:13:32.655314 TX Vref=34, minBit 4, minWin=23, winSum=390
7784 22:13:32.661704 [TxChooseVref] Worse bit 5, Min win 25, Win sum 420, Final Vref 28
7785 22:13:32.662140
7786 22:13:32.664739 Final TX Range 0 Vref 28
7787 22:13:32.665172
7788 22:13:32.665604 ==
7789 22:13:32.668595 Dram Type= 6, Freq= 0, CH_0, rank 0
7790 22:13:32.671893 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7791 22:13:32.672320 ==
7792 22:13:32.672656
7793 22:13:32.672965
7794 22:13:32.674906 TX Vref Scan disable
7795 22:13:32.681357 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7796 22:13:32.681782 == TX Byte 0 ==
7797 22:13:32.684578 u2DelayCellOfst[0]=15 cells (4 PI)
7798 22:13:32.687593 u2DelayCellOfst[1]=15 cells (4 PI)
7799 22:13:32.691329 u2DelayCellOfst[2]=11 cells (3 PI)
7800 22:13:32.694467 u2DelayCellOfst[3]=11 cells (3 PI)
7801 22:13:32.697491 u2DelayCellOfst[4]=7 cells (2 PI)
7802 22:13:32.701120 u2DelayCellOfst[5]=0 cells (0 PI)
7803 22:13:32.704210 u2DelayCellOfst[6]=15 cells (4 PI)
7804 22:13:32.707772 u2DelayCellOfst[7]=18 cells (5 PI)
7805 22:13:32.711134 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7806 22:13:32.714180 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7807 22:13:32.717211 == TX Byte 1 ==
7808 22:13:32.720489 u2DelayCellOfst[8]=0 cells (0 PI)
7809 22:13:32.723840 u2DelayCellOfst[9]=0 cells (0 PI)
7810 22:13:32.727437 u2DelayCellOfst[10]=3 cells (1 PI)
7811 22:13:32.727704 u2DelayCellOfst[11]=0 cells (0 PI)
7812 22:13:32.730534 u2DelayCellOfst[12]=11 cells (3 PI)
7813 22:13:32.733796 u2DelayCellOfst[13]=11 cells (3 PI)
7814 22:13:32.737447 u2DelayCellOfst[14]=15 cells (4 PI)
7815 22:13:32.740739 u2DelayCellOfst[15]=11 cells (3 PI)
7816 22:13:32.746958 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7817 22:13:32.750593 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7818 22:13:32.750816 DramC Write-DBI on
7819 22:13:32.753771 ==
7820 22:13:32.753992 Dram Type= 6, Freq= 0, CH_0, rank 0
7821 22:13:32.760418 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7822 22:13:32.760643 ==
7823 22:13:32.760822
7824 22:13:32.760986
7825 22:13:32.764118 TX Vref Scan disable
7826 22:13:32.764351 == TX Byte 0 ==
7827 22:13:32.770196 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7828 22:13:32.770427 == TX Byte 1 ==
7829 22:13:32.773790 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7830 22:13:32.777039 DramC Write-DBI off
7831 22:13:32.777267
7832 22:13:32.777447 [DATLAT]
7833 22:13:32.780797 Freq=1600, CH0 RK0
7834 22:13:32.781026
7835 22:13:32.781205 DATLAT Default: 0xf
7836 22:13:32.783440 0, 0xFFFF, sum = 0
7837 22:13:32.783671 1, 0xFFFF, sum = 0
7838 22:13:32.786693 2, 0xFFFF, sum = 0
7839 22:13:32.786924 3, 0xFFFF, sum = 0
7840 22:13:32.789861 4, 0xFFFF, sum = 0
7841 22:13:32.793251 5, 0xFFFF, sum = 0
7842 22:13:32.793334 6, 0xFFFF, sum = 0
7843 22:13:32.796764 7, 0xFFFF, sum = 0
7844 22:13:32.796853 8, 0xFFFF, sum = 0
7845 22:13:32.799803 9, 0xFFFF, sum = 0
7846 22:13:32.799893 10, 0xFFFF, sum = 0
7847 22:13:32.802801 11, 0xFFFF, sum = 0
7848 22:13:32.802897 12, 0xFFFF, sum = 0
7849 22:13:32.806377 13, 0xFFFF, sum = 0
7850 22:13:32.806480 14, 0x0, sum = 1
7851 22:13:32.809523 15, 0x0, sum = 2
7852 22:13:32.809625 16, 0x0, sum = 3
7853 22:13:32.812846 17, 0x0, sum = 4
7854 22:13:32.812959 best_step = 15
7855 22:13:32.813046
7856 22:13:32.813126 ==
7857 22:13:32.816302 Dram Type= 6, Freq= 0, CH_0, rank 0
7858 22:13:32.822534 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7859 22:13:32.822668 ==
7860 22:13:32.822772 RX Vref Scan: 1
7861 22:13:32.822869
7862 22:13:32.826400 Set Vref Range= 24 -> 127
7863 22:13:32.826555
7864 22:13:32.829720 RX Vref 24 -> 127, step: 1
7865 22:13:32.829950
7866 22:13:32.830080 RX Delay 19 -> 252, step: 4
7867 22:13:32.830199
7868 22:13:32.832670 Set Vref, RX VrefLevel [Byte0]: 24
7869 22:13:32.836320 [Byte1]: 24
7870 22:13:32.840308
7871 22:13:32.840667 Set Vref, RX VrefLevel [Byte0]: 25
7872 22:13:32.846670 [Byte1]: 25
7873 22:13:32.846973
7874 22:13:32.850279 Set Vref, RX VrefLevel [Byte0]: 26
7875 22:13:32.853836 [Byte1]: 26
7876 22:13:32.854227
7877 22:13:32.856833 Set Vref, RX VrefLevel [Byte0]: 27
7878 22:13:32.859810 [Byte1]: 27
7879 22:13:32.860273
7880 22:13:32.863114 Set Vref, RX VrefLevel [Byte0]: 28
7881 22:13:32.866597 [Byte1]: 28
7882 22:13:32.870964
7883 22:13:32.871725 Set Vref, RX VrefLevel [Byte0]: 29
7884 22:13:32.873792 [Byte1]: 29
7885 22:13:32.878159
7886 22:13:32.878613 Set Vref, RX VrefLevel [Byte0]: 30
7887 22:13:32.881958 [Byte1]: 30
7888 22:13:32.886251
7889 22:13:32.886814 Set Vref, RX VrefLevel [Byte0]: 31
7890 22:13:32.889248 [Byte1]: 31
7891 22:13:32.893754
7892 22:13:32.894309 Set Vref, RX VrefLevel [Byte0]: 32
7893 22:13:32.896777 [Byte1]: 32
7894 22:13:32.901374
7895 22:13:32.901985 Set Vref, RX VrefLevel [Byte0]: 33
7896 22:13:32.904014 [Byte1]: 33
7897 22:13:32.908793
7898 22:13:32.909366 Set Vref, RX VrefLevel [Byte0]: 34
7899 22:13:32.912051 [Byte1]: 34
7900 22:13:32.915848
7901 22:13:32.916490 Set Vref, RX VrefLevel [Byte0]: 35
7902 22:13:32.919315 [Byte1]: 35
7903 22:13:32.923293
7904 22:13:32.923913 Set Vref, RX VrefLevel [Byte0]: 36
7905 22:13:32.926789 [Byte1]: 36
7906 22:13:32.930982
7907 22:13:32.931660 Set Vref, RX VrefLevel [Byte0]: 37
7908 22:13:32.934192 [Byte1]: 37
7909 22:13:32.938717
7910 22:13:32.939217 Set Vref, RX VrefLevel [Byte0]: 38
7911 22:13:32.941886 [Byte1]: 38
7912 22:13:32.947137
7913 22:13:32.947695 Set Vref, RX VrefLevel [Byte0]: 39
7914 22:13:32.949574 [Byte1]: 39
7915 22:13:32.954107
7916 22:13:32.954659 Set Vref, RX VrefLevel [Byte0]: 40
7917 22:13:32.957126 [Byte1]: 40
7918 22:13:32.961515
7919 22:13:32.962130 Set Vref, RX VrefLevel [Byte0]: 41
7920 22:13:32.965245 [Byte1]: 41
7921 22:13:32.969620
7922 22:13:32.970179 Set Vref, RX VrefLevel [Byte0]: 42
7923 22:13:32.972097 [Byte1]: 42
7924 22:13:32.977096
7925 22:13:32.977575 Set Vref, RX VrefLevel [Byte0]: 43
7926 22:13:32.979990 [Byte1]: 43
7927 22:13:32.984152
7928 22:13:32.984708 Set Vref, RX VrefLevel [Byte0]: 44
7929 22:13:32.987647 [Byte1]: 44
7930 22:13:32.991967
7931 22:13:32.992529 Set Vref, RX VrefLevel [Byte0]: 45
7932 22:13:32.995223 [Byte1]: 45
7933 22:13:32.999909
7934 22:13:33.000621 Set Vref, RX VrefLevel [Byte0]: 46
7935 22:13:33.002701 [Byte1]: 46
7936 22:13:33.007180
7937 22:13:33.007635 Set Vref, RX VrefLevel [Byte0]: 47
7938 22:13:33.010112 [Byte1]: 47
7939 22:13:33.014767
7940 22:13:33.015486 Set Vref, RX VrefLevel [Byte0]: 48
7941 22:13:33.017688 [Byte1]: 48
7942 22:13:33.021960
7943 22:13:33.022418 Set Vref, RX VrefLevel [Byte0]: 49
7944 22:13:33.025636 [Byte1]: 49
7945 22:13:33.029773
7946 22:13:33.030564 Set Vref, RX VrefLevel [Byte0]: 50
7947 22:13:33.033142 [Byte1]: 50
7948 22:13:33.036965
7949 22:13:33.037454 Set Vref, RX VrefLevel [Byte0]: 51
7950 22:13:33.040408 [Byte1]: 51
7951 22:13:33.044929
7952 22:13:33.045429 Set Vref, RX VrefLevel [Byte0]: 52
7953 22:13:33.048111 [Byte1]: 52
7954 22:13:33.052274
7955 22:13:33.052731 Set Vref, RX VrefLevel [Byte0]: 53
7956 22:13:33.055366 [Byte1]: 53
7957 22:13:33.059685
7958 22:13:33.060351 Set Vref, RX VrefLevel [Byte0]: 54
7959 22:13:33.063257 [Byte1]: 54
7960 22:13:33.067681
7961 22:13:33.068233 Set Vref, RX VrefLevel [Byte0]: 55
7962 22:13:33.070562 [Byte1]: 55
7963 22:13:33.075296
7964 22:13:33.075734 Set Vref, RX VrefLevel [Byte0]: 56
7965 22:13:33.078837 [Byte1]: 56
7966 22:13:33.082564
7967 22:13:33.082974 Set Vref, RX VrefLevel [Byte0]: 57
7968 22:13:33.086008 [Byte1]: 57
7969 22:13:33.089893
7970 22:13:33.090303 Set Vref, RX VrefLevel [Byte0]: 58
7971 22:13:33.093963 [Byte1]: 58
7972 22:13:33.098331
7973 22:13:33.098853 Set Vref, RX VrefLevel [Byte0]: 59
7974 22:13:33.101300 [Byte1]: 59
7975 22:13:33.105637
7976 22:13:33.106050 Set Vref, RX VrefLevel [Byte0]: 60
7977 22:13:33.108440 [Byte1]: 60
7978 22:13:33.113783
7979 22:13:33.114303 Set Vref, RX VrefLevel [Byte0]: 61
7980 22:13:33.116570 [Byte1]: 61
7981 22:13:33.120539
7982 22:13:33.120950 Set Vref, RX VrefLevel [Byte0]: 62
7983 22:13:33.123789 [Byte1]: 62
7984 22:13:33.127736
7985 22:13:33.128173 Set Vref, RX VrefLevel [Byte0]: 63
7986 22:13:33.131597 [Byte1]: 63
7987 22:13:33.135956
7988 22:13:33.136370 Set Vref, RX VrefLevel [Byte0]: 64
7989 22:13:33.138740 [Byte1]: 64
7990 22:13:33.143419
7991 22:13:33.143884 Set Vref, RX VrefLevel [Byte0]: 65
7992 22:13:33.147111 [Byte1]: 65
7993 22:13:33.150699
7994 22:13:33.151261 Set Vref, RX VrefLevel [Byte0]: 66
7995 22:13:33.154088 [Byte1]: 66
7996 22:13:33.158806
7997 22:13:33.159522 Set Vref, RX VrefLevel [Byte0]: 67
7998 22:13:33.161671 [Byte1]: 67
7999 22:13:33.166235
8000 22:13:33.166761 Set Vref, RX VrefLevel [Byte0]: 68
8001 22:13:33.169433 [Byte1]: 68
8002 22:13:33.173613
8003 22:13:33.177208 Set Vref, RX VrefLevel [Byte0]: 69
8004 22:13:33.180116 [Byte1]: 69
8005 22:13:33.180579
8006 22:13:33.183929 Set Vref, RX VrefLevel [Byte0]: 70
8007 22:13:33.186723 [Byte1]: 70
8008 22:13:33.187343
8009 22:13:33.190264 Set Vref, RX VrefLevel [Byte0]: 71
8010 22:13:33.193346 [Byte1]: 71
8011 22:13:33.193917
8012 22:13:33.196551 Set Vref, RX VrefLevel [Byte0]: 72
8013 22:13:33.199977 [Byte1]: 72
8014 22:13:33.203835
8015 22:13:33.204639 Set Vref, RX VrefLevel [Byte0]: 73
8016 22:13:33.207003 [Byte1]: 73
8017 22:13:33.211698
8018 22:13:33.212265 Set Vref, RX VrefLevel [Byte0]: 74
8019 22:13:33.214627 [Byte1]: 74
8020 22:13:33.219143
8021 22:13:33.219704 Set Vref, RX VrefLevel [Byte0]: 75
8022 22:13:33.222510 [Byte1]: 75
8023 22:13:33.226547
8024 22:13:33.227316 Set Vref, RX VrefLevel [Byte0]: 76
8025 22:13:33.230069 [Byte1]: 76
8026 22:13:33.234429
8027 22:13:33.235199 Set Vref, RX VrefLevel [Byte0]: 77
8028 22:13:33.237927 [Byte1]: 77
8029 22:13:33.241452
8030 22:13:33.241917 Set Vref, RX VrefLevel [Byte0]: 78
8031 22:13:33.245519 [Byte1]: 78
8032 22:13:33.249083
8033 22:13:33.249658 Final RX Vref Byte 0 = 66 to rank0
8034 22:13:33.252982 Final RX Vref Byte 1 = 59 to rank0
8035 22:13:33.255741 Final RX Vref Byte 0 = 66 to rank1
8036 22:13:33.259166 Final RX Vref Byte 1 = 59 to rank1==
8037 22:13:33.262445 Dram Type= 6, Freq= 0, CH_0, rank 0
8038 22:13:33.268695 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8039 22:13:33.269171 ==
8040 22:13:33.269552 DQS Delay:
8041 22:13:33.272285 DQS0 = 0, DQS1 = 0
8042 22:13:33.272830 DQM Delay:
8043 22:13:33.273206 DQM0 = 133, DQM1 = 123
8044 22:13:33.275435 DQ Delay:
8045 22:13:33.278915 DQ0 =132, DQ1 =136, DQ2 =130, DQ3 =132
8046 22:13:33.281948 DQ4 =136, DQ5 =122, DQ6 =140, DQ7 =140
8047 22:13:33.285177 DQ8 =116, DQ9 =112, DQ10 =122, DQ11 =118
8048 22:13:33.288371 DQ12 =128, DQ13 =128, DQ14 =134, DQ15 =128
8049 22:13:33.288837
8050 22:13:33.289202
8051 22:13:33.289539
8052 22:13:33.292057 [DramC_TX_OE_Calibration] TA2
8053 22:13:33.295591 Original DQ_B0 (3 6) =30, OEN = 27
8054 22:13:33.299008 Original DQ_B1 (3 6) =30, OEN = 27
8055 22:13:33.302051 24, 0x0, End_B0=24 End_B1=24
8056 22:13:33.305054 25, 0x0, End_B0=25 End_B1=25
8057 22:13:33.305486 26, 0x0, End_B0=26 End_B1=26
8058 22:13:33.308346 27, 0x0, End_B0=27 End_B1=27
8059 22:13:33.311353 28, 0x0, End_B0=28 End_B1=28
8060 22:13:33.315292 29, 0x0, End_B0=29 End_B1=29
8061 22:13:33.315722 30, 0x0, End_B0=30 End_B1=30
8062 22:13:33.318293 31, 0x5151, End_B0=30 End_B1=30
8063 22:13:33.321791 Byte0 end_step=30 best_step=27
8064 22:13:33.324803 Byte1 end_step=30 best_step=27
8065 22:13:33.328407 Byte0 TX OE(2T, 0.5T) = (3, 3)
8066 22:13:33.331240 Byte1 TX OE(2T, 0.5T) = (3, 3)
8067 22:13:33.331712
8068 22:13:33.332082
8069 22:13:33.338088 [DQSOSCAuto] RK0, (LSB)MR18= 0x2415, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 391 ps
8070 22:13:33.341305 CH0 RK0: MR19=303, MR18=2415
8071 22:13:33.348357 CH0_RK0: MR19=0x303, MR18=0x2415, DQSOSC=391, MR23=63, INC=24, DEC=16
8072 22:13:33.348839
8073 22:13:33.351254 ----->DramcWriteLeveling(PI) begin...
8074 22:13:33.351729 ==
8075 22:13:33.354598 Dram Type= 6, Freq= 0, CH_0, rank 1
8076 22:13:33.357410 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8077 22:13:33.357880 ==
8078 22:13:33.360755 Write leveling (Byte 0): 34 => 34
8079 22:13:33.364351 Write leveling (Byte 1): 27 => 27
8080 22:13:33.367723 DramcWriteLeveling(PI) end<-----
8081 22:13:33.368237
8082 22:13:33.368566 ==
8083 22:13:33.370875 Dram Type= 6, Freq= 0, CH_0, rank 1
8084 22:13:33.377547 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8085 22:13:33.378044 ==
8086 22:13:33.378445 [Gating] SW mode calibration
8087 22:13:33.387257 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8088 22:13:33.390684 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8089 22:13:33.393910 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8090 22:13:33.400645 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8091 22:13:33.404152 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8092 22:13:33.410338 1 4 12 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8093 22:13:33.413663 1 4 16 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
8094 22:13:33.417141 1 4 20 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
8095 22:13:33.423879 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8096 22:13:33.426556 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8097 22:13:33.430082 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8098 22:13:33.436556 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8099 22:13:33.440525 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8100 22:13:33.443593 1 5 12 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
8101 22:13:33.450416 1 5 16 | B1->B0 | 3434 2727 | 1 0 | (1 0) (0 0)
8102 22:13:33.453287 1 5 20 | B1->B0 | 2e2e 2323 | 0 0 | (1 0) (0 0)
8103 22:13:33.456521 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8104 22:13:33.460439 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8105 22:13:33.466800 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8106 22:13:33.469866 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8107 22:13:33.473365 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8108 22:13:33.480234 1 6 12 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (0 0)
8109 22:13:33.483222 1 6 16 | B1->B0 | 2323 4444 | 0 0 | (0 0) (0 0)
8110 22:13:33.486505 1 6 20 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
8111 22:13:33.493099 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8112 22:13:33.496217 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8113 22:13:33.499878 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8114 22:13:33.505976 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8115 22:13:33.509407 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8116 22:13:33.513113 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8117 22:13:33.519209 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8118 22:13:33.522399 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8119 22:13:33.525749 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8120 22:13:33.532359 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8121 22:13:33.535922 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8122 22:13:33.538981 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8123 22:13:33.545371 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8124 22:13:33.548537 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8125 22:13:33.551878 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8126 22:13:33.558710 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8127 22:13:33.561819 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8128 22:13:33.565479 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8129 22:13:33.571747 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8130 22:13:33.574739 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8131 22:13:33.578545 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8132 22:13:33.585140 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8133 22:13:33.588216 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8134 22:13:33.592075 Total UI for P1: 0, mck2ui 16
8135 22:13:33.594900 best dqsien dly found for B0: ( 1, 9, 12)
8136 22:13:33.598256 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8137 22:13:33.604994 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8138 22:13:33.608551 Total UI for P1: 0, mck2ui 16
8139 22:13:33.611213 best dqsien dly found for B1: ( 1, 9, 18)
8140 22:13:33.614988 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8141 22:13:33.618137 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8142 22:13:33.618399
8143 22:13:33.621405 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8144 22:13:33.625520 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8145 22:13:33.628115 [Gating] SW calibration Done
8146 22:13:33.628366 ==
8147 22:13:33.631480 Dram Type= 6, Freq= 0, CH_0, rank 1
8148 22:13:33.635146 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8149 22:13:33.635639 ==
8150 22:13:33.638186 RX Vref Scan: 0
8151 22:13:33.638682
8152 22:13:33.641813 RX Vref 0 -> 0, step: 1
8153 22:13:33.642373
8154 22:13:33.642738 RX Delay 0 -> 252, step: 8
8155 22:13:33.648173 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8156 22:13:33.651797 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8157 22:13:33.654717 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8158 22:13:33.657760 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8159 22:13:33.661048 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8160 22:13:33.667740 iDelay=200, Bit 5, Center 123 (64 ~ 183) 120
8161 22:13:33.670999 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8162 22:13:33.674250 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8163 22:13:33.677813 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8164 22:13:33.680832 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8165 22:13:33.687273 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8166 22:13:33.690782 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8167 22:13:33.694028 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8168 22:13:33.697456 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8169 22:13:33.704013 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
8170 22:13:33.707015 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8171 22:13:33.707124 ==
8172 22:13:33.710525 Dram Type= 6, Freq= 0, CH_0, rank 1
8173 22:13:33.714067 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8174 22:13:33.714182 ==
8175 22:13:33.717059 DQS Delay:
8176 22:13:33.717162 DQS0 = 0, DQS1 = 0
8177 22:13:33.717243 DQM Delay:
8178 22:13:33.720199 DQM0 = 133, DQM1 = 128
8179 22:13:33.720312 DQ Delay:
8180 22:13:33.723923 DQ0 =135, DQ1 =135, DQ2 =127, DQ3 =127
8181 22:13:33.726828 DQ4 =135, DQ5 =123, DQ6 =139, DQ7 =143
8182 22:13:33.730104 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8183 22:13:33.737011 DQ12 =131, DQ13 =135, DQ14 =139, DQ15 =135
8184 22:13:33.737094
8185 22:13:33.737158
8186 22:13:33.737215 ==
8187 22:13:33.740014 Dram Type= 6, Freq= 0, CH_0, rank 1
8188 22:13:33.743478 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8189 22:13:33.743558 ==
8190 22:13:33.743622
8191 22:13:33.743680
8192 22:13:33.746684 TX Vref Scan disable
8193 22:13:33.746764 == TX Byte 0 ==
8194 22:13:33.753171 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8195 22:13:33.757132 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8196 22:13:33.757214 == TX Byte 1 ==
8197 22:13:33.763517 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8198 22:13:33.766627 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8199 22:13:33.766700 ==
8200 22:13:33.769844 Dram Type= 6, Freq= 0, CH_0, rank 1
8201 22:13:33.773290 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8202 22:13:33.773369 ==
8203 22:13:33.786832
8204 22:13:33.789987 TX Vref early break, caculate TX vref
8205 22:13:33.793834 TX Vref=16, minBit 3, minWin=21, winSum=379
8206 22:13:33.796747 TX Vref=18, minBit 2, minWin=23, winSum=383
8207 22:13:33.799959 TX Vref=20, minBit 4, minWin=23, winSum=391
8208 22:13:33.803361 TX Vref=22, minBit 1, minWin=24, winSum=401
8209 22:13:33.806429 TX Vref=24, minBit 1, minWin=24, winSum=406
8210 22:13:33.813340 TX Vref=26, minBit 1, minWin=24, winSum=414
8211 22:13:33.816620 TX Vref=28, minBit 0, minWin=25, winSum=408
8212 22:13:33.819582 TX Vref=30, minBit 0, minWin=24, winSum=399
8213 22:13:33.823348 TX Vref=32, minBit 1, minWin=23, winSum=390
8214 22:13:33.829520 [TxChooseVref] Worse bit 0, Min win 25, Win sum 408, Final Vref 28
8215 22:13:33.829606
8216 22:13:33.832984 Final TX Range 0 Vref 28
8217 22:13:33.833067
8218 22:13:33.833150 ==
8219 22:13:33.836004 Dram Type= 6, Freq= 0, CH_0, rank 1
8220 22:13:33.839925 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8221 22:13:33.840010 ==
8222 22:13:33.840094
8223 22:13:33.840172
8224 22:13:33.842791 TX Vref Scan disable
8225 22:13:33.849962 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8226 22:13:33.850046 == TX Byte 0 ==
8227 22:13:33.853324 u2DelayCellOfst[0]=15 cells (4 PI)
8228 22:13:33.857243 u2DelayCellOfst[1]=18 cells (5 PI)
8229 22:13:33.859987 u2DelayCellOfst[2]=15 cells (4 PI)
8230 22:13:33.862918 u2DelayCellOfst[3]=15 cells (4 PI)
8231 22:13:33.866546 u2DelayCellOfst[4]=11 cells (3 PI)
8232 22:13:33.869867 u2DelayCellOfst[5]=0 cells (0 PI)
8233 22:13:33.873024 u2DelayCellOfst[6]=22 cells (6 PI)
8234 22:13:33.873453 u2DelayCellOfst[7]=22 cells (6 PI)
8235 22:13:33.879567 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
8236 22:13:33.883096 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8237 22:13:33.886248 == TX Byte 1 ==
8238 22:13:33.886776 u2DelayCellOfst[8]=0 cells (0 PI)
8239 22:13:33.889588 u2DelayCellOfst[9]=0 cells (0 PI)
8240 22:13:33.892655 u2DelayCellOfst[10]=7 cells (2 PI)
8241 22:13:33.896110 u2DelayCellOfst[11]=3 cells (1 PI)
8242 22:13:33.899128 u2DelayCellOfst[12]=11 cells (3 PI)
8243 22:13:33.902886 u2DelayCellOfst[13]=11 cells (3 PI)
8244 22:13:33.906017 u2DelayCellOfst[14]=18 cells (5 PI)
8245 22:13:33.909353 u2DelayCellOfst[15]=11 cells (3 PI)
8246 22:13:33.912396 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8247 22:13:33.919285 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8248 22:13:33.919810 DramC Write-DBI on
8249 22:13:33.920149 ==
8250 22:13:33.922341 Dram Type= 6, Freq= 0, CH_0, rank 1
8251 22:13:33.929329 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8252 22:13:33.929856 ==
8253 22:13:33.930194
8254 22:13:33.930497
8255 22:13:33.930789 TX Vref Scan disable
8256 22:13:33.933413 == TX Byte 0 ==
8257 22:13:33.936307 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
8258 22:13:33.939287 == TX Byte 1 ==
8259 22:13:33.942512 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8260 22:13:33.946246 DramC Write-DBI off
8261 22:13:33.946807
8262 22:13:33.947231 [DATLAT]
8263 22:13:33.947581 Freq=1600, CH0 RK1
8264 22:13:33.947907
8265 22:13:33.949371 DATLAT Default: 0xf
8266 22:13:33.952338 0, 0xFFFF, sum = 0
8267 22:13:33.952981 1, 0xFFFF, sum = 0
8268 22:13:33.955607 2, 0xFFFF, sum = 0
8269 22:13:33.956098 3, 0xFFFF, sum = 0
8270 22:13:33.959456 4, 0xFFFF, sum = 0
8271 22:13:33.959903 5, 0xFFFF, sum = 0
8272 22:13:33.962117 6, 0xFFFF, sum = 0
8273 22:13:33.962546 7, 0xFFFF, sum = 0
8274 22:13:33.965823 8, 0xFFFF, sum = 0
8275 22:13:33.966359 9, 0xFFFF, sum = 0
8276 22:13:33.969390 10, 0xFFFF, sum = 0
8277 22:13:33.969927 11, 0xFFFF, sum = 0
8278 22:13:33.972454 12, 0xFFFF, sum = 0
8279 22:13:33.972927 13, 0xFFFF, sum = 0
8280 22:13:33.976117 14, 0x0, sum = 1
8281 22:13:33.976589 15, 0x0, sum = 2
8282 22:13:33.979014 16, 0x0, sum = 3
8283 22:13:33.979471 17, 0x0, sum = 4
8284 22:13:33.982619 best_step = 15
8285 22:13:33.983044
8286 22:13:33.983428 ==
8287 22:13:33.985360 Dram Type= 6, Freq= 0, CH_0, rank 1
8288 22:13:33.988767 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8289 22:13:33.989196 ==
8290 22:13:33.992468 RX Vref Scan: 0
8291 22:13:33.993127
8292 22:13:33.993476 RX Vref 0 -> 0, step: 1
8293 22:13:33.993793
8294 22:13:33.995366 RX Delay 11 -> 252, step: 4
8295 22:13:34.002172 iDelay=195, Bit 0, Center 126 (75 ~ 178) 104
8296 22:13:34.005365 iDelay=195, Bit 1, Center 134 (79 ~ 190) 112
8297 22:13:34.008685 iDelay=195, Bit 2, Center 124 (71 ~ 178) 108
8298 22:13:34.012060 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8299 22:13:34.015379 iDelay=195, Bit 4, Center 132 (79 ~ 186) 108
8300 22:13:34.022009 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
8301 22:13:34.025703 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8302 22:13:34.028844 iDelay=195, Bit 7, Center 140 (87 ~ 194) 108
8303 22:13:34.032097 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8304 22:13:34.035295 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8305 22:13:34.041741 iDelay=195, Bit 10, Center 126 (71 ~ 182) 112
8306 22:13:34.045340 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8307 22:13:34.048599 iDelay=195, Bit 12, Center 130 (75 ~ 186) 112
8308 22:13:34.051747 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8309 22:13:34.055508 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
8310 22:13:34.061581 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8311 22:13:34.062231 ==
8312 22:13:34.065047 Dram Type= 6, Freq= 0, CH_0, rank 1
8313 22:13:34.067832 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8314 22:13:34.068305 ==
8315 22:13:34.068676 DQS Delay:
8316 22:13:34.072442 DQS0 = 0, DQS1 = 0
8317 22:13:34.073012 DQM Delay:
8318 22:13:34.074753 DQM0 = 130, DQM1 = 125
8319 22:13:34.075250 DQ Delay:
8320 22:13:34.078131 DQ0 =126, DQ1 =134, DQ2 =124, DQ3 =128
8321 22:13:34.081317 DQ4 =132, DQ5 =120, DQ6 =138, DQ7 =140
8322 22:13:34.085028 DQ8 =116, DQ9 =112, DQ10 =126, DQ11 =120
8323 22:13:34.091537 DQ12 =130, DQ13 =132, DQ14 =136, DQ15 =132
8324 22:13:34.092007
8325 22:13:34.092375
8326 22:13:34.092712
8327 22:13:34.093116 [DramC_TX_OE_Calibration] TA2
8328 22:13:34.095493 Original DQ_B0 (3 6) =30, OEN = 27
8329 22:13:34.098416 Original DQ_B1 (3 6) =30, OEN = 27
8330 22:13:34.101134 24, 0x0, End_B0=24 End_B1=24
8331 22:13:34.105109 25, 0x0, End_B0=25 End_B1=25
8332 22:13:34.107862 26, 0x0, End_B0=26 End_B1=26
8333 22:13:34.111029 27, 0x0, End_B0=27 End_B1=27
8334 22:13:34.111541 28, 0x0, End_B0=28 End_B1=28
8335 22:13:34.114450 29, 0x0, End_B0=29 End_B1=29
8336 22:13:34.117828 30, 0x0, End_B0=30 End_B1=30
8337 22:13:34.120848 31, 0x4141, End_B0=30 End_B1=30
8338 22:13:34.124819 Byte0 end_step=30 best_step=27
8339 22:13:34.125487 Byte1 end_step=30 best_step=27
8340 22:13:34.127425 Byte0 TX OE(2T, 0.5T) = (3, 3)
8341 22:13:34.131203 Byte1 TX OE(2T, 0.5T) = (3, 3)
8342 22:13:34.131762
8343 22:13:34.132132
8344 22:13:34.141170 [DQSOSCAuto] RK1, (LSB)MR18= 0x1e01, (MSB)MR19= 0x303, tDQSOscB0 = 409 ps tDQSOscB1 = 394 ps
8345 22:13:34.141723 CH0 RK1: MR19=303, MR18=1E01
8346 22:13:34.147293 CH0_RK1: MR19=0x303, MR18=0x1E01, DQSOSC=394, MR23=63, INC=23, DEC=15
8347 22:13:34.150800 [RxdqsGatingPostProcess] freq 1600
8348 22:13:34.157618 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8349 22:13:34.160542 best DQS0 dly(2T, 0.5T) = (1, 1)
8350 22:13:34.163710 best DQS1 dly(2T, 0.5T) = (1, 1)
8351 22:13:34.167184 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8352 22:13:34.171134 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8353 22:13:34.173737 best DQS0 dly(2T, 0.5T) = (1, 1)
8354 22:13:34.174221 best DQS1 dly(2T, 0.5T) = (1, 1)
8355 22:13:34.177106 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8356 22:13:34.180821 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8357 22:13:34.183573 Pre-setting of DQS Precalculation
8358 22:13:34.190762 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8359 22:13:34.191374 ==
8360 22:13:34.193568 Dram Type= 6, Freq= 0, CH_1, rank 0
8361 22:13:34.197047 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8362 22:13:34.197462 ==
8363 22:13:34.203351 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8364 22:13:34.206939 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8365 22:13:34.210387 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8366 22:13:34.216195 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8367 22:13:34.226062 [CA 0] Center 41 (12~71) winsize 60
8368 22:13:34.229124 [CA 1] Center 42 (12~72) winsize 61
8369 22:13:34.232495 [CA 2] Center 37 (8~66) winsize 59
8370 22:13:34.236137 [CA 3] Center 36 (7~65) winsize 59
8371 22:13:34.239032 [CA 4] Center 37 (8~66) winsize 59
8372 22:13:34.242273 [CA 5] Center 36 (6~66) winsize 61
8373 22:13:34.242680
8374 22:13:34.245615 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8375 22:13:34.246020
8376 22:13:34.249536 [CATrainingPosCal] consider 1 rank data
8377 22:13:34.252650 u2DelayCellTimex100 = 258/100 ps
8378 22:13:34.258729 CA0 delay=41 (12~71),Diff = 5 PI (18 cell)
8379 22:13:34.261970 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8380 22:13:34.265076 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8381 22:13:34.268966 CA3 delay=36 (7~65),Diff = 0 PI (0 cell)
8382 22:13:34.272687 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8383 22:13:34.275438 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
8384 22:13:34.276003
8385 22:13:34.279179 CA PerBit enable=1, Macro0, CA PI delay=36
8386 22:13:34.279729
8387 22:13:34.283027 [CBTSetCACLKResult] CA Dly = 36
8388 22:13:34.285647 CS Dly: 9 (0~40)
8389 22:13:34.288961 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8390 22:13:34.292426 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8391 22:13:34.292983 ==
8392 22:13:34.295240 Dram Type= 6, Freq= 0, CH_1, rank 1
8393 22:13:34.302239 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8394 22:13:34.302799 ==
8395 22:13:34.305173 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8396 22:13:34.308564 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8397 22:13:34.315445 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8398 22:13:34.321605 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8399 22:13:34.329379 [CA 0] Center 41 (12~71) winsize 60
8400 22:13:34.332086 [CA 1] Center 42 (13~72) winsize 60
8401 22:13:34.335564 [CA 2] Center 37 (8~67) winsize 60
8402 22:13:34.339357 [CA 3] Center 36 (7~66) winsize 60
8403 22:13:34.342320 [CA 4] Center 37 (8~67) winsize 60
8404 22:13:34.345630 [CA 5] Center 37 (8~66) winsize 59
8405 22:13:34.346219
8406 22:13:34.348833 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8407 22:13:34.349442
8408 22:13:34.352536 [CATrainingPosCal] consider 2 rank data
8409 22:13:34.355588 u2DelayCellTimex100 = 258/100 ps
8410 22:13:34.362191 CA0 delay=41 (12~71),Diff = 5 PI (18 cell)
8411 22:13:34.365388 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8412 22:13:34.368943 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8413 22:13:34.372007 CA3 delay=36 (7~65),Diff = 0 PI (0 cell)
8414 22:13:34.375127 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8415 22:13:34.379031 CA5 delay=37 (8~66),Diff = 1 PI (3 cell)
8416 22:13:34.379525
8417 22:13:34.382056 CA PerBit enable=1, Macro0, CA PI delay=36
8418 22:13:34.382511
8419 22:13:34.386049 [CBTSetCACLKResult] CA Dly = 36
8420 22:13:34.388205 CS Dly: 10 (0~43)
8421 22:13:34.391482 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8422 22:13:34.395052 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8423 22:13:34.395547
8424 22:13:34.398430 ----->DramcWriteLeveling(PI) begin...
8425 22:13:34.398900 ==
8426 22:13:34.401667 Dram Type= 6, Freq= 0, CH_1, rank 0
8427 22:13:34.408015 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8428 22:13:34.408438 ==
8429 22:13:34.411474 Write leveling (Byte 0): 24 => 24
8430 22:13:34.415308 Write leveling (Byte 1): 26 => 26
8431 22:13:34.415829 DramcWriteLeveling(PI) end<-----
8432 22:13:34.417998
8433 22:13:34.418493 ==
8434 22:13:34.421575 Dram Type= 6, Freq= 0, CH_1, rank 0
8435 22:13:34.424423 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8436 22:13:34.424845 ==
8437 22:13:34.428077 [Gating] SW mode calibration
8438 22:13:34.434809 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8439 22:13:34.437943 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8440 22:13:34.444501 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8441 22:13:34.447612 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8442 22:13:34.451091 1 4 8 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
8443 22:13:34.457973 1 4 12 | B1->B0 | 3332 3434 | 1 1 | (0 0) (1 1)
8444 22:13:34.460642 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8445 22:13:34.464258 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8446 22:13:34.471222 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8447 22:13:34.474285 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8448 22:13:34.477574 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8449 22:13:34.484424 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8450 22:13:34.487938 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8451 22:13:34.491227 1 5 12 | B1->B0 | 3030 2727 | 0 0 | (0 1) (1 0)
8452 22:13:34.497800 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8453 22:13:34.500537 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8454 22:13:34.504165 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8455 22:13:34.510440 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8456 22:13:34.514096 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8457 22:13:34.517685 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8458 22:13:34.523585 1 6 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8459 22:13:34.527037 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8460 22:13:34.530071 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8461 22:13:34.537157 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8462 22:13:34.540309 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8463 22:13:34.543288 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8464 22:13:34.550222 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8465 22:13:34.553289 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8466 22:13:34.557093 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8467 22:13:34.563291 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8468 22:13:34.567459 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8469 22:13:34.570230 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8470 22:13:34.576573 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8471 22:13:34.579781 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8472 22:13:34.583090 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8473 22:13:34.589861 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8474 22:13:34.593461 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8475 22:13:34.596648 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8476 22:13:34.603148 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8477 22:13:34.606169 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8478 22:13:34.609905 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8479 22:13:34.615820 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8480 22:13:34.619657 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8481 22:13:34.622793 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8482 22:13:34.629584 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8483 22:13:34.632581 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8484 22:13:34.635980 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8485 22:13:34.638883 Total UI for P1: 0, mck2ui 16
8486 22:13:34.642664 best dqsien dly found for B0: ( 1, 9, 10)
8487 22:13:34.645722 Total UI for P1: 0, mck2ui 16
8488 22:13:34.649213 best dqsien dly found for B1: ( 1, 9, 10)
8489 22:13:34.652557 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8490 22:13:34.655400 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8491 22:13:34.659179
8492 22:13:34.662347 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8493 22:13:34.665861 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8494 22:13:34.668878 [Gating] SW calibration Done
8495 22:13:34.669451 ==
8496 22:13:34.672282 Dram Type= 6, Freq= 0, CH_1, rank 0
8497 22:13:34.675436 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8498 22:13:34.676013 ==
8499 22:13:34.679201 RX Vref Scan: 0
8500 22:13:34.679687
8501 22:13:34.680204 RX Vref 0 -> 0, step: 1
8502 22:13:34.680573
8503 22:13:34.682425 RX Delay 0 -> 252, step: 8
8504 22:13:34.685145 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8505 22:13:34.688456 iDelay=208, Bit 1, Center 131 (80 ~ 183) 104
8506 22:13:34.695175 iDelay=208, Bit 2, Center 127 (72 ~ 183) 112
8507 22:13:34.698727 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8508 22:13:34.701809 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8509 22:13:34.705144 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8510 22:13:34.708399 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8511 22:13:34.715227 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8512 22:13:34.718216 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8513 22:13:34.722114 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8514 22:13:34.725122 iDelay=208, Bit 10, Center 127 (72 ~ 183) 112
8515 22:13:34.728535 iDelay=208, Bit 11, Center 119 (64 ~ 175) 112
8516 22:13:34.735119 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8517 22:13:34.738466 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8518 22:13:34.741963 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8519 22:13:34.744982 iDelay=208, Bit 15, Center 135 (80 ~ 191) 112
8520 22:13:34.748267 ==
8521 22:13:34.748836 Dram Type= 6, Freq= 0, CH_1, rank 0
8522 22:13:34.754558 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8523 22:13:34.755179 ==
8524 22:13:34.755565 DQS Delay:
8525 22:13:34.757661 DQS0 = 0, DQS1 = 0
8526 22:13:34.758128 DQM Delay:
8527 22:13:34.761145 DQM0 = 137, DQM1 = 127
8528 22:13:34.761614 DQ Delay:
8529 22:13:34.764544 DQ0 =139, DQ1 =131, DQ2 =127, DQ3 =135
8530 22:13:34.767842 DQ4 =135, DQ5 =151, DQ6 =143, DQ7 =135
8531 22:13:34.771167 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =119
8532 22:13:34.774896 DQ12 =135, DQ13 =139, DQ14 =135, DQ15 =135
8533 22:13:34.775513
8534 22:13:34.775884
8535 22:13:34.777476 ==
8536 22:13:34.777945 Dram Type= 6, Freq= 0, CH_1, rank 0
8537 22:13:34.784033 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8538 22:13:34.784538 ==
8539 22:13:34.784916
8540 22:13:34.785257
8541 22:13:34.787491 TX Vref Scan disable
8542 22:13:34.788075 == TX Byte 0 ==
8543 22:13:34.790420 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8544 22:13:34.797571 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8545 22:13:34.798148 == TX Byte 1 ==
8546 22:13:34.803572 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8547 22:13:34.806962 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8548 22:13:34.807608 ==
8549 22:13:34.810138 Dram Type= 6, Freq= 0, CH_1, rank 0
8550 22:13:34.813590 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8551 22:13:34.814060 ==
8552 22:13:34.826000
8553 22:13:34.829320 TX Vref early break, caculate TX vref
8554 22:13:34.832118 TX Vref=16, minBit 6, minWin=21, winSum=374
8555 22:13:34.835447 TX Vref=18, minBit 0, minWin=22, winSum=387
8556 22:13:34.838979 TX Vref=20, minBit 0, minWin=22, winSum=394
8557 22:13:34.842465 TX Vref=22, minBit 0, minWin=24, winSum=405
8558 22:13:34.846076 TX Vref=24, minBit 0, minWin=24, winSum=415
8559 22:13:34.852189 TX Vref=26, minBit 0, minWin=25, winSum=424
8560 22:13:34.855234 TX Vref=28, minBit 0, minWin=25, winSum=420
8561 22:13:34.858871 TX Vref=30, minBit 0, minWin=25, winSum=413
8562 22:13:34.862066 TX Vref=32, minBit 5, minWin=23, winSum=401
8563 22:13:34.868734 [TxChooseVref] Worse bit 0, Min win 25, Win sum 424, Final Vref 26
8564 22:13:34.869308
8565 22:13:34.872267 Final TX Range 0 Vref 26
8566 22:13:34.872840
8567 22:13:34.873208 ==
8568 22:13:34.875434 Dram Type= 6, Freq= 0, CH_1, rank 0
8569 22:13:34.879142 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8570 22:13:34.879636 ==
8571 22:13:34.880010
8572 22:13:34.880346
8573 22:13:34.882326 TX Vref Scan disable
8574 22:13:34.885893 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8575 22:13:34.888667 == TX Byte 0 ==
8576 22:13:34.891612 u2DelayCellOfst[0]=18 cells (5 PI)
8577 22:13:34.895318 u2DelayCellOfst[1]=11 cells (3 PI)
8578 22:13:34.899018 u2DelayCellOfst[2]=0 cells (0 PI)
8579 22:13:34.901395 u2DelayCellOfst[3]=3 cells (1 PI)
8580 22:13:34.905406 u2DelayCellOfst[4]=7 cells (2 PI)
8581 22:13:34.908336 u2DelayCellOfst[5]=22 cells (6 PI)
8582 22:13:34.908804 u2DelayCellOfst[6]=18 cells (5 PI)
8583 22:13:34.911390 u2DelayCellOfst[7]=3 cells (1 PI)
8584 22:13:34.917826 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8585 22:13:34.921356 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8586 22:13:34.921823 == TX Byte 1 ==
8587 22:13:34.924613 u2DelayCellOfst[8]=0 cells (0 PI)
8588 22:13:34.927847 u2DelayCellOfst[9]=3 cells (1 PI)
8589 22:13:34.931267 u2DelayCellOfst[10]=11 cells (3 PI)
8590 22:13:34.934485 u2DelayCellOfst[11]=7 cells (2 PI)
8591 22:13:34.938086 u2DelayCellOfst[12]=15 cells (4 PI)
8592 22:13:34.941434 u2DelayCellOfst[13]=15 cells (4 PI)
8593 22:13:34.944348 u2DelayCellOfst[14]=18 cells (5 PI)
8594 22:13:34.947753 u2DelayCellOfst[15]=18 cells (5 PI)
8595 22:13:34.951641 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8596 22:13:34.958072 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8597 22:13:34.958657 DramC Write-DBI on
8598 22:13:34.959035 ==
8599 22:13:34.961135 Dram Type= 6, Freq= 0, CH_1, rank 0
8600 22:13:34.964446 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8601 22:13:34.967524 ==
8602 22:13:34.968099
8603 22:13:34.968583
8604 22:13:34.969038 TX Vref Scan disable
8605 22:13:34.971096 == TX Byte 0 ==
8606 22:13:34.974345 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8607 22:13:34.977317 == TX Byte 1 ==
8608 22:13:34.980478 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8609 22:13:34.984401 DramC Write-DBI off
8610 22:13:34.984859
8611 22:13:34.985224 [DATLAT]
8612 22:13:34.985560 Freq=1600, CH1 RK0
8613 22:13:34.985889
8614 22:13:34.987644 DATLAT Default: 0xf
8615 22:13:34.990686 0, 0xFFFF, sum = 0
8616 22:13:34.991288 1, 0xFFFF, sum = 0
8617 22:13:34.994113 2, 0xFFFF, sum = 0
8618 22:13:34.994711 3, 0xFFFF, sum = 0
8619 22:13:34.997485 4, 0xFFFF, sum = 0
8620 22:13:34.998049 5, 0xFFFF, sum = 0
8621 22:13:35.000752 6, 0xFFFF, sum = 0
8622 22:13:35.001223 7, 0xFFFF, sum = 0
8623 22:13:35.004509 8, 0xFFFF, sum = 0
8624 22:13:35.004975 9, 0xFFFF, sum = 0
8625 22:13:35.007624 10, 0xFFFF, sum = 0
8626 22:13:35.008092 11, 0xFFFF, sum = 0
8627 22:13:35.010449 12, 0xFFFF, sum = 0
8628 22:13:35.010920 13, 0xFFFF, sum = 0
8629 22:13:35.013517 14, 0x0, sum = 1
8630 22:13:35.013984 15, 0x0, sum = 2
8631 22:13:35.017266 16, 0x0, sum = 3
8632 22:13:35.017733 17, 0x0, sum = 4
8633 22:13:35.020757 best_step = 15
8634 22:13:35.021249
8635 22:13:35.021738 ==
8636 22:13:35.023569 Dram Type= 6, Freq= 0, CH_1, rank 0
8637 22:13:35.026993 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8638 22:13:35.027574 ==
8639 22:13:35.030220 RX Vref Scan: 1
8640 22:13:35.030722
8641 22:13:35.031215 Set Vref Range= 24 -> 127
8642 22:13:35.031664
8643 22:13:35.033534 RX Vref 24 -> 127, step: 1
8644 22:13:35.033951
8645 22:13:35.036737 RX Delay 11 -> 252, step: 4
8646 22:13:35.037154
8647 22:13:35.040416 Set Vref, RX VrefLevel [Byte0]: 24
8648 22:13:35.043462 [Byte1]: 24
8649 22:13:35.043886
8650 22:13:35.046567 Set Vref, RX VrefLevel [Byte0]: 25
8651 22:13:35.049884 [Byte1]: 25
8652 22:13:35.053987
8653 22:13:35.054511 Set Vref, RX VrefLevel [Byte0]: 26
8654 22:13:35.057315 [Byte1]: 26
8655 22:13:35.061800
8656 22:13:35.062325 Set Vref, RX VrefLevel [Byte0]: 27
8657 22:13:35.064639 [Byte1]: 27
8658 22:13:35.068886
8659 22:13:35.069553 Set Vref, RX VrefLevel [Byte0]: 28
8660 22:13:35.072490 [Byte1]: 28
8661 22:13:35.076506
8662 22:13:35.077034 Set Vref, RX VrefLevel [Byte0]: 29
8663 22:13:35.079586 [Byte1]: 29
8664 22:13:35.083997
8665 22:13:35.084412 Set Vref, RX VrefLevel [Byte0]: 30
8666 22:13:35.087593 [Byte1]: 30
8667 22:13:35.091669
8668 22:13:35.092083 Set Vref, RX VrefLevel [Byte0]: 31
8669 22:13:35.095293 [Byte1]: 31
8670 22:13:35.099590
8671 22:13:35.100147 Set Vref, RX VrefLevel [Byte0]: 32
8672 22:13:35.102803 [Byte1]: 32
8673 22:13:35.107229
8674 22:13:35.107823 Set Vref, RX VrefLevel [Byte0]: 33
8675 22:13:35.110444 [Byte1]: 33
8676 22:13:35.114646
8677 22:13:35.115105 Set Vref, RX VrefLevel [Byte0]: 34
8678 22:13:35.117995 [Byte1]: 34
8679 22:13:35.122462
8680 22:13:35.125753 Set Vref, RX VrefLevel [Byte0]: 35
8681 22:13:35.128811 [Byte1]: 35
8682 22:13:35.129365
8683 22:13:35.132087 Set Vref, RX VrefLevel [Byte0]: 36
8684 22:13:35.135698 [Byte1]: 36
8685 22:13:35.136228
8686 22:13:35.138789 Set Vref, RX VrefLevel [Byte0]: 37
8687 22:13:35.142135 [Byte1]: 37
8688 22:13:35.145407
8689 22:13:35.145921 Set Vref, RX VrefLevel [Byte0]: 38
8690 22:13:35.148149 [Byte1]: 38
8691 22:13:35.152774
8692 22:13:35.153291 Set Vref, RX VrefLevel [Byte0]: 39
8693 22:13:35.156164 [Byte1]: 39
8694 22:13:35.160648
8695 22:13:35.161160 Set Vref, RX VrefLevel [Byte0]: 40
8696 22:13:35.163561 [Byte1]: 40
8697 22:13:35.168013
8698 22:13:35.168526 Set Vref, RX VrefLevel [Byte0]: 41
8699 22:13:35.171143 [Byte1]: 41
8700 22:13:35.175782
8701 22:13:35.176372 Set Vref, RX VrefLevel [Byte0]: 42
8702 22:13:35.178476 [Byte1]: 42
8703 22:13:35.182985
8704 22:13:35.183440 Set Vref, RX VrefLevel [Byte0]: 43
8705 22:13:35.186364 [Byte1]: 43
8706 22:13:35.191171
8707 22:13:35.191589 Set Vref, RX VrefLevel [Byte0]: 44
8708 22:13:35.193889 [Byte1]: 44
8709 22:13:35.198423
8710 22:13:35.198838 Set Vref, RX VrefLevel [Byte0]: 45
8711 22:13:35.201984 [Byte1]: 45
8712 22:13:35.206435
8713 22:13:35.207004 Set Vref, RX VrefLevel [Byte0]: 46
8714 22:13:35.209203 [Byte1]: 46
8715 22:13:35.213385
8716 22:13:35.214042 Set Vref, RX VrefLevel [Byte0]: 47
8717 22:13:35.216636 [Byte1]: 47
8718 22:13:35.220890
8719 22:13:35.224514 Set Vref, RX VrefLevel [Byte0]: 48
8720 22:13:35.228255 [Byte1]: 48
8721 22:13:35.228826
8722 22:13:35.230611 Set Vref, RX VrefLevel [Byte0]: 49
8723 22:13:35.234422 [Byte1]: 49
8724 22:13:35.234992
8725 22:13:35.237581 Set Vref, RX VrefLevel [Byte0]: 50
8726 22:13:35.241060 [Byte1]: 50
8727 22:13:35.244122
8728 22:13:35.244761 Set Vref, RX VrefLevel [Byte0]: 51
8729 22:13:35.247481 [Byte1]: 51
8730 22:13:35.251977
8731 22:13:35.252540 Set Vref, RX VrefLevel [Byte0]: 52
8732 22:13:35.258540 [Byte1]: 52
8733 22:13:35.259128
8734 22:13:35.261118 Set Vref, RX VrefLevel [Byte0]: 53
8735 22:13:35.264615 [Byte1]: 53
8736 22:13:35.265079
8737 22:13:35.267785 Set Vref, RX VrefLevel [Byte0]: 54
8738 22:13:35.271469 [Byte1]: 54
8739 22:13:35.274977
8740 22:13:35.275607 Set Vref, RX VrefLevel [Byte0]: 55
8741 22:13:35.277891 [Byte1]: 55
8742 22:13:35.282049
8743 22:13:35.282651 Set Vref, RX VrefLevel [Byte0]: 56
8744 22:13:35.285531 [Byte1]: 56
8745 22:13:35.289755
8746 22:13:35.290342 Set Vref, RX VrefLevel [Byte0]: 57
8747 22:13:35.293174 [Byte1]: 57
8748 22:13:35.296978
8749 22:13:35.297435 Set Vref, RX VrefLevel [Byte0]: 58
8750 22:13:35.300440 [Byte1]: 58
8751 22:13:35.305176
8752 22:13:35.305741 Set Vref, RX VrefLevel [Byte0]: 59
8753 22:13:35.308125 [Byte1]: 59
8754 22:13:35.312911
8755 22:13:35.313478 Set Vref, RX VrefLevel [Byte0]: 60
8756 22:13:35.315554 [Byte1]: 60
8757 22:13:35.320360
8758 22:13:35.320928 Set Vref, RX VrefLevel [Byte0]: 61
8759 22:13:35.323262 [Byte1]: 61
8760 22:13:35.327832
8761 22:13:35.328401 Set Vref, RX VrefLevel [Byte0]: 62
8762 22:13:35.331004 [Byte1]: 62
8763 22:13:35.335728
8764 22:13:35.336303 Set Vref, RX VrefLevel [Byte0]: 63
8765 22:13:35.338957 [Byte1]: 63
8766 22:13:35.343213
8767 22:13:35.343673 Set Vref, RX VrefLevel [Byte0]: 64
8768 22:13:35.346364 [Byte1]: 64
8769 22:13:35.350922
8770 22:13:35.351548 Set Vref, RX VrefLevel [Byte0]: 65
8771 22:13:35.353925 [Byte1]: 65
8772 22:13:35.357882
8773 22:13:35.358342 Set Vref, RX VrefLevel [Byte0]: 66
8774 22:13:35.361711 [Byte1]: 66
8775 22:13:35.365439
8776 22:13:35.365900 Set Vref, RX VrefLevel [Byte0]: 67
8777 22:13:35.369228 [Byte1]: 67
8778 22:13:35.373884
8779 22:13:35.374445 Set Vref, RX VrefLevel [Byte0]: 68
8780 22:13:35.376538 [Byte1]: 68
8781 22:13:35.381425
8782 22:13:35.382004 Set Vref, RX VrefLevel [Byte0]: 69
8783 22:13:35.384321 [Byte1]: 69
8784 22:13:35.388733
8785 22:13:35.389288 Set Vref, RX VrefLevel [Byte0]: 70
8786 22:13:35.391713 [Byte1]: 70
8787 22:13:35.396454
8788 22:13:35.397189 Set Vref, RX VrefLevel [Byte0]: 71
8789 22:13:35.399693 [Byte1]: 71
8790 22:13:35.403763
8791 22:13:35.404226 Set Vref, RX VrefLevel [Byte0]: 72
8792 22:13:35.407479 [Byte1]: 72
8793 22:13:35.411487
8794 22:13:35.412046 Final RX Vref Byte 0 = 53 to rank0
8795 22:13:35.414964 Final RX Vref Byte 1 = 58 to rank0
8796 22:13:35.418084 Final RX Vref Byte 0 = 53 to rank1
8797 22:13:35.421426 Final RX Vref Byte 1 = 58 to rank1==
8798 22:13:35.425106 Dram Type= 6, Freq= 0, CH_1, rank 0
8799 22:13:35.431510 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8800 22:13:35.431979 ==
8801 22:13:35.432349 DQS Delay:
8802 22:13:35.432687 DQS0 = 0, DQS1 = 0
8803 22:13:35.434622 DQM Delay:
8804 22:13:35.435132 DQM0 = 133, DQM1 = 127
8805 22:13:35.437941 DQ Delay:
8806 22:13:35.441356 DQ0 =140, DQ1 =128, DQ2 =124, DQ3 =130
8807 22:13:35.444566 DQ4 =130, DQ5 =146, DQ6 =142, DQ7 =128
8808 22:13:35.448076 DQ8 =114, DQ9 =116, DQ10 =130, DQ11 =116
8809 22:13:35.451350 DQ12 =136, DQ13 =136, DQ14 =136, DQ15 =138
8810 22:13:35.451906
8811 22:13:35.452273
8812 22:13:35.452609
8813 22:13:35.454452 [DramC_TX_OE_Calibration] TA2
8814 22:13:35.458183 Original DQ_B0 (3 6) =30, OEN = 27
8815 22:13:35.461546 Original DQ_B1 (3 6) =30, OEN = 27
8816 22:13:35.464643 24, 0x0, End_B0=24 End_B1=24
8817 22:13:35.465128 25, 0x0, End_B0=25 End_B1=25
8818 22:13:35.467715 26, 0x0, End_B0=26 End_B1=26
8819 22:13:35.471157 27, 0x0, End_B0=27 End_B1=27
8820 22:13:35.474595 28, 0x0, End_B0=28 End_B1=28
8821 22:13:35.478041 29, 0x0, End_B0=29 End_B1=29
8822 22:13:35.478637 30, 0x0, End_B0=30 End_B1=30
8823 22:13:35.480742 31, 0x4141, End_B0=30 End_B1=30
8824 22:13:35.484401 Byte0 end_step=30 best_step=27
8825 22:13:35.487938 Byte1 end_step=30 best_step=27
8826 22:13:35.491162 Byte0 TX OE(2T, 0.5T) = (3, 3)
8827 22:13:35.494131 Byte1 TX OE(2T, 0.5T) = (3, 3)
8828 22:13:35.494692
8829 22:13:35.495053
8830 22:13:35.500986 [DQSOSCAuto] RK0, (LSB)MR18= 0x180e, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 397 ps
8831 22:13:35.503771 CH1 RK0: MR19=303, MR18=180E
8832 22:13:35.510525 CH1_RK0: MR19=0x303, MR18=0x180E, DQSOSC=397, MR23=63, INC=23, DEC=15
8833 22:13:35.511214
8834 22:13:35.514414 ----->DramcWriteLeveling(PI) begin...
8835 22:13:35.514883 ==
8836 22:13:35.517534 Dram Type= 6, Freq= 0, CH_1, rank 1
8837 22:13:35.520438 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8838 22:13:35.520900 ==
8839 22:13:35.523596 Write leveling (Byte 0): 25 => 25
8840 22:13:35.527296 Write leveling (Byte 1): 28 => 28
8841 22:13:35.530459 DramcWriteLeveling(PI) end<-----
8842 22:13:35.531015
8843 22:13:35.531479 ==
8844 22:13:35.534244 Dram Type= 6, Freq= 0, CH_1, rank 1
8845 22:13:35.537130 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8846 22:13:35.540143 ==
8847 22:13:35.540787 [Gating] SW mode calibration
8848 22:13:35.550361 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8849 22:13:35.553711 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8850 22:13:35.556833 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8851 22:13:35.563664 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8852 22:13:35.566686 1 4 8 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
8853 22:13:35.569846 1 4 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
8854 22:13:35.576314 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8855 22:13:35.579513 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8856 22:13:35.583127 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8857 22:13:35.589949 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8858 22:13:35.592802 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8859 22:13:35.596105 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8860 22:13:35.602859 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8861 22:13:35.606410 1 5 12 | B1->B0 | 2525 3434 | 0 1 | (1 0) (1 0)
8862 22:13:35.609376 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8863 22:13:35.615715 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8864 22:13:35.619649 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8865 22:13:35.622816 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8866 22:13:35.629168 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8867 22:13:35.632622 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8868 22:13:35.636133 1 6 8 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
8869 22:13:35.642361 1 6 12 | B1->B0 | 4646 2525 | 0 1 | (0 0) (0 0)
8870 22:13:35.645696 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8871 22:13:35.649443 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8872 22:13:35.655716 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8873 22:13:35.659136 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8874 22:13:35.662316 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8875 22:13:35.669293 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8876 22:13:35.672413 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8877 22:13:35.675533 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8878 22:13:35.681843 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8879 22:13:35.685527 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8880 22:13:35.688740 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8881 22:13:35.695856 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8882 22:13:35.698870 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8883 22:13:35.702187 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8884 22:13:35.709020 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8885 22:13:35.711836 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8886 22:13:35.715489 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8887 22:13:35.721672 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8888 22:13:35.724921 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8889 22:13:35.728330 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8890 22:13:35.735127 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8891 22:13:35.738002 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8892 22:13:35.741956 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8893 22:13:35.748433 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8894 22:13:35.751465 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8895 22:13:35.754760 Total UI for P1: 0, mck2ui 16
8896 22:13:35.757970 best dqsien dly found for B0: ( 1, 9, 12)
8897 22:13:35.761143 Total UI for P1: 0, mck2ui 16
8898 22:13:35.764843 best dqsien dly found for B1: ( 1, 9, 10)
8899 22:13:35.767749 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8900 22:13:35.771323 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8901 22:13:35.771893
8902 22:13:35.774569 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8903 22:13:35.782119 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8904 22:13:35.782721 [Gating] SW calibration Done
8905 22:13:35.783285 ==
8906 22:13:35.784233 Dram Type= 6, Freq= 0, CH_1, rank 1
8907 22:13:35.791532 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8908 22:13:35.792106 ==
8909 22:13:35.792480 RX Vref Scan: 0
8910 22:13:35.792822
8911 22:13:35.794451 RX Vref 0 -> 0, step: 1
8912 22:13:35.795188
8913 22:13:35.797597 RX Delay 0 -> 252, step: 8
8914 22:13:35.800578 iDelay=208, Bit 0, Center 143 (88 ~ 199) 112
8915 22:13:35.803847 iDelay=208, Bit 1, Center 131 (72 ~ 191) 120
8916 22:13:35.807318 iDelay=208, Bit 2, Center 123 (64 ~ 183) 120
8917 22:13:35.810421 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8918 22:13:35.817189 iDelay=208, Bit 4, Center 131 (72 ~ 191) 120
8919 22:13:35.820530 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8920 22:13:35.824269 iDelay=208, Bit 6, Center 147 (88 ~ 207) 120
8921 22:13:35.826937 iDelay=208, Bit 7, Center 131 (72 ~ 191) 120
8922 22:13:35.830329 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8923 22:13:35.837518 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8924 22:13:35.840774 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8925 22:13:35.843884 iDelay=208, Bit 11, Center 119 (64 ~ 175) 112
8926 22:13:35.847387 iDelay=208, Bit 12, Center 139 (80 ~ 199) 120
8927 22:13:35.853998 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8928 22:13:35.857024 iDelay=208, Bit 14, Center 139 (80 ~ 199) 120
8929 22:13:35.860879 iDelay=208, Bit 15, Center 139 (80 ~ 199) 120
8930 22:13:35.861439 ==
8931 22:13:35.863351 Dram Type= 6, Freq= 0, CH_1, rank 1
8932 22:13:35.867051 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8933 22:13:35.867650 ==
8934 22:13:35.870104 DQS Delay:
8935 22:13:35.870661 DQS0 = 0, DQS1 = 0
8936 22:13:35.873639 DQM Delay:
8937 22:13:35.874199 DQM0 = 136, DQM1 = 129
8938 22:13:35.876941 DQ Delay:
8939 22:13:35.880262 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8940 22:13:35.883604 DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =131
8941 22:13:35.886661 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8942 22:13:35.890069 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =139
8943 22:13:35.890627
8944 22:13:35.890993
8945 22:13:35.891363 ==
8946 22:13:35.892972 Dram Type= 6, Freq= 0, CH_1, rank 1
8947 22:13:35.896600 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8948 22:13:35.897162 ==
8949 22:13:35.897531
8950 22:13:35.897867
8951 22:13:35.899547 TX Vref Scan disable
8952 22:13:35.903617 == TX Byte 0 ==
8953 22:13:35.906632 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8954 22:13:35.909550 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8955 22:13:35.913112 == TX Byte 1 ==
8956 22:13:35.916304 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8957 22:13:35.919617 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8958 22:13:35.920082 ==
8959 22:13:35.923156 Dram Type= 6, Freq= 0, CH_1, rank 1
8960 22:13:35.929587 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8961 22:13:35.930189 ==
8962 22:13:35.941488
8963 22:13:35.944161 TX Vref early break, caculate TX vref
8964 22:13:35.947483 TX Vref=16, minBit 8, minWin=22, winSum=383
8965 22:13:35.951145 TX Vref=18, minBit 0, minWin=23, winSum=395
8966 22:13:35.954519 TX Vref=20, minBit 8, minWin=23, winSum=403
8967 22:13:35.957548 TX Vref=22, minBit 1, minWin=25, winSum=410
8968 22:13:35.961035 TX Vref=24, minBit 1, minWin=25, winSum=415
8969 22:13:35.967406 TX Vref=26, minBit 0, minWin=25, winSum=422
8970 22:13:35.970976 TX Vref=28, minBit 0, minWin=25, winSum=425
8971 22:13:35.974175 TX Vref=30, minBit 0, minWin=25, winSum=418
8972 22:13:35.978292 TX Vref=32, minBit 0, minWin=24, winSum=408
8973 22:13:35.980463 TX Vref=34, minBit 0, minWin=24, winSum=401
8974 22:13:35.987185 [TxChooseVref] Worse bit 0, Min win 25, Win sum 425, Final Vref 28
8975 22:13:35.987673
8976 22:13:35.991396 Final TX Range 0 Vref 28
8977 22:13:35.991969
8978 22:13:35.992343 ==
8979 22:13:35.993873 Dram Type= 6, Freq= 0, CH_1, rank 1
8980 22:13:35.997385 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8981 22:13:35.997857 ==
8982 22:13:35.998229
8983 22:13:35.998570
8984 22:13:36.001240 TX Vref Scan disable
8985 22:13:36.007266 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8986 22:13:36.007832 == TX Byte 0 ==
8987 22:13:36.010744 u2DelayCellOfst[0]=22 cells (6 PI)
8988 22:13:36.013763 u2DelayCellOfst[1]=15 cells (4 PI)
8989 22:13:36.017243 u2DelayCellOfst[2]=0 cells (0 PI)
8990 22:13:36.020119 u2DelayCellOfst[3]=7 cells (2 PI)
8991 22:13:36.023399 u2DelayCellOfst[4]=11 cells (3 PI)
8992 22:13:36.026522 u2DelayCellOfst[5]=22 cells (6 PI)
8993 22:13:36.030265 u2DelayCellOfst[6]=22 cells (6 PI)
8994 22:13:36.033805 u2DelayCellOfst[7]=7 cells (2 PI)
8995 22:13:36.037015 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8996 22:13:36.039902 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8997 22:13:36.043808 == TX Byte 1 ==
8998 22:13:36.047177 u2DelayCellOfst[8]=0 cells (0 PI)
8999 22:13:36.047769 u2DelayCellOfst[9]=7 cells (2 PI)
9000 22:13:36.050343 u2DelayCellOfst[10]=15 cells (4 PI)
9001 22:13:36.053758 u2DelayCellOfst[11]=7 cells (2 PI)
9002 22:13:36.057017 u2DelayCellOfst[12]=18 cells (5 PI)
9003 22:13:36.059889 u2DelayCellOfst[13]=18 cells (5 PI)
9004 22:13:36.063757 u2DelayCellOfst[14]=22 cells (6 PI)
9005 22:13:36.066881 u2DelayCellOfst[15]=18 cells (5 PI)
9006 22:13:36.073771 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
9007 22:13:36.076787 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
9008 22:13:36.077362 DramC Write-DBI on
9009 22:13:36.077737 ==
9010 22:13:36.080305 Dram Type= 6, Freq= 0, CH_1, rank 1
9011 22:13:36.086870 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9012 22:13:36.087579 ==
9013 22:13:36.087968
9014 22:13:36.088316
9015 22:13:36.088646 TX Vref Scan disable
9016 22:13:36.090759 == TX Byte 0 ==
9017 22:13:36.093980 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
9018 22:13:36.096921 == TX Byte 1 ==
9019 22:13:36.100990 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
9020 22:13:36.103963 DramC Write-DBI off
9021 22:13:36.104521
9022 22:13:36.104888 [DATLAT]
9023 22:13:36.105226 Freq=1600, CH1 RK1
9024 22:13:36.105557
9025 22:13:36.106701 DATLAT Default: 0xf
9026 22:13:36.110277 0, 0xFFFF, sum = 0
9027 22:13:36.110752 1, 0xFFFF, sum = 0
9028 22:13:36.113638 2, 0xFFFF, sum = 0
9029 22:13:36.114113 3, 0xFFFF, sum = 0
9030 22:13:36.116769 4, 0xFFFF, sum = 0
9031 22:13:36.117336 5, 0xFFFF, sum = 0
9032 22:13:36.119916 6, 0xFFFF, sum = 0
9033 22:13:36.120393 7, 0xFFFF, sum = 0
9034 22:13:36.123185 8, 0xFFFF, sum = 0
9035 22:13:36.123661 9, 0xFFFF, sum = 0
9036 22:13:36.126938 10, 0xFFFF, sum = 0
9037 22:13:36.127564 11, 0xFFFF, sum = 0
9038 22:13:36.130060 12, 0xFFFF, sum = 0
9039 22:13:36.130632 13, 0xFFFF, sum = 0
9040 22:13:36.134001 14, 0x0, sum = 1
9041 22:13:36.134564 15, 0x0, sum = 2
9042 22:13:36.136573 16, 0x0, sum = 3
9043 22:13:36.137044 17, 0x0, sum = 4
9044 22:13:36.140316 best_step = 15
9045 22:13:36.140874
9046 22:13:36.141244 ==
9047 22:13:36.142891 Dram Type= 6, Freq= 0, CH_1, rank 1
9048 22:13:36.146415 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9049 22:13:36.146980 ==
9050 22:13:36.149640 RX Vref Scan: 0
9051 22:13:36.150197
9052 22:13:36.150565 RX Vref 0 -> 0, step: 1
9053 22:13:36.150904
9054 22:13:36.153352 RX Delay 11 -> 252, step: 4
9055 22:13:36.159642 iDelay=203, Bit 0, Center 140 (87 ~ 194) 108
9056 22:13:36.163291 iDelay=203, Bit 1, Center 128 (75 ~ 182) 108
9057 22:13:36.166079 iDelay=203, Bit 2, Center 122 (67 ~ 178) 112
9058 22:13:36.170047 iDelay=203, Bit 3, Center 130 (79 ~ 182) 104
9059 22:13:36.172957 iDelay=203, Bit 4, Center 132 (75 ~ 190) 116
9060 22:13:36.179263 iDelay=203, Bit 5, Center 144 (91 ~ 198) 108
9061 22:13:36.182315 iDelay=203, Bit 6, Center 146 (91 ~ 202) 112
9062 22:13:36.185912 iDelay=203, Bit 7, Center 130 (79 ~ 182) 104
9063 22:13:36.189208 iDelay=203, Bit 8, Center 112 (55 ~ 170) 116
9064 22:13:36.192411 iDelay=203, Bit 9, Center 116 (63 ~ 170) 108
9065 22:13:36.199407 iDelay=203, Bit 10, Center 126 (71 ~ 182) 112
9066 22:13:36.202708 iDelay=203, Bit 11, Center 116 (63 ~ 170) 108
9067 22:13:36.205601 iDelay=203, Bit 12, Center 136 (83 ~ 190) 108
9068 22:13:36.209135 iDelay=203, Bit 13, Center 134 (79 ~ 190) 112
9069 22:13:36.215810 iDelay=203, Bit 14, Center 134 (79 ~ 190) 112
9070 22:13:36.219208 iDelay=203, Bit 15, Center 138 (83 ~ 194) 112
9071 22:13:36.219845 ==
9072 22:13:36.222246 Dram Type= 6, Freq= 0, CH_1, rank 1
9073 22:13:36.225553 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9074 22:13:36.226132 ==
9075 22:13:36.229064 DQS Delay:
9076 22:13:36.229629 DQS0 = 0, DQS1 = 0
9077 22:13:36.229996 DQM Delay:
9078 22:13:36.232069 DQM0 = 134, DQM1 = 126
9079 22:13:36.232533 DQ Delay:
9080 22:13:36.235432 DQ0 =140, DQ1 =128, DQ2 =122, DQ3 =130
9081 22:13:36.238958 DQ4 =132, DQ5 =144, DQ6 =146, DQ7 =130
9082 22:13:36.245537 DQ8 =112, DQ9 =116, DQ10 =126, DQ11 =116
9083 22:13:36.248618 DQ12 =136, DQ13 =134, DQ14 =134, DQ15 =138
9084 22:13:36.249086
9085 22:13:36.249468
9086 22:13:36.250054
9087 22:13:36.251576 [DramC_TX_OE_Calibration] TA2
9088 22:13:36.255417 Original DQ_B0 (3 6) =30, OEN = 27
9089 22:13:36.258297 Original DQ_B1 (3 6) =30, OEN = 27
9090 22:13:36.258865 24, 0x0, End_B0=24 End_B1=24
9091 22:13:36.261640 25, 0x0, End_B0=25 End_B1=25
9092 22:13:36.264816 26, 0x0, End_B0=26 End_B1=26
9093 22:13:36.268166 27, 0x0, End_B0=27 End_B1=27
9094 22:13:36.268884 28, 0x0, End_B0=28 End_B1=28
9095 22:13:36.271586 29, 0x0, End_B0=29 End_B1=29
9096 22:13:36.274898 30, 0x0, End_B0=30 End_B1=30
9097 22:13:36.278559 31, 0x4545, End_B0=30 End_B1=30
9098 22:13:36.281547 Byte0 end_step=30 best_step=27
9099 22:13:36.285041 Byte1 end_step=30 best_step=27
9100 22:13:36.285505 Byte0 TX OE(2T, 0.5T) = (3, 3)
9101 22:13:36.288069 Byte1 TX OE(2T, 0.5T) = (3, 3)
9102 22:13:36.288531
9103 22:13:36.288893
9104 22:13:36.298611 [DQSOSCAuto] RK1, (LSB)MR18= 0xe09, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 402 ps
9105 22:13:36.301791 CH1 RK1: MR19=303, MR18=E09
9106 22:13:36.305028 CH1_RK1: MR19=0x303, MR18=0xE09, DQSOSC=402, MR23=63, INC=22, DEC=15
9107 22:13:36.308416 [RxdqsGatingPostProcess] freq 1600
9108 22:13:36.314771 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9109 22:13:36.318060 best DQS0 dly(2T, 0.5T) = (1, 1)
9110 22:13:36.321112 best DQS1 dly(2T, 0.5T) = (1, 1)
9111 22:13:36.324572 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9112 22:13:36.327925 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9113 22:13:36.331147 best DQS0 dly(2T, 0.5T) = (1, 1)
9114 22:13:36.334434 best DQS1 dly(2T, 0.5T) = (1, 1)
9115 22:13:36.337655 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9116 22:13:36.338224 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9117 22:13:36.340739 Pre-setting of DQS Precalculation
9118 22:13:36.347330 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9119 22:13:36.354456 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9120 22:13:36.360815 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9121 22:13:36.361381
9122 22:13:36.361746
9123 22:13:36.363542 [Calibration Summary] 3200 Mbps
9124 22:13:36.366726 CH 0, Rank 0
9125 22:13:36.367222 SW Impedance : PASS
9126 22:13:36.370659 DUTY Scan : NO K
9127 22:13:36.374074 ZQ Calibration : PASS
9128 22:13:36.374625 Jitter Meter : NO K
9129 22:13:36.377283 CBT Training : PASS
9130 22:13:36.380665 Write leveling : PASS
9131 22:13:36.381220 RX DQS gating : PASS
9132 22:13:36.383572 RX DQ/DQS(RDDQC) : PASS
9133 22:13:36.386986 TX DQ/DQS : PASS
9134 22:13:36.387496 RX DATLAT : PASS
9135 22:13:36.390562 RX DQ/DQS(Engine): PASS
9136 22:13:36.391161 TX OE : PASS
9137 22:13:36.393256 All Pass.
9138 22:13:36.393716
9139 22:13:36.394106 CH 0, Rank 1
9140 22:13:36.397100 SW Impedance : PASS
9141 22:13:36.397561 DUTY Scan : NO K
9142 22:13:36.400044 ZQ Calibration : PASS
9143 22:13:36.403257 Jitter Meter : NO K
9144 22:13:36.403720 CBT Training : PASS
9145 22:13:36.407141 Write leveling : PASS
9146 22:13:36.409823 RX DQS gating : PASS
9147 22:13:36.410283 RX DQ/DQS(RDDQC) : PASS
9148 22:13:36.413585 TX DQ/DQS : PASS
9149 22:13:36.416717 RX DATLAT : PASS
9150 22:13:36.417392 RX DQ/DQS(Engine): PASS
9151 22:13:36.420010 TX OE : PASS
9152 22:13:36.420472 All Pass.
9153 22:13:36.420840
9154 22:13:36.422829 CH 1, Rank 0
9155 22:13:36.423340 SW Impedance : PASS
9156 22:13:36.426898 DUTY Scan : NO K
9157 22:13:36.429922 ZQ Calibration : PASS
9158 22:13:36.430504 Jitter Meter : NO K
9159 22:13:36.432928 CBT Training : PASS
9160 22:13:36.436447 Write leveling : PASS
9161 22:13:36.437023 RX DQS gating : PASS
9162 22:13:36.440212 RX DQ/DQS(RDDQC) : PASS
9163 22:13:36.443322 TX DQ/DQS : PASS
9164 22:13:36.443951 RX DATLAT : PASS
9165 22:13:36.446616 RX DQ/DQS(Engine): PASS
9166 22:13:36.447246 TX OE : PASS
9167 22:13:36.449800 All Pass.
9168 22:13:36.450366
9169 22:13:36.450757 CH 1, Rank 1
9170 22:13:36.452816 SW Impedance : PASS
9171 22:13:36.456643 DUTY Scan : NO K
9172 22:13:36.457209 ZQ Calibration : PASS
9173 22:13:36.459724 Jitter Meter : NO K
9174 22:13:36.460187 CBT Training : PASS
9175 22:13:36.463236 Write leveling : PASS
9176 22:13:36.466424 RX DQS gating : PASS
9177 22:13:36.466988 RX DQ/DQS(RDDQC) : PASS
9178 22:13:36.469605 TX DQ/DQS : PASS
9179 22:13:36.473128 RX DATLAT : PASS
9180 22:13:36.473708 RX DQ/DQS(Engine): PASS
9181 22:13:36.476990 TX OE : PASS
9182 22:13:36.477554 All Pass.
9183 22:13:36.477926
9184 22:13:36.479825 DramC Write-DBI on
9185 22:13:36.482643 PER_BANK_REFRESH: Hybrid Mode
9186 22:13:36.483148 TX_TRACKING: ON
9187 22:13:36.493009 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9188 22:13:36.499407 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9189 22:13:36.506449 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9190 22:13:36.509618 [FAST_K] Save calibration result to emmc
9191 22:13:36.513030 sync common calibartion params.
9192 22:13:36.516065 sync cbt_mode0:1, 1:1
9193 22:13:36.519668 dram_init: ddr_geometry: 2
9194 22:13:36.520229 dram_init: ddr_geometry: 2
9195 22:13:36.522665 dram_init: ddr_geometry: 2
9196 22:13:36.525921 0:dram_rank_size:100000000
9197 22:13:36.529588 1:dram_rank_size:100000000
9198 22:13:36.532479 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9199 22:13:36.535933 DFS_SHUFFLE_HW_MODE: ON
9200 22:13:36.538817 dramc_set_vcore_voltage set vcore to 725000
9201 22:13:36.542491 Read voltage for 1600, 0
9202 22:13:36.543091 Vio18 = 0
9203 22:13:36.545815 Vcore = 725000
9204 22:13:36.546410 Vdram = 0
9205 22:13:36.546795 Vddq = 0
9206 22:13:36.547195 Vmddr = 0
9207 22:13:36.548841 switch to 3200 Mbps bootup
9208 22:13:36.552506 [DramcRunTimeConfig]
9209 22:13:36.553071 PHYPLL
9210 22:13:36.556205 DPM_CONTROL_AFTERK: ON
9211 22:13:36.556766 PER_BANK_REFRESH: ON
9212 22:13:36.559132 REFRESH_OVERHEAD_REDUCTION: ON
9213 22:13:36.562114 CMD_PICG_NEW_MODE: OFF
9214 22:13:36.562575 XRTWTW_NEW_MODE: ON
9215 22:13:36.565701 XRTRTR_NEW_MODE: ON
9216 22:13:36.566162 TX_TRACKING: ON
9217 22:13:36.568859 RDSEL_TRACKING: OFF
9218 22:13:36.569424 DQS Precalculation for DVFS: ON
9219 22:13:36.572261 RX_TRACKING: OFF
9220 22:13:36.572829 HW_GATING DBG: ON
9221 22:13:36.575567 ZQCS_ENABLE_LP4: ON
9222 22:13:36.578793 RX_PICG_NEW_MODE: ON
9223 22:13:36.579397 TX_PICG_NEW_MODE: ON
9224 22:13:36.581865 ENABLE_RX_DCM_DPHY: ON
9225 22:13:36.585125 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9226 22:13:36.585588 DUMMY_READ_FOR_TRACKING: OFF
9227 22:13:36.588546 !!! SPM_CONTROL_AFTERK: OFF
9228 22:13:36.592060 !!! SPM could not control APHY
9229 22:13:36.595410 IMPEDANCE_TRACKING: ON
9230 22:13:36.595872 TEMP_SENSOR: ON
9231 22:13:36.598492 HW_SAVE_FOR_SR: OFF
9232 22:13:36.602113 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9233 22:13:36.604840 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9234 22:13:36.605304 Read ODT Tracking: ON
9235 22:13:36.608594 Refresh Rate DeBounce: ON
9236 22:13:36.611414 DFS_NO_QUEUE_FLUSH: ON
9237 22:13:36.615565 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9238 22:13:36.616317 ENABLE_DFS_RUNTIME_MRW: OFF
9239 22:13:36.617954 DDR_RESERVE_NEW_MODE: ON
9240 22:13:36.621351 MR_CBT_SWITCH_FREQ: ON
9241 22:13:36.621815 =========================
9242 22:13:36.642422 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9243 22:13:36.645551 dram_init: ddr_geometry: 2
9244 22:13:36.663163 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9245 22:13:36.666421 dram_init: dram init end (result: 0)
9246 22:13:36.672958 DRAM-K: Full calibration passed in 24572 msecs
9247 22:13:36.676790 MRC: failed to locate region type 0.
9248 22:13:36.677352 DRAM rank0 size:0x100000000,
9249 22:13:36.680153 DRAM rank1 size=0x100000000
9250 22:13:36.689998 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9251 22:13:36.696247 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9252 22:13:36.702797 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9253 22:13:36.712574 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9254 22:13:36.713092 DRAM rank0 size:0x100000000,
9255 22:13:36.716257 DRAM rank1 size=0x100000000
9256 22:13:36.716726 CBMEM:
9257 22:13:36.719348 IMD: root @ 0xfffff000 254 entries.
9258 22:13:36.722487 IMD: root @ 0xffffec00 62 entries.
9259 22:13:36.726590 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9260 22:13:36.732959 WARNING: RO_VPD is uninitialized or empty.
9261 22:13:36.736129 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9262 22:13:36.743051 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9263 22:13:36.756103 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9264 22:13:36.767646 BS: romstage times (exec / console): total (unknown) / 24074 ms
9265 22:13:36.768238
9266 22:13:36.768611
9267 22:13:36.777359 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9268 22:13:36.781102 ARM64: Exception handlers installed.
9269 22:13:36.783630 ARM64: Testing exception
9270 22:13:36.787298 ARM64: Done test exception
9271 22:13:36.787876 Enumerating buses...
9272 22:13:36.790433 Show all devs... Before device enumeration.
9273 22:13:36.794014 Root Device: enabled 1
9274 22:13:36.796962 CPU_CLUSTER: 0: enabled 1
9275 22:13:36.797433 CPU: 00: enabled 1
9276 22:13:36.800749 Compare with tree...
9277 22:13:36.801312 Root Device: enabled 1
9278 22:13:36.804267 CPU_CLUSTER: 0: enabled 1
9279 22:13:36.807106 CPU: 00: enabled 1
9280 22:13:36.807574 Root Device scanning...
9281 22:13:36.810370 scan_static_bus for Root Device
9282 22:13:36.814227 CPU_CLUSTER: 0 enabled
9283 22:13:36.817264 scan_static_bus for Root Device done
9284 22:13:36.820135 scan_bus: bus Root Device finished in 8 msecs
9285 22:13:36.820699 done
9286 22:13:36.826909 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9287 22:13:36.830042 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9288 22:13:36.836853 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9289 22:13:36.843778 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9290 22:13:36.844445 Allocating resources...
9291 22:13:36.846943 Reading resources...
9292 22:13:36.849775 Root Device read_resources bus 0 link: 0
9293 22:13:36.853036 DRAM rank0 size:0x100000000,
9294 22:13:36.853619 DRAM rank1 size=0x100000000
9295 22:13:36.859652 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9296 22:13:36.860219 CPU: 00 missing read_resources
9297 22:13:36.866203 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9298 22:13:36.869601 Root Device read_resources bus 0 link: 0 done
9299 22:13:36.873098 Done reading resources.
9300 22:13:36.876116 Show resources in subtree (Root Device)...After reading.
9301 22:13:36.879596 Root Device child on link 0 CPU_CLUSTER: 0
9302 22:13:36.883159 CPU_CLUSTER: 0 child on link 0 CPU: 00
9303 22:13:36.892947 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9304 22:13:36.893514 CPU: 00
9305 22:13:36.896203 Root Device assign_resources, bus 0 link: 0
9306 22:13:36.899477 CPU_CLUSTER: 0 missing set_resources
9307 22:13:36.906346 Root Device assign_resources, bus 0 link: 0 done
9308 22:13:36.906914 Done setting resources.
9309 22:13:36.912272 Show resources in subtree (Root Device)...After assigning values.
9310 22:13:36.916011 Root Device child on link 0 CPU_CLUSTER: 0
9311 22:13:36.919903 CPU_CLUSTER: 0 child on link 0 CPU: 00
9312 22:13:36.929123 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9313 22:13:36.929691 CPU: 00
9314 22:13:36.932722 Done allocating resources.
9315 22:13:36.939032 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9316 22:13:36.939541 Enabling resources...
9317 22:13:36.942378 done.
9318 22:13:36.945405 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9319 22:13:36.948841 Initializing devices...
9320 22:13:36.949307 Root Device init
9321 22:13:36.951841 init hardware done!
9322 22:13:36.952306 0x00000018: ctrlr->caps
9323 22:13:36.955630 52.000 MHz: ctrlr->f_max
9324 22:13:36.958854 0.400 MHz: ctrlr->f_min
9325 22:13:36.959483 0x40ff8080: ctrlr->voltages
9326 22:13:36.962391 sclk: 390625
9327 22:13:36.962950 Bus Width = 1
9328 22:13:36.965200 sclk: 390625
9329 22:13:36.965769 Bus Width = 1
9330 22:13:36.968388 Early init status = 3
9331 22:13:36.971638 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9332 22:13:36.976019 in-header: 03 fc 00 00 01 00 00 00
9333 22:13:36.979225 in-data: 00
9334 22:13:36.982469 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9335 22:13:36.987380 in-header: 03 fd 00 00 00 00 00 00
9336 22:13:36.991215 in-data:
9337 22:13:36.994724 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9338 22:13:36.998283 in-header: 03 fc 00 00 01 00 00 00
9339 22:13:37.001871 in-data: 00
9340 22:13:37.005100 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9341 22:13:37.012765 in-header: 03 fd 00 00 00 00 00 00
9342 22:13:37.016163 in-data:
9343 22:13:37.020241 [SSUSB] Setting up USB HOST controller...
9344 22:13:37.022754 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9345 22:13:37.026314 [SSUSB] phy power-on done.
9346 22:13:37.029787 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9347 22:13:37.035654 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9348 22:13:37.039434 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9349 22:13:37.045747 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9350 22:13:37.052208 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9351 22:13:37.058805 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9352 22:13:37.065473 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9353 22:13:37.072509 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9354 22:13:37.075530 SPM: binary array size = 0x9dc
9355 22:13:37.078702 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9356 22:13:37.085193 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9357 22:13:37.091835 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9358 22:13:37.098244 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9359 22:13:37.101795 configure_display: Starting display init
9360 22:13:37.136027 anx7625_power_on_init: Init interface.
9361 22:13:37.139637 anx7625_disable_pd_protocol: Disabled PD feature.
9362 22:13:37.142502 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9363 22:13:37.170293 anx7625_start_dp_work: Secure OCM version=00
9364 22:13:37.173400 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9365 22:13:37.188560 sp_tx_get_edid_block: EDID Block = 1
9366 22:13:37.291436 Extracted contents:
9367 22:13:37.294826 header: 00 ff ff ff ff ff ff 00
9368 22:13:37.297587 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9369 22:13:37.301357 version: 01 04
9370 22:13:37.304462 basic params: 95 1f 11 78 0a
9371 22:13:37.307659 chroma info: 76 90 94 55 54 90 27 21 50 54
9372 22:13:37.311253 established: 00 00 00
9373 22:13:37.317772 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9374 22:13:37.320708 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9375 22:13:37.327836 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9376 22:13:37.334270 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9377 22:13:37.340788 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9378 22:13:37.344126 extensions: 00
9379 22:13:37.344687 checksum: fb
9380 22:13:37.345057
9381 22:13:37.347664 Manufacturer: IVO Model 57d Serial Number 0
9382 22:13:37.350872 Made week 0 of 2020
9383 22:13:37.351472 EDID version: 1.4
9384 22:13:37.354221 Digital display
9385 22:13:37.357316 6 bits per primary color channel
9386 22:13:37.357814 DisplayPort interface
9387 22:13:37.360478 Maximum image size: 31 cm x 17 cm
9388 22:13:37.363569 Gamma: 220%
9389 22:13:37.364034 Check DPMS levels
9390 22:13:37.367169 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9391 22:13:37.374132 First detailed timing is preferred timing
9392 22:13:37.374696 Established timings supported:
9393 22:13:37.377088 Standard timings supported:
9394 22:13:37.380824 Detailed timings
9395 22:13:37.383713 Hex of detail: 383680a07038204018303c0035ae10000019
9396 22:13:37.390064 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9397 22:13:37.393559 0780 0798 07c8 0820 hborder 0
9398 22:13:37.397069 0438 043b 0447 0458 vborder 0
9399 22:13:37.400106 -hsync -vsync
9400 22:13:37.400677 Did detailed timing
9401 22:13:37.406786 Hex of detail: 000000000000000000000000000000000000
9402 22:13:37.410580 Manufacturer-specified data, tag 0
9403 22:13:37.413472 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9404 22:13:37.416299 ASCII string: InfoVision
9405 22:13:37.419822 Hex of detail: 000000fe00523134304e574635205248200a
9406 22:13:37.423260 ASCII string: R140NWF5 RH
9407 22:13:37.423823 Checksum
9408 22:13:37.426515 Checksum: 0xfb (valid)
9409 22:13:37.429853 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9410 22:13:37.433181 DSI data_rate: 832800000 bps
9411 22:13:37.439592 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9412 22:13:37.443237 anx7625_parse_edid: pixelclock(138800).
9413 22:13:37.446340 hactive(1920), hsync(48), hfp(24), hbp(88)
9414 22:13:37.449579 vactive(1080), vsync(12), vfp(3), vbp(17)
9415 22:13:37.453395 anx7625_dsi_config: config dsi.
9416 22:13:37.460291 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9417 22:13:37.473192 anx7625_dsi_config: success to config DSI
9418 22:13:37.476202 anx7625_dp_start: MIPI phy setup OK.
9419 22:13:37.479784 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9420 22:13:37.482768 mtk_ddp_mode_set invalid vrefresh 60
9421 22:13:37.486687 main_disp_path_setup
9422 22:13:37.487188 ovl_layer_smi_id_en
9423 22:13:37.489873 ovl_layer_smi_id_en
9424 22:13:37.490436 ccorr_config
9425 22:13:37.490800 aal_config
9426 22:13:37.493110 gamma_config
9427 22:13:37.493664 postmask_config
9428 22:13:37.496304 dither_config
9429 22:13:37.499730 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9430 22:13:37.506007 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9431 22:13:37.509568 Root Device init finished in 556 msecs
9432 22:13:37.512566 CPU_CLUSTER: 0 init
9433 22:13:37.519298 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9434 22:13:37.526361 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9435 22:13:37.526940 APU_MBOX 0x190000b0 = 0x10001
9436 22:13:37.529058 APU_MBOX 0x190001b0 = 0x10001
9437 22:13:37.532751 APU_MBOX 0x190005b0 = 0x10001
9438 22:13:37.535436 APU_MBOX 0x190006b0 = 0x10001
9439 22:13:37.542679 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9440 22:13:37.552428 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9441 22:13:37.564385 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9442 22:13:37.571523 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9443 22:13:37.582778 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9444 22:13:37.592332 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9445 22:13:37.595368 CPU_CLUSTER: 0 init finished in 81 msecs
9446 22:13:37.598670 Devices initialized
9447 22:13:37.601588 Show all devs... After init.
9448 22:13:37.602046 Root Device: enabled 1
9449 22:13:37.605350 CPU_CLUSTER: 0: enabled 1
9450 22:13:37.608313 CPU: 00: enabled 1
9451 22:13:37.611597 BS: BS_DEV_INIT run times (exec / console): 215 / 447 ms
9452 22:13:37.614821 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9453 22:13:37.617873 ELOG: NV offset 0x57f000 size 0x1000
9454 22:13:37.625273 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9455 22:13:37.631464 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9456 22:13:37.635161 ELOG: Event(17) added with size 13 at 2023-06-04 22:13:49 UTC
9457 22:13:37.641077 out: cmd=0x121: 03 db 21 01 00 00 00 00
9458 22:13:37.645037 in-header: 03 f2 00 00 2c 00 00 00
9459 22:13:37.654252 in-data: 6d 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9460 22:13:37.661330 ELOG: Event(A1) added with size 10 at 2023-06-04 22:13:49 UTC
9461 22:13:37.667682 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9462 22:13:37.674510 ELOG: Event(A0) added with size 9 at 2023-06-04 22:13:49 UTC
9463 22:13:37.677697 elog_add_boot_reason: Logged dev mode boot
9464 22:13:37.684217 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9465 22:13:37.684783 Finalize devices...
9466 22:13:37.687876 Devices finalized
9467 22:13:37.691275 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9468 22:13:37.694548 Writing coreboot table at 0xffe64000
9469 22:13:37.697339 0. 000000000010a000-0000000000113fff: RAMSTAGE
9470 22:13:37.700891 1. 0000000040000000-00000000400fffff: RAM
9471 22:13:37.708170 2. 0000000040100000-000000004032afff: RAMSTAGE
9472 22:13:37.710881 3. 000000004032b000-00000000545fffff: RAM
9473 22:13:37.714278 4. 0000000054600000-000000005465ffff: BL31
9474 22:13:37.717596 5. 0000000054660000-00000000ffe63fff: RAM
9475 22:13:37.724586 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9476 22:13:37.727521 7. 0000000100000000-000000023fffffff: RAM
9477 22:13:37.730782 Passing 5 GPIOs to payload:
9478 22:13:37.733973 NAME | PORT | POLARITY | VALUE
9479 22:13:37.740476 EC in RW | 0x000000aa | low | undefined
9480 22:13:37.743982 EC interrupt | 0x00000005 | low | undefined
9481 22:13:37.747329 TPM interrupt | 0x000000ab | high | undefined
9482 22:13:37.754584 SD card detect | 0x00000011 | high | undefined
9483 22:13:37.757312 speaker enable | 0x00000093 | high | undefined
9484 22:13:37.760987 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9485 22:13:37.764012 in-header: 03 f9 00 00 02 00 00 00
9486 22:13:37.767296 in-data: 02 00
9487 22:13:37.770679 ADC[4]: Raw value=901922 ID=7
9488 22:13:37.771291 ADC[3]: Raw value=213652 ID=1
9489 22:13:37.774743 RAM Code: 0x71
9490 22:13:37.777029 ADC[6]: Raw value=75036 ID=0
9491 22:13:37.777498 ADC[5]: Raw value=213652 ID=1
9492 22:13:37.780543 SKU Code: 0x1
9493 22:13:37.787610 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum a129
9494 22:13:37.788084 coreboot table: 964 bytes.
9495 22:13:37.790379 IMD ROOT 0. 0xfffff000 0x00001000
9496 22:13:37.793788 IMD SMALL 1. 0xffffe000 0x00001000
9497 22:13:37.797127 RO MCACHE 2. 0xffffc000 0x00001104
9498 22:13:37.800146 CONSOLE 3. 0xfff7c000 0x00080000
9499 22:13:37.804001 FMAP 4. 0xfff7b000 0x00000452
9500 22:13:37.807142 TIME STAMP 5. 0xfff7a000 0x00000910
9501 22:13:37.810369 VBOOT WORK 6. 0xfff66000 0x00014000
9502 22:13:37.813706 RAMOOPS 7. 0xffe66000 0x00100000
9503 22:13:37.817015 COREBOOT 8. 0xffe64000 0x00002000
9504 22:13:37.820003 IMD small region:
9505 22:13:37.823636 IMD ROOT 0. 0xffffec00 0x00000400
9506 22:13:37.826736 VPD 1. 0xffffeba0 0x0000004c
9507 22:13:37.830379 MMC STATUS 2. 0xffffeb80 0x00000004
9508 22:13:37.833314 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9509 22:13:37.836750 Probing TPM: done!
9510 22:13:37.839988 Connected to device vid:did:rid of 1ae0:0028:00
9511 22:13:37.850760 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9512 22:13:37.854897 Initialized TPM device CR50 revision 0
9513 22:13:37.857727 Checking cr50 for pending updates
9514 22:13:37.861716 Reading cr50 TPM mode
9515 22:13:37.870364 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9516 22:13:37.877275 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9517 22:13:37.916631 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9518 22:13:37.920347 Checking segment from ROM address 0x40100000
9519 22:13:37.923874 Checking segment from ROM address 0x4010001c
9520 22:13:37.930130 Loading segment from ROM address 0x40100000
9521 22:13:37.930677 code (compression=0)
9522 22:13:37.940212 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9523 22:13:37.946932 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9524 22:13:37.947521 it's not compressed!
9525 22:13:37.953976 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9526 22:13:37.960185 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9527 22:13:37.977419 Loading segment from ROM address 0x4010001c
9528 22:13:37.977981 Entry Point 0x80000000
9529 22:13:37.980947 Loaded segments
9530 22:13:37.984135 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9531 22:13:37.990854 Jumping to boot code at 0x80000000(0xffe64000)
9532 22:13:37.997682 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9533 22:13:38.003820 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9534 22:13:38.011977 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9535 22:13:38.015054 Checking segment from ROM address 0x40100000
9536 22:13:38.018405 Checking segment from ROM address 0x4010001c
9537 22:13:38.025334 Loading segment from ROM address 0x40100000
9538 22:13:38.025881 code (compression=1)
9539 22:13:38.031660 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9540 22:13:38.041740 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9541 22:13:38.042305 using LZMA
9542 22:13:38.050343 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9543 22:13:38.056808 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9544 22:13:38.060498 Loading segment from ROM address 0x4010001c
9545 22:13:38.060962 Entry Point 0x54601000
9546 22:13:38.063272 Loaded segments
9547 22:13:38.066908 NOTICE: MT8192 bl31_setup
9548 22:13:38.074109 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9549 22:13:38.076786 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9550 22:13:38.080446 WARNING: region 0:
9551 22:13:38.084193 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9552 22:13:38.084659 WARNING: region 1:
9553 22:13:38.090562 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9554 22:13:38.093999 WARNING: region 2:
9555 22:13:38.096931 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9556 22:13:38.099864 WARNING: region 3:
9557 22:13:38.103734 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9558 22:13:38.107332 WARNING: region 4:
9559 22:13:38.114050 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9560 22:13:38.114599 WARNING: region 5:
9561 22:13:38.116904 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9562 22:13:38.120540 WARNING: region 6:
9563 22:13:38.123825 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9564 22:13:38.126809 WARNING: region 7:
9565 22:13:38.130054 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9566 22:13:38.137242 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9567 22:13:38.139830 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9568 22:13:38.143193 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9569 22:13:38.150261 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9570 22:13:38.153551 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9571 22:13:38.156953 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9572 22:13:38.163174 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9573 22:13:38.166692 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9574 22:13:38.173611 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9575 22:13:38.176697 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9576 22:13:38.180509 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9577 22:13:38.186835 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9578 22:13:38.190107 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9579 22:13:38.193564 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9580 22:13:38.200195 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9581 22:13:38.203561 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9582 22:13:38.210203 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9583 22:13:38.213636 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9584 22:13:38.216435 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9585 22:13:38.223410 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9586 22:13:38.226486 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9587 22:13:38.233210 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9588 22:13:38.236257 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9589 22:13:38.239987 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9590 22:13:38.246049 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9591 22:13:38.249555 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9592 22:13:38.255851 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9593 22:13:38.259434 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9594 22:13:38.262534 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9595 22:13:38.269525 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9596 22:13:38.272631 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9597 22:13:38.279313 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9598 22:13:38.283000 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9599 22:13:38.285828 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9600 22:13:38.289116 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9601 22:13:38.296318 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9602 22:13:38.299372 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9603 22:13:38.302696 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9604 22:13:38.306264 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9605 22:13:38.312456 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9606 22:13:38.315556 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9607 22:13:38.319195 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9608 22:13:38.322707 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9609 22:13:38.329161 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9610 22:13:38.332414 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9611 22:13:38.335631 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9612 22:13:38.342459 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9613 22:13:38.346249 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9614 22:13:38.348942 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9615 22:13:38.355998 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9616 22:13:38.359155 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9617 22:13:38.362183 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9618 22:13:38.368989 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9619 22:13:38.372263 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9620 22:13:38.379186 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9621 22:13:38.381911 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9622 22:13:38.388765 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9623 22:13:38.392152 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9624 22:13:38.398929 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9625 22:13:38.402286 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9626 22:13:38.405399 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9627 22:13:38.412371 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9628 22:13:38.415385 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9629 22:13:38.422408 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9630 22:13:38.425143 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9631 22:13:38.431844 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9632 22:13:38.435293 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9633 22:13:38.438478 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9634 22:13:38.445034 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9635 22:13:38.448263 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9636 22:13:38.455115 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9637 22:13:38.458488 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9638 22:13:38.464876 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9639 22:13:38.468020 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9640 22:13:38.475293 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9641 22:13:38.478844 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9642 22:13:38.481550 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9643 22:13:38.488204 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9644 22:13:38.492255 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9645 22:13:38.498544 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9646 22:13:38.501987 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9647 22:13:38.508949 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9648 22:13:38.511917 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9649 22:13:38.514801 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9650 22:13:38.521356 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9651 22:13:38.525116 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9652 22:13:38.531237 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9653 22:13:38.534457 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9654 22:13:38.541566 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9655 22:13:38.545411 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9656 22:13:38.551015 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9657 22:13:38.554688 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9658 22:13:38.557885 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9659 22:13:38.565141 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9660 22:13:38.567614 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9661 22:13:38.574791 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9662 22:13:38.577646 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9663 22:13:38.581157 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9664 22:13:38.587842 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9665 22:13:38.591376 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9666 22:13:38.594591 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9667 22:13:38.597945 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9668 22:13:38.604444 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9669 22:13:38.607628 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9670 22:13:38.614658 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9671 22:13:38.617471 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9672 22:13:38.621194 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9673 22:13:38.627696 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9674 22:13:38.630818 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9675 22:13:38.637551 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9676 22:13:38.640887 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9677 22:13:38.643960 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9678 22:13:38.651263 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9679 22:13:38.654002 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9680 22:13:38.660638 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9681 22:13:38.663746 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9682 22:13:38.667279 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9683 22:13:38.673923 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9684 22:13:38.677470 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9685 22:13:38.680249 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9686 22:13:38.687320 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9687 22:13:38.690280 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9688 22:13:38.693813 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9689 22:13:38.697500 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9690 22:13:38.703547 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9691 22:13:38.707603 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9692 22:13:38.710479 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9693 22:13:38.717057 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9694 22:13:38.720295 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9695 22:13:38.727278 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9696 22:13:38.730335 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9697 22:13:38.733875 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9698 22:13:38.739993 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9699 22:13:38.743513 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9700 22:13:38.750194 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9701 22:13:38.753242 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9702 22:13:38.757138 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9703 22:13:38.763585 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9704 22:13:38.766446 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9705 22:13:38.773115 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9706 22:13:38.776541 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9707 22:13:38.779824 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9708 22:13:38.786314 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9709 22:13:38.789605 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9710 22:13:38.796312 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9711 22:13:38.799873 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9712 22:13:38.804226 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9713 22:13:38.809827 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9714 22:13:38.812954 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9715 22:13:38.819801 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9716 22:13:38.823399 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9717 22:13:38.826445 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9718 22:13:38.832980 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9719 22:13:38.836507 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9720 22:13:38.842838 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9721 22:13:38.845866 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9722 22:13:38.849286 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9723 22:13:38.856254 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9724 22:13:38.859133 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9725 22:13:38.862347 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9726 22:13:38.869612 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9727 22:13:38.872449 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9728 22:13:38.879574 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9729 22:13:38.882552 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9730 22:13:38.885495 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9731 22:13:38.892333 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9732 22:13:38.895296 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9733 22:13:38.902315 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9734 22:13:38.905643 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9735 22:13:38.908959 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9736 22:13:38.915570 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9737 22:13:38.918831 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9738 22:13:38.925715 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9739 22:13:38.929160 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9740 22:13:38.932043 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9741 22:13:38.938947 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9742 22:13:38.942060 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9743 22:13:38.948619 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9744 22:13:38.951656 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9745 22:13:38.954928 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9746 22:13:38.961716 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9747 22:13:38.964792 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9748 22:13:38.971639 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9749 22:13:38.974565 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9750 22:13:38.978341 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9751 22:13:38.984994 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9752 22:13:38.987772 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9753 22:13:38.994500 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9754 22:13:38.997936 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9755 22:13:39.004328 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9756 22:13:39.007939 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9757 22:13:39.011159 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9758 22:13:39.017638 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9759 22:13:39.020816 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9760 22:13:39.027737 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9761 22:13:39.031342 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9762 22:13:39.034588 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9763 22:13:39.040834 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9764 22:13:39.043852 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9765 22:13:39.050647 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9766 22:13:39.054145 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9767 22:13:39.060623 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9768 22:13:39.063772 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9769 22:13:39.066831 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9770 22:13:39.074093 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9771 22:13:39.077026 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9772 22:13:39.083562 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9773 22:13:39.087138 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9774 22:13:39.093285 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9775 22:13:39.096600 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9776 22:13:39.100067 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9777 22:13:39.107146 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9778 22:13:39.110268 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9779 22:13:39.116707 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9780 22:13:39.120179 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9781 22:13:39.126660 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9782 22:13:39.130498 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9783 22:13:39.132927 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9784 22:13:39.140083 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9785 22:13:39.143195 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9786 22:13:39.149552 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9787 22:13:39.152946 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9788 22:13:39.159514 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9789 22:13:39.162739 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9790 22:13:39.166310 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9791 22:13:39.172571 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9792 22:13:39.176180 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9793 22:13:39.182588 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9794 22:13:39.185795 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9795 22:13:39.189163 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9796 22:13:39.196269 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9797 22:13:39.199228 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9798 22:13:39.202949 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9799 22:13:39.205696 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9800 22:13:39.212633 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9801 22:13:39.215619 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9802 22:13:39.218873 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9803 22:13:39.225747 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9804 22:13:39.229257 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9805 22:13:39.232764 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9806 22:13:39.238954 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9807 22:13:39.242302 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9808 22:13:39.248706 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9809 22:13:39.251921 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9810 22:13:39.255505 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9811 22:13:39.261910 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9812 22:13:39.265449 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9813 22:13:39.271775 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9814 22:13:39.275512 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9815 22:13:39.278347 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9816 22:13:39.284946 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9817 22:13:39.288285 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9818 22:13:39.291728 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9819 22:13:39.298167 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9820 22:13:39.301409 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9821 22:13:39.307911 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9822 22:13:39.311326 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9823 22:13:39.314966 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9824 22:13:39.321229 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9825 22:13:39.325059 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9826 22:13:39.327903 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9827 22:13:39.334763 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9828 22:13:39.338012 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9829 22:13:39.341018 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9830 22:13:39.348300 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9831 22:13:39.351157 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9832 22:13:39.357754 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9833 22:13:39.360784 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9834 22:13:39.364934 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9835 22:13:39.367468 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9836 22:13:39.374285 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9837 22:13:39.377821 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9838 22:13:39.380819 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9839 22:13:39.384378 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9840 22:13:39.390553 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9841 22:13:39.393937 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9842 22:13:39.397659 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9843 22:13:39.400556 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9844 22:13:39.407291 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9845 22:13:39.410883 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9846 22:13:39.413927 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9847 22:13:39.420953 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9848 22:13:39.423623 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9849 22:13:39.426943 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9850 22:13:39.433464 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9851 22:13:39.437000 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9852 22:13:39.443346 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9853 22:13:39.447004 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9854 22:13:39.453926 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9855 22:13:39.456553 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9856 22:13:39.460343 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9857 22:13:39.466970 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9858 22:13:39.470168 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9859 22:13:39.476478 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9860 22:13:39.480533 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9861 22:13:39.483664 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9862 22:13:39.489911 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9863 22:13:39.493420 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9864 22:13:39.499814 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9865 22:13:39.503394 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9866 22:13:39.506700 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9867 22:13:39.513294 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9868 22:13:39.516248 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9869 22:13:39.522885 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9870 22:13:39.526234 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9871 22:13:39.529568 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9872 22:13:39.536392 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9873 22:13:39.539140 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9874 22:13:39.545823 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9875 22:13:39.548949 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9876 22:13:39.555853 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9877 22:13:39.559215 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9878 22:13:39.566057 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9879 22:13:39.569431 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9880 22:13:39.572596 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9881 22:13:39.578877 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9882 22:13:39.582586 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9883 22:13:39.588989 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9884 22:13:39.592370 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9885 22:13:39.595385 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9886 22:13:39.602269 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9887 22:13:39.605654 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9888 22:13:39.611828 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9889 22:13:39.615452 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9890 22:13:39.618746 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9891 22:13:39.625082 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9892 22:13:39.628458 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9893 22:13:39.635297 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9894 22:13:39.638193 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9895 22:13:39.641904 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9896 22:13:39.648326 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9897 22:13:39.651483 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9898 22:13:39.658542 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9899 22:13:39.662052 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9900 22:13:39.667900 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9901 22:13:39.671393 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9902 22:13:39.678137 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9903 22:13:39.681168 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9904 22:13:39.684638 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9905 22:13:39.691235 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9906 22:13:39.694041 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9907 22:13:39.700731 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9908 22:13:39.704577 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9909 22:13:39.711217 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9910 22:13:39.714284 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9911 22:13:39.717389 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9912 22:13:39.724122 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9913 22:13:39.727498 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9914 22:13:39.734134 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9915 22:13:39.737328 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9916 22:13:39.740421 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9917 22:13:39.747032 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9918 22:13:39.750218 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9919 22:13:39.757339 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9920 22:13:39.760443 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9921 22:13:39.763445 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9922 22:13:39.770552 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9923 22:13:39.773117 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9924 22:13:39.780321 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9925 22:13:39.783786 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9926 22:13:39.789545 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9927 22:13:39.793430 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9928 22:13:39.799994 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9929 22:13:39.803164 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9930 22:13:39.806875 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9931 22:13:39.813000 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9932 22:13:39.816370 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9933 22:13:39.822965 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9934 22:13:39.826374 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9935 22:13:39.833287 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9936 22:13:39.836135 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9937 22:13:39.842780 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9938 22:13:39.845971 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9939 22:13:39.852555 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9940 22:13:39.855595 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9941 22:13:39.859635 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9942 22:13:39.865808 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9943 22:13:39.869438 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9944 22:13:39.875273 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9945 22:13:39.878877 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9946 22:13:39.885456 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9947 22:13:39.888782 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9948 22:13:39.895241 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9949 22:13:39.898804 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9950 22:13:39.902210 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9951 22:13:39.908425 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9952 22:13:39.912368 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9953 22:13:39.918314 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9954 22:13:39.921632 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9955 22:13:39.928530 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9956 22:13:39.931790 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9957 22:13:39.938649 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9958 22:13:39.941210 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9959 22:13:39.945189 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9960 22:13:39.951269 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9961 22:13:39.954688 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9962 22:13:39.961243 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9963 22:13:39.964538 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9964 22:13:39.971223 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9965 22:13:39.974130 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9966 22:13:39.981157 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9967 22:13:39.984581 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9968 22:13:39.987702 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9969 22:13:39.994522 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9970 22:13:39.997628 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9971 22:13:40.004139 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9972 22:13:40.007495 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9973 22:13:40.014548 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9974 22:13:40.017171 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9975 22:13:40.024065 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9976 22:13:40.027415 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9977 22:13:40.033975 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9978 22:13:40.036883 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9979 22:13:40.040469 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9980 22:13:40.047359 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9981 22:13:40.050278 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9982 22:13:40.057061 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9983 22:13:40.060175 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9984 22:13:40.066836 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9985 22:13:40.070315 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9986 22:13:40.076680 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9987 22:13:40.080720 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9988 22:13:40.086859 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9989 22:13:40.090276 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9990 22:13:40.096652 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9991 22:13:40.099988 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9992 22:13:40.106720 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9993 22:13:40.113077 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9994 22:13:40.116454 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9995 22:13:40.122983 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9996 22:13:40.126641 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9997 22:13:40.133362 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9998 22:13:40.136160 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9999 22:13:40.142681 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
10000 22:13:40.146326 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
10001 22:13:40.146888 INFO: [APUAPC] vio 0
10002 22:13:40.153515 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
10003 22:13:40.156678 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
10004 22:13:40.160101 INFO: [APUAPC] D0_APC_0: 0x400510
10005 22:13:40.163261 INFO: [APUAPC] D0_APC_1: 0x0
10006 22:13:40.167262 INFO: [APUAPC] D0_APC_2: 0x1540
10007 22:13:40.170322 INFO: [APUAPC] D0_APC_3: 0x0
10008 22:13:40.173243 INFO: [APUAPC] D1_APC_0: 0xffffffff
10009 22:13:40.176505 INFO: [APUAPC] D1_APC_1: 0xffffffff
10010 22:13:40.180032 INFO: [APUAPC] D1_APC_2: 0x3fffff
10011 22:13:40.183917 INFO: [APUAPC] D1_APC_3: 0x0
10012 22:13:40.187284 INFO: [APUAPC] D2_APC_0: 0xffffffff
10013 22:13:40.190012 INFO: [APUAPC] D2_APC_1: 0xffffffff
10014 22:13:40.193534 INFO: [APUAPC] D2_APC_2: 0x3fffff
10015 22:13:40.196372 INFO: [APUAPC] D2_APC_3: 0x0
10016 22:13:40.200414 INFO: [APUAPC] D3_APC_0: 0xffffffff
10017 22:13:40.203155 INFO: [APUAPC] D3_APC_1: 0xffffffff
10018 22:13:40.206246 INFO: [APUAPC] D3_APC_2: 0x3fffff
10019 22:13:40.209632 INFO: [APUAPC] D3_APC_3: 0x0
10020 22:13:40.212815 INFO: [APUAPC] D4_APC_0: 0xffffffff
10021 22:13:40.216014 INFO: [APUAPC] D4_APC_1: 0xffffffff
10022 22:13:40.219584 INFO: [APUAPC] D4_APC_2: 0x3fffff
10023 22:13:40.223160 INFO: [APUAPC] D4_APC_3: 0x0
10024 22:13:40.226358 INFO: [APUAPC] D5_APC_0: 0xffffffff
10025 22:13:40.229427 INFO: [APUAPC] D5_APC_1: 0xffffffff
10026 22:13:40.232472 INFO: [APUAPC] D5_APC_2: 0x3fffff
10027 22:13:40.235989 INFO: [APUAPC] D5_APC_3: 0x0
10028 22:13:40.239459 INFO: [APUAPC] D6_APC_0: 0xffffffff
10029 22:13:40.242420 INFO: [APUAPC] D6_APC_1: 0xffffffff
10030 22:13:40.245986 INFO: [APUAPC] D6_APC_2: 0x3fffff
10031 22:13:40.248913 INFO: [APUAPC] D6_APC_3: 0x0
10032 22:13:40.252506 INFO: [APUAPC] D7_APC_0: 0xffffffff
10033 22:13:40.255758 INFO: [APUAPC] D7_APC_1: 0xffffffff
10034 22:13:40.259232 INFO: [APUAPC] D7_APC_2: 0x3fffff
10035 22:13:40.259695 INFO: [APUAPC] D7_APC_3: 0x0
10036 22:13:40.262648 INFO: [APUAPC] D8_APC_0: 0xffffffff
10037 22:13:40.269407 INFO: [APUAPC] D8_APC_1: 0xffffffff
10038 22:13:40.272358 INFO: [APUAPC] D8_APC_2: 0x3fffff
10039 22:13:40.272823 INFO: [APUAPC] D8_APC_3: 0x0
10040 22:13:40.275472 INFO: [APUAPC] D9_APC_0: 0xffffffff
10041 22:13:40.278978 INFO: [APUAPC] D9_APC_1: 0xffffffff
10042 22:13:40.282570 INFO: [APUAPC] D9_APC_2: 0x3fffff
10043 22:13:40.285399 INFO: [APUAPC] D9_APC_3: 0x0
10044 22:13:40.288642 INFO: [APUAPC] D10_APC_0: 0xffffffff
10045 22:13:40.291700 INFO: [APUAPC] D10_APC_1: 0xffffffff
10046 22:13:40.295369 INFO: [APUAPC] D10_APC_2: 0x3fffff
10047 22:13:40.298965 INFO: [APUAPC] D10_APC_3: 0x0
10048 22:13:40.301988 INFO: [APUAPC] D11_APC_0: 0xffffffff
10049 22:13:40.308826 INFO: [APUAPC] D11_APC_1: 0xffffffff
10050 22:13:40.311897 INFO: [APUAPC] D11_APC_2: 0x3fffff
10051 22:13:40.312468 INFO: [APUAPC] D11_APC_3: 0x0
10052 22:13:40.318267 INFO: [APUAPC] D12_APC_0: 0xffffffff
10053 22:13:40.321743 INFO: [APUAPC] D12_APC_1: 0xffffffff
10054 22:13:40.324855 INFO: [APUAPC] D12_APC_2: 0x3fffff
10055 22:13:40.325319 INFO: [APUAPC] D12_APC_3: 0x0
10056 22:13:40.331522 INFO: [APUAPC] D13_APC_0: 0xffffffff
10057 22:13:40.335044 INFO: [APUAPC] D13_APC_1: 0xffffffff
10058 22:13:40.338162 INFO: [APUAPC] D13_APC_2: 0x3fffff
10059 22:13:40.341458 INFO: [APUAPC] D13_APC_3: 0x0
10060 22:13:40.344693 INFO: [APUAPC] D14_APC_0: 0xffffffff
10061 22:13:40.348116 INFO: [APUAPC] D14_APC_1: 0xffffffff
10062 22:13:40.351338 INFO: [APUAPC] D14_APC_2: 0x3fffff
10063 22:13:40.354436 INFO: [APUAPC] D14_APC_3: 0x0
10064 22:13:40.358012 INFO: [APUAPC] D15_APC_0: 0xffffffff
10065 22:13:40.361222 INFO: [APUAPC] D15_APC_1: 0xffffffff
10066 22:13:40.364553 INFO: [APUAPC] D15_APC_2: 0x3fffff
10067 22:13:40.367742 INFO: [APUAPC] D15_APC_3: 0x0
10068 22:13:40.371124 INFO: [APUAPC] APC_CON: 0x4
10069 22:13:40.371592 INFO: [NOCDAPC] D0_APC_0: 0x0
10070 22:13:40.374795 INFO: [NOCDAPC] D0_APC_1: 0x0
10071 22:13:40.377365 INFO: [NOCDAPC] D1_APC_0: 0x0
10072 22:13:40.381337 INFO: [NOCDAPC] D1_APC_1: 0xfff
10073 22:13:40.383769 INFO: [NOCDAPC] D2_APC_0: 0x0
10074 22:13:40.387767 INFO: [NOCDAPC] D2_APC_1: 0xfff
10075 22:13:40.390794 INFO: [NOCDAPC] D3_APC_0: 0x0
10076 22:13:40.394084 INFO: [NOCDAPC] D3_APC_1: 0xfff
10077 22:13:40.397553 INFO: [NOCDAPC] D4_APC_0: 0x0
10078 22:13:40.401162 INFO: [NOCDAPC] D4_APC_1: 0xfff
10079 22:13:40.401739 INFO: [NOCDAPC] D5_APC_0: 0x0
10080 22:13:40.404264 INFO: [NOCDAPC] D5_APC_1: 0xfff
10081 22:13:40.407518 INFO: [NOCDAPC] D6_APC_0: 0x0
10082 22:13:40.410562 INFO: [NOCDAPC] D6_APC_1: 0xfff
10083 22:13:40.413829 INFO: [NOCDAPC] D7_APC_0: 0x0
10084 22:13:40.417256 INFO: [NOCDAPC] D7_APC_1: 0xfff
10085 22:13:40.420388 INFO: [NOCDAPC] D8_APC_0: 0x0
10086 22:13:40.424308 INFO: [NOCDAPC] D8_APC_1: 0xfff
10087 22:13:40.427527 INFO: [NOCDAPC] D9_APC_0: 0x0
10088 22:13:40.430856 INFO: [NOCDAPC] D9_APC_1: 0xfff
10089 22:13:40.433702 INFO: [NOCDAPC] D10_APC_0: 0x0
10090 22:13:40.437346 INFO: [NOCDAPC] D10_APC_1: 0xfff
10091 22:13:40.440765 INFO: [NOCDAPC] D11_APC_0: 0x0
10092 22:13:40.441496 INFO: [NOCDAPC] D11_APC_1: 0xfff
10093 22:13:40.443764 INFO: [NOCDAPC] D12_APC_0: 0x0
10094 22:13:40.447098 INFO: [NOCDAPC] D12_APC_1: 0xfff
10095 22:13:40.450019 INFO: [NOCDAPC] D13_APC_0: 0x0
10096 22:13:40.453577 INFO: [NOCDAPC] D13_APC_1: 0xfff
10097 22:13:40.456826 INFO: [NOCDAPC] D14_APC_0: 0x0
10098 22:13:40.460568 INFO: [NOCDAPC] D14_APC_1: 0xfff
10099 22:13:40.463789 INFO: [NOCDAPC] D15_APC_0: 0x0
10100 22:13:40.466671 INFO: [NOCDAPC] D15_APC_1: 0xfff
10101 22:13:40.470401 INFO: [NOCDAPC] APC_CON: 0x4
10102 22:13:40.473519 INFO: [APUAPC] set_apusys_apc done
10103 22:13:40.477217 INFO: [DEVAPC] devapc_init done
10104 22:13:40.480153 INFO: GICv3 without legacy support detected.
10105 22:13:40.483339 INFO: ARM GICv3 driver initialized in EL3
10106 22:13:40.486744 INFO: Maximum SPI INTID supported: 639
10107 22:13:40.493217 INFO: BL31: Initializing runtime services
10108 22:13:40.496865 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10109 22:13:40.499673 INFO: SPM: enable CPC mode
10110 22:13:40.506768 INFO: mcdi ready for mcusys-off-idle and system suspend
10111 22:13:40.509581 INFO: BL31: Preparing for EL3 exit to normal world
10112 22:13:40.513290 INFO: Entry point address = 0x80000000
10113 22:13:40.516317 INFO: SPSR = 0x8
10114 22:13:40.521445
10115 22:13:40.521906
10116 22:13:40.522270
10117 22:13:40.525046 Starting depthcharge on Spherion...
10118 22:13:40.525528
10119 22:13:40.525890 Wipe memory regions:
10120 22:13:40.526228
10121 22:13:40.529082 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10122 22:13:40.529648 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10123 22:13:40.530106 Setting prompt string to ['asurada:']
10124 22:13:40.530538 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10125 22:13:40.531284 [0x00000040000000, 0x00000054600000)
10126 22:13:40.650470
10127 22:13:40.651017 [0x00000054660000, 0x00000080000000)
10128 22:13:40.911553
10129 22:13:40.912112 [0x000000821a7280, 0x000000ffe64000)
10130 22:13:41.656095
10131 22:13:41.656654 [0x00000100000000, 0x00000240000000)
10132 22:13:43.546449
10133 22:13:43.549320 Initializing XHCI USB controller at 0x11200000.
10134 22:13:44.531327
10135 22:13:44.531884 R8152: Initializing
10136 22:13:44.532251
10137 22:13:44.534632 Version 9 (ocp_data = 6010)
10138 22:13:44.535238
10139 22:13:44.538234 R8152: Done initializing
10140 22:13:44.538792
10141 22:13:44.539222 Adding net device
10142 22:13:45.059635
10143 22:13:45.062673 [firmware-asurada-13885.B-collabora] Dec 14 2021 15:21:43
10144 22:13:45.063235
10145 22:13:45.063622
10146 22:13:45.063970
10147 22:13:45.064836 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10149 22:13:45.166160 asurada: tftpboot 192.168.201.1 10583852/tftp-deploy-8m8yc9em/kernel/image.itb 10583852/tftp-deploy-8m8yc9em/kernel/cmdline
10150 22:13:45.166870 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10151 22:13:45.167482 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10152 22:13:45.172534 tftpboot 192.168.201.1 10583852/tftp-deploy-8m8yc9em/kernel/image.itp-deploy-8m8yc9em/kernel/cmdline
10153 22:13:45.173046
10154 22:13:45.173425 Waiting for link
10155 22:13:45.374718
10156 22:13:45.375390 done.
10157 22:13:45.375793
10158 22:13:45.376141 MAC: f4:f5:e8:50:de:0a
10159 22:13:45.376500
10160 22:13:45.377855 Sending DHCP discover... done.
10161 22:13:45.378402
10162 22:13:45.382042 Waiting for reply... done.
10163 22:13:45.382666
10164 22:13:45.384483 Sending DHCP request... done.
10165 22:13:45.384991
10166 22:13:45.390455 Waiting for reply... done.
10167 22:13:45.390939
10168 22:13:45.391354 My ip is 192.168.201.14
10169 22:13:45.391734
10170 22:13:45.393650 The DHCP server ip is 192.168.201.1
10171 22:13:45.394117
10172 22:13:45.400383 TFTP server IP predefined by user: 192.168.201.1
10173 22:13:45.400857
10174 22:13:45.407360 Bootfile predefined by user: 10583852/tftp-deploy-8m8yc9em/kernel/image.itb
10175 22:13:45.407828
10176 22:13:45.410322 Sending tftp read request... done.
10177 22:13:45.410746
10178 22:13:45.415529 Waiting for the transfer...
10179 22:13:45.415971
10180 22:13:45.647205 00000000 ################################################################
10181 22:13:45.647337
10182 22:13:45.874213 00080000 ################################################################
10183 22:13:45.874348
10184 22:13:46.101510 00100000 ################################################################
10185 22:13:46.101667
10186 22:13:46.337954 00180000 ################################################################
10187 22:13:46.338087
10188 22:13:46.569448 00200000 ################################################################
10189 22:13:46.569603
10190 22:13:46.794830 00280000 ################################################################
10191 22:13:46.794965
10192 22:13:47.019544 00300000 ################################################################
10193 22:13:47.019677
10194 22:13:47.238479 00380000 ################################################################
10195 22:13:47.238624
10196 22:13:47.462508 00400000 ################################################################
10197 22:13:47.462651
10198 22:13:47.682106 00480000 ################################################################
10199 22:13:47.682256
10200 22:13:47.901457 00500000 ################################################################
10201 22:13:47.901660
10202 22:13:48.119982 00580000 ################################################################
10203 22:13:48.120119
10204 22:13:48.339580 00600000 ################################################################
10205 22:13:48.339728
10206 22:13:48.558876 00680000 ################################################################
10207 22:13:48.559006
10208 22:13:48.784086 00700000 ################################################################
10209 22:13:48.784230
10210 22:13:49.015415 00780000 ################################################################
10211 22:13:49.015557
10212 22:13:49.252327 00800000 ################################################################
10213 22:13:49.252458
10214 22:13:49.476092 00880000 ################################################################
10215 22:13:49.476229
10216 22:13:49.708110 00900000 ################################################################
10217 22:13:49.708261
10218 22:13:49.940184 00980000 ################################################################
10219 22:13:49.940313
10220 22:13:50.160454 00a00000 ################################################################
10221 22:13:50.160599
10222 22:13:50.384806 00a80000 ################################################################
10223 22:13:50.384982
10224 22:13:50.616278 00b00000 ################################################################
10225 22:13:50.616428
10226 22:13:50.858505 00b80000 ################################################################
10227 22:13:50.858657
10228 22:13:51.091454 00c00000 ################################################################
10229 22:13:51.091604
10230 22:13:51.329472 00c80000 ################################################################
10231 22:13:51.329615
10232 22:13:51.560357 00d00000 ################################################################
10233 22:13:51.560492
10234 22:13:51.795235 00d80000 ################################################################
10235 22:13:51.795382
10236 22:13:52.025585 00e00000 ################################################################
10237 22:13:52.025736
10238 22:13:52.251551 00e80000 ################################################################
10239 22:13:52.251684
10240 22:13:52.475724 00f00000 ################################################################
10241 22:13:52.475857
10242 22:13:52.704679 00f80000 ################################################################
10243 22:13:52.704806
10244 22:13:52.939890 01000000 ################################################################
10245 22:13:52.940020
10246 22:13:53.166576 01080000 ################################################################
10247 22:13:53.166705
10248 22:13:53.393547 01100000 ################################################################
10249 22:13:53.393715
10250 22:13:53.620911 01180000 ################################################################
10251 22:13:53.621072
10252 22:13:53.856646 01200000 ################################################################
10253 22:13:53.856779
10254 22:13:54.082260 01280000 ################################################################
10255 22:13:54.082395
10256 22:13:54.377762 01300000 ################################################################
10257 22:13:54.377942
10258 22:13:54.710687 01380000 ################################################################
10259 22:13:54.710868
10260 22:13:55.030692 01400000 ################################################################
10261 22:13:55.030870
10262 22:13:55.335926 01480000 ################################################################
10263 22:13:55.336096
10264 22:13:55.625050 01500000 ################################################################
10265 22:13:55.625199
10266 22:13:55.883759 01580000 ################################################################
10267 22:13:55.883896
10268 22:13:56.120845 01600000 ################################################################
10269 22:13:56.120981
10270 22:13:56.356239 01680000 ################################################################
10271 22:13:56.356379
10272 22:13:56.596895 01700000 ################################################################
10273 22:13:56.597054
10274 22:13:56.843772 01780000 ################################################################
10275 22:13:56.843899
10276 22:13:57.077936 01800000 ################################################################
10277 22:13:57.078068
10278 22:13:57.324156 01880000 ################################################################
10279 22:13:57.324297
10280 22:13:57.574350 01900000 ################################################################
10281 22:13:57.574481
10282 22:13:57.824119 01980000 ################################################################
10283 22:13:57.824278
10284 22:13:58.064745 01a00000 ############################################################### done.
10285 22:13:58.065231
10286 22:13:58.067623 The bootfile was 27774654 bytes long.
10287 22:13:58.068047
10288 22:13:58.070671 Sending tftp read request... done.
10289 22:13:58.071108
10290 22:13:58.074062 Waiting for the transfer...
10291 22:13:58.074668
10292 22:13:58.075030 00000000 # done.
10293 22:13:58.077337
10294 22:13:58.084273 Command line loaded dynamically from TFTP file: 10583852/tftp-deploy-8m8yc9em/kernel/cmdline
10295 22:13:58.084791
10296 22:13:58.104106 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10583852/extract-nfsrootfs-_32h7bf0,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10297 22:13:58.104682
10298 22:13:58.105053 Loading FIT.
10299 22:13:58.105396
10300 22:13:58.108105 Image ramdisk-1 has 17643968 bytes.
10301 22:13:58.108661
10302 22:13:58.110474 Image fdt-1 has 46924 bytes.
10303 22:13:58.110932
10304 22:13:58.113993 Image kernel-1 has 10081729 bytes.
10305 22:13:58.114579
10306 22:13:58.123609 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10307 22:13:58.124140
10308 22:13:58.139512 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10309 22:13:58.139605
10310 22:13:58.146676 Choosing best match conf-1 for compat google,spherion-rev2.
10311 22:13:58.146847
10312 22:13:58.153379 Connected to device vid:did:rid of 1ae0:0028:00
10313 22:13:58.160590
10314 22:13:58.164094 tpm_get_response: command 0x17b, return code 0x0
10315 22:13:58.164324
10316 22:13:58.167758 ec_init: CrosEC protocol v3 supported (256, 248)
10317 22:13:58.171666
10318 22:13:58.174691 tpm_cleanup: add release locality here.
10319 22:13:58.174952
10320 22:13:58.175138 Shutting down all USB controllers.
10321 22:13:58.178388
10322 22:13:58.178580 Removing current net device
10323 22:13:58.178719
10324 22:13:58.184766 Exiting depthcharge with code 4 at timestamp: 47035138
10325 22:13:58.185009
10326 22:13:58.188189 LZMA decompressing kernel-1 to 0x821a6718
10327 22:13:58.188439
10328 22:13:58.191334 LZMA decompressing kernel-1 to 0x40000000
10329 22:13:59.459769
10330 22:13:59.460318 jumping to kernel
10331 22:13:59.461724 end: 2.2.4 bootloader-commands (duration 00:00:19) [common]
10332 22:13:59.462255 start: 2.2.5 auto-login-action (timeout 00:04:06) [common]
10333 22:13:59.462653 Setting prompt string to ['Linux version [0-9]']
10334 22:13:59.463020 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10335 22:13:59.463426 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10336 22:13:59.541308
10337 22:13:59.544420 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10338 22:13:59.548529 start: 2.2.5.1 login-action (timeout 00:04:06) [common]
10339 22:13:59.548983 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10340 22:13:59.549428 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10341 22:13:59.549806 Using line separator: #'\n'#
10342 22:13:59.550114 No login prompt set.
10343 22:13:59.550424 Parsing kernel messages
10344 22:13:59.550704 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10345 22:13:59.551363 [login-action] Waiting for messages, (timeout 00:04:06)
10346 22:13:59.567315 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j1606555-arm64-gcc-10-defconfig-arm64-chromebook-vtq55) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sun Jun 4 21:56:05 UTC 2023
10347 22:13:59.570633 [ 0.000000] random: crng init done
10348 22:13:59.577572 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10349 22:13:59.580966 [ 0.000000] efi: UEFI not found.
10350 22:13:59.587410 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10351 22:13:59.594180 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10352 22:13:59.603575 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10353 22:13:59.613997 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10354 22:13:59.620024 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10355 22:13:59.626620 [ 0.000000] printk: bootconsole [mtk8250] enabled
10356 22:13:59.633038 [ 0.000000] NUMA: No NUMA configuration found
10357 22:13:59.639864 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10358 22:13:59.643001 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcda00-0x23efcffff]
10359 22:13:59.646568 [ 0.000000] Zone ranges:
10360 22:13:59.653040 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10361 22:13:59.656520 [ 0.000000] DMA32 empty
10362 22:13:59.663184 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10363 22:13:59.666173 [ 0.000000] Movable zone start for each node
10364 22:13:59.669407 [ 0.000000] Early memory node ranges
10365 22:13:59.676773 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10366 22:13:59.682750 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10367 22:13:59.689828 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10368 22:13:59.696249 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10369 22:13:59.702607 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10370 22:13:59.709085 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10371 22:13:59.765343 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10372 22:13:59.771862 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10373 22:13:59.779110 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10374 22:13:59.781578 [ 0.000000] psci: probing for conduit method from DT.
10375 22:13:59.787734 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10376 22:13:59.791551 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10377 22:13:59.797947 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10378 22:13:59.801083 [ 0.000000] psci: SMC Calling Convention v1.2
10379 22:13:59.807735 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10380 22:13:59.811632 [ 0.000000] Detected VIPT I-cache on CPU0
10381 22:13:59.817611 [ 0.000000] CPU features: detected: GIC system register CPU interface
10382 22:13:59.824290 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10383 22:13:59.831001 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10384 22:13:59.837789 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10385 22:13:59.847856 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10386 22:13:59.854245 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10387 22:13:59.857498 [ 0.000000] alternatives: applying boot alternatives
10388 22:13:59.864574 [ 0.000000] Fallback order for Node 0: 0
10389 22:13:59.870878 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10390 22:13:59.874308 [ 0.000000] Policy zone: Normal
10391 22:13:59.893518 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10583852/extract-nfsrootfs-_32h7bf0,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10392 22:13:59.903650 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10393 22:13:59.914585 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10394 22:13:59.924142 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10395 22:13:59.931179 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10396 22:13:59.934765 <6>[ 0.000000] software IO TLB: area num 8.
10397 22:13:59.990995 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10398 22:14:00.140236 <6>[ 0.000000] Memory: 7955712K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 397056K reserved, 32768K cma-reserved)
10399 22:14:00.146824 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10400 22:14:00.153652 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10401 22:14:00.156737 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10402 22:14:00.163432 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10403 22:14:00.169776 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10404 22:14:00.173317 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10405 22:14:00.182725 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10406 22:14:00.190194 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10407 22:14:00.196301 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10408 22:14:00.202512 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10409 22:14:00.205981 <6>[ 0.000000] GICv3: 608 SPIs implemented
10410 22:14:00.209510 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10411 22:14:00.216374 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10412 22:14:00.219591 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10413 22:14:00.226096 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10414 22:14:00.239427 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10415 22:14:00.253214 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10416 22:14:00.258930 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10417 22:14:00.266972 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10418 22:14:00.280350 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10419 22:14:00.286531 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10420 22:14:00.293388 <6>[ 0.009231] Console: colour dummy device 80x25
10421 22:14:00.303282 <6>[ 0.013960] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10422 22:14:00.310087 <6>[ 0.024402] pid_max: default: 32768 minimum: 301
10423 22:14:00.313390 <6>[ 0.029275] LSM: Security Framework initializing
10424 22:14:00.320053 <6>[ 0.034213] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10425 22:14:00.329637 <6>[ 0.042026] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10426 22:14:00.339608 <6>[ 0.051506] cblist_init_generic: Setting adjustable number of callback queues.
10427 22:14:00.343388 <6>[ 0.059006] cblist_init_generic: Setting shift to 3 and lim to 1.
10428 22:14:00.350014 <6>[ 0.065346] cblist_init_generic: Setting shift to 3 and lim to 1.
10429 22:14:00.356567 <6>[ 0.071750] rcu: Hierarchical SRCU implementation.
10430 22:14:00.363043 <6>[ 0.076795] rcu: Max phase no-delay instances is 1000.
10431 22:14:00.366193 <6>[ 0.083814] EFI services will not be available.
10432 22:14:00.373012 <6>[ 0.088783] smp: Bringing up secondary CPUs ...
10433 22:14:00.380699 <6>[ 0.093865] Detected VIPT I-cache on CPU1
10434 22:14:00.387210 <6>[ 0.093937] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10435 22:14:00.393816 <6>[ 0.093967] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10436 22:14:00.396795 <6>[ 0.094282] Detected VIPT I-cache on CPU2
10437 22:14:00.403870 <6>[ 0.094328] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10438 22:14:00.413541 <6>[ 0.094344] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10439 22:14:00.416627 <6>[ 0.094601] Detected VIPT I-cache on CPU3
10440 22:14:00.423528 <6>[ 0.094648] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10441 22:14:00.430008 <6>[ 0.094663] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10442 22:14:00.432957 <6>[ 0.094969] CPU features: detected: Spectre-v4
10443 22:14:00.440331 <6>[ 0.094975] CPU features: detected: Spectre-BHB
10444 22:14:00.443194 <6>[ 0.094981] Detected PIPT I-cache on CPU4
10445 22:14:00.449826 <6>[ 0.095037] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10446 22:14:00.456414 <6>[ 0.095054] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10447 22:14:00.462985 <6>[ 0.095345] Detected PIPT I-cache on CPU5
10448 22:14:00.470005 <6>[ 0.095408] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10449 22:14:00.476483 <6>[ 0.095425] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10450 22:14:00.479485 <6>[ 0.095705] Detected PIPT I-cache on CPU6
10451 22:14:00.486583 <6>[ 0.095770] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10452 22:14:00.495870 <6>[ 0.095786] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10453 22:14:00.499590 <6>[ 0.096086] Detected PIPT I-cache on CPU7
10454 22:14:00.506330 <6>[ 0.096150] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10455 22:14:00.513124 <6>[ 0.096166] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10456 22:14:00.517003 <6>[ 0.096213] smp: Brought up 1 node, 8 CPUs
10457 22:14:00.522546 <6>[ 0.237507] SMP: Total of 8 processors activated.
10458 22:14:00.525499 <6>[ 0.242459] CPU features: detected: 32-bit EL0 Support
10459 22:14:00.536089 <6>[ 0.247854] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10460 22:14:00.542966 <6>[ 0.256709] CPU features: detected: Common not Private translations
10461 22:14:00.549439 <6>[ 0.263225] CPU features: detected: CRC32 instructions
10462 22:14:00.553384 <6>[ 0.268576] CPU features: detected: RCpc load-acquire (LDAPR)
10463 22:14:00.559102 <6>[ 0.274572] CPU features: detected: LSE atomic instructions
10464 22:14:00.565983 <6>[ 0.280353] CPU features: detected: Privileged Access Never
10465 22:14:00.572710 <6>[ 0.286133] CPU features: detected: RAS Extension Support
10466 22:14:00.578980 <6>[ 0.291741] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10467 22:14:00.582146 <6>[ 0.298960] CPU: All CPU(s) started at EL2
10468 22:14:00.589052 <6>[ 0.303276] alternatives: applying system-wide alternatives
10469 22:14:00.598334 <6>[ 0.313943] devtmpfs: initialized
10470 22:14:00.613544 <6>[ 0.322719] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10471 22:14:00.620661 <6>[ 0.332683] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10472 22:14:00.627088 <6>[ 0.340700] pinctrl core: initialized pinctrl subsystem
10473 22:14:00.629962 <6>[ 0.347328] DMI not present or invalid.
10474 22:14:00.636794 <6>[ 0.351733] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10475 22:14:00.646422 <6>[ 0.358588] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10476 22:14:00.653318 <6>[ 0.366175] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10477 22:14:00.663393 <6>[ 0.374390] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10478 22:14:00.667169 <6>[ 0.382635] audit: initializing netlink subsys (disabled)
10479 22:14:00.676352 <5>[ 0.388329] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10480 22:14:00.683236 <6>[ 0.389022] thermal_sys: Registered thermal governor 'step_wise'
10481 22:14:00.689612 <6>[ 0.396297] thermal_sys: Registered thermal governor 'power_allocator'
10482 22:14:00.692602 <6>[ 0.402552] cpuidle: using governor menu
10483 22:14:00.699553 <6>[ 0.413513] NET: Registered PF_QIPCRTR protocol family
10484 22:14:00.706161 <6>[ 0.418999] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10485 22:14:00.713239 <6>[ 0.426102] ASID allocator initialised with 32768 entries
10486 22:14:00.715326 <6>[ 0.432651] Serial: AMBA PL011 UART driver
10487 22:14:00.725368 <4>[ 0.441240] Trying to register duplicate clock ID: 134
10488 22:14:00.779181 <6>[ 0.498425] KASLR enabled
10489 22:14:00.793714 <6>[ 0.506151] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10490 22:14:00.800244 <6>[ 0.513165] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10491 22:14:00.806730 <6>[ 0.519657] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10492 22:14:00.813635 <6>[ 0.526662] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10493 22:14:00.819598 <6>[ 0.533150] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10494 22:14:00.826492 <6>[ 0.540155] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10495 22:14:00.833344 <6>[ 0.546642] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10496 22:14:00.839580 <6>[ 0.553648] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10497 22:14:00.842689 <6>[ 0.561155] ACPI: Interpreter disabled.
10498 22:14:00.851717 <6>[ 0.567530] iommu: Default domain type: Translated
10499 22:14:00.858211 <6>[ 0.572643] iommu: DMA domain TLB invalidation policy: strict mode
10500 22:14:00.861536 <5>[ 0.579298] SCSI subsystem initialized
10501 22:14:00.868224 <6>[ 0.583463] usbcore: registered new interface driver usbfs
10502 22:14:00.874877 <6>[ 0.589197] usbcore: registered new interface driver hub
10503 22:14:00.877969 <6>[ 0.594750] usbcore: registered new device driver usb
10504 22:14:00.884850 <6>[ 0.600822] pps_core: LinuxPPS API ver. 1 registered
10505 22:14:00.894791 <6>[ 0.606017] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10506 22:14:00.898466 <6>[ 0.615363] PTP clock support registered
10507 22:14:00.902042 <6>[ 0.619604] EDAC MC: Ver: 3.0.0
10508 22:14:00.909412 <6>[ 0.624738] FPGA manager framework
10509 22:14:00.915335 <6>[ 0.628416] Advanced Linux Sound Architecture Driver Initialized.
10510 22:14:00.919200 <6>[ 0.635180] vgaarb: loaded
10511 22:14:00.925254 <6>[ 0.638356] clocksource: Switched to clocksource arch_sys_counter
10512 22:14:00.929074 <5>[ 0.644794] VFS: Disk quotas dquot_6.6.0
10513 22:14:00.935823 <6>[ 0.648978] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10514 22:14:00.938934 <6>[ 0.656167] pnp: PnP ACPI: disabled
10515 22:14:00.947586 <6>[ 0.662823] NET: Registered PF_INET protocol family
10516 22:14:00.957136 <6>[ 0.668408] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10517 22:14:00.968948 <6>[ 0.680631] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10518 22:14:00.978533 <6>[ 0.689446] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10519 22:14:00.985338 <6>[ 0.697415] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10520 22:14:00.995241 <6>[ 0.706116] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10521 22:14:01.001452 <6>[ 0.715836] TCP: Hash tables configured (established 65536 bind 65536)
10522 22:14:01.008115 <6>[ 0.722692] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10523 22:14:01.017648 <6>[ 0.729891] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10524 22:14:01.024422 <6>[ 0.737593] NET: Registered PF_UNIX/PF_LOCAL protocol family
10525 22:14:01.031233 <6>[ 0.743765] RPC: Registered named UNIX socket transport module.
10526 22:14:01.034690 <6>[ 0.749919] RPC: Registered udp transport module.
10527 22:14:01.040904 <6>[ 0.754850] RPC: Registered tcp transport module.
10528 22:14:01.047586 <6>[ 0.759784] RPC: Registered tcp NFSv4.1 backchannel transport module.
10529 22:14:01.050626 <6>[ 0.766455] PCI: CLS 0 bytes, default 64
10530 22:14:01.053847 <6>[ 0.770858] Unpacking initramfs...
10531 22:14:01.064166 <6>[ 0.774949] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10532 22:14:01.070783 <6>[ 0.783589] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10533 22:14:01.077066 <6>[ 0.792460] kvm [1]: IPA Size Limit: 40 bits
10534 22:14:01.080902 <6>[ 0.796990] kvm [1]: GICv3: no GICV resource entry
10535 22:14:01.087487 <6>[ 0.802011] kvm [1]: disabling GICv2 emulation
10536 22:14:01.093356 <6>[ 0.806696] kvm [1]: GIC system register CPU interface enabled
10537 22:14:01.097255 <6>[ 0.812861] kvm [1]: vgic interrupt IRQ18
10538 22:14:01.104229 <6>[ 0.817222] kvm [1]: VHE mode initialized successfully
10539 22:14:01.106827 <5>[ 0.823556] Initialise system trusted keyrings
10540 22:14:01.113055 <6>[ 0.828333] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10541 22:14:01.122843 <6>[ 0.838263] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10542 22:14:01.129186 <5>[ 0.844637] NFS: Registering the id_resolver key type
10543 22:14:01.132495 <5>[ 0.849940] Key type id_resolver registered
10544 22:14:01.139869 <5>[ 0.854355] Key type id_legacy registered
10545 22:14:01.145732 <6>[ 0.858635] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10546 22:14:01.153209 <6>[ 0.865555] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10547 22:14:01.159020 <6>[ 0.873256] 9p: Installing v9fs 9p2000 file system support
10548 22:14:01.194950 <5>[ 0.910183] Key type asymmetric registered
10549 22:14:01.198220 <5>[ 0.914512] Asymmetric key parser 'x509' registered
10550 22:14:01.208367 <6>[ 0.919650] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10551 22:14:01.211099 <6>[ 0.927264] io scheduler mq-deadline registered
10552 22:14:01.214614 <6>[ 0.932026] io scheduler kyber registered
10553 22:14:01.232963 <6>[ 0.948698] EINJ: ACPI disabled.
10554 22:14:01.265198 <4>[ 0.974125] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10555 22:14:01.275610 <4>[ 0.984748] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10556 22:14:01.289997 <6>[ 1.005320] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10557 22:14:01.298363 <6>[ 1.013399] printk: console [ttyS0] disabled
10558 22:14:01.325638 <6>[ 1.038058] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10559 22:14:01.332368 <6>[ 1.047543] printk: console [ttyS0] enabled
10560 22:14:01.335815 <6>[ 1.047543] printk: console [ttyS0] enabled
10561 22:14:01.342757 <6>[ 1.056436] printk: bootconsole [mtk8250] disabled
10562 22:14:01.345577 <6>[ 1.056436] printk: bootconsole [mtk8250] disabled
10563 22:14:01.353402 <6>[ 1.067715] SuperH (H)SCI(F) driver initialized
10564 22:14:01.356078 <6>[ 1.072972] msm_serial: driver initialized
10565 22:14:01.369822 <6>[ 1.081907] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10566 22:14:01.379706 <6>[ 1.090460] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10567 22:14:01.386402 <6>[ 1.099003] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10568 22:14:01.396444 <6>[ 1.107631] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10569 22:14:01.405932 <6>[ 1.116336] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10570 22:14:01.412886 <6>[ 1.125050] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10571 22:14:01.422520 <6>[ 1.133593] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10572 22:14:01.429174 <6>[ 1.142412] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10573 22:14:01.438769 <6>[ 1.150962] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10574 22:14:01.450957 <6>[ 1.166546] loop: module loaded
10575 22:14:01.457960 <6>[ 1.172567] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10576 22:14:01.480452 <4>[ 1.195869] mtk-pmic-keys: Failed to locate of_node [id: -1]
10577 22:14:01.487532 <6>[ 1.202714] megasas: 07.719.03.00-rc1
10578 22:14:01.496764 <6>[ 1.212255] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10579 22:14:01.510263 <6>[ 1.225731] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10580 22:14:01.527086 <6>[ 1.242354] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10581 22:14:01.588041 <6>[ 1.296823] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10582 22:14:01.830032 <6>[ 1.546048] Freeing initrd memory: 17228K
10583 22:14:01.840836 <6>[ 1.556110] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10584 22:14:01.851514 <6>[ 1.566873] tun: Universal TUN/TAP device driver, 1.6
10585 22:14:01.854319 <6>[ 1.572913] thunder_xcv, ver 1.0
10586 22:14:01.858092 <6>[ 1.576416] thunder_bgx, ver 1.0
10587 22:14:01.861047 <6>[ 1.579911] nicpf, ver 1.0
10588 22:14:01.871584 <6>[ 1.583926] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10589 22:14:01.874903 <6>[ 1.591403] hns3: Copyright (c) 2017 Huawei Corporation.
10590 22:14:01.878443 <6>[ 1.596988] hclge is initializing
10591 22:14:01.884938 <6>[ 1.600565] e1000: Intel(R) PRO/1000 Network Driver
10592 22:14:01.891288 <6>[ 1.605694] e1000: Copyright (c) 1999-2006 Intel Corporation.
10593 22:14:01.894804 <6>[ 1.611707] e1000e: Intel(R) PRO/1000 Network Driver
10594 22:14:01.901725 <6>[ 1.616924] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10595 22:14:01.908559 <6>[ 1.623114] igb: Intel(R) Gigabit Ethernet Network Driver
10596 22:14:01.914843 <6>[ 1.628764] igb: Copyright (c) 2007-2014 Intel Corporation.
10597 22:14:01.921576 <6>[ 1.634600] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10598 22:14:01.927621 <6>[ 1.641118] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10599 22:14:01.931136 <6>[ 1.647576] sky2: driver version 1.30
10600 22:14:01.937549 <6>[ 1.652543] VFIO - User Level meta-driver version: 0.3
10601 22:14:01.945094 <6>[ 1.660667] usbcore: registered new interface driver usb-storage
10602 22:14:01.952338 <6>[ 1.667107] usbcore: registered new device driver onboard-usb-hub
10603 22:14:01.960497 <6>[ 1.676151] mt6397-rtc mt6359-rtc: registered as rtc0
10604 22:14:01.970286 <6>[ 1.681626] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-04T22:14:14 UTC (1685916854)
10605 22:14:01.973671 <6>[ 1.691194] i2c_dev: i2c /dev entries driver
10606 22:14:01.991029 <6>[ 1.702776] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10607 22:14:01.997487 <6>[ 1.712980] sdhci: Secure Digital Host Controller Interface driver
10608 22:14:02.003900 <6>[ 1.719418] sdhci: Copyright(c) Pierre Ossman
10609 22:14:02.010580 <6>[ 1.724812] Synopsys Designware Multimedia Card Interface Driver
10610 22:14:02.014226 <6>[ 1.731432] mmc0: CQHCI version 5.10
10611 22:14:02.021104 <6>[ 1.731958] sdhci-pltfm: SDHCI platform and OF driver helper
10612 22:14:02.028329 <6>[ 1.743715] ledtrig-cpu: registered to indicate activity on CPUs
10613 22:14:02.038889 <6>[ 1.751093] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10614 22:14:02.042064 <6>[ 1.758494] usbcore: registered new interface driver usbhid
10615 22:14:02.049074 <6>[ 1.764319] usbhid: USB HID core driver
10616 22:14:02.055476 <6>[ 1.768568] spi_master spi0: will run message pump with realtime priority
10617 22:14:02.102326 <6>[ 1.811352] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10618 22:14:02.122570 <6>[ 1.827898] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10619 22:14:02.125837 <6>[ 1.841454] mmc0: Command Queue Engine enabled
10620 22:14:02.132455 <6>[ 1.846235] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10621 22:14:02.139261 <6>[ 1.853370] cros-ec-spi spi0.0: Chrome EC device registered
10622 22:14:02.142891 <6>[ 1.853637] mmcblk0: mmc0:0001 DA4128 116 GiB
10623 22:14:02.153176 <6>[ 1.868803] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10624 22:14:02.160985 <6>[ 1.876333] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10625 22:14:02.167889 <6>[ 1.882324] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10626 22:14:02.174136 <6>[ 1.888334] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10627 22:14:02.190988 <6>[ 1.903657] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10628 22:14:02.199574 <6>[ 1.915107] NET: Registered PF_PACKET protocol family
10629 22:14:02.203160 <6>[ 1.920543] 9pnet: Installing 9P2000 support
10630 22:14:02.209673 <5>[ 1.925132] Key type dns_resolver registered
10631 22:14:02.213062 <6>[ 1.930339] registered taskstats version 1
10632 22:14:02.219463 <5>[ 1.934775] Loading compiled-in X.509 certificates
10633 22:14:02.253119 <4>[ 1.961776] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10634 22:14:02.262989 <4>[ 1.972484] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10635 22:14:02.273293 <3>[ 1.985081] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10636 22:14:02.284859 <6>[ 2.000661] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10637 22:14:02.291634 <6>[ 2.007419] xhci-mtk 11200000.usb: xHCI Host Controller
10638 22:14:02.298157 <6>[ 2.012928] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10639 22:14:02.308357 <6>[ 2.020781] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10640 22:14:02.314888 <6>[ 2.030222] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10641 22:14:02.321271 <6>[ 2.036398] xhci-mtk 11200000.usb: xHCI Host Controller
10642 22:14:02.328348 <6>[ 2.041901] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10643 22:14:02.334974 <6>[ 2.049562] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10644 22:14:02.342085 <6>[ 2.057434] hub 1-0:1.0: USB hub found
10645 22:14:02.344872 <6>[ 2.061467] hub 1-0:1.0: 1 port detected
10646 22:14:02.355609 <6>[ 2.065817] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10647 22:14:02.358229 <6>[ 2.074640] hub 2-0:1.0: USB hub found
10648 22:14:02.361536 <6>[ 2.078672] hub 2-0:1.0: 1 port detected
10649 22:14:02.370399 <6>[ 2.085804] mtk-msdc 11f70000.mmc: Got CD GPIO
10650 22:14:02.388152 <6>[ 2.100384] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10651 22:14:02.394560 <6>[ 2.108413] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10652 22:14:02.405266 <4>[ 2.116393] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10653 22:14:02.414708 <6>[ 2.126046] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10654 22:14:02.421569 <6>[ 2.134128] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10655 22:14:02.427977 <6>[ 2.142149] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10656 22:14:02.438167 <6>[ 2.150067] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10657 22:14:02.444726 <6>[ 2.157888] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10658 22:14:02.455374 <6>[ 2.165709] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10659 22:14:02.464624 <6>[ 2.176380] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10660 22:14:02.470716 <6>[ 2.184752] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10661 22:14:02.481158 <6>[ 2.193104] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10662 22:14:02.488118 <6>[ 2.201448] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10663 22:14:02.497985 <6>[ 2.209792] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10664 22:14:02.504203 <6>[ 2.218134] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10665 22:14:02.514394 <6>[ 2.226477] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10666 22:14:02.524059 <6>[ 2.234820] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10667 22:14:02.531556 <6>[ 2.243164] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10668 22:14:02.540911 <6>[ 2.251517] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10669 22:14:02.547738 <6>[ 2.259861] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10670 22:14:02.557800 <6>[ 2.268204] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10671 22:14:02.564266 <6>[ 2.276554] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10672 22:14:02.573901 <6>[ 2.284899] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10673 22:14:02.580519 <6>[ 2.293245] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10674 22:14:02.586897 <6>[ 2.302146] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10675 22:14:02.593828 <6>[ 2.309574] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10676 22:14:02.601140 <6>[ 2.316590] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10677 22:14:02.611271 <6>[ 2.323678] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10678 22:14:02.617842 <6>[ 2.330953] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10679 22:14:02.628023 <6>[ 2.337852] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10680 22:14:02.634541 <6>[ 2.346991] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10681 22:14:02.645005 <6>[ 2.356119] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10682 22:14:02.654452 <6>[ 2.365421] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10683 22:14:02.663908 <6>[ 2.374897] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10684 22:14:02.674289 <6>[ 2.384371] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10685 22:14:02.684407 <6>[ 2.393498] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10686 22:14:02.690213 <6>[ 2.402973] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10687 22:14:02.700925 <6>[ 2.412100] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10688 22:14:02.710436 <6>[ 2.421401] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10689 22:14:02.720586 <6>[ 2.431568] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10690 22:14:02.730756 <6>[ 2.443089] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10691 22:14:02.737834 <6>[ 2.453221] Trying to probe devices needed for running init ...
10692 22:14:02.774339 <6>[ 2.486634] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10693 22:14:02.927679 <6>[ 2.643244] hub 1-1:1.0: USB hub found
10694 22:14:02.930690 <6>[ 2.647698] hub 1-1:1.0: 4 ports detected
10695 22:14:03.054704 <6>[ 2.766706] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10696 22:14:03.081974 <6>[ 2.796820] hub 2-1:1.0: USB hub found
10697 22:14:03.084899 <6>[ 2.801315] hub 2-1:1.0: 3 ports detected
10698 22:14:03.250448 <6>[ 2.962628] usb 1-1.1: new high-speed USB device number 3 using xhci-mtk
10699 22:14:03.381203 <6>[ 3.096491] hub 1-1.1:1.0: USB hub found
10700 22:14:03.385621 <6>[ 3.100774] hub 1-1.1:1.0: 4 ports detected
10701 22:14:03.498000 <6>[ 3.210406] usb 1-1.4: new high-speed USB device number 4 using xhci-mtk
10702 22:14:03.631119 <6>[ 3.346391] hub 1-1.4:1.0: USB hub found
10703 22:14:03.633989 <6>[ 3.351012] hub 1-1.4:1.0: 2 ports detected
10704 22:14:03.710351 <6>[ 3.422631] usb 1-1.1.1: new high-speed USB device number 5 using xhci-mtk
10705 22:14:03.898808 <6>[ 3.610629] usb 1-1.1.4: new full-speed USB device number 6 using xhci-mtk
10706 22:14:03.983815 <3>[ 3.698842] usb 1-1.1.4: device descriptor read/64, error -32
10707 22:14:04.175472 <3>[ 3.890864] usb 1-1.1.4: device descriptor read/64, error -32
10708 22:14:04.370390 <6>[ 4.082582] usb 1-1.4.1: new high-speed USB device number 7 using xhci-mtk
10709 22:14:04.558864 <6>[ 4.270630] usb 1-1.1.4: new full-speed USB device number 8 using xhci-mtk
10710 22:14:04.643161 <3>[ 4.358839] usb 1-1.1.4: device descriptor read/64, error -32
10711 22:14:04.835604 <3>[ 4.550839] usb 1-1.1.4: device descriptor read/64, error -32
10712 22:14:04.947974 <6>[ 4.663206] usb 1-1.1-port4: attempt power cycle
10713 22:14:05.034133 <6>[ 4.746629] usb 1-1.4.2: new high-speed USB device number 9 using xhci-mtk
10714 22:14:05.558544 <6>[ 5.270630] usb 1-1.1.4: new full-speed USB device number 10 using xhci-mtk
10715 22:14:05.564606 <4>[ 5.277986] usb 1-1.1.4: Device not responding to setup address.
10716 22:14:05.774769 <4>[ 5.490743] usb 1-1.1.4: Device not responding to setup address.
10717 22:14:05.986631 <3>[ 5.702617] usb 1-1.1.4: device not accepting address 10, error -71
10718 22:14:06.074460 <6>[ 5.786629] usb 1-1.1.4: new full-speed USB device number 11 using xhci-mtk
10719 22:14:06.081042 <4>[ 5.794084] usb 1-1.1.4: Device not responding to setup address.
10720 22:14:06.291046 <4>[ 6.006913] usb 1-1.1.4: Device not responding to setup address.
10721 22:14:06.503042 <3>[ 6.218619] usb 1-1.1.4: device not accepting address 11, error -71
10722 22:14:06.510480 <3>[ 6.225568] usb 1-1.1-port4: unable to enumerate USB device
10723 22:14:15.011148 <6>[ 14.731189] ALSA device list:
10724 22:14:15.017624 <6>[ 14.734445] No soundcards found.
10725 22:14:15.030228 <6>[ 14.746884] Freeing unused kernel memory: 8384K
10726 22:14:15.033956 <6>[ 14.751815] Run /init as init process
10727 22:14:15.043863 Loading, please wait...
10728 22:14:15.063845 Starting version 247.3-7+deb11u2
10729 22:14:15.403591 <6>[ 15.117126] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10730 22:14:15.413907 <3>[ 15.127225] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10731 22:14:15.420501 <6>[ 15.128295] remoteproc remoteproc0: scp is available
10732 22:14:15.426970 <3>[ 15.135476] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10733 22:14:15.436676 <4>[ 15.140832] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10734 22:14:15.440248 <6>[ 15.141133] mc: Linux media interface: v0.10
10735 22:14:15.450332 <6>[ 15.142516] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10736 22:14:15.456831 <6>[ 15.142544] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10737 22:14:15.467441 <6>[ 15.142554] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10738 22:14:15.473407 <6>[ 15.150584] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10739 22:14:15.480371 <6>[ 15.157603] usbcore: registered new interface driver r8152
10740 22:14:15.486352 <6>[ 15.159729] videodev: Linux video capture interface: v2.00
10741 22:14:15.490062 <6>[ 15.161327] remoteproc remoteproc0: powering up scp
10742 22:14:15.499639 <4>[ 15.161362] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10743 22:14:15.506447 <3>[ 15.161368] remoteproc remoteproc0: request_firmware failed: -2
10744 22:14:15.515864 <3>[ 15.163790] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10745 22:14:15.533199 <3>[ 15.246025] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10746 22:14:15.538891 <3>[ 15.254169] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10747 22:14:15.549441 <4>[ 15.255187] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10748 22:14:15.555832 <3>[ 15.262272] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10749 22:14:15.565464 <3>[ 15.262283] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10750 22:14:15.572423 <3>[ 15.262290] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10751 22:14:15.578972 <3>[ 15.262453] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10752 22:14:15.588274 <6>[ 15.263866] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10753 22:14:15.592313 <6>[ 15.263874] pci_bus 0000:00: root bus resource [bus 00-ff]
10754 22:14:15.599028 <6>[ 15.263881] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10755 22:14:15.609238 <6>[ 15.263887] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10756 22:14:15.615235 <6>[ 15.263919] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10757 22:14:15.622051 <6>[ 15.263939] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10758 22:14:15.628905 <6>[ 15.264023] pci 0000:00:00.0: supports D1 D2
10759 22:14:15.635580 <6>[ 15.264027] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10760 22:14:15.643119 <6>[ 15.266019] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10761 22:14:15.648915 <6>[ 15.266125] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10762 22:14:15.655686 <6>[ 15.266155] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10763 22:14:15.665478 <6>[ 15.266174] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10764 22:14:15.672355 <6>[ 15.266192] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10765 22:14:15.675566 <6>[ 15.266303] pci 0000:01:00.0: supports D1 D2
10766 22:14:15.682264 <6>[ 15.266307] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10767 22:14:15.692129 <4>[ 15.270030] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10768 22:14:15.698691 <3>[ 15.277807] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10769 22:14:15.705318 <6>[ 15.278441] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10770 22:14:15.715622 <6>[ 15.278475] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10771 22:14:15.721528 <6>[ 15.278484] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10772 22:14:15.727981 <6>[ 15.278501] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10773 22:14:15.738498 <6>[ 15.278517] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10774 22:14:15.744975 <6>[ 15.278534] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10775 22:14:15.752436 <6>[ 15.278551] pci 0000:00:00.0: PCI bridge to [bus 01]
10776 22:14:15.758274 <6>[ 15.278559] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10777 22:14:15.764787 <6>[ 15.278783] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10778 22:14:15.771626 <6>[ 15.280528] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10779 22:14:15.778698 <6>[ 15.280801] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10780 22:14:15.784756 <4>[ 15.293302] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10781 22:14:15.791736 <4>[ 15.293302] Fallback method does not support PEC.
10782 22:14:15.798279 <3>[ 15.293977] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10783 22:14:15.807702 <3>[ 15.318304] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10784 22:14:15.817652 <3>[ 15.321769] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10785 22:14:15.823975 <3>[ 15.321953] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10786 22:14:15.830940 <6>[ 15.346620] usb 1-1.1.1: reset high-speed USB device number 5 using xhci-mtk
10787 22:14:15.840497 <3>[ 15.350072] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10788 22:14:15.847375 <3>[ 15.350079] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10789 22:14:15.858640 <3>[ 15.350086] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10790 22:14:15.863944 <3>[ 15.363962] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10791 22:14:15.873894 <3>[ 15.365211] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10792 22:14:15.883856 <6>[ 15.374190] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10793 22:14:15.890596 <3>[ 15.379004] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10794 22:14:15.900488 <6>[ 15.386932] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10795 22:14:15.910222 <6>[ 15.397716] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10796 22:14:15.916766 <4>[ 15.461546] r8152 1-1.1.1:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10797 22:14:15.923968 <6>[ 15.488645] usbcore: registered new interface driver cdc_ether
10798 22:14:15.933357 <5>[ 15.490960] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10799 22:14:15.940217 <4>[ 15.493442] r8152 1-1.1.1:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10800 22:14:15.943326 <6>[ 15.500812] Bluetooth: Core ver 2.22
10801 22:14:15.950796 <5>[ 15.502759] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10802 22:14:15.959565 <4>[ 15.502843] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10803 22:14:15.966105 <6>[ 15.502850] cfg80211: failed to load regulatory.db
10804 22:14:15.972743 <6>[ 15.521450] usbcore: registered new interface driver r8153_ecm
10805 22:14:15.979670 <6>[ 15.522040] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10806 22:14:15.989342 <6>[ 15.523307] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10807 22:14:15.995742 <6>[ 15.523442] usbcore: registered new interface driver uvcvideo
10808 22:14:16.002623 <6>[ 15.529947] NET: Registered PF_BLUETOOTH protocol family
10809 22:14:16.009454 <6>[ 15.562983] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10810 22:14:16.015712 <6>[ 15.569614] Bluetooth: HCI device and connection manager initialized
10811 22:14:16.019346 <6>[ 15.570437] r8152 1-1.1.1:1.0 eth0: v1.12.13
10812 22:14:16.026110 <6>[ 15.579744] r8152 1-1.1.1:1.0 enxf4f5e850de0a: renamed from eth0
10813 22:14:16.032732 <6>[ 15.586484] Bluetooth: HCI socket layer initialized
10814 22:14:16.039734 <6>[ 15.613351] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10815 22:14:16.045984 <6>[ 15.621749] Bluetooth: L2CAP socket layer initialized
10816 22:14:16.049337 <6>[ 15.631136] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10817 22:14:16.056019 <6>[ 15.640258] Bluetooth: SCO socket layer initialized
10818 22:14:16.062152 <6>[ 15.666543] mt7921e 0000:01:00.0: ASIC revision: 79610010
10819 22:14:16.066189 <6>[ 15.724887] usbcore: registered new interface driver btusb
10820 22:14:16.078473 <4>[ 15.742102] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10821 22:14:16.085185 <3>[ 15.799446] Bluetooth: hci0: Failed to load firmware file (-2)
10822 22:14:16.088456 <3>[ 15.805635] Bluetooth: hci0: Failed to set up firmware (-2)
10823 22:14:16.098229 <4>[ 15.811494] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10824 22:14:16.127344 <4>[ 15.837877] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10825 22:14:16.131000 Begin: Loading essential drivers ... done.
10826 22:14:16.134109 Begin: Running /scripts/init-premount ... done.
10827 22:14:16.144193 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10828 22:14:16.151633 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10829 22:14:16.154585 Device /sys/class/net/enxf4f5e850de0a found
10830 22:14:16.157851 done.
10831 22:14:16.213130 IP-Config: enxf4f5e850de0a hardware address f4:f5:e8:50:de:0a mtu 1500 DHCP
10832 22:14:16.250995 <4>[ 15.960815] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10833 22:14:16.370372 <4>[ 16.080161] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10834 22:14:16.485472 <4>[ 16.195959] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10835 22:14:16.601458 <4>[ 16.311933] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10836 22:14:16.717258 <4>[ 16.427808] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10837 22:14:16.834690 <4>[ 16.543843] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10838 22:14:16.949242 <4>[ 16.659714] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10839 22:14:17.065675 <4>[ 16.775722] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10840 22:14:17.181139 <4>[ 16.891573] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10841 22:14:17.288338 <3>[ 17.005578] mt7921e 0000:01:00.0: hardware init failed
10842 22:14:17.464595 IP-Config: no response after 2 secs - giving up
10843 22:14:17.504983 IP-Config: enxf4f5e850de0a hardware address f4:f5:e8:50:de:0a mtu 1500 DHCP
10844 22:14:17.561853 <6>[ 17.278625] r8152 1-1.1.1:1.0 enxf4f5e850de0a: carrier on
10845 22:14:18.606534 IP-Config: enxf4f5e850de0a complete (dhcp from 192.168.201.1):
10846 22:14:18.613227 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10847 22:14:18.619602 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10848 22:14:18.625942 host : mt8192-asurada-spherion-r0-cbg-9
10849 22:14:18.632710 domain : lava-rack
10850 22:14:18.636454 rootserver: 192.168.201.1 rootpath:
10851 22:14:18.639671 filename :
10852 22:14:18.688252 done.
10853 22:14:18.695093 Begin: Running /scripts/nfs-bottom ... done.
10854 22:14:18.712998 Begin: Running /scripts/init-bottom ... done.
10855 22:14:19.846972 <6>[ 19.563901] NET: Registered PF_INET6 protocol family
10856 22:14:19.853201 <6>[ 19.570622] Segment Routing with IPv6
10857 22:14:19.856177 <6>[ 19.574611] In-situ OAM (IOAM) with IPv6
10858 22:14:19.975654 <30>[ 19.672930] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10859 22:14:19.978413 <30>[ 19.696685] systemd[1]: Detected architecture arm64.
10860 22:14:20.000428
10861 22:14:20.003662 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10862 22:14:20.004131
10863 22:14:20.020294 <30>[ 19.737345] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10864 22:14:20.604078 <30>[ 20.318408] systemd[1]: Queued start job for default target Graphical Interface.
10865 22:14:20.642207 <30>[ 20.359670] systemd[1]: Created slice system-getty.slice.
10866 22:14:20.648533 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10867 22:14:20.665641 <30>[ 20.383212] systemd[1]: Created slice system-modprobe.slice.
10868 22:14:20.672719 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10869 22:14:20.690397 <30>[ 20.407790] systemd[1]: Created slice system-serial\x2dgetty.slice.
10870 22:14:20.700775 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10871 22:14:20.714083 <30>[ 20.431127] systemd[1]: Created slice User and Session Slice.
10872 22:14:20.720425 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10873 22:14:20.740815 <30>[ 20.455210] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10874 22:14:20.751217 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10875 22:14:20.768630 <30>[ 20.482802] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10876 22:14:20.775345 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10877 22:14:20.795894 <30>[ 20.506739] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10878 22:14:20.802937 <30>[ 20.518774] systemd[1]: Reached target Local Encrypted Volumes.
10879 22:14:20.809210 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10880 22:14:20.825461 <30>[ 20.542926] systemd[1]: Reached target Paths.
10881 22:14:20.828934 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10882 22:14:20.845431 <30>[ 20.562680] systemd[1]: Reached target Remote File Systems.
10883 22:14:20.851993 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10884 22:14:20.865016 <30>[ 20.582664] systemd[1]: Reached target Slices.
10885 22:14:20.868243 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10886 22:14:20.886003 <30>[ 20.602679] systemd[1]: Reached target Swap.
10887 22:14:20.888943 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10888 22:14:20.908924 <30>[ 20.622996] systemd[1]: Listening on initctl Compatibility Named Pipe.
10889 22:14:20.915742 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10890 22:14:20.922281 <30>[ 20.638527] systemd[1]: Listening on Journal Audit Socket.
10891 22:14:20.929219 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10892 22:14:20.941954 <30>[ 20.659732] systemd[1]: Listening on Journal Socket (/dev/log).
10893 22:14:20.948905 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10894 22:14:20.965931 <30>[ 20.683455] systemd[1]: Listening on Journal Socket.
10895 22:14:20.972310 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10896 22:14:20.990141 <30>[ 20.704001] systemd[1]: Listening on Network Service Netlink Socket.
10897 22:14:20.996660 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10898 22:14:21.012144 <30>[ 20.729934] systemd[1]: Listening on udev Control Socket.
10899 22:14:21.019508 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10900 22:14:21.033585 <30>[ 20.750919] systemd[1]: Listening on udev Kernel Socket.
10901 22:14:21.040152 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10902 22:14:21.089213 <30>[ 20.806834] systemd[1]: Mounting Huge Pages File System...
10903 22:14:21.096066 Mounting [0;1;39mHuge Pages File System[0m...
10904 22:14:21.111360 <30>[ 20.828835] systemd[1]: Mounting POSIX Message Queue File System...
10905 22:14:21.117804 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10906 22:14:21.135176 <30>[ 20.852881] systemd[1]: Mounting Kernel Debug File System...
10907 22:14:21.141829 Mounting [0;1;39mKernel Debug File System[0m...
10908 22:14:21.160651 <30>[ 20.874854] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10909 22:14:21.176585 <30>[ 20.891104] systemd[1]: Starting Create list of static device nodes for the current kernel...
10910 22:14:21.183232 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10911 22:14:21.241717 <30>[ 20.959038] systemd[1]: Starting Load Kernel Module configfs...
10912 22:14:21.247838 Starting [0;1;39mLoad Kernel Module configfs[0m...
10913 22:14:21.267797 <30>[ 20.985143] systemd[1]: Starting Load Kernel Module drm...
10914 22:14:21.274393 Starting [0;1;39mLoad Kernel Module drm[0m...
10915 22:14:21.291838 <30>[ 21.009340] systemd[1]: Starting Load Kernel Module fuse...
10916 22:14:21.298004 Starting [0;1;39mLoad Kernel Module fuse[0m...
10917 22:14:21.330537 <6>[ 21.048204] fuse: init (API version 7.37)
10918 22:14:21.340505 <30>[ 21.048528] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10919 22:14:21.369253 <30>[ 21.086959] systemd[1]: Starting Journal Service...
10920 22:14:21.373062 Starting [0;1;39mJournal Service[0m...
10921 22:14:21.397526 <30>[ 21.114964] systemd[1]: Starting Load Kernel Modules...
10922 22:14:21.403850 Starting [0;1;39mLoad Kernel Modules[0m...
10923 22:14:21.422946 <30>[ 21.137067] systemd[1]: Starting Remount Root and Kernel File Systems...
10924 22:14:21.428977 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10925 22:14:21.444976 <30>[ 21.162744] systemd[1]: Starting Coldplug All udev Devices...
10926 22:14:21.451549 Starting [0;1;39mColdplug All udev Devices[0m...
10927 22:14:21.473470 <30>[ 21.190918] systemd[1]: Mounted Huge Pages File System.
10928 22:14:21.480041 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10929 22:14:21.497497 <30>[ 21.215137] systemd[1]: Mounted POSIX Message Queue File System.
10930 22:14:21.503637 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10931 22:14:21.521487 <30>[ 21.238987] systemd[1]: Mounted Kernel Debug File System.
10932 22:14:21.531852 [[0;32m OK [<3>[ 21.245385] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10933 22:14:21.535307 0m] Mounted [0;1;39mKernel Debug File System[0m.
10934 22:14:21.561342 <30>[ 21.275514] systemd[1]: Finished Create list of static device nodes for the current kernel.
10935 22:14:21.571831 <3>[ 21.280811] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10936 22:14:21.578511 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10937 22:14:21.598765 <30>[ 21.315829] systemd[1]: modprobe@configfs.service: Succeeded.
10938 22:14:21.605582 <30>[ 21.322774] systemd[1]: Finished Load Kernel Module configfs.
10939 22:14:21.614921 <3>[ 21.327950] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10940 22:14:21.621163 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10941 22:14:21.638281 <30>[ 21.355861] systemd[1]: modprobe@drm.service: Succeeded.
10942 22:14:21.645202 <30>[ 21.362382] systemd[1]: Finished Load Kernel Module drm.
10943 22:14:21.651985 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10944 22:14:21.662070 <3>[ 21.376418] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10945 22:14:21.669914 <30>[ 21.387544] systemd[1]: modprobe@fuse.service: Succeeded.
10946 22:14:21.676489 <30>[ 21.394149] systemd[1]: Finished Load Kernel Module fuse.
10947 22:14:21.683080 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10948 22:14:21.703283 <30>[ 21.419992] systemd[1]: Finished Load Kernel Modules.
10949 22:14:21.712744 [[0;32m OK [<3>[ 21.426553] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10950 22:14:21.719054 0m] Finished [0;1;39mLoad Kernel Modules[0m.
10951 22:14:21.741367 <30>[ 21.455974] systemd[1]: Finished Remount Root and Kernel File Systems.
10952 22:14:21.751098 [[0;32m OK [0m] Finished [0<3>[ 21.465331] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10953 22:14:21.757657 ;1;39mRemount Root and Kernel File Systems[0m.
10954 22:14:21.783525 <3>[ 21.497762] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10955 22:14:21.808079 <30>[ 21.526188] systemd[1]: Mounting FUSE Control File System...
10956 22:14:21.817968 <3>[ 21.530853] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10957 22:14:21.824742 Mounting [0;1;39mFUSE Control File System[0m...
10958 22:14:21.839317 <30>[ 21.557176] systemd[1]: Mounting Kernel Configuration File System...
10959 22:14:21.849304 <3>[ 21.560230] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10960 22:14:21.856410 Mounting [0;1;39mKernel Configuration File System[0m...
10961 22:14:21.879852 <3>[ 21.593404] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10962 22:14:21.889386 <30>[ 21.596838] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10963 22:14:21.898601 <30>[ 21.611196] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10964 22:14:21.934181 <30>[ 21.651335] systemd[1]: Starting Load/Save Random Seed...
10965 22:14:21.940015 Starting [0;1;39mLoad/Save Random Seed[0m...
10966 22:14:21.955537 <30>[ 21.673721] systemd[1]: Starting Apply Kernel Variables...
10967 22:14:21.962467 Starting [0;1;39mApply Kernel Variables[0m...
10968 22:14:21.981233 <30>[ 21.698610] systemd[1]: Starting Create System Users...
10969 22:14:21.987189 Starting [0;1;39mCreate System Users[0m...
10970 22:14:22.007045 <30>[ 21.724950] systemd[1]: Started Journal Service.
10971 22:14:22.014176 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10972 22:14:22.039615 [[0;32m OK [0m] Mounted [0;<4>[ 21.746424] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10973 22:14:22.049552 1;39mFUSE Contro<3>[ 21.763083] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10974 22:14:22.049643 l File System[0m.
10975 22:14:22.069603 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10976 22:14:22.089899 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10977 22:14:22.101286 See 'systemctl status systemd-udev-trigger.service' for details.
10978 22:14:22.118541 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10979 22:14:22.134388 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10980 22:14:22.149939 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10981 22:14:22.201779 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10982 22:14:22.219522 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10983 22:14:22.259380 <46>[ 21.974154] systemd-journald[289]: Received client request to flush runtime journal.
10984 22:14:22.295239 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10985 22:14:22.309379 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10986 22:14:22.325090 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10987 22:14:22.376913 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10988 22:14:23.648010 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10989 22:14:23.685069 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10990 22:14:23.712743 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10991 22:14:23.736416 Starting [0;1;39mNetwork Service[0m...
10992 22:14:24.099446 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10993 22:14:24.117509 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10994 22:14:24.156850 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10995 22:14:24.269528 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10996 22:14:24.290550 <6>[ 24.008617] remoteproc remoteproc0: powering up scp
10997 22:14:24.315779 <4>[ 24.030234] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10998 22:14:24.322315 <3>[ 24.040151] remoteproc remoteproc0: request_firmware failed: -2
10999 22:14:24.332430 <3>[ 24.046335] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
11000 22:14:24.443868 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
11001 22:14:24.460538 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
11002 22:14:24.517294 Starting [0;1;39mNetwork Time Synchronization[0m...
11003 22:14:24.535340 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
11004 22:14:24.553764 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
11005 22:14:24.574279 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
11006 22:14:24.641193 Starting [0;1;39mNetwork Name Resolution[0m...
11007 22:14:24.660079 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
11008 22:14:24.677154 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
11009 22:14:24.693580 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
11010 22:14:24.713413 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
11011 22:14:24.734429 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
11012 22:14:24.753380 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
11013 22:14:24.770238 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
11014 22:14:25.486470 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
11015 22:14:25.516603 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
11016 22:14:25.835787 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
11017 22:14:25.858479 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
11018 22:14:25.876012 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
11019 22:14:25.888204 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
11020 22:14:25.914323 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
11021 22:14:25.932324 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
11022 22:14:25.952244 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
11023 22:14:25.992778 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
11024 22:14:26.125417 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
11025 22:14:26.240749 Starting [0;1;39mUser Login Management[0m...
11026 22:14:26.489123 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
11027 22:14:26.504268 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
11028 22:14:26.523784 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
11029 22:14:26.560539 Starting [0;1;39mPermit User Sessions[0m...
11030 22:14:26.581226 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
11031 22:14:26.613005 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11032 22:14:26.629659 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11033 22:14:26.665468 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11034 22:14:26.684226 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11035 22:14:26.700905 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11036 22:14:26.717062 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11037 22:14:26.732854 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11038 22:14:26.780830 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11039 22:14:26.853921 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11040 22:14:26.940257
11041 22:14:26.940813
11042 22:14:26.943160 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11043 22:14:26.943623
11044 22:14:26.946183 debian-bullseye-arm64 login: root (automatic login)
11045 22:14:26.946714
11046 22:14:26.947265
11047 22:14:27.265985 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Sun Jun 4 21:56:05 UTC 2023 aarch64
11048 22:14:27.266483
11049 22:14:27.272543 The programs included with the Debian GNU/Linux system are free software;
11050 22:14:27.279157 the exact distribution terms for each program are described in the
11051 22:14:27.282757 individual files in /usr/share/doc/*/copyright.
11052 22:14:27.283209
11053 22:14:27.289551 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11054 22:14:27.293101 permitted by applicable law.
11055 22:14:28.092459 Matched prompt #10: / #
11057 22:14:28.093605 Setting prompt string to ['/ #']
11058 22:14:28.094062 end: 2.2.5.1 login-action (duration 00:00:29) [common]
11060 22:14:28.095043 end: 2.2.5 auto-login-action (duration 00:00:29) [common]
11061 22:14:28.095546 start: 2.2.6 expect-shell-connection (timeout 00:03:38) [common]
11062 22:14:28.095909 Setting prompt string to ['/ #']
11063 22:14:28.096245 Forcing a shell prompt, looking for ['/ #']
11065 22:14:28.147168 / #
11066 22:14:28.147537 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11067 22:14:28.147828 Waiting using forced prompt support (timeout 00:02:30)
11068 22:14:28.152887
11069 22:14:28.153682 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11070 22:14:28.154101 start: 2.2.7 export-device-env (timeout 00:03:38) [common]
11072 22:14:28.255160 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10583852/extract-nfsrootfs-_32h7bf0'
11073 22:14:28.260323 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10583852/extract-nfsrootfs-_32h7bf0'
11075 22:14:28.361439 / # export NFS_SERVER_IP='192.168.201.1'
11076 22:14:28.368316 export NFS_SERVER_IP='192.168.201.1'
11077 22:14:28.369246 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11078 22:14:28.369796 end: 2.2 depthcharge-retry (duration 00:01:23) [common]
11079 22:14:28.370281 end: 2 depthcharge-action (duration 00:01:23) [common]
11080 22:14:28.370770 start: 3 lava-test-retry (timeout 00:07:57) [common]
11081 22:14:28.371279 start: 3.1 lava-test-shell (timeout 00:07:57) [common]
11082 22:14:28.371685 Using namespace: common
11084 22:14:28.473056 / # #
11085 22:14:28.473709 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11086 22:14:28.479932 #
11087 22:14:28.480819 Using /lava-10583852
11089 22:14:28.581994 / # export SHELL=/bin/bash
11090 22:14:28.588258 export SHELL=/bin/bash
11092 22:14:28.690124 / # . /lava-10583852/environment
11093 22:14:28.696945 . /lava-10583852/environment
11095 22:14:28.803897 / # /lava-10583852/bin/lava-test-runner /lava-10583852/0
11096 22:14:28.804548 Test shell timeout: 10s (minimum of the action and connection timeout)
11097 22:14:28.810079 /lava-10583852/bin/lava-test-runner /lava-10583852/0
11098 22:14:29.066282 + export TESTRUN_ID=0_timesync-off
11099 22:14:29.069452 + TESTRUN_ID=0_timesync-off
11100 22:14:29.072504 + cd /lava-10583852/0/tests/0_timesync-off
11101 22:14:29.076015 ++ cat uuid
11102 22:14:29.076095 + UUID=10583852_1.6.2.3.1
11103 22:14:29.078783 + set +x
11104 22:14:29.082810 <LAVA_SIGNAL_STARTRUN 0_timesync-off 10583852_1.6.2.3.1>
11105 22:14:29.083067 Received signal: <STARTRUN> 0_timesync-off 10583852_1.6.2.3.1
11106 22:14:29.083170 Starting test lava.0_timesync-off (10583852_1.6.2.3.1)
11107 22:14:29.083256 Skipping test definition patterns.
11108 22:14:29.085955 + systemctl stop systemd-timesyncd
11109 22:14:29.114484 + set +x
11110 22:14:29.117648 <LAVA_SIGNAL_ENDRUN 0_timesync-off 10583852_1.6.2.3.1>
11111 22:14:29.117906 Received signal: <ENDRUN> 0_timesync-off 10583852_1.6.2.3.1
11112 22:14:29.117992 Ending use of test pattern.
11113 22:14:29.118057 Ending test lava.0_timesync-off (10583852_1.6.2.3.1), duration 0.03
11115 22:14:29.185783 + export TESTRUN_ID=1_kselftest-arm64
11116 22:14:29.186247 + TESTRUN_ID=1_kselftest-arm64
11117 22:14:29.192640 + cd /lava-10583852/0/tests/1_kselftest-arm64
11118 22:14:29.193068 ++ cat uuid
11119 22:14:29.195842 + UUID=10583852_1.6.2.3.5
11120 22:14:29.196266 + set +x
11121 22:14:29.202476 <LAVA_SIGNAL_STARTRUN 1_kselftest-arm64 10583852_1.6.2.3.5>
11122 22:14:29.203168 Received signal: <STARTRUN> 1_kselftest-arm64 10583852_1.6.2.3.5
11123 22:14:29.203528 Starting test lava.1_kselftest-arm64 (10583852_1.6.2.3.5)
11124 22:14:29.203919 Skipping test definition patterns.
11125 22:14:29.206596 + cd ./automated/linux/kselftest/
11126 22:14:29.232671 + ./kselftest.sh -c arm64 -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1281-g84d5372e0f314/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11127 22:14:29.271405 INFO: install_deps skipped
11128 22:14:29.380272 --2023-06-04 22:14:29-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1281-g84d5372e0f314/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11129 22:14:29.401521 Resolving storage.kernelci.org (storage.kernelci.org)... 52.250.1.28
11130 22:14:29.542989 Connecting to storage.kernelci.org (storage.kernelci.org)|52.250.1.28|:80... connected.
11131 22:14:29.684020 HTTP request sent, awaiting response... 200 OK
11132 22:14:29.686647 Length: 2860264 (2.7M) [application/octet-stream]
11133 22:14:29.690001 Saving to: 'kselftest.tar.xz'
11134 22:14:29.690571
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11138 22:14:30.573864 kselftest.tar.xz 7%[> ] 217.50K 387KB/s
11139 22:14:30.864352 kselftest.tar.xz 28%[====> ] 808.57K 908KB/s
11140 22:14:30.992550 kselftest.tar.xz 69%[============> ] 1.90M 1.61MB/s
11141 22:14:30.999607 kselftest.tar.xz 100%[===================>] 2.73M 2.08MB/s in 1.3s
11142 22:14:30.999726
11143 22:14:31.246292 2023-06-04 22:14:31 (2.08 MB/s) - 'kselftest.tar.xz' saved [2860264/2860264]
11144 22:14:31.246433
11145 22:14:35.832199 skiplist:
11146 22:14:35.834729 ========================================
11147 22:14:35.838246 ========================================
11148 22:14:35.871040 arm64:tags_test
11149 22:14:35.874968 arm64:run_tags_test.sh
11150 22:14:35.875085 arm64:fake_sigreturn_bad_magic
11151 22:14:35.878363 arm64:fake_sigreturn_bad_size
11152 22:14:35.881072 arm64:fake_sigreturn_bad_size_for_magic0
11153 22:14:35.884486 arm64:fake_sigreturn_duplicated_fpsimd
11154 22:14:35.887441 arm64:fake_sigreturn_misaligned_sp
11155 22:14:35.891188 arm64:fake_sigreturn_missing_fpsimd
11156 22:14:35.894267 arm64:fake_sigreturn_sme_change_vl
11157 22:14:35.897155 arm64:fake_sigreturn_sve_change_vl
11158 22:14:35.900936 arm64:mangle_pstate_invalid_compat_toggle
11159 22:14:35.904546 arm64:mangle_pstate_invalid_daif_bits
11160 22:14:35.907047 arm64:mangle_pstate_invalid_mode_el1h
11161 22:14:35.910968 arm64:mangle_pstate_invalid_mode_el1t
11162 22:14:35.914491 arm64:mangle_pstate_invalid_mode_el2h
11163 22:14:35.917139 arm64:mangle_pstate_invalid_mode_el2t
11164 22:14:35.920366 arm64:mangle_pstate_invalid_mode_el3h
11165 22:14:35.927362 arm64:mangle_pstate_invalid_mode_el3t
11166 22:14:35.927443 arm64:sme_trap_no_sm
11167 22:14:35.930178 arm64:sme_trap_non_streaming
11168 22:14:35.930260 arm64:sme_trap_za
11169 22:14:35.933985 arm64:sme_vl
11170 22:14:35.934066 arm64:ssve_regs
11171 22:14:35.937200 arm64:sve_regs
11172 22:14:35.937281 arm64:sve_vl
11173 22:14:35.937345 arm64:za_no_regs
11174 22:14:35.940096 arm64:za_regs
11175 22:14:35.940169 arm64:pac
11176 22:14:35.943425 arm64:fp-stress
11177 22:14:35.943499 arm64:sve-ptrace
11178 22:14:35.947495 arm64:sve-probe-vls
11179 22:14:35.947571 arm64:vec-syscfg
11180 22:14:35.947633 arm64:za-fork
11181 22:14:35.949825 arm64:za-ptrace
11182 22:14:35.953618 arm64:check_buffer_fill
11183 22:14:35.953728 arm64:check_child_memory
11184 22:14:35.956906 arm64:check_gcr_el1_cswitch
11185 22:14:35.959961 arm64:check_ksm_options
11186 22:14:35.960041 arm64:check_mmap_options
11187 22:14:35.963580 arm64:check_prctl
11188 22:14:35.966902 arm64:check_tags_inclusion
11189 22:14:35.966984 arm64:check_user_mem
11190 22:14:35.969658 arm64:btitest
11191 22:14:35.969739 arm64:nobtitest
11192 22:14:35.969803 arm64:hwcap
11193 22:14:35.973235 arm64:ptrace
11194 22:14:35.973315 arm64:syscall-abi
11195 22:14:35.977256 arm64:tpidr2
11196 22:14:35.980453 ============== Tests to run ===============
11197 22:14:35.980534 arm64:tags_test
11198 22:14:35.982990 arm64:run_tags_test.sh
11199 22:14:35.986874 arm64:fake_sigreturn_bad_magic
11200 22:14:35.989794 arm64:fake_sigreturn_bad_size
11201 22:14:35.993396 arm64:fake_sigreturn_bad_size_for_magic0
11202 22:14:35.996242 arm64:fake_sigreturn_duplicated_fpsimd
11203 22:14:35.999635 arm64:fake_sigreturn_misaligned_sp
11204 22:14:36.003265 arm64:fake_sigreturn_missing_fpsimd
11205 22:14:36.006186 arm64:fake_sigreturn_sme_change_vl
11206 22:14:36.006267 arm64:fake_sigreturn_sve_change_vl
11207 22:14:36.012681 arm64:mangle_pstate_invalid_compat_toggle
11208 22:14:36.016791 arm64:mangle_pstate_invalid_daif_bits
11209 22:14:36.019735 arm64:mangle_pstate_invalid_mode_el1h
11210 22:14:36.022935 arm64:mangle_pstate_invalid_mode_el1t
11211 22:14:36.026303 arm64:mangle_pstate_invalid_mode_el2h
11212 22:14:36.029363 arm64:mangle_pstate_invalid_mode_el2t
11213 22:14:36.032707 arm64:mangle_pstate_invalid_mode_el3h
11214 22:14:36.036033 arm64:mangle_pstate_invalid_mode_el3t
11215 22:14:36.036116 arm64:sme_trap_no_sm
11216 22:14:36.038974 arm64:sme_trap_non_streaming
11217 22:14:36.042571 arm64:sme_trap_za
11218 22:14:36.042666 arm64:sme_vl
11219 22:14:36.042732 arm64:ssve_regs
11220 22:14:36.046035 arm64:sve_regs
11221 22:14:36.046116 arm64:sve_vl
11222 22:14:36.049413 arm64:za_no_regs
11223 22:14:36.049494 arm64:za_regs
11224 22:14:36.049558 arm64:pac
11225 22:14:36.052554 arm64:fp-stress
11226 22:14:36.052635 arm64:sve-ptrace
11227 22:14:36.055913 arm64:sve-probe-vls
11228 22:14:36.055994 arm64:vec-syscfg
11229 22:14:36.059114 arm64:za-fork
11230 22:14:36.059196 arm64:za-ptrace
11231 22:14:36.062596 arm64:check_buffer_fill
11232 22:14:36.065769 arm64:check_child_memory
11233 22:14:36.065851 arm64:check_gcr_el1_cswitch
11234 22:14:36.068853 arm64:check_ksm_options
11235 22:14:36.072551 arm64:check_mmap_options
11236 22:14:36.072634 arm64:check_prctl
11237 22:14:36.075319 arm64:check_tags_inclusion
11238 22:14:36.075400 arm64:check_user_mem
11239 22:14:36.078779 arm64:btitest
11240 22:14:36.078860 arm64:nobtitest
11241 22:14:36.082120 arm64:hwcap
11242 22:14:36.082201 arm64:ptrace
11243 22:14:36.085536 arm64:syscall-abi
11244 22:14:36.085617 arm64:tpidr2
11245 22:14:36.088539 ===========End Tests to run ===============
11246 22:14:36.240709 <12>[ 35.960253] kselftest: Running tests in arm64
11247 22:14:36.249519 TAP version 13
11248 22:14:36.260187 1..48
11249 22:14:36.274503 # selftests: arm64: tags_test
11250 22:14:36.631574 ok 1 selftests: arm64: tags_test
11251 22:14:36.645018 # selftests: arm64: run_tags_test.sh
11252 22:14:36.690848 # --------------------
11253 22:14:36.694220 # running tags test
11254 22:14:36.694308 # --------------------
11255 22:14:36.698549 # [PASS]
11256 22:14:36.700651 ok 2 selftests: arm64: run_tags_test.sh
11257 22:14:36.712963 # selftests: arm64: fake_sigreturn_bad_magic
11258 22:14:36.758993 # Registered handlers for all signals.
11259 22:14:36.759176 # Detected MINSTKSIGSZ:4720
11260 22:14:36.762751 # Testcase initialized.
11261 22:14:36.766065 # uc context validated.
11262 22:14:36.769112 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11263 22:14:36.773137 # Handled SIG_COPYCTX
11264 22:14:36.773220 # Available space:3568
11265 22:14:36.779180 # Using badly built context - ERR: BAD MAGIC !
11266 22:14:36.785586 # SIG_OK -- SP:0xFFFFDBE30C90 si_addr@:0xffffdbe30c90 si_code:2 token@:0xffffdbe2fa30 offset:-4704
11267 22:14:36.789042 # ==>> completed. PASS(1)
11268 22:14:36.796481 # # FAKE_SIGRETURN_BAD_MAGIC :: Trigger a sigreturn with a sigframe with a bad magic
11269 22:14:36.802161 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFDBE2FA30
11270 22:14:36.808696 ok 3 selftests: arm64: fake_sigreturn_bad_magic
11271 22:14:36.812058 # selftests: arm64: fake_sigreturn_bad_size
11272 22:14:36.822330 # Registered handlers for all signals.
11273 22:14:36.822415 # Detected MINSTKSIGSZ:4720
11274 22:14:36.825448 # Testcase initialized.
11275 22:14:36.828766 # uc context validated.
11276 22:14:36.831756 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11277 22:14:36.835067 # Handled SIG_COPYCTX
11278 22:14:36.835165 # Available space:3568
11279 22:14:36.838689 # uc context validated.
11280 22:14:36.845408 # Using badly built context - ERR: Bad size for esr_context
11281 22:14:36.852065 # SIG_OK -- SP:0xFFFFE76E67A0 si_addr@:0xffffe76e67a0 si_code:2 token@:0xffffe76e5540 offset:-4704
11282 22:14:36.854962 # ==>> completed. PASS(1)
11283 22:14:36.861464 # # FAKE_SIGRETURN_BAD_SIZE :: Triggers a sigreturn with a overrun __reserved area
11284 22:14:36.867863 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFE76E5540
11285 22:14:36.871636 ok 4 selftests: arm64: fake_sigreturn_bad_size
11286 22:14:36.878060 # selftests: arm64: fake_sigreturn_bad_size_for_magic0
11287 22:14:36.885805 # Registered handlers for all signals.
11288 22:14:36.885915 # Detected MINSTKSIGSZ:4720
11289 22:14:36.889103 # Testcase initialized.
11290 22:14:36.892676 # uc context validated.
11291 22:14:36.895743 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11292 22:14:36.898849 # Handled SIG_COPYCTX
11293 22:14:36.898925 # Available space:3568
11294 22:14:36.905513 # Using badly built context - ERR: Bad size for terminator
11295 22:14:36.915417 # SIG_OK -- SP:0xFFFFFA7B77F0 si_addr@:0xfffffa7b77f0 si_code:2 token@:0xfffffa7b6590 offset:-4704
11296 22:14:36.915498 # ==>> completed. PASS(1)
11297 22:14:36.925198 # # FAKE_SIGRETURN_BAD_SIZE_FOR_TERMINATOR :: Trigger a sigreturn using non-zero size terminator
11298 22:14:36.931891 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFFA7B6590
11299 22:14:36.935308 ok 5 selftests: arm64: fake_sigreturn_bad_size_for_magic0
11300 22:14:36.941472 # selftests: arm64: fake_sigreturn_duplicated_fpsimd
11301 22:14:36.948633 # Registered handlers for all signals.
11302 22:14:36.948718 # Detected MINSTKSIGSZ:4720
11303 22:14:36.952542 # Testcase initialized.
11304 22:14:36.955985 # uc context validated.
11305 22:14:36.958976 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11306 22:14:36.962001 # Handled SIG_COPYCTX
11307 22:14:36.962109 # Available space:3568
11308 22:14:36.968868 # Using badly built context - ERR: Multiple FPSIMD_MAGIC
11309 22:14:36.978990 # SIG_OK -- SP:0xFFFFDE6E2240 si_addr@:0xffffde6e2240 si_code:2 token@:0xffffde6e0fe0 offset:-4704
11310 22:14:36.979113 # ==>> completed. PASS(1)
11311 22:14:36.988739 # # FAKE_SIGRETURN_DUPLICATED_FPSIMD :: Triggers a sigreturn including two fpsimd_context
11312 22:14:36.995810 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFDE6E0FE0
11313 22:14:36.998506 ok 6 selftests: arm64: fake_sigreturn_duplicated_fpsimd
11314 22:14:37.001811 # selftests: arm64: fake_sigreturn_misaligned_sp
11315 22:14:37.010751 # Registered handlers for all signals.
11316 22:14:37.010850 # Detected MINSTKSIGSZ:4720
11317 22:14:37.014608 # Testcase initialized.
11318 22:14:37.017476 # uc context validated.
11319 22:14:37.021212 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11320 22:14:37.024790 # Handled SIG_COPYCTX
11321 22:14:37.030739 # SIG_OK -- SP:0xFFFFF74BE6B3 si_addr@:0xfffff74be6b3 si_code:2 token@:0xfffff74be6b3 offset:0
11322 22:14:37.034097 # ==>> completed. PASS(1)
11323 22:14:37.040680 # # FAKE_SIGRETURN_MISALIGNED_SP :: Triggers a sigreturn with a misaligned sigframe
11324 22:14:37.047384 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFF74BE6B3
11325 22:14:37.053539 ok 7 selftests: arm64: fake_sigreturn_misaligned_sp
11326 22:14:37.056630 # selftests: arm64: fake_sigreturn_missing_fpsimd
11327 22:14:37.074074 # Registered handlers for all signals.
11328 22:14:37.074162 # Detected MINSTKSIGSZ:4720
11329 22:14:37.076948 # Testcase initialized.
11330 22:14:37.080371 # uc context validated.
11331 22:14:37.083627 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11332 22:14:37.086820 # Handled SIG_COPYCTX
11333 22:14:37.090088 # Mangling template header. Spare space:4096
11334 22:14:37.093323 # Using badly built context - ERR: Missing FPSIMD
11335 22:14:37.104060 # SIG_OK -- SP:0xFFFFDD998070 si_addr@:0xffffdd998070 si_code:2 token@:0xffffdd996e10 offset:-4704
11336 22:14:37.106703 # ==>> completed. PASS(1)
11337 22:14:37.112948 # # FAKE_SIGRETURN_MISSING_FPSIMD :: Triggers a sigreturn with a missing fpsimd_context
11338 22:14:37.119965 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFDD996E10
11339 22:14:37.122918 ok 8 selftests: arm64: fake_sigreturn_missing_fpsimd
11340 22:14:37.130053 # selftests: arm64: fake_sigreturn_sme_change_vl
11341 22:14:37.138021 # Registered handlers for all signals.
11342 22:14:37.138104 # Detected MINSTKSIGSZ:4720
11343 22:14:37.141369 # ==>> completed. SKIP.
11344 22:14:37.148102 # # FAKE_SIGRETURN_SSVE_CHANGE :: Attempt to change Streaming SVE VL
11345 22:14:37.150992 ok 9 selftests: arm64: fake_sigreturn_sme_change_vl # SKIP
11346 22:14:37.158056 # selftests: arm64: fake_sigreturn_sve_change_vl
11347 22:14:37.200578 # Registered handlers for all signals.
11348 22:14:37.200698 # Detected MINSTKSIGSZ:4720
11349 22:14:37.204263 # ==>> completed. SKIP.
11350 22:14:37.210201 # # FAKE_SIGRETURN_SVE_CHANGE :: Attempt to change SVE VL
11351 22:14:37.213435 ok 10 selftests: arm64: fake_sigreturn_sve_change_vl # SKIP
11352 22:14:37.219861 # selftests: arm64: mangle_pstate_invalid_compat_toggle
11353 22:14:37.263307 # Registered handlers for all signals.
11354 22:14:37.263439 # Detected MINSTKSIGSZ:4720
11355 22:14:37.267015 # Testcase initialized.
11356 22:14:37.269774 # uc context validated.
11357 22:14:37.269880 # Handled SIG_TRIG
11358 22:14:37.280055 # SIG_OK -- SP:0xFFFFDD98E780 si_addr@:0xffffdd98e780 si_code:2 token@:(nil) offset:-281474399528832
11359 22:14:37.282996 # ==>> completed. PASS(1)
11360 22:14:37.289993 # # MANGLE_PSTATE_INVALID_STATE_TOGGLE :: Mangling uc_mcontext with INVALID STATE_TOGGLE
11361 22:14:37.296866 ok 11 selftests: arm64: mangle_pstate_invalid_compat_toggle
11362 22:14:37.299999 # selftests: arm64: mangle_pstate_invalid_daif_bits
11363 22:14:37.325473 # Registered handlers for all signals.
11364 22:14:37.325617 # Detected MINSTKSIGSZ:4720
11365 22:14:37.328247 # Testcase initialized.
11366 22:14:37.332247 # uc context validated.
11367 22:14:37.332361 # Handled SIG_TRIG
11368 22:14:37.341971 # SIG_OK -- SP:0xFFFFE23BB580 si_addr@:0xffffe23bb580 si_code:2 token@:(nil) offset:-281474477307264
11369 22:14:37.344789 # ==>> completed. PASS(1)
11370 22:14:37.352110 # # MANGLE_PSTATE_INVALID_DAIF_BITS :: Mangling uc_mcontext with INVALID DAIF_BITS
11371 22:14:37.354750 ok 12 selftests: arm64: mangle_pstate_invalid_daif_bits
11372 22:14:37.361472 # selftests: arm64: mangle_pstate_invalid_mode_el1h
11373 22:14:37.389215 # Registered handlers for all signals.
11374 22:14:37.389322 # Detected MINSTKSIGSZ:4720
11375 22:14:37.391780 # Testcase initialized.
11376 22:14:37.395289 # uc context validated.
11377 22:14:37.395372 # Handled SIG_TRIG
11378 22:14:37.405312 # SIG_OK -- SP:0xFFFFD8E99630 si_addr@:0xffffd8e99630 si_code:2 token@:(nil) offset:-281474320930352
11379 22:14:37.408967 # ==>> completed. PASS(1)
11380 22:14:37.415027 # # MANGLE_PSTATE_INVALID_MODE_EL1h :: Mangling uc_mcontext INVALID MODE EL1h
11381 22:14:37.418512 ok 13 selftests: arm64: mangle_pstate_invalid_mode_el1h
11382 22:14:37.424910 # selftests: arm64: mangle_pstate_invalid_mode_el1t
11383 22:14:37.454486 # Registered handlers for all signals.
11384 22:14:37.454613 # Detected MINSTKSIGSZ:4720
11385 22:14:37.457373 # Testcase initialized.
11386 22:14:37.460853 # uc context validated.
11387 22:14:37.460936 # Handled SIG_TRIG
11388 22:14:37.470650 # SIG_OK -- SP:0xFFFFE4D18FA0 si_addr@:0xffffe4d18fa0 si_code:2 token@:(nil) offset:-281474520682400
11389 22:14:37.474364 # ==>> completed. PASS(1)
11390 22:14:37.480996 # # MANGLE_PSTATE_INVALID_MODE_EL1t :: Mangling uc_mcontext INVALID MODE EL1t
11391 22:14:37.484109 ok 14 selftests: arm64: mangle_pstate_invalid_mode_el1t
11392 22:14:37.490255 # selftests: arm64: mangle_pstate_invalid_mode_el2h
11393 22:14:37.517846 # Registered handlers for all signals.
11394 22:14:37.517940 # Detected MINSTKSIGSZ:4720
11395 22:14:37.521389 # Testcase initialized.
11396 22:14:37.524463 # uc context validated.
11397 22:14:37.524545 # Handled SIG_TRIG
11398 22:14:37.534509 # SIG_OK -- SP:0xFFFFCA95E5F0 si_addr@:0xffffca95e5f0 si_code:2 token@:(nil) offset:-281474080564720
11399 22:14:37.537423 # ==>> completed. PASS(1)
11400 22:14:37.544352 # # MANGLE_PSTATE_INVALID_MODE_EL2h :: Mangling uc_mcontext INVALID MODE EL2h
11401 22:14:37.547725 ok 15 selftests: arm64: mangle_pstate_invalid_mode_el2h
11402 22:14:37.553992 # selftests: arm64: mangle_pstate_invalid_mode_el2t
11403 22:14:37.580697 # Registered handlers for all signals.
11404 22:14:37.580796 # Detected MINSTKSIGSZ:4720
11405 22:14:37.583662 # Testcase initialized.
11406 22:14:37.587288 # uc context validated.
11407 22:14:37.587370 # Handled SIG_TRIG
11408 22:14:37.597150 # SIG_OK -- SP:0xFFFFC67BDF50 si_addr@:0xffffc67bdf50 si_code:2 token@:(nil) offset:-281474011750224
11409 22:14:37.600558 # ==>> completed. PASS(1)
11410 22:14:37.607544 # # MANGLE_PSTATE_INVALID_MODE_EL2t :: Mangling uc_mcontext INVALID MODE EL2t
11411 22:14:37.610255 ok 16 selftests: arm64: mangle_pstate_invalid_mode_el2t
11412 22:14:37.617056 # selftests: arm64: mangle_pstate_invalid_mode_el3h
11413 22:14:37.640892 # Registered handlers for all signals.
11414 22:14:37.640984 # Detected MINSTKSIGSZ:4720
11415 22:14:37.643810 # Testcase initialized.
11416 22:14:37.647062 # uc context validated.
11417 22:14:37.647160 # Handled SIG_TRIG
11418 22:14:37.657096 # SIG_OK -- SP:0xFFFFDC1A10E0 si_addr@:0xffffdc1a10e0 si_code:2 token@:(nil) offset:-281474374439136
11419 22:14:37.660082 # ==>> completed. PASS(1)
11420 22:14:37.667191 # # MANGLE_PSTATE_INVALID_MODE_EL3h :: Mangling uc_mcontext INVALID MODE EL3h
11421 22:14:37.670148 ok 17 selftests: arm64: mangle_pstate_invalid_mode_el3h
11422 22:14:37.676686 # selftests: arm64: mangle_pstate_invalid_mode_el3t
11423 22:14:37.703027 # Registered handlers for all signals.
11424 22:14:37.703167 # Detected MINSTKSIGSZ:4720
11425 22:14:37.705996 # Testcase initialized.
11426 22:14:37.709588 # uc context validated.
11427 22:14:37.709676 # Handled SIG_TRIG
11428 22:14:37.719236 # SIG_OK -- SP:0xFFFFC1242380 si_addr@:0xffffc1242380 si_code:2 token@:(nil) offset:-281473922114432
11429 22:14:37.722777 # ==>> completed. PASS(1)
11430 22:14:37.729352 # # MANGLE_PSTATE_INVALID_MODE_EL3t :: Mangling uc_mcontext INVALID MODE EL3t
11431 22:14:37.732491 ok 18 selftests: arm64: mangle_pstate_invalid_mode_el3t
11432 22:14:37.735651 # selftests: arm64: sme_trap_no_sm
11433 22:14:37.765751 # Registered handlers for all signals.
11434 22:14:37.765854 # Detected MINSTKSIGSZ:4720
11435 22:14:37.769301 # ==>> completed. SKIP.
11436 22:14:37.779590 # # SME trap without SM :: Check that we get a SIGILL if we use streaming mode without enabling it
11437 22:14:37.781777 ok 19 selftests: arm64: sme_trap_no_sm # SKIP
11438 22:14:37.785137 # selftests: arm64: sme_trap_non_streaming
11439 22:14:37.829856 # Registered handlers for all signals.
11440 22:14:37.829972 # Detected MINSTKSIGSZ:4720
11441 22:14:37.833571 # ==>> completed. SKIP.
11442 22:14:37.843503 # # SME SM trap unsupported instruction :: Check that we get a SIGILL if we use an unsupported instruction in streaming mode
11443 22:14:37.849554 ok 20 selftests: arm64: sme_trap_non_streaming # SKIP
11444 22:14:37.852739 # selftests: arm64: sme_trap_za
11445 22:14:37.892841 # Registered handlers for all signals.
11446 22:14:37.892959 # Detected MINSTKSIGSZ:4720
11447 22:14:37.895706 # Testcase initialized.
11448 22:14:37.905401 # SIG_OK -- SP:0xFFFFC0EB7050 si_addr@:0xaaaaac652510 si_code:1 token@:(nil) offset:-187650013472016
11449 22:14:37.905511 # ==>> completed. PASS(1)
11450 22:14:37.915719 # # SME ZA trap :: Check that we get a SIGILL if we access ZA without enabling
11451 22:14:37.918887 ok 21 selftests: arm64: sme_trap_za
11452 22:14:37.918990 # selftests: arm64: sme_vl
11453 22:14:37.957075 # Registered handlers for all signals.
11454 22:14:37.957183 # Detected MINSTKSIGSZ:4720
11455 22:14:37.959691 # ==>> completed. SKIP.
11456 22:14:37.967089 # # SME VL :: Check that we get the right SME VL reported
11457 22:14:37.969528 ok 22 selftests: arm64: sme_vl # SKIP
11458 22:14:37.969603 # selftests: arm64: ssve_regs
11459 22:14:38.020314 # Registered handlers for all signals.
11460 22:14:38.020434 # Detected MINSTKSIGSZ:4720
11461 22:14:38.023217 # ==>> completed. SKIP.
11462 22:14:38.029959 # # Streaming SVE registers :: Check that we get the right Streaming SVE registers reported
11463 22:14:38.036093 ok 23 selftests: arm64: ssve_regs # SKIP
11464 22:14:38.036177 # selftests: arm64: sve_regs
11465 22:14:38.084011 # Registered handlers for all signals.
11466 22:14:38.084132 # Detected MINSTKSIGSZ:4720
11467 22:14:38.087016 # ==>> completed. SKIP.
11468 22:14:38.093842 # # SVE registers :: Check that we get the right SVE registers reported
11469 22:14:38.097232 ok 24 selftests: arm64: sve_regs # SKIP
11470 22:14:38.100190 # selftests: arm64: sve_vl
11471 22:14:38.147615 # Registered handlers for all signals.
11472 22:14:38.147749 # Detected MINSTKSIGSZ:4720
11473 22:14:38.150618 # ==>> completed. SKIP.
11474 22:14:38.156949 # # SVE VL :: Check that we get the right SVE VL reported
11475 22:14:38.161264 ok 25 selftests: arm64: sve_vl # SKIP
11476 22:14:38.161367 # selftests: arm64: za_no_regs
11477 22:14:38.209020 # Registered handlers for all signals.
11478 22:14:38.209160 # Detected MINSTKSIGSZ:4720
11479 22:14:38.212454 # ==>> completed. SKIP.
11480 22:14:38.219061 # # ZA registers - ZA disabled :: Check ZA context with ZA disabled
11481 22:14:38.222717 ok 26 selftests: arm64: za_no_regs # SKIP
11482 22:14:38.226287 # selftests: arm64: za_regs
11483 22:14:38.271941 # Registered handlers for all signals.
11484 22:14:38.272069 # Detected MINSTKSIGSZ:4720
11485 22:14:38.275025 # ==>> completed. SKIP.
11486 22:14:38.281864 # # ZA register :: Check that we get the right ZA registers reported
11487 22:14:38.284999 ok 27 selftests: arm64: za_regs # SKIP
11488 22:14:38.288404 # selftests: arm64: pac
11489 22:14:38.331817 # TAP version 13
11490 22:14:38.331953 # 1..7
11491 22:14:38.335045 # # Starting 7 tests from 1 test cases.
11492 22:14:38.338467 # # RUN global.corrupt_pac ...
11493 22:14:38.341853 # # SKIP PAUTH not enabled
11494 22:14:38.345097 # # OK global.corrupt_pac
11495 22:14:38.349028 # ok 1 # SKIP PAUTH not enabled
11496 22:14:38.354699 # # RUN global.pac_instructions_not_nop ...
11497 22:14:38.358136 # # SKIP PAUTH not enabled
11498 22:14:38.361754 # # OK global.pac_instructions_not_nop
11499 22:14:38.364625 # ok 2 # SKIP PAUTH not enabled
11500 22:14:38.371563 # # RUN global.pac_instructions_not_nop_generic ...
11501 22:14:38.374654 # # SKIP Generic PAUTH not enabled
11502 22:14:38.378133 # # OK global.pac_instructions_not_nop_generic
11503 22:14:38.384766 # ok 3 # SKIP Generic PAUTH not enabled
11504 22:14:38.387845 # # RUN global.single_thread_different_keys ...
11505 22:14:38.391320 # # SKIP PAUTH not enabled
11506 22:14:38.397808 # # OK global.single_thread_different_keys
11507 22:14:38.397899 # ok 4 # SKIP PAUTH not enabled
11508 22:14:38.404448 # # RUN global.exec_changed_keys ...
11509 22:14:38.408286 # # SKIP PAUTH not enabled
11510 22:14:38.410767 # # OK global.exec_changed_keys
11511 22:14:38.414507 # ok 5 # SKIP PAUTH not enabled
11512 22:14:38.417808 # # RUN global.context_switch_keep_keys ...
11513 22:14:38.420910 # # SKIP PAUTH not enabled
11514 22:14:38.428158 # # OK global.context_switch_keep_keys
11515 22:14:38.428241 # ok 6 # SKIP PAUTH not enabled
11516 22:14:38.434558 # # RUN global.context_switch_keep_keys_generic ...
11517 22:14:38.437665 # # SKIP Generic PAUTH not enabled
11518 22:14:38.443918 # # OK global.context_switch_keep_keys_generic
11519 22:14:38.447273 # ok 7 # SKIP Generic PAUTH not enabled
11520 22:14:38.450558 # # PASSED: 7 / 7 tests passed.
11521 22:14:38.453773 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:7 error:0
11522 22:14:38.457701 ok 28 selftests: arm64: pac
11523 22:14:38.460378 # selftests: arm64: fp-stress
11524 22:14:46.430743 <6>[ 46.154443] vpu: disabling
11525 22:14:46.434094 <6>[ 46.157505] vproc2: disabling
11526 22:14:46.437636 <6>[ 46.160783] vproc1: disabling
11527 22:14:46.440282 <6>[ 46.164062] vaud18: disabling
11528 22:14:46.447109 <6>[ 46.167548] vsram_others: disabling
11529 22:14:46.450227 <6>[ 46.171475] va09: disabling
11530 22:14:46.453316 <6>[ 46.174610] vsram_md: disabling
11531 22:14:46.456550 <6>[ 46.178129] Vgpu: disabling
11532 22:14:48.411886 # TAP version 13
11533 22:14:48.412458 # 1..16
11534 22:14:48.415774 # # 8 CPUs, 0 SVE VLs, 0 SME VLs
11535 22:14:48.418211 # # Will run for 10s
11536 22:14:48.418671 # # Started FPSIMD-0-0
11537 22:14:48.421739 # # Started FPSIMD-0-1
11538 22:14:48.425636 # # Started FPSIMD-1-0
11539 22:14:48.426098 # # Started FPSIMD-1-1
11540 22:14:48.428348 # # Started FPSIMD-2-0
11541 22:14:48.428932 # # Started FPSIMD-2-1
11542 22:14:48.431819 # # Started FPSIMD-3-0
11543 22:14:48.434927 # # Started FPSIMD-3-1
11544 22:14:48.435441 # # Started FPSIMD-4-0
11545 22:14:48.438447 # # Started FPSIMD-4-1
11546 22:14:48.441187 # # Started FPSIMD-5-0
11547 22:14:48.441647 # # Started FPSIMD-5-1
11548 22:14:48.445018 # # Started FPSIMD-6-0
11549 22:14:48.448745 # # Started FPSIMD-6-1
11550 22:14:48.449225 # # Started FPSIMD-7-0
11551 22:14:48.451254 # # Started FPSIMD-7-1
11552 22:14:48.454896 # # FPSIMD-0-0: Vector length: 128 bits
11553 22:14:48.458010 # # FPSIMD-0-0: PID: 1131
11554 22:14:48.461519 # # FPSIMD-0-1: Vector length: 128 bits
11555 22:14:48.462047 # # FPSIMD-0-1: PID: 1132
11556 22:14:48.464642 # # FPSIMD-3-0: Vector length: 128 bits
11557 22:14:48.467640 # # FPSIMD-3-0: PID: 1137
11558 22:14:48.471228 # # FPSIMD-4-0: Vector length: 128 bits
11559 22:14:48.474520 # # FPSIMD-4-0: PID: 1139
11560 22:14:48.478348 # # FPSIMD-4-1: Vector length: 128 bits
11561 22:14:48.480825 # # FPSIMD-4-1: PID: 1140
11562 22:14:48.484351 # # FPSIMD-1-0: Vector length: 128 bits
11563 22:14:48.487752 # # FPSIMD-1-0: PID: 1133
11564 22:14:48.490805 # # FPSIMD-1-1: Vector length: 128 bits
11565 22:14:48.493902 # # FPSIMD-6-0: Vector length: 128 bits
11566 22:14:48.494319 # # FPSIMD-6-0: PID: 1143
11567 22:14:48.497752 # # FPSIMD-1-1: PID: 1134
11568 22:14:48.500603 # # FPSIMD-3-1: Vector length: 128 bits
11569 22:14:48.503766 # # FPSIMD-3-1: PID: 1138
11570 22:14:48.507463 # # FPSIMD-2-1: Vector length: 128 bits
11571 22:14:48.510511 # # FPSIMD-2-1: PID: 1136
11572 22:14:48.513950 # # FPSIMD-5-1: Vector length: 128 bits
11573 22:14:48.514377 # # FPSIMD-5-1: PID: 1142
11574 22:14:48.520802 # # FPSIMD-7-1: Vector length: 128 bits
11575 22:14:48.521225 # # FPSIMD-7-1: PID: 1146
11576 22:14:48.523781 # # FPSIMD-2-0: Vector length: 128 bits
11577 22:14:48.527588 # # FPSIMD-2-0: PID: 1135
11578 22:14:48.530715 # # FPSIMD-7-0: Vector length: 128 bits
11579 22:14:48.533726 # # FPSIMD-7-0: PID: 1145
11580 22:14:48.537432 # # FPSIMD-5-0: Vector length: 128 bits
11581 22:14:48.540664 # # FPSIMD-5-0: PID: 1141
11582 22:14:48.543744 # # FPSIMD-6-1: Vector length: 128 bits
11583 22:14:48.544164 # # FPSIMD-6-1: PID: 1144
11584 22:14:48.546684 # # Finishing up...
11585 22:14:48.553862 # # FPSIMD-0-0: Terminated by signal 15, no error, iterations=1085093, signals=10
11586 22:14:48.561129 # # FPSIMD-0-1: Terminated by signal 15, no error, iterations=1702653, signals=10
11587 22:14:48.567141 # # FPSIMD-1-0: Terminated by signal 15, no error, iterations=508660, signals=10
11588 22:14:48.576706 # # FPSIMD-2-1: Terminated by signal 15, no error, iterations=627264, signals=10
11589 22:14:48.583665 # # FPSIMD-3-0: Terminated by signal 15, no error, iterations=1189652, signals=10
11590 22:14:48.589829 # # FPSIMD-5-0: Terminated by signal 15, no error, iterations=490631, signals=10
11591 22:14:48.596205 # # FPSIMD-6-0: Terminated by signal 15, no error, iterations=648075, signals=9
11592 22:14:48.599916 # ok 1 FPSIMD-0-0
11593 22:14:48.600334 # ok 2 FPSIMD-0-1
11594 22:14:48.603024 # ok 3 FPSIMD-1-0
11595 22:14:48.603486 # ok 4 FPSIMD-1-1
11596 22:14:48.606612 # ok 5 FPSIMD-2-0
11597 22:14:48.607212 # ok 6 FPSIMD-2-1
11598 22:14:48.609415 # ok 7 FPSIMD-3-0
11599 22:14:48.609831 # ok 8 FPSIMD-3-1
11600 22:14:48.612715 # ok 9 FPSIMD-4-0
11601 22:14:48.613128 # ok 10 FPSIMD-4-1
11602 22:14:48.616441 # ok 11 FPSIMD-5-0
11603 22:14:48.616854 # ok 12 FPSIMD-5-1
11604 22:14:48.619683 # ok 13 FPSIMD-6-0
11605 22:14:48.620096 # ok 14 FPSIMD-6-1
11606 22:14:48.622874 # ok 15 FPSIMD-7-0
11607 22:14:48.623317 # ok 16 FPSIMD-7-1
11608 22:14:48.630029 # # FPSIMD-1-1: Terminated by signal 15, no error, iterations=364170, signals=9
11609 22:14:48.638885 # # FPSIMD-6-1: Terminated by signal 15, no error, iterations=373461, signals=10
11610 22:14:48.646000 # # FPSIMD-7-0: Terminated by signal 15, no error, iterations=580469, signals=10
11611 22:14:48.652610 # # FPSIMD-2-0: Terminated by signal 15, no error, iterations=986214, signals=10
11612 22:14:48.658688 # # FPSIMD-3-1: Terminated by signal 15, no error, iterations=1057408, signals=10
11613 22:14:48.665465 # # FPSIMD-5-1: Terminated by signal 15, no error, iterations=502418, signals=9
11614 22:14:48.672120 # # FPSIMD-7-1: Terminated by signal 15, no error, iterations=547736, signals=10
11615 22:14:48.682050 # # FPSIMD-4-1: Terminated by signal 15, no error, iterations=1239580, signals=10
11616 22:14:48.688917 # # FPSIMD-4-0: Terminated by signal 15, no error, iterations=891982, signals=9
11617 22:14:48.691793 # # Totals: pass:16 fail:0 xfail:0 xpass:0 skip:0 error:0
11618 22:14:48.695459 ok 29 selftests: arm64: fp-stress
11619 22:14:48.698611 # selftests: arm64: sve-ptrace
11620 22:14:48.699034 # TAP version 13
11621 22:14:48.702053 # 1..4104
11622 22:14:48.705734 # ok 2 # SKIP SVE not available
11623 22:14:48.708160 # # Planned tests != run tests (4104 != 1)
11624 22:14:48.711724 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11625 22:14:48.714859 ok 30 selftests: arm64: sve-ptrace # SKIP
11626 22:14:48.718278 # selftests: arm64: sve-probe-vls
11627 22:14:48.721566 # TAP version 13
11628 22:14:48.722124 # 1..2
11629 22:14:48.725037 # ok 2 # SKIP SVE not available
11630 22:14:48.728381 # # Planned tests != run tests (2 != 1)
11631 22:14:48.735181 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11632 22:14:48.738443 ok 31 selftests: arm64: sve-probe-vls # SKIP
11633 22:14:48.741929 # selftests: arm64: vec-syscfg
11634 22:14:48.742345 # TAP version 13
11635 22:14:48.742680 # 1..20
11636 22:14:48.744732 # ok 1 # SKIP SVE not supported
11637 22:14:48.747768 # ok 2 # SKIP SVE not supported
11638 22:14:48.751372 # ok 3 # SKIP SVE not supported
11639 22:14:48.755006 # ok 4 # SKIP SVE not supported
11640 22:14:48.758323 # ok 5 # SKIP SVE not supported
11641 22:14:48.761846 # ok 6 # SKIP SVE not supported
11642 22:14:48.762405 # ok 7 # SKIP SVE not supported
11643 22:14:48.764581 # ok 8 # SKIP SVE not supported
11644 22:14:48.768927 # ok 9 # SKIP SVE not supported
11645 22:14:48.771249 # ok 10 # SKIP SVE not supported
11646 22:14:48.775020 # ok 11 # SKIP SME not supported
11647 22:14:48.777885 # ok 12 # SKIP SME not supported
11648 22:14:48.781001 # ok 13 # SKIP SME not supported
11649 22:14:48.784431 # ok 14 # SKIP SME not supported
11650 22:14:48.784939 # ok 15 # SKIP SME not supported
11651 22:14:48.787642 # ok 16 # SKIP SME not supported
11652 22:14:48.790978 # ok 17 # SKIP SME not supported
11653 22:14:48.793864 # ok 18 # SKIP SME not supported
11654 22:14:48.797360 # ok 19 # SKIP SME not supported
11655 22:14:48.800655 # ok 20 # SKIP SME not supported
11656 22:14:48.807336 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:20 error:0
11657 22:14:48.807955 ok 32 selftests: arm64: vec-syscfg
11658 22:14:48.810864 # selftests: arm64: za-fork
11659 22:14:48.813995 # TAP version 13
11660 22:14:48.814409 # 1..1
11661 22:14:48.814739 # # PID: 1217
11662 22:14:48.816997 # # SME support not present
11663 22:14:48.817434 # ok 0 skipped
11664 22:14:48.824220 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11665 22:14:48.827176 ok 33 selftests: arm64: za-fork
11666 22:14:48.830722 # selftests: arm64: za-ptrace
11667 22:14:48.831346 # TAP version 13
11668 22:14:48.831694 # 1..1
11669 22:14:48.834061 # ok 2 # SKIP SME not available
11670 22:14:48.840289 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11671 22:14:48.844157 ok 34 selftests: arm64: za-ptrace # SKIP
11672 22:14:48.847177 # selftests: arm64: check_buffer_fill
11673 22:14:48.850262 # # SKIP: MTE features unavailable
11674 22:14:48.853637 ok 35 selftests: arm64: check_buffer_fill # SKIP
11675 22:14:48.856829 # selftests: arm64: check_child_memory
11676 22:14:48.907337 # # SKIP: MTE features unavailable
11677 22:14:48.913993 ok 36 selftests: arm64: check_child_memory # SKIP
11678 22:14:48.928367 # selftests: arm64: check_gcr_el1_cswitch
11679 22:14:48.976484 # # SKIP: MTE features unavailable
11680 22:14:48.983674 ok 37 selftests: arm64: check_gcr_el1_cswitch # SKIP
11681 22:14:48.999169 # selftests: arm64: check_ksm_options
11682 22:14:49.048058 # # SKIP: MTE features unavailable
11683 22:14:49.054226 ok 38 selftests: arm64: check_ksm_options # SKIP
11684 22:14:49.068468 # selftests: arm64: check_mmap_options
11685 22:14:49.118948 # # SKIP: MTE features unavailable
11686 22:14:49.125684 ok 39 selftests: arm64: check_mmap_options # SKIP
11687 22:14:49.138149 # selftests: arm64: check_prctl
11688 22:14:49.188025 # TAP version 13
11689 22:14:49.188738 # 1..5
11690 22:14:49.190721 # ok 1 check_basic_read
11691 22:14:49.191375 # ok 2 NONE
11692 22:14:49.194127 # ok 3 # SKIP SYNC
11693 22:14:49.194735 # ok 4 # SKIP ASYNC
11694 22:14:49.197256 # ok 5 # SKIP SYNC+ASYNC
11695 22:14:49.200772 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:3 error:0
11696 22:14:49.204541 ok 40 selftests: arm64: check_prctl
11697 22:14:49.210858 # selftests: arm64: check_tags_inclusion
11698 22:14:49.256652 # # SKIP: MTE features unavailable
11699 22:14:49.263332 ok 41 selftests: arm64: check_tags_inclusion # SKIP
11700 22:14:49.275334 # selftests: arm64: check_user_mem
11701 22:14:49.325852 # # SKIP: MTE features unavailable
11702 22:14:49.332610 ok 42 selftests: arm64: check_user_mem # SKIP
11703 22:14:49.345383 # selftests: arm64: btitest
11704 22:14:49.395751 # TAP version 13
11705 22:14:49.396302 # 1..18
11706 22:14:49.399050 # # HWCAP_PACA not present
11707 22:14:49.402834 # # HWCAP2_BTI not present
11708 22:14:49.403482 # # Test binary built for BTI
11709 22:14:49.408969 # ok 1 nohint_func/call_using_br_x0 # SKIP
11710 22:14:49.412819 # ok 1 nohint_func/call_using_br_x16 # SKIP
11711 22:14:49.415984 # ok 1 nohint_func/call_using_blr # SKIP
11712 22:14:49.419010 # ok 1 bti_none_func/call_using_br_x0 # SKIP
11713 22:14:49.421769 # ok 1 bti_none_func/call_using_br_x16 # SKIP
11714 22:14:49.429065 # ok 1 bti_none_func/call_using_blr # SKIP
11715 22:14:49.432203 # ok 1 bti_c_func/call_using_br_x0 # SKIP
11716 22:14:49.435278 # ok 1 bti_c_func/call_using_br_x16 # SKIP
11717 22:14:49.439193 # ok 1 bti_c_func/call_using_blr # SKIP
11718 22:14:49.441877 # ok 1 bti_j_func/call_using_br_x0 # SKIP
11719 22:14:49.446101 # ok 1 bti_j_func/call_using_br_x16 # SKIP
11720 22:14:49.448762 # ok 1 bti_j_func/call_using_blr # SKIP
11721 22:14:49.452181 # ok 1 bti_jc_func/call_using_br_x0 # SKIP
11722 22:14:49.458493 # ok 1 bti_jc_func/call_using_br_x16 # SKIP
11723 22:14:49.462138 # ok 1 bti_jc_func/call_using_blr # SKIP
11724 22:14:49.464792 # ok 1 paciasp_func/call_using_br_x0 # SKIP
11725 22:14:49.468596 # ok 1 paciasp_func/call_using_br_x16 # SKIP
11726 22:14:49.471677 # ok 1 paciasp_func/call_using_blr # SKIP
11727 22:14:49.478025 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:18 error:0
11728 22:14:49.481235 # # WARNING - EXPECTED TEST COUNT WRONG
11729 22:14:49.484664 ok 43 selftests: arm64: btitest
11730 22:14:49.487971 # selftests: arm64: nobtitest
11731 22:14:49.488548 # TAP version 13
11732 22:14:49.489025 # 1..18
11733 22:14:49.492042 # # HWCAP_PACA not present
11734 22:14:49.494578 # # HWCAP2_BTI not present
11735 22:14:49.497810 # # Test binary not built for BTI
11736 22:14:49.501254 # ok 1 nohint_func/call_using_br_x0 # SKIP
11737 22:14:49.504007 # ok 1 nohint_func/call_using_br_x16 # SKIP
11738 22:14:49.507465 # ok 1 nohint_func/call_using_blr # SKIP
11739 22:14:49.510901 # ok 1 bti_none_func/call_using_br_x0 # SKIP
11740 22:14:49.517981 # ok 1 bti_none_func/call_using_br_x16 # SKIP
11741 22:14:49.521145 # ok 1 bti_none_func/call_using_blr # SKIP
11742 22:14:49.524165 # ok 1 bti_c_func/call_using_br_x0 # SKIP
11743 22:14:49.527305 # ok 1 bti_c_func/call_using_br_x16 # SKIP
11744 22:14:49.530973 # ok 1 bti_c_func/call_using_blr # SKIP
11745 22:14:49.534635 # ok 1 bti_j_func/call_using_br_x0 # SKIP
11746 22:14:49.537368 # ok 1 bti_j_func/call_using_br_x16 # SKIP
11747 22:14:49.543926 # ok 1 bti_j_func/call_using_blr # SKIP
11748 22:14:49.547314 # ok 1 bti_jc_func/call_using_br_x0 # SKIP
11749 22:14:49.550756 # ok 1 bti_jc_func/call_using_br_x16 # SKIP
11750 22:14:49.553965 # ok 1 bti_jc_func/call_using_blr # SKIP
11751 22:14:49.557076 # ok 1 paciasp_func/call_using_br_x0 # SKIP
11752 22:14:49.560536 # ok 1 paciasp_func/call_using_br_x16 # SKIP
11753 22:14:49.567143 # ok 1 paciasp_func/call_using_blr # SKIP
11754 22:14:49.570034 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:18 error:0
11755 22:14:49.573641 # # WARNING - EXPECTED TEST COUNT WRONG
11756 22:14:49.577245 ok 44 selftests: arm64: nobtitest
11757 22:14:49.580224 # selftests: arm64: hwcap
11758 22:14:49.580649 # TAP version 13
11759 22:14:49.580983 # 1..28
11760 22:14:49.583272 # ok 1 cpuinfo_match_RNG
11761 22:14:49.586872 # # SIGILL reported for RNG
11762 22:14:49.590113 # ok 2 # SKIP sigill_RNG
11763 22:14:49.590534 # ok 3 cpuinfo_match_SME
11764 22:14:49.593423 # ok 4 sigill_SME
11765 22:14:49.593840 # ok 5 cpuinfo_match_SVE
11766 22:14:49.596441 # ok 6 sigill_SVE
11767 22:14:49.600378 # ok 7 cpuinfo_match_SVE 2
11768 22:14:49.604074 # # SIGILL reported for SVE 2
11769 22:14:49.604499 # ok 8 # SKIP sigill_SVE 2
11770 22:14:49.606722 # ok 9 cpuinfo_match_SVE AES
11771 22:14:49.610267 # # SIGILL reported for SVE AES
11772 22:14:49.613390 # ok 10 # SKIP sigill_SVE AES
11773 22:14:49.616504 # ok 11 cpuinfo_match_SVE2 PMULL
11774 22:14:49.620045 # # SIGILL reported for SVE2 PMULL
11775 22:14:49.620526 # ok 12 # SKIP sigill_SVE2 PMULL
11776 22:14:49.623301 # ok 13 cpuinfo_match_SVE2 BITPERM
11777 22:14:49.626776 # # SIGILL reported for SVE2 BITPERM
11778 22:14:49.629637 # ok 14 # SKIP sigill_SVE2 BITPERM
11779 22:14:49.632690 # ok 15 cpuinfo_match_SVE2 SHA3
11780 22:14:49.636007 # # SIGILL reported for SVE2 SHA3
11781 22:14:49.639855 # ok 16 # SKIP sigill_SVE2 SHA3
11782 22:14:49.642549 # ok 17 cpuinfo_match_SVE2 SM4
11783 22:14:49.645963 # # SIGILL reported for SVE2 SM4
11784 22:14:49.649828 # ok 18 # SKIP sigill_SVE2 SM4
11785 22:14:49.649959 # ok 19 cpuinfo_match_SVE2 I8MM
11786 22:14:49.652692 # # SIGILL reported for SVE2 I8MM
11787 22:14:49.656032 # ok 20 # SKIP sigill_SVE2 I8MM
11788 22:14:49.659449 # ok 21 cpuinfo_match_SVE2 F32MM
11789 22:14:49.662496 # # SIGILL reported for SVE2 F32MM
11790 22:14:49.665463 # ok 22 # SKIP sigill_SVE2 F32MM
11791 22:14:49.668975 # ok 23 cpuinfo_match_SVE2 F64MM
11792 22:14:49.671943 # # SIGILL reported for SVE2 F64MM
11793 22:14:49.675368 # ok 24 # SKIP sigill_SVE2 F64MM
11794 22:14:49.678805 # ok 25 cpuinfo_match_SVE2 BF16
11795 22:14:49.682277 # # SIGILL reported for SVE2 BF16
11796 22:14:49.682370 # ok 26 # SKIP sigill_SVE2 BF16
11797 22:14:49.685284 # ok 27 cpuinfo_match_SVE2 EBF16
11798 22:14:49.688810 # ok 28 # SKIP sigill_SVE2 EBF16
11799 22:14:49.694969 # # Totals: pass:16 fail:0 xfail:0 xpass:0 skip:12 error:0
11800 22:14:49.698436 ok 45 selftests: arm64: hwcap
11801 22:14:49.698523 # selftests: arm64: ptrace
11802 22:14:49.702117 # TAP version 13
11803 22:14:49.702197 # 1..7
11804 22:14:49.705493 # # Parent is 1446, child is 1447
11805 22:14:49.708686 # ok 1 read_tpidr_one
11806 22:14:49.708759 # ok 2 write_tpidr_one
11807 22:14:49.711878 # ok 3 verify_tpidr_one
11808 22:14:49.711959 # ok 4 count_tpidrs
11809 22:14:49.715037 # ok 5 tpidr2_write
11810 22:14:49.715157 # ok 6 tpidr2_read
11811 22:14:49.718368 # ok 7 write_tpidr_only
11812 22:14:49.725512 # # Totals: pass:7 fail:0 xfail:0 xpass:0 skip:0 error:0
11813 22:14:49.725625 ok 46 selftests: arm64: ptrace
11814 22:14:49.728175 # selftests: arm64: syscall-abi
11815 22:14:49.731442 # TAP version 13
11816 22:14:49.731537 # 1..2
11817 22:14:49.735048 # ok 1 getpid() FPSIMD
11818 22:14:49.735179 # ok 2 sched_yield() FPSIMD
11819 22:14:49.741165 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:0 error:0
11820 22:14:49.745862 ok 47 selftests: arm64: syscall-abi
11821 22:14:49.747916 # selftests: arm64: tpidr2
11822 22:14:49.747999 # TAP version 13
11823 22:14:49.748063 # 1..5
11824 22:14:49.751460 # # PID: 1481
11825 22:14:49.751544 # # SME support not present
11826 22:14:49.754548 # ok 0 skipped, TPIDR2 not supported
11827 22:14:49.758023 # ok 1 skipped, TPIDR2 not supported
11828 22:14:49.761547 # ok 2 skipped, TPIDR2 not supported
11829 22:14:49.764492 # ok 3 skipped, TPIDR2 not supported
11830 22:14:49.768062 # ok 4 skipped, TPIDR2 not supported
11831 22:14:49.774402 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:5 error:0
11832 22:14:49.778179 ok 48 selftests: arm64: tpidr2
11833 22:14:50.393377 arm64_tags_test pass
11834 22:14:50.397204 arm64_run_tags_test_sh pass
11835 22:14:50.400414 arm64_fake_sigreturn_bad_magic pass
11836 22:14:50.403904 arm64_fake_sigreturn_bad_size pass
11837 22:14:50.407607 arm64_fake_sigreturn_bad_size_for_magic0 pass
11838 22:14:50.410104 arm64_fake_sigreturn_duplicated_fpsimd pass
11839 22:14:50.413504 arm64_fake_sigreturn_misaligned_sp pass
11840 22:14:50.416893 arm64_fake_sigreturn_missing_fpsimd pass
11841 22:14:50.419807 arm64_fake_sigreturn_sme_change_vl skip
11842 22:14:50.423623 arm64_fake_sigreturn_sve_change_vl skip
11843 22:14:50.429777 arm64_mangle_pstate_invalid_compat_toggle pass
11844 22:14:50.433503 arm64_mangle_pstate_invalid_daif_bits pass
11845 22:14:50.437250 arm64_mangle_pstate_invalid_mode_el1h pass
11846 22:14:50.439766 arm64_mangle_pstate_invalid_mode_el1t pass
11847 22:14:50.442898 arm64_mangle_pstate_invalid_mode_el2h pass
11848 22:14:50.449766 arm64_mangle_pstate_invalid_mode_el2t pass
11849 22:14:50.453207 arm64_mangle_pstate_invalid_mode_el3h pass
11850 22:14:50.456302 arm64_mangle_pstate_invalid_mode_el3t pass
11851 22:14:50.459575 arm64_sme_trap_no_sm skip
11852 22:14:50.459663 arm64_sme_trap_non_streaming skip
11853 22:14:50.463004 arm64_sme_trap_za pass
11854 22:14:50.466592 arm64_sme_vl skip
11855 22:14:50.466676 arm64_ssve_regs skip
11856 22:14:50.469366 arm64_sve_regs skip
11857 22:14:50.469450 arm64_sve_vl skip
11858 22:14:50.473611 arm64_za_no_regs skip
11859 22:14:50.473695 arm64_za_regs skip
11860 22:14:50.475876 arm64_pac_PAUTH_not_enabled skip
11861 22:14:50.479933 arm64_pac_PAUTH_not_enabled skip
11862 22:14:50.483244 arm64_pac_Generic_PAUTH_not_enabled skip
11863 22:14:50.486453 arm64_pac_PAUTH_not_enabled skip
11864 22:14:50.489603 arm64_pac_PAUTH_not_enabled skip
11865 22:14:50.492646 arm64_pac_PAUTH_not_enabled skip
11866 22:14:50.496224 arm64_pac_Generic_PAUTH_not_enabled skip
11867 22:14:50.496315 arm64_pac pass
11868 22:14:50.499330 arm64_fp-stress_FPSIMD-0-0 pass
11869 22:14:50.502640 arm64_fp-stress_FPSIMD-0-1 pass
11870 22:14:50.506166 arm64_fp-stress_FPSIMD-1-0 pass
11871 22:14:50.509364 arm64_fp-stress_FPSIMD-1-1 pass
11872 22:14:50.512994 arm64_fp-stress_FPSIMD-2-0 pass
11873 22:14:50.515918 arm64_fp-stress_FPSIMD-2-1 pass
11874 22:14:50.519621 arm64_fp-stress_FPSIMD-3-0 pass
11875 22:14:50.519702 arm64_fp-stress_FPSIMD-3-1 pass
11876 22:14:50.522853 arm64_fp-stress_FPSIMD-4-0 pass
11877 22:14:50.525580 arm64_fp-stress_FPSIMD-4-1 pass
11878 22:14:50.529228 arm64_fp-stress_FPSIMD-5-0 pass
11879 22:14:50.532026 arm64_fp-stress_FPSIMD-5-1 pass
11880 22:14:50.535834 arm64_fp-stress_FPSIMD-6-0 pass
11881 22:14:50.538878 arm64_fp-stress_FPSIMD-6-1 pass
11882 22:14:50.538982 arm64_fp-stress_FPSIMD-7-0 pass
11883 22:14:50.542331 arm64_fp-stress_FPSIMD-7-1 pass
11884 22:14:50.545473 arm64_fp-stress pass
11885 22:14:50.549062 arm64_sve-ptrace_SVE_not_available skip
11886 22:14:50.552191 arm64_sve-ptrace skip
11887 22:14:50.555461 arm64_sve-probe-vls_SVE_not_available skip
11888 22:14:50.555540 arm64_sve-probe-vls skip
11889 22:14:50.562342 arm64_vec-syscfg_SVE_not_supported skip
11890 22:14:50.565588 arm64_vec-syscfg_SVE_not_supported skip
11891 22:14:50.568827 arm64_vec-syscfg_SVE_not_supported skip
11892 22:14:50.572742 arm64_vec-syscfg_SVE_not_supported skip
11893 22:14:50.575416 arm64_vec-syscfg_SVE_not_supported skip
11894 22:14:50.578987 arm64_vec-syscfg_SVE_not_supported skip
11895 22:14:50.581828 arm64_vec-syscfg_SVE_not_supported skip
11896 22:14:50.585257 arm64_vec-syscfg_SVE_not_supported skip
11897 22:14:50.588575 arm64_vec-syscfg_SVE_not_supported skip
11898 22:14:50.591432 arm64_vec-syscfg_SVE_not_supported skip
11899 22:14:50.595360 arm64_vec-syscfg_SME_not_supported skip
11900 22:14:50.598348 arm64_vec-syscfg_SME_not_supported skip
11901 22:14:50.602113 arm64_vec-syscfg_SME_not_supported skip
11902 22:14:50.608264 arm64_vec-syscfg_SME_not_supported skip
11903 22:14:50.611598 arm64_vec-syscfg_SME_not_supported skip
11904 22:14:50.614959 arm64_vec-syscfg_SME_not_supported skip
11905 22:14:50.618198 arm64_vec-syscfg_SME_not_supported skip
11906 22:14:50.621084 arm64_vec-syscfg_SME_not_supported skip
11907 22:14:50.625818 arm64_vec-syscfg_SME_not_supported skip
11908 22:14:50.628210 arm64_vec-syscfg_SME_not_supported skip
11909 22:14:50.631015 arm64_vec-syscfg pass
11910 22:14:50.631156 arm64_za-fork_skipped pass
11911 22:14:50.634974 arm64_za-fork pass
11912 22:14:50.637966 arm64_za-ptrace_SME_not_available skip
11913 22:14:50.640961 arm64_za-ptrace skip
11914 22:14:50.641045 arm64_check_buffer_fill skip
11915 22:14:50.644541 arm64_check_child_memory skip
11916 22:14:50.648060 arm64_check_gcr_el1_cswitch skip
11917 22:14:50.651472 arm64_check_ksm_options skip
11918 22:14:50.654370 arm64_check_mmap_options skip
11919 22:14:50.657726 arm64_check_prctl_check_basic_read pass
11920 22:14:50.657809 arm64_check_prctl_NONE pass
11921 22:14:50.661360 arm64_check_prctl_SYNC skip
11922 22:14:50.664180 arm64_check_prctl_ASYNC skip
11923 22:14:50.667919 arm64_check_prctl_SYNC_ASYNC skip
11924 22:14:50.670883 arm64_check_prctl pass
11925 22:14:50.670985 arm64_check_tags_inclusion skip
11926 22:14:50.674059 arm64_check_user_mem skip
11927 22:14:50.677486 arm64_btitest_nohint_func_call_using_br_x0 skip
11928 22:14:50.684361 arm64_btitest_nohint_func_call_using_br_x16 skip
11929 22:14:50.687194 arm64_btitest_nohint_func_call_using_blr skip
11930 22:14:50.690517 arm64_btitest_bti_none_func_call_using_br_x0 skip
11931 22:14:50.697154 arm64_btitest_bti_none_func_call_using_br_x16 skip
11932 22:14:50.701129 arm64_btitest_bti_none_func_call_using_blr skip
11933 22:14:50.703666 arm64_btitest_bti_c_func_call_using_br_x0 skip
11934 22:14:50.710176 arm64_btitest_bti_c_func_call_using_br_x16 skip
11935 22:14:50.713444 arm64_btitest_bti_c_func_call_using_blr skip
11936 22:14:50.717002 arm64_btitest_bti_j_func_call_using_br_x0 skip
11937 22:14:50.720268 arm64_btitest_bti_j_func_call_using_br_x16 skip
11938 22:14:50.726768 arm64_btitest_bti_j_func_call_using_blr skip
11939 22:14:50.730057 arm64_btitest_bti_jc_func_call_using_br_x0 skip
11940 22:14:50.733562 arm64_btitest_bti_jc_func_call_using_br_x16 skip
11941 22:14:50.736475 arm64_btitest_bti_jc_func_call_using_blr skip
11942 22:14:50.743346 arm64_btitest_paciasp_func_call_using_br_x0 skip
11943 22:14:50.746903 arm64_btitest_paciasp_func_call_using_br_x16 skip
11944 22:14:50.749756 arm64_btitest_paciasp_func_call_using_blr skip
11945 22:14:50.752976 arm64_btitest pass
11946 22:14:50.756488 arm64_nobtitest_nohint_func_call_using_br_x0 skip
11947 22:14:50.763179 arm64_nobtitest_nohint_func_call_using_br_x16 skip
11948 22:14:50.766610 arm64_nobtitest_nohint_func_call_using_blr skip
11949 22:14:50.769417 arm64_nobtitest_bti_none_func_call_using_br_x0 skip
11950 22:14:50.776370 arm64_nobtitest_bti_none_func_call_using_br_x16 skip
11951 22:14:50.779720 arm64_nobtitest_bti_none_func_call_using_blr skip
11952 22:14:50.782911 arm64_nobtitest_bti_c_func_call_using_br_x0 skip
11953 22:14:50.790177 arm64_nobtitest_bti_c_func_call_using_br_x16 skip
11954 22:14:50.792527 arm64_nobtitest_bti_c_func_call_using_blr skip
11955 22:14:50.796566 arm64_nobtitest_bti_j_func_call_using_br_x0 skip
11956 22:14:50.803009 arm64_nobtitest_bti_j_func_call_using_br_x16 skip
11957 22:14:50.806108 arm64_nobtitest_bti_j_func_call_using_blr skip
11958 22:14:50.809353 arm64_nobtitest_bti_jc_func_call_using_br_x0 skip
11959 22:14:50.816143 arm64_nobtitest_bti_jc_func_call_using_br_x16 skip
11960 22:14:50.819385 arm64_nobtitest_bti_jc_func_call_using_blr skip
11961 22:14:50.822601 arm64_nobtitest_paciasp_func_call_using_br_x0 skip
11962 22:14:50.829419 arm64_nobtitest_paciasp_func_call_using_br_x16 skip
11963 22:14:50.832480 arm64_nobtitest_paciasp_func_call_using_blr skip
11964 22:14:50.832563 arm64_nobtitest pass
11965 22:14:50.836026 arm64_hwcap_cpuinfo_match_RNG pass
11966 22:14:50.839541 arm64_hwcap_sigill_RNG skip
11967 22:14:50.842450 arm64_hwcap_cpuinfo_match_SME pass
11968 22:14:50.845324 arm64_hwcap_sigill_SME pass
11969 22:14:50.849091 arm64_hwcap_cpuinfo_match_SVE pass
11970 22:14:50.852243 arm64_hwcap_sigill_SVE pass
11971 22:14:50.855500 arm64_hwcap_cpuinfo_match_SVE_2 pass
11972 22:14:50.855584 arm64_hwcap_sigill_SVE_2 skip
11973 22:14:50.858935 arm64_hwcap_cpuinfo_match_SVE_AES pass
11974 22:14:50.862017 arm64_hwcap_sigill_SVE_AES skip
11975 22:14:50.865397 arm64_hwcap_cpuinfo_match_SVE2_PMULL pass
11976 22:14:50.868561 arm64_hwcap_sigill_SVE2_PMULL skip
11977 22:14:50.875246 arm64_hwcap_cpuinfo_match_SVE2_BITPERM pass
11978 22:14:50.878263 arm64_hwcap_sigill_SVE2_BITPERM skip
11979 22:14:50.881618 arm64_hwcap_cpuinfo_match_SVE2_SHA3 pass
11980 22:14:50.884868 arm64_hwcap_sigill_SVE2_SHA3 skip
11981 22:14:50.888468 arm64_hwcap_cpuinfo_match_SVE2_SM4 pass
11982 22:14:50.891617 arm64_hwcap_sigill_SVE2_SM4 skip
11983 22:14:50.894777 arm64_hwcap_cpuinfo_match_SVE2_I8MM pass
11984 22:14:50.898169 arm64_hwcap_sigill_SVE2_I8MM skip
11985 22:14:50.901376 arm64_hwcap_cpuinfo_match_SVE2_F32MM pass
11986 22:14:50.904969 arm64_hwcap_sigill_SVE2_F32MM skip
11987 22:14:50.908468 arm64_hwcap_cpuinfo_match_SVE2_F64MM pass
11988 22:14:50.911518 arm64_hwcap_sigill_SVE2_F64MM skip
11989 22:14:50.915017 arm64_hwcap_cpuinfo_match_SVE2_BF16 pass
11990 22:14:50.917543 arm64_hwcap_sigill_SVE2_BF16 skip
11991 22:14:50.921081 arm64_hwcap_cpuinfo_match_SVE2_EBF16 pass
11992 22:14:50.924208 arm64_hwcap_sigill_SVE2_EBF16 skip
11993 22:14:50.924290 arm64_hwcap pass
11994 22:14:50.928001 arm64_ptrace_read_tpidr_one pass
11995 22:14:50.930714 arm64_ptrace_write_tpidr_one pass
11996 22:14:50.934346 arm64_ptrace_verify_tpidr_one pass
11997 22:14:50.937343 arm64_ptrace_count_tpidrs pass
11998 22:14:50.941183 arm64_ptrace_tpidr2_write pass
11999 22:14:50.944013 arm64_ptrace_tpidr2_read pass
12000 22:14:50.947542 arm64_ptrace_write_tpidr_only pass
12001 22:14:50.947624 arm64_ptrace pass
12002 22:14:50.951261 arm64_syscall-abi_getpid_FPSIMD pass
12003 22:14:50.954132 arm64_syscall-abi_sched_yield_FPSIMD pass
12004 22:14:50.957487 arm64_syscall-abi pass
12005 22:14:50.961079 arm64_tpidr2_skipped_TPIDR2_not_supported pass
12006 22:14:50.964498 arm64_tpidr2_skipped_TPIDR2_not_supported pass
12007 22:14:50.970445 arm64_tpidr2_skipped_TPIDR2_not_supported pass
12008 22:14:50.974072 arm64_tpidr2_skipped_TPIDR2_not_supported pass
12009 22:14:50.977303 arm64_tpidr2_skipped_TPIDR2_not_supported pass
12010 22:14:50.980596 arm64_tpidr2 pass
12011 22:14:50.983518 + ../../utils/send-to-lava.sh ./output/result.txt
12012 22:14:50.991192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tags_test RESULT=pass>
12013 22:14:50.991465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tags_test RESULT=pass
12015 22:14:50.997109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass>
12016 22:14:50.997364 Received signal: <TESTCASE> TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass
12018 22:14:51.003502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass>
12019 22:14:51.003756 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass
12021 22:14:51.009852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass>
12022 22:14:51.010106 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass
12024 22:14:51.016530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass>
12025 22:14:51.016784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass
12027 22:14:51.024008 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass
12029 22:14:51.026520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass>
12030 22:14:51.050921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass>
12031 22:14:51.051178 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass
12033 22:14:51.092381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass>
12034 22:14:51.092642 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass
12036 22:14:51.131705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=skip>
12037 22:14:51.131982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=skip
12039 22:14:51.176617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=skip>
12040 22:14:51.176877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=skip
12042 22:14:51.221588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass>
12043 22:14:51.221871 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass
12045 22:14:51.263531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass>
12046 22:14:51.263803 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass
12048 22:14:51.307832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass>
12049 22:14:51.308147 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass
12051 22:14:51.351758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass>
12052 22:14:51.352066 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass
12054 22:14:51.399442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass>
12055 22:14:51.399751 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass
12057 22:14:51.438362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass>
12058 22:14:51.438710 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass
12060 22:14:51.477313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass>
12061 22:14:51.477628 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass
12063 22:14:51.514147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass>
12064 22:14:51.514448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass
12066 22:14:51.549901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=skip>
12067 22:14:51.550217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=skip
12069 22:14:51.593542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip
12071 22:14:51.596503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip>
12072 22:14:51.636775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_za RESULT=pass>
12073 22:14:51.637097 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_za RESULT=pass
12075 22:14:51.681136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_vl RESULT=skip>
12076 22:14:51.681453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_vl RESULT=skip
12078 22:14:51.722036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ssve_regs RESULT=skip>
12079 22:14:51.722354 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ssve_regs RESULT=skip
12081 22:14:51.755644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_regs RESULT=skip>
12082 22:14:51.755991 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_regs RESULT=skip
12084 22:14:51.796607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_vl RESULT=skip>
12085 22:14:51.796934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_vl RESULT=skip
12087 22:14:51.837220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_no_regs RESULT=skip>
12088 22:14:51.837540 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_no_regs RESULT=skip
12090 22:14:51.866996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_regs RESULT=skip>
12091 22:14:51.867318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_regs RESULT=skip
12093 22:14:51.903553 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip
12095 22:14:51.906383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip>
12096 22:14:51.939353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip
12098 22:14:51.942049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip>
12099 22:14:51.977222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled RESULT=skip>
12100 22:14:51.977513 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled RESULT=skip
12102 22:14:52.014635 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip
12104 22:14:52.018187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip>
12105 22:14:52.056126 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip
12107 22:14:52.059647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip>
12108 22:14:52.094524 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip
12110 22:14:52.097614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip>
12111 22:14:52.135541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled RESULT=skip>
12112 22:14:52.135868 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled RESULT=skip
12114 22:14:52.172287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac RESULT=pass>
12115 22:14:52.172633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac RESULT=pass
12117 22:14:52.213853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass>
12118 22:14:52.214189 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass
12120 22:14:52.250342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-1 RESULT=pass>
12121 22:14:52.250658 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-1 RESULT=pass
12123 22:14:52.287610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-0 RESULT=pass>
12124 22:14:52.287914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-0 RESULT=pass
12126 22:14:52.322943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-1 RESULT=pass>
12127 22:14:52.323297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-1 RESULT=pass
12129 22:14:52.364527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-0 RESULT=pass>
12130 22:14:52.364821 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-0 RESULT=pass
12132 22:14:52.403182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-1 RESULT=pass>
12133 22:14:52.403479 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-1 RESULT=pass
12135 22:14:52.442341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-0 RESULT=pass>
12136 22:14:52.442666 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-0 RESULT=pass
12138 22:14:52.479707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-1 RESULT=pass>
12139 22:14:52.480005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-1 RESULT=pass
12141 22:14:52.518790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-0 RESULT=pass>
12142 22:14:52.519097 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-0 RESULT=pass
12144 22:14:52.556046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-1 RESULT=pass>
12145 22:14:52.556328 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-1 RESULT=pass
12147 22:14:52.597301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-0 RESULT=pass>
12148 22:14:52.597655 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-0 RESULT=pass
12150 22:14:52.633513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-1 RESULT=pass>
12151 22:14:52.633808 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-1 RESULT=pass
12153 22:14:52.670742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-0 RESULT=pass>
12154 22:14:52.671043 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-0 RESULT=pass
12156 22:14:52.709475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-1 RESULT=pass>
12157 22:14:52.709784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-1 RESULT=pass
12159 22:14:52.748569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-0 RESULT=pass>
12160 22:14:52.748856 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-0 RESULT=pass
12162 22:14:52.786731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-1 RESULT=pass>
12163 22:14:52.787040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-1 RESULT=pass
12165 22:14:52.828085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress RESULT=pass>
12166 22:14:52.828408 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress RESULT=pass
12168 22:14:52.871632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_not_available RESULT=skip>
12169 22:14:52.871938 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_not_available RESULT=skip
12171 22:14:52.907403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace RESULT=skip>
12172 22:14:52.907726 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace RESULT=skip
12174 22:14:52.953021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls_SVE_not_available RESULT=skip>
12175 22:14:52.953340 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls_SVE_not_available RESULT=skip
12177 22:14:52.988611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls RESULT=skip>
12178 22:14:52.988920 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls RESULT=skip
12180 22:14:53.035686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12181 22:14:53.035999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12183 22:14:53.084573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12184 22:14:53.084880 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12186 22:14:53.122399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12187 22:14:53.122713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12189 22:14:53.164930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12190 22:14:53.165247 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12192 22:14:53.202497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12193 22:14:53.202793 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12195 22:14:53.243524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12196 22:14:53.243868 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12198 22:14:53.286708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12199 22:14:53.287007 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12201 22:14:53.321247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12202 22:14:53.321545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12204 22:14:53.362369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12205 22:14:53.362670 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12207 22:14:53.398220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12208 22:14:53.398571 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12210 22:14:53.443839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12211 22:14:53.444199 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12213 22:14:53.482112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12214 22:14:53.482438 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12216 22:14:53.524359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12217 22:14:53.524673 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12219 22:14:53.561881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12220 22:14:53.562181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12222 22:14:53.594882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12223 22:14:53.595157 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12225 22:14:53.634289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12226 22:14:53.634591 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12228 22:14:53.670066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12229 22:14:53.670373 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12231 22:14:53.703321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12232 22:14:53.703620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12234 22:14:53.736193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12235 22:14:53.736477 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12237 22:14:53.778778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12238 22:14:53.779096 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12240 22:14:53.817116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg RESULT=pass>
12241 22:14:53.817452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg RESULT=pass
12243 22:14:53.851686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork_skipped RESULT=pass>
12244 22:14:53.851968 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork_skipped RESULT=pass
12246 22:14:53.890711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork RESULT=pass>
12247 22:14:53.891020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork RESULT=pass
12249 22:14:53.934643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_SME_not_available RESULT=skip>
12250 22:14:53.934951 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_SME_not_available RESULT=skip
12252 22:14:53.964722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace RESULT=skip>
12253 22:14:53.965001 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace RESULT=skip
12255 22:14:54.006226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill RESULT=skip>
12256 22:14:54.006547 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill RESULT=skip
12258 22:14:54.043159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory RESULT=skip>
12259 22:14:54.043467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory RESULT=skip
12261 22:14:54.074729 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=skip
12263 22:14:54.077705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=skip>
12264 22:14:54.112394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_ksm_options RESULT=skip>
12265 22:14:54.112694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_ksm_options RESULT=skip
12267 22:14:54.147306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options RESULT=skip>
12268 22:14:54.147649 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options RESULT=skip
12270 22:14:54.186803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass>
12271 22:14:54.187129 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass
12273 22:14:54.219251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass>
12274 22:14:54.219608 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass
12276 22:14:54.255351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_SYNC RESULT=skip>
12277 22:14:54.255652 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_SYNC RESULT=skip
12279 22:14:54.294851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_ASYNC RESULT=skip>
12280 22:14:54.295187 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_ASYNC RESULT=skip
12282 22:14:54.327776 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_SYNC_ASYNC RESULT=skip
12284 22:14:54.331084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_SYNC_ASYNC RESULT=skip>
12285 22:14:54.360349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl RESULT=pass>
12286 22:14:54.360649 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl RESULT=pass
12288 22:14:54.395326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion RESULT=skip>
12289 22:14:54.395628 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion RESULT=skip
12291 22:14:54.427973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem RESULT=skip>
12292 22:14:54.428289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem RESULT=skip
12294 22:14:54.466118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=skip>
12295 22:14:54.466429 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=skip
12297 22:14:54.496573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=skip>
12298 22:14:54.496867 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=skip
12300 22:14:54.530026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=skip>
12301 22:14:54.530329 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=skip
12303 22:14:54.564728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=skip>
12304 22:14:54.565017 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=skip
12306 22:14:54.603842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=skip>
12307 22:14:54.604131 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=skip
12309 22:14:54.641723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=skip>
12310 22:14:54.642016 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=skip
12312 22:14:54.674696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=skip>
12313 22:14:54.674984 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=skip
12315 22:14:54.714497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=skip>
12316 22:14:54.714793 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=skip
12318 22:14:54.751075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=skip>
12319 22:14:54.751383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=skip
12321 22:14:54.786596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=skip>
12322 22:14:54.786878 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=skip
12324 22:14:54.824173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=skip>
12325 22:14:54.824470 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=skip
12327 22:14:54.864843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=skip>
12328 22:14:54.865148 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=skip
12330 22:14:54.900654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=skip>
12331 22:14:54.900969 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=skip
12333 22:14:54.937407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=skip>
12334 22:14:54.937712 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=skip
12336 22:14:54.975013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=skip>
12337 22:14:54.975334 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=skip
12339 22:14:55.011035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=skip>
12340 22:14:55.011353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=skip
12342 22:14:55.046232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=skip>
12343 22:14:55.046521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=skip
12345 22:14:55.083042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=skip>
12346 22:14:55.083401 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=skip
12348 22:14:55.118608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest RESULT=pass>
12349 22:14:55.118899 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest RESULT=pass
12351 22:14:55.157678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=skip>
12352 22:14:55.157965 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=skip
12354 22:14:55.190567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=skip>
12355 22:14:55.190883 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=skip
12357 22:14:55.223389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=skip>
12358 22:14:55.223683 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=skip
12360 22:14:55.262502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=skip>
12361 22:14:55.262822 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=skip
12363 22:14:55.302280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=skip>
12364 22:14:55.302628 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=skip
12366 22:14:55.343245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=skip>
12367 22:14:55.343548 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=skip
12369 22:14:55.383481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=skip>
12370 22:14:55.383801 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=skip
12372 22:14:55.420914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=skip>
12373 22:14:55.421219 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=skip
12375 22:14:55.455662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=skip>
12376 22:14:55.455968 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=skip
12378 22:14:55.489060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=skip>
12379 22:14:55.489391 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=skip
12381 22:14:55.521712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=skip>
12382 22:14:55.522039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=skip
12384 22:14:55.553918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=skip>
12385 22:14:55.554227 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=skip
12387 22:14:55.594562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=skip>
12388 22:14:55.594885 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=skip
12390 22:14:55.626963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=skip>
12391 22:14:55.627285 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=skip
12393 22:14:55.662501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=skip>
12394 22:14:55.662796 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=skip
12396 22:14:55.698210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=skip>
12397 22:14:55.698535 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=skip
12399 22:14:55.732763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=skip>
12400 22:14:55.733061 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=skip
12402 22:14:55.772899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=skip>
12403 22:14:55.773210 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=skip
12405 22:14:55.803811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest RESULT=pass>
12406 22:14:55.804151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest RESULT=pass
12408 22:14:55.843701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass>
12409 22:14:55.844022 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass
12411 22:14:55.873106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_RNG RESULT=skip>
12412 22:14:55.873419 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_RNG RESULT=skip
12414 22:14:55.910831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass>
12415 22:14:55.911167 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass
12417 22:14:55.938939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass>
12418 22:14:55.939292 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass
12420 22:14:55.978110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass>
12421 22:14:55.978419 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass
12423 22:14:56.008500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass>
12424 22:14:56.008835 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass
12426 22:14:56.047445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass>
12427 22:14:56.047765 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass
12429 22:14:56.083402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE_2 RESULT=skip>
12430 22:14:56.083718 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE_2 RESULT=skip
12432 22:14:56.124007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass>
12433 22:14:56.124325 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass
12435 22:14:56.159291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE_AES RESULT=skip>
12436 22:14:56.159645 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE_AES RESULT=skip
12438 22:14:56.199300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass>
12439 22:14:56.199612 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass
12441 22:14:56.234264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_PMULL RESULT=skip>
12442 22:14:56.234573 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_PMULL RESULT=skip
12444 22:14:56.270991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass>
12445 22:14:56.271339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass
12447 22:14:56.316278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BITPERM RESULT=skip>
12448 22:14:56.316600 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BITPERM RESULT=skip
12450 22:14:56.355325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass>
12451 22:14:56.355641 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass
12453 22:14:56.392152 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SHA3 RESULT=skip
12455 22:14:56.394834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SHA3 RESULT=skip>
12456 22:14:56.428339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass>
12457 22:14:56.428649 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass
12459 22:14:56.468441 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SM4 RESULT=skip
12461 22:14:56.471864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SM4 RESULT=skip>
12462 22:14:56.507851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass>
12463 22:14:56.508159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass
12465 22:14:56.543950 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_I8MM RESULT=skip
12467 22:14:56.546600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_I8MM RESULT=skip>
12468 22:14:56.589131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass>
12469 22:14:56.589463 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass
12471 22:14:56.624584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F32MM RESULT=skip>
12472 22:14:56.624923 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F32MM RESULT=skip
12474 22:14:56.659068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass>
12475 22:14:56.659373 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass
12477 22:14:56.693381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F64MM RESULT=skip>
12478 22:14:56.693689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F64MM RESULT=skip
12480 22:14:56.730512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass>
12481 22:14:56.730849 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass
12483 22:14:56.764425 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BF16 RESULT=skip
12485 22:14:56.767020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BF16 RESULT=skip>
12486 22:14:56.803164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass>
12487 22:14:56.803489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass
12489 22:14:56.843419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_EBF16 RESULT=skip>
12490 22:14:56.843726 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_EBF16 RESULT=skip
12492 22:14:56.882372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap RESULT=pass>
12493 22:14:56.882675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap RESULT=pass
12495 22:14:56.916990 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass
12497 22:14:56.919936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass>
12498 22:14:56.948264 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass
12500 22:14:56.951263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass>
12501 22:14:56.999170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass>
12502 22:14:56.999529 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass
12504 22:14:57.032911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass>
12505 22:14:57.033252 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass
12507 22:14:57.079308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass>
12508 22:14:57.079646 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass
12510 22:14:57.120678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass>
12511 22:14:57.121072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass
12513 22:14:57.170390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass>
12514 22:14:57.170774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass
12516 22:14:57.204079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace RESULT=pass>
12517 22:14:57.204386 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace RESULT=pass
12519 22:14:57.252211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass>
12520 22:14:57.252570 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass
12522 22:14:57.289894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass>
12523 22:14:57.290156 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass
12525 22:14:57.333232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi RESULT=pass>
12526 22:14:57.333530 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi RESULT=pass
12528 22:14:57.378425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12529 22:14:57.378696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12531 22:14:57.424045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12532 22:14:57.424310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12534 22:14:57.463200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12535 22:14:57.463471 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12537 22:14:57.511250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12538 22:14:57.511514 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12540 22:14:57.548197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12541 22:14:57.548460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12543 22:14:57.587093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2 RESULT=pass>
12544 22:14:57.587200 + set +x
12545 22:14:57.587436 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2 RESULT=pass
12547 22:14:57.593799 <LAVA_SIGNAL_ENDRUN 1_kselftest-arm64 10583852_1.6.2.3.5>
12548 22:14:57.594050 Received signal: <ENDRUN> 1_kselftest-arm64 10583852_1.6.2.3.5
12549 22:14:57.594124 Ending use of test pattern.
12550 22:14:57.594185 Ending test lava.1_kselftest-arm64 (10583852_1.6.2.3.5), duration 28.39
12552 22:14:57.597078 <LAVA_TEST_RUNNER EXIT>
12553 22:14:57.597327 ok: lava_test_shell seems to have completed
12554 22:14:57.598269 arm64_btitest: pass
arm64_btitest_bti_c_func_call_using_blr: skip
arm64_btitest_bti_c_func_call_using_br_x0: skip
arm64_btitest_bti_c_func_call_using_br_x16: skip
arm64_btitest_bti_j_func_call_using_blr: skip
arm64_btitest_bti_j_func_call_using_br_x0: skip
arm64_btitest_bti_j_func_call_using_br_x16: skip
arm64_btitest_bti_jc_func_call_using_blr: skip
arm64_btitest_bti_jc_func_call_using_br_x0: skip
arm64_btitest_bti_jc_func_call_using_br_x16: skip
arm64_btitest_bti_none_func_call_using_blr: skip
arm64_btitest_bti_none_func_call_using_br_x0: skip
arm64_btitest_bti_none_func_call_using_br_x16: skip
arm64_btitest_nohint_func_call_using_blr: skip
arm64_btitest_nohint_func_call_using_br_x0: skip
arm64_btitest_nohint_func_call_using_br_x16: skip
arm64_btitest_paciasp_func_call_using_blr: skip
arm64_btitest_paciasp_func_call_using_br_x0: skip
arm64_btitest_paciasp_func_call_using_br_x16: skip
arm64_check_buffer_fill: skip
arm64_check_child_memory: skip
arm64_check_gcr_el1_cswitch: skip
arm64_check_ksm_options: skip
arm64_check_mmap_options: skip
arm64_check_prctl: pass
arm64_check_prctl_ASYNC: skip
arm64_check_prctl_NONE: pass
arm64_check_prctl_SYNC: skip
arm64_check_prctl_SYNC_ASYNC: skip
arm64_check_prctl_check_basic_read: pass
arm64_check_tags_inclusion: skip
arm64_check_user_mem: skip
arm64_fake_sigreturn_bad_magic: pass
arm64_fake_sigreturn_bad_size: pass
arm64_fake_sigreturn_bad_size_for_magic0: pass
arm64_fake_sigreturn_duplicated_fpsimd: pass
arm64_fake_sigreturn_misaligned_sp: pass
arm64_fake_sigreturn_missing_fpsimd: pass
arm64_fake_sigreturn_sme_change_vl: skip
arm64_fake_sigreturn_sve_change_vl: skip
arm64_fp-stress: pass
arm64_fp-stress_FPSIMD-0-0: pass
arm64_fp-stress_FPSIMD-0-1: pass
arm64_fp-stress_FPSIMD-1-0: pass
arm64_fp-stress_FPSIMD-1-1: pass
arm64_fp-stress_FPSIMD-2-0: pass
arm64_fp-stress_FPSIMD-2-1: pass
arm64_fp-stress_FPSIMD-3-0: pass
arm64_fp-stress_FPSIMD-3-1: pass
arm64_fp-stress_FPSIMD-4-0: pass
arm64_fp-stress_FPSIMD-4-1: pass
arm64_fp-stress_FPSIMD-5-0: pass
arm64_fp-stress_FPSIMD-5-1: pass
arm64_fp-stress_FPSIMD-6-0: pass
arm64_fp-stress_FPSIMD-6-1: pass
arm64_fp-stress_FPSIMD-7-0: pass
arm64_fp-stress_FPSIMD-7-1: pass
arm64_hwcap: pass
arm64_hwcap_cpuinfo_match_RNG: pass
arm64_hwcap_cpuinfo_match_SME: pass
arm64_hwcap_cpuinfo_match_SVE: pass
arm64_hwcap_cpuinfo_match_SVE2_BF16: pass
arm64_hwcap_cpuinfo_match_SVE2_BITPERM: pass
arm64_hwcap_cpuinfo_match_SVE2_EBF16: pass
arm64_hwcap_cpuinfo_match_SVE2_F32MM: pass
arm64_hwcap_cpuinfo_match_SVE2_F64MM: pass
arm64_hwcap_cpuinfo_match_SVE2_I8MM: pass
arm64_hwcap_cpuinfo_match_SVE2_PMULL: pass
arm64_hwcap_cpuinfo_match_SVE2_SHA3: pass
arm64_hwcap_cpuinfo_match_SVE2_SM4: pass
arm64_hwcap_cpuinfo_match_SVE_2: pass
arm64_hwcap_cpuinfo_match_SVE_AES: pass
arm64_hwcap_sigill_RNG: skip
arm64_hwcap_sigill_SME: pass
arm64_hwcap_sigill_SVE: pass
arm64_hwcap_sigill_SVE2_BF16: skip
arm64_hwcap_sigill_SVE2_BITPERM: skip
arm64_hwcap_sigill_SVE2_EBF16: skip
arm64_hwcap_sigill_SVE2_F32MM: skip
arm64_hwcap_sigill_SVE2_F64MM: skip
arm64_hwcap_sigill_SVE2_I8MM: skip
arm64_hwcap_sigill_SVE2_PMULL: skip
arm64_hwcap_sigill_SVE2_SHA3: skip
arm64_hwcap_sigill_SVE2_SM4: skip
arm64_hwcap_sigill_SVE_2: skip
arm64_hwcap_sigill_SVE_AES: skip
arm64_mangle_pstate_invalid_compat_toggle: pass
arm64_mangle_pstate_invalid_daif_bits: pass
arm64_mangle_pstate_invalid_mode_el1h: pass
arm64_mangle_pstate_invalid_mode_el1t: pass
arm64_mangle_pstate_invalid_mode_el2h: pass
arm64_mangle_pstate_invalid_mode_el2t: pass
arm64_mangle_pstate_invalid_mode_el3h: pass
arm64_mangle_pstate_invalid_mode_el3t: pass
arm64_nobtitest: pass
arm64_nobtitest_bti_c_func_call_using_blr: skip
arm64_nobtitest_bti_c_func_call_using_br_x0: skip
arm64_nobtitest_bti_c_func_call_using_br_x16: skip
arm64_nobtitest_bti_j_func_call_using_blr: skip
arm64_nobtitest_bti_j_func_call_using_br_x0: skip
arm64_nobtitest_bti_j_func_call_using_br_x16: skip
arm64_nobtitest_bti_jc_func_call_using_blr: skip
arm64_nobtitest_bti_jc_func_call_using_br_x0: skip
arm64_nobtitest_bti_jc_func_call_using_br_x16: skip
arm64_nobtitest_bti_none_func_call_using_blr: skip
arm64_nobtitest_bti_none_func_call_using_br_x0: skip
arm64_nobtitest_bti_none_func_call_using_br_x16: skip
arm64_nobtitest_nohint_func_call_using_blr: skip
arm64_nobtitest_nohint_func_call_using_br_x0: skip
arm64_nobtitest_nohint_func_call_using_br_x16: skip
arm64_nobtitest_paciasp_func_call_using_blr: skip
arm64_nobtitest_paciasp_func_call_using_br_x0: skip
arm64_nobtitest_paciasp_func_call_using_br_x16: skip
arm64_pac: pass
arm64_pac_Generic_PAUTH_not_enabled: skip
arm64_pac_PAUTH_not_enabled: skip
arm64_ptrace: pass
arm64_ptrace_count_tpidrs: pass
arm64_ptrace_read_tpidr_one: pass
arm64_ptrace_tpidr2_read: pass
arm64_ptrace_tpidr2_write: pass
arm64_ptrace_verify_tpidr_one: pass
arm64_ptrace_write_tpidr_one: pass
arm64_ptrace_write_tpidr_only: pass
arm64_run_tags_test_sh: pass
arm64_sme_trap_no_sm: skip
arm64_sme_trap_non_streaming: skip
arm64_sme_trap_za: pass
arm64_sme_vl: skip
arm64_ssve_regs: skip
arm64_sve-probe-vls: skip
arm64_sve-probe-vls_SVE_not_available: skip
arm64_sve-ptrace: skip
arm64_sve-ptrace_SVE_not_available: skip
arm64_sve_regs: skip
arm64_sve_vl: skip
arm64_syscall-abi: pass
arm64_syscall-abi_getpid_FPSIMD: pass
arm64_syscall-abi_sched_yield_FPSIMD: pass
arm64_tags_test: pass
arm64_tpidr2: pass
arm64_tpidr2_skipped_TPIDR2_not_supported: pass
arm64_vec-syscfg: pass
arm64_vec-syscfg_SME_not_supported: skip
arm64_vec-syscfg_SVE_not_supported: skip
arm64_za-fork: pass
arm64_za-fork_skipped: pass
arm64_za-ptrace: skip
arm64_za-ptrace_SME_not_available: skip
arm64_za_no_regs: skip
arm64_za_regs: skip
12555 22:14:57.598412 end: 3.1 lava-test-shell (duration 00:00:29) [common]
12556 22:14:57.598496 end: 3 lava-test-retry (duration 00:00:29) [common]
12557 22:14:57.598581 start: 4 finalize (timeout 00:07:28) [common]
12558 22:14:57.598671 start: 4.1 power-off (timeout 00:00:30) [common]
12559 22:14:57.598826 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=off'
12560 22:14:57.673829 >> Command sent successfully.
12561 22:14:57.676194 Returned 0 in 0 seconds
12562 22:14:57.776561 end: 4.1 power-off (duration 00:00:00) [common]
12564 22:14:57.776887 start: 4.2 read-feedback (timeout 00:07:28) [common]
12565 22:14:57.777145 Listened to connection for namespace 'common' for up to 1s
12566 22:14:58.778100 Finalising connection for namespace 'common'
12567 22:14:58.778283 Disconnecting from shell: Finalise
12568 22:14:58.778363 / #
12569 22:14:58.878673 end: 4.2 read-feedback (duration 00:00:01) [common]
12570 22:14:58.878847 end: 4 finalize (duration 00:00:01) [common]
12571 22:14:58.878959 Cleaning after the job
12572 22:14:58.879065 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10583852/tftp-deploy-8m8yc9em/ramdisk
12573 22:14:58.881077 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10583852/tftp-deploy-8m8yc9em/kernel
12574 22:14:58.889957 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10583852/tftp-deploy-8m8yc9em/dtb
12575 22:14:58.890164 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10583852/tftp-deploy-8m8yc9em/nfsrootfs
12576 22:14:58.955744 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10583852/tftp-deploy-8m8yc9em/modules
12577 22:14:58.961129 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10583852
12578 22:14:59.491969 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10583852
12579 22:14:59.492152 Job finished correctly