Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 48
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 30
1 22:15:07.939666 lava-dispatcher, installed at version: 2023.03
2 22:15:07.939856 start: 0 validate
3 22:15:07.939978 Start time: 2023-06-04 22:15:07.939970+00:00 (UTC)
4 22:15:07.940097 Using caching service: 'http://localhost/cache/?uri=%s'
5 22:15:07.940225 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-libcamera%2F20230527.0%2Farm64%2Finitrd.cpio.gz exists
6 22:15:08.233988 Using caching service: 'http://localhost/cache/?uri=%s'
7 22:15:08.234832 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1281-g84d5372e0f314%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 22:15:08.519640 Using caching service: 'http://localhost/cache/?uri=%s'
9 22:15:08.520449 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1281-g84d5372e0f314%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 22:15:08.812765 Using caching service: 'http://localhost/cache/?uri=%s'
11 22:15:08.813557 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-libcamera%2F20230527.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 22:15:09.103782 Using caching service: 'http://localhost/cache/?uri=%s'
13 22:15:09.104540 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1281-g84d5372e0f314%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 22:15:09.398687 validate duration: 1.46
16 22:15:09.399977 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 22:15:09.400563 start: 1.1 download-retry (timeout 00:10:00) [common]
18 22:15:09.401068 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 22:15:09.401689 Not decompressing ramdisk as can be used compressed.
20 22:15:09.402164 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-libcamera/20230527.0/arm64/initrd.cpio.gz
21 22:15:09.402576 saving as /var/lib/lava/dispatcher/tmp/10583896/tftp-deploy-406nn8fa/ramdisk/initrd.cpio.gz
22 22:15:09.402934 total size: 4665273 (4MB)
23 22:15:09.408991 progress 0% (0MB)
24 22:15:09.416527 progress 5% (0MB)
25 22:15:09.423682 progress 10% (0MB)
26 22:15:09.428595 progress 15% (0MB)
27 22:15:09.432296 progress 20% (0MB)
28 22:15:09.435398 progress 25% (1MB)
29 22:15:09.438154 progress 30% (1MB)
30 22:15:09.440563 progress 35% (1MB)
31 22:15:09.442878 progress 40% (1MB)
32 22:15:09.445236 progress 45% (2MB)
33 22:15:09.447209 progress 50% (2MB)
34 22:15:09.449133 progress 55% (2MB)
35 22:15:09.450886 progress 60% (2MB)
36 22:15:09.452618 progress 65% (2MB)
37 22:15:09.454279 progress 70% (3MB)
38 22:15:09.455814 progress 75% (3MB)
39 22:15:09.457338 progress 80% (3MB)
40 22:15:09.459053 progress 85% (3MB)
41 22:15:09.460425 progress 90% (4MB)
42 22:15:09.461801 progress 95% (4MB)
43 22:15:09.463198 progress 100% (4MB)
44 22:15:09.463369 4MB downloaded in 0.06s (73.61MB/s)
45 22:15:09.463534 end: 1.1.1 http-download (duration 00:00:00) [common]
47 22:15:09.463815 end: 1.1 download-retry (duration 00:00:00) [common]
48 22:15:09.463906 start: 1.2 download-retry (timeout 00:10:00) [common]
49 22:15:09.463995 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 22:15:09.464126 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1281-g84d5372e0f314/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 22:15:09.464203 saving as /var/lib/lava/dispatcher/tmp/10583896/tftp-deploy-406nn8fa/kernel/Image
52 22:15:09.464268 total size: 45746688 (43MB)
53 22:15:09.464331 No compression specified
54 22:15:09.465454 progress 0% (0MB)
55 22:15:09.476788 progress 5% (2MB)
56 22:15:09.488060 progress 10% (4MB)
57 22:15:09.499314 progress 15% (6MB)
58 22:15:09.510632 progress 20% (8MB)
59 22:15:09.522188 progress 25% (10MB)
60 22:15:09.533520 progress 30% (13MB)
61 22:15:09.544944 progress 35% (15MB)
62 22:15:09.556384 progress 40% (17MB)
63 22:15:09.567607 progress 45% (19MB)
64 22:15:09.578850 progress 50% (21MB)
65 22:15:09.589912 progress 55% (24MB)
66 22:15:09.601242 progress 60% (26MB)
67 22:15:09.612616 progress 65% (28MB)
68 22:15:09.623945 progress 70% (30MB)
69 22:15:09.635535 progress 75% (32MB)
70 22:15:09.646794 progress 80% (34MB)
71 22:15:09.658190 progress 85% (37MB)
72 22:15:09.669503 progress 90% (39MB)
73 22:15:09.680592 progress 95% (41MB)
74 22:15:09.691695 progress 100% (43MB)
75 22:15:09.691810 43MB downloaded in 0.23s (191.74MB/s)
76 22:15:09.691957 end: 1.2.1 http-download (duration 00:00:00) [common]
78 22:15:09.692184 end: 1.2 download-retry (duration 00:00:00) [common]
79 22:15:09.692271 start: 1.3 download-retry (timeout 00:10:00) [common]
80 22:15:09.692356 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 22:15:09.692488 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1281-g84d5372e0f314/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 22:15:09.692558 saving as /var/lib/lava/dispatcher/tmp/10583896/tftp-deploy-406nn8fa/dtb/mt8192-asurada-spherion-r0.dtb
83 22:15:09.692625 total size: 46924 (0MB)
84 22:15:09.692685 No compression specified
85 22:15:09.693796 progress 69% (0MB)
86 22:15:09.694062 progress 100% (0MB)
87 22:15:09.694211 0MB downloaded in 0.00s (28.26MB/s)
88 22:15:09.694329 end: 1.3.1 http-download (duration 00:00:00) [common]
90 22:15:09.694590 end: 1.3 download-retry (duration 00:00:00) [common]
91 22:15:09.694676 start: 1.4 download-retry (timeout 00:10:00) [common]
92 22:15:09.694759 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 22:15:09.694866 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-libcamera/20230527.0/arm64/full.rootfs.tar.xz
94 22:15:09.694934 saving as /var/lib/lava/dispatcher/tmp/10583896/tftp-deploy-406nn8fa/nfsrootfs/full.rootfs.tar
95 22:15:09.694993 total size: 89386020 (85MB)
96 22:15:09.695055 Using unxz to decompress xz
97 22:15:09.700286 progress 0% (0MB)
98 22:15:09.909643 progress 5% (4MB)
99 22:15:10.119613 progress 10% (8MB)
100 22:15:10.364590 progress 15% (12MB)
101 22:15:10.553430 progress 20% (17MB)
102 22:15:10.645007 progress 25% (21MB)
103 22:15:10.886160 progress 30% (25MB)
104 22:15:11.163818 progress 35% (29MB)
105 22:15:11.420546 progress 40% (34MB)
106 22:15:11.673074 progress 45% (38MB)
107 22:15:11.913196 progress 50% (42MB)
108 22:15:12.167077 progress 55% (46MB)
109 22:15:12.410167 progress 60% (51MB)
110 22:15:12.670885 progress 65% (55MB)
111 22:15:12.958716 progress 70% (59MB)
112 22:15:13.251200 progress 75% (63MB)
113 22:15:13.535785 progress 80% (68MB)
114 22:15:13.779456 progress 85% (72MB)
115 22:15:14.000529 progress 90% (76MB)
116 22:15:14.249228 progress 95% (81MB)
117 22:15:14.504440 progress 100% (85MB)
118 22:15:14.510537 85MB downloaded in 4.82s (17.70MB/s)
119 22:15:14.510826 end: 1.4.1 http-download (duration 00:00:05) [common]
121 22:15:14.511083 end: 1.4 download-retry (duration 00:00:05) [common]
122 22:15:14.511173 start: 1.5 download-retry (timeout 00:09:55) [common]
123 22:15:14.511261 start: 1.5.1 http-download (timeout 00:09:55) [common]
124 22:15:14.511434 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1281-g84d5372e0f314/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 22:15:14.511519 saving as /var/lib/lava/dispatcher/tmp/10583896/tftp-deploy-406nn8fa/modules/modules.tar
126 22:15:14.511581 total size: 8541948 (8MB)
127 22:15:14.511644 Using unxz to decompress xz
128 22:15:14.515356 progress 0% (0MB)
129 22:15:14.537054 progress 5% (0MB)
130 22:15:14.561888 progress 10% (0MB)
131 22:15:14.586951 progress 15% (1MB)
132 22:15:14.611440 progress 20% (1MB)
133 22:15:14.634380 progress 25% (2MB)
134 22:15:14.660772 progress 30% (2MB)
135 22:15:14.685078 progress 35% (2MB)
136 22:15:14.708844 progress 40% (3MB)
137 22:15:14.732054 progress 45% (3MB)
138 22:15:14.756470 progress 50% (4MB)
139 22:15:14.779136 progress 55% (4MB)
140 22:15:14.802881 progress 60% (4MB)
141 22:15:14.827455 progress 65% (5MB)
142 22:15:14.851599 progress 70% (5MB)
143 22:15:14.874405 progress 75% (6MB)
144 22:15:14.897610 progress 80% (6MB)
145 22:15:14.921682 progress 85% (6MB)
146 22:15:14.949885 progress 90% (7MB)
147 22:15:14.974756 progress 95% (7MB)
148 22:15:14.998211 progress 100% (8MB)
149 22:15:15.003905 8MB downloaded in 0.49s (16.55MB/s)
150 22:15:15.004163 end: 1.5.1 http-download (duration 00:00:00) [common]
152 22:15:15.004419 end: 1.5 download-retry (duration 00:00:00) [common]
153 22:15:15.004510 start: 1.6 prepare-tftp-overlay (timeout 00:09:54) [common]
154 22:15:15.004605 start: 1.6.1 extract-nfsrootfs (timeout 00:09:54) [common]
155 22:15:16.517959 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/10583896/extract-nfsrootfs-cnr11rcj
156 22:15:16.518163 end: 1.6.1 extract-nfsrootfs (duration 00:00:02) [common]
157 22:15:16.518263 start: 1.6.2 lava-overlay (timeout 00:09:53) [common]
158 22:15:16.518617 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10583896/lava-overlay-65dg2d6m
159 22:15:16.518743 makedir: /var/lib/lava/dispatcher/tmp/10583896/lava-overlay-65dg2d6m/lava-10583896/bin
160 22:15:16.518842 makedir: /var/lib/lava/dispatcher/tmp/10583896/lava-overlay-65dg2d6m/lava-10583896/tests
161 22:15:16.518938 makedir: /var/lib/lava/dispatcher/tmp/10583896/lava-overlay-65dg2d6m/lava-10583896/results
162 22:15:16.519037 Creating /var/lib/lava/dispatcher/tmp/10583896/lava-overlay-65dg2d6m/lava-10583896/bin/lava-add-keys
163 22:15:16.519172 Creating /var/lib/lava/dispatcher/tmp/10583896/lava-overlay-65dg2d6m/lava-10583896/bin/lava-add-sources
164 22:15:16.519296 Creating /var/lib/lava/dispatcher/tmp/10583896/lava-overlay-65dg2d6m/lava-10583896/bin/lava-background-process-start
165 22:15:16.519418 Creating /var/lib/lava/dispatcher/tmp/10583896/lava-overlay-65dg2d6m/lava-10583896/bin/lava-background-process-stop
166 22:15:16.519538 Creating /var/lib/lava/dispatcher/tmp/10583896/lava-overlay-65dg2d6m/lava-10583896/bin/lava-common-functions
167 22:15:16.519657 Creating /var/lib/lava/dispatcher/tmp/10583896/lava-overlay-65dg2d6m/lava-10583896/bin/lava-echo-ipv4
168 22:15:16.519774 Creating /var/lib/lava/dispatcher/tmp/10583896/lava-overlay-65dg2d6m/lava-10583896/bin/lava-install-packages
169 22:15:16.519891 Creating /var/lib/lava/dispatcher/tmp/10583896/lava-overlay-65dg2d6m/lava-10583896/bin/lava-installed-packages
170 22:15:16.520006 Creating /var/lib/lava/dispatcher/tmp/10583896/lava-overlay-65dg2d6m/lava-10583896/bin/lava-os-build
171 22:15:16.520123 Creating /var/lib/lava/dispatcher/tmp/10583896/lava-overlay-65dg2d6m/lava-10583896/bin/lava-probe-channel
172 22:15:16.520239 Creating /var/lib/lava/dispatcher/tmp/10583896/lava-overlay-65dg2d6m/lava-10583896/bin/lava-probe-ip
173 22:15:16.520357 Creating /var/lib/lava/dispatcher/tmp/10583896/lava-overlay-65dg2d6m/lava-10583896/bin/lava-target-ip
174 22:15:16.520473 Creating /var/lib/lava/dispatcher/tmp/10583896/lava-overlay-65dg2d6m/lava-10583896/bin/lava-target-mac
175 22:15:16.520590 Creating /var/lib/lava/dispatcher/tmp/10583896/lava-overlay-65dg2d6m/lava-10583896/bin/lava-target-storage
176 22:15:16.520708 Creating /var/lib/lava/dispatcher/tmp/10583896/lava-overlay-65dg2d6m/lava-10583896/bin/lava-test-case
177 22:15:16.520826 Creating /var/lib/lava/dispatcher/tmp/10583896/lava-overlay-65dg2d6m/lava-10583896/bin/lava-test-event
178 22:15:16.520943 Creating /var/lib/lava/dispatcher/tmp/10583896/lava-overlay-65dg2d6m/lava-10583896/bin/lava-test-feedback
179 22:15:16.521060 Creating /var/lib/lava/dispatcher/tmp/10583896/lava-overlay-65dg2d6m/lava-10583896/bin/lava-test-raise
180 22:15:16.521209 Creating /var/lib/lava/dispatcher/tmp/10583896/lava-overlay-65dg2d6m/lava-10583896/bin/lava-test-reference
181 22:15:16.521326 Creating /var/lib/lava/dispatcher/tmp/10583896/lava-overlay-65dg2d6m/lava-10583896/bin/lava-test-runner
182 22:15:16.521445 Creating /var/lib/lava/dispatcher/tmp/10583896/lava-overlay-65dg2d6m/lava-10583896/bin/lava-test-set
183 22:15:16.521562 Creating /var/lib/lava/dispatcher/tmp/10583896/lava-overlay-65dg2d6m/lava-10583896/bin/lava-test-shell
184 22:15:16.521679 Updating /var/lib/lava/dispatcher/tmp/10583896/lava-overlay-65dg2d6m/lava-10583896/bin/lava-install-packages (oe)
185 22:15:16.521824 Updating /var/lib/lava/dispatcher/tmp/10583896/lava-overlay-65dg2d6m/lava-10583896/bin/lava-installed-packages (oe)
186 22:15:16.521941 Creating /var/lib/lava/dispatcher/tmp/10583896/lava-overlay-65dg2d6m/lava-10583896/environment
187 22:15:16.522033 LAVA metadata
188 22:15:16.522103 - LAVA_JOB_ID=10583896
189 22:15:16.522166 - LAVA_DISPATCHER_IP=192.168.201.1
190 22:15:16.522263 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:53) [common]
191 22:15:16.522330 skipped lava-vland-overlay
192 22:15:16.522446 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
193 22:15:16.522524 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:53) [common]
194 22:15:16.522586 skipped lava-multinode-overlay
195 22:15:16.522659 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
196 22:15:16.522736 start: 1.6.2.3 test-definition (timeout 00:09:53) [common]
197 22:15:16.522807 Loading test definitions
198 22:15:16.522903 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:53) [common]
199 22:15:16.522973 Using /lava-10583896 at stage 0
200 22:15:16.523245 uuid=10583896_1.6.2.3.1 testdef=None
201 22:15:16.523333 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
202 22:15:16.523416 start: 1.6.2.3.2 test-overlay (timeout 00:09:53) [common]
203 22:15:16.523876 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
205 22:15:16.524095 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:53) [common]
206 22:15:16.524666 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
208 22:15:16.524892 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:53) [common]
209 22:15:16.525454 runner path: /var/lib/lava/dispatcher/tmp/10583896/lava-overlay-65dg2d6m/lava-10583896/0/tests/0_lc-compliance test_uuid 10583896_1.6.2.3.1
210 22:15:16.525604 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
212 22:15:16.525806 Creating lava-test-runner.conf files
213 22:15:16.525869 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10583896/lava-overlay-65dg2d6m/lava-10583896/0 for stage 0
214 22:15:16.525954 - 0_lc-compliance
215 22:15:16.526049 end: 1.6.2.3 test-definition (duration 00:00:00) [common]
216 22:15:16.526132 start: 1.6.2.4 compress-overlay (timeout 00:09:53) [common]
217 22:15:16.531684 end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
218 22:15:16.531785 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:53) [common]
219 22:15:16.531869 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
220 22:15:16.531952 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
221 22:15:16.532036 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:53) [common]
222 22:15:16.642080 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
223 22:15:16.642500 start: 1.6.4 extract-modules (timeout 00:09:53) [common]
224 22:15:16.642611 extracting modules file /var/lib/lava/dispatcher/tmp/10583896/tftp-deploy-406nn8fa/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10583896/extract-nfsrootfs-cnr11rcj
225 22:15:16.836943 extracting modules file /var/lib/lava/dispatcher/tmp/10583896/tftp-deploy-406nn8fa/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10583896/extract-overlay-ramdisk-1qmkqm3n/ramdisk
226 22:15:17.035808 end: 1.6.4 extract-modules (duration 00:00:00) [common]
227 22:15:17.035982 start: 1.6.5 apply-overlay-tftp (timeout 00:09:52) [common]
228 22:15:17.036076 [common] Applying overlay to NFS
229 22:15:17.036147 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10583896/compress-overlay-mhh_uitc/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10583896/extract-nfsrootfs-cnr11rcj
230 22:15:17.042128 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
231 22:15:17.042237 start: 1.6.6 configure-preseed-file (timeout 00:09:52) [common]
232 22:15:17.042330 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
233 22:15:17.042463 start: 1.6.7 compress-ramdisk (timeout 00:09:52) [common]
234 22:15:17.042540 Building ramdisk /var/lib/lava/dispatcher/tmp/10583896/extract-overlay-ramdisk-1qmkqm3n/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10583896/extract-overlay-ramdisk-1qmkqm3n/ramdisk
235 22:15:17.335388 >> 117799 blocks
236 22:15:19.181116 rename /var/lib/lava/dispatcher/tmp/10583896/extract-overlay-ramdisk-1qmkqm3n/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10583896/tftp-deploy-406nn8fa/ramdisk/ramdisk.cpio.gz
237 22:15:19.181536 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
238 22:15:19.181649 start: 1.6.8 prepare-kernel (timeout 00:09:50) [common]
239 22:15:19.181743 start: 1.6.8.1 prepare-fit (timeout 00:09:50) [common]
240 22:15:19.181846 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10583896/tftp-deploy-406nn8fa/kernel/Image'
241 22:15:30.340998 Returned 0 in 11 seconds
242 22:15:30.442024 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10583896/tftp-deploy-406nn8fa/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10583896/tftp-deploy-406nn8fa/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10583896/tftp-deploy-406nn8fa/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10583896/tftp-deploy-406nn8fa/kernel/image.itb
243 22:15:30.831353 output: FIT description: Kernel Image image with one or more FDT blobs
244 22:15:30.831698 output: Created: Sun Jun 4 23:15:30 2023
245 22:15:30.831773 output: Image 0 (kernel-1)
246 22:15:30.831902 output: Description:
247 22:15:30.831979 output: Created: Sun Jun 4 23:15:30 2023
248 22:15:30.832039 output: Type: Kernel Image
249 22:15:30.832098 output: Compression: lzma compressed
250 22:15:30.832154 output: Data Size: 10081729 Bytes = 9845.44 KiB = 9.61 MiB
251 22:15:30.832212 output: Architecture: AArch64
252 22:15:30.832268 output: OS: Linux
253 22:15:30.832326 output: Load Address: 0x00000000
254 22:15:30.832383 output: Entry Point: 0x00000000
255 22:15:30.832438 output: Hash algo: crc32
256 22:15:30.832491 output: Hash value: 3b3111d8
257 22:15:30.832543 output: Image 1 (fdt-1)
258 22:15:30.832595 output: Description: mt8192-asurada-spherion-r0
259 22:15:30.832646 output: Created: Sun Jun 4 23:15:30 2023
260 22:15:30.832697 output: Type: Flat Device Tree
261 22:15:30.832749 output: Compression: uncompressed
262 22:15:30.832800 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
263 22:15:30.832851 output: Architecture: AArch64
264 22:15:30.832902 output: Hash algo: crc32
265 22:15:30.832953 output: Hash value: 1df858fa
266 22:15:30.833005 output: Image 2 (ramdisk-1)
267 22:15:30.833055 output: Description: unavailable
268 22:15:30.833107 output: Created: Sun Jun 4 23:15:30 2023
269 22:15:30.833158 output: Type: RAMDisk Image
270 22:15:30.833209 output: Compression: Unknown Compression
271 22:15:30.833260 output: Data Size: 17644514 Bytes = 17230.97 KiB = 16.83 MiB
272 22:15:30.833312 output: Architecture: AArch64
273 22:15:30.833362 output: OS: Linux
274 22:15:30.833413 output: Load Address: unavailable
275 22:15:30.833465 output: Entry Point: unavailable
276 22:15:30.833515 output: Hash algo: crc32
277 22:15:30.833566 output: Hash value: 09f275b2
278 22:15:30.833617 output: Default Configuration: 'conf-1'
279 22:15:30.833668 output: Configuration 0 (conf-1)
280 22:15:30.833719 output: Description: mt8192-asurada-spherion-r0
281 22:15:30.833769 output: Kernel: kernel-1
282 22:15:30.833837 output: Init Ramdisk: ramdisk-1
283 22:15:30.833891 output: FDT: fdt-1
284 22:15:30.833943 output: Loadables: kernel-1
285 22:15:30.833994 output:
286 22:15:30.834176 end: 1.6.8.1 prepare-fit (duration 00:00:12) [common]
287 22:15:30.834273 end: 1.6.8 prepare-kernel (duration 00:00:12) [common]
288 22:15:30.834409 end: 1.6 prepare-tftp-overlay (duration 00:00:16) [common]
289 22:15:30.834516 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:39) [common]
290 22:15:30.834593 No LXC device requested
291 22:15:30.834670 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
292 22:15:30.834749 start: 1.8 deploy-device-env (timeout 00:09:39) [common]
293 22:15:30.834823 end: 1.8 deploy-device-env (duration 00:00:00) [common]
294 22:15:30.834884 Checking files for TFTP limit of 4294967296 bytes.
295 22:15:30.835347 end: 1 tftp-deploy (duration 00:00:21) [common]
296 22:15:30.835445 start: 2 depthcharge-action (timeout 00:05:00) [common]
297 22:15:30.835531 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
298 22:15:30.835660 substitutions:
299 22:15:30.835727 - {DTB}: 10583896/tftp-deploy-406nn8fa/dtb/mt8192-asurada-spherion-r0.dtb
300 22:15:30.835790 - {INITRD}: 10583896/tftp-deploy-406nn8fa/ramdisk/ramdisk.cpio.gz
301 22:15:30.835852 - {KERNEL}: 10583896/tftp-deploy-406nn8fa/kernel/Image
302 22:15:30.835908 - {LAVA_MAC}: None
303 22:15:30.835964 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/10583896/extract-nfsrootfs-cnr11rcj
304 22:15:30.836019 - {NFS_SERVER_IP}: 192.168.201.1
305 22:15:30.836072 - {PRESEED_CONFIG}: None
306 22:15:30.836124 - {PRESEED_LOCAL}: None
307 22:15:30.836176 - {RAMDISK}: 10583896/tftp-deploy-406nn8fa/ramdisk/ramdisk.cpio.gz
308 22:15:30.836229 - {ROOT_PART}: None
309 22:15:30.836281 - {ROOT}: None
310 22:15:30.836333 - {SERVER_IP}: 192.168.201.1
311 22:15:30.836385 - {TEE}: None
312 22:15:30.836436 Parsed boot commands:
313 22:15:30.836488 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
314 22:15:30.836659 Parsed boot commands: tftpboot 192.168.201.1 10583896/tftp-deploy-406nn8fa/kernel/image.itb 10583896/tftp-deploy-406nn8fa/kernel/cmdline
315 22:15:30.836744 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
316 22:15:30.836826 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
317 22:15:30.836919 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
318 22:15:30.837002 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
319 22:15:30.837068 Not connected, no need to disconnect.
320 22:15:30.837138 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
321 22:15:30.837216 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
322 22:15:30.837280 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-1'
323 22:15:30.840682 Setting prompt string to ['lava-test: # ']
324 22:15:30.840997 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
325 22:15:30.841104 end: 2.2.1 reset-connection (duration 00:00:00) [common]
326 22:15:30.841194 start: 2.2.2 reset-device (timeout 00:05:00) [common]
327 22:15:30.841283 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
328 22:15:30.841467 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=reboot'
329 22:15:35.983105 >> Command sent successfully.
330 22:15:35.989080 Returned 0 in 5 seconds
331 22:15:36.089855 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
333 22:15:36.091464 end: 2.2.2 reset-device (duration 00:00:05) [common]
334 22:15:36.092036 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
335 22:15:36.092536 Setting prompt string to 'Starting depthcharge on Spherion...'
336 22:15:36.092925 Changing prompt to 'Starting depthcharge on Spherion...'
337 22:15:36.093374 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
338 22:15:36.094925 [Enter `^Ec?' for help]
339 22:15:36.262564
340 22:15:36.263174
341 22:15:36.263575 F0: 102B 0000
342 22:15:36.263937
343 22:15:36.264272 F3: 1001 0000 [0200]
344 22:15:36.264601
345 22:15:36.266040 F3: 1001 0000
346 22:15:36.266675
347 22:15:36.267064 F7: 102D 0000
348 22:15:36.267422
349 22:15:36.269763 F1: 0000 0000
350 22:15:36.270153
351 22:15:36.270578 V0: 0000 0000 [0001]
352 22:15:36.271146
353 22:15:36.271743 00: 0007 8000
354 22:15:36.272118
355 22:15:36.273490 01: 0000 0000
356 22:15:36.273976
357 22:15:36.274389 BP: 0C00 0209 [0000]
358 22:15:36.274757
359 22:15:36.277320 G0: 1182 0000
360 22:15:36.277795
361 22:15:36.278171 EC: 0000 0021 [4000]
362 22:15:36.278577
363 22:15:36.280642 S7: 0000 0000 [0000]
364 22:15:36.281121
365 22:15:36.281498 CC: 0000 0000 [0001]
366 22:15:36.281858
367 22:15:36.284335 T0: 0000 0040 [010F]
368 22:15:36.284817
369 22:15:36.285196 Jump to BL
370 22:15:36.285546
371 22:15:36.309526
372 22:15:36.310098
373 22:15:36.310511
374 22:15:36.316401 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
375 22:15:36.320813 ARM64: Exception handlers installed.
376 22:15:36.324437 ARM64: Testing exception
377 22:15:36.328749 ARM64: Done test exception
378 22:15:36.335718 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
379 22:15:36.342167 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
380 22:15:36.352380 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
381 22:15:36.362748 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
382 22:15:36.369282 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
383 22:15:36.375981 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
384 22:15:36.386294 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
385 22:15:36.393455 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
386 22:15:36.412265 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
387 22:15:36.415330 WDT: Last reset was cold boot
388 22:15:36.418929 SPI1(PAD0) initialized at 2873684 Hz
389 22:15:36.422009 SPI5(PAD0) initialized at 992727 Hz
390 22:15:36.425643 VBOOT: Loading verstage.
391 22:15:36.431988 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
392 22:15:36.435173 FMAP: Found "FLASH" version 1.1 at 0x20000.
393 22:15:36.439231 FMAP: base = 0x0 size = 0x800000 #areas = 25
394 22:15:36.441769 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
395 22:15:36.449874 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
396 22:15:36.456682 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
397 22:15:36.467122 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
398 22:15:36.467703
399 22:15:36.468086
400 22:15:36.477314 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
401 22:15:36.480650 ARM64: Exception handlers installed.
402 22:15:36.483804 ARM64: Testing exception
403 22:15:36.484389 ARM64: Done test exception
404 22:15:36.490492 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
405 22:15:36.493533 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
406 22:15:36.508584 Probing TPM: . done!
407 22:15:36.509168 TPM ready after 0 ms
408 22:15:36.515008 Connected to device vid:did:rid of 1ae0:0028:00
409 22:15:36.521893 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
410 22:15:36.525265 Initialized TPM device CR50 revision 0
411 22:15:36.591347 tlcl_send_startup: Startup return code is 0
412 22:15:36.591924 TPM: setup succeeded
413 22:15:36.602728 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
414 22:15:36.611756 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
415 22:15:36.618566 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
416 22:15:36.630621 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
417 22:15:36.633828 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
418 22:15:36.639657 in-header: 03 07 00 00 08 00 00 00
419 22:15:36.642893 in-data: aa e4 47 04 13 02 00 00
420 22:15:36.648333 Chrome EC: UHEPI supported
421 22:15:36.654400 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
422 22:15:36.658089 in-header: 03 ad 00 00 08 00 00 00
423 22:15:36.661307 in-data: 00 20 20 08 00 00 00 00
424 22:15:36.661848 Phase 1
425 22:15:36.665474 FMAP: area GBB found @ 3f5000 (12032 bytes)
426 22:15:36.672626 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
427 22:15:36.679974 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
428 22:15:36.680525 Recovery requested (1009000e)
429 22:15:36.690459 TPM: Extending digest for VBOOT: boot mode into PCR 0
430 22:15:36.696462 tlcl_extend: response is 0
431 22:15:36.706548 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
432 22:15:36.712414 tlcl_extend: response is 0
433 22:15:36.719029 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
434 22:15:36.739890 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
435 22:15:36.746958 BS: bootblock times (exec / console): total (unknown) / 148 ms
436 22:15:36.747570
437 22:15:36.747963
438 22:15:36.756733 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
439 22:15:36.760382 ARM64: Exception handlers installed.
440 22:15:36.760872 ARM64: Testing exception
441 22:15:36.763389 ARM64: Done test exception
442 22:15:36.785171 pmic_efuse_setting: Set efuses in 11 msecs
443 22:15:36.788763 pmwrap_interface_init: Select PMIF_VLD_RDY
444 22:15:36.795452 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
445 22:15:36.799927 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
446 22:15:36.805766 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
447 22:15:36.809237 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
448 22:15:36.812334 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
449 22:15:36.819581 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
450 22:15:36.823474 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
451 22:15:36.827342 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
452 22:15:36.834196 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
453 22:15:36.838437 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
454 22:15:36.841971 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
455 22:15:36.844811 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
456 22:15:36.851359 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
457 22:15:36.858153 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
458 22:15:36.861456 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
459 22:15:36.868478 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
460 22:15:36.875462 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
461 22:15:36.879550 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
462 22:15:36.886073 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
463 22:15:36.893915 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
464 22:15:36.896233 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
465 22:15:36.903709 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
466 22:15:36.906882 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
467 22:15:36.913861 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
468 22:15:36.920187 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
469 22:15:36.923613 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
470 22:15:36.931289 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
471 22:15:36.933285 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
472 22:15:36.941065 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
473 22:15:36.943593 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
474 22:15:36.950015 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
475 22:15:36.953027 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
476 22:15:36.959649 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
477 22:15:36.962823 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
478 22:15:36.969393 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
479 22:15:36.972867 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
480 22:15:36.979184 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
481 22:15:36.982603 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
482 22:15:36.989517 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
483 22:15:36.993133 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
484 22:15:36.996120 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
485 22:15:37.004189 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
486 22:15:37.006896 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
487 22:15:37.010319 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
488 22:15:37.013818 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
489 22:15:37.020484 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
490 22:15:37.024524 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
491 22:15:37.026858 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
492 22:15:37.030567 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
493 22:15:37.037484 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
494 22:15:37.040701 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
495 22:15:37.047260 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
496 22:15:37.057207 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
497 22:15:37.060733 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
498 22:15:37.070712 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
499 22:15:37.076969 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
500 22:15:37.083711 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
501 22:15:37.086826 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
502 22:15:37.089931 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
503 22:15:37.097733 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x30
504 22:15:37.104508 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
505 22:15:37.107660 [RTC]rtc_osc_init,62: osc32con val = 0xde70
506 22:15:37.114442 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
507 22:15:37.122892 [RTC]rtc_get_frequency_meter,154: input=15, output=773
508 22:15:37.131743 [RTC]rtc_get_frequency_meter,154: input=23, output=958
509 22:15:37.142323 [RTC]rtc_get_frequency_meter,154: input=19, output=863
510 22:15:37.151126 [RTC]rtc_get_frequency_meter,154: input=17, output=817
511 22:15:37.160587 [RTC]rtc_get_frequency_meter,154: input=16, output=795
512 22:15:37.163889 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
513 22:15:37.170282 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
514 22:15:37.174023 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
515 22:15:37.177438 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
516 22:15:37.181274 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
517 22:15:37.184316 ADC[4]: Raw value=903614 ID=7
518 22:15:37.187504 ADC[3]: Raw value=213179 ID=1
519 22:15:37.187991 RAM Code: 0x71
520 22:15:37.194673 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
521 22:15:37.198798 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
522 22:15:37.205702 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
523 22:15:37.213744 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
524 22:15:37.216739 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
525 22:15:37.220493 in-header: 03 07 00 00 08 00 00 00
526 22:15:37.224357 in-data: aa e4 47 04 13 02 00 00
527 22:15:37.227991 Chrome EC: UHEPI supported
528 22:15:37.231367 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
529 22:15:37.235087 in-header: 03 ed 00 00 08 00 00 00
530 22:15:37.239121 in-data: 80 20 60 08 00 00 00 00
531 22:15:37.242920 MRC: failed to locate region type 0.
532 22:15:37.249856 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
533 22:15:37.252302 DRAM-K: Running full calibration
534 22:15:37.259088 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
535 22:15:37.259675 header.status = 0x0
536 22:15:37.262821 header.version = 0x6 (expected: 0x6)
537 22:15:37.266035 header.size = 0xd00 (expected: 0xd00)
538 22:15:37.269222 header.flags = 0x0
539 22:15:37.275238 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
540 22:15:37.292768 read SPI 0x72590 0x1c583: 12501 us, 9287 KB/s, 74.296 Mbps
541 22:15:37.299486 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
542 22:15:37.303176 dram_init: ddr_geometry: 2
543 22:15:37.303780 [EMI] MDL number = 2
544 22:15:37.307902 [EMI] Get MDL freq = 0
545 22:15:37.308341 dram_init: ddr_type: 0
546 22:15:37.310647 is_discrete_lpddr4: 1
547 22:15:37.313821 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
548 22:15:37.314401
549 22:15:37.314831
550 22:15:37.317499 [Bian_co] ETT version 0.0.0.1
551 22:15:37.320931 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
552 22:15:37.321528
553 22:15:37.324565 dramc_set_vcore_voltage set vcore to 650000
554 22:15:37.328215 Read voltage for 800, 4
555 22:15:37.328753 Vio18 = 0
556 22:15:37.331345 Vcore = 650000
557 22:15:37.331903 Vdram = 0
558 22:15:37.332263 Vddq = 0
559 22:15:37.332589 Vmddr = 0
560 22:15:37.334491 dram_init: config_dvfs: 1
561 22:15:37.342023 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
562 22:15:37.344384 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
563 22:15:37.347707 [SwImpedanceCal] DRVP=10, DRVN=17, ODTN=9
564 22:15:37.354268 freq_region=0, Reg: DRVP=10, DRVN=17, ODTN=9
565 22:15:37.357586 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
566 22:15:37.361043 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
567 22:15:37.363851 MEM_TYPE=3, freq_sel=18
568 22:15:37.364289 sv_algorithm_assistance_LP4_1600
569 22:15:37.371063 ============ PULL DRAM RESETB DOWN ============
570 22:15:37.374044 ========== PULL DRAM RESETB DOWN end =========
571 22:15:37.377450 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
572 22:15:37.381258 ===================================
573 22:15:37.384073 LPDDR4 DRAM CONFIGURATION
574 22:15:37.387532 ===================================
575 22:15:37.390643 EX_ROW_EN[0] = 0x0
576 22:15:37.391186 EX_ROW_EN[1] = 0x0
577 22:15:37.394327 LP4Y_EN = 0x0
578 22:15:37.394909 WORK_FSP = 0x0
579 22:15:37.397429 WL = 0x2
580 22:15:37.397986 RL = 0x2
581 22:15:37.401024 BL = 0x2
582 22:15:37.401622 RPST = 0x0
583 22:15:37.403963 RD_PRE = 0x0
584 22:15:37.404500 WR_PRE = 0x1
585 22:15:37.407124 WR_PST = 0x0
586 22:15:37.407564 DBI_WR = 0x0
587 22:15:37.410545 DBI_RD = 0x0
588 22:15:37.410981 OTF = 0x1
589 22:15:37.413753 ===================================
590 22:15:37.417276 ===================================
591 22:15:37.421113 ANA top config
592 22:15:37.423635 ===================================
593 22:15:37.427028 DLL_ASYNC_EN = 0
594 22:15:37.427468 ALL_SLAVE_EN = 1
595 22:15:37.430610 NEW_RANK_MODE = 1
596 22:15:37.434043 DLL_IDLE_MODE = 1
597 22:15:37.437456 LP45_APHY_COMB_EN = 1
598 22:15:37.440628 TX_ODT_DIS = 1
599 22:15:37.441170 NEW_8X_MODE = 1
600 22:15:37.443948 ===================================
601 22:15:37.447038 ===================================
602 22:15:37.450510 data_rate = 1600
603 22:15:37.454214 CKR = 1
604 22:15:37.457380 DQ_P2S_RATIO = 8
605 22:15:37.460550 ===================================
606 22:15:37.463984 CA_P2S_RATIO = 8
607 22:15:37.464530 DQ_CA_OPEN = 0
608 22:15:37.467703 DQ_SEMI_OPEN = 0
609 22:15:37.470532 CA_SEMI_OPEN = 0
610 22:15:37.474161 CA_FULL_RATE = 0
611 22:15:37.477196 DQ_CKDIV4_EN = 1
612 22:15:37.480055 CA_CKDIV4_EN = 1
613 22:15:37.483737 CA_PREDIV_EN = 0
614 22:15:37.484278 PH8_DLY = 0
615 22:15:37.486774 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
616 22:15:37.490500 DQ_AAMCK_DIV = 4
617 22:15:37.493678 CA_AAMCK_DIV = 4
618 22:15:37.497416 CA_ADMCK_DIV = 4
619 22:15:37.497964 DQ_TRACK_CA_EN = 0
620 22:15:37.500125 CA_PICK = 800
621 22:15:37.503856 CA_MCKIO = 800
622 22:15:37.507084 MCKIO_SEMI = 0
623 22:15:37.510805 PLL_FREQ = 3068
624 22:15:37.513535 DQ_UI_PI_RATIO = 32
625 22:15:37.516316 CA_UI_PI_RATIO = 0
626 22:15:37.520551 ===================================
627 22:15:37.524124 ===================================
628 22:15:37.524683 memory_type:LPDDR4
629 22:15:37.526292 GP_NUM : 10
630 22:15:37.530140 SRAM_EN : 1
631 22:15:37.530857 MD32_EN : 0
632 22:15:37.534021 ===================================
633 22:15:37.536963 [ANA_INIT] >>>>>>>>>>>>>>
634 22:15:37.540873 <<<<<< [CONFIGURE PHASE]: ANA_TX
635 22:15:37.544073 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
636 22:15:37.547805 ===================================
637 22:15:37.548288 data_rate = 1600,PCW = 0X7600
638 22:15:37.551087 ===================================
639 22:15:37.555135 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
640 22:15:37.562544 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
641 22:15:37.566197 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
642 22:15:37.569925 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
643 22:15:37.573245 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
644 22:15:37.576771 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
645 22:15:37.579501 [ANA_INIT] flow start
646 22:15:37.582883 [ANA_INIT] PLL >>>>>>>>
647 22:15:37.583362 [ANA_INIT] PLL <<<<<<<<
648 22:15:37.586734 [ANA_INIT] MIDPI >>>>>>>>
649 22:15:37.589798 [ANA_INIT] MIDPI <<<<<<<<
650 22:15:37.593075 [ANA_INIT] DLL >>>>>>>>
651 22:15:37.593664 [ANA_INIT] flow end
652 22:15:37.596833 ============ LP4 DIFF to SE enter ============
653 22:15:37.603456 ============ LP4 DIFF to SE exit ============
654 22:15:37.604050 [ANA_INIT] <<<<<<<<<<<<<
655 22:15:37.606525 [Flow] Enable top DCM control >>>>>
656 22:15:37.609768 [Flow] Enable top DCM control <<<<<
657 22:15:37.613443 Enable DLL master slave shuffle
658 22:15:37.619980 ==============================================================
659 22:15:37.620600 Gating Mode config
660 22:15:37.626989 ==============================================================
661 22:15:37.629574 Config description:
662 22:15:37.636164 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
663 22:15:37.643477 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
664 22:15:37.649958 SELPH_MODE 0: By rank 1: By Phase
665 22:15:37.656901 ==============================================================
666 22:15:37.657488 GAT_TRACK_EN = 1
667 22:15:37.660213 RX_GATING_MODE = 2
668 22:15:37.663150 RX_GATING_TRACK_MODE = 2
669 22:15:37.666260 SELPH_MODE = 1
670 22:15:37.670408 PICG_EARLY_EN = 1
671 22:15:37.672997 VALID_LAT_VALUE = 1
672 22:15:37.679607 ==============================================================
673 22:15:37.682834 Enter into Gating configuration >>>>
674 22:15:37.686769 Exit from Gating configuration <<<<
675 22:15:37.689993 Enter into DVFS_PRE_config >>>>>
676 22:15:37.699989 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
677 22:15:37.703052 Exit from DVFS_PRE_config <<<<<
678 22:15:37.706653 Enter into PICG configuration >>>>
679 22:15:37.709954 Exit from PICG configuration <<<<
680 22:15:37.713376 [RX_INPUT] configuration >>>>>
681 22:15:37.716570 [RX_INPUT] configuration <<<<<
682 22:15:37.719229 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
683 22:15:37.728236 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
684 22:15:37.732715 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
685 22:15:37.735819 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
686 22:15:37.742970 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
687 22:15:37.749408 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
688 22:15:37.752404 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
689 22:15:37.756135 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
690 22:15:37.762786 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
691 22:15:37.766920 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
692 22:15:37.770009 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
693 22:15:37.773644 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
694 22:15:37.776457 ===================================
695 22:15:37.779738 LPDDR4 DRAM CONFIGURATION
696 22:15:37.783070 ===================================
697 22:15:37.786696 EX_ROW_EN[0] = 0x0
698 22:15:37.787280 EX_ROW_EN[1] = 0x0
699 22:15:37.790239 LP4Y_EN = 0x0
700 22:15:37.790868 WORK_FSP = 0x0
701 22:15:37.793467 WL = 0x2
702 22:15:37.794053 RL = 0x2
703 22:15:37.796438 BL = 0x2
704 22:15:37.796949 RPST = 0x0
705 22:15:37.800012 RD_PRE = 0x0
706 22:15:37.800499 WR_PRE = 0x1
707 22:15:37.803485 WR_PST = 0x0
708 22:15:37.804067 DBI_WR = 0x0
709 22:15:37.807649 DBI_RD = 0x0
710 22:15:37.808232 OTF = 0x1
711 22:15:37.810182 ===================================
712 22:15:37.816861 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
713 22:15:37.820450 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
714 22:15:37.823015 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
715 22:15:37.826859 ===================================
716 22:15:37.830169 LPDDR4 DRAM CONFIGURATION
717 22:15:37.833690 ===================================
718 22:15:37.837969 EX_ROW_EN[0] = 0x10
719 22:15:37.838575 EX_ROW_EN[1] = 0x0
720 22:15:37.839930 LP4Y_EN = 0x0
721 22:15:37.840421 WORK_FSP = 0x0
722 22:15:37.843539 WL = 0x2
723 22:15:37.844127 RL = 0x2
724 22:15:37.846211 BL = 0x2
725 22:15:37.846752 RPST = 0x0
726 22:15:37.850406 RD_PRE = 0x0
727 22:15:37.850979 WR_PRE = 0x1
728 22:15:37.853507 WR_PST = 0x0
729 22:15:37.853983 DBI_WR = 0x0
730 22:15:37.857675 DBI_RD = 0x0
731 22:15:37.858313 OTF = 0x1
732 22:15:37.861300 ===================================
733 22:15:37.867745 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
734 22:15:37.870875 nWR fixed to 40
735 22:15:37.874838 [ModeRegInit_LP4] CH0 RK0
736 22:15:37.875424 [ModeRegInit_LP4] CH0 RK1
737 22:15:37.878473 [ModeRegInit_LP4] CH1 RK0
738 22:15:37.882320 [ModeRegInit_LP4] CH1 RK1
739 22:15:37.882843 match AC timing 13
740 22:15:37.885490 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
741 22:15:37.889356 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
742 22:15:37.896156 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
743 22:15:37.899889 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
744 22:15:37.903456 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
745 22:15:37.907234 [EMI DOE] emi_dcm 0
746 22:15:37.910934 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
747 22:15:37.911458 ==
748 22:15:37.915165 Dram Type= 6, Freq= 0, CH_0, rank 0
749 22:15:37.918333 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
750 22:15:37.919131 ==
751 22:15:37.923311 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
752 22:15:37.929192 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
753 22:15:37.939114 [CA 0] Center 38 (7~69) winsize 63
754 22:15:37.942803 [CA 1] Center 38 (7~69) winsize 63
755 22:15:37.946576 [CA 2] Center 35 (5~66) winsize 62
756 22:15:37.950446 [CA 3] Center 35 (5~66) winsize 62
757 22:15:37.953946 [CA 4] Center 34 (4~65) winsize 62
758 22:15:37.954758 [CA 5] Center 34 (3~65) winsize 63
759 22:15:37.958315
760 22:15:37.961900 [CmdBusTrainingLP45] Vref(ca) range 1: 34
761 22:15:37.962426
762 22:15:37.964704 [CATrainingPosCal] consider 1 rank data
763 22:15:37.965356 u2DelayCellTimex100 = 270/100 ps
764 22:15:37.968651 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
765 22:15:37.972262 CA1 delay=38 (7~69),Diff = 4 PI (28 cell)
766 22:15:37.975387 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
767 22:15:37.979520 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
768 22:15:37.983407 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
769 22:15:37.987725 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
770 22:15:37.988351
771 22:15:37.990773 CA PerBit enable=1, Macro0, CA PI delay=34
772 22:15:37.991271
773 22:15:37.994584 [CBTSetCACLKResult] CA Dly = 34
774 22:15:37.998113 CS Dly: 5 (0~36)
775 22:15:37.998665 ==
776 22:15:38.001945 Dram Type= 6, Freq= 0, CH_0, rank 1
777 22:15:38.006062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
778 22:15:38.006750 ==
779 22:15:38.009747 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
780 22:15:38.016784 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
781 22:15:38.024916 [CA 0] Center 38 (7~69) winsize 63
782 22:15:38.028650 [CA 1] Center 38 (8~69) winsize 62
783 22:15:38.032238 [CA 2] Center 36 (6~67) winsize 62
784 22:15:38.036214 [CA 3] Center 36 (5~67) winsize 63
785 22:15:38.039723 [CA 4] Center 35 (4~66) winsize 63
786 22:15:38.043706 [CA 5] Center 34 (4~65) winsize 62
787 22:15:38.044327
788 22:15:38.046789 [CmdBusTrainingLP45] Vref(ca) range 1: 34
789 22:15:38.047392
790 22:15:38.050021 [CATrainingPosCal] consider 2 rank data
791 22:15:38.053715 u2DelayCellTimex100 = 270/100 ps
792 22:15:38.057645 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
793 22:15:38.060992 CA1 delay=38 (8~69),Diff = 4 PI (28 cell)
794 22:15:38.064511 CA2 delay=36 (6~66),Diff = 2 PI (14 cell)
795 22:15:38.068099 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
796 22:15:38.072262 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
797 22:15:38.075494 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
798 22:15:38.075985
799 22:15:38.079569 CA PerBit enable=1, Macro0, CA PI delay=34
800 22:15:38.080139
801 22:15:38.082742 [CBTSetCACLKResult] CA Dly = 34
802 22:15:38.083232 CS Dly: 6 (0~38)
803 22:15:38.083627
804 22:15:38.086673 ----->DramcWriteLeveling(PI) begin...
805 22:15:38.087167 ==
806 22:15:38.090241 Dram Type= 6, Freq= 0, CH_0, rank 0
807 22:15:38.095885 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
808 22:15:38.096422 ==
809 22:15:38.097865 Write leveling (Byte 0): 29 => 29
810 22:15:38.102403 Write leveling (Byte 1): 29 => 29
811 22:15:38.102944 DramcWriteLeveling(PI) end<-----
812 22:15:38.105882
813 22:15:38.106485 ==
814 22:15:38.106850 Dram Type= 6, Freq= 0, CH_0, rank 0
815 22:15:38.113004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
816 22:15:38.113572 ==
817 22:15:38.113934 [Gating] SW mode calibration
818 22:15:38.120050 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
819 22:15:38.127693 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
820 22:15:38.131497 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
821 22:15:38.135496 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
822 22:15:38.138923 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
823 22:15:38.142389 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 22:15:38.149658 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 22:15:38.153425 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 22:15:38.156828 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 22:15:38.160472 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 22:15:38.167888 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
829 22:15:38.171899 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
830 22:15:38.175049 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
831 22:15:38.178187 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
832 22:15:38.184827 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
833 22:15:38.188256 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
834 22:15:38.191479 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
835 22:15:38.195014 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
836 22:15:38.201706 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
837 22:15:38.204919 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
838 22:15:38.208911 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
839 22:15:38.214793 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
840 22:15:38.218401 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
841 22:15:38.221739 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
842 22:15:38.228509 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
843 22:15:38.231525 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
844 22:15:38.235331 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
845 22:15:38.241899 0 9 4 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
846 22:15:38.244969 0 9 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
847 22:15:38.248194 0 9 12 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
848 22:15:38.254788 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
849 22:15:38.259164 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
850 22:15:38.261452 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
851 22:15:38.268438 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
852 22:15:38.271717 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
853 22:15:38.274925 0 10 4 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 1)
854 22:15:38.281356 0 10 8 | B1->B0 | 3131 2323 | 0 0 | (1 1) (0 0)
855 22:15:38.285301 0 10 12 | B1->B0 | 2424 2323 | 1 0 | (0 0) (0 0)
856 22:15:38.288012 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 22:15:38.294503 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 22:15:38.297927 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 22:15:38.301123 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 22:15:38.307870 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 22:15:38.311281 0 11 4 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
862 22:15:38.314722 0 11 8 | B1->B0 | 2e2e 4646 | 0 0 | (0 0) (0 0)
863 22:15:38.321715 0 11 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
864 22:15:38.324322 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
865 22:15:38.328063 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
866 22:15:38.331594 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
867 22:15:38.338043 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
868 22:15:38.341189 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
869 22:15:38.344661 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
870 22:15:38.351123 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
871 22:15:38.354689 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
872 22:15:38.357924 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
873 22:15:38.364623 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
874 22:15:38.367479 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
875 22:15:38.371331 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
876 22:15:38.377729 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
877 22:15:38.380655 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
878 22:15:38.383971 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
879 22:15:38.391035 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
880 22:15:38.394309 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
881 22:15:38.397486 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
882 22:15:38.404408 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
883 22:15:38.407758 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
884 22:15:38.411002 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
885 22:15:38.417478 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
886 22:15:38.420612 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
887 22:15:38.423665 Total UI for P1: 0, mck2ui 16
888 22:15:38.427072 best dqsien dly found for B0: ( 0, 14, 2)
889 22:15:38.431124 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
890 22:15:38.434281 Total UI for P1: 0, mck2ui 16
891 22:15:38.437047 best dqsien dly found for B1: ( 0, 14, 10)
892 22:15:38.441020 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
893 22:15:38.443994 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
894 22:15:38.444573
895 22:15:38.451280 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
896 22:15:38.454109 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
897 22:15:38.454742 [Gating] SW calibration Done
898 22:15:38.457731 ==
899 22:15:38.461099 Dram Type= 6, Freq= 0, CH_0, rank 0
900 22:15:38.464397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
901 22:15:38.464986 ==
902 22:15:38.465371 RX Vref Scan: 0
903 22:15:38.465725
904 22:15:38.467255 RX Vref 0 -> 0, step: 1
905 22:15:38.467736
906 22:15:38.470646 RX Delay -130 -> 252, step: 16
907 22:15:38.474515 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
908 22:15:38.477420 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
909 22:15:38.484206 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
910 22:15:38.486897 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
911 22:15:38.490893 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
912 22:15:38.494420 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
913 22:15:38.496672 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
914 22:15:38.503836 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
915 22:15:38.507047 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
916 22:15:38.510189 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
917 22:15:38.513689 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
918 22:15:38.517000 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
919 22:15:38.523428 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
920 22:15:38.526765 iDelay=222, Bit 13, Center 77 (-34 ~ 189) 224
921 22:15:38.530202 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
922 22:15:38.533721 iDelay=222, Bit 15, Center 85 (-18 ~ 189) 208
923 22:15:38.534308 ==
924 22:15:38.537300 Dram Type= 6, Freq= 0, CH_0, rank 0
925 22:15:38.543349 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
926 22:15:38.543786 ==
927 22:15:38.544131 DQS Delay:
928 22:15:38.546903 DQS0 = 0, DQS1 = 0
929 22:15:38.547385 DQM Delay:
930 22:15:38.547885 DQM0 = 89, DQM1 = 78
931 22:15:38.550947 DQ Delay:
932 22:15:38.553512 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
933 22:15:38.558203 DQ4 =85, DQ5 =77, DQ6 =101, DQ7 =101
934 22:15:38.560429 DQ8 =77, DQ9 =61, DQ10 =77, DQ11 =77
935 22:15:38.563520 DQ12 =77, DQ13 =77, DQ14 =93, DQ15 =85
936 22:15:38.564063
937 22:15:38.564412
938 22:15:38.564729 ==
939 22:15:38.566755 Dram Type= 6, Freq= 0, CH_0, rank 0
940 22:15:38.570140 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
941 22:15:38.570729 ==
942 22:15:38.571085
943 22:15:38.571402
944 22:15:38.573095 TX Vref Scan disable
945 22:15:38.573528 == TX Byte 0 ==
946 22:15:38.579742 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
947 22:15:38.582861 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
948 22:15:38.586445 == TX Byte 1 ==
949 22:15:38.590012 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
950 22:15:38.593232 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
951 22:15:38.593773 ==
952 22:15:38.596760 Dram Type= 6, Freq= 0, CH_0, rank 0
953 22:15:38.599794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
954 22:15:38.600229 ==
955 22:15:38.613875 TX Vref=22, minBit 5, minWin=27, winSum=441
956 22:15:38.617636 TX Vref=24, minBit 5, minWin=27, winSum=444
957 22:15:38.620391 TX Vref=26, minBit 8, minWin=27, winSum=447
958 22:15:38.623455 TX Vref=28, minBit 9, minWin=27, winSum=454
959 22:15:38.626873 TX Vref=30, minBit 9, minWin=27, winSum=455
960 22:15:38.633756 TX Vref=32, minBit 1, minWin=28, winSum=453
961 22:15:38.637293 [TxChooseVref] Worse bit 1, Min win 28, Win sum 453, Final Vref 32
962 22:15:38.637780
963 22:15:38.640575 Final TX Range 1 Vref 32
964 22:15:38.641166
965 22:15:38.641550 ==
966 22:15:38.643459 Dram Type= 6, Freq= 0, CH_0, rank 0
967 22:15:38.647125 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
968 22:15:38.650217 ==
969 22:15:38.650852
970 22:15:38.651238
971 22:15:38.651598 TX Vref Scan disable
972 22:15:38.653635 == TX Byte 0 ==
973 22:15:38.657054 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
974 22:15:38.663534 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
975 22:15:38.664132 == TX Byte 1 ==
976 22:15:38.666813 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
977 22:15:38.673497 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
978 22:15:38.674090
979 22:15:38.674511 [DATLAT]
980 22:15:38.674869 Freq=800, CH0 RK0
981 22:15:38.675220
982 22:15:38.676735 DATLAT Default: 0xa
983 22:15:38.677225 0, 0xFFFF, sum = 0
984 22:15:38.680708 1, 0xFFFF, sum = 0
985 22:15:38.683844 2, 0xFFFF, sum = 0
986 22:15:38.684343 3, 0xFFFF, sum = 0
987 22:15:38.686713 4, 0xFFFF, sum = 0
988 22:15:38.687204 5, 0xFFFF, sum = 0
989 22:15:38.690089 6, 0xFFFF, sum = 0
990 22:15:38.690618 7, 0xFFFF, sum = 0
991 22:15:38.693597 8, 0xFFFF, sum = 0
992 22:15:38.694196 9, 0x0, sum = 1
993 22:15:38.696795 10, 0x0, sum = 2
994 22:15:38.697398 11, 0x0, sum = 3
995 22:15:38.697796 12, 0x0, sum = 4
996 22:15:38.700573 best_step = 10
997 22:15:38.701058
998 22:15:38.701443 ==
999 22:15:38.703555 Dram Type= 6, Freq= 0, CH_0, rank 0
1000 22:15:38.706633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1001 22:15:38.707223 ==
1002 22:15:38.710082 RX Vref Scan: 1
1003 22:15:38.710713
1004 22:15:38.713306 Set Vref Range= 32 -> 127
1005 22:15:38.713897
1006 22:15:38.714285 RX Vref 32 -> 127, step: 1
1007 22:15:38.714746
1008 22:15:38.716506 RX Delay -95 -> 252, step: 8
1009 22:15:38.716995
1010 22:15:38.719887 Set Vref, RX VrefLevel [Byte0]: 32
1011 22:15:38.724033 [Byte1]: 32
1012 22:15:38.726198
1013 22:15:38.726839 Set Vref, RX VrefLevel [Byte0]: 33
1014 22:15:38.729730 [Byte1]: 33
1015 22:15:38.733886
1016 22:15:38.734506 Set Vref, RX VrefLevel [Byte0]: 34
1017 22:15:38.736837 [Byte1]: 34
1018 22:15:38.741615
1019 22:15:38.742200 Set Vref, RX VrefLevel [Byte0]: 35
1020 22:15:38.745147 [Byte1]: 35
1021 22:15:38.749203
1022 22:15:38.749791 Set Vref, RX VrefLevel [Byte0]: 36
1023 22:15:38.752595 [Byte1]: 36
1024 22:15:38.756781
1025 22:15:38.757400 Set Vref, RX VrefLevel [Byte0]: 37
1026 22:15:38.759814 [Byte1]: 37
1027 22:15:38.764787
1028 22:15:38.765390 Set Vref, RX VrefLevel [Byte0]: 38
1029 22:15:38.768541 [Byte1]: 38
1030 22:15:38.771923
1031 22:15:38.772499 Set Vref, RX VrefLevel [Byte0]: 39
1032 22:15:38.775230 [Byte1]: 39
1033 22:15:38.779656
1034 22:15:38.780229 Set Vref, RX VrefLevel [Byte0]: 40
1035 22:15:38.783085 [Byte1]: 40
1036 22:15:38.787483
1037 22:15:38.787955 Set Vref, RX VrefLevel [Byte0]: 41
1038 22:15:38.790723 [Byte1]: 41
1039 22:15:38.794916
1040 22:15:38.795391 Set Vref, RX VrefLevel [Byte0]: 42
1041 22:15:38.798616 [Byte1]: 42
1042 22:15:38.802085
1043 22:15:38.802552 Set Vref, RX VrefLevel [Byte0]: 43
1044 22:15:38.805870 [Byte1]: 43
1045 22:15:38.810267
1046 22:15:38.810879 Set Vref, RX VrefLevel [Byte0]: 44
1047 22:15:38.813604 [Byte1]: 44
1048 22:15:38.818713
1049 22:15:38.819282 Set Vref, RX VrefLevel [Byte0]: 45
1050 22:15:38.821378 [Byte1]: 45
1051 22:15:38.825745
1052 22:15:38.826324 Set Vref, RX VrefLevel [Byte0]: 46
1053 22:15:38.829182 [Byte1]: 46
1054 22:15:38.833034
1055 22:15:38.833617 Set Vref, RX VrefLevel [Byte0]: 47
1056 22:15:38.835918 [Byte1]: 47
1057 22:15:38.840506
1058 22:15:38.841080 Set Vref, RX VrefLevel [Byte0]: 48
1059 22:15:38.843531 [Byte1]: 48
1060 22:15:38.847927
1061 22:15:38.848591 Set Vref, RX VrefLevel [Byte0]: 49
1062 22:15:38.851806 [Byte1]: 49
1063 22:15:38.856271
1064 22:15:38.856843 Set Vref, RX VrefLevel [Byte0]: 50
1065 22:15:38.858786 [Byte1]: 50
1066 22:15:38.863141
1067 22:15:38.863725 Set Vref, RX VrefLevel [Byte0]: 51
1068 22:15:38.866823 [Byte1]: 51
1069 22:15:38.871171
1070 22:15:38.871768 Set Vref, RX VrefLevel [Byte0]: 52
1071 22:15:38.873678 [Byte1]: 52
1072 22:15:38.878487
1073 22:15:38.882160 Set Vref, RX VrefLevel [Byte0]: 53
1074 22:15:38.882683 [Byte1]: 53
1075 22:15:38.885848
1076 22:15:38.886480 Set Vref, RX VrefLevel [Byte0]: 54
1077 22:15:38.889311 [Byte1]: 54
1078 22:15:38.894088
1079 22:15:38.894700 Set Vref, RX VrefLevel [Byte0]: 55
1080 22:15:38.897256 [Byte1]: 55
1081 22:15:38.901029
1082 22:15:38.901559 Set Vref, RX VrefLevel [Byte0]: 56
1083 22:15:38.904652 [Byte1]: 56
1084 22:15:38.908763
1085 22:15:38.909325 Set Vref, RX VrefLevel [Byte0]: 57
1086 22:15:38.912201 [Byte1]: 57
1087 22:15:38.916190
1088 22:15:38.916757 Set Vref, RX VrefLevel [Byte0]: 58
1089 22:15:38.920120 [Byte1]: 58
1090 22:15:38.924257
1091 22:15:38.924824 Set Vref, RX VrefLevel [Byte0]: 59
1092 22:15:38.927573 [Byte1]: 59
1093 22:15:38.931362
1094 22:15:38.934783 Set Vref, RX VrefLevel [Byte0]: 60
1095 22:15:38.935257 [Byte1]: 60
1096 22:15:38.939007
1097 22:15:38.939472 Set Vref, RX VrefLevel [Byte0]: 61
1098 22:15:38.942557 [Byte1]: 61
1099 22:15:38.946646
1100 22:15:38.947217 Set Vref, RX VrefLevel [Byte0]: 62
1101 22:15:38.950529 [Byte1]: 62
1102 22:15:38.954531
1103 22:15:38.955089 Set Vref, RX VrefLevel [Byte0]: 63
1104 22:15:38.957491 [Byte1]: 63
1105 22:15:38.961967
1106 22:15:38.962576 Set Vref, RX VrefLevel [Byte0]: 64
1107 22:15:38.966099 [Byte1]: 64
1108 22:15:38.969644
1109 22:15:38.970269 Set Vref, RX VrefLevel [Byte0]: 65
1110 22:15:38.972852 [Byte1]: 65
1111 22:15:38.976901
1112 22:15:38.977369 Set Vref, RX VrefLevel [Byte0]: 66
1113 22:15:38.980364 [Byte1]: 66
1114 22:15:38.984427
1115 22:15:38.984892 Set Vref, RX VrefLevel [Byte0]: 67
1116 22:15:38.988135 [Byte1]: 67
1117 22:15:38.992074
1118 22:15:38.992553 Set Vref, RX VrefLevel [Byte0]: 68
1119 22:15:38.995439 [Byte1]: 68
1120 22:15:38.999969
1121 22:15:39.000438 Set Vref, RX VrefLevel [Byte0]: 69
1122 22:15:39.003729 [Byte1]: 69
1123 22:15:39.007623
1124 22:15:39.008255 Set Vref, RX VrefLevel [Byte0]: 70
1125 22:15:39.013868 [Byte1]: 70
1126 22:15:39.014489
1127 22:15:39.017880 Set Vref, RX VrefLevel [Byte0]: 71
1128 22:15:39.020654 [Byte1]: 71
1129 22:15:39.021224
1130 22:15:39.023543 Set Vref, RX VrefLevel [Byte0]: 72
1131 22:15:39.027472 [Byte1]: 72
1132 22:15:39.028048
1133 22:15:39.030315 Set Vref, RX VrefLevel [Byte0]: 73
1134 22:15:39.034168 [Byte1]: 73
1135 22:15:39.037948
1136 22:15:39.038591 Set Vref, RX VrefLevel [Byte0]: 74
1137 22:15:39.041517 [Byte1]: 74
1138 22:15:39.045680
1139 22:15:39.046254 Set Vref, RX VrefLevel [Byte0]: 75
1140 22:15:39.049006 [Byte1]: 75
1141 22:15:39.053146
1142 22:15:39.053893 Set Vref, RX VrefLevel [Byte0]: 76
1143 22:15:39.056331 [Byte1]: 76
1144 22:15:39.060553
1145 22:15:39.061189 Set Vref, RX VrefLevel [Byte0]: 77
1146 22:15:39.064411 [Byte1]: 77
1147 22:15:39.068292
1148 22:15:39.068841 Set Vref, RX VrefLevel [Byte0]: 78
1149 22:15:39.071346 [Byte1]: 78
1150 22:15:39.075512
1151 22:15:39.076003 Set Vref, RX VrefLevel [Byte0]: 79
1152 22:15:39.078863 [Byte1]: 79
1153 22:15:39.083247
1154 22:15:39.083718 Final RX Vref Byte 0 = 60 to rank0
1155 22:15:39.087071 Final RX Vref Byte 1 = 60 to rank0
1156 22:15:39.090390 Final RX Vref Byte 0 = 60 to rank1
1157 22:15:39.093948 Final RX Vref Byte 1 = 60 to rank1==
1158 22:15:39.097165 Dram Type= 6, Freq= 0, CH_0, rank 0
1159 22:15:39.103258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1160 22:15:39.103758 ==
1161 22:15:39.104241 DQS Delay:
1162 22:15:39.104660 DQS0 = 0, DQS1 = 0
1163 22:15:39.106487 DQM Delay:
1164 22:15:39.106976 DQM0 = 93, DQM1 = 82
1165 22:15:39.110083 DQ Delay:
1166 22:15:39.113509 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1167 22:15:39.116837 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104
1168 22:15:39.121025 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =80
1169 22:15:39.123618 DQ12 =84, DQ13 =80, DQ14 =92, DQ15 =92
1170 22:15:39.124214
1171 22:15:39.124706
1172 22:15:39.130432 [DQSOSCAuto] RK0, (LSB)MR18= 0x3d39, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 394 ps
1173 22:15:39.134116 CH0 RK0: MR19=606, MR18=3D39
1174 22:15:39.140540 CH0_RK0: MR19=0x606, MR18=0x3D39, DQSOSC=394, MR23=63, INC=95, DEC=63
1175 22:15:39.141134
1176 22:15:39.143339 ----->DramcWriteLeveling(PI) begin...
1177 22:15:39.143942 ==
1178 22:15:39.146714 Dram Type= 6, Freq= 0, CH_0, rank 1
1179 22:15:39.149887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1180 22:15:39.150526 ==
1181 22:15:39.153104 Write leveling (Byte 0): 32 => 32
1182 22:15:39.157596 Write leveling (Byte 1): 31 => 31
1183 22:15:39.160046 DramcWriteLeveling(PI) end<-----
1184 22:15:39.160634
1185 22:15:39.161124 ==
1186 22:15:39.163738 Dram Type= 6, Freq= 0, CH_0, rank 1
1187 22:15:39.166466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1188 22:15:39.167060 ==
1189 22:15:39.169613 [Gating] SW mode calibration
1190 22:15:39.176319 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1191 22:15:39.182878 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1192 22:15:39.186188 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1193 22:15:39.230077 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1194 22:15:39.230936 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 22:15:39.231790 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 22:15:39.232213 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1197 22:15:39.232671 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1198 22:15:39.233118 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1199 22:15:39.233557 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1200 22:15:39.234107 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1201 22:15:39.234730 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1202 22:15:39.235146 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1203 22:15:39.253110 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1204 22:15:39.253718 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1205 22:15:39.254553 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1206 22:15:39.254981 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1207 22:15:39.255444 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1208 22:15:39.256537 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1209 22:15:39.260324 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1210 22:15:39.266656 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1211 22:15:39.270174 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1212 22:15:39.273789 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1213 22:15:39.280003 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1214 22:15:39.283085 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1215 22:15:39.286600 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1216 22:15:39.293407 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1217 22:15:39.296750 0 9 4 | B1->B0 | 2323 2323 | 0 1 | (1 1) (1 1)
1218 22:15:39.299717 0 9 8 | B1->B0 | 2929 3434 | 0 1 | (0 0) (1 1)
1219 22:15:39.306612 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1220 22:15:39.310137 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1221 22:15:39.314163 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1222 22:15:39.320316 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1223 22:15:39.323758 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1224 22:15:39.326976 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1225 22:15:39.333580 0 10 4 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
1226 22:15:39.336617 0 10 8 | B1->B0 | 2b2b 2323 | 1 0 | (1 0) (1 0)
1227 22:15:39.339649 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 22:15:39.346967 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 22:15:39.349834 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 22:15:39.352938 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 22:15:39.360092 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 22:15:39.363211 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 22:15:39.367077 0 11 4 | B1->B0 | 2c2c 3434 | 0 0 | (1 1) (1 1)
1234 22:15:39.370954 0 11 8 | B1->B0 | 3a3a 4444 | 0 0 | (0 0) (0 0)
1235 22:15:39.377904 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1236 22:15:39.381360 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1237 22:15:39.384524 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1238 22:15:39.388045 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1239 22:15:39.394900 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1240 22:15:39.398552 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1241 22:15:39.402226 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1242 22:15:39.405251 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1243 22:15:39.412154 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1244 22:15:39.415091 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1245 22:15:39.419070 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1246 22:15:39.425395 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1247 22:15:39.428491 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1248 22:15:39.432041 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1249 22:15:39.438952 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1250 22:15:39.441935 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1251 22:15:39.445526 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1252 22:15:39.452067 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1253 22:15:39.455024 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1254 22:15:39.458461 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1255 22:15:39.465506 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1256 22:15:39.468331 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1257 22:15:39.472017 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1258 22:15:39.478318 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1259 22:15:39.478937 Total UI for P1: 0, mck2ui 16
1260 22:15:39.484566 best dqsien dly found for B1: ( 0, 14, 4)
1261 22:15:39.488375 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1262 22:15:39.491477 Total UI for P1: 0, mck2ui 16
1263 22:15:39.494877 best dqsien dly found for B0: ( 0, 14, 6)
1264 22:15:39.498035 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1265 22:15:39.501206 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1266 22:15:39.501685
1267 22:15:39.504585 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1268 22:15:39.508005 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1269 22:15:39.510934 [Gating] SW calibration Done
1270 22:15:39.511410 ==
1271 22:15:39.514657 Dram Type= 6, Freq= 0, CH_0, rank 1
1272 22:15:39.518252 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1273 22:15:39.521364 ==
1274 22:15:39.521940 RX Vref Scan: 0
1275 22:15:39.522312
1276 22:15:39.525030 RX Vref 0 -> 0, step: 1
1277 22:15:39.525597
1278 22:15:39.527544 RX Delay -130 -> 252, step: 16
1279 22:15:39.531340 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1280 22:15:39.534182 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1281 22:15:39.538127 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1282 22:15:39.541118 iDelay=222, Bit 3, Center 77 (-34 ~ 189) 224
1283 22:15:39.548272 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1284 22:15:39.551265 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
1285 22:15:39.554415 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1286 22:15:39.557368 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1287 22:15:39.561788 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1288 22:15:39.567767 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
1289 22:15:39.571275 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1290 22:15:39.574443 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1291 22:15:39.577944 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1292 22:15:39.581164 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1293 22:15:39.588089 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1294 22:15:39.590474 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1295 22:15:39.590962 ==
1296 22:15:39.594217 Dram Type= 6, Freq= 0, CH_0, rank 1
1297 22:15:39.597542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1298 22:15:39.598150 ==
1299 22:15:39.600279 DQS Delay:
1300 22:15:39.600799 DQS0 = 0, DQS1 = 0
1301 22:15:39.604199 DQM Delay:
1302 22:15:39.604668 DQM0 = 89, DQM1 = 80
1303 22:15:39.605092 DQ Delay:
1304 22:15:39.607504 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =77
1305 22:15:39.610853 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101
1306 22:15:39.613741 DQ8 =77, DQ9 =61, DQ10 =77, DQ11 =77
1307 22:15:39.617162 DQ12 =77, DQ13 =85, DQ14 =93, DQ15 =93
1308 22:15:39.617738
1309 22:15:39.618108
1310 22:15:39.620299 ==
1311 22:15:39.623897 Dram Type= 6, Freq= 0, CH_0, rank 1
1312 22:15:39.627253 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1313 22:15:39.627852 ==
1314 22:15:39.628241
1315 22:15:39.628594
1316 22:15:39.630118 TX Vref Scan disable
1317 22:15:39.630619 == TX Byte 0 ==
1318 22:15:39.633957 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1319 22:15:39.640220 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1320 22:15:39.640703 == TX Byte 1 ==
1321 22:15:39.643725 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1322 22:15:39.650531 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1323 22:15:39.651117 ==
1324 22:15:39.653974 Dram Type= 6, Freq= 0, CH_0, rank 1
1325 22:15:39.657499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1326 22:15:39.658077 ==
1327 22:15:39.670307 TX Vref=22, minBit 6, minWin=27, winSum=443
1328 22:15:39.673845 TX Vref=24, minBit 3, minWin=27, winSum=446
1329 22:15:39.676901 TX Vref=26, minBit 8, minWin=27, winSum=452
1330 22:15:39.680462 TX Vref=28, minBit 4, minWin=28, winSum=455
1331 22:15:39.683397 TX Vref=30, minBit 8, minWin=28, winSum=458
1332 22:15:39.687132 TX Vref=32, minBit 8, minWin=28, winSum=457
1333 22:15:39.693816 [TxChooseVref] Worse bit 8, Min win 28, Win sum 458, Final Vref 30
1334 22:15:39.694290
1335 22:15:39.696682 Final TX Range 1 Vref 30
1336 22:15:39.697156
1337 22:15:39.697481 ==
1338 22:15:39.700165 Dram Type= 6, Freq= 0, CH_0, rank 1
1339 22:15:39.703701 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1340 22:15:39.704146 ==
1341 22:15:39.704479
1342 22:15:39.706552
1343 22:15:39.707101 TX Vref Scan disable
1344 22:15:39.710413 == TX Byte 0 ==
1345 22:15:39.713145 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1346 22:15:39.720172 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1347 22:15:39.720606 == TX Byte 1 ==
1348 22:15:39.723346 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1349 22:15:39.730072 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1350 22:15:39.730622
1351 22:15:39.730954 [DATLAT]
1352 22:15:39.731265 Freq=800, CH0 RK1
1353 22:15:39.731563
1354 22:15:39.733352 DATLAT Default: 0xa
1355 22:15:39.733890 0, 0xFFFF, sum = 0
1356 22:15:39.736670 1, 0xFFFF, sum = 0
1357 22:15:39.740129 2, 0xFFFF, sum = 0
1358 22:15:39.740563 3, 0xFFFF, sum = 0
1359 22:15:39.743126 4, 0xFFFF, sum = 0
1360 22:15:39.743601 5, 0xFFFF, sum = 0
1361 22:15:39.746850 6, 0xFFFF, sum = 0
1362 22:15:39.747385 7, 0xFFFF, sum = 0
1363 22:15:39.749771 8, 0xFFFF, sum = 0
1364 22:15:39.750202 9, 0x0, sum = 1
1365 22:15:39.753090 10, 0x0, sum = 2
1366 22:15:39.753519 11, 0x0, sum = 3
1367 22:15:39.753858 12, 0x0, sum = 4
1368 22:15:39.757076 best_step = 10
1369 22:15:39.757496
1370 22:15:39.757827 ==
1371 22:15:39.759686 Dram Type= 6, Freq= 0, CH_0, rank 1
1372 22:15:39.762965 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1373 22:15:39.763399 ==
1374 22:15:39.766781 RX Vref Scan: 0
1375 22:15:39.767301
1376 22:15:39.769659 RX Vref 0 -> 0, step: 1
1377 22:15:39.770185
1378 22:15:39.770563 RX Delay -95 -> 252, step: 8
1379 22:15:39.776404 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1380 22:15:39.780476 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1381 22:15:39.783500 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1382 22:15:39.786734 iDelay=209, Bit 3, Center 88 (-15 ~ 192) 208
1383 22:15:39.790222 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1384 22:15:39.796914 iDelay=209, Bit 5, Center 80 (-31 ~ 192) 224
1385 22:15:39.799820 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1386 22:15:39.803592 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1387 22:15:39.806884 iDelay=209, Bit 8, Center 72 (-31 ~ 176) 208
1388 22:15:39.809939 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1389 22:15:39.816890 iDelay=209, Bit 10, Center 80 (-23 ~ 184) 208
1390 22:15:39.820850 iDelay=209, Bit 11, Center 80 (-23 ~ 184) 208
1391 22:15:39.823358 iDelay=209, Bit 12, Center 88 (-15 ~ 192) 208
1392 22:15:39.826873 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1393 22:15:39.833536 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1394 22:15:39.836874 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
1395 22:15:39.837564 ==
1396 22:15:39.839580 Dram Type= 6, Freq= 0, CH_0, rank 1
1397 22:15:39.843887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1398 22:15:39.844415 ==
1399 22:15:39.844788 DQS Delay:
1400 22:15:39.847341 DQS0 = 0, DQS1 = 0
1401 22:15:39.847845 DQM Delay:
1402 22:15:39.849514 DQM0 = 91, DQM1 = 82
1403 22:15:39.849901 DQ Delay:
1404 22:15:39.853558 DQ0 =88, DQ1 =92, DQ2 =88, DQ3 =88
1405 22:15:39.856659 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1406 22:15:39.860155 DQ8 =72, DQ9 =72, DQ10 =80, DQ11 =80
1407 22:15:39.863322 DQ12 =88, DQ13 =84, DQ14 =92, DQ15 =92
1408 22:15:39.863849
1409 22:15:39.864177
1410 22:15:39.873451 [DQSOSCAuto] RK1, (LSB)MR18= 0x401b, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 393 ps
1411 22:15:39.873982 CH0 RK1: MR19=606, MR18=401B
1412 22:15:39.879551 CH0_RK1: MR19=0x606, MR18=0x401B, DQSOSC=393, MR23=63, INC=95, DEC=63
1413 22:15:39.882760 [RxdqsGatingPostProcess] freq 800
1414 22:15:39.889417 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1415 22:15:39.892680 Pre-setting of DQS Precalculation
1416 22:15:39.895983 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1417 22:15:39.896514 ==
1418 22:15:39.899405 Dram Type= 6, Freq= 0, CH_1, rank 0
1419 22:15:39.906461 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1420 22:15:39.906986 ==
1421 22:15:39.909421 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1422 22:15:39.916687 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1423 22:15:39.925660 [CA 0] Center 36 (6~67) winsize 62
1424 22:15:39.929482 [CA 1] Center 36 (6~67) winsize 62
1425 22:15:39.932135 [CA 2] Center 34 (4~65) winsize 62
1426 22:15:39.935134 [CA 3] Center 34 (4~65) winsize 62
1427 22:15:39.938313 [CA 4] Center 34 (4~65) winsize 62
1428 22:15:39.941740 [CA 5] Center 33 (3~64) winsize 62
1429 22:15:39.942207
1430 22:15:39.945344 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1431 22:15:39.946038
1432 22:15:39.948326 [CATrainingPosCal] consider 1 rank data
1433 22:15:39.952288 u2DelayCellTimex100 = 270/100 ps
1434 22:15:39.954970 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1435 22:15:39.958582 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1436 22:15:39.965058 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1437 22:15:39.968799 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1438 22:15:39.971865 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1439 22:15:39.975163 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1440 22:15:39.975728
1441 22:15:39.978636 CA PerBit enable=1, Macro0, CA PI delay=33
1442 22:15:39.979199
1443 22:15:39.981761 [CBTSetCACLKResult] CA Dly = 33
1444 22:15:39.982336 CS Dly: 5 (0~36)
1445 22:15:39.985598 ==
1446 22:15:39.986168 Dram Type= 6, Freq= 0, CH_1, rank 1
1447 22:15:39.991553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1448 22:15:39.992265 ==
1449 22:15:39.994808 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1450 22:15:40.001733 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1451 22:15:40.011536 [CA 0] Center 37 (6~68) winsize 63
1452 22:15:40.015039 [CA 1] Center 37 (6~68) winsize 63
1453 22:15:40.018522 [CA 2] Center 35 (5~66) winsize 62
1454 22:15:40.021553 [CA 3] Center 34 (4~65) winsize 62
1455 22:15:40.024877 [CA 4] Center 34 (4~65) winsize 62
1456 22:15:40.028525 [CA 5] Center 34 (4~64) winsize 61
1457 22:15:40.029103
1458 22:15:40.032262 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1459 22:15:40.032836
1460 22:15:40.035274 [CATrainingPosCal] consider 2 rank data
1461 22:15:40.039076 u2DelayCellTimex100 = 270/100 ps
1462 22:15:40.042006 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1463 22:15:40.045818 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1464 22:15:40.048707 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1465 22:15:40.052745 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1466 22:15:40.056551 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1467 22:15:40.059955 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1468 22:15:40.060131
1469 22:15:40.063427 CA PerBit enable=1, Macro0, CA PI delay=34
1470 22:15:40.063611
1471 22:15:40.066366 [CBTSetCACLKResult] CA Dly = 34
1472 22:15:40.070319 CS Dly: 6 (0~38)
1473 22:15:40.070522
1474 22:15:40.072929 ----->DramcWriteLeveling(PI) begin...
1475 22:15:40.073109 ==
1476 22:15:40.076445 Dram Type= 6, Freq= 0, CH_1, rank 0
1477 22:15:40.079913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1478 22:15:40.080134 ==
1479 22:15:40.082902 Write leveling (Byte 0): 24 => 24
1480 22:15:40.085894 Write leveling (Byte 1): 28 => 28
1481 22:15:40.090162 DramcWriteLeveling(PI) end<-----
1482 22:15:40.090441
1483 22:15:40.090599 ==
1484 22:15:40.092580 Dram Type= 6, Freq= 0, CH_1, rank 0
1485 22:15:40.095955 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1486 22:15:40.096157 ==
1487 22:15:40.100243 [Gating] SW mode calibration
1488 22:15:40.106524 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1489 22:15:40.113299 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1490 22:15:40.116808 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1491 22:15:40.123336 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1492 22:15:40.127030 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 22:15:40.129629 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 22:15:40.137591 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1495 22:15:40.139693 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1496 22:15:40.143312 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1497 22:15:40.149711 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1498 22:15:40.152934 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1499 22:15:40.156332 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1500 22:15:40.159245 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1501 22:15:40.166935 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1502 22:15:40.169659 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1503 22:15:40.172608 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1504 22:15:40.179684 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1505 22:15:40.183078 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1506 22:15:40.186530 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1507 22:15:40.193583 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1508 22:15:40.195989 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1509 22:15:40.199696 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1510 22:15:40.206204 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1511 22:15:40.209871 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1512 22:15:40.212672 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1513 22:15:40.219545 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1514 22:15:40.222617 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1515 22:15:40.225845 0 9 4 | B1->B0 | 2323 2424 | 0 1 | (0 0) (1 1)
1516 22:15:40.232707 0 9 8 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
1517 22:15:40.235930 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1518 22:15:40.238843 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1519 22:15:40.245929 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1520 22:15:40.249077 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1521 22:15:40.252601 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1522 22:15:40.259406 0 10 0 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
1523 22:15:40.262710 0 10 4 | B1->B0 | 2f2f 2a2a | 0 1 | (0 0) (1 0)
1524 22:15:40.265441 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 22:15:40.272438 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 22:15:40.275468 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 22:15:40.278527 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 22:15:40.286262 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 22:15:40.289028 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 22:15:40.292394 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 22:15:40.298970 0 11 4 | B1->B0 | 3131 3f3f | 0 1 | (0 0) (0 0)
1532 22:15:40.302446 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1533 22:15:40.305029 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1534 22:15:40.311976 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1535 22:15:40.315035 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1536 22:15:40.318826 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1537 22:15:40.325170 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1538 22:15:40.329060 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1539 22:15:40.332041 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1540 22:15:40.338570 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1541 22:15:40.342114 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1542 22:15:40.345165 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1543 22:15:40.351991 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1544 22:15:40.355448 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1545 22:15:40.358786 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1546 22:15:40.365074 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1547 22:15:40.368169 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1548 22:15:40.371405 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1549 22:15:40.374532 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1550 22:15:40.381232 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1551 22:15:40.384451 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1552 22:15:40.387981 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1553 22:15:40.395371 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1554 22:15:40.398040 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1555 22:15:40.401102 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1556 22:15:40.408269 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1557 22:15:40.411581 Total UI for P1: 0, mck2ui 16
1558 22:15:40.414543 best dqsien dly found for B0: ( 0, 14, 4)
1559 22:15:40.418077 Total UI for P1: 0, mck2ui 16
1560 22:15:40.421351 best dqsien dly found for B1: ( 0, 14, 4)
1561 22:15:40.425026 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1562 22:15:40.428211 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1563 22:15:40.428783
1564 22:15:40.431072 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1565 22:15:40.434793 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1566 22:15:40.438097 [Gating] SW calibration Done
1567 22:15:40.438719 ==
1568 22:15:40.440983 Dram Type= 6, Freq= 0, CH_1, rank 0
1569 22:15:40.444618 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1570 22:15:40.445194 ==
1571 22:15:40.447979 RX Vref Scan: 0
1572 22:15:40.448547
1573 22:15:40.448922 RX Vref 0 -> 0, step: 1
1574 22:15:40.449269
1575 22:15:40.450937 RX Delay -130 -> 252, step: 16
1576 22:15:40.458166 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1577 22:15:40.461349 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1578 22:15:40.464587 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1579 22:15:40.467824 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1580 22:15:40.471267 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1581 22:15:40.477562 iDelay=222, Bit 5, Center 93 (-18 ~ 205) 224
1582 22:15:40.480934 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1583 22:15:40.483920 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1584 22:15:40.487378 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1585 22:15:40.490519 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1586 22:15:40.497228 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1587 22:15:40.500818 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1588 22:15:40.504408 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1589 22:15:40.510048 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1590 22:15:40.510992 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1591 22:15:40.517659 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1592 22:15:40.518238 ==
1593 22:15:40.520968 Dram Type= 6, Freq= 0, CH_1, rank 0
1594 22:15:40.524162 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1595 22:15:40.524742 ==
1596 22:15:40.525115 DQS Delay:
1597 22:15:40.527496 DQS0 = 0, DQS1 = 0
1598 22:15:40.528068 DQM Delay:
1599 22:15:40.530657 DQM0 = 89, DQM1 = 80
1600 22:15:40.531229 DQ Delay:
1601 22:15:40.534381 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1602 22:15:40.537676 DQ4 =85, DQ5 =93, DQ6 =101, DQ7 =85
1603 22:15:40.540705 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1604 22:15:40.544366 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1605 22:15:40.544946
1606 22:15:40.545319
1607 22:15:40.545660 ==
1608 22:15:40.547354 Dram Type= 6, Freq= 0, CH_1, rank 0
1609 22:15:40.551285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1610 22:15:40.551863 ==
1611 22:15:40.554271
1612 22:15:40.554888
1613 22:15:40.555265 TX Vref Scan disable
1614 22:15:40.557412 == TX Byte 0 ==
1615 22:15:40.560658 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1616 22:15:40.564105 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1617 22:15:40.567296 == TX Byte 1 ==
1618 22:15:40.571208 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1619 22:15:40.574162 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1620 22:15:40.574784 ==
1621 22:15:40.577286 Dram Type= 6, Freq= 0, CH_1, rank 0
1622 22:15:40.583566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1623 22:15:40.584248 ==
1624 22:15:40.596428 TX Vref=22, minBit 10, minWin=27, winSum=449
1625 22:15:40.599027 TX Vref=24, minBit 15, minWin=27, winSum=454
1626 22:15:40.602503 TX Vref=26, minBit 15, minWin=27, winSum=457
1627 22:15:40.605639 TX Vref=28, minBit 15, minWin=27, winSum=457
1628 22:15:40.608981 TX Vref=30, minBit 15, minWin=27, winSum=458
1629 22:15:40.616631 TX Vref=32, minBit 8, minWin=28, winSum=458
1630 22:15:40.619637 [TxChooseVref] Worse bit 8, Min win 28, Win sum 458, Final Vref 32
1631 22:15:40.620114
1632 22:15:40.623558 Final TX Range 1 Vref 32
1633 22:15:40.624140
1634 22:15:40.624512 ==
1635 22:15:40.626555 Dram Type= 6, Freq= 0, CH_1, rank 0
1636 22:15:40.630096 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1637 22:15:40.630731 ==
1638 22:15:40.631113
1639 22:15:40.633257
1640 22:15:40.633829 TX Vref Scan disable
1641 22:15:40.637022 == TX Byte 0 ==
1642 22:15:40.639584 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1643 22:15:40.646734 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1644 22:15:40.647309 == TX Byte 1 ==
1645 22:15:40.649630 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1646 22:15:40.656288 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1647 22:15:40.656849
1648 22:15:40.657220 [DATLAT]
1649 22:15:40.657565 Freq=800, CH1 RK0
1650 22:15:40.657894
1651 22:15:40.660173 DATLAT Default: 0xa
1652 22:15:40.660745 0, 0xFFFF, sum = 0
1653 22:15:40.662999 1, 0xFFFF, sum = 0
1654 22:15:40.663582 2, 0xFFFF, sum = 0
1655 22:15:40.666317 3, 0xFFFF, sum = 0
1656 22:15:40.669752 4, 0xFFFF, sum = 0
1657 22:15:40.670335 5, 0xFFFF, sum = 0
1658 22:15:40.673415 6, 0xFFFF, sum = 0
1659 22:15:40.674089 7, 0xFFFF, sum = 0
1660 22:15:40.676412 8, 0xFFFF, sum = 0
1661 22:15:40.676891 9, 0x0, sum = 1
1662 22:15:40.677266 10, 0x0, sum = 2
1663 22:15:40.680485 11, 0x0, sum = 3
1664 22:15:40.681090 12, 0x0, sum = 4
1665 22:15:40.682915 best_step = 10
1666 22:15:40.683384
1667 22:15:40.683753 ==
1668 22:15:40.686440 Dram Type= 6, Freq= 0, CH_1, rank 0
1669 22:15:40.689350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1670 22:15:40.689826 ==
1671 22:15:40.693078 RX Vref Scan: 1
1672 22:15:40.693646
1673 22:15:40.694021 Set Vref Range= 32 -> 127
1674 22:15:40.696117
1675 22:15:40.696638 RX Vref 32 -> 127, step: 1
1676 22:15:40.697278
1677 22:15:40.699721 RX Delay -95 -> 252, step: 8
1678 22:15:40.700199
1679 22:15:40.702780 Set Vref, RX VrefLevel [Byte0]: 32
1680 22:15:40.705968 [Byte1]: 32
1681 22:15:40.706481
1682 22:15:40.709401 Set Vref, RX VrefLevel [Byte0]: 33
1683 22:15:40.713043 [Byte1]: 33
1684 22:15:40.716737
1685 22:15:40.717335 Set Vref, RX VrefLevel [Byte0]: 34
1686 22:15:40.720226 [Byte1]: 34
1687 22:15:40.724509
1688 22:15:40.725087 Set Vref, RX VrefLevel [Byte0]: 35
1689 22:15:40.727903 [Byte1]: 35
1690 22:15:40.732329
1691 22:15:40.732908 Set Vref, RX VrefLevel [Byte0]: 36
1692 22:15:40.735063 [Byte1]: 36
1693 22:15:40.739488
1694 22:15:40.740065 Set Vref, RX VrefLevel [Byte0]: 37
1695 22:15:40.742659 [Byte1]: 37
1696 22:15:40.747699
1697 22:15:40.748280 Set Vref, RX VrefLevel [Byte0]: 38
1698 22:15:40.750531 [Byte1]: 38
1699 22:15:40.754970
1700 22:15:40.755551 Set Vref, RX VrefLevel [Byte0]: 39
1701 22:15:40.758286 [Byte1]: 39
1702 22:15:40.762313
1703 22:15:40.762925 Set Vref, RX VrefLevel [Byte0]: 40
1704 22:15:40.765793 [Byte1]: 40
1705 22:15:40.769993
1706 22:15:40.770606 Set Vref, RX VrefLevel [Byte0]: 41
1707 22:15:40.773259 [Byte1]: 41
1708 22:15:40.777947
1709 22:15:40.778569 Set Vref, RX VrefLevel [Byte0]: 42
1710 22:15:40.781068 [Byte1]: 42
1711 22:15:40.784993
1712 22:15:40.785466 Set Vref, RX VrefLevel [Byte0]: 43
1713 22:15:40.788188 [Byte1]: 43
1714 22:15:40.793362
1715 22:15:40.793939 Set Vref, RX VrefLevel [Byte0]: 44
1716 22:15:40.796158 [Byte1]: 44
1717 22:15:40.801304
1718 22:15:40.801920 Set Vref, RX VrefLevel [Byte0]: 45
1719 22:15:40.803288 [Byte1]: 45
1720 22:15:40.807654
1721 22:15:40.808131 Set Vref, RX VrefLevel [Byte0]: 46
1722 22:15:40.811020 [Byte1]: 46
1723 22:15:40.815686
1724 22:15:40.816160 Set Vref, RX VrefLevel [Byte0]: 47
1725 22:15:40.819039 [Byte1]: 47
1726 22:15:40.823130
1727 22:15:40.823713 Set Vref, RX VrefLevel [Byte0]: 48
1728 22:15:40.826340 [Byte1]: 48
1729 22:15:40.831068
1730 22:15:40.831660 Set Vref, RX VrefLevel [Byte0]: 49
1731 22:15:40.834733 [Byte1]: 49
1732 22:15:40.838605
1733 22:15:40.839182 Set Vref, RX VrefLevel [Byte0]: 50
1734 22:15:40.841450 [Byte1]: 50
1735 22:15:40.847059
1736 22:15:40.847637 Set Vref, RX VrefLevel [Byte0]: 51
1737 22:15:40.849039 [Byte1]: 51
1738 22:15:40.853598
1739 22:15:40.854074 Set Vref, RX VrefLevel [Byte0]: 52
1740 22:15:40.856730 [Byte1]: 52
1741 22:15:40.861285
1742 22:15:40.861859 Set Vref, RX VrefLevel [Byte0]: 53
1743 22:15:40.864709 [Byte1]: 53
1744 22:15:40.868707
1745 22:15:40.869286 Set Vref, RX VrefLevel [Byte0]: 54
1746 22:15:40.872211 [Byte1]: 54
1747 22:15:40.876257
1748 22:15:40.876851 Set Vref, RX VrefLevel [Byte0]: 55
1749 22:15:40.880189 [Byte1]: 55
1750 22:15:40.884711
1751 22:15:40.885350 Set Vref, RX VrefLevel [Byte0]: 56
1752 22:15:40.887789 [Byte1]: 56
1753 22:15:40.891247
1754 22:15:40.891718 Set Vref, RX VrefLevel [Byte0]: 57
1755 22:15:40.895185 [Byte1]: 57
1756 22:15:40.899188
1757 22:15:40.899664 Set Vref, RX VrefLevel [Byte0]: 58
1758 22:15:40.902111 [Byte1]: 58
1759 22:15:40.906952
1760 22:15:40.907526 Set Vref, RX VrefLevel [Byte0]: 59
1761 22:15:40.910018 [Byte1]: 59
1762 22:15:40.914285
1763 22:15:40.914800 Set Vref, RX VrefLevel [Byte0]: 60
1764 22:15:40.917210 [Byte1]: 60
1765 22:15:40.922037
1766 22:15:40.922676 Set Vref, RX VrefLevel [Byte0]: 61
1767 22:15:40.925010 [Byte1]: 61
1768 22:15:40.929478
1769 22:15:40.930046 Set Vref, RX VrefLevel [Byte0]: 62
1770 22:15:40.932534 [Byte1]: 62
1771 22:15:40.937353
1772 22:15:40.937921 Set Vref, RX VrefLevel [Byte0]: 63
1773 22:15:40.941176 [Byte1]: 63
1774 22:15:40.944875
1775 22:15:40.945443 Set Vref, RX VrefLevel [Byte0]: 64
1776 22:15:40.948016 [Byte1]: 64
1777 22:15:40.952381
1778 22:15:40.952950 Set Vref, RX VrefLevel [Byte0]: 65
1779 22:15:40.955473 [Byte1]: 65
1780 22:15:40.959950
1781 22:15:40.960525 Set Vref, RX VrefLevel [Byte0]: 66
1782 22:15:40.963144 [Byte1]: 66
1783 22:15:40.967495
1784 22:15:40.968065 Set Vref, RX VrefLevel [Byte0]: 67
1785 22:15:40.970732 [Byte1]: 67
1786 22:15:40.975295
1787 22:15:40.975865 Set Vref, RX VrefLevel [Byte0]: 68
1788 22:15:40.978430 [Byte1]: 68
1789 22:15:40.982913
1790 22:15:40.983491 Set Vref, RX VrefLevel [Byte0]: 69
1791 22:15:40.985637 [Byte1]: 69
1792 22:15:40.990418
1793 22:15:40.990996 Set Vref, RX VrefLevel [Byte0]: 70
1794 22:15:40.993319 [Byte1]: 70
1795 22:15:40.998023
1796 22:15:40.998918 Set Vref, RX VrefLevel [Byte0]: 71
1797 22:15:41.001165 [Byte1]: 71
1798 22:15:41.005565
1799 22:15:41.006036 Set Vref, RX VrefLevel [Byte0]: 72
1800 22:15:41.008847 [Byte1]: 72
1801 22:15:41.013221
1802 22:15:41.013786 Set Vref, RX VrefLevel [Byte0]: 73
1803 22:15:41.016162 [Byte1]: 73
1804 22:15:41.020723
1805 22:15:41.021288 Set Vref, RX VrefLevel [Byte0]: 74
1806 22:15:41.024279 [Byte1]: 74
1807 22:15:41.028402
1808 22:15:41.028973 Set Vref, RX VrefLevel [Byte0]: 75
1809 22:15:41.031267 [Byte1]: 75
1810 22:15:41.035723
1811 22:15:41.036308 Set Vref, RX VrefLevel [Byte0]: 76
1812 22:15:41.039479 [Byte1]: 76
1813 22:15:41.043328
1814 22:15:41.043825 Final RX Vref Byte 0 = 51 to rank0
1815 22:15:41.046475 Final RX Vref Byte 1 = 62 to rank0
1816 22:15:41.050466 Final RX Vref Byte 0 = 51 to rank1
1817 22:15:41.053708 Final RX Vref Byte 1 = 62 to rank1==
1818 22:15:41.057218 Dram Type= 6, Freq= 0, CH_1, rank 0
1819 22:15:41.064434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1820 22:15:41.065007 ==
1821 22:15:41.065379 DQS Delay:
1822 22:15:41.065724 DQS0 = 0, DQS1 = 0
1823 22:15:41.066958 DQM Delay:
1824 22:15:41.067424 DQM0 = 92, DQM1 = 82
1825 22:15:41.070766 DQ Delay:
1826 22:15:41.073497 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =88
1827 22:15:41.076706 DQ4 =92, DQ5 =104, DQ6 =100, DQ7 =88
1828 22:15:41.080161 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =76
1829 22:15:41.083279 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =88
1830 22:15:41.083999
1831 22:15:41.084379
1832 22:15:41.089888 [DQSOSCAuto] RK0, (LSB)MR18= 0x2f4c, (MSB)MR19= 0x606, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
1833 22:15:41.093394 CH1 RK0: MR19=606, MR18=2F4C
1834 22:15:41.099964 CH1_RK0: MR19=0x606, MR18=0x2F4C, DQSOSC=390, MR23=63, INC=97, DEC=64
1835 22:15:41.100691
1836 22:15:41.103047 ----->DramcWriteLeveling(PI) begin...
1837 22:15:41.103533 ==
1838 22:15:41.106306 Dram Type= 6, Freq= 0, CH_1, rank 1
1839 22:15:41.109968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1840 22:15:41.110476 ==
1841 22:15:41.113179 Write leveling (Byte 0): 29 => 29
1842 22:15:41.116806 Write leveling (Byte 1): 30 => 30
1843 22:15:41.119927 DramcWriteLeveling(PI) end<-----
1844 22:15:41.120500
1845 22:15:41.120866 ==
1846 22:15:41.123327 Dram Type= 6, Freq= 0, CH_1, rank 1
1847 22:15:41.126713 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1848 22:15:41.127286 ==
1849 22:15:41.129879 [Gating] SW mode calibration
1850 22:15:41.136567 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1851 22:15:41.142983 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1852 22:15:41.146254 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1853 22:15:41.152910 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1854 22:15:41.156801 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1855 22:15:41.159562 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 22:15:41.163208 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1857 22:15:41.169518 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 22:15:41.172498 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 22:15:41.176588 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 22:15:41.182739 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1861 22:15:41.186170 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 22:15:41.189522 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 22:15:41.195980 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1864 22:15:41.199402 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1865 22:15:41.203263 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1866 22:15:41.209488 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1867 22:15:41.212520 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1868 22:15:41.216123 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1869 22:15:41.222680 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 1)
1870 22:15:41.226038 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 22:15:41.229997 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 22:15:41.236363 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 22:15:41.239243 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 22:15:41.242596 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 22:15:41.249058 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 22:15:41.252216 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 22:15:41.255722 0 9 4 | B1->B0 | 2726 2323 | 1 0 | (1 0) (0 0)
1878 22:15:41.262378 0 9 8 | B1->B0 | 3434 3434 | 0 0 | (0 0) (0 0)
1879 22:15:41.265764 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1880 22:15:41.269431 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1881 22:15:41.275590 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1882 22:15:41.278578 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1883 22:15:41.282487 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1884 22:15:41.289208 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1885 22:15:41.291742 0 10 4 | B1->B0 | 2f2f 3030 | 0 0 | (0 1) (0 1)
1886 22:15:41.295446 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1887 22:15:41.301929 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 22:15:41.305025 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 22:15:41.308714 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 22:15:41.315519 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 22:15:41.318794 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 22:15:41.322061 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 22:15:41.328693 0 11 4 | B1->B0 | 3131 2f2f | 1 0 | (0 0) (0 0)
1894 22:15:41.331869 0 11 8 | B1->B0 | 4545 4343 | 0 0 | (0 0) (0 0)
1895 22:15:41.335360 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1896 22:15:41.341993 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1897 22:15:41.345182 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1898 22:15:41.348831 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1899 22:15:41.351575 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1900 22:15:41.358588 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1901 22:15:41.361586 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1902 22:15:41.365019 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1903 22:15:41.372746 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1904 22:15:41.374810 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1905 22:15:41.378591 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1906 22:15:41.385186 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1907 22:15:41.388468 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1908 22:15:41.391634 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1909 22:15:41.398222 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1910 22:15:41.401474 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1911 22:15:41.404705 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1912 22:15:41.411779 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1913 22:15:41.414950 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1914 22:15:41.419308 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1915 22:15:41.424774 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1916 22:15:41.428208 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1917 22:15:41.431577 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1918 22:15:41.438125 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1919 22:15:41.438736 Total UI for P1: 0, mck2ui 16
1920 22:15:41.444967 best dqsien dly found for B1: ( 0, 14, 4)
1921 22:15:41.448237 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1922 22:15:41.451310 Total UI for P1: 0, mck2ui 16
1923 22:15:41.454992 best dqsien dly found for B0: ( 0, 14, 6)
1924 22:15:41.457691 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1925 22:15:41.461057 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1926 22:15:41.461705
1927 22:15:41.464454 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1928 22:15:41.467776 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1929 22:15:41.471212 [Gating] SW calibration Done
1930 22:15:41.471790 ==
1931 22:15:41.474337 Dram Type= 6, Freq= 0, CH_1, rank 1
1932 22:15:41.477801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1933 22:15:41.481195 ==
1934 22:15:41.481661 RX Vref Scan: 0
1935 22:15:41.482033
1936 22:15:41.484277 RX Vref 0 -> 0, step: 1
1937 22:15:41.484748
1938 22:15:41.488040 RX Delay -130 -> 252, step: 16
1939 22:15:41.491181 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1940 22:15:41.494731 iDelay=206, Bit 1, Center 85 (-18 ~ 189) 208
1941 22:15:41.498220 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1942 22:15:41.500970 iDelay=206, Bit 3, Center 93 (-18 ~ 205) 224
1943 22:15:41.507709 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1944 22:15:41.511286 iDelay=206, Bit 5, Center 101 (-2 ~ 205) 208
1945 22:15:41.514735 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1946 22:15:41.517560 iDelay=206, Bit 7, Center 85 (-18 ~ 189) 208
1947 22:15:41.521256 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1948 22:15:41.524453 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
1949 22:15:41.530920 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1950 22:15:41.534791 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1951 22:15:41.537776 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1952 22:15:41.541017 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1953 22:15:41.547419 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1954 22:15:41.551242 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1955 22:15:41.551817 ==
1956 22:15:41.554520 Dram Type= 6, Freq= 0, CH_1, rank 1
1957 22:15:41.557235 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1958 22:15:41.557707 ==
1959 22:15:41.560850 DQS Delay:
1960 22:15:41.561419 DQS0 = 0, DQS1 = 0
1961 22:15:41.561874 DQM Delay:
1962 22:15:41.563933 DQM0 = 90, DQM1 = 82
1963 22:15:41.564474 DQ Delay:
1964 22:15:41.567659 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1965 22:15:41.570924 DQ4 =93, DQ5 =101, DQ6 =93, DQ7 =85
1966 22:15:41.574902 DQ8 =69, DQ9 =77, DQ10 =85, DQ11 =77
1967 22:15:41.577385 DQ12 =93, DQ13 =85, DQ14 =85, DQ15 =85
1968 22:15:41.577855
1969 22:15:41.578318
1970 22:15:41.578855 ==
1971 22:15:41.580775 Dram Type= 6, Freq= 0, CH_1, rank 1
1972 22:15:41.587564 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1973 22:15:41.588137 ==
1974 22:15:41.588518
1975 22:15:41.588860
1976 22:15:41.589191 TX Vref Scan disable
1977 22:15:41.590989 == TX Byte 0 ==
1978 22:15:41.594215 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1979 22:15:41.600570 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1980 22:15:41.601124 == TX Byte 1 ==
1981 22:15:41.604036 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1982 22:15:41.607966 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1983 22:15:41.610487 ==
1984 22:15:41.614468 Dram Type= 6, Freq= 0, CH_1, rank 1
1985 22:15:41.617799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1986 22:15:41.618411 ==
1987 22:15:41.630013 TX Vref=22, minBit 12, minWin=27, winSum=446
1988 22:15:41.632920 TX Vref=24, minBit 13, minWin=27, winSum=453
1989 22:15:41.636351 TX Vref=26, minBit 13, minWin=27, winSum=457
1990 22:15:41.640179 TX Vref=28, minBit 13, minWin=27, winSum=456
1991 22:15:41.646321 TX Vref=30, minBit 15, minWin=27, winSum=461
1992 22:15:41.649405 TX Vref=32, minBit 8, minWin=28, winSum=458
1993 22:15:41.652547 [TxChooseVref] Worse bit 8, Min win 28, Win sum 458, Final Vref 32
1994 22:15:41.656430
1995 22:15:41.656995 Final TX Range 1 Vref 32
1996 22:15:41.657370
1997 22:15:41.657712 ==
1998 22:15:41.659567 Dram Type= 6, Freq= 0, CH_1, rank 1
1999 22:15:41.666056 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2000 22:15:41.666636 ==
2001 22:15:41.667008
2002 22:15:41.667351
2003 22:15:41.667681 TX Vref Scan disable
2004 22:15:41.669815 == TX Byte 0 ==
2005 22:15:41.673372 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2006 22:15:41.676683 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2007 22:15:41.680323 == TX Byte 1 ==
2008 22:15:41.683651 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2009 22:15:41.686426 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2010 22:15:41.689750
2011 22:15:41.690215 [DATLAT]
2012 22:15:41.690643 Freq=800, CH1 RK1
2013 22:15:41.691000
2014 22:15:41.693199 DATLAT Default: 0xa
2015 22:15:41.693765 0, 0xFFFF, sum = 0
2016 22:15:41.696438 1, 0xFFFF, sum = 0
2017 22:15:41.697008 2, 0xFFFF, sum = 0
2018 22:15:41.700319 3, 0xFFFF, sum = 0
2019 22:15:41.700890 4, 0xFFFF, sum = 0
2020 22:15:41.703711 5, 0xFFFF, sum = 0
2021 22:15:41.704188 6, 0xFFFF, sum = 0
2022 22:15:41.706444 7, 0xFFFF, sum = 0
2023 22:15:41.710096 8, 0xFFFF, sum = 0
2024 22:15:41.710747 9, 0x0, sum = 1
2025 22:15:41.711132 10, 0x0, sum = 2
2026 22:15:41.713163 11, 0x0, sum = 3
2027 22:15:41.713739 12, 0x0, sum = 4
2028 22:15:41.716552 best_step = 10
2029 22:15:41.717020
2030 22:15:41.717387 ==
2031 22:15:41.720686 Dram Type= 6, Freq= 0, CH_1, rank 1
2032 22:15:41.723346 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2033 22:15:41.723920 ==
2034 22:15:41.726396 RX Vref Scan: 0
2035 22:15:41.726869
2036 22:15:41.727237 RX Vref 0 -> 0, step: 1
2037 22:15:41.727581
2038 22:15:41.730064 RX Delay -95 -> 252, step: 8
2039 22:15:41.736872 iDelay=209, Bit 0, Center 92 (-7 ~ 192) 200
2040 22:15:41.739985 iDelay=209, Bit 1, Center 88 (-15 ~ 192) 208
2041 22:15:41.742990 iDelay=209, Bit 2, Center 80 (-23 ~ 184) 208
2042 22:15:41.746905 iDelay=209, Bit 3, Center 88 (-15 ~ 192) 208
2043 22:15:41.749946 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
2044 22:15:41.756573 iDelay=209, Bit 5, Center 100 (-7 ~ 208) 216
2045 22:15:41.759876 iDelay=209, Bit 6, Center 96 (-7 ~ 200) 208
2046 22:15:41.763255 iDelay=209, Bit 7, Center 88 (-15 ~ 192) 208
2047 22:15:41.767163 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2048 22:15:41.769705 iDelay=209, Bit 9, Center 76 (-31 ~ 184) 216
2049 22:15:41.776710 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
2050 22:15:41.780388 iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224
2051 22:15:41.782885 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
2052 22:15:41.786300 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2053 22:15:41.789690 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2054 22:15:41.796100 iDelay=209, Bit 15, Center 92 (-23 ~ 208) 232
2055 22:15:41.796686 ==
2056 22:15:41.799745 Dram Type= 6, Freq= 0, CH_1, rank 1
2057 22:15:41.802926 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2058 22:15:41.803489 ==
2059 22:15:41.803867 DQS Delay:
2060 22:15:41.805872 DQS0 = 0, DQS1 = 0
2061 22:15:41.806344 DQM Delay:
2062 22:15:41.809616 DQM0 = 90, DQM1 = 83
2063 22:15:41.810198 DQ Delay:
2064 22:15:41.813353 DQ0 =92, DQ1 =88, DQ2 =80, DQ3 =88
2065 22:15:41.816119 DQ4 =92, DQ5 =100, DQ6 =96, DQ7 =88
2066 22:15:41.819337 DQ8 =68, DQ9 =76, DQ10 =84, DQ11 =80
2067 22:15:41.822981 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =92
2068 22:15:41.823554
2069 22:15:41.823928
2070 22:15:41.832792 [DQSOSCAuto] RK1, (LSB)MR18= 0x3a0f, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 395 ps
2071 22:15:41.833438 CH1 RK1: MR19=606, MR18=3A0F
2072 22:15:41.839379 CH1_RK1: MR19=0x606, MR18=0x3A0F, DQSOSC=395, MR23=63, INC=94, DEC=63
2073 22:15:41.842989 [RxdqsGatingPostProcess] freq 800
2074 22:15:41.849363 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2075 22:15:41.852687 Pre-setting of DQS Precalculation
2076 22:15:41.855755 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2077 22:15:41.862666 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2078 22:15:41.872660 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2079 22:15:41.873234
2080 22:15:41.873603
2081 22:15:41.877105 [Calibration Summary] 1600 Mbps
2082 22:15:41.877678 CH 0, Rank 0
2083 22:15:41.879722 SW Impedance : PASS
2084 22:15:41.880286 DUTY Scan : NO K
2085 22:15:41.882532 ZQ Calibration : PASS
2086 22:15:41.883096 Jitter Meter : NO K
2087 22:15:41.886437 CBT Training : PASS
2088 22:15:41.888746 Write leveling : PASS
2089 22:15:41.889231 RX DQS gating : PASS
2090 22:15:41.892467 RX DQ/DQS(RDDQC) : PASS
2091 22:15:41.895661 TX DQ/DQS : PASS
2092 22:15:41.896161 RX DATLAT : PASS
2093 22:15:41.898926 RX DQ/DQS(Engine): PASS
2094 22:15:41.902280 TX OE : NO K
2095 22:15:41.902898 All Pass.
2096 22:15:41.903517
2097 22:15:41.904025 CH 0, Rank 1
2098 22:15:41.905311 SW Impedance : PASS
2099 22:15:41.909090 DUTY Scan : NO K
2100 22:15:41.909667 ZQ Calibration : PASS
2101 22:15:41.912492 Jitter Meter : NO K
2102 22:15:41.915593 CBT Training : PASS
2103 22:15:41.916167 Write leveling : PASS
2104 22:15:41.919052 RX DQS gating : PASS
2105 22:15:41.922192 RX DQ/DQS(RDDQC) : PASS
2106 22:15:41.922806 TX DQ/DQS : PASS
2107 22:15:41.925649 RX DATLAT : PASS
2108 22:15:41.929583 RX DQ/DQS(Engine): PASS
2109 22:15:41.930157 TX OE : NO K
2110 22:15:41.930599 All Pass.
2111 22:15:41.931985
2112 22:15:41.932450 CH 1, Rank 0
2113 22:15:41.935885 SW Impedance : PASS
2114 22:15:41.936461 DUTY Scan : NO K
2115 22:15:41.938683 ZQ Calibration : PASS
2116 22:15:41.942479 Jitter Meter : NO K
2117 22:15:41.943051 CBT Training : PASS
2118 22:15:41.945445 Write leveling : PASS
2119 22:15:41.946019 RX DQS gating : PASS
2120 22:15:41.948718 RX DQ/DQS(RDDQC) : PASS
2121 22:15:41.952441 TX DQ/DQS : PASS
2122 22:15:41.953013 RX DATLAT : PASS
2123 22:15:41.955016 RX DQ/DQS(Engine): PASS
2124 22:15:41.958915 TX OE : NO K
2125 22:15:41.959492 All Pass.
2126 22:15:41.959864
2127 22:15:41.960207 CH 1, Rank 1
2128 22:15:41.961929 SW Impedance : PASS
2129 22:15:41.965185 DUTY Scan : NO K
2130 22:15:41.965652 ZQ Calibration : PASS
2131 22:15:41.968418 Jitter Meter : NO K
2132 22:15:41.971879 CBT Training : PASS
2133 22:15:41.972453 Write leveling : PASS
2134 22:15:41.975267 RX DQS gating : PASS
2135 22:15:41.979251 RX DQ/DQS(RDDQC) : PASS
2136 22:15:41.979824 TX DQ/DQS : PASS
2137 22:15:41.982348 RX DATLAT : PASS
2138 22:15:41.985251 RX DQ/DQS(Engine): PASS
2139 22:15:41.985724 TX OE : NO K
2140 22:15:41.986095 All Pass.
2141 22:15:41.988552
2142 22:15:41.989105 DramC Write-DBI off
2143 22:15:41.991841 PER_BANK_REFRESH: Hybrid Mode
2144 22:15:41.992312 TX_TRACKING: ON
2145 22:15:41.995381 [GetDramInforAfterCalByMRR] Vendor 6.
2146 22:15:41.998589 [GetDramInforAfterCalByMRR] Revision 606.
2147 22:15:42.005126 [GetDramInforAfterCalByMRR] Revision 2 0.
2148 22:15:42.005700 MR0 0x3b3b
2149 22:15:42.006103 MR8 0x5151
2150 22:15:42.009025 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2151 22:15:42.009591
2152 22:15:42.011889 MR0 0x3b3b
2153 22:15:42.012495 MR8 0x5151
2154 22:15:42.015464 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2155 22:15:42.016081
2156 22:15:42.025299 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2157 22:15:42.028387 [FAST_K] Save calibration result to emmc
2158 22:15:42.031875 [FAST_K] Save calibration result to emmc
2159 22:15:42.034790 dram_init: config_dvfs: 1
2160 22:15:42.038777 dramc_set_vcore_voltage set vcore to 662500
2161 22:15:42.042220 Read voltage for 1200, 2
2162 22:15:42.042755 Vio18 = 0
2163 22:15:42.043129 Vcore = 662500
2164 22:15:42.044638 Vdram = 0
2165 22:15:42.045106 Vddq = 0
2166 22:15:42.045470 Vmddr = 0
2167 22:15:42.052154 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2168 22:15:42.055084 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2169 22:15:42.057840 MEM_TYPE=3, freq_sel=15
2170 22:15:42.061653 sv_algorithm_assistance_LP4_1600
2171 22:15:42.064870 ============ PULL DRAM RESETB DOWN ============
2172 22:15:42.068623 ========== PULL DRAM RESETB DOWN end =========
2173 22:15:42.074842 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2174 22:15:42.078141 ===================================
2175 22:15:42.078742 LPDDR4 DRAM CONFIGURATION
2176 22:15:42.081952 ===================================
2177 22:15:42.084907 EX_ROW_EN[0] = 0x0
2178 22:15:42.088538 EX_ROW_EN[1] = 0x0
2179 22:15:42.089082 LP4Y_EN = 0x0
2180 22:15:42.091100 WORK_FSP = 0x0
2181 22:15:42.091568 WL = 0x4
2182 22:15:42.095173 RL = 0x4
2183 22:15:42.095744 BL = 0x2
2184 22:15:42.098582 RPST = 0x0
2185 22:15:42.099047 RD_PRE = 0x0
2186 22:15:42.101291 WR_PRE = 0x1
2187 22:15:42.101863 WR_PST = 0x0
2188 22:15:42.104375 DBI_WR = 0x0
2189 22:15:42.105042 DBI_RD = 0x0
2190 22:15:42.108046 OTF = 0x1
2191 22:15:42.111284 ===================================
2192 22:15:42.114816 ===================================
2193 22:15:42.115441 ANA top config
2194 22:15:42.117889 ===================================
2195 22:15:42.121078 DLL_ASYNC_EN = 0
2196 22:15:42.124282 ALL_SLAVE_EN = 0
2197 22:15:42.127631 NEW_RANK_MODE = 1
2198 22:15:42.128114 DLL_IDLE_MODE = 1
2199 22:15:42.130941 LP45_APHY_COMB_EN = 1
2200 22:15:42.134911 TX_ODT_DIS = 1
2201 22:15:42.137951 NEW_8X_MODE = 1
2202 22:15:42.141115 ===================================
2203 22:15:42.144375 ===================================
2204 22:15:42.148300 data_rate = 2400
2205 22:15:42.148866 CKR = 1
2206 22:15:42.150996 DQ_P2S_RATIO = 8
2207 22:15:42.154458 ===================================
2208 22:15:42.157740 CA_P2S_RATIO = 8
2209 22:15:42.161168 DQ_CA_OPEN = 0
2210 22:15:42.164687 DQ_SEMI_OPEN = 0
2211 22:15:42.165250 CA_SEMI_OPEN = 0
2212 22:15:42.167726 CA_FULL_RATE = 0
2213 22:15:42.171209 DQ_CKDIV4_EN = 0
2214 22:15:42.174141 CA_CKDIV4_EN = 0
2215 22:15:42.177524 CA_PREDIV_EN = 0
2216 22:15:42.180794 PH8_DLY = 17
2217 22:15:42.184096 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2218 22:15:42.184658 DQ_AAMCK_DIV = 4
2219 22:15:42.187589 CA_AAMCK_DIV = 4
2220 22:15:42.191015 CA_ADMCK_DIV = 4
2221 22:15:42.194510 DQ_TRACK_CA_EN = 0
2222 22:15:42.197961 CA_PICK = 1200
2223 22:15:42.200769 CA_MCKIO = 1200
2224 22:15:42.204284 MCKIO_SEMI = 0
2225 22:15:42.204899 PLL_FREQ = 2366
2226 22:15:42.207030 DQ_UI_PI_RATIO = 32
2227 22:15:42.210698 CA_UI_PI_RATIO = 0
2228 22:15:42.214174 ===================================
2229 22:15:42.217365 ===================================
2230 22:15:42.220370 memory_type:LPDDR4
2231 22:15:42.220950 GP_NUM : 10
2232 22:15:42.223678 SRAM_EN : 1
2233 22:15:42.227137 MD32_EN : 0
2234 22:15:42.230785 ===================================
2235 22:15:42.231360 [ANA_INIT] >>>>>>>>>>>>>>
2236 22:15:42.233731 <<<<<< [CONFIGURE PHASE]: ANA_TX
2237 22:15:42.237235 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2238 22:15:42.240587 ===================================
2239 22:15:42.243730 data_rate = 2400,PCW = 0X5b00
2240 22:15:42.247411 ===================================
2241 22:15:42.250418 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2242 22:15:42.257006 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2243 22:15:42.260094 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2244 22:15:42.266928 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2245 22:15:42.270429 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2246 22:15:42.273905 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2247 22:15:42.277533 [ANA_INIT] flow start
2248 22:15:42.278097 [ANA_INIT] PLL >>>>>>>>
2249 22:15:42.280627 [ANA_INIT] PLL <<<<<<<<
2250 22:15:42.283350 [ANA_INIT] MIDPI >>>>>>>>
2251 22:15:42.283823 [ANA_INIT] MIDPI <<<<<<<<
2252 22:15:42.287331 [ANA_INIT] DLL >>>>>>>>
2253 22:15:42.290520 [ANA_INIT] DLL <<<<<<<<
2254 22:15:42.291089 [ANA_INIT] flow end
2255 22:15:42.297173 ============ LP4 DIFF to SE enter ============
2256 22:15:42.300317 ============ LP4 DIFF to SE exit ============
2257 22:15:42.300893 [ANA_INIT] <<<<<<<<<<<<<
2258 22:15:42.303570 [Flow] Enable top DCM control >>>>>
2259 22:15:42.306657 [Flow] Enable top DCM control <<<<<
2260 22:15:42.310511 Enable DLL master slave shuffle
2261 22:15:42.317173 ==============================================================
2262 22:15:42.317750 Gating Mode config
2263 22:15:42.323343 ==============================================================
2264 22:15:42.326943 Config description:
2265 22:15:42.336528 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2266 22:15:42.343057 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2267 22:15:42.346778 SELPH_MODE 0: By rank 1: By Phase
2268 22:15:42.353557 ==============================================================
2269 22:15:42.356828 GAT_TRACK_EN = 1
2270 22:15:42.360001 RX_GATING_MODE = 2
2271 22:15:42.360476 RX_GATING_TRACK_MODE = 2
2272 22:15:42.363579 SELPH_MODE = 1
2273 22:15:42.366677 PICG_EARLY_EN = 1
2274 22:15:42.370277 VALID_LAT_VALUE = 1
2275 22:15:42.376788 ==============================================================
2276 22:15:42.380012 Enter into Gating configuration >>>>
2277 22:15:42.383522 Exit from Gating configuration <<<<
2278 22:15:42.387287 Enter into DVFS_PRE_config >>>>>
2279 22:15:42.396531 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2280 22:15:42.400169 Exit from DVFS_PRE_config <<<<<
2281 22:15:42.403232 Enter into PICG configuration >>>>
2282 22:15:42.406444 Exit from PICG configuration <<<<
2283 22:15:42.409459 [RX_INPUT] configuration >>>>>
2284 22:15:42.413629 [RX_INPUT] configuration <<<<<
2285 22:15:42.416528 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2286 22:15:42.422958 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2287 22:15:42.429537 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2288 22:15:42.436230 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2289 22:15:42.439721 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2290 22:15:42.445918 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2291 22:15:42.449374 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2292 22:15:42.456270 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2293 22:15:42.459652 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2294 22:15:42.464468 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2295 22:15:42.465930 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2296 22:15:42.472917 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2297 22:15:42.475927 ===================================
2298 22:15:42.479466 LPDDR4 DRAM CONFIGURATION
2299 22:15:42.482851 ===================================
2300 22:15:42.483422 EX_ROW_EN[0] = 0x0
2301 22:15:42.486571 EX_ROW_EN[1] = 0x0
2302 22:15:42.487140 LP4Y_EN = 0x0
2303 22:15:42.489349 WORK_FSP = 0x0
2304 22:15:42.489819 WL = 0x4
2305 22:15:42.492396 RL = 0x4
2306 22:15:42.492864 BL = 0x2
2307 22:15:42.495991 RPST = 0x0
2308 22:15:42.496562 RD_PRE = 0x0
2309 22:15:42.499597 WR_PRE = 0x1
2310 22:15:42.500165 WR_PST = 0x0
2311 22:15:42.502668 DBI_WR = 0x0
2312 22:15:42.503236 DBI_RD = 0x0
2313 22:15:42.505808 OTF = 0x1
2314 22:15:42.509187 ===================================
2315 22:15:42.512931 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2316 22:15:42.515790 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2317 22:15:42.522532 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2318 22:15:42.526269 ===================================
2319 22:15:42.526879 LPDDR4 DRAM CONFIGURATION
2320 22:15:42.529436 ===================================
2321 22:15:42.532430 EX_ROW_EN[0] = 0x10
2322 22:15:42.535978 EX_ROW_EN[1] = 0x0
2323 22:15:42.536558 LP4Y_EN = 0x0
2324 22:15:42.539063 WORK_FSP = 0x0
2325 22:15:42.539534 WL = 0x4
2326 22:15:42.542491 RL = 0x4
2327 22:15:42.543069 BL = 0x2
2328 22:15:42.545616 RPST = 0x0
2329 22:15:42.546090 RD_PRE = 0x0
2330 22:15:42.549000 WR_PRE = 0x1
2331 22:15:42.549458 WR_PST = 0x0
2332 22:15:42.552628 DBI_WR = 0x0
2333 22:15:42.553089 DBI_RD = 0x0
2334 22:15:42.555753 OTF = 0x1
2335 22:15:42.558783 ===================================
2336 22:15:42.565966 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2337 22:15:42.566472 ==
2338 22:15:42.568653 Dram Type= 6, Freq= 0, CH_0, rank 0
2339 22:15:42.572607 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2340 22:15:42.573068 ==
2341 22:15:42.575446 [Duty_Offset_Calibration]
2342 22:15:42.575904 B0:2 B1:0 CA:1
2343 22:15:42.576325
2344 22:15:42.578724 [DutyScan_Calibration_Flow] k_type=0
2345 22:15:42.588538
2346 22:15:42.589202 ==CLK 0==
2347 22:15:42.591806 Final CLK duty delay cell = -4
2348 22:15:42.595030 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2349 22:15:42.598429 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2350 22:15:42.601405 [-4] AVG Duty = 4953%(X100)
2351 22:15:42.601820
2352 22:15:42.605467 CH0 CLK Duty spec in!! Max-Min= 156%
2353 22:15:42.608119 [DutyScan_Calibration_Flow] ====Done====
2354 22:15:42.608585
2355 22:15:42.611591 [DutyScan_Calibration_Flow] k_type=1
2356 22:15:42.627499
2357 22:15:42.628012 ==DQS 0 ==
2358 22:15:42.630847 Final DQS duty delay cell = 0
2359 22:15:42.634084 [0] MAX Duty = 5187%(X100), DQS PI = 30
2360 22:15:42.637614 [0] MIN Duty = 4938%(X100), DQS PI = 0
2361 22:15:42.638174 [0] AVG Duty = 5062%(X100)
2362 22:15:42.640718
2363 22:15:42.641274 ==DQS 1 ==
2364 22:15:42.643963 Final DQS duty delay cell = -4
2365 22:15:42.647385 [-4] MAX Duty = 5124%(X100), DQS PI = 32
2366 22:15:42.650812 [-4] MIN Duty = 4938%(X100), DQS PI = 8
2367 22:15:42.653956 [-4] AVG Duty = 5031%(X100)
2368 22:15:42.654555
2369 22:15:42.657025 CH0 DQS 0 Duty spec in!! Max-Min= 249%
2370 22:15:42.657504
2371 22:15:42.660412 CH0 DQS 1 Duty spec in!! Max-Min= 186%
2372 22:15:42.663870 [DutyScan_Calibration_Flow] ====Done====
2373 22:15:42.664437
2374 22:15:42.667176 [DutyScan_Calibration_Flow] k_type=3
2375 22:15:42.684091
2376 22:15:42.684711 ==DQM 0 ==
2377 22:15:42.687117 Final DQM duty delay cell = 0
2378 22:15:42.690516 [0] MAX Duty = 5062%(X100), DQS PI = 24
2379 22:15:42.694039 [0] MIN Duty = 4844%(X100), DQS PI = 2
2380 22:15:42.694538 [0] AVG Duty = 4953%(X100)
2381 22:15:42.697480
2382 22:15:42.698032 ==DQM 1 ==
2383 22:15:42.700567 Final DQM duty delay cell = 0
2384 22:15:42.704162 [0] MAX Duty = 5187%(X100), DQS PI = 46
2385 22:15:42.707445 [0] MIN Duty = 5000%(X100), DQS PI = 24
2386 22:15:42.710471 [0] AVG Duty = 5093%(X100)
2387 22:15:42.710935
2388 22:15:42.715760 CH0 DQM 0 Duty spec in!! Max-Min= 218%
2389 22:15:42.716326
2390 22:15:42.717053 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2391 22:15:42.720696 [DutyScan_Calibration_Flow] ====Done====
2392 22:15:42.721260
2393 22:15:42.723949 [DutyScan_Calibration_Flow] k_type=2
2394 22:15:42.739773
2395 22:15:42.740335 ==DQ 0 ==
2396 22:15:42.743340 Final DQ duty delay cell = -4
2397 22:15:42.746535 [-4] MAX Duty = 5031%(X100), DQS PI = 32
2398 22:15:42.749914 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2399 22:15:42.753283 [-4] AVG Duty = 4969%(X100)
2400 22:15:42.753844
2401 22:15:42.754206 ==DQ 1 ==
2402 22:15:42.756369 Final DQ duty delay cell = 0
2403 22:15:42.759995 [0] MAX Duty = 4969%(X100), DQS PI = 56
2404 22:15:42.763106 [0] MIN Duty = 4907%(X100), DQS PI = 0
2405 22:15:42.763674 [0] AVG Duty = 4938%(X100)
2406 22:15:42.766147
2407 22:15:42.770080 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2408 22:15:42.770724
2409 22:15:42.772894 CH0 DQ 1 Duty spec in!! Max-Min= 62%
2410 22:15:42.776283 [DutyScan_Calibration_Flow] ====Done====
2411 22:15:42.776888 ==
2412 22:15:42.779808 Dram Type= 6, Freq= 0, CH_1, rank 0
2413 22:15:42.782758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2414 22:15:42.783224 ==
2415 22:15:42.786027 [Duty_Offset_Calibration]
2416 22:15:42.786525 B0:0 B1:-1 CA:2
2417 22:15:42.786895
2418 22:15:42.789756 [DutyScan_Calibration_Flow] k_type=0
2419 22:15:42.799674
2420 22:15:42.800176 ==CLK 0==
2421 22:15:42.803195 Final CLK duty delay cell = 0
2422 22:15:42.806767 [0] MAX Duty = 5156%(X100), DQS PI = 16
2423 22:15:42.809783 [0] MIN Duty = 4938%(X100), DQS PI = 44
2424 22:15:42.810391 [0] AVG Duty = 5047%(X100)
2425 22:15:42.813281
2426 22:15:42.817136 CH1 CLK Duty spec in!! Max-Min= 218%
2427 22:15:42.820023 [DutyScan_Calibration_Flow] ====Done====
2428 22:15:42.820600
2429 22:15:42.823875 [DutyScan_Calibration_Flow] k_type=1
2430 22:15:42.839393
2431 22:15:42.839973 ==DQS 0 ==
2432 22:15:42.842904 Final DQS duty delay cell = 0
2433 22:15:42.845812 [0] MAX Duty = 5093%(X100), DQS PI = 24
2434 22:15:42.849306 [0] MIN Duty = 4969%(X100), DQS PI = 0
2435 22:15:42.849886 [0] AVG Duty = 5031%(X100)
2436 22:15:42.852997
2437 22:15:42.853570 ==DQS 1 ==
2438 22:15:42.856026 Final DQS duty delay cell = 0
2439 22:15:42.859198 [0] MAX Duty = 5187%(X100), DQS PI = 0
2440 22:15:42.862671 [0] MIN Duty = 4844%(X100), DQS PI = 36
2441 22:15:42.863246 [0] AVG Duty = 5015%(X100)
2442 22:15:42.865915
2443 22:15:42.869721 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2444 22:15:42.870292
2445 22:15:42.872642 CH1 DQS 1 Duty spec in!! Max-Min= 343%
2446 22:15:42.875640 [DutyScan_Calibration_Flow] ====Done====
2447 22:15:42.876119
2448 22:15:42.879082 [DutyScan_Calibration_Flow] k_type=3
2449 22:15:42.896947
2450 22:15:42.897521 ==DQM 0 ==
2451 22:15:42.899765 Final DQM duty delay cell = 4
2452 22:15:42.903320 [4] MAX Duty = 5093%(X100), DQS PI = 6
2453 22:15:42.906424 [4] MIN Duty = 4938%(X100), DQS PI = 46
2454 22:15:42.909473 [4] AVG Duty = 5015%(X100)
2455 22:15:42.909955
2456 22:15:42.910328 ==DQM 1 ==
2457 22:15:42.912950 Final DQM duty delay cell = 0
2458 22:15:42.916234 [0] MAX Duty = 5249%(X100), DQS PI = 0
2459 22:15:42.920033 [0] MIN Duty = 4875%(X100), DQS PI = 36
2460 22:15:42.923004 [0] AVG Duty = 5062%(X100)
2461 22:15:42.923581
2462 22:15:42.926416 CH1 DQM 0 Duty spec in!! Max-Min= 155%
2463 22:15:42.926995
2464 22:15:42.929760 CH1 DQM 1 Duty spec in!! Max-Min= 374%
2465 22:15:42.932937 [DutyScan_Calibration_Flow] ====Done====
2466 22:15:42.933515
2467 22:15:42.936359 [DutyScan_Calibration_Flow] k_type=2
2468 22:15:42.953267
2469 22:15:42.953841 ==DQ 0 ==
2470 22:15:42.956609 Final DQ duty delay cell = 0
2471 22:15:42.959704 [0] MAX Duty = 5062%(X100), DQS PI = 20
2472 22:15:42.963228 [0] MIN Duty = 4938%(X100), DQS PI = 0
2473 22:15:42.963808 [0] AVG Duty = 5000%(X100)
2474 22:15:42.966178
2475 22:15:42.966802 ==DQ 1 ==
2476 22:15:42.969586 Final DQ duty delay cell = 0
2477 22:15:42.972938 [0] MAX Duty = 5031%(X100), DQS PI = 0
2478 22:15:42.977473 [0] MIN Duty = 4813%(X100), DQS PI = 34
2479 22:15:42.978054 [0] AVG Duty = 4922%(X100)
2480 22:15:42.978465
2481 22:15:42.979275 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2482 22:15:42.982676
2483 22:15:42.985977 CH1 DQ 1 Duty spec in!! Max-Min= 218%
2484 22:15:42.989097 [DutyScan_Calibration_Flow] ====Done====
2485 22:15:42.992832 nWR fixed to 30
2486 22:15:42.993309 [ModeRegInit_LP4] CH0 RK0
2487 22:15:42.995557 [ModeRegInit_LP4] CH0 RK1
2488 22:15:42.999014 [ModeRegInit_LP4] CH1 RK0
2489 22:15:43.002251 [ModeRegInit_LP4] CH1 RK1
2490 22:15:43.002780 match AC timing 7
2491 22:15:43.006124 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2492 22:15:43.012647 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2493 22:15:43.015511 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2494 22:15:43.022528 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2495 22:15:43.025819 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2496 22:15:43.026429 ==
2497 22:15:43.030147 Dram Type= 6, Freq= 0, CH_0, rank 0
2498 22:15:43.032818 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2499 22:15:43.033398 ==
2500 22:15:43.039074 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2501 22:15:43.045571 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2502 22:15:43.053290 [CA 0] Center 38 (8~69) winsize 62
2503 22:15:43.056682 [CA 1] Center 38 (7~69) winsize 63
2504 22:15:43.059881 [CA 2] Center 35 (5~66) winsize 62
2505 22:15:43.062445 [CA 3] Center 35 (4~66) winsize 63
2506 22:15:43.065998 [CA 4] Center 34 (4~65) winsize 62
2507 22:15:43.070036 [CA 5] Center 33 (3~63) winsize 61
2508 22:15:43.070660
2509 22:15:43.072555 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2510 22:15:43.073132
2511 22:15:43.075726 [CATrainingPosCal] consider 1 rank data
2512 22:15:43.079253 u2DelayCellTimex100 = 270/100 ps
2513 22:15:43.082526 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2514 22:15:43.089648 CA1 delay=38 (7~69),Diff = 5 PI (24 cell)
2515 22:15:43.092132 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2516 22:15:43.095588 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2517 22:15:43.099121 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2518 22:15:43.102048 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2519 22:15:43.102871
2520 22:15:43.105412 CA PerBit enable=1, Macro0, CA PI delay=33
2521 22:15:43.105996
2522 22:15:43.108897 [CBTSetCACLKResult] CA Dly = 33
2523 22:15:43.112434 CS Dly: 6 (0~37)
2524 22:15:43.112928 ==
2525 22:15:43.115784 Dram Type= 6, Freq= 0, CH_0, rank 1
2526 22:15:43.118502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2527 22:15:43.119003 ==
2528 22:15:43.125378 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2529 22:15:43.128650 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2530 22:15:43.138573 [CA 0] Center 39 (8~70) winsize 63
2531 22:15:43.142107 [CA 1] Center 38 (8~69) winsize 62
2532 22:15:43.145539 [CA 2] Center 35 (5~66) winsize 62
2533 22:15:43.148244 [CA 3] Center 35 (5~66) winsize 62
2534 22:15:43.151700 [CA 4] Center 34 (4~65) winsize 62
2535 22:15:43.155106 [CA 5] Center 34 (4~64) winsize 61
2536 22:15:43.155682
2537 22:15:43.158419 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2538 22:15:43.158995
2539 22:15:43.162282 [CATrainingPosCal] consider 2 rank data
2540 22:15:43.165340 u2DelayCellTimex100 = 270/100 ps
2541 22:15:43.168540 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2542 22:15:43.171848 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2543 22:15:43.178904 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2544 22:15:43.181292 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2545 22:15:43.185079 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2546 22:15:43.188654 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2547 22:15:43.189230
2548 22:15:43.191492 CA PerBit enable=1, Macro0, CA PI delay=33
2549 22:15:43.191967
2550 22:15:43.195102 [CBTSetCACLKResult] CA Dly = 33
2551 22:15:43.195895 CS Dly: 7 (0~39)
2552 22:15:43.197850
2553 22:15:43.201150 ----->DramcWriteLeveling(PI) begin...
2554 22:15:43.201749 ==
2555 22:15:43.204441 Dram Type= 6, Freq= 0, CH_0, rank 0
2556 22:15:43.208289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2557 22:15:43.208766 ==
2558 22:15:43.210941 Write leveling (Byte 0): 36 => 36
2559 22:15:43.214821 Write leveling (Byte 1): 32 => 32
2560 22:15:43.218252 DramcWriteLeveling(PI) end<-----
2561 22:15:43.218866
2562 22:15:43.219238 ==
2563 22:15:43.221224 Dram Type= 6, Freq= 0, CH_0, rank 0
2564 22:15:43.225648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2565 22:15:43.226224 ==
2566 22:15:43.227903 [Gating] SW mode calibration
2567 22:15:43.234177 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2568 22:15:43.241317 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2569 22:15:43.244694 0 15 0 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
2570 22:15:43.247914 0 15 4 | B1->B0 | 2e2e 3434 | 1 1 | (1 1) (1 1)
2571 22:15:43.254420 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2572 22:15:43.258211 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2573 22:15:43.261239 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2574 22:15:43.267540 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2575 22:15:43.271137 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
2576 22:15:43.274632 0 15 28 | B1->B0 | 3434 2323 | 1 1 | (1 1) (1 0)
2577 22:15:43.280836 1 0 0 | B1->B0 | 2d2d 2323 | 1 0 | (1 0) (0 0)
2578 22:15:43.284270 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2579 22:15:43.287547 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2580 22:15:43.294916 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2581 22:15:43.297653 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2582 22:15:43.300407 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2583 22:15:43.307461 1 0 24 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
2584 22:15:43.310315 1 0 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
2585 22:15:43.313887 1 1 0 | B1->B0 | 3030 4646 | 0 0 | (0 0) (0 0)
2586 22:15:43.320563 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2587 22:15:43.323921 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2588 22:15:43.327074 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2589 22:15:43.334122 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2590 22:15:43.337190 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2591 22:15:43.340544 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2592 22:15:43.343672 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2593 22:15:43.350540 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2594 22:15:43.354308 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2595 22:15:43.357410 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2596 22:15:43.363386 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2597 22:15:43.367011 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2598 22:15:43.370339 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2599 22:15:43.377003 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2600 22:15:43.380403 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2601 22:15:43.383584 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2602 22:15:43.390734 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2603 22:15:43.393969 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2604 22:15:43.396522 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2605 22:15:43.403338 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2606 22:15:43.406608 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2607 22:15:43.409753 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2608 22:15:43.416265 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2609 22:15:43.420264 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2610 22:15:43.423572 Total UI for P1: 0, mck2ui 16
2611 22:15:43.426333 best dqsien dly found for B0: ( 1, 3, 28)
2612 22:15:43.429824 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2613 22:15:43.433345 Total UI for P1: 0, mck2ui 16
2614 22:15:43.436663 best dqsien dly found for B1: ( 1, 4, 0)
2615 22:15:43.439374 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2616 22:15:43.443192 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2617 22:15:43.443763
2618 22:15:43.449781 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2619 22:15:43.452937 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2620 22:15:43.456273 [Gating] SW calibration Done
2621 22:15:43.456847 ==
2622 22:15:43.459147 Dram Type= 6, Freq= 0, CH_0, rank 0
2623 22:15:43.462680 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2624 22:15:43.463156 ==
2625 22:15:43.463529 RX Vref Scan: 0
2626 22:15:43.463875
2627 22:15:43.466423 RX Vref 0 -> 0, step: 1
2628 22:15:43.466993
2629 22:15:43.469685 RX Delay -40 -> 252, step: 8
2630 22:15:43.472675 iDelay=208, Bit 0, Center 123 (56 ~ 191) 136
2631 22:15:43.475943 iDelay=208, Bit 1, Center 127 (56 ~ 199) 144
2632 22:15:43.482459 iDelay=208, Bit 2, Center 119 (48 ~ 191) 144
2633 22:15:43.485944 iDelay=208, Bit 3, Center 119 (48 ~ 191) 144
2634 22:15:43.489042 iDelay=208, Bit 4, Center 127 (56 ~ 199) 144
2635 22:15:43.492366 iDelay=208, Bit 5, Center 115 (48 ~ 183) 136
2636 22:15:43.495917 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
2637 22:15:43.502336 iDelay=208, Bit 7, Center 127 (56 ~ 199) 144
2638 22:15:43.505728 iDelay=208, Bit 8, Center 99 (32 ~ 167) 136
2639 22:15:43.508830 iDelay=208, Bit 9, Center 99 (32 ~ 167) 136
2640 22:15:43.512334 iDelay=208, Bit 10, Center 107 (40 ~ 175) 136
2641 22:15:43.516297 iDelay=208, Bit 11, Center 107 (40 ~ 175) 136
2642 22:15:43.522314 iDelay=208, Bit 12, Center 115 (48 ~ 183) 136
2643 22:15:43.525760 iDelay=208, Bit 13, Center 115 (48 ~ 183) 136
2644 22:15:43.528783 iDelay=208, Bit 14, Center 123 (56 ~ 191) 136
2645 22:15:43.531767 iDelay=208, Bit 15, Center 115 (48 ~ 183) 136
2646 22:15:43.532243 ==
2647 22:15:43.535140 Dram Type= 6, Freq= 0, CH_0, rank 0
2648 22:15:43.542143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2649 22:15:43.542825 ==
2650 22:15:43.543206 DQS Delay:
2651 22:15:43.545372 DQS0 = 0, DQS1 = 0
2652 22:15:43.545843 DQM Delay:
2653 22:15:43.546261 DQM0 = 123, DQM1 = 110
2654 22:15:43.548791 DQ Delay:
2655 22:15:43.552171 DQ0 =123, DQ1 =127, DQ2 =119, DQ3 =119
2656 22:15:43.555272 DQ4 =127, DQ5 =115, DQ6 =131, DQ7 =127
2657 22:15:43.558420 DQ8 =99, DQ9 =99, DQ10 =107, DQ11 =107
2658 22:15:43.561828 DQ12 =115, DQ13 =115, DQ14 =123, DQ15 =115
2659 22:15:43.562330
2660 22:15:43.562880
2661 22:15:43.563306 ==
2662 22:15:43.565361 Dram Type= 6, Freq= 0, CH_0, rank 0
2663 22:15:43.568807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2664 22:15:43.572081 ==
2665 22:15:43.572649
2666 22:15:43.573023
2667 22:15:43.573364 TX Vref Scan disable
2668 22:15:43.575250 == TX Byte 0 ==
2669 22:15:43.578859 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2670 22:15:43.581919 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2671 22:15:43.585493 == TX Byte 1 ==
2672 22:15:43.588661 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2673 22:15:43.591438 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2674 22:15:43.595119 ==
2675 22:15:43.598503 Dram Type= 6, Freq= 0, CH_0, rank 0
2676 22:15:43.601625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2677 22:15:43.602194 ==
2678 22:15:43.612673 TX Vref=22, minBit 4, minWin=24, winSum=406
2679 22:15:43.617140 TX Vref=24, minBit 0, minWin=24, winSum=409
2680 22:15:43.619602 TX Vref=26, minBit 2, minWin=25, winSum=417
2681 22:15:43.623294 TX Vref=28, minBit 4, minWin=25, winSum=422
2682 22:15:43.627014 TX Vref=30, minBit 0, minWin=26, winSum=423
2683 22:15:43.629374 TX Vref=32, minBit 3, minWin=25, winSum=416
2684 22:15:43.636451 [TxChooseVref] Worse bit 0, Min win 26, Win sum 423, Final Vref 30
2685 22:15:43.637019
2686 22:15:43.639288 Final TX Range 1 Vref 30
2687 22:15:43.639762
2688 22:15:43.640133 ==
2689 22:15:43.642565 Dram Type= 6, Freq= 0, CH_0, rank 0
2690 22:15:43.646286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2691 22:15:43.646931 ==
2692 22:15:43.647434
2693 22:15:43.649525
2694 22:15:43.650092 TX Vref Scan disable
2695 22:15:43.652739 == TX Byte 0 ==
2696 22:15:43.655928 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2697 22:15:43.659795 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2698 22:15:43.662601 == TX Byte 1 ==
2699 22:15:43.666093 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2700 22:15:43.669447 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2701 22:15:43.669926
2702 22:15:43.673115 [DATLAT]
2703 22:15:43.673815 Freq=1200, CH0 RK0
2704 22:15:43.674200
2705 22:15:43.676186 DATLAT Default: 0xd
2706 22:15:43.676755 0, 0xFFFF, sum = 0
2707 22:15:43.679529 1, 0xFFFF, sum = 0
2708 22:15:43.680105 2, 0xFFFF, sum = 0
2709 22:15:43.683004 3, 0xFFFF, sum = 0
2710 22:15:43.683582 4, 0xFFFF, sum = 0
2711 22:15:43.686040 5, 0xFFFF, sum = 0
2712 22:15:43.689888 6, 0xFFFF, sum = 0
2713 22:15:43.690406 7, 0xFFFF, sum = 0
2714 22:15:43.692885 8, 0xFFFF, sum = 0
2715 22:15:43.693366 9, 0xFFFF, sum = 0
2716 22:15:43.695870 10, 0xFFFF, sum = 0
2717 22:15:43.696353 11, 0xFFFF, sum = 0
2718 22:15:43.699374 12, 0x0, sum = 1
2719 22:15:43.699878 13, 0x0, sum = 2
2720 22:15:43.702808 14, 0x0, sum = 3
2721 22:15:43.703288 15, 0x0, sum = 4
2722 22:15:43.703665 best_step = 13
2723 22:15:43.704011
2724 22:15:43.706008 ==
2725 22:15:43.709297 Dram Type= 6, Freq= 0, CH_0, rank 0
2726 22:15:43.713100 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2727 22:15:43.713671 ==
2728 22:15:43.714050 RX Vref Scan: 1
2729 22:15:43.714442
2730 22:15:43.716034 Set Vref Range= 32 -> 127
2731 22:15:43.716607
2732 22:15:43.719569 RX Vref 32 -> 127, step: 1
2733 22:15:43.720139
2734 22:15:43.722527 RX Delay -13 -> 252, step: 4
2735 22:15:43.723003
2736 22:15:43.726266 Set Vref, RX VrefLevel [Byte0]: 32
2737 22:15:43.729540 [Byte1]: 32
2738 22:15:43.730107
2739 22:15:43.732897 Set Vref, RX VrefLevel [Byte0]: 33
2740 22:15:43.735838 [Byte1]: 33
2741 22:15:43.736317
2742 22:15:43.738889 Set Vref, RX VrefLevel [Byte0]: 34
2743 22:15:43.742592 [Byte1]: 34
2744 22:15:43.746701
2745 22:15:43.747178 Set Vref, RX VrefLevel [Byte0]: 35
2746 22:15:43.750135 [Byte1]: 35
2747 22:15:43.754780
2748 22:15:43.755347 Set Vref, RX VrefLevel [Byte0]: 36
2749 22:15:43.758123 [Byte1]: 36
2750 22:15:43.762940
2751 22:15:43.763511 Set Vref, RX VrefLevel [Byte0]: 37
2752 22:15:43.765759 [Byte1]: 37
2753 22:15:43.770571
2754 22:15:43.771136 Set Vref, RX VrefLevel [Byte0]: 38
2755 22:15:43.773715 [Byte1]: 38
2756 22:15:43.778767
2757 22:15:43.779334 Set Vref, RX VrefLevel [Byte0]: 39
2758 22:15:43.781761 [Byte1]: 39
2759 22:15:43.786628
2760 22:15:43.787197 Set Vref, RX VrefLevel [Byte0]: 40
2761 22:15:43.790101 [Byte1]: 40
2762 22:15:43.794299
2763 22:15:43.794803 Set Vref, RX VrefLevel [Byte0]: 41
2764 22:15:43.797428 [Byte1]: 41
2765 22:15:43.802196
2766 22:15:43.802822 Set Vref, RX VrefLevel [Byte0]: 42
2767 22:15:43.805847 [Byte1]: 42
2768 22:15:43.809917
2769 22:15:43.810510 Set Vref, RX VrefLevel [Byte0]: 43
2770 22:15:43.813320 [Byte1]: 43
2771 22:15:43.818073
2772 22:15:43.818709 Set Vref, RX VrefLevel [Byte0]: 44
2773 22:15:43.822094 [Byte1]: 44
2774 22:15:43.825815
2775 22:15:43.826422 Set Vref, RX VrefLevel [Byte0]: 45
2776 22:15:43.829458 [Byte1]: 45
2777 22:15:43.833817
2778 22:15:43.834423 Set Vref, RX VrefLevel [Byte0]: 46
2779 22:15:43.837043 [Byte1]: 46
2780 22:15:43.842013
2781 22:15:43.842620 Set Vref, RX VrefLevel [Byte0]: 47
2782 22:15:43.844851 [Byte1]: 47
2783 22:15:43.849331
2784 22:15:43.849803 Set Vref, RX VrefLevel [Byte0]: 48
2785 22:15:43.853631 [Byte1]: 48
2786 22:15:43.857196
2787 22:15:43.857702 Set Vref, RX VrefLevel [Byte0]: 49
2788 22:15:43.861724 [Byte1]: 49
2789 22:15:43.864869
2790 22:15:43.865346 Set Vref, RX VrefLevel [Byte0]: 50
2791 22:15:43.868748 [Byte1]: 50
2792 22:15:43.873180
2793 22:15:43.873754 Set Vref, RX VrefLevel [Byte0]: 51
2794 22:15:43.876697 [Byte1]: 51
2795 22:15:43.881144
2796 22:15:43.881715 Set Vref, RX VrefLevel [Byte0]: 52
2797 22:15:43.884347 [Byte1]: 52
2798 22:15:43.888877
2799 22:15:43.889454 Set Vref, RX VrefLevel [Byte0]: 53
2800 22:15:43.891953 [Byte1]: 53
2801 22:15:43.896696
2802 22:15:43.897257 Set Vref, RX VrefLevel [Byte0]: 54
2803 22:15:43.899909 [Byte1]: 54
2804 22:15:43.904938
2805 22:15:43.905500 Set Vref, RX VrefLevel [Byte0]: 55
2806 22:15:43.907743 [Byte1]: 55
2807 22:15:43.913273
2808 22:15:43.913989 Set Vref, RX VrefLevel [Byte0]: 56
2809 22:15:43.915705 [Byte1]: 56
2810 22:15:43.920406
2811 22:15:43.920966 Set Vref, RX VrefLevel [Byte0]: 57
2812 22:15:43.923848 [Byte1]: 57
2813 22:15:43.928463
2814 22:15:43.929024 Set Vref, RX VrefLevel [Byte0]: 58
2815 22:15:43.931807 [Byte1]: 58
2816 22:15:43.936217
2817 22:15:43.936780 Set Vref, RX VrefLevel [Byte0]: 59
2818 22:15:43.939975 [Byte1]: 59
2819 22:15:43.944289
2820 22:15:43.944850 Set Vref, RX VrefLevel [Byte0]: 60
2821 22:15:43.947490 [Byte1]: 60
2822 22:15:43.952006
2823 22:15:43.952566 Set Vref, RX VrefLevel [Byte0]: 61
2824 22:15:43.955642 [Byte1]: 61
2825 22:15:43.960166
2826 22:15:43.960730 Set Vref, RX VrefLevel [Byte0]: 62
2827 22:15:43.962940 [Byte1]: 62
2828 22:15:43.967959
2829 22:15:43.968544 Set Vref, RX VrefLevel [Byte0]: 63
2830 22:15:43.971052 [Byte1]: 63
2831 22:15:43.975674
2832 22:15:43.976255 Set Vref, RX VrefLevel [Byte0]: 64
2833 22:15:43.978924 [Byte1]: 64
2834 22:15:43.983487
2835 22:15:43.984092 Set Vref, RX VrefLevel [Byte0]: 65
2836 22:15:43.987235 [Byte1]: 65
2837 22:15:43.991593
2838 22:15:43.992061 Set Vref, RX VrefLevel [Byte0]: 66
2839 22:15:43.994981 [Byte1]: 66
2840 22:15:43.999216
2841 22:15:43.999777 Set Vref, RX VrefLevel [Byte0]: 67
2842 22:15:44.002831 [Byte1]: 67
2843 22:15:44.007502
2844 22:15:44.008081 Set Vref, RX VrefLevel [Byte0]: 68
2845 22:15:44.010227 [Byte1]: 68
2846 22:15:44.015252
2847 22:15:44.015824 Set Vref, RX VrefLevel [Byte0]: 69
2848 22:15:44.018394 [Byte1]: 69
2849 22:15:44.023166
2850 22:15:44.023735 Set Vref, RX VrefLevel [Byte0]: 70
2851 22:15:44.026295 [Byte1]: 70
2852 22:15:44.030967
2853 22:15:44.031534 Final RX Vref Byte 0 = 57 to rank0
2854 22:15:44.034466 Final RX Vref Byte 1 = 50 to rank0
2855 22:15:44.037698 Final RX Vref Byte 0 = 57 to rank1
2856 22:15:44.041045 Final RX Vref Byte 1 = 50 to rank1==
2857 22:15:44.044381 Dram Type= 6, Freq= 0, CH_0, rank 0
2858 22:15:44.051245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2859 22:15:44.051822 ==
2860 22:15:44.052201 DQS Delay:
2861 22:15:44.052547 DQS0 = 0, DQS1 = 0
2862 22:15:44.054133 DQM Delay:
2863 22:15:44.054746 DQM0 = 122, DQM1 = 109
2864 22:15:44.057519 DQ Delay:
2865 22:15:44.061637 DQ0 =122, DQ1 =122, DQ2 =118, DQ3 =120
2866 22:15:44.064453 DQ4 =124, DQ5 =116, DQ6 =130, DQ7 =130
2867 22:15:44.068027 DQ8 =100, DQ9 =94, DQ10 =110, DQ11 =108
2868 22:15:44.071133 DQ12 =116, DQ13 =110, DQ14 =122, DQ15 =116
2869 22:15:44.071804
2870 22:15:44.072182
2871 22:15:44.077718 [DQSOSCAuto] RK0, (LSB)MR18= 0x603, (MSB)MR19= 0x404, tDQSOscB0 = 408 ps tDQSOscB1 = 407 ps
2872 22:15:44.080745 CH0 RK0: MR19=404, MR18=603
2873 22:15:44.087393 CH0_RK0: MR19=0x404, MR18=0x603, DQSOSC=407, MR23=63, INC=39, DEC=26
2874 22:15:44.087963
2875 22:15:44.091156 ----->DramcWriteLeveling(PI) begin...
2876 22:15:44.091730 ==
2877 22:15:44.094480 Dram Type= 6, Freq= 0, CH_0, rank 1
2878 22:15:44.098055 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2879 22:15:44.101054 ==
2880 22:15:44.101525 Write leveling (Byte 0): 37 => 37
2881 22:15:44.104143 Write leveling (Byte 1): 32 => 32
2882 22:15:44.107249 DramcWriteLeveling(PI) end<-----
2883 22:15:44.107819
2884 22:15:44.108192 ==
2885 22:15:44.110998 Dram Type= 6, Freq= 0, CH_0, rank 1
2886 22:15:44.117645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2887 22:15:44.118214 ==
2888 22:15:44.120932 [Gating] SW mode calibration
2889 22:15:44.126904 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2890 22:15:44.130697 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2891 22:15:44.137055 0 15 0 | B1->B0 | 3332 3434 | 1 1 | (1 1) (1 1)
2892 22:15:44.140684 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2893 22:15:44.144313 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2894 22:15:44.150687 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2895 22:15:44.153659 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2896 22:15:44.157739 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2897 22:15:44.160522 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2898 22:15:44.167192 0 15 28 | B1->B0 | 3333 2d2d | 0 0 | (1 0) (1 0)
2899 22:15:44.170113 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2900 22:15:44.173683 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2901 22:15:44.180405 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2902 22:15:44.183659 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2903 22:15:44.186664 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2904 22:15:44.193134 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2905 22:15:44.197995 1 0 24 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
2906 22:15:44.199849 1 0 28 | B1->B0 | 3939 4343 | 0 1 | (0 0) (0 0)
2907 22:15:44.206485 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2908 22:15:44.210028 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2909 22:15:44.213113 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2910 22:15:44.220220 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2911 22:15:44.223156 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2912 22:15:44.226481 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2913 22:15:44.233118 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2914 22:15:44.236678 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2915 22:15:44.239658 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
2916 22:15:44.246491 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2917 22:15:44.249830 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2918 22:15:44.253738 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2919 22:15:44.260057 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2920 22:15:44.263082 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2921 22:15:44.267081 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2922 22:15:44.273040 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2923 22:15:44.276344 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2924 22:15:44.279528 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2925 22:15:44.286157 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2926 22:15:44.289368 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2927 22:15:44.292726 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2928 22:15:44.299463 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2929 22:15:44.302973 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2930 22:15:44.305915 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2931 22:15:44.312989 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
2932 22:15:44.313559 Total UI for P1: 0, mck2ui 16
2933 22:15:44.319117 best dqsien dly found for B1: ( 1, 3, 30)
2934 22:15:44.322425 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2935 22:15:44.325788 Total UI for P1: 0, mck2ui 16
2936 22:15:44.329677 best dqsien dly found for B0: ( 1, 3, 30)
2937 22:15:44.332418 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2938 22:15:44.336375 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2939 22:15:44.336949
2940 22:15:44.338973 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2941 22:15:44.342570 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2942 22:15:44.345855 [Gating] SW calibration Done
2943 22:15:44.346465 ==
2944 22:15:44.349641 Dram Type= 6, Freq= 0, CH_0, rank 1
2945 22:15:44.352433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2946 22:15:44.356201 ==
2947 22:15:44.356771 RX Vref Scan: 0
2948 22:15:44.357142
2949 22:15:44.358976 RX Vref 0 -> 0, step: 1
2950 22:15:44.359442
2951 22:15:44.359810 RX Delay -40 -> 252, step: 8
2952 22:15:44.365953 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2953 22:15:44.369193 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2954 22:15:44.372845 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2955 22:15:44.375808 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2956 22:15:44.379233 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2957 22:15:44.385727 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2958 22:15:44.389400 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2959 22:15:44.392312 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2960 22:15:44.395554 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2961 22:15:44.398707 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2962 22:15:44.405383 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2963 22:15:44.408431 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2964 22:15:44.411500 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2965 22:15:44.415249 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2966 22:15:44.421645 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2967 22:15:44.425303 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2968 22:15:44.425771 ==
2969 22:15:44.428486 Dram Type= 6, Freq= 0, CH_0, rank 1
2970 22:15:44.432135 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2971 22:15:44.432704 ==
2972 22:15:44.434719 DQS Delay:
2973 22:15:44.435188 DQS0 = 0, DQS1 = 0
2974 22:15:44.435556 DQM Delay:
2975 22:15:44.438281 DQM0 = 120, DQM1 = 108
2976 22:15:44.438911 DQ Delay:
2977 22:15:44.441652 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
2978 22:15:44.445164 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2979 22:15:44.448781 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
2980 22:15:44.455700 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115
2981 22:15:44.456262
2982 22:15:44.456628
2983 22:15:44.456969 ==
2984 22:15:44.458091 Dram Type= 6, Freq= 0, CH_0, rank 1
2985 22:15:44.461503 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2986 22:15:44.462067 ==
2987 22:15:44.462483
2988 22:15:44.462832
2989 22:15:44.464967 TX Vref Scan disable
2990 22:15:44.465527 == TX Byte 0 ==
2991 22:15:44.472360 Update DQ dly =855 (3 ,2, 23) DQ OEN =(2 ,7)
2992 22:15:44.475415 Update DQM dly =855 (3 ,2, 23) DQM OEN =(2 ,7)
2993 22:15:44.475982 == TX Byte 1 ==
2994 22:15:44.481814 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2995 22:15:44.484980 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2996 22:15:44.485545 ==
2997 22:15:44.488226 Dram Type= 6, Freq= 0, CH_0, rank 1
2998 22:15:44.491309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2999 22:15:44.491877 ==
3000 22:15:44.504768 TX Vref=22, minBit 0, minWin=26, winSum=419
3001 22:15:44.508284 TX Vref=24, minBit 0, minWin=26, winSum=421
3002 22:15:44.510991 TX Vref=26, minBit 12, minWin=25, winSum=422
3003 22:15:44.514492 TX Vref=28, minBit 13, minWin=25, winSum=426
3004 22:15:44.517766 TX Vref=30, minBit 8, minWin=26, winSum=431
3005 22:15:44.524735 TX Vref=32, minBit 8, minWin=26, winSum=430
3006 22:15:44.527853 [TxChooseVref] Worse bit 8, Min win 26, Win sum 431, Final Vref 30
3007 22:15:44.528330
3008 22:15:44.531018 Final TX Range 1 Vref 30
3009 22:15:44.531490
3010 22:15:44.531856 ==
3011 22:15:44.534159 Dram Type= 6, Freq= 0, CH_0, rank 1
3012 22:15:44.537893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3013 22:15:44.540771 ==
3014 22:15:44.541247
3015 22:15:44.541622
3016 22:15:44.541965 TX Vref Scan disable
3017 22:15:44.544460 == TX Byte 0 ==
3018 22:15:44.548552 Update DQ dly =855 (3 ,2, 23) DQ OEN =(2 ,7)
3019 22:15:44.554972 Update DQM dly =855 (3 ,2, 23) DQM OEN =(2 ,7)
3020 22:15:44.555557 == TX Byte 1 ==
3021 22:15:44.557739 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
3022 22:15:44.564951 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
3023 22:15:44.565536
3024 22:15:44.565913 [DATLAT]
3025 22:15:44.566266 Freq=1200, CH0 RK1
3026 22:15:44.566641
3027 22:15:44.567540 DATLAT Default: 0xd
3028 22:15:44.568010 0, 0xFFFF, sum = 0
3029 22:15:44.571656 1, 0xFFFF, sum = 0
3030 22:15:44.574347 2, 0xFFFF, sum = 0
3031 22:15:44.574968 3, 0xFFFF, sum = 0
3032 22:15:44.577831 4, 0xFFFF, sum = 0
3033 22:15:44.578453 5, 0xFFFF, sum = 0
3034 22:15:44.581131 6, 0xFFFF, sum = 0
3035 22:15:44.581717 7, 0xFFFF, sum = 0
3036 22:15:44.584368 8, 0xFFFF, sum = 0
3037 22:15:44.584980 9, 0xFFFF, sum = 0
3038 22:15:44.587875 10, 0xFFFF, sum = 0
3039 22:15:44.588465 11, 0xFFFF, sum = 0
3040 22:15:44.590623 12, 0x0, sum = 1
3041 22:15:44.591290 13, 0x0, sum = 2
3042 22:15:44.593816 14, 0x0, sum = 3
3043 22:15:44.594405 15, 0x0, sum = 4
3044 22:15:44.597516 best_step = 13
3045 22:15:44.598099
3046 22:15:44.598509 ==
3047 22:15:44.600879 Dram Type= 6, Freq= 0, CH_0, rank 1
3048 22:15:44.603755 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3049 22:15:44.604236 ==
3050 22:15:44.604613 RX Vref Scan: 0
3051 22:15:44.607709
3052 22:15:44.608184 RX Vref 0 -> 0, step: 1
3053 22:15:44.608559
3054 22:15:44.610540 RX Delay -21 -> 252, step: 4
3055 22:15:44.617313 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3056 22:15:44.620675 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3057 22:15:44.623848 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3058 22:15:44.627161 iDelay=195, Bit 3, Center 114 (51 ~ 178) 128
3059 22:15:44.630903 iDelay=195, Bit 4, Center 120 (55 ~ 186) 132
3060 22:15:44.634034 iDelay=195, Bit 5, Center 114 (51 ~ 178) 128
3061 22:15:44.641200 iDelay=195, Bit 6, Center 124 (55 ~ 194) 140
3062 22:15:44.644263 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3063 22:15:44.647539 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3064 22:15:44.650286 iDelay=195, Bit 9, Center 94 (31 ~ 158) 128
3065 22:15:44.654102 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3066 22:15:44.660679 iDelay=195, Bit 11, Center 104 (43 ~ 166) 124
3067 22:15:44.664190 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3068 22:15:44.667554 iDelay=195, Bit 13, Center 110 (47 ~ 174) 128
3069 22:15:44.671075 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3070 22:15:44.677360 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3071 22:15:44.677924 ==
3072 22:15:44.680935 Dram Type= 6, Freq= 0, CH_0, rank 1
3073 22:15:44.684120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3074 22:15:44.684683 ==
3075 22:15:44.685056 DQS Delay:
3076 22:15:44.687493 DQS0 = 0, DQS1 = 0
3077 22:15:44.688058 DQM Delay:
3078 22:15:44.690745 DQM0 = 119, DQM1 = 107
3079 22:15:44.691314 DQ Delay:
3080 22:15:44.694219 DQ0 =118, DQ1 =122, DQ2 =118, DQ3 =114
3081 22:15:44.697269 DQ4 =120, DQ5 =114, DQ6 =124, DQ7 =126
3082 22:15:44.700564 DQ8 =98, DQ9 =94, DQ10 =110, DQ11 =104
3083 22:15:44.704365 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114
3084 22:15:44.704931
3085 22:15:44.705298
3086 22:15:44.714263 [DQSOSCAuto] RK1, (LSB)MR18= 0x10f7, (MSB)MR19= 0x403, tDQSOscB0 = 413 ps tDQSOscB1 = 403 ps
3087 22:15:44.717045 CH0 RK1: MR19=403, MR18=10F7
3088 22:15:44.720387 CH0_RK1: MR19=0x403, MR18=0x10F7, DQSOSC=403, MR23=63, INC=40, DEC=26
3089 22:15:44.723783 [RxdqsGatingPostProcess] freq 1200
3090 22:15:44.730123 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3091 22:15:44.733604 best DQS0 dly(2T, 0.5T) = (0, 11)
3092 22:15:44.737389 best DQS1 dly(2T, 0.5T) = (0, 12)
3093 22:15:44.740546 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3094 22:15:44.743762 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3095 22:15:44.747491 best DQS0 dly(2T, 0.5T) = (0, 11)
3096 22:15:44.749823 best DQS1 dly(2T, 0.5T) = (0, 11)
3097 22:15:44.753537 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3098 22:15:44.756907 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3099 22:15:44.760288 Pre-setting of DQS Precalculation
3100 22:15:44.763389 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3101 22:15:44.763859 ==
3102 22:15:44.767153 Dram Type= 6, Freq= 0, CH_1, rank 0
3103 22:15:44.770538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3104 22:15:44.771112 ==
3105 22:15:44.776888 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3106 22:15:44.783814 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3107 22:15:44.791246 [CA 0] Center 37 (7~68) winsize 62
3108 22:15:44.794465 [CA 1] Center 37 (7~68) winsize 62
3109 22:15:44.797559 [CA 2] Center 35 (5~65) winsize 61
3110 22:15:44.800847 [CA 3] Center 34 (4~65) winsize 62
3111 22:15:44.804270 [CA 4] Center 34 (4~64) winsize 61
3112 22:15:44.807837 [CA 5] Center 33 (3~64) winsize 62
3113 22:15:44.808408
3114 22:15:44.811299 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3115 22:15:44.811777
3116 22:15:44.814516 [CATrainingPosCal] consider 1 rank data
3117 22:15:44.817444 u2DelayCellTimex100 = 270/100 ps
3118 22:15:44.821018 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3119 22:15:44.824215 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3120 22:15:44.830763 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3121 22:15:44.834399 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3122 22:15:44.837599 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3123 22:15:44.840759 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3124 22:15:44.841399
3125 22:15:44.843957 CA PerBit enable=1, Macro0, CA PI delay=33
3126 22:15:44.844528
3127 22:15:44.847130 [CBTSetCACLKResult] CA Dly = 33
3128 22:15:44.847601 CS Dly: 5 (0~36)
3129 22:15:44.850472 ==
3130 22:15:44.853912 Dram Type= 6, Freq= 0, CH_1, rank 1
3131 22:15:44.857311 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3132 22:15:44.857886 ==
3133 22:15:44.861071 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3134 22:15:44.867082 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3135 22:15:44.876781 [CA 0] Center 38 (8~68) winsize 61
3136 22:15:44.879968 [CA 1] Center 38 (7~69) winsize 63
3137 22:15:44.883271 [CA 2] Center 35 (5~66) winsize 62
3138 22:15:44.886567 [CA 3] Center 35 (5~65) winsize 61
3139 22:15:44.890223 [CA 4] Center 34 (4~65) winsize 62
3140 22:15:44.893274 [CA 5] Center 34 (4~64) winsize 61
3141 22:15:44.893843
3142 22:15:44.896935 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3143 22:15:44.897507
3144 22:15:44.900074 [CATrainingPosCal] consider 2 rank data
3145 22:15:44.903235 u2DelayCellTimex100 = 270/100 ps
3146 22:15:44.906093 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3147 22:15:44.912985 CA1 delay=37 (7~68),Diff = 3 PI (14 cell)
3148 22:15:44.916259 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3149 22:15:44.919602 CA3 delay=35 (5~65),Diff = 1 PI (4 cell)
3150 22:15:44.922946 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
3151 22:15:44.926313 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3152 22:15:44.926937
3153 22:15:44.929604 CA PerBit enable=1, Macro0, CA PI delay=34
3154 22:15:44.930181
3155 22:15:44.933075 [CBTSetCACLKResult] CA Dly = 34
3156 22:15:44.936137 CS Dly: 6 (0~39)
3157 22:15:44.936718
3158 22:15:44.939313 ----->DramcWriteLeveling(PI) begin...
3159 22:15:44.939791 ==
3160 22:15:44.942616 Dram Type= 6, Freq= 0, CH_1, rank 0
3161 22:15:44.946401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3162 22:15:44.947000 ==
3163 22:15:44.949636 Write leveling (Byte 0): 25 => 25
3164 22:15:44.952744 Write leveling (Byte 1): 27 => 27
3165 22:15:44.956455 DramcWriteLeveling(PI) end<-----
3166 22:15:44.957043
3167 22:15:44.957421 ==
3168 22:15:44.959494 Dram Type= 6, Freq= 0, CH_1, rank 0
3169 22:15:44.962556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3170 22:15:44.963035 ==
3171 22:15:44.966102 [Gating] SW mode calibration
3172 22:15:44.972733 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3173 22:15:44.979461 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3174 22:15:44.983296 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3175 22:15:44.986146 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3176 22:15:44.992760 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3177 22:15:44.995665 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3178 22:15:44.999539 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3179 22:15:45.005839 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3180 22:15:45.009352 0 15 24 | B1->B0 | 2929 2323 | 1 0 | (1 0) (1 0)
3181 22:15:45.013073 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3182 22:15:45.019160 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3183 22:15:45.022900 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3184 22:15:45.026761 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3185 22:15:45.032307 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3186 22:15:45.035919 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3187 22:15:45.039096 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3188 22:15:45.042315 1 0 24 | B1->B0 | 3a3a 4242 | 0 0 | (0 0) (0 0)
3189 22:15:45.049123 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3190 22:15:45.052411 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3191 22:15:45.055853 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3192 22:15:45.062695 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3193 22:15:45.066047 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3194 22:15:45.068900 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3195 22:15:45.076444 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3196 22:15:45.078998 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3197 22:15:45.082869 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3198 22:15:45.089506 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3199 22:15:45.092295 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3200 22:15:45.095897 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3201 22:15:45.102795 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3202 22:15:45.105741 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3203 22:15:45.109093 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3204 22:15:45.115874 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3205 22:15:45.119259 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3206 22:15:45.122000 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3207 22:15:45.129558 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3208 22:15:45.132288 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3209 22:15:45.135773 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3210 22:15:45.142507 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3211 22:15:45.145778 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3212 22:15:45.149028 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3213 22:15:45.152775 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3214 22:15:45.155453 Total UI for P1: 0, mck2ui 16
3215 22:15:45.158993 best dqsien dly found for B0: ( 1, 3, 22)
3216 22:15:45.165213 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3217 22:15:45.168818 Total UI for P1: 0, mck2ui 16
3218 22:15:45.172103 best dqsien dly found for B1: ( 1, 3, 26)
3219 22:15:45.176307 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3220 22:15:45.179160 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3221 22:15:45.179819
3222 22:15:45.182657 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3223 22:15:45.185463 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3224 22:15:45.188805 [Gating] SW calibration Done
3225 22:15:45.189372 ==
3226 22:15:45.192207 Dram Type= 6, Freq= 0, CH_1, rank 0
3227 22:15:45.195413 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3228 22:15:45.195978 ==
3229 22:15:45.198897 RX Vref Scan: 0
3230 22:15:45.199368
3231 22:15:45.199744 RX Vref 0 -> 0, step: 1
3232 22:15:45.202460
3233 22:15:45.203042 RX Delay -40 -> 252, step: 8
3234 22:15:45.208960 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3235 22:15:45.212104 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3236 22:15:45.215704 iDelay=200, Bit 2, Center 111 (48 ~ 175) 128
3237 22:15:45.219271 iDelay=200, Bit 3, Center 123 (56 ~ 191) 136
3238 22:15:45.222090 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3239 22:15:45.225499 iDelay=200, Bit 5, Center 127 (64 ~ 191) 128
3240 22:15:45.232695 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3241 22:15:45.235640 iDelay=200, Bit 7, Center 119 (56 ~ 183) 128
3242 22:15:45.239049 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3243 22:15:45.242106 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3244 22:15:45.245577 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3245 22:15:45.252010 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3246 22:15:45.255240 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3247 22:15:45.258625 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3248 22:15:45.261788 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3249 22:15:45.268514 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3250 22:15:45.269177 ==
3251 22:15:45.271495 Dram Type= 6, Freq= 0, CH_1, rank 0
3252 22:15:45.274832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3253 22:15:45.275312 ==
3254 22:15:45.275686 DQS Delay:
3255 22:15:45.278513 DQS0 = 0, DQS1 = 0
3256 22:15:45.279088 DQM Delay:
3257 22:15:45.281725 DQM0 = 120, DQM1 = 112
3258 22:15:45.282198 DQ Delay:
3259 22:15:45.285054 DQ0 =123, DQ1 =115, DQ2 =111, DQ3 =123
3260 22:15:45.288164 DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =119
3261 22:15:45.291888 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3262 22:15:45.294947 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3263 22:15:45.295427
3264 22:15:45.295798
3265 22:15:45.298143 ==
3266 22:15:45.298850 Dram Type= 6, Freq= 0, CH_1, rank 0
3267 22:15:45.305129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3268 22:15:45.305719 ==
3269 22:15:45.306096
3270 22:15:45.306473
3271 22:15:45.308100 TX Vref Scan disable
3272 22:15:45.308576 == TX Byte 0 ==
3273 22:15:45.311678 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3274 22:15:45.318692 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3275 22:15:45.319276 == TX Byte 1 ==
3276 22:15:45.322156 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3277 22:15:45.328293 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3278 22:15:45.328872 ==
3279 22:15:45.331787 Dram Type= 6, Freq= 0, CH_1, rank 0
3280 22:15:45.335050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3281 22:15:45.335633 ==
3282 22:15:45.347219 TX Vref=22, minBit 1, minWin=24, winSum=403
3283 22:15:45.349548 TX Vref=24, minBit 11, minWin=24, winSum=408
3284 22:15:45.353281 TX Vref=26, minBit 3, minWin=25, winSum=415
3285 22:15:45.356917 TX Vref=28, minBit 10, minWin=25, winSum=422
3286 22:15:45.359897 TX Vref=30, minBit 10, minWin=25, winSum=422
3287 22:15:45.367052 TX Vref=32, minBit 8, minWin=26, winSum=426
3288 22:15:45.370165 [TxChooseVref] Worse bit 8, Min win 26, Win sum 426, Final Vref 32
3289 22:15:45.370787
3290 22:15:45.373236 Final TX Range 1 Vref 32
3291 22:15:45.373814
3292 22:15:45.374188 ==
3293 22:15:45.376514 Dram Type= 6, Freq= 0, CH_1, rank 0
3294 22:15:45.379797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3295 22:15:45.382816 ==
3296 22:15:45.383392
3297 22:15:45.383782
3298 22:15:45.384133 TX Vref Scan disable
3299 22:15:45.386533 == TX Byte 0 ==
3300 22:15:45.389737 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3301 22:15:45.393386 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3302 22:15:45.396336 == TX Byte 1 ==
3303 22:15:45.399601 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3304 22:15:45.403170 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3305 22:15:45.406825
3306 22:15:45.407576 [DATLAT]
3307 22:15:45.407996 Freq=1200, CH1 RK0
3308 22:15:45.408351
3309 22:15:45.409611 DATLAT Default: 0xd
3310 22:15:45.410084 0, 0xFFFF, sum = 0
3311 22:15:45.412725 1, 0xFFFF, sum = 0
3312 22:15:45.413207 2, 0xFFFF, sum = 0
3313 22:15:45.416385 3, 0xFFFF, sum = 0
3314 22:15:45.416870 4, 0xFFFF, sum = 0
3315 22:15:45.419644 5, 0xFFFF, sum = 0
3316 22:15:45.422873 6, 0xFFFF, sum = 0
3317 22:15:45.423358 7, 0xFFFF, sum = 0
3318 22:15:45.426220 8, 0xFFFF, sum = 0
3319 22:15:45.426746 9, 0xFFFF, sum = 0
3320 22:15:45.430080 10, 0xFFFF, sum = 0
3321 22:15:45.430719 11, 0xFFFF, sum = 0
3322 22:15:45.433162 12, 0x0, sum = 1
3323 22:15:45.433751 13, 0x0, sum = 2
3324 22:15:45.436404 14, 0x0, sum = 3
3325 22:15:45.436995 15, 0x0, sum = 4
3326 22:15:45.437379 best_step = 13
3327 22:15:45.440017
3328 22:15:45.440592 ==
3329 22:15:45.442649 Dram Type= 6, Freq= 0, CH_1, rank 0
3330 22:15:45.446262 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3331 22:15:45.446768 ==
3332 22:15:45.447134 RX Vref Scan: 1
3333 22:15:45.447472
3334 22:15:45.449307 Set Vref Range= 32 -> 127
3335 22:15:45.449771
3336 22:15:45.453729 RX Vref 32 -> 127, step: 1
3337 22:15:45.454193
3338 22:15:45.456336 RX Delay -13 -> 252, step: 4
3339 22:15:45.456802
3340 22:15:45.459317 Set Vref, RX VrefLevel [Byte0]: 32
3341 22:15:45.462567 [Byte1]: 32
3342 22:15:45.463030
3343 22:15:45.466308 Set Vref, RX VrefLevel [Byte0]: 33
3344 22:15:45.468936 [Byte1]: 33
3345 22:15:45.473004
3346 22:15:45.473431 Set Vref, RX VrefLevel [Byte0]: 34
3347 22:15:45.476246 [Byte1]: 34
3348 22:15:45.480563
3349 22:15:45.480989 Set Vref, RX VrefLevel [Byte0]: 35
3350 22:15:45.483640 [Byte1]: 35
3351 22:15:45.488260
3352 22:15:45.488689 Set Vref, RX VrefLevel [Byte0]: 36
3353 22:15:45.491348 [Byte1]: 36
3354 22:15:45.496045
3355 22:15:45.496487 Set Vref, RX VrefLevel [Byte0]: 37
3356 22:15:45.499725 [Byte1]: 37
3357 22:15:45.504337
3358 22:15:45.504898 Set Vref, RX VrefLevel [Byte0]: 38
3359 22:15:45.507419 [Byte1]: 38
3360 22:15:45.511743
3361 22:15:45.515556 Set Vref, RX VrefLevel [Byte0]: 39
3362 22:15:45.516266 [Byte1]: 39
3363 22:15:45.519871
3364 22:15:45.520331 Set Vref, RX VrefLevel [Byte0]: 40
3365 22:15:45.523268 [Byte1]: 40
3366 22:15:45.528394
3367 22:15:45.528957 Set Vref, RX VrefLevel [Byte0]: 41
3368 22:15:45.531683 [Byte1]: 41
3369 22:15:45.535966
3370 22:15:45.536529 Set Vref, RX VrefLevel [Byte0]: 42
3371 22:15:45.539141 [Byte1]: 42
3372 22:15:45.543709
3373 22:15:45.544280 Set Vref, RX VrefLevel [Byte0]: 43
3374 22:15:45.547110 [Byte1]: 43
3375 22:15:45.551640
3376 22:15:45.552203 Set Vref, RX VrefLevel [Byte0]: 44
3377 22:15:45.555246 [Byte1]: 44
3378 22:15:45.559704
3379 22:15:45.560268 Set Vref, RX VrefLevel [Byte0]: 45
3380 22:15:45.563242 [Byte1]: 45
3381 22:15:45.568352
3382 22:15:45.568921 Set Vref, RX VrefLevel [Byte0]: 46
3383 22:15:45.570914 [Byte1]: 46
3384 22:15:45.575475
3385 22:15:45.576034 Set Vref, RX VrefLevel [Byte0]: 47
3386 22:15:45.578948 [Byte1]: 47
3387 22:15:45.583492
3388 22:15:45.584054 Set Vref, RX VrefLevel [Byte0]: 48
3389 22:15:45.586723 [Byte1]: 48
3390 22:15:45.591764
3391 22:15:45.592323 Set Vref, RX VrefLevel [Byte0]: 49
3392 22:15:45.594321 [Byte1]: 49
3393 22:15:45.598890
3394 22:15:45.599356 Set Vref, RX VrefLevel [Byte0]: 50
3395 22:15:45.602228 [Byte1]: 50
3396 22:15:45.606681
3397 22:15:45.607284 Set Vref, RX VrefLevel [Byte0]: 51
3398 22:15:45.610031 [Byte1]: 51
3399 22:15:45.614479
3400 22:15:45.614981 Set Vref, RX VrefLevel [Byte0]: 52
3401 22:15:45.618140 [Byte1]: 52
3402 22:15:45.622835
3403 22:15:45.623468 Set Vref, RX VrefLevel [Byte0]: 53
3404 22:15:45.625813 [Byte1]: 53
3405 22:15:45.630385
3406 22:15:45.630965 Set Vref, RX VrefLevel [Byte0]: 54
3407 22:15:45.633900 [Byte1]: 54
3408 22:15:45.638745
3409 22:15:45.639323 Set Vref, RX VrefLevel [Byte0]: 55
3410 22:15:45.641920 [Byte1]: 55
3411 22:15:45.646459
3412 22:15:45.647032 Set Vref, RX VrefLevel [Byte0]: 56
3413 22:15:45.649337 [Byte1]: 56
3414 22:15:45.654407
3415 22:15:45.654989 Set Vref, RX VrefLevel [Byte0]: 57
3416 22:15:45.657916 [Byte1]: 57
3417 22:15:45.662494
3418 22:15:45.663070 Set Vref, RX VrefLevel [Byte0]: 58
3419 22:15:45.665368 [Byte1]: 58
3420 22:15:45.670202
3421 22:15:45.670816 Set Vref, RX VrefLevel [Byte0]: 59
3422 22:15:45.673514 [Byte1]: 59
3423 22:15:45.677941
3424 22:15:45.678546 Set Vref, RX VrefLevel [Byte0]: 60
3425 22:15:45.681180 [Byte1]: 60
3426 22:15:45.685783
3427 22:15:45.686386 Set Vref, RX VrefLevel [Byte0]: 61
3428 22:15:45.689040 [Byte1]: 61
3429 22:15:45.693718
3430 22:15:45.694309 Set Vref, RX VrefLevel [Byte0]: 62
3431 22:15:45.697079 [Byte1]: 62
3432 22:15:45.701434
3433 22:15:45.702039 Set Vref, RX VrefLevel [Byte0]: 63
3434 22:15:45.705252 [Byte1]: 63
3435 22:15:45.709718
3436 22:15:45.710311 Set Vref, RX VrefLevel [Byte0]: 64
3437 22:15:45.712583 [Byte1]: 64
3438 22:15:45.717254
3439 22:15:45.717743 Set Vref, RX VrefLevel [Byte0]: 65
3440 22:15:45.720401 [Byte1]: 65
3441 22:15:45.725724
3442 22:15:45.726196 Set Vref, RX VrefLevel [Byte0]: 66
3443 22:15:45.728415 [Byte1]: 66
3444 22:15:45.733329
3445 22:15:45.733871 Set Vref, RX VrefLevel [Byte0]: 67
3446 22:15:45.736443 [Byte1]: 67
3447 22:15:45.740903
3448 22:15:45.741476 Final RX Vref Byte 0 = 51 to rank0
3449 22:15:45.744256 Final RX Vref Byte 1 = 50 to rank0
3450 22:15:45.747572 Final RX Vref Byte 0 = 51 to rank1
3451 22:15:45.751246 Final RX Vref Byte 1 = 50 to rank1==
3452 22:15:45.754257 Dram Type= 6, Freq= 0, CH_1, rank 0
3453 22:15:45.760745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3454 22:15:45.761311 ==
3455 22:15:45.761688 DQS Delay:
3456 22:15:45.762037 DQS0 = 0, DQS1 = 0
3457 22:15:45.764774 DQM Delay:
3458 22:15:45.765355 DQM0 = 119, DQM1 = 111
3459 22:15:45.767964 DQ Delay:
3460 22:15:45.770853 DQ0 =120, DQ1 =112, DQ2 =112, DQ3 =118
3461 22:15:45.774424 DQ4 =118, DQ5 =128, DQ6 =128, DQ7 =118
3462 22:15:45.778167 DQ8 =100, DQ9 =100, DQ10 =114, DQ11 =104
3463 22:15:45.780817 DQ12 =122, DQ13 =116, DQ14 =118, DQ15 =116
3464 22:15:45.781397
3465 22:15:45.781777
3466 22:15:45.787595 [DQSOSCAuto] RK0, (LSB)MR18= 0x14, (MSB)MR19= 0x404, tDQSOscB0 = 402 ps tDQSOscB1 = 410 ps
3467 22:15:45.791184 CH1 RK0: MR19=404, MR18=14
3468 22:15:45.797780 CH1_RK0: MR19=0x404, MR18=0x14, DQSOSC=402, MR23=63, INC=40, DEC=27
3469 22:15:45.798397
3470 22:15:45.801156 ----->DramcWriteLeveling(PI) begin...
3471 22:15:45.801641 ==
3472 22:15:45.804686 Dram Type= 6, Freq= 0, CH_1, rank 1
3473 22:15:45.808108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3474 22:15:45.808691 ==
3475 22:15:45.813248 Write leveling (Byte 0): 26 => 26
3476 22:15:45.814245 Write leveling (Byte 1): 28 => 28
3477 22:15:45.817535 DramcWriteLeveling(PI) end<-----
3478 22:15:45.818024
3479 22:15:45.818450 ==
3480 22:15:45.820562 Dram Type= 6, Freq= 0, CH_1, rank 1
3481 22:15:45.827436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3482 22:15:45.827931 ==
3483 22:15:45.828301 [Gating] SW mode calibration
3484 22:15:45.837610 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3485 22:15:45.841184 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3486 22:15:45.844248 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3487 22:15:45.850374 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3488 22:15:45.854636 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3489 22:15:45.857814 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3490 22:15:45.864162 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3491 22:15:45.867873 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3492 22:15:45.871668 0 15 24 | B1->B0 | 2b2b 3434 | 0 0 | (0 0) (0 1)
3493 22:15:45.877792 0 15 28 | B1->B0 | 2323 2a2a | 0 1 | (1 0) (1 0)
3494 22:15:45.881223 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3495 22:15:45.884116 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3496 22:15:45.891280 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3497 22:15:45.894278 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3498 22:15:45.897558 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3499 22:15:45.904544 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3500 22:15:45.907819 1 0 24 | B1->B0 | 3535 2525 | 0 0 | (1 1) (0 0)
3501 22:15:45.911018 1 0 28 | B1->B0 | 4646 4141 | 0 0 | (0 0) (0 0)
3502 22:15:45.916970 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3503 22:15:45.920464 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3504 22:15:45.923667 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3505 22:15:45.930760 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3506 22:15:45.933687 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3507 22:15:45.937073 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3508 22:15:45.943492 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3509 22:15:45.947473 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3510 22:15:45.950524 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3511 22:15:45.956707 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3512 22:15:45.960168 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3513 22:15:45.963153 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3514 22:15:45.970173 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3515 22:15:45.973723 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3516 22:15:45.976848 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3517 22:15:45.983191 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3518 22:15:45.986687 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3519 22:15:45.990114 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3520 22:15:45.996333 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3521 22:15:45.999497 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3522 22:15:46.003557 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3523 22:15:46.009889 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3524 22:15:46.012845 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3525 22:15:46.016397 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3526 22:15:46.019643 Total UI for P1: 0, mck2ui 16
3527 22:15:46.023004 best dqsien dly found for B1: ( 1, 3, 24)
3528 22:15:46.026123 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3529 22:15:46.029633 Total UI for P1: 0, mck2ui 16
3530 22:15:46.033011 best dqsien dly found for B0: ( 1, 3, 26)
3531 22:15:46.036005 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3532 22:15:46.043495 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3533 22:15:46.044069
3534 22:15:46.046095 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3535 22:15:46.049451 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3536 22:15:46.052395 [Gating] SW calibration Done
3537 22:15:46.052904 ==
3538 22:15:46.056286 Dram Type= 6, Freq= 0, CH_1, rank 1
3539 22:15:46.059368 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3540 22:15:46.059851 ==
3541 22:15:46.062964 RX Vref Scan: 0
3542 22:15:46.063543
3543 22:15:46.063918 RX Vref 0 -> 0, step: 1
3544 22:15:46.064264
3545 22:15:46.066275 RX Delay -40 -> 252, step: 8
3546 22:15:46.069194 iDelay=200, Bit 0, Center 123 (64 ~ 183) 120
3547 22:15:46.076099 iDelay=200, Bit 1, Center 111 (48 ~ 175) 128
3548 22:15:46.079377 iDelay=200, Bit 2, Center 107 (48 ~ 167) 120
3549 22:15:46.082627 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3550 22:15:46.085658 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
3551 22:15:46.090137 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3552 22:15:46.095565 iDelay=200, Bit 6, Center 123 (56 ~ 191) 136
3553 22:15:46.098723 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3554 22:15:46.102220 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3555 22:15:46.105946 iDelay=200, Bit 9, Center 103 (40 ~ 167) 128
3556 22:15:46.109016 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3557 22:15:46.115560 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3558 22:15:46.119051 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3559 22:15:46.122133 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3560 22:15:46.126144 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3561 22:15:46.128712 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3562 22:15:46.132167 ==
3563 22:15:46.134940 Dram Type= 6, Freq= 0, CH_1, rank 1
3564 22:15:46.138812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3565 22:15:46.139389 ==
3566 22:15:46.139768 DQS Delay:
3567 22:15:46.141780 DQS0 = 0, DQS1 = 0
3568 22:15:46.142255 DQM Delay:
3569 22:15:46.144929 DQM0 = 119, DQM1 = 112
3570 22:15:46.145405 DQ Delay:
3571 22:15:46.148449 DQ0 =123, DQ1 =111, DQ2 =107, DQ3 =119
3572 22:15:46.151454 DQ4 =123, DQ5 =131, DQ6 =123, DQ7 =115
3573 22:15:46.155015 DQ8 =99, DQ9 =103, DQ10 =115, DQ11 =107
3574 22:15:46.158736 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3575 22:15:46.159343
3576 22:15:46.159829
3577 22:15:46.160284 ==
3578 22:15:46.161419 Dram Type= 6, Freq= 0, CH_1, rank 1
3579 22:15:46.168228 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3580 22:15:46.168813 ==
3581 22:15:46.169308
3582 22:15:46.169764
3583 22:15:46.170208 TX Vref Scan disable
3584 22:15:46.172088 == TX Byte 0 ==
3585 22:15:46.175219 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3586 22:15:46.181991 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3587 22:15:46.182606 == TX Byte 1 ==
3588 22:15:46.185158 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3589 22:15:46.191950 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3590 22:15:46.192534 ==
3591 22:15:46.195538 Dram Type= 6, Freq= 0, CH_1, rank 1
3592 22:15:46.198591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3593 22:15:46.199192 ==
3594 22:15:46.209901 TX Vref=22, minBit 1, minWin=25, winSum=414
3595 22:15:46.212741 TX Vref=24, minBit 1, minWin=25, winSum=420
3596 22:15:46.216016 TX Vref=26, minBit 0, minWin=26, winSum=427
3597 22:15:46.219474 TX Vref=28, minBit 0, minWin=26, winSum=428
3598 22:15:46.223224 TX Vref=30, minBit 1, minWin=26, winSum=427
3599 22:15:46.229691 TX Vref=32, minBit 1, minWin=26, winSum=428
3600 22:15:46.232955 [TxChooseVref] Worse bit 0, Min win 26, Win sum 428, Final Vref 28
3601 22:15:46.233529
3602 22:15:46.236239 Final TX Range 1 Vref 28
3603 22:15:46.236812
3604 22:15:46.237181 ==
3605 22:15:46.239300 Dram Type= 6, Freq= 0, CH_1, rank 1
3606 22:15:46.246011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3607 22:15:46.246672 ==
3608 22:15:46.247049
3609 22:15:46.247390
3610 22:15:46.247717 TX Vref Scan disable
3611 22:15:46.249333 == TX Byte 0 ==
3612 22:15:46.252284 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3613 22:15:46.259149 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3614 22:15:46.259702 == TX Byte 1 ==
3615 22:15:46.262594 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3616 22:15:46.269198 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3617 22:15:46.269765
3618 22:15:46.270133 [DATLAT]
3619 22:15:46.270656 Freq=1200, CH1 RK1
3620 22:15:46.271148
3621 22:15:46.272419 DATLAT Default: 0xd
3622 22:15:46.276291 0, 0xFFFF, sum = 0
3623 22:15:46.276769 1, 0xFFFF, sum = 0
3624 22:15:46.279089 2, 0xFFFF, sum = 0
3625 22:15:46.279634 3, 0xFFFF, sum = 0
3626 22:15:46.282391 4, 0xFFFF, sum = 0
3627 22:15:46.282978 5, 0xFFFF, sum = 0
3628 22:15:46.285824 6, 0xFFFF, sum = 0
3629 22:15:46.286452 7, 0xFFFF, sum = 0
3630 22:15:46.288910 8, 0xFFFF, sum = 0
3631 22:15:46.289489 9, 0xFFFF, sum = 0
3632 22:15:46.292561 10, 0xFFFF, sum = 0
3633 22:15:46.293143 11, 0xFFFF, sum = 0
3634 22:15:46.295725 12, 0x0, sum = 1
3635 22:15:46.296202 13, 0x0, sum = 2
3636 22:15:46.298828 14, 0x0, sum = 3
3637 22:15:46.299305 15, 0x0, sum = 4
3638 22:15:46.302218 best_step = 13
3639 22:15:46.302818
3640 22:15:46.303190 ==
3641 22:15:46.305539 Dram Type= 6, Freq= 0, CH_1, rank 1
3642 22:15:46.309037 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3643 22:15:46.309612 ==
3644 22:15:46.312748 RX Vref Scan: 0
3645 22:15:46.313335
3646 22:15:46.313708 RX Vref 0 -> 0, step: 1
3647 22:15:46.314093
3648 22:15:46.315008 RX Delay -13 -> 252, step: 4
3649 22:15:46.322055 iDelay=195, Bit 0, Center 122 (63 ~ 182) 120
3650 22:15:46.325396 iDelay=195, Bit 1, Center 114 (55 ~ 174) 120
3651 22:15:46.328617 iDelay=195, Bit 2, Center 108 (51 ~ 166) 116
3652 22:15:46.331670 iDelay=195, Bit 3, Center 116 (55 ~ 178) 124
3653 22:15:46.335085 iDelay=195, Bit 4, Center 122 (63 ~ 182) 120
3654 22:15:46.341587 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3655 22:15:46.345757 iDelay=195, Bit 6, Center 126 (67 ~ 186) 120
3656 22:15:46.348136 iDelay=195, Bit 7, Center 116 (55 ~ 178) 124
3657 22:15:46.351698 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3658 22:15:46.354686 iDelay=195, Bit 9, Center 100 (35 ~ 166) 132
3659 22:15:46.361644 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3660 22:15:46.365125 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3661 22:15:46.368325 iDelay=195, Bit 12, Center 122 (59 ~ 186) 128
3662 22:15:46.371042 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3663 22:15:46.378327 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3664 22:15:46.382107 iDelay=195, Bit 15, Center 124 (59 ~ 190) 132
3665 22:15:46.382725 ==
3666 22:15:46.384843 Dram Type= 6, Freq= 0, CH_1, rank 1
3667 22:15:46.388029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3668 22:15:46.388515 ==
3669 22:15:46.388884 DQS Delay:
3670 22:15:46.391906 DQS0 = 0, DQS1 = 0
3671 22:15:46.392473 DQM Delay:
3672 22:15:46.395023 DQM0 = 119, DQM1 = 113
3673 22:15:46.395493 DQ Delay:
3674 22:15:46.397849 DQ0 =122, DQ1 =114, DQ2 =108, DQ3 =116
3675 22:15:46.401740 DQ4 =122, DQ5 =130, DQ6 =126, DQ7 =116
3676 22:15:46.405196 DQ8 =98, DQ9 =100, DQ10 =114, DQ11 =106
3677 22:15:46.411622 DQ12 =122, DQ13 =118, DQ14 =122, DQ15 =124
3678 22:15:46.412183
3679 22:15:46.412552
3680 22:15:46.417945 [DQSOSCAuto] RK1, (LSB)MR18= 0x7eb, (MSB)MR19= 0x403, tDQSOscB0 = 418 ps tDQSOscB1 = 407 ps
3681 22:15:46.421076 CH1 RK1: MR19=403, MR18=7EB
3682 22:15:46.428043 CH1_RK1: MR19=0x403, MR18=0x7EB, DQSOSC=407, MR23=63, INC=39, DEC=26
3683 22:15:46.430901 [RxdqsGatingPostProcess] freq 1200
3684 22:15:46.434402 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3685 22:15:46.437713 best DQS0 dly(2T, 0.5T) = (0, 11)
3686 22:15:46.441215 best DQS1 dly(2T, 0.5T) = (0, 11)
3687 22:15:46.444094 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3688 22:15:46.447068 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3689 22:15:46.451241 best DQS0 dly(2T, 0.5T) = (0, 11)
3690 22:15:46.454057 best DQS1 dly(2T, 0.5T) = (0, 11)
3691 22:15:46.457426 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3692 22:15:46.460479 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3693 22:15:46.463758 Pre-setting of DQS Precalculation
3694 22:15:46.467093 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3695 22:15:46.476924 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3696 22:15:46.483624 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3697 22:15:46.484227
3698 22:15:46.484610
3699 22:15:46.486828 [Calibration Summary] 2400 Mbps
3700 22:15:46.487415 CH 0, Rank 0
3701 22:15:46.490064 SW Impedance : PASS
3702 22:15:46.490582 DUTY Scan : NO K
3703 22:15:46.493876 ZQ Calibration : PASS
3704 22:15:46.497413 Jitter Meter : NO K
3705 22:15:46.497892 CBT Training : PASS
3706 22:15:46.499921 Write leveling : PASS
3707 22:15:46.503183 RX DQS gating : PASS
3708 22:15:46.503751 RX DQ/DQS(RDDQC) : PASS
3709 22:15:46.506718 TX DQ/DQS : PASS
3710 22:15:46.510238 RX DATLAT : PASS
3711 22:15:46.510760 RX DQ/DQS(Engine): PASS
3712 22:15:46.512932 TX OE : NO K
3713 22:15:46.513455 All Pass.
3714 22:15:46.513845
3715 22:15:46.516566 CH 0, Rank 1
3716 22:15:46.517038 SW Impedance : PASS
3717 22:15:46.520377 DUTY Scan : NO K
3718 22:15:46.522935 ZQ Calibration : PASS
3719 22:15:46.523414 Jitter Meter : NO K
3720 22:15:46.526957 CBT Training : PASS
3721 22:15:46.529475 Write leveling : PASS
3722 22:15:46.529951 RX DQS gating : PASS
3723 22:15:46.533095 RX DQ/DQS(RDDQC) : PASS
3724 22:15:46.536428 TX DQ/DQS : PASS
3725 22:15:46.537002 RX DATLAT : PASS
3726 22:15:46.539443 RX DQ/DQS(Engine): PASS
3727 22:15:46.540013 TX OE : NO K
3728 22:15:46.542809 All Pass.
3729 22:15:46.543286
3730 22:15:46.543660 CH 1, Rank 0
3731 22:15:46.546119 SW Impedance : PASS
3732 22:15:46.546623 DUTY Scan : NO K
3733 22:15:46.549766 ZQ Calibration : PASS
3734 22:15:46.553129 Jitter Meter : NO K
3735 22:15:46.553774 CBT Training : PASS
3736 22:15:46.556821 Write leveling : PASS
3737 22:15:46.559633 RX DQS gating : PASS
3738 22:15:46.560200 RX DQ/DQS(RDDQC) : PASS
3739 22:15:46.562909 TX DQ/DQS : PASS
3740 22:15:46.566719 RX DATLAT : PASS
3741 22:15:46.567291 RX DQ/DQS(Engine): PASS
3742 22:15:46.569584 TX OE : NO K
3743 22:15:46.570152 All Pass.
3744 22:15:46.570568
3745 22:15:46.573494 CH 1, Rank 1
3746 22:15:46.574060 SW Impedance : PASS
3747 22:15:46.576075 DUTY Scan : NO K
3748 22:15:46.579467 ZQ Calibration : PASS
3749 22:15:46.579945 Jitter Meter : NO K
3750 22:15:46.583000 CBT Training : PASS
3751 22:15:46.586172 Write leveling : PASS
3752 22:15:46.586860 RX DQS gating : PASS
3753 22:15:46.589332 RX DQ/DQS(RDDQC) : PASS
3754 22:15:46.592924 TX DQ/DQS : PASS
3755 22:15:46.593496 RX DATLAT : PASS
3756 22:15:46.595800 RX DQ/DQS(Engine): PASS
3757 22:15:46.596278 TX OE : NO K
3758 22:15:46.599190 All Pass.
3759 22:15:46.599675
3760 22:15:46.600119 DramC Write-DBI off
3761 22:15:46.602546 PER_BANK_REFRESH: Hybrid Mode
3762 22:15:46.606325 TX_TRACKING: ON
3763 22:15:46.612405 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3764 22:15:46.615709 [FAST_K] Save calibration result to emmc
3765 22:15:46.622444 dramc_set_vcore_voltage set vcore to 650000
3766 22:15:46.623020 Read voltage for 600, 5
3767 22:15:46.623405 Vio18 = 0
3768 22:15:46.625436 Vcore = 650000
3769 22:15:46.625910 Vdram = 0
3770 22:15:46.626284 Vddq = 0
3771 22:15:46.629052 Vmddr = 0
3772 22:15:46.632121 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3773 22:15:46.638949 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3774 22:15:46.642630 MEM_TYPE=3, freq_sel=19
3775 22:15:46.643202 sv_algorithm_assistance_LP4_1600
3776 22:15:46.648766 ============ PULL DRAM RESETB DOWN ============
3777 22:15:46.652226 ========== PULL DRAM RESETB DOWN end =========
3778 22:15:46.655279 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3779 22:15:46.659256 ===================================
3780 22:15:46.662631 LPDDR4 DRAM CONFIGURATION
3781 22:15:46.665318 ===================================
3782 22:15:46.668478 EX_ROW_EN[0] = 0x0
3783 22:15:46.669050 EX_ROW_EN[1] = 0x0
3784 22:15:46.672486 LP4Y_EN = 0x0
3785 22:15:46.673055 WORK_FSP = 0x0
3786 22:15:46.674799 WL = 0x2
3787 22:15:46.675277 RL = 0x2
3788 22:15:46.678342 BL = 0x2
3789 22:15:46.678997 RPST = 0x0
3790 22:15:46.681758 RD_PRE = 0x0
3791 22:15:46.685444 WR_PRE = 0x1
3792 22:15:46.686008 WR_PST = 0x0
3793 22:15:46.688613 DBI_WR = 0x0
3794 22:15:46.689186 DBI_RD = 0x0
3795 22:15:46.691517 OTF = 0x1
3796 22:15:46.694914 ===================================
3797 22:15:46.698376 ===================================
3798 22:15:46.698951 ANA top config
3799 22:15:46.701407 ===================================
3800 22:15:46.705223 DLL_ASYNC_EN = 0
3801 22:15:46.708359 ALL_SLAVE_EN = 1
3802 22:15:46.708921 NEW_RANK_MODE = 1
3803 22:15:46.711195 DLL_IDLE_MODE = 1
3804 22:15:46.714717 LP45_APHY_COMB_EN = 1
3805 22:15:46.718155 TX_ODT_DIS = 1
3806 22:15:46.721139 NEW_8X_MODE = 1
3807 22:15:46.724945 ===================================
3808 22:15:46.727687 ===================================
3809 22:15:46.728174 data_rate = 1200
3810 22:15:46.730748 CKR = 1
3811 22:15:46.734300 DQ_P2S_RATIO = 8
3812 22:15:46.737405 ===================================
3813 22:15:46.741065 CA_P2S_RATIO = 8
3814 22:15:46.744434 DQ_CA_OPEN = 0
3815 22:15:46.747490 DQ_SEMI_OPEN = 0
3816 22:15:46.748060 CA_SEMI_OPEN = 0
3817 22:15:46.750677 CA_FULL_RATE = 0
3818 22:15:46.753901 DQ_CKDIV4_EN = 1
3819 22:15:46.757920 CA_CKDIV4_EN = 1
3820 22:15:46.760578 CA_PREDIV_EN = 0
3821 22:15:46.763959 PH8_DLY = 0
3822 22:15:46.764527 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3823 22:15:46.767415 DQ_AAMCK_DIV = 4
3824 22:15:46.770508 CA_AAMCK_DIV = 4
3825 22:15:46.774567 CA_ADMCK_DIV = 4
3826 22:15:46.777553 DQ_TRACK_CA_EN = 0
3827 22:15:46.780625 CA_PICK = 600
3828 22:15:46.784441 CA_MCKIO = 600
3829 22:15:46.785014 MCKIO_SEMI = 0
3830 22:15:46.786826 PLL_FREQ = 2288
3831 22:15:46.790134 DQ_UI_PI_RATIO = 32
3832 22:15:46.793689 CA_UI_PI_RATIO = 0
3833 22:15:46.796791 ===================================
3834 22:15:46.800146 ===================================
3835 22:15:46.803336 memory_type:LPDDR4
3836 22:15:46.803907 GP_NUM : 10
3837 22:15:46.806657 SRAM_EN : 1
3838 22:15:46.810009 MD32_EN : 0
3839 22:15:46.813705 ===================================
3840 22:15:46.814185 [ANA_INIT] >>>>>>>>>>>>>>
3841 22:15:46.816605 <<<<<< [CONFIGURE PHASE]: ANA_TX
3842 22:15:46.820277 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3843 22:15:46.823221 ===================================
3844 22:15:46.826785 data_rate = 1200,PCW = 0X5800
3845 22:15:46.829818 ===================================
3846 22:15:46.833363 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3847 22:15:46.840094 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3848 22:15:46.843110 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3849 22:15:46.849937 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3850 22:15:46.853621 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3851 22:15:46.856726 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3852 22:15:46.859980 [ANA_INIT] flow start
3853 22:15:46.860551 [ANA_INIT] PLL >>>>>>>>
3854 22:15:46.862780 [ANA_INIT] PLL <<<<<<<<
3855 22:15:46.866115 [ANA_INIT] MIDPI >>>>>>>>
3856 22:15:46.866622 [ANA_INIT] MIDPI <<<<<<<<
3857 22:15:46.869366 [ANA_INIT] DLL >>>>>>>>
3858 22:15:46.873189 [ANA_INIT] flow end
3859 22:15:46.876499 ============ LP4 DIFF to SE enter ============
3860 22:15:46.879425 ============ LP4 DIFF to SE exit ============
3861 22:15:46.883323 [ANA_INIT] <<<<<<<<<<<<<
3862 22:15:46.886573 [Flow] Enable top DCM control >>>>>
3863 22:15:46.889624 [Flow] Enable top DCM control <<<<<
3864 22:15:46.892850 Enable DLL master slave shuffle
3865 22:15:46.895960 ==============================================================
3866 22:15:46.899430 Gating Mode config
3867 22:15:46.905594 ==============================================================
3868 22:15:46.906115 Config description:
3869 22:15:46.915633 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3870 22:15:46.922452 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3871 22:15:46.925679 SELPH_MODE 0: By rank 1: By Phase
3872 22:15:46.932250 ==============================================================
3873 22:15:46.936463 GAT_TRACK_EN = 1
3874 22:15:46.939078 RX_GATING_MODE = 2
3875 22:15:46.942103 RX_GATING_TRACK_MODE = 2
3876 22:15:46.946100 SELPH_MODE = 1
3877 22:15:46.949457 PICG_EARLY_EN = 1
3878 22:15:46.952564 VALID_LAT_VALUE = 1
3879 22:15:46.955389 ==============================================================
3880 22:15:46.959243 Enter into Gating configuration >>>>
3881 22:15:46.962603 Exit from Gating configuration <<<<
3882 22:15:46.965688 Enter into DVFS_PRE_config >>>>>
3883 22:15:46.979211 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3884 22:15:46.982633 Exit from DVFS_PRE_config <<<<<
3885 22:15:46.983202 Enter into PICG configuration >>>>
3886 22:15:46.985397 Exit from PICG configuration <<<<
3887 22:15:46.988915 [RX_INPUT] configuration >>>>>
3888 22:15:46.992920 [RX_INPUT] configuration <<<<<
3889 22:15:46.999170 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3890 22:15:47.001965 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3891 22:15:47.008592 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3892 22:15:47.015126 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3893 22:15:47.021698 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3894 22:15:47.028573 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3895 22:15:47.031377 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3896 22:15:47.035018 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3897 22:15:47.038725 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3898 22:15:47.044885 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3899 22:15:47.048171 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3900 22:15:47.051307 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3901 22:15:47.054699 ===================================
3902 22:15:47.057905 LPDDR4 DRAM CONFIGURATION
3903 22:15:47.061224 ===================================
3904 22:15:47.064788 EX_ROW_EN[0] = 0x0
3905 22:15:47.065358 EX_ROW_EN[1] = 0x0
3906 22:15:47.067859 LP4Y_EN = 0x0
3907 22:15:47.068432 WORK_FSP = 0x0
3908 22:15:47.071236 WL = 0x2
3909 22:15:47.071807 RL = 0x2
3910 22:15:47.074706 BL = 0x2
3911 22:15:47.075276 RPST = 0x0
3912 22:15:47.078011 RD_PRE = 0x0
3913 22:15:47.078606 WR_PRE = 0x1
3914 22:15:47.081430 WR_PST = 0x0
3915 22:15:47.081997 DBI_WR = 0x0
3916 22:15:47.084748 DBI_RD = 0x0
3917 22:15:47.087743 OTF = 0x1
3918 22:15:47.091226 ===================================
3919 22:15:47.095222 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3920 22:15:47.097406 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3921 22:15:47.100861 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3922 22:15:47.104369 ===================================
3923 22:15:47.107635 LPDDR4 DRAM CONFIGURATION
3924 22:15:47.111887 ===================================
3925 22:15:47.114437 EX_ROW_EN[0] = 0x10
3926 22:15:47.115020 EX_ROW_EN[1] = 0x0
3927 22:15:47.117409 LP4Y_EN = 0x0
3928 22:15:47.117882 WORK_FSP = 0x0
3929 22:15:47.120765 WL = 0x2
3930 22:15:47.121335 RL = 0x2
3931 22:15:47.124981 BL = 0x2
3932 22:15:47.125450 RPST = 0x0
3933 22:15:47.127001 RD_PRE = 0x0
3934 22:15:47.127472 WR_PRE = 0x1
3935 22:15:47.130541 WR_PST = 0x0
3936 22:15:47.131104 DBI_WR = 0x0
3937 22:15:47.133908 DBI_RD = 0x0
3938 22:15:47.137408 OTF = 0x1
3939 22:15:47.141352 ===================================
3940 22:15:47.144331 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3941 22:15:47.149380 nWR fixed to 30
3942 22:15:47.152517 [ModeRegInit_LP4] CH0 RK0
3943 22:15:47.153099 [ModeRegInit_LP4] CH0 RK1
3944 22:15:47.155236 [ModeRegInit_LP4] CH1 RK0
3945 22:15:47.159349 [ModeRegInit_LP4] CH1 RK1
3946 22:15:47.159929 match AC timing 17
3947 22:15:47.165721 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3948 22:15:47.169448 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3949 22:15:47.172569 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3950 22:15:47.178929 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3951 22:15:47.181938 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3952 22:15:47.182465 ==
3953 22:15:47.186343 Dram Type= 6, Freq= 0, CH_0, rank 0
3954 22:15:47.188866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3955 22:15:47.189447 ==
3956 22:15:47.195340 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3957 22:15:47.201750 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3958 22:15:47.205417 [CA 0] Center 36 (6~67) winsize 62
3959 22:15:47.208911 [CA 1] Center 36 (6~67) winsize 62
3960 22:15:47.212342 [CA 2] Center 34 (4~65) winsize 62
3961 22:15:47.215042 [CA 3] Center 34 (3~65) winsize 63
3962 22:15:47.220106 [CA 4] Center 34 (3~65) winsize 63
3963 22:15:47.221660 [CA 5] Center 33 (3~64) winsize 62
3964 22:15:47.222136
3965 22:15:47.225482 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3966 22:15:47.226048
3967 22:15:47.228794 [CATrainingPosCal] consider 1 rank data
3968 22:15:47.231846 u2DelayCellTimex100 = 270/100 ps
3969 22:15:47.235455 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3970 22:15:47.238796 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3971 22:15:47.241789 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3972 22:15:47.244786 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3973 22:15:47.251338 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
3974 22:15:47.254817 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3975 22:15:47.255298
3976 22:15:47.258021 CA PerBit enable=1, Macro0, CA PI delay=33
3977 22:15:47.258611
3978 22:15:47.261289 [CBTSetCACLKResult] CA Dly = 33
3979 22:15:47.261766 CS Dly: 5 (0~36)
3980 22:15:47.262141 ==
3981 22:15:47.264904 Dram Type= 6, Freq= 0, CH_0, rank 1
3982 22:15:47.271835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3983 22:15:47.272409 ==
3984 22:15:47.275044 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3985 22:15:47.281489 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3986 22:15:47.284654 [CA 0] Center 36 (6~67) winsize 62
3987 22:15:47.288457 [CA 1] Center 36 (6~67) winsize 62
3988 22:15:47.290946 [CA 2] Center 35 (4~66) winsize 63
3989 22:15:47.294533 [CA 3] Center 34 (4~65) winsize 62
3990 22:15:47.298174 [CA 4] Center 34 (3~65) winsize 63
3991 22:15:47.300977 [CA 5] Center 34 (3~65) winsize 63
3992 22:15:47.301452
3993 22:15:47.304905 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3994 22:15:47.305469
3995 22:15:47.308003 [CATrainingPosCal] consider 2 rank data
3996 22:15:47.311301 u2DelayCellTimex100 = 270/100 ps
3997 22:15:47.314530 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3998 22:15:47.317592 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3999 22:15:47.324817 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4000 22:15:47.327304 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4001 22:15:47.331159 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4002 22:15:47.334339 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4003 22:15:47.334880
4004 22:15:47.337497 CA PerBit enable=1, Macro0, CA PI delay=33
4005 22:15:47.337965
4006 22:15:47.340829 [CBTSetCACLKResult] CA Dly = 33
4007 22:15:47.341401 CS Dly: 5 (0~37)
4008 22:15:47.341850
4009 22:15:47.347610 ----->DramcWriteLeveling(PI) begin...
4010 22:15:47.348170 ==
4011 22:15:47.350663 Dram Type= 6, Freq= 0, CH_0, rank 0
4012 22:15:47.353977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4013 22:15:47.354479 ==
4014 22:15:47.357283 Write leveling (Byte 0): 35 => 35
4015 22:15:47.360638 Write leveling (Byte 1): 29 => 29
4016 22:15:47.364295 DramcWriteLeveling(PI) end<-----
4017 22:15:47.364863
4018 22:15:47.365253 ==
4019 22:15:47.367446 Dram Type= 6, Freq= 0, CH_0, rank 0
4020 22:15:47.370616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4021 22:15:47.371190 ==
4022 22:15:47.374164 [Gating] SW mode calibration
4023 22:15:47.380615 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4024 22:15:47.387028 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4025 22:15:47.390759 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4026 22:15:47.393688 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4027 22:15:47.400711 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4028 22:15:47.403533 0 9 12 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 0)
4029 22:15:47.407246 0 9 16 | B1->B0 | 2a2a 2323 | 1 0 | (1 0) (0 0)
4030 22:15:47.414220 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4031 22:15:47.416598 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4032 22:15:47.420188 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4033 22:15:47.426942 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4034 22:15:47.430196 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4035 22:15:47.433719 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4036 22:15:47.440071 0 10 12 | B1->B0 | 2626 3838 | 0 0 | (0 0) (1 1)
4037 22:15:47.442982 0 10 16 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
4038 22:15:47.446968 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4039 22:15:47.453677 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4040 22:15:47.456545 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4041 22:15:47.459918 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4042 22:15:47.463058 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4043 22:15:47.470520 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4044 22:15:47.473464 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4045 22:15:47.477089 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4046 22:15:47.483536 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4047 22:15:47.486158 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4048 22:15:47.489986 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4049 22:15:47.496699 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4050 22:15:47.499493 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4051 22:15:47.503747 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4052 22:15:47.509926 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4053 22:15:47.513117 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4054 22:15:47.516408 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4055 22:15:47.523097 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4056 22:15:47.527097 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4057 22:15:47.529543 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4058 22:15:47.536036 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4059 22:15:47.539011 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4060 22:15:47.542618 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4061 22:15:47.546002 Total UI for P1: 0, mck2ui 16
4062 22:15:47.549170 best dqsien dly found for B0: ( 0, 13, 10)
4063 22:15:47.555772 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4064 22:15:47.559259 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4065 22:15:47.562645 Total UI for P1: 0, mck2ui 16
4066 22:15:47.566028 best dqsien dly found for B1: ( 0, 13, 14)
4067 22:15:47.568992 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4068 22:15:47.572352 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4069 22:15:47.572934
4070 22:15:47.575611 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4071 22:15:47.582463 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4072 22:15:47.583046 [Gating] SW calibration Done
4073 22:15:47.583543 ==
4074 22:15:47.585907 Dram Type= 6, Freq= 0, CH_0, rank 0
4075 22:15:47.592063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4076 22:15:47.592656 ==
4077 22:15:47.593148 RX Vref Scan: 0
4078 22:15:47.593606
4079 22:15:47.595493 RX Vref 0 -> 0, step: 1
4080 22:15:47.596073
4081 22:15:47.599001 RX Delay -230 -> 252, step: 16
4082 22:15:47.601967 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4083 22:15:47.605816 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4084 22:15:47.612240 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4085 22:15:47.615498 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4086 22:15:47.618333 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4087 22:15:47.621913 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4088 22:15:47.625290 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4089 22:15:47.631758 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4090 22:15:47.634922 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4091 22:15:47.638334 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4092 22:15:47.641973 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4093 22:15:47.648109 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4094 22:15:47.651245 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4095 22:15:47.655028 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4096 22:15:47.658333 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4097 22:15:47.664866 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4098 22:15:47.665464 ==
4099 22:15:47.667749 Dram Type= 6, Freq= 0, CH_0, rank 0
4100 22:15:47.671179 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4101 22:15:47.671762 ==
4102 22:15:47.672249 DQS Delay:
4103 22:15:47.674498 DQS0 = 0, DQS1 = 0
4104 22:15:47.675079 DQM Delay:
4105 22:15:47.677469 DQM0 = 50, DQM1 = 40
4106 22:15:47.677961 DQ Delay:
4107 22:15:47.681225 DQ0 =49, DQ1 =57, DQ2 =41, DQ3 =41
4108 22:15:47.684486 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57
4109 22:15:47.687833 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =33
4110 22:15:47.690965 DQ12 =41, DQ13 =49, DQ14 =49, DQ15 =49
4111 22:15:47.691562
4112 22:15:47.692047
4113 22:15:47.692504 ==
4114 22:15:47.694010 Dram Type= 6, Freq= 0, CH_0, rank 0
4115 22:15:47.697314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4116 22:15:47.700836 ==
4117 22:15:47.701323
4118 22:15:47.701809
4119 22:15:47.702262 TX Vref Scan disable
4120 22:15:47.703902 == TX Byte 0 ==
4121 22:15:47.707504 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4122 22:15:47.714087 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4123 22:15:47.714721 == TX Byte 1 ==
4124 22:15:47.717061 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4125 22:15:47.723873 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4126 22:15:47.724458 ==
4127 22:15:47.727694 Dram Type= 6, Freq= 0, CH_0, rank 0
4128 22:15:47.730657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4129 22:15:47.731245 ==
4130 22:15:47.731729
4131 22:15:47.732183
4132 22:15:47.734004 TX Vref Scan disable
4133 22:15:47.736817 == TX Byte 0 ==
4134 22:15:47.740464 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4135 22:15:47.744008 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4136 22:15:47.747754 == TX Byte 1 ==
4137 22:15:47.750316 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4138 22:15:47.753823 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4139 22:15:47.754436
4140 22:15:47.754816 [DATLAT]
4141 22:15:47.757428 Freq=600, CH0 RK0
4142 22:15:47.757984
4143 22:15:47.760616 DATLAT Default: 0x9
4144 22:15:47.761185 0, 0xFFFF, sum = 0
4145 22:15:47.763744 1, 0xFFFF, sum = 0
4146 22:15:47.764324 2, 0xFFFF, sum = 0
4147 22:15:47.767124 3, 0xFFFF, sum = 0
4148 22:15:47.767701 4, 0xFFFF, sum = 0
4149 22:15:47.770222 5, 0xFFFF, sum = 0
4150 22:15:47.770784 6, 0xFFFF, sum = 0
4151 22:15:47.773253 7, 0xFFFF, sum = 0
4152 22:15:47.773886 8, 0x0, sum = 1
4153 22:15:47.776239 9, 0x0, sum = 2
4154 22:15:47.776324 10, 0x0, sum = 3
4155 22:15:47.779946 11, 0x0, sum = 4
4156 22:15:47.780033 best_step = 9
4157 22:15:47.780099
4158 22:15:47.780158 ==
4159 22:15:47.783068 Dram Type= 6, Freq= 0, CH_0, rank 0
4160 22:15:47.786257 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4161 22:15:47.786496 ==
4162 22:15:47.789970 RX Vref Scan: 1
4163 22:15:47.790138
4164 22:15:47.793360 RX Vref 0 -> 0, step: 1
4165 22:15:47.793534
4166 22:15:47.793617 RX Delay -179 -> 252, step: 8
4167 22:15:47.793690
4168 22:15:47.797159 Set Vref, RX VrefLevel [Byte0]: 57
4169 22:15:47.799936 [Byte1]: 50
4170 22:15:47.805192
4171 22:15:47.805390 Final RX Vref Byte 0 = 57 to rank0
4172 22:15:47.807471 Final RX Vref Byte 1 = 50 to rank0
4173 22:15:47.811089 Final RX Vref Byte 0 = 57 to rank1
4174 22:15:47.814308 Final RX Vref Byte 1 = 50 to rank1==
4175 22:15:47.817335 Dram Type= 6, Freq= 0, CH_0, rank 0
4176 22:15:47.825031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4177 22:15:47.825290 ==
4178 22:15:47.825444 DQS Delay:
4179 22:15:47.827208 DQS0 = 0, DQS1 = 0
4180 22:15:47.827387 DQM Delay:
4181 22:15:47.827526 DQM0 = 48, DQM1 = 39
4182 22:15:47.830634 DQ Delay:
4183 22:15:47.834465 DQ0 =44, DQ1 =52, DQ2 =44, DQ3 =44
4184 22:15:47.837680 DQ4 =48, DQ5 =36, DQ6 =60, DQ7 =56
4185 22:15:47.841303 DQ8 =36, DQ9 =28, DQ10 =36, DQ11 =32
4186 22:15:47.844158 DQ12 =44, DQ13 =40, DQ14 =52, DQ15 =44
4187 22:15:47.844656
4188 22:15:47.844968
4189 22:15:47.850911 [DQSOSCAuto] RK0, (LSB)MR18= 0x5752, (MSB)MR19= 0x808, tDQSOscB0 = 394 ps tDQSOscB1 = 393 ps
4190 22:15:47.854275 CH0 RK0: MR19=808, MR18=5752
4191 22:15:47.860818 CH0_RK0: MR19=0x808, MR18=0x5752, DQSOSC=393, MR23=63, INC=169, DEC=113
4192 22:15:47.861390
4193 22:15:47.864325 ----->DramcWriteLeveling(PI) begin...
4194 22:15:47.864902 ==
4195 22:15:47.867048 Dram Type= 6, Freq= 0, CH_0, rank 1
4196 22:15:47.871046 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4197 22:15:47.871618 ==
4198 22:15:47.873987 Write leveling (Byte 0): 33 => 33
4199 22:15:47.877109 Write leveling (Byte 1): 30 => 30
4200 22:15:47.880788 DramcWriteLeveling(PI) end<-----
4201 22:15:47.881355
4202 22:15:47.881850 ==
4203 22:15:47.883842 Dram Type= 6, Freq= 0, CH_0, rank 1
4204 22:15:47.887208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4205 22:15:47.891155 ==
4206 22:15:47.891704 [Gating] SW mode calibration
4207 22:15:47.900156 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4208 22:15:47.903832 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4209 22:15:47.907137 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4210 22:15:47.913463 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4211 22:15:47.916818 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4212 22:15:47.920430 0 9 12 | B1->B0 | 3131 3333 | 1 0 | (1 1) (0 1)
4213 22:15:47.926901 0 9 16 | B1->B0 | 2626 2323 | 0 0 | (1 1) (0 0)
4214 22:15:47.931506 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4215 22:15:47.933311 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4216 22:15:47.940030 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4217 22:15:47.942996 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4218 22:15:47.946967 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4219 22:15:47.953622 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4220 22:15:47.956424 0 10 12 | B1->B0 | 2a2a 3030 | 1 0 | (0 0) (0 0)
4221 22:15:47.960276 0 10 16 | B1->B0 | 4444 4646 | 1 0 | (1 1) (0 0)
4222 22:15:47.967109 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4223 22:15:47.970314 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4224 22:15:47.973029 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4225 22:15:47.980322 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4226 22:15:47.983162 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4227 22:15:47.986165 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4228 22:15:47.992863 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4229 22:15:47.995790 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4230 22:15:47.999720 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4231 22:15:48.006175 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4232 22:15:48.009194 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4233 22:15:48.012732 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4234 22:15:48.019823 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4235 22:15:48.022381 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4236 22:15:48.026186 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4237 22:15:48.033225 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4238 22:15:48.036007 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4239 22:15:48.038858 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4240 22:15:48.045682 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4241 22:15:48.049219 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4242 22:15:48.052412 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4243 22:15:48.058799 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4244 22:15:48.062584 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4245 22:15:48.065417 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4246 22:15:48.068740 Total UI for P1: 0, mck2ui 16
4247 22:15:48.072565 best dqsien dly found for B0: ( 0, 13, 12)
4248 22:15:48.075266 Total UI for P1: 0, mck2ui 16
4249 22:15:48.079152 best dqsien dly found for B1: ( 0, 13, 12)
4250 22:15:48.082423 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4251 22:15:48.085566 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4252 22:15:48.086134
4253 22:15:48.092205 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4254 22:15:48.095289 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4255 22:15:48.098706 [Gating] SW calibration Done
4256 22:15:48.099304 ==
4257 22:15:48.101565 Dram Type= 6, Freq= 0, CH_0, rank 1
4258 22:15:48.104990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4259 22:15:48.105513 ==
4260 22:15:48.105885 RX Vref Scan: 0
4261 22:15:48.106228
4262 22:15:48.108517 RX Vref 0 -> 0, step: 1
4263 22:15:48.109087
4264 22:15:48.111362 RX Delay -230 -> 252, step: 16
4265 22:15:48.115117 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4266 22:15:48.118070 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4267 22:15:48.125102 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4268 22:15:48.128471 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4269 22:15:48.132007 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4270 22:15:48.134825 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4271 22:15:48.141449 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4272 22:15:48.145024 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4273 22:15:48.148415 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4274 22:15:48.151747 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4275 22:15:48.157976 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4276 22:15:48.161472 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4277 22:15:48.164697 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4278 22:15:48.168016 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4279 22:15:48.175189 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4280 22:15:48.177778 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4281 22:15:48.178385 ==
4282 22:15:48.180610 Dram Type= 6, Freq= 0, CH_0, rank 1
4283 22:15:48.184311 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4284 22:15:48.184884 ==
4285 22:15:48.187640 DQS Delay:
4286 22:15:48.188209 DQS0 = 0, DQS1 = 0
4287 22:15:48.188582 DQM Delay:
4288 22:15:48.190797 DQM0 = 47, DQM1 = 41
4289 22:15:48.191369 DQ Delay:
4290 22:15:48.195196 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =41
4291 22:15:48.197394 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4292 22:15:48.201378 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =41
4293 22:15:48.203924 DQ12 =41, DQ13 =49, DQ14 =57, DQ15 =49
4294 22:15:48.204410
4295 22:15:48.204774
4296 22:15:48.205113 ==
4297 22:15:48.207338 Dram Type= 6, Freq= 0, CH_0, rank 1
4298 22:15:48.213940 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4299 22:15:48.214592 ==
4300 22:15:48.214977
4301 22:15:48.215320
4302 22:15:48.215645 TX Vref Scan disable
4303 22:15:48.218405 == TX Byte 0 ==
4304 22:15:48.220606 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4305 22:15:48.227494 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4306 22:15:48.228095 == TX Byte 1 ==
4307 22:15:48.230969 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4308 22:15:48.237151 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4309 22:15:48.237652 ==
4310 22:15:48.240870 Dram Type= 6, Freq= 0, CH_0, rank 1
4311 22:15:48.244097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4312 22:15:48.244571 ==
4313 22:15:48.244943
4314 22:15:48.245299
4315 22:15:48.247190 TX Vref Scan disable
4316 22:15:48.250291 == TX Byte 0 ==
4317 22:15:48.253875 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4318 22:15:48.257317 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4319 22:15:48.260721 == TX Byte 1 ==
4320 22:15:48.264000 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4321 22:15:48.268459 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4322 22:15:48.269023
4323 22:15:48.269392 [DATLAT]
4324 22:15:48.270588 Freq=600, CH0 RK1
4325 22:15:48.271061
4326 22:15:48.273785 DATLAT Default: 0x9
4327 22:15:48.274345 0, 0xFFFF, sum = 0
4328 22:15:48.277813 1, 0xFFFF, sum = 0
4329 22:15:48.278424 2, 0xFFFF, sum = 0
4330 22:15:48.280192 3, 0xFFFF, sum = 0
4331 22:15:48.280656 4, 0xFFFF, sum = 0
4332 22:15:48.283517 5, 0xFFFF, sum = 0
4333 22:15:48.283981 6, 0xFFFF, sum = 0
4334 22:15:48.287131 7, 0xFFFF, sum = 0
4335 22:15:48.287550 8, 0x0, sum = 1
4336 22:15:48.290101 9, 0x0, sum = 2
4337 22:15:48.290563 10, 0x0, sum = 3
4338 22:15:48.293374 11, 0x0, sum = 4
4339 22:15:48.293794 best_step = 9
4340 22:15:48.294117
4341 22:15:48.294459 ==
4342 22:15:48.296514 Dram Type= 6, Freq= 0, CH_0, rank 1
4343 22:15:48.300189 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4344 22:15:48.300602 ==
4345 22:15:48.303685 RX Vref Scan: 0
4346 22:15:48.304244
4347 22:15:48.306743 RX Vref 0 -> 0, step: 1
4348 22:15:48.307155
4349 22:15:48.307480 RX Delay -179 -> 252, step: 8
4350 22:15:48.314909 iDelay=205, Bit 0, Center 48 (-99 ~ 196) 296
4351 22:15:48.317840 iDelay=205, Bit 1, Center 48 (-99 ~ 196) 296
4352 22:15:48.320991 iDelay=205, Bit 2, Center 44 (-99 ~ 188) 288
4353 22:15:48.324519 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4354 22:15:48.330988 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4355 22:15:48.334820 iDelay=205, Bit 5, Center 40 (-107 ~ 188) 296
4356 22:15:48.337466 iDelay=205, Bit 6, Center 56 (-91 ~ 204) 296
4357 22:15:48.341069 iDelay=205, Bit 7, Center 52 (-91 ~ 196) 288
4358 22:15:48.344794 iDelay=205, Bit 8, Center 36 (-107 ~ 180) 288
4359 22:15:48.350829 iDelay=205, Bit 9, Center 28 (-115 ~ 172) 288
4360 22:15:48.354447 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4361 22:15:48.357652 iDelay=205, Bit 11, Center 36 (-107 ~ 180) 288
4362 22:15:48.360899 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4363 22:15:48.367644 iDelay=205, Bit 13, Center 44 (-99 ~ 188) 288
4364 22:15:48.371235 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4365 22:15:48.374202 iDelay=205, Bit 15, Center 48 (-99 ~ 196) 296
4366 22:15:48.374808 ==
4367 22:15:48.377195 Dram Type= 6, Freq= 0, CH_0, rank 1
4368 22:15:48.380652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4369 22:15:48.381216 ==
4370 22:15:48.384301 DQS Delay:
4371 22:15:48.384869 DQS0 = 0, DQS1 = 0
4372 22:15:48.387304 DQM Delay:
4373 22:15:48.387855 DQM0 = 47, DQM1 = 41
4374 22:15:48.388216 DQ Delay:
4375 22:15:48.390507 DQ0 =48, DQ1 =48, DQ2 =44, DQ3 =44
4376 22:15:48.393990 DQ4 =48, DQ5 =40, DQ6 =56, DQ7 =52
4377 22:15:48.397029 DQ8 =36, DQ9 =28, DQ10 =40, DQ11 =36
4378 22:15:48.400130 DQ12 =48, DQ13 =44, DQ14 =48, DQ15 =48
4379 22:15:48.400591
4380 22:15:48.403753
4381 22:15:48.410487 [DQSOSCAuto] RK1, (LSB)MR18= 0x602f, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 391 ps
4382 22:15:48.413997 CH0 RK1: MR19=808, MR18=602F
4383 22:15:48.419880 CH0_RK1: MR19=0x808, MR18=0x602F, DQSOSC=391, MR23=63, INC=171, DEC=114
4384 22:15:48.423324 [RxdqsGatingPostProcess] freq 600
4385 22:15:48.426841 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4386 22:15:48.430021 Pre-setting of DQS Precalculation
4387 22:15:48.436833 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4388 22:15:48.437409 ==
4389 22:15:48.440034 Dram Type= 6, Freq= 0, CH_1, rank 0
4390 22:15:48.443147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4391 22:15:48.443608 ==
4392 22:15:48.450046 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4393 22:15:48.453174 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4394 22:15:48.457208 [CA 0] Center 35 (5~66) winsize 62
4395 22:15:48.461295 [CA 1] Center 35 (5~66) winsize 62
4396 22:15:48.464200 [CA 2] Center 34 (3~65) winsize 63
4397 22:15:48.467101 [CA 3] Center 33 (3~64) winsize 62
4398 22:15:48.470993 [CA 4] Center 34 (3~65) winsize 63
4399 22:15:48.474117 [CA 5] Center 33 (3~64) winsize 62
4400 22:15:48.474716
4401 22:15:48.477286 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4402 22:15:48.477842
4403 22:15:48.480585 [CATrainingPosCal] consider 1 rank data
4404 22:15:48.484219 u2DelayCellTimex100 = 270/100 ps
4405 22:15:48.487692 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4406 22:15:48.493608 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4407 22:15:48.497267 CA2 delay=34 (3~65),Diff = 1 PI (9 cell)
4408 22:15:48.500689 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4409 22:15:48.503776 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4410 22:15:48.507178 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4411 22:15:48.507753
4412 22:15:48.510565 CA PerBit enable=1, Macro0, CA PI delay=33
4413 22:15:48.511137
4414 22:15:48.513690 [CBTSetCACLKResult] CA Dly = 33
4415 22:15:48.517260 CS Dly: 4 (0~35)
4416 22:15:48.517860 ==
4417 22:15:48.520076 Dram Type= 6, Freq= 0, CH_1, rank 1
4418 22:15:48.523900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4419 22:15:48.524486 ==
4420 22:15:48.529803 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4421 22:15:48.533405 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4422 22:15:48.538215 [CA 0] Center 35 (5~66) winsize 62
4423 22:15:48.540947 [CA 1] Center 35 (5~66) winsize 62
4424 22:15:48.544513 [CA 2] Center 34 (4~65) winsize 62
4425 22:15:48.547255 [CA 3] Center 34 (4~65) winsize 62
4426 22:15:48.550420 [CA 4] Center 34 (4~65) winsize 62
4427 22:15:48.553814 [CA 5] Center 34 (4~64) winsize 61
4428 22:15:48.554523
4429 22:15:48.557392 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4430 22:15:48.557862
4431 22:15:48.560413 [CATrainingPosCal] consider 2 rank data
4432 22:15:48.564112 u2DelayCellTimex100 = 270/100 ps
4433 22:15:48.567233 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4434 22:15:48.573547 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4435 22:15:48.577210 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4436 22:15:48.581048 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
4437 22:15:48.584530 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4438 22:15:48.587080 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4439 22:15:48.587659
4440 22:15:48.591393 CA PerBit enable=1, Macro0, CA PI delay=34
4441 22:15:48.591964
4442 22:15:48.593337 [CBTSetCACLKResult] CA Dly = 34
4443 22:15:48.593806 CS Dly: 5 (0~37)
4444 22:15:48.597206
4445 22:15:48.600367 ----->DramcWriteLeveling(PI) begin...
4446 22:15:48.600945 ==
4447 22:15:48.603386 Dram Type= 6, Freq= 0, CH_1, rank 0
4448 22:15:48.606637 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4449 22:15:48.607111 ==
4450 22:15:48.610158 Write leveling (Byte 0): 30 => 30
4451 22:15:48.613529 Write leveling (Byte 1): 31 => 31
4452 22:15:48.616854 DramcWriteLeveling(PI) end<-----
4453 22:15:48.617459
4454 22:15:48.617852 ==
4455 22:15:48.620123 Dram Type= 6, Freq= 0, CH_1, rank 0
4456 22:15:48.623293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4457 22:15:48.623871 ==
4458 22:15:48.627646 [Gating] SW mode calibration
4459 22:15:48.633598 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4460 22:15:48.640266 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4461 22:15:48.643739 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4462 22:15:48.646401 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4463 22:15:48.652841 0 9 8 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
4464 22:15:48.656477 0 9 12 | B1->B0 | 2d2d 2c2c | 0 0 | (0 0) (0 0)
4465 22:15:48.660019 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4466 22:15:48.666093 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4467 22:15:48.669739 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4468 22:15:48.672543 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4469 22:15:48.679217 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4470 22:15:48.682936 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4471 22:15:48.685887 0 10 8 | B1->B0 | 2525 2827 | 0 1 | (0 0) (0 0)
4472 22:15:48.692820 0 10 12 | B1->B0 | 3b3b 3e3e | 0 0 | (0 0) (0 0)
4473 22:15:48.695493 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4474 22:15:48.699182 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4475 22:15:48.705556 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4476 22:15:48.708882 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4477 22:15:48.711912 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4478 22:15:48.719070 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4479 22:15:48.722016 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4480 22:15:48.724916 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4481 22:15:48.731710 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4482 22:15:48.734919 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4483 22:15:48.738552 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4484 22:15:48.745051 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4485 22:15:48.747922 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4486 22:15:48.751258 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4487 22:15:48.757807 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4488 22:15:48.761160 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4489 22:15:48.764422 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4490 22:15:48.771299 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4491 22:15:48.775496 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4492 22:15:48.778248 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4493 22:15:48.784438 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4494 22:15:48.787878 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4495 22:15:48.791366 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4496 22:15:48.797668 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4497 22:15:48.798098 Total UI for P1: 0, mck2ui 16
4498 22:15:48.804405 best dqsien dly found for B1: ( 0, 13, 10)
4499 22:15:48.807659 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4500 22:15:48.810793 Total UI for P1: 0, mck2ui 16
4501 22:15:48.814493 best dqsien dly found for B0: ( 0, 13, 12)
4502 22:15:48.817862 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4503 22:15:48.821243 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4504 22:15:48.821545
4505 22:15:48.824052 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4506 22:15:48.830277 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4507 22:15:48.830482 [Gating] SW calibration Done
4508 22:15:48.830628 ==
4509 22:15:48.833605 Dram Type= 6, Freq= 0, CH_1, rank 0
4510 22:15:48.840579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4511 22:15:48.840735 ==
4512 22:15:48.840857 RX Vref Scan: 0
4513 22:15:48.840969
4514 22:15:48.843762 RX Vref 0 -> 0, step: 1
4515 22:15:48.843917
4516 22:15:48.847190 RX Delay -230 -> 252, step: 16
4517 22:15:48.850211 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4518 22:15:48.853130 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4519 22:15:48.859728 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4520 22:15:48.863199 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4521 22:15:48.866337 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4522 22:15:48.869598 iDelay=218, Bit 5, Center 57 (-86 ~ 201) 288
4523 22:15:48.872850 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4524 22:15:48.879551 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4525 22:15:48.882916 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4526 22:15:48.886288 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4527 22:15:48.889538 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4528 22:15:48.895998 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4529 22:15:48.899534 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4530 22:15:48.902689 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4531 22:15:48.905936 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4532 22:15:48.912813 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4533 22:15:48.913240 ==
4534 22:15:48.916297 Dram Type= 6, Freq= 0, CH_1, rank 0
4535 22:15:48.919692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4536 22:15:48.920119 ==
4537 22:15:48.920456 DQS Delay:
4538 22:15:48.923344 DQS0 = 0, DQS1 = 0
4539 22:15:48.923770 DQM Delay:
4540 22:15:48.926503 DQM0 = 51, DQM1 = 42
4541 22:15:48.926925 DQ Delay:
4542 22:15:48.930606 DQ0 =57, DQ1 =49, DQ2 =33, DQ3 =49
4543 22:15:48.933124 DQ4 =49, DQ5 =57, DQ6 =65, DQ7 =49
4544 22:15:48.936447 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =41
4545 22:15:48.939260 DQ12 =57, DQ13 =57, DQ14 =41, DQ15 =49
4546 22:15:48.939722
4547 22:15:48.940061
4548 22:15:48.940370 ==
4549 22:15:48.942908 Dram Type= 6, Freq= 0, CH_1, rank 0
4550 22:15:48.945753 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4551 22:15:48.946187 ==
4552 22:15:48.949695
4553 22:15:48.950125
4554 22:15:48.950499 TX Vref Scan disable
4555 22:15:48.952928 == TX Byte 0 ==
4556 22:15:48.955771 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4557 22:15:48.959179 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4558 22:15:48.962290 == TX Byte 1 ==
4559 22:15:48.965407 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4560 22:15:48.968668 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4561 22:15:48.972236 ==
4562 22:15:48.976003 Dram Type= 6, Freq= 0, CH_1, rank 0
4563 22:15:48.978832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4564 22:15:48.979032 ==
4565 22:15:48.979141
4566 22:15:48.979238
4567 22:15:48.981862 TX Vref Scan disable
4568 22:15:48.981996 == TX Byte 0 ==
4569 22:15:48.988755 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4570 22:15:48.992096 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4571 22:15:48.992232 == TX Byte 1 ==
4572 22:15:48.998998 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4573 22:15:49.001905 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4574 22:15:49.002338
4575 22:15:49.002707 [DATLAT]
4576 22:15:49.005236 Freq=600, CH1 RK0
4577 22:15:49.005669
4578 22:15:49.006100 DATLAT Default: 0x9
4579 22:15:49.008621 0, 0xFFFF, sum = 0
4580 22:15:49.009059 1, 0xFFFF, sum = 0
4581 22:15:49.012206 2, 0xFFFF, sum = 0
4582 22:15:49.012646 3, 0xFFFF, sum = 0
4583 22:15:49.015301 4, 0xFFFF, sum = 0
4584 22:15:49.018295 5, 0xFFFF, sum = 0
4585 22:15:49.018758 6, 0xFFFF, sum = 0
4586 22:15:49.021996 7, 0xFFFF, sum = 0
4587 22:15:49.022302 8, 0x0, sum = 1
4588 22:15:49.022576 9, 0x0, sum = 2
4589 22:15:49.024982 10, 0x0, sum = 3
4590 22:15:49.025307 11, 0x0, sum = 4
4591 22:15:49.028620 best_step = 9
4592 22:15:49.028995
4593 22:15:49.029262 ==
4594 22:15:49.031471 Dram Type= 6, Freq= 0, CH_1, rank 0
4595 22:15:49.034661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4596 22:15:49.034816 ==
4597 22:15:49.038260 RX Vref Scan: 1
4598 22:15:49.038476
4599 22:15:49.038673 RX Vref 0 -> 0, step: 1
4600 22:15:49.038841
4601 22:15:49.041520 RX Delay -179 -> 252, step: 8
4602 22:15:49.041660
4603 22:15:49.044562 Set Vref, RX VrefLevel [Byte0]: 51
4604 22:15:49.048218 [Byte1]: 50
4605 22:15:49.051903
4606 22:15:49.052021 Final RX Vref Byte 0 = 51 to rank0
4607 22:15:49.055561 Final RX Vref Byte 1 = 50 to rank0
4608 22:15:49.058654 Final RX Vref Byte 0 = 51 to rank1
4609 22:15:49.061959 Final RX Vref Byte 1 = 50 to rank1==
4610 22:15:49.065796 Dram Type= 6, Freq= 0, CH_1, rank 0
4611 22:15:49.071945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4612 22:15:49.072030 ==
4613 22:15:49.072096 DQS Delay:
4614 22:15:49.075241 DQS0 = 0, DQS1 = 0
4615 22:15:49.075323 DQM Delay:
4616 22:15:49.075389 DQM0 = 47, DQM1 = 40
4617 22:15:49.078820 DQ Delay:
4618 22:15:49.081607 DQ0 =52, DQ1 =40, DQ2 =36, DQ3 =44
4619 22:15:49.085027 DQ4 =48, DQ5 =56, DQ6 =56, DQ7 =44
4620 22:15:49.088851 DQ8 =28, DQ9 =28, DQ10 =44, DQ11 =36
4621 22:15:49.091881 DQ12 =48, DQ13 =48, DQ14 =44, DQ15 =48
4622 22:15:49.091965
4623 22:15:49.092029
4624 22:15:49.098241 [DQSOSCAuto] RK0, (LSB)MR18= 0x486f, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
4625 22:15:49.101141 CH1 RK0: MR19=808, MR18=486F
4626 22:15:49.108263 CH1_RK0: MR19=0x808, MR18=0x486F, DQSOSC=389, MR23=63, INC=173, DEC=115
4627 22:15:49.108347
4628 22:15:49.111825 ----->DramcWriteLeveling(PI) begin...
4629 22:15:49.111908 ==
4630 22:15:49.115142 Dram Type= 6, Freq= 0, CH_1, rank 1
4631 22:15:49.118194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4632 22:15:49.118359 ==
4633 22:15:49.121582 Write leveling (Byte 0): 32 => 32
4634 22:15:49.125364 Write leveling (Byte 1): 32 => 32
4635 22:15:49.128277 DramcWriteLeveling(PI) end<-----
4636 22:15:49.128473
4637 22:15:49.128572 ==
4638 22:15:49.131949 Dram Type= 6, Freq= 0, CH_1, rank 1
4639 22:15:49.134895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4640 22:15:49.138243 ==
4641 22:15:49.138477 [Gating] SW mode calibration
4642 22:15:49.148247 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4643 22:15:49.151856 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4644 22:15:49.154819 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4645 22:15:49.161921 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4646 22:15:49.164803 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4647 22:15:49.168221 0 9 12 | B1->B0 | 2828 3030 | 0 0 | (1 1) (0 0)
4648 22:15:49.174692 0 9 16 | B1->B0 | 2323 2727 | 0 1 | (0 0) (1 0)
4649 22:15:49.177893 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4650 22:15:49.180984 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4651 22:15:49.187603 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4652 22:15:49.190844 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4653 22:15:49.194567 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4654 22:15:49.200774 0 10 8 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
4655 22:15:49.204568 0 10 12 | B1->B0 | 3838 3232 | 0 0 | (0 0) (0 0)
4656 22:15:49.207376 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4657 22:15:49.214130 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4658 22:15:49.217469 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4659 22:15:49.220435 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4660 22:15:49.227462 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4661 22:15:49.230321 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4662 22:15:49.234044 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4663 22:15:49.240348 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4664 22:15:49.243721 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4665 22:15:49.246776 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4666 22:15:49.253750 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4667 22:15:49.257052 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4668 22:15:49.260390 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4669 22:15:49.266600 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4670 22:15:49.270184 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4671 22:15:49.273656 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4672 22:15:49.280092 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4673 22:15:49.283254 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4674 22:15:49.286975 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4675 22:15:49.293031 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4676 22:15:49.296760 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4677 22:15:49.299486 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4678 22:15:49.306030 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4679 22:15:49.310011 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4680 22:15:49.313034 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4681 22:15:49.316675 Total UI for P1: 0, mck2ui 16
4682 22:15:49.319993 best dqsien dly found for B0: ( 0, 13, 12)
4683 22:15:49.322794 Total UI for P1: 0, mck2ui 16
4684 22:15:49.326389 best dqsien dly found for B1: ( 0, 13, 12)
4685 22:15:49.330073 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4686 22:15:49.336388 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4687 22:15:49.336970
4688 22:15:49.339881 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4689 22:15:49.342972 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4690 22:15:49.346548 [Gating] SW calibration Done
4691 22:15:49.347125 ==
4692 22:15:49.349830 Dram Type= 6, Freq= 0, CH_1, rank 1
4693 22:15:49.352676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4694 22:15:49.353170 ==
4695 22:15:49.356584 RX Vref Scan: 0
4696 22:15:49.357203
4697 22:15:49.357587 RX Vref 0 -> 0, step: 1
4698 22:15:49.357940
4699 22:15:49.359751 RX Delay -230 -> 252, step: 16
4700 22:15:49.363071 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4701 22:15:49.369298 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4702 22:15:49.372794 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4703 22:15:49.376582 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4704 22:15:49.379556 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4705 22:15:49.382776 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4706 22:15:49.389221 iDelay=218, Bit 6, Center 57 (-86 ~ 201) 288
4707 22:15:49.392906 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4708 22:15:49.395834 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4709 22:15:49.398726 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4710 22:15:49.405577 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4711 22:15:49.408792 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4712 22:15:49.412166 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4713 22:15:49.415781 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4714 22:15:49.421716 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4715 22:15:49.425234 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4716 22:15:49.425814 ==
4717 22:15:49.428508 Dram Type= 6, Freq= 0, CH_1, rank 1
4718 22:15:49.431512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4719 22:15:49.432006 ==
4720 22:15:49.435202 DQS Delay:
4721 22:15:49.435805 DQS0 = 0, DQS1 = 0
4722 22:15:49.436298 DQM Delay:
4723 22:15:49.438473 DQM0 = 51, DQM1 = 46
4724 22:15:49.439050 DQ Delay:
4725 22:15:49.442011 DQ0 =57, DQ1 =49, DQ2 =33, DQ3 =49
4726 22:15:49.445139 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4727 22:15:49.448642 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4728 22:15:49.451819 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4729 22:15:49.452405
4730 22:15:49.452894
4731 22:15:49.453350 ==
4732 22:15:49.455012 Dram Type= 6, Freq= 0, CH_1, rank 1
4733 22:15:49.461949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4734 22:15:49.462461 ==
4735 22:15:49.462955
4736 22:15:49.463414
4737 22:15:49.463864 TX Vref Scan disable
4738 22:15:49.465446 == TX Byte 0 ==
4739 22:15:49.468808 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4740 22:15:49.475159 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4741 22:15:49.475740 == TX Byte 1 ==
4742 22:15:49.478402 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4743 22:15:49.485172 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4744 22:15:49.485756 ==
4745 22:15:49.488786 Dram Type= 6, Freq= 0, CH_1, rank 1
4746 22:15:49.492019 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4747 22:15:49.492607 ==
4748 22:15:49.493101
4749 22:15:49.493562
4750 22:15:49.494736 TX Vref Scan disable
4751 22:15:49.498150 == TX Byte 0 ==
4752 22:15:49.501818 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4753 22:15:49.504531 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4754 22:15:49.508553 == TX Byte 1 ==
4755 22:15:49.511830 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4756 22:15:49.514793 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4757 22:15:49.515380
4758 22:15:49.518094 [DATLAT]
4759 22:15:49.518737 Freq=600, CH1 RK1
4760 22:15:49.519263
4761 22:15:49.521260 DATLAT Default: 0x9
4762 22:15:49.521774 0, 0xFFFF, sum = 0
4763 22:15:49.524697 1, 0xFFFF, sum = 0
4764 22:15:49.525286 2, 0xFFFF, sum = 0
4765 22:15:49.528779 3, 0xFFFF, sum = 0
4766 22:15:49.529373 4, 0xFFFF, sum = 0
4767 22:15:49.531138 5, 0xFFFF, sum = 0
4768 22:15:49.531635 6, 0xFFFF, sum = 0
4769 22:15:49.534267 7, 0xFFFF, sum = 0
4770 22:15:49.534836 8, 0x0, sum = 1
4771 22:15:49.538006 9, 0x0, sum = 2
4772 22:15:49.538561 10, 0x0, sum = 3
4773 22:15:49.540978 11, 0x0, sum = 4
4774 22:15:49.541475 best_step = 9
4775 22:15:49.541960
4776 22:15:49.542454 ==
4777 22:15:49.544340 Dram Type= 6, Freq= 0, CH_1, rank 1
4778 22:15:49.548239 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4779 22:15:49.548820 ==
4780 22:15:49.550671 RX Vref Scan: 0
4781 22:15:49.551135
4782 22:15:49.554308 RX Vref 0 -> 0, step: 1
4783 22:15:49.554910
4784 22:15:49.557293 RX Delay -163 -> 252, step: 8
4785 22:15:49.560620 iDelay=205, Bit 0, Center 48 (-91 ~ 188) 280
4786 22:15:49.564004 iDelay=205, Bit 1, Center 40 (-99 ~ 180) 280
4787 22:15:49.570793 iDelay=205, Bit 2, Center 40 (-99 ~ 180) 280
4788 22:15:49.574160 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4789 22:15:49.577288 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4790 22:15:49.580674 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4791 22:15:49.583726 iDelay=205, Bit 6, Center 52 (-91 ~ 196) 288
4792 22:15:49.590404 iDelay=205, Bit 7, Center 48 (-91 ~ 188) 280
4793 22:15:49.593824 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4794 22:15:49.597204 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4795 22:15:49.600456 iDelay=205, Bit 10, Center 44 (-99 ~ 188) 288
4796 22:15:49.606786 iDelay=205, Bit 11, Center 36 (-107 ~ 180) 288
4797 22:15:49.610128 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4798 22:15:49.613590 iDelay=205, Bit 13, Center 48 (-99 ~ 196) 296
4799 22:15:49.617808 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4800 22:15:49.619989 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4801 22:15:49.623188 ==
4802 22:15:49.626471 Dram Type= 6, Freq= 0, CH_1, rank 1
4803 22:15:49.630436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4804 22:15:49.630925 ==
4805 22:15:49.631406 DQS Delay:
4806 22:15:49.633863 DQS0 = 0, DQS1 = 0
4807 22:15:49.634503 DQM Delay:
4808 22:15:49.636767 DQM0 = 47, DQM1 = 43
4809 22:15:49.637252 DQ Delay:
4810 22:15:49.639710 DQ0 =48, DQ1 =40, DQ2 =40, DQ3 =44
4811 22:15:49.643591 DQ4 =48, DQ5 =60, DQ6 =52, DQ7 =48
4812 22:15:49.646265 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =36
4813 22:15:49.649754 DQ12 =48, DQ13 =48, DQ14 =48, DQ15 =56
4814 22:15:49.650347
4815 22:15:49.650883
4816 22:15:49.656436 [DQSOSCAuto] RK1, (LSB)MR18= 0x571e, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 393 ps
4817 22:15:49.659555 CH1 RK1: MR19=808, MR18=571E
4818 22:15:49.666584 CH1_RK1: MR19=0x808, MR18=0x571E, DQSOSC=393, MR23=63, INC=169, DEC=113
4819 22:15:49.669656 [RxdqsGatingPostProcess] freq 600
4820 22:15:49.676696 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4821 22:15:49.679542 Pre-setting of DQS Precalculation
4822 22:15:49.682923 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4823 22:15:49.689388 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4824 22:15:49.696013 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4825 22:15:49.696599
4826 22:15:49.696973
4827 22:15:49.698969 [Calibration Summary] 1200 Mbps
4828 22:15:49.702608 CH 0, Rank 0
4829 22:15:49.703188 SW Impedance : PASS
4830 22:15:49.705894 DUTY Scan : NO K
4831 22:15:49.709251 ZQ Calibration : PASS
4832 22:15:49.709727 Jitter Meter : NO K
4833 22:15:49.712295 CBT Training : PASS
4834 22:15:49.715746 Write leveling : PASS
4835 22:15:49.716342 RX DQS gating : PASS
4836 22:15:49.718747 RX DQ/DQS(RDDQC) : PASS
4837 22:15:49.722557 TX DQ/DQS : PASS
4838 22:15:49.723125 RX DATLAT : PASS
4839 22:15:49.725589 RX DQ/DQS(Engine): PASS
4840 22:15:49.729148 TX OE : NO K
4841 22:15:49.729733 All Pass.
4842 22:15:49.730114
4843 22:15:49.730494 CH 0, Rank 1
4844 22:15:49.732383 SW Impedance : PASS
4845 22:15:49.735514 DUTY Scan : NO K
4846 22:15:49.735990 ZQ Calibration : PASS
4847 22:15:49.739052 Jitter Meter : NO K
4848 22:15:49.739528 CBT Training : PASS
4849 22:15:49.742465 Write leveling : PASS
4850 22:15:49.745386 RX DQS gating : PASS
4851 22:15:49.746073 RX DQ/DQS(RDDQC) : PASS
4852 22:15:49.748787 TX DQ/DQS : PASS
4853 22:15:49.752146 RX DATLAT : PASS
4854 22:15:49.752719 RX DQ/DQS(Engine): PASS
4855 22:15:49.756061 TX OE : NO K
4856 22:15:49.756630 All Pass.
4857 22:15:49.757009
4858 22:15:49.758612 CH 1, Rank 0
4859 22:15:49.759091 SW Impedance : PASS
4860 22:15:49.761762 DUTY Scan : NO K
4861 22:15:49.765949 ZQ Calibration : PASS
4862 22:15:49.766561 Jitter Meter : NO K
4863 22:15:49.768773 CBT Training : PASS
4864 22:15:49.772034 Write leveling : PASS
4865 22:15:49.772604 RX DQS gating : PASS
4866 22:15:49.775880 RX DQ/DQS(RDDQC) : PASS
4867 22:15:49.778472 TX DQ/DQS : PASS
4868 22:15:49.778951 RX DATLAT : PASS
4869 22:15:49.781821 RX DQ/DQS(Engine): PASS
4870 22:15:49.785141 TX OE : NO K
4871 22:15:49.785717 All Pass.
4872 22:15:49.786094
4873 22:15:49.786478 CH 1, Rank 1
4874 22:15:49.788456 SW Impedance : PASS
4875 22:15:49.791982 DUTY Scan : NO K
4876 22:15:49.792554 ZQ Calibration : PASS
4877 22:15:49.795204 Jitter Meter : NO K
4878 22:15:49.798261 CBT Training : PASS
4879 22:15:49.798875 Write leveling : PASS
4880 22:15:49.801565 RX DQS gating : PASS
4881 22:15:49.805504 RX DQ/DQS(RDDQC) : PASS
4882 22:15:49.806075 TX DQ/DQS : PASS
4883 22:15:49.808057 RX DATLAT : PASS
4884 22:15:49.808532 RX DQ/DQS(Engine): PASS
4885 22:15:49.811370 TX OE : NO K
4886 22:15:49.811942 All Pass.
4887 22:15:49.812326
4888 22:15:49.814701 DramC Write-DBI off
4889 22:15:49.818119 PER_BANK_REFRESH: Hybrid Mode
4890 22:15:49.818718 TX_TRACKING: ON
4891 22:15:49.828592 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4892 22:15:49.831173 [FAST_K] Save calibration result to emmc
4893 22:15:49.834465 dramc_set_vcore_voltage set vcore to 662500
4894 22:15:49.837969 Read voltage for 933, 3
4895 22:15:49.838592 Vio18 = 0
4896 22:15:49.841180 Vcore = 662500
4897 22:15:49.841656 Vdram = 0
4898 22:15:49.842027 Vddq = 0
4899 22:15:49.842415 Vmddr = 0
4900 22:15:49.847493 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4901 22:15:49.854520 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4902 22:15:49.855098 MEM_TYPE=3, freq_sel=17
4903 22:15:49.857397 sv_algorithm_assistance_LP4_1600
4904 22:15:49.860532 ============ PULL DRAM RESETB DOWN ============
4905 22:15:49.867792 ========== PULL DRAM RESETB DOWN end =========
4906 22:15:49.871045 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4907 22:15:49.875236 ===================================
4908 22:15:49.877988 LPDDR4 DRAM CONFIGURATION
4909 22:15:49.881343 ===================================
4910 22:15:49.881916 EX_ROW_EN[0] = 0x0
4911 22:15:49.884196 EX_ROW_EN[1] = 0x0
4912 22:15:49.884772 LP4Y_EN = 0x0
4913 22:15:49.887773 WORK_FSP = 0x0
4914 22:15:49.891106 WL = 0x3
4915 22:15:49.891675 RL = 0x3
4916 22:15:49.894068 BL = 0x2
4917 22:15:49.894686 RPST = 0x0
4918 22:15:49.897603 RD_PRE = 0x0
4919 22:15:49.898173 WR_PRE = 0x1
4920 22:15:49.900372 WR_PST = 0x0
4921 22:15:49.900850 DBI_WR = 0x0
4922 22:15:49.904369 DBI_RD = 0x0
4923 22:15:49.904941 OTF = 0x1
4924 22:15:49.907106 ===================================
4925 22:15:49.910567 ===================================
4926 22:15:49.913892 ANA top config
4927 22:15:49.917191 ===================================
4928 22:15:49.917759 DLL_ASYNC_EN = 0
4929 22:15:49.920176 ALL_SLAVE_EN = 1
4930 22:15:49.923803 NEW_RANK_MODE = 1
4931 22:15:49.927116 DLL_IDLE_MODE = 1
4932 22:15:49.930635 LP45_APHY_COMB_EN = 1
4933 22:15:49.931222 TX_ODT_DIS = 1
4934 22:15:49.933308 NEW_8X_MODE = 1
4935 22:15:49.936830 ===================================
4936 22:15:49.940002 ===================================
4937 22:15:49.943030 data_rate = 1866
4938 22:15:49.946790 CKR = 1
4939 22:15:49.950486 DQ_P2S_RATIO = 8
4940 22:15:49.953831 ===================================
4941 22:15:49.954478 CA_P2S_RATIO = 8
4942 22:15:49.956537 DQ_CA_OPEN = 0
4943 22:15:49.960043 DQ_SEMI_OPEN = 0
4944 22:15:49.963590 CA_SEMI_OPEN = 0
4945 22:15:49.966533 CA_FULL_RATE = 0
4946 22:15:49.970272 DQ_CKDIV4_EN = 1
4947 22:15:49.970890 CA_CKDIV4_EN = 1
4948 22:15:49.973203 CA_PREDIV_EN = 0
4949 22:15:49.976644 PH8_DLY = 0
4950 22:15:49.980832 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4951 22:15:49.983453 DQ_AAMCK_DIV = 4
4952 22:15:49.987258 CA_AAMCK_DIV = 4
4953 22:15:49.987828 CA_ADMCK_DIV = 4
4954 22:15:49.989851 DQ_TRACK_CA_EN = 0
4955 22:15:49.993160 CA_PICK = 933
4956 22:15:49.997338 CA_MCKIO = 933
4957 22:15:49.999777 MCKIO_SEMI = 0
4958 22:15:50.003309 PLL_FREQ = 3732
4959 22:15:50.006612 DQ_UI_PI_RATIO = 32
4960 22:15:50.007186 CA_UI_PI_RATIO = 0
4961 22:15:50.009381 ===================================
4962 22:15:50.012990 ===================================
4963 22:15:50.016403 memory_type:LPDDR4
4964 22:15:50.020109 GP_NUM : 10
4965 22:15:50.020685 SRAM_EN : 1
4966 22:15:50.023021 MD32_EN : 0
4967 22:15:50.026198 ===================================
4968 22:15:50.029658 [ANA_INIT] >>>>>>>>>>>>>>
4969 22:15:50.033118 <<<<<< [CONFIGURE PHASE]: ANA_TX
4970 22:15:50.035899 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4971 22:15:50.039253 ===================================
4972 22:15:50.042516 data_rate = 1866,PCW = 0X8f00
4973 22:15:50.045928 ===================================
4974 22:15:50.048833 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4975 22:15:50.052497 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4976 22:15:50.058968 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4977 22:15:50.062326 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4978 22:15:50.065730 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4979 22:15:50.069438 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4980 22:15:50.072420 [ANA_INIT] flow start
4981 22:15:50.076614 [ANA_INIT] PLL >>>>>>>>
4982 22:15:50.077181 [ANA_INIT] PLL <<<<<<<<
4983 22:15:50.078902 [ANA_INIT] MIDPI >>>>>>>>
4984 22:15:50.082486 [ANA_INIT] MIDPI <<<<<<<<
4985 22:15:50.085922 [ANA_INIT] DLL >>>>>>>>
4986 22:15:50.086525 [ANA_INIT] flow end
4987 22:15:50.088778 ============ LP4 DIFF to SE enter ============
4988 22:15:50.095032 ============ LP4 DIFF to SE exit ============
4989 22:15:50.095594 [ANA_INIT] <<<<<<<<<<<<<
4990 22:15:50.099033 [Flow] Enable top DCM control >>>>>
4991 22:15:50.101984 [Flow] Enable top DCM control <<<<<
4992 22:15:50.105232 Enable DLL master slave shuffle
4993 22:15:50.112217 ==============================================================
4994 22:15:50.112787 Gating Mode config
4995 22:15:50.118729 ==============================================================
4996 22:15:50.121866 Config description:
4997 22:15:50.131762 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4998 22:15:50.138216 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4999 22:15:50.141283 SELPH_MODE 0: By rank 1: By Phase
5000 22:15:50.148151 ==============================================================
5001 22:15:50.151440 GAT_TRACK_EN = 1
5002 22:15:50.154755 RX_GATING_MODE = 2
5003 22:15:50.157863 RX_GATING_TRACK_MODE = 2
5004 22:15:50.158411 SELPH_MODE = 1
5005 22:15:50.161789 PICG_EARLY_EN = 1
5006 22:15:50.164989 VALID_LAT_VALUE = 1
5007 22:15:50.170997 ==============================================================
5008 22:15:50.174125 Enter into Gating configuration >>>>
5009 22:15:50.177381 Exit from Gating configuration <<<<
5010 22:15:50.180901 Enter into DVFS_PRE_config >>>>>
5011 22:15:50.190914 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5012 22:15:50.194139 Exit from DVFS_PRE_config <<<<<
5013 22:15:50.197333 Enter into PICG configuration >>>>
5014 22:15:50.200952 Exit from PICG configuration <<<<
5015 22:15:50.204256 [RX_INPUT] configuration >>>>>
5016 22:15:50.207050 [RX_INPUT] configuration <<<<<
5017 22:15:50.211002 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5018 22:15:50.217689 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5019 22:15:50.223970 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5020 22:15:50.230510 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5021 22:15:50.237918 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5022 22:15:50.240381 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5023 22:15:50.247022 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5024 22:15:50.250183 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5025 22:15:50.253324 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5026 22:15:50.257256 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5027 22:15:50.263295 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5028 22:15:50.266734 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5029 22:15:50.270576 ===================================
5030 22:15:50.273564 LPDDR4 DRAM CONFIGURATION
5031 22:15:50.276832 ===================================
5032 22:15:50.277422 EX_ROW_EN[0] = 0x0
5033 22:15:50.280221 EX_ROW_EN[1] = 0x0
5034 22:15:50.280800 LP4Y_EN = 0x0
5035 22:15:50.283438 WORK_FSP = 0x0
5036 22:15:50.284027 WL = 0x3
5037 22:15:50.286732 RL = 0x3
5038 22:15:50.291237 BL = 0x2
5039 22:15:50.291814 RPST = 0x0
5040 22:15:50.292883 RD_PRE = 0x0
5041 22:15:50.293355 WR_PRE = 0x1
5042 22:15:50.296397 WR_PST = 0x0
5043 22:15:50.296973 DBI_WR = 0x0
5044 22:15:50.299623 DBI_RD = 0x0
5045 22:15:50.300195 OTF = 0x1
5046 22:15:50.303091 ===================================
5047 22:15:50.306207 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5048 22:15:50.313018 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5049 22:15:50.316472 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5050 22:15:50.319619 ===================================
5051 22:15:50.323128 LPDDR4 DRAM CONFIGURATION
5052 22:15:50.326495 ===================================
5053 22:15:50.327070 EX_ROW_EN[0] = 0x10
5054 22:15:50.329831 EX_ROW_EN[1] = 0x0
5055 22:15:50.330432 LP4Y_EN = 0x0
5056 22:15:50.332975 WORK_FSP = 0x0
5057 22:15:50.333447 WL = 0x3
5058 22:15:50.336498 RL = 0x3
5059 22:15:50.339474 BL = 0x2
5060 22:15:50.340046 RPST = 0x0
5061 22:15:50.343029 RD_PRE = 0x0
5062 22:15:50.343501 WR_PRE = 0x1
5063 22:15:50.346190 WR_PST = 0x0
5064 22:15:50.346818 DBI_WR = 0x0
5065 22:15:50.349244 DBI_RD = 0x0
5066 22:15:50.349729 OTF = 0x1
5067 22:15:50.352594 ===================================
5068 22:15:50.359229 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5069 22:15:50.363014 nWR fixed to 30
5070 22:15:50.366718 [ModeRegInit_LP4] CH0 RK0
5071 22:15:50.367297 [ModeRegInit_LP4] CH0 RK1
5072 22:15:50.369683 [ModeRegInit_LP4] CH1 RK0
5073 22:15:50.373817 [ModeRegInit_LP4] CH1 RK1
5074 22:15:50.374446 match AC timing 9
5075 22:15:50.379980 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5076 22:15:50.383026 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5077 22:15:50.386271 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5078 22:15:50.393210 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5079 22:15:50.396396 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5080 22:15:50.396972 ==
5081 22:15:50.399528 Dram Type= 6, Freq= 0, CH_0, rank 0
5082 22:15:50.402806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5083 22:15:50.403282 ==
5084 22:15:50.409539 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5085 22:15:50.416263 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5086 22:15:50.419557 [CA 0] Center 37 (7~68) winsize 62
5087 22:15:50.423069 [CA 1] Center 38 (7~69) winsize 63
5088 22:15:50.426048 [CA 2] Center 35 (5~65) winsize 61
5089 22:15:50.429411 [CA 3] Center 35 (5~65) winsize 61
5090 22:15:50.432714 [CA 4] Center 34 (4~65) winsize 62
5091 22:15:50.436007 [CA 5] Center 33 (3~64) winsize 62
5092 22:15:50.436577
5093 22:15:50.439747 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5094 22:15:50.440324
5095 22:15:50.442467 [CATrainingPosCal] consider 1 rank data
5096 22:15:50.445813 u2DelayCellTimex100 = 270/100 ps
5097 22:15:50.449073 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5098 22:15:50.452568 CA1 delay=38 (7~69),Diff = 5 PI (31 cell)
5099 22:15:50.455934 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5100 22:15:50.458961 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5101 22:15:50.465661 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5102 22:15:50.469233 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5103 22:15:50.469806
5104 22:15:50.472287 CA PerBit enable=1, Macro0, CA PI delay=33
5105 22:15:50.472868
5106 22:15:50.475951 [CBTSetCACLKResult] CA Dly = 33
5107 22:15:50.476527 CS Dly: 6 (0~37)
5108 22:15:50.476901 ==
5109 22:15:50.478786 Dram Type= 6, Freq= 0, CH_0, rank 1
5110 22:15:50.485582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5111 22:15:50.486056 ==
5112 22:15:50.488808 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5113 22:15:50.495633 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5114 22:15:50.498523 [CA 0] Center 38 (8~69) winsize 62
5115 22:15:50.502267 [CA 1] Center 38 (8~69) winsize 62
5116 22:15:50.505045 [CA 2] Center 36 (6~66) winsize 61
5117 22:15:50.508461 [CA 3] Center 35 (5~66) winsize 62
5118 22:15:50.511598 [CA 4] Center 34 (4~65) winsize 62
5119 22:15:50.516390 [CA 5] Center 34 (4~65) winsize 62
5120 22:15:50.516970
5121 22:15:50.518417 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5122 22:15:50.518892
5123 22:15:50.522301 [CATrainingPosCal] consider 2 rank data
5124 22:15:50.525135 u2DelayCellTimex100 = 270/100 ps
5125 22:15:50.528920 CA0 delay=38 (8~68),Diff = 4 PI (24 cell)
5126 22:15:50.531757 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5127 22:15:50.538991 CA2 delay=35 (6~65),Diff = 1 PI (6 cell)
5128 22:15:50.541770 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5129 22:15:50.545058 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5130 22:15:50.548304 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5131 22:15:50.548885
5132 22:15:50.551861 CA PerBit enable=1, Macro0, CA PI delay=34
5133 22:15:50.552440
5134 22:15:50.555078 [CBTSetCACLKResult] CA Dly = 34
5135 22:15:50.555658 CS Dly: 7 (0~39)
5136 22:15:50.556036
5137 22:15:50.558732 ----->DramcWriteLeveling(PI) begin...
5138 22:15:50.561597 ==
5139 22:15:50.565152 Dram Type= 6, Freq= 0, CH_0, rank 0
5140 22:15:50.568309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5141 22:15:50.568888 ==
5142 22:15:50.571182 Write leveling (Byte 0): 35 => 35
5143 22:15:50.574743 Write leveling (Byte 1): 29 => 29
5144 22:15:50.578518 DramcWriteLeveling(PI) end<-----
5145 22:15:50.579091
5146 22:15:50.579464 ==
5147 22:15:50.581203 Dram Type= 6, Freq= 0, CH_0, rank 0
5148 22:15:50.584787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5149 22:15:50.585366 ==
5150 22:15:50.588158 [Gating] SW mode calibration
5151 22:15:50.594428 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5152 22:15:50.601229 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5153 22:15:50.605122 0 14 0 | B1->B0 | 3131 3434 | 1 1 | (0 0) (1 1)
5154 22:15:50.607555 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5155 22:15:50.614478 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5156 22:15:50.617989 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5157 22:15:50.621123 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5158 22:15:50.628052 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5159 22:15:50.631293 0 14 24 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
5160 22:15:50.634629 0 14 28 | B1->B0 | 3131 2323 | 0 0 | (0 0) (0 0)
5161 22:15:50.641181 0 15 0 | B1->B0 | 2a2a 2323 | 0 0 | (0 1) (0 0)
5162 22:15:50.644069 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5163 22:15:50.647283 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5164 22:15:50.654465 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5165 22:15:50.657552 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5166 22:15:50.660642 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5167 22:15:50.667282 0 15 24 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
5168 22:15:50.670609 0 15 28 | B1->B0 | 2525 4444 | 0 0 | (0 0) (0 0)
5169 22:15:50.673937 1 0 0 | B1->B0 | 4444 4646 | 1 0 | (0 0) (0 0)
5170 22:15:50.680368 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5171 22:15:50.683848 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5172 22:15:50.687167 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5173 22:15:50.693804 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5174 22:15:50.697269 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5175 22:15:50.700512 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5176 22:15:50.706776 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5177 22:15:50.710008 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5178 22:15:50.713498 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5179 22:15:50.720034 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5180 22:15:50.723376 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5181 22:15:50.726574 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5182 22:15:50.733346 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5183 22:15:50.736686 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5184 22:15:50.739867 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5185 22:15:50.746722 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5186 22:15:50.749609 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5187 22:15:50.753367 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5188 22:15:50.759474 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5189 22:15:50.763003 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5190 22:15:50.766251 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5191 22:15:50.773082 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5192 22:15:50.776393 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5193 22:15:50.779687 Total UI for P1: 0, mck2ui 16
5194 22:15:50.782957 best dqsien dly found for B0: ( 1, 2, 26)
5195 22:15:50.786308 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5196 22:15:50.789598 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5197 22:15:50.792833 Total UI for P1: 0, mck2ui 16
5198 22:15:50.796095 best dqsien dly found for B1: ( 1, 2, 30)
5199 22:15:50.799164 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5200 22:15:50.805875 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5201 22:15:50.806392
5202 22:15:50.809355 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5203 22:15:50.812419 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5204 22:15:50.816202 [Gating] SW calibration Done
5205 22:15:50.816766 ==
5206 22:15:50.818859 Dram Type= 6, Freq= 0, CH_0, rank 0
5207 22:15:50.822248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5208 22:15:50.822755 ==
5209 22:15:50.825692 RX Vref Scan: 0
5210 22:15:50.826252
5211 22:15:50.826694 RX Vref 0 -> 0, step: 1
5212 22:15:50.827042
5213 22:15:50.829647 RX Delay -80 -> 252, step: 8
5214 22:15:50.832973 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5215 22:15:50.839059 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5216 22:15:50.842234 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5217 22:15:50.845570 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5218 22:15:50.848844 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5219 22:15:50.852661 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5220 22:15:50.855394 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5221 22:15:50.861979 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5222 22:15:50.865601 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5223 22:15:50.868977 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5224 22:15:50.871944 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5225 22:15:50.875874 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5226 22:15:50.878635 iDelay=208, Bit 12, Center 95 (8 ~ 183) 176
5227 22:15:50.885321 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5228 22:15:50.888669 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5229 22:15:50.891817 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5230 22:15:50.892386 ==
5231 22:15:50.895237 Dram Type= 6, Freq= 0, CH_0, rank 0
5232 22:15:50.898479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5233 22:15:50.899078 ==
5234 22:15:50.901683 DQS Delay:
5235 22:15:50.902253 DQS0 = 0, DQS1 = 0
5236 22:15:50.905194 DQM Delay:
5237 22:15:50.905664 DQM0 = 105, DQM1 = 90
5238 22:15:50.908281 DQ Delay:
5239 22:15:50.908749 DQ0 =107, DQ1 =107, DQ2 =99, DQ3 =99
5240 22:15:50.914889 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =115
5241 22:15:50.915448 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5242 22:15:50.921216 DQ12 =95, DQ13 =91, DQ14 =99, DQ15 =99
5243 22:15:50.921774
5244 22:15:50.922203
5245 22:15:50.922611 ==
5246 22:15:50.924628 Dram Type= 6, Freq= 0, CH_0, rank 0
5247 22:15:50.928454 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5248 22:15:50.929025 ==
5249 22:15:50.929402
5250 22:15:50.929745
5251 22:15:50.931670 TX Vref Scan disable
5252 22:15:50.932239 == TX Byte 0 ==
5253 22:15:50.938127 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5254 22:15:50.941238 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5255 22:15:50.941810 == TX Byte 1 ==
5256 22:15:50.947668 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5257 22:15:50.951060 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5258 22:15:50.951650 ==
5259 22:15:50.954063 Dram Type= 6, Freq= 0, CH_0, rank 0
5260 22:15:50.957632 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5261 22:15:50.958205 ==
5262 22:15:50.960890
5263 22:15:50.961453
5264 22:15:50.961884 TX Vref Scan disable
5265 22:15:50.965086 == TX Byte 0 ==
5266 22:15:50.967637 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5267 22:15:50.974256 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5268 22:15:50.974888 == TX Byte 1 ==
5269 22:15:50.978135 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5270 22:15:50.984114 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5271 22:15:50.984686
5272 22:15:50.985057 [DATLAT]
5273 22:15:50.985402 Freq=933, CH0 RK0
5274 22:15:50.985730
5275 22:15:50.987323 DATLAT Default: 0xd
5276 22:15:50.987818 0, 0xFFFF, sum = 0
5277 22:15:50.990882 1, 0xFFFF, sum = 0
5278 22:15:50.993969 2, 0xFFFF, sum = 0
5279 22:15:50.994614 3, 0xFFFF, sum = 0
5280 22:15:50.997812 4, 0xFFFF, sum = 0
5281 22:15:50.998431 5, 0xFFFF, sum = 0
5282 22:15:51.000959 6, 0xFFFF, sum = 0
5283 22:15:51.001540 7, 0xFFFF, sum = 0
5284 22:15:51.003818 8, 0xFFFF, sum = 0
5285 22:15:51.004313 9, 0xFFFF, sum = 0
5286 22:15:51.007146 10, 0x0, sum = 1
5287 22:15:51.007624 11, 0x0, sum = 2
5288 22:15:51.010207 12, 0x0, sum = 3
5289 22:15:51.010856 13, 0x0, sum = 4
5290 22:15:51.011249 best_step = 11
5291 22:15:51.013987
5292 22:15:51.014649 ==
5293 22:15:51.017020 Dram Type= 6, Freq= 0, CH_0, rank 0
5294 22:15:51.020781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5295 22:15:51.021356 ==
5296 22:15:51.021723 RX Vref Scan: 1
5297 22:15:51.022111
5298 22:15:51.024211 RX Vref 0 -> 0, step: 1
5299 22:15:51.024817
5300 22:15:51.026977 RX Delay -53 -> 252, step: 4
5301 22:15:51.027449
5302 22:15:51.030514 Set Vref, RX VrefLevel [Byte0]: 57
5303 22:15:51.033570 [Byte1]: 50
5304 22:15:51.034198
5305 22:15:51.036978 Final RX Vref Byte 0 = 57 to rank0
5306 22:15:51.040260 Final RX Vref Byte 1 = 50 to rank0
5307 22:15:51.044093 Final RX Vref Byte 0 = 57 to rank1
5308 22:15:51.047275 Final RX Vref Byte 1 = 50 to rank1==
5309 22:15:51.050190 Dram Type= 6, Freq= 0, CH_0, rank 0
5310 22:15:51.056859 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5311 22:15:51.057460 ==
5312 22:15:51.057841 DQS Delay:
5313 22:15:51.058186 DQS0 = 0, DQS1 = 0
5314 22:15:51.060206 DQM Delay:
5315 22:15:51.060781 DQM0 = 106, DQM1 = 93
5316 22:15:51.063776 DQ Delay:
5317 22:15:51.066869 DQ0 =106, DQ1 =106, DQ2 =102, DQ3 =106
5318 22:15:51.069986 DQ4 =106, DQ5 =98, DQ6 =116, DQ7 =114
5319 22:15:51.074001 DQ8 =88, DQ9 =80, DQ10 =94, DQ11 =92
5320 22:15:51.076497 DQ12 =96, DQ13 =94, DQ14 =100, DQ15 =100
5321 22:15:51.077068
5322 22:15:51.077436
5323 22:15:51.083232 [DQSOSCAuto] RK0, (LSB)MR18= 0x211d, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 411 ps
5324 22:15:51.086769 CH0 RK0: MR19=505, MR18=211D
5325 22:15:51.093099 CH0_RK0: MR19=0x505, MR18=0x211D, DQSOSC=411, MR23=63, INC=64, DEC=42
5326 22:15:51.093672
5327 22:15:51.096398 ----->DramcWriteLeveling(PI) begin...
5328 22:15:51.096981 ==
5329 22:15:51.099299 Dram Type= 6, Freq= 0, CH_0, rank 1
5330 22:15:51.102985 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5331 22:15:51.105989 ==
5332 22:15:51.106476 Write leveling (Byte 0): 33 => 33
5333 22:15:51.109269 Write leveling (Byte 1): 29 => 29
5334 22:15:51.112676 DramcWriteLeveling(PI) end<-----
5335 22:15:51.113134
5336 22:15:51.113489 ==
5337 22:15:51.115915 Dram Type= 6, Freq= 0, CH_0, rank 1
5338 22:15:51.122721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5339 22:15:51.123209 ==
5340 22:15:51.123573 [Gating] SW mode calibration
5341 22:15:51.132458 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5342 22:15:51.136086 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5343 22:15:51.142614 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5344 22:15:51.146194 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5345 22:15:51.149082 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5346 22:15:51.155902 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5347 22:15:51.159869 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5348 22:15:51.162210 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5349 22:15:51.169277 0 14 24 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
5350 22:15:51.172770 0 14 28 | B1->B0 | 2c2c 2424 | 0 0 | (0 0) (0 0)
5351 22:15:51.175711 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5352 22:15:51.179158 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5353 22:15:51.185976 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5354 22:15:51.189183 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5355 22:15:51.192738 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5356 22:15:51.199549 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5357 22:15:51.202472 0 15 24 | B1->B0 | 2626 2d2d | 0 0 | (0 0) (0 0)
5358 22:15:51.205584 0 15 28 | B1->B0 | 3939 3d3d | 0 0 | (1 1) (1 1)
5359 22:15:51.211996 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5360 22:15:51.215282 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5361 22:15:51.219186 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5362 22:15:51.225527 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5363 22:15:51.228729 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5364 22:15:51.232215 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5365 22:15:51.238240 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5366 22:15:51.241392 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5367 22:15:51.245132 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5368 22:15:51.252379 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5369 22:15:51.254942 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5370 22:15:51.258534 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5371 22:15:51.264808 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5372 22:15:51.267722 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5373 22:15:51.271653 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5374 22:15:51.278458 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5375 22:15:51.282098 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5376 22:15:51.284761 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5377 22:15:51.291303 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5378 22:15:51.295189 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5379 22:15:51.297821 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5380 22:15:51.304532 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5381 22:15:51.308296 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5382 22:15:51.311067 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5383 22:15:51.314734 Total UI for P1: 0, mck2ui 16
5384 22:15:51.318123 best dqsien dly found for B0: ( 1, 2, 24)
5385 22:15:51.321487 Total UI for P1: 0, mck2ui 16
5386 22:15:51.324366 best dqsien dly found for B1: ( 1, 2, 26)
5387 22:15:51.327864 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5388 22:15:51.330955 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5389 22:15:51.331429
5390 22:15:51.337993 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5391 22:15:51.341523 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5392 22:15:51.344046 [Gating] SW calibration Done
5393 22:15:51.344517 ==
5394 22:15:51.347397 Dram Type= 6, Freq= 0, CH_0, rank 1
5395 22:15:51.350651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5396 22:15:51.351125 ==
5397 22:15:51.351494 RX Vref Scan: 0
5398 22:15:51.351832
5399 22:15:51.354134 RX Vref 0 -> 0, step: 1
5400 22:15:51.354826
5401 22:15:51.357408 RX Delay -80 -> 252, step: 8
5402 22:15:51.360705 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5403 22:15:51.364395 iDelay=208, Bit 1, Center 103 (8 ~ 199) 192
5404 22:15:51.371359 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5405 22:15:51.373914 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5406 22:15:51.376932 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5407 22:15:51.380529 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5408 22:15:51.384002 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5409 22:15:51.387248 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5410 22:15:51.393794 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5411 22:15:51.397529 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5412 22:15:51.400274 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5413 22:15:51.403650 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5414 22:15:51.407080 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5415 22:15:51.413543 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5416 22:15:51.416696 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5417 22:15:51.420161 iDelay=208, Bit 15, Center 95 (8 ~ 183) 176
5418 22:15:51.420730 ==
5419 22:15:51.423744 Dram Type= 6, Freq= 0, CH_0, rank 1
5420 22:15:51.426747 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5421 22:15:51.427326 ==
5422 22:15:51.430037 DQS Delay:
5423 22:15:51.430531 DQS0 = 0, DQS1 = 0
5424 22:15:51.430920 DQM Delay:
5425 22:15:51.434132 DQM0 = 103, DQM1 = 90
5426 22:15:51.434748 DQ Delay:
5427 22:15:51.436499 DQ0 =103, DQ1 =103, DQ2 =99, DQ3 =99
5428 22:15:51.440172 DQ4 =107, DQ5 =95, DQ6 =111, DQ7 =111
5429 22:15:51.443463 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5430 22:15:51.446781 DQ12 =95, DQ13 =91, DQ14 =99, DQ15 =95
5431 22:15:51.447252
5432 22:15:51.447635
5433 22:15:51.450725 ==
5434 22:15:51.451299 Dram Type= 6, Freq= 0, CH_0, rank 1
5435 22:15:51.456215 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5436 22:15:51.456688 ==
5437 22:15:51.457059
5438 22:15:51.457397
5439 22:15:51.459690 TX Vref Scan disable
5440 22:15:51.460387 == TX Byte 0 ==
5441 22:15:51.463145 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5442 22:15:51.469762 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5443 22:15:51.470337 == TX Byte 1 ==
5444 22:15:51.476643 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5445 22:15:51.479424 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5446 22:15:51.479923 ==
5447 22:15:51.483105 Dram Type= 6, Freq= 0, CH_0, rank 1
5448 22:15:51.486273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5449 22:15:51.486884 ==
5450 22:15:51.487255
5451 22:15:51.487592
5452 22:15:51.489593 TX Vref Scan disable
5453 22:15:51.492980 == TX Byte 0 ==
5454 22:15:51.496254 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5455 22:15:51.499954 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5456 22:15:51.503182 == TX Byte 1 ==
5457 22:15:51.506014 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5458 22:15:51.509487 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5459 22:15:51.510075
5460 22:15:51.513071 [DATLAT]
5461 22:15:51.513541 Freq=933, CH0 RK1
5462 22:15:51.513915
5463 22:15:51.515963 DATLAT Default: 0xb
5464 22:15:51.516336 0, 0xFFFF, sum = 0
5465 22:15:51.519322 1, 0xFFFF, sum = 0
5466 22:15:51.519893 2, 0xFFFF, sum = 0
5467 22:15:51.522742 3, 0xFFFF, sum = 0
5468 22:15:51.523321 4, 0xFFFF, sum = 0
5469 22:15:51.526781 5, 0xFFFF, sum = 0
5470 22:15:51.527259 6, 0xFFFF, sum = 0
5471 22:15:51.529294 7, 0xFFFF, sum = 0
5472 22:15:51.529832 8, 0xFFFF, sum = 0
5473 22:15:51.532763 9, 0xFFFF, sum = 0
5474 22:15:51.533340 10, 0x0, sum = 1
5475 22:15:51.535785 11, 0x0, sum = 2
5476 22:15:51.536343 12, 0x0, sum = 3
5477 22:15:51.539362 13, 0x0, sum = 4
5478 22:15:51.539952 best_step = 11
5479 22:15:51.540379
5480 22:15:51.540742 ==
5481 22:15:51.542954 Dram Type= 6, Freq= 0, CH_0, rank 1
5482 22:15:51.549075 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5483 22:15:51.549649 ==
5484 22:15:51.550020 RX Vref Scan: 0
5485 22:15:51.550410
5486 22:15:51.552140 RX Vref 0 -> 0, step: 1
5487 22:15:51.552710
5488 22:15:51.555639 RX Delay -53 -> 252, step: 4
5489 22:15:51.558812 iDelay=199, Bit 0, Center 104 (19 ~ 190) 172
5490 22:15:51.565403 iDelay=199, Bit 1, Center 106 (19 ~ 194) 176
5491 22:15:51.568820 iDelay=199, Bit 2, Center 100 (15 ~ 186) 172
5492 22:15:51.572040 iDelay=199, Bit 3, Center 98 (15 ~ 182) 168
5493 22:15:51.575212 iDelay=199, Bit 4, Center 104 (19 ~ 190) 172
5494 22:15:51.578949 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5495 22:15:51.582242 iDelay=199, Bit 6, Center 112 (27 ~ 198) 172
5496 22:15:51.588693 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5497 22:15:51.592201 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5498 22:15:51.595567 iDelay=199, Bit 9, Center 80 (-1 ~ 162) 164
5499 22:15:51.598521 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5500 22:15:51.602103 iDelay=199, Bit 11, Center 92 (11 ~ 174) 164
5501 22:15:51.608388 iDelay=199, Bit 12, Center 96 (11 ~ 182) 172
5502 22:15:51.611890 iDelay=199, Bit 13, Center 94 (11 ~ 178) 168
5503 22:15:51.615020 iDelay=199, Bit 14, Center 104 (19 ~ 190) 172
5504 22:15:51.618284 iDelay=199, Bit 15, Center 100 (19 ~ 182) 164
5505 22:15:51.618893 ==
5506 22:15:51.621597 Dram Type= 6, Freq= 0, CH_0, rank 1
5507 22:15:51.628167 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5508 22:15:51.628739 ==
5509 22:15:51.629119 DQS Delay:
5510 22:15:51.631200 DQS0 = 0, DQS1 = 0
5511 22:15:51.631679 DQM Delay:
5512 22:15:51.632059 DQM0 = 104, DQM1 = 93
5513 22:15:51.635272 DQ Delay:
5514 22:15:51.638035 DQ0 =104, DQ1 =106, DQ2 =100, DQ3 =98
5515 22:15:51.641783 DQ4 =104, DQ5 =98, DQ6 =112, DQ7 =112
5516 22:15:51.644555 DQ8 =84, DQ9 =80, DQ10 =94, DQ11 =92
5517 22:15:51.648015 DQ12 =96, DQ13 =94, DQ14 =104, DQ15 =100
5518 22:15:51.648489
5519 22:15:51.648863
5520 22:15:51.654452 [DQSOSCAuto] RK1, (LSB)MR18= 0x2608, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 409 ps
5521 22:15:51.657946 CH0 RK1: MR19=505, MR18=2608
5522 22:15:51.665199 CH0_RK1: MR19=0x505, MR18=0x2608, DQSOSC=409, MR23=63, INC=64, DEC=43
5523 22:15:51.667814 [RxdqsGatingPostProcess] freq 933
5524 22:15:51.674474 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5525 22:15:51.678054 best DQS0 dly(2T, 0.5T) = (0, 10)
5526 22:15:51.678675 best DQS1 dly(2T, 0.5T) = (0, 10)
5527 22:15:51.680928 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5528 22:15:51.684377 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5529 22:15:51.687868 best DQS0 dly(2T, 0.5T) = (0, 10)
5530 22:15:51.691852 best DQS1 dly(2T, 0.5T) = (0, 10)
5531 22:15:51.695189 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5532 22:15:51.698263 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5533 22:15:51.701132 Pre-setting of DQS Precalculation
5534 22:15:51.707640 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5535 22:15:51.708215 ==
5536 22:15:51.711044 Dram Type= 6, Freq= 0, CH_1, rank 0
5537 22:15:51.715168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5538 22:15:51.715742 ==
5539 22:15:51.721995 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5540 22:15:51.724129 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5541 22:15:51.728931 [CA 0] Center 37 (7~68) winsize 62
5542 22:15:51.732044 [CA 1] Center 37 (7~68) winsize 62
5543 22:15:51.735421 [CA 2] Center 36 (6~66) winsize 61
5544 22:15:51.738443 [CA 3] Center 35 (5~65) winsize 61
5545 22:15:51.741510 [CA 4] Center 35 (5~66) winsize 62
5546 22:15:51.744897 [CA 5] Center 35 (5~65) winsize 61
5547 22:15:51.745468
5548 22:15:51.748023 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5549 22:15:51.748502
5550 22:15:51.751278 [CATrainingPosCal] consider 1 rank data
5551 22:15:51.754764 u2DelayCellTimex100 = 270/100 ps
5552 22:15:51.757922 CA0 delay=37 (7~68),Diff = 2 PI (12 cell)
5553 22:15:51.764455 CA1 delay=37 (7~68),Diff = 2 PI (12 cell)
5554 22:15:51.768660 CA2 delay=36 (6~66),Diff = 1 PI (6 cell)
5555 22:15:51.771668 CA3 delay=35 (5~65),Diff = 0 PI (0 cell)
5556 22:15:51.774757 CA4 delay=35 (5~66),Diff = 0 PI (0 cell)
5557 22:15:51.777748 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
5558 22:15:51.778226
5559 22:15:51.781099 CA PerBit enable=1, Macro0, CA PI delay=35
5560 22:15:51.781665
5561 22:15:51.784557 [CBTSetCACLKResult] CA Dly = 35
5562 22:15:51.787734 CS Dly: 7 (0~38)
5563 22:15:51.788304 ==
5564 22:15:51.791055 Dram Type= 6, Freq= 0, CH_1, rank 1
5565 22:15:51.794472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5566 22:15:51.795231 ==
5567 22:15:51.800744 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5568 22:15:51.804317 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5569 22:15:51.809167 [CA 0] Center 38 (8~69) winsize 62
5570 22:15:51.811453 [CA 1] Center 38 (8~69) winsize 62
5571 22:15:51.814994 [CA 2] Center 36 (6~66) winsize 61
5572 22:15:51.818387 [CA 3] Center 35 (6~65) winsize 60
5573 22:15:51.821663 [CA 4] Center 35 (6~65) winsize 60
5574 22:15:51.824982 [CA 5] Center 34 (5~64) winsize 60
5575 22:15:51.825464
5576 22:15:51.828816 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5577 22:15:51.829389
5578 22:15:51.831507 [CATrainingPosCal] consider 2 rank data
5579 22:15:51.835112 u2DelayCellTimex100 = 270/100 ps
5580 22:15:51.838428 CA0 delay=38 (8~68),Diff = 4 PI (24 cell)
5581 22:15:51.845554 CA1 delay=38 (8~68),Diff = 4 PI (24 cell)
5582 22:15:51.848614 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5583 22:15:51.850985 CA3 delay=35 (6~65),Diff = 1 PI (6 cell)
5584 22:15:51.854565 CA4 delay=35 (6~65),Diff = 1 PI (6 cell)
5585 22:15:51.857494 CA5 delay=34 (5~64),Diff = 0 PI (0 cell)
5586 22:15:51.858075
5587 22:15:51.861201 CA PerBit enable=1, Macro0, CA PI delay=34
5588 22:15:51.861802
5589 22:15:51.864407 [CBTSetCACLKResult] CA Dly = 34
5590 22:15:51.867826 CS Dly: 7 (0~39)
5591 22:15:51.868399
5592 22:15:51.870554 ----->DramcWriteLeveling(PI) begin...
5593 22:15:51.871042 ==
5594 22:15:51.874103 Dram Type= 6, Freq= 0, CH_1, rank 0
5595 22:15:51.878113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5596 22:15:51.878740 ==
5597 22:15:51.880806 Write leveling (Byte 0): 27 => 27
5598 22:15:51.884052 Write leveling (Byte 1): 29 => 29
5599 22:15:51.887062 DramcWriteLeveling(PI) end<-----
5600 22:15:51.887542
5601 22:15:51.887919 ==
5602 22:15:51.890525 Dram Type= 6, Freq= 0, CH_1, rank 0
5603 22:15:51.894550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5604 22:15:51.895121 ==
5605 22:15:51.897722 [Gating] SW mode calibration
5606 22:15:51.903931 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5607 22:15:51.910438 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5608 22:15:51.913473 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5609 22:15:51.921131 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5610 22:15:51.923614 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5611 22:15:51.926448 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5612 22:15:51.933328 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5613 22:15:51.937030 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5614 22:15:51.940089 0 14 24 | B1->B0 | 3333 3232 | 0 0 | (0 0) (0 0)
5615 22:15:51.946378 0 14 28 | B1->B0 | 2929 2727 | 0 0 | (1 1) (0 0)
5616 22:15:51.949786 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5617 22:15:51.953026 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5618 22:15:51.959418 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5619 22:15:51.962915 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5620 22:15:51.965793 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5621 22:15:51.972417 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5622 22:15:51.975933 0 15 24 | B1->B0 | 2a2a 2f2f | 0 0 | (0 0) (0 0)
5623 22:15:51.978954 0 15 28 | B1->B0 | 3c3c 4242 | 1 0 | (0 0) (0 0)
5624 22:15:51.985842 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5625 22:15:51.988970 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5626 22:15:51.992536 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5627 22:15:51.999215 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5628 22:15:52.002923 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5629 22:15:52.006134 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5630 22:15:52.012935 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5631 22:15:52.015451 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5632 22:15:52.019410 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5633 22:15:52.025365 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5634 22:15:52.029167 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5635 22:15:52.032435 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5636 22:15:52.039198 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5637 22:15:52.042724 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5638 22:15:52.045763 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5639 22:15:52.052213 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5640 22:15:52.055232 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5641 22:15:52.058711 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5642 22:15:52.065093 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5643 22:15:52.068969 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5644 22:15:52.071743 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5645 22:15:52.075635 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5646 22:15:52.081947 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5647 22:15:52.085638 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5648 22:15:52.088368 Total UI for P1: 0, mck2ui 16
5649 22:15:52.092199 best dqsien dly found for B0: ( 1, 2, 24)
5650 22:15:52.095210 Total UI for P1: 0, mck2ui 16
5651 22:15:52.097986 best dqsien dly found for B1: ( 1, 2, 24)
5652 22:15:52.101904 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5653 22:15:52.104870 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5654 22:15:52.105436
5655 22:15:52.108205 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5656 22:15:52.114805 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5657 22:15:52.115285 [Gating] SW calibration Done
5658 22:15:52.115660 ==
5659 22:15:52.118039 Dram Type= 6, Freq= 0, CH_1, rank 0
5660 22:15:52.124713 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5661 22:15:52.125294 ==
5662 22:15:52.125672 RX Vref Scan: 0
5663 22:15:52.126024
5664 22:15:52.128086 RX Vref 0 -> 0, step: 1
5665 22:15:52.128565
5666 22:15:52.131551 RX Delay -80 -> 252, step: 8
5667 22:15:52.134913 iDelay=208, Bit 0, Center 107 (24 ~ 191) 168
5668 22:15:52.137712 iDelay=208, Bit 1, Center 95 (8 ~ 183) 176
5669 22:15:52.141134 iDelay=208, Bit 2, Center 95 (8 ~ 183) 176
5670 22:15:52.144799 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5671 22:15:52.151772 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5672 22:15:52.154671 iDelay=208, Bit 5, Center 111 (24 ~ 199) 176
5673 22:15:52.157506 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5674 22:15:52.161045 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5675 22:15:52.164172 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5676 22:15:52.170735 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5677 22:15:52.174067 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5678 22:15:52.177123 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5679 22:15:52.180519 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5680 22:15:52.184141 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5681 22:15:52.191037 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5682 22:15:52.193972 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5683 22:15:52.194586 ==
5684 22:15:52.197128 Dram Type= 6, Freq= 0, CH_1, rank 0
5685 22:15:52.200744 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5686 22:15:52.201333 ==
5687 22:15:52.201717 DQS Delay:
5688 22:15:52.204339 DQS0 = 0, DQS1 = 0
5689 22:15:52.204817 DQM Delay:
5690 22:15:52.207106 DQM0 = 102, DQM1 = 94
5691 22:15:52.207679 DQ Delay:
5692 22:15:52.210084 DQ0 =107, DQ1 =95, DQ2 =95, DQ3 =99
5693 22:15:52.213689 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =99
5694 22:15:52.217324 DQ8 =83, DQ9 =83, DQ10 =99, DQ11 =87
5695 22:15:52.220860 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =99
5696 22:15:52.221432
5697 22:15:52.221809
5698 22:15:52.222152 ==
5699 22:15:52.223404 Dram Type= 6, Freq= 0, CH_1, rank 0
5700 22:15:52.230635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5701 22:15:52.231216 ==
5702 22:15:52.231595
5703 22:15:52.231944
5704 22:15:52.232275 TX Vref Scan disable
5705 22:15:52.233722 == TX Byte 0 ==
5706 22:15:52.237167 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5707 22:15:52.244181 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5708 22:15:52.244755 == TX Byte 1 ==
5709 22:15:52.247681 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5710 22:15:52.254455 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5711 22:15:52.255033 ==
5712 22:15:52.257262 Dram Type= 6, Freq= 0, CH_1, rank 0
5713 22:15:52.260087 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5714 22:15:52.260568 ==
5715 22:15:52.260944
5716 22:15:52.261290
5717 22:15:52.263940 TX Vref Scan disable
5718 22:15:52.264420 == TX Byte 0 ==
5719 22:15:52.270737 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5720 22:15:52.273752 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5721 22:15:52.274324 == TX Byte 1 ==
5722 22:15:52.280221 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5723 22:15:52.283179 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5724 22:15:52.283668
5725 22:15:52.284050 [DATLAT]
5726 22:15:52.286490 Freq=933, CH1 RK0
5727 22:15:52.286970
5728 22:15:52.287343 DATLAT Default: 0xd
5729 22:15:52.290250 0, 0xFFFF, sum = 0
5730 22:15:52.290862 1, 0xFFFF, sum = 0
5731 22:15:52.293560 2, 0xFFFF, sum = 0
5732 22:15:52.297149 3, 0xFFFF, sum = 0
5733 22:15:52.297736 4, 0xFFFF, sum = 0
5734 22:15:52.300236 5, 0xFFFF, sum = 0
5735 22:15:52.300820 6, 0xFFFF, sum = 0
5736 22:15:52.303433 7, 0xFFFF, sum = 0
5737 22:15:52.303931 8, 0xFFFF, sum = 0
5738 22:15:52.306563 9, 0xFFFF, sum = 0
5739 22:15:52.307161 10, 0x0, sum = 1
5740 22:15:52.309936 11, 0x0, sum = 2
5741 22:15:52.310550 12, 0x0, sum = 3
5742 22:15:52.313149 13, 0x0, sum = 4
5743 22:15:52.313634 best_step = 11
5744 22:15:52.314006
5745 22:15:52.314509 ==
5746 22:15:52.316580 Dram Type= 6, Freq= 0, CH_1, rank 0
5747 22:15:52.320032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5748 22:15:52.320606 ==
5749 22:15:52.323762 RX Vref Scan: 1
5750 22:15:52.324330
5751 22:15:52.326647 RX Vref 0 -> 0, step: 1
5752 22:15:52.327124
5753 22:15:52.327503 RX Delay -53 -> 252, step: 4
5754 22:15:52.327852
5755 22:15:52.329894 Set Vref, RX VrefLevel [Byte0]: 51
5756 22:15:52.333272 [Byte1]: 50
5757 22:15:52.338128
5758 22:15:52.338725 Final RX Vref Byte 0 = 51 to rank0
5759 22:15:52.341252 Final RX Vref Byte 1 = 50 to rank0
5760 22:15:52.344534 Final RX Vref Byte 0 = 51 to rank1
5761 22:15:52.347821 Final RX Vref Byte 1 = 50 to rank1==
5762 22:15:52.351182 Dram Type= 6, Freq= 0, CH_1, rank 0
5763 22:15:52.357773 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5764 22:15:52.358380 ==
5765 22:15:52.358772 DQS Delay:
5766 22:15:52.359124 DQS0 = 0, DQS1 = 0
5767 22:15:52.360776 DQM Delay:
5768 22:15:52.361245 DQM0 = 104, DQM1 = 96
5769 22:15:52.364108 DQ Delay:
5770 22:15:52.367699 DQ0 =108, DQ1 =98, DQ2 =96, DQ3 =102
5771 22:15:52.370907 DQ4 =104, DQ5 =114, DQ6 =116, DQ7 =100
5772 22:15:52.374425 DQ8 =86, DQ9 =86, DQ10 =100, DQ11 =90
5773 22:15:52.377900 DQ12 =106, DQ13 =102, DQ14 =102, DQ15 =102
5774 22:15:52.378514
5775 22:15:52.378889
5776 22:15:52.384012 [DQSOSCAuto] RK0, (LSB)MR18= 0x162e, (MSB)MR19= 0x505, tDQSOscB0 = 407 ps tDQSOscB1 = 414 ps
5777 22:15:52.387047 CH1 RK0: MR19=505, MR18=162E
5778 22:15:52.393867 CH1_RK0: MR19=0x505, MR18=0x162E, DQSOSC=407, MR23=63, INC=65, DEC=43
5779 22:15:52.394480
5780 22:15:52.397309 ----->DramcWriteLeveling(PI) begin...
5781 22:15:52.397889 ==
5782 22:15:52.400386 Dram Type= 6, Freq= 0, CH_1, rank 1
5783 22:15:52.403954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5784 22:15:52.407015 ==
5785 22:15:52.410513 Write leveling (Byte 0): 26 => 26
5786 22:15:52.410989 Write leveling (Byte 1): 26 => 26
5787 22:15:52.413499 DramcWriteLeveling(PI) end<-----
5788 22:15:52.413993
5789 22:15:52.414408 ==
5790 22:15:52.416795 Dram Type= 6, Freq= 0, CH_1, rank 1
5791 22:15:52.423345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5792 22:15:52.423855 ==
5793 22:15:52.427207 [Gating] SW mode calibration
5794 22:15:52.433764 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5795 22:15:52.436897 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5796 22:15:52.443477 0 14 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5797 22:15:52.447079 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5798 22:15:52.450047 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5799 22:15:52.456546 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5800 22:15:52.459775 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5801 22:15:52.463609 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5802 22:15:52.469841 0 14 24 | B1->B0 | 3030 3434 | 1 0 | (0 1) (0 0)
5803 22:15:52.473279 0 14 28 | B1->B0 | 2424 2a2a | 0 0 | (0 0) (0 0)
5804 22:15:52.477128 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5805 22:15:52.483274 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5806 22:15:52.486678 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5807 22:15:52.489954 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5808 22:15:52.496489 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5809 22:15:52.499431 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5810 22:15:52.502915 0 15 24 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5811 22:15:52.509218 0 15 28 | B1->B0 | 4545 3838 | 0 1 | (0 0) (0 0)
5812 22:15:52.512557 1 0 0 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
5813 22:15:52.516476 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5814 22:15:52.522652 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5815 22:15:52.526256 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5816 22:15:52.529501 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5817 22:15:52.536392 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5818 22:15:52.539721 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5819 22:15:52.542617 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5820 22:15:52.549301 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5821 22:15:52.553436 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5822 22:15:52.555725 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5823 22:15:52.559003 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5824 22:15:52.565589 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5825 22:15:52.569038 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5826 22:15:52.572360 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5827 22:15:52.579232 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5828 22:15:52.582284 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5829 22:15:52.585624 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5830 22:15:52.592092 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5831 22:15:52.596224 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5832 22:15:52.598774 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5833 22:15:52.605132 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5834 22:15:52.608714 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5835 22:15:52.615658 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5836 22:15:52.618540 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5837 22:15:52.621543 Total UI for P1: 0, mck2ui 16
5838 22:15:52.625464 best dqsien dly found for B0: ( 1, 2, 26)
5839 22:15:52.628383 Total UI for P1: 0, mck2ui 16
5840 22:15:52.632098 best dqsien dly found for B1: ( 1, 2, 26)
5841 22:15:52.635362 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5842 22:15:52.638485 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5843 22:15:52.639114
5844 22:15:52.641834 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5845 22:15:52.644808 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5846 22:15:52.648483 [Gating] SW calibration Done
5847 22:15:52.649061 ==
5848 22:15:52.651659 Dram Type= 6, Freq= 0, CH_1, rank 1
5849 22:15:52.654575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5850 22:15:52.655055 ==
5851 22:15:52.658305 RX Vref Scan: 0
5852 22:15:52.658959
5853 22:15:52.661460 RX Vref 0 -> 0, step: 1
5854 22:15:52.661934
5855 22:15:52.662577 RX Delay -80 -> 252, step: 8
5856 22:15:52.668210 iDelay=200, Bit 0, Center 107 (24 ~ 191) 168
5857 22:15:52.671067 iDelay=200, Bit 1, Center 99 (16 ~ 183) 168
5858 22:15:52.674870 iDelay=200, Bit 2, Center 91 (8 ~ 175) 168
5859 22:15:52.678272 iDelay=200, Bit 3, Center 103 (16 ~ 191) 176
5860 22:15:52.681553 iDelay=200, Bit 4, Center 103 (16 ~ 191) 176
5861 22:15:52.688340 iDelay=200, Bit 5, Center 111 (24 ~ 199) 176
5862 22:15:52.692059 iDelay=200, Bit 6, Center 111 (24 ~ 199) 176
5863 22:15:52.694579 iDelay=200, Bit 7, Center 103 (16 ~ 191) 176
5864 22:15:52.698036 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5865 22:15:52.701309 iDelay=200, Bit 9, Center 87 (0 ~ 175) 176
5866 22:15:52.704863 iDelay=200, Bit 10, Center 95 (8 ~ 183) 176
5867 22:15:52.711246 iDelay=200, Bit 11, Center 87 (-8 ~ 183) 192
5868 22:15:52.714309 iDelay=200, Bit 12, Center 103 (8 ~ 199) 192
5869 22:15:52.717557 iDelay=200, Bit 13, Center 103 (8 ~ 199) 192
5870 22:15:52.720925 iDelay=200, Bit 14, Center 99 (8 ~ 191) 184
5871 22:15:52.724012 iDelay=200, Bit 15, Center 103 (8 ~ 199) 192
5872 22:15:52.727915 ==
5873 22:15:52.730955 Dram Type= 6, Freq= 0, CH_1, rank 1
5874 22:15:52.734666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5875 22:15:52.735247 ==
5876 22:15:52.735793 DQS Delay:
5877 22:15:52.737488 DQS0 = 0, DQS1 = 0
5878 22:15:52.737966 DQM Delay:
5879 22:15:52.741862 DQM0 = 103, DQM1 = 95
5880 22:15:52.742485 DQ Delay:
5881 22:15:52.744462 DQ0 =107, DQ1 =99, DQ2 =91, DQ3 =103
5882 22:15:52.747488 DQ4 =103, DQ5 =111, DQ6 =111, DQ7 =103
5883 22:15:52.751263 DQ8 =83, DQ9 =87, DQ10 =95, DQ11 =87
5884 22:15:52.754600 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =103
5885 22:15:52.755180
5886 22:15:52.755558
5887 22:15:52.755903 ==
5888 22:15:52.757428 Dram Type= 6, Freq= 0, CH_1, rank 1
5889 22:15:52.761614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5890 22:15:52.763732 ==
5891 22:15:52.764213
5892 22:15:52.764584
5893 22:15:52.764930 TX Vref Scan disable
5894 22:15:52.767288 == TX Byte 0 ==
5895 22:15:52.770973 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5896 22:15:52.773813 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5897 22:15:52.777400 == TX Byte 1 ==
5898 22:15:52.780545 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5899 22:15:52.783818 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5900 22:15:52.787609 ==
5901 22:15:52.790527 Dram Type= 6, Freq= 0, CH_1, rank 1
5902 22:15:52.794307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5903 22:15:52.794931 ==
5904 22:15:52.795314
5905 22:15:52.795661
5906 22:15:52.796689 TX Vref Scan disable
5907 22:15:52.797163 == TX Byte 0 ==
5908 22:15:52.803792 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5909 22:15:52.807151 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5910 22:15:52.807722 == TX Byte 1 ==
5911 22:15:52.813508 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5912 22:15:52.816818 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5913 22:15:52.817330
5914 22:15:52.817732 [DATLAT]
5915 22:15:52.820016 Freq=933, CH1 RK1
5916 22:15:52.820717
5917 22:15:52.821110 DATLAT Default: 0xb
5918 22:15:52.823396 0, 0xFFFF, sum = 0
5919 22:15:52.823874 1, 0xFFFF, sum = 0
5920 22:15:52.826858 2, 0xFFFF, sum = 0
5921 22:15:52.827398 3, 0xFFFF, sum = 0
5922 22:15:52.829982 4, 0xFFFF, sum = 0
5923 22:15:52.830539 5, 0xFFFF, sum = 0
5924 22:15:52.833432 6, 0xFFFF, sum = 0
5925 22:15:52.836756 7, 0xFFFF, sum = 0
5926 22:15:52.837248 8, 0xFFFF, sum = 0
5927 22:15:52.840370 9, 0xFFFF, sum = 0
5928 22:15:52.840951 10, 0x0, sum = 1
5929 22:15:52.843936 11, 0x0, sum = 2
5930 22:15:52.844416 12, 0x0, sum = 3
5931 22:15:52.844797 13, 0x0, sum = 4
5932 22:15:52.847119 best_step = 11
5933 22:15:52.847705
5934 22:15:52.848079 ==
5935 22:15:52.850050 Dram Type= 6, Freq= 0, CH_1, rank 1
5936 22:15:52.853547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5937 22:15:52.854120 ==
5938 22:15:52.856612 RX Vref Scan: 0
5939 22:15:52.857185
5940 22:15:52.860123 RX Vref 0 -> 0, step: 1
5941 22:15:52.860699
5942 22:15:52.861074 RX Delay -53 -> 252, step: 4
5943 22:15:52.867649 iDelay=199, Bit 0, Center 110 (35 ~ 186) 152
5944 22:15:52.870702 iDelay=199, Bit 1, Center 98 (19 ~ 178) 160
5945 22:15:52.874063 iDelay=199, Bit 2, Center 94 (15 ~ 174) 160
5946 22:15:52.877448 iDelay=199, Bit 3, Center 102 (19 ~ 186) 168
5947 22:15:52.881395 iDelay=199, Bit 4, Center 106 (23 ~ 190) 168
5948 22:15:52.887846 iDelay=199, Bit 5, Center 114 (31 ~ 198) 168
5949 22:15:52.890768 iDelay=199, Bit 6, Center 112 (31 ~ 194) 164
5950 22:15:52.894006 iDelay=199, Bit 7, Center 102 (23 ~ 182) 160
5951 22:15:52.897279 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5952 22:15:52.902111 iDelay=199, Bit 9, Center 86 (3 ~ 170) 168
5953 22:15:52.907118 iDelay=199, Bit 10, Center 98 (15 ~ 182) 168
5954 22:15:52.910735 iDelay=199, Bit 11, Center 94 (11 ~ 178) 168
5955 22:15:52.914119 iDelay=199, Bit 12, Center 108 (23 ~ 194) 172
5956 22:15:52.916644 iDelay=199, Bit 13, Center 106 (23 ~ 190) 168
5957 22:15:52.919915 iDelay=199, Bit 14, Center 104 (19 ~ 190) 172
5958 22:15:52.926772 iDelay=199, Bit 15, Center 108 (23 ~ 194) 172
5959 22:15:52.927354 ==
5960 22:15:52.930136 Dram Type= 6, Freq= 0, CH_1, rank 1
5961 22:15:52.933511 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5962 22:15:52.934109 ==
5963 22:15:52.934519 DQS Delay:
5964 22:15:52.937292 DQS0 = 0, DQS1 = 0
5965 22:15:52.937764 DQM Delay:
5966 22:15:52.939889 DQM0 = 104, DQM1 = 98
5967 22:15:52.940361 DQ Delay:
5968 22:15:52.943058 DQ0 =110, DQ1 =98, DQ2 =94, DQ3 =102
5969 22:15:52.947450 DQ4 =106, DQ5 =114, DQ6 =112, DQ7 =102
5970 22:15:52.950317 DQ8 =84, DQ9 =86, DQ10 =98, DQ11 =94
5971 22:15:52.952999 DQ12 =108, DQ13 =106, DQ14 =104, DQ15 =108
5972 22:15:52.953469
5973 22:15:52.953839
5974 22:15:52.963070 [DQSOSCAuto] RK1, (LSB)MR18= 0x2402, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 410 ps
5975 22:15:52.966475 CH1 RK1: MR19=505, MR18=2402
5976 22:15:52.969613 CH1_RK1: MR19=0x505, MR18=0x2402, DQSOSC=410, MR23=63, INC=64, DEC=42
5977 22:15:52.972717 [RxdqsGatingPostProcess] freq 933
5978 22:15:52.979484 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5979 22:15:52.982971 best DQS0 dly(2T, 0.5T) = (0, 10)
5980 22:15:52.986297 best DQS1 dly(2T, 0.5T) = (0, 10)
5981 22:15:52.989762 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5982 22:15:52.993151 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5983 22:15:52.996566 best DQS0 dly(2T, 0.5T) = (0, 10)
5984 22:15:52.999517 best DQS1 dly(2T, 0.5T) = (0, 10)
5985 22:15:53.002887 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5986 22:15:53.006272 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5987 22:15:53.009656 Pre-setting of DQS Precalculation
5988 22:15:53.012625 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5989 22:15:53.018991 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5990 22:15:53.029162 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5991 22:15:53.029747
5992 22:15:53.030117
5993 22:15:53.030502 [Calibration Summary] 1866 Mbps
5994 22:15:53.032687 CH 0, Rank 0
5995 22:15:53.035579 SW Impedance : PASS
5996 22:15:53.036152 DUTY Scan : NO K
5997 22:15:53.038789 ZQ Calibration : PASS
5998 22:15:53.039266 Jitter Meter : NO K
5999 22:15:53.042256 CBT Training : PASS
6000 22:15:53.045366 Write leveling : PASS
6001 22:15:53.045944 RX DQS gating : PASS
6002 22:15:53.049201 RX DQ/DQS(RDDQC) : PASS
6003 22:15:53.051969 TX DQ/DQS : PASS
6004 22:15:53.052463 RX DATLAT : PASS
6005 22:15:53.055391 RX DQ/DQS(Engine): PASS
6006 22:15:53.058936 TX OE : NO K
6007 22:15:53.059428 All Pass.
6008 22:15:53.059912
6009 22:15:53.060368 CH 0, Rank 1
6010 22:15:53.061785 SW Impedance : PASS
6011 22:15:53.065029 DUTY Scan : NO K
6012 22:15:53.065517 ZQ Calibration : PASS
6013 22:15:53.068670 Jitter Meter : NO K
6014 22:15:53.072003 CBT Training : PASS
6015 22:15:53.072585 Write leveling : PASS
6016 22:15:53.075800 RX DQS gating : PASS
6017 22:15:53.078871 RX DQ/DQS(RDDQC) : PASS
6018 22:15:53.079453 TX DQ/DQS : PASS
6019 22:15:53.082030 RX DATLAT : PASS
6020 22:15:53.085378 RX DQ/DQS(Engine): PASS
6021 22:15:53.085964 TX OE : NO K
6022 22:15:53.088434 All Pass.
6023 22:15:53.089019
6024 22:15:53.089507 CH 1, Rank 0
6025 22:15:53.091715 SW Impedance : PASS
6026 22:15:53.092297 DUTY Scan : NO K
6027 22:15:53.095202 ZQ Calibration : PASS
6028 22:15:53.098733 Jitter Meter : NO K
6029 22:15:53.099313 CBT Training : PASS
6030 22:15:53.101998 Write leveling : PASS
6031 22:15:53.105440 RX DQS gating : PASS
6032 22:15:53.106026 RX DQ/DQS(RDDQC) : PASS
6033 22:15:53.108463 TX DQ/DQS : PASS
6034 22:15:53.109045 RX DATLAT : PASS
6035 22:15:53.112187 RX DQ/DQS(Engine): PASS
6036 22:15:53.115080 TX OE : NO K
6037 22:15:53.115671 All Pass.
6038 22:15:53.116159
6039 22:15:53.116615 CH 1, Rank 1
6040 22:15:53.118241 SW Impedance : PASS
6041 22:15:53.121911 DUTY Scan : NO K
6042 22:15:53.122531 ZQ Calibration : PASS
6043 22:15:53.124999 Jitter Meter : NO K
6044 22:15:53.128152 CBT Training : PASS
6045 22:15:53.128643 Write leveling : PASS
6046 22:15:53.131277 RX DQS gating : PASS
6047 22:15:53.134449 RX DQ/DQS(RDDQC) : PASS
6048 22:15:53.135039 TX DQ/DQS : PASS
6049 22:15:53.138171 RX DATLAT : PASS
6050 22:15:53.141064 RX DQ/DQS(Engine): PASS
6051 22:15:53.141558 TX OE : NO K
6052 22:15:53.144511 All Pass.
6053 22:15:53.145093
6054 22:15:53.145588 DramC Write-DBI off
6055 22:15:53.148273 PER_BANK_REFRESH: Hybrid Mode
6056 22:15:53.148861 TX_TRACKING: ON
6057 22:15:53.158080 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6058 22:15:53.161037 [FAST_K] Save calibration result to emmc
6059 22:15:53.165325 dramc_set_vcore_voltage set vcore to 650000
6060 22:15:53.167671 Read voltage for 400, 6
6061 22:15:53.168162 Vio18 = 0
6062 22:15:53.171186 Vcore = 650000
6063 22:15:53.171677 Vdram = 0
6064 22:15:53.172163 Vddq = 0
6065 22:15:53.174770 Vmddr = 0
6066 22:15:53.177816 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6067 22:15:53.184463 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6068 22:15:53.185048 MEM_TYPE=3, freq_sel=20
6069 22:15:53.187701 sv_algorithm_assistance_LP4_800
6070 22:15:53.194786 ============ PULL DRAM RESETB DOWN ============
6071 22:15:53.197659 ========== PULL DRAM RESETB DOWN end =========
6072 22:15:53.201043 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6073 22:15:53.204367 ===================================
6074 22:15:53.207699 LPDDR4 DRAM CONFIGURATION
6075 22:15:53.210900 ===================================
6076 22:15:53.211478 EX_ROW_EN[0] = 0x0
6077 22:15:53.214108 EX_ROW_EN[1] = 0x0
6078 22:15:53.217694 LP4Y_EN = 0x0
6079 22:15:53.218280 WORK_FSP = 0x0
6080 22:15:53.221034 WL = 0x2
6081 22:15:53.221621 RL = 0x2
6082 22:15:53.224245 BL = 0x2
6083 22:15:53.224833 RPST = 0x0
6084 22:15:53.227613 RD_PRE = 0x0
6085 22:15:53.228105 WR_PRE = 0x1
6086 22:15:53.231320 WR_PST = 0x0
6087 22:15:53.231900 DBI_WR = 0x0
6088 22:15:53.233896 DBI_RD = 0x0
6089 22:15:53.234521 OTF = 0x1
6090 22:15:53.237835 ===================================
6091 22:15:53.240301 ===================================
6092 22:15:53.243917 ANA top config
6093 22:15:53.247385 ===================================
6094 22:15:53.247971 DLL_ASYNC_EN = 0
6095 22:15:53.250507 ALL_SLAVE_EN = 1
6096 22:15:53.253825 NEW_RANK_MODE = 1
6097 22:15:53.257407 DLL_IDLE_MODE = 1
6098 22:15:53.260816 LP45_APHY_COMB_EN = 1
6099 22:15:53.261404 TX_ODT_DIS = 1
6100 22:15:53.263513 NEW_8X_MODE = 1
6101 22:15:53.266915 ===================================
6102 22:15:53.270458 ===================================
6103 22:15:53.273599 data_rate = 800
6104 22:15:53.277148 CKR = 1
6105 22:15:53.280411 DQ_P2S_RATIO = 4
6106 22:15:53.283478 ===================================
6107 22:15:53.287228 CA_P2S_RATIO = 4
6108 22:15:53.287809 DQ_CA_OPEN = 0
6109 22:15:53.290096 DQ_SEMI_OPEN = 1
6110 22:15:53.293392 CA_SEMI_OPEN = 1
6111 22:15:53.296846 CA_FULL_RATE = 0
6112 22:15:53.300753 DQ_CKDIV4_EN = 0
6113 22:15:53.303304 CA_CKDIV4_EN = 1
6114 22:15:53.303885 CA_PREDIV_EN = 0
6115 22:15:53.306419 PH8_DLY = 0
6116 22:15:53.310022 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6117 22:15:53.313076 DQ_AAMCK_DIV = 0
6118 22:15:53.316090 CA_AAMCK_DIV = 0
6119 22:15:53.319586 CA_ADMCK_DIV = 4
6120 22:15:53.320171 DQ_TRACK_CA_EN = 0
6121 22:15:53.323014 CA_PICK = 800
6122 22:15:53.326497 CA_MCKIO = 400
6123 22:15:53.329574 MCKIO_SEMI = 400
6124 22:15:53.333157 PLL_FREQ = 3016
6125 22:15:53.336250 DQ_UI_PI_RATIO = 32
6126 22:15:53.339420 CA_UI_PI_RATIO = 32
6127 22:15:53.342979 ===================================
6128 22:15:53.346081 ===================================
6129 22:15:53.346715 memory_type:LPDDR4
6130 22:15:53.349163 GP_NUM : 10
6131 22:15:53.352791 SRAM_EN : 1
6132 22:15:53.353374 MD32_EN : 0
6133 22:15:53.356094 ===================================
6134 22:15:53.359089 [ANA_INIT] >>>>>>>>>>>>>>
6135 22:15:53.362408 <<<<<< [CONFIGURE PHASE]: ANA_TX
6136 22:15:53.365814 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6137 22:15:53.369241 ===================================
6138 22:15:53.372713 data_rate = 800,PCW = 0X7400
6139 22:15:53.376058 ===================================
6140 22:15:53.379190 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6141 22:15:53.384022 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6142 22:15:53.395668 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6143 22:15:53.399060 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6144 22:15:53.402424 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6145 22:15:53.405602 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6146 22:15:53.409075 [ANA_INIT] flow start
6147 22:15:53.412237 [ANA_INIT] PLL >>>>>>>>
6148 22:15:53.412821 [ANA_INIT] PLL <<<<<<<<
6149 22:15:53.415665 [ANA_INIT] MIDPI >>>>>>>>
6150 22:15:53.418855 [ANA_INIT] MIDPI <<<<<<<<
6151 22:15:53.419448 [ANA_INIT] DLL >>>>>>>>
6152 22:15:53.422186 [ANA_INIT] flow end
6153 22:15:53.425791 ============ LP4 DIFF to SE enter ============
6154 22:15:53.432572 ============ LP4 DIFF to SE exit ============
6155 22:15:53.433163 [ANA_INIT] <<<<<<<<<<<<<
6156 22:15:53.436070 [Flow] Enable top DCM control >>>>>
6157 22:15:53.438799 [Flow] Enable top DCM control <<<<<
6158 22:15:53.442788 Enable DLL master slave shuffle
6159 22:15:53.449378 ==============================================================
6160 22:15:53.449964 Gating Mode config
6161 22:15:53.455609 ==============================================================
6162 22:15:53.458518 Config description:
6163 22:15:53.464974 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6164 22:15:53.472049 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6165 22:15:53.478515 SELPH_MODE 0: By rank 1: By Phase
6166 22:15:53.485261 ==============================================================
6167 22:15:53.488692 GAT_TRACK_EN = 0
6168 22:15:53.489279 RX_GATING_MODE = 2
6169 22:15:53.492163 RX_GATING_TRACK_MODE = 2
6170 22:15:53.494947 SELPH_MODE = 1
6171 22:15:53.497979 PICG_EARLY_EN = 1
6172 22:15:53.501733 VALID_LAT_VALUE = 1
6173 22:15:53.508267 ==============================================================
6174 22:15:53.512116 Enter into Gating configuration >>>>
6175 22:15:53.515068 Exit from Gating configuration <<<<
6176 22:15:53.517909 Enter into DVFS_PRE_config >>>>>
6177 22:15:53.528327 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6178 22:15:53.531525 Exit from DVFS_PRE_config <<<<<
6179 22:15:53.534577 Enter into PICG configuration >>>>
6180 22:15:53.538285 Exit from PICG configuration <<<<
6181 22:15:53.541407 [RX_INPUT] configuration >>>>>
6182 22:15:53.544941 [RX_INPUT] configuration <<<<<
6183 22:15:53.547850 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6184 22:15:53.554591 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6185 22:15:53.561094 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6186 22:15:53.567211 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6187 22:15:53.570642 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6188 22:15:53.577720 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6189 22:15:53.580822 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6190 22:15:53.587007 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6191 22:15:53.591454 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6192 22:15:53.593594 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6193 22:15:53.597432 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6194 22:15:53.603788 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6195 22:15:53.606920 ===================================
6196 22:15:53.610726 LPDDR4 DRAM CONFIGURATION
6197 22:15:53.613794 ===================================
6198 22:15:53.614405 EX_ROW_EN[0] = 0x0
6199 22:15:53.616869 EX_ROW_EN[1] = 0x0
6200 22:15:53.617357 LP4Y_EN = 0x0
6201 22:15:53.620025 WORK_FSP = 0x0
6202 22:15:53.620515 WL = 0x2
6203 22:15:53.623955 RL = 0x2
6204 22:15:53.624534 BL = 0x2
6205 22:15:53.626740 RPST = 0x0
6206 22:15:53.627321 RD_PRE = 0x0
6207 22:15:53.630807 WR_PRE = 0x1
6208 22:15:53.633911 WR_PST = 0x0
6209 22:15:53.634538 DBI_WR = 0x0
6210 22:15:53.636883 DBI_RD = 0x0
6211 22:15:53.637468 OTF = 0x1
6212 22:15:53.640920 ===================================
6213 22:15:53.643587 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6214 22:15:53.647013 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6215 22:15:53.653228 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6216 22:15:53.656569 ===================================
6217 22:15:53.659641 LPDDR4 DRAM CONFIGURATION
6218 22:15:53.663035 ===================================
6219 22:15:53.663622 EX_ROW_EN[0] = 0x10
6220 22:15:53.666621 EX_ROW_EN[1] = 0x0
6221 22:15:53.667271 LP4Y_EN = 0x0
6222 22:15:53.670157 WORK_FSP = 0x0
6223 22:15:53.670801 WL = 0x2
6224 22:15:53.672843 RL = 0x2
6225 22:15:53.673336 BL = 0x2
6226 22:15:53.676235 RPST = 0x0
6227 22:15:53.676721 RD_PRE = 0x0
6228 22:15:53.679344 WR_PRE = 0x1
6229 22:15:53.683087 WR_PST = 0x0
6230 22:15:53.683681 DBI_WR = 0x0
6231 22:15:53.687077 DBI_RD = 0x0
6232 22:15:53.687564 OTF = 0x1
6233 22:15:53.689126 ===================================
6234 22:15:53.695932 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6235 22:15:53.699664 nWR fixed to 30
6236 22:15:53.702820 [ModeRegInit_LP4] CH0 RK0
6237 22:15:53.703311 [ModeRegInit_LP4] CH0 RK1
6238 22:15:53.706218 [ModeRegInit_LP4] CH1 RK0
6239 22:15:53.709628 [ModeRegInit_LP4] CH1 RK1
6240 22:15:53.710207 match AC timing 19
6241 22:15:53.716032 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6242 22:15:53.719799 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6243 22:15:53.723423 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6244 22:15:53.729951 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6245 22:15:53.732814 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6246 22:15:53.733395 ==
6247 22:15:53.736137 Dram Type= 6, Freq= 0, CH_0, rank 0
6248 22:15:53.739941 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6249 22:15:53.740533 ==
6250 22:15:53.746732 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6251 22:15:53.752756 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6252 22:15:53.756215 [CA 0] Center 36 (8~64) winsize 57
6253 22:15:53.759630 [CA 1] Center 36 (8~64) winsize 57
6254 22:15:53.762750 [CA 2] Center 36 (8~64) winsize 57
6255 22:15:53.766119 [CA 3] Center 36 (8~64) winsize 57
6256 22:15:53.766753 [CA 4] Center 36 (8~64) winsize 57
6257 22:15:53.769747 [CA 5] Center 36 (8~64) winsize 57
6258 22:15:53.770235
6259 22:15:53.776013 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6260 22:15:53.776610
6261 22:15:53.779366 [CATrainingPosCal] consider 1 rank data
6262 22:15:53.782257 u2DelayCellTimex100 = 270/100 ps
6263 22:15:53.786133 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6264 22:15:53.789003 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6265 22:15:53.792442 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6266 22:15:53.796170 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6267 22:15:53.798916 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6268 22:15:53.802065 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6269 22:15:53.802748
6270 22:15:53.805328 CA PerBit enable=1, Macro0, CA PI delay=36
6271 22:15:53.805820
6272 22:15:53.809120 [CBTSetCACLKResult] CA Dly = 36
6273 22:15:53.812081 CS Dly: 1 (0~32)
6274 22:15:53.812571 ==
6275 22:15:53.815131 Dram Type= 6, Freq= 0, CH_0, rank 1
6276 22:15:53.818425 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6277 22:15:53.818921 ==
6278 22:15:53.825236 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6279 22:15:53.831726 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6280 22:15:53.835503 [CA 0] Center 36 (8~64) winsize 57
6281 22:15:53.839057 [CA 1] Center 36 (8~64) winsize 57
6282 22:15:53.841928 [CA 2] Center 36 (8~64) winsize 57
6283 22:15:53.842552 [CA 3] Center 36 (8~64) winsize 57
6284 22:15:53.845757 [CA 4] Center 36 (8~64) winsize 57
6285 22:15:53.848396 [CA 5] Center 36 (8~64) winsize 57
6286 22:15:53.848982
6287 22:15:53.855042 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6288 22:15:53.855626
6289 22:15:53.858882 [CATrainingPosCal] consider 2 rank data
6290 22:15:53.862290 u2DelayCellTimex100 = 270/100 ps
6291 22:15:53.864526 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6292 22:15:53.868420 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6293 22:15:53.871487 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6294 22:15:53.875150 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6295 22:15:53.878232 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6296 22:15:53.881144 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6297 22:15:53.881718
6298 22:15:53.884597 CA PerBit enable=1, Macro0, CA PI delay=36
6299 22:15:53.885167
6300 22:15:53.887768 [CBTSetCACLKResult] CA Dly = 36
6301 22:15:53.891009 CS Dly: 1 (0~32)
6302 22:15:53.891565
6303 22:15:53.894811 ----->DramcWriteLeveling(PI) begin...
6304 22:15:53.895387 ==
6305 22:15:53.897431 Dram Type= 6, Freq= 0, CH_0, rank 0
6306 22:15:53.900665 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6307 22:15:53.901141 ==
6308 22:15:53.904167 Write leveling (Byte 0): 40 => 8
6309 22:15:53.907457 Write leveling (Byte 1): 32 => 0
6310 22:15:53.911049 DramcWriteLeveling(PI) end<-----
6311 22:15:53.911519
6312 22:15:53.911981 ==
6313 22:15:53.914095 Dram Type= 6, Freq= 0, CH_0, rank 0
6314 22:15:53.917223 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6315 22:15:53.917694 ==
6316 22:15:53.920864 [Gating] SW mode calibration
6317 22:15:53.927872 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6318 22:15:53.933992 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6319 22:15:53.937272 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6320 22:15:53.944001 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6321 22:15:53.947288 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6322 22:15:53.950927 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6323 22:15:53.957243 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6324 22:15:53.960319 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6325 22:15:53.963943 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6326 22:15:53.967502 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6327 22:15:53.973804 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6328 22:15:53.977105 Total UI for P1: 0, mck2ui 16
6329 22:15:53.980784 best dqsien dly found for B0: ( 0, 14, 24)
6330 22:15:53.983236 Total UI for P1: 0, mck2ui 16
6331 22:15:53.988093 best dqsien dly found for B1: ( 0, 14, 24)
6332 22:15:53.989656 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6333 22:15:53.993609 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6334 22:15:53.993780
6335 22:15:53.996309 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6336 22:15:53.999642 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6337 22:15:54.003408 [Gating] SW calibration Done
6338 22:15:54.003626 ==
6339 22:15:54.005958 Dram Type= 6, Freq= 0, CH_0, rank 0
6340 22:15:54.009265 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6341 22:15:54.012736 ==
6342 22:15:54.013147 RX Vref Scan: 0
6343 22:15:54.013476
6344 22:15:54.016622 RX Vref 0 -> 0, step: 1
6345 22:15:54.017312
6346 22:15:54.019913 RX Delay -410 -> 252, step: 16
6347 22:15:54.022690 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6348 22:15:54.026290 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6349 22:15:54.029587 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6350 22:15:54.036268 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6351 22:15:54.039519 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6352 22:15:54.042831 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6353 22:15:54.050091 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6354 22:15:54.052435 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6355 22:15:54.055918 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6356 22:15:54.059330 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6357 22:15:54.065649 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6358 22:15:54.069061 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6359 22:15:54.072437 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6360 22:15:54.075897 iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480
6361 22:15:54.082914 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6362 22:15:54.085829 iDelay=230, Bit 15, Center -27 (-266 ~ 213) 480
6363 22:15:54.086435 ==
6364 22:15:54.088955 Dram Type= 6, Freq= 0, CH_0, rank 0
6365 22:15:54.092463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6366 22:15:54.092921 ==
6367 22:15:54.095345 DQS Delay:
6368 22:15:54.095808 DQS0 = 27, DQS1 = 43
6369 22:15:54.098797 DQM Delay:
6370 22:15:54.099259 DQM0 = 12, DQM1 = 13
6371 22:15:54.099624 DQ Delay:
6372 22:15:54.102131 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6373 22:15:54.105045 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =24
6374 22:15:54.108982 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6375 22:15:54.111710 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6376 22:15:54.112178
6377 22:15:54.112542
6378 22:15:54.112878 ==
6379 22:15:54.115178 Dram Type= 6, Freq= 0, CH_0, rank 0
6380 22:15:54.121643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6381 22:15:54.122127 ==
6382 22:15:54.122557
6383 22:15:54.122908
6384 22:15:54.123238 TX Vref Scan disable
6385 22:15:54.124777 == TX Byte 0 ==
6386 22:15:54.128812 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6387 22:15:54.131711 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6388 22:15:54.135005 == TX Byte 1 ==
6389 22:15:54.138678 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6390 22:15:54.142190 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6391 22:15:54.145345 ==
6392 22:15:54.145863 Dram Type= 6, Freq= 0, CH_0, rank 0
6393 22:15:54.151445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6394 22:15:54.152009 ==
6395 22:15:54.152386
6396 22:15:54.152731
6397 22:15:54.154878 TX Vref Scan disable
6398 22:15:54.155441 == TX Byte 0 ==
6399 22:15:54.158483 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6400 22:15:54.165498 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6401 22:15:54.166067 == TX Byte 1 ==
6402 22:15:54.167746 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6403 22:15:54.174989 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6404 22:15:54.175555
6405 22:15:54.175929 [DATLAT]
6406 22:15:54.176279 Freq=400, CH0 RK0
6407 22:15:54.177922
6408 22:15:54.178419 DATLAT Default: 0xf
6409 22:15:54.181256 0, 0xFFFF, sum = 0
6410 22:15:54.181826 1, 0xFFFF, sum = 0
6411 22:15:54.184647 2, 0xFFFF, sum = 0
6412 22:15:54.185218 3, 0xFFFF, sum = 0
6413 22:15:54.188100 4, 0xFFFF, sum = 0
6414 22:15:54.188670 5, 0xFFFF, sum = 0
6415 22:15:54.190703 6, 0xFFFF, sum = 0
6416 22:15:54.191182 7, 0xFFFF, sum = 0
6417 22:15:54.194318 8, 0xFFFF, sum = 0
6418 22:15:54.194929 9, 0xFFFF, sum = 0
6419 22:15:54.198430 10, 0xFFFF, sum = 0
6420 22:15:54.199013 11, 0xFFFF, sum = 0
6421 22:15:54.201270 12, 0xFFFF, sum = 0
6422 22:15:54.201837 13, 0x0, sum = 1
6423 22:15:54.204131 14, 0x0, sum = 2
6424 22:15:54.204706 15, 0x0, sum = 3
6425 22:15:54.207583 16, 0x0, sum = 4
6426 22:15:54.208161 best_step = 14
6427 22:15:54.208538
6428 22:15:54.208881 ==
6429 22:15:54.210685 Dram Type= 6, Freq= 0, CH_0, rank 0
6430 22:15:54.217558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6431 22:15:54.218149 ==
6432 22:15:54.218602 RX Vref Scan: 1
6433 22:15:54.218961
6434 22:15:54.220693 RX Vref 0 -> 0, step: 1
6435 22:15:54.221166
6436 22:15:54.224412 RX Delay -327 -> 252, step: 8
6437 22:15:54.224982
6438 22:15:54.227936 Set Vref, RX VrefLevel [Byte0]: 57
6439 22:15:54.230776 [Byte1]: 50
6440 22:15:54.231249
6441 22:15:54.234116 Final RX Vref Byte 0 = 57 to rank0
6442 22:15:54.237352 Final RX Vref Byte 1 = 50 to rank0
6443 22:15:54.241267 Final RX Vref Byte 0 = 57 to rank1
6444 22:15:54.244024 Final RX Vref Byte 1 = 50 to rank1==
6445 22:15:54.247362 Dram Type= 6, Freq= 0, CH_0, rank 0
6446 22:15:54.251042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6447 22:15:54.254167 ==
6448 22:15:54.254758 DQS Delay:
6449 22:15:54.255137 DQS0 = 28, DQS1 = 48
6450 22:15:54.257810 DQM Delay:
6451 22:15:54.258431 DQM0 = 11, DQM1 = 14
6452 22:15:54.260450 DQ Delay:
6453 22:15:54.260921 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6454 22:15:54.263560 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6455 22:15:54.267060 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6456 22:15:54.270459 DQ12 =20, DQ13 =16, DQ14 =28, DQ15 =24
6457 22:15:54.270888
6458 22:15:54.271224
6459 22:15:54.281006 [DQSOSCAuto] RK0, (LSB)MR18= 0xb3ab, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 387 ps
6460 22:15:54.284081 CH0 RK0: MR19=C0C, MR18=B3AB
6461 22:15:54.290487 CH0_RK0: MR19=0xC0C, MR18=0xB3AB, DQSOSC=387, MR23=63, INC=394, DEC=262
6462 22:15:54.291010 ==
6463 22:15:54.293763 Dram Type= 6, Freq= 0, CH_0, rank 1
6464 22:15:54.297276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6465 22:15:54.297802 ==
6466 22:15:54.301138 [Gating] SW mode calibration
6467 22:15:54.306755 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6468 22:15:54.310196 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6469 22:15:54.317012 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6470 22:15:54.320139 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6471 22:15:54.323819 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6472 22:15:54.330030 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6473 22:15:54.333703 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6474 22:15:54.336894 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6475 22:15:54.343305 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6476 22:15:54.346762 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6477 22:15:54.349727 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6478 22:15:54.353821 Total UI for P1: 0, mck2ui 16
6479 22:15:54.356403 best dqsien dly found for B0: ( 0, 14, 24)
6480 22:15:54.360467 Total UI for P1: 0, mck2ui 16
6481 22:15:54.363536 best dqsien dly found for B1: ( 0, 14, 24)
6482 22:15:54.366221 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6483 22:15:54.373562 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6484 22:15:54.374092
6485 22:15:54.376640 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6486 22:15:54.379603 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6487 22:15:54.383340 [Gating] SW calibration Done
6488 22:15:54.383870 ==
6489 22:15:54.386950 Dram Type= 6, Freq= 0, CH_0, rank 1
6490 22:15:54.389793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6491 22:15:54.390224 ==
6492 22:15:54.392884 RX Vref Scan: 0
6493 22:15:54.393409
6494 22:15:54.393745 RX Vref 0 -> 0, step: 1
6495 22:15:54.394063
6496 22:15:54.396596 RX Delay -410 -> 252, step: 16
6497 22:15:54.399789 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6498 22:15:54.406913 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6499 22:15:54.409626 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6500 22:15:54.412679 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6501 22:15:54.415975 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6502 22:15:54.422672 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6503 22:15:54.426009 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6504 22:15:54.429027 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6505 22:15:54.432765 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6506 22:15:54.438920 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6507 22:15:54.442703 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6508 22:15:54.446288 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6509 22:15:54.452230 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6510 22:15:54.455990 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6511 22:15:54.459812 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6512 22:15:54.462608 iDelay=230, Bit 15, Center -27 (-266 ~ 213) 480
6513 22:15:54.463134 ==
6514 22:15:54.465771 Dram Type= 6, Freq= 0, CH_0, rank 1
6515 22:15:54.472113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6516 22:15:54.472542 ==
6517 22:15:54.472878 DQS Delay:
6518 22:15:54.475618 DQS0 = 27, DQS1 = 43
6519 22:15:54.476184 DQM Delay:
6520 22:15:54.478824 DQM0 = 9, DQM1 = 15
6521 22:15:54.479295 DQ Delay:
6522 22:15:54.482083 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6523 22:15:54.485895 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6524 22:15:54.486482 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =16
6525 22:15:54.489044 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =16
6526 22:15:54.492572
6527 22:15:54.493146
6528 22:15:54.493513 ==
6529 22:15:54.495504 Dram Type= 6, Freq= 0, CH_0, rank 1
6530 22:15:54.499828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6531 22:15:54.500399 ==
6532 22:15:54.500766
6533 22:15:54.501108
6534 22:15:54.501976 TX Vref Scan disable
6535 22:15:54.502504 == TX Byte 0 ==
6536 22:15:54.505455 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6537 22:15:54.511890 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6538 22:15:54.512465 == TX Byte 1 ==
6539 22:15:54.515664 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6540 22:15:54.522062 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6541 22:15:54.522608 ==
6542 22:15:54.525084 Dram Type= 6, Freq= 0, CH_0, rank 1
6543 22:15:54.528588 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6544 22:15:54.529160 ==
6545 22:15:54.529544
6546 22:15:54.529894
6547 22:15:54.531801 TX Vref Scan disable
6548 22:15:54.532281 == TX Byte 0 ==
6549 22:15:54.535202 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6550 22:15:54.541432 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6551 22:15:54.541912 == TX Byte 1 ==
6552 22:15:54.544841 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6553 22:15:54.551539 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6554 22:15:54.551972
6555 22:15:54.552314 [DATLAT]
6556 22:15:54.555065 Freq=400, CH0 RK1
6557 22:15:54.555498
6558 22:15:54.555839 DATLAT Default: 0xe
6559 22:15:54.558061 0, 0xFFFF, sum = 0
6560 22:15:54.558534 1, 0xFFFF, sum = 0
6561 22:15:54.561659 2, 0xFFFF, sum = 0
6562 22:15:54.562187 3, 0xFFFF, sum = 0
6563 22:15:54.564652 4, 0xFFFF, sum = 0
6564 22:15:54.565090 5, 0xFFFF, sum = 0
6565 22:15:54.568171 6, 0xFFFF, sum = 0
6566 22:15:54.568607 7, 0xFFFF, sum = 0
6567 22:15:54.571194 8, 0xFFFF, sum = 0
6568 22:15:54.571634 9, 0xFFFF, sum = 0
6569 22:15:54.574894 10, 0xFFFF, sum = 0
6570 22:15:54.575335 11, 0xFFFF, sum = 0
6571 22:15:54.578780 12, 0xFFFF, sum = 0
6572 22:15:54.579316 13, 0x0, sum = 1
6573 22:15:54.581545 14, 0x0, sum = 2
6574 22:15:54.582078 15, 0x0, sum = 3
6575 22:15:54.584879 16, 0x0, sum = 4
6576 22:15:54.585408 best_step = 14
6577 22:15:54.585751
6578 22:15:54.586069 ==
6579 22:15:54.588010 Dram Type= 6, Freq= 0, CH_0, rank 1
6580 22:15:54.595334 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6581 22:15:54.595864 ==
6582 22:15:54.596209 RX Vref Scan: 0
6583 22:15:54.596526
6584 22:15:54.598027 RX Vref 0 -> 0, step: 1
6585 22:15:54.598493
6586 22:15:54.601836 RX Delay -327 -> 252, step: 8
6587 22:15:54.607963 iDelay=217, Bit 0, Center -20 (-247 ~ 208) 456
6588 22:15:54.611014 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6589 22:15:54.614421 iDelay=217, Bit 2, Center -20 (-239 ~ 200) 440
6590 22:15:54.618013 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6591 22:15:54.624484 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6592 22:15:54.627862 iDelay=217, Bit 5, Center -28 (-255 ~ 200) 456
6593 22:15:54.630791 iDelay=217, Bit 6, Center -12 (-239 ~ 216) 456
6594 22:15:54.634114 iDelay=217, Bit 7, Center -12 (-239 ~ 216) 456
6595 22:15:54.640670 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6596 22:15:54.644244 iDelay=217, Bit 9, Center -40 (-263 ~ 184) 448
6597 22:15:54.647274 iDelay=217, Bit 10, Center -28 (-255 ~ 200) 456
6598 22:15:54.654294 iDelay=217, Bit 11, Center -36 (-263 ~ 192) 456
6599 22:15:54.657788 iDelay=217, Bit 12, Center -24 (-247 ~ 200) 448
6600 22:15:54.661050 iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440
6601 22:15:54.663831 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6602 22:15:54.670734 iDelay=217, Bit 15, Center -20 (-239 ~ 200) 440
6603 22:15:54.671214 ==
6604 22:15:54.673616 Dram Type= 6, Freq= 0, CH_0, rank 1
6605 22:15:54.677828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6606 22:15:54.678433 ==
6607 22:15:54.678819 DQS Delay:
6608 22:15:54.680853 DQS0 = 28, DQS1 = 40
6609 22:15:54.681424 DQM Delay:
6610 22:15:54.684106 DQM0 = 9, DQM1 = 12
6611 22:15:54.684676 DQ Delay:
6612 22:15:54.687247 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =4
6613 22:15:54.690647 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6614 22:15:54.694025 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =4
6615 22:15:54.697292 DQ12 =16, DQ13 =20, DQ14 =20, DQ15 =20
6616 22:15:54.697859
6617 22:15:54.698233
6618 22:15:54.703818 [DQSOSCAuto] RK1, (LSB)MR18= 0xbf73, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 386 ps
6619 22:15:54.707242 CH0 RK1: MR19=C0C, MR18=BF73
6620 22:15:54.713663 CH0_RK1: MR19=0xC0C, MR18=0xBF73, DQSOSC=386, MR23=63, INC=396, DEC=264
6621 22:15:54.717351 [RxdqsGatingPostProcess] freq 400
6622 22:15:54.723550 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6623 22:15:54.726909 best DQS0 dly(2T, 0.5T) = (0, 10)
6624 22:15:54.730019 best DQS1 dly(2T, 0.5T) = (0, 10)
6625 22:15:54.733495 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6626 22:15:54.736580 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6627 22:15:54.737060 best DQS0 dly(2T, 0.5T) = (0, 10)
6628 22:15:54.739762 best DQS1 dly(2T, 0.5T) = (0, 10)
6629 22:15:54.743489 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6630 22:15:54.746423 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6631 22:15:54.749827 Pre-setting of DQS Precalculation
6632 22:15:54.756747 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6633 22:15:54.757318 ==
6634 22:15:54.759891 Dram Type= 6, Freq= 0, CH_1, rank 0
6635 22:15:54.763055 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6636 22:15:54.763530 ==
6637 22:15:54.769525 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6638 22:15:54.776535 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6639 22:15:54.780184 [CA 0] Center 36 (8~64) winsize 57
6640 22:15:54.780754 [CA 1] Center 36 (8~64) winsize 57
6641 22:15:54.782587 [CA 2] Center 36 (8~64) winsize 57
6642 22:15:54.786322 [CA 3] Center 36 (8~64) winsize 57
6643 22:15:54.789612 [CA 4] Center 36 (8~64) winsize 57
6644 22:15:54.793131 [CA 5] Center 36 (8~64) winsize 57
6645 22:15:54.793713
6646 22:15:54.795992 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6647 22:15:54.796562
6648 22:15:54.802786 [CATrainingPosCal] consider 1 rank data
6649 22:15:54.803358 u2DelayCellTimex100 = 270/100 ps
6650 22:15:54.809420 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6651 22:15:54.812358 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6652 22:15:54.816264 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6653 22:15:54.819244 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6654 22:15:54.822259 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6655 22:15:54.825870 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6656 22:15:54.826345
6657 22:15:54.829413 CA PerBit enable=1, Macro0, CA PI delay=36
6658 22:15:54.829885
6659 22:15:54.832342 [CBTSetCACLKResult] CA Dly = 36
6660 22:15:54.835780 CS Dly: 1 (0~32)
6661 22:15:54.836305 ==
6662 22:15:54.839312 Dram Type= 6, Freq= 0, CH_1, rank 1
6663 22:15:54.841999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6664 22:15:54.842489 ==
6665 22:15:54.849250 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6666 22:15:54.852483 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6667 22:15:54.855487 [CA 0] Center 36 (8~64) winsize 57
6668 22:15:54.859262 [CA 1] Center 36 (8~64) winsize 57
6669 22:15:54.862003 [CA 2] Center 36 (8~64) winsize 57
6670 22:15:54.865821 [CA 3] Center 36 (8~64) winsize 57
6671 22:15:54.868467 [CA 4] Center 36 (8~64) winsize 57
6672 22:15:54.871815 [CA 5] Center 36 (8~64) winsize 57
6673 22:15:54.872289
6674 22:15:54.875527 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6675 22:15:54.875999
6676 22:15:54.878517 [CATrainingPosCal] consider 2 rank data
6677 22:15:54.882103 u2DelayCellTimex100 = 270/100 ps
6678 22:15:54.885083 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6679 22:15:54.888758 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6680 22:15:54.895070 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6681 22:15:54.898698 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6682 22:15:54.901984 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6683 22:15:54.905359 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6684 22:15:54.905934
6685 22:15:54.908654 CA PerBit enable=1, Macro0, CA PI delay=36
6686 22:15:54.909234
6687 22:15:54.912127 [CBTSetCACLKResult] CA Dly = 36
6688 22:15:54.912703 CS Dly: 1 (0~32)
6689 22:15:54.913078
6690 22:15:54.914875 ----->DramcWriteLeveling(PI) begin...
6691 22:15:54.918601 ==
6692 22:15:54.921490 Dram Type= 6, Freq= 0, CH_1, rank 0
6693 22:15:54.925242 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6694 22:15:54.925828 ==
6695 22:15:54.928424 Write leveling (Byte 0): 40 => 8
6696 22:15:54.931508 Write leveling (Byte 1): 32 => 0
6697 22:15:54.935031 DramcWriteLeveling(PI) end<-----
6698 22:15:54.935603
6699 22:15:54.935974 ==
6700 22:15:54.938592 Dram Type= 6, Freq= 0, CH_1, rank 0
6701 22:15:54.941975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6702 22:15:54.942591 ==
6703 22:15:54.944708 [Gating] SW mode calibration
6704 22:15:54.951191 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6705 22:15:54.958485 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6706 22:15:54.961070 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6707 22:15:54.964791 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6708 22:15:54.971663 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6709 22:15:54.974711 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6710 22:15:54.978218 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6711 22:15:54.981457 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6712 22:15:54.987727 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6713 22:15:54.990923 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6714 22:15:54.994229 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6715 22:15:54.998523 Total UI for P1: 0, mck2ui 16
6716 22:15:55.001286 best dqsien dly found for B0: ( 0, 14, 24)
6717 22:15:55.004738 Total UI for P1: 0, mck2ui 16
6718 22:15:55.007578 best dqsien dly found for B1: ( 0, 14, 24)
6719 22:15:55.011015 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6720 22:15:55.018891 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6721 22:15:55.019472
6722 22:15:55.020884 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6723 22:15:55.025035 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6724 22:15:55.027494 [Gating] SW calibration Done
6725 22:15:55.028066 ==
6726 22:15:55.030764 Dram Type= 6, Freq= 0, CH_1, rank 0
6727 22:15:55.034339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6728 22:15:55.034958 ==
6729 22:15:55.037475 RX Vref Scan: 0
6730 22:15:55.037947
6731 22:15:55.038316 RX Vref 0 -> 0, step: 1
6732 22:15:55.038692
6733 22:15:55.040676 RX Delay -410 -> 252, step: 16
6734 22:15:55.044289 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6735 22:15:55.050883 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6736 22:15:55.054246 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6737 22:15:55.057153 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6738 22:15:55.060216 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6739 22:15:55.067586 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6740 22:15:55.070343 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6741 22:15:55.073990 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6742 22:15:55.078008 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6743 22:15:55.083875 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6744 22:15:55.087586 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6745 22:15:55.090965 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6746 22:15:55.096753 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6747 22:15:55.100221 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6748 22:15:55.103528 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6749 22:15:55.106942 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6750 22:15:55.110480 ==
6751 22:15:55.111061 Dram Type= 6, Freq= 0, CH_1, rank 0
6752 22:15:55.117095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6753 22:15:55.117674 ==
6754 22:15:55.118049 DQS Delay:
6755 22:15:55.120225 DQS0 = 27, DQS1 = 43
6756 22:15:55.120864 DQM Delay:
6757 22:15:55.123237 DQM0 = 9, DQM1 = 20
6758 22:15:55.123733 DQ Delay:
6759 22:15:55.127209 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6760 22:15:55.129930 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6761 22:15:55.133187 DQ8 =0, DQ9 =8, DQ10 =24, DQ11 =16
6762 22:15:55.137655 DQ12 =32, DQ13 =24, DQ14 =24, DQ15 =32
6763 22:15:55.138227
6764 22:15:55.138631
6765 22:15:55.138975 ==
6766 22:15:55.139768 Dram Type= 6, Freq= 0, CH_1, rank 0
6767 22:15:55.144836 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6768 22:15:55.145418 ==
6769 22:15:55.145793
6770 22:15:55.146136
6771 22:15:55.146824 TX Vref Scan disable
6772 22:15:55.147186 == TX Byte 0 ==
6773 22:15:55.153483 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6774 22:15:55.156407 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6775 22:15:55.156985 == TX Byte 1 ==
6776 22:15:55.163396 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6777 22:15:55.166416 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6778 22:15:55.167101 ==
6779 22:15:55.169614 Dram Type= 6, Freq= 0, CH_1, rank 0
6780 22:15:55.172791 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6781 22:15:55.173414 ==
6782 22:15:55.173804
6783 22:15:55.174154
6784 22:15:55.176173 TX Vref Scan disable
6785 22:15:55.176655 == TX Byte 0 ==
6786 22:15:55.182757 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6787 22:15:55.186281 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6788 22:15:55.186892 == TX Byte 1 ==
6789 22:15:55.192784 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6790 22:15:55.196140 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6791 22:15:55.196728
6792 22:15:55.197107 [DATLAT]
6793 22:15:55.199031 Freq=400, CH1 RK0
6794 22:15:55.199509
6795 22:15:55.199880 DATLAT Default: 0xf
6796 22:15:55.202511 0, 0xFFFF, sum = 0
6797 22:15:55.202996 1, 0xFFFF, sum = 0
6798 22:15:55.205849 2, 0xFFFF, sum = 0
6799 22:15:55.209564 3, 0xFFFF, sum = 0
6800 22:15:55.210136 4, 0xFFFF, sum = 0
6801 22:15:55.212620 5, 0xFFFF, sum = 0
6802 22:15:55.213192 6, 0xFFFF, sum = 0
6803 22:15:55.215624 7, 0xFFFF, sum = 0
6804 22:15:55.216106 8, 0xFFFF, sum = 0
6805 22:15:55.219290 9, 0xFFFF, sum = 0
6806 22:15:55.219865 10, 0xFFFF, sum = 0
6807 22:15:55.222524 11, 0xFFFF, sum = 0
6808 22:15:55.223007 12, 0xFFFF, sum = 0
6809 22:15:55.225612 13, 0x0, sum = 1
6810 22:15:55.226189 14, 0x0, sum = 2
6811 22:15:55.228986 15, 0x0, sum = 3
6812 22:15:55.229565 16, 0x0, sum = 4
6813 22:15:55.232438 best_step = 14
6814 22:15:55.232915
6815 22:15:55.233291 ==
6816 22:15:55.235628 Dram Type= 6, Freq= 0, CH_1, rank 0
6817 22:15:55.239298 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6818 22:15:55.239872 ==
6819 22:15:55.240252 RX Vref Scan: 1
6820 22:15:55.242153
6821 22:15:55.242755 RX Vref 0 -> 0, step: 1
6822 22:15:55.243135
6823 22:15:55.245891 RX Delay -327 -> 252, step: 8
6824 22:15:55.246495
6825 22:15:55.248906 Set Vref, RX VrefLevel [Byte0]: 51
6826 22:15:55.252064 [Byte1]: 50
6827 22:15:55.256495
6828 22:15:55.257068 Final RX Vref Byte 0 = 51 to rank0
6829 22:15:55.260344 Final RX Vref Byte 1 = 50 to rank0
6830 22:15:55.262724 Final RX Vref Byte 0 = 51 to rank1
6831 22:15:55.266085 Final RX Vref Byte 1 = 50 to rank1==
6832 22:15:55.269237 Dram Type= 6, Freq= 0, CH_1, rank 0
6833 22:15:55.276046 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6834 22:15:55.276605 ==
6835 22:15:55.276986 DQS Delay:
6836 22:15:55.279522 DQS0 = 32, DQS1 = 40
6837 22:15:55.280133 DQM Delay:
6838 22:15:55.282780 DQM0 = 11, DQM1 = 12
6839 22:15:55.283259 DQ Delay:
6840 22:15:55.285894 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6841 22:15:55.289078 DQ4 =8, DQ5 =24, DQ6 =20, DQ7 =8
6842 22:15:55.289661 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
6843 22:15:55.295305 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6844 22:15:55.295859
6845 22:15:55.296235
6846 22:15:55.302617 [DQSOSCAuto] RK0, (LSB)MR18= 0x92cc, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 391 ps
6847 22:15:55.305453 CH1 RK0: MR19=C0C, MR18=92CC
6848 22:15:55.312176 CH1_RK0: MR19=0xC0C, MR18=0x92CC, DQSOSC=384, MR23=63, INC=400, DEC=267
6849 22:15:55.312744 ==
6850 22:15:55.315816 Dram Type= 6, Freq= 0, CH_1, rank 1
6851 22:15:55.319160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6852 22:15:55.319737 ==
6853 22:15:55.322141 [Gating] SW mode calibration
6854 22:15:55.328710 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6855 22:15:55.335215 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6856 22:15:55.338589 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6857 22:15:55.341896 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6858 22:15:55.348252 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6859 22:15:55.351626 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6860 22:15:55.354979 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6861 22:15:55.361812 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6862 22:15:55.365055 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6863 22:15:55.368209 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6864 22:15:55.375576 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6865 22:15:55.378083 Total UI for P1: 0, mck2ui 16
6866 22:15:55.381406 best dqsien dly found for B0: ( 0, 14, 24)
6867 22:15:55.381999 Total UI for P1: 0, mck2ui 16
6868 22:15:55.388430 best dqsien dly found for B1: ( 0, 14, 24)
6869 22:15:55.391557 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6870 22:15:55.394830 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6871 22:15:55.395378
6872 22:15:55.398009 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6873 22:15:55.401438 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6874 22:15:55.404607 [Gating] SW calibration Done
6875 22:15:55.405176 ==
6876 22:15:55.407999 Dram Type= 6, Freq= 0, CH_1, rank 1
6877 22:15:55.411795 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6878 22:15:55.412371 ==
6879 22:15:55.414701 RX Vref Scan: 0
6880 22:15:55.415176
6881 22:15:55.415549 RX Vref 0 -> 0, step: 1
6882 22:15:55.417711
6883 22:15:55.418196 RX Delay -410 -> 252, step: 16
6884 22:15:55.424782 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6885 22:15:55.428224 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6886 22:15:55.430952 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6887 22:15:55.434492 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6888 22:15:55.441369 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6889 22:15:55.445199 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6890 22:15:55.447860 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6891 22:15:55.451034 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6892 22:15:55.457813 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6893 22:15:55.461182 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6894 22:15:55.464335 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6895 22:15:55.470554 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6896 22:15:55.474147 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6897 22:15:55.477352 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6898 22:15:55.481805 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6899 22:15:55.487311 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6900 22:15:55.487994 ==
6901 22:15:55.490318 Dram Type= 6, Freq= 0, CH_1, rank 1
6902 22:15:55.493678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6903 22:15:55.494328 ==
6904 22:15:55.494761 DQS Delay:
6905 22:15:55.496845 DQS0 = 35, DQS1 = 43
6906 22:15:55.497321 DQM Delay:
6907 22:15:55.500083 DQM0 = 16, DQM1 = 19
6908 22:15:55.500656 DQ Delay:
6909 22:15:55.503678 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6910 22:15:55.506918 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =16
6911 22:15:55.510249 DQ8 =0, DQ9 =8, DQ10 =24, DQ11 =16
6912 22:15:55.513482 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =32
6913 22:15:55.514052
6914 22:15:55.514481
6915 22:15:55.514848 ==
6916 22:15:55.516828 Dram Type= 6, Freq= 0, CH_1, rank 1
6917 22:15:55.520359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6918 22:15:55.523257 ==
6919 22:15:55.523736
6920 22:15:55.524109
6921 22:15:55.524458 TX Vref Scan disable
6922 22:15:55.527181 == TX Byte 0 ==
6923 22:15:55.530294 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6924 22:15:55.533345 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6925 22:15:55.536748 == TX Byte 1 ==
6926 22:15:55.540304 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6927 22:15:55.543185 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6928 22:15:55.543756 ==
6929 22:15:55.547052 Dram Type= 6, Freq= 0, CH_1, rank 1
6930 22:15:55.550346 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6931 22:15:55.553339 ==
6932 22:15:55.553906
6933 22:15:55.554284
6934 22:15:55.554665 TX Vref Scan disable
6935 22:15:55.556846 == TX Byte 0 ==
6936 22:15:55.559780 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6937 22:15:55.563048 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6938 22:15:55.566886 == TX Byte 1 ==
6939 22:15:55.570685 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6940 22:15:55.572909 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6941 22:15:55.573479
6942 22:15:55.575970 [DATLAT]
6943 22:15:55.576452 Freq=400, CH1 RK1
6944 22:15:55.577086
6945 22:15:55.579235 DATLAT Default: 0xe
6946 22:15:55.579703 0, 0xFFFF, sum = 0
6947 22:15:55.582993 1, 0xFFFF, sum = 0
6948 22:15:55.583565 2, 0xFFFF, sum = 0
6949 22:15:55.586006 3, 0xFFFF, sum = 0
6950 22:15:55.586510 4, 0xFFFF, sum = 0
6951 22:15:55.589523 5, 0xFFFF, sum = 0
6952 22:15:55.590158 6, 0xFFFF, sum = 0
6953 22:15:55.592800 7, 0xFFFF, sum = 0
6954 22:15:55.593373 8, 0xFFFF, sum = 0
6955 22:15:55.596182 9, 0xFFFF, sum = 0
6956 22:15:55.596658 10, 0xFFFF, sum = 0
6957 22:15:55.599619 11, 0xFFFF, sum = 0
6958 22:15:55.602476 12, 0xFFFF, sum = 0
6959 22:15:55.602957 13, 0x0, sum = 1
6960 22:15:55.606042 14, 0x0, sum = 2
6961 22:15:55.606631 15, 0x0, sum = 3
6962 22:15:55.607009 16, 0x0, sum = 4
6963 22:15:55.609490 best_step = 14
6964 22:15:55.610048
6965 22:15:55.610520 ==
6966 22:15:55.612526 Dram Type= 6, Freq= 0, CH_1, rank 1
6967 22:15:55.615514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6968 22:15:55.615986 ==
6969 22:15:55.619482 RX Vref Scan: 0
6970 22:15:55.619950
6971 22:15:55.620372 RX Vref 0 -> 0, step: 1
6972 22:15:55.622254
6973 22:15:55.622796 RX Delay -327 -> 252, step: 8
6974 22:15:55.630706 iDelay=217, Bit 0, Center -20 (-239 ~ 200) 440
6975 22:15:55.633964 iDelay=217, Bit 1, Center -28 (-247 ~ 192) 440
6976 22:15:55.637128 iDelay=217, Bit 2, Center -32 (-255 ~ 192) 448
6977 22:15:55.640989 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6978 22:15:55.647469 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6979 22:15:55.650780 iDelay=217, Bit 5, Center -12 (-239 ~ 216) 456
6980 22:15:55.654167 iDelay=217, Bit 6, Center -16 (-239 ~ 208) 448
6981 22:15:55.657387 iDelay=217, Bit 7, Center -20 (-239 ~ 200) 440
6982 22:15:55.664055 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6983 22:15:55.667215 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6984 22:15:55.670553 iDelay=217, Bit 10, Center -24 (-247 ~ 200) 448
6985 22:15:55.677551 iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456
6986 22:15:55.680381 iDelay=217, Bit 12, Center -20 (-247 ~ 208) 456
6987 22:15:55.683872 iDelay=217, Bit 13, Center -20 (-247 ~ 208) 456
6988 22:15:55.687247 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6989 22:15:55.693698 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
6990 22:15:55.694275 ==
6991 22:15:55.696986 Dram Type= 6, Freq= 0, CH_1, rank 1
6992 22:15:55.700701 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6993 22:15:55.701311 ==
6994 22:15:55.701686 DQS Delay:
6995 22:15:55.703933 DQS0 = 32, DQS1 = 36
6996 22:15:55.704502 DQM Delay:
6997 22:15:55.707019 DQM0 = 11, DQM1 = 12
6998 22:15:55.707495 DQ Delay:
6999 22:15:55.710167 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
7000 22:15:55.713739 DQ4 =16, DQ5 =20, DQ6 =16, DQ7 =12
7001 22:15:55.716867 DQ8 =0, DQ9 =4, DQ10 =12, DQ11 =8
7002 22:15:55.720030 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =24
7003 22:15:55.720599
7004 22:15:55.720972
7005 22:15:55.727224 [DQSOSCAuto] RK1, (LSB)MR18= 0xa64e, (MSB)MR19= 0xc0c, tDQSOscB0 = 400 ps tDQSOscB1 = 389 ps
7006 22:15:55.730088 CH1 RK1: MR19=C0C, MR18=A64E
7007 22:15:55.736397 CH1_RK1: MR19=0xC0C, MR18=0xA64E, DQSOSC=389, MR23=63, INC=390, DEC=260
7008 22:15:55.739903 [RxdqsGatingPostProcess] freq 400
7009 22:15:55.746616 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7010 22:15:55.750019 best DQS0 dly(2T, 0.5T) = (0, 10)
7011 22:15:55.753207 best DQS1 dly(2T, 0.5T) = (0, 10)
7012 22:15:55.756326 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7013 22:15:55.759955 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7014 22:15:55.760526 best DQS0 dly(2T, 0.5T) = (0, 10)
7015 22:15:55.763719 best DQS1 dly(2T, 0.5T) = (0, 10)
7016 22:15:55.766996 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7017 22:15:55.769556 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7018 22:15:55.772785 Pre-setting of DQS Precalculation
7019 22:15:55.779240 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7020 22:15:55.786731 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7021 22:15:55.792499 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7022 22:15:55.793075
7023 22:15:55.793450
7024 22:15:55.795731 [Calibration Summary] 800 Mbps
7025 22:15:55.799644 CH 0, Rank 0
7026 22:15:55.800220 SW Impedance : PASS
7027 22:15:55.802780 DUTY Scan : NO K
7028 22:15:55.803252 ZQ Calibration : PASS
7029 22:15:55.806195 Jitter Meter : NO K
7030 22:15:55.809069 CBT Training : PASS
7031 22:15:55.809639 Write leveling : PASS
7032 22:15:55.812816 RX DQS gating : PASS
7033 22:15:55.815472 RX DQ/DQS(RDDQC) : PASS
7034 22:15:55.815964 TX DQ/DQS : PASS
7035 22:15:55.818900 RX DATLAT : PASS
7036 22:15:55.822567 RX DQ/DQS(Engine): PASS
7037 22:15:55.823139 TX OE : NO K
7038 22:15:55.825590 All Pass.
7039 22:15:55.826060
7040 22:15:55.826454 CH 0, Rank 1
7041 22:15:55.829202 SW Impedance : PASS
7042 22:15:55.829768 DUTY Scan : NO K
7043 22:15:55.832326 ZQ Calibration : PASS
7044 22:15:55.835373 Jitter Meter : NO K
7045 22:15:55.835844 CBT Training : PASS
7046 22:15:55.838855 Write leveling : NO K
7047 22:15:55.841753 RX DQS gating : PASS
7048 22:15:55.842313 RX DQ/DQS(RDDQC) : PASS
7049 22:15:55.845285 TX DQ/DQS : PASS
7050 22:15:55.848565 RX DATLAT : PASS
7051 22:15:55.849142 RX DQ/DQS(Engine): PASS
7052 22:15:55.852009 TX OE : NO K
7053 22:15:55.852580 All Pass.
7054 22:15:55.852952
7055 22:15:55.855565 CH 1, Rank 0
7056 22:15:55.856132 SW Impedance : PASS
7057 22:15:55.858539 DUTY Scan : NO K
7058 22:15:55.861744 ZQ Calibration : PASS
7059 22:15:55.862308 Jitter Meter : NO K
7060 22:15:55.865433 CBT Training : PASS
7061 22:15:55.868689 Write leveling : PASS
7062 22:15:55.869255 RX DQS gating : PASS
7063 22:15:55.871536 RX DQ/DQS(RDDQC) : PASS
7064 22:15:55.872008 TX DQ/DQS : PASS
7065 22:15:55.875175 RX DATLAT : PASS
7066 22:15:55.878544 RX DQ/DQS(Engine): PASS
7067 22:15:55.879148 TX OE : NO K
7068 22:15:55.881435 All Pass.
7069 22:15:55.881903
7070 22:15:55.882267 CH 1, Rank 1
7071 22:15:55.884807 SW Impedance : PASS
7072 22:15:55.885377 DUTY Scan : NO K
7073 22:15:55.888691 ZQ Calibration : PASS
7074 22:15:55.891628 Jitter Meter : NO K
7075 22:15:55.892196 CBT Training : PASS
7076 22:15:55.894792 Write leveling : NO K
7077 22:15:55.898209 RX DQS gating : PASS
7078 22:15:55.898815 RX DQ/DQS(RDDQC) : PASS
7079 22:15:55.902028 TX DQ/DQS : PASS
7080 22:15:55.905006 RX DATLAT : PASS
7081 22:15:55.905572 RX DQ/DQS(Engine): PASS
7082 22:15:55.908097 TX OE : NO K
7083 22:15:55.908668 All Pass.
7084 22:15:55.909040
7085 22:15:55.911021 DramC Write-DBI off
7086 22:15:55.914920 PER_BANK_REFRESH: Hybrid Mode
7087 22:15:55.915516 TX_TRACKING: ON
7088 22:15:55.924314 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7089 22:15:55.927973 [FAST_K] Save calibration result to emmc
7090 22:15:55.931173 dramc_set_vcore_voltage set vcore to 725000
7091 22:15:55.934328 Read voltage for 1600, 0
7092 22:15:55.934827 Vio18 = 0
7093 22:15:55.935195 Vcore = 725000
7094 22:15:55.937656 Vdram = 0
7095 22:15:55.938399 Vddq = 0
7096 22:15:55.938791 Vmddr = 0
7097 22:15:55.944674 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7098 22:15:55.950462 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7099 22:15:55.950935 MEM_TYPE=3, freq_sel=13
7100 22:15:55.953926 sv_algorithm_assistance_LP4_3733
7101 22:15:55.957422 ============ PULL DRAM RESETB DOWN ============
7102 22:15:55.964064 ========== PULL DRAM RESETB DOWN end =========
7103 22:15:55.967611 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7104 22:15:55.970293 ===================================
7105 22:15:55.973907 LPDDR4 DRAM CONFIGURATION
7106 22:15:55.977118 ===================================
7107 22:15:55.977688 EX_ROW_EN[0] = 0x0
7108 22:15:55.980453 EX_ROW_EN[1] = 0x0
7109 22:15:55.980921 LP4Y_EN = 0x0
7110 22:15:55.984583 WORK_FSP = 0x1
7111 22:15:55.985157 WL = 0x5
7112 22:15:55.986834 RL = 0x5
7113 22:15:55.990488 BL = 0x2
7114 22:15:55.991052 RPST = 0x0
7115 22:15:55.993449 RD_PRE = 0x0
7116 22:15:55.993914 WR_PRE = 0x1
7117 22:15:55.996884 WR_PST = 0x1
7118 22:15:55.997452 DBI_WR = 0x0
7119 22:15:56.000392 DBI_RD = 0x0
7120 22:15:56.000797 OTF = 0x1
7121 22:15:56.003554 ===================================
7122 22:15:56.006635 ===================================
7123 22:15:56.009996 ANA top config
7124 22:15:56.013580 ===================================
7125 22:15:56.014147 DLL_ASYNC_EN = 0
7126 22:15:56.016482 ALL_SLAVE_EN = 0
7127 22:15:56.020100 NEW_RANK_MODE = 1
7128 22:15:56.022956 DLL_IDLE_MODE = 1
7129 22:15:56.026316 LP45_APHY_COMB_EN = 1
7130 22:15:56.026829 TX_ODT_DIS = 0
7131 22:15:56.029754 NEW_8X_MODE = 1
7132 22:15:56.032929 ===================================
7133 22:15:56.035894 ===================================
7134 22:15:56.039724 data_rate = 3200
7135 22:15:56.043466 CKR = 1
7136 22:15:56.046407 DQ_P2S_RATIO = 8
7137 22:15:56.049436 ===================================
7138 22:15:56.052446 CA_P2S_RATIO = 8
7139 22:15:56.052924 DQ_CA_OPEN = 0
7140 22:15:56.056064 DQ_SEMI_OPEN = 0
7141 22:15:56.059431 CA_SEMI_OPEN = 0
7142 22:15:56.063029 CA_FULL_RATE = 0
7143 22:15:56.065931 DQ_CKDIV4_EN = 0
7144 22:15:56.069346 CA_CKDIV4_EN = 0
7145 22:15:56.069914 CA_PREDIV_EN = 0
7146 22:15:56.072019 PH8_DLY = 12
7147 22:15:56.075833 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7148 22:15:56.079373 DQ_AAMCK_DIV = 4
7149 22:15:56.082419 CA_AAMCK_DIV = 4
7150 22:15:56.085601 CA_ADMCK_DIV = 4
7151 22:15:56.086079 DQ_TRACK_CA_EN = 0
7152 22:15:56.089265 CA_PICK = 1600
7153 22:15:56.092302 CA_MCKIO = 1600
7154 22:15:56.095671 MCKIO_SEMI = 0
7155 22:15:56.098896 PLL_FREQ = 3068
7156 22:15:56.102698 DQ_UI_PI_RATIO = 32
7157 22:15:56.105643 CA_UI_PI_RATIO = 0
7158 22:15:56.109196 ===================================
7159 22:15:56.112333 ===================================
7160 22:15:56.112904 memory_type:LPDDR4
7161 22:15:56.116145 GP_NUM : 10
7162 22:15:56.119645 SRAM_EN : 1
7163 22:15:56.120214 MD32_EN : 0
7164 22:15:56.122215 ===================================
7165 22:15:56.125466 [ANA_INIT] >>>>>>>>>>>>>>
7166 22:15:56.128713 <<<<<< [CONFIGURE PHASE]: ANA_TX
7167 22:15:56.132129 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7168 22:15:56.135242 ===================================
7169 22:15:56.138413 data_rate = 3200,PCW = 0X7600
7170 22:15:56.141679 ===================================
7171 22:15:56.145288 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7172 22:15:56.148597 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7173 22:15:56.155001 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7174 22:15:56.158404 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7175 22:15:56.164892 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7176 22:15:56.168303 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7177 22:15:56.168878 [ANA_INIT] flow start
7178 22:15:56.171466 [ANA_INIT] PLL >>>>>>>>
7179 22:15:56.174686 [ANA_INIT] PLL <<<<<<<<
7180 22:15:56.175161 [ANA_INIT] MIDPI >>>>>>>>
7181 22:15:56.178282 [ANA_INIT] MIDPI <<<<<<<<
7182 22:15:56.181895 [ANA_INIT] DLL >>>>>>>>
7183 22:15:56.182407 [ANA_INIT] DLL <<<<<<<<
7184 22:15:56.185210 [ANA_INIT] flow end
7185 22:15:56.188201 ============ LP4 DIFF to SE enter ============
7186 22:15:56.191081 ============ LP4 DIFF to SE exit ============
7187 22:15:56.194801 [ANA_INIT] <<<<<<<<<<<<<
7188 22:15:56.198402 [Flow] Enable top DCM control >>>>>
7189 22:15:56.201443 [Flow] Enable top DCM control <<<<<
7190 22:15:56.204442 Enable DLL master slave shuffle
7191 22:15:56.211152 ==============================================================
7192 22:15:56.211727 Gating Mode config
7193 22:15:56.217533 ==============================================================
7194 22:15:56.221215 Config description:
7195 22:15:56.227489 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7196 22:15:56.234569 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7197 22:15:56.241077 SELPH_MODE 0: By rank 1: By Phase
7198 22:15:56.247408 ==============================================================
7199 22:15:56.247980 GAT_TRACK_EN = 1
7200 22:15:56.251038 RX_GATING_MODE = 2
7201 22:15:56.254269 RX_GATING_TRACK_MODE = 2
7202 22:15:56.257908 SELPH_MODE = 1
7203 22:15:56.261105 PICG_EARLY_EN = 1
7204 22:15:56.264308 VALID_LAT_VALUE = 1
7205 22:15:56.270489 ==============================================================
7206 22:15:56.273556 Enter into Gating configuration >>>>
7207 22:15:56.277298 Exit from Gating configuration <<<<
7208 22:15:56.280643 Enter into DVFS_PRE_config >>>>>
7209 22:15:56.290282 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7210 22:15:56.293798 Exit from DVFS_PRE_config <<<<<
7211 22:15:56.297698 Enter into PICG configuration >>>>
7212 22:15:56.300288 Exit from PICG configuration <<<<
7213 22:15:56.303704 [RX_INPUT] configuration >>>>>
7214 22:15:56.307257 [RX_INPUT] configuration <<<<<
7215 22:15:56.310210 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7216 22:15:56.317199 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7217 22:15:56.323443 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7218 22:15:56.329836 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7219 22:15:56.333608 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7220 22:15:56.340831 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7221 22:15:56.342683 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7222 22:15:56.349642 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7223 22:15:56.352852 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7224 22:15:56.356344 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7225 22:15:56.359264 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7226 22:15:56.366088 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7227 22:15:56.369541 ===================================
7228 22:15:56.373339 LPDDR4 DRAM CONFIGURATION
7229 22:15:56.376381 ===================================
7230 22:15:56.376861 EX_ROW_EN[0] = 0x0
7231 22:15:56.379479 EX_ROW_EN[1] = 0x0
7232 22:15:56.379954 LP4Y_EN = 0x0
7233 22:15:56.383203 WORK_FSP = 0x1
7234 22:15:56.383679 WL = 0x5
7235 22:15:56.385816 RL = 0x5
7236 22:15:56.386287 BL = 0x2
7237 22:15:56.389483 RPST = 0x0
7238 22:15:56.390053 RD_PRE = 0x0
7239 22:15:56.392990 WR_PRE = 0x1
7240 22:15:56.393556 WR_PST = 0x1
7241 22:15:56.396630 DBI_WR = 0x0
7242 22:15:56.397201 DBI_RD = 0x0
7243 22:15:56.398962 OTF = 0x1
7244 22:15:56.402733 ===================================
7245 22:15:56.406766 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7246 22:15:56.409267 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7247 22:15:56.416011 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7248 22:15:56.418973 ===================================
7249 22:15:56.419468 LPDDR4 DRAM CONFIGURATION
7250 22:15:56.422448 ===================================
7251 22:15:56.425802 EX_ROW_EN[0] = 0x10
7252 22:15:56.429282 EX_ROW_EN[1] = 0x0
7253 22:15:56.429855 LP4Y_EN = 0x0
7254 22:15:56.432281 WORK_FSP = 0x1
7255 22:15:56.432849 WL = 0x5
7256 22:15:56.435608 RL = 0x5
7257 22:15:56.436087 BL = 0x2
7258 22:15:56.439126 RPST = 0x0
7259 22:15:56.439696 RD_PRE = 0x0
7260 22:15:56.442908 WR_PRE = 0x1
7261 22:15:56.443480 WR_PST = 0x1
7262 22:15:56.445666 DBI_WR = 0x0
7263 22:15:56.446277 DBI_RD = 0x0
7264 22:15:56.448927 OTF = 0x1
7265 22:15:56.451674 ===================================
7266 22:15:56.458423 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7267 22:15:56.459016 ==
7268 22:15:56.462392 Dram Type= 6, Freq= 0, CH_0, rank 0
7269 22:15:56.465552 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7270 22:15:56.466118 ==
7271 22:15:56.468447 [Duty_Offset_Calibration]
7272 22:15:56.468920 B0:2 B1:0 CA:1
7273 22:15:56.469296
7274 22:15:56.471739 [DutyScan_Calibration_Flow] k_type=0
7275 22:15:56.482396
7276 22:15:56.482993 ==CLK 0==
7277 22:15:56.485594 Final CLK duty delay cell = -4
7278 22:15:56.488858 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7279 22:15:56.492219 [-4] MIN Duty = 4813%(X100), DQS PI = 62
7280 22:15:56.495538 [-4] AVG Duty = 4906%(X100)
7281 22:15:56.496108
7282 22:15:56.498401 CH0 CLK Duty spec in!! Max-Min= 187%
7283 22:15:56.502281 [DutyScan_Calibration_Flow] ====Done====
7284 22:15:56.502939
7285 22:15:56.505219 [DutyScan_Calibration_Flow] k_type=1
7286 22:15:56.522083
7287 22:15:56.522703 ==DQS 0 ==
7288 22:15:56.524967 Final DQS duty delay cell = 0
7289 22:15:56.528481 [0] MAX Duty = 5249%(X100), DQS PI = 32
7290 22:15:56.532120 [0] MIN Duty = 4969%(X100), DQS PI = 0
7291 22:15:56.535098 [0] AVG Duty = 5109%(X100)
7292 22:15:56.535570
7293 22:15:56.535938 ==DQS 1 ==
7294 22:15:56.538149 Final DQS duty delay cell = -4
7295 22:15:56.541959 [-4] MAX Duty = 5125%(X100), DQS PI = 28
7296 22:15:56.545126 [-4] MIN Duty = 4875%(X100), DQS PI = 4
7297 22:15:56.548363 [-4] AVG Duty = 5000%(X100)
7298 22:15:56.548931
7299 22:15:56.551320 CH0 DQS 0 Duty spec in!! Max-Min= 280%
7300 22:15:56.551888
7301 22:15:56.554946 CH0 DQS 1 Duty spec in!! Max-Min= 250%
7302 22:15:56.558069 [DutyScan_Calibration_Flow] ====Done====
7303 22:15:56.558689
7304 22:15:56.561272 [DutyScan_Calibration_Flow] k_type=3
7305 22:15:56.578090
7306 22:15:56.578688 ==DQM 0 ==
7307 22:15:56.581508 Final DQM duty delay cell = 0
7308 22:15:56.584884 [0] MAX Duty = 5093%(X100), DQS PI = 28
7309 22:15:56.588564 [0] MIN Duty = 4813%(X100), DQS PI = 50
7310 22:15:56.591379 [0] AVG Duty = 4953%(X100)
7311 22:15:56.591853
7312 22:15:56.592222 ==DQM 1 ==
7313 22:15:56.594476 Final DQM duty delay cell = -4
7314 22:15:56.598720 [-4] MAX Duty = 5031%(X100), DQS PI = 46
7315 22:15:56.601398 [-4] MIN Duty = 4751%(X100), DQS PI = 18
7316 22:15:56.604634 [-4] AVG Duty = 4891%(X100)
7317 22:15:56.605207
7318 22:15:56.607901 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7319 22:15:56.608480
7320 22:15:56.611515 CH0 DQM 1 Duty spec in!! Max-Min= 280%
7321 22:15:56.614769 [DutyScan_Calibration_Flow] ====Done====
7322 22:15:56.615348
7323 22:15:56.617948 [DutyScan_Calibration_Flow] k_type=2
7324 22:15:56.636096
7325 22:15:56.636671 ==DQ 0 ==
7326 22:15:56.639529 Final DQ duty delay cell = 0
7327 22:15:56.642580 [0] MAX Duty = 5156%(X100), DQS PI = 36
7328 22:15:56.646035 [0] MIN Duty = 5000%(X100), DQS PI = 16
7329 22:15:56.646653 [0] AVG Duty = 5078%(X100)
7330 22:15:56.648873
7331 22:15:56.649333 ==DQ 1 ==
7332 22:15:56.652186 Final DQ duty delay cell = 0
7333 22:15:56.655934 [0] MAX Duty = 4969%(X100), DQS PI = 44
7334 22:15:56.659211 [0] MIN Duty = 4875%(X100), DQS PI = 12
7335 22:15:56.659673 [0] AVG Duty = 4922%(X100)
7336 22:15:56.660038
7337 22:15:56.662997 CH0 DQ 0 Duty spec in!! Max-Min= 156%
7338 22:15:56.665643
7339 22:15:56.668944 CH0 DQ 1 Duty spec in!! Max-Min= 94%
7340 22:15:56.672442 [DutyScan_Calibration_Flow] ====Done====
7341 22:15:56.672930 ==
7342 22:15:56.675794 Dram Type= 6, Freq= 0, CH_1, rank 0
7343 22:15:56.679461 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7344 22:15:56.679966 ==
7345 22:15:56.682265 [Duty_Offset_Calibration]
7346 22:15:56.682775 B0:0 B1:-1 CA:2
7347 22:15:56.683183
7348 22:15:56.685367 [DutyScan_Calibration_Flow] k_type=0
7349 22:15:56.695991
7350 22:15:56.696451 ==CLK 0==
7351 22:15:56.699165 Final CLK duty delay cell = 0
7352 22:15:56.702293 [0] MAX Duty = 5187%(X100), DQS PI = 16
7353 22:15:56.706079 [0] MIN Duty = 4938%(X100), DQS PI = 46
7354 22:15:56.709159 [0] AVG Duty = 5062%(X100)
7355 22:15:56.709622
7356 22:15:56.712755 CH1 CLK Duty spec in!! Max-Min= 249%
7357 22:15:56.716203 [DutyScan_Calibration_Flow] ====Done====
7358 22:15:56.716728
7359 22:15:56.719308 [DutyScan_Calibration_Flow] k_type=1
7360 22:15:56.736066
7361 22:15:56.736629 ==DQS 0 ==
7362 22:15:56.739981 Final DQS duty delay cell = 0
7363 22:15:56.742563 [0] MAX Duty = 5124%(X100), DQS PI = 24
7364 22:15:56.745876 [0] MIN Duty = 4969%(X100), DQS PI = 2
7365 22:15:56.749361 [0] AVG Duty = 5046%(X100)
7366 22:15:56.749923
7367 22:15:56.750318 ==DQS 1 ==
7368 22:15:56.752731 Final DQS duty delay cell = 0
7369 22:15:56.756005 [0] MAX Duty = 5187%(X100), DQS PI = 0
7370 22:15:56.759290 [0] MIN Duty = 4844%(X100), DQS PI = 34
7371 22:15:56.762421 [0] AVG Duty = 5015%(X100)
7372 22:15:56.762985
7373 22:15:56.765844 CH1 DQS 0 Duty spec in!! Max-Min= 155%
7374 22:15:56.766446
7375 22:15:56.769123 CH1 DQS 1 Duty spec in!! Max-Min= 343%
7376 22:15:56.771811 [DutyScan_Calibration_Flow] ====Done====
7377 22:15:56.772302
7378 22:15:56.775295 [DutyScan_Calibration_Flow] k_type=3
7379 22:15:56.793603
7380 22:15:56.794165 ==DQM 0 ==
7381 22:15:56.796550 Final DQM duty delay cell = 4
7382 22:15:56.799812 [4] MAX Duty = 5125%(X100), DQS PI = 8
7383 22:15:56.803420 [4] MIN Duty = 4969%(X100), DQS PI = 46
7384 22:15:56.806677 [4] AVG Duty = 5047%(X100)
7385 22:15:56.807145
7386 22:15:56.807504 ==DQM 1 ==
7387 22:15:56.809677 Final DQM duty delay cell = 0
7388 22:15:56.813207 [0] MAX Duty = 5281%(X100), DQS PI = 58
7389 22:15:56.816520 [0] MIN Duty = 4907%(X100), DQS PI = 32
7390 22:15:56.819707 [0] AVG Duty = 5094%(X100)
7391 22:15:56.820198
7392 22:15:56.823910 CH1 DQM 0 Duty spec in!! Max-Min= 156%
7393 22:15:56.824496
7394 22:15:56.826205 CH1 DQM 1 Duty spec in!! Max-Min= 374%
7395 22:15:56.829776 [DutyScan_Calibration_Flow] ====Done====
7396 22:15:56.830345
7397 22:15:56.833107 [DutyScan_Calibration_Flow] k_type=2
7398 22:15:56.850576
7399 22:15:56.851148 ==DQ 0 ==
7400 22:15:56.854484 Final DQ duty delay cell = 0
7401 22:15:56.857085 [0] MAX Duty = 5093%(X100), DQS PI = 22
7402 22:15:56.860232 [0] MIN Duty = 4969%(X100), DQS PI = 32
7403 22:15:56.860806 [0] AVG Duty = 5031%(X100)
7404 22:15:56.863491
7405 22:15:56.864057 ==DQ 1 ==
7406 22:15:56.867287 Final DQ duty delay cell = 0
7407 22:15:56.869853 [0] MAX Duty = 5062%(X100), DQS PI = 2
7408 22:15:56.873223 [0] MIN Duty = 4813%(X100), DQS PI = 34
7409 22:15:56.873698 [0] AVG Duty = 4937%(X100)
7410 22:15:56.874117
7411 22:15:56.876559 CH1 DQ 0 Duty spec in!! Max-Min= 124%
7412 22:15:56.880708
7413 22:15:56.883210 CH1 DQ 1 Duty spec in!! Max-Min= 249%
7414 22:15:56.886587 [DutyScan_Calibration_Flow] ====Done====
7415 22:15:56.889897 nWR fixed to 30
7416 22:15:56.890406 [ModeRegInit_LP4] CH0 RK0
7417 22:15:56.893116 [ModeRegInit_LP4] CH0 RK1
7418 22:15:56.896793 [ModeRegInit_LP4] CH1 RK0
7419 22:15:56.899339 [ModeRegInit_LP4] CH1 RK1
7420 22:15:56.899811 match AC timing 5
7421 22:15:56.906704 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7422 22:15:56.909793 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7423 22:15:56.912889 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7424 22:15:56.919386 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7425 22:15:56.923122 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7426 22:15:56.923691 [MiockJmeterHQA]
7427 22:15:56.924068
7428 22:15:56.926080 [DramcMiockJmeter] u1RxGatingPI = 0
7429 22:15:56.929556 0 : 4252, 4027
7430 22:15:56.930132 4 : 4252, 4027
7431 22:15:56.933091 8 : 4363, 4137
7432 22:15:56.933663 12 : 4363, 4138
7433 22:15:56.934040 16 : 4363, 4138
7434 22:15:56.935992 20 : 4252, 4027
7435 22:15:56.936471 24 : 4253, 4026
7436 22:15:56.939576 28 : 4252, 4027
7437 22:15:56.940162 32 : 4363, 4138
7438 22:15:56.943610 36 : 4363, 4138
7439 22:15:56.944194 40 : 4252, 4027
7440 22:15:56.946907 44 : 4253, 4026
7441 22:15:56.947491 48 : 4252, 4027
7442 22:15:56.947876 52 : 4252, 4027
7443 22:15:56.949521 56 : 4255, 4029
7444 22:15:56.950099 60 : 4252, 4027
7445 22:15:56.953131 64 : 4253, 4026
7446 22:15:56.953709 68 : 4252, 4027
7447 22:15:56.956414 72 : 4252, 4027
7448 22:15:56.957000 76 : 4255, 4029
7449 22:15:56.959480 80 : 4254, 4029
7450 22:15:56.960060 84 : 4361, 4138
7451 22:15:56.960450 88 : 4363, 3850
7452 22:15:56.962808 92 : 4362, 0
7453 22:15:56.963389 96 : 4250, 0
7454 22:15:56.966506 100 : 4361, 0
7455 22:15:56.967092 104 : 4250, 0
7456 22:15:56.967476 108 : 4360, 0
7457 22:15:56.969171 112 : 4250, 0
7458 22:15:56.969754 116 : 4250, 0
7459 22:15:56.972521 120 : 4250, 0
7460 22:15:56.973020 124 : 4250, 0
7461 22:15:56.973431 128 : 4253, 0
7462 22:15:56.975763 132 : 4250, 0
7463 22:15:56.976423 136 : 4250, 0
7464 22:15:56.976888 140 : 4252, 0
7465 22:15:56.979127 144 : 4360, 0
7466 22:15:56.979606 148 : 4250, 0
7467 22:15:56.982235 152 : 4250, 0
7468 22:15:56.982748 156 : 4250, 0
7469 22:15:56.983136 160 : 4249, 0
7470 22:15:56.985338 164 : 4250, 0
7471 22:15:56.985821 168 : 4250, 0
7472 22:15:56.988854 172 : 4249, 0
7473 22:15:56.989336 176 : 4250, 0
7474 22:15:56.989719 180 : 4252, 0
7475 22:15:56.991935 184 : 4250, 0
7476 22:15:56.992520 188 : 4250, 0
7477 22:15:56.995222 192 : 4255, 0
7478 22:15:56.995701 196 : 4360, 0
7479 22:15:56.996082 200 : 4250, 4
7480 22:15:56.998689 204 : 4361, 2510
7481 22:15:56.999171 208 : 4250, 4027
7482 22:15:57.002025 212 : 4249, 4027
7483 22:15:57.002642 216 : 4249, 4027
7484 22:15:57.005535 220 : 4363, 4140
7485 22:15:57.006115 224 : 4250, 4027
7486 22:15:57.008786 228 : 4250, 4027
7487 22:15:57.009389 232 : 4249, 4027
7488 22:15:57.011689 236 : 4255, 4031
7489 22:15:57.012233 240 : 4250, 4027
7490 22:15:57.015177 244 : 4363, 4140
7491 22:15:57.015781 248 : 4361, 4137
7492 22:15:57.018308 252 : 4250, 4026
7493 22:15:57.018914 256 : 4361, 4137
7494 22:15:57.019297 260 : 4250, 4027
7495 22:15:57.021906 264 : 4250, 4027
7496 22:15:57.022416 268 : 4250, 4026
7497 22:15:57.025394 272 : 4363, 4140
7498 22:15:57.026009 276 : 4250, 4027
7499 22:15:57.029013 280 : 4250, 4026
7500 22:15:57.029623 284 : 4363, 4140
7501 22:15:57.031513 288 : 4253, 4029
7502 22:15:57.031993 292 : 4250, 4027
7503 22:15:57.034662 296 : 4362, 4140
7504 22:15:57.035200 300 : 4361, 4137
7505 22:15:57.038152 304 : 4250, 4026
7506 22:15:57.038661 308 : 4250, 4027
7507 22:15:57.041582 312 : 4252, 3919
7508 22:15:57.042164 316 : 4250, 1934
7509 22:15:57.042588
7510 22:15:57.045452 MIOCK jitter meter ch=0
7511 22:15:57.046026
7512 22:15:57.048147 1T = (316-92) = 224 dly cells
7513 22:15:57.051412 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7514 22:15:57.055092 ==
7515 22:15:57.055668 Dram Type= 6, Freq= 0, CH_0, rank 0
7516 22:15:57.061413 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7517 22:15:57.061992 ==
7518 22:15:57.064566 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7519 22:15:57.071304 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7520 22:15:57.074275 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7521 22:15:57.081411 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7522 22:15:57.089179 [CA 0] Center 42 (12~72) winsize 61
7523 22:15:57.092277 [CA 1] Center 42 (13~72) winsize 60
7524 22:15:57.095741 [CA 2] Center 37 (7~67) winsize 61
7525 22:15:57.099485 [CA 3] Center 37 (7~67) winsize 61
7526 22:15:57.102146 [CA 4] Center 36 (6~66) winsize 61
7527 22:15:57.105540 [CA 5] Center 35 (5~65) winsize 61
7528 22:15:57.106014
7529 22:15:57.108913 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7530 22:15:57.109486
7531 22:15:57.112591 [CATrainingPosCal] consider 1 rank data
7532 22:15:57.115426 u2DelayCellTimex100 = 290/100 ps
7533 22:15:57.119023 CA0 delay=42 (12~72),Diff = 7 PI (23 cell)
7534 22:15:57.125592 CA1 delay=42 (13~72),Diff = 7 PI (23 cell)
7535 22:15:57.129466 CA2 delay=37 (7~67),Diff = 2 PI (6 cell)
7536 22:15:57.132140 CA3 delay=37 (7~67),Diff = 2 PI (6 cell)
7537 22:15:57.135880 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7538 22:15:57.138780 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7539 22:15:57.139357
7540 22:15:57.142254 CA PerBit enable=1, Macro0, CA PI delay=35
7541 22:15:57.142871
7542 22:15:57.145486 [CBTSetCACLKResult] CA Dly = 35
7543 22:15:57.148733 CS Dly: 9 (0~40)
7544 22:15:57.151733 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7545 22:15:57.155118 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7546 22:15:57.155695 ==
7547 22:15:57.158467 Dram Type= 6, Freq= 0, CH_0, rank 1
7548 22:15:57.161818 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7549 22:15:57.165282 ==
7550 22:15:57.168104 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7551 22:15:57.171479 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7552 22:15:57.178435 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7553 22:15:57.185373 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7554 22:15:57.193000 [CA 0] Center 43 (13~74) winsize 62
7555 22:15:57.196244 [CA 1] Center 43 (13~73) winsize 61
7556 22:15:57.198680 [CA 2] Center 38 (9~68) winsize 60
7557 22:15:57.202224 [CA 3] Center 38 (9~68) winsize 60
7558 22:15:57.205669 [CA 4] Center 37 (7~67) winsize 61
7559 22:15:57.208782 [CA 5] Center 36 (6~66) winsize 61
7560 22:15:57.209269
7561 22:15:57.212102 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7562 22:15:57.212681
7563 22:15:57.215105 [CATrainingPosCal] consider 2 rank data
7564 22:15:57.219395 u2DelayCellTimex100 = 290/100 ps
7565 22:15:57.225290 CA0 delay=42 (13~72),Diff = 7 PI (23 cell)
7566 22:15:57.228963 CA1 delay=42 (13~72),Diff = 7 PI (23 cell)
7567 22:15:57.231972 CA2 delay=38 (9~67),Diff = 3 PI (10 cell)
7568 22:15:57.235171 CA3 delay=38 (9~67),Diff = 3 PI (10 cell)
7569 22:15:57.239105 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7570 22:15:57.241836 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7571 22:15:57.242452
7572 22:15:57.247252 CA PerBit enable=1, Macro0, CA PI delay=35
7573 22:15:57.247829
7574 22:15:57.248539 [CBTSetCACLKResult] CA Dly = 35
7575 22:15:57.251791 CS Dly: 10 (0~43)
7576 22:15:57.255360 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7577 22:15:57.258759 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7578 22:15:57.259328
7579 22:15:57.261841 ----->DramcWriteLeveling(PI) begin...
7580 22:15:57.262460 ==
7581 22:15:57.264923 Dram Type= 6, Freq= 0, CH_0, rank 0
7582 22:15:57.271502 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7583 22:15:57.272098 ==
7584 22:15:57.274880 Write leveling (Byte 0): 36 => 36
7585 22:15:57.278895 Write leveling (Byte 1): 32 => 32
7586 22:15:57.279473 DramcWriteLeveling(PI) end<-----
7587 22:15:57.279849
7588 22:15:57.281546 ==
7589 22:15:57.285286 Dram Type= 6, Freq= 0, CH_0, rank 0
7590 22:15:57.288486 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7591 22:15:57.289220 ==
7592 22:15:57.291823 [Gating] SW mode calibration
7593 22:15:57.298444 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7594 22:15:57.301420 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7595 22:15:57.308066 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7596 22:15:57.310988 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7597 22:15:57.314438 1 4 8 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
7598 22:15:57.321163 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7599 22:15:57.324474 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7600 22:15:57.328328 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7601 22:15:57.335318 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7602 22:15:57.337705 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7603 22:15:57.340899 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7604 22:15:57.347832 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7605 22:15:57.351113 1 5 8 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (1 0)
7606 22:15:57.354621 1 5 12 | B1->B0 | 3434 2424 | 1 0 | (1 1) (1 0)
7607 22:15:57.360886 1 5 16 | B1->B0 | 3333 2323 | 1 0 | (1 0) (0 0)
7608 22:15:57.364223 1 5 20 | B1->B0 | 2b2b 2323 | 0 0 | (1 0) (0 0)
7609 22:15:57.367483 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
7610 22:15:57.374723 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7611 22:15:57.377606 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7612 22:15:57.381011 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7613 22:15:57.387560 1 6 8 | B1->B0 | 2323 3f3f | 0 0 | (0 0) (0 0)
7614 22:15:57.390494 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7615 22:15:57.393980 1 6 16 | B1->B0 | 2525 4646 | 0 0 | (0 0) (0 0)
7616 22:15:57.400313 1 6 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
7617 22:15:57.404102 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7618 22:15:57.407450 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7619 22:15:57.414435 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7620 22:15:57.417184 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7621 22:15:57.420228 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7622 22:15:57.426933 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7623 22:15:57.429984 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7624 22:15:57.433598 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7625 22:15:57.440701 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7626 22:15:57.443390 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7627 22:15:57.446822 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7628 22:15:57.453679 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7629 22:15:57.456549 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7630 22:15:57.460136 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7631 22:15:57.467230 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7632 22:15:57.470228 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7633 22:15:57.473065 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7634 22:15:57.479628 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7635 22:15:57.483425 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7636 22:15:57.486985 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7637 22:15:57.492829 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7638 22:15:57.496548 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7639 22:15:57.499417 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7640 22:15:57.502803 Total UI for P1: 0, mck2ui 16
7641 22:15:57.506520 best dqsien dly found for B0: ( 1, 9, 10)
7642 22:15:57.512766 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7643 22:15:57.516299 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7644 22:15:57.519083 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7645 22:15:57.522266 Total UI for P1: 0, mck2ui 16
7646 22:15:57.525791 best dqsien dly found for B1: ( 1, 9, 22)
7647 22:15:57.528918 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7648 22:15:57.532494 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7649 22:15:57.533070
7650 22:15:57.538912 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7651 22:15:57.542449 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7652 22:15:57.545672 [Gating] SW calibration Done
7653 22:15:57.546152 ==
7654 22:15:57.548866 Dram Type= 6, Freq= 0, CH_0, rank 0
7655 22:15:57.552871 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7656 22:15:57.553454 ==
7657 22:15:57.553835 RX Vref Scan: 0
7658 22:15:57.555957
7659 22:15:57.556532 RX Vref 0 -> 0, step: 1
7660 22:15:57.556913
7661 22:15:57.558754 RX Delay 0 -> 252, step: 8
7662 22:15:57.562395 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7663 22:15:57.565759 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7664 22:15:57.572094 iDelay=200, Bit 2, Center 135 (88 ~ 183) 96
7665 22:15:57.575237 iDelay=200, Bit 3, Center 135 (88 ~ 183) 96
7666 22:15:57.578703 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7667 22:15:57.582740 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
7668 22:15:57.585376 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7669 22:15:57.592261 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7670 22:15:57.595117 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7671 22:15:57.599234 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7672 22:15:57.601496 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
7673 22:15:57.605525 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
7674 22:15:57.611543 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7675 22:15:57.615082 iDelay=200, Bit 13, Center 127 (80 ~ 175) 96
7676 22:15:57.619198 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7677 22:15:57.621478 iDelay=200, Bit 15, Center 135 (88 ~ 183) 96
7678 22:15:57.622047 ==
7679 22:15:57.624638 Dram Type= 6, Freq= 0, CH_0, rank 0
7680 22:15:57.631530 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7681 22:15:57.632011 ==
7682 22:15:57.632387 DQS Delay:
7683 22:15:57.632734 DQS0 = 0, DQS1 = 0
7684 22:15:57.634685 DQM Delay:
7685 22:15:57.635157 DQM0 = 138, DQM1 = 127
7686 22:15:57.637881 DQ Delay:
7687 22:15:57.641657 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
7688 22:15:57.644757 DQ4 =139, DQ5 =127, DQ6 =147, DQ7 =147
7689 22:15:57.647855 DQ8 =119, DQ9 =115, DQ10 =127, DQ11 =123
7690 22:15:57.651268 DQ12 =131, DQ13 =127, DQ14 =139, DQ15 =135
7691 22:15:57.651848
7692 22:15:57.652221
7693 22:15:57.652562 ==
7694 22:15:57.654833 Dram Type= 6, Freq= 0, CH_0, rank 0
7695 22:15:57.658101 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7696 22:15:57.661202 ==
7697 22:15:57.661774
7698 22:15:57.662148
7699 22:15:57.662541 TX Vref Scan disable
7700 22:15:57.664616 == TX Byte 0 ==
7701 22:15:57.668148 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7702 22:15:57.671507 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7703 22:15:57.674526 == TX Byte 1 ==
7704 22:15:57.677996 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7705 22:15:57.681025 Update DQM dly =988 (3 ,6, 28) DQM OEN =(3 ,3)
7706 22:15:57.685261 ==
7707 22:15:57.687450 Dram Type= 6, Freq= 0, CH_0, rank 0
7708 22:15:57.691153 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7709 22:15:57.691631 ==
7710 22:15:57.703320
7711 22:15:57.706890 TX Vref early break, caculate TX vref
7712 22:15:57.710040 TX Vref=16, minBit 7, minWin=22, winSum=375
7713 22:15:57.713821 TX Vref=18, minBit 6, minWin=23, winSum=388
7714 22:15:57.716814 TX Vref=20, minBit 0, minWin=24, winSum=395
7715 22:15:57.719573 TX Vref=22, minBit 12, minWin=23, winSum=405
7716 22:15:57.722857 TX Vref=24, minBit 1, minWin=25, winSum=412
7717 22:15:57.729873 TX Vref=26, minBit 1, minWin=25, winSum=421
7718 22:15:57.733513 TX Vref=28, minBit 2, minWin=26, winSum=431
7719 22:15:57.736300 TX Vref=30, minBit 0, minWin=26, winSum=424
7720 22:15:57.739781 TX Vref=32, minBit 0, minWin=25, winSum=414
7721 22:15:57.742913 TX Vref=34, minBit 11, minWin=24, winSum=406
7722 22:15:57.749378 [TxChooseVref] Worse bit 2, Min win 26, Win sum 431, Final Vref 28
7723 22:15:57.749935
7724 22:15:57.752757 Final TX Range 0 Vref 28
7725 22:15:57.753321
7726 22:15:57.753692 ==
7727 22:15:57.756229 Dram Type= 6, Freq= 0, CH_0, rank 0
7728 22:15:57.759546 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7729 22:15:57.760120 ==
7730 22:15:57.760497
7731 22:15:57.760839
7732 22:15:57.762675 TX Vref Scan disable
7733 22:15:57.769268 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7734 22:15:57.769837 == TX Byte 0 ==
7735 22:15:57.772713 u2DelayCellOfst[0]=10 cells (3 PI)
7736 22:15:57.775822 u2DelayCellOfst[1]=16 cells (5 PI)
7737 22:15:57.779032 u2DelayCellOfst[2]=10 cells (3 PI)
7738 22:15:57.782244 u2DelayCellOfst[3]=13 cells (4 PI)
7739 22:15:57.787392 u2DelayCellOfst[4]=6 cells (2 PI)
7740 22:15:57.788881 u2DelayCellOfst[5]=0 cells (0 PI)
7741 22:15:57.792349 u2DelayCellOfst[6]=16 cells (5 PI)
7742 22:15:57.795733 u2DelayCellOfst[7]=13 cells (4 PI)
7743 22:15:57.799513 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7744 22:15:57.802088 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7745 22:15:57.805578 == TX Byte 1 ==
7746 22:15:57.808820 u2DelayCellOfst[8]=0 cells (0 PI)
7747 22:15:57.812261 u2DelayCellOfst[9]=0 cells (0 PI)
7748 22:15:57.815167 u2DelayCellOfst[10]=6 cells (2 PI)
7749 22:15:57.815647 u2DelayCellOfst[11]=3 cells (1 PI)
7750 22:15:57.818668 u2DelayCellOfst[12]=13 cells (4 PI)
7751 22:15:57.822170 u2DelayCellOfst[13]=10 cells (3 PI)
7752 22:15:57.825115 u2DelayCellOfst[14]=13 cells (4 PI)
7753 22:15:57.828303 u2DelayCellOfst[15]=10 cells (3 PI)
7754 22:15:57.835128 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7755 22:15:57.838831 Update DQM dly =987 (3 ,6, 27) DQM OEN =(3 ,3)
7756 22:15:57.839313 DramC Write-DBI on
7757 22:15:57.841542 ==
7758 22:15:57.844876 Dram Type= 6, Freq= 0, CH_0, rank 0
7759 22:15:57.848160 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7760 22:15:57.848733 ==
7761 22:15:57.849113
7762 22:15:57.849461
7763 22:15:57.851566 TX Vref Scan disable
7764 22:15:57.852146 == TX Byte 0 ==
7765 22:15:57.858050 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7766 22:15:57.858670 == TX Byte 1 ==
7767 22:15:57.861899 Update DQM dly =728 (2 ,6, 24) DQM OEN =(3 ,3)
7768 22:15:57.864271 DramC Write-DBI off
7769 22:15:57.864874
7770 22:15:57.865265 [DATLAT]
7771 22:15:57.867687 Freq=1600, CH0 RK0
7772 22:15:57.868269
7773 22:15:57.868647 DATLAT Default: 0xf
7774 22:15:57.871151 0, 0xFFFF, sum = 0
7775 22:15:57.871721 1, 0xFFFF, sum = 0
7776 22:15:57.874170 2, 0xFFFF, sum = 0
7777 22:15:57.877649 3, 0xFFFF, sum = 0
7778 22:15:57.878235 4, 0xFFFF, sum = 0
7779 22:15:57.881455 5, 0xFFFF, sum = 0
7780 22:15:57.882086 6, 0xFFFF, sum = 0
7781 22:15:57.884838 7, 0xFFFF, sum = 0
7782 22:15:57.885426 8, 0xFFFF, sum = 0
7783 22:15:57.887984 9, 0xFFFF, sum = 0
7784 22:15:57.888572 10, 0xFFFF, sum = 0
7785 22:15:57.890660 11, 0xFFFF, sum = 0
7786 22:15:57.891141 12, 0xFFFF, sum = 0
7787 22:15:57.894747 13, 0xFFFF, sum = 0
7788 22:15:57.895333 14, 0x0, sum = 1
7789 22:15:57.897478 15, 0x0, sum = 2
7790 22:15:57.898065 16, 0x0, sum = 3
7791 22:15:57.900818 17, 0x0, sum = 4
7792 22:15:57.901401 best_step = 15
7793 22:15:57.901874
7794 22:15:57.902237 ==
7795 22:15:57.904691 Dram Type= 6, Freq= 0, CH_0, rank 0
7796 22:15:57.911318 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7797 22:15:57.911904 ==
7798 22:15:57.912290 RX Vref Scan: 1
7799 22:15:57.912646
7800 22:15:57.913753 Set Vref Range= 24 -> 127
7801 22:15:57.914231
7802 22:15:57.917438 RX Vref 24 -> 127, step: 1
7803 22:15:57.918020
7804 22:15:57.918452 RX Delay 19 -> 252, step: 4
7805 22:15:57.920490
7806 22:15:57.921067 Set Vref, RX VrefLevel [Byte0]: 24
7807 22:15:57.924213 [Byte1]: 24
7808 22:15:57.927807
7809 22:15:57.928284 Set Vref, RX VrefLevel [Byte0]: 25
7810 22:15:57.931280 [Byte1]: 25
7811 22:15:57.935576
7812 22:15:57.936151 Set Vref, RX VrefLevel [Byte0]: 26
7813 22:15:57.938595 [Byte1]: 26
7814 22:15:57.943198
7815 22:15:57.943774 Set Vref, RX VrefLevel [Byte0]: 27
7816 22:15:57.946715 [Byte1]: 27
7817 22:15:57.950438
7818 22:15:57.950914 Set Vref, RX VrefLevel [Byte0]: 28
7819 22:15:57.954073 [Byte1]: 28
7820 22:15:57.958042
7821 22:15:57.958683 Set Vref, RX VrefLevel [Byte0]: 29
7822 22:15:57.961526 [Byte1]: 29
7823 22:15:57.965672
7824 22:15:57.966148 Set Vref, RX VrefLevel [Byte0]: 30
7825 22:15:57.969545 [Byte1]: 30
7826 22:15:57.973601
7827 22:15:57.976695 Set Vref, RX VrefLevel [Byte0]: 31
7828 22:15:57.977175 [Byte1]: 31
7829 22:15:57.980854
7830 22:15:57.981359 Set Vref, RX VrefLevel [Byte0]: 32
7831 22:15:57.984415 [Byte1]: 32
7832 22:15:57.988639
7833 22:15:57.989231 Set Vref, RX VrefLevel [Byte0]: 33
7834 22:15:57.992084 [Byte1]: 33
7835 22:15:57.996366
7836 22:15:57.996943 Set Vref, RX VrefLevel [Byte0]: 34
7837 22:15:57.999493 [Byte1]: 34
7838 22:15:58.003650
7839 22:15:58.004223 Set Vref, RX VrefLevel [Byte0]: 35
7840 22:15:58.007053 [Byte1]: 35
7841 22:15:58.012189
7842 22:15:58.012763 Set Vref, RX VrefLevel [Byte0]: 36
7843 22:15:58.014221 [Byte1]: 36
7844 22:15:58.019224
7845 22:15:58.019803 Set Vref, RX VrefLevel [Byte0]: 37
7846 22:15:58.022161 [Byte1]: 37
7847 22:15:58.026693
7848 22:15:58.027271 Set Vref, RX VrefLevel [Byte0]: 38
7849 22:15:58.029529 [Byte1]: 38
7850 22:15:58.033979
7851 22:15:58.034596 Set Vref, RX VrefLevel [Byte0]: 39
7852 22:15:58.037116 [Byte1]: 39
7853 22:15:58.041583
7854 22:15:58.042162 Set Vref, RX VrefLevel [Byte0]: 40
7855 22:15:58.045077 [Byte1]: 40
7856 22:15:58.049278
7857 22:15:58.049856 Set Vref, RX VrefLevel [Byte0]: 41
7858 22:15:58.052315 [Byte1]: 41
7859 22:15:58.056432
7860 22:15:58.057011 Set Vref, RX VrefLevel [Byte0]: 42
7861 22:15:58.059720 [Byte1]: 42
7862 22:15:58.064331
7863 22:15:58.064904 Set Vref, RX VrefLevel [Byte0]: 43
7864 22:15:58.067620 [Byte1]: 43
7865 22:15:58.071564
7866 22:15:58.072288 Set Vref, RX VrefLevel [Byte0]: 44
7867 22:15:58.075192 [Byte1]: 44
7868 22:15:58.079175
7869 22:15:58.079774 Set Vref, RX VrefLevel [Byte0]: 45
7870 22:15:58.082651 [Byte1]: 45
7871 22:15:58.087319
7872 22:15:58.087905 Set Vref, RX VrefLevel [Byte0]: 46
7873 22:15:58.090097 [Byte1]: 46
7874 22:15:58.094148
7875 22:15:58.094666 Set Vref, RX VrefLevel [Byte0]: 47
7876 22:15:58.098032 [Byte1]: 47
7877 22:15:58.102079
7878 22:15:58.102771 Set Vref, RX VrefLevel [Byte0]: 48
7879 22:15:58.109003 [Byte1]: 48
7880 22:15:58.109584
7881 22:15:58.111800 Set Vref, RX VrefLevel [Byte0]: 49
7882 22:15:58.115479 [Byte1]: 49
7883 22:15:58.116089
7884 22:15:58.119774 Set Vref, RX VrefLevel [Byte0]: 50
7885 22:15:58.122318 [Byte1]: 50
7886 22:15:58.122941
7887 22:15:58.125258 Set Vref, RX VrefLevel [Byte0]: 51
7888 22:15:58.128278 [Byte1]: 51
7889 22:15:58.132475
7890 22:15:58.133085 Set Vref, RX VrefLevel [Byte0]: 52
7891 22:15:58.136498 [Byte1]: 52
7892 22:15:58.140034
7893 22:15:58.140616 Set Vref, RX VrefLevel [Byte0]: 53
7894 22:15:58.143289 [Byte1]: 53
7895 22:15:58.147889
7896 22:15:58.148464 Set Vref, RX VrefLevel [Byte0]: 54
7897 22:15:58.151040 [Byte1]: 54
7898 22:15:58.155095
7899 22:15:58.155673 Set Vref, RX VrefLevel [Byte0]: 55
7900 22:15:58.158501 [Byte1]: 55
7901 22:15:58.162760
7902 22:15:58.163351 Set Vref, RX VrefLevel [Byte0]: 56
7903 22:15:58.165828 [Byte1]: 56
7904 22:15:58.170261
7905 22:15:58.170894 Set Vref, RX VrefLevel [Byte0]: 57
7906 22:15:58.173577 [Byte1]: 57
7907 22:15:58.177860
7908 22:15:58.178335 Set Vref, RX VrefLevel [Byte0]: 58
7909 22:15:58.181714 [Byte1]: 58
7910 22:15:58.185248
7911 22:15:58.185829 Set Vref, RX VrefLevel [Byte0]: 59
7912 22:15:58.189257 [Byte1]: 59
7913 22:15:58.193096
7914 22:15:58.193570 Set Vref, RX VrefLevel [Byte0]: 60
7915 22:15:58.196070 [Byte1]: 60
7916 22:15:58.200770
7917 22:15:58.201363 Set Vref, RX VrefLevel [Byte0]: 61
7918 22:15:58.204559 [Byte1]: 61
7919 22:15:58.208031
7920 22:15:58.208607 Set Vref, RX VrefLevel [Byte0]: 62
7921 22:15:58.211647 [Byte1]: 62
7922 22:15:58.215679
7923 22:15:58.216254 Set Vref, RX VrefLevel [Byte0]: 63
7924 22:15:58.219826 [Byte1]: 63
7925 22:15:58.223233
7926 22:15:58.223707 Set Vref, RX VrefLevel [Byte0]: 64
7927 22:15:58.226530 [Byte1]: 64
7928 22:15:58.230691
7929 22:15:58.231266 Set Vref, RX VrefLevel [Byte0]: 65
7930 22:15:58.234033 [Byte1]: 65
7931 22:15:58.238494
7932 22:15:58.239074 Set Vref, RX VrefLevel [Byte0]: 66
7933 22:15:58.241539 [Byte1]: 66
7934 22:15:58.246038
7935 22:15:58.246656 Set Vref, RX VrefLevel [Byte0]: 67
7936 22:15:58.249540 [Byte1]: 67
7937 22:15:58.253590
7938 22:15:58.254163 Set Vref, RX VrefLevel [Byte0]: 68
7939 22:15:58.256898 [Byte1]: 68
7940 22:15:58.261261
7941 22:15:58.261839 Set Vref, RX VrefLevel [Byte0]: 69
7942 22:15:58.264656 [Byte1]: 69
7943 22:15:58.268634
7944 22:15:58.269216 Set Vref, RX VrefLevel [Byte0]: 70
7945 22:15:58.271975 [Byte1]: 70
7946 22:15:58.276120
7947 22:15:58.276698 Set Vref, RX VrefLevel [Byte0]: 71
7948 22:15:58.280078 [Byte1]: 71
7949 22:15:58.283712
7950 22:15:58.284428 Set Vref, RX VrefLevel [Byte0]: 72
7951 22:15:58.286863 [Byte1]: 72
7952 22:15:58.291621
7953 22:15:58.292240 Set Vref, RX VrefLevel [Byte0]: 73
7954 22:15:58.294958 [Byte1]: 73
7955 22:15:58.299024
7956 22:15:58.299501 Set Vref, RX VrefLevel [Byte0]: 74
7957 22:15:58.302466 [Byte1]: 74
7958 22:15:58.306462
7959 22:15:58.307044 Set Vref, RX VrefLevel [Byte0]: 75
7960 22:15:58.309594 [Byte1]: 75
7961 22:15:58.314276
7962 22:15:58.314911 Set Vref, RX VrefLevel [Byte0]: 76
7963 22:15:58.317288 [Byte1]: 76
7964 22:15:58.322287
7965 22:15:58.322912 Set Vref, RX VrefLevel [Byte0]: 77
7966 22:15:58.324904 [Byte1]: 77
7967 22:15:58.329504
7968 22:15:58.330089 Set Vref, RX VrefLevel [Byte0]: 78
7969 22:15:58.332407 [Byte1]: 78
7970 22:15:58.337648
7971 22:15:58.340541 Set Vref, RX VrefLevel [Byte0]: 79
7972 22:15:58.341123 [Byte1]: 79
7973 22:15:58.344700
7974 22:15:58.345279 Set Vref, RX VrefLevel [Byte0]: 80
7975 22:15:58.347523 [Byte1]: 80
7976 22:15:58.352202
7977 22:15:58.352781 Final RX Vref Byte 0 = 61 to rank0
7978 22:15:58.355739 Final RX Vref Byte 1 = 61 to rank0
7979 22:15:58.358714 Final RX Vref Byte 0 = 61 to rank1
7980 22:15:58.361882 Final RX Vref Byte 1 = 61 to rank1==
7981 22:15:58.365296 Dram Type= 6, Freq= 0, CH_0, rank 0
7982 22:15:58.371742 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7983 22:15:58.372340 ==
7984 22:15:58.372726 DQS Delay:
7985 22:15:58.375022 DQS0 = 0, DQS1 = 0
7986 22:15:58.375498 DQM Delay:
7987 22:15:58.375876 DQM0 = 137, DQM1 = 124
7988 22:15:58.378236 DQ Delay:
7989 22:15:58.382591 DQ0 =136, DQ1 =140, DQ2 =132, DQ3 =134
7990 22:15:58.384649 DQ4 =140, DQ5 =126, DQ6 =146, DQ7 =144
7991 22:15:58.388865 DQ8 =116, DQ9 =110, DQ10 =126, DQ11 =118
7992 22:15:58.391376 DQ12 =128, DQ13 =128, DQ14 =136, DQ15 =134
7993 22:15:58.391958
7994 22:15:58.392339
7995 22:15:58.392866
7996 22:15:58.394832 [DramC_TX_OE_Calibration] TA2
7997 22:15:58.398075 Original DQ_B0 (3 6) =30, OEN = 27
7998 22:15:58.401626 Original DQ_B1 (3 6) =30, OEN = 27
7999 22:15:58.404801 24, 0x0, End_B0=24 End_B1=24
8000 22:15:58.405386 25, 0x0, End_B0=25 End_B1=25
8001 22:15:58.408198 26, 0x0, End_B0=26 End_B1=26
8002 22:15:58.411679 27, 0x0, End_B0=27 End_B1=27
8003 22:15:58.414544 28, 0x0, End_B0=28 End_B1=28
8004 22:15:58.418502 29, 0x0, End_B0=29 End_B1=29
8005 22:15:58.419090 30, 0x0, End_B0=30 End_B1=30
8006 22:15:58.421588 31, 0x4141, End_B0=30 End_B1=30
8007 22:15:58.424907 Byte0 end_step=30 best_step=27
8008 22:15:58.428160 Byte1 end_step=30 best_step=27
8009 22:15:58.431976 Byte0 TX OE(2T, 0.5T) = (3, 3)
8010 22:15:58.434464 Byte1 TX OE(2T, 0.5T) = (3, 3)
8011 22:15:58.434943
8012 22:15:58.435320
8013 22:15:58.441195 [DQSOSCAuto] RK0, (LSB)MR18= 0x1d1b, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 395 ps
8014 22:15:58.444688 CH0 RK0: MR19=303, MR18=1D1B
8015 22:15:58.451778 CH0_RK0: MR19=0x303, MR18=0x1D1B, DQSOSC=395, MR23=63, INC=23, DEC=15
8016 22:15:58.452360
8017 22:15:58.454490 ----->DramcWriteLeveling(PI) begin...
8018 22:15:58.455073 ==
8019 22:15:58.458788 Dram Type= 6, Freq= 0, CH_0, rank 1
8020 22:15:58.460788 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8021 22:15:58.461271 ==
8022 22:15:58.464064 Write leveling (Byte 0): 40 => 40
8023 22:15:58.467351 Write leveling (Byte 1): 31 => 31
8024 22:15:58.471033 DramcWriteLeveling(PI) end<-----
8025 22:15:58.471615
8026 22:15:58.471992 ==
8027 22:15:58.474093 Dram Type= 6, Freq= 0, CH_0, rank 1
8028 22:15:58.477459 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8029 22:15:58.481012 ==
8030 22:15:58.481589 [Gating] SW mode calibration
8031 22:15:58.490324 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8032 22:15:58.494045 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8033 22:15:58.497267 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8034 22:15:58.504011 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8035 22:15:58.507798 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8036 22:15:58.510457 1 4 12 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (1 1)
8037 22:15:58.517233 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8038 22:15:58.520869 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8039 22:15:58.523986 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8040 22:15:58.530456 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8041 22:15:58.533848 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8042 22:15:58.536747 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8043 22:15:58.543728 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8044 22:15:58.547274 1 5 12 | B1->B0 | 3434 2c2c | 1 0 | (1 0) (0 0)
8045 22:15:58.550629 1 5 16 | B1->B0 | 2828 2323 | 0 0 | (0 1) (1 0)
8046 22:15:58.556949 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8047 22:15:58.560627 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8048 22:15:58.564178 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8049 22:15:58.570342 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8050 22:15:58.573112 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8051 22:15:58.576319 1 6 8 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
8052 22:15:58.583298 1 6 12 | B1->B0 | 2b2b 4242 | 0 0 | (0 0) (0 0)
8053 22:15:58.586271 1 6 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8054 22:15:58.590265 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8055 22:15:58.596231 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8056 22:15:58.599768 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8057 22:15:58.602790 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8058 22:15:58.609498 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8059 22:15:58.612999 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8060 22:15:58.616166 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8061 22:15:58.622671 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8062 22:15:58.626281 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8063 22:15:58.629371 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8064 22:15:58.636172 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8065 22:15:58.639198 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8066 22:15:58.643258 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8067 22:15:58.649575 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8068 22:15:58.653858 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8069 22:15:58.656053 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8070 22:15:58.662803 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8071 22:15:58.666441 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8072 22:15:58.669594 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8073 22:15:58.672721 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8074 22:15:58.679332 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8075 22:15:58.682822 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8076 22:15:58.685898 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8077 22:15:58.692662 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8078 22:15:58.696042 Total UI for P1: 0, mck2ui 16
8079 22:15:58.698905 best dqsien dly found for B0: ( 1, 9, 10)
8080 22:15:58.702169 Total UI for P1: 0, mck2ui 16
8081 22:15:58.705447 best dqsien dly found for B1: ( 1, 9, 12)
8082 22:15:58.709251 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8083 22:15:58.712165 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8084 22:15:58.712645
8085 22:15:58.715599 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8086 22:15:58.718839 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8087 22:15:58.721726 [Gating] SW calibration Done
8088 22:15:58.722201 ==
8089 22:15:58.725756 Dram Type= 6, Freq= 0, CH_0, rank 1
8090 22:15:58.728747 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8091 22:15:58.731664 ==
8092 22:15:58.732199 RX Vref Scan: 0
8093 22:15:58.732596
8094 22:15:58.735205 RX Vref 0 -> 0, step: 1
8095 22:15:58.735685
8096 22:15:58.736061 RX Delay 0 -> 252, step: 8
8097 22:15:58.741974 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8098 22:15:58.745288 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8099 22:15:58.748561 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8100 22:15:58.752022 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8101 22:15:58.758746 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8102 22:15:58.761580 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8103 22:15:58.765577 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8104 22:15:58.768752 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8105 22:15:58.771777 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8106 22:15:58.777863 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8107 22:15:58.781394 iDelay=200, Bit 10, Center 127 (80 ~ 175) 96
8108 22:15:58.784981 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8109 22:15:58.788336 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8110 22:15:58.791417 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
8111 22:15:58.798023 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8112 22:15:58.801273 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8113 22:15:58.801857 ==
8114 22:15:58.804171 Dram Type= 6, Freq= 0, CH_0, rank 1
8115 22:15:58.808061 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8116 22:15:58.808651 ==
8117 22:15:58.811067 DQS Delay:
8118 22:15:58.811606 DQS0 = 0, DQS1 = 0
8119 22:15:58.811992 DQM Delay:
8120 22:15:58.814188 DQM0 = 136, DQM1 = 125
8121 22:15:58.814706 DQ Delay:
8122 22:15:58.817966 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =131
8123 22:15:58.821031 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8124 22:15:58.827635 DQ8 =115, DQ9 =111, DQ10 =127, DQ11 =123
8125 22:15:58.830849 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =135
8126 22:15:58.831354
8127 22:15:58.831748
8128 22:15:58.832187 ==
8129 22:15:58.834210 Dram Type= 6, Freq= 0, CH_0, rank 1
8130 22:15:58.837442 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8131 22:15:58.837922 ==
8132 22:15:58.838301
8133 22:15:58.838840
8134 22:15:58.841130 TX Vref Scan disable
8135 22:15:58.844847 == TX Byte 0 ==
8136 22:15:58.847560 Update DQ dly =996 (3 ,6, 36) DQ OEN =(3 ,3)
8137 22:15:58.850771 Update DQM dly =996 (3 ,6, 36) DQM OEN =(3 ,3)
8138 22:15:58.854053 == TX Byte 1 ==
8139 22:15:58.857568 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8140 22:15:58.860796 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8141 22:15:58.861381 ==
8142 22:15:58.864568 Dram Type= 6, Freq= 0, CH_0, rank 1
8143 22:15:58.868230 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8144 22:15:58.871066 ==
8145 22:15:58.883866
8146 22:15:58.887268 TX Vref early break, caculate TX vref
8147 22:15:58.890493 TX Vref=16, minBit 0, minWin=23, winSum=388
8148 22:15:58.893935 TX Vref=18, minBit 0, minWin=24, winSum=397
8149 22:15:58.896834 TX Vref=20, minBit 8, minWin=24, winSum=408
8150 22:15:58.900955 TX Vref=22, minBit 8, minWin=24, winSum=414
8151 22:15:58.903690 TX Vref=24, minBit 0, minWin=25, winSum=424
8152 22:15:58.910437 TX Vref=26, minBit 1, minWin=26, winSum=432
8153 22:15:58.913251 TX Vref=28, minBit 0, minWin=26, winSum=434
8154 22:15:58.916861 TX Vref=30, minBit 0, minWin=26, winSum=425
8155 22:15:58.920086 TX Vref=32, minBit 0, minWin=26, winSum=419
8156 22:15:58.924141 TX Vref=34, minBit 4, minWin=24, winSum=412
8157 22:15:58.926658 TX Vref=36, minBit 4, minWin=24, winSum=403
8158 22:15:58.933129 [TxChooseVref] Worse bit 0, Min win 26, Win sum 434, Final Vref 28
8159 22:15:58.933612
8160 22:15:58.937789 Final TX Range 0 Vref 28
8161 22:15:58.938386
8162 22:15:58.938954 ==
8163 22:15:58.939653 Dram Type= 6, Freq= 0, CH_0, rank 1
8164 22:15:58.942992 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8165 22:15:58.943474 ==
8166 22:15:58.946472
8167 22:15:58.947049
8168 22:15:58.947427 TX Vref Scan disable
8169 22:15:58.953719 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8170 22:15:58.954299 == TX Byte 0 ==
8171 22:15:58.956751 u2DelayCellOfst[0]=16 cells (5 PI)
8172 22:15:58.959540 u2DelayCellOfst[1]=20 cells (6 PI)
8173 22:15:58.963233 u2DelayCellOfst[2]=13 cells (4 PI)
8174 22:15:58.966558 u2DelayCellOfst[3]=13 cells (4 PI)
8175 22:15:58.969841 u2DelayCellOfst[4]=10 cells (3 PI)
8176 22:15:58.973401 u2DelayCellOfst[5]=0 cells (0 PI)
8177 22:15:58.975851 u2DelayCellOfst[6]=20 cells (6 PI)
8178 22:15:58.979667 u2DelayCellOfst[7]=16 cells (5 PI)
8179 22:15:58.982866 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
8180 22:15:58.986305 Update DQM dly =996 (3 ,6, 36) DQM OEN =(3 ,3)
8181 22:15:58.989637 == TX Byte 1 ==
8182 22:15:58.993121 u2DelayCellOfst[8]=3 cells (1 PI)
8183 22:15:58.995769 u2DelayCellOfst[9]=0 cells (0 PI)
8184 22:15:58.999153 u2DelayCellOfst[10]=10 cells (3 PI)
8185 22:15:59.002589 u2DelayCellOfst[11]=3 cells (1 PI)
8186 22:15:59.006093 u2DelayCellOfst[12]=13 cells (4 PI)
8187 22:15:59.009420 u2DelayCellOfst[13]=13 cells (4 PI)
8188 22:15:59.012343 u2DelayCellOfst[14]=13 cells (4 PI)
8189 22:15:59.012827 u2DelayCellOfst[15]=10 cells (3 PI)
8190 22:15:59.019353 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8191 22:15:59.022482 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8192 22:15:59.025685 DramC Write-DBI on
8193 22:15:59.026381 ==
8194 22:15:59.028750 Dram Type= 6, Freq= 0, CH_0, rank 1
8195 22:15:59.032176 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8196 22:15:59.032823 ==
8197 22:15:59.033339
8198 22:15:59.033707
8199 22:15:59.035403 TX Vref Scan disable
8200 22:15:59.035882 == TX Byte 0 ==
8201 22:15:59.042460 Update DQM dly =739 (2 ,6, 35) DQM OEN =(3 ,3)
8202 22:15:59.042957 == TX Byte 1 ==
8203 22:15:59.046092 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8204 22:15:59.049388 DramC Write-DBI off
8205 22:15:59.049868
8206 22:15:59.050239 [DATLAT]
8207 22:15:59.052270 Freq=1600, CH0 RK1
8208 22:15:59.052855
8209 22:15:59.053234 DATLAT Default: 0xf
8210 22:15:59.055775 0, 0xFFFF, sum = 0
8211 22:15:59.058598 1, 0xFFFF, sum = 0
8212 22:15:59.059112 2, 0xFFFF, sum = 0
8213 22:15:59.061899 3, 0xFFFF, sum = 0
8214 22:15:59.062407 4, 0xFFFF, sum = 0
8215 22:15:59.065767 5, 0xFFFF, sum = 0
8216 22:15:59.066386 6, 0xFFFF, sum = 0
8217 22:15:59.068592 7, 0xFFFF, sum = 0
8218 22:15:59.069174 8, 0xFFFF, sum = 0
8219 22:15:59.072083 9, 0xFFFF, sum = 0
8220 22:15:59.072670 10, 0xFFFF, sum = 0
8221 22:15:59.075473 11, 0xFFFF, sum = 0
8222 22:15:59.076061 12, 0xFFFF, sum = 0
8223 22:15:59.078408 13, 0xFFFF, sum = 0
8224 22:15:59.078898 14, 0x0, sum = 1
8225 22:15:59.081898 15, 0x0, sum = 2
8226 22:15:59.082521 16, 0x0, sum = 3
8227 22:15:59.085454 17, 0x0, sum = 4
8228 22:15:59.086040 best_step = 15
8229 22:15:59.086453
8230 22:15:59.086805 ==
8231 22:15:59.088747 Dram Type= 6, Freq= 0, CH_0, rank 1
8232 22:15:59.095207 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8233 22:15:59.095794 ==
8234 22:15:59.096177 RX Vref Scan: 0
8235 22:15:59.096534
8236 22:15:59.098468 RX Vref 0 -> 0, step: 1
8237 22:15:59.098949
8238 22:15:59.101776 RX Delay 11 -> 252, step: 4
8239 22:15:59.105645 iDelay=191, Bit 0, Center 132 (83 ~ 182) 100
8240 22:15:59.108226 iDelay=191, Bit 1, Center 136 (87 ~ 186) 100
8241 22:15:59.111501 iDelay=191, Bit 2, Center 128 (79 ~ 178) 100
8242 22:15:59.118060 iDelay=191, Bit 3, Center 130 (83 ~ 178) 96
8243 22:15:59.121477 iDelay=191, Bit 4, Center 136 (87 ~ 186) 100
8244 22:15:59.124675 iDelay=191, Bit 5, Center 124 (75 ~ 174) 100
8245 22:15:59.128058 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8246 22:15:59.131143 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8247 22:15:59.138170 iDelay=191, Bit 8, Center 116 (67 ~ 166) 100
8248 22:15:59.140998 iDelay=191, Bit 9, Center 112 (59 ~ 166) 108
8249 22:15:59.144414 iDelay=191, Bit 10, Center 124 (75 ~ 174) 100
8250 22:15:59.147897 iDelay=191, Bit 11, Center 120 (71 ~ 170) 100
8251 22:15:59.154201 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8252 22:15:59.157775 iDelay=191, Bit 13, Center 128 (79 ~ 178) 100
8253 22:15:59.160679 iDelay=191, Bit 14, Center 132 (79 ~ 186) 108
8254 22:15:59.163930 iDelay=191, Bit 15, Center 130 (79 ~ 182) 104
8255 22:15:59.164519 ==
8256 22:15:59.167270 Dram Type= 6, Freq= 0, CH_0, rank 1
8257 22:15:59.174036 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8258 22:15:59.174665 ==
8259 22:15:59.175057 DQS Delay:
8260 22:15:59.177170 DQS0 = 0, DQS1 = 0
8261 22:15:59.177650 DQM Delay:
8262 22:15:59.180521 DQM0 = 133, DQM1 = 123
8263 22:15:59.181095 DQ Delay:
8264 22:15:59.183691 DQ0 =132, DQ1 =136, DQ2 =128, DQ3 =130
8265 22:15:59.187323 DQ4 =136, DQ5 =124, DQ6 =140, DQ7 =140
8266 22:15:59.190332 DQ8 =116, DQ9 =112, DQ10 =124, DQ11 =120
8267 22:15:59.193998 DQ12 =128, DQ13 =128, DQ14 =132, DQ15 =130
8268 22:15:59.194602
8269 22:15:59.194985
8270 22:15:59.195335
8271 22:15:59.197690 [DramC_TX_OE_Calibration] TA2
8272 22:15:59.200501 Original DQ_B0 (3 6) =30, OEN = 27
8273 22:15:59.204084 Original DQ_B1 (3 6) =30, OEN = 27
8274 22:15:59.207796 24, 0x0, End_B0=24 End_B1=24
8275 22:15:59.211222 25, 0x0, End_B0=25 End_B1=25
8276 22:15:59.211804 26, 0x0, End_B0=26 End_B1=26
8277 22:15:59.213217 27, 0x0, End_B0=27 End_B1=27
8278 22:15:59.216893 28, 0x0, End_B0=28 End_B1=28
8279 22:15:59.220195 29, 0x0, End_B0=29 End_B1=29
8280 22:15:59.220774 30, 0x0, End_B0=30 End_B1=30
8281 22:15:59.223639 31, 0x4141, End_B0=30 End_B1=30
8282 22:15:59.226888 Byte0 end_step=30 best_step=27
8283 22:15:59.230154 Byte1 end_step=30 best_step=27
8284 22:15:59.233799 Byte0 TX OE(2T, 0.5T) = (3, 3)
8285 22:15:59.236609 Byte1 TX OE(2T, 0.5T) = (3, 3)
8286 22:15:59.237085
8287 22:15:59.237460
8288 22:15:59.243075 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f0c, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 394 ps
8289 22:15:59.246557 CH0 RK1: MR19=303, MR18=1F0C
8290 22:15:59.253211 CH0_RK1: MR19=0x303, MR18=0x1F0C, DQSOSC=394, MR23=63, INC=23, DEC=15
8291 22:15:59.256383 [RxdqsGatingPostProcess] freq 1600
8292 22:15:59.263225 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8293 22:15:59.263814 best DQS0 dly(2T, 0.5T) = (1, 1)
8294 22:15:59.267079 best DQS1 dly(2T, 0.5T) = (1, 1)
8295 22:15:59.269791 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8296 22:15:59.272881 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8297 22:15:59.277106 best DQS0 dly(2T, 0.5T) = (1, 1)
8298 22:15:59.279689 best DQS1 dly(2T, 0.5T) = (1, 1)
8299 22:15:59.283304 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8300 22:15:59.286348 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8301 22:15:59.289895 Pre-setting of DQS Precalculation
8302 22:15:59.293191 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8303 22:15:59.293776 ==
8304 22:15:59.296136 Dram Type= 6, Freq= 0, CH_1, rank 0
8305 22:15:59.302743 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8306 22:15:59.303224 ==
8307 22:15:59.306638 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8308 22:15:59.313329 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8309 22:15:59.316114 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8310 22:15:59.323194 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8311 22:15:59.330675 [CA 0] Center 40 (11~70) winsize 60
8312 22:15:59.333516 [CA 1] Center 41 (11~71) winsize 61
8313 22:15:59.338433 [CA 2] Center 37 (8~66) winsize 59
8314 22:15:59.339997 [CA 3] Center 35 (6~65) winsize 60
8315 22:15:59.343519 [CA 4] Center 36 (6~67) winsize 62
8316 22:15:59.346962 [CA 5] Center 36 (6~66) winsize 61
8317 22:15:59.347541
8318 22:15:59.350580 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8319 22:15:59.351160
8320 22:15:59.353684 [CATrainingPosCal] consider 1 rank data
8321 22:15:59.356985 u2DelayCellTimex100 = 290/100 ps
8322 22:15:59.363504 CA0 delay=40 (11~70),Diff = 5 PI (16 cell)
8323 22:15:59.366643 CA1 delay=41 (11~71),Diff = 6 PI (20 cell)
8324 22:15:59.371080 CA2 delay=37 (8~66),Diff = 2 PI (6 cell)
8325 22:15:59.373041 CA3 delay=35 (6~65),Diff = 0 PI (0 cell)
8326 22:15:59.376524 CA4 delay=36 (6~67),Diff = 1 PI (3 cell)
8327 22:15:59.380257 CA5 delay=36 (6~66),Diff = 1 PI (3 cell)
8328 22:15:59.380836
8329 22:15:59.383133 CA PerBit enable=1, Macro0, CA PI delay=35
8330 22:15:59.383601
8331 22:15:59.386606 [CBTSetCACLKResult] CA Dly = 35
8332 22:15:59.389892 CS Dly: 8 (0~39)
8333 22:15:59.393139 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8334 22:15:59.396347 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8335 22:15:59.396767 ==
8336 22:15:59.399553 Dram Type= 6, Freq= 0, CH_1, rank 1
8337 22:15:59.406581 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8338 22:15:59.407006 ==
8339 22:15:59.409728 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8340 22:15:59.416481 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8341 22:15:59.419762 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8342 22:15:59.425820 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8343 22:15:59.433649 [CA 0] Center 41 (12~71) winsize 60
8344 22:15:59.437089 [CA 1] Center 41 (12~71) winsize 60
8345 22:15:59.439612 [CA 2] Center 38 (9~67) winsize 59
8346 22:15:59.443400 [CA 3] Center 37 (8~67) winsize 60
8347 22:15:59.446645 [CA 4] Center 37 (8~67) winsize 60
8348 22:15:59.449897 [CA 5] Center 37 (7~67) winsize 61
8349 22:15:59.450478
8350 22:15:59.453280 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8351 22:15:59.453838
8352 22:15:59.456735 [CATrainingPosCal] consider 2 rank data
8353 22:15:59.460720 u2DelayCellTimex100 = 290/100 ps
8354 22:15:59.462946 CA0 delay=41 (12~70),Diff = 5 PI (16 cell)
8355 22:15:59.469606 CA1 delay=41 (12~71),Diff = 5 PI (16 cell)
8356 22:15:59.473475 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8357 22:15:59.477279 CA3 delay=36 (8~65),Diff = 0 PI (0 cell)
8358 22:15:59.479925 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8359 22:15:59.483301 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8360 22:15:59.483855
8361 22:15:59.485987 CA PerBit enable=1, Macro0, CA PI delay=36
8362 22:15:59.486478
8363 22:15:59.490087 [CBTSetCACLKResult] CA Dly = 36
8364 22:15:59.493252 CS Dly: 10 (0~43)
8365 22:15:59.496474 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8366 22:15:59.499746 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8367 22:15:59.500302
8368 22:15:59.502886 ----->DramcWriteLeveling(PI) begin...
8369 22:15:59.503363 ==
8370 22:15:59.506192 Dram Type= 6, Freq= 0, CH_1, rank 0
8371 22:15:59.512812 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8372 22:15:59.513373 ==
8373 22:15:59.516247 Write leveling (Byte 0): 24 => 24
8374 22:15:59.516799 Write leveling (Byte 1): 28 => 28
8375 22:15:59.519580 DramcWriteLeveling(PI) end<-----
8376 22:15:59.520134
8377 22:15:59.523141 ==
8378 22:15:59.523696 Dram Type= 6, Freq= 0, CH_1, rank 0
8379 22:15:59.529333 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8380 22:15:59.529890 ==
8381 22:15:59.532655 [Gating] SW mode calibration
8382 22:15:59.539142 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8383 22:15:59.542441 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8384 22:15:59.549256 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8385 22:15:59.552745 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8386 22:15:59.556169 1 4 8 | B1->B0 | 2e2e 3232 | 0 0 | (0 0) (0 0)
8387 22:15:59.562347 1 4 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8388 22:15:59.565965 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8389 22:15:59.569043 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8390 22:15:59.575713 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8391 22:15:59.578749 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8392 22:15:59.582510 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8393 22:15:59.588968 1 5 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (1 0)
8394 22:15:59.592233 1 5 8 | B1->B0 | 3030 2c2c | 0 0 | (0 0) (1 0)
8395 22:15:59.595888 1 5 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
8396 22:15:59.602220 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8397 22:15:59.605435 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8398 22:15:59.608653 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8399 22:15:59.615284 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8400 22:15:59.618400 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8401 22:15:59.622029 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8402 22:15:59.628400 1 6 8 | B1->B0 | 3e3e 4444 | 0 0 | (0 0) (0 0)
8403 22:15:59.632009 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8404 22:15:59.635827 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8405 22:15:59.641583 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8406 22:15:59.645302 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8407 22:15:59.648769 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8408 22:15:59.654874 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8409 22:15:59.658342 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8410 22:15:59.661467 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8411 22:15:59.668220 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8412 22:15:59.671228 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8413 22:15:59.674715 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8414 22:15:59.681429 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8415 22:15:59.684710 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8416 22:15:59.688835 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8417 22:15:59.694593 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8418 22:15:59.697642 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8419 22:15:59.701385 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8420 22:15:59.708196 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8421 22:15:59.710984 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8422 22:15:59.714784 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8423 22:15:59.721594 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8424 22:15:59.724396 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8425 22:15:59.727764 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8426 22:15:59.733943 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8427 22:15:59.737487 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8428 22:15:59.740664 Total UI for P1: 0, mck2ui 16
8429 22:15:59.744393 best dqsien dly found for B0: ( 1, 9, 8)
8430 22:15:59.747970 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8431 22:15:59.750699 Total UI for P1: 0, mck2ui 16
8432 22:15:59.754626 best dqsien dly found for B1: ( 1, 9, 10)
8433 22:15:59.757596 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8434 22:15:59.760752 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8435 22:15:59.761344
8436 22:15:59.763834 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8437 22:15:59.770314 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8438 22:15:59.770930 [Gating] SW calibration Done
8439 22:15:59.773801 ==
8440 22:15:59.777229 Dram Type= 6, Freq= 0, CH_1, rank 0
8441 22:15:59.779997 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8442 22:15:59.780480 ==
8443 22:15:59.780864 RX Vref Scan: 0
8444 22:15:59.781212
8445 22:15:59.783379 RX Vref 0 -> 0, step: 1
8446 22:15:59.783856
8447 22:15:59.786799 RX Delay 0 -> 252, step: 8
8448 22:15:59.790535 iDelay=200, Bit 0, Center 139 (96 ~ 183) 88
8449 22:15:59.793966 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8450 22:15:59.798392 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8451 22:15:59.803173 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8452 22:15:59.806417 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8453 22:15:59.809739 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8454 22:15:59.813916 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8455 22:15:59.816499 iDelay=200, Bit 7, Center 135 (88 ~ 183) 96
8456 22:15:59.823595 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8457 22:15:59.826756 iDelay=200, Bit 9, Center 119 (72 ~ 167) 96
8458 22:15:59.829822 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8459 22:15:59.833258 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8460 22:15:59.836300 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8461 22:15:59.842621 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
8462 22:15:59.846230 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8463 22:15:59.849821 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8464 22:15:59.850439 ==
8465 22:15:59.853094 Dram Type= 6, Freq= 0, CH_1, rank 0
8466 22:15:59.856591 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8467 22:15:59.859359 ==
8468 22:15:59.859837 DQS Delay:
8469 22:15:59.860213 DQS0 = 0, DQS1 = 0
8470 22:15:59.862672 DQM Delay:
8471 22:15:59.863146 DQM0 = 136, DQM1 = 131
8472 22:15:59.866223 DQ Delay:
8473 22:15:59.870123 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8474 22:15:59.872805 DQ4 =135, DQ5 =147, DQ6 =147, DQ7 =135
8475 22:15:59.875656 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
8476 22:15:59.879009 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =139
8477 22:15:59.879514
8478 22:15:59.879885
8479 22:15:59.880248 ==
8480 22:15:59.882600 Dram Type= 6, Freq= 0, CH_1, rank 0
8481 22:15:59.885829 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8482 22:15:59.889367 ==
8483 22:15:59.889946
8484 22:15:59.890380
8485 22:15:59.890815 TX Vref Scan disable
8486 22:15:59.892043 == TX Byte 0 ==
8487 22:15:59.895625 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8488 22:15:59.898807 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8489 22:15:59.902408 == TX Byte 1 ==
8490 22:15:59.906031 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8491 22:15:59.909337 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8492 22:15:59.912486 ==
8493 22:15:59.913236 Dram Type= 6, Freq= 0, CH_1, rank 0
8494 22:15:59.918607 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8495 22:15:59.919083 ==
8496 22:15:59.930911
8497 22:15:59.934052 TX Vref early break, caculate TX vref
8498 22:15:59.938090 TX Vref=16, minBit 10, minWin=21, winSum=366
8499 22:15:59.940819 TX Vref=18, minBit 10, minWin=22, winSum=381
8500 22:15:59.943929 TX Vref=20, minBit 10, minWin=22, winSum=386
8501 22:15:59.947252 TX Vref=22, minBit 10, minWin=23, winSum=396
8502 22:15:59.953721 TX Vref=24, minBit 8, minWin=24, winSum=404
8503 22:15:59.957153 TX Vref=26, minBit 10, minWin=24, winSum=417
8504 22:15:59.960491 TX Vref=28, minBit 10, minWin=25, winSum=420
8505 22:15:59.963732 TX Vref=30, minBit 8, minWin=24, winSum=413
8506 22:15:59.967267 TX Vref=32, minBit 8, minWin=24, winSum=404
8507 22:15:59.974169 TX Vref=34, minBit 8, minWin=23, winSum=392
8508 22:15:59.976797 [TxChooseVref] Worse bit 10, Min win 25, Win sum 420, Final Vref 28
8509 22:15:59.977383
8510 22:15:59.980059 Final TX Range 0 Vref 28
8511 22:15:59.980534
8512 22:15:59.980901 ==
8513 22:15:59.983600 Dram Type= 6, Freq= 0, CH_1, rank 0
8514 22:15:59.986674 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8515 22:15:59.989876 ==
8516 22:15:59.990374
8517 22:15:59.990756
8518 22:15:59.991100 TX Vref Scan disable
8519 22:15:59.996563 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8520 22:15:59.997126 == TX Byte 0 ==
8521 22:15:59.999917 u2DelayCellOfst[0]=16 cells (5 PI)
8522 22:16:00.003062 u2DelayCellOfst[1]=10 cells (3 PI)
8523 22:16:00.006566 u2DelayCellOfst[2]=0 cells (0 PI)
8524 22:16:00.010004 u2DelayCellOfst[3]=6 cells (2 PI)
8525 22:16:00.013217 u2DelayCellOfst[4]=6 cells (2 PI)
8526 22:16:00.016345 u2DelayCellOfst[5]=16 cells (5 PI)
8527 22:16:00.019653 u2DelayCellOfst[6]=16 cells (5 PI)
8528 22:16:00.022841 u2DelayCellOfst[7]=3 cells (1 PI)
8529 22:16:00.026652 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8530 22:16:00.029849 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8531 22:16:00.033359 == TX Byte 1 ==
8532 22:16:00.036787 u2DelayCellOfst[8]=0 cells (0 PI)
8533 22:16:00.039529 u2DelayCellOfst[9]=3 cells (1 PI)
8534 22:16:00.043007 u2DelayCellOfst[10]=13 cells (4 PI)
8535 22:16:00.046524 u2DelayCellOfst[11]=6 cells (2 PI)
8536 22:16:00.049546 u2DelayCellOfst[12]=16 cells (5 PI)
8537 22:16:00.050120 u2DelayCellOfst[13]=16 cells (5 PI)
8538 22:16:00.052785 u2DelayCellOfst[14]=20 cells (6 PI)
8539 22:16:00.056184 u2DelayCellOfst[15]=16 cells (5 PI)
8540 22:16:00.063291 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8541 22:16:00.065976 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8542 22:16:00.069755 DramC Write-DBI on
8543 22:16:00.070336 ==
8544 22:16:00.072797 Dram Type= 6, Freq= 0, CH_1, rank 0
8545 22:16:00.075855 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8546 22:16:00.076436 ==
8547 22:16:00.076818
8548 22:16:00.077166
8549 22:16:00.079162 TX Vref Scan disable
8550 22:16:00.079634 == TX Byte 0 ==
8551 22:16:00.086465 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8552 22:16:00.087041 == TX Byte 1 ==
8553 22:16:00.089695 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8554 22:16:00.092609 DramC Write-DBI off
8555 22:16:00.093179
8556 22:16:00.093553 [DATLAT]
8557 22:16:00.095450 Freq=1600, CH1 RK0
8558 22:16:00.095952
8559 22:16:00.096351 DATLAT Default: 0xf
8560 22:16:00.098740 0, 0xFFFF, sum = 0
8561 22:16:00.099222 1, 0xFFFF, sum = 0
8562 22:16:00.102299 2, 0xFFFF, sum = 0
8563 22:16:00.105491 3, 0xFFFF, sum = 0
8564 22:16:00.105987 4, 0xFFFF, sum = 0
8565 22:16:00.108753 5, 0xFFFF, sum = 0
8566 22:16:00.109248 6, 0xFFFF, sum = 0
8567 22:16:00.111770 7, 0xFFFF, sum = 0
8568 22:16:00.112264 8, 0xFFFF, sum = 0
8569 22:16:00.116207 9, 0xFFFF, sum = 0
8570 22:16:00.116819 10, 0xFFFF, sum = 0
8571 22:16:00.119273 11, 0xFFFF, sum = 0
8572 22:16:00.119771 12, 0xFFFF, sum = 0
8573 22:16:00.121912 13, 0xFFFF, sum = 0
8574 22:16:00.122438 14, 0x0, sum = 1
8575 22:16:00.124788 15, 0x0, sum = 2
8576 22:16:00.125289 16, 0x0, sum = 3
8577 22:16:00.128188 17, 0x0, sum = 4
8578 22:16:00.128640 best_step = 15
8579 22:16:00.129081
8580 22:16:00.129516 ==
8581 22:16:00.131639 Dram Type= 6, Freq= 0, CH_1, rank 0
8582 22:16:00.138527 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8583 22:16:00.139083 ==
8584 22:16:00.139535 RX Vref Scan: 1
8585 22:16:00.139953
8586 22:16:00.141633 Set Vref Range= 24 -> 127
8587 22:16:00.142157
8588 22:16:00.145250 RX Vref 24 -> 127, step: 1
8589 22:16:00.145802
8590 22:16:00.146257 RX Delay 19 -> 252, step: 4
8591 22:16:00.148240
8592 22:16:00.148794 Set Vref, RX VrefLevel [Byte0]: 24
8593 22:16:00.151693 [Byte1]: 24
8594 22:16:00.155735
8595 22:16:00.156283 Set Vref, RX VrefLevel [Byte0]: 25
8596 22:16:00.159258 [Byte1]: 25
8597 22:16:00.163184
8598 22:16:00.163732 Set Vref, RX VrefLevel [Byte0]: 26
8599 22:16:00.166993 [Byte1]: 26
8600 22:16:00.170849
8601 22:16:00.171396 Set Vref, RX VrefLevel [Byte0]: 27
8602 22:16:00.173777 [Byte1]: 27
8603 22:16:00.178560
8604 22:16:00.179001 Set Vref, RX VrefLevel [Byte0]: 28
8605 22:16:00.182077 [Byte1]: 28
8606 22:16:00.185972
8607 22:16:00.186539 Set Vref, RX VrefLevel [Byte0]: 29
8608 22:16:00.189262 [Byte1]: 29
8609 22:16:00.193427
8610 22:16:00.193954 Set Vref, RX VrefLevel [Byte0]: 30
8611 22:16:00.196631 [Byte1]: 30
8612 22:16:00.201015
8613 22:16:00.201560 Set Vref, RX VrefLevel [Byte0]: 31
8614 22:16:00.204564 [Byte1]: 31
8615 22:16:00.209285
8616 22:16:00.209760 Set Vref, RX VrefLevel [Byte0]: 32
8617 22:16:00.211759 [Byte1]: 32
8618 22:16:00.216298
8619 22:16:00.216868 Set Vref, RX VrefLevel [Byte0]: 33
8620 22:16:00.219349 [Byte1]: 33
8621 22:16:00.223853
8622 22:16:00.224424 Set Vref, RX VrefLevel [Byte0]: 34
8623 22:16:00.226928 [Byte1]: 34
8624 22:16:00.231573
8625 22:16:00.232144 Set Vref, RX VrefLevel [Byte0]: 35
8626 22:16:00.234649 [Byte1]: 35
8627 22:16:00.238808
8628 22:16:00.239283 Set Vref, RX VrefLevel [Byte0]: 36
8629 22:16:00.242049 [Byte1]: 36
8630 22:16:00.246758
8631 22:16:00.247330 Set Vref, RX VrefLevel [Byte0]: 37
8632 22:16:00.250009 [Byte1]: 37
8633 22:16:00.254240
8634 22:16:00.257735 Set Vref, RX VrefLevel [Byte0]: 38
8635 22:16:00.260572 [Byte1]: 38
8636 22:16:00.261153
8637 22:16:00.263857 Set Vref, RX VrefLevel [Byte0]: 39
8638 22:16:00.267267 [Byte1]: 39
8639 22:16:00.267842
8640 22:16:00.270621 Set Vref, RX VrefLevel [Byte0]: 40
8641 22:16:00.273810 [Byte1]: 40
8642 22:16:00.274415
8643 22:16:00.277221 Set Vref, RX VrefLevel [Byte0]: 41
8644 22:16:00.280436 [Byte1]: 41
8645 22:16:00.284884
8646 22:16:00.285454 Set Vref, RX VrefLevel [Byte0]: 42
8647 22:16:00.287900 [Byte1]: 42
8648 22:16:00.292200
8649 22:16:00.292772 Set Vref, RX VrefLevel [Byte0]: 43
8650 22:16:00.295269 [Byte1]: 43
8651 22:16:00.299536
8652 22:16:00.300117 Set Vref, RX VrefLevel [Byte0]: 44
8653 22:16:00.302803 [Byte1]: 44
8654 22:16:00.307016
8655 22:16:00.307491 Set Vref, RX VrefLevel [Byte0]: 45
8656 22:16:00.310109 [Byte1]: 45
8657 22:16:00.314981
8658 22:16:00.315554 Set Vref, RX VrefLevel [Byte0]: 46
8659 22:16:00.317860 [Byte1]: 46
8660 22:16:00.322102
8661 22:16:00.322737 Set Vref, RX VrefLevel [Byte0]: 47
8662 22:16:00.325388 [Byte1]: 47
8663 22:16:00.329719
8664 22:16:00.330303 Set Vref, RX VrefLevel [Byte0]: 48
8665 22:16:00.333297 [Byte1]: 48
8666 22:16:00.337502
8667 22:16:00.337979 Set Vref, RX VrefLevel [Byte0]: 49
8668 22:16:00.340401 [Byte1]: 49
8669 22:16:00.344719
8670 22:16:00.345191 Set Vref, RX VrefLevel [Byte0]: 50
8671 22:16:00.348658 [Byte1]: 50
8672 22:16:00.352757
8673 22:16:00.355602 Set Vref, RX VrefLevel [Byte0]: 51
8674 22:16:00.358872 [Byte1]: 51
8675 22:16:00.359452
8676 22:16:00.362117 Set Vref, RX VrefLevel [Byte0]: 52
8677 22:16:00.366069 [Byte1]: 52
8678 22:16:00.366678
8679 22:16:00.369228 Set Vref, RX VrefLevel [Byte0]: 53
8680 22:16:00.372558 [Byte1]: 53
8681 22:16:00.373138
8682 22:16:00.375598 Set Vref, RX VrefLevel [Byte0]: 54
8683 22:16:00.378713 [Byte1]: 54
8684 22:16:00.382895
8685 22:16:00.383473 Set Vref, RX VrefLevel [Byte0]: 55
8686 22:16:00.389722 [Byte1]: 55
8687 22:16:00.390297
8688 22:16:00.393602 Set Vref, RX VrefLevel [Byte0]: 56
8689 22:16:00.395966 [Byte1]: 56
8690 22:16:00.396547
8691 22:16:00.399573 Set Vref, RX VrefLevel [Byte0]: 57
8692 22:16:00.402821 [Byte1]: 57
8693 22:16:00.403424
8694 22:16:00.405714 Set Vref, RX VrefLevel [Byte0]: 58
8695 22:16:00.408861 [Byte1]: 58
8696 22:16:00.413677
8697 22:16:00.414277 Set Vref, RX VrefLevel [Byte0]: 59
8698 22:16:00.416325 [Byte1]: 59
8699 22:16:00.421196
8700 22:16:00.421840 Set Vref, RX VrefLevel [Byte0]: 60
8701 22:16:00.423769 [Byte1]: 60
8702 22:16:00.428665
8703 22:16:00.429239 Set Vref, RX VrefLevel [Byte0]: 61
8704 22:16:00.431687 [Byte1]: 61
8705 22:16:00.435785
8706 22:16:00.436259 Set Vref, RX VrefLevel [Byte0]: 62
8707 22:16:00.438893 [Byte1]: 62
8708 22:16:00.443170
8709 22:16:00.443650 Set Vref, RX VrefLevel [Byte0]: 63
8710 22:16:00.446605 [Byte1]: 63
8711 22:16:00.451068
8712 22:16:00.451541 Set Vref, RX VrefLevel [Byte0]: 64
8713 22:16:00.454576 [Byte1]: 64
8714 22:16:00.458523
8715 22:16:00.459104 Set Vref, RX VrefLevel [Byte0]: 65
8716 22:16:00.461960 [Byte1]: 65
8717 22:16:00.465991
8718 22:16:00.466615 Set Vref, RX VrefLevel [Byte0]: 66
8719 22:16:00.469513 [Byte1]: 66
8720 22:16:00.473723
8721 22:16:00.474315 Set Vref, RX VrefLevel [Byte0]: 67
8722 22:16:00.477035 [Byte1]: 67
8723 22:16:00.481015
8724 22:16:00.481545 Set Vref, RX VrefLevel [Byte0]: 68
8725 22:16:00.484947 [Byte1]: 68
8726 22:16:00.489331
8727 22:16:00.489915 Set Vref, RX VrefLevel [Byte0]: 69
8728 22:16:00.492847 [Byte1]: 69
8729 22:16:00.496689
8730 22:16:00.497162 Set Vref, RX VrefLevel [Byte0]: 70
8731 22:16:00.500016 [Byte1]: 70
8732 22:16:00.504033
8733 22:16:00.504605 Set Vref, RX VrefLevel [Byte0]: 71
8734 22:16:00.507106 [Byte1]: 71
8735 22:16:00.511540
8736 22:16:00.512107 Set Vref, RX VrefLevel [Byte0]: 72
8737 22:16:00.514593 [Byte1]: 72
8738 22:16:00.519570
8739 22:16:00.520142 Set Vref, RX VrefLevel [Byte0]: 73
8740 22:16:00.522326 [Byte1]: 73
8741 22:16:00.526474
8742 22:16:00.526947 Set Vref, RX VrefLevel [Byte0]: 74
8743 22:16:00.530143 [Byte1]: 74
8744 22:16:00.535038
8745 22:16:00.535608 Set Vref, RX VrefLevel [Byte0]: 75
8746 22:16:00.537367 [Byte1]: 75
8747 22:16:00.541681
8748 22:16:00.542155 Final RX Vref Byte 0 = 58 to rank0
8749 22:16:00.545301 Final RX Vref Byte 1 = 62 to rank0
8750 22:16:00.549097 Final RX Vref Byte 0 = 58 to rank1
8751 22:16:00.552209 Final RX Vref Byte 1 = 62 to rank1==
8752 22:16:00.555063 Dram Type= 6, Freq= 0, CH_1, rank 0
8753 22:16:00.562146 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8754 22:16:00.562766 ==
8755 22:16:00.563152 DQS Delay:
8756 22:16:00.565308 DQS0 = 0, DQS1 = 0
8757 22:16:00.565878 DQM Delay:
8758 22:16:00.566254 DQM0 = 134, DQM1 = 129
8759 22:16:00.568376 DQ Delay:
8760 22:16:00.572102 DQ0 =136, DQ1 =128, DQ2 =122, DQ3 =132
8761 22:16:00.575247 DQ4 =132, DQ5 =144, DQ6 =146, DQ7 =132
8762 22:16:00.578546 DQ8 =116, DQ9 =120, DQ10 =132, DQ11 =122
8763 22:16:00.581202 DQ12 =140, DQ13 =134, DQ14 =136, DQ15 =136
8764 22:16:00.581678
8765 22:16:00.582052
8766 22:16:00.582423
8767 22:16:00.585103 [DramC_TX_OE_Calibration] TA2
8768 22:16:00.588078 Original DQ_B0 (3 6) =30, OEN = 27
8769 22:16:00.591507 Original DQ_B1 (3 6) =30, OEN = 27
8770 22:16:00.594573 24, 0x0, End_B0=24 End_B1=24
8771 22:16:00.595164 25, 0x0, End_B0=25 End_B1=25
8772 22:16:00.598316 26, 0x0, End_B0=26 End_B1=26
8773 22:16:00.601680 27, 0x0, End_B0=27 End_B1=27
8774 22:16:00.605085 28, 0x0, End_B0=28 End_B1=28
8775 22:16:00.607888 29, 0x0, End_B0=29 End_B1=29
8776 22:16:00.608465 30, 0x0, End_B0=30 End_B1=30
8777 22:16:00.611956 31, 0x4141, End_B0=30 End_B1=30
8778 22:16:00.614384 Byte0 end_step=30 best_step=27
8779 22:16:00.618015 Byte1 end_step=30 best_step=27
8780 22:16:00.621378 Byte0 TX OE(2T, 0.5T) = (3, 3)
8781 22:16:00.624625 Byte1 TX OE(2T, 0.5T) = (3, 3)
8782 22:16:00.625106
8783 22:16:00.625478
8784 22:16:00.631243 [DQSOSCAuto] RK0, (LSB)MR18= 0x1927, (MSB)MR19= 0x303, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
8785 22:16:00.634327 CH1 RK0: MR19=303, MR18=1927
8786 22:16:00.641079 CH1_RK0: MR19=0x303, MR18=0x1927, DQSOSC=390, MR23=63, INC=24, DEC=16
8787 22:16:00.641562
8788 22:16:00.644599 ----->DramcWriteLeveling(PI) begin...
8789 22:16:00.645180 ==
8790 22:16:00.647696 Dram Type= 6, Freq= 0, CH_1, rank 1
8791 22:16:00.651313 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8792 22:16:00.651885 ==
8793 22:16:00.654149 Write leveling (Byte 0): 23 => 23
8794 22:16:00.657854 Write leveling (Byte 1): 28 => 28
8795 22:16:00.660807 DramcWriteLeveling(PI) end<-----
8796 22:16:00.661381
8797 22:16:00.661758 ==
8798 22:16:00.664355 Dram Type= 6, Freq= 0, CH_1, rank 1
8799 22:16:00.667633 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8800 22:16:00.668209 ==
8801 22:16:00.670740 [Gating] SW mode calibration
8802 22:16:00.677468 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8803 22:16:00.684194 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8804 22:16:00.687262 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8805 22:16:00.694138 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8806 22:16:00.697428 1 4 8 | B1->B0 | 3333 2323 | 1 0 | (1 1) (0 0)
8807 22:16:00.700664 1 4 12 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (1 1)
8808 22:16:00.707400 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8809 22:16:00.710532 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8810 22:16:00.713765 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8811 22:16:00.720565 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8812 22:16:00.724420 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8813 22:16:00.726750 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8814 22:16:00.733605 1 5 8 | B1->B0 | 2727 3434 | 0 1 | (0 0) (1 0)
8815 22:16:00.737090 1 5 12 | B1->B0 | 2323 3131 | 0 1 | (1 0) (1 0)
8816 22:16:00.740276 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8817 22:16:00.747070 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8818 22:16:00.750336 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8819 22:16:00.753255 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8820 22:16:00.760370 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8821 22:16:00.763069 1 6 4 | B1->B0 | 2726 2323 | 1 0 | (0 0) (0 0)
8822 22:16:00.766667 1 6 8 | B1->B0 | 4444 2525 | 0 0 | (0 0) (0 0)
8823 22:16:00.773875 1 6 12 | B1->B0 | 4646 4040 | 0 0 | (0 0) (0 0)
8824 22:16:00.776644 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8825 22:16:00.779987 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8826 22:16:00.786304 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8827 22:16:00.789756 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8828 22:16:00.792899 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8829 22:16:00.799786 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8830 22:16:00.802949 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8831 22:16:00.806310 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8832 22:16:00.813087 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8833 22:16:00.816010 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8834 22:16:00.819623 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8835 22:16:00.826302 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8836 22:16:00.829151 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8837 22:16:00.832434 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8838 22:16:00.838860 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8839 22:16:00.842407 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8840 22:16:00.845627 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8841 22:16:00.852215 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8842 22:16:00.855664 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8843 22:16:00.858969 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8844 22:16:00.865172 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8845 22:16:00.868384 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8846 22:16:00.871861 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8847 22:16:00.878610 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8848 22:16:00.879166 Total UI for P1: 0, mck2ui 16
8849 22:16:00.884977 best dqsien dly found for B0: ( 1, 9, 8)
8850 22:16:00.885547 Total UI for P1: 0, mck2ui 16
8851 22:16:00.891373 best dqsien dly found for B1: ( 1, 9, 8)
8852 22:16:00.894950 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8853 22:16:00.898093 best DQS1 dly(MCK, UI, PI) = (1, 9, 8)
8854 22:16:00.898906
8855 22:16:00.902459 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8856 22:16:00.904988 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 8)
8857 22:16:00.907797 [Gating] SW calibration Done
8858 22:16:00.908274 ==
8859 22:16:00.911921 Dram Type= 6, Freq= 0, CH_1, rank 1
8860 22:16:00.914638 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8861 22:16:00.915213 ==
8862 22:16:00.917927 RX Vref Scan: 0
8863 22:16:00.918535
8864 22:16:00.918918 RX Vref 0 -> 0, step: 1
8865 22:16:00.919267
8866 22:16:00.921275 RX Delay 0 -> 252, step: 8
8867 22:16:00.924636 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8868 22:16:00.931311 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8869 22:16:00.934584 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8870 22:16:00.937998 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8871 22:16:00.940945 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8872 22:16:00.944519 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8873 22:16:00.950637 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8874 22:16:00.954241 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8875 22:16:00.957922 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8876 22:16:00.960912 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8877 22:16:00.964328 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8878 22:16:00.971069 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8879 22:16:00.974160 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8880 22:16:00.977642 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8881 22:16:00.980687 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8882 22:16:00.987209 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8883 22:16:00.987770 ==
8884 22:16:00.990513 Dram Type= 6, Freq= 0, CH_1, rank 1
8885 22:16:00.994540 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8886 22:16:00.995107 ==
8887 22:16:00.995487 DQS Delay:
8888 22:16:00.997228 DQS0 = 0, DQS1 = 0
8889 22:16:00.997797 DQM Delay:
8890 22:16:01.000411 DQM0 = 136, DQM1 = 131
8891 22:16:01.000887 DQ Delay:
8892 22:16:01.003638 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8893 22:16:01.006942 DQ4 =139, DQ5 =147, DQ6 =139, DQ7 =135
8894 22:16:01.010140 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =127
8895 22:16:01.013790 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =143
8896 22:16:01.016877
8897 22:16:01.017446
8898 22:16:01.017815 ==
8899 22:16:01.020335 Dram Type= 6, Freq= 0, CH_1, rank 1
8900 22:16:01.023723 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8901 22:16:01.024294 ==
8902 22:16:01.024667
8903 22:16:01.025013
8904 22:16:01.027082 TX Vref Scan disable
8905 22:16:01.027558 == TX Byte 0 ==
8906 22:16:01.033673 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8907 22:16:01.036974 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8908 22:16:01.037554 == TX Byte 1 ==
8909 22:16:01.043279 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8910 22:16:01.046916 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8911 22:16:01.047493 ==
8912 22:16:01.050139 Dram Type= 6, Freq= 0, CH_1, rank 1
8913 22:16:01.053182 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8914 22:16:01.053754 ==
8915 22:16:01.067185
8916 22:16:01.069935 TX Vref early break, caculate TX vref
8917 22:16:01.073347 TX Vref=16, minBit 9, minWin=21, winSum=378
8918 22:16:01.077208 TX Vref=18, minBit 10, minWin=23, winSum=391
8919 22:16:01.079699 TX Vref=20, minBit 9, minWin=23, winSum=393
8920 22:16:01.083477 TX Vref=22, minBit 9, minWin=23, winSum=406
8921 22:16:01.087138 TX Vref=24, minBit 12, minWin=24, winSum=415
8922 22:16:01.093237 TX Vref=26, minBit 9, minWin=25, winSum=419
8923 22:16:01.096621 TX Vref=28, minBit 15, minWin=25, winSum=424
8924 22:16:01.099916 TX Vref=30, minBit 9, minWin=24, winSum=411
8925 22:16:01.103320 TX Vref=32, minBit 0, minWin=25, winSum=413
8926 22:16:01.106856 TX Vref=34, minBit 8, minWin=24, winSum=400
8927 22:16:01.113567 [TxChooseVref] Worse bit 15, Min win 25, Win sum 424, Final Vref 28
8928 22:16:01.114139
8929 22:16:01.116455 Final TX Range 0 Vref 28
8930 22:16:01.117024
8931 22:16:01.117402 ==
8932 22:16:01.119670 Dram Type= 6, Freq= 0, CH_1, rank 1
8933 22:16:01.123090 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8934 22:16:01.123567 ==
8935 22:16:01.123940
8936 22:16:01.124282
8937 22:16:01.126187 TX Vref Scan disable
8938 22:16:01.132576 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8939 22:16:01.133133 == TX Byte 0 ==
8940 22:16:01.136291 u2DelayCellOfst[0]=13 cells (4 PI)
8941 22:16:01.139289 u2DelayCellOfst[1]=10 cells (3 PI)
8942 22:16:01.143643 u2DelayCellOfst[2]=0 cells (0 PI)
8943 22:16:01.145787 u2DelayCellOfst[3]=6 cells (2 PI)
8944 22:16:01.149435 u2DelayCellOfst[4]=6 cells (2 PI)
8945 22:16:01.153054 u2DelayCellOfst[5]=16 cells (5 PI)
8946 22:16:01.156108 u2DelayCellOfst[6]=16 cells (5 PI)
8947 22:16:01.158962 u2DelayCellOfst[7]=3 cells (1 PI)
8948 22:16:01.162743 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8949 22:16:01.165793 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8950 22:16:01.168802 == TX Byte 1 ==
8951 22:16:01.172612 u2DelayCellOfst[8]=0 cells (0 PI)
8952 22:16:01.175737 u2DelayCellOfst[9]=0 cells (0 PI)
8953 22:16:01.178878 u2DelayCellOfst[10]=6 cells (2 PI)
8954 22:16:01.179443 u2DelayCellOfst[11]=3 cells (1 PI)
8955 22:16:01.181965 u2DelayCellOfst[12]=13 cells (4 PI)
8956 22:16:01.185669 u2DelayCellOfst[13]=13 cells (4 PI)
8957 22:16:01.188791 u2DelayCellOfst[14]=16 cells (5 PI)
8958 22:16:01.191930 u2DelayCellOfst[15]=16 cells (5 PI)
8959 22:16:01.198990 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8960 22:16:01.201933 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8961 22:16:01.202448 DramC Write-DBI on
8962 22:16:01.202830 ==
8963 22:16:01.206083 Dram Type= 6, Freq= 0, CH_1, rank 1
8964 22:16:01.212738 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8965 22:16:01.213306 ==
8966 22:16:01.213678
8967 22:16:01.214025
8968 22:16:01.214394 TX Vref Scan disable
8969 22:16:01.216372 == TX Byte 0 ==
8970 22:16:01.219847 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8971 22:16:01.223144 == TX Byte 1 ==
8972 22:16:01.226815 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8973 22:16:01.230306 DramC Write-DBI off
8974 22:16:01.230902
8975 22:16:01.231280 [DATLAT]
8976 22:16:01.231625 Freq=1600, CH1 RK1
8977 22:16:01.231963
8978 22:16:01.232609 DATLAT Default: 0xf
8979 22:16:01.236686 0, 0xFFFF, sum = 0
8980 22:16:01.237318 1, 0xFFFF, sum = 0
8981 22:16:01.239313 2, 0xFFFF, sum = 0
8982 22:16:01.239792 3, 0xFFFF, sum = 0
8983 22:16:01.242392 4, 0xFFFF, sum = 0
8984 22:16:01.242876 5, 0xFFFF, sum = 0
8985 22:16:01.245977 6, 0xFFFF, sum = 0
8986 22:16:01.246580 7, 0xFFFF, sum = 0
8987 22:16:01.249533 8, 0xFFFF, sum = 0
8988 22:16:01.250105 9, 0xFFFF, sum = 0
8989 22:16:01.252878 10, 0xFFFF, sum = 0
8990 22:16:01.253456 11, 0xFFFF, sum = 0
8991 22:16:01.255826 12, 0xFFFF, sum = 0
8992 22:16:01.256405 13, 0xFFFF, sum = 0
8993 22:16:01.259267 14, 0x0, sum = 1
8994 22:16:01.259841 15, 0x0, sum = 2
8995 22:16:01.262567 16, 0x0, sum = 3
8996 22:16:01.263146 17, 0x0, sum = 4
8997 22:16:01.265598 best_step = 15
8998 22:16:01.266068
8999 22:16:01.266473 ==
9000 22:16:01.269064 Dram Type= 6, Freq= 0, CH_1, rank 1
9001 22:16:01.272347 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9002 22:16:01.272919 ==
9003 22:16:01.275655 RX Vref Scan: 0
9004 22:16:01.276222
9005 22:16:01.276598 RX Vref 0 -> 0, step: 1
9006 22:16:01.276949
9007 22:16:01.278805 RX Delay 19 -> 252, step: 4
9008 22:16:01.285717 iDelay=195, Bit 0, Center 136 (91 ~ 182) 92
9009 22:16:01.289010 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
9010 22:16:01.292955 iDelay=195, Bit 2, Center 120 (71 ~ 170) 100
9011 22:16:01.295546 iDelay=195, Bit 3, Center 132 (83 ~ 182) 100
9012 22:16:01.298749 iDelay=195, Bit 4, Center 134 (87 ~ 182) 96
9013 22:16:01.301846 iDelay=195, Bit 5, Center 144 (99 ~ 190) 92
9014 22:16:01.308735 iDelay=195, Bit 6, Center 142 (95 ~ 190) 96
9015 22:16:01.312372 iDelay=195, Bit 7, Center 130 (83 ~ 178) 96
9016 22:16:01.315408 iDelay=195, Bit 8, Center 112 (63 ~ 162) 100
9017 22:16:01.318820 iDelay=195, Bit 9, Center 120 (71 ~ 170) 100
9018 22:16:01.322294 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
9019 22:16:01.328375 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
9020 22:16:01.331748 iDelay=195, Bit 12, Center 138 (87 ~ 190) 104
9021 22:16:01.335643 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
9022 22:16:01.338566 iDelay=195, Bit 14, Center 138 (91 ~ 186) 96
9023 22:16:01.344888 iDelay=195, Bit 15, Center 142 (91 ~ 194) 104
9024 22:16:01.345442 ==
9025 22:16:01.348054 Dram Type= 6, Freq= 0, CH_1, rank 1
9026 22:16:01.351966 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9027 22:16:01.352546 ==
9028 22:16:01.352926 DQS Delay:
9029 22:16:01.355234 DQS0 = 0, DQS1 = 0
9030 22:16:01.355800 DQM Delay:
9031 22:16:01.358274 DQM0 = 133, DQM1 = 130
9032 22:16:01.358870 DQ Delay:
9033 22:16:01.361376 DQ0 =136, DQ1 =130, DQ2 =120, DQ3 =132
9034 22:16:01.364108 DQ4 =134, DQ5 =144, DQ6 =142, DQ7 =130
9035 22:16:01.367728 DQ8 =112, DQ9 =120, DQ10 =130, DQ11 =124
9036 22:16:01.371050 DQ12 =138, DQ13 =138, DQ14 =138, DQ15 =142
9037 22:16:01.374566
9038 22:16:01.375131
9039 22:16:01.375509
9040 22:16:01.375852 [DramC_TX_OE_Calibration] TA2
9041 22:16:01.377557 Original DQ_B0 (3 6) =30, OEN = 27
9042 22:16:01.380807 Original DQ_B1 (3 6) =30, OEN = 27
9043 22:16:01.384696 24, 0x0, End_B0=24 End_B1=24
9044 22:16:01.387485 25, 0x0, End_B0=25 End_B1=25
9045 22:16:01.390732 26, 0x0, End_B0=26 End_B1=26
9046 22:16:01.391307 27, 0x0, End_B0=27 End_B1=27
9047 22:16:01.394186 28, 0x0, End_B0=28 End_B1=28
9048 22:16:01.398124 29, 0x0, End_B0=29 End_B1=29
9049 22:16:01.401675 30, 0x0, End_B0=30 End_B1=30
9050 22:16:01.403876 31, 0x4141, End_B0=30 End_B1=30
9051 22:16:01.407672 Byte0 end_step=30 best_step=27
9052 22:16:01.408372 Byte1 end_step=30 best_step=27
9053 22:16:01.410551 Byte0 TX OE(2T, 0.5T) = (3, 3)
9054 22:16:01.413817 Byte1 TX OE(2T, 0.5T) = (3, 3)
9055 22:16:01.414291
9056 22:16:01.414716
9057 22:16:01.424159 [DQSOSCAuto] RK1, (LSB)MR18= 0x1e08, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 394 ps
9058 22:16:01.424724 CH1 RK1: MR19=303, MR18=1E08
9059 22:16:01.430863 CH1_RK1: MR19=0x303, MR18=0x1E08, DQSOSC=394, MR23=63, INC=23, DEC=15
9060 22:16:01.433741 [RxdqsGatingPostProcess] freq 1600
9061 22:16:01.440690 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9062 22:16:01.443586 best DQS0 dly(2T, 0.5T) = (1, 1)
9063 22:16:01.448577 best DQS1 dly(2T, 0.5T) = (1, 1)
9064 22:16:01.450238 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9065 22:16:01.453700 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9066 22:16:01.454273 best DQS0 dly(2T, 0.5T) = (1, 1)
9067 22:16:01.456959 best DQS1 dly(2T, 0.5T) = (1, 1)
9068 22:16:01.460668 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9069 22:16:01.463938 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9070 22:16:01.467322 Pre-setting of DQS Precalculation
9071 22:16:01.473264 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9072 22:16:01.479751 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9073 22:16:01.486464 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9074 22:16:01.487030
9075 22:16:01.487406
9076 22:16:01.489716 [Calibration Summary] 3200 Mbps
9077 22:16:01.490284 CH 0, Rank 0
9078 22:16:01.493256 SW Impedance : PASS
9079 22:16:01.496322 DUTY Scan : NO K
9080 22:16:01.496880 ZQ Calibration : PASS
9081 22:16:01.499658 Jitter Meter : NO K
9082 22:16:01.502758 CBT Training : PASS
9083 22:16:01.503236 Write leveling : PASS
9084 22:16:01.506691 RX DQS gating : PASS
9085 22:16:01.509339 RX DQ/DQS(RDDQC) : PASS
9086 22:16:01.509813 TX DQ/DQS : PASS
9087 22:16:01.513075 RX DATLAT : PASS
9088 22:16:01.516599 RX DQ/DQS(Engine): PASS
9089 22:16:01.517183 TX OE : PASS
9090 22:16:01.519641 All Pass.
9091 22:16:01.520205
9092 22:16:01.520582 CH 0, Rank 1
9093 22:16:01.523306 SW Impedance : PASS
9094 22:16:01.523864 DUTY Scan : NO K
9095 22:16:01.525882 ZQ Calibration : PASS
9096 22:16:01.529965 Jitter Meter : NO K
9097 22:16:01.530571 CBT Training : PASS
9098 22:16:01.533345 Write leveling : PASS
9099 22:16:01.535813 RX DQS gating : PASS
9100 22:16:01.536378 RX DQ/DQS(RDDQC) : PASS
9101 22:16:01.539152 TX DQ/DQS : PASS
9102 22:16:01.542639 RX DATLAT : PASS
9103 22:16:01.543356 RX DQ/DQS(Engine): PASS
9104 22:16:01.545699 TX OE : PASS
9105 22:16:01.546116 All Pass.
9106 22:16:01.546499
9107 22:16:01.549308 CH 1, Rank 0
9108 22:16:01.549867 SW Impedance : PASS
9109 22:16:01.552669 DUTY Scan : NO K
9110 22:16:01.555915 ZQ Calibration : PASS
9111 22:16:01.556394 Jitter Meter : NO K
9112 22:16:01.559290 CBT Training : PASS
9113 22:16:01.559766 Write leveling : PASS
9114 22:16:01.562054 RX DQS gating : PASS
9115 22:16:01.566033 RX DQ/DQS(RDDQC) : PASS
9116 22:16:01.566644 TX DQ/DQS : PASS
9117 22:16:01.569381 RX DATLAT : PASS
9118 22:16:01.572415 RX DQ/DQS(Engine): PASS
9119 22:16:01.572992 TX OE : PASS
9120 22:16:01.575873 All Pass.
9121 22:16:01.576449
9122 22:16:01.576823 CH 1, Rank 1
9123 22:16:01.579118 SW Impedance : PASS
9124 22:16:01.579694 DUTY Scan : NO K
9125 22:16:01.582145 ZQ Calibration : PASS
9126 22:16:01.585631 Jitter Meter : NO K
9127 22:16:01.586230 CBT Training : PASS
9128 22:16:01.588873 Write leveling : PASS
9129 22:16:01.592149 RX DQS gating : PASS
9130 22:16:01.592855 RX DQ/DQS(RDDQC) : PASS
9131 22:16:01.595449 TX DQ/DQS : PASS
9132 22:16:01.598866 RX DATLAT : PASS
9133 22:16:01.599445 RX DQ/DQS(Engine): PASS
9134 22:16:01.602079 TX OE : PASS
9135 22:16:01.602601 All Pass.
9136 22:16:01.602978
9137 22:16:01.605361 DramC Write-DBI on
9138 22:16:01.608925 PER_BANK_REFRESH: Hybrid Mode
9139 22:16:01.609398 TX_TRACKING: ON
9140 22:16:01.618799 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9141 22:16:01.624954 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9142 22:16:01.632028 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9143 22:16:01.635563 [FAST_K] Save calibration result to emmc
9144 22:16:01.638583 sync common calibartion params.
9145 22:16:01.642112 sync cbt_mode0:1, 1:1
9146 22:16:01.645091 dram_init: ddr_geometry: 2
9147 22:16:01.645545 dram_init: ddr_geometry: 2
9148 22:16:01.648398 dram_init: ddr_geometry: 2
9149 22:16:01.652466 0:dram_rank_size:100000000
9150 22:16:01.654712 1:dram_rank_size:100000000
9151 22:16:01.658684 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9152 22:16:01.661835 DFS_SHUFFLE_HW_MODE: ON
9153 22:16:01.665216 dramc_set_vcore_voltage set vcore to 725000
9154 22:16:01.668596 Read voltage for 1600, 0
9155 22:16:01.669127 Vio18 = 0
9156 22:16:01.669469 Vcore = 725000
9157 22:16:01.671086 Vdram = 0
9158 22:16:01.671512 Vddq = 0
9159 22:16:01.671850 Vmddr = 0
9160 22:16:01.675790 switch to 3200 Mbps bootup
9161 22:16:01.677929 [DramcRunTimeConfig]
9162 22:16:01.678387 PHYPLL
9163 22:16:01.678737 DPM_CONTROL_AFTERK: ON
9164 22:16:01.681798 PER_BANK_REFRESH: ON
9165 22:16:01.684810 REFRESH_OVERHEAD_REDUCTION: ON
9166 22:16:01.685336 CMD_PICG_NEW_MODE: OFF
9167 22:16:01.688036 XRTWTW_NEW_MODE: ON
9168 22:16:01.691272 XRTRTR_NEW_MODE: ON
9169 22:16:01.691799 TX_TRACKING: ON
9170 22:16:01.694259 RDSEL_TRACKING: OFF
9171 22:16:01.694847 DQS Precalculation for DVFS: ON
9172 22:16:01.697925 RX_TRACKING: OFF
9173 22:16:01.698505 HW_GATING DBG: ON
9174 22:16:01.700916 ZQCS_ENABLE_LP4: ON
9175 22:16:01.704737 RX_PICG_NEW_MODE: ON
9176 22:16:01.705273 TX_PICG_NEW_MODE: ON
9177 22:16:01.707218 ENABLE_RX_DCM_DPHY: ON
9178 22:16:01.710591 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9179 22:16:01.711183 DUMMY_READ_FOR_TRACKING: OFF
9180 22:16:01.714130 !!! SPM_CONTROL_AFTERK: OFF
9181 22:16:01.717587 !!! SPM could not control APHY
9182 22:16:01.721156 IMPEDANCE_TRACKING: ON
9183 22:16:01.721690 TEMP_SENSOR: ON
9184 22:16:01.724037 HW_SAVE_FOR_SR: OFF
9185 22:16:01.727377 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9186 22:16:01.730480 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9187 22:16:01.730916 Read ODT Tracking: ON
9188 22:16:01.733806 Refresh Rate DeBounce: ON
9189 22:16:01.737029 DFS_NO_QUEUE_FLUSH: ON
9190 22:16:01.740418 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9191 22:16:01.740847 ENABLE_DFS_RUNTIME_MRW: OFF
9192 22:16:01.743653 DDR_RESERVE_NEW_MODE: ON
9193 22:16:01.747255 MR_CBT_SWITCH_FREQ: ON
9194 22:16:01.747681 =========================
9195 22:16:01.768037 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9196 22:16:01.770695 dram_init: ddr_geometry: 2
9197 22:16:01.789465 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9198 22:16:01.792355 dram_init: dram init end (result: 0)
9199 22:16:01.798954 DRAM-K: Full calibration passed in 24534 msecs
9200 22:16:01.802508 MRC: failed to locate region type 0.
9201 22:16:01.803082 DRAM rank0 size:0x100000000,
9202 22:16:01.805483 DRAM rank1 size=0x100000000
9203 22:16:01.814991 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9204 22:16:01.822127 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9205 22:16:01.828488 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9206 22:16:01.834879 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9207 22:16:01.838632 DRAM rank0 size:0x100000000,
9208 22:16:01.842199 DRAM rank1 size=0x100000000
9209 22:16:01.842838 CBMEM:
9210 22:16:01.844919 IMD: root @ 0xfffff000 254 entries.
9211 22:16:01.848494 IMD: root @ 0xffffec00 62 entries.
9212 22:16:01.851528 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9213 22:16:01.858216 WARNING: RO_VPD is uninitialized or empty.
9214 22:16:01.861460 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9215 22:16:01.869404 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9216 22:16:01.881795 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9217 22:16:01.892966 BS: romstage times (exec / console): total (unknown) / 24030 ms
9218 22:16:01.893569
9219 22:16:01.893948
9220 22:16:01.902976 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9221 22:16:01.906515 ARM64: Exception handlers installed.
9222 22:16:01.909206 ARM64: Testing exception
9223 22:16:01.912795 ARM64: Done test exception
9224 22:16:01.913301 Enumerating buses...
9225 22:16:01.915879 Show all devs... Before device enumeration.
9226 22:16:01.919318 Root Device: enabled 1
9227 22:16:01.922530 CPU_CLUSTER: 0: enabled 1
9228 22:16:01.923004 CPU: 00: enabled 1
9229 22:16:01.925881 Compare with tree...
9230 22:16:01.926485 Root Device: enabled 1
9231 22:16:01.929332 CPU_CLUSTER: 0: enabled 1
9232 22:16:01.932600 CPU: 00: enabled 1
9233 22:16:01.933074 Root Device scanning...
9234 22:16:01.936349 scan_static_bus for Root Device
9235 22:16:01.939280 CPU_CLUSTER: 0 enabled
9236 22:16:01.942263 scan_static_bus for Root Device done
9237 22:16:01.945534 scan_bus: bus Root Device finished in 8 msecs
9238 22:16:01.945998 done
9239 22:16:01.952625 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9240 22:16:01.956676 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9241 22:16:01.962714 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9242 22:16:01.965566 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9243 22:16:01.969164 Allocating resources...
9244 22:16:01.972533 Reading resources...
9245 22:16:01.975447 Root Device read_resources bus 0 link: 0
9246 22:16:01.979265 DRAM rank0 size:0x100000000,
9247 22:16:01.979832 DRAM rank1 size=0x100000000
9248 22:16:01.981994 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9249 22:16:01.985321 CPU: 00 missing read_resources
9250 22:16:01.992045 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9251 22:16:01.995406 Root Device read_resources bus 0 link: 0 done
9252 22:16:01.998799 Done reading resources.
9253 22:16:02.002096 Show resources in subtree (Root Device)...After reading.
9254 22:16:02.004904 Root Device child on link 0 CPU_CLUSTER: 0
9255 22:16:02.008568 CPU_CLUSTER: 0 child on link 0 CPU: 00
9256 22:16:02.018825 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9257 22:16:02.019307 CPU: 00
9258 22:16:02.021342 Root Device assign_resources, bus 0 link: 0
9259 22:16:02.025039 CPU_CLUSTER: 0 missing set_resources
9260 22:16:02.031321 Root Device assign_resources, bus 0 link: 0 done
9261 22:16:02.031888 Done setting resources.
9262 22:16:02.037989 Show resources in subtree (Root Device)...After assigning values.
9263 22:16:02.041786 Root Device child on link 0 CPU_CLUSTER: 0
9264 22:16:02.044529 CPU_CLUSTER: 0 child on link 0 CPU: 00
9265 22:16:02.054804 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9266 22:16:02.055382 CPU: 00
9267 22:16:02.057867 Done allocating resources.
9268 22:16:02.064658 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9269 22:16:02.065242 Enabling resources...
9270 22:16:02.068087 done.
9271 22:16:02.071322 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9272 22:16:02.075028 Initializing devices...
9273 22:16:02.075606 Root Device init
9274 22:16:02.077855 init hardware done!
9275 22:16:02.078472 0x00000018: ctrlr->caps
9276 22:16:02.081721 52.000 MHz: ctrlr->f_max
9277 22:16:02.084452 0.400 MHz: ctrlr->f_min
9278 22:16:02.084935 0x40ff8080: ctrlr->voltages
9279 22:16:02.088173 sclk: 390625
9280 22:16:02.088746 Bus Width = 1
9281 22:16:02.091219 sclk: 390625
9282 22:16:02.091793 Bus Width = 1
9283 22:16:02.094218 Early init status = 3
9284 22:16:02.097250 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9285 22:16:02.100928 in-header: 03 fc 00 00 01 00 00 00
9286 22:16:02.104681 in-data: 00
9287 22:16:02.107835 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9288 22:16:02.111968 in-header: 03 fd 00 00 00 00 00 00
9289 22:16:02.114840 in-data:
9290 22:16:02.118476 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9291 22:16:02.122565 in-header: 03 fc 00 00 01 00 00 00
9292 22:16:02.125909 in-data: 00
9293 22:16:02.128753 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9294 22:16:02.135094 in-header: 03 fd 00 00 00 00 00 00
9295 22:16:02.137803 in-data:
9296 22:16:02.141039 [SSUSB] Setting up USB HOST controller...
9297 22:16:02.144262 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9298 22:16:02.148117 [SSUSB] phy power-on done.
9299 22:16:02.151885 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9300 22:16:02.157908 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9301 22:16:02.161037 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9302 22:16:02.167805 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9303 22:16:02.174426 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9304 22:16:02.180924 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9305 22:16:02.188014 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9306 22:16:02.194485 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9307 22:16:02.197862 SPM: binary array size = 0x9dc
9308 22:16:02.201264 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9309 22:16:02.207468 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9310 22:16:02.213761 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9311 22:16:02.220969 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9312 22:16:02.223849 configure_display: Starting display init
9313 22:16:02.258409 anx7625_power_on_init: Init interface.
9314 22:16:02.260881 anx7625_disable_pd_protocol: Disabled PD feature.
9315 22:16:02.264250 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9316 22:16:02.292494 anx7625_start_dp_work: Secure OCM version=00
9317 22:16:02.295888 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9318 22:16:02.310504 sp_tx_get_edid_block: EDID Block = 1
9319 22:16:02.413169 Extracted contents:
9320 22:16:02.416771 header: 00 ff ff ff ff ff ff 00
9321 22:16:02.419278 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9322 22:16:02.423259 version: 01 04
9323 22:16:02.425886 basic params: 95 1f 11 78 0a
9324 22:16:02.429431 chroma info: 76 90 94 55 54 90 27 21 50 54
9325 22:16:02.432897 established: 00 00 00
9326 22:16:02.439320 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9327 22:16:02.442511 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9328 22:16:02.449025 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9329 22:16:02.455555 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9330 22:16:02.462090 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9331 22:16:02.465159 extensions: 00
9332 22:16:02.465320 checksum: fb
9333 22:16:02.465395
9334 22:16:02.472885 Manufacturer: IVO Model 57d Serial Number 0
9335 22:16:02.473060 Made week 0 of 2020
9336 22:16:02.475185 EDID version: 1.4
9337 22:16:02.475338 Digital display
9338 22:16:02.478113 6 bits per primary color channel
9339 22:16:02.481607 DisplayPort interface
9340 22:16:02.481814 Maximum image size: 31 cm x 17 cm
9341 22:16:02.485389 Gamma: 220%
9342 22:16:02.485518 Check DPMS levels
9343 22:16:02.491682 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9344 22:16:02.494922 First detailed timing is preferred timing
9345 22:16:02.498441 Established timings supported:
9346 22:16:02.498692 Standard timings supported:
9347 22:16:02.501566 Detailed timings
9348 22:16:02.505019 Hex of detail: 383680a07038204018303c0035ae10000019
9349 22:16:02.511816 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9350 22:16:02.514739 0780 0798 07c8 0820 hborder 0
9351 22:16:02.518553 0438 043b 0447 0458 vborder 0
9352 22:16:02.521807 -hsync -vsync
9353 22:16:02.522269 Did detailed timing
9354 22:16:02.528672 Hex of detail: 000000000000000000000000000000000000
9355 22:16:02.531926 Manufacturer-specified data, tag 0
9356 22:16:02.534988 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9357 22:16:02.538160 ASCII string: InfoVision
9358 22:16:02.541202 Hex of detail: 000000fe00523134304e574635205248200a
9359 22:16:02.544639 ASCII string: R140NWF5 RH
9360 22:16:02.545206 Checksum
9361 22:16:02.547887 Checksum: 0xfb (valid)
9362 22:16:02.551172 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9363 22:16:02.554515 DSI data_rate: 832800000 bps
9364 22:16:02.561244 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9365 22:16:02.564161 anx7625_parse_edid: pixelclock(138800).
9366 22:16:02.567709 hactive(1920), hsync(48), hfp(24), hbp(88)
9367 22:16:02.571303 vactive(1080), vsync(12), vfp(3), vbp(17)
9368 22:16:02.574060 anx7625_dsi_config: config dsi.
9369 22:16:02.581313 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9370 22:16:02.595179 anx7625_dsi_config: success to config DSI
9371 22:16:02.598546 anx7625_dp_start: MIPI phy setup OK.
9372 22:16:02.602092 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9373 22:16:02.604804 mtk_ddp_mode_set invalid vrefresh 60
9374 22:16:02.608274 main_disp_path_setup
9375 22:16:02.608748 ovl_layer_smi_id_en
9376 22:16:02.611942 ovl_layer_smi_id_en
9377 22:16:02.612509 ccorr_config
9378 22:16:02.612883 aal_config
9379 22:16:02.615004 gamma_config
9380 22:16:02.615595 postmask_config
9381 22:16:02.618242 dither_config
9382 22:16:02.621585 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9383 22:16:02.627966 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9384 22:16:02.631384 Root Device init finished in 553 msecs
9385 22:16:02.634702 CPU_CLUSTER: 0 init
9386 22:16:02.641130 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9387 22:16:02.647767 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9388 22:16:02.648332 APU_MBOX 0x190000b0 = 0x10001
9389 22:16:02.651474 APU_MBOX 0x190001b0 = 0x10001
9390 22:16:02.654688 APU_MBOX 0x190005b0 = 0x10001
9391 22:16:02.658112 APU_MBOX 0x190006b0 = 0x10001
9392 22:16:02.664277 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9393 22:16:02.673875 read SPI 0x539f4 0xe237: 6249 us, 9267 KB/s, 74.136 Mbps
9394 22:16:02.686767 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9395 22:16:02.693263 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9396 22:16:02.704748 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9397 22:16:02.713931 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9398 22:16:02.717441 CPU_CLUSTER: 0 init finished in 81 msecs
9399 22:16:02.721700 Devices initialized
9400 22:16:02.723822 Show all devs... After init.
9401 22:16:02.724395 Root Device: enabled 1
9402 22:16:02.726942 CPU_CLUSTER: 0: enabled 1
9403 22:16:02.730283 CPU: 00: enabled 1
9404 22:16:02.733750 BS: BS_DEV_INIT run times (exec / console): 211 / 447 ms
9405 22:16:02.737007 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9406 22:16:02.740168 ELOG: NV offset 0x57f000 size 0x1000
9407 22:16:02.746879 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9408 22:16:02.753590 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9409 22:16:02.756795 ELOG: Event(17) added with size 13 at 2023-06-04 22:16:15 UTC
9410 22:16:02.760278 out: cmd=0x121: 03 db 21 01 00 00 00 00
9411 22:16:02.763839 in-header: 03 10 00 00 2c 00 00 00
9412 22:16:02.777485 in-data: 4f 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9413 22:16:02.783927 ELOG: Event(A1) added with size 10 at 2023-06-04 22:16:15 UTC
9414 22:16:02.790632 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9415 22:16:02.797287 ELOG: Event(A0) added with size 9 at 2023-06-04 22:16:15 UTC
9416 22:16:02.801283 elog_add_boot_reason: Logged dev mode boot
9417 22:16:02.803825 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9418 22:16:02.806921 Finalize devices...
9419 22:16:02.807496 Devices finalized
9420 22:16:02.813796 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9421 22:16:02.816730 Writing coreboot table at 0xffe64000
9422 22:16:02.820339 0. 000000000010a000-0000000000113fff: RAMSTAGE
9423 22:16:02.823405 1. 0000000040000000-00000000400fffff: RAM
9424 22:16:02.830188 2. 0000000040100000-000000004032afff: RAMSTAGE
9425 22:16:02.833429 3. 000000004032b000-00000000545fffff: RAM
9426 22:16:02.836568 4. 0000000054600000-000000005465ffff: BL31
9427 22:16:02.840371 5. 0000000054660000-00000000ffe63fff: RAM
9428 22:16:02.846683 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9429 22:16:02.850280 7. 0000000100000000-000000023fffffff: RAM
9430 22:16:02.853236 Passing 5 GPIOs to payload:
9431 22:16:02.856604 NAME | PORT | POLARITY | VALUE
9432 22:16:02.859778 EC in RW | 0x000000aa | low | undefined
9433 22:16:02.866228 EC interrupt | 0x00000005 | low | undefined
9434 22:16:02.869475 TPM interrupt | 0x000000ab | high | undefined
9435 22:16:02.876371 SD card detect | 0x00000011 | high | undefined
9436 22:16:02.879809 speaker enable | 0x00000093 | high | undefined
9437 22:16:02.882821 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9438 22:16:02.885891 in-header: 03 f9 00 00 02 00 00 00
9439 22:16:02.889364 in-data: 02 00
9440 22:16:02.889859 ADC[4]: Raw value=901032 ID=7
9441 22:16:02.892725 ADC[3]: Raw value=213179 ID=1
9442 22:16:02.896051 RAM Code: 0x71
9443 22:16:02.896546 ADC[6]: Raw value=74502 ID=0
9444 22:16:02.899033 ADC[5]: Raw value=212072 ID=1
9445 22:16:02.902453 SKU Code: 0x1
9446 22:16:02.905764 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 4ba3
9447 22:16:02.909573 coreboot table: 964 bytes.
9448 22:16:02.912441 IMD ROOT 0. 0xfffff000 0x00001000
9449 22:16:02.916204 IMD SMALL 1. 0xffffe000 0x00001000
9450 22:16:02.919275 RO MCACHE 2. 0xffffc000 0x00001104
9451 22:16:02.923284 CONSOLE 3. 0xfff7c000 0x00080000
9452 22:16:02.925931 FMAP 4. 0xfff7b000 0x00000452
9453 22:16:02.929281 TIME STAMP 5. 0xfff7a000 0x00000910
9454 22:16:02.932728 VBOOT WORK 6. 0xfff66000 0x00014000
9455 22:16:02.935851 RAMOOPS 7. 0xffe66000 0x00100000
9456 22:16:02.938886 COREBOOT 8. 0xffe64000 0x00002000
9457 22:16:02.939360 IMD small region:
9458 22:16:02.945833 IMD ROOT 0. 0xffffec00 0x00000400
9459 22:16:02.949237 VPD 1. 0xffffeba0 0x0000004c
9460 22:16:02.952693 MMC STATUS 2. 0xffffeb80 0x00000004
9461 22:16:02.955703 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9462 22:16:02.959196 Probing TPM: done!
9463 22:16:02.962459 Connected to device vid:did:rid of 1ae0:0028:00
9464 22:16:02.972753 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9465 22:16:02.976395 Initialized TPM device CR50 revision 0
9466 22:16:02.979403 Checking cr50 for pending updates
9467 22:16:02.983694 Reading cr50 TPM mode
9468 22:16:02.992054 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9469 22:16:02.998502 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9470 22:16:03.039019 read SPI 0x3990ec 0x4f1b0: 34851 us, 9297 KB/s, 74.376 Mbps
9471 22:16:03.042093 Checking segment from ROM address 0x40100000
9472 22:16:03.046041 Checking segment from ROM address 0x4010001c
9473 22:16:03.052058 Loading segment from ROM address 0x40100000
9474 22:16:03.052634 code (compression=0)
9475 22:16:03.061875 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9476 22:16:03.068516 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9477 22:16:03.069101 it's not compressed!
9478 22:16:03.075171 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9479 22:16:03.081953 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9480 22:16:03.099018 Loading segment from ROM address 0x4010001c
9481 22:16:03.099587 Entry Point 0x80000000
9482 22:16:03.102489 Loaded segments
9483 22:16:03.105479 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9484 22:16:03.113248 Jumping to boot code at 0x80000000(0xffe64000)
9485 22:16:03.118789 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9486 22:16:03.125671 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9487 22:16:03.133877 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9488 22:16:03.137380 Checking segment from ROM address 0x40100000
9489 22:16:03.140610 Checking segment from ROM address 0x4010001c
9490 22:16:03.146977 Loading segment from ROM address 0x40100000
9491 22:16:03.147591 code (compression=1)
9492 22:16:03.153740 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9493 22:16:03.163599 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9494 22:16:03.164173 using LZMA
9495 22:16:03.172134 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9496 22:16:03.178505 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9497 22:16:03.181796 Loading segment from ROM address 0x4010001c
9498 22:16:03.182401 Entry Point 0x54601000
9499 22:16:03.185016 Loaded segments
9500 22:16:03.188534 NOTICE: MT8192 bl31_setup
9501 22:16:03.195273 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9502 22:16:03.198514 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9503 22:16:03.202000 WARNING: region 0:
9504 22:16:03.205226 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9505 22:16:03.205892 WARNING: region 1:
9506 22:16:03.211962 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9507 22:16:03.215032 WARNING: region 2:
9508 22:16:03.218605 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9509 22:16:03.222104 WARNING: region 3:
9510 22:16:03.228320 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9511 22:16:03.228938 WARNING: region 4:
9512 22:16:03.235285 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9513 22:16:03.235863 WARNING: region 5:
9514 22:16:03.238798 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9515 22:16:03.242651 WARNING: region 6:
9516 22:16:03.245038 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9517 22:16:03.248322 WARNING: region 7:
9518 22:16:03.251474 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9519 22:16:03.258708 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9520 22:16:03.261949 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9521 22:16:03.267968 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9522 22:16:03.271544 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9523 22:16:03.274667 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9524 22:16:03.281443 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9525 22:16:03.284731 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9526 22:16:03.288775 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9527 22:16:03.294729 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9528 22:16:03.297638 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9529 22:16:03.304581 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9530 22:16:03.307486 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9531 22:16:03.311121 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9532 22:16:03.318245 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9533 22:16:03.321211 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9534 22:16:03.324718 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9535 22:16:03.330708 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9536 22:16:03.334311 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9537 22:16:03.340883 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9538 22:16:03.344811 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9539 22:16:03.347499 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9540 22:16:03.354144 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9541 22:16:03.358225 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9542 22:16:03.364247 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9543 22:16:03.367739 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9544 22:16:03.371224 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9545 22:16:03.377574 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9546 22:16:03.381139 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9547 22:16:03.387291 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9548 22:16:03.390893 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9549 22:16:03.394543 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9550 22:16:03.400774 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9551 22:16:03.404065 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9552 22:16:03.407360 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9553 22:16:03.413798 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9554 22:16:03.417486 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9555 22:16:03.420781 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9556 22:16:03.423800 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9557 22:16:03.427188 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9558 22:16:03.434827 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9559 22:16:03.436982 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9560 22:16:03.440486 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9561 22:16:03.443370 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9562 22:16:03.450758 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9563 22:16:03.453863 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9564 22:16:03.457373 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9565 22:16:03.463568 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9566 22:16:03.467268 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9567 22:16:03.470448 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9568 22:16:03.477003 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9569 22:16:03.480627 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9570 22:16:03.486888 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9571 22:16:03.490128 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9572 22:16:03.493635 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9573 22:16:03.500067 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9574 22:16:03.503954 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9575 22:16:03.510132 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9576 22:16:03.513428 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9577 22:16:03.519623 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9578 22:16:03.523658 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9579 22:16:03.529732 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9580 22:16:03.533511 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9581 22:16:03.536841 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9582 22:16:03.543213 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9583 22:16:03.546319 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9584 22:16:03.552773 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9585 22:16:03.556769 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9586 22:16:03.562852 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9587 22:16:03.567110 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9588 22:16:03.572961 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9589 22:16:03.576195 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9590 22:16:03.580279 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9591 22:16:03.586408 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9592 22:16:03.589520 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9593 22:16:03.596403 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9594 22:16:03.599721 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9595 22:16:03.605963 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9596 22:16:03.609400 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9597 22:16:03.616257 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9598 22:16:03.619215 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9599 22:16:03.622541 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9600 22:16:03.629092 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9601 22:16:03.632473 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9602 22:16:03.639625 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9603 22:16:03.642186 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9604 22:16:03.649169 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9605 22:16:03.652458 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9606 22:16:03.655885 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9607 22:16:03.662660 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9608 22:16:03.665844 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9609 22:16:03.672367 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9610 22:16:03.675880 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9611 22:16:03.682194 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9612 22:16:03.686242 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9613 22:16:03.692672 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9614 22:16:03.695582 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9615 22:16:03.699048 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9616 22:16:03.705681 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9617 22:16:03.709003 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9618 22:16:03.712700 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9619 22:16:03.715067 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9620 22:16:03.722285 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9621 22:16:03.725240 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9622 22:16:03.731873 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9623 22:16:03.735156 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9624 22:16:03.738323 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9625 22:16:03.745887 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9626 22:16:03.748411 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9627 22:16:03.755065 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9628 22:16:03.758828 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9629 22:16:03.762209 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9630 22:16:03.768693 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9631 22:16:03.772131 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9632 22:16:03.778879 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9633 22:16:03.782434 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9634 22:16:03.785939 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9635 22:16:03.788325 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9636 22:16:03.795000 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9637 22:16:03.798799 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9638 22:16:03.801902 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9639 22:16:03.808734 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9640 22:16:03.811504 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9641 22:16:03.814894 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9642 22:16:03.818569 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9643 22:16:03.826143 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9644 22:16:03.828441 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9645 22:16:03.835493 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9646 22:16:03.838189 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9647 22:16:03.841523 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9648 22:16:03.848279 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9649 22:16:03.851406 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9650 22:16:03.858319 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9651 22:16:03.861714 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9652 22:16:03.865809 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9653 22:16:03.871160 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9654 22:16:03.874805 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9655 22:16:03.881519 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9656 22:16:03.884825 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9657 22:16:03.888037 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9658 22:16:03.894994 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9659 22:16:03.898242 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9660 22:16:03.901314 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9661 22:16:03.908644 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9662 22:16:03.911235 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9663 22:16:03.918140 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9664 22:16:03.921448 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9665 22:16:03.925393 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9666 22:16:03.931560 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9667 22:16:03.934575 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9668 22:16:03.940992 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9669 22:16:03.944273 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9670 22:16:03.947670 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9671 22:16:03.954425 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9672 22:16:03.957623 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9673 22:16:03.963988 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9674 22:16:03.967950 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9675 22:16:03.970562 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9676 22:16:03.978065 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9677 22:16:03.980919 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9678 22:16:03.987192 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9679 22:16:03.991045 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9680 22:16:03.994334 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9681 22:16:04.000610 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9682 22:16:04.005147 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9683 22:16:04.010554 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9684 22:16:04.014124 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9685 22:16:04.017591 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9686 22:16:04.023718 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9687 22:16:04.027308 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9688 22:16:04.033881 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9689 22:16:04.037173 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9690 22:16:04.040197 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9691 22:16:04.046569 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9692 22:16:04.050567 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9693 22:16:04.056864 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9694 22:16:04.060701 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9695 22:16:04.063340 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9696 22:16:04.070294 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9697 22:16:04.073594 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9698 22:16:04.076973 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9699 22:16:04.083671 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9700 22:16:04.086720 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9701 22:16:04.092836 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9702 22:16:04.096659 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9703 22:16:04.102980 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9704 22:16:04.106435 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9705 22:16:04.109816 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9706 22:16:04.116486 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9707 22:16:04.119785 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9708 22:16:04.126404 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9709 22:16:04.129664 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9710 22:16:04.132853 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9711 22:16:04.140036 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9712 22:16:04.142569 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9713 22:16:04.149734 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9714 22:16:04.152613 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9715 22:16:04.158745 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9716 22:16:04.162570 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9717 22:16:04.165943 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9718 22:16:04.172668 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9719 22:16:04.175714 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9720 22:16:04.182265 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9721 22:16:04.185553 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9722 22:16:04.191936 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9723 22:16:04.195336 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9724 22:16:04.199282 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9725 22:16:04.205580 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9726 22:16:04.208898 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9727 22:16:04.215267 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9728 22:16:04.218885 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9729 22:16:04.222424 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9730 22:16:04.228422 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9731 22:16:04.231570 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9732 22:16:04.238799 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9733 22:16:04.241404 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9734 22:16:04.248335 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9735 22:16:04.251351 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9736 22:16:04.254894 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9737 22:16:04.261533 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9738 22:16:04.264865 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9739 22:16:04.271317 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9740 22:16:04.275464 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9741 22:16:04.278541 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9742 22:16:04.284907 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9743 22:16:04.288753 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9744 22:16:04.294546 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9745 22:16:04.298051 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9746 22:16:04.304555 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9747 22:16:04.308050 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9748 22:16:04.311444 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9749 22:16:04.314500 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9750 22:16:04.321680 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9751 22:16:04.324595 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9752 22:16:04.328086 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9753 22:16:04.334731 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9754 22:16:04.337743 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9755 22:16:04.341314 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9756 22:16:04.348057 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9757 22:16:04.350816 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9758 22:16:04.354484 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9759 22:16:04.360867 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9760 22:16:04.364399 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9761 22:16:04.370776 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9762 22:16:04.373671 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9763 22:16:04.377375 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9764 22:16:04.383545 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9765 22:16:04.387152 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9766 22:16:04.393672 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9767 22:16:04.397382 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9768 22:16:04.400477 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9769 22:16:04.406511 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9770 22:16:04.410242 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9771 22:16:04.413425 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9772 22:16:04.420675 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9773 22:16:04.423350 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9774 22:16:04.426507 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9775 22:16:04.434199 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9776 22:16:04.437087 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9777 22:16:04.440190 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9778 22:16:04.446948 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9779 22:16:04.450093 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9780 22:16:04.456797 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9781 22:16:04.459779 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9782 22:16:04.463244 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9783 22:16:04.469679 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9784 22:16:04.473348 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9785 22:16:04.480014 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9786 22:16:04.482934 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9787 22:16:04.486328 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9788 22:16:04.489417 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9789 22:16:04.496091 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9790 22:16:04.500561 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9791 22:16:04.502423 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9792 22:16:04.505769 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9793 22:16:04.512721 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9794 22:16:04.515711 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9795 22:16:04.519314 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9796 22:16:04.522445 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9797 22:16:04.529248 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9798 22:16:04.533007 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9799 22:16:04.535952 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9800 22:16:04.539309 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9801 22:16:04.545917 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9802 22:16:04.549029 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9803 22:16:04.555654 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9804 22:16:04.558804 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9805 22:16:04.565578 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9806 22:16:04.568732 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9807 22:16:04.575261 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9808 22:16:04.578752 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9809 22:16:04.581665 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9810 22:16:04.588156 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9811 22:16:04.592104 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9812 22:16:04.598117 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9813 22:16:04.601622 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9814 22:16:04.608839 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9815 22:16:04.611275 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9816 22:16:04.615043 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9817 22:16:04.621357 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9818 22:16:04.624556 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9819 22:16:04.631277 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9820 22:16:04.635304 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9821 22:16:04.637858 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9822 22:16:04.644622 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9823 22:16:04.647459 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9824 22:16:04.654538 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9825 22:16:04.657717 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9826 22:16:04.660844 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9827 22:16:04.667525 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9828 22:16:04.670960 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9829 22:16:04.677689 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9830 22:16:04.681258 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9831 22:16:04.687320 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9832 22:16:04.690451 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9833 22:16:04.693978 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9834 22:16:04.701140 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9835 22:16:04.704166 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9836 22:16:04.710464 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9837 22:16:04.713714 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9838 22:16:04.720373 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9839 22:16:04.723461 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9840 22:16:04.726712 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9841 22:16:04.733691 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9842 22:16:04.736742 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9843 22:16:04.743581 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9844 22:16:04.747189 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9845 22:16:04.750154 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9846 22:16:04.756646 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9847 22:16:04.760074 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9848 22:16:04.767099 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9849 22:16:04.770252 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9850 22:16:04.773577 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9851 22:16:04.779901 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9852 22:16:04.783235 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9853 22:16:04.789492 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9854 22:16:04.792778 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9855 22:16:04.799849 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9856 22:16:04.803130 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9857 22:16:04.806322 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9858 22:16:04.813234 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9859 22:16:04.816427 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9860 22:16:04.822879 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9861 22:16:04.826513 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9862 22:16:04.829635 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9863 22:16:04.836003 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9864 22:16:04.839227 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9865 22:16:04.846237 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9866 22:16:04.849453 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9867 22:16:04.853267 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9868 22:16:04.859358 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9869 22:16:04.862827 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9870 22:16:04.869468 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9871 22:16:04.872908 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9872 22:16:04.876170 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9873 22:16:04.882594 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9874 22:16:04.886510 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9875 22:16:04.892409 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9876 22:16:04.896119 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9877 22:16:04.902424 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9878 22:16:04.905464 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9879 22:16:04.912116 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9880 22:16:04.915348 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9881 22:16:04.918647 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9882 22:16:04.925509 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9883 22:16:04.928928 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9884 22:16:04.935377 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9885 22:16:04.938469 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9886 22:16:04.945442 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9887 22:16:04.948355 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9888 22:16:04.955271 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9889 22:16:04.958573 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9890 22:16:04.962019 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9891 22:16:04.968585 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9892 22:16:04.971696 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9893 22:16:04.978408 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9894 22:16:04.981597 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9895 22:16:04.988241 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9896 22:16:04.991337 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9897 22:16:04.998079 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9898 22:16:05.001391 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9899 22:16:05.004417 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9900 22:16:05.011048 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9901 22:16:05.014820 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9902 22:16:05.020898 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9903 22:16:05.024640 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9904 22:16:05.030750 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9905 22:16:05.034181 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9906 22:16:05.041071 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9907 22:16:05.044171 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9908 22:16:05.047338 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9909 22:16:05.054465 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9910 22:16:05.057470 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9911 22:16:05.064086 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9912 22:16:05.067744 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9913 22:16:05.075261 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9914 22:16:05.077367 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9915 22:16:05.080653 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9916 22:16:05.087361 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9917 22:16:05.090196 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9918 22:16:05.097065 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9919 22:16:05.100616 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9920 22:16:05.107511 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9921 22:16:05.110779 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9922 22:16:05.113760 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9923 22:16:05.120126 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9924 22:16:05.123821 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9925 22:16:05.130693 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9926 22:16:05.133405 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9927 22:16:05.140063 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9928 22:16:05.143342 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9929 22:16:05.149821 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9930 22:16:05.153137 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9931 22:16:05.160112 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9932 22:16:05.163554 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9933 22:16:05.170044 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9934 22:16:05.173244 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9935 22:16:05.179998 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9936 22:16:05.183245 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9937 22:16:05.190150 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9938 22:16:05.193143 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9939 22:16:05.199665 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9940 22:16:05.203306 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9941 22:16:05.210049 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9942 22:16:05.212722 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9943 22:16:05.219068 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9944 22:16:05.222573 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9945 22:16:05.229138 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9946 22:16:05.232622 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9947 22:16:05.239127 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9948 22:16:05.242540 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9949 22:16:05.249402 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9950 22:16:05.253336 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9951 22:16:05.258952 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9952 22:16:05.262701 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9953 22:16:05.265858 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9954 22:16:05.269365 INFO: [APUAPC] vio 0
9955 22:16:05.275896 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9956 22:16:05.278686 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9957 22:16:05.282443 INFO: [APUAPC] D0_APC_0: 0x400510
9958 22:16:05.285622 INFO: [APUAPC] D0_APC_1: 0x0
9959 22:16:05.288786 INFO: [APUAPC] D0_APC_2: 0x1540
9960 22:16:05.292817 INFO: [APUAPC] D0_APC_3: 0x0
9961 22:16:05.295712 INFO: [APUAPC] D1_APC_0: 0xffffffff
9962 22:16:05.299117 INFO: [APUAPC] D1_APC_1: 0xffffffff
9963 22:16:05.301923 INFO: [APUAPC] D1_APC_2: 0x3fffff
9964 22:16:05.305419 INFO: [APUAPC] D1_APC_3: 0x0
9965 22:16:05.309808 INFO: [APUAPC] D2_APC_0: 0xffffffff
9966 22:16:05.312375 INFO: [APUAPC] D2_APC_1: 0xffffffff
9967 22:16:05.315440 INFO: [APUAPC] D2_APC_2: 0x3fffff
9968 22:16:05.319059 INFO: [APUAPC] D2_APC_3: 0x0
9969 22:16:05.321955 INFO: [APUAPC] D3_APC_0: 0xffffffff
9970 22:16:05.325058 INFO: [APUAPC] D3_APC_1: 0xffffffff
9971 22:16:05.328503 INFO: [APUAPC] D3_APC_2: 0x3fffff
9972 22:16:05.332043 INFO: [APUAPC] D3_APC_3: 0x0
9973 22:16:05.334875 INFO: [APUAPC] D4_APC_0: 0xffffffff
9974 22:16:05.338081 INFO: [APUAPC] D4_APC_1: 0xffffffff
9975 22:16:05.341631 INFO: [APUAPC] D4_APC_2: 0x3fffff
9976 22:16:05.345257 INFO: [APUAPC] D4_APC_3: 0x0
9977 22:16:05.348408 INFO: [APUAPC] D5_APC_0: 0xffffffff
9978 22:16:05.351753 INFO: [APUAPC] D5_APC_1: 0xffffffff
9979 22:16:05.354378 INFO: [APUAPC] D5_APC_2: 0x3fffff
9980 22:16:05.355003 INFO: [APUAPC] D5_APC_3: 0x0
9981 22:16:05.361109 INFO: [APUAPC] D6_APC_0: 0xffffffff
9982 22:16:05.364852 INFO: [APUAPC] D6_APC_1: 0xffffffff
9983 22:16:05.367942 INFO: [APUAPC] D6_APC_2: 0x3fffff
9984 22:16:05.368510 INFO: [APUAPC] D6_APC_3: 0x0
9985 22:16:05.371138 INFO: [APUAPC] D7_APC_0: 0xffffffff
9986 22:16:05.374443 INFO: [APUAPC] D7_APC_1: 0xffffffff
9987 22:16:05.378186 INFO: [APUAPC] D7_APC_2: 0x3fffff
9988 22:16:05.381882 INFO: [APUAPC] D7_APC_3: 0x0
9989 22:16:05.384769 INFO: [APUAPC] D8_APC_0: 0xffffffff
9990 22:16:05.387600 INFO: [APUAPC] D8_APC_1: 0xffffffff
9991 22:16:05.390920 INFO: [APUAPC] D8_APC_2: 0x3fffff
9992 22:16:05.395518 INFO: [APUAPC] D8_APC_3: 0x0
9993 22:16:05.398314 INFO: [APUAPC] D9_APC_0: 0xffffffff
9994 22:16:05.400908 INFO: [APUAPC] D9_APC_1: 0xffffffff
9995 22:16:05.404341 INFO: [APUAPC] D9_APC_2: 0x3fffff
9996 22:16:05.408297 INFO: [APUAPC] D9_APC_3: 0x0
9997 22:16:05.410751 INFO: [APUAPC] D10_APC_0: 0xffffffff
9998 22:16:05.414202 INFO: [APUAPC] D10_APC_1: 0xffffffff
9999 22:16:05.417488 INFO: [APUAPC] D10_APC_2: 0x3fffff
10000 22:16:05.420996 INFO: [APUAPC] D10_APC_3: 0x0
10001 22:16:05.424100 INFO: [APUAPC] D11_APC_0: 0xffffffff
10002 22:16:05.427173 INFO: [APUAPC] D11_APC_1: 0xffffffff
10003 22:16:05.430820 INFO: [APUAPC] D11_APC_2: 0x3fffff
10004 22:16:05.433965 INFO: [APUAPC] D11_APC_3: 0x0
10005 22:16:05.437167 INFO: [APUAPC] D12_APC_0: 0xffffffff
10006 22:16:05.440704 INFO: [APUAPC] D12_APC_1: 0xffffffff
10007 22:16:05.443962 INFO: [APUAPC] D12_APC_2: 0x3fffff
10008 22:16:05.447406 INFO: [APUAPC] D12_APC_3: 0x0
10009 22:16:05.450927 INFO: [APUAPC] D13_APC_0: 0xffffffff
10010 22:16:05.454176 INFO: [APUAPC] D13_APC_1: 0xffffffff
10011 22:16:05.457101 INFO: [APUAPC] D13_APC_2: 0x3fffff
10012 22:16:05.460864 INFO: [APUAPC] D13_APC_3: 0x0
10013 22:16:05.463602 INFO: [APUAPC] D14_APC_0: 0xffffffff
10014 22:16:05.467271 INFO: [APUAPC] D14_APC_1: 0xffffffff
10015 22:16:05.474088 INFO: [APUAPC] D14_APC_2: 0x3fffff
10016 22:16:05.474610 INFO: [APUAPC] D14_APC_3: 0x0
10017 22:16:05.476864 INFO: [APUAPC] D15_APC_0: 0xffffffff
10018 22:16:05.483833 INFO: [APUAPC] D15_APC_1: 0xffffffff
10019 22:16:05.487464 INFO: [APUAPC] D15_APC_2: 0x3fffff
10020 22:16:05.488044 INFO: [APUAPC] D15_APC_3: 0x0
10021 22:16:05.490019 INFO: [APUAPC] APC_CON: 0x4
10022 22:16:05.493387 INFO: [NOCDAPC] D0_APC_0: 0x0
10023 22:16:05.496655 INFO: [NOCDAPC] D0_APC_1: 0x0
10024 22:16:05.500391 INFO: [NOCDAPC] D1_APC_0: 0x0
10025 22:16:05.503870 INFO: [NOCDAPC] D1_APC_1: 0xfff
10026 22:16:05.506758 INFO: [NOCDAPC] D2_APC_0: 0x0
10027 22:16:05.510402 INFO: [NOCDAPC] D2_APC_1: 0xfff
10028 22:16:05.513534 INFO: [NOCDAPC] D3_APC_0: 0x0
10029 22:16:05.516313 INFO: [NOCDAPC] D3_APC_1: 0xfff
10030 22:16:05.516789 INFO: [NOCDAPC] D4_APC_0: 0x0
10031 22:16:05.520015 INFO: [NOCDAPC] D4_APC_1: 0xfff
10032 22:16:05.523408 INFO: [NOCDAPC] D5_APC_0: 0x0
10033 22:16:05.526741 INFO: [NOCDAPC] D5_APC_1: 0xfff
10034 22:16:05.529708 INFO: [NOCDAPC] D6_APC_0: 0x0
10035 22:16:05.532973 INFO: [NOCDAPC] D6_APC_1: 0xfff
10036 22:16:05.536221 INFO: [NOCDAPC] D7_APC_0: 0x0
10037 22:16:05.539594 INFO: [NOCDAPC] D7_APC_1: 0xfff
10038 22:16:05.542980 INFO: [NOCDAPC] D8_APC_0: 0x0
10039 22:16:05.546752 INFO: [NOCDAPC] D8_APC_1: 0xfff
10040 22:16:05.549517 INFO: [NOCDAPC] D9_APC_0: 0x0
10041 22:16:05.552705 INFO: [NOCDAPC] D9_APC_1: 0xfff
10042 22:16:05.553185 INFO: [NOCDAPC] D10_APC_0: 0x0
10043 22:16:05.555999 INFO: [NOCDAPC] D10_APC_1: 0xfff
10044 22:16:05.559295 INFO: [NOCDAPC] D11_APC_0: 0x0
10045 22:16:05.562726 INFO: [NOCDAPC] D11_APC_1: 0xfff
10046 22:16:05.566163 INFO: [NOCDAPC] D12_APC_0: 0x0
10047 22:16:05.569684 INFO: [NOCDAPC] D12_APC_1: 0xfff
10048 22:16:05.572430 INFO: [NOCDAPC] D13_APC_0: 0x0
10049 22:16:05.577250 INFO: [NOCDAPC] D13_APC_1: 0xfff
10050 22:16:05.579293 INFO: [NOCDAPC] D14_APC_0: 0x0
10051 22:16:05.582748 INFO: [NOCDAPC] D14_APC_1: 0xfff
10052 22:16:05.585899 INFO: [NOCDAPC] D15_APC_0: 0x0
10053 22:16:05.589792 INFO: [NOCDAPC] D15_APC_1: 0xfff
10054 22:16:05.592691 INFO: [NOCDAPC] APC_CON: 0x4
10055 22:16:05.595662 INFO: [APUAPC] set_apusys_apc done
10056 22:16:05.599727 INFO: [DEVAPC] devapc_init done
10057 22:16:05.602718 INFO: GICv3 without legacy support detected.
10058 22:16:05.606248 INFO: ARM GICv3 driver initialized in EL3
10059 22:16:05.609205 INFO: Maximum SPI INTID supported: 639
10060 22:16:05.612575 INFO: BL31: Initializing runtime services
10061 22:16:05.619037 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10062 22:16:05.622471 INFO: SPM: enable CPC mode
10063 22:16:05.629163 INFO: mcdi ready for mcusys-off-idle and system suspend
10064 22:16:05.632110 INFO: BL31: Preparing for EL3 exit to normal world
10065 22:16:05.635594 INFO: Entry point address = 0x80000000
10066 22:16:05.639271 INFO: SPSR = 0x8
10067 22:16:05.643926
10068 22:16:05.644503
10069 22:16:05.644883
10070 22:16:05.646924 Starting depthcharge on Spherion...
10071 22:16:05.647404
10072 22:16:05.647779 Wipe memory regions:
10073 22:16:05.648134
10074 22:16:05.650518 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10075 22:16:05.651084 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10076 22:16:05.651589 Setting prompt string to ['asurada:']
10077 22:16:05.652213 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10078 22:16:05.652960 [0x00000040000000, 0x00000054600000)
10079 22:16:05.772401
10080 22:16:05.773022 [0x00000054660000, 0x00000080000000)
10081 22:16:06.033141
10082 22:16:06.033720 [0x000000821a7280, 0x000000ffe64000)
10083 22:16:06.778391
10084 22:16:06.778981 [0x00000100000000, 0x00000240000000)
10085 22:16:08.668381
10086 22:16:08.671432 Initializing XHCI USB controller at 0x11200000.
10087 22:16:09.709174
10088 22:16:09.712429 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10089 22:16:09.713012
10090 22:16:09.713390
10091 22:16:09.713743
10092 22:16:09.714598 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10094 22:16:09.816237 asurada: tftpboot 192.168.201.1 10583896/tftp-deploy-406nn8fa/kernel/image.itb 10583896/tftp-deploy-406nn8fa/kernel/cmdline
10095 22:16:09.816917 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10096 22:16:09.817404 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10097 22:16:09.821624 tftpboot 192.168.201.1 10583896/tftp-deploy-406nn8fa/kernel/image.itp-deploy-406nn8fa/kernel/cmdline
10098 22:16:09.821705
10099 22:16:09.821770 Waiting for link
10100 22:16:09.982667
10101 22:16:09.983260 R8152: Initializing
10102 22:16:09.983644
10103 22:16:09.985658 Version 9 (ocp_data = 6010)
10104 22:16:09.986132
10105 22:16:09.989072 R8152: Done initializing
10106 22:16:09.989654
10107 22:16:09.990033 Adding net device
10108 22:16:11.857842
10109 22:16:11.858701 done.
10110 22:16:11.859101
10111 22:16:11.859454 MAC: 00:e0:4c:72:2d:d6
10112 22:16:11.859799
10113 22:16:11.861124 Sending DHCP discover... done.
10114 22:16:11.861599
10115 22:16:11.863456 Waiting for reply... done.
10116 22:16:11.864075
10117 22:16:11.866851 Sending DHCP request... done.
10118 22:16:11.867349
10119 22:16:11.870271 Waiting for reply... done.
10120 22:16:11.870949
10121 22:16:11.871335 My ip is 192.168.201.21
10122 22:16:11.871682
10123 22:16:11.873549 The DHCP server ip is 192.168.201.1
10124 22:16:11.874029
10125 22:16:11.880116 TFTP server IP predefined by user: 192.168.201.1
10126 22:16:11.880699
10127 22:16:11.886874 Bootfile predefined by user: 10583896/tftp-deploy-406nn8fa/kernel/image.itb
10128 22:16:11.887457
10129 22:16:11.887833 Sending tftp read request... done.
10130 22:16:11.890218
10131 22:16:11.894314 Waiting for the transfer...
10132 22:16:11.894898
10133 22:16:12.270233 00000000 ################################################################
10134 22:16:12.270433
10135 22:16:12.568151 00080000 ################################################################
10136 22:16:12.568297
10137 22:16:12.869111 00100000 ################################################################
10138 22:16:12.869243
10139 22:16:13.165378 00180000 ################################################################
10140 22:16:13.165514
10141 22:16:13.457079 00200000 ################################################################
10142 22:16:13.457212
10143 22:16:13.726928 00280000 ################################################################
10144 22:16:13.727062
10145 22:16:14.001424 00300000 ################################################################
10146 22:16:14.001567
10147 22:16:14.282585 00380000 ################################################################
10148 22:16:14.282722
10149 22:16:14.576152 00400000 ################################################################
10150 22:16:14.576284
10151 22:16:14.864584 00480000 ################################################################
10152 22:16:14.864721
10153 22:16:15.187789 00500000 ################################################################
10154 22:16:15.188312
10155 22:16:15.599560 00580000 ################################################################
10156 22:16:15.600078
10157 22:16:16.004487 00600000 ################################################################
10158 22:16:16.005145
10159 22:16:16.390329 00680000 ################################################################
10160 22:16:16.390874
10161 22:16:16.729161 00700000 ################################################################
10162 22:16:16.729302
10163 22:16:17.028384 00780000 ################################################################
10164 22:16:17.028526
10165 22:16:17.327280 00800000 ################################################################
10166 22:16:17.327421
10167 22:16:17.616363 00880000 ################################################################
10168 22:16:17.616499
10169 22:16:17.912622 00900000 ################################################################
10170 22:16:17.912756
10171 22:16:18.200274 00980000 ################################################################
10172 22:16:18.200424
10173 22:16:18.449852 00a00000 ################################################################
10174 22:16:18.449975
10175 22:16:18.710246 00a80000 ################################################################
10176 22:16:18.710404
10177 22:16:18.975389 00b00000 ################################################################
10178 22:16:18.975532
10179 22:16:19.255468 00b80000 ################################################################
10180 22:16:19.255605
10181 22:16:19.539418 00c00000 ################################################################
10182 22:16:19.539542
10183 22:16:19.829247 00c80000 ################################################################
10184 22:16:19.829377
10185 22:16:20.097251 00d00000 ################################################################
10186 22:16:20.097389
10187 22:16:20.393847 00d80000 ################################################################
10188 22:16:20.393983
10189 22:16:20.690079 00e00000 ################################################################
10190 22:16:20.690219
10191 22:16:20.981820 00e80000 ################################################################
10192 22:16:20.981950
10193 22:16:21.254024 00f00000 ################################################################
10194 22:16:21.254153
10195 22:16:21.503842 00f80000 ################################################################
10196 22:16:21.503969
10197 22:16:21.756281 01000000 ################################################################
10198 22:16:21.756407
10199 22:16:22.045613 01080000 ################################################################
10200 22:16:22.045751
10201 22:16:22.415426 01100000 ################################################################
10202 22:16:22.415991
10203 22:16:22.799737 01180000 ################################################################
10204 22:16:22.800300
10205 22:16:23.181370 01200000 ################################################################
10206 22:16:23.181903
10207 22:16:23.583512 01280000 ################################################################
10208 22:16:23.584108
10209 22:16:23.969039 01300000 ################################################################
10210 22:16:23.969557
10211 22:16:24.375697 01380000 ################################################################
10212 22:16:24.376266
10213 22:16:24.741494 01400000 ################################################################
10214 22:16:24.742051
10215 22:16:25.111415 01480000 ################################################################
10216 22:16:25.111920
10217 22:16:25.465607 01500000 ################################################################
10218 22:16:25.466118
10219 22:16:25.834931 01580000 ################################################################
10220 22:16:25.835496
10221 22:16:26.243518 01600000 ################################################################
10222 22:16:26.244084
10223 22:16:26.634272 01680000 ################################################################
10224 22:16:26.634824
10225 22:16:27.019156 01700000 ################################################################
10226 22:16:27.019703
10227 22:16:27.427378 01780000 ################################################################
10228 22:16:27.427897
10229 22:16:27.698260 01800000 ################################################################
10230 22:16:27.698403
10231 22:16:27.951502 01880000 ################################################################
10232 22:16:27.951644
10233 22:16:28.200983 01900000 ################################################################
10234 22:16:28.201116
10235 22:16:28.471457 01980000 ################################################################
10236 22:16:28.471589
10237 22:16:28.740252 01a00000 ############################################################### done.
10238 22:16:28.740387
10239 22:16:28.743501 The bootfile was 27775202 bytes long.
10240 22:16:28.743592
10241 22:16:28.746623 Sending tftp read request... done.
10242 22:16:28.746714
10243 22:16:28.750064 Waiting for the transfer...
10244 22:16:28.750245
10245 22:16:28.753339 00000000 # done.
10246 22:16:28.753529
10247 22:16:28.760592 Command line loaded dynamically from TFTP file: 10583896/tftp-deploy-406nn8fa/kernel/cmdline
10248 22:16:28.760792
10249 22:16:28.779796 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10583896/extract-nfsrootfs-cnr11rcj,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10250 22:16:28.780074
10251 22:16:28.780232 Loading FIT.
10252 22:16:28.780372
10253 22:16:28.783359 Image ramdisk-1 has 17644514 bytes.
10254 22:16:28.783655
10255 22:16:28.787019 Image fdt-1 has 46924 bytes.
10256 22:16:28.787315
10257 22:16:28.789757 Image kernel-1 has 10081729 bytes.
10258 22:16:28.790008
10259 22:16:28.800238 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10260 22:16:28.800753
10261 22:16:28.816124 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10262 22:16:28.816706
10263 22:16:28.823015 Choosing best match conf-1 for compat google,spherion-rev2.
10264 22:16:28.826245
10265 22:16:28.830573 Connected to device vid:did:rid of 1ae0:0028:00
10266 22:16:28.838047
10267 22:16:28.841617 tpm_get_response: command 0x17b, return code 0x0
10268 22:16:28.842189
10269 22:16:28.844604 ec_init: CrosEC protocol v3 supported (256, 248)
10270 22:16:28.848330
10271 22:16:28.851899 tpm_cleanup: add release locality here.
10272 22:16:28.852476
10273 22:16:28.852853 Shutting down all USB controllers.
10274 22:16:28.854908
10275 22:16:28.855384 Removing current net device
10276 22:16:28.855763
10277 22:16:28.861856 Exiting depthcharge with code 4 at timestamp: 52548769
10278 22:16:28.862458
10279 22:16:28.864653 LZMA decompressing kernel-1 to 0x821a6718
10280 22:16:28.865187
10281 22:16:28.868650 LZMA decompressing kernel-1 to 0x40000000
10282 22:16:30.135487
10283 22:16:30.136056 jumping to kernel
10284 22:16:30.137788 end: 2.2.4 bootloader-commands (duration 00:00:24) [common]
10285 22:16:30.138340 start: 2.2.5 auto-login-action (timeout 00:04:01) [common]
10286 22:16:30.138801 Setting prompt string to ['Linux version [0-9]']
10287 22:16:30.139250 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10288 22:16:30.139640 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10289 22:16:30.218761
10290 22:16:30.221516 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10291 22:16:30.225504 start: 2.2.5.1 login-action (timeout 00:04:01) [common]
10292 22:16:30.226100 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10293 22:16:30.226612 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10294 22:16:30.227029 Using line separator: #'\n'#
10295 22:16:30.227387 No login prompt set.
10296 22:16:30.227746 Parsing kernel messages
10297 22:16:30.228070 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10298 22:16:30.228633 [login-action] Waiting for messages, (timeout 00:04:01)
10299 22:16:30.243851 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j1606555-arm64-gcc-10-defconfig-arm64-chromebook-vtq55) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sun Jun 4 21:56:05 UTC 2023
10300 22:16:30.247325 [ 0.000000] random: crng init done
10301 22:16:30.254103 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10302 22:16:30.257801 [ 0.000000] efi: UEFI not found.
10303 22:16:30.264220 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10304 22:16:30.270452 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10305 22:16:30.280530 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10306 22:16:30.290927 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10307 22:16:30.297225 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10308 22:16:30.303876 [ 0.000000] printk: bootconsole [mtk8250] enabled
10309 22:16:30.310445 [ 0.000000] NUMA: No NUMA configuration found
10310 22:16:30.317071 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10311 22:16:30.320122 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcda00-0x23efcffff]
10312 22:16:30.323225 [ 0.000000] Zone ranges:
10313 22:16:30.330109 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10314 22:16:30.333741 [ 0.000000] DMA32 empty
10315 22:16:30.339956 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10316 22:16:30.342979 [ 0.000000] Movable zone start for each node
10317 22:16:30.346500 [ 0.000000] Early memory node ranges
10318 22:16:30.353211 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10319 22:16:30.360294 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10320 22:16:30.366983 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10321 22:16:30.373049 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10322 22:16:30.379856 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10323 22:16:30.386119 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10324 22:16:30.441986 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10325 22:16:30.448546 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10326 22:16:30.455429 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10327 22:16:30.458521 [ 0.000000] psci: probing for conduit method from DT.
10328 22:16:30.465335 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10329 22:16:30.468869 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10330 22:16:30.475346 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10331 22:16:30.478282 [ 0.000000] psci: SMC Calling Convention v1.2
10332 22:16:30.485624 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10333 22:16:30.488778 [ 0.000000] Detected VIPT I-cache on CPU0
10334 22:16:30.495281 [ 0.000000] CPU features: detected: GIC system register CPU interface
10335 22:16:30.501679 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10336 22:16:30.508166 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10337 22:16:30.515120 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10338 22:16:30.524853 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10339 22:16:30.531444 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10340 22:16:30.534721 [ 0.000000] alternatives: applying boot alternatives
10341 22:16:30.541038 [ 0.000000] Fallback order for Node 0: 0
10342 22:16:30.547281 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10343 22:16:30.551462 [ 0.000000] Policy zone: Normal
10344 22:16:30.570709 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10583896/extract-nfsrootfs-cnr11rcj,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10345 22:16:30.580462 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10346 22:16:30.592602 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10347 22:16:30.602544 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10348 22:16:30.608586 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10349 22:16:30.612120 <6>[ 0.000000] software IO TLB: area num 8.
10350 22:16:30.669527 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10351 22:16:30.818407 <6>[ 0.000000] Memory: 7955712K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 397056K reserved, 32768K cma-reserved)
10352 22:16:30.824757 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10353 22:16:30.831059 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10354 22:16:30.834652 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10355 22:16:30.841739 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10356 22:16:30.847886 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10357 22:16:30.851858 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10358 22:16:30.861204 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10359 22:16:30.867788 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10360 22:16:30.874269 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10361 22:16:30.881012 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10362 22:16:30.884006 <6>[ 0.000000] GICv3: 608 SPIs implemented
10363 22:16:30.887228 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10364 22:16:30.893889 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10365 22:16:30.897091 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10366 22:16:30.903893 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10367 22:16:30.917159 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10368 22:16:30.930009 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10369 22:16:30.936344 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10370 22:16:30.944771 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10371 22:16:30.957994 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10372 22:16:30.963919 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10373 22:16:30.971101 <6>[ 0.009182] Console: colour dummy device 80x25
10374 22:16:30.980942 <6>[ 0.013911] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10375 22:16:30.987465 <6>[ 0.024353] pid_max: default: 32768 minimum: 301
10376 22:16:30.990775 <6>[ 0.029228] LSM: Security Framework initializing
10377 22:16:30.997322 <6>[ 0.034166] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10378 22:16:31.007277 <6>[ 0.042027] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10379 22:16:31.017238 <6>[ 0.051452] cblist_init_generic: Setting adjustable number of callback queues.
10380 22:16:31.020524 <6>[ 0.058907] cblist_init_generic: Setting shift to 3 and lim to 1.
10381 22:16:31.026882 <6>[ 0.065244] cblist_init_generic: Setting shift to 3 and lim to 1.
10382 22:16:31.033959 <6>[ 0.071653] rcu: Hierarchical SRCU implementation.
10383 22:16:31.039935 <6>[ 0.076697] rcu: Max phase no-delay instances is 1000.
10384 22:16:31.043449 <6>[ 0.083753] EFI services will not be available.
10385 22:16:31.050641 <6>[ 0.088723] smp: Bringing up secondary CPUs ...
10386 22:16:31.057830 <6>[ 0.093777] Detected VIPT I-cache on CPU1
10387 22:16:31.064726 <6>[ 0.093852] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10388 22:16:31.070634 <6>[ 0.093881] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10389 22:16:31.074709 <6>[ 0.094219] Detected VIPT I-cache on CPU2
10390 22:16:31.085078 <6>[ 0.094268] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10391 22:16:31.090960 <6>[ 0.094284] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10392 22:16:31.094420 <6>[ 0.094541] Detected VIPT I-cache on CPU3
10393 22:16:31.100601 <6>[ 0.094588] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10394 22:16:31.107030 <6>[ 0.094602] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10395 22:16:31.110906 <6>[ 0.094906] CPU features: detected: Spectre-v4
10396 22:16:31.117420 <6>[ 0.094912] CPU features: detected: Spectre-BHB
10397 22:16:31.120197 <6>[ 0.094918] Detected PIPT I-cache on CPU4
10398 22:16:31.126815 <6>[ 0.094974] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10399 22:16:31.134253 <6>[ 0.094991] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10400 22:16:31.140039 <6>[ 0.095289] Detected PIPT I-cache on CPU5
10401 22:16:31.147015 <6>[ 0.095350] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10402 22:16:31.153809 <6>[ 0.095367] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10403 22:16:31.156990 <6>[ 0.095652] Detected PIPT I-cache on CPU6
10404 22:16:31.163519 <6>[ 0.095718] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10405 22:16:31.170453 <6>[ 0.095734] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10406 22:16:31.177039 <6>[ 0.096032] Detected PIPT I-cache on CPU7
10407 22:16:31.183143 <6>[ 0.096096] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10408 22:16:31.190110 <6>[ 0.096112] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10409 22:16:31.193182 <6>[ 0.096161] smp: Brought up 1 node, 8 CPUs
10410 22:16:31.200073 <6>[ 0.237462] SMP: Total of 8 processors activated.
10411 22:16:31.204193 <6>[ 0.242383] CPU features: detected: 32-bit EL0 Support
10412 22:16:31.213255 <6>[ 0.247776] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10413 22:16:31.219522 <6>[ 0.256628] CPU features: detected: Common not Private translations
10414 22:16:31.226807 <6>[ 0.263146] CPU features: detected: CRC32 instructions
10415 22:16:31.229991 <6>[ 0.268499] CPU features: detected: RCpc load-acquire (LDAPR)
10416 22:16:31.236137 <6>[ 0.274458] CPU features: detected: LSE atomic instructions
10417 22:16:31.243025 <6>[ 0.280275] CPU features: detected: Privileged Access Never
10418 22:16:31.249603 <6>[ 0.286062] CPU features: detected: RAS Extension Support
10419 22:16:31.256328 <6>[ 0.291672] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10420 22:16:31.259538 <6>[ 0.298891] CPU: All CPU(s) started at EL2
10421 22:16:31.265812 <6>[ 0.303207] alternatives: applying system-wide alternatives
10422 22:16:31.275648 <6>[ 0.313954] devtmpfs: initialized
10423 22:16:31.291210 <6>[ 0.322821] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10424 22:16:31.297867 <6>[ 0.332785] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10425 22:16:31.304149 <6>[ 0.341038] pinctrl core: initialized pinctrl subsystem
10426 22:16:31.307889 <6>[ 0.347677] DMI not present or invalid.
10427 22:16:31.314493 <6>[ 0.352100] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10428 22:16:31.324055 <6>[ 0.359000] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10429 22:16:31.331023 <6>[ 0.366590] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10430 22:16:31.340274 <6>[ 0.374820] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10431 22:16:31.346755 <6>[ 0.383071] audit: initializing netlink subsys (disabled)
10432 22:16:31.353468 <5>[ 0.388772] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10433 22:16:31.360478 <6>[ 0.389487] thermal_sys: Registered thermal governor 'step_wise'
10434 22:16:31.367223 <6>[ 0.396737] thermal_sys: Registered thermal governor 'power_allocator'
10435 22:16:31.369824 <6>[ 0.402994] cpuidle: using governor menu
10436 22:16:31.377123 <6>[ 0.413960] NET: Registered PF_QIPCRTR protocol family
10437 22:16:31.382955 <6>[ 0.419491] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10438 22:16:31.389870 <6>[ 0.426595] ASID allocator initialised with 32768 entries
10439 22:16:31.393197 <6>[ 0.433172] Serial: AMBA PL011 UART driver
10440 22:16:31.403274 <4>[ 0.441867] Trying to register duplicate clock ID: 134
10441 22:16:31.459728 <6>[ 0.501408] KASLR enabled
10442 22:16:31.474088 <6>[ 0.509166] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10443 22:16:31.481062 <6>[ 0.516180] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10444 22:16:31.487642 <6>[ 0.522671] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10445 22:16:31.493826 <6>[ 0.529677] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10446 22:16:31.500780 <6>[ 0.536164] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10447 22:16:31.507315 <6>[ 0.543171] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10448 22:16:31.514534 <6>[ 0.549658] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10449 22:16:31.520523 <6>[ 0.556665] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10450 22:16:31.523838 <6>[ 0.564186] ACPI: Interpreter disabled.
10451 22:16:31.532783 <6>[ 0.570574] iommu: Default domain type: Translated
10452 22:16:31.539046 <6>[ 0.575686] iommu: DMA domain TLB invalidation policy: strict mode
10453 22:16:31.542650 <5>[ 0.582345] SCSI subsystem initialized
10454 22:16:31.548399 <6>[ 0.586510] usbcore: registered new interface driver usbfs
10455 22:16:31.555705 <6>[ 0.592244] usbcore: registered new interface driver hub
10456 22:16:31.558458 <6>[ 0.597797] usbcore: registered new device driver usb
10457 22:16:31.565996 <6>[ 0.603879] pps_core: LinuxPPS API ver. 1 registered
10458 22:16:31.575299 <6>[ 0.609074] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10459 22:16:31.578708 <6>[ 0.618423] PTP clock support registered
10460 22:16:31.581788 <6>[ 0.622663] EDAC MC: Ver: 3.0.0
10461 22:16:31.589626 <6>[ 0.627807] FPGA manager framework
10462 22:16:31.595831 <6>[ 0.631487] Advanced Linux Sound Architecture Driver Initialized.
10463 22:16:31.599204 <6>[ 0.638264] vgaarb: loaded
10464 22:16:31.605734 <6>[ 0.641441] clocksource: Switched to clocksource arch_sys_counter
10465 22:16:31.609473 <5>[ 0.647875] VFS: Disk quotas dquot_6.6.0
10466 22:16:31.616321 <6>[ 0.652059] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10467 22:16:31.618797 <6>[ 0.659250] pnp: PnP ACPI: disabled
10468 22:16:31.627550 <6>[ 0.666001] NET: Registered PF_INET protocol family
10469 22:16:31.637801 <6>[ 0.671583] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10470 22:16:31.648546 <6>[ 0.683882] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10471 22:16:31.658879 <6>[ 0.692695] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10472 22:16:31.665111 <6>[ 0.700667] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10473 22:16:31.675398 <6>[ 0.709369] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10474 22:16:31.681599 <6>[ 0.719123] TCP: Hash tables configured (established 65536 bind 65536)
10475 22:16:31.688261 <6>[ 0.725979] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10476 22:16:31.697740 <6>[ 0.733181] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10477 22:16:31.704803 <6>[ 0.740881] NET: Registered PF_UNIX/PF_LOCAL protocol family
10478 22:16:31.711213 <6>[ 0.747058] RPC: Registered named UNIX socket transport module.
10479 22:16:31.714605 <6>[ 0.753215] RPC: Registered udp transport module.
10480 22:16:31.721051 <6>[ 0.758149] RPC: Registered tcp transport module.
10481 22:16:31.728183 <6>[ 0.763080] RPC: Registered tcp NFSv4.1 backchannel transport module.
10482 22:16:31.730650 <6>[ 0.769750] PCI: CLS 0 bytes, default 64
10483 22:16:31.734150 <6>[ 0.774112] Unpacking initramfs...
10484 22:16:31.744379 <6>[ 0.778243] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10485 22:16:31.750962 <6>[ 0.786904] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10486 22:16:31.757359 <6>[ 0.795745] kvm [1]: IPA Size Limit: 40 bits
10487 22:16:31.760274 <6>[ 0.800272] kvm [1]: GICv3: no GICV resource entry
10488 22:16:31.767030 <6>[ 0.805299] kvm [1]: disabling GICv2 emulation
10489 22:16:31.774507 <6>[ 0.809985] kvm [1]: GIC system register CPU interface enabled
10490 22:16:31.777350 <6>[ 0.816145] kvm [1]: vgic interrupt IRQ18
10491 22:16:31.783622 <6>[ 0.820506] kvm [1]: VHE mode initialized successfully
10492 22:16:31.787089 <5>[ 0.826932] Initialise system trusted keyrings
10493 22:16:31.793462 <6>[ 0.831712] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10494 22:16:31.803130 <6>[ 0.841654] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10495 22:16:31.810128 <5>[ 0.848076] NFS: Registering the id_resolver key type
10496 22:16:31.813149 <5>[ 0.853385] Key type id_resolver registered
10497 22:16:31.819720 <5>[ 0.857801] Key type id_legacy registered
10498 22:16:31.826723 <6>[ 0.862077] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10499 22:16:31.833227 <6>[ 0.869001] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10500 22:16:31.839381 <6>[ 0.876726] 9p: Installing v9fs 9p2000 file system support
10501 22:16:31.876873 <5>[ 0.915224] Key type asymmetric registered
10502 22:16:31.880861 <5>[ 0.919557] Asymmetric key parser 'x509' registered
10503 22:16:31.890467 <6>[ 0.924697] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10504 22:16:31.893437 <6>[ 0.932313] io scheduler mq-deadline registered
10505 22:16:31.896671 <6>[ 0.937072] io scheduler kyber registered
10506 22:16:31.915801 <6>[ 0.954138] EINJ: ACPI disabled.
10507 22:16:31.948406 <4>[ 0.980056] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10508 22:16:31.957949 <4>[ 0.990662] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10509 22:16:31.973374 <6>[ 1.011569] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10510 22:16:31.981015 <6>[ 1.019888] printk: console [ttyS0] disabled
10511 22:16:32.009727 <6>[ 1.044560] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10512 22:16:32.016454 <6>[ 1.054040] printk: console [ttyS0] enabled
10513 22:16:32.019178 <6>[ 1.054040] printk: console [ttyS0] enabled
10514 22:16:32.026117 <6>[ 1.062933] printk: bootconsole [mtk8250] disabled
10515 22:16:32.028980 <6>[ 1.062933] printk: bootconsole [mtk8250] disabled
10516 22:16:32.036028 <6>[ 1.074255] SuperH (H)SCI(F) driver initialized
10517 22:16:32.039214 <6>[ 1.079513] msm_serial: driver initialized
10518 22:16:32.053967 <6>[ 1.088422] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10519 22:16:32.063276 <6>[ 1.096970] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10520 22:16:32.069765 <6>[ 1.105512] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10521 22:16:32.080064 <6>[ 1.114142] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10522 22:16:32.089583 <6>[ 1.122849] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10523 22:16:32.096507 <6>[ 1.131562] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10524 22:16:32.106451 <6>[ 1.140103] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10525 22:16:32.112884 <6>[ 1.148907] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10526 22:16:32.122563 <6>[ 1.157453] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10527 22:16:32.134682 <6>[ 1.172996] loop: module loaded
10528 22:16:32.141453 <6>[ 1.179031] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10529 22:16:32.164479 <4>[ 1.202518] mtk-pmic-keys: Failed to locate of_node [id: -1]
10530 22:16:32.172144 <6>[ 1.209399] megasas: 07.719.03.00-rc1
10531 22:16:32.180367 <6>[ 1.218992] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10532 22:16:32.190736 <6>[ 1.228835] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10533 22:16:32.207268 <6>[ 1.245517] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10534 22:16:32.268092 <6>[ 1.299832] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10535 22:16:32.510940 <6>[ 1.549300] Freeing initrd memory: 17228K
10536 22:16:32.521244 <6>[ 1.559667] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10537 22:16:32.532053 <6>[ 1.570516] tun: Universal TUN/TAP device driver, 1.6
10538 22:16:32.535178 <6>[ 1.576556] thunder_xcv, ver 1.0
10539 22:16:32.538428 <6>[ 1.580061] thunder_bgx, ver 1.0
10540 22:16:32.542605 <6>[ 1.583558] nicpf, ver 1.0
10541 22:16:32.552284 <6>[ 1.587554] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10542 22:16:32.556321 <6>[ 1.595029] hns3: Copyright (c) 2017 Huawei Corporation.
10543 22:16:32.562696 <6>[ 1.600616] hclge is initializing
10544 22:16:32.566154 <6>[ 1.604192] e1000: Intel(R) PRO/1000 Network Driver
10545 22:16:32.572487 <6>[ 1.609321] e1000: Copyright (c) 1999-2006 Intel Corporation.
10546 22:16:32.575931 <6>[ 1.615333] e1000e: Intel(R) PRO/1000 Network Driver
10547 22:16:32.582489 <6>[ 1.620549] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10548 22:16:32.588921 <6>[ 1.626737] igb: Intel(R) Gigabit Ethernet Network Driver
10549 22:16:32.596107 <6>[ 1.632386] igb: Copyright (c) 2007-2014 Intel Corporation.
10550 22:16:32.602278 <6>[ 1.638221] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10551 22:16:32.608724 <6>[ 1.644739] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10552 22:16:32.612039 <6>[ 1.651196] sky2: driver version 1.30
10553 22:16:32.618680 <6>[ 1.656180] VFIO - User Level meta-driver version: 0.3
10554 22:16:32.625972 <6>[ 1.664306] usbcore: registered new interface driver usb-storage
10555 22:16:32.632410 <6>[ 1.670757] usbcore: registered new device driver onboard-usb-hub
10556 22:16:32.641227 <6>[ 1.679820] mt6397-rtc mt6359-rtc: registered as rtc0
10557 22:16:32.651745 <6>[ 1.685288] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-04T22:16:45 UTC (1685917005)
10558 22:16:32.654808 <6>[ 1.694845] i2c_dev: i2c /dev entries driver
10559 22:16:32.671330 <6>[ 1.706529] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10560 22:16:32.678648 <6>[ 1.716724] sdhci: Secure Digital Host Controller Interface driver
10561 22:16:32.684631 <6>[ 1.723164] sdhci: Copyright(c) Pierre Ossman
10562 22:16:32.691454 <6>[ 1.728554] Synopsys Designware Multimedia Card Interface Driver
10563 22:16:32.694918 <6>[ 1.735129] mmc0: CQHCI version 5.10
10564 22:16:32.701879 <6>[ 1.735704] sdhci-pltfm: SDHCI platform and OF driver helper
10565 22:16:32.708114 <6>[ 1.746986] ledtrig-cpu: registered to indicate activity on CPUs
10566 22:16:32.719280 <6>[ 1.754325] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10567 22:16:32.722714 <6>[ 1.761703] usbcore: registered new interface driver usbhid
10568 22:16:32.729365 <6>[ 1.767530] usbhid: USB HID core driver
10569 22:16:32.735825 <6>[ 1.771766] spi_master spi0: will run message pump with realtime priority
10570 22:16:32.778279 <6>[ 1.810259] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10571 22:16:32.797067 <6>[ 1.825573] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10572 22:16:32.801044 <6>[ 1.839144] mmc0: Command Queue Engine enabled
10573 22:16:32.807375 <6>[ 1.843897] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10574 22:16:32.813958 <6>[ 1.850872] cros-ec-spi spi0.0: Chrome EC device registered
10575 22:16:32.817217 <6>[ 1.851253] mmcblk0: mmc0:0001 DA4128 116 GiB
10576 22:16:32.827100 <6>[ 1.865767] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10577 22:16:32.834263 <6>[ 1.873007] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10578 22:16:32.840802 <6>[ 1.878924] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10579 22:16:32.847516 <6>[ 1.884820] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10580 22:16:32.866250 <6>[ 1.901376] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10581 22:16:32.874342 <6>[ 1.912811] NET: Registered PF_PACKET protocol family
10582 22:16:32.877989 <6>[ 1.918286] 9pnet: Installing 9P2000 support
10583 22:16:32.884702 <5>[ 1.922864] Key type dns_resolver registered
10584 22:16:32.887748 <6>[ 1.927941] registered taskstats version 1
10585 22:16:32.894193 <5>[ 1.932345] Loading compiled-in X.509 certificates
10586 22:16:32.928329 <4>[ 1.959844] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10587 22:16:32.938408 <4>[ 1.970582] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10588 22:16:32.947867 <3>[ 1.983256] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10589 22:16:32.960062 <6>[ 1.998680] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10590 22:16:32.966979 <6>[ 2.005448] xhci-mtk 11200000.usb: xHCI Host Controller
10591 22:16:32.973890 <6>[ 2.010944] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10592 22:16:32.984278 <6>[ 2.018800] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10593 22:16:32.989960 <6>[ 2.028232] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10594 22:16:32.996782 <6>[ 2.034337] xhci-mtk 11200000.usb: xHCI Host Controller
10595 22:16:33.004079 <6>[ 2.039833] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10596 22:16:33.010040 <6>[ 2.047597] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10597 22:16:33.017213 <6>[ 2.055514] hub 1-0:1.0: USB hub found
10598 22:16:33.020399 <6>[ 2.059562] hub 1-0:1.0: 1 port detected
10599 22:16:33.031000 <6>[ 2.063919] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10600 22:16:33.033335 <6>[ 2.072737] hub 2-0:1.0: USB hub found
10601 22:16:33.036598 <6>[ 2.076786] hub 2-0:1.0: 1 port detected
10602 22:16:33.045109 <6>[ 2.083889] mtk-msdc 11f70000.mmc: Got CD GPIO
10603 22:16:33.061527 <6>[ 2.096900] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10604 22:16:33.068572 <6>[ 2.104936] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10605 22:16:33.078107 <4>[ 2.112912] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10606 22:16:33.088447 <6>[ 2.122579] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10607 22:16:33.094927 <6>[ 2.130661] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10608 22:16:33.101435 <6>[ 2.138688] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10609 22:16:33.111275 <6>[ 2.146602] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10610 22:16:33.117983 <6>[ 2.154424] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10611 22:16:33.127811 <6>[ 2.162251] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10612 22:16:33.137761 <6>[ 2.172998] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10613 22:16:33.144240 <6>[ 2.181368] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10614 22:16:33.154153 <6>[ 2.189733] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10615 22:16:33.164120 <6>[ 2.198077] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10616 22:16:33.170848 <6>[ 2.206421] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10617 22:16:33.180923 <6>[ 2.214763] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10618 22:16:33.187940 <6>[ 2.223107] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10619 22:16:33.197629 <6>[ 2.231449] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10620 22:16:33.204251 <6>[ 2.239793] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10621 22:16:33.214261 <6>[ 2.248140] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10622 22:16:33.221203 <6>[ 2.256483] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10623 22:16:33.230777 <6>[ 2.264826] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10624 22:16:33.236949 <6>[ 2.273169] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10625 22:16:33.247095 <6>[ 2.281513] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10626 22:16:33.253847 <6>[ 2.289859] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10627 22:16:33.260288 <6>[ 2.298777] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10628 22:16:33.267278 <6>[ 2.306211] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10629 22:16:33.274339 <6>[ 2.313240] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10630 22:16:33.284829 <6>[ 2.320345] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10631 22:16:33.291873 <6>[ 2.327614] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10632 22:16:33.301785 <6>[ 2.334520] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10633 22:16:33.308029 <6>[ 2.343660] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10634 22:16:33.319315 <6>[ 2.352787] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10635 22:16:33.328357 <6>[ 2.362089] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10636 22:16:33.338145 <6>[ 2.371566] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10637 22:16:33.348286 <6>[ 2.381040] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10638 22:16:33.354252 <6>[ 2.390167] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10639 22:16:33.364407 <6>[ 2.399648] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10640 22:16:33.374169 <6>[ 2.408777] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10641 22:16:33.384176 <6>[ 2.418091] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10642 22:16:33.394393 <6>[ 2.428257] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10643 22:16:33.404824 <6>[ 2.439742] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10644 22:16:33.410845 <6>[ 2.449693] Trying to probe devices needed for running init ...
10645 22:16:33.450395 <6>[ 2.485714] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10646 22:16:33.604395 <6>[ 2.643093] hub 1-1:1.0: USB hub found
10647 22:16:33.607653 <6>[ 2.647543] hub 1-1:1.0: 4 ports detected
10648 22:16:33.730754 <6>[ 2.765920] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10649 22:16:33.756047 <6>[ 2.794219] hub 2-1:1.0: USB hub found
10650 22:16:33.759129 <6>[ 2.798615] hub 2-1:1.0: 3 ports detected
10651 22:16:33.930270 <6>[ 2.965715] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10652 22:16:34.063304 <6>[ 3.101927] hub 1-1.4:1.0: USB hub found
10653 22:16:34.066620 <6>[ 3.106606] hub 1-1.4:1.0: 2 ports detected
10654 22:16:34.142515 <6>[ 3.177969] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10655 22:16:34.362263 <6>[ 3.397717] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10656 22:16:34.554315 <6>[ 3.589716] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10657 22:16:45.686992 <6>[ 14.730273] ALSA device list:
10658 22:16:45.693331 <6>[ 14.733530] No soundcards found.
10659 22:16:45.706427 <6>[ 14.745916] Freeing unused kernel memory: 8384K
10660 22:16:45.709352 <6>[ 14.750824] Run /init as init process
10661 22:16:45.719908 Loading, please wait...
10662 22:16:45.738927 Starting version 247.3-7+deb11u2
10663 22:16:46.058878 <6>[ 15.095980] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10664 22:16:46.068952 <6>[ 15.108547] remoteproc remoteproc0: scp is available
10665 22:16:46.078515 <4>[ 15.114363] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10666 22:16:46.085829 <6>[ 15.124218] remoteproc remoteproc0: powering up scp
10667 22:16:46.095763 <4>[ 15.129843] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10668 22:16:46.101853 <3>[ 15.139693] remoteproc remoteproc0: request_firmware failed: -2
10669 22:16:46.107918 <6>[ 15.140981] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10670 22:16:46.118068 <3>[ 15.146867] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10671 22:16:46.124810 <6>[ 15.153532] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10672 22:16:46.131333 <6>[ 15.154427] usbcore: registered new interface driver r8152
10673 22:16:46.138099 <3>[ 15.161669] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10674 22:16:46.144611 <6>[ 15.162083] mc: Linux media interface: v0.10
10675 22:16:46.151342 <6>[ 15.170292] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10676 22:16:46.160929 <3>[ 15.176103] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10677 22:16:46.167561 <6>[ 15.176780] videodev: Linux video capture interface: v2.00
10678 22:16:46.170998 <6>[ 15.185012] usbcore: registered new interface driver cdc_ether
10679 22:16:46.180955 <4>[ 15.185315] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10680 22:16:46.187684 <4>[ 15.185471] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10681 22:16:46.194184 <3>[ 15.200503] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10682 22:16:46.204368 <3>[ 15.240086] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10683 22:16:46.210725 <6>[ 15.243083] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10684 22:16:46.217139 <6>[ 15.244692] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10685 22:16:46.226737 <3>[ 15.248318] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10686 22:16:46.233447 <4>[ 15.267349] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10687 22:16:46.240583 <4>[ 15.267349] Fallback method does not support PEC.
10688 22:16:46.247323 <3>[ 15.271198] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10689 22:16:46.256837 <4>[ 15.276454] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10690 22:16:46.263952 <4>[ 15.276465] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10691 22:16:46.270726 <3>[ 15.289654] elants_i2c 4-0010: invalid 'hello' packet: ff ff ff ff
10692 22:16:46.280328 <3>[ 15.292792] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10693 22:16:46.287366 <6>[ 15.306943] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10694 22:16:46.293890 <3>[ 15.309959] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10695 22:16:46.304455 <3>[ 15.310477] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10696 22:16:46.307353 <6>[ 15.316341] pci_bus 0000:00: root bus resource [bus 00-ff]
10697 22:16:46.317058 <3>[ 15.324463] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10698 22:16:46.320741 <6>[ 15.325625] r8152 2-1.3:1.0 eth0: v1.12.13
10699 22:16:46.327234 <6>[ 15.331285] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10700 22:16:46.337600 <3>[ 15.333384] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10701 22:16:46.343807 <3>[ 15.339364] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10702 22:16:46.353913 <6>[ 15.348137] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10703 22:16:46.363761 <3>[ 15.353870] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10704 22:16:46.370381 <6>[ 15.361975] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10705 22:16:46.379693 <6>[ 15.362140] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10706 22:16:46.389952 <6>[ 15.362493] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10707 22:16:46.396884 <3>[ 15.366344] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10708 22:16:46.403428 <6>[ 15.373438] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10709 22:16:46.413182 <3>[ 15.382202] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10710 22:16:46.419885 <3>[ 15.382209] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10711 22:16:46.429278 <3>[ 15.382217] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10712 22:16:46.436201 <3>[ 15.382223] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10713 22:16:46.446099 <3>[ 15.382250] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10714 22:16:46.452936 <3>[ 15.409607] elants_i2c 4-0010: invalid 'hello' packet: ff ff ff ff
10715 22:16:46.456128 <6>[ 15.414760] pci 0000:00:00.0: supports D1 D2
10716 22:16:46.462707 <6>[ 15.500750] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10717 22:16:46.472657 <6>[ 15.509504] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10718 22:16:46.479254 <6>[ 15.517868] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10719 22:16:46.485705 <6>[ 15.524162] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10720 22:16:46.492607 <3>[ 15.525743] elants_i2c 4-0010: invalid 'hello' packet: ff ff ff ff
10721 22:16:46.499496 <6>[ 15.531654] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10722 22:16:46.508919 <3>[ 15.538414] elants_i2c 4-0010: (read fw id) unexpected response: ff ff
10723 22:16:46.515195 <6>[ 15.545562] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10724 22:16:46.518451 <6>[ 15.545677] pci 0000:01:00.0: supports D1 D2
10725 22:16:46.528702 <6>[ 15.552462] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10726 22:16:46.535187 <6>[ 15.559822] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10727 22:16:46.542246 <6>[ 15.569807] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10728 22:16:46.551700 <6>[ 15.587584] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10729 22:16:46.555300 <6>[ 15.588736] Bluetooth: Core ver 2.22
10730 22:16:46.561652 <6>[ 15.588766] usbcore: registered new interface driver r8153_ecm
10731 22:16:46.568196 <6>[ 15.595695] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10732 22:16:46.577882 <6>[ 15.595713] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10733 22:16:46.581726 <6>[ 15.598714] r8152 2-1.3:1.0 enx00e04c722dd6: renamed from eth0
10734 22:16:46.587783 <6>[ 15.599636] NET: Registered PF_BLUETOOTH protocol family
10735 22:16:46.594405 <6>[ 15.605648] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10736 22:16:46.605284 <6>[ 15.607039] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10737 22:16:46.614526 <6>[ 15.608305] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10738 22:16:46.621359 <6>[ 15.608450] usbcore: registered new interface driver uvcvideo
10739 22:16:46.628170 <6>[ 15.613635] Bluetooth: HCI device and connection manager initialized
10740 22:16:46.637471 <6>[ 15.621651] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10741 22:16:46.644169 <6>[ 15.622429] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10742 22:16:46.647663 <6>[ 15.627732] Bluetooth: HCI socket layer initialized
10743 22:16:46.654462 <6>[ 15.633295] pci 0000:00:00.0: PCI bridge to [bus 01]
10744 22:16:46.657757 <6>[ 15.641278] Bluetooth: L2CAP socket layer initialized
10745 22:16:46.667217 <6>[ 15.648316] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10746 22:16:46.670584 <6>[ 15.660739] Bluetooth: SCO socket layer initialized
10747 22:16:46.676988 <6>[ 15.666856] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10748 22:16:46.683611 <6>[ 15.717221] usbcore: registered new interface driver btusb
10749 22:16:46.693707 <4>[ 15.718026] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10750 22:16:46.700176 <3>[ 15.718036] Bluetooth: hci0: Failed to load firmware file (-2)
10751 22:16:46.706610 <3>[ 15.718040] Bluetooth: hci0: Failed to set up firmware (-2)
10752 22:16:46.716757 <4>[ 15.718044] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10753 22:16:46.723457 <6>[ 15.723826] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10754 22:16:46.729984 <6>[ 15.768011] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10755 22:16:46.767106 <5>[ 15.803444] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10756 22:16:46.785395 <5>[ 15.822003] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10757 22:16:46.792339 <4>[ 15.828881] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10758 22:16:46.798450 <6>[ 15.837774] cfg80211: failed to load regulatory.db
10759 22:16:46.843078 <6>[ 15.879958] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10760 22:16:46.849658 <6>[ 15.887503] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10761 22:16:46.874212 <6>[ 15.914197] mt7921e 0000:01:00.0: ASIC revision: 79610010
10762 22:16:46.979366 <4>[ 16.012945] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10763 22:16:46.983505 Begin: Loading essential drivers ... done.
10764 22:16:46.990022 Begin: Running /scripts/init-premount ... done.
10765 22:16:46.995775 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10766 22:16:47.002560 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10767 22:16:47.008992 Device /sys/class/net/enx00e04c722dd6 found
10768 22:16:47.009562 done.
10769 22:16:47.044473 IP-Config: enx00e04c722dd6 hardware address 00:e0:4c:72:2d:d6 mtu 1500 DHCP
10770 22:16:47.098699 <4>[ 16.131756] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10771 22:16:47.218228 <4>[ 16.251366] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10772 22:16:47.333650 <4>[ 16.367167] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10773 22:16:47.449803 <4>[ 16.483099] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10774 22:16:47.565644 <4>[ 16.598948] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10775 22:16:47.681118 <4>[ 16.714968] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10776 22:16:47.797049 <4>[ 16.830900] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10777 22:16:47.913085 <4>[ 16.946811] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10778 22:16:47.963560 <6>[ 17.004019] r8152 2-1.3:1.0 enx00e04c722dd6: carrier on
10779 22:16:48.029414 <4>[ 17.062863] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10780 22:16:48.136108 <3>[ 17.176768] mt7921e 0000:01:00.0: hardware init failed
10781 22:16:48.144983 IP-Config: no response after 2 secs - giving up
10782 22:16:48.180985 IP-Config: enx00e04c722dd6 hardware address 00:e0:4c:72:2d:d6 mtu 1500 DHCP
10783 22:16:48.184013 IP-Config: enx00e04c722dd6 complete (dhcp from 192.168.201.1):
10784 22:16:48.190707 address: 192.168.201.21 broadcast: 192.168.201.255 netmask: 255.255.255.0
10785 22:16:48.200723 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10786 22:16:48.207032 host : mt8192-asurada-spherion-r0-cbg-1
10787 22:16:48.213631 domain : lava-rack
10788 22:16:48.216787 rootserver: 192.168.201.1 rootpath:
10789 22:16:48.217253 filename :
10790 22:16:48.271211 done.
10791 22:16:48.279808 Begin: Running /scripts/nfs-bottom ... done.
10792 22:16:48.296648 Begin: Running /scripts/init-bottom ... done.
10793 22:16:49.418513 <6>[ 18.458989] NET: Registered PF_INET6 protocol family
10794 22:16:49.425405 <6>[ 18.465813] Segment Routing with IPv6
10795 22:16:49.428655 <6>[ 18.469800] In-situ OAM (IOAM) with IPv6
10796 22:16:49.548373 <30>[ 18.569306] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10797 22:16:49.551591 <30>[ 18.593043] systemd[1]: Detected architecture arm64.
10798 22:16:49.572311
10799 22:16:49.576104 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10800 22:16:49.576667
10801 22:16:49.591669 <30>[ 18.632355] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10802 22:16:50.132930 <30>[ 19.169987] systemd[1]: Queued start job for default target Graphical Interface.
10803 22:16:50.162577 <30>[ 19.202780] systemd[1]: Created slice system-getty.slice.
10804 22:16:50.169400 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10805 22:16:50.185950 <30>[ 19.226358] systemd[1]: Created slice system-modprobe.slice.
10806 22:16:50.192591 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10807 22:16:50.210198 <30>[ 19.250359] systemd[1]: Created slice system-serial\x2dgetty.slice.
10808 22:16:50.219719 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10809 22:16:50.234192 <30>[ 19.274686] systemd[1]: Created slice User and Session Slice.
10810 22:16:50.241427 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10811 22:16:50.261561 <30>[ 19.298290] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10812 22:16:50.270847 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10813 22:16:50.289050 <30>[ 19.326231] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10814 22:16:50.295851 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10815 22:16:50.316715 <30>[ 19.349834] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10816 22:16:50.322945 <30>[ 19.361864] systemd[1]: Reached target Local Encrypted Volumes.
10817 22:16:50.329137 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10818 22:16:50.345467 <30>[ 19.386117] systemd[1]: Reached target Paths.
10819 22:16:50.348883 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10820 22:16:50.365215 <30>[ 19.405753] systemd[1]: Reached target Remote File Systems.
10821 22:16:50.371957 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10822 22:16:50.385132 <30>[ 19.425739] systemd[1]: Reached target Slices.
10823 22:16:50.388487 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10824 22:16:50.404958 <30>[ 19.445757] systemd[1]: Reached target Swap.
10825 22:16:50.408705 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10826 22:16:50.429101 <30>[ 19.466063] systemd[1]: Listening on initctl Compatibility Named Pipe.
10827 22:16:50.435226 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10828 22:16:50.442048 <30>[ 19.481554] systemd[1]: Listening on Journal Audit Socket.
10829 22:16:50.448912 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10830 22:16:50.462651 <30>[ 19.502869] systemd[1]: Listening on Journal Socket (/dev/log).
10831 22:16:50.468813 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10832 22:16:50.486065 <30>[ 19.526533] systemd[1]: Listening on Journal Socket.
10833 22:16:50.492804 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10834 22:16:50.509716 <30>[ 19.547078] systemd[1]: Listening on Network Service Netlink Socket.
10835 22:16:50.516384 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10836 22:16:50.532211 <30>[ 19.572717] systemd[1]: Listening on udev Control Socket.
10837 22:16:50.539034 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10838 22:16:50.553619 <30>[ 19.593943] systemd[1]: Listening on udev Kernel Socket.
10839 22:16:50.559803 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10840 22:16:50.609475 <30>[ 19.650003] systemd[1]: Mounting Huge Pages File System...
10841 22:16:50.615777 Mounting [0;1;39mHuge Pages File System[0m...
10842 22:16:50.632093 <30>[ 19.672200] systemd[1]: Mounting POSIX Message Queue File System...
10843 22:16:50.638426 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10844 22:16:50.655565 <30>[ 19.696270] systemd[1]: Mounting Kernel Debug File System...
10845 22:16:50.662184 Mounting [0;1;39mKernel Debug File System[0m...
10846 22:16:50.680714 <30>[ 19.717911] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10847 22:16:50.699159 <30>[ 19.736440] systemd[1]: Starting Create list of static device nodes for the current kernel...
10848 22:16:50.705681 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10849 22:16:50.723548 <30>[ 19.764468] systemd[1]: Starting Load Kernel Module configfs...
10850 22:16:50.730451 Starting [0;1;39mLoad Kernel Module configfs[0m...
10851 22:16:50.747832 <30>[ 19.788551] systemd[1]: Starting Load Kernel Module drm...
10852 22:16:50.754281 Starting [0;1;39mLoad Kernel Module drm[0m...
10853 22:16:50.771536 <30>[ 19.812527] systemd[1]: Starting Load Kernel Module fuse...
10854 22:16:50.778410 Starting [0;1;39mLoad Kernel Module fuse[0m...
10855 22:16:50.807737 <6>[ 19.848739] fuse: init (API version 7.37)
10856 22:16:50.818155 <30>[ 19.849478] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10857 22:16:50.857845 <30>[ 19.898356] systemd[1]: Starting Journal Service...
10858 22:16:50.863912 Starting [0;1;39mJournal Service[0m...
10859 22:16:50.885345 <30>[ 19.926100] systemd[1]: Starting Load Kernel Modules...
10860 22:16:50.891977 Starting [0;1;39mLoad Kernel Modules[0m...
10861 22:16:50.952989 <30>[ 19.990436] systemd[1]: Starting Remount Root and Kernel File Systems...
10862 22:16:50.959677 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10863 22:16:50.976067 <30>[ 20.016912] systemd[1]: Starting Coldplug All udev Devices...
10864 22:16:50.982556 Starting [0;1;39mColdplug All udev Devices[0m...
10865 22:16:50.999913 <30>[ 20.041020] systemd[1]: Mounted Huge Pages File System.
10866 22:16:51.006575 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10867 22:16:51.019382 <3>[ 20.057057] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10868 22:16:51.025727 <30>[ 20.066733] systemd[1]: Mounted POSIX Message Queue File System.
10869 22:16:51.032241 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10870 22:16:51.050699 <3>[ 20.087700] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10871 22:16:51.057117 <30>[ 20.097112] systemd[1]: Mounted Kernel Debug File System.
10872 22:16:51.063486 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10873 22:16:51.081814 <30>[ 20.118612] systemd[1]: Finished Create list of static device nodes for the current kernel.
10874 22:16:51.095134 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes<3>[ 20.132758] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10875 22:16:51.098159 for the current kernel[0m.
10876 22:16:51.115029 <30>[ 20.154933] systemd[1]: modprobe@configfs.service: Succeeded.
10877 22:16:51.121200 <30>[ 20.161693] systemd[1]: Finished Load Kernel Module configfs.
10878 22:16:51.131360 <3>[ 20.163695] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10879 22:16:51.137467 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10880 22:16:51.154338 <30>[ 20.194968] systemd[1]: modprobe@drm.service: Succeeded.
10881 22:16:51.165338 <3>[ 20.199159] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10882 22:16:51.168292 <30>[ 20.201302] systemd[1]: Finished Load Kernel Module drm.
10883 22:16:51.174566 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10884 22:16:51.190922 <30>[ 20.230851] systemd[1]: modprobe@fuse.service: Succeeded.
10885 22:16:51.200737 <3>[ 20.232487] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10886 22:16:51.206864 <30>[ 20.237172] systemd[1]: Finished Load Kernel Module fuse.
10887 22:16:51.210574 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10888 22:16:51.226824 <30>[ 20.267115] systemd[1]: Finished Load Kernel Modules.
10889 22:16:51.236462 <3>[ 20.268972] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10890 22:16:51.242864 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10891 22:16:51.259329 <30>[ 20.299022] systemd[1]: Finished Remount Root and Kernel File Systems.
10892 22:16:51.269061 <3>[ 20.304272] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10893 22:16:51.275688 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10894 22:16:51.302403 <3>[ 20.339566] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10895 22:16:51.332512 <3>[ 20.369711] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10896 22:16:51.338986 <30>[ 20.369783] systemd[1]: Mounting FUSE Control File System...
10897 22:16:51.345170 Mounting [0;1;39mFUSE Control File System[0m...
10898 22:16:51.362090 <3>[ 20.399565] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10899 22:16:51.368652 <30>[ 20.400478] systemd[1]: Mounting Kernel Configuration File System...
10900 22:16:51.375219 Mounting [0;1;39mKernel Configuration File System[0m...
10901 22:16:51.391036 <3>[ 20.428567] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10902 22:16:51.406714 <30>[ 20.443181] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10903 22:16:51.415915 <30>[ 20.452196] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10904 22:16:51.425968 <3>[ 20.458234] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10905 22:16:51.429096 <30>[ 20.464499] systemd[1]: Starting Load/Save Random Seed...
10906 22:16:51.435760 Starting [0;1;39mLoad/Save Random Seed[0m...
10907 22:16:51.454194 <3>[ 20.491635] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10908 22:16:51.461045 <30>[ 20.492517] systemd[1]: Starting Apply Kernel Variables...
10909 22:16:51.464095 Starting [0;1;39mApply Kernel Variables[0m...
10910 22:16:51.485375 <3>[ 20.523139] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10911 22:16:51.495351 <3>[ 20.523836] power_supply sbs-5-000b: driver failed to report `cycle_count' property: -6
10912 22:16:51.498628 <30>[ 20.525063] systemd[1]: Starting Create System Users...
10913 22:16:51.505582 Starting [0;1;39mCreate System Users[0m...
10914 22:16:51.523139 <30>[ 20.563478] systemd[1]: Mounted FUSE Control File System.
10915 22:16:51.536640 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0<3>[ 20.574230] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10916 22:16:51.537234 m.
10917 22:16:51.552500 <3>[ 20.589914] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10918 22:16:51.569183 <4>[ 20.598738] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10919 22:16:51.575633 <30>[ 20.599263] systemd[1]: Mounted Kernel Configuration File System.
10920 22:16:51.583176 <3>[ 20.614387] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10921 22:16:51.590334 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10922 22:16:51.607104 <30>[ 20.647588] systemd[1]: Finished Load/Save Random Seed.
10923 22:16:51.614273 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10924 22:16:51.633362 <29>[ 20.670548] systemd[1]: systemd-udev-trigger.service: Main process exited, code=exited, status=1/FAILURE
10925 22:16:51.643852 <28>[ 20.680931] systemd[1]: systemd-udev-trigger.service: Failed with result 'exit-code'.
10926 22:16:51.651040 <27>[ 20.689756] systemd[1]: Failed to start Coldplug All udev Devices.
10927 22:16:51.657568 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10928 22:16:51.673694 See 'systemctl status systemd-udev-trigger.service' for details.
10929 22:16:51.690004 <30>[ 20.730183] systemd[1]: Started Journal Service.
10930 22:16:51.695845 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10931 22:16:51.711246 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10932 22:16:51.730498 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10933 22:16:51.765926 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10934 22:16:51.783066 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10935 22:16:51.821918 <46>[ 20.859848] systemd-journald[297]: Received client request to flush runtime journal.
10936 22:16:51.844712 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10937 22:16:51.860159 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10938 22:16:51.872961 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10939 22:16:51.912315 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10940 22:16:53.199861 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10941 22:16:53.240801 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10942 22:16:53.262281 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10943 22:16:53.285839 Starting [0;1;39mNetwork Service[0m...
10944 22:16:53.613939 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10945 22:16:53.633684 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10946 22:16:53.693265 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10947 22:16:53.869871 <6>[ 22.911148] remoteproc remoteproc0: powering up scp
10948 22:16:53.893944 <4>[ 22.931793] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10949 22:16:53.900390 <3>[ 22.941675] remoteproc remoteproc0: request_firmware failed: -2
10950 22:16:53.910294 <3>[ 22.947863] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
10951 22:16:54.016690 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10952 22:16:54.037849 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10953 22:16:54.057421 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10954 22:16:54.078580 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10955 22:16:54.096263 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10956 22:16:54.137358 Starting [0;1;39mNetwork Name Resolution[0m...
10957 22:16:54.162943 Starting [0;1;39mNetwork Time Synchronization[0m...
10958 22:16:54.179589 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10959 22:16:54.202080 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10960 22:16:54.232450 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10961 22:16:54.253287 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10962 22:16:54.417502 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10963 22:16:54.437453 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10964 22:16:54.455611 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10965 22:16:54.468153 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10966 22:16:54.483941 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10967 22:16:54.598053 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10968 22:16:54.640939 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10969 22:16:54.667362 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10970 22:16:54.957857 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10971 22:16:54.975927 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10972 22:16:55.226654 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10973 22:16:55.240269 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10974 22:16:55.256098 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10975 22:16:55.289008 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10976 22:16:55.441295 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10977 22:16:55.797370 Starting [0;1;39mUser Login Management[0m...
10978 22:16:55.813063 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10979 22:16:55.829840 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10980 22:16:55.847637 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10981 22:16:55.884419 Starting [0;1;39mPermit User Sessions[0m...
10982 22:16:55.986230 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10983 22:16:56.013575 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10984 22:16:56.060925 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10985 22:16:56.080062 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10986 22:16:56.100527 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10987 22:16:56.122002 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10988 22:16:56.138167 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10989 22:16:56.153130 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10990 22:16:56.196883 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10991 22:16:56.240298 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10992 22:16:56.290687
10993 22:16:56.290848
10994 22:16:56.294559 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10995 22:16:56.294647
10996 22:16:56.297138 debian-bullseye-arm64 login: root (automatic login)
10997 22:16:56.297223
10998 22:16:56.297308
10999 22:16:56.533186 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Sun Jun 4 21:56:05 UTC 2023 aarch64
11000 22:16:56.533344
11001 22:16:56.539751 The programs included with the Debian GNU/Linux system are free software;
11002 22:16:56.546308 the exact distribution terms for each program are described in the
11003 22:16:56.549823 individual files in /usr/share/doc/*/copyright.
11004 22:16:56.549907
11005 22:16:56.556465 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11006 22:16:56.559556 permitted by applicable law.
11007 22:16:56.643263 Matched prompt #10: / #
11009 22:16:56.644064 Setting prompt string to ['/ #']
11010 22:16:56.644422 end: 2.2.5.1 login-action (duration 00:00:26) [common]
11012 22:16:56.645153 end: 2.2.5 auto-login-action (duration 00:00:27) [common]
11013 22:16:56.645497 start: 2.2.6 expect-shell-connection (timeout 00:03:34) [common]
11014 22:16:56.645770 Setting prompt string to ['/ #']
11015 22:16:56.646022 Forcing a shell prompt, looking for ['/ #']
11017 22:16:56.696864 / #
11018 22:16:56.697678 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11019 22:16:56.698175 Waiting using forced prompt support (timeout 00:02:30)
11020 22:16:56.703292
11021 22:16:56.704114 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11022 22:16:56.704654 start: 2.2.7 export-device-env (timeout 00:03:34) [common]
11024 22:16:56.805926 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10583896/extract-nfsrootfs-cnr11rcj'
11025 22:16:56.812655 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10583896/extract-nfsrootfs-cnr11rcj'
11027 22:16:56.914585 / # export NFS_SERVER_IP='192.168.201.1'
11028 22:16:56.920772 export NFS_SERVER_IP='192.168.201.1'
11029 22:16:56.921717 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11030 22:16:56.922252 end: 2.2 depthcharge-retry (duration 00:01:26) [common]
11031 22:16:56.922777 end: 2 depthcharge-action (duration 00:01:26) [common]
11032 22:16:56.923270 start: 3 lava-test-retry (timeout 00:30:00) [common]
11033 22:16:56.923748 start: 3.1 lava-test-shell (timeout 00:30:00) [common]
11034 22:16:56.924160 Using namespace: common
11036 22:16:57.025350 / # #
11037 22:16:57.026008 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:30:00)
11038 22:16:57.031704 #
11039 22:16:57.032595 Using /lava-10583896
11041 22:16:57.133791 / # export SHELL=/bin/sh
11042 22:16:57.140397 export SHELL=/bin/sh
11044 22:16:57.242127 / # . /lava-10583896/environment
11045 22:16:57.248507 . /lava-10583896/environment
11047 22:16:57.356022 / # /lava-10583896/bin/lava-test-runner /lava-10583896/0
11048 22:16:57.356720 Test shell timeout: 10s (minimum of the action and connection timeout)
11049 22:16:57.362333 /lava-10583896/bin/lava-test-runner /lava-10583896/0
11050 22:16:57.589913 + export TESTRUN_ID=0_lc-compliance
11051 22:16:57.596188 + cd /lava-10583896/0/tests/0_lc-compliance
11052 22:16:57.596658 + cat uuid
11053 22:16:57.600507 + UUID=10583896_1.6.2.3.1
11054 22:16:57.600973 + set +x
11055 22:16:57.606080 <LAVA_SIGNAL_STARTRUN 0_lc-compliance 10583896_1.6.2.3.1>
11056 22:16:57.606818 Received signal: <STARTRUN> 0_lc-compliance 10583896_1.6.2.3.1
11057 22:16:57.607299 Starting test lava.0_lc-compliance (10583896_1.6.2.3.1)
11058 22:16:57.607770 Skipping test definition patterns.
11059 22:16:57.609564 + /usr/bin/lc-compliance-parser.sh
11060 22:16:58.745945 [0:00:27.671225309] [403] [1;32m INFO [1;37mCamera [1;34mcamera_manager.cpp:298 [0mlibcamera v0.0.0+1-76e1cb9f
11061 22:16:58.749210 Using camera /base/soc/usb@11200000-1.4.1:1.0-04f2:b741
11062 22:16:58.759427 [0:00:27.686619847] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11063 22:16:58.820554 [0:00:27.746066540] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11064 22:16:58.842594 [==========] Running 120 tests from 1 test suite.
11065 22:16:58.877177 [0:00:27.803018693] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11066 22:16:58.908914 [----------] Global test environment set-up.
11067 22:16:58.934446 [0:00:27.860080770] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11068 22:16:58.976154 [----------] 120 tests from CaptureTests/SingleStream
11069 22:16:59.032727 [ RUN ] CaptureTests/SingleStream.Capture/Raw_1
11070 22:16:59.086536 <LAVA_SIGNAL_TESTSET START CaptureTests/SingleStream>
11071 22:16:59.087238 Received signal: <TESTSET> START CaptureTests/SingleStream
11072 22:16:59.087634 Starting test_set CaptureTests/SingleStream
11073 22:16:59.089307 Camera needs 4 requests, can't test only 1
11074 22:16:59.170121 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11075 22:16:59.236760
11076 22:16:59.302002 [0:00:28.227795540] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11077 22:16:59.305345 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_1 (60 ms)
11078 22:16:59.391988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_1 RESULT=skip>
11079 22:16:59.392862 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_1 RESULT=skip
11081 22:16:59.405533 [ RUN ] CaptureTests/SingleStream.Capture/Raw_2
11082 22:16:59.455424 Camera needs 4 requests, can't test only 2
11083 22:16:59.521955 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11084 22:16:59.595313
11085 22:16:59.669856 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_2 (57 ms)
11086 22:16:59.762101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_2 RESULT=skip>
11087 22:16:59.762463 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_2 RESULT=skip
11089 22:16:59.771471 [0:00:28.695377309] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11090 22:16:59.782409 [ RUN ] CaptureTests/SingleStream.Capture/Raw_3
11091 22:16:59.835284 Camera needs 4 requests, can't test only 3
11092 22:16:59.909279 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11093 22:16:59.987602
11094 22:17:00.075773 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_3 (57 ms)
11095 22:17:00.181638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_3 RESULT=skip>
11096 22:17:00.182507 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_3 RESULT=skip
11098 22:17:00.199466 [ RUN ] CaptureTests/SingleStream.Capture/Raw_5
11099 22:17:00.249651 [ OK ] CaptureTests/SingleStream.Capture/Raw_5 (368 ms)
11100 22:17:00.321044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_5 RESULT=pass>
11101 22:17:00.321373 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_5 RESULT=pass
11103 22:17:00.333532 [ RUN ] CaptureTests/SingleStream.Capture/Raw_8
11104 22:17:00.377720 [ OK ] CaptureTests/SingleStream.Capture/Raw_8 (467 ms)
11105 22:17:00.452316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_8 RESULT=pass>
11106 22:17:00.453014 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_8 RESULT=pass
11108 22:17:00.469082 [0:00:29.394563617] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11109 22:17:00.472167 [ RUN ] CaptureTests/SingleStream.Capture/Raw_13
11110 22:17:00.523262 [ OK ] CaptureTests/SingleStream.Capture/Raw_13 (699 ms)
11111 22:17:00.600362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_13 RESULT=pass>
11112 22:17:00.601129 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_13 RESULT=pass
11114 22:17:00.614173 [ RUN ] CaptureTests/SingleStream.Capture/Raw_21
11115 22:17:01.459058 [ OK ] CaptureTests/SingleStream.Capture/Raw_21 (999 ms)
11116 22:17:01.471062 [0:00:30.393738078] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11117 22:17:01.550916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_21 RESULT=pass>
11118 22:17:01.551735 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_21 RESULT=pass
11120 22:17:01.567709 [ RUN ] CaptureTests/SingleStream.Capture/Raw_34
11121 22:17:02.859043 [ OK ] CaptureTests/SingleStream.Capture/Raw_34 (1400 ms)
11122 22:17:02.868685 [0:00:31.793242078] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11123 22:17:02.962240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_34 RESULT=pass>
11124 22:17:02.963060 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_34 RESULT=pass
11126 22:17:02.979686 [ RUN ] CaptureTests/SingleStream.Capture/Raw_55
11127 22:17:04.957733 [ OK ] CaptureTests/SingleStream.Capture/Raw_55 (2099 ms)
11128 22:17:04.966971 [0:00:33.891195540] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11129 22:17:05.056867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_55 RESULT=pass>
11130 22:17:05.057825 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_55 RESULT=pass
11132 22:17:05.072514 [ RUN ] CaptureTests/SingleStream.Capture/Raw_89
11133 22:17:08.186881 [ OK ] CaptureTests/SingleStream.Capture/Raw_89 (3230 ms)
11134 22:17:08.196735 [0:00:37.121756771] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11135 22:17:08.252796 [0:00:37.179644694] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11136 22:17:08.292901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_89 RESULT=pass>
11137 22:17:08.293638 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_89 RESULT=pass
11139 22:17:08.310464 [0:00:37.237010771] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11140 22:17:08.313342 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_1
11141 22:17:08.368040 [0:00:37.294324232] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11142 22:17:08.374315 Camera needs 4 requests, can't test only 1
11143 22:17:08.444002 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11144 22:17:08.513410
11145 22:17:08.590543 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_1 (58 ms)
11146 22:17:08.669002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_1 RESULT=skip>
11147 22:17:08.669726 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_1 RESULT=skip
11149 22:17:08.684010 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_2
11150 22:17:08.733654 Camera needs 4 requests, can't test only 2
11151 22:17:08.810014 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11152 22:17:08.832739 [0:00:37.759783771] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11153 22:17:08.883075
11154 22:17:08.949715 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_2 (58 ms)
11155 22:17:09.029479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_2 RESULT=skip>
11156 22:17:09.030181 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_2 RESULT=skip
11158 22:17:09.044496 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_3
11159 22:17:09.093283 Camera needs 4 requests, can't test only 3
11160 22:17:09.161151 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11161 22:17:09.240971
11162 22:17:09.329750 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_3 (57 ms)
11163 22:17:09.400641 [0:00:38.327272002] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11164 22:17:09.430881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_3 RESULT=skip>
11165 22:17:09.431649 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_3 RESULT=skip
11167 22:17:09.445549 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_5
11168 22:17:09.496196 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_5 (465 ms)
11169 22:17:09.572665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_5 RESULT=pass>
11170 22:17:09.573438 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_5 RESULT=pass
11172 22:17:09.590235 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_8
11173 22:17:09.643447 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_8 (567 ms)
11174 22:17:09.732151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_8 RESULT=pass>
11175 22:17:09.733017 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_8 RESULT=pass
11177 22:17:09.745240 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_13
11178 22:17:10.091267 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_13 (699 ms)
11179 22:17:10.104224 [0:00:39.027795617] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11180 22:17:10.193292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_13 RESULT=pass>
11181 22:17:10.194098 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_13 RESULT=pass
11183 22:17:10.206987 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_21
11184 22:17:10.995634 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_21 (905 ms)
11185 22:17:11.008474 [0:00:39.931956156] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11186 22:17:11.073978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_21 RESULT=pass>
11187 22:17:11.074248 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_21 RESULT=pass
11189 22:17:11.085250 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_34
11190 22:17:12.396098 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_34 (1400 ms)
11191 22:17:12.409169 [0:00:41.332844617] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11192 22:17:12.483462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_34 RESULT=pass>
11193 22:17:12.484248 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_34 RESULT=pass
11195 22:17:12.494848 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_55
11196 22:17:14.530152 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_55 (2135 ms)
11197 22:17:14.542686 [0:00:43.466799156] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11198 22:17:14.638389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_55 RESULT=pass>
11199 22:17:14.639193 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_55 RESULT=pass
11201 22:17:14.654559 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_89
11202 22:17:17.106924 <6>[ 46.153707] vpu: disabling
11203 22:17:17.110101 <6>[ 46.156757] vproc2: disabling
11204 22:17:17.113287 <6>[ 46.160028] vproc1: disabling
11205 22:17:17.116923 <6>[ 46.163289] vaud18: disabling
11206 22:17:17.123494 <6>[ 46.166700] vsram_others: disabling
11207 22:17:17.126425 <6>[ 46.170576] va09: disabling
11208 22:17:17.129468 <6>[ 46.173684] vsram_md: disabling
11209 22:17:17.132718 <6>[ 46.177170] Vgpu: disabling
11210 22:17:17.760444 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_89 (3231 ms)
11211 22:17:17.773623 [0:00:46.696159464] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11212 22:17:17.826929 [0:00:46.754634002] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11213 22:17:17.861121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_89 RESULT=pass>
11214 22:17:17.861824 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_89 RESULT=pass
11216 22:17:17.875228 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_1
11217 22:17:17.884726 [0:00:46.811677695] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11218 22:17:17.929047 Camera needs 4 requests, can't test only 1
11219 22:17:17.938646 [0:00:46.868999618] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11220 22:17:18.002079 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11221 22:17:18.072518
11222 22:17:18.146916 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_1 (58 ms)
11223 22:17:18.230016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_1 RESULT=skip>
11224 22:17:18.230769 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_1 RESULT=skip
11226 22:17:18.244367 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_2
11227 22:17:18.289622 Camera needs 4 requests, can't test only 2
11228 22:17:18.372632 [0:00:47.300422541] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11229 22:17:18.375648 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11230 22:17:18.446483
11231 22:17:18.519864 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_2 (57 ms)
11232 22:17:18.591499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_2 RESULT=skip>
11233 22:17:18.592255 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_2 RESULT=skip
11235 22:17:18.604652 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_3
11236 22:17:18.652251 Camera needs 4 requests, can't test only 3
11237 22:17:18.721279 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11238 22:17:18.773902
11239 22:17:18.843533 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_3 (57 ms)
11240 22:17:18.904121 [0:00:47.832315310] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11241 22:17:18.935670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_3 RESULT=skip>
11242 22:17:18.936363 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_3 RESULT=skip
11244 22:17:18.949758 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_5
11245 22:17:18.999104 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_5 (431 ms)
11246 22:17:19.072643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_5 RESULT=pass>
11247 22:17:19.073328 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_5 RESULT=pass
11249 22:17:19.087751 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_8
11250 22:17:19.137568 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_8 (532 ms)
11251 22:17:19.219442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_8 RESULT=pass>
11252 22:17:19.220161 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_8 RESULT=pass
11254 22:17:19.233444 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_13
11255 22:17:19.563048 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_13 (667 ms)
11256 22:17:19.576489 [0:00:48.499712541] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11257 22:17:19.655758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_13 RESULT=pass>
11258 22:17:19.656533 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_13 RESULT=pass
11260 22:17:19.671344 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_21
11261 22:17:20.464728 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_21 (901 ms)
11262 22:17:20.477283 [0:00:49.400587387] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11263 22:17:20.548919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_21 RESULT=pass>
11264 22:17:20.549284 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_21 RESULT=pass
11266 22:17:20.561116 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_34
11267 22:17:21.866999 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_34 (1399 ms)
11268 22:17:21.876555 [0:00:50.800098695] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11269 22:17:21.963975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_34 RESULT=pass>
11270 22:17:21.964846 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_34 RESULT=pass
11272 22:17:21.977973 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_55
11273 22:17:23.962252 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_55 (2099 ms)
11274 22:17:23.975603 [0:00:52.899034618] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11275 22:17:24.039648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_55 RESULT=pass>
11276 22:17:24.039997 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_55 RESULT=pass
11278 22:17:24.048675 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_89
11279 22:17:27.193985 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_89 (3232 ms)
11280 22:17:27.206702 [0:00:56.131073204] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11281 22:17:27.259781 [0:00:56.188552591] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11282 22:17:27.297774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_89 RESULT=pass>
11283 22:17:27.298655 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_89 RESULT=pass
11285 22:17:27.317841 [0:00:56.246326555] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11286 22:17:27.320727 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_1
11287 22:17:27.374204 [0:00:56.303197020] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11288 22:17:27.377571 Camera needs 4 requests, can't test only 1
11289 22:17:27.455139 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11290 22:17:27.517176
11291 22:17:27.578246 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_1 (58 ms)
11292 22:17:27.647810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_1 RESULT=skip>
11293 22:17:27.648126 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_1 RESULT=skip
11295 22:17:27.659189 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_2
11296 22:17:27.705932 Camera needs 4 requests, can't test only 2
11297 22:17:27.744290 [0:00:56.673319910] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11298 22:17:27.776188 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11299 22:17:27.840394
11300 22:17:27.913369 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_2 (58 ms)
11301 22:17:27.988185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_2 RESULT=skip>
11302 22:17:27.988469 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_2 RESULT=skip
11304 22:17:28.002606 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_3
11305 22:17:28.047485 Camera needs 4 requests, can't test only 3
11306 22:17:28.118831 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11307 22:17:28.181626
11308 22:17:28.213639 [0:00:57.142762377] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11309 22:17:28.256519 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_3 (57 ms)
11310 22:17:28.336083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_3 RESULT=skip>
11311 22:17:28.336416 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_3 RESULT=skip
11313 22:17:28.347087 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_5
11314 22:17:28.391955 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_5 (369 ms)
11315 22:17:28.482957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_5 RESULT=pass>
11316 22:17:28.483277 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_5 RESULT=pass
11318 22:17:28.497972 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_8
11319 22:17:28.547854 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_8 (470 ms)
11320 22:17:28.626822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_8 RESULT=pass>
11321 22:17:28.627586 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_8 RESULT=pass
11323 22:17:28.640539 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_13
11324 22:17:28.937319 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_13 (731 ms)
11325 22:17:28.950102 [0:00:57.874727331] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11326 22:17:29.029793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_13 RESULT=pass>
11327 22:17:29.030203 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_13 RESULT=pass
11329 22:17:29.043511 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_21
11330 22:17:29.839445 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_21 (903 ms)
11331 22:17:29.852757 [0:00:58.777193004] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11332 22:17:29.936237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_21 RESULT=pass>
11333 22:17:29.937141 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_21 RESULT=pass
11335 22:17:29.952243 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_34
11336 22:17:31.238922 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_34 (1399 ms)
11337 22:17:31.252302 [0:01:00.176526179] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11338 22:17:31.329138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_34 RESULT=pass>
11339 22:17:31.330022 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_34 RESULT=pass
11341 22:17:31.345275 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_55
11342 22:17:33.338424 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_55 (2099 ms)
11343 22:17:33.350963 [0:01:02.275672618] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11344 22:17:33.423303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_55 RESULT=pass>
11345 22:17:33.423576 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_55 RESULT=pass
11347 22:17:33.434868 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_89
11348 22:17:36.569819 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_89 (3232 ms)
11349 22:17:36.582763 [0:01:05.507104546] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11350 22:17:36.636151 [0:01:05.565691293] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11351 22:17:36.663303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_89 RESULT=pass>
11352 22:17:36.663612 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_89 RESULT=pass
11354 22:17:36.674231 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_1
11355 22:17:36.693882 [0:01:05.622718922] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11356 22:17:36.733193 Camera needs 4 requests, can't test only 1
11357 22:17:36.750641 [0:01:05.679803932] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11358 22:17:36.808890 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11359 22:17:36.869252
11360 22:17:36.926370 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_1 (59 ms)
11361 22:17:36.990042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_1 RESULT=skip>
11362 22:17:36.990319 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_1 RESULT=skip
11364 22:17:37.004007 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_2
11365 22:17:37.052383 Camera needs 4 requests, can't test only 2
11366 22:17:37.124564 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11367 22:17:37.187430
11368 22:17:37.254281 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_2 (57 ms)
11369 22:17:37.329221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_2 RESULT=skip>
11370 22:17:37.329550 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_2 RESULT=skip
11372 22:17:37.343454 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_3
11373 22:17:37.391862 Camera needs 4 requests, can't test only 3
11374 22:17:37.463764 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11375 22:17:37.534302
11376 22:17:37.615289 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_3 (57 ms)
11377 22:17:37.698977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_3 RESULT=skip>
11378 22:17:37.699260 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_3 RESULT=skip
11380 22:17:37.711146 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_5
11381 22:17:38.003178 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_5 (1261 ms)
11382 22:17:38.016161 [0:01:06.939981442] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11383 22:17:38.091013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_5 RESULT=pass>
11384 22:17:38.091340 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_5 RESULT=pass
11386 22:17:38.101904 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_8
11387 22:17:39.493783 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_8 (1490 ms)
11388 22:17:39.506693 [0:01:08.430483756] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11389 22:17:39.592852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_8 RESULT=pass>
11390 22:17:39.593728 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_8 RESULT=pass
11392 22:17:39.608655 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_13
11393 22:17:41.581416 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_13 (2088 ms)
11394 22:17:41.594079 [0:01:10.518139818] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11395 22:17:41.665914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_13 RESULT=pass>
11396 22:17:41.666184 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_13 RESULT=pass
11398 22:17:41.677569 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_21
11399 22:17:44.271901 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_21 (2690 ms)
11400 22:17:44.284999 [0:01:13.208547826] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11401 22:17:44.366024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_21 RESULT=pass>
11402 22:17:44.366290 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_21 RESULT=pass
11404 22:17:44.379834 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_34
11405 22:17:48.488968 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_34 (4217 ms)
11406 22:17:48.500989 [0:01:17.426004411] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11407 22:17:48.572547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_34 RESULT=pass>
11408 22:17:48.572840 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_34 RESULT=pass
11410 22:17:48.587158 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_55
11411 22:17:54.805272 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_55 (6317 ms)
11412 22:17:54.817884 [0:01:23.742923081] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11413 22:17:54.893734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_55 RESULT=pass>
11414 22:17:54.894474 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_55 RESULT=pass
11416 22:17:54.908229 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_89
11417 22:18:04.423083 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_89 (9618 ms)
11418 22:18:04.435614 [0:01:33.361563843] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11419 22:18:04.486677 [0:01:33.418135477] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11420 22:18:04.518513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_89 RESULT=pass>
11421 22:18:04.518791 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_89 RESULT=pass
11423 22:18:04.533387 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_1
11424 22:18:04.546382 [0:01:33.474749648] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11425 22:18:04.588129 Camera needs 4 requests, can't test only 1
11426 22:18:04.600705 [0:01:33.532036273] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11427 22:18:04.660024 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11428 22:18:04.727810
11429 22:18:04.807618 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_1 (57 ms)
11430 22:18:04.884028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_1 RESULT=skip>
11431 22:18:04.884607 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_1 RESULT=skip
11433 22:18:04.894018 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_2
11434 22:18:04.942603 Camera needs 4 requests, can't test only 2
11435 22:18:05.011540 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11436 22:18:05.091634
11437 22:18:05.164319 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_2 (56 ms)
11438 22:18:05.248183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_2 RESULT=skip>
11439 22:18:05.248956 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_2 RESULT=skip
11441 22:18:05.259859 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_3
11442 22:18:05.309847 Camera needs 4 requests, can't test only 3
11443 22:18:05.379246 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11444 22:18:05.451754
11445 22:18:05.527499 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_3 (58 ms)
11446 22:18:05.601804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_3 RESULT=skip>
11447 22:18:05.602102 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_3 RESULT=skip
11449 22:18:05.608958 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_5
11450 22:18:05.884072 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_5 (1287 ms)
11451 22:18:05.893643 [0:01:34.821065607] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11452 22:18:05.968921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_5 RESULT=pass>
11453 22:18:05.969295 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_5 RESULT=pass
11455 22:18:05.977230 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_8
11456 22:18:07.571725 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_8 (1687 ms)
11457 22:18:07.581443 [0:01:36.509446196] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11458 22:18:07.654712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_8 RESULT=pass>
11459 22:18:07.655711 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_8 RESULT=pass
11461 22:18:07.665325 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_13
11462 22:18:09.596537 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_13 (2025 ms)
11463 22:18:09.606487 [0:01:38.534766480] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11464 22:18:09.686758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_13 RESULT=pass>
11465 22:18:09.687574 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_13 RESULT=pass
11467 22:18:09.697909 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_21
11468 22:18:12.288125 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_21 (2692 ms)
11469 22:18:12.297634 [0:01:41.225375961] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11470 22:18:12.376752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_21 RESULT=pass>
11471 22:18:12.377621 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_21 RESULT=pass
11473 22:18:12.388374 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_34
11474 22:18:16.474938 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_34 (4188 ms)
11475 22:18:16.484712 [0:01:45.412689828] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11476 22:18:16.567220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_34 RESULT=pass>
11477 22:18:16.568095 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_34 RESULT=pass
11479 22:18:16.579214 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_55
11480 22:18:22.793128 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_55 (6319 ms)
11481 22:18:22.802747 [0:01:51.731832986] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11482 22:18:22.880417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_55 RESULT=pass>
11483 22:18:22.881119 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_55 RESULT=pass
11485 22:18:22.890742 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_89
11486 22:18:32.412835 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_89 (9620 ms)
11487 22:18:32.422616 [0:02:01.352693694] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11488 22:18:32.475750 [0:02:01.410595022] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11489 22:18:32.513399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_89 RESULT=pass>
11490 22:18:32.513664 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_89 RESULT=pass
11492 22:18:32.520929 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_1
11493 22:18:32.534133 [0:02:01.467516380] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11494 22:18:32.570884 Camera needs 4 requests, can't test only 1
11495 22:18:32.589398 [0:02:01.524018541] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11496 22:18:32.648319 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11497 22:18:32.706241
11498 22:18:32.775716 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_1 (59 ms)
11499 22:18:32.844884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_1 RESULT=skip>
11500 22:18:32.845386 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_1 RESULT=skip
11502 22:18:32.856527 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_2
11503 22:18:32.898293 Camera needs 4 requests, can't test only 2
11504 22:18:32.957826 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11505 22:18:33.019688
11506 22:18:33.097225 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_2 (57 ms)
11507 22:18:33.172356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_2 RESULT=skip>
11508 22:18:33.173128 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_2 RESULT=skip
11510 22:18:33.183460 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_3
11511 22:18:33.228243 Camera needs 4 requests, can't test only 3
11512 22:18:33.288494 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11513 22:18:33.355325
11514 22:18:33.436018 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_3 (57 ms)
11515 22:18:33.516989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_3 RESULT=skip>
11516 22:18:33.517312 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_3 RESULT=skip
11518 22:18:33.524904 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_5
11519 22:18:33.910301 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_5 (1324 ms)
11520 22:18:33.919944 [0:02:02.850311986] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11521 22:18:34.018569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_5 RESULT=pass>
11522 22:18:34.019285 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_5 RESULT=pass
11524 22:18:34.031483 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_8
11525 22:18:35.598449 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_8 (1688 ms)
11526 22:18:35.608060 [0:02:04.537738732] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11527 22:18:35.696526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_8 RESULT=pass>
11528 22:18:35.697526 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_8 RESULT=pass
11530 22:18:35.708449 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_13
11531 22:18:37.623438 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_13 (2025 ms)
11532 22:18:37.633690 [0:02:06.563727851] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11533 22:18:37.720105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_13 RESULT=pass>
11534 22:18:37.720441 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_13 RESULT=pass
11536 22:18:37.727371 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_21
11537 22:18:40.317245 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_21 (2694 ms)
11538 22:18:40.326775 [0:02:09.256464086] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11539 22:18:40.398392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_21 RESULT=pass>
11540 22:18:40.398734 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_21 RESULT=pass
11542 22:18:40.405244 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_34
11543 22:18:44.504358 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_34 (4186 ms)
11544 22:18:44.514258 [0:02:13.443610238] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11545 22:18:44.593856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_34 RESULT=pass>
11546 22:18:44.594177 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_34 RESULT=pass
11548 22:18:44.602074 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_55
11549 22:18:50.790189 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_55 (6285 ms)
11550 22:18:50.800014 [0:02:19.728559293] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11551 22:18:50.883739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_55 RESULT=pass>
11552 22:18:50.884031 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_55 RESULT=pass
11554 22:18:50.893276 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_89
11555 22:19:00.444230 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_89 (9653 ms)
11556 22:19:00.453959 [0:02:29.381264397] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11557 22:19:00.508008 [0:02:29.440851018] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11558 22:19:00.543322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_89 RESULT=pass>
11559 22:19:00.543604 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_89 RESULT=pass
11561 22:19:00.553372 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_1
11562 22:19:00.567220 [0:02:29.498115855] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11563 22:19:00.604812 Camera needs 4 requests, can't test only 1
11564 22:19:00.622493 [0:02:29.555000817] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11565 22:19:00.690155 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11566 22:19:00.764591
11567 22:19:00.850913 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_1 (60 ms)
11568 22:19:00.936587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_1 RESULT=skip>
11569 22:19:00.937358 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_1 RESULT=skip
11571 22:19:00.947795 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_2
11572 22:19:00.999595 Camera needs 4 requests, can't test only 2
11573 22:19:01.068239 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11574 22:19:01.138471
11575 22:19:01.225467 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_2 (58 ms)
11576 22:19:01.311395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_2 RESULT=skip>
11577 22:19:01.312094 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_2 RESULT=skip
11579 22:19:01.321985 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_3
11580 22:19:01.373339 Camera needs 4 requests, can't test only 3
11581 22:19:01.444629 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11582 22:19:01.523639
11583 22:19:01.597423 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_3 (57 ms)
11584 22:19:01.676326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_3 RESULT=skip>
11585 22:19:01.677057 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_3 RESULT=skip
11587 22:19:01.688363 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_5
11588 22:19:01.813016 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_5 (1194 ms)
11589 22:19:01.822839 [0:02:30.750918770] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11590 22:19:01.910461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_5 RESULT=pass>
11591 22:19:01.911170 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_5 RESULT=pass
11593 22:19:01.921783 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_8
11594 22:19:03.207154 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_8 (1394 ms)
11595 22:19:03.217916 [0:02:32.144873453] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11596 22:19:03.306188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_8 RESULT=pass>
11597 22:19:03.306936 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_8 RESULT=pass
11599 22:19:03.316225 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_13
11600 22:19:05.296780 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_13 (2089 ms)
11601 22:19:05.306899 [0:02:34.234451179] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11602 22:19:05.386147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_13 RESULT=pass>
11603 22:19:05.386985 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_13 RESULT=pass
11605 22:19:05.397517 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_21
11606 22:19:08.087672 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_21 (2791 ms)
11607 22:19:08.096761 [0:02:37.024755900] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11608 22:19:08.176370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_21 RESULT=pass>
11609 22:19:08.176703 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_21 RESULT=pass
11611 22:19:08.187969 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_34
11612 22:19:12.274255 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_34 (4187 ms)
11613 22:19:12.284505 [0:02:41.212330719] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11614 22:19:12.371941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_34 RESULT=pass>
11615 22:19:12.372268 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_34 RESULT=pass
11617 22:19:12.382883 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_55
11618 22:19:18.560582 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_55 (6286 ms)
11619 22:19:18.570456 [0:02:47.498645156] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11620 22:19:18.655348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_55 RESULT=pass>
11621 22:19:18.656196 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_55 RESULT=pass
11623 22:19:18.666081 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_89
11624 22:19:28.180512 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_89 (9620 ms)
11625 22:19:28.189910 [0:02:57.118758463] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11626 22:19:28.268470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_89 RESULT=pass>
11627 22:19:28.269197 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_89 RESULT=pass
11629 22:19:28.282043 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_1
11630 22:19:28.475935 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_1 (299 ms)
11631 22:19:28.489122 [0:02:57.417703968] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11632 22:19:28.574835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_1 RESULT=pass>
11633 22:19:28.575541 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_1 RESULT=pass
11635 22:19:28.592112 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_2
11636 22:19:28.744410 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_2 (268 ms)
11637 22:19:28.757335 [0:02:57.685633931] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11638 22:19:28.845880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_2 RESULT=pass>
11639 22:19:28.846813 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_2 RESULT=pass
11641 22:19:28.862206 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_3
11642 22:19:29.045721 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_3 (301 ms)
11643 22:19:29.058405 [0:02:57.987069951] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11644 22:19:29.123798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_3 RESULT=pass>
11645 22:19:29.124171 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_3 RESULT=pass
11647 22:19:29.134479 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_5
11648 22:19:29.478222 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_5 (433 ms)
11649 22:19:29.491756 [0:02:58.419675345] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11650 22:19:29.563808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_5 RESULT=pass>
11651 22:19:29.564561 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_5 RESULT=pass
11653 22:19:29.577208 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_8
11654 22:19:29.946501 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_8 (468 ms)
11655 22:19:29.959054 [0:02:58.887614582] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11656 22:19:30.041829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_8 RESULT=pass>
11657 22:19:30.042713 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_8 RESULT=pass
11659 22:19:30.058383 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_13
11660 22:19:30.645563 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_13 (699 ms)
11661 22:19:30.658668 [0:02:59.587295175] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11662 22:19:30.725153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_13 RESULT=pass>
11663 22:19:30.725978 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_13 RESULT=pass
11665 22:19:30.737552 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_21
11666 22:19:31.644966 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_21 (999 ms)
11667 22:19:31.658322 [0:03:00.586681709] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11668 22:19:31.738106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_21 RESULT=pass>
11669 22:19:31.738435 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_21 RESULT=pass
11671 22:19:31.750679 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_34
11672 22:19:33.077346 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_34 (1433 ms)
11673 22:19:33.090144 [0:03:02.019088950] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11674 22:19:33.171546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_34 RESULT=pass>
11675 22:19:33.171845 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_34 RESULT=pass
11677 22:19:33.183116 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_55
11678 22:19:35.174991 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_55 (2098 ms)
11679 22:19:35.187796 [0:03:04.116713099] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11680 22:19:35.252676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_55 RESULT=pass>
11681 22:19:35.253002 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_55 RESULT=pass
11683 22:19:35.263081 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_89
11684 22:19:38.406651 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_89 (3231 ms)
11685 22:19:38.419826 [0:03:07.348646567] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11686 22:19:38.499508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_89 RESULT=pass>
11687 22:19:38.499828 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_89 RESULT=pass
11689 22:19:38.512096 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_1
11690 22:19:38.709922 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_1 (300 ms)
11691 22:19:38.720797 [0:03:07.648240275] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11692 22:19:38.790281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_1 RESULT=pass>
11693 22:19:38.790673 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_1 RESULT=pass
11695 22:19:38.796893 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_2
11696 22:19:39.043381 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_2 (333 ms)
11697 22:19:39.052905 [0:03:07.982227649] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11698 22:19:39.128282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_2 RESULT=pass>
11699 22:19:39.129074 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_2 RESULT=pass
11701 22:19:39.138441 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_3
11702 22:19:39.344661 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_3 (301 ms)
11703 22:19:39.354658 [0:03:08.283316543] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11704 22:19:39.440003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_3 RESULT=pass>
11705 22:19:39.440710 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_3 RESULT=pass
11707 22:19:39.450032 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_5
11708 22:19:39.810320 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_5 (466 ms)
11709 22:19:39.820253 [0:03:08.748914969] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11710 22:19:39.904861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_5 RESULT=pass>
11711 22:19:39.905646 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_5 RESULT=pass
11713 22:19:39.917823 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_8
11714 22:19:40.376716 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_8 (566 ms)
11715 22:19:40.385881 [0:03:09.314941335] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11716 22:19:40.471036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_8 RESULT=pass>
11717 22:19:40.471850 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_8 RESULT=pass
11719 22:19:40.480665 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_13
11720 22:19:41.074896 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_13 (699 ms)
11721 22:19:41.085365 [0:03:10.014025079] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11722 22:19:41.179292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_13 RESULT=pass>
11723 22:19:41.180192 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_13 RESULT=pass
11725 22:19:41.192019 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_21
11726 22:19:41.976809 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_21 (901 ms)
11727 22:19:41.986195 [0:03:10.915510256] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11728 22:19:42.070395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_21 RESULT=pass>
11729 22:19:42.071232 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_21 RESULT=pass
11731 22:19:42.082919 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_34
11732 22:19:43.376180 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_34 (1400 ms)
11733 22:19:43.385811 [0:03:12.315153309] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11734 22:19:43.461333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_34 RESULT=pass>
11735 22:19:43.461602 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_34 RESULT=pass
11737 22:19:43.468271 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_55
11738 22:19:45.507874 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_55 (2132 ms)
11739 22:19:45.517862 [0:03:14.446986929] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11740 22:19:45.607139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_55 RESULT=pass>
11741 22:19:45.607869 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_55 RESULT=pass
11743 22:19:45.617853 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_89
11744 22:19:48.739933 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_89 (3232 ms)
11745 22:19:48.749214 [0:03:17.678969482] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11746 22:19:48.828412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_89 RESULT=pass>
11747 22:19:48.828723 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_89 RESULT=pass
11749 22:19:48.836271 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_1
11750 22:19:48.976299 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_1 (237 ms)
11751 22:19:48.986458 [0:03:17.915755308] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11752 22:19:49.065891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_1 RESULT=pass>
11753 22:19:49.066234 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_1 RESULT=pass
11755 22:19:49.075967 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_2
11756 22:19:49.247059 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_2 (270 ms)
11757 22:19:49.256940 [0:03:18.186652319] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11758 22:19:49.333803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_2 RESULT=pass>
11759 22:19:49.334075 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_2 RESULT=pass
11761 22:19:49.342528 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_3
11762 22:19:49.547594 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_3 (301 ms)
11763 22:19:49.557811 [0:03:18.487628597] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11764 22:19:49.634765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_3 RESULT=pass>
11765 22:19:49.635043 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_3 RESULT=pass
11767 22:19:49.642315 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_5
11768 22:19:49.982000 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_5 (434 ms)
11769 22:19:49.991297 [0:03:18.920635165] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11770 22:19:50.070881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_5 RESULT=pass>
11771 22:19:50.071224 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_5 RESULT=pass
11773 22:19:50.081665 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_8
11774 22:19:50.513290 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_8 (531 ms)
11775 22:19:50.522880 [0:03:19.451640219] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11776 22:19:50.601635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_8 RESULT=pass>
11777 22:19:50.602455 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_8 RESULT=pass
11779 22:19:50.610778 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_13
11780 22:19:51.211306 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_13 (698 ms)
11781 22:19:51.220856 [0:03:20.150016274] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11782 22:19:51.303992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_13 RESULT=pass>
11783 22:19:51.304699 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_13 RESULT=pass
11785 22:19:51.317441 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_21
11786 22:19:52.111282 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_21 (900 ms)
11787 22:19:52.121384 [0:03:21.050325171] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11788 22:19:52.206083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_21 RESULT=pass>
11789 22:19:52.206825 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_21 RESULT=pass
11791 22:19:52.218318 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_34
11792 22:19:53.507849 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_34 (1396 ms)
11793 22:19:53.518187 [0:03:22.446747368] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11794 22:19:53.600730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_34 RESULT=pass>
11795 22:19:53.601499 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_34 RESULT=pass
11797 22:19:53.611571 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_55
11798 22:19:55.604578 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_55 (2096 ms)
11799 22:19:55.613514 [0:03:24.543024560] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11800 22:19:55.695399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_55 RESULT=pass>
11801 22:19:55.696117 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_55 RESULT=pass
11803 22:19:55.708973 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_89
11804 22:19:58.833095 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_89 (3229 ms)
11805 22:19:58.842826 [0:03:27.772493760] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11806 22:19:58.926063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_89 RESULT=pass>
11807 22:19:58.926885 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_89 RESULT=pass
11809 22:19:58.938402 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_1
11810 22:19:59.069726 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_1 (237 ms)
11811 22:19:59.079270 [0:03:28.009831999] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11812 22:19:59.160250 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_1 RESULT=pass
11814 22:19:59.163129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_1 RESULT=pass>
11815 22:19:59.174308 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_2
11816 22:19:59.339832 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_2 (270 ms)
11817 22:19:59.350010 [0:03:28.279628259] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11818 22:19:59.422197 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_2 RESULT=pass
11820 22:19:59.425175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_2 RESULT=pass>
11821 22:19:59.434783 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_3
11822 22:19:59.640355 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_3 (300 ms)
11823 22:19:59.649705 [0:03:28.579944472] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11824 22:19:59.716853 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_3 RESULT=pass
11826 22:19:59.720175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_3 RESULT=pass>
11827 22:19:59.728354 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_5
11828 22:20:00.072692 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_5 (433 ms)
11829 22:20:00.082461 [0:03:29.012637245] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11830 22:20:00.161747 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_5 RESULT=pass
11832 22:20:00.164673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_5 RESULT=pass>
11833 22:20:00.178826 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_8
11834 22:20:00.605385 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_8 (532 ms)
11835 22:20:00.614837 [0:03:29.545540156] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11836 22:20:00.681535 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_8 RESULT=pass
11838 22:20:00.685029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_8 RESULT=pass>
11839 22:20:00.691599 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_13
11840 22:20:01.304169 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_13 (699 ms)
11841 22:20:01.314031 [0:03:30.244664687] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11842 22:20:01.382109 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_13 RESULT=pass
11844 22:20:01.385220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_13 RESULT=pass>
11845 22:20:01.393662 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_21
11846 22:20:02.205895 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_21 (902 ms)
11847 22:20:02.215964 [0:03:31.146410524] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11848 22:20:02.295033 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_21 RESULT=pass
11850 22:20:02.298416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_21 RESULT=pass>
11851 22:20:02.309875 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_34
11852 22:20:03.604646 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_34 (1399 ms)
11853 22:20:03.614785 [0:03:32.545266535] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11854 22:20:03.697204 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_34 RESULT=pass
11856 22:20:03.700223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_34 RESULT=pass>
11857 22:20:03.711396 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_55
11858 22:20:05.704476 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_55 (2100 ms)
11859 22:20:05.714035 [0:03:34.644619330] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11860 22:20:05.784692 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_55 RESULT=pass
11862 22:20:05.788469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_55 RESULT=pass>
11863 22:20:05.797866 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_89
11864 22:20:08.935760 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_89 (3232 ms)
11865 22:20:09.019388 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_89 RESULT=pass
11867 22:20:09.022225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_89 RESULT=pass>
11868 22:20:09.033514 [----------] 120 tests from CaptureTests/SingleStream (190191 ms total)
11869 22:20:09.103410
11870 22:20:09.178992 [----------] Global test environment tear-down
11871 22:20:09.250442 [==========] 120 tests from 1 test suite ran. (190191 ms total)
11872 22:20:09.324904 <LAVA_SIGNAL_TESTSET STOP>
11873 22:20:09.325282 Received signal: <TESTSET> STOP
11874 22:20:09.325383 Closing test_set CaptureTests/SingleStream
11875 22:20:09.334701 + set +x
11876 22:20:09.338531 <LAVA_SIGNAL_ENDRUN 0_lc-compliance 10583896_1.6.2.3.1>
11877 22:20:09.338784 Received signal: <ENDRUN> 0_lc-compliance 10583896_1.6.2.3.1
11878 22:20:09.338863 Ending use of test pattern.
11879 22:20:09.338926 Ending test lava.0_lc-compliance (10583896_1.6.2.3.1), duration 191.73
11881 22:20:09.341643 <LAVA_TEST_RUNNER EXIT>
11882 22:20:09.341997 ok: lava_test_shell seems to have completed
11883 22:20:09.344017 Capture/Raw_1:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_13:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_2:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_21:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_3:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_34:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_5:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_55:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_8:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_89:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_1:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_2:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_3:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_1:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_2:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_3:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_1:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_2:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_3:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
11884 22:20:09.344228 end: 3.1 lava-test-shell (duration 00:03:12) [common]
11885 22:20:09.344322 end: 3 lava-test-retry (duration 00:03:12) [common]
11886 22:20:09.344418 start: 4 finalize (timeout 00:10:00) [common]
11887 22:20:09.344515 start: 4.1 power-off (timeout 00:00:30) [common]
11888 22:20:09.344679 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=off'
11889 22:20:09.422389 >> Command sent successfully.
11890 22:20:09.427556 Returned 0 in 0 seconds
11891 22:20:09.528545 end: 4.1 power-off (duration 00:00:00) [common]
11893 22:20:09.530061 start: 4.2 read-feedback (timeout 00:10:00) [common]
11894 22:20:09.531333 Listened to connection for namespace 'common' for up to 1s
11895 22:20:10.532047 Finalising connection for namespace 'common'
11896 22:20:10.532805 Disconnecting from shell: Finalise
11897 22:20:10.533283 / #
11898 22:20:10.634275 end: 4.2 read-feedback (duration 00:00:01) [common]
11899 22:20:10.635150 end: 4 finalize (duration 00:00:01) [common]
11900 22:20:10.635822 Cleaning after the job
11901 22:20:10.636338 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10583896/tftp-deploy-406nn8fa/ramdisk
11902 22:20:10.646278 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10583896/tftp-deploy-406nn8fa/kernel
11903 22:20:10.678824 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10583896/tftp-deploy-406nn8fa/dtb
11904 22:20:10.679238 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10583896/tftp-deploy-406nn8fa/nfsrootfs
11905 22:20:10.729363 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10583896/tftp-deploy-406nn8fa/modules
11906 22:20:10.734870 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10583896
11907 22:20:10.982178 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10583896
11908 22:20:10.982585 Job finished correctly