Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 41
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 33
1 22:54:25.453095 lava-dispatcher, installed at version: 2023.05.1
2 22:54:25.453329 start: 0 validate
3 22:54:25.453456 Start time: 2023-06-05 22:54:25.453447+00:00 (UTC)
4 22:54:25.453575 Using caching service: 'http://localhost/cache/?uri=%s'
5 22:54:25.453703 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20230527.0%2Farm64%2Finitrd.cpio.gz exists
6 22:54:25.746919 Using caching service: 'http://localhost/cache/?uri=%s'
7 22:54:25.747729 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1314-g1ab0ac1d7e2e3%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 22:55:06.786289 Using caching service: 'http://localhost/cache/?uri=%s'
9 22:55:06.787069 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1314-g1ab0ac1d7e2e3%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 22:55:07.077021 Using caching service: 'http://localhost/cache/?uri=%s'
11 22:55:07.077773 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20230527.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 22:55:07.646462 Using caching service: 'http://localhost/cache/?uri=%s'
13 22:55:07.647241 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1314-g1ab0ac1d7e2e3%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 22:55:09.656832 validate duration: 44.20
16 22:55:09.657091 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 22:55:09.657187 start: 1.1 download-retry (timeout 00:10:00) [common]
18 22:55:09.657276 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 22:55:09.657400 Not decompressing ramdisk as can be used compressed.
20 22:55:09.657483 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20230527.0/arm64/initrd.cpio.gz
21 22:55:09.657547 saving as /var/lib/lava/dispatcher/tmp/10597661/tftp-deploy-zpr5obgr/ramdisk/initrd.cpio.gz
22 22:55:09.657610 total size: 5624321 (5MB)
23 22:55:09.943031 progress 0% (0MB)
24 22:55:09.944828 progress 5% (0MB)
25 22:55:09.946425 progress 10% (0MB)
26 22:55:09.947866 progress 15% (0MB)
27 22:55:09.949458 progress 20% (1MB)
28 22:55:09.950836 progress 25% (1MB)
29 22:55:09.952450 progress 30% (1MB)
30 22:55:09.954081 progress 35% (1MB)
31 22:55:09.955438 progress 40% (2MB)
32 22:55:09.956952 progress 45% (2MB)
33 22:55:09.958405 progress 50% (2MB)
34 22:55:09.959921 progress 55% (2MB)
35 22:55:09.961326 progress 60% (3MB)
36 22:55:09.962841 progress 65% (3MB)
37 22:55:09.964399 progress 70% (3MB)
38 22:55:09.965797 progress 75% (4MB)
39 22:55:09.967307 progress 80% (4MB)
40 22:55:09.968696 progress 85% (4MB)
41 22:55:09.970200 progress 90% (4MB)
42 22:55:09.971701 progress 95% (5MB)
43 22:55:09.973115 progress 100% (5MB)
44 22:55:09.973306 5MB downloaded in 0.32s (16.99MB/s)
45 22:55:09.973458 end: 1.1.1 http-download (duration 00:00:00) [common]
47 22:55:09.973694 end: 1.1 download-retry (duration 00:00:00) [common]
48 22:55:09.973781 start: 1.2 download-retry (timeout 00:10:00) [common]
49 22:55:09.973866 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 22:55:09.974000 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1314-g1ab0ac1d7e2e3/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 22:55:09.974071 saving as /var/lib/lava/dispatcher/tmp/10597661/tftp-deploy-zpr5obgr/kernel/Image
52 22:55:09.974132 total size: 45746688 (43MB)
53 22:55:09.974192 No compression specified
54 22:55:09.975285 progress 0% (0MB)
55 22:55:09.986711 progress 5% (2MB)
56 22:55:09.998306 progress 10% (4MB)
57 22:55:10.010074 progress 15% (6MB)
58 22:55:10.022043 progress 20% (8MB)
59 22:55:10.033828 progress 25% (10MB)
60 22:55:10.045322 progress 30% (13MB)
61 22:55:10.057281 progress 35% (15MB)
62 22:55:10.069078 progress 40% (17MB)
63 22:55:10.080781 progress 45% (19MB)
64 22:55:10.092287 progress 50% (21MB)
65 22:55:10.103738 progress 55% (24MB)
66 22:55:10.115487 progress 60% (26MB)
67 22:55:10.127275 progress 65% (28MB)
68 22:55:10.139115 progress 70% (30MB)
69 22:55:10.151210 progress 75% (32MB)
70 22:55:10.163268 progress 80% (34MB)
71 22:55:10.175054 progress 85% (37MB)
72 22:55:10.186912 progress 90% (39MB)
73 22:55:10.198376 progress 95% (41MB)
74 22:55:10.209884 progress 100% (43MB)
75 22:55:10.210050 43MB downloaded in 0.24s (184.93MB/s)
76 22:55:10.210206 end: 1.2.1 http-download (duration 00:00:00) [common]
78 22:55:10.210446 end: 1.2 download-retry (duration 00:00:00) [common]
79 22:55:10.210537 start: 1.3 download-retry (timeout 00:09:59) [common]
80 22:55:10.210626 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 22:55:10.210761 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1314-g1ab0ac1d7e2e3/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 22:55:10.210832 saving as /var/lib/lava/dispatcher/tmp/10597661/tftp-deploy-zpr5obgr/dtb/mt8192-asurada-spherion-r0.dtb
83 22:55:10.210893 total size: 46924 (0MB)
84 22:55:10.210952 No compression specified
85 22:55:10.212057 progress 69% (0MB)
86 22:55:10.212331 progress 100% (0MB)
87 22:55:10.212486 0MB downloaded in 0.00s (28.13MB/s)
88 22:55:10.212650 end: 1.3.1 http-download (duration 00:00:00) [common]
90 22:55:10.212879 end: 1.3 download-retry (duration 00:00:00) [common]
91 22:55:10.212965 start: 1.4 download-retry (timeout 00:09:59) [common]
92 22:55:10.213047 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 22:55:10.213158 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20230527.0/arm64/full.rootfs.tar.xz
94 22:55:10.213227 saving as /var/lib/lava/dispatcher/tmp/10597661/tftp-deploy-zpr5obgr/nfsrootfs/full.rootfs.tar
95 22:55:10.213288 total size: 195125384 (186MB)
96 22:55:10.213347 Using unxz to decompress xz
97 22:55:10.216785 progress 0% (0MB)
98 22:55:10.772161 progress 5% (9MB)
99 22:55:11.271065 progress 10% (18MB)
100 22:55:11.850244 progress 15% (27MB)
101 22:55:12.126561 progress 20% (37MB)
102 22:55:12.576882 progress 25% (46MB)
103 22:55:13.146118 progress 30% (55MB)
104 22:55:13.703832 progress 35% (65MB)
105 22:55:14.254628 progress 40% (74MB)
106 22:55:14.822706 progress 45% (83MB)
107 22:55:15.430729 progress 50% (93MB)
108 22:55:16.025708 progress 55% (102MB)
109 22:55:16.672922 progress 60% (111MB)
110 22:55:17.079718 progress 65% (120MB)
111 22:55:17.164380 progress 70% (130MB)
112 22:55:17.318238 progress 75% (139MB)
113 22:55:17.390997 progress 80% (148MB)
114 22:55:17.438053 progress 85% (158MB)
115 22:55:17.528727 progress 90% (167MB)
116 22:55:17.902092 progress 95% (176MB)
117 22:55:18.471116 progress 100% (186MB)
118 22:55:18.477181 186MB downloaded in 8.26s (22.52MB/s)
119 22:55:18.477479 end: 1.4.1 http-download (duration 00:00:08) [common]
121 22:55:18.477737 end: 1.4 download-retry (duration 00:00:08) [common]
122 22:55:18.477826 start: 1.5 download-retry (timeout 00:09:51) [common]
123 22:55:18.477914 start: 1.5.1 http-download (timeout 00:09:51) [common]
124 22:55:18.478051 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1314-g1ab0ac1d7e2e3/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 22:55:18.478121 saving as /var/lib/lava/dispatcher/tmp/10597661/tftp-deploy-zpr5obgr/modules/modules.tar
126 22:55:18.478182 total size: 8552396 (8MB)
127 22:55:18.478242 Using unxz to decompress xz
128 22:55:18.481677 progress 0% (0MB)
129 22:55:18.502454 progress 5% (0MB)
130 22:55:18.526197 progress 10% (0MB)
131 22:55:18.556855 progress 15% (1MB)
132 22:55:18.582518 progress 20% (1MB)
133 22:55:18.607538 progress 25% (2MB)
134 22:55:18.632742 progress 30% (2MB)
135 22:55:18.658745 progress 35% (2MB)
136 22:55:18.683811 progress 40% (3MB)
137 22:55:18.709356 progress 45% (3MB)
138 22:55:18.734499 progress 50% (4MB)
139 22:55:18.759317 progress 55% (4MB)
140 22:55:18.783395 progress 60% (4MB)
141 22:55:18.807992 progress 65% (5MB)
142 22:55:18.833317 progress 70% (5MB)
143 22:55:18.858102 progress 75% (6MB)
144 22:55:18.884850 progress 80% (6MB)
145 22:55:18.910824 progress 85% (6MB)
146 22:55:18.936364 progress 90% (7MB)
147 22:55:18.961191 progress 95% (7MB)
148 22:55:18.986301 progress 100% (8MB)
149 22:55:18.992797 8MB downloaded in 0.51s (15.85MB/s)
150 22:55:18.993079 end: 1.5.1 http-download (duration 00:00:01) [common]
152 22:55:18.993345 end: 1.5 download-retry (duration 00:00:01) [common]
153 22:55:18.993438 start: 1.6 prepare-tftp-overlay (timeout 00:09:51) [common]
154 22:55:18.993537 start: 1.6.1 extract-nfsrootfs (timeout 00:09:51) [common]
155 22:55:22.306887 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/10597661/extract-nfsrootfs-kuyzofdd
156 22:55:22.307098 end: 1.6.1 extract-nfsrootfs (duration 00:00:03) [common]
157 22:55:22.307213 start: 1.6.2 lava-overlay (timeout 00:09:47) [common]
158 22:55:22.307378 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10597661/lava-overlay-vsa1y883
159 22:55:22.307506 makedir: /var/lib/lava/dispatcher/tmp/10597661/lava-overlay-vsa1y883/lava-10597661/bin
160 22:55:22.307610 makedir: /var/lib/lava/dispatcher/tmp/10597661/lava-overlay-vsa1y883/lava-10597661/tests
161 22:55:22.307712 makedir: /var/lib/lava/dispatcher/tmp/10597661/lava-overlay-vsa1y883/lava-10597661/results
162 22:55:22.307815 Creating /var/lib/lava/dispatcher/tmp/10597661/lava-overlay-vsa1y883/lava-10597661/bin/lava-add-keys
163 22:55:22.307952 Creating /var/lib/lava/dispatcher/tmp/10597661/lava-overlay-vsa1y883/lava-10597661/bin/lava-add-sources
164 22:55:22.308076 Creating /var/lib/lava/dispatcher/tmp/10597661/lava-overlay-vsa1y883/lava-10597661/bin/lava-background-process-start
165 22:55:22.308198 Creating /var/lib/lava/dispatcher/tmp/10597661/lava-overlay-vsa1y883/lava-10597661/bin/lava-background-process-stop
166 22:55:22.308320 Creating /var/lib/lava/dispatcher/tmp/10597661/lava-overlay-vsa1y883/lava-10597661/bin/lava-common-functions
167 22:55:22.308441 Creating /var/lib/lava/dispatcher/tmp/10597661/lava-overlay-vsa1y883/lava-10597661/bin/lava-echo-ipv4
168 22:55:22.308812 Creating /var/lib/lava/dispatcher/tmp/10597661/lava-overlay-vsa1y883/lava-10597661/bin/lava-install-packages
169 22:55:22.308941 Creating /var/lib/lava/dispatcher/tmp/10597661/lava-overlay-vsa1y883/lava-10597661/bin/lava-installed-packages
170 22:55:22.309063 Creating /var/lib/lava/dispatcher/tmp/10597661/lava-overlay-vsa1y883/lava-10597661/bin/lava-os-build
171 22:55:22.309184 Creating /var/lib/lava/dispatcher/tmp/10597661/lava-overlay-vsa1y883/lava-10597661/bin/lava-probe-channel
172 22:55:22.309304 Creating /var/lib/lava/dispatcher/tmp/10597661/lava-overlay-vsa1y883/lava-10597661/bin/lava-probe-ip
173 22:55:22.309427 Creating /var/lib/lava/dispatcher/tmp/10597661/lava-overlay-vsa1y883/lava-10597661/bin/lava-target-ip
174 22:55:22.309547 Creating /var/lib/lava/dispatcher/tmp/10597661/lava-overlay-vsa1y883/lava-10597661/bin/lava-target-mac
175 22:55:22.309666 Creating /var/lib/lava/dispatcher/tmp/10597661/lava-overlay-vsa1y883/lava-10597661/bin/lava-target-storage
176 22:55:22.309790 Creating /var/lib/lava/dispatcher/tmp/10597661/lava-overlay-vsa1y883/lava-10597661/bin/lava-test-case
177 22:55:22.309909 Creating /var/lib/lava/dispatcher/tmp/10597661/lava-overlay-vsa1y883/lava-10597661/bin/lava-test-event
178 22:55:22.310027 Creating /var/lib/lava/dispatcher/tmp/10597661/lava-overlay-vsa1y883/lava-10597661/bin/lava-test-feedback
179 22:55:22.310145 Creating /var/lib/lava/dispatcher/tmp/10597661/lava-overlay-vsa1y883/lava-10597661/bin/lava-test-raise
180 22:55:22.310263 Creating /var/lib/lava/dispatcher/tmp/10597661/lava-overlay-vsa1y883/lava-10597661/bin/lava-test-reference
181 22:55:22.310384 Creating /var/lib/lava/dispatcher/tmp/10597661/lava-overlay-vsa1y883/lava-10597661/bin/lava-test-runner
182 22:55:22.310503 Creating /var/lib/lava/dispatcher/tmp/10597661/lava-overlay-vsa1y883/lava-10597661/bin/lava-test-set
183 22:55:22.310621 Creating /var/lib/lava/dispatcher/tmp/10597661/lava-overlay-vsa1y883/lava-10597661/bin/lava-test-shell
184 22:55:22.310743 Updating /var/lib/lava/dispatcher/tmp/10597661/lava-overlay-vsa1y883/lava-10597661/bin/lava-add-keys (debian)
185 22:55:22.310885 Updating /var/lib/lava/dispatcher/tmp/10597661/lava-overlay-vsa1y883/lava-10597661/bin/lava-add-sources (debian)
186 22:55:22.311036 Updating /var/lib/lava/dispatcher/tmp/10597661/lava-overlay-vsa1y883/lava-10597661/bin/lava-install-packages (debian)
187 22:55:22.311175 Updating /var/lib/lava/dispatcher/tmp/10597661/lava-overlay-vsa1y883/lava-10597661/bin/lava-installed-packages (debian)
188 22:55:22.311307 Updating /var/lib/lava/dispatcher/tmp/10597661/lava-overlay-vsa1y883/lava-10597661/bin/lava-os-build (debian)
189 22:55:22.311428 Creating /var/lib/lava/dispatcher/tmp/10597661/lava-overlay-vsa1y883/lava-10597661/environment
190 22:55:22.311525 LAVA metadata
191 22:55:22.311596 - LAVA_JOB_ID=10597661
192 22:55:22.311659 - LAVA_DISPATCHER_IP=192.168.201.1
193 22:55:22.311756 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:47) [common]
194 22:55:22.311821 skipped lava-vland-overlay
195 22:55:22.311894 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 22:55:22.311972 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:47) [common]
197 22:55:22.312033 skipped lava-multinode-overlay
198 22:55:22.312105 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 22:55:22.312182 start: 1.6.2.3 test-definition (timeout 00:09:47) [common]
200 22:55:22.312253 Loading test definitions
201 22:55:22.312342 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:47) [common]
202 22:55:22.312414 Using /lava-10597661 at stage 0
203 22:55:22.312752 uuid=10597661_1.6.2.3.1 testdef=None
204 22:55:22.312841 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 22:55:22.312926 start: 1.6.2.3.2 test-overlay (timeout 00:09:47) [common]
206 22:55:22.313364 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 22:55:22.313586 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:47) [common]
209 22:55:22.314126 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 22:55:22.314352 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:47) [common]
212 22:55:22.314875 runner path: /var/lib/lava/dispatcher/tmp/10597661/lava-overlay-vsa1y883/lava-10597661/0/tests/0_timesync-off test_uuid 10597661_1.6.2.3.1
213 22:55:22.315024 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 22:55:22.315246 start: 1.6.2.3.5 git-repo-action (timeout 00:09:47) [common]
216 22:55:22.315319 Using /lava-10597661 at stage 0
217 22:55:22.315415 Fetching tests from https://github.com/kernelci/test-definitions.git
218 22:55:22.315491 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/10597661/lava-overlay-vsa1y883/lava-10597661/0/tests/1_kselftest-alsa'
219 22:55:24.703644 Running '/usr/bin/git checkout kernelci.org
220 22:55:24.848419 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/10597661/lava-overlay-vsa1y883/lava-10597661/0/tests/1_kselftest-alsa/automated/linux/kselftest/kselftest.yaml
221 22:55:24.849226 uuid=10597661_1.6.2.3.5 testdef=None
222 22:55:24.849392 end: 1.6.2.3.5 git-repo-action (duration 00:00:03) [common]
224 22:55:24.849676 start: 1.6.2.3.6 test-overlay (timeout 00:09:45) [common]
225 22:55:24.850410 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 22:55:24.850648 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:45) [common]
228 22:55:24.851605 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 22:55:24.851840 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:45) [common]
231 22:55:24.852860 runner path: /var/lib/lava/dispatcher/tmp/10597661/lava-overlay-vsa1y883/lava-10597661/0/tests/1_kselftest-alsa test_uuid 10597661_1.6.2.3.5
232 22:55:24.852955 BOARD='mt8192-asurada-spherion-r0'
233 22:55:24.853022 BRANCH='cip'
234 22:55:24.853083 SKIPFILE='/dev/null'
235 22:55:24.853147 SKIP_INSTALL='True'
236 22:55:24.853206 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1314-g1ab0ac1d7e2e3/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 22:55:24.853265 TST_CASENAME=''
238 22:55:24.853322 TST_CMDFILES='alsa'
239 22:55:24.853543 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 22:55:24.853750 Creating lava-test-runner.conf files
242 22:55:24.853815 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10597661/lava-overlay-vsa1y883/lava-10597661/0 for stage 0
243 22:55:24.853912 - 0_timesync-off
244 22:55:24.853998 - 1_kselftest-alsa
245 22:55:24.854109 end: 1.6.2.3 test-definition (duration 00:00:03) [common]
246 22:55:24.854198 start: 1.6.2.4 compress-overlay (timeout 00:09:45) [common]
247 22:55:32.376009 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 22:55:32.376166 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:37) [common]
249 22:55:32.376344 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 22:55:32.376486 end: 1.6.2 lava-overlay (duration 00:00:10) [common]
251 22:55:32.376624 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:37) [common]
252 22:55:32.537628 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 22:55:32.538000 start: 1.6.4 extract-modules (timeout 00:09:37) [common]
254 22:55:32.538119 extracting modules file /var/lib/lava/dispatcher/tmp/10597661/tftp-deploy-zpr5obgr/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10597661/extract-nfsrootfs-kuyzofdd
255 22:55:32.743028 extracting modules file /var/lib/lava/dispatcher/tmp/10597661/tftp-deploy-zpr5obgr/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10597661/extract-overlay-ramdisk-w_gg4u0b/ramdisk
256 22:55:32.949759 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 22:55:32.949933 start: 1.6.5 apply-overlay-tftp (timeout 00:09:37) [common]
258 22:55:32.950037 [common] Applying overlay to NFS
259 22:55:32.950108 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10597661/compress-overlay-32g5ies0/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10597661/extract-nfsrootfs-kuyzofdd
260 22:55:33.844935 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 22:55:33.845106 start: 1.6.6 configure-preseed-file (timeout 00:09:36) [common]
262 22:55:33.845206 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 22:55:33.845303 start: 1.6.7 compress-ramdisk (timeout 00:09:36) [common]
264 22:55:33.845388 Building ramdisk /var/lib/lava/dispatcher/tmp/10597661/extract-overlay-ramdisk-w_gg4u0b/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10597661/extract-overlay-ramdisk-w_gg4u0b/ramdisk
265 22:55:34.173331 >> 128929 blocks
266 22:55:36.152665 rename /var/lib/lava/dispatcher/tmp/10597661/extract-overlay-ramdisk-w_gg4u0b/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10597661/tftp-deploy-zpr5obgr/ramdisk/ramdisk.cpio.gz
267 22:55:36.153085 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 22:55:36.153227 start: 1.6.8 prepare-kernel (timeout 00:09:34) [common]
269 22:55:36.153333 start: 1.6.8.1 prepare-fit (timeout 00:09:34) [common]
270 22:55:36.153442 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10597661/tftp-deploy-zpr5obgr/kernel/Image'
271 22:55:48.138338 Returned 0 in 11 seconds
272 22:55:48.238971 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10597661/tftp-deploy-zpr5obgr/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10597661/tftp-deploy-zpr5obgr/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10597661/tftp-deploy-zpr5obgr/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10597661/tftp-deploy-zpr5obgr/kernel/image.itb
273 22:55:48.555196 output: FIT description: Kernel Image image with one or more FDT blobs
274 22:55:48.555563 output: Created: Mon Jun 5 23:55:48 2023
275 22:55:48.555645 output: Image 0 (kernel-1)
276 22:55:48.555714 output: Description:
277 22:55:48.555779 output: Created: Mon Jun 5 23:55:48 2023
278 22:55:48.555841 output: Type: Kernel Image
279 22:55:48.555900 output: Compression: lzma compressed
280 22:55:48.555959 output: Data Size: 10085945 Bytes = 9849.56 KiB = 9.62 MiB
281 22:55:48.556020 output: Architecture: AArch64
282 22:55:48.556079 output: OS: Linux
283 22:55:48.556143 output: Load Address: 0x00000000
284 22:55:48.556205 output: Entry Point: 0x00000000
285 22:55:48.556262 output: Hash algo: crc32
286 22:55:48.556317 output: Hash value: b2943ff2
287 22:55:48.556371 output: Image 1 (fdt-1)
288 22:55:48.556425 output: Description: mt8192-asurada-spherion-r0
289 22:55:48.556478 output: Created: Mon Jun 5 23:55:48 2023
290 22:55:48.556563 output: Type: Flat Device Tree
291 22:55:48.556632 output: Compression: uncompressed
292 22:55:48.556688 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
293 22:55:48.556746 output: Architecture: AArch64
294 22:55:48.556800 output: Hash algo: crc32
295 22:55:48.556854 output: Hash value: 1df858fa
296 22:55:48.556908 output: Image 2 (ramdisk-1)
297 22:55:48.556962 output: Description: unavailable
298 22:55:48.557015 output: Created: Mon Jun 5 23:55:48 2023
299 22:55:48.557069 output: Type: RAMDisk Image
300 22:55:48.557122 output: Compression: Unknown Compression
301 22:55:48.557175 output: Data Size: 18608845 Bytes = 18172.70 KiB = 17.75 MiB
302 22:55:48.557229 output: Architecture: AArch64
303 22:55:48.557290 output: OS: Linux
304 22:55:48.557345 output: Load Address: unavailable
305 22:55:48.557399 output: Entry Point: unavailable
306 22:55:48.557452 output: Hash algo: crc32
307 22:55:48.557505 output: Hash value: 620b547f
308 22:55:48.557559 output: Default Configuration: 'conf-1'
309 22:55:48.557612 output: Configuration 0 (conf-1)
310 22:55:48.557666 output: Description: mt8192-asurada-spherion-r0
311 22:55:48.557719 output: Kernel: kernel-1
312 22:55:48.557773 output: Init Ramdisk: ramdisk-1
313 22:55:48.557826 output: FDT: fdt-1
314 22:55:48.557886 output: Loadables: kernel-1
315 22:55:48.557939 output:
316 22:55:48.558132 end: 1.6.8.1 prepare-fit (duration 00:00:12) [common]
317 22:55:48.558233 end: 1.6.8 prepare-kernel (duration 00:00:12) [common]
318 22:55:48.558335 end: 1.6 prepare-tftp-overlay (duration 00:00:30) [common]
319 22:55:48.558439 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:21) [common]
320 22:55:48.558522 No LXC device requested
321 22:55:48.558602 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 22:55:48.558689 start: 1.8 deploy-device-env (timeout 00:09:21) [common]
323 22:55:48.558771 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 22:55:48.558841 Checking files for TFTP limit of 4294967296 bytes.
325 22:55:48.559331 end: 1 tftp-deploy (duration 00:00:39) [common]
326 22:55:48.559445 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 22:55:48.559537 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 22:55:48.559670 substitutions:
329 22:55:48.559739 - {DTB}: 10597661/tftp-deploy-zpr5obgr/dtb/mt8192-asurada-spherion-r0.dtb
330 22:55:48.559804 - {INITRD}: 10597661/tftp-deploy-zpr5obgr/ramdisk/ramdisk.cpio.gz
331 22:55:48.559865 - {KERNEL}: 10597661/tftp-deploy-zpr5obgr/kernel/Image
332 22:55:48.559924 - {LAVA_MAC}: None
333 22:55:48.559981 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/10597661/extract-nfsrootfs-kuyzofdd
334 22:55:48.560038 - {NFS_SERVER_IP}: 192.168.201.1
335 22:55:48.560095 - {PRESEED_CONFIG}: None
336 22:55:48.560151 - {PRESEED_LOCAL}: None
337 22:55:48.560217 - {RAMDISK}: 10597661/tftp-deploy-zpr5obgr/ramdisk/ramdisk.cpio.gz
338 22:55:48.560273 - {ROOT_PART}: None
339 22:55:48.560329 - {ROOT}: None
340 22:55:48.560384 - {SERVER_IP}: 192.168.201.1
341 22:55:48.560438 - {TEE}: None
342 22:55:48.560493 Parsed boot commands:
343 22:55:48.560595 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 22:55:48.560780 Parsed boot commands: tftpboot 192.168.201.1 10597661/tftp-deploy-zpr5obgr/kernel/image.itb 10597661/tftp-deploy-zpr5obgr/kernel/cmdline
345 22:55:48.560872 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 22:55:48.560956 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 22:55:48.561048 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 22:55:48.561134 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 22:55:48.561208 Not connected, no need to disconnect.
350 22:55:48.561288 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 22:55:48.561371 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 22:55:48.561440 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-9'
353 22:55:48.564736 Setting prompt string to ['lava-test: # ']
354 22:55:48.565092 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 22:55:48.565203 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 22:55:48.565302 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 22:55:48.565395 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 22:55:48.565605 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=reboot'
359 22:55:53.698101 >> Command sent successfully.
360 22:55:53.708081 Returned 0 in 5 seconds
361 22:55:53.809022 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 22:55:53.809467 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 22:55:53.809602 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 22:55:53.809700 Setting prompt string to 'Starting depthcharge on Spherion...'
366 22:55:53.809786 Changing prompt to 'Starting depthcharge on Spherion...'
367 22:55:53.809873 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 22:55:53.810336 [Enter `^Ec?' for help]
369 22:55:53.974496
370 22:55:53.975024
371 22:55:53.975387 F0: 102B 0000
372 22:55:53.975819
373 22:55:53.976231 F3: 1001 0000 [0200]
374 22:55:53.976744
375 22:55:53.977429 F3: 1001 0000
376 22:55:53.977793
377 22:55:53.978191 F7: 102D 0000
378 22:55:53.978587
379 22:55:53.980688 F1: 0000 0000
380 22:55:53.981131
381 22:55:53.981678 V0: 0000 0000 [0001]
382 22:55:53.982099
383 22:55:53.984138 00: 0007 8000
384 22:55:53.984620
385 22:55:53.985059 01: 0000 0000
386 22:55:53.985479
387 22:55:53.985886 BP: 0C00 0209 [0000]
388 22:55:53.987354
389 22:55:53.987791 G0: 1182 0000
390 22:55:53.988262
391 22:55:53.988766 EC: 0000 0021 [4000]
392 22:55:53.989184
393 22:55:53.991213 S7: 0000 0000 [0000]
394 22:55:53.991782
395 22:55:53.992201 CC: 0000 0000 [0001]
396 22:55:53.992748
397 22:55:53.994880 T0: 0000 0040 [010F]
398 22:55:53.995416
399 22:55:53.995786 Jump to BL
400 22:55:53.996149
401 22:55:54.020595
402 22:55:54.021259
403 22:55:54.021815
404 22:55:54.028054 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 22:55:54.031764 ARM64: Exception handlers installed.
406 22:55:54.035554 ARM64: Testing exception
407 22:55:54.039278 ARM64: Done test exception
408 22:55:54.046498 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 22:55:54.056957 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 22:55:54.060570 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 22:55:54.071927 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 22:55:54.078680 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 22:55:54.085188 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 22:55:54.096977 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 22:55:54.103748 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 22:55:54.123288 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 22:55:54.127242 WDT: Last reset was cold boot
418 22:55:54.130221 SPI1(PAD0) initialized at 2873684 Hz
419 22:55:54.133699 SPI5(PAD0) initialized at 992727 Hz
420 22:55:54.136737 VBOOT: Loading verstage.
421 22:55:54.143717 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 22:55:54.146843 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 22:55:54.150259 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 22:55:54.153303 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 22:55:54.160866 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 22:55:54.167393 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 22:55:54.178636 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
428 22:55:54.179162
429 22:55:54.179506
430 22:55:54.188420 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 22:55:54.191662 ARM64: Exception handlers installed.
432 22:55:54.195140 ARM64: Testing exception
433 22:55:54.195604 ARM64: Done test exception
434 22:55:54.201634 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 22:55:54.205122 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 22:55:54.219316 Probing TPM: . done!
437 22:55:54.219854 TPM ready after 0 ms
438 22:55:54.226222 Connected to device vid:did:rid of 1ae0:0028:00
439 22:55:54.236742 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
440 22:55:54.274456 Initialized TPM device CR50 revision 0
441 22:55:54.286421 tlcl_send_startup: Startup return code is 0
442 22:55:54.286860 TPM: setup succeeded
443 22:55:54.298922 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 22:55:54.307789 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 22:55:54.314445 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 22:55:54.326890 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 22:55:54.329848 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 22:55:54.333356 in-header: 03 07 00 00 08 00 00 00
449 22:55:54.336767 in-data: aa e4 47 04 13 02 00 00
450 22:55:54.340149 Chrome EC: UHEPI supported
451 22:55:54.346626 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 22:55:54.349913 in-header: 03 ad 00 00 08 00 00 00
453 22:55:54.353209 in-data: 00 20 20 08 00 00 00 00
454 22:55:54.353641 Phase 1
455 22:55:54.356639 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 22:55:54.362995 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 22:55:54.369376 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 22:55:54.373066 Recovery requested (1009000e)
459 22:55:54.376958 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 22:55:54.385435 tlcl_extend: response is 0
461 22:55:54.394309 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 22:55:54.399083 tlcl_extend: response is 0
463 22:55:54.405627 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 22:55:54.426361 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
465 22:55:54.432634 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 22:55:54.433222
467 22:55:54.433605
468 22:55:54.443739 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 22:55:54.446846 ARM64: Exception handlers installed.
470 22:55:54.447357 ARM64: Testing exception
471 22:55:54.450146 ARM64: Done test exception
472 22:55:54.472343 pmic_efuse_setting: Set efuses in 11 msecs
473 22:55:54.475981 pmwrap_interface_init: Select PMIF_VLD_RDY
474 22:55:54.479444 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 22:55:54.486234 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 22:55:54.489919 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 22:55:54.496748 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 22:55:54.499488 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 22:55:54.506941 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 22:55:54.510118 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 22:55:54.512992 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 22:55:54.519801 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 22:55:54.522865 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 22:55:54.529517 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 22:55:54.533069 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 22:55:54.536389 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 22:55:54.543109 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 22:55:54.550015 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 22:55:54.556228 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 22:55:54.559563 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 22:55:54.566505 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 22:55:54.573564 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 22:55:54.576695 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 22:55:54.582931 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 22:55:54.590139 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 22:55:54.593768 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 22:55:54.601344 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 22:55:54.604614 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 22:55:54.611586 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 22:55:54.615440 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 22:55:54.621892 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 22:55:54.625097 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 22:55:54.629001 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 22:55:54.635770 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 22:55:54.639463 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 22:55:54.646180 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 22:55:54.649554 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 22:55:54.656280 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 22:55:54.659424 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 22:55:54.666349 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 22:55:54.668926 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 22:55:54.675746 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 22:55:54.679347 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 22:55:54.683173 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 22:55:54.687187 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 22:55:54.693750 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 22:55:54.696742 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 22:55:54.700689 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 22:55:54.707414 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 22:55:54.710347 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 22:55:54.713870 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 22:55:54.717081 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 22:55:54.723652 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 22:55:54.727255 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 22:55:54.733647 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 22:55:54.743931 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 22:55:54.747292 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 22:55:54.757048 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 22:55:54.763798 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 22:55:54.767054 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 22:55:54.773396 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 22:55:54.777149 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 22:55:54.784236 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6c, sec=0x2e
534 22:55:54.790621 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 22:55:54.794175 [RTC]rtc_osc_init,62: osc32con val = 0xde6c
536 22:55:54.800672 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 22:55:54.808563 [RTC]rtc_get_frequency_meter,154: input=15, output=836
538 22:55:54.818288 [RTC]rtc_get_frequency_meter,154: input=7, output=709
539 22:55:54.827582 [RTC]rtc_get_frequency_meter,154: input=11, output=772
540 22:55:54.837206 [RTC]rtc_get_frequency_meter,154: input=13, output=804
541 22:55:54.846581 [RTC]rtc_get_frequency_meter,154: input=12, output=789
542 22:55:54.856059 [RTC]rtc_get_frequency_meter,154: input=12, output=788
543 22:55:54.865644 [RTC]rtc_get_frequency_meter,154: input=13, output=803
544 22:55:54.869260 [RTC]rtc_eosc_cali,47: left: 12, middle: 12, right: 13
545 22:55:54.876205 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6c
546 22:55:54.879146 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 22:55:54.882648 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
548 22:55:54.889298 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 22:55:54.892886 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
550 22:55:54.895804 ADC[4]: Raw value=903031 ID=7
551 22:55:54.896246 ADC[3]: Raw value=213282 ID=1
552 22:55:54.899030 RAM Code: 0x71
553 22:55:54.902666 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 22:55:54.909630 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 22:55:54.915624 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
556 22:55:54.922712 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
557 22:55:54.925629 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 22:55:54.929424 in-header: 03 07 00 00 08 00 00 00
559 22:55:54.932505 in-data: aa e4 47 04 13 02 00 00
560 22:55:54.935588 Chrome EC: UHEPI supported
561 22:55:54.942325 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 22:55:54.945319 in-header: 03 dd 00 00 08 00 00 00
563 22:55:54.949457 in-data: 90 20 60 08 00 00 00 00
564 22:55:54.952468 MRC: failed to locate region type 0.
565 22:55:54.958907 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 22:55:54.962387 DRAM-K: Running full calibration
567 22:55:54.969021 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
568 22:55:54.969468 header.status = 0x0
569 22:55:54.972156 header.version = 0x6 (expected: 0x6)
570 22:55:54.975713 header.size = 0xd00 (expected: 0xd00)
571 22:55:54.978931 header.flags = 0x0
572 22:55:54.985388 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 22:55:55.002477 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
574 22:55:55.009200 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 22:55:55.012191 dram_init: ddr_geometry: 2
576 22:55:55.015901 [EMI] MDL number = 2
577 22:55:55.016337 [EMI] Get MDL freq = 0
578 22:55:55.018886 dram_init: ddr_type: 0
579 22:55:55.019355 is_discrete_lpddr4: 1
580 22:55:55.022306 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 22:55:55.022784
582 22:55:55.023131
583 22:55:55.025676 [Bian_co] ETT version 0.0.0.1
584 22:55:55.032660 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
585 22:55:55.033185
586 22:55:55.035682 dramc_set_vcore_voltage set vcore to 650000
587 22:55:55.039328 Read voltage for 800, 4
588 22:55:55.039759 Vio18 = 0
589 22:55:55.040102 Vcore = 650000
590 22:55:55.040420 Vdram = 0
591 22:55:55.042221 Vddq = 0
592 22:55:55.042651 Vmddr = 0
593 22:55:55.045534 dram_init: config_dvfs: 1
594 22:55:55.048950 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 22:55:55.056092 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 22:55:55.058816 [SwImpedanceCal] DRVP=8, DRVN=16, ODTN=9
597 22:55:55.062798 freq_region=0, Reg: DRVP=8, DRVN=16, ODTN=9
598 22:55:55.065780 [SwImpedanceCal] DRVP=14, DRVN=24, ODTN=9
599 22:55:55.068890 freq_region=1, Reg: DRVP=14, DRVN=24, ODTN=9
600 22:55:55.072873 MEM_TYPE=3, freq_sel=18
601 22:55:55.076108 sv_algorithm_assistance_LP4_1600
602 22:55:55.079479 ============ PULL DRAM RESETB DOWN ============
603 22:55:55.082606 ========== PULL DRAM RESETB DOWN end =========
604 22:55:55.088878 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 22:55:55.092259 ===================================
606 22:55:55.095721 LPDDR4 DRAM CONFIGURATION
607 22:55:55.099040 ===================================
608 22:55:55.099474 EX_ROW_EN[0] = 0x0
609 22:55:55.102223 EX_ROW_EN[1] = 0x0
610 22:55:55.102657 LP4Y_EN = 0x0
611 22:55:55.105636 WORK_FSP = 0x0
612 22:55:55.106069 WL = 0x2
613 22:55:55.109264 RL = 0x2
614 22:55:55.109692 BL = 0x2
615 22:55:55.112097 RPST = 0x0
616 22:55:55.112685 RD_PRE = 0x0
617 22:55:55.115754 WR_PRE = 0x1
618 22:55:55.116195 WR_PST = 0x0
619 22:55:55.119049 DBI_WR = 0x0
620 22:55:55.119491 DBI_RD = 0x0
621 22:55:55.122141 OTF = 0x1
622 22:55:55.125877 ===================================
623 22:55:55.129218 ===================================
624 22:55:55.129839 ANA top config
625 22:55:55.132814 ===================================
626 22:55:55.135750 DLL_ASYNC_EN = 0
627 22:55:55.138501 ALL_SLAVE_EN = 1
628 22:55:55.142087 NEW_RANK_MODE = 1
629 22:55:55.142537 DLL_IDLE_MODE = 1
630 22:55:55.145144 LP45_APHY_COMB_EN = 1
631 22:55:55.148758 TX_ODT_DIS = 1
632 22:55:55.152169 NEW_8X_MODE = 1
633 22:55:55.155872 ===================================
634 22:55:55.159063 ===================================
635 22:55:55.162268 data_rate = 1600
636 22:55:55.162704 CKR = 1
637 22:55:55.165686 DQ_P2S_RATIO = 8
638 22:55:55.169074 ===================================
639 22:55:55.172139 CA_P2S_RATIO = 8
640 22:55:55.175768 DQ_CA_OPEN = 0
641 22:55:55.178501 DQ_SEMI_OPEN = 0
642 22:55:55.182188 CA_SEMI_OPEN = 0
643 22:55:55.182912 CA_FULL_RATE = 0
644 22:55:55.185194 DQ_CKDIV4_EN = 1
645 22:55:55.188677 CA_CKDIV4_EN = 1
646 22:55:55.191947 CA_PREDIV_EN = 0
647 22:55:55.195165 PH8_DLY = 0
648 22:55:55.198389 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 22:55:55.199021 DQ_AAMCK_DIV = 4
650 22:55:55.201722 CA_AAMCK_DIV = 4
651 22:55:55.205330 CA_ADMCK_DIV = 4
652 22:55:55.209039 DQ_TRACK_CA_EN = 0
653 22:55:55.211909 CA_PICK = 800
654 22:55:55.215726 CA_MCKIO = 800
655 22:55:55.216161 MCKIO_SEMI = 0
656 22:55:55.218736 PLL_FREQ = 3068
657 22:55:55.221943 DQ_UI_PI_RATIO = 32
658 22:55:55.225386 CA_UI_PI_RATIO = 0
659 22:55:55.228352 ===================================
660 22:55:55.231989 ===================================
661 22:55:55.235303 memory_type:LPDDR4
662 22:55:55.235777 GP_NUM : 10
663 22:55:55.238341 SRAM_EN : 1
664 22:55:55.241969 MD32_EN : 0
665 22:55:55.245238 ===================================
666 22:55:55.245695 [ANA_INIT] >>>>>>>>>>>>>>
667 22:55:55.248495 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 22:55:55.252268 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 22:55:55.255344 ===================================
670 22:55:55.258602 data_rate = 1600,PCW = 0X7600
671 22:55:55.261547 ===================================
672 22:55:55.264862 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 22:55:55.271574 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 22:55:55.274888 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 22:55:55.281265 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 22:55:55.284863 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 22:55:55.288112 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 22:55:55.291134 [ANA_INIT] flow start
679 22:55:55.291223 [ANA_INIT] PLL >>>>>>>>
680 22:55:55.294556 [ANA_INIT] PLL <<<<<<<<
681 22:55:55.297655 [ANA_INIT] MIDPI >>>>>>>>
682 22:55:55.297760 [ANA_INIT] MIDPI <<<<<<<<
683 22:55:55.301089 [ANA_INIT] DLL >>>>>>>>
684 22:55:55.304409 [ANA_INIT] flow end
685 22:55:55.307497 ============ LP4 DIFF to SE enter ============
686 22:55:55.310939 ============ LP4 DIFF to SE exit ============
687 22:55:55.314736 [ANA_INIT] <<<<<<<<<<<<<
688 22:55:55.317718 [Flow] Enable top DCM control >>>>>
689 22:55:55.321243 [Flow] Enable top DCM control <<<<<
690 22:55:55.324845 Enable DLL master slave shuffle
691 22:55:55.327882 ==============================================================
692 22:55:55.330957 Gating Mode config
693 22:55:55.337695 ==============================================================
694 22:55:55.338036 Config description:
695 22:55:55.348059 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 22:55:55.354619 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 22:55:55.357804 SELPH_MODE 0: By rank 1: By Phase
698 22:55:55.364229 ==============================================================
699 22:55:55.367969 GAT_TRACK_EN = 1
700 22:55:55.371526 RX_GATING_MODE = 2
701 22:55:55.374549 RX_GATING_TRACK_MODE = 2
702 22:55:55.377864 SELPH_MODE = 1
703 22:55:55.381045 PICG_EARLY_EN = 1
704 22:55:55.384184 VALID_LAT_VALUE = 1
705 22:55:55.388154 ==============================================================
706 22:55:55.390999 Enter into Gating configuration >>>>
707 22:55:55.394250 Exit from Gating configuration <<<<
708 22:55:55.397666 Enter into DVFS_PRE_config >>>>>
709 22:55:55.407754 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 22:55:55.411048 Exit from DVFS_PRE_config <<<<<
711 22:55:55.414555 Enter into PICG configuration >>>>
712 22:55:55.417740 Exit from PICG configuration <<<<
713 22:55:55.420771 [RX_INPUT] configuration >>>>>
714 22:55:55.424458 [RX_INPUT] configuration <<<<<
715 22:55:55.431429 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 22:55:55.434675 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 22:55:55.441819 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 22:55:55.448957 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 22:55:55.452676 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 22:55:55.459935 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 22:55:55.463734 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 22:55:55.467228 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 22:55:55.470533 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 22:55:55.474196 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 22:55:55.481480 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 22:55:55.485249 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 22:55:55.488415 ===================================
728 22:55:55.488962 LPDDR4 DRAM CONFIGURATION
729 22:55:55.492226 ===================================
730 22:55:55.496002 EX_ROW_EN[0] = 0x0
731 22:55:55.496583 EX_ROW_EN[1] = 0x0
732 22:55:55.500062 LP4Y_EN = 0x0
733 22:55:55.500714 WORK_FSP = 0x0
734 22:55:55.503449 WL = 0x2
735 22:55:55.503931 RL = 0x2
736 22:55:55.506418 BL = 0x2
737 22:55:55.506852 RPST = 0x0
738 22:55:55.510400 RD_PRE = 0x0
739 22:55:55.510873 WR_PRE = 0x1
740 22:55:55.513744 WR_PST = 0x0
741 22:55:55.514189 DBI_WR = 0x0
742 22:55:55.517639 DBI_RD = 0x0
743 22:55:55.518116 OTF = 0x1
744 22:55:55.521789 ===================================
745 22:55:55.524956 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 22:55:55.528704 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 22:55:55.536017 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 22:55:55.536499 ===================================
749 22:55:55.539697 LPDDR4 DRAM CONFIGURATION
750 22:55:55.543090 ===================================
751 22:55:55.546409 EX_ROW_EN[0] = 0x10
752 22:55:55.546840 EX_ROW_EN[1] = 0x0
753 22:55:55.550473 LP4Y_EN = 0x0
754 22:55:55.550907 WORK_FSP = 0x0
755 22:55:55.551248 WL = 0x2
756 22:55:55.553759 RL = 0x2
757 22:55:55.554353 BL = 0x2
758 22:55:55.557499 RPST = 0x0
759 22:55:55.557932 RD_PRE = 0x0
760 22:55:55.561989 WR_PRE = 0x1
761 22:55:55.562421 WR_PST = 0x0
762 22:55:55.565321 DBI_WR = 0x0
763 22:55:55.565753 DBI_RD = 0x0
764 22:55:55.568654 OTF = 0x1
765 22:55:55.572319 ===================================
766 22:55:55.575674 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 22:55:55.581168 nWR fixed to 40
768 22:55:55.581769 [ModeRegInit_LP4] CH0 RK0
769 22:55:55.584942 [ModeRegInit_LP4] CH0 RK1
770 22:55:55.588964 [ModeRegInit_LP4] CH1 RK0
771 22:55:55.589392 [ModeRegInit_LP4] CH1 RK1
772 22:55:55.593138 match AC timing 13
773 22:55:55.596859 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
774 22:55:55.599614 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 22:55:55.603358 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 22:55:55.609777 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 22:55:55.612917 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 22:55:55.616302 [EMI DOE] emi_dcm 0
779 22:55:55.619885 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 22:55:55.620317 ==
781 22:55:55.623311 Dram Type= 6, Freq= 0, CH_0, rank 0
782 22:55:55.626345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
783 22:55:55.626780 ==
784 22:55:55.633772 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 22:55:55.640734 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 22:55:55.648111 [CA 0] Center 37 (6~68) winsize 63
787 22:55:55.651709 [CA 1] Center 37 (6~68) winsize 63
788 22:55:55.654590 [CA 2] Center 34 (4~65) winsize 62
789 22:55:55.659364 [CA 3] Center 34 (4~65) winsize 62
790 22:55:55.661488 [CA 4] Center 33 (3~64) winsize 62
791 22:55:55.665535 [CA 5] Center 33 (3~64) winsize 62
792 22:55:55.665970
793 22:55:55.668976 [CmdBusTrainingLP45] Vref(ca) range 1: 34
794 22:55:55.669440
795 22:55:55.672302 [CATrainingPosCal] consider 1 rank data
796 22:55:55.675542 u2DelayCellTimex100 = 270/100 ps
797 22:55:55.679016 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
798 22:55:55.682550 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
799 22:55:55.685488 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
800 22:55:55.688626 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
801 22:55:55.695659 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
802 22:55:55.698783 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
803 22:55:55.699315
804 22:55:55.702160 CA PerBit enable=1, Macro0, CA PI delay=33
805 22:55:55.702680
806 22:55:55.705573 [CBTSetCACLKResult] CA Dly = 33
807 22:55:55.706058 CS Dly: 7 (0~38)
808 22:55:55.706474 ==
809 22:55:55.708593 Dram Type= 6, Freq= 0, CH_0, rank 1
810 22:55:55.715211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 22:55:55.715707 ==
812 22:55:55.718606 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 22:55:55.724948 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 22:55:55.734327 [CA 0] Center 37 (6~68) winsize 63
815 22:55:55.737991 [CA 1] Center 37 (7~68) winsize 62
816 22:55:55.741696 [CA 2] Center 34 (4~65) winsize 62
817 22:55:55.744025 [CA 3] Center 34 (4~65) winsize 62
818 22:55:55.747547 [CA 4] Center 33 (3~64) winsize 62
819 22:55:55.750799 [CA 5] Center 33 (3~64) winsize 62
820 22:55:55.751241
821 22:55:55.754505 [CmdBusTrainingLP45] Vref(ca) range 1: 34
822 22:55:55.755130
823 22:55:55.757524 [CATrainingPosCal] consider 2 rank data
824 22:55:55.760612 u2DelayCellTimex100 = 270/100 ps
825 22:55:55.764117 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
826 22:55:55.770721 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
827 22:55:55.774611 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
828 22:55:55.778352 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
829 22:55:55.782052 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
830 22:55:55.785422 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
831 22:55:55.785887
832 22:55:55.789305 CA PerBit enable=1, Macro0, CA PI delay=33
833 22:55:55.789738
834 22:55:55.790116 [CBTSetCACLKResult] CA Dly = 33
835 22:55:55.793260 CS Dly: 7 (0~39)
836 22:55:55.793864
837 22:55:55.796401 ----->DramcWriteLeveling(PI) begin...
838 22:55:55.797158 ==
839 22:55:55.800129 Dram Type= 6, Freq= 0, CH_0, rank 0
840 22:55:55.803993 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
841 22:55:55.804464 ==
842 22:55:55.807378 Write leveling (Byte 0): 34 => 34
843 22:55:55.810925 Write leveling (Byte 1): 30 => 30
844 22:55:55.814333 DramcWriteLeveling(PI) end<-----
845 22:55:55.814791
846 22:55:55.815199 ==
847 22:55:55.817408 Dram Type= 6, Freq= 0, CH_0, rank 0
848 22:55:55.820681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
849 22:55:55.821210 ==
850 22:55:55.823848 [Gating] SW mode calibration
851 22:55:55.830653 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 22:55:55.837499 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 22:55:55.840806 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
854 22:55:55.844160 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
855 22:55:55.850909 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
856 22:55:55.854066 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 22:55:55.857038 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 22:55:55.860626 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 22:55:55.866961 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 22:55:55.870002 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 22:55:55.877093 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 22:55:55.880202 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 22:55:55.883776 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 22:55:55.887161 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 22:55:55.893552 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 22:55:55.896993 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 22:55:55.900327 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 22:55:55.907086 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 22:55:55.910429 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 22:55:55.913791 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
871 22:55:55.920098 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
872 22:55:55.923889 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 22:55:55.926676 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 22:55:55.933310 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 22:55:55.936675 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 22:55:55.939993 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 22:55:55.946463 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 22:55:55.950122 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
879 22:55:55.953403 0 9 8 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
880 22:55:55.960067 0 9 12 | B1->B0 | 2a29 3434 | 1 1 | (0 0) (1 1)
881 22:55:55.963379 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 22:55:55.966380 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 22:55:55.973029 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 22:55:55.976163 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 22:55:55.979638 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
886 22:55:55.986931 0 10 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
887 22:55:55.989842 0 10 8 | B1->B0 | 3232 2929 | 0 0 | (0 1) (0 0)
888 22:55:55.993197 0 10 12 | B1->B0 | 2626 2323 | 0 0 | (1 1) (0 0)
889 22:55:55.999437 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 22:55:56.003282 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 22:55:56.006839 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 22:55:56.013367 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 22:55:56.016035 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
894 22:55:56.019701 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
895 22:55:56.026327 0 11 8 | B1->B0 | 2323 3a3a | 0 0 | (0 0) (0 0)
896 22:55:56.029682 0 11 12 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
897 22:55:56.033068 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 22:55:56.036582 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 22:55:56.043158 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 22:55:56.046280 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 22:55:56.050106 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
902 22:55:56.055942 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
903 22:55:56.059427 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
904 22:55:56.062909 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 22:55:56.069427 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 22:55:56.072415 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 22:55:56.075967 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 22:55:56.082590 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 22:55:56.086054 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 22:55:56.089179 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 22:55:56.095993 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 22:55:56.098958 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 22:55:56.102270 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 22:55:56.108956 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 22:55:56.112449 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 22:55:56.115758 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 22:55:56.122743 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
918 22:55:56.125762 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
919 22:55:56.129180 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
920 22:55:56.132254 Total UI for P1: 0, mck2ui 16
921 22:55:56.135308 best dqsien dly found for B0: ( 0, 14, 6)
922 22:55:56.141919 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
923 22:55:56.142400 Total UI for P1: 0, mck2ui 16
924 22:55:56.148850 best dqsien dly found for B1: ( 0, 14, 8)
925 22:55:56.151898 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
926 22:55:56.155371 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
927 22:55:56.155838
928 22:55:56.158775 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
929 22:55:56.162005 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
930 22:55:56.165468 [Gating] SW calibration Done
931 22:55:56.165933 ==
932 22:55:56.169360 Dram Type= 6, Freq= 0, CH_0, rank 0
933 22:55:56.173247 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 22:55:56.173870 ==
935 22:55:56.174277 RX Vref Scan: 0
936 22:55:56.174604
937 22:55:56.176055 RX Vref 0 -> 0, step: 1
938 22:55:56.176541
939 22:55:56.179540 RX Delay -130 -> 252, step: 16
940 22:55:56.182624 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
941 22:55:56.187002 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
942 22:55:56.190080 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
943 22:55:56.194029 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
944 22:55:56.201307 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
945 22:55:56.204628 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
946 22:55:56.209001 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
947 22:55:56.212327 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
948 22:55:56.215696 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
949 22:55:56.220017 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
950 22:55:56.222913 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
951 22:55:56.227156 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
952 22:55:56.230410 iDelay=222, Bit 12, Center 69 (-50 ~ 189) 240
953 22:55:56.234296 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
954 22:55:56.241419 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
955 22:55:56.244609 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
956 22:55:56.245028 ==
957 22:55:56.248095 Dram Type= 6, Freq= 0, CH_0, rank 0
958 22:55:56.251378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
959 22:55:56.251806 ==
960 22:55:56.252140 DQS Delay:
961 22:55:56.255157 DQS0 = 0, DQS1 = 0
962 22:55:56.255579 DQM Delay:
963 22:55:56.257794 DQM0 = 88, DQM1 = 71
964 22:55:56.258216 DQ Delay:
965 22:55:56.261496 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
966 22:55:56.264432 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =101
967 22:55:56.267877 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
968 22:55:56.271587 DQ12 =69, DQ13 =77, DQ14 =85, DQ15 =77
969 22:55:56.272011
970 22:55:56.272345
971 22:55:56.272695 ==
972 22:55:56.274710 Dram Type= 6, Freq= 0, CH_0, rank 0
973 22:55:56.277909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
974 22:55:56.281234 ==
975 22:55:56.281657
976 22:55:56.281991
977 22:55:56.282303 TX Vref Scan disable
978 22:55:56.284506 == TX Byte 0 ==
979 22:55:56.287871 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
980 22:55:56.291480 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
981 22:55:56.294857 == TX Byte 1 ==
982 22:55:56.298746 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
983 22:55:56.302025 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
984 22:55:56.302561 ==
985 22:55:56.305790 Dram Type= 6, Freq= 0, CH_0, rank 0
986 22:55:56.309052 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
987 22:55:56.309663 ==
988 22:55:56.323836 TX Vref=22, minBit 1, minWin=27, winSum=442
989 22:55:56.327591 TX Vref=24, minBit 4, minWin=27, winSum=443
990 22:55:56.330857 TX Vref=26, minBit 8, minWin=27, winSum=444
991 22:55:56.334201 TX Vref=28, minBit 10, minWin=27, winSum=448
992 22:55:56.337638 TX Vref=30, minBit 7, minWin=27, winSum=448
993 22:55:56.340885 TX Vref=32, minBit 4, minWin=27, winSum=443
994 22:55:56.347460 [TxChooseVref] Worse bit 10, Min win 27, Win sum 448, Final Vref 28
995 22:55:56.347946
996 22:55:56.350717 Final TX Range 1 Vref 28
997 22:55:56.350822
998 22:55:56.350915 ==
999 22:55:56.354004 Dram Type= 6, Freq= 0, CH_0, rank 0
1000 22:55:56.357452 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1001 22:55:56.357570 ==
1002 22:55:56.357677
1003 22:55:56.357743
1004 22:55:56.360811 TX Vref Scan disable
1005 22:55:56.363812 == TX Byte 0 ==
1006 22:55:56.367271 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1007 22:55:56.370503 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1008 22:55:56.373911 == TX Byte 1 ==
1009 22:55:56.377190 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1010 22:55:56.380195 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1011 22:55:56.380278
1012 22:55:56.383589 [DATLAT]
1013 22:55:56.383671 Freq=800, CH0 RK0
1014 22:55:56.383738
1015 22:55:56.387498 DATLAT Default: 0xa
1016 22:55:56.387580 0, 0xFFFF, sum = 0
1017 22:55:56.390401 1, 0xFFFF, sum = 0
1018 22:55:56.390484 2, 0xFFFF, sum = 0
1019 22:55:56.393535 3, 0xFFFF, sum = 0
1020 22:55:56.393618 4, 0xFFFF, sum = 0
1021 22:55:56.396902 5, 0xFFFF, sum = 0
1022 22:55:56.397012 6, 0xFFFF, sum = 0
1023 22:55:56.400351 7, 0xFFFF, sum = 0
1024 22:55:56.400472 8, 0xFFFF, sum = 0
1025 22:55:56.403420 9, 0x0, sum = 1
1026 22:55:56.403502 10, 0x0, sum = 2
1027 22:55:56.407365 11, 0x0, sum = 3
1028 22:55:56.407447 12, 0x0, sum = 4
1029 22:55:56.410203 best_step = 10
1030 22:55:56.410289
1031 22:55:56.410357 ==
1032 22:55:56.413446 Dram Type= 6, Freq= 0, CH_0, rank 0
1033 22:55:56.417055 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1034 22:55:56.417137 ==
1035 22:55:56.420288 RX Vref Scan: 1
1036 22:55:56.420369
1037 22:55:56.420433 Set Vref Range= 32 -> 127
1038 22:55:56.420493
1039 22:55:56.423960 RX Vref 32 -> 127, step: 1
1040 22:55:56.424040
1041 22:55:56.426802 RX Delay -111 -> 252, step: 8
1042 22:55:56.426883
1043 22:55:56.429916 Set Vref, RX VrefLevel [Byte0]: 32
1044 22:55:56.433598 [Byte1]: 32
1045 22:55:56.433679
1046 22:55:56.436551 Set Vref, RX VrefLevel [Byte0]: 33
1047 22:55:56.439901 [Byte1]: 33
1048 22:55:56.443970
1049 22:55:56.444051 Set Vref, RX VrefLevel [Byte0]: 34
1050 22:55:56.447110 [Byte1]: 34
1051 22:55:56.451435
1052 22:55:56.451515 Set Vref, RX VrefLevel [Byte0]: 35
1053 22:55:56.455199 [Byte1]: 35
1054 22:55:56.459234
1055 22:55:56.459351 Set Vref, RX VrefLevel [Byte0]: 36
1056 22:55:56.462505 [Byte1]: 36
1057 22:55:56.467203
1058 22:55:56.467284 Set Vref, RX VrefLevel [Byte0]: 37
1059 22:55:56.470894 [Byte1]: 37
1060 22:55:56.474724
1061 22:55:56.474804 Set Vref, RX VrefLevel [Byte0]: 38
1062 22:55:56.477587 [Byte1]: 38
1063 22:55:56.482409
1064 22:55:56.482490 Set Vref, RX VrefLevel [Byte0]: 39
1065 22:55:56.485706 [Byte1]: 39
1066 22:55:56.489813
1067 22:55:56.489894 Set Vref, RX VrefLevel [Byte0]: 40
1068 22:55:56.492942 [Byte1]: 40
1069 22:55:56.497347
1070 22:55:56.497428 Set Vref, RX VrefLevel [Byte0]: 41
1071 22:55:56.500923 [Byte1]: 41
1072 22:55:56.505242
1073 22:55:56.505322 Set Vref, RX VrefLevel [Byte0]: 42
1074 22:55:56.508655 [Byte1]: 42
1075 22:55:56.512420
1076 22:55:56.512501 Set Vref, RX VrefLevel [Byte0]: 43
1077 22:55:56.515966 [Byte1]: 43
1078 22:55:56.520446
1079 22:55:56.520532 Set Vref, RX VrefLevel [Byte0]: 44
1080 22:55:56.523717 [Byte1]: 44
1081 22:55:56.527966
1082 22:55:56.528046 Set Vref, RX VrefLevel [Byte0]: 45
1083 22:55:56.531911 [Byte1]: 45
1084 22:55:56.536198
1085 22:55:56.536342 Set Vref, RX VrefLevel [Byte0]: 46
1086 22:55:56.538838 [Byte1]: 46
1087 22:55:56.543273
1088 22:55:56.543428 Set Vref, RX VrefLevel [Byte0]: 47
1089 22:55:56.546414 [Byte1]: 47
1090 22:55:56.550791
1091 22:55:56.550959 Set Vref, RX VrefLevel [Byte0]: 48
1092 22:55:56.554466 [Byte1]: 48
1093 22:55:56.559082
1094 22:55:56.559541 Set Vref, RX VrefLevel [Byte0]: 49
1095 22:55:56.562051 [Byte1]: 49
1096 22:55:56.566629
1097 22:55:56.567048 Set Vref, RX VrefLevel [Byte0]: 50
1098 22:55:56.569982 [Byte1]: 50
1099 22:55:56.574452
1100 22:55:56.574866 Set Vref, RX VrefLevel [Byte0]: 51
1101 22:55:56.577707 [Byte1]: 51
1102 22:55:56.581540
1103 22:55:56.581955 Set Vref, RX VrefLevel [Byte0]: 52
1104 22:55:56.584985 [Byte1]: 52
1105 22:55:56.589283
1106 22:55:56.589735 Set Vref, RX VrefLevel [Byte0]: 53
1107 22:55:56.592736 [Byte1]: 53
1108 22:55:56.597082
1109 22:55:56.597499 Set Vref, RX VrefLevel [Byte0]: 54
1110 22:55:56.600223 [Byte1]: 54
1111 22:55:56.604819
1112 22:55:56.605233 Set Vref, RX VrefLevel [Byte0]: 55
1113 22:55:56.607800 [Byte1]: 55
1114 22:55:56.612405
1115 22:55:56.612866 Set Vref, RX VrefLevel [Byte0]: 56
1116 22:55:56.615754 [Byte1]: 56
1117 22:55:56.620027
1118 22:55:56.620454 Set Vref, RX VrefLevel [Byte0]: 57
1119 22:55:56.623531 [Byte1]: 57
1120 22:55:56.627945
1121 22:55:56.628358 Set Vref, RX VrefLevel [Byte0]: 58
1122 22:55:56.630847 [Byte1]: 58
1123 22:55:56.635095
1124 22:55:56.635508 Set Vref, RX VrefLevel [Byte0]: 59
1125 22:55:56.638986 [Byte1]: 59
1126 22:55:56.643132
1127 22:55:56.643638 Set Vref, RX VrefLevel [Byte0]: 60
1128 22:55:56.646099 [Byte1]: 60
1129 22:55:56.650500
1130 22:55:56.650945 Set Vref, RX VrefLevel [Byte0]: 61
1131 22:55:56.653577 [Byte1]: 61
1132 22:55:56.658408
1133 22:55:56.659019 Set Vref, RX VrefLevel [Byte0]: 62
1134 22:55:56.661451 [Byte1]: 62
1135 22:55:56.666305
1136 22:55:56.666769 Set Vref, RX VrefLevel [Byte0]: 63
1137 22:55:56.669460 [Byte1]: 63
1138 22:55:56.674007
1139 22:55:56.674456 Set Vref, RX VrefLevel [Byte0]: 64
1140 22:55:56.676479 [Byte1]: 64
1141 22:55:56.680939
1142 22:55:56.681369 Set Vref, RX VrefLevel [Byte0]: 65
1143 22:55:56.684293 [Byte1]: 65
1144 22:55:56.689046
1145 22:55:56.689460 Set Vref, RX VrefLevel [Byte0]: 66
1146 22:55:56.692194 [Byte1]: 66
1147 22:55:56.696312
1148 22:55:56.696941 Set Vref, RX VrefLevel [Byte0]: 67
1149 22:55:56.699854 [Byte1]: 67
1150 22:55:56.704409
1151 22:55:56.704952 Set Vref, RX VrefLevel [Byte0]: 68
1152 22:55:56.707669 [Byte1]: 68
1153 22:55:56.711831
1154 22:55:56.712413 Set Vref, RX VrefLevel [Byte0]: 69
1155 22:55:56.715163 [Byte1]: 69
1156 22:55:56.719564
1157 22:55:56.720092 Set Vref, RX VrefLevel [Byte0]: 70
1158 22:55:56.722997 [Byte1]: 70
1159 22:55:56.727117
1160 22:55:56.727560 Set Vref, RX VrefLevel [Byte0]: 71
1161 22:55:56.730493 [Byte1]: 71
1162 22:55:56.734441
1163 22:55:56.734653 Set Vref, RX VrefLevel [Byte0]: 72
1164 22:55:56.737478 [Byte1]: 72
1165 22:55:56.742271
1166 22:55:56.742352 Set Vref, RX VrefLevel [Byte0]: 73
1167 22:55:56.745240 [Byte1]: 73
1168 22:55:56.749621
1169 22:55:56.749703 Set Vref, RX VrefLevel [Byte0]: 74
1170 22:55:56.752819 [Byte1]: 74
1171 22:55:56.757067
1172 22:55:56.757148 Set Vref, RX VrefLevel [Byte0]: 75
1173 22:55:56.760819 [Byte1]: 75
1174 22:55:56.765389
1175 22:55:56.765474 Set Vref, RX VrefLevel [Byte0]: 76
1176 22:55:56.768229 [Byte1]: 76
1177 22:55:56.772642
1178 22:55:56.772723 Set Vref, RX VrefLevel [Byte0]: 77
1179 22:55:56.775804 [Byte1]: 77
1180 22:55:56.780855
1181 22:55:56.780938 Set Vref, RX VrefLevel [Byte0]: 78
1182 22:55:56.783770 [Byte1]: 78
1183 22:55:56.788316
1184 22:55:56.788391 Set Vref, RX VrefLevel [Byte0]: 79
1185 22:55:56.791125 [Byte1]: 79
1186 22:55:56.795308
1187 22:55:56.795381 Set Vref, RX VrefLevel [Byte0]: 80
1188 22:55:56.798872 [Byte1]: 80
1189 22:55:56.803548
1190 22:55:56.803652 Set Vref, RX VrefLevel [Byte0]: 81
1191 22:55:56.806642 [Byte1]: 81
1192 22:55:56.811384
1193 22:55:56.811464 Set Vref, RX VrefLevel [Byte0]: 82
1194 22:55:56.815112 [Byte1]: 82
1195 22:55:56.818738
1196 22:55:56.818820 Set Vref, RX VrefLevel [Byte0]: 83
1197 22:55:56.822507 [Byte1]: 83
1198 22:55:56.826795
1199 22:55:56.826871 Set Vref, RX VrefLevel [Byte0]: 84
1200 22:55:56.829616 [Byte1]: 84
1201 22:55:56.833912
1202 22:55:56.833994 Set Vref, RX VrefLevel [Byte0]: 85
1203 22:55:56.837970 [Byte1]: 85
1204 22:55:56.841586
1205 22:55:56.841668 Final RX Vref Byte 0 = 66 to rank0
1206 22:55:56.844970 Final RX Vref Byte 1 = 62 to rank0
1207 22:55:56.848562 Final RX Vref Byte 0 = 66 to rank1
1208 22:55:56.852705 Final RX Vref Byte 1 = 62 to rank1==
1209 22:55:56.856406 Dram Type= 6, Freq= 0, CH_0, rank 0
1210 22:55:56.859988 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1211 22:55:56.860089 ==
1212 22:55:56.860169 DQS Delay:
1213 22:55:56.863518 DQS0 = 0, DQS1 = 0
1214 22:55:56.863613 DQM Delay:
1215 22:55:56.867318 DQM0 = 88, DQM1 = 74
1216 22:55:56.867418 DQ Delay:
1217 22:55:56.870596 DQ0 =84, DQ1 =92, DQ2 =84, DQ3 =84
1218 22:55:56.873814 DQ4 =88, DQ5 =76, DQ6 =100, DQ7 =96
1219 22:55:56.877210 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =68
1220 22:55:56.880640 DQ12 =80, DQ13 =76, DQ14 =84, DQ15 =80
1221 22:55:56.880761
1222 22:55:56.880858
1223 22:55:56.887738 [DQSOSCAuto] RK0, (LSB)MR18= 0x492a, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 391 ps
1224 22:55:56.891436 CH0 RK0: MR19=606, MR18=492A
1225 22:55:56.939485 CH0_RK0: MR19=0x606, MR18=0x492A, DQSOSC=391, MR23=63, INC=96, DEC=64
1226 22:55:56.939683
1227 22:55:56.939799 ----->DramcWriteLeveling(PI) begin...
1228 22:55:56.939895 ==
1229 22:55:56.939985 Dram Type= 6, Freq= 0, CH_0, rank 1
1230 22:55:56.940303 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1231 22:55:56.940410 ==
1232 22:55:56.940492 Write leveling (Byte 0): 31 => 31
1233 22:55:56.940602 Write leveling (Byte 1): 29 => 29
1234 22:55:56.940694 DramcWriteLeveling(PI) end<-----
1235 22:55:56.940771
1236 22:55:56.940846 ==
1237 22:55:56.941113 Dram Type= 6, Freq= 0, CH_0, rank 1
1238 22:55:56.941223 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1239 22:55:56.941304 ==
1240 22:55:56.941380 [Gating] SW mode calibration
1241 22:55:56.941457 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1242 22:55:56.941550 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1243 22:55:56.981808 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1244 22:55:56.982803 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1245 22:55:56.983386 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1246 22:55:56.984012 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1247 22:55:56.984551 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1248 22:55:56.985095 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1249 22:55:56.985442 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1250 22:55:56.985833 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1251 22:55:56.986200 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1252 22:55:56.986582 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1253 22:55:56.987260 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1254 22:55:56.994061 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1255 22:55:56.997123 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1256 22:55:57.000703 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1257 22:55:57.007437 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1258 22:55:57.010296 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1259 22:55:57.014256 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1260 22:55:57.020898 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1261 22:55:57.023863 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1262 22:55:57.026919 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1263 22:55:57.033780 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1264 22:55:57.037025 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1265 22:55:57.040196 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1266 22:55:57.046883 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1267 22:55:57.050452 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1268 22:55:57.053497 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1269 22:55:57.059712 0 9 8 | B1->B0 | 2424 2e2e | 1 1 | (0 0) (0 0)
1270 22:55:57.063173 0 9 12 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
1271 22:55:57.067090 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1272 22:55:57.073319 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1273 22:55:57.076883 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1274 22:55:57.079878 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1275 22:55:57.086367 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1276 22:55:57.089778 0 10 4 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
1277 22:55:57.093989 0 10 8 | B1->B0 | 3030 2424 | 0 1 | (0 0) (1 0)
1278 22:55:57.100312 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1279 22:55:57.103322 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1280 22:55:57.106550 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1281 22:55:57.113705 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1282 22:55:57.116852 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1283 22:55:57.120253 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1284 22:55:57.126792 0 11 4 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
1285 22:55:57.130341 0 11 8 | B1->B0 | 2f2f 3c3c | 0 0 | (0 0) (1 1)
1286 22:55:57.133793 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1287 22:55:57.140034 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1288 22:55:57.143810 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1289 22:55:57.146821 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1290 22:55:57.153404 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1291 22:55:57.156494 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1292 22:55:57.160239 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1293 22:55:57.163419 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1294 22:55:57.170621 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1295 22:55:57.173131 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1296 22:55:57.177070 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1297 22:55:57.183264 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1298 22:55:57.186753 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1299 22:55:57.189905 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1300 22:55:57.196367 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1301 22:55:57.200101 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1302 22:55:57.203503 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1303 22:55:57.207367 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1304 22:55:57.214255 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1305 22:55:57.218177 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1306 22:55:57.221338 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1307 22:55:57.224891 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1308 22:55:57.231768 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1309 22:55:57.235851 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1310 22:55:57.239189 Total UI for P1: 0, mck2ui 16
1311 22:55:57.242916 best dqsien dly found for B0: ( 0, 14, 6)
1312 22:55:57.245810 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1313 22:55:57.249548 Total UI for P1: 0, mck2ui 16
1314 22:55:57.253586 best dqsien dly found for B1: ( 0, 14, 8)
1315 22:55:57.256892 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1316 22:55:57.260397 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1317 22:55:57.260480
1318 22:55:57.264319 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1319 22:55:57.267964 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1320 22:55:57.271096 [Gating] SW calibration Done
1321 22:55:57.271179 ==
1322 22:55:57.271246 Dram Type= 6, Freq= 0, CH_0, rank 1
1323 22:55:57.278750 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1324 22:55:57.278836 ==
1325 22:55:57.278901 RX Vref Scan: 0
1326 22:55:57.278961
1327 22:55:57.282462 RX Vref 0 -> 0, step: 1
1328 22:55:57.282571
1329 22:55:57.285676 RX Delay -130 -> 252, step: 16
1330 22:55:57.289361 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1331 22:55:57.293476 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1332 22:55:57.296811 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1333 22:55:57.300329 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1334 22:55:57.304290 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1335 22:55:57.307455 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1336 22:55:57.311378 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1337 22:55:57.314753 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1338 22:55:57.318290 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1339 22:55:57.325869 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1340 22:55:57.329256 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1341 22:55:57.333440 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1342 22:55:57.336925 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1343 22:55:57.340577 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1344 22:55:57.343978 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1345 22:55:57.347378 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1346 22:55:57.347456 ==
1347 22:55:57.351008 Dram Type= 6, Freq= 0, CH_0, rank 1
1348 22:55:57.354805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1349 22:55:57.354888 ==
1350 22:55:57.358759 DQS Delay:
1351 22:55:57.358828 DQS0 = 0, DQS1 = 0
1352 22:55:57.358923 DQM Delay:
1353 22:55:57.362304 DQM0 = 84, DQM1 = 75
1354 22:55:57.362390 DQ Delay:
1355 22:55:57.366054 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =77
1356 22:55:57.370048 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1357 22:55:57.373920 DQ8 =61, DQ9 =53, DQ10 =77, DQ11 =69
1358 22:55:57.376942 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1359 22:55:57.377044
1360 22:55:57.377117
1361 22:55:57.377177 ==
1362 22:55:57.380585 Dram Type= 6, Freq= 0, CH_0, rank 1
1363 22:55:57.384501 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1364 22:55:57.384624 ==
1365 22:55:57.384688
1366 22:55:57.384746
1367 22:55:57.387624 TX Vref Scan disable
1368 22:55:57.387717 == TX Byte 0 ==
1369 22:55:57.391256 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1370 22:55:57.398366 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1371 22:55:57.398468 == TX Byte 1 ==
1372 22:55:57.402165 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1373 22:55:57.406052 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1374 22:55:57.406153 ==
1375 22:55:57.409871 Dram Type= 6, Freq= 0, CH_0, rank 1
1376 22:55:57.413390 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1377 22:55:57.413487 ==
1378 22:55:57.427472 TX Vref=22, minBit 8, minWin=27, winSum=445
1379 22:55:57.431283 TX Vref=24, minBit 9, minWin=27, winSum=448
1380 22:55:57.435175 TX Vref=26, minBit 9, minWin=27, winSum=447
1381 22:55:57.438766 TX Vref=28, minBit 8, minWin=27, winSum=447
1382 22:55:57.442120 TX Vref=30, minBit 9, minWin=27, winSum=448
1383 22:55:57.446138 TX Vref=32, minBit 9, minWin=27, winSum=446
1384 22:55:57.452798 [TxChooseVref] Worse bit 9, Min win 27, Win sum 448, Final Vref 24
1385 22:55:57.452878
1386 22:55:57.452940 Final TX Range 1 Vref 24
1387 22:55:57.453000
1388 22:55:57.456276 ==
1389 22:55:57.456354 Dram Type= 6, Freq= 0, CH_0, rank 1
1390 22:55:57.464035 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1391 22:55:57.464146 ==
1392 22:55:57.464241
1393 22:55:57.464303
1394 22:55:57.464359 TX Vref Scan disable
1395 22:55:57.467867 == TX Byte 0 ==
1396 22:55:57.471493 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1397 22:55:57.474614 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1398 22:55:57.479094 == TX Byte 1 ==
1399 22:55:57.482229 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1400 22:55:57.485653 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1401 22:55:57.485729
1402 22:55:57.485792 [DATLAT]
1403 22:55:57.489436 Freq=800, CH0 RK1
1404 22:55:57.489507
1405 22:55:57.489566 DATLAT Default: 0xa
1406 22:55:57.492940 0, 0xFFFF, sum = 0
1407 22:55:57.493021 1, 0xFFFF, sum = 0
1408 22:55:57.496505 2, 0xFFFF, sum = 0
1409 22:55:57.496643 3, 0xFFFF, sum = 0
1410 22:55:57.499785 4, 0xFFFF, sum = 0
1411 22:55:57.499864 5, 0xFFFF, sum = 0
1412 22:55:57.503911 6, 0xFFFF, sum = 0
1413 22:55:57.503991 7, 0xFFFF, sum = 0
1414 22:55:57.507656 8, 0xFFFF, sum = 0
1415 22:55:57.507729 9, 0x0, sum = 1
1416 22:55:57.511177 10, 0x0, sum = 2
1417 22:55:57.511281 11, 0x0, sum = 3
1418 22:55:57.511372 12, 0x0, sum = 4
1419 22:55:57.514879 best_step = 10
1420 22:55:57.514978
1421 22:55:57.515065 ==
1422 22:55:57.518503 Dram Type= 6, Freq= 0, CH_0, rank 1
1423 22:55:57.522525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1424 22:55:57.522608 ==
1425 22:55:57.522672 RX Vref Scan: 0
1426 22:55:57.522732
1427 22:55:57.526055 RX Vref 0 -> 0, step: 1
1428 22:55:57.526158
1429 22:55:57.529402 RX Delay -111 -> 252, step: 8
1430 22:55:57.533570 iDelay=217, Bit 0, Center 84 (-31 ~ 200) 232
1431 22:55:57.536665 iDelay=217, Bit 1, Center 92 (-23 ~ 208) 232
1432 22:55:57.540867 iDelay=217, Bit 2, Center 76 (-39 ~ 192) 232
1433 22:55:57.543943 iDelay=217, Bit 3, Center 80 (-39 ~ 200) 240
1434 22:55:57.547969 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
1435 22:55:57.551297 iDelay=217, Bit 5, Center 76 (-39 ~ 192) 232
1436 22:55:57.558597 iDelay=217, Bit 6, Center 96 (-15 ~ 208) 224
1437 22:55:57.562774 iDelay=217, Bit 7, Center 96 (-23 ~ 216) 240
1438 22:55:57.565475 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
1439 22:55:57.568933 iDelay=217, Bit 9, Center 64 (-47 ~ 176) 224
1440 22:55:57.572200 iDelay=217, Bit 10, Center 80 (-39 ~ 200) 240
1441 22:55:57.576203 iDelay=217, Bit 11, Center 72 (-39 ~ 184) 224
1442 22:55:57.582469 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
1443 22:55:57.585529 iDelay=217, Bit 13, Center 80 (-31 ~ 192) 224
1444 22:55:57.588567 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
1445 22:55:57.591906 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1446 22:55:57.591988 ==
1447 22:55:57.595313 Dram Type= 6, Freq= 0, CH_0, rank 1
1448 22:55:57.602177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1449 22:55:57.602297 ==
1450 22:55:57.602363 DQS Delay:
1451 22:55:57.605380 DQS0 = 0, DQS1 = 0
1452 22:55:57.605461 DQM Delay:
1453 22:55:57.605526 DQM0 = 85, DQM1 = 77
1454 22:55:57.608790 DQ Delay:
1455 22:55:57.612080 DQ0 =84, DQ1 =92, DQ2 =76, DQ3 =80
1456 22:55:57.615358 DQ4 =84, DQ5 =76, DQ6 =96, DQ7 =96
1457 22:55:57.619103 DQ8 =68, DQ9 =64, DQ10 =80, DQ11 =72
1458 22:55:57.621831 DQ12 =84, DQ13 =80, DQ14 =84, DQ15 =84
1459 22:55:57.621945
1460 22:55:57.622039
1461 22:55:57.628365 [DQSOSCAuto] RK1, (LSB)MR18= 0x4208, (MSB)MR19= 0x606, tDQSOscB0 = 408 ps tDQSOscB1 = 393 ps
1462 22:55:57.631957 CH0 RK1: MR19=606, MR18=4208
1463 22:55:57.638749 CH0_RK1: MR19=0x606, MR18=0x4208, DQSOSC=393, MR23=63, INC=95, DEC=63
1464 22:55:57.641972 [RxdqsGatingPostProcess] freq 800
1465 22:55:57.645305 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1466 22:55:57.648622 Pre-setting of DQS Precalculation
1467 22:55:57.654871 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1468 22:55:57.655065 ==
1469 22:55:57.658641 Dram Type= 6, Freq= 0, CH_1, rank 0
1470 22:55:57.661921 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1471 22:55:57.662117 ==
1472 22:55:57.668684 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1473 22:55:57.675280 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1474 22:55:57.682881 [CA 0] Center 36 (6~67) winsize 62
1475 22:55:57.686512 [CA 1] Center 36 (6~67) winsize 62
1476 22:55:57.689992 [CA 2] Center 34 (4~65) winsize 62
1477 22:55:57.692986 [CA 3] Center 34 (4~65) winsize 62
1478 22:55:57.696447 [CA 4] Center 34 (4~65) winsize 62
1479 22:55:57.699644 [CA 5] Center 34 (3~65) winsize 63
1480 22:55:57.700179
1481 22:55:57.703509 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1482 22:55:57.704074
1483 22:55:57.706577 [CATrainingPosCal] consider 1 rank data
1484 22:55:57.709533 u2DelayCellTimex100 = 270/100 ps
1485 22:55:57.713019 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1486 22:55:57.719545 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1487 22:55:57.723325 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1488 22:55:57.726382 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1489 22:55:57.730198 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1490 22:55:57.733471 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1491 22:55:57.733994
1492 22:55:57.736532 CA PerBit enable=1, Macro0, CA PI delay=34
1493 22:55:57.737077
1494 22:55:57.739707 [CBTSetCACLKResult] CA Dly = 34
1495 22:55:57.740290 CS Dly: 5 (0~36)
1496 22:55:57.742869 ==
1497 22:55:57.743333 Dram Type= 6, Freq= 0, CH_1, rank 1
1498 22:55:57.749525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1499 22:55:57.750079 ==
1500 22:55:57.752785 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1501 22:55:57.759780 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1502 22:55:57.769363 [CA 0] Center 36 (6~67) winsize 62
1503 22:55:57.773012 [CA 1] Center 36 (6~67) winsize 62
1504 22:55:57.776329 [CA 2] Center 34 (4~65) winsize 62
1505 22:55:57.779429 [CA 3] Center 34 (3~65) winsize 63
1506 22:55:57.783032 [CA 4] Center 34 (4~65) winsize 62
1507 22:55:57.786347 [CA 5] Center 34 (3~65) winsize 63
1508 22:55:57.786815
1509 22:55:57.789270 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1510 22:55:57.789694
1511 22:55:57.792374 [CATrainingPosCal] consider 2 rank data
1512 22:55:57.796250 u2DelayCellTimex100 = 270/100 ps
1513 22:55:57.799504 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1514 22:55:57.802860 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1515 22:55:57.809214 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1516 22:55:57.812459 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1517 22:55:57.815755 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1518 22:55:57.819274 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1519 22:55:57.819738
1520 22:55:57.822407 CA PerBit enable=1, Macro0, CA PI delay=34
1521 22:55:57.822967
1522 22:55:57.825461 [CBTSetCACLKResult] CA Dly = 34
1523 22:55:57.825889 CS Dly: 6 (0~38)
1524 22:55:57.828792
1525 22:55:57.832735 ----->DramcWriteLeveling(PI) begin...
1526 22:55:57.833162 ==
1527 22:55:57.835480 Dram Type= 6, Freq= 0, CH_1, rank 0
1528 22:55:57.839166 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1529 22:55:57.839593 ==
1530 22:55:57.842167 Write leveling (Byte 0): 26 => 26
1531 22:55:57.845415 Write leveling (Byte 1): 27 => 27
1532 22:55:57.848672 DramcWriteLeveling(PI) end<-----
1533 22:55:57.849093
1534 22:55:57.849425 ==
1535 22:55:57.852454 Dram Type= 6, Freq= 0, CH_1, rank 0
1536 22:55:57.855238 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1537 22:55:57.855660 ==
1538 22:55:57.858784 [Gating] SW mode calibration
1539 22:55:57.865582 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1540 22:55:57.872175 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1541 22:55:57.875100 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1542 22:55:57.878703 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1543 22:55:57.885245 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1544 22:55:57.888391 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1545 22:55:57.891795 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1546 22:55:57.898359 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1547 22:55:57.901576 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1548 22:55:57.905345 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1549 22:55:57.911413 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1550 22:55:57.915102 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1551 22:55:57.918282 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1552 22:55:57.924955 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1553 22:55:57.928483 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1554 22:55:57.931417 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1555 22:55:57.937981 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1556 22:55:57.941563 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1557 22:55:57.944617 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1558 22:55:57.948227 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1559 22:55:57.954696 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1560 22:55:57.958166 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1561 22:55:57.961727 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1562 22:55:57.968243 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1563 22:55:57.971401 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1564 22:55:57.974220 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1565 22:55:57.981084 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1566 22:55:57.984302 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1567 22:55:57.987629 0 9 8 | B1->B0 | 2c2c 3232 | 1 1 | (0 0) (1 1)
1568 22:55:57.994504 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1569 22:55:57.997630 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1570 22:55:58.001449 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1571 22:55:58.007411 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1572 22:55:58.010851 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1573 22:55:58.014463 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1574 22:55:58.020817 0 10 4 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
1575 22:55:58.023919 0 10 8 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
1576 22:55:58.027663 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1577 22:55:58.033842 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1578 22:55:58.037104 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1579 22:55:58.040925 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1580 22:55:58.047188 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1581 22:55:58.051088 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1582 22:55:58.054095 0 11 4 | B1->B0 | 2727 2727 | 0 0 | (1 1) (0 0)
1583 22:55:58.060312 0 11 8 | B1->B0 | 3838 3c3c | 0 0 | (0 0) (0 0)
1584 22:55:58.064387 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1585 22:55:58.067122 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1586 22:55:58.073693 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1587 22:55:58.077337 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1588 22:55:58.080379 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1589 22:55:58.087329 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1590 22:55:58.090200 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1591 22:55:58.093613 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1592 22:55:58.100454 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1593 22:55:58.103588 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1594 22:55:58.107040 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1595 22:55:58.113410 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1596 22:55:58.116827 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1597 22:55:58.120304 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1598 22:55:58.126392 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1599 22:55:58.129865 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1600 22:55:58.133532 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1601 22:55:58.136892 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1602 22:55:58.143177 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1603 22:55:58.146711 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1604 22:55:58.149830 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1605 22:55:58.156828 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1606 22:55:58.160173 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1607 22:55:58.163130 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1608 22:55:58.166882 Total UI for P1: 0, mck2ui 16
1609 22:55:58.170214 best dqsien dly found for B0: ( 0, 14, 4)
1610 22:55:58.176642 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1611 22:55:58.179771 Total UI for P1: 0, mck2ui 16
1612 22:55:58.182985 best dqsien dly found for B1: ( 0, 14, 8)
1613 22:55:58.186377 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1614 22:55:58.189785 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1615 22:55:58.189875
1616 22:55:58.193350 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1617 22:55:58.196916 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1618 22:55:58.200199 [Gating] SW calibration Done
1619 22:55:58.200308 ==
1620 22:55:58.203663 Dram Type= 6, Freq= 0, CH_1, rank 0
1621 22:55:58.206735 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1622 22:55:58.206818 ==
1623 22:55:58.209739 RX Vref Scan: 0
1624 22:55:58.209821
1625 22:55:58.209886 RX Vref 0 -> 0, step: 1
1626 22:55:58.209946
1627 22:55:58.213122 RX Delay -130 -> 252, step: 16
1628 22:55:58.219311 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1629 22:55:58.222742 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1630 22:55:58.226135 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1631 22:55:58.229671 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1632 22:55:58.232542 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1633 22:55:58.239647 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1634 22:55:58.242940 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1635 22:55:58.245974 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1636 22:55:58.249191 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1637 22:55:58.252910 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1638 22:55:58.259157 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1639 22:55:58.262753 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1640 22:55:58.265850 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1641 22:55:58.269109 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1642 22:55:58.272750 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1643 22:55:58.279172 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1644 22:55:58.279254 ==
1645 22:55:58.282492 Dram Type= 6, Freq= 0, CH_1, rank 0
1646 22:55:58.285757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1647 22:55:58.285840 ==
1648 22:55:58.285910 DQS Delay:
1649 22:55:58.289350 DQS0 = 0, DQS1 = 0
1650 22:55:58.289432 DQM Delay:
1651 22:55:58.292506 DQM0 = 89, DQM1 = 78
1652 22:55:58.292612 DQ Delay:
1653 22:55:58.295916 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =85
1654 22:55:58.299012 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1655 22:55:58.302432 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1656 22:55:58.305546 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1657 22:55:58.305628
1658 22:55:58.305694
1659 22:55:58.305754 ==
1660 22:55:58.309058 Dram Type= 6, Freq= 0, CH_1, rank 0
1661 22:55:58.312314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1662 22:55:58.315653 ==
1663 22:55:58.315735
1664 22:55:58.315799
1665 22:55:58.315870 TX Vref Scan disable
1666 22:55:58.318892 == TX Byte 0 ==
1667 22:55:58.322409 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1668 22:55:58.325618 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1669 22:55:58.328990 == TX Byte 1 ==
1670 22:55:58.332960 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1671 22:55:58.335625 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1672 22:55:58.339356 ==
1673 22:55:58.339507 Dram Type= 6, Freq= 0, CH_1, rank 0
1674 22:55:58.345404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1675 22:55:58.345558 ==
1676 22:55:58.358060 TX Vref=22, minBit 10, minWin=26, winSum=440
1677 22:55:58.361278 TX Vref=24, minBit 3, minWin=27, winSum=446
1678 22:55:58.364556 TX Vref=26, minBit 11, minWin=27, winSum=447
1679 22:55:58.367464 TX Vref=28, minBit 9, minWin=27, winSum=448
1680 22:55:58.370675 TX Vref=30, minBit 8, minWin=27, winSum=448
1681 22:55:58.377713 TX Vref=32, minBit 0, minWin=27, winSum=443
1682 22:55:58.381085 [TxChooseVref] Worse bit 9, Min win 27, Win sum 448, Final Vref 28
1683 22:55:58.381168
1684 22:55:58.384469 Final TX Range 1 Vref 28
1685 22:55:58.384595
1686 22:55:58.384661 ==
1687 22:55:58.387704 Dram Type= 6, Freq= 0, CH_1, rank 0
1688 22:55:58.391018 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1689 22:55:58.394064 ==
1690 22:55:58.394143
1691 22:55:58.394206
1692 22:55:58.394265 TX Vref Scan disable
1693 22:55:58.398069 == TX Byte 0 ==
1694 22:55:58.401188 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1695 22:55:58.407682 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1696 22:55:58.407765 == TX Byte 1 ==
1697 22:55:58.410885 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1698 22:55:58.417893 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1699 22:55:58.417975
1700 22:55:58.418040 [DATLAT]
1701 22:55:58.418104 Freq=800, CH1 RK0
1702 22:55:58.418176
1703 22:55:58.421431 DATLAT Default: 0xa
1704 22:55:58.421515 0, 0xFFFF, sum = 0
1705 22:55:58.424250 1, 0xFFFF, sum = 0
1706 22:55:58.427624 2, 0xFFFF, sum = 0
1707 22:55:58.427713 3, 0xFFFF, sum = 0
1708 22:55:58.431283 4, 0xFFFF, sum = 0
1709 22:55:58.431366 5, 0xFFFF, sum = 0
1710 22:55:58.434327 6, 0xFFFF, sum = 0
1711 22:55:58.434410 7, 0xFFFF, sum = 0
1712 22:55:58.437750 8, 0xFFFF, sum = 0
1713 22:55:58.437845 9, 0x0, sum = 1
1714 22:55:58.441017 10, 0x0, sum = 2
1715 22:55:58.441109 11, 0x0, sum = 3
1716 22:55:58.441174 12, 0x0, sum = 4
1717 22:55:58.444331 best_step = 10
1718 22:55:58.444412
1719 22:55:58.444476 ==
1720 22:55:58.447770 Dram Type= 6, Freq= 0, CH_1, rank 0
1721 22:55:58.450831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1722 22:55:58.450913 ==
1723 22:55:58.454619 RX Vref Scan: 1
1724 22:55:58.454720
1725 22:55:58.457655 Set Vref Range= 32 -> 127
1726 22:55:58.457737
1727 22:55:58.457802 RX Vref 32 -> 127, step: 1
1728 22:55:58.457863
1729 22:55:58.460680 RX Delay -95 -> 252, step: 8
1730 22:55:58.460793
1731 22:55:58.464037 Set Vref, RX VrefLevel [Byte0]: 32
1732 22:55:58.467868 [Byte1]: 32
1733 22:55:58.470498
1734 22:55:58.470580 Set Vref, RX VrefLevel [Byte0]: 33
1735 22:55:58.474059 [Byte1]: 33
1736 22:55:58.477867
1737 22:55:58.477949 Set Vref, RX VrefLevel [Byte0]: 34
1738 22:55:58.481787 [Byte1]: 34
1739 22:55:58.485802
1740 22:55:58.485887 Set Vref, RX VrefLevel [Byte0]: 35
1741 22:55:58.488902 [Byte1]: 35
1742 22:55:58.493384
1743 22:55:58.493484 Set Vref, RX VrefLevel [Byte0]: 36
1744 22:55:58.496861 [Byte1]: 36
1745 22:55:58.500990
1746 22:55:58.501072 Set Vref, RX VrefLevel [Byte0]: 37
1747 22:55:58.504233 [Byte1]: 37
1748 22:55:58.508765
1749 22:55:58.508848 Set Vref, RX VrefLevel [Byte0]: 38
1750 22:55:58.511684 [Byte1]: 38
1751 22:55:58.516147
1752 22:55:58.516225 Set Vref, RX VrefLevel [Byte0]: 39
1753 22:55:58.519845 [Byte1]: 39
1754 22:55:58.523654
1755 22:55:58.523725 Set Vref, RX VrefLevel [Byte0]: 40
1756 22:55:58.527426 [Byte1]: 40
1757 22:55:58.531111
1758 22:55:58.531188 Set Vref, RX VrefLevel [Byte0]: 41
1759 22:55:58.534682 [Byte1]: 41
1760 22:55:58.539117
1761 22:55:58.539190 Set Vref, RX VrefLevel [Byte0]: 42
1762 22:55:58.542256 [Byte1]: 42
1763 22:55:58.546475
1764 22:55:58.546562 Set Vref, RX VrefLevel [Byte0]: 43
1765 22:55:58.549872 [Byte1]: 43
1766 22:55:58.554530
1767 22:55:58.554634 Set Vref, RX VrefLevel [Byte0]: 44
1768 22:55:58.557572 [Byte1]: 44
1769 22:55:58.561974
1770 22:55:58.562086 Set Vref, RX VrefLevel [Byte0]: 45
1771 22:55:58.565273 [Byte1]: 45
1772 22:55:58.569345
1773 22:55:58.569488 Set Vref, RX VrefLevel [Byte0]: 46
1774 22:55:58.573016 [Byte1]: 46
1775 22:55:58.576886
1776 22:55:58.577067 Set Vref, RX VrefLevel [Byte0]: 47
1777 22:55:58.580106 [Byte1]: 47
1778 22:55:58.585131
1779 22:55:58.585335 Set Vref, RX VrefLevel [Byte0]: 48
1780 22:55:58.588222 [Byte1]: 48
1781 22:55:58.592099
1782 22:55:58.592340 Set Vref, RX VrefLevel [Byte0]: 49
1783 22:55:58.595524 [Byte1]: 49
1784 22:55:58.600019
1785 22:55:58.600448 Set Vref, RX VrefLevel [Byte0]: 50
1786 22:55:58.603196 [Byte1]: 50
1787 22:55:58.607549
1788 22:55:58.610634 Set Vref, RX VrefLevel [Byte0]: 51
1789 22:55:58.614534 [Byte1]: 51
1790 22:55:58.615002
1791 22:55:58.617853 Set Vref, RX VrefLevel [Byte0]: 52
1792 22:55:58.620837 [Byte1]: 52
1793 22:55:58.621348
1794 22:55:58.623991 Set Vref, RX VrefLevel [Byte0]: 53
1795 22:55:58.627216 [Byte1]: 53
1796 22:55:58.627640
1797 22:55:58.630928 Set Vref, RX VrefLevel [Byte0]: 54
1798 22:55:58.633930 [Byte1]: 54
1799 22:55:58.638366
1800 22:55:58.638612 Set Vref, RX VrefLevel [Byte0]: 55
1801 22:55:58.641019 [Byte1]: 55
1802 22:55:58.645831
1803 22:55:58.645912 Set Vref, RX VrefLevel [Byte0]: 56
1804 22:55:58.648446 [Byte1]: 56
1805 22:55:58.653143
1806 22:55:58.653233 Set Vref, RX VrefLevel [Byte0]: 57
1807 22:55:58.656717 [Byte1]: 57
1808 22:55:58.660321
1809 22:55:58.660414 Set Vref, RX VrefLevel [Byte0]: 58
1810 22:55:58.663693 [Byte1]: 58
1811 22:55:58.668093
1812 22:55:58.668204 Set Vref, RX VrefLevel [Byte0]: 59
1813 22:55:58.671412 [Byte1]: 59
1814 22:55:58.675664
1815 22:55:58.675785 Set Vref, RX VrefLevel [Byte0]: 60
1816 22:55:58.679341 [Byte1]: 60
1817 22:55:58.683881
1818 22:55:58.684032 Set Vref, RX VrefLevel [Byte0]: 61
1819 22:55:58.686394 [Byte1]: 61
1820 22:55:58.691019
1821 22:55:58.691266 Set Vref, RX VrefLevel [Byte0]: 62
1822 22:55:58.694403 [Byte1]: 62
1823 22:55:58.698333
1824 22:55:58.698409 Set Vref, RX VrefLevel [Byte0]: 63
1825 22:55:58.701952 [Byte1]: 63
1826 22:55:58.706021
1827 22:55:58.706094 Set Vref, RX VrefLevel [Byte0]: 64
1828 22:55:58.709559 [Byte1]: 64
1829 22:55:58.714026
1830 22:55:58.714099 Set Vref, RX VrefLevel [Byte0]: 65
1831 22:55:58.716904 [Byte1]: 65
1832 22:55:58.721255
1833 22:55:58.721329 Set Vref, RX VrefLevel [Byte0]: 66
1834 22:55:58.724645 [Byte1]: 66
1835 22:55:58.729014
1836 22:55:58.729085 Set Vref, RX VrefLevel [Byte0]: 67
1837 22:55:58.732355 [Byte1]: 67
1838 22:55:58.736816
1839 22:55:58.736886 Set Vref, RX VrefLevel [Byte0]: 68
1840 22:55:58.743006 [Byte1]: 68
1841 22:55:58.743104
1842 22:55:58.746526 Set Vref, RX VrefLevel [Byte0]: 69
1843 22:55:58.749453 [Byte1]: 69
1844 22:55:58.749522
1845 22:55:58.752654 Set Vref, RX VrefLevel [Byte0]: 70
1846 22:55:58.755896 [Byte1]: 70
1847 22:55:58.759444
1848 22:55:58.759513 Set Vref, RX VrefLevel [Byte0]: 71
1849 22:55:58.762468 [Byte1]: 71
1850 22:55:58.766802
1851 22:55:58.766876 Set Vref, RX VrefLevel [Byte0]: 72
1852 22:55:58.770554 [Byte1]: 72
1853 22:55:58.774286
1854 22:55:58.774365 Set Vref, RX VrefLevel [Byte0]: 73
1855 22:55:58.777600 [Byte1]: 73
1856 22:55:58.781768
1857 22:55:58.781847 Set Vref, RX VrefLevel [Byte0]: 74
1858 22:55:58.785593 [Byte1]: 74
1859 22:55:58.789607
1860 22:55:58.789687 Set Vref, RX VrefLevel [Byte0]: 75
1861 22:55:58.792781 [Byte1]: 75
1862 22:55:58.797392
1863 22:55:58.797473 Set Vref, RX VrefLevel [Byte0]: 76
1864 22:55:58.800771 [Byte1]: 76
1865 22:55:58.805211
1866 22:55:58.805292 Final RX Vref Byte 0 = 52 to rank0
1867 22:55:58.808528 Final RX Vref Byte 1 = 62 to rank0
1868 22:55:58.811376 Final RX Vref Byte 0 = 52 to rank1
1869 22:55:58.814545 Final RX Vref Byte 1 = 62 to rank1==
1870 22:55:58.818209 Dram Type= 6, Freq= 0, CH_1, rank 0
1871 22:55:58.824927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1872 22:55:58.825009 ==
1873 22:55:58.825073 DQS Delay:
1874 22:55:58.825131 DQS0 = 0, DQS1 = 0
1875 22:55:58.828071 DQM Delay:
1876 22:55:58.828151 DQM0 = 86, DQM1 = 80
1877 22:55:58.831743 DQ Delay:
1878 22:55:58.834657 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =80
1879 22:55:58.838032 DQ4 =84, DQ5 =96, DQ6 =96, DQ7 =84
1880 22:55:58.841280 DQ8 =68, DQ9 =72, DQ10 =80, DQ11 =72
1881 22:55:58.844745 DQ12 =88, DQ13 =84, DQ14 =88, DQ15 =88
1882 22:55:58.844826
1883 22:55:58.844889
1884 22:55:58.851460 [DQSOSCAuto] RK0, (LSB)MR18= 0x3521, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 396 ps
1885 22:55:58.854603 CH1 RK0: MR19=606, MR18=3521
1886 22:55:58.861113 CH1_RK0: MR19=0x606, MR18=0x3521, DQSOSC=396, MR23=63, INC=94, DEC=62
1887 22:55:58.861196
1888 22:55:58.864924 ----->DramcWriteLeveling(PI) begin...
1889 22:55:58.865007 ==
1890 22:55:58.867826 Dram Type= 6, Freq= 0, CH_1, rank 1
1891 22:55:58.871749 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1892 22:55:58.871832 ==
1893 22:55:58.874400 Write leveling (Byte 0): 26 => 26
1894 22:55:58.878384 Write leveling (Byte 1): 31 => 31
1895 22:55:58.881111 DramcWriteLeveling(PI) end<-----
1896 22:55:58.881193
1897 22:55:58.881258 ==
1898 22:55:58.884935 Dram Type= 6, Freq= 0, CH_1, rank 1
1899 22:55:58.888064 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1900 22:55:58.888156 ==
1901 22:55:58.891211 [Gating] SW mode calibration
1902 22:55:58.898105 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1903 22:55:58.904272 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1904 22:55:58.907717 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1905 22:55:58.911038 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1906 22:55:58.917605 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1907 22:55:58.920881 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1908 22:55:58.924180 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1909 22:55:58.930825 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1910 22:55:58.934195 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1911 22:55:58.937694 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1912 22:55:58.944241 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1913 22:55:58.947704 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1914 22:55:58.951008 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1915 22:55:58.957651 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1916 22:55:58.960871 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1917 22:55:58.964434 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1918 22:55:58.970875 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1919 22:55:58.973981 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1920 22:55:58.977602 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1921 22:55:58.984085 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1922 22:55:58.987910 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
1923 22:55:58.991082 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1924 22:55:58.997678 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1925 22:55:59.000751 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1926 22:55:59.004035 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1927 22:55:59.010330 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1928 22:55:59.014022 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1929 22:55:59.017071 0 9 4 | B1->B0 | 2323 2323 | 1 0 | (1 1) (0 0)
1930 22:55:59.024334 0 9 8 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (0 0)
1931 22:55:59.027389 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1932 22:55:59.030888 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1933 22:55:59.037217 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1934 22:55:59.040689 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1935 22:55:59.043808 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1936 22:55:59.050182 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1937 22:55:59.054228 0 10 4 | B1->B0 | 3232 3434 | 1 1 | (1 0) (1 0)
1938 22:55:59.057562 0 10 8 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (1 0)
1939 22:55:59.060761 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1940 22:55:59.067512 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1941 22:55:59.070761 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1942 22:55:59.073480 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1943 22:55:59.080563 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1944 22:55:59.083749 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1945 22:55:59.087103 0 11 4 | B1->B0 | 2727 2424 | 0 0 | (0 0) (0 0)
1946 22:55:59.093564 0 11 8 | B1->B0 | 4444 3838 | 0 1 | (0 0) (1 1)
1947 22:55:59.096904 0 11 12 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
1948 22:55:59.100579 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1949 22:55:59.106838 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1950 22:55:59.110080 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1951 22:55:59.113282 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1952 22:55:59.119829 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1953 22:55:59.123652 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1954 22:55:59.126639 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1955 22:55:59.133126 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1956 22:55:59.136493 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1957 22:55:59.140364 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1958 22:55:59.146740 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1959 22:55:59.149818 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1960 22:55:59.153212 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1961 22:55:59.160103 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1962 22:55:59.163021 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1963 22:55:59.166811 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1964 22:55:59.173412 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1965 22:55:59.176253 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1966 22:55:59.179580 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1967 22:55:59.186914 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1968 22:55:59.189563 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1969 22:55:59.193162 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1970 22:55:59.199883 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1971 22:55:59.202869 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1972 22:55:59.206577 Total UI for P1: 0, mck2ui 16
1973 22:55:59.209697 best dqsien dly found for B0: ( 0, 14, 6)
1974 22:55:59.212868 Total UI for P1: 0, mck2ui 16
1975 22:55:59.216073 best dqsien dly found for B1: ( 0, 14, 8)
1976 22:55:59.219550 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1977 22:55:59.222998 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1978 22:55:59.223440
1979 22:55:59.226023 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1980 22:55:59.229876 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1981 22:55:59.233097 [Gating] SW calibration Done
1982 22:55:59.233519 ==
1983 22:55:59.236293 Dram Type= 6, Freq= 0, CH_1, rank 1
1984 22:55:59.239828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1985 22:55:59.240250 ==
1986 22:55:59.242930 RX Vref Scan: 0
1987 22:55:59.243352
1988 22:55:59.246294 RX Vref 0 -> 0, step: 1
1989 22:55:59.246731
1990 22:55:59.249745 RX Delay -130 -> 252, step: 16
1991 22:55:59.252670 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1992 22:55:59.256239 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1993 22:55:59.259291 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1994 22:55:59.262881 iDelay=222, Bit 3, Center 77 (-34 ~ 189) 224
1995 22:55:59.269164 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1996 22:55:59.272627 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1997 22:55:59.276112 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1998 22:55:59.279256 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1999 22:55:59.282737 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
2000 22:55:59.289434 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
2001 22:55:59.292552 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
2002 22:55:59.295787 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
2003 22:55:59.299287 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
2004 22:55:59.302351 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
2005 22:55:59.309000 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
2006 22:55:59.312174 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
2007 22:55:59.312584 ==
2008 22:55:59.315395 Dram Type= 6, Freq= 0, CH_1, rank 1
2009 22:55:59.319366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2010 22:55:59.319749 ==
2011 22:55:59.322408 DQS Delay:
2012 22:55:59.322842 DQS0 = 0, DQS1 = 0
2013 22:55:59.323167 DQM Delay:
2014 22:55:59.325599 DQM0 = 86, DQM1 = 80
2015 22:55:59.326015 DQ Delay:
2016 22:55:59.329235 DQ0 =85, DQ1 =77, DQ2 =77, DQ3 =77
2017 22:55:59.332420 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
2018 22:55:59.335652 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
2019 22:55:59.339145 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
2020 22:55:59.339895
2021 22:55:59.340437
2022 22:55:59.340956 ==
2023 22:55:59.341955 Dram Type= 6, Freq= 0, CH_1, rank 1
2024 22:55:59.349220 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2025 22:55:59.349665 ==
2026 22:55:59.349999
2027 22:55:59.350324
2028 22:55:59.350619 TX Vref Scan disable
2029 22:55:59.352766 == TX Byte 0 ==
2030 22:55:59.355999 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2031 22:55:59.362642 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2032 22:55:59.363122 == TX Byte 1 ==
2033 22:55:59.366017 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
2034 22:55:59.372819 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
2035 22:55:59.373296 ==
2036 22:55:59.375925 Dram Type= 6, Freq= 0, CH_1, rank 1
2037 22:55:59.379029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2038 22:55:59.379476 ==
2039 22:55:59.392153 TX Vref=22, minBit 0, minWin=27, winSum=440
2040 22:55:59.395512 TX Vref=24, minBit 8, minWin=27, winSum=447
2041 22:55:59.398930 TX Vref=26, minBit 9, minWin=27, winSum=450
2042 22:55:59.402327 TX Vref=28, minBit 13, minWin=27, winSum=452
2043 22:55:59.405382 TX Vref=30, minBit 8, minWin=27, winSum=448
2044 22:55:59.411900 TX Vref=32, minBit 8, minWin=27, winSum=447
2045 22:55:59.415674 [TxChooseVref] Worse bit 13, Min win 27, Win sum 452, Final Vref 28
2046 22:55:59.416122
2047 22:55:59.418854 Final TX Range 1 Vref 28
2048 22:55:59.419432
2049 22:55:59.419803 ==
2050 22:55:59.422100 Dram Type= 6, Freq= 0, CH_1, rank 1
2051 22:55:59.425276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2052 22:55:59.428561 ==
2053 22:55:59.429001
2054 22:55:59.429347
2055 22:55:59.429693 TX Vref Scan disable
2056 22:55:59.432243 == TX Byte 0 ==
2057 22:55:59.435650 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2058 22:55:59.442192 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2059 22:55:59.442623 == TX Byte 1 ==
2060 22:55:59.445337 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2061 22:55:59.451925 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2062 22:55:59.452350
2063 22:55:59.452732 [DATLAT]
2064 22:55:59.453047 Freq=800, CH1 RK1
2065 22:55:59.453350
2066 22:55:59.455104 DATLAT Default: 0xa
2067 22:55:59.455523 0, 0xFFFF, sum = 0
2068 22:55:59.458516 1, 0xFFFF, sum = 0
2069 22:55:59.461853 2, 0xFFFF, sum = 0
2070 22:55:59.462284 3, 0xFFFF, sum = 0
2071 22:55:59.465401 4, 0xFFFF, sum = 0
2072 22:55:59.465827 5, 0xFFFF, sum = 0
2073 22:55:59.468913 6, 0xFFFF, sum = 0
2074 22:55:59.469342 7, 0xFFFF, sum = 0
2075 22:55:59.471754 8, 0xFFFF, sum = 0
2076 22:55:59.472180 9, 0x0, sum = 1
2077 22:55:59.475099 10, 0x0, sum = 2
2078 22:55:59.475527 11, 0x0, sum = 3
2079 22:55:59.475868 12, 0x0, sum = 4
2080 22:55:59.478350 best_step = 10
2081 22:55:59.478773
2082 22:55:59.479110 ==
2083 22:55:59.482213 Dram Type= 6, Freq= 0, CH_1, rank 1
2084 22:55:59.485547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2085 22:55:59.485972 ==
2086 22:55:59.488794 RX Vref Scan: 0
2087 22:55:59.489215
2088 22:55:59.491725 RX Vref 0 -> 0, step: 1
2089 22:55:59.492146
2090 22:55:59.492480 RX Delay -95 -> 252, step: 8
2091 22:55:59.498539 iDelay=217, Bit 0, Center 88 (-23 ~ 200) 224
2092 22:55:59.501940 iDelay=217, Bit 1, Center 84 (-23 ~ 192) 216
2093 22:55:59.505352 iDelay=217, Bit 2, Center 76 (-31 ~ 184) 216
2094 22:55:59.508459 iDelay=217, Bit 3, Center 84 (-23 ~ 192) 216
2095 22:55:59.511826 iDelay=217, Bit 4, Center 88 (-23 ~ 200) 224
2096 22:55:59.518720 iDelay=217, Bit 5, Center 96 (-15 ~ 208) 224
2097 22:55:59.521591 iDelay=217, Bit 6, Center 100 (-15 ~ 216) 232
2098 22:55:59.524985 iDelay=217, Bit 7, Center 84 (-31 ~ 200) 232
2099 22:55:59.528260 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
2100 22:55:59.531879 iDelay=217, Bit 9, Center 68 (-47 ~ 184) 232
2101 22:55:59.538253 iDelay=217, Bit 10, Center 80 (-39 ~ 200) 240
2102 22:55:59.541615 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
2103 22:55:59.545049 iDelay=217, Bit 12, Center 88 (-23 ~ 200) 224
2104 22:55:59.548620 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
2105 22:55:59.555406 iDelay=217, Bit 14, Center 88 (-23 ~ 200) 224
2106 22:55:59.558270 iDelay=217, Bit 15, Center 88 (-31 ~ 208) 240
2107 22:55:59.558352 ==
2108 22:55:59.561528 Dram Type= 6, Freq= 0, CH_1, rank 1
2109 22:55:59.564952 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2110 22:55:59.565035 ==
2111 22:55:59.568290 DQS Delay:
2112 22:55:59.568371 DQS0 = 0, DQS1 = 0
2113 22:55:59.568435 DQM Delay:
2114 22:55:59.571860 DQM0 = 87, DQM1 = 79
2115 22:55:59.571942 DQ Delay:
2116 22:55:59.575139 DQ0 =88, DQ1 =84, DQ2 =76, DQ3 =84
2117 22:55:59.578791 DQ4 =88, DQ5 =96, DQ6 =100, DQ7 =84
2118 22:55:59.581517 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
2119 22:55:59.584784 DQ12 =88, DQ13 =84, DQ14 =88, DQ15 =88
2120 22:55:59.584866
2121 22:55:59.584931
2122 22:55:59.594963 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f17, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 402 ps
2123 22:55:59.595046 CH1 RK1: MR19=606, MR18=1F17
2124 22:55:59.601547 CH1_RK1: MR19=0x606, MR18=0x1F17, DQSOSC=402, MR23=63, INC=91, DEC=60
2125 22:55:59.604844 [RxdqsGatingPostProcess] freq 800
2126 22:55:59.611755 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2127 22:55:59.615033 Pre-setting of DQS Precalculation
2128 22:55:59.617920 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2129 22:55:59.624594 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2130 22:55:59.634693 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2131 22:55:59.634816
2132 22:55:59.634937
2133 22:55:59.637929 [Calibration Summary] 1600 Mbps
2134 22:55:59.638062 CH 0, Rank 0
2135 22:55:59.641394 SW Impedance : PASS
2136 22:55:59.641528 DUTY Scan : NO K
2137 22:55:59.644580 ZQ Calibration : PASS
2138 22:55:59.647946 Jitter Meter : NO K
2139 22:55:59.648117 CBT Training : PASS
2140 22:55:59.650996 Write leveling : PASS
2141 22:55:59.651168 RX DQS gating : PASS
2142 22:55:59.654886 RX DQ/DQS(RDDQC) : PASS
2143 22:55:59.658269 TX DQ/DQS : PASS
2144 22:55:59.658507 RX DATLAT : PASS
2145 22:55:59.661552 RX DQ/DQS(Engine): PASS
2146 22:55:59.664588 TX OE : NO K
2147 22:55:59.664886 All Pass.
2148 22:55:59.665121
2149 22:55:59.665337 CH 0, Rank 1
2150 22:55:59.667901 SW Impedance : PASS
2151 22:55:59.671815 DUTY Scan : NO K
2152 22:55:59.672244 ZQ Calibration : PASS
2153 22:55:59.674883 Jitter Meter : NO K
2154 22:55:59.678027 CBT Training : PASS
2155 22:55:59.678460 Write leveling : PASS
2156 22:55:59.681485 RX DQS gating : PASS
2157 22:55:59.684473 RX DQ/DQS(RDDQC) : PASS
2158 22:55:59.684940 TX DQ/DQS : PASS
2159 22:55:59.687758 RX DATLAT : PASS
2160 22:55:59.691111 RX DQ/DQS(Engine): PASS
2161 22:55:59.691529 TX OE : NO K
2162 22:55:59.694708 All Pass.
2163 22:55:59.695121
2164 22:55:59.695448 CH 1, Rank 0
2165 22:55:59.698029 SW Impedance : PASS
2166 22:55:59.698446 DUTY Scan : NO K
2167 22:55:59.701251 ZQ Calibration : PASS
2168 22:55:59.704481 Jitter Meter : NO K
2169 22:55:59.704925 CBT Training : PASS
2170 22:55:59.707798 Write leveling : PASS
2171 22:55:59.708214 RX DQS gating : PASS
2172 22:55:59.711116 RX DQ/DQS(RDDQC) : PASS
2173 22:55:59.714664 TX DQ/DQS : PASS
2174 22:55:59.715081 RX DATLAT : PASS
2175 22:55:59.717980 RX DQ/DQS(Engine): PASS
2176 22:55:59.721161 TX OE : NO K
2177 22:55:59.721581 All Pass.
2178 22:55:59.721911
2179 22:55:59.722219 CH 1, Rank 1
2180 22:55:59.724235 SW Impedance : PASS
2181 22:55:59.727607 DUTY Scan : NO K
2182 22:55:59.728024 ZQ Calibration : PASS
2183 22:55:59.731501 Jitter Meter : NO K
2184 22:55:59.734363 CBT Training : PASS
2185 22:55:59.734914 Write leveling : PASS
2186 22:55:59.737944 RX DQS gating : PASS
2187 22:55:59.741273 RX DQ/DQS(RDDQC) : PASS
2188 22:55:59.741691 TX DQ/DQS : PASS
2189 22:55:59.744613 RX DATLAT : PASS
2190 22:55:59.747667 RX DQ/DQS(Engine): PASS
2191 22:55:59.748082 TX OE : NO K
2192 22:55:59.748436 All Pass.
2193 22:55:59.751131
2194 22:55:59.751542 DramC Write-DBI off
2195 22:55:59.754669 PER_BANK_REFRESH: Hybrid Mode
2196 22:55:59.755086 TX_TRACKING: ON
2197 22:55:59.757685 [GetDramInforAfterCalByMRR] Vendor 6.
2198 22:55:59.760983 [GetDramInforAfterCalByMRR] Revision 606.
2199 22:55:59.767604 [GetDramInforAfterCalByMRR] Revision 2 0.
2200 22:55:59.768109 MR0 0x3b3b
2201 22:55:59.768675 MR8 0x5151
2202 22:55:59.770799 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2203 22:55:59.771214
2204 22:55:59.774035 MR0 0x3b3b
2205 22:55:59.774449 MR8 0x5151
2206 22:55:59.777527 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2207 22:55:59.777949
2208 22:55:59.787504 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2209 22:55:59.790857 [FAST_K] Save calibration result to emmc
2210 22:55:59.794460 [FAST_K] Save calibration result to emmc
2211 22:55:59.797633 dram_init: config_dvfs: 1
2212 22:55:59.801328 dramc_set_vcore_voltage set vcore to 662500
2213 22:55:59.804006 Read voltage for 1200, 2
2214 22:55:59.804427 Vio18 = 0
2215 22:55:59.804895 Vcore = 662500
2216 22:55:59.807621 Vdram = 0
2217 22:55:59.808040 Vddq = 0
2218 22:55:59.808370 Vmddr = 0
2219 22:55:59.814297 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2220 22:55:59.817425 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2221 22:55:59.820813 MEM_TYPE=3, freq_sel=15
2222 22:55:59.824961 sv_algorithm_assistance_LP4_1600
2223 22:55:59.827489 ============ PULL DRAM RESETB DOWN ============
2224 22:55:59.830683 ========== PULL DRAM RESETB DOWN end =========
2225 22:55:59.837375 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2226 22:55:59.840593 ===================================
2227 22:55:59.841024 LPDDR4 DRAM CONFIGURATION
2228 22:55:59.844117 ===================================
2229 22:55:59.847709 EX_ROW_EN[0] = 0x0
2230 22:55:59.850507 EX_ROW_EN[1] = 0x0
2231 22:55:59.851105 LP4Y_EN = 0x0
2232 22:55:59.854064 WORK_FSP = 0x0
2233 22:55:59.854487 WL = 0x4
2234 22:55:59.857451 RL = 0x4
2235 22:55:59.857875 BL = 0x2
2236 22:55:59.860820 RPST = 0x0
2237 22:55:59.861373 RD_PRE = 0x0
2238 22:55:59.863852 WR_PRE = 0x1
2239 22:55:59.864273 WR_PST = 0x0
2240 22:55:59.867231 DBI_WR = 0x0
2241 22:55:59.867807 DBI_RD = 0x0
2242 22:55:59.870748 OTF = 0x1
2243 22:55:59.873775 ===================================
2244 22:55:59.877256 ===================================
2245 22:55:59.877679 ANA top config
2246 22:55:59.880630 ===================================
2247 22:55:59.883700 DLL_ASYNC_EN = 0
2248 22:55:59.887503 ALL_SLAVE_EN = 0
2249 22:55:59.887927 NEW_RANK_MODE = 1
2250 22:55:59.890402 DLL_IDLE_MODE = 1
2251 22:55:59.893824 LP45_APHY_COMB_EN = 1
2252 22:55:59.897145 TX_ODT_DIS = 1
2253 22:55:59.900510 NEW_8X_MODE = 1
2254 22:55:59.903655 ===================================
2255 22:55:59.906976 ===================================
2256 22:55:59.910407 data_rate = 2400
2257 22:55:59.910833 CKR = 1
2258 22:55:59.913584 DQ_P2S_RATIO = 8
2259 22:55:59.917228 ===================================
2260 22:55:59.920781 CA_P2S_RATIO = 8
2261 22:55:59.923466 DQ_CA_OPEN = 0
2262 22:55:59.927298 DQ_SEMI_OPEN = 0
2263 22:55:59.927721 CA_SEMI_OPEN = 0
2264 22:55:59.930209 CA_FULL_RATE = 0
2265 22:55:59.933572 DQ_CKDIV4_EN = 0
2266 22:55:59.936817 CA_CKDIV4_EN = 0
2267 22:55:59.940394 CA_PREDIV_EN = 0
2268 22:55:59.943833 PH8_DLY = 17
2269 22:55:59.944267 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2270 22:55:59.947089 DQ_AAMCK_DIV = 4
2271 22:55:59.950176 CA_AAMCK_DIV = 4
2272 22:55:59.953746 CA_ADMCK_DIV = 4
2273 22:55:59.957001 DQ_TRACK_CA_EN = 0
2274 22:55:59.960024 CA_PICK = 1200
2275 22:55:59.963705 CA_MCKIO = 1200
2276 22:55:59.964132 MCKIO_SEMI = 0
2277 22:55:59.966771 PLL_FREQ = 2366
2278 22:55:59.970004 DQ_UI_PI_RATIO = 32
2279 22:55:59.973808 CA_UI_PI_RATIO = 0
2280 22:55:59.976725 ===================================
2281 22:55:59.979956 ===================================
2282 22:55:59.983692 memory_type:LPDDR4
2283 22:55:59.984117 GP_NUM : 10
2284 22:55:59.986907 SRAM_EN : 1
2285 22:55:59.989703 MD32_EN : 0
2286 22:55:59.992951 ===================================
2287 22:55:59.993381 [ANA_INIT] >>>>>>>>>>>>>>
2288 22:55:59.996399 <<<<<< [CONFIGURE PHASE]: ANA_TX
2289 22:55:59.999864 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2290 22:56:00.003177 ===================================
2291 22:56:00.006872 data_rate = 2400,PCW = 0X5b00
2292 22:56:00.010154 ===================================
2293 22:56:00.013125 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2294 22:56:00.020243 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2295 22:56:00.023071 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2296 22:56:00.030175 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2297 22:56:00.033197 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2298 22:56:00.036476 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2299 22:56:00.039702 [ANA_INIT] flow start
2300 22:56:00.040128 [ANA_INIT] PLL >>>>>>>>
2301 22:56:00.042754 [ANA_INIT] PLL <<<<<<<<
2302 22:56:00.046139 [ANA_INIT] MIDPI >>>>>>>>
2303 22:56:00.046564 [ANA_INIT] MIDPI <<<<<<<<
2304 22:56:00.049568 [ANA_INIT] DLL >>>>>>>>
2305 22:56:00.052738 [ANA_INIT] DLL <<<<<<<<
2306 22:56:00.053164 [ANA_INIT] flow end
2307 22:56:00.056392 ============ LP4 DIFF to SE enter ============
2308 22:56:00.063098 ============ LP4 DIFF to SE exit ============
2309 22:56:00.063528 [ANA_INIT] <<<<<<<<<<<<<
2310 22:56:00.066323 [Flow] Enable top DCM control >>>>>
2311 22:56:00.069555 [Flow] Enable top DCM control <<<<<
2312 22:56:00.072815 Enable DLL master slave shuffle
2313 22:56:00.079241 ==============================================================
2314 22:56:00.082705 Gating Mode config
2315 22:56:00.085914 ==============================================================
2316 22:56:00.089141 Config description:
2317 22:56:00.099219 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2318 22:56:00.106520 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2319 22:56:00.109480 SELPH_MODE 0: By rank 1: By Phase
2320 22:56:00.115808 ==============================================================
2321 22:56:00.119274 GAT_TRACK_EN = 1
2322 22:56:00.122740 RX_GATING_MODE = 2
2323 22:56:00.123205 RX_GATING_TRACK_MODE = 2
2324 22:56:00.126118 SELPH_MODE = 1
2325 22:56:00.129418 PICG_EARLY_EN = 1
2326 22:56:00.132722 VALID_LAT_VALUE = 1
2327 22:56:00.138896 ==============================================================
2328 22:56:00.142531 Enter into Gating configuration >>>>
2329 22:56:00.145507 Exit from Gating configuration <<<<
2330 22:56:00.148880 Enter into DVFS_PRE_config >>>>>
2331 22:56:00.158696 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2332 22:56:00.162157 Exit from DVFS_PRE_config <<<<<
2333 22:56:00.166196 Enter into PICG configuration >>>>
2334 22:56:00.169185 Exit from PICG configuration <<<<
2335 22:56:00.171847 [RX_INPUT] configuration >>>>>
2336 22:56:00.175578 [RX_INPUT] configuration <<<<<
2337 22:56:00.178765 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2338 22:56:00.185251 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2339 22:56:00.191845 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2340 22:56:00.198877 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2341 22:56:00.205056 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2342 22:56:00.208444 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2343 22:56:00.215124 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2344 22:56:00.218807 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2345 22:56:00.222021 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2346 22:56:00.225345 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2347 22:56:00.231986 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2348 22:56:00.235151 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2349 22:56:00.238541 ===================================
2350 22:56:00.241869 LPDDR4 DRAM CONFIGURATION
2351 22:56:00.245395 ===================================
2352 22:56:00.245821 EX_ROW_EN[0] = 0x0
2353 22:56:00.248611 EX_ROW_EN[1] = 0x0
2354 22:56:00.249037 LP4Y_EN = 0x0
2355 22:56:00.251781 WORK_FSP = 0x0
2356 22:56:00.252205 WL = 0x4
2357 22:56:00.255293 RL = 0x4
2358 22:56:00.255756 BL = 0x2
2359 22:56:00.258600 RPST = 0x0
2360 22:56:00.259015 RD_PRE = 0x0
2361 22:56:00.261770 WR_PRE = 0x1
2362 22:56:00.262231 WR_PST = 0x0
2363 22:56:00.264891 DBI_WR = 0x0
2364 22:56:00.265306 DBI_RD = 0x0
2365 22:56:00.268754 OTF = 0x1
2366 22:56:00.271494 ===================================
2367 22:56:00.274524 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2368 22:56:00.277876 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2369 22:56:00.284634 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2370 22:56:00.288130 ===================================
2371 22:56:00.291570 LPDDR4 DRAM CONFIGURATION
2372 22:56:00.294938 ===================================
2373 22:56:00.295490 EX_ROW_EN[0] = 0x10
2374 22:56:00.298194 EX_ROW_EN[1] = 0x0
2375 22:56:00.298605 LP4Y_EN = 0x0
2376 22:56:00.301067 WORK_FSP = 0x0
2377 22:56:00.301486 WL = 0x4
2378 22:56:00.304967 RL = 0x4
2379 22:56:00.305576 BL = 0x2
2380 22:56:00.308457 RPST = 0x0
2381 22:56:00.309154 RD_PRE = 0x0
2382 22:56:00.311216 WR_PRE = 0x1
2383 22:56:00.311784 WR_PST = 0x0
2384 22:56:00.315068 DBI_WR = 0x0
2385 22:56:00.315595 DBI_RD = 0x0
2386 22:56:00.317444 OTF = 0x1
2387 22:56:00.321281 ===================================
2388 22:56:00.327428 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2389 22:56:00.327508 ==
2390 22:56:00.330817 Dram Type= 6, Freq= 0, CH_0, rank 0
2391 22:56:00.333992 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2392 22:56:00.334069 ==
2393 22:56:00.337386 [Duty_Offset_Calibration]
2394 22:56:00.337456 B0:1 B1:-1 CA:0
2395 22:56:00.337520
2396 22:56:00.340719 [DutyScan_Calibration_Flow] k_type=0
2397 22:56:00.351297
2398 22:56:00.351380 ==CLK 0==
2399 22:56:00.354826 Final CLK duty delay cell = 0
2400 22:56:00.358131 [0] MAX Duty = 5094%(X100), DQS PI = 16
2401 22:56:00.361391 [0] MIN Duty = 4875%(X100), DQS PI = 8
2402 22:56:00.364547 [0] AVG Duty = 4984%(X100)
2403 22:56:00.364636
2404 22:56:00.367882 CH0 CLK Duty spec in!! Max-Min= 219%
2405 22:56:00.371360 [DutyScan_Calibration_Flow] ====Done====
2406 22:56:00.371472
2407 22:56:00.374566 [DutyScan_Calibration_Flow] k_type=1
2408 22:56:00.389051
2409 22:56:00.389127 ==DQS 0 ==
2410 22:56:00.392577 Final DQS duty delay cell = -4
2411 22:56:00.396201 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2412 22:56:00.398898 [-4] MIN Duty = 4875%(X100), DQS PI = 54
2413 22:56:00.402729 [-4] AVG Duty = 4968%(X100)
2414 22:56:00.402829
2415 22:56:00.402919 ==DQS 1 ==
2416 22:56:00.405849 Final DQS duty delay cell = -4
2417 22:56:00.409380 [-4] MAX Duty = 5000%(X100), DQS PI = 6
2418 22:56:00.412463 [-4] MIN Duty = 4876%(X100), DQS PI = 22
2419 22:56:00.415836 [-4] AVG Duty = 4938%(X100)
2420 22:56:00.415905
2421 22:56:00.419358 CH0 DQS 0 Duty spec in!! Max-Min= 187%
2422 22:56:00.419473
2423 22:56:00.422341 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2424 22:56:00.425891 [DutyScan_Calibration_Flow] ====Done====
2425 22:56:00.425961
2426 22:56:00.429010 [DutyScan_Calibration_Flow] k_type=3
2427 22:56:00.447337
2428 22:56:00.447438 ==DQM 0 ==
2429 22:56:00.450525 Final DQM duty delay cell = 0
2430 22:56:00.453747 [0] MAX Duty = 5031%(X100), DQS PI = 16
2431 22:56:00.457097 [0] MIN Duty = 4875%(X100), DQS PI = 6
2432 22:56:00.460183 [0] AVG Duty = 4953%(X100)
2433 22:56:00.460256
2434 22:56:00.460315 ==DQM 1 ==
2435 22:56:00.463590 Final DQM duty delay cell = 4
2436 22:56:00.466982 [4] MAX Duty = 5187%(X100), DQS PI = 14
2437 22:56:00.469932 [4] MIN Duty = 5000%(X100), DQS PI = 24
2438 22:56:00.473580 [4] AVG Duty = 5093%(X100)
2439 22:56:00.473682
2440 22:56:00.477056 CH0 DQM 0 Duty spec in!! Max-Min= 156%
2441 22:56:00.477154
2442 22:56:00.480476 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2443 22:56:00.483608 [DutyScan_Calibration_Flow] ====Done====
2444 22:56:00.483706
2445 22:56:00.486475 [DutyScan_Calibration_Flow] k_type=2
2446 22:56:00.503055
2447 22:56:00.503158 ==DQ 0 ==
2448 22:56:00.506204 Final DQ duty delay cell = -4
2449 22:56:00.509850 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2450 22:56:00.512674 [-4] MIN Duty = 4907%(X100), DQS PI = 48
2451 22:56:00.516340 [-4] AVG Duty = 4969%(X100)
2452 22:56:00.516448
2453 22:56:00.516578 ==DQ 1 ==
2454 22:56:00.519445 Final DQ duty delay cell = 0
2455 22:56:00.522862 [0] MAX Duty = 5093%(X100), DQS PI = 4
2456 22:56:00.525874 [0] MIN Duty = 4969%(X100), DQS PI = 40
2457 22:56:00.529607 [0] AVG Duty = 5031%(X100)
2458 22:56:00.529687
2459 22:56:00.533085 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2460 22:56:00.533164
2461 22:56:00.536123 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2462 22:56:00.539593 [DutyScan_Calibration_Flow] ====Done====
2463 22:56:00.539675 ==
2464 22:56:00.542881 Dram Type= 6, Freq= 0, CH_1, rank 0
2465 22:56:00.546157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2466 22:56:00.546240 ==
2467 22:56:00.549461 [Duty_Offset_Calibration]
2468 22:56:00.549543 B0:-1 B1:1 CA:2
2469 22:56:00.549608
2470 22:56:00.552608 [DutyScan_Calibration_Flow] k_type=0
2471 22:56:00.563381
2472 22:56:00.563484 ==CLK 0==
2473 22:56:00.566366 Final CLK duty delay cell = 0
2474 22:56:00.569538 [0] MAX Duty = 5156%(X100), DQS PI = 20
2475 22:56:00.572841 [0] MIN Duty = 4969%(X100), DQS PI = 60
2476 22:56:00.576336 [0] AVG Duty = 5062%(X100)
2477 22:56:00.576419
2478 22:56:00.579663 CH1 CLK Duty spec in!! Max-Min= 187%
2479 22:56:00.583170 [DutyScan_Calibration_Flow] ====Done====
2480 22:56:00.583257
2481 22:56:00.586606 [DutyScan_Calibration_Flow] k_type=1
2482 22:56:00.602722
2483 22:56:00.602803 ==DQS 0 ==
2484 22:56:00.605893 Final DQS duty delay cell = 0
2485 22:56:00.609259 [0] MAX Duty = 5156%(X100), DQS PI = 48
2486 22:56:00.612667 [0] MIN Duty = 4907%(X100), DQS PI = 8
2487 22:56:00.615546 [0] AVG Duty = 5031%(X100)
2488 22:56:00.615628
2489 22:56:00.615692 ==DQS 1 ==
2490 22:56:00.619242 Final DQS duty delay cell = 0
2491 22:56:00.622716 [0] MAX Duty = 5094%(X100), DQS PI = 12
2492 22:56:00.625544 [0] MIN Duty = 4969%(X100), DQS PI = 56
2493 22:56:00.628966 [0] AVG Duty = 5031%(X100)
2494 22:56:00.629048
2495 22:56:00.632165 CH1 DQS 0 Duty spec in!! Max-Min= 249%
2496 22:56:00.632247
2497 22:56:00.635355 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2498 22:56:00.638877 [DutyScan_Calibration_Flow] ====Done====
2499 22:56:00.638958
2500 22:56:00.642031 [DutyScan_Calibration_Flow] k_type=3
2501 22:56:00.658236
2502 22:56:00.658317 ==DQM 0 ==
2503 22:56:00.661583 Final DQM duty delay cell = -4
2504 22:56:00.664890 [-4] MAX Duty = 5062%(X100), DQS PI = 34
2505 22:56:00.668145 [-4] MIN Duty = 4876%(X100), DQS PI = 6
2506 22:56:00.671148 [-4] AVG Duty = 4969%(X100)
2507 22:56:00.671230
2508 22:56:00.671295 ==DQM 1 ==
2509 22:56:00.674794 Final DQM duty delay cell = 0
2510 22:56:00.678257 [0] MAX Duty = 5187%(X100), DQS PI = 6
2511 22:56:00.681136 [0] MIN Duty = 5000%(X100), DQS PI = 28
2512 22:56:00.684504 [0] AVG Duty = 5093%(X100)
2513 22:56:00.684626
2514 22:56:00.687791 CH1 DQM 0 Duty spec in!! Max-Min= 186%
2515 22:56:00.687873
2516 22:56:00.691263 CH1 DQM 1 Duty spec in!! Max-Min= 187%
2517 22:56:00.694644 [DutyScan_Calibration_Flow] ====Done====
2518 22:56:00.694726
2519 22:56:00.697845 [DutyScan_Calibration_Flow] k_type=2
2520 22:56:00.714955
2521 22:56:00.715038 ==DQ 0 ==
2522 22:56:00.718250 Final DQ duty delay cell = 0
2523 22:56:00.721742 [0] MAX Duty = 5187%(X100), DQS PI = 30
2524 22:56:00.724873 [0] MIN Duty = 4907%(X100), DQS PI = 6
2525 22:56:00.724957 [0] AVG Duty = 5047%(X100)
2526 22:56:00.727991
2527 22:56:00.728073 ==DQ 1 ==
2528 22:56:00.731449 Final DQ duty delay cell = 0
2529 22:56:00.734373 [0] MAX Duty = 5156%(X100), DQS PI = 10
2530 22:56:00.737991 [0] MIN Duty = 4969%(X100), DQS PI = 60
2531 22:56:00.738074 [0] AVG Duty = 5062%(X100)
2532 22:56:00.741191
2533 22:56:00.744671 CH1 DQ 0 Duty spec in!! Max-Min= 280%
2534 22:56:00.744753
2535 22:56:00.747902 CH1 DQ 1 Duty spec in!! Max-Min= 187%
2536 22:56:00.751233 [DutyScan_Calibration_Flow] ====Done====
2537 22:56:00.754888 nWR fixed to 30
2538 22:56:00.754971 [ModeRegInit_LP4] CH0 RK0
2539 22:56:00.757607 [ModeRegInit_LP4] CH0 RK1
2540 22:56:00.761171 [ModeRegInit_LP4] CH1 RK0
2541 22:56:00.764250 [ModeRegInit_LP4] CH1 RK1
2542 22:56:00.764332 match AC timing 7
2543 22:56:00.771163 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2544 22:56:00.774043 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2545 22:56:00.777774 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2546 22:56:00.784232 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2547 22:56:00.787495 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2548 22:56:00.787578 ==
2549 22:56:00.791003 Dram Type= 6, Freq= 0, CH_0, rank 0
2550 22:56:00.794593 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2551 22:56:00.794677 ==
2552 22:56:00.800835 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2553 22:56:00.807599 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2554 22:56:00.814887 [CA 0] Center 39 (9~70) winsize 62
2555 22:56:00.817995 [CA 1] Center 39 (9~69) winsize 61
2556 22:56:00.821696 [CA 2] Center 35 (5~66) winsize 62
2557 22:56:00.824925 [CA 3] Center 35 (5~66) winsize 62
2558 22:56:00.828337 [CA 4] Center 33 (4~63) winsize 60
2559 22:56:00.831294 [CA 5] Center 33 (3~63) winsize 61
2560 22:56:00.831376
2561 22:56:00.834661 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2562 22:56:00.834744
2563 22:56:00.838156 [CATrainingPosCal] consider 1 rank data
2564 22:56:00.841702 u2DelayCellTimex100 = 270/100 ps
2565 22:56:00.845134 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2566 22:56:00.851560 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2567 22:56:00.854671 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2568 22:56:00.857812 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2569 22:56:00.861353 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
2570 22:56:00.864416 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2571 22:56:00.864498
2572 22:56:00.868379 CA PerBit enable=1, Macro0, CA PI delay=33
2573 22:56:00.868461
2574 22:56:00.871447 [CBTSetCACLKResult] CA Dly = 33
2575 22:56:00.871530 CS Dly: 8 (0~39)
2576 22:56:00.874957 ==
2577 22:56:00.875040 Dram Type= 6, Freq= 0, CH_0, rank 1
2578 22:56:00.881333 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2579 22:56:00.881420 ==
2580 22:56:00.884764 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2581 22:56:00.891163 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2582 22:56:00.900255 [CA 0] Center 39 (9~70) winsize 62
2583 22:56:00.903841 [CA 1] Center 39 (9~70) winsize 62
2584 22:56:00.907423 [CA 2] Center 35 (5~66) winsize 62
2585 22:56:00.910436 [CA 3] Center 34 (4~65) winsize 62
2586 22:56:00.913452 [CA 4] Center 33 (3~64) winsize 62
2587 22:56:00.917170 [CA 5] Center 33 (3~63) winsize 61
2588 22:56:00.917244
2589 22:56:00.920355 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2590 22:56:00.920474
2591 22:56:00.924114 [CATrainingPosCal] consider 2 rank data
2592 22:56:00.926958 u2DelayCellTimex100 = 270/100 ps
2593 22:56:00.930185 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2594 22:56:00.933697 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2595 22:56:00.940409 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2596 22:56:00.943995 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2597 22:56:00.946990 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
2598 22:56:00.950407 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2599 22:56:00.950482
2600 22:56:00.953650 CA PerBit enable=1, Macro0, CA PI delay=33
2601 22:56:00.953728
2602 22:56:00.956702 [CBTSetCACLKResult] CA Dly = 33
2603 22:56:00.956775 CS Dly: 8 (0~40)
2604 22:56:00.956836
2605 22:56:00.963625 ----->DramcWriteLeveling(PI) begin...
2606 22:56:00.963701 ==
2607 22:56:00.966971 Dram Type= 6, Freq= 0, CH_0, rank 0
2608 22:56:00.970353 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2609 22:56:00.970428 ==
2610 22:56:00.973894 Write leveling (Byte 0): 32 => 32
2611 22:56:00.977416 Write leveling (Byte 1): 30 => 30
2612 22:56:00.979945 DramcWriteLeveling(PI) end<-----
2613 22:56:00.980021
2614 22:56:00.980084 ==
2615 22:56:00.983842 Dram Type= 6, Freq= 0, CH_0, rank 0
2616 22:56:00.986919 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2617 22:56:00.986990 ==
2618 22:56:00.990009 [Gating] SW mode calibration
2619 22:56:00.996603 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2620 22:56:01.003255 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2621 22:56:01.007056 0 15 0 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
2622 22:56:01.010084 0 15 4 | B1->B0 | 2b2a 3434 | 1 1 | (0 0) (1 1)
2623 22:56:01.016664 0 15 8 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
2624 22:56:01.019917 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2625 22:56:01.023182 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2626 22:56:01.030176 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2627 22:56:01.033145 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2628 22:56:01.036585 0 15 28 | B1->B0 | 3434 2d2d | 1 1 | (1 1) (1 0)
2629 22:56:01.043692 1 0 0 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)
2630 22:56:01.046696 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2631 22:56:01.049912 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2632 22:56:01.053466 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2633 22:56:01.059814 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2634 22:56:01.062865 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2635 22:56:01.066286 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2636 22:56:01.072977 1 0 28 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
2637 22:56:01.076376 1 1 0 | B1->B0 | 2c2b 4646 | 1 0 | (1 1) (0 0)
2638 22:56:01.079471 1 1 4 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
2639 22:56:01.086068 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2640 22:56:01.089588 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2641 22:56:01.092641 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2642 22:56:01.099345 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2643 22:56:01.102824 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2644 22:56:01.106046 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2645 22:56:01.112794 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2646 22:56:01.115984 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2647 22:56:01.119532 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2648 22:56:01.125979 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2649 22:56:01.129405 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2650 22:56:01.132732 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2651 22:56:01.139545 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2652 22:56:01.142771 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2653 22:56:01.146051 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2654 22:56:01.152617 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2655 22:56:01.156089 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2656 22:56:01.159541 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2657 22:56:01.166177 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2658 22:56:01.169486 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2659 22:56:01.172825 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2660 22:56:01.179013 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2661 22:56:01.183005 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2662 22:56:01.186373 Total UI for P1: 0, mck2ui 16
2663 22:56:01.189757 best dqsien dly found for B0: ( 1, 3, 28)
2664 22:56:01.192816 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2665 22:56:01.195819 Total UI for P1: 0, mck2ui 16
2666 22:56:01.199352 best dqsien dly found for B1: ( 1, 4, 0)
2667 22:56:01.202265 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2668 22:56:01.206078 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2669 22:56:01.206148
2670 22:56:01.209266 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2671 22:56:01.215432 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2672 22:56:01.215507 [Gating] SW calibration Done
2673 22:56:01.215569 ==
2674 22:56:01.219520 Dram Type= 6, Freq= 0, CH_0, rank 0
2675 22:56:01.225258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2676 22:56:01.225333 ==
2677 22:56:01.225395 RX Vref Scan: 0
2678 22:56:01.225457
2679 22:56:01.228639 RX Vref 0 -> 0, step: 1
2680 22:56:01.228712
2681 22:56:01.232199 RX Delay -40 -> 252, step: 8
2682 22:56:01.236064 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2683 22:56:01.239506 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2684 22:56:01.242272 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2685 22:56:01.248738 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2686 22:56:01.252317 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2687 22:56:01.255457 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2688 22:56:01.258459 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2689 22:56:01.262068 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2690 22:56:01.268894 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2691 22:56:01.272062 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2692 22:56:01.275453 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2693 22:56:01.278359 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2694 22:56:01.282169 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2695 22:56:01.288513 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2696 22:56:01.292678 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2697 22:56:01.295398 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2698 22:56:01.295471 ==
2699 22:56:01.298750 Dram Type= 6, Freq= 0, CH_0, rank 0
2700 22:56:01.301680 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2701 22:56:01.301753 ==
2702 22:56:01.305393 DQS Delay:
2703 22:56:01.305464 DQS0 = 0, DQS1 = 0
2704 22:56:01.308281 DQM Delay:
2705 22:56:01.308350 DQM0 = 119, DQM1 = 106
2706 22:56:01.308417 DQ Delay:
2707 22:56:01.314935 DQ0 =119, DQ1 =119, DQ2 =115, DQ3 =115
2708 22:56:01.318544 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =127
2709 22:56:01.321620 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2710 22:56:01.324708 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2711 22:56:01.324780
2712 22:56:01.324841
2713 22:56:01.324899 ==
2714 22:56:01.328864 Dram Type= 6, Freq= 0, CH_0, rank 0
2715 22:56:01.331585 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2716 22:56:01.331660 ==
2717 22:56:01.331719
2718 22:56:01.331777
2719 22:56:01.334761 TX Vref Scan disable
2720 22:56:01.338501 == TX Byte 0 ==
2721 22:56:01.341702 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2722 22:56:01.344804 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2723 22:56:01.348253 == TX Byte 1 ==
2724 22:56:01.351811 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2725 22:56:01.355086 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2726 22:56:01.355160 ==
2727 22:56:01.358277 Dram Type= 6, Freq= 0, CH_0, rank 0
2728 22:56:01.361800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2729 22:56:01.364422 ==
2730 22:56:01.375233 TX Vref=22, minBit 6, minWin=25, winSum=417
2731 22:56:01.378418 TX Vref=24, minBit 1, minWin=25, winSum=419
2732 22:56:01.381861 TX Vref=26, minBit 1, minWin=26, winSum=428
2733 22:56:01.385208 TX Vref=28, minBit 5, minWin=26, winSum=432
2734 22:56:01.388743 TX Vref=30, minBit 5, minWin=26, winSum=432
2735 22:56:01.391617 TX Vref=32, minBit 4, minWin=26, winSum=428
2736 22:56:01.398056 [TxChooseVref] Worse bit 5, Min win 26, Win sum 432, Final Vref 28
2737 22:56:01.398139
2738 22:56:01.401759 Final TX Range 1 Vref 28
2739 22:56:01.401832
2740 22:56:01.401900 ==
2741 22:56:01.404712 Dram Type= 6, Freq= 0, CH_0, rank 0
2742 22:56:01.408313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2743 22:56:01.408401 ==
2744 22:56:01.408467
2745 22:56:01.411900
2746 22:56:01.411982 TX Vref Scan disable
2747 22:56:01.415097 == TX Byte 0 ==
2748 22:56:01.418102 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2749 22:56:01.421717 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2750 22:56:01.425076 == TX Byte 1 ==
2751 22:56:01.428461 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2752 22:56:01.431334 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2753 22:56:01.431417
2754 22:56:01.434990 [DATLAT]
2755 22:56:01.435072 Freq=1200, CH0 RK0
2756 22:56:01.435138
2757 22:56:01.437763 DATLAT Default: 0xd
2758 22:56:01.437859 0, 0xFFFF, sum = 0
2759 22:56:01.441768 1, 0xFFFF, sum = 0
2760 22:56:01.441871 2, 0xFFFF, sum = 0
2761 22:56:01.444462 3, 0xFFFF, sum = 0
2762 22:56:01.444586 4, 0xFFFF, sum = 0
2763 22:56:01.448208 5, 0xFFFF, sum = 0
2764 22:56:01.448324 6, 0xFFFF, sum = 0
2765 22:56:01.451686 7, 0xFFFF, sum = 0
2766 22:56:01.454742 8, 0xFFFF, sum = 0
2767 22:56:01.454826 9, 0xFFFF, sum = 0
2768 22:56:01.458008 10, 0xFFFF, sum = 0
2769 22:56:01.458092 11, 0xFFFF, sum = 0
2770 22:56:01.461331 12, 0x0, sum = 1
2771 22:56:01.461414 13, 0x0, sum = 2
2772 22:56:01.464710 14, 0x0, sum = 3
2773 22:56:01.464794 15, 0x0, sum = 4
2774 22:56:01.464861 best_step = 13
2775 22:56:01.464921
2776 22:56:01.468153 ==
2777 22:56:01.471111 Dram Type= 6, Freq= 0, CH_0, rank 0
2778 22:56:01.474894 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2779 22:56:01.474978 ==
2780 22:56:01.475044 RX Vref Scan: 1
2781 22:56:01.475105
2782 22:56:01.478132 Set Vref Range= 32 -> 127
2783 22:56:01.478214
2784 22:56:01.481056 RX Vref 32 -> 127, step: 1
2785 22:56:01.481139
2786 22:56:01.484309 RX Delay -21 -> 252, step: 4
2787 22:56:01.484391
2788 22:56:01.487657 Set Vref, RX VrefLevel [Byte0]: 32
2789 22:56:01.490995 [Byte1]: 32
2790 22:56:01.491070
2791 22:56:01.494531 Set Vref, RX VrefLevel [Byte0]: 33
2792 22:56:01.497774 [Byte1]: 33
2793 22:56:01.500993
2794 22:56:01.501067 Set Vref, RX VrefLevel [Byte0]: 34
2795 22:56:01.504506 [Byte1]: 34
2796 22:56:01.508811
2797 22:56:01.508887 Set Vref, RX VrefLevel [Byte0]: 35
2798 22:56:01.511916 [Byte1]: 35
2799 22:56:01.516752
2800 22:56:01.516827 Set Vref, RX VrefLevel [Byte0]: 36
2801 22:56:01.520132 [Byte1]: 36
2802 22:56:01.524546
2803 22:56:01.524634 Set Vref, RX VrefLevel [Byte0]: 37
2804 22:56:01.528333 [Byte1]: 37
2805 22:56:01.532684
2806 22:56:01.532757 Set Vref, RX VrefLevel [Byte0]: 38
2807 22:56:01.535832 [Byte1]: 38
2808 22:56:01.540491
2809 22:56:01.540606 Set Vref, RX VrefLevel [Byte0]: 39
2810 22:56:01.543922 [Byte1]: 39
2811 22:56:01.549042
2812 22:56:01.549120 Set Vref, RX VrefLevel [Byte0]: 40
2813 22:56:01.551575 [Byte1]: 40
2814 22:56:01.556661
2815 22:56:01.556734 Set Vref, RX VrefLevel [Byte0]: 41
2816 22:56:01.559795 [Byte1]: 41
2817 22:56:01.564193
2818 22:56:01.564265 Set Vref, RX VrefLevel [Byte0]: 42
2819 22:56:01.567777 [Byte1]: 42
2820 22:56:01.572153
2821 22:56:01.572226 Set Vref, RX VrefLevel [Byte0]: 43
2822 22:56:01.576065 [Byte1]: 43
2823 22:56:01.580585
2824 22:56:01.580665 Set Vref, RX VrefLevel [Byte0]: 44
2825 22:56:01.583751 [Byte1]: 44
2826 22:56:01.588057
2827 22:56:01.588133 Set Vref, RX VrefLevel [Byte0]: 45
2828 22:56:01.591477 [Byte1]: 45
2829 22:56:01.595965
2830 22:56:01.596041 Set Vref, RX VrefLevel [Byte0]: 46
2831 22:56:01.599882 [Byte1]: 46
2832 22:56:01.604088
2833 22:56:01.604163 Set Vref, RX VrefLevel [Byte0]: 47
2834 22:56:01.607741 [Byte1]: 47
2835 22:56:01.611941
2836 22:56:01.612015 Set Vref, RX VrefLevel [Byte0]: 48
2837 22:56:01.615290 [Byte1]: 48
2838 22:56:01.620167
2839 22:56:01.620245 Set Vref, RX VrefLevel [Byte0]: 49
2840 22:56:01.623358 [Byte1]: 49
2841 22:56:01.628402
2842 22:56:01.628531 Set Vref, RX VrefLevel [Byte0]: 50
2843 22:56:01.631355 [Byte1]: 50
2844 22:56:01.635505
2845 22:56:01.635577 Set Vref, RX VrefLevel [Byte0]: 51
2846 22:56:01.639509 [Byte1]: 51
2847 22:56:01.643623
2848 22:56:01.643700 Set Vref, RX VrefLevel [Byte0]: 52
2849 22:56:01.646883 [Byte1]: 52
2850 22:56:01.651577
2851 22:56:01.651657 Set Vref, RX VrefLevel [Byte0]: 53
2852 22:56:01.655454 [Byte1]: 53
2853 22:56:01.659276
2854 22:56:01.659350 Set Vref, RX VrefLevel [Byte0]: 54
2855 22:56:01.662959 [Byte1]: 54
2856 22:56:01.667213
2857 22:56:01.667285 Set Vref, RX VrefLevel [Byte0]: 55
2858 22:56:01.670591 [Byte1]: 55
2859 22:56:01.675855
2860 22:56:01.675936 Set Vref, RX VrefLevel [Byte0]: 56
2861 22:56:01.678485 [Byte1]: 56
2862 22:56:01.683074
2863 22:56:01.686354 Set Vref, RX VrefLevel [Byte0]: 57
2864 22:56:01.689903 [Byte1]: 57
2865 22:56:01.689975
2866 22:56:01.693065 Set Vref, RX VrefLevel [Byte0]: 58
2867 22:56:01.696433 [Byte1]: 58
2868 22:56:01.696505
2869 22:56:01.699723 Set Vref, RX VrefLevel [Byte0]: 59
2870 22:56:01.703291 [Byte1]: 59
2871 22:56:01.707044
2872 22:56:01.707115 Set Vref, RX VrefLevel [Byte0]: 60
2873 22:56:01.710216 [Byte1]: 60
2874 22:56:01.715278
2875 22:56:01.715352 Set Vref, RX VrefLevel [Byte0]: 61
2876 22:56:01.718349 [Byte1]: 61
2877 22:56:01.723236
2878 22:56:01.723309 Set Vref, RX VrefLevel [Byte0]: 62
2879 22:56:01.726438 [Byte1]: 62
2880 22:56:01.730759
2881 22:56:01.730830 Set Vref, RX VrefLevel [Byte0]: 63
2882 22:56:01.734297 [Byte1]: 63
2883 22:56:01.738834
2884 22:56:01.738905 Set Vref, RX VrefLevel [Byte0]: 64
2885 22:56:01.742065 [Byte1]: 64
2886 22:56:01.746952
2887 22:56:01.747022 Set Vref, RX VrefLevel [Byte0]: 65
2888 22:56:01.750099 [Byte1]: 65
2889 22:56:01.754903
2890 22:56:01.754975 Set Vref, RX VrefLevel [Byte0]: 66
2891 22:56:01.757771 [Byte1]: 66
2892 22:56:01.762821
2893 22:56:01.762893 Set Vref, RX VrefLevel [Byte0]: 67
2894 22:56:01.765839 [Byte1]: 67
2895 22:56:01.770683
2896 22:56:01.770765 Set Vref, RX VrefLevel [Byte0]: 68
2897 22:56:01.773739 [Byte1]: 68
2898 22:56:01.778595
2899 22:56:01.778676 Set Vref, RX VrefLevel [Byte0]: 69
2900 22:56:01.784772 [Byte1]: 69
2901 22:56:01.784853
2902 22:56:01.788441 Set Vref, RX VrefLevel [Byte0]: 70
2903 22:56:01.791777 [Byte1]: 70
2904 22:56:01.791888
2905 22:56:01.795220 Set Vref, RX VrefLevel [Byte0]: 71
2906 22:56:01.797971 [Byte1]: 71
2907 22:56:01.802150
2908 22:56:01.802231 Set Vref, RX VrefLevel [Byte0]: 72
2909 22:56:01.805616 [Byte1]: 72
2910 22:56:01.810521
2911 22:56:01.810607 Set Vref, RX VrefLevel [Byte0]: 73
2912 22:56:01.813139 [Byte1]: 73
2913 22:56:01.818379
2914 22:56:01.818460 Set Vref, RX VrefLevel [Byte0]: 74
2915 22:56:01.821469 [Byte1]: 74
2916 22:56:01.826262
2917 22:56:01.826344 Set Vref, RX VrefLevel [Byte0]: 75
2918 22:56:01.829051 [Byte1]: 75
2919 22:56:01.833958
2920 22:56:01.834039 Set Vref, RX VrefLevel [Byte0]: 76
2921 22:56:01.837422 [Byte1]: 76
2922 22:56:01.841826
2923 22:56:01.841906 Set Vref, RX VrefLevel [Byte0]: 77
2924 22:56:01.845575 [Byte1]: 77
2925 22:56:01.849925
2926 22:56:01.850007 Set Vref, RX VrefLevel [Byte0]: 78
2927 22:56:01.853406 [Byte1]: 78
2928 22:56:01.858206
2929 22:56:01.858286 Final RX Vref Byte 0 = 61 to rank0
2930 22:56:01.861220 Final RX Vref Byte 1 = 59 to rank0
2931 22:56:01.864299 Final RX Vref Byte 0 = 61 to rank1
2932 22:56:01.867513 Final RX Vref Byte 1 = 59 to rank1==
2933 22:56:01.871319 Dram Type= 6, Freq= 0, CH_0, rank 0
2934 22:56:01.877840 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2935 22:56:01.877924 ==
2936 22:56:01.877989 DQS Delay:
2937 22:56:01.878049 DQS0 = 0, DQS1 = 0
2938 22:56:01.880986 DQM Delay:
2939 22:56:01.881067 DQM0 = 119, DQM1 = 107
2940 22:56:01.884702 DQ Delay:
2941 22:56:01.887749 DQ0 =116, DQ1 =120, DQ2 =116, DQ3 =116
2942 22:56:01.890495 DQ4 =120, DQ5 =114, DQ6 =128, DQ7 =126
2943 22:56:01.894194 DQ8 =96, DQ9 =94, DQ10 =110, DQ11 =102
2944 22:56:01.897764 DQ12 =112, DQ13 =110, DQ14 =122, DQ15 =114
2945 22:56:01.897848
2946 22:56:01.897948
2947 22:56:01.907480 [DQSOSCAuto] RK0, (LSB)MR18= 0x10fb, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 403 ps
2948 22:56:01.907563 CH0 RK0: MR19=403, MR18=10FB
2949 22:56:01.914565 CH0_RK0: MR19=0x403, MR18=0x10FB, DQSOSC=403, MR23=63, INC=40, DEC=26
2950 22:56:01.914648
2951 22:56:01.917928 ----->DramcWriteLeveling(PI) begin...
2952 22:56:01.918011 ==
2953 22:56:01.920905 Dram Type= 6, Freq= 0, CH_0, rank 1
2954 22:56:01.927153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2955 22:56:01.927235 ==
2956 22:56:01.930644 Write leveling (Byte 0): 34 => 34
2957 22:56:01.930726 Write leveling (Byte 1): 31 => 31
2958 22:56:01.934105 DramcWriteLeveling(PI) end<-----
2959 22:56:01.934187
2960 22:56:01.934292 ==
2961 22:56:01.937664 Dram Type= 6, Freq= 0, CH_0, rank 1
2962 22:56:01.943719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2963 22:56:01.943802 ==
2964 22:56:01.947651 [Gating] SW mode calibration
2965 22:56:01.953658 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2966 22:56:01.956952 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2967 22:56:01.963880 0 15 0 | B1->B0 | 2525 3434 | 0 0 | (0 0) (0 0)
2968 22:56:01.967372 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2969 22:56:01.970433 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2970 22:56:01.977134 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2971 22:56:01.980145 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2972 22:56:01.983559 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2973 22:56:01.990532 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2974 22:56:01.993950 0 15 28 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 0)
2975 22:56:01.996650 1 0 0 | B1->B0 | 2d2d 2323 | 0 0 | (0 1) (0 0)
2976 22:56:02.003211 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2977 22:56:02.006829 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2978 22:56:02.010186 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2979 22:56:02.017148 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2980 22:56:02.019698 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2981 22:56:02.023147 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2982 22:56:02.030330 1 0 28 | B1->B0 | 2424 3838 | 0 0 | (0 0) (0 0)
2983 22:56:02.033056 1 1 0 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
2984 22:56:02.036936 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2985 22:56:02.043576 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2986 22:56:02.046566 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2987 22:56:02.050365 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2988 22:56:02.053334 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2989 22:56:02.059933 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2990 22:56:02.063171 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2991 22:56:02.066686 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2992 22:56:02.073411 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2993 22:56:02.076453 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2994 22:56:02.080100 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2995 22:56:02.086926 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2996 22:56:02.090200 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2997 22:56:02.093538 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2998 22:56:02.099813 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2999 22:56:02.103056 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3000 22:56:02.106491 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3001 22:56:02.113072 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3002 22:56:02.116255 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3003 22:56:02.119403 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3004 22:56:02.126732 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3005 22:56:02.129561 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3006 22:56:02.133343 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3007 22:56:02.139249 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3008 22:56:02.139332 Total UI for P1: 0, mck2ui 16
3009 22:56:02.145747 best dqsien dly found for B0: ( 1, 3, 28)
3010 22:56:02.145830 Total UI for P1: 0, mck2ui 16
3011 22:56:02.152666 best dqsien dly found for B1: ( 1, 3, 30)
3012 22:56:02.155752 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3013 22:56:02.159315 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
3014 22:56:02.159394
3015 22:56:02.162662 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3016 22:56:02.166385 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
3017 22:56:02.169368 [Gating] SW calibration Done
3018 22:56:02.169445 ==
3019 22:56:02.172749 Dram Type= 6, Freq= 0, CH_0, rank 1
3020 22:56:02.176081 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3021 22:56:02.176163 ==
3022 22:56:02.178959 RX Vref Scan: 0
3023 22:56:02.179036
3024 22:56:02.179116 RX Vref 0 -> 0, step: 1
3025 22:56:02.179198
3026 22:56:02.182654 RX Delay -40 -> 252, step: 8
3027 22:56:02.185940 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
3028 22:56:02.192321 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
3029 22:56:02.195478 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
3030 22:56:02.199335 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3031 22:56:02.202741 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3032 22:56:02.205405 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
3033 22:56:02.211904 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3034 22:56:02.215386 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
3035 22:56:02.218632 iDelay=200, Bit 8, Center 99 (24 ~ 175) 152
3036 22:56:02.222211 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3037 22:56:02.225631 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3038 22:56:02.232422 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3039 22:56:02.235217 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3040 22:56:02.238446 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
3041 22:56:02.242320 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3042 22:56:02.248644 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3043 22:56:02.248721 ==
3044 22:56:02.251898 Dram Type= 6, Freq= 0, CH_0, rank 1
3045 22:56:02.255114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3046 22:56:02.255191 ==
3047 22:56:02.255272 DQS Delay:
3048 22:56:02.258378 DQS0 = 0, DQS1 = 0
3049 22:56:02.258451 DQM Delay:
3050 22:56:02.261480 DQM0 = 116, DQM1 = 109
3051 22:56:02.261556 DQ Delay:
3052 22:56:02.265007 DQ0 =111, DQ1 =123, DQ2 =111, DQ3 =115
3053 22:56:02.268125 DQ4 =115, DQ5 =111, DQ6 =123, DQ7 =123
3054 22:56:02.271492 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =103
3055 22:56:02.275044 DQ12 =115, DQ13 =115, DQ14 =119, DQ15 =119
3056 22:56:02.275159
3057 22:56:02.275255
3058 22:56:02.278256 ==
3059 22:56:02.281264 Dram Type= 6, Freq= 0, CH_0, rank 1
3060 22:56:02.284500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3061 22:56:02.284609 ==
3062 22:56:02.284671
3063 22:56:02.284728
3064 22:56:02.288280 TX Vref Scan disable
3065 22:56:02.288377 == TX Byte 0 ==
3066 22:56:02.291472 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
3067 22:56:02.298231 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
3068 22:56:02.298310 == TX Byte 1 ==
3069 22:56:02.301292 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
3070 22:56:02.308277 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
3071 22:56:02.308353 ==
3072 22:56:02.311903 Dram Type= 6, Freq= 0, CH_0, rank 1
3073 22:56:02.314993 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3074 22:56:02.315065 ==
3075 22:56:02.327032 TX Vref=22, minBit 3, minWin=25, winSum=415
3076 22:56:02.330129 TX Vref=24, minBit 8, minWin=26, winSum=426
3077 22:56:02.333457 TX Vref=26, minBit 13, minWin=25, winSum=428
3078 22:56:02.336898 TX Vref=28, minBit 8, minWin=26, winSum=431
3079 22:56:02.340419 TX Vref=30, minBit 12, minWin=25, winSum=429
3080 22:56:02.346838 TX Vref=32, minBit 9, minWin=26, winSum=431
3081 22:56:02.350076 [TxChooseVref] Worse bit 8, Min win 26, Win sum 431, Final Vref 28
3082 22:56:02.350171
3083 22:56:02.353590 Final TX Range 1 Vref 28
3084 22:56:02.353659
3085 22:56:02.353720 ==
3086 22:56:02.356704 Dram Type= 6, Freq= 0, CH_0, rank 1
3087 22:56:02.360176 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3088 22:56:02.360277 ==
3089 22:56:02.363415
3090 22:56:02.363486
3091 22:56:02.363546 TX Vref Scan disable
3092 22:56:02.367252 == TX Byte 0 ==
3093 22:56:02.369978 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
3094 22:56:02.376478 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
3095 22:56:02.376603 == TX Byte 1 ==
3096 22:56:02.379826 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
3097 22:56:02.386479 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
3098 22:56:02.386588
3099 22:56:02.386678 [DATLAT]
3100 22:56:02.386766 Freq=1200, CH0 RK1
3101 22:56:02.386853
3102 22:56:02.390087 DATLAT Default: 0xd
3103 22:56:02.390181 0, 0xFFFF, sum = 0
3104 22:56:02.393361 1, 0xFFFF, sum = 0
3105 22:56:02.396993 2, 0xFFFF, sum = 0
3106 22:56:02.397071 3, 0xFFFF, sum = 0
3107 22:56:02.399749 4, 0xFFFF, sum = 0
3108 22:56:02.399819 5, 0xFFFF, sum = 0
3109 22:56:02.403246 6, 0xFFFF, sum = 0
3110 22:56:02.403351 7, 0xFFFF, sum = 0
3111 22:56:02.406554 8, 0xFFFF, sum = 0
3112 22:56:02.406656 9, 0xFFFF, sum = 0
3113 22:56:02.409901 10, 0xFFFF, sum = 0
3114 22:56:02.410001 11, 0xFFFF, sum = 0
3115 22:56:02.413125 12, 0x0, sum = 1
3116 22:56:02.413194 13, 0x0, sum = 2
3117 22:56:02.416628 14, 0x0, sum = 3
3118 22:56:02.416696 15, 0x0, sum = 4
3119 22:56:02.419704 best_step = 13
3120 22:56:02.419798
3121 22:56:02.419885 ==
3122 22:56:02.423001 Dram Type= 6, Freq= 0, CH_0, rank 1
3123 22:56:02.426371 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3124 22:56:02.426443 ==
3125 22:56:02.426503 RX Vref Scan: 0
3126 22:56:02.430038
3127 22:56:02.430104 RX Vref 0 -> 0, step: 1
3128 22:56:02.430162
3129 22:56:02.433269 RX Delay -21 -> 252, step: 4
3130 22:56:02.439735 iDelay=199, Bit 0, Center 114 (47 ~ 182) 136
3131 22:56:02.443106 iDelay=199, Bit 1, Center 120 (47 ~ 194) 148
3132 22:56:02.446302 iDelay=199, Bit 2, Center 110 (43 ~ 178) 136
3133 22:56:02.449364 iDelay=199, Bit 3, Center 114 (43 ~ 186) 144
3134 22:56:02.452897 iDelay=199, Bit 4, Center 116 (47 ~ 186) 140
3135 22:56:02.459758 iDelay=199, Bit 5, Center 110 (43 ~ 178) 136
3136 22:56:02.462813 iDelay=199, Bit 6, Center 126 (55 ~ 198) 144
3137 22:56:02.465756 iDelay=199, Bit 7, Center 124 (55 ~ 194) 140
3138 22:56:02.469352 iDelay=199, Bit 8, Center 98 (31 ~ 166) 136
3139 22:56:02.472443 iDelay=199, Bit 9, Center 94 (27 ~ 162) 136
3140 22:56:02.476225 iDelay=199, Bit 10, Center 112 (43 ~ 182) 140
3141 22:56:02.482509 iDelay=199, Bit 11, Center 102 (35 ~ 170) 136
3142 22:56:02.485894 iDelay=199, Bit 12, Center 116 (51 ~ 182) 132
3143 22:56:02.489336 iDelay=199, Bit 13, Center 114 (51 ~ 178) 128
3144 22:56:02.492619 iDelay=199, Bit 14, Center 120 (55 ~ 186) 132
3145 22:56:02.499371 iDelay=199, Bit 15, Center 116 (51 ~ 182) 132
3146 22:56:02.499480 ==
3147 22:56:02.502487 Dram Type= 6, Freq= 0, CH_0, rank 1
3148 22:56:02.505863 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3149 22:56:02.505940 ==
3150 22:56:02.506019 DQS Delay:
3151 22:56:02.508893 DQS0 = 0, DQS1 = 0
3152 22:56:02.508965 DQM Delay:
3153 22:56:02.512760 DQM0 = 116, DQM1 = 109
3154 22:56:02.512858 DQ Delay:
3155 22:56:02.516070 DQ0 =114, DQ1 =120, DQ2 =110, DQ3 =114
3156 22:56:02.518989 DQ4 =116, DQ5 =110, DQ6 =126, DQ7 =124
3157 22:56:02.522940 DQ8 =98, DQ9 =94, DQ10 =112, DQ11 =102
3158 22:56:02.525870 DQ12 =116, DQ13 =114, DQ14 =120, DQ15 =116
3159 22:56:02.525945
3160 22:56:02.526006
3161 22:56:02.535623 [DQSOSCAuto] RK1, (LSB)MR18= 0xde9, (MSB)MR19= 0x403, tDQSOscB0 = 419 ps tDQSOscB1 = 405 ps
3162 22:56:02.539470 CH0 RK1: MR19=403, MR18=DE9
3163 22:56:02.542060 CH0_RK1: MR19=0x403, MR18=0xDE9, DQSOSC=405, MR23=63, INC=39, DEC=26
3164 22:56:02.545569 [RxdqsGatingPostProcess] freq 1200
3165 22:56:02.552253 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3166 22:56:02.555223 best DQS0 dly(2T, 0.5T) = (0, 11)
3167 22:56:02.558640 best DQS1 dly(2T, 0.5T) = (0, 12)
3168 22:56:02.562600 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3169 22:56:02.566008 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3170 22:56:02.568536 best DQS0 dly(2T, 0.5T) = (0, 11)
3171 22:56:02.572109 best DQS1 dly(2T, 0.5T) = (0, 11)
3172 22:56:02.575901 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3173 22:56:02.578769 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3174 22:56:02.582143 Pre-setting of DQS Precalculation
3175 22:56:02.585812 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3176 22:56:02.585917 ==
3177 22:56:02.588522 Dram Type= 6, Freq= 0, CH_1, rank 0
3178 22:56:02.592440 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3179 22:56:02.592579 ==
3180 22:56:02.598888 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3181 22:56:02.605060 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3182 22:56:02.613114 [CA 0] Center 37 (7~67) winsize 61
3183 22:56:02.616043 [CA 1] Center 38 (8~68) winsize 61
3184 22:56:02.619467 [CA 2] Center 34 (4~64) winsize 61
3185 22:56:02.623211 [CA 3] Center 33 (3~64) winsize 62
3186 22:56:02.626242 [CA 4] Center 34 (4~64) winsize 61
3187 22:56:02.629205 [CA 5] Center 33 (3~64) winsize 62
3188 22:56:02.629303
3189 22:56:02.632881 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3190 22:56:02.632952
3191 22:56:02.636056 [CATrainingPosCal] consider 1 rank data
3192 22:56:02.639211 u2DelayCellTimex100 = 270/100 ps
3193 22:56:02.642783 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3194 22:56:02.649439 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3195 22:56:02.652487 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3196 22:56:02.656204 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3197 22:56:02.659432 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3198 22:56:02.662466 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3199 22:56:02.662563
3200 22:56:02.666103 CA PerBit enable=1, Macro0, CA PI delay=33
3201 22:56:02.666186
3202 22:56:02.669198 [CBTSetCACLKResult] CA Dly = 33
3203 22:56:02.672646 CS Dly: 6 (0~37)
3204 22:56:02.672727 ==
3205 22:56:02.675842 Dram Type= 6, Freq= 0, CH_1, rank 1
3206 22:56:02.679271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3207 22:56:02.679353 ==
3208 22:56:02.682499 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3209 22:56:02.689340 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3210 22:56:02.698734 [CA 0] Center 37 (7~67) winsize 61
3211 22:56:02.702238 [CA 1] Center 38 (8~68) winsize 61
3212 22:56:02.705708 [CA 2] Center 34 (4~65) winsize 62
3213 22:56:02.708671 [CA 3] Center 33 (3~64) winsize 62
3214 22:56:02.712285 [CA 4] Center 34 (3~65) winsize 63
3215 22:56:02.715139 [CA 5] Center 33 (3~64) winsize 62
3216 22:56:02.715221
3217 22:56:02.718321 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3218 22:56:02.718403
3219 22:56:02.721592 [CATrainingPosCal] consider 2 rank data
3220 22:56:02.725588 u2DelayCellTimex100 = 270/100 ps
3221 22:56:02.728399 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3222 22:56:02.731834 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3223 22:56:02.738407 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3224 22:56:02.741930 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3225 22:56:02.744996 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3226 22:56:02.748407 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3227 22:56:02.748490
3228 22:56:02.751548 CA PerBit enable=1, Macro0, CA PI delay=33
3229 22:56:02.751630
3230 22:56:02.755234 [CBTSetCACLKResult] CA Dly = 33
3231 22:56:02.755316 CS Dly: 7 (0~40)
3232 22:56:02.755382
3233 22:56:02.758268 ----->DramcWriteLeveling(PI) begin...
3234 22:56:02.761912 ==
3235 22:56:02.764984 Dram Type= 6, Freq= 0, CH_1, rank 0
3236 22:56:02.768243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3237 22:56:02.768326 ==
3238 22:56:02.771635 Write leveling (Byte 0): 26 => 26
3239 22:56:02.774874 Write leveling (Byte 1): 26 => 26
3240 22:56:02.778348 DramcWriteLeveling(PI) end<-----
3241 22:56:02.778426
3242 22:56:02.778493 ==
3243 22:56:02.781439 Dram Type= 6, Freq= 0, CH_1, rank 0
3244 22:56:02.784570 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3245 22:56:02.784646 ==
3246 22:56:02.787938 [Gating] SW mode calibration
3247 22:56:02.794621 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3248 22:56:02.801161 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3249 22:56:02.804846 0 15 0 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
3250 22:56:02.808049 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3251 22:56:02.814572 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3252 22:56:02.818064 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3253 22:56:02.821230 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3254 22:56:02.827962 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3255 22:56:02.831115 0 15 24 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 0)
3256 22:56:02.834230 0 15 28 | B1->B0 | 2626 2323 | 0 0 | (1 0) (1 0)
3257 22:56:02.841089 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3258 22:56:02.844269 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3259 22:56:02.847902 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3260 22:56:02.851406 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3261 22:56:02.857758 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3262 22:56:02.860964 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3263 22:56:02.864721 1 0 24 | B1->B0 | 2525 3d3d | 0 0 | (0 0) (0 0)
3264 22:56:02.871255 1 0 28 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
3265 22:56:02.874318 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3266 22:56:02.877443 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3267 22:56:02.884181 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3268 22:56:02.887500 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3269 22:56:02.890969 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3270 22:56:02.897262 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3271 22:56:02.900458 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3272 22:56:02.903922 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3273 22:56:02.910941 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3274 22:56:02.913943 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3275 22:56:02.917218 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3276 22:56:02.924209 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3277 22:56:02.927719 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3278 22:56:02.930791 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3279 22:56:02.937626 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3280 22:56:02.940386 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3281 22:56:02.943819 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3282 22:56:02.950653 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3283 22:56:02.953903 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3284 22:56:02.957249 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3285 22:56:02.963705 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3286 22:56:02.967328 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3287 22:56:02.970917 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3288 22:56:02.977346 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3289 22:56:02.980975 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3290 22:56:02.983958 Total UI for P1: 0, mck2ui 16
3291 22:56:02.987423 best dqsien dly found for B0: ( 1, 3, 26)
3292 22:56:02.990451 Total UI for P1: 0, mck2ui 16
3293 22:56:02.993591 best dqsien dly found for B1: ( 1, 3, 28)
3294 22:56:02.997466 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3295 22:56:03.000566 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3296 22:56:03.000648
3297 22:56:03.003641 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3298 22:56:03.007433 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3299 22:56:03.010826 [Gating] SW calibration Done
3300 22:56:03.010908 ==
3301 22:56:03.013607 Dram Type= 6, Freq= 0, CH_1, rank 0
3302 22:56:03.017576 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3303 22:56:03.017658 ==
3304 22:56:03.020678 RX Vref Scan: 0
3305 22:56:03.020760
3306 22:56:03.023678 RX Vref 0 -> 0, step: 1
3307 22:56:03.023775
3308 22:56:03.023840 RX Delay -40 -> 252, step: 8
3309 22:56:03.030579 iDelay=208, Bit 0, Center 123 (48 ~ 199) 152
3310 22:56:03.033730 iDelay=208, Bit 1, Center 115 (48 ~ 183) 136
3311 22:56:03.037000 iDelay=208, Bit 2, Center 111 (40 ~ 183) 144
3312 22:56:03.040758 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3313 22:56:03.044193 iDelay=208, Bit 4, Center 115 (48 ~ 183) 136
3314 22:56:03.050544 iDelay=208, Bit 5, Center 131 (56 ~ 207) 152
3315 22:56:03.053789 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3316 22:56:03.057142 iDelay=208, Bit 7, Center 115 (48 ~ 183) 136
3317 22:56:03.060945 iDelay=208, Bit 8, Center 95 (24 ~ 167) 144
3318 22:56:03.064184 iDelay=208, Bit 9, Center 99 (24 ~ 175) 152
3319 22:56:03.067147 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3320 22:56:03.074266 iDelay=208, Bit 11, Center 99 (32 ~ 167) 136
3321 22:56:03.077516 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3322 22:56:03.080425 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3323 22:56:03.084246 iDelay=208, Bit 14, Center 119 (48 ~ 191) 144
3324 22:56:03.090398 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3325 22:56:03.090480 ==
3326 22:56:03.093932 Dram Type= 6, Freq= 0, CH_1, rank 0
3327 22:56:03.097374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3328 22:56:03.097473 ==
3329 22:56:03.097539 DQS Delay:
3330 22:56:03.100853 DQS0 = 0, DQS1 = 0
3331 22:56:03.100935 DQM Delay:
3332 22:56:03.103764 DQM0 = 118, DQM1 = 110
3333 22:56:03.103846 DQ Delay:
3334 22:56:03.107486 DQ0 =123, DQ1 =115, DQ2 =111, DQ3 =115
3335 22:56:03.110738 DQ4 =115, DQ5 =131, DQ6 =123, DQ7 =115
3336 22:56:03.113891 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =99
3337 22:56:03.117066 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3338 22:56:03.117148
3339 22:56:03.117213
3340 22:56:03.117272 ==
3341 22:56:03.120287 Dram Type= 6, Freq= 0, CH_1, rank 0
3342 22:56:03.127103 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3343 22:56:03.127186 ==
3344 22:56:03.127282
3345 22:56:03.127362
3346 22:56:03.127421 TX Vref Scan disable
3347 22:56:03.130471 == TX Byte 0 ==
3348 22:56:03.134251 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3349 22:56:03.140235 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3350 22:56:03.140318 == TX Byte 1 ==
3351 22:56:03.143627 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3352 22:56:03.150567 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3353 22:56:03.150649 ==
3354 22:56:03.153817 Dram Type= 6, Freq= 0, CH_1, rank 0
3355 22:56:03.157069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3356 22:56:03.157152 ==
3357 22:56:03.168157 TX Vref=22, minBit 9, minWin=25, winSum=419
3358 22:56:03.171451 TX Vref=24, minBit 10, minWin=25, winSum=424
3359 22:56:03.174717 TX Vref=26, minBit 11, minWin=25, winSum=432
3360 22:56:03.178083 TX Vref=28, minBit 11, minWin=26, winSum=436
3361 22:56:03.181579 TX Vref=30, minBit 13, minWin=26, winSum=435
3362 22:56:03.188019 TX Vref=32, minBit 4, minWin=26, winSum=430
3363 22:56:03.191967 [TxChooseVref] Worse bit 11, Min win 26, Win sum 436, Final Vref 28
3364 22:56:03.192048
3365 22:56:03.195052 Final TX Range 1 Vref 28
3366 22:56:03.195159
3367 22:56:03.195250 ==
3368 22:56:03.198593 Dram Type= 6, Freq= 0, CH_1, rank 0
3369 22:56:03.201684 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3370 22:56:03.205030 ==
3371 22:56:03.205137
3372 22:56:03.205214
3373 22:56:03.205274 TX Vref Scan disable
3374 22:56:03.208722 == TX Byte 0 ==
3375 22:56:03.211654 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3376 22:56:03.218250 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3377 22:56:03.218353 == TX Byte 1 ==
3378 22:56:03.221834 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3379 22:56:03.228210 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3380 22:56:03.228287
3381 22:56:03.228348 [DATLAT]
3382 22:56:03.228406 Freq=1200, CH1 RK0
3383 22:56:03.228464
3384 22:56:03.231551 DATLAT Default: 0xd
3385 22:56:03.231648 0, 0xFFFF, sum = 0
3386 22:56:03.234690 1, 0xFFFF, sum = 0
3387 22:56:03.234772 2, 0xFFFF, sum = 0
3388 22:56:03.238012 3, 0xFFFF, sum = 0
3389 22:56:03.241249 4, 0xFFFF, sum = 0
3390 22:56:03.241331 5, 0xFFFF, sum = 0
3391 22:56:03.244764 6, 0xFFFF, sum = 0
3392 22:56:03.244846 7, 0xFFFF, sum = 0
3393 22:56:03.248202 8, 0xFFFF, sum = 0
3394 22:56:03.248288 9, 0xFFFF, sum = 0
3395 22:56:03.251406 10, 0xFFFF, sum = 0
3396 22:56:03.251492 11, 0xFFFF, sum = 0
3397 22:56:03.254886 12, 0x0, sum = 1
3398 22:56:03.254968 13, 0x0, sum = 2
3399 22:56:03.258048 14, 0x0, sum = 3
3400 22:56:03.258157 15, 0x0, sum = 4
3401 22:56:03.261302 best_step = 13
3402 22:56:03.261400
3403 22:56:03.261466 ==
3404 22:56:03.265237 Dram Type= 6, Freq= 0, CH_1, rank 0
3405 22:56:03.268439 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3406 22:56:03.268549 ==
3407 22:56:03.268629 RX Vref Scan: 1
3408 22:56:03.268690
3409 22:56:03.271708 Set Vref Range= 32 -> 127
3410 22:56:03.271787
3411 22:56:03.274956 RX Vref 32 -> 127, step: 1
3412 22:56:03.275036
3413 22:56:03.278195 RX Delay -21 -> 252, step: 4
3414 22:56:03.278276
3415 22:56:03.281219 Set Vref, RX VrefLevel [Byte0]: 32
3416 22:56:03.284862 [Byte1]: 32
3417 22:56:03.284955
3418 22:56:03.288130 Set Vref, RX VrefLevel [Byte0]: 33
3419 22:56:03.291433 [Byte1]: 33
3420 22:56:03.294728
3421 22:56:03.294821 Set Vref, RX VrefLevel [Byte0]: 34
3422 22:56:03.298691 [Byte1]: 34
3423 22:56:03.302706
3424 22:56:03.302786 Set Vref, RX VrefLevel [Byte0]: 35
3425 22:56:03.305902 [Byte1]: 35
3426 22:56:03.310680
3427 22:56:03.310760 Set Vref, RX VrefLevel [Byte0]: 36
3428 22:56:03.313903 [Byte1]: 36
3429 22:56:03.318597
3430 22:56:03.318678 Set Vref, RX VrefLevel [Byte0]: 37
3431 22:56:03.321806 [Byte1]: 37
3432 22:56:03.326714
3433 22:56:03.326794 Set Vref, RX VrefLevel [Byte0]: 38
3434 22:56:03.329709 [Byte1]: 38
3435 22:56:03.334806
3436 22:56:03.334889 Set Vref, RX VrefLevel [Byte0]: 39
3437 22:56:03.338074 [Byte1]: 39
3438 22:56:03.342339
3439 22:56:03.342423 Set Vref, RX VrefLevel [Byte0]: 40
3440 22:56:03.345455 [Byte1]: 40
3441 22:56:03.350339
3442 22:56:03.350429 Set Vref, RX VrefLevel [Byte0]: 41
3443 22:56:03.353855 [Byte1]: 41
3444 22:56:03.358153
3445 22:56:03.358242 Set Vref, RX VrefLevel [Byte0]: 42
3446 22:56:03.361306 [Byte1]: 42
3447 22:56:03.366170
3448 22:56:03.366252 Set Vref, RX VrefLevel [Byte0]: 43
3449 22:56:03.372846 [Byte1]: 43
3450 22:56:03.372933
3451 22:56:03.376188 Set Vref, RX VrefLevel [Byte0]: 44
3452 22:56:03.378960 [Byte1]: 44
3453 22:56:03.379043
3454 22:56:03.382682 Set Vref, RX VrefLevel [Byte0]: 45
3455 22:56:03.385573 [Byte1]: 45
3456 22:56:03.390250
3457 22:56:03.390361 Set Vref, RX VrefLevel [Byte0]: 46
3458 22:56:03.393365 [Byte1]: 46
3459 22:56:03.397914
3460 22:56:03.398009 Set Vref, RX VrefLevel [Byte0]: 47
3461 22:56:03.400860 [Byte1]: 47
3462 22:56:03.405954
3463 22:56:03.406027 Set Vref, RX VrefLevel [Byte0]: 48
3464 22:56:03.409252 [Byte1]: 48
3465 22:56:03.413886
3466 22:56:03.413960 Set Vref, RX VrefLevel [Byte0]: 49
3467 22:56:03.417159 [Byte1]: 49
3468 22:56:03.421579
3469 22:56:03.421680 Set Vref, RX VrefLevel [Byte0]: 50
3470 22:56:03.424737 [Byte1]: 50
3471 22:56:03.429536
3472 22:56:03.429641 Set Vref, RX VrefLevel [Byte0]: 51
3473 22:56:03.432816 [Byte1]: 51
3474 22:56:03.437476
3475 22:56:03.437552 Set Vref, RX VrefLevel [Byte0]: 52
3476 22:56:03.440974 [Byte1]: 52
3477 22:56:03.445990
3478 22:56:03.446063 Set Vref, RX VrefLevel [Byte0]: 53
3479 22:56:03.449182 [Byte1]: 53
3480 22:56:03.453133
3481 22:56:03.453204 Set Vref, RX VrefLevel [Byte0]: 54
3482 22:56:03.456773 [Byte1]: 54
3483 22:56:03.461491
3484 22:56:03.461586 Set Vref, RX VrefLevel [Byte0]: 55
3485 22:56:03.464770 [Byte1]: 55
3486 22:56:03.468997
3487 22:56:03.469070 Set Vref, RX VrefLevel [Byte0]: 56
3488 22:56:03.472702 [Byte1]: 56
3489 22:56:03.477055
3490 22:56:03.477137 Set Vref, RX VrefLevel [Byte0]: 57
3491 22:56:03.480234 [Byte1]: 57
3492 22:56:03.484837
3493 22:56:03.484951 Set Vref, RX VrefLevel [Byte0]: 58
3494 22:56:03.488104 [Byte1]: 58
3495 22:56:03.492788
3496 22:56:03.492890 Set Vref, RX VrefLevel [Byte0]: 59
3497 22:56:03.496044 [Byte1]: 59
3498 22:56:03.500979
3499 22:56:03.501064 Set Vref, RX VrefLevel [Byte0]: 60
3500 22:56:03.504293 [Byte1]: 60
3501 22:56:03.508494
3502 22:56:03.508626 Set Vref, RX VrefLevel [Byte0]: 61
3503 22:56:03.511715 [Byte1]: 61
3504 22:56:03.516436
3505 22:56:03.516538 Set Vref, RX VrefLevel [Byte0]: 62
3506 22:56:03.520044 [Byte1]: 62
3507 22:56:03.524644
3508 22:56:03.524755 Set Vref, RX VrefLevel [Byte0]: 63
3509 22:56:03.527684 [Byte1]: 63
3510 22:56:03.532195
3511 22:56:03.532306 Set Vref, RX VrefLevel [Byte0]: 64
3512 22:56:03.535754 [Byte1]: 64
3513 22:56:03.540644
3514 22:56:03.540720 Set Vref, RX VrefLevel [Byte0]: 65
3515 22:56:03.543657 [Byte1]: 65
3516 22:56:03.548419
3517 22:56:03.548501 Set Vref, RX VrefLevel [Byte0]: 66
3518 22:56:03.551611 [Byte1]: 66
3519 22:56:03.555965
3520 22:56:03.556046 Set Vref, RX VrefLevel [Byte0]: 67
3521 22:56:03.559228 [Byte1]: 67
3522 22:56:03.563963
3523 22:56:03.564046 Set Vref, RX VrefLevel [Byte0]: 68
3524 22:56:03.570809 [Byte1]: 68
3525 22:56:03.570892
3526 22:56:03.574520 Final RX Vref Byte 0 = 52 to rank0
3527 22:56:03.577271 Final RX Vref Byte 1 = 53 to rank0
3528 22:56:03.580409 Final RX Vref Byte 0 = 52 to rank1
3529 22:56:03.583561 Final RX Vref Byte 1 = 53 to rank1==
3530 22:56:03.586939 Dram Type= 6, Freq= 0, CH_1, rank 0
3531 22:56:03.590774 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3532 22:56:03.590858 ==
3533 22:56:03.590924 DQS Delay:
3534 22:56:03.593772 DQS0 = 0, DQS1 = 0
3535 22:56:03.593854 DQM Delay:
3536 22:56:03.597211 DQM0 = 116, DQM1 = 110
3537 22:56:03.597294 DQ Delay:
3538 22:56:03.600687 DQ0 =120, DQ1 =110, DQ2 =110, DQ3 =110
3539 22:56:03.603744 DQ4 =114, DQ5 =128, DQ6 =124, DQ7 =112
3540 22:56:03.607679 DQ8 =98, DQ9 =104, DQ10 =112, DQ11 =100
3541 22:56:03.610268 DQ12 =118, DQ13 =118, DQ14 =118, DQ15 =118
3542 22:56:03.610350
3543 22:56:03.613900
3544 22:56:03.620352 [DQSOSCAuto] RK0, (LSB)MR18= 0x2f5, (MSB)MR19= 0x403, tDQSOscB0 = 414 ps tDQSOscB1 = 409 ps
3545 22:56:03.623732 CH1 RK0: MR19=403, MR18=2F5
3546 22:56:03.630107 CH1_RK0: MR19=0x403, MR18=0x2F5, DQSOSC=409, MR23=63, INC=39, DEC=26
3547 22:56:03.630190
3548 22:56:03.633544 ----->DramcWriteLeveling(PI) begin...
3549 22:56:03.633628 ==
3550 22:56:03.636716 Dram Type= 6, Freq= 0, CH_1, rank 1
3551 22:56:03.640372 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3552 22:56:03.640481 ==
3553 22:56:03.643586 Write leveling (Byte 0): 24 => 24
3554 22:56:03.646808 Write leveling (Byte 1): 28 => 28
3555 22:56:03.649810 DramcWriteLeveling(PI) end<-----
3556 22:56:03.649892
3557 22:56:03.649957 ==
3558 22:56:03.653339 Dram Type= 6, Freq= 0, CH_1, rank 1
3559 22:56:03.656656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3560 22:56:03.656739 ==
3561 22:56:03.660066 [Gating] SW mode calibration
3562 22:56:03.666698 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3563 22:56:03.672857 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3564 22:56:03.676713 0 15 0 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
3565 22:56:03.679771 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3566 22:56:03.686273 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3567 22:56:03.689496 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3568 22:56:03.692846 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3569 22:56:03.699703 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3570 22:56:03.702817 0 15 24 | B1->B0 | 2d2d 3232 | 0 1 | (0 0) (1 0)
3571 22:56:03.706159 0 15 28 | B1->B0 | 2323 2828 | 0 0 | (1 0) (0 0)
3572 22:56:03.712867 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3573 22:56:03.716367 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3574 22:56:03.719621 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3575 22:56:03.725953 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3576 22:56:03.729339 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3577 22:56:03.732447 1 0 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3578 22:56:03.739169 1 0 24 | B1->B0 | 3b3b 2525 | 1 0 | (0 0) (0 0)
3579 22:56:03.742437 1 0 28 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
3580 22:56:03.745877 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3581 22:56:03.752275 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3582 22:56:03.755872 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3583 22:56:03.759876 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3584 22:56:03.765545 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3585 22:56:03.769148 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3586 22:56:03.772562 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3587 22:56:03.778705 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3588 22:56:03.781988 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3589 22:56:03.785600 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3590 22:56:03.792008 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3591 22:56:03.795425 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3592 22:56:03.798725 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3593 22:56:03.805474 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3594 22:56:03.808512 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3595 22:56:03.811632 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3596 22:56:03.818988 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3597 22:56:03.822033 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3598 22:56:03.825268 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3599 22:56:03.831570 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3600 22:56:03.835395 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3601 22:56:03.838173 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3602 22:56:03.845231 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3603 22:56:03.848186 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3604 22:56:03.851526 Total UI for P1: 0, mck2ui 16
3605 22:56:03.855120 best dqsien dly found for B1: ( 1, 3, 24)
3606 22:56:03.857916 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3607 22:56:03.861914 Total UI for P1: 0, mck2ui 16
3608 22:56:03.864918 best dqsien dly found for B0: ( 1, 3, 26)
3609 22:56:03.868186 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3610 22:56:03.871593 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3611 22:56:03.871693
3612 22:56:03.874986 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3613 22:56:03.881331 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3614 22:56:03.881415 [Gating] SW calibration Done
3615 22:56:03.881511 ==
3616 22:56:03.885155 Dram Type= 6, Freq= 0, CH_1, rank 1
3617 22:56:03.891500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3618 22:56:03.891584 ==
3619 22:56:03.891663 RX Vref Scan: 0
3620 22:56:03.891740
3621 22:56:03.894629 RX Vref 0 -> 0, step: 1
3622 22:56:03.894712
3623 22:56:03.898253 RX Delay -40 -> 252, step: 8
3624 22:56:03.901130 iDelay=208, Bit 0, Center 119 (48 ~ 191) 144
3625 22:56:03.905055 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3626 22:56:03.908069 iDelay=208, Bit 2, Center 103 (32 ~ 175) 144
3627 22:56:03.915082 iDelay=208, Bit 3, Center 111 (40 ~ 183) 144
3628 22:56:03.918090 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3629 22:56:03.921221 iDelay=208, Bit 5, Center 123 (48 ~ 199) 152
3630 22:56:03.925053 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
3631 22:56:03.927881 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3632 22:56:03.934475 iDelay=208, Bit 8, Center 95 (24 ~ 167) 144
3633 22:56:03.938056 iDelay=208, Bit 9, Center 99 (24 ~ 175) 152
3634 22:56:03.941195 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3635 22:56:03.944352 iDelay=208, Bit 11, Center 103 (32 ~ 175) 144
3636 22:56:03.948119 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3637 22:56:03.954353 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3638 22:56:03.957925 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3639 22:56:03.960727 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3640 22:56:03.960798 ==
3641 22:56:03.964538 Dram Type= 6, Freq= 0, CH_1, rank 1
3642 22:56:03.967548 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3643 22:56:03.970732 ==
3644 22:56:03.970805 DQS Delay:
3645 22:56:03.970865 DQS0 = 0, DQS1 = 0
3646 22:56:03.974435 DQM Delay:
3647 22:56:03.974530 DQM0 = 116, DQM1 = 110
3648 22:56:03.977638 DQ Delay:
3649 22:56:03.980683 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =111
3650 22:56:03.984071 DQ4 =115, DQ5 =123, DQ6 =131, DQ7 =115
3651 22:56:03.987424 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =103
3652 22:56:03.990558 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3653 22:56:03.990654
3654 22:56:03.990742
3655 22:56:03.990829 ==
3656 22:56:03.993785 Dram Type= 6, Freq= 0, CH_1, rank 1
3657 22:56:03.997238 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3658 22:56:03.997308 ==
3659 22:56:03.997369
3660 22:56:03.997426
3661 22:56:04.000319 TX Vref Scan disable
3662 22:56:04.003696 == TX Byte 0 ==
3663 22:56:04.007406 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3664 22:56:04.010457 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3665 22:56:04.014022 == TX Byte 1 ==
3666 22:56:04.017253 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3667 22:56:04.020387 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3668 22:56:04.020474 ==
3669 22:56:04.023999 Dram Type= 6, Freq= 0, CH_1, rank 1
3670 22:56:04.030599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3671 22:56:04.030683 ==
3672 22:56:04.040895 TX Vref=22, minBit 8, minWin=25, winSum=422
3673 22:56:04.044282 TX Vref=24, minBit 8, minWin=25, winSum=431
3674 22:56:04.047220 TX Vref=26, minBit 9, minWin=26, winSum=432
3675 22:56:04.050629 TX Vref=28, minBit 9, minWin=26, winSum=435
3676 22:56:04.054163 TX Vref=30, minBit 8, minWin=26, winSum=435
3677 22:56:04.061036 TX Vref=32, minBit 8, minWin=26, winSum=434
3678 22:56:04.064062 [TxChooseVref] Worse bit 9, Min win 26, Win sum 435, Final Vref 28
3679 22:56:04.064145
3680 22:56:04.067246 Final TX Range 1 Vref 28
3681 22:56:04.067329
3682 22:56:04.067394 ==
3683 22:56:04.070618 Dram Type= 6, Freq= 0, CH_1, rank 1
3684 22:56:04.073917 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3685 22:56:04.077042 ==
3686 22:56:04.077124
3687 22:56:04.077238
3688 22:56:04.077308 TX Vref Scan disable
3689 22:56:04.080831 == TX Byte 0 ==
3690 22:56:04.084188 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3691 22:56:04.091040 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3692 22:56:04.091123 == TX Byte 1 ==
3693 22:56:04.094177 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3694 22:56:04.100435 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3695 22:56:04.100528
3696 22:56:04.100629 [DATLAT]
3697 22:56:04.100754 Freq=1200, CH1 RK1
3698 22:56:04.100845
3699 22:56:04.103988 DATLAT Default: 0xd
3700 22:56:04.104070 0, 0xFFFF, sum = 0
3701 22:56:04.107510 1, 0xFFFF, sum = 0
3702 22:56:04.110488 2, 0xFFFF, sum = 0
3703 22:56:04.110570 3, 0xFFFF, sum = 0
3704 22:56:04.113602 4, 0xFFFF, sum = 0
3705 22:56:04.113688 5, 0xFFFF, sum = 0
3706 22:56:04.117602 6, 0xFFFF, sum = 0
3707 22:56:04.117700 7, 0xFFFF, sum = 0
3708 22:56:04.120100 8, 0xFFFF, sum = 0
3709 22:56:04.120184 9, 0xFFFF, sum = 0
3710 22:56:04.123489 10, 0xFFFF, sum = 0
3711 22:56:04.123588 11, 0xFFFF, sum = 0
3712 22:56:04.127012 12, 0x0, sum = 1
3713 22:56:04.127113 13, 0x0, sum = 2
3714 22:56:04.129958 14, 0x0, sum = 3
3715 22:56:04.130086 15, 0x0, sum = 4
3716 22:56:04.133448 best_step = 13
3717 22:56:04.133561
3718 22:56:04.133642 ==
3719 22:56:04.136667 Dram Type= 6, Freq= 0, CH_1, rank 1
3720 22:56:04.140020 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3721 22:56:04.140103 ==
3722 22:56:04.143174 RX Vref Scan: 0
3723 22:56:04.143258
3724 22:56:04.143324 RX Vref 0 -> 0, step: 1
3725 22:56:04.143386
3726 22:56:04.146952 RX Delay -21 -> 252, step: 4
3727 22:56:04.153386 iDelay=199, Bit 0, Center 120 (51 ~ 190) 140
3728 22:56:04.156647 iDelay=199, Bit 1, Center 110 (43 ~ 178) 136
3729 22:56:04.159489 iDelay=199, Bit 2, Center 108 (43 ~ 174) 132
3730 22:56:04.162973 iDelay=199, Bit 3, Center 112 (47 ~ 178) 132
3731 22:56:04.169476 iDelay=199, Bit 4, Center 116 (47 ~ 186) 140
3732 22:56:04.172444 iDelay=199, Bit 5, Center 126 (59 ~ 194) 136
3733 22:56:04.176142 iDelay=199, Bit 6, Center 128 (59 ~ 198) 140
3734 22:56:04.179289 iDelay=199, Bit 7, Center 116 (51 ~ 182) 132
3735 22:56:04.182727 iDelay=199, Bit 8, Center 98 (31 ~ 166) 136
3736 22:56:04.186380 iDelay=199, Bit 9, Center 100 (35 ~ 166) 132
3737 22:56:04.192362 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
3738 22:56:04.195717 iDelay=199, Bit 11, Center 100 (35 ~ 166) 132
3739 22:56:04.199060 iDelay=199, Bit 12, Center 118 (51 ~ 186) 136
3740 22:56:04.202641 iDelay=199, Bit 13, Center 118 (51 ~ 186) 136
3741 22:56:04.208660 iDelay=199, Bit 14, Center 118 (51 ~ 186) 136
3742 22:56:04.212363 iDelay=199, Bit 15, Center 120 (51 ~ 190) 140
3743 22:56:04.212460 ==
3744 22:56:04.215842 Dram Type= 6, Freq= 0, CH_1, rank 1
3745 22:56:04.218887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3746 22:56:04.218971 ==
3747 22:56:04.222529 DQS Delay:
3748 22:56:04.222630 DQS0 = 0, DQS1 = 0
3749 22:56:04.222748 DQM Delay:
3750 22:56:04.225699 DQM0 = 117, DQM1 = 110
3751 22:56:04.225800 DQ Delay:
3752 22:56:04.228423 DQ0 =120, DQ1 =110, DQ2 =108, DQ3 =112
3753 22:56:04.231820 DQ4 =116, DQ5 =126, DQ6 =128, DQ7 =116
3754 22:56:04.238519 DQ8 =98, DQ9 =100, DQ10 =110, DQ11 =100
3755 22:56:04.242270 DQ12 =118, DQ13 =118, DQ14 =118, DQ15 =120
3756 22:56:04.242390
3757 22:56:04.242455
3758 22:56:04.248271 [DQSOSCAuto] RK1, (LSB)MR18= 0xf8f2, (MSB)MR19= 0x303, tDQSOscB0 = 415 ps tDQSOscB1 = 413 ps
3759 22:56:04.251716 CH1 RK1: MR19=303, MR18=F8F2
3760 22:56:04.258280 CH1_RK1: MR19=0x303, MR18=0xF8F2, DQSOSC=413, MR23=63, INC=38, DEC=25
3761 22:56:04.261789 [RxdqsGatingPostProcess] freq 1200
3762 22:56:04.268183 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3763 22:56:04.268355 best DQS0 dly(2T, 0.5T) = (0, 11)
3764 22:56:04.271694 best DQS1 dly(2T, 0.5T) = (0, 11)
3765 22:56:04.274901 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3766 22:56:04.278137 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3767 22:56:04.281452 best DQS0 dly(2T, 0.5T) = (0, 11)
3768 22:56:04.284721 best DQS1 dly(2T, 0.5T) = (0, 11)
3769 22:56:04.288012 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3770 22:56:04.291070 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3771 22:56:04.294374 Pre-setting of DQS Precalculation
3772 22:56:04.301624 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3773 22:56:04.307789 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3774 22:56:04.314657 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3775 22:56:04.314741
3776 22:56:04.314806
3777 22:56:04.317895 [Calibration Summary] 2400 Mbps
3778 22:56:04.317977 CH 0, Rank 0
3779 22:56:04.321345 SW Impedance : PASS
3780 22:56:04.324461 DUTY Scan : NO K
3781 22:56:04.324625 ZQ Calibration : PASS
3782 22:56:04.327535 Jitter Meter : NO K
3783 22:56:04.330937 CBT Training : PASS
3784 22:56:04.331018 Write leveling : PASS
3785 22:56:04.334339 RX DQS gating : PASS
3786 22:56:04.337846 RX DQ/DQS(RDDQC) : PASS
3787 22:56:04.337929 TX DQ/DQS : PASS
3788 22:56:04.340625 RX DATLAT : PASS
3789 22:56:04.340705 RX DQ/DQS(Engine): PASS
3790 22:56:04.344408 TX OE : NO K
3791 22:56:04.344490 All Pass.
3792 22:56:04.344560
3793 22:56:04.347581 CH 0, Rank 1
3794 22:56:04.347662 SW Impedance : PASS
3795 22:56:04.350798 DUTY Scan : NO K
3796 22:56:04.353990 ZQ Calibration : PASS
3797 22:56:04.354072 Jitter Meter : NO K
3798 22:56:04.357169 CBT Training : PASS
3799 22:56:04.360935 Write leveling : PASS
3800 22:56:04.361017 RX DQS gating : PASS
3801 22:56:04.363939 RX DQ/DQS(RDDQC) : PASS
3802 22:56:04.367568 TX DQ/DQS : PASS
3803 22:56:04.367650 RX DATLAT : PASS
3804 22:56:04.370770 RX DQ/DQS(Engine): PASS
3805 22:56:04.374046 TX OE : NO K
3806 22:56:04.374128 All Pass.
3807 22:56:04.374192
3808 22:56:04.374253 CH 1, Rank 0
3809 22:56:04.377206 SW Impedance : PASS
3810 22:56:04.380687 DUTY Scan : NO K
3811 22:56:04.380770 ZQ Calibration : PASS
3812 22:56:04.383768 Jitter Meter : NO K
3813 22:56:04.387189 CBT Training : PASS
3814 22:56:04.387270 Write leveling : PASS
3815 22:56:04.390104 RX DQS gating : PASS
3816 22:56:04.393642 RX DQ/DQS(RDDQC) : PASS
3817 22:56:04.393723 TX DQ/DQS : PASS
3818 22:56:04.396712 RX DATLAT : PASS
3819 22:56:04.399973 RX DQ/DQS(Engine): PASS
3820 22:56:04.400080 TX OE : NO K
3821 22:56:04.403420 All Pass.
3822 22:56:04.403501
3823 22:56:04.403565 CH 1, Rank 1
3824 22:56:04.406452 SW Impedance : PASS
3825 22:56:04.406533 DUTY Scan : NO K
3826 22:56:04.409982 ZQ Calibration : PASS
3827 22:56:04.413201 Jitter Meter : NO K
3828 22:56:04.413282 CBT Training : PASS
3829 22:56:04.416882 Write leveling : PASS
3830 22:56:04.420313 RX DQS gating : PASS
3831 22:56:04.420395 RX DQ/DQS(RDDQC) : PASS
3832 22:56:04.423509 TX DQ/DQS : PASS
3833 22:56:04.426373 RX DATLAT : PASS
3834 22:56:04.426454 RX DQ/DQS(Engine): PASS
3835 22:56:04.430011 TX OE : NO K
3836 22:56:04.430107 All Pass.
3837 22:56:04.430187
3838 22:56:04.433270 DramC Write-DBI off
3839 22:56:04.436283 PER_BANK_REFRESH: Hybrid Mode
3840 22:56:04.436365 TX_TRACKING: ON
3841 22:56:04.445963 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3842 22:56:04.450060 [FAST_K] Save calibration result to emmc
3843 22:56:04.452785 dramc_set_vcore_voltage set vcore to 650000
3844 22:56:04.455932 Read voltage for 600, 5
3845 22:56:04.456013 Vio18 = 0
3846 22:56:04.456077 Vcore = 650000
3847 22:56:04.459704 Vdram = 0
3848 22:56:04.459786 Vddq = 0
3849 22:56:04.459849 Vmddr = 0
3850 22:56:04.466163 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3851 22:56:04.469177 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3852 22:56:04.472832 MEM_TYPE=3, freq_sel=19
3853 22:56:04.475729 sv_algorithm_assistance_LP4_1600
3854 22:56:04.479363 ============ PULL DRAM RESETB DOWN ============
3855 22:56:04.482748 ========== PULL DRAM RESETB DOWN end =========
3856 22:56:04.489076 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3857 22:56:04.492508 ===================================
3858 22:56:04.492627 LPDDR4 DRAM CONFIGURATION
3859 22:56:04.495878 ===================================
3860 22:56:04.499001 EX_ROW_EN[0] = 0x0
3861 22:56:04.502322 EX_ROW_EN[1] = 0x0
3862 22:56:04.502403 LP4Y_EN = 0x0
3863 22:56:04.505532 WORK_FSP = 0x0
3864 22:56:04.505613 WL = 0x2
3865 22:56:04.508770 RL = 0x2
3866 22:56:04.508851 BL = 0x2
3867 22:56:04.512658 RPST = 0x0
3868 22:56:04.512740 RD_PRE = 0x0
3869 22:56:04.515464 WR_PRE = 0x1
3870 22:56:04.515545 WR_PST = 0x0
3871 22:56:04.518700 DBI_WR = 0x0
3872 22:56:04.518781 DBI_RD = 0x0
3873 22:56:04.522207 OTF = 0x1
3874 22:56:04.525294 ===================================
3875 22:56:04.529070 ===================================
3876 22:56:04.529152 ANA top config
3877 22:56:04.531829 ===================================
3878 22:56:04.535763 DLL_ASYNC_EN = 0
3879 22:56:04.539015 ALL_SLAVE_EN = 1
3880 22:56:04.542175 NEW_RANK_MODE = 1
3881 22:56:04.542258 DLL_IDLE_MODE = 1
3882 22:56:04.545624 LP45_APHY_COMB_EN = 1
3883 22:56:04.549016 TX_ODT_DIS = 1
3884 22:56:04.552119 NEW_8X_MODE = 1
3885 22:56:04.555086 ===================================
3886 22:56:04.558932 ===================================
3887 22:56:04.561637 data_rate = 1200
3888 22:56:04.565179 CKR = 1
3889 22:56:04.565261 DQ_P2S_RATIO = 8
3890 22:56:04.568496 ===================================
3891 22:56:04.571598 CA_P2S_RATIO = 8
3892 22:56:04.574809 DQ_CA_OPEN = 0
3893 22:56:04.578257 DQ_SEMI_OPEN = 0
3894 22:56:04.581471 CA_SEMI_OPEN = 0
3895 22:56:04.584666 CA_FULL_RATE = 0
3896 22:56:04.584750 DQ_CKDIV4_EN = 1
3897 22:56:04.588099 CA_CKDIV4_EN = 1
3898 22:56:04.591376 CA_PREDIV_EN = 0
3899 22:56:04.594619 PH8_DLY = 0
3900 22:56:04.598408 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3901 22:56:04.601675 DQ_AAMCK_DIV = 4
3902 22:56:04.601757 CA_AAMCK_DIV = 4
3903 22:56:04.604753 CA_ADMCK_DIV = 4
3904 22:56:04.607960 DQ_TRACK_CA_EN = 0
3905 22:56:04.611248 CA_PICK = 600
3906 22:56:04.614209 CA_MCKIO = 600
3907 22:56:04.617767 MCKIO_SEMI = 0
3908 22:56:04.620761 PLL_FREQ = 2288
3909 22:56:04.620843 DQ_UI_PI_RATIO = 32
3910 22:56:04.624334 CA_UI_PI_RATIO = 0
3911 22:56:04.627384 ===================================
3912 22:56:04.631080 ===================================
3913 22:56:04.634327 memory_type:LPDDR4
3914 22:56:04.637434 GP_NUM : 10
3915 22:56:04.637547 SRAM_EN : 1
3916 22:56:04.640769 MD32_EN : 0
3917 22:56:04.643802 ===================================
3918 22:56:04.647511 [ANA_INIT] >>>>>>>>>>>>>>
3919 22:56:04.650430 <<<<<< [CONFIGURE PHASE]: ANA_TX
3920 22:56:04.653851 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3921 22:56:04.657034 ===================================
3922 22:56:04.657117 data_rate = 1200,PCW = 0X5800
3923 22:56:04.660613 ===================================
3924 22:56:04.663848 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3925 22:56:04.670270 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3926 22:56:04.676887 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3927 22:56:04.680181 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3928 22:56:04.683489 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3929 22:56:04.686912 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3930 22:56:04.690099 [ANA_INIT] flow start
3931 22:56:04.693401 [ANA_INIT] PLL >>>>>>>>
3932 22:56:04.693483 [ANA_INIT] PLL <<<<<<<<
3933 22:56:04.697225 [ANA_INIT] MIDPI >>>>>>>>
3934 22:56:04.700364 [ANA_INIT] MIDPI <<<<<<<<
3935 22:56:04.700446 [ANA_INIT] DLL >>>>>>>>
3936 22:56:04.703725 [ANA_INIT] flow end
3937 22:56:04.706422 ============ LP4 DIFF to SE enter ============
3938 22:56:04.709918 ============ LP4 DIFF to SE exit ============
3939 22:56:04.713248 [ANA_INIT] <<<<<<<<<<<<<
3940 22:56:04.716842 [Flow] Enable top DCM control >>>>>
3941 22:56:04.720252 [Flow] Enable top DCM control <<<<<
3942 22:56:04.723605 Enable DLL master slave shuffle
3943 22:56:04.729869 ==============================================================
3944 22:56:04.729952 Gating Mode config
3945 22:56:04.736503 ==============================================================
3946 22:56:04.739609 Config description:
3947 22:56:04.746352 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3948 22:56:04.752797 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3949 22:56:04.759524 SELPH_MODE 0: By rank 1: By Phase
3950 22:56:04.765991 ==============================================================
3951 22:56:04.766069 GAT_TRACK_EN = 1
3952 22:56:04.769588 RX_GATING_MODE = 2
3953 22:56:04.772369 RX_GATING_TRACK_MODE = 2
3954 22:56:04.775775 SELPH_MODE = 1
3955 22:56:04.779201 PICG_EARLY_EN = 1
3956 22:56:04.782473 VALID_LAT_VALUE = 1
3957 22:56:04.788871 ==============================================================
3958 22:56:04.792210 Enter into Gating configuration >>>>
3959 22:56:04.795711 Exit from Gating configuration <<<<
3960 22:56:04.798733 Enter into DVFS_PRE_config >>>>>
3961 22:56:04.809402 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3962 22:56:04.812409 Exit from DVFS_PRE_config <<<<<
3963 22:56:04.815514 Enter into PICG configuration >>>>
3964 22:56:04.818539 Exit from PICG configuration <<<<
3965 22:56:04.822007 [RX_INPUT] configuration >>>>>
3966 22:56:04.825103 [RX_INPUT] configuration <<<<<
3967 22:56:04.828893 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3968 22:56:04.835016 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3969 22:56:04.841657 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3970 22:56:04.848269 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3971 22:56:04.851548 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3972 22:56:04.858395 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3973 22:56:04.861804 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3974 22:56:04.868294 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3975 22:56:04.871481 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3976 22:56:04.874728 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3977 22:56:04.878375 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3978 22:56:04.884492 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3979 22:56:04.888266 ===================================
3980 22:56:04.891009 LPDDR4 DRAM CONFIGURATION
3981 22:56:04.894567 ===================================
3982 22:56:04.894649 EX_ROW_EN[0] = 0x0
3983 22:56:04.898234 EX_ROW_EN[1] = 0x0
3984 22:56:04.898316 LP4Y_EN = 0x0
3985 22:56:04.901596 WORK_FSP = 0x0
3986 22:56:04.901678 WL = 0x2
3987 22:56:04.904557 RL = 0x2
3988 22:56:04.904640 BL = 0x2
3989 22:56:04.907877 RPST = 0x0
3990 22:56:04.907960 RD_PRE = 0x0
3991 22:56:04.911369 WR_PRE = 0x1
3992 22:56:04.911452 WR_PST = 0x0
3993 22:56:04.914120 DBI_WR = 0x0
3994 22:56:04.917456 DBI_RD = 0x0
3995 22:56:04.917552 OTF = 0x1
3996 22:56:04.920786 ===================================
3997 22:56:04.923981 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3998 22:56:04.927278 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3999 22:56:04.934269 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
4000 22:56:04.937725 ===================================
4001 22:56:04.941076 LPDDR4 DRAM CONFIGURATION
4002 22:56:04.944168 ===================================
4003 22:56:04.944241 EX_ROW_EN[0] = 0x10
4004 22:56:04.947403 EX_ROW_EN[1] = 0x0
4005 22:56:04.947474 LP4Y_EN = 0x0
4006 22:56:04.950686 WORK_FSP = 0x0
4007 22:56:04.950781 WL = 0x2
4008 22:56:04.954080 RL = 0x2
4009 22:56:04.954175 BL = 0x2
4010 22:56:04.957032 RPST = 0x0
4011 22:56:04.957128 RD_PRE = 0x0
4012 22:56:04.960616 WR_PRE = 0x1
4013 22:56:04.963802 WR_PST = 0x0
4014 22:56:04.963897 DBI_WR = 0x0
4015 22:56:04.967204 DBI_RD = 0x0
4016 22:56:04.967300 OTF = 0x1
4017 22:56:04.970223 ===================================
4018 22:56:04.976732 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4019 22:56:04.980630 nWR fixed to 30
4020 22:56:04.984125 [ModeRegInit_LP4] CH0 RK0
4021 22:56:04.984229 [ModeRegInit_LP4] CH0 RK1
4022 22:56:04.986923 [ModeRegInit_LP4] CH1 RK0
4023 22:56:04.990627 [ModeRegInit_LP4] CH1 RK1
4024 22:56:04.990732 match AC timing 17
4025 22:56:04.997140 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
4026 22:56:05.000027 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4027 22:56:05.003585 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
4028 22:56:05.009883 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
4029 22:56:05.013272 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
4030 22:56:05.013352 ==
4031 22:56:05.016613 Dram Type= 6, Freq= 0, CH_0, rank 0
4032 22:56:05.019877 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4033 22:56:05.019979 ==
4034 22:56:05.026675 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4035 22:56:05.032918 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4036 22:56:05.036766 [CA 0] Center 35 (5~66) winsize 62
4037 22:56:05.039745 [CA 1] Center 36 (6~66) winsize 61
4038 22:56:05.042703 [CA 2] Center 34 (4~65) winsize 62
4039 22:56:05.046249 [CA 3] Center 34 (4~65) winsize 62
4040 22:56:05.049674 [CA 4] Center 33 (3~64) winsize 62
4041 22:56:05.052683 [CA 5] Center 33 (3~64) winsize 62
4042 22:56:05.052798
4043 22:56:05.055964 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4044 22:56:05.056059
4045 22:56:05.059836 [CATrainingPosCal] consider 1 rank data
4046 22:56:05.062869 u2DelayCellTimex100 = 270/100 ps
4047 22:56:05.066302 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4048 22:56:05.069257 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4049 22:56:05.072580 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4050 22:56:05.079462 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4051 22:56:05.083161 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4052 22:56:05.085902 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4053 22:56:05.085991
4054 22:56:05.089320 CA PerBit enable=1, Macro0, CA PI delay=33
4055 22:56:05.089404
4056 22:56:05.092207 [CBTSetCACLKResult] CA Dly = 33
4057 22:56:05.092283 CS Dly: 5 (0~36)
4058 22:56:05.092382 ==
4059 22:56:05.095446 Dram Type= 6, Freq= 0, CH_0, rank 1
4060 22:56:05.102334 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4061 22:56:05.102415 ==
4062 22:56:05.105409 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4063 22:56:05.112060 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4064 22:56:05.116150 [CA 0] Center 35 (5~66) winsize 62
4065 22:56:05.118985 [CA 1] Center 36 (6~66) winsize 61
4066 22:56:05.122770 [CA 2] Center 33 (3~64) winsize 62
4067 22:56:05.125914 [CA 3] Center 34 (4~64) winsize 61
4068 22:56:05.129106 [CA 4] Center 33 (2~64) winsize 63
4069 22:56:05.132347 [CA 5] Center 33 (2~64) winsize 63
4070 22:56:05.132424
4071 22:56:05.135744 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4072 22:56:05.135817
4073 22:56:05.138937 [CATrainingPosCal] consider 2 rank data
4074 22:56:05.142770 u2DelayCellTimex100 = 270/100 ps
4075 22:56:05.145553 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4076 22:56:05.152035 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4077 22:56:05.155502 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
4078 22:56:05.159399 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4079 22:56:05.162356 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4080 22:56:05.165359 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4081 22:56:05.165430
4082 22:56:05.169173 CA PerBit enable=1, Macro0, CA PI delay=33
4083 22:56:05.169247
4084 22:56:05.171953 [CBTSetCACLKResult] CA Dly = 33
4085 22:56:05.175993 CS Dly: 5 (0~37)
4086 22:56:05.176069
4087 22:56:05.178753 ----->DramcWriteLeveling(PI) begin...
4088 22:56:05.178850 ==
4089 22:56:05.182213 Dram Type= 6, Freq= 0, CH_0, rank 0
4090 22:56:05.185373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4091 22:56:05.185447 ==
4092 22:56:05.188442 Write leveling (Byte 0): 32 => 32
4093 22:56:05.192067 Write leveling (Byte 1): 32 => 32
4094 22:56:05.195133 DramcWriteLeveling(PI) end<-----
4095 22:56:05.195207
4096 22:56:05.195268 ==
4097 22:56:05.198544 Dram Type= 6, Freq= 0, CH_0, rank 0
4098 22:56:05.202231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4099 22:56:05.202310 ==
4100 22:56:05.205490 [Gating] SW mode calibration
4101 22:56:05.211696 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4102 22:56:05.218123 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4103 22:56:05.221625 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4104 22:56:05.224959 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4105 22:56:05.231420 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4106 22:56:05.234833 0 9 12 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
4107 22:56:05.237997 0 9 16 | B1->B0 | 2f2f 2424 | 0 0 | (0 0) (0 0)
4108 22:56:05.244475 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4109 22:56:05.248071 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4110 22:56:05.250915 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4111 22:56:05.257493 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4112 22:56:05.261356 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4113 22:56:05.264665 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4114 22:56:05.270756 0 10 12 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
4115 22:56:05.274373 0 10 16 | B1->B0 | 3535 4343 | 0 0 | (0 0) (0 0)
4116 22:56:05.277788 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4117 22:56:05.284034 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4118 22:56:05.287337 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4119 22:56:05.290950 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4120 22:56:05.297265 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4121 22:56:05.300540 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4122 22:56:05.304264 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4123 22:56:05.310396 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4124 22:56:05.314207 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4125 22:56:05.317054 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4126 22:56:05.323571 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4127 22:56:05.327020 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4128 22:56:05.330675 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4129 22:56:05.336799 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4130 22:56:05.340091 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4131 22:56:05.344010 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4132 22:56:05.350016 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4133 22:56:05.353390 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4134 22:56:05.356764 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4135 22:56:05.363143 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4136 22:56:05.366411 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4137 22:56:05.369530 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4138 22:56:05.376348 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4139 22:56:05.379751 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4140 22:56:05.383030 Total UI for P1: 0, mck2ui 16
4141 22:56:05.386504 best dqsien dly found for B0: ( 0, 13, 12)
4142 22:56:05.389387 Total UI for P1: 0, mck2ui 16
4143 22:56:05.392705 best dqsien dly found for B1: ( 0, 13, 14)
4144 22:56:05.395969 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4145 22:56:05.399401 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4146 22:56:05.399493
4147 22:56:05.402686 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4148 22:56:05.409501 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4149 22:56:05.409617 [Gating] SW calibration Done
4150 22:56:05.409715 ==
4151 22:56:05.412637 Dram Type= 6, Freq= 0, CH_0, rank 0
4152 22:56:05.419305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4153 22:56:05.419400 ==
4154 22:56:05.419466 RX Vref Scan: 0
4155 22:56:05.419526
4156 22:56:05.422326 RX Vref 0 -> 0, step: 1
4157 22:56:05.422409
4158 22:56:05.425955 RX Delay -230 -> 252, step: 16
4159 22:56:05.429077 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4160 22:56:05.432353 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4161 22:56:05.438820 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4162 22:56:05.442237 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4163 22:56:05.445486 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4164 22:56:05.448834 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4165 22:56:05.452103 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4166 22:56:05.458961 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4167 22:56:05.462225 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4168 22:56:05.465962 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4169 22:56:05.468990 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4170 22:56:05.475335 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4171 22:56:05.478518 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4172 22:56:05.481668 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4173 22:56:05.484952 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4174 22:56:05.492021 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4175 22:56:05.492180 ==
4176 22:56:05.495087 Dram Type= 6, Freq= 0, CH_0, rank 0
4177 22:56:05.498254 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4178 22:56:05.498336 ==
4179 22:56:05.498401 DQS Delay:
4180 22:56:05.501503 DQS0 = 0, DQS1 = 0
4181 22:56:05.501591 DQM Delay:
4182 22:56:05.504780 DQM0 = 41, DQM1 = 30
4183 22:56:05.504869 DQ Delay:
4184 22:56:05.508100 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4185 22:56:05.511655 DQ4 =41, DQ5 =33, DQ6 =57, DQ7 =49
4186 22:56:05.514933 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4187 22:56:05.518416 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4188 22:56:05.518499
4189 22:56:05.518564
4190 22:56:05.518625 ==
4191 22:56:05.521716 Dram Type= 6, Freq= 0, CH_0, rank 0
4192 22:56:05.524982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4193 22:56:05.528173 ==
4194 22:56:05.528254
4195 22:56:05.528318
4196 22:56:05.528378 TX Vref Scan disable
4197 22:56:05.531556 == TX Byte 0 ==
4198 22:56:05.534532 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4199 22:56:05.538311 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4200 22:56:05.541374 == TX Byte 1 ==
4201 22:56:05.544349 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4202 22:56:05.547637 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4203 22:56:05.551441 ==
4204 22:56:05.554635 Dram Type= 6, Freq= 0, CH_0, rank 0
4205 22:56:05.557795 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4206 22:56:05.557894 ==
4207 22:56:05.557960
4208 22:56:05.558021
4209 22:56:05.561207 TX Vref Scan disable
4210 22:56:05.561290 == TX Byte 0 ==
4211 22:56:05.567790 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4212 22:56:05.571114 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4213 22:56:05.574650 == TX Byte 1 ==
4214 22:56:05.577372 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4215 22:56:05.580832 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4216 22:56:05.580951
4217 22:56:05.581022 [DATLAT]
4218 22:56:05.584507 Freq=600, CH0 RK0
4219 22:56:05.584634
4220 22:56:05.584701 DATLAT Default: 0x9
4221 22:56:05.587327 0, 0xFFFF, sum = 0
4222 22:56:05.591236 1, 0xFFFF, sum = 0
4223 22:56:05.591339 2, 0xFFFF, sum = 0
4224 22:56:05.594566 3, 0xFFFF, sum = 0
4225 22:56:05.594692 4, 0xFFFF, sum = 0
4226 22:56:05.597408 5, 0xFFFF, sum = 0
4227 22:56:05.597503 6, 0xFFFF, sum = 0
4228 22:56:05.600884 7, 0xFFFF, sum = 0
4229 22:56:05.600975 8, 0x0, sum = 1
4230 22:56:05.603926 9, 0x0, sum = 2
4231 22:56:05.604022 10, 0x0, sum = 3
4232 22:56:05.607638 11, 0x0, sum = 4
4233 22:56:05.607742 best_step = 9
4234 22:56:05.607811
4235 22:56:05.607873 ==
4236 22:56:05.610705 Dram Type= 6, Freq= 0, CH_0, rank 0
4237 22:56:05.613801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4238 22:56:05.613933 ==
4239 22:56:05.617027 RX Vref Scan: 1
4240 22:56:05.617129
4241 22:56:05.620532 RX Vref 0 -> 0, step: 1
4242 22:56:05.620647
4243 22:56:05.620799 RX Delay -195 -> 252, step: 8
4244 22:56:05.620973
4245 22:56:05.623993 Set Vref, RX VrefLevel [Byte0]: 61
4246 22:56:05.627069 [Byte1]: 59
4247 22:56:05.631782
4248 22:56:05.631894 Final RX Vref Byte 0 = 61 to rank0
4249 22:56:05.634942 Final RX Vref Byte 1 = 59 to rank0
4250 22:56:05.638412 Final RX Vref Byte 0 = 61 to rank1
4251 22:56:05.641511 Final RX Vref Byte 1 = 59 to rank1==
4252 22:56:05.644720 Dram Type= 6, Freq= 0, CH_0, rank 0
4253 22:56:05.651250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4254 22:56:05.651371 ==
4255 22:56:05.651437 DQS Delay:
4256 22:56:05.654810 DQS0 = 0, DQS1 = 0
4257 22:56:05.654904 DQM Delay:
4258 22:56:05.654997 DQM0 = 43, DQM1 = 32
4259 22:56:05.658002 DQ Delay:
4260 22:56:05.661191 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4261 22:56:05.664737 DQ4 =44, DQ5 =36, DQ6 =52, DQ7 =48
4262 22:56:05.668176 DQ8 =24, DQ9 =20, DQ10 =32, DQ11 =24
4263 22:56:05.671511 DQ12 =40, DQ13 =36, DQ14 =40, DQ15 =40
4264 22:56:05.671613
4265 22:56:05.671707
4266 22:56:05.677623 [DQSOSCAuto] RK0, (LSB)MR18= 0x6941, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 390 ps
4267 22:56:05.681337 CH0 RK0: MR19=808, MR18=6941
4268 22:56:05.687582 CH0_RK0: MR19=0x808, MR18=0x6941, DQSOSC=390, MR23=63, INC=172, DEC=114
4269 22:56:05.687712
4270 22:56:05.691236 ----->DramcWriteLeveling(PI) begin...
4271 22:56:05.691348 ==
4272 22:56:05.694489 Dram Type= 6, Freq= 0, CH_0, rank 1
4273 22:56:05.697647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4274 22:56:05.697740 ==
4275 22:56:05.701345 Write leveling (Byte 0): 33 => 33
4276 22:56:05.704283 Write leveling (Byte 1): 31 => 31
4277 22:56:05.707375 DramcWriteLeveling(PI) end<-----
4278 22:56:05.707505
4279 22:56:05.707597 ==
4280 22:56:05.711307 Dram Type= 6, Freq= 0, CH_0, rank 1
4281 22:56:05.713924 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4282 22:56:05.717784 ==
4283 22:56:05.717914 [Gating] SW mode calibration
4284 22:56:05.727071 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4285 22:56:05.730578 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4286 22:56:05.734135 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4287 22:56:05.740219 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4288 22:56:05.743498 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4289 22:56:05.746614 0 9 12 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 0)
4290 22:56:05.753807 0 9 16 | B1->B0 | 2d2d 2525 | 0 0 | (0 0) (0 0)
4291 22:56:05.756639 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4292 22:56:05.760164 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4293 22:56:05.766671 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4294 22:56:05.770028 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4295 22:56:05.773530 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4296 22:56:05.780107 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4297 22:56:05.783290 0 10 12 | B1->B0 | 2424 2525 | 0 1 | (0 0) (0 0)
4298 22:56:05.786751 0 10 16 | B1->B0 | 3a3a 3e3e | 0 0 | (0 0) (0 0)
4299 22:56:05.793093 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4300 22:56:05.796691 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4301 22:56:05.799971 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4302 22:56:05.806112 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4303 22:56:05.809680 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4304 22:56:05.812591 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4305 22:56:05.819180 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4306 22:56:05.822501 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4307 22:56:05.825917 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4308 22:56:05.832305 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4309 22:56:05.835701 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4310 22:56:05.839004 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4311 22:56:05.845472 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4312 22:56:05.849116 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4313 22:56:05.855173 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4314 22:56:05.859071 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4315 22:56:05.862031 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4316 22:56:05.868537 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4317 22:56:05.872208 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4318 22:56:05.874919 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4319 22:56:05.881658 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4320 22:56:05.884955 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4321 22:56:05.887906 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4322 22:56:05.894629 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4323 22:56:05.894745 Total UI for P1: 0, mck2ui 16
4324 22:56:05.898522 best dqsien dly found for B0: ( 0, 13, 12)
4325 22:56:05.901474 Total UI for P1: 0, mck2ui 16
4326 22:56:05.904807 best dqsien dly found for B1: ( 0, 13, 12)
4327 22:56:05.911209 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4328 22:56:05.914667 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4329 22:56:05.914771
4330 22:56:05.918039 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4331 22:56:05.921195 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4332 22:56:05.924526 [Gating] SW calibration Done
4333 22:56:05.924621 ==
4334 22:56:05.927923 Dram Type= 6, Freq= 0, CH_0, rank 1
4335 22:56:05.931043 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4336 22:56:05.931138 ==
4337 22:56:05.934429 RX Vref Scan: 0
4338 22:56:05.934516
4339 22:56:05.934583 RX Vref 0 -> 0, step: 1
4340 22:56:05.934646
4341 22:56:05.937706 RX Delay -230 -> 252, step: 16
4342 22:56:05.944044 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4343 22:56:05.947398 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4344 22:56:05.950969 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4345 22:56:05.954638 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4346 22:56:05.957411 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4347 22:56:05.964051 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4348 22:56:05.967426 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4349 22:56:05.971029 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4350 22:56:05.974148 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4351 22:56:05.980374 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4352 22:56:05.983638 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4353 22:56:05.987110 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4354 22:56:05.990632 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4355 22:56:05.997029 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4356 22:56:06.000045 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4357 22:56:06.004066 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4358 22:56:06.004194 ==
4359 22:56:06.007335 Dram Type= 6, Freq= 0, CH_0, rank 1
4360 22:56:06.010246 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4361 22:56:06.013322 ==
4362 22:56:06.013454 DQS Delay:
4363 22:56:06.013551 DQS0 = 0, DQS1 = 0
4364 22:56:06.017147 DQM Delay:
4365 22:56:06.017238 DQM0 = 41, DQM1 = 35
4366 22:56:06.020061 DQ Delay:
4367 22:56:06.020174 DQ0 =41, DQ1 =49, DQ2 =33, DQ3 =33
4368 22:56:06.023301 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4369 22:56:06.027139 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =33
4370 22:56:06.030313 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4371 22:56:06.030417
4372 22:56:06.033306
4373 22:56:06.033397 ==
4374 22:56:06.036582 Dram Type= 6, Freq= 0, CH_0, rank 1
4375 22:56:06.040458 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4376 22:56:06.040577 ==
4377 22:56:06.040646
4378 22:56:06.040707
4379 22:56:06.043358 TX Vref Scan disable
4380 22:56:06.043447 == TX Byte 0 ==
4381 22:56:06.049895 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4382 22:56:06.053724 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4383 22:56:06.053827 == TX Byte 1 ==
4384 22:56:06.059898 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4385 22:56:06.063718 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4386 22:56:06.063831 ==
4387 22:56:06.066527 Dram Type= 6, Freq= 0, CH_0, rank 1
4388 22:56:06.069916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4389 22:56:06.070007 ==
4390 22:56:06.070071
4391 22:56:06.070142
4392 22:56:06.073007 TX Vref Scan disable
4393 22:56:06.077107 == TX Byte 0 ==
4394 22:56:06.080060 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4395 22:56:06.083172 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4396 22:56:06.086782 == TX Byte 1 ==
4397 22:56:06.089735 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4398 22:56:06.096348 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4399 22:56:06.096491
4400 22:56:06.096597 [DATLAT]
4401 22:56:06.096659 Freq=600, CH0 RK1
4402 22:56:06.096733
4403 22:56:06.099576 DATLAT Default: 0x9
4404 22:56:06.099656 0, 0xFFFF, sum = 0
4405 22:56:06.102467 1, 0xFFFF, sum = 0
4406 22:56:06.106507 2, 0xFFFF, sum = 0
4407 22:56:06.106640 3, 0xFFFF, sum = 0
4408 22:56:06.109267 4, 0xFFFF, sum = 0
4409 22:56:06.109350 5, 0xFFFF, sum = 0
4410 22:56:06.112679 6, 0xFFFF, sum = 0
4411 22:56:06.112773 7, 0xFFFF, sum = 0
4412 22:56:06.115995 8, 0x0, sum = 1
4413 22:56:06.116092 9, 0x0, sum = 2
4414 22:56:06.116165 10, 0x0, sum = 3
4415 22:56:06.119334 11, 0x0, sum = 4
4416 22:56:06.119414 best_step = 9
4417 22:56:06.119489
4418 22:56:06.122322 ==
4419 22:56:06.122413 Dram Type= 6, Freq= 0, CH_0, rank 1
4420 22:56:06.129076 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4421 22:56:06.129232 ==
4422 22:56:06.129328 RX Vref Scan: 0
4423 22:56:06.129430
4424 22:56:06.132185 RX Vref 0 -> 0, step: 1
4425 22:56:06.132261
4426 22:56:06.135841 RX Delay -195 -> 252, step: 8
4427 22:56:06.142578 iDelay=205, Bit 0, Center 36 (-115 ~ 188) 304
4428 22:56:06.145730 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4429 22:56:06.148884 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4430 22:56:06.152118 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4431 22:56:06.155549 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4432 22:56:06.162603 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4433 22:56:06.165518 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4434 22:56:06.169423 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4435 22:56:06.172103 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4436 22:56:06.178985 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4437 22:56:06.182012 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4438 22:56:06.185233 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4439 22:56:06.188591 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4440 22:56:06.195009 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4441 22:56:06.198757 iDelay=205, Bit 14, Center 48 (-107 ~ 204) 312
4442 22:56:06.201717 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4443 22:56:06.201839 ==
4444 22:56:06.205062 Dram Type= 6, Freq= 0, CH_0, rank 1
4445 22:56:06.208381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4446 22:56:06.211723 ==
4447 22:56:06.211849 DQS Delay:
4448 22:56:06.211942 DQS0 = 0, DQS1 = 0
4449 22:56:06.214812 DQM Delay:
4450 22:56:06.214926 DQM0 = 41, DQM1 = 35
4451 22:56:06.218378 DQ Delay:
4452 22:56:06.218492 DQ0 =36, DQ1 =44, DQ2 =36, DQ3 =40
4453 22:56:06.221721 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4454 22:56:06.224646 DQ8 =24, DQ9 =24, DQ10 =40, DQ11 =28
4455 22:56:06.228295 DQ12 =40, DQ13 =40, DQ14 =48, DQ15 =40
4456 22:56:06.231550
4457 22:56:06.231679
4458 22:56:06.237980 [DQSOSCAuto] RK1, (LSB)MR18= 0x6014, (MSB)MR19= 0x808, tDQSOscB0 = 406 ps tDQSOscB1 = 391 ps
4459 22:56:06.241060 CH0 RK1: MR19=808, MR18=6014
4460 22:56:06.248241 CH0_RK1: MR19=0x808, MR18=0x6014, DQSOSC=391, MR23=63, INC=171, DEC=114
4461 22:56:06.251536 [RxdqsGatingPostProcess] freq 600
4462 22:56:06.254713 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4463 22:56:06.258038 Pre-setting of DQS Precalculation
4464 22:56:06.264713 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4465 22:56:06.264840 ==
4466 22:56:06.268062 Dram Type= 6, Freq= 0, CH_1, rank 0
4467 22:56:06.271956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4468 22:56:06.272092 ==
4469 22:56:06.277769 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4470 22:56:06.281380 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4471 22:56:06.285319 [CA 0] Center 35 (5~66) winsize 62
4472 22:56:06.288916 [CA 1] Center 36 (6~66) winsize 61
4473 22:56:06.291953 [CA 2] Center 34 (4~65) winsize 62
4474 22:56:06.295117 [CA 3] Center 33 (3~64) winsize 62
4475 22:56:06.298745 [CA 4] Center 34 (3~65) winsize 63
4476 22:56:06.301808 [CA 5] Center 33 (3~64) winsize 62
4477 22:56:06.301926
4478 22:56:06.305054 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4479 22:56:06.305158
4480 22:56:06.308547 [CATrainingPosCal] consider 1 rank data
4481 22:56:06.311634 u2DelayCellTimex100 = 270/100 ps
4482 22:56:06.314929 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4483 22:56:06.321348 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4484 22:56:06.325043 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4485 22:56:06.327944 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4486 22:56:06.331408 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4487 22:56:06.334495 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4488 22:56:06.334600
4489 22:56:06.338176 CA PerBit enable=1, Macro0, CA PI delay=33
4490 22:56:06.338263
4491 22:56:06.340982 [CBTSetCACLKResult] CA Dly = 33
4492 22:56:06.344275 CS Dly: 4 (0~35)
4493 22:56:06.344396 ==
4494 22:56:06.347676 Dram Type= 6, Freq= 0, CH_1, rank 1
4495 22:56:06.350916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4496 22:56:06.351009 ==
4497 22:56:06.357563 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4498 22:56:06.361124 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4499 22:56:06.365389 [CA 0] Center 35 (5~66) winsize 62
4500 22:56:06.368888 [CA 1] Center 36 (6~66) winsize 61
4501 22:56:06.372053 [CA 2] Center 34 (4~65) winsize 62
4502 22:56:06.375614 [CA 3] Center 34 (3~65) winsize 63
4503 22:56:06.379196 [CA 4] Center 34 (4~65) winsize 62
4504 22:56:06.381762 [CA 5] Center 34 (3~65) winsize 63
4505 22:56:06.381867
4506 22:56:06.385758 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4507 22:56:06.385854
4508 22:56:06.388739 [CATrainingPosCal] consider 2 rank data
4509 22:56:06.391652 u2DelayCellTimex100 = 270/100 ps
4510 22:56:06.395374 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4511 22:56:06.401894 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4512 22:56:06.404982 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4513 22:56:06.408195 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4514 22:56:06.411617 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4515 22:56:06.415141 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4516 22:56:06.415247
4517 22:56:06.418098 CA PerBit enable=1, Macro0, CA PI delay=33
4518 22:56:06.418180
4519 22:56:06.421467 [CBTSetCACLKResult] CA Dly = 33
4520 22:56:06.424600 CS Dly: 5 (0~37)
4521 22:56:06.424700
4522 22:56:06.428211 ----->DramcWriteLeveling(PI) begin...
4523 22:56:06.428310 ==
4524 22:56:06.431676 Dram Type= 6, Freq= 0, CH_1, rank 0
4525 22:56:06.435077 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4526 22:56:06.435178 ==
4527 22:56:06.438321 Write leveling (Byte 0): 30 => 30
4528 22:56:06.441627 Write leveling (Byte 1): 29 => 29
4529 22:56:06.444793 DramcWriteLeveling(PI) end<-----
4530 22:56:06.444895
4531 22:56:06.444986 ==
4532 22:56:06.448056 Dram Type= 6, Freq= 0, CH_1, rank 0
4533 22:56:06.450996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4534 22:56:06.451096 ==
4535 22:56:06.454406 [Gating] SW mode calibration
4536 22:56:06.461425 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4537 22:56:06.467726 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4538 22:56:06.471183 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4539 22:56:06.474409 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4540 22:56:06.480743 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4541 22:56:06.484259 0 9 12 | B1->B0 | 3232 2f2f | 1 1 | (0 1) (1 0)
4542 22:56:06.487608 0 9 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4543 22:56:06.494158 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4544 22:56:06.497725 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4545 22:56:06.501013 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4546 22:56:06.507785 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4547 22:56:06.510814 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4548 22:56:06.513805 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4549 22:56:06.520442 0 10 12 | B1->B0 | 3131 3a3a | 1 0 | (0 0) (1 1)
4550 22:56:06.523902 0 10 16 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
4551 22:56:06.527137 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4552 22:56:06.533594 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4553 22:56:06.537475 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4554 22:56:06.540507 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4555 22:56:06.547111 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4556 22:56:06.550219 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4557 22:56:06.553374 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4558 22:56:06.560110 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4559 22:56:06.563249 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4560 22:56:06.566566 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4561 22:56:06.573439 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4562 22:56:06.576638 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4563 22:56:06.579997 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4564 22:56:06.586865 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4565 22:56:06.589865 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4566 22:56:06.593584 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4567 22:56:06.600185 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4568 22:56:06.603433 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4569 22:56:06.606414 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4570 22:56:06.613412 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4571 22:56:06.616580 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4572 22:56:06.619894 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4573 22:56:06.626833 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4574 22:56:06.629440 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4575 22:56:06.633553 Total UI for P1: 0, mck2ui 16
4576 22:56:06.636605 best dqsien dly found for B0: ( 0, 13, 12)
4577 22:56:06.639516 Total UI for P1: 0, mck2ui 16
4578 22:56:06.642985 best dqsien dly found for B1: ( 0, 13, 12)
4579 22:56:06.646194 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4580 22:56:06.649398 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4581 22:56:06.649498
4582 22:56:06.652760 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4583 22:56:06.656524 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4584 22:56:06.659175 [Gating] SW calibration Done
4585 22:56:06.659313 ==
4586 22:56:06.662684 Dram Type= 6, Freq= 0, CH_1, rank 0
4587 22:56:06.666260 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4588 22:56:06.669802 ==
4589 22:56:06.669886 RX Vref Scan: 0
4590 22:56:06.669951
4591 22:56:06.673021 RX Vref 0 -> 0, step: 1
4592 22:56:06.673105
4593 22:56:06.675951 RX Delay -230 -> 252, step: 16
4594 22:56:06.679178 iDelay=218, Bit 0, Center 65 (-86 ~ 217) 304
4595 22:56:06.682733 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4596 22:56:06.686060 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4597 22:56:06.692622 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4598 22:56:06.695992 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4599 22:56:06.698889 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4600 22:56:06.702366 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4601 22:56:06.705353 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4602 22:56:06.712542 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4603 22:56:06.715683 iDelay=218, Bit 9, Center 33 (-134 ~ 201) 336
4604 22:56:06.719073 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4605 22:56:06.721880 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4606 22:56:06.728756 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4607 22:56:06.732332 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4608 22:56:06.735212 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4609 22:56:06.738461 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4610 22:56:06.741983 ==
4611 22:56:06.742171 Dram Type= 6, Freq= 0, CH_1, rank 0
4612 22:56:06.748296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4613 22:56:06.748399 ==
4614 22:56:06.748468 DQS Delay:
4615 22:56:06.751535 DQS0 = 0, DQS1 = 0
4616 22:56:06.751625 DQM Delay:
4617 22:56:06.755134 DQM0 = 49, DQM1 = 36
4618 22:56:06.755226 DQ Delay:
4619 22:56:06.758266 DQ0 =65, DQ1 =41, DQ2 =33, DQ3 =41
4620 22:56:06.761684 DQ4 =41, DQ5 =65, DQ6 =65, DQ7 =41
4621 22:56:06.764952 DQ8 =17, DQ9 =33, DQ10 =33, DQ11 =25
4622 22:56:06.768420 DQ12 =49, DQ13 =41, DQ14 =41, DQ15 =49
4623 22:56:06.768560
4624 22:56:06.768627
4625 22:56:06.768692 ==
4626 22:56:06.771490 Dram Type= 6, Freq= 0, CH_1, rank 0
4627 22:56:06.774401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4628 22:56:06.774509 ==
4629 22:56:06.774579
4630 22:56:06.774655
4631 22:56:06.777731 TX Vref Scan disable
4632 22:56:06.781139 == TX Byte 0 ==
4633 22:56:06.784397 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4634 22:56:06.787730 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4635 22:56:06.791444 == TX Byte 1 ==
4636 22:56:06.794614 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4637 22:56:06.797978 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4638 22:56:06.798083 ==
4639 22:56:06.801111 Dram Type= 6, Freq= 0, CH_1, rank 0
4640 22:56:06.807324 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4641 22:56:06.807471 ==
4642 22:56:06.807541
4643 22:56:06.807600
4644 22:56:06.807657 TX Vref Scan disable
4645 22:56:06.812385 == TX Byte 0 ==
4646 22:56:06.815585 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4647 22:56:06.822491 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4648 22:56:06.822597 == TX Byte 1 ==
4649 22:56:06.825777 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4650 22:56:06.831718 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4651 22:56:06.831852
4652 22:56:06.831920 [DATLAT]
4653 22:56:06.831985 Freq=600, CH1 RK0
4654 22:56:06.832044
4655 22:56:06.835355 DATLAT Default: 0x9
4656 22:56:06.835430 0, 0xFFFF, sum = 0
4657 22:56:06.838571 1, 0xFFFF, sum = 0
4658 22:56:06.841999 2, 0xFFFF, sum = 0
4659 22:56:06.842076 3, 0xFFFF, sum = 0
4660 22:56:06.845618 4, 0xFFFF, sum = 0
4661 22:56:06.845711 5, 0xFFFF, sum = 0
4662 22:56:06.848253 6, 0xFFFF, sum = 0
4663 22:56:06.848330 7, 0xFFFF, sum = 0
4664 22:56:06.851715 8, 0x0, sum = 1
4665 22:56:06.851794 9, 0x0, sum = 2
4666 22:56:06.851857 10, 0x0, sum = 3
4667 22:56:06.855118 11, 0x0, sum = 4
4668 22:56:06.855196 best_step = 9
4669 22:56:06.855260
4670 22:56:06.855320 ==
4671 22:56:06.858238 Dram Type= 6, Freq= 0, CH_1, rank 0
4672 22:56:06.864779 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4673 22:56:06.864883 ==
4674 22:56:06.864954 RX Vref Scan: 1
4675 22:56:06.865015
4676 22:56:06.868238 RX Vref 0 -> 0, step: 1
4677 22:56:06.868322
4678 22:56:06.871724 RX Delay -195 -> 252, step: 8
4679 22:56:06.871813
4680 22:56:06.874663 Set Vref, RX VrefLevel [Byte0]: 52
4681 22:56:06.878601 [Byte1]: 53
4682 22:56:06.878693
4683 22:56:06.881658 Final RX Vref Byte 0 = 52 to rank0
4684 22:56:06.884490 Final RX Vref Byte 1 = 53 to rank0
4685 22:56:06.888158 Final RX Vref Byte 0 = 52 to rank1
4686 22:56:06.891280 Final RX Vref Byte 1 = 53 to rank1==
4687 22:56:06.894894 Dram Type= 6, Freq= 0, CH_1, rank 0
4688 22:56:06.898012 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4689 22:56:06.898110 ==
4690 22:56:06.901394 DQS Delay:
4691 22:56:06.901474 DQS0 = 0, DQS1 = 0
4692 22:56:06.904688 DQM Delay:
4693 22:56:06.904770 DQM0 = 47, DQM1 = 37
4694 22:56:06.904841 DQ Delay:
4695 22:56:06.908133 DQ0 =52, DQ1 =44, DQ2 =40, DQ3 =40
4696 22:56:06.911165 DQ4 =44, DQ5 =56, DQ6 =56, DQ7 =44
4697 22:56:06.914785 DQ8 =24, DQ9 =24, DQ10 =40, DQ11 =28
4698 22:56:06.917882 DQ12 =48, DQ13 =40, DQ14 =44, DQ15 =48
4699 22:56:06.917979
4700 22:56:06.921128
4701 22:56:06.927871 [DQSOSCAuto] RK0, (LSB)MR18= 0x4f34, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 394 ps
4702 22:56:06.930996 CH1 RK0: MR19=808, MR18=4F34
4703 22:56:06.938243 CH1_RK0: MR19=0x808, MR18=0x4F34, DQSOSC=394, MR23=63, INC=168, DEC=112
4704 22:56:06.938368
4705 22:56:06.941008 ----->DramcWriteLeveling(PI) begin...
4706 22:56:06.941101 ==
4707 22:56:06.944345 Dram Type= 6, Freq= 0, CH_1, rank 1
4708 22:56:06.947410 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4709 22:56:06.947505 ==
4710 22:56:06.951009 Write leveling (Byte 0): 30 => 30
4711 22:56:06.953989 Write leveling (Byte 1): 30 => 30
4712 22:56:06.957707 DramcWriteLeveling(PI) end<-----
4713 22:56:06.957811
4714 22:56:06.957882 ==
4715 22:56:06.960959 Dram Type= 6, Freq= 0, CH_1, rank 1
4716 22:56:06.963965 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4717 22:56:06.964060 ==
4718 22:56:06.967119 [Gating] SW mode calibration
4719 22:56:06.973792 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4720 22:56:06.980344 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4721 22:56:06.984067 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4722 22:56:06.990798 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4723 22:56:06.993959 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4724 22:56:06.997332 0 9 12 | B1->B0 | 2f2f 3333 | 1 0 | (1 0) (0 1)
4725 22:56:07.003449 0 9 16 | B1->B0 | 2323 2525 | 0 1 | (0 0) (1 0)
4726 22:56:07.006857 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4727 22:56:07.010766 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4728 22:56:07.016542 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4729 22:56:07.019939 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4730 22:56:07.023524 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4731 22:56:07.029913 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4732 22:56:07.033405 0 10 12 | B1->B0 | 3131 2525 | 0 1 | (0 0) (1 1)
4733 22:56:07.036239 0 10 16 | B1->B0 | 4646 3f3f | 0 0 | (0 0) (0 0)
4734 22:56:07.043295 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4735 22:56:07.046611 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4736 22:56:07.049736 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4737 22:56:07.056141 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4738 22:56:07.059655 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4739 22:56:07.063259 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4740 22:56:07.069793 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4741 22:56:07.072624 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4742 22:56:07.076103 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4743 22:56:07.082355 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4744 22:56:07.085825 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4745 22:56:07.089178 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4746 22:56:07.095721 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4747 22:56:07.099121 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4748 22:56:07.102679 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4749 22:56:07.108730 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4750 22:56:07.111956 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4751 22:56:07.115203 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4752 22:56:07.121840 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4753 22:56:07.125362 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4754 22:56:07.128501 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4755 22:56:07.135291 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4756 22:56:07.138558 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4757 22:56:07.141922 Total UI for P1: 0, mck2ui 16
4758 22:56:07.145335 best dqsien dly found for B1: ( 0, 13, 10)
4759 22:56:07.148892 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4760 22:56:07.151941 Total UI for P1: 0, mck2ui 16
4761 22:56:07.155452 best dqsien dly found for B0: ( 0, 13, 12)
4762 22:56:07.158508 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4763 22:56:07.161794 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4764 22:56:07.161906
4765 22:56:07.165151 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4766 22:56:07.172029 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4767 22:56:07.172181 [Gating] SW calibration Done
4768 22:56:07.172305 ==
4769 22:56:07.175235 Dram Type= 6, Freq= 0, CH_1, rank 1
4770 22:56:07.181727 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4771 22:56:07.181887 ==
4772 22:56:07.181967 RX Vref Scan: 0
4773 22:56:07.182028
4774 22:56:07.185058 RX Vref 0 -> 0, step: 1
4775 22:56:07.185155
4776 22:56:07.188421 RX Delay -230 -> 252, step: 16
4777 22:56:07.191529 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4778 22:56:07.195372 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4779 22:56:07.201772 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4780 22:56:07.204905 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4781 22:56:07.208117 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4782 22:56:07.211676 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4783 22:56:07.214691 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4784 22:56:07.221335 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4785 22:56:07.224747 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4786 22:56:07.228004 iDelay=218, Bit 9, Center 25 (-150 ~ 201) 352
4787 22:56:07.231774 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4788 22:56:07.237960 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4789 22:56:07.241164 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4790 22:56:07.244377 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4791 22:56:07.248035 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4792 22:56:07.254209 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4793 22:56:07.254330 ==
4794 22:56:07.257962 Dram Type= 6, Freq= 0, CH_1, rank 1
4795 22:56:07.261092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4796 22:56:07.261196 ==
4797 22:56:07.261267 DQS Delay:
4798 22:56:07.264159 DQS0 = 0, DQS1 = 0
4799 22:56:07.264244 DQM Delay:
4800 22:56:07.267362 DQM0 = 44, DQM1 = 37
4801 22:56:07.267449 DQ Delay:
4802 22:56:07.270562 DQ0 =49, DQ1 =41, DQ2 =25, DQ3 =41
4803 22:56:07.274438 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4804 22:56:07.277857 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4805 22:56:07.280471 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4806 22:56:07.280613
4807 22:56:07.280693
4808 22:56:07.280755 ==
4809 22:56:07.283822 Dram Type= 6, Freq= 0, CH_1, rank 1
4810 22:56:07.290640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4811 22:56:07.290780 ==
4812 22:56:07.290852
4813 22:56:07.290915
4814 22:56:07.290975 TX Vref Scan disable
4815 22:56:07.294154 == TX Byte 0 ==
4816 22:56:07.297073 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4817 22:56:07.303695 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4818 22:56:07.303828 == TX Byte 1 ==
4819 22:56:07.306949 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4820 22:56:07.313881 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4821 22:56:07.314002 ==
4822 22:56:07.317156 Dram Type= 6, Freq= 0, CH_1, rank 1
4823 22:56:07.320258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4824 22:56:07.320385 ==
4825 22:56:07.320484
4826 22:56:07.320589
4827 22:56:07.323755 TX Vref Scan disable
4828 22:56:07.326576 == TX Byte 0 ==
4829 22:56:07.329816 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4830 22:56:07.333340 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4831 22:56:07.336752 == TX Byte 1 ==
4832 22:56:07.340245 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4833 22:56:07.343123 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4834 22:56:07.343218
4835 22:56:07.346541 [DATLAT]
4836 22:56:07.346653 Freq=600, CH1 RK1
4837 22:56:07.346723
4838 22:56:07.349767 DATLAT Default: 0x9
4839 22:56:07.349885 0, 0xFFFF, sum = 0
4840 22:56:07.352973 1, 0xFFFF, sum = 0
4841 22:56:07.353091 2, 0xFFFF, sum = 0
4842 22:56:07.356189 3, 0xFFFF, sum = 0
4843 22:56:07.356311 4, 0xFFFF, sum = 0
4844 22:56:07.359987 5, 0xFFFF, sum = 0
4845 22:56:07.360118 6, 0xFFFF, sum = 0
4846 22:56:07.362960 7, 0xFFFF, sum = 0
4847 22:56:07.363089 8, 0x0, sum = 1
4848 22:56:07.366351 9, 0x0, sum = 2
4849 22:56:07.366471 10, 0x0, sum = 3
4850 22:56:07.369720 11, 0x0, sum = 4
4851 22:56:07.369845 best_step = 9
4852 22:56:07.369947
4853 22:56:07.370049 ==
4854 22:56:07.372817 Dram Type= 6, Freq= 0, CH_1, rank 1
4855 22:56:07.376248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4856 22:56:07.376384 ==
4857 22:56:07.379701 RX Vref Scan: 0
4858 22:56:07.379845
4859 22:56:07.382879 RX Vref 0 -> 0, step: 1
4860 22:56:07.383004
4861 22:56:07.385968 RX Delay -195 -> 252, step: 8
4862 22:56:07.389087 iDelay=213, Bit 0, Center 48 (-99 ~ 196) 296
4863 22:56:07.392495 iDelay=213, Bit 1, Center 40 (-107 ~ 188) 296
4864 22:56:07.398901 iDelay=213, Bit 2, Center 32 (-115 ~ 180) 296
4865 22:56:07.402482 iDelay=213, Bit 3, Center 40 (-107 ~ 188) 296
4866 22:56:07.405990 iDelay=213, Bit 4, Center 44 (-107 ~ 196) 304
4867 22:56:07.409282 iDelay=213, Bit 5, Center 56 (-91 ~ 204) 296
4868 22:56:07.415506 iDelay=213, Bit 6, Center 60 (-91 ~ 212) 304
4869 22:56:07.419128 iDelay=213, Bit 7, Center 44 (-107 ~ 196) 304
4870 22:56:07.422183 iDelay=213, Bit 8, Center 24 (-131 ~ 180) 312
4871 22:56:07.425681 iDelay=213, Bit 9, Center 24 (-131 ~ 180) 312
4872 22:56:07.429219 iDelay=213, Bit 10, Center 32 (-123 ~ 188) 312
4873 22:56:07.435178 iDelay=213, Bit 11, Center 24 (-131 ~ 180) 312
4874 22:56:07.438521 iDelay=213, Bit 12, Center 48 (-107 ~ 204) 312
4875 22:56:07.442232 iDelay=213, Bit 13, Center 44 (-107 ~ 196) 304
4876 22:56:07.448554 iDelay=213, Bit 14, Center 44 (-107 ~ 196) 304
4877 22:56:07.451871 iDelay=213, Bit 15, Center 48 (-107 ~ 204) 312
4878 22:56:07.451981 ==
4879 22:56:07.455539 Dram Type= 6, Freq= 0, CH_1, rank 1
4880 22:56:07.458287 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4881 22:56:07.458397 ==
4882 22:56:07.458491 DQS Delay:
4883 22:56:07.461684 DQS0 = 0, DQS1 = 0
4884 22:56:07.461778 DQM Delay:
4885 22:56:07.465247 DQM0 = 45, DQM1 = 36
4886 22:56:07.465372 DQ Delay:
4887 22:56:07.468419 DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =40
4888 22:56:07.471690 DQ4 =44, DQ5 =56, DQ6 =60, DQ7 =44
4889 22:56:07.475072 DQ8 =24, DQ9 =24, DQ10 =32, DQ11 =24
4890 22:56:07.478300 DQ12 =48, DQ13 =44, DQ14 =44, DQ15 =48
4891 22:56:07.478419
4892 22:56:07.478509
4893 22:56:07.487931 [DQSOSCAuto] RK1, (LSB)MR18= 0x352a, (MSB)MR19= 0x808, tDQSOscB0 = 401 ps tDQSOscB1 = 399 ps
4894 22:56:07.488080 CH1 RK1: MR19=808, MR18=352A
4895 22:56:07.494718 CH1_RK1: MR19=0x808, MR18=0x352A, DQSOSC=399, MR23=63, INC=164, DEC=109
4896 22:56:07.498011 [RxdqsGatingPostProcess] freq 600
4897 22:56:07.504702 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4898 22:56:07.508121 Pre-setting of DQS Precalculation
4899 22:56:07.511480 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4900 22:56:07.518060 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4901 22:56:07.528137 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4902 22:56:07.528265
4903 22:56:07.528343
4904 22:56:07.530906 [Calibration Summary] 1200 Mbps
4905 22:56:07.531009 CH 0, Rank 0
4906 22:56:07.534294 SW Impedance : PASS
4907 22:56:07.534384 DUTY Scan : NO K
4908 22:56:07.537576 ZQ Calibration : PASS
4909 22:56:07.541446 Jitter Meter : NO K
4910 22:56:07.541567 CBT Training : PASS
4911 22:56:07.544363 Write leveling : PASS
4912 22:56:07.547898 RX DQS gating : PASS
4913 22:56:07.548018 RX DQ/DQS(RDDQC) : PASS
4914 22:56:07.551520 TX DQ/DQS : PASS
4915 22:56:07.551633 RX DATLAT : PASS
4916 22:56:07.554166 RX DQ/DQS(Engine): PASS
4917 22:56:07.557390 TX OE : NO K
4918 22:56:07.557477 All Pass.
4919 22:56:07.557540
4920 22:56:07.557599 CH 0, Rank 1
4921 22:56:07.561316 SW Impedance : PASS
4922 22:56:07.563979 DUTY Scan : NO K
4923 22:56:07.564073 ZQ Calibration : PASS
4924 22:56:07.567690 Jitter Meter : NO K
4925 22:56:07.570923 CBT Training : PASS
4926 22:56:07.571013 Write leveling : PASS
4927 22:56:07.573820 RX DQS gating : PASS
4928 22:56:07.577250 RX DQ/DQS(RDDQC) : PASS
4929 22:56:07.577373 TX DQ/DQS : PASS
4930 22:56:07.580470 RX DATLAT : PASS
4931 22:56:07.583768 RX DQ/DQS(Engine): PASS
4932 22:56:07.583875 TX OE : NO K
4933 22:56:07.587506 All Pass.
4934 22:56:07.587620
4935 22:56:07.587715 CH 1, Rank 0
4936 22:56:07.590806 SW Impedance : PASS
4937 22:56:07.590886 DUTY Scan : NO K
4938 22:56:07.594148 ZQ Calibration : PASS
4939 22:56:07.597293 Jitter Meter : NO K
4940 22:56:07.597385 CBT Training : PASS
4941 22:56:07.600367 Write leveling : PASS
4942 22:56:07.603825 RX DQS gating : PASS
4943 22:56:07.603919 RX DQ/DQS(RDDQC) : PASS
4944 22:56:07.607287 TX DQ/DQS : PASS
4945 22:56:07.609959 RX DATLAT : PASS
4946 22:56:07.610046 RX DQ/DQS(Engine): PASS
4947 22:56:07.613385 TX OE : NO K
4948 22:56:07.613478 All Pass.
4949 22:56:07.613544
4950 22:56:07.616762 CH 1, Rank 1
4951 22:56:07.616848 SW Impedance : PASS
4952 22:56:07.620381 DUTY Scan : NO K
4953 22:56:07.623479 ZQ Calibration : PASS
4954 22:56:07.623568 Jitter Meter : NO K
4955 22:56:07.626608 CBT Training : PASS
4956 22:56:07.626695 Write leveling : PASS
4957 22:56:07.630190 RX DQS gating : PASS
4958 22:56:07.633560 RX DQ/DQS(RDDQC) : PASS
4959 22:56:07.633655 TX DQ/DQS : PASS
4960 22:56:07.636655 RX DATLAT : PASS
4961 22:56:07.640957 RX DQ/DQS(Engine): PASS
4962 22:56:07.641056 TX OE : NO K
4963 22:56:07.643707 All Pass.
4964 22:56:07.643792
4965 22:56:07.643858 DramC Write-DBI off
4966 22:56:07.646894 PER_BANK_REFRESH: Hybrid Mode
4967 22:56:07.649832 TX_TRACKING: ON
4968 22:56:07.656386 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4969 22:56:07.660332 [FAST_K] Save calibration result to emmc
4970 22:56:07.663434 dramc_set_vcore_voltage set vcore to 662500
4971 22:56:07.666468 Read voltage for 933, 3
4972 22:56:07.666565 Vio18 = 0
4973 22:56:07.669937 Vcore = 662500
4974 22:56:07.670037 Vdram = 0
4975 22:56:07.670113 Vddq = 0
4976 22:56:07.672980 Vmddr = 0
4977 22:56:07.676642 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4978 22:56:07.683038 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4979 22:56:07.683173 MEM_TYPE=3, freq_sel=17
4980 22:56:07.686284 sv_algorithm_assistance_LP4_1600
4981 22:56:07.693230 ============ PULL DRAM RESETB DOWN ============
4982 22:56:07.696367 ========== PULL DRAM RESETB DOWN end =========
4983 22:56:07.699339 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4984 22:56:07.703173 ===================================
4985 22:56:07.706410 LPDDR4 DRAM CONFIGURATION
4986 22:56:07.709848 ===================================
4987 22:56:07.712876 EX_ROW_EN[0] = 0x0
4988 22:56:07.712973 EX_ROW_EN[1] = 0x0
4989 22:56:07.715991 LP4Y_EN = 0x0
4990 22:56:07.716078 WORK_FSP = 0x0
4991 22:56:07.719345 WL = 0x3
4992 22:56:07.719463 RL = 0x3
4993 22:56:07.722512 BL = 0x2
4994 22:56:07.722629 RPST = 0x0
4995 22:56:07.726165 RD_PRE = 0x0
4996 22:56:07.726282 WR_PRE = 0x1
4997 22:56:07.729206 WR_PST = 0x0
4998 22:56:07.729347 DBI_WR = 0x0
4999 22:56:07.732334 DBI_RD = 0x0
5000 22:56:07.732477 OTF = 0x1
5001 22:56:07.736202 ===================================
5002 22:56:07.739621 ===================================
5003 22:56:07.742423 ANA top config
5004 22:56:07.745735 ===================================
5005 22:56:07.748892 DLL_ASYNC_EN = 0
5006 22:56:07.749039 ALL_SLAVE_EN = 1
5007 22:56:07.752897 NEW_RANK_MODE = 1
5008 22:56:07.755417 DLL_IDLE_MODE = 1
5009 22:56:07.759148 LP45_APHY_COMB_EN = 1
5010 22:56:07.762529 TX_ODT_DIS = 1
5011 22:56:07.762650 NEW_8X_MODE = 1
5012 22:56:07.765421 ===================================
5013 22:56:07.768845 ===================================
5014 22:56:07.772005 data_rate = 1866
5015 22:56:07.775648 CKR = 1
5016 22:56:07.778449 DQ_P2S_RATIO = 8
5017 22:56:07.782669 ===================================
5018 22:56:07.785133 CA_P2S_RATIO = 8
5019 22:56:07.788695 DQ_CA_OPEN = 0
5020 22:56:07.788797 DQ_SEMI_OPEN = 0
5021 22:56:07.791647 CA_SEMI_OPEN = 0
5022 22:56:07.795143 CA_FULL_RATE = 0
5023 22:56:07.798606 DQ_CKDIV4_EN = 1
5024 22:56:07.801494 CA_CKDIV4_EN = 1
5025 22:56:07.804666 CA_PREDIV_EN = 0
5026 22:56:07.804756 PH8_DLY = 0
5027 22:56:07.807893 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
5028 22:56:07.811528 DQ_AAMCK_DIV = 4
5029 22:56:07.814792 CA_AAMCK_DIV = 4
5030 22:56:07.818300 CA_ADMCK_DIV = 4
5031 22:56:07.821489 DQ_TRACK_CA_EN = 0
5032 22:56:07.824853 CA_PICK = 933
5033 22:56:07.824939 CA_MCKIO = 933
5034 22:56:07.827653 MCKIO_SEMI = 0
5035 22:56:07.831183 PLL_FREQ = 3732
5036 22:56:07.834854 DQ_UI_PI_RATIO = 32
5037 22:56:07.837671 CA_UI_PI_RATIO = 0
5038 22:56:07.841385 ===================================
5039 22:56:07.844237 ===================================
5040 22:56:07.847802 memory_type:LPDDR4
5041 22:56:07.847905 GP_NUM : 10
5042 22:56:07.851149 SRAM_EN : 1
5043 22:56:07.851239 MD32_EN : 0
5044 22:56:07.854705 ===================================
5045 22:56:07.857785 [ANA_INIT] >>>>>>>>>>>>>>
5046 22:56:07.861068 <<<<<< [CONFIGURE PHASE]: ANA_TX
5047 22:56:07.864396 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5048 22:56:07.867861 ===================================
5049 22:56:07.870714 data_rate = 1866,PCW = 0X8f00
5050 22:56:07.874264 ===================================
5051 22:56:07.877683 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5052 22:56:07.884549 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5053 22:56:07.887460 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5054 22:56:07.894200 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5055 22:56:07.897221 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5056 22:56:07.900531 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5057 22:56:07.900631 [ANA_INIT] flow start
5058 22:56:07.903696 [ANA_INIT] PLL >>>>>>>>
5059 22:56:07.907150 [ANA_INIT] PLL <<<<<<<<
5060 22:56:07.907246 [ANA_INIT] MIDPI >>>>>>>>
5061 22:56:07.910254 [ANA_INIT] MIDPI <<<<<<<<
5062 22:56:07.913942 [ANA_INIT] DLL >>>>>>>>
5063 22:56:07.914039 [ANA_INIT] flow end
5064 22:56:07.920109 ============ LP4 DIFF to SE enter ============
5065 22:56:07.923344 ============ LP4 DIFF to SE exit ============
5066 22:56:07.926665 [ANA_INIT] <<<<<<<<<<<<<
5067 22:56:07.929998 [Flow] Enable top DCM control >>>>>
5068 22:56:07.933378 [Flow] Enable top DCM control <<<<<
5069 22:56:07.937010 Enable DLL master slave shuffle
5070 22:56:07.940075 ==============================================================
5071 22:56:07.943371 Gating Mode config
5072 22:56:07.950031 ==============================================================
5073 22:56:07.950151 Config description:
5074 22:56:07.959707 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5075 22:56:07.966197 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5076 22:56:07.969557 SELPH_MODE 0: By rank 1: By Phase
5077 22:56:07.976117 ==============================================================
5078 22:56:07.979188 GAT_TRACK_EN = 1
5079 22:56:07.982544 RX_GATING_MODE = 2
5080 22:56:07.986548 RX_GATING_TRACK_MODE = 2
5081 22:56:07.989653 SELPH_MODE = 1
5082 22:56:07.992480 PICG_EARLY_EN = 1
5083 22:56:07.996145 VALID_LAT_VALUE = 1
5084 22:56:07.999115 ==============================================================
5085 22:56:08.002655 Enter into Gating configuration >>>>
5086 22:56:08.006076 Exit from Gating configuration <<<<
5087 22:56:08.009224 Enter into DVFS_PRE_config >>>>>
5088 22:56:08.022438 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5089 22:56:08.025703 Exit from DVFS_PRE_config <<<<<
5090 22:56:08.025825 Enter into PICG configuration >>>>
5091 22:56:08.029222 Exit from PICG configuration <<<<
5092 22:56:08.032483 [RX_INPUT] configuration >>>>>
5093 22:56:08.036251 [RX_INPUT] configuration <<<<<
5094 22:56:08.042178 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5095 22:56:08.045409 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5096 22:56:08.051836 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5097 22:56:08.058851 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5098 22:56:08.065455 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5099 22:56:08.071666 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5100 22:56:08.075541 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5101 22:56:08.078597 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5102 22:56:08.085260 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5103 22:56:08.088154 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5104 22:56:08.091526 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5105 22:56:08.094926 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5106 22:56:08.098327 ===================================
5107 22:56:08.101779 LPDDR4 DRAM CONFIGURATION
5108 22:56:08.104709 ===================================
5109 22:56:08.108416 EX_ROW_EN[0] = 0x0
5110 22:56:08.108555 EX_ROW_EN[1] = 0x0
5111 22:56:08.111705 LP4Y_EN = 0x0
5112 22:56:08.111796 WORK_FSP = 0x0
5113 22:56:08.114651 WL = 0x3
5114 22:56:08.114746 RL = 0x3
5115 22:56:08.118062 BL = 0x2
5116 22:56:08.118159 RPST = 0x0
5117 22:56:08.121413 RD_PRE = 0x0
5118 22:56:08.121544 WR_PRE = 0x1
5119 22:56:08.125109 WR_PST = 0x0
5120 22:56:08.128165 DBI_WR = 0x0
5121 22:56:08.128290 DBI_RD = 0x0
5122 22:56:08.131228 OTF = 0x1
5123 22:56:08.134646 ===================================
5124 22:56:08.137982 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5125 22:56:08.141257 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5126 22:56:08.144875 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5127 22:56:08.147556 ===================================
5128 22:56:08.151238 LPDDR4 DRAM CONFIGURATION
5129 22:56:08.154818 ===================================
5130 22:56:08.157839 EX_ROW_EN[0] = 0x10
5131 22:56:08.157967 EX_ROW_EN[1] = 0x0
5132 22:56:08.161413 LP4Y_EN = 0x0
5133 22:56:08.161535 WORK_FSP = 0x0
5134 22:56:08.164231 WL = 0x3
5135 22:56:08.164320 RL = 0x3
5136 22:56:08.167877 BL = 0x2
5137 22:56:08.167969 RPST = 0x0
5138 22:56:08.170785 RD_PRE = 0x0
5139 22:56:08.170876 WR_PRE = 0x1
5140 22:56:08.174523 WR_PST = 0x0
5141 22:56:08.174631 DBI_WR = 0x0
5142 22:56:08.177518 DBI_RD = 0x0
5143 22:56:08.180819 OTF = 0x1
5144 22:56:08.184077 ===================================
5145 22:56:08.187571 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5146 22:56:08.192481 nWR fixed to 30
5147 22:56:08.196079 [ModeRegInit_LP4] CH0 RK0
5148 22:56:08.196177 [ModeRegInit_LP4] CH0 RK1
5149 22:56:08.199601 [ModeRegInit_LP4] CH1 RK0
5150 22:56:08.202867 [ModeRegInit_LP4] CH1 RK1
5151 22:56:08.202958 match AC timing 9
5152 22:56:08.208859 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5153 22:56:08.212459 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5154 22:56:08.215427 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5155 22:56:08.222013 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5156 22:56:08.225717 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5157 22:56:08.225833 ==
5158 22:56:08.228936 Dram Type= 6, Freq= 0, CH_0, rank 0
5159 22:56:08.232068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5160 22:56:08.235663 ==
5161 22:56:08.239514 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5162 22:56:08.245836 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5163 22:56:08.248604 [CA 0] Center 37 (7~68) winsize 62
5164 22:56:08.251998 [CA 1] Center 37 (7~68) winsize 62
5165 22:56:08.255057 [CA 2] Center 34 (4~65) winsize 62
5166 22:56:08.258788 [CA 3] Center 34 (4~65) winsize 62
5167 22:56:08.261622 [CA 4] Center 33 (3~64) winsize 62
5168 22:56:08.265467 [CA 5] Center 33 (3~64) winsize 62
5169 22:56:08.265571
5170 22:56:08.268629 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5171 22:56:08.268711
5172 22:56:08.271824 [CATrainingPosCal] consider 1 rank data
5173 22:56:08.275138 u2DelayCellTimex100 = 270/100 ps
5174 22:56:08.278503 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5175 22:56:08.281348 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5176 22:56:08.284638 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5177 22:56:08.291720 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5178 22:56:08.294613 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5179 22:56:08.298352 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5180 22:56:08.298456
5181 22:56:08.301748 CA PerBit enable=1, Macro0, CA PI delay=33
5182 22:56:08.301845
5183 22:56:08.305122 [CBTSetCACLKResult] CA Dly = 33
5184 22:56:08.305211 CS Dly: 7 (0~38)
5185 22:56:08.305296 ==
5186 22:56:08.307802 Dram Type= 6, Freq= 0, CH_0, rank 1
5187 22:56:08.314913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5188 22:56:08.315023 ==
5189 22:56:08.317943 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5190 22:56:08.324679 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5191 22:56:08.327648 [CA 0] Center 37 (7~68) winsize 62
5192 22:56:08.331071 [CA 1] Center 37 (7~68) winsize 62
5193 22:56:08.334167 [CA 2] Center 34 (4~65) winsize 62
5194 22:56:08.337466 [CA 3] Center 34 (4~65) winsize 62
5195 22:56:08.340851 [CA 4] Center 33 (3~64) winsize 62
5196 22:56:08.344081 [CA 5] Center 33 (3~63) winsize 61
5197 22:56:08.344201
5198 22:56:08.347439 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5199 22:56:08.347522
5200 22:56:08.350681 [CATrainingPosCal] consider 2 rank data
5201 22:56:08.354061 u2DelayCellTimex100 = 270/100 ps
5202 22:56:08.357579 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5203 22:56:08.364267 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5204 22:56:08.367326 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5205 22:56:08.370515 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5206 22:56:08.373973 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5207 22:56:08.377218 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5208 22:56:08.377317
5209 22:56:08.380452 CA PerBit enable=1, Macro0, CA PI delay=33
5210 22:56:08.380604
5211 22:56:08.383719 [CBTSetCACLKResult] CA Dly = 33
5212 22:56:08.387183 CS Dly: 7 (0~39)
5213 22:56:08.387291
5214 22:56:08.390184 ----->DramcWriteLeveling(PI) begin...
5215 22:56:08.390272 ==
5216 22:56:08.393509 Dram Type= 6, Freq= 0, CH_0, rank 0
5217 22:56:08.396822 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5218 22:56:08.396919 ==
5219 22:56:08.400771 Write leveling (Byte 0): 31 => 31
5220 22:56:08.404036 Write leveling (Byte 1): 29 => 29
5221 22:56:08.406621 DramcWriteLeveling(PI) end<-----
5222 22:56:08.406712
5223 22:56:08.406793 ==
5224 22:56:08.410153 Dram Type= 6, Freq= 0, CH_0, rank 0
5225 22:56:08.413658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5226 22:56:08.413747 ==
5227 22:56:08.416634 [Gating] SW mode calibration
5228 22:56:08.423254 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5229 22:56:08.430292 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5230 22:56:08.433258 0 14 0 | B1->B0 | 2323 3333 | 0 1 | (0 0) (0 0)
5231 22:56:08.436558 0 14 4 | B1->B0 | 2e2e 3434 | 1 1 | (1 1) (1 1)
5232 22:56:08.443305 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5233 22:56:08.446976 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5234 22:56:08.449880 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5235 22:56:08.456783 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5236 22:56:08.459637 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5237 22:56:08.462796 0 14 28 | B1->B0 | 3434 2e2e | 1 0 | (1 0) (0 0)
5238 22:56:08.469838 0 15 0 | B1->B0 | 3030 2424 | 0 0 | (1 0) (0 0)
5239 22:56:08.472739 0 15 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5240 22:56:08.476504 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5241 22:56:08.483006 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5242 22:56:08.486231 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5243 22:56:08.489279 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5244 22:56:08.496089 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5245 22:56:08.499994 0 15 28 | B1->B0 | 2323 3232 | 0 1 | (0 0) (0 0)
5246 22:56:08.502605 1 0 0 | B1->B0 | 3636 4545 | 0 0 | (1 1) (0 0)
5247 22:56:08.509501 1 0 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5248 22:56:08.512454 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5249 22:56:08.515897 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5250 22:56:08.522350 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5251 22:56:08.526195 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5252 22:56:08.529357 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5253 22:56:08.535785 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5254 22:56:08.538834 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
5255 22:56:08.542186 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5256 22:56:08.548858 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5257 22:56:08.552295 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5258 22:56:08.555548 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5259 22:56:08.562258 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5260 22:56:08.565446 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5261 22:56:08.568821 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5262 22:56:08.575178 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5263 22:56:08.578659 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5264 22:56:08.581756 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5265 22:56:08.588365 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5266 22:56:08.591841 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5267 22:56:08.595224 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5268 22:56:08.601939 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5269 22:56:08.604860 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5270 22:56:08.607996 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5271 22:56:08.611640 Total UI for P1: 0, mck2ui 16
5272 22:56:08.615032 best dqsien dly found for B0: ( 1, 2, 28)
5273 22:56:08.621628 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5274 22:56:08.621798 Total UI for P1: 0, mck2ui 16
5275 22:56:08.627898 best dqsien dly found for B1: ( 1, 3, 0)
5276 22:56:08.631847 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5277 22:56:08.635096 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5278 22:56:08.635250
5279 22:56:08.637767 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5280 22:56:08.641056 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5281 22:56:08.644418 [Gating] SW calibration Done
5282 22:56:08.644582 ==
5283 22:56:08.648193 Dram Type= 6, Freq= 0, CH_0, rank 0
5284 22:56:08.651169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5285 22:56:08.651311 ==
5286 22:56:08.654255 RX Vref Scan: 0
5287 22:56:08.654374
5288 22:56:08.654500 RX Vref 0 -> 0, step: 1
5289 22:56:08.654597
5290 22:56:08.657493 RX Delay -80 -> 252, step: 8
5291 22:56:08.660794 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5292 22:56:08.668130 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5293 22:56:08.671506 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5294 22:56:08.674845 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5295 22:56:08.677701 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5296 22:56:08.680947 iDelay=208, Bit 5, Center 87 (-16 ~ 191) 208
5297 22:56:08.687613 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5298 22:56:08.690875 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5299 22:56:08.693867 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5300 22:56:08.697383 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5301 22:56:08.700711 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5302 22:56:08.707307 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5303 22:56:08.710488 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5304 22:56:08.713839 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5305 22:56:08.717213 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5306 22:56:08.720227 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5307 22:56:08.720346 ==
5308 22:56:08.723716 Dram Type= 6, Freq= 0, CH_0, rank 0
5309 22:56:08.729995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5310 22:56:08.730118 ==
5311 22:56:08.730187 DQS Delay:
5312 22:56:08.733175 DQS0 = 0, DQS1 = 0
5313 22:56:08.733262 DQM Delay:
5314 22:56:08.733324 DQM0 = 98, DQM1 = 87
5315 22:56:08.736470 DQ Delay:
5316 22:56:08.740156 DQ0 =103, DQ1 =99, DQ2 =91, DQ3 =91
5317 22:56:08.743208 DQ4 =103, DQ5 =87, DQ6 =107, DQ7 =107
5318 22:56:08.746715 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =79
5319 22:56:08.749858 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =91
5320 22:56:08.749953
5321 22:56:08.750021
5322 22:56:08.750083 ==
5323 22:56:08.753114 Dram Type= 6, Freq= 0, CH_0, rank 0
5324 22:56:08.756089 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5325 22:56:08.756180 ==
5326 22:56:08.756252
5327 22:56:08.759979
5328 22:56:08.760070 TX Vref Scan disable
5329 22:56:08.762641 == TX Byte 0 ==
5330 22:56:08.766364 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5331 22:56:08.769483 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5332 22:56:08.772902 == TX Byte 1 ==
5333 22:56:08.776134 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5334 22:56:08.779472 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5335 22:56:08.779606 ==
5336 22:56:08.782699 Dram Type= 6, Freq= 0, CH_0, rank 0
5337 22:56:08.789351 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5338 22:56:08.789497 ==
5339 22:56:08.789589
5340 22:56:08.789652
5341 22:56:08.789718 TX Vref Scan disable
5342 22:56:08.793377 == TX Byte 0 ==
5343 22:56:08.797130 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5344 22:56:08.803326 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5345 22:56:08.803445 == TX Byte 1 ==
5346 22:56:08.807056 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5347 22:56:08.813484 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5348 22:56:08.813605
5349 22:56:08.813680 [DATLAT]
5350 22:56:08.813743 Freq=933, CH0 RK0
5351 22:56:08.813804
5352 22:56:08.816649 DATLAT Default: 0xd
5353 22:56:08.816737 0, 0xFFFF, sum = 0
5354 22:56:08.819782 1, 0xFFFF, sum = 0
5355 22:56:08.823722 2, 0xFFFF, sum = 0
5356 22:56:08.823817 3, 0xFFFF, sum = 0
5357 22:56:08.826428 4, 0xFFFF, sum = 0
5358 22:56:08.826520 5, 0xFFFF, sum = 0
5359 22:56:08.830027 6, 0xFFFF, sum = 0
5360 22:56:08.830140 7, 0xFFFF, sum = 0
5361 22:56:08.833720 8, 0xFFFF, sum = 0
5362 22:56:08.833831 9, 0xFFFF, sum = 0
5363 22:56:08.836956 10, 0x0, sum = 1
5364 22:56:08.837067 11, 0x0, sum = 2
5365 22:56:08.840136 12, 0x0, sum = 3
5366 22:56:08.840241 13, 0x0, sum = 4
5367 22:56:08.840307 best_step = 11
5368 22:56:08.842996
5369 22:56:08.843094 ==
5370 22:56:08.846420 Dram Type= 6, Freq= 0, CH_0, rank 0
5371 22:56:08.849713 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5372 22:56:08.849801 ==
5373 22:56:08.849894 RX Vref Scan: 1
5374 22:56:08.850016
5375 22:56:08.852723 RX Vref 0 -> 0, step: 1
5376 22:56:08.852822
5377 22:56:08.856062 RX Delay -61 -> 252, step: 4
5378 22:56:08.856154
5379 22:56:08.859503 Set Vref, RX VrefLevel [Byte0]: 61
5380 22:56:08.863111 [Byte1]: 59
5381 22:56:08.866318
5382 22:56:08.866413 Final RX Vref Byte 0 = 61 to rank0
5383 22:56:08.869770 Final RX Vref Byte 1 = 59 to rank0
5384 22:56:08.872912 Final RX Vref Byte 0 = 61 to rank1
5385 22:56:08.875876 Final RX Vref Byte 1 = 59 to rank1==
5386 22:56:08.879494 Dram Type= 6, Freq= 0, CH_0, rank 0
5387 22:56:08.885596 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5388 22:56:08.885810 ==
5389 22:56:08.885882 DQS Delay:
5390 22:56:08.888757 DQS0 = 0, DQS1 = 0
5391 22:56:08.888870 DQM Delay:
5392 22:56:08.888953 DQM0 = 97, DQM1 = 86
5393 22:56:08.892489 DQ Delay:
5394 22:56:08.895553 DQ0 =98, DQ1 =98, DQ2 =94, DQ3 =94
5395 22:56:08.898776 DQ4 =98, DQ5 =88, DQ6 =106, DQ7 =104
5396 22:56:08.902115 DQ8 =78, DQ9 =76, DQ10 =86, DQ11 =84
5397 22:56:08.905389 DQ12 =90, DQ13 =90, DQ14 =96, DQ15 =92
5398 22:56:08.905491
5399 22:56:08.905557
5400 22:56:08.911905 [DQSOSCAuto] RK0, (LSB)MR18= 0x2e14, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 407 ps
5401 22:56:08.915649 CH0 RK0: MR19=505, MR18=2E14
5402 22:56:08.921997 CH0_RK0: MR19=0x505, MR18=0x2E14, DQSOSC=407, MR23=63, INC=65, DEC=43
5403 22:56:08.922124
5404 22:56:08.925450 ----->DramcWriteLeveling(PI) begin...
5405 22:56:08.925539 ==
5406 22:56:08.928502 Dram Type= 6, Freq= 0, CH_0, rank 1
5407 22:56:08.931774 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5408 22:56:08.931872 ==
5409 22:56:08.934929 Write leveling (Byte 0): 32 => 32
5410 22:56:08.938111 Write leveling (Byte 1): 31 => 31
5411 22:56:08.941849 DramcWriteLeveling(PI) end<-----
5412 22:56:08.941954
5413 22:56:08.942019 ==
5414 22:56:08.944663 Dram Type= 6, Freq= 0, CH_0, rank 1
5415 22:56:08.951521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5416 22:56:08.951678 ==
5417 22:56:08.951748 [Gating] SW mode calibration
5418 22:56:08.961514 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5419 22:56:08.964985 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5420 22:56:08.968189 0 14 0 | B1->B0 | 2929 3232 | 0 1 | (0 0) (1 1)
5421 22:56:08.974699 0 14 4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
5422 22:56:08.977992 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5423 22:56:08.981394 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5424 22:56:08.988119 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5425 22:56:08.991051 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5426 22:56:08.994295 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5427 22:56:09.000869 0 14 28 | B1->B0 | 3434 2f2f | 0 1 | (0 0) (1 1)
5428 22:56:09.004451 0 15 0 | B1->B0 | 3030 2a2a | 0 0 | (0 1) (1 1)
5429 22:56:09.007825 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5430 22:56:09.014683 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5431 22:56:09.017528 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5432 22:56:09.020967 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5433 22:56:09.027351 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5434 22:56:09.030707 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5435 22:56:09.034140 0 15 28 | B1->B0 | 2626 2f2f | 0 0 | (0 0) (0 0)
5436 22:56:09.040901 1 0 0 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
5437 22:56:09.044400 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5438 22:56:09.047287 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5439 22:56:09.054036 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5440 22:56:09.057325 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5441 22:56:09.060771 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5442 22:56:09.067365 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5443 22:56:09.070731 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5444 22:56:09.073995 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5445 22:56:09.080739 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5446 22:56:09.084404 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5447 22:56:09.086987 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5448 22:56:09.094097 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5449 22:56:09.097369 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5450 22:56:09.100765 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5451 22:56:09.106799 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5452 22:56:09.109957 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5453 22:56:09.113233 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5454 22:56:09.120383 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5455 22:56:09.123626 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5456 22:56:09.127182 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5457 22:56:09.133065 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5458 22:56:09.136406 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5459 22:56:09.139666 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5460 22:56:09.146345 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5461 22:56:09.146453 Total UI for P1: 0, mck2ui 16
5462 22:56:09.152970 best dqsien dly found for B0: ( 1, 2, 28)
5463 22:56:09.156115 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5464 22:56:09.159747 Total UI for P1: 0, mck2ui 16
5465 22:56:09.162909 best dqsien dly found for B1: ( 1, 2, 30)
5466 22:56:09.166019 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5467 22:56:09.169432 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5468 22:56:09.169522
5469 22:56:09.172761 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5470 22:56:09.175754 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5471 22:56:09.179139 [Gating] SW calibration Done
5472 22:56:09.179225 ==
5473 22:56:09.182962 Dram Type= 6, Freq= 0, CH_0, rank 1
5474 22:56:09.189066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5475 22:56:09.189186 ==
5476 22:56:09.189253 RX Vref Scan: 0
5477 22:56:09.189314
5478 22:56:09.192352 RX Vref 0 -> 0, step: 1
5479 22:56:09.192471
5480 22:56:09.196292 RX Delay -80 -> 252, step: 8
5481 22:56:09.198936 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5482 22:56:09.202576 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5483 22:56:09.205880 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5484 22:56:09.208824 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5485 22:56:09.212269 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5486 22:56:09.219020 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5487 22:56:09.222343 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5488 22:56:09.225662 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5489 22:56:09.229223 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5490 22:56:09.232231 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5491 22:56:09.239244 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5492 22:56:09.242253 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5493 22:56:09.245627 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5494 22:56:09.248587 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5495 22:56:09.252332 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5496 22:56:09.255378 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5497 22:56:09.258613 ==
5498 22:56:09.261897 Dram Type= 6, Freq= 0, CH_0, rank 1
5499 22:56:09.265226 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5500 22:56:09.265326 ==
5501 22:56:09.265393 DQS Delay:
5502 22:56:09.268314 DQS0 = 0, DQS1 = 0
5503 22:56:09.268416 DQM Delay:
5504 22:56:09.271925 DQM0 = 97, DQM1 = 90
5505 22:56:09.272033 DQ Delay:
5506 22:56:09.275287 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =91
5507 22:56:09.278297 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =107
5508 22:56:09.281341 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5509 22:56:09.285070 DQ12 =95, DQ13 =95, DQ14 =99, DQ15 =95
5510 22:56:09.285180
5511 22:56:09.285247
5512 22:56:09.285307 ==
5513 22:56:09.288104 Dram Type= 6, Freq= 0, CH_0, rank 1
5514 22:56:09.291329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5515 22:56:09.291411 ==
5516 22:56:09.291513
5517 22:56:09.295355
5518 22:56:09.295448 TX Vref Scan disable
5519 22:56:09.298250 == TX Byte 0 ==
5520 22:56:09.301530 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5521 22:56:09.305000 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5522 22:56:09.308070 == TX Byte 1 ==
5523 22:56:09.311337 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5524 22:56:09.314796 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5525 22:56:09.314883 ==
5526 22:56:09.318293 Dram Type= 6, Freq= 0, CH_0, rank 1
5527 22:56:09.324437 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5528 22:56:09.324585 ==
5529 22:56:09.324657
5530 22:56:09.324717
5531 22:56:09.324776 TX Vref Scan disable
5532 22:56:09.328720 == TX Byte 0 ==
5533 22:56:09.332378 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5534 22:56:09.338461 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5535 22:56:09.338568 == TX Byte 1 ==
5536 22:56:09.341998 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5537 22:56:09.348851 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5538 22:56:09.348976
5539 22:56:09.349058 [DATLAT]
5540 22:56:09.349122 Freq=933, CH0 RK1
5541 22:56:09.349184
5542 22:56:09.352121 DATLAT Default: 0xb
5543 22:56:09.352239 0, 0xFFFF, sum = 0
5544 22:56:09.355129 1, 0xFFFF, sum = 0
5545 22:56:09.358319 2, 0xFFFF, sum = 0
5546 22:56:09.358406 3, 0xFFFF, sum = 0
5547 22:56:09.362275 4, 0xFFFF, sum = 0
5548 22:56:09.362366 5, 0xFFFF, sum = 0
5549 22:56:09.365272 6, 0xFFFF, sum = 0
5550 22:56:09.365346 7, 0xFFFF, sum = 0
5551 22:56:09.368408 8, 0xFFFF, sum = 0
5552 22:56:09.368480 9, 0xFFFF, sum = 0
5553 22:56:09.371825 10, 0x0, sum = 1
5554 22:56:09.371910 11, 0x0, sum = 2
5555 22:56:09.375038 12, 0x0, sum = 3
5556 22:56:09.375163 13, 0x0, sum = 4
5557 22:56:09.378159 best_step = 11
5558 22:56:09.378250
5559 22:56:09.378320 ==
5560 22:56:09.381401 Dram Type= 6, Freq= 0, CH_0, rank 1
5561 22:56:09.384591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5562 22:56:09.384724 ==
5563 22:56:09.384829 RX Vref Scan: 0
5564 22:56:09.384905
5565 22:56:09.388336 RX Vref 0 -> 0, step: 1
5566 22:56:09.388439
5567 22:56:09.391279 RX Delay -61 -> 252, step: 4
5568 22:56:09.398029 iDelay=203, Bit 0, Center 92 (-1 ~ 186) 188
5569 22:56:09.401542 iDelay=203, Bit 1, Center 98 (3 ~ 194) 192
5570 22:56:09.404782 iDelay=203, Bit 2, Center 88 (-5 ~ 182) 188
5571 22:56:09.407664 iDelay=203, Bit 3, Center 92 (-5 ~ 190) 196
5572 22:56:09.411257 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5573 22:56:09.414617 iDelay=203, Bit 5, Center 86 (-9 ~ 182) 192
5574 22:56:09.421050 iDelay=203, Bit 6, Center 104 (7 ~ 202) 196
5575 22:56:09.424429 iDelay=203, Bit 7, Center 104 (11 ~ 198) 188
5576 22:56:09.427855 iDelay=203, Bit 8, Center 82 (-9 ~ 174) 184
5577 22:56:09.430940 iDelay=203, Bit 9, Center 76 (-13 ~ 166) 180
5578 22:56:09.434164 iDelay=203, Bit 10, Center 90 (-5 ~ 186) 192
5579 22:56:09.440982 iDelay=203, Bit 11, Center 82 (-9 ~ 174) 184
5580 22:56:09.444164 iDelay=203, Bit 12, Center 92 (-1 ~ 186) 188
5581 22:56:09.447231 iDelay=203, Bit 13, Center 92 (-1 ~ 186) 188
5582 22:56:09.450830 iDelay=203, Bit 14, Center 94 (-1 ~ 190) 192
5583 22:56:09.454397 iDelay=203, Bit 15, Center 92 (-1 ~ 186) 188
5584 22:56:09.457689 ==
5585 22:56:09.457785 Dram Type= 6, Freq= 0, CH_0, rank 1
5586 22:56:09.463892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5587 22:56:09.464038 ==
5588 22:56:09.464170 DQS Delay:
5589 22:56:09.467237 DQS0 = 0, DQS1 = 0
5590 22:56:09.467361 DQM Delay:
5591 22:56:09.470658 DQM0 = 95, DQM1 = 87
5592 22:56:09.470804 DQ Delay:
5593 22:56:09.473977 DQ0 =92, DQ1 =98, DQ2 =88, DQ3 =92
5594 22:56:09.477434 DQ4 =96, DQ5 =86, DQ6 =104, DQ7 =104
5595 22:56:09.480505 DQ8 =82, DQ9 =76, DQ10 =90, DQ11 =82
5596 22:56:09.483707 DQ12 =92, DQ13 =92, DQ14 =94, DQ15 =92
5597 22:56:09.483861
5598 22:56:09.483960
5599 22:56:09.490133 [DQSOSCAuto] RK1, (LSB)MR18= 0x2afa, (MSB)MR19= 0x504, tDQSOscB0 = 424 ps tDQSOscB1 = 408 ps
5600 22:56:09.493478 CH0 RK1: MR19=504, MR18=2AFA
5601 22:56:09.500119 CH0_RK1: MR19=0x504, MR18=0x2AFA, DQSOSC=408, MR23=63, INC=65, DEC=43
5602 22:56:09.503390 [RxdqsGatingPostProcess] freq 933
5603 22:56:09.510024 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5604 22:56:09.513382 best DQS0 dly(2T, 0.5T) = (0, 10)
5605 22:56:09.516403 best DQS1 dly(2T, 0.5T) = (0, 11)
5606 22:56:09.519921 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5607 22:56:09.523072 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5608 22:56:09.523201 best DQS0 dly(2T, 0.5T) = (0, 10)
5609 22:56:09.526388 best DQS1 dly(2T, 0.5T) = (0, 10)
5610 22:56:09.529544 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5611 22:56:09.533001 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5612 22:56:09.536303 Pre-setting of DQS Precalculation
5613 22:56:09.543016 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5614 22:56:09.543164 ==
5615 22:56:09.546401 Dram Type= 6, Freq= 0, CH_1, rank 0
5616 22:56:09.549625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5617 22:56:09.549747 ==
5618 22:56:09.556209 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5619 22:56:09.562451 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5620 22:56:09.565916 [CA 0] Center 36 (6~67) winsize 62
5621 22:56:09.569043 [CA 1] Center 36 (6~67) winsize 62
5622 22:56:09.572673 [CA 2] Center 34 (4~64) winsize 61
5623 22:56:09.575380 [CA 3] Center 33 (3~64) winsize 62
5624 22:56:09.578724 [CA 4] Center 34 (4~64) winsize 61
5625 22:56:09.582558 [CA 5] Center 33 (3~64) winsize 62
5626 22:56:09.582663
5627 22:56:09.585544 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5628 22:56:09.585643
5629 22:56:09.588809 [CATrainingPosCal] consider 1 rank data
5630 22:56:09.591990 u2DelayCellTimex100 = 270/100 ps
5631 22:56:09.595423 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5632 22:56:09.598643 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5633 22:56:09.601947 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5634 22:56:09.605576 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5635 22:56:09.608899 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5636 22:56:09.611901 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5637 22:56:09.612005
5638 22:56:09.618477 CA PerBit enable=1, Macro0, CA PI delay=33
5639 22:56:09.618595
5640 22:56:09.621952 [CBTSetCACLKResult] CA Dly = 33
5641 22:56:09.622049 CS Dly: 5 (0~36)
5642 22:56:09.622117 ==
5643 22:56:09.625088 Dram Type= 6, Freq= 0, CH_1, rank 1
5644 22:56:09.628565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5645 22:56:09.628659 ==
5646 22:56:09.635211 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5647 22:56:09.641528 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5648 22:56:09.645195 [CA 0] Center 36 (6~67) winsize 62
5649 22:56:09.648198 [CA 1] Center 36 (6~67) winsize 62
5650 22:56:09.651438 [CA 2] Center 34 (4~65) winsize 62
5651 22:56:09.654791 [CA 3] Center 33 (3~64) winsize 62
5652 22:56:09.658201 [CA 4] Center 34 (3~65) winsize 63
5653 22:56:09.661167 [CA 5] Center 33 (3~64) winsize 62
5654 22:56:09.661265
5655 22:56:09.664410 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5656 22:56:09.664494
5657 22:56:09.667994 [CATrainingPosCal] consider 2 rank data
5658 22:56:09.671217 u2DelayCellTimex100 = 270/100 ps
5659 22:56:09.674954 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5660 22:56:09.677948 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5661 22:56:09.681690 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5662 22:56:09.684593 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5663 22:56:09.691197 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5664 22:56:09.694436 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5665 22:56:09.694547
5666 22:56:09.697613 CA PerBit enable=1, Macro0, CA PI delay=33
5667 22:56:09.697694
5668 22:56:09.700858 [CBTSetCACLKResult] CA Dly = 33
5669 22:56:09.700963 CS Dly: 6 (0~39)
5670 22:56:09.701054
5671 22:56:09.704867 ----->DramcWriteLeveling(PI) begin...
5672 22:56:09.704947 ==
5673 22:56:09.707454 Dram Type= 6, Freq= 0, CH_1, rank 0
5674 22:56:09.714299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5675 22:56:09.714391 ==
5676 22:56:09.717939 Write leveling (Byte 0): 26 => 26
5677 22:56:09.720685 Write leveling (Byte 1): 28 => 28
5678 22:56:09.720776 DramcWriteLeveling(PI) end<-----
5679 22:56:09.720849
5680 22:56:09.724004 ==
5681 22:56:09.727334 Dram Type= 6, Freq= 0, CH_1, rank 0
5682 22:56:09.730853 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5683 22:56:09.730965 ==
5684 22:56:09.734433 [Gating] SW mode calibration
5685 22:56:09.740799 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5686 22:56:09.744328 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5687 22:56:09.750614 0 14 0 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
5688 22:56:09.754200 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5689 22:56:09.757479 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5690 22:56:09.763847 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5691 22:56:09.767199 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5692 22:56:09.770908 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5693 22:56:09.777193 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
5694 22:56:09.780662 0 14 28 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
5695 22:56:09.783491 0 15 0 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
5696 22:56:09.790488 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5697 22:56:09.793595 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5698 22:56:09.797081 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5699 22:56:09.803415 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5700 22:56:09.806645 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5701 22:56:09.810131 0 15 24 | B1->B0 | 2323 2625 | 0 1 | (0 0) (0 0)
5702 22:56:09.816524 0 15 28 | B1->B0 | 3636 3939 | 1 0 | (1 1) (0 0)
5703 22:56:09.819962 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5704 22:56:09.823452 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5705 22:56:09.829949 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5706 22:56:09.833151 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5707 22:56:09.836321 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5708 22:56:09.843067 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5709 22:56:09.846627 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5710 22:56:09.849835 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5711 22:56:09.856066 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5712 22:56:09.859405 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5713 22:56:09.862785 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5714 22:56:09.869447 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5715 22:56:09.872593 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5716 22:56:09.876344 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5717 22:56:09.882488 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5718 22:56:09.886187 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5719 22:56:09.889231 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5720 22:56:09.895868 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5721 22:56:09.899167 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5722 22:56:09.902451 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5723 22:56:09.909063 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5724 22:56:09.912613 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5725 22:56:09.915863 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5726 22:56:09.919101 Total UI for P1: 0, mck2ui 16
5727 22:56:09.922376 best dqsien dly found for B0: ( 1, 2, 22)
5728 22:56:09.928791 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5729 22:56:09.931851 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5730 22:56:09.935452 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5731 22:56:09.938649 Total UI for P1: 0, mck2ui 16
5732 22:56:09.942389 best dqsien dly found for B1: ( 1, 2, 28)
5733 22:56:09.945841 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5734 22:56:09.948653 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5735 22:56:09.948761
5736 22:56:09.955528 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5737 22:56:09.958812 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5738 22:56:09.961485 [Gating] SW calibration Done
5739 22:56:09.961563 ==
5740 22:56:09.965002 Dram Type= 6, Freq= 0, CH_1, rank 0
5741 22:56:09.968353 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5742 22:56:09.968459 ==
5743 22:56:09.968563 RX Vref Scan: 0
5744 22:56:09.968626
5745 22:56:09.971593 RX Vref 0 -> 0, step: 1
5746 22:56:09.971728
5747 22:56:09.975057 RX Delay -80 -> 252, step: 8
5748 22:56:09.978650 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5749 22:56:09.981666 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5750 22:56:09.988404 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5751 22:56:09.991714 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5752 22:56:09.994588 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5753 22:56:09.998014 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5754 22:56:10.001589 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5755 22:56:10.004390 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5756 22:56:10.011486 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5757 22:56:10.014535 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5758 22:56:10.017837 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5759 22:56:10.021150 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5760 22:56:10.024380 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5761 22:56:10.027534 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5762 22:56:10.034166 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5763 22:56:10.037623 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5764 22:56:10.037732 ==
5765 22:56:10.041233 Dram Type= 6, Freq= 0, CH_1, rank 0
5766 22:56:10.044263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5767 22:56:10.044359 ==
5768 22:56:10.047496 DQS Delay:
5769 22:56:10.047581 DQS0 = 0, DQS1 = 0
5770 22:56:10.047646 DQM Delay:
5771 22:56:10.050745 DQM0 = 100, DQM1 = 92
5772 22:56:10.050832 DQ Delay:
5773 22:56:10.054222 DQ0 =103, DQ1 =99, DQ2 =95, DQ3 =99
5774 22:56:10.057390 DQ4 =95, DQ5 =107, DQ6 =107, DQ7 =99
5775 22:56:10.060911 DQ8 =79, DQ9 =83, DQ10 =91, DQ11 =83
5776 22:56:10.064231 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =103
5777 22:56:10.064347
5778 22:56:10.064451
5779 22:56:10.067549 ==
5780 22:56:10.067682 Dram Type= 6, Freq= 0, CH_1, rank 0
5781 22:56:10.073890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5782 22:56:10.073987 ==
5783 22:56:10.074053
5784 22:56:10.074112
5785 22:56:10.077450 TX Vref Scan disable
5786 22:56:10.077565 == TX Byte 0 ==
5787 22:56:10.081128 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5788 22:56:10.087666 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5789 22:56:10.087820 == TX Byte 1 ==
5790 22:56:10.090549 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5791 22:56:10.097076 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5792 22:56:10.097217 ==
5793 22:56:10.100381 Dram Type= 6, Freq= 0, CH_1, rank 0
5794 22:56:10.103716 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5795 22:56:10.103874 ==
5796 22:56:10.103966
5797 22:56:10.104061
5798 22:56:10.107133 TX Vref Scan disable
5799 22:56:10.110400 == TX Byte 0 ==
5800 22:56:10.113553 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5801 22:56:10.116768 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5802 22:56:10.120004 == TX Byte 1 ==
5803 22:56:10.123757 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5804 22:56:10.126467 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5805 22:56:10.126586
5806 22:56:10.130002 [DATLAT]
5807 22:56:10.130108 Freq=933, CH1 RK0
5808 22:56:10.130207
5809 22:56:10.133256 DATLAT Default: 0xd
5810 22:56:10.133386 0, 0xFFFF, sum = 0
5811 22:56:10.136671 1, 0xFFFF, sum = 0
5812 22:56:10.136786 2, 0xFFFF, sum = 0
5813 22:56:10.140008 3, 0xFFFF, sum = 0
5814 22:56:10.140113 4, 0xFFFF, sum = 0
5815 22:56:10.143151 5, 0xFFFF, sum = 0
5816 22:56:10.143265 6, 0xFFFF, sum = 0
5817 22:56:10.146484 7, 0xFFFF, sum = 0
5818 22:56:10.146604 8, 0xFFFF, sum = 0
5819 22:56:10.149645 9, 0xFFFF, sum = 0
5820 22:56:10.149753 10, 0x0, sum = 1
5821 22:56:10.153157 11, 0x0, sum = 2
5822 22:56:10.153277 12, 0x0, sum = 3
5823 22:56:10.156278 13, 0x0, sum = 4
5824 22:56:10.156387 best_step = 11
5825 22:56:10.156481
5826 22:56:10.156606 ==
5827 22:56:10.159640 Dram Type= 6, Freq= 0, CH_1, rank 0
5828 22:56:10.166556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5829 22:56:10.166671 ==
5830 22:56:10.166740 RX Vref Scan: 1
5831 22:56:10.166801
5832 22:56:10.169367 RX Vref 0 -> 0, step: 1
5833 22:56:10.169446
5834 22:56:10.172583 RX Delay -61 -> 252, step: 4
5835 22:56:10.172691
5836 22:56:10.176324 Set Vref, RX VrefLevel [Byte0]: 52
5837 22:56:10.179165 [Byte1]: 53
5838 22:56:10.179296
5839 22:56:10.182472 Final RX Vref Byte 0 = 52 to rank0
5840 22:56:10.186359 Final RX Vref Byte 1 = 53 to rank0
5841 22:56:10.189625 Final RX Vref Byte 0 = 52 to rank1
5842 22:56:10.192761 Final RX Vref Byte 1 = 53 to rank1==
5843 22:56:10.195911 Dram Type= 6, Freq= 0, CH_1, rank 0
5844 22:56:10.199331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5845 22:56:10.199435 ==
5846 22:56:10.202736 DQS Delay:
5847 22:56:10.202825 DQS0 = 0, DQS1 = 0
5848 22:56:10.205748 DQM Delay:
5849 22:56:10.205827 DQM0 = 100, DQM1 = 93
5850 22:56:10.205901 DQ Delay:
5851 22:56:10.209247 DQ0 =104, DQ1 =96, DQ2 =92, DQ3 =96
5852 22:56:10.212474 DQ4 =100, DQ5 =110, DQ6 =112, DQ7 =96
5853 22:56:10.215487 DQ8 =80, DQ9 =84, DQ10 =94, DQ11 =86
5854 22:56:10.222812 DQ12 =102, DQ13 =98, DQ14 =104, DQ15 =102
5855 22:56:10.222935
5856 22:56:10.223007
5857 22:56:10.229196 [DQSOSCAuto] RK0, (LSB)MR18= 0x1909, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 413 ps
5858 22:56:10.232568 CH1 RK0: MR19=505, MR18=1909
5859 22:56:10.238593 CH1_RK0: MR19=0x505, MR18=0x1909, DQSOSC=413, MR23=63, INC=63, DEC=42
5860 22:56:10.238709
5861 22:56:10.242067 ----->DramcWriteLeveling(PI) begin...
5862 22:56:10.242153 ==
5863 22:56:10.245350 Dram Type= 6, Freq= 0, CH_1, rank 1
5864 22:56:10.248606 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5865 22:56:10.248707 ==
5866 22:56:10.252040 Write leveling (Byte 0): 27 => 27
5867 22:56:10.255389 Write leveling (Byte 1): 27 => 27
5868 22:56:10.258300 DramcWriteLeveling(PI) end<-----
5869 22:56:10.258416
5870 22:56:10.258515 ==
5871 22:56:10.261718 Dram Type= 6, Freq= 0, CH_1, rank 1
5872 22:56:10.264800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5873 22:56:10.264881 ==
5874 22:56:10.268426 [Gating] SW mode calibration
5875 22:56:10.275064 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5876 22:56:10.282078 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5877 22:56:10.285404 0 14 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5878 22:56:10.291395 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5879 22:56:10.294932 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5880 22:56:10.298632 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5881 22:56:10.305089 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5882 22:56:10.308230 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5883 22:56:10.311566 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5884 22:56:10.317927 0 14 28 | B1->B0 | 2b2b 2e2e | 0 0 | (0 0) (1 0)
5885 22:56:10.321288 0 15 0 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (1 1)
5886 22:56:10.324352 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5887 22:56:10.331323 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5888 22:56:10.334479 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5889 22:56:10.338015 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5890 22:56:10.344352 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5891 22:56:10.347802 0 15 24 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
5892 22:56:10.351410 0 15 28 | B1->B0 | 4444 3838 | 0 0 | (0 0) (0 0)
5893 22:56:10.357958 1 0 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
5894 22:56:10.360884 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5895 22:56:10.364202 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5896 22:56:10.370894 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5897 22:56:10.374303 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5898 22:56:10.377634 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5899 22:56:10.384164 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5900 22:56:10.387396 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5901 22:56:10.391362 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5902 22:56:10.397128 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5903 22:56:10.400495 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5904 22:56:10.403888 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5905 22:56:10.410500 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5906 22:56:10.414229 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5907 22:56:10.417063 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5908 22:56:10.423555 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5909 22:56:10.427364 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5910 22:56:10.430591 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5911 22:56:10.433525 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5912 22:56:10.440109 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5913 22:56:10.443495 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5914 22:56:10.447020 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5915 22:56:10.453832 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5916 22:56:10.456745 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5917 22:56:10.460390 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5918 22:56:10.463299 Total UI for P1: 0, mck2ui 16
5919 22:56:10.466844 best dqsien dly found for B0: ( 1, 2, 26)
5920 22:56:10.470232 Total UI for P1: 0, mck2ui 16
5921 22:56:10.473322 best dqsien dly found for B1: ( 1, 2, 26)
5922 22:56:10.476452 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5923 22:56:10.483196 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5924 22:56:10.483370
5925 22:56:10.486724 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5926 22:56:10.489924 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5927 22:56:10.493216 [Gating] SW calibration Done
5928 22:56:10.493345 ==
5929 22:56:10.496413 Dram Type= 6, Freq= 0, CH_1, rank 1
5930 22:56:10.499717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5931 22:56:10.499834 ==
5932 22:56:10.503342 RX Vref Scan: 0
5933 22:56:10.503457
5934 22:56:10.503551 RX Vref 0 -> 0, step: 1
5935 22:56:10.503638
5936 22:56:10.506453 RX Delay -80 -> 252, step: 8
5937 22:56:10.510217 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5938 22:56:10.515940 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5939 22:56:10.519413 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5940 22:56:10.522756 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5941 22:56:10.525942 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5942 22:56:10.529740 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5943 22:56:10.532706 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5944 22:56:10.539655 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5945 22:56:10.542608 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5946 22:56:10.545868 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5947 22:56:10.549109 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5948 22:56:10.552493 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5949 22:56:10.559244 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5950 22:56:10.562565 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5951 22:56:10.565623 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5952 22:56:10.568904 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5953 22:56:10.569038 ==
5954 22:56:10.572225 Dram Type= 6, Freq= 0, CH_1, rank 1
5955 22:56:10.575487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5956 22:56:10.575610 ==
5957 22:56:10.578887 DQS Delay:
5958 22:56:10.578982 DQS0 = 0, DQS1 = 0
5959 22:56:10.582047 DQM Delay:
5960 22:56:10.582177 DQM0 = 100, DQM1 = 91
5961 22:56:10.585338 DQ Delay:
5962 22:56:10.585434 DQ0 =103, DQ1 =95, DQ2 =87, DQ3 =99
5963 22:56:10.589221 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =95
5964 22:56:10.592226 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5965 22:56:10.598580 DQ12 =99, DQ13 =99, DQ14 =95, DQ15 =103
5966 22:56:10.598726
5967 22:56:10.598850
5968 22:56:10.598943 ==
5969 22:56:10.602413 Dram Type= 6, Freq= 0, CH_1, rank 1
5970 22:56:10.605553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5971 22:56:10.605671 ==
5972 22:56:10.605768
5973 22:56:10.605860
5974 22:56:10.608895 TX Vref Scan disable
5975 22:56:10.609020 == TX Byte 0 ==
5976 22:56:10.615311 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5977 22:56:10.618552 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5978 22:56:10.618664 == TX Byte 1 ==
5979 22:56:10.625416 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5980 22:56:10.628316 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5981 22:56:10.628442 ==
5982 22:56:10.632035 Dram Type= 6, Freq= 0, CH_1, rank 1
5983 22:56:10.635279 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5984 22:56:10.635414 ==
5985 22:56:10.635518
5986 22:56:10.638213
5987 22:56:10.638324 TX Vref Scan disable
5988 22:56:10.641820 == TX Byte 0 ==
5989 22:56:10.645349 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5990 22:56:10.648624 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5991 22:56:10.651629 == TX Byte 1 ==
5992 22:56:10.654968 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5993 22:56:10.658298 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5994 22:56:10.658412
5995 22:56:10.661928 [DATLAT]
5996 22:56:10.662025 Freq=933, CH1 RK1
5997 22:56:10.662092
5998 22:56:10.665455 DATLAT Default: 0xb
5999 22:56:10.665534 0, 0xFFFF, sum = 0
6000 22:56:10.668470 1, 0xFFFF, sum = 0
6001 22:56:10.668580 2, 0xFFFF, sum = 0
6002 22:56:10.672072 3, 0xFFFF, sum = 0
6003 22:56:10.672186 4, 0xFFFF, sum = 0
6004 22:56:10.675288 5, 0xFFFF, sum = 0
6005 22:56:10.675393 6, 0xFFFF, sum = 0
6006 22:56:10.678653 7, 0xFFFF, sum = 0
6007 22:56:10.681704 8, 0xFFFF, sum = 0
6008 22:56:10.681823 9, 0xFFFF, sum = 0
6009 22:56:10.684938 10, 0x0, sum = 1
6010 22:56:10.685039 11, 0x0, sum = 2
6011 22:56:10.685153 12, 0x0, sum = 3
6012 22:56:10.688314 13, 0x0, sum = 4
6013 22:56:10.688438 best_step = 11
6014 22:56:10.688561
6015 22:56:10.688670 ==
6016 22:56:10.691271 Dram Type= 6, Freq= 0, CH_1, rank 1
6017 22:56:10.698357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
6018 22:56:10.698503 ==
6019 22:56:10.698605 RX Vref Scan: 0
6020 22:56:10.698696
6021 22:56:10.701278 RX Vref 0 -> 0, step: 1
6022 22:56:10.701388
6023 22:56:10.704505 RX Delay -61 -> 252, step: 4
6024 22:56:10.707880 iDelay=207, Bit 0, Center 104 (15 ~ 194) 180
6025 22:56:10.714627 iDelay=207, Bit 1, Center 96 (7 ~ 186) 180
6026 22:56:10.717891 iDelay=207, Bit 2, Center 90 (3 ~ 178) 176
6027 22:56:10.721507 iDelay=207, Bit 3, Center 98 (11 ~ 186) 176
6028 22:56:10.724472 iDelay=207, Bit 4, Center 102 (11 ~ 194) 184
6029 22:56:10.727961 iDelay=207, Bit 5, Center 110 (19 ~ 202) 184
6030 22:56:10.734488 iDelay=207, Bit 6, Center 114 (23 ~ 206) 184
6031 22:56:10.737681 iDelay=207, Bit 7, Center 98 (7 ~ 190) 184
6032 22:56:10.740682 iDelay=207, Bit 8, Center 82 (-5 ~ 170) 176
6033 22:56:10.744351 iDelay=207, Bit 9, Center 84 (-5 ~ 174) 180
6034 22:56:10.747248 iDelay=207, Bit 10, Center 94 (3 ~ 186) 184
6035 22:56:10.750602 iDelay=207, Bit 11, Center 84 (-5 ~ 174) 180
6036 22:56:10.757141 iDelay=207, Bit 12, Center 102 (11 ~ 194) 184
6037 22:56:10.761033 iDelay=207, Bit 13, Center 100 (7 ~ 194) 188
6038 22:56:10.764032 iDelay=207, Bit 14, Center 98 (7 ~ 190) 184
6039 22:56:10.767200 iDelay=207, Bit 15, Center 100 (7 ~ 194) 188
6040 22:56:10.767340 ==
6041 22:56:10.770725 Dram Type= 6, Freq= 0, CH_1, rank 1
6042 22:56:10.777177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
6043 22:56:10.777303 ==
6044 22:56:10.777377 DQS Delay:
6045 22:56:10.777439 DQS0 = 0, DQS1 = 0
6046 22:56:10.780904 DQM Delay:
6047 22:56:10.781022 DQM0 = 101, DQM1 = 93
6048 22:56:10.783797 DQ Delay:
6049 22:56:10.787165 DQ0 =104, DQ1 =96, DQ2 =90, DQ3 =98
6050 22:56:10.790718 DQ4 =102, DQ5 =110, DQ6 =114, DQ7 =98
6051 22:56:10.793911 DQ8 =82, DQ9 =84, DQ10 =94, DQ11 =84
6052 22:56:10.797054 DQ12 =102, DQ13 =100, DQ14 =98, DQ15 =100
6053 22:56:10.797181
6054 22:56:10.797289
6055 22:56:10.803880 [DQSOSCAuto] RK1, (LSB)MR18= 0xd06, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 417 ps
6056 22:56:10.807494 CH1 RK1: MR19=505, MR18=D06
6057 22:56:10.813694 CH1_RK1: MR19=0x505, MR18=0xD06, DQSOSC=417, MR23=63, INC=62, DEC=41
6058 22:56:10.816909 [RxdqsGatingPostProcess] freq 933
6059 22:56:10.820527 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6060 22:56:10.824125 best DQS0 dly(2T, 0.5T) = (0, 10)
6061 22:56:10.826985 best DQS1 dly(2T, 0.5T) = (0, 10)
6062 22:56:10.830330 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6063 22:56:10.833785 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6064 22:56:10.836934 best DQS0 dly(2T, 0.5T) = (0, 10)
6065 22:56:10.840025 best DQS1 dly(2T, 0.5T) = (0, 10)
6066 22:56:10.843569 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6067 22:56:10.846904 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6068 22:56:10.849829 Pre-setting of DQS Precalculation
6069 22:56:10.853734 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6070 22:56:10.863160 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6071 22:56:10.870279 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6072 22:56:10.870440
6073 22:56:10.870546
6074 22:56:10.873045 [Calibration Summary] 1866 Mbps
6075 22:56:10.873160 CH 0, Rank 0
6076 22:56:10.876159 SW Impedance : PASS
6077 22:56:10.880291 DUTY Scan : NO K
6078 22:56:10.880414 ZQ Calibration : PASS
6079 22:56:10.883020 Jitter Meter : NO K
6080 22:56:10.883144 CBT Training : PASS
6081 22:56:10.886167 Write leveling : PASS
6082 22:56:10.889648 RX DQS gating : PASS
6083 22:56:10.889789 RX DQ/DQS(RDDQC) : PASS
6084 22:56:10.892877 TX DQ/DQS : PASS
6085 22:56:10.896540 RX DATLAT : PASS
6086 22:56:10.896666 RX DQ/DQS(Engine): PASS
6087 22:56:10.899387 TX OE : NO K
6088 22:56:10.899505 All Pass.
6089 22:56:10.899596
6090 22:56:10.902771 CH 0, Rank 1
6091 22:56:10.902888 SW Impedance : PASS
6092 22:56:10.906370 DUTY Scan : NO K
6093 22:56:10.909618 ZQ Calibration : PASS
6094 22:56:10.909744 Jitter Meter : NO K
6095 22:56:10.912639 CBT Training : PASS
6096 22:56:10.915984 Write leveling : PASS
6097 22:56:10.916101 RX DQS gating : PASS
6098 22:56:10.919380 RX DQ/DQS(RDDQC) : PASS
6099 22:56:10.922613 TX DQ/DQS : PASS
6100 22:56:10.922739 RX DATLAT : PASS
6101 22:56:10.926136 RX DQ/DQS(Engine): PASS
6102 22:56:10.929320 TX OE : NO K
6103 22:56:10.929453 All Pass.
6104 22:56:10.929554
6105 22:56:10.929645 CH 1, Rank 0
6106 22:56:10.932442 SW Impedance : PASS
6107 22:56:10.936014 DUTY Scan : NO K
6108 22:56:10.936150 ZQ Calibration : PASS
6109 22:56:10.938949 Jitter Meter : NO K
6110 22:56:10.942817 CBT Training : PASS
6111 22:56:10.942954 Write leveling : PASS
6112 22:56:10.945657 RX DQS gating : PASS
6113 22:56:10.948786 RX DQ/DQS(RDDQC) : PASS
6114 22:56:10.948906 TX DQ/DQS : PASS
6115 22:56:10.952619 RX DATLAT : PASS
6116 22:56:10.952744 RX DQ/DQS(Engine): PASS
6117 22:56:10.955681 TX OE : NO K
6118 22:56:10.955792 All Pass.
6119 22:56:10.955884
6120 22:56:10.958687 CH 1, Rank 1
6121 22:56:10.958802 SW Impedance : PASS
6122 22:56:10.962474 DUTY Scan : NO K
6123 22:56:10.965925 ZQ Calibration : PASS
6124 22:56:10.966044 Jitter Meter : NO K
6125 22:56:10.969277 CBT Training : PASS
6126 22:56:10.972289 Write leveling : PASS
6127 22:56:10.972414 RX DQS gating : PASS
6128 22:56:10.975572 RX DQ/DQS(RDDQC) : PASS
6129 22:56:10.978593 TX DQ/DQS : PASS
6130 22:56:10.978707 RX DATLAT : PASS
6131 22:56:10.982249 RX DQ/DQS(Engine): PASS
6132 22:56:10.985567 TX OE : NO K
6133 22:56:10.985684 All Pass.
6134 22:56:10.985780
6135 22:56:10.985876 DramC Write-DBI off
6136 22:56:10.988928 PER_BANK_REFRESH: Hybrid Mode
6137 22:56:10.992290 TX_TRACKING: ON
6138 22:56:10.998896 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6139 22:56:11.005316 [FAST_K] Save calibration result to emmc
6140 22:56:11.008271 dramc_set_vcore_voltage set vcore to 650000
6141 22:56:11.008397 Read voltage for 400, 6
6142 22:56:11.011732 Vio18 = 0
6143 22:56:11.011818 Vcore = 650000
6144 22:56:11.011882 Vdram = 0
6145 22:56:11.015591 Vddq = 0
6146 22:56:11.015698 Vmddr = 0
6147 22:56:11.018168 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6148 22:56:11.024823 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6149 22:56:11.027991 MEM_TYPE=3, freq_sel=20
6150 22:56:11.031528 sv_algorithm_assistance_LP4_800
6151 22:56:11.035077 ============ PULL DRAM RESETB DOWN ============
6152 22:56:11.038034 ========== PULL DRAM RESETB DOWN end =========
6153 22:56:11.044706 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6154 22:56:11.048288 ===================================
6155 22:56:11.048416 LPDDR4 DRAM CONFIGURATION
6156 22:56:11.051083 ===================================
6157 22:56:11.054879 EX_ROW_EN[0] = 0x0
6158 22:56:11.054999 EX_ROW_EN[1] = 0x0
6159 22:56:11.057700 LP4Y_EN = 0x0
6160 22:56:11.061055 WORK_FSP = 0x0
6161 22:56:11.061136 WL = 0x2
6162 22:56:11.064769 RL = 0x2
6163 22:56:11.064878 BL = 0x2
6164 22:56:11.068028 RPST = 0x0
6165 22:56:11.068135 RD_PRE = 0x0
6166 22:56:11.071785 WR_PRE = 0x1
6167 22:56:11.071895 WR_PST = 0x0
6168 22:56:11.074297 DBI_WR = 0x0
6169 22:56:11.074418 DBI_RD = 0x0
6170 22:56:11.077473 OTF = 0x1
6171 22:56:11.081531 ===================================
6172 22:56:11.084715 ===================================
6173 22:56:11.084844 ANA top config
6174 22:56:11.087941 ===================================
6175 22:56:11.090937 DLL_ASYNC_EN = 0
6176 22:56:11.094054 ALL_SLAVE_EN = 1
6177 22:56:11.094176 NEW_RANK_MODE = 1
6178 22:56:11.097400 DLL_IDLE_MODE = 1
6179 22:56:11.100909 LP45_APHY_COMB_EN = 1
6180 22:56:11.104393 TX_ODT_DIS = 1
6181 22:56:11.108191 NEW_8X_MODE = 1
6182 22:56:11.110626 ===================================
6183 22:56:11.114031 ===================================
6184 22:56:11.114128 data_rate = 800
6185 22:56:11.117655 CKR = 1
6186 22:56:11.121169 DQ_P2S_RATIO = 4
6187 22:56:11.124336 ===================================
6188 22:56:11.127068 CA_P2S_RATIO = 4
6189 22:56:11.130552 DQ_CA_OPEN = 0
6190 22:56:11.134040 DQ_SEMI_OPEN = 1
6191 22:56:11.134126 CA_SEMI_OPEN = 1
6192 22:56:11.137377 CA_FULL_RATE = 0
6193 22:56:11.140503 DQ_CKDIV4_EN = 0
6194 22:56:11.143740 CA_CKDIV4_EN = 1
6195 22:56:11.147128 CA_PREDIV_EN = 0
6196 22:56:11.150531 PH8_DLY = 0
6197 22:56:11.154051 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6198 22:56:11.154135 DQ_AAMCK_DIV = 0
6199 22:56:11.157207 CA_AAMCK_DIV = 0
6200 22:56:11.160453 CA_ADMCK_DIV = 4
6201 22:56:11.163671 DQ_TRACK_CA_EN = 0
6202 22:56:11.166900 CA_PICK = 800
6203 22:56:11.170535 CA_MCKIO = 400
6204 22:56:11.170620 MCKIO_SEMI = 400
6205 22:56:11.173367 PLL_FREQ = 3016
6206 22:56:11.176890 DQ_UI_PI_RATIO = 32
6207 22:56:11.180369 CA_UI_PI_RATIO = 32
6208 22:56:11.183457 ===================================
6209 22:56:11.186913 ===================================
6210 22:56:11.190546 memory_type:LPDDR4
6211 22:56:11.190633 GP_NUM : 10
6212 22:56:11.193501 SRAM_EN : 1
6213 22:56:11.196529 MD32_EN : 0
6214 22:56:11.200342 ===================================
6215 22:56:11.200427 [ANA_INIT] >>>>>>>>>>>>>>
6216 22:56:11.203790 <<<<<< [CONFIGURE PHASE]: ANA_TX
6217 22:56:11.206675 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6218 22:56:11.210301 ===================================
6219 22:56:11.213062 data_rate = 800,PCW = 0X7400
6220 22:56:11.216871 ===================================
6221 22:56:11.220056 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6222 22:56:11.227204 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6223 22:56:11.236479 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6224 22:56:11.243673 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6225 22:56:11.246551 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6226 22:56:11.250079 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6227 22:56:11.250163 [ANA_INIT] flow start
6228 22:56:11.253275 [ANA_INIT] PLL >>>>>>>>
6229 22:56:11.256150 [ANA_INIT] PLL <<<<<<<<
6230 22:56:11.256233 [ANA_INIT] MIDPI >>>>>>>>
6231 22:56:11.259307 [ANA_INIT] MIDPI <<<<<<<<
6232 22:56:11.262634 [ANA_INIT] DLL >>>>>>>>
6233 22:56:11.262717 [ANA_INIT] flow end
6234 22:56:11.269641 ============ LP4 DIFF to SE enter ============
6235 22:56:11.273000 ============ LP4 DIFF to SE exit ============
6236 22:56:11.276230 [ANA_INIT] <<<<<<<<<<<<<
6237 22:56:11.279322 [Flow] Enable top DCM control >>>>>
6238 22:56:11.282650 [Flow] Enable top DCM control <<<<<
6239 22:56:11.282782 Enable DLL master slave shuffle
6240 22:56:11.289357 ==============================================================
6241 22:56:11.292501 Gating Mode config
6242 22:56:11.295885 ==============================================================
6243 22:56:11.299106 Config description:
6244 22:56:11.309326 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6245 22:56:11.316393 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6246 22:56:11.319210 SELPH_MODE 0: By rank 1: By Phase
6247 22:56:11.325686 ==============================================================
6248 22:56:11.329025 GAT_TRACK_EN = 0
6249 22:56:11.332488 RX_GATING_MODE = 2
6250 22:56:11.335880 RX_GATING_TRACK_MODE = 2
6251 22:56:11.338875 SELPH_MODE = 1
6252 22:56:11.342156 PICG_EARLY_EN = 1
6253 22:56:11.342239 VALID_LAT_VALUE = 1
6254 22:56:11.348641 ==============================================================
6255 22:56:11.352201 Enter into Gating configuration >>>>
6256 22:56:11.355514 Exit from Gating configuration <<<<
6257 22:56:11.358660 Enter into DVFS_PRE_config >>>>>
6258 22:56:11.368413 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6259 22:56:11.372026 Exit from DVFS_PRE_config <<<<<
6260 22:56:11.375342 Enter into PICG configuration >>>>
6261 22:56:11.378609 Exit from PICG configuration <<<<
6262 22:56:11.381713 [RX_INPUT] configuration >>>>>
6263 22:56:11.385291 [RX_INPUT] configuration <<<<<
6264 22:56:11.391525 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6265 22:56:11.394942 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6266 22:56:11.401554 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6267 22:56:11.408180 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6268 22:56:11.415105 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6269 22:56:11.421259 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6270 22:56:11.424867 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6271 22:56:11.427938 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6272 22:56:11.431293 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6273 22:56:11.437716 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6274 22:56:11.440990 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6275 22:56:11.444260 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6276 22:56:11.447722 ===================================
6277 22:56:11.450756 LPDDR4 DRAM CONFIGURATION
6278 22:56:11.454127 ===================================
6279 22:56:11.457546 EX_ROW_EN[0] = 0x0
6280 22:56:11.457619 EX_ROW_EN[1] = 0x0
6281 22:56:11.461128 LP4Y_EN = 0x0
6282 22:56:11.461198 WORK_FSP = 0x0
6283 22:56:11.464283 WL = 0x2
6284 22:56:11.464353 RL = 0x2
6285 22:56:11.467149 BL = 0x2
6286 22:56:11.467218 RPST = 0x0
6287 22:56:11.470621 RD_PRE = 0x0
6288 22:56:11.470692 WR_PRE = 0x1
6289 22:56:11.473807 WR_PST = 0x0
6290 22:56:11.473875 DBI_WR = 0x0
6291 22:56:11.477125 DBI_RD = 0x0
6292 22:56:11.480308 OTF = 0x1
6293 22:56:11.483830 ===================================
6294 22:56:11.487476 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6295 22:56:11.490231 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6296 22:56:11.494003 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6297 22:56:11.497284 ===================================
6298 22:56:11.500092 LPDDR4 DRAM CONFIGURATION
6299 22:56:11.503329 ===================================
6300 22:56:11.507165 EX_ROW_EN[0] = 0x10
6301 22:56:11.507264 EX_ROW_EN[1] = 0x0
6302 22:56:11.510302 LP4Y_EN = 0x0
6303 22:56:11.510404 WORK_FSP = 0x0
6304 22:56:11.513828 WL = 0x2
6305 22:56:11.513930 RL = 0x2
6306 22:56:11.516634 BL = 0x2
6307 22:56:11.516731 RPST = 0x0
6308 22:56:11.520041 RD_PRE = 0x0
6309 22:56:11.520114 WR_PRE = 0x1
6310 22:56:11.523301 WR_PST = 0x0
6311 22:56:11.523385 DBI_WR = 0x0
6312 22:56:11.526918 DBI_RD = 0x0
6313 22:56:11.527000 OTF = 0x1
6314 22:56:11.530194 ===================================
6315 22:56:11.536423 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6316 22:56:11.541981 nWR fixed to 30
6317 22:56:11.544892 [ModeRegInit_LP4] CH0 RK0
6318 22:56:11.544974 [ModeRegInit_LP4] CH0 RK1
6319 22:56:11.548462 [ModeRegInit_LP4] CH1 RK0
6320 22:56:11.551606 [ModeRegInit_LP4] CH1 RK1
6321 22:56:11.551688 match AC timing 19
6322 22:56:11.558091 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6323 22:56:11.561358 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6324 22:56:11.564686 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6325 22:56:11.571159 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6326 22:56:11.574595 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6327 22:56:11.574679 ==
6328 22:56:11.578279 Dram Type= 6, Freq= 0, CH_0, rank 0
6329 22:56:11.581535 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6330 22:56:11.581635 ==
6331 22:56:11.587684 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6332 22:56:11.594632 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6333 22:56:11.597767 [CA 0] Center 36 (8~64) winsize 57
6334 22:56:11.601040 [CA 1] Center 36 (8~64) winsize 57
6335 22:56:11.604433 [CA 2] Center 36 (8~64) winsize 57
6336 22:56:11.607545 [CA 3] Center 36 (8~64) winsize 57
6337 22:56:11.610837 [CA 4] Center 36 (8~64) winsize 57
6338 22:56:11.614154 [CA 5] Center 36 (8~64) winsize 57
6339 22:56:11.614236
6340 22:56:11.617438 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6341 22:56:11.617520
6342 22:56:11.620767 [CATrainingPosCal] consider 1 rank data
6343 22:56:11.624305 u2DelayCellTimex100 = 270/100 ps
6344 22:56:11.627880 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6345 22:56:11.630919 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6346 22:56:11.634286 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6347 22:56:11.637281 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6348 22:56:11.641009 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6349 22:56:11.643824 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6350 22:56:11.643936
6351 22:56:11.647278 CA PerBit enable=1, Macro0, CA PI delay=36
6352 22:56:11.647360
6353 22:56:11.650986 [CBTSetCACLKResult] CA Dly = 36
6354 22:56:11.654063 CS Dly: 1 (0~32)
6355 22:56:11.654144 ==
6356 22:56:11.657721 Dram Type= 6, Freq= 0, CH_0, rank 1
6357 22:56:11.661001 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6358 22:56:11.661084 ==
6359 22:56:11.667540 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6360 22:56:11.673665 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6361 22:56:11.676976 [CA 0] Center 36 (8~64) winsize 57
6362 22:56:11.680329 [CA 1] Center 36 (8~64) winsize 57
6363 22:56:11.680408 [CA 2] Center 36 (8~64) winsize 57
6364 22:56:11.683706 [CA 3] Center 36 (8~64) winsize 57
6365 22:56:11.687071 [CA 4] Center 36 (8~64) winsize 57
6366 22:56:11.690461 [CA 5] Center 36 (8~64) winsize 57
6367 22:56:11.690543
6368 22:56:11.693578 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6369 22:56:11.696698
6370 22:56:11.700161 [CATrainingPosCal] consider 2 rank data
6371 22:56:11.700240 u2DelayCellTimex100 = 270/100 ps
6372 22:56:11.706907 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6373 22:56:11.710158 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6374 22:56:11.713353 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6375 22:56:11.716940 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6376 22:56:11.719952 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6377 22:56:11.723099 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6378 22:56:11.723180
6379 22:56:11.726956 CA PerBit enable=1, Macro0, CA PI delay=36
6380 22:56:11.727036
6381 22:56:11.729773 [CBTSetCACLKResult] CA Dly = 36
6382 22:56:11.733100 CS Dly: 1 (0~32)
6383 22:56:11.733186
6384 22:56:11.736806 ----->DramcWriteLeveling(PI) begin...
6385 22:56:11.736912 ==
6386 22:56:11.739542 Dram Type= 6, Freq= 0, CH_0, rank 0
6387 22:56:11.743256 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6388 22:56:11.743336 ==
6389 22:56:11.747122 Write leveling (Byte 0): 40 => 8
6390 22:56:11.749835 Write leveling (Byte 1): 32 => 0
6391 22:56:11.752843 DramcWriteLeveling(PI) end<-----
6392 22:56:11.752923
6393 22:56:11.752984 ==
6394 22:56:11.756901 Dram Type= 6, Freq= 0, CH_0, rank 0
6395 22:56:11.759763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6396 22:56:11.759843 ==
6397 22:56:11.762794 [Gating] SW mode calibration
6398 22:56:11.769805 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6399 22:56:11.776057 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6400 22:56:11.779105 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6401 22:56:11.786318 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6402 22:56:11.789737 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6403 22:56:11.792438 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6404 22:56:11.799314 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6405 22:56:11.802773 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6406 22:56:11.805864 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6407 22:56:11.808813 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6408 22:56:11.815976 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6409 22:56:11.819101 Total UI for P1: 0, mck2ui 16
6410 22:56:11.822236 best dqsien dly found for B0: ( 0, 14, 24)
6411 22:56:11.825954 Total UI for P1: 0, mck2ui 16
6412 22:56:11.829077 best dqsien dly found for B1: ( 0, 14, 24)
6413 22:56:11.832291 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6414 22:56:11.835520 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6415 22:56:11.835614
6416 22:56:11.838692 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6417 22:56:11.842028 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6418 22:56:11.845364 [Gating] SW calibration Done
6419 22:56:11.845445 ==
6420 22:56:11.848816 Dram Type= 6, Freq= 0, CH_0, rank 0
6421 22:56:11.852156 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6422 22:56:11.852240 ==
6423 22:56:11.855290 RX Vref Scan: 0
6424 22:56:11.855386
6425 22:56:11.859016 RX Vref 0 -> 0, step: 1
6426 22:56:11.859098
6427 22:56:11.859165 RX Delay -410 -> 252, step: 16
6428 22:56:11.865355 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6429 22:56:11.868811 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6430 22:56:11.872348 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6431 22:56:11.879275 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6432 22:56:11.882452 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6433 22:56:11.885143 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6434 22:56:11.888934 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6435 22:56:11.895074 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6436 22:56:11.898571 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6437 22:56:11.902139 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6438 22:56:11.905519 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6439 22:56:11.911827 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6440 22:56:11.914787 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6441 22:56:11.918669 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6442 22:56:11.921535 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6443 22:56:11.928352 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6444 22:56:11.928442 ==
6445 22:56:11.931672 Dram Type= 6, Freq= 0, CH_0, rank 0
6446 22:56:11.934999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6447 22:56:11.935089 ==
6448 22:56:11.935173 DQS Delay:
6449 22:56:11.937957 DQS0 = 43, DQS1 = 59
6450 22:56:11.938031 DQM Delay:
6451 22:56:11.941300 DQM0 = 10, DQM1 = 12
6452 22:56:11.941377 DQ Delay:
6453 22:56:11.944504 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6454 22:56:11.948222 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6455 22:56:11.951617 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6456 22:56:11.954989 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6457 22:56:11.955062
6458 22:56:11.955142
6459 22:56:11.955221 ==
6460 22:56:11.958165 Dram Type= 6, Freq= 0, CH_0, rank 0
6461 22:56:11.961438 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6462 22:56:11.961512 ==
6463 22:56:11.961594
6464 22:56:11.964867
6465 22:56:11.964945 TX Vref Scan disable
6466 22:56:11.967774 == TX Byte 0 ==
6467 22:56:11.971772 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6468 22:56:11.974278 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6469 22:56:11.977648 == TX Byte 1 ==
6470 22:56:11.981188 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6471 22:56:11.984308 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6472 22:56:11.984379 ==
6473 22:56:11.987705 Dram Type= 6, Freq= 0, CH_0, rank 0
6474 22:56:11.990875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6475 22:56:11.994317 ==
6476 22:56:11.994408
6477 22:56:11.994477
6478 22:56:11.994538 TX Vref Scan disable
6479 22:56:11.997853 == TX Byte 0 ==
6480 22:56:12.000718 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6481 22:56:12.004089 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6482 22:56:12.007358 == TX Byte 1 ==
6483 22:56:12.010560 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6484 22:56:12.013969 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6485 22:56:12.014053
6486 22:56:12.017824 [DATLAT]
6487 22:56:12.017904 Freq=400, CH0 RK0
6488 22:56:12.017969
6489 22:56:12.020490 DATLAT Default: 0xf
6490 22:56:12.020635 0, 0xFFFF, sum = 0
6491 22:56:12.023878 1, 0xFFFF, sum = 0
6492 22:56:12.023959 2, 0xFFFF, sum = 0
6493 22:56:12.027190 3, 0xFFFF, sum = 0
6494 22:56:12.027273 4, 0xFFFF, sum = 0
6495 22:56:12.030740 5, 0xFFFF, sum = 0
6496 22:56:12.030823 6, 0xFFFF, sum = 0
6497 22:56:12.034012 7, 0xFFFF, sum = 0
6498 22:56:12.034121 8, 0xFFFF, sum = 0
6499 22:56:12.037179 9, 0xFFFF, sum = 0
6500 22:56:12.040856 10, 0xFFFF, sum = 0
6501 22:56:12.040939 11, 0xFFFF, sum = 0
6502 22:56:12.044152 12, 0xFFFF, sum = 0
6503 22:56:12.044234 13, 0x0, sum = 1
6504 22:56:12.047041 14, 0x0, sum = 2
6505 22:56:12.047123 15, 0x0, sum = 3
6506 22:56:12.050668 16, 0x0, sum = 4
6507 22:56:12.050750 best_step = 14
6508 22:56:12.050814
6509 22:56:12.050873 ==
6510 22:56:12.053937 Dram Type= 6, Freq= 0, CH_0, rank 0
6511 22:56:12.056770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6512 22:56:12.056852 ==
6513 22:56:12.060129 RX Vref Scan: 1
6514 22:56:12.060209
6515 22:56:12.064060 RX Vref 0 -> 0, step: 1
6516 22:56:12.064141
6517 22:56:12.064206 RX Delay -359 -> 252, step: 8
6518 22:56:12.064266
6519 22:56:12.066820 Set Vref, RX VrefLevel [Byte0]: 61
6520 22:56:12.070067 [Byte1]: 59
6521 22:56:12.075886
6522 22:56:12.075966 Final RX Vref Byte 0 = 61 to rank0
6523 22:56:12.078704 Final RX Vref Byte 1 = 59 to rank0
6524 22:56:12.081901 Final RX Vref Byte 0 = 61 to rank1
6525 22:56:12.085189 Final RX Vref Byte 1 = 59 to rank1==
6526 22:56:12.089119 Dram Type= 6, Freq= 0, CH_0, rank 0
6527 22:56:12.095422 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6528 22:56:12.095507 ==
6529 22:56:12.095572 DQS Delay:
6530 22:56:12.098524 DQS0 = 48, DQS1 = 60
6531 22:56:12.098604 DQM Delay:
6532 22:56:12.098668 DQM0 = 11, DQM1 = 10
6533 22:56:12.101964 DQ Delay:
6534 22:56:12.105048 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6535 22:56:12.108612 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6536 22:56:12.108702 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =4
6537 22:56:12.115020 DQ12 =16, DQ13 =12, DQ14 =20, DQ15 =16
6538 22:56:12.115127
6539 22:56:12.115218
6540 22:56:12.121976 [DQSOSCAuto] RK0, (LSB)MR18= 0xc487, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 385 ps
6541 22:56:12.125402 CH0 RK0: MR19=C0C, MR18=C487
6542 22:56:12.131843 CH0_RK0: MR19=0xC0C, MR18=0xC487, DQSOSC=385, MR23=63, INC=398, DEC=265
6543 22:56:12.131925 ==
6544 22:56:12.134994 Dram Type= 6, Freq= 0, CH_0, rank 1
6545 22:56:12.137966 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6546 22:56:12.138073 ==
6547 22:56:12.141292 [Gating] SW mode calibration
6548 22:56:12.148056 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6549 22:56:12.154703 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6550 22:56:12.158090 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6551 22:56:12.161053 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6552 22:56:12.168396 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6553 22:56:12.171461 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6554 22:56:12.174391 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6555 22:56:12.181265 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6556 22:56:12.184685 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6557 22:56:12.188007 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6558 22:56:12.194476 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6559 22:56:12.197683 Total UI for P1: 0, mck2ui 16
6560 22:56:12.201040 best dqsien dly found for B0: ( 0, 14, 24)
6561 22:56:12.201150 Total UI for P1: 0, mck2ui 16
6562 22:56:12.207589 best dqsien dly found for B1: ( 0, 14, 24)
6563 22:56:12.211055 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6564 22:56:12.214272 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6565 22:56:12.214354
6566 22:56:12.217532 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6567 22:56:12.221081 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6568 22:56:12.223934 [Gating] SW calibration Done
6569 22:56:12.224016 ==
6570 22:56:12.227284 Dram Type= 6, Freq= 0, CH_0, rank 1
6571 22:56:12.230897 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6572 22:56:12.230979 ==
6573 22:56:12.233921 RX Vref Scan: 0
6574 22:56:12.234029
6575 22:56:12.237042 RX Vref 0 -> 0, step: 1
6576 22:56:12.237123
6577 22:56:12.237189 RX Delay -410 -> 252, step: 16
6578 22:56:12.243831 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6579 22:56:12.247447 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6580 22:56:12.250475 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6581 22:56:12.253824 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6582 22:56:12.260724 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6583 22:56:12.264093 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6584 22:56:12.267037 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6585 22:56:12.270375 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6586 22:56:12.276888 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6587 22:56:12.280134 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6588 22:56:12.283907 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6589 22:56:12.290251 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6590 22:56:12.293467 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6591 22:56:12.296765 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6592 22:56:12.299914 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6593 22:56:12.306752 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6594 22:56:12.306866 ==
6595 22:56:12.309900 Dram Type= 6, Freq= 0, CH_0, rank 1
6596 22:56:12.313699 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6597 22:56:12.313782 ==
6598 22:56:12.313848 DQS Delay:
6599 22:56:12.316456 DQS0 = 43, DQS1 = 59
6600 22:56:12.316575 DQM Delay:
6601 22:56:12.319864 DQM0 = 12, DQM1 = 17
6602 22:56:12.319945 DQ Delay:
6603 22:56:12.322947 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6604 22:56:12.326967 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =24
6605 22:56:12.329817 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6606 22:56:12.332872 DQ12 =24, DQ13 =24, DQ14 =32, DQ15 =24
6607 22:56:12.332954
6608 22:56:12.333018
6609 22:56:12.333077 ==
6610 22:56:12.336445 Dram Type= 6, Freq= 0, CH_0, rank 1
6611 22:56:12.339552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6612 22:56:12.339649 ==
6613 22:56:12.339713
6614 22:56:12.339773
6615 22:56:12.343334 TX Vref Scan disable
6616 22:56:12.346278 == TX Byte 0 ==
6617 22:56:12.349364 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6618 22:56:12.353234 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6619 22:56:12.355989 == TX Byte 1 ==
6620 22:56:12.359399 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6621 22:56:12.362862 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6622 22:56:12.362944 ==
6623 22:56:12.365874 Dram Type= 6, Freq= 0, CH_0, rank 1
6624 22:56:12.369557 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6625 22:56:12.369639 ==
6626 22:56:12.372799
6627 22:56:12.372880
6628 22:56:12.372944 TX Vref Scan disable
6629 22:56:12.375790 == TX Byte 0 ==
6630 22:56:12.379110 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6631 22:56:12.382870 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6632 22:56:12.386456 == TX Byte 1 ==
6633 22:56:12.389728 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6634 22:56:12.392740 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6635 22:56:12.392847
6636 22:56:12.392944 [DATLAT]
6637 22:56:12.396065 Freq=400, CH0 RK1
6638 22:56:12.396163
6639 22:56:12.399293 DATLAT Default: 0xe
6640 22:56:12.399393 0, 0xFFFF, sum = 0
6641 22:56:12.402570 1, 0xFFFF, sum = 0
6642 22:56:12.402681 2, 0xFFFF, sum = 0
6643 22:56:12.406123 3, 0xFFFF, sum = 0
6644 22:56:12.406207 4, 0xFFFF, sum = 0
6645 22:56:12.409110 5, 0xFFFF, sum = 0
6646 22:56:12.409193 6, 0xFFFF, sum = 0
6647 22:56:12.412740 7, 0xFFFF, sum = 0
6648 22:56:12.412822 8, 0xFFFF, sum = 0
6649 22:56:12.415622 9, 0xFFFF, sum = 0
6650 22:56:12.415705 10, 0xFFFF, sum = 0
6651 22:56:12.419424 11, 0xFFFF, sum = 0
6652 22:56:12.419508 12, 0xFFFF, sum = 0
6653 22:56:12.422577 13, 0x0, sum = 1
6654 22:56:12.422689 14, 0x0, sum = 2
6655 22:56:12.425436 15, 0x0, sum = 3
6656 22:56:12.425520 16, 0x0, sum = 4
6657 22:56:12.428683 best_step = 14
6658 22:56:12.428766
6659 22:56:12.428830 ==
6660 22:56:12.431993 Dram Type= 6, Freq= 0, CH_0, rank 1
6661 22:56:12.435335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6662 22:56:12.435419 ==
6663 22:56:12.438569 RX Vref Scan: 0
6664 22:56:12.438652
6665 22:56:12.438716 RX Vref 0 -> 0, step: 1
6666 22:56:12.438778
6667 22:56:12.442556 RX Delay -359 -> 252, step: 8
6668 22:56:12.450183 iDelay=217, Bit 0, Center -40 (-279 ~ 200) 480
6669 22:56:12.453263 iDelay=217, Bit 1, Center -36 (-279 ~ 208) 488
6670 22:56:12.456627 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6671 22:56:12.463570 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6672 22:56:12.466366 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6673 22:56:12.469770 iDelay=217, Bit 5, Center -44 (-287 ~ 200) 488
6674 22:56:12.473280 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6675 22:56:12.479725 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6676 22:56:12.483182 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6677 22:56:12.486318 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6678 22:56:12.489632 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
6679 22:56:12.496278 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6680 22:56:12.499456 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6681 22:56:12.502976 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6682 22:56:12.506005 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6683 22:56:12.513107 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6684 22:56:12.513190 ==
6685 22:56:12.515874 Dram Type= 6, Freq= 0, CH_0, rank 1
6686 22:56:12.519315 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6687 22:56:12.519399 ==
6688 22:56:12.519464 DQS Delay:
6689 22:56:12.522721 DQS0 = 44, DQS1 = 60
6690 22:56:12.522804 DQM Delay:
6691 22:56:12.525716 DQM0 = 8, DQM1 = 14
6692 22:56:12.525798 DQ Delay:
6693 22:56:12.529054 DQ0 =4, DQ1 =8, DQ2 =4, DQ3 =8
6694 22:56:12.532799 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6695 22:56:12.535587 DQ8 =4, DQ9 =0, DQ10 =20, DQ11 =8
6696 22:56:12.538975 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6697 22:56:12.539090
6698 22:56:12.539157
6699 22:56:12.545561 [DQSOSCAuto] RK1, (LSB)MR18= 0xc04a, (MSB)MR19= 0xc0c, tDQSOscB0 = 400 ps tDQSOscB1 = 386 ps
6700 22:56:12.549525 CH0 RK1: MR19=C0C, MR18=C04A
6701 22:56:12.556085 CH0_RK1: MR19=0xC0C, MR18=0xC04A, DQSOSC=386, MR23=63, INC=396, DEC=264
6702 22:56:12.558514 [RxdqsGatingPostProcess] freq 400
6703 22:56:12.565648 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6704 22:56:12.568646 best DQS0 dly(2T, 0.5T) = (0, 10)
6705 22:56:12.572041 best DQS1 dly(2T, 0.5T) = (0, 10)
6706 22:56:12.575159 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6707 22:56:12.579182 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6708 22:56:12.579287 best DQS0 dly(2T, 0.5T) = (0, 10)
6709 22:56:12.581956 best DQS1 dly(2T, 0.5T) = (0, 10)
6710 22:56:12.585382 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6711 22:56:12.588344 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6712 22:56:12.591688 Pre-setting of DQS Precalculation
6713 22:56:12.598517 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6714 22:56:12.598604 ==
6715 22:56:12.601696 Dram Type= 6, Freq= 0, CH_1, rank 0
6716 22:56:12.605181 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6717 22:56:12.605265 ==
6718 22:56:12.611766 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6719 22:56:12.617903 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6720 22:56:12.621555 [CA 0] Center 36 (8~64) winsize 57
6721 22:56:12.624706 [CA 1] Center 36 (8~64) winsize 57
6722 22:56:12.628180 [CA 2] Center 36 (8~64) winsize 57
6723 22:56:12.628263 [CA 3] Center 36 (8~64) winsize 57
6724 22:56:12.631688 [CA 4] Center 36 (8~64) winsize 57
6725 22:56:12.634931 [CA 5] Center 36 (8~64) winsize 57
6726 22:56:12.635014
6727 22:56:12.641069 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6728 22:56:12.641152
6729 22:56:12.644381 [CATrainingPosCal] consider 1 rank data
6730 22:56:12.647653 u2DelayCellTimex100 = 270/100 ps
6731 22:56:12.650933 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6732 22:56:12.654292 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6733 22:56:12.658011 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6734 22:56:12.661307 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6735 22:56:12.664160 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6736 22:56:12.667317 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6737 22:56:12.667403
6738 22:56:12.670518 CA PerBit enable=1, Macro0, CA PI delay=36
6739 22:56:12.670592
6740 22:56:12.673850 [CBTSetCACLKResult] CA Dly = 36
6741 22:56:12.677254 CS Dly: 1 (0~32)
6742 22:56:12.677327 ==
6743 22:56:12.680400 Dram Type= 6, Freq= 0, CH_1, rank 1
6744 22:56:12.683291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6745 22:56:12.683365 ==
6746 22:56:12.689907 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6747 22:56:12.696608 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6748 22:56:12.699928 [CA 0] Center 36 (8~64) winsize 57
6749 22:56:12.703681 [CA 1] Center 36 (8~64) winsize 57
6750 22:56:12.706727 [CA 2] Center 36 (8~64) winsize 57
6751 22:56:12.706810 [CA 3] Center 36 (8~64) winsize 57
6752 22:56:12.709721 [CA 4] Center 36 (8~64) winsize 57
6753 22:56:12.713570 [CA 5] Center 36 (8~64) winsize 57
6754 22:56:12.713666
6755 22:56:12.716756 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6756 22:56:12.719826
6757 22:56:12.723074 [CATrainingPosCal] consider 2 rank data
6758 22:56:12.726394 u2DelayCellTimex100 = 270/100 ps
6759 22:56:12.729920 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6760 22:56:12.733170 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6761 22:56:12.736210 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6762 22:56:12.739906 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6763 22:56:12.742748 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6764 22:56:12.746480 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6765 22:56:12.746600
6766 22:56:12.749377 CA PerBit enable=1, Macro0, CA PI delay=36
6767 22:56:12.749570
6768 22:56:12.753265 [CBTSetCACLKResult] CA Dly = 36
6769 22:56:12.756225 CS Dly: 1 (0~32)
6770 22:56:12.756322
6771 22:56:12.759962 ----->DramcWriteLeveling(PI) begin...
6772 22:56:12.760045 ==
6773 22:56:12.762657 Dram Type= 6, Freq= 0, CH_1, rank 0
6774 22:56:12.766144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6775 22:56:12.766226 ==
6776 22:56:12.769200 Write leveling (Byte 0): 40 => 8
6777 22:56:12.772642 Write leveling (Byte 1): 32 => 0
6778 22:56:12.775982 DramcWriteLeveling(PI) end<-----
6779 22:56:12.776063
6780 22:56:12.776127 ==
6781 22:56:12.779201 Dram Type= 6, Freq= 0, CH_1, rank 0
6782 22:56:12.783134 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6783 22:56:12.783247 ==
6784 22:56:12.786343 [Gating] SW mode calibration
6785 22:56:12.792371 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6786 22:56:12.799094 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6787 22:56:12.802348 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6788 22:56:12.805664 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6789 22:56:12.812319 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6790 22:56:12.815925 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6791 22:56:12.818943 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6792 22:56:12.825706 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6793 22:56:12.828938 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6794 22:56:12.832223 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6795 22:56:12.838680 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6796 22:56:12.841973 Total UI for P1: 0, mck2ui 16
6797 22:56:12.845268 best dqsien dly found for B0: ( 0, 14, 24)
6798 22:56:12.849110 Total UI for P1: 0, mck2ui 16
6799 22:56:12.851974 best dqsien dly found for B1: ( 0, 14, 24)
6800 22:56:12.855243 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6801 22:56:12.858625 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6802 22:56:12.858707
6803 22:56:12.861700 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6804 22:56:12.864920 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6805 22:56:12.868708 [Gating] SW calibration Done
6806 22:56:12.868790 ==
6807 22:56:12.871655 Dram Type= 6, Freq= 0, CH_1, rank 0
6808 22:56:12.875235 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6809 22:56:12.875318 ==
6810 22:56:12.878131 RX Vref Scan: 0
6811 22:56:12.878213
6812 22:56:12.881995 RX Vref 0 -> 0, step: 1
6813 22:56:12.882077
6814 22:56:12.884545 RX Delay -410 -> 252, step: 16
6815 22:56:12.888681 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6816 22:56:12.891542 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6817 22:56:12.894777 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6818 22:56:12.901787 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6819 22:56:12.904904 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6820 22:56:12.908298 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6821 22:56:12.911305 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6822 22:56:12.917728 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6823 22:56:12.921373 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6824 22:56:12.924392 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6825 22:56:12.928127 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6826 22:56:12.934360 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6827 22:56:12.937626 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6828 22:56:12.941007 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6829 22:56:12.947886 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6830 22:56:12.950897 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6831 22:56:12.950977 ==
6832 22:56:12.954167 Dram Type= 6, Freq= 0, CH_1, rank 0
6833 22:56:12.957206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6834 22:56:12.957284 ==
6835 22:56:12.960904 DQS Delay:
6836 22:56:12.961003 DQS0 = 43, DQS1 = 51
6837 22:56:12.961097 DQM Delay:
6838 22:56:12.964210 DQM0 = 12, DQM1 = 14
6839 22:56:12.964310 DQ Delay:
6840 22:56:12.967273 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6841 22:56:12.970741 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6842 22:56:12.973985 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6843 22:56:12.977316 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6844 22:56:12.977417
6845 22:56:12.977517
6846 22:56:12.977606 ==
6847 22:56:12.980735 Dram Type= 6, Freq= 0, CH_1, rank 0
6848 22:56:12.983958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6849 22:56:12.987134 ==
6850 22:56:12.987235
6851 22:56:12.987328
6852 22:56:12.987415 TX Vref Scan disable
6853 22:56:12.990727 == TX Byte 0 ==
6854 22:56:12.993585 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6855 22:56:12.997420 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6856 22:56:13.000763 == TX Byte 1 ==
6857 22:56:13.003949 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6858 22:56:13.007079 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6859 22:56:13.007178 ==
6860 22:56:13.010058 Dram Type= 6, Freq= 0, CH_1, rank 0
6861 22:56:13.016728 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6862 22:56:13.016814 ==
6863 22:56:13.016912
6864 22:56:13.016976
6865 22:56:13.017034 TX Vref Scan disable
6866 22:56:13.020384 == TX Byte 0 ==
6867 22:56:13.023378 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6868 22:56:13.026734 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6869 22:56:13.030302 == TX Byte 1 ==
6870 22:56:13.033260 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6871 22:56:13.036389 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6872 22:56:13.036489
6873 22:56:13.039671 [DATLAT]
6874 22:56:13.039740 Freq=400, CH1 RK0
6875 22:56:13.039800
6876 22:56:13.043400 DATLAT Default: 0xf
6877 22:56:13.043466 0, 0xFFFF, sum = 0
6878 22:56:13.046228 1, 0xFFFF, sum = 0
6879 22:56:13.046301 2, 0xFFFF, sum = 0
6880 22:56:13.049618 3, 0xFFFF, sum = 0
6881 22:56:13.049695 4, 0xFFFF, sum = 0
6882 22:56:13.052854 5, 0xFFFF, sum = 0
6883 22:56:13.056595 6, 0xFFFF, sum = 0
6884 22:56:13.056664 7, 0xFFFF, sum = 0
6885 22:56:13.059501 8, 0xFFFF, sum = 0
6886 22:56:13.059595 9, 0xFFFF, sum = 0
6887 22:56:13.062976 10, 0xFFFF, sum = 0
6888 22:56:13.063077 11, 0xFFFF, sum = 0
6889 22:56:13.066163 12, 0xFFFF, sum = 0
6890 22:56:13.066265 13, 0x0, sum = 1
6891 22:56:13.069433 14, 0x0, sum = 2
6892 22:56:13.069519 15, 0x0, sum = 3
6893 22:56:13.072753 16, 0x0, sum = 4
6894 22:56:13.072828 best_step = 14
6895 22:56:13.072892
6896 22:56:13.072954 ==
6897 22:56:13.076687 Dram Type= 6, Freq= 0, CH_1, rank 0
6898 22:56:13.079267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6899 22:56:13.079354 ==
6900 22:56:13.082851 RX Vref Scan: 1
6901 22:56:13.082949
6902 22:56:13.085753 RX Vref 0 -> 0, step: 1
6903 22:56:13.085856
6904 22:56:13.089587 RX Delay -343 -> 252, step: 8
6905 22:56:13.089686
6906 22:56:13.092676 Set Vref, RX VrefLevel [Byte0]: 52
6907 22:56:13.096350 [Byte1]: 53
6908 22:56:13.096449
6909 22:56:13.099080 Final RX Vref Byte 0 = 52 to rank0
6910 22:56:13.102754 Final RX Vref Byte 1 = 53 to rank0
6911 22:56:13.106042 Final RX Vref Byte 0 = 52 to rank1
6912 22:56:13.109151 Final RX Vref Byte 1 = 53 to rank1==
6913 22:56:13.112506 Dram Type= 6, Freq= 0, CH_1, rank 0
6914 22:56:13.115672 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6915 22:56:13.115777 ==
6916 22:56:13.118870 DQS Delay:
6917 22:56:13.118966 DQS0 = 48, DQS1 = 52
6918 22:56:13.122554 DQM Delay:
6919 22:56:13.122651 DQM0 = 14, DQM1 = 9
6920 22:56:13.125406 DQ Delay:
6921 22:56:13.125516 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =12
6922 22:56:13.129120 DQ4 =12, DQ5 =28, DQ6 =20, DQ7 =12
6923 22:56:13.132157 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =0
6924 22:56:13.135429 DQ12 =20, DQ13 =12, DQ14 =16, DQ15 =16
6925 22:56:13.135525
6926 22:56:13.135617
6927 22:56:13.145176 [DQSOSCAuto] RK0, (LSB)MR18= 0x9a71, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 390 ps
6928 22:56:13.148564 CH1 RK0: MR19=C0C, MR18=9A71
6929 22:56:13.155189 CH1_RK0: MR19=0xC0C, MR18=0x9A71, DQSOSC=390, MR23=63, INC=388, DEC=258
6930 22:56:13.155297 ==
6931 22:56:13.158788 Dram Type= 6, Freq= 0, CH_1, rank 1
6932 22:56:13.161918 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6933 22:56:13.162002 ==
6934 22:56:13.165192 [Gating] SW mode calibration
6935 22:56:13.171680 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6936 22:56:13.175122 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6937 22:56:13.181423 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6938 22:56:13.185078 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6939 22:56:13.188285 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6940 22:56:13.194673 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6941 22:56:13.197978 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6942 22:56:13.201544 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6943 22:56:13.208045 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6944 22:56:13.211836 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6945 22:56:13.214725 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6946 22:56:13.217933 Total UI for P1: 0, mck2ui 16
6947 22:56:13.221330 best dqsien dly found for B0: ( 0, 14, 24)
6948 22:56:13.224767 Total UI for P1: 0, mck2ui 16
6949 22:56:13.227918 best dqsien dly found for B1: ( 0, 14, 24)
6950 22:56:13.231311 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6951 22:56:13.238163 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6952 22:56:13.238241
6953 22:56:13.241286 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6954 22:56:13.244906 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6955 22:56:13.247575 [Gating] SW calibration Done
6956 22:56:13.247652 ==
6957 22:56:13.250993 Dram Type= 6, Freq= 0, CH_1, rank 1
6958 22:56:13.254140 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6959 22:56:13.254214 ==
6960 22:56:13.257457 RX Vref Scan: 0
6961 22:56:13.257534
6962 22:56:13.257596 RX Vref 0 -> 0, step: 1
6963 22:56:13.257655
6964 22:56:13.260924 RX Delay -410 -> 252, step: 16
6965 22:56:13.264178 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6966 22:56:13.270699 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6967 22:56:13.274328 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6968 22:56:13.277690 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6969 22:56:13.280983 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6970 22:56:13.287519 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6971 22:56:13.290564 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6972 22:56:13.293947 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6973 22:56:13.297339 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6974 22:56:13.303793 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6975 22:56:13.306986 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6976 22:56:13.310578 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6977 22:56:13.317291 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6978 22:56:13.320291 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6979 22:56:13.323703 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6980 22:56:13.326940 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6981 22:56:13.330046 ==
6982 22:56:13.333350 Dram Type= 6, Freq= 0, CH_1, rank 1
6983 22:56:13.337206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6984 22:56:13.337280 ==
6985 22:56:13.337350 DQS Delay:
6986 22:56:13.340237 DQS0 = 43, DQS1 = 51
6987 22:56:13.340341 DQM Delay:
6988 22:56:13.343445 DQM0 = 12, DQM1 = 14
6989 22:56:13.343516 DQ Delay:
6990 22:56:13.346584 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6991 22:56:13.350181 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6992 22:56:13.353624 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6993 22:56:13.356460 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6994 22:56:13.356556
6995 22:56:13.356622
6996 22:56:13.356680 ==
6997 22:56:13.359595 Dram Type= 6, Freq= 0, CH_1, rank 1
6998 22:56:13.363506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6999 22:56:13.363581 ==
7000 22:56:13.363642
7001 22:56:13.363706
7002 22:56:13.366506 TX Vref Scan disable
7003 22:56:13.366576 == TX Byte 0 ==
7004 22:56:13.373393 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
7005 22:56:13.376802 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
7006 22:56:13.376906 == TX Byte 1 ==
7007 22:56:13.382856 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
7008 22:56:13.386438 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
7009 22:56:13.386512 ==
7010 22:56:13.389651 Dram Type= 6, Freq= 0, CH_1, rank 1
7011 22:56:13.392761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7012 22:56:13.392855 ==
7013 22:56:13.392953
7014 22:56:13.393012
7015 22:56:13.396649 TX Vref Scan disable
7016 22:56:13.396729 == TX Byte 0 ==
7017 22:56:13.402657 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
7018 22:56:13.405851 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
7019 22:56:13.405926 == TX Byte 1 ==
7020 22:56:13.412476 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
7021 22:56:13.416134 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
7022 22:56:13.416214
7023 22:56:13.416277 [DATLAT]
7024 22:56:13.419264 Freq=400, CH1 RK1
7025 22:56:13.419336
7026 22:56:13.419395 DATLAT Default: 0xe
7027 22:56:13.422612 0, 0xFFFF, sum = 0
7028 22:56:13.422694 1, 0xFFFF, sum = 0
7029 22:56:13.425845 2, 0xFFFF, sum = 0
7030 22:56:13.425919 3, 0xFFFF, sum = 0
7031 22:56:13.428934 4, 0xFFFF, sum = 0
7032 22:56:13.429007 5, 0xFFFF, sum = 0
7033 22:56:13.432246 6, 0xFFFF, sum = 0
7034 22:56:13.435490 7, 0xFFFF, sum = 0
7035 22:56:13.435564 8, 0xFFFF, sum = 0
7036 22:56:13.439213 9, 0xFFFF, sum = 0
7037 22:56:13.439287 10, 0xFFFF, sum = 0
7038 22:56:13.442347 11, 0xFFFF, sum = 0
7039 22:56:13.442419 12, 0xFFFF, sum = 0
7040 22:56:13.445534 13, 0x0, sum = 1
7041 22:56:13.445612 14, 0x0, sum = 2
7042 22:56:13.448958 15, 0x0, sum = 3
7043 22:56:13.449036 16, 0x0, sum = 4
7044 22:56:13.451911 best_step = 14
7045 22:56:13.452006
7046 22:56:13.452092 ==
7047 22:56:13.455316 Dram Type= 6, Freq= 0, CH_1, rank 1
7048 22:56:13.458723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7049 22:56:13.458795 ==
7050 22:56:13.458862 RX Vref Scan: 0
7051 22:56:13.458919
7052 22:56:13.462540 RX Vref 0 -> 0, step: 1
7053 22:56:13.462611
7054 22:56:13.465422 RX Delay -343 -> 252, step: 8
7055 22:56:13.472746 iDelay=225, Bit 0, Center -28 (-271 ~ 216) 488
7056 22:56:13.475988 iDelay=225, Bit 1, Center -44 (-287 ~ 200) 488
7057 22:56:13.479331 iDelay=225, Bit 2, Center -44 (-287 ~ 200) 488
7058 22:56:13.486206 iDelay=225, Bit 3, Center -40 (-279 ~ 200) 480
7059 22:56:13.488968 iDelay=225, Bit 4, Center -40 (-287 ~ 208) 496
7060 22:56:13.492459 iDelay=225, Bit 5, Center -28 (-271 ~ 216) 488
7061 22:56:13.496023 iDelay=225, Bit 6, Center -24 (-271 ~ 224) 496
7062 22:56:13.502327 iDelay=225, Bit 7, Center -40 (-287 ~ 208) 496
7063 22:56:13.505695 iDelay=225, Bit 8, Center -56 (-303 ~ 192) 496
7064 22:56:13.508993 iDelay=225, Bit 9, Center -56 (-303 ~ 192) 496
7065 22:56:13.512481 iDelay=225, Bit 10, Center -44 (-295 ~ 208) 504
7066 22:56:13.518643 iDelay=225, Bit 11, Center -52 (-295 ~ 192) 488
7067 22:56:13.522282 iDelay=225, Bit 12, Center -36 (-287 ~ 216) 504
7068 22:56:13.525480 iDelay=225, Bit 13, Center -40 (-287 ~ 208) 496
7069 22:56:13.532233 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
7070 22:56:13.535697 iDelay=225, Bit 15, Center -36 (-287 ~ 216) 504
7071 22:56:13.535780 ==
7072 22:56:13.538524 Dram Type= 6, Freq= 0, CH_1, rank 1
7073 22:56:13.541906 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7074 22:56:13.541988 ==
7075 22:56:13.545266 DQS Delay:
7076 22:56:13.545366 DQS0 = 44, DQS1 = 56
7077 22:56:13.545446 DQM Delay:
7078 22:56:13.548110 DQM0 = 8, DQM1 = 11
7079 22:56:13.548192 DQ Delay:
7080 22:56:13.551842 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =4
7081 22:56:13.554877 DQ4 =4, DQ5 =16, DQ6 =20, DQ7 =4
7082 22:56:13.558106 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
7083 22:56:13.561490 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
7084 22:56:13.561573
7085 22:56:13.561637
7086 22:56:13.571411 [DQSOSCAuto] RK1, (LSB)MR18= 0x6f5d, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 395 ps
7087 22:56:13.571495 CH1 RK1: MR19=C0C, MR18=6F5D
7088 22:56:13.578149 CH1_RK1: MR19=0xC0C, MR18=0x6F5D, DQSOSC=395, MR23=63, INC=378, DEC=252
7089 22:56:13.581262 [RxdqsGatingPostProcess] freq 400
7090 22:56:13.588240 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7091 22:56:13.590958 best DQS0 dly(2T, 0.5T) = (0, 10)
7092 22:56:13.594153 best DQS1 dly(2T, 0.5T) = (0, 10)
7093 22:56:13.597990 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7094 22:56:13.601049 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7095 22:56:13.604166 best DQS0 dly(2T, 0.5T) = (0, 10)
7096 22:56:13.604251 best DQS1 dly(2T, 0.5T) = (0, 10)
7097 22:56:13.607987 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7098 22:56:13.610700 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7099 22:56:13.614516 Pre-setting of DQS Precalculation
7100 22:56:13.620675 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7101 22:56:13.627675 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7102 22:56:13.633953 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7103 22:56:13.634036
7104 22:56:13.634101
7105 22:56:13.637525 [Calibration Summary] 800 Mbps
7106 22:56:13.640624 CH 0, Rank 0
7107 22:56:13.640727 SW Impedance : PASS
7108 22:56:13.644205 DUTY Scan : NO K
7109 22:56:13.647385 ZQ Calibration : PASS
7110 22:56:13.647467 Jitter Meter : NO K
7111 22:56:13.650697 CBT Training : PASS
7112 22:56:13.650779 Write leveling : PASS
7113 22:56:13.653854 RX DQS gating : PASS
7114 22:56:13.657231 RX DQ/DQS(RDDQC) : PASS
7115 22:56:13.657312 TX DQ/DQS : PASS
7116 22:56:13.660428 RX DATLAT : PASS
7117 22:56:13.663733 RX DQ/DQS(Engine): PASS
7118 22:56:13.663815 TX OE : NO K
7119 22:56:13.667227 All Pass.
7120 22:56:13.667310
7121 22:56:13.667375 CH 0, Rank 1
7122 22:56:13.670703 SW Impedance : PASS
7123 22:56:13.670785 DUTY Scan : NO K
7124 22:56:13.673825 ZQ Calibration : PASS
7125 22:56:13.676782 Jitter Meter : NO K
7126 22:56:13.676865 CBT Training : PASS
7127 22:56:13.680090 Write leveling : NO K
7128 22:56:13.683700 RX DQS gating : PASS
7129 22:56:13.683782 RX DQ/DQS(RDDQC) : PASS
7130 22:56:13.687116 TX DQ/DQS : PASS
7131 22:56:13.690172 RX DATLAT : PASS
7132 22:56:13.690255 RX DQ/DQS(Engine): PASS
7133 22:56:13.693701 TX OE : NO K
7134 22:56:13.693784 All Pass.
7135 22:56:13.693849
7136 22:56:13.697023 CH 1, Rank 0
7137 22:56:13.697105 SW Impedance : PASS
7138 22:56:13.700344 DUTY Scan : NO K
7139 22:56:13.703896 ZQ Calibration : PASS
7140 22:56:13.703978 Jitter Meter : NO K
7141 22:56:13.707127 CBT Training : PASS
7142 22:56:13.707209 Write leveling : PASS
7143 22:56:13.710573 RX DQS gating : PASS
7144 22:56:13.713438 RX DQ/DQS(RDDQC) : PASS
7145 22:56:13.713535 TX DQ/DQS : PASS
7146 22:56:13.717055 RX DATLAT : PASS
7147 22:56:13.720079 RX DQ/DQS(Engine): PASS
7148 22:56:13.720162 TX OE : NO K
7149 22:56:13.724044 All Pass.
7150 22:56:13.724126
7151 22:56:13.724191 CH 1, Rank 1
7152 22:56:13.726708 SW Impedance : PASS
7153 22:56:13.726790 DUTY Scan : NO K
7154 22:56:13.730598 ZQ Calibration : PASS
7155 22:56:13.733145 Jitter Meter : NO K
7156 22:56:13.733229 CBT Training : PASS
7157 22:56:13.737090 Write leveling : NO K
7158 22:56:13.739903 RX DQS gating : PASS
7159 22:56:13.739986 RX DQ/DQS(RDDQC) : PASS
7160 22:56:13.743576 TX DQ/DQS : PASS
7161 22:56:13.746764 RX DATLAT : PASS
7162 22:56:13.746958 RX DQ/DQS(Engine): PASS
7163 22:56:13.749741 TX OE : NO K
7164 22:56:13.749824 All Pass.
7165 22:56:13.749889
7166 22:56:13.753367 DramC Write-DBI off
7167 22:56:13.756556 PER_BANK_REFRESH: Hybrid Mode
7168 22:56:13.756653 TX_TRACKING: ON
7169 22:56:13.766713 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7170 22:56:13.769451 [FAST_K] Save calibration result to emmc
7171 22:56:13.773225 dramc_set_vcore_voltage set vcore to 725000
7172 22:56:13.776424 Read voltage for 1600, 0
7173 22:56:13.776509 Vio18 = 0
7174 22:56:13.776594 Vcore = 725000
7175 22:56:13.779437 Vdram = 0
7176 22:56:13.779519 Vddq = 0
7177 22:56:13.779585 Vmddr = 0
7178 22:56:13.786312 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7179 22:56:13.789768 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7180 22:56:13.792931 MEM_TYPE=3, freq_sel=13
7181 22:56:13.796378 sv_algorithm_assistance_LP4_3733
7182 22:56:13.799615 ============ PULL DRAM RESETB DOWN ============
7183 22:56:13.802987 ========== PULL DRAM RESETB DOWN end =========
7184 22:56:13.809401 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7185 22:56:13.812827 ===================================
7186 22:56:13.815845 LPDDR4 DRAM CONFIGURATION
7187 22:56:13.819044 ===================================
7188 22:56:13.819126 EX_ROW_EN[0] = 0x0
7189 22:56:13.822377 EX_ROW_EN[1] = 0x0
7190 22:56:13.822459 LP4Y_EN = 0x0
7191 22:56:13.826209 WORK_FSP = 0x1
7192 22:56:13.826292 WL = 0x5
7193 22:56:13.828816 RL = 0x5
7194 22:56:13.828898 BL = 0x2
7195 22:56:13.832493 RPST = 0x0
7196 22:56:13.832607 RD_PRE = 0x0
7197 22:56:13.835398 WR_PRE = 0x1
7198 22:56:13.835506 WR_PST = 0x1
7199 22:56:13.838955 DBI_WR = 0x0
7200 22:56:13.842583 DBI_RD = 0x0
7201 22:56:13.842666 OTF = 0x1
7202 22:56:13.845715 ===================================
7203 22:56:13.849241 ===================================
7204 22:56:13.849323 ANA top config
7205 22:56:13.851996 ===================================
7206 22:56:13.855946 DLL_ASYNC_EN = 0
7207 22:56:13.859218 ALL_SLAVE_EN = 0
7208 22:56:13.861948 NEW_RANK_MODE = 1
7209 22:56:13.865390 DLL_IDLE_MODE = 1
7210 22:56:13.865473 LP45_APHY_COMB_EN = 1
7211 22:56:13.868651 TX_ODT_DIS = 0
7212 22:56:13.871692 NEW_8X_MODE = 1
7213 22:56:13.875023 ===================================
7214 22:56:13.878563 ===================================
7215 22:56:13.881695 data_rate = 3200
7216 22:56:13.885207 CKR = 1
7217 22:56:13.888510 DQ_P2S_RATIO = 8
7218 22:56:13.891810 ===================================
7219 22:56:13.891893 CA_P2S_RATIO = 8
7220 22:56:13.894925 DQ_CA_OPEN = 0
7221 22:56:13.898771 DQ_SEMI_OPEN = 0
7222 22:56:13.901535 CA_SEMI_OPEN = 0
7223 22:56:13.904772 CA_FULL_RATE = 0
7224 22:56:13.908117 DQ_CKDIV4_EN = 0
7225 22:56:13.908199 CA_CKDIV4_EN = 0
7226 22:56:13.911425 CA_PREDIV_EN = 0
7227 22:56:13.914953 PH8_DLY = 12
7228 22:56:13.918385 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7229 22:56:13.921223 DQ_AAMCK_DIV = 4
7230 22:56:13.924703 CA_AAMCK_DIV = 4
7231 22:56:13.924787 CA_ADMCK_DIV = 4
7232 22:56:13.927810 DQ_TRACK_CA_EN = 0
7233 22:56:13.931164 CA_PICK = 1600
7234 22:56:13.934601 CA_MCKIO = 1600
7235 22:56:13.937939 MCKIO_SEMI = 0
7236 22:56:13.941096 PLL_FREQ = 3068
7237 22:56:13.944489 DQ_UI_PI_RATIO = 32
7238 22:56:13.947598 CA_UI_PI_RATIO = 0
7239 22:56:13.950849 ===================================
7240 22:56:13.954223 ===================================
7241 22:56:13.954306 memory_type:LPDDR4
7242 22:56:13.957420 GP_NUM : 10
7243 22:56:13.960747 SRAM_EN : 1
7244 22:56:13.960830 MD32_EN : 0
7245 22:56:13.964058 ===================================
7246 22:56:13.967428 [ANA_INIT] >>>>>>>>>>>>>>
7247 22:56:13.970458 <<<<<< [CONFIGURE PHASE]: ANA_TX
7248 22:56:13.973797 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7249 22:56:13.977115 ===================================
7250 22:56:13.980457 data_rate = 3200,PCW = 0X7600
7251 22:56:13.983923 ===================================
7252 22:56:13.987074 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7253 22:56:13.990157 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7254 22:56:13.996712 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7255 22:56:14.000078 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7256 22:56:14.003559 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7257 22:56:14.010054 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7258 22:56:14.010137 [ANA_INIT] flow start
7259 22:56:14.013349 [ANA_INIT] PLL >>>>>>>>
7260 22:56:14.013432 [ANA_INIT] PLL <<<<<<<<
7261 22:56:14.016559 [ANA_INIT] MIDPI >>>>>>>>
7262 22:56:14.020048 [ANA_INIT] MIDPI <<<<<<<<
7263 22:56:14.023250 [ANA_INIT] DLL >>>>>>>>
7264 22:56:14.023333 [ANA_INIT] DLL <<<<<<<<
7265 22:56:14.026633 [ANA_INIT] flow end
7266 22:56:14.030128 ============ LP4 DIFF to SE enter ============
7267 22:56:14.033463 ============ LP4 DIFF to SE exit ============
7268 22:56:14.036453 [ANA_INIT] <<<<<<<<<<<<<
7269 22:56:14.039915 [Flow] Enable top DCM control >>>>>
7270 22:56:14.043670 [Flow] Enable top DCM control <<<<<
7271 22:56:14.046670 Enable DLL master slave shuffle
7272 22:56:14.052812 ==============================================================
7273 22:56:14.052893 Gating Mode config
7274 22:56:14.059707 ==============================================================
7275 22:56:14.059789 Config description:
7276 22:56:14.069641 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7277 22:56:14.076689 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7278 22:56:14.082809 SELPH_MODE 0: By rank 1: By Phase
7279 22:56:14.086532 ==============================================================
7280 22:56:14.089862 GAT_TRACK_EN = 1
7281 22:56:14.092636 RX_GATING_MODE = 2
7282 22:56:14.095944 RX_GATING_TRACK_MODE = 2
7283 22:56:14.099400 SELPH_MODE = 1
7284 22:56:14.102841 PICG_EARLY_EN = 1
7285 22:56:14.105964 VALID_LAT_VALUE = 1
7286 22:56:14.112734 ==============================================================
7287 22:56:14.116185 Enter into Gating configuration >>>>
7288 22:56:14.119629 Exit from Gating configuration <<<<
7289 22:56:14.122659 Enter into DVFS_PRE_config >>>>>
7290 22:56:14.132527 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7291 22:56:14.135604 Exit from DVFS_PRE_config <<<<<
7292 22:56:14.139381 Enter into PICG configuration >>>>
7293 22:56:14.142151 Exit from PICG configuration <<<<
7294 22:56:14.145407 [RX_INPUT] configuration >>>>>
7295 22:56:14.145492 [RX_INPUT] configuration <<<<<
7296 22:56:14.152379 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7297 22:56:14.159085 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7298 22:56:14.165325 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7299 22:56:14.169037 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7300 22:56:14.175381 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7301 22:56:14.181851 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7302 22:56:14.185150 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7303 22:56:14.188672 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7304 22:56:14.195660 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7305 22:56:14.198865 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7306 22:56:14.201888 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7307 22:56:14.208218 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7308 22:56:14.211768 ===================================
7309 22:56:14.211854 LPDDR4 DRAM CONFIGURATION
7310 22:56:14.215189 ===================================
7311 22:56:14.218294 EX_ROW_EN[0] = 0x0
7312 22:56:14.221641 EX_ROW_EN[1] = 0x0
7313 22:56:14.221725 LP4Y_EN = 0x0
7314 22:56:14.224939 WORK_FSP = 0x1
7315 22:56:14.225023 WL = 0x5
7316 22:56:14.228634 RL = 0x5
7317 22:56:14.228719 BL = 0x2
7318 22:56:14.231637 RPST = 0x0
7319 22:56:14.231721 RD_PRE = 0x0
7320 22:56:14.235099 WR_PRE = 0x1
7321 22:56:14.235184 WR_PST = 0x1
7322 22:56:14.237973 DBI_WR = 0x0
7323 22:56:14.238058 DBI_RD = 0x0
7324 22:56:14.241189 OTF = 0x1
7325 22:56:14.244626 ===================================
7326 22:56:14.248287 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7327 22:56:14.251583 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7328 22:56:14.257934 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7329 22:56:14.261740 ===================================
7330 22:56:14.261822 LPDDR4 DRAM CONFIGURATION
7331 22:56:14.264419 ===================================
7332 22:56:14.268012 EX_ROW_EN[0] = 0x10
7333 22:56:14.271337 EX_ROW_EN[1] = 0x0
7334 22:56:14.271419 LP4Y_EN = 0x0
7335 22:56:14.274494 WORK_FSP = 0x1
7336 22:56:14.274575 WL = 0x5
7337 22:56:14.277762 RL = 0x5
7338 22:56:14.277844 BL = 0x2
7339 22:56:14.281087 RPST = 0x0
7340 22:56:14.281185 RD_PRE = 0x0
7341 22:56:14.284188 WR_PRE = 0x1
7342 22:56:14.284269 WR_PST = 0x1
7343 22:56:14.287817 DBI_WR = 0x0
7344 22:56:14.287898 DBI_RD = 0x0
7345 22:56:14.291086 OTF = 0x1
7346 22:56:14.294409 ===================================
7347 22:56:14.300941 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7348 22:56:14.301024 ==
7349 22:56:14.304316 Dram Type= 6, Freq= 0, CH_0, rank 0
7350 22:56:14.307299 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7351 22:56:14.307383 ==
7352 22:56:14.310834 [Duty_Offset_Calibration]
7353 22:56:14.310916 B0:1 B1:-1 CA:0
7354 22:56:14.310981
7355 22:56:14.314058 [DutyScan_Calibration_Flow] k_type=0
7356 22:56:14.324991
7357 22:56:14.325073 ==CLK 0==
7358 22:56:14.328250 Final CLK duty delay cell = 0
7359 22:56:14.331613 [0] MAX Duty = 5125%(X100), DQS PI = 20
7360 22:56:14.334680 [0] MIN Duty = 4907%(X100), DQS PI = 4
7361 22:56:14.334761 [0] AVG Duty = 5016%(X100)
7362 22:56:14.338005
7363 22:56:14.341319 CH0 CLK Duty spec in!! Max-Min= 218%
7364 22:56:14.344730 [DutyScan_Calibration_Flow] ====Done====
7365 22:56:14.344810
7366 22:56:14.347919 [DutyScan_Calibration_Flow] k_type=1
7367 22:56:14.364175
7368 22:56:14.364264 ==DQS 0 ==
7369 22:56:14.367056 Final DQS duty delay cell = -4
7370 22:56:14.370593 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7371 22:56:14.374126 [-4] MIN Duty = 4844%(X100), DQS PI = 58
7372 22:56:14.377128 [-4] AVG Duty = 4922%(X100)
7373 22:56:14.377209
7374 22:56:14.377272 ==DQS 1 ==
7375 22:56:14.380398 Final DQS duty delay cell = 0
7376 22:56:14.383715 [0] MAX Duty = 5187%(X100), DQS PI = 2
7377 22:56:14.386936 [0] MIN Duty = 5031%(X100), DQS PI = 20
7378 22:56:14.390286 [0] AVG Duty = 5109%(X100)
7379 22:56:14.390366
7380 22:56:14.394573 CH0 DQS 0 Duty spec in!! Max-Min= 156%
7381 22:56:14.394655
7382 22:56:14.396687 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7383 22:56:14.400382 [DutyScan_Calibration_Flow] ====Done====
7384 22:56:14.400463
7385 22:56:14.403384 [DutyScan_Calibration_Flow] k_type=3
7386 22:56:14.421470
7387 22:56:14.421551 ==DQM 0 ==
7388 22:56:14.424921 Final DQM duty delay cell = 0
7389 22:56:14.427958 [0] MAX Duty = 5124%(X100), DQS PI = 24
7390 22:56:14.431411 [0] MIN Duty = 4907%(X100), DQS PI = 8
7391 22:56:14.434382 [0] AVG Duty = 5015%(X100)
7392 22:56:14.434463
7393 22:56:14.434565 ==DQM 1 ==
7394 22:56:14.437885 Final DQM duty delay cell = 0
7395 22:56:14.440896 [0] MAX Duty = 5031%(X100), DQS PI = 52
7396 22:56:14.444169 [0] MIN Duty = 4813%(X100), DQS PI = 20
7397 22:56:14.447495 [0] AVG Duty = 4922%(X100)
7398 22:56:14.447575
7399 22:56:14.451410 CH0 DQM 0 Duty spec in!! Max-Min= 217%
7400 22:56:14.451490
7401 22:56:14.454743 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7402 22:56:14.457783 [DutyScan_Calibration_Flow] ====Done====
7403 22:56:14.457864
7404 22:56:14.461238 [DutyScan_Calibration_Flow] k_type=2
7405 22:56:14.477931
7406 22:56:14.478015 ==DQ 0 ==
7407 22:56:14.481541 Final DQ duty delay cell = -4
7408 22:56:14.484653 [-4] MAX Duty = 5031%(X100), DQS PI = 24
7409 22:56:14.487560 [-4] MIN Duty = 4876%(X100), DQS PI = 54
7410 22:56:14.490935 [-4] AVG Duty = 4953%(X100)
7411 22:56:14.491018
7412 22:56:14.491082 ==DQ 1 ==
7413 22:56:14.494521 Final DQ duty delay cell = 0
7414 22:56:14.497830 [0] MAX Duty = 5125%(X100), DQS PI = 4
7415 22:56:14.501148 [0] MIN Duty = 4969%(X100), DQS PI = 38
7416 22:56:14.504257 [0] AVG Duty = 5047%(X100)
7417 22:56:14.504339
7418 22:56:14.507363 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7419 22:56:14.507446
7420 22:56:14.510966 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7421 22:56:14.514594 [DutyScan_Calibration_Flow] ====Done====
7422 22:56:14.514677 ==
7423 22:56:14.517360 Dram Type= 6, Freq= 0, CH_1, rank 0
7424 22:56:14.520764 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7425 22:56:14.520848 ==
7426 22:56:14.524015 [Duty_Offset_Calibration]
7427 22:56:14.524098 B0:-1 B1:1 CA:2
7428 22:56:14.524163
7429 22:56:14.527212 [DutyScan_Calibration_Flow] k_type=0
7430 22:56:14.538443
7431 22:56:14.538526 ==CLK 0==
7432 22:56:14.541591 Final CLK duty delay cell = 0
7433 22:56:14.545073 [0] MAX Duty = 5218%(X100), DQS PI = 24
7434 22:56:14.548341 [0] MIN Duty = 4969%(X100), DQS PI = 62
7435 22:56:14.548424 [0] AVG Duty = 5093%(X100)
7436 22:56:14.551692
7437 22:56:14.555064 CH1 CLK Duty spec in!! Max-Min= 249%
7438 22:56:14.558226 [DutyScan_Calibration_Flow] ====Done====
7439 22:56:14.558309
7440 22:56:14.561777 [DutyScan_Calibration_Flow] k_type=1
7441 22:56:14.578096
7442 22:56:14.578178 ==DQS 0 ==
7443 22:56:14.581182 Final DQS duty delay cell = 0
7444 22:56:14.584771 [0] MAX Duty = 5156%(X100), DQS PI = 18
7445 22:56:14.587707 [0] MIN Duty = 4907%(X100), DQS PI = 10
7446 22:56:14.591362 [0] AVG Duty = 5031%(X100)
7447 22:56:14.591444
7448 22:56:14.591509 ==DQS 1 ==
7449 22:56:14.594377 Final DQS duty delay cell = 0
7450 22:56:14.598083 [0] MAX Duty = 5093%(X100), DQS PI = 24
7451 22:56:14.601049 [0] MIN Duty = 4969%(X100), DQS PI = 54
7452 22:56:14.604632 [0] AVG Duty = 5031%(X100)
7453 22:56:14.604714
7454 22:56:14.607946 CH1 DQS 0 Duty spec in!! Max-Min= 249%
7455 22:56:14.608028
7456 22:56:14.611211 CH1 DQS 1 Duty spec in!! Max-Min= 124%
7457 22:56:14.614519 [DutyScan_Calibration_Flow] ====Done====
7458 22:56:14.614601
7459 22:56:14.617831 [DutyScan_Calibration_Flow] k_type=3
7460 22:56:14.634188
7461 22:56:14.634270 ==DQM 0 ==
7462 22:56:14.637354 Final DQM duty delay cell = -4
7463 22:56:14.640597 [-4] MAX Duty = 5062%(X100), DQS PI = 18
7464 22:56:14.644600 [-4] MIN Duty = 4813%(X100), DQS PI = 8
7465 22:56:14.647398 [-4] AVG Duty = 4937%(X100)
7466 22:56:14.647481
7467 22:56:14.647545 ==DQM 1 ==
7468 22:56:14.650692 Final DQM duty delay cell = 0
7469 22:56:14.654350 [0] MAX Duty = 5156%(X100), DQS PI = 2
7470 22:56:14.657244 [0] MIN Duty = 5000%(X100), DQS PI = 30
7471 22:56:14.660558 [0] AVG Duty = 5078%(X100)
7472 22:56:14.660643
7473 22:56:14.663922 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7474 22:56:14.664004
7475 22:56:14.667081 CH1 DQM 1 Duty spec in!! Max-Min= 156%
7476 22:56:14.671034 [DutyScan_Calibration_Flow] ====Done====
7477 22:56:14.671117
7478 22:56:14.674069 [DutyScan_Calibration_Flow] k_type=2
7479 22:56:14.691350
7480 22:56:14.691433 ==DQ 0 ==
7481 22:56:14.694587 Final DQ duty delay cell = 0
7482 22:56:14.698061 [0] MAX Duty = 5187%(X100), DQS PI = 32
7483 22:56:14.701473 [0] MIN Duty = 4906%(X100), DQS PI = 8
7484 22:56:14.701561 [0] AVG Duty = 5046%(X100)
7485 22:56:14.701626
7486 22:56:14.704600 ==DQ 1 ==
7487 22:56:14.707779 Final DQ duty delay cell = 0
7488 22:56:14.710952 [0] MAX Duty = 5156%(X100), DQS PI = 8
7489 22:56:14.714553 [0] MIN Duty = 4969%(X100), DQS PI = 56
7490 22:56:14.714653 [0] AVG Duty = 5062%(X100)
7491 22:56:14.714743
7492 22:56:14.717951 CH1 DQ 0 Duty spec in!! Max-Min= 281%
7493 22:56:14.718023
7494 22:56:14.725054 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7495 22:56:14.727796 [DutyScan_Calibration_Flow] ====Done====
7496 22:56:14.731076 nWR fixed to 30
7497 22:56:14.731159 [ModeRegInit_LP4] CH0 RK0
7498 22:56:14.734600 [ModeRegInit_LP4] CH0 RK1
7499 22:56:14.737661 [ModeRegInit_LP4] CH1 RK0
7500 22:56:14.737743 [ModeRegInit_LP4] CH1 RK1
7501 22:56:14.741022 match AC timing 5
7502 22:56:14.744307 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7503 22:56:14.751158 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7504 22:56:14.754342 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7505 22:56:14.757808 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7506 22:56:14.764462 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7507 22:56:14.764585 [MiockJmeterHQA]
7508 22:56:14.764651
7509 22:56:14.767402 [DramcMiockJmeter] u1RxGatingPI = 0
7510 22:56:14.771040 0 : 4363, 4138
7511 22:56:14.771123 4 : 4252, 4027
7512 22:56:14.771190 8 : 4363, 4138
7513 22:56:14.774570 12 : 4252, 4027
7514 22:56:14.774654 16 : 4363, 4138
7515 22:56:14.777575 20 : 4253, 4027
7516 22:56:14.777678 24 : 4253, 4026
7517 22:56:14.780885 28 : 4253, 4026
7518 22:56:14.780969 32 : 4363, 4138
7519 22:56:14.784251 36 : 4363, 4137
7520 22:56:14.784334 40 : 4363, 4138
7521 22:56:14.784400 44 : 4252, 4026
7522 22:56:14.787393 48 : 4255, 4029
7523 22:56:14.787476 52 : 4252, 4027
7524 22:56:14.790983 56 : 4255, 4029
7525 22:56:14.791066 60 : 4361, 4137
7526 22:56:14.794169 64 : 4250, 4027
7527 22:56:14.794306 68 : 4250, 4027
7528 22:56:14.797294 72 : 4250, 4027
7529 22:56:14.797378 76 : 4250, 4026
7530 22:56:14.797445 80 : 4250, 4027
7531 22:56:14.800495 84 : 4361, 4138
7532 22:56:14.800603 88 : 4360, 4138
7533 22:56:14.803592 92 : 4363, 588
7534 22:56:14.803676 96 : 4248, 0
7535 22:56:14.807056 100 : 4252, 0
7536 22:56:14.807140 104 : 4252, 0
7537 22:56:14.807207 108 : 4250, 0
7538 22:56:14.810344 112 : 4253, 0
7539 22:56:14.810444 116 : 4252, 0
7540 22:56:14.813715 120 : 4250, 0
7541 22:56:14.813798 124 : 4255, 0
7542 22:56:14.813864 128 : 4252, 0
7543 22:56:14.816904 132 : 4250, 0
7544 22:56:14.816988 136 : 4250, 0
7545 22:56:14.819859 140 : 4361, 0
7546 22:56:14.819942 144 : 4361, 0
7547 22:56:14.820009 148 : 4363, 0
7548 22:56:14.823234 152 : 4250, 0
7549 22:56:14.823317 156 : 4360, 0
7550 22:56:14.823383 160 : 4250, 0
7551 22:56:14.826628 164 : 4250, 0
7552 22:56:14.826718 168 : 4250, 0
7553 22:56:14.829923 172 : 4250, 0
7554 22:56:14.830007 176 : 4255, 0
7555 22:56:14.830072 180 : 4250, 0
7556 22:56:14.833139 184 : 4250, 0
7557 22:56:14.833223 188 : 4250, 0
7558 22:56:14.836831 192 : 4363, 0
7559 22:56:14.836914 196 : 4361, 0
7560 22:56:14.836980 200 : 4363, 0
7561 22:56:14.839901 204 : 4250, 0
7562 22:56:14.839984 208 : 4360, 0
7563 22:56:14.843243 212 : 4250, 0
7564 22:56:14.843367 216 : 4250, 0
7565 22:56:14.843434 220 : 4250, 0
7566 22:56:14.846489 224 : 4250, 372
7567 22:56:14.846576 228 : 4361, 3711
7568 22:56:14.850175 232 : 4250, 4027
7569 22:56:14.850259 236 : 4361, 4137
7570 22:56:14.853010 240 : 4250, 4027
7571 22:56:14.853099 244 : 4250, 4027
7572 22:56:14.856444 248 : 4252, 4029
7573 22:56:14.856550 252 : 4363, 4140
7574 22:56:14.859642 256 : 4250, 4027
7575 22:56:14.859756 260 : 4250, 4027
7576 22:56:14.859859 264 : 4250, 4027
7577 22:56:14.862886 268 : 4252, 4029
7578 22:56:14.862957 272 : 4250, 4026
7579 22:56:14.866617 276 : 4360, 4138
7580 22:56:14.866693 280 : 4361, 4138
7581 22:56:14.869419 284 : 4250, 4027
7582 22:56:14.869493 288 : 4250, 4026
7583 22:56:14.873153 292 : 4250, 4027
7584 22:56:14.873230 296 : 4250, 4027
7585 22:56:14.876360 300 : 4250, 4026
7586 22:56:14.876428 304 : 4360, 4138
7587 22:56:14.879462 308 : 4250, 4027
7588 22:56:14.879537 312 : 4250, 4027
7589 22:56:14.883107 316 : 4363, 4140
7590 22:56:14.883183 320 : 4250, 4027
7591 22:56:14.886333 324 : 4250, 4027
7592 22:56:14.886410 328 : 4360, 4138
7593 22:56:14.886475 332 : 4361, 4138
7594 22:56:14.889871 336 : 4250, 3701
7595 22:56:14.889944 340 : 4250, 1853
7596 22:56:14.890014
7597 22:56:14.893016 MIOCK jitter meter ch=0
7598 22:56:14.893092
7599 22:56:14.896341 1T = (340-92) = 248 dly cells
7600 22:56:14.902622 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 262/100 ps
7601 22:56:14.902707 ==
7602 22:56:14.905908 Dram Type= 6, Freq= 0, CH_0, rank 0
7603 22:56:14.909047 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7604 22:56:14.909157 ==
7605 22:56:14.916187 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7606 22:56:14.919408 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7607 22:56:14.922439 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7608 22:56:14.929751 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7609 22:56:14.938080 [CA 0] Center 43 (12~74) winsize 63
7610 22:56:14.941527 [CA 1] Center 42 (12~73) winsize 62
7611 22:56:14.944835 [CA 2] Center 38 (9~68) winsize 60
7612 22:56:14.948720 [CA 3] Center 38 (8~68) winsize 61
7613 22:56:14.951418 [CA 4] Center 36 (7~66) winsize 60
7614 22:56:14.954713 [CA 5] Center 35 (6~65) winsize 60
7615 22:56:14.954804
7616 22:56:14.958308 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7617 22:56:14.958378
7618 22:56:14.961101 [CATrainingPosCal] consider 1 rank data
7619 22:56:14.964710 u2DelayCellTimex100 = 262/100 ps
7620 22:56:14.971186 CA0 delay=43 (12~74),Diff = 8 PI (29 cell)
7621 22:56:14.974250 CA1 delay=42 (12~73),Diff = 7 PI (26 cell)
7622 22:56:14.977940 CA2 delay=38 (9~68),Diff = 3 PI (11 cell)
7623 22:56:14.980907 CA3 delay=38 (8~68),Diff = 3 PI (11 cell)
7624 22:56:14.984393 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7625 22:56:14.987537 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7626 22:56:14.987633
7627 22:56:14.991471 CA PerBit enable=1, Macro0, CA PI delay=35
7628 22:56:14.991588
7629 22:56:14.994226 [CBTSetCACLKResult] CA Dly = 35
7630 22:56:14.997479 CS Dly: 12 (0~43)
7631 22:56:15.001373 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7632 22:56:15.004328 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7633 22:56:15.004442 ==
7634 22:56:15.007405 Dram Type= 6, Freq= 0, CH_0, rank 1
7635 22:56:15.013794 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7636 22:56:15.013877 ==
7637 22:56:15.017429 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7638 22:56:15.023879 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7639 22:56:15.026992 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7640 22:56:15.033984 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7641 22:56:15.041874 [CA 0] Center 42 (12~73) winsize 62
7642 22:56:15.045150 [CA 1] Center 43 (13~73) winsize 61
7643 22:56:15.048392 [CA 2] Center 37 (8~67) winsize 60
7644 22:56:15.051716 [CA 3] Center 37 (7~67) winsize 61
7645 22:56:15.054887 [CA 4] Center 35 (6~65) winsize 60
7646 22:56:15.058366 [CA 5] Center 35 (5~65) winsize 61
7647 22:56:15.058552
7648 22:56:15.061277 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7649 22:56:15.061359
7650 22:56:15.068194 [CATrainingPosCal] consider 2 rank data
7651 22:56:15.068285 u2DelayCellTimex100 = 262/100 ps
7652 22:56:15.074625 CA0 delay=42 (12~73),Diff = 7 PI (26 cell)
7653 22:56:15.078002 CA1 delay=43 (13~73),Diff = 8 PI (29 cell)
7654 22:56:15.081119 CA2 delay=38 (9~67),Diff = 3 PI (11 cell)
7655 22:56:15.084717 CA3 delay=37 (8~67),Diff = 2 PI (7 cell)
7656 22:56:15.087737 CA4 delay=36 (7~65),Diff = 1 PI (3 cell)
7657 22:56:15.091284 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7658 22:56:15.091362
7659 22:56:15.094255 CA PerBit enable=1, Macro0, CA PI delay=35
7660 22:56:15.094383
7661 22:56:15.097877 [CBTSetCACLKResult] CA Dly = 35
7662 22:56:15.101312 CS Dly: 12 (0~44)
7663 22:56:15.104222 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7664 22:56:15.107836 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7665 22:56:15.107920
7666 22:56:15.110807 ----->DramcWriteLeveling(PI) begin...
7667 22:56:15.114026 ==
7668 22:56:15.114104 Dram Type= 6, Freq= 0, CH_0, rank 0
7669 22:56:15.120862 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7670 22:56:15.120944 ==
7671 22:56:15.123812 Write leveling (Byte 0): 36 => 36
7672 22:56:15.127045 Write leveling (Byte 1): 26 => 26
7673 22:56:15.130359 DramcWriteLeveling(PI) end<-----
7674 22:56:15.130440
7675 22:56:15.130504 ==
7676 22:56:15.133794 Dram Type= 6, Freq= 0, CH_0, rank 0
7677 22:56:15.137388 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7678 22:56:15.137471 ==
7679 22:56:15.140379 [Gating] SW mode calibration
7680 22:56:15.147089 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7681 22:56:15.153694 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7682 22:56:15.156943 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7683 22:56:15.160096 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7684 22:56:15.167066 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7685 22:56:15.170068 1 4 12 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
7686 22:56:15.173496 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7687 22:56:15.180097 1 4 20 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
7688 22:56:15.183838 1 4 24 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
7689 22:56:15.186873 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7690 22:56:15.193496 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7691 22:56:15.196359 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7692 22:56:15.200256 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7693 22:56:15.206656 1 5 12 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (1 0)
7694 22:56:15.210023 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7695 22:56:15.213250 1 5 20 | B1->B0 | 3232 2323 | 0 0 | (0 1) (0 0)
7696 22:56:15.219368 1 5 24 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
7697 22:56:15.222654 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7698 22:56:15.226358 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7699 22:56:15.233235 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7700 22:56:15.236035 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7701 22:56:15.239131 1 6 12 | B1->B0 | 2323 3939 | 0 0 | (0 0) (0 0)
7702 22:56:15.246131 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7703 22:56:15.249394 1 6 20 | B1->B0 | 3232 4646 | 0 0 | (0 0) (0 0)
7704 22:56:15.252657 1 6 24 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
7705 22:56:15.259264 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7706 22:56:15.262425 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7707 22:56:15.265786 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7708 22:56:15.272938 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7709 22:56:15.276025 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7710 22:56:15.279024 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7711 22:56:15.285573 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7712 22:56:15.289305 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7713 22:56:15.292284 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7714 22:56:15.296107 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7715 22:56:15.302217 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7716 22:56:15.305863 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7717 22:56:15.308612 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7718 22:56:15.316009 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7719 22:56:15.318768 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7720 22:56:15.322184 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7721 22:56:15.328669 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7722 22:56:15.331964 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7723 22:56:15.335206 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7724 22:56:15.341960 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7725 22:56:15.345679 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7726 22:56:15.348899 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7727 22:56:15.355605 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7728 22:56:15.358793 Total UI for P1: 0, mck2ui 16
7729 22:56:15.361930 best dqsien dly found for B0: ( 1, 9, 14)
7730 22:56:15.365464 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7731 22:56:15.368233 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7732 22:56:15.372070 Total UI for P1: 0, mck2ui 16
7733 22:56:15.375150 best dqsien dly found for B1: ( 1, 9, 22)
7734 22:56:15.378339 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
7735 22:56:15.381914 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7736 22:56:15.384929
7737 22:56:15.388155 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
7738 22:56:15.391862 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7739 22:56:15.395289 [Gating] SW calibration Done
7740 22:56:15.395386 ==
7741 22:56:15.397982 Dram Type= 6, Freq= 0, CH_0, rank 0
7742 22:56:15.401276 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7743 22:56:15.401376 ==
7744 22:56:15.404704 RX Vref Scan: 0
7745 22:56:15.404785
7746 22:56:15.404849 RX Vref 0 -> 0, step: 1
7747 22:56:15.404908
7748 22:56:15.407957 RX Delay 0 -> 252, step: 8
7749 22:56:15.411416 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7750 22:56:15.414206 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7751 22:56:15.421482 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7752 22:56:15.424419 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7753 22:56:15.428010 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7754 22:56:15.431269 iDelay=200, Bit 5, Center 123 (64 ~ 183) 120
7755 22:56:15.434596 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7756 22:56:15.441155 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
7757 22:56:15.444456 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7758 22:56:15.447629 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7759 22:56:15.450944 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
7760 22:56:15.457773 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7761 22:56:15.460701 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7762 22:56:15.464187 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7763 22:56:15.467629 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7764 22:56:15.470481 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7765 22:56:15.474116 ==
7766 22:56:15.474197 Dram Type= 6, Freq= 0, CH_0, rank 0
7767 22:56:15.481092 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7768 22:56:15.481175 ==
7769 22:56:15.481240 DQS Delay:
7770 22:56:15.484080 DQS0 = 0, DQS1 = 0
7771 22:56:15.484161 DQM Delay:
7772 22:56:15.487616 DQM0 = 135, DQM1 = 127
7773 22:56:15.487698 DQ Delay:
7774 22:56:15.490836 DQ0 =135, DQ1 =139, DQ2 =131, DQ3 =131
7775 22:56:15.494098 DQ4 =135, DQ5 =123, DQ6 =143, DQ7 =143
7776 22:56:15.497080 DQ8 =119, DQ9 =115, DQ10 =127, DQ11 =119
7777 22:56:15.500258 DQ12 =131, DQ13 =135, DQ14 =139, DQ15 =131
7778 22:56:15.500343
7779 22:56:15.500408
7780 22:56:15.500469 ==
7781 22:56:15.503847 Dram Type= 6, Freq= 0, CH_0, rank 0
7782 22:56:15.510429 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7783 22:56:15.510536 ==
7784 22:56:15.510602
7785 22:56:15.510662
7786 22:56:15.510721 TX Vref Scan disable
7787 22:56:15.513926 == TX Byte 0 ==
7788 22:56:15.517151 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7789 22:56:15.523892 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7790 22:56:15.523979 == TX Byte 1 ==
7791 22:56:15.527166 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7792 22:56:15.534394 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7793 22:56:15.534486 ==
7794 22:56:15.537243 Dram Type= 6, Freq= 0, CH_0, rank 0
7795 22:56:15.541087 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7796 22:56:15.541174 ==
7797 22:56:15.552460
7798 22:56:15.555764 TX Vref early break, caculate TX vref
7799 22:56:15.559083 TX Vref=16, minBit 9, minWin=22, winSum=371
7800 22:56:15.562740 TX Vref=18, minBit 1, minWin=23, winSum=377
7801 22:56:15.565722 TX Vref=20, minBit 11, minWin=23, winSum=386
7802 22:56:15.569238 TX Vref=22, minBit 1, minWin=24, winSum=400
7803 22:56:15.572457 TX Vref=24, minBit 0, minWin=25, winSum=409
7804 22:56:15.578824 TX Vref=26, minBit 1, minWin=25, winSum=415
7805 22:56:15.582369 TX Vref=28, minBit 7, minWin=25, winSum=419
7806 22:56:15.585276 TX Vref=30, minBit 4, minWin=24, winSum=410
7807 22:56:15.588911 TX Vref=32, minBit 7, minWin=23, winSum=397
7808 22:56:15.595670 [TxChooseVref] Worse bit 7, Min win 25, Win sum 419, Final Vref 28
7809 22:56:15.595792
7810 22:56:15.598382 Final TX Range 0 Vref 28
7811 22:56:15.598467
7812 22:56:15.598533 ==
7813 22:56:15.602173 Dram Type= 6, Freq= 0, CH_0, rank 0
7814 22:56:15.605420 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7815 22:56:15.605505 ==
7816 22:56:15.605570
7817 22:56:15.605631
7818 22:56:15.608508 TX Vref Scan disable
7819 22:56:15.615304 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
7820 22:56:15.615392 == TX Byte 0 ==
7821 22:56:15.618400 u2DelayCellOfst[0]=14 cells (4 PI)
7822 22:56:15.621691 u2DelayCellOfst[1]=18 cells (5 PI)
7823 22:56:15.625620 u2DelayCellOfst[2]=14 cells (4 PI)
7824 22:56:15.628433 u2DelayCellOfst[3]=14 cells (4 PI)
7825 22:56:15.631681 u2DelayCellOfst[4]=11 cells (3 PI)
7826 22:56:15.635386 u2DelayCellOfst[5]=0 cells (0 PI)
7827 22:56:15.638365 u2DelayCellOfst[6]=22 cells (6 PI)
7828 22:56:15.641848 u2DelayCellOfst[7]=22 cells (6 PI)
7829 22:56:15.644927 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7830 22:56:15.648277 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7831 22:56:15.651576 == TX Byte 1 ==
7832 22:56:15.655025 u2DelayCellOfst[8]=0 cells (0 PI)
7833 22:56:15.655112 u2DelayCellOfst[9]=3 cells (1 PI)
7834 22:56:15.658167 u2DelayCellOfst[10]=7 cells (2 PI)
7835 22:56:15.661311 u2DelayCellOfst[11]=0 cells (0 PI)
7836 22:56:15.664496 u2DelayCellOfst[12]=14 cells (4 PI)
7837 22:56:15.667634 u2DelayCellOfst[13]=14 cells (4 PI)
7838 22:56:15.671077 u2DelayCellOfst[14]=14 cells (4 PI)
7839 22:56:15.674916 u2DelayCellOfst[15]=11 cells (3 PI)
7840 22:56:15.678432 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7841 22:56:15.684559 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7842 22:56:15.684647 DramC Write-DBI on
7843 22:56:15.684714 ==
7844 22:56:15.687718 Dram Type= 6, Freq= 0, CH_0, rank 0
7845 22:56:15.694589 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7846 22:56:15.694676 ==
7847 22:56:15.694743
7848 22:56:15.694803
7849 22:56:15.694861 TX Vref Scan disable
7850 22:56:15.698671 == TX Byte 0 ==
7851 22:56:15.702047 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7852 22:56:15.704985 == TX Byte 1 ==
7853 22:56:15.708538 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
7854 22:56:15.711549 DramC Write-DBI off
7855 22:56:15.711644
7856 22:56:15.711710 [DATLAT]
7857 22:56:15.711770 Freq=1600, CH0 RK0
7858 22:56:15.711829
7859 22:56:15.714968 DATLAT Default: 0xf
7860 22:56:15.715051 0, 0xFFFF, sum = 0
7861 22:56:15.718227 1, 0xFFFF, sum = 0
7862 22:56:15.721502 2, 0xFFFF, sum = 0
7863 22:56:15.721586 3, 0xFFFF, sum = 0
7864 22:56:15.724971 4, 0xFFFF, sum = 0
7865 22:56:15.725056 5, 0xFFFF, sum = 0
7866 22:56:15.727964 6, 0xFFFF, sum = 0
7867 22:56:15.728048 7, 0xFFFF, sum = 0
7868 22:56:15.731484 8, 0xFFFF, sum = 0
7869 22:56:15.731569 9, 0xFFFF, sum = 0
7870 22:56:15.734615 10, 0xFFFF, sum = 0
7871 22:56:15.734700 11, 0xFFFF, sum = 0
7872 22:56:15.737767 12, 0xFFFF, sum = 0
7873 22:56:15.737852 13, 0xFFFF, sum = 0
7874 22:56:15.741476 14, 0x0, sum = 1
7875 22:56:15.741561 15, 0x0, sum = 2
7876 22:56:15.744811 16, 0x0, sum = 3
7877 22:56:15.744895 17, 0x0, sum = 4
7878 22:56:15.747950 best_step = 15
7879 22:56:15.748033
7880 22:56:15.748098 ==
7881 22:56:15.751149 Dram Type= 6, Freq= 0, CH_0, rank 0
7882 22:56:15.755030 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7883 22:56:15.755114 ==
7884 22:56:15.758298 RX Vref Scan: 1
7885 22:56:15.758380
7886 22:56:15.758446 Set Vref Range= 24 -> 127
7887 22:56:15.758507
7888 22:56:15.761060 RX Vref 24 -> 127, step: 1
7889 22:56:15.761143
7890 22:56:15.764348 RX Delay 19 -> 252, step: 4
7891 22:56:15.764431
7892 22:56:15.767485 Set Vref, RX VrefLevel [Byte0]: 24
7893 22:56:15.770694 [Byte1]: 24
7894 22:56:15.770779
7895 22:56:15.774433 Set Vref, RX VrefLevel [Byte0]: 25
7896 22:56:15.777774 [Byte1]: 25
7897 22:56:15.781394
7898 22:56:15.781478 Set Vref, RX VrefLevel [Byte0]: 26
7899 22:56:15.784447 [Byte1]: 26
7900 22:56:15.788302
7901 22:56:15.791700 Set Vref, RX VrefLevel [Byte0]: 27
7902 22:56:15.795099 [Byte1]: 27
7903 22:56:15.795184
7904 22:56:15.798264 Set Vref, RX VrefLevel [Byte0]: 28
7905 22:56:15.801479 [Byte1]: 28
7906 22:56:15.801564
7907 22:56:15.805123 Set Vref, RX VrefLevel [Byte0]: 29
7908 22:56:15.808762 [Byte1]: 29
7909 22:56:15.808845
7910 22:56:15.811406 Set Vref, RX VrefLevel [Byte0]: 30
7911 22:56:15.814697 [Byte1]: 30
7912 22:56:15.819508
7913 22:56:15.819591 Set Vref, RX VrefLevel [Byte0]: 31
7914 22:56:15.822708 [Byte1]: 31
7915 22:56:15.826731
7916 22:56:15.826815 Set Vref, RX VrefLevel [Byte0]: 32
7917 22:56:15.829801 [Byte1]: 32
7918 22:56:15.834174
7919 22:56:15.834265 Set Vref, RX VrefLevel [Byte0]: 33
7920 22:56:15.837103 [Byte1]: 33
7921 22:56:15.841610
7922 22:56:15.841696 Set Vref, RX VrefLevel [Byte0]: 34
7923 22:56:15.845053 [Byte1]: 34
7924 22:56:15.849055
7925 22:56:15.849139 Set Vref, RX VrefLevel [Byte0]: 35
7926 22:56:15.852543 [Byte1]: 35
7927 22:56:15.856771
7928 22:56:15.856861 Set Vref, RX VrefLevel [Byte0]: 36
7929 22:56:15.859939 [Byte1]: 36
7930 22:56:15.864454
7931 22:56:15.864575 Set Vref, RX VrefLevel [Byte0]: 37
7932 22:56:15.867820 [Byte1]: 37
7933 22:56:15.871941
7934 22:56:15.872039 Set Vref, RX VrefLevel [Byte0]: 38
7935 22:56:15.875165 [Byte1]: 38
7936 22:56:15.879706
7937 22:56:15.879793 Set Vref, RX VrefLevel [Byte0]: 39
7938 22:56:15.882845 [Byte1]: 39
7939 22:56:15.887032
7940 22:56:15.890572 Set Vref, RX VrefLevel [Byte0]: 40
7941 22:56:15.893538 [Byte1]: 40
7942 22:56:15.893622
7943 22:56:15.896578 Set Vref, RX VrefLevel [Byte0]: 41
7944 22:56:15.900191 [Byte1]: 41
7945 22:56:15.900280
7946 22:56:15.903476 Set Vref, RX VrefLevel [Byte0]: 42
7947 22:56:15.906912 [Byte1]: 42
7948 22:56:15.906996
7949 22:56:15.909899 Set Vref, RX VrefLevel [Byte0]: 43
7950 22:56:15.913032 [Byte1]: 43
7951 22:56:15.917799
7952 22:56:15.917907 Set Vref, RX VrefLevel [Byte0]: 44
7953 22:56:15.920780 [Byte1]: 44
7954 22:56:15.924944
7955 22:56:15.925031 Set Vref, RX VrefLevel [Byte0]: 45
7956 22:56:15.928225 [Byte1]: 45
7957 22:56:15.932746
7958 22:56:15.932834 Set Vref, RX VrefLevel [Byte0]: 46
7959 22:56:15.935648 [Byte1]: 46
7960 22:56:15.940224
7961 22:56:15.940316 Set Vref, RX VrefLevel [Byte0]: 47
7962 22:56:15.943633 [Byte1]: 47
7963 22:56:15.947964
7964 22:56:15.948072 Set Vref, RX VrefLevel [Byte0]: 48
7965 22:56:15.950955 [Byte1]: 48
7966 22:56:15.955214
7967 22:56:15.955318 Set Vref, RX VrefLevel [Byte0]: 49
7968 22:56:15.958871 [Byte1]: 49
7969 22:56:15.962764
7970 22:56:15.962854 Set Vref, RX VrefLevel [Byte0]: 50
7971 22:56:15.965937 [Byte1]: 50
7972 22:56:15.970645
7973 22:56:15.970743 Set Vref, RX VrefLevel [Byte0]: 51
7974 22:56:15.974044 [Byte1]: 51
7975 22:56:15.978150
7976 22:56:15.978245 Set Vref, RX VrefLevel [Byte0]: 52
7977 22:56:15.981261 [Byte1]: 52
7978 22:56:15.985396
7979 22:56:15.985487 Set Vref, RX VrefLevel [Byte0]: 53
7980 22:56:15.988906 [Byte1]: 53
7981 22:56:15.993404
7982 22:56:15.993528 Set Vref, RX VrefLevel [Byte0]: 54
7983 22:56:15.996548 [Byte1]: 54
7984 22:56:16.000625
7985 22:56:16.000731 Set Vref, RX VrefLevel [Byte0]: 55
7986 22:56:16.004107 [Byte1]: 55
7987 22:56:16.008850
7988 22:56:16.008957 Set Vref, RX VrefLevel [Byte0]: 56
7989 22:56:16.011610 [Byte1]: 56
7990 22:56:16.016225
7991 22:56:16.016316 Set Vref, RX VrefLevel [Byte0]: 57
7992 22:56:16.019180 [Byte1]: 57
7993 22:56:16.023336
7994 22:56:16.023424 Set Vref, RX VrefLevel [Byte0]: 58
7995 22:56:16.026788 [Byte1]: 58
7996 22:56:16.031121
7997 22:56:16.031225 Set Vref, RX VrefLevel [Byte0]: 59
7998 22:56:16.034777 [Byte1]: 59
7999 22:56:16.038462
8000 22:56:16.038551 Set Vref, RX VrefLevel [Byte0]: 60
8001 22:56:16.042086 [Byte1]: 60
8002 22:56:16.046119
8003 22:56:16.046216 Set Vref, RX VrefLevel [Byte0]: 61
8004 22:56:16.049657 [Byte1]: 61
8005 22:56:16.053918
8006 22:56:16.054007 Set Vref, RX VrefLevel [Byte0]: 62
8007 22:56:16.057359 [Byte1]: 62
8008 22:56:16.061265
8009 22:56:16.061353 Set Vref, RX VrefLevel [Byte0]: 63
8010 22:56:16.064839 [Byte1]: 63
8011 22:56:16.068971
8012 22:56:16.069065 Set Vref, RX VrefLevel [Byte0]: 64
8013 22:56:16.072079 [Byte1]: 64
8014 22:56:16.076775
8015 22:56:16.076889 Set Vref, RX VrefLevel [Byte0]: 65
8016 22:56:16.079792 [Byte1]: 65
8017 22:56:16.084142
8018 22:56:16.084250 Set Vref, RX VrefLevel [Byte0]: 66
8019 22:56:16.087296 [Byte1]: 66
8020 22:56:16.091460
8021 22:56:16.091559 Set Vref, RX VrefLevel [Byte0]: 67
8022 22:56:16.094893 [Byte1]: 67
8023 22:56:16.099343
8024 22:56:16.099462 Set Vref, RX VrefLevel [Byte0]: 68
8025 22:56:16.102434 [Byte1]: 68
8026 22:56:16.106497
8027 22:56:16.106597 Set Vref, RX VrefLevel [Byte0]: 69
8028 22:56:16.110052 [Byte1]: 69
8029 22:56:16.114392
8030 22:56:16.114495 Set Vref, RX VrefLevel [Byte0]: 70
8031 22:56:16.117351 [Byte1]: 70
8032 22:56:16.121652
8033 22:56:16.121756 Set Vref, RX VrefLevel [Byte0]: 71
8034 22:56:16.125366 [Byte1]: 71
8035 22:56:16.129273
8036 22:56:16.129375 Set Vref, RX VrefLevel [Byte0]: 72
8037 22:56:16.132949 [Byte1]: 72
8038 22:56:16.137293
8039 22:56:16.137396 Set Vref, RX VrefLevel [Byte0]: 73
8040 22:56:16.140172 [Byte1]: 73
8041 22:56:16.144711
8042 22:56:16.144862 Set Vref, RX VrefLevel [Byte0]: 74
8043 22:56:16.147812 [Byte1]: 74
8044 22:56:16.151880
8045 22:56:16.151982 Set Vref, RX VrefLevel [Byte0]: 75
8046 22:56:16.155292 [Byte1]: 75
8047 22:56:16.159857
8048 22:56:16.159960 Set Vref, RX VrefLevel [Byte0]: 76
8049 22:56:16.163125 [Byte1]: 76
8050 22:56:16.167631
8051 22:56:16.167737 Set Vref, RX VrefLevel [Byte0]: 77
8052 22:56:16.170629 [Byte1]: 77
8053 22:56:16.174802
8054 22:56:16.174901 Set Vref, RX VrefLevel [Byte0]: 78
8055 22:56:16.177925 [Byte1]: 78
8056 22:56:16.182223
8057 22:56:16.182330 Final RX Vref Byte 0 = 67 to rank0
8058 22:56:16.185933 Final RX Vref Byte 1 = 56 to rank0
8059 22:56:16.189187 Final RX Vref Byte 0 = 67 to rank1
8060 22:56:16.192347 Final RX Vref Byte 1 = 56 to rank1==
8061 22:56:16.195837 Dram Type= 6, Freq= 0, CH_0, rank 0
8062 22:56:16.202379 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8063 22:56:16.202531 ==
8064 22:56:16.202605 DQS Delay:
8065 22:56:16.206081 DQS0 = 0, DQS1 = 0
8066 22:56:16.206172 DQM Delay:
8067 22:56:16.206239 DQM0 = 133, DQM1 = 124
8068 22:56:16.208792 DQ Delay:
8069 22:56:16.212240 DQ0 =132, DQ1 =136, DQ2 =130, DQ3 =132
8070 22:56:16.215639 DQ4 =132, DQ5 =122, DQ6 =142, DQ7 =142
8071 22:56:16.218951 DQ8 =116, DQ9 =112, DQ10 =124, DQ11 =118
8072 22:56:16.222213 DQ12 =130, DQ13 =128, DQ14 =134, DQ15 =130
8073 22:56:16.222311
8074 22:56:16.222379
8075 22:56:16.222438
8076 22:56:16.225121 [DramC_TX_OE_Calibration] TA2
8077 22:56:16.228495 Original DQ_B0 (3 6) =30, OEN = 27
8078 22:56:16.232036 Original DQ_B1 (3 6) =30, OEN = 27
8079 22:56:16.235438 24, 0x0, End_B0=24 End_B1=24
8080 22:56:16.235534 25, 0x0, End_B0=25 End_B1=25
8081 22:56:16.238382 26, 0x0, End_B0=26 End_B1=26
8082 22:56:16.241785 27, 0x0, End_B0=27 End_B1=27
8083 22:56:16.245514 28, 0x0, End_B0=28 End_B1=28
8084 22:56:16.248322 29, 0x0, End_B0=29 End_B1=29
8085 22:56:16.248416 30, 0x0, End_B0=30 End_B1=30
8086 22:56:16.251856 31, 0x4141, End_B0=30 End_B1=30
8087 22:56:16.255210 Byte0 end_step=30 best_step=27
8088 22:56:16.258342 Byte1 end_step=30 best_step=27
8089 22:56:16.261374 Byte0 TX OE(2T, 0.5T) = (3, 3)
8090 22:56:16.264943 Byte1 TX OE(2T, 0.5T) = (3, 3)
8091 22:56:16.265040
8092 22:56:16.265107
8093 22:56:16.271685 [DQSOSCAuto] RK0, (LSB)MR18= 0x2112, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 393 ps
8094 22:56:16.274755 CH0 RK0: MR19=303, MR18=2112
8095 22:56:16.281433 CH0_RK0: MR19=0x303, MR18=0x2112, DQSOSC=393, MR23=63, INC=23, DEC=15
8096 22:56:16.281567
8097 22:56:16.285194 ----->DramcWriteLeveling(PI) begin...
8098 22:56:16.285288 ==
8099 22:56:16.288413 Dram Type= 6, Freq= 0, CH_0, rank 1
8100 22:56:16.291605 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8101 22:56:16.291700 ==
8102 22:56:16.294823 Write leveling (Byte 0): 35 => 35
8103 22:56:16.297909 Write leveling (Byte 1): 28 => 28
8104 22:56:16.301259 DramcWriteLeveling(PI) end<-----
8105 22:56:16.301364
8106 22:56:16.301451 ==
8107 22:56:16.304463 Dram Type= 6, Freq= 0, CH_0, rank 1
8108 22:56:16.307815 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8109 22:56:16.311335 ==
8110 22:56:16.311449 [Gating] SW mode calibration
8111 22:56:16.318133 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8112 22:56:16.324486 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8113 22:56:16.328144 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8114 22:56:16.334935 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8115 22:56:16.338008 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8116 22:56:16.341309 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8117 22:56:16.347795 1 4 16 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
8118 22:56:16.350784 1 4 20 | B1->B0 | 3332 3434 | 1 1 | (0 0) (1 1)
8119 22:56:16.354492 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8120 22:56:16.360602 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8121 22:56:16.363978 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8122 22:56:16.367182 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8123 22:56:16.373976 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8124 22:56:16.377406 1 5 12 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
8125 22:56:16.380694 1 5 16 | B1->B0 | 3434 2a2a | 1 0 | (1 0) (0 0)
8126 22:56:16.387385 1 5 20 | B1->B0 | 2d2d 2323 | 1 0 | (1 0) (0 0)
8127 22:56:16.390593 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8128 22:56:16.393699 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8129 22:56:16.400011 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8130 22:56:16.403377 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8131 22:56:16.407107 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8132 22:56:16.413417 1 6 12 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
8133 22:56:16.416665 1 6 16 | B1->B0 | 2323 4242 | 0 0 | (0 0) (0 0)
8134 22:56:16.420078 1 6 20 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
8135 22:56:16.426914 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8136 22:56:16.430137 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8137 22:56:16.433003 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8138 22:56:16.439718 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8139 22:56:16.443089 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8140 22:56:16.446389 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8141 22:56:16.452998 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8142 22:56:16.456201 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8143 22:56:16.459831 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8144 22:56:16.466756 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8145 22:56:16.469492 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8146 22:56:16.472885 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8147 22:56:16.479444 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8148 22:56:16.483198 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8149 22:56:16.486365 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8150 22:56:16.492997 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8151 22:56:16.496616 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8152 22:56:16.499660 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8153 22:56:16.505996 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8154 22:56:16.509402 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8155 22:56:16.512423 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8156 22:56:16.519240 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8157 22:56:16.522560 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8158 22:56:16.525605 Total UI for P1: 0, mck2ui 16
8159 22:56:16.528904 best dqsien dly found for B0: ( 1, 9, 12)
8160 22:56:16.532558 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8161 22:56:16.539005 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8162 22:56:16.539127 Total UI for P1: 0, mck2ui 16
8163 22:56:16.545811 best dqsien dly found for B1: ( 1, 9, 18)
8164 22:56:16.549205 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8165 22:56:16.552445 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8166 22:56:16.552584
8167 22:56:16.555382 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8168 22:56:16.558678 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8169 22:56:16.562168 [Gating] SW calibration Done
8170 22:56:16.562269 ==
8171 22:56:16.565634 Dram Type= 6, Freq= 0, CH_0, rank 1
8172 22:56:16.568654 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8173 22:56:16.568749 ==
8174 22:56:16.572317 RX Vref Scan: 0
8175 22:56:16.572406
8176 22:56:16.572475 RX Vref 0 -> 0, step: 1
8177 22:56:16.572581
8178 22:56:16.575412 RX Delay 0 -> 252, step: 8
8179 22:56:16.578939 iDelay=208, Bit 0, Center 135 (80 ~ 191) 112
8180 22:56:16.585473 iDelay=208, Bit 1, Center 139 (80 ~ 199) 120
8181 22:56:16.588675 iDelay=208, Bit 2, Center 127 (72 ~ 183) 112
8182 22:56:16.591887 iDelay=208, Bit 3, Center 127 (72 ~ 183) 112
8183 22:56:16.594945 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8184 22:56:16.598466 iDelay=208, Bit 5, Center 123 (64 ~ 183) 120
8185 22:56:16.605112 iDelay=208, Bit 6, Center 139 (80 ~ 199) 120
8186 22:56:16.608847 iDelay=208, Bit 7, Center 147 (88 ~ 207) 120
8187 22:56:16.611904 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8188 22:56:16.614932 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8189 22:56:16.618332 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8190 22:56:16.625235 iDelay=208, Bit 11, Center 123 (64 ~ 183) 120
8191 22:56:16.628638 iDelay=208, Bit 12, Center 131 (72 ~ 191) 120
8192 22:56:16.631852 iDelay=208, Bit 13, Center 135 (80 ~ 191) 112
8193 22:56:16.635053 iDelay=208, Bit 14, Center 139 (80 ~ 199) 120
8194 22:56:16.641602 iDelay=208, Bit 15, Center 135 (80 ~ 191) 112
8195 22:56:16.641727 ==
8196 22:56:16.644723 Dram Type= 6, Freq= 0, CH_0, rank 1
8197 22:56:16.648119 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8198 22:56:16.648216 ==
8199 22:56:16.648284 DQS Delay:
8200 22:56:16.651864 DQS0 = 0, DQS1 = 0
8201 22:56:16.651950 DQM Delay:
8202 22:56:16.654623 DQM0 = 134, DQM1 = 128
8203 22:56:16.654709 DQ Delay:
8204 22:56:16.658010 DQ0 =135, DQ1 =139, DQ2 =127, DQ3 =127
8205 22:56:16.661247 DQ4 =135, DQ5 =123, DQ6 =139, DQ7 =147
8206 22:56:16.664470 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8207 22:56:16.668302 DQ12 =131, DQ13 =135, DQ14 =139, DQ15 =135
8208 22:56:16.668426
8209 22:56:16.668552
8210 22:56:16.671588 ==
8211 22:56:16.674476 Dram Type= 6, Freq= 0, CH_0, rank 1
8212 22:56:16.677769 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8213 22:56:16.677864 ==
8214 22:56:16.677932
8215 22:56:16.677992
8216 22:56:16.680852 TX Vref Scan disable
8217 22:56:16.680939 == TX Byte 0 ==
8218 22:56:16.684630 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8219 22:56:16.691041 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8220 22:56:16.691166 == TX Byte 1 ==
8221 22:56:16.697536 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8222 22:56:16.701068 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8223 22:56:16.701165 ==
8224 22:56:16.704042 Dram Type= 6, Freq= 0, CH_0, rank 1
8225 22:56:16.707322 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8226 22:56:16.707418 ==
8227 22:56:16.721576
8228 22:56:16.724796 TX Vref early break, caculate TX vref
8229 22:56:16.728028 TX Vref=16, minBit 1, minWin=22, winSum=375
8230 22:56:16.731492 TX Vref=18, minBit 1, minWin=22, winSum=388
8231 22:56:16.734352 TX Vref=20, minBit 0, minWin=23, winSum=393
8232 22:56:16.738152 TX Vref=22, minBit 2, minWin=23, winSum=400
8233 22:56:16.741392 TX Vref=24, minBit 1, minWin=24, winSum=411
8234 22:56:16.747818 TX Vref=26, minBit 1, minWin=24, winSum=416
8235 22:56:16.751472 TX Vref=28, minBit 4, minWin=24, winSum=416
8236 22:56:16.754241 TX Vref=30, minBit 1, minWin=23, winSum=403
8237 22:56:16.757779 TX Vref=32, minBit 2, minWin=23, winSum=395
8238 22:56:16.761202 TX Vref=34, minBit 0, minWin=22, winSum=386
8239 22:56:16.767867 [TxChooseVref] Worse bit 1, Min win 24, Win sum 416, Final Vref 26
8240 22:56:16.767999
8241 22:56:16.771062 Final TX Range 0 Vref 26
8242 22:56:16.771157
8243 22:56:16.771222 ==
8244 22:56:16.774862 Dram Type= 6, Freq= 0, CH_0, rank 1
8245 22:56:16.777993 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8246 22:56:16.778088 ==
8247 22:56:16.778155
8248 22:56:16.778216
8249 22:56:16.780747 TX Vref Scan disable
8250 22:56:16.787683 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8251 22:56:16.787812 == TX Byte 0 ==
8252 22:56:16.790881 u2DelayCellOfst[0]=14 cells (4 PI)
8253 22:56:16.793976 u2DelayCellOfst[1]=18 cells (5 PI)
8254 22:56:16.797447 u2DelayCellOfst[2]=14 cells (4 PI)
8255 22:56:16.800885 u2DelayCellOfst[3]=14 cells (4 PI)
8256 22:56:16.803899 u2DelayCellOfst[4]=11 cells (3 PI)
8257 22:56:16.807460 u2DelayCellOfst[5]=0 cells (0 PI)
8258 22:56:16.810378 u2DelayCellOfst[6]=22 cells (6 PI)
8259 22:56:16.813713 u2DelayCellOfst[7]=22 cells (6 PI)
8260 22:56:16.817027 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8261 22:56:16.820571 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8262 22:56:16.823809 == TX Byte 1 ==
8263 22:56:16.826986 u2DelayCellOfst[8]=0 cells (0 PI)
8264 22:56:16.830429 u2DelayCellOfst[9]=3 cells (1 PI)
8265 22:56:16.830537 u2DelayCellOfst[10]=7 cells (2 PI)
8266 22:56:16.833913 u2DelayCellOfst[11]=3 cells (1 PI)
8267 22:56:16.836939 u2DelayCellOfst[12]=14 cells (4 PI)
8268 22:56:16.840405 u2DelayCellOfst[13]=11 cells (3 PI)
8269 22:56:16.843575 u2DelayCellOfst[14]=18 cells (5 PI)
8270 22:56:16.846927 u2DelayCellOfst[15]=11 cells (3 PI)
8271 22:56:16.853741 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8272 22:56:16.856766 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8273 22:56:16.856922 DramC Write-DBI on
8274 22:56:16.856994 ==
8275 22:56:16.860324 Dram Type= 6, Freq= 0, CH_0, rank 1
8276 22:56:16.866683 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8277 22:56:16.866822 ==
8278 22:56:16.866934
8279 22:56:16.867026
8280 22:56:16.870113 TX Vref Scan disable
8281 22:56:16.870236 == TX Byte 0 ==
8282 22:56:16.876371 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8283 22:56:16.876487 == TX Byte 1 ==
8284 22:56:16.879984 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8285 22:56:16.883385 DramC Write-DBI off
8286 22:56:16.883468
8287 22:56:16.883531 [DATLAT]
8288 22:56:16.886579 Freq=1600, CH0 RK1
8289 22:56:16.886655
8290 22:56:16.886717 DATLAT Default: 0xf
8291 22:56:16.889682 0, 0xFFFF, sum = 0
8292 22:56:16.889792 1, 0xFFFF, sum = 0
8293 22:56:16.893028 2, 0xFFFF, sum = 0
8294 22:56:16.893132 3, 0xFFFF, sum = 0
8295 22:56:16.896296 4, 0xFFFF, sum = 0
8296 22:56:16.896370 5, 0xFFFF, sum = 0
8297 22:56:16.899432 6, 0xFFFF, sum = 0
8298 22:56:16.899524 7, 0xFFFF, sum = 0
8299 22:56:16.903160 8, 0xFFFF, sum = 0
8300 22:56:16.906077 9, 0xFFFF, sum = 0
8301 22:56:16.906178 10, 0xFFFF, sum = 0
8302 22:56:16.909653 11, 0xFFFF, sum = 0
8303 22:56:16.909737 12, 0xFFFF, sum = 0
8304 22:56:16.912607 13, 0xFFFF, sum = 0
8305 22:56:16.912707 14, 0x0, sum = 1
8306 22:56:16.915929 15, 0x0, sum = 2
8307 22:56:16.916013 16, 0x0, sum = 3
8308 22:56:16.919462 17, 0x0, sum = 4
8309 22:56:16.919545 best_step = 15
8310 22:56:16.919610
8311 22:56:16.919671 ==
8312 22:56:16.922799 Dram Type= 6, Freq= 0, CH_0, rank 1
8313 22:56:16.925938 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8314 22:56:16.929448 ==
8315 22:56:16.929559 RX Vref Scan: 0
8316 22:56:16.929658
8317 22:56:16.932397 RX Vref 0 -> 0, step: 1
8318 22:56:16.932479
8319 22:56:16.932582 RX Delay 11 -> 252, step: 4
8320 22:56:16.939932 iDelay=195, Bit 0, Center 128 (79 ~ 178) 100
8321 22:56:16.943683 iDelay=195, Bit 1, Center 134 (79 ~ 190) 112
8322 22:56:16.946621 iDelay=195, Bit 2, Center 124 (71 ~ 178) 108
8323 22:56:16.949644 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8324 22:56:16.952918 iDelay=195, Bit 4, Center 132 (79 ~ 186) 108
8325 22:56:16.960270 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
8326 22:56:16.963395 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8327 22:56:16.966224 iDelay=195, Bit 7, Center 140 (87 ~ 194) 108
8328 22:56:16.969780 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
8329 22:56:16.973171 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8330 22:56:16.979931 iDelay=195, Bit 10, Center 126 (71 ~ 182) 112
8331 22:56:16.982743 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8332 22:56:16.986333 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
8333 22:56:16.989194 iDelay=195, Bit 13, Center 130 (75 ~ 186) 112
8334 22:56:16.996794 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
8335 22:56:16.999478 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8336 22:56:16.999607 ==
8337 22:56:17.002812 Dram Type= 6, Freq= 0, CH_0, rank 1
8338 22:56:17.006124 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8339 22:56:17.006242 ==
8340 22:56:17.009384 DQS Delay:
8341 22:56:17.009476 DQS0 = 0, DQS1 = 0
8342 22:56:17.009542 DQM Delay:
8343 22:56:17.012463 DQM0 = 130, DQM1 = 125
8344 22:56:17.012585 DQ Delay:
8345 22:56:17.016067 DQ0 =128, DQ1 =134, DQ2 =124, DQ3 =128
8346 22:56:17.018971 DQ4 =132, DQ5 =120, DQ6 =138, DQ7 =140
8347 22:56:17.026044 DQ8 =114, DQ9 =112, DQ10 =126, DQ11 =120
8348 22:56:17.028999 DQ12 =132, DQ13 =130, DQ14 =136, DQ15 =132
8349 22:56:17.029120
8350 22:56:17.029214
8351 22:56:17.029315
8352 22:56:17.032539 [DramC_TX_OE_Calibration] TA2
8353 22:56:17.035846 Original DQ_B0 (3 6) =30, OEN = 27
8354 22:56:17.039094 Original DQ_B1 (3 6) =30, OEN = 27
8355 22:56:17.039222 24, 0x0, End_B0=24 End_B1=24
8356 22:56:17.042425 25, 0x0, End_B0=25 End_B1=25
8357 22:56:17.045725 26, 0x0, End_B0=26 End_B1=26
8358 22:56:17.049008 27, 0x0, End_B0=27 End_B1=27
8359 22:56:17.049123 28, 0x0, End_B0=28 End_B1=28
8360 22:56:17.052121 29, 0x0, End_B0=29 End_B1=29
8361 22:56:17.055781 30, 0x0, End_B0=30 End_B1=30
8362 22:56:17.058502 31, 0x4141, End_B0=30 End_B1=30
8363 22:56:17.062244 Byte0 end_step=30 best_step=27
8364 22:56:17.065393 Byte1 end_step=30 best_step=27
8365 22:56:17.065506 Byte0 TX OE(2T, 0.5T) = (3, 3)
8366 22:56:17.068445 Byte1 TX OE(2T, 0.5T) = (3, 3)
8367 22:56:17.068585
8368 22:56:17.068650
8369 22:56:17.078672 [DQSOSCAuto] RK1, (LSB)MR18= 0x2003, (MSB)MR19= 0x303, tDQSOscB0 = 408 ps tDQSOscB1 = 393 ps
8370 22:56:17.081869 CH0 RK1: MR19=303, MR18=2003
8371 22:56:17.085348 CH0_RK1: MR19=0x303, MR18=0x2003, DQSOSC=393, MR23=63, INC=23, DEC=15
8372 22:56:17.088332 [RxdqsGatingPostProcess] freq 1600
8373 22:56:17.095105 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8374 22:56:17.098790 best DQS0 dly(2T, 0.5T) = (1, 1)
8375 22:56:17.102041 best DQS1 dly(2T, 0.5T) = (1, 1)
8376 22:56:17.105120 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8377 22:56:17.108121 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8378 22:56:17.111790 best DQS0 dly(2T, 0.5T) = (1, 1)
8379 22:56:17.115153 best DQS1 dly(2T, 0.5T) = (1, 1)
8380 22:56:17.118192 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8381 22:56:17.118314 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8382 22:56:17.121376 Pre-setting of DQS Precalculation
8383 22:56:17.128238 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8384 22:56:17.128373 ==
8385 22:56:17.131373 Dram Type= 6, Freq= 0, CH_1, rank 0
8386 22:56:17.134868 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8387 22:56:17.135025 ==
8388 22:56:17.141169 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8389 22:56:17.144804 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8390 22:56:17.148184 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8391 22:56:17.154399 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8392 22:56:17.164434 [CA 0] Center 42 (13~71) winsize 59
8393 22:56:17.167126 [CA 1] Center 42 (12~72) winsize 61
8394 22:56:17.170951 [CA 2] Center 37 (8~66) winsize 59
8395 22:56:17.174288 [CA 3] Center 35 (6~65) winsize 60
8396 22:56:17.177693 [CA 4] Center 37 (8~66) winsize 59
8397 22:56:17.181168 [CA 5] Center 36 (6~66) winsize 61
8398 22:56:17.181318
8399 22:56:17.184191 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8400 22:56:17.184314
8401 22:56:17.187493 [CATrainingPosCal] consider 1 rank data
8402 22:56:17.190298 u2DelayCellTimex100 = 262/100 ps
8403 22:56:17.193877 CA0 delay=42 (13~71),Diff = 7 PI (26 cell)
8404 22:56:17.200498 CA1 delay=42 (12~72),Diff = 7 PI (26 cell)
8405 22:56:17.203816 CA2 delay=37 (8~66),Diff = 2 PI (7 cell)
8406 22:56:17.207438 CA3 delay=35 (6~65),Diff = 0 PI (0 cell)
8407 22:56:17.210486 CA4 delay=37 (8~66),Diff = 2 PI (7 cell)
8408 22:56:17.213719 CA5 delay=36 (6~66),Diff = 1 PI (3 cell)
8409 22:56:17.213814
8410 22:56:17.217609 CA PerBit enable=1, Macro0, CA PI delay=35
8411 22:56:17.217726
8412 22:56:17.220419 [CBTSetCACLKResult] CA Dly = 35
8413 22:56:17.224121 CS Dly: 10 (0~41)
8414 22:56:17.226789 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8415 22:56:17.230495 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8416 22:56:17.230578 ==
8417 22:56:17.233717 Dram Type= 6, Freq= 0, CH_1, rank 1
8418 22:56:17.236787 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8419 22:56:17.240013 ==
8420 22:56:17.243332 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8421 22:56:17.246789 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8422 22:56:17.253143 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8423 22:56:17.259935 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8424 22:56:17.267398 [CA 0] Center 41 (12~71) winsize 60
8425 22:56:17.270820 [CA 1] Center 42 (13~72) winsize 60
8426 22:56:17.274244 [CA 2] Center 37 (8~67) winsize 60
8427 22:56:17.277466 [CA 3] Center 37 (7~67) winsize 61
8428 22:56:17.280943 [CA 4] Center 37 (7~67) winsize 61
8429 22:56:17.284034 [CA 5] Center 37 (8~66) winsize 59
8430 22:56:17.284118
8431 22:56:17.287457 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8432 22:56:17.287541
8433 22:56:17.290274 [CATrainingPosCal] consider 2 rank data
8434 22:56:17.293602 u2DelayCellTimex100 = 262/100 ps
8435 22:56:17.300147 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8436 22:56:17.303484 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8437 22:56:17.306725 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8438 22:56:17.310391 CA3 delay=36 (7~65),Diff = 0 PI (0 cell)
8439 22:56:17.313574 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8440 22:56:17.316863 CA5 delay=37 (8~66),Diff = 1 PI (3 cell)
8441 22:56:17.316967
8442 22:56:17.320238 CA PerBit enable=1, Macro0, CA PI delay=36
8443 22:56:17.320324
8444 22:56:17.323392 [CBTSetCACLKResult] CA Dly = 36
8445 22:56:17.326636 CS Dly: 11 (0~43)
8446 22:56:17.330570 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8447 22:56:17.333293 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8448 22:56:17.333395
8449 22:56:17.336730 ----->DramcWriteLeveling(PI) begin...
8450 22:56:17.336814 ==
8451 22:56:17.339783 Dram Type= 6, Freq= 0, CH_1, rank 0
8452 22:56:17.346089 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8453 22:56:17.346176 ==
8454 22:56:17.349569 Write leveling (Byte 0): 23 => 23
8455 22:56:17.353172 Write leveling (Byte 1): 26 => 26
8456 22:56:17.353258 DramcWriteLeveling(PI) end<-----
8457 22:56:17.356305
8458 22:56:17.356388 ==
8459 22:56:17.359805 Dram Type= 6, Freq= 0, CH_1, rank 0
8460 22:56:17.363293 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8461 22:56:17.363389 ==
8462 22:56:17.365998 [Gating] SW mode calibration
8463 22:56:17.372745 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8464 22:56:17.376027 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8465 22:56:17.382872 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8466 22:56:17.385947 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8467 22:56:17.389545 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8468 22:56:17.395896 1 4 12 | B1->B0 | 2928 3232 | 1 1 | (1 0) (0 0)
8469 22:56:17.399395 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8470 22:56:17.402916 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8471 22:56:17.409696 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8472 22:56:17.412721 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8473 22:56:17.416060 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8474 22:56:17.422865 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8475 22:56:17.425860 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 1)
8476 22:56:17.429150 1 5 12 | B1->B0 | 3131 2323 | 1 0 | (1 0) (1 0)
8477 22:56:17.435653 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8478 22:56:17.438794 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8479 22:56:17.442643 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8480 22:56:17.448893 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8481 22:56:17.452183 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8482 22:56:17.455716 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8483 22:56:17.462326 1 6 8 | B1->B0 | 2323 2525 | 0 1 | (0 0) (1 1)
8484 22:56:17.464914 1 6 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
8485 22:56:17.468653 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8486 22:56:17.475040 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8487 22:56:17.478317 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8488 22:56:17.481889 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8489 22:56:17.488103 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8490 22:56:17.491291 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8491 22:56:17.494666 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8492 22:56:17.501166 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8493 22:56:17.504323 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8494 22:56:17.510875 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8495 22:56:17.514267 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8496 22:56:17.517959 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8497 22:56:17.524141 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8498 22:56:17.527845 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8499 22:56:17.530925 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8500 22:56:17.537395 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8501 22:56:17.540533 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8502 22:56:17.543704 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8503 22:56:17.550733 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8504 22:56:17.553684 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8505 22:56:17.557532 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8506 22:56:17.563773 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8507 22:56:17.566945 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8508 22:56:17.570583 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8509 22:56:17.573796 Total UI for P1: 0, mck2ui 16
8510 22:56:17.577141 best dqsien dly found for B0: ( 1, 9, 8)
8511 22:56:17.580291 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8512 22:56:17.583971 Total UI for P1: 0, mck2ui 16
8513 22:56:17.586788 best dqsien dly found for B1: ( 1, 9, 10)
8514 22:56:17.593448 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8515 22:56:17.596663 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8516 22:56:17.596772
8517 22:56:17.600266 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8518 22:56:17.603339 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8519 22:56:17.606838 [Gating] SW calibration Done
8520 22:56:17.606921 ==
8521 22:56:17.609906 Dram Type= 6, Freq= 0, CH_1, rank 0
8522 22:56:17.613158 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8523 22:56:17.613241 ==
8524 22:56:17.616465 RX Vref Scan: 0
8525 22:56:17.616573
8526 22:56:17.616652 RX Vref 0 -> 0, step: 1
8527 22:56:17.616713
8528 22:56:17.620372 RX Delay 0 -> 252, step: 8
8529 22:56:17.623676 iDelay=208, Bit 0, Center 143 (88 ~ 199) 112
8530 22:56:17.629866 iDelay=208, Bit 1, Center 131 (80 ~ 183) 104
8531 22:56:17.633543 iDelay=208, Bit 2, Center 127 (72 ~ 183) 112
8532 22:56:17.636341 iDelay=208, Bit 3, Center 139 (88 ~ 191) 104
8533 22:56:17.639878 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8534 22:56:17.643018 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8535 22:56:17.649434 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8536 22:56:17.653187 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8537 22:56:17.656813 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8538 22:56:17.659396 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8539 22:56:17.662798 iDelay=208, Bit 10, Center 131 (80 ~ 183) 104
8540 22:56:17.669412 iDelay=208, Bit 11, Center 123 (72 ~ 175) 104
8541 22:56:17.672938 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8542 22:56:17.676108 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8543 22:56:17.679594 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8544 22:56:17.682508 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8545 22:56:17.686055 ==
8546 22:56:17.689360 Dram Type= 6, Freq= 0, CH_1, rank 0
8547 22:56:17.692531 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8548 22:56:17.692628 ==
8549 22:56:17.692693 DQS Delay:
8550 22:56:17.695975 DQS0 = 0, DQS1 = 0
8551 22:56:17.696057 DQM Delay:
8552 22:56:17.699490 DQM0 = 138, DQM1 = 130
8553 22:56:17.699587 DQ Delay:
8554 22:56:17.702334 DQ0 =143, DQ1 =131, DQ2 =127, DQ3 =139
8555 22:56:17.706225 DQ4 =135, DQ5 =151, DQ6 =143, DQ7 =135
8556 22:56:17.709163 DQ8 =119, DQ9 =115, DQ10 =131, DQ11 =123
8557 22:56:17.712175 DQ12 =135, DQ13 =139, DQ14 =135, DQ15 =143
8558 22:56:17.712256
8559 22:56:17.712320
8560 22:56:17.712378 ==
8561 22:56:17.715970 Dram Type= 6, Freq= 0, CH_1, rank 0
8562 22:56:17.722319 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8563 22:56:17.722402 ==
8564 22:56:17.722465
8565 22:56:17.722524
8566 22:56:17.725583 TX Vref Scan disable
8567 22:56:17.725665 == TX Byte 0 ==
8568 22:56:17.728928 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8569 22:56:17.735467 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8570 22:56:17.735551 == TX Byte 1 ==
8571 22:56:17.738825 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8572 22:56:17.745158 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8573 22:56:17.745271 ==
8574 22:56:17.748375 Dram Type= 6, Freq= 0, CH_1, rank 0
8575 22:56:17.751769 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8576 22:56:17.751854 ==
8577 22:56:17.764923
8578 22:56:17.768045 TX Vref early break, caculate TX vref
8579 22:56:17.771644 TX Vref=16, minBit 0, minWin=21, winSum=372
8580 22:56:17.774866 TX Vref=18, minBit 0, minWin=22, winSum=380
8581 22:56:17.778106 TX Vref=20, minBit 0, minWin=23, winSum=393
8582 22:56:17.781818 TX Vref=22, minBit 0, minWin=23, winSum=401
8583 22:56:17.784480 TX Vref=24, minBit 5, minWin=23, winSum=409
8584 22:56:17.791267 TX Vref=26, minBit 0, minWin=24, winSum=416
8585 22:56:17.795082 TX Vref=28, minBit 0, minWin=24, winSum=418
8586 22:56:17.797839 TX Vref=30, minBit 5, minWin=24, winSum=414
8587 22:56:17.801165 TX Vref=32, minBit 0, minWin=23, winSum=401
8588 22:56:17.804912 TX Vref=34, minBit 0, minWin=23, winSum=396
8589 22:56:17.810975 [TxChooseVref] Worse bit 0, Min win 24, Win sum 418, Final Vref 28
8590 22:56:17.811076
8591 22:56:17.814125 Final TX Range 0 Vref 28
8592 22:56:17.814208
8593 22:56:17.814272 ==
8594 22:56:17.818183 Dram Type= 6, Freq= 0, CH_1, rank 0
8595 22:56:17.820839 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8596 22:56:17.820922 ==
8597 22:56:17.820988
8598 22:56:17.821047
8599 22:56:17.824120 TX Vref Scan disable
8600 22:56:17.830687 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8601 22:56:17.830799 == TX Byte 0 ==
8602 22:56:17.834460 u2DelayCellOfst[0]=14 cells (4 PI)
8603 22:56:17.837185 u2DelayCellOfst[1]=11 cells (3 PI)
8604 22:56:17.841032 u2DelayCellOfst[2]=0 cells (0 PI)
8605 22:56:17.843995 u2DelayCellOfst[3]=3 cells (1 PI)
8606 22:56:17.847337 u2DelayCellOfst[4]=7 cells (2 PI)
8607 22:56:17.850762 u2DelayCellOfst[5]=18 cells (5 PI)
8608 22:56:17.853762 u2DelayCellOfst[6]=18 cells (5 PI)
8609 22:56:17.857676 u2DelayCellOfst[7]=3 cells (1 PI)
8610 22:56:17.860133 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8611 22:56:17.863765 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8612 22:56:17.867146 == TX Byte 1 ==
8613 22:56:17.870540 u2DelayCellOfst[8]=0 cells (0 PI)
8614 22:56:17.870651 u2DelayCellOfst[9]=3 cells (1 PI)
8615 22:56:17.873880 u2DelayCellOfst[10]=11 cells (3 PI)
8616 22:56:17.877020 u2DelayCellOfst[11]=3 cells (1 PI)
8617 22:56:17.880198 u2DelayCellOfst[12]=14 cells (4 PI)
8618 22:56:17.883993 u2DelayCellOfst[13]=18 cells (5 PI)
8619 22:56:17.886992 u2DelayCellOfst[14]=18 cells (5 PI)
8620 22:56:17.890282 u2DelayCellOfst[15]=18 cells (5 PI)
8621 22:56:17.893766 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8622 22:56:17.900429 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8623 22:56:17.900573 DramC Write-DBI on
8624 22:56:17.900655 ==
8625 22:56:17.903733 Dram Type= 6, Freq= 0, CH_1, rank 0
8626 22:56:17.910473 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8627 22:56:17.910560 ==
8628 22:56:17.910626
8629 22:56:17.910686
8630 22:56:17.910744 TX Vref Scan disable
8631 22:56:17.914309 == TX Byte 0 ==
8632 22:56:17.917328 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8633 22:56:17.920509 == TX Byte 1 ==
8634 22:56:17.924317 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8635 22:56:17.927722 DramC Write-DBI off
8636 22:56:17.927833
8637 22:56:17.927900 [DATLAT]
8638 22:56:17.927962 Freq=1600, CH1 RK0
8639 22:56:17.928034
8640 22:56:17.930566 DATLAT Default: 0xf
8641 22:56:17.930668 0, 0xFFFF, sum = 0
8642 22:56:17.934022 1, 0xFFFF, sum = 0
8643 22:56:17.936959 2, 0xFFFF, sum = 0
8644 22:56:17.937042 3, 0xFFFF, sum = 0
8645 22:56:17.940512 4, 0xFFFF, sum = 0
8646 22:56:17.940632 5, 0xFFFF, sum = 0
8647 22:56:17.943896 6, 0xFFFF, sum = 0
8648 22:56:17.944003 7, 0xFFFF, sum = 0
8649 22:56:17.947167 8, 0xFFFF, sum = 0
8650 22:56:17.947251 9, 0xFFFF, sum = 0
8651 22:56:17.950439 10, 0xFFFF, sum = 0
8652 22:56:17.950522 11, 0xFFFF, sum = 0
8653 22:56:17.953699 12, 0xFFFF, sum = 0
8654 22:56:17.953784 13, 0xFFFF, sum = 0
8655 22:56:17.957125 14, 0x0, sum = 1
8656 22:56:17.957208 15, 0x0, sum = 2
8657 22:56:17.960912 16, 0x0, sum = 3
8658 22:56:17.960996 17, 0x0, sum = 4
8659 22:56:17.963611 best_step = 15
8660 22:56:17.963693
8661 22:56:17.963757 ==
8662 22:56:17.966728 Dram Type= 6, Freq= 0, CH_1, rank 0
8663 22:56:17.970225 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8664 22:56:17.970307 ==
8665 22:56:17.973748 RX Vref Scan: 1
8666 22:56:17.973829
8667 22:56:17.973894 Set Vref Range= 24 -> 127
8668 22:56:17.973956
8669 22:56:17.977154 RX Vref 24 -> 127, step: 1
8670 22:56:17.977236
8671 22:56:17.980239 RX Delay 11 -> 252, step: 4
8672 22:56:17.980321
8673 22:56:17.983398 Set Vref, RX VrefLevel [Byte0]: 24
8674 22:56:17.986828 [Byte1]: 24
8675 22:56:17.986910
8676 22:56:17.990207 Set Vref, RX VrefLevel [Byte0]: 25
8677 22:56:17.993469 [Byte1]: 25
8678 22:56:17.996860
8679 22:56:17.996942 Set Vref, RX VrefLevel [Byte0]: 26
8680 22:56:18.000211 [Byte1]: 26
8681 22:56:18.004621
8682 22:56:18.004704 Set Vref, RX VrefLevel [Byte0]: 27
8683 22:56:18.007766 [Byte1]: 27
8684 22:56:18.011892
8685 22:56:18.012000 Set Vref, RX VrefLevel [Byte0]: 28
8686 22:56:18.015371 [Byte1]: 28
8687 22:56:18.019592
8688 22:56:18.019708 Set Vref, RX VrefLevel [Byte0]: 29
8689 22:56:18.023132 [Byte1]: 29
8690 22:56:18.027389
8691 22:56:18.027503 Set Vref, RX VrefLevel [Byte0]: 30
8692 22:56:18.030456 [Byte1]: 30
8693 22:56:18.034745
8694 22:56:18.034830 Set Vref, RX VrefLevel [Byte0]: 31
8695 22:56:18.038022 [Byte1]: 31
8696 22:56:18.043080
8697 22:56:18.043164 Set Vref, RX VrefLevel [Byte0]: 32
8698 22:56:18.046083 [Byte1]: 32
8699 22:56:18.050098
8700 22:56:18.050180 Set Vref, RX VrefLevel [Byte0]: 33
8701 22:56:18.053767 [Byte1]: 33
8702 22:56:18.057967
8703 22:56:18.058051 Set Vref, RX VrefLevel [Byte0]: 34
8704 22:56:18.060916 [Byte1]: 34
8705 22:56:18.065778
8706 22:56:18.065878 Set Vref, RX VrefLevel [Byte0]: 35
8707 22:56:18.068754 [Byte1]: 35
8708 22:56:18.072890
8709 22:56:18.073058 Set Vref, RX VrefLevel [Byte0]: 36
8710 22:56:18.076227 [Byte1]: 36
8711 22:56:18.080350
8712 22:56:18.080426 Set Vref, RX VrefLevel [Byte0]: 37
8713 22:56:18.084022 [Byte1]: 37
8714 22:56:18.088137
8715 22:56:18.088228 Set Vref, RX VrefLevel [Byte0]: 38
8716 22:56:18.091318 [Byte1]: 38
8717 22:56:18.095584
8718 22:56:18.095658 Set Vref, RX VrefLevel [Byte0]: 39
8719 22:56:18.098954 [Byte1]: 39
8720 22:56:18.103655
8721 22:56:18.103736 Set Vref, RX VrefLevel [Byte0]: 40
8722 22:56:18.107281 [Byte1]: 40
8723 22:56:18.110926
8724 22:56:18.111009 Set Vref, RX VrefLevel [Byte0]: 41
8725 22:56:18.114376 [Byte1]: 41
8726 22:56:18.118772
8727 22:56:18.118906 Set Vref, RX VrefLevel [Byte0]: 42
8728 22:56:18.122053 [Byte1]: 42
8729 22:56:18.126075
8730 22:56:18.126149 Set Vref, RX VrefLevel [Byte0]: 43
8731 22:56:18.129626 [Byte1]: 43
8732 22:56:18.133879
8733 22:56:18.133954 Set Vref, RX VrefLevel [Byte0]: 44
8734 22:56:18.136967 [Byte1]: 44
8735 22:56:18.141803
8736 22:56:18.141929 Set Vref, RX VrefLevel [Byte0]: 45
8737 22:56:18.144761 [Byte1]: 45
8738 22:56:18.149142
8739 22:56:18.149227 Set Vref, RX VrefLevel [Byte0]: 46
8740 22:56:18.152432 [Byte1]: 46
8741 22:56:18.156449
8742 22:56:18.156565 Set Vref, RX VrefLevel [Byte0]: 47
8743 22:56:18.160137 [Byte1]: 47
8744 22:56:18.164511
8745 22:56:18.164604 Set Vref, RX VrefLevel [Byte0]: 48
8746 22:56:18.167896 [Byte1]: 48
8747 22:56:18.171781
8748 22:56:18.171892 Set Vref, RX VrefLevel [Byte0]: 49
8749 22:56:18.175045 [Byte1]: 49
8750 22:56:18.179368
8751 22:56:18.179453 Set Vref, RX VrefLevel [Byte0]: 50
8752 22:56:18.182656 [Byte1]: 50
8753 22:56:18.187090
8754 22:56:18.187179 Set Vref, RX VrefLevel [Byte0]: 51
8755 22:56:18.190487 [Byte1]: 51
8756 22:56:18.194656
8757 22:56:18.194742 Set Vref, RX VrefLevel [Byte0]: 52
8758 22:56:18.198138 [Byte1]: 52
8759 22:56:18.202187
8760 22:56:18.202275 Set Vref, RX VrefLevel [Byte0]: 53
8761 22:56:18.205461 [Byte1]: 53
8762 22:56:18.210213
8763 22:56:18.210298 Set Vref, RX VrefLevel [Byte0]: 54
8764 22:56:18.213713 [Byte1]: 54
8765 22:56:18.217634
8766 22:56:18.217719 Set Vref, RX VrefLevel [Byte0]: 55
8767 22:56:18.221248 [Byte1]: 55
8768 22:56:18.225209
8769 22:56:18.225295 Set Vref, RX VrefLevel [Byte0]: 56
8770 22:56:18.228563 [Byte1]: 56
8771 22:56:18.232817
8772 22:56:18.232902 Set Vref, RX VrefLevel [Byte0]: 57
8773 22:56:18.236111 [Byte1]: 57
8774 22:56:18.240685
8775 22:56:18.240795 Set Vref, RX VrefLevel [Byte0]: 58
8776 22:56:18.243915 [Byte1]: 58
8777 22:56:18.248136
8778 22:56:18.248219 Set Vref, RX VrefLevel [Byte0]: 59
8779 22:56:18.251353 [Byte1]: 59
8780 22:56:18.255724
8781 22:56:18.255834 Set Vref, RX VrefLevel [Byte0]: 60
8782 22:56:18.258725 [Byte1]: 60
8783 22:56:18.263461
8784 22:56:18.263544 Set Vref, RX VrefLevel [Byte0]: 61
8785 22:56:18.266913 [Byte1]: 61
8786 22:56:18.271088
8787 22:56:18.271171 Set Vref, RX VrefLevel [Byte0]: 62
8788 22:56:18.274280 [Byte1]: 62
8789 22:56:18.278782
8790 22:56:18.278865 Set Vref, RX VrefLevel [Byte0]: 63
8791 22:56:18.281848 [Byte1]: 63
8792 22:56:18.286298
8793 22:56:18.286396 Set Vref, RX VrefLevel [Byte0]: 64
8794 22:56:18.289332 [Byte1]: 64
8795 22:56:18.294226
8796 22:56:18.294309 Set Vref, RX VrefLevel [Byte0]: 65
8797 22:56:18.297429 [Byte1]: 65
8798 22:56:18.301322
8799 22:56:18.301407 Set Vref, RX VrefLevel [Byte0]: 66
8800 22:56:18.304629 [Byte1]: 66
8801 22:56:18.308833
8802 22:56:18.308916 Set Vref, RX VrefLevel [Byte0]: 67
8803 22:56:18.312650 [Byte1]: 67
8804 22:56:18.316395
8805 22:56:18.316480 Set Vref, RX VrefLevel [Byte0]: 68
8806 22:56:18.319655 [Byte1]: 68
8807 22:56:18.324846
8808 22:56:18.324923 Set Vref, RX VrefLevel [Byte0]: 69
8809 22:56:18.327757 [Byte1]: 69
8810 22:56:18.332242
8811 22:56:18.332379 Set Vref, RX VrefLevel [Byte0]: 70
8812 22:56:18.335207 [Byte1]: 70
8813 22:56:18.339204
8814 22:56:18.339277 Set Vref, RX VrefLevel [Byte0]: 71
8815 22:56:18.342754 [Byte1]: 71
8816 22:56:18.347101
8817 22:56:18.347202 Final RX Vref Byte 0 = 54 to rank0
8818 22:56:18.350675 Final RX Vref Byte 1 = 59 to rank0
8819 22:56:18.353483 Final RX Vref Byte 0 = 54 to rank1
8820 22:56:18.356855 Final RX Vref Byte 1 = 59 to rank1==
8821 22:56:18.360135 Dram Type= 6, Freq= 0, CH_1, rank 0
8822 22:56:18.366564 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8823 22:56:18.366649 ==
8824 22:56:18.366730 DQS Delay:
8825 22:56:18.370075 DQS0 = 0, DQS1 = 0
8826 22:56:18.370187 DQM Delay:
8827 22:56:18.372958 DQM0 = 135, DQM1 = 129
8828 22:56:18.373040 DQ Delay:
8829 22:56:18.376828 DQ0 =142, DQ1 =128, DQ2 =124, DQ3 =132
8830 22:56:18.379974 DQ4 =132, DQ5 =148, DQ6 =144, DQ7 =130
8831 22:56:18.382893 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =120
8832 22:56:18.386417 DQ12 =138, DQ13 =138, DQ14 =138, DQ15 =138
8833 22:56:18.386514
8834 22:56:18.386579
8835 22:56:18.386639
8836 22:56:18.389928 [DramC_TX_OE_Calibration] TA2
8837 22:56:18.393168 Original DQ_B0 (3 6) =30, OEN = 27
8838 22:56:18.396024 Original DQ_B1 (3 6) =30, OEN = 27
8839 22:56:18.399942 24, 0x0, End_B0=24 End_B1=24
8840 22:56:18.403212 25, 0x0, End_B0=25 End_B1=25
8841 22:56:18.403298 26, 0x0, End_B0=26 End_B1=26
8842 22:56:18.406450 27, 0x0, End_B0=27 End_B1=27
8843 22:56:18.409164 28, 0x0, End_B0=28 End_B1=28
8844 22:56:18.412445 29, 0x0, End_B0=29 End_B1=29
8845 22:56:18.415811 30, 0x0, End_B0=30 End_B1=30
8846 22:56:18.415895 31, 0x4141, End_B0=30 End_B1=30
8847 22:56:18.419127 Byte0 end_step=30 best_step=27
8848 22:56:18.422527 Byte1 end_step=30 best_step=27
8849 22:56:18.426010 Byte0 TX OE(2T, 0.5T) = (3, 3)
8850 22:56:18.429227 Byte1 TX OE(2T, 0.5T) = (3, 3)
8851 22:56:18.429310
8852 22:56:18.429375
8853 22:56:18.435708 [DQSOSCAuto] RK0, (LSB)MR18= 0x180e, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 397 ps
8854 22:56:18.439284 CH1 RK0: MR19=303, MR18=180E
8855 22:56:18.445868 CH1_RK0: MR19=0x303, MR18=0x180E, DQSOSC=397, MR23=63, INC=23, DEC=15
8856 22:56:18.445954
8857 22:56:18.449480 ----->DramcWriteLeveling(PI) begin...
8858 22:56:18.449565 ==
8859 22:56:18.452239 Dram Type= 6, Freq= 0, CH_1, rank 1
8860 22:56:18.455870 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8861 22:56:18.455954 ==
8862 22:56:18.459031 Write leveling (Byte 0): 24 => 24
8863 22:56:18.462582 Write leveling (Byte 1): 27 => 27
8864 22:56:18.465561 DramcWriteLeveling(PI) end<-----
8865 22:56:18.465650
8866 22:56:18.465720 ==
8867 22:56:18.468977 Dram Type= 6, Freq= 0, CH_1, rank 1
8868 22:56:18.475728 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8869 22:56:18.475814 ==
8870 22:56:18.475880 [Gating] SW mode calibration
8871 22:56:18.485215 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8872 22:56:18.488938 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8873 22:56:18.492075 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8874 22:56:18.498792 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8875 22:56:18.501981 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8876 22:56:18.505207 1 4 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
8877 22:56:18.511679 1 4 16 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
8878 22:56:18.515801 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8879 22:56:18.518540 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8880 22:56:18.525119 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8881 22:56:18.528379 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8882 22:56:18.531297 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8883 22:56:18.538607 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8884 22:56:18.541532 1 5 12 | B1->B0 | 2727 3434 | 0 1 | (1 0) (1 0)
8885 22:56:18.544674 1 5 16 | B1->B0 | 2323 2525 | 0 0 | (0 0) (1 0)
8886 22:56:18.551401 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8887 22:56:18.554870 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8888 22:56:18.558041 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8889 22:56:18.564459 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8890 22:56:18.568447 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8891 22:56:18.571646 1 6 8 | B1->B0 | 3232 2323 | 0 0 | (0 0) (0 0)
8892 22:56:18.578202 1 6 12 | B1->B0 | 4646 2a2a | 0 0 | (0 0) (1 1)
8893 22:56:18.581133 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8894 22:56:18.584506 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8895 22:56:18.591337 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8896 22:56:18.594705 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8897 22:56:18.597658 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8898 22:56:18.604549 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8899 22:56:18.607792 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8900 22:56:18.610911 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8901 22:56:18.617368 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8902 22:56:18.620999 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8903 22:56:18.623796 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8904 22:56:18.630650 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8905 22:56:18.634059 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8906 22:56:18.637532 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8907 22:56:18.643998 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8908 22:56:18.646893 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8909 22:56:18.650517 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8910 22:56:18.656959 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8911 22:56:18.660475 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8912 22:56:18.663787 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8913 22:56:18.670797 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8914 22:56:18.673727 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8915 22:56:18.677017 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8916 22:56:18.683651 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8917 22:56:18.687079 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8918 22:56:18.690104 Total UI for P1: 0, mck2ui 16
8919 22:56:18.693574 best dqsien dly found for B0: ( 1, 9, 10)
8920 22:56:18.696620 Total UI for P1: 0, mck2ui 16
8921 22:56:18.700339 best dqsien dly found for B1: ( 1, 9, 10)
8922 22:56:18.703527 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8923 22:56:18.706783 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8924 22:56:18.706865
8925 22:56:18.709828 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8926 22:56:18.713080 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8927 22:56:18.716301 [Gating] SW calibration Done
8928 22:56:18.716409 ==
8929 22:56:18.720239 Dram Type= 6, Freq= 0, CH_1, rank 1
8930 22:56:18.726267 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8931 22:56:18.726350 ==
8932 22:56:18.726414 RX Vref Scan: 0
8933 22:56:18.726474
8934 22:56:18.729777 RX Vref 0 -> 0, step: 1
8935 22:56:18.729858
8936 22:56:18.733493 RX Delay 0 -> 252, step: 8
8937 22:56:18.736204 iDelay=208, Bit 0, Center 139 (80 ~ 199) 120
8938 22:56:18.739971 iDelay=208, Bit 1, Center 131 (72 ~ 191) 120
8939 22:56:18.743238 iDelay=208, Bit 2, Center 123 (64 ~ 183) 120
8940 22:56:18.746123 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8941 22:56:18.753002 iDelay=208, Bit 4, Center 135 (72 ~ 199) 128
8942 22:56:18.756167 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8943 22:56:18.759198 iDelay=208, Bit 6, Center 147 (88 ~ 207) 120
8944 22:56:18.762844 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8945 22:56:18.765848 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8946 22:56:18.772825 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8947 22:56:18.775915 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8948 22:56:18.779071 iDelay=208, Bit 11, Center 119 (64 ~ 175) 112
8949 22:56:18.782599 iDelay=208, Bit 12, Center 139 (80 ~ 199) 120
8950 22:56:18.789139 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8951 22:56:18.792424 iDelay=208, Bit 14, Center 135 (72 ~ 199) 128
8952 22:56:18.795607 iDelay=208, Bit 15, Center 139 (80 ~ 199) 120
8953 22:56:18.795719 ==
8954 22:56:18.798800 Dram Type= 6, Freq= 0, CH_1, rank 1
8955 22:56:18.802202 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8956 22:56:18.802290 ==
8957 22:56:18.805883 DQS Delay:
8958 22:56:18.805966 DQS0 = 0, DQS1 = 0
8959 22:56:18.809202 DQM Delay:
8960 22:56:18.809312 DQM0 = 136, DQM1 = 129
8961 22:56:18.812471 DQ Delay:
8962 22:56:18.815665 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8963 22:56:18.818757 DQ4 =135, DQ5 =147, DQ6 =147, DQ7 =135
8964 22:56:18.822124 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8965 22:56:18.825170 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8966 22:56:18.825247
8967 22:56:18.825308
8968 22:56:18.825366 ==
8969 22:56:18.828782 Dram Type= 6, Freq= 0, CH_1, rank 1
8970 22:56:18.832166 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8971 22:56:18.832311 ==
8972 22:56:18.832428
8973 22:56:18.832526
8974 22:56:18.835021 TX Vref Scan disable
8975 22:56:18.838832 == TX Byte 0 ==
8976 22:56:18.842173 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8977 22:56:18.845362 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8978 22:56:18.848402 == TX Byte 1 ==
8979 22:56:18.852159 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8980 22:56:18.855763 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8981 22:56:18.855870 ==
8982 22:56:18.858381 Dram Type= 6, Freq= 0, CH_1, rank 1
8983 22:56:18.864815 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8984 22:56:18.864898 ==
8985 22:56:18.876699
8986 22:56:18.880094 TX Vref early break, caculate TX vref
8987 22:56:18.883613 TX Vref=16, minBit 0, minWin=21, winSum=381
8988 22:56:18.886829 TX Vref=18, minBit 0, minWin=22, winSum=393
8989 22:56:18.890248 TX Vref=20, minBit 6, minWin=23, winSum=400
8990 22:56:18.893030 TX Vref=22, minBit 1, minWin=24, winSum=406
8991 22:56:18.896566 TX Vref=24, minBit 0, minWin=25, winSum=419
8992 22:56:18.902941 TX Vref=26, minBit 0, minWin=25, winSum=419
8993 22:56:18.906437 TX Vref=28, minBit 0, minWin=24, winSum=420
8994 22:56:18.910008 TX Vref=30, minBit 0, minWin=24, winSum=414
8995 22:56:18.912960 TX Vref=32, minBit 0, minWin=24, winSum=406
8996 22:56:18.916167 TX Vref=34, minBit 0, minWin=21, winSum=394
8997 22:56:18.922870 [TxChooseVref] Worse bit 0, Min win 25, Win sum 419, Final Vref 24
8998 22:56:18.922960
8999 22:56:18.926142 Final TX Range 0 Vref 24
9000 22:56:18.926225
9001 22:56:18.926290 ==
9002 22:56:18.929318 Dram Type= 6, Freq= 0, CH_1, rank 1
9003 22:56:18.932540 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9004 22:56:18.932640 ==
9005 22:56:18.932706
9006 22:56:18.932766
9007 22:56:18.936066 TX Vref Scan disable
9008 22:56:18.942684 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
9009 22:56:18.942786 == TX Byte 0 ==
9010 22:56:18.945929 u2DelayCellOfst[0]=18 cells (5 PI)
9011 22:56:18.949392 u2DelayCellOfst[1]=14 cells (4 PI)
9012 22:56:18.952647 u2DelayCellOfst[2]=0 cells (0 PI)
9013 22:56:18.955764 u2DelayCellOfst[3]=3 cells (1 PI)
9014 22:56:18.959266 u2DelayCellOfst[4]=7 cells (2 PI)
9015 22:56:18.962563 u2DelayCellOfst[5]=18 cells (5 PI)
9016 22:56:18.965548 u2DelayCellOfst[6]=18 cells (5 PI)
9017 22:56:18.969040 u2DelayCellOfst[7]=3 cells (1 PI)
9018 22:56:18.972172 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
9019 22:56:18.975305 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
9020 22:56:18.978890 == TX Byte 1 ==
9021 22:56:18.981865 u2DelayCellOfst[8]=0 cells (0 PI)
9022 22:56:18.985218 u2DelayCellOfst[9]=3 cells (1 PI)
9023 22:56:18.988885 u2DelayCellOfst[10]=11 cells (3 PI)
9024 22:56:18.988968 u2DelayCellOfst[11]=7 cells (2 PI)
9025 22:56:18.992425 u2DelayCellOfst[12]=14 cells (4 PI)
9026 22:56:18.995096 u2DelayCellOfst[13]=14 cells (4 PI)
9027 22:56:18.998592 u2DelayCellOfst[14]=18 cells (5 PI)
9028 22:56:19.002201 u2DelayCellOfst[15]=18 cells (5 PI)
9029 22:56:19.008426 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
9030 22:56:19.011721 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
9031 22:56:19.011807 DramC Write-DBI on
9032 22:56:19.011872 ==
9033 22:56:19.014926 Dram Type= 6, Freq= 0, CH_1, rank 1
9034 22:56:19.021728 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9035 22:56:19.021829 ==
9036 22:56:19.021895
9037 22:56:19.021957
9038 22:56:19.024773 TX Vref Scan disable
9039 22:56:19.024856 == TX Byte 0 ==
9040 22:56:19.031604 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
9041 22:56:19.031721 == TX Byte 1 ==
9042 22:56:19.035000 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
9043 22:56:19.038156 DramC Write-DBI off
9044 22:56:19.038239
9045 22:56:19.038306 [DATLAT]
9046 22:56:19.042189 Freq=1600, CH1 RK1
9047 22:56:19.042298
9048 22:56:19.042392 DATLAT Default: 0xf
9049 22:56:19.044962 0, 0xFFFF, sum = 0
9050 22:56:19.045047 1, 0xFFFF, sum = 0
9051 22:56:19.048479 2, 0xFFFF, sum = 0
9052 22:56:19.048597 3, 0xFFFF, sum = 0
9053 22:56:19.051624 4, 0xFFFF, sum = 0
9054 22:56:19.051707 5, 0xFFFF, sum = 0
9055 22:56:19.055106 6, 0xFFFF, sum = 0
9056 22:56:19.055189 7, 0xFFFF, sum = 0
9057 22:56:19.058325 8, 0xFFFF, sum = 0
9058 22:56:19.058408 9, 0xFFFF, sum = 0
9059 22:56:19.061463 10, 0xFFFF, sum = 0
9060 22:56:19.064816 11, 0xFFFF, sum = 0
9061 22:56:19.064900 12, 0xFFFF, sum = 0
9062 22:56:19.067725 13, 0xFFFF, sum = 0
9063 22:56:19.067808 14, 0x0, sum = 1
9064 22:56:19.071607 15, 0x0, sum = 2
9065 22:56:19.071689 16, 0x0, sum = 3
9066 22:56:19.074355 17, 0x0, sum = 4
9067 22:56:19.074438 best_step = 15
9068 22:56:19.074503
9069 22:56:19.074562 ==
9070 22:56:19.078812 Dram Type= 6, Freq= 0, CH_1, rank 1
9071 22:56:19.081155 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9072 22:56:19.081238 ==
9073 22:56:19.084400 RX Vref Scan: 0
9074 22:56:19.084481
9075 22:56:19.087532 RX Vref 0 -> 0, step: 1
9076 22:56:19.087614
9077 22:56:19.087679 RX Delay 11 -> 252, step: 4
9078 22:56:19.094725 iDelay=203, Bit 0, Center 140 (87 ~ 194) 108
9079 22:56:19.098165 iDelay=203, Bit 1, Center 128 (75 ~ 182) 108
9080 22:56:19.101578 iDelay=203, Bit 2, Center 122 (67 ~ 178) 112
9081 22:56:19.104816 iDelay=203, Bit 3, Center 130 (79 ~ 182) 104
9082 22:56:19.111236 iDelay=203, Bit 4, Center 134 (79 ~ 190) 112
9083 22:56:19.114724 iDelay=203, Bit 5, Center 144 (91 ~ 198) 108
9084 22:56:19.117789 iDelay=203, Bit 6, Center 146 (91 ~ 202) 112
9085 22:56:19.121482 iDelay=203, Bit 7, Center 130 (79 ~ 182) 104
9086 22:56:19.124368 iDelay=203, Bit 8, Center 112 (55 ~ 170) 116
9087 22:56:19.131625 iDelay=203, Bit 9, Center 116 (63 ~ 170) 108
9088 22:56:19.134809 iDelay=203, Bit 10, Center 126 (71 ~ 182) 112
9089 22:56:19.138372 iDelay=203, Bit 11, Center 116 (63 ~ 170) 108
9090 22:56:19.141340 iDelay=203, Bit 12, Center 134 (79 ~ 190) 112
9091 22:56:19.144900 iDelay=203, Bit 13, Center 134 (79 ~ 190) 112
9092 22:56:19.151155 iDelay=203, Bit 14, Center 132 (75 ~ 190) 116
9093 22:56:19.154552 iDelay=203, Bit 15, Center 138 (83 ~ 194) 112
9094 22:56:19.154635 ==
9095 22:56:19.157783 Dram Type= 6, Freq= 0, CH_1, rank 1
9096 22:56:19.161244 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9097 22:56:19.161327 ==
9098 22:56:19.164299 DQS Delay:
9099 22:56:19.164381 DQS0 = 0, DQS1 = 0
9100 22:56:19.164474 DQM Delay:
9101 22:56:19.167610 DQM0 = 134, DQM1 = 126
9102 22:56:19.167750 DQ Delay:
9103 22:56:19.170876 DQ0 =140, DQ1 =128, DQ2 =122, DQ3 =130
9104 22:56:19.174073 DQ4 =134, DQ5 =144, DQ6 =146, DQ7 =130
9105 22:56:19.180736 DQ8 =112, DQ9 =116, DQ10 =126, DQ11 =116
9106 22:56:19.184455 DQ12 =134, DQ13 =134, DQ14 =132, DQ15 =138
9107 22:56:19.184624
9108 22:56:19.184690
9109 22:56:19.184750
9110 22:56:19.187573 [DramC_TX_OE_Calibration] TA2
9111 22:56:19.190719 Original DQ_B0 (3 6) =30, OEN = 27
9112 22:56:19.190803 Original DQ_B1 (3 6) =30, OEN = 27
9113 22:56:19.194018 24, 0x0, End_B0=24 End_B1=24
9114 22:56:19.197427 25, 0x0, End_B0=25 End_B1=25
9115 22:56:19.200666 26, 0x0, End_B0=26 End_B1=26
9116 22:56:19.204199 27, 0x0, End_B0=27 End_B1=27
9117 22:56:19.204287 28, 0x0, End_B0=28 End_B1=28
9118 22:56:19.207492 29, 0x0, End_B0=29 End_B1=29
9119 22:56:19.210751 30, 0x0, End_B0=30 End_B1=30
9120 22:56:19.214059 31, 0x5151, End_B0=30 End_B1=30
9121 22:56:19.217789 Byte0 end_step=30 best_step=27
9122 22:56:19.220452 Byte1 end_step=30 best_step=27
9123 22:56:19.220592 Byte0 TX OE(2T, 0.5T) = (3, 3)
9124 22:56:19.223889 Byte1 TX OE(2T, 0.5T) = (3, 3)
9125 22:56:19.223971
9126 22:56:19.224036
9127 22:56:19.233873 [DQSOSCAuto] RK1, (LSB)MR18= 0xd09, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 403 ps
9128 22:56:19.233985 CH1 RK1: MR19=303, MR18=D09
9129 22:56:19.240478 CH1_RK1: MR19=0x303, MR18=0xD09, DQSOSC=403, MR23=63, INC=22, DEC=15
9130 22:56:19.243564 [RxdqsGatingPostProcess] freq 1600
9131 22:56:19.250151 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9132 22:56:19.253633 best DQS0 dly(2T, 0.5T) = (1, 1)
9133 22:56:19.256790 best DQS1 dly(2T, 0.5T) = (1, 1)
9134 22:56:19.260094 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9135 22:56:19.263680 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9136 22:56:19.266569 best DQS0 dly(2T, 0.5T) = (1, 1)
9137 22:56:19.266652 best DQS1 dly(2T, 0.5T) = (1, 1)
9138 22:56:19.270852 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9139 22:56:19.273185 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9140 22:56:19.276860 Pre-setting of DQS Precalculation
9141 22:56:19.283754 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9142 22:56:19.290242 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9143 22:56:19.296363 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9144 22:56:19.296453
9145 22:56:19.296549
9146 22:56:19.299805 [Calibration Summary] 3200 Mbps
9147 22:56:19.302778 CH 0, Rank 0
9148 22:56:19.302877 SW Impedance : PASS
9149 22:56:19.306276 DUTY Scan : NO K
9150 22:56:19.306369 ZQ Calibration : PASS
9151 22:56:19.309653 Jitter Meter : NO K
9152 22:56:19.312984 CBT Training : PASS
9153 22:56:19.313070 Write leveling : PASS
9154 22:56:19.316437 RX DQS gating : PASS
9155 22:56:19.319487 RX DQ/DQS(RDDQC) : PASS
9156 22:56:19.319570 TX DQ/DQS : PASS
9157 22:56:19.322998 RX DATLAT : PASS
9158 22:56:19.325981 RX DQ/DQS(Engine): PASS
9159 22:56:19.326093 TX OE : PASS
9160 22:56:19.329641 All Pass.
9161 22:56:19.329722
9162 22:56:19.329799 CH 0, Rank 1
9163 22:56:19.333131 SW Impedance : PASS
9164 22:56:19.333215 DUTY Scan : NO K
9165 22:56:19.336267 ZQ Calibration : PASS
9166 22:56:19.339424 Jitter Meter : NO K
9167 22:56:19.339516 CBT Training : PASS
9168 22:56:19.342537 Write leveling : PASS
9169 22:56:19.346077 RX DQS gating : PASS
9170 22:56:19.346158 RX DQ/DQS(RDDQC) : PASS
9171 22:56:19.349164 TX DQ/DQS : PASS
9172 22:56:19.352807 RX DATLAT : PASS
9173 22:56:19.352891 RX DQ/DQS(Engine): PASS
9174 22:56:19.355630 TX OE : PASS
9175 22:56:19.355716 All Pass.
9176 22:56:19.355792
9177 22:56:19.359255 CH 1, Rank 0
9178 22:56:19.359345 SW Impedance : PASS
9179 22:56:19.362594 DUTY Scan : NO K
9180 22:56:19.366246 ZQ Calibration : PASS
9181 22:56:19.366385 Jitter Meter : NO K
9182 22:56:19.368945 CBT Training : PASS
9183 22:56:19.369052 Write leveling : PASS
9184 22:56:19.372403 RX DQS gating : PASS
9185 22:56:19.375825 RX DQ/DQS(RDDQC) : PASS
9186 22:56:19.375908 TX DQ/DQS : PASS
9187 22:56:19.378961 RX DATLAT : PASS
9188 22:56:19.382240 RX DQ/DQS(Engine): PASS
9189 22:56:19.382323 TX OE : PASS
9190 22:56:19.385320 All Pass.
9191 22:56:19.385402
9192 22:56:19.385467 CH 1, Rank 1
9193 22:56:19.388713 SW Impedance : PASS
9194 22:56:19.388796 DUTY Scan : NO K
9195 22:56:19.391898 ZQ Calibration : PASS
9196 22:56:19.395529 Jitter Meter : NO K
9197 22:56:19.395612 CBT Training : PASS
9198 22:56:19.399089 Write leveling : PASS
9199 22:56:19.402033 RX DQS gating : PASS
9200 22:56:19.402143 RX DQ/DQS(RDDQC) : PASS
9201 22:56:19.405226 TX DQ/DQS : PASS
9202 22:56:19.408456 RX DATLAT : PASS
9203 22:56:19.408576 RX DQ/DQS(Engine): PASS
9204 22:56:19.411911 TX OE : PASS
9205 22:56:19.411994 All Pass.
9206 22:56:19.412060
9207 22:56:19.415364 DramC Write-DBI on
9208 22:56:19.418507 PER_BANK_REFRESH: Hybrid Mode
9209 22:56:19.418588 TX_TRACKING: ON
9210 22:56:19.428417 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9211 22:56:19.435559 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9212 22:56:19.441562 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9213 22:56:19.445218 [FAST_K] Save calibration result to emmc
9214 22:56:19.448381 sync common calibartion params.
9215 22:56:19.451465 sync cbt_mode0:1, 1:1
9216 22:56:19.455000 dram_init: ddr_geometry: 2
9217 22:56:19.455076 dram_init: ddr_geometry: 2
9218 22:56:19.458443 dram_init: ddr_geometry: 2
9219 22:56:19.461564 0:dram_rank_size:100000000
9220 22:56:19.464614 1:dram_rank_size:100000000
9221 22:56:19.467866 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9222 22:56:19.471868 DFS_SHUFFLE_HW_MODE: ON
9223 22:56:19.474615 dramc_set_vcore_voltage set vcore to 725000
9224 22:56:19.478162 Read voltage for 1600, 0
9225 22:56:19.478264 Vio18 = 0
9226 22:56:19.478358 Vcore = 725000
9227 22:56:19.481880 Vdram = 0
9228 22:56:19.481958 Vddq = 0
9229 22:56:19.482038 Vmddr = 0
9230 22:56:19.484628 switch to 3200 Mbps bootup
9231 22:56:19.487760 [DramcRunTimeConfig]
9232 22:56:19.487838 PHYPLL
9233 22:56:19.487900 DPM_CONTROL_AFTERK: ON
9234 22:56:19.491419 PER_BANK_REFRESH: ON
9235 22:56:19.494497 REFRESH_OVERHEAD_REDUCTION: ON
9236 22:56:19.494615 CMD_PICG_NEW_MODE: OFF
9237 22:56:19.497620 XRTWTW_NEW_MODE: ON
9238 22:56:19.501336 XRTRTR_NEW_MODE: ON
9239 22:56:19.501451 TX_TRACKING: ON
9240 22:56:19.504390 RDSEL_TRACKING: OFF
9241 22:56:19.504533 DQS Precalculation for DVFS: ON
9242 22:56:19.507839 RX_TRACKING: OFF
9243 22:56:19.507932 HW_GATING DBG: ON
9244 22:56:19.510891 ZQCS_ENABLE_LP4: ON
9245 22:56:19.514052 RX_PICG_NEW_MODE: ON
9246 22:56:19.514148 TX_PICG_NEW_MODE: ON
9247 22:56:19.517975 ENABLE_RX_DCM_DPHY: ON
9248 22:56:19.520875 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9249 22:56:19.520966 DUMMY_READ_FOR_TRACKING: OFF
9250 22:56:19.524341 !!! SPM_CONTROL_AFTERK: OFF
9251 22:56:19.527651 !!! SPM could not control APHY
9252 22:56:19.531187 IMPEDANCE_TRACKING: ON
9253 22:56:19.531289 TEMP_SENSOR: ON
9254 22:56:19.534464 HW_SAVE_FOR_SR: OFF
9255 22:56:19.537800 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9256 22:56:19.541241 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9257 22:56:19.541346 Read ODT Tracking: ON
9258 22:56:19.544283 Refresh Rate DeBounce: ON
9259 22:56:19.547724 DFS_NO_QUEUE_FLUSH: ON
9260 22:56:19.550639 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9261 22:56:19.550740 ENABLE_DFS_RUNTIME_MRW: OFF
9262 22:56:19.554008 DDR_RESERVE_NEW_MODE: ON
9263 22:56:19.557103 MR_CBT_SWITCH_FREQ: ON
9264 22:56:19.557195 =========================
9265 22:56:19.577155 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9266 22:56:19.580509 dram_init: ddr_geometry: 2
9267 22:56:19.598562 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9268 22:56:19.601774 dram_init: dram init end (result: 0)
9269 22:56:19.609016 DRAM-K: Full calibration passed in 24635 msecs
9270 22:56:19.611867 MRC: failed to locate region type 0.
9271 22:56:19.611997 DRAM rank0 size:0x100000000,
9272 22:56:19.615792 DRAM rank1 size=0x100000000
9273 22:56:19.625194 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9274 22:56:19.631783 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9275 22:56:19.638140 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9276 22:56:19.648412 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9277 22:56:19.648607 DRAM rank0 size:0x100000000,
9278 22:56:19.651519 DRAM rank1 size=0x100000000
9279 22:56:19.651599 CBMEM:
9280 22:56:19.655011 IMD: root @ 0xfffff000 254 entries.
9281 22:56:19.658023 IMD: root @ 0xffffec00 62 entries.
9282 22:56:19.661287 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9283 22:56:19.667974 WARNING: RO_VPD is uninitialized or empty.
9284 22:56:19.671652 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9285 22:56:19.678685 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9286 22:56:19.691973 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9287 22:56:19.703188 BS: romstage times (exec / console): total (unknown) / 24126 ms
9288 22:56:19.703337
9289 22:56:19.703413
9290 22:56:19.713018 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9291 22:56:19.716124 ARM64: Exception handlers installed.
9292 22:56:19.719548 ARM64: Testing exception
9293 22:56:19.722744 ARM64: Done test exception
9294 22:56:19.722843 Enumerating buses...
9295 22:56:19.726128 Show all devs... Before device enumeration.
9296 22:56:19.729929 Root Device: enabled 1
9297 22:56:19.732701 CPU_CLUSTER: 0: enabled 1
9298 22:56:19.732836 CPU: 00: enabled 1
9299 22:56:19.735782 Compare with tree...
9300 22:56:19.735934 Root Device: enabled 1
9301 22:56:19.739505 CPU_CLUSTER: 0: enabled 1
9302 22:56:19.742697 CPU: 00: enabled 1
9303 22:56:19.742870 Root Device scanning...
9304 22:56:19.745983 scan_static_bus for Root Device
9305 22:56:19.749172 CPU_CLUSTER: 0 enabled
9306 22:56:19.752494 scan_static_bus for Root Device done
9307 22:56:19.755570 scan_bus: bus Root Device finished in 8 msecs
9308 22:56:19.755657 done
9309 22:56:19.762358 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9310 22:56:19.765843 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9311 22:56:19.772084 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9312 22:56:19.775682 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9313 22:56:19.778916 Allocating resources...
9314 22:56:19.782438 Reading resources...
9315 22:56:19.785219 Root Device read_resources bus 0 link: 0
9316 22:56:19.788858 DRAM rank0 size:0x100000000,
9317 22:56:19.788986 DRAM rank1 size=0x100000000
9318 22:56:19.795107 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9319 22:56:19.795230 CPU: 00 missing read_resources
9320 22:56:19.801980 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9321 22:56:19.805472 Root Device read_resources bus 0 link: 0 done
9322 22:56:19.808734 Done reading resources.
9323 22:56:19.811806 Show resources in subtree (Root Device)...After reading.
9324 22:56:19.815080 Root Device child on link 0 CPU_CLUSTER: 0
9325 22:56:19.818718 CPU_CLUSTER: 0 child on link 0 CPU: 00
9326 22:56:19.828618 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9327 22:56:19.828861 CPU: 00
9328 22:56:19.831588 Root Device assign_resources, bus 0 link: 0
9329 22:56:19.835108 CPU_CLUSTER: 0 missing set_resources
9330 22:56:19.841357 Root Device assign_resources, bus 0 link: 0 done
9331 22:56:19.841501 Done setting resources.
9332 22:56:19.848708 Show resources in subtree (Root Device)...After assigning values.
9333 22:56:19.851809 Root Device child on link 0 CPU_CLUSTER: 0
9334 22:56:19.854633 CPU_CLUSTER: 0 child on link 0 CPU: 00
9335 22:56:19.864583 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9336 22:56:19.864701 CPU: 00
9337 22:56:19.868270 Done allocating resources.
9338 22:56:19.874676 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9339 22:56:19.874768 Enabling resources...
9340 22:56:19.874836 done.
9341 22:56:19.881102 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9342 22:56:19.884657 Initializing devices...
9343 22:56:19.884743 Root Device init
9344 22:56:19.887869 init hardware done!
9345 22:56:19.887953 0x00000018: ctrlr->caps
9346 22:56:19.891188 52.000 MHz: ctrlr->f_max
9347 22:56:19.894403 0.400 MHz: ctrlr->f_min
9348 22:56:19.894491 0x40ff8080: ctrlr->voltages
9349 22:56:19.897894 sclk: 390625
9350 22:56:19.897999 Bus Width = 1
9351 22:56:19.898071 sclk: 390625
9352 22:56:19.901070 Bus Width = 1
9353 22:56:19.905011 Early init status = 3
9354 22:56:19.907674 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9355 22:56:19.911263 in-header: 03 fc 00 00 01 00 00 00
9356 22:56:19.914749 in-data: 00
9357 22:56:19.918207 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9358 22:56:19.922123 in-header: 03 fd 00 00 00 00 00 00
9359 22:56:19.925529 in-data:
9360 22:56:19.929188 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9361 22:56:19.932575 in-header: 03 fc 00 00 01 00 00 00
9362 22:56:19.936044 in-data: 00
9363 22:56:19.939139 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9364 22:56:19.943855 in-header: 03 fd 00 00 00 00 00 00
9365 22:56:19.946943 in-data:
9366 22:56:19.950558 [SSUSB] Setting up USB HOST controller...
9367 22:56:19.953981 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9368 22:56:19.957022 [SSUSB] phy power-on done.
9369 22:56:19.960418 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9370 22:56:19.966900 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9371 22:56:19.970321 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9372 22:56:19.976495 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9373 22:56:19.983362 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9374 22:56:19.989741 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9375 22:56:19.996794 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9376 22:56:20.003110 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9377 22:56:20.006628 SPM: binary array size = 0x9dc
9378 22:56:20.009858 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9379 22:56:20.017025 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9380 22:56:20.023033 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9381 22:56:20.029351 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9382 22:56:20.032912 configure_display: Starting display init
9383 22:56:20.067404 anx7625_power_on_init: Init interface.
9384 22:56:20.070256 anx7625_disable_pd_protocol: Disabled PD feature.
9385 22:56:20.073885 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9386 22:56:20.101640 anx7625_start_dp_work: Secure OCM version=00
9387 22:56:20.104424 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9388 22:56:20.119632 sp_tx_get_edid_block: EDID Block = 1
9389 22:56:20.222558 Extracted contents:
9390 22:56:20.225136 header: 00 ff ff ff ff ff ff 00
9391 22:56:20.228930 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9392 22:56:20.231952 version: 01 04
9393 22:56:20.235204 basic params: 95 1f 11 78 0a
9394 22:56:20.238871 chroma info: 76 90 94 55 54 90 27 21 50 54
9395 22:56:20.241785 established: 00 00 00
9396 22:56:20.248368 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9397 22:56:20.254986 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9398 22:56:20.258243 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9399 22:56:20.264682 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9400 22:56:20.271111 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9401 22:56:20.274768 extensions: 00
9402 22:56:20.274886 checksum: fb
9403 22:56:20.274950
9404 22:56:20.281436 Manufacturer: IVO Model 57d Serial Number 0
9405 22:56:20.281547 Made week 0 of 2020
9406 22:56:20.284561 EDID version: 1.4
9407 22:56:20.284652 Digital display
9408 22:56:20.287854 6 bits per primary color channel
9409 22:56:20.291097 DisplayPort interface
9410 22:56:20.291189 Maximum image size: 31 cm x 17 cm
9411 22:56:20.294744 Gamma: 220%
9412 22:56:20.294833 Check DPMS levels
9413 22:56:20.300950 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9414 22:56:20.304362 First detailed timing is preferred timing
9415 22:56:20.307413 Established timings supported:
9416 22:56:20.307523 Standard timings supported:
9417 22:56:20.310732 Detailed timings
9418 22:56:20.314186 Hex of detail: 383680a07038204018303c0035ae10000019
9419 22:56:20.320808 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9420 22:56:20.324273 0780 0798 07c8 0820 hborder 0
9421 22:56:20.327281 0438 043b 0447 0458 vborder 0
9422 22:56:20.330894 -hsync -vsync
9423 22:56:20.331000 Did detailed timing
9424 22:56:20.337549 Hex of detail: 000000000000000000000000000000000000
9425 22:56:20.340998 Manufacturer-specified data, tag 0
9426 22:56:20.343762 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9427 22:56:20.347513 ASCII string: InfoVision
9428 22:56:20.350913 Hex of detail: 000000fe00523134304e574635205248200a
9429 22:56:20.353815 ASCII string: R140NWF5 RH
9430 22:56:20.353911 Checksum
9431 22:56:20.357040 Checksum: 0xfb (valid)
9432 22:56:20.360497 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9433 22:56:20.363737 DSI data_rate: 832800000 bps
9434 22:56:20.370192 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9435 22:56:20.373703 anx7625_parse_edid: pixelclock(138800).
9436 22:56:20.377190 hactive(1920), hsync(48), hfp(24), hbp(88)
9437 22:56:20.380047 vactive(1080), vsync(12), vfp(3), vbp(17)
9438 22:56:20.383715 anx7625_dsi_config: config dsi.
9439 22:56:20.390005 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9440 22:56:20.404078 anx7625_dsi_config: success to config DSI
9441 22:56:20.407498 anx7625_dp_start: MIPI phy setup OK.
9442 22:56:20.410642 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9443 22:56:20.413833 mtk_ddp_mode_set invalid vrefresh 60
9444 22:56:20.416992 main_disp_path_setup
9445 22:56:20.417092 ovl_layer_smi_id_en
9446 22:56:20.420341 ovl_layer_smi_id_en
9447 22:56:20.420457 ccorr_config
9448 22:56:20.420596 aal_config
9449 22:56:20.423685 gamma_config
9450 22:56:20.423773 postmask_config
9451 22:56:20.427468 dither_config
9452 22:56:20.430590 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9453 22:56:20.436996 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9454 22:56:20.440722 Root Device init finished in 552 msecs
9455 22:56:20.443617 CPU_CLUSTER: 0 init
9456 22:56:20.450404 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9457 22:56:20.457065 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9458 22:56:20.457187 APU_MBOX 0x190000b0 = 0x10001
9459 22:56:20.460126 APU_MBOX 0x190001b0 = 0x10001
9460 22:56:20.463598 APU_MBOX 0x190005b0 = 0x10001
9461 22:56:20.466627 APU_MBOX 0x190006b0 = 0x10001
9462 22:56:20.473497 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9463 22:56:20.482944 read SPI 0x539f4 0xe237: 6245 us, 9273 KB/s, 74.184 Mbps
9464 22:56:20.495604 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9465 22:56:20.502419 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9466 22:56:20.513631 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9467 22:56:20.522725 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9468 22:56:20.526076 CPU_CLUSTER: 0 init finished in 81 msecs
9469 22:56:20.529920 Devices initialized
9470 22:56:20.532767 Show all devs... After init.
9471 22:56:20.532863 Root Device: enabled 1
9472 22:56:20.536348 CPU_CLUSTER: 0: enabled 1
9473 22:56:20.539361 CPU: 00: enabled 1
9474 22:56:20.542854 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms
9475 22:56:20.545884 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9476 22:56:20.549493 ELOG: NV offset 0x57f000 size 0x1000
9477 22:56:20.555751 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9478 22:56:20.562717 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9479 22:56:20.566053 ELOG: Event(17) added with size 13 at 2023-06-05 22:56:20 UTC
9480 22:56:20.572459 out: cmd=0x121: 03 db 21 01 00 00 00 00
9481 22:56:20.575880 in-header: 03 bb 00 00 2c 00 00 00
9482 22:56:20.588614 in-data: a4 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9483 22:56:20.592466 ELOG: Event(A1) added with size 10 at 2023-06-05 22:56:20 UTC
9484 22:56:20.599014 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9485 22:56:20.605725 ELOG: Event(A0) added with size 9 at 2023-06-05 22:56:20 UTC
9486 22:56:20.608970 elog_add_boot_reason: Logged dev mode boot
9487 22:56:20.615236 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9488 22:56:20.615369 Finalize devices...
9489 22:56:20.618721 Devices finalized
9490 22:56:20.622268 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9491 22:56:20.625213 Writing coreboot table at 0xffe64000
9492 22:56:20.631713 0. 000000000010a000-0000000000113fff: RAMSTAGE
9493 22:56:20.635183 1. 0000000040000000-00000000400fffff: RAM
9494 22:56:20.638214 2. 0000000040100000-000000004032afff: RAMSTAGE
9495 22:56:20.641465 3. 000000004032b000-00000000545fffff: RAM
9496 22:56:20.645171 4. 0000000054600000-000000005465ffff: BL31
9497 22:56:20.648396 5. 0000000054660000-00000000ffe63fff: RAM
9498 22:56:20.654844 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9499 22:56:20.657798 7. 0000000100000000-000000023fffffff: RAM
9500 22:56:20.661267 Passing 5 GPIOs to payload:
9501 22:56:20.664480 NAME | PORT | POLARITY | VALUE
9502 22:56:20.670997 EC in RW | 0x000000aa | low | undefined
9503 22:56:20.674198 EC interrupt | 0x00000005 | low | undefined
9504 22:56:20.681058 TPM interrupt | 0x000000ab | high | undefined
9505 22:56:20.684753 SD card detect | 0x00000011 | high | undefined
9506 22:56:20.687828 speaker enable | 0x00000093 | high | undefined
9507 22:56:20.694036 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9508 22:56:20.697448 in-header: 03 f9 00 00 02 00 00 00
9509 22:56:20.697561 in-data: 02 00
9510 22:56:20.701061 ADC[4]: Raw value=902291 ID=7
9511 22:56:20.704724 ADC[3]: Raw value=214021 ID=1
9512 22:56:20.704867 RAM Code: 0x71
9513 22:56:20.707770 ADC[6]: Raw value=75036 ID=0
9514 22:56:20.711011 ADC[5]: Raw value=212912 ID=1
9515 22:56:20.711109 SKU Code: 0x1
9516 22:56:20.717158 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum a129
9517 22:56:20.720510 coreboot table: 964 bytes.
9518 22:56:20.723988 IMD ROOT 0. 0xfffff000 0x00001000
9519 22:56:20.726936 IMD SMALL 1. 0xffffe000 0x00001000
9520 22:56:20.730490 RO MCACHE 2. 0xffffc000 0x00001104
9521 22:56:20.733805 CONSOLE 3. 0xfff7c000 0x00080000
9522 22:56:20.737391 FMAP 4. 0xfff7b000 0x00000452
9523 22:56:20.740448 TIME STAMP 5. 0xfff7a000 0x00000910
9524 22:56:20.743692 VBOOT WORK 6. 0xfff66000 0x00014000
9525 22:56:20.746801 RAMOOPS 7. 0xffe66000 0x00100000
9526 22:56:20.750364 COREBOOT 8. 0xffe64000 0x00002000
9527 22:56:20.750452 IMD small region:
9528 22:56:20.753967 IMD ROOT 0. 0xffffec00 0x00000400
9529 22:56:20.756781 VPD 1. 0xffffeba0 0x0000004c
9530 22:56:20.759987 MMC STATUS 2. 0xffffeb80 0x00000004
9531 22:56:20.766856 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9532 22:56:20.770370 Probing TPM: done!
9533 22:56:20.773583 Connected to device vid:did:rid of 1ae0:0028:00
9534 22:56:20.783593 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9535 22:56:20.786628 Initialized TPM device CR50 revision 0
9536 22:56:20.790344 Checking cr50 for pending updates
9537 22:56:20.793888 Reading cr50 TPM mode
9538 22:56:20.801983 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9539 22:56:20.808636 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9540 22:56:20.848660 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9541 22:56:20.852444 Checking segment from ROM address 0x40100000
9542 22:56:20.855563 Checking segment from ROM address 0x4010001c
9543 22:56:20.862151 Loading segment from ROM address 0x40100000
9544 22:56:20.862237 code (compression=0)
9545 22:56:20.872513 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9546 22:56:20.878614 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9547 22:56:20.878746 it's not compressed!
9548 22:56:20.885177 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9549 22:56:20.891755 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9550 22:56:20.909312 Loading segment from ROM address 0x4010001c
9551 22:56:20.909475 Entry Point 0x80000000
9552 22:56:20.912353 Loaded segments
9553 22:56:20.916083 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9554 22:56:20.922411 Jumping to boot code at 0x80000000(0xffe64000)
9555 22:56:20.929397 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9556 22:56:20.935726 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9557 22:56:20.944159 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9558 22:56:20.946831 Checking segment from ROM address 0x40100000
9559 22:56:20.950303 Checking segment from ROM address 0x4010001c
9560 22:56:20.956933 Loading segment from ROM address 0x40100000
9561 22:56:20.957222 code (compression=1)
9562 22:56:20.963880 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9563 22:56:20.973748 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9564 22:56:20.974125 using LZMA
9565 22:56:20.982146 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9566 22:56:20.988591 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9567 22:56:20.991940 Loading segment from ROM address 0x4010001c
9568 22:56:20.992299 Entry Point 0x54601000
9569 22:56:20.995881 Loaded segments
9570 22:56:20.998537 NOTICE: MT8192 bl31_setup
9571 22:56:21.005835 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9572 22:56:21.009234 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9573 22:56:21.012583 WARNING: region 0:
9574 22:56:21.016169 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9575 22:56:21.016708 WARNING: region 1:
9576 22:56:21.022687 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9577 22:56:21.025463 WARNING: region 2:
9578 22:56:21.029023 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9579 22:56:21.032737 WARNING: region 3:
9580 22:56:21.036037 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9581 22:56:21.039292 WARNING: region 4:
9582 22:56:21.045478 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9583 22:56:21.045987 WARNING: region 5:
9584 22:56:21.048905 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9585 22:56:21.052348 WARNING: region 6:
9586 22:56:21.055696 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9587 22:56:21.059054 WARNING: region 7:
9588 22:56:21.062525 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9589 22:56:21.068785 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9590 22:56:21.072045 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9591 22:56:21.078221 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9592 22:56:21.081882 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9593 22:56:21.085271 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9594 22:56:21.091920 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9595 22:56:21.095044 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9596 22:56:21.098476 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9597 22:56:21.104759 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9598 22:56:21.108343 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9599 22:56:21.115084 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9600 22:56:21.118654 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9601 22:56:21.121251 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9602 22:56:21.128313 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9603 22:56:21.131362 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9604 22:56:21.134790 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9605 22:56:21.141112 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9606 22:56:21.144830 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9607 22:56:21.150915 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9608 22:56:21.154893 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9609 22:56:21.157531 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9610 22:56:21.164409 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9611 22:56:21.168193 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9612 22:56:21.174311 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9613 22:56:21.178035 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9614 22:56:21.181398 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9615 22:56:21.187911 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9616 22:56:21.191145 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9617 22:56:21.198059 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9618 22:56:21.201518 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9619 22:56:21.204141 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9620 22:56:21.211407 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9621 22:56:21.214479 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9622 22:56:21.217623 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9623 22:56:21.224431 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9624 22:56:21.228029 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9625 22:56:21.231624 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9626 22:56:21.234540 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9627 22:56:21.240597 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9628 22:56:21.244092 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9629 22:56:21.247363 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9630 22:56:21.250691 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9631 22:56:21.257229 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9632 22:56:21.260825 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9633 22:56:21.264633 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9634 22:56:21.267780 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9635 22:56:21.274352 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9636 22:56:21.277412 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9637 22:56:21.281005 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9638 22:56:21.287098 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9639 22:56:21.290416 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9640 22:56:21.297181 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9641 22:56:21.300574 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9642 22:56:21.303976 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9643 22:56:21.310417 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9644 22:56:21.313574 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9645 22:56:21.320359 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9646 22:56:21.324142 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9647 22:56:21.330492 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9648 22:56:21.334187 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9649 22:56:21.340384 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9650 22:56:21.343912 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9651 22:56:21.346883 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9652 22:56:21.353986 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9653 22:56:21.356891 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9654 22:56:21.363568 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9655 22:56:21.367092 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9656 22:56:21.373840 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9657 22:56:21.377167 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9658 22:56:21.380397 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9659 22:56:21.386937 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9660 22:56:21.390310 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9661 22:56:21.397221 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9662 22:56:21.400307 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9663 22:56:21.407208 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9664 22:56:21.410375 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9665 22:56:21.416479 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9666 22:56:21.420410 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9667 22:56:21.423529 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9668 22:56:21.430087 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9669 22:56:21.433462 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9670 22:56:21.439733 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9671 22:56:21.443327 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9672 22:56:21.449825 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9673 22:56:21.453092 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9674 22:56:21.456647 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9675 22:56:21.463268 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9676 22:56:21.466708 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9677 22:56:21.473269 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9678 22:56:21.476595 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9679 22:56:21.483174 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9680 22:56:21.486228 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9681 22:56:21.493199 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9682 22:56:21.496392 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9683 22:56:21.499656 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9684 22:56:21.506823 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9685 22:56:21.510124 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9686 22:56:21.512880 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9687 22:56:21.519494 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9688 22:56:21.522894 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9689 22:56:21.526314 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9690 22:56:21.532783 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9691 22:56:21.535933 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9692 22:56:21.542444 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9693 22:56:21.546071 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9694 22:56:21.549839 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9695 22:56:21.556728 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9696 22:56:21.559576 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9697 22:56:21.562461 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9698 22:56:21.569699 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9699 22:56:21.572678 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9700 22:56:21.579097 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9701 22:56:21.582979 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9702 22:56:21.585738 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9703 22:56:21.592861 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9704 22:56:21.596009 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9705 22:56:21.599554 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9706 22:56:21.605905 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9707 22:56:21.609400 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9708 22:56:21.612506 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9709 22:56:21.619393 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9710 22:56:21.622848 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9711 22:56:21.626055 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9712 22:56:21.628902 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9713 22:56:21.635914 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9714 22:56:21.639037 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9715 22:56:21.645937 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9716 22:56:21.648922 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9717 22:56:21.652731 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9718 22:56:21.659192 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9719 22:56:21.662138 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9720 22:56:21.665566 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9721 22:56:21.672425 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9722 22:56:21.675634 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9723 22:56:21.682653 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9724 22:56:21.685906 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9725 22:56:21.689011 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9726 22:56:21.695911 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9727 22:56:21.699036 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9728 22:56:21.705609 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9729 22:56:21.708933 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9730 22:56:21.712128 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9731 22:56:21.719143 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9732 22:56:21.722471 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9733 22:56:21.725406 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9734 22:56:21.732607 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9735 22:56:21.735757 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9736 22:56:21.742652 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9737 22:56:21.745305 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9738 22:56:21.752174 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9739 22:56:21.755794 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9740 22:56:21.758626 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9741 22:56:21.765072 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9742 22:56:21.768476 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9743 22:56:21.772126 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9744 22:56:21.778464 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9745 22:56:21.782356 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9746 22:56:21.788861 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9747 22:56:21.791666 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9748 22:56:21.795326 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9749 22:56:21.801160 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9750 22:56:21.804509 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9751 22:56:21.811039 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9752 22:56:21.814619 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9753 22:56:21.821054 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9754 22:56:21.824546 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9755 22:56:21.827612 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9756 22:56:21.834038 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9757 22:56:21.837396 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9758 22:56:21.844823 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9759 22:56:21.847389 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9760 22:56:21.850474 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9761 22:56:21.857687 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9762 22:56:21.860952 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9763 22:56:21.866937 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9764 22:56:21.870499 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9765 22:56:21.874066 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9766 22:56:21.880116 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9767 22:56:21.883879 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9768 22:56:21.890364 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9769 22:56:21.893692 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9770 22:56:21.897146 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9771 22:56:21.903487 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9772 22:56:21.906685 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9773 22:56:21.913750 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9774 22:56:21.916505 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9775 22:56:21.920252 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9776 22:56:21.926822 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9777 22:56:21.929725 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9778 22:56:21.936602 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9779 22:56:21.939859 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9780 22:56:21.942880 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9781 22:56:21.950288 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9782 22:56:21.952791 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9783 22:56:21.959757 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9784 22:56:21.963263 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9785 22:56:21.969706 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9786 22:56:21.973025 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9787 22:56:21.976011 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9788 22:56:21.982714 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9789 22:56:21.986190 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9790 22:56:21.992610 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9791 22:56:21.996073 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9792 22:56:22.002450 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9793 22:56:22.006251 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9794 22:56:22.009212 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9795 22:56:22.015599 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9796 22:56:22.019120 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9797 22:56:22.025900 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9798 22:56:22.028746 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9799 22:56:22.035391 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9800 22:56:22.038618 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9801 22:56:22.042628 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9802 22:56:22.048484 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9803 22:56:22.051613 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9804 22:56:22.058690 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9805 22:56:22.062385 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9806 22:56:22.068650 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9807 22:56:22.071828 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9808 22:56:22.075272 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9809 22:56:22.082061 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9810 22:56:22.085316 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9811 22:56:22.091443 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9812 22:56:22.094692 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9813 22:56:22.101274 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9814 22:56:22.104783 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9815 22:56:22.108000 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9816 22:56:22.114445 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9817 22:56:22.117940 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9818 22:56:22.121438 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9819 22:56:22.128160 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9820 22:56:22.131074 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9821 22:56:22.134300 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9822 22:56:22.137580 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9823 22:56:22.144331 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9824 22:56:22.147391 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9825 22:56:22.154159 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9826 22:56:22.157272 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9827 22:56:22.160540 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9828 22:56:22.167511 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9829 22:56:22.170938 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9830 22:56:22.173806 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9831 22:56:22.181000 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9832 22:56:22.184010 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9833 22:56:22.187653 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9834 22:56:22.193653 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9835 22:56:22.197088 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9836 22:56:22.203805 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9837 22:56:22.206875 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9838 22:56:22.210841 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9839 22:56:22.216718 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9840 22:56:22.219896 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9841 22:56:22.226670 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9842 22:56:22.230526 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9843 22:56:22.233378 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9844 22:56:22.239994 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9845 22:56:22.243609 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9846 22:56:22.246513 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9847 22:56:22.252606 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9848 22:56:22.256281 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9849 22:56:22.263079 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9850 22:56:22.266188 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9851 22:56:22.269554 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9852 22:56:22.276293 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9853 22:56:22.279668 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9854 22:56:22.282981 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9855 22:56:22.289604 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9856 22:56:22.292584 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9857 22:56:22.296056 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9858 22:56:22.302346 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9859 22:56:22.306259 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9860 22:56:22.309105 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9861 22:56:22.312146 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9862 22:56:22.315973 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9863 22:56:22.322575 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9864 22:56:22.325415 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9865 22:56:22.329075 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9866 22:56:22.335239 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9867 22:56:22.338474 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9868 22:56:22.342585 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9869 22:56:22.348817 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9870 22:56:22.351916 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9871 22:56:22.355740 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9872 22:56:22.362563 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9873 22:56:22.365187 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9874 22:56:22.371990 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9875 22:56:22.375332 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9876 22:56:22.378546 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9877 22:56:22.385010 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9878 22:56:22.388426 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9879 22:56:22.395162 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9880 22:56:22.398105 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9881 22:56:22.401194 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9882 22:56:22.408166 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9883 22:56:22.411246 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9884 22:56:22.417944 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9885 22:56:22.421100 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9886 22:56:22.427792 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9887 22:56:22.430626 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9888 22:56:22.434447 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9889 22:56:22.441225 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9890 22:56:22.444603 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9891 22:56:22.451095 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9892 22:56:22.454036 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9893 22:56:22.460610 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9894 22:56:22.464205 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9895 22:56:22.467537 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9896 22:56:22.474174 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9897 22:56:22.477018 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9898 22:56:22.484339 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9899 22:56:22.487290 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9900 22:56:22.490700 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9901 22:56:22.497335 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9902 22:56:22.500308 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9903 22:56:22.507585 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9904 22:56:22.510837 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9905 22:56:22.513621 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9906 22:56:22.520439 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9907 22:56:22.523445 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9908 22:56:22.530441 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9909 22:56:22.533308 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9910 22:56:22.536407 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9911 22:56:22.543586 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9912 22:56:22.546963 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9913 22:56:22.553678 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9914 22:56:22.556868 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9915 22:56:22.563290 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9916 22:56:22.566695 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9917 22:56:22.569871 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9918 22:56:22.576575 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9919 22:56:22.579721 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9920 22:56:22.586352 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9921 22:56:22.589666 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9922 22:56:22.596069 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9923 22:56:22.599480 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9924 22:56:22.602831 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9925 22:56:22.609368 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9926 22:56:22.612736 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9927 22:56:22.619528 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9928 22:56:22.622716 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9929 22:56:22.626070 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9930 22:56:22.632507 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9931 22:56:22.635577 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9932 22:56:22.642256 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9933 22:56:22.645326 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9934 22:56:22.652144 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9935 22:56:22.655157 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9936 22:56:22.658770 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9937 22:56:22.665606 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9938 22:56:22.668622 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9939 22:56:22.675133 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9940 22:56:22.678409 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9941 22:56:22.685355 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9942 22:56:22.688604 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9943 22:56:22.691960 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9944 22:56:22.698320 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9945 22:56:22.701705 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9946 22:56:22.708386 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9947 22:56:22.711698 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9948 22:56:22.718228 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9949 22:56:22.721175 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9950 22:56:22.724423 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9951 22:56:22.731525 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9952 22:56:22.734555 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9953 22:56:22.741040 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9954 22:56:22.744649 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9955 22:56:22.751205 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9956 22:56:22.754510 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9957 22:56:22.761023 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9958 22:56:22.764710 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9959 22:56:22.767819 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9960 22:56:22.774152 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9961 22:56:22.777371 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9962 22:56:22.784111 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9963 22:56:22.787574 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9964 22:56:22.794424 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9965 22:56:22.797353 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9966 22:56:22.800656 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9967 22:56:22.807381 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9968 22:56:22.810437 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9969 22:56:22.817124 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9970 22:56:22.820444 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9971 22:56:22.827095 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9972 22:56:22.830569 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9973 22:56:22.837042 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9974 22:56:22.840279 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9975 22:56:22.843507 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9976 22:56:22.850527 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9977 22:56:22.853457 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9978 22:56:22.860354 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9979 22:56:22.863237 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9980 22:56:22.870292 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9981 22:56:22.873466 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9982 22:56:22.876998 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9983 22:56:22.883699 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9984 22:56:22.886935 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9985 22:56:22.893180 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9986 22:56:22.896462 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9987 22:56:22.902991 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9988 22:56:22.906721 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9989 22:56:22.913343 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9990 22:56:22.916384 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9991 22:56:22.919418 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9992 22:56:22.926515 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9993 22:56:22.929226 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9994 22:56:22.936397 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9995 22:56:22.939203 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9996 22:56:22.946276 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9997 22:56:22.949621 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9998 22:56:22.955686 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9999 22:56:22.959040 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
10000 22:56:22.965830 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
10001 22:56:22.969020 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
10002 22:56:22.975903 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
10003 22:56:22.979143 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
10004 22:56:22.985343 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
10005 22:56:22.988619 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
10006 22:56:22.995054 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
10007 22:56:22.998355 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
10008 22:56:23.005029 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
10009 22:56:23.008490 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
10010 22:56:23.014971 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
10011 22:56:23.018836 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
10012 22:56:23.025397 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
10013 22:56:23.028675 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
10014 22:56:23.035246 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
10015 22:56:23.038532 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
10016 22:56:23.045218 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
10017 22:56:23.048244 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
10018 22:56:23.054967 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
10019 22:56:23.058195 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
10020 22:56:23.064759 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
10021 22:56:23.068088 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
10022 22:56:23.074971 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
10023 22:56:23.077803 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
10024 22:56:23.081180 INFO: [APUAPC] vio 0
10025 22:56:23.084752 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
10026 22:56:23.091251 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
10027 22:56:23.094718 INFO: [APUAPC] D0_APC_0: 0x400510
10028 22:56:23.095255 INFO: [APUAPC] D0_APC_1: 0x0
10029 22:56:23.097708 INFO: [APUAPC] D0_APC_2: 0x1540
10030 22:56:23.101448 INFO: [APUAPC] D0_APC_3: 0x0
10031 22:56:23.104025 INFO: [APUAPC] D1_APC_0: 0xffffffff
10032 22:56:23.108062 INFO: [APUAPC] D1_APC_1: 0xffffffff
10033 22:56:23.111097 INFO: [APUAPC] D1_APC_2: 0x3fffff
10034 22:56:23.114439 INFO: [APUAPC] D1_APC_3: 0x0
10035 22:56:23.117394 INFO: [APUAPC] D2_APC_0: 0xffffffff
10036 22:56:23.120963 INFO: [APUAPC] D2_APC_1: 0xffffffff
10037 22:56:23.124447 INFO: [APUAPC] D2_APC_2: 0x3fffff
10038 22:56:23.127519 INFO: [APUAPC] D2_APC_3: 0x0
10039 22:56:23.130654 INFO: [APUAPC] D3_APC_0: 0xffffffff
10040 22:56:23.134244 INFO: [APUAPC] D3_APC_1: 0xffffffff
10041 22:56:23.137786 INFO: [APUAPC] D3_APC_2: 0x3fffff
10042 22:56:23.140620 INFO: [APUAPC] D3_APC_3: 0x0
10043 22:56:23.143812 INFO: [APUAPC] D4_APC_0: 0xffffffff
10044 22:56:23.147663 INFO: [APUAPC] D4_APC_1: 0xffffffff
10045 22:56:23.150397 INFO: [APUAPC] D4_APC_2: 0x3fffff
10046 22:56:23.153826 INFO: [APUAPC] D4_APC_3: 0x0
10047 22:56:23.157107 INFO: [APUAPC] D5_APC_0: 0xffffffff
10048 22:56:23.161055 INFO: [APUAPC] D5_APC_1: 0xffffffff
10049 22:56:23.163669 INFO: [APUAPC] D5_APC_2: 0x3fffff
10050 22:56:23.167249 INFO: [APUAPC] D5_APC_3: 0x0
10051 22:56:23.170543 INFO: [APUAPC] D6_APC_0: 0xffffffff
10052 22:56:23.173562 INFO: [APUAPC] D6_APC_1: 0xffffffff
10053 22:56:23.176883 INFO: [APUAPC] D6_APC_2: 0x3fffff
10054 22:56:23.180504 INFO: [APUAPC] D6_APC_3: 0x0
10055 22:56:23.184010 INFO: [APUAPC] D7_APC_0: 0xffffffff
10056 22:56:23.186780 INFO: [APUAPC] D7_APC_1: 0xffffffff
10057 22:56:23.190059 INFO: [APUAPC] D7_APC_2: 0x3fffff
10058 22:56:23.192817 INFO: [APUAPC] D7_APC_3: 0x0
10059 22:56:23.196035 INFO: [APUAPC] D8_APC_0: 0xffffffff
10060 22:56:23.200050 INFO: [APUAPC] D8_APC_1: 0xffffffff
10061 22:56:23.203463 INFO: [APUAPC] D8_APC_2: 0x3fffff
10062 22:56:23.206554 INFO: [APUAPC] D8_APC_3: 0x0
10063 22:56:23.209532 INFO: [APUAPC] D9_APC_0: 0xffffffff
10064 22:56:23.213090 INFO: [APUAPC] D9_APC_1: 0xffffffff
10065 22:56:23.216531 INFO: [APUAPC] D9_APC_2: 0x3fffff
10066 22:56:23.220035 INFO: [APUAPC] D9_APC_3: 0x0
10067 22:56:23.222865 INFO: [APUAPC] D10_APC_0: 0xffffffff
10068 22:56:23.226223 INFO: [APUAPC] D10_APC_1: 0xffffffff
10069 22:56:23.229703 INFO: [APUAPC] D10_APC_2: 0x3fffff
10070 22:56:23.233264 INFO: [APUAPC] D10_APC_3: 0x0
10071 22:56:23.236080 INFO: [APUAPC] D11_APC_0: 0xffffffff
10072 22:56:23.239667 INFO: [APUAPC] D11_APC_1: 0xffffffff
10073 22:56:23.243035 INFO: [APUAPC] D11_APC_2: 0x3fffff
10074 22:56:23.246338 INFO: [APUAPC] D11_APC_3: 0x0
10075 22:56:23.249399 INFO: [APUAPC] D12_APC_0: 0xffffffff
10076 22:56:23.253271 INFO: [APUAPC] D12_APC_1: 0xffffffff
10077 22:56:23.256346 INFO: [APUAPC] D12_APC_2: 0x3fffff
10078 22:56:23.259403 INFO: [APUAPC] D12_APC_3: 0x0
10079 22:56:23.262823 INFO: [APUAPC] D13_APC_0: 0xffffffff
10080 22:56:23.265938 INFO: [APUAPC] D13_APC_1: 0xffffffff
10081 22:56:23.269333 INFO: [APUAPC] D13_APC_2: 0x3fffff
10082 22:56:23.273164 INFO: [APUAPC] D13_APC_3: 0x0
10083 22:56:23.276001 INFO: [APUAPC] D14_APC_0: 0xffffffff
10084 22:56:23.279837 INFO: [APUAPC] D14_APC_1: 0xffffffff
10085 22:56:23.282622 INFO: [APUAPC] D14_APC_2: 0x3fffff
10086 22:56:23.286209 INFO: [APUAPC] D14_APC_3: 0x0
10087 22:56:23.289427 INFO: [APUAPC] D15_APC_0: 0xffffffff
10088 22:56:23.292802 INFO: [APUAPC] D15_APC_1: 0xffffffff
10089 22:56:23.296214 INFO: [APUAPC] D15_APC_2: 0x3fffff
10090 22:56:23.299441 INFO: [APUAPC] D15_APC_3: 0x0
10091 22:56:23.302506 INFO: [APUAPC] APC_CON: 0x4
10092 22:56:23.306429 INFO: [NOCDAPC] D0_APC_0: 0x0
10093 22:56:23.307056 INFO: [NOCDAPC] D0_APC_1: 0x0
10094 22:56:23.309618 INFO: [NOCDAPC] D1_APC_0: 0x0
10095 22:56:23.312599 INFO: [NOCDAPC] D1_APC_1: 0xfff
10096 22:56:23.315817 INFO: [NOCDAPC] D2_APC_0: 0x0
10097 22:56:23.318789 INFO: [NOCDAPC] D2_APC_1: 0xfff
10098 22:56:23.322079 INFO: [NOCDAPC] D3_APC_0: 0x0
10099 22:56:23.325515 INFO: [NOCDAPC] D3_APC_1: 0xfff
10100 22:56:23.328645 INFO: [NOCDAPC] D4_APC_0: 0x0
10101 22:56:23.332173 INFO: [NOCDAPC] D4_APC_1: 0xfff
10102 22:56:23.335589 INFO: [NOCDAPC] D5_APC_0: 0x0
10103 22:56:23.338461 INFO: [NOCDAPC] D5_APC_1: 0xfff
10104 22:56:23.342096 INFO: [NOCDAPC] D6_APC_0: 0x0
10105 22:56:23.342185 INFO: [NOCDAPC] D6_APC_1: 0xfff
10106 22:56:23.345079 INFO: [NOCDAPC] D7_APC_0: 0x0
10107 22:56:23.348643 INFO: [NOCDAPC] D7_APC_1: 0xfff
10108 22:56:23.351742 INFO: [NOCDAPC] D8_APC_0: 0x0
10109 22:56:23.354740 INFO: [NOCDAPC] D8_APC_1: 0xfff
10110 22:56:23.358399 INFO: [NOCDAPC] D9_APC_0: 0x0
10111 22:56:23.361935 INFO: [NOCDAPC] D9_APC_1: 0xfff
10112 22:56:23.364920 INFO: [NOCDAPC] D10_APC_0: 0x0
10113 22:56:23.368469 INFO: [NOCDAPC] D10_APC_1: 0xfff
10114 22:56:23.371638 INFO: [NOCDAPC] D11_APC_0: 0x0
10115 22:56:23.375170 INFO: [NOCDAPC] D11_APC_1: 0xfff
10116 22:56:23.377831 INFO: [NOCDAPC] D12_APC_0: 0x0
10117 22:56:23.381199 INFO: [NOCDAPC] D12_APC_1: 0xfff
10118 22:56:23.381286 INFO: [NOCDAPC] D13_APC_0: 0x0
10119 22:56:23.384894 INFO: [NOCDAPC] D13_APC_1: 0xfff
10120 22:56:23.388452 INFO: [NOCDAPC] D14_APC_0: 0x0
10121 22:56:23.391397 INFO: [NOCDAPC] D14_APC_1: 0xfff
10122 22:56:23.394488 INFO: [NOCDAPC] D15_APC_0: 0x0
10123 22:56:23.397770 INFO: [NOCDAPC] D15_APC_1: 0xfff
10124 22:56:23.401115 INFO: [NOCDAPC] APC_CON: 0x4
10125 22:56:23.404545 INFO: [APUAPC] set_apusys_apc done
10126 22:56:23.407975 INFO: [DEVAPC] devapc_init done
10127 22:56:23.411142 INFO: GICv3 without legacy support detected.
10128 22:56:23.417451 INFO: ARM GICv3 driver initialized in EL3
10129 22:56:23.420710 INFO: Maximum SPI INTID supported: 639
10130 22:56:23.424031 INFO: BL31: Initializing runtime services
10131 22:56:23.430557 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10132 22:56:23.430670 INFO: SPM: enable CPC mode
10133 22:56:23.437543 INFO: mcdi ready for mcusys-off-idle and system suspend
10134 22:56:23.440921 INFO: BL31: Preparing for EL3 exit to normal world
10135 22:56:23.447334 INFO: Entry point address = 0x80000000
10136 22:56:23.447437 INFO: SPSR = 0x8
10137 22:56:23.453520
10138 22:56:23.453622
10139 22:56:23.453723
10140 22:56:23.456928 Starting depthcharge on Spherion...
10141 22:56:23.457028
10142 22:56:23.457118 Wipe memory regions:
10143 22:56:23.457205
10144 22:56:23.458049 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10145 22:56:23.458176 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10146 22:56:23.458288 Setting prompt string to ['asurada:']
10147 22:56:23.458395 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10148 22:56:23.460405 [0x00000040000000, 0x00000054600000)
10149 22:56:23.583215
10150 22:56:23.583618 [0x00000054660000, 0x00000080000000)
10151 22:56:23.843418
10152 22:56:23.843994 [0x000000821a7280, 0x000000ffe64000)
10153 22:56:24.588595
10154 22:56:24.589170 [0x00000100000000, 0x00000240000000)
10155 22:56:26.477914
10156 22:56:26.481061 Initializing XHCI USB controller at 0x11200000.
10157 22:56:27.462893
10158 22:56:27.463039 R8152: Initializing
10159 22:56:27.463110
10160 22:56:27.466003 Version 9 (ocp_data = 6010)
10161 22:56:27.466092
10162 22:56:27.469618 R8152: Done initializing
10163 22:56:27.469709
10164 22:56:27.469775 Adding net device
10165 22:56:27.991171
10166 22:56:27.994385 [firmware-asurada-13885.B-collabora] Dec 14 2021 15:21:43
10167 22:56:27.994502
10168 22:56:27.994581
10169 22:56:27.994671
10170 22:56:27.994958 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10172 22:56:28.095343 asurada: tftpboot 192.168.201.1 10597661/tftp-deploy-zpr5obgr/kernel/image.itb 10597661/tftp-deploy-zpr5obgr/kernel/cmdline
10173 22:56:28.095529 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10174 22:56:28.095653 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:20)
10175 22:56:28.100140 tftpboot 192.168.201.1 10597661/tftp-deploy-zpr5obgr/kernel/image.itp-deploy-zpr5obgr/kernel/cmdline
10176 22:56:28.100244
10177 22:56:28.100312 Waiting for link
10178 22:56:28.302250
10179 22:56:28.302430 done.
10180 22:56:28.302531
10181 22:56:28.302623 MAC: f4:f5:e8:50:de:0a
10182 22:56:28.302706
10183 22:56:28.305145 Sending DHCP discover... done.
10184 22:56:28.305269
10185 22:56:28.308995 Waiting for reply... done.
10186 22:56:28.309114
10187 22:56:28.312199 Sending DHCP request... done.
10188 22:56:28.312316
10189 22:56:28.442443 Waiting for reply... done.
10190 22:56:28.442622
10191 22:56:28.442720 My ip is 192.168.201.14
10192 22:56:28.442817
10193 22:56:28.445756 The DHCP server ip is 192.168.201.1
10194 22:56:28.445875
10195 22:56:28.452268 TFTP server IP predefined by user: 192.168.201.1
10196 22:56:28.452417
10197 22:56:28.458719 Bootfile predefined by user: 10597661/tftp-deploy-zpr5obgr/kernel/image.itb
10198 22:56:28.458869
10199 22:56:28.462059 Sending tftp read request... done.
10200 22:56:28.462182
10201 22:56:28.465684 Waiting for the transfer...
10202 22:56:28.465814
10203 22:56:28.683727 00000000 ################################################################
10204 22:56:28.683867
10205 22:56:28.905251 00080000 ################################################################
10206 22:56:28.905392
10207 22:56:29.141695 00100000 ################################################################
10208 22:56:29.141879
10209 22:56:29.382134 00180000 ################################################################
10210 22:56:29.382276
10211 22:56:29.621309 00200000 ################################################################
10212 22:56:29.621445
10213 22:56:29.865616 00280000 ################################################################
10214 22:56:29.865765
10215 22:56:30.100788 00300000 ################################################################
10216 22:56:30.100929
10217 22:56:30.339741 00380000 ################################################################
10218 22:56:30.339880
10219 22:56:30.582529 00400000 ################################################################
10220 22:56:30.582688
10221 22:56:30.820990 00480000 ################################################################
10222 22:56:30.821155
10223 22:56:31.068756 00500000 ################################################################
10224 22:56:31.068919
10225 22:56:31.299099 00580000 ################################################################
10226 22:56:31.299241
10227 22:56:31.537247 00600000 ################################################################
10228 22:56:31.537384
10229 22:56:31.766705 00680000 ################################################################
10230 22:56:31.766845
10231 22:56:32.009779 00700000 ################################################################
10232 22:56:32.009915
10233 22:56:32.279075 00780000 ################################################################
10234 22:56:32.279224
10235 22:56:32.532637 00800000 ################################################################
10236 22:56:32.532796
10237 22:56:32.766117 00880000 ################################################################
10238 22:56:32.766271
10239 22:56:32.995970 00900000 ################################################################
10240 22:56:32.996118
10241 22:56:33.227865 00980000 ################################################################
10242 22:56:33.228003
10243 22:56:33.486178 00a00000 ################################################################
10244 22:56:33.486317
10245 22:56:33.727931 00a80000 ################################################################
10246 22:56:33.728074
10247 22:56:33.963579 00b00000 ################################################################
10248 22:56:33.963719
10249 22:56:34.195022 00b80000 ################################################################
10250 22:56:34.195164
10251 22:56:34.425474 00c00000 ################################################################
10252 22:56:34.425677
10253 22:56:34.656977 00c80000 ################################################################
10254 22:56:34.657127
10255 22:56:34.888707 00d00000 ################################################################
10256 22:56:34.888858
10257 22:56:35.121310 00d80000 ################################################################
10258 22:56:35.121447
10259 22:56:35.353291 00e00000 ################################################################
10260 22:56:35.353434
10261 22:56:35.589392 00e80000 ################################################################
10262 22:56:35.589558
10263 22:56:35.825108 00f00000 ################################################################
10264 22:56:35.825261
10265 22:56:36.062050 00f80000 ################################################################
10266 22:56:36.062232
10267 22:56:36.303440 01000000 ################################################################
10268 22:56:36.303589
10269 22:56:36.542459 01080000 ################################################################
10270 22:56:36.542617
10271 22:56:36.774539 01100000 ################################################################
10272 22:56:36.774708
10273 22:56:37.009831 01180000 ################################################################
10274 22:56:37.010017
10275 22:56:37.241835 01200000 ################################################################
10276 22:56:37.241996
10277 22:56:37.472781 01280000 ################################################################
10278 22:56:37.472935
10279 22:56:37.703087 01300000 ################################################################
10280 22:56:37.703238
10281 22:56:37.938594 01380000 ################################################################
10282 22:56:37.938773
10283 22:56:38.173018 01400000 ################################################################
10284 22:56:38.173159
10285 22:56:38.410815 01480000 ################################################################
10286 22:56:38.410999
10287 22:56:38.648563 01500000 ################################################################
10288 22:56:38.648712
10289 22:56:38.885969 01580000 ################################################################
10290 22:56:38.886121
10291 22:56:39.120973 01600000 ################################################################
10292 22:56:39.121141
10293 22:56:39.348399 01680000 ################################################################
10294 22:56:39.348581
10295 22:56:39.572699 01700000 ################################################################
10296 22:56:39.572861
10297 22:56:39.797558 01780000 ################################################################
10298 22:56:39.797699
10299 22:56:40.025198 01800000 ################################################################
10300 22:56:40.025352
10301 22:56:40.246617 01880000 ################################################################
10302 22:56:40.246765
10303 22:56:40.467001 01900000 ################################################################
10304 22:56:40.467193
10305 22:56:40.681741 01980000 ################################################################
10306 22:56:40.681924
10307 22:56:40.894364 01a00000 ################################################################
10308 22:56:40.894544
10309 22:56:41.107694 01a80000 ################################################################
10310 22:56:41.107866
10311 22:56:41.277107 01b00000 ##################################################### done.
10312 22:56:41.280336
10313 22:56:41.284092 The bootfile was 28743750 bytes long.
10314 22:56:41.284233
10315 22:56:41.284335 Sending tftp read request... done.
10316 22:56:41.284437
10317 22:56:41.287223 Waiting for the transfer...
10318 22:56:41.287355
10319 22:56:41.290243 00000000 # done.
10320 22:56:41.290328
10321 22:56:41.297110 Command line loaded dynamically from TFTP file: 10597661/tftp-deploy-zpr5obgr/kernel/cmdline
10322 22:56:41.297209
10323 22:56:41.316595 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10597661/extract-nfsrootfs-kuyzofdd,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10324 22:56:41.316747
10325 22:56:41.316824 Loading FIT.
10326 22:56:41.319976
10327 22:56:41.320071 Image ramdisk-1 has 18608845 bytes.
10328 22:56:41.320142
10329 22:56:41.323397 Image fdt-1 has 46924 bytes.
10330 22:56:41.323487
10331 22:56:41.326833 Image kernel-1 has 10085945 bytes.
10332 22:56:41.326918
10333 22:56:41.336447 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10334 22:56:41.336541
10335 22:56:41.353164 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10336 22:56:41.353264
10337 22:56:41.359691 Choosing best match conf-1 for compat google,spherion-rev2.
10338 22:56:41.363384
10339 22:56:41.367089 Connected to device vid:did:rid of 1ae0:0028:00
10340 22:56:41.374799
10341 22:56:41.377723 tpm_get_response: command 0x17b, return code 0x0
10342 22:56:41.377805
10343 22:56:41.381237 ec_init: CrosEC protocol v3 supported (256, 248)
10344 22:56:41.385228
10345 22:56:41.388795 tpm_cleanup: add release locality here.
10346 22:56:41.388905
10347 22:56:41.389001 Shutting down all USB controllers.
10348 22:56:41.392310
10349 22:56:41.392414 Removing current net device
10350 22:56:41.392508
10351 22:56:41.398579 Exiting depthcharge with code 4 at timestamp: 47374858
10352 22:56:41.398666
10353 22:56:41.402133 LZMA decompressing kernel-1 to 0x821a6718
10354 22:56:41.402218
10355 22:56:41.405642 LZMA decompressing kernel-1 to 0x40000000
10356 22:56:42.672512
10357 22:56:42.672713 jumping to kernel
10358 22:56:42.673382 end: 2.2.4 bootloader-commands (duration 00:00:19) [common]
10359 22:56:42.673515 start: 2.2.5 auto-login-action (timeout 00:04:06) [common]
10360 22:56:42.673625 Setting prompt string to ['Linux version [0-9]']
10361 22:56:42.673727 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10362 22:56:42.673823 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10363 22:56:42.754040
10364 22:56:42.756992 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10365 22:56:42.760894 start: 2.2.5.1 login-action (timeout 00:04:06) [common]
10366 22:56:42.761020 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10367 22:56:42.761138 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10368 22:56:42.761246 Using line separator: #'\n'#
10369 22:56:42.761340 No login prompt set.
10370 22:56:42.761429 Parsing kernel messages
10371 22:56:42.761518 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10372 22:56:42.761690 [login-action] Waiting for messages, (timeout 00:04:06)
10373 22:56:42.780257 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j1612582-arm64-gcc-10-defconfig-arm64-chromebook-7xwc5) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Jun 5 22:41:02 UTC 2023
10374 22:56:42.784313 [ 0.000000] random: crng init done
10375 22:56:42.787066 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10376 22:56:42.790602 [ 0.000000] efi: UEFI not found.
10377 22:56:42.800260 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10378 22:56:42.807173 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10379 22:56:42.816994 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10380 22:56:42.826790 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10381 22:56:42.833840 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10382 22:56:42.840195 [ 0.000000] printk: bootconsole [mtk8250] enabled
10383 22:56:42.846745 [ 0.000000] NUMA: No NUMA configuration found
10384 22:56:42.852853 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10385 22:56:42.856275 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcda00-0x23efcffff]
10386 22:56:42.859893 [ 0.000000] Zone ranges:
10387 22:56:42.866432 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10388 22:56:42.869677 [ 0.000000] DMA32 empty
10389 22:56:42.876466 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10390 22:56:42.879468 [ 0.000000] Movable zone start for each node
10391 22:56:42.882808 [ 0.000000] Early memory node ranges
10392 22:56:42.889473 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10393 22:56:42.895847 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10394 22:56:42.902445 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10395 22:56:42.909086 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10396 22:56:42.912532 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10397 22:56:42.922566 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10398 22:56:42.978338 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10399 22:56:42.984924 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10400 22:56:42.991369 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10401 22:56:42.995088 [ 0.000000] psci: probing for conduit method from DT.
10402 22:56:43.001678 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10403 22:56:43.005049 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10404 22:56:43.011444 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10405 22:56:43.014779 [ 0.000000] psci: SMC Calling Convention v1.2
10406 22:56:43.021609 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10407 22:56:43.024539 [ 0.000000] Detected VIPT I-cache on CPU0
10408 22:56:43.030828 [ 0.000000] CPU features: detected: GIC system register CPU interface
10409 22:56:43.037672 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10410 22:56:43.044176 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10411 22:56:43.050859 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10412 22:56:43.060378 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10413 22:56:43.067292 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10414 22:56:43.070968 [ 0.000000] alternatives: applying boot alternatives
10415 22:56:43.077261 [ 0.000000] Fallback order for Node 0: 0
10416 22:56:43.083719 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10417 22:56:43.087305 [ 0.000000] Policy zone: Normal
10418 22:56:43.107018 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10597661/extract-nfsrootfs-kuyzofdd,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10419 22:56:43.116958 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10420 22:56:43.128917 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10421 22:56:43.138506 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10422 22:56:43.145278 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10423 22:56:43.148251 <6>[ 0.000000] software IO TLB: area num 8.
10424 22:56:43.204864 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10425 22:56:43.354044 <6>[ 0.000000] Memory: 7954772K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 397996K reserved, 32768K cma-reserved)
10426 22:56:43.360501 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10427 22:56:43.367468 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10428 22:56:43.370956 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10429 22:56:43.377321 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10430 22:56:43.384157 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10431 22:56:43.387158 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10432 22:56:43.396962 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10433 22:56:43.403909 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10434 22:56:43.410328 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10435 22:56:43.416714 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10436 22:56:43.419972 <6>[ 0.000000] GICv3: 608 SPIs implemented
10437 22:56:43.423400 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10438 22:56:43.430447 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10439 22:56:43.433665 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10440 22:56:43.439874 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10441 22:56:43.453566 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10442 22:56:43.466449 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10443 22:56:43.473335 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10444 22:56:43.481513 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10445 22:56:43.494497 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10446 22:56:43.501205 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10447 22:56:43.507889 <6>[ 0.009181] Console: colour dummy device 80x25
10448 22:56:43.517944 <6>[ 0.013908] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10449 22:56:43.524143 <6>[ 0.024401] pid_max: default: 32768 minimum: 301
10450 22:56:43.527590 <6>[ 0.029275] LSM: Security Framework initializing
10451 22:56:43.534062 <6>[ 0.034212] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10452 22:56:43.544111 <6>[ 0.042028] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10453 22:56:43.553814 <6>[ 0.051457] cblist_init_generic: Setting adjustable number of callback queues.
10454 22:56:43.557226 <6>[ 0.058911] cblist_init_generic: Setting shift to 3 and lim to 1.
10455 22:56:43.563691 <6>[ 0.065289] cblist_init_generic: Setting shift to 3 and lim to 1.
10456 22:56:43.570242 <6>[ 0.071695] rcu: Hierarchical SRCU implementation.
10457 22:56:43.577222 <6>[ 0.076740] rcu: Max phase no-delay instances is 1000.
10458 22:56:43.583876 <6>[ 0.083759] EFI services will not be available.
10459 22:56:43.586920 <6>[ 0.088761] smp: Bringing up secondary CPUs ...
10460 22:56:43.594822 <6>[ 0.093816] Detected VIPT I-cache on CPU1
10461 22:56:43.601434 <6>[ 0.093887] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10462 22:56:43.607758 <6>[ 0.093917] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10463 22:56:43.611435 <6>[ 0.094257] Detected VIPT I-cache on CPU2
10464 22:56:43.617704 <6>[ 0.094310] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10465 22:56:43.627935 <6>[ 0.094326] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10466 22:56:43.630801 <6>[ 0.094587] Detected VIPT I-cache on CPU3
10467 22:56:43.637707 <6>[ 0.094634] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10468 22:56:43.644501 <6>[ 0.094648] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10469 22:56:43.647885 <6>[ 0.094956] CPU features: detected: Spectre-v4
10470 22:56:43.653988 <6>[ 0.094963] CPU features: detected: Spectre-BHB
10471 22:56:43.657706 <6>[ 0.094968] Detected PIPT I-cache on CPU4
10472 22:56:43.663606 <6>[ 0.095025] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10473 22:56:43.670299 <6>[ 0.095042] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10474 22:56:43.677044 <6>[ 0.095346] Detected PIPT I-cache on CPU5
10475 22:56:43.683869 <6>[ 0.095408] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10476 22:56:43.690717 <6>[ 0.095425] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10477 22:56:43.693619 <6>[ 0.095711] Detected PIPT I-cache on CPU6
10478 22:56:43.700893 <6>[ 0.095776] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10479 22:56:43.707063 <6>[ 0.095792] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10480 22:56:43.714165 <6>[ 0.096091] Detected PIPT I-cache on CPU7
10481 22:56:43.720073 <6>[ 0.096156] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10482 22:56:43.726786 <6>[ 0.096172] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10483 22:56:43.730293 <6>[ 0.096220] smp: Brought up 1 node, 8 CPUs
10484 22:56:43.737079 <6>[ 0.237561] SMP: Total of 8 processors activated.
10485 22:56:43.740147 <6>[ 0.242482] CPU features: detected: 32-bit EL0 Support
10486 22:56:43.749851 <6>[ 0.247845] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10487 22:56:43.756560 <6>[ 0.256644] CPU features: detected: Common not Private translations
10488 22:56:43.763532 <6>[ 0.263120] CPU features: detected: CRC32 instructions
10489 22:56:43.766860 <6>[ 0.268472] CPU features: detected: RCpc load-acquire (LDAPR)
10490 22:56:43.772860 <6>[ 0.274431] CPU features: detected: LSE atomic instructions
10491 22:56:43.779337 <6>[ 0.280249] CPU features: detected: Privileged Access Never
10492 22:56:43.786128 <6>[ 0.286065] CPU features: detected: RAS Extension Support
10493 22:56:43.793420 <6>[ 0.291673] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10494 22:56:43.796043 <6>[ 0.298893] CPU: All CPU(s) started at EL2
10495 22:56:43.802843 <6>[ 0.303209] alternatives: applying system-wide alternatives
10496 22:56:43.812571 <6>[ 0.313951] devtmpfs: initialized
10497 22:56:43.828210 <6>[ 0.322952] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10498 22:56:43.834837 <6>[ 0.332913] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10499 22:56:43.841081 <6>[ 0.341146] pinctrl core: initialized pinctrl subsystem
10500 22:56:43.844222 <6>[ 0.347788] DMI not present or invalid.
10501 22:56:43.851078 <6>[ 0.352190] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10502 22:56:43.860966 <6>[ 0.359086] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10503 22:56:43.867392 <6>[ 0.366665] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10504 22:56:43.877380 <6>[ 0.374895] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10505 22:56:43.880932 <6>[ 0.383133] audit: initializing netlink subsys (disabled)
10506 22:56:43.890668 <5>[ 0.388823] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10507 22:56:43.897022 <6>[ 0.389527] thermal_sys: Registered thermal governor 'step_wise'
10508 22:56:43.903855 <6>[ 0.396789] thermal_sys: Registered thermal governor 'power_allocator'
10509 22:56:43.906911 <6>[ 0.403046] cpuidle: using governor menu
10510 22:56:43.913967 <6>[ 0.414007] NET: Registered PF_QIPCRTR protocol family
10511 22:56:43.920139 <6>[ 0.419494] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10512 22:56:43.927285 <6>[ 0.426597] ASID allocator initialised with 32768 entries
10513 22:56:43.929868 <6>[ 0.433158] Serial: AMBA PL011 UART driver
10514 22:56:43.939933 <4>[ 0.441799] Trying to register duplicate clock ID: 134
10515 22:56:43.996003 <6>[ 0.501175] KASLR enabled
10516 22:56:44.010294 <6>[ 0.508968] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10517 22:56:44.016967 <6>[ 0.515981] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10518 22:56:44.023441 <6>[ 0.522470] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10519 22:56:44.029836 <6>[ 0.529476] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10520 22:56:44.036788 <6>[ 0.535963] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10521 22:56:44.043349 <6>[ 0.542969] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10522 22:56:44.049753 <6>[ 0.549457] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10523 22:56:44.056695 <6>[ 0.556462] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10524 22:56:44.059783 <6>[ 0.563986] ACPI: Interpreter disabled.
10525 22:56:44.068792 <6>[ 0.570390] iommu: Default domain type: Translated
10526 22:56:44.075311 <6>[ 0.575503] iommu: DMA domain TLB invalidation policy: strict mode
10527 22:56:44.078431 <5>[ 0.582159] SCSI subsystem initialized
10528 22:56:44.084910 <6>[ 0.586324] usbcore: registered new interface driver usbfs
10529 22:56:44.091939 <6>[ 0.592059] usbcore: registered new interface driver hub
10530 22:56:44.094765 <6>[ 0.597612] usbcore: registered new device driver usb
10531 22:56:44.101511 <6>[ 0.603699] pps_core: LinuxPPS API ver. 1 registered
10532 22:56:44.111507 <6>[ 0.608891] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10533 22:56:44.115033 <6>[ 0.618236] PTP clock support registered
10534 22:56:44.118273 <6>[ 0.622476] EDAC MC: Ver: 3.0.0
10535 22:56:44.125773 <6>[ 0.627619] FPGA manager framework
10536 22:56:44.131995 <6>[ 0.631300] Advanced Linux Sound Architecture Driver Initialized.
10537 22:56:44.135479 <6>[ 0.638069] vgaarb: loaded
10538 22:56:44.141709 <6>[ 0.641252] clocksource: Switched to clocksource arch_sys_counter
10539 22:56:44.145313 <5>[ 0.647692] VFS: Disk quotas dquot_6.6.0
10540 22:56:44.151998 <6>[ 0.651877] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10541 22:56:44.155426 <6>[ 0.659064] pnp: PnP ACPI: disabled
10542 22:56:44.164272 <6>[ 0.665779] NET: Registered PF_INET protocol family
10543 22:56:44.173333 <6>[ 0.671364] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10544 22:56:44.184737 <6>[ 0.683658] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10545 22:56:44.195309 <6>[ 0.692474] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10546 22:56:44.201564 <6>[ 0.700446] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10547 22:56:44.211301 <6>[ 0.709145] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10548 22:56:44.217754 <6>[ 0.718879] TCP: Hash tables configured (established 65536 bind 65536)
10549 22:56:44.224351 <6>[ 0.725736] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10550 22:56:44.234584 <6>[ 0.732937] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10551 22:56:44.241109 <6>[ 0.740642] NET: Registered PF_UNIX/PF_LOCAL protocol family
10552 22:56:44.247888 <6>[ 0.746813] RPC: Registered named UNIX socket transport module.
10553 22:56:44.251224 <6>[ 0.752967] RPC: Registered udp transport module.
10554 22:56:44.257431 <6>[ 0.757898] RPC: Registered tcp transport module.
10555 22:56:44.263872 <6>[ 0.762831] RPC: Registered tcp NFSv4.1 backchannel transport module.
10556 22:56:44.267337 <6>[ 0.769501] PCI: CLS 0 bytes, default 64
10557 22:56:44.270775 <6>[ 0.773840] Unpacking initramfs...
10558 22:56:44.280713 <6>[ 0.777977] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10559 22:56:44.286947 <6>[ 0.786620] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10560 22:56:44.293497 <6>[ 0.795457] kvm [1]: IPA Size Limit: 40 bits
10561 22:56:44.296912 <6>[ 0.799991] kvm [1]: GICv3: no GICV resource entry
10562 22:56:44.303364 <6>[ 0.805014] kvm [1]: disabling GICv2 emulation
10563 22:56:44.309957 <6>[ 0.809706] kvm [1]: GIC system register CPU interface enabled
10564 22:56:44.313586 <6>[ 0.815875] kvm [1]: vgic interrupt IRQ18
10565 22:56:44.320178 <6>[ 0.820226] kvm [1]: VHE mode initialized successfully
10566 22:56:44.323229 <5>[ 0.826683] Initialise system trusted keyrings
10567 22:56:44.330332 <6>[ 0.831488] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10568 22:56:44.339906 <6>[ 0.841781] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10569 22:56:44.346263 <5>[ 0.848213] NFS: Registering the id_resolver key type
10570 22:56:44.349784 <5>[ 0.853536] Key type id_resolver registered
10571 22:56:44.356343 <5>[ 0.857947] Key type id_legacy registered
10572 22:56:44.362716 <6>[ 0.862224] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10573 22:56:44.369584 <6>[ 0.869145] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10574 22:56:44.376019 <6>[ 0.876902] 9p: Installing v9fs 9p2000 file system support
10575 22:56:44.412357 <5>[ 0.914625] Key type asymmetric registered
10576 22:56:44.415637 <5>[ 0.918957] Asymmetric key parser 'x509' registered
10577 22:56:44.425679 <6>[ 0.924096] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10578 22:56:44.429363 <6>[ 0.931709] io scheduler mq-deadline registered
10579 22:56:44.432350 <6>[ 0.936468] io scheduler kyber registered
10580 22:56:44.451340 <6>[ 0.953533] EINJ: ACPI disabled.
10581 22:56:44.484079 <4>[ 0.979303] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10582 22:56:44.494092 <4>[ 0.989946] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10583 22:56:44.508693 <6>[ 1.010663] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10584 22:56:44.516932 <6>[ 1.018845] printk: console [ttyS0] disabled
10585 22:56:44.544667 <6>[ 1.043505] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10586 22:56:44.551766 <6>[ 1.052981] printk: console [ttyS0] enabled
10587 22:56:44.554442 <6>[ 1.052981] printk: console [ttyS0] enabled
10588 22:56:44.561408 <6>[ 1.061876] printk: bootconsole [mtk8250] disabled
10589 22:56:44.564509 <6>[ 1.061876] printk: bootconsole [mtk8250] disabled
10590 22:56:44.570932 <6>[ 1.073115] SuperH (H)SCI(F) driver initialized
10591 22:56:44.574347 <6>[ 1.078391] msm_serial: driver initialized
10592 22:56:44.588987 <6>[ 1.087291] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10593 22:56:44.598379 <6>[ 1.095839] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10594 22:56:44.604933 <6>[ 1.104381] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10595 22:56:44.615028 <6>[ 1.113008] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10596 22:56:44.625078 <6>[ 1.121715] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10597 22:56:44.631886 <6>[ 1.130431] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10598 22:56:44.641413 <6>[ 1.138972] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10599 22:56:44.647819 <6>[ 1.147781] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10600 22:56:44.658185 <6>[ 1.156333] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10601 22:56:44.669628 <6>[ 1.171669] loop: module loaded
10602 22:56:44.676090 <6>[ 1.177735] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10603 22:56:44.699413 <4>[ 1.201112] mtk-pmic-keys: Failed to locate of_node [id: -1]
10604 22:56:44.705675 <6>[ 1.207916] megasas: 07.719.03.00-rc1
10605 22:56:44.715710 <6>[ 1.217617] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10606 22:56:44.722914 <6>[ 1.224637] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10607 22:56:44.739299 <6>[ 1.241252] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10608 22:56:44.800253 <6>[ 1.295454] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10609 22:56:45.096087 <6>[ 1.598215] Freeing initrd memory: 18168K
10610 22:56:45.107658 <6>[ 1.609790] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10611 22:56:45.118858 <6>[ 1.620794] tun: Universal TUN/TAP device driver, 1.6
10612 22:56:45.122384 <6>[ 1.626858] thunder_xcv, ver 1.0
10613 22:56:45.125427 <6>[ 1.630362] thunder_bgx, ver 1.0
10614 22:56:45.128449 <6>[ 1.633856] nicpf, ver 1.0
10615 22:56:45.139175 <6>[ 1.637885] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10616 22:56:45.142503 <6>[ 1.645366] hns3: Copyright (c) 2017 Huawei Corporation.
10617 22:56:45.149126 <6>[ 1.650956] hclge is initializing
10618 22:56:45.152584 <6>[ 1.654530] e1000: Intel(R) PRO/1000 Network Driver
10619 22:56:45.159155 <6>[ 1.659658] e1000: Copyright (c) 1999-2006 Intel Corporation.
10620 22:56:45.162335 <6>[ 1.665677] e1000e: Intel(R) PRO/1000 Network Driver
10621 22:56:45.169313 <6>[ 1.670892] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10622 22:56:45.175596 <6>[ 1.677077] igb: Intel(R) Gigabit Ethernet Network Driver
10623 22:56:45.182678 <6>[ 1.682727] igb: Copyright (c) 2007-2014 Intel Corporation.
10624 22:56:45.189127 <6>[ 1.688563] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10625 22:56:45.195986 <6>[ 1.695081] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10626 22:56:45.198771 <6>[ 1.701542] sky2: driver version 1.30
10627 22:56:45.205579 <6>[ 1.706536] VFIO - User Level meta-driver version: 0.3
10628 22:56:45.213324 <6>[ 1.714766] usbcore: registered new interface driver usb-storage
10629 22:56:45.219678 <6>[ 1.721211] usbcore: registered new device driver onboard-usb-hub
10630 22:56:45.230476 <6>[ 1.730338] mt6397-rtc mt6359-rtc: registered as rtc0
10631 22:56:45.238225 <6>[ 1.735803] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-05T22:56:45 UTC (1686005805)
10632 22:56:45.241532 <6>[ 1.745373] i2c_dev: i2c /dev entries driver
10633 22:56:45.258263 <6>[ 1.757043] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10634 22:56:45.264995 <6>[ 1.767248] sdhci: Secure Digital Host Controller Interface driver
10635 22:56:45.271830 <6>[ 1.773687] sdhci: Copyright(c) Pierre Ossman
10636 22:56:45.278681 <6>[ 1.779089] Synopsys Designware Multimedia Card Interface Driver
10637 22:56:45.281989 <6>[ 1.785724] mmc0: CQHCI version 5.10
10638 22:56:45.288318 <6>[ 1.786246] sdhci-pltfm: SDHCI platform and OF driver helper
10639 22:56:45.295798 <6>[ 1.797682] ledtrig-cpu: registered to indicate activity on CPUs
10640 22:56:45.306123 <6>[ 1.804973] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10641 22:56:45.309781 <6>[ 1.812360] usbcore: registered new interface driver usbhid
10642 22:56:45.316117 <6>[ 1.818192] usbhid: USB HID core driver
10643 22:56:45.322763 <6>[ 1.822438] spi_master spi0: will run message pump with realtime priority
10644 22:56:45.363242 <6>[ 1.858924] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10645 22:56:45.382690 <6>[ 1.874750] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10646 22:56:45.386830 <6>[ 1.888309] mmc0: Command Queue Engine enabled
10647 22:56:45.393117 <6>[ 1.893058] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10648 22:56:45.399624 <6>[ 1.899985] cros-ec-spi spi0.0: Chrome EC device registered
10649 22:56:45.403192 <6>[ 1.900297] mmcblk0: mmc0:0001 DA4128 116 GiB
10650 22:56:45.415178 <6>[ 1.917034] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10651 22:56:45.422152 <6>[ 1.924289] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10652 22:56:45.428809 <6>[ 1.930218] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10653 22:56:45.438944 <6>[ 1.932163] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10654 22:56:45.445727 <6>[ 1.936111] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10655 22:56:45.448521 <6>[ 1.946833] NET: Registered PF_PACKET protocol family
10656 22:56:45.455225 <6>[ 1.956700] 9pnet: Installing 9P2000 support
10657 22:56:45.458706 <5>[ 1.961301] Key type dns_resolver registered
10658 22:56:45.465128 <6>[ 1.966325] registered taskstats version 1
10659 22:56:45.468422 <5>[ 1.970756] Loading compiled-in X.509 certificates
10660 22:56:45.508690 <4>[ 2.004132] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10661 22:56:45.518518 <4>[ 2.014841] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10662 22:56:45.528548 <3>[ 2.027471] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10663 22:56:45.540928 <6>[ 2.043014] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10664 22:56:45.547678 <6>[ 2.049845] xhci-mtk 11200000.usb: xHCI Host Controller
10665 22:56:45.554589 <6>[ 2.055343] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10666 22:56:45.564629 <6>[ 2.063194] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10667 22:56:45.571319 <6>[ 2.072625] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10668 22:56:45.577890 <6>[ 2.078812] xhci-mtk 11200000.usb: xHCI Host Controller
10669 22:56:45.584277 <6>[ 2.084313] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10670 22:56:45.591277 <6>[ 2.091974] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10671 22:56:45.598099 <6>[ 2.099871] hub 1-0:1.0: USB hub found
10672 22:56:45.601373 <6>[ 2.103918] hub 1-0:1.0: 1 port detected
10673 22:56:45.610997 <6>[ 2.108267] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10674 22:56:45.614175 <6>[ 2.117083] hub 2-0:1.0: USB hub found
10675 22:56:45.617957 <6>[ 2.121115] hub 2-0:1.0: 1 port detected
10676 22:56:45.626063 <6>[ 2.128258] mtk-msdc 11f70000.mmc: Got CD GPIO
10677 22:56:45.643004 <6>[ 2.141851] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10678 22:56:45.649474 <6>[ 2.149991] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10679 22:56:45.659492 <4>[ 2.157956] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10680 22:56:45.669514 <6>[ 2.167655] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10681 22:56:45.675962 <6>[ 2.175743] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10682 22:56:45.685777 <6>[ 2.183802] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10683 22:56:45.692804 <6>[ 2.191719] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10684 22:56:45.698941 <6>[ 2.199579] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10685 22:56:45.709281 <6>[ 2.207403] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10686 22:56:45.719203 <6>[ 2.218110] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10687 22:56:45.729329 <6>[ 2.226470] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10688 22:56:45.735879 <6>[ 2.234859] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10689 22:56:45.745964 <6>[ 2.243207] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10690 22:56:45.752504 <6>[ 2.251578] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10691 22:56:45.762473 <6>[ 2.259925] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10692 22:56:45.769453 <6>[ 2.268295] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10693 22:56:45.779077 <6>[ 2.276640] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10694 22:56:45.785600 <6>[ 2.285005] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10695 22:56:45.796072 <6>[ 2.293350] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10696 22:56:45.802524 <6>[ 2.301695] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10697 22:56:45.812098 <6>[ 2.310037] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10698 22:56:45.818669 <6>[ 2.318387] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10699 22:56:45.828553 <6>[ 2.326731] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10700 22:56:45.835577 <6>[ 2.335074] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10701 22:56:45.841953 <6>[ 2.344015] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10702 22:56:45.849461 <6>[ 2.351505] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10703 22:56:45.856532 <6>[ 2.358620] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10704 22:56:45.866790 <6>[ 2.365778] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10705 22:56:45.873377 <6>[ 2.373099] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10706 22:56:45.883201 <6>[ 2.380022] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10707 22:56:45.890189 <6>[ 2.389163] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10708 22:56:45.899737 <6>[ 2.398329] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10709 22:56:45.910094 <6>[ 2.407737] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10710 22:56:45.919438 <6>[ 2.417216] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10711 22:56:45.929580 <6>[ 2.426690] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10712 22:56:45.939578 <6>[ 2.435818] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10713 22:56:45.946165 <6>[ 2.445292] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10714 22:56:45.956286 <6>[ 2.454420] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10715 22:56:45.966334 <6>[ 2.463721] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10716 22:56:45.975729 <6>[ 2.473910] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10717 22:56:45.987127 <6>[ 2.485841] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10718 22:56:45.993680 <6>[ 2.495791] Trying to probe devices needed for running init ...
10719 22:56:46.034516 <6>[ 2.533524] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10720 22:56:46.188928 <6>[ 2.691032] hub 1-1:1.0: USB hub found
10721 22:56:46.192486 <6>[ 2.695491] hub 1-1:1.0: 4 ports detected
10722 22:56:46.314447 <6>[ 2.813547] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10723 22:56:46.339752 <6>[ 2.841730] hub 2-1:1.0: USB hub found
10724 22:56:46.342929 <6>[ 2.846102] hub 2-1:1.0: 3 ports detected
10725 22:56:46.514531 <6>[ 3.013524] usb 1-1.1: new high-speed USB device number 3 using xhci-mtk
10726 22:56:46.645044 <6>[ 3.147223] hub 1-1.1:1.0: USB hub found
10727 22:56:46.648571 <6>[ 3.151504] hub 1-1.1:1.0: 4 ports detected
10728 22:56:46.762257 <6>[ 3.261299] usb 1-1.4: new high-speed USB device number 4 using xhci-mtk
10729 22:56:46.895955 <6>[ 3.397614] hub 1-1.4:1.0: USB hub found
10730 22:56:46.898634 <6>[ 3.402269] hub 1-1.4:1.0: 2 ports detected
10731 22:56:46.974627 <6>[ 3.473522] usb 1-1.1.1: new high-speed USB device number 5 using xhci-mtk
10732 22:56:47.162347 <6>[ 3.661524] usb 1-1.1.4: new full-speed USB device number 6 using xhci-mtk
10733 22:56:47.247487 <3>[ 3.749729] usb 1-1.1.4: device descriptor read/64, error -32
10734 22:56:47.439517 <3>[ 3.941734] usb 1-1.1.4: device descriptor read/64, error -32
10735 22:56:47.634324 <6>[ 4.133521] usb 1-1.4.1: new high-speed USB device number 7 using xhci-mtk
10736 22:56:47.822466 <6>[ 4.321524] usb 1-1.1.4: new full-speed USB device number 8 using xhci-mtk
10737 22:56:47.907136 <3>[ 4.409614] usb 1-1.1.4: device descriptor read/64, error -32
10738 22:56:48.099829 <3>[ 4.601729] usb 1-1.1.4: device descriptor read/64, error -32
10739 22:56:48.212023 <6>[ 4.714085] usb 1-1.1-port4: attempt power cycle
10740 22:56:48.298402 <6>[ 4.797522] usb 1-1.4.2: new high-speed USB device number 9 using xhci-mtk
10741 22:56:48.822315 <6>[ 5.321522] usb 1-1.1.4: new full-speed USB device number 10 using xhci-mtk
10742 22:56:48.828712 <4>[ 5.328970] usb 1-1.1.4: Device not responding to setup address.
10743 22:56:49.039389 <4>[ 5.541787] usb 1-1.1.4: Device not responding to setup address.
10744 22:56:49.251036 <3>[ 5.753514] usb 1-1.1.4: device not accepting address 10, error -71
10745 22:56:49.338253 <6>[ 5.837523] usb 1-1.1.4: new full-speed USB device number 11 using xhci-mtk
10746 22:56:49.344665 <4>[ 5.844944] usb 1-1.1.4: Device not responding to setup address.
10747 22:56:49.555420 <4>[ 6.057787] usb 1-1.1.4: Device not responding to setup address.
10748 22:56:49.766799 <3>[ 6.269511] usb 1-1.1.4: device not accepting address 11, error -71
10749 22:56:49.773743 <3>[ 6.276461] usb 1-1.1-port4: unable to enumerate USB device
10750 22:56:58.287352 <6>[ 14.794084] ALSA device list:
10751 22:56:58.293587 <6>[ 14.797339] No soundcards found.
10752 22:56:58.306715 <6>[ 14.809768] Freeing unused kernel memory: 8384K
10753 22:56:58.309498 <6>[ 14.814700] Run /init as init process
10754 22:56:58.321768 Loading, please wait...
10755 22:56:58.349304 Starting systemd-udevd version 252.6-1
10756 22:56:58.778980 <6>[ 15.279411] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10757 22:56:58.789084 <3>[ 15.288119] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10758 22:56:58.795702 <3>[ 15.296292] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10759 22:56:58.805564 <3>[ 15.304390] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10760 22:56:58.812298 <6>[ 15.304688] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10761 22:56:58.815271 <6>[ 15.305931] remoteproc remoteproc0: scp is available
10762 22:56:58.825612 <4>[ 15.306187] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10763 22:56:58.832257 <6>[ 15.306199] remoteproc remoteproc0: powering up scp
10764 22:56:58.842153 <4>[ 15.306226] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10765 22:56:58.848378 <3>[ 15.306231] remoteproc remoteproc0: request_firmware failed: -2
10766 22:56:58.855392 <4>[ 15.307238] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10767 22:56:58.861862 <4>[ 15.307465] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10768 22:56:58.871922 <6>[ 15.308329] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10769 22:56:58.878791 <3>[ 15.312813] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10770 22:56:58.885602 <6>[ 15.320150] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10771 22:56:58.895132 <3>[ 15.325299] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10772 22:56:58.905336 <6>[ 15.335241] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10773 22:56:58.911788 <3>[ 15.340260] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10774 22:56:58.915059 <6>[ 15.340793] mc: Linux media interface: v0.10
10775 22:56:58.925122 <4>[ 15.358647] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10776 22:56:58.929270 <4>[ 15.358647] Fallback method does not support PEC.
10777 22:56:58.935470 <6>[ 15.359679] videodev: Linux video capture interface: v2.00
10778 22:56:58.942086 <6>[ 15.359762] usbcore: registered new interface driver r8152
10779 22:56:58.948722 <3>[ 15.363588] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10780 22:56:58.958501 <3>[ 15.363601] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10781 22:56:58.965533 <3>[ 15.386727] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10782 22:56:58.975307 <3>[ 15.395430] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10783 22:56:58.985535 <6>[ 15.413219] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10784 22:56:58.991666 <3>[ 15.420263] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10785 22:56:59.001916 <6>[ 15.432298] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10786 22:56:59.008092 <3>[ 15.438421] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10787 22:56:59.018311 <3>[ 15.439123] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10788 22:56:59.024870 <6>[ 15.441539] usb 1-1.1.1: reset high-speed USB device number 5 using xhci-mtk
10789 22:56:59.034898 <6>[ 15.444398] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10790 22:56:59.044534 <3>[ 15.449880] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10791 22:56:59.051040 <3>[ 15.449938] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10792 22:56:59.057420 <6>[ 15.473869] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10793 22:56:59.067366 <3>[ 15.474837] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10794 22:56:59.070789 <6>[ 15.482940] pci_bus 0000:00: root bus resource [bus 00-ff]
10795 22:56:59.080452 <3>[ 15.492221] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10796 22:56:59.087260 <6>[ 15.492643] usbcore: registered new interface driver cdc_ether
10797 22:56:59.093726 <6>[ 15.500316] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10798 22:56:59.100836 <6>[ 15.500762] usbcore: registered new interface driver r8153_ecm
10799 22:56:59.107030 <3>[ 15.510394] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10800 22:56:59.117060 <6>[ 15.518475] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10801 22:56:59.120464 <6>[ 15.519218] Bluetooth: Core ver 2.22
10802 22:56:59.127107 <6>[ 15.519432] NET: Registered PF_BLUETOOTH protocol family
10803 22:56:59.133537 <6>[ 15.519438] Bluetooth: HCI device and connection manager initialized
10804 22:56:59.140299 <6>[ 15.519459] Bluetooth: HCI socket layer initialized
10805 22:56:59.143769 <6>[ 15.519466] Bluetooth: L2CAP socket layer initialized
10806 22:56:59.149909 <6>[ 15.519522] Bluetooth: SCO socket layer initialized
10807 22:56:59.157015 <3>[ 15.527263] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10808 22:56:59.163767 <6>[ 15.534612] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10809 22:56:59.169846 <6>[ 15.535976] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10810 22:56:59.183450 <6>[ 15.537096] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10811 22:56:59.189659 <6>[ 15.537235] usbcore: registered new interface driver uvcvideo
10812 22:56:59.196155 <3>[ 15.543652] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10813 22:56:59.202994 <6>[ 15.551719] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10814 22:56:59.212794 <4>[ 15.561117] r8152 1-1.1.1:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10815 22:56:59.219582 <6>[ 15.561228] usbcore: registered new interface driver btusb
10816 22:56:59.222833 <6>[ 15.567415] pci 0000:00:00.0: supports D1 D2
10817 22:56:59.229550 <6>[ 15.567844] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10818 22:56:59.239557 <4>[ 15.575031] r8152 1-1.1.1:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10819 22:56:59.246590 <6>[ 15.580718] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10820 22:56:59.255648 <4>[ 15.580889] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10821 22:56:59.265706 <6>[ 15.582530] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10822 22:56:59.269433 <6>[ 15.582639] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10823 22:56:59.279144 <6>[ 15.582669] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10824 22:56:59.285503 <6>[ 15.582688] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10825 22:56:59.292288 <6>[ 15.582706] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10826 22:56:59.298949 <6>[ 15.582816] pci 0000:01:00.0: supports D1 D2
10827 22:56:59.305501 <6>[ 15.582819] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10828 22:56:59.311839 <6>[ 15.593514] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10829 22:56:59.318573 <3>[ 15.594965] Bluetooth: hci0: Failed to load firmware file (-2)
10830 22:56:59.325251 <6>[ 15.602111] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10831 22:56:59.331814 <3>[ 15.608164] Bluetooth: hci0: Failed to set up firmware (-2)
10832 22:56:59.338822 <6>[ 15.616248] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10833 22:56:59.348470 <4>[ 15.626145] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10834 22:56:59.358348 <6>[ 15.629979] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10835 22:56:59.361529 <6>[ 15.649401] r8152 1-1.1.1:1.0 eth0: v1.12.13
10836 22:56:59.371651 <6>[ 15.652590] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10837 22:56:59.374599 <6>[ 15.668422] r8152 1-1.1.1:1.0 enxf4f5e850de0a: renamed from eth0
10838 22:56:59.384616 <6>[ 15.672048] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10839 22:56:59.388047 <6>[ 15.892970] pci 0000:00:00.0: PCI bridge to [bus 01]
10840 22:56:59.397921 <6>[ 15.898197] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10841 22:56:59.404382 <6>[ 15.906362] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10842 22:56:59.411253 <6>[ 15.913643] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10843 22:56:59.417576 <6>[ 15.920456] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10844 22:56:59.435064 <5>[ 15.935798] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10845 22:56:59.456448 <5>[ 15.957092] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10846 22:56:59.463503 <4>[ 15.964026] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10847 22:56:59.470113 <6>[ 15.972917] cfg80211: failed to load regulatory.db
10848 22:56:59.512701 <6>[ 16.013209] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10849 22:56:59.519316 <6>[ 16.020753] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10850 22:56:59.543908 <6>[ 16.047528] mt7921e 0000:01:00.0: ASIC revision: 79610010
10851 22:56:59.652723 <4>[ 16.149660] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10852 22:56:59.655443 Begin: Loading essential drivers ... done.
10853 22:56:59.662392 Begin: Running /scripts/init-premount ... done.
10854 22:56:59.668871 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10855 22:56:59.679188 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10856 22:56:59.682065 Device /sys/class/net/enxf4f5e850de0a found
10857 22:56:59.682185 done.
10858 22:56:59.713458 Begin: Waiting up to 180 secs for any network device to become available ... done.
10859 22:56:59.774755 <4>[ 16.272079] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10860 22:56:59.785974 IP-Config: enxf4f5e850de0a hardware address f4:f5:e8:50:de:0a mtu 1500 DHCP
10861 22:56:59.893898 <4>[ 16.391239] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10862 22:57:00.009765 <4>[ 16.507051] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10863 22:57:00.125550 <4>[ 16.623010] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10864 22:57:00.241706 <4>[ 16.738908] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10865 22:57:00.357778 <4>[ 16.854809] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10866 22:57:00.473845 <4>[ 16.970843] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10867 22:57:00.589967 <4>[ 17.086749] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10868 22:57:00.705316 <4>[ 17.202704] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10869 22:57:00.813251 <3>[ 17.316638] mt7921e 0000:01:00.0: hardware init failed
10870 22:57:00.819636 <6>[ 17.320941] r8152 1-1.1.1:1.0 enxf4f5e850de0a: carrier on
10871 22:57:01.732033 IP-Config: no response after 2 secs - giving up
10872 22:57:01.780980 IP-Config: enxf4f5e850de0a hardware address f4:f5:e8:50:de:0a mtu 1500 DHCP
10873 22:57:01.921585 IP-Config: enxf4f5e850de0a complete (dhcp from 192.168.201.1):
10874 22:57:01.928359 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10875 22:57:01.934640 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10876 22:57:01.941193 host : mt8192-asurada-spherion-r0-cbg-9
10877 22:57:01.948381 domain : lava-rack
10878 22:57:01.954332 rootserver: 192.168.201.1 rootpath:
10879 22:57:01.954463 filename :
10880 22:57:01.977871 done.
10881 22:57:01.984327 Begin: Running /scripts/nfs-bottom ... done.
10882 22:57:02.004421 Begin: Running /scripts/init-bottom ... done.
10883 22:57:03.227411 <6>[ 19.731721] NET: Registered PF_INET6 protocol family
10884 22:57:03.234984 <6>[ 19.738745] Segment Routing with IPv6
10885 22:57:03.237728 <6>[ 19.742714] In-situ OAM (IOAM) with IPv6
10886 22:57:03.401875 <30>[ 19.879844] systemd[1]: systemd 252.6-1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10887 22:57:03.408937 <30>[ 19.912157] systemd[1]: Detected architecture arm64.
10888 22:57:03.413769
10889 22:57:03.417030 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10890 22:57:03.417146
10891 22:57:03.445274 <30>[ 19.949471] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10892 22:57:04.028881 <30>[ 20.529829] systemd[1]: Queued start job for default target graphical.target.
10893 22:57:04.058918 <30>[ 20.559465] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10894 22:57:04.065293 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10895 22:57:04.085094 <30>[ 20.586303] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10896 22:57:04.095051 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10897 22:57:04.113272 <30>[ 20.614317] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10898 22:57:04.123281 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10899 22:57:04.141699 <30>[ 20.642709] systemd[1]: Created slice user.slice - User and Session Slice.
10900 22:57:04.148413 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10901 22:57:04.167925 <30>[ 20.665766] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10902 22:57:04.174887 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10903 22:57:04.195953 <30>[ 20.693691] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10904 22:57:04.202488 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10905 22:57:04.230870 <30>[ 20.721972] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10906 22:57:04.240979 <30>[ 20.741823] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10907 22:57:04.247086 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10908 22:57:04.265132 <30>[ 20.765874] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10909 22:57:04.274748 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10910 22:57:04.290010 <30>[ 20.793885] systemd[1]: Reached target paths.target - Path Units.
10911 22:57:04.296429 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10912 22:57:04.317446 <30>[ 20.817856] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10913 22:57:04.323893 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10914 22:57:04.337065 <30>[ 20.841510] systemd[1]: Reached target slices.target - Slice Units.
10915 22:57:04.347113 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10916 22:57:04.362000 <30>[ 20.865882] systemd[1]: Reached target swap.target - Swaps.
10917 22:57:04.368039 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10918 22:57:04.388574 <30>[ 20.889641] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10919 22:57:04.398389 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10920 22:57:04.417753 <30>[ 20.918198] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10921 22:57:04.427310 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10922 22:57:04.446159 <30>[ 20.947212] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10923 22:57:04.455872 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10924 22:57:04.473834 <30>[ 20.974494] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10925 22:57:04.483095 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10926 22:57:04.501007 <30>[ 21.001874] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10927 22:57:04.507461 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10928 22:57:04.525611 <30>[ 21.026436] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10929 22:57:04.535640 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10930 22:57:04.555148 <30>[ 21.056196] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10931 22:57:04.565260 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10932 22:57:04.581123 <30>[ 21.082291] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10933 22:57:04.590919 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10934 22:57:04.628963 <30>[ 21.129851] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10935 22:57:04.635237 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10936 22:57:04.655197 <30>[ 21.156133] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10937 22:57:04.661541 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10938 22:57:04.683049 <30>[ 21.184308] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10939 22:57:04.689979 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10940 22:57:04.715618 <30>[ 21.209863] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10941 22:57:04.727990 <30>[ 21.228743] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10942 22:57:04.737207 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10943 22:57:04.759510 <30>[ 21.260575] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10944 22:57:04.766438 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10945 22:57:04.787988 <30>[ 21.288634] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10946 22:57:04.794342 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10947 22:57:04.815416 <30>[ 21.316645] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10948 22:57:04.825360 Starting [0;1;39mmodpr<6>[ 21.326905] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10949 22:57:04.832013 obe@drm.service[0m - Load Kernel Module drm...
10950 22:57:04.851734 <30>[ 21.352570] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10951 22:57:04.861522 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10952 22:57:04.879606 <30>[ 21.380730] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10953 22:57:04.886596 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10954 22:57:04.908146 <30>[ 21.408806] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10955 22:57:04.914109 Startin<6>[ 21.417745] fuse: init (API version 7.37)
10956 22:57:04.917653 g [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10957 22:57:04.941892 <30>[ 21.442828] systemd[1]: Starting systemd-journald.service - Journal Service...
10958 22:57:04.948489 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10959 22:57:04.970871 <30>[ 21.471763] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10960 22:57:04.976928 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10961 22:57:05.005189 <30>[ 21.502956] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10962 22:57:05.011556 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10963 22:57:05.031980 <30>[ 21.532970] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10964 22:57:05.041781 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10965 22:57:05.063720 <30>[ 21.564754] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10966 22:57:05.070297 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10967 22:57:05.093130 <30>[ 21.593634] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10968 22:57:05.099391 <3>[ 21.596460] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10969 22:57:05.109284 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10970 22:57:05.125060 <30>[ 21.626036] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10971 22:57:05.135244 <3>[ 21.634219] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10972 22:57:05.141566 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10973 22:57:05.160892 <30>[ 21.661980] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10974 22:57:05.167434 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10975 22:57:05.179625 <3>[ 21.680593] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10976 22:57:05.189418 <30>[ 21.690441] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10977 22:57:05.199596 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10978 22:57:05.209797 <3>[ 21.710424] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10979 22:57:05.221700 <30>[ 21.722892] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10980 22:57:05.228432 <30>[ 21.730809] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10981 22:57:05.242291 [[0;32m OK [0m] Finished [0<3>[ 21.741537] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10982 22:57:05.248177 ;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10983 22:57:05.266356 <30>[ 21.766946] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10984 22:57:05.273527 <30>[ 21.774647] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10985 22:57:05.282997 <3>[ 21.776822] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10986 22:57:05.289955 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10987 22:57:05.307020 <30>[ 21.810839] systemd[1]: modprobe@drm.service: Deactivated successfully.
10988 22:57:05.316979 <3>[ 21.816879] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10989 22:57:05.323247 <30>[ 21.818234] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10990 22:57:05.333390 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10991 22:57:05.350208 <3>[ 21.850791] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10992 22:57:05.359725 <30>[ 21.860842] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
10993 22:57:05.369612 <30>[ 21.868838] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
10994 22:57:05.383607 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Lo<3>[ 21.882305] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10995 22:57:05.387059 ad Kernel Module efi_pstore.
10996 22:57:05.403256 <30>[ 21.906843] systemd[1]: modprobe@fuse.service: Deactivated successfully.
10997 22:57:05.413919 <30>[ 21.914301] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
10998 22:57:05.420496 <3>[ 21.915799] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10999 22:57:05.430446 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
11000 22:57:05.450132 <30>[ 21.950639] systemd[1]: modprobe@loop.service: Deactivated successfully.
11001 22:57:05.456241 <30>[ 21.958111] systemd[1]: Finished modprobe@loop.service - Load Kernel Module loop.
11002 22:57:05.470128 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
11003 22:57:05.481303 <30>[ 21.982275] systemd[1]: Started systemd-journald.service - Journal Service.
11004 22:57:05.488341 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
11005 22:57:05.507042 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
11006 22:57:05.525910 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
11007 22:57:05.546406 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
11008 22:57:05.566500 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
11009 22:57:05.609852 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
11010 22:57:05.635629 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
11011 22:57:05.663913 <4>[ 22.158288] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
11012 22:57:05.674122 <3>[ 22.173992] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
11013 22:57:05.680493 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
11014 22:57:05.723045 <46>[ 22.224109] systemd-journald[298]: Received client request to flush runtime journal.
11015 22:57:05.745419 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
11016 22:57:05.769401 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
11017 22:57:05.973302 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
11018 22:57:06.228959 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
11019 22:57:06.245209 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
11020 22:57:06.264656 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
11021 22:57:06.529281 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
11022 22:57:06.549279 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
11023 22:57:06.605120 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
11024 22:57:06.668643 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
11025 22:57:06.684445 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
11026 22:57:06.700078 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
11027 22:57:06.748910 Starting [0;1;39msystemd-binfmt.se…et Up Additional Binary Formats...
11028 22:57:06.773194 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
11029 22:57:06.793773 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-bi… Set Up Additional Binary Formats.
11030 22:57:06.808783 See 'systemctl status systemd-binfmt.service' for details.
11031 22:57:06.947490 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
11032 22:57:07.010051 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
11033 22:57:07.077213 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
11034 22:57:07.449515 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
11035 22:57:07.449709 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11036 22:57:07.449825 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11037 22:57:07.795483 <6>[ 24.300052] remoteproc remoteproc0: powering up scp
11038 22:57:07.808895 [[0;32m OK [0m] Reached target [0;1;39mblue<4>[ 24.309002] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
11039 22:57:07.818904 tooth.target[0m<3>[ 24.319636] remoteproc remoteproc0: request_firmware failed: -2
11040 22:57:07.824967 - Bluetooth Sup<3>[ 24.327145] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
11041 22:57:07.828452 port.
11042 22:57:07.845088 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11043 22:57:07.892999 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11044 22:57:08.129459 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11045 22:57:08.149299 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
11046 22:57:08.192891 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
11047 22:57:08.229854 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11048 22:57:08.277509 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
11049 22:57:08.293290 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
11050 22:57:08.517366 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
11051 22:57:08.569283 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
11052 22:57:08.591728 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
11053 22:57:08.715075 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
11054 22:57:08.733649 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
11055 22:57:08.973072 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
11056 22:57:08.980859 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
11057 22:57:09.003453 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
11058 22:57:09.021645 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
11059 22:57:09.040417 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
11060 22:57:09.058036 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
11061 22:57:09.078026 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
11062 22:57:09.096357 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
11063 22:57:09.111985 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11064 22:57:09.129040 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11065 22:57:09.147852 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11066 22:57:09.164280 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11067 22:57:09.209495 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11068 22:57:09.239399 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
11069 22:57:09.333230 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11070 22:57:09.355670 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11071 22:57:09.537574 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11072 22:57:09.577366 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11073 22:57:09.596783 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11074 22:57:09.613234 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11075 22:57:09.633181 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11076 22:57:09.655036 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
11077 22:57:09.678542 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11078 22:57:09.702255 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11079 22:57:09.720914 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11080 22:57:09.749861 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11081 22:57:09.788884 Starting [0;1;39msystemd-hostnamed.service[0m - Hostname Service...
11082 22:57:09.822032 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11083 22:57:09.920960 [[0;32m OK [0m] Started [0;1;39msystemd-hostnamed.service[0m - Hostname Service.
11084 22:57:10.086756
11085 22:57:10.087097
11086 22:57:10.090175 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11087 22:57:10.090453
11088 22:57:10.093496 debian-bookworm-arm64 login: root (automatic login)
11089 22:57:10.093754
11090 22:57:10.094008
11091 22:57:10.325918 Linux debian-bookworm-arm64 6.1.31 #1 SMP PREEMPT Mon Jun 5 22:41:02 UTC 2023 aarch64
11092 22:57:10.326055
11093 22:57:10.332926 The programs included with the Debian GNU/Linux system are free software;
11094 22:57:10.339868 the exact distribution terms for each program are described in the
11095 22:57:10.343051 individual files in /usr/share/doc/*/copyright.
11096 22:57:10.343474
11097 22:57:10.350034 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11098 22:57:10.352863 permitted by applicable law.
11099 22:57:11.275390 Matched prompt #10: / #
11101 22:57:11.276554 Setting prompt string to ['/ #']
11102 22:57:11.277051 end: 2.2.5.1 login-action (duration 00:00:29) [common]
11104 22:57:11.278070 end: 2.2.5 auto-login-action (duration 00:00:29) [common]
11105 22:57:11.278549 start: 2.2.6 expect-shell-connection (timeout 00:03:37) [common]
11106 22:57:11.279005 Setting prompt string to ['/ #']
11107 22:57:11.279470 Forcing a shell prompt, looking for ['/ #']
11109 22:57:11.330476 / #
11110 22:57:11.331151 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11111 22:57:11.331763 Waiting using forced prompt support (timeout 00:02:30)
11112 22:57:11.336830
11113 22:57:11.337578 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11114 22:57:11.338073 start: 2.2.7 export-device-env (timeout 00:03:37) [common]
11116 22:57:11.439236 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10597661/extract-nfsrootfs-kuyzofdd'
11117 22:57:11.445855 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10597661/extract-nfsrootfs-kuyzofdd'
11119 22:57:11.547918 / # export NFS_SERVER_IP='192.168.201.1'
11120 22:57:11.553453 export NFS_SERVER_IP='192.168.201.1'
11121 22:57:11.553877 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11122 22:57:11.554030 end: 2.2 depthcharge-retry (duration 00:01:23) [common]
11123 22:57:11.554154 end: 2 depthcharge-action (duration 00:01:23) [common]
11124 22:57:11.554279 start: 3 lava-test-retry (timeout 00:07:58) [common]
11125 22:57:11.554400 start: 3.1 lava-test-shell (timeout 00:07:58) [common]
11126 22:57:11.554508 Using namespace: common
11128 22:57:11.654892 / # #
11129 22:57:11.655097 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11130 22:57:11.659952 #
11131 22:57:11.660227 Using /lava-10597661
11133 22:57:11.760558 / # export SHELL=/bin/bash
11134 22:57:11.765727 export SHELL=/bin/bash
11136 22:57:11.866287 / # . /lava-10597661/environment
11137 22:57:11.871639 . /lava-10597661/environment
11139 22:57:11.976505 / # /lava-10597661/bin/lava-test-runner /lava-10597661/0
11140 22:57:11.976971 Test shell timeout: 10s (minimum of the action and connection timeout)
11141 22:57:11.982094 /lava-10597661/bin/lava-test-runner /lava-10597661/0
11142 22:57:12.229696 + export TESTRUN_ID=0_timesync-off
11143 22:57:12.233222 + TESTRUN_ID=0_timesync-off
11144 22:57:12.236025 + cd /lava-10597661/0/tests/0_timesync-off
11145 22:57:12.239683 ++ cat uuid
11146 22:57:12.239805 + UUID=10597661_1.6.2.3.1
11147 22:57:12.243008 + set +x
11148 22:57:12.246077 <LAVA_SIGNAL_STARTRUN 0_timesync-off 10597661_1.6.2.3.1>
11149 22:57:12.246387 Received signal: <STARTRUN> 0_timesync-off 10597661_1.6.2.3.1
11150 22:57:12.246522 Starting test lava.0_timesync-off (10597661_1.6.2.3.1)
11151 22:57:12.246672 Skipping test definition patterns.
11152 22:57:12.249476 + systemctl stop systemd-timesyncd
11153 22:57:12.283571 + set +x
11154 22:57:12.286704 <LAVA_SIGNAL_ENDRUN 0_timesync-off 10597661_1.6.2.3.1>
11155 22:57:12.287053 Received signal: <ENDRUN> 0_timesync-off 10597661_1.6.2.3.1
11156 22:57:12.287225 Ending use of test pattern.
11157 22:57:12.287379 Ending test lava.0_timesync-off (10597661_1.6.2.3.1), duration 0.04
11159 22:57:12.363869 + export TESTRUN_ID=1_kselftest-alsa
11160 22:57:12.367276 + TESTRUN_ID=1_kselftest-alsa
11161 22:57:12.373861 + cd /lava-10597661/0/tests/1_kselftest-alsa
11162 22:57:12.374057 ++ cat uuid
11163 22:57:12.376840 + UUID=10597661_1.6.2.3.5
11164 22:57:12.376994 + set +x
11165 22:57:12.380388 <LAVA_SIGNAL_STARTRUN 1_kselftest-alsa 10597661_1.6.2.3.5>
11166 22:57:12.380753 Received signal: <STARTRUN> 1_kselftest-alsa 10597661_1.6.2.3.5
11167 22:57:12.380901 Starting test lava.1_kselftest-alsa (10597661_1.6.2.3.5)
11168 22:57:12.381055 Skipping test definition patterns.
11169 22:57:12.383688 + cd ./automated/linux/kselftest/
11170 22:57:12.409939 + ./kselftest.sh -c alsa -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1314-g1ab0ac1d7e2e3/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11171 22:57:12.430089 INFO: install_deps skipped
11172 22:57:12.902415 --2023-06-05 22:57:13-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1314-g1ab0ac1d7e2e3/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11173 22:57:12.908928 Resolving storage.kernelci.org (storage.kernelci.org)... 52.250.1.28
11174 22:57:13.040206 Connecting to storage.kernelci.org (storage.kernelci.org)|52.250.1.28|:80... connected.
11175 22:57:13.180799 HTTP request sent, awaiting response... 200 OK
11176 22:57:13.184304 Length: 2703120 (2.6M) [application/octet-stream]
11177 22:57:13.203515 Saving to: 'kselftest.tar.xz'
11178 22:57:13.203698
11179 22:57:13.203797
11180 22:57:13.462933 kselftest.tar.xz 0%[ ] 0 --.-KB/s
11181 22:57:13.744081 kselftest.tar.xz 1%[ ] 47.81K 189KB/s
11182 22:57:14.216628 kselftest.tar.xz 8%[> ] 217.50K 413KB/s
11183 22:57:14.506968 kselftest.tar.xz 31%[=====> ] 822.71K 833KB/s
11184 22:57:14.599194 kselftest.tar.xz 91%[=================> ] 2.35M 1.85MB/s
11185 22:57:14.605997 kselftest.tar.xz 100%[===================>] 2.58M 1.89MB/s in 1.4s
11186 22:57:14.606099
11187 22:57:14.935255 2023-06-05 22:57:15 (1.89 MB/s) - 'kselftest.tar.xz' saved [2703120/2703120]
11188 22:57:14.935442
11189 22:57:29.942968 <6>[ 46.453330] vpu: disabling
11190 22:57:29.945929 <6>[ 46.456386] vproc2: disabling
11191 22:57:29.949031 <6>[ 46.459664] vproc1: disabling
11192 22:57:29.952833 <6>[ 46.462930] vaud18: disabling
11193 22:57:29.959043 <6>[ 46.466339] vsram_others: disabling
11194 22:57:29.962671 <6>[ 46.470220] va09: disabling
11195 22:57:29.965784 <6>[ 46.473326] vsram_md: disabling
11196 22:57:29.968808 <6>[ 46.476811] Vgpu: disabling
11197 22:57:43.160933 skiplist:
11198 22:57:43.164057 ========================================
11199 22:57:43.167186 ========================================
11200 22:57:43.199447 alsa:mixer-test
11201 22:57:43.216032 ============== Tests to run ===============
11202 22:57:43.216229 alsa:mixer-test
11203 22:57:43.219057 ===========End Tests to run ===============
11204 22:57:43.297854 <12>[ 59.806720] kselftest: Running tests in alsa
11205 22:57:43.305553 TAP version 13
11206 22:57:43.318145 1..1
11207 22:57:43.329973 # selftests: alsa: mixer-test
11208 22:57:43.736806 # TAP version 13
11209 22:57:43.736977 # 1..0
11210 22:57:43.743338 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:0 error:0
11211 22:57:43.746381 ok 1 selftests: alsa: mixer-test
11212 22:57:44.345337 alsa_mixer-test pass
11213 22:57:44.376695 + ../../utils/send-to-lava.sh ./output/result.txt
11214 22:57:44.426604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test RESULT=pass>
11215 22:57:44.426741 + set +x
11216 22:57:44.426992 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test RESULT=pass
11218 22:57:44.433305 <LAVA_SIGNAL_ENDRUN 1_kselftest-alsa 10597661_1.6.2.3.5>
11219 22:57:44.433555 Received signal: <ENDRUN> 1_kselftest-alsa 10597661_1.6.2.3.5
11220 22:57:44.433629 Ending use of test pattern.
11221 22:57:44.433699 Ending test lava.1_kselftest-alsa (10597661_1.6.2.3.5), duration 32.05
11223 22:57:44.436246 <LAVA_TEST_RUNNER EXIT>
11224 22:57:44.436565 ok: lava_test_shell seems to have completed
11225 22:57:44.436661 alsa_mixer-test: pass
11226 22:57:44.436750 end: 3.1 lava-test-shell (duration 00:00:33) [common]
11227 22:57:44.436833 end: 3 lava-test-retry (duration 00:00:33) [common]
11228 22:57:44.436920 start: 4 finalize (timeout 00:07:25) [common]
11229 22:57:44.437006 start: 4.1 power-off (timeout 00:00:30) [common]
11230 22:57:44.437162 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=off'
11231 22:57:44.516384 >> Command sent successfully.
11232 22:57:44.518651 Returned 0 in 0 seconds
11233 22:57:44.619031 end: 4.1 power-off (duration 00:00:00) [common]
11235 22:57:44.619427 start: 4.2 read-feedback (timeout 00:07:25) [common]
11236 22:57:44.619712 Listened to connection for namespace 'common' for up to 1s
11237 22:57:45.620578 Finalising connection for namespace 'common'
11238 22:57:45.620749 Disconnecting from shell: Finalise
11239 22:57:45.620836 / #
11240 22:57:45.721150 end: 4.2 read-feedback (duration 00:00:01) [common]
11241 22:57:45.721327 end: 4 finalize (duration 00:00:01) [common]
11242 22:57:45.721465 Cleaning after the job
11243 22:57:45.721567 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597661/tftp-deploy-zpr5obgr/ramdisk
11244 22:57:45.723917 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597661/tftp-deploy-zpr5obgr/kernel
11245 22:57:45.733305 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597661/tftp-deploy-zpr5obgr/dtb
11246 22:57:45.733581 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597661/tftp-deploy-zpr5obgr/nfsrootfs
11247 22:57:45.810928 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597661/tftp-deploy-zpr5obgr/modules
11248 22:57:45.816595 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10597661
11249 22:57:46.356378 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10597661
11250 22:57:46.356619 Job finished correctly