Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 41
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 30
1 22:58:25.974626 lava-dispatcher, installed at version: 2023.05.1
2 22:58:25.974850 start: 0 validate
3 22:58:25.974990 Start time: 2023-06-05 22:58:25.974981+00:00 (UTC)
4 22:58:25.975125 Using caching service: 'http://localhost/cache/?uri=%s'
5 22:58:25.975264 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230527.0%2Farm64%2Finitrd.cpio.gz exists
6 22:58:26.261494 Using caching service: 'http://localhost/cache/?uri=%s'
7 22:58:26.261690 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1314-g1ab0ac1d7e2e3%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 22:58:26.551954 Using caching service: 'http://localhost/cache/?uri=%s'
9 22:58:26.552213 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1314-g1ab0ac1d7e2e3%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 22:58:26.842286 Using caching service: 'http://localhost/cache/?uri=%s'
11 22:58:26.842519 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230527.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 22:58:27.124108 Using caching service: 'http://localhost/cache/?uri=%s'
13 22:58:27.124308 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1314-g1ab0ac1d7e2e3%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 22:58:27.410381 validate duration: 1.44
16 22:58:27.410652 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 22:58:27.410754 start: 1.1 download-retry (timeout 00:10:00) [common]
18 22:58:27.410845 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 22:58:27.410974 Not decompressing ramdisk as can be used compressed.
20 22:58:27.411059 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230527.0/arm64/initrd.cpio.gz
21 22:58:27.411125 saving as /var/lib/lava/dispatcher/tmp/10597701/tftp-deploy-gimehd2h/ramdisk/initrd.cpio.gz
22 22:58:27.411189 total size: 4665601 (4MB)
23 22:58:27.412420 progress 0% (0MB)
24 22:58:27.413904 progress 5% (0MB)
25 22:58:27.415193 progress 10% (0MB)
26 22:58:27.416558 progress 15% (0MB)
27 22:58:27.417912 progress 20% (0MB)
28 22:58:27.419248 progress 25% (1MB)
29 22:58:27.420566 progress 30% (1MB)
30 22:58:27.421825 progress 35% (1MB)
31 22:58:27.423116 progress 40% (1MB)
32 22:58:27.424584 progress 45% (2MB)
33 22:58:27.425863 progress 50% (2MB)
34 22:58:27.427121 progress 55% (2MB)
35 22:58:27.428412 progress 60% (2MB)
36 22:58:27.429663 progress 65% (2MB)
37 22:58:27.431007 progress 70% (3MB)
38 22:58:27.432275 progress 75% (3MB)
39 22:58:27.433500 progress 80% (3MB)
40 22:58:27.434891 progress 85% (3MB)
41 22:58:27.436183 progress 90% (4MB)
42 22:58:27.437408 progress 95% (4MB)
43 22:58:27.438658 progress 100% (4MB)
44 22:58:27.438815 4MB downloaded in 0.03s (161.09MB/s)
45 22:58:27.438966 end: 1.1.1 http-download (duration 00:00:00) [common]
47 22:58:27.439208 end: 1.1 download-retry (duration 00:00:00) [common]
48 22:58:27.439296 start: 1.2 download-retry (timeout 00:10:00) [common]
49 22:58:27.439385 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 22:58:27.439527 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1314-g1ab0ac1d7e2e3/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 22:58:27.439600 saving as /var/lib/lava/dispatcher/tmp/10597701/tftp-deploy-gimehd2h/kernel/Image
52 22:58:27.439661 total size: 45746688 (43MB)
53 22:58:27.439722 No compression specified
54 22:58:27.440900 progress 0% (0MB)
55 22:58:27.452622 progress 5% (2MB)
56 22:58:27.464727 progress 10% (4MB)
57 22:58:27.476620 progress 15% (6MB)
58 22:58:27.488438 progress 20% (8MB)
59 22:58:27.500468 progress 25% (10MB)
60 22:58:27.512115 progress 30% (13MB)
61 22:58:27.524073 progress 35% (15MB)
62 22:58:27.535961 progress 40% (17MB)
63 22:58:27.547903 progress 45% (19MB)
64 22:58:27.559665 progress 50% (21MB)
65 22:58:27.571449 progress 55% (24MB)
66 22:58:27.583208 progress 60% (26MB)
67 22:58:27.595017 progress 65% (28MB)
68 22:58:27.606700 progress 70% (30MB)
69 22:58:27.618605 progress 75% (32MB)
70 22:58:27.630157 progress 80% (34MB)
71 22:58:27.642036 progress 85% (37MB)
72 22:58:27.653820 progress 90% (39MB)
73 22:58:27.665682 progress 95% (41MB)
74 22:58:27.677226 progress 100% (43MB)
75 22:58:27.677393 43MB downloaded in 0.24s (183.52MB/s)
76 22:58:27.677545 end: 1.2.1 http-download (duration 00:00:00) [common]
78 22:58:27.677788 end: 1.2 download-retry (duration 00:00:00) [common]
79 22:58:27.677882 start: 1.3 download-retry (timeout 00:10:00) [common]
80 22:58:27.677971 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 22:58:27.678114 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1314-g1ab0ac1d7e2e3/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 22:58:27.678185 saving as /var/lib/lava/dispatcher/tmp/10597701/tftp-deploy-gimehd2h/dtb/mt8192-asurada-spherion-r0.dtb
83 22:58:27.678247 total size: 46924 (0MB)
84 22:58:27.678307 No compression specified
85 22:58:27.679401 progress 69% (0MB)
86 22:58:27.679676 progress 100% (0MB)
87 22:58:27.679831 0MB downloaded in 0.00s (28.30MB/s)
88 22:58:27.679954 end: 1.3.1 http-download (duration 00:00:00) [common]
90 22:58:27.680195 end: 1.3 download-retry (duration 00:00:00) [common]
91 22:58:27.680282 start: 1.4 download-retry (timeout 00:10:00) [common]
92 22:58:27.680367 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 22:58:27.680488 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230527.0/arm64/full.rootfs.tar.xz
94 22:58:27.680557 saving as /var/lib/lava/dispatcher/tmp/10597701/tftp-deploy-gimehd2h/nfsrootfs/full.rootfs.tar
95 22:58:27.680619 total size: 200770336 (191MB)
96 22:58:27.680679 Using unxz to decompress xz
97 22:58:27.684385 progress 0% (0MB)
98 22:58:28.227786 progress 5% (9MB)
99 22:58:28.751791 progress 10% (19MB)
100 22:58:29.353357 progress 15% (28MB)
101 22:58:29.725029 progress 20% (38MB)
102 22:58:30.062240 progress 25% (47MB)
103 22:58:30.689992 progress 30% (57MB)
104 22:58:31.264075 progress 35% (67MB)
105 22:58:31.886757 progress 40% (76MB)
106 22:58:32.484861 progress 45% (86MB)
107 22:58:33.096208 progress 50% (95MB)
108 22:58:33.747390 progress 55% (105MB)
109 22:58:34.441099 progress 60% (114MB)
110 22:58:34.566965 progress 65% (124MB)
111 22:58:34.717902 progress 70% (134MB)
112 22:58:34.819462 progress 75% (143MB)
113 22:58:34.898543 progress 80% (153MB)
114 22:58:34.972334 progress 85% (162MB)
115 22:58:35.074392 progress 90% (172MB)
116 22:58:35.369874 progress 95% (181MB)
117 22:58:35.980625 progress 100% (191MB)
118 22:58:35.985570 191MB downloaded in 8.30s (23.05MB/s)
119 22:58:35.985903 end: 1.4.1 http-download (duration 00:00:08) [common]
121 22:58:35.986324 end: 1.4 download-retry (duration 00:00:08) [common]
122 22:58:35.986455 start: 1.5 download-retry (timeout 00:09:51) [common]
123 22:58:35.986578 start: 1.5.1 http-download (timeout 00:09:51) [common]
124 22:58:35.986786 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1314-g1ab0ac1d7e2e3/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 22:58:35.986899 saving as /var/lib/lava/dispatcher/tmp/10597701/tftp-deploy-gimehd2h/modules/modules.tar
126 22:58:35.986995 total size: 8552396 (8MB)
127 22:58:35.987091 Using unxz to decompress xz
128 22:58:35.990616 progress 0% (0MB)
129 22:58:36.011793 progress 5% (0MB)
130 22:58:36.035608 progress 10% (0MB)
131 22:58:36.066318 progress 15% (1MB)
132 22:58:36.092137 progress 20% (1MB)
133 22:58:36.117016 progress 25% (2MB)
134 22:58:36.142298 progress 30% (2MB)
135 22:58:36.169287 progress 35% (2MB)
136 22:58:36.195883 progress 40% (3MB)
137 22:58:36.222727 progress 45% (3MB)
138 22:58:36.249196 progress 50% (4MB)
139 22:58:36.274938 progress 55% (4MB)
140 22:58:36.299938 progress 60% (4MB)
141 22:58:36.325372 progress 65% (5MB)
142 22:58:36.352038 progress 70% (5MB)
143 22:58:36.377793 progress 75% (6MB)
144 22:58:36.405131 progress 80% (6MB)
145 22:58:36.431413 progress 85% (6MB)
146 22:58:36.457464 progress 90% (7MB)
147 22:58:36.482009 progress 95% (7MB)
148 22:58:36.508351 progress 100% (8MB)
149 22:58:36.515711 8MB downloaded in 0.53s (15.43MB/s)
150 22:58:36.516047 end: 1.5.1 http-download (duration 00:00:01) [common]
152 22:58:36.516340 end: 1.5 download-retry (duration 00:00:01) [common]
153 22:58:36.516437 start: 1.6 prepare-tftp-overlay (timeout 00:09:51) [common]
154 22:58:36.516553 start: 1.6.1 extract-nfsrootfs (timeout 00:09:51) [common]
155 22:58:39.884509 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/10597701/extract-nfsrootfs-vfhoriyx
156 22:58:39.884716 end: 1.6.1 extract-nfsrootfs (duration 00:00:03) [common]
157 22:58:39.884821 start: 1.6.2 lava-overlay (timeout 00:09:48) [common]
158 22:58:39.885014 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10597701/lava-overlay-7satbszp
159 22:58:39.885158 makedir: /var/lib/lava/dispatcher/tmp/10597701/lava-overlay-7satbszp/lava-10597701/bin
160 22:58:39.885267 makedir: /var/lib/lava/dispatcher/tmp/10597701/lava-overlay-7satbszp/lava-10597701/tests
161 22:58:39.885371 makedir: /var/lib/lava/dispatcher/tmp/10597701/lava-overlay-7satbszp/lava-10597701/results
162 22:58:39.885472 Creating /var/lib/lava/dispatcher/tmp/10597701/lava-overlay-7satbszp/lava-10597701/bin/lava-add-keys
163 22:58:39.885613 Creating /var/lib/lava/dispatcher/tmp/10597701/lava-overlay-7satbszp/lava-10597701/bin/lava-add-sources
164 22:58:39.885739 Creating /var/lib/lava/dispatcher/tmp/10597701/lava-overlay-7satbszp/lava-10597701/bin/lava-background-process-start
165 22:58:39.885864 Creating /var/lib/lava/dispatcher/tmp/10597701/lava-overlay-7satbszp/lava-10597701/bin/lava-background-process-stop
166 22:58:39.885987 Creating /var/lib/lava/dispatcher/tmp/10597701/lava-overlay-7satbszp/lava-10597701/bin/lava-common-functions
167 22:58:39.886108 Creating /var/lib/lava/dispatcher/tmp/10597701/lava-overlay-7satbszp/lava-10597701/bin/lava-echo-ipv4
168 22:58:39.886229 Creating /var/lib/lava/dispatcher/tmp/10597701/lava-overlay-7satbszp/lava-10597701/bin/lava-install-packages
169 22:58:39.886349 Creating /var/lib/lava/dispatcher/tmp/10597701/lava-overlay-7satbszp/lava-10597701/bin/lava-installed-packages
170 22:58:39.886467 Creating /var/lib/lava/dispatcher/tmp/10597701/lava-overlay-7satbszp/lava-10597701/bin/lava-os-build
171 22:58:39.886586 Creating /var/lib/lava/dispatcher/tmp/10597701/lava-overlay-7satbszp/lava-10597701/bin/lava-probe-channel
172 22:58:39.886709 Creating /var/lib/lava/dispatcher/tmp/10597701/lava-overlay-7satbszp/lava-10597701/bin/lava-probe-ip
173 22:58:39.886829 Creating /var/lib/lava/dispatcher/tmp/10597701/lava-overlay-7satbszp/lava-10597701/bin/lava-target-ip
174 22:58:39.886949 Creating /var/lib/lava/dispatcher/tmp/10597701/lava-overlay-7satbszp/lava-10597701/bin/lava-target-mac
175 22:58:39.887069 Creating /var/lib/lava/dispatcher/tmp/10597701/lava-overlay-7satbszp/lava-10597701/bin/lava-target-storage
176 22:58:39.887194 Creating /var/lib/lava/dispatcher/tmp/10597701/lava-overlay-7satbszp/lava-10597701/bin/lava-test-case
177 22:58:39.887316 Creating /var/lib/lava/dispatcher/tmp/10597701/lava-overlay-7satbszp/lava-10597701/bin/lava-test-event
178 22:58:39.887435 Creating /var/lib/lava/dispatcher/tmp/10597701/lava-overlay-7satbszp/lava-10597701/bin/lava-test-feedback
179 22:58:39.887559 Creating /var/lib/lava/dispatcher/tmp/10597701/lava-overlay-7satbszp/lava-10597701/bin/lava-test-raise
180 22:58:39.887677 Creating /var/lib/lava/dispatcher/tmp/10597701/lava-overlay-7satbszp/lava-10597701/bin/lava-test-reference
181 22:58:39.887797 Creating /var/lib/lava/dispatcher/tmp/10597701/lava-overlay-7satbszp/lava-10597701/bin/lava-test-runner
182 22:58:39.887916 Creating /var/lib/lava/dispatcher/tmp/10597701/lava-overlay-7satbszp/lava-10597701/bin/lava-test-set
183 22:58:39.888199 Creating /var/lib/lava/dispatcher/tmp/10597701/lava-overlay-7satbszp/lava-10597701/bin/lava-test-shell
184 22:58:39.888329 Updating /var/lib/lava/dispatcher/tmp/10597701/lava-overlay-7satbszp/lava-10597701/bin/lava-add-keys (debian)
185 22:58:39.888486 Updating /var/lib/lava/dispatcher/tmp/10597701/lava-overlay-7satbszp/lava-10597701/bin/lava-add-sources (debian)
186 22:58:39.888632 Updating /var/lib/lava/dispatcher/tmp/10597701/lava-overlay-7satbszp/lava-10597701/bin/lava-install-packages (debian)
187 22:58:39.888776 Updating /var/lib/lava/dispatcher/tmp/10597701/lava-overlay-7satbszp/lava-10597701/bin/lava-installed-packages (debian)
188 22:58:39.888914 Updating /var/lib/lava/dispatcher/tmp/10597701/lava-overlay-7satbszp/lava-10597701/bin/lava-os-build (debian)
189 22:58:39.889031 Creating /var/lib/lava/dispatcher/tmp/10597701/lava-overlay-7satbszp/lava-10597701/environment
190 22:58:39.889132 LAVA metadata
191 22:58:39.889203 - LAVA_JOB_ID=10597701
192 22:58:39.889268 - LAVA_DISPATCHER_IP=192.168.201.1
193 22:58:39.889369 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:48) [common]
194 22:58:39.889436 skipped lava-vland-overlay
195 22:58:39.889511 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 22:58:39.889591 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:48) [common]
197 22:58:39.889652 skipped lava-multinode-overlay
198 22:58:39.889726 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 22:58:39.889804 start: 1.6.2.3 test-definition (timeout 00:09:48) [common]
200 22:58:39.889878 Loading test definitions
201 22:58:39.889969 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:48) [common]
202 22:58:39.890042 Using /lava-10597701 at stage 0
203 22:58:39.890339 uuid=10597701_1.6.2.3.1 testdef=None
204 22:58:39.890427 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 22:58:39.890513 start: 1.6.2.3.2 test-overlay (timeout 00:09:48) [common]
206 22:58:39.890955 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 22:58:39.891181 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:48) [common]
209 22:58:39.891729 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 22:58:39.891964 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:48) [common]
212 22:58:39.892524 runner path: /var/lib/lava/dispatcher/tmp/10597701/lava-overlay-7satbszp/lava-10597701/0/tests/0_timesync-off test_uuid 10597701_1.6.2.3.1
213 22:58:39.892675 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 22:58:39.892903 start: 1.6.2.3.5 git-repo-action (timeout 00:09:48) [common]
216 22:58:39.892978 Using /lava-10597701 at stage 0
217 22:58:39.893074 Fetching tests from https://github.com/kernelci/test-definitions.git
218 22:58:39.893151 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/10597701/lava-overlay-7satbszp/lava-10597701/0/tests/1_kselftest-tpm2'
219 22:58:45.799267 Running '/usr/bin/git checkout kernelci.org
220 22:58:45.943506 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/10597701/lava-overlay-7satbszp/lava-10597701/0/tests/1_kselftest-tpm2/automated/linux/kselftest/kselftest.yaml
221 22:58:45.944262 uuid=10597701_1.6.2.3.5 testdef=None
222 22:58:45.944414 end: 1.6.2.3.5 git-repo-action (duration 00:00:06) [common]
224 22:58:45.944660 start: 1.6.2.3.6 test-overlay (timeout 00:09:41) [common]
225 22:58:45.945398 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 22:58:45.945631 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:41) [common]
228 22:58:45.946616 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 22:58:45.946882 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:41) [common]
231 22:58:45.947836 runner path: /var/lib/lava/dispatcher/tmp/10597701/lava-overlay-7satbszp/lava-10597701/0/tests/1_kselftest-tpm2 test_uuid 10597701_1.6.2.3.5
232 22:58:45.947928 BOARD='mt8192-asurada-spherion-r0'
233 22:58:45.947992 BRANCH='cip'
234 22:58:45.948074 SKIPFILE='/dev/null'
235 22:58:45.948147 SKIP_INSTALL='True'
236 22:58:45.948204 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1314-g1ab0ac1d7e2e3/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 22:58:45.948262 TST_CASENAME=''
238 22:58:45.948318 TST_CMDFILES='tpm2'
239 22:58:45.948459 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 22:58:45.948668 Creating lava-test-runner.conf files
242 22:58:45.948731 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10597701/lava-overlay-7satbszp/lava-10597701/0 for stage 0
243 22:58:45.948820 - 0_timesync-off
244 22:58:45.948889 - 1_kselftest-tpm2
245 22:58:45.948985 end: 1.6.2.3 test-definition (duration 00:00:06) [common]
246 22:58:45.949074 start: 1.6.2.4 compress-overlay (timeout 00:09:41) [common]
247 22:58:53.493643 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 22:58:53.493802 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:34) [common]
249 22:58:53.493895 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 22:58:53.493995 end: 1.6.2 lava-overlay (duration 00:00:14) [common]
251 22:58:53.494085 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:34) [common]
252 22:58:53.616887 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 22:58:53.617247 start: 1.6.4 extract-modules (timeout 00:09:34) [common]
254 22:58:53.617362 extracting modules file /var/lib/lava/dispatcher/tmp/10597701/tftp-deploy-gimehd2h/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10597701/extract-nfsrootfs-vfhoriyx
255 22:58:53.829363 extracting modules file /var/lib/lava/dispatcher/tmp/10597701/tftp-deploy-gimehd2h/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10597701/extract-overlay-ramdisk-vfo537s8/ramdisk
256 22:58:54.040463 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 22:58:54.040629 start: 1.6.5 apply-overlay-tftp (timeout 00:09:33) [common]
258 22:58:54.040723 [common] Applying overlay to NFS
259 22:58:54.040795 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10597701/compress-overlay-lkziuoun/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10597701/extract-nfsrootfs-vfhoriyx
260 22:58:54.929202 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 22:58:54.929373 start: 1.6.6 configure-preseed-file (timeout 00:09:32) [common]
262 22:58:54.929469 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 22:58:54.929559 start: 1.6.7 compress-ramdisk (timeout 00:09:32) [common]
264 22:58:54.929642 Building ramdisk /var/lib/lava/dispatcher/tmp/10597701/extract-overlay-ramdisk-vfo537s8/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10597701/extract-overlay-ramdisk-vfo537s8/ramdisk
265 22:58:55.194936 >> 117807 blocks
266 22:58:57.091302 rename /var/lib/lava/dispatcher/tmp/10597701/extract-overlay-ramdisk-vfo537s8/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10597701/tftp-deploy-gimehd2h/ramdisk/ramdisk.cpio.gz
267 22:58:57.091711 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 22:58:57.091827 start: 1.6.8 prepare-kernel (timeout 00:09:30) [common]
269 22:58:57.091931 start: 1.6.8.1 prepare-fit (timeout 00:09:30) [common]
270 22:58:57.092056 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10597701/tftp-deploy-gimehd2h/kernel/Image'
271 22:59:08.676934 Returned 0 in 11 seconds
272 22:59:08.777557 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10597701/tftp-deploy-gimehd2h/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10597701/tftp-deploy-gimehd2h/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10597701/tftp-deploy-gimehd2h/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10597701/tftp-deploy-gimehd2h/kernel/image.itb
273 22:59:09.093572 output: FIT description: Kernel Image image with one or more FDT blobs
274 22:59:09.093922 output: Created: Mon Jun 5 23:59:09 2023
275 22:59:09.094001 output: Image 0 (kernel-1)
276 22:59:09.094067 output: Description:
277 22:59:09.094130 output: Created: Mon Jun 5 23:59:09 2023
278 22:59:09.094194 output: Type: Kernel Image
279 22:59:09.094255 output: Compression: lzma compressed
280 22:59:09.094315 output: Data Size: 10085945 Bytes = 9849.56 KiB = 9.62 MiB
281 22:59:09.094375 output: Architecture: AArch64
282 22:59:09.094431 output: OS: Linux
283 22:59:09.094487 output: Load Address: 0x00000000
284 22:59:09.094544 output: Entry Point: 0x00000000
285 22:59:09.094600 output: Hash algo: crc32
286 22:59:09.094654 output: Hash value: b2943ff2
287 22:59:09.094707 output: Image 1 (fdt-1)
288 22:59:09.094760 output: Description: mt8192-asurada-spherion-r0
289 22:59:09.094813 output: Created: Mon Jun 5 23:59:09 2023
290 22:59:09.094866 output: Type: Flat Device Tree
291 22:59:09.094919 output: Compression: uncompressed
292 22:59:09.094972 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
293 22:59:09.095025 output: Architecture: AArch64
294 22:59:09.095078 output: Hash algo: crc32
295 22:59:09.095131 output: Hash value: 1df858fa
296 22:59:09.095184 output: Image 2 (ramdisk-1)
297 22:59:09.095236 output: Description: unavailable
298 22:59:09.095289 output: Created: Mon Jun 5 23:59:09 2023
299 22:59:09.095342 output: Type: RAMDisk Image
300 22:59:09.095395 output: Compression: Unknown Compression
301 22:59:09.095463 output: Data Size: 17637423 Bytes = 17224.05 KiB = 16.82 MiB
302 22:59:09.095529 output: Architecture: AArch64
303 22:59:09.095612 output: OS: Linux
304 22:59:09.095665 output: Load Address: unavailable
305 22:59:09.095718 output: Entry Point: unavailable
306 22:59:09.095789 output: Hash algo: crc32
307 22:59:09.095854 output: Hash value: 07f17ffb
308 22:59:09.095907 output: Default Configuration: 'conf-1'
309 22:59:09.095982 output: Configuration 0 (conf-1)
310 22:59:09.096044 output: Description: mt8192-asurada-spherion-r0
311 22:59:09.096113 output: Kernel: kernel-1
312 22:59:09.096198 output: Init Ramdisk: ramdisk-1
313 22:59:09.096251 output: FDT: fdt-1
314 22:59:09.096319 output: Loadables: kernel-1
315 22:59:09.096373 output:
316 22:59:09.096572 end: 1.6.8.1 prepare-fit (duration 00:00:12) [common]
317 22:59:09.096671 end: 1.6.8 prepare-kernel (duration 00:00:12) [common]
318 22:59:09.096777 end: 1.6 prepare-tftp-overlay (duration 00:00:33) [common]
319 22:59:09.096878 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:18) [common]
320 22:59:09.096970 No LXC device requested
321 22:59:09.097049 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 22:59:09.097135 start: 1.8 deploy-device-env (timeout 00:09:18) [common]
323 22:59:09.097243 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 22:59:09.097330 Checking files for TFTP limit of 4294967296 bytes.
325 22:59:09.097843 end: 1 tftp-deploy (duration 00:00:42) [common]
326 22:59:09.097988 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 22:59:09.098081 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 22:59:09.098257 substitutions:
329 22:59:09.098341 - {DTB}: 10597701/tftp-deploy-gimehd2h/dtb/mt8192-asurada-spherion-r0.dtb
330 22:59:09.098436 - {INITRD}: 10597701/tftp-deploy-gimehd2h/ramdisk/ramdisk.cpio.gz
331 22:59:09.098497 - {KERNEL}: 10597701/tftp-deploy-gimehd2h/kernel/Image
332 22:59:09.098555 - {LAVA_MAC}: None
333 22:59:09.098613 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/10597701/extract-nfsrootfs-vfhoriyx
334 22:59:09.098670 - {NFS_SERVER_IP}: 192.168.201.1
335 22:59:09.098726 - {PRESEED_CONFIG}: None
336 22:59:09.098799 - {PRESEED_LOCAL}: None
337 22:59:09.098867 - {RAMDISK}: 10597701/tftp-deploy-gimehd2h/ramdisk/ramdisk.cpio.gz
338 22:59:09.098954 - {ROOT_PART}: None
339 22:59:09.099009 - {ROOT}: None
340 22:59:09.099078 - {SERVER_IP}: 192.168.201.1
341 22:59:09.099146 - {TEE}: None
342 22:59:09.099220 Parsed boot commands:
343 22:59:09.099288 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 22:59:09.099461 Parsed boot commands: tftpboot 192.168.201.1 10597701/tftp-deploy-gimehd2h/kernel/image.itb 10597701/tftp-deploy-gimehd2h/kernel/cmdline
345 22:59:09.099599 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 22:59:09.099715 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 22:59:09.099809 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 22:59:09.099900 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 22:59:09.099974 Not connected, no need to disconnect.
350 22:59:09.100056 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 22:59:09.100141 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 22:59:09.100238 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-2'
353 22:59:09.103524 Setting prompt string to ['lava-test: # ']
354 22:59:09.103886 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 22:59:09.103992 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 22:59:09.104122 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 22:59:09.104265 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 22:59:09.104512 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=reboot'
359 22:59:14.235279 >> Command sent successfully.
360 22:59:14.237493 Returned 0 in 5 seconds
361 22:59:14.337848 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 22:59:14.338217 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 22:59:14.338354 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 22:59:14.338473 Setting prompt string to 'Starting depthcharge on Spherion...'
366 22:59:14.338573 Changing prompt to 'Starting depthcharge on Spherion...'
367 22:59:14.338678 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 22:59:14.339077 [Enter `^Ec?' for help]
369 22:59:14.511627
370 22:59:14.511799
371 22:59:14.511904 F0: 102B 0000
372 22:59:14.512006
373 22:59:14.512130 F3: 1001 0000 [0200]
374 22:59:14.514924
375 22:59:14.515002 F3: 1001 0000
376 22:59:14.515067
377 22:59:14.515129 F7: 102D 0000
378 22:59:14.515188
379 22:59:14.518320 F1: 0000 0000
380 22:59:14.518406
381 22:59:14.518474 V0: 0000 0000 [0001]
382 22:59:14.518536
383 22:59:14.522075 00: 0007 8000
384 22:59:14.522278
385 22:59:14.522393 01: 0000 0000
386 22:59:14.522508
387 22:59:14.525251 BP: 0C00 0209 [0000]
388 22:59:14.525360
389 22:59:14.525439 G0: 1182 0000
390 22:59:14.525513
391 22:59:14.528389 EC: 0000 0021 [4000]
392 22:59:14.528487
393 22:59:14.528564 S7: 0000 0000 [0000]
394 22:59:14.528663
395 22:59:14.532329 CC: 0000 0000 [0001]
396 22:59:14.532435
397 22:59:14.532519 T0: 0000 0040 [010F]
398 22:59:14.532598
399 22:59:14.532672 Jump to BL
400 22:59:14.535072
401 22:59:14.558252
402 22:59:14.558387
403 22:59:14.558485
404 22:59:14.565826 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 22:59:14.569255 ARM64: Exception handlers installed.
406 22:59:14.573025 ARM64: Testing exception
407 22:59:14.576656 ARM64: Done test exception
408 22:59:14.583225 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 22:59:14.593522 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 22:59:14.600282 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 22:59:14.610496 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 22:59:14.617108 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 22:59:14.623162 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 22:59:14.635233 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 22:59:14.642199 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 22:59:14.661175 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 22:59:14.664498 WDT: Last reset was cold boot
418 22:59:14.667977 SPI1(PAD0) initialized at 2873684 Hz
419 22:59:14.671216 SPI5(PAD0) initialized at 992727 Hz
420 22:59:14.674886 VBOOT: Loading verstage.
421 22:59:14.681378 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 22:59:14.684580 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 22:59:14.688221 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 22:59:14.691001 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 22:59:14.698744 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 22:59:14.705193 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 22:59:14.716199 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
428 22:59:14.716314
429 22:59:14.716412
430 22:59:14.726191 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 22:59:14.729510 ARM64: Exception handlers installed.
432 22:59:14.733015 ARM64: Testing exception
433 22:59:14.733117 ARM64: Done test exception
434 22:59:14.740414 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 22:59:14.743881 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 22:59:14.757807 Probing TPM: . done!
437 22:59:14.757885 TPM ready after 0 ms
438 22:59:14.766961 Connected to device vid:did:rid of 1ae0:0028:00
439 22:59:14.773768 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
440 22:59:14.830696 Initialized TPM device CR50 revision 0
441 22:59:14.841217 tlcl_send_startup: Startup return code is 0
442 22:59:14.841317 TPM: setup succeeded
443 22:59:14.853130 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 22:59:14.861428 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 22:59:14.873728 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 22:59:14.884026 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 22:59:14.887068 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 22:59:14.891637 in-header: 03 07 00 00 08 00 00 00
449 22:59:14.895324 in-data: aa e4 47 04 13 02 00 00
450 22:59:14.899074 Chrome EC: UHEPI supported
451 22:59:14.905884 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 22:59:14.909713 in-header: 03 95 00 00 08 00 00 00
453 22:59:14.913141 in-data: 18 20 20 08 00 00 00 00
454 22:59:14.913227 Phase 1
455 22:59:14.917023 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 22:59:14.924407 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 22:59:14.927702 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 22:59:14.931506 Recovery requested (1009000e)
459 22:59:14.941007 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 22:59:14.946271 tlcl_extend: response is 0
461 22:59:14.955695 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 22:59:14.960804 tlcl_extend: response is 0
463 22:59:14.967966 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 22:59:14.988245 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
465 22:59:14.994890 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 22:59:14.994978
467 22:59:14.995045
468 22:59:15.004592 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 22:59:15.008000 ARM64: Exception handlers installed.
470 22:59:15.011397 ARM64: Testing exception
471 22:59:15.011486 ARM64: Done test exception
472 22:59:15.033651 pmic_efuse_setting: Set efuses in 11 msecs
473 22:59:15.036520 pmwrap_interface_init: Select PMIF_VLD_RDY
474 22:59:15.043222 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 22:59:15.046927 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 22:59:15.053517 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 22:59:15.056986 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 22:59:15.060872 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 22:59:15.068798 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 22:59:15.072269 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 22:59:15.076050 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 22:59:15.079532 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 22:59:15.087386 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 22:59:15.090989 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 22:59:15.094573 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 22:59:15.098128 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 22:59:15.105578 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 22:59:15.113174 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 22:59:15.116311 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 22:59:15.123703 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 22:59:15.127689 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 22:59:15.135052 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 22:59:15.138848 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 22:59:15.145667 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 22:59:15.149583 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 22:59:15.157278 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 22:59:15.160731 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 22:59:15.168319 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 22:59:15.172240 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 22:59:15.179439 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 22:59:15.182849 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 22:59:15.186250 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 22:59:15.193521 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 22:59:15.197011 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 22:59:15.204542 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 22:59:15.208043 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 22:59:15.211973 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 22:59:15.219057 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 22:59:15.222621 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 22:59:15.226399 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 22:59:15.233712 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 22:59:15.237094 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 22:59:15.241213 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 22:59:15.244197 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 22:59:15.251711 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 22:59:15.254957 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 22:59:15.258619 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 22:59:15.261916 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 22:59:15.269201 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 22:59:15.273192 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 22:59:15.276549 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 22:59:15.280448 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 22:59:15.283964 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 22:59:15.287515 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 22:59:15.294780 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 22:59:15.305681 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 22:59:15.309852 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 22:59:15.316552 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 22:59:15.328049 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 22:59:15.331669 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 22:59:15.335640 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 22:59:15.338360 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 22:59:15.346817 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6b, sec=0x3
534 22:59:15.350191 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 22:59:15.358559 [RTC]rtc_osc_init,62: osc32con val = 0xde6b
536 22:59:15.361785 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 22:59:15.370737 [RTC]rtc_get_frequency_meter,154: input=15, output=851
538 22:59:15.380872 [RTC]rtc_get_frequency_meter,154: input=7, output=725
539 22:59:15.389848 [RTC]rtc_get_frequency_meter,154: input=11, output=788
540 22:59:15.399685 [RTC]rtc_get_frequency_meter,154: input=13, output=819
541 22:59:15.408800 [RTC]rtc_get_frequency_meter,154: input=12, output=804
542 22:59:15.418150 [RTC]rtc_get_frequency_meter,154: input=11, output=789
543 22:59:15.428189 [RTC]rtc_get_frequency_meter,154: input=12, output=805
544 22:59:15.432317 [RTC]rtc_eosc_cali,47: left: 11, middle: 11, right: 12
545 22:59:15.436128 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6b
546 22:59:15.439949 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 22:59:15.447361 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
548 22:59:15.451013 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 22:59:15.455049 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
550 22:59:15.458191 ADC[4]: Raw value=904433 ID=7
551 22:59:15.458276 ADC[3]: Raw value=213546 ID=1
552 22:59:15.462130 RAM Code: 0x71
553 22:59:15.465739 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 22:59:15.469501 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 22:59:15.479984 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
556 22:59:15.484173 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
557 22:59:15.487530 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 22:59:15.491269 in-header: 03 07 00 00 08 00 00 00
559 22:59:15.495140 in-data: aa e4 47 04 13 02 00 00
560 22:59:15.499027 Chrome EC: UHEPI supported
561 22:59:15.506953 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 22:59:15.510083 in-header: 03 95 00 00 08 00 00 00
563 22:59:15.514078 in-data: 18 20 20 08 00 00 00 00
564 22:59:15.517984 MRC: failed to locate region type 0.
565 22:59:15.521190 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 22:59:15.525098 DRAM-K: Running full calibration
567 22:59:15.532160 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
568 22:59:15.532246 header.status = 0x0
569 22:59:15.535732 header.version = 0x6 (expected: 0x6)
570 22:59:15.539538 header.size = 0xd00 (expected: 0xd00)
571 22:59:15.543260 header.flags = 0x0
572 22:59:15.546968 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 22:59:15.567024 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
574 22:59:15.574130 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 22:59:15.574216 dram_init: ddr_geometry: 2
576 22:59:15.577733 [EMI] MDL number = 2
577 22:59:15.581165 [EMI] Get MDL freq = 0
578 22:59:15.581250 dram_init: ddr_type: 0
579 22:59:15.585029 is_discrete_lpddr4: 1
580 22:59:15.588901 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 22:59:15.588986
582 22:59:15.589052
583 22:59:15.589113 [Bian_co] ETT version 0.0.0.1
584 22:59:15.596189 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
585 22:59:15.596300
586 22:59:15.600039 dramc_set_vcore_voltage set vcore to 650000
587 22:59:15.600155 Read voltage for 800, 4
588 22:59:15.603389 Vio18 = 0
589 22:59:15.603497 Vcore = 650000
590 22:59:15.603607 Vdram = 0
591 22:59:15.603701 Vddq = 0
592 22:59:15.607473 Vmddr = 0
593 22:59:15.607613 dram_init: config_dvfs: 1
594 22:59:15.613732 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 22:59:15.617453 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 22:59:15.620781 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
597 22:59:15.627062 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
598 22:59:15.630750 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
599 22:59:15.634872 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
600 22:59:15.634963 MEM_TYPE=3, freq_sel=18
601 22:59:15.638163 sv_algorithm_assistance_LP4_1600
602 22:59:15.642065 ============ PULL DRAM RESETB DOWN ============
603 22:59:15.648939 ========== PULL DRAM RESETB DOWN end =========
604 22:59:15.652198 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 22:59:15.655531 ===================================
606 22:59:15.658803 LPDDR4 DRAM CONFIGURATION
607 22:59:15.658887 ===================================
608 22:59:15.662678 EX_ROW_EN[0] = 0x0
609 22:59:15.665998 EX_ROW_EN[1] = 0x0
610 22:59:15.666083 LP4Y_EN = 0x0
611 22:59:15.669311 WORK_FSP = 0x0
612 22:59:15.669395 WL = 0x2
613 22:59:15.672581 RL = 0x2
614 22:59:15.672665 BL = 0x2
615 22:59:15.675969 RPST = 0x0
616 22:59:15.676076 RD_PRE = 0x0
617 22:59:15.678895 WR_PRE = 0x1
618 22:59:15.678979 WR_PST = 0x0
619 22:59:15.682519 DBI_WR = 0x0
620 22:59:15.682603 DBI_RD = 0x0
621 22:59:15.685804 OTF = 0x1
622 22:59:15.688763 ===================================
623 22:59:15.692187 ===================================
624 22:59:15.692271 ANA top config
625 22:59:15.695446 ===================================
626 22:59:15.698760 DLL_ASYNC_EN = 0
627 22:59:15.702179 ALL_SLAVE_EN = 1
628 22:59:15.705537 NEW_RANK_MODE = 1
629 22:59:15.705627 DLL_IDLE_MODE = 1
630 22:59:15.708867 LP45_APHY_COMB_EN = 1
631 22:59:15.712237 TX_ODT_DIS = 1
632 22:59:15.715510 NEW_8X_MODE = 1
633 22:59:15.718656 ===================================
634 22:59:15.722009 ===================================
635 22:59:15.725668 data_rate = 1600
636 22:59:15.725752 CKR = 1
637 22:59:15.728967 DQ_P2S_RATIO = 8
638 22:59:15.731944 ===================================
639 22:59:15.735812 CA_P2S_RATIO = 8
640 22:59:15.739656 DQ_CA_OPEN = 0
641 22:59:15.742713 DQ_SEMI_OPEN = 0
642 22:59:15.742791 CA_SEMI_OPEN = 0
643 22:59:15.746399 CA_FULL_RATE = 0
644 22:59:15.749408 DQ_CKDIV4_EN = 1
645 22:59:15.752522 CA_CKDIV4_EN = 1
646 22:59:15.756244 CA_PREDIV_EN = 0
647 22:59:15.756327 PH8_DLY = 0
648 22:59:15.759483 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 22:59:15.763000 DQ_AAMCK_DIV = 4
650 22:59:15.765849 CA_AAMCK_DIV = 4
651 22:59:15.769152 CA_ADMCK_DIV = 4
652 22:59:15.773114 DQ_TRACK_CA_EN = 0
653 22:59:15.776438 CA_PICK = 800
654 22:59:15.776525 CA_MCKIO = 800
655 22:59:15.779628 MCKIO_SEMI = 0
656 22:59:15.783593 PLL_FREQ = 3068
657 22:59:15.787048 DQ_UI_PI_RATIO = 32
658 22:59:15.791043 CA_UI_PI_RATIO = 0
659 22:59:15.791228 ===================================
660 22:59:15.795198 ===================================
661 22:59:15.798290 memory_type:LPDDR4
662 22:59:15.798471 GP_NUM : 10
663 22:59:15.802232 SRAM_EN : 1
664 22:59:15.805769 MD32_EN : 0
665 22:59:15.805910 ===================================
666 22:59:15.809550 [ANA_INIT] >>>>>>>>>>>>>>
667 22:59:15.813032 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 22:59:15.816920 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 22:59:15.820232 ===================================
670 22:59:15.823665 data_rate = 1600,PCW = 0X7600
671 22:59:15.826847 ===================================
672 22:59:15.830325 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 22:59:15.833735 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 22:59:15.840380 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 22:59:15.843623 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 22:59:15.847149 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 22:59:15.850435 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 22:59:15.853553 [ANA_INIT] flow start
679 22:59:15.856926 [ANA_INIT] PLL >>>>>>>>
680 22:59:15.857661 [ANA_INIT] PLL <<<<<<<<
681 22:59:15.860498 [ANA_INIT] MIDPI >>>>>>>>
682 22:59:15.863625 [ANA_INIT] MIDPI <<<<<<<<
683 22:59:15.864250 [ANA_INIT] DLL >>>>>>>>
684 22:59:15.866683 [ANA_INIT] flow end
685 22:59:15.870538 ============ LP4 DIFF to SE enter ============
686 22:59:15.873802 ============ LP4 DIFF to SE exit ============
687 22:59:15.876809 [ANA_INIT] <<<<<<<<<<<<<
688 22:59:15.880077 [Flow] Enable top DCM control >>>>>
689 22:59:15.883686 [Flow] Enable top DCM control <<<<<
690 22:59:15.887077 Enable DLL master slave shuffle
691 22:59:15.893392 ==============================================================
692 22:59:15.893510 Gating Mode config
693 22:59:15.899616 ==============================================================
694 22:59:15.899734 Config description:
695 22:59:15.909618 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 22:59:15.916138 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 22:59:15.922949 SELPH_MODE 0: By rank 1: By Phase
698 22:59:15.926172 ==============================================================
699 22:59:15.929467 GAT_TRACK_EN = 1
700 22:59:15.933302 RX_GATING_MODE = 2
701 22:59:15.936860 RX_GATING_TRACK_MODE = 2
702 22:59:15.939467 SELPH_MODE = 1
703 22:59:15.942950 PICG_EARLY_EN = 1
704 22:59:15.946291 VALID_LAT_VALUE = 1
705 22:59:15.953115 ==============================================================
706 22:59:15.956215 Enter into Gating configuration >>>>
707 22:59:15.959984 Exit from Gating configuration <<<<
708 22:59:15.962958 Enter into DVFS_PRE_config >>>>>
709 22:59:15.973117 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 22:59:15.976064 Exit from DVFS_PRE_config <<<<<
711 22:59:15.979495 Enter into PICG configuration >>>>
712 22:59:15.982760 Exit from PICG configuration <<<<
713 22:59:15.986510 [RX_INPUT] configuration >>>>>
714 22:59:15.986760 [RX_INPUT] configuration <<<<<
715 22:59:15.993130 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 22:59:15.999332 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 22:59:16.002945 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 22:59:16.009370 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 22:59:16.015970 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 22:59:16.022811 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 22:59:16.026384 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 22:59:16.029505 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 22:59:16.036585 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 22:59:16.040092 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 22:59:16.043359 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 22:59:16.049899 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 22:59:16.053143 ===================================
728 22:59:16.053790 LPDDR4 DRAM CONFIGURATION
729 22:59:16.056413 ===================================
730 22:59:16.059449 EX_ROW_EN[0] = 0x0
731 22:59:16.060028 EX_ROW_EN[1] = 0x0
732 22:59:16.063197 LP4Y_EN = 0x0
733 22:59:16.063730 WORK_FSP = 0x0
734 22:59:16.066342 WL = 0x2
735 22:59:16.066975 RL = 0x2
736 22:59:16.069341 BL = 0x2
737 22:59:16.069947 RPST = 0x0
738 22:59:16.073323 RD_PRE = 0x0
739 22:59:16.076212 WR_PRE = 0x1
740 22:59:16.076806 WR_PST = 0x0
741 22:59:16.079222 DBI_WR = 0x0
742 22:59:16.079775 DBI_RD = 0x0
743 22:59:16.083263 OTF = 0x1
744 22:59:16.086420 ===================================
745 22:59:16.089623 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 22:59:16.092676 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 22:59:16.096220 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 22:59:16.099638 ===================================
749 22:59:16.102991 LPDDR4 DRAM CONFIGURATION
750 22:59:16.106025 ===================================
751 22:59:16.109173 EX_ROW_EN[0] = 0x10
752 22:59:16.109738 EX_ROW_EN[1] = 0x0
753 22:59:16.112707 LP4Y_EN = 0x0
754 22:59:16.113255 WORK_FSP = 0x0
755 22:59:16.116331 WL = 0x2
756 22:59:16.116900 RL = 0x2
757 22:59:16.119695 BL = 0x2
758 22:59:16.120336 RPST = 0x0
759 22:59:16.123069 RD_PRE = 0x0
760 22:59:16.123523 WR_PRE = 0x1
761 22:59:16.125972 WR_PST = 0x0
762 22:59:16.126566 DBI_WR = 0x0
763 22:59:16.129237 DBI_RD = 0x0
764 22:59:16.129844 OTF = 0x1
765 22:59:16.132937 ===================================
766 22:59:16.139103 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 22:59:16.144736 nWR fixed to 40
768 22:59:16.147822 [ModeRegInit_LP4] CH0 RK0
769 22:59:16.148339 [ModeRegInit_LP4] CH0 RK1
770 22:59:16.150811 [ModeRegInit_LP4] CH1 RK0
771 22:59:16.154572 [ModeRegInit_LP4] CH1 RK1
772 22:59:16.155055 match AC timing 13
773 22:59:16.161205 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
774 22:59:16.164083 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 22:59:16.167419 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 22:59:16.174397 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 22:59:16.177214 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 22:59:16.180543 [EMI DOE] emi_dcm 0
779 22:59:16.184101 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 22:59:16.184634 ==
781 22:59:16.187939 Dram Type= 6, Freq= 0, CH_0, rank 0
782 22:59:16.190981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
783 22:59:16.191448 ==
784 22:59:16.197359 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 22:59:16.204003 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 22:59:16.211815 [CA 0] Center 37 (7~68) winsize 62
787 22:59:16.215279 [CA 1] Center 37 (6~68) winsize 63
788 22:59:16.218528 [CA 2] Center 34 (4~65) winsize 62
789 22:59:16.221825 [CA 3] Center 35 (4~66) winsize 63
790 22:59:16.225162 [CA 4] Center 33 (3~64) winsize 62
791 22:59:16.228644 [CA 5] Center 33 (3~64) winsize 62
792 22:59:16.229083
793 22:59:16.231747 [CmdBusTrainingLP45] Vref(ca) range 1: 34
794 22:59:16.232326
795 22:59:16.235172 [CATrainingPosCal] consider 1 rank data
796 22:59:16.238436 u2DelayCellTimex100 = 270/100 ps
797 22:59:16.241629 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
798 22:59:16.248500 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
799 22:59:16.251899 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
800 22:59:16.255069 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
801 22:59:16.258454 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
802 22:59:16.261688 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
803 22:59:16.262130
804 22:59:16.265072 CA PerBit enable=1, Macro0, CA PI delay=33
805 22:59:16.265620
806 22:59:16.268489 [CBTSetCACLKResult] CA Dly = 33
807 22:59:16.268929 CS Dly: 5 (0~36)
808 22:59:16.271785 ==
809 22:59:16.274708 Dram Type= 6, Freq= 0, CH_0, rank 1
810 22:59:16.277971 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 22:59:16.278664 ==
812 22:59:16.281630 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 22:59:16.288482 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 22:59:16.298166 [CA 0] Center 38 (7~69) winsize 63
815 22:59:16.301451 [CA 1] Center 37 (7~68) winsize 62
816 22:59:16.304668 [CA 2] Center 35 (4~66) winsize 63
817 22:59:16.308106 [CA 3] Center 34 (4~65) winsize 62
818 22:59:16.311471 [CA 4] Center 34 (3~65) winsize 63
819 22:59:16.314944 [CA 5] Center 33 (3~64) winsize 62
820 22:59:16.315542
821 22:59:16.318278 [CmdBusTrainingLP45] Vref(ca) range 1: 34
822 22:59:16.318901
823 22:59:16.321699 [CATrainingPosCal] consider 2 rank data
824 22:59:16.325014 u2DelayCellTimex100 = 270/100 ps
825 22:59:16.328327 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
826 22:59:16.335019 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
827 22:59:16.338180 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
828 22:59:16.341314 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
829 22:59:16.344571 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
830 22:59:16.347678 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
831 22:59:16.347782
832 22:59:16.351004 CA PerBit enable=1, Macro0, CA PI delay=33
833 22:59:16.351105
834 22:59:16.354245 [CBTSetCACLKResult] CA Dly = 33
835 22:59:16.354345 CS Dly: 6 (0~38)
836 22:59:16.357729
837 22:59:16.361072 ----->DramcWriteLeveling(PI) begin...
838 22:59:16.361148 ==
839 22:59:16.364375 Dram Type= 6, Freq= 0, CH_0, rank 0
840 22:59:16.368383 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
841 22:59:16.368487 ==
842 22:59:16.371856 Write leveling (Byte 0): 32 => 32
843 22:59:16.371972 Write leveling (Byte 1): 28 => 28
844 22:59:16.375617 DramcWriteLeveling(PI) end<-----
845 22:59:16.375720
846 22:59:16.375811 ==
847 22:59:16.379712 Dram Type= 6, Freq= 0, CH_0, rank 0
848 22:59:16.382808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
849 22:59:16.385894 ==
850 22:59:16.386002 [Gating] SW mode calibration
851 22:59:16.392972 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 22:59:16.399919 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 22:59:16.403537 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
854 22:59:16.406638 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
855 22:59:16.413216 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
856 22:59:16.416576 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 22:59:16.419895 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 22:59:16.426978 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 22:59:16.429999 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 22:59:16.433215 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 22:59:16.439513 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 22:59:16.442986 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 22:59:16.446604 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 22:59:16.453110 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 22:59:16.456424 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 22:59:16.459408 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 22:59:16.466024 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 22:59:16.469417 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 22:59:16.472873 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 22:59:16.479441 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
871 22:59:16.482908 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
872 22:59:16.486104 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 22:59:16.492941 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 22:59:16.496138 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 22:59:16.499866 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 22:59:16.506334 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 22:59:16.509360 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 22:59:16.513029 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
879 22:59:16.519397 0 9 8 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
880 22:59:16.522752 0 9 12 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
881 22:59:16.525915 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 22:59:16.529347 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 22:59:16.535977 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 22:59:16.539586 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 22:59:16.542821 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
886 22:59:16.549497 0 10 4 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
887 22:59:16.552806 0 10 8 | B1->B0 | 3333 2525 | 0 0 | (0 1) (1 1)
888 22:59:16.555656 0 10 12 | B1->B0 | 2929 2323 | 0 0 | (1 1) (0 0)
889 22:59:16.562402 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 22:59:16.565602 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 22:59:16.569030 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 22:59:16.575747 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 22:59:16.579367 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
894 22:59:16.582418 0 11 4 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
895 22:59:16.589349 0 11 8 | B1->B0 | 2929 4545 | 0 0 | (0 0) (0 0)
896 22:59:16.592423 0 11 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
897 22:59:16.595399 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 22:59:16.602243 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 22:59:16.605415 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 22:59:16.609385 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 22:59:16.615539 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
902 22:59:16.618827 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
903 22:59:16.622086 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
904 22:59:16.628939 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 22:59:16.632385 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 22:59:16.635599 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 22:59:16.642316 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 22:59:16.645505 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 22:59:16.648891 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 22:59:16.655231 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 22:59:16.658961 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 22:59:16.661890 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 22:59:16.668586 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 22:59:16.671891 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 22:59:16.675361 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 22:59:16.681990 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 22:59:16.685106 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
918 22:59:16.688411 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
919 22:59:16.695013 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
920 22:59:16.698518 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
921 22:59:16.701668 Total UI for P1: 0, mck2ui 16
922 22:59:16.704831 best dqsien dly found for B0: ( 0, 14, 8)
923 22:59:16.708915 Total UI for P1: 0, mck2ui 16
924 22:59:16.712219 best dqsien dly found for B1: ( 0, 14, 8)
925 22:59:16.715611 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
926 22:59:16.718262 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
927 22:59:16.718660
928 22:59:16.721879 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
929 22:59:16.725139 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
930 22:59:16.728183 [Gating] SW calibration Done
931 22:59:16.728616 ==
932 22:59:16.731814 Dram Type= 6, Freq= 0, CH_0, rank 0
933 22:59:16.735369 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 22:59:16.735801 ==
935 22:59:16.738881 RX Vref Scan: 0
936 22:59:16.738964
937 22:59:16.739031 RX Vref 0 -> 0, step: 1
938 22:59:16.739092
939 22:59:16.742118 RX Delay -130 -> 252, step: 16
940 22:59:16.745433 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
941 22:59:16.752066 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
942 22:59:16.755532 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
943 22:59:16.758368 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
944 22:59:16.762333 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
945 22:59:16.765086 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
946 22:59:16.771799 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
947 22:59:16.775125 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
948 22:59:16.778679 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
949 22:59:16.781928 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
950 22:59:16.785279 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
951 22:59:16.791698 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
952 22:59:16.795052 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
953 22:59:16.798894 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
954 22:59:16.802016 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
955 22:59:16.808742 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
956 22:59:16.808885 ==
957 22:59:16.811931 Dram Type= 6, Freq= 0, CH_0, rank 0
958 22:59:16.815297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
959 22:59:16.815382 ==
960 22:59:16.815449 DQS Delay:
961 22:59:16.818350 DQS0 = 0, DQS1 = 0
962 22:59:16.818434 DQM Delay:
963 22:59:16.822306 DQM0 = 92, DQM1 = 75
964 22:59:16.822390 DQ Delay:
965 22:59:16.825433 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =93
966 22:59:16.828444 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =93
967 22:59:16.831617 DQ8 =69, DQ9 =53, DQ10 =69, DQ11 =69
968 22:59:16.835348 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
969 22:59:16.835432
970 22:59:16.835499
971 22:59:16.835559 ==
972 22:59:16.838595 Dram Type= 6, Freq= 0, CH_0, rank 0
973 22:59:16.842153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
974 22:59:16.842238 ==
975 22:59:16.842305
976 22:59:16.842367
977 22:59:16.845313 TX Vref Scan disable
978 22:59:16.848525 == TX Byte 0 ==
979 22:59:16.851946 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
980 22:59:16.855226 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
981 22:59:16.858795 == TX Byte 1 ==
982 22:59:16.862146 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
983 22:59:16.865415 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
984 22:59:16.865499 ==
985 22:59:16.868687 Dram Type= 6, Freq= 0, CH_0, rank 0
986 22:59:16.875713 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
987 22:59:16.876179 ==
988 22:59:16.887677 TX Vref=22, minBit 0, minWin=27, winSum=438
989 22:59:16.891260 TX Vref=24, minBit 1, minWin=27, winSum=443
990 22:59:16.894700 TX Vref=26, minBit 1, minWin=27, winSum=445
991 22:59:16.897701 TX Vref=28, minBit 0, minWin=28, winSum=451
992 22:59:16.900454 TX Vref=30, minBit 5, minWin=27, winSum=452
993 22:59:16.903989 TX Vref=32, minBit 1, minWin=27, winSum=447
994 22:59:16.910932 [TxChooseVref] Worse bit 0, Min win 28, Win sum 451, Final Vref 28
995 22:59:16.911640
996 22:59:16.913988 Final TX Range 1 Vref 28
997 22:59:16.914538
998 22:59:16.914887 ==
999 22:59:16.917179 Dram Type= 6, Freq= 0, CH_0, rank 0
1000 22:59:16.920848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1001 22:59:16.921315 ==
1002 22:59:16.924436
1003 22:59:16.924983
1004 22:59:16.925362 TX Vref Scan disable
1005 22:59:16.927658 == TX Byte 0 ==
1006 22:59:16.931043 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1007 22:59:16.937722 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1008 22:59:16.938173 == TX Byte 1 ==
1009 22:59:16.940618 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1010 22:59:16.944492 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1011 22:59:16.944928
1012 22:59:16.947618 [DATLAT]
1013 22:59:16.948084 Freq=800, CH0 RK0
1014 22:59:16.948477
1015 22:59:16.951012 DATLAT Default: 0xa
1016 22:59:16.951564 0, 0xFFFF, sum = 0
1017 22:59:16.954323 1, 0xFFFF, sum = 0
1018 22:59:16.954762 2, 0xFFFF, sum = 0
1019 22:59:16.957472 3, 0xFFFF, sum = 0
1020 22:59:16.957909 4, 0xFFFF, sum = 0
1021 22:59:16.960902 5, 0xFFFF, sum = 0
1022 22:59:16.961338 6, 0xFFFF, sum = 0
1023 22:59:16.964373 7, 0xFFFF, sum = 0
1024 22:59:16.967215 8, 0xFFFF, sum = 0
1025 22:59:16.967686 9, 0x0, sum = 1
1026 22:59:16.968242 10, 0x0, sum = 2
1027 22:59:16.970905 11, 0x0, sum = 3
1028 22:59:16.971509 12, 0x0, sum = 4
1029 22:59:16.974171 best_step = 10
1030 22:59:16.974772
1031 22:59:16.975293 ==
1032 22:59:16.977013 Dram Type= 6, Freq= 0, CH_0, rank 0
1033 22:59:16.980474 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1034 22:59:16.980926 ==
1035 22:59:16.984209 RX Vref Scan: 1
1036 22:59:16.984636
1037 22:59:16.984998 Set Vref Range= 32 -> 127
1038 22:59:16.985318
1039 22:59:16.987170 RX Vref 32 -> 127, step: 1
1040 22:59:16.987599
1041 22:59:16.991316 RX Delay -111 -> 252, step: 8
1042 22:59:16.991744
1043 22:59:16.994338 Set Vref, RX VrefLevel [Byte0]: 32
1044 22:59:16.997216 [Byte1]: 32
1045 22:59:16.997643
1046 22:59:17.000729 Set Vref, RX VrefLevel [Byte0]: 33
1047 22:59:17.003950 [Byte1]: 33
1048 22:59:17.007690
1049 22:59:17.008151 Set Vref, RX VrefLevel [Byte0]: 34
1050 22:59:17.011266 [Byte1]: 34
1051 22:59:17.015637
1052 22:59:17.016096 Set Vref, RX VrefLevel [Byte0]: 35
1053 22:59:17.018908 [Byte1]: 35
1054 22:59:17.023369
1055 22:59:17.023795 Set Vref, RX VrefLevel [Byte0]: 36
1056 22:59:17.026312 [Byte1]: 36
1057 22:59:17.030561
1058 22:59:17.030950 Set Vref, RX VrefLevel [Byte0]: 37
1059 22:59:17.033863 [Byte1]: 37
1060 22:59:17.038470
1061 22:59:17.038663 Set Vref, RX VrefLevel [Byte0]: 38
1062 22:59:17.041444 [Byte1]: 38
1063 22:59:17.046045
1064 22:59:17.046189 Set Vref, RX VrefLevel [Byte0]: 39
1065 22:59:17.049300 [Byte1]: 39
1066 22:59:17.053644
1067 22:59:17.053800 Set Vref, RX VrefLevel [Byte0]: 40
1068 22:59:17.057277 [Byte1]: 40
1069 22:59:17.061382
1070 22:59:17.061535 Set Vref, RX VrefLevel [Byte0]: 41
1071 22:59:17.064666 [Byte1]: 41
1072 22:59:17.068774
1073 22:59:17.068914 Set Vref, RX VrefLevel [Byte0]: 42
1074 22:59:17.071999 [Byte1]: 42
1075 22:59:17.076259
1076 22:59:17.076339 Set Vref, RX VrefLevel [Byte0]: 43
1077 22:59:17.079666 [Byte1]: 43
1078 22:59:17.084235
1079 22:59:17.084326 Set Vref, RX VrefLevel [Byte0]: 44
1080 22:59:17.087012 [Byte1]: 44
1081 22:59:17.091517
1082 22:59:17.091592 Set Vref, RX VrefLevel [Byte0]: 45
1083 22:59:17.094890 [Byte1]: 45
1084 22:59:17.099368
1085 22:59:17.099449 Set Vref, RX VrefLevel [Byte0]: 46
1086 22:59:17.102639 [Byte1]: 46
1087 22:59:17.107060
1088 22:59:17.107133 Set Vref, RX VrefLevel [Byte0]: 47
1089 22:59:17.109976 [Byte1]: 47
1090 22:59:17.114495
1091 22:59:17.114574 Set Vref, RX VrefLevel [Byte0]: 48
1092 22:59:17.117742 [Byte1]: 48
1093 22:59:17.122276
1094 22:59:17.122357 Set Vref, RX VrefLevel [Byte0]: 49
1095 22:59:17.125344 [Byte1]: 49
1096 22:59:17.129863
1097 22:59:17.129936 Set Vref, RX VrefLevel [Byte0]: 50
1098 22:59:17.133207 [Byte1]: 50
1099 22:59:17.137580
1100 22:59:17.137660 Set Vref, RX VrefLevel [Byte0]: 51
1101 22:59:17.140607 [Byte1]: 51
1102 22:59:17.144774
1103 22:59:17.144856 Set Vref, RX VrefLevel [Byte0]: 52
1104 22:59:17.148542 [Byte1]: 52
1105 22:59:17.152845
1106 22:59:17.152932 Set Vref, RX VrefLevel [Byte0]: 53
1107 22:59:17.155994 [Byte1]: 53
1108 22:59:17.160144
1109 22:59:17.160227 Set Vref, RX VrefLevel [Byte0]: 54
1110 22:59:17.163903 [Byte1]: 54
1111 22:59:17.167925
1112 22:59:17.168022 Set Vref, RX VrefLevel [Byte0]: 55
1113 22:59:17.171409 [Byte1]: 55
1114 22:59:17.175681
1115 22:59:17.175782 Set Vref, RX VrefLevel [Byte0]: 56
1116 22:59:17.178926 [Byte1]: 56
1117 22:59:17.183327
1118 22:59:17.183433 Set Vref, RX VrefLevel [Byte0]: 57
1119 22:59:17.186932 [Byte1]: 57
1120 22:59:17.190654
1121 22:59:17.190734 Set Vref, RX VrefLevel [Byte0]: 58
1122 22:59:17.193955 [Byte1]: 58
1123 22:59:17.198615
1124 22:59:17.198688 Set Vref, RX VrefLevel [Byte0]: 59
1125 22:59:17.201960 [Byte1]: 59
1126 22:59:17.206387
1127 22:59:17.206464 Set Vref, RX VrefLevel [Byte0]: 60
1128 22:59:17.209388 [Byte1]: 60
1129 22:59:17.213833
1130 22:59:17.213939 Set Vref, RX VrefLevel [Byte0]: 61
1131 22:59:17.216936 [Byte1]: 61
1132 22:59:17.221498
1133 22:59:17.221573 Set Vref, RX VrefLevel [Byte0]: 62
1134 22:59:17.224894 [Byte1]: 62
1135 22:59:17.229211
1136 22:59:17.229288 Set Vref, RX VrefLevel [Byte0]: 63
1137 22:59:17.232519 [Byte1]: 63
1138 22:59:17.236690
1139 22:59:17.236794 Set Vref, RX VrefLevel [Byte0]: 64
1140 22:59:17.239854 [Byte1]: 64
1141 22:59:17.244274
1142 22:59:17.244348 Set Vref, RX VrefLevel [Byte0]: 65
1143 22:59:17.247778 [Byte1]: 65
1144 22:59:17.251920
1145 22:59:17.252045 Set Vref, RX VrefLevel [Byte0]: 66
1146 22:59:17.255290 [Byte1]: 66
1147 22:59:17.259694
1148 22:59:17.259795 Set Vref, RX VrefLevel [Byte0]: 67
1149 22:59:17.263151 [Byte1]: 67
1150 22:59:17.267195
1151 22:59:17.267301 Set Vref, RX VrefLevel [Byte0]: 68
1152 22:59:17.270816 [Byte1]: 68
1153 22:59:17.274949
1154 22:59:17.275056 Set Vref, RX VrefLevel [Byte0]: 69
1155 22:59:17.278503 [Byte1]: 69
1156 22:59:17.282643
1157 22:59:17.282729 Set Vref, RX VrefLevel [Byte0]: 70
1158 22:59:17.285692 [Byte1]: 70
1159 22:59:17.290130
1160 22:59:17.290213 Set Vref, RX VrefLevel [Byte0]: 71
1161 22:59:17.293545 [Byte1]: 71
1162 22:59:17.298079
1163 22:59:17.298157 Set Vref, RX VrefLevel [Byte0]: 72
1164 22:59:17.301347 [Byte1]: 72
1165 22:59:17.305354
1166 22:59:17.305432 Set Vref, RX VrefLevel [Byte0]: 73
1167 22:59:17.308695 [Byte1]: 73
1168 22:59:17.313387
1169 22:59:17.313470 Set Vref, RX VrefLevel [Byte0]: 74
1170 22:59:17.316431 [Byte1]: 74
1171 22:59:17.320662
1172 22:59:17.320744 Final RX Vref Byte 0 = 56 to rank0
1173 22:59:17.324025 Final RX Vref Byte 1 = 59 to rank0
1174 22:59:17.327294 Final RX Vref Byte 0 = 56 to rank1
1175 22:59:17.331107 Final RX Vref Byte 1 = 59 to rank1==
1176 22:59:17.334356 Dram Type= 6, Freq= 0, CH_0, rank 0
1177 22:59:17.341187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1178 22:59:17.341276 ==
1179 22:59:17.341360 DQS Delay:
1180 22:59:17.341443 DQS0 = 0, DQS1 = 0
1181 22:59:17.344234 DQM Delay:
1182 22:59:17.344315 DQM0 = 87, DQM1 = 77
1183 22:59:17.347776 DQ Delay:
1184 22:59:17.350479 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1185 22:59:17.353832 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1186 22:59:17.357621 DQ8 =68, DQ9 =60, DQ10 =76, DQ11 =76
1187 22:59:17.360490 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
1188 22:59:17.360591
1189 22:59:17.360692
1190 22:59:17.367228 [DQSOSCAuto] RK0, (LSB)MR18= 0x322c, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 397 ps
1191 22:59:17.370849 CH0 RK0: MR19=606, MR18=322C
1192 22:59:17.377060 CH0_RK0: MR19=0x606, MR18=0x322C, DQSOSC=397, MR23=63, INC=93, DEC=62
1193 22:59:17.377142
1194 22:59:17.380772 ----->DramcWriteLeveling(PI) begin...
1195 22:59:17.380877 ==
1196 22:59:17.383945 Dram Type= 6, Freq= 0, CH_0, rank 1
1197 22:59:17.386911 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1198 22:59:17.387014 ==
1199 22:59:17.390472 Write leveling (Byte 0): 29 => 29
1200 22:59:17.393601 Write leveling (Byte 1): 28 => 28
1201 22:59:17.397342 DramcWriteLeveling(PI) end<-----
1202 22:59:17.397429
1203 22:59:17.397511 ==
1204 22:59:17.400730 Dram Type= 6, Freq= 0, CH_0, rank 1
1205 22:59:17.404044 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1206 22:59:17.404125 ==
1207 22:59:17.407388 [Gating] SW mode calibration
1208 22:59:17.413435 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1209 22:59:17.420758 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1210 22:59:17.423940 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1211 22:59:17.467709 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1212 22:59:17.468058 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1213 22:59:17.468822 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1214 22:59:17.468944 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1215 22:59:17.469233 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1216 22:59:17.469353 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1217 22:59:17.469454 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1218 22:59:17.469564 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1219 22:59:17.469661 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 22:59:17.469754 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 22:59:17.512496 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 22:59:17.513429 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 22:59:17.513881 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 22:59:17.514279 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 22:59:17.514714 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 22:59:17.515325 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 22:59:17.515798 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1228 22:59:17.516258 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1229 22:59:17.516683 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 22:59:17.517158 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 22:59:17.556415 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 22:59:17.557310 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 22:59:17.557713 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 22:59:17.558251 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 22:59:17.558722 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 22:59:17.559176 0 9 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
1237 22:59:17.559731 0 9 12 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
1238 22:59:17.560325 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1239 22:59:17.560844 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1240 22:59:17.561348 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1241 22:59:17.571811 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1242 22:59:17.572772 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1243 22:59:17.574984 0 10 4 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 0)
1244 22:59:17.575469 0 10 8 | B1->B0 | 3232 2323 | 0 0 | (0 1) (0 0)
1245 22:59:17.579018 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1246 22:59:17.582276 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1247 22:59:17.588711 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1248 22:59:17.592099 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1249 22:59:17.594993 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1250 22:59:17.601629 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1251 22:59:17.604942 0 11 4 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (1 1)
1252 22:59:17.608721 0 11 8 | B1->B0 | 3434 4646 | 0 0 | (0 0) (0 0)
1253 22:59:17.611782 0 11 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
1254 22:59:17.619080 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1255 22:59:17.623268 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1256 22:59:17.626973 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1257 22:59:17.630471 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1258 22:59:17.636928 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1259 22:59:17.640661 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1260 22:59:17.644131 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1261 22:59:17.647320 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1262 22:59:17.654178 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1263 22:59:17.657507 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1264 22:59:17.660996 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1265 22:59:17.667604 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1266 22:59:17.670360 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1267 22:59:17.674370 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1268 22:59:17.680242 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1269 22:59:17.683942 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1270 22:59:17.687364 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1271 22:59:17.693809 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 22:59:17.697292 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 22:59:17.700635 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 22:59:17.706890 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 22:59:17.710324 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1276 22:59:17.713569 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1277 22:59:17.717041 Total UI for P1: 0, mck2ui 16
1278 22:59:17.720273 best dqsien dly found for B0: ( 0, 14, 4)
1279 22:59:17.726929 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1280 22:59:17.727381 Total UI for P1: 0, mck2ui 16
1281 22:59:17.730463 best dqsien dly found for B1: ( 0, 14, 8)
1282 22:59:17.737154 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1283 22:59:17.739912 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1284 22:59:17.740378
1285 22:59:17.743276 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1286 22:59:17.746663 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1287 22:59:17.749940 [Gating] SW calibration Done
1288 22:59:17.750364 ==
1289 22:59:17.753044 Dram Type= 6, Freq= 0, CH_0, rank 1
1290 22:59:17.756509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1291 22:59:17.756940 ==
1292 22:59:17.759858 RX Vref Scan: 0
1293 22:59:17.760325
1294 22:59:17.760660 RX Vref 0 -> 0, step: 1
1295 22:59:17.760971
1296 22:59:17.762984 RX Delay -130 -> 252, step: 16
1297 22:59:17.766475 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1298 22:59:17.773369 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1299 22:59:17.776494 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1300 22:59:17.779697 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1301 22:59:17.783172 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1302 22:59:17.786236 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
1303 22:59:17.793260 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1304 22:59:17.796482 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1305 22:59:17.799863 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1306 22:59:17.803240 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1307 22:59:17.806816 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1308 22:59:17.813021 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1309 22:59:17.816493 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1310 22:59:17.819705 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1311 22:59:17.823228 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1312 22:59:17.826342 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1313 22:59:17.829691 ==
1314 22:59:17.832957 Dram Type= 6, Freq= 0, CH_0, rank 1
1315 22:59:17.836605 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1316 22:59:17.837042 ==
1317 22:59:17.837382 DQS Delay:
1318 22:59:17.839636 DQS0 = 0, DQS1 = 0
1319 22:59:17.840188 DQM Delay:
1320 22:59:17.842641 DQM0 = 86, DQM1 = 77
1321 22:59:17.843149 DQ Delay:
1322 22:59:17.846171 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =85
1323 22:59:17.849561 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
1324 22:59:17.852905 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =69
1325 22:59:17.856232 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1326 22:59:17.856713
1327 22:59:17.857222
1328 22:59:17.857715 ==
1329 22:59:17.859480 Dram Type= 6, Freq= 0, CH_0, rank 1
1330 22:59:17.862529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1331 22:59:17.863143 ==
1332 22:59:17.863558
1333 22:59:17.863876
1334 22:59:17.866164 TX Vref Scan disable
1335 22:59:17.869671 == TX Byte 0 ==
1336 22:59:17.872927 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1337 22:59:17.875699 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1338 22:59:17.879052 == TX Byte 1 ==
1339 22:59:17.882902 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1340 22:59:17.885512 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1341 22:59:17.886063 ==
1342 22:59:17.889072 Dram Type= 6, Freq= 0, CH_0, rank 1
1343 22:59:17.895478 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1344 22:59:17.895950 ==
1345 22:59:17.907209 TX Vref=22, minBit 1, minWin=26, winSum=437
1346 22:59:17.910614 TX Vref=24, minBit 2, minWin=27, winSum=443
1347 22:59:17.914003 TX Vref=26, minBit 1, minWin=27, winSum=450
1348 22:59:17.917041 TX Vref=28, minBit 7, minWin=27, winSum=452
1349 22:59:17.920161 TX Vref=30, minBit 2, minWin=27, winSum=449
1350 22:59:17.926872 TX Vref=32, minBit 6, minWin=27, winSum=449
1351 22:59:17.930406 [TxChooseVref] Worse bit 7, Min win 27, Win sum 452, Final Vref 28
1352 22:59:17.930981
1353 22:59:17.933510 Final TX Range 1 Vref 28
1354 22:59:17.933939
1355 22:59:17.934279 ==
1356 22:59:17.937013 Dram Type= 6, Freq= 0, CH_0, rank 1
1357 22:59:17.939929 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1358 22:59:17.940286 ==
1359 22:59:17.943282
1360 22:59:17.943576
1361 22:59:17.943808 TX Vref Scan disable
1362 22:59:17.946598 == TX Byte 0 ==
1363 22:59:17.950036 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1364 22:59:17.953380 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1365 22:59:17.956912 == TX Byte 1 ==
1366 22:59:17.960204 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1367 22:59:17.967349 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1368 22:59:17.967653
1369 22:59:17.967885 [DATLAT]
1370 22:59:17.968143 Freq=800, CH0 RK1
1371 22:59:17.968375
1372 22:59:17.970413 DATLAT Default: 0xa
1373 22:59:17.970721 0, 0xFFFF, sum = 0
1374 22:59:17.973535 1, 0xFFFF, sum = 0
1375 22:59:17.973848 2, 0xFFFF, sum = 0
1376 22:59:17.976964 3, 0xFFFF, sum = 0
1377 22:59:17.977268 4, 0xFFFF, sum = 0
1378 22:59:17.980411 5, 0xFFFF, sum = 0
1379 22:59:17.983593 6, 0xFFFF, sum = 0
1380 22:59:17.983891 7, 0xFFFF, sum = 0
1381 22:59:17.986937 8, 0xFFFF, sum = 0
1382 22:59:17.987348 9, 0x0, sum = 1
1383 22:59:17.987607 10, 0x0, sum = 2
1384 22:59:17.990324 11, 0x0, sum = 3
1385 22:59:17.990621 12, 0x0, sum = 4
1386 22:59:17.993689 best_step = 10
1387 22:59:17.994115
1388 22:59:17.994379 ==
1389 22:59:17.996682 Dram Type= 6, Freq= 0, CH_0, rank 1
1390 22:59:18.000697 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1391 22:59:18.001009 ==
1392 22:59:18.003506 RX Vref Scan: 0
1393 22:59:18.003797
1394 22:59:18.004028 RX Vref 0 -> 0, step: 1
1395 22:59:18.004312
1396 22:59:18.007224 RX Delay -95 -> 252, step: 8
1397 22:59:18.013394 iDelay=209, Bit 0, Center 84 (-23 ~ 192) 216
1398 22:59:18.016727 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1399 22:59:18.020108 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1400 22:59:18.023993 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1401 22:59:18.026983 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1402 22:59:18.033663 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1403 22:59:18.036667 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1404 22:59:18.039839 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1405 22:59:18.043915 iDelay=209, Bit 8, Center 64 (-47 ~ 176) 224
1406 22:59:18.046551 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1407 22:59:18.053599 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1408 22:59:18.056996 iDelay=209, Bit 11, Center 72 (-39 ~ 184) 224
1409 22:59:18.060315 iDelay=209, Bit 12, Center 88 (-23 ~ 200) 224
1410 22:59:18.063475 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1411 22:59:18.070153 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1412 22:59:18.073402 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1413 22:59:18.073817 ==
1414 22:59:18.076681 Dram Type= 6, Freq= 0, CH_0, rank 1
1415 22:59:18.080096 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1416 22:59:18.080564 ==
1417 22:59:18.080904 DQS Delay:
1418 22:59:18.083228 DQS0 = 0, DQS1 = 0
1419 22:59:18.083595 DQM Delay:
1420 22:59:18.086613 DQM0 = 86, DQM1 = 77
1421 22:59:18.087035 DQ Delay:
1422 22:59:18.089870 DQ0 =84, DQ1 =92, DQ2 =80, DQ3 =80
1423 22:59:18.093291 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1424 22:59:18.096540 DQ8 =64, DQ9 =64, DQ10 =80, DQ11 =72
1425 22:59:18.099853 DQ12 =88, DQ13 =80, DQ14 =88, DQ15 =84
1426 22:59:18.100350
1427 22:59:18.100699
1428 22:59:18.110145 [DQSOSCAuto] RK1, (LSB)MR18= 0x2b28, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 398 ps
1429 22:59:18.110613 CH0 RK1: MR19=606, MR18=2B28
1430 22:59:18.116511 CH0_RK1: MR19=0x606, MR18=0x2B28, DQSOSC=398, MR23=63, INC=93, DEC=62
1431 22:59:18.119972 [RxdqsGatingPostProcess] freq 800
1432 22:59:18.126734 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1433 22:59:18.129625 Pre-setting of DQS Precalculation
1434 22:59:18.132874 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1435 22:59:18.133300 ==
1436 22:59:18.136475 Dram Type= 6, Freq= 0, CH_1, rank 0
1437 22:59:18.143386 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1438 22:59:18.144096 ==
1439 22:59:18.146597 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1440 22:59:18.153171 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1441 22:59:18.162222 [CA 0] Center 37 (6~68) winsize 63
1442 22:59:18.165642 [CA 1] Center 37 (6~68) winsize 63
1443 22:59:18.168958 [CA 2] Center 35 (5~65) winsize 61
1444 22:59:18.172094 [CA 3] Center 34 (4~65) winsize 62
1445 22:59:18.175674 [CA 4] Center 34 (4~65) winsize 62
1446 22:59:18.178784 [CA 5] Center 34 (3~65) winsize 63
1447 22:59:18.179441
1448 22:59:18.181970 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1449 22:59:18.182580
1450 22:59:18.185293 [CATrainingPosCal] consider 1 rank data
1451 22:59:18.188259 u2DelayCellTimex100 = 270/100 ps
1452 22:59:18.191643 CA0 delay=37 (6~68),Diff = 3 PI (21 cell)
1453 22:59:18.198532 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
1454 22:59:18.201464 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1455 22:59:18.204907 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1456 22:59:18.208329 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1457 22:59:18.211780 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1458 22:59:18.212358
1459 22:59:18.214958 CA PerBit enable=1, Macro0, CA PI delay=34
1460 22:59:18.215392
1461 22:59:18.218645 [CBTSetCACLKResult] CA Dly = 34
1462 22:59:18.219228 CS Dly: 4 (0~35)
1463 22:59:18.221587 ==
1464 22:59:18.224921 Dram Type= 6, Freq= 0, CH_1, rank 1
1465 22:59:18.228273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1466 22:59:18.228823 ==
1467 22:59:18.231595 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1468 22:59:18.238073 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1469 22:59:18.248331 [CA 0] Center 36 (6~67) winsize 62
1470 22:59:18.251169 [CA 1] Center 36 (6~67) winsize 62
1471 22:59:18.254535 [CA 2] Center 34 (4~65) winsize 62
1472 22:59:18.257854 [CA 3] Center 33 (3~64) winsize 62
1473 22:59:18.261231 [CA 4] Center 34 (3~65) winsize 63
1474 22:59:18.265002 [CA 5] Center 33 (3~64) winsize 62
1475 22:59:18.265669
1476 22:59:18.268249 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1477 22:59:18.268875
1478 22:59:18.271652 [CATrainingPosCal] consider 2 rank data
1479 22:59:18.274773 u2DelayCellTimex100 = 270/100 ps
1480 22:59:18.278680 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1481 22:59:18.281953 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1482 22:59:18.285829 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1483 22:59:18.289237 CA3 delay=34 (4~64),Diff = 1 PI (7 cell)
1484 22:59:18.293110 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1485 22:59:18.297234 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1486 22:59:18.297812
1487 22:59:18.300149 CA PerBit enable=1, Macro0, CA PI delay=33
1488 22:59:18.300832
1489 22:59:18.303888 [CBTSetCACLKResult] CA Dly = 33
1490 22:59:18.308085 CS Dly: 5 (0~37)
1491 22:59:18.308750
1492 22:59:18.311799 ----->DramcWriteLeveling(PI) begin...
1493 22:59:18.312542 ==
1494 22:59:18.314555 Dram Type= 6, Freq= 0, CH_1, rank 0
1495 22:59:18.317859 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1496 22:59:18.318655 ==
1497 22:59:18.321121 Write leveling (Byte 0): 26 => 26
1498 22:59:18.324413 Write leveling (Byte 1): 25 => 25
1499 22:59:18.327631 DramcWriteLeveling(PI) end<-----
1500 22:59:18.328209
1501 22:59:18.328559 ==
1502 22:59:18.330961 Dram Type= 6, Freq= 0, CH_1, rank 0
1503 22:59:18.334380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1504 22:59:18.334823 ==
1505 22:59:18.337816 [Gating] SW mode calibration
1506 22:59:18.344607 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1507 22:59:18.351270 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1508 22:59:18.354275 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1509 22:59:18.357930 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1510 22:59:18.364420 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1511 22:59:18.367633 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1512 22:59:18.371005 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1513 22:59:18.377295 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1514 22:59:18.380664 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1515 22:59:18.384451 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1516 22:59:18.390956 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 22:59:18.394075 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 22:59:18.396970 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 22:59:18.400737 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 22:59:18.406823 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 22:59:18.410097 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 22:59:18.414085 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 22:59:18.420002 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 22:59:18.423733 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 22:59:18.426832 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1526 22:59:18.433684 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 22:59:18.437193 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 22:59:18.439909 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 22:59:18.446891 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 22:59:18.449965 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 22:59:18.453731 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 22:59:18.459907 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 22:59:18.463417 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 22:59:18.466405 0 9 8 | B1->B0 | 2c2c 3030 | 1 1 | (1 1) (1 1)
1535 22:59:18.473344 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1536 22:59:18.476787 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1537 22:59:18.480172 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1538 22:59:18.486729 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1539 22:59:18.490080 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1540 22:59:18.493417 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1541 22:59:18.499824 0 10 4 | B1->B0 | 3434 3131 | 0 0 | (0 0) (0 1)
1542 22:59:18.503140 0 10 8 | B1->B0 | 2727 2424 | 0 0 | (0 0) (0 0)
1543 22:59:18.506644 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1544 22:59:18.512676 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1545 22:59:18.516237 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1546 22:59:18.520213 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1547 22:59:18.526602 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1548 22:59:18.529837 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1549 22:59:18.533390 0 11 4 | B1->B0 | 2525 2f2f | 0 1 | (0 0) (0 0)
1550 22:59:18.539811 0 11 8 | B1->B0 | 3b3b 4343 | 0 0 | (0 0) (0 0)
1551 22:59:18.543194 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1552 22:59:18.546728 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1553 22:59:18.553202 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1554 22:59:18.555956 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1555 22:59:18.559419 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1556 22:59:18.566056 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1557 22:59:18.569672 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1558 22:59:18.572807 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1559 22:59:18.575966 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1560 22:59:18.582659 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1561 22:59:18.585906 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1562 22:59:18.589339 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1563 22:59:18.595988 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1564 22:59:18.599436 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1565 22:59:18.602496 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1566 22:59:18.609132 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1567 22:59:18.612409 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 22:59:18.615728 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 22:59:18.622499 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 22:59:18.625759 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 22:59:18.632380 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 22:59:18.635213 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 22:59:18.638544 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 22:59:18.641964 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1575 22:59:18.645372 Total UI for P1: 0, mck2ui 16
1576 22:59:18.648760 best dqsien dly found for B0: ( 0, 14, 6)
1577 22:59:18.652154 Total UI for P1: 0, mck2ui 16
1578 22:59:18.655450 best dqsien dly found for B1: ( 0, 14, 6)
1579 22:59:18.658698 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1580 22:59:18.665138 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1581 22:59:18.665225
1582 22:59:18.668435 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1583 22:59:18.671732 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1584 22:59:18.675191 [Gating] SW calibration Done
1585 22:59:18.675276 ==
1586 22:59:18.678483 Dram Type= 6, Freq= 0, CH_1, rank 0
1587 22:59:18.681790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1588 22:59:18.681876 ==
1589 22:59:18.681961 RX Vref Scan: 0
1590 22:59:18.684843
1591 22:59:18.684955 RX Vref 0 -> 0, step: 1
1592 22:59:18.685029
1593 22:59:18.688159 RX Delay -130 -> 252, step: 16
1594 22:59:18.691901 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1595 22:59:18.695183 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1596 22:59:18.701803 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1597 22:59:18.704949 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1598 22:59:18.708406 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1599 22:59:18.711570 iDelay=222, Bit 5, Center 93 (-18 ~ 205) 224
1600 22:59:18.714910 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1601 22:59:18.721549 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1602 22:59:18.724843 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1603 22:59:18.728343 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1604 22:59:18.731449 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1605 22:59:18.734843 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1606 22:59:18.741454 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1607 22:59:18.744856 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1608 22:59:18.748390 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1609 22:59:18.751481 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1610 22:59:18.751563 ==
1611 22:59:18.754867 Dram Type= 6, Freq= 0, CH_1, rank 0
1612 22:59:18.761570 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1613 22:59:18.761653 ==
1614 22:59:18.761719 DQS Delay:
1615 22:59:18.764939 DQS0 = 0, DQS1 = 0
1616 22:59:18.765021 DQM Delay:
1617 22:59:18.765086 DQM0 = 85, DQM1 = 80
1618 22:59:18.768134 DQ Delay:
1619 22:59:18.771395 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =85
1620 22:59:18.774656 DQ4 =85, DQ5 =93, DQ6 =101, DQ7 =85
1621 22:59:18.777866 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1622 22:59:18.781242 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1623 22:59:18.781326
1624 22:59:18.781391
1625 22:59:18.781451 ==
1626 22:59:18.784765 Dram Type= 6, Freq= 0, CH_1, rank 0
1627 22:59:18.787755 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1628 22:59:18.787840 ==
1629 22:59:18.787906
1630 22:59:18.787966
1631 22:59:18.791012 TX Vref Scan disable
1632 22:59:18.794833 == TX Byte 0 ==
1633 22:59:18.798059 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1634 22:59:18.801283 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1635 22:59:18.804873 == TX Byte 1 ==
1636 22:59:18.808220 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1637 22:59:18.811322 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1638 22:59:18.811405 ==
1639 22:59:18.814239 Dram Type= 6, Freq= 0, CH_1, rank 0
1640 22:59:18.818122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1641 22:59:18.820773 ==
1642 22:59:18.832226 TX Vref=22, minBit 2, minWin=26, winSum=439
1643 22:59:18.835425 TX Vref=24, minBit 4, minWin=27, winSum=447
1644 22:59:18.838853 TX Vref=26, minBit 4, minWin=27, winSum=451
1645 22:59:18.842593 TX Vref=28, minBit 0, minWin=27, winSum=454
1646 22:59:18.845338 TX Vref=30, minBit 5, minWin=27, winSum=453
1647 22:59:18.849218 TX Vref=32, minBit 1, minWin=27, winSum=452
1648 22:59:18.855829 [TxChooseVref] Worse bit 0, Min win 27, Win sum 454, Final Vref 28
1649 22:59:18.855930
1650 22:59:18.859849 Final TX Range 1 Vref 28
1651 22:59:18.859953
1652 22:59:18.860068 ==
1653 22:59:18.862832 Dram Type= 6, Freq= 0, CH_1, rank 0
1654 22:59:18.866013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1655 22:59:18.866092 ==
1656 22:59:18.866168
1657 22:59:18.866257
1658 22:59:18.869227 TX Vref Scan disable
1659 22:59:18.873119 == TX Byte 0 ==
1660 22:59:18.876635 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1661 22:59:18.879738 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1662 22:59:18.882949 == TX Byte 1 ==
1663 22:59:18.886156 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1664 22:59:18.889415 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1665 22:59:18.889494
1666 22:59:18.892839 [DATLAT]
1667 22:59:18.892916 Freq=800, CH1 RK0
1668 22:59:18.892979
1669 22:59:18.896049 DATLAT Default: 0xa
1670 22:59:18.896123 0, 0xFFFF, sum = 0
1671 22:59:18.899598 1, 0xFFFF, sum = 0
1672 22:59:18.899695 2, 0xFFFF, sum = 0
1673 22:59:18.902846 3, 0xFFFF, sum = 0
1674 22:59:18.902921 4, 0xFFFF, sum = 0
1675 22:59:18.905927 5, 0xFFFF, sum = 0
1676 22:59:18.906000 6, 0xFFFF, sum = 0
1677 22:59:18.909248 7, 0xFFFF, sum = 0
1678 22:59:18.909318 8, 0xFFFF, sum = 0
1679 22:59:18.912608 9, 0x0, sum = 1
1680 22:59:18.912678 10, 0x0, sum = 2
1681 22:59:18.916222 11, 0x0, sum = 3
1682 22:59:18.916319 12, 0x0, sum = 4
1683 22:59:18.919339 best_step = 10
1684 22:59:18.919413
1685 22:59:18.919496 ==
1686 22:59:18.922681 Dram Type= 6, Freq= 0, CH_1, rank 0
1687 22:59:18.925932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1688 22:59:18.926001 ==
1689 22:59:18.929544 RX Vref Scan: 1
1690 22:59:18.929610
1691 22:59:18.929673 Set Vref Range= 32 -> 127
1692 22:59:18.929732
1693 22:59:18.932756 RX Vref 32 -> 127, step: 1
1694 22:59:18.932846
1695 22:59:18.935959 RX Delay -95 -> 252, step: 8
1696 22:59:18.936087
1697 22:59:18.939217 Set Vref, RX VrefLevel [Byte0]: 32
1698 22:59:18.942576 [Byte1]: 32
1699 22:59:18.942669
1700 22:59:18.945807 Set Vref, RX VrefLevel [Byte0]: 33
1701 22:59:18.949136 [Byte1]: 33
1702 22:59:18.952705
1703 22:59:18.952777 Set Vref, RX VrefLevel [Byte0]: 34
1704 22:59:18.955878 [Byte1]: 34
1705 22:59:18.960470
1706 22:59:18.960570 Set Vref, RX VrefLevel [Byte0]: 35
1707 22:59:18.963414 [Byte1]: 35
1708 22:59:18.967684
1709 22:59:18.967785 Set Vref, RX VrefLevel [Byte0]: 36
1710 22:59:18.970909 [Byte1]: 36
1711 22:59:18.975088
1712 22:59:18.975192 Set Vref, RX VrefLevel [Byte0]: 37
1713 22:59:18.978409 [Byte1]: 37
1714 22:59:18.982968
1715 22:59:18.983056 Set Vref, RX VrefLevel [Byte0]: 38
1716 22:59:18.986140 [Byte1]: 38
1717 22:59:18.990232
1718 22:59:18.990344 Set Vref, RX VrefLevel [Byte0]: 39
1719 22:59:18.994042 [Byte1]: 39
1720 22:59:18.997998
1721 22:59:18.998093 Set Vref, RX VrefLevel [Byte0]: 40
1722 22:59:19.001478 [Byte1]: 40
1723 22:59:19.005812
1724 22:59:19.005903 Set Vref, RX VrefLevel [Byte0]: 41
1725 22:59:19.008777 [Byte1]: 41
1726 22:59:19.013455
1727 22:59:19.013532 Set Vref, RX VrefLevel [Byte0]: 42
1728 22:59:19.016545 [Byte1]: 42
1729 22:59:19.021112
1730 22:59:19.021217 Set Vref, RX VrefLevel [Byte0]: 43
1731 22:59:19.024507 [Byte1]: 43
1732 22:59:19.028421
1733 22:59:19.028498 Set Vref, RX VrefLevel [Byte0]: 44
1734 22:59:19.031764 [Byte1]: 44
1735 22:59:19.036314
1736 22:59:19.036390 Set Vref, RX VrefLevel [Byte0]: 45
1737 22:59:19.039728 [Byte1]: 45
1738 22:59:19.043523
1739 22:59:19.043603 Set Vref, RX VrefLevel [Byte0]: 46
1740 22:59:19.046841 [Byte1]: 46
1741 22:59:19.051160
1742 22:59:19.051261 Set Vref, RX VrefLevel [Byte0]: 47
1743 22:59:19.054735 [Byte1]: 47
1744 22:59:19.059138
1745 22:59:19.059238 Set Vref, RX VrefLevel [Byte0]: 48
1746 22:59:19.062064 [Byte1]: 48
1747 22:59:19.066337
1748 22:59:19.066439 Set Vref, RX VrefLevel [Byte0]: 49
1749 22:59:19.069832 [Byte1]: 49
1750 22:59:19.074323
1751 22:59:19.074426 Set Vref, RX VrefLevel [Byte0]: 50
1752 22:59:19.077579 [Byte1]: 50
1753 22:59:19.081968
1754 22:59:19.082090 Set Vref, RX VrefLevel [Byte0]: 51
1755 22:59:19.085231 [Byte1]: 51
1756 22:59:19.089146
1757 22:59:19.089231 Set Vref, RX VrefLevel [Byte0]: 52
1758 22:59:19.092431 [Byte1]: 52
1759 22:59:19.096975
1760 22:59:19.097059 Set Vref, RX VrefLevel [Byte0]: 53
1761 22:59:19.100152 [Byte1]: 53
1762 22:59:19.104473
1763 22:59:19.104555 Set Vref, RX VrefLevel [Byte0]: 54
1764 22:59:19.107589 [Byte1]: 54
1765 22:59:19.112153
1766 22:59:19.112235 Set Vref, RX VrefLevel [Byte0]: 55
1767 22:59:19.115496 [Byte1]: 55
1768 22:59:19.119930
1769 22:59:19.120014 Set Vref, RX VrefLevel [Byte0]: 56
1770 22:59:19.122882 [Byte1]: 56
1771 22:59:19.127193
1772 22:59:19.127343 Set Vref, RX VrefLevel [Byte0]: 57
1773 22:59:19.130614 [Byte1]: 57
1774 22:59:19.134576
1775 22:59:19.134667 Set Vref, RX VrefLevel [Byte0]: 58
1776 22:59:19.138255 [Byte1]: 58
1777 22:59:19.142539
1778 22:59:19.142621 Set Vref, RX VrefLevel [Byte0]: 59
1779 22:59:19.145915 [Byte1]: 59
1780 22:59:19.150314
1781 22:59:19.150396 Set Vref, RX VrefLevel [Byte0]: 60
1782 22:59:19.153559 [Byte1]: 60
1783 22:59:19.157998
1784 22:59:19.158080 Set Vref, RX VrefLevel [Byte0]: 61
1785 22:59:19.160890 [Byte1]: 61
1786 22:59:19.165478
1787 22:59:19.165560 Set Vref, RX VrefLevel [Byte0]: 62
1788 22:59:19.168784 [Byte1]: 62
1789 22:59:19.172692
1790 22:59:19.172774 Set Vref, RX VrefLevel [Byte0]: 63
1791 22:59:19.175997 [Byte1]: 63
1792 22:59:19.180489
1793 22:59:19.180622 Set Vref, RX VrefLevel [Byte0]: 64
1794 22:59:19.183808 [Byte1]: 64
1795 22:59:19.187850
1796 22:59:19.187933 Set Vref, RX VrefLevel [Byte0]: 65
1797 22:59:19.191130 [Byte1]: 65
1798 22:59:19.195547
1799 22:59:19.195629 Set Vref, RX VrefLevel [Byte0]: 66
1800 22:59:19.198653 [Byte1]: 66
1801 22:59:19.203376
1802 22:59:19.203531 Set Vref, RX VrefLevel [Byte0]: 67
1803 22:59:19.206689 [Byte1]: 67
1804 22:59:19.210978
1805 22:59:19.211061 Set Vref, RX VrefLevel [Byte0]: 68
1806 22:59:19.214253 [Byte1]: 68
1807 22:59:19.218062
1808 22:59:19.218160 Set Vref, RX VrefLevel [Byte0]: 69
1809 22:59:19.222229 [Byte1]: 69
1810 22:59:19.225778
1811 22:59:19.225862 Set Vref, RX VrefLevel [Byte0]: 70
1812 22:59:19.229149 [Byte1]: 70
1813 22:59:19.233675
1814 22:59:19.233756 Set Vref, RX VrefLevel [Byte0]: 71
1815 22:59:19.236891 [Byte1]: 71
1816 22:59:19.241232
1817 22:59:19.241315 Set Vref, RX VrefLevel [Byte0]: 72
1818 22:59:19.244799 [Byte1]: 72
1819 22:59:19.249044
1820 22:59:19.249126 Set Vref, RX VrefLevel [Byte0]: 73
1821 22:59:19.251886 [Byte1]: 73
1822 22:59:19.256292
1823 22:59:19.256374 Set Vref, RX VrefLevel [Byte0]: 74
1824 22:59:19.259580 [Byte1]: 74
1825 22:59:19.264118
1826 22:59:19.264190 Final RX Vref Byte 0 = 59 to rank0
1827 22:59:19.267760 Final RX Vref Byte 1 = 59 to rank0
1828 22:59:19.270937 Final RX Vref Byte 0 = 59 to rank1
1829 22:59:19.274157 Final RX Vref Byte 1 = 59 to rank1==
1830 22:59:19.277041 Dram Type= 6, Freq= 0, CH_1, rank 0
1831 22:59:19.284234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1832 22:59:19.284317 ==
1833 22:59:19.284382 DQS Delay:
1834 22:59:19.284444 DQS0 = 0, DQS1 = 0
1835 22:59:19.287513 DQM Delay:
1836 22:59:19.287586 DQM0 = 86, DQM1 = 80
1837 22:59:19.290824 DQ Delay:
1838 22:59:19.293901 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1839 22:59:19.294037 DQ4 =84, DQ5 =96, DQ6 =96, DQ7 =84
1840 22:59:19.297345 DQ8 =68, DQ9 =72, DQ10 =80, DQ11 =72
1841 22:59:19.303835 DQ12 =88, DQ13 =92, DQ14 =84, DQ15 =88
1842 22:59:19.303918
1843 22:59:19.303983
1844 22:59:19.310486 [DQSOSCAuto] RK0, (LSB)MR18= 0x1629, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 404 ps
1845 22:59:19.314192 CH1 RK0: MR19=606, MR18=1629
1846 22:59:19.320651 CH1_RK0: MR19=0x606, MR18=0x1629, DQSOSC=399, MR23=63, INC=92, DEC=61
1847 22:59:19.320740
1848 22:59:19.323871 ----->DramcWriteLeveling(PI) begin...
1849 22:59:19.323969 ==
1850 22:59:19.327252 Dram Type= 6, Freq= 0, CH_1, rank 1
1851 22:59:19.330340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1852 22:59:19.330415 ==
1853 22:59:19.333845 Write leveling (Byte 0): 25 => 25
1854 22:59:19.337197 Write leveling (Byte 1): 29 => 29
1855 22:59:19.340741 DramcWriteLeveling(PI) end<-----
1856 22:59:19.340824
1857 22:59:19.340889 ==
1858 22:59:19.343712 Dram Type= 6, Freq= 0, CH_1, rank 1
1859 22:59:19.347125 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1860 22:59:19.347208 ==
1861 22:59:19.350609 [Gating] SW mode calibration
1862 22:59:19.357181 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1863 22:59:19.363932 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1864 22:59:19.366809 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1865 22:59:19.369985 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1866 22:59:19.376772 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1867 22:59:19.380183 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1868 22:59:19.383250 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1869 22:59:19.390189 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1870 22:59:19.393404 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 22:59:19.396402 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 22:59:19.402869 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 22:59:19.406253 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 22:59:19.409567 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 22:59:19.416344 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 22:59:19.419660 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 22:59:19.422823 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 22:59:19.429877 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 22:59:19.433031 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 22:59:19.436379 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1881 22:59:19.443109 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1882 22:59:19.446446 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 22:59:19.449269 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 22:59:19.455969 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 22:59:19.459498 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 22:59:19.462815 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 22:59:19.469372 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 22:59:19.472789 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 22:59:19.476177 0 9 4 | B1->B0 | 2323 2e2e | 1 0 | (1 1) (0 0)
1890 22:59:19.482372 0 9 8 | B1->B0 | 2929 3434 | 1 1 | (1 1) (1 1)
1891 22:59:19.486262 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1892 22:59:19.488921 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1893 22:59:19.496264 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1894 22:59:19.499303 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1895 22:59:19.502541 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1896 22:59:19.509174 0 10 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
1897 22:59:19.512418 0 10 4 | B1->B0 | 3434 3030 | 1 0 | (1 1) (1 1)
1898 22:59:19.515695 0 10 8 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
1899 22:59:19.522424 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 22:59:19.525706 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1901 22:59:19.528856 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 22:59:19.535479 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1903 22:59:19.538644 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1904 22:59:19.542010 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1905 22:59:19.548688 0 11 4 | B1->B0 | 2424 3d3d | 1 0 | (0 0) (0 0)
1906 22:59:19.551926 0 11 8 | B1->B0 | 3e3e 4646 | 1 0 | (0 0) (0 0)
1907 22:59:19.555271 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1908 22:59:19.561769 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1909 22:59:19.565273 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1910 22:59:19.568675 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1911 22:59:19.575166 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1912 22:59:19.578382 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1913 22:59:19.581708 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1914 22:59:19.588388 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1915 22:59:19.591747 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1916 22:59:19.595023 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1917 22:59:19.601752 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1918 22:59:19.605054 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1919 22:59:19.608115 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1920 22:59:19.614860 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1921 22:59:19.618153 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1922 22:59:19.621640 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1923 22:59:19.628392 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1924 22:59:19.631781 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1925 22:59:19.634813 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1926 22:59:19.638236 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1927 22:59:19.644803 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1928 22:59:19.648192 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1929 22:59:19.651526 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1930 22:59:19.657943 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1931 22:59:19.661322 Total UI for P1: 0, mck2ui 16
1932 22:59:19.664659 best dqsien dly found for B0: ( 0, 14, 2)
1933 22:59:19.667908 Total UI for P1: 0, mck2ui 16
1934 22:59:19.671290 best dqsien dly found for B1: ( 0, 14, 6)
1935 22:59:19.674529 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1936 22:59:19.677764 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1937 22:59:19.677850
1938 22:59:19.681433 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1939 22:59:19.684215 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1940 22:59:19.687498 [Gating] SW calibration Done
1941 22:59:19.687570 ==
1942 22:59:19.690944 Dram Type= 6, Freq= 0, CH_1, rank 1
1943 22:59:19.694522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1944 22:59:19.694604 ==
1945 22:59:19.697566 RX Vref Scan: 0
1946 22:59:19.697640
1947 22:59:19.701342 RX Vref 0 -> 0, step: 1
1948 22:59:19.701424
1949 22:59:19.701488 RX Delay -130 -> 252, step: 16
1950 22:59:19.707893 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1951 22:59:19.710924 iDelay=206, Bit 1, Center 77 (-50 ~ 205) 256
1952 22:59:19.714160 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1953 22:59:19.717593 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1954 22:59:19.720878 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1955 22:59:19.728016 iDelay=206, Bit 5, Center 85 (-34 ~ 205) 240
1956 22:59:19.731268 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1957 22:59:19.734567 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1958 22:59:19.737787 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1959 22:59:19.740836 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1960 22:59:19.747526 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1961 22:59:19.750744 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1962 22:59:19.754265 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1963 22:59:19.757776 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1964 22:59:19.764160 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1965 22:59:19.767558 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1966 22:59:19.768027 ==
1967 22:59:19.771079 Dram Type= 6, Freq= 0, CH_1, rank 1
1968 22:59:19.774217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1969 22:59:19.774595 ==
1970 22:59:19.774937 DQS Delay:
1971 22:59:19.777725 DQS0 = 0, DQS1 = 0
1972 22:59:19.778150 DQM Delay:
1973 22:59:19.780907 DQM0 = 82, DQM1 = 79
1974 22:59:19.781359 DQ Delay:
1975 22:59:19.784187 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =85
1976 22:59:19.787477 DQ4 =85, DQ5 =85, DQ6 =85, DQ7 =85
1977 22:59:19.790901 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1978 22:59:19.794088 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1979 22:59:19.794580
1980 22:59:19.794923
1981 22:59:19.795289 ==
1982 22:59:19.797748 Dram Type= 6, Freq= 0, CH_1, rank 1
1983 22:59:19.800450 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1984 22:59:19.803770 ==
1985 22:59:19.804251
1986 22:59:19.804591
1987 22:59:19.804905 TX Vref Scan disable
1988 22:59:19.807075 == TX Byte 0 ==
1989 22:59:19.810410 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1990 22:59:19.816733 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1991 22:59:19.817159 == TX Byte 1 ==
1992 22:59:19.820248 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1993 22:59:19.827102 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1994 22:59:19.827684 ==
1995 22:59:19.830152 Dram Type= 6, Freq= 0, CH_1, rank 1
1996 22:59:19.833453 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1997 22:59:19.834025 ==
1998 22:59:19.846836 TX Vref=22, minBit 1, minWin=27, winSum=444
1999 22:59:19.849998 TX Vref=24, minBit 1, minWin=27, winSum=446
2000 22:59:19.853709 TX Vref=26, minBit 1, minWin=27, winSum=453
2001 22:59:19.856867 TX Vref=28, minBit 0, minWin=28, winSum=456
2002 22:59:19.859486 TX Vref=30, minBit 0, minWin=28, winSum=457
2003 22:59:19.866649 TX Vref=32, minBit 1, minWin=27, winSum=454
2004 22:59:19.869905 [TxChooseVref] Worse bit 0, Min win 28, Win sum 457, Final Vref 30
2005 22:59:19.870328
2006 22:59:19.873261 Final TX Range 1 Vref 30
2007 22:59:19.873684
2008 22:59:19.874016 ==
2009 22:59:19.876080 Dram Type= 6, Freq= 0, CH_1, rank 1
2010 22:59:19.879394 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2011 22:59:19.882761 ==
2012 22:59:19.883336
2013 22:59:19.883731
2014 22:59:19.884344 TX Vref Scan disable
2015 22:59:19.886528 == TX Byte 0 ==
2016 22:59:19.889817 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
2017 22:59:19.896254 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
2018 22:59:19.896810 == TX Byte 1 ==
2019 22:59:19.899718 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2020 22:59:19.906483 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2021 22:59:19.907048
2022 22:59:19.907558 [DATLAT]
2023 22:59:19.908108 Freq=800, CH1 RK1
2024 22:59:19.908648
2025 22:59:19.909478 DATLAT Default: 0xa
2026 22:59:19.909875 0, 0xFFFF, sum = 0
2027 22:59:19.913386 1, 0xFFFF, sum = 0
2028 22:59:19.913893 2, 0xFFFF, sum = 0
2029 22:59:19.916542 3, 0xFFFF, sum = 0
2030 22:59:19.919672 4, 0xFFFF, sum = 0
2031 22:59:19.920450 5, 0xFFFF, sum = 0
2032 22:59:19.923054 6, 0xFFFF, sum = 0
2033 22:59:19.923516 7, 0xFFFF, sum = 0
2034 22:59:19.926369 8, 0xFFFF, sum = 0
2035 22:59:19.926818 9, 0x0, sum = 1
2036 22:59:19.930193 10, 0x0, sum = 2
2037 22:59:19.930795 11, 0x0, sum = 3
2038 22:59:19.931148 12, 0x0, sum = 4
2039 22:59:19.933086 best_step = 10
2040 22:59:19.933511
2041 22:59:19.933842 ==
2042 22:59:19.936396 Dram Type= 6, Freq= 0, CH_1, rank 1
2043 22:59:19.939529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2044 22:59:19.939983 ==
2045 22:59:19.942588 RX Vref Scan: 0
2046 22:59:19.943052
2047 22:59:19.943392 RX Vref 0 -> 0, step: 1
2048 22:59:19.945978
2049 22:59:19.946449 RX Delay -95 -> 252, step: 8
2050 22:59:19.953379 iDelay=209, Bit 0, Center 92 (-23 ~ 208) 232
2051 22:59:19.956206 iDelay=209, Bit 1, Center 80 (-39 ~ 200) 240
2052 22:59:19.959745 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
2053 22:59:19.962915 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
2054 22:59:19.966228 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
2055 22:59:19.973040 iDelay=209, Bit 5, Center 96 (-15 ~ 208) 224
2056 22:59:19.976367 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
2057 22:59:19.979660 iDelay=209, Bit 7, Center 84 (-31 ~ 200) 232
2058 22:59:19.982754 iDelay=209, Bit 8, Center 72 (-39 ~ 184) 224
2059 22:59:19.986140 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
2060 22:59:19.992948 iDelay=209, Bit 10, Center 84 (-31 ~ 200) 232
2061 22:59:19.995875 iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224
2062 22:59:19.999216 iDelay=209, Bit 12, Center 88 (-23 ~ 200) 224
2063 22:59:20.002679 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2064 22:59:20.009444 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2065 22:59:20.013000 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
2066 22:59:20.013425 ==
2067 22:59:20.016119 Dram Type= 6, Freq= 0, CH_1, rank 1
2068 22:59:20.019446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2069 22:59:20.019875 ==
2070 22:59:20.022769 DQS Delay:
2071 22:59:20.023193 DQS0 = 0, DQS1 = 0
2072 22:59:20.023526 DQM Delay:
2073 22:59:20.026133 DQM0 = 86, DQM1 = 82
2074 22:59:20.026555 DQ Delay:
2075 22:59:20.029559 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =80
2076 22:59:20.032974 DQ4 =84, DQ5 =96, DQ6 =96, DQ7 =84
2077 22:59:20.035590 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =80
2078 22:59:20.038903 DQ12 =88, DQ13 =88, DQ14 =88, DQ15 =88
2079 22:59:20.039328
2080 22:59:20.039661
2081 22:59:20.048767 [DQSOSCAuto] RK1, (LSB)MR18= 0x213d, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 401 ps
2082 22:59:20.049197 CH1 RK1: MR19=606, MR18=213D
2083 22:59:20.055846 CH1_RK1: MR19=0x606, MR18=0x213D, DQSOSC=394, MR23=63, INC=95, DEC=63
2084 22:59:20.059192 [RxdqsGatingPostProcess] freq 800
2085 22:59:20.065810 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2086 22:59:20.069238 Pre-setting of DQS Precalculation
2087 22:59:20.072434 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2088 22:59:20.079156 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2089 22:59:20.089224 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2090 22:59:20.089667
2091 22:59:20.090023
2092 22:59:20.092404 [Calibration Summary] 1600 Mbps
2093 22:59:20.092877 CH 0, Rank 0
2094 22:59:20.095527 SW Impedance : PASS
2095 22:59:20.096138 DUTY Scan : NO K
2096 22:59:20.098856 ZQ Calibration : PASS
2097 22:59:20.101714 Jitter Meter : NO K
2098 22:59:20.102313 CBT Training : PASS
2099 22:59:20.105290 Write leveling : PASS
2100 22:59:20.108401 RX DQS gating : PASS
2101 22:59:20.108875 RX DQ/DQS(RDDQC) : PASS
2102 22:59:20.111710 TX DQ/DQS : PASS
2103 22:59:20.115218 RX DATLAT : PASS
2104 22:59:20.115798 RX DQ/DQS(Engine): PASS
2105 22:59:20.118500 TX OE : NO K
2106 22:59:20.119046 All Pass.
2107 22:59:20.119537
2108 22:59:20.121782 CH 0, Rank 1
2109 22:59:20.122338 SW Impedance : PASS
2110 22:59:20.125231 DUTY Scan : NO K
2111 22:59:20.125711 ZQ Calibration : PASS
2112 22:59:20.128462 Jitter Meter : NO K
2113 22:59:20.131548 CBT Training : PASS
2114 22:59:20.132185 Write leveling : PASS
2115 22:59:20.134827 RX DQS gating : PASS
2116 22:59:20.138219 RX DQ/DQS(RDDQC) : PASS
2117 22:59:20.138812 TX DQ/DQS : PASS
2118 22:59:20.141700 RX DATLAT : PASS
2119 22:59:20.145097 RX DQ/DQS(Engine): PASS
2120 22:59:20.145615 TX OE : NO K
2121 22:59:20.148133 All Pass.
2122 22:59:20.148656
2123 22:59:20.149103 CH 1, Rank 0
2124 22:59:20.151270 SW Impedance : PASS
2125 22:59:20.151775 DUTY Scan : NO K
2126 22:59:20.154504 ZQ Calibration : PASS
2127 22:59:20.157817 Jitter Meter : NO K
2128 22:59:20.157927 CBT Training : PASS
2129 22:59:20.161073 Write leveling : PASS
2130 22:59:20.164479 RX DQS gating : PASS
2131 22:59:20.164570 RX DQ/DQS(RDDQC) : PASS
2132 22:59:20.167849 TX DQ/DQS : PASS
2133 22:59:20.170731 RX DATLAT : PASS
2134 22:59:20.170829 RX DQ/DQS(Engine): PASS
2135 22:59:20.174254 TX OE : NO K
2136 22:59:20.174351 All Pass.
2137 22:59:20.174440
2138 22:59:20.177969 CH 1, Rank 1
2139 22:59:20.178067 SW Impedance : PASS
2140 22:59:20.180759 DUTY Scan : NO K
2141 22:59:20.183988 ZQ Calibration : PASS
2142 22:59:20.184121 Jitter Meter : NO K
2143 22:59:20.187990 CBT Training : PASS
2144 22:59:20.188093 Write leveling : PASS
2145 22:59:20.190726 RX DQS gating : PASS
2146 22:59:20.194098 RX DQ/DQS(RDDQC) : PASS
2147 22:59:20.194178 TX DQ/DQS : PASS
2148 22:59:20.197403 RX DATLAT : PASS
2149 22:59:20.200718 RX DQ/DQS(Engine): PASS
2150 22:59:20.200813 TX OE : NO K
2151 22:59:20.204115 All Pass.
2152 22:59:20.204213
2153 22:59:20.204303 DramC Write-DBI off
2154 22:59:20.207417 PER_BANK_REFRESH: Hybrid Mode
2155 22:59:20.210785 TX_TRACKING: ON
2156 22:59:20.214273 [GetDramInforAfterCalByMRR] Vendor 6.
2157 22:59:20.217467 [GetDramInforAfterCalByMRR] Revision 606.
2158 22:59:20.220868 [GetDramInforAfterCalByMRR] Revision 2 0.
2159 22:59:20.220973 MR0 0x3b3b
2160 22:59:20.221065 MR8 0x5151
2161 22:59:20.227692 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2162 22:59:20.227798
2163 22:59:20.227890 MR0 0x3b3b
2164 22:59:20.227979 MR8 0x5151
2165 22:59:20.230696 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2166 22:59:20.230778
2167 22:59:20.241011 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2168 22:59:20.243711 [FAST_K] Save calibration result to emmc
2169 22:59:20.247136 [FAST_K] Save calibration result to emmc
2170 22:59:20.250843 dram_init: config_dvfs: 1
2171 22:59:20.254020 dramc_set_vcore_voltage set vcore to 662500
2172 22:59:20.257384 Read voltage for 1200, 2
2173 22:59:20.257467 Vio18 = 0
2174 22:59:20.257533 Vcore = 662500
2175 22:59:20.260461 Vdram = 0
2176 22:59:20.260543 Vddq = 0
2177 22:59:20.260609 Vmddr = 0
2178 22:59:20.267349 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2179 22:59:20.271333 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2180 22:59:20.273963 MEM_TYPE=3, freq_sel=15
2181 22:59:20.277291 sv_algorithm_assistance_LP4_1600
2182 22:59:20.280682 ============ PULL DRAM RESETB DOWN ============
2183 22:59:20.287143 ========== PULL DRAM RESETB DOWN end =========
2184 22:59:20.290548 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2185 22:59:20.293674 ===================================
2186 22:59:20.297047 LPDDR4 DRAM CONFIGURATION
2187 22:59:20.300414 ===================================
2188 22:59:20.300997 EX_ROW_EN[0] = 0x0
2189 22:59:20.303712 EX_ROW_EN[1] = 0x0
2190 22:59:20.304309 LP4Y_EN = 0x0
2191 22:59:20.306917 WORK_FSP = 0x0
2192 22:59:20.307516 WL = 0x4
2193 22:59:20.310116 RL = 0x4
2194 22:59:20.310669 BL = 0x2
2195 22:59:20.313300 RPST = 0x0
2196 22:59:20.313902 RD_PRE = 0x0
2197 22:59:20.316840 WR_PRE = 0x1
2198 22:59:20.320104 WR_PST = 0x0
2199 22:59:20.320665 DBI_WR = 0x0
2200 22:59:20.323723 DBI_RD = 0x0
2201 22:59:20.324309 OTF = 0x1
2202 22:59:20.326974 ===================================
2203 22:59:20.330120 ===================================
2204 22:59:20.333377 ANA top config
2205 22:59:20.336318 ===================================
2206 22:59:20.336592 DLL_ASYNC_EN = 0
2207 22:59:20.340197 ALL_SLAVE_EN = 0
2208 22:59:20.343176 NEW_RANK_MODE = 1
2209 22:59:20.346370 DLL_IDLE_MODE = 1
2210 22:59:20.346533 LP45_APHY_COMB_EN = 1
2211 22:59:20.349809 TX_ODT_DIS = 1
2212 22:59:20.352809 NEW_8X_MODE = 1
2213 22:59:20.356764 ===================================
2214 22:59:20.359754 ===================================
2215 22:59:20.362986 data_rate = 2400
2216 22:59:20.366365 CKR = 1
2217 22:59:20.366447 DQ_P2S_RATIO = 8
2218 22:59:20.369397 ===================================
2219 22:59:20.372737 CA_P2S_RATIO = 8
2220 22:59:20.375994 DQ_CA_OPEN = 0
2221 22:59:20.379513 DQ_SEMI_OPEN = 0
2222 22:59:20.382835 CA_SEMI_OPEN = 0
2223 22:59:20.386063 CA_FULL_RATE = 0
2224 22:59:20.386138 DQ_CKDIV4_EN = 0
2225 22:59:20.389389 CA_CKDIV4_EN = 0
2226 22:59:20.392724 CA_PREDIV_EN = 0
2227 22:59:20.395937 PH8_DLY = 17
2228 22:59:20.399236 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2229 22:59:20.402832 DQ_AAMCK_DIV = 4
2230 22:59:20.406127 CA_AAMCK_DIV = 4
2231 22:59:20.406205 CA_ADMCK_DIV = 4
2232 22:59:20.409300 DQ_TRACK_CA_EN = 0
2233 22:59:20.412677 CA_PICK = 1200
2234 22:59:20.415954 CA_MCKIO = 1200
2235 22:59:20.419254 MCKIO_SEMI = 0
2236 22:59:20.422700 PLL_FREQ = 2366
2237 22:59:20.425955 DQ_UI_PI_RATIO = 32
2238 22:59:20.426027 CA_UI_PI_RATIO = 0
2239 22:59:20.429228 ===================================
2240 22:59:20.432121 ===================================
2241 22:59:20.435505 memory_type:LPDDR4
2242 22:59:20.439086 GP_NUM : 10
2243 22:59:20.439162 SRAM_EN : 1
2244 22:59:20.442416 MD32_EN : 0
2245 22:59:20.445861 ===================================
2246 22:59:20.449101 [ANA_INIT] >>>>>>>>>>>>>>
2247 22:59:20.452163 <<<<<< [CONFIGURE PHASE]: ANA_TX
2248 22:59:20.455272 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2249 22:59:20.459061 ===================================
2250 22:59:20.459145 data_rate = 2400,PCW = 0X5b00
2251 22:59:20.462123 ===================================
2252 22:59:20.465594 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2253 22:59:20.471942 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2254 22:59:20.478742 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2255 22:59:20.482203 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2256 22:59:20.485509 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2257 22:59:20.488723 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2258 22:59:20.492192 [ANA_INIT] flow start
2259 22:59:20.495380 [ANA_INIT] PLL >>>>>>>>
2260 22:59:20.495451 [ANA_INIT] PLL <<<<<<<<
2261 22:59:20.498342 [ANA_INIT] MIDPI >>>>>>>>
2262 22:59:20.501662 [ANA_INIT] MIDPI <<<<<<<<
2263 22:59:20.501733 [ANA_INIT] DLL >>>>>>>>
2264 22:59:20.505428 [ANA_INIT] DLL <<<<<<<<
2265 22:59:20.508760 [ANA_INIT] flow end
2266 22:59:20.511967 ============ LP4 DIFF to SE enter ============
2267 22:59:20.514983 ============ LP4 DIFF to SE exit ============
2268 22:59:20.518357 [ANA_INIT] <<<<<<<<<<<<<
2269 22:59:20.521456 [Flow] Enable top DCM control >>>>>
2270 22:59:20.524980 [Flow] Enable top DCM control <<<<<
2271 22:59:20.528266 Enable DLL master slave shuffle
2272 22:59:20.531657 ==============================================================
2273 22:59:20.535172 Gating Mode config
2274 22:59:20.541439 ==============================================================
2275 22:59:20.541545 Config description:
2276 22:59:20.551875 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2277 22:59:20.557979 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2278 22:59:20.564634 SELPH_MODE 0: By rank 1: By Phase
2279 22:59:20.567958 ==============================================================
2280 22:59:20.571351 GAT_TRACK_EN = 1
2281 22:59:20.574766 RX_GATING_MODE = 2
2282 22:59:20.577759 RX_GATING_TRACK_MODE = 2
2283 22:59:20.581486 SELPH_MODE = 1
2284 22:59:20.584372 PICG_EARLY_EN = 1
2285 22:59:20.587692 VALID_LAT_VALUE = 1
2286 22:59:20.591354 ==============================================================
2287 22:59:20.594302 Enter into Gating configuration >>>>
2288 22:59:20.597815 Exit from Gating configuration <<<<
2289 22:59:20.601387 Enter into DVFS_PRE_config >>>>>
2290 22:59:20.614293 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2291 22:59:20.617606 Exit from DVFS_PRE_config <<<<<
2292 22:59:20.617706 Enter into PICG configuration >>>>
2293 22:59:20.621060 Exit from PICG configuration <<<<
2294 22:59:20.624625 [RX_INPUT] configuration >>>>>
2295 22:59:20.627685 [RX_INPUT] configuration <<<<<
2296 22:59:20.634442 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2297 22:59:20.637842 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2298 22:59:20.644711 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2299 22:59:20.651443 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2300 22:59:20.657387 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2301 22:59:20.663946 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2302 22:59:20.667655 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2303 22:59:20.670886 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2304 22:59:20.674177 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2305 22:59:20.680676 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2306 22:59:20.684271 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2307 22:59:20.687138 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2308 22:59:20.690505 ===================================
2309 22:59:20.693810 LPDDR4 DRAM CONFIGURATION
2310 22:59:20.697088 ===================================
2311 22:59:20.700425 EX_ROW_EN[0] = 0x0
2312 22:59:20.700497 EX_ROW_EN[1] = 0x0
2313 22:59:20.703854 LP4Y_EN = 0x0
2314 22:59:20.703924 WORK_FSP = 0x0
2315 22:59:20.707083 WL = 0x4
2316 22:59:20.707182 RL = 0x4
2317 22:59:20.710470 BL = 0x2
2318 22:59:20.710565 RPST = 0x0
2319 22:59:20.713648 RD_PRE = 0x0
2320 22:59:20.713718 WR_PRE = 0x1
2321 22:59:20.717037 WR_PST = 0x0
2322 22:59:20.717107 DBI_WR = 0x0
2323 22:59:20.720282 DBI_RD = 0x0
2324 22:59:20.720376 OTF = 0x1
2325 22:59:20.726793 ===================================
2326 22:59:20.730038 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2327 22:59:20.733380 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2328 22:59:20.736691 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2329 22:59:20.740265 ===================================
2330 22:59:20.743689 LPDDR4 DRAM CONFIGURATION
2331 22:59:20.746338 ===================================
2332 22:59:20.749908 EX_ROW_EN[0] = 0x10
2333 22:59:20.750006 EX_ROW_EN[1] = 0x0
2334 22:59:20.753186 LP4Y_EN = 0x0
2335 22:59:20.753258 WORK_FSP = 0x0
2336 22:59:20.756548 WL = 0x4
2337 22:59:20.756618 RL = 0x4
2338 22:59:20.759882 BL = 0x2
2339 22:59:20.759977 RPST = 0x0
2340 22:59:20.763485 RD_PRE = 0x0
2341 22:59:20.763569 WR_PRE = 0x1
2342 22:59:20.766188 WR_PST = 0x0
2343 22:59:20.769528 DBI_WR = 0x0
2344 22:59:20.769638 DBI_RD = 0x0
2345 22:59:20.773217 OTF = 0x1
2346 22:59:20.776341 ===================================
2347 22:59:20.779316 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2348 22:59:20.783062 ==
2349 22:59:20.783161 Dram Type= 6, Freq= 0, CH_0, rank 0
2350 22:59:20.789339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2351 22:59:20.789417 ==
2352 22:59:20.792585 [Duty_Offset_Calibration]
2353 22:59:20.792658 B0:2 B1:0 CA:4
2354 22:59:20.792721
2355 22:59:20.795942 [DutyScan_Calibration_Flow] k_type=0
2356 22:59:20.804788
2357 22:59:20.804860 ==CLK 0==
2358 22:59:20.808008 Final CLK duty delay cell = -4
2359 22:59:20.811623 [-4] MAX Duty = 5031%(X100), DQS PI = 14
2360 22:59:20.814652 [-4] MIN Duty = 4844%(X100), DQS PI = 8
2361 22:59:20.817910 [-4] AVG Duty = 4937%(X100)
2362 22:59:20.818012
2363 22:59:20.821406 CH0 CLK Duty spec in!! Max-Min= 187%
2364 22:59:20.824611 [DutyScan_Calibration_Flow] ====Done====
2365 22:59:20.824719
2366 22:59:20.827813 [DutyScan_Calibration_Flow] k_type=1
2367 22:59:20.844113
2368 22:59:20.844194 ==DQS 0 ==
2369 22:59:20.847469 Final DQS duty delay cell = 0
2370 22:59:20.850755 [0] MAX Duty = 5156%(X100), DQS PI = 18
2371 22:59:20.854243 [0] MIN Duty = 5093%(X100), DQS PI = 0
2372 22:59:20.854350 [0] AVG Duty = 5124%(X100)
2373 22:59:20.857471
2374 22:59:20.857579 ==DQS 1 ==
2375 22:59:20.860976 Final DQS duty delay cell = 0
2376 22:59:20.863979 [0] MAX Duty = 5125%(X100), DQS PI = 4
2377 22:59:20.867595 [0] MIN Duty = 5000%(X100), DQS PI = 0
2378 22:59:20.867704 [0] AVG Duty = 5062%(X100)
2379 22:59:20.867799
2380 22:59:20.874201 CH0 DQS 0 Duty spec in!! Max-Min= 63%
2381 22:59:20.874312
2382 22:59:20.877593 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2383 22:59:20.880672 [DutyScan_Calibration_Flow] ====Done====
2384 22:59:20.880753
2385 22:59:20.884223 [DutyScan_Calibration_Flow] k_type=3
2386 22:59:20.900491
2387 22:59:20.900607 ==DQM 0 ==
2388 22:59:20.904137 Final DQM duty delay cell = 0
2389 22:59:20.907380 [0] MAX Duty = 5125%(X100), DQS PI = 20
2390 22:59:20.910503 [0] MIN Duty = 4844%(X100), DQS PI = 52
2391 22:59:20.913824 [0] AVG Duty = 4984%(X100)
2392 22:59:20.913893
2393 22:59:20.913953 ==DQM 1 ==
2394 22:59:20.917026 Final DQM duty delay cell = 0
2395 22:59:20.920292 [0] MAX Duty = 4969%(X100), DQS PI = 0
2396 22:59:20.923935 [0] MIN Duty = 4875%(X100), DQS PI = 20
2397 22:59:20.927020 [0] AVG Duty = 4922%(X100)
2398 22:59:20.927119
2399 22:59:20.930370 CH0 DQM 0 Duty spec in!! Max-Min= 281%
2400 22:59:20.930467
2401 22:59:20.933662 CH0 DQM 1 Duty spec in!! Max-Min= 94%
2402 22:59:20.937113 [DutyScan_Calibration_Flow] ====Done====
2403 22:59:20.937209
2404 22:59:20.940455 [DutyScan_Calibration_Flow] k_type=2
2405 22:59:20.957050
2406 22:59:20.957133 ==DQ 0 ==
2407 22:59:20.960233 Final DQ duty delay cell = 0
2408 22:59:20.963833 [0] MAX Duty = 5156%(X100), DQS PI = 18
2409 22:59:20.966889 [0] MIN Duty = 5000%(X100), DQS PI = 8
2410 22:59:20.966972 [0] AVG Duty = 5078%(X100)
2411 22:59:20.970251
2412 22:59:20.970332 ==DQ 1 ==
2413 22:59:20.973801 Final DQ duty delay cell = 0
2414 22:59:20.976620 [0] MAX Duty = 5156%(X100), DQS PI = 4
2415 22:59:20.979818 [0] MIN Duty = 4938%(X100), DQS PI = 14
2416 22:59:20.979901 [0] AVG Duty = 5047%(X100)
2417 22:59:20.979967
2418 22:59:20.983441 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2419 22:59:20.986813
2420 22:59:20.990214 CH0 DQ 1 Duty spec in!! Max-Min= 218%
2421 22:59:20.993806 [DutyScan_Calibration_Flow] ====Done====
2422 22:59:20.994228 ==
2423 22:59:20.997415 Dram Type= 6, Freq= 0, CH_1, rank 0
2424 22:59:21.000713 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2425 22:59:21.001146 ==
2426 22:59:21.004150 [Duty_Offset_Calibration]
2427 22:59:21.004596 B0:0 B1:-1 CA:3
2428 22:59:21.004938
2429 22:59:21.007408 [DutyScan_Calibration_Flow] k_type=0
2430 22:59:21.016497
2431 22:59:21.016946 ==CLK 0==
2432 22:59:21.019675 Final CLK duty delay cell = -4
2433 22:59:21.022995 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2434 22:59:21.026138 [-4] MIN Duty = 4876%(X100), DQS PI = 36
2435 22:59:21.029588 [-4] AVG Duty = 4938%(X100)
2436 22:59:21.030097
2437 22:59:21.032940 CH1 CLK Duty spec in!! Max-Min= 124%
2438 22:59:21.036420 [DutyScan_Calibration_Flow] ====Done====
2439 22:59:21.036951
2440 22:59:21.039653 [DutyScan_Calibration_Flow] k_type=1
2441 22:59:21.055426
2442 22:59:21.055945 ==DQS 0 ==
2443 22:59:21.058725 Final DQS duty delay cell = 0
2444 22:59:21.061925 [0] MAX Duty = 5187%(X100), DQS PI = 28
2445 22:59:21.065326 [0] MIN Duty = 4938%(X100), DQS PI = 38
2446 22:59:21.068343 [0] AVG Duty = 5062%(X100)
2447 22:59:21.068816
2448 22:59:21.069175 ==DQS 1 ==
2449 22:59:21.071735 Final DQS duty delay cell = -4
2450 22:59:21.075379 [-4] MAX Duty = 5000%(X100), DQS PI = 32
2451 22:59:21.078763 [-4] MIN Duty = 4875%(X100), DQS PI = 2
2452 22:59:21.081842 [-4] AVG Duty = 4937%(X100)
2453 22:59:21.082345
2454 22:59:21.085205 CH1 DQS 0 Duty spec in!! Max-Min= 249%
2455 22:59:21.085634
2456 22:59:21.088549 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2457 22:59:21.091850 [DutyScan_Calibration_Flow] ====Done====
2458 22:59:21.092324
2459 22:59:21.095270 [DutyScan_Calibration_Flow] k_type=3
2460 22:59:21.112696
2461 22:59:21.113117 ==DQM 0 ==
2462 22:59:21.116117 Final DQM duty delay cell = 0
2463 22:59:21.119524 [0] MAX Duty = 5031%(X100), DQS PI = 26
2464 22:59:21.122847 [0] MIN Duty = 4813%(X100), DQS PI = 38
2465 22:59:21.126047 [0] AVG Duty = 4922%(X100)
2466 22:59:21.126520
2467 22:59:21.126895 ==DQM 1 ==
2468 22:59:21.129201 Final DQM duty delay cell = 4
2469 22:59:21.132945 [4] MAX Duty = 5187%(X100), DQS PI = 30
2470 22:59:21.136325 [4] MIN Duty = 5062%(X100), DQS PI = 0
2471 22:59:21.139063 [4] AVG Duty = 5124%(X100)
2472 22:59:21.139489
2473 22:59:21.142887 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2474 22:59:21.143316
2475 22:59:21.146180 CH1 DQM 1 Duty spec in!! Max-Min= 125%
2476 22:59:21.149597 [DutyScan_Calibration_Flow] ====Done====
2477 22:59:21.150056
2478 22:59:21.152251 [DutyScan_Calibration_Flow] k_type=2
2479 22:59:21.168586
2480 22:59:21.169136 ==DQ 0 ==
2481 22:59:21.171952 Final DQ duty delay cell = -4
2482 22:59:21.175216 [-4] MAX Duty = 5031%(X100), DQS PI = 28
2483 22:59:21.178499 [-4] MIN Duty = 4844%(X100), DQS PI = 36
2484 22:59:21.181549 [-4] AVG Duty = 4937%(X100)
2485 22:59:21.182150
2486 22:59:21.182710 ==DQ 1 ==
2487 22:59:21.184910 Final DQ duty delay cell = 0
2488 22:59:21.188212 [0] MAX Duty = 5031%(X100), DQS PI = 34
2489 22:59:21.191515 [0] MIN Duty = 4844%(X100), DQS PI = 0
2490 22:59:21.195084 [0] AVG Duty = 4937%(X100)
2491 22:59:21.195513
2492 22:59:21.198147 CH1 DQ 0 Duty spec in!! Max-Min= 187%
2493 22:59:21.198577
2494 22:59:21.201929 CH1 DQ 1 Duty spec in!! Max-Min= 187%
2495 22:59:21.204900 [DutyScan_Calibration_Flow] ====Done====
2496 22:59:21.208312 nWR fixed to 30
2497 22:59:21.211641 [ModeRegInit_LP4] CH0 RK0
2498 22:59:21.212198 [ModeRegInit_LP4] CH0 RK1
2499 22:59:21.215038 [ModeRegInit_LP4] CH1 RK0
2500 22:59:21.218112 [ModeRegInit_LP4] CH1 RK1
2501 22:59:21.218539 match AC timing 7
2502 22:59:21.224755 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2503 22:59:21.228286 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2504 22:59:21.231245 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2505 22:59:21.238207 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2506 22:59:21.241271 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2507 22:59:21.241694 ==
2508 22:59:21.245176 Dram Type= 6, Freq= 0, CH_0, rank 0
2509 22:59:21.248206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2510 22:59:21.248635 ==
2511 22:59:21.255077 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2512 22:59:21.261699 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2513 22:59:21.268920 [CA 0] Center 39 (9~70) winsize 62
2514 22:59:21.272521 [CA 1] Center 39 (9~69) winsize 61
2515 22:59:21.275457 [CA 2] Center 35 (5~66) winsize 62
2516 22:59:21.279075 [CA 3] Center 35 (5~66) winsize 62
2517 22:59:21.282092 [CA 4] Center 33 (3~64) winsize 62
2518 22:59:21.285888 [CA 5] Center 33 (3~63) winsize 61
2519 22:59:21.286418
2520 22:59:21.288895 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2521 22:59:21.289323
2522 22:59:21.292332 [CATrainingPosCal] consider 1 rank data
2523 22:59:21.295684 u2DelayCellTimex100 = 270/100 ps
2524 22:59:21.299035 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2525 22:59:21.302057 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2526 22:59:21.308530 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2527 22:59:21.311939 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2528 22:59:21.315360 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2529 22:59:21.318921 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2530 22:59:21.319443
2531 22:59:21.321709 CA PerBit enable=1, Macro0, CA PI delay=33
2532 22:59:21.322137
2533 22:59:21.325068 [CBTSetCACLKResult] CA Dly = 33
2534 22:59:21.325524 CS Dly: 7 (0~38)
2535 22:59:21.328127 ==
2536 22:59:21.331701 Dram Type= 6, Freq= 0, CH_0, rank 1
2537 22:59:21.335380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2538 22:59:21.335941 ==
2539 22:59:21.338055 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2540 22:59:21.344965 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2541 22:59:21.354319 [CA 0] Center 39 (9~70) winsize 62
2542 22:59:21.358264 [CA 1] Center 39 (9~70) winsize 62
2543 22:59:21.361411 [CA 2] Center 35 (5~66) winsize 62
2544 22:59:21.364238 [CA 3] Center 35 (5~66) winsize 62
2545 22:59:21.367649 [CA 4] Center 34 (4~65) winsize 62
2546 22:59:21.371040 [CA 5] Center 33 (3~64) winsize 62
2547 22:59:21.371465
2548 22:59:21.374470 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2549 22:59:21.374898
2550 22:59:21.377767 [CATrainingPosCal] consider 2 rank data
2551 22:59:21.381297 u2DelayCellTimex100 = 270/100 ps
2552 22:59:21.384496 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2553 22:59:21.387906 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2554 22:59:21.394472 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2555 22:59:21.397815 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2556 22:59:21.401163 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2557 22:59:21.404441 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2558 22:59:21.404868
2559 22:59:21.407591 CA PerBit enable=1, Macro0, CA PI delay=33
2560 22:59:21.408014
2561 22:59:21.411110 [CBTSetCACLKResult] CA Dly = 33
2562 22:59:21.411531 CS Dly: 8 (0~41)
2563 22:59:21.411866
2564 22:59:21.414312 ----->DramcWriteLeveling(PI) begin...
2565 22:59:21.417585 ==
2566 22:59:21.420796 Dram Type= 6, Freq= 0, CH_0, rank 0
2567 22:59:21.424220 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2568 22:59:21.424344 ==
2569 22:59:21.427233 Write leveling (Byte 0): 33 => 33
2570 22:59:21.430184 Write leveling (Byte 1): 27 => 27
2571 22:59:21.433622 DramcWriteLeveling(PI) end<-----
2572 22:59:21.433702
2573 22:59:21.433766 ==
2574 22:59:21.437326 Dram Type= 6, Freq= 0, CH_0, rank 0
2575 22:59:21.440335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2576 22:59:21.440418 ==
2577 22:59:21.443903 [Gating] SW mode calibration
2578 22:59:21.450345 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2579 22:59:21.456953 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2580 22:59:21.460373 0 15 0 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
2581 22:59:21.463300 0 15 4 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
2582 22:59:21.469981 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2583 22:59:21.473399 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2584 22:59:21.476980 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2585 22:59:21.483400 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2586 22:59:21.486727 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2587 22:59:21.489912 0 15 28 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
2588 22:59:21.496926 1 0 0 | B1->B0 | 3030 2323 | 1 0 | (1 0) (0 0)
2589 22:59:21.499580 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2590 22:59:21.503303 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2591 22:59:21.510008 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2592 22:59:21.513400 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2593 22:59:21.516604 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2594 22:59:21.522936 1 0 24 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
2595 22:59:21.526622 1 0 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
2596 22:59:21.529574 1 1 0 | B1->B0 | 2a2a 4646 | 0 0 | (0 0) (0 0)
2597 22:59:21.536396 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2598 22:59:21.539480 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2599 22:59:21.542980 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2600 22:59:21.549186 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2601 22:59:21.552805 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2602 22:59:21.555848 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2603 22:59:21.559465 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2604 22:59:21.566204 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2605 22:59:21.569328 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2606 22:59:21.572975 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2607 22:59:21.579010 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2608 22:59:21.582439 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2609 22:59:21.585722 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2610 22:59:21.592275 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2611 22:59:21.595514 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2612 22:59:21.598967 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2613 22:59:21.605801 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2614 22:59:21.609201 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2615 22:59:21.611951 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2616 22:59:21.619149 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2617 22:59:21.622063 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2618 22:59:21.625339 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2619 22:59:21.632023 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2620 22:59:21.635566 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2621 22:59:21.638945 Total UI for P1: 0, mck2ui 16
2622 22:59:21.642343 best dqsien dly found for B0: ( 1, 3, 26)
2623 22:59:21.645368 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2624 22:59:21.652052 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2625 22:59:21.652167 Total UI for P1: 0, mck2ui 16
2626 22:59:21.658647 best dqsien dly found for B1: ( 1, 4, 2)
2627 22:59:21.662239 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2628 22:59:21.665315 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2629 22:59:21.665490
2630 22:59:21.668642 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2631 22:59:21.672257 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2632 22:59:21.675705 [Gating] SW calibration Done
2633 22:59:21.675946 ==
2634 22:59:21.678766 Dram Type= 6, Freq= 0, CH_0, rank 0
2635 22:59:21.682525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2636 22:59:21.682825 ==
2637 22:59:21.685390 RX Vref Scan: 0
2638 22:59:21.685772
2639 22:59:21.686073 RX Vref 0 -> 0, step: 1
2640 22:59:21.686355
2641 22:59:21.688939 RX Delay -40 -> 252, step: 8
2642 22:59:21.692170 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2643 22:59:21.698722 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2644 22:59:21.702463 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2645 22:59:21.705644 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2646 22:59:21.708980 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
2647 22:59:21.712315 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2648 22:59:21.718999 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2649 22:59:21.722505 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2650 22:59:21.725343 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2651 22:59:21.728750 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2652 22:59:21.732298 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2653 22:59:21.738743 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2654 22:59:21.742312 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2655 22:59:21.745079 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2656 22:59:21.748883 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2657 22:59:21.752014 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2658 22:59:21.755159 ==
2659 22:59:21.758724 Dram Type= 6, Freq= 0, CH_0, rank 0
2660 22:59:21.761941 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2661 22:59:21.762368 ==
2662 22:59:21.762701 DQS Delay:
2663 22:59:21.765152 DQS0 = 0, DQS1 = 0
2664 22:59:21.765574 DQM Delay:
2665 22:59:21.768484 DQM0 = 119, DQM1 = 108
2666 22:59:21.768907 DQ Delay:
2667 22:59:21.771730 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =111
2668 22:59:21.775076 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =127
2669 22:59:21.778518 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2670 22:59:21.781823 DQ12 =119, DQ13 =111, DQ14 =119, DQ15 =115
2671 22:59:21.782244
2672 22:59:21.782573
2673 22:59:21.782880 ==
2674 22:59:21.784998 Dram Type= 6, Freq= 0, CH_0, rank 0
2675 22:59:21.791549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2676 22:59:21.791987 ==
2677 22:59:21.792355
2678 22:59:21.792667
2679 22:59:21.792963 TX Vref Scan disable
2680 22:59:21.795453 == TX Byte 0 ==
2681 22:59:21.798868 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2682 22:59:21.805034 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2683 22:59:21.805479 == TX Byte 1 ==
2684 22:59:21.808758 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2685 22:59:21.815096 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2686 22:59:21.815564 ==
2687 22:59:21.818506 Dram Type= 6, Freq= 0, CH_0, rank 0
2688 22:59:21.821931 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2689 22:59:21.822396 ==
2690 22:59:21.833645 TX Vref=22, minBit 1, minWin=25, winSum=413
2691 22:59:21.837264 TX Vref=24, minBit 10, minWin=25, winSum=418
2692 22:59:21.840311 TX Vref=26, minBit 10, minWin=25, winSum=425
2693 22:59:21.843671 TX Vref=28, minBit 1, minWin=26, winSum=428
2694 22:59:21.846885 TX Vref=30, minBit 7, minWin=26, winSum=432
2695 22:59:21.853541 TX Vref=32, minBit 2, minWin=26, winSum=429
2696 22:59:21.856953 [TxChooseVref] Worse bit 7, Min win 26, Win sum 432, Final Vref 30
2697 22:59:21.857429
2698 22:59:21.859766 Final TX Range 1 Vref 30
2699 22:59:21.860279
2700 22:59:21.860722 ==
2701 22:59:21.863464 Dram Type= 6, Freq= 0, CH_0, rank 0
2702 22:59:21.866486 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2703 22:59:21.869871 ==
2704 22:59:21.870337
2705 22:59:21.870786
2706 22:59:21.871214 TX Vref Scan disable
2707 22:59:21.873577 == TX Byte 0 ==
2708 22:59:21.876726 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2709 22:59:21.880389 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2710 22:59:21.883351 == TX Byte 1 ==
2711 22:59:21.887265 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2712 22:59:21.889846 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2713 22:59:21.893303
2714 22:59:21.893742 [DATLAT]
2715 22:59:21.894224 Freq=1200, CH0 RK0
2716 22:59:21.894720
2717 22:59:21.896850 DATLAT Default: 0xd
2718 22:59:21.897292 0, 0xFFFF, sum = 0
2719 22:59:21.900233 1, 0xFFFF, sum = 0
2720 22:59:21.900705 2, 0xFFFF, sum = 0
2721 22:59:21.903457 3, 0xFFFF, sum = 0
2722 22:59:21.906546 4, 0xFFFF, sum = 0
2723 22:59:21.906998 5, 0xFFFF, sum = 0
2724 22:59:21.909650 6, 0xFFFF, sum = 0
2725 22:59:21.910050 7, 0xFFFF, sum = 0
2726 22:59:21.913294 8, 0xFFFF, sum = 0
2727 22:59:21.913739 9, 0xFFFF, sum = 0
2728 22:59:21.916671 10, 0xFFFF, sum = 0
2729 22:59:21.917118 11, 0xFFFF, sum = 0
2730 22:59:21.920056 12, 0x0, sum = 1
2731 22:59:21.920512 13, 0x0, sum = 2
2732 22:59:21.923348 14, 0x0, sum = 3
2733 22:59:21.923795 15, 0x0, sum = 4
2734 22:59:21.926249 best_step = 13
2735 22:59:21.926883
2736 22:59:21.927418 ==
2737 22:59:21.930110 Dram Type= 6, Freq= 0, CH_0, rank 0
2738 22:59:21.933188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2739 22:59:21.933660 ==
2740 22:59:21.934097 RX Vref Scan: 1
2741 22:59:21.934511
2742 22:59:21.936742 Set Vref Range= 32 -> 127
2743 22:59:21.937184
2744 22:59:21.939958 RX Vref 32 -> 127, step: 1
2745 22:59:21.940410
2746 22:59:21.943301 RX Delay -21 -> 252, step: 4
2747 22:59:21.943742
2748 22:59:21.946693 Set Vref, RX VrefLevel [Byte0]: 32
2749 22:59:21.949514 [Byte1]: 32
2750 22:59:21.949957
2751 22:59:21.952920 Set Vref, RX VrefLevel [Byte0]: 33
2752 22:59:21.956171 [Byte1]: 33
2753 22:59:21.959809
2754 22:59:21.960322 Set Vref, RX VrefLevel [Byte0]: 34
2755 22:59:21.963382 [Byte1]: 34
2756 22:59:21.968021
2757 22:59:21.968506 Set Vref, RX VrefLevel [Byte0]: 35
2758 22:59:21.971049 [Byte1]: 35
2759 22:59:21.975668
2760 22:59:21.976203 Set Vref, RX VrefLevel [Byte0]: 36
2761 22:59:21.978819 [Byte1]: 36
2762 22:59:21.984089
2763 22:59:21.984516 Set Vref, RX VrefLevel [Byte0]: 37
2764 22:59:21.987159 [Byte1]: 37
2765 22:59:21.991576
2766 22:59:21.992171 Set Vref, RX VrefLevel [Byte0]: 38
2767 22:59:21.995284 [Byte1]: 38
2768 22:59:21.999381
2769 22:59:21.999806 Set Vref, RX VrefLevel [Byte0]: 39
2770 22:59:22.002644 [Byte1]: 39
2771 22:59:22.007559
2772 22:59:22.007980 Set Vref, RX VrefLevel [Byte0]: 40
2773 22:59:22.010964 [Byte1]: 40
2774 22:59:22.014942
2775 22:59:22.015030 Set Vref, RX VrefLevel [Byte0]: 41
2776 22:59:22.018389 [Byte1]: 41
2777 22:59:22.022852
2778 22:59:22.022962 Set Vref, RX VrefLevel [Byte0]: 42
2779 22:59:22.026341 [Byte1]: 42
2780 22:59:22.030862
2781 22:59:22.030976 Set Vref, RX VrefLevel [Byte0]: 43
2782 22:59:22.034484 [Byte1]: 43
2783 22:59:22.038859
2784 22:59:22.038996 Set Vref, RX VrefLevel [Byte0]: 44
2785 22:59:22.042281 [Byte1]: 44
2786 22:59:22.046987
2787 22:59:22.047136 Set Vref, RX VrefLevel [Byte0]: 45
2788 22:59:22.050076 [Byte1]: 45
2789 22:59:22.054788
2790 22:59:22.054983 Set Vref, RX VrefLevel [Byte0]: 46
2791 22:59:22.058129 [Byte1]: 46
2792 22:59:22.062626
2793 22:59:22.062855 Set Vref, RX VrefLevel [Byte0]: 47
2794 22:59:22.066183 [Byte1]: 47
2795 22:59:22.070755
2796 22:59:22.071267 Set Vref, RX VrefLevel [Byte0]: 48
2797 22:59:22.074411 [Byte1]: 48
2798 22:59:22.078935
2799 22:59:22.079410 Set Vref, RX VrefLevel [Byte0]: 49
2800 22:59:22.082050 [Byte1]: 49
2801 22:59:22.086678
2802 22:59:22.087196 Set Vref, RX VrefLevel [Byte0]: 50
2803 22:59:22.090208 [Byte1]: 50
2804 22:59:22.094516
2805 22:59:22.095030 Set Vref, RX VrefLevel [Byte0]: 51
2806 22:59:22.097791 [Byte1]: 51
2807 22:59:22.102732
2808 22:59:22.103198 Set Vref, RX VrefLevel [Byte0]: 52
2809 22:59:22.106233 [Byte1]: 52
2810 22:59:22.110669
2811 22:59:22.111270 Set Vref, RX VrefLevel [Byte0]: 53
2812 22:59:22.113835 [Byte1]: 53
2813 22:59:22.118262
2814 22:59:22.118736 Set Vref, RX VrefLevel [Byte0]: 54
2815 22:59:22.121454 [Byte1]: 54
2816 22:59:22.126855
2817 22:59:22.127274 Set Vref, RX VrefLevel [Byte0]: 55
2818 22:59:22.130042 [Byte1]: 55
2819 22:59:22.134477
2820 22:59:22.134960 Set Vref, RX VrefLevel [Byte0]: 56
2821 22:59:22.137748 [Byte1]: 56
2822 22:59:22.142269
2823 22:59:22.142746 Set Vref, RX VrefLevel [Byte0]: 57
2824 22:59:22.145593 [Byte1]: 57
2825 22:59:22.150085
2826 22:59:22.150559 Set Vref, RX VrefLevel [Byte0]: 58
2827 22:59:22.153337 [Byte1]: 58
2828 22:59:22.158297
2829 22:59:22.158790 Set Vref, RX VrefLevel [Byte0]: 59
2830 22:59:22.161208 [Byte1]: 59
2831 22:59:22.166139
2832 22:59:22.166616 Set Vref, RX VrefLevel [Byte0]: 60
2833 22:59:22.169471 [Byte1]: 60
2834 22:59:22.173764
2835 22:59:22.174238 Set Vref, RX VrefLevel [Byte0]: 61
2836 22:59:22.177029 [Byte1]: 61
2837 22:59:22.181873
2838 22:59:22.182293 Set Vref, RX VrefLevel [Byte0]: 62
2839 22:59:22.184905 [Byte1]: 62
2840 22:59:22.189606
2841 22:59:22.190069 Set Vref, RX VrefLevel [Byte0]: 63
2842 22:59:22.193176 [Byte1]: 63
2843 22:59:22.197870
2844 22:59:22.198323 Set Vref, RX VrefLevel [Byte0]: 64
2845 22:59:22.200881 [Byte1]: 64
2846 22:59:22.205927
2847 22:59:22.206306 Set Vref, RX VrefLevel [Byte0]: 65
2848 22:59:22.208660 [Byte1]: 65
2849 22:59:22.213773
2850 22:59:22.214251 Set Vref, RX VrefLevel [Byte0]: 66
2851 22:59:22.217503 [Byte1]: 66
2852 22:59:22.221423
2853 22:59:22.221798 Set Vref, RX VrefLevel [Byte0]: 67
2854 22:59:22.224704 [Byte1]: 67
2855 22:59:22.229811
2856 22:59:22.230372 Set Vref, RX VrefLevel [Byte0]: 68
2857 22:59:22.232500 [Byte1]: 68
2858 22:59:22.237688
2859 22:59:22.238171 Final RX Vref Byte 0 = 53 to rank0
2860 22:59:22.240409 Final RX Vref Byte 1 = 58 to rank0
2861 22:59:22.244264 Final RX Vref Byte 0 = 53 to rank1
2862 22:59:22.247615 Final RX Vref Byte 1 = 58 to rank1==
2863 22:59:22.250433 Dram Type= 6, Freq= 0, CH_0, rank 0
2864 22:59:22.257615 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2865 22:59:22.258100 ==
2866 22:59:22.258494 DQS Delay:
2867 22:59:22.258842 DQS0 = 0, DQS1 = 0
2868 22:59:22.260388 DQM Delay:
2869 22:59:22.260871 DQM0 = 117, DQM1 = 105
2870 22:59:22.263910 DQ Delay:
2871 22:59:22.267100 DQ0 =118, DQ1 =116, DQ2 =114, DQ3 =114
2872 22:59:22.270643 DQ4 =120, DQ5 =112, DQ6 =124, DQ7 =122
2873 22:59:22.273909 DQ8 =94, DQ9 =90, DQ10 =106, DQ11 =100
2874 22:59:22.277291 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =112
2875 22:59:22.277774
2876 22:59:22.278166
2877 22:59:22.283948 [DQSOSCAuto] RK0, (LSB)MR18= 0x4ff, (MSB)MR19= 0x403, tDQSOscB0 = 410 ps tDQSOscB1 = 408 ps
2878 22:59:22.286996 CH0 RK0: MR19=403, MR18=4FF
2879 22:59:22.293827 CH0_RK0: MR19=0x403, MR18=0x4FF, DQSOSC=408, MR23=63, INC=39, DEC=26
2880 22:59:22.294251
2881 22:59:22.297217 ----->DramcWriteLeveling(PI) begin...
2882 22:59:22.297664 ==
2883 22:59:22.300489 Dram Type= 6, Freq= 0, CH_0, rank 1
2884 22:59:22.303969 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2885 22:59:22.307095 ==
2886 22:59:22.307532 Write leveling (Byte 0): 31 => 31
2887 22:59:22.310522 Write leveling (Byte 1): 27 => 27
2888 22:59:22.313694 DramcWriteLeveling(PI) end<-----
2889 22:59:22.314114
2890 22:59:22.314443 ==
2891 22:59:22.316732 Dram Type= 6, Freq= 0, CH_0, rank 1
2892 22:59:22.323804 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2893 22:59:22.324341 ==
2894 22:59:22.324694 [Gating] SW mode calibration
2895 22:59:22.333729 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2896 22:59:22.337068 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2897 22:59:22.340439 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2898 22:59:22.346953 0 15 4 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
2899 22:59:22.350212 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2900 22:59:22.353793 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2901 22:59:22.360421 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2902 22:59:22.363693 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2903 22:59:22.367439 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2904 22:59:22.373380 0 15 28 | B1->B0 | 3434 2525 | 0 0 | (0 0) (0 0)
2905 22:59:22.376797 1 0 0 | B1->B0 | 2c2c 2323 | 0 0 | (1 0) (0 0)
2906 22:59:22.380107 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2907 22:59:22.386506 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2908 22:59:22.389877 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2909 22:59:22.393417 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2910 22:59:22.399759 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2911 22:59:22.403222 1 0 24 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
2912 22:59:22.406244 1 0 28 | B1->B0 | 2828 4545 | 0 0 | (1 1) (0 0)
2913 22:59:22.413112 1 1 0 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
2914 22:59:22.416402 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2915 22:59:22.419514 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2916 22:59:22.426374 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2917 22:59:22.429429 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2918 22:59:22.432681 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2919 22:59:22.439249 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2920 22:59:22.443136 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2921 22:59:22.445856 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2922 22:59:22.452965 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2923 22:59:22.455753 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2924 22:59:22.459186 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2925 22:59:22.465706 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2926 22:59:22.469115 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2927 22:59:22.472467 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2928 22:59:22.479177 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2929 22:59:22.482588 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2930 22:59:22.485879 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2931 22:59:22.492535 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2932 22:59:22.495963 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2933 22:59:22.498682 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2934 22:59:22.505518 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2935 22:59:22.509340 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2936 22:59:22.512398 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2937 22:59:22.518773 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2938 22:59:22.519292 Total UI for P1: 0, mck2ui 16
2939 22:59:22.525780 best dqsien dly found for B0: ( 1, 3, 24)
2940 22:59:22.526308 Total UI for P1: 0, mck2ui 16
2941 22:59:22.532059 best dqsien dly found for B1: ( 1, 3, 30)
2942 22:59:22.535435 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
2943 22:59:22.538960 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2944 22:59:22.539391
2945 22:59:22.542227 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
2946 22:59:22.545655 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2947 22:59:22.548958 [Gating] SW calibration Done
2948 22:59:22.549412 ==
2949 22:59:22.552113 Dram Type= 6, Freq= 0, CH_0, rank 1
2950 22:59:22.555738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2951 22:59:22.556377 ==
2952 22:59:22.558935 RX Vref Scan: 0
2953 22:59:22.559363
2954 22:59:22.559701 RX Vref 0 -> 0, step: 1
2955 22:59:22.560116
2956 22:59:22.562021 RX Delay -40 -> 252, step: 8
2957 22:59:22.564728 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2958 22:59:22.571626 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2959 22:59:22.574785 iDelay=200, Bit 2, Center 115 (48 ~ 183) 136
2960 22:59:22.578286 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2961 22:59:22.581589 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2962 22:59:22.584993 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2963 22:59:22.591268 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2964 22:59:22.594571 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2965 22:59:22.597878 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2966 22:59:22.601363 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2967 22:59:22.604526 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2968 22:59:22.611421 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2969 22:59:22.614823 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2970 22:59:22.617893 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2971 22:59:22.621102 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2972 22:59:22.624759 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2973 22:59:22.627924 ==
2974 22:59:22.631132 Dram Type= 6, Freq= 0, CH_0, rank 1
2975 22:59:22.634455 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2976 22:59:22.634540 ==
2977 22:59:22.634608 DQS Delay:
2978 22:59:22.637647 DQS0 = 0, DQS1 = 0
2979 22:59:22.637733 DQM Delay:
2980 22:59:22.640887 DQM0 = 117, DQM1 = 109
2981 22:59:22.640992 DQ Delay:
2982 22:59:22.644498 DQ0 =111, DQ1 =119, DQ2 =115, DQ3 =111
2983 22:59:22.647806 DQ4 =119, DQ5 =111, DQ6 =127, DQ7 =123
2984 22:59:22.651227 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =103
2985 22:59:22.654601 DQ12 =115, DQ13 =115, DQ14 =123, DQ15 =115
2986 22:59:22.654724
2987 22:59:22.654790
2988 22:59:22.654850 ==
2989 22:59:22.657802 Dram Type= 6, Freq= 0, CH_0, rank 1
2990 22:59:22.664448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2991 22:59:22.664533 ==
2992 22:59:22.664599
2993 22:59:22.664660
2994 22:59:22.664719 TX Vref Scan disable
2995 22:59:22.667799 == TX Byte 0 ==
2996 22:59:22.671253 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2997 22:59:22.678019 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2998 22:59:22.678103 == TX Byte 1 ==
2999 22:59:22.681419 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3000 22:59:22.687620 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3001 22:59:22.687704 ==
3002 22:59:22.690981 Dram Type= 6, Freq= 0, CH_0, rank 1
3003 22:59:22.694220 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3004 22:59:22.694303 ==
3005 22:59:22.706210 TX Vref=22, minBit 4, minWin=25, winSum=415
3006 22:59:22.709266 TX Vref=24, minBit 1, minWin=25, winSum=419
3007 22:59:22.712679 TX Vref=26, minBit 0, minWin=26, winSum=421
3008 22:59:22.715754 TX Vref=28, minBit 15, minWin=25, winSum=423
3009 22:59:22.719334 TX Vref=30, minBit 4, minWin=26, winSum=424
3010 22:59:22.725528 TX Vref=32, minBit 0, minWin=26, winSum=421
3011 22:59:22.729368 [TxChooseVref] Worse bit 4, Min win 26, Win sum 424, Final Vref 30
3012 22:59:22.729453
3013 22:59:22.732593 Final TX Range 1 Vref 30
3014 22:59:22.732677
3015 22:59:22.732743 ==
3016 22:59:22.736261 Dram Type= 6, Freq= 0, CH_0, rank 1
3017 22:59:22.739367 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3018 22:59:22.739451 ==
3019 22:59:22.742449
3020 22:59:22.742532
3021 22:59:22.742597 TX Vref Scan disable
3022 22:59:22.745823 == TX Byte 0 ==
3023 22:59:22.748840 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
3024 22:59:22.752218 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
3025 22:59:22.755713 == TX Byte 1 ==
3026 22:59:22.758998 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3027 22:59:22.762488 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3028 22:59:22.765578
3029 22:59:22.765661 [DATLAT]
3030 22:59:22.765727 Freq=1200, CH0 RK1
3031 22:59:22.765796
3032 22:59:22.768736 DATLAT Default: 0xd
3033 22:59:22.768819 0, 0xFFFF, sum = 0
3034 22:59:22.772121 1, 0xFFFF, sum = 0
3035 22:59:22.772214 2, 0xFFFF, sum = 0
3036 22:59:22.775464 3, 0xFFFF, sum = 0
3037 22:59:22.778727 4, 0xFFFF, sum = 0
3038 22:59:22.778828 5, 0xFFFF, sum = 0
3039 22:59:22.782316 6, 0xFFFF, sum = 0
3040 22:59:22.782401 7, 0xFFFF, sum = 0
3041 22:59:22.785638 8, 0xFFFF, sum = 0
3042 22:59:22.785730 9, 0xFFFF, sum = 0
3043 22:59:22.789245 10, 0xFFFF, sum = 0
3044 22:59:22.789330 11, 0xFFFF, sum = 0
3045 22:59:22.792369 12, 0x0, sum = 1
3046 22:59:22.792453 13, 0x0, sum = 2
3047 22:59:22.795776 14, 0x0, sum = 3
3048 22:59:22.795892 15, 0x0, sum = 4
3049 22:59:22.798685 best_step = 13
3050 22:59:22.798787
3051 22:59:22.798881 ==
3052 22:59:22.801897 Dram Type= 6, Freq= 0, CH_0, rank 1
3053 22:59:22.805353 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3054 22:59:22.805472 ==
3055 22:59:22.805580 RX Vref Scan: 0
3056 22:59:22.805681
3057 22:59:22.808762 RX Vref 0 -> 0, step: 1
3058 22:59:22.808876
3059 22:59:22.811958 RX Delay -21 -> 252, step: 4
3060 22:59:22.815335 iDelay=195, Bit 0, Center 114 (51 ~ 178) 128
3061 22:59:22.821758 iDelay=195, Bit 1, Center 116 (47 ~ 186) 140
3062 22:59:22.825172 iDelay=195, Bit 2, Center 112 (47 ~ 178) 132
3063 22:59:22.828469 iDelay=195, Bit 3, Center 112 (47 ~ 178) 132
3064 22:59:22.832069 iDelay=195, Bit 4, Center 118 (51 ~ 186) 136
3065 22:59:22.835021 iDelay=195, Bit 5, Center 110 (43 ~ 178) 136
3066 22:59:22.841780 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3067 22:59:22.844980 iDelay=195, Bit 7, Center 122 (55 ~ 190) 136
3068 22:59:22.848396 iDelay=195, Bit 8, Center 96 (31 ~ 162) 132
3069 22:59:22.851536 iDelay=195, Bit 9, Center 92 (27 ~ 158) 132
3070 22:59:22.855094 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3071 22:59:22.861559 iDelay=195, Bit 11, Center 102 (35 ~ 170) 136
3072 22:59:22.865067 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3073 22:59:22.868338 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3074 22:59:22.871394 iDelay=195, Bit 14, Center 120 (55 ~ 186) 132
3075 22:59:22.878297 iDelay=195, Bit 15, Center 112 (47 ~ 178) 132
3076 22:59:22.878515 ==
3077 22:59:22.881522 Dram Type= 6, Freq= 0, CH_0, rank 1
3078 22:59:22.885023 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3079 22:59:22.885233 ==
3080 22:59:22.885365 DQS Delay:
3081 22:59:22.888313 DQS0 = 0, DQS1 = 0
3082 22:59:22.888493 DQM Delay:
3083 22:59:22.891427 DQM0 = 116, DQM1 = 106
3084 22:59:22.891527 DQ Delay:
3085 22:59:22.894955 DQ0 =114, DQ1 =116, DQ2 =112, DQ3 =112
3086 22:59:22.898333 DQ4 =118, DQ5 =110, DQ6 =126, DQ7 =122
3087 22:59:22.901714 DQ8 =96, DQ9 =92, DQ10 =110, DQ11 =102
3088 22:59:22.905013 DQ12 =112, DQ13 =110, DQ14 =120, DQ15 =112
3089 22:59:22.905097
3090 22:59:22.905169
3091 22:59:22.915203 [DQSOSCAuto] RK1, (LSB)MR18= 0xfdfa, (MSB)MR19= 0x303, tDQSOscB0 = 412 ps tDQSOscB1 = 411 ps
3092 22:59:22.917861 CH0 RK1: MR19=303, MR18=FDFA
3093 22:59:22.921348 CH0_RK1: MR19=0x303, MR18=0xFDFA, DQSOSC=411, MR23=63, INC=38, DEC=25
3094 22:59:22.924808 [RxdqsGatingPostProcess] freq 1200
3095 22:59:22.931357 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3096 22:59:22.934920 best DQS0 dly(2T, 0.5T) = (0, 11)
3097 22:59:22.937964 best DQS1 dly(2T, 0.5T) = (0, 12)
3098 22:59:22.941586 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3099 22:59:22.944821 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3100 22:59:22.947985 best DQS0 dly(2T, 0.5T) = (0, 11)
3101 22:59:22.951554 best DQS1 dly(2T, 0.5T) = (0, 11)
3102 22:59:22.955054 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3103 22:59:22.957940 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3104 22:59:22.961092 Pre-setting of DQS Precalculation
3105 22:59:22.964628 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3106 22:59:22.964702 ==
3107 22:59:22.967906 Dram Type= 6, Freq= 0, CH_1, rank 0
3108 22:59:22.971213 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3109 22:59:22.971318 ==
3110 22:59:22.978309 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3111 22:59:22.984378 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3112 22:59:22.992177 [CA 0] Center 38 (8~68) winsize 61
3113 22:59:22.995472 [CA 1] Center 37 (7~68) winsize 62
3114 22:59:22.998912 [CA 2] Center 35 (5~65) winsize 61
3115 22:59:23.001705 [CA 3] Center 34 (4~64) winsize 61
3116 22:59:23.005214 [CA 4] Center 34 (4~65) winsize 62
3117 22:59:23.008332 [CA 5] Center 34 (4~64) winsize 61
3118 22:59:23.008403
3119 22:59:23.011772 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3120 22:59:23.011841
3121 22:59:23.014936 [CATrainingPosCal] consider 1 rank data
3122 22:59:23.018394 u2DelayCellTimex100 = 270/100 ps
3123 22:59:23.022081 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3124 22:59:23.028479 CA1 delay=37 (7~68),Diff = 3 PI (14 cell)
3125 22:59:23.031681 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3126 22:59:23.034910 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
3127 22:59:23.038278 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3128 22:59:23.042209 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3129 22:59:23.042325
3130 22:59:23.045187 CA PerBit enable=1, Macro0, CA PI delay=34
3131 22:59:23.045282
3132 22:59:23.048353 [CBTSetCACLKResult] CA Dly = 34
3133 22:59:23.048460 CS Dly: 5 (0~36)
3134 22:59:23.051839 ==
3135 22:59:23.055047 Dram Type= 6, Freq= 0, CH_1, rank 1
3136 22:59:23.058545 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3137 22:59:23.058634 ==
3138 22:59:23.061720 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3139 22:59:23.068380 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3140 22:59:23.077799 [CA 0] Center 37 (7~68) winsize 62
3141 22:59:23.081432 [CA 1] Center 38 (8~68) winsize 61
3142 22:59:23.084763 [CA 2] Center 35 (5~65) winsize 61
3143 22:59:23.087583 [CA 3] Center 33 (3~64) winsize 62
3144 22:59:23.090953 [CA 4] Center 34 (4~64) winsize 61
3145 22:59:23.094366 [CA 5] Center 33 (3~63) winsize 61
3146 22:59:23.094502
3147 22:59:23.097797 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3148 22:59:23.097879
3149 22:59:23.101166 [CATrainingPosCal] consider 2 rank data
3150 22:59:23.103980 u2DelayCellTimex100 = 270/100 ps
3151 22:59:23.107336 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3152 22:59:23.114245 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3153 22:59:23.117683 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3154 22:59:23.121014 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3155 22:59:23.123968 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3156 22:59:23.127234 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3157 22:59:23.127365
3158 22:59:23.130509 CA PerBit enable=1, Macro0, CA PI delay=33
3159 22:59:23.130648
3160 22:59:23.133935 [CBTSetCACLKResult] CA Dly = 33
3161 22:59:23.137836 CS Dly: 6 (0~38)
3162 22:59:23.138015
3163 22:59:23.140616 ----->DramcWriteLeveling(PI) begin...
3164 22:59:23.140795 ==
3165 22:59:23.144134 Dram Type= 6, Freq= 0, CH_1, rank 0
3166 22:59:23.147172 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3167 22:59:23.147378 ==
3168 22:59:23.150989 Write leveling (Byte 0): 27 => 27
3169 22:59:23.154263 Write leveling (Byte 1): 27 => 27
3170 22:59:23.157272 DramcWriteLeveling(PI) end<-----
3171 22:59:23.157611
3172 22:59:23.157874 ==
3173 22:59:23.160886 Dram Type= 6, Freq= 0, CH_1, rank 0
3174 22:59:23.164086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3175 22:59:23.164518 ==
3176 22:59:23.167635 [Gating] SW mode calibration
3177 22:59:23.174121 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3178 22:59:23.180523 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3179 22:59:23.184342 0 15 0 | B1->B0 | 3232 3434 | 0 0 | (0 0) (0 0)
3180 22:59:23.187394 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3181 22:59:23.193813 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3182 22:59:23.197222 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3183 22:59:23.200826 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3184 22:59:23.207513 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3185 22:59:23.210859 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
3186 22:59:23.214306 0 15 28 | B1->B0 | 2b2b 2424 | 1 0 | (1 0) (0 0)
3187 22:59:23.220817 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3188 22:59:23.224425 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3189 22:59:23.227785 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3190 22:59:23.233594 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3191 22:59:23.237144 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3192 22:59:23.240289 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3193 22:59:23.247118 1 0 24 | B1->B0 | 2424 2929 | 0 0 | (0 0) (0 0)
3194 22:59:23.250321 1 0 28 | B1->B0 | 3939 4646 | 1 0 | (0 0) (0 0)
3195 22:59:23.253772 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3196 22:59:23.260253 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3197 22:59:23.263505 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3198 22:59:23.267279 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3199 22:59:23.270439 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3200 22:59:23.276961 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3201 22:59:23.280116 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3202 22:59:23.284004 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3203 22:59:23.289975 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3204 22:59:23.293558 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3205 22:59:23.296635 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3206 22:59:23.303549 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3207 22:59:23.306639 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3208 22:59:23.310114 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3209 22:59:23.316422 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3210 22:59:23.319775 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3211 22:59:23.323196 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3212 22:59:23.329903 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3213 22:59:23.332823 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3214 22:59:23.336275 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3215 22:59:23.342718 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3216 22:59:23.346164 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3217 22:59:23.349701 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3218 22:59:23.356090 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3219 22:59:23.359807 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3220 22:59:23.362990 Total UI for P1: 0, mck2ui 16
3221 22:59:23.366460 best dqsien dly found for B0: ( 1, 3, 26)
3222 22:59:23.369697 Total UI for P1: 0, mck2ui 16
3223 22:59:23.372852 best dqsien dly found for B1: ( 1, 3, 28)
3224 22:59:23.376690 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3225 22:59:23.379573 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3226 22:59:23.379652
3227 22:59:23.382748 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3228 22:59:23.386371 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3229 22:59:23.389697 [Gating] SW calibration Done
3230 22:59:23.389771 ==
3231 22:59:23.393124 Dram Type= 6, Freq= 0, CH_1, rank 0
3232 22:59:23.396334 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3233 22:59:23.396412 ==
3234 22:59:23.399333 RX Vref Scan: 0
3235 22:59:23.399405
3236 22:59:23.403495 RX Vref 0 -> 0, step: 1
3237 22:59:23.403924
3238 22:59:23.404357 RX Delay -40 -> 252, step: 8
3239 22:59:23.409778 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
3240 22:59:23.413159 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3241 22:59:23.416627 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3242 22:59:23.420100 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3243 22:59:23.423514 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3244 22:59:23.429719 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3245 22:59:23.433083 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3246 22:59:23.436373 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3247 22:59:23.439667 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3248 22:59:23.443172 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3249 22:59:23.449774 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3250 22:59:23.452971 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3251 22:59:23.456336 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3252 22:59:23.459676 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
3253 22:59:23.466115 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3254 22:59:23.469665 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3255 22:59:23.470090 ==
3256 22:59:23.472884 Dram Type= 6, Freq= 0, CH_1, rank 0
3257 22:59:23.476289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3258 22:59:23.476718 ==
3259 22:59:23.479070 DQS Delay:
3260 22:59:23.479171 DQS0 = 0, DQS1 = 0
3261 22:59:23.479255 DQM Delay:
3262 22:59:23.482631 DQM0 = 115, DQM1 = 113
3263 22:59:23.482713 DQ Delay:
3264 22:59:23.485680 DQ0 =123, DQ1 =111, DQ2 =103, DQ3 =115
3265 22:59:23.488853 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =111
3266 22:59:23.492494 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
3267 22:59:23.499155 DQ12 =123, DQ13 =123, DQ14 =119, DQ15 =119
3268 22:59:23.499236
3269 22:59:23.499323
3270 22:59:23.499384 ==
3271 22:59:23.502298 Dram Type= 6, Freq= 0, CH_1, rank 0
3272 22:59:23.505334 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3273 22:59:23.505439 ==
3274 22:59:23.505540
3275 22:59:23.505641
3276 22:59:23.508533 TX Vref Scan disable
3277 22:59:23.508610 == TX Byte 0 ==
3278 22:59:23.515469 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3279 22:59:23.518647 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3280 22:59:23.518734 == TX Byte 1 ==
3281 22:59:23.525415 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3282 22:59:23.528771 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3283 22:59:23.528848 ==
3284 22:59:23.531814 Dram Type= 6, Freq= 0, CH_1, rank 0
3285 22:59:23.535636 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3286 22:59:23.535714 ==
3287 22:59:23.547653 TX Vref=22, minBit 8, minWin=24, winSum=405
3288 22:59:23.551008 TX Vref=24, minBit 8, minWin=24, winSum=410
3289 22:59:23.554309 TX Vref=26, minBit 9, minWin=25, winSum=422
3290 22:59:23.557527 TX Vref=28, minBit 9, minWin=25, winSum=423
3291 22:59:23.561009 TX Vref=30, minBit 9, minWin=25, winSum=425
3292 22:59:23.567758 TX Vref=32, minBit 0, minWin=26, winSum=424
3293 22:59:23.570859 [TxChooseVref] Worse bit 0, Min win 26, Win sum 424, Final Vref 32
3294 22:59:23.570941
3295 22:59:23.574207 Final TX Range 1 Vref 32
3296 22:59:23.574281
3297 22:59:23.574344 ==
3298 22:59:23.577471 Dram Type= 6, Freq= 0, CH_1, rank 0
3299 22:59:23.580985 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3300 22:59:23.581060 ==
3301 22:59:23.584105
3302 22:59:23.584181
3303 22:59:23.584252 TX Vref Scan disable
3304 22:59:23.587090 == TX Byte 0 ==
3305 22:59:23.590555 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3306 22:59:23.597482 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3307 22:59:23.597574 == TX Byte 1 ==
3308 22:59:23.600456 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3309 22:59:23.607134 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3310 22:59:23.607311
3311 22:59:23.607416 [DATLAT]
3312 22:59:23.607483 Freq=1200, CH1 RK0
3313 22:59:23.607544
3314 22:59:23.610378 DATLAT Default: 0xd
3315 22:59:23.610461 0, 0xFFFF, sum = 0
3316 22:59:23.613866 1, 0xFFFF, sum = 0
3317 22:59:23.613948 2, 0xFFFF, sum = 0
3318 22:59:23.617156 3, 0xFFFF, sum = 0
3319 22:59:23.617234 4, 0xFFFF, sum = 0
3320 22:59:23.620820 5, 0xFFFF, sum = 0
3321 22:59:23.623920 6, 0xFFFF, sum = 0
3322 22:59:23.623998 7, 0xFFFF, sum = 0
3323 22:59:23.627496 8, 0xFFFF, sum = 0
3324 22:59:23.627588 9, 0xFFFF, sum = 0
3325 22:59:23.630725 10, 0xFFFF, sum = 0
3326 22:59:23.630826 11, 0xFFFF, sum = 0
3327 22:59:23.634104 12, 0x0, sum = 1
3328 22:59:23.634198 13, 0x0, sum = 2
3329 22:59:23.637045 14, 0x0, sum = 3
3330 22:59:23.637129 15, 0x0, sum = 4
3331 22:59:23.637194 best_step = 13
3332 22:59:23.640274
3333 22:59:23.640354 ==
3334 22:59:23.644036 Dram Type= 6, Freq= 0, CH_1, rank 0
3335 22:59:23.647196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3336 22:59:23.647269 ==
3337 22:59:23.647331 RX Vref Scan: 1
3338 22:59:23.647399
3339 22:59:23.650252 Set Vref Range= 32 -> 127
3340 22:59:23.650333
3341 22:59:23.653683 RX Vref 32 -> 127, step: 1
3342 22:59:23.653756
3343 22:59:23.657131 RX Delay -13 -> 252, step: 4
3344 22:59:23.657203
3345 22:59:23.660242 Set Vref, RX VrefLevel [Byte0]: 32
3346 22:59:23.663666 [Byte1]: 32
3347 22:59:23.663753
3348 22:59:23.667232 Set Vref, RX VrefLevel [Byte0]: 33
3349 22:59:23.670266 [Byte1]: 33
3350 22:59:23.673491
3351 22:59:23.673586 Set Vref, RX VrefLevel [Byte0]: 34
3352 22:59:23.677237 [Byte1]: 34
3353 22:59:23.681773
3354 22:59:23.681866 Set Vref, RX VrefLevel [Byte0]: 35
3355 22:59:23.685018 [Byte1]: 35
3356 22:59:23.689629
3357 22:59:23.689727 Set Vref, RX VrefLevel [Byte0]: 36
3358 22:59:23.692966 [Byte1]: 36
3359 22:59:23.697197
3360 22:59:23.697289 Set Vref, RX VrefLevel [Byte0]: 37
3361 22:59:23.700578 [Byte1]: 37
3362 22:59:23.705083
3363 22:59:23.705159 Set Vref, RX VrefLevel [Byte0]: 38
3364 22:59:23.708829 [Byte1]: 38
3365 22:59:23.713449
3366 22:59:23.713525 Set Vref, RX VrefLevel [Byte0]: 39
3367 22:59:23.716211 [Byte1]: 39
3368 22:59:23.720768
3369 22:59:23.720843 Set Vref, RX VrefLevel [Byte0]: 40
3370 22:59:23.724455 [Byte1]: 40
3371 22:59:23.728660
3372 22:59:23.728744 Set Vref, RX VrefLevel [Byte0]: 41
3373 22:59:23.731949 [Byte1]: 41
3374 22:59:23.737138
3375 22:59:23.737235 Set Vref, RX VrefLevel [Byte0]: 42
3376 22:59:23.739947 [Byte1]: 42
3377 22:59:23.744395
3378 22:59:23.744470 Set Vref, RX VrefLevel [Byte0]: 43
3379 22:59:23.750968 [Byte1]: 43
3380 22:59:23.751045
3381 22:59:23.754256 Set Vref, RX VrefLevel [Byte0]: 44
3382 22:59:23.757643 [Byte1]: 44
3383 22:59:23.757717
3384 22:59:23.760939 Set Vref, RX VrefLevel [Byte0]: 45
3385 22:59:23.764301 [Byte1]: 45
3386 22:59:23.768081
3387 22:59:23.768155 Set Vref, RX VrefLevel [Byte0]: 46
3388 22:59:23.771458 [Byte1]: 46
3389 22:59:23.775960
3390 22:59:23.776051 Set Vref, RX VrefLevel [Byte0]: 47
3391 22:59:23.779650 [Byte1]: 47
3392 22:59:23.784197
3393 22:59:23.784315 Set Vref, RX VrefLevel [Byte0]: 48
3394 22:59:23.787071 [Byte1]: 48
3395 22:59:23.791875
3396 22:59:23.791958 Set Vref, RX VrefLevel [Byte0]: 49
3397 22:59:23.795375 [Byte1]: 49
3398 22:59:23.799972
3399 22:59:23.800069 Set Vref, RX VrefLevel [Byte0]: 50
3400 22:59:23.803505 [Byte1]: 50
3401 22:59:23.807741
3402 22:59:23.807829 Set Vref, RX VrefLevel [Byte0]: 51
3403 22:59:23.810906 [Byte1]: 51
3404 22:59:23.815402
3405 22:59:23.815496 Set Vref, RX VrefLevel [Byte0]: 52
3406 22:59:23.818780 [Byte1]: 52
3407 22:59:23.823327
3408 22:59:23.823409 Set Vref, RX VrefLevel [Byte0]: 53
3409 22:59:23.826792 [Byte1]: 53
3410 22:59:23.831268
3411 22:59:23.831356 Set Vref, RX VrefLevel [Byte0]: 54
3412 22:59:23.834678 [Byte1]: 54
3413 22:59:23.839414
3414 22:59:23.839490 Set Vref, RX VrefLevel [Byte0]: 55
3415 22:59:23.842928 [Byte1]: 55
3416 22:59:23.846935
3417 22:59:23.847006 Set Vref, RX VrefLevel [Byte0]: 56
3418 22:59:23.850654 [Byte1]: 56
3419 22:59:23.854930
3420 22:59:23.854999 Set Vref, RX VrefLevel [Byte0]: 57
3421 22:59:23.858423 [Byte1]: 57
3422 22:59:23.862966
3423 22:59:23.863041 Set Vref, RX VrefLevel [Byte0]: 58
3424 22:59:23.866278 [Byte1]: 58
3425 22:59:23.870694
3426 22:59:23.870770 Set Vref, RX VrefLevel [Byte0]: 59
3427 22:59:23.873857 [Byte1]: 59
3428 22:59:23.878895
3429 22:59:23.878966 Set Vref, RX VrefLevel [Byte0]: 60
3430 22:59:23.882159 [Byte1]: 60
3431 22:59:23.886576
3432 22:59:23.886648 Set Vref, RX VrefLevel [Byte0]: 61
3433 22:59:23.889861 [Byte1]: 61
3434 22:59:23.894107
3435 22:59:23.894204 Set Vref, RX VrefLevel [Byte0]: 62
3436 22:59:23.897619 [Byte1]: 62
3437 22:59:23.902216
3438 22:59:23.902287 Set Vref, RX VrefLevel [Byte0]: 63
3439 22:59:23.905647 [Byte1]: 63
3440 22:59:23.910055
3441 22:59:23.910128 Set Vref, RX VrefLevel [Byte0]: 64
3442 22:59:23.913219 [Byte1]: 64
3443 22:59:23.917877
3444 22:59:23.917955 Set Vref, RX VrefLevel [Byte0]: 65
3445 22:59:23.921555 [Byte1]: 65
3446 22:59:23.925733
3447 22:59:23.925805 Final RX Vref Byte 0 = 52 to rank0
3448 22:59:23.929339 Final RX Vref Byte 1 = 51 to rank0
3449 22:59:23.932758 Final RX Vref Byte 0 = 52 to rank1
3450 22:59:23.935987 Final RX Vref Byte 1 = 51 to rank1==
3451 22:59:23.939139 Dram Type= 6, Freq= 0, CH_1, rank 0
3452 22:59:23.945865 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3453 22:59:23.945946 ==
3454 22:59:23.946014 DQS Delay:
3455 22:59:23.946077 DQS0 = 0, DQS1 = 0
3456 22:59:23.949346 DQM Delay:
3457 22:59:23.949420 DQM0 = 114, DQM1 = 112
3458 22:59:23.952526 DQ Delay:
3459 22:59:23.955948 DQ0 =120, DQ1 =110, DQ2 =106, DQ3 =114
3460 22:59:23.959356 DQ4 =110, DQ5 =122, DQ6 =126, DQ7 =110
3461 22:59:23.962789 DQ8 =98, DQ9 =102, DQ10 =114, DQ11 =108
3462 22:59:23.965625 DQ12 =120, DQ13 =120, DQ14 =120, DQ15 =120
3463 22:59:23.965697
3464 22:59:23.965758
3465 22:59:23.975603 [DQSOSCAuto] RK0, (LSB)MR18= 0xf501, (MSB)MR19= 0x304, tDQSOscB0 = 409 ps tDQSOscB1 = 414 ps
3466 22:59:23.975684 CH1 RK0: MR19=304, MR18=F501
3467 22:59:23.982377 CH1_RK0: MR19=0x304, MR18=0xF501, DQSOSC=409, MR23=63, INC=39, DEC=26
3468 22:59:23.982454
3469 22:59:23.985431 ----->DramcWriteLeveling(PI) begin...
3470 22:59:23.985507 ==
3471 22:59:23.988845 Dram Type= 6, Freq= 0, CH_1, rank 1
3472 22:59:23.995530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3473 22:59:23.995610 ==
3474 22:59:23.998651 Write leveling (Byte 0): 24 => 24
3475 22:59:23.998729 Write leveling (Byte 1): 26 => 26
3476 22:59:24.002114 DramcWriteLeveling(PI) end<-----
3477 22:59:24.002188
3478 22:59:24.002250 ==
3479 22:59:24.005393 Dram Type= 6, Freq= 0, CH_1, rank 1
3480 22:59:24.012166 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3481 22:59:24.012247 ==
3482 22:59:24.015706 [Gating] SW mode calibration
3483 22:59:24.021835 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3484 22:59:24.025143 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3485 22:59:24.031815 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3486 22:59:24.035123 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3487 22:59:24.038754 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3488 22:59:24.045358 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3489 22:59:24.048557 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3490 22:59:24.051635 0 15 20 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
3491 22:59:24.058393 0 15 24 | B1->B0 | 3434 2323 | 1 0 | (1 0) (1 0)
3492 22:59:24.061787 0 15 28 | B1->B0 | 2f2f 2323 | 0 0 | (1 0) (0 0)
3493 22:59:24.065095 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3494 22:59:24.071858 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3495 22:59:24.075122 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3496 22:59:24.078382 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3497 22:59:24.084768 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3498 22:59:24.088007 1 0 20 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (1 1)
3499 22:59:24.091716 1 0 24 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
3500 22:59:24.098051 1 0 28 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
3501 22:59:24.101375 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3502 22:59:24.105160 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3503 22:59:24.111349 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3504 22:59:24.114594 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3505 22:59:24.117950 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3506 22:59:24.124712 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3507 22:59:24.127969 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3508 22:59:24.131222 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3509 22:59:24.137946 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3510 22:59:24.141055 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3511 22:59:24.144284 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3512 22:59:24.151025 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3513 22:59:24.154615 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3514 22:59:24.157576 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3515 22:59:24.160856 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3516 22:59:24.167372 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3517 22:59:24.170877 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3518 22:59:24.174243 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3519 22:59:24.180824 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3520 22:59:24.184155 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3521 22:59:24.187476 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3522 22:59:24.193780 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3523 22:59:24.197152 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3524 22:59:24.203960 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3525 22:59:24.204053 Total UI for P1: 0, mck2ui 16
3526 22:59:24.206763 best dqsien dly found for B0: ( 1, 3, 24)
3527 22:59:24.210207 Total UI for P1: 0, mck2ui 16
3528 22:59:24.214007 best dqsien dly found for B1: ( 1, 3, 26)
3529 22:59:24.220156 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3530 22:59:24.223605 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3531 22:59:24.223687
3532 22:59:24.226485 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3533 22:59:24.230350 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3534 22:59:24.233698 [Gating] SW calibration Done
3535 22:59:24.233781 ==
3536 22:59:24.236833 Dram Type= 6, Freq= 0, CH_1, rank 1
3537 22:59:24.239656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3538 22:59:24.239739 ==
3539 22:59:24.242915 RX Vref Scan: 0
3540 22:59:24.243031
3541 22:59:24.243117 RX Vref 0 -> 0, step: 1
3542 22:59:24.243217
3543 22:59:24.246454 RX Delay -40 -> 252, step: 8
3544 22:59:24.250048 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3545 22:59:24.256210 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3546 22:59:24.259531 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3547 22:59:24.262743 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3548 22:59:24.266253 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3549 22:59:24.269760 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3550 22:59:24.276296 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3551 22:59:24.279178 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3552 22:59:24.282492 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3553 22:59:24.285815 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3554 22:59:24.289222 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3555 22:59:24.295914 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3556 22:59:24.299854 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3557 22:59:24.302625 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3558 22:59:24.306039 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3559 22:59:24.312981 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3560 22:59:24.313196 ==
3561 22:59:24.315976 Dram Type= 6, Freq= 0, CH_1, rank 1
3562 22:59:24.319254 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3563 22:59:24.319445 ==
3564 22:59:24.319577 DQS Delay:
3565 22:59:24.322913 DQS0 = 0, DQS1 = 0
3566 22:59:24.323172 DQM Delay:
3567 22:59:24.326221 DQM0 = 115, DQM1 = 111
3568 22:59:24.326494 DQ Delay:
3569 22:59:24.329628 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =111
3570 22:59:24.333285 DQ4 =115, DQ5 =127, DQ6 =119, DQ7 =115
3571 22:59:24.335779 DQ8 =99, DQ9 =99, DQ10 =111, DQ11 =107
3572 22:59:24.339510 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3573 22:59:24.339907
3574 22:59:24.340205
3575 22:59:24.340434 ==
3576 22:59:24.342725 Dram Type= 6, Freq= 0, CH_1, rank 1
3577 22:59:24.349340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3578 22:59:24.349802 ==
3579 22:59:24.350141
3580 22:59:24.350450
3581 22:59:24.352615 TX Vref Scan disable
3582 22:59:24.353035 == TX Byte 0 ==
3583 22:59:24.355945 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3584 22:59:24.362565 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3585 22:59:24.362986 == TX Byte 1 ==
3586 22:59:24.365578 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3587 22:59:24.372202 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3588 22:59:24.372631 ==
3589 22:59:24.375887 Dram Type= 6, Freq= 0, CH_1, rank 1
3590 22:59:24.378919 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3591 22:59:24.379345 ==
3592 22:59:24.390962 TX Vref=22, minBit 3, minWin=24, winSum=414
3593 22:59:24.394145 TX Vref=24, minBit 9, minWin=25, winSum=420
3594 22:59:24.397598 TX Vref=26, minBit 9, minWin=25, winSum=422
3595 22:59:24.400943 TX Vref=28, minBit 9, minWin=25, winSum=426
3596 22:59:24.404095 TX Vref=30, minBit 9, minWin=25, winSum=427
3597 22:59:24.410445 TX Vref=32, minBit 9, minWin=25, winSum=426
3598 22:59:24.413617 [TxChooseVref] Worse bit 9, Min win 25, Win sum 427, Final Vref 30
3599 22:59:24.413712
3600 22:59:24.416893 Final TX Range 1 Vref 30
3601 22:59:24.416987
3602 22:59:24.417061 ==
3603 22:59:24.420113 Dram Type= 6, Freq= 0, CH_1, rank 1
3604 22:59:24.423552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3605 22:59:24.427307 ==
3606 22:59:24.427496
3607 22:59:24.427593
3608 22:59:24.427684 TX Vref Scan disable
3609 22:59:24.430555 == TX Byte 0 ==
3610 22:59:24.433767 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3611 22:59:24.440113 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3612 22:59:24.440325 == TX Byte 1 ==
3613 22:59:24.443827 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3614 22:59:24.449743 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3615 22:59:24.449827
3616 22:59:24.449892 [DATLAT]
3617 22:59:24.449956 Freq=1200, CH1 RK1
3618 22:59:24.450015
3619 22:59:24.453336 DATLAT Default: 0xd
3620 22:59:24.456428 0, 0xFFFF, sum = 0
3621 22:59:24.456511 1, 0xFFFF, sum = 0
3622 22:59:24.459631 2, 0xFFFF, sum = 0
3623 22:59:24.459714 3, 0xFFFF, sum = 0
3624 22:59:24.462997 4, 0xFFFF, sum = 0
3625 22:59:24.463080 5, 0xFFFF, sum = 0
3626 22:59:24.466219 6, 0xFFFF, sum = 0
3627 22:59:24.466302 7, 0xFFFF, sum = 0
3628 22:59:24.469466 8, 0xFFFF, sum = 0
3629 22:59:24.469550 9, 0xFFFF, sum = 0
3630 22:59:24.472831 10, 0xFFFF, sum = 0
3631 22:59:24.472914 11, 0xFFFF, sum = 0
3632 22:59:24.476489 12, 0x0, sum = 1
3633 22:59:24.476573 13, 0x0, sum = 2
3634 22:59:24.479423 14, 0x0, sum = 3
3635 22:59:24.479506 15, 0x0, sum = 4
3636 22:59:24.482745 best_step = 13
3637 22:59:24.482827
3638 22:59:24.482892 ==
3639 22:59:24.486277 Dram Type= 6, Freq= 0, CH_1, rank 1
3640 22:59:24.489340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3641 22:59:24.489423 ==
3642 22:59:24.492966 RX Vref Scan: 0
3643 22:59:24.493048
3644 22:59:24.493113 RX Vref 0 -> 0, step: 1
3645 22:59:24.493172
3646 22:59:24.496198 RX Delay -13 -> 252, step: 4
3647 22:59:24.502970 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3648 22:59:24.506549 iDelay=195, Bit 1, Center 112 (43 ~ 182) 140
3649 22:59:24.509659 iDelay=195, Bit 2, Center 106 (39 ~ 174) 136
3650 22:59:24.512864 iDelay=195, Bit 3, Center 114 (47 ~ 182) 136
3651 22:59:24.515790 iDelay=195, Bit 4, Center 116 (47 ~ 186) 140
3652 22:59:24.522921 iDelay=195, Bit 5, Center 124 (55 ~ 194) 140
3653 22:59:24.526321 iDelay=195, Bit 6, Center 122 (55 ~ 190) 136
3654 22:59:24.529049 iDelay=195, Bit 7, Center 114 (47 ~ 182) 136
3655 22:59:24.532206 iDelay=195, Bit 8, Center 100 (39 ~ 162) 124
3656 22:59:24.535559 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3657 22:59:24.542367 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3658 22:59:24.545644 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3659 22:59:24.549009 iDelay=195, Bit 12, Center 120 (59 ~ 182) 124
3660 22:59:24.552305 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3661 22:59:24.559025 iDelay=195, Bit 14, Center 116 (55 ~ 178) 124
3662 22:59:24.562048 iDelay=195, Bit 15, Center 122 (59 ~ 186) 128
3663 22:59:24.562354 ==
3664 22:59:24.565737 Dram Type= 6, Freq= 0, CH_1, rank 1
3665 22:59:24.568927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3666 22:59:24.569361 ==
3667 22:59:24.572069 DQS Delay:
3668 22:59:24.572507 DQS0 = 0, DQS1 = 0
3669 22:59:24.572957 DQM Delay:
3670 22:59:24.575475 DQM0 = 115, DQM1 = 112
3671 22:59:24.575909 DQ Delay:
3672 22:59:24.578534 DQ0 =118, DQ1 =112, DQ2 =106, DQ3 =114
3673 22:59:24.581642 DQ4 =116, DQ5 =124, DQ6 =122, DQ7 =114
3674 22:59:24.588636 DQ8 =100, DQ9 =102, DQ10 =114, DQ11 =106
3675 22:59:24.592123 DQ12 =120, DQ13 =118, DQ14 =116, DQ15 =122
3676 22:59:24.592596
3677 22:59:24.592928
3678 22:59:24.598388 [DQSOSCAuto] RK1, (LSB)MR18= 0xf80a, (MSB)MR19= 0x304, tDQSOscB0 = 406 ps tDQSOscB1 = 413 ps
3679 22:59:24.601957 CH1 RK1: MR19=304, MR18=F80A
3680 22:59:24.608718 CH1_RK1: MR19=0x304, MR18=0xF80A, DQSOSC=406, MR23=63, INC=39, DEC=26
3681 22:59:24.612096 [RxdqsGatingPostProcess] freq 1200
3682 22:59:24.618518 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3683 22:59:24.619046 best DQS0 dly(2T, 0.5T) = (0, 11)
3684 22:59:24.621722 best DQS1 dly(2T, 0.5T) = (0, 11)
3685 22:59:24.625013 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3686 22:59:24.628203 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3687 22:59:24.631402 best DQS0 dly(2T, 0.5T) = (0, 11)
3688 22:59:24.634838 best DQS1 dly(2T, 0.5T) = (0, 11)
3689 22:59:24.638461 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3690 22:59:24.641339 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3691 22:59:24.644549 Pre-setting of DQS Precalculation
3692 22:59:24.651360 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3693 22:59:24.657846 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3694 22:59:24.664568 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3695 22:59:24.665139
3696 22:59:24.665532
3697 22:59:24.667987 [Calibration Summary] 2400 Mbps
3698 22:59:24.668643 CH 0, Rank 0
3699 22:59:24.671058 SW Impedance : PASS
3700 22:59:24.674390 DUTY Scan : NO K
3701 22:59:24.674836 ZQ Calibration : PASS
3702 22:59:24.677218 Jitter Meter : NO K
3703 22:59:24.680568 CBT Training : PASS
3704 22:59:24.680990 Write leveling : PASS
3705 22:59:24.683759 RX DQS gating : PASS
3706 22:59:24.686977 RX DQ/DQS(RDDQC) : PASS
3707 22:59:24.687403 TX DQ/DQS : PASS
3708 22:59:24.690546 RX DATLAT : PASS
3709 22:59:24.694112 RX DQ/DQS(Engine): PASS
3710 22:59:24.694537 TX OE : NO K
3711 22:59:24.697451 All Pass.
3712 22:59:24.697871
3713 22:59:24.698209 CH 0, Rank 1
3714 22:59:24.700388 SW Impedance : PASS
3715 22:59:24.700823 DUTY Scan : NO K
3716 22:59:24.703618 ZQ Calibration : PASS
3717 22:59:24.707059 Jitter Meter : NO K
3718 22:59:24.707587 CBT Training : PASS
3719 22:59:24.710429 Write leveling : PASS
3720 22:59:24.713495 RX DQS gating : PASS
3721 22:59:24.713920 RX DQ/DQS(RDDQC) : PASS
3722 22:59:24.716781 TX DQ/DQS : PASS
3723 22:59:24.720069 RX DATLAT : PASS
3724 22:59:24.720518 RX DQ/DQS(Engine): PASS
3725 22:59:24.723661 TX OE : NO K
3726 22:59:24.724233 All Pass.
3727 22:59:24.724589
3728 22:59:24.726772 CH 1, Rank 0
3729 22:59:24.727199 SW Impedance : PASS
3730 22:59:24.730226 DUTY Scan : NO K
3731 22:59:24.730655 ZQ Calibration : PASS
3732 22:59:24.733489 Jitter Meter : NO K
3733 22:59:24.737033 CBT Training : PASS
3734 22:59:24.737461 Write leveling : PASS
3735 22:59:24.740369 RX DQS gating : PASS
3736 22:59:24.743302 RX DQ/DQS(RDDQC) : PASS
3737 22:59:24.743837 TX DQ/DQS : PASS
3738 22:59:24.746673 RX DATLAT : PASS
3739 22:59:24.750166 RX DQ/DQS(Engine): PASS
3740 22:59:24.750697 TX OE : NO K
3741 22:59:24.753226 All Pass.
3742 22:59:24.753759
3743 22:59:24.754102 CH 1, Rank 1
3744 22:59:24.756357 SW Impedance : PASS
3745 22:59:24.756788 DUTY Scan : NO K
3746 22:59:24.760291 ZQ Calibration : PASS
3747 22:59:24.763647 Jitter Meter : NO K
3748 22:59:24.764222 CBT Training : PASS
3749 22:59:24.766592 Write leveling : PASS
3750 22:59:24.770324 RX DQS gating : PASS
3751 22:59:24.770865 RX DQ/DQS(RDDQC) : PASS
3752 22:59:24.772844 TX DQ/DQS : PASS
3753 22:59:24.776984 RX DATLAT : PASS
3754 22:59:24.777520 RX DQ/DQS(Engine): PASS
3755 22:59:24.779543 TX OE : NO K
3756 22:59:24.780111 All Pass.
3757 22:59:24.780469
3758 22:59:24.783154 DramC Write-DBI off
3759 22:59:24.786075 PER_BANK_REFRESH: Hybrid Mode
3760 22:59:24.786511 TX_TRACKING: ON
3761 22:59:24.795903 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3762 22:59:24.799361 [FAST_K] Save calibration result to emmc
3763 22:59:24.802859 dramc_set_vcore_voltage set vcore to 650000
3764 22:59:24.806088 Read voltage for 600, 5
3765 22:59:24.806716 Vio18 = 0
3766 22:59:24.807245 Vcore = 650000
3767 22:59:24.809091 Vdram = 0
3768 22:59:24.809747 Vddq = 0
3769 22:59:24.810236 Vmddr = 0
3770 22:59:24.815695 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3771 22:59:24.818665 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3772 22:59:24.822410 MEM_TYPE=3, freq_sel=19
3773 22:59:24.825576 sv_algorithm_assistance_LP4_1600
3774 22:59:24.828865 ============ PULL DRAM RESETB DOWN ============
3775 22:59:24.832280 ========== PULL DRAM RESETB DOWN end =========
3776 22:59:24.838815 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3777 22:59:24.842389 ===================================
3778 22:59:24.845573 LPDDR4 DRAM CONFIGURATION
3779 22:59:24.845696 ===================================
3780 22:59:24.849029 EX_ROW_EN[0] = 0x0
3781 22:59:24.851662 EX_ROW_EN[1] = 0x0
3782 22:59:24.851844 LP4Y_EN = 0x0
3783 22:59:24.855887 WORK_FSP = 0x0
3784 22:59:24.856068 WL = 0x2
3785 22:59:24.858534 RL = 0x2
3786 22:59:24.858748 BL = 0x2
3787 22:59:24.861806 RPST = 0x0
3788 22:59:24.861964 RD_PRE = 0x0
3789 22:59:24.865002 WR_PRE = 0x1
3790 22:59:24.865206 WR_PST = 0x0
3791 22:59:24.868380 DBI_WR = 0x0
3792 22:59:24.868626 DBI_RD = 0x0
3793 22:59:24.871927 OTF = 0x1
3794 22:59:24.875286 ===================================
3795 22:59:24.878177 ===================================
3796 22:59:24.878694 ANA top config
3797 22:59:24.881589 ===================================
3798 22:59:24.884856 DLL_ASYNC_EN = 0
3799 22:59:24.888517 ALL_SLAVE_EN = 1
3800 22:59:24.891773 NEW_RANK_MODE = 1
3801 22:59:24.895114 DLL_IDLE_MODE = 1
3802 22:59:24.895641 LP45_APHY_COMB_EN = 1
3803 22:59:24.898393 TX_ODT_DIS = 1
3804 22:59:24.901675 NEW_8X_MODE = 1
3805 22:59:24.905084 ===================================
3806 22:59:24.908005 ===================================
3807 22:59:24.911529 data_rate = 1200
3808 22:59:24.914539 CKR = 1
3809 22:59:24.917760 DQ_P2S_RATIO = 8
3810 22:59:24.921319 ===================================
3811 22:59:24.921833 CA_P2S_RATIO = 8
3812 22:59:24.924371 DQ_CA_OPEN = 0
3813 22:59:24.927761 DQ_SEMI_OPEN = 0
3814 22:59:24.931198 CA_SEMI_OPEN = 0
3815 22:59:24.934126 CA_FULL_RATE = 0
3816 22:59:24.937438 DQ_CKDIV4_EN = 1
3817 22:59:24.938080 CA_CKDIV4_EN = 1
3818 22:59:24.941257 CA_PREDIV_EN = 0
3819 22:59:24.943980 PH8_DLY = 0
3820 22:59:24.947379 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3821 22:59:24.950616 DQ_AAMCK_DIV = 4
3822 22:59:24.954149 CA_AAMCK_DIV = 4
3823 22:59:24.954674 CA_ADMCK_DIV = 4
3824 22:59:24.957402 DQ_TRACK_CA_EN = 0
3825 22:59:24.960848 CA_PICK = 600
3826 22:59:24.964357 CA_MCKIO = 600
3827 22:59:24.967313 MCKIO_SEMI = 0
3828 22:59:24.970656 PLL_FREQ = 2288
3829 22:59:24.973994 DQ_UI_PI_RATIO = 32
3830 22:59:24.974406 CA_UI_PI_RATIO = 0
3831 22:59:24.976520 ===================================
3832 22:59:24.979952 ===================================
3833 22:59:24.983045 memory_type:LPDDR4
3834 22:59:24.986422 GP_NUM : 10
3835 22:59:24.986497 SRAM_EN : 1
3836 22:59:24.990115 MD32_EN : 0
3837 22:59:24.993222 ===================================
3838 22:59:24.996431 [ANA_INIT] >>>>>>>>>>>>>>
3839 22:59:24.999851 <<<<<< [CONFIGURE PHASE]: ANA_TX
3840 22:59:25.003226 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3841 22:59:25.006064 ===================================
3842 22:59:25.009444 data_rate = 1200,PCW = 0X5800
3843 22:59:25.013455 ===================================
3844 22:59:25.016155 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3845 22:59:25.019250 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3846 22:59:25.026191 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3847 22:59:25.029154 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3848 22:59:25.032314 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3849 22:59:25.035887 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3850 22:59:25.039021 [ANA_INIT] flow start
3851 22:59:25.042571 [ANA_INIT] PLL >>>>>>>>
3852 22:59:25.042854 [ANA_INIT] PLL <<<<<<<<
3853 22:59:25.046289 [ANA_INIT] MIDPI >>>>>>>>
3854 22:59:25.049486 [ANA_INIT] MIDPI <<<<<<<<
3855 22:59:25.052765 [ANA_INIT] DLL >>>>>>>>
3856 22:59:25.053214 [ANA_INIT] flow end
3857 22:59:25.055802 ============ LP4 DIFF to SE enter ============
3858 22:59:25.061995 ============ LP4 DIFF to SE exit ============
3859 22:59:25.062084 [ANA_INIT] <<<<<<<<<<<<<
3860 22:59:25.065324 [Flow] Enable top DCM control >>>>>
3861 22:59:25.068532 [Flow] Enable top DCM control <<<<<
3862 22:59:25.071753 Enable DLL master slave shuffle
3863 22:59:25.078456 ==============================================================
3864 22:59:25.081843 Gating Mode config
3865 22:59:25.085211 ==============================================================
3866 22:59:25.088349 Config description:
3867 22:59:25.098528 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3868 22:59:25.105295 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3869 22:59:25.108187 SELPH_MODE 0: By rank 1: By Phase
3870 22:59:25.115055 ==============================================================
3871 22:59:25.118139 GAT_TRACK_EN = 1
3872 22:59:25.121536 RX_GATING_MODE = 2
3873 22:59:25.124762 RX_GATING_TRACK_MODE = 2
3874 22:59:25.124856 SELPH_MODE = 1
3875 22:59:25.128044 PICG_EARLY_EN = 1
3876 22:59:25.131469 VALID_LAT_VALUE = 1
3877 22:59:25.137999 ==============================================================
3878 22:59:25.141358 Enter into Gating configuration >>>>
3879 22:59:25.144771 Exit from Gating configuration <<<<
3880 22:59:25.147833 Enter into DVFS_PRE_config >>>>>
3881 22:59:25.157789 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3882 22:59:25.161082 Exit from DVFS_PRE_config <<<<<
3883 22:59:25.164334 Enter into PICG configuration >>>>
3884 22:59:25.167893 Exit from PICG configuration <<<<
3885 22:59:25.171307 [RX_INPUT] configuration >>>>>
3886 22:59:25.174606 [RX_INPUT] configuration <<<<<
3887 22:59:25.177883 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3888 22:59:25.184250 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3889 22:59:25.190919 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3890 22:59:25.197625 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3891 22:59:25.204335 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3892 22:59:25.210626 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3893 22:59:25.213872 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3894 22:59:25.217649 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3895 22:59:25.220242 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3896 22:59:25.227001 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3897 22:59:25.230483 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3898 22:59:25.233850 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3899 22:59:25.237000 ===================================
3900 22:59:25.240408 LPDDR4 DRAM CONFIGURATION
3901 22:59:25.243852 ===================================
3902 22:59:25.243999 EX_ROW_EN[0] = 0x0
3903 22:59:25.246714 EX_ROW_EN[1] = 0x0
3904 22:59:25.250529 LP4Y_EN = 0x0
3905 22:59:25.250953 WORK_FSP = 0x0
3906 22:59:25.253634 WL = 0x2
3907 22:59:25.254059 RL = 0x2
3908 22:59:25.257261 BL = 0x2
3909 22:59:25.257683 RPST = 0x0
3910 22:59:25.260621 RD_PRE = 0x0
3911 22:59:25.261043 WR_PRE = 0x1
3912 22:59:25.263618 WR_PST = 0x0
3913 22:59:25.264063 DBI_WR = 0x0
3914 22:59:25.267090 DBI_RD = 0x0
3915 22:59:25.267532 OTF = 0x1
3916 22:59:25.270629 ===================================
3917 22:59:25.274021 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3918 22:59:25.280245 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3919 22:59:25.283641 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3920 22:59:25.287055 ===================================
3921 22:59:25.289844 LPDDR4 DRAM CONFIGURATION
3922 22:59:25.293157 ===================================
3923 22:59:25.293582 EX_ROW_EN[0] = 0x10
3924 22:59:25.297002 EX_ROW_EN[1] = 0x0
3925 22:59:25.300158 LP4Y_EN = 0x0
3926 22:59:25.300731 WORK_FSP = 0x0
3927 22:59:25.302999 WL = 0x2
3928 22:59:25.303423 RL = 0x2
3929 22:59:25.306411 BL = 0x2
3930 22:59:25.306834 RPST = 0x0
3931 22:59:25.310001 RD_PRE = 0x0
3932 22:59:25.310422 WR_PRE = 0x1
3933 22:59:25.313339 WR_PST = 0x0
3934 22:59:25.313761 DBI_WR = 0x0
3935 22:59:25.316131 DBI_RD = 0x0
3936 22:59:25.316555 OTF = 0x1
3937 22:59:25.319406 ===================================
3938 22:59:25.325946 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3939 22:59:25.330393 nWR fixed to 30
3940 22:59:25.333737 [ModeRegInit_LP4] CH0 RK0
3941 22:59:25.334164 [ModeRegInit_LP4] CH0 RK1
3942 22:59:25.336956 [ModeRegInit_LP4] CH1 RK0
3943 22:59:25.340795 [ModeRegInit_LP4] CH1 RK1
3944 22:59:25.341218 match AC timing 17
3945 22:59:25.347138 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3946 22:59:25.350240 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3947 22:59:25.353721 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3948 22:59:25.359993 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3949 22:59:25.363600 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3950 22:59:25.364195 ==
3951 22:59:25.366803 Dram Type= 6, Freq= 0, CH_0, rank 0
3952 22:59:25.370501 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3953 22:59:25.370928 ==
3954 22:59:25.376850 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3955 22:59:25.383171 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3956 22:59:25.386453 [CA 0] Center 36 (6~67) winsize 62
3957 22:59:25.389826 [CA 1] Center 36 (5~67) winsize 63
3958 22:59:25.393207 [CA 2] Center 34 (4~65) winsize 62
3959 22:59:25.396508 [CA 3] Center 34 (4~65) winsize 62
3960 22:59:25.399474 [CA 4] Center 33 (3~64) winsize 62
3961 22:59:25.402970 [CA 5] Center 33 (3~64) winsize 62
3962 22:59:25.403074
3963 22:59:25.406448 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3964 22:59:25.406620
3965 22:59:25.409353 [CATrainingPosCal] consider 1 rank data
3966 22:59:25.412602 u2DelayCellTimex100 = 270/100 ps
3967 22:59:25.415921 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3968 22:59:25.419465 CA1 delay=36 (5~67),Diff = 3 PI (28 cell)
3969 22:59:25.422636 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3970 22:59:25.429296 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3971 22:59:25.432552 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3972 22:59:25.435869 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3973 22:59:25.436110
3974 22:59:25.439119 CA PerBit enable=1, Macro0, CA PI delay=33
3975 22:59:25.439297
3976 22:59:25.442500 [CBTSetCACLKResult] CA Dly = 33
3977 22:59:25.442679 CS Dly: 6 (0~37)
3978 22:59:25.442818 ==
3979 22:59:25.445422 Dram Type= 6, Freq= 0, CH_0, rank 1
3980 22:59:25.452270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3981 22:59:25.452450 ==
3982 22:59:25.455763 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3983 22:59:25.461807 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3984 22:59:25.465837 [CA 0] Center 36 (6~67) winsize 62
3985 22:59:25.469313 [CA 1] Center 36 (6~67) winsize 62
3986 22:59:25.472491 [CA 2] Center 34 (4~65) winsize 62
3987 22:59:25.475614 [CA 3] Center 34 (4~65) winsize 62
3988 22:59:25.478561 [CA 4] Center 34 (3~65) winsize 63
3989 22:59:25.482087 [CA 5] Center 33 (3~64) winsize 62
3990 22:59:25.482173
3991 22:59:25.485511 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3992 22:59:25.485596
3993 22:59:25.488911 [CATrainingPosCal] consider 2 rank data
3994 22:59:25.491923 u2DelayCellTimex100 = 270/100 ps
3995 22:59:25.495319 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3996 22:59:25.502032 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3997 22:59:25.505423 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3998 22:59:25.508478 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3999 22:59:25.511989 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4000 22:59:25.515338 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4001 22:59:25.515421
4002 22:59:25.518272 CA PerBit enable=1, Macro0, CA PI delay=33
4003 22:59:25.518355
4004 22:59:25.521477 [CBTSetCACLKResult] CA Dly = 33
4005 22:59:25.524953 CS Dly: 6 (0~37)
4006 22:59:25.525036
4007 22:59:25.528340 ----->DramcWriteLeveling(PI) begin...
4008 22:59:25.528450 ==
4009 22:59:25.531824 Dram Type= 6, Freq= 0, CH_0, rank 0
4010 22:59:25.535184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4011 22:59:25.535268 ==
4012 22:59:25.538332 Write leveling (Byte 0): 34 => 34
4013 22:59:25.541940 Write leveling (Byte 1): 30 => 30
4014 22:59:25.544938 DramcWriteLeveling(PI) end<-----
4015 22:59:25.545099
4016 22:59:25.545184 ==
4017 22:59:25.548363 Dram Type= 6, Freq= 0, CH_0, rank 0
4018 22:59:25.551573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4019 22:59:25.551699 ==
4020 22:59:25.555212 [Gating] SW mode calibration
4021 22:59:25.561811 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4022 22:59:25.568062 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4023 22:59:25.571436 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4024 22:59:25.574531 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4025 22:59:25.581086 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4026 22:59:25.584660 0 9 12 | B1->B0 | 3434 3232 | 0 0 | (0 0) (0 0)
4027 22:59:25.587750 0 9 16 | B1->B0 | 2b2b 2424 | 0 0 | (0 0) (0 0)
4028 22:59:25.594493 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4029 22:59:25.597748 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4030 22:59:25.601243 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4031 22:59:25.607730 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4032 22:59:25.611133 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4033 22:59:25.614507 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4034 22:59:25.620775 0 10 12 | B1->B0 | 2424 3030 | 0 0 | (0 0) (0 0)
4035 22:59:25.623969 0 10 16 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
4036 22:59:25.627689 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4037 22:59:25.633838 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4038 22:59:25.637031 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4039 22:59:25.643787 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4040 22:59:25.647503 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4041 22:59:25.650475 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4042 22:59:25.653574 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4043 22:59:25.660282 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4044 22:59:25.663583 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4045 22:59:25.666740 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4046 22:59:25.673492 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4047 22:59:25.676783 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4048 22:59:25.680003 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4049 22:59:25.686754 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4050 22:59:25.689726 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4051 22:59:25.693247 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4052 22:59:25.699795 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4053 22:59:25.703115 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4054 22:59:25.706456 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4055 22:59:25.713104 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4056 22:59:25.716165 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4057 22:59:25.719593 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4058 22:59:25.726539 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4059 22:59:25.729942 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4060 22:59:25.732554 Total UI for P1: 0, mck2ui 16
4061 22:59:25.735849 best dqsien dly found for B0: ( 0, 13, 14)
4062 22:59:25.739381 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4063 22:59:25.742580 Total UI for P1: 0, mck2ui 16
4064 22:59:25.745746 best dqsien dly found for B1: ( 0, 13, 18)
4065 22:59:25.752644 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4066 22:59:25.756420 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4067 22:59:25.756848
4068 22:59:25.759120 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4069 22:59:25.762576 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4070 22:59:25.765817 [Gating] SW calibration Done
4071 22:59:25.766238 ==
4072 22:59:25.769343 Dram Type= 6, Freq= 0, CH_0, rank 0
4073 22:59:25.772378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4074 22:59:25.772802 ==
4075 22:59:25.775835 RX Vref Scan: 0
4076 22:59:25.776284
4077 22:59:25.776619 RX Vref 0 -> 0, step: 1
4078 22:59:25.776933
4079 22:59:25.779317 RX Delay -230 -> 252, step: 16
4080 22:59:25.782365 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4081 22:59:25.788943 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4082 22:59:25.792199 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4083 22:59:25.795320 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4084 22:59:25.798816 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4085 22:59:25.805218 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4086 22:59:25.808802 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4087 22:59:25.811782 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4088 22:59:25.815374 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4089 22:59:25.821791 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4090 22:59:25.824908 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4091 22:59:25.828228 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4092 22:59:25.831413 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4093 22:59:25.838332 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4094 22:59:25.841089 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4095 22:59:25.844435 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4096 22:59:25.844859 ==
4097 22:59:25.847653 Dram Type= 6, Freq= 0, CH_0, rank 0
4098 22:59:25.851143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4099 22:59:25.854503 ==
4100 22:59:25.854924 DQS Delay:
4101 22:59:25.855261 DQS0 = 0, DQS1 = 0
4102 22:59:25.857839 DQM Delay:
4103 22:59:25.858265 DQM0 = 41, DQM1 = 34
4104 22:59:25.861105 DQ Delay:
4105 22:59:25.864575 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =33
4106 22:59:25.865000 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4107 22:59:25.867714 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =33
4108 22:59:25.874069 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4109 22:59:25.874497
4110 22:59:25.874829
4111 22:59:25.875140 ==
4112 22:59:25.877495 Dram Type= 6, Freq= 0, CH_0, rank 0
4113 22:59:25.880794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4114 22:59:25.881222 ==
4115 22:59:25.881560
4116 22:59:25.881872
4117 22:59:25.884165 TX Vref Scan disable
4118 22:59:25.884590 == TX Byte 0 ==
4119 22:59:25.890768 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4120 22:59:25.894249 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4121 22:59:25.894689 == TX Byte 1 ==
4122 22:59:25.900636 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4123 22:59:25.904173 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4124 22:59:25.904595 ==
4125 22:59:25.907258 Dram Type= 6, Freq= 0, CH_0, rank 0
4126 22:59:25.910705 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4127 22:59:25.911131 ==
4128 22:59:25.911464
4129 22:59:25.913999
4130 22:59:25.914560 TX Vref Scan disable
4131 22:59:25.917325 == TX Byte 0 ==
4132 22:59:25.920801 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4133 22:59:25.927510 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4134 22:59:25.928155 == TX Byte 1 ==
4135 22:59:25.930778 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4136 22:59:25.937405 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4137 22:59:25.938023
4138 22:59:25.938436 [DATLAT]
4139 22:59:25.939040 Freq=600, CH0 RK0
4140 22:59:25.939446
4141 22:59:25.940443 DATLAT Default: 0x9
4142 22:59:25.944257 0, 0xFFFF, sum = 0
4143 22:59:25.944689 1, 0xFFFF, sum = 0
4144 22:59:25.947651 2, 0xFFFF, sum = 0
4145 22:59:25.948132 3, 0xFFFF, sum = 0
4146 22:59:25.950727 4, 0xFFFF, sum = 0
4147 22:59:25.951159 5, 0xFFFF, sum = 0
4148 22:59:25.953487 6, 0xFFFF, sum = 0
4149 22:59:25.953956 7, 0xFFFF, sum = 0
4150 22:59:25.956880 8, 0x0, sum = 1
4151 22:59:25.957330 9, 0x0, sum = 2
4152 22:59:25.960014 10, 0x0, sum = 3
4153 22:59:25.960497 11, 0x0, sum = 4
4154 22:59:25.960841 best_step = 9
4155 22:59:25.961171
4156 22:59:25.963964 ==
4157 22:59:25.966799 Dram Type= 6, Freq= 0, CH_0, rank 0
4158 22:59:25.970289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4159 22:59:25.970822 ==
4160 22:59:25.971160 RX Vref Scan: 1
4161 22:59:25.971474
4162 22:59:25.973696 RX Vref 0 -> 0, step: 1
4163 22:59:25.974231
4164 22:59:25.976959 RX Delay -195 -> 252, step: 8
4165 22:59:25.977400
4166 22:59:25.980267 Set Vref, RX VrefLevel [Byte0]: 53
4167 22:59:25.983091 [Byte1]: 58
4168 22:59:25.983597
4169 22:59:25.986651 Final RX Vref Byte 0 = 53 to rank0
4170 22:59:25.989855 Final RX Vref Byte 1 = 58 to rank0
4171 22:59:25.993571 Final RX Vref Byte 0 = 53 to rank1
4172 22:59:25.996760 Final RX Vref Byte 1 = 58 to rank1==
4173 22:59:25.999986 Dram Type= 6, Freq= 0, CH_0, rank 0
4174 22:59:26.006635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4175 22:59:26.007069 ==
4176 22:59:26.007410 DQS Delay:
4177 22:59:26.007727 DQS0 = 0, DQS1 = 0
4178 22:59:26.009986 DQM Delay:
4179 22:59:26.010576 DQM0 = 41, DQM1 = 33
4180 22:59:26.013093 DQ Delay:
4181 22:59:26.016784 DQ0 =44, DQ1 =44, DQ2 =36, DQ3 =36
4182 22:59:26.017375 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =44
4183 22:59:26.019884 DQ8 =24, DQ9 =16, DQ10 =36, DQ11 =28
4184 22:59:26.023003 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4185 22:59:26.026167
4186 22:59:26.026688
4187 22:59:26.033151 [DQSOSCAuto] RK0, (LSB)MR18= 0x4d44, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 395 ps
4188 22:59:26.036154 CH0 RK0: MR19=808, MR18=4D44
4189 22:59:26.042810 CH0_RK0: MR19=0x808, MR18=0x4D44, DQSOSC=395, MR23=63, INC=168, DEC=112
4190 22:59:26.043274
4191 22:59:26.046425 ----->DramcWriteLeveling(PI) begin...
4192 22:59:26.046969 ==
4193 22:59:26.049587 Dram Type= 6, Freq= 0, CH_0, rank 1
4194 22:59:26.052803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4195 22:59:26.053272 ==
4196 22:59:26.055585 Write leveling (Byte 0): 34 => 34
4197 22:59:26.058867 Write leveling (Byte 1): 30 => 30
4198 22:59:26.062580 DramcWriteLeveling(PI) end<-----
4199 22:59:26.063145
4200 22:59:26.063604 ==
4201 22:59:26.065466 Dram Type= 6, Freq= 0, CH_0, rank 1
4202 22:59:26.069146 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4203 22:59:26.072296 ==
4204 22:59:26.072795 [Gating] SW mode calibration
4205 22:59:26.081907 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4206 22:59:26.085543 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4207 22:59:26.088812 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4208 22:59:26.095468 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4209 22:59:26.098848 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4210 22:59:26.101975 0 9 12 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 0)
4211 22:59:26.108470 0 9 16 | B1->B0 | 2e2e 2525 | 1 0 | (1 0) (0 0)
4212 22:59:26.112119 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4213 22:59:26.115030 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4214 22:59:26.121904 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4215 22:59:26.125056 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4216 22:59:26.127819 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4217 22:59:26.134741 0 10 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (1 1)
4218 22:59:26.138121 0 10 12 | B1->B0 | 2828 3333 | 0 0 | (1 1) (0 0)
4219 22:59:26.141152 0 10 16 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
4220 22:59:26.147786 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4221 22:59:26.151085 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4222 22:59:26.154228 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4223 22:59:26.161332 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4224 22:59:26.164597 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4225 22:59:26.167954 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4226 22:59:26.174529 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4227 22:59:26.177342 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4228 22:59:26.180741 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4229 22:59:26.187200 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4230 22:59:26.191133 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4231 22:59:26.193972 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4232 22:59:26.200542 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4233 22:59:26.204057 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4234 22:59:26.207360 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4235 22:59:26.214056 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4236 22:59:26.217241 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4237 22:59:26.220139 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4238 22:59:26.227008 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4239 22:59:26.230061 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4240 22:59:26.233845 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4241 22:59:26.240311 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4242 22:59:26.243669 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4243 22:59:26.246435 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4244 22:59:26.249779 Total UI for P1: 0, mck2ui 16
4245 22:59:26.253523 best dqsien dly found for B0: ( 0, 13, 12)
4246 22:59:26.260135 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4247 22:59:26.263300 Total UI for P1: 0, mck2ui 16
4248 22:59:26.266407 best dqsien dly found for B1: ( 0, 13, 16)
4249 22:59:26.269576 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4250 22:59:26.272439 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4251 22:59:26.272521
4252 22:59:26.275681 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4253 22:59:26.278895 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4254 22:59:26.282417 [Gating] SW calibration Done
4255 22:59:26.282512 ==
4256 22:59:26.285991 Dram Type= 6, Freq= 0, CH_0, rank 1
4257 22:59:26.289237 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4258 22:59:26.292286 ==
4259 22:59:26.292451 RX Vref Scan: 0
4260 22:59:26.292555
4261 22:59:26.295472 RX Vref 0 -> 0, step: 1
4262 22:59:26.295632
4263 22:59:26.298799 RX Delay -230 -> 252, step: 16
4264 22:59:26.302056 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4265 22:59:26.305353 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4266 22:59:26.308853 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4267 22:59:26.315417 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4268 22:59:26.318810 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4269 22:59:26.322158 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4270 22:59:26.325502 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4271 22:59:26.329011 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4272 22:59:26.334916 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4273 22:59:26.338572 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4274 22:59:26.341453 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4275 22:59:26.344496 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4276 22:59:26.351130 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4277 22:59:26.354680 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4278 22:59:26.357766 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4279 22:59:26.361249 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4280 22:59:26.364466 ==
4281 22:59:26.367957 Dram Type= 6, Freq= 0, CH_0, rank 1
4282 22:59:26.371315 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4283 22:59:26.371387 ==
4284 22:59:26.371447 DQS Delay:
4285 22:59:26.374495 DQS0 = 0, DQS1 = 0
4286 22:59:26.374583 DQM Delay:
4287 22:59:26.377803 DQM0 = 46, DQM1 = 34
4288 22:59:26.377890 DQ Delay:
4289 22:59:26.381104 DQ0 =41, DQ1 =49, DQ2 =33, DQ3 =49
4290 22:59:26.384486 DQ4 =49, DQ5 =33, DQ6 =57, DQ7 =57
4291 22:59:26.387685 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =33
4292 22:59:26.391130 DQ12 =41, DQ13 =33, DQ14 =57, DQ15 =33
4293 22:59:26.391241
4294 22:59:26.391329
4295 22:59:26.391410 ==
4296 22:59:26.394769 Dram Type= 6, Freq= 0, CH_0, rank 1
4297 22:59:26.397971 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4298 22:59:26.398151 ==
4299 22:59:26.398272
4300 22:59:26.398382
4301 22:59:26.401210 TX Vref Scan disable
4302 22:59:26.404653 == TX Byte 0 ==
4303 22:59:26.407571 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4304 22:59:26.411007 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4305 22:59:26.414085 == TX Byte 1 ==
4306 22:59:26.417500 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4307 22:59:26.420278 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4308 22:59:26.420360 ==
4309 22:59:26.423980 Dram Type= 6, Freq= 0, CH_0, rank 1
4310 22:59:26.430246 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4311 22:59:26.430342 ==
4312 22:59:26.430416
4313 22:59:26.430486
4314 22:59:26.430552 TX Vref Scan disable
4315 22:59:26.435125 == TX Byte 0 ==
4316 22:59:26.438451 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4317 22:59:26.445004 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4318 22:59:26.445126 == TX Byte 1 ==
4319 22:59:26.448015 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4320 22:59:26.454956 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4321 22:59:26.455110
4322 22:59:26.455229 [DATLAT]
4323 22:59:26.455340 Freq=600, CH0 RK1
4324 22:59:26.455448
4325 22:59:26.457969 DATLAT Default: 0x9
4326 22:59:26.461596 0, 0xFFFF, sum = 0
4327 22:59:26.461771 1, 0xFFFF, sum = 0
4328 22:59:26.464843 2, 0xFFFF, sum = 0
4329 22:59:26.465049 3, 0xFFFF, sum = 0
4330 22:59:26.467974 4, 0xFFFF, sum = 0
4331 22:59:26.468194 5, 0xFFFF, sum = 0
4332 22:59:26.471178 6, 0xFFFF, sum = 0
4333 22:59:26.471424 7, 0xFFFF, sum = 0
4334 22:59:26.474578 8, 0x0, sum = 1
4335 22:59:26.474880 9, 0x0, sum = 2
4336 22:59:26.477808 10, 0x0, sum = 3
4337 22:59:26.478110 11, 0x0, sum = 4
4338 22:59:26.478396 best_step = 9
4339 22:59:26.478620
4340 22:59:26.481164 ==
4341 22:59:26.484573 Dram Type= 6, Freq= 0, CH_0, rank 1
4342 22:59:26.488553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4343 22:59:26.488977 ==
4344 22:59:26.489308 RX Vref Scan: 0
4345 22:59:26.489619
4346 22:59:26.491198 RX Vref 0 -> 0, step: 1
4347 22:59:26.491618
4348 22:59:26.494943 RX Delay -195 -> 252, step: 8
4349 22:59:26.501535 iDelay=205, Bit 0, Center 40 (-107 ~ 188) 296
4350 22:59:26.504690 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4351 22:59:26.507738 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4352 22:59:26.511204 iDelay=205, Bit 3, Center 40 (-107 ~ 188) 296
4353 22:59:26.517748 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4354 22:59:26.520626 iDelay=205, Bit 5, Center 32 (-115 ~ 180) 296
4355 22:59:26.524321 iDelay=205, Bit 6, Center 48 (-99 ~ 196) 296
4356 22:59:26.527545 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4357 22:59:26.530924 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4358 22:59:26.537236 iDelay=205, Bit 9, Center 16 (-139 ~ 172) 312
4359 22:59:26.540445 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4360 22:59:26.543383 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4361 22:59:26.546754 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4362 22:59:26.553340 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4363 22:59:26.556681 iDelay=205, Bit 14, Center 48 (-107 ~ 204) 312
4364 22:59:26.559719 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4365 22:59:26.559799 ==
4366 22:59:26.563276 Dram Type= 6, Freq= 0, CH_0, rank 1
4367 22:59:26.569493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4368 22:59:26.569573 ==
4369 22:59:26.569636 DQS Delay:
4370 22:59:26.573202 DQS0 = 0, DQS1 = 0
4371 22:59:26.573282 DQM Delay:
4372 22:59:26.573345 DQM0 = 41, DQM1 = 33
4373 22:59:26.576359 DQ Delay:
4374 22:59:26.579926 DQ0 =40, DQ1 =44, DQ2 =36, DQ3 =40
4375 22:59:26.583092 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4376 22:59:26.586311 DQ8 =24, DQ9 =16, DQ10 =36, DQ11 =24
4377 22:59:26.589645 DQ12 =40, DQ13 =40, DQ14 =48, DQ15 =40
4378 22:59:26.589725
4379 22:59:26.589788
4380 22:59:26.596464 [DQSOSCAuto] RK1, (LSB)MR18= 0x3e3a, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 398 ps
4381 22:59:26.599814 CH0 RK1: MR19=808, MR18=3E3A
4382 22:59:26.606191 CH0_RK1: MR19=0x808, MR18=0x3E3A, DQSOSC=398, MR23=63, INC=165, DEC=110
4383 22:59:26.609466 [RxdqsGatingPostProcess] freq 600
4384 22:59:26.612921 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4385 22:59:26.616274 Pre-setting of DQS Precalculation
4386 22:59:26.622989 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4387 22:59:26.623174 ==
4388 22:59:26.626277 Dram Type= 6, Freq= 0, CH_1, rank 0
4389 22:59:26.629360 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4390 22:59:26.629557 ==
4391 22:59:26.635632 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4392 22:59:26.642825 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4393 22:59:26.645689 [CA 0] Center 36 (6~66) winsize 61
4394 22:59:26.649257 [CA 1] Center 36 (6~66) winsize 61
4395 22:59:26.652050 [CA 2] Center 34 (4~65) winsize 62
4396 22:59:26.655504 [CA 3] Center 34 (4~65) winsize 62
4397 22:59:26.658827 [CA 4] Center 34 (4~65) winsize 62
4398 22:59:26.662190 [CA 5] Center 34 (4~65) winsize 62
4399 22:59:26.662665
4400 22:59:26.666025 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4401 22:59:26.666504
4402 22:59:26.668902 [CATrainingPosCal] consider 1 rank data
4403 22:59:26.672026 u2DelayCellTimex100 = 270/100 ps
4404 22:59:26.675705 CA0 delay=36 (6~66),Diff = 2 PI (19 cell)
4405 22:59:26.678692 CA1 delay=36 (6~66),Diff = 2 PI (19 cell)
4406 22:59:26.682199 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4407 22:59:26.685299 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4408 22:59:26.688729 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4409 22:59:26.694806 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4410 22:59:26.695218
4411 22:59:26.698082 CA PerBit enable=1, Macro0, CA PI delay=34
4412 22:59:26.698497
4413 22:59:26.701490 [CBTSetCACLKResult] CA Dly = 34
4414 22:59:26.701910 CS Dly: 4 (0~35)
4415 22:59:26.702246 ==
4416 22:59:26.705143 Dram Type= 6, Freq= 0, CH_1, rank 1
4417 22:59:26.711611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4418 22:59:26.712066 ==
4419 22:59:26.715138 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4420 22:59:26.721331 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4421 22:59:26.724687 [CA 0] Center 36 (6~66) winsize 61
4422 22:59:26.728071 [CA 1] Center 36 (6~66) winsize 61
4423 22:59:26.731356 [CA 2] Center 34 (4~65) winsize 62
4424 22:59:26.734653 [CA 3] Center 34 (4~65) winsize 62
4425 22:59:26.737765 [CA 4] Center 34 (4~65) winsize 62
4426 22:59:26.741044 [CA 5] Center 34 (4~65) winsize 62
4427 22:59:26.741654
4428 22:59:26.744697 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4429 22:59:26.745118
4430 22:59:26.748166 [CATrainingPosCal] consider 2 rank data
4431 22:59:26.751249 u2DelayCellTimex100 = 270/100 ps
4432 22:59:26.754604 CA0 delay=36 (6~66),Diff = 2 PI (19 cell)
4433 22:59:26.761196 CA1 delay=36 (6~66),Diff = 2 PI (19 cell)
4434 22:59:26.764102 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4435 22:59:26.767804 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4436 22:59:26.770652 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4437 22:59:26.774289 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4438 22:59:26.774753
4439 22:59:26.777587 CA PerBit enable=1, Macro0, CA PI delay=34
4440 22:59:26.778010
4441 22:59:26.780679 [CBTSetCACLKResult] CA Dly = 34
4442 22:59:26.784364 CS Dly: 4 (0~36)
4443 22:59:26.784927
4444 22:59:26.787505 ----->DramcWriteLeveling(PI) begin...
4445 22:59:26.787934 ==
4446 22:59:26.790726 Dram Type= 6, Freq= 0, CH_1, rank 0
4447 22:59:26.793929 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4448 22:59:26.794474 ==
4449 22:59:26.797481 Write leveling (Byte 0): 29 => 29
4450 22:59:26.800512 Write leveling (Byte 1): 31 => 31
4451 22:59:26.803894 DramcWriteLeveling(PI) end<-----
4452 22:59:26.804344
4453 22:59:26.804674 ==
4454 22:59:26.807199 Dram Type= 6, Freq= 0, CH_1, rank 0
4455 22:59:26.810538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4456 22:59:26.811002 ==
4457 22:59:26.813428 [Gating] SW mode calibration
4458 22:59:26.820136 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4459 22:59:26.826981 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4460 22:59:26.830702 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4461 22:59:26.833942 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4462 22:59:26.840187 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4463 22:59:26.843357 0 9 12 | B1->B0 | 2f2f 2f2f | 1 1 | (1 1) (1 0)
4464 22:59:26.846726 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4465 22:59:26.853389 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4466 22:59:26.856186 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4467 22:59:26.859583 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4468 22:59:26.866322 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4469 22:59:26.869679 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4470 22:59:26.873137 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4471 22:59:26.879256 0 10 12 | B1->B0 | 3131 3939 | 0 0 | (0 0) (0 0)
4472 22:59:26.882616 0 10 16 | B1->B0 | 4040 4646 | 1 0 | (0 0) (0 0)
4473 22:59:26.885829 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4474 22:59:26.892570 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4475 22:59:26.895942 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4476 22:59:26.899163 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4477 22:59:26.906195 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4478 22:59:26.909304 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4479 22:59:26.912198 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4480 22:59:26.919073 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4481 22:59:26.922556 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4482 22:59:26.925491 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4483 22:59:26.932162 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4484 22:59:26.935514 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4485 22:59:26.939155 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4486 22:59:26.945371 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4487 22:59:26.948836 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4488 22:59:26.952348 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4489 22:59:26.958547 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4490 22:59:26.962296 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4491 22:59:26.965575 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4492 22:59:26.971813 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4493 22:59:26.975229 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4494 22:59:26.978696 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4495 22:59:26.984687 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4496 22:59:26.987801 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4497 22:59:26.991274 Total UI for P1: 0, mck2ui 16
4498 22:59:26.994434 best dqsien dly found for B0: ( 0, 13, 14)
4499 22:59:26.997947 Total UI for P1: 0, mck2ui 16
4500 22:59:27.001176 best dqsien dly found for B1: ( 0, 13, 12)
4501 22:59:27.004149 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4502 22:59:27.007504 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4503 22:59:27.007934
4504 22:59:27.011010 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4505 22:59:27.017895 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4506 22:59:27.018432 [Gating] SW calibration Done
4507 22:59:27.018780 ==
4508 22:59:27.021245 Dram Type= 6, Freq= 0, CH_1, rank 0
4509 22:59:27.027978 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4510 22:59:27.028557 ==
4511 22:59:27.028906 RX Vref Scan: 0
4512 22:59:27.029226
4513 22:59:27.031553 RX Vref 0 -> 0, step: 1
4514 22:59:27.032141
4515 22:59:27.034341 RX Delay -230 -> 252, step: 16
4516 22:59:27.037247 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4517 22:59:27.040587 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4518 22:59:27.047056 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4519 22:59:27.050329 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4520 22:59:27.054067 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4521 22:59:27.057499 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4522 22:59:27.060354 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4523 22:59:27.066914 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4524 22:59:27.070263 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4525 22:59:27.073593 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4526 22:59:27.077140 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4527 22:59:27.083204 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4528 22:59:27.086439 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4529 22:59:27.089407 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4530 22:59:27.095948 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4531 22:59:27.099746 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4532 22:59:27.099885 ==
4533 22:59:27.102783 Dram Type= 6, Freq= 0, CH_1, rank 0
4534 22:59:27.105805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4535 22:59:27.105898 ==
4536 22:59:27.109465 DQS Delay:
4537 22:59:27.109539 DQS0 = 0, DQS1 = 0
4538 22:59:27.109602 DQM Delay:
4539 22:59:27.112594 DQM0 = 43, DQM1 = 38
4540 22:59:27.112663 DQ Delay:
4541 22:59:27.116547 DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =41
4542 22:59:27.119540 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4543 22:59:27.122480 DQ8 =17, DQ9 =25, DQ10 =41, DQ11 =33
4544 22:59:27.125842 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =41
4545 22:59:27.125915
4546 22:59:27.125976
4547 22:59:27.126035 ==
4548 22:59:27.129131 Dram Type= 6, Freq= 0, CH_1, rank 0
4549 22:59:27.135802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4550 22:59:27.135902 ==
4551 22:59:27.135992
4552 22:59:27.136120
4553 22:59:27.136206 TX Vref Scan disable
4554 22:59:27.139533 == TX Byte 0 ==
4555 22:59:27.142690 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4556 22:59:27.149580 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4557 22:59:27.149683 == TX Byte 1 ==
4558 22:59:27.152189 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4559 22:59:27.159273 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4560 22:59:27.159348 ==
4561 22:59:27.162450 Dram Type= 6, Freq= 0, CH_1, rank 0
4562 22:59:27.165906 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4563 22:59:27.166004 ==
4564 22:59:27.166096
4565 22:59:27.166184
4566 22:59:27.169097 TX Vref Scan disable
4567 22:59:27.172414 == TX Byte 0 ==
4568 22:59:27.175754 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4569 22:59:27.179021 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4570 22:59:27.182433 == TX Byte 1 ==
4571 22:59:27.185692 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4572 22:59:27.189075 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4573 22:59:27.189152
4574 22:59:27.189214 [DATLAT]
4575 22:59:27.191897 Freq=600, CH1 RK0
4576 22:59:27.191969
4577 22:59:27.195681 DATLAT Default: 0x9
4578 22:59:27.195756 0, 0xFFFF, sum = 0
4579 22:59:27.198770 1, 0xFFFF, sum = 0
4580 22:59:27.198865 2, 0xFFFF, sum = 0
4581 22:59:27.201708 3, 0xFFFF, sum = 0
4582 22:59:27.201808 4, 0xFFFF, sum = 0
4583 22:59:27.205304 5, 0xFFFF, sum = 0
4584 22:59:27.205394 6, 0xFFFF, sum = 0
4585 22:59:27.208240 7, 0xFFFF, sum = 0
4586 22:59:27.208328 8, 0x0, sum = 1
4587 22:59:27.211900 9, 0x0, sum = 2
4588 22:59:27.211987 10, 0x0, sum = 3
4589 22:59:27.214878 11, 0x0, sum = 4
4590 22:59:27.214965 best_step = 9
4591 22:59:27.215051
4592 22:59:27.215131 ==
4593 22:59:27.218225 Dram Type= 6, Freq= 0, CH_1, rank 0
4594 22:59:27.221627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4595 22:59:27.224866 ==
4596 22:59:27.224952 RX Vref Scan: 1
4597 22:59:27.225039
4598 22:59:27.228533 RX Vref 0 -> 0, step: 1
4599 22:59:27.228619
4600 22:59:27.231451 RX Delay -195 -> 252, step: 8
4601 22:59:27.231537
4602 22:59:27.234866 Set Vref, RX VrefLevel [Byte0]: 52
4603 22:59:27.237749 [Byte1]: 51
4604 22:59:27.237837
4605 22:59:27.240972 Final RX Vref Byte 0 = 52 to rank0
4606 22:59:27.244353 Final RX Vref Byte 1 = 51 to rank0
4607 22:59:27.247931 Final RX Vref Byte 0 = 52 to rank1
4608 22:59:27.251138 Final RX Vref Byte 1 = 51 to rank1==
4609 22:59:27.254454 Dram Type= 6, Freq= 0, CH_1, rank 0
4610 22:59:27.257902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4611 22:59:27.257989 ==
4612 22:59:27.261275 DQS Delay:
4613 22:59:27.261361 DQS0 = 0, DQS1 = 0
4614 22:59:27.261446 DQM Delay:
4615 22:59:27.264355 DQM0 = 37, DQM1 = 33
4616 22:59:27.264440 DQ Delay:
4617 22:59:27.267726 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =36
4618 22:59:27.270991 DQ4 =32, DQ5 =44, DQ6 =48, DQ7 =32
4619 22:59:27.274480 DQ8 =16, DQ9 =20, DQ10 =32, DQ11 =28
4620 22:59:27.277806 DQ12 =44, DQ13 =44, DQ14 =40, DQ15 =40
4621 22:59:27.277892
4622 22:59:27.277977
4623 22:59:27.287311 [DQSOSCAuto] RK0, (LSB)MR18= 0x2d46, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 401 ps
4624 22:59:27.290891 CH1 RK0: MR19=808, MR18=2D46
4625 22:59:27.294212 CH1_RK0: MR19=0x808, MR18=0x2D46, DQSOSC=396, MR23=63, INC=167, DEC=111
4626 22:59:27.297054
4627 22:59:27.300389 ----->DramcWriteLeveling(PI) begin...
4628 22:59:27.300465 ==
4629 22:59:27.303852 Dram Type= 6, Freq= 0, CH_1, rank 1
4630 22:59:27.307008 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4631 22:59:27.307105 ==
4632 22:59:27.310503 Write leveling (Byte 0): 29 => 29
4633 22:59:27.313692 Write leveling (Byte 1): 29 => 29
4634 22:59:27.316860 DramcWriteLeveling(PI) end<-----
4635 22:59:27.316948
4636 22:59:27.317022 ==
4637 22:59:27.320433 Dram Type= 6, Freq= 0, CH_1, rank 1
4638 22:59:27.323393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4639 22:59:27.323491 ==
4640 22:59:27.326668 [Gating] SW mode calibration
4641 22:59:27.333534 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4642 22:59:27.340010 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4643 22:59:27.343490 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4644 22:59:27.346413 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4645 22:59:27.353078 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4646 22:59:27.356606 0 9 12 | B1->B0 | 3030 2f2f | 1 1 | (1 1) (1 0)
4647 22:59:27.359816 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4648 22:59:27.366416 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4649 22:59:27.369642 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4650 22:59:27.373081 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4651 22:59:27.379927 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4652 22:59:27.382682 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4653 22:59:27.385966 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4654 22:59:27.393093 0 10 12 | B1->B0 | 3333 3c3c | 0 0 | (0 0) (0 0)
4655 22:59:27.396023 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4656 22:59:27.399500 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4657 22:59:27.406087 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4658 22:59:27.409193 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4659 22:59:27.412582 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4660 22:59:27.419037 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4661 22:59:27.422538 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4662 22:59:27.425647 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4663 22:59:27.432188 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4664 22:59:27.435708 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4665 22:59:27.438913 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4666 22:59:27.445611 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4667 22:59:27.448835 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4668 22:59:27.452172 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4669 22:59:27.458880 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4670 22:59:27.461672 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4671 22:59:27.465008 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4672 22:59:27.472300 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4673 22:59:27.474958 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4674 22:59:27.478318 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4675 22:59:27.484803 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4676 22:59:27.488340 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4677 22:59:27.491462 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4678 22:59:27.498195 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4679 22:59:27.498274 Total UI for P1: 0, mck2ui 16
4680 22:59:27.504861 best dqsien dly found for B0: ( 0, 13, 10)
4681 22:59:27.508239 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4682 22:59:27.511585 Total UI for P1: 0, mck2ui 16
4683 22:59:27.514543 best dqsien dly found for B1: ( 0, 13, 12)
4684 22:59:27.517982 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4685 22:59:27.521633 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4686 22:59:27.521702
4687 22:59:27.524293 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4688 22:59:27.527907 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4689 22:59:27.531051 [Gating] SW calibration Done
4690 22:59:27.531125 ==
4691 22:59:27.534362 Dram Type= 6, Freq= 0, CH_1, rank 1
4692 22:59:27.540808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4693 22:59:27.540899 ==
4694 22:59:27.540966 RX Vref Scan: 0
4695 22:59:27.541037
4696 22:59:27.544172 RX Vref 0 -> 0, step: 1
4697 22:59:27.544254
4698 22:59:27.547716 RX Delay -230 -> 252, step: 16
4699 22:59:27.550690 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4700 22:59:27.554143 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4701 22:59:27.560988 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4702 22:59:27.564222 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4703 22:59:27.566919 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4704 22:59:27.570305 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4705 22:59:27.573771 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4706 22:59:27.580297 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4707 22:59:27.583549 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4708 22:59:27.586990 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4709 22:59:27.589851 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4710 22:59:27.596852 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4711 22:59:27.599999 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4712 22:59:27.603312 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4713 22:59:27.606657 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4714 22:59:27.612847 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4715 22:59:27.612930 ==
4716 22:59:27.616203 Dram Type= 6, Freq= 0, CH_1, rank 1
4717 22:59:27.619482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4718 22:59:27.619594 ==
4719 22:59:27.619694 DQS Delay:
4720 22:59:27.622759 DQS0 = 0, DQS1 = 0
4721 22:59:27.622839 DQM Delay:
4722 22:59:27.626682 DQM0 = 42, DQM1 = 39
4723 22:59:27.626753 DQ Delay:
4724 22:59:27.629988 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =41
4725 22:59:27.632977 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4726 22:59:27.636495 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4727 22:59:27.639622 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =49
4728 22:59:27.639713
4729 22:59:27.639778
4730 22:59:27.639847 ==
4731 22:59:27.642714 Dram Type= 6, Freq= 0, CH_1, rank 1
4732 22:59:27.646210 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4733 22:59:27.649332 ==
4734 22:59:27.649411
4735 22:59:27.649476
4736 22:59:27.649547 TX Vref Scan disable
4737 22:59:27.652737 == TX Byte 0 ==
4738 22:59:27.655971 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4739 22:59:27.659589 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4740 22:59:27.662816 == TX Byte 1 ==
4741 22:59:27.666181 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4742 22:59:27.672345 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4743 22:59:27.672430 ==
4744 22:59:27.675706 Dram Type= 6, Freq= 0, CH_1, rank 1
4745 22:59:27.678905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4746 22:59:27.678979 ==
4747 22:59:27.679041
4748 22:59:27.679110
4749 22:59:27.682256 TX Vref Scan disable
4750 22:59:27.686059 == TX Byte 0 ==
4751 22:59:27.688755 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4752 22:59:27.692171 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4753 22:59:27.695777 == TX Byte 1 ==
4754 22:59:27.698884 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4755 22:59:27.702221 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4756 22:59:27.702318
4757 22:59:27.702383 [DATLAT]
4758 22:59:27.705592 Freq=600, CH1 RK1
4759 22:59:27.705691
4760 22:59:27.708892 DATLAT Default: 0x9
4761 22:59:27.708979 0, 0xFFFF, sum = 0
4762 22:59:27.712496 1, 0xFFFF, sum = 0
4763 22:59:27.712570 2, 0xFFFF, sum = 0
4764 22:59:27.715137 3, 0xFFFF, sum = 0
4765 22:59:27.715208 4, 0xFFFF, sum = 0
4766 22:59:27.718313 5, 0xFFFF, sum = 0
4767 22:59:27.718384 6, 0xFFFF, sum = 0
4768 22:59:27.721729 7, 0xFFFF, sum = 0
4769 22:59:27.721801 8, 0x0, sum = 1
4770 22:59:27.724911 9, 0x0, sum = 2
4771 22:59:27.724989 10, 0x0, sum = 3
4772 22:59:27.728490 11, 0x0, sum = 4
4773 22:59:27.728560 best_step = 9
4774 22:59:27.728621
4775 22:59:27.728684 ==
4776 22:59:27.731700 Dram Type= 6, Freq= 0, CH_1, rank 1
4777 22:59:27.735048 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4778 22:59:27.735121 ==
4779 22:59:27.738519 RX Vref Scan: 0
4780 22:59:27.738599
4781 22:59:27.741355 RX Vref 0 -> 0, step: 1
4782 22:59:27.741458
4783 22:59:27.744926 RX Delay -179 -> 252, step: 8
4784 22:59:27.747894 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4785 22:59:27.751578 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4786 22:59:27.758057 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4787 22:59:27.761082 iDelay=205, Bit 3, Center 36 (-123 ~ 196) 320
4788 22:59:27.764626 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4789 22:59:27.767967 iDelay=205, Bit 5, Center 44 (-115 ~ 204) 320
4790 22:59:27.774197 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4791 22:59:27.777511 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4792 22:59:27.780777 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4793 22:59:27.784075 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4794 22:59:27.790699 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4795 22:59:27.794050 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4796 22:59:27.797276 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4797 22:59:27.800867 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4798 22:59:27.807452 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4799 22:59:27.810922 iDelay=205, Bit 15, Center 44 (-115 ~ 204) 320
4800 22:59:27.811001 ==
4801 22:59:27.813679 Dram Type= 6, Freq= 0, CH_1, rank 1
4802 22:59:27.817199 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4803 22:59:27.817270 ==
4804 22:59:27.820165 DQS Delay:
4805 22:59:27.820232 DQS0 = 0, DQS1 = 0
4806 22:59:27.820300 DQM Delay:
4807 22:59:27.823884 DQM0 = 37, DQM1 = 34
4808 22:59:27.823951 DQ Delay:
4809 22:59:27.827125 DQ0 =40, DQ1 =36, DQ2 =28, DQ3 =36
4810 22:59:27.830536 DQ4 =36, DQ5 =44, DQ6 =44, DQ7 =32
4811 22:59:27.833786 DQ8 =20, DQ9 =24, DQ10 =36, DQ11 =24
4812 22:59:27.837140 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =44
4813 22:59:27.837222
4814 22:59:27.837286
4815 22:59:27.846604 [DQSOSCAuto] RK1, (LSB)MR18= 0x3257, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 400 ps
4816 22:59:27.850410 CH1 RK1: MR19=808, MR18=3257
4817 22:59:27.853241 CH1_RK1: MR19=0x808, MR18=0x3257, DQSOSC=393, MR23=63, INC=169, DEC=113
4818 22:59:27.856833 [RxdqsGatingPostProcess] freq 600
4819 22:59:27.862949 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4820 22:59:27.866575 Pre-setting of DQS Precalculation
4821 22:59:27.869817 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4822 22:59:27.879511 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4823 22:59:27.885839 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4824 22:59:27.885917
4825 22:59:27.885980
4826 22:59:27.889747 [Calibration Summary] 1200 Mbps
4827 22:59:27.889818 CH 0, Rank 0
4828 22:59:27.893168 SW Impedance : PASS
4829 22:59:27.893238 DUTY Scan : NO K
4830 22:59:27.896237 ZQ Calibration : PASS
4831 22:59:27.899710 Jitter Meter : NO K
4832 22:59:27.899783 CBT Training : PASS
4833 22:59:27.902335 Write leveling : PASS
4834 22:59:27.905805 RX DQS gating : PASS
4835 22:59:27.905875 RX DQ/DQS(RDDQC) : PASS
4836 22:59:27.909226 TX DQ/DQS : PASS
4837 22:59:27.912253 RX DATLAT : PASS
4838 22:59:27.912324 RX DQ/DQS(Engine): PASS
4839 22:59:27.915928 TX OE : NO K
4840 22:59:27.916004 All Pass.
4841 22:59:27.916097
4842 22:59:27.918723 CH 0, Rank 1
4843 22:59:27.918792 SW Impedance : PASS
4844 22:59:27.922646 DUTY Scan : NO K
4845 22:59:27.925583 ZQ Calibration : PASS
4846 22:59:27.925652 Jitter Meter : NO K
4847 22:59:27.929183 CBT Training : PASS
4848 22:59:27.932277 Write leveling : PASS
4849 22:59:27.932347 RX DQS gating : PASS
4850 22:59:27.935701 RX DQ/DQS(RDDQC) : PASS
4851 22:59:27.939065 TX DQ/DQS : PASS
4852 22:59:27.939134 RX DATLAT : PASS
4853 22:59:27.941958 RX DQ/DQS(Engine): PASS
4854 22:59:27.945598 TX OE : NO K
4855 22:59:27.945673 All Pass.
4856 22:59:27.945735
4857 22:59:27.945804 CH 1, Rank 0
4858 22:59:27.949079 SW Impedance : PASS
4859 22:59:27.951990 DUTY Scan : NO K
4860 22:59:27.952097 ZQ Calibration : PASS
4861 22:59:27.955207 Jitter Meter : NO K
4862 22:59:27.958672 CBT Training : PASS
4863 22:59:27.958748 Write leveling : PASS
4864 22:59:27.961968 RX DQS gating : PASS
4865 22:59:27.965102 RX DQ/DQS(RDDQC) : PASS
4866 22:59:27.965178 TX DQ/DQS : PASS
4867 22:59:27.968196 RX DATLAT : PASS
4868 22:59:27.968267 RX DQ/DQS(Engine): PASS
4869 22:59:27.971852 TX OE : NO K
4870 22:59:27.971920 All Pass.
4871 22:59:27.971979
4872 22:59:27.974990 CH 1, Rank 1
4873 22:59:27.978280 SW Impedance : PASS
4874 22:59:27.978348 DUTY Scan : NO K
4875 22:59:27.981977 ZQ Calibration : PASS
4876 22:59:27.982050 Jitter Meter : NO K
4877 22:59:27.984805 CBT Training : PASS
4878 22:59:27.988293 Write leveling : PASS
4879 22:59:27.988375 RX DQS gating : PASS
4880 22:59:27.991528 RX DQ/DQS(RDDQC) : PASS
4881 22:59:27.994676 TX DQ/DQS : PASS
4882 22:59:27.994758 RX DATLAT : PASS
4883 22:59:27.998078 RX DQ/DQS(Engine): PASS
4884 22:59:28.001432 TX OE : NO K
4885 22:59:28.001517 All Pass.
4886 22:59:28.001602
4887 22:59:28.004702 DramC Write-DBI off
4888 22:59:28.004786 PER_BANK_REFRESH: Hybrid Mode
4889 22:59:28.007942 TX_TRACKING: ON
4890 22:59:28.018042 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4891 22:59:28.021326 [FAST_K] Save calibration result to emmc
4892 22:59:28.024258 dramc_set_vcore_voltage set vcore to 662500
4893 22:59:28.024343 Read voltage for 933, 3
4894 22:59:28.027597 Vio18 = 0
4895 22:59:28.027681 Vcore = 662500
4896 22:59:28.027765 Vdram = 0
4897 22:59:28.030842 Vddq = 0
4898 22:59:28.030925 Vmddr = 0
4899 22:59:28.037903 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4900 22:59:28.040658 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4901 22:59:28.043981 MEM_TYPE=3, freq_sel=17
4902 22:59:28.047394 sv_algorithm_assistance_LP4_1600
4903 22:59:28.050853 ============ PULL DRAM RESETB DOWN ============
4904 22:59:28.054297 ========== PULL DRAM RESETB DOWN end =========
4905 22:59:28.060956 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4906 22:59:28.063946 ===================================
4907 22:59:28.064056 LPDDR4 DRAM CONFIGURATION
4908 22:59:28.067118 ===================================
4909 22:59:28.070778 EX_ROW_EN[0] = 0x0
4910 22:59:28.073809 EX_ROW_EN[1] = 0x0
4911 22:59:28.073895 LP4Y_EN = 0x0
4912 22:59:28.077023 WORK_FSP = 0x0
4913 22:59:28.077098 WL = 0x3
4914 22:59:28.080746 RL = 0x3
4915 22:59:28.080820 BL = 0x2
4916 22:59:28.083395 RPST = 0x0
4917 22:59:28.083469 RD_PRE = 0x0
4918 22:59:28.086997 WR_PRE = 0x1
4919 22:59:28.087069 WR_PST = 0x0
4920 22:59:28.090261 DBI_WR = 0x0
4921 22:59:28.090335 DBI_RD = 0x0
4922 22:59:28.094109 OTF = 0x1
4923 22:59:28.096880 ===================================
4924 22:59:28.100007 ===================================
4925 22:59:28.100114 ANA top config
4926 22:59:28.103427 ===================================
4927 22:59:28.106625 DLL_ASYNC_EN = 0
4928 22:59:28.110138 ALL_SLAVE_EN = 1
4929 22:59:28.113002 NEW_RANK_MODE = 1
4930 22:59:28.113078 DLL_IDLE_MODE = 1
4931 22:59:28.116315 LP45_APHY_COMB_EN = 1
4932 22:59:28.119728 TX_ODT_DIS = 1
4933 22:59:28.123109 NEW_8X_MODE = 1
4934 22:59:28.126569 ===================================
4935 22:59:28.129799 ===================================
4936 22:59:28.132866 data_rate = 1866
4937 22:59:28.136046 CKR = 1
4938 22:59:28.136134 DQ_P2S_RATIO = 8
4939 22:59:28.139753 ===================================
4940 22:59:28.142960 CA_P2S_RATIO = 8
4941 22:59:28.145922 DQ_CA_OPEN = 0
4942 22:59:28.149419 DQ_SEMI_OPEN = 0
4943 22:59:28.152715 CA_SEMI_OPEN = 0
4944 22:59:28.156156 CA_FULL_RATE = 0
4945 22:59:28.156228 DQ_CKDIV4_EN = 1
4946 22:59:28.159405 CA_CKDIV4_EN = 1
4947 22:59:28.162506 CA_PREDIV_EN = 0
4948 22:59:28.165772 PH8_DLY = 0
4949 22:59:28.169204 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4950 22:59:28.172197 DQ_AAMCK_DIV = 4
4951 22:59:28.172270 CA_AAMCK_DIV = 4
4952 22:59:28.175745 CA_ADMCK_DIV = 4
4953 22:59:28.178853 DQ_TRACK_CA_EN = 0
4954 22:59:28.182655 CA_PICK = 933
4955 22:59:28.185508 CA_MCKIO = 933
4956 22:59:28.189086 MCKIO_SEMI = 0
4957 22:59:28.192234 PLL_FREQ = 3732
4958 22:59:28.192309 DQ_UI_PI_RATIO = 32
4959 22:59:28.195416 CA_UI_PI_RATIO = 0
4960 22:59:28.199057 ===================================
4961 22:59:28.202317 ===================================
4962 22:59:28.205359 memory_type:LPDDR4
4963 22:59:28.208632 GP_NUM : 10
4964 22:59:28.208726 SRAM_EN : 1
4965 22:59:28.211946 MD32_EN : 0
4966 22:59:28.215266 ===================================
4967 22:59:28.218605 [ANA_INIT] >>>>>>>>>>>>>>
4968 22:59:28.222092 <<<<<< [CONFIGURE PHASE]: ANA_TX
4969 22:59:28.224909 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4970 22:59:28.228791 ===================================
4971 22:59:28.228875 data_rate = 1866,PCW = 0X8f00
4972 22:59:28.231568 ===================================
4973 22:59:28.235124 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4974 22:59:28.241664 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4975 22:59:28.248202 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4976 22:59:28.251495 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4977 22:59:28.254793 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4978 22:59:28.258330 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4979 22:59:28.261077 [ANA_INIT] flow start
4980 22:59:28.264576 [ANA_INIT] PLL >>>>>>>>
4981 22:59:28.264659 [ANA_INIT] PLL <<<<<<<<
4982 22:59:28.267842 [ANA_INIT] MIDPI >>>>>>>>
4983 22:59:28.271210 [ANA_INIT] MIDPI <<<<<<<<
4984 22:59:28.271294 [ANA_INIT] DLL >>>>>>>>
4985 22:59:28.274713 [ANA_INIT] flow end
4986 22:59:28.277672 ============ LP4 DIFF to SE enter ============
4987 22:59:28.284080 ============ LP4 DIFF to SE exit ============
4988 22:59:28.284174 [ANA_INIT] <<<<<<<<<<<<<
4989 22:59:28.287373 [Flow] Enable top DCM control >>>>>
4990 22:59:28.290842 [Flow] Enable top DCM control <<<<<
4991 22:59:28.293962 Enable DLL master slave shuffle
4992 22:59:28.300646 ==============================================================
4993 22:59:28.300723 Gating Mode config
4994 22:59:28.307091 ==============================================================
4995 22:59:28.310489 Config description:
4996 22:59:28.317275 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4997 22:59:28.323866 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4998 22:59:28.330476 SELPH_MODE 0: By rank 1: By Phase
4999 22:59:28.337246 ==============================================================
5000 22:59:28.340170 GAT_TRACK_EN = 1
5001 22:59:28.340277 RX_GATING_MODE = 2
5002 22:59:28.343452 RX_GATING_TRACK_MODE = 2
5003 22:59:28.346920 SELPH_MODE = 1
5004 22:59:28.350095 PICG_EARLY_EN = 1
5005 22:59:28.353266 VALID_LAT_VALUE = 1
5006 22:59:28.359976 ==============================================================
5007 22:59:28.363407 Enter into Gating configuration >>>>
5008 22:59:28.366698 Exit from Gating configuration <<<<
5009 22:59:28.370124 Enter into DVFS_PRE_config >>>>>
5010 22:59:28.379623 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5011 22:59:28.382794 Exit from DVFS_PRE_config <<<<<
5012 22:59:28.386520 Enter into PICG configuration >>>>
5013 22:59:28.389661 Exit from PICG configuration <<<<
5014 22:59:28.392787 [RX_INPUT] configuration >>>>>
5015 22:59:28.395999 [RX_INPUT] configuration <<<<<
5016 22:59:28.399670 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5017 22:59:28.406406 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5018 22:59:28.412457 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5019 22:59:28.419084 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5020 22:59:28.425614 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5021 22:59:28.429085 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5022 22:59:28.435502 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5023 22:59:28.438857 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5024 22:59:28.442403 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5025 22:59:28.445891 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5026 22:59:28.452149 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5027 22:59:28.455308 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5028 22:59:28.458671 ===================================
5029 22:59:28.462098 LPDDR4 DRAM CONFIGURATION
5030 22:59:28.465354 ===================================
5031 22:59:28.465453 EX_ROW_EN[0] = 0x0
5032 22:59:28.468686 EX_ROW_EN[1] = 0x0
5033 22:59:28.468784 LP4Y_EN = 0x0
5034 22:59:28.471629 WORK_FSP = 0x0
5035 22:59:28.471727 WL = 0x3
5036 22:59:28.475239 RL = 0x3
5037 22:59:28.478286 BL = 0x2
5038 22:59:28.478385 RPST = 0x0
5039 22:59:28.481705 RD_PRE = 0x0
5040 22:59:28.481802 WR_PRE = 0x1
5041 22:59:28.485241 WR_PST = 0x0
5042 22:59:28.485337 DBI_WR = 0x0
5043 22:59:28.487980 DBI_RD = 0x0
5044 22:59:28.488086 OTF = 0x1
5045 22:59:28.491553 ===================================
5046 22:59:28.494584 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5047 22:59:28.501524 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5048 22:59:28.504816 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5049 22:59:28.507908 ===================================
5050 22:59:28.511595 LPDDR4 DRAM CONFIGURATION
5051 22:59:28.514618 ===================================
5052 22:59:28.514700 EX_ROW_EN[0] = 0x10
5053 22:59:28.517865 EX_ROW_EN[1] = 0x0
5054 22:59:28.521150 LP4Y_EN = 0x0
5055 22:59:28.521234 WORK_FSP = 0x0
5056 22:59:28.524535 WL = 0x3
5057 22:59:28.524618 RL = 0x3
5058 22:59:28.527901 BL = 0x2
5059 22:59:28.527983 RPST = 0x0
5060 22:59:28.530925 RD_PRE = 0x0
5061 22:59:28.531007 WR_PRE = 0x1
5062 22:59:28.534349 WR_PST = 0x0
5063 22:59:28.534432 DBI_WR = 0x0
5064 22:59:28.537610 DBI_RD = 0x0
5065 22:59:28.537692 OTF = 0x1
5066 22:59:28.540974 ===================================
5067 22:59:28.547873 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5068 22:59:28.552015 nWR fixed to 30
5069 22:59:28.555099 [ModeRegInit_LP4] CH0 RK0
5070 22:59:28.555182 [ModeRegInit_LP4] CH0 RK1
5071 22:59:28.558263 [ModeRegInit_LP4] CH1 RK0
5072 22:59:28.561573 [ModeRegInit_LP4] CH1 RK1
5073 22:59:28.561656 match AC timing 9
5074 22:59:28.568025 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5075 22:59:28.571426 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5076 22:59:28.574993 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5077 22:59:28.581614 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5078 22:59:28.584396 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5079 22:59:28.584484 ==
5080 22:59:28.587770 Dram Type= 6, Freq= 0, CH_0, rank 0
5081 22:59:28.591081 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5082 22:59:28.594516 ==
5083 22:59:28.597735 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5084 22:59:28.604330 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5085 22:59:28.607565 [CA 0] Center 37 (7~68) winsize 62
5086 22:59:28.610882 [CA 1] Center 37 (7~68) winsize 62
5087 22:59:28.614007 [CA 2] Center 34 (4~64) winsize 61
5088 22:59:28.617658 [CA 3] Center 34 (4~65) winsize 62
5089 22:59:28.620799 [CA 4] Center 33 (3~63) winsize 61
5090 22:59:28.623923 [CA 5] Center 32 (2~63) winsize 62
5091 22:59:28.624023
5092 22:59:28.627666 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5093 22:59:28.627766
5094 22:59:28.630757 [CATrainingPosCal] consider 1 rank data
5095 22:59:28.633920 u2DelayCellTimex100 = 270/100 ps
5096 22:59:28.637167 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5097 22:59:28.640384 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5098 22:59:28.643895 CA2 delay=34 (4~64),Diff = 2 PI (12 cell)
5099 22:59:28.650426 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5100 22:59:28.653828 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5101 22:59:28.657322 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5102 22:59:28.657420
5103 22:59:28.660562 CA PerBit enable=1, Macro0, CA PI delay=32
5104 22:59:28.660637
5105 22:59:28.663733 [CBTSetCACLKResult] CA Dly = 32
5106 22:59:28.663829 CS Dly: 5 (0~36)
5107 22:59:28.666860 ==
5108 22:59:28.670309 Dram Type= 6, Freq= 0, CH_0, rank 1
5109 22:59:28.673779 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5110 22:59:28.673880 ==
5111 22:59:28.676488 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5112 22:59:28.683180 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5113 22:59:28.686658 [CA 0] Center 37 (7~68) winsize 62
5114 22:59:28.690597 [CA 1] Center 37 (7~68) winsize 62
5115 22:59:28.693444 [CA 2] Center 35 (5~65) winsize 61
5116 22:59:28.696760 [CA 3] Center 34 (4~65) winsize 62
5117 22:59:28.700127 [CA 4] Center 33 (3~64) winsize 62
5118 22:59:28.703830 [CA 5] Center 32 (2~63) winsize 62
5119 22:59:28.703943
5120 22:59:28.707163 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5121 22:59:28.707285
5122 22:59:28.709863 [CATrainingPosCal] consider 2 rank data
5123 22:59:28.713034 u2DelayCellTimex100 = 270/100 ps
5124 22:59:28.719797 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5125 22:59:28.722799 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5126 22:59:28.726457 CA2 delay=34 (5~64),Diff = 2 PI (12 cell)
5127 22:59:28.729419 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5128 22:59:28.733010 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5129 22:59:28.736261 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5130 22:59:28.736338
5131 22:59:28.739366 CA PerBit enable=1, Macro0, CA PI delay=32
5132 22:59:28.739467
5133 22:59:28.742782 [CBTSetCACLKResult] CA Dly = 32
5134 22:59:28.745837 CS Dly: 6 (0~39)
5135 22:59:28.745960
5136 22:59:28.749490 ----->DramcWriteLeveling(PI) begin...
5137 22:59:28.749607 ==
5138 22:59:28.752744 Dram Type= 6, Freq= 0, CH_0, rank 0
5139 22:59:28.755968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5140 22:59:28.756115 ==
5141 22:59:28.758949 Write leveling (Byte 0): 31 => 31
5142 22:59:28.762285 Write leveling (Byte 1): 28 => 28
5143 22:59:28.765559 DramcWriteLeveling(PI) end<-----
5144 22:59:28.765660
5145 22:59:28.765763 ==
5146 22:59:28.768837 Dram Type= 6, Freq= 0, CH_0, rank 0
5147 22:59:28.772175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5148 22:59:28.772251 ==
5149 22:59:28.775669 [Gating] SW mode calibration
5150 22:59:28.782371 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5151 22:59:28.789115 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5152 22:59:28.792230 0 14 0 | B1->B0 | 2626 3434 | 1 0 | (1 1) (0 0)
5153 22:59:28.798653 0 14 4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
5154 22:59:28.802058 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5155 22:59:28.805367 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5156 22:59:28.812257 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5157 22:59:28.815301 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5158 22:59:28.818588 0 14 24 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
5159 22:59:28.825071 0 14 28 | B1->B0 | 3434 2929 | 1 0 | (1 1) (1 0)
5160 22:59:28.828098 0 15 0 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)
5161 22:59:28.831953 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5162 22:59:28.838619 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5163 22:59:28.841631 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5164 22:59:28.844745 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5165 22:59:28.851933 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5166 22:59:28.854859 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5167 22:59:28.858378 0 15 28 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
5168 22:59:28.865296 1 0 0 | B1->B0 | 3434 4646 | 1 0 | (0 0) (0 0)
5169 22:59:28.868260 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5170 22:59:28.871256 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5171 22:59:28.878003 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5172 22:59:28.881196 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5173 22:59:28.884533 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5174 22:59:28.891039 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5175 22:59:28.894380 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5176 22:59:28.897727 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5177 22:59:28.904592 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5178 22:59:28.907849 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5179 22:59:28.910812 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5180 22:59:28.917354 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5181 22:59:28.920819 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5182 22:59:28.924345 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5183 22:59:28.930608 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5184 22:59:28.934250 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5185 22:59:28.937203 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5186 22:59:28.943847 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5187 22:59:28.946974 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5188 22:59:28.950302 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5189 22:59:28.956814 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5190 22:59:28.960749 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5191 22:59:28.963723 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5192 22:59:28.966768 Total UI for P1: 0, mck2ui 16
5193 22:59:28.970101 best dqsien dly found for B0: ( 1, 2, 26)
5194 22:59:28.976457 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5195 22:59:28.979805 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5196 22:59:28.983046 Total UI for P1: 0, mck2ui 16
5197 22:59:28.986336 best dqsien dly found for B1: ( 1, 3, 0)
5198 22:59:28.989881 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5199 22:59:28.992869 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5200 22:59:28.992971
5201 22:59:28.996604 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5202 22:59:28.999593 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5203 22:59:29.002848 [Gating] SW calibration Done
5204 22:59:29.002959 ==
5205 22:59:29.006332 Dram Type= 6, Freq= 0, CH_0, rank 0
5206 22:59:29.009458 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5207 22:59:29.012811 ==
5208 22:59:29.012881 RX Vref Scan: 0
5209 22:59:29.012941
5210 22:59:29.016175 RX Vref 0 -> 0, step: 1
5211 22:59:29.016247
5212 22:59:29.019510 RX Delay -80 -> 252, step: 8
5213 22:59:29.022765 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5214 22:59:29.025771 iDelay=208, Bit 1, Center 103 (8 ~ 199) 192
5215 22:59:29.029014 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5216 22:59:29.032840 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5217 22:59:29.036427 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5218 22:59:29.042673 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5219 22:59:29.045691 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5220 22:59:29.048995 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5221 22:59:29.052611 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5222 22:59:29.055621 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5223 22:59:29.062546 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5224 22:59:29.065610 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5225 22:59:29.068756 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5226 22:59:29.071954 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5227 22:59:29.075220 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5228 22:59:29.078595 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5229 22:59:29.082232 ==
5230 22:59:29.085495 Dram Type= 6, Freq= 0, CH_0, rank 0
5231 22:59:29.088947 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5232 22:59:29.089058 ==
5233 22:59:29.089155 DQS Delay:
5234 22:59:29.092436 DQS0 = 0, DQS1 = 0
5235 22:59:29.092543 DQM Delay:
5236 22:59:29.095060 DQM0 = 100, DQM1 = 88
5237 22:59:29.095142 DQ Delay:
5238 22:59:29.098441 DQ0 =103, DQ1 =103, DQ2 =95, DQ3 =95
5239 22:59:29.101740 DQ4 =103, DQ5 =87, DQ6 =111, DQ7 =107
5240 22:59:29.105092 DQ8 =83, DQ9 =75, DQ10 =87, DQ11 =83
5241 22:59:29.108813 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5242 22:59:29.108925
5243 22:59:29.108995
5244 22:59:29.109056 ==
5245 22:59:29.111855 Dram Type= 6, Freq= 0, CH_0, rank 0
5246 22:59:29.114722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5247 22:59:29.118121 ==
5248 22:59:29.118204
5249 22:59:29.118270
5250 22:59:29.118332 TX Vref Scan disable
5251 22:59:29.121341 == TX Byte 0 ==
5252 22:59:29.124703 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5253 22:59:29.127983 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5254 22:59:29.131394 == TX Byte 1 ==
5255 22:59:29.134640 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5256 22:59:29.141380 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5257 22:59:29.141465 ==
5258 22:59:29.144547 Dram Type= 6, Freq= 0, CH_0, rank 0
5259 22:59:29.147734 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5260 22:59:29.147821 ==
5261 22:59:29.147888
5262 22:59:29.147950
5263 22:59:29.151181 TX Vref Scan disable
5264 22:59:29.151265 == TX Byte 0 ==
5265 22:59:29.157562 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5266 22:59:29.161098 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5267 22:59:29.161183 == TX Byte 1 ==
5268 22:59:29.167452 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5269 22:59:29.171002 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5270 22:59:29.171105
5271 22:59:29.171196 [DATLAT]
5272 22:59:29.174273 Freq=933, CH0 RK0
5273 22:59:29.174345
5274 22:59:29.174406 DATLAT Default: 0xd
5275 22:59:29.177351 0, 0xFFFF, sum = 0
5276 22:59:29.180602 1, 0xFFFF, sum = 0
5277 22:59:29.180677 2, 0xFFFF, sum = 0
5278 22:59:29.183926 3, 0xFFFF, sum = 0
5279 22:59:29.184025 4, 0xFFFF, sum = 0
5280 22:59:29.187176 5, 0xFFFF, sum = 0
5281 22:59:29.187276 6, 0xFFFF, sum = 0
5282 22:59:29.190555 7, 0xFFFF, sum = 0
5283 22:59:29.190655 8, 0xFFFF, sum = 0
5284 22:59:29.193962 9, 0xFFFF, sum = 0
5285 22:59:29.194052 10, 0x0, sum = 1
5286 22:59:29.196818 11, 0x0, sum = 2
5287 22:59:29.196888 12, 0x0, sum = 3
5288 22:59:29.200290 13, 0x0, sum = 4
5289 22:59:29.200360 best_step = 11
5290 22:59:29.200418
5291 22:59:29.200476 ==
5292 22:59:29.203622 Dram Type= 6, Freq= 0, CH_0, rank 0
5293 22:59:29.206894 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5294 22:59:29.210406 ==
5295 22:59:29.210502 RX Vref Scan: 1
5296 22:59:29.210589
5297 22:59:29.213708 RX Vref 0 -> 0, step: 1
5298 22:59:29.213775
5299 22:59:29.216613 RX Delay -61 -> 252, step: 4
5300 22:59:29.216682
5301 22:59:29.219840 Set Vref, RX VrefLevel [Byte0]: 53
5302 22:59:29.223664 [Byte1]: 58
5303 22:59:29.223733
5304 22:59:29.226349 Final RX Vref Byte 0 = 53 to rank0
5305 22:59:29.229796 Final RX Vref Byte 1 = 58 to rank0
5306 22:59:29.233119 Final RX Vref Byte 0 = 53 to rank1
5307 22:59:29.236380 Final RX Vref Byte 1 = 58 to rank1==
5308 22:59:29.239505 Dram Type= 6, Freq= 0, CH_0, rank 0
5309 22:59:29.242925 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5310 22:59:29.242994 ==
5311 22:59:29.246279 DQS Delay:
5312 22:59:29.246348 DQS0 = 0, DQS1 = 0
5313 22:59:29.246407 DQM Delay:
5314 22:59:29.250012 DQM0 = 98, DQM1 = 88
5315 22:59:29.250087 DQ Delay:
5316 22:59:29.253160 DQ0 =100, DQ1 =98, DQ2 =94, DQ3 =96
5317 22:59:29.256212 DQ4 =98, DQ5 =90, DQ6 =108, DQ7 =106
5318 22:59:29.259260 DQ8 =78, DQ9 =74, DQ10 =88, DQ11 =84
5319 22:59:29.262580 DQ12 =96, DQ13 =92, DQ14 =98, DQ15 =94
5320 22:59:29.262661
5321 22:59:29.262726
5322 22:59:29.272725 [DQSOSCAuto] RK0, (LSB)MR18= 0x1b15, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 413 ps
5323 22:59:29.275749 CH0 RK0: MR19=505, MR18=1B15
5324 22:59:29.282665 CH0_RK0: MR19=0x505, MR18=0x1B15, DQSOSC=413, MR23=63, INC=63, DEC=42
5325 22:59:29.282751
5326 22:59:29.285716 ----->DramcWriteLeveling(PI) begin...
5327 22:59:29.285848 ==
5328 22:59:29.288991 Dram Type= 6, Freq= 0, CH_0, rank 1
5329 22:59:29.292507 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5330 22:59:29.292590 ==
5331 22:59:29.295809 Write leveling (Byte 0): 32 => 32
5332 22:59:29.298708 Write leveling (Byte 1): 25 => 25
5333 22:59:29.302214 DramcWriteLeveling(PI) end<-----
5334 22:59:29.302296
5335 22:59:29.302362 ==
5336 22:59:29.305870 Dram Type= 6, Freq= 0, CH_0, rank 1
5337 22:59:29.308663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5338 22:59:29.308759 ==
5339 22:59:29.311923 [Gating] SW mode calibration
5340 22:59:29.318754 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5341 22:59:29.325504 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5342 22:59:29.328388 0 14 0 | B1->B0 | 2929 3434 | 0 1 | (0 0) (1 1)
5343 22:59:29.331675 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5344 22:59:29.338325 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5345 22:59:29.341655 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5346 22:59:29.345228 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5347 22:59:29.351732 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5348 22:59:29.355065 0 14 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
5349 22:59:29.358159 0 14 28 | B1->B0 | 3131 2b2b | 1 0 | (1 1) (0 0)
5350 22:59:29.364579 0 15 0 | B1->B0 | 2f2f 2323 | 1 0 | (1 1) (0 0)
5351 22:59:29.368162 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5352 22:59:29.371294 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5353 22:59:29.378125 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5354 22:59:29.381541 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5355 22:59:29.384677 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5356 22:59:29.390980 0 15 24 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
5357 22:59:29.394089 0 15 28 | B1->B0 | 2323 3b3b | 0 0 | (0 0) (0 0)
5358 22:59:29.397784 1 0 0 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5359 22:59:29.404398 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5360 22:59:29.407794 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5361 22:59:29.410736 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5362 22:59:29.417440 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5363 22:59:29.420763 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5364 22:59:29.424194 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5365 22:59:29.430885 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5366 22:59:29.433523 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5367 22:59:29.440319 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5368 22:59:29.443752 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5369 22:59:29.446983 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5370 22:59:29.453964 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5371 22:59:29.457078 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5372 22:59:29.460246 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5373 22:59:29.466683 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5374 22:59:29.469791 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5375 22:59:29.473213 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5376 22:59:29.479945 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5377 22:59:29.483173 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5378 22:59:29.486507 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5379 22:59:29.493247 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5380 22:59:29.496279 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5381 22:59:29.499509 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5382 22:59:29.505922 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5383 22:59:29.506031 Total UI for P1: 0, mck2ui 16
5384 22:59:29.509869 best dqsien dly found for B0: ( 1, 2, 28)
5385 22:59:29.515901 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5386 22:59:29.519291 Total UI for P1: 0, mck2ui 16
5387 22:59:29.522672 best dqsien dly found for B1: ( 1, 3, 0)
5388 22:59:29.525981 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5389 22:59:29.529274 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5390 22:59:29.529374
5391 22:59:29.532786 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5392 22:59:29.536198 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5393 22:59:29.539489 [Gating] SW calibration Done
5394 22:59:29.539600 ==
5395 22:59:29.542835 Dram Type= 6, Freq= 0, CH_0, rank 1
5396 22:59:29.545820 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5397 22:59:29.545923 ==
5398 22:59:29.548969 RX Vref Scan: 0
5399 22:59:29.549072
5400 22:59:29.552336 RX Vref 0 -> 0, step: 1
5401 22:59:29.552440
5402 22:59:29.552537 RX Delay -80 -> 252, step: 8
5403 22:59:29.559062 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5404 22:59:29.562356 iDelay=200, Bit 1, Center 99 (0 ~ 199) 200
5405 22:59:29.566004 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5406 22:59:29.569101 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5407 22:59:29.572300 iDelay=200, Bit 4, Center 99 (0 ~ 199) 200
5408 22:59:29.575583 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5409 22:59:29.581906 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5410 22:59:29.585535 iDelay=200, Bit 7, Center 107 (16 ~ 199) 184
5411 22:59:29.588733 iDelay=200, Bit 8, Center 79 (-8 ~ 167) 176
5412 22:59:29.591843 iDelay=200, Bit 9, Center 79 (-8 ~ 167) 176
5413 22:59:29.595308 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5414 22:59:29.601810 iDelay=200, Bit 11, Center 87 (0 ~ 175) 176
5415 22:59:29.605301 iDelay=200, Bit 12, Center 91 (0 ~ 183) 184
5416 22:59:29.608128 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5417 22:59:29.611476 iDelay=200, Bit 14, Center 99 (8 ~ 191) 184
5418 22:59:29.614799 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5419 22:59:29.614886 ==
5420 22:59:29.618202 Dram Type= 6, Freq= 0, CH_0, rank 1
5421 22:59:29.625091 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5422 22:59:29.625180 ==
5423 22:59:29.625258 DQS Delay:
5424 22:59:29.627849 DQS0 = 0, DQS1 = 0
5425 22:59:29.627918 DQM Delay:
5426 22:59:29.627982 DQM0 = 97, DQM1 = 89
5427 22:59:29.631027 DQ Delay:
5428 22:59:29.634409 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =95
5429 22:59:29.637689 DQ4 =99, DQ5 =87, DQ6 =103, DQ7 =107
5430 22:59:29.641067 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =87
5431 22:59:29.644522 DQ12 =91, DQ13 =95, DQ14 =99, DQ15 =95
5432 22:59:29.644596
5433 22:59:29.644658
5434 22:59:29.644720 ==
5435 22:59:29.648225 Dram Type= 6, Freq= 0, CH_0, rank 1
5436 22:59:29.650812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5437 22:59:29.650885 ==
5438 22:59:29.650947
5439 22:59:29.651005
5440 22:59:29.654493 TX Vref Scan disable
5441 22:59:29.658079 == TX Byte 0 ==
5442 22:59:29.661407 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5443 22:59:29.664296 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5444 22:59:29.667883 == TX Byte 1 ==
5445 22:59:29.670923 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5446 22:59:29.674153 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5447 22:59:29.674258 ==
5448 22:59:29.677443 Dram Type= 6, Freq= 0, CH_0, rank 1
5449 22:59:29.683777 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5450 22:59:29.683854 ==
5451 22:59:29.683917
5452 22:59:29.683976
5453 22:59:29.684063 TX Vref Scan disable
5454 22:59:29.688028 == TX Byte 0 ==
5455 22:59:29.691225 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5456 22:59:29.697634 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5457 22:59:29.697710 == TX Byte 1 ==
5458 22:59:29.701246 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5459 22:59:29.707400 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5460 22:59:29.707479
5461 22:59:29.707542 [DATLAT]
5462 22:59:29.707601 Freq=933, CH0 RK1
5463 22:59:29.707663
5464 22:59:29.710959 DATLAT Default: 0xb
5465 22:59:29.713991 0, 0xFFFF, sum = 0
5466 22:59:29.714061 1, 0xFFFF, sum = 0
5467 22:59:29.717475 2, 0xFFFF, sum = 0
5468 22:59:29.717546 3, 0xFFFF, sum = 0
5469 22:59:29.720847 4, 0xFFFF, sum = 0
5470 22:59:29.720916 5, 0xFFFF, sum = 0
5471 22:59:29.724161 6, 0xFFFF, sum = 0
5472 22:59:29.724233 7, 0xFFFF, sum = 0
5473 22:59:29.727604 8, 0xFFFF, sum = 0
5474 22:59:29.727694 9, 0xFFFF, sum = 0
5475 22:59:29.731083 10, 0x0, sum = 1
5476 22:59:29.731259 11, 0x0, sum = 2
5477 22:59:29.734095 12, 0x0, sum = 3
5478 22:59:29.734280 13, 0x0, sum = 4
5479 22:59:29.737642 best_step = 11
5480 22:59:29.737787
5481 22:59:29.737880 ==
5482 22:59:29.740511 Dram Type= 6, Freq= 0, CH_0, rank 1
5483 22:59:29.743811 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5484 22:59:29.743973 ==
5485 22:59:29.744096 RX Vref Scan: 0
5486 22:59:29.747182
5487 22:59:29.747288 RX Vref 0 -> 0, step: 1
5488 22:59:29.747379
5489 22:59:29.750460 RX Delay -53 -> 252, step: 4
5490 22:59:29.757096 iDelay=195, Bit 0, Center 94 (7 ~ 182) 176
5491 22:59:29.760519 iDelay=195, Bit 1, Center 100 (11 ~ 190) 180
5492 22:59:29.763900 iDelay=195, Bit 2, Center 92 (3 ~ 182) 180
5493 22:59:29.766891 iDelay=195, Bit 3, Center 94 (3 ~ 186) 184
5494 22:59:29.770337 iDelay=195, Bit 4, Center 100 (11 ~ 190) 180
5495 22:59:29.776851 iDelay=195, Bit 5, Center 88 (-1 ~ 178) 180
5496 22:59:29.779617 iDelay=195, Bit 6, Center 108 (23 ~ 194) 172
5497 22:59:29.783614 iDelay=195, Bit 7, Center 104 (15 ~ 194) 180
5498 22:59:29.786699 iDelay=195, Bit 8, Center 78 (-9 ~ 166) 176
5499 22:59:29.789842 iDelay=195, Bit 9, Center 76 (-9 ~ 162) 172
5500 22:59:29.792845 iDelay=195, Bit 10, Center 92 (3 ~ 182) 180
5501 22:59:29.799779 iDelay=195, Bit 11, Center 84 (-5 ~ 174) 180
5502 22:59:29.803128 iDelay=195, Bit 12, Center 94 (7 ~ 182) 176
5503 22:59:29.806238 iDelay=195, Bit 13, Center 92 (-1 ~ 186) 188
5504 22:59:29.809478 iDelay=195, Bit 14, Center 102 (15 ~ 190) 176
5505 22:59:29.812590 iDelay=195, Bit 15, Center 96 (7 ~ 186) 180
5506 22:59:29.816369 ==
5507 22:59:29.819518 Dram Type= 6, Freq= 0, CH_0, rank 1
5508 22:59:29.822480 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5509 22:59:29.822549 ==
5510 22:59:29.822611 DQS Delay:
5511 22:59:29.825974 DQS0 = 0, DQS1 = 0
5512 22:59:29.826041 DQM Delay:
5513 22:59:29.829277 DQM0 = 97, DQM1 = 89
5514 22:59:29.829342 DQ Delay:
5515 22:59:29.832647 DQ0 =94, DQ1 =100, DQ2 =92, DQ3 =94
5516 22:59:29.835942 DQ4 =100, DQ5 =88, DQ6 =108, DQ7 =104
5517 22:59:29.839368 DQ8 =78, DQ9 =76, DQ10 =92, DQ11 =84
5518 22:59:29.842636 DQ12 =94, DQ13 =92, DQ14 =102, DQ15 =96
5519 22:59:29.842730
5520 22:59:29.842818
5521 22:59:29.852190 [DQSOSCAuto] RK1, (LSB)MR18= 0x120e, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 416 ps
5522 22:59:29.852279 CH0 RK1: MR19=505, MR18=120E
5523 22:59:29.859245 CH0_RK1: MR19=0x505, MR18=0x120E, DQSOSC=416, MR23=63, INC=62, DEC=41
5524 22:59:29.862455 [RxdqsGatingPostProcess] freq 933
5525 22:59:29.869386 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5526 22:59:29.872873 best DQS0 dly(2T, 0.5T) = (0, 10)
5527 22:59:29.876132 best DQS1 dly(2T, 0.5T) = (0, 11)
5528 22:59:29.879613 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5529 22:59:29.882626 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5530 22:59:29.885588 best DQS0 dly(2T, 0.5T) = (0, 10)
5531 22:59:29.886050 best DQS1 dly(2T, 0.5T) = (0, 11)
5532 22:59:29.889151 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5533 22:59:29.892350 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5534 22:59:29.895541 Pre-setting of DQS Precalculation
5535 22:59:29.901725 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5536 22:59:29.902187 ==
5537 22:59:29.905424 Dram Type= 6, Freq= 0, CH_1, rank 0
5538 22:59:29.908486 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5539 22:59:29.908926 ==
5540 22:59:29.915114 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5541 22:59:29.921861 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5542 22:59:29.925138 [CA 0] Center 36 (6~67) winsize 62
5543 22:59:29.928186 [CA 1] Center 36 (6~67) winsize 62
5544 22:59:29.931398 [CA 2] Center 34 (4~65) winsize 62
5545 22:59:29.934666 [CA 3] Center 33 (3~64) winsize 62
5546 22:59:29.938085 [CA 4] Center 34 (4~64) winsize 61
5547 22:59:29.941457 [CA 5] Center 33 (3~64) winsize 62
5548 22:59:29.941885
5549 22:59:29.944828 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5550 22:59:29.945258
5551 22:59:29.948195 [CATrainingPosCal] consider 1 rank data
5552 22:59:29.951590 u2DelayCellTimex100 = 270/100 ps
5553 22:59:29.955071 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5554 22:59:29.958411 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5555 22:59:29.961290 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5556 22:59:29.964475 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5557 22:59:29.967650 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5558 22:59:29.974332 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5559 22:59:29.974775
5560 22:59:29.977751 CA PerBit enable=1, Macro0, CA PI delay=33
5561 22:59:29.978205
5562 22:59:29.981230 [CBTSetCACLKResult] CA Dly = 33
5563 22:59:29.981664 CS Dly: 5 (0~36)
5564 22:59:29.982000 ==
5565 22:59:29.984103 Dram Type= 6, Freq= 0, CH_1, rank 1
5566 22:59:29.987443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5567 22:59:29.990749 ==
5568 22:59:29.994083 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5569 22:59:30.000712 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5570 22:59:30.003967 [CA 0] Center 36 (6~67) winsize 62
5571 22:59:30.007122 [CA 1] Center 36 (6~67) winsize 62
5572 22:59:30.010386 [CA 2] Center 34 (4~65) winsize 62
5573 22:59:30.013855 [CA 3] Center 33 (3~64) winsize 62
5574 22:59:30.017086 [CA 4] Center 33 (3~64) winsize 62
5575 22:59:30.020910 [CA 5] Center 33 (3~64) winsize 62
5576 22:59:30.021335
5577 22:59:30.024010 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5578 22:59:30.024477
5579 22:59:30.027017 [CATrainingPosCal] consider 2 rank data
5580 22:59:30.030171 u2DelayCellTimex100 = 270/100 ps
5581 22:59:30.033829 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5582 22:59:30.037024 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5583 22:59:30.043522 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5584 22:59:30.046739 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5585 22:59:30.050114 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5586 22:59:30.053566 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5587 22:59:30.054018
5588 22:59:30.056439 CA PerBit enable=1, Macro0, CA PI delay=33
5589 22:59:30.056874
5590 22:59:30.059772 [CBTSetCACLKResult] CA Dly = 33
5591 22:59:30.060306 CS Dly: 6 (0~38)
5592 22:59:30.063178
5593 22:59:30.066610 ----->DramcWriteLeveling(PI) begin...
5594 22:59:30.067079 ==
5595 22:59:30.069904 Dram Type= 6, Freq= 0, CH_1, rank 0
5596 22:59:30.073223 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5597 22:59:30.073651 ==
5598 22:59:30.076495 Write leveling (Byte 0): 26 => 26
5599 22:59:30.079334 Write leveling (Byte 1): 31 => 31
5600 22:59:30.083045 DramcWriteLeveling(PI) end<-----
5601 22:59:30.083513
5602 22:59:30.083852 ==
5603 22:59:30.086494 Dram Type= 6, Freq= 0, CH_1, rank 0
5604 22:59:30.089403 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5605 22:59:30.089829 ==
5606 22:59:30.093357 [Gating] SW mode calibration
5607 22:59:30.099494 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5608 22:59:30.106316 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5609 22:59:30.109341 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5610 22:59:30.112675 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5611 22:59:30.119333 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5612 22:59:30.122651 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5613 22:59:30.125927 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5614 22:59:30.132905 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5615 22:59:30.135755 0 14 24 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 1)
5616 22:59:30.139053 0 14 28 | B1->B0 | 2d2d 2828 | 1 0 | (1 0) (0 0)
5617 22:59:30.145696 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5618 22:59:30.148963 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5619 22:59:30.152255 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5620 22:59:30.158552 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5621 22:59:30.162083 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5622 22:59:30.165486 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5623 22:59:30.171946 0 15 24 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
5624 22:59:30.175352 0 15 28 | B1->B0 | 3737 3b3b | 0 0 | (0 0) (0 0)
5625 22:59:30.178360 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5626 22:59:30.185097 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5627 22:59:30.188616 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5628 22:59:30.191695 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5629 22:59:30.198076 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5630 22:59:30.201280 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5631 22:59:30.204739 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5632 22:59:30.211227 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5633 22:59:30.214315 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5634 22:59:30.217946 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5635 22:59:30.224536 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5636 22:59:30.227995 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5637 22:59:30.231165 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5638 22:59:30.237790 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5639 22:59:30.240954 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5640 22:59:30.244362 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5641 22:59:30.250692 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5642 22:59:30.254281 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5643 22:59:30.257328 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5644 22:59:30.264021 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5645 22:59:30.267366 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5646 22:59:30.270810 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5647 22:59:30.277036 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5648 22:59:30.280157 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5649 22:59:30.283527 Total UI for P1: 0, mck2ui 16
5650 22:59:30.286676 best dqsien dly found for B0: ( 1, 2, 24)
5651 22:59:30.290152 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5652 22:59:30.293506 Total UI for P1: 0, mck2ui 16
5653 22:59:30.297055 best dqsien dly found for B1: ( 1, 2, 26)
5654 22:59:30.300245 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5655 22:59:30.306206 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5656 22:59:30.306700
5657 22:59:30.309915 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5658 22:59:30.313029 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5659 22:59:30.316351 [Gating] SW calibration Done
5660 22:59:30.316751 ==
5661 22:59:30.319554 Dram Type= 6, Freq= 0, CH_1, rank 0
5662 22:59:30.322770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5663 22:59:30.323147 ==
5664 22:59:30.326352 RX Vref Scan: 0
5665 22:59:30.326746
5666 22:59:30.327059 RX Vref 0 -> 0, step: 1
5667 22:59:30.327381
5668 22:59:30.329301 RX Delay -80 -> 252, step: 8
5669 22:59:30.332729 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5670 22:59:30.339373 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5671 22:59:30.342398 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5672 22:59:30.345649 iDelay=208, Bit 3, Center 99 (0 ~ 199) 200
5673 22:59:30.349598 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5674 22:59:30.352328 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5675 22:59:30.355447 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5676 22:59:30.362372 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5677 22:59:30.365701 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5678 22:59:30.368557 iDelay=208, Bit 9, Center 87 (-8 ~ 183) 192
5679 22:59:30.371976 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5680 22:59:30.375252 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5681 22:59:30.381906 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5682 22:59:30.385266 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5683 22:59:30.388641 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5684 22:59:30.391463 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5685 22:59:30.391868 ==
5686 22:59:30.395212 Dram Type= 6, Freq= 0, CH_1, rank 0
5687 22:59:30.401562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5688 22:59:30.401981 ==
5689 22:59:30.402390 DQS Delay:
5690 22:59:30.402725 DQS0 = 0, DQS1 = 0
5691 22:59:30.404955 DQM Delay:
5692 22:59:30.405397 DQM0 = 100, DQM1 = 95
5693 22:59:30.408293 DQ Delay:
5694 22:59:30.411762 DQ0 =103, DQ1 =95, DQ2 =91, DQ3 =99
5695 22:59:30.414977 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =95
5696 22:59:30.418249 DQ8 =83, DQ9 =87, DQ10 =95, DQ11 =87
5697 22:59:30.421312 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5698 22:59:30.421738
5699 22:59:30.422071
5700 22:59:30.422379 ==
5701 22:59:30.424775 Dram Type= 6, Freq= 0, CH_1, rank 0
5702 22:59:30.427977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5703 22:59:30.428468 ==
5704 22:59:30.428806
5705 22:59:30.429121
5706 22:59:30.431367 TX Vref Scan disable
5707 22:59:30.434440 == TX Byte 0 ==
5708 22:59:30.438119 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5709 22:59:30.441397 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5710 22:59:30.444671 == TX Byte 1 ==
5711 22:59:30.448248 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5712 22:59:30.451572 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5713 22:59:30.451992 ==
5714 22:59:30.454502 Dram Type= 6, Freq= 0, CH_1, rank 0
5715 22:59:30.460822 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5716 22:59:30.461247 ==
5717 22:59:30.461581
5718 22:59:30.461895
5719 22:59:30.462195 TX Vref Scan disable
5720 22:59:30.465034 == TX Byte 0 ==
5721 22:59:30.468337 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5722 22:59:30.475006 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5723 22:59:30.475430 == TX Byte 1 ==
5724 22:59:30.478459 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5725 22:59:30.484597 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5726 22:59:30.485025
5727 22:59:30.485357 [DATLAT]
5728 22:59:30.485668 Freq=933, CH1 RK0
5729 22:59:30.485975
5730 22:59:30.488245 DATLAT Default: 0xd
5731 22:59:30.488669 0, 0xFFFF, sum = 0
5732 22:59:30.491352 1, 0xFFFF, sum = 0
5733 22:59:30.494685 2, 0xFFFF, sum = 0
5734 22:59:30.495112 3, 0xFFFF, sum = 0
5735 22:59:30.498095 4, 0xFFFF, sum = 0
5736 22:59:30.498523 5, 0xFFFF, sum = 0
5737 22:59:30.501138 6, 0xFFFF, sum = 0
5738 22:59:30.501568 7, 0xFFFF, sum = 0
5739 22:59:30.504574 8, 0xFFFF, sum = 0
5740 22:59:30.505003 9, 0xFFFF, sum = 0
5741 22:59:30.507750 10, 0x0, sum = 1
5742 22:59:30.508210 11, 0x0, sum = 2
5743 22:59:30.511127 12, 0x0, sum = 3
5744 22:59:30.511559 13, 0x0, sum = 4
5745 22:59:30.514517 best_step = 11
5746 22:59:30.514939
5747 22:59:30.515272 ==
5748 22:59:30.517894 Dram Type= 6, Freq= 0, CH_1, rank 0
5749 22:59:30.521343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5750 22:59:30.521768 ==
5751 22:59:30.522102 RX Vref Scan: 1
5752 22:59:30.524177
5753 22:59:30.524599 RX Vref 0 -> 0, step: 1
5754 22:59:30.524937
5755 22:59:30.527905 RX Delay -53 -> 252, step: 4
5756 22:59:30.528397
5757 22:59:30.530979 Set Vref, RX VrefLevel [Byte0]: 52
5758 22:59:30.534058 [Byte1]: 51
5759 22:59:30.538218
5760 22:59:30.538646 Final RX Vref Byte 0 = 52 to rank0
5761 22:59:30.540809 Final RX Vref Byte 1 = 51 to rank0
5762 22:59:30.544294 Final RX Vref Byte 0 = 52 to rank1
5763 22:59:30.547245 Final RX Vref Byte 1 = 51 to rank1==
5764 22:59:30.550566 Dram Type= 6, Freq= 0, CH_1, rank 0
5765 22:59:30.557428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5766 22:59:30.557514 ==
5767 22:59:30.557580 DQS Delay:
5768 22:59:30.557641 DQS0 = 0, DQS1 = 0
5769 22:59:30.560625 DQM Delay:
5770 22:59:30.560707 DQM0 = 98, DQM1 = 94
5771 22:59:30.563845 DQ Delay:
5772 22:59:30.566947 DQ0 =102, DQ1 =92, DQ2 =88, DQ3 =98
5773 22:59:30.570201 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =92
5774 22:59:30.573888 DQ8 =80, DQ9 =84, DQ10 =94, DQ11 =88
5775 22:59:30.576801 DQ12 =102, DQ13 =102, DQ14 =100, DQ15 =104
5776 22:59:30.576883
5777 22:59:30.576947
5778 22:59:30.583416 [DQSOSCAuto] RK0, (LSB)MR18= 0x919, (MSB)MR19= 0x505, tDQSOscB0 = 413 ps tDQSOscB1 = 419 ps
5779 22:59:30.586918 CH1 RK0: MR19=505, MR18=919
5780 22:59:30.593475 CH1_RK0: MR19=0x505, MR18=0x919, DQSOSC=413, MR23=63, INC=63, DEC=42
5781 22:59:30.593557
5782 22:59:30.596705 ----->DramcWriteLeveling(PI) begin...
5783 22:59:30.596784 ==
5784 22:59:30.599954 Dram Type= 6, Freq= 0, CH_1, rank 1
5785 22:59:30.603480 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5786 22:59:30.603569 ==
5787 22:59:30.606819 Write leveling (Byte 0): 27 => 27
5788 22:59:30.609546 Write leveling (Byte 1): 27 => 27
5789 22:59:30.613210 DramcWriteLeveling(PI) end<-----
5790 22:59:30.613292
5791 22:59:30.613357 ==
5792 22:59:30.616357 Dram Type= 6, Freq= 0, CH_1, rank 1
5793 22:59:30.623100 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5794 22:59:30.623183 ==
5795 22:59:30.623248 [Gating] SW mode calibration
5796 22:59:30.632702 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5797 22:59:30.635788 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5798 22:59:30.639384 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5799 22:59:30.645764 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5800 22:59:30.649006 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5801 22:59:30.652596 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5802 22:59:30.659179 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5803 22:59:30.662610 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5804 22:59:30.668873 0 14 24 | B1->B0 | 3333 2f2f | 1 0 | (1 0) (0 0)
5805 22:59:30.672060 0 14 28 | B1->B0 | 2e2e 2323 | 0 0 | (1 0) (0 0)
5806 22:59:30.675467 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5807 22:59:30.682283 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5808 22:59:30.685204 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5809 22:59:30.688429 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5810 22:59:30.695205 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5811 22:59:30.698333 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5812 22:59:30.701656 0 15 24 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
5813 22:59:30.708339 0 15 28 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
5814 22:59:30.711844 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5815 22:59:30.715256 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5816 22:59:30.721287 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5817 22:59:30.724625 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5818 22:59:30.728218 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5819 22:59:30.734884 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5820 22:59:30.737671 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5821 22:59:30.741407 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5822 22:59:30.747998 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5823 22:59:30.751085 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5824 22:59:30.754330 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5825 22:59:30.760660 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5826 22:59:30.764290 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5827 22:59:30.767565 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5828 22:59:30.774002 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5829 22:59:30.777318 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5830 22:59:30.780375 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5831 22:59:30.787176 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5832 22:59:30.790094 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5833 22:59:30.793605 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5834 22:59:30.800270 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5835 22:59:30.803440 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5836 22:59:30.807314 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5837 22:59:30.810153 Total UI for P1: 0, mck2ui 16
5838 22:59:30.813560 best dqsien dly found for B0: ( 1, 2, 22)
5839 22:59:30.820286 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5840 22:59:30.823568 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5841 22:59:30.826919 Total UI for P1: 0, mck2ui 16
5842 22:59:30.829758 best dqsien dly found for B1: ( 1, 2, 26)
5843 22:59:30.833121 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5844 22:59:30.836614 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5845 22:59:30.836834
5846 22:59:30.839759 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5847 22:59:30.842970 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5848 22:59:30.846371 [Gating] SW calibration Done
5849 22:59:30.846608 ==
5850 22:59:30.849719 Dram Type= 6, Freq= 0, CH_1, rank 1
5851 22:59:30.856552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5852 22:59:30.856806 ==
5853 22:59:30.857004 RX Vref Scan: 0
5854 22:59:30.857187
5855 22:59:30.859705 RX Vref 0 -> 0, step: 1
5856 22:59:30.860009
5857 22:59:30.862842 RX Delay -80 -> 252, step: 8
5858 22:59:30.866477 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5859 22:59:30.869601 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5860 22:59:30.873497 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5861 22:59:30.876316 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5862 22:59:30.882720 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5863 22:59:30.886228 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5864 22:59:30.889458 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5865 22:59:30.892518 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5866 22:59:30.896383 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5867 22:59:30.899122 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5868 22:59:30.905791 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5869 22:59:30.909223 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5870 22:59:30.912471 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5871 22:59:30.915643 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5872 22:59:30.919009 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5873 22:59:30.925424 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5874 22:59:30.925937 ==
5875 22:59:30.928664 Dram Type= 6, Freq= 0, CH_1, rank 1
5876 22:59:30.932266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5877 22:59:30.932706 ==
5878 22:59:30.933046 DQS Delay:
5879 22:59:30.935591 DQS0 = 0, DQS1 = 0
5880 22:59:30.936096 DQM Delay:
5881 22:59:30.938465 DQM0 = 97, DQM1 = 93
5882 22:59:30.939109 DQ Delay:
5883 22:59:30.941668 DQ0 =103, DQ1 =91, DQ2 =87, DQ3 =95
5884 22:59:30.944852 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =95
5885 22:59:30.948068 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87
5886 22:59:30.951682 DQ12 =103, DQ13 =103, DQ14 =95, DQ15 =99
5887 22:59:30.951798
5888 22:59:30.951893
5889 22:59:30.951983 ==
5890 22:59:30.954915 Dram Type= 6, Freq= 0, CH_1, rank 1
5891 22:59:30.961667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5892 22:59:30.961751 ==
5893 22:59:30.961846
5894 22:59:30.961907
5895 22:59:30.961966 TX Vref Scan disable
5896 22:59:30.965044 == TX Byte 0 ==
5897 22:59:30.967734 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5898 22:59:30.974712 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5899 22:59:30.974797 == TX Byte 1 ==
5900 22:59:30.977874 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5901 22:59:30.984628 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5902 22:59:30.984721 ==
5903 22:59:30.987700 Dram Type= 6, Freq= 0, CH_1, rank 1
5904 22:59:30.990879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5905 22:59:30.990963 ==
5906 22:59:30.991029
5907 22:59:30.991090
5908 22:59:30.994487 TX Vref Scan disable
5909 22:59:30.997723 == TX Byte 0 ==
5910 22:59:31.000812 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5911 22:59:31.004053 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5912 22:59:31.007427 == TX Byte 1 ==
5913 22:59:31.010765 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5914 22:59:31.013739 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5915 22:59:31.013822
5916 22:59:31.013887 [DATLAT]
5917 22:59:31.017136 Freq=933, CH1 RK1
5918 22:59:31.017220
5919 22:59:31.020482 DATLAT Default: 0xb
5920 22:59:31.020564 0, 0xFFFF, sum = 0
5921 22:59:31.023734 1, 0xFFFF, sum = 0
5922 22:59:31.023845 2, 0xFFFF, sum = 0
5923 22:59:31.027189 3, 0xFFFF, sum = 0
5924 22:59:31.027277 4, 0xFFFF, sum = 0
5925 22:59:31.030688 5, 0xFFFF, sum = 0
5926 22:59:31.030767 6, 0xFFFF, sum = 0
5927 22:59:31.033706 7, 0xFFFF, sum = 0
5928 22:59:31.033782 8, 0xFFFF, sum = 0
5929 22:59:31.036867 9, 0xFFFF, sum = 0
5930 22:59:31.036938 10, 0x0, sum = 1
5931 22:59:31.040003 11, 0x0, sum = 2
5932 22:59:31.040113 12, 0x0, sum = 3
5933 22:59:31.043472 13, 0x0, sum = 4
5934 22:59:31.043545 best_step = 11
5935 22:59:31.043605
5936 22:59:31.043663 ==
5937 22:59:31.046731 Dram Type= 6, Freq= 0, CH_1, rank 1
5938 22:59:31.053446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5939 22:59:31.053531 ==
5940 22:59:31.053596 RX Vref Scan: 0
5941 22:59:31.053658
5942 22:59:31.056298 RX Vref 0 -> 0, step: 1
5943 22:59:31.056380
5944 22:59:31.059708 RX Delay -53 -> 252, step: 4
5945 22:59:31.063058 iDelay=199, Bit 0, Center 102 (11 ~ 194) 184
5946 22:59:31.066419 iDelay=199, Bit 1, Center 94 (-1 ~ 190) 192
5947 22:59:31.072733 iDelay=199, Bit 2, Center 88 (-5 ~ 182) 188
5948 22:59:31.075963 iDelay=199, Bit 3, Center 92 (-1 ~ 186) 188
5949 22:59:31.079233 iDelay=199, Bit 4, Center 96 (3 ~ 190) 188
5950 22:59:31.082726 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5951 22:59:31.085843 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5952 22:59:31.092913 iDelay=199, Bit 7, Center 94 (-1 ~ 190) 192
5953 22:59:31.096008 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5954 22:59:31.099662 iDelay=199, Bit 9, Center 84 (-5 ~ 174) 180
5955 22:59:31.102687 iDelay=199, Bit 10, Center 92 (-1 ~ 186) 188
5956 22:59:31.105772 iDelay=199, Bit 11, Center 86 (-5 ~ 178) 184
5957 22:59:31.112571 iDelay=199, Bit 12, Center 100 (11 ~ 190) 180
5958 22:59:31.115732 iDelay=199, Bit 13, Center 100 (11 ~ 190) 180
5959 22:59:31.119004 iDelay=199, Bit 14, Center 96 (7 ~ 186) 180
5960 22:59:31.122333 iDelay=199, Bit 15, Center 102 (11 ~ 194) 184
5961 22:59:31.122419 ==
5962 22:59:31.125710 Dram Type= 6, Freq= 0, CH_1, rank 1
5963 22:59:31.131896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5964 22:59:31.132009 ==
5965 22:59:31.132105 DQS Delay:
5966 22:59:31.132176 DQS0 = 0, DQS1 = 0
5967 22:59:31.135199 DQM Delay:
5968 22:59:31.135285 DQM0 = 97, DQM1 = 92
5969 22:59:31.138715 DQ Delay:
5970 22:59:31.142100 DQ0 =102, DQ1 =94, DQ2 =88, DQ3 =92
5971 22:59:31.145419 DQ4 =96, DQ5 =106, DQ6 =104, DQ7 =94
5972 22:59:31.148772 DQ8 =80, DQ9 =84, DQ10 =92, DQ11 =86
5973 22:59:31.152090 DQ12 =100, DQ13 =100, DQ14 =96, DQ15 =102
5974 22:59:31.152209
5975 22:59:31.152317
5976 22:59:31.158344 [DQSOSCAuto] RK1, (LSB)MR18= 0xb22, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 418 ps
5977 22:59:31.161834 CH1 RK1: MR19=505, MR18=B22
5978 22:59:31.168471 CH1_RK1: MR19=0x505, MR18=0xB22, DQSOSC=411, MR23=63, INC=64, DEC=42
5979 22:59:31.171694 [RxdqsGatingPostProcess] freq 933
5980 22:59:31.174887 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5981 22:59:31.178251 best DQS0 dly(2T, 0.5T) = (0, 10)
5982 22:59:31.181584 best DQS1 dly(2T, 0.5T) = (0, 10)
5983 22:59:31.184727 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5984 22:59:31.187914 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5985 22:59:31.191683 best DQS0 dly(2T, 0.5T) = (0, 10)
5986 22:59:31.194907 best DQS1 dly(2T, 0.5T) = (0, 10)
5987 22:59:31.198131 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5988 22:59:31.201061 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5989 22:59:31.204567 Pre-setting of DQS Precalculation
5990 22:59:31.211381 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5991 22:59:31.217719 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5992 22:59:31.224121 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5993 22:59:31.224221
5994 22:59:31.224320
5995 22:59:31.227908 [Calibration Summary] 1866 Mbps
5996 22:59:31.228020 CH 0, Rank 0
5997 22:59:31.230602 SW Impedance : PASS
5998 22:59:31.234131 DUTY Scan : NO K
5999 22:59:31.234234 ZQ Calibration : PASS
6000 22:59:31.237367 Jitter Meter : NO K
6001 22:59:31.240815 CBT Training : PASS
6002 22:59:31.240923 Write leveling : PASS
6003 22:59:31.244025 RX DQS gating : PASS
6004 22:59:31.244145 RX DQ/DQS(RDDQC) : PASS
6005 22:59:31.247360 TX DQ/DQS : PASS
6006 22:59:31.250685 RX DATLAT : PASS
6007 22:59:31.250811 RX DQ/DQS(Engine): PASS
6008 22:59:31.254186 TX OE : NO K
6009 22:59:31.254297 All Pass.
6010 22:59:31.254390
6011 22:59:31.257358 CH 0, Rank 1
6012 22:59:31.257442 SW Impedance : PASS
6013 22:59:31.260762 DUTY Scan : NO K
6014 22:59:31.263645 ZQ Calibration : PASS
6015 22:59:31.263729 Jitter Meter : NO K
6016 22:59:31.267483 CBT Training : PASS
6017 22:59:31.270198 Write leveling : PASS
6018 22:59:31.270282 RX DQS gating : PASS
6019 22:59:31.273403 RX DQ/DQS(RDDQC) : PASS
6020 22:59:31.276740 TX DQ/DQS : PASS
6021 22:59:31.276824 RX DATLAT : PASS
6022 22:59:31.280667 RX DQ/DQS(Engine): PASS
6023 22:59:31.283350 TX OE : NO K
6024 22:59:31.283434 All Pass.
6025 22:59:31.283499
6026 22:59:31.283561 CH 1, Rank 0
6027 22:59:31.287148 SW Impedance : PASS
6028 22:59:31.290071 DUTY Scan : NO K
6029 22:59:31.290155 ZQ Calibration : PASS
6030 22:59:31.293832 Jitter Meter : NO K
6031 22:59:31.296750 CBT Training : PASS
6032 22:59:31.296834 Write leveling : PASS
6033 22:59:31.299862 RX DQS gating : PASS
6034 22:59:31.303318 RX DQ/DQS(RDDQC) : PASS
6035 22:59:31.303402 TX DQ/DQS : PASS
6036 22:59:31.306499 RX DATLAT : PASS
6037 22:59:31.309692 RX DQ/DQS(Engine): PASS
6038 22:59:31.309774 TX OE : NO K
6039 22:59:31.313431 All Pass.
6040 22:59:31.313514
6041 22:59:31.313579 CH 1, Rank 1
6042 22:59:31.316414 SW Impedance : PASS
6043 22:59:31.316496 DUTY Scan : NO K
6044 22:59:31.320189 ZQ Calibration : PASS
6045 22:59:31.323594 Jitter Meter : NO K
6046 22:59:31.323676 CBT Training : PASS
6047 22:59:31.326556 Write leveling : PASS
6048 22:59:31.326639 RX DQS gating : PASS
6049 22:59:31.329958 RX DQ/DQS(RDDQC) : PASS
6050 22:59:31.333094 TX DQ/DQS : PASS
6051 22:59:31.333177 RX DATLAT : PASS
6052 22:59:31.336358 RX DQ/DQS(Engine): PASS
6053 22:59:31.339774 TX OE : NO K
6054 22:59:31.339902 All Pass.
6055 22:59:31.340018
6056 22:59:31.343116 DramC Write-DBI off
6057 22:59:31.343224 PER_BANK_REFRESH: Hybrid Mode
6058 22:59:31.346500 TX_TRACKING: ON
6059 22:59:31.355967 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6060 22:59:31.359301 [FAST_K] Save calibration result to emmc
6061 22:59:31.362566 dramc_set_vcore_voltage set vcore to 650000
6062 22:59:31.366029 Read voltage for 400, 6
6063 22:59:31.366111 Vio18 = 0
6064 22:59:31.366177 Vcore = 650000
6065 22:59:31.369254 Vdram = 0
6066 22:59:31.369337 Vddq = 0
6067 22:59:31.369402 Vmddr = 0
6068 22:59:31.376014 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6069 22:59:31.379343 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6070 22:59:31.382762 MEM_TYPE=3, freq_sel=20
6071 22:59:31.386022 sv_algorithm_assistance_LP4_800
6072 22:59:31.389203 ============ PULL DRAM RESETB DOWN ============
6073 22:59:31.392429 ========== PULL DRAM RESETB DOWN end =========
6074 22:59:31.399079 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6075 22:59:31.402155 ===================================
6076 22:59:31.402242 LPDDR4 DRAM CONFIGURATION
6077 22:59:31.405683 ===================================
6078 22:59:31.408794 EX_ROW_EN[0] = 0x0
6079 22:59:31.411880 EX_ROW_EN[1] = 0x0
6080 22:59:31.411962 LP4Y_EN = 0x0
6081 22:59:31.415582 WORK_FSP = 0x0
6082 22:59:31.415664 WL = 0x2
6083 22:59:31.418704 RL = 0x2
6084 22:59:31.418787 BL = 0x2
6085 22:59:31.421869 RPST = 0x0
6086 22:59:31.421951 RD_PRE = 0x0
6087 22:59:31.425395 WR_PRE = 0x1
6088 22:59:31.425477 WR_PST = 0x0
6089 22:59:31.428625 DBI_WR = 0x0
6090 22:59:31.428707 DBI_RD = 0x0
6091 22:59:31.431657 OTF = 0x1
6092 22:59:31.435282 ===================================
6093 22:59:31.438363 ===================================
6094 22:59:31.438446 ANA top config
6095 22:59:31.441466 ===================================
6096 22:59:31.444797 DLL_ASYNC_EN = 0
6097 22:59:31.448071 ALL_SLAVE_EN = 1
6098 22:59:31.451369 NEW_RANK_MODE = 1
6099 22:59:31.451452 DLL_IDLE_MODE = 1
6100 22:59:31.454802 LP45_APHY_COMB_EN = 1
6101 22:59:31.458267 TX_ODT_DIS = 1
6102 22:59:31.461580 NEW_8X_MODE = 1
6103 22:59:31.464864 ===================================
6104 22:59:31.467893 ===================================
6105 22:59:31.471138 data_rate = 800
6106 22:59:31.474604 CKR = 1
6107 22:59:31.474686 DQ_P2S_RATIO = 4
6108 22:59:31.477956 ===================================
6109 22:59:31.481249 CA_P2S_RATIO = 4
6110 22:59:31.484498 DQ_CA_OPEN = 0
6111 22:59:31.487676 DQ_SEMI_OPEN = 1
6112 22:59:31.491169 CA_SEMI_OPEN = 1
6113 22:59:31.494347 CA_FULL_RATE = 0
6114 22:59:31.494434 DQ_CKDIV4_EN = 0
6115 22:59:31.497599 CA_CKDIV4_EN = 1
6116 22:59:31.500938 CA_PREDIV_EN = 0
6117 22:59:31.504347 PH8_DLY = 0
6118 22:59:31.507210 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6119 22:59:31.510886 DQ_AAMCK_DIV = 0
6120 22:59:31.510967 CA_AAMCK_DIV = 0
6121 22:59:31.514223 CA_ADMCK_DIV = 4
6122 22:59:31.517507 DQ_TRACK_CA_EN = 0
6123 22:59:31.520262 CA_PICK = 800
6124 22:59:31.524045 CA_MCKIO = 400
6125 22:59:31.527126 MCKIO_SEMI = 400
6126 22:59:31.530456 PLL_FREQ = 3016
6127 22:59:31.533696 DQ_UI_PI_RATIO = 32
6128 22:59:31.536958 CA_UI_PI_RATIO = 32
6129 22:59:31.540416 ===================================
6130 22:59:31.543410 ===================================
6131 22:59:31.543513 memory_type:LPDDR4
6132 22:59:31.546970 GP_NUM : 10
6133 22:59:31.549939 SRAM_EN : 1
6134 22:59:31.550013 MD32_EN : 0
6135 22:59:31.553266 ===================================
6136 22:59:31.556568 [ANA_INIT] >>>>>>>>>>>>>>
6137 22:59:31.559926 <<<<<< [CONFIGURE PHASE]: ANA_TX
6138 22:59:31.563223 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6139 22:59:31.566652 ===================================
6140 22:59:31.569510 data_rate = 800,PCW = 0X7400
6141 22:59:31.572866 ===================================
6142 22:59:31.576110 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6143 22:59:31.579314 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6144 22:59:31.592435 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6145 22:59:31.595848 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6146 22:59:31.598948 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6147 22:59:31.602796 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6148 22:59:31.605746 [ANA_INIT] flow start
6149 22:59:31.608984 [ANA_INIT] PLL >>>>>>>>
6150 22:59:31.609065 [ANA_INIT] PLL <<<<<<<<
6151 22:59:31.612350 [ANA_INIT] MIDPI >>>>>>>>
6152 22:59:31.615824 [ANA_INIT] MIDPI <<<<<<<<
6153 22:59:31.615906 [ANA_INIT] DLL >>>>>>>>
6154 22:59:31.619107 [ANA_INIT] flow end
6155 22:59:31.622249 ============ LP4 DIFF to SE enter ============
6156 22:59:31.628678 ============ LP4 DIFF to SE exit ============
6157 22:59:31.628761 [ANA_INIT] <<<<<<<<<<<<<
6158 22:59:31.632261 [Flow] Enable top DCM control >>>>>
6159 22:59:31.635403 [Flow] Enable top DCM control <<<<<
6160 22:59:31.638620 Enable DLL master slave shuffle
6161 22:59:31.644914 ==============================================================
6162 22:59:31.644997 Gating Mode config
6163 22:59:31.651701 ==============================================================
6164 22:59:31.655046 Config description:
6165 22:59:31.664967 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6166 22:59:31.671574 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6167 22:59:31.674907 SELPH_MODE 0: By rank 1: By Phase
6168 22:59:31.681452 ==============================================================
6169 22:59:31.685084 GAT_TRACK_EN = 0
6170 22:59:31.687695 RX_GATING_MODE = 2
6171 22:59:31.687778 RX_GATING_TRACK_MODE = 2
6172 22:59:31.691482 SELPH_MODE = 1
6173 22:59:31.694617 PICG_EARLY_EN = 1
6174 22:59:31.697903 VALID_LAT_VALUE = 1
6175 22:59:31.704164 ==============================================================
6176 22:59:31.707811 Enter into Gating configuration >>>>
6177 22:59:31.711096 Exit from Gating configuration <<<<
6178 22:59:31.713950 Enter into DVFS_PRE_config >>>>>
6179 22:59:31.723968 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6180 22:59:31.727185 Exit from DVFS_PRE_config <<<<<
6181 22:59:31.730559 Enter into PICG configuration >>>>
6182 22:59:31.734033 Exit from PICG configuration <<<<
6183 22:59:31.737040 [RX_INPUT] configuration >>>>>
6184 22:59:31.740733 [RX_INPUT] configuration <<<<<
6185 22:59:31.743705 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6186 22:59:31.750457 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6187 22:59:31.757103 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6188 22:59:31.763674 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6189 22:59:31.770103 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6190 22:59:31.776785 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6191 22:59:31.780180 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6192 22:59:31.783463 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6193 22:59:31.786971 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6194 22:59:31.793590 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6195 22:59:31.796307 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6196 22:59:31.799581 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6197 22:59:31.803300 ===================================
6198 22:59:31.806504 LPDDR4 DRAM CONFIGURATION
6199 22:59:31.809621 ===================================
6200 22:59:31.809699 EX_ROW_EN[0] = 0x0
6201 22:59:31.812892 EX_ROW_EN[1] = 0x0
6202 22:59:31.816319 LP4Y_EN = 0x0
6203 22:59:31.816390 WORK_FSP = 0x0
6204 22:59:31.819801 WL = 0x2
6205 22:59:31.819871 RL = 0x2
6206 22:59:31.822493 BL = 0x2
6207 22:59:31.822563 RPST = 0x0
6208 22:59:31.826020 RD_PRE = 0x0
6209 22:59:31.826092 WR_PRE = 0x1
6210 22:59:31.829299 WR_PST = 0x0
6211 22:59:31.829369 DBI_WR = 0x0
6212 22:59:31.832749 DBI_RD = 0x0
6213 22:59:31.832820 OTF = 0x1
6214 22:59:31.836201 ===================================
6215 22:59:31.839014 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6216 22:59:31.846259 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6217 22:59:31.849074 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6218 22:59:31.852172 ===================================
6219 22:59:31.855438 LPDDR4 DRAM CONFIGURATION
6220 22:59:31.859150 ===================================
6221 22:59:31.859227 EX_ROW_EN[0] = 0x10
6222 22:59:31.862233 EX_ROW_EN[1] = 0x0
6223 22:59:31.865629 LP4Y_EN = 0x0
6224 22:59:31.865704 WORK_FSP = 0x0
6225 22:59:31.868645 WL = 0x2
6226 22:59:31.868755 RL = 0x2
6227 22:59:31.871943 BL = 0x2
6228 22:59:31.872087 RPST = 0x0
6229 22:59:31.875426 RD_PRE = 0x0
6230 22:59:31.875509 WR_PRE = 0x1
6231 22:59:31.878754 WR_PST = 0x0
6232 22:59:31.878862 DBI_WR = 0x0
6233 22:59:31.881571 DBI_RD = 0x0
6234 22:59:31.881653 OTF = 0x1
6235 22:59:31.884944 ===================================
6236 22:59:31.891769 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6237 22:59:31.896235 nWR fixed to 30
6238 22:59:31.899661 [ModeRegInit_LP4] CH0 RK0
6239 22:59:31.899744 [ModeRegInit_LP4] CH0 RK1
6240 22:59:31.902787 [ModeRegInit_LP4] CH1 RK0
6241 22:59:31.905984 [ModeRegInit_LP4] CH1 RK1
6242 22:59:31.906068 match AC timing 19
6243 22:59:31.912627 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6244 22:59:31.915951 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6245 22:59:31.919640 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6246 22:59:31.925661 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6247 22:59:31.929056 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6248 22:59:31.929139 ==
6249 22:59:31.932671 Dram Type= 6, Freq= 0, CH_0, rank 0
6250 22:59:31.935954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6251 22:59:31.936458 ==
6252 22:59:31.942461 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6253 22:59:31.949300 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6254 22:59:31.952730 [CA 0] Center 36 (8~64) winsize 57
6255 22:59:31.955940 [CA 1] Center 36 (8~64) winsize 57
6256 22:59:31.958998 [CA 2] Center 36 (8~64) winsize 57
6257 22:59:31.962681 [CA 3] Center 36 (8~64) winsize 57
6258 22:59:31.965954 [CA 4] Center 36 (8~64) winsize 57
6259 22:59:31.969040 [CA 5] Center 36 (8~64) winsize 57
6260 22:59:31.969487
6261 22:59:31.972482 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6262 22:59:31.972906
6263 22:59:31.975575 [CATrainingPosCal] consider 1 rank data
6264 22:59:31.978869 u2DelayCellTimex100 = 270/100 ps
6265 22:59:31.982197 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6266 22:59:31.985629 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6267 22:59:31.988662 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6268 22:59:31.992108 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6269 22:59:31.995502 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6270 22:59:31.998787 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6271 22:59:31.999207
6272 22:59:32.005564 CA PerBit enable=1, Macro0, CA PI delay=36
6273 22:59:32.005984
6274 22:59:32.006548 [CBTSetCACLKResult] CA Dly = 36
6275 22:59:32.008847 CS Dly: 1 (0~32)
6276 22:59:32.009287 ==
6277 22:59:32.012112 Dram Type= 6, Freq= 0, CH_0, rank 1
6278 22:59:32.015382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6279 22:59:32.015965 ==
6280 22:59:32.021953 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6281 22:59:32.028323 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6282 22:59:32.031991 [CA 0] Center 36 (8~64) winsize 57
6283 22:59:32.035391 [CA 1] Center 36 (8~64) winsize 57
6284 22:59:32.038244 [CA 2] Center 36 (8~64) winsize 57
6285 22:59:32.041578 [CA 3] Center 36 (8~64) winsize 57
6286 22:59:32.041988 [CA 4] Center 36 (8~64) winsize 57
6287 22:59:32.044834 [CA 5] Center 36 (8~64) winsize 57
6288 22:59:32.045286
6289 22:59:32.051695 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6290 22:59:32.052285
6291 22:59:32.054625 [CATrainingPosCal] consider 2 rank data
6292 22:59:32.057936 u2DelayCellTimex100 = 270/100 ps
6293 22:59:32.061104 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6294 22:59:32.064886 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6295 22:59:32.068151 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6296 22:59:32.071303 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6297 22:59:32.074741 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6298 22:59:32.077742 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6299 22:59:32.078217
6300 22:59:32.081128 CA PerBit enable=1, Macro0, CA PI delay=36
6301 22:59:32.081588
6302 22:59:32.084687 [CBTSetCACLKResult] CA Dly = 36
6303 22:59:32.087870 CS Dly: 1 (0~32)
6304 22:59:32.088417
6305 22:59:32.091433 ----->DramcWriteLeveling(PI) begin...
6306 22:59:32.091890 ==
6307 22:59:32.094335 Dram Type= 6, Freq= 0, CH_0, rank 0
6308 22:59:32.097565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6309 22:59:32.098172 ==
6310 22:59:32.100970 Write leveling (Byte 0): 40 => 8
6311 22:59:32.104147 Write leveling (Byte 1): 40 => 8
6312 22:59:32.107724 DramcWriteLeveling(PI) end<-----
6313 22:59:32.108361
6314 22:59:32.108935 ==
6315 22:59:32.110969 Dram Type= 6, Freq= 0, CH_0, rank 0
6316 22:59:32.114503 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6317 22:59:32.115018 ==
6318 22:59:32.117612 [Gating] SW mode calibration
6319 22:59:32.124194 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6320 22:59:32.130912 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6321 22:59:32.134305 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6322 22:59:32.140681 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6323 22:59:32.144112 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6324 22:59:32.147011 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6325 22:59:32.154159 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6326 22:59:32.156735 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6327 22:59:32.160203 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6328 22:59:32.166957 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6329 22:59:32.170236 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6330 22:59:32.173264 Total UI for P1: 0, mck2ui 16
6331 22:59:32.176520 best dqsien dly found for B0: ( 0, 14, 24)
6332 22:59:32.179773 Total UI for P1: 0, mck2ui 16
6333 22:59:32.182760 best dqsien dly found for B1: ( 0, 14, 24)
6334 22:59:32.186074 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6335 22:59:32.189610 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6336 22:59:32.189688
6337 22:59:32.192670 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6338 22:59:32.199171 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6339 22:59:32.199281 [Gating] SW calibration Done
6340 22:59:32.199388 ==
6341 22:59:32.202559 Dram Type= 6, Freq= 0, CH_0, rank 0
6342 22:59:32.209017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6343 22:59:32.209104 ==
6344 22:59:32.209170 RX Vref Scan: 0
6345 22:59:32.209231
6346 22:59:32.212379 RX Vref 0 -> 0, step: 1
6347 22:59:32.212461
6348 22:59:32.215765 RX Delay -410 -> 252, step: 16
6349 22:59:32.219062 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6350 22:59:32.222296 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6351 22:59:32.228795 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6352 22:59:32.232307 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6353 22:59:32.235688 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6354 22:59:32.238570 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6355 22:59:32.245295 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6356 22:59:32.248445 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6357 22:59:32.251735 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6358 22:59:32.255312 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6359 22:59:32.261537 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6360 22:59:32.265077 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6361 22:59:32.268372 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6362 22:59:32.274870 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6363 22:59:32.278184 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6364 22:59:32.281325 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6365 22:59:32.281443 ==
6366 22:59:32.284724 Dram Type= 6, Freq= 0, CH_0, rank 0
6367 22:59:32.287951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6368 22:59:32.291353 ==
6369 22:59:32.291453 DQS Delay:
6370 22:59:32.291536 DQS0 = 35, DQS1 = 59
6371 22:59:32.294613 DQM Delay:
6372 22:59:32.294714 DQM0 = 5, DQM1 = 16
6373 22:59:32.297665 DQ Delay:
6374 22:59:32.297772 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6375 22:59:32.301397 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6376 22:59:32.304285 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6377 22:59:32.307945 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6378 22:59:32.308076
6379 22:59:32.308177
6380 22:59:32.310912 ==
6381 22:59:32.311053 Dram Type= 6, Freq= 0, CH_0, rank 0
6382 22:59:32.317645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6383 22:59:32.317757 ==
6384 22:59:32.317848
6385 22:59:32.317938
6386 22:59:32.320979 TX Vref Scan disable
6387 22:59:32.321076 == TX Byte 0 ==
6388 22:59:32.324261 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6389 22:59:32.330810 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6390 22:59:32.330911 == TX Byte 1 ==
6391 22:59:32.334243 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6392 22:59:32.340505 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6393 22:59:32.340580 ==
6394 22:59:32.343806 Dram Type= 6, Freq= 0, CH_0, rank 0
6395 22:59:32.347213 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6396 22:59:32.347284 ==
6397 22:59:32.347352
6398 22:59:32.347439
6399 22:59:32.350324 TX Vref Scan disable
6400 22:59:32.350430 == TX Byte 0 ==
6401 22:59:32.353724 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6402 22:59:32.360622 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6403 22:59:32.360735 == TX Byte 1 ==
6404 22:59:32.364028 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6405 22:59:32.370101 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6406 22:59:32.370203
6407 22:59:32.370303 [DATLAT]
6408 22:59:32.370394 Freq=400, CH0 RK0
6409 22:59:32.373500
6410 22:59:32.373597 DATLAT Default: 0xf
6411 22:59:32.377256 0, 0xFFFF, sum = 0
6412 22:59:32.377353 1, 0xFFFF, sum = 0
6413 22:59:32.380402 2, 0xFFFF, sum = 0
6414 22:59:32.380506 3, 0xFFFF, sum = 0
6415 22:59:32.383940 4, 0xFFFF, sum = 0
6416 22:59:32.384095 5, 0xFFFF, sum = 0
6417 22:59:32.386924 6, 0xFFFF, sum = 0
6418 22:59:32.387033 7, 0xFFFF, sum = 0
6419 22:59:32.390187 8, 0xFFFF, sum = 0
6420 22:59:32.390291 9, 0xFFFF, sum = 0
6421 22:59:32.393393 10, 0xFFFF, sum = 0
6422 22:59:32.393495 11, 0xFFFF, sum = 0
6423 22:59:32.396630 12, 0xFFFF, sum = 0
6424 22:59:32.396739 13, 0x0, sum = 1
6425 22:59:32.399938 14, 0x0, sum = 2
6426 22:59:32.400065 15, 0x0, sum = 3
6427 22:59:32.403833 16, 0x0, sum = 4
6428 22:59:32.403964 best_step = 14
6429 22:59:32.404083
6430 22:59:32.404173 ==
6431 22:59:32.406982 Dram Type= 6, Freq= 0, CH_0, rank 0
6432 22:59:32.413313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6433 22:59:32.413427 ==
6434 22:59:32.413534 RX Vref Scan: 1
6435 22:59:32.413650
6436 22:59:32.416507 RX Vref 0 -> 0, step: 1
6437 22:59:32.416618
6438 22:59:32.419763 RX Delay -359 -> 252, step: 8
6439 22:59:32.419867
6440 22:59:32.423073 Set Vref, RX VrefLevel [Byte0]: 53
6441 22:59:32.426478 [Byte1]: 58
6442 22:59:32.426601
6443 22:59:32.429801 Final RX Vref Byte 0 = 53 to rank0
6444 22:59:32.433141 Final RX Vref Byte 1 = 58 to rank0
6445 22:59:32.436387 Final RX Vref Byte 0 = 53 to rank1
6446 22:59:32.440239 Final RX Vref Byte 1 = 58 to rank1==
6447 22:59:32.442972 Dram Type= 6, Freq= 0, CH_0, rank 0
6448 22:59:32.446416 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6449 22:59:32.450120 ==
6450 22:59:32.450236 DQS Delay:
6451 22:59:32.450337 DQS0 = 44, DQS1 = 60
6452 22:59:32.452985 DQM Delay:
6453 22:59:32.453093 DQM0 = 10, DQM1 = 15
6454 22:59:32.456458 DQ Delay:
6455 22:59:32.459943 DQ0 =12, DQ1 =12, DQ2 =4, DQ3 =4
6456 22:59:32.460065 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6457 22:59:32.463028 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6458 22:59:32.466425 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6459 22:59:32.466537
6460 22:59:32.469438
6461 22:59:32.476331 [DQSOSCAuto] RK0, (LSB)MR18= 0x9a8d, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 390 ps
6462 22:59:32.479288 CH0 RK0: MR19=C0C, MR18=9A8D
6463 22:59:32.485928 CH0_RK0: MR19=0xC0C, MR18=0x9A8D, DQSOSC=390, MR23=63, INC=388, DEC=258
6464 22:59:32.486047 ==
6465 22:59:32.489328 Dram Type= 6, Freq= 0, CH_0, rank 1
6466 22:59:32.492671 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6467 22:59:32.492786 ==
6468 22:59:32.495585 [Gating] SW mode calibration
6469 22:59:32.502344 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6470 22:59:32.508824 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6471 22:59:32.512549 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6472 22:59:32.515680 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6473 22:59:32.522022 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6474 22:59:32.525282 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6475 22:59:32.528674 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6476 22:59:32.535059 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6477 22:59:32.538407 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6478 22:59:32.541695 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6479 22:59:32.548092 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6480 22:59:32.551430 Total UI for P1: 0, mck2ui 16
6481 22:59:32.554793 best dqsien dly found for B0: ( 0, 14, 24)
6482 22:59:32.558063 Total UI for P1: 0, mck2ui 16
6483 22:59:32.561272 best dqsien dly found for B1: ( 0, 14, 24)
6484 22:59:32.564750 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6485 22:59:32.568154 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6486 22:59:32.568236
6487 22:59:32.571417 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6488 22:59:32.574809 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6489 22:59:32.577524 [Gating] SW calibration Done
6490 22:59:32.577606 ==
6491 22:59:32.580963 Dram Type= 6, Freq= 0, CH_0, rank 1
6492 22:59:32.584263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6493 22:59:32.584347 ==
6494 22:59:32.587636 RX Vref Scan: 0
6495 22:59:32.587717
6496 22:59:32.590994 RX Vref 0 -> 0, step: 1
6497 22:59:32.591075
6498 22:59:32.594540 RX Delay -410 -> 252, step: 16
6499 22:59:32.597852 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6500 22:59:32.600699 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6501 22:59:32.603902 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6502 22:59:32.610756 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6503 22:59:32.613785 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6504 22:59:32.617284 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6505 22:59:32.620439 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6506 22:59:32.626701 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6507 22:59:32.630144 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6508 22:59:32.633332 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6509 22:59:32.639863 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6510 22:59:32.643123 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6511 22:59:32.646483 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6512 22:59:32.649977 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6513 22:59:32.656637 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6514 22:59:32.659993 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6515 22:59:32.660108 ==
6516 22:59:32.662751 Dram Type= 6, Freq= 0, CH_0, rank 1
6517 22:59:32.666063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6518 22:59:32.666144 ==
6519 22:59:32.669669 DQS Delay:
6520 22:59:32.669744 DQS0 = 35, DQS1 = 51
6521 22:59:32.672805 DQM Delay:
6522 22:59:32.672878 DQM0 = 6, DQM1 = 10
6523 22:59:32.672941 DQ Delay:
6524 22:59:32.676198 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6525 22:59:32.679614 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6526 22:59:32.682955 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6527 22:59:32.686232 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6528 22:59:32.686305
6529 22:59:32.686370
6530 22:59:32.686432 ==
6531 22:59:32.689469 Dram Type= 6, Freq= 0, CH_0, rank 1
6532 22:59:32.696155 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6533 22:59:32.696235 ==
6534 22:59:32.696303
6535 22:59:32.696365
6536 22:59:32.696426 TX Vref Scan disable
6537 22:59:32.699065 == TX Byte 0 ==
6538 22:59:32.702432 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6539 22:59:32.706046 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6540 22:59:32.709054 == TX Byte 1 ==
6541 22:59:32.712289 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6542 22:59:32.715739 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6543 22:59:32.715849 ==
6544 22:59:32.719292 Dram Type= 6, Freq= 0, CH_0, rank 1
6545 22:59:32.725316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6546 22:59:32.725429 ==
6547 22:59:32.725529
6548 22:59:32.725623
6549 22:59:32.728924 TX Vref Scan disable
6550 22:59:32.728999 == TX Byte 0 ==
6551 22:59:32.731921 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6552 22:59:32.738729 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6553 22:59:32.738811 == TX Byte 1 ==
6554 22:59:32.741686 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6555 22:59:32.748717 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6556 22:59:32.748797
6557 22:59:32.748862 [DATLAT]
6558 22:59:32.748925 Freq=400, CH0 RK1
6559 22:59:32.748987
6560 22:59:32.751932 DATLAT Default: 0xe
6561 22:59:32.752021 0, 0xFFFF, sum = 0
6562 22:59:32.754785 1, 0xFFFF, sum = 0
6563 22:59:32.758307 2, 0xFFFF, sum = 0
6564 22:59:32.758390 3, 0xFFFF, sum = 0
6565 22:59:32.761558 4, 0xFFFF, sum = 0
6566 22:59:32.761630 5, 0xFFFF, sum = 0
6567 22:59:32.765249 6, 0xFFFF, sum = 0
6568 22:59:32.765322 7, 0xFFFF, sum = 0
6569 22:59:32.768024 8, 0xFFFF, sum = 0
6570 22:59:32.768123 9, 0xFFFF, sum = 0
6571 22:59:32.771359 10, 0xFFFF, sum = 0
6572 22:59:32.771432 11, 0xFFFF, sum = 0
6573 22:59:32.774802 12, 0xFFFF, sum = 0
6574 22:59:32.774875 13, 0x0, sum = 1
6575 22:59:32.778097 14, 0x0, sum = 2
6576 22:59:32.778168 15, 0x0, sum = 3
6577 22:59:32.781633 16, 0x0, sum = 4
6578 22:59:32.781704 best_step = 14
6579 22:59:32.781766
6580 22:59:32.781825 ==
6581 22:59:32.784513 Dram Type= 6, Freq= 0, CH_0, rank 1
6582 22:59:32.790947 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6583 22:59:32.791023 ==
6584 22:59:32.791089 RX Vref Scan: 0
6585 22:59:32.791150
6586 22:59:32.794395 RX Vref 0 -> 0, step: 1
6587 22:59:32.794470
6588 22:59:32.797665 RX Delay -343 -> 252, step: 8
6589 22:59:32.804421 iDelay=209, Bit 0, Center -36 (-271 ~ 200) 472
6590 22:59:32.807734 iDelay=209, Bit 1, Center -32 (-271 ~ 208) 480
6591 22:59:32.810944 iDelay=209, Bit 2, Center -40 (-279 ~ 200) 480
6592 22:59:32.814189 iDelay=209, Bit 3, Center -40 (-279 ~ 200) 480
6593 22:59:32.821086 iDelay=209, Bit 4, Center -32 (-271 ~ 208) 480
6594 22:59:32.824333 iDelay=209, Bit 5, Center -44 (-279 ~ 192) 472
6595 22:59:32.827452 iDelay=209, Bit 6, Center -28 (-263 ~ 208) 472
6596 22:59:32.830444 iDelay=209, Bit 7, Center -28 (-263 ~ 208) 472
6597 22:59:32.837821 iDelay=209, Bit 8, Center -56 (-303 ~ 192) 496
6598 22:59:32.840770 iDelay=209, Bit 9, Center -60 (-303 ~ 184) 488
6599 22:59:32.843898 iDelay=209, Bit 10, Center -44 (-287 ~ 200) 488
6600 22:59:32.847242 iDelay=209, Bit 11, Center -52 (-295 ~ 192) 488
6601 22:59:32.853772 iDelay=209, Bit 12, Center -36 (-279 ~ 208) 488
6602 22:59:32.856816 iDelay=209, Bit 13, Center -36 (-279 ~ 208) 488
6603 22:59:32.860171 iDelay=209, Bit 14, Center -36 (-279 ~ 208) 488
6604 22:59:32.866822 iDelay=209, Bit 15, Center -36 (-279 ~ 208) 488
6605 22:59:32.866899 ==
6606 22:59:32.870109 Dram Type= 6, Freq= 0, CH_0, rank 1
6607 22:59:32.873381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6608 22:59:32.873452 ==
6609 22:59:32.873517 DQS Delay:
6610 22:59:32.876899 DQS0 = 44, DQS1 = 60
6611 22:59:32.876967 DQM Delay:
6612 22:59:32.880428 DQM0 = 9, DQM1 = 15
6613 22:59:32.880495 DQ Delay:
6614 22:59:32.883130 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =4
6615 22:59:32.886416 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6616 22:59:32.889716 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6617 22:59:32.893192 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6618 22:59:32.893264
6619 22:59:32.893329
6620 22:59:32.899719 [DQSOSCAuto] RK1, (LSB)MR18= 0x8880, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 392 ps
6621 22:59:32.903070 CH0 RK1: MR19=C0C, MR18=8880
6622 22:59:32.909782 CH0_RK1: MR19=0xC0C, MR18=0x8880, DQSOSC=392, MR23=63, INC=384, DEC=256
6623 22:59:32.913154 [RxdqsGatingPostProcess] freq 400
6624 22:59:32.919287 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6625 22:59:32.922644 best DQS0 dly(2T, 0.5T) = (0, 10)
6626 22:59:32.926363 best DQS1 dly(2T, 0.5T) = (0, 10)
6627 22:59:32.929455 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6628 22:59:32.933058 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6629 22:59:32.933144 best DQS0 dly(2T, 0.5T) = (0, 10)
6630 22:59:32.935849 best DQS1 dly(2T, 0.5T) = (0, 10)
6631 22:59:32.939283 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6632 22:59:32.942549 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6633 22:59:32.945670 Pre-setting of DQS Precalculation
6634 22:59:32.952232 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6635 22:59:32.952341 ==
6636 22:59:32.955848 Dram Type= 6, Freq= 0, CH_1, rank 0
6637 22:59:32.958906 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6638 22:59:32.958990 ==
6639 22:59:32.965426 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6640 22:59:32.972358 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6641 22:59:32.975213 [CA 0] Center 36 (8~64) winsize 57
6642 22:59:32.979001 [CA 1] Center 36 (8~64) winsize 57
6643 22:59:32.979104 [CA 2] Center 36 (8~64) winsize 57
6644 22:59:32.981683 [CA 3] Center 36 (8~64) winsize 57
6645 22:59:32.985041 [CA 4] Center 36 (8~64) winsize 57
6646 22:59:32.988547 [CA 5] Center 36 (8~64) winsize 57
6647 22:59:32.988632
6648 22:59:32.991744 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6649 22:59:32.995072
6650 22:59:32.998627 [CATrainingPosCal] consider 1 rank data
6651 22:59:33.001852 u2DelayCellTimex100 = 270/100 ps
6652 22:59:33.005000 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6653 22:59:33.008464 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6654 22:59:33.011363 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6655 22:59:33.014715 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6656 22:59:33.018700 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6657 22:59:33.021621 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6658 22:59:33.021704
6659 22:59:33.025015 CA PerBit enable=1, Macro0, CA PI delay=36
6660 22:59:33.025098
6661 22:59:33.028362 [CBTSetCACLKResult] CA Dly = 36
6662 22:59:33.031779 CS Dly: 1 (0~32)
6663 22:59:33.031862 ==
6664 22:59:33.035160 Dram Type= 6, Freq= 0, CH_1, rank 1
6665 22:59:33.038189 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6666 22:59:33.038273 ==
6667 22:59:33.044767 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6668 22:59:33.051117 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6669 22:59:33.054311 [CA 0] Center 36 (8~64) winsize 57
6670 22:59:33.054394 [CA 1] Center 36 (8~64) winsize 57
6671 22:59:33.057764 [CA 2] Center 36 (8~64) winsize 57
6672 22:59:33.060754 [CA 3] Center 36 (8~64) winsize 57
6673 22:59:33.064014 [CA 4] Center 36 (8~64) winsize 57
6674 22:59:33.067665 [CA 5] Center 36 (8~64) winsize 57
6675 22:59:33.067774
6676 22:59:33.070551 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6677 22:59:33.070634
6678 22:59:33.077460 [CATrainingPosCal] consider 2 rank data
6679 22:59:33.077544 u2DelayCellTimex100 = 270/100 ps
6680 22:59:33.083752 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6681 22:59:33.087087 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6682 22:59:33.090327 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6683 22:59:33.093732 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6684 22:59:33.097046 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6685 22:59:33.100390 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6686 22:59:33.100473
6687 22:59:33.103770 CA PerBit enable=1, Macro0, CA PI delay=36
6688 22:59:33.103872
6689 22:59:33.107114 [CBTSetCACLKResult] CA Dly = 36
6690 22:59:33.110540 CS Dly: 1 (0~32)
6691 22:59:33.110641
6692 22:59:33.113265 ----->DramcWriteLeveling(PI) begin...
6693 22:59:33.113338 ==
6694 22:59:33.116663 Dram Type= 6, Freq= 0, CH_1, rank 0
6695 22:59:33.119971 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6696 22:59:33.120073 ==
6697 22:59:33.123455 Write leveling (Byte 0): 40 => 8
6698 22:59:33.126615 Write leveling (Byte 1): 40 => 8
6699 22:59:33.130043 DramcWriteLeveling(PI) end<-----
6700 22:59:33.130113
6701 22:59:33.130174 ==
6702 22:59:33.133329 Dram Type= 6, Freq= 0, CH_1, rank 0
6703 22:59:33.136640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6704 22:59:33.136710 ==
6705 22:59:33.139830 [Gating] SW mode calibration
6706 22:59:33.146328 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6707 22:59:33.153039 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6708 22:59:33.156293 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6709 22:59:33.162987 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6710 22:59:33.165908 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6711 22:59:33.169216 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6712 22:59:33.175792 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6713 22:59:33.179440 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6714 22:59:33.182693 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6715 22:59:33.189605 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6716 22:59:33.192215 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6717 22:59:33.195697 Total UI for P1: 0, mck2ui 16
6718 22:59:33.199197 best dqsien dly found for B0: ( 0, 14, 24)
6719 22:59:33.202183 Total UI for P1: 0, mck2ui 16
6720 22:59:33.205699 best dqsien dly found for B1: ( 0, 14, 24)
6721 22:59:33.209029 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6722 22:59:33.212357 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6723 22:59:33.212430
6724 22:59:33.215265 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6725 22:59:33.218831 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6726 22:59:33.222122 [Gating] SW calibration Done
6727 22:59:33.222195 ==
6728 22:59:33.225627 Dram Type= 6, Freq= 0, CH_1, rank 0
6729 22:59:33.228394 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6730 22:59:33.231746 ==
6731 22:59:33.231847 RX Vref Scan: 0
6732 22:59:33.231938
6733 22:59:33.235129 RX Vref 0 -> 0, step: 1
6734 22:59:33.235234
6735 22:59:33.238410 RX Delay -410 -> 252, step: 16
6736 22:59:33.241515 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6737 22:59:33.244768 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6738 22:59:33.248226 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6739 22:59:33.254805 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6740 22:59:33.258047 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6741 22:59:33.261236 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6742 22:59:33.264798 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6743 22:59:33.271779 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6744 22:59:33.274849 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6745 22:59:33.278392 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6746 22:59:33.284642 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6747 22:59:33.287922 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6748 22:59:33.291213 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6749 22:59:33.294717 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6750 22:59:33.301302 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6751 22:59:33.304738 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6752 22:59:33.304821 ==
6753 22:59:33.307680 Dram Type= 6, Freq= 0, CH_1, rank 0
6754 22:59:33.310990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6755 22:59:33.311072 ==
6756 22:59:33.314434 DQS Delay:
6757 22:59:33.314516 DQS0 = 35, DQS1 = 51
6758 22:59:33.317888 DQM Delay:
6759 22:59:33.317970 DQM0 = 6, DQM1 = 14
6760 22:59:33.318036 DQ Delay:
6761 22:59:33.321396 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6762 22:59:33.324088 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6763 22:59:33.327538 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6764 22:59:33.330740 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =16
6765 22:59:33.330822
6766 22:59:33.330887
6767 22:59:33.330947 ==
6768 22:59:33.333933 Dram Type= 6, Freq= 0, CH_1, rank 0
6769 22:59:33.340723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6770 22:59:33.340806 ==
6771 22:59:33.340871
6772 22:59:33.340932
6773 22:59:33.340990 TX Vref Scan disable
6774 22:59:33.343945 == TX Byte 0 ==
6775 22:59:33.347327 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6776 22:59:33.350674 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6777 22:59:33.353584 == TX Byte 1 ==
6778 22:59:33.357318 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6779 22:59:33.360823 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6780 22:59:33.360905 ==
6781 22:59:33.363906 Dram Type= 6, Freq= 0, CH_1, rank 0
6782 22:59:33.370628 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6783 22:59:33.370712 ==
6784 22:59:33.370777
6785 22:59:33.370838
6786 22:59:33.370896 TX Vref Scan disable
6787 22:59:33.373710 == TX Byte 0 ==
6788 22:59:33.376766 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6789 22:59:33.383565 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6790 22:59:33.383647 == TX Byte 1 ==
6791 22:59:33.386442 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6792 22:59:33.393176 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6793 22:59:33.393287
6794 22:59:33.393393 [DATLAT]
6795 22:59:33.393494 Freq=400, CH1 RK0
6796 22:59:33.393593
6797 22:59:33.396672 DATLAT Default: 0xf
6798 22:59:33.396749 0, 0xFFFF, sum = 0
6799 22:59:33.400131 1, 0xFFFF, sum = 0
6800 22:59:33.403363 2, 0xFFFF, sum = 0
6801 22:59:33.403514 3, 0xFFFF, sum = 0
6802 22:59:33.406695 4, 0xFFFF, sum = 0
6803 22:59:33.406800 5, 0xFFFF, sum = 0
6804 22:59:33.409986 6, 0xFFFF, sum = 0
6805 22:59:33.410181 7, 0xFFFF, sum = 0
6806 22:59:33.412793 8, 0xFFFF, sum = 0
6807 22:59:33.412897 9, 0xFFFF, sum = 0
6808 22:59:33.416126 10, 0xFFFF, sum = 0
6809 22:59:33.416203 11, 0xFFFF, sum = 0
6810 22:59:33.419385 12, 0xFFFF, sum = 0
6811 22:59:33.419484 13, 0x0, sum = 1
6812 22:59:33.422885 14, 0x0, sum = 2
6813 22:59:33.423074 15, 0x0, sum = 3
6814 22:59:33.426146 16, 0x0, sum = 4
6815 22:59:33.426291 best_step = 14
6816 22:59:33.426423
6817 22:59:33.426552 ==
6818 22:59:33.429079 Dram Type= 6, Freq= 0, CH_1, rank 0
6819 22:59:33.435757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6820 22:59:33.435863 ==
6821 22:59:33.435966 RX Vref Scan: 1
6822 22:59:33.436074
6823 22:59:33.439086 RX Vref 0 -> 0, step: 1
6824 22:59:33.439199
6825 22:59:33.442315 RX Delay -343 -> 252, step: 8
6826 22:59:33.442416
6827 22:59:33.445599 Set Vref, RX VrefLevel [Byte0]: 52
6828 22:59:33.449071 [Byte1]: 51
6829 22:59:33.449170
6830 22:59:33.452403 Final RX Vref Byte 0 = 52 to rank0
6831 22:59:33.455680 Final RX Vref Byte 1 = 51 to rank0
6832 22:59:33.459150 Final RX Vref Byte 0 = 52 to rank1
6833 22:59:33.462375 Final RX Vref Byte 1 = 51 to rank1==
6834 22:59:33.465424 Dram Type= 6, Freq= 0, CH_1, rank 0
6835 22:59:33.468874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6836 22:59:33.472118 ==
6837 22:59:33.472222 DQS Delay:
6838 22:59:33.472325 DQS0 = 44, DQS1 = 52
6839 22:59:33.475247 DQM Delay:
6840 22:59:33.475347 DQM0 = 11, DQM1 = 10
6841 22:59:33.478372 DQ Delay:
6842 22:59:33.482134 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6843 22:59:33.482236 DQ4 =8, DQ5 =16, DQ6 =24, DQ7 =4
6844 22:59:33.485235 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
6845 22:59:33.488707 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =16
6846 22:59:33.488810
6847 22:59:33.488918
6848 22:59:33.498230 [DQSOSCAuto] RK0, (LSB)MR18= 0x6288, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 397 ps
6849 22:59:33.502121 CH1 RK0: MR19=C0C, MR18=6288
6850 22:59:33.508337 CH1_RK0: MR19=0xC0C, MR18=0x6288, DQSOSC=392, MR23=63, INC=384, DEC=256
6851 22:59:33.508444 ==
6852 22:59:33.511800 Dram Type= 6, Freq= 0, CH_1, rank 1
6853 22:59:33.514914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6854 22:59:33.515017 ==
6855 22:59:33.518396 [Gating] SW mode calibration
6856 22:59:33.524752 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6857 22:59:33.531347 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6858 22:59:33.534594 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6859 22:59:33.538081 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6860 22:59:33.544525 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6861 22:59:33.547837 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6862 22:59:33.551348 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6863 22:59:33.557873 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6864 22:59:33.561365 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6865 22:59:33.564023 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6866 22:59:33.570744 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6867 22:59:33.570849 Total UI for P1: 0, mck2ui 16
6868 22:59:33.577230 best dqsien dly found for B0: ( 0, 14, 24)
6869 22:59:33.577346 Total UI for P1: 0, mck2ui 16
6870 22:59:33.583988 best dqsien dly found for B1: ( 0, 14, 24)
6871 22:59:33.587034 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6872 22:59:33.590738 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6873 22:59:33.590848
6874 22:59:33.593710 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6875 22:59:33.597013 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6876 22:59:33.600608 [Gating] SW calibration Done
6877 22:59:33.600714 ==
6878 22:59:33.603820 Dram Type= 6, Freq= 0, CH_1, rank 1
6879 22:59:33.607057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6880 22:59:33.607160 ==
6881 22:59:33.609930 RX Vref Scan: 0
6882 22:59:33.610029
6883 22:59:33.613291 RX Vref 0 -> 0, step: 1
6884 22:59:33.613393
6885 22:59:33.613488 RX Delay -410 -> 252, step: 16
6886 22:59:33.620232 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6887 22:59:33.623060 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6888 22:59:33.626513 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6889 22:59:33.632954 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6890 22:59:33.636333 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6891 22:59:33.639864 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6892 22:59:33.643177 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6893 22:59:33.649691 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6894 22:59:33.652867 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6895 22:59:33.656280 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6896 22:59:33.659473 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6897 22:59:33.666344 iDelay=230, Bit 11, Center -35 (-282 ~ 213) 496
6898 22:59:33.669574 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6899 22:59:33.672883 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6900 22:59:33.676389 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6901 22:59:33.682786 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6902 22:59:33.682869 ==
6903 22:59:33.686010 Dram Type= 6, Freq= 0, CH_1, rank 1
6904 22:59:33.689008 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6905 22:59:33.689091 ==
6906 22:59:33.689157 DQS Delay:
6907 22:59:33.692648 DQS0 = 43, DQS1 = 51
6908 22:59:33.692730 DQM Delay:
6909 22:59:33.695730 DQM0 = 10, DQM1 = 15
6910 22:59:33.695812 DQ Delay:
6911 22:59:33.699172 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6912 22:59:33.702245 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6913 22:59:33.705688 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6914 22:59:33.708738 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6915 22:59:33.708821
6916 22:59:33.708896
6917 22:59:33.708958 ==
6918 22:59:33.711880 Dram Type= 6, Freq= 0, CH_1, rank 1
6919 22:59:33.715401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6920 22:59:33.718641 ==
6921 22:59:33.718715
6922 22:59:33.718777
6923 22:59:33.718836 TX Vref Scan disable
6924 22:59:33.722166 == TX Byte 0 ==
6925 22:59:33.725371 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6926 22:59:33.728784 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6927 22:59:33.731534 == TX Byte 1 ==
6928 22:59:33.735367 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6929 22:59:33.738139 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6930 22:59:33.738210 ==
6931 22:59:33.741466 Dram Type= 6, Freq= 0, CH_1, rank 1
6932 22:59:33.748077 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6933 22:59:33.748160 ==
6934 22:59:33.748224
6935 22:59:33.748285
6936 22:59:33.748343 TX Vref Scan disable
6937 22:59:33.751452 == TX Byte 0 ==
6938 22:59:33.754542 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6939 22:59:33.757836 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6940 22:59:33.761296 == TX Byte 1 ==
6941 22:59:33.764414 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6942 22:59:33.767632 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6943 22:59:33.767714
6944 22:59:33.771008 [DATLAT]
6945 22:59:33.771090 Freq=400, CH1 RK1
6946 22:59:33.771156
6947 22:59:33.774425 DATLAT Default: 0xe
6948 22:59:33.774507 0, 0xFFFF, sum = 0
6949 22:59:33.777897 1, 0xFFFF, sum = 0
6950 22:59:33.777981 2, 0xFFFF, sum = 0
6951 22:59:33.781213 3, 0xFFFF, sum = 0
6952 22:59:33.781297 4, 0xFFFF, sum = 0
6953 22:59:33.784663 5, 0xFFFF, sum = 0
6954 22:59:33.787722 6, 0xFFFF, sum = 0
6955 22:59:33.787806 7, 0xFFFF, sum = 0
6956 22:59:33.791169 8, 0xFFFF, sum = 0
6957 22:59:33.791279 9, 0xFFFF, sum = 0
6958 22:59:33.794159 10, 0xFFFF, sum = 0
6959 22:59:33.794242 11, 0xFFFF, sum = 0
6960 22:59:33.797369 12, 0xFFFF, sum = 0
6961 22:59:33.797452 13, 0x0, sum = 1
6962 22:59:33.800377 14, 0x0, sum = 2
6963 22:59:33.800460 15, 0x0, sum = 3
6964 22:59:33.804231 16, 0x0, sum = 4
6965 22:59:33.804315 best_step = 14
6966 22:59:33.804379
6967 22:59:33.804439 ==
6968 22:59:33.807363 Dram Type= 6, Freq= 0, CH_1, rank 1
6969 22:59:33.810353 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6970 22:59:33.813907 ==
6971 22:59:33.813990 RX Vref Scan: 0
6972 22:59:33.814056
6973 22:59:33.817267 RX Vref 0 -> 0, step: 1
6974 22:59:33.817349
6975 22:59:33.820494 RX Delay -343 -> 252, step: 8
6976 22:59:33.827165 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6977 22:59:33.830587 iDelay=217, Bit 1, Center -40 (-287 ~ 208) 496
6978 22:59:33.833910 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6979 22:59:33.836758 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6980 22:59:33.843394 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6981 22:59:33.846745 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6982 22:59:33.850265 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6983 22:59:33.853111 iDelay=217, Bit 7, Center -40 (-287 ~ 208) 496
6984 22:59:33.859994 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6985 22:59:33.863525 iDelay=217, Bit 9, Center -52 (-295 ~ 192) 488
6986 22:59:33.866829 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
6987 22:59:33.869941 iDelay=217, Bit 11, Center -48 (-287 ~ 192) 480
6988 22:59:33.876191 iDelay=217, Bit 12, Center -32 (-271 ~ 208) 480
6989 22:59:33.879738 iDelay=217, Bit 13, Center -36 (-279 ~ 208) 488
6990 22:59:33.882609 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6991 22:59:33.889501 iDelay=217, Bit 15, Center -32 (-279 ~ 216) 496
6992 22:59:33.889574 ==
6993 22:59:33.892390 Dram Type= 6, Freq= 0, CH_1, rank 1
6994 22:59:33.895819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6995 22:59:33.895903 ==
6996 22:59:33.895986 DQS Delay:
6997 22:59:33.898938 DQS0 = 48, DQS1 = 52
6998 22:59:33.899019 DQM Delay:
6999 22:59:33.902646 DQM0 = 11, DQM1 = 11
7000 22:59:33.902728 DQ Delay:
7001 22:59:33.905709 DQ0 =12, DQ1 =8, DQ2 =0, DQ3 =8
7002 22:59:33.908995 DQ4 =12, DQ5 =20, DQ6 =20, DQ7 =8
7003 22:59:33.912515 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
7004 22:59:33.915633 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
7005 22:59:33.915716
7006 22:59:33.915781
7007 22:59:33.922156 [DQSOSCAuto] RK1, (LSB)MR18= 0x72aa, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps
7008 22:59:33.925465 CH1 RK1: MR19=C0C, MR18=72AA
7009 22:59:33.932049 CH1_RK1: MR19=0xC0C, MR18=0x72AA, DQSOSC=388, MR23=63, INC=392, DEC=261
7010 22:59:33.935598 [RxdqsGatingPostProcess] freq 400
7011 22:59:33.942267 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7012 22:59:33.945082 best DQS0 dly(2T, 0.5T) = (0, 10)
7013 22:59:33.948577 best DQS1 dly(2T, 0.5T) = (0, 10)
7014 22:59:33.951881 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7015 22:59:33.955368 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7016 22:59:33.955441 best DQS0 dly(2T, 0.5T) = (0, 10)
7017 22:59:33.958184 best DQS1 dly(2T, 0.5T) = (0, 10)
7018 22:59:33.961823 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7019 22:59:33.965040 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7020 22:59:33.968530 Pre-setting of DQS Precalculation
7021 22:59:33.974723 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7022 22:59:33.981525 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7023 22:59:33.988259 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7024 22:59:33.988346
7025 22:59:33.988411
7026 22:59:33.991392 [Calibration Summary] 800 Mbps
7027 22:59:33.994891 CH 0, Rank 0
7028 22:59:33.994973 SW Impedance : PASS
7029 22:59:33.997754 DUTY Scan : NO K
7030 22:59:33.997837 ZQ Calibration : PASS
7031 22:59:34.001393 Jitter Meter : NO K
7032 22:59:34.004703 CBT Training : PASS
7033 22:59:34.004786 Write leveling : PASS
7034 22:59:34.007773 RX DQS gating : PASS
7035 22:59:34.011103 RX DQ/DQS(RDDQC) : PASS
7036 22:59:34.011186 TX DQ/DQS : PASS
7037 22:59:34.014155 RX DATLAT : PASS
7038 22:59:34.017636 RX DQ/DQS(Engine): PASS
7039 22:59:34.017714 TX OE : NO K
7040 22:59:34.020917 All Pass.
7041 22:59:34.020996
7042 22:59:34.021062 CH 0, Rank 1
7043 22:59:34.023973 SW Impedance : PASS
7044 22:59:34.024081 DUTY Scan : NO K
7045 22:59:34.027484 ZQ Calibration : PASS
7046 22:59:34.030725 Jitter Meter : NO K
7047 22:59:34.030828 CBT Training : PASS
7048 22:59:34.034116 Write leveling : NO K
7049 22:59:34.037616 RX DQS gating : PASS
7050 22:59:34.037699 RX DQ/DQS(RDDQC) : PASS
7051 22:59:34.040878 TX DQ/DQS : PASS
7052 22:59:34.043794 RX DATLAT : PASS
7053 22:59:34.043903 RX DQ/DQS(Engine): PASS
7054 22:59:34.047042 TX OE : NO K
7055 22:59:34.047125 All Pass.
7056 22:59:34.047191
7057 22:59:34.050450 CH 1, Rank 0
7058 22:59:34.050533 SW Impedance : PASS
7059 22:59:34.053825 DUTY Scan : NO K
7060 22:59:34.057136 ZQ Calibration : PASS
7061 22:59:34.057237 Jitter Meter : NO K
7062 22:59:34.060674 CBT Training : PASS
7063 22:59:34.064183 Write leveling : PASS
7064 22:59:34.064268 RX DQS gating : PASS
7065 22:59:34.066746 RX DQ/DQS(RDDQC) : PASS
7066 22:59:34.066848 TX DQ/DQS : PASS
7067 22:59:34.070132 RX DATLAT : PASS
7068 22:59:34.073433 RX DQ/DQS(Engine): PASS
7069 22:59:34.073514 TX OE : NO K
7070 22:59:34.076533 All Pass.
7071 22:59:34.076613
7072 22:59:34.076676 CH 1, Rank 1
7073 22:59:34.080078 SW Impedance : PASS
7074 22:59:34.083377 DUTY Scan : NO K
7075 22:59:34.083451 ZQ Calibration : PASS
7076 22:59:34.086687 Jitter Meter : NO K
7077 22:59:34.086759 CBT Training : PASS
7078 22:59:34.090048 Write leveling : NO K
7079 22:59:34.093512 RX DQS gating : PASS
7080 22:59:34.093587 RX DQ/DQS(RDDQC) : PASS
7081 22:59:34.096229 TX DQ/DQS : PASS
7082 22:59:34.099766 RX DATLAT : PASS
7083 22:59:34.099849 RX DQ/DQS(Engine): PASS
7084 22:59:34.102873 TX OE : NO K
7085 22:59:34.102946 All Pass.
7086 22:59:34.103016
7087 22:59:34.106040 DramC Write-DBI off
7088 22:59:34.109833 PER_BANK_REFRESH: Hybrid Mode
7089 22:59:34.109919 TX_TRACKING: ON
7090 22:59:34.119319 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7091 22:59:34.122845 [FAST_K] Save calibration result to emmc
7092 22:59:34.126147 dramc_set_vcore_voltage set vcore to 725000
7093 22:59:34.129142 Read voltage for 1600, 0
7094 22:59:34.129215 Vio18 = 0
7095 22:59:34.132619 Vcore = 725000
7096 22:59:34.132690 Vdram = 0
7097 22:59:34.132752 Vddq = 0
7098 22:59:34.132820 Vmddr = 0
7099 22:59:34.139103 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7100 22:59:34.145683 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7101 22:59:34.145790 MEM_TYPE=3, freq_sel=13
7102 22:59:34.149247 sv_algorithm_assistance_LP4_3733
7103 22:59:34.152351 ============ PULL DRAM RESETB DOWN ============
7104 22:59:34.159068 ========== PULL DRAM RESETB DOWN end =========
7105 22:59:34.162296 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7106 22:59:34.165251 ===================================
7107 22:59:34.168557 LPDDR4 DRAM CONFIGURATION
7108 22:59:34.171969 ===================================
7109 22:59:34.172075 EX_ROW_EN[0] = 0x0
7110 22:59:34.175049 EX_ROW_EN[1] = 0x0
7111 22:59:34.178909 LP4Y_EN = 0x0
7112 22:59:34.179020 WORK_FSP = 0x1
7113 22:59:34.181706 WL = 0x5
7114 22:59:34.181803 RL = 0x5
7115 22:59:34.185119 BL = 0x2
7116 22:59:34.185216 RPST = 0x0
7117 22:59:34.188397 RD_PRE = 0x0
7118 22:59:34.188495 WR_PRE = 0x1
7119 22:59:34.191728 WR_PST = 0x1
7120 22:59:34.191824 DBI_WR = 0x0
7121 22:59:34.195162 DBI_RD = 0x0
7122 22:59:34.195259 OTF = 0x1
7123 22:59:34.197989 ===================================
7124 22:59:34.201428 ===================================
7125 22:59:34.204718 ANA top config
7126 22:59:34.207987 ===================================
7127 22:59:34.211500 DLL_ASYNC_EN = 0
7128 22:59:34.211583 ALL_SLAVE_EN = 0
7129 22:59:34.214752 NEW_RANK_MODE = 1
7130 22:59:34.217800 DLL_IDLE_MODE = 1
7131 22:59:34.221528 LP45_APHY_COMB_EN = 1
7132 22:59:34.221611 TX_ODT_DIS = 0
7133 22:59:34.224554 NEW_8X_MODE = 1
7134 22:59:34.228246 ===================================
7135 22:59:34.231157 ===================================
7136 22:59:34.234306 data_rate = 3200
7137 22:59:34.237874 CKR = 1
7138 22:59:34.241064 DQ_P2S_RATIO = 8
7139 22:59:34.244182 ===================================
7140 22:59:34.247605 CA_P2S_RATIO = 8
7141 22:59:34.247689 DQ_CA_OPEN = 0
7142 22:59:34.251172 DQ_SEMI_OPEN = 0
7143 22:59:34.254258 CA_SEMI_OPEN = 0
7144 22:59:34.257423 CA_FULL_RATE = 0
7145 22:59:34.260907 DQ_CKDIV4_EN = 0
7146 22:59:34.264254 CA_CKDIV4_EN = 0
7147 22:59:34.267609 CA_PREDIV_EN = 0
7148 22:59:34.267692 PH8_DLY = 12
7149 22:59:34.270992 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7150 22:59:34.274166 DQ_AAMCK_DIV = 4
7151 22:59:34.277486 CA_AAMCK_DIV = 4
7152 22:59:34.281038 CA_ADMCK_DIV = 4
7153 22:59:34.284376 DQ_TRACK_CA_EN = 0
7154 22:59:34.284460 CA_PICK = 1600
7155 22:59:34.287467 CA_MCKIO = 1600
7156 22:59:34.290739 MCKIO_SEMI = 0
7157 22:59:34.294423 PLL_FREQ = 3068
7158 22:59:34.297431 DQ_UI_PI_RATIO = 32
7159 22:59:34.300185 CA_UI_PI_RATIO = 0
7160 22:59:34.303558 ===================================
7161 22:59:34.307066 ===================================
7162 22:59:34.310258 memory_type:LPDDR4
7163 22:59:34.310341 GP_NUM : 10
7164 22:59:34.313566 SRAM_EN : 1
7165 22:59:34.313664 MD32_EN : 0
7166 22:59:34.316780 ===================================
7167 22:59:34.319887 [ANA_INIT] >>>>>>>>>>>>>>
7168 22:59:34.323690 <<<<<< [CONFIGURE PHASE]: ANA_TX
7169 22:59:34.326623 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7170 22:59:34.330023 ===================================
7171 22:59:34.333068 data_rate = 3200,PCW = 0X7600
7172 22:59:34.336641 ===================================
7173 22:59:34.339708 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7174 22:59:34.346420 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7175 22:59:34.349584 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7176 22:59:34.356471 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7177 22:59:34.359585 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7178 22:59:34.362791 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7179 22:59:34.362902 [ANA_INIT] flow start
7180 22:59:34.366341 [ANA_INIT] PLL >>>>>>>>
7181 22:59:34.369610 [ANA_INIT] PLL <<<<<<<<
7182 22:59:34.372660 [ANA_INIT] MIDPI >>>>>>>>
7183 22:59:34.372733 [ANA_INIT] MIDPI <<<<<<<<
7184 22:59:34.376224 [ANA_INIT] DLL >>>>>>>>
7185 22:59:34.379412 [ANA_INIT] DLL <<<<<<<<
7186 22:59:34.379483 [ANA_INIT] flow end
7187 22:59:34.382879 ============ LP4 DIFF to SE enter ============
7188 22:59:34.389349 ============ LP4 DIFF to SE exit ============
7189 22:59:34.389428 [ANA_INIT] <<<<<<<<<<<<<
7190 22:59:34.392754 [Flow] Enable top DCM control >>>>>
7191 22:59:34.396218 [Flow] Enable top DCM control <<<<<
7192 22:59:34.398937 Enable DLL master slave shuffle
7193 22:59:34.405783 ==============================================================
7194 22:59:34.409229 Gating Mode config
7195 22:59:34.411962 ==============================================================
7196 22:59:34.415466 Config description:
7197 22:59:34.425327 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7198 22:59:34.431701 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7199 22:59:34.435537 SELPH_MODE 0: By rank 1: By Phase
7200 22:59:34.441650 ==============================================================
7201 22:59:34.445194 GAT_TRACK_EN = 1
7202 22:59:34.448335 RX_GATING_MODE = 2
7203 22:59:34.451420 RX_GATING_TRACK_MODE = 2
7204 22:59:34.454963 SELPH_MODE = 1
7205 22:59:34.458014 PICG_EARLY_EN = 1
7206 22:59:34.458133 VALID_LAT_VALUE = 1
7207 22:59:34.464455 ==============================================================
7208 22:59:34.467805 Enter into Gating configuration >>>>
7209 22:59:34.471275 Exit from Gating configuration <<<<
7210 22:59:34.474840 Enter into DVFS_PRE_config >>>>>
7211 22:59:34.484410 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7212 22:59:34.487859 Exit from DVFS_PRE_config <<<<<
7213 22:59:34.491171 Enter into PICG configuration >>>>
7214 22:59:34.494380 Exit from PICG configuration <<<<
7215 22:59:34.497759 [RX_INPUT] configuration >>>>>
7216 22:59:34.500644 [RX_INPUT] configuration <<<<<
7217 22:59:34.507345 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7218 22:59:34.510828 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7219 22:59:34.517138 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7220 22:59:34.523991 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7221 22:59:34.530426 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7222 22:59:34.537165 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7223 22:59:34.540501 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7224 22:59:34.543972 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7225 22:59:34.547088 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7226 22:59:34.553983 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7227 22:59:34.556890 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7228 22:59:34.559984 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7229 22:59:34.563476 ===================================
7230 22:59:34.567241 LPDDR4 DRAM CONFIGURATION
7231 22:59:34.570335 ===================================
7232 22:59:34.573642 EX_ROW_EN[0] = 0x0
7233 22:59:34.573977 EX_ROW_EN[1] = 0x0
7234 22:59:34.576880 LP4Y_EN = 0x0
7235 22:59:34.577188 WORK_FSP = 0x1
7236 22:59:34.580372 WL = 0x5
7237 22:59:34.580773 RL = 0x5
7238 22:59:34.583480 BL = 0x2
7239 22:59:34.583781 RPST = 0x0
7240 22:59:34.587047 RD_PRE = 0x0
7241 22:59:34.587434 WR_PRE = 0x1
7242 22:59:34.590230 WR_PST = 0x1
7243 22:59:34.590654 DBI_WR = 0x0
7244 22:59:34.593752 DBI_RD = 0x0
7245 22:59:34.594175 OTF = 0x1
7246 22:59:34.597126 ===================================
7247 22:59:34.603879 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7248 22:59:34.606573 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7249 22:59:34.609717 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7250 22:59:34.613067 ===================================
7251 22:59:34.616346 LPDDR4 DRAM CONFIGURATION
7252 22:59:34.619604 ===================================
7253 22:59:34.622997 EX_ROW_EN[0] = 0x10
7254 22:59:34.623420 EX_ROW_EN[1] = 0x0
7255 22:59:34.626267 LP4Y_EN = 0x0
7256 22:59:34.626692 WORK_FSP = 0x1
7257 22:59:34.629652 WL = 0x5
7258 22:59:34.630072 RL = 0x5
7259 22:59:34.632999 BL = 0x2
7260 22:59:34.633421 RPST = 0x0
7261 22:59:34.636291 RD_PRE = 0x0
7262 22:59:34.636876 WR_PRE = 0x1
7263 22:59:34.639511 WR_PST = 0x1
7264 22:59:34.642349 DBI_WR = 0x0
7265 22:59:34.642773 DBI_RD = 0x0
7266 22:59:34.646003 OTF = 0x1
7267 22:59:34.648973 ===================================
7268 22:59:34.652444 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7269 22:59:34.655426 ==
7270 22:59:34.655508 Dram Type= 6, Freq= 0, CH_0, rank 0
7271 22:59:34.661998 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7272 22:59:34.662094 ==
7273 22:59:34.665620 [Duty_Offset_Calibration]
7274 22:59:34.665695 B0:2 B1:0 CA:4
7275 22:59:34.665761
7276 22:59:34.668551 [DutyScan_Calibration_Flow] k_type=0
7277 22:59:34.678112
7278 22:59:34.678196 ==CLK 0==
7279 22:59:34.681016 Final CLK duty delay cell = -4
7280 22:59:34.684429 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7281 22:59:34.687669 [-4] MIN Duty = 4844%(X100), DQS PI = 0
7282 22:59:34.690980 [-4] AVG Duty = 4937%(X100)
7283 22:59:34.691063
7284 22:59:34.694061 CH0 CLK Duty spec in!! Max-Min= 187%
7285 22:59:34.697825 [DutyScan_Calibration_Flow] ====Done====
7286 22:59:34.697913
7287 22:59:34.700888 [DutyScan_Calibration_Flow] k_type=1
7288 22:59:34.717669
7289 22:59:34.717752 ==DQS 0 ==
7290 22:59:34.720947 Final DQS duty delay cell = 0
7291 22:59:34.724314 [0] MAX Duty = 5249%(X100), DQS PI = 38
7292 22:59:34.727617 [0] MIN Duty = 5093%(X100), DQS PI = 10
7293 22:59:34.730575 [0] AVG Duty = 5171%(X100)
7294 22:59:34.730656
7295 22:59:34.730722 ==DQS 1 ==
7296 22:59:34.733918 Final DQS duty delay cell = 0
7297 22:59:34.737356 [0] MAX Duty = 5187%(X100), DQS PI = 2
7298 22:59:34.740689 [0] MIN Duty = 4969%(X100), DQS PI = 10
7299 22:59:34.743878 [0] AVG Duty = 5078%(X100)
7300 22:59:34.743986
7301 22:59:34.747161 CH0 DQS 0 Duty spec in!! Max-Min= 156%
7302 22:59:34.747270
7303 22:59:34.750542 CH0 DQS 1 Duty spec in!! Max-Min= 218%
7304 22:59:34.753824 [DutyScan_Calibration_Flow] ====Done====
7305 22:59:34.753910
7306 22:59:34.757219 [DutyScan_Calibration_Flow] k_type=3
7307 22:59:34.774874
7308 22:59:34.774963 ==DQM 0 ==
7309 22:59:34.778699 Final DQM duty delay cell = 0
7310 22:59:34.781668 [0] MAX Duty = 5124%(X100), DQS PI = 20
7311 22:59:34.784749 [0] MIN Duty = 4875%(X100), DQS PI = 56
7312 22:59:34.788508 [0] AVG Duty = 4999%(X100)
7313 22:59:34.788627
7314 22:59:34.788705 ==DQM 1 ==
7315 22:59:34.791688 Final DQM duty delay cell = 0
7316 22:59:34.794935 [0] MAX Duty = 4969%(X100), DQS PI = 0
7317 22:59:34.798365 [0] MIN Duty = 4813%(X100), DQS PI = 16
7318 22:59:34.801084 [0] AVG Duty = 4891%(X100)
7319 22:59:34.801158
7320 22:59:34.804491 CH0 DQM 0 Duty spec in!! Max-Min= 249%
7321 22:59:34.804566
7322 22:59:34.807834 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7323 22:59:34.811090 [DutyScan_Calibration_Flow] ====Done====
7324 22:59:34.811167
7325 22:59:34.814563 [DutyScan_Calibration_Flow] k_type=2
7326 22:59:34.832118
7327 22:59:34.832194 ==DQ 0 ==
7328 22:59:34.835285 Final DQ duty delay cell = 0
7329 22:59:34.838663 [0] MAX Duty = 5156%(X100), DQS PI = 22
7330 22:59:34.842142 [0] MIN Duty = 4938%(X100), DQS PI = 12
7331 22:59:34.845431 [0] AVG Duty = 5047%(X100)
7332 22:59:34.845503
7333 22:59:34.845565 ==DQ 1 ==
7334 22:59:34.848458 Final DQ duty delay cell = 0
7335 22:59:34.851624 [0] MAX Duty = 5187%(X100), DQS PI = 2
7336 22:59:34.855210 [0] MIN Duty = 4938%(X100), DQS PI = 12
7337 22:59:34.855288 [0] AVG Duty = 5062%(X100)
7338 22:59:34.858719
7339 22:59:34.862065 CH0 DQ 0 Duty spec in!! Max-Min= 218%
7340 22:59:34.862145
7341 22:59:34.865524 CH0 DQ 1 Duty spec in!! Max-Min= 249%
7342 22:59:34.868380 [DutyScan_Calibration_Flow] ====Done====
7343 22:59:34.868457 ==
7344 22:59:34.871487 Dram Type= 6, Freq= 0, CH_1, rank 0
7345 22:59:34.875258 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7346 22:59:34.875334 ==
7347 22:59:34.878267 [Duty_Offset_Calibration]
7348 22:59:34.878348 B0:0 B1:-1 CA:3
7349 22:59:34.878414
7350 22:59:34.881281 [DutyScan_Calibration_Flow] k_type=0
7351 22:59:34.891785
7352 22:59:34.891869 ==CLK 0==
7353 22:59:34.894993 Final CLK duty delay cell = -4
7354 22:59:34.898169 [-4] MAX Duty = 5000%(X100), DQS PI = 4
7355 22:59:34.901461 [-4] MIN Duty = 4844%(X100), DQS PI = 38
7356 22:59:34.904918 [-4] AVG Duty = 4922%(X100)
7357 22:59:34.905002
7358 22:59:34.908211 CH1 CLK Duty spec in!! Max-Min= 156%
7359 22:59:34.911226 [DutyScan_Calibration_Flow] ====Done====
7360 22:59:34.911315
7361 22:59:34.914639 [DutyScan_Calibration_Flow] k_type=1
7362 22:59:34.930714
7363 22:59:34.930795 ==DQS 0 ==
7364 22:59:34.934227 Final DQS duty delay cell = 0
7365 22:59:34.937613 [0] MAX Duty = 5250%(X100), DQS PI = 28
7366 22:59:34.940368 [0] MIN Duty = 4907%(X100), DQS PI = 58
7367 22:59:34.943909 [0] AVG Duty = 5078%(X100)
7368 22:59:34.944014
7369 22:59:34.944129 ==DQS 1 ==
7370 22:59:34.947086 Final DQS duty delay cell = -4
7371 22:59:34.950277 [-4] MAX Duty = 5000%(X100), DQS PI = 30
7372 22:59:34.953659 [-4] MIN Duty = 4813%(X100), DQS PI = 0
7373 22:59:34.957221 [-4] AVG Duty = 4906%(X100)
7374 22:59:34.957300
7375 22:59:34.960409 CH1 DQS 0 Duty spec in!! Max-Min= 343%
7376 22:59:34.960489
7377 22:59:34.963708 CH1 DQS 1 Duty spec in!! Max-Min= 187%
7378 22:59:34.967307 [DutyScan_Calibration_Flow] ====Done====
7379 22:59:34.967377
7380 22:59:34.970495 [DutyScan_Calibration_Flow] k_type=3
7381 22:59:34.987768
7382 22:59:34.987843 ==DQM 0 ==
7383 22:59:34.991349 Final DQM duty delay cell = 0
7384 22:59:34.994305 [0] MAX Duty = 5062%(X100), DQS PI = 30
7385 22:59:34.997915 [0] MIN Duty = 4750%(X100), DQS PI = 40
7386 22:59:35.000987 [0] AVG Duty = 4906%(X100)
7387 22:59:35.001064
7388 22:59:35.001129 ==DQM 1 ==
7389 22:59:35.004622 Final DQM duty delay cell = 0
7390 22:59:35.007806 [0] MAX Duty = 5000%(X100), DQS PI = 32
7391 22:59:35.011305 [0] MIN Duty = 4813%(X100), DQS PI = 12
7392 22:59:35.014501 [0] AVG Duty = 4906%(X100)
7393 22:59:35.014601
7394 22:59:35.017882 CH1 DQM 0 Duty spec in!! Max-Min= 312%
7395 22:59:35.017952
7396 22:59:35.021335 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7397 22:59:35.024527 [DutyScan_Calibration_Flow] ====Done====
7398 22:59:35.024608
7399 22:59:35.027869 [DutyScan_Calibration_Flow] k_type=2
7400 22:59:35.044103
7401 22:59:35.044185 ==DQ 0 ==
7402 22:59:35.047315 Final DQ duty delay cell = -4
7403 22:59:35.050710 [-4] MAX Duty = 4969%(X100), DQS PI = 32
7404 22:59:35.053940 [-4] MIN Duty = 4813%(X100), DQS PI = 36
7405 22:59:35.057133 [-4] AVG Duty = 4891%(X100)
7406 22:59:35.057216
7407 22:59:35.057283 ==DQ 1 ==
7408 22:59:35.060606 Final DQ duty delay cell = 0
7409 22:59:35.063885 [0] MAX Duty = 5062%(X100), DQS PI = 32
7410 22:59:35.066922 [0] MIN Duty = 4875%(X100), DQS PI = 0
7411 22:59:35.070435 [0] AVG Duty = 4968%(X100)
7412 22:59:35.070519
7413 22:59:35.073721 CH1 DQ 0 Duty spec in!! Max-Min= 156%
7414 22:59:35.073804
7415 22:59:35.077068 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7416 22:59:35.080206 [DutyScan_Calibration_Flow] ====Done====
7417 22:59:35.083990 nWR fixed to 30
7418 22:59:35.087314 [ModeRegInit_LP4] CH0 RK0
7419 22:59:35.087398 [ModeRegInit_LP4] CH0 RK1
7420 22:59:35.090420 [ModeRegInit_LP4] CH1 RK0
7421 22:59:35.093529 [ModeRegInit_LP4] CH1 RK1
7422 22:59:35.093612 match AC timing 5
7423 22:59:35.100161 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7424 22:59:35.103284 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7425 22:59:35.106816 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7426 22:59:35.113602 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7427 22:59:35.116724 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7428 22:59:35.116808 [MiockJmeterHQA]
7429 22:59:35.120091
7430 22:59:35.120174 [DramcMiockJmeter] u1RxGatingPI = 0
7431 22:59:35.123470 0 : 4366, 4137
7432 22:59:35.123555 4 : 4252, 4027
7433 22:59:35.126887 8 : 4252, 4027
7434 22:59:35.126972 12 : 4252, 4027
7435 22:59:35.129698 16 : 4253, 4027
7436 22:59:35.129782 20 : 4363, 4137
7437 22:59:35.133048 24 : 4252, 4027
7438 22:59:35.133132 28 : 4365, 4140
7439 22:59:35.133199 32 : 4252, 4027
7440 22:59:35.136461 36 : 4253, 4027
7441 22:59:35.136545 40 : 4253, 4026
7442 22:59:35.139817 44 : 4255, 4029
7443 22:59:35.139902 48 : 4253, 4027
7444 22:59:35.143217 52 : 4252, 4027
7445 22:59:35.143302 56 : 4365, 4140
7446 22:59:35.146542 60 : 4253, 4026
7447 22:59:35.146627 64 : 4252, 4029
7448 22:59:35.146694 68 : 4250, 4027
7449 22:59:35.149536 72 : 4361, 4137
7450 22:59:35.149621 76 : 4250, 4027
7451 22:59:35.152901 80 : 4361, 4137
7452 22:59:35.152984 84 : 4252, 4027
7453 22:59:35.156431 88 : 4250, 4027
7454 22:59:35.156515 92 : 4250, 4027
7455 22:59:35.159792 96 : 4252, 3416
7456 22:59:35.159878 100 : 4361, 0
7457 22:59:35.159945 104 : 4252, 0
7458 22:59:35.163332 108 : 4363, 0
7459 22:59:35.163417 112 : 4361, 0
7460 22:59:35.163484 116 : 4363, 0
7461 22:59:35.165891 120 : 4253, 0
7462 22:59:35.165976 124 : 4250, 0
7463 22:59:35.169228 128 : 4249, 0
7464 22:59:35.169314 132 : 4252, 0
7465 22:59:35.169381 136 : 4253, 0
7466 22:59:35.172433 140 : 4249, 0
7467 22:59:35.172518 144 : 4253, 0
7468 22:59:35.175981 148 : 4361, 0
7469 22:59:35.176087 152 : 4250, 0
7470 22:59:35.176154 156 : 4250, 0
7471 22:59:35.179260 160 : 4252, 0
7472 22:59:35.179354 164 : 4361, 0
7473 22:59:35.182633 168 : 4360, 0
7474 22:59:35.182718 172 : 4252, 0
7475 22:59:35.182785 176 : 4361, 0
7476 22:59:35.185704 180 : 4250, 0
7477 22:59:35.185793 184 : 4250, 0
7478 22:59:35.189090 188 : 4250, 0
7479 22:59:35.189175 192 : 4249, 0
7480 22:59:35.189242 196 : 4253, 0
7481 22:59:35.192436 200 : 4255, 0
7482 22:59:35.192521 204 : 4250, 0
7483 22:59:35.195756 208 : 4252, 0
7484 22:59:35.195840 212 : 4250, 0
7485 22:59:35.195908 216 : 4361, 0
7486 22:59:35.199160 220 : 4252, 412
7487 22:59:35.199245 224 : 4250, 3970
7488 22:59:35.202127 228 : 4361, 4138
7489 22:59:35.202213 232 : 4250, 4027
7490 22:59:35.205621 236 : 4250, 4027
7491 22:59:35.205706 240 : 4361, 4137
7492 22:59:35.208607 244 : 4361, 4138
7493 22:59:35.208719 248 : 4250, 4027
7494 22:59:35.212232 252 : 4363, 4140
7495 22:59:35.212317 256 : 4250, 4027
7496 22:59:35.212389 260 : 4250, 4026
7497 22:59:35.215863 264 : 4252, 4027
7498 22:59:35.215948 268 : 4252, 4029
7499 22:59:35.218813 272 : 4249, 4027
7500 22:59:35.218898 276 : 4250, 4026
7501 22:59:35.221984 280 : 4252, 4027
7502 22:59:35.222069 284 : 4252, 4029
7503 22:59:35.225094 288 : 4249, 4027
7504 22:59:35.225178 292 : 4361, 4137
7505 22:59:35.228526 296 : 4361, 4138
7506 22:59:35.228611 300 : 4250, 4027
7507 22:59:35.231749 304 : 4363, 4140
7508 22:59:35.231833 308 : 4249, 4027
7509 22:59:35.235127 312 : 4250, 4027
7510 22:59:35.235212 316 : 4252, 4027
7511 22:59:35.238525 320 : 4252, 4029
7512 22:59:35.238609 324 : 4250, 4027
7513 22:59:35.238677 328 : 4250, 4026
7514 22:59:35.242005 332 : 4250, 4013
7515 22:59:35.242090 336 : 4252, 2200
7516 22:59:35.245267 340 : 4249, 14
7517 22:59:35.245352
7518 22:59:35.248671 MIOCK jitter meter ch=0
7519 22:59:35.248755
7520 22:59:35.248822 1T = (340-100) = 240 dly cells
7521 22:59:35.254842 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 271/100 ps
7522 22:59:35.254926 ==
7523 22:59:35.258438 Dram Type= 6, Freq= 0, CH_0, rank 0
7524 22:59:35.264758 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7525 22:59:35.264843 ==
7526 22:59:35.268009 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7527 22:59:35.271324 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7528 22:59:35.278142 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7529 22:59:35.284653 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7530 22:59:35.292154 [CA 0] Center 43 (13~74) winsize 62
7531 22:59:35.295097 [CA 1] Center 42 (12~73) winsize 62
7532 22:59:35.298462 [CA 2] Center 37 (8~67) winsize 60
7533 22:59:35.301806 [CA 3] Center 37 (8~67) winsize 60
7534 22:59:35.304993 [CA 4] Center 36 (6~66) winsize 61
7535 22:59:35.308623 [CA 5] Center 35 (5~66) winsize 62
7536 22:59:35.308706
7537 22:59:35.311727 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7538 22:59:35.311811
7539 22:59:35.315302 [CATrainingPosCal] consider 1 rank data
7540 22:59:35.318400 u2DelayCellTimex100 = 271/100 ps
7541 22:59:35.324901 CA0 delay=43 (13~74),Diff = 8 PI (28 cell)
7542 22:59:35.328573 CA1 delay=42 (12~73),Diff = 7 PI (25 cell)
7543 22:59:35.331525 CA2 delay=37 (8~67),Diff = 2 PI (7 cell)
7544 22:59:35.334928 CA3 delay=37 (8~67),Diff = 2 PI (7 cell)
7545 22:59:35.338221 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7546 22:59:35.341215 CA5 delay=35 (5~66),Diff = 0 PI (0 cell)
7547 22:59:35.341299
7548 22:59:35.344769 CA PerBit enable=1, Macro0, CA PI delay=35
7549 22:59:35.344852
7550 22:59:35.347699 [CBTSetCACLKResult] CA Dly = 35
7551 22:59:35.351068 CS Dly: 10 (0~41)
7552 22:59:35.354501 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7553 22:59:35.357964 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7554 22:59:35.358047 ==
7555 22:59:35.361075 Dram Type= 6, Freq= 0, CH_0, rank 1
7556 22:59:35.367879 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7557 22:59:35.367966 ==
7558 22:59:35.371224 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7559 22:59:35.377789 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7560 22:59:35.381154 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7561 22:59:35.387587 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7562 22:59:35.395200 [CA 0] Center 43 (13~74) winsize 62
7563 22:59:35.398668 [CA 1] Center 43 (13~74) winsize 62
7564 22:59:35.401893 [CA 2] Center 38 (9~68) winsize 60
7565 22:59:35.405425 [CA 3] Center 38 (9~68) winsize 60
7566 22:59:35.408829 [CA 4] Center 37 (7~67) winsize 61
7567 22:59:35.412086 [CA 5] Center 36 (6~66) winsize 61
7568 22:59:35.412169
7569 22:59:35.415417 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7570 22:59:35.415500
7571 22:59:35.418606 [CATrainingPosCal] consider 2 rank data
7572 22:59:35.422084 u2DelayCellTimex100 = 271/100 ps
7573 22:59:35.428824 CA0 delay=43 (13~74),Diff = 7 PI (25 cell)
7574 22:59:35.431980 CA1 delay=43 (13~73),Diff = 7 PI (25 cell)
7575 22:59:35.435098 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
7576 22:59:35.438277 CA3 delay=38 (9~67),Diff = 2 PI (7 cell)
7577 22:59:35.441728 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7578 22:59:35.445226 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7579 22:59:35.445309
7580 22:59:35.448262 CA PerBit enable=1, Macro0, CA PI delay=36
7581 22:59:35.448346
7582 22:59:35.451355 [CBTSetCACLKResult] CA Dly = 36
7583 22:59:35.454793 CS Dly: 11 (0~43)
7584 22:59:35.458170 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7585 22:59:35.461351 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7586 22:59:35.461435
7587 22:59:35.464485 ----->DramcWriteLeveling(PI) begin...
7588 22:59:35.464570 ==
7589 22:59:35.467544 Dram Type= 6, Freq= 0, CH_0, rank 0
7590 22:59:35.474600 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7591 22:59:35.474684 ==
7592 22:59:35.477552 Write leveling (Byte 0): 35 => 35
7593 22:59:35.481347 Write leveling (Byte 1): 27 => 27
7594 22:59:35.481431 DramcWriteLeveling(PI) end<-----
7595 22:59:35.484708
7596 22:59:35.484790 ==
7597 22:59:35.487604 Dram Type= 6, Freq= 0, CH_0, rank 0
7598 22:59:35.490932 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7599 22:59:35.491015 ==
7600 22:59:35.494185 [Gating] SW mode calibration
7601 22:59:35.500693 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7602 22:59:35.504021 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7603 22:59:35.510929 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7604 22:59:35.514077 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7605 22:59:35.517495 1 4 8 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
7606 22:59:35.524021 1 4 12 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
7607 22:59:35.527491 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7608 22:59:35.530316 1 4 20 | B1->B0 | 2626 3434 | 0 1 | (0 0) (1 1)
7609 22:59:35.537651 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7610 22:59:35.540741 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7611 22:59:35.544001 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7612 22:59:35.550645 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7613 22:59:35.553977 1 5 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
7614 22:59:35.557252 1 5 12 | B1->B0 | 3434 2626 | 1 0 | (1 1) (0 0)
7615 22:59:35.563591 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7616 22:59:35.566913 1 5 20 | B1->B0 | 3232 2323 | 1 0 | (1 0) (0 0)
7617 22:59:35.574178 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7618 22:59:35.577502 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7619 22:59:35.580735 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7620 22:59:35.583904 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7621 22:59:35.590410 1 6 8 | B1->B0 | 2323 3131 | 0 1 | (0 0) (0 0)
7622 22:59:35.594008 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7623 22:59:35.597450 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7624 22:59:35.603697 1 6 20 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
7625 22:59:35.607137 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7626 22:59:35.610436 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7627 22:59:35.616814 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7628 22:59:35.620399 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7629 22:59:35.623509 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7630 22:59:35.630403 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7631 22:59:35.632938 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7632 22:59:35.636657 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7633 22:59:35.643352 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7634 22:59:35.646195 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7635 22:59:35.649709 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7636 22:59:35.655990 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7637 22:59:35.659445 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7638 22:59:35.662778 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7639 22:59:35.669677 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7640 22:59:35.673180 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7641 22:59:35.676299 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7642 22:59:35.682622 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7643 22:59:35.685761 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7644 22:59:35.692257 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7645 22:59:35.695809 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7646 22:59:35.699261 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7647 22:59:35.705679 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7648 22:59:35.706209 Total UI for P1: 0, mck2ui 16
7649 22:59:35.712027 best dqsien dly found for B0: ( 1, 9, 10)
7650 22:59:35.715195 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7651 22:59:35.718932 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7652 22:59:35.725221 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7653 22:59:35.725655 Total UI for P1: 0, mck2ui 16
7654 22:59:35.728551 best dqsien dly found for B1: ( 1, 9, 24)
7655 22:59:35.735140 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7656 22:59:35.738652 best DQS1 dly(MCK, UI, PI) = (1, 9, 24)
7657 22:59:35.739081
7658 22:59:35.741981 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7659 22:59:35.744833 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 24)
7660 22:59:35.747938 [Gating] SW calibration Done
7661 22:59:35.748403 ==
7662 22:59:35.751390 Dram Type= 6, Freq= 0, CH_0, rank 0
7663 22:59:35.754616 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7664 22:59:35.755044 ==
7665 22:59:35.758306 RX Vref Scan: 0
7666 22:59:35.758729
7667 22:59:35.759067 RX Vref 0 -> 0, step: 1
7668 22:59:35.759384
7669 22:59:35.761281 RX Delay 0 -> 252, step: 8
7670 22:59:35.764326 iDelay=192, Bit 0, Center 135 (80 ~ 191) 112
7671 22:59:35.771312 iDelay=192, Bit 1, Center 135 (80 ~ 191) 112
7672 22:59:35.774820 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7673 22:59:35.778165 iDelay=192, Bit 3, Center 127 (72 ~ 183) 112
7674 22:59:35.781263 iDelay=192, Bit 4, Center 135 (80 ~ 191) 112
7675 22:59:35.784545 iDelay=192, Bit 5, Center 119 (64 ~ 175) 112
7676 22:59:35.791064 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7677 22:59:35.794787 iDelay=192, Bit 7, Center 139 (88 ~ 191) 104
7678 22:59:35.797518 iDelay=192, Bit 8, Center 119 (64 ~ 175) 112
7679 22:59:35.801215 iDelay=192, Bit 9, Center 115 (64 ~ 167) 104
7680 22:59:35.804128 iDelay=192, Bit 10, Center 127 (80 ~ 175) 96
7681 22:59:35.810469 iDelay=192, Bit 11, Center 123 (72 ~ 175) 104
7682 22:59:35.814204 iDelay=192, Bit 12, Center 135 (80 ~ 191) 112
7683 22:59:35.817749 iDelay=192, Bit 13, Center 131 (80 ~ 183) 104
7684 22:59:35.820466 iDelay=192, Bit 14, Center 139 (88 ~ 191) 104
7685 22:59:35.827190 iDelay=192, Bit 15, Center 135 (80 ~ 191) 112
7686 22:59:35.827728 ==
7687 22:59:35.830425 Dram Type= 6, Freq= 0, CH_0, rank 0
7688 22:59:35.833900 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7689 22:59:35.834448 ==
7690 22:59:35.834799 DQS Delay:
7691 22:59:35.837008 DQS0 = 0, DQS1 = 0
7692 22:59:35.837441 DQM Delay:
7693 22:59:35.840647 DQM0 = 132, DQM1 = 128
7694 22:59:35.841187 DQ Delay:
7695 22:59:35.843770 DQ0 =135, DQ1 =135, DQ2 =127, DQ3 =127
7696 22:59:35.847160 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
7697 22:59:35.850498 DQ8 =119, DQ9 =115, DQ10 =127, DQ11 =123
7698 22:59:35.853816 DQ12 =135, DQ13 =131, DQ14 =139, DQ15 =135
7699 22:59:35.856623
7700 22:59:35.857051
7701 22:59:35.857390 ==
7702 22:59:35.860392 Dram Type= 6, Freq= 0, CH_0, rank 0
7703 22:59:35.863115 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7704 22:59:35.863548 ==
7705 22:59:35.863889
7706 22:59:35.864263
7707 22:59:35.867045 TX Vref Scan disable
7708 22:59:35.867581 == TX Byte 0 ==
7709 22:59:35.873311 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7710 22:59:35.876345 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7711 22:59:35.876783 == TX Byte 1 ==
7712 22:59:35.883724 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7713 22:59:35.886232 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7714 22:59:35.886665 ==
7715 22:59:35.889492 Dram Type= 6, Freq= 0, CH_0, rank 0
7716 22:59:35.893231 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7717 22:59:35.893663 ==
7718 22:59:35.907723
7719 22:59:35.911032 TX Vref early break, caculate TX vref
7720 22:59:35.914422 TX Vref=16, minBit 4, minWin=22, winSum=371
7721 22:59:35.917764 TX Vref=18, minBit 1, minWin=22, winSum=381
7722 22:59:35.920924 TX Vref=20, minBit 7, minWin=23, winSum=391
7723 22:59:35.924555 TX Vref=22, minBit 3, minWin=24, winSum=398
7724 22:59:35.927996 TX Vref=24, minBit 1, minWin=24, winSum=407
7725 22:59:35.934524 TX Vref=26, minBit 1, minWin=25, winSum=417
7726 22:59:35.937424 TX Vref=28, minBit 2, minWin=25, winSum=423
7727 22:59:35.940582 TX Vref=30, minBit 2, minWin=24, winSum=418
7728 22:59:35.944233 TX Vref=32, minBit 2, minWin=24, winSum=411
7729 22:59:35.947445 TX Vref=34, minBit 1, minWin=23, winSum=399
7730 22:59:35.953695 [TxChooseVref] Worse bit 2, Min win 25, Win sum 423, Final Vref 28
7731 22:59:35.954129
7732 22:59:35.957074 Final TX Range 0 Vref 28
7733 22:59:35.957507
7734 22:59:35.957846 ==
7735 22:59:35.960273 Dram Type= 6, Freq= 0, CH_0, rank 0
7736 22:59:35.963378 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7737 22:59:35.963945 ==
7738 22:59:35.964351
7739 22:59:35.964679
7740 22:59:35.967072 TX Vref Scan disable
7741 22:59:35.973583 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7742 22:59:35.974128 == TX Byte 0 ==
7743 22:59:35.976738 u2DelayCellOfst[0]=10 cells (3 PI)
7744 22:59:35.980068 u2DelayCellOfst[1]=14 cells (4 PI)
7745 22:59:35.983418 u2DelayCellOfst[2]=7 cells (2 PI)
7746 22:59:35.986938 u2DelayCellOfst[3]=10 cells (3 PI)
7747 22:59:35.989804 u2DelayCellOfst[4]=7 cells (2 PI)
7748 22:59:35.993130 u2DelayCellOfst[5]=0 cells (0 PI)
7749 22:59:35.996148 u2DelayCellOfst[6]=14 cells (4 PI)
7750 22:59:35.999825 u2DelayCellOfst[7]=14 cells (4 PI)
7751 22:59:36.002811 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7752 22:59:36.006716 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7753 22:59:36.009464 == TX Byte 1 ==
7754 22:59:36.012924 u2DelayCellOfst[8]=0 cells (0 PI)
7755 22:59:36.016194 u2DelayCellOfst[9]=0 cells (0 PI)
7756 22:59:36.019946 u2DelayCellOfst[10]=7 cells (2 PI)
7757 22:59:36.020514 u2DelayCellOfst[11]=3 cells (1 PI)
7758 22:59:36.023188 u2DelayCellOfst[12]=10 cells (3 PI)
7759 22:59:36.026394 u2DelayCellOfst[13]=10 cells (3 PI)
7760 22:59:36.030203 u2DelayCellOfst[14]=14 cells (4 PI)
7761 22:59:36.033501 u2DelayCellOfst[15]=10 cells (3 PI)
7762 22:59:36.039552 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7763 22:59:36.042849 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7764 22:59:36.043272 DramC Write-DBI on
7765 22:59:36.046132 ==
7766 22:59:36.046555 Dram Type= 6, Freq= 0, CH_0, rank 0
7767 22:59:36.052519 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7768 22:59:36.052945 ==
7769 22:59:36.053279
7770 22:59:36.053587
7771 22:59:36.055831 TX Vref Scan disable
7772 22:59:36.056296 == TX Byte 0 ==
7773 22:59:36.062469 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7774 22:59:36.062893 == TX Byte 1 ==
7775 22:59:36.065958 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7776 22:59:36.068832 DramC Write-DBI off
7777 22:59:36.069251
7778 22:59:36.069580 [DATLAT]
7779 22:59:36.072354 Freq=1600, CH0 RK0
7780 22:59:36.072778
7781 22:59:36.073114 DATLAT Default: 0xf
7782 22:59:36.075972 0, 0xFFFF, sum = 0
7783 22:59:36.076451 1, 0xFFFF, sum = 0
7784 22:59:36.079205 2, 0xFFFF, sum = 0
7785 22:59:36.079631 3, 0xFFFF, sum = 0
7786 22:59:36.082410 4, 0xFFFF, sum = 0
7787 22:59:36.082948 5, 0xFFFF, sum = 0
7788 22:59:36.085325 6, 0xFFFF, sum = 0
7789 22:59:36.088842 7, 0xFFFF, sum = 0
7790 22:59:36.089357 8, 0xFFFF, sum = 0
7791 22:59:36.092122 9, 0xFFFF, sum = 0
7792 22:59:36.092638 10, 0xFFFF, sum = 0
7793 22:59:36.095079 11, 0xFFFF, sum = 0
7794 22:59:36.095537 12, 0xFFFF, sum = 0
7795 22:59:36.098727 13, 0xFFFF, sum = 0
7796 22:59:36.099111 14, 0x0, sum = 1
7797 22:59:36.102041 15, 0x0, sum = 2
7798 22:59:36.102505 16, 0x0, sum = 3
7799 22:59:36.105417 17, 0x0, sum = 4
7800 22:59:36.105851 best_step = 15
7801 22:59:36.106192
7802 22:59:36.106510 ==
7803 22:59:36.108126 Dram Type= 6, Freq= 0, CH_0, rank 0
7804 22:59:36.111886 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7805 22:59:36.115107 ==
7806 22:59:36.115534 RX Vref Scan: 1
7807 22:59:36.115878
7808 22:59:36.117950 Set Vref Range= 24 -> 127
7809 22:59:36.118380
7810 22:59:36.121932 RX Vref 24 -> 127, step: 1
7811 22:59:36.122469
7812 22:59:36.122815 RX Delay 19 -> 252, step: 4
7813 22:59:36.123135
7814 22:59:36.124642 Set Vref, RX VrefLevel [Byte0]: 24
7815 22:59:36.128099 [Byte1]: 24
7816 22:59:36.132485
7817 22:59:36.133014 Set Vref, RX VrefLevel [Byte0]: 25
7818 22:59:36.135109 [Byte1]: 25
7819 22:59:36.139803
7820 22:59:36.140329 Set Vref, RX VrefLevel [Byte0]: 26
7821 22:59:36.142950 [Byte1]: 26
7822 22:59:36.147302
7823 22:59:36.147730 Set Vref, RX VrefLevel [Byte0]: 27
7824 22:59:36.150704 [Byte1]: 27
7825 22:59:36.154520
7826 22:59:36.154947 Set Vref, RX VrefLevel [Byte0]: 28
7827 22:59:36.158319 [Byte1]: 28
7828 22:59:36.162555
7829 22:59:36.163189 Set Vref, RX VrefLevel [Byte0]: 29
7830 22:59:36.165543 [Byte1]: 29
7831 22:59:36.170318
7832 22:59:36.170862 Set Vref, RX VrefLevel [Byte0]: 30
7833 22:59:36.173273 [Byte1]: 30
7834 22:59:36.177901
7835 22:59:36.178437 Set Vref, RX VrefLevel [Byte0]: 31
7836 22:59:36.181188 [Byte1]: 31
7837 22:59:36.185069
7838 22:59:36.185499 Set Vref, RX VrefLevel [Byte0]: 32
7839 22:59:36.188271 [Byte1]: 32
7840 22:59:36.193030
7841 22:59:36.193503 Set Vref, RX VrefLevel [Byte0]: 33
7842 22:59:36.195762 [Byte1]: 33
7843 22:59:36.200006
7844 22:59:36.200495 Set Vref, RX VrefLevel [Byte0]: 34
7845 22:59:36.203383 [Byte1]: 34
7846 22:59:36.208079
7847 22:59:36.208522 Set Vref, RX VrefLevel [Byte0]: 35
7848 22:59:36.210938 [Byte1]: 35
7849 22:59:36.215394
7850 22:59:36.215953 Set Vref, RX VrefLevel [Byte0]: 36
7851 22:59:36.218888 [Byte1]: 36
7852 22:59:36.223130
7853 22:59:36.223688 Set Vref, RX VrefLevel [Byte0]: 37
7854 22:59:36.226520 [Byte1]: 37
7855 22:59:36.230720
7856 22:59:36.231227 Set Vref, RX VrefLevel [Byte0]: 38
7857 22:59:36.233943 [Byte1]: 38
7858 22:59:36.238749
7859 22:59:36.239271 Set Vref, RX VrefLevel [Byte0]: 39
7860 22:59:36.241538 [Byte1]: 39
7861 22:59:36.245735
7862 22:59:36.246175 Set Vref, RX VrefLevel [Byte0]: 40
7863 22:59:36.248944 [Byte1]: 40
7864 22:59:36.253380
7865 22:59:36.253804 Set Vref, RX VrefLevel [Byte0]: 41
7866 22:59:36.256789 [Byte1]: 41
7867 22:59:36.260692
7868 22:59:36.261114 Set Vref, RX VrefLevel [Byte0]: 42
7869 22:59:36.263908 [Byte1]: 42
7870 22:59:36.268566
7871 22:59:36.268987 Set Vref, RX VrefLevel [Byte0]: 43
7872 22:59:36.272141 [Byte1]: 43
7873 22:59:36.275917
7874 22:59:36.276526 Set Vref, RX VrefLevel [Byte0]: 44
7875 22:59:36.279130 [Byte1]: 44
7876 22:59:36.283627
7877 22:59:36.284178 Set Vref, RX VrefLevel [Byte0]: 45
7878 22:59:36.286928 [Byte1]: 45
7879 22:59:36.291344
7880 22:59:36.291866 Set Vref, RX VrefLevel [Byte0]: 46
7881 22:59:36.294665 [Byte1]: 46
7882 22:59:36.298511
7883 22:59:36.298939 Set Vref, RX VrefLevel [Byte0]: 47
7884 22:59:36.302001 [Byte1]: 47
7885 22:59:36.306040
7886 22:59:36.306462 Set Vref, RX VrefLevel [Byte0]: 48
7887 22:59:36.309584 [Byte1]: 48
7888 22:59:36.314216
7889 22:59:36.314711 Set Vref, RX VrefLevel [Byte0]: 49
7890 22:59:36.316875 [Byte1]: 49
7891 22:59:36.321474
7892 22:59:36.321900 Set Vref, RX VrefLevel [Byte0]: 50
7893 22:59:36.324551 [Byte1]: 50
7894 22:59:36.328811
7895 22:59:36.329392 Set Vref, RX VrefLevel [Byte0]: 51
7896 22:59:36.332230 [Byte1]: 51
7897 22:59:36.336709
7898 22:59:36.337194 Set Vref, RX VrefLevel [Byte0]: 52
7899 22:59:36.340007 [Byte1]: 52
7900 22:59:36.344353
7901 22:59:36.344777 Set Vref, RX VrefLevel [Byte0]: 53
7902 22:59:36.347108 [Byte1]: 53
7903 22:59:36.351453
7904 22:59:36.351879 Set Vref, RX VrefLevel [Byte0]: 54
7905 22:59:36.354897 [Byte1]: 54
7906 22:59:36.359045
7907 22:59:36.359613 Set Vref, RX VrefLevel [Byte0]: 55
7908 22:59:36.362375 [Byte1]: 55
7909 22:59:36.366826
7910 22:59:36.367253 Set Vref, RX VrefLevel [Byte0]: 56
7911 22:59:36.370528 [Byte1]: 56
7912 22:59:36.374229
7913 22:59:36.374676 Set Vref, RX VrefLevel [Byte0]: 57
7914 22:59:36.377848 [Byte1]: 57
7915 22:59:36.382534
7916 22:59:36.383065 Set Vref, RX VrefLevel [Byte0]: 58
7917 22:59:36.385510 [Byte1]: 58
7918 22:59:36.389491
7919 22:59:36.390040 Set Vref, RX VrefLevel [Byte0]: 59
7920 22:59:36.393274 [Byte1]: 59
7921 22:59:36.397280
7922 22:59:36.397784 Set Vref, RX VrefLevel [Byte0]: 60
7923 22:59:36.400173 [Byte1]: 60
7924 22:59:36.405232
7925 22:59:36.405799 Set Vref, RX VrefLevel [Byte0]: 61
7926 22:59:36.408350 [Byte1]: 61
7927 22:59:36.412344
7928 22:59:36.412866 Set Vref, RX VrefLevel [Byte0]: 62
7929 22:59:36.415380 [Byte1]: 62
7930 22:59:36.420177
7931 22:59:36.420604 Set Vref, RX VrefLevel [Byte0]: 63
7932 22:59:36.423459 [Byte1]: 63
7933 22:59:36.427333
7934 22:59:36.427874 Set Vref, RX VrefLevel [Byte0]: 64
7935 22:59:36.430855 [Byte1]: 64
7936 22:59:36.435357
7937 22:59:36.435925 Set Vref, RX VrefLevel [Byte0]: 65
7938 22:59:36.438400 [Byte1]: 65
7939 22:59:36.443059
7940 22:59:36.443600 Set Vref, RX VrefLevel [Byte0]: 66
7941 22:59:36.446393 [Byte1]: 66
7942 22:59:36.450050
7943 22:59:36.450479 Set Vref, RX VrefLevel [Byte0]: 67
7944 22:59:36.453289 [Byte1]: 67
7945 22:59:36.457766
7946 22:59:36.458297 Set Vref, RX VrefLevel [Byte0]: 68
7947 22:59:36.460881 [Byte1]: 68
7948 22:59:36.465330
7949 22:59:36.465761 Set Vref, RX VrefLevel [Byte0]: 69
7950 22:59:36.468688 [Byte1]: 69
7951 22:59:36.472982
7952 22:59:36.473627 Set Vref, RX VrefLevel [Byte0]: 70
7953 22:59:36.476418 [Byte1]: 70
7954 22:59:36.480597
7955 22:59:36.481028 Set Vref, RX VrefLevel [Byte0]: 71
7956 22:59:36.483702 [Byte1]: 71
7957 22:59:36.488420
7958 22:59:36.488954 Set Vref, RX VrefLevel [Byte0]: 72
7959 22:59:36.491745 [Byte1]: 72
7960 22:59:36.495660
7961 22:59:36.496226 Set Vref, RX VrefLevel [Byte0]: 73
7962 22:59:36.498978 [Byte1]: 73
7963 22:59:36.503601
7964 22:59:36.504170 Set Vref, RX VrefLevel [Byte0]: 74
7965 22:59:36.506940 [Byte1]: 74
7966 22:59:36.511111
7967 22:59:36.511648 Set Vref, RX VrefLevel [Byte0]: 75
7968 22:59:36.513978 [Byte1]: 75
7969 22:59:36.518231
7970 22:59:36.518660 Set Vref, RX VrefLevel [Byte0]: 76
7971 22:59:36.521298 [Byte1]: 76
7972 22:59:36.526178
7973 22:59:36.526721 Set Vref, RX VrefLevel [Byte0]: 77
7974 22:59:36.529327 [Byte1]: 77
7975 22:59:36.533802
7976 22:59:36.534330 Set Vref, RX VrefLevel [Byte0]: 78
7977 22:59:36.536823 [Byte1]: 78
7978 22:59:36.541212
7979 22:59:36.541743 Final RX Vref Byte 0 = 56 to rank0
7980 22:59:36.544105 Final RX Vref Byte 1 = 58 to rank0
7981 22:59:36.547588 Final RX Vref Byte 0 = 56 to rank1
7982 22:59:36.551147 Final RX Vref Byte 1 = 58 to rank1==
7983 22:59:36.553909 Dram Type= 6, Freq= 0, CH_0, rank 0
7984 22:59:36.560703 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7985 22:59:36.561244 ==
7986 22:59:36.561593 DQS Delay:
7987 22:59:36.563709 DQS0 = 0, DQS1 = 0
7988 22:59:36.564178 DQM Delay:
7989 22:59:36.567272 DQM0 = 129, DQM1 = 124
7990 22:59:36.567700 DQ Delay:
7991 22:59:36.571001 DQ0 =130, DQ1 =130, DQ2 =128, DQ3 =126
7992 22:59:36.574253 DQ4 =130, DQ5 =120, DQ6 =138, DQ7 =134
7993 22:59:36.577593 DQ8 =112, DQ9 =112, DQ10 =126, DQ11 =120
7994 22:59:36.580344 DQ12 =130, DQ13 =128, DQ14 =134, DQ15 =132
7995 22:59:36.580776
7996 22:59:36.581114
7997 22:59:36.581429
7998 22:59:36.584429 [DramC_TX_OE_Calibration] TA2
7999 22:59:36.587214 Original DQ_B0 (3 6) =30, OEN = 27
8000 22:59:36.590541 Original DQ_B1 (3 6) =30, OEN = 27
8001 22:59:36.593854 24, 0x0, End_B0=24 End_B1=24
8002 22:59:36.596999 25, 0x0, End_B0=25 End_B1=25
8003 22:59:36.597438 26, 0x0, End_B0=26 End_B1=26
8004 22:59:36.600477 27, 0x0, End_B0=27 End_B1=27
8005 22:59:36.603694 28, 0x0, End_B0=28 End_B1=28
8006 22:59:36.607176 29, 0x0, End_B0=29 End_B1=29
8007 22:59:36.607720 30, 0x0, End_B0=30 End_B1=30
8008 22:59:36.610698 31, 0x4141, End_B0=30 End_B1=30
8009 22:59:36.613022 Byte0 end_step=30 best_step=27
8010 22:59:36.616933 Byte1 end_step=30 best_step=27
8011 22:59:36.620195 Byte0 TX OE(2T, 0.5T) = (3, 3)
8012 22:59:36.622970 Byte1 TX OE(2T, 0.5T) = (3, 3)
8013 22:59:36.623406
8014 22:59:36.623812
8015 22:59:36.629645 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a17, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 396 ps
8016 22:59:36.632696 CH0 RK0: MR19=303, MR18=1A17
8017 22:59:36.639684 CH0_RK0: MR19=0x303, MR18=0x1A17, DQSOSC=396, MR23=63, INC=23, DEC=15
8018 22:59:36.640135
8019 22:59:36.643125 ----->DramcWriteLeveling(PI) begin...
8020 22:59:36.643562 ==
8021 22:59:36.645870 Dram Type= 6, Freq= 0, CH_0, rank 1
8022 22:59:36.649305 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8023 22:59:36.649752 ==
8024 22:59:36.652484 Write leveling (Byte 0): 32 => 32
8025 22:59:36.656269 Write leveling (Byte 1): 26 => 26
8026 22:59:36.659413 DramcWriteLeveling(PI) end<-----
8027 22:59:36.659837
8028 22:59:36.660206 ==
8029 22:59:36.662773 Dram Type= 6, Freq= 0, CH_0, rank 1
8030 22:59:36.669178 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8031 22:59:36.669743 ==
8032 22:59:36.670107 [Gating] SW mode calibration
8033 22:59:36.678994 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8034 22:59:36.682498 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8035 22:59:36.689419 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8036 22:59:36.692758 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8037 22:59:36.695600 1 4 8 | B1->B0 | 2323 2524 | 0 1 | (0 0) (0 0)
8038 22:59:36.702257 1 4 12 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
8039 22:59:36.705626 1 4 16 | B1->B0 | 2727 3434 | 0 1 | (0 0) (1 1)
8040 22:59:36.708966 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8041 22:59:36.715269 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8042 22:59:36.718506 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8043 22:59:36.721611 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8044 22:59:36.728684 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8045 22:59:36.731646 1 5 8 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 1)
8046 22:59:36.735042 1 5 12 | B1->B0 | 3434 2424 | 1 0 | (1 1) (0 0)
8047 22:59:36.741815 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8048 22:59:36.744873 1 5 20 | B1->B0 | 2d2d 2323 | 0 0 | (1 0) (0 0)
8049 22:59:36.747935 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8050 22:59:36.754755 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8051 22:59:36.757736 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8052 22:59:36.760623 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8053 22:59:36.767163 1 6 8 | B1->B0 | 2323 3c3c | 0 0 | (0 0) (0 0)
8054 22:59:36.770844 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8055 22:59:36.773827 1 6 16 | B1->B0 | 2727 4646 | 0 0 | (0 0) (0 0)
8056 22:59:36.780093 1 6 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8057 22:59:36.784070 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8058 22:59:36.786751 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8059 22:59:36.793584 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8060 22:59:36.796934 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8061 22:59:36.800386 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8062 22:59:36.806765 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8063 22:59:36.810289 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8064 22:59:36.813588 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8065 22:59:36.819845 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8066 22:59:36.823151 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8067 22:59:36.826404 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8068 22:59:36.833032 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8069 22:59:36.836536 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8070 22:59:36.839760 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8071 22:59:36.845971 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8072 22:59:36.849913 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8073 22:59:36.852927 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8074 22:59:36.859436 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8075 22:59:36.862776 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8076 22:59:36.865855 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8077 22:59:36.872697 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8078 22:59:36.875838 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8079 22:59:36.878937 Total UI for P1: 0, mck2ui 16
8080 22:59:36.882349 best dqsien dly found for B0: ( 1, 9, 8)
8081 22:59:36.885720 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8082 22:59:36.892424 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8083 22:59:36.895725 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8084 22:59:36.899182 Total UI for P1: 0, mck2ui 16
8085 22:59:36.902586 best dqsien dly found for B1: ( 1, 9, 18)
8086 22:59:36.905993 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8087 22:59:36.908884 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8088 22:59:36.908987
8089 22:59:36.912018 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8090 22:59:36.915470 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8091 22:59:36.918687 [Gating] SW calibration Done
8092 22:59:36.918809 ==
8093 22:59:36.922022 Dram Type= 6, Freq= 0, CH_0, rank 1
8094 22:59:36.928681 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8095 22:59:36.928780 ==
8096 22:59:36.928862 RX Vref Scan: 0
8097 22:59:36.928940
8098 22:59:36.932283 RX Vref 0 -> 0, step: 1
8099 22:59:36.932366
8100 22:59:36.935301 RX Delay 0 -> 252, step: 8
8101 22:59:36.938287 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8102 22:59:36.941680 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8103 22:59:36.944906 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8104 22:59:36.948372 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8105 22:59:36.954879 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8106 22:59:36.958605 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8107 22:59:36.961636 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8108 22:59:36.964678 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8109 22:59:36.967933 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8110 22:59:36.974677 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8111 22:59:36.977868 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8112 22:59:36.981519 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8113 22:59:36.984462 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8114 22:59:36.990996 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8115 22:59:36.994722 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8116 22:59:36.998001 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8117 22:59:36.998084 ==
8118 22:59:37.000739 Dram Type= 6, Freq= 0, CH_0, rank 1
8119 22:59:37.004226 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8120 22:59:37.007646 ==
8121 22:59:37.007730 DQS Delay:
8122 22:59:37.007831 DQS0 = 0, DQS1 = 0
8123 22:59:37.010971 DQM Delay:
8124 22:59:37.011055 DQM0 = 131, DQM1 = 124
8125 22:59:37.014047 DQ Delay:
8126 22:59:37.017224 DQ0 =127, DQ1 =135, DQ2 =127, DQ3 =127
8127 22:59:37.020845 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
8128 22:59:37.023976 DQ8 =115, DQ9 =111, DQ10 =127, DQ11 =115
8129 22:59:37.027260 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
8130 22:59:37.027344
8131 22:59:37.027427
8132 22:59:37.027505 ==
8133 22:59:37.030697 Dram Type= 6, Freq= 0, CH_0, rank 1
8134 22:59:37.033933 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8135 22:59:37.034017 ==
8136 22:59:37.037417
8137 22:59:37.037500
8138 22:59:37.037584 TX Vref Scan disable
8139 22:59:37.040284 == TX Byte 0 ==
8140 22:59:37.043548 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8141 22:59:37.046943 Update DQM dly =988 (3 ,6, 28) DQM OEN =(3 ,3)
8142 22:59:37.050264 == TX Byte 1 ==
8143 22:59:37.053612 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8144 22:59:37.057093 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8145 22:59:37.060136 ==
8146 22:59:37.060220 Dram Type= 6, Freq= 0, CH_0, rank 1
8147 22:59:37.066971 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8148 22:59:37.067063 ==
8149 22:59:37.079406
8150 22:59:37.082705 TX Vref early break, caculate TX vref
8151 22:59:37.085672 TX Vref=16, minBit 8, minWin=23, winSum=382
8152 22:59:37.089344 TX Vref=18, minBit 8, minWin=23, winSum=390
8153 22:59:37.092404 TX Vref=20, minBit 2, minWin=24, winSum=395
8154 22:59:37.096161 TX Vref=22, minBit 9, minWin=24, winSum=406
8155 22:59:37.099153 TX Vref=24, minBit 1, minWin=25, winSum=414
8156 22:59:37.105743 TX Vref=26, minBit 3, minWin=25, winSum=423
8157 22:59:37.108809 TX Vref=28, minBit 3, minWin=25, winSum=419
8158 22:59:37.111962 TX Vref=30, minBit 8, minWin=24, winSum=412
8159 22:59:37.115403 TX Vref=32, minBit 1, minWin=25, winSum=407
8160 22:59:37.118885 TX Vref=34, minBit 0, minWin=24, winSum=399
8161 22:59:37.125032 [TxChooseVref] Worse bit 3, Min win 25, Win sum 423, Final Vref 26
8162 22:59:37.125116
8163 22:59:37.128306 Final TX Range 0 Vref 26
8164 22:59:37.128391
8165 22:59:37.128475 ==
8166 22:59:37.131704 Dram Type= 6, Freq= 0, CH_0, rank 1
8167 22:59:37.134921 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8168 22:59:37.135006 ==
8169 22:59:37.135090
8170 22:59:37.138374
8171 22:59:37.138459 TX Vref Scan disable
8172 22:59:37.145064 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8173 22:59:37.145149 == TX Byte 0 ==
8174 22:59:37.148451 u2DelayCellOfst[0]=10 cells (3 PI)
8175 22:59:37.152088 u2DelayCellOfst[1]=14 cells (4 PI)
8176 22:59:37.155478 u2DelayCellOfst[2]=7 cells (2 PI)
8177 22:59:37.158686 u2DelayCellOfst[3]=7 cells (2 PI)
8178 22:59:37.162012 u2DelayCellOfst[4]=7 cells (2 PI)
8179 22:59:37.164901 u2DelayCellOfst[5]=0 cells (0 PI)
8180 22:59:37.168944 u2DelayCellOfst[6]=14 cells (4 PI)
8181 22:59:37.171747 u2DelayCellOfst[7]=14 cells (4 PI)
8182 22:59:37.175560 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
8183 22:59:37.178756 Update DQM dly =988 (3 ,6, 28) DQM OEN =(3 ,3)
8184 22:59:37.181746 == TX Byte 1 ==
8185 22:59:37.185277 u2DelayCellOfst[8]=0 cells (0 PI)
8186 22:59:37.188372 u2DelayCellOfst[9]=0 cells (0 PI)
8187 22:59:37.191609 u2DelayCellOfst[10]=3 cells (1 PI)
8188 22:59:37.191997 u2DelayCellOfst[11]=3 cells (1 PI)
8189 22:59:37.194700 u2DelayCellOfst[12]=10 cells (3 PI)
8190 22:59:37.197855 u2DelayCellOfst[13]=10 cells (3 PI)
8191 22:59:37.201443 u2DelayCellOfst[14]=14 cells (4 PI)
8192 22:59:37.204318 u2DelayCellOfst[15]=10 cells (3 PI)
8193 22:59:37.210697 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8194 22:59:37.214045 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8195 22:59:37.214129 DramC Write-DBI on
8196 22:59:37.217475 ==
8197 22:59:37.220870 Dram Type= 6, Freq= 0, CH_0, rank 1
8198 22:59:37.223809 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8199 22:59:37.223893 ==
8200 22:59:37.223959
8201 22:59:37.224021
8202 22:59:37.227109 TX Vref Scan disable
8203 22:59:37.227192 == TX Byte 0 ==
8204 22:59:37.233620 Update DQM dly =731 (2 ,6, 27) DQM OEN =(3 ,3)
8205 22:59:37.233704 == TX Byte 1 ==
8206 22:59:37.237102 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8207 22:59:37.240227 DramC Write-DBI off
8208 22:59:37.240310
8209 22:59:37.240375 [DATLAT]
8210 22:59:37.243477 Freq=1600, CH0 RK1
8211 22:59:37.243561
8212 22:59:37.243627 DATLAT Default: 0xf
8213 22:59:37.246788 0, 0xFFFF, sum = 0
8214 22:59:37.246899 1, 0xFFFF, sum = 0
8215 22:59:37.250199 2, 0xFFFF, sum = 0
8216 22:59:37.253555 3, 0xFFFF, sum = 0
8217 22:59:37.253640 4, 0xFFFF, sum = 0
8218 22:59:37.256907 5, 0xFFFF, sum = 0
8219 22:59:37.256992 6, 0xFFFF, sum = 0
8220 22:59:37.260193 7, 0xFFFF, sum = 0
8221 22:59:37.260277 8, 0xFFFF, sum = 0
8222 22:59:37.263640 9, 0xFFFF, sum = 0
8223 22:59:37.263725 10, 0xFFFF, sum = 0
8224 22:59:37.267071 11, 0xFFFF, sum = 0
8225 22:59:37.267156 12, 0xFFFF, sum = 0
8226 22:59:37.269686 13, 0xFFFF, sum = 0
8227 22:59:37.269770 14, 0x0, sum = 1
8228 22:59:37.273005 15, 0x0, sum = 2
8229 22:59:37.273089 16, 0x0, sum = 3
8230 22:59:37.276364 17, 0x0, sum = 4
8231 22:59:37.276449 best_step = 15
8232 22:59:37.276515
8233 22:59:37.276578 ==
8234 22:59:37.279648 Dram Type= 6, Freq= 0, CH_0, rank 1
8235 22:59:37.286396 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8236 22:59:37.286481 ==
8237 22:59:37.286547 RX Vref Scan: 0
8238 22:59:37.286608
8239 22:59:37.289583 RX Vref 0 -> 0, step: 1
8240 22:59:37.289666
8241 22:59:37.293210 RX Delay 11 -> 252, step: 4
8242 22:59:37.296346 iDelay=191, Bit 0, Center 126 (75 ~ 178) 104
8243 22:59:37.299735 iDelay=191, Bit 1, Center 132 (79 ~ 186) 108
8244 22:59:37.305886 iDelay=191, Bit 2, Center 122 (71 ~ 174) 104
8245 22:59:37.309491 iDelay=191, Bit 3, Center 126 (75 ~ 178) 104
8246 22:59:37.312598 iDelay=191, Bit 4, Center 132 (83 ~ 182) 100
8247 22:59:37.315917 iDelay=191, Bit 5, Center 118 (63 ~ 174) 112
8248 22:59:37.319341 iDelay=191, Bit 6, Center 138 (87 ~ 190) 104
8249 22:59:37.325579 iDelay=191, Bit 7, Center 134 (83 ~ 186) 104
8250 22:59:37.329033 iDelay=191, Bit 8, Center 114 (63 ~ 166) 104
8251 22:59:37.332176 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8252 22:59:37.335753 iDelay=191, Bit 10, Center 126 (75 ~ 178) 104
8253 22:59:37.338726 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8254 22:59:37.345702 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8255 22:59:37.348558 iDelay=191, Bit 13, Center 128 (79 ~ 178) 100
8256 22:59:37.351831 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8257 22:59:37.355341 iDelay=191, Bit 15, Center 130 (79 ~ 182) 104
8258 22:59:37.355424 ==
8259 22:59:37.358739 Dram Type= 6, Freq= 0, CH_0, rank 1
8260 22:59:37.365326 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8261 22:59:37.365439 ==
8262 22:59:37.365508 DQS Delay:
8263 22:59:37.368826 DQS0 = 0, DQS1 = 0
8264 22:59:37.368920 DQM Delay:
8265 22:59:37.371976 DQM0 = 128, DQM1 = 123
8266 22:59:37.372102 DQ Delay:
8267 22:59:37.375297 DQ0 =126, DQ1 =132, DQ2 =122, DQ3 =126
8268 22:59:37.378152 DQ4 =132, DQ5 =118, DQ6 =138, DQ7 =134
8269 22:59:37.381551 DQ8 =114, DQ9 =110, DQ10 =126, DQ11 =118
8270 22:59:37.385257 DQ12 =128, DQ13 =128, DQ14 =136, DQ15 =130
8271 22:59:37.385339
8272 22:59:37.385404
8273 22:59:37.385463
8274 22:59:37.388602 [DramC_TX_OE_Calibration] TA2
8275 22:59:37.391965 Original DQ_B0 (3 6) =30, OEN = 27
8276 22:59:37.395143 Original DQ_B1 (3 6) =30, OEN = 27
8277 22:59:37.398032 24, 0x0, End_B0=24 End_B1=24
8278 22:59:37.401601 25, 0x0, End_B0=25 End_B1=25
8279 22:59:37.401687 26, 0x0, End_B0=26 End_B1=26
8280 22:59:37.404809 27, 0x0, End_B0=27 End_B1=27
8281 22:59:37.407981 28, 0x0, End_B0=28 End_B1=28
8282 22:59:37.411177 29, 0x0, End_B0=29 End_B1=29
8283 22:59:37.414668 30, 0x0, End_B0=30 End_B1=30
8284 22:59:37.414753 31, 0x4141, End_B0=30 End_B1=30
8285 22:59:37.417850 Byte0 end_step=30 best_step=27
8286 22:59:37.421329 Byte1 end_step=30 best_step=27
8287 22:59:37.424896 Byte0 TX OE(2T, 0.5T) = (3, 3)
8288 22:59:37.427850 Byte1 TX OE(2T, 0.5T) = (3, 3)
8289 22:59:37.427932
8290 22:59:37.427997
8291 22:59:37.434160 [DQSOSCAuto] RK1, (LSB)MR18= 0x1311, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 400 ps
8292 22:59:37.437401 CH0 RK1: MR19=303, MR18=1311
8293 22:59:37.444012 CH0_RK1: MR19=0x303, MR18=0x1311, DQSOSC=400, MR23=63, INC=23, DEC=15
8294 22:59:37.447429 [RxdqsGatingPostProcess] freq 1600
8295 22:59:37.454314 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8296 22:59:37.457403 best DQS0 dly(2T, 0.5T) = (1, 1)
8297 22:59:37.457485 best DQS1 dly(2T, 0.5T) = (1, 1)
8298 22:59:37.460770 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8299 22:59:37.463517 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8300 22:59:37.467310 best DQS0 dly(2T, 0.5T) = (1, 1)
8301 22:59:37.470319 best DQS1 dly(2T, 0.5T) = (1, 1)
8302 22:59:37.474029 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8303 22:59:37.476922 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8304 22:59:37.480537 Pre-setting of DQS Precalculation
8305 22:59:37.486769 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8306 22:59:37.486851 ==
8307 22:59:37.489887 Dram Type= 6, Freq= 0, CH_1, rank 0
8308 22:59:37.493410 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8309 22:59:37.493493 ==
8310 22:59:37.499714 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8311 22:59:37.503808 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8312 22:59:37.506694 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8313 22:59:37.513159 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8314 22:59:37.521705 [CA 0] Center 42 (13~72) winsize 60
8315 22:59:37.525248 [CA 1] Center 42 (12~72) winsize 61
8316 22:59:37.528147 [CA 2] Center 38 (9~68) winsize 60
8317 22:59:37.531586 [CA 3] Center 37 (8~67) winsize 60
8318 22:59:37.534977 [CA 4] Center 38 (8~68) winsize 61
8319 22:59:37.538221 [CA 5] Center 37 (8~66) winsize 59
8320 22:59:37.538301
8321 22:59:37.541474 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8322 22:59:37.541554
8323 22:59:37.548019 [CATrainingPosCal] consider 1 rank data
8324 22:59:37.548171 u2DelayCellTimex100 = 271/100 ps
8325 22:59:37.554771 CA0 delay=42 (13~72),Diff = 5 PI (18 cell)
8326 22:59:37.558224 CA1 delay=42 (12~72),Diff = 5 PI (18 cell)
8327 22:59:37.561405 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8328 22:59:37.564745 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8329 22:59:37.567635 CA4 delay=38 (8~68),Diff = 1 PI (3 cell)
8330 22:59:37.571062 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8331 22:59:37.571142
8332 22:59:37.574549 CA PerBit enable=1, Macro0, CA PI delay=37
8333 22:59:37.574629
8334 22:59:37.577968 [CBTSetCACLKResult] CA Dly = 37
8335 22:59:37.581006 CS Dly: 8 (0~39)
8336 22:59:37.584285 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8337 22:59:37.587168 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8338 22:59:37.587248 ==
8339 22:59:37.590516 Dram Type= 6, Freq= 0, CH_1, rank 1
8340 22:59:37.597973 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8341 22:59:37.598054 ==
8342 22:59:37.600371 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8343 22:59:37.607289 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8344 22:59:37.610345 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8345 22:59:37.617007 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8346 22:59:37.625177 [CA 0] Center 42 (12~72) winsize 61
8347 22:59:37.628120 [CA 1] Center 42 (12~72) winsize 61
8348 22:59:37.631390 [CA 2] Center 38 (9~68) winsize 60
8349 22:59:37.634981 [CA 3] Center 37 (8~66) winsize 59
8350 22:59:37.638569 [CA 4] Center 37 (7~68) winsize 62
8351 22:59:37.642023 [CA 5] Center 37 (8~67) winsize 60
8352 22:59:37.642546
8353 22:59:37.645150 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8354 22:59:37.645575
8355 22:59:37.648621 [CATrainingPosCal] consider 2 rank data
8356 22:59:37.652197 u2DelayCellTimex100 = 271/100 ps
8357 22:59:37.655476 CA0 delay=42 (13~72),Diff = 5 PI (18 cell)
8358 22:59:37.661928 CA1 delay=42 (12~72),Diff = 5 PI (18 cell)
8359 22:59:37.664636 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8360 22:59:37.668003 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8361 22:59:37.671274 CA4 delay=38 (8~68),Diff = 1 PI (3 cell)
8362 22:59:37.674542 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8363 22:59:37.674698
8364 22:59:37.677645 CA PerBit enable=1, Macro0, CA PI delay=37
8365 22:59:37.677761
8366 22:59:37.681123 [CBTSetCACLKResult] CA Dly = 37
8367 22:59:37.684337 CS Dly: 9 (0~42)
8368 22:59:37.688026 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8369 22:59:37.691267 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8370 22:59:37.691444
8371 22:59:37.694175 ----->DramcWriteLeveling(PI) begin...
8372 22:59:37.694320 ==
8373 22:59:37.697667 Dram Type= 6, Freq= 0, CH_1, rank 0
8374 22:59:37.704295 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8375 22:59:37.704505 ==
8376 22:59:37.707650 Write leveling (Byte 0): 26 => 26
8377 22:59:37.710711 Write leveling (Byte 1): 27 => 27
8378 22:59:37.710878 DramcWriteLeveling(PI) end<-----
8379 22:59:37.713730
8380 22:59:37.713891 ==
8381 22:59:37.716976 Dram Type= 6, Freq= 0, CH_1, rank 0
8382 22:59:37.720543 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8383 22:59:37.720732 ==
8384 22:59:37.723536 [Gating] SW mode calibration
8385 22:59:37.730600 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8386 22:59:37.737346 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8387 22:59:37.740416 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8388 22:59:37.744199 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8389 22:59:37.750469 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8390 22:59:37.753575 1 4 12 | B1->B0 | 2525 3434 | 1 1 | (1 1) (1 1)
8391 22:59:37.756939 1 4 16 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8392 22:59:37.763316 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8393 22:59:37.766453 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8394 22:59:37.769454 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8395 22:59:37.776689 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8396 22:59:37.779403 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8397 22:59:37.782864 1 5 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
8398 22:59:37.789596 1 5 12 | B1->B0 | 3232 2828 | 0 0 | (0 1) (1 0)
8399 22:59:37.792463 1 5 16 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
8400 22:59:37.795771 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8401 22:59:37.802571 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8402 22:59:37.805707 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8403 22:59:37.808982 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8404 22:59:37.815598 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8405 22:59:37.818950 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8406 22:59:37.823065 1 6 12 | B1->B0 | 2e2e 4646 | 0 0 | (0 0) (0 0)
8407 22:59:37.828799 1 6 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8408 22:59:37.832591 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8409 22:59:37.835671 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8410 22:59:37.841872 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8411 22:59:37.845746 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8412 22:59:37.848899 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8413 22:59:37.855092 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8414 22:59:37.858343 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8415 22:59:37.861759 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8416 22:59:37.868221 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8417 22:59:37.871842 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8418 22:59:37.875006 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8419 22:59:37.881294 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8420 22:59:37.884612 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8421 22:59:37.887902 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8422 22:59:37.894574 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8423 22:59:37.897830 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8424 22:59:37.901180 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8425 22:59:37.907742 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8426 22:59:37.910977 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8427 22:59:37.914481 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8428 22:59:37.920787 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8429 22:59:37.924570 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8430 22:59:37.927501 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8431 22:59:37.934149 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8432 22:59:37.934232 Total UI for P1: 0, mck2ui 16
8433 22:59:37.940868 best dqsien dly found for B0: ( 1, 9, 10)
8434 22:59:37.944261 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8435 22:59:37.947131 Total UI for P1: 0, mck2ui 16
8436 22:59:37.950571 best dqsien dly found for B1: ( 1, 9, 14)
8437 22:59:37.954298 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8438 22:59:37.957114 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8439 22:59:37.957195
8440 22:59:37.960798 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8441 22:59:37.964035 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8442 22:59:37.966911 [Gating] SW calibration Done
8443 22:59:37.966988 ==
8444 22:59:37.970250 Dram Type= 6, Freq= 0, CH_1, rank 0
8445 22:59:37.977132 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8446 22:59:37.977240 ==
8447 22:59:37.977334 RX Vref Scan: 0
8448 22:59:37.977427
8449 22:59:37.980520 RX Vref 0 -> 0, step: 1
8450 22:59:37.980622
8451 22:59:37.983791 RX Delay 0 -> 252, step: 8
8452 22:59:37.987188 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8453 22:59:37.990112 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8454 22:59:37.993573 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8455 22:59:37.996933 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8456 22:59:38.003474 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8457 22:59:38.006665 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8458 22:59:38.009987 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8459 22:59:38.013196 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8460 22:59:38.016686 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8461 22:59:38.023274 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8462 22:59:38.026724 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8463 22:59:38.030101 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8464 22:59:38.033154 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8465 22:59:38.036730 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8466 22:59:38.042916 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8467 22:59:38.046760 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8468 22:59:38.046864 ==
8469 22:59:38.049754 Dram Type= 6, Freq= 0, CH_1, rank 0
8470 22:59:38.053169 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8471 22:59:38.053268 ==
8472 22:59:38.056262 DQS Delay:
8473 22:59:38.056368 DQS0 = 0, DQS1 = 0
8474 22:59:38.059479 DQM Delay:
8475 22:59:38.059585 DQM0 = 134, DQM1 = 130
8476 22:59:38.059667 DQ Delay:
8477 22:59:38.063116 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8478 22:59:38.069442 DQ4 =131, DQ5 =143, DQ6 =147, DQ7 =127
8479 22:59:38.073232 DQ8 =111, DQ9 =119, DQ10 =127, DQ11 =123
8480 22:59:38.076020 DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =139
8481 22:59:38.076173
8482 22:59:38.076288
8483 22:59:38.076392 ==
8484 22:59:38.079325 Dram Type= 6, Freq= 0, CH_1, rank 0
8485 22:59:38.082562 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8486 22:59:38.082798 ==
8487 22:59:38.082999
8488 22:59:38.083195
8489 22:59:38.085938 TX Vref Scan disable
8490 22:59:38.089518 == TX Byte 0 ==
8491 22:59:38.092818 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8492 22:59:38.096070 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8493 22:59:38.099660 == TX Byte 1 ==
8494 22:59:38.103068 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8495 22:59:38.105960 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8496 22:59:38.106358 ==
8497 22:59:38.109287 Dram Type= 6, Freq= 0, CH_1, rank 0
8498 22:59:38.115992 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8499 22:59:38.116520 ==
8500 22:59:38.128181
8501 22:59:38.131632 TX Vref early break, caculate TX vref
8502 22:59:38.134937 TX Vref=16, minBit 8, minWin=21, winSum=369
8503 22:59:38.138245 TX Vref=18, minBit 6, minWin=22, winSum=373
8504 22:59:38.141737 TX Vref=20, minBit 3, minWin=23, winSum=388
8505 22:59:38.144457 TX Vref=22, minBit 9, minWin=23, winSum=396
8506 22:59:38.148258 TX Vref=24, minBit 8, minWin=24, winSum=405
8507 22:59:38.154598 TX Vref=26, minBit 3, minWin=25, winSum=414
8508 22:59:38.157752 TX Vref=28, minBit 3, minWin=25, winSum=421
8509 22:59:38.161483 TX Vref=30, minBit 9, minWin=24, winSum=411
8510 22:59:38.164439 TX Vref=32, minBit 0, minWin=25, winSum=411
8511 22:59:38.167635 TX Vref=34, minBit 15, minWin=23, winSum=400
8512 22:59:38.174049 TX Vref=36, minBit 9, minWin=22, winSum=381
8513 22:59:38.177481 [TxChooseVref] Worse bit 3, Min win 25, Win sum 421, Final Vref 28
8514 22:59:38.177980
8515 22:59:38.181372 Final TX Range 0 Vref 28
8516 22:59:38.181961
8517 22:59:38.182419 ==
8518 22:59:38.184248 Dram Type= 6, Freq= 0, CH_1, rank 0
8519 22:59:38.187682 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8520 22:59:38.188236 ==
8521 22:59:38.191174
8522 22:59:38.191747
8523 22:59:38.192225 TX Vref Scan disable
8524 22:59:38.197285 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8525 22:59:38.197720 == TX Byte 0 ==
8526 22:59:38.200872 u2DelayCellOfst[0]=14 cells (4 PI)
8527 22:59:38.204110 u2DelayCellOfst[1]=10 cells (3 PI)
8528 22:59:38.207642 u2DelayCellOfst[2]=0 cells (0 PI)
8529 22:59:38.210692 u2DelayCellOfst[3]=7 cells (2 PI)
8530 22:59:38.213969 u2DelayCellOfst[4]=10 cells (3 PI)
8531 22:59:38.217490 u2DelayCellOfst[5]=18 cells (5 PI)
8532 22:59:38.220831 u2DelayCellOfst[6]=18 cells (5 PI)
8533 22:59:38.224010 u2DelayCellOfst[7]=7 cells (2 PI)
8534 22:59:38.227192 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8535 22:59:38.230458 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8536 22:59:38.233808 == TX Byte 1 ==
8537 22:59:38.236972 u2DelayCellOfst[8]=0 cells (0 PI)
8538 22:59:38.240357 u2DelayCellOfst[9]=3 cells (1 PI)
8539 22:59:38.243613 u2DelayCellOfst[10]=10 cells (3 PI)
8540 22:59:38.247014 u2DelayCellOfst[11]=7 cells (2 PI)
8541 22:59:38.250403 u2DelayCellOfst[12]=14 cells (4 PI)
8542 22:59:38.253678 u2DelayCellOfst[13]=18 cells (5 PI)
8543 22:59:38.256959 u2DelayCellOfst[14]=18 cells (5 PI)
8544 22:59:38.260023 u2DelayCellOfst[15]=18 cells (5 PI)
8545 22:59:38.263111 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8546 22:59:38.266469 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8547 22:59:38.269691 DramC Write-DBI on
8548 22:59:38.270292 ==
8549 22:59:38.273298 Dram Type= 6, Freq= 0, CH_1, rank 0
8550 22:59:38.276339 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8551 22:59:38.276835 ==
8552 22:59:38.277255
8553 22:59:38.277760
8554 22:59:38.279851 TX Vref Scan disable
8555 22:59:38.283046 == TX Byte 0 ==
8556 22:59:38.286175 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8557 22:59:38.286793 == TX Byte 1 ==
8558 22:59:38.292815 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8559 22:59:38.293259 DramC Write-DBI off
8560 22:59:38.293601
8561 22:59:38.293915 [DATLAT]
8562 22:59:38.296205 Freq=1600, CH1 RK0
8563 22:59:38.296637
8564 22:59:38.299665 DATLAT Default: 0xf
8565 22:59:38.300130 0, 0xFFFF, sum = 0
8566 22:59:38.302957 1, 0xFFFF, sum = 0
8567 22:59:38.303394 2, 0xFFFF, sum = 0
8568 22:59:38.306214 3, 0xFFFF, sum = 0
8569 22:59:38.306649 4, 0xFFFF, sum = 0
8570 22:59:38.309056 5, 0xFFFF, sum = 0
8571 22:59:38.309492 6, 0xFFFF, sum = 0
8572 22:59:38.312129 7, 0xFFFF, sum = 0
8573 22:59:38.312214 8, 0xFFFF, sum = 0
8574 22:59:38.315222 9, 0xFFFF, sum = 0
8575 22:59:38.315307 10, 0xFFFF, sum = 0
8576 22:59:38.318802 11, 0xFFFF, sum = 0
8577 22:59:38.318887 12, 0xFFFF, sum = 0
8578 22:59:38.322176 13, 0xFFFF, sum = 0
8579 22:59:38.322261 14, 0x0, sum = 1
8580 22:59:38.325266 15, 0x0, sum = 2
8581 22:59:38.325351 16, 0x0, sum = 3
8582 22:59:38.328972 17, 0x0, sum = 4
8583 22:59:38.329057 best_step = 15
8584 22:59:38.329123
8585 22:59:38.329185 ==
8586 22:59:38.331614 Dram Type= 6, Freq= 0, CH_1, rank 0
8587 22:59:38.338328 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8588 22:59:38.338412 ==
8589 22:59:38.338478 RX Vref Scan: 1
8590 22:59:38.338538
8591 22:59:38.341937 Set Vref Range= 24 -> 127
8592 22:59:38.342020
8593 22:59:38.344926 RX Vref 24 -> 127, step: 1
8594 22:59:38.345009
8595 22:59:38.348297 RX Delay 11 -> 252, step: 4
8596 22:59:38.348380
8597 22:59:38.351576 Set Vref, RX VrefLevel [Byte0]: 24
8598 22:59:38.354981 [Byte1]: 24
8599 22:59:38.355065
8600 22:59:38.358162 Set Vref, RX VrefLevel [Byte0]: 25
8601 22:59:38.361337 [Byte1]: 25
8602 22:59:38.361421
8603 22:59:38.364504 Set Vref, RX VrefLevel [Byte0]: 26
8604 22:59:38.367955 [Byte1]: 26
8605 22:59:38.371212
8606 22:59:38.371296 Set Vref, RX VrefLevel [Byte0]: 27
8607 22:59:38.374814 [Byte1]: 27
8608 22:59:38.379171
8609 22:59:38.379253 Set Vref, RX VrefLevel [Byte0]: 28
8610 22:59:38.382153 [Byte1]: 28
8611 22:59:38.386877
8612 22:59:38.386960 Set Vref, RX VrefLevel [Byte0]: 29
8613 22:59:38.390089 [Byte1]: 29
8614 22:59:38.394251
8615 22:59:38.394333 Set Vref, RX VrefLevel [Byte0]: 30
8616 22:59:38.397895 [Byte1]: 30
8617 22:59:38.402261
8618 22:59:38.402343 Set Vref, RX VrefLevel [Byte0]: 31
8619 22:59:38.405549 [Byte1]: 31
8620 22:59:38.409630
8621 22:59:38.409711 Set Vref, RX VrefLevel [Byte0]: 32
8622 22:59:38.412905 [Byte1]: 32
8623 22:59:38.417597
8624 22:59:38.417681 Set Vref, RX VrefLevel [Byte0]: 33
8625 22:59:38.420683 [Byte1]: 33
8626 22:59:38.424686
8627 22:59:38.424767 Set Vref, RX VrefLevel [Byte0]: 34
8628 22:59:38.427891 [Byte1]: 34
8629 22:59:38.432300
8630 22:59:38.432399 Set Vref, RX VrefLevel [Byte0]: 35
8631 22:59:38.435804 [Byte1]: 35
8632 22:59:38.440081
8633 22:59:38.440177 Set Vref, RX VrefLevel [Byte0]: 36
8634 22:59:38.443466 [Byte1]: 36
8635 22:59:38.447582
8636 22:59:38.447664 Set Vref, RX VrefLevel [Byte0]: 37
8637 22:59:38.451082 [Byte1]: 37
8638 22:59:38.455312
8639 22:59:38.455744 Set Vref, RX VrefLevel [Byte0]: 38
8640 22:59:38.458756 [Byte1]: 38
8641 22:59:38.463428
8642 22:59:38.463970 Set Vref, RX VrefLevel [Byte0]: 39
8643 22:59:38.466526 [Byte1]: 39
8644 22:59:38.470687
8645 22:59:38.471120 Set Vref, RX VrefLevel [Byte0]: 40
8646 22:59:38.474657 [Byte1]: 40
8647 22:59:38.478534
8648 22:59:38.478965 Set Vref, RX VrefLevel [Byte0]: 41
8649 22:59:38.481772 [Byte1]: 41
8650 22:59:38.485630
8651 22:59:38.485711 Set Vref, RX VrefLevel [Byte0]: 42
8652 22:59:38.488753 [Byte1]: 42
8653 22:59:38.493332
8654 22:59:38.493414 Set Vref, RX VrefLevel [Byte0]: 43
8655 22:59:38.496327 [Byte1]: 43
8656 22:59:38.500839
8657 22:59:38.500920 Set Vref, RX VrefLevel [Byte0]: 44
8658 22:59:38.504421 [Byte1]: 44
8659 22:59:38.508456
8660 22:59:38.508538 Set Vref, RX VrefLevel [Byte0]: 45
8661 22:59:38.511808 [Byte1]: 45
8662 22:59:38.516261
8663 22:59:38.516343 Set Vref, RX VrefLevel [Byte0]: 46
8664 22:59:38.519907 [Byte1]: 46
8665 22:59:38.523649
8666 22:59:38.523731 Set Vref, RX VrefLevel [Byte0]: 47
8667 22:59:38.527074 [Byte1]: 47
8668 22:59:38.531494
8669 22:59:38.531577 Set Vref, RX VrefLevel [Byte0]: 48
8670 22:59:38.534724 [Byte1]: 48
8671 22:59:38.539299
8672 22:59:38.539721 Set Vref, RX VrefLevel [Byte0]: 49
8673 22:59:38.542730 [Byte1]: 49
8674 22:59:38.547060
8675 22:59:38.547485 Set Vref, RX VrefLevel [Byte0]: 50
8676 22:59:38.550587 [Byte1]: 50
8677 22:59:38.554946
8678 22:59:38.555369 Set Vref, RX VrefLevel [Byte0]: 51
8679 22:59:38.558139 [Byte1]: 51
8680 22:59:38.562153
8681 22:59:38.562617 Set Vref, RX VrefLevel [Byte0]: 52
8682 22:59:38.565429 [Byte1]: 52
8683 22:59:38.569956
8684 22:59:38.570468 Set Vref, RX VrefLevel [Byte0]: 53
8685 22:59:38.573051 [Byte1]: 53
8686 22:59:38.577757
8687 22:59:38.578269 Set Vref, RX VrefLevel [Byte0]: 54
8688 22:59:38.580701 [Byte1]: 54
8689 22:59:38.585314
8690 22:59:38.585825 Set Vref, RX VrefLevel [Byte0]: 55
8691 22:59:38.588528 [Byte1]: 55
8692 22:59:38.592757
8693 22:59:38.593231 Set Vref, RX VrefLevel [Byte0]: 56
8694 22:59:38.595911 [Byte1]: 56
8695 22:59:38.600386
8696 22:59:38.600813 Set Vref, RX VrefLevel [Byte0]: 57
8697 22:59:38.603537 [Byte1]: 57
8698 22:59:38.607718
8699 22:59:38.608285 Set Vref, RX VrefLevel [Byte0]: 58
8700 22:59:38.611571 [Byte1]: 58
8701 22:59:38.615672
8702 22:59:38.616258 Set Vref, RX VrefLevel [Byte0]: 59
8703 22:59:38.618883 [Byte1]: 59
8704 22:59:38.623598
8705 22:59:38.624179 Set Vref, RX VrefLevel [Byte0]: 60
8706 22:59:38.626215 [Byte1]: 60
8707 22:59:38.630655
8708 22:59:38.631092 Set Vref, RX VrefLevel [Byte0]: 61
8709 22:59:38.634067 [Byte1]: 61
8710 22:59:38.638381
8711 22:59:38.638970 Set Vref, RX VrefLevel [Byte0]: 62
8712 22:59:38.641593 [Byte1]: 62
8713 22:59:38.646079
8714 22:59:38.646505 Set Vref, RX VrefLevel [Byte0]: 63
8715 22:59:38.648933 [Byte1]: 63
8716 22:59:38.653353
8717 22:59:38.653780 Set Vref, RX VrefLevel [Byte0]: 64
8718 22:59:38.656678 [Byte1]: 64
8719 22:59:38.661285
8720 22:59:38.661815 Set Vref, RX VrefLevel [Byte0]: 65
8721 22:59:38.664535 [Byte1]: 65
8722 22:59:38.668915
8723 22:59:38.669352 Set Vref, RX VrefLevel [Byte0]: 66
8724 22:59:38.675332 [Byte1]: 66
8725 22:59:38.675915
8726 22:59:38.678541 Set Vref, RX VrefLevel [Byte0]: 67
8727 22:59:38.681571 [Byte1]: 67
8728 22:59:38.682007
8729 22:59:38.685212 Set Vref, RX VrefLevel [Byte0]: 68
8730 22:59:38.688354 [Byte1]: 68
8731 22:59:38.691531
8732 22:59:38.691959 Set Vref, RX VrefLevel [Byte0]: 69
8733 22:59:38.694831 [Byte1]: 69
8734 22:59:38.699400
8735 22:59:38.700061 Final RX Vref Byte 0 = 58 to rank0
8736 22:59:38.702494 Final RX Vref Byte 1 = 62 to rank0
8737 22:59:38.706089 Final RX Vref Byte 0 = 58 to rank1
8738 22:59:38.709284 Final RX Vref Byte 1 = 62 to rank1==
8739 22:59:38.712485 Dram Type= 6, Freq= 0, CH_1, rank 0
8740 22:59:38.718821 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8741 22:59:38.719352 ==
8742 22:59:38.719900 DQS Delay:
8743 22:59:38.722180 DQS0 = 0, DQS1 = 0
8744 22:59:38.722694 DQM Delay:
8745 22:59:38.723156 DQM0 = 133, DQM1 = 128
8746 22:59:38.725898 DQ Delay:
8747 22:59:38.729007 DQ0 =140, DQ1 =130, DQ2 =118, DQ3 =130
8748 22:59:38.732305 DQ4 =128, DQ5 =142, DQ6 =146, DQ7 =130
8749 22:59:38.735609 DQ8 =114, DQ9 =116, DQ10 =128, DQ11 =122
8750 22:59:38.738547 DQ12 =138, DQ13 =138, DQ14 =136, DQ15 =138
8751 22:59:38.738978
8752 22:59:38.739436
8753 22:59:38.739837
8754 22:59:38.741779 [DramC_TX_OE_Calibration] TA2
8755 22:59:38.745008 Original DQ_B0 (3 6) =30, OEN = 27
8756 22:59:38.748257 Original DQ_B1 (3 6) =30, OEN = 27
8757 22:59:38.752165 24, 0x0, End_B0=24 End_B1=24
8758 22:59:38.754980 25, 0x0, End_B0=25 End_B1=25
8759 22:59:38.755481 26, 0x0, End_B0=26 End_B1=26
8760 22:59:38.758301 27, 0x0, End_B0=27 End_B1=27
8761 22:59:38.761910 28, 0x0, End_B0=28 End_B1=28
8762 22:59:38.765354 29, 0x0, End_B0=29 End_B1=29
8763 22:59:38.765899 30, 0x0, End_B0=30 End_B1=30
8764 22:59:38.768776 31, 0x4141, End_B0=30 End_B1=30
8765 22:59:38.771754 Byte0 end_step=30 best_step=27
8766 22:59:38.774696 Byte1 end_step=30 best_step=27
8767 22:59:38.778487 Byte0 TX OE(2T, 0.5T) = (3, 3)
8768 22:59:38.781392 Byte1 TX OE(2T, 0.5T) = (3, 3)
8769 22:59:38.781824
8770 22:59:38.782162
8771 22:59:38.787746 [DQSOSCAuto] RK0, (LSB)MR18= 0xf18, (MSB)MR19= 0x303, tDQSOscB0 = 397 ps tDQSOscB1 = 402 ps
8772 22:59:38.791418 CH1 RK0: MR19=303, MR18=F18
8773 22:59:38.798035 CH1_RK0: MR19=0x303, MR18=0xF18, DQSOSC=397, MR23=63, INC=23, DEC=15
8774 22:59:38.798466
8775 22:59:38.801044 ----->DramcWriteLeveling(PI) begin...
8776 22:59:38.801528 ==
8777 22:59:38.804571 Dram Type= 6, Freq= 0, CH_1, rank 1
8778 22:59:38.807603 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8779 22:59:38.808073 ==
8780 22:59:38.811286 Write leveling (Byte 0): 26 => 26
8781 22:59:38.814113 Write leveling (Byte 1): 28 => 28
8782 22:59:38.817718 DramcWriteLeveling(PI) end<-----
8783 22:59:38.817962
8784 22:59:38.818028 ==
8785 22:59:38.820388 Dram Type= 6, Freq= 0, CH_1, rank 1
8786 22:59:38.823943 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8787 22:59:38.827468 ==
8788 22:59:38.827551 [Gating] SW mode calibration
8789 22:59:38.836879 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8790 22:59:38.840201 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8791 22:59:38.843602 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8792 22:59:38.850145 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8793 22:59:38.853337 1 4 8 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
8794 22:59:38.856745 1 4 12 | B1->B0 | 2626 3434 | 0 1 | (0 0) (1 1)
8795 22:59:38.863574 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8796 22:59:38.866755 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8797 22:59:38.870208 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8798 22:59:38.876775 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8799 22:59:38.879463 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8800 22:59:38.886286 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8801 22:59:38.889893 1 5 8 | B1->B0 | 3434 2828 | 1 0 | (1 1) (0 0)
8802 22:59:38.893277 1 5 12 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (0 0)
8803 22:59:38.899313 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8804 22:59:38.902761 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8805 22:59:38.905793 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8806 22:59:38.912473 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8807 22:59:38.915709 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8808 22:59:38.919567 1 6 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (1 1)
8809 22:59:38.925541 1 6 8 | B1->B0 | 2323 3f3f | 0 0 | (0 0) (1 1)
8810 22:59:38.928648 1 6 12 | B1->B0 | 2f2f 4646 | 0 0 | (0 0) (0 0)
8811 22:59:38.932329 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8812 22:59:38.938980 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8813 22:59:38.942409 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8814 22:59:38.945792 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8815 22:59:38.951860 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8816 22:59:38.955466 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8817 22:59:38.958815 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8818 22:59:38.964870 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8819 22:59:38.968287 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8820 22:59:38.971696 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8821 22:59:38.978244 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8822 22:59:38.981637 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8823 22:59:38.984934 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8824 22:59:38.991176 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8825 22:59:38.994518 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8826 22:59:38.997874 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8827 22:59:39.004346 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8828 22:59:39.007880 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8829 22:59:39.011160 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8830 22:59:39.017619 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8831 22:59:39.020862 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8832 22:59:39.024500 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8833 22:59:39.030784 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8834 22:59:39.033914 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8835 22:59:39.037422 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8836 22:59:39.040811 Total UI for P1: 0, mck2ui 16
8837 22:59:39.044072 best dqsien dly found for B0: ( 1, 9, 10)
8838 22:59:39.050804 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8839 22:59:39.050886 Total UI for P1: 0, mck2ui 16
8840 22:59:39.056897 best dqsien dly found for B1: ( 1, 9, 14)
8841 22:59:39.060582 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8842 22:59:39.063640 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8843 22:59:39.063722
8844 22:59:39.066811 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8845 22:59:39.070088 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8846 22:59:39.073495 [Gating] SW calibration Done
8847 22:59:39.073577 ==
8848 22:59:39.076839 Dram Type= 6, Freq= 0, CH_1, rank 1
8849 22:59:39.080069 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8850 22:59:39.080152 ==
8851 22:59:39.083471 RX Vref Scan: 0
8852 22:59:39.083552
8853 22:59:39.086917 RX Vref 0 -> 0, step: 1
8854 22:59:39.086999
8855 22:59:39.087063 RX Delay 0 -> 252, step: 8
8856 22:59:39.093947 iDelay=200, Bit 0, Center 139 (80 ~ 199) 120
8857 22:59:39.096643 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8858 22:59:39.099961 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8859 22:59:39.103234 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8860 22:59:39.106652 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8861 22:59:39.113862 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8862 22:59:39.116529 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8863 22:59:39.119910 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8864 22:59:39.123070 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8865 22:59:39.126181 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8866 22:59:39.132833 iDelay=200, Bit 10, Center 135 (80 ~ 191) 112
8867 22:59:39.136091 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8868 22:59:39.139469 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8869 22:59:39.143160 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8870 22:59:39.149278 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8871 22:59:39.152575 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8872 22:59:39.152712 ==
8873 22:59:39.155955 Dram Type= 6, Freq= 0, CH_1, rank 1
8874 22:59:39.159055 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8875 22:59:39.159138 ==
8876 22:59:39.159203 DQS Delay:
8877 22:59:39.162462 DQS0 = 0, DQS1 = 0
8878 22:59:39.162544 DQM Delay:
8879 22:59:39.165810 DQM0 = 133, DQM1 = 131
8880 22:59:39.165892 DQ Delay:
8881 22:59:39.169181 DQ0 =139, DQ1 =131, DQ2 =119, DQ3 =131
8882 22:59:39.172592 DQ4 =135, DQ5 =143, DQ6 =139, DQ7 =131
8883 22:59:39.175957 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =127
8884 22:59:39.182601 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =135
8885 22:59:39.182683
8886 22:59:39.182747
8887 22:59:39.182805 ==
8888 22:59:39.186007 Dram Type= 6, Freq= 0, CH_1, rank 1
8889 22:59:39.188837 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8890 22:59:39.188919 ==
8891 22:59:39.188984
8892 22:59:39.189042
8893 22:59:39.192461 TX Vref Scan disable
8894 22:59:39.192544 == TX Byte 0 ==
8895 22:59:39.198926 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8896 22:59:39.202507 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8897 22:59:39.202589 == TX Byte 1 ==
8898 22:59:39.209048 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8899 22:59:39.212421 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8900 22:59:39.212503 ==
8901 22:59:39.215511 Dram Type= 6, Freq= 0, CH_1, rank 1
8902 22:59:39.218675 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8903 22:59:39.218758 ==
8904 22:59:39.233577
8905 22:59:39.236790 TX Vref early break, caculate TX vref
8906 22:59:39.240578 TX Vref=16, minBit 9, minWin=21, winSum=375
8907 22:59:39.243559 TX Vref=18, minBit 9, minWin=22, winSum=385
8908 22:59:39.246825 TX Vref=20, minBit 9, minWin=23, winSum=396
8909 22:59:39.249837 TX Vref=22, minBit 9, minWin=23, winSum=403
8910 22:59:39.253434 TX Vref=24, minBit 8, minWin=24, winSum=410
8911 22:59:39.259966 TX Vref=26, minBit 9, minWin=24, winSum=413
8912 22:59:39.263221 TX Vref=28, minBit 9, minWin=25, winSum=421
8913 22:59:39.266395 TX Vref=30, minBit 15, minWin=24, winSum=417
8914 22:59:39.269839 TX Vref=32, minBit 8, minWin=24, winSum=407
8915 22:59:39.273320 TX Vref=34, minBit 8, minWin=24, winSum=404
8916 22:59:39.279916 TX Vref=36, minBit 8, minWin=23, winSum=391
8917 22:59:39.282722 [TxChooseVref] Worse bit 9, Min win 25, Win sum 421, Final Vref 28
8918 22:59:39.282805
8919 22:59:39.286011 Final TX Range 0 Vref 28
8920 22:59:39.286094
8921 22:59:39.286160 ==
8922 22:59:39.289271 Dram Type= 6, Freq= 0, CH_1, rank 1
8923 22:59:39.292769 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8924 22:59:39.295692 ==
8925 22:59:39.295774
8926 22:59:39.295838
8927 22:59:39.295897 TX Vref Scan disable
8928 22:59:39.303076 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8929 22:59:39.303159 == TX Byte 0 ==
8930 22:59:39.306346 u2DelayCellOfst[0]=14 cells (4 PI)
8931 22:59:39.309395 u2DelayCellOfst[1]=10 cells (3 PI)
8932 22:59:39.312602 u2DelayCellOfst[2]=0 cells (0 PI)
8933 22:59:39.315968 u2DelayCellOfst[3]=7 cells (2 PI)
8934 22:59:39.319187 u2DelayCellOfst[4]=7 cells (2 PI)
8935 22:59:39.322837 u2DelayCellOfst[5]=18 cells (5 PI)
8936 22:59:39.325958 u2DelayCellOfst[6]=18 cells (5 PI)
8937 22:59:39.329079 u2DelayCellOfst[7]=7 cells (2 PI)
8938 22:59:39.332333 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8939 22:59:39.335633 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8940 22:59:39.339232 == TX Byte 1 ==
8941 22:59:39.342262 u2DelayCellOfst[8]=0 cells (0 PI)
8942 22:59:39.345820 u2DelayCellOfst[9]=3 cells (1 PI)
8943 22:59:39.348847 u2DelayCellOfst[10]=14 cells (4 PI)
8944 22:59:39.352570 u2DelayCellOfst[11]=7 cells (2 PI)
8945 22:59:39.355952 u2DelayCellOfst[12]=14 cells (4 PI)
8946 22:59:39.358974 u2DelayCellOfst[13]=18 cells (5 PI)
8947 22:59:39.362050 u2DelayCellOfst[14]=21 cells (6 PI)
8948 22:59:39.362133 u2DelayCellOfst[15]=18 cells (5 PI)
8949 22:59:39.369042 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8950 22:59:39.372309 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8951 22:59:39.375847 DramC Write-DBI on
8952 22:59:39.376312 ==
8953 22:59:39.379145 Dram Type= 6, Freq= 0, CH_1, rank 1
8954 22:59:39.382371 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8955 22:59:39.382799 ==
8956 22:59:39.383135
8957 22:59:39.383445
8958 22:59:39.385920 TX Vref Scan disable
8959 22:59:39.386346 == TX Byte 0 ==
8960 22:59:39.392431 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8961 22:59:39.392859 == TX Byte 1 ==
8962 22:59:39.395745 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8963 22:59:39.399039 DramC Write-DBI off
8964 22:59:39.399461
8965 22:59:39.399810 [DATLAT]
8966 22:59:39.402609 Freq=1600, CH1 RK1
8967 22:59:39.403032
8968 22:59:39.403365 DATLAT Default: 0xf
8969 22:59:39.405316 0, 0xFFFF, sum = 0
8970 22:59:39.405746 1, 0xFFFF, sum = 0
8971 22:59:39.408805 2, 0xFFFF, sum = 0
8972 22:59:39.412190 3, 0xFFFF, sum = 0
8973 22:59:39.412623 4, 0xFFFF, sum = 0
8974 22:59:39.415544 5, 0xFFFF, sum = 0
8975 22:59:39.415974 6, 0xFFFF, sum = 0
8976 22:59:39.418733 7, 0xFFFF, sum = 0
8977 22:59:39.419162 8, 0xFFFF, sum = 0
8978 22:59:39.422095 9, 0xFFFF, sum = 0
8979 22:59:39.422526 10, 0xFFFF, sum = 0
8980 22:59:39.425324 11, 0xFFFF, sum = 0
8981 22:59:39.425756 12, 0xFFFF, sum = 0
8982 22:59:39.428690 13, 0xFFFF, sum = 0
8983 22:59:39.429143 14, 0x0, sum = 1
8984 22:59:39.432302 15, 0x0, sum = 2
8985 22:59:39.432735 16, 0x0, sum = 3
8986 22:59:39.435272 17, 0x0, sum = 4
8987 22:59:39.435701 best_step = 15
8988 22:59:39.436058
8989 22:59:39.436383 ==
8990 22:59:39.438201 Dram Type= 6, Freq= 0, CH_1, rank 1
8991 22:59:39.445091 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8992 22:59:39.445657 ==
8993 22:59:39.446008 RX Vref Scan: 0
8994 22:59:39.446325
8995 22:59:39.448143 RX Vref 0 -> 0, step: 1
8996 22:59:39.448569
8997 22:59:39.451786 RX Delay 19 -> 252, step: 4
8998 22:59:39.454874 iDelay=195, Bit 0, Center 136 (87 ~ 186) 100
8999 22:59:39.458701 iDelay=195, Bit 1, Center 130 (79 ~ 182) 104
9000 22:59:39.461498 iDelay=195, Bit 2, Center 120 (67 ~ 174) 108
9001 22:59:39.468312 iDelay=195, Bit 3, Center 130 (79 ~ 182) 104
9002 22:59:39.471663 iDelay=195, Bit 4, Center 130 (75 ~ 186) 112
9003 22:59:39.474409 iDelay=195, Bit 5, Center 144 (95 ~ 194) 100
9004 22:59:39.478223 iDelay=195, Bit 6, Center 140 (87 ~ 194) 108
9005 22:59:39.481547 iDelay=195, Bit 7, Center 128 (75 ~ 182) 108
9006 22:59:39.487771 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
9007 22:59:39.490938 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
9008 22:59:39.494443 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
9009 22:59:39.497992 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
9010 22:59:39.504166 iDelay=195, Bit 12, Center 136 (83 ~ 190) 108
9011 22:59:39.507374 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
9012 22:59:39.510676 iDelay=195, Bit 14, Center 134 (83 ~ 186) 104
9013 22:59:39.514161 iDelay=195, Bit 15, Center 140 (91 ~ 190) 100
9014 22:59:39.514762 ==
9015 22:59:39.517543 Dram Type= 6, Freq= 0, CH_1, rank 1
9016 22:59:39.523987 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9017 22:59:39.524594 ==
9018 22:59:39.525025 DQS Delay:
9019 22:59:39.525441 DQS0 = 0, DQS1 = 0
9020 22:59:39.527345 DQM Delay:
9021 22:59:39.527968 DQM0 = 132, DQM1 = 128
9022 22:59:39.530790 DQ Delay:
9023 22:59:39.533972 DQ0 =136, DQ1 =130, DQ2 =120, DQ3 =130
9024 22:59:39.537599 DQ4 =130, DQ5 =144, DQ6 =140, DQ7 =128
9025 22:59:39.540741 DQ8 =116, DQ9 =118, DQ10 =128, DQ11 =120
9026 22:59:39.543785 DQ12 =136, DQ13 =136, DQ14 =134, DQ15 =140
9027 22:59:39.544255
9028 22:59:39.544599
9029 22:59:39.544919
9030 22:59:39.547041 [DramC_TX_OE_Calibration] TA2
9031 22:59:39.550290 Original DQ_B0 (3 6) =30, OEN = 27
9032 22:59:39.553891 Original DQ_B1 (3 6) =30, OEN = 27
9033 22:59:39.557361 24, 0x0, End_B0=24 End_B1=24
9034 22:59:39.557904 25, 0x0, End_B0=25 End_B1=25
9035 22:59:39.560236 26, 0x0, End_B0=26 End_B1=26
9036 22:59:39.564157 27, 0x0, End_B0=27 End_B1=27
9037 22:59:39.567296 28, 0x0, End_B0=28 End_B1=28
9038 22:59:39.570558 29, 0x0, End_B0=29 End_B1=29
9039 22:59:39.571102 30, 0x0, End_B0=30 End_B1=30
9040 22:59:39.573441 31, 0x4141, End_B0=30 End_B1=30
9041 22:59:39.576768 Byte0 end_step=30 best_step=27
9042 22:59:39.579916 Byte1 end_step=30 best_step=27
9043 22:59:39.583084 Byte0 TX OE(2T, 0.5T) = (3, 3)
9044 22:59:39.586607 Byte1 TX OE(2T, 0.5T) = (3, 3)
9045 22:59:39.587038
9046 22:59:39.587377
9047 22:59:39.593401 [DQSOSCAuto] RK1, (LSB)MR18= 0x111f, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 401 ps
9048 22:59:39.596647 CH1 RK1: MR19=303, MR18=111F
9049 22:59:39.603670 CH1_RK1: MR19=0x303, MR18=0x111F, DQSOSC=394, MR23=63, INC=23, DEC=15
9050 22:59:39.606242 [RxdqsGatingPostProcess] freq 1600
9051 22:59:39.613511 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9052 22:59:39.614046 best DQS0 dly(2T, 0.5T) = (1, 1)
9053 22:59:39.616552 best DQS1 dly(2T, 0.5T) = (1, 1)
9054 22:59:39.619778 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9055 22:59:39.623175 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9056 22:59:39.626447 best DQS0 dly(2T, 0.5T) = (1, 1)
9057 22:59:39.629818 best DQS1 dly(2T, 0.5T) = (1, 1)
9058 22:59:39.632985 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9059 22:59:39.636584 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9060 22:59:39.639701 Pre-setting of DQS Precalculation
9061 22:59:39.642891 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9062 22:59:39.652563 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9063 22:59:39.658892 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9064 22:59:39.659421
9065 22:59:39.659824
9066 22:59:39.662503 [Calibration Summary] 3200 Mbps
9067 22:59:39.663122 CH 0, Rank 0
9068 22:59:39.665276 SW Impedance : PASS
9069 22:59:39.665884 DUTY Scan : NO K
9070 22:59:39.669097 ZQ Calibration : PASS
9071 22:59:39.671756 Jitter Meter : NO K
9072 22:59:39.672350 CBT Training : PASS
9073 22:59:39.675397 Write leveling : PASS
9074 22:59:39.678628 RX DQS gating : PASS
9075 22:59:39.679099 RX DQ/DQS(RDDQC) : PASS
9076 22:59:39.681930 TX DQ/DQS : PASS
9077 22:59:39.685038 RX DATLAT : PASS
9078 22:59:39.685465 RX DQ/DQS(Engine): PASS
9079 22:59:39.688297 TX OE : PASS
9080 22:59:39.688722 All Pass.
9081 22:59:39.689056
9082 22:59:39.691692 CH 0, Rank 1
9083 22:59:39.692161 SW Impedance : PASS
9084 22:59:39.695005 DUTY Scan : NO K
9085 22:59:39.698310 ZQ Calibration : PASS
9086 22:59:39.698730 Jitter Meter : NO K
9087 22:59:39.701646 CBT Training : PASS
9088 22:59:39.705143 Write leveling : PASS
9089 22:59:39.705567 RX DQS gating : PASS
9090 22:59:39.707973 RX DQ/DQS(RDDQC) : PASS
9091 22:59:39.711941 TX DQ/DQS : PASS
9092 22:59:39.712409 RX DATLAT : PASS
9093 22:59:39.714686 RX DQ/DQS(Engine): PASS
9094 22:59:39.718105 TX OE : PASS
9095 22:59:39.718530 All Pass.
9096 22:59:39.718862
9097 22:59:39.719170 CH 1, Rank 0
9098 22:59:39.721512 SW Impedance : PASS
9099 22:59:39.724811 DUTY Scan : NO K
9100 22:59:39.725234 ZQ Calibration : PASS
9101 22:59:39.728386 Jitter Meter : NO K
9102 22:59:39.730995 CBT Training : PASS
9103 22:59:39.731417 Write leveling : PASS
9104 22:59:39.734474 RX DQS gating : PASS
9105 22:59:39.737860 RX DQ/DQS(RDDQC) : PASS
9106 22:59:39.738349 TX DQ/DQS : PASS
9107 22:59:39.741199 RX DATLAT : PASS
9108 22:59:39.741619 RX DQ/DQS(Engine): PASS
9109 22:59:39.744551 TX OE : PASS
9110 22:59:39.744992 All Pass.
9111 22:59:39.745336
9112 22:59:39.747738 CH 1, Rank 1
9113 22:59:39.750892 SW Impedance : PASS
9114 22:59:39.751314 DUTY Scan : NO K
9115 22:59:39.754293 ZQ Calibration : PASS
9116 22:59:39.754714 Jitter Meter : NO K
9117 22:59:39.757718 CBT Training : PASS
9118 22:59:39.761036 Write leveling : PASS
9119 22:59:39.761502 RX DQS gating : PASS
9120 22:59:39.763986 RX DQ/DQS(RDDQC) : PASS
9121 22:59:39.767143 TX DQ/DQS : PASS
9122 22:59:39.767226 RX DATLAT : PASS
9123 22:59:39.770410 RX DQ/DQS(Engine): PASS
9124 22:59:39.773810 TX OE : PASS
9125 22:59:39.773892 All Pass.
9126 22:59:39.773957
9127 22:59:39.776723 DramC Write-DBI on
9128 22:59:39.776806 PER_BANK_REFRESH: Hybrid Mode
9129 22:59:39.780464 TX_TRACKING: ON
9130 22:59:39.790162 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9131 22:59:39.796768 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9132 22:59:39.802980 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9133 22:59:39.806284 [FAST_K] Save calibration result to emmc
9134 22:59:39.809503 sync common calibartion params.
9135 22:59:39.812958 sync cbt_mode0:1, 1:1
9136 22:59:39.816643 dram_init: ddr_geometry: 2
9137 22:59:39.816725 dram_init: ddr_geometry: 2
9138 22:59:39.819683 dram_init: ddr_geometry: 2
9139 22:59:39.822580 0:dram_rank_size:100000000
9140 22:59:39.822664 1:dram_rank_size:100000000
9141 22:59:39.829684 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9142 22:59:39.832578 DFS_SHUFFLE_HW_MODE: ON
9143 22:59:39.835941 dramc_set_vcore_voltage set vcore to 725000
9144 22:59:39.839302 Read voltage for 1600, 0
9145 22:59:39.839384 Vio18 = 0
9146 22:59:39.839448 Vcore = 725000
9147 22:59:39.842748 Vdram = 0
9148 22:59:39.842830 Vddq = 0
9149 22:59:39.842894 Vmddr = 0
9150 22:59:39.846242 switch to 3200 Mbps bootup
9151 22:59:39.848841 [DramcRunTimeConfig]
9152 22:59:39.848922 PHYPLL
9153 22:59:39.848987 DPM_CONTROL_AFTERK: ON
9154 22:59:39.852393 PER_BANK_REFRESH: ON
9155 22:59:39.855989 REFRESH_OVERHEAD_REDUCTION: ON
9156 22:59:39.856123 CMD_PICG_NEW_MODE: OFF
9157 22:59:39.859197 XRTWTW_NEW_MODE: ON
9158 22:59:39.862346 XRTRTR_NEW_MODE: ON
9159 22:59:39.862428 TX_TRACKING: ON
9160 22:59:39.865409 RDSEL_TRACKING: OFF
9161 22:59:39.865494 DQS Precalculation for DVFS: ON
9162 22:59:39.868725 RX_TRACKING: OFF
9163 22:59:39.868807 HW_GATING DBG: ON
9164 22:59:39.872346 ZQCS_ENABLE_LP4: ON
9165 22:59:39.875502 RX_PICG_NEW_MODE: ON
9166 22:59:39.875584 TX_PICG_NEW_MODE: ON
9167 22:59:39.878571 ENABLE_RX_DCM_DPHY: ON
9168 22:59:39.882106 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9169 22:59:39.882188 DUMMY_READ_FOR_TRACKING: OFF
9170 22:59:39.885175 !!! SPM_CONTROL_AFTERK: OFF
9171 22:59:39.888809 !!! SPM could not control APHY
9172 22:59:39.891953 IMPEDANCE_TRACKING: ON
9173 22:59:39.892094 TEMP_SENSOR: ON
9174 22:59:39.895100 HW_SAVE_FOR_SR: OFF
9175 22:59:39.898588 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9176 22:59:39.901709 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9177 22:59:39.901791 Read ODT Tracking: ON
9178 22:59:39.905080 Refresh Rate DeBounce: ON
9179 22:59:39.908434 DFS_NO_QUEUE_FLUSH: ON
9180 22:59:39.911787 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9181 22:59:39.911892 ENABLE_DFS_RUNTIME_MRW: OFF
9182 22:59:39.915201 DDR_RESERVE_NEW_MODE: ON
9183 22:59:39.918049 MR_CBT_SWITCH_FREQ: ON
9184 22:59:39.918130 =========================
9185 22:59:39.938095 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9186 22:59:39.941499 dram_init: ddr_geometry: 2
9187 22:59:39.960008 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9188 22:59:39.962895 dram_init: dram init end (result: 0)
9189 22:59:39.969691 DRAM-K: Full calibration passed in 24432 msecs
9190 22:59:39.973088 MRC: failed to locate region type 0.
9191 22:59:39.973169 DRAM rank0 size:0x100000000,
9192 22:59:39.976235 DRAM rank1 size=0x100000000
9193 22:59:39.986711 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9194 22:59:39.992901 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9195 22:59:39.999445 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9196 22:59:40.009141 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9197 22:59:40.009222 DRAM rank0 size:0x100000000,
9198 22:59:40.012977 DRAM rank1 size=0x100000000
9199 22:59:40.013058 CBMEM:
9200 22:59:40.015743 IMD: root @ 0xfffff000 254 entries.
9201 22:59:40.019052 IMD: root @ 0xffffec00 62 entries.
9202 22:59:40.022524 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9203 22:59:40.029473 WARNING: RO_VPD is uninitialized or empty.
9204 22:59:40.032082 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9205 22:59:40.039938 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9206 22:59:40.052411 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9207 22:59:40.064093 BS: romstage times (exec / console): total (unknown) / 23962 ms
9208 22:59:40.064174
9209 22:59:40.064239
9210 22:59:40.073959 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9211 22:59:40.077091 ARM64: Exception handlers installed.
9212 22:59:40.080139 ARM64: Testing exception
9213 22:59:40.084002 ARM64: Done test exception
9214 22:59:40.084123 Enumerating buses...
9215 22:59:40.087151 Show all devs... Before device enumeration.
9216 22:59:40.090320 Root Device: enabled 1
9217 22:59:40.093369 CPU_CLUSTER: 0: enabled 1
9218 22:59:40.093479 CPU: 00: enabled 1
9219 22:59:40.097189 Compare with tree...
9220 22:59:40.097309 Root Device: enabled 1
9221 22:59:40.100183 CPU_CLUSTER: 0: enabled 1
9222 22:59:40.103808 CPU: 00: enabled 1
9223 22:59:40.103968 Root Device scanning...
9224 22:59:40.106883 scan_static_bus for Root Device
9225 22:59:40.110179 CPU_CLUSTER: 0 enabled
9226 22:59:40.113558 scan_static_bus for Root Device done
9227 22:59:40.117089 scan_bus: bus Root Device finished in 8 msecs
9228 22:59:40.117171 done
9229 22:59:40.123396 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9230 22:59:40.126855 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9231 22:59:40.133193 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9232 22:59:40.139544 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9233 22:59:40.139627 Allocating resources...
9234 22:59:40.142909 Reading resources...
9235 22:59:40.146300 Root Device read_resources bus 0 link: 0
9236 22:59:40.149629 DRAM rank0 size:0x100000000,
9237 22:59:40.149742 DRAM rank1 size=0x100000000
9238 22:59:40.156188 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9239 22:59:40.156271 CPU: 00 missing read_resources
9240 22:59:40.163056 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9241 22:59:40.165914 Root Device read_resources bus 0 link: 0 done
9242 22:59:40.169256 Done reading resources.
9243 22:59:40.172542 Show resources in subtree (Root Device)...After reading.
9244 22:59:40.175643 Root Device child on link 0 CPU_CLUSTER: 0
9245 22:59:40.178980 CPU_CLUSTER: 0 child on link 0 CPU: 00
9246 22:59:40.190001 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9247 22:59:40.190170 CPU: 00
9248 22:59:40.195758 Root Device assign_resources, bus 0 link: 0
9249 22:59:40.198861 CPU_CLUSTER: 0 missing set_resources
9250 22:59:40.201953 Root Device assign_resources, bus 0 link: 0 done
9251 22:59:40.205203 Done setting resources.
9252 22:59:40.208459 Show resources in subtree (Root Device)...After assigning values.
9253 22:59:40.215710 Root Device child on link 0 CPU_CLUSTER: 0
9254 22:59:40.218493 CPU_CLUSTER: 0 child on link 0 CPU: 00
9255 22:59:40.225214 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9256 22:59:40.228340 CPU: 00
9257 22:59:40.228464 Done allocating resources.
9258 22:59:40.235108 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9259 22:59:40.238051 Enabling resources...
9260 22:59:40.238133 done.
9261 22:59:40.241438 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9262 22:59:40.244725 Initializing devices...
9263 22:59:40.244807 Root Device init
9264 22:59:40.247976 init hardware done!
9265 22:59:40.251642 0x00000018: ctrlr->caps
9266 22:59:40.251756 52.000 MHz: ctrlr->f_max
9267 22:59:40.254995 0.400 MHz: ctrlr->f_min
9268 22:59:40.258106 0x40ff8080: ctrlr->voltages
9269 22:59:40.258189 sclk: 390625
9270 22:59:40.258254 Bus Width = 1
9271 22:59:40.261465 sclk: 390625
9272 22:59:40.261546 Bus Width = 1
9273 22:59:40.264336 Early init status = 3
9274 22:59:40.267648 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9275 22:59:40.272307 in-header: 03 fc 00 00 01 00 00 00
9276 22:59:40.274963 in-data: 00
9277 22:59:40.278246 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9278 22:59:40.283667 in-header: 03 fd 00 00 00 00 00 00
9279 22:59:40.287159 in-data:
9280 22:59:40.290431 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9281 22:59:40.294648 in-header: 03 fc 00 00 01 00 00 00
9282 22:59:40.297715 in-data: 00
9283 22:59:40.300931 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9284 22:59:40.306612 in-header: 03 fd 00 00 00 00 00 00
9285 22:59:40.310201 in-data:
9286 22:59:40.313638 [SSUSB] Setting up USB HOST controller...
9287 22:59:40.316883 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9288 22:59:40.319822 [SSUSB] phy power-on done.
9289 22:59:40.323114 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9290 22:59:40.329830 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9291 22:59:40.333185 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9292 22:59:40.339928 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9293 22:59:40.346440 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9294 22:59:40.352732 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9295 22:59:40.359545 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9296 22:59:40.366016 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9297 22:59:40.369338 SPM: binary array size = 0x9dc
9298 22:59:40.372862 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9299 22:59:40.379552 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9300 22:59:40.386126 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9301 22:59:40.392761 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9302 22:59:40.395888 configure_display: Starting display init
9303 22:59:40.429944 anx7625_power_on_init: Init interface.
9304 22:59:40.433446 anx7625_disable_pd_protocol: Disabled PD feature.
9305 22:59:40.436702 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9306 22:59:40.464266 anx7625_start_dp_work: Secure OCM version=00
9307 22:59:40.467628 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9308 22:59:40.482941 sp_tx_get_edid_block: EDID Block = 1
9309 22:59:40.586074 Extracted contents:
9310 22:59:40.588636 header: 00 ff ff ff ff ff ff 00
9311 22:59:40.592057 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9312 22:59:40.595693 version: 01 04
9313 22:59:40.598714 basic params: 95 1f 11 78 0a
9314 22:59:40.602288 chroma info: 76 90 94 55 54 90 27 21 50 54
9315 22:59:40.605684 established: 00 00 00
9316 22:59:40.611688 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9317 22:59:40.618236 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9318 22:59:40.621477 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9319 22:59:40.628185 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9320 22:59:40.634658 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9321 22:59:40.637601 extensions: 00
9322 22:59:40.637675 checksum: fb
9323 22:59:40.637749
9324 22:59:40.644119 Manufacturer: IVO Model 57d Serial Number 0
9325 22:59:40.644205 Made week 0 of 2020
9326 22:59:40.647844 EDID version: 1.4
9327 22:59:40.647922 Digital display
9328 22:59:40.650623 6 bits per primary color channel
9329 22:59:40.653934 DisplayPort interface
9330 22:59:40.654014 Maximum image size: 31 cm x 17 cm
9331 22:59:40.657206 Gamma: 220%
9332 22:59:40.657283 Check DPMS levels
9333 22:59:40.663887 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9334 22:59:40.667453 First detailed timing is preferred timing
9335 22:59:40.670660 Established timings supported:
9336 22:59:40.670736 Standard timings supported:
9337 22:59:40.674091 Detailed timings
9338 22:59:40.676889 Hex of detail: 383680a07038204018303c0035ae10000019
9339 22:59:40.683626 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9340 22:59:40.687090 0780 0798 07c8 0820 hborder 0
9341 22:59:40.690380 0438 043b 0447 0458 vborder 0
9342 22:59:40.693643 -hsync -vsync
9343 22:59:40.693730 Did detailed timing
9344 22:59:40.700224 Hex of detail: 000000000000000000000000000000000000
9345 22:59:40.703535 Manufacturer-specified data, tag 0
9346 22:59:40.706905 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9347 22:59:40.710241 ASCII string: InfoVision
9348 22:59:40.713355 Hex of detail: 000000fe00523134304e574635205248200a
9349 22:59:40.717001 ASCII string: R140NWF5 RH
9350 22:59:40.717077 Checksum
9351 22:59:40.720015 Checksum: 0xfb (valid)
9352 22:59:40.723126 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9353 22:59:40.726364 DSI data_rate: 832800000 bps
9354 22:59:40.733267 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9355 22:59:40.736217 anx7625_parse_edid: pixelclock(138800).
9356 22:59:40.739679 hactive(1920), hsync(48), hfp(24), hbp(88)
9357 22:59:40.742787 vactive(1080), vsync(12), vfp(3), vbp(17)
9358 22:59:40.746274 anx7625_dsi_config: config dsi.
9359 22:59:40.752855 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9360 22:59:40.766890 anx7625_dsi_config: success to config DSI
9361 22:59:40.770195 anx7625_dp_start: MIPI phy setup OK.
9362 22:59:40.773576 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9363 22:59:40.776956 mtk_ddp_mode_set invalid vrefresh 60
9364 22:59:40.780415 main_disp_path_setup
9365 22:59:40.780497 ovl_layer_smi_id_en
9366 22:59:40.783376 ovl_layer_smi_id_en
9367 22:59:40.783458 ccorr_config
9368 22:59:40.783521 aal_config
9369 22:59:40.786777 gamma_config
9370 22:59:40.786858 postmask_config
9371 22:59:40.790147 dither_config
9372 22:59:40.793554 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9373 22:59:40.800174 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9374 22:59:40.803413 Root Device init finished in 554 msecs
9375 22:59:40.806873 CPU_CLUSTER: 0 init
9376 22:59:40.813353 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9377 22:59:40.820002 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9378 22:59:40.820127 APU_MBOX 0x190000b0 = 0x10001
9379 22:59:40.823424 APU_MBOX 0x190001b0 = 0x10001
9380 22:59:40.826225 APU_MBOX 0x190005b0 = 0x10001
9381 22:59:40.829725 APU_MBOX 0x190006b0 = 0x10001
9382 22:59:40.836382 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9383 22:59:40.846319 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9384 22:59:40.858759 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9385 22:59:40.864893 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9386 22:59:40.876634 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9387 22:59:40.886219 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9388 22:59:40.889640 CPU_CLUSTER: 0 init finished in 81 msecs
9389 22:59:40.892369 Devices initialized
9390 22:59:40.895578 Show all devs... After init.
9391 22:59:40.895659 Root Device: enabled 1
9392 22:59:40.898967 CPU_CLUSTER: 0: enabled 1
9393 22:59:40.902325 CPU: 00: enabled 1
9394 22:59:40.905670 BS: BS_DEV_INIT run times (exec / console): 212 / 447 ms
9395 22:59:40.909161 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9396 22:59:40.912741 ELOG: NV offset 0x57f000 size 0x1000
9397 22:59:40.919230 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9398 22:59:40.926066 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9399 22:59:40.929176 ELOG: Event(17) added with size 13 at 2023-06-05 22:59:40 UTC
9400 22:59:40.935605 out: cmd=0x121: 03 db 21 01 00 00 00 00
9401 22:59:40.939015 in-header: 03 23 00 00 2c 00 00 00
9402 22:59:40.948848 in-data: 3c 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9403 22:59:40.955004 ELOG: Event(A1) added with size 10 at 2023-06-05 22:59:40 UTC
9404 22:59:40.961608 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9405 22:59:40.968311 ELOG: Event(A0) added with size 9 at 2023-06-05 22:59:40 UTC
9406 22:59:40.971842 elog_add_boot_reason: Logged dev mode boot
9407 22:59:40.978290 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9408 22:59:40.978377 Finalize devices...
9409 22:59:40.981780 Devices finalized
9410 22:59:40.985264 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9411 22:59:40.987982 Writing coreboot table at 0xffe64000
9412 22:59:40.991576 0. 000000000010a000-0000000000113fff: RAMSTAGE
9413 22:59:40.998173 1. 0000000040000000-00000000400fffff: RAM
9414 22:59:41.001589 2. 0000000040100000-000000004032afff: RAMSTAGE
9415 22:59:41.005031 3. 000000004032b000-00000000545fffff: RAM
9416 22:59:41.007855 4. 0000000054600000-000000005465ffff: BL31
9417 22:59:41.011180 5. 0000000054660000-00000000ffe63fff: RAM
9418 22:59:41.017743 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9419 22:59:41.021268 7. 0000000100000000-000000023fffffff: RAM
9420 22:59:41.024547 Passing 5 GPIOs to payload:
9421 22:59:41.027904 NAME | PORT | POLARITY | VALUE
9422 22:59:41.034529 EC in RW | 0x000000aa | low | undefined
9423 22:59:41.037832 EC interrupt | 0x00000005 | low | undefined
9424 22:59:41.041087 TPM interrupt | 0x000000ab | high | undefined
9425 22:59:41.047486 SD card detect | 0x00000011 | high | undefined
9426 22:59:41.051011 speaker enable | 0x00000093 | high | undefined
9427 22:59:41.054092 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9428 22:59:41.058335 in-header: 03 f9 00 00 02 00 00 00
9429 22:59:41.061290 in-data: 02 00
9430 22:59:41.064779 ADC[4]: Raw value=903325 ID=7
9431 22:59:41.068321 ADC[3]: Raw value=213546 ID=1
9432 22:59:41.068405 RAM Code: 0x71
9433 22:59:41.071590 ADC[6]: Raw value=75000 ID=0
9434 22:59:41.074804 ADC[5]: Raw value=213916 ID=1
9435 22:59:41.074887 SKU Code: 0x1
9436 22:59:41.081308 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum a53a
9437 22:59:41.081396 coreboot table: 964 bytes.
9438 22:59:41.084772 IMD ROOT 0. 0xfffff000 0x00001000
9439 22:59:41.087867 IMD SMALL 1. 0xffffe000 0x00001000
9440 22:59:41.091402 RO MCACHE 2. 0xffffc000 0x00001104
9441 22:59:41.094267 CONSOLE 3. 0xfff7c000 0x00080000
9442 22:59:41.098157 FMAP 4. 0xfff7b000 0x00000452
9443 22:59:41.101480 TIME STAMP 5. 0xfff7a000 0x00000910
9444 22:59:41.104315 VBOOT WORK 6. 0xfff66000 0x00014000
9445 22:59:41.107710 RAMOOPS 7. 0xffe66000 0x00100000
9446 22:59:41.111003 COREBOOT 8. 0xffe64000 0x00002000
9447 22:59:41.114152 IMD small region:
9448 22:59:41.117227 IMD ROOT 0. 0xffffec00 0x00000400
9449 22:59:41.120583 VPD 1. 0xffffeba0 0x0000004c
9450 22:59:41.123973 MMC STATUS 2. 0xffffeb80 0x00000004
9451 22:59:41.130584 BS: BS_WRITE_TABLES run times (exec / console): 2 / 137 ms
9452 22:59:41.130667 Probing TPM: done!
9453 22:59:41.137419 Connected to device vid:did:rid of 1ae0:0028:00
9454 22:59:41.143863 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
9455 22:59:41.147290 Initialized TPM device CR50 revision 0
9456 22:59:41.151054 Checking cr50 for pending updates
9457 22:59:41.156332 Reading cr50 TPM mode
9458 22:59:41.165557 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9459 22:59:41.172177 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9460 22:59:41.211947 read SPI 0x3990ec 0x4f1b0: 34847 us, 9298 KB/s, 74.384 Mbps
9461 22:59:41.215384 Checking segment from ROM address 0x40100000
9462 22:59:41.218808 Checking segment from ROM address 0x4010001c
9463 22:59:41.225453 Loading segment from ROM address 0x40100000
9464 22:59:41.225550 code (compression=0)
9465 22:59:41.234896 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9466 22:59:41.242059 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9467 22:59:41.242139 it's not compressed!
9468 22:59:41.248534 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9469 22:59:41.251934 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9470 22:59:41.272346 Loading segment from ROM address 0x4010001c
9471 22:59:41.272426 Entry Point 0x80000000
9472 22:59:41.275331 Loaded segments
9473 22:59:41.279053 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9474 22:59:41.285716 Jumping to boot code at 0x80000000(0xffe64000)
9475 22:59:41.292316 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9476 22:59:41.298951 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9477 22:59:41.306891 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9478 22:59:41.310185 Checking segment from ROM address 0x40100000
9479 22:59:41.313110 Checking segment from ROM address 0x4010001c
9480 22:59:41.319863 Loading segment from ROM address 0x40100000
9481 22:59:41.319975 code (compression=1)
9482 22:59:41.326619 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9483 22:59:41.336316 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9484 22:59:41.336401 using LZMA
9485 22:59:41.345420 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9486 22:59:41.351919 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9487 22:59:41.355229 Loading segment from ROM address 0x4010001c
9488 22:59:41.355312 Entry Point 0x54601000
9489 22:59:41.358807 Loaded segments
9490 22:59:41.361523 NOTICE: MT8192 bl31_setup
9491 22:59:41.368773 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9492 22:59:41.371988 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9493 22:59:41.375486 WARNING: region 0:
9494 22:59:41.378957 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9495 22:59:41.379037 WARNING: region 1:
9496 22:59:41.385256 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9497 22:59:41.388899 WARNING: region 2:
9498 22:59:41.392130 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9499 22:59:41.395229 WARNING: region 3:
9500 22:59:41.398536 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9501 22:59:41.401782 WARNING: region 4:
9502 22:59:41.409043 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9503 22:59:41.409127 WARNING: region 5:
9504 22:59:41.411652 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9505 22:59:41.414945 WARNING: region 6:
9506 22:59:41.418224 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9507 22:59:41.421634 WARNING: region 7:
9508 22:59:41.425037 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9509 22:59:41.431737 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9510 22:59:41.435186 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9511 22:59:41.438377 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9512 22:59:41.445049 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9513 22:59:41.448370 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9514 22:59:41.455054 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9515 22:59:41.458302 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9516 22:59:41.461793 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9517 22:59:41.468149 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9518 22:59:41.471795 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9519 22:59:41.475076 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9520 22:59:41.481871 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9521 22:59:41.485044 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9522 22:59:41.491660 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9523 22:59:41.494896 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9524 22:59:41.497889 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9525 22:59:41.504795 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9526 22:59:41.507794 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9527 22:59:41.511416 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9528 22:59:41.518381 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9529 22:59:41.521463 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9530 22:59:41.527832 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9531 22:59:41.531802 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9532 22:59:41.534509 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9533 22:59:41.541214 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9534 22:59:41.544642 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9535 22:59:41.550859 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9536 22:59:41.554624 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9537 22:59:41.557596 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9538 22:59:41.564206 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9539 22:59:41.567430 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9540 22:59:41.573994 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9541 22:59:41.577258 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9542 22:59:41.580629 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9543 22:59:41.583933 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9544 22:59:41.590621 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9545 22:59:41.593799 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9546 22:59:41.596980 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9547 22:59:41.600791 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9548 22:59:41.607429 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9549 22:59:41.610579 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9550 22:59:41.613695 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9551 22:59:41.617138 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9552 22:59:41.623808 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9553 22:59:41.627036 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9554 22:59:41.630347 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9555 22:59:41.637473 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9556 22:59:41.640567 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9557 22:59:41.643463 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9558 22:59:41.650202 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9559 22:59:41.653565 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9560 22:59:41.660142 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9561 22:59:41.663391 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9562 22:59:41.666879 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9563 22:59:41.673563 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9564 22:59:41.677216 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9565 22:59:41.683840 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9566 22:59:41.686788 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9567 22:59:41.693743 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9568 22:59:41.696710 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9569 22:59:41.699927 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9570 22:59:41.706910 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9571 22:59:41.709917 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9572 22:59:41.716780 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9573 22:59:41.719910 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9574 22:59:41.726805 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9575 22:59:41.730003 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9576 22:59:41.736778 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9577 22:59:41.739563 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9578 22:59:41.743410 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9579 22:59:41.749578 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9580 22:59:41.753371 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9581 22:59:41.759536 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9582 22:59:41.763304 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9583 22:59:41.769669 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9584 22:59:41.772958 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9585 22:59:41.776332 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9586 22:59:41.783074 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9587 22:59:41.786660 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9588 22:59:41.792563 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9589 22:59:41.796587 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9590 22:59:41.802593 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9591 22:59:41.805868 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9592 22:59:41.812667 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9593 22:59:41.816219 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9594 22:59:41.819278 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9595 22:59:41.826252 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9596 22:59:41.829422 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9597 22:59:41.836162 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9598 22:59:41.838964 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9599 22:59:41.845709 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9600 22:59:41.849046 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9601 22:59:41.855742 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9602 22:59:41.858966 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9603 22:59:41.862293 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9604 22:59:41.869166 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9605 22:59:41.872322 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9606 22:59:41.875767 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9607 22:59:41.882423 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9608 22:59:41.886026 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9609 22:59:41.889223 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9610 22:59:41.895871 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9611 22:59:41.898832 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9612 22:59:41.902448 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9613 22:59:41.909040 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9614 22:59:41.912206 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9615 22:59:41.919059 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9616 22:59:41.922424 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9617 22:59:41.925771 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9618 22:59:41.931895 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9619 22:59:41.935700 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9620 22:59:41.942263 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9621 22:59:41.945772 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9622 22:59:41.948410 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9623 22:59:41.955119 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9624 22:59:41.958757 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9625 22:59:41.962166 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9626 22:59:41.968769 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9627 22:59:41.972115 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9628 22:59:41.975289 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9629 22:59:41.978789 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9630 22:59:41.985549 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9631 22:59:41.988779 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9632 22:59:41.992203 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9633 22:59:41.998449 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9634 22:59:42.001761 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9635 22:59:42.008203 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9636 22:59:42.011774 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9637 22:59:42.014917 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9638 22:59:42.021962 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9639 22:59:42.025093 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9640 22:59:42.028280 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9641 22:59:42.035078 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9642 22:59:42.038385 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9643 22:59:42.044745 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9644 22:59:42.048212 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9645 22:59:42.051566 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9646 22:59:42.058251 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9647 22:59:42.061830 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9648 22:59:42.068256 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9649 22:59:42.071604 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9650 22:59:42.074902 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9651 22:59:42.081508 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9652 22:59:42.084857 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9653 22:59:42.091232 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9654 22:59:42.094381 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9655 22:59:42.097736 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9656 22:59:42.104321 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9657 22:59:42.107752 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9658 22:59:42.114206 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9659 22:59:42.117970 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9660 22:59:42.121213 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9661 22:59:42.127793 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9662 22:59:42.130821 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9663 22:59:42.137527 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9664 22:59:42.141176 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9665 22:59:42.144123 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9666 22:59:42.150842 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9667 22:59:42.154176 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9668 22:59:42.157359 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9669 22:59:42.164224 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9670 22:59:42.167140 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9671 22:59:42.173704 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9672 22:59:42.176973 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9673 22:59:42.184292 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9674 22:59:42.187230 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9675 22:59:42.190713 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9676 22:59:42.196989 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9677 22:59:42.200410 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9678 22:59:42.207166 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9679 22:59:42.209992 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9680 22:59:42.213180 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9681 22:59:42.219832 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9682 22:59:42.223081 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9683 22:59:42.229683 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9684 22:59:42.233058 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9685 22:59:42.236621 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9686 22:59:42.243370 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9687 22:59:42.246369 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9688 22:59:42.249732 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9689 22:59:42.256172 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9690 22:59:42.259943 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9691 22:59:42.266360 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9692 22:59:42.269707 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9693 22:59:42.276403 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9694 22:59:42.279659 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9695 22:59:42.282953 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9696 22:59:42.289445 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9697 22:59:42.292878 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9698 22:59:42.299511 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9699 22:59:42.302809 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9700 22:59:42.306290 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9701 22:59:42.312428 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9702 22:59:42.315688 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9703 22:59:42.322238 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9704 22:59:42.325973 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9705 22:59:42.332021 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9706 22:59:42.335416 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9707 22:59:42.338951 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9708 22:59:42.345463 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9709 22:59:42.348854 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9710 22:59:42.355145 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9711 22:59:42.358834 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9712 22:59:42.365239 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9713 22:59:42.368336 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9714 22:59:42.371705 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9715 22:59:42.378368 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9716 22:59:42.381749 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9717 22:59:42.388414 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9718 22:59:42.391690 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9719 22:59:42.398528 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9720 22:59:42.401718 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9721 22:59:42.405266 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9722 22:59:42.411374 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9723 22:59:42.414703 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9724 22:59:42.421238 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9725 22:59:42.424609 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9726 22:59:42.431151 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9727 22:59:42.434433 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9728 22:59:42.437979 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9729 22:59:42.444459 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9730 22:59:42.447598 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9731 22:59:42.454041 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9732 22:59:42.457874 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9733 22:59:42.464019 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9734 22:59:42.468192 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9735 22:59:42.471172 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9736 22:59:42.477691 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9737 22:59:42.480892 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9738 22:59:42.484656 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9739 22:59:42.491151 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9740 22:59:42.493907 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9741 22:59:42.497472 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9742 22:59:42.501043 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9743 22:59:42.507215 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9744 22:59:42.510668 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9745 22:59:42.517613 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9746 22:59:42.520733 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9747 22:59:42.523530 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9748 22:59:42.530316 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9749 22:59:42.533478 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9750 22:59:42.536990 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9751 22:59:42.543609 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9752 22:59:42.546962 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9753 22:59:42.549889 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9754 22:59:42.556301 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9755 22:59:42.559817 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9756 22:59:42.565984 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9757 22:59:42.569578 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9758 22:59:42.572851 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9759 22:59:42.579933 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9760 22:59:42.582524 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9761 22:59:42.589152 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9762 22:59:42.592546 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9763 22:59:42.595797 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9764 22:59:42.602532 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9765 22:59:42.605756 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9766 22:59:42.612244 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9767 22:59:42.615663 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9768 22:59:42.619385 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9769 22:59:42.625361 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9770 22:59:42.628824 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9771 22:59:42.631961 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9772 22:59:42.638251 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9773 22:59:42.642250 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9774 22:59:42.644812 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9775 22:59:42.651519 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9776 22:59:42.654753 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9777 22:59:42.661766 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9778 22:59:42.664676 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9779 22:59:42.668052 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9780 22:59:42.671277 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9781 22:59:42.674988 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9782 22:59:42.681262 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9783 22:59:42.685190 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9784 22:59:42.687665 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9785 22:59:42.691489 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9786 22:59:42.697512 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9787 22:59:42.700991 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9788 22:59:42.704304 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9789 22:59:42.710870 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9790 22:59:42.714166 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9791 22:59:42.717608 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9792 22:59:42.724239 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9793 22:59:42.727185 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9794 22:59:42.734122 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9795 22:59:42.737030 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9796 22:59:42.743657 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9797 22:59:42.747355 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9798 22:59:42.750165 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9799 22:59:42.757239 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9800 22:59:42.760264 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9801 22:59:42.767028 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9802 22:59:42.770040 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9803 22:59:42.773728 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9804 22:59:42.779901 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9805 22:59:42.783753 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9806 22:59:42.790033 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9807 22:59:42.793176 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9808 22:59:42.799569 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9809 22:59:42.802897 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9810 22:59:42.806285 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9811 22:59:42.813020 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9812 22:59:42.816159 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9813 22:59:42.822833 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9814 22:59:42.826393 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9815 22:59:42.829649 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9816 22:59:42.836311 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9817 22:59:42.839205 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9818 22:59:42.845766 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9819 22:59:42.849099 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9820 22:59:42.855636 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9821 22:59:42.859279 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9822 22:59:42.862237 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9823 22:59:42.869279 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9824 22:59:42.872428 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9825 22:59:42.878780 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9826 22:59:42.881901 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9827 22:59:42.889086 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9828 22:59:42.892143 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9829 22:59:42.895434 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9830 22:59:42.901989 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9831 22:59:42.905037 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9832 22:59:42.911765 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9833 22:59:42.914908 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9834 22:59:42.918263 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9835 22:59:42.924935 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9836 22:59:42.928468 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9837 22:59:42.935105 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9838 22:59:42.938683 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9839 22:59:42.941315 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9840 22:59:42.947985 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9841 22:59:42.951227 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9842 22:59:42.957773 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9843 22:59:42.960787 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9844 22:59:42.967836 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9845 22:59:42.970693 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9846 22:59:42.974400 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9847 22:59:42.980868 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9848 22:59:42.984412 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9849 22:59:42.990807 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9850 22:59:42.994031 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9851 22:59:43.000842 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9852 22:59:43.003950 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9853 22:59:43.007105 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9854 22:59:43.013597 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9855 22:59:43.017319 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9856 22:59:43.023610 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9857 22:59:43.026843 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9858 22:59:43.030352 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9859 22:59:43.037102 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9860 22:59:43.040400 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9861 22:59:43.047135 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9862 22:59:43.049850 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9863 22:59:43.056451 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9864 22:59:43.060234 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9865 22:59:43.063150 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9866 22:59:43.069802 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9867 22:59:43.073320 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9868 22:59:43.079832 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9869 22:59:43.083237 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9870 22:59:43.089838 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9871 22:59:43.093063 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9872 22:59:43.099688 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9873 22:59:43.102732 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9874 22:59:43.106351 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9875 22:59:43.113275 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9876 22:59:43.116442 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9877 22:59:43.122510 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9878 22:59:43.125880 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9879 22:59:43.132812 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9880 22:59:43.135545 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9881 22:59:43.142551 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9882 22:59:43.145444 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9883 22:59:43.152197 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9884 22:59:43.155652 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9885 22:59:43.158996 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9886 22:59:43.165539 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9887 22:59:43.168860 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9888 22:59:43.175598 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9889 22:59:43.179033 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9890 22:59:43.185511 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9891 22:59:43.188639 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9892 22:59:43.195150 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9893 22:59:43.198780 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9894 22:59:43.201973 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9895 22:59:43.208313 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9896 22:59:43.211505 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9897 22:59:43.217932 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9898 22:59:43.221281 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9899 22:59:43.228259 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9900 22:59:43.231450 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9901 22:59:43.237809 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9902 22:59:43.241191 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9903 22:59:43.244502 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9904 22:59:43.250859 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9905 22:59:43.254281 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9906 22:59:43.261357 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9907 22:59:43.263932 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9908 22:59:43.270929 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9909 22:59:43.273821 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9910 22:59:43.277406 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9911 22:59:43.283947 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9912 22:59:43.287530 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9913 22:59:43.293526 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9914 22:59:43.296836 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9915 22:59:43.303641 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9916 22:59:43.307046 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9917 22:59:43.313730 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9918 22:59:43.316766 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9919 22:59:43.323539 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9920 22:59:43.326529 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9921 22:59:43.333485 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9922 22:59:43.336810 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9923 22:59:43.343601 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9924 22:59:43.346547 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9925 22:59:43.353132 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9926 22:59:43.356591 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9927 22:59:43.363236 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9928 22:59:43.366646 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9929 22:59:43.373259 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9930 22:59:43.376557 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9931 22:59:43.382916 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9932 22:59:43.386124 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9933 22:59:43.393106 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9934 22:59:43.395913 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9935 22:59:43.402651 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9936 22:59:43.405893 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9937 22:59:43.412459 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9938 22:59:43.416062 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9939 22:59:43.422894 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9940 22:59:43.425778 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9941 22:59:43.432252 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9942 22:59:43.435866 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9943 22:59:43.439157 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9944 22:59:43.442735 INFO: [APUAPC] vio 0
9945 22:59:43.449480 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9946 22:59:43.452407 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9947 22:59:43.455774 INFO: [APUAPC] D0_APC_0: 0x400510
9948 22:59:43.459210 INFO: [APUAPC] D0_APC_1: 0x0
9949 22:59:43.462434 INFO: [APUAPC] D0_APC_2: 0x1540
9950 22:59:43.465956 INFO: [APUAPC] D0_APC_3: 0x0
9951 22:59:43.468704 INFO: [APUAPC] D1_APC_0: 0xffffffff
9952 22:59:43.472130 INFO: [APUAPC] D1_APC_1: 0xffffffff
9953 22:59:43.475955 INFO: [APUAPC] D1_APC_2: 0x3fffff
9954 22:59:43.479434 INFO: [APUAPC] D1_APC_3: 0x0
9955 22:59:43.481951 INFO: [APUAPC] D2_APC_0: 0xffffffff
9956 22:59:43.485591 INFO: [APUAPC] D2_APC_1: 0xffffffff
9957 22:59:43.488721 INFO: [APUAPC] D2_APC_2: 0x3fffff
9958 22:59:43.492133 INFO: [APUAPC] D2_APC_3: 0x0
9959 22:59:43.495221 INFO: [APUAPC] D3_APC_0: 0xffffffff
9960 22:59:43.498644 INFO: [APUAPC] D3_APC_1: 0xffffffff
9961 22:59:43.502032 INFO: [APUAPC] D3_APC_2: 0x3fffff
9962 22:59:43.505307 INFO: [APUAPC] D3_APC_3: 0x0
9963 22:59:43.508748 INFO: [APUAPC] D4_APC_0: 0xffffffff
9964 22:59:43.512124 INFO: [APUAPC] D4_APC_1: 0xffffffff
9965 22:59:43.515429 INFO: [APUAPC] D4_APC_2: 0x3fffff
9966 22:59:43.515853 INFO: [APUAPC] D4_APC_3: 0x0
9967 22:59:43.518737 INFO: [APUAPC] D5_APC_0: 0xffffffff
9968 22:59:43.522225 INFO: [APUAPC] D5_APC_1: 0xffffffff
9969 22:59:43.525308 INFO: [APUAPC] D5_APC_2: 0x3fffff
9970 22:59:43.528414 INFO: [APUAPC] D5_APC_3: 0x0
9971 22:59:43.531477 INFO: [APUAPC] D6_APC_0: 0xffffffff
9972 22:59:43.535038 INFO: [APUAPC] D6_APC_1: 0xffffffff
9973 22:59:43.538127 INFO: [APUAPC] D6_APC_2: 0x3fffff
9974 22:59:43.541689 INFO: [APUAPC] D6_APC_3: 0x0
9975 22:59:43.544910 INFO: [APUAPC] D7_APC_0: 0xffffffff
9976 22:59:43.548143 INFO: [APUAPC] D7_APC_1: 0xffffffff
9977 22:59:43.551602 INFO: [APUAPC] D7_APC_2: 0x3fffff
9978 22:59:43.554832 INFO: [APUAPC] D7_APC_3: 0x0
9979 22:59:43.558299 INFO: [APUAPC] D8_APC_0: 0xffffffff
9980 22:59:43.561477 INFO: [APUAPC] D8_APC_1: 0xffffffff
9981 22:59:43.564608 INFO: [APUAPC] D8_APC_2: 0x3fffff
9982 22:59:43.568248 INFO: [APUAPC] D8_APC_3: 0x0
9983 22:59:43.571007 INFO: [APUAPC] D9_APC_0: 0xffffffff
9984 22:59:43.574426 INFO: [APUAPC] D9_APC_1: 0xffffffff
9985 22:59:43.577654 INFO: [APUAPC] D9_APC_2: 0x3fffff
9986 22:59:43.581039 INFO: [APUAPC] D9_APC_3: 0x0
9987 22:59:43.584380 INFO: [APUAPC] D10_APC_0: 0xffffffff
9988 22:59:43.587726 INFO: [APUAPC] D10_APC_1: 0xffffffff
9989 22:59:43.590462 INFO: [APUAPC] D10_APC_2: 0x3fffff
9990 22:59:43.593809 INFO: [APUAPC] D10_APC_3: 0x0
9991 22:59:43.597111 INFO: [APUAPC] D11_APC_0: 0xffffffff
9992 22:59:43.600363 INFO: [APUAPC] D11_APC_1: 0xffffffff
9993 22:59:43.603862 INFO: [APUAPC] D11_APC_2: 0x3fffff
9994 22:59:43.607193 INFO: [APUAPC] D11_APC_3: 0x0
9995 22:59:43.610579 INFO: [APUAPC] D12_APC_0: 0xffffffff
9996 22:59:43.613742 INFO: [APUAPC] D12_APC_1: 0xffffffff
9997 22:59:43.617436 INFO: [APUAPC] D12_APC_2: 0x3fffff
9998 22:59:43.620749 INFO: [APUAPC] D12_APC_3: 0x0
9999 22:59:43.623529 INFO: [APUAPC] D13_APC_0: 0xffffffff
10000 22:59:43.630571 INFO: [APUAPC] D13_APC_1: 0xffffffff
10001 22:59:43.633381 INFO: [APUAPC] D13_APC_2: 0x3fffff
10002 22:59:43.633462 INFO: [APUAPC] D13_APC_3: 0x0
10003 22:59:43.640097 INFO: [APUAPC] D14_APC_0: 0xffffffff
10004 22:59:43.643349 INFO: [APUAPC] D14_APC_1: 0xffffffff
10005 22:59:43.646612 INFO: [APUAPC] D14_APC_2: 0x3fffff
10006 22:59:43.649690 INFO: [APUAPC] D14_APC_3: 0x0
10007 22:59:43.653325 INFO: [APUAPC] D15_APC_0: 0xffffffff
10008 22:59:43.656374 INFO: [APUAPC] D15_APC_1: 0xffffffff
10009 22:59:43.659739 INFO: [APUAPC] D15_APC_2: 0x3fffff
10010 22:59:43.662726 INFO: [APUAPC] D15_APC_3: 0x0
10011 22:59:43.662808 INFO: [APUAPC] APC_CON: 0x4
10012 22:59:43.666544 INFO: [NOCDAPC] D0_APC_0: 0x0
10013 22:59:43.669856 INFO: [NOCDAPC] D0_APC_1: 0x0
10014 22:59:43.672703 INFO: [NOCDAPC] D1_APC_0: 0x0
10015 22:59:43.676204 INFO: [NOCDAPC] D1_APC_1: 0xfff
10016 22:59:43.679438 INFO: [NOCDAPC] D2_APC_0: 0x0
10017 22:59:43.682900 INFO: [NOCDAPC] D2_APC_1: 0xfff
10018 22:59:43.686100 INFO: [NOCDAPC] D3_APC_0: 0x0
10019 22:59:43.689368 INFO: [NOCDAPC] D3_APC_1: 0xfff
10020 22:59:43.692751 INFO: [NOCDAPC] D4_APC_0: 0x0
10021 22:59:43.695766 INFO: [NOCDAPC] D4_APC_1: 0xfff
10022 22:59:43.695874 INFO: [NOCDAPC] D5_APC_0: 0x0
10023 22:59:43.699104 INFO: [NOCDAPC] D5_APC_1: 0xfff
10024 22:59:43.702596 INFO: [NOCDAPC] D6_APC_0: 0x0
10025 22:59:43.705943 INFO: [NOCDAPC] D6_APC_1: 0xfff
10026 22:59:43.709266 INFO: [NOCDAPC] D7_APC_0: 0x0
10027 22:59:43.712754 INFO: [NOCDAPC] D7_APC_1: 0xfff
10028 22:59:43.715892 INFO: [NOCDAPC] D8_APC_0: 0x0
10029 22:59:43.719395 INFO: [NOCDAPC] D8_APC_1: 0xfff
10030 22:59:43.722540 INFO: [NOCDAPC] D9_APC_0: 0x0
10031 22:59:43.725426 INFO: [NOCDAPC] D9_APC_1: 0xfff
10032 22:59:43.728659 INFO: [NOCDAPC] D10_APC_0: 0x0
10033 22:59:43.732277 INFO: [NOCDAPC] D10_APC_1: 0xfff
10034 22:59:43.732358 INFO: [NOCDAPC] D11_APC_0: 0x0
10035 22:59:43.735807 INFO: [NOCDAPC] D11_APC_1: 0xfff
10036 22:59:43.738527 INFO: [NOCDAPC] D12_APC_0: 0x0
10037 22:59:43.742145 INFO: [NOCDAPC] D12_APC_1: 0xfff
10038 22:59:43.745228 INFO: [NOCDAPC] D13_APC_0: 0x0
10039 22:59:43.748365 INFO: [NOCDAPC] D13_APC_1: 0xfff
10040 22:59:43.751932 INFO: [NOCDAPC] D14_APC_0: 0x0
10041 22:59:43.755126 INFO: [NOCDAPC] D14_APC_1: 0xfff
10042 22:59:43.758531 INFO: [NOCDAPC] D15_APC_0: 0x0
10043 22:59:43.761418 INFO: [NOCDAPC] D15_APC_1: 0xfff
10044 22:59:43.765158 INFO: [NOCDAPC] APC_CON: 0x4
10045 22:59:43.767982 INFO: [APUAPC] set_apusys_apc done
10046 22:59:43.771352 INFO: [DEVAPC] devapc_init done
10047 22:59:43.775231 INFO: GICv3 without legacy support detected.
10048 22:59:43.778003 INFO: ARM GICv3 driver initialized in EL3
10049 22:59:43.781356 INFO: Maximum SPI INTID supported: 639
10050 22:59:43.788001 INFO: BL31: Initializing runtime services
10051 22:59:43.791230 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10052 22:59:43.794712 INFO: SPM: enable CPC mode
10053 22:59:43.801014 INFO: mcdi ready for mcusys-off-idle and system suspend
10054 22:59:43.804225 INFO: BL31: Preparing for EL3 exit to normal world
10055 22:59:43.807649 INFO: Entry point address = 0x80000000
10056 22:59:43.810979 INFO: SPSR = 0x8
10057 22:59:43.816576
10058 22:59:43.816656
10059 22:59:43.816719
10060 22:59:43.819903 Starting depthcharge on Spherion...
10061 22:59:43.819984
10062 22:59:43.820073 Wipe memory regions:
10063 22:59:43.820148
10064 22:59:43.820750 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10065 22:59:43.820847 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10066 22:59:43.820929 Setting prompt string to ['asurada:']
10067 22:59:43.821010 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10068 22:59:43.823448 [0x00000040000000, 0x00000054600000)
10069 22:59:43.945323
10070 22:59:43.945437 [0x00000054660000, 0x00000080000000)
10071 22:59:44.205842
10072 22:59:44.206003 [0x000000821a7280, 0x000000ffe64000)
10073 22:59:44.950591
10074 22:59:44.950749 [0x00000100000000, 0x00000240000000)
10075 22:59:46.839183
10076 22:59:46.842431 Initializing XHCI USB controller at 0x11200000.
10077 22:59:47.881410
10078 22:59:47.884710 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10079 22:59:47.884839
10080 22:59:47.884943
10081 22:59:47.885046
10082 22:59:47.885384 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10084 22:59:47.985795 asurada: tftpboot 192.168.201.1 10597701/tftp-deploy-gimehd2h/kernel/image.itb 10597701/tftp-deploy-gimehd2h/kernel/cmdline
10085 22:59:47.986000 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10086 22:59:47.986113 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10087 22:59:47.990473 tftpboot 192.168.201.1 10597701/tftp-deploy-gimehd2h/kernel/image.itp-deploy-gimehd2h/kernel/cmdline
10088 22:59:47.990589
10089 22:59:47.990682 Waiting for link
10090 22:59:48.150683
10091 22:59:48.150831 R8152: Initializing
10092 22:59:48.150903
10093 22:59:48.153914 Version 6 (ocp_data = 5c30)
10094 22:59:48.153983
10095 22:59:48.157162 R8152: Done initializing
10096 22:59:48.157230
10097 22:59:48.157294 Adding net device
10098 22:59:50.138350
10099 22:59:50.138539 done.
10100 22:59:50.138654
10101 22:59:50.138750 MAC: 00:24:32:30:7c:7b
10102 22:59:50.138843
10103 22:59:50.141428 Sending DHCP discover... done.
10104 22:59:50.141533
10105 22:59:50.145061 Waiting for reply... done.
10106 22:59:50.145180
10107 22:59:50.148150 Sending DHCP request... done.
10108 22:59:50.148257
10109 22:59:50.148352 Waiting for reply... done.
10110 22:59:50.148459
10111 22:59:50.151762 My ip is 192.168.201.14
10112 22:59:50.151866
10113 22:59:50.154807 The DHCP server ip is 192.168.201.1
10114 22:59:50.154911
10115 22:59:50.158296 TFTP server IP predefined by user: 192.168.201.1
10116 22:59:50.158396
10117 22:59:50.164646 Bootfile predefined by user: 10597701/tftp-deploy-gimehd2h/kernel/image.itb
10118 22:59:50.164757
10119 22:59:50.168127 Sending tftp read request... done.
10120 22:59:50.168230
10121 22:59:50.171381 Waiting for the transfer...
10122 22:59:50.171485
10123 22:59:50.820648 00000000 ################################################################
10124 22:59:50.820801
10125 22:59:51.461143 00080000 ################################################################
10126 22:59:51.461293
10127 22:59:52.103210 00100000 ################################################################
10128 22:59:52.103353
10129 22:59:52.758184 00180000 ################################################################
10130 22:59:52.758337
10131 22:59:53.414531 00200000 ################################################################
10132 22:59:53.414714
10133 22:59:54.071112 00280000 ################################################################
10134 22:59:54.071266
10135 22:59:54.720479 00300000 ################################################################
10136 22:59:54.720627
10137 22:59:55.362306 00380000 ################################################################
10138 22:59:55.362493
10139 22:59:56.011654 00400000 ################################################################
10140 22:59:56.011805
10141 22:59:56.530035 00480000 ################################################################
10142 22:59:56.530217
10143 22:59:57.058314 00500000 ################################################################
10144 22:59:57.058463
10145 22:59:57.624759 00580000 ################################################################
10146 22:59:57.624902
10147 22:59:58.228322 00600000 ################################################################
10148 22:59:58.228471
10149 22:59:58.850010 00680000 ################################################################
10150 22:59:58.850160
10151 22:59:59.431185 00700000 ################################################################
10152 22:59:59.431328
10153 23:00:00.014337 00780000 ################################################################
10154 23:00:00.014470
10155 23:00:00.567529 00800000 ################################################################
10156 23:00:00.567678
10157 23:00:01.095119 00880000 ################################################################
10158 23:00:01.095276
10159 23:00:01.648931 00900000 ################################################################
10160 23:00:01.649086
10161 23:00:02.199174 00980000 ################################################################
10162 23:00:02.199324
10163 23:00:02.737614 00a00000 ################################################################
10164 23:00:02.737801
10165 23:00:03.292640 00a80000 ################################################################
10166 23:00:03.292806
10167 23:00:03.881990 00b00000 ################################################################
10168 23:00:03.882169
10169 23:00:04.436002 00b80000 ################################################################
10170 23:00:04.436191
10171 23:00:05.006056 00c00000 ################################################################
10172 23:00:05.006222
10173 23:00:05.651943 00c80000 ################################################################
10174 23:00:05.652128
10175 23:00:06.296841 00d00000 ################################################################
10176 23:00:06.296990
10177 23:00:06.963267 00d80000 ################################################################
10178 23:00:06.963421
10179 23:00:07.655353 00e00000 ################################################################
10180 23:00:07.655507
10181 23:00:08.327853 00e80000 ################################################################
10182 23:00:08.328027
10183 23:00:08.936604 00f00000 ################################################################
10184 23:00:08.936801
10185 23:00:09.476090 00f80000 ################################################################
10186 23:00:09.476242
10187 23:00:10.006438 01000000 ################################################################
10188 23:00:10.006577
10189 23:00:10.525588 01080000 ################################################################
10190 23:00:10.525758
10191 23:00:11.039785 01100000 ################################################################
10192 23:00:11.039967
10193 23:00:11.556760 01180000 ################################################################
10194 23:00:11.556905
10195 23:00:12.090859 01200000 ################################################################
10196 23:00:12.091041
10197 23:00:12.613391 01280000 ################################################################
10198 23:00:12.613566
10199 23:00:13.142913 01300000 ################################################################
10200 23:00:13.143075
10201 23:00:13.681324 01380000 ################################################################
10202 23:00:13.681476
10203 23:00:14.207027 01400000 ################################################################
10204 23:00:14.207184
10205 23:00:14.746112 01480000 ################################################################
10206 23:00:14.746268
10207 23:00:15.295420 01500000 ################################################################
10208 23:00:15.295594
10209 23:00:15.940070 01580000 ################################################################
10210 23:00:15.940236
10211 23:00:16.579338 01600000 ################################################################
10212 23:00:16.579525
10213 23:00:17.224377 01680000 ################################################################
10214 23:00:17.224555
10215 23:00:17.880667 01700000 ################################################################
10216 23:00:17.880814
10217 23:00:18.523737 01780000 ################################################################
10218 23:00:18.523892
10219 23:00:19.165648 01800000 ################################################################
10220 23:00:19.165798
10221 23:00:19.821153 01880000 ################################################################
10222 23:00:19.821306
10223 23:00:20.502347 01900000 ################################################################
10224 23:00:20.502501
10225 23:00:21.034077 01980000 ################################################################
10226 23:00:21.034235
10227 23:00:21.578304 01a00000 ############################################################### done.
10228 23:00:21.578451
10229 23:00:21.582368 The bootfile was 27772326 bytes long.
10230 23:00:21.582553
10231 23:00:21.585047 Sending tftp read request... done.
10232 23:00:21.585200
10233 23:00:21.588340 Waiting for the transfer...
10234 23:00:21.588499
10235 23:00:21.588581 00000000 # done.
10236 23:00:21.588659
10237 23:00:21.598876 Command line loaded dynamically from TFTP file: 10597701/tftp-deploy-gimehd2h/kernel/cmdline
10238 23:00:21.599063
10239 23:00:21.617769 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10597701/extract-nfsrootfs-vfhoriyx,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10240 23:00:21.618021
10241 23:00:21.618209 Loading FIT.
10242 23:00:21.618350
10243 23:00:21.621159 Image ramdisk-1 has 17637423 bytes.
10244 23:00:21.621331
10245 23:00:21.624412 Image fdt-1 has 46924 bytes.
10246 23:00:21.624632
10247 23:00:21.627704 Image kernel-1 has 10085945 bytes.
10248 23:00:21.627965
10249 23:00:21.634433 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10250 23:00:21.634755
10251 23:00:21.654340 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10252 23:00:21.654951
10253 23:00:21.657456 Choosing best match conf-1 for compat google,spherion-rev2.
10254 23:00:21.663099
10255 23:00:21.667744 Connected to device vid:did:rid of 1ae0:0028:00
10256 23:00:21.674676
10257 23:00:21.677910 tpm_get_response: command 0x17b, return code 0x0
10258 23:00:21.678552
10259 23:00:21.681508 ec_init: CrosEC protocol v3 supported (256, 248)
10260 23:00:21.684980
10261 23:00:21.688469 tpm_cleanup: add release locality here.
10262 23:00:21.689010
10263 23:00:21.689643 Shutting down all USB controllers.
10264 23:00:21.691617
10265 23:00:21.692169 Removing current net device
10266 23:00:21.692587
10267 23:00:21.698530 Exiting depthcharge with code 4 at timestamp: 67135819
10268 23:00:21.699114
10269 23:00:21.701674 LZMA decompressing kernel-1 to 0x821a6718
10270 23:00:21.702128
10271 23:00:21.704952 LZMA decompressing kernel-1 to 0x40000000
10272 23:00:22.971469
10273 23:00:22.971652 jumping to kernel
10274 23:00:22.972146 end: 2.2.4 bootloader-commands (duration 00:00:39) [common]
10275 23:00:22.972253 start: 2.2.5 auto-login-action (timeout 00:03:46) [common]
10276 23:00:22.972338 Setting prompt string to ['Linux version [0-9]']
10277 23:00:22.972410 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10278 23:00:22.972481 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10279 23:00:23.054213
10280 23:00:23.057261 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10281 23:00:23.061121 start: 2.2.5.1 login-action (timeout 00:03:46) [common]
10282 23:00:23.061218 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10283 23:00:23.061301 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10284 23:00:23.061375 Using line separator: #'\n'#
10285 23:00:23.061435 No login prompt set.
10286 23:00:23.061493 Parsing kernel messages
10287 23:00:23.061548 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10288 23:00:23.061650 [login-action] Waiting for messages, (timeout 00:03:46)
10289 23:00:23.080966 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j1612582-arm64-gcc-10-defconfig-arm64-chromebook-7xwc5) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Jun 5 22:41:02 UTC 2023
10290 23:00:23.083489 [ 0.000000] random: crng init done
10291 23:00:23.090359 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10292 23:00:23.090441 [ 0.000000] efi: UEFI not found.
10293 23:00:23.100298 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10294 23:00:23.107025 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10295 23:00:23.116978 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10296 23:00:23.126835 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10297 23:00:23.133621 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10298 23:00:23.140400 [ 0.000000] printk: bootconsole [mtk8250] enabled
10299 23:00:23.146655 [ 0.000000] NUMA: No NUMA configuration found
10300 23:00:23.153321 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10301 23:00:23.156598 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcda00-0x23efcffff]
10302 23:00:23.159559 [ 0.000000] Zone ranges:
10303 23:00:23.166485 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10304 23:00:23.169618 [ 0.000000] DMA32 empty
10305 23:00:23.176012 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10306 23:00:23.179604 [ 0.000000] Movable zone start for each node
10307 23:00:23.183248 [ 0.000000] Early memory node ranges
10308 23:00:23.189209 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10309 23:00:23.195620 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10310 23:00:23.202791 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10311 23:00:23.209402 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10312 23:00:23.215575 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10313 23:00:23.222131 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10314 23:00:23.278273 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10315 23:00:23.284471 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10316 23:00:23.291293 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10317 23:00:23.294973 [ 0.000000] psci: probing for conduit method from DT.
10318 23:00:23.301265 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10319 23:00:23.304491 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10320 23:00:23.311044 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10321 23:00:23.314380 [ 0.000000] psci: SMC Calling Convention v1.2
10322 23:00:23.320716 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10323 23:00:23.324018 [ 0.000000] Detected VIPT I-cache on CPU0
10324 23:00:23.330465 [ 0.000000] CPU features: detected: GIC system register CPU interface
10325 23:00:23.337490 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10326 23:00:23.344218 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10327 23:00:23.350683 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10328 23:00:23.360709 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10329 23:00:23.366917 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10330 23:00:23.370758 [ 0.000000] alternatives: applying boot alternatives
10331 23:00:23.377156 [ 0.000000] Fallback order for Node 0: 0
10332 23:00:23.383667 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10333 23:00:23.386985 [ 0.000000] Policy zone: Normal
10334 23:00:23.406903 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10597701/extract-nfsrootfs-vfhoriyx,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10335 23:00:23.416340 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10336 23:00:23.428646 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10337 23:00:23.438222 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10338 23:00:23.444866 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10339 23:00:23.448363 <6>[ 0.000000] software IO TLB: area num 8.
10340 23:00:23.504871 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10341 23:00:23.653828 <6>[ 0.000000] Memory: 7955720K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 397048K reserved, 32768K cma-reserved)
10342 23:00:23.660440 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10343 23:00:23.667141 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10344 23:00:23.670426 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10345 23:00:23.677084 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10346 23:00:23.683778 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10347 23:00:23.687168 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10348 23:00:23.696804 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10349 23:00:23.703160 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10350 23:00:23.710216 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10351 23:00:23.716282 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10352 23:00:23.719736 <6>[ 0.000000] GICv3: 608 SPIs implemented
10353 23:00:23.722853 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10354 23:00:23.729395 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10355 23:00:23.732614 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10356 23:00:23.739442 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10357 23:00:23.752508 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10358 23:00:23.765825 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10359 23:00:23.772504 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10360 23:00:23.780282 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10361 23:00:23.793420 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10362 23:00:23.799970 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10363 23:00:23.806739 <6>[ 0.009233] Console: colour dummy device 80x25
10364 23:00:23.817091 <6>[ 0.013960] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10365 23:00:23.823536 <6>[ 0.024467] pid_max: default: 32768 minimum: 301
10366 23:00:23.826671 <6>[ 0.029370] LSM: Security Framework initializing
10367 23:00:23.833479 <6>[ 0.034306] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10368 23:00:23.843397 <6>[ 0.042120] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10369 23:00:23.853091 <6>[ 0.051432] cblist_init_generic: Setting adjustable number of callback queues.
10370 23:00:23.859495 <6>[ 0.058934] cblist_init_generic: Setting shift to 3 and lim to 1.
10371 23:00:23.862815 <6>[ 0.065312] cblist_init_generic: Setting shift to 3 and lim to 1.
10372 23:00:23.869390 <6>[ 0.071720] rcu: Hierarchical SRCU implementation.
10373 23:00:23.876011 <6>[ 0.076764] rcu: Max phase no-delay instances is 1000.
10374 23:00:23.882613 <6>[ 0.083819] EFI services will not be available.
10375 23:00:23.885979 <6>[ 0.088820] smp: Bringing up secondary CPUs ...
10376 23:00:23.893890 <6>[ 0.093874] Detected VIPT I-cache on CPU1
10377 23:00:23.900493 <6>[ 0.093945] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10378 23:00:23.907119 <6>[ 0.093975] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10379 23:00:23.910537 <6>[ 0.094310] Detected VIPT I-cache on CPU2
10380 23:00:23.916922 <6>[ 0.094365] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10381 23:00:23.927139 <6>[ 0.094382] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10382 23:00:23.930166 <6>[ 0.094648] Detected VIPT I-cache on CPU3
10383 23:00:23.937494 <6>[ 0.094694] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10384 23:00:23.943269 <6>[ 0.094708] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10385 23:00:23.946508 <6>[ 0.095015] CPU features: detected: Spectre-v4
10386 23:00:23.953281 <6>[ 0.095022] CPU features: detected: Spectre-BHB
10387 23:00:23.956679 <6>[ 0.095027] Detected PIPT I-cache on CPU4
10388 23:00:23.963249 <6>[ 0.095085] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10389 23:00:23.969962 <6>[ 0.095101] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10390 23:00:23.976485 <6>[ 0.095398] Detected PIPT I-cache on CPU5
10391 23:00:23.983173 <6>[ 0.095458] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10392 23:00:23.989387 <6>[ 0.095475] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10393 23:00:23.993354 <6>[ 0.095759] Detected PIPT I-cache on CPU6
10394 23:00:23.999128 <6>[ 0.095825] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10395 23:00:24.005878 <6>[ 0.095841] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10396 23:00:24.012935 <6>[ 0.096140] Detected PIPT I-cache on CPU7
10397 23:00:24.019518 <6>[ 0.096204] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10398 23:00:24.025858 <6>[ 0.096220] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10399 23:00:24.029262 <6>[ 0.096268] smp: Brought up 1 node, 8 CPUs
10400 23:00:24.035962 <6>[ 0.237540] SMP: Total of 8 processors activated.
10401 23:00:24.038923 <6>[ 0.242492] CPU features: detected: 32-bit EL0 Support
10402 23:00:24.049438 <6>[ 0.247888] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10403 23:00:24.055676 <6>[ 0.256688] CPU features: detected: Common not Private translations
10404 23:00:24.062187 <6>[ 0.263163] CPU features: detected: CRC32 instructions
10405 23:00:24.068765 <6>[ 0.268548] CPU features: detected: RCpc load-acquire (LDAPR)
10406 23:00:24.072219 <6>[ 0.274545] CPU features: detected: LSE atomic instructions
10407 23:00:24.078706 <6>[ 0.280362] CPU features: detected: Privileged Access Never
10408 23:00:24.085404 <6>[ 0.286177] CPU features: detected: RAS Extension Support
10409 23:00:24.092077 <6>[ 0.291786] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10410 23:00:24.095506 <6>[ 0.299007] CPU: All CPU(s) started at EL2
10411 23:00:24.102025 <6>[ 0.303323] alternatives: applying system-wide alternatives
10412 23:00:24.111573 <6>[ 0.314063] devtmpfs: initialized
10413 23:00:24.127840 <6>[ 0.322934] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10414 23:00:24.134118 <6>[ 0.332895] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10415 23:00:24.140395 <6>[ 0.340969] pinctrl core: initialized pinctrl subsystem
10416 23:00:24.144247 <6>[ 0.347620] DMI not present or invalid.
10417 23:00:24.150500 <6>[ 0.351968] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10418 23:00:24.160560 <6>[ 0.358853] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10419 23:00:24.166876 <6>[ 0.366434] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10420 23:00:24.176891 <6>[ 0.374651] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10421 23:00:24.180291 <6>[ 0.382894] audit: initializing netlink subsys (disabled)
10422 23:00:24.190355 <5>[ 0.388586] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10423 23:00:24.196695 <6>[ 0.389291] thermal_sys: Registered thermal governor 'step_wise'
10424 23:00:24.203337 <6>[ 0.396549] thermal_sys: Registered thermal governor 'power_allocator'
10425 23:00:24.206461 <6>[ 0.402802] cpuidle: using governor menu
10426 23:00:24.212893 <6>[ 0.413763] NET: Registered PF_QIPCRTR protocol family
10427 23:00:24.219673 <6>[ 0.419226] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10428 23:00:24.226269 <6>[ 0.426325] ASID allocator initialised with 32768 entries
10429 23:00:24.229044 <6>[ 0.432880] Serial: AMBA PL011 UART driver
10430 23:00:24.238941 <4>[ 0.441521] Trying to register duplicate clock ID: 134
10431 23:00:24.293120 <6>[ 0.498676] KASLR enabled
10432 23:00:24.307474 <6>[ 0.506343] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10433 23:00:24.313760 <6>[ 0.513356] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10434 23:00:24.320647 <6>[ 0.519846] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10435 23:00:24.327079 <6>[ 0.526852] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10436 23:00:24.333829 <6>[ 0.533341] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10437 23:00:24.340337 <6>[ 0.540349] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10438 23:00:24.346966 <6>[ 0.546834] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10439 23:00:24.353684 <6>[ 0.553842] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10440 23:00:24.356582 <6>[ 0.561317] ACPI: Interpreter disabled.
10441 23:00:24.365562 <6>[ 0.567740] iommu: Default domain type: Translated
10442 23:00:24.372039 <6>[ 0.572855] iommu: DMA domain TLB invalidation policy: strict mode
10443 23:00:24.375155 <5>[ 0.579515] SCSI subsystem initialized
10444 23:00:24.382003 <6>[ 0.583751] usbcore: registered new interface driver usbfs
10445 23:00:24.388302 <6>[ 0.589478] usbcore: registered new interface driver hub
10446 23:00:24.391468 <6>[ 0.595030] usbcore: registered new device driver usb
10447 23:00:24.399214 <6>[ 0.601131] pps_core: LinuxPPS API ver. 1 registered
10448 23:00:24.409282 <6>[ 0.606325] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10449 23:00:24.411868 <6>[ 0.615665] PTP clock support registered
10450 23:00:24.415283 <6>[ 0.619905] EDAC MC: Ver: 3.0.0
10451 23:00:24.422550 <6>[ 0.625079] FPGA manager framework
10452 23:00:24.429496 <6>[ 0.628756] Advanced Linux Sound Architecture Driver Initialized.
10453 23:00:24.432703 <6>[ 0.635519] vgaarb: loaded
10454 23:00:24.439329 <6>[ 0.638694] clocksource: Switched to clocksource arch_sys_counter
10455 23:00:24.442472 <5>[ 0.645143] VFS: Disk quotas dquot_6.6.0
10456 23:00:24.449285 <6>[ 0.649330] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10457 23:00:24.452195 <6>[ 0.656522] pnp: PnP ACPI: disabled
10458 23:00:24.460945 <6>[ 0.663186] NET: Registered PF_INET protocol family
10459 23:00:24.470460 <6>[ 0.668770] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10460 23:00:24.481912 <6>[ 0.681068] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10461 23:00:24.491975 <6>[ 0.689878] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10462 23:00:24.498698 <6>[ 0.697849] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10463 23:00:24.507988 <6>[ 0.706548] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10464 23:00:24.514677 <6>[ 0.716286] TCP: Hash tables configured (established 65536 bind 65536)
10465 23:00:24.521254 <6>[ 0.723145] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10466 23:00:24.531086 <6>[ 0.730342] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10467 23:00:24.537752 <6>[ 0.738041] NET: Registered PF_UNIX/PF_LOCAL protocol family
10468 23:00:24.544240 <6>[ 0.744210] RPC: Registered named UNIX socket transport module.
10469 23:00:24.547663 <6>[ 0.750364] RPC: Registered udp transport module.
10470 23:00:24.554284 <6>[ 0.755298] RPC: Registered tcp transport module.
10471 23:00:24.561084 <6>[ 0.760229] RPC: Registered tcp NFSv4.1 backchannel transport module.
10472 23:00:24.563899 <6>[ 0.766901] PCI: CLS 0 bytes, default 64
10473 23:00:24.567691 <6>[ 0.771180] Unpacking initramfs...
10474 23:00:24.591612 <6>[ 0.790815] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10475 23:00:24.601780 <6>[ 0.799481] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10476 23:00:24.605233 <6>[ 0.808328] kvm [1]: IPA Size Limit: 40 bits
10477 23:00:24.611778 <6>[ 0.812853] kvm [1]: GICv3: no GICV resource entry
10478 23:00:24.614737 <6>[ 0.817873] kvm [1]: disabling GICv2 emulation
10479 23:00:24.621392 <6>[ 0.822557] kvm [1]: GIC system register CPU interface enabled
10480 23:00:24.624589 <6>[ 0.828725] kvm [1]: vgic interrupt IRQ18
10481 23:00:24.631334 <6>[ 0.833079] kvm [1]: VHE mode initialized successfully
10482 23:00:24.637762 <5>[ 0.839506] Initialise system trusted keyrings
10483 23:00:24.644464 <6>[ 0.844323] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10484 23:00:24.651904 <6>[ 0.854304] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10485 23:00:24.658687 <5>[ 0.860675] NFS: Registering the id_resolver key type
10486 23:00:24.661874 <5>[ 0.865973] Key type id_resolver registered
10487 23:00:24.668375 <5>[ 0.870390] Key type id_legacy registered
10488 23:00:24.675482 <6>[ 0.874668] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10489 23:00:24.681902 <6>[ 0.881588] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10490 23:00:24.687964 <6>[ 0.889294] 9p: Installing v9fs 9p2000 file system support
10491 23:00:24.724536 <5>[ 0.927213] Key type asymmetric registered
10492 23:00:24.727749 <5>[ 0.931547] Asymmetric key parser 'x509' registered
10493 23:00:24.737658 <6>[ 0.936692] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10494 23:00:24.740961 <6>[ 0.944323] io scheduler mq-deadline registered
10495 23:00:24.744413 <6>[ 0.949092] io scheduler kyber registered
10496 23:00:24.763079 <6>[ 0.965798] EINJ: ACPI disabled.
10497 23:00:24.795547 <4>[ 0.991235] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10498 23:00:24.804954 <4>[ 1.001889] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10499 23:00:24.819804 <6>[ 1.022580] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10500 23:00:24.828022 <6>[ 1.030655] printk: console [ttyS0] disabled
10501 23:00:24.856374 <6>[ 1.055308] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10502 23:00:24.862749 <6>[ 1.064783] printk: console [ttyS0] enabled
10503 23:00:24.866044 <6>[ 1.064783] printk: console [ttyS0] enabled
10504 23:00:24.872553 <6>[ 1.073678] printk: bootconsole [mtk8250] disabled
10505 23:00:24.875999 <6>[ 1.073678] printk: bootconsole [mtk8250] disabled
10506 23:00:24.882825 <6>[ 1.084989] SuperH (H)SCI(F) driver initialized
10507 23:00:24.886134 <6>[ 1.090272] msm_serial: driver initialized
10508 23:00:24.900071 <6>[ 1.099200] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10509 23:00:24.910152 <6>[ 1.107746] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10510 23:00:24.916647 <6>[ 1.116288] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10511 23:00:24.926986 <6>[ 1.124917] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10512 23:00:24.933685 <6>[ 1.133625] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10513 23:00:24.943396 <6>[ 1.142338] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10514 23:00:24.953492 <6>[ 1.150879] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10515 23:00:24.959910 <6>[ 1.159684] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10516 23:00:24.969682 <6>[ 1.168227] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10517 23:00:24.981265 <6>[ 1.183793] loop: module loaded
10518 23:00:24.987864 <6>[ 1.189782] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10519 23:00:25.010381 <4>[ 1.213097] mtk-pmic-keys: Failed to locate of_node [id: -1]
10520 23:00:25.017088 <6>[ 1.219880] megasas: 07.719.03.00-rc1
10521 23:00:25.026855 <6>[ 1.229373] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10522 23:00:25.036256 <6>[ 1.238069] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10523 23:00:25.052538 <6>[ 1.254798] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10524 23:00:25.109297 <6>[ 1.305460] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9
10525 23:00:25.301980 <6>[ 1.504406] Freeing initrd memory: 17220K
10526 23:00:25.312715 <6>[ 1.514807] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10527 23:00:25.322869 <6>[ 1.525598] tun: Universal TUN/TAP device driver, 1.6
10528 23:00:25.326848 <6>[ 1.531655] thunder_xcv, ver 1.0
10529 23:00:25.329705 <6>[ 1.535161] thunder_bgx, ver 1.0
10530 23:00:25.332944 <6>[ 1.538650] nicpf, ver 1.0
10531 23:00:25.343924 <6>[ 1.542637] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10532 23:00:25.346884 <6>[ 1.550113] hns3: Copyright (c) 2017 Huawei Corporation.
10533 23:00:25.350032 <6>[ 1.555699] hclge is initializing
10534 23:00:25.356984 <6>[ 1.559283] e1000: Intel(R) PRO/1000 Network Driver
10535 23:00:25.363579 <6>[ 1.564412] e1000: Copyright (c) 1999-2006 Intel Corporation.
10536 23:00:25.366889 <6>[ 1.570425] e1000e: Intel(R) PRO/1000 Network Driver
10537 23:00:25.373648 <6>[ 1.575640] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10538 23:00:25.379962 <6>[ 1.581826] igb: Intel(R) Gigabit Ethernet Network Driver
10539 23:00:25.386701 <6>[ 1.587476] igb: Copyright (c) 2007-2014 Intel Corporation.
10540 23:00:25.393221 <6>[ 1.593313] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10541 23:00:25.399699 <6>[ 1.599831] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10542 23:00:25.402837 <6>[ 1.606287] sky2: driver version 1.30
10543 23:00:25.409846 <6>[ 1.611272] VFIO - User Level meta-driver version: 0.3
10544 23:00:25.416966 <6>[ 1.619495] usbcore: registered new interface driver usb-storage
10545 23:00:25.423815 <6>[ 1.625933] usbcore: registered new device driver onboard-usb-hub
10546 23:00:25.432497 <6>[ 1.635038] mt6397-rtc mt6359-rtc: registered as rtc0
10547 23:00:25.442871 <6>[ 1.640502] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-05T23:00:25 UTC (1686006025)
10548 23:00:25.446261 <6>[ 1.650060] i2c_dev: i2c /dev entries driver
10549 23:00:25.462236 <6>[ 1.661611] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10550 23:00:25.469394 <6>[ 1.671796] sdhci: Secure Digital Host Controller Interface driver
10551 23:00:25.475971 <6>[ 1.678233] sdhci: Copyright(c) Pierre Ossman
10552 23:00:25.482446 <6>[ 1.683623] Synopsys Designware Multimedia Card Interface Driver
10553 23:00:25.485727 <6>[ 1.690222] mmc0: CQHCI version 5.10
10554 23:00:25.492516 <6>[ 1.690783] sdhci-pltfm: SDHCI platform and OF driver helper
10555 23:00:25.499627 <6>[ 1.702167] ledtrig-cpu: registered to indicate activity on CPUs
10556 23:00:25.510420 <6>[ 1.709466] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10557 23:00:25.513615 <6>[ 1.716850] usbcore: registered new interface driver usbhid
10558 23:00:25.520263 <6>[ 1.722686] usbhid: USB HID core driver
10559 23:00:25.526930 <6>[ 1.726929] spi_master spi0: will run message pump with realtime priority
10560 23:00:25.570434 <6>[ 1.766344] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10561 23:00:25.589460 <6>[ 1.781391] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10562 23:00:25.592503 <6>[ 1.794977] mmc0: Command Queue Engine enabled
10563 23:00:25.599704 <6>[ 1.796941] cros-ec-spi spi0.0: Chrome EC device registered
10564 23:00:25.606338 <6>[ 1.799723] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10565 23:00:25.609792 <6>[ 1.812828] mmcblk0: mmc0:0001 DA4128 116 GiB
10566 23:00:25.619997 <6>[ 1.822478] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10567 23:00:25.630107 <6>[ 1.822665] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10568 23:00:25.636626 <6>[ 1.829853] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10569 23:00:25.639818 <6>[ 1.839821] NET: Registered PF_PACKET protocol family
10570 23:00:25.646637 <6>[ 1.843582] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10571 23:00:25.650221 <6>[ 1.848345] 9pnet: Installing 9P2000 support
10572 23:00:25.656529 <6>[ 1.854129] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10573 23:00:25.663370 <5>[ 1.858037] Key type dns_resolver registered
10574 23:00:25.666402 <6>[ 1.869572] registered taskstats version 1
10575 23:00:25.672809 <5>[ 1.873952] Loading compiled-in X.509 certificates
10576 23:00:25.705104 <4>[ 1.900874] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10577 23:00:25.714883 <4>[ 1.911572] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10578 23:00:25.725392 <3>[ 1.924473] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10579 23:00:25.737727 <6>[ 1.940201] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10580 23:00:25.744467 <6>[ 1.946990] xhci-mtk 11200000.usb: xHCI Host Controller
10581 23:00:25.751253 <6>[ 1.952484] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10582 23:00:25.761486 <6>[ 1.960335] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10583 23:00:25.767473 <6>[ 1.969769] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10584 23:00:25.774476 <6>[ 1.975861] xhci-mtk 11200000.usb: xHCI Host Controller
10585 23:00:25.780763 <6>[ 1.981346] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10586 23:00:25.787407 <6>[ 1.988998] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10587 23:00:25.794077 <6>[ 1.996723] hub 1-0:1.0: USB hub found
10588 23:00:25.797918 <6>[ 2.000757] hub 1-0:1.0: 1 port detected
10589 23:00:25.807258 <6>[ 2.005104] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10590 23:00:25.810941 <6>[ 2.013849] hub 2-0:1.0: USB hub found
10591 23:00:25.814060 <6>[ 2.017903] hub 2-0:1.0: 1 port detected
10592 23:00:25.822739 <6>[ 2.025261] mtk-msdc 11f70000.mmc: Got CD GPIO
10593 23:00:25.839475 <6>[ 2.038545] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10594 23:00:25.846024 <6>[ 2.046613] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10595 23:00:25.855966 <4>[ 2.054578] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10596 23:00:25.866155 <6>[ 2.064252] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10597 23:00:25.872737 <6>[ 2.072335] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10598 23:00:25.879103 <6>[ 2.080352] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10599 23:00:25.889331 <6>[ 2.088267] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10600 23:00:25.895857 <6>[ 2.096090] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10601 23:00:25.905423 <6>[ 2.103911] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10602 23:00:25.915350 <6>[ 2.114610] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10603 23:00:25.922489 <6>[ 2.122990] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10604 23:00:25.932125 <6>[ 2.131346] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10605 23:00:25.942101 <6>[ 2.139689] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10606 23:00:25.948655 <6>[ 2.148032] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10607 23:00:25.958531 <6>[ 2.156375] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10608 23:00:25.965259 <6>[ 2.164718] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10609 23:00:25.974882 <6>[ 2.173061] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10610 23:00:25.981634 <6>[ 2.181404] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10611 23:00:25.991567 <6>[ 2.189746] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10612 23:00:25.997974 <6>[ 2.198089] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10613 23:00:26.008183 <6>[ 2.206432] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10614 23:00:26.014812 <6>[ 2.214775] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10615 23:00:26.024512 <6>[ 2.223118] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10616 23:00:26.030997 <6>[ 2.231463] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10617 23:00:26.037746 <6>[ 2.240390] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10618 23:00:26.044985 <6>[ 2.247847] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10619 23:00:26.052276 <6>[ 2.254878] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10620 23:00:26.062782 <6>[ 2.261960] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10621 23:00:26.069569 <6>[ 2.269226] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10622 23:00:26.079017 <6>[ 2.276122] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10623 23:00:26.085644 <6>[ 2.285270] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10624 23:00:26.095653 <6>[ 2.294398] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10625 23:00:26.105410 <6>[ 2.303701] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10626 23:00:26.115407 <6>[ 2.313177] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10627 23:00:26.125392 <6>[ 2.322655] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10628 23:00:26.132155 <6>[ 2.331784] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10629 23:00:26.141868 <6>[ 2.341257] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10630 23:00:26.151794 <6>[ 2.350384] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10631 23:00:26.161904 <6>[ 2.359686] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10632 23:00:26.171548 <6>[ 2.369853] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10633 23:00:26.182559 <6>[ 2.381743] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10634 23:00:26.189005 <6>[ 2.391648] Trying to probe devices needed for running init ...
10635 23:00:26.203243 <6>[ 2.402947] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10636 23:00:26.230874 <6>[ 2.433222] hub 2-1:1.0: USB hub found
10637 23:00:26.233619 <6>[ 2.437604] hub 2-1:1.0: 3 ports detected
10638 23:00:26.355477 <6>[ 2.554903] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10639 23:00:26.509871 <6>[ 2.712347] hub 1-1:1.0: USB hub found
10640 23:00:26.513121 <6>[ 2.716832] hub 1-1:1.0: 4 ports detected
10641 23:00:26.587914 <6>[ 2.787204] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10642 23:00:26.836455 <6>[ 3.034964] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10643 23:00:26.968838 <6>[ 3.171153] hub 1-1.4:1.0: USB hub found
10644 23:00:26.972598 <6>[ 3.175808] hub 1-1.4:1.0: 2 ports detected
10645 23:00:27.268255 <6>[ 3.466966] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10646 23:00:27.459526 <6>[ 3.658967] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10647 23:00:38.460696 <6>[ 14.667533] ALSA device list:
10648 23:00:38.467017 <6>[ 14.670790] No soundcards found.
10649 23:00:38.479500 <6>[ 14.683147] Freeing unused kernel memory: 8384K
10650 23:00:38.482476 <6>[ 14.688077] Run /init as init process
10651 23:00:38.492948 Loading, please wait...
10652 23:00:38.512381 Starting version 247.3-7+deb11u2
10653 23:00:38.825955 <6>[ 15.026361] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10654 23:00:38.840584 <6>[ 15.043905] remoteproc remoteproc0: scp is available
10655 23:00:38.849896 <4>[ 15.049329] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10656 23:00:38.856547 <6>[ 15.059540] remoteproc remoteproc0: powering up scp
10657 23:00:38.866364 <4>[ 15.064904] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10658 23:00:38.873244 <3>[ 15.065850] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10659 23:00:38.879654 <3>[ 15.074736] remoteproc remoteproc0: request_firmware failed: -2
10660 23:00:38.889431 <3>[ 15.089176] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10661 23:00:38.896688 <3>[ 15.097287] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10662 23:00:38.915962 <6>[ 15.116502] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10663 23:00:38.922602 <6>[ 15.124185] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10664 23:00:38.932370 <3>[ 15.127611] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10665 23:00:38.935388 <6>[ 15.131049] mc: Linux media interface: v0.10
10666 23:00:38.945544 <6>[ 15.131177] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10667 23:00:38.952218 <6>[ 15.132886] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10668 23:00:38.958794 <4>[ 15.157011] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10669 23:00:38.968750 <3>[ 15.161933] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10670 23:00:38.975437 <6>[ 15.164033] videodev: Linux video capture interface: v2.00
10671 23:00:38.982269 <4>[ 15.169566] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10672 23:00:38.989254 <4>[ 15.172451] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10673 23:00:38.995707 <4>[ 15.172451] Fallback method does not support PEC.
10674 23:00:39.002001 <3>[ 15.177377] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10675 23:00:39.008735 <6>[ 15.193881] usbcore: registered new interface driver r8152
10676 23:00:39.018716 <3>[ 15.204148] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10677 23:00:39.025233 <3>[ 15.204160] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10678 23:00:39.031996 <3>[ 15.204258] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10679 23:00:39.042871 <3>[ 15.213762] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10680 23:00:39.049735 <3>[ 15.218095] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10681 23:00:39.059368 <3>[ 15.249416] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10682 23:00:39.066441 <3>[ 15.251050] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10683 23:00:39.072528 <6>[ 15.256132] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10684 23:00:39.079250 <6>[ 15.256140] pci_bus 0000:00: root bus resource [bus 00-ff]
10685 23:00:39.085976 <6>[ 15.256148] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10686 23:00:39.096061 <6>[ 15.256154] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10687 23:00:39.102778 <6>[ 15.256186] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10688 23:00:39.109406 <6>[ 15.256204] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10689 23:00:39.115886 <6>[ 15.256282] pci 0000:00:00.0: supports D1 D2
10690 23:00:39.122661 <6>[ 15.256286] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10691 23:00:39.129167 <6>[ 15.258093] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10692 23:00:39.135397 <6>[ 15.258191] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10693 23:00:39.145707 <6>[ 15.258220] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10694 23:00:39.152245 <6>[ 15.258238] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10695 23:00:39.158802 <6>[ 15.258256] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10696 23:00:39.162012 <6>[ 15.258367] pci 0000:01:00.0: supports D1 D2
10697 23:00:39.169255 <6>[ 15.258370] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10698 23:00:39.178505 <6>[ 15.266735] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10699 23:00:39.185202 <3>[ 15.267902] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10700 23:00:39.191959 <6>[ 15.276009] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10701 23:00:39.205220 <6>[ 15.276468] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10702 23:00:39.211468 <6>[ 15.276840] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10703 23:00:39.221407 <3>[ 15.282904] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10704 23:00:39.228125 <6>[ 15.288581] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10705 23:00:39.237972 <6>[ 15.291698] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10706 23:00:39.244618 <3>[ 15.295710] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10707 23:00:39.254522 <6>[ 15.305631] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10708 23:00:39.261321 <3>[ 15.311888] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10709 23:00:39.267751 <6>[ 15.314939] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10710 23:00:39.277182 <6>[ 15.319377] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10711 23:00:39.284255 <6>[ 15.319806] usbcore: registered new interface driver cdc_ether
10712 23:00:39.290653 <3>[ 15.323949] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10713 23:00:39.300728 <3>[ 15.323960] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10714 23:00:39.307130 <3>[ 15.324012] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10715 23:00:39.313552 <6>[ 15.324504] usbcore: registered new interface driver r8153_ecm
10716 23:00:39.320624 <6>[ 15.327186] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10717 23:00:39.333494 <6>[ 15.328852] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10718 23:00:39.340180 <6>[ 15.329072] usbcore: registered new interface driver uvcvideo
10719 23:00:39.346518 <6>[ 15.330882] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10720 23:00:39.357094 <4>[ 15.338068] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10721 23:00:39.363316 <4>[ 15.338078] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10722 23:00:39.366548 <6>[ 15.340123] Bluetooth: Core ver 2.22
10723 23:00:39.373529 <6>[ 15.345401] pci 0000:00:00.0: PCI bridge to [bus 01]
10724 23:00:39.379776 <6>[ 15.352938] NET: Registered PF_BLUETOOTH protocol family
10725 23:00:39.387040 <6>[ 15.360346] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10726 23:00:39.393164 <6>[ 15.361038] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10727 23:00:39.399821 <6>[ 15.367813] Bluetooth: HCI device and connection manager initialized
10728 23:00:39.406551 <6>[ 15.372454] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10729 23:00:39.412944 <6>[ 15.379205] Bluetooth: HCI socket layer initialized
10730 23:00:39.416275 <6>[ 15.386920] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10731 23:00:39.422831 <6>[ 15.386944] r8152 2-1.3:1.0 eth0: v1.12.13
10732 23:00:39.426011 <6>[ 15.394147] Bluetooth: L2CAP socket layer initialized
10733 23:00:39.432595 <6>[ 15.394156] Bluetooth: SCO socket layer initialized
10734 23:00:39.439172 <6>[ 15.394632] r8152 2-1.3:1.0 enx002432307c7b: renamed from eth0
10735 23:00:39.442921 <6>[ 15.402421] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10736 23:00:39.449121 <6>[ 15.463627] usbcore: registered new interface driver btusb
10737 23:00:39.459113 <4>[ 15.464380] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10738 23:00:39.465358 <3>[ 15.464391] Bluetooth: hci0: Failed to load firmware file (-2)
10739 23:00:39.472767 <3>[ 15.464395] Bluetooth: hci0: Failed to set up firmware (-2)
10740 23:00:39.481787 <4>[ 15.464398] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10741 23:00:39.496089 <5>[ 15.696758] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10742 23:00:39.516138 <5>[ 15.716336] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10743 23:00:39.522391 <4>[ 15.723238] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10744 23:00:39.528663 <6>[ 15.732119] cfg80211: failed to load regulatory.db
10745 23:00:39.574808 <6>[ 15.775359] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10746 23:00:39.581098 <6>[ 15.782974] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10747 23:00:39.605608 <6>[ 15.809750] mt7921e 0000:01:00.0: ASIC revision: 79610010
10748 23:00:39.714261 <4>[ 15.911293] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10749 23:00:39.727227 Begin: Loading essential drivers ... done.
10750 23:00:39.729875 Begin: Running /scripts/init-premount ... done.
10751 23:00:39.737129 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10752 23:00:39.746949 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10753 23:00:39.750303 Device /sys/class/net/enx002432307c7b found
10754 23:00:39.750697 done.
10755 23:00:39.839461 <4>[ 16.037159] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10756 23:00:39.846229 IP-Config: enx002432307c7b hardware address 00:24:32:30:7c:7b mtu 1500 DHCP
10757 23:00:39.958703 <4>[ 16.156495] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10758 23:00:40.074562 <4>[ 16.272309] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10759 23:00:40.190830 <4>[ 16.388304] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10760 23:00:40.306453 <4>[ 16.504233] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10761 23:00:40.422336 <4>[ 16.620176] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10762 23:00:40.538312 <4>[ 16.736163] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10763 23:00:40.654549 <4>[ 16.852165] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10764 23:00:40.770410 <4>[ 16.968042] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10765 23:00:40.834926 <6>[ 17.039242] r8152 2-1.3:1.0 enx002432307c7b: carrier on
10766 23:00:40.877561 <3>[ 17.082037] mt7921e 0000:01:00.0: hardware init failed
10767 23:00:40.936521 IP-Config: no response after 2 secs - giving up
10768 23:00:40.985870 IP-Config: enx002432307c7b hardware address 00:24:32:30:7c:7b mtu 1500 DHCP
10769 23:00:40.989267 IP-Config: enx002432307c7b complete (dhcp from 192.168.201.1):
10770 23:00:40.995816 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10771 23:00:41.005557 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10772 23:00:41.012148 host : mt8192-asurada-spherion-r0-cbg-2
10773 23:00:41.019235 domain : lava-rack
10774 23:00:41.022290 rootserver: 192.168.201.1 rootpath:
10775 23:00:41.022383 filename :
10776 23:00:41.048734 done.
10777 23:00:41.056240 Begin: Running /scripts/nfs-bottom ... done.
10778 23:00:41.073552 Begin: Running /scripts/init-bottom ... done.
10779 23:00:42.205266 <6>[ 18.409497] NET: Registered PF_INET6 protocol family
10780 23:00:42.212303 <6>[ 18.416551] Segment Routing with IPv6
10781 23:00:42.215486 <6>[ 18.420540] In-situ OAM (IOAM) with IPv6
10782 23:00:42.335823 <30>[ 18.520314] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10783 23:00:42.338717 <30>[ 18.544121] systemd[1]: Detected architecture arm64.
10784 23:00:42.359279
10785 23:00:42.362947 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10786 23:00:42.363033
10787 23:00:42.381109 <30>[ 18.585806] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10788 23:00:43.051326 <30>[ 19.252718] systemd[1]: Queued start job for default target Graphical Interface.
10789 23:00:43.079855 <30>[ 19.284047] systemd[1]: Created slice system-getty.slice.
10790 23:00:43.086754 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10791 23:00:43.103226 <30>[ 19.307497] systemd[1]: Created slice system-modprobe.slice.
10792 23:00:43.109532 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10793 23:00:43.127277 <30>[ 19.331545] systemd[1]: Created slice system-serial\x2dgetty.slice.
10794 23:00:43.137013 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10795 23:00:43.151569 <30>[ 19.355985] systemd[1]: Created slice User and Session Slice.
10796 23:00:43.158096 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10797 23:00:43.178502 <30>[ 19.379604] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10798 23:00:43.188213 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10799 23:00:43.205767 <30>[ 19.407093] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10800 23:00:43.212273 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10801 23:00:43.233220 <30>[ 19.431077] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10802 23:00:43.239943 <30>[ 19.443102] systemd[1]: Reached target Local Encrypted Volumes.
10803 23:00:43.246344 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10804 23:00:43.263066 <30>[ 19.467437] systemd[1]: Reached target Paths.
10805 23:00:43.266244 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10806 23:00:43.282723 <30>[ 19.487015] systemd[1]: Reached target Remote File Systems.
10807 23:00:43.289361 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10808 23:00:43.302336 <30>[ 19.506986] systemd[1]: Reached target Slices.
10809 23:00:43.308761 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10810 23:00:43.322445 <30>[ 19.527010] systemd[1]: Reached target Swap.
10811 23:00:43.325651 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10812 23:00:43.346150 <30>[ 19.547313] systemd[1]: Listening on initctl Compatibility Named Pipe.
10813 23:00:43.352625 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10814 23:00:43.359444 <30>[ 19.562993] systemd[1]: Listening on Journal Audit Socket.
10815 23:00:43.365980 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10816 23:00:43.379377 <30>[ 19.584142] systemd[1]: Listening on Journal Socket (/dev/log).
10817 23:00:43.386138 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10818 23:00:43.403445 <30>[ 19.607828] systemd[1]: Listening on Journal Socket.
10819 23:00:43.409827 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10820 23:00:43.427095 <30>[ 19.628456] systemd[1]: Listening on Network Service Netlink Socket.
10821 23:00:43.433805 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10822 23:00:43.449721 <30>[ 19.654043] systemd[1]: Listening on udev Control Socket.
10823 23:00:43.456066 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10824 23:00:43.470965 <30>[ 19.675255] systemd[1]: Listening on udev Kernel Socket.
10825 23:00:43.477599 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10826 23:00:43.518837 <30>[ 19.723228] systemd[1]: Mounting Huge Pages File System...
10827 23:00:43.525169 Mounting [0;1;39mHuge Pages File System[0m...
10828 23:00:43.541137 <30>[ 19.745625] systemd[1]: Mounting POSIX Message Queue File System...
10829 23:00:43.547552 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10830 23:00:43.565178 <30>[ 19.769323] systemd[1]: Mounting Kernel Debug File System...
10831 23:00:43.571476 Mounting [0;1;39mKernel Debug File System[0m...
10832 23:00:43.590219 <30>[ 19.791261] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10833 23:00:43.601885 <30>[ 19.803383] systemd[1]: Starting Create list of static device nodes for the current kernel...
10834 23:00:43.608637 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10835 23:00:43.629530 <30>[ 19.833933] systemd[1]: Starting Load Kernel Module configfs...
10836 23:00:43.635988 Starting [0;1;39mLoad Kernel Module configfs[0m...
10837 23:00:43.653038 <30>[ 19.857625] systemd[1]: Starting Load Kernel Module drm...
10838 23:00:43.659793 Starting [0;1;39mLoad Kernel Module drm[0m...
10839 23:00:43.677191 <30>[ 19.881495] systemd[1]: Starting Load Kernel Module fuse...
10840 23:00:43.683566 Starting [0;1;39mLoad Kernel Module fuse[0m...
10841 23:00:43.718198 <6>[ 19.922582] fuse: init (API version 7.37)
10842 23:00:43.727815 <30>[ 19.923336] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10843 23:00:43.750872 <30>[ 19.955478] systemd[1]: Starting Journal Service...
10844 23:00:43.754526 Starting [0;1;39mJournal Service[0m...
10845 23:00:43.778994 <30>[ 19.983412] systemd[1]: Starting Load Kernel Modules...
10846 23:00:43.785416 Starting [0;1;39mLoad Kernel Modules[0m...
10847 23:00:43.804277 <30>[ 20.005628] systemd[1]: Starting Remount Root and Kernel File Systems...
10848 23:00:43.810824 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10849 23:00:43.847115 <30>[ 20.051591] systemd[1]: Starting Coldplug All udev Devices...
10850 23:00:43.853332 Starting [0;1;39mColdplug All udev Devices[0m...
10851 23:00:43.869666 <30>[ 20.074133] systemd[1]: Mounted Huge Pages File System.
10852 23:00:43.876395 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10853 23:00:43.890904 <30>[ 20.095558] systemd[1]: Mounted POSIX Message Queue File System.
10854 23:00:43.897597 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10855 23:00:43.915520 <3>[ 20.116622] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10856 23:00:43.922499 <30>[ 20.126047] systemd[1]: Mounted Kernel Debug File System.
10857 23:00:43.928279 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10858 23:00:43.944742 <3>[ 20.146287] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10859 23:00:43.954990 <30>[ 20.156185] systemd[1]: Finished Create list of static device nodes for the current kernel.
10860 23:00:43.965001 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10861 23:00:43.984475 <30>[ 20.188184] systemd[1]: modprobe@configfs.service: Succeeded.
10862 23:00:43.994388 <3>[ 20.193097] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10863 23:00:44.000918 <30>[ 20.194887] systemd[1]: Finished Load Kernel Module configfs.
10864 23:00:44.007489 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10865 23:00:44.023028 <3>[ 20.224257] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10866 23:00:44.030351 <30>[ 20.234796] systemd[1]: modprobe@drm.service: Succeeded.
10867 23:00:44.037186 <30>[ 20.241036] systemd[1]: Finished Load Kernel Module drm.
10868 23:00:44.043845 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10869 23:00:44.053558 <3>[ 20.254223] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10870 23:00:44.060276 <30>[ 20.264420] systemd[1]: modprobe@fuse.service: Succeeded.
10871 23:00:44.067069 <30>[ 20.271125] systemd[1]: Finished Load Kernel Module fuse.
10872 23:00:44.073695 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10873 23:00:44.084825 <3>[ 20.286051] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10874 23:00:44.091704 <30>[ 20.296522] systemd[1]: Finished Load Kernel Modules.
10875 23:00:44.098783 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10876 23:00:44.115308 <30>[ 20.316159] systemd[1]: Finished Remount Root and Kernel File Systems.
10877 23:00:44.121316 <3>[ 20.317343] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10878 23:00:44.131267 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10879 23:00:44.154324 <3>[ 20.355878] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10880 23:00:44.175350 <30>[ 20.379636] systemd[1]: Mounting FUSE Control File System...
10881 23:00:44.182407 Mounting [0;1;39mFUSE Control File System[0m...
10882 23:00:44.192107 <3>[ 20.391797] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10883 23:00:44.204400 <30>[ 20.405917] systemd[1]: Mounting Kernel Configuration File System...
10884 23:00:44.208453 Mounting [0;1;39mKernel Configuration File System[0m...
10885 23:00:44.222867 <3>[ 20.424110] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10886 23:00:44.238077 <30>[ 20.439107] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10887 23:00:44.248184 <30>[ 20.448141] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10888 23:00:44.257733 <3>[ 20.453438] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10889 23:00:44.266922 <30>[ 20.471540] systemd[1]: Starting Load/Save Random Seed...
10890 23:00:44.273630 Starting [0;1;39mLoad/Save Random Seed[0m...
10891 23:00:44.286019 <3>[ 20.487299] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10892 23:00:44.295278 <30>[ 20.499875] systemd[1]: Starting Apply Kernel Variables...
10893 23:00:44.301854 Starting [0;1;39mApply Kernel Variables[0m...
10894 23:00:44.315589 <3>[ 20.516790] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10895 23:00:44.324872 <30>[ 20.529119] systemd[1]: Starting Create System Users...
10896 23:00:44.331361 Starting [0;1;39mCreate System Users[0m...
10897 23:00:44.348532 <30>[ 20.552656] systemd[1]: Mounted FUSE Control File System.
10898 23:00:44.355171 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10899 23:00:44.371353 <30>[ 20.575680] systemd[1]: Mounted Kernel Configuration File System.
10900 23:00:44.377879 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10901 23:00:44.395646 <4>[ 20.590139] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10902 23:00:44.405306 <3>[ 20.605848] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -6
10903 23:00:44.408457 <30>[ 20.606204] systemd[1]: Started Journal Service.
10904 23:00:44.414950 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10905 23:00:44.436736 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10906 23:00:44.450582 See 'systemctl status systemd-udev-trigger.service' for details.
10907 23:00:44.467696 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10908 23:00:44.483467 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10909 23:00:44.503392 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10910 23:00:44.567446 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10911 23:00:44.588742 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10912 23:00:44.629167 <46>[ 20.830159] systemd-journald[295]: Received client request to flush runtime journal.
10913 23:00:44.936500 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10914 23:00:44.954931 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10915 23:00:44.970328 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10916 23:00:45.030281 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10917 23:00:46.005430 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10918 23:00:46.042970 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10919 23:00:46.093048 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10920 23:00:46.151805 Starting [0;1;39mNetwork Service[0m...
10921 23:00:46.469052 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10922 23:00:46.492642 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10923 23:00:46.534365 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10924 23:00:46.704522 <6>[ 22.909394] remoteproc remoteproc0: powering up scp
10925 23:00:46.733895 <4>[ 22.935479] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10926 23:00:46.740841 <3>[ 22.945399] remoteproc remoteproc0: request_firmware failed: -2
10927 23:00:46.750558 <3>[ 22.951716] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
10928 23:00:46.842857 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10929 23:00:46.883900 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10930 23:00:46.898809 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10931 23:00:46.920157 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10932 23:00:46.937652 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10933 23:00:46.986468 Starting [0;1;39mNetwork Name Resolution[0m...
10934 23:00:47.011784 Starting [0;1;39mNetwork Time Synchronization[0m...
10935 23:00:47.029292 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10936 23:00:47.050722 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10937 23:00:47.080969 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10938 23:00:47.112069 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10939 23:00:47.278784 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10940 23:00:47.294613 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10941 23:00:47.313770 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10942 23:00:47.330582 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10943 23:00:47.346192 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10944 23:00:47.480836 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10945 23:00:47.525456 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10946 23:00:47.550138 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10947 23:00:47.578958 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10948 23:00:47.589979 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10949 23:00:47.617332 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10950 23:00:47.630822 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10951 23:00:47.646140 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10952 23:00:47.698815 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10953 23:00:47.731654 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10954 23:00:47.794714 Starting [0;1;39mUser Login Management[0m...
10955 23:00:47.811049 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10956 23:00:47.826982 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10957 23:00:47.845359 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10958 23:00:47.878740 Starting [0;1;39mPermit User Sessions[0m...
10959 23:00:48.020313 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10960 23:00:48.076179 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10961 23:00:48.094975 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10962 23:00:48.112178 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10963 23:00:48.132839 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10964 23:00:48.150058 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10965 23:00:48.169542 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10966 23:00:48.184587 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10967 23:00:48.244804 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10968 23:00:48.288421 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10969 23:00:48.346091
10970 23:00:48.346209
10971 23:00:48.349307 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10972 23:00:48.349396
10973 23:00:48.352451 debian-bullseye-arm64 login: root (automatic login)
10974 23:00:48.352538
10975 23:00:48.352604
10976 23:00:48.707067 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Mon Jun 5 22:41:02 UTC 2023 aarch64
10977 23:00:48.707218
10978 23:00:48.713703 The programs included with the Debian GNU/Linux system are free software;
10979 23:00:48.720363 the exact distribution terms for each program are described in the
10980 23:00:48.723209 individual files in /usr/share/doc/*/copyright.
10981 23:00:48.723292
10982 23:00:48.730227 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10983 23:00:48.733322 permitted by applicable law.
10984 23:00:49.611222 Matched prompt #10: / #
10986 23:00:49.611605 Setting prompt string to ['/ #']
10987 23:00:49.611732 end: 2.2.5.1 login-action (duration 00:00:27) [common]
10989 23:00:49.612067 end: 2.2.5 auto-login-action (duration 00:00:27) [common]
10990 23:00:49.612173 start: 2.2.6 expect-shell-connection (timeout 00:03:19) [common]
10991 23:00:49.612250 Setting prompt string to ['/ #']
10992 23:00:49.612312 Forcing a shell prompt, looking for ['/ #']
10994 23:00:49.662547 / #
10995 23:00:49.662730 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10996 23:00:49.662865 Waiting using forced prompt support (timeout 00:02:30)
10997 23:00:49.667527
10998 23:00:49.667810 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10999 23:00:49.667911 start: 2.2.7 export-device-env (timeout 00:03:19) [common]
11001 23:00:49.768278 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10597701/extract-nfsrootfs-vfhoriyx'
11002 23:00:49.773632 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10597701/extract-nfsrootfs-vfhoriyx'
11004 23:00:49.874210 / # export NFS_SERVER_IP='192.168.201.1'
11005 23:00:49.879409 export NFS_SERVER_IP='192.168.201.1'
11006 23:00:49.879703 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11007 23:00:49.879803 end: 2.2 depthcharge-retry (duration 00:01:41) [common]
11008 23:00:49.879900 end: 2 depthcharge-action (duration 00:01:41) [common]
11009 23:00:49.879993 start: 3 lava-test-retry (timeout 00:07:38) [common]
11010 23:00:49.880093 start: 3.1 lava-test-shell (timeout 00:07:38) [common]
11011 23:00:49.880169 Using namespace: common
11013 23:00:49.980532 / # #
11014 23:00:49.980711 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11015 23:00:49.985665 #
11016 23:00:49.985934 Using /lava-10597701
11018 23:00:50.086228 / # export SHELL=/bin/bash
11019 23:00:50.091886 export SHELL=/bin/bash
11021 23:00:50.192533 / # . /lava-10597701/environment
11022 23:00:50.198077 . /lava-10597701/environment
11024 23:00:50.304193 / # /lava-10597701/bin/lava-test-runner /lava-10597701/0
11025 23:00:50.304377 Test shell timeout: 10s (minimum of the action and connection timeout)
11026 23:00:50.309598 /lava-10597701/bin/lava-test-runner /lava-10597701/0
11027 23:00:50.577783 + export TESTRUN_ID=0_timesync-off
11028 23:00:50.581078 + TESTRUN_ID=0_timesync-off
11029 23:00:50.583980 + cd /lava-10597701/0/tests/0_timesync-off
11030 23:00:50.587378 ++ cat uuid
11031 23:00:50.595391 + UUID=10597701_1.6.2.3.1
11032 23:00:50.595475 + set +x
11033 23:00:50.601984 <LAVA_SIGNAL_STARTRUN 0_timesync-off 10597701_1.6.2.3.1>
11034 23:00:50.602280 Received signal: <STARTRUN> 0_timesync-off 10597701_1.6.2.3.1
11035 23:00:50.602383 Starting test lava.0_timesync-off (10597701_1.6.2.3.1)
11036 23:00:50.602509 Skipping test definition patterns.
11037 23:00:50.605343 + systemctl stop systemd-timesyncd
11038 23:00:50.641679 + set +x
11039 23:00:50.644984 <LAVA_SIGNAL_ENDRUN 0_timesync-off 10597701_1.6.2.3.1>
11040 23:00:50.645261 Received signal: <ENDRUN> 0_timesync-off 10597701_1.6.2.3.1
11041 23:00:50.645378 Ending use of test pattern.
11042 23:00:50.645469 Ending test lava.0_timesync-off (10597701_1.6.2.3.1), duration 0.04
11044 23:00:50.725677 + export TESTRUN_ID=1_kselftest-tpm2
11045 23:00:50.728826 + TESTRUN_ID=1_kselftest-tpm2
11046 23:00:50.735392 + cd /lava-10597701/0/tests/1_kselftest-tpm2
11047 23:00:50.735478 ++ cat uuid
11048 23:00:50.741694 + UUID=10597701_1.6.2.3.5
11049 23:00:50.741779 + set +x
11050 23:00:50.748753 <LAVA_SIGNAL_STARTRUN 1_kselftest-tpm2 10597701_1.6.2.3.5>
11051 23:00:50.749012 Received signal: <STARTRUN> 1_kselftest-tpm2 10597701_1.6.2.3.5
11052 23:00:50.749087 Starting test lava.1_kselftest-tpm2 (10597701_1.6.2.3.5)
11053 23:00:50.749224 Skipping test definition patterns.
11054 23:00:50.751888 + cd ./automated/linux/kselftest/
11055 23:00:50.778252 + ./kselftest.sh -c tpm2 -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1314-g1ab0ac1d7e2e3/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11056 23:00:50.817731 INFO: install_deps skipped
11057 23:00:50.938287 --2023-06-05 23:00:50-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1314-g1ab0ac1d7e2e3/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11058 23:00:50.944764 Resolving storage.kernelci.org (storage.kernelci.org)... 52.250.1.28
11059 23:00:51.101375 Connecting to storage.kernelci.org (storage.kernelci.org)|52.250.1.28|:80... connected.
11060 23:00:51.258554 HTTP request sent, awaiting response... 200 OK
11061 23:00:51.261680 Length: 2703120 (2.6M) [application/octet-stream]
11062 23:00:51.265034 Saving to: 'kselftest.tar.xz'
11063 23:00:51.265109
11064 23:00:51.265173
11065 23:00:51.573892 kselftest.tar.xz 0%[ ] 0 --.-KB/s
11066 23:00:51.888988 kselftest.tar.xz 1%[ ] 47.81K 153KB/s
11067 23:00:52.251638 kselftest.tar.xz 8%[> ] 217.50K 348KB/s
11068 23:00:52.577194 kselftest.tar.xz 30%[=====> ] 804.33K 815KB/s
11069 23:00:52.705642 kselftest.tar.xz 72%[=============> ] 1.88M 1.43MB/s
11070 23:00:52.712311 kselftest.tar.xz 100%[===================>] 2.58M 1.79MB/s in 1.4s
11071 23:00:52.712461
11072 23:00:52.945567 2023-06-05 23:00:52 (1.79 MB/s) - 'kselftest.tar.xz' saved [2703120/2703120]
11073 23:00:52.945719
11074 23:00:58.405354 skiplist:
11075 23:00:58.408464 ========================================
11076 23:00:58.411217 ========================================
11077 23:00:58.459665 tpm2:test_smoke.sh
11078 23:00:58.462192 tpm2:test_space.sh
11079 23:00:58.481247 ============== Tests to run ===============
11080 23:00:58.484325 tpm2:test_smoke.sh
11081 23:00:58.484422 tpm2:test_space.sh
11082 23:00:58.487893 ===========End Tests to run ===============
11083 23:00:58.590403 <12>[ 34.796651] kselftest: Running tests in tpm2
11084 23:00:58.600657 TAP version 13
11085 23:00:58.613546 1..2
11086 23:00:58.647231 # selftests: tpm2: test_smoke.sh
11087 23:00:59.865628 # test_read_partial_overwrite (tpm2_tests.SmokeTest) ... ERROR
11088 23:00:59.868759 # test_read_partial_resp (tpm2_tests.SmokeTest) ... ERROR
11089 23:00:59.875365 # Exception ignored in: <function Client.__del__ at 0xffff94d89d30>
11090 23:00:59.878539 # Traceback (most recent call last):
11091 23:00:59.888997 # File "/lava-10597701/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11092 23:00:59.889093 # if self.tpm:
11093 23:00:59.895334 # AttributeError: 'Client' object has no attribute 'tpm'
11094 23:00:59.898611 # test_seal_with_auth (tpm2_tests.SmokeTest) ... ERROR
11095 23:00:59.905177 # Exception ignored in: <function Client.__del__ at 0xffff94d89d30>
11096 23:00:59.908863 # Traceback (most recent call last):
11097 23:00:59.918587 # File "/lava-10597701/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11098 23:00:59.921800 # if self.tpm:
11099 23:00:59.925148 # AttributeError: 'Client' object has no attribute 'tpm'
11100 23:00:59.931706 # test_seal_with_policy (tpm2_tests.SmokeTest) ... ERROR
11101 23:00:59.937999 # Exception ignored in: <function Client.__del__ at 0xffff94d89d30>
11102 23:00:59.941849 # Traceback (most recent call last):
11103 23:00:59.951332 # File "/lava-10597701/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11104 23:00:59.951424 # if self.tpm:
11105 23:00:59.957905 # AttributeError: 'Client' object has no attribute 'tpm'
11106 23:00:59.961302 # test_seal_with_too_long_auth (tpm2_tests.SmokeTest) ... ERROR
11107 23:00:59.967947 # Exception ignored in: <function Client.__del__ at 0xffff94d89d30>
11108 23:00:59.971173 # Traceback (most recent call last):
11109 23:00:59.981113 # File "/lava-10597701/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11110 23:00:59.984390 # if self.tpm:
11111 23:00:59.988113 # AttributeError: 'Client' object has no attribute 'tpm'
11112 23:00:59.994646 # test_send_two_cmds (tpm2_tests.SmokeTest) ... ERROR
11113 23:00:59.998013 # Exception ignored in: <function Client.__del__ at 0xffff94d89d30>
11114 23:01:00.001182 # Traceback (most recent call last):
11115 23:01:00.011187 # File "/lava-10597701/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11116 23:01:00.014643 # if self.tpm:
11117 23:01:00.017656 # AttributeError: 'Client' object has no attribute 'tpm'
11118 23:01:00.024233 # test_too_short_cmd (tpm2_tests.SmokeTest) ... ERROR
11119 23:01:00.030982 # Exception ignored in: <function Client.__del__ at 0xffff94d89d30>
11120 23:01:00.034170 # Traceback (most recent call last):
11121 23:01:00.044244 # File "/lava-10597701/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11122 23:01:00.044350 # if self.tpm:
11123 23:01:00.051099 # AttributeError: 'Client' object has no attribute 'tpm'
11124 23:01:00.054322 # test_unseal_with_wrong_auth (tpm2_tests.SmokeTest) ... ERROR
11125 23:01:00.060952 # Exception ignored in: <function Client.__del__ at 0xffff94d89d30>
11126 23:01:00.064193 # Traceback (most recent call last):
11127 23:01:00.074049 # File "/lava-10597701/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11128 23:01:00.077345 # if self.tpm:
11129 23:01:00.080624 # AttributeError: 'Client' object has no attribute 'tpm'
11130 23:01:00.087098 # test_unseal_with_wrong_policy (tpm2_tests.SmokeTest) ... ERROR
11131 23:01:00.093805 # Exception ignored in: <function Client.__del__ at 0xffff94d89d30>
11132 23:01:00.097437 # Traceback (most recent call last):
11133 23:01:00.107270 # File "/lava-10597701/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11134 23:01:00.107361 # if self.tpm:
11135 23:01:00.114024 # AttributeError: 'Client' object has no attribute 'tpm'
11136 23:01:00.114112 #
11137 23:01:00.120342 # ======================================================================
11138 23:01:00.123973 # ERROR: test_read_partial_overwrite (tpm2_tests.SmokeTest)
11139 23:01:00.130630 # ----------------------------------------------------------------------
11140 23:01:00.133595 # Traceback (most recent call last):
11141 23:01:00.146398 # File "/lava-10597701/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 16, in setUp
11142 23:01:00.149645 # self.root_key = self.client.create_root_key()
11143 23:01:00.159575 # File "/lava-10597701/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11144 23:01:00.166253 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11145 23:01:00.176305 # File "/lava-10597701/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11146 23:01:00.179540 # raise ProtocolError(cc, rc)
11147 23:01:00.182930 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11148 23:01:00.186220 #
11149 23:01:00.192718 # ======================================================================
11150 23:01:00.195942 # ERROR: test_read_partial_resp (tpm2_tests.SmokeTest)
11151 23:01:00.202527 # ----------------------------------------------------------------------
11152 23:01:00.206006 # Traceback (most recent call last):
11153 23:01:00.215771 # File "/lava-10597701/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11154 23:01:00.218933 # self.client = tpm2.Client()
11155 23:01:00.229110 # File "/lava-10597701/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11156 23:01:00.232144 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11157 23:01:00.238690 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11158 23:01:00.238784 #
11159 23:01:00.245583 # ======================================================================
11160 23:01:00.249108 # ERROR: test_seal_with_auth (tpm2_tests.SmokeTest)
11161 23:01:00.255385 # ----------------------------------------------------------------------
11162 23:01:00.258874 # Traceback (most recent call last):
11163 23:01:00.268693 # File "/lava-10597701/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11164 23:01:00.272196 # self.client = tpm2.Client()
11165 23:01:00.281759 # File "/lava-10597701/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11166 23:01:00.288326 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11167 23:01:00.291676 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11168 23:01:00.291759 #
11169 23:01:00.298617 # ======================================================================
11170 23:01:00.305226 # ERROR: test_seal_with_policy (tpm2_tests.SmokeTest)
11171 23:01:00.311838 # ----------------------------------------------------------------------
11172 23:01:00.314676 # Traceback (most recent call last):
11173 23:01:00.324568 # File "/lava-10597701/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11174 23:01:00.328319 # self.client = tpm2.Client()
11175 23:01:00.338152 # File "/lava-10597701/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11176 23:01:00.341270 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11177 23:01:00.348052 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11178 23:01:00.348151 #
11179 23:01:00.354560 # ======================================================================
11180 23:01:00.357925 # ERROR: test_seal_with_too_long_auth (tpm2_tests.SmokeTest)
11181 23:01:00.364762 # ----------------------------------------------------------------------
11182 23:01:00.367932 # Traceback (most recent call last):
11183 23:01:00.377964 # File "/lava-10597701/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11184 23:01:00.380789 # self.client = tpm2.Client()
11185 23:01:00.391300 # File "/lava-10597701/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11186 23:01:00.397316 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11187 23:01:00.400626 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11188 23:01:00.403852 #
11189 23:01:00.407032 # ======================================================================
11190 23:01:00.414207 # ERROR: test_send_two_cmds (tpm2_tests.SmokeTest)
11191 23:01:00.420544 # ----------------------------------------------------------------------
11192 23:01:00.424060 # Traceback (most recent call last):
11193 23:01:00.433809 # File "/lava-10597701/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11194 23:01:00.436937 # self.client = tpm2.Client()
11195 23:01:00.447204 # File "/lava-10597701/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11196 23:01:00.450194 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11197 23:01:00.456770 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11198 23:01:00.456861 #
11199 23:01:00.463327 # ======================================================================
11200 23:01:00.467395 # ERROR: test_too_short_cmd (tpm2_tests.SmokeTest)
11201 23:01:00.474503 # ----------------------------------------------------------------------
11202 23:01:00.477724 # Traceback (most recent call last):
11203 23:01:00.488842 # File "/lava-10597701/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11204 23:01:00.493351 # self.client = tpm2.Client()
11205 23:01:00.500440 # File "/lava-10597701/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11206 23:01:00.504409 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11207 23:01:00.510427 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11208 23:01:00.510528 #
11209 23:01:00.516886 # ======================================================================
11210 23:01:00.527158 # ERROR: test_unseal_with_wrong_auth (tpm2_tests.SmokeTest)
11211 23:01:00.530173 # ----------------------------------------------------------------------
11212 23:01:00.533396 # Traceback (most recent call last):
11213 23:01:00.543472 # File "/lava-10597701/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11214 23:01:00.546607 # self.client = tpm2.Client()
11215 23:01:00.556832 # File "/lava-10597701/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11216 23:01:00.559914 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11217 23:01:00.566757 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11218 23:01:00.566858 #
11219 23:01:00.573494 # ======================================================================
11220 23:01:00.576775 # ERROR: test_unseal_with_wrong_policy (tpm2_tests.SmokeTest)
11221 23:01:00.583472 # ----------------------------------------------------------------------
11222 23:01:00.586233 # Traceback (most recent call last):
11223 23:01:00.596843 # File "/lava-10597701/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11224 23:01:00.599820 # self.client = tpm2.Client()
11225 23:01:00.609716 # File "/lava-10597701/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11226 23:01:00.616235 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11227 23:01:00.619562 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11228 23:01:00.619695 #
11229 23:01:00.626121 # ----------------------------------------------------------------------
11230 23:01:00.629350 # Ran 9 tests in 0.030s
11231 23:01:00.629464 #
11232 23:01:00.632671 # FAILED (errors=9)
11233 23:01:00.635947 # test_async (tpm2_tests.AsyncTest) ... ok
11234 23:01:00.639430 # test_flush_invalid_context (tpm2_tests.AsyncTest) ... ok
11235 23:01:00.639519 #
11236 23:01:00.645879 # ----------------------------------------------------------------------
11237 23:01:00.649099 # Ran 2 tests in 0.032s
11238 23:01:00.649191 #
11239 23:01:00.649277 # OK
11240 23:01:00.652604 ok 1 selftests: tpm2: test_smoke.sh
11241 23:01:00.655488 # selftests: tpm2: test_space.sh
11242 23:01:00.662262 # test_flush_context (tpm2_tests.SpaceTest) ... ERROR
11243 23:01:00.665314 # test_get_handles (tpm2_tests.SpaceTest) ... ERROR
11244 23:01:00.668921 # test_invalid_cc (tpm2_tests.SpaceTest) ... ERROR
11245 23:01:00.675698 # test_make_two_spaces (tpm2_tests.SpaceTest) ... ERROR
11246 23:01:00.675826 #
11247 23:01:00.682496 # ======================================================================
11248 23:01:00.684995 # ERROR: test_flush_context (tpm2_tests.SpaceTest)
11249 23:01:00.691605 # ----------------------------------------------------------------------
11250 23:01:00.694956 # Traceback (most recent call last):
11251 23:01:00.708285 # File "/lava-10597701/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 261, in test_flush_context
11252 23:01:00.711706 # root1 = space1.create_root_key()
11253 23:01:00.721468 # File "/lava-10597701/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11254 23:01:00.727907 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11255 23:01:00.737936 # File "/lava-10597701/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11256 23:01:00.741226 # raise ProtocolError(cc, rc)
11257 23:01:00.744490 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11258 23:01:00.747821 #
11259 23:01:00.751374 # ======================================================================
11260 23:01:00.757564 # ERROR: test_get_handles (tpm2_tests.SpaceTest)
11261 23:01:00.764301 # ----------------------------------------------------------------------
11262 23:01:00.767519 # Traceback (most recent call last):
11263 23:01:00.777369 # File "/lava-10597701/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 271, in test_get_handles
11264 23:01:00.780655 # space1.create_root_key()
11265 23:01:00.790515 # File "/lava-10597701/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11266 23:01:00.796783 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11267 23:01:00.806844 # File "/lava-10597701/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11268 23:01:00.809898 # raise ProtocolError(cc, rc)
11269 23:01:00.816652 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11270 23:01:00.816755 #
11271 23:01:00.823050 # ======================================================================
11272 23:01:00.826425 # ERROR: test_invalid_cc (tpm2_tests.SpaceTest)
11273 23:01:00.832871 # ----------------------------------------------------------------------
11274 23:01:00.836278 # Traceback (most recent call last):
11275 23:01:00.846443 # File "/lava-10597701/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 290, in test_invalid_cc
11276 23:01:00.849843 # root1 = space1.create_root_key()
11277 23:01:00.859705 # File "/lava-10597701/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11278 23:01:00.866249 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11279 23:01:00.875986 # File "/lava-10597701/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11280 23:01:00.879664 # raise ProtocolError(cc, rc)
11281 23:01:00.886557 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11282 23:01:00.886675 #
11283 23:01:00.892882 # ======================================================================
11284 23:01:00.896195 # ERROR: test_make_two_spaces (tpm2_tests.SpaceTest)
11285 23:01:00.902975 # ----------------------------------------------------------------------
11286 23:01:00.905785 # Traceback (most recent call last):
11287 23:01:00.919400 # File "/lava-10597701/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 247, in test_make_two_spaces
11288 23:01:00.922419 # root1 = space1.create_root_key()
11289 23:01:00.932559 # File "/lava-10597701/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11290 23:01:00.939126 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11291 23:01:00.949144 # File "/lava-10597701/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11292 23:01:00.952428 # raise ProtocolError(cc, rc)
11293 23:01:00.955766 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11294 23:01:00.955847 #
11295 23:01:00.962281 # ----------------------------------------------------------------------
11296 23:01:00.965252 # Ran 4 tests in 0.074s
11297 23:01:00.965381 #
11298 23:01:00.968750 # FAILED (errors=4)
11299 23:01:00.972164 not ok 2 selftests: tpm2: test_space.sh # exit=1
11300 23:01:00.992264 tpm2_test_smoke_sh pass
11301 23:01:00.995608 tpm2_test_space_sh fail
11302 23:01:01.011957 + ../../utils/send-to-lava.sh ./output/result.txt
11303 23:01:01.086322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm2_test_smoke_sh RESULT=pass>
11304 23:01:01.086668 Received signal: <TESTCASE> TEST_CASE_ID=tpm2_test_smoke_sh RESULT=pass
11306 23:01:01.140686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm2_test_space_sh RESULT=fail>
11307 23:01:01.141013 Received signal: <TESTCASE> TEST_CASE_ID=tpm2_test_space_sh RESULT=fail
11309 23:01:01.144089 + set +x
11310 23:01:01.147209 <LAVA_SIGNAL_ENDRUN 1_kselftest-tpm2 10597701_1.6.2.3.5>
11311 23:01:01.147468 Received signal: <ENDRUN> 1_kselftest-tpm2 10597701_1.6.2.3.5
11312 23:01:01.147551 Ending use of test pattern.
11313 23:01:01.147630 Ending test lava.1_kselftest-tpm2 (10597701_1.6.2.3.5), duration 10.40
11315 23:01:01.150500 <LAVA_TEST_RUNNER EXIT>
11316 23:01:01.150757 ok: lava_test_shell seems to have completed
11317 23:01:01.150880 tpm2_test_smoke_sh: pass
tpm2_test_space_sh: fail
11318 23:01:01.150985 end: 3.1 lava-test-shell (duration 00:00:11) [common]
11319 23:01:01.151087 end: 3 lava-test-retry (duration 00:00:11) [common]
11320 23:01:01.151191 start: 4 finalize (timeout 00:07:26) [common]
11321 23:01:01.151299 start: 4.1 power-off (timeout 00:00:30) [common]
11322 23:01:01.151471 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=off'
11323 23:01:01.227009 >> Command sent successfully.
11324 23:01:01.229288 Returned 0 in 0 seconds
11325 23:01:01.329701 end: 4.1 power-off (duration 00:00:00) [common]
11327 23:01:01.330050 start: 4.2 read-feedback (timeout 00:07:26) [common]
11328 23:01:01.330311 Listened to connection for namespace 'common' for up to 1s
11329 23:01:02.331249 Finalising connection for namespace 'common'
11330 23:01:02.331436 Disconnecting from shell: Finalise
11331 23:01:02.331522 / #
11332 23:01:02.431869 end: 4.2 read-feedback (duration 00:00:01) [common]
11333 23:01:02.432115 end: 4 finalize (duration 00:00:01) [common]
11334 23:01:02.432241 Cleaning after the job
11335 23:01:02.432338 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597701/tftp-deploy-gimehd2h/ramdisk
11336 23:01:02.434482 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597701/tftp-deploy-gimehd2h/kernel
11337 23:01:02.442818 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597701/tftp-deploy-gimehd2h/dtb
11338 23:01:02.443079 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597701/tftp-deploy-gimehd2h/nfsrootfs
11339 23:01:02.505082 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597701/tftp-deploy-gimehd2h/modules
11340 23:01:02.510134 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10597701
11341 23:01:03.033915 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10597701
11342 23:01:03.034102 Job finished correctly