Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 132
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 27
1 22:58:11.530660 lava-dispatcher, installed at version: 2023.05.1
2 22:58:11.530910 start: 0 validate
3 22:58:11.531075 Start time: 2023-06-05 22:58:11.531066+00:00 (UTC)
4 22:58:11.531260 Using caching service: 'http://localhost/cache/?uri=%s'
5 22:58:11.531468 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230527.0%2Farm64%2Frootfs.cpio.gz exists
6 22:58:11.818572 Using caching service: 'http://localhost/cache/?uri=%s'
7 22:58:11.818763 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1314-g1ab0ac1d7e2e3%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 22:58:12.108252 Using caching service: 'http://localhost/cache/?uri=%s'
9 22:58:12.108495 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1314-g1ab0ac1d7e2e3%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 22:58:12.390420 Using caching service: 'http://localhost/cache/?uri=%s'
11 22:58:12.390655 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1314-g1ab0ac1d7e2e3%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 22:58:12.674360 validate duration: 1.14
14 22:58:12.674667 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 22:58:12.674790 start: 1.1 download-retry (timeout 00:10:00) [common]
16 22:58:12.674919 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 22:58:12.675110 Not decompressing ramdisk as can be used compressed.
18 22:58:12.675242 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230527.0/arm64/rootfs.cpio.gz
19 22:58:12.675341 saving as /var/lib/lava/dispatcher/tmp/10597696/tftp-deploy-ndc77cb0/ramdisk/rootfs.cpio.gz
20 22:58:12.675438 total size: 84903995 (80MB)
21 22:58:12.676979 progress 0% (0MB)
22 22:58:12.700970 progress 5% (4MB)
23 22:58:12.724745 progress 10% (8MB)
24 22:58:12.748602 progress 15% (12MB)
25 22:58:12.772634 progress 20% (16MB)
26 22:58:12.795795 progress 25% (20MB)
27 22:58:12.818507 progress 30% (24MB)
28 22:58:12.841052 progress 35% (28MB)
29 22:58:12.864129 progress 40% (32MB)
30 22:58:12.887854 progress 45% (36MB)
31 22:58:12.911746 progress 50% (40MB)
32 22:58:12.935691 progress 55% (44MB)
33 22:58:12.959471 progress 60% (48MB)
34 22:58:12.982772 progress 65% (52MB)
35 22:58:13.006162 progress 70% (56MB)
36 22:58:13.029725 progress 75% (60MB)
37 22:58:13.053160 progress 80% (64MB)
38 22:58:13.076852 progress 85% (68MB)
39 22:58:13.099290 progress 90% (72MB)
40 22:58:13.122400 progress 95% (76MB)
41 22:58:13.145651 progress 100% (80MB)
42 22:58:13.145805 80MB downloaded in 0.47s (172.15MB/s)
43 22:58:13.145980 end: 1.1.1 http-download (duration 00:00:00) [common]
45 22:58:13.146357 end: 1.1 download-retry (duration 00:00:00) [common]
46 22:58:13.146477 start: 1.2 download-retry (timeout 00:10:00) [common]
47 22:58:13.146605 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 22:58:13.146799 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1314-g1ab0ac1d7e2e3/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 22:58:13.146903 saving as /var/lib/lava/dispatcher/tmp/10597696/tftp-deploy-ndc77cb0/kernel/Image
50 22:58:13.147008 total size: 45746688 (43MB)
51 22:58:13.147101 No compression specified
52 22:58:13.148352 progress 0% (0MB)
53 22:58:13.161161 progress 5% (2MB)
54 22:58:13.174278 progress 10% (4MB)
55 22:58:13.187202 progress 15% (6MB)
56 22:58:13.200177 progress 20% (8MB)
57 22:58:13.212510 progress 25% (10MB)
58 22:58:13.224813 progress 30% (13MB)
59 22:58:13.237391 progress 35% (15MB)
60 22:58:13.250237 progress 40% (17MB)
61 22:58:13.263164 progress 45% (19MB)
62 22:58:13.276092 progress 50% (21MB)
63 22:58:13.288825 progress 55% (24MB)
64 22:58:13.301672 progress 60% (26MB)
65 22:58:13.313901 progress 65% (28MB)
66 22:58:13.326500 progress 70% (30MB)
67 22:58:13.339307 progress 75% (32MB)
68 22:58:13.351921 progress 80% (34MB)
69 22:58:13.364628 progress 85% (37MB)
70 22:58:13.377102 progress 90% (39MB)
71 22:58:13.389326 progress 95% (41MB)
72 22:58:13.401503 progress 100% (43MB)
73 22:58:13.401644 43MB downloaded in 0.25s (171.34MB/s)
74 22:58:13.401799 end: 1.2.1 http-download (duration 00:00:00) [common]
76 22:58:13.402045 end: 1.2 download-retry (duration 00:00:00) [common]
77 22:58:13.402140 start: 1.3 download-retry (timeout 00:09:59) [common]
78 22:58:13.402258 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 22:58:13.402450 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1314-g1ab0ac1d7e2e3/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 22:58:13.402557 saving as /var/lib/lava/dispatcher/tmp/10597696/tftp-deploy-ndc77cb0/dtb/mt8192-asurada-spherion-r0.dtb
81 22:58:13.402656 total size: 46924 (0MB)
82 22:58:13.402752 No compression specified
83 22:58:13.404137 progress 69% (0MB)
84 22:58:13.404420 progress 100% (0MB)
85 22:58:13.404584 0MB downloaded in 0.00s (23.25MB/s)
86 22:58:13.404710 end: 1.3.1 http-download (duration 00:00:00) [common]
88 22:58:13.404952 end: 1.3 download-retry (duration 00:00:00) [common]
89 22:58:13.405048 start: 1.4 download-retry (timeout 00:09:59) [common]
90 22:58:13.405135 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 22:58:13.405268 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1314-g1ab0ac1d7e2e3/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 22:58:13.405344 saving as /var/lib/lava/dispatcher/tmp/10597696/tftp-deploy-ndc77cb0/modules/modules.tar
93 22:58:13.405410 total size: 8552396 (8MB)
94 22:58:13.405480 Using unxz to decompress xz
95 22:58:13.408972 progress 0% (0MB)
96 22:58:13.431694 progress 5% (0MB)
97 22:58:13.456873 progress 10% (0MB)
98 22:58:13.490416 progress 15% (1MB)
99 22:58:13.518535 progress 20% (1MB)
100 22:58:13.545262 progress 25% (2MB)
101 22:58:13.572213 progress 30% (2MB)
102 22:58:13.600752 progress 35% (2MB)
103 22:58:13.627933 progress 40% (3MB)
104 22:58:13.654485 progress 45% (3MB)
105 22:58:13.681966 progress 50% (4MB)
106 22:58:13.708796 progress 55% (4MB)
107 22:58:13.734906 progress 60% (4MB)
108 22:58:13.761853 progress 65% (5MB)
109 22:58:13.789446 progress 70% (5MB)
110 22:58:13.815745 progress 75% (6MB)
111 22:58:13.843693 progress 80% (6MB)
112 22:58:13.870989 progress 85% (6MB)
113 22:58:13.898247 progress 90% (7MB)
114 22:58:13.923820 progress 95% (7MB)
115 22:58:13.950683 progress 100% (8MB)
116 22:58:13.957762 8MB downloaded in 0.55s (14.77MB/s)
117 22:58:13.958051 end: 1.4.1 http-download (duration 00:00:01) [common]
119 22:58:13.958316 end: 1.4 download-retry (duration 00:00:01) [common]
120 22:58:13.958415 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 22:58:13.958514 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 22:58:13.958599 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 22:58:13.958689 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 22:58:13.958965 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10597696/lava-overlay-2ppg5h7l
125 22:58:13.959166 makedir: /var/lib/lava/dispatcher/tmp/10597696/lava-overlay-2ppg5h7l/lava-10597696/bin
126 22:58:13.959318 makedir: /var/lib/lava/dispatcher/tmp/10597696/lava-overlay-2ppg5h7l/lava-10597696/tests
127 22:58:13.959448 makedir: /var/lib/lava/dispatcher/tmp/10597696/lava-overlay-2ppg5h7l/lava-10597696/results
128 22:58:13.959566 Creating /var/lib/lava/dispatcher/tmp/10597696/lava-overlay-2ppg5h7l/lava-10597696/bin/lava-add-keys
129 22:58:13.959713 Creating /var/lib/lava/dispatcher/tmp/10597696/lava-overlay-2ppg5h7l/lava-10597696/bin/lava-add-sources
130 22:58:13.959845 Creating /var/lib/lava/dispatcher/tmp/10597696/lava-overlay-2ppg5h7l/lava-10597696/bin/lava-background-process-start
131 22:58:13.959976 Creating /var/lib/lava/dispatcher/tmp/10597696/lava-overlay-2ppg5h7l/lava-10597696/bin/lava-background-process-stop
132 22:58:13.960101 Creating /var/lib/lava/dispatcher/tmp/10597696/lava-overlay-2ppg5h7l/lava-10597696/bin/lava-common-functions
133 22:58:13.960238 Creating /var/lib/lava/dispatcher/tmp/10597696/lava-overlay-2ppg5h7l/lava-10597696/bin/lava-echo-ipv4
134 22:58:13.960365 Creating /var/lib/lava/dispatcher/tmp/10597696/lava-overlay-2ppg5h7l/lava-10597696/bin/lava-install-packages
135 22:58:13.960490 Creating /var/lib/lava/dispatcher/tmp/10597696/lava-overlay-2ppg5h7l/lava-10597696/bin/lava-installed-packages
136 22:58:13.960617 Creating /var/lib/lava/dispatcher/tmp/10597696/lava-overlay-2ppg5h7l/lava-10597696/bin/lava-os-build
137 22:58:13.960739 Creating /var/lib/lava/dispatcher/tmp/10597696/lava-overlay-2ppg5h7l/lava-10597696/bin/lava-probe-channel
138 22:58:13.960862 Creating /var/lib/lava/dispatcher/tmp/10597696/lava-overlay-2ppg5h7l/lava-10597696/bin/lava-probe-ip
139 22:58:13.960984 Creating /var/lib/lava/dispatcher/tmp/10597696/lava-overlay-2ppg5h7l/lava-10597696/bin/lava-target-ip
140 22:58:13.961107 Creating /var/lib/lava/dispatcher/tmp/10597696/lava-overlay-2ppg5h7l/lava-10597696/bin/lava-target-mac
141 22:58:13.961229 Creating /var/lib/lava/dispatcher/tmp/10597696/lava-overlay-2ppg5h7l/lava-10597696/bin/lava-target-storage
142 22:58:13.961356 Creating /var/lib/lava/dispatcher/tmp/10597696/lava-overlay-2ppg5h7l/lava-10597696/bin/lava-test-case
143 22:58:13.961480 Creating /var/lib/lava/dispatcher/tmp/10597696/lava-overlay-2ppg5h7l/lava-10597696/bin/lava-test-event
144 22:58:13.961601 Creating /var/lib/lava/dispatcher/tmp/10597696/lava-overlay-2ppg5h7l/lava-10597696/bin/lava-test-feedback
145 22:58:13.961723 Creating /var/lib/lava/dispatcher/tmp/10597696/lava-overlay-2ppg5h7l/lava-10597696/bin/lava-test-raise
146 22:58:13.961846 Creating /var/lib/lava/dispatcher/tmp/10597696/lava-overlay-2ppg5h7l/lava-10597696/bin/lava-test-reference
147 22:58:13.961969 Creating /var/lib/lava/dispatcher/tmp/10597696/lava-overlay-2ppg5h7l/lava-10597696/bin/lava-test-runner
148 22:58:13.962090 Creating /var/lib/lava/dispatcher/tmp/10597696/lava-overlay-2ppg5h7l/lava-10597696/bin/lava-test-set
149 22:58:13.962218 Creating /var/lib/lava/dispatcher/tmp/10597696/lava-overlay-2ppg5h7l/lava-10597696/bin/lava-test-shell
150 22:58:13.962343 Updating /var/lib/lava/dispatcher/tmp/10597696/lava-overlay-2ppg5h7l/lava-10597696/bin/lava-install-packages (oe)
151 22:58:15.193940 Updating /var/lib/lava/dispatcher/tmp/10597696/lava-overlay-2ppg5h7l/lava-10597696/bin/lava-installed-packages (oe)
152 22:58:15.196661 Creating /var/lib/lava/dispatcher/tmp/10597696/lava-overlay-2ppg5h7l/lava-10597696/environment
153 22:58:15.196836 LAVA metadata
154 22:58:15.196948 - LAVA_JOB_ID=10597696
155 22:58:15.197071 - LAVA_DISPATCHER_IP=192.168.201.1
156 22:58:15.197341 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:57) [common]
157 22:58:15.197470 skipped lava-vland-overlay
158 22:58:15.197589 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 22:58:15.197675 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:57) [common]
160 22:58:15.197742 skipped lava-multinode-overlay
161 22:58:15.197838 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 22:58:15.197925 start: 1.5.2.3 test-definition (timeout 00:09:57) [common]
163 22:58:15.198051 Loading test definitions
164 22:58:15.198175 start: 1.5.2.3.1 git-repo-action (timeout 00:09:57) [common]
165 22:58:15.198250 Using /lava-10597696 at stage 0
166 22:58:15.198350 Fetching tests from https://github.com/kernelci/kernelci-core
167 22:58:15.198434 Running '/usr/bin/git clone -b kernelci.org --depth=1 https://github.com/kernelci/kernelci-core /var/lib/lava/dispatcher/tmp/10597696/lava-overlay-2ppg5h7l/lava-10597696/0/tests/0_sleep'
168 22:58:16.131263 Removing '.git' directory in /var/lib/lava/dispatcher/tmp/10597696/lava-overlay-2ppg5h7l/lava-10597696/0/tests/0_sleep
169 22:58:16.132562 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/10597696/lava-overlay-2ppg5h7l/lava-10597696/0/tests/0_sleep/config/lava/sleep/sleep.yaml
170 22:58:16.133119 uuid=10597696_1.5.2.3.1 testdef=None
171 22:58:16.133332 end: 1.5.2.3.1 git-repo-action (duration 00:00:01) [common]
173 22:58:16.133752 start: 1.5.2.3.2 test-overlay (timeout 00:09:57) [common]
174 22:58:16.134575 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
176 22:58:16.134864 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:57) [common]
177 22:58:16.150407 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
179 22:58:16.150693 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:57) [common]
180 22:58:16.151473 runner path: /var/lib/lava/dispatcher/tmp/10597696/lava-overlay-2ppg5h7l/lava-10597696/0/tests/0_sleep test_uuid 10597696_1.5.2.3.1
181 22:58:16.151578 sleep_params='mem freeze'
182 22:58:16.151767 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
184 22:58:16.151980 Creating lava-test-runner.conf files
185 22:58:16.152046 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10597696/lava-overlay-2ppg5h7l/lava-10597696/0 for stage 0
186 22:58:16.152137 - 0_sleep
187 22:58:16.152262 end: 1.5.2.3 test-definition (duration 00:00:01) [common]
188 22:58:16.152368 start: 1.5.2.4 compress-overlay (timeout 00:09:57) [common]
189 22:58:16.275976 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
190 22:58:16.276130 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:56) [common]
191 22:58:16.276231 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
192 22:58:16.276333 end: 1.5.2 lava-overlay (duration 00:00:02) [common]
193 22:58:16.276425 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:56) [common]
194 22:58:19.354236 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:03) [common]
195 22:58:19.354589 start: 1.5.4 extract-modules (timeout 00:09:53) [common]
196 22:58:19.354709 extracting modules file /var/lib/lava/dispatcher/tmp/10597696/tftp-deploy-ndc77cb0/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10597696/extract-overlay-ramdisk-pqp8cfmw/ramdisk
197 22:58:19.578003 end: 1.5.4 extract-modules (duration 00:00:00) [common]
198 22:58:19.578163 start: 1.5.5 apply-overlay-tftp (timeout 00:09:53) [common]
199 22:58:19.578258 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10597696/compress-overlay-ghmv4w4v/overlay-1.5.2.4.tar.gz to ramdisk
200 22:58:19.578331 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10597696/compress-overlay-ghmv4w4v/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10597696/extract-overlay-ramdisk-pqp8cfmw/ramdisk
201 22:58:19.672139 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
202 22:58:19.672298 start: 1.5.6 configure-preseed-file (timeout 00:09:53) [common]
203 22:58:19.672401 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
204 22:58:19.672503 start: 1.5.7 compress-ramdisk (timeout 00:09:53) [common]
205 22:58:19.672590 Building ramdisk /var/lib/lava/dispatcher/tmp/10597696/extract-overlay-ramdisk-pqp8cfmw/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10597696/extract-overlay-ramdisk-pqp8cfmw/ramdisk
206 22:58:21.314415 >> 561596 blocks
207 22:58:31.218024 rename /var/lib/lava/dispatcher/tmp/10597696/extract-overlay-ramdisk-pqp8cfmw/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10597696/tftp-deploy-ndc77cb0/ramdisk/ramdisk.cpio.gz
208 22:58:31.218449 end: 1.5.7 compress-ramdisk (duration 00:00:12) [common]
209 22:58:31.218611 start: 1.5.8 prepare-kernel (timeout 00:09:41) [common]
210 22:58:31.218760 start: 1.5.8.1 prepare-fit (timeout 00:09:41) [common]
211 22:58:31.218875 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10597696/tftp-deploy-ndc77cb0/kernel/Image'
212 22:58:43.204012 Returned 0 in 11 seconds
213 22:58:43.304609 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10597696/tftp-deploy-ndc77cb0/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10597696/tftp-deploy-ndc77cb0/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10597696/tftp-deploy-ndc77cb0/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10597696/tftp-deploy-ndc77cb0/kernel/image.itb
214 22:58:44.515685 output: FIT description: Kernel Image image with one or more FDT blobs
215 22:58:44.516113 output: Created: Mon Jun 5 23:58:44 2023
216 22:58:44.516196 output: Image 0 (kernel-1)
217 22:58:44.516286 output: Description:
218 22:58:44.516351 output: Created: Mon Jun 5 23:58:44 2023
219 22:58:44.516421 output: Type: Kernel Image
220 22:58:44.516485 output: Compression: lzma compressed
221 22:58:44.516545 output: Data Size: 10085945 Bytes = 9849.56 KiB = 9.62 MiB
222 22:58:44.516610 output: Architecture: AArch64
223 22:58:44.516667 output: OS: Linux
224 22:58:44.516724 output: Load Address: 0x00000000
225 22:58:44.516785 output: Entry Point: 0x00000000
226 22:58:44.516852 output: Hash algo: crc32
227 22:58:44.516907 output: Hash value: b2943ff2
228 22:58:44.516961 output: Image 1 (fdt-1)
229 22:58:44.517025 output: Description: mt8192-asurada-spherion-r0
230 22:58:44.517080 output: Created: Mon Jun 5 23:58:44 2023
231 22:58:44.517133 output: Type: Flat Device Tree
232 22:58:44.517200 output: Compression: uncompressed
233 22:58:44.517256 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
234 22:58:44.517310 output: Architecture: AArch64
235 22:58:44.517363 output: Hash algo: crc32
236 22:58:44.517434 output: Hash value: 1df858fa
237 22:58:44.517489 output: Image 2 (ramdisk-1)
238 22:58:44.517542 output: Description: unavailable
239 22:58:44.517596 output: Created: Mon Jun 5 23:58:44 2023
240 22:58:44.517655 output: Type: RAMDisk Image
241 22:58:44.517709 output: Compression: Unknown Compression
242 22:58:44.517762 output: Data Size: 98152934 Bytes = 95852.47 KiB = 93.61 MiB
243 22:58:44.517822 output: Architecture: AArch64
244 22:58:44.517875 output: OS: Linux
245 22:58:44.517931 output: Load Address: unavailable
246 22:58:44.517999 output: Entry Point: unavailable
247 22:58:44.518062 output: Hash algo: crc32
248 22:58:44.518116 output: Hash value: 1bed160a
249 22:58:44.518169 output: Default Configuration: 'conf-1'
250 22:58:44.518242 output: Configuration 0 (conf-1)
251 22:58:44.518334 output: Description: mt8192-asurada-spherion-r0
252 22:58:44.518394 output: Kernel: kernel-1
253 22:58:44.518449 output: Init Ramdisk: ramdisk-1
254 22:58:44.518502 output: FDT: fdt-1
255 22:58:44.518555 output: Loadables: kernel-1
256 22:58:44.518619 output:
257 22:58:44.518816 end: 1.5.8.1 prepare-fit (duration 00:00:13) [common]
258 22:58:44.518961 end: 1.5.8 prepare-kernel (duration 00:00:13) [common]
259 22:58:44.519076 end: 1.5 prepare-tftp-overlay (duration 00:00:31) [common]
260 22:58:44.519173 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:28) [common]
261 22:58:44.519264 No LXC device requested
262 22:58:44.519361 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
263 22:58:44.519486 start: 1.7 deploy-device-env (timeout 00:09:28) [common]
264 22:58:44.519567 end: 1.7 deploy-device-env (duration 00:00:00) [common]
265 22:58:44.519646 Checking files for TFTP limit of 4294967296 bytes.
266 22:58:44.520159 end: 1 tftp-deploy (duration 00:00:32) [common]
267 22:58:44.520308 start: 2 depthcharge-action (timeout 00:05:00) [common]
268 22:58:44.520428 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
269 22:58:44.520559 substitutions:
270 22:58:44.520629 - {DTB}: 10597696/tftp-deploy-ndc77cb0/dtb/mt8192-asurada-spherion-r0.dtb
271 22:58:44.520740 - {INITRD}: 10597696/tftp-deploy-ndc77cb0/ramdisk/ramdisk.cpio.gz
272 22:58:44.520801 - {KERNEL}: 10597696/tftp-deploy-ndc77cb0/kernel/Image
273 22:58:44.520865 - {LAVA_MAC}: None
274 22:58:44.520924 - {PRESEED_CONFIG}: None
275 22:58:44.520980 - {PRESEED_LOCAL}: None
276 22:58:44.521035 - {RAMDISK}: 10597696/tftp-deploy-ndc77cb0/ramdisk/ramdisk.cpio.gz
277 22:58:44.521103 - {ROOT_PART}: None
278 22:58:44.521158 - {ROOT}: None
279 22:58:44.521212 - {SERVER_IP}: 192.168.201.1
280 22:58:44.521294 - {TEE}: None
281 22:58:44.521364 Parsed boot commands:
282 22:58:44.521418 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
283 22:58:44.521600 Parsed boot commands: tftpboot 192.168.201.1 10597696/tftp-deploy-ndc77cb0/kernel/image.itb 10597696/tftp-deploy-ndc77cb0/kernel/cmdline
284 22:58:44.521707 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
285 22:58:44.521797 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
286 22:58:44.521896 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
287 22:58:44.522012 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
288 22:58:44.522092 Not connected, no need to disconnect.
289 22:58:44.522169 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
290 22:58:44.522259 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
291 22:58:44.522363 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-3'
292 22:58:44.525665 Setting prompt string to ['lava-test: # ']
293 22:58:44.526049 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
294 22:58:44.526160 end: 2.2.1 reset-connection (duration 00:00:00) [common]
295 22:58:44.526313 start: 2.2.2 reset-device (timeout 00:05:00) [common]
296 22:58:44.526416 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
297 22:58:44.526623 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=reboot'
298 22:58:49.665675 >> Command sent successfully.
299 22:58:49.668060 Returned 0 in 5 seconds
300 22:58:49.768437 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
302 22:58:49.768805 end: 2.2.2 reset-device (duration 00:00:05) [common]
303 22:58:49.768911 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
304 22:58:49.769003 Setting prompt string to 'Starting depthcharge on Spherion...'
305 22:58:49.769076 Changing prompt to 'Starting depthcharge on Spherion...'
306 22:58:49.769153 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
307 22:58:49.769413 [Enter `^Ec?' for help]
308 22:58:49.943853
309 22:58:49.944024
310 22:58:49.944098 F0: 102B 0000
311 22:58:49.944164
312 22:58:49.944227 F3: 1001 0000 [0200]
313 22:58:49.946943
314 22:58:49.947031 F3: 1001 0000
315 22:58:49.947102
316 22:58:49.947167 F7: 102D 0000
317 22:58:49.947230
318 22:58:49.950785 F1: 0000 0000
319 22:58:49.950872
320 22:58:49.950941 V0: 0000 0000 [0001]
321 22:58:49.951005
322 22:58:49.953842 00: 0007 8000
323 22:58:49.953932
324 22:58:49.954001 01: 0000 0000
325 22:58:49.954067
326 22:58:49.957457 BP: 0C00 0209 [0000]
327 22:58:49.957543
328 22:58:49.957613 G0: 1182 0000
329 22:58:49.957678
330 22:58:49.960462 EC: 0000 0021 [4000]
331 22:58:49.960548
332 22:58:49.960617 S7: 0000 0000 [0000]
333 22:58:49.960681
334 22:58:49.963734 CC: 0000 0000 [0001]
335 22:58:49.963820
336 22:58:49.963889 T0: 0000 0040 [010F]
337 22:58:49.963954
338 22:58:49.967338 Jump to BL
339 22:58:49.967480
340 22:58:49.990500
341 22:58:49.990624
342 22:58:49.990726
343 22:58:49.997864 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
344 22:58:50.000994 ARM64: Exception handlers installed.
345 22:58:50.004806 ARM64: Testing exception
346 22:58:50.008011 ARM64: Done test exception
347 22:58:50.014990 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
348 22:58:50.025239 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
349 22:58:50.032070 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
350 22:58:50.042612 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
351 22:58:50.048702 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
352 22:58:50.055650 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
353 22:58:50.067718 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
354 22:58:50.074359 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
355 22:58:50.093646 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
356 22:58:50.097436 WDT: Last reset was cold boot
357 22:58:50.100546 SPI1(PAD0) initialized at 2873684 Hz
358 22:58:50.103660 SPI5(PAD0) initialized at 992727 Hz
359 22:58:50.107297 VBOOT: Loading verstage.
360 22:58:50.113614 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
361 22:58:50.117414 FMAP: Found "FLASH" version 1.1 at 0x20000.
362 22:58:50.120591 FMAP: base = 0x0 size = 0x800000 #areas = 25
363 22:58:50.123635 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
364 22:58:50.131233 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
365 22:58:50.138035 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
366 22:58:50.148463 read SPI 0x96554 0xa1eb: 4594 us, 9022 KB/s, 72.176 Mbps
367 22:58:50.148556
368 22:58:50.148636
369 22:58:50.158956 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
370 22:58:50.162257 ARM64: Exception handlers installed.
371 22:58:50.165515 ARM64: Testing exception
372 22:58:50.165595 ARM64: Done test exception
373 22:58:50.172026 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
374 22:58:50.175584 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
375 22:58:50.191054 Probing TPM: . done!
376 22:58:50.191174 TPM ready after 0 ms
377 22:58:50.198105 Connected to device vid:did:rid of 1ae0:0028:00
378 22:58:50.204360 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
379 22:58:50.263081 Initialized TPM device CR50 revision 0
380 22:58:50.274977 tlcl_send_startup: Startup return code is 0
381 22:58:50.275081 TPM: setup succeeded
382 22:58:50.286722 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
383 22:58:50.294985 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
384 22:58:50.307481 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
385 22:58:50.317300 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
386 22:58:50.320498 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
387 22:58:50.325043 in-header: 03 07 00 00 08 00 00 00
388 22:58:50.329052 in-data: aa e4 47 04 13 02 00 00
389 22:58:50.331865 Chrome EC: UHEPI supported
390 22:58:50.339389 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
391 22:58:50.343080 in-header: 03 ad 00 00 08 00 00 00
392 22:58:50.346921 in-data: 00 20 20 08 00 00 00 00
393 22:58:50.347023 Phase 1
394 22:58:50.350555 FMAP: area GBB found @ 3f5000 (12032 bytes)
395 22:58:50.354150 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
396 22:58:50.362208 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
397 22:58:50.365513 Recovery requested (1009000e)
398 22:58:50.374220 TPM: Extending digest for VBOOT: boot mode into PCR 0
399 22:58:50.379806 tlcl_extend: response is 0
400 22:58:50.390388 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
401 22:58:50.395882 tlcl_extend: response is 0
402 22:58:50.402900 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
403 22:58:50.422851 read SPI 0x210d4 0x2173b: 15147 us, 9045 KB/s, 72.360 Mbps
404 22:58:50.429772 BS: bootblock times (exec / console): total (unknown) / 148 ms
405 22:58:50.429864
406 22:58:50.429932
407 22:58:50.440598 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
408 22:58:50.444290 ARM64: Exception handlers installed.
409 22:58:50.444378 ARM64: Testing exception
410 22:58:50.447253 ARM64: Done test exception
411 22:58:50.468966 pmic_efuse_setting: Set efuses in 11 msecs
412 22:58:50.472062 pmwrap_interface_init: Select PMIF_VLD_RDY
413 22:58:50.478929 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
414 22:58:50.482039 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
415 22:58:50.489274 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
416 22:58:50.492221 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
417 22:58:50.496108 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
418 22:58:50.502703 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
419 22:58:50.506619 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
420 22:58:50.510161 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
421 22:58:50.517645 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
422 22:58:50.521297 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
423 22:58:50.525089 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
424 22:58:50.528897 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
425 22:58:50.535975 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
426 22:58:50.539806 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
427 22:58:50.547251 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
428 22:58:50.550952 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
429 22:58:50.558403 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
430 22:58:50.562228 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
431 22:58:50.568934 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
432 22:58:50.576861 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
433 22:58:50.580550 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
434 22:58:50.587513 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
435 22:58:50.591462 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
436 22:58:50.598923 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
437 22:58:50.602745 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
438 22:58:50.609994 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
439 22:58:50.613742 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
440 22:58:50.616792 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
441 22:58:50.624643 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
442 22:58:50.628364 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
443 22:58:50.631581 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
444 22:58:50.638974 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
445 22:58:50.642733 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
446 22:58:50.646548 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
447 22:58:50.654120 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
448 22:58:50.657169 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
449 22:58:50.661462 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
450 22:58:50.668252 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
451 22:58:50.672478 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
452 22:58:50.676104 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
453 22:58:50.679577 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
454 22:58:50.686672 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
455 22:58:50.690182 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
456 22:58:50.694441 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
457 22:58:50.697551 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
458 22:58:50.701428 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
459 22:58:50.708624 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
460 22:58:50.712103 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
461 22:58:50.715719 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
462 22:58:50.719790 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
463 22:58:50.723692 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
464 22:58:50.730783 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
465 22:58:50.741981 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
466 22:58:50.745084 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
467 22:58:50.752723 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
468 22:58:50.760120 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
469 22:58:50.766862 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
470 22:58:50.770471 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
471 22:58:50.773983 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
472 22:58:50.782105 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x0
473 22:58:50.785199 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
474 22:58:50.793341 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
475 22:58:50.796396 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
476 22:58:50.805714 [RTC]rtc_get_frequency_meter,154: input=15, output=789
477 22:58:50.815331 [RTC]rtc_get_frequency_meter,154: input=23, output=978
478 22:58:50.825146 [RTC]rtc_get_frequency_meter,154: input=19, output=884
479 22:58:50.834153 [RTC]rtc_get_frequency_meter,154: input=17, output=837
480 22:58:50.844241 [RTC]rtc_get_frequency_meter,154: input=16, output=813
481 22:58:50.852967 [RTC]rtc_get_frequency_meter,154: input=15, output=791
482 22:58:50.863207 [RTC]rtc_get_frequency_meter,154: input=16, output=814
483 22:58:50.866865 [RTC]rtc_eosc_cali,47: left: 15, middle: 15, right: 16
484 22:58:50.873801 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
485 22:58:50.877611 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
486 22:58:50.881307 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
487 22:58:50.884814 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
488 22:58:50.888552 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
489 22:58:50.892353 ADC[4]: Raw value=901697 ID=7
490 22:58:50.895624 ADC[3]: Raw value=213336 ID=1
491 22:58:50.895728 RAM Code: 0x71
492 22:58:50.899468 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
493 22:58:50.906875 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
494 22:58:50.914249 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
495 22:58:50.921523 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
496 22:58:50.925321 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
497 22:58:50.928895 in-header: 03 07 00 00 08 00 00 00
498 22:58:50.932927 in-data: aa e4 47 04 13 02 00 00
499 22:58:50.933061 Chrome EC: UHEPI supported
500 22:58:50.939321 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
501 22:58:50.943088 in-header: 03 ed 00 00 08 00 00 00
502 22:58:50.946916 in-data: 80 20 60 08 00 00 00 00
503 22:58:50.950717 MRC: failed to locate region type 0.
504 22:58:50.958261 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
505 22:58:50.961535 DRAM-K: Running full calibration
506 22:58:50.965384 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
507 22:58:50.969302 header.status = 0x0
508 22:58:50.972409 header.version = 0x6 (expected: 0x6)
509 22:58:50.976085 header.size = 0xd00 (expected: 0xd00)
510 22:58:50.976176 header.flags = 0x0
511 22:58:50.983572 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
512 22:58:51.000764 read SPI 0x72590 0x1c583: 12502 us, 9286 KB/s, 74.288 Mbps
513 22:58:51.008136 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
514 22:58:51.011887 dram_init: ddr_geometry: 2
515 22:58:51.011981 [EMI] MDL number = 2
516 22:58:51.015646 [EMI] Get MDL freq = 0
517 22:58:51.015733 dram_init: ddr_type: 0
518 22:58:51.019421 is_discrete_lpddr4: 1
519 22:58:51.023191 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
520 22:58:51.023304
521 22:58:51.023409
522 22:58:51.023498 [Bian_co] ETT version 0.0.0.1
523 22:58:51.030487 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
524 22:58:51.030606
525 22:58:51.034120 dramc_set_vcore_voltage set vcore to 650000
526 22:58:51.034240 Read voltage for 800, 4
527 22:58:51.038013 Vio18 = 0
528 22:58:51.038152 Vcore = 650000
529 22:58:51.038245 Vdram = 0
530 22:58:51.038339 Vddq = 0
531 22:58:51.041087 Vmddr = 0
532 22:58:51.041205 dram_init: config_dvfs: 1
533 22:58:51.047828 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
534 22:58:51.054675 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
535 22:58:51.057861 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=10
536 22:58:51.061096 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=10
537 22:58:51.064258 [SwImpedanceCal] DRVP=12, DRVN=25, ODTN=9
538 22:58:51.068091 freq_region=1, Reg: DRVP=12, DRVN=25, ODTN=9
539 22:58:51.071065 MEM_TYPE=3, freq_sel=18
540 22:58:51.074731 sv_algorithm_assistance_LP4_1600
541 22:58:51.077752 ============ PULL DRAM RESETB DOWN ============
542 22:58:51.081471 ========== PULL DRAM RESETB DOWN end =========
543 22:58:51.088132 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
544 22:58:51.091368 ===================================
545 22:58:51.091454 LPDDR4 DRAM CONFIGURATION
546 22:58:51.094525 ===================================
547 22:58:51.097745 EX_ROW_EN[0] = 0x0
548 22:58:51.097830 EX_ROW_EN[1] = 0x0
549 22:58:51.101499 LP4Y_EN = 0x0
550 22:58:51.101584 WORK_FSP = 0x0
551 22:58:51.104767 WL = 0x2
552 22:58:51.107973 RL = 0x2
553 22:58:51.108058 BL = 0x2
554 22:58:51.110962 RPST = 0x0
555 22:58:51.111047 RD_PRE = 0x0
556 22:58:51.114730 WR_PRE = 0x1
557 22:58:51.114815 WR_PST = 0x0
558 22:58:51.117822 DBI_WR = 0x0
559 22:58:51.117907 DBI_RD = 0x0
560 22:58:51.121369 OTF = 0x1
561 22:58:51.124673 ===================================
562 22:58:51.127650 ===================================
563 22:58:51.127737 ANA top config
564 22:58:51.131190 ===================================
565 22:58:51.134314 DLL_ASYNC_EN = 0
566 22:58:51.137779 ALL_SLAVE_EN = 1
567 22:58:51.137865 NEW_RANK_MODE = 1
568 22:58:51.140923 DLL_IDLE_MODE = 1
569 22:58:51.144800 LP45_APHY_COMB_EN = 1
570 22:58:51.147689 TX_ODT_DIS = 1
571 22:58:51.147775 NEW_8X_MODE = 1
572 22:58:51.150760 ===================================
573 22:58:51.154013 ===================================
574 22:58:51.157762 data_rate = 1600
575 22:58:51.161117 CKR = 1
576 22:58:51.164088 DQ_P2S_RATIO = 8
577 22:58:51.167947 ===================================
578 22:58:51.171052 CA_P2S_RATIO = 8
579 22:58:51.174333 DQ_CA_OPEN = 0
580 22:58:51.174418 DQ_SEMI_OPEN = 0
581 22:58:51.177922 CA_SEMI_OPEN = 0
582 22:58:51.180993 CA_FULL_RATE = 0
583 22:58:51.184698 DQ_CKDIV4_EN = 1
584 22:58:51.187880 CA_CKDIV4_EN = 1
585 22:58:51.191528 CA_PREDIV_EN = 0
586 22:58:51.191632 PH8_DLY = 0
587 22:58:51.194540 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
588 22:58:51.197533 DQ_AAMCK_DIV = 4
589 22:58:51.201166 CA_AAMCK_DIV = 4
590 22:58:51.204467 CA_ADMCK_DIV = 4
591 22:58:51.207637 DQ_TRACK_CA_EN = 0
592 22:58:51.207723 CA_PICK = 800
593 22:58:51.211365 CA_MCKIO = 800
594 22:58:51.214512 MCKIO_SEMI = 0
595 22:58:51.217605 PLL_FREQ = 3068
596 22:58:51.221704 DQ_UI_PI_RATIO = 32
597 22:58:51.225365 CA_UI_PI_RATIO = 0
598 22:58:51.225475 ===================================
599 22:58:51.229225 ===================================
600 22:58:51.232333 memory_type:LPDDR4
601 22:58:51.235980 GP_NUM : 10
602 22:58:51.236066 SRAM_EN : 1
603 22:58:51.239003 MD32_EN : 0
604 22:58:51.243314 ===================================
605 22:58:51.243442 [ANA_INIT] >>>>>>>>>>>>>>
606 22:58:51.246510 <<<<<< [CONFIGURE PHASE]: ANA_TX
607 22:58:51.250009 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
608 22:58:51.253671 ===================================
609 22:58:51.257388 data_rate = 1600,PCW = 0X7600
610 22:58:51.260587 ===================================
611 22:58:51.263679 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
612 22:58:51.270516 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
613 22:58:51.273740 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
614 22:58:51.280499 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
615 22:58:51.283534 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
616 22:58:51.287233 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
617 22:58:51.287346 [ANA_INIT] flow start
618 22:58:51.290237 [ANA_INIT] PLL >>>>>>>>
619 22:58:51.293989 [ANA_INIT] PLL <<<<<<<<
620 22:58:51.294075 [ANA_INIT] MIDPI >>>>>>>>
621 22:58:51.296963 [ANA_INIT] MIDPI <<<<<<<<
622 22:58:51.300760 [ANA_INIT] DLL >>>>>>>>
623 22:58:51.300846 [ANA_INIT] flow end
624 22:58:51.307427 ============ LP4 DIFF to SE enter ============
625 22:58:51.310678 ============ LP4 DIFF to SE exit ============
626 22:58:51.310764 [ANA_INIT] <<<<<<<<<<<<<
627 22:58:51.313699 [Flow] Enable top DCM control >>>>>
628 22:58:51.317041 [Flow] Enable top DCM control <<<<<
629 22:58:51.320644 Enable DLL master slave shuffle
630 22:58:51.327409 ==============================================================
631 22:58:51.330315 Gating Mode config
632 22:58:51.333968 ==============================================================
633 22:58:51.336991 Config description:
634 22:58:51.346669 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
635 22:58:51.354061 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
636 22:58:51.357042 SELPH_MODE 0: By rank 1: By Phase
637 22:58:51.363670 ==============================================================
638 22:58:51.367579 GAT_TRACK_EN = 1
639 22:58:51.367665 RX_GATING_MODE = 2
640 22:58:51.369976 RX_GATING_TRACK_MODE = 2
641 22:58:51.373748 SELPH_MODE = 1
642 22:58:51.376917 PICG_EARLY_EN = 1
643 22:58:51.380021 VALID_LAT_VALUE = 1
644 22:58:51.386871 ==============================================================
645 22:58:51.390163 Enter into Gating configuration >>>>
646 22:58:51.393751 Exit from Gating configuration <<<<
647 22:58:51.396944 Enter into DVFS_PRE_config >>>>>
648 22:58:51.407085 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
649 22:58:51.410265 Exit from DVFS_PRE_config <<<<<
650 22:58:51.413413 Enter into PICG configuration >>>>
651 22:58:51.417071 Exit from PICG configuration <<<<
652 22:58:51.420286 [RX_INPUT] configuration >>>>>
653 22:58:51.423331 [RX_INPUT] configuration <<<<<
654 22:58:51.426970 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
655 22:58:51.433706 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
656 22:58:51.437882 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
657 22:58:51.444762 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
658 22:58:51.451438 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
659 22:58:51.458308 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
660 22:58:51.461370 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
661 22:58:51.464570 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
662 22:58:51.468255 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
663 22:58:51.474706 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
664 22:58:51.478477 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
665 22:58:51.481605 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
666 22:58:51.484849 ===================================
667 22:58:51.488611 LPDDR4 DRAM CONFIGURATION
668 22:58:51.491666 ===================================
669 22:58:51.494750 EX_ROW_EN[0] = 0x0
670 22:58:51.494853 EX_ROW_EN[1] = 0x0
671 22:58:51.498431 LP4Y_EN = 0x0
672 22:58:51.498525 WORK_FSP = 0x0
673 22:58:51.501702 WL = 0x2
674 22:58:51.501816 RL = 0x2
675 22:58:51.504691 BL = 0x2
676 22:58:51.504808 RPST = 0x0
677 22:58:51.508265 RD_PRE = 0x0
678 22:58:51.508372 WR_PRE = 0x1
679 22:58:51.511888 WR_PST = 0x0
680 22:58:51.512005 DBI_WR = 0x0
681 22:58:51.515210 DBI_RD = 0x0
682 22:58:51.515315 OTF = 0x1
683 22:58:51.518076 ===================================
684 22:58:51.521424 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
685 22:58:51.528078 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
686 22:58:51.531705 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
687 22:58:51.535004 ===================================
688 22:58:51.538243 LPDDR4 DRAM CONFIGURATION
689 22:58:51.541803 ===================================
690 22:58:51.541929 EX_ROW_EN[0] = 0x10
691 22:58:51.544768 EX_ROW_EN[1] = 0x0
692 22:58:51.544875 LP4Y_EN = 0x0
693 22:58:51.548571 WORK_FSP = 0x0
694 22:58:51.548658 WL = 0x2
695 22:58:51.551653 RL = 0x2
696 22:58:51.554624 BL = 0x2
697 22:58:51.554729 RPST = 0x0
698 22:58:51.558305 RD_PRE = 0x0
699 22:58:51.558418 WR_PRE = 0x1
700 22:58:51.561464 WR_PST = 0x0
701 22:58:51.561591 DBI_WR = 0x0
702 22:58:51.565110 DBI_RD = 0x0
703 22:58:51.565238 OTF = 0x1
704 22:58:51.568218 ===================================
705 22:58:51.575183 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
706 22:58:51.578418 nWR fixed to 40
707 22:58:51.582360 [ModeRegInit_LP4] CH0 RK0
708 22:58:51.582445 [ModeRegInit_LP4] CH0 RK1
709 22:58:51.585553 [ModeRegInit_LP4] CH1 RK0
710 22:58:51.588654 [ModeRegInit_LP4] CH1 RK1
711 22:58:51.588741 match AC timing 13
712 22:58:51.595233 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
713 22:58:51.599016 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
714 22:58:51.601986 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
715 22:58:51.608825 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
716 22:58:51.611842 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
717 22:58:51.611927 [EMI DOE] emi_dcm 0
718 22:58:51.618564 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
719 22:58:51.618675 ==
720 22:58:51.622238 Dram Type= 6, Freq= 0, CH_0, rank 0
721 22:58:51.625474 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
722 22:58:51.625594 ==
723 22:58:51.632444 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
724 22:58:51.635327 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
725 22:58:51.646311 [CA 0] Center 37 (7~68) winsize 62
726 22:58:51.649379 [CA 1] Center 37 (6~68) winsize 63
727 22:58:51.653489 [CA 2] Center 35 (5~66) winsize 62
728 22:58:51.656287 [CA 3] Center 34 (4~65) winsize 62
729 22:58:51.659286 [CA 4] Center 34 (3~65) winsize 63
730 22:58:51.663053 [CA 5] Center 33 (3~64) winsize 62
731 22:58:51.663129
732 22:58:51.666369 [CmdBusTrainingLP45] Vref(ca) range 1: 34
733 22:58:51.666456
734 22:58:51.669436 [CATrainingPosCal] consider 1 rank data
735 22:58:51.673119 u2DelayCellTimex100 = 270/100 ps
736 22:58:51.676167 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
737 22:58:51.679383 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
738 22:58:51.686455 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
739 22:58:51.689618 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
740 22:58:51.692785 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
741 22:58:51.695898 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
742 22:58:51.695984
743 22:58:51.699654 CA PerBit enable=1, Macro0, CA PI delay=33
744 22:58:51.699741
745 22:58:51.702919 [CBTSetCACLKResult] CA Dly = 33
746 22:58:51.703005 CS Dly: 5 (0~36)
747 22:58:51.706003 ==
748 22:58:51.706090 Dram Type= 6, Freq= 0, CH_0, rank 1
749 22:58:51.712600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
750 22:58:51.712718 ==
751 22:58:51.716285 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
752 22:58:51.722942 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
753 22:58:51.732384 [CA 0] Center 37 (6~68) winsize 63
754 22:58:51.735470 [CA 1] Center 37 (6~68) winsize 63
755 22:58:51.739115 [CA 2] Center 35 (4~66) winsize 63
756 22:58:51.742590 [CA 3] Center 35 (4~66) winsize 63
757 22:58:51.745651 [CA 4] Center 34 (4~65) winsize 62
758 22:58:51.748864 [CA 5] Center 33 (3~64) winsize 62
759 22:58:51.748957
760 22:58:51.752458 [CmdBusTrainingLP45] Vref(ca) range 1: 34
761 22:58:51.752558
762 22:58:51.755795 [CATrainingPosCal] consider 2 rank data
763 22:58:51.759271 u2DelayCellTimex100 = 270/100 ps
764 22:58:51.762490 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
765 22:58:51.766226 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
766 22:58:51.772431 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
767 22:58:51.775568 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
768 22:58:51.779368 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
769 22:58:51.782432 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
770 22:58:51.782648
771 22:58:51.786247 CA PerBit enable=1, Macro0, CA PI delay=33
772 22:58:51.786513
773 22:58:51.789429 [CBTSetCACLKResult] CA Dly = 33
774 22:58:51.789681 CS Dly: 6 (0~38)
775 22:58:51.789930
776 22:58:51.792602 ----->DramcWriteLeveling(PI) begin...
777 22:58:51.795833 ==
778 22:58:51.799752 Dram Type= 6, Freq= 0, CH_0, rank 0
779 22:58:51.802914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
780 22:58:51.803420 ==
781 22:58:51.806638 Write leveling (Byte 0): 29 => 29
782 22:58:51.807065 Write leveling (Byte 1): 28 => 28
783 22:58:51.810331 DramcWriteLeveling(PI) end<-----
784 22:58:51.810772
785 22:58:51.811142 ==
786 22:58:51.813920 Dram Type= 6, Freq= 0, CH_0, rank 0
787 22:58:51.820813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
788 22:58:51.821256 ==
789 22:58:51.821607 [Gating] SW mode calibration
790 22:58:51.828105 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
791 22:58:51.834883 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
792 22:58:51.837980 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
793 22:58:51.840994 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
794 22:58:51.847687 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
795 22:58:51.851487 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 22:58:51.854411 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 22:58:51.861165 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 22:58:51.864211 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 22:58:51.867975 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 22:58:51.874151 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 22:58:51.877840 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 22:58:51.880960 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 22:58:51.887541 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 22:58:51.891218 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 22:58:51.894637 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 22:58:51.900946 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 22:58:51.904720 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 22:58:51.907800 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 22:58:51.914546 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 22:58:51.917650 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
811 22:58:51.920733 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 22:58:51.927468 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
813 22:58:51.931051 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
814 22:58:51.934102 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
815 22:58:51.937817 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
816 22:58:51.944775 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
817 22:58:51.948003 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
818 22:58:51.950949 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
819 22:58:51.957792 0 9 12 | B1->B0 | 2a2a 3333 | 1 0 | (1 1) (0 0)
820 22:58:51.960920 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
821 22:58:51.964640 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
822 22:58:51.971230 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
823 22:58:51.974313 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
824 22:58:51.977608 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
825 22:58:51.984814 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
826 22:58:51.987940 0 10 8 | B1->B0 | 3333 3030 | 1 0 | (1 0) (0 0)
827 22:58:51.991181 0 10 12 | B1->B0 | 3030 2424 | 0 0 | (1 1) (0 0)
828 22:58:51.997969 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
829 22:58:52.001022 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
830 22:58:52.004736 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
831 22:58:52.010826 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
832 22:58:52.014469 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
833 22:58:52.017575 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
834 22:58:52.024361 0 11 8 | B1->B0 | 2424 2929 | 0 0 | (0 0) (0 0)
835 22:58:52.027930 0 11 12 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
836 22:58:52.030871 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
837 22:58:52.034593 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
838 22:58:52.040989 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
839 22:58:52.044742 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
840 22:58:52.047851 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
841 22:58:52.054717 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
842 22:58:52.057710 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
843 22:58:52.061358 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 22:58:52.068107 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 22:58:52.071292 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 22:58:52.074384 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 22:58:52.081083 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 22:58:52.084941 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 22:58:52.087966 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 22:58:52.094791 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 22:58:52.097956 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
852 22:58:52.101168 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
853 22:58:52.108113 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
854 22:58:52.111393 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
855 22:58:52.115070 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
856 22:58:52.118021 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
857 22:58:52.124941 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
858 22:58:52.128018 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
859 22:58:52.131175 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
860 22:58:52.134715 Total UI for P1: 0, mck2ui 16
861 22:58:52.137711 best dqsien dly found for B0: ( 0, 14, 8)
862 22:58:52.144458 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
863 22:58:52.144546 Total UI for P1: 0, mck2ui 16
864 22:58:52.151210 best dqsien dly found for B1: ( 0, 14, 10)
865 22:58:52.154320 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
866 22:58:52.157948 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
867 22:58:52.158035
868 22:58:52.161060 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
869 22:58:52.164832 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
870 22:58:52.167983 [Gating] SW calibration Done
871 22:58:52.168126 ==
872 22:58:52.171547 Dram Type= 6, Freq= 0, CH_0, rank 0
873 22:58:52.174656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
874 22:58:52.174743 ==
875 22:58:52.177632 RX Vref Scan: 0
876 22:58:52.177720
877 22:58:52.177789 RX Vref 0 -> 0, step: 1
878 22:58:52.177855
879 22:58:52.181271 RX Delay -130 -> 252, step: 16
880 22:58:52.184429 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
881 22:58:52.191284 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
882 22:58:52.194927 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
883 22:58:52.198102 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
884 22:58:52.201265 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
885 22:58:52.204471 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
886 22:58:52.211541 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
887 22:58:52.214659 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
888 22:58:52.218295 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
889 22:58:52.221371 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
890 22:58:52.224482 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
891 22:58:52.231438 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
892 22:58:52.234350 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
893 22:58:52.238035 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
894 22:58:52.241084 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
895 22:58:52.244624 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
896 22:58:52.247750 ==
897 22:58:52.251336 Dram Type= 6, Freq= 0, CH_0, rank 0
898 22:58:52.254647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
899 22:58:52.254754 ==
900 22:58:52.254832 DQS Delay:
901 22:58:52.257789 DQS0 = 0, DQS1 = 0
902 22:58:52.257865 DQM Delay:
903 22:58:52.261026 DQM0 = 86, DQM1 = 78
904 22:58:52.261115 DQ Delay:
905 22:58:52.264756 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
906 22:58:52.267669 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =93
907 22:58:52.271396 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
908 22:58:52.274296 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
909 22:58:52.274400
910 22:58:52.274468
911 22:58:52.274530 ==
912 22:58:52.278078 Dram Type= 6, Freq= 0, CH_0, rank 0
913 22:58:52.281034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
914 22:58:52.281120 ==
915 22:58:52.281193
916 22:58:52.281264
917 22:58:52.284724 TX Vref Scan disable
918 22:58:52.287787 == TX Byte 0 ==
919 22:58:52.290943 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
920 22:58:52.294686 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
921 22:58:52.297745 == TX Byte 1 ==
922 22:58:52.300849 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
923 22:58:52.304712 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
924 22:58:52.304797 ==
925 22:58:52.308029 Dram Type= 6, Freq= 0, CH_0, rank 0
926 22:58:52.311143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
927 22:58:52.314216 ==
928 22:58:52.326013 TX Vref=22, minBit 0, minWin=27, winSum=437
929 22:58:52.329636 TX Vref=24, minBit 5, minWin=27, winSum=443
930 22:58:52.332698 TX Vref=26, minBit 12, minWin=27, winSum=449
931 22:58:52.336423 TX Vref=28, minBit 12, minWin=27, winSum=452
932 22:58:52.339458 TX Vref=30, minBit 2, minWin=28, winSum=454
933 22:58:52.343303 TX Vref=32, minBit 12, minWin=27, winSum=451
934 22:58:52.349467 [TxChooseVref] Worse bit 2, Min win 28, Win sum 454, Final Vref 30
935 22:58:52.349593
936 22:58:52.352939 Final TX Range 1 Vref 30
937 22:58:52.353061
938 22:58:52.353168 ==
939 22:58:52.356261 Dram Type= 6, Freq= 0, CH_0, rank 0
940 22:58:52.359941 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
941 22:58:52.360068 ==
942 22:58:52.360170
943 22:58:52.362997
944 22:58:52.363100 TX Vref Scan disable
945 22:58:52.366276 == TX Byte 0 ==
946 22:58:52.369876 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
947 22:58:52.372841 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
948 22:58:52.376066 == TX Byte 1 ==
949 22:58:52.379599 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
950 22:58:52.382855 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
951 22:58:52.386391
952 22:58:52.386519 [DATLAT]
953 22:58:52.386627 Freq=800, CH0 RK0
954 22:58:52.386725
955 22:58:52.389401 DATLAT Default: 0xa
956 22:58:52.389526 0, 0xFFFF, sum = 0
957 22:58:52.393064 1, 0xFFFF, sum = 0
958 22:58:52.393197 2, 0xFFFF, sum = 0
959 22:58:52.396272 3, 0xFFFF, sum = 0
960 22:58:52.396361 4, 0xFFFF, sum = 0
961 22:58:52.399805 5, 0xFFFF, sum = 0
962 22:58:52.399882 6, 0xFFFF, sum = 0
963 22:58:52.402963 7, 0xFFFF, sum = 0
964 22:58:52.405985 8, 0xFFFF, sum = 0
965 22:58:52.406073 9, 0x0, sum = 1
966 22:58:52.406149 10, 0x0, sum = 2
967 22:58:52.409659 11, 0x0, sum = 3
968 22:58:52.409765 12, 0x0, sum = 4
969 22:58:52.412793 best_step = 10
970 22:58:52.412880
971 22:58:52.412948 ==
972 22:58:52.416588 Dram Type= 6, Freq= 0, CH_0, rank 0
973 22:58:52.419670 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
974 22:58:52.419762 ==
975 22:58:52.422916 RX Vref Scan: 1
976 22:58:52.423000
977 22:58:52.423067 Set Vref Range= 32 -> 127
978 22:58:52.423130
979 22:58:52.426537 RX Vref 32 -> 127, step: 1
980 22:58:52.426622
981 22:58:52.429537 RX Delay -95 -> 252, step: 8
982 22:58:52.429623
983 22:58:52.433406 Set Vref, RX VrefLevel [Byte0]: 32
984 22:58:52.436583 [Byte1]: 32
985 22:58:52.436737
986 22:58:52.439684 Set Vref, RX VrefLevel [Byte0]: 33
987 22:58:52.443475 [Byte1]: 33
988 22:58:52.446376
989 22:58:52.446466 Set Vref, RX VrefLevel [Byte0]: 34
990 22:58:52.449647 [Byte1]: 34
991 22:58:52.453785
992 22:58:52.453874 Set Vref, RX VrefLevel [Byte0]: 35
993 22:58:52.457653 [Byte1]: 35
994 22:58:52.461878
995 22:58:52.461977 Set Vref, RX VrefLevel [Byte0]: 36
996 22:58:52.465215 [Byte1]: 36
997 22:58:52.469555
998 22:58:52.469645 Set Vref, RX VrefLevel [Byte0]: 37
999 22:58:52.473299 [Byte1]: 37
1000 22:58:52.477769
1001 22:58:52.477914 Set Vref, RX VrefLevel [Byte0]: 38
1002 22:58:52.480730 [Byte1]: 38
1003 22:58:52.484987
1004 22:58:52.485131 Set Vref, RX VrefLevel [Byte0]: 39
1005 22:58:52.488271 [Byte1]: 39
1006 22:58:52.492404
1007 22:58:52.492546 Set Vref, RX VrefLevel [Byte0]: 40
1008 22:58:52.496025 [Byte1]: 40
1009 22:58:52.499936
1010 22:58:52.500047 Set Vref, RX VrefLevel [Byte0]: 41
1011 22:58:52.503019 [Byte1]: 41
1012 22:58:52.507265
1013 22:58:52.507406 Set Vref, RX VrefLevel [Byte0]: 42
1014 22:58:52.510429 [Byte1]: 42
1015 22:58:52.515070
1016 22:58:52.515182 Set Vref, RX VrefLevel [Byte0]: 43
1017 22:58:52.518203 [Byte1]: 43
1018 22:58:52.522702
1019 22:58:52.522816 Set Vref, RX VrefLevel [Byte0]: 44
1020 22:58:52.525809 [Byte1]: 44
1021 22:58:52.530142
1022 22:58:52.530256 Set Vref, RX VrefLevel [Byte0]: 45
1023 22:58:52.533213 [Byte1]: 45
1024 22:58:52.537600
1025 22:58:52.537716 Set Vref, RX VrefLevel [Byte0]: 46
1026 22:58:52.540849 [Byte1]: 46
1027 22:58:52.545699
1028 22:58:52.545808 Set Vref, RX VrefLevel [Byte0]: 47
1029 22:58:52.548776 [Byte1]: 47
1030 22:58:52.553087
1031 22:58:52.553166 Set Vref, RX VrefLevel [Byte0]: 48
1032 22:58:52.556205 [Byte1]: 48
1033 22:58:52.560609
1034 22:58:52.560712 Set Vref, RX VrefLevel [Byte0]: 49
1035 22:58:52.563673 [Byte1]: 49
1036 22:58:52.567900
1037 22:58:52.568010 Set Vref, RX VrefLevel [Byte0]: 50
1038 22:58:52.571612 [Byte1]: 50
1039 22:58:52.575453
1040 22:58:52.575539 Set Vref, RX VrefLevel [Byte0]: 51
1041 22:58:52.579247 [Byte1]: 51
1042 22:58:52.583456
1043 22:58:52.583533 Set Vref, RX VrefLevel [Byte0]: 52
1044 22:58:52.586500 [Byte1]: 52
1045 22:58:52.590783
1046 22:58:52.590868 Set Vref, RX VrefLevel [Byte0]: 53
1047 22:58:52.594594 [Byte1]: 53
1048 22:58:52.598143
1049 22:58:52.598229 Set Vref, RX VrefLevel [Byte0]: 54
1050 22:58:52.601891 [Byte1]: 54
1051 22:58:52.606246
1052 22:58:52.606333 Set Vref, RX VrefLevel [Byte0]: 55
1053 22:58:52.609439 [Byte1]: 55
1054 22:58:52.613665
1055 22:58:52.613752 Set Vref, RX VrefLevel [Byte0]: 56
1056 22:58:52.617308 [Byte1]: 56
1057 22:58:52.621212
1058 22:58:52.621296 Set Vref, RX VrefLevel [Byte0]: 57
1059 22:58:52.624292 [Byte1]: 57
1060 22:58:52.628698
1061 22:58:52.628917 Set Vref, RX VrefLevel [Byte0]: 58
1062 22:58:52.631994 [Byte1]: 58
1063 22:58:52.636151
1064 22:58:52.636241 Set Vref, RX VrefLevel [Byte0]: 59
1065 22:58:52.639833 [Byte1]: 59
1066 22:58:52.644334
1067 22:58:52.644425 Set Vref, RX VrefLevel [Byte0]: 60
1068 22:58:52.647138 [Byte1]: 60
1069 22:58:52.651619
1070 22:58:52.651711 Set Vref, RX VrefLevel [Byte0]: 61
1071 22:58:52.655172 [Byte1]: 61
1072 22:58:52.659321
1073 22:58:52.659450 Set Vref, RX VrefLevel [Byte0]: 62
1074 22:58:52.662502 [Byte1]: 62
1075 22:58:52.666757
1076 22:58:52.666866 Set Vref, RX VrefLevel [Byte0]: 63
1077 22:58:52.669960 [Byte1]: 63
1078 22:58:52.674313
1079 22:58:52.674429 Set Vref, RX VrefLevel [Byte0]: 64
1080 22:58:52.677494 [Byte1]: 64
1081 22:58:52.681921
1082 22:58:52.682019 Set Vref, RX VrefLevel [Byte0]: 65
1083 22:58:52.684975 [Byte1]: 65
1084 22:58:52.689296
1085 22:58:52.689376 Set Vref, RX VrefLevel [Byte0]: 66
1086 22:58:52.692986 [Byte1]: 66
1087 22:58:52.697347
1088 22:58:52.697426 Set Vref, RX VrefLevel [Byte0]: 67
1089 22:58:52.700262 [Byte1]: 67
1090 22:58:52.704478
1091 22:58:52.704558 Set Vref, RX VrefLevel [Byte0]: 68
1092 22:58:52.708190 [Byte1]: 68
1093 22:58:52.712072
1094 22:58:52.712207 Set Vref, RX VrefLevel [Byte0]: 69
1095 22:58:52.715751 [Byte1]: 69
1096 22:58:52.720253
1097 22:58:52.720346 Set Vref, RX VrefLevel [Byte0]: 70
1098 22:58:52.723305 [Byte1]: 70
1099 22:58:52.727706
1100 22:58:52.727791 Set Vref, RX VrefLevel [Byte0]: 71
1101 22:58:52.730869 [Byte1]: 71
1102 22:58:52.735233
1103 22:58:52.735316 Set Vref, RX VrefLevel [Byte0]: 72
1104 22:58:52.738572 [Byte1]: 72
1105 22:58:52.742738
1106 22:58:52.742825 Set Vref, RX VrefLevel [Byte0]: 73
1107 22:58:52.745980 [Byte1]: 73
1108 22:58:52.750521
1109 22:58:52.750615 Set Vref, RX VrefLevel [Byte0]: 74
1110 22:58:52.753390 [Byte1]: 74
1111 22:58:52.757697
1112 22:58:52.757813 Set Vref, RX VrefLevel [Byte0]: 75
1113 22:58:52.761233 [Byte1]: 75
1114 22:58:52.765542
1115 22:58:52.765627 Set Vref, RX VrefLevel [Byte0]: 76
1116 22:58:52.768637 [Byte1]: 76
1117 22:58:52.773468
1118 22:58:52.773552 Final RX Vref Byte 0 = 60 to rank0
1119 22:58:52.776578 Final RX Vref Byte 1 = 55 to rank0
1120 22:58:52.779724 Final RX Vref Byte 0 = 60 to rank1
1121 22:58:52.783358 Final RX Vref Byte 1 = 55 to rank1==
1122 22:58:52.786499 Dram Type= 6, Freq= 0, CH_0, rank 0
1123 22:58:52.789589 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1124 22:58:52.793221 ==
1125 22:58:52.793347 DQS Delay:
1126 22:58:52.793468 DQS0 = 0, DQS1 = 0
1127 22:58:52.796281 DQM Delay:
1128 22:58:52.796364 DQM0 = 87, DQM1 = 79
1129 22:58:52.799597 DQ Delay:
1130 22:58:52.803221 DQ0 =88, DQ1 =92, DQ2 =84, DQ3 =84
1131 22:58:52.803330 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =92
1132 22:58:52.806850 DQ8 =68, DQ9 =64, DQ10 =84, DQ11 =76
1133 22:58:52.809892 DQ12 =84, DQ13 =80, DQ14 =92, DQ15 =88
1134 22:58:52.809980
1135 22:58:52.813049
1136 22:58:52.819812 [DQSOSCAuto] RK0, (LSB)MR18= 0x230a, (MSB)MR19= 0x606, tDQSOscB0 = 407 ps tDQSOscB1 = 401 ps
1137 22:58:52.823551 CH0 RK0: MR19=606, MR18=230A
1138 22:58:52.829882 CH0_RK0: MR19=0x606, MR18=0x230A, DQSOSC=401, MR23=63, INC=91, DEC=61
1139 22:58:52.829998
1140 22:58:52.833062 ----->DramcWriteLeveling(PI) begin...
1141 22:58:52.833166 ==
1142 22:58:52.836755 Dram Type= 6, Freq= 0, CH_0, rank 1
1143 22:58:52.839904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1144 22:58:52.840010 ==
1145 22:58:52.843153 Write leveling (Byte 0): 33 => 33
1146 22:58:52.846295 Write leveling (Byte 1): 30 => 30
1147 22:58:52.849849 DramcWriteLeveling(PI) end<-----
1148 22:58:52.849954
1149 22:58:52.850050 ==
1150 22:58:52.852973 Dram Type= 6, Freq= 0, CH_0, rank 1
1151 22:58:52.856760 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1152 22:58:52.856864 ==
1153 22:58:52.859963 [Gating] SW mode calibration
1154 22:58:52.866513 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1155 22:58:52.872695 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1156 22:58:52.876302 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1157 22:58:52.879433 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1158 22:58:52.923998 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1159 22:58:52.924363 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 22:58:52.924472 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 22:58:52.925039 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 22:58:52.925138 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 22:58:52.925819 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 22:58:52.926097 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 22:58:52.926191 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 22:58:52.926299 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 22:58:52.926394 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 22:58:52.967790 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 22:58:52.968198 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 22:58:52.968324 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 22:58:52.968482 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 22:58:52.968594 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1173 22:58:52.968717 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1174 22:58:52.968900 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1175 22:58:52.969604 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 22:58:52.969884 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 22:58:52.969982 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 22:58:52.994273 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 22:58:52.994806 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 22:58:52.995421 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 22:58:52.995704 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 22:58:52.995802 0 9 8 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
1183 22:58:52.998752 0 9 12 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
1184 22:58:53.001837 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1185 22:58:53.004796 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1186 22:58:53.008493 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1187 22:58:53.011605 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1188 22:58:53.018303 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1189 22:58:53.021998 0 10 4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
1190 22:58:53.024842 0 10 8 | B1->B0 | 3131 2929 | 1 0 | (1 0) (0 0)
1191 22:58:53.031723 0 10 12 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
1192 22:58:53.034898 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 22:58:53.038676 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 22:58:53.041751 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 22:58:53.048820 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 22:58:53.052557 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1197 22:58:53.056173 0 11 4 | B1->B0 | 2323 2727 | 0 1 | (0 0) (0 0)
1198 22:58:53.059772 0 11 8 | B1->B0 | 2c2c 3e3e | 0 0 | (0 0) (0 0)
1199 22:58:53.066781 0 11 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
1200 22:58:53.070443 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1201 22:58:53.073617 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1202 22:58:53.077267 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1203 22:58:53.084082 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1204 22:58:53.087673 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1205 22:58:53.090749 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1206 22:58:53.097686 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1207 22:58:53.100775 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 22:58:53.104588 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 22:58:53.111159 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 22:58:53.114271 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 22:58:53.117858 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 22:58:53.120868 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 22:58:53.127853 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 22:58:53.130747 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 22:58:53.133939 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 22:58:53.140952 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 22:58:53.144023 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 22:58:53.147979 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 22:58:53.154084 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 22:58:53.157914 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1221 22:58:53.161049 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1222 22:58:53.167324 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1223 22:58:53.167446 Total UI for P1: 0, mck2ui 16
1224 22:58:53.174174 best dqsien dly found for B0: ( 0, 14, 4)
1225 22:58:53.177375 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1226 22:58:53.180963 Total UI for P1: 0, mck2ui 16
1227 22:58:53.184219 best dqsien dly found for B1: ( 0, 14, 8)
1228 22:58:53.187444 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1229 22:58:53.190715 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1230 22:58:53.190818
1231 22:58:53.193927 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1232 22:58:53.197712 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1233 22:58:53.200754 [Gating] SW calibration Done
1234 22:58:53.200845 ==
1235 22:58:53.204463 Dram Type= 6, Freq= 0, CH_0, rank 1
1236 22:58:53.207523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1237 22:58:53.207610 ==
1238 22:58:53.210654 RX Vref Scan: 0
1239 22:58:53.210738
1240 22:58:53.213878 RX Vref 0 -> 0, step: 1
1241 22:58:53.213964
1242 22:58:53.214032 RX Delay -130 -> 252, step: 16
1243 22:58:53.221178 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1244 22:58:53.224174 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1245 22:58:53.227844 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1246 22:58:53.230958 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1247 22:58:53.234038 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1248 22:58:53.241023 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1249 22:58:53.244211 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1250 22:58:53.247444 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1251 22:58:53.251141 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1252 22:58:53.254229 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1253 22:58:53.260545 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1254 22:58:53.264376 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1255 22:58:53.267270 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1256 22:58:53.271053 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1257 22:58:53.277668 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1258 22:58:53.280797 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1259 22:58:53.280897 ==
1260 22:58:53.283953 Dram Type= 6, Freq= 0, CH_0, rank 1
1261 22:58:53.287598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1262 22:58:53.287715 ==
1263 22:58:53.287811 DQS Delay:
1264 22:58:53.290810 DQS0 = 0, DQS1 = 0
1265 22:58:53.290923 DQM Delay:
1266 22:58:53.294360 DQM0 = 87, DQM1 = 77
1267 22:58:53.294445 DQ Delay:
1268 22:58:53.297346 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
1269 22:58:53.300968 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =101
1270 22:58:53.304093 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1271 22:58:53.307296 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
1272 22:58:53.307432
1273 22:58:53.307529
1274 22:58:53.307604 ==
1275 22:58:53.310945 Dram Type= 6, Freq= 0, CH_0, rank 1
1276 22:58:53.314067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1277 22:58:53.317657 ==
1278 22:58:53.317758
1279 22:58:53.317868
1280 22:58:53.317990 TX Vref Scan disable
1281 22:58:53.320772 == TX Byte 0 ==
1282 22:58:53.324532 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1283 22:58:53.327432 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1284 22:58:53.331070 == TX Byte 1 ==
1285 22:58:53.334178 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1286 22:58:53.337190 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1287 22:58:53.340917 ==
1288 22:58:53.341025 Dram Type= 6, Freq= 0, CH_0, rank 1
1289 22:58:53.347275 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1290 22:58:53.347407 ==
1291 22:58:53.360241 TX Vref=22, minBit 8, minWin=27, winSum=443
1292 22:58:53.363385 TX Vref=24, minBit 8, minWin=27, winSum=449
1293 22:58:53.366570 TX Vref=26, minBit 8, minWin=27, winSum=448
1294 22:58:53.369681 TX Vref=28, minBit 12, minWin=27, winSum=453
1295 22:58:53.372995 TX Vref=30, minBit 9, minWin=27, winSum=450
1296 22:58:53.380241 TX Vref=32, minBit 1, minWin=28, winSum=457
1297 22:58:53.383362 [TxChooseVref] Worse bit 1, Min win 28, Win sum 457, Final Vref 32
1298 22:58:53.383459
1299 22:58:53.386349 Final TX Range 1 Vref 32
1300 22:58:53.386456
1301 22:58:53.386571 ==
1302 22:58:53.389796 Dram Type= 6, Freq= 0, CH_0, rank 1
1303 22:58:53.393045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1304 22:58:53.393171 ==
1305 22:58:53.396716
1306 22:58:53.396826
1307 22:58:53.396944 TX Vref Scan disable
1308 22:58:53.399829 == TX Byte 0 ==
1309 22:58:53.403466 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1310 22:58:53.409665 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1311 22:58:53.409794 == TX Byte 1 ==
1312 22:58:53.413432 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1313 22:58:53.420144 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1314 22:58:53.420265
1315 22:58:53.420419 [DATLAT]
1316 22:58:53.420561 Freq=800, CH0 RK1
1317 22:58:53.420664
1318 22:58:53.423145 DATLAT Default: 0xa
1319 22:58:53.423255 0, 0xFFFF, sum = 0
1320 22:58:53.426273 1, 0xFFFF, sum = 0
1321 22:58:53.426387 2, 0xFFFF, sum = 0
1322 22:58:53.429796 3, 0xFFFF, sum = 0
1323 22:58:53.429928 4, 0xFFFF, sum = 0
1324 22:58:53.433272 5, 0xFFFF, sum = 0
1325 22:58:53.436434 6, 0xFFFF, sum = 0
1326 22:58:53.436546 7, 0xFFFF, sum = 0
1327 22:58:53.440051 8, 0xFFFF, sum = 0
1328 22:58:53.440166 9, 0x0, sum = 1
1329 22:58:53.440270 10, 0x0, sum = 2
1330 22:58:53.442943 11, 0x0, sum = 3
1331 22:58:53.443053 12, 0x0, sum = 4
1332 22:58:53.446791 best_step = 10
1333 22:58:53.446899
1334 22:58:53.447004 ==
1335 22:58:53.450048 Dram Type= 6, Freq= 0, CH_0, rank 1
1336 22:58:53.453091 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1337 22:58:53.453184 ==
1338 22:58:53.456869 RX Vref Scan: 0
1339 22:58:53.456948
1340 22:58:53.457017 RX Vref 0 -> 0, step: 1
1341 22:58:53.457083
1342 22:58:53.460065 RX Delay -95 -> 252, step: 8
1343 22:58:53.466920 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1344 22:58:53.470182 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1345 22:58:53.473146 iDelay=209, Bit 2, Center 84 (-31 ~ 200) 232
1346 22:58:53.476520 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1347 22:58:53.480190 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1348 22:58:53.486981 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1349 22:58:53.489997 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1350 22:58:53.493146 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1351 22:58:53.496825 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1352 22:58:53.499882 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1353 22:58:53.506658 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1354 22:58:53.509782 iDelay=209, Bit 11, Center 68 (-39 ~ 176) 216
1355 22:58:53.513718 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1356 22:58:53.516784 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1357 22:58:53.519757 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1358 22:58:53.526620 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1359 22:58:53.526715 ==
1360 22:58:53.529717 Dram Type= 6, Freq= 0, CH_0, rank 1
1361 22:58:53.533265 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1362 22:58:53.533365 ==
1363 22:58:53.533434 DQS Delay:
1364 22:58:53.536870 DQS0 = 0, DQS1 = 0
1365 22:58:53.536982 DQM Delay:
1366 22:58:53.540127 DQM0 = 87, DQM1 = 77
1367 22:58:53.540239 DQ Delay:
1368 22:58:53.543186 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1369 22:58:53.546662 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1370 22:58:53.549937 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1371 22:58:53.553709 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =88
1372 22:58:53.553838
1373 22:58:53.553938
1374 22:58:53.563200 [DQSOSCAuto] RK1, (LSB)MR18= 0x341d, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 396 ps
1375 22:58:53.563324 CH0 RK1: MR19=606, MR18=341D
1376 22:58:53.569583 CH0_RK1: MR19=0x606, MR18=0x341D, DQSOSC=396, MR23=63, INC=94, DEC=62
1377 22:58:53.573342 [RxdqsGatingPostProcess] freq 800
1378 22:58:53.580064 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1379 22:58:53.582982 Pre-setting of DQS Precalculation
1380 22:58:53.586399 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1381 22:58:53.586492 ==
1382 22:58:53.589950 Dram Type= 6, Freq= 0, CH_1, rank 0
1383 22:58:53.593167 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1384 22:58:53.593254 ==
1385 22:58:53.599772 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1386 22:58:53.606501 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1387 22:58:53.615254 [CA 0] Center 36 (6~67) winsize 62
1388 22:58:53.618340 [CA 1] Center 36 (6~67) winsize 62
1389 22:58:53.621364 [CA 2] Center 34 (4~64) winsize 61
1390 22:58:53.625077 [CA 3] Center 33 (3~64) winsize 62
1391 22:58:53.628337 [CA 4] Center 34 (3~65) winsize 63
1392 22:58:53.631434 [CA 5] Center 33 (3~64) winsize 62
1393 22:58:53.631563
1394 22:58:53.635174 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1395 22:58:53.635303
1396 22:58:53.638274 [CATrainingPosCal] consider 1 rank data
1397 22:58:53.641921 u2DelayCellTimex100 = 270/100 ps
1398 22:58:53.644968 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1399 22:58:53.648696 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1400 22:58:53.651628 CA2 delay=34 (4~64),Diff = 1 PI (7 cell)
1401 22:58:53.658618 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1402 22:58:53.661765 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
1403 22:58:53.664930 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1404 22:58:53.665016
1405 22:58:53.668806 CA PerBit enable=1, Macro0, CA PI delay=33
1406 22:58:53.668922
1407 22:58:53.671853 [CBTSetCACLKResult] CA Dly = 33
1408 22:58:53.671943 CS Dly: 4 (0~35)
1409 22:58:53.672013 ==
1410 22:58:53.674999 Dram Type= 6, Freq= 0, CH_1, rank 1
1411 22:58:53.681467 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1412 22:58:53.681559 ==
1413 22:58:53.685063 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1414 22:58:53.691835 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1415 22:58:53.701315 [CA 0] Center 36 (5~67) winsize 63
1416 22:58:53.704249 [CA 1] Center 36 (6~67) winsize 62
1417 22:58:53.707725 [CA 2] Center 33 (3~64) winsize 62
1418 22:58:53.710908 [CA 3] Center 33 (3~64) winsize 62
1419 22:58:53.714649 [CA 4] Center 33 (3~64) winsize 62
1420 22:58:53.718180 [CA 5] Center 33 (3~64) winsize 62
1421 22:58:53.718316
1422 22:58:53.722175 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1423 22:58:53.722312
1424 22:58:53.725920 [CATrainingPosCal] consider 2 rank data
1425 22:58:53.729575 u2DelayCellTimex100 = 270/100 ps
1426 22:58:53.733288 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1427 22:58:53.736346 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1428 22:58:53.740027 CA2 delay=34 (4~64),Diff = 1 PI (7 cell)
1429 22:58:53.743748 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1430 22:58:53.747492 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1431 22:58:53.750629 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1432 22:58:53.750740
1433 22:58:53.754154 CA PerBit enable=1, Macro0, CA PI delay=33
1434 22:58:53.754280
1435 22:58:53.757388 [CBTSetCACLKResult] CA Dly = 33
1436 22:58:53.757506 CS Dly: 5 (0~37)
1437 22:58:53.760425
1438 22:58:53.763634 ----->DramcWriteLeveling(PI) begin...
1439 22:58:53.763744 ==
1440 22:58:53.767365 Dram Type= 6, Freq= 0, CH_1, rank 0
1441 22:58:53.770405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1442 22:58:53.770509 ==
1443 22:58:53.773678 Write leveling (Byte 0): 26 => 26
1444 22:58:53.777503 Write leveling (Byte 1): 32 => 32
1445 22:58:53.780676 DramcWriteLeveling(PI) end<-----
1446 22:58:53.780781
1447 22:58:53.780876 ==
1448 22:58:53.783915 Dram Type= 6, Freq= 0, CH_1, rank 0
1449 22:58:53.787502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1450 22:58:53.787611 ==
1451 22:58:53.790306 [Gating] SW mode calibration
1452 22:58:53.797238 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1453 22:58:53.804238 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1454 22:58:53.807101 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1455 22:58:53.810234 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1456 22:58:53.813892 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 22:58:53.820542 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 22:58:53.823687 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 22:58:53.827494 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 22:58:53.833679 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 22:58:53.837329 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 22:58:53.840465 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 22:58:53.846989 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 22:58:53.850683 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 22:58:53.853842 0 7 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1466 22:58:53.860428 0 7 16 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1467 22:58:53.864072 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 22:58:53.867413 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 22:58:53.873636 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 22:58:53.877399 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 22:58:53.880354 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1472 22:58:53.887249 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1473 22:58:53.890413 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 22:58:53.894074 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 22:58:53.900376 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 22:58:53.903464 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 22:58:53.907222 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 22:58:53.913568 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 22:58:53.917035 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 22:58:53.920163 0 9 8 | B1->B0 | 2c2c 2e2e | 0 1 | (0 0) (1 1)
1481 22:58:53.926817 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1482 22:58:53.930585 0 9 16 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1483 22:58:53.933715 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1484 22:58:53.936810 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1485 22:58:53.943633 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1486 22:58:53.947273 0 10 0 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1487 22:58:53.950169 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (0 0) (1 1)
1488 22:58:53.956940 0 10 8 | B1->B0 | 2b2b 2929 | 0 1 | (1 0) (1 0)
1489 22:58:53.960613 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 22:58:53.963892 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 22:58:53.970513 0 10 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1492 22:58:53.973623 0 10 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1493 22:58:53.976897 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 22:58:53.983852 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1495 22:58:53.987015 0 11 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1496 22:58:53.990103 0 11 8 | B1->B0 | 3636 3636 | 0 0 | (0 0) (0 0)
1497 22:58:53.997028 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 22:58:54.000668 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1499 22:58:54.003702 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1500 22:58:54.010632 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1501 22:58:54.013775 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1502 22:58:54.016803 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1503 22:58:54.023415 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1504 22:58:54.027290 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1505 22:58:54.030183 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 22:58:54.033949 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 22:58:54.040210 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 22:58:54.043967 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 22:58:54.047080 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 22:58:54.053783 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 22:58:54.057334 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 22:58:54.060609 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 22:58:54.066775 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 22:58:54.070360 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 22:58:54.073509 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 22:58:54.080573 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 22:58:54.083726 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1518 22:58:54.086837 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1519 22:58:54.093810 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1520 22:58:54.096910 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1521 22:58:54.100490 Total UI for P1: 0, mck2ui 16
1522 22:58:54.103576 best dqsien dly found for B0: ( 0, 14, 6)
1523 22:58:54.107306 Total UI for P1: 0, mck2ui 16
1524 22:58:54.110453 best dqsien dly found for B1: ( 0, 14, 4)
1525 22:58:54.114027 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1526 22:58:54.117248 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1527 22:58:54.117362
1528 22:58:54.120392 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1529 22:58:54.124189 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1530 22:58:54.127092 [Gating] SW calibration Done
1531 22:58:54.127218 ==
1532 22:58:54.130149 Dram Type= 6, Freq= 0, CH_1, rank 0
1533 22:58:54.133792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1534 22:58:54.133909 ==
1535 22:58:54.136894 RX Vref Scan: 0
1536 22:58:54.137008
1537 22:58:54.137105 RX Vref 0 -> 0, step: 1
1538 22:58:54.140734
1539 22:58:54.140844 RX Delay -130 -> 252, step: 16
1540 22:58:54.146946 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1541 22:58:54.150663 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1542 22:58:54.153651 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1543 22:58:54.157274 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1544 22:58:54.160311 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1545 22:58:54.167016 iDelay=206, Bit 5, Center 85 (-34 ~ 205) 240
1546 22:58:54.170251 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1547 22:58:54.173744 iDelay=206, Bit 7, Center 77 (-50 ~ 205) 256
1548 22:58:54.177387 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
1549 22:58:54.180536 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1550 22:58:54.186899 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1551 22:58:54.190604 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1552 22:58:54.193739 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1553 22:58:54.197040 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1554 22:58:54.200147 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1555 22:58:54.206963 iDelay=206, Bit 15, Center 77 (-50 ~ 205) 256
1556 22:58:54.207079 ==
1557 22:58:54.210182 Dram Type= 6, Freq= 0, CH_1, rank 0
1558 22:58:54.213500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1559 22:58:54.213634 ==
1560 22:58:54.213740 DQS Delay:
1561 22:58:54.217192 DQS0 = 0, DQS1 = 0
1562 22:58:54.217316 DQM Delay:
1563 22:58:54.220188 DQM0 = 81, DQM1 = 74
1564 22:58:54.220307 DQ Delay:
1565 22:58:54.223903 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =85
1566 22:58:54.227144 DQ4 =85, DQ5 =85, DQ6 =93, DQ7 =77
1567 22:58:54.230701 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
1568 22:58:54.233731 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =77
1569 22:58:54.233852
1570 22:58:54.233950
1571 22:58:54.234048 ==
1572 22:58:54.237327 Dram Type= 6, Freq= 0, CH_1, rank 0
1573 22:58:54.240523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1574 22:58:54.240634 ==
1575 22:58:54.240730
1576 22:58:54.240825
1577 22:58:54.243718 TX Vref Scan disable
1578 22:58:54.246767 == TX Byte 0 ==
1579 22:58:54.250478 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1580 22:58:54.253495 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1581 22:58:54.257176 == TX Byte 1 ==
1582 22:58:54.260364 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1583 22:58:54.263993 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1584 22:58:54.264126 ==
1585 22:58:54.266882 Dram Type= 6, Freq= 0, CH_1, rank 0
1586 22:58:54.273643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1587 22:58:54.273766 ==
1588 22:58:54.285790 TX Vref=22, minBit 8, minWin=26, winSum=435
1589 22:58:54.289000 TX Vref=24, minBit 8, minWin=26, winSum=437
1590 22:58:54.292732 TX Vref=26, minBit 0, minWin=27, winSum=442
1591 22:58:54.296017 TX Vref=28, minBit 10, minWin=27, winSum=449
1592 22:58:54.299748 TX Vref=30, minBit 1, minWin=28, winSum=456
1593 22:58:54.303020 TX Vref=32, minBit 0, minWin=28, winSum=452
1594 22:58:54.309821 [TxChooseVref] Worse bit 1, Min win 28, Win sum 456, Final Vref 30
1595 22:58:54.309914
1596 22:58:54.312905 Final TX Range 1 Vref 30
1597 22:58:54.312993
1598 22:58:54.313064 ==
1599 22:58:54.316653 Dram Type= 6, Freq= 0, CH_1, rank 0
1600 22:58:54.319771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1601 22:58:54.319867 ==
1602 22:58:54.319956
1603 22:58:54.320039
1604 22:58:54.322751 TX Vref Scan disable
1605 22:58:54.326456 == TX Byte 0 ==
1606 22:58:54.329674 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1607 22:58:54.333257 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1608 22:58:54.336334 == TX Byte 1 ==
1609 22:58:54.339993 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1610 22:58:54.343028 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1611 22:58:54.343112
1612 22:58:54.346267 [DATLAT]
1613 22:58:54.346347 Freq=800, CH1 RK0
1614 22:58:54.346430
1615 22:58:54.350063 DATLAT Default: 0xa
1616 22:58:54.350152 0, 0xFFFF, sum = 0
1617 22:58:54.353168 1, 0xFFFF, sum = 0
1618 22:58:54.353257 2, 0xFFFF, sum = 0
1619 22:58:54.356909 3, 0xFFFF, sum = 0
1620 22:58:54.357042 4, 0xFFFF, sum = 0
1621 22:58:54.359867 5, 0xFFFF, sum = 0
1622 22:58:54.360006 6, 0xFFFF, sum = 0
1623 22:58:54.362915 7, 0xFFFF, sum = 0
1624 22:58:54.363041 8, 0xFFFF, sum = 0
1625 22:58:54.366781 9, 0x0, sum = 1
1626 22:58:54.366941 10, 0x0, sum = 2
1627 22:58:54.369820 11, 0x0, sum = 3
1628 22:58:54.369968 12, 0x0, sum = 4
1629 22:58:54.372842 best_step = 10
1630 22:58:54.372959
1631 22:58:54.373064 ==
1632 22:58:54.376697 Dram Type= 6, Freq= 0, CH_1, rank 0
1633 22:58:54.379832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1634 22:58:54.379932 ==
1635 22:58:54.383289 RX Vref Scan: 1
1636 22:58:54.383404
1637 22:58:54.383475 Set Vref Range= 32 -> 127
1638 22:58:54.383539
1639 22:58:54.386340 RX Vref 32 -> 127, step: 1
1640 22:58:54.386428
1641 22:58:54.390086 RX Delay -111 -> 252, step: 8
1642 22:58:54.390174
1643 22:58:54.393363 Set Vref, RX VrefLevel [Byte0]: 32
1644 22:58:54.396424 [Byte1]: 32
1645 22:58:54.396538
1646 22:58:54.400054 Set Vref, RX VrefLevel [Byte0]: 33
1647 22:58:54.403283 [Byte1]: 33
1648 22:58:54.406528
1649 22:58:54.406627 Set Vref, RX VrefLevel [Byte0]: 34
1650 22:58:54.409588 [Byte1]: 34
1651 22:58:54.414083
1652 22:58:54.414177 Set Vref, RX VrefLevel [Byte0]: 35
1653 22:58:54.417152 [Byte1]: 35
1654 22:58:54.421463
1655 22:58:54.421583 Set Vref, RX VrefLevel [Byte0]: 36
1656 22:58:54.425276 [Byte1]: 36
1657 22:58:54.429519
1658 22:58:54.429640 Set Vref, RX VrefLevel [Byte0]: 37
1659 22:58:54.432542 [Byte1]: 37
1660 22:58:54.436833
1661 22:58:54.436957 Set Vref, RX VrefLevel [Byte0]: 38
1662 22:58:54.440419 [Byte1]: 38
1663 22:58:54.444839
1664 22:58:54.444932 Set Vref, RX VrefLevel [Byte0]: 39
1665 22:58:54.447840 [Byte1]: 39
1666 22:58:54.452083
1667 22:58:54.452203 Set Vref, RX VrefLevel [Byte0]: 40
1668 22:58:54.456024 [Byte1]: 40
1669 22:58:54.459882
1670 22:58:54.459980 Set Vref, RX VrefLevel [Byte0]: 41
1671 22:58:54.463455 [Byte1]: 41
1672 22:58:54.467560
1673 22:58:54.467654 Set Vref, RX VrefLevel [Byte0]: 42
1674 22:58:54.470738 [Byte1]: 42
1675 22:58:54.474981
1676 22:58:54.475110 Set Vref, RX VrefLevel [Byte0]: 43
1677 22:58:54.478514 [Byte1]: 43
1678 22:58:54.482818
1679 22:58:54.482953 Set Vref, RX VrefLevel [Byte0]: 44
1680 22:58:54.486582 [Byte1]: 44
1681 22:58:54.490754
1682 22:58:54.490877 Set Vref, RX VrefLevel [Byte0]: 45
1683 22:58:54.493958 [Byte1]: 45
1684 22:58:54.498363
1685 22:58:54.498502 Set Vref, RX VrefLevel [Byte0]: 46
1686 22:58:54.501561 [Byte1]: 46
1687 22:58:54.505981
1688 22:58:54.506066 Set Vref, RX VrefLevel [Byte0]: 47
1689 22:58:54.509047 [Byte1]: 47
1690 22:58:54.513344
1691 22:58:54.513462 Set Vref, RX VrefLevel [Byte0]: 48
1692 22:58:54.517076 [Byte1]: 48
1693 22:58:54.521198
1694 22:58:54.521313 Set Vref, RX VrefLevel [Byte0]: 49
1695 22:58:54.524270 [Byte1]: 49
1696 22:58:54.528771
1697 22:58:54.528884 Set Vref, RX VrefLevel [Byte0]: 50
1698 22:58:54.532349 [Byte1]: 50
1699 22:58:54.536734
1700 22:58:54.536875 Set Vref, RX VrefLevel [Byte0]: 51
1701 22:58:54.539994 [Byte1]: 51
1702 22:58:54.544221
1703 22:58:54.544313 Set Vref, RX VrefLevel [Byte0]: 52
1704 22:58:54.547222 [Byte1]: 52
1705 22:58:54.551988
1706 22:58:54.552081 Set Vref, RX VrefLevel [Byte0]: 53
1707 22:58:54.555250 [Byte1]: 53
1708 22:58:54.559634
1709 22:58:54.559760 Set Vref, RX VrefLevel [Byte0]: 54
1710 22:58:54.562908 [Byte1]: 54
1711 22:58:54.567196
1712 22:58:54.567316 Set Vref, RX VrefLevel [Byte0]: 55
1713 22:58:54.570208 [Byte1]: 55
1714 22:58:54.574940
1715 22:58:54.575066 Set Vref, RX VrefLevel [Byte0]: 56
1716 22:58:54.577973 [Byte1]: 56
1717 22:58:54.582253
1718 22:58:54.582370 Set Vref, RX VrefLevel [Byte0]: 57
1719 22:58:54.585399 [Byte1]: 57
1720 22:58:54.589781
1721 22:58:54.589898 Set Vref, RX VrefLevel [Byte0]: 58
1722 22:58:54.593389 [Byte1]: 58
1723 22:58:54.597810
1724 22:58:54.597898 Set Vref, RX VrefLevel [Byte0]: 59
1725 22:58:54.600904 [Byte1]: 59
1726 22:58:54.605355
1727 22:58:54.605451 Set Vref, RX VrefLevel [Byte0]: 60
1728 22:58:54.608519 [Byte1]: 60
1729 22:58:54.612836
1730 22:58:54.612950 Set Vref, RX VrefLevel [Byte0]: 61
1731 22:58:54.616014 [Byte1]: 61
1732 22:58:54.620372
1733 22:58:54.620502 Set Vref, RX VrefLevel [Byte0]: 62
1734 22:58:54.623973 [Byte1]: 62
1735 22:58:54.628032
1736 22:58:54.628165 Set Vref, RX VrefLevel [Byte0]: 63
1737 22:58:54.631286 [Byte1]: 63
1738 22:58:54.635621
1739 22:58:54.635713 Set Vref, RX VrefLevel [Byte0]: 64
1740 22:58:54.639256 [Byte1]: 64
1741 22:58:54.643736
1742 22:58:54.643827 Set Vref, RX VrefLevel [Byte0]: 65
1743 22:58:54.646917 [Byte1]: 65
1744 22:58:54.651080
1745 22:58:54.651189 Set Vref, RX VrefLevel [Byte0]: 66
1746 22:58:54.654689 [Byte1]: 66
1747 22:58:54.658514
1748 22:58:54.658604 Set Vref, RX VrefLevel [Byte0]: 67
1749 22:58:54.662113 [Byte1]: 67
1750 22:58:54.666642
1751 22:58:54.666725 Set Vref, RX VrefLevel [Byte0]: 68
1752 22:58:54.669549 [Byte1]: 68
1753 22:58:54.673789
1754 22:58:54.673889 Set Vref, RX VrefLevel [Byte0]: 69
1755 22:58:54.677312 [Byte1]: 69
1756 22:58:54.681521
1757 22:58:54.681612 Set Vref, RX VrefLevel [Byte0]: 70
1758 22:58:54.685168 [Byte1]: 70
1759 22:58:54.689563
1760 22:58:54.689692 Set Vref, RX VrefLevel [Byte0]: 71
1761 22:58:54.692788 [Byte1]: 71
1762 22:58:54.696861
1763 22:58:54.696999 Set Vref, RX VrefLevel [Byte0]: 72
1764 22:58:54.700181 [Byte1]: 72
1765 22:58:54.704522
1766 22:58:54.704633 Set Vref, RX VrefLevel [Byte0]: 73
1767 22:58:54.708449 [Byte1]: 73
1768 22:58:54.712260
1769 22:58:54.712404 Set Vref, RX VrefLevel [Byte0]: 74
1770 22:58:54.715334 [Byte1]: 74
1771 22:58:54.719792
1772 22:58:54.719878 Set Vref, RX VrefLevel [Byte0]: 75
1773 22:58:54.723631 [Byte1]: 75
1774 22:58:54.727853
1775 22:58:54.727970 Set Vref, RX VrefLevel [Byte0]: 76
1776 22:58:54.730789 [Byte1]: 76
1777 22:58:54.735652
1778 22:58:54.735790 Set Vref, RX VrefLevel [Byte0]: 77
1779 22:58:54.738555 [Byte1]: 77
1780 22:58:54.743062
1781 22:58:54.743181 Final RX Vref Byte 0 = 60 to rank0
1782 22:58:54.746138 Final RX Vref Byte 1 = 59 to rank0
1783 22:58:54.749339 Final RX Vref Byte 0 = 60 to rank1
1784 22:58:54.753033 Final RX Vref Byte 1 = 59 to rank1==
1785 22:58:54.756035 Dram Type= 6, Freq= 0, CH_1, rank 0
1786 22:58:54.762982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1787 22:58:54.763116 ==
1788 22:58:54.763216 DQS Delay:
1789 22:58:54.763309 DQS0 = 0, DQS1 = 0
1790 22:58:54.766199 DQM Delay:
1791 22:58:54.766285 DQM0 = 84, DQM1 = 74
1792 22:58:54.769648 DQ Delay:
1793 22:58:54.772848 DQ0 =88, DQ1 =76, DQ2 =76, DQ3 =84
1794 22:58:54.772964 DQ4 =84, DQ5 =92, DQ6 =92, DQ7 =80
1795 22:58:54.776580 DQ8 =60, DQ9 =60, DQ10 =76, DQ11 =72
1796 22:58:54.779615 DQ12 =84, DQ13 =80, DQ14 =80, DQ15 =80
1797 22:58:54.783066
1798 22:58:54.783193
1799 22:58:54.789361 [DQSOSCAuto] RK0, (LSB)MR18= 0x27fc, (MSB)MR19= 0x605, tDQSOscB0 = 411 ps tDQSOscB1 = 400 ps
1800 22:58:54.793032 CH1 RK0: MR19=605, MR18=27FC
1801 22:58:54.799784 CH1_RK0: MR19=0x605, MR18=0x27FC, DQSOSC=400, MR23=63, INC=92, DEC=61
1802 22:58:54.799919
1803 22:58:54.802905 ----->DramcWriteLeveling(PI) begin...
1804 22:58:54.803037 ==
1805 22:58:54.806695 Dram Type= 6, Freq= 0, CH_1, rank 1
1806 22:58:54.809770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1807 22:58:54.809905 ==
1808 22:58:54.813013 Write leveling (Byte 0): 25 => 25
1809 22:58:54.816097 Write leveling (Byte 1): 29 => 29
1810 22:58:54.819871 DramcWriteLeveling(PI) end<-----
1811 22:58:54.819981
1812 22:58:54.820105 ==
1813 22:58:54.823083 Dram Type= 6, Freq= 0, CH_1, rank 1
1814 22:58:54.826177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1815 22:58:54.826307 ==
1816 22:58:54.829841 [Gating] SW mode calibration
1817 22:58:54.836147 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1818 22:58:54.842765 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1819 22:58:54.846511 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1820 22:58:54.849468 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1821 22:58:54.856396 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 22:58:54.859934 0 6 12 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1823 22:58:54.862900 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 22:58:54.869776 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 22:58:54.872951 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 22:58:54.876656 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 22:58:54.882999 0 7 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1828 22:58:54.886193 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 22:58:54.889889 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 22:58:54.892934 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 22:58:54.899767 0 7 16 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1832 22:58:54.902862 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 22:58:54.906318 0 7 24 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1834 22:58:54.913103 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 22:58:54.916830 0 8 0 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 1)
1836 22:58:54.919953 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1837 22:58:54.926277 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 22:58:54.930045 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 22:58:54.933242 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 22:58:54.939513 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 22:58:54.943304 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 22:58:54.946390 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 22:58:54.952985 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 22:58:54.956422 0 9 4 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
1845 22:58:54.959604 0 9 8 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
1846 22:58:54.966217 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1847 22:58:54.969440 0 9 16 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1848 22:58:54.973164 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1849 22:58:54.979987 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1850 22:58:54.982918 0 9 28 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1851 22:58:54.986526 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1852 22:58:54.989640 0 10 4 | B1->B0 | 3232 2c2c | 0 0 | (0 0) (0 1)
1853 22:58:54.996251 0 10 8 | B1->B0 | 2828 2323 | 0 0 | (1 1) (0 0)
1854 22:58:54.999889 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 22:58:55.002918 0 10 16 | B1->B0 | 2423 2323 | 1 0 | (0 0) (0 0)
1856 22:58:55.009738 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1857 22:58:55.013155 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 22:58:55.016337 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 22:58:55.023212 0 11 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1860 22:58:55.026449 0 11 4 | B1->B0 | 2525 3636 | 0 0 | (0 0) (0 0)
1861 22:58:55.029601 0 11 8 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
1862 22:58:55.036514 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1863 22:58:55.039701 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1864 22:58:55.042782 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1865 22:58:55.049751 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1866 22:58:55.052951 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1867 22:58:55.056564 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1868 22:58:55.062893 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1869 22:58:55.066512 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1870 22:58:55.069844 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 22:58:55.072903 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 22:58:55.079939 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 22:58:55.082990 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 22:58:55.089750 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 22:58:55.092750 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 22:58:55.096289 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 22:58:55.099990 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 22:58:55.106637 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 22:58:55.109806 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1880 22:58:55.113028 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1881 22:58:55.119746 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1882 22:58:55.122871 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1883 22:58:55.126704 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1884 22:58:55.132958 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1885 22:58:55.133123 Total UI for P1: 0, mck2ui 16
1886 22:58:55.139867 best dqsien dly found for B0: ( 0, 14, 0)
1887 22:58:55.143110 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1888 22:58:55.146253 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1889 22:58:55.149426 Total UI for P1: 0, mck2ui 16
1890 22:58:55.153161 best dqsien dly found for B1: ( 0, 14, 6)
1891 22:58:55.156322 best DQS0 dly(MCK, UI, PI) = (0, 14, 0)
1892 22:58:55.159473 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1893 22:58:55.159600
1894 22:58:55.163243 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 0)
1895 22:58:55.169536 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1896 22:58:55.169650 [Gating] SW calibration Done
1897 22:58:55.169749 ==
1898 22:58:55.172757 Dram Type= 6, Freq= 0, CH_1, rank 1
1899 22:58:55.179525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1900 22:58:55.179620 ==
1901 22:58:55.179690 RX Vref Scan: 0
1902 22:58:55.179753
1903 22:58:55.183495 RX Vref 0 -> 0, step: 1
1904 22:58:55.183645
1905 22:58:55.186564 RX Delay -130 -> 252, step: 16
1906 22:58:55.189478 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1907 22:58:55.193276 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1908 22:58:55.196376 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1909 22:58:55.202762 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1910 22:58:55.206580 iDelay=206, Bit 4, Center 77 (-50 ~ 205) 256
1911 22:58:55.209669 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1912 22:58:55.212884 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1913 22:58:55.215965 iDelay=206, Bit 7, Center 69 (-50 ~ 189) 240
1914 22:58:55.223199 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1915 22:58:55.226219 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1916 22:58:55.229408 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1917 22:58:55.232606 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1918 22:58:55.236339 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1919 22:58:55.242700 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1920 22:58:55.246385 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1921 22:58:55.249703 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1922 22:58:55.249807 ==
1923 22:58:55.252627 Dram Type= 6, Freq= 0, CH_1, rank 1
1924 22:58:55.256555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1925 22:58:55.256637 ==
1926 22:58:55.259584 DQS Delay:
1927 22:58:55.259660 DQS0 = 0, DQS1 = 0
1928 22:58:55.262679 DQM Delay:
1929 22:58:55.262759 DQM0 = 79, DQM1 = 77
1930 22:58:55.262825 DQ Delay:
1931 22:58:55.266532 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =85
1932 22:58:55.269768 DQ4 =77, DQ5 =93, DQ6 =85, DQ7 =69
1933 22:58:55.272679 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
1934 22:58:55.276467 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1935 22:58:55.276559
1936 22:58:55.276628
1937 22:58:55.276690 ==
1938 22:58:55.279321 Dram Type= 6, Freq= 0, CH_1, rank 1
1939 22:58:55.286027 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1940 22:58:55.286118 ==
1941 22:58:55.286216
1942 22:58:55.286307
1943 22:58:55.286410 TX Vref Scan disable
1944 22:58:55.290381 == TX Byte 0 ==
1945 22:58:55.293328 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1946 22:58:55.297116 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1947 22:58:55.300138 == TX Byte 1 ==
1948 22:58:55.303279 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1949 22:58:55.306852 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1950 22:58:55.309893 ==
1951 22:58:55.313477 Dram Type= 6, Freq= 0, CH_1, rank 1
1952 22:58:55.316597 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1953 22:58:55.316711 ==
1954 22:58:55.329486 TX Vref=22, minBit 3, minWin=27, winSum=440
1955 22:58:55.333219 TX Vref=24, minBit 1, minWin=27, winSum=445
1956 22:58:55.336511 TX Vref=26, minBit 13, minWin=27, winSum=448
1957 22:58:55.339589 TX Vref=28, minBit 0, minWin=27, winSum=450
1958 22:58:55.342631 TX Vref=30, minBit 4, minWin=28, winSum=454
1959 22:58:55.349513 TX Vref=32, minBit 5, minWin=28, winSum=455
1960 22:58:55.352677 [TxChooseVref] Worse bit 5, Min win 28, Win sum 455, Final Vref 32
1961 22:58:55.352810
1962 22:58:55.355887 Final TX Range 1 Vref 32
1963 22:58:55.356009
1964 22:58:55.356119 ==
1965 22:58:55.359214 Dram Type= 6, Freq= 0, CH_1, rank 1
1966 22:58:55.362409 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1967 22:58:55.362557 ==
1968 22:58:55.366292
1969 22:58:55.366438
1970 22:58:55.366573 TX Vref Scan disable
1971 22:58:55.369483 == TX Byte 0 ==
1972 22:58:55.372643 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1973 22:58:55.376417 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1974 22:58:55.379496 == TX Byte 1 ==
1975 22:58:55.383150 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1976 22:58:55.386203 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1977 22:58:55.389778
1978 22:58:55.389905 [DATLAT]
1979 22:58:55.390008 Freq=800, CH1 RK1
1980 22:58:55.390122
1981 22:58:55.392589 DATLAT Default: 0xa
1982 22:58:55.392669 0, 0xFFFF, sum = 0
1983 22:58:55.395966 1, 0xFFFF, sum = 0
1984 22:58:55.396094 2, 0xFFFF, sum = 0
1985 22:58:55.399355 3, 0xFFFF, sum = 0
1986 22:58:55.399439 4, 0xFFFF, sum = 0
1987 22:58:55.403154 5, 0xFFFF, sum = 0
1988 22:58:55.405984 6, 0xFFFF, sum = 0
1989 22:58:55.406125 7, 0xFFFF, sum = 0
1990 22:58:55.409724 8, 0xFFFF, sum = 0
1991 22:58:55.409810 9, 0x0, sum = 1
1992 22:58:55.409896 10, 0x0, sum = 2
1993 22:58:55.412719 11, 0x0, sum = 3
1994 22:58:55.412802 12, 0x0, sum = 4
1995 22:58:55.416439 best_step = 10
1996 22:58:55.416542
1997 22:58:55.416639 ==
1998 22:58:55.419450 Dram Type= 6, Freq= 0, CH_1, rank 1
1999 22:58:55.422596 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2000 22:58:55.422681 ==
2001 22:58:55.426254 RX Vref Scan: 0
2002 22:58:55.426351
2003 22:58:55.426419 RX Vref 0 -> 0, step: 1
2004 22:58:55.426495
2005 22:58:55.429330 RX Delay -95 -> 252, step: 8
2006 22:58:55.435865 iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232
2007 22:58:55.439208 iDelay=209, Bit 1, Center 76 (-39 ~ 192) 232
2008 22:58:55.442861 iDelay=209, Bit 2, Center 68 (-47 ~ 184) 232
2009 22:58:55.445962 iDelay=209, Bit 3, Center 76 (-39 ~ 192) 232
2010 22:58:55.449731 iDelay=209, Bit 4, Center 80 (-39 ~ 200) 240
2011 22:58:55.455977 iDelay=209, Bit 5, Center 92 (-23 ~ 208) 232
2012 22:58:55.459870 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
2013 22:58:55.462923 iDelay=209, Bit 7, Center 76 (-39 ~ 192) 232
2014 22:58:55.466709 iDelay=209, Bit 8, Center 68 (-47 ~ 184) 232
2015 22:58:55.469958 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
2016 22:58:55.476226 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
2017 22:58:55.479326 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
2018 22:58:55.483120 iDelay=209, Bit 12, Center 76 (-39 ~ 192) 232
2019 22:58:55.486295 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
2020 22:58:55.489863 iDelay=209, Bit 14, Center 84 (-31 ~ 200) 232
2021 22:58:55.496216 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
2022 22:58:55.496333 ==
2023 22:58:55.499787 Dram Type= 6, Freq= 0, CH_1, rank 1
2024 22:58:55.503143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2025 22:58:55.503232 ==
2026 22:58:55.503367 DQS Delay:
2027 22:58:55.506129 DQS0 = 0, DQS1 = 0
2028 22:58:55.506214 DQM Delay:
2029 22:58:55.509481 DQM0 = 80, DQM1 = 74
2030 22:58:55.509615 DQ Delay:
2031 22:58:55.513146 DQ0 =84, DQ1 =76, DQ2 =68, DQ3 =76
2032 22:58:55.516520 DQ4 =80, DQ5 =92, DQ6 =92, DQ7 =76
2033 22:58:55.519505 DQ8 =68, DQ9 =64, DQ10 =72, DQ11 =68
2034 22:58:55.523202 DQ12 =76, DQ13 =84, DQ14 =84, DQ15 =80
2035 22:58:55.523314
2036 22:58:55.523435
2037 22:58:55.529605 [DQSOSCAuto] RK1, (LSB)MR18= 0x1c27, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 402 ps
2038 22:58:55.533307 CH1 RK1: MR19=606, MR18=1C27
2039 22:58:55.539611 CH1_RK1: MR19=0x606, MR18=0x1C27, DQSOSC=400, MR23=63, INC=92, DEC=61
2040 22:58:55.543154 [RxdqsGatingPostProcess] freq 800
2041 22:58:55.549457 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2042 22:58:55.549553 Pre-setting of DQS Precalculation
2043 22:58:55.556461 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2044 22:58:55.563467 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2045 22:58:55.569626 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2046 22:58:55.569724
2047 22:58:55.569795
2048 22:58:55.572930 [Calibration Summary] 1600 Mbps
2049 22:58:55.576598 CH 0, Rank 0
2050 22:58:55.576686 SW Impedance : PASS
2051 22:58:55.579779 DUTY Scan : NO K
2052 22:58:55.582896 ZQ Calibration : PASS
2053 22:58:55.583004 Jitter Meter : NO K
2054 22:58:55.586453 CBT Training : PASS
2055 22:58:55.586574 Write leveling : PASS
2056 22:58:55.589699 RX DQS gating : PASS
2057 22:58:55.593350 RX DQ/DQS(RDDQC) : PASS
2058 22:58:55.593461 TX DQ/DQS : PASS
2059 22:58:55.596425 RX DATLAT : PASS
2060 22:58:55.599579 RX DQ/DQS(Engine): PASS
2061 22:58:55.599685 TX OE : NO K
2062 22:58:55.603206 All Pass.
2063 22:58:55.603309
2064 22:58:55.603422 CH 0, Rank 1
2065 22:58:55.606389 SW Impedance : PASS
2066 22:58:55.606500 DUTY Scan : NO K
2067 22:58:55.610071 ZQ Calibration : PASS
2068 22:58:55.613290 Jitter Meter : NO K
2069 22:58:55.613379 CBT Training : PASS
2070 22:58:55.616690 Write leveling : PASS
2071 22:58:55.619682 RX DQS gating : PASS
2072 22:58:55.619826 RX DQ/DQS(RDDQC) : PASS
2073 22:58:55.623329 TX DQ/DQS : PASS
2074 22:58:55.623452 RX DATLAT : PASS
2075 22:58:55.626302 RX DQ/DQS(Engine): PASS
2076 22:58:55.629808 TX OE : NO K
2077 22:58:55.629922 All Pass.
2078 22:58:55.630028
2079 22:58:55.630138 CH 1, Rank 0
2080 22:58:55.633467 SW Impedance : PASS
2081 22:58:55.636488 DUTY Scan : NO K
2082 22:58:55.636619 ZQ Calibration : PASS
2083 22:58:55.639978 Jitter Meter : NO K
2084 22:58:55.642826 CBT Training : PASS
2085 22:58:55.642947 Write leveling : PASS
2086 22:58:55.646179 RX DQS gating : PASS
2087 22:58:55.649792 RX DQ/DQS(RDDQC) : PASS
2088 22:58:55.649919 TX DQ/DQS : PASS
2089 22:58:55.653021 RX DATLAT : PASS
2090 22:58:55.656799 RX DQ/DQS(Engine): PASS
2091 22:58:55.656913 TX OE : NO K
2092 22:58:55.659782 All Pass.
2093 22:58:55.659896
2094 22:58:55.660011 CH 1, Rank 1
2095 22:58:55.662887 SW Impedance : PASS
2096 22:58:55.662997 DUTY Scan : NO K
2097 22:58:55.666146 ZQ Calibration : PASS
2098 22:58:55.669743 Jitter Meter : NO K
2099 22:58:55.669852 CBT Training : PASS
2100 22:58:55.673004 Write leveling : PASS
2101 22:58:55.673115 RX DQS gating : PASS
2102 22:58:55.676682 RX DQ/DQS(RDDQC) : PASS
2103 22:58:55.679979 TX DQ/DQS : PASS
2104 22:58:55.680070 RX DATLAT : PASS
2105 22:58:55.683209 RX DQ/DQS(Engine): PASS
2106 22:58:55.686258 TX OE : NO K
2107 22:58:55.686378 All Pass.
2108 22:58:55.686485
2109 22:58:55.689851 DramC Write-DBI off
2110 22:58:55.689961 PER_BANK_REFRESH: Hybrid Mode
2111 22:58:55.692927 TX_TRACKING: ON
2112 22:58:55.696173 [GetDramInforAfterCalByMRR] Vendor 6.
2113 22:58:55.699865 [GetDramInforAfterCalByMRR] Revision 606.
2114 22:58:55.702865 [GetDramInforAfterCalByMRR] Revision 2 0.
2115 22:58:55.702972 MR0 0x3b3b
2116 22:58:55.706683 MR8 0x5151
2117 22:58:55.710149 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2118 22:58:55.710268
2119 22:58:55.710377 MR0 0x3b3b
2120 22:58:55.710495 MR8 0x5151
2121 22:58:55.716433 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2122 22:58:55.716545
2123 22:58:55.722967 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2124 22:58:55.726764 [FAST_K] Save calibration result to emmc
2125 22:58:55.729758 [FAST_K] Save calibration result to emmc
2126 22:58:55.733346 dram_init: config_dvfs: 1
2127 22:58:55.736681 dramc_set_vcore_voltage set vcore to 662500
2128 22:58:55.740292 Read voltage for 1200, 2
2129 22:58:55.740379 Vio18 = 0
2130 22:58:55.743301 Vcore = 662500
2131 22:58:55.743413 Vdram = 0
2132 22:58:55.743482 Vddq = 0
2133 22:58:55.743557 Vmddr = 0
2134 22:58:55.750215 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2135 22:58:55.756582 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2136 22:58:55.756710 MEM_TYPE=3, freq_sel=15
2137 22:58:55.759792 sv_algorithm_assistance_LP4_1600
2138 22:58:55.762958 ============ PULL DRAM RESETB DOWN ============
2139 22:58:55.769666 ========== PULL DRAM RESETB DOWN end =========
2140 22:58:55.773450 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2141 22:58:55.776652 ===================================
2142 22:58:55.779899 LPDDR4 DRAM CONFIGURATION
2143 22:58:55.782954 ===================================
2144 22:58:55.783034 EX_ROW_EN[0] = 0x0
2145 22:58:55.786805 EX_ROW_EN[1] = 0x0
2146 22:58:55.786917 LP4Y_EN = 0x0
2147 22:58:55.790031 WORK_FSP = 0x0
2148 22:58:55.790118 WL = 0x4
2149 22:58:55.793012 RL = 0x4
2150 22:58:55.793097 BL = 0x2
2151 22:58:55.796713 RPST = 0x0
2152 22:58:55.799898 RD_PRE = 0x0
2153 22:58:55.799985 WR_PRE = 0x1
2154 22:58:55.803476 WR_PST = 0x0
2155 22:58:55.803572 DBI_WR = 0x0
2156 22:58:55.806549 DBI_RD = 0x0
2157 22:58:55.806665 OTF = 0x1
2158 22:58:55.809645 ===================================
2159 22:58:55.813299 ===================================
2160 22:58:55.813411 ANA top config
2161 22:58:55.816411 ===================================
2162 22:58:55.820182 DLL_ASYNC_EN = 0
2163 22:58:55.823152 ALL_SLAVE_EN = 0
2164 22:58:55.826308 NEW_RANK_MODE = 1
2165 22:58:55.830032 DLL_IDLE_MODE = 1
2166 22:58:55.830123 LP45_APHY_COMB_EN = 1
2167 22:58:55.832928 TX_ODT_DIS = 1
2168 22:58:55.836760 NEW_8X_MODE = 1
2169 22:58:55.840424 ===================================
2170 22:58:55.843493 ===================================
2171 22:58:55.846412 data_rate = 2400
2172 22:58:55.850266 CKR = 1
2173 22:58:55.850375 DQ_P2S_RATIO = 8
2174 22:58:55.853384 ===================================
2175 22:58:55.856372 CA_P2S_RATIO = 8
2176 22:58:55.859874 DQ_CA_OPEN = 0
2177 22:58:55.863487 DQ_SEMI_OPEN = 0
2178 22:58:55.867062 CA_SEMI_OPEN = 0
2179 22:58:55.867180 CA_FULL_RATE = 0
2180 22:58:55.870278 DQ_CKDIV4_EN = 0
2181 22:58:55.873390 CA_CKDIV4_EN = 0
2182 22:58:55.876542 CA_PREDIV_EN = 0
2183 22:58:55.879834 PH8_DLY = 17
2184 22:58:55.882918 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2185 22:58:55.886752 DQ_AAMCK_DIV = 4
2186 22:58:55.886881 CA_AAMCK_DIV = 4
2187 22:58:55.889796 CA_ADMCK_DIV = 4
2188 22:58:55.893620 DQ_TRACK_CA_EN = 0
2189 22:58:55.896701 CA_PICK = 1200
2190 22:58:55.899737 CA_MCKIO = 1200
2191 22:58:55.902928 MCKIO_SEMI = 0
2192 22:58:55.906399 PLL_FREQ = 2366
2193 22:58:55.906493 DQ_UI_PI_RATIO = 32
2194 22:58:55.910127 CA_UI_PI_RATIO = 0
2195 22:58:55.913331 ===================================
2196 22:58:55.916428 ===================================
2197 22:58:55.920080 memory_type:LPDDR4
2198 22:58:55.923277 GP_NUM : 10
2199 22:58:55.923399 SRAM_EN : 1
2200 22:58:55.926406 MD32_EN : 0
2201 22:58:55.930119 ===================================
2202 22:58:55.933150 [ANA_INIT] >>>>>>>>>>>>>>
2203 22:58:55.933266 <<<<<< [CONFIGURE PHASE]: ANA_TX
2204 22:58:55.936281 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2205 22:58:55.939835 ===================================
2206 22:58:55.942931 data_rate = 2400,PCW = 0X5b00
2207 22:58:55.946443 ===================================
2208 22:58:55.949505 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2209 22:58:55.956708 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2210 22:58:55.962904 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2211 22:58:55.966455 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2212 22:58:55.970056 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2213 22:58:55.973265 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2214 22:58:55.976304 [ANA_INIT] flow start
2215 22:58:55.976431 [ANA_INIT] PLL >>>>>>>>
2216 22:58:55.980145 [ANA_INIT] PLL <<<<<<<<
2217 22:58:55.983231 [ANA_INIT] MIDPI >>>>>>>>
2218 22:58:55.983358 [ANA_INIT] MIDPI <<<<<<<<
2219 22:58:55.986448 [ANA_INIT] DLL >>>>>>>>
2220 22:58:55.989652 [ANA_INIT] DLL <<<<<<<<
2221 22:58:55.989779 [ANA_INIT] flow end
2222 22:58:55.996490 ============ LP4 DIFF to SE enter ============
2223 22:58:55.999579 ============ LP4 DIFF to SE exit ============
2224 22:58:55.999703 [ANA_INIT] <<<<<<<<<<<<<
2225 22:58:56.003316 [Flow] Enable top DCM control >>>>>
2226 22:58:56.006626 [Flow] Enable top DCM control <<<<<
2227 22:58:56.010036 Enable DLL master slave shuffle
2228 22:58:56.016304 ==============================================================
2229 22:58:56.019492 Gating Mode config
2230 22:58:56.023158 ==============================================================
2231 22:58:56.026232 Config description:
2232 22:58:56.036244 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2233 22:58:56.042830 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2234 22:58:56.046600 SELPH_MODE 0: By rank 1: By Phase
2235 22:58:56.053019 ==============================================================
2236 22:58:56.056308 GAT_TRACK_EN = 1
2237 22:58:56.059817 RX_GATING_MODE = 2
2238 22:58:56.059937 RX_GATING_TRACK_MODE = 2
2239 22:58:56.062703 SELPH_MODE = 1
2240 22:58:56.066376 PICG_EARLY_EN = 1
2241 22:58:56.069422 VALID_LAT_VALUE = 1
2242 22:58:56.076117 ==============================================================
2243 22:58:56.079848 Enter into Gating configuration >>>>
2244 22:58:56.083051 Exit from Gating configuration <<<<
2245 22:58:56.086222 Enter into DVFS_PRE_config >>>>>
2246 22:58:56.096358 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2247 22:58:56.099670 Exit from DVFS_PRE_config <<<<<
2248 22:58:56.103372 Enter into PICG configuration >>>>
2249 22:58:56.106390 Exit from PICG configuration <<<<
2250 22:58:56.109560 [RX_INPUT] configuration >>>>>
2251 22:58:56.113044 [RX_INPUT] configuration <<<<<
2252 22:58:56.116131 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2253 22:58:56.122874 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2254 22:58:56.129616 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2255 22:58:56.132672 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2256 22:58:56.139432 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2257 22:58:56.146620 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2258 22:58:56.149635 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2259 22:58:56.153208 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2260 22:58:56.159668 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2261 22:58:56.162872 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2262 22:58:56.166561 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2263 22:58:56.172619 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2264 22:58:56.176135 ===================================
2265 22:58:56.176256 LPDDR4 DRAM CONFIGURATION
2266 22:58:56.179877 ===================================
2267 22:58:56.182975 EX_ROW_EN[0] = 0x0
2268 22:58:56.186048 EX_ROW_EN[1] = 0x0
2269 22:58:56.186159 LP4Y_EN = 0x0
2270 22:58:56.189749 WORK_FSP = 0x0
2271 22:58:56.189887 WL = 0x4
2272 22:58:56.193032 RL = 0x4
2273 22:58:56.193155 BL = 0x2
2274 22:58:56.196215 RPST = 0x0
2275 22:58:56.196331 RD_PRE = 0x0
2276 22:58:56.199824 WR_PRE = 0x1
2277 22:58:56.199954 WR_PST = 0x0
2278 22:58:56.202940 DBI_WR = 0x0
2279 22:58:56.203060 DBI_RD = 0x0
2280 22:58:56.206158 OTF = 0x1
2281 22:58:56.209902 ===================================
2282 22:58:56.213007 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2283 22:58:56.216132 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2284 22:58:56.223034 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2285 22:58:56.226101 ===================================
2286 22:58:56.226234 LPDDR4 DRAM CONFIGURATION
2287 22:58:56.229276 ===================================
2288 22:58:56.232766 EX_ROW_EN[0] = 0x10
2289 22:58:56.232878 EX_ROW_EN[1] = 0x0
2290 22:58:56.236577 LP4Y_EN = 0x0
2291 22:58:56.236704 WORK_FSP = 0x0
2292 22:58:56.239671 WL = 0x4
2293 22:58:56.239788 RL = 0x4
2294 22:58:56.242693 BL = 0x2
2295 22:58:56.246234 RPST = 0x0
2296 22:58:56.246352 RD_PRE = 0x0
2297 22:58:56.249296 WR_PRE = 0x1
2298 22:58:56.249416 WR_PST = 0x0
2299 22:58:56.253012 DBI_WR = 0x0
2300 22:58:56.253147 DBI_RD = 0x0
2301 22:58:56.256075 OTF = 0x1
2302 22:58:56.259792 ===================================
2303 22:58:56.262804 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2304 22:58:56.266029 ==
2305 22:58:56.269806 Dram Type= 6, Freq= 0, CH_0, rank 0
2306 22:58:56.272916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2307 22:58:56.273049 ==
2308 22:58:56.275832 [Duty_Offset_Calibration]
2309 22:58:56.275914 B0:2 B1:-1 CA:1
2310 22:58:56.275999
2311 22:58:56.279525 [DutyScan_Calibration_Flow] k_type=0
2312 22:58:56.288235
2313 22:58:56.288334 ==CLK 0==
2314 22:58:56.291378 Final CLK duty delay cell = -4
2315 22:58:56.295144 [-4] MAX Duty = 5031%(X100), DQS PI = 4
2316 22:58:56.298213 [-4] MIN Duty = 4875%(X100), DQS PI = 32
2317 22:58:56.301387 [-4] AVG Duty = 4953%(X100)
2318 22:58:56.301527
2319 22:58:56.304621 CH0 CLK Duty spec in!! Max-Min= 156%
2320 22:58:56.308339 [DutyScan_Calibration_Flow] ====Done====
2321 22:58:56.308459
2322 22:58:56.311580 [DutyScan_Calibration_Flow] k_type=1
2323 22:58:56.326274
2324 22:58:56.326455 ==DQS 0 ==
2325 22:58:56.329353 Final DQS duty delay cell = -4
2326 22:58:56.332996 [-4] MAX Duty = 5000%(X100), DQS PI = 54
2327 22:58:56.335907 [-4] MIN Duty = 4876%(X100), DQS PI = 12
2328 22:58:56.339581 [-4] AVG Duty = 4938%(X100)
2329 22:58:56.339708
2330 22:58:56.339814 ==DQS 1 ==
2331 22:58:56.342723 Final DQS duty delay cell = -4
2332 22:58:56.346552 [-4] MAX Duty = 5124%(X100), DQS PI = 6
2333 22:58:56.349550 [-4] MIN Duty = 5000%(X100), DQS PI = 44
2334 22:58:56.353178 [-4] AVG Duty = 5062%(X100)
2335 22:58:56.353292
2336 22:58:56.356450 CH0 DQS 0 Duty spec in!! Max-Min= 124%
2337 22:58:56.356557
2338 22:58:56.359590 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2339 22:58:56.362748 [DutyScan_Calibration_Flow] ====Done====
2340 22:58:56.362868
2341 22:58:56.365730 [DutyScan_Calibration_Flow] k_type=3
2342 22:58:56.383289
2343 22:58:56.383481 ==DQM 0 ==
2344 22:58:56.386778 Final DQM duty delay cell = 0
2345 22:58:56.389804 [0] MAX Duty = 5000%(X100), DQS PI = 54
2346 22:58:56.393003 [0] MIN Duty = 4876%(X100), DQS PI = 22
2347 22:58:56.396720 [0] AVG Duty = 4938%(X100)
2348 22:58:56.396820
2349 22:58:56.396888 ==DQM 1 ==
2350 22:58:56.399938 Final DQM duty delay cell = 0
2351 22:58:56.403146 [0] MAX Duty = 5124%(X100), DQS PI = 32
2352 22:58:56.406814 [0] MIN Duty = 4969%(X100), DQS PI = 10
2353 22:58:56.409931 [0] AVG Duty = 5046%(X100)
2354 22:58:56.410021
2355 22:58:56.413106 CH0 DQM 0 Duty spec in!! Max-Min= 124%
2356 22:58:56.413241
2357 22:58:56.417085 CH0 DQM 1 Duty spec in!! Max-Min= 155%
2358 22:58:56.419806 [DutyScan_Calibration_Flow] ====Done====
2359 22:58:56.419937
2360 22:58:56.423689 [DutyScan_Calibration_Flow] k_type=2
2361 22:58:56.439041
2362 22:58:56.439211 ==DQ 0 ==
2363 22:58:56.442727 Final DQ duty delay cell = -4
2364 22:58:56.445907 [-4] MAX Duty = 5031%(X100), DQS PI = 0
2365 22:58:56.449125 [-4] MIN Duty = 4876%(X100), DQS PI = 18
2366 22:58:56.452942 [-4] AVG Duty = 4953%(X100)
2367 22:58:56.453036
2368 22:58:56.453164 ==DQ 1 ==
2369 22:58:56.455976 Final DQ duty delay cell = 0
2370 22:58:56.459654 [0] MAX Duty = 5031%(X100), DQS PI = 18
2371 22:58:56.462731 [0] MIN Duty = 4907%(X100), DQS PI = 46
2372 22:58:56.462847 [0] AVG Duty = 4969%(X100)
2373 22:58:56.465755
2374 22:58:56.469351 CH0 DQ 0 Duty spec in!! Max-Min= 155%
2375 22:58:56.469445
2376 22:58:56.472772 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2377 22:58:56.476247 [DutyScan_Calibration_Flow] ====Done====
2378 22:58:56.476361 ==
2379 22:58:56.479179 Dram Type= 6, Freq= 0, CH_1, rank 0
2380 22:58:56.482877 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2381 22:58:56.483005 ==
2382 22:58:56.485742 [Duty_Offset_Calibration]
2383 22:58:56.485855 B0:1 B1:1 CA:2
2384 22:58:56.485953
2385 22:58:56.489259 [DutyScan_Calibration_Flow] k_type=0
2386 22:58:56.499270
2387 22:58:56.499426 ==CLK 0==
2388 22:58:56.502931 Final CLK duty delay cell = 0
2389 22:58:56.506075 [0] MAX Duty = 5156%(X100), DQS PI = 24
2390 22:58:56.509256 [0] MIN Duty = 4969%(X100), DQS PI = 38
2391 22:58:56.509382 [0] AVG Duty = 5062%(X100)
2392 22:58:56.513062
2393 22:58:56.513178 CH1 CLK Duty spec in!! Max-Min= 187%
2394 22:58:56.519324 [DutyScan_Calibration_Flow] ====Done====
2395 22:58:56.519452
2396 22:58:56.522906 [DutyScan_Calibration_Flow] k_type=1
2397 22:58:56.538723
2398 22:58:56.538902 ==DQS 0 ==
2399 22:58:56.542256 Final DQS duty delay cell = 0
2400 22:58:56.545207 [0] MAX Duty = 5031%(X100), DQS PI = 18
2401 22:58:56.548348 [0] MIN Duty = 4844%(X100), DQS PI = 48
2402 22:58:56.552238 [0] AVG Duty = 4937%(X100)
2403 22:58:56.552370
2404 22:58:56.552489 ==DQS 1 ==
2405 22:58:56.555357 Final DQS duty delay cell = 0
2406 22:58:56.558486 [0] MAX Duty = 5062%(X100), DQS PI = 36
2407 22:58:56.562265 [0] MIN Duty = 4907%(X100), DQS PI = 8
2408 22:58:56.562394 [0] AVG Duty = 4984%(X100)
2409 22:58:56.565374
2410 22:58:56.568519 CH1 DQS 0 Duty spec in!! Max-Min= 187%
2411 22:58:56.568638
2412 22:58:56.571872 CH1 DQS 1 Duty spec in!! Max-Min= 155%
2413 22:58:56.575528 [DutyScan_Calibration_Flow] ====Done====
2414 22:58:56.575644
2415 22:58:56.578522 [DutyScan_Calibration_Flow] k_type=3
2416 22:58:56.595413
2417 22:58:56.595597 ==DQM 0 ==
2418 22:58:56.598277 Final DQM duty delay cell = 0
2419 22:58:56.601944 [0] MAX Duty = 5093%(X100), DQS PI = 16
2420 22:58:56.605080 [0] MIN Duty = 4907%(X100), DQS PI = 44
2421 22:58:56.608212 [0] AVG Duty = 5000%(X100)
2422 22:58:56.608329
2423 22:58:56.608452 ==DQM 1 ==
2424 22:58:56.612050 Final DQM duty delay cell = 0
2425 22:58:56.615193 [0] MAX Duty = 5156%(X100), DQS PI = 60
2426 22:58:56.618327 [0] MIN Duty = 4938%(X100), DQS PI = 22
2427 22:58:56.621743 [0] AVG Duty = 5047%(X100)
2428 22:58:56.621884
2429 22:58:56.625374 CH1 DQM 0 Duty spec in!! Max-Min= 186%
2430 22:58:56.625508
2431 22:58:56.628603 CH1 DQM 1 Duty spec in!! Max-Min= 218%
2432 22:58:56.631645 [DutyScan_Calibration_Flow] ====Done====
2433 22:58:56.631750
2434 22:58:56.634851 [DutyScan_Calibration_Flow] k_type=2
2435 22:58:56.651527
2436 22:58:56.651692 ==DQ 0 ==
2437 22:58:56.655183 Final DQ duty delay cell = 0
2438 22:58:56.658283 [0] MAX Duty = 5124%(X100), DQS PI = 18
2439 22:58:56.661458 [0] MIN Duty = 4938%(X100), DQS PI = 50
2440 22:58:56.661586 [0] AVG Duty = 5031%(X100)
2441 22:58:56.665139
2442 22:58:56.665266 ==DQ 1 ==
2443 22:58:56.668230 Final DQ duty delay cell = 0
2444 22:58:56.671913 [0] MAX Duty = 5124%(X100), DQS PI = 58
2445 22:58:56.674915 [0] MIN Duty = 5031%(X100), DQS PI = 2
2446 22:58:56.675036 [0] AVG Duty = 5077%(X100)
2447 22:58:56.675137
2448 22:58:56.678579 CH1 DQ 0 Duty spec in!! Max-Min= 186%
2449 22:58:56.681648
2450 22:58:56.681760 CH1 DQ 1 Duty spec in!! Max-Min= 93%
2451 22:58:56.688439 [DutyScan_Calibration_Flow] ====Done====
2452 22:58:56.691588 nWR fixed to 30
2453 22:58:56.691720 [ModeRegInit_LP4] CH0 RK0
2454 22:58:56.695157 [ModeRegInit_LP4] CH0 RK1
2455 22:58:56.698376 [ModeRegInit_LP4] CH1 RK0
2456 22:58:56.698460 [ModeRegInit_LP4] CH1 RK1
2457 22:58:56.701828 match AC timing 7
2458 22:58:56.705216 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2459 22:58:56.708483 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2460 22:58:56.715273 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2461 22:58:56.718571 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2462 22:58:56.724880 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2463 22:58:56.725009 ==
2464 22:58:56.728677 Dram Type= 6, Freq= 0, CH_0, rank 0
2465 22:58:56.731692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2466 22:58:56.731817 ==
2467 22:58:56.738569 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2468 22:58:56.741650 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2469 22:58:56.751663 [CA 0] Center 40 (10~71) winsize 62
2470 22:58:56.755301 [CA 1] Center 39 (9~70) winsize 62
2471 22:58:56.758342 [CA 2] Center 36 (6~67) winsize 62
2472 22:58:56.761416 [CA 3] Center 35 (5~66) winsize 62
2473 22:58:56.764820 [CA 4] Center 34 (4~65) winsize 62
2474 22:58:56.768570 [CA 5] Center 34 (4~64) winsize 61
2475 22:58:56.768693
2476 22:58:56.771754 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2477 22:58:56.771864
2478 22:58:56.774827 [CATrainingPosCal] consider 1 rank data
2479 22:58:56.778496 u2DelayCellTimex100 = 270/100 ps
2480 22:58:56.782087 CA0 delay=40 (10~71),Diff = 6 PI (28 cell)
2481 22:58:56.785124 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2482 22:58:56.791954 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2483 22:58:56.794841 CA3 delay=35 (5~66),Diff = 1 PI (4 cell)
2484 22:58:56.798398 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
2485 22:58:56.801630 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2486 22:58:56.801745
2487 22:58:56.805272 CA PerBit enable=1, Macro0, CA PI delay=34
2488 22:58:56.805381
2489 22:58:56.808227 [CBTSetCACLKResult] CA Dly = 34
2490 22:58:56.808336 CS Dly: 7 (0~38)
2491 22:58:56.808434 ==
2492 22:58:56.811871 Dram Type= 6, Freq= 0, CH_0, rank 1
2493 22:58:56.818634 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2494 22:58:56.818749 ==
2495 22:58:56.821730 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2496 22:58:56.828643 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2497 22:58:56.837815 [CA 0] Center 39 (9~70) winsize 62
2498 22:58:56.841124 [CA 1] Center 39 (9~70) winsize 62
2499 22:58:56.844013 [CA 2] Center 36 (6~67) winsize 62
2500 22:58:56.847556 [CA 3] Center 36 (5~67) winsize 63
2501 22:58:56.850630 [CA 4] Center 34 (4~65) winsize 62
2502 22:58:56.854280 [CA 5] Center 34 (4~64) winsize 61
2503 22:58:56.854395
2504 22:58:56.857960 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2505 22:58:56.858091
2506 22:58:56.861059 [CATrainingPosCal] consider 2 rank data
2507 22:58:56.864123 u2DelayCellTimex100 = 270/100 ps
2508 22:58:56.867981 CA0 delay=40 (10~70),Diff = 6 PI (28 cell)
2509 22:58:56.871119 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2510 22:58:56.877961 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2511 22:58:56.881029 CA3 delay=35 (5~66),Diff = 1 PI (4 cell)
2512 22:58:56.884700 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
2513 22:58:56.887781 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2514 22:58:56.887901
2515 22:58:56.891500 CA PerBit enable=1, Macro0, CA PI delay=34
2516 22:58:56.891625
2517 22:58:56.894460 [CBTSetCACLKResult] CA Dly = 34
2518 22:58:56.894573 CS Dly: 8 (0~41)
2519 22:58:56.894670
2520 22:58:56.898217 ----->DramcWriteLeveling(PI) begin...
2521 22:58:56.898331 ==
2522 22:58:56.901018 Dram Type= 6, Freq= 0, CH_0, rank 0
2523 22:58:56.907866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2524 22:58:56.907991 ==
2525 22:58:56.911634 Write leveling (Byte 0): 30 => 30
2526 22:58:56.914630 Write leveling (Byte 1): 29 => 29
2527 22:58:56.914742 DramcWriteLeveling(PI) end<-----
2528 22:58:56.914847
2529 22:58:56.918168 ==
2530 22:58:56.921371 Dram Type= 6, Freq= 0, CH_0, rank 0
2531 22:58:56.924442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2532 22:58:56.924571 ==
2533 22:58:56.928326 [Gating] SW mode calibration
2534 22:58:56.934725 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2535 22:58:56.937847 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2536 22:58:56.944654 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2537 22:58:56.948432 0 15 4 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
2538 22:58:56.951517 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2539 22:58:56.958296 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2540 22:58:56.961399 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2541 22:58:56.964924 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2542 22:58:56.971819 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2543 22:58:56.974874 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2544 22:58:56.977942 1 0 0 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 1)
2545 22:58:56.984886 1 0 4 | B1->B0 | 2828 2323 | 0 0 | (1 0) (0 0)
2546 22:58:56.987999 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2547 22:58:56.991634 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2548 22:58:56.994798 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2549 22:58:57.001358 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2550 22:58:57.004853 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2551 22:58:57.008002 1 0 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
2552 22:58:57.014711 1 1 0 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
2553 22:58:57.018365 1 1 4 | B1->B0 | 3636 4444 | 0 0 | (0 0) (0 0)
2554 22:58:57.021318 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2555 22:58:57.028338 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2556 22:58:57.031385 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2557 22:58:57.035206 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2558 22:58:57.041331 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2559 22:58:57.044994 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2560 22:58:57.047965 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2561 22:58:57.054747 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2562 22:58:57.057901 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 22:58:57.061681 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 22:58:57.068447 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 22:58:57.071429 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 22:58:57.074683 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 22:58:57.078438 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 22:58:57.084799 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 22:58:57.088127 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2570 22:58:57.091662 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2571 22:58:57.098278 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2572 22:58:57.101458 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2573 22:58:57.105028 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2574 22:58:57.111533 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2575 22:58:57.114717 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2576 22:58:57.118376 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2577 22:58:57.125019 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2578 22:58:57.128159 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2579 22:58:57.131370 Total UI for P1: 0, mck2ui 16
2580 22:58:57.135246 best dqsien dly found for B0: ( 1, 4, 2)
2581 22:58:57.138457 Total UI for P1: 0, mck2ui 16
2582 22:58:57.141477 best dqsien dly found for B1: ( 1, 4, 2)
2583 22:58:57.144743 best DQS0 dly(MCK, UI, PI) = (1, 4, 2)
2584 22:58:57.148554 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2585 22:58:57.148670
2586 22:58:57.151429 best DQS0 P1 dly(MCK, UI, PI) = (1, 8, 2)
2587 22:58:57.154531 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2588 22:58:57.158128 [Gating] SW calibration Done
2589 22:58:57.158256 ==
2590 22:58:57.161261 Dram Type= 6, Freq= 0, CH_0, rank 0
2591 22:58:57.164915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2592 22:58:57.165036 ==
2593 22:58:57.168210 RX Vref Scan: 0
2594 22:58:57.168332
2595 22:58:57.171186 RX Vref 0 -> 0, step: 1
2596 22:58:57.171305
2597 22:58:57.171423 RX Delay -40 -> 252, step: 8
2598 22:58:57.178166 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2599 22:58:57.181305 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2600 22:58:57.184981 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2601 22:58:57.188237 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2602 22:58:57.191411 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2603 22:58:57.198337 iDelay=200, Bit 5, Center 107 (40 ~ 175) 136
2604 22:58:57.201266 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2605 22:58:57.204874 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2606 22:58:57.208097 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2607 22:58:57.211732 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2608 22:58:57.214650 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2609 22:58:57.221583 iDelay=200, Bit 11, Center 99 (24 ~ 175) 152
2610 22:58:57.225040 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2611 22:58:57.228043 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2612 22:58:57.231173 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2613 22:58:57.238087 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2614 22:58:57.238214 ==
2615 22:58:57.241237 Dram Type= 6, Freq= 0, CH_0, rank 0
2616 22:58:57.244418 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2617 22:58:57.244535 ==
2618 22:58:57.244657 DQS Delay:
2619 22:58:57.248318 DQS0 = 0, DQS1 = 0
2620 22:58:57.248432 DQM Delay:
2621 22:58:57.251569 DQM0 = 115, DQM1 = 107
2622 22:58:57.251688 DQ Delay:
2623 22:58:57.254405 DQ0 =115, DQ1 =115, DQ2 =115, DQ3 =111
2624 22:58:57.257613 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2625 22:58:57.261443 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =99
2626 22:58:57.264483 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115
2627 22:58:57.264593
2628 22:58:57.264701
2629 22:58:57.264804 ==
2630 22:58:57.268251 Dram Type= 6, Freq= 0, CH_0, rank 0
2631 22:58:57.274419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2632 22:58:57.274566 ==
2633 22:58:57.274674
2634 22:58:57.274781
2635 22:58:57.274889 TX Vref Scan disable
2636 22:58:57.278132 == TX Byte 0 ==
2637 22:58:57.281624 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2638 22:58:57.287928 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2639 22:58:57.288067 == TX Byte 1 ==
2640 22:58:57.291783 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2641 22:58:57.297940 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2642 22:58:57.298083 ==
2643 22:58:57.301730 Dram Type= 6, Freq= 0, CH_0, rank 0
2644 22:58:57.304758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2645 22:58:57.304879 ==
2646 22:58:57.316215 TX Vref=22, minBit 1, minWin=25, winSum=419
2647 22:58:57.319229 TX Vref=24, minBit 7, minWin=24, winSum=420
2648 22:58:57.322923 TX Vref=26, minBit 5, minWin=25, winSum=425
2649 22:58:57.326119 TX Vref=28, minBit 5, minWin=25, winSum=428
2650 22:58:57.329704 TX Vref=30, minBit 1, minWin=26, winSum=432
2651 22:58:57.332745 TX Vref=32, minBit 0, minWin=26, winSum=430
2652 22:58:57.339483 [TxChooseVref] Worse bit 1, Min win 26, Win sum 432, Final Vref 30
2653 22:58:57.339638
2654 22:58:57.342739 Final TX Range 1 Vref 30
2655 22:58:57.342884
2656 22:58:57.342983 ==
2657 22:58:57.346606 Dram Type= 6, Freq= 0, CH_0, rank 0
2658 22:58:57.349813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2659 22:58:57.349934 ==
2660 22:58:57.350037
2661 22:58:57.353020
2662 22:58:57.353136 TX Vref Scan disable
2663 22:58:57.356250 == TX Byte 0 ==
2664 22:58:57.359130 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2665 22:58:57.362924 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2666 22:58:57.366022 == TX Byte 1 ==
2667 22:58:57.369146 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2668 22:58:57.372764 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2669 22:58:57.372883
2670 22:58:57.375986 [DATLAT]
2671 22:58:57.376102 Freq=1200, CH0 RK0
2672 22:58:57.376208
2673 22:58:57.379196 DATLAT Default: 0xd
2674 22:58:57.379304 0, 0xFFFF, sum = 0
2675 22:58:57.382821 1, 0xFFFF, sum = 0
2676 22:58:57.382931 2, 0xFFFF, sum = 0
2677 22:58:57.385848 3, 0xFFFF, sum = 0
2678 22:58:57.385960 4, 0xFFFF, sum = 0
2679 22:58:57.389599 5, 0xFFFF, sum = 0
2680 22:58:57.389706 6, 0xFFFF, sum = 0
2681 22:58:57.392758 7, 0xFFFF, sum = 0
2682 22:58:57.392866 8, 0xFFFF, sum = 0
2683 22:58:57.395985 9, 0xFFFF, sum = 0
2684 22:58:57.399673 10, 0xFFFF, sum = 0
2685 22:58:57.399790 11, 0xFFFF, sum = 0
2686 22:58:57.402838 12, 0x0, sum = 1
2687 22:58:57.402954 13, 0x0, sum = 2
2688 22:58:57.403053 14, 0x0, sum = 3
2689 22:58:57.406019 15, 0x0, sum = 4
2690 22:58:57.406107 best_step = 13
2691 22:58:57.406175
2692 22:58:57.409200 ==
2693 22:58:57.409287 Dram Type= 6, Freq= 0, CH_0, rank 0
2694 22:58:57.415817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2695 22:58:57.415913 ==
2696 22:58:57.416029 RX Vref Scan: 1
2697 22:58:57.416126
2698 22:58:57.419454 Set Vref Range= 32 -> 127
2699 22:58:57.419546
2700 22:58:57.422508 RX Vref 32 -> 127, step: 1
2701 22:58:57.422594
2702 22:58:57.425985 RX Delay -21 -> 252, step: 4
2703 22:58:57.426080
2704 22:58:57.429160 Set Vref, RX VrefLevel [Byte0]: 32
2705 22:58:57.432785 [Byte1]: 32
2706 22:58:57.432904
2707 22:58:57.436265 Set Vref, RX VrefLevel [Byte0]: 33
2708 22:58:57.439324 [Byte1]: 33
2709 22:58:57.439464
2710 22:58:57.442412 Set Vref, RX VrefLevel [Byte0]: 34
2711 22:58:57.445599 [Byte1]: 34
2712 22:58:57.449954
2713 22:58:57.450058 Set Vref, RX VrefLevel [Byte0]: 35
2714 22:58:57.453233 [Byte1]: 35
2715 22:58:57.458064
2716 22:58:57.458156 Set Vref, RX VrefLevel [Byte0]: 36
2717 22:58:57.461258 [Byte1]: 36
2718 22:58:57.466366
2719 22:58:57.466492 Set Vref, RX VrefLevel [Byte0]: 37
2720 22:58:57.469421 [Byte1]: 37
2721 22:58:57.474207
2722 22:58:57.474332 Set Vref, RX VrefLevel [Byte0]: 38
2723 22:58:57.477228 [Byte1]: 38
2724 22:58:57.481596
2725 22:58:57.481737 Set Vref, RX VrefLevel [Byte0]: 39
2726 22:58:57.485381 [Byte1]: 39
2727 22:58:57.489687
2728 22:58:57.489788 Set Vref, RX VrefLevel [Byte0]: 40
2729 22:58:57.493365 [Byte1]: 40
2730 22:58:57.497717
2731 22:58:57.497809 Set Vref, RX VrefLevel [Byte0]: 41
2732 22:58:57.500852 [Byte1]: 41
2733 22:58:57.505790
2734 22:58:57.505905 Set Vref, RX VrefLevel [Byte0]: 42
2735 22:58:57.508907 [Byte1]: 42
2736 22:58:57.513368
2737 22:58:57.513487 Set Vref, RX VrefLevel [Byte0]: 43
2738 22:58:57.517025 [Byte1]: 43
2739 22:58:57.521915
2740 22:58:57.522038 Set Vref, RX VrefLevel [Byte0]: 44
2741 22:58:57.524796 [Byte1]: 44
2742 22:58:57.529125
2743 22:58:57.529253 Set Vref, RX VrefLevel [Byte0]: 45
2744 22:58:57.532792 [Byte1]: 45
2745 22:58:57.537055
2746 22:58:57.537186 Set Vref, RX VrefLevel [Byte0]: 46
2747 22:58:57.540600 [Byte1]: 46
2748 22:58:57.545588
2749 22:58:57.545705 Set Vref, RX VrefLevel [Byte0]: 47
2750 22:58:57.548751 [Byte1]: 47
2751 22:58:57.553003
2752 22:58:57.553097 Set Vref, RX VrefLevel [Byte0]: 48
2753 22:58:57.556874 [Byte1]: 48
2754 22:58:57.561197
2755 22:58:57.561286 Set Vref, RX VrefLevel [Byte0]: 49
2756 22:58:57.564523 [Byte1]: 49
2757 22:58:57.568844
2758 22:58:57.568933 Set Vref, RX VrefLevel [Byte0]: 50
2759 22:58:57.572626 [Byte1]: 50
2760 22:58:57.577220
2761 22:58:57.577351 Set Vref, RX VrefLevel [Byte0]: 51
2762 22:58:57.580159 [Byte1]: 51
2763 22:58:57.584728
2764 22:58:57.584817 Set Vref, RX VrefLevel [Byte0]: 52
2765 22:58:57.588572 [Byte1]: 52
2766 22:58:57.592780
2767 22:58:57.592869 Set Vref, RX VrefLevel [Byte0]: 53
2768 22:58:57.595930 [Byte1]: 53
2769 22:58:57.600935
2770 22:58:57.601068 Set Vref, RX VrefLevel [Byte0]: 54
2771 22:58:57.604159 [Byte1]: 54
2772 22:58:57.608381
2773 22:58:57.608483 Set Vref, RX VrefLevel [Byte0]: 55
2774 22:58:57.612277 [Byte1]: 55
2775 22:58:57.616743
2776 22:58:57.616882 Set Vref, RX VrefLevel [Byte0]: 56
2777 22:58:57.620175 [Byte1]: 56
2778 22:58:57.624501
2779 22:58:57.624640 Set Vref, RX VrefLevel [Byte0]: 57
2780 22:58:57.628114 [Byte1]: 57
2781 22:58:57.632270
2782 22:58:57.632406 Set Vref, RX VrefLevel [Byte0]: 58
2783 22:58:57.635980 [Byte1]: 58
2784 22:58:57.640235
2785 22:58:57.640361 Set Vref, RX VrefLevel [Byte0]: 59
2786 22:58:57.643386 [Byte1]: 59
2787 22:58:57.648260
2788 22:58:57.648380 Set Vref, RX VrefLevel [Byte0]: 60
2789 22:58:57.651469 [Byte1]: 60
2790 22:58:57.656393
2791 22:58:57.656507 Set Vref, RX VrefLevel [Byte0]: 61
2792 22:58:57.659511 [Byte1]: 61
2793 22:58:57.663998
2794 22:58:57.664118 Set Vref, RX VrefLevel [Byte0]: 62
2795 22:58:57.667795 [Byte1]: 62
2796 22:58:57.672319
2797 22:58:57.672468 Set Vref, RX VrefLevel [Byte0]: 63
2798 22:58:57.675491 [Byte1]: 63
2799 22:58:57.680278
2800 22:58:57.680412 Set Vref, RX VrefLevel [Byte0]: 64
2801 22:58:57.683448 [Byte1]: 64
2802 22:58:57.687754
2803 22:58:57.687873 Set Vref, RX VrefLevel [Byte0]: 65
2804 22:58:57.691411 [Byte1]: 65
2805 22:58:57.695597
2806 22:58:57.695690 Set Vref, RX VrefLevel [Byte0]: 66
2807 22:58:57.698840 [Byte1]: 66
2808 22:58:57.703649
2809 22:58:57.703775 Set Vref, RX VrefLevel [Byte0]: 67
2810 22:58:57.706812 [Byte1]: 67
2811 22:58:57.711372
2812 22:58:57.711494 Set Vref, RX VrefLevel [Byte0]: 68
2813 22:58:57.715145 [Byte1]: 68
2814 22:58:57.719395
2815 22:58:57.719524 Set Vref, RX VrefLevel [Byte0]: 69
2816 22:58:57.723240 [Byte1]: 69
2817 22:58:57.727292
2818 22:58:57.727415 Final RX Vref Byte 0 = 52 to rank0
2819 22:58:57.730995 Final RX Vref Byte 1 = 50 to rank0
2820 22:58:57.734395 Final RX Vref Byte 0 = 52 to rank1
2821 22:58:57.737561 Final RX Vref Byte 1 = 50 to rank1==
2822 22:58:57.740644 Dram Type= 6, Freq= 0, CH_0, rank 0
2823 22:58:57.747395 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2824 22:58:57.747515 ==
2825 22:58:57.747590 DQS Delay:
2826 22:58:57.747671 DQS0 = 0, DQS1 = 0
2827 22:58:57.751087 DQM Delay:
2828 22:58:57.751204 DQM0 = 114, DQM1 = 105
2829 22:58:57.754323 DQ Delay:
2830 22:58:57.757490 DQ0 =112, DQ1 =114, DQ2 =112, DQ3 =112
2831 22:58:57.761254 DQ4 =116, DQ5 =108, DQ6 =120, DQ7 =122
2832 22:58:57.764472 DQ8 =92, DQ9 =90, DQ10 =104, DQ11 =98
2833 22:58:57.767535 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114
2834 22:58:57.767661
2835 22:58:57.767787
2836 22:58:57.774453 [DQSOSCAuto] RK0, (LSB)MR18= 0x1f0, (MSB)MR19= 0x403, tDQSOscB0 = 416 ps tDQSOscB1 = 409 ps
2837 22:58:57.777520 CH0 RK0: MR19=403, MR18=1F0
2838 22:58:57.784492 CH0_RK0: MR19=0x403, MR18=0x1F0, DQSOSC=409, MR23=63, INC=39, DEC=26
2839 22:58:57.784610
2840 22:58:57.787418 ----->DramcWriteLeveling(PI) begin...
2841 22:58:57.787504 ==
2842 22:58:57.791074 Dram Type= 6, Freq= 0, CH_0, rank 1
2843 22:58:57.794196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2844 22:58:57.794297 ==
2845 22:58:57.797968 Write leveling (Byte 0): 32 => 32
2846 22:58:57.800869 Write leveling (Byte 1): 29 => 29
2847 22:58:57.804553 DramcWriteLeveling(PI) end<-----
2848 22:58:57.804640
2849 22:58:57.804742 ==
2850 22:58:57.807618 Dram Type= 6, Freq= 0, CH_0, rank 1
2851 22:58:57.810984 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2852 22:58:57.813953 ==
2853 22:58:57.814084 [Gating] SW mode calibration
2854 22:58:57.821165 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2855 22:58:57.827510 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2856 22:58:57.830984 0 15 0 | B1->B0 | 2323 2727 | 0 0 | (0 0) (1 1)
2857 22:58:57.837788 0 15 4 | B1->B0 | 2d2d 3434 | 1 1 | (1 1) (1 1)
2858 22:58:57.840786 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2859 22:58:57.844286 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2860 22:58:57.851047 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2861 22:58:57.853970 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2862 22:58:57.857671 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2863 22:58:57.864539 0 15 28 | B1->B0 | 3434 2727 | 1 0 | (1 1) (1 0)
2864 22:58:57.867676 1 0 0 | B1->B0 | 2d2d 2424 | 0 0 | (0 0) (0 0)
2865 22:58:57.870709 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2866 22:58:57.877696 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2867 22:58:57.880943 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2868 22:58:57.884361 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2869 22:58:57.887593 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2870 22:58:57.894207 1 0 24 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (0 0)
2871 22:58:57.897993 1 0 28 | B1->B0 | 2323 4141 | 0 0 | (0 0) (0 0)
2872 22:58:57.901189 1 1 0 | B1->B0 | 3333 4343 | 1 0 | (1 1) (0 0)
2873 22:58:57.907651 1 1 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
2874 22:58:57.911231 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2875 22:58:57.914424 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2876 22:58:57.920777 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2877 22:58:57.924472 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2878 22:58:57.927735 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2879 22:58:57.934601 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2880 22:58:57.937594 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2881 22:58:57.941180 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2882 22:58:57.947681 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2883 22:58:57.951224 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 22:58:57.954181 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 22:58:57.961380 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 22:58:57.964552 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 22:58:57.967782 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 22:58:57.970961 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2889 22:58:57.977804 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2890 22:58:57.980972 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2891 22:58:57.984254 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2892 22:58:57.991325 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2893 22:58:57.994520 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2894 22:58:57.998062 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2895 22:58:58.004244 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2896 22:58:58.007509 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2897 22:58:58.011126 Total UI for P1: 0, mck2ui 16
2898 22:58:58.014203 best dqsien dly found for B0: ( 1, 3, 28)
2899 22:58:58.017798 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2900 22:58:58.020981 Total UI for P1: 0, mck2ui 16
2901 22:58:58.024738 best dqsien dly found for B1: ( 1, 4, 0)
2902 22:58:58.027801 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2903 22:58:58.031058 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2904 22:58:58.031171
2905 22:58:58.034244 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2906 22:58:58.041117 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2907 22:58:58.041255 [Gating] SW calibration Done
2908 22:58:58.041365 ==
2909 22:58:58.044289 Dram Type= 6, Freq= 0, CH_0, rank 1
2910 22:58:58.051270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2911 22:58:58.051409 ==
2912 22:58:58.051521 RX Vref Scan: 0
2913 22:58:58.051625
2914 22:58:58.054234 RX Vref 0 -> 0, step: 1
2915 22:58:58.054321
2916 22:58:58.057920 RX Delay -40 -> 252, step: 8
2917 22:58:58.060944 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2918 22:58:58.064367 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2919 22:58:58.067384 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2920 22:58:58.074439 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2921 22:58:58.077594 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2922 22:58:58.080636 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2923 22:58:58.084455 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2924 22:58:58.087674 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2925 22:58:58.094388 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2926 22:58:58.097407 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2927 22:58:58.100995 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2928 22:58:58.104122 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2929 22:58:58.107876 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2930 22:58:58.114226 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2931 22:58:58.117443 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2932 22:58:58.120944 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2933 22:58:58.121063 ==
2934 22:58:58.123906 Dram Type= 6, Freq= 0, CH_0, rank 1
2935 22:58:58.127729 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2936 22:58:58.127853 ==
2937 22:58:58.130816 DQS Delay:
2938 22:58:58.130929 DQS0 = 0, DQS1 = 0
2939 22:58:58.131027 DQM Delay:
2940 22:58:58.134619 DQM0 = 115, DQM1 = 105
2941 22:58:58.134750 DQ Delay:
2942 22:58:58.137729 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =115
2943 22:58:58.140818 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2944 22:58:58.143967 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =99
2945 22:58:58.150710 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2946 22:58:58.150846
2947 22:58:58.150946
2948 22:58:58.151056 ==
2949 22:58:58.154128 Dram Type= 6, Freq= 0, CH_0, rank 1
2950 22:58:58.157561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2951 22:58:58.157678 ==
2952 22:58:58.157778
2953 22:58:58.157874
2954 22:58:58.160561 TX Vref Scan disable
2955 22:58:58.160676 == TX Byte 0 ==
2956 22:58:58.167756 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2957 22:58:58.170713 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2958 22:58:58.170848 == TX Byte 1 ==
2959 22:58:58.177468 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2960 22:58:58.181324 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2961 22:58:58.181438 ==
2962 22:58:58.184365 Dram Type= 6, Freq= 0, CH_0, rank 1
2963 22:58:58.187447 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2964 22:58:58.187579 ==
2965 22:58:58.200599 TX Vref=22, minBit 0, minWin=25, winSum=423
2966 22:58:58.203744 TX Vref=24, minBit 12, minWin=25, winSum=427
2967 22:58:58.207254 TX Vref=26, minBit 0, minWin=26, winSum=433
2968 22:58:58.210351 TX Vref=28, minBit 12, minWin=26, winSum=435
2969 22:58:58.213948 TX Vref=30, minBit 3, minWin=26, winSum=436
2970 22:58:58.220402 TX Vref=32, minBit 12, minWin=26, winSum=437
2971 22:58:58.223935 [TxChooseVref] Worse bit 12, Min win 26, Win sum 437, Final Vref 32
2972 22:58:58.224070
2973 22:58:58.226890 Final TX Range 1 Vref 32
2974 22:58:58.227004
2975 22:58:58.227121 ==
2976 22:58:58.230116 Dram Type= 6, Freq= 0, CH_0, rank 1
2977 22:58:58.233890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2978 22:58:58.237065 ==
2979 22:58:58.237181
2980 22:58:58.237301
2981 22:58:58.237395 TX Vref Scan disable
2982 22:58:58.240802 == TX Byte 0 ==
2983 22:58:58.243856 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2984 22:58:58.250773 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2985 22:58:58.250864 == TX Byte 1 ==
2986 22:58:58.253919 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2987 22:58:58.257081 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2988 22:58:58.260578
2989 22:58:58.260660 [DATLAT]
2990 22:58:58.260740 Freq=1200, CH0 RK1
2991 22:58:58.260808
2992 22:58:58.264038 DATLAT Default: 0xd
2993 22:58:58.264123 0, 0xFFFF, sum = 0
2994 22:58:58.267102 1, 0xFFFF, sum = 0
2995 22:58:58.267214 2, 0xFFFF, sum = 0
2996 22:58:58.270430 3, 0xFFFF, sum = 0
2997 22:58:58.270527 4, 0xFFFF, sum = 0
2998 22:58:58.273964 5, 0xFFFF, sum = 0
2999 22:58:58.277458 6, 0xFFFF, sum = 0
3000 22:58:58.277554 7, 0xFFFF, sum = 0
3001 22:58:58.280976 8, 0xFFFF, sum = 0
3002 22:58:58.281091 9, 0xFFFF, sum = 0
3003 22:58:58.283794 10, 0xFFFF, sum = 0
3004 22:58:58.283888 11, 0xFFFF, sum = 0
3005 22:58:58.286989 12, 0x0, sum = 1
3006 22:58:58.287080 13, 0x0, sum = 2
3007 22:58:58.290796 14, 0x0, sum = 3
3008 22:58:58.290887 15, 0x0, sum = 4
3009 22:58:58.290977 best_step = 13
3010 22:58:58.293978
3011 22:58:58.294068 ==
3012 22:58:58.297191 Dram Type= 6, Freq= 0, CH_0, rank 1
3013 22:58:58.300306 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3014 22:58:58.300397 ==
3015 22:58:58.300486 RX Vref Scan: 0
3016 22:58:58.300571
3017 22:58:58.303844 RX Vref 0 -> 0, step: 1
3018 22:58:58.303934
3019 22:58:58.306935 RX Delay -21 -> 252, step: 4
3020 22:58:58.310518 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3021 22:58:58.317125 iDelay=195, Bit 1, Center 114 (43 ~ 186) 144
3022 22:58:58.320222 iDelay=195, Bit 2, Center 110 (39 ~ 182) 144
3023 22:58:58.323979 iDelay=195, Bit 3, Center 114 (43 ~ 186) 144
3024 22:58:58.327025 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3025 22:58:58.330123 iDelay=195, Bit 5, Center 104 (35 ~ 174) 140
3026 22:58:58.337026 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3027 22:58:58.340272 iDelay=195, Bit 7, Center 122 (51 ~ 194) 144
3028 22:58:58.343483 iDelay=195, Bit 8, Center 94 (27 ~ 162) 136
3029 22:58:58.347133 iDelay=195, Bit 9, Center 92 (23 ~ 162) 140
3030 22:58:58.350400 iDelay=195, Bit 10, Center 106 (39 ~ 174) 136
3031 22:58:58.356686 iDelay=195, Bit 11, Center 94 (27 ~ 162) 136
3032 22:58:58.360572 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3033 22:58:58.363510 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3034 22:58:58.366707 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3035 22:58:58.370191 iDelay=195, Bit 15, Center 114 (47 ~ 182) 136
3036 22:58:58.370324 ==
3037 22:58:58.373524 Dram Type= 6, Freq= 0, CH_0, rank 1
3038 22:58:58.380196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3039 22:58:58.380351 ==
3040 22:58:58.380474 DQS Delay:
3041 22:58:58.383751 DQS0 = 0, DQS1 = 0
3042 22:58:58.383861 DQM Delay:
3043 22:58:58.386747 DQM0 = 114, DQM1 = 104
3044 22:58:58.386861 DQ Delay:
3045 22:58:58.390377 DQ0 =114, DQ1 =114, DQ2 =110, DQ3 =114
3046 22:58:58.393395 DQ4 =112, DQ5 =104, DQ6 =122, DQ7 =122
3047 22:58:58.397096 DQ8 =94, DQ9 =92, DQ10 =106, DQ11 =94
3048 22:58:58.400291 DQ12 =110, DQ13 =110, DQ14 =116, DQ15 =114
3049 22:58:58.400412
3050 22:58:58.400530
3051 22:58:58.410304 [DQSOSCAuto] RK1, (LSB)MR18= 0xfff0, (MSB)MR19= 0x303, tDQSOscB0 = 416 ps tDQSOscB1 = 410 ps
3052 22:58:58.410439 CH0 RK1: MR19=303, MR18=FFF0
3053 22:58:58.416797 CH0_RK1: MR19=0x303, MR18=0xFFF0, DQSOSC=410, MR23=63, INC=39, DEC=26
3054 22:58:58.420315 [RxdqsGatingPostProcess] freq 1200
3055 22:58:58.426631 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3056 22:58:58.430402 best DQS0 dly(2T, 0.5T) = (0, 12)
3057 22:58:58.433401 best DQS1 dly(2T, 0.5T) = (0, 12)
3058 22:58:58.437113 best DQS0 P1 dly(2T, 0.5T) = (1, 0)
3059 22:58:58.440282 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3060 22:58:58.440401 best DQS0 dly(2T, 0.5T) = (0, 11)
3061 22:58:58.443451 best DQS1 dly(2T, 0.5T) = (0, 12)
3062 22:58:58.447134 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3063 22:58:58.450272 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3064 22:58:58.453294 Pre-setting of DQS Precalculation
3065 22:58:58.460287 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3066 22:58:58.460419 ==
3067 22:58:58.463436 Dram Type= 6, Freq= 0, CH_1, rank 0
3068 22:58:58.466652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3069 22:58:58.466770 ==
3070 22:58:58.473413 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3071 22:58:58.476895 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3072 22:58:58.486513 [CA 0] Center 38 (9~68) winsize 60
3073 22:58:58.490236 [CA 1] Center 38 (8~68) winsize 61
3074 22:58:58.493236 [CA 2] Center 35 (5~65) winsize 61
3075 22:58:58.496854 [CA 3] Center 34 (3~65) winsize 63
3076 22:58:58.500215 [CA 4] Center 34 (4~65) winsize 62
3077 22:58:58.503392 [CA 5] Center 34 (4~64) winsize 61
3078 22:58:58.503519
3079 22:58:58.506698 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3080 22:58:58.506806
3081 22:58:58.510164 [CATrainingPosCal] consider 1 rank data
3082 22:58:58.513175 u2DelayCellTimex100 = 270/100 ps
3083 22:58:58.516830 CA0 delay=38 (9~68),Diff = 4 PI (19 cell)
3084 22:58:58.519979 CA1 delay=38 (8~68),Diff = 4 PI (19 cell)
3085 22:58:58.526735 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3086 22:58:58.529808 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
3087 22:58:58.533691 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3088 22:58:58.536901 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3089 22:58:58.537020
3090 22:58:58.539979 CA PerBit enable=1, Macro0, CA PI delay=34
3091 22:58:58.540109
3092 22:58:58.543118 [CBTSetCACLKResult] CA Dly = 34
3093 22:58:58.543241 CS Dly: 6 (0~37)
3094 22:58:58.543337 ==
3095 22:58:58.546846 Dram Type= 6, Freq= 0, CH_1, rank 1
3096 22:58:58.553330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3097 22:58:58.553459 ==
3098 22:58:58.556934 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3099 22:58:58.563229 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3100 22:58:58.571971 [CA 0] Center 38 (8~68) winsize 61
3101 22:58:58.575562 [CA 1] Center 38 (8~68) winsize 61
3102 22:58:58.579179 [CA 2] Center 34 (4~65) winsize 62
3103 22:58:58.582309 [CA 3] Center 34 (4~65) winsize 62
3104 22:58:58.585417 [CA 4] Center 34 (4~65) winsize 62
3105 22:58:58.588963 [CA 5] Center 33 (3~63) winsize 61
3106 22:58:58.589175
3107 22:58:58.592097 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3108 22:58:58.592267
3109 22:58:58.595547 [CATrainingPosCal] consider 2 rank data
3110 22:58:58.598968 u2DelayCellTimex100 = 270/100 ps
3111 22:58:58.602015 CA0 delay=38 (9~68),Diff = 5 PI (24 cell)
3112 22:58:58.605631 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3113 22:58:58.612212 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3114 22:58:58.615375 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3115 22:58:58.618493 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3116 22:58:58.622314 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3117 22:58:58.622480
3118 22:58:58.625365 CA PerBit enable=1, Macro0, CA PI delay=33
3119 22:58:58.625530
3120 22:58:58.628984 [CBTSetCACLKResult] CA Dly = 33
3121 22:58:58.629146 CS Dly: 7 (0~40)
3122 22:58:58.629294
3123 22:58:58.632016 ----->DramcWriteLeveling(PI) begin...
3124 22:58:58.635881 ==
3125 22:58:58.636046 Dram Type= 6, Freq= 0, CH_1, rank 0
3126 22:58:58.641962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3127 22:58:58.642138 ==
3128 22:58:58.645566 Write leveling (Byte 0): 27 => 27
3129 22:58:58.648713 Write leveling (Byte 1): 29 => 29
3130 22:58:58.652597 DramcWriteLeveling(PI) end<-----
3131 22:58:58.652759
3132 22:58:58.652908 ==
3133 22:58:58.655640 Dram Type= 6, Freq= 0, CH_1, rank 0
3134 22:58:58.658866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3135 22:58:58.659025 ==
3136 22:58:58.662615 [Gating] SW mode calibration
3137 22:58:58.668840 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3138 22:58:58.672066 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3139 22:58:58.678992 0 15 0 | B1->B0 | 2727 2525 | 0 1 | (0 0) (1 1)
3140 22:58:58.681989 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3141 22:58:58.685786 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3142 22:58:58.691841 0 15 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3143 22:58:58.695480 0 15 16 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3144 22:58:58.699018 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3145 22:58:58.705586 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3146 22:58:58.708639 0 15 28 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 0)
3147 22:58:58.712133 1 0 0 | B1->B0 | 2424 2626 | 0 0 | (1 0) (0 0)
3148 22:58:58.718766 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3149 22:58:58.722721 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3150 22:58:58.725327 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3151 22:58:58.732119 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3152 22:58:58.735229 1 0 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3153 22:58:58.738832 1 0 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3154 22:58:58.745705 1 0 28 | B1->B0 | 2b2b 2525 | 1 0 | (0 0) (0 0)
3155 22:58:58.748745 1 1 0 | B1->B0 | 4141 3434 | 0 0 | (0 0) (0 0)
3156 22:58:58.752557 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3157 22:58:58.755788 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3158 22:58:58.762179 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3159 22:58:58.765927 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3160 22:58:58.768988 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3161 22:58:58.775319 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3162 22:58:58.779154 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3163 22:58:58.782233 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3164 22:58:58.789055 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3165 22:58:58.792228 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3166 22:58:58.795455 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 22:58:58.801974 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 22:58:58.805603 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 22:58:58.808697 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 22:58:58.815178 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 22:58:58.818886 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3172 22:58:58.821924 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3173 22:58:58.828641 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3174 22:58:58.832205 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3175 22:58:58.835426 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3176 22:58:58.841804 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3177 22:58:58.845552 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3178 22:58:58.848668 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3179 22:58:58.855548 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3180 22:58:58.855645 Total UI for P1: 0, mck2ui 16
3181 22:58:58.858588 best dqsien dly found for B0: ( 1, 3, 28)
3182 22:58:58.862388 Total UI for P1: 0, mck2ui 16
3183 22:58:58.865524 best dqsien dly found for B1: ( 1, 3, 28)
3184 22:58:58.868752 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3185 22:58:58.875654 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3186 22:58:58.875751
3187 22:58:58.878837 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3188 22:58:58.882024 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3189 22:58:58.885172 [Gating] SW calibration Done
3190 22:58:58.885287 ==
3191 22:58:58.888940 Dram Type= 6, Freq= 0, CH_1, rank 0
3192 22:58:58.892105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3193 22:58:58.892186 ==
3194 22:58:58.892264 RX Vref Scan: 0
3195 22:58:58.895250
3196 22:58:58.895366 RX Vref 0 -> 0, step: 1
3197 22:58:58.895434
3198 22:58:58.898834 RX Delay -40 -> 252, step: 8
3199 22:58:58.902117 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3200 22:58:58.905475 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3201 22:58:58.912106 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3202 22:58:58.915084 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3203 22:58:58.918697 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3204 22:58:58.921728 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3205 22:58:58.925278 iDelay=200, Bit 6, Center 127 (64 ~ 191) 128
3206 22:58:58.932135 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3207 22:58:58.935063 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3208 22:58:58.938801 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3209 22:58:58.941845 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3210 22:58:58.945323 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3211 22:58:58.952305 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3212 22:58:58.955264 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
3213 22:58:58.958469 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3214 22:58:58.961574 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3215 22:58:58.961683 ==
3216 22:58:58.965368 Dram Type= 6, Freq= 0, CH_1, rank 0
3217 22:58:58.971656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3218 22:58:58.971778 ==
3219 22:58:58.971881 DQS Delay:
3220 22:58:58.971980 DQS0 = 0, DQS1 = 0
3221 22:58:58.975428 DQM Delay:
3222 22:58:58.975541 DQM0 = 116, DQM1 = 109
3223 22:58:58.978717 DQ Delay:
3224 22:58:58.981760 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =119
3225 22:58:58.984808 DQ4 =111, DQ5 =127, DQ6 =127, DQ7 =115
3226 22:58:58.988624 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =107
3227 22:58:58.991722 DQ12 =119, DQ13 =115, DQ14 =115, DQ15 =115
3228 22:58:58.991805
3229 22:58:58.991873
3230 22:58:58.991952 ==
3231 22:58:58.994824 Dram Type= 6, Freq= 0, CH_1, rank 0
3232 22:58:58.998571 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3233 22:58:58.998690 ==
3234 22:58:59.001665
3235 22:58:59.001791
3236 22:58:59.001899 TX Vref Scan disable
3237 22:58:59.005325 == TX Byte 0 ==
3238 22:58:59.008456 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3239 22:58:59.012000 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3240 22:58:59.014951 == TX Byte 1 ==
3241 22:58:59.018689 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3242 22:58:59.021852 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3243 22:58:59.021964 ==
3244 22:58:59.024850 Dram Type= 6, Freq= 0, CH_1, rank 0
3245 22:58:59.031851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3246 22:58:59.031971 ==
3247 22:58:59.042315 TX Vref=22, minBit 1, minWin=24, winSum=410
3248 22:58:59.045319 TX Vref=24, minBit 4, minWin=25, winSum=415
3249 22:58:59.049032 TX Vref=26, minBit 1, minWin=26, winSum=427
3250 22:58:59.052150 TX Vref=28, minBit 1, minWin=26, winSum=428
3251 22:58:59.055402 TX Vref=30, minBit 3, minWin=26, winSum=429
3252 22:58:59.062144 TX Vref=32, minBit 2, minWin=26, winSum=426
3253 22:58:59.065340 [TxChooseVref] Worse bit 3, Min win 26, Win sum 429, Final Vref 30
3254 22:58:59.065481
3255 22:58:59.069138 Final TX Range 1 Vref 30
3256 22:58:59.069297
3257 22:58:59.069409 ==
3258 22:58:59.072219 Dram Type= 6, Freq= 0, CH_1, rank 0
3259 22:58:59.075438 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3260 22:58:59.075568 ==
3261 22:58:59.078631
3262 22:58:59.078746
3263 22:58:59.078850 TX Vref Scan disable
3264 22:58:59.081919 == TX Byte 0 ==
3265 22:58:59.084967 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3266 22:58:59.088724 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3267 22:58:59.091872 == TX Byte 1 ==
3268 22:58:59.095676 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3269 22:58:59.098828 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3270 22:58:59.102003
3271 22:58:59.102116 [DATLAT]
3272 22:58:59.102238 Freq=1200, CH1 RK0
3273 22:58:59.102350
3274 22:58:59.105155 DATLAT Default: 0xd
3275 22:58:59.105277 0, 0xFFFF, sum = 0
3276 22:58:59.108905 1, 0xFFFF, sum = 0
3277 22:58:59.109029 2, 0xFFFF, sum = 0
3278 22:58:59.111865 3, 0xFFFF, sum = 0
3279 22:58:59.111986 4, 0xFFFF, sum = 0
3280 22:58:59.115501 5, 0xFFFF, sum = 0
3281 22:58:59.118503 6, 0xFFFF, sum = 0
3282 22:58:59.118613 7, 0xFFFF, sum = 0
3283 22:58:59.122102 8, 0xFFFF, sum = 0
3284 22:58:59.122216 9, 0xFFFF, sum = 0
3285 22:58:59.125209 10, 0xFFFF, sum = 0
3286 22:58:59.125328 11, 0xFFFF, sum = 0
3287 22:58:59.128331 12, 0x0, sum = 1
3288 22:58:59.128446 13, 0x0, sum = 2
3289 22:58:59.131887 14, 0x0, sum = 3
3290 22:58:59.132003 15, 0x0, sum = 4
3291 22:58:59.132105 best_step = 13
3292 22:58:59.132206
3293 22:58:59.135418 ==
3294 22:58:59.138464 Dram Type= 6, Freq= 0, CH_1, rank 0
3295 22:58:59.142292 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3296 22:58:59.142414 ==
3297 22:58:59.142532 RX Vref Scan: 1
3298 22:58:59.142628
3299 22:58:59.145117 Set Vref Range= 32 -> 127
3300 22:58:59.145226
3301 22:58:59.148714 RX Vref 32 -> 127, step: 1
3302 22:58:59.148844
3303 22:58:59.151882 RX Delay -21 -> 252, step: 4
3304 22:58:59.151995
3305 22:58:59.155326 Set Vref, RX VrefLevel [Byte0]: 32
3306 22:58:59.158629 [Byte1]: 32
3307 22:58:59.158751
3308 22:58:59.161596 Set Vref, RX VrefLevel [Byte0]: 33
3309 22:58:59.165303 [Byte1]: 33
3310 22:58:59.168555
3311 22:58:59.168676 Set Vref, RX VrefLevel [Byte0]: 34
3312 22:58:59.174807 [Byte1]: 34
3313 22:58:59.174916
3314 22:58:59.178007 Set Vref, RX VrefLevel [Byte0]: 35
3315 22:58:59.181806 [Byte1]: 35
3316 22:58:59.181921
3317 22:58:59.185102 Set Vref, RX VrefLevel [Byte0]: 36
3318 22:58:59.188313 [Byte1]: 36
3319 22:58:59.192043
3320 22:58:59.192153 Set Vref, RX VrefLevel [Byte0]: 37
3321 22:58:59.195307 [Byte1]: 37
3322 22:58:59.200241
3323 22:58:59.200348 Set Vref, RX VrefLevel [Byte0]: 38
3324 22:58:59.203425 [Byte1]: 38
3325 22:58:59.207827
3326 22:58:59.207912 Set Vref, RX VrefLevel [Byte0]: 39
3327 22:58:59.211561 [Byte1]: 39
3328 22:58:59.215936
3329 22:58:59.216072 Set Vref, RX VrefLevel [Byte0]: 40
3330 22:58:59.219412 [Byte1]: 40
3331 22:58:59.223707
3332 22:58:59.223834 Set Vref, RX VrefLevel [Byte0]: 41
3333 22:58:59.227280 [Byte1]: 41
3334 22:58:59.231530
3335 22:58:59.231645 Set Vref, RX VrefLevel [Byte0]: 42
3336 22:58:59.235035 [Byte1]: 42
3337 22:58:59.239774
3338 22:58:59.239900 Set Vref, RX VrefLevel [Byte0]: 43
3339 22:58:59.242862 [Byte1]: 43
3340 22:58:59.247647
3341 22:58:59.247732 Set Vref, RX VrefLevel [Byte0]: 44
3342 22:58:59.250722 [Byte1]: 44
3343 22:58:59.255630
3344 22:58:59.255743 Set Vref, RX VrefLevel [Byte0]: 45
3345 22:58:59.258716 [Byte1]: 45
3346 22:58:59.263714
3347 22:58:59.263805 Set Vref, RX VrefLevel [Byte0]: 46
3348 22:58:59.266765 [Byte1]: 46
3349 22:58:59.271650
3350 22:58:59.271765 Set Vref, RX VrefLevel [Byte0]: 47
3351 22:58:59.274893 [Byte1]: 47
3352 22:58:59.279383
3353 22:58:59.279463 Set Vref, RX VrefLevel [Byte0]: 48
3354 22:58:59.282488 [Byte1]: 48
3355 22:58:59.287638
3356 22:58:59.287722 Set Vref, RX VrefLevel [Byte0]: 49
3357 22:58:59.290612 [Byte1]: 49
3358 22:58:59.294995
3359 22:58:59.295123 Set Vref, RX VrefLevel [Byte0]: 50
3360 22:58:59.298297 [Byte1]: 50
3361 22:58:59.303218
3362 22:58:59.303339 Set Vref, RX VrefLevel [Byte0]: 51
3363 22:58:59.306421 [Byte1]: 51
3364 22:58:59.310788
3365 22:58:59.310898 Set Vref, RX VrefLevel [Byte0]: 52
3366 22:58:59.313961 [Byte1]: 52
3367 22:58:59.318725
3368 22:58:59.318849 Set Vref, RX VrefLevel [Byte0]: 53
3369 22:58:59.322395 [Byte1]: 53
3370 22:58:59.326806
3371 22:58:59.326916 Set Vref, RX VrefLevel [Byte0]: 54
3372 22:58:59.330052 [Byte1]: 54
3373 22:58:59.334813
3374 22:58:59.334925 Set Vref, RX VrefLevel [Byte0]: 55
3375 22:58:59.338565 [Byte1]: 55
3376 22:58:59.342530
3377 22:58:59.342617 Set Vref, RX VrefLevel [Byte0]: 56
3378 22:58:59.346151 [Byte1]: 56
3379 22:58:59.350345
3380 22:58:59.350447 Set Vref, RX VrefLevel [Byte0]: 57
3381 22:58:59.353856 [Byte1]: 57
3382 22:58:59.358327
3383 22:58:59.358409 Set Vref, RX VrefLevel [Byte0]: 58
3384 22:58:59.361897 [Byte1]: 58
3385 22:58:59.366151
3386 22:58:59.366247 Set Vref, RX VrefLevel [Byte0]: 59
3387 22:58:59.369853 [Byte1]: 59
3388 22:58:59.374120
3389 22:58:59.374255 Set Vref, RX VrefLevel [Byte0]: 60
3390 22:58:59.377352 [Byte1]: 60
3391 22:58:59.382426
3392 22:58:59.382518 Set Vref, RX VrefLevel [Byte0]: 61
3393 22:58:59.385642 [Byte1]: 61
3394 22:58:59.390026
3395 22:58:59.390127 Set Vref, RX VrefLevel [Byte0]: 62
3396 22:58:59.393145 [Byte1]: 62
3397 22:58:59.398102
3398 22:58:59.398185 Set Vref, RX VrefLevel [Byte0]: 63
3399 22:58:59.401394 [Byte1]: 63
3400 22:58:59.405744
3401 22:58:59.405835 Set Vref, RX VrefLevel [Byte0]: 64
3402 22:58:59.409603 [Byte1]: 64
3403 22:58:59.413814
3404 22:58:59.413911 Set Vref, RX VrefLevel [Byte0]: 65
3405 22:58:59.416965 [Byte1]: 65
3406 22:58:59.421923
3407 22:58:59.422042 Set Vref, RX VrefLevel [Byte0]: 66
3408 22:58:59.425109 [Byte1]: 66
3409 22:58:59.429425
3410 22:58:59.429514 Set Vref, RX VrefLevel [Byte0]: 67
3411 22:58:59.433220 [Byte1]: 67
3412 22:58:59.437526
3413 22:58:59.437645 Set Vref, RX VrefLevel [Byte0]: 68
3414 22:58:59.441093 [Byte1]: 68
3415 22:58:59.445308
3416 22:58:59.445422 Set Vref, RX VrefLevel [Byte0]: 69
3417 22:58:59.448963 [Byte1]: 69
3418 22:58:59.453752
3419 22:58:59.453884 Set Vref, RX VrefLevel [Byte0]: 70
3420 22:58:59.456760 [Byte1]: 70
3421 22:58:59.461260
3422 22:58:59.461373 Set Vref, RX VrefLevel [Byte0]: 71
3423 22:58:59.464873 [Byte1]: 71
3424 22:58:59.469117
3425 22:58:59.472301 Final RX Vref Byte 0 = 54 to rank0
3426 22:58:59.472425 Final RX Vref Byte 1 = 51 to rank0
3427 22:58:59.475777 Final RX Vref Byte 0 = 54 to rank1
3428 22:58:59.479006 Final RX Vref Byte 1 = 51 to rank1==
3429 22:58:59.482185 Dram Type= 6, Freq= 0, CH_1, rank 0
3430 22:58:59.489205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3431 22:58:59.489318 ==
3432 22:58:59.489427 DQS Delay:
3433 22:58:59.492411 DQS0 = 0, DQS1 = 0
3434 22:58:59.492524 DQM Delay:
3435 22:58:59.492625 DQM0 = 115, DQM1 = 108
3436 22:58:59.496007 DQ Delay:
3437 22:58:59.499254 DQ0 =116, DQ1 =108, DQ2 =106, DQ3 =114
3438 22:58:59.502519 DQ4 =116, DQ5 =124, DQ6 =128, DQ7 =114
3439 22:58:59.505531 DQ8 =98, DQ9 =98, DQ10 =110, DQ11 =104
3440 22:58:59.509296 DQ12 =116, DQ13 =116, DQ14 =114, DQ15 =114
3441 22:58:59.509410
3442 22:58:59.509511
3443 22:58:59.519206 [DQSOSCAuto] RK0, (LSB)MR18= 0xfce1, (MSB)MR19= 0x303, tDQSOscB0 = 422 ps tDQSOscB1 = 411 ps
3444 22:58:59.519333 CH1 RK0: MR19=303, MR18=FCE1
3445 22:58:59.526006 CH1_RK0: MR19=0x303, MR18=0xFCE1, DQSOSC=411, MR23=63, INC=38, DEC=25
3446 22:58:59.526107
3447 22:58:59.528924 ----->DramcWriteLeveling(PI) begin...
3448 22:58:59.529016 ==
3449 22:58:59.532653 Dram Type= 6, Freq= 0, CH_1, rank 1
3450 22:58:59.535661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3451 22:58:59.538924 ==
3452 22:58:59.542651 Write leveling (Byte 0): 26 => 26
3453 22:58:59.542769 Write leveling (Byte 1): 28 => 28
3454 22:58:59.545596 DramcWriteLeveling(PI) end<-----
3455 22:58:59.545675
3456 22:58:59.545741 ==
3457 22:58:59.549266 Dram Type= 6, Freq= 0, CH_1, rank 1
3458 22:58:59.556081 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3459 22:58:59.556172 ==
3460 22:58:59.559198 [Gating] SW mode calibration
3461 22:58:59.565740 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3462 22:58:59.568866 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3463 22:58:59.575567 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3464 22:58:59.578726 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3465 22:58:59.582327 0 15 8 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3466 22:58:59.588706 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3467 22:58:59.592420 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3468 22:58:59.595571 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3469 22:58:59.598714 0 15 24 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 0)
3470 22:58:59.605589 0 15 28 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
3471 22:58:59.609184 1 0 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3472 22:58:59.612418 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3473 22:58:59.618727 1 0 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3474 22:58:59.622446 1 0 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3475 22:58:59.625527 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3476 22:58:59.632521 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3477 22:58:59.635366 1 0 24 | B1->B0 | 2424 4545 | 0 0 | (0 0) (0 0)
3478 22:58:59.639149 1 0 28 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
3479 22:58:59.645227 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3480 22:58:59.648992 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3481 22:58:59.652168 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3482 22:58:59.658800 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3483 22:58:59.661772 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3484 22:58:59.665499 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3485 22:58:59.672221 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3486 22:58:59.675366 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3487 22:58:59.678539 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3488 22:58:59.685352 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3489 22:58:59.688616 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3490 22:58:59.691725 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3491 22:58:59.698864 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3492 22:58:59.701789 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3493 22:58:59.704902 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3494 22:58:59.711897 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3495 22:58:59.715177 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3496 22:58:59.718167 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3497 22:58:59.724855 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3498 22:58:59.728519 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3499 22:58:59.731663 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3500 22:58:59.738213 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3501 22:58:59.741501 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3502 22:58:59.745098 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3503 22:58:59.748021 Total UI for P1: 0, mck2ui 16
3504 22:58:59.751804 best dqsien dly found for B0: ( 1, 3, 24)
3505 22:58:59.754969 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3506 22:58:59.757902 Total UI for P1: 0, mck2ui 16
3507 22:58:59.761500 best dqsien dly found for B1: ( 1, 3, 28)
3508 22:58:59.764455 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3509 22:58:59.771088 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3510 22:58:59.771203
3511 22:58:59.774685 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3512 22:58:59.777747 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3513 22:58:59.781371 [Gating] SW calibration Done
3514 22:58:59.781483 ==
3515 22:58:59.784393 Dram Type= 6, Freq= 0, CH_1, rank 1
3516 22:58:59.788137 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3517 22:58:59.788243 ==
3518 22:58:59.791132 RX Vref Scan: 0
3519 22:58:59.791239
3520 22:58:59.791334 RX Vref 0 -> 0, step: 1
3521 22:58:59.791426
3522 22:58:59.794836 RX Delay -40 -> 252, step: 8
3523 22:58:59.798088 iDelay=200, Bit 0, Center 115 (48 ~ 183) 136
3524 22:58:59.804294 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3525 22:58:59.808091 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3526 22:58:59.811344 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3527 22:58:59.814427 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3528 22:58:59.817630 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3529 22:58:59.821493 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3530 22:58:59.827584 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3531 22:58:59.831300 iDelay=200, Bit 8, Center 99 (24 ~ 175) 152
3532 22:58:59.834417 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3533 22:58:59.837685 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3534 22:58:59.840943 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3535 22:58:59.847588 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
3536 22:58:59.851296 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3537 22:58:59.854283 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3538 22:58:59.858053 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3539 22:58:59.858170 ==
3540 22:58:59.860971 Dram Type= 6, Freq= 0, CH_1, rank 1
3541 22:58:59.867769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3542 22:58:59.867892 ==
3543 22:58:59.867964 DQS Delay:
3544 22:58:59.870971 DQS0 = 0, DQS1 = 0
3545 22:58:59.871089 DQM Delay:
3546 22:58:59.873944 DQM0 = 113, DQM1 = 110
3547 22:58:59.874025 DQ Delay:
3548 22:58:59.877554 DQ0 =115, DQ1 =111, DQ2 =103, DQ3 =111
3549 22:58:59.880673 DQ4 =111, DQ5 =127, DQ6 =119, DQ7 =111
3550 22:58:59.884408 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =103
3551 22:58:59.887516 DQ12 =115, DQ13 =119, DQ14 =119, DQ15 =119
3552 22:58:59.887607
3553 22:58:59.887673
3554 22:58:59.887735 ==
3555 22:58:59.890627 Dram Type= 6, Freq= 0, CH_1, rank 1
3556 22:58:59.894264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3557 22:58:59.897314 ==
3558 22:58:59.897399
3559 22:58:59.897466
3560 22:58:59.897534 TX Vref Scan disable
3561 22:58:59.900622 == TX Byte 0 ==
3562 22:58:59.904277 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3563 22:58:59.907471 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3564 22:58:59.910646 == TX Byte 1 ==
3565 22:58:59.914336 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3566 22:58:59.917687 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3567 22:58:59.920906 ==
3568 22:58:59.920984 Dram Type= 6, Freq= 0, CH_1, rank 1
3569 22:58:59.927763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3570 22:58:59.927852 ==
3571 22:58:59.938150 TX Vref=22, minBit 1, minWin=25, winSum=417
3572 22:58:59.941963 TX Vref=24, minBit 1, minWin=25, winSum=425
3573 22:58:59.945175 TX Vref=26, minBit 0, minWin=26, winSum=428
3574 22:58:59.948169 TX Vref=28, minBit 0, minWin=26, winSum=432
3575 22:58:59.951692 TX Vref=30, minBit 4, minWin=26, winSum=433
3576 22:58:59.955342 TX Vref=32, minBit 4, minWin=26, winSum=432
3577 22:58:59.961287 [TxChooseVref] Worse bit 4, Min win 26, Win sum 433, Final Vref 30
3578 22:58:59.961375
3579 22:58:59.964899 Final TX Range 1 Vref 30
3580 22:58:59.964988
3581 22:58:59.965056 ==
3582 22:58:59.968134 Dram Type= 6, Freq= 0, CH_1, rank 1
3583 22:58:59.971696 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3584 22:58:59.971782 ==
3585 22:58:59.974727
3586 22:58:59.974811
3587 22:58:59.974879 TX Vref Scan disable
3588 22:58:59.978552 == TX Byte 0 ==
3589 22:58:59.981435 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3590 22:58:59.984509 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3591 22:58:59.988167 == TX Byte 1 ==
3592 22:58:59.991341 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3593 22:58:59.998090 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3594 22:58:59.998179
3595 22:58:59.998250 [DATLAT]
3596 22:58:59.998316 Freq=1200, CH1 RK1
3597 22:58:59.998381
3598 22:59:00.001310 DATLAT Default: 0xd
3599 22:59:00.001390 0, 0xFFFF, sum = 0
3600 22:59:00.004655 1, 0xFFFF, sum = 0
3601 22:59:00.007644 2, 0xFFFF, sum = 0
3602 22:59:00.007723 3, 0xFFFF, sum = 0
3603 22:59:00.011311 4, 0xFFFF, sum = 0
3604 22:59:00.011393 5, 0xFFFF, sum = 0
3605 22:59:00.014420 6, 0xFFFF, sum = 0
3606 22:59:00.014495 7, 0xFFFF, sum = 0
3607 22:59:00.017590 8, 0xFFFF, sum = 0
3608 22:59:00.017670 9, 0xFFFF, sum = 0
3609 22:59:00.021437 10, 0xFFFF, sum = 0
3610 22:59:00.021543 11, 0xFFFF, sum = 0
3611 22:59:00.024453 12, 0x0, sum = 1
3612 22:59:00.024558 13, 0x0, sum = 2
3613 22:59:00.027547 14, 0x0, sum = 3
3614 22:59:00.027647 15, 0x0, sum = 4
3615 22:59:00.031501 best_step = 13
3616 22:59:00.031576
3617 22:59:00.031639 ==
3618 22:59:00.034472 Dram Type= 6, Freq= 0, CH_1, rank 1
3619 22:59:00.037574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3620 22:59:00.037682 ==
3621 22:59:00.037786 RX Vref Scan: 0
3622 22:59:00.037867
3623 22:59:00.041159 RX Vref 0 -> 0, step: 1
3624 22:59:00.041241
3625 22:59:00.044300 RX Delay -21 -> 252, step: 4
3626 22:59:00.047370 iDelay=191, Bit 0, Center 112 (43 ~ 182) 140
3627 22:59:00.054101 iDelay=191, Bit 1, Center 110 (43 ~ 178) 136
3628 22:59:00.057840 iDelay=191, Bit 2, Center 104 (39 ~ 170) 132
3629 22:59:00.060665 iDelay=191, Bit 3, Center 110 (43 ~ 178) 136
3630 22:59:00.064410 iDelay=191, Bit 4, Center 114 (47 ~ 182) 136
3631 22:59:00.067506 iDelay=191, Bit 5, Center 124 (59 ~ 190) 132
3632 22:59:00.074219 iDelay=191, Bit 6, Center 122 (55 ~ 190) 136
3633 22:59:00.077622 iDelay=191, Bit 7, Center 110 (43 ~ 178) 136
3634 22:59:00.081281 iDelay=191, Bit 8, Center 100 (35 ~ 166) 132
3635 22:59:00.084354 iDelay=191, Bit 9, Center 98 (35 ~ 162) 128
3636 22:59:00.087437 iDelay=191, Bit 10, Center 110 (43 ~ 178) 136
3637 22:59:00.094121 iDelay=191, Bit 11, Center 102 (35 ~ 170) 136
3638 22:59:00.097299 iDelay=191, Bit 12, Center 114 (51 ~ 178) 128
3639 22:59:00.100837 iDelay=191, Bit 13, Center 120 (55 ~ 186) 132
3640 22:59:00.103939 iDelay=191, Bit 14, Center 118 (55 ~ 182) 128
3641 22:59:00.110913 iDelay=191, Bit 15, Center 116 (51 ~ 182) 132
3642 22:59:00.111024 ==
3643 22:59:00.114163 Dram Type= 6, Freq= 0, CH_1, rank 1
3644 22:59:00.117328 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3645 22:59:00.117439 ==
3646 22:59:00.117539 DQS Delay:
3647 22:59:00.120426 DQS0 = 0, DQS1 = 0
3648 22:59:00.120529 DQM Delay:
3649 22:59:00.124256 DQM0 = 113, DQM1 = 109
3650 22:59:00.124366 DQ Delay:
3651 22:59:00.127392 DQ0 =112, DQ1 =110, DQ2 =104, DQ3 =110
3652 22:59:00.130555 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =110
3653 22:59:00.133666 DQ8 =100, DQ9 =98, DQ10 =110, DQ11 =102
3654 22:59:00.137456 DQ12 =114, DQ13 =120, DQ14 =118, DQ15 =116
3655 22:59:00.137572
3656 22:59:00.137676
3657 22:59:00.147300 [DQSOSCAuto] RK1, (LSB)MR18= 0xfa02, (MSB)MR19= 0x304, tDQSOscB0 = 409 ps tDQSOscB1 = 412 ps
3658 22:59:00.150499 CH1 RK1: MR19=304, MR18=FA02
3659 22:59:00.153687 CH1_RK1: MR19=0x304, MR18=0xFA02, DQSOSC=409, MR23=63, INC=39, DEC=26
3660 22:59:00.157524 [RxdqsGatingPostProcess] freq 1200
3661 22:59:00.164225 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3662 22:59:00.167216 best DQS0 dly(2T, 0.5T) = (0, 11)
3663 22:59:00.170414 best DQS1 dly(2T, 0.5T) = (0, 11)
3664 22:59:00.174157 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3665 22:59:00.177262 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3666 22:59:00.180870 best DQS0 dly(2T, 0.5T) = (0, 11)
3667 22:59:00.183923 best DQS1 dly(2T, 0.5T) = (0, 11)
3668 22:59:00.187531 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3669 22:59:00.190520 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3670 22:59:00.190602 Pre-setting of DQS Precalculation
3671 22:59:00.197166 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3672 22:59:00.203948 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3673 22:59:00.210796 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3674 22:59:00.210915
3675 22:59:00.211026
3676 22:59:00.213886 [Calibration Summary] 2400 Mbps
3677 22:59:00.217165 CH 0, Rank 0
3678 22:59:00.217281 SW Impedance : PASS
3679 22:59:00.221000 DUTY Scan : NO K
3680 22:59:00.223953 ZQ Calibration : PASS
3681 22:59:00.224062 Jitter Meter : NO K
3682 22:59:00.227175 CBT Training : PASS
3683 22:59:00.230423 Write leveling : PASS
3684 22:59:00.230523 RX DQS gating : PASS
3685 22:59:00.233452 RX DQ/DQS(RDDQC) : PASS
3686 22:59:00.237151 TX DQ/DQS : PASS
3687 22:59:00.237236 RX DATLAT : PASS
3688 22:59:00.240315 RX DQ/DQS(Engine): PASS
3689 22:59:00.240398 TX OE : NO K
3690 22:59:00.243366 All Pass.
3691 22:59:00.243451
3692 22:59:00.243519 CH 0, Rank 1
3693 22:59:00.247158 SW Impedance : PASS
3694 22:59:00.247240 DUTY Scan : NO K
3695 22:59:00.250017 ZQ Calibration : PASS
3696 22:59:00.253779 Jitter Meter : NO K
3697 22:59:00.253863 CBT Training : PASS
3698 22:59:00.256973 Write leveling : PASS
3699 22:59:00.260217 RX DQS gating : PASS
3700 22:59:00.260307 RX DQ/DQS(RDDQC) : PASS
3701 22:59:00.263949 TX DQ/DQS : PASS
3702 22:59:00.267109 RX DATLAT : PASS
3703 22:59:00.267229 RX DQ/DQS(Engine): PASS
3704 22:59:00.270258 TX OE : NO K
3705 22:59:00.270393 All Pass.
3706 22:59:00.270516
3707 22:59:00.274223 CH 1, Rank 0
3708 22:59:00.274380 SW Impedance : PASS
3709 22:59:00.276570 DUTY Scan : NO K
3710 22:59:00.280272 ZQ Calibration : PASS
3711 22:59:00.280380 Jitter Meter : NO K
3712 22:59:00.283299 CBT Training : PASS
3713 22:59:00.286864 Write leveling : PASS
3714 22:59:00.287071 RX DQS gating : PASS
3715 22:59:00.289952 RX DQ/DQS(RDDQC) : PASS
3716 22:59:00.293606 TX DQ/DQS : PASS
3717 22:59:00.293752 RX DATLAT : PASS
3718 22:59:00.296567 RX DQ/DQS(Engine): PASS
3719 22:59:00.296713 TX OE : NO K
3720 22:59:00.300232 All Pass.
3721 22:59:00.300380
3722 22:59:00.300486 CH 1, Rank 1
3723 22:59:00.303212 SW Impedance : PASS
3724 22:59:00.303327 DUTY Scan : NO K
3725 22:59:00.306369 ZQ Calibration : PASS
3726 22:59:00.309973 Jitter Meter : NO K
3727 22:59:00.310054 CBT Training : PASS
3728 22:59:00.313166 Write leveling : PASS
3729 22:59:00.316309 RX DQS gating : PASS
3730 22:59:00.316420 RX DQ/DQS(RDDQC) : PASS
3731 22:59:00.319548 TX DQ/DQS : PASS
3732 22:59:00.323367 RX DATLAT : PASS
3733 22:59:00.323458 RX DQ/DQS(Engine): PASS
3734 22:59:00.326494 TX OE : NO K
3735 22:59:00.326598 All Pass.
3736 22:59:00.326701
3737 22:59:00.329649 DramC Write-DBI off
3738 22:59:00.332909 PER_BANK_REFRESH: Hybrid Mode
3739 22:59:00.332996 TX_TRACKING: ON
3740 22:59:00.343044 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3741 22:59:00.346088 [FAST_K] Save calibration result to emmc
3742 22:59:00.349826 dramc_set_vcore_voltage set vcore to 650000
3743 22:59:00.353284 Read voltage for 600, 5
3744 22:59:00.353379 Vio18 = 0
3745 22:59:00.353451 Vcore = 650000
3746 22:59:00.356451 Vdram = 0
3747 22:59:00.356567 Vddq = 0
3748 22:59:00.356675 Vmddr = 0
3749 22:59:00.363343 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3750 22:59:00.366338 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3751 22:59:00.369410 MEM_TYPE=3, freq_sel=19
3752 22:59:00.373158 sv_algorithm_assistance_LP4_1600
3753 22:59:00.376196 ============ PULL DRAM RESETB DOWN ============
3754 22:59:00.379832 ========== PULL DRAM RESETB DOWN end =========
3755 22:59:00.386447 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3756 22:59:00.389421 ===================================
3757 22:59:00.393140 LPDDR4 DRAM CONFIGURATION
3758 22:59:00.393236 ===================================
3759 22:59:00.396280 EX_ROW_EN[0] = 0x0
3760 22:59:00.399406 EX_ROW_EN[1] = 0x0
3761 22:59:00.399531 LP4Y_EN = 0x0
3762 22:59:00.402924 WORK_FSP = 0x0
3763 22:59:00.403031 WL = 0x2
3764 22:59:00.405982 RL = 0x2
3765 22:59:00.406098 BL = 0x2
3766 22:59:00.409215 RPST = 0x0
3767 22:59:00.409329 RD_PRE = 0x0
3768 22:59:00.412876 WR_PRE = 0x1
3769 22:59:00.412991 WR_PST = 0x0
3770 22:59:00.416125 DBI_WR = 0x0
3771 22:59:00.416236 DBI_RD = 0x0
3772 22:59:00.419312 OTF = 0x1
3773 22:59:00.422391 ===================================
3774 22:59:00.426133 ===================================
3775 22:59:00.426239 ANA top config
3776 22:59:00.429327 ===================================
3777 22:59:00.432395 DLL_ASYNC_EN = 0
3778 22:59:00.436169 ALL_SLAVE_EN = 1
3779 22:59:00.439323 NEW_RANK_MODE = 1
3780 22:59:00.439443 DLL_IDLE_MODE = 1
3781 22:59:00.442489 LP45_APHY_COMB_EN = 1
3782 22:59:00.445700 TX_ODT_DIS = 1
3783 22:59:00.449449 NEW_8X_MODE = 1
3784 22:59:00.452606 ===================================
3785 22:59:00.455789 ===================================
3786 22:59:00.459326 data_rate = 1200
3787 22:59:00.459428 CKR = 1
3788 22:59:00.462436 DQ_P2S_RATIO = 8
3789 22:59:00.465698 ===================================
3790 22:59:00.469486 CA_P2S_RATIO = 8
3791 22:59:00.472504 DQ_CA_OPEN = 0
3792 22:59:00.475627 DQ_SEMI_OPEN = 0
3793 22:59:00.479257 CA_SEMI_OPEN = 0
3794 22:59:00.479377 CA_FULL_RATE = 0
3795 22:59:00.482296 DQ_CKDIV4_EN = 1
3796 22:59:00.485862 CA_CKDIV4_EN = 1
3797 22:59:00.489074 CA_PREDIV_EN = 0
3798 22:59:00.492111 PH8_DLY = 0
3799 22:59:00.495842 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3800 22:59:00.495957 DQ_AAMCK_DIV = 4
3801 22:59:00.498860 CA_AAMCK_DIV = 4
3802 22:59:00.502631 CA_ADMCK_DIV = 4
3803 22:59:00.505482 DQ_TRACK_CA_EN = 0
3804 22:59:00.509224 CA_PICK = 600
3805 22:59:00.512281 CA_MCKIO = 600
3806 22:59:00.512390 MCKIO_SEMI = 0
3807 22:59:00.515437 PLL_FREQ = 2288
3808 22:59:00.518856 DQ_UI_PI_RATIO = 32
3809 22:59:00.522035 CA_UI_PI_RATIO = 0
3810 22:59:00.525900 ===================================
3811 22:59:00.529007 ===================================
3812 22:59:00.532199 memory_type:LPDDR4
3813 22:59:00.532320 GP_NUM : 10
3814 22:59:00.535956 SRAM_EN : 1
3815 22:59:00.538966 MD32_EN : 0
3816 22:59:00.542200 ===================================
3817 22:59:00.542327 [ANA_INIT] >>>>>>>>>>>>>>
3818 22:59:00.545421 <<<<<< [CONFIGURE PHASE]: ANA_TX
3819 22:59:00.549064 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3820 22:59:00.552216 ===================================
3821 22:59:00.555430 data_rate = 1200,PCW = 0X5800
3822 22:59:00.558630 ===================================
3823 22:59:00.562132 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3824 22:59:00.568939 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3825 22:59:00.572115 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3826 22:59:00.578621 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3827 22:59:00.582518 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3828 22:59:00.585555 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3829 22:59:00.585670 [ANA_INIT] flow start
3830 22:59:00.589056 [ANA_INIT] PLL >>>>>>>>
3831 22:59:00.592055 [ANA_INIT] PLL <<<<<<<<
3832 22:59:00.595212 [ANA_INIT] MIDPI >>>>>>>>
3833 22:59:00.595314 [ANA_INIT] MIDPI <<<<<<<<
3834 22:59:00.598969 [ANA_INIT] DLL >>>>>>>>
3835 22:59:00.601983 [ANA_INIT] flow end
3836 22:59:00.605579 ============ LP4 DIFF to SE enter ============
3837 22:59:00.608750 ============ LP4 DIFF to SE exit ============
3838 22:59:00.611842 [ANA_INIT] <<<<<<<<<<<<<
3839 22:59:00.615657 [Flow] Enable top DCM control >>>>>
3840 22:59:00.618663 [Flow] Enable top DCM control <<<<<
3841 22:59:00.622301 Enable DLL master slave shuffle
3842 22:59:00.625389 ==============================================================
3843 22:59:00.628572 Gating Mode config
3844 22:59:00.631827 ==============================================================
3845 22:59:00.635571 Config description:
3846 22:59:00.645733 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3847 22:59:00.652001 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3848 22:59:00.655177 SELPH_MODE 0: By rank 1: By Phase
3849 22:59:00.661955 ==============================================================
3850 22:59:00.665150 GAT_TRACK_EN = 1
3851 22:59:00.668886 RX_GATING_MODE = 2
3852 22:59:00.671717 RX_GATING_TRACK_MODE = 2
3853 22:59:00.674909 SELPH_MODE = 1
3854 22:59:00.678636 PICG_EARLY_EN = 1
3855 22:59:00.678759 VALID_LAT_VALUE = 1
3856 22:59:00.684816 ==============================================================
3857 22:59:00.688629 Enter into Gating configuration >>>>
3858 22:59:00.691750 Exit from Gating configuration <<<<
3859 22:59:00.694797 Enter into DVFS_PRE_config >>>>>
3860 22:59:00.704955 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3861 22:59:00.708019 Exit from DVFS_PRE_config <<<<<
3862 22:59:00.711847 Enter into PICG configuration >>>>
3863 22:59:00.714894 Exit from PICG configuration <<<<
3864 22:59:00.718467 [RX_INPUT] configuration >>>>>
3865 22:59:00.721675 [RX_INPUT] configuration <<<<<
3866 22:59:00.728333 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3867 22:59:00.731581 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3868 22:59:00.738050 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3869 22:59:00.744847 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3870 22:59:00.751720 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3871 22:59:00.758071 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3872 22:59:00.761868 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3873 22:59:00.765035 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3874 22:59:00.768330 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3875 22:59:00.771487 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3876 22:59:00.778078 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3877 22:59:00.781312 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3878 22:59:00.785027 ===================================
3879 22:59:00.788058 LPDDR4 DRAM CONFIGURATION
3880 22:59:00.791815 ===================================
3881 22:59:00.791933 EX_ROW_EN[0] = 0x0
3882 22:59:00.794854 EX_ROW_EN[1] = 0x0
3883 22:59:00.794964 LP4Y_EN = 0x0
3884 22:59:00.797846 WORK_FSP = 0x0
3885 22:59:00.797971 WL = 0x2
3886 22:59:00.801623 RL = 0x2
3887 22:59:00.801730 BL = 0x2
3888 22:59:00.804645 RPST = 0x0
3889 22:59:00.808331 RD_PRE = 0x0
3890 22:59:00.808443 WR_PRE = 0x1
3891 22:59:00.811371 WR_PST = 0x0
3892 22:59:00.811490 DBI_WR = 0x0
3893 22:59:00.814505 DBI_RD = 0x0
3894 22:59:00.814619 OTF = 0x1
3895 22:59:00.818199 ===================================
3896 22:59:00.821224 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3897 22:59:00.827898 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3898 22:59:00.831147 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3899 22:59:00.834841 ===================================
3900 22:59:00.837918 LPDDR4 DRAM CONFIGURATION
3901 22:59:00.841001 ===================================
3902 22:59:00.841089 EX_ROW_EN[0] = 0x10
3903 22:59:00.844706 EX_ROW_EN[1] = 0x0
3904 22:59:00.844835 LP4Y_EN = 0x0
3905 22:59:00.847973 WORK_FSP = 0x0
3906 22:59:00.848093 WL = 0x2
3907 22:59:00.851130 RL = 0x2
3908 22:59:00.851246 BL = 0x2
3909 22:59:00.854221 RPST = 0x0
3910 22:59:00.854341 RD_PRE = 0x0
3911 22:59:00.858111 WR_PRE = 0x1
3912 22:59:00.858222 WR_PST = 0x0
3913 22:59:00.861299 DBI_WR = 0x0
3914 22:59:00.864348 DBI_RD = 0x0
3915 22:59:00.864462 OTF = 0x1
3916 22:59:00.867446 ===================================
3917 22:59:00.874170 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3918 22:59:00.877941 nWR fixed to 30
3919 22:59:00.880933 [ModeRegInit_LP4] CH0 RK0
3920 22:59:00.881049 [ModeRegInit_LP4] CH0 RK1
3921 22:59:00.884630 [ModeRegInit_LP4] CH1 RK0
3922 22:59:00.887882 [ModeRegInit_LP4] CH1 RK1
3923 22:59:00.887972 match AC timing 17
3924 22:59:00.894577 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3925 22:59:00.897805 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3926 22:59:00.901422 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3927 22:59:00.908175 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3928 22:59:00.911254 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3929 22:59:00.911343 ==
3930 22:59:00.914671 Dram Type= 6, Freq= 0, CH_0, rank 0
3931 22:59:00.917742 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3932 22:59:00.917830 ==
3933 22:59:00.924567 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3934 22:59:00.931267 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3935 22:59:00.934353 [CA 0] Center 36 (6~67) winsize 62
3936 22:59:00.937874 [CA 1] Center 36 (6~66) winsize 61
3937 22:59:00.941119 [CA 2] Center 34 (4~65) winsize 62
3938 22:59:00.944276 [CA 3] Center 34 (4~64) winsize 61
3939 22:59:00.947503 [CA 4] Center 33 (3~64) winsize 62
3940 22:59:00.951197 [CA 5] Center 33 (3~64) winsize 62
3941 22:59:00.951313
3942 22:59:00.954361 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3943 22:59:00.954472
3944 22:59:00.957575 [CATrainingPosCal] consider 1 rank data
3945 22:59:00.961418 u2DelayCellTimex100 = 270/100 ps
3946 22:59:00.964476 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3947 22:59:00.967558 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3948 22:59:00.970838 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3949 22:59:00.973991 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
3950 22:59:00.977353 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3951 22:59:00.980940 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3952 22:59:00.983889
3953 22:59:00.987653 CA PerBit enable=1, Macro0, CA PI delay=33
3954 22:59:00.987766
3955 22:59:00.990875 [CBTSetCACLKResult] CA Dly = 33
3956 22:59:00.990986 CS Dly: 5 (0~36)
3957 22:59:00.991084 ==
3958 22:59:00.994085 Dram Type= 6, Freq= 0, CH_0, rank 1
3959 22:59:00.997727 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3960 22:59:00.997843 ==
3961 22:59:01.003809 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3962 22:59:01.010535 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3963 22:59:01.014243 [CA 0] Center 36 (6~66) winsize 61
3964 22:59:01.017414 [CA 1] Center 36 (6~66) winsize 61
3965 22:59:01.020973 [CA 2] Center 34 (4~65) winsize 62
3966 22:59:01.023996 [CA 3] Center 34 (4~65) winsize 62
3967 22:59:01.027187 [CA 4] Center 33 (3~64) winsize 62
3968 22:59:01.030671 [CA 5] Center 33 (3~64) winsize 62
3969 22:59:01.030782
3970 22:59:01.033870 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3971 22:59:01.033971
3972 22:59:01.037586 [CATrainingPosCal] consider 2 rank data
3973 22:59:01.040550 u2DelayCellTimex100 = 270/100 ps
3974 22:59:01.043730 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3975 22:59:01.047307 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3976 22:59:01.050507 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3977 22:59:01.053545 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
3978 22:59:01.060558 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3979 22:59:01.063780 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3980 22:59:01.063870
3981 22:59:01.067617 CA PerBit enable=1, Macro0, CA PI delay=33
3982 22:59:01.067706
3983 22:59:01.070674 [CBTSetCACLKResult] CA Dly = 33
3984 22:59:01.070761 CS Dly: 5 (0~36)
3985 22:59:01.070828
3986 22:59:01.073914 ----->DramcWriteLeveling(PI) begin...
3987 22:59:01.073994 ==
3988 22:59:01.077162 Dram Type= 6, Freq= 0, CH_0, rank 0
3989 22:59:01.083979 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3990 22:59:01.084082 ==
3991 22:59:01.087007 Write leveling (Byte 0): 34 => 34
3992 22:59:01.090781 Write leveling (Byte 1): 30 => 30
3993 22:59:01.090868 DramcWriteLeveling(PI) end<-----
3994 22:59:01.090937
3995 22:59:01.093820 ==
3996 22:59:01.093906 Dram Type= 6, Freq= 0, CH_0, rank 0
3997 22:59:01.100113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3998 22:59:01.100201 ==
3999 22:59:01.103762 [Gating] SW mode calibration
4000 22:59:01.110447 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4001 22:59:01.113605 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4002 22:59:01.120148 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4003 22:59:01.123800 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4004 22:59:01.126925 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4005 22:59:01.133752 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
4006 22:59:01.136703 0 9 16 | B1->B0 | 2f2f 2d2d | 1 1 | (1 1) (1 0)
4007 22:59:01.140488 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4008 22:59:01.146597 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4009 22:59:01.150491 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4010 22:59:01.153476 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4011 22:59:01.159928 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4012 22:59:01.163582 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4013 22:59:01.166742 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4014 22:59:01.170536 0 10 16 | B1->B0 | 302f 3f3f | 1 0 | (1 1) (0 0)
4015 22:59:01.176823 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4016 22:59:01.179982 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4017 22:59:01.183115 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4018 22:59:01.190149 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4019 22:59:01.193160 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4020 22:59:01.196798 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4021 22:59:01.203616 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4022 22:59:01.206690 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4023 22:59:01.209858 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4024 22:59:01.216965 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4025 22:59:01.220113 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4026 22:59:01.223142 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4027 22:59:01.230052 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4028 22:59:01.233552 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4029 22:59:01.236616 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4030 22:59:01.243455 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4031 22:59:01.246581 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4032 22:59:01.249614 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4033 22:59:01.256585 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4034 22:59:01.259767 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4035 22:59:01.262914 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4036 22:59:01.269813 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4037 22:59:01.272912 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4038 22:59:01.276692 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4039 22:59:01.283432 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4040 22:59:01.283531 Total UI for P1: 0, mck2ui 16
4041 22:59:01.286665 best dqsien dly found for B0: ( 0, 13, 16)
4042 22:59:01.292912 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4043 22:59:01.296648 Total UI for P1: 0, mck2ui 16
4044 22:59:01.299756 best dqsien dly found for B1: ( 0, 13, 20)
4045 22:59:01.302949 best DQS0 dly(MCK, UI, PI) = (0, 13, 16)
4046 22:59:01.306107 best DQS1 dly(MCK, UI, PI) = (0, 13, 20)
4047 22:59:01.306221
4048 22:59:01.309806 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 16)
4049 22:59:01.312807 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 20)
4050 22:59:01.315861 [Gating] SW calibration Done
4051 22:59:01.315944 ==
4052 22:59:01.319489 Dram Type= 6, Freq= 0, CH_0, rank 0
4053 22:59:01.322580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4054 22:59:01.322662 ==
4055 22:59:01.326235 RX Vref Scan: 0
4056 22:59:01.326309
4057 22:59:01.329287 RX Vref 0 -> 0, step: 1
4058 22:59:01.329396
4059 22:59:01.332825 RX Delay -230 -> 252, step: 16
4060 22:59:01.335922 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4061 22:59:01.339600 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4062 22:59:01.342623 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4063 22:59:01.345738 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4064 22:59:01.352535 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4065 22:59:01.356307 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4066 22:59:01.359496 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4067 22:59:01.362539 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4068 22:59:01.369430 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4069 22:59:01.372567 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4070 22:59:01.375697 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4071 22:59:01.379621 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4072 22:59:01.385626 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4073 22:59:01.389386 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4074 22:59:01.392606 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4075 22:59:01.395791 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4076 22:59:01.395872 ==
4077 22:59:01.398785 Dram Type= 6, Freq= 0, CH_0, rank 0
4078 22:59:01.405713 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4079 22:59:01.405822 ==
4080 22:59:01.405893 DQS Delay:
4081 22:59:01.408845 DQS0 = 0, DQS1 = 0
4082 22:59:01.408922 DQM Delay:
4083 22:59:01.408991 DQM0 = 40, DQM1 = 34
4084 22:59:01.412004 DQ Delay:
4085 22:59:01.415641 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4086 22:59:01.418761 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4087 22:59:01.421845 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =25
4088 22:59:01.425428 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =49
4089 22:59:01.425538
4090 22:59:01.425637
4091 22:59:01.425738 ==
4092 22:59:01.429093 Dram Type= 6, Freq= 0, CH_0, rank 0
4093 22:59:01.432144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4094 22:59:01.432283 ==
4095 22:59:01.432393
4096 22:59:01.432517
4097 22:59:01.435067 TX Vref Scan disable
4098 22:59:01.438641 == TX Byte 0 ==
4099 22:59:01.441799 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4100 22:59:01.445539 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4101 22:59:01.448628 == TX Byte 1 ==
4102 22:59:01.452177 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4103 22:59:01.455362 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4104 22:59:01.455479 ==
4105 22:59:01.458804 Dram Type= 6, Freq= 0, CH_0, rank 0
4106 22:59:01.462002 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4107 22:59:01.462118 ==
4108 22:59:01.465311
4109 22:59:01.465421
4110 22:59:01.465525 TX Vref Scan disable
4111 22:59:01.469017 == TX Byte 0 ==
4112 22:59:01.472087 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4113 22:59:01.479193 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4114 22:59:01.479313 == TX Byte 1 ==
4115 22:59:01.482243 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4116 22:59:01.489094 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4117 22:59:01.489222
4118 22:59:01.489331 [DATLAT]
4119 22:59:01.489433 Freq=600, CH0 RK0
4120 22:59:01.489525
4121 22:59:01.492344 DATLAT Default: 0x9
4122 22:59:01.492424 0, 0xFFFF, sum = 0
4123 22:59:01.495492 1, 0xFFFF, sum = 0
4124 22:59:01.498537 2, 0xFFFF, sum = 0
4125 22:59:01.498641 3, 0xFFFF, sum = 0
4126 22:59:01.502233 4, 0xFFFF, sum = 0
4127 22:59:01.502352 5, 0xFFFF, sum = 0
4128 22:59:01.505575 6, 0xFFFF, sum = 0
4129 22:59:01.505689 7, 0xFFFF, sum = 0
4130 22:59:01.508471 8, 0x0, sum = 1
4131 22:59:01.508582 9, 0x0, sum = 2
4132 22:59:01.512090 10, 0x0, sum = 3
4133 22:59:01.512201 11, 0x0, sum = 4
4134 22:59:01.512306 best_step = 9
4135 22:59:01.512399
4136 22:59:01.515207 ==
4137 22:59:01.515315 Dram Type= 6, Freq= 0, CH_0, rank 0
4138 22:59:01.521994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4139 22:59:01.522110 ==
4140 22:59:01.522208 RX Vref Scan: 1
4141 22:59:01.522299
4142 22:59:01.525175 RX Vref 0 -> 0, step: 1
4143 22:59:01.525256
4144 22:59:01.528728 RX Delay -179 -> 252, step: 8
4145 22:59:01.528811
4146 22:59:01.531762 Set Vref, RX VrefLevel [Byte0]: 52
4147 22:59:01.535415 [Byte1]: 50
4148 22:59:01.535510
4149 22:59:01.538407 Final RX Vref Byte 0 = 52 to rank0
4150 22:59:01.541903 Final RX Vref Byte 1 = 50 to rank0
4151 22:59:01.544891 Final RX Vref Byte 0 = 52 to rank1
4152 22:59:01.548128 Final RX Vref Byte 1 = 50 to rank1==
4153 22:59:01.551748 Dram Type= 6, Freq= 0, CH_0, rank 0
4154 22:59:01.554853 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4155 22:59:01.554976 ==
4156 22:59:01.558051 DQS Delay:
4157 22:59:01.558158 DQS0 = 0, DQS1 = 0
4158 22:59:01.561683 DQM Delay:
4159 22:59:01.561785 DQM0 = 41, DQM1 = 33
4160 22:59:01.564639 DQ Delay:
4161 22:59:01.564716 DQ0 =40, DQ1 =40, DQ2 =36, DQ3 =40
4162 22:59:01.568430 DQ4 =40, DQ5 =32, DQ6 =52, DQ7 =52
4163 22:59:01.571521 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =28
4164 22:59:01.574740 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44
4165 22:59:01.574846
4166 22:59:01.577733
4167 22:59:01.584690 [DQSOSCAuto] RK0, (LSB)MR18= 0x4322, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 397 ps
4168 22:59:01.587817 CH0 RK0: MR19=808, MR18=4322
4169 22:59:01.594851 CH0_RK0: MR19=0x808, MR18=0x4322, DQSOSC=397, MR23=63, INC=166, DEC=110
4170 22:59:01.594987
4171 22:59:01.598211 ----->DramcWriteLeveling(PI) begin...
4172 22:59:01.598339 ==
4173 22:59:01.601186 Dram Type= 6, Freq= 0, CH_0, rank 1
4174 22:59:01.604452 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4175 22:59:01.604569 ==
4176 22:59:01.607786 Write leveling (Byte 0): 30 => 30
4177 22:59:01.610978 Write leveling (Byte 1): 31 => 31
4178 22:59:01.614681 DramcWriteLeveling(PI) end<-----
4179 22:59:01.614793
4180 22:59:01.614891 ==
4181 22:59:01.617798 Dram Type= 6, Freq= 0, CH_0, rank 1
4182 22:59:01.620958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4183 22:59:01.621068 ==
4184 22:59:01.624687 [Gating] SW mode calibration
4185 22:59:01.631468 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4186 22:59:01.637597 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4187 22:59:01.641327 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4188 22:59:01.644361 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4189 22:59:01.651141 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4190 22:59:01.654237 0 9 12 | B1->B0 | 3434 3131 | 1 0 | (1 1) (1 0)
4191 22:59:01.657814 0 9 16 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
4192 22:59:01.664143 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4193 22:59:01.667764 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4194 22:59:01.670834 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4195 22:59:01.677693 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4196 22:59:01.680729 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4197 22:59:01.684561 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4198 22:59:01.690779 0 10 12 | B1->B0 | 2323 3636 | 0 1 | (0 0) (0 0)
4199 22:59:01.694124 0 10 16 | B1->B0 | 3232 4646 | 0 0 | (0 0) (0 0)
4200 22:59:01.697699 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4201 22:59:01.704075 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4202 22:59:01.707743 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4203 22:59:01.710856 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4204 22:59:01.717702 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4205 22:59:01.720791 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4206 22:59:01.723984 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4207 22:59:01.730838 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4208 22:59:01.734470 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4209 22:59:01.737439 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4210 22:59:01.744309 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4211 22:59:01.747437 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4212 22:59:01.750258 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4213 22:59:01.757624 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4214 22:59:01.760717 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4215 22:59:01.763732 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4216 22:59:01.766895 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4217 22:59:01.773603 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4218 22:59:01.777488 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4219 22:59:01.780640 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4220 22:59:01.786806 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4221 22:59:01.790614 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4222 22:59:01.793764 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4223 22:59:01.800165 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4224 22:59:01.803722 Total UI for P1: 0, mck2ui 16
4225 22:59:01.806957 best dqsien dly found for B0: ( 0, 13, 12)
4226 22:59:01.809938 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4227 22:59:01.813782 Total UI for P1: 0, mck2ui 16
4228 22:59:01.816897 best dqsien dly found for B1: ( 0, 13, 16)
4229 22:59:01.820080 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4230 22:59:01.823527 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4231 22:59:01.823611
4232 22:59:01.826724 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4233 22:59:01.833561 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4234 22:59:01.833657 [Gating] SW calibration Done
4235 22:59:01.833738 ==
4236 22:59:01.836697 Dram Type= 6, Freq= 0, CH_0, rank 1
4237 22:59:01.843462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4238 22:59:01.843557 ==
4239 22:59:01.843632 RX Vref Scan: 0
4240 22:59:01.843711
4241 22:59:01.846501 RX Vref 0 -> 0, step: 1
4242 22:59:01.846613
4243 22:59:01.849672 RX Delay -230 -> 252, step: 16
4244 22:59:01.853094 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4245 22:59:01.856313 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4246 22:59:01.862872 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4247 22:59:01.866504 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4248 22:59:01.869739 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4249 22:59:01.872763 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4250 22:59:01.876307 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4251 22:59:01.883211 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4252 22:59:01.886483 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4253 22:59:01.889500 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4254 22:59:01.892552 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4255 22:59:01.899574 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4256 22:59:01.902716 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4257 22:59:01.906324 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4258 22:59:01.909605 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4259 22:59:01.916586 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4260 22:59:01.916702 ==
4261 22:59:01.919544 Dram Type= 6, Freq= 0, CH_0, rank 1
4262 22:59:01.922589 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4263 22:59:01.922694 ==
4264 22:59:01.922788 DQS Delay:
4265 22:59:01.925714 DQS0 = 0, DQS1 = 0
4266 22:59:01.925817 DQM Delay:
4267 22:59:01.929306 DQM0 = 39, DQM1 = 32
4268 22:59:01.929409 DQ Delay:
4269 22:59:01.932543 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =33
4270 22:59:01.935599 DQ4 =41, DQ5 =25, DQ6 =57, DQ7 =49
4271 22:59:01.939388 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =25
4272 22:59:01.942506 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =41
4273 22:59:01.942622
4274 22:59:01.942727
4275 22:59:01.942833 ==
4276 22:59:01.945456 Dram Type= 6, Freq= 0, CH_0, rank 1
4277 22:59:01.949136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4278 22:59:01.949247 ==
4279 22:59:01.952811
4280 22:59:01.952923
4281 22:59:01.953022 TX Vref Scan disable
4282 22:59:01.955877 == TX Byte 0 ==
4283 22:59:01.958950 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4284 22:59:01.962642 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4285 22:59:01.965684 == TX Byte 1 ==
4286 22:59:01.968643 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4287 22:59:01.972307 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4288 22:59:01.975490 ==
4289 22:59:01.975598 Dram Type= 6, Freq= 0, CH_0, rank 1
4290 22:59:01.982405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4291 22:59:01.982519 ==
4292 22:59:01.982629
4293 22:59:01.982741
4294 22:59:01.985578 TX Vref Scan disable
4295 22:59:01.985698 == TX Byte 0 ==
4296 22:59:01.991839 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4297 22:59:01.995085 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4298 22:59:01.995199 == TX Byte 1 ==
4299 22:59:02.002201 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4300 22:59:02.005219 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4301 22:59:02.005331
4302 22:59:02.005429 [DATLAT]
4303 22:59:02.008420 Freq=600, CH0 RK1
4304 22:59:02.008540
4305 22:59:02.008651 DATLAT Default: 0x9
4306 22:59:02.012324 0, 0xFFFF, sum = 0
4307 22:59:02.012441 1, 0xFFFF, sum = 0
4308 22:59:02.015524 2, 0xFFFF, sum = 0
4309 22:59:02.015636 3, 0xFFFF, sum = 0
4310 22:59:02.018483 4, 0xFFFF, sum = 0
4311 22:59:02.018613 5, 0xFFFF, sum = 0
4312 22:59:02.022323 6, 0xFFFF, sum = 0
4313 22:59:02.022441 7, 0xFFFF, sum = 0
4314 22:59:02.025359 8, 0x0, sum = 1
4315 22:59:02.025490 9, 0x0, sum = 2
4316 22:59:02.028550 10, 0x0, sum = 3
4317 22:59:02.028665 11, 0x0, sum = 4
4318 22:59:02.032140 best_step = 9
4319 22:59:02.032291
4320 22:59:02.032393 ==
4321 22:59:02.035228 Dram Type= 6, Freq= 0, CH_0, rank 1
4322 22:59:02.038802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4323 22:59:02.038937 ==
4324 22:59:02.041886 RX Vref Scan: 0
4325 22:59:02.042018
4326 22:59:02.042135 RX Vref 0 -> 0, step: 1
4327 22:59:02.042234
4328 22:59:02.045566 RX Delay -179 -> 252, step: 8
4329 22:59:02.052284 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4330 22:59:02.055911 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4331 22:59:02.059007 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4332 22:59:02.062158 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4333 22:59:02.068738 iDelay=205, Bit 4, Center 36 (-115 ~ 188) 304
4334 22:59:02.071847 iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304
4335 22:59:02.075560 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4336 22:59:02.078615 iDelay=205, Bit 7, Center 44 (-107 ~ 196) 304
4337 22:59:02.082196 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4338 22:59:02.088566 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4339 22:59:02.092271 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4340 22:59:02.095214 iDelay=205, Bit 11, Center 24 (-123 ~ 172) 296
4341 22:59:02.098625 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4342 22:59:02.105501 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4343 22:59:02.108563 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4344 22:59:02.112480 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4345 22:59:02.112571 ==
4346 22:59:02.115102 Dram Type= 6, Freq= 0, CH_0, rank 1
4347 22:59:02.118867 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4348 22:59:02.121897 ==
4349 22:59:02.122011 DQS Delay:
4350 22:59:02.122108 DQS0 = 0, DQS1 = 0
4351 22:59:02.125102 DQM Delay:
4352 22:59:02.125177 DQM0 = 39, DQM1 = 33
4353 22:59:02.129013 DQ Delay:
4354 22:59:02.132055 DQ0 =40, DQ1 =44, DQ2 =36, DQ3 =40
4355 22:59:02.132141 DQ4 =36, DQ5 =28, DQ6 =48, DQ7 =44
4356 22:59:02.135038 DQ8 =24, DQ9 =24, DQ10 =32, DQ11 =24
4357 22:59:02.138799 DQ12 =36, DQ13 =40, DQ14 =44, DQ15 =44
4358 22:59:02.141959
4359 22:59:02.142069
4360 22:59:02.148253 [DQSOSCAuto] RK1, (LSB)MR18= 0x4e2f, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 395 ps
4361 22:59:02.151769 CH0 RK1: MR19=808, MR18=4E2F
4362 22:59:02.158683 CH0_RK1: MR19=0x808, MR18=0x4E2F, DQSOSC=395, MR23=63, INC=168, DEC=112
4363 22:59:02.161653 [RxdqsGatingPostProcess] freq 600
4364 22:59:02.165353 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4365 22:59:02.168444 Pre-setting of DQS Precalculation
4366 22:59:02.175141 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4367 22:59:02.175274 ==
4368 22:59:02.178120 Dram Type= 6, Freq= 0, CH_1, rank 0
4369 22:59:02.181928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4370 22:59:02.182022 ==
4371 22:59:02.188082 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4372 22:59:02.191680 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4373 22:59:02.196219 [CA 0] Center 35 (5~66) winsize 62
4374 22:59:02.199292 [CA 1] Center 35 (5~66) winsize 62
4375 22:59:02.202444 [CA 2] Center 33 (3~64) winsize 62
4376 22:59:02.205685 [CA 3] Center 33 (2~64) winsize 63
4377 22:59:02.209523 [CA 4] Center 33 (3~64) winsize 62
4378 22:59:02.212621 [CA 5] Center 33 (2~64) winsize 63
4379 22:59:02.212709
4380 22:59:02.215886 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4381 22:59:02.215992
4382 22:59:02.219142 [CATrainingPosCal] consider 1 rank data
4383 22:59:02.222093 u2DelayCellTimex100 = 270/100 ps
4384 22:59:02.225389 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4385 22:59:02.232379 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4386 22:59:02.235424 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4387 22:59:02.239152 CA3 delay=33 (2~64),Diff = 0 PI (0 cell)
4388 22:59:02.242254 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4389 22:59:02.245208 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4390 22:59:02.245326
4391 22:59:02.248939 CA PerBit enable=1, Macro0, CA PI delay=33
4392 22:59:02.249054
4393 22:59:02.252043 [CBTSetCACLKResult] CA Dly = 33
4394 22:59:02.252156 CS Dly: 5 (0~36)
4395 22:59:02.255129 ==
4396 22:59:02.258817 Dram Type= 6, Freq= 0, CH_1, rank 1
4397 22:59:02.261829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4398 22:59:02.261916 ==
4399 22:59:02.265415 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4400 22:59:02.272223 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4401 22:59:02.275753 [CA 0] Center 35 (5~66) winsize 62
4402 22:59:02.279381 [CA 1] Center 35 (5~66) winsize 62
4403 22:59:02.282457 [CA 2] Center 34 (3~65) winsize 63
4404 22:59:02.286148 [CA 3] Center 33 (3~64) winsize 62
4405 22:59:02.289279 [CA 4] Center 34 (3~65) winsize 63
4406 22:59:02.292325 [CA 5] Center 33 (2~64) winsize 63
4407 22:59:02.292407
4408 22:59:02.296035 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4409 22:59:02.296120
4410 22:59:02.299193 [CATrainingPosCal] consider 2 rank data
4411 22:59:02.302274 u2DelayCellTimex100 = 270/100 ps
4412 22:59:02.305575 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4413 22:59:02.312500 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4414 22:59:02.315593 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4415 22:59:02.318785 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4416 22:59:02.322507 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4417 22:59:02.325638 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4418 22:59:02.325750
4419 22:59:02.328740 CA PerBit enable=1, Macro0, CA PI delay=33
4420 22:59:02.328848
4421 22:59:02.331939 [CBTSetCACLKResult] CA Dly = 33
4422 22:59:02.332053 CS Dly: 5 (0~37)
4423 22:59:02.335787
4424 22:59:02.338928 ----->DramcWriteLeveling(PI) begin...
4425 22:59:02.339017 ==
4426 22:59:02.342146 Dram Type= 6, Freq= 0, CH_1, rank 0
4427 22:59:02.345513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4428 22:59:02.345648 ==
4429 22:59:02.348659 Write leveling (Byte 0): 29 => 29
4430 22:59:02.352361 Write leveling (Byte 1): 31 => 31
4431 22:59:02.355425 DramcWriteLeveling(PI) end<-----
4432 22:59:02.355541
4433 22:59:02.355656 ==
4434 22:59:02.358429 Dram Type= 6, Freq= 0, CH_1, rank 0
4435 22:59:02.362194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4436 22:59:02.362308 ==
4437 22:59:02.365336 [Gating] SW mode calibration
4438 22:59:02.372017 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4439 22:59:02.378735 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4440 22:59:02.382288 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4441 22:59:02.385474 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4442 22:59:02.391980 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4443 22:59:02.395118 0 9 12 | B1->B0 | 3434 3232 | 0 1 | (0 0) (1 1)
4444 22:59:02.398655 0 9 16 | B1->B0 | 2d2d 2a2a | 0 0 | (0 0) (0 0)
4445 22:59:02.405301 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4446 22:59:02.408696 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4447 22:59:02.411703 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4448 22:59:02.418103 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4449 22:59:02.421856 0 10 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4450 22:59:02.424991 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4451 22:59:02.428189 0 10 12 | B1->B0 | 2727 2929 | 0 0 | (0 0) (0 0)
4452 22:59:02.435090 0 10 16 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
4453 22:59:02.438358 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4454 22:59:02.442009 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4455 22:59:02.448218 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4456 22:59:02.451448 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4457 22:59:02.455229 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4458 22:59:02.461403 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4459 22:59:02.464830 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4460 22:59:02.468577 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4461 22:59:02.474667 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4462 22:59:02.478577 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4463 22:59:02.481513 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4464 22:59:02.488365 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4465 22:59:02.491301 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4466 22:59:02.494864 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4467 22:59:02.501618 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4468 22:59:02.504739 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4469 22:59:02.508361 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4470 22:59:02.514657 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4471 22:59:02.517910 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4472 22:59:02.521632 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4473 22:59:02.528416 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4474 22:59:02.531523 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4475 22:59:02.534777 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4476 22:59:02.541750 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4477 22:59:02.541837 Total UI for P1: 0, mck2ui 16
4478 22:59:02.544875 best dqsien dly found for B0: ( 0, 13, 12)
4479 22:59:02.547996 Total UI for P1: 0, mck2ui 16
4480 22:59:02.551182 best dqsien dly found for B1: ( 0, 13, 12)
4481 22:59:02.558015 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4482 22:59:02.561071 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4483 22:59:02.561195
4484 22:59:02.564805 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4485 22:59:02.567818 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4486 22:59:02.571429 [Gating] SW calibration Done
4487 22:59:02.571527 ==
4488 22:59:02.574510 Dram Type= 6, Freq= 0, CH_1, rank 0
4489 22:59:02.578306 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4490 22:59:02.578394 ==
4491 22:59:02.581281 RX Vref Scan: 0
4492 22:59:02.581394
4493 22:59:02.581496 RX Vref 0 -> 0, step: 1
4494 22:59:02.581590
4495 22:59:02.584788 RX Delay -230 -> 252, step: 16
4496 22:59:02.588128 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4497 22:59:02.594232 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4498 22:59:02.597769 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4499 22:59:02.600820 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4500 22:59:02.604652 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4501 22:59:02.610885 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4502 22:59:02.614505 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4503 22:59:02.617803 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4504 22:59:02.620902 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4505 22:59:02.624221 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4506 22:59:02.630653 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4507 22:59:02.634352 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4508 22:59:02.637625 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4509 22:59:02.640744 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4510 22:59:02.647692 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4511 22:59:02.650719 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4512 22:59:02.650831 ==
4513 22:59:02.653849 Dram Type= 6, Freq= 0, CH_1, rank 0
4514 22:59:02.657443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4515 22:59:02.657528 ==
4516 22:59:02.660510 DQS Delay:
4517 22:59:02.660612 DQS0 = 0, DQS1 = 0
4518 22:59:02.664106 DQM Delay:
4519 22:59:02.664199 DQM0 = 43, DQM1 = 33
4520 22:59:02.664279 DQ Delay:
4521 22:59:02.667154 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4522 22:59:02.670786 DQ4 =41, DQ5 =49, DQ6 =57, DQ7 =41
4523 22:59:02.673913 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =33
4524 22:59:02.677445 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4525 22:59:02.677544
4526 22:59:02.677632
4527 22:59:02.677748 ==
4528 22:59:02.680487 Dram Type= 6, Freq= 0, CH_1, rank 0
4529 22:59:02.687231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4530 22:59:02.687391 ==
4531 22:59:02.687482
4532 22:59:02.687564
4533 22:59:02.687645 TX Vref Scan disable
4534 22:59:02.691406 == TX Byte 0 ==
4535 22:59:02.694551 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4536 22:59:02.701241 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4537 22:59:02.701448 == TX Byte 1 ==
4538 22:59:02.704136 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4539 22:59:02.711172 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4540 22:59:02.711412 ==
4541 22:59:02.714291 Dram Type= 6, Freq= 0, CH_1, rank 0
4542 22:59:02.717768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4543 22:59:02.717900 ==
4544 22:59:02.717973
4545 22:59:02.718052
4546 22:59:02.720840 TX Vref Scan disable
4547 22:59:02.724577 == TX Byte 0 ==
4548 22:59:02.727663 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4549 22:59:02.730900 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4550 22:59:02.734081 == TX Byte 1 ==
4551 22:59:02.737796 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4552 22:59:02.740910 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4553 22:59:02.741042
4554 22:59:02.741148 [DATLAT]
4555 22:59:02.744151 Freq=600, CH1 RK0
4556 22:59:02.744296
4557 22:59:02.744413 DATLAT Default: 0x9
4558 22:59:02.747440 0, 0xFFFF, sum = 0
4559 22:59:02.751221 1, 0xFFFF, sum = 0
4560 22:59:02.751338 2, 0xFFFF, sum = 0
4561 22:59:02.754340 3, 0xFFFF, sum = 0
4562 22:59:02.754456 4, 0xFFFF, sum = 0
4563 22:59:02.757440 5, 0xFFFF, sum = 0
4564 22:59:02.757556 6, 0xFFFF, sum = 0
4565 22:59:02.760577 7, 0xFFFF, sum = 0
4566 22:59:02.760710 8, 0x0, sum = 1
4567 22:59:02.764179 9, 0x0, sum = 2
4568 22:59:02.764323 10, 0x0, sum = 3
4569 22:59:02.764449 11, 0x0, sum = 4
4570 22:59:02.767355 best_step = 9
4571 22:59:02.767495
4572 22:59:02.767601 ==
4573 22:59:02.771102 Dram Type= 6, Freq= 0, CH_1, rank 0
4574 22:59:02.774157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4575 22:59:02.774275 ==
4576 22:59:02.777638 RX Vref Scan: 1
4577 22:59:02.777727
4578 22:59:02.777824 RX Vref 0 -> 0, step: 1
4579 22:59:02.780695
4580 22:59:02.780804 RX Delay -195 -> 252, step: 8
4581 22:59:02.780914
4582 22:59:02.783774 Set Vref, RX VrefLevel [Byte0]: 54
4583 22:59:02.787590 [Byte1]: 51
4584 22:59:02.791724
4585 22:59:02.791806 Final RX Vref Byte 0 = 54 to rank0
4586 22:59:02.795169 Final RX Vref Byte 1 = 51 to rank0
4587 22:59:02.798386 Final RX Vref Byte 0 = 54 to rank1
4588 22:59:02.801996 Final RX Vref Byte 1 = 51 to rank1==
4589 22:59:02.805069 Dram Type= 6, Freq= 0, CH_1, rank 0
4590 22:59:02.811853 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4591 22:59:02.811960 ==
4592 22:59:02.812034 DQS Delay:
4593 22:59:02.812098 DQS0 = 0, DQS1 = 0
4594 22:59:02.814910 DQM Delay:
4595 22:59:02.815022 DQM0 = 40, DQM1 = 32
4596 22:59:02.818096 DQ Delay:
4597 22:59:02.821674 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =36
4598 22:59:02.824730 DQ4 =40, DQ5 =48, DQ6 =52, DQ7 =36
4599 22:59:02.827901 DQ8 =20, DQ9 =24, DQ10 =32, DQ11 =24
4600 22:59:02.831737 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4601 22:59:02.831881
4602 22:59:02.831999
4603 22:59:02.837995 [DQSOSCAuto] RK0, (LSB)MR18= 0x470d, (MSB)MR19= 0x808, tDQSOscB0 = 407 ps tDQSOscB1 = 396 ps
4604 22:59:02.841138 CH1 RK0: MR19=808, MR18=470D
4605 22:59:02.848083 CH1_RK0: MR19=0x808, MR18=0x470D, DQSOSC=396, MR23=63, INC=167, DEC=111
4606 22:59:02.848188
4607 22:59:02.851259 ----->DramcWriteLeveling(PI) begin...
4608 22:59:02.851383 ==
4609 22:59:02.855023 Dram Type= 6, Freq= 0, CH_1, rank 1
4610 22:59:02.858252 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4611 22:59:02.858368 ==
4612 22:59:02.861396 Write leveling (Byte 0): 30 => 30
4613 22:59:02.864507 Write leveling (Byte 1): 31 => 31
4614 22:59:02.868149 DramcWriteLeveling(PI) end<-----
4615 22:59:02.868236
4616 22:59:02.868304 ==
4617 22:59:02.871221 Dram Type= 6, Freq= 0, CH_1, rank 1
4618 22:59:02.874764 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4619 22:59:02.874852 ==
4620 22:59:02.877922 [Gating] SW mode calibration
4621 22:59:02.884747 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4622 22:59:02.891317 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4623 22:59:02.895003 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4624 22:59:02.901132 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4625 22:59:02.904692 0 9 8 | B1->B0 | 3535 3434 | 0 0 | (0 0) (0 0)
4626 22:59:02.907822 0 9 12 | B1->B0 | 2f2f 2d2d | 0 0 | (0 0) (0 0)
4627 22:59:02.911279 0 9 16 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
4628 22:59:02.917765 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4629 22:59:02.920977 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4630 22:59:02.924220 0 9 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4631 22:59:02.930808 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4632 22:59:02.934470 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4633 22:59:02.937656 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4634 22:59:02.944543 0 10 12 | B1->B0 | 3030 3e3e | 0 0 | (0 0) (0 0)
4635 22:59:02.947732 0 10 16 | B1->B0 | 4444 4646 | 0 0 | (1 1) (0 0)
4636 22:59:02.950874 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4637 22:59:02.957179 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4638 22:59:02.960325 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4639 22:59:02.964186 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4640 22:59:02.970450 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4641 22:59:02.974097 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4642 22:59:02.977134 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4643 22:59:02.983806 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4644 22:59:02.986935 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4645 22:59:02.990567 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4646 22:59:02.997365 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4647 22:59:03.000328 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4648 22:59:03.003800 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4649 22:59:03.010611 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4650 22:59:03.013806 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4651 22:59:03.016876 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4652 22:59:03.023335 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4653 22:59:03.027008 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4654 22:59:03.030666 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4655 22:59:03.036684 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4656 22:59:03.040534 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4657 22:59:03.043669 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4658 22:59:03.050233 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4659 22:59:03.053940 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4660 22:59:03.057099 Total UI for P1: 0, mck2ui 16
4661 22:59:03.060189 best dqsien dly found for B0: ( 0, 13, 10)
4662 22:59:03.063398 Total UI for P1: 0, mck2ui 16
4663 22:59:03.066569 best dqsien dly found for B1: ( 0, 13, 14)
4664 22:59:03.070257 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4665 22:59:03.073378 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4666 22:59:03.073465
4667 22:59:03.076623 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4668 22:59:03.080147 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4669 22:59:03.083221 [Gating] SW calibration Done
4670 22:59:03.083354 ==
4671 22:59:03.086925 Dram Type= 6, Freq= 0, CH_1, rank 1
4672 22:59:03.090010 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4673 22:59:03.093604 ==
4674 22:59:03.093728 RX Vref Scan: 0
4675 22:59:03.093828
4676 22:59:03.096738 RX Vref 0 -> 0, step: 1
4677 22:59:03.096858
4678 22:59:03.100297 RX Delay -230 -> 252, step: 16
4679 22:59:03.103496 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4680 22:59:03.106496 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4681 22:59:03.109974 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4682 22:59:03.113111 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4683 22:59:03.119968 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4684 22:59:03.123571 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4685 22:59:03.126563 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4686 22:59:03.130287 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4687 22:59:03.137112 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4688 22:59:03.140211 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4689 22:59:03.143115 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4690 22:59:03.147089 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4691 22:59:03.153186 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4692 22:59:03.156932 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4693 22:59:03.160073 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4694 22:59:03.163291 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4695 22:59:03.163413 ==
4696 22:59:03.166519 Dram Type= 6, Freq= 0, CH_1, rank 1
4697 22:59:03.173366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4698 22:59:03.173484 ==
4699 22:59:03.173593 DQS Delay:
4700 22:59:03.173695 DQS0 = 0, DQS1 = 0
4701 22:59:03.176435 DQM Delay:
4702 22:59:03.176548 DQM0 = 37, DQM1 = 35
4703 22:59:03.180256 DQ Delay:
4704 22:59:03.183427 DQ0 =41, DQ1 =33, DQ2 =25, DQ3 =33
4705 22:59:03.186435 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4706 22:59:03.189629 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =25
4707 22:59:03.193179 DQ12 =41, DQ13 =49, DQ14 =41, DQ15 =41
4708 22:59:03.193296
4709 22:59:03.193398
4710 22:59:03.193498 ==
4711 22:59:03.196323 Dram Type= 6, Freq= 0, CH_1, rank 1
4712 22:59:03.200107 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4713 22:59:03.200216 ==
4714 22:59:03.200314
4715 22:59:03.200408
4716 22:59:03.203012 TX Vref Scan disable
4717 22:59:03.203119 == TX Byte 0 ==
4718 22:59:03.209787 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4719 22:59:03.212840 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4720 22:59:03.212958 == TX Byte 1 ==
4721 22:59:03.220121 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4722 22:59:03.223182 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4723 22:59:03.223293 ==
4724 22:59:03.226235 Dram Type= 6, Freq= 0, CH_1, rank 1
4725 22:59:03.229305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4726 22:59:03.229415 ==
4727 22:59:03.229515
4728 22:59:03.232974
4729 22:59:03.233081 TX Vref Scan disable
4730 22:59:03.236655 == TX Byte 0 ==
4731 22:59:03.239742 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4732 22:59:03.246337 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4733 22:59:03.246462 == TX Byte 1 ==
4734 22:59:03.249634 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4735 22:59:03.256019 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4736 22:59:03.256146
4737 22:59:03.256277 [DATLAT]
4738 22:59:03.256379 Freq=600, CH1 RK1
4739 22:59:03.256480
4740 22:59:03.259065 DATLAT Default: 0x9
4741 22:59:03.259179 0, 0xFFFF, sum = 0
4742 22:59:03.262776 1, 0xFFFF, sum = 0
4743 22:59:03.265819 2, 0xFFFF, sum = 0
4744 22:59:03.265930 3, 0xFFFF, sum = 0
4745 22:59:03.269619 4, 0xFFFF, sum = 0
4746 22:59:03.269735 5, 0xFFFF, sum = 0
4747 22:59:03.272893 6, 0xFFFF, sum = 0
4748 22:59:03.273012 7, 0xFFFF, sum = 0
4749 22:59:03.276126 8, 0x0, sum = 1
4750 22:59:03.276239 9, 0x0, sum = 2
4751 22:59:03.276339 10, 0x0, sum = 3
4752 22:59:03.279220 11, 0x0, sum = 4
4753 22:59:03.279333 best_step = 9
4754 22:59:03.279418
4755 22:59:03.279491 ==
4756 22:59:03.282956 Dram Type= 6, Freq= 0, CH_1, rank 1
4757 22:59:03.289228 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4758 22:59:03.289340 ==
4759 22:59:03.289439 RX Vref Scan: 0
4760 22:59:03.289534
4761 22:59:03.292181 RX Vref 0 -> 0, step: 1
4762 22:59:03.292291
4763 22:59:03.295770 RX Delay -179 -> 252, step: 8
4764 22:59:03.299424 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4765 22:59:03.305530 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4766 22:59:03.309131 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4767 22:59:03.312366 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4768 22:59:03.316051 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4769 22:59:03.322082 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4770 22:59:03.325871 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4771 22:59:03.328869 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4772 22:59:03.332527 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4773 22:59:03.335630 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4774 22:59:03.342393 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4775 22:59:03.345613 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4776 22:59:03.349120 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4777 22:59:03.352215 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4778 22:59:03.358741 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4779 22:59:03.362567 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4780 22:59:03.362672 ==
4781 22:59:03.365764 Dram Type= 6, Freq= 0, CH_1, rank 1
4782 22:59:03.368862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4783 22:59:03.368961 ==
4784 22:59:03.371937 DQS Delay:
4785 22:59:03.372023 DQS0 = 0, DQS1 = 0
4786 22:59:03.372093 DQM Delay:
4787 22:59:03.375698 DQM0 = 37, DQM1 = 32
4788 22:59:03.375790 DQ Delay:
4789 22:59:03.378955 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =36
4790 22:59:03.382065 DQ4 =40, DQ5 =48, DQ6 =48, DQ7 =32
4791 22:59:03.385105 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =24
4792 22:59:03.389086 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4793 22:59:03.389178
4794 22:59:03.389247
4795 22:59:03.398859 [DQSOSCAuto] RK1, (LSB)MR18= 0x3442, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 400 ps
4796 22:59:03.401901 CH1 RK1: MR19=808, MR18=3442
4797 22:59:03.405457 CH1_RK1: MR19=0x808, MR18=0x3442, DQSOSC=397, MR23=63, INC=166, DEC=110
4798 22:59:03.408560 [RxdqsGatingPostProcess] freq 600
4799 22:59:03.415469 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4800 22:59:03.418551 Pre-setting of DQS Precalculation
4801 22:59:03.421613 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4802 22:59:03.431916 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4803 22:59:03.438763 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4804 22:59:03.438881
4805 22:59:03.438980
4806 22:59:03.441782 [Calibration Summary] 1200 Mbps
4807 22:59:03.441893 CH 0, Rank 0
4808 22:59:03.445011 SW Impedance : PASS
4809 22:59:03.445132 DUTY Scan : NO K
4810 22:59:03.448255 ZQ Calibration : PASS
4811 22:59:03.451965 Jitter Meter : NO K
4812 22:59:03.452083 CBT Training : PASS
4813 22:59:03.454916 Write leveling : PASS
4814 22:59:03.458646 RX DQS gating : PASS
4815 22:59:03.458767 RX DQ/DQS(RDDQC) : PASS
4816 22:59:03.461768 TX DQ/DQS : PASS
4817 22:59:03.461886 RX DATLAT : PASS
4818 22:59:03.464894 RX DQ/DQS(Engine): PASS
4819 22:59:03.468130 TX OE : NO K
4820 22:59:03.468245 All Pass.
4821 22:59:03.468344
4822 22:59:03.471830 CH 0, Rank 1
4823 22:59:03.471936 SW Impedance : PASS
4824 22:59:03.475004 DUTY Scan : NO K
4825 22:59:03.475110 ZQ Calibration : PASS
4826 22:59:03.478296 Jitter Meter : NO K
4827 22:59:03.481453 CBT Training : PASS
4828 22:59:03.481566 Write leveling : PASS
4829 22:59:03.485340 RX DQS gating : PASS
4830 22:59:03.488432 RX DQ/DQS(RDDQC) : PASS
4831 22:59:03.488543 TX DQ/DQS : PASS
4832 22:59:03.491682 RX DATLAT : PASS
4833 22:59:03.495388 RX DQ/DQS(Engine): PASS
4834 22:59:03.495498 TX OE : NO K
4835 22:59:03.498475 All Pass.
4836 22:59:03.498594
4837 22:59:03.498693 CH 1, Rank 0
4838 22:59:03.502212 SW Impedance : PASS
4839 22:59:03.502319 DUTY Scan : NO K
4840 22:59:03.505223 ZQ Calibration : PASS
4841 22:59:03.508774 Jitter Meter : NO K
4842 22:59:03.508860 CBT Training : PASS
4843 22:59:03.511748 Write leveling : PASS
4844 22:59:03.511862 RX DQS gating : PASS
4845 22:59:03.514815 RX DQ/DQS(RDDQC) : PASS
4846 22:59:03.518435 TX DQ/DQS : PASS
4847 22:59:03.518558 RX DATLAT : PASS
4848 22:59:03.521545 RX DQ/DQS(Engine): PASS
4849 22:59:03.525017 TX OE : NO K
4850 22:59:03.525134 All Pass.
4851 22:59:03.525231
4852 22:59:03.525338 CH 1, Rank 1
4853 22:59:03.528164 SW Impedance : PASS
4854 22:59:03.531723 DUTY Scan : NO K
4855 22:59:03.531809 ZQ Calibration : PASS
4856 22:59:03.534894 Jitter Meter : NO K
4857 22:59:03.538299 CBT Training : PASS
4858 22:59:03.538410 Write leveling : PASS
4859 22:59:03.541353 RX DQS gating : PASS
4860 22:59:03.545163 RX DQ/DQS(RDDQC) : PASS
4861 22:59:03.545271 TX DQ/DQS : PASS
4862 22:59:03.548116 RX DATLAT : PASS
4863 22:59:03.551890 RX DQ/DQS(Engine): PASS
4864 22:59:03.551978 TX OE : NO K
4865 22:59:03.554979 All Pass.
4866 22:59:03.555065
4867 22:59:03.555167 DramC Write-DBI off
4868 22:59:03.558041 PER_BANK_REFRESH: Hybrid Mode
4869 22:59:03.558126 TX_TRACKING: ON
4870 22:59:03.568203 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4871 22:59:03.571444 [FAST_K] Save calibration result to emmc
4872 22:59:03.574568 dramc_set_vcore_voltage set vcore to 662500
4873 22:59:03.577864 Read voltage for 933, 3
4874 22:59:03.577983 Vio18 = 0
4875 22:59:03.581585 Vcore = 662500
4876 22:59:03.581704 Vdram = 0
4877 22:59:03.581814 Vddq = 0
4878 22:59:03.581923 Vmddr = 0
4879 22:59:03.587980 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4880 22:59:03.594684 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4881 22:59:03.594798 MEM_TYPE=3, freq_sel=17
4882 22:59:03.597908 sv_algorithm_assistance_LP4_1600
4883 22:59:03.601519 ============ PULL DRAM RESETB DOWN ============
4884 22:59:03.607791 ========== PULL DRAM RESETB DOWN end =========
4885 22:59:03.611266 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4886 22:59:03.614309 ===================================
4887 22:59:03.618064 LPDDR4 DRAM CONFIGURATION
4888 22:59:03.621122 ===================================
4889 22:59:03.621231 EX_ROW_EN[0] = 0x0
4890 22:59:03.624782 EX_ROW_EN[1] = 0x0
4891 22:59:03.624893 LP4Y_EN = 0x0
4892 22:59:03.627857 WORK_FSP = 0x0
4893 22:59:03.627980 WL = 0x3
4894 22:59:03.631333 RL = 0x3
4895 22:59:03.634266 BL = 0x2
4896 22:59:03.634374 RPST = 0x0
4897 22:59:03.637987 RD_PRE = 0x0
4898 22:59:03.638104 WR_PRE = 0x1
4899 22:59:03.640934 WR_PST = 0x0
4900 22:59:03.641048 DBI_WR = 0x0
4901 22:59:03.644891 DBI_RD = 0x0
4902 22:59:03.645011 OTF = 0x1
4903 22:59:03.647903 ===================================
4904 22:59:03.651346 ===================================
4905 22:59:03.654359 ANA top config
4906 22:59:03.658104 ===================================
4907 22:59:03.658231 DLL_ASYNC_EN = 0
4908 22:59:03.661151 ALL_SLAVE_EN = 1
4909 22:59:03.664157 NEW_RANK_MODE = 1
4910 22:59:03.667958 DLL_IDLE_MODE = 1
4911 22:59:03.668069 LP45_APHY_COMB_EN = 1
4912 22:59:03.671212 TX_ODT_DIS = 1
4913 22:59:03.674329 NEW_8X_MODE = 1
4914 22:59:03.677559 ===================================
4915 22:59:03.681291 ===================================
4916 22:59:03.684597 data_rate = 1866
4917 22:59:03.687681 CKR = 1
4918 22:59:03.690955 DQ_P2S_RATIO = 8
4919 22:59:03.694278 ===================================
4920 22:59:03.694387 CA_P2S_RATIO = 8
4921 22:59:03.697538 DQ_CA_OPEN = 0
4922 22:59:03.701014 DQ_SEMI_OPEN = 0
4923 22:59:03.704272 CA_SEMI_OPEN = 0
4924 22:59:03.707833 CA_FULL_RATE = 0
4925 22:59:03.707939 DQ_CKDIV4_EN = 1
4926 22:59:03.710994 CA_CKDIV4_EN = 1
4927 22:59:03.713902 CA_PREDIV_EN = 0
4928 22:59:03.717515 PH8_DLY = 0
4929 22:59:03.721138 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4930 22:59:03.724106 DQ_AAMCK_DIV = 4
4931 22:59:03.727092 CA_AAMCK_DIV = 4
4932 22:59:03.727178 CA_ADMCK_DIV = 4
4933 22:59:03.730720 DQ_TRACK_CA_EN = 0
4934 22:59:03.734010 CA_PICK = 933
4935 22:59:03.737504 CA_MCKIO = 933
4936 22:59:03.740731 MCKIO_SEMI = 0
4937 22:59:03.744213 PLL_FREQ = 3732
4938 22:59:03.747163 DQ_UI_PI_RATIO = 32
4939 22:59:03.747285 CA_UI_PI_RATIO = 0
4940 22:59:03.750296 ===================================
4941 22:59:03.754146 ===================================
4942 22:59:03.757200 memory_type:LPDDR4
4943 22:59:03.760281 GP_NUM : 10
4944 22:59:03.760388 SRAM_EN : 1
4945 22:59:03.763895 MD32_EN : 0
4946 22:59:03.766828 ===================================
4947 22:59:03.770610 [ANA_INIT] >>>>>>>>>>>>>>
4948 22:59:03.773361 <<<<<< [CONFIGURE PHASE]: ANA_TX
4949 22:59:03.776919 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4950 22:59:03.779998 ===================================
4951 22:59:03.780116 data_rate = 1866,PCW = 0X8f00
4952 22:59:03.783793 ===================================
4953 22:59:03.786901 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4954 22:59:03.793363 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4955 22:59:03.800333 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4956 22:59:03.803570 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4957 22:59:03.806543 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4958 22:59:03.809724 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4959 22:59:03.813429 [ANA_INIT] flow start
4960 22:59:03.816937 [ANA_INIT] PLL >>>>>>>>
4961 22:59:03.817056 [ANA_INIT] PLL <<<<<<<<
4962 22:59:03.819911 [ANA_INIT] MIDPI >>>>>>>>
4963 22:59:03.823631 [ANA_INIT] MIDPI <<<<<<<<
4964 22:59:03.823750 [ANA_INIT] DLL >>>>>>>>
4965 22:59:03.826687 [ANA_INIT] flow end
4966 22:59:03.830220 ============ LP4 DIFF to SE enter ============
4967 22:59:03.833320 ============ LP4 DIFF to SE exit ============
4968 22:59:03.837141 [ANA_INIT] <<<<<<<<<<<<<
4969 22:59:03.840205 [Flow] Enable top DCM control >>>>>
4970 22:59:03.843140 [Flow] Enable top DCM control <<<<<
4971 22:59:03.846916 Enable DLL master slave shuffle
4972 22:59:03.853393 ==============================================================
4973 22:59:03.853519 Gating Mode config
4974 22:59:03.859680 ==============================================================
4975 22:59:03.859792 Config description:
4976 22:59:03.870129 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4977 22:59:03.876308 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4978 22:59:03.883278 SELPH_MODE 0: By rank 1: By Phase
4979 22:59:03.886463 ==============================================================
4980 22:59:03.889672 GAT_TRACK_EN = 1
4981 22:59:03.892937 RX_GATING_MODE = 2
4982 22:59:03.896083 RX_GATING_TRACK_MODE = 2
4983 22:59:03.899885 SELPH_MODE = 1
4984 22:59:03.902953 PICG_EARLY_EN = 1
4985 22:59:03.906014 VALID_LAT_VALUE = 1
4986 22:59:03.913097 ==============================================================
4987 22:59:03.916147 Enter into Gating configuration >>>>
4988 22:59:03.919869 Exit from Gating configuration <<<<
4989 22:59:03.919984 Enter into DVFS_PRE_config >>>>>
4990 22:59:03.932869 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4991 22:59:03.936137 Exit from DVFS_PRE_config <<<<<
4992 22:59:03.939058 Enter into PICG configuration >>>>
4993 22:59:03.942686 Exit from PICG configuration <<<<
4994 22:59:03.945839 [RX_INPUT] configuration >>>>>
4995 22:59:03.946013 [RX_INPUT] configuration <<<<<
4996 22:59:03.953182 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4997 22:59:03.959197 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4998 22:59:03.962175 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4999 22:59:03.968978 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5000 22:59:03.975653 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5001 22:59:03.982513 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5002 22:59:03.985661 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5003 22:59:03.988932 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5004 22:59:03.995831 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5005 22:59:03.998953 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5006 22:59:04.002171 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5007 22:59:04.005845 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5008 22:59:04.009061 ===================================
5009 22:59:04.012243 LPDDR4 DRAM CONFIGURATION
5010 22:59:04.016016 ===================================
5011 22:59:04.019339 EX_ROW_EN[0] = 0x0
5012 22:59:04.019458 EX_ROW_EN[1] = 0x0
5013 22:59:04.022280 LP4Y_EN = 0x0
5014 22:59:04.022383 WORK_FSP = 0x0
5015 22:59:04.026098 WL = 0x3
5016 22:59:04.026210 RL = 0x3
5017 22:59:04.029156 BL = 0x2
5018 22:59:04.029243 RPST = 0x0
5019 22:59:04.032806 RD_PRE = 0x0
5020 22:59:04.032892 WR_PRE = 0x1
5021 22:59:04.035769 WR_PST = 0x0
5022 22:59:04.039290 DBI_WR = 0x0
5023 22:59:04.039413 DBI_RD = 0x0
5024 22:59:04.042219 OTF = 0x1
5025 22:59:04.045662 ===================================
5026 22:59:04.048665 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5027 22:59:04.052247 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5028 22:59:04.055821 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5029 22:59:04.058904 ===================================
5030 22:59:04.062099 LPDDR4 DRAM CONFIGURATION
5031 22:59:04.065184 ===================================
5032 22:59:04.068905 EX_ROW_EN[0] = 0x10
5033 22:59:04.068992 EX_ROW_EN[1] = 0x0
5034 22:59:04.071848 LP4Y_EN = 0x0
5035 22:59:04.071943 WORK_FSP = 0x0
5036 22:59:04.075606 WL = 0x3
5037 22:59:04.075693 RL = 0x3
5038 22:59:04.078706 BL = 0x2
5039 22:59:04.078793 RPST = 0x0
5040 22:59:04.081757 RD_PRE = 0x0
5041 22:59:04.081870 WR_PRE = 0x1
5042 22:59:04.085634 WR_PST = 0x0
5043 22:59:04.085764 DBI_WR = 0x0
5044 22:59:04.088724 DBI_RD = 0x0
5045 22:59:04.091971 OTF = 0x1
5046 22:59:04.095087 ===================================
5047 22:59:04.098232 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5048 22:59:04.103901 nWR fixed to 30
5049 22:59:04.107192 [ModeRegInit_LP4] CH0 RK0
5050 22:59:04.107306 [ModeRegInit_LP4] CH0 RK1
5051 22:59:04.110315 [ModeRegInit_LP4] CH1 RK0
5052 22:59:04.113634 [ModeRegInit_LP4] CH1 RK1
5053 22:59:04.113746 match AC timing 9
5054 22:59:04.120369 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5055 22:59:04.123574 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5056 22:59:04.126679 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5057 22:59:04.133588 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5058 22:59:04.136544 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5059 22:59:04.136676 ==
5060 22:59:04.139855 Dram Type= 6, Freq= 0, CH_0, rank 0
5061 22:59:04.143588 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5062 22:59:04.143676 ==
5063 22:59:04.149962 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5064 22:59:04.156422 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5065 22:59:04.160078 [CA 0] Center 38 (8~69) winsize 62
5066 22:59:04.163623 [CA 1] Center 38 (7~69) winsize 63
5067 22:59:04.166647 [CA 2] Center 35 (5~66) winsize 62
5068 22:59:04.169643 [CA 3] Center 35 (5~65) winsize 61
5069 22:59:04.173211 [CA 4] Center 34 (3~65) winsize 63
5070 22:59:04.176928 [CA 5] Center 33 (3~64) winsize 62
5071 22:59:04.177048
5072 22:59:04.179995 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5073 22:59:04.180097
5074 22:59:04.183091 [CATrainingPosCal] consider 1 rank data
5075 22:59:04.186221 u2DelayCellTimex100 = 270/100 ps
5076 22:59:04.189522 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5077 22:59:04.193248 CA1 delay=38 (7~69),Diff = 5 PI (31 cell)
5078 22:59:04.196456 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5079 22:59:04.199632 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5080 22:59:04.203406 CA4 delay=34 (3~65),Diff = 1 PI (6 cell)
5081 22:59:04.209731 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5082 22:59:04.209813
5083 22:59:04.212965 CA PerBit enable=1, Macro0, CA PI delay=33
5084 22:59:04.213039
5085 22:59:04.216206 [CBTSetCACLKResult] CA Dly = 33
5086 22:59:04.216282 CS Dly: 6 (0~37)
5087 22:59:04.216345 ==
5088 22:59:04.219884 Dram Type= 6, Freq= 0, CH_0, rank 1
5089 22:59:04.222965 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5090 22:59:04.226819 ==
5091 22:59:04.229864 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5092 22:59:04.236291 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5093 22:59:04.239939 [CA 0] Center 38 (8~69) winsize 62
5094 22:59:04.242926 [CA 1] Center 38 (8~69) winsize 62
5095 22:59:04.246634 [CA 2] Center 35 (5~66) winsize 62
5096 22:59:04.250010 [CA 3] Center 35 (5~66) winsize 62
5097 22:59:04.253119 [CA 4] Center 34 (3~65) winsize 63
5098 22:59:04.256665 [CA 5] Center 33 (3~64) winsize 62
5099 22:59:04.256795
5100 22:59:04.259546 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5101 22:59:04.259662
5102 22:59:04.263018 [CATrainingPosCal] consider 2 rank data
5103 22:59:04.266178 u2DelayCellTimex100 = 270/100 ps
5104 22:59:04.269652 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5105 22:59:04.272774 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5106 22:59:04.276391 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5107 22:59:04.279602 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5108 22:59:04.286138 CA4 delay=34 (3~65),Diff = 1 PI (6 cell)
5109 22:59:04.289903 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5110 22:59:04.290019
5111 22:59:04.293004 CA PerBit enable=1, Macro0, CA PI delay=33
5112 22:59:04.293108
5113 22:59:04.296226 [CBTSetCACLKResult] CA Dly = 33
5114 22:59:04.296331 CS Dly: 7 (0~39)
5115 22:59:04.296424
5116 22:59:04.299463 ----->DramcWriteLeveling(PI) begin...
5117 22:59:04.299573 ==
5118 22:59:04.303152 Dram Type= 6, Freq= 0, CH_0, rank 0
5119 22:59:04.309208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5120 22:59:04.309322 ==
5121 22:59:04.313097 Write leveling (Byte 0): 30 => 30
5122 22:59:04.316172 Write leveling (Byte 1): 29 => 29
5123 22:59:04.316277 DramcWriteLeveling(PI) end<-----
5124 22:59:04.316373
5125 22:59:04.319447 ==
5126 22:59:04.322674 Dram Type= 6, Freq= 0, CH_0, rank 0
5127 22:59:04.326278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5128 22:59:04.326394 ==
5129 22:59:04.329448 [Gating] SW mode calibration
5130 22:59:04.335742 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5131 22:59:04.338961 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5132 22:59:04.345927 0 14 0 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (1 1)
5133 22:59:04.349485 0 14 4 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
5134 22:59:04.352485 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5135 22:59:04.359128 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5136 22:59:04.362804 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5137 22:59:04.366268 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5138 22:59:04.372801 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5139 22:59:04.375938 0 14 28 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5140 22:59:04.379299 0 15 0 | B1->B0 | 3131 2e2e | 1 0 | (0 1) (1 0)
5141 22:59:04.385695 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5142 22:59:04.389277 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5143 22:59:04.392397 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5144 22:59:04.399415 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5145 22:59:04.402063 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5146 22:59:04.405741 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5147 22:59:04.412069 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5148 22:59:04.415962 1 0 0 | B1->B0 | 3130 3a3a | 1 0 | (0 0) (1 1)
5149 22:59:04.418971 1 0 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5150 22:59:04.425414 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5151 22:59:04.428891 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5152 22:59:04.432070 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5153 22:59:04.438968 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5154 22:59:04.442012 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5155 22:59:04.445136 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5156 22:59:04.452021 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5157 22:59:04.455293 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5158 22:59:04.458616 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5159 22:59:04.462023 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5160 22:59:04.468611 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5161 22:59:04.472186 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5162 22:59:04.475244 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5163 22:59:04.482000 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5164 22:59:04.485630 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5165 22:59:04.488573 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5166 22:59:04.495561 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5167 22:59:04.498643 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5168 22:59:04.501678 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5169 22:59:04.508840 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5170 22:59:04.511925 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5171 22:59:04.514912 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5172 22:59:04.521870 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5173 22:59:04.524972 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5174 22:59:04.528790 Total UI for P1: 0, mck2ui 16
5175 22:59:04.531825 best dqsien dly found for B0: ( 1, 2, 30)
5176 22:59:04.534887 Total UI for P1: 0, mck2ui 16
5177 22:59:04.538635 best dqsien dly found for B1: ( 1, 2, 30)
5178 22:59:04.541796 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5179 22:59:04.544876 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5180 22:59:04.544991
5181 22:59:04.548603 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5182 22:59:04.551790 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5183 22:59:04.554773 [Gating] SW calibration Done
5184 22:59:04.554896 ==
5185 22:59:04.558058 Dram Type= 6, Freq= 0, CH_0, rank 0
5186 22:59:04.561693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5187 22:59:04.564844 ==
5188 22:59:04.564961 RX Vref Scan: 0
5189 22:59:04.565077
5190 22:59:04.568240 RX Vref 0 -> 0, step: 1
5191 22:59:04.568326
5192 22:59:04.571757 RX Delay -80 -> 252, step: 8
5193 22:59:04.574674 iDelay=208, Bit 0, Center 99 (8 ~ 191) 184
5194 22:59:04.577984 iDelay=208, Bit 1, Center 103 (8 ~ 199) 192
5195 22:59:04.581592 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5196 22:59:04.585163 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5197 22:59:04.588266 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5198 22:59:04.594644 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5199 22:59:04.598155 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5200 22:59:04.601148 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5201 22:59:04.604802 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5202 22:59:04.608313 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5203 22:59:04.611492 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5204 22:59:04.617706 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5205 22:59:04.621483 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5206 22:59:04.624824 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5207 22:59:04.627967 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5208 22:59:04.631159 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5209 22:59:04.631271 ==
5210 22:59:04.634308 Dram Type= 6, Freq= 0, CH_0, rank 0
5211 22:59:04.641065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5212 22:59:04.641179 ==
5213 22:59:04.641291 DQS Delay:
5214 22:59:04.644802 DQS0 = 0, DQS1 = 0
5215 22:59:04.644924 DQM Delay:
5216 22:59:04.645024 DQM0 = 99, DQM1 = 87
5217 22:59:04.648098 DQ Delay:
5218 22:59:04.651249 DQ0 =99, DQ1 =103, DQ2 =95, DQ3 =95
5219 22:59:04.654461 DQ4 =103, DQ5 =87, DQ6 =107, DQ7 =103
5220 22:59:04.657543 DQ8 =79, DQ9 =71, DQ10 =87, DQ11 =79
5221 22:59:04.661354 DQ12 =95, DQ13 =95, DQ14 =99, DQ15 =95
5222 22:59:04.661477
5223 22:59:04.661580
5224 22:59:04.661683 ==
5225 22:59:04.664428 Dram Type= 6, Freq= 0, CH_0, rank 0
5226 22:59:04.667954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5227 22:59:04.668043 ==
5228 22:59:04.668123
5229 22:59:04.668193
5230 22:59:04.671124 TX Vref Scan disable
5231 22:59:04.674433 == TX Byte 0 ==
5232 22:59:04.677352 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5233 22:59:04.681006 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5234 22:59:04.684339 == TX Byte 1 ==
5235 22:59:04.687481 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5236 22:59:04.691045 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5237 22:59:04.691158 ==
5238 22:59:04.694617 Dram Type= 6, Freq= 0, CH_0, rank 0
5239 22:59:04.697595 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5240 22:59:04.700559 ==
5241 22:59:04.700674
5242 22:59:04.700777
5243 22:59:04.700873 TX Vref Scan disable
5244 22:59:04.704735 == TX Byte 0 ==
5245 22:59:04.708304 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5246 22:59:04.714616 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5247 22:59:04.714725 == TX Byte 1 ==
5248 22:59:04.717627 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5249 22:59:04.724642 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5250 22:59:04.724764
5251 22:59:04.724886 [DATLAT]
5252 22:59:04.724993 Freq=933, CH0 RK0
5253 22:59:04.725108
5254 22:59:04.727701 DATLAT Default: 0xd
5255 22:59:04.727816 0, 0xFFFF, sum = 0
5256 22:59:04.731465 1, 0xFFFF, sum = 0
5257 22:59:04.734535 2, 0xFFFF, sum = 0
5258 22:59:04.734647 3, 0xFFFF, sum = 0
5259 22:59:04.737727 4, 0xFFFF, sum = 0
5260 22:59:04.737816 5, 0xFFFF, sum = 0
5261 22:59:04.740958 6, 0xFFFF, sum = 0
5262 22:59:04.741045 7, 0xFFFF, sum = 0
5263 22:59:04.744448 8, 0xFFFF, sum = 0
5264 22:59:04.744535 9, 0xFFFF, sum = 0
5265 22:59:04.747657 10, 0x0, sum = 1
5266 22:59:04.747773 11, 0x0, sum = 2
5267 22:59:04.751493 12, 0x0, sum = 3
5268 22:59:04.751582 13, 0x0, sum = 4
5269 22:59:04.751651 best_step = 11
5270 22:59:04.751714
5271 22:59:04.754543 ==
5272 22:59:04.757827 Dram Type= 6, Freq= 0, CH_0, rank 0
5273 22:59:04.761506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5274 22:59:04.761635 ==
5275 22:59:04.761735 RX Vref Scan: 1
5276 22:59:04.761847
5277 22:59:04.764630 RX Vref 0 -> 0, step: 1
5278 22:59:04.764718
5279 22:59:04.767878 RX Delay -69 -> 252, step: 4
5280 22:59:04.767963
5281 22:59:04.770956 Set Vref, RX VrefLevel [Byte0]: 52
5282 22:59:04.774215 [Byte1]: 50
5283 22:59:04.774301
5284 22:59:04.777851 Final RX Vref Byte 0 = 52 to rank0
5285 22:59:04.780936 Final RX Vref Byte 1 = 50 to rank0
5286 22:59:04.784530 Final RX Vref Byte 0 = 52 to rank1
5287 22:59:04.787494 Final RX Vref Byte 1 = 50 to rank1==
5288 22:59:04.791013 Dram Type= 6, Freq= 0, CH_0, rank 0
5289 22:59:04.794508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5290 22:59:04.794591 ==
5291 22:59:04.797578 DQS Delay:
5292 22:59:04.797658 DQS0 = 0, DQS1 = 0
5293 22:59:04.801103 DQM Delay:
5294 22:59:04.801184 DQM0 = 97, DQM1 = 88
5295 22:59:04.801252 DQ Delay:
5296 22:59:04.804759 DQ0 =98, DQ1 =98, DQ2 =94, DQ3 =96
5297 22:59:04.807622 DQ4 =100, DQ5 =86, DQ6 =106, DQ7 =104
5298 22:59:04.810597 DQ8 =78, DQ9 =74, DQ10 =88, DQ11 =80
5299 22:59:04.817681 DQ12 =94, DQ13 =90, DQ14 =102, DQ15 =98
5300 22:59:04.817796
5301 22:59:04.817924
5302 22:59:04.824388 [DQSOSCAuto] RK0, (LSB)MR18= 0x12fd, (MSB)MR19= 0x504, tDQSOscB0 = 423 ps tDQSOscB1 = 416 ps
5303 22:59:04.827271 CH0 RK0: MR19=504, MR18=12FD
5304 22:59:04.833717 CH0_RK0: MR19=0x504, MR18=0x12FD, DQSOSC=416, MR23=63, INC=62, DEC=41
5305 22:59:04.833837
5306 22:59:04.837364 ----->DramcWriteLeveling(PI) begin...
5307 22:59:04.837488 ==
5308 22:59:04.840635 Dram Type= 6, Freq= 0, CH_0, rank 1
5309 22:59:04.843832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5310 22:59:04.843910 ==
5311 22:59:04.847521 Write leveling (Byte 0): 29 => 29
5312 22:59:04.850558 Write leveling (Byte 1): 29 => 29
5313 22:59:04.854431 DramcWriteLeveling(PI) end<-----
5314 22:59:04.854516
5315 22:59:04.854584 ==
5316 22:59:04.856969 Dram Type= 6, Freq= 0, CH_0, rank 1
5317 22:59:04.860645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5318 22:59:04.860730 ==
5319 22:59:04.863811 [Gating] SW mode calibration
5320 22:59:04.870835 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5321 22:59:04.877016 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5322 22:59:04.880192 0 14 0 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
5323 22:59:04.884074 0 14 4 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
5324 22:59:04.890175 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5325 22:59:04.893667 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5326 22:59:04.897179 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5327 22:59:04.903933 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5328 22:59:04.906875 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5329 22:59:04.910593 0 14 28 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 0)
5330 22:59:04.917083 0 15 0 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
5331 22:59:04.920328 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5332 22:59:04.923739 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5333 22:59:04.930500 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5334 22:59:04.933621 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5335 22:59:04.936839 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5336 22:59:04.943757 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5337 22:59:04.946930 0 15 28 | B1->B0 | 2424 3a3a | 0 0 | (0 0) (0 0)
5338 22:59:04.949990 1 0 0 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
5339 22:59:04.956698 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5340 22:59:04.959900 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5341 22:59:04.963080 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5342 22:59:04.969958 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5343 22:59:04.973190 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5344 22:59:04.976861 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5345 22:59:04.983213 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
5346 22:59:04.987037 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5347 22:59:04.990080 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5348 22:59:04.996850 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5349 22:59:05.000001 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5350 22:59:05.003503 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5351 22:59:05.010305 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5352 22:59:05.013336 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5353 22:59:05.016348 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5354 22:59:05.023043 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5355 22:59:05.026661 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5356 22:59:05.029708 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5357 22:59:05.033216 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5358 22:59:05.040120 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5359 22:59:05.043184 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5360 22:59:05.046397 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5361 22:59:05.053267 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5362 22:59:05.056350 Total UI for P1: 0, mck2ui 16
5363 22:59:05.059570 best dqsien dly found for B0: ( 1, 2, 26)
5364 22:59:05.062727 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5365 22:59:05.066392 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5366 22:59:05.073255 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5367 22:59:05.076523 Total UI for P1: 0, mck2ui 16
5368 22:59:05.079640 best dqsien dly found for B1: ( 1, 3, 0)
5369 22:59:05.082919 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5370 22:59:05.086104 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5371 22:59:05.086210
5372 22:59:05.089955 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5373 22:59:05.093062 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5374 22:59:05.096134 [Gating] SW calibration Done
5375 22:59:05.096242 ==
5376 22:59:05.099690 Dram Type= 6, Freq= 0, CH_0, rank 1
5377 22:59:05.102743 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5378 22:59:05.102855 ==
5379 22:59:05.105800 RX Vref Scan: 0
5380 22:59:05.105907
5381 22:59:05.106009 RX Vref 0 -> 0, step: 1
5382 22:59:05.106107
5383 22:59:05.109391 RX Delay -80 -> 252, step: 8
5384 22:59:05.116047 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5385 22:59:05.119092 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5386 22:59:05.122664 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5387 22:59:05.125757 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5388 22:59:05.129330 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5389 22:59:05.132819 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5390 22:59:05.135995 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5391 22:59:05.142812 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5392 22:59:05.145889 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5393 22:59:05.149040 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5394 22:59:05.152282 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5395 22:59:05.155463 iDelay=208, Bit 11, Center 75 (-16 ~ 167) 184
5396 22:59:05.162224 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5397 22:59:05.165868 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5398 22:59:05.168886 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5399 22:59:05.172248 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5400 22:59:05.172364 ==
5401 22:59:05.175887 Dram Type= 6, Freq= 0, CH_0, rank 1
5402 22:59:05.178977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5403 22:59:05.179085 ==
5404 22:59:05.182164 DQS Delay:
5405 22:59:05.182272 DQS0 = 0, DQS1 = 0
5406 22:59:05.185397 DQM Delay:
5407 22:59:05.185502 DQM0 = 97, DQM1 = 87
5408 22:59:05.185602 DQ Delay:
5409 22:59:05.189091 DQ0 =99, DQ1 =95, DQ2 =95, DQ3 =95
5410 22:59:05.192149 DQ4 =95, DQ5 =87, DQ6 =107, DQ7 =107
5411 22:59:05.195847 DQ8 =83, DQ9 =79, DQ10 =87, DQ11 =75
5412 22:59:05.199074 DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =95
5413 22:59:05.199178
5414 22:59:05.199298
5415 22:59:05.202178 ==
5416 22:59:05.205906 Dram Type= 6, Freq= 0, CH_0, rank 1
5417 22:59:05.208885 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5418 22:59:05.208989 ==
5419 22:59:05.209083
5420 22:59:05.209174
5421 22:59:05.212589 TX Vref Scan disable
5422 22:59:05.212689 == TX Byte 0 ==
5423 22:59:05.215497 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5424 22:59:05.222264 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5425 22:59:05.222350 == TX Byte 1 ==
5426 22:59:05.225906 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5427 22:59:05.232077 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5428 22:59:05.232190 ==
5429 22:59:05.235742 Dram Type= 6, Freq= 0, CH_0, rank 1
5430 22:59:05.238721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5431 22:59:05.238803 ==
5432 22:59:05.238870
5433 22:59:05.238932
5434 22:59:05.242415 TX Vref Scan disable
5435 22:59:05.245558 == TX Byte 0 ==
5436 22:59:05.248581 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5437 22:59:05.251969 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5438 22:59:05.255788 == TX Byte 1 ==
5439 22:59:05.258920 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5440 22:59:05.261980 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5441 22:59:05.262068
5442 22:59:05.262136 [DATLAT]
5443 22:59:05.265714 Freq=933, CH0 RK1
5444 22:59:05.265802
5445 22:59:05.268705 DATLAT Default: 0xb
5446 22:59:05.268792 0, 0xFFFF, sum = 0
5447 22:59:05.272431 1, 0xFFFF, sum = 0
5448 22:59:05.272519 2, 0xFFFF, sum = 0
5449 22:59:05.275621 3, 0xFFFF, sum = 0
5450 22:59:05.275708 4, 0xFFFF, sum = 0
5451 22:59:05.278771 5, 0xFFFF, sum = 0
5452 22:59:05.278859 6, 0xFFFF, sum = 0
5453 22:59:05.282026 7, 0xFFFF, sum = 0
5454 22:59:05.282114 8, 0xFFFF, sum = 0
5455 22:59:05.285234 9, 0xFFFF, sum = 0
5456 22:59:05.285322 10, 0x0, sum = 1
5457 22:59:05.288843 11, 0x0, sum = 2
5458 22:59:05.288958 12, 0x0, sum = 3
5459 22:59:05.291892 13, 0x0, sum = 4
5460 22:59:05.292003 best_step = 11
5461 22:59:05.292097
5462 22:59:05.292189 ==
5463 22:59:05.295008 Dram Type= 6, Freq= 0, CH_0, rank 1
5464 22:59:05.298825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5465 22:59:05.301978 ==
5466 22:59:05.302085 RX Vref Scan: 0
5467 22:59:05.302180
5468 22:59:05.305060 RX Vref 0 -> 0, step: 1
5469 22:59:05.305178
5470 22:59:05.308190 RX Delay -61 -> 252, step: 4
5471 22:59:05.311777 iDelay=199, Bit 0, Center 96 (3 ~ 190) 188
5472 22:59:05.315050 iDelay=199, Bit 1, Center 96 (3 ~ 190) 188
5473 22:59:05.318460 iDelay=199, Bit 2, Center 92 (-1 ~ 186) 188
5474 22:59:05.325117 iDelay=199, Bit 3, Center 94 (-1 ~ 190) 192
5475 22:59:05.328402 iDelay=199, Bit 4, Center 96 (7 ~ 186) 180
5476 22:59:05.332106 iDelay=199, Bit 5, Center 84 (-9 ~ 178) 188
5477 22:59:05.335307 iDelay=199, Bit 6, Center 106 (15 ~ 198) 184
5478 22:59:05.338246 iDelay=199, Bit 7, Center 102 (11 ~ 194) 184
5479 22:59:05.341908 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5480 22:59:05.348509 iDelay=199, Bit 9, Center 78 (-13 ~ 170) 184
5481 22:59:05.351722 iDelay=199, Bit 10, Center 88 (-1 ~ 178) 180
5482 22:59:05.354858 iDelay=199, Bit 11, Center 78 (-9 ~ 166) 176
5483 22:59:05.357936 iDelay=199, Bit 12, Center 90 (-1 ~ 182) 184
5484 22:59:05.361643 iDelay=199, Bit 13, Center 94 (7 ~ 182) 176
5485 22:59:05.368088 iDelay=199, Bit 14, Center 100 (15 ~ 186) 172
5486 22:59:05.371575 iDelay=199, Bit 15, Center 94 (7 ~ 182) 176
5487 22:59:05.371660 ==
5488 22:59:05.374666 Dram Type= 6, Freq= 0, CH_0, rank 1
5489 22:59:05.377913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5490 22:59:05.378037 ==
5491 22:59:05.381610 DQS Delay:
5492 22:59:05.381728 DQS0 = 0, DQS1 = 0
5493 22:59:05.381829 DQM Delay:
5494 22:59:05.384810 DQM0 = 95, DQM1 = 87
5495 22:59:05.384918 DQ Delay:
5496 22:59:05.387915 DQ0 =96, DQ1 =96, DQ2 =92, DQ3 =94
5497 22:59:05.391201 DQ4 =96, DQ5 =84, DQ6 =106, DQ7 =102
5498 22:59:05.394867 DQ8 =80, DQ9 =78, DQ10 =88, DQ11 =78
5499 22:59:05.398152 DQ12 =90, DQ13 =94, DQ14 =100, DQ15 =94
5500 22:59:05.398266
5501 22:59:05.398371
5502 22:59:05.408149 [DQSOSCAuto] RK1, (LSB)MR18= 0x1a08, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 413 ps
5503 22:59:05.411282 CH0 RK1: MR19=505, MR18=1A08
5504 22:59:05.414451 CH0_RK1: MR19=0x505, MR18=0x1A08, DQSOSC=413, MR23=63, INC=63, DEC=42
5505 22:59:05.418152 [RxdqsGatingPostProcess] freq 933
5506 22:59:05.424800 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5507 22:59:05.427790 best DQS0 dly(2T, 0.5T) = (0, 10)
5508 22:59:05.431452 best DQS1 dly(2T, 0.5T) = (0, 10)
5509 22:59:05.434340 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5510 22:59:05.437816 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5511 22:59:05.440859 best DQS0 dly(2T, 0.5T) = (0, 10)
5512 22:59:05.444526 best DQS1 dly(2T, 0.5T) = (0, 11)
5513 22:59:05.448082 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5514 22:59:05.451009 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5515 22:59:05.451125 Pre-setting of DQS Precalculation
5516 22:59:05.458064 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5517 22:59:05.458176 ==
5518 22:59:05.461205 Dram Type= 6, Freq= 0, CH_1, rank 0
5519 22:59:05.464272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5520 22:59:05.464384 ==
5521 22:59:05.471201 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5522 22:59:05.478086 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5523 22:59:05.481145 [CA 0] Center 36 (6~67) winsize 62
5524 22:59:05.484358 [CA 1] Center 36 (6~67) winsize 62
5525 22:59:05.487573 [CA 2] Center 33 (3~64) winsize 62
5526 22:59:05.490762 [CA 3] Center 33 (3~64) winsize 62
5527 22:59:05.494513 [CA 4] Center 34 (3~65) winsize 63
5528 22:59:05.497659 [CA 5] Center 33 (3~63) winsize 61
5529 22:59:05.497770
5530 22:59:05.501261 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5531 22:59:05.501370
5532 22:59:05.504382 [CATrainingPosCal] consider 1 rank data
5533 22:59:05.507513 u2DelayCellTimex100 = 270/100 ps
5534 22:59:05.511304 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5535 22:59:05.514381 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5536 22:59:05.517459 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
5537 22:59:05.521096 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5538 22:59:05.524109 CA4 delay=34 (3~65),Diff = 1 PI (6 cell)
5539 22:59:05.527704 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5540 22:59:05.527813
5541 22:59:05.534187 CA PerBit enable=1, Macro0, CA PI delay=33
5542 22:59:05.534298
5543 22:59:05.537134 [CBTSetCACLKResult] CA Dly = 33
5544 22:59:05.537241 CS Dly: 4 (0~35)
5545 22:59:05.537338 ==
5546 22:59:05.540662 Dram Type= 6, Freq= 0, CH_1, rank 1
5547 22:59:05.543733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5548 22:59:05.543844 ==
5549 22:59:05.550484 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5550 22:59:05.557358 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5551 22:59:05.560500 [CA 0] Center 36 (6~67) winsize 62
5552 22:59:05.563626 [CA 1] Center 36 (6~67) winsize 62
5553 22:59:05.566961 [CA 2] Center 34 (4~64) winsize 61
5554 22:59:05.570631 [CA 3] Center 34 (4~64) winsize 61
5555 22:59:05.573762 [CA 4] Center 34 (4~64) winsize 61
5556 22:59:05.577489 [CA 5] Center 32 (2~63) winsize 62
5557 22:59:05.577597
5558 22:59:05.580452 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5559 22:59:05.580559
5560 22:59:05.583538 [CATrainingPosCal] consider 2 rank data
5561 22:59:05.587413 u2DelayCellTimex100 = 270/100 ps
5562 22:59:05.590493 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5563 22:59:05.593694 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5564 22:59:05.597080 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5565 22:59:05.600337 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5566 22:59:05.603512 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5567 22:59:05.610298 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5568 22:59:05.610414
5569 22:59:05.613514 CA PerBit enable=1, Macro0, CA PI delay=33
5570 22:59:05.613627
5571 22:59:05.616552 [CBTSetCACLKResult] CA Dly = 33
5572 22:59:05.616662 CS Dly: 5 (0~38)
5573 22:59:05.616763
5574 22:59:05.620463 ----->DramcWriteLeveling(PI) begin...
5575 22:59:05.620567 ==
5576 22:59:05.623508 Dram Type= 6, Freq= 0, CH_1, rank 0
5577 22:59:05.630235 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5578 22:59:05.630347 ==
5579 22:59:05.633216 Write leveling (Byte 0): 24 => 24
5580 22:59:05.633333 Write leveling (Byte 1): 30 => 30
5581 22:59:05.636983 DramcWriteLeveling(PI) end<-----
5582 22:59:05.637095
5583 22:59:05.640130 ==
5584 22:59:05.640236 Dram Type= 6, Freq= 0, CH_1, rank 0
5585 22:59:05.646776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5586 22:59:05.646887 ==
5587 22:59:05.649734 [Gating] SW mode calibration
5588 22:59:05.656312 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5589 22:59:05.659956 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5590 22:59:05.666887 0 14 0 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
5591 22:59:05.669953 0 14 4 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5592 22:59:05.673048 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5593 22:59:05.679438 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5594 22:59:05.682971 0 14 16 | B1->B0 | 3535 3434 | 1 1 | (0 0) (1 1)
5595 22:59:05.686786 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5596 22:59:05.693155 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5597 22:59:05.696363 0 14 28 | B1->B0 | 2f2f 3131 | 1 0 | (1 0) (0 0)
5598 22:59:05.699446 0 15 0 | B1->B0 | 2424 2424 | 0 0 | (0 0) (0 0)
5599 22:59:05.706281 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5600 22:59:05.709563 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5601 22:59:05.712551 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5602 22:59:05.719432 0 15 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5603 22:59:05.722707 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5604 22:59:05.725944 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5605 22:59:05.732512 0 15 28 | B1->B0 | 3434 3030 | 0 0 | (0 0) (0 0)
5606 22:59:05.735680 1 0 0 | B1->B0 | 4545 3e3e | 1 0 | (0 0) (0 0)
5607 22:59:05.739156 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5608 22:59:05.745609 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5609 22:59:05.749339 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5610 22:59:05.752363 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5611 22:59:05.759002 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5612 22:59:05.762589 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5613 22:59:05.765614 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5614 22:59:05.769397 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5615 22:59:05.775874 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5616 22:59:05.778932 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5617 22:59:05.782708 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5618 22:59:05.788882 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5619 22:59:05.791980 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5620 22:59:05.795823 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5621 22:59:05.802134 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5622 22:59:05.805238 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5623 22:59:05.808582 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5624 22:59:05.815504 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5625 22:59:05.818697 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5626 22:59:05.821750 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5627 22:59:05.828699 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5628 22:59:05.831879 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5629 22:59:05.835279 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5630 22:59:05.841858 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5631 22:59:05.845692 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5632 22:59:05.848704 Total UI for P1: 0, mck2ui 16
5633 22:59:05.851745 best dqsien dly found for B0: ( 1, 3, 0)
5634 22:59:05.855452 Total UI for P1: 0, mck2ui 16
5635 22:59:05.858468 best dqsien dly found for B1: ( 1, 2, 30)
5636 22:59:05.862180 best DQS0 dly(MCK, UI, PI) = (1, 3, 0)
5637 22:59:05.865208 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5638 22:59:05.865295
5639 22:59:05.868714 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 0)
5640 22:59:05.871911 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5641 22:59:05.875044 [Gating] SW calibration Done
5642 22:59:05.875158 ==
5643 22:59:05.878247 Dram Type= 6, Freq= 0, CH_1, rank 0
5644 22:59:05.882227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5645 22:59:05.885312 ==
5646 22:59:05.885398 RX Vref Scan: 0
5647 22:59:05.885466
5648 22:59:05.888482 RX Vref 0 -> 0, step: 1
5649 22:59:05.888599
5650 22:59:05.891678 RX Delay -80 -> 252, step: 8
5651 22:59:05.895251 iDelay=200, Bit 0, Center 99 (8 ~ 191) 184
5652 22:59:05.898473 iDelay=200, Bit 1, Center 91 (-8 ~ 191) 200
5653 22:59:05.901657 iDelay=200, Bit 2, Center 87 (-8 ~ 183) 192
5654 22:59:05.904897 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5655 22:59:05.908593 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5656 22:59:05.914878 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5657 22:59:05.918596 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5658 22:59:05.921783 iDelay=200, Bit 7, Center 91 (-8 ~ 191) 200
5659 22:59:05.924989 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5660 22:59:05.928306 iDelay=200, Bit 9, Center 75 (-24 ~ 175) 200
5661 22:59:05.931960 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5662 22:59:05.938619 iDelay=200, Bit 11, Center 83 (-16 ~ 183) 200
5663 22:59:05.941785 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5664 22:59:05.945409 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5665 22:59:05.948224 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5666 22:59:05.951267 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5667 22:59:05.951388 ==
5668 22:59:05.954764 Dram Type= 6, Freq= 0, CH_1, rank 0
5669 22:59:05.961681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5670 22:59:05.961798 ==
5671 22:59:05.961896 DQS Delay:
5672 22:59:05.964835 DQS0 = 0, DQS1 = 0
5673 22:59:05.964940 DQM Delay:
5674 22:59:05.965033 DQM0 = 96, DQM1 = 88
5675 22:59:05.968182 DQ Delay:
5676 22:59:05.971712 DQ0 =99, DQ1 =91, DQ2 =87, DQ3 =95
5677 22:59:05.974968 DQ4 =95, DQ5 =103, DQ6 =107, DQ7 =91
5678 22:59:05.978052 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =83
5679 22:59:05.981960 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5680 22:59:05.982067
5681 22:59:05.982165
5682 22:59:05.982258 ==
5683 22:59:05.985008 Dram Type= 6, Freq= 0, CH_1, rank 0
5684 22:59:05.988192 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5685 22:59:05.988278 ==
5686 22:59:05.988346
5687 22:59:05.988407
5688 22:59:05.991377 TX Vref Scan disable
5689 22:59:05.994608 == TX Byte 0 ==
5690 22:59:05.998221 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5691 22:59:06.001364 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5692 22:59:06.004445 == TX Byte 1 ==
5693 22:59:06.007659 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5694 22:59:06.011245 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5695 22:59:06.011330 ==
5696 22:59:06.014309 Dram Type= 6, Freq= 0, CH_1, rank 0
5697 22:59:06.018342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5698 22:59:06.021344 ==
5699 22:59:06.021429
5700 22:59:06.021496
5701 22:59:06.021558 TX Vref Scan disable
5702 22:59:06.024606 == TX Byte 0 ==
5703 22:59:06.028382 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5704 22:59:06.034712 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5705 22:59:06.034833 == TX Byte 1 ==
5706 22:59:06.037914 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5707 22:59:06.044559 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5708 22:59:06.044676
5709 22:59:06.044790 [DATLAT]
5710 22:59:06.044886 Freq=933, CH1 RK0
5711 22:59:06.044980
5712 22:59:06.047785 DATLAT Default: 0xd
5713 22:59:06.051270 0, 0xFFFF, sum = 0
5714 22:59:06.051390 1, 0xFFFF, sum = 0
5715 22:59:06.054274 2, 0xFFFF, sum = 0
5716 22:59:06.054389 3, 0xFFFF, sum = 0
5717 22:59:06.057746 4, 0xFFFF, sum = 0
5718 22:59:06.057861 5, 0xFFFF, sum = 0
5719 22:59:06.061447 6, 0xFFFF, sum = 0
5720 22:59:06.061570 7, 0xFFFF, sum = 0
5721 22:59:06.064464 8, 0xFFFF, sum = 0
5722 22:59:06.064574 9, 0xFFFF, sum = 0
5723 22:59:06.067598 10, 0x0, sum = 1
5724 22:59:06.067691 11, 0x0, sum = 2
5725 22:59:06.071119 12, 0x0, sum = 3
5726 22:59:06.071248 13, 0x0, sum = 4
5727 22:59:06.071356 best_step = 11
5728 22:59:06.074233
5729 22:59:06.074354 ==
5730 22:59:06.077906 Dram Type= 6, Freq= 0, CH_1, rank 0
5731 22:59:06.081054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5732 22:59:06.081174 ==
5733 22:59:06.081277 RX Vref Scan: 1
5734 22:59:06.081369
5735 22:59:06.084194 RX Vref 0 -> 0, step: 1
5736 22:59:06.084304
5737 22:59:06.087916 RX Delay -69 -> 252, step: 4
5738 22:59:06.088032
5739 22:59:06.091268 Set Vref, RX VrefLevel [Byte0]: 54
5740 22:59:06.094456 [Byte1]: 51
5741 22:59:06.094541
5742 22:59:06.097632 Final RX Vref Byte 0 = 54 to rank0
5743 22:59:06.100829 Final RX Vref Byte 1 = 51 to rank0
5744 22:59:06.104423 Final RX Vref Byte 0 = 54 to rank1
5745 22:59:06.107558 Final RX Vref Byte 1 = 51 to rank1==
5746 22:59:06.110669 Dram Type= 6, Freq= 0, CH_1, rank 0
5747 22:59:06.117564 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5748 22:59:06.117683 ==
5749 22:59:06.117785 DQS Delay:
5750 22:59:06.117882 DQS0 = 0, DQS1 = 0
5751 22:59:06.120604 DQM Delay:
5752 22:59:06.120719 DQM0 = 98, DQM1 = 90
5753 22:59:06.123847 DQ Delay:
5754 22:59:06.127558 DQ0 =102, DQ1 =92, DQ2 =86, DQ3 =98
5755 22:59:06.130597 DQ4 =96, DQ5 =108, DQ6 =110, DQ7 =94
5756 22:59:06.134454 DQ8 =80, DQ9 =78, DQ10 =92, DQ11 =86
5757 22:59:06.137590 DQ12 =96, DQ13 =98, DQ14 =96, DQ15 =96
5758 22:59:06.137702
5759 22:59:06.137798
5760 22:59:06.144390 [DQSOSCAuto] RK0, (LSB)MR18= 0x12ee, (MSB)MR19= 0x504, tDQSOscB0 = 428 ps tDQSOscB1 = 416 ps
5761 22:59:06.147415 CH1 RK0: MR19=504, MR18=12EE
5762 22:59:06.154202 CH1_RK0: MR19=0x504, MR18=0x12EE, DQSOSC=416, MR23=63, INC=62, DEC=41
5763 22:59:06.154326
5764 22:59:06.157255 ----->DramcWriteLeveling(PI) begin...
5765 22:59:06.157360 ==
5766 22:59:06.160758 Dram Type= 6, Freq= 0, CH_1, rank 1
5767 22:59:06.163820 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5768 22:59:06.163926 ==
5769 22:59:06.167508 Write leveling (Byte 0): 26 => 26
5770 22:59:06.170586 Write leveling (Byte 1): 30 => 30
5771 22:59:06.173637 DramcWriteLeveling(PI) end<-----
5772 22:59:06.173743
5773 22:59:06.173838 ==
5774 22:59:06.177280 Dram Type= 6, Freq= 0, CH_1, rank 1
5775 22:59:06.180432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5776 22:59:06.180540 ==
5777 22:59:06.184001 [Gating] SW mode calibration
5778 22:59:06.190783 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5779 22:59:06.197334 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5780 22:59:06.200466 0 14 0 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5781 22:59:06.206762 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5782 22:59:06.210433 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5783 22:59:06.213682 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5784 22:59:06.220536 0 14 16 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5785 22:59:06.223698 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5786 22:59:06.226857 0 14 24 | B1->B0 | 3333 2f2f | 0 0 | (0 0) (0 1)
5787 22:59:06.230578 0 14 28 | B1->B0 | 2727 2626 | 0 0 | (0 0) (0 0)
5788 22:59:06.236819 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5789 22:59:06.240021 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5790 22:59:06.243884 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5791 22:59:06.250047 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5792 22:59:06.253669 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5793 22:59:06.256560 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5794 22:59:06.263358 0 15 24 | B1->B0 | 2727 3131 | 1 1 | (0 0) (1 1)
5795 22:59:06.266895 0 15 28 | B1->B0 | 3b3b 4444 | 0 0 | (0 0) (0 0)
5796 22:59:06.269985 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5797 22:59:06.276747 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5798 22:59:06.280260 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5799 22:59:06.283230 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5800 22:59:06.290234 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5801 22:59:06.293405 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5802 22:59:06.296485 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5803 22:59:06.303447 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5804 22:59:06.306594 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5805 22:59:06.309819 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5806 22:59:06.316597 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5807 22:59:06.319678 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5808 22:59:06.323399 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5809 22:59:06.329600 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5810 22:59:06.333532 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5811 22:59:06.336695 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5812 22:59:06.343116 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5813 22:59:06.346865 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5814 22:59:06.349897 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5815 22:59:06.356149 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5816 22:59:06.359803 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5817 22:59:06.362836 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5818 22:59:06.369569 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5819 22:59:06.372547 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5820 22:59:06.376050 Total UI for P1: 0, mck2ui 16
5821 22:59:06.379159 best dqsien dly found for B0: ( 1, 2, 24)
5822 22:59:06.382848 Total UI for P1: 0, mck2ui 16
5823 22:59:06.385879 best dqsien dly found for B1: ( 1, 2, 26)
5824 22:59:06.389319 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5825 22:59:06.392388 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5826 22:59:06.392514
5827 22:59:06.396201 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5828 22:59:06.399198 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5829 22:59:06.402379 [Gating] SW calibration Done
5830 22:59:06.402487 ==
5831 22:59:06.406193 Dram Type= 6, Freq= 0, CH_1, rank 1
5832 22:59:06.409328 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5833 22:59:06.412432 ==
5834 22:59:06.412547 RX Vref Scan: 0
5835 22:59:06.412662
5836 22:59:06.415592 RX Vref 0 -> 0, step: 1
5837 22:59:06.415708
5838 22:59:06.415814 RX Delay -80 -> 252, step: 8
5839 22:59:06.422944 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5840 22:59:06.426055 iDelay=200, Bit 1, Center 87 (-8 ~ 183) 192
5841 22:59:06.429148 iDelay=200, Bit 2, Center 87 (-8 ~ 183) 192
5842 22:59:06.432889 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5843 22:59:06.436031 iDelay=200, Bit 4, Center 91 (-8 ~ 191) 200
5844 22:59:06.439075 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5845 22:59:06.445868 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5846 22:59:06.449109 iDelay=200, Bit 7, Center 91 (-8 ~ 191) 200
5847 22:59:06.452369 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5848 22:59:06.455476 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5849 22:59:06.458992 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5850 22:59:06.465579 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5851 22:59:06.469236 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5852 22:59:06.472305 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5853 22:59:06.475494 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5854 22:59:06.479020 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5855 22:59:06.479135 ==
5856 22:59:06.482460 Dram Type= 6, Freq= 0, CH_1, rank 1
5857 22:59:06.488805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5858 22:59:06.488891 ==
5859 22:59:06.488959 DQS Delay:
5860 22:59:06.492391 DQS0 = 0, DQS1 = 0
5861 22:59:06.492470 DQM Delay:
5862 22:59:06.492535 DQM0 = 94, DQM1 = 88
5863 22:59:06.495360 DQ Delay:
5864 22:59:06.498596 DQ0 =95, DQ1 =87, DQ2 =87, DQ3 =95
5865 22:59:06.502465 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5866 22:59:06.505602 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =83
5867 22:59:06.508617 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5868 22:59:06.508724
5869 22:59:06.508821
5870 22:59:06.508913 ==
5871 22:59:06.511921 Dram Type= 6, Freq= 0, CH_1, rank 1
5872 22:59:06.515662 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5873 22:59:06.515769 ==
5874 22:59:06.515864
5875 22:59:06.515954
5876 22:59:06.518624 TX Vref Scan disable
5877 22:59:06.521819 == TX Byte 0 ==
5878 22:59:06.525423 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5879 22:59:06.528402 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5880 22:59:06.532159 == TX Byte 1 ==
5881 22:59:06.535366 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5882 22:59:06.538465 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5883 22:59:06.538563 ==
5884 22:59:06.541557 Dram Type= 6, Freq= 0, CH_1, rank 1
5885 22:59:06.545300 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5886 22:59:06.548510 ==
5887 22:59:06.548599
5888 22:59:06.548697
5889 22:59:06.548763 TX Vref Scan disable
5890 22:59:06.551710 == TX Byte 0 ==
5891 22:59:06.554875 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5892 22:59:06.561660 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5893 22:59:06.561783 == TX Byte 1 ==
5894 22:59:06.565401 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5895 22:59:06.568395 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5896 22:59:06.572053
5897 22:59:06.572137 [DATLAT]
5898 22:59:06.572208 Freq=933, CH1 RK1
5899 22:59:06.572273
5900 22:59:06.575023 DATLAT Default: 0xb
5901 22:59:06.575134 0, 0xFFFF, sum = 0
5902 22:59:06.578596 1, 0xFFFF, sum = 0
5903 22:59:06.578677 2, 0xFFFF, sum = 0
5904 22:59:06.581698 3, 0xFFFF, sum = 0
5905 22:59:06.581788 4, 0xFFFF, sum = 0
5906 22:59:06.585296 5, 0xFFFF, sum = 0
5907 22:59:06.588419 6, 0xFFFF, sum = 0
5908 22:59:06.588539 7, 0xFFFF, sum = 0
5909 22:59:06.591472 8, 0xFFFF, sum = 0
5910 22:59:06.591555 9, 0xFFFF, sum = 0
5911 22:59:06.595107 10, 0x0, sum = 1
5912 22:59:06.595227 11, 0x0, sum = 2
5913 22:59:06.598307 12, 0x0, sum = 3
5914 22:59:06.598443 13, 0x0, sum = 4
5915 22:59:06.598552 best_step = 11
5916 22:59:06.598621
5917 22:59:06.601454 ==
5918 22:59:06.605264 Dram Type= 6, Freq= 0, CH_1, rank 1
5919 22:59:06.608469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5920 22:59:06.608555 ==
5921 22:59:06.608628 RX Vref Scan: 0
5922 22:59:06.608692
5923 22:59:06.611638 RX Vref 0 -> 0, step: 1
5924 22:59:06.611723
5925 22:59:06.614874 RX Delay -61 -> 252, step: 4
5926 22:59:06.617928 iDelay=199, Bit 0, Center 98 (7 ~ 190) 184
5927 22:59:06.624879 iDelay=199, Bit 1, Center 88 (-5 ~ 182) 188
5928 22:59:06.628509 iDelay=199, Bit 2, Center 84 (-9 ~ 178) 188
5929 22:59:06.631655 iDelay=199, Bit 3, Center 92 (-1 ~ 186) 188
5930 22:59:06.634790 iDelay=199, Bit 4, Center 98 (7 ~ 190) 184
5931 22:59:06.638049 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5932 22:59:06.641200 iDelay=199, Bit 6, Center 104 (15 ~ 194) 180
5933 22:59:06.648112 iDelay=199, Bit 7, Center 90 (-1 ~ 182) 184
5934 22:59:06.651199 iDelay=199, Bit 8, Center 80 (-13 ~ 174) 188
5935 22:59:06.655117 iDelay=199, Bit 9, Center 78 (-13 ~ 170) 184
5936 22:59:06.658302 iDelay=199, Bit 10, Center 94 (3 ~ 186) 184
5937 22:59:06.661394 iDelay=199, Bit 11, Center 82 (-9 ~ 174) 184
5938 22:59:06.667973 iDelay=199, Bit 12, Center 96 (7 ~ 186) 180
5939 22:59:06.671578 iDelay=199, Bit 13, Center 98 (7 ~ 190) 184
5940 22:59:06.674692 iDelay=199, Bit 14, Center 98 (7 ~ 190) 184
5941 22:59:06.677657 iDelay=199, Bit 15, Center 100 (11 ~ 190) 180
5942 22:59:06.677776 ==
5943 22:59:06.681299 Dram Type= 6, Freq= 0, CH_1, rank 1
5944 22:59:06.684209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5945 22:59:06.687786 ==
5946 22:59:06.687900 DQS Delay:
5947 22:59:06.688007 DQS0 = 0, DQS1 = 0
5948 22:59:06.690909 DQM Delay:
5949 22:59:06.691013 DQM0 = 95, DQM1 = 90
5950 22:59:06.694463 DQ Delay:
5951 22:59:06.697689 DQ0 =98, DQ1 =88, DQ2 =84, DQ3 =92
5952 22:59:06.701272 DQ4 =98, DQ5 =106, DQ6 =104, DQ7 =90
5953 22:59:06.704137 DQ8 =80, DQ9 =78, DQ10 =94, DQ11 =82
5954 22:59:06.707753 DQ12 =96, DQ13 =98, DQ14 =98, DQ15 =100
5955 22:59:06.707877
5956 22:59:06.707980
5957 22:59:06.714709 [DQSOSCAuto] RK1, (LSB)MR18= 0x101a, (MSB)MR19= 0x505, tDQSOscB0 = 413 ps tDQSOscB1 = 416 ps
5958 22:59:06.717725 CH1 RK1: MR19=505, MR18=101A
5959 22:59:06.724640 CH1_RK1: MR19=0x505, MR18=0x101A, DQSOSC=413, MR23=63, INC=63, DEC=42
5960 22:59:06.727690 [RxdqsGatingPostProcess] freq 933
5961 22:59:06.730808 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5962 22:59:06.734196 best DQS0 dly(2T, 0.5T) = (0, 11)
5963 22:59:06.737486 best DQS1 dly(2T, 0.5T) = (0, 10)
5964 22:59:06.740762 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
5965 22:59:06.744507 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5966 22:59:06.747592 best DQS0 dly(2T, 0.5T) = (0, 10)
5967 22:59:06.750641 best DQS1 dly(2T, 0.5T) = (0, 10)
5968 22:59:06.754579 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5969 22:59:06.757576 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5970 22:59:06.760717 Pre-setting of DQS Precalculation
5971 22:59:06.763841 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5972 22:59:06.770789 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5973 22:59:06.780595 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5974 22:59:06.780733
5975 22:59:06.780862
5976 22:59:06.784175 [Calibration Summary] 1866 Mbps
5977 22:59:06.784280 CH 0, Rank 0
5978 22:59:06.787192 SW Impedance : PASS
5979 22:59:06.787300 DUTY Scan : NO K
5980 22:59:06.790721 ZQ Calibration : PASS
5981 22:59:06.793926 Jitter Meter : NO K
5982 22:59:06.794035 CBT Training : PASS
5983 22:59:06.797375 Write leveling : PASS
5984 22:59:06.797486 RX DQS gating : PASS
5985 22:59:06.800519 RX DQ/DQS(RDDQC) : PASS
5986 22:59:06.804222 TX DQ/DQS : PASS
5987 22:59:06.804331 RX DATLAT : PASS
5988 22:59:06.807153 RX DQ/DQS(Engine): PASS
5989 22:59:06.810877 TX OE : NO K
5990 22:59:06.810992 All Pass.
5991 22:59:06.811100
5992 22:59:06.811203 CH 0, Rank 1
5993 22:59:06.813895 SW Impedance : PASS
5994 22:59:06.817225 DUTY Scan : NO K
5995 22:59:06.817334 ZQ Calibration : PASS
5996 22:59:06.820881 Jitter Meter : NO K
5997 22:59:06.824000 CBT Training : PASS
5998 22:59:06.824109 Write leveling : PASS
5999 22:59:06.827905 RX DQS gating : PASS
6000 22:59:06.831046 RX DQ/DQS(RDDQC) : PASS
6001 22:59:06.831155 TX DQ/DQS : PASS
6002 22:59:06.834047 RX DATLAT : PASS
6003 22:59:06.837150 RX DQ/DQS(Engine): PASS
6004 22:59:06.837276 TX OE : NO K
6005 22:59:06.837379 All Pass.
6006 22:59:06.840692
6007 22:59:06.840799 CH 1, Rank 0
6008 22:59:06.843821 SW Impedance : PASS
6009 22:59:06.843909 DUTY Scan : NO K
6010 22:59:06.847659 ZQ Calibration : PASS
6011 22:59:06.847745 Jitter Meter : NO K
6012 22:59:06.850852 CBT Training : PASS
6013 22:59:06.853986 Write leveling : PASS
6014 22:59:06.854076 RX DQS gating : PASS
6015 22:59:06.857067 RX DQ/DQS(RDDQC) : PASS
6016 22:59:06.860813 TX DQ/DQS : PASS
6017 22:59:06.860925 RX DATLAT : PASS
6018 22:59:06.864158 RX DQ/DQS(Engine): PASS
6019 22:59:06.867129 TX OE : NO K
6020 22:59:06.867262 All Pass.
6021 22:59:06.867389
6022 22:59:06.867460 CH 1, Rank 1
6023 22:59:06.870395 SW Impedance : PASS
6024 22:59:06.874044 DUTY Scan : NO K
6025 22:59:06.874127 ZQ Calibration : PASS
6026 22:59:06.876978 Jitter Meter : NO K
6027 22:59:06.880654 CBT Training : PASS
6028 22:59:06.880751 Write leveling : PASS
6029 22:59:06.883798 RX DQS gating : PASS
6030 22:59:06.886830 RX DQ/DQS(RDDQC) : PASS
6031 22:59:06.886911 TX DQ/DQS : PASS
6032 22:59:06.890545 RX DATLAT : PASS
6033 22:59:06.893511 RX DQ/DQS(Engine): PASS
6034 22:59:06.893622 TX OE : NO K
6035 22:59:06.893721 All Pass.
6036 22:59:06.897080
6037 22:59:06.897189 DramC Write-DBI off
6038 22:59:06.900213 PER_BANK_REFRESH: Hybrid Mode
6039 22:59:06.900309 TX_TRACKING: ON
6040 22:59:06.910379 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6041 22:59:06.913413 [FAST_K] Save calibration result to emmc
6042 22:59:06.917003 dramc_set_vcore_voltage set vcore to 650000
6043 22:59:06.920129 Read voltage for 400, 6
6044 22:59:06.920211 Vio18 = 0
6045 22:59:06.923457 Vcore = 650000
6046 22:59:06.923575 Vdram = 0
6047 22:59:06.923644 Vddq = 0
6048 22:59:06.923729 Vmddr = 0
6049 22:59:06.930220 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6050 22:59:06.936573 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6051 22:59:06.936665 MEM_TYPE=3, freq_sel=20
6052 22:59:06.940316 sv_algorithm_assistance_LP4_800
6053 22:59:06.943476 ============ PULL DRAM RESETB DOWN ============
6054 22:59:06.949717 ========== PULL DRAM RESETB DOWN end =========
6055 22:59:06.953570 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6056 22:59:06.956558 ===================================
6057 22:59:06.959689 LPDDR4 DRAM CONFIGURATION
6058 22:59:06.963538 ===================================
6059 22:59:06.963662 EX_ROW_EN[0] = 0x0
6060 22:59:06.966698 EX_ROW_EN[1] = 0x0
6061 22:59:06.966817 LP4Y_EN = 0x0
6062 22:59:06.969652 WORK_FSP = 0x0
6063 22:59:06.969755 WL = 0x2
6064 22:59:06.972957 RL = 0x2
6065 22:59:06.976719 BL = 0x2
6066 22:59:06.976806 RPST = 0x0
6067 22:59:06.979758 RD_PRE = 0x0
6068 22:59:06.979887 WR_PRE = 0x1
6069 22:59:06.983359 WR_PST = 0x0
6070 22:59:06.983485 DBI_WR = 0x0
6071 22:59:06.986477 DBI_RD = 0x0
6072 22:59:06.986562 OTF = 0x1
6073 22:59:06.989551 ===================================
6074 22:59:06.993248 ===================================
6075 22:59:06.996232 ANA top config
6076 22:59:06.999431 ===================================
6077 22:59:06.999514 DLL_ASYNC_EN = 0
6078 22:59:07.002902 ALL_SLAVE_EN = 1
6079 22:59:07.006765 NEW_RANK_MODE = 1
6080 22:59:07.009697 DLL_IDLE_MODE = 1
6081 22:59:07.009836 LP45_APHY_COMB_EN = 1
6082 22:59:07.012778 TX_ODT_DIS = 1
6083 22:59:07.016284 NEW_8X_MODE = 1
6084 22:59:07.019951 ===================================
6085 22:59:07.022970 ===================================
6086 22:59:07.026163 data_rate = 800
6087 22:59:07.029412 CKR = 1
6088 22:59:07.029526 DQ_P2S_RATIO = 4
6089 22:59:07.033146 ===================================
6090 22:59:07.036320 CA_P2S_RATIO = 4
6091 22:59:07.039444 DQ_CA_OPEN = 0
6092 22:59:07.043043 DQ_SEMI_OPEN = 1
6093 22:59:07.046290 CA_SEMI_OPEN = 1
6094 22:59:07.049890 CA_FULL_RATE = 0
6095 22:59:07.050017 DQ_CKDIV4_EN = 0
6096 22:59:07.053084 CA_CKDIV4_EN = 1
6097 22:59:07.056241 CA_PREDIV_EN = 0
6098 22:59:07.059276 PH8_DLY = 0
6099 22:59:07.063203 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6100 22:59:07.066149 DQ_AAMCK_DIV = 0
6101 22:59:07.066271 CA_AAMCK_DIV = 0
6102 22:59:07.069522 CA_ADMCK_DIV = 4
6103 22:59:07.072630 DQ_TRACK_CA_EN = 0
6104 22:59:07.075767 CA_PICK = 800
6105 22:59:07.079525 CA_MCKIO = 400
6106 22:59:07.082526 MCKIO_SEMI = 400
6107 22:59:07.086154 PLL_FREQ = 3016
6108 22:59:07.089274 DQ_UI_PI_RATIO = 32
6109 22:59:07.089384 CA_UI_PI_RATIO = 32
6110 22:59:07.092506 ===================================
6111 22:59:07.095905 ===================================
6112 22:59:07.099571 memory_type:LPDDR4
6113 22:59:07.102540 GP_NUM : 10
6114 22:59:07.102664 SRAM_EN : 1
6115 22:59:07.106147 MD32_EN : 0
6116 22:59:07.109141 ===================================
6117 22:59:07.112355 [ANA_INIT] >>>>>>>>>>>>>>
6118 22:59:07.116075 <<<<<< [CONFIGURE PHASE]: ANA_TX
6119 22:59:07.119120 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6120 22:59:07.122087 ===================================
6121 22:59:07.122205 data_rate = 800,PCW = 0X7400
6122 22:59:07.125843 ===================================
6123 22:59:07.128802 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6124 22:59:07.135772 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6125 22:59:07.148826 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6126 22:59:07.152080 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6127 22:59:07.155836 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6128 22:59:07.158919 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6129 22:59:07.162180 [ANA_INIT] flow start
6130 22:59:07.162287 [ANA_INIT] PLL >>>>>>>>
6131 22:59:07.165849 [ANA_INIT] PLL <<<<<<<<
6132 22:59:07.169049 [ANA_INIT] MIDPI >>>>>>>>
6133 22:59:07.169160 [ANA_INIT] MIDPI <<<<<<<<
6134 22:59:07.172367 [ANA_INIT] DLL >>>>>>>>
6135 22:59:07.176052 [ANA_INIT] flow end
6136 22:59:07.179166 ============ LP4 DIFF to SE enter ============
6137 22:59:07.182341 ============ LP4 DIFF to SE exit ============
6138 22:59:07.185415 [ANA_INIT] <<<<<<<<<<<<<
6139 22:59:07.188980 [Flow] Enable top DCM control >>>>>
6140 22:59:07.192480 [Flow] Enable top DCM control <<<<<
6141 22:59:07.195744 Enable DLL master slave shuffle
6142 22:59:07.199243 ==============================================================
6143 22:59:07.202261 Gating Mode config
6144 22:59:07.208972 ==============================================================
6145 22:59:07.209072 Config description:
6146 22:59:07.218667 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6147 22:59:07.225303 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6148 22:59:07.228879 SELPH_MODE 0: By rank 1: By Phase
6149 22:59:07.235066 ==============================================================
6150 22:59:07.238878 GAT_TRACK_EN = 0
6151 22:59:07.241891 RX_GATING_MODE = 2
6152 22:59:07.245251 RX_GATING_TRACK_MODE = 2
6153 22:59:07.248797 SELPH_MODE = 1
6154 22:59:07.251976 PICG_EARLY_EN = 1
6155 22:59:07.255099 VALID_LAT_VALUE = 1
6156 22:59:07.258863 ==============================================================
6157 22:59:07.262005 Enter into Gating configuration >>>>
6158 22:59:07.265136 Exit from Gating configuration <<<<
6159 22:59:07.268266 Enter into DVFS_PRE_config >>>>>
6160 22:59:07.281657 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6161 22:59:07.281782 Exit from DVFS_PRE_config <<<<<
6162 22:59:07.284893 Enter into PICG configuration >>>>
6163 22:59:07.288601 Exit from PICG configuration <<<<
6164 22:59:07.291661 [RX_INPUT] configuration >>>>>
6165 22:59:07.295170 [RX_INPUT] configuration <<<<<
6166 22:59:07.301497 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6167 22:59:07.305071 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6168 22:59:07.311841 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6169 22:59:07.318373 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6170 22:59:07.325185 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6171 22:59:07.331162 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6172 22:59:07.334762 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6173 22:59:07.337750 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6174 22:59:07.341625 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6175 22:59:07.347906 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6176 22:59:07.351106 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6177 22:59:07.354375 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6178 22:59:07.358108 ===================================
6179 22:59:07.361191 LPDDR4 DRAM CONFIGURATION
6180 22:59:07.364972 ===================================
6181 22:59:07.368193 EX_ROW_EN[0] = 0x0
6182 22:59:07.368322 EX_ROW_EN[1] = 0x0
6183 22:59:07.371272 LP4Y_EN = 0x0
6184 22:59:07.371404 WORK_FSP = 0x0
6185 22:59:07.374626 WL = 0x2
6186 22:59:07.374734 RL = 0x2
6187 22:59:07.377546 BL = 0x2
6188 22:59:07.377671 RPST = 0x0
6189 22:59:07.381386 RD_PRE = 0x0
6190 22:59:07.381522 WR_PRE = 0x1
6191 22:59:07.384521 WR_PST = 0x0
6192 22:59:07.384649 DBI_WR = 0x0
6193 22:59:07.387674 DBI_RD = 0x0
6194 22:59:07.387801 OTF = 0x1
6195 22:59:07.390926 ===================================
6196 22:59:07.394174 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6197 22:59:07.400704 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6198 22:59:07.404437 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6199 22:59:07.407512 ===================================
6200 22:59:07.411241 LPDDR4 DRAM CONFIGURATION
6201 22:59:07.414189 ===================================
6202 22:59:07.414302 EX_ROW_EN[0] = 0x10
6203 22:59:07.417323 EX_ROW_EN[1] = 0x0
6204 22:59:07.420723 LP4Y_EN = 0x0
6205 22:59:07.420830 WORK_FSP = 0x0
6206 22:59:07.424015 WL = 0x2
6207 22:59:07.424134 RL = 0x2
6208 22:59:07.427674 BL = 0x2
6209 22:59:07.427796 RPST = 0x0
6210 22:59:07.430749 RD_PRE = 0x0
6211 22:59:07.430857 WR_PRE = 0x1
6212 22:59:07.433900 WR_PST = 0x0
6213 22:59:07.434005 DBI_WR = 0x0
6214 22:59:07.437576 DBI_RD = 0x0
6215 22:59:07.437685 OTF = 0x1
6216 22:59:07.440626 ===================================
6217 22:59:07.447376 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6218 22:59:07.451844 nWR fixed to 30
6219 22:59:07.454982 [ModeRegInit_LP4] CH0 RK0
6220 22:59:07.455101 [ModeRegInit_LP4] CH0 RK1
6221 22:59:07.458648 [ModeRegInit_LP4] CH1 RK0
6222 22:59:07.461829 [ModeRegInit_LP4] CH1 RK1
6223 22:59:07.461935 match AC timing 19
6224 22:59:07.468652 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6225 22:59:07.471823 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6226 22:59:07.474874 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6227 22:59:07.481776 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6228 22:59:07.484991 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6229 22:59:07.485104 ==
6230 22:59:07.488195 Dram Type= 6, Freq= 0, CH_0, rank 0
6231 22:59:07.491945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6232 22:59:07.492056 ==
6233 22:59:07.498243 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6234 22:59:07.504868 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6235 22:59:07.507913 [CA 0] Center 36 (8~64) winsize 57
6236 22:59:07.511642 [CA 1] Center 36 (8~64) winsize 57
6237 22:59:07.514812 [CA 2] Center 36 (8~64) winsize 57
6238 22:59:07.518265 [CA 3] Center 36 (8~64) winsize 57
6239 22:59:07.518376 [CA 4] Center 36 (8~64) winsize 57
6240 22:59:07.521325 [CA 5] Center 36 (8~64) winsize 57
6241 22:59:07.521428
6242 22:59:07.528104 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6243 22:59:07.528214
6244 22:59:07.531096 [CATrainingPosCal] consider 1 rank data
6245 22:59:07.534804 u2DelayCellTimex100 = 270/100 ps
6246 22:59:07.537966 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6247 22:59:07.541403 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6248 22:59:07.544875 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6249 22:59:07.547853 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6250 22:59:07.550966 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6251 22:59:07.554295 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6252 22:59:07.554402
6253 22:59:07.558161 CA PerBit enable=1, Macro0, CA PI delay=36
6254 22:59:07.558265
6255 22:59:07.561371 [CBTSetCACLKResult] CA Dly = 36
6256 22:59:07.564575 CS Dly: 1 (0~32)
6257 22:59:07.564680 ==
6258 22:59:07.567801 Dram Type= 6, Freq= 0, CH_0, rank 1
6259 22:59:07.571335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6260 22:59:07.571448 ==
6261 22:59:07.577760 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6262 22:59:07.584687 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6263 22:59:07.584803 [CA 0] Center 36 (8~64) winsize 57
6264 22:59:07.587823 [CA 1] Center 36 (8~64) winsize 57
6265 22:59:07.591015 [CA 2] Center 36 (8~64) winsize 57
6266 22:59:07.594244 [CA 3] Center 36 (8~64) winsize 57
6267 22:59:07.597384 [CA 4] Center 36 (8~64) winsize 57
6268 22:59:07.600564 [CA 5] Center 36 (8~64) winsize 57
6269 22:59:07.600654
6270 22:59:07.604177 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6271 22:59:07.604266
6272 22:59:07.610847 [CATrainingPosCal] consider 2 rank data
6273 22:59:07.610937 u2DelayCellTimex100 = 270/100 ps
6274 22:59:07.616929 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6275 22:59:07.620595 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6276 22:59:07.623708 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6277 22:59:07.627314 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6278 22:59:07.630436 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6279 22:59:07.633621 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6280 22:59:07.633710
6281 22:59:07.636996 CA PerBit enable=1, Macro0, CA PI delay=36
6282 22:59:07.637083
6283 22:59:07.640191 [CBTSetCACLKResult] CA Dly = 36
6284 22:59:07.643778 CS Dly: 1 (0~32)
6285 22:59:07.643863
6286 22:59:07.647278 ----->DramcWriteLeveling(PI) begin...
6287 22:59:07.647394 ==
6288 22:59:07.650396 Dram Type= 6, Freq= 0, CH_0, rank 0
6289 22:59:07.653368 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6290 22:59:07.653484 ==
6291 22:59:07.657153 Write leveling (Byte 0): 40 => 8
6292 22:59:07.660308 Write leveling (Byte 1): 32 => 0
6293 22:59:07.663653 DramcWriteLeveling(PI) end<-----
6294 22:59:07.663744
6295 22:59:07.663815 ==
6296 22:59:07.666648 Dram Type= 6, Freq= 0, CH_0, rank 0
6297 22:59:07.669810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6298 22:59:07.669918 ==
6299 22:59:07.673620 [Gating] SW mode calibration
6300 22:59:07.680511 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6301 22:59:07.686685 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6302 22:59:07.689867 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6303 22:59:07.693630 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6304 22:59:07.699861 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6305 22:59:07.703111 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6306 22:59:07.706935 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6307 22:59:07.713119 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6308 22:59:07.716836 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6309 22:59:07.719853 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6310 22:59:07.726624 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6311 22:59:07.726712 Total UI for P1: 0, mck2ui 16
6312 22:59:07.733273 best dqsien dly found for B0: ( 0, 14, 24)
6313 22:59:07.733358 Total UI for P1: 0, mck2ui 16
6314 22:59:07.739618 best dqsien dly found for B1: ( 0, 14, 24)
6315 22:59:07.743416 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6316 22:59:07.746550 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6317 22:59:07.746665
6318 22:59:07.749394 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6319 22:59:07.752841 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6320 22:59:07.756408 [Gating] SW calibration Done
6321 22:59:07.756522 ==
6322 22:59:07.759609 Dram Type= 6, Freq= 0, CH_0, rank 0
6323 22:59:07.762668 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6324 22:59:07.762774 ==
6325 22:59:07.765763 RX Vref Scan: 0
6326 22:59:07.765841
6327 22:59:07.765907 RX Vref 0 -> 0, step: 1
6328 22:59:07.765972
6329 22:59:07.769497 RX Delay -410 -> 252, step: 16
6330 22:59:07.775773 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6331 22:59:07.779471 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6332 22:59:07.782511 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6333 22:59:07.785782 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6334 22:59:07.792659 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6335 22:59:07.795901 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6336 22:59:07.799339 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6337 22:59:07.802268 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6338 22:59:07.809276 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6339 22:59:07.812487 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6340 22:59:07.816186 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6341 22:59:07.819169 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6342 22:59:07.825913 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6343 22:59:07.828816 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6344 22:59:07.832626 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6345 22:59:07.835575 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6346 22:59:07.839136 ==
6347 22:59:07.842284 Dram Type= 6, Freq= 0, CH_0, rank 0
6348 22:59:07.845423 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6349 22:59:07.845521 ==
6350 22:59:07.845605 DQS Delay:
6351 22:59:07.849060 DQS0 = 35, DQS1 = 51
6352 22:59:07.849204 DQM Delay:
6353 22:59:07.852176 DQM0 = 6, DQM1 = 10
6354 22:59:07.852297 DQ Delay:
6355 22:59:07.855798 DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0
6356 22:59:07.858722 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6357 22:59:07.862386 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6358 22:59:07.865593 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6359 22:59:07.865685
6360 22:59:07.865752
6361 22:59:07.865814 ==
6362 22:59:07.868799 Dram Type= 6, Freq= 0, CH_0, rank 0
6363 22:59:07.872480 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6364 22:59:07.872559 ==
6365 22:59:07.872624
6366 22:59:07.872684
6367 22:59:07.875662 TX Vref Scan disable
6368 22:59:07.875746 == TX Byte 0 ==
6369 22:59:07.882617 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6370 22:59:07.885634 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6371 22:59:07.885767 == TX Byte 1 ==
6372 22:59:07.892493 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6373 22:59:07.895660 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6374 22:59:07.895755 ==
6375 22:59:07.898867 Dram Type= 6, Freq= 0, CH_0, rank 0
6376 22:59:07.901952 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6377 22:59:07.902036 ==
6378 22:59:07.902119
6379 22:59:07.902185
6380 22:59:07.905117 TX Vref Scan disable
6381 22:59:07.905200 == TX Byte 0 ==
6382 22:59:07.912235 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6383 22:59:07.915267 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6384 22:59:07.915381 == TX Byte 1 ==
6385 22:59:07.921944 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6386 22:59:07.925077 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6387 22:59:07.925162
6388 22:59:07.925230 [DATLAT]
6389 22:59:07.928784 Freq=400, CH0 RK0
6390 22:59:07.928865
6391 22:59:07.928931 DATLAT Default: 0xf
6392 22:59:07.932334 0, 0xFFFF, sum = 0
6393 22:59:07.932417 1, 0xFFFF, sum = 0
6394 22:59:07.935335 2, 0xFFFF, sum = 0
6395 22:59:07.935425 3, 0xFFFF, sum = 0
6396 22:59:07.938456 4, 0xFFFF, sum = 0
6397 22:59:07.938546 5, 0xFFFF, sum = 0
6398 22:59:07.941926 6, 0xFFFF, sum = 0
6399 22:59:07.942025 7, 0xFFFF, sum = 0
6400 22:59:07.945629 8, 0xFFFF, sum = 0
6401 22:59:07.945713 9, 0xFFFF, sum = 0
6402 22:59:07.948691 10, 0xFFFF, sum = 0
6403 22:59:07.952419 11, 0xFFFF, sum = 0
6404 22:59:07.952520 12, 0xFFFF, sum = 0
6405 22:59:07.955470 13, 0x0, sum = 1
6406 22:59:07.955574 14, 0x0, sum = 2
6407 22:59:07.958515 15, 0x0, sum = 3
6408 22:59:07.958610 16, 0x0, sum = 4
6409 22:59:07.958679 best_step = 14
6410 22:59:07.958754
6411 22:59:07.961617 ==
6412 22:59:07.965319 Dram Type= 6, Freq= 0, CH_0, rank 0
6413 22:59:07.968850 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6414 22:59:07.968933 ==
6415 22:59:07.969027 RX Vref Scan: 1
6416 22:59:07.969104
6417 22:59:07.971962 RX Vref 0 -> 0, step: 1
6418 22:59:07.972042
6419 22:59:07.975109 RX Delay -343 -> 252, step: 8
6420 22:59:07.975187
6421 22:59:07.978382 Set Vref, RX VrefLevel [Byte0]: 52
6422 22:59:07.981531 [Byte1]: 50
6423 22:59:07.985791
6424 22:59:07.985874 Final RX Vref Byte 0 = 52 to rank0
6425 22:59:07.988863 Final RX Vref Byte 1 = 50 to rank0
6426 22:59:07.991961 Final RX Vref Byte 0 = 52 to rank1
6427 22:59:07.995185 Final RX Vref Byte 1 = 50 to rank1==
6428 22:59:07.998493 Dram Type= 6, Freq= 0, CH_0, rank 0
6429 22:59:08.005384 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6430 22:59:08.005472 ==
6431 22:59:08.005565 DQS Delay:
6432 22:59:08.008530 DQS0 = 44, DQS1 = 60
6433 22:59:08.008621 DQM Delay:
6434 22:59:08.008687 DQM0 = 10, DQM1 = 15
6435 22:59:08.011644 DQ Delay:
6436 22:59:08.014863 DQ0 =12, DQ1 =12, DQ2 =4, DQ3 =8
6437 22:59:08.018523 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =20
6438 22:59:08.018643 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =12
6439 22:59:08.025244 DQ12 =20, DQ13 =20, DQ14 =28, DQ15 =28
6440 22:59:08.025364
6441 22:59:08.025463
6442 22:59:08.031431 [DQSOSCAuto] RK0, (LSB)MR18= 0x8552, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 393 ps
6443 22:59:08.034964 CH0 RK0: MR19=C0C, MR18=8552
6444 22:59:08.041804 CH0_RK0: MR19=0xC0C, MR18=0x8552, DQSOSC=393, MR23=63, INC=382, DEC=254
6445 22:59:08.041919 ==
6446 22:59:08.044785 Dram Type= 6, Freq= 0, CH_0, rank 1
6447 22:59:08.048374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6448 22:59:08.048489 ==
6449 22:59:08.051444 [Gating] SW mode calibration
6450 22:59:08.058138 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6451 22:59:08.064766 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6452 22:59:08.068327 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6453 22:59:08.071238 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6454 22:59:08.078034 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6455 22:59:08.081126 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6456 22:59:08.084912 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6457 22:59:08.091167 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6458 22:59:08.094909 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6459 22:59:08.098054 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6460 22:59:08.104846 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6461 22:59:08.104937 Total UI for P1: 0, mck2ui 16
6462 22:59:08.111061 best dqsien dly found for B0: ( 0, 14, 24)
6463 22:59:08.111176 Total UI for P1: 0, mck2ui 16
6464 22:59:08.118017 best dqsien dly found for B1: ( 0, 14, 24)
6465 22:59:08.121230 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6466 22:59:08.124179 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6467 22:59:08.124294
6468 22:59:08.128100 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6469 22:59:08.130967 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6470 22:59:08.134052 [Gating] SW calibration Done
6471 22:59:08.134160 ==
6472 22:59:08.137645 Dram Type= 6, Freq= 0, CH_0, rank 1
6473 22:59:08.140795 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6474 22:59:08.140882 ==
6475 22:59:08.144487 RX Vref Scan: 0
6476 22:59:08.144590
6477 22:59:08.144664 RX Vref 0 -> 0, step: 1
6478 22:59:08.144727
6479 22:59:08.147609 RX Delay -410 -> 252, step: 16
6480 22:59:08.154095 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6481 22:59:08.157823 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6482 22:59:08.160917 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6483 22:59:08.164522 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6484 22:59:08.170679 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6485 22:59:08.174419 iDelay=230, Bit 5, Center -43 (-282 ~ 197) 480
6486 22:59:08.177492 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6487 22:59:08.180558 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6488 22:59:08.187559 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6489 22:59:08.190616 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6490 22:59:08.194336 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6491 22:59:08.197341 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6492 22:59:08.204281 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6493 22:59:08.207381 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6494 22:59:08.210474 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6495 22:59:08.214087 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6496 22:59:08.217179 ==
6497 22:59:08.220355 Dram Type= 6, Freq= 0, CH_0, rank 1
6498 22:59:08.224114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6499 22:59:08.224225 ==
6500 22:59:08.224339 DQS Delay:
6501 22:59:08.227291 DQS0 = 43, DQS1 = 51
6502 22:59:08.227400 DQM Delay:
6503 22:59:08.230507 DQM0 = 11, DQM1 = 10
6504 22:59:08.230617 DQ Delay:
6505 22:59:08.234033 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6506 22:59:08.237169 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =24
6507 22:59:08.240212 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6508 22:59:08.243829 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6509 22:59:08.243916
6510 22:59:08.243985
6511 22:59:08.244048 ==
6512 22:59:08.247463 Dram Type= 6, Freq= 0, CH_0, rank 1
6513 22:59:08.250560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6514 22:59:08.250647 ==
6515 22:59:08.250716
6516 22:59:08.250779
6517 22:59:08.253467 TX Vref Scan disable
6518 22:59:08.253586 == TX Byte 0 ==
6519 22:59:08.260117 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6520 22:59:08.263861 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6521 22:59:08.263974 == TX Byte 1 ==
6522 22:59:08.270477 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6523 22:59:08.273487 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6524 22:59:08.273577 ==
6525 22:59:08.277103 Dram Type= 6, Freq= 0, CH_0, rank 1
6526 22:59:08.280072 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6527 22:59:08.280162 ==
6528 22:59:08.280250
6529 22:59:08.280333
6530 22:59:08.283872 TX Vref Scan disable
6531 22:59:08.283985 == TX Byte 0 ==
6532 22:59:08.290176 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6533 22:59:08.293312 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6534 22:59:08.293397 == TX Byte 1 ==
6535 22:59:08.300118 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6536 22:59:08.303165 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6537 22:59:08.303255
6538 22:59:08.303369 [DATLAT]
6539 22:59:08.306985 Freq=400, CH0 RK1
6540 22:59:08.307074
6541 22:59:08.307179 DATLAT Default: 0xe
6542 22:59:08.310266 0, 0xFFFF, sum = 0
6543 22:59:08.310355 1, 0xFFFF, sum = 0
6544 22:59:08.313201 2, 0xFFFF, sum = 0
6545 22:59:08.313291 3, 0xFFFF, sum = 0
6546 22:59:08.316585 4, 0xFFFF, sum = 0
6547 22:59:08.316675 5, 0xFFFF, sum = 0
6548 22:59:08.319674 6, 0xFFFF, sum = 0
6549 22:59:08.319763 7, 0xFFFF, sum = 0
6550 22:59:08.323544 8, 0xFFFF, sum = 0
6551 22:59:08.323636 9, 0xFFFF, sum = 0
6552 22:59:08.326635 10, 0xFFFF, sum = 0
6553 22:59:08.329833 11, 0xFFFF, sum = 0
6554 22:59:08.329923 12, 0xFFFF, sum = 0
6555 22:59:08.332968 13, 0x0, sum = 1
6556 22:59:08.333058 14, 0x0, sum = 2
6557 22:59:08.336126 15, 0x0, sum = 3
6558 22:59:08.336215 16, 0x0, sum = 4
6559 22:59:08.336304 best_step = 14
6560 22:59:08.336387
6561 22:59:08.339698 ==
6562 22:59:08.342927 Dram Type= 6, Freq= 0, CH_0, rank 1
6563 22:59:08.346457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6564 22:59:08.346571 ==
6565 22:59:08.346676 RX Vref Scan: 0
6566 22:59:08.346777
6567 22:59:08.349489 RX Vref 0 -> 0, step: 1
6568 22:59:08.349578
6569 22:59:08.353212 RX Delay -343 -> 252, step: 8
6570 22:59:08.359836 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6571 22:59:08.363332 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6572 22:59:08.366549 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6573 22:59:08.370224 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6574 22:59:08.376384 iDelay=217, Bit 4, Center -36 (-271 ~ 200) 472
6575 22:59:08.379955 iDelay=217, Bit 5, Center -48 (-287 ~ 192) 480
6576 22:59:08.383527 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6577 22:59:08.386554 iDelay=217, Bit 7, Center -28 (-263 ~ 208) 472
6578 22:59:08.393530 iDelay=217, Bit 8, Center -56 (-295 ~ 184) 480
6579 22:59:08.396803 iDelay=217, Bit 9, Center -52 (-295 ~ 192) 488
6580 22:59:08.399882 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6581 22:59:08.403616 iDelay=217, Bit 11, Center -52 (-287 ~ 184) 472
6582 22:59:08.409804 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6583 22:59:08.413440 iDelay=217, Bit 13, Center -40 (-279 ~ 200) 480
6584 22:59:08.416554 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6585 22:59:08.422960 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6586 22:59:08.423075 ==
6587 22:59:08.426603 Dram Type= 6, Freq= 0, CH_0, rank 1
6588 22:59:08.429657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6589 22:59:08.429743 ==
6590 22:59:08.429811 DQS Delay:
6591 22:59:08.432926 DQS0 = 48, DQS1 = 56
6592 22:59:08.433011 DQM Delay:
6593 22:59:08.436737 DQM0 = 13, DQM1 = 11
6594 22:59:08.436845 DQ Delay:
6595 22:59:08.439746 DQ0 =16, DQ1 =16, DQ2 =8, DQ3 =12
6596 22:59:08.443520 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6597 22:59:08.446491 DQ8 =0, DQ9 =4, DQ10 =12, DQ11 =4
6598 22:59:08.449508 DQ12 =12, DQ13 =16, DQ14 =20, DQ15 =20
6599 22:59:08.449621
6600 22:59:08.449719
6601 22:59:08.456061 [DQSOSCAuto] RK1, (LSB)MR18= 0x8f61, (MSB)MR19= 0xc0c, tDQSOscB0 = 397 ps tDQSOscB1 = 391 ps
6602 22:59:08.459811 CH0 RK1: MR19=C0C, MR18=8F61
6603 22:59:08.466422 CH0_RK1: MR19=0xC0C, MR18=0x8F61, DQSOSC=391, MR23=63, INC=386, DEC=257
6604 22:59:08.469930 [RxdqsGatingPostProcess] freq 400
6605 22:59:08.476039 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6606 22:59:08.476161 best DQS0 dly(2T, 0.5T) = (0, 10)
6607 22:59:08.479802 best DQS1 dly(2T, 0.5T) = (0, 10)
6608 22:59:08.482832 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6609 22:59:08.486483 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6610 22:59:08.489472 best DQS0 dly(2T, 0.5T) = (0, 10)
6611 22:59:08.492609 best DQS1 dly(2T, 0.5T) = (0, 10)
6612 22:59:08.496415 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6613 22:59:08.499487 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6614 22:59:08.502776 Pre-setting of DQS Precalculation
6615 22:59:08.509661 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6616 22:59:08.509799 ==
6617 22:59:08.512669 Dram Type= 6, Freq= 0, CH_1, rank 0
6618 22:59:08.515846 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6619 22:59:08.515966 ==
6620 22:59:08.522642 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6621 22:59:08.525796 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6622 22:59:08.528996 [CA 0] Center 36 (8~64) winsize 57
6623 22:59:08.532624 [CA 1] Center 36 (8~64) winsize 57
6624 22:59:08.535666 [CA 2] Center 36 (8~64) winsize 57
6625 22:59:08.538804 [CA 3] Center 36 (8~64) winsize 57
6626 22:59:08.542591 [CA 4] Center 36 (8~64) winsize 57
6627 22:59:08.545554 [CA 5] Center 36 (8~64) winsize 57
6628 22:59:08.545663
6629 22:59:08.549180 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6630 22:59:08.549299
6631 22:59:08.552453 [CATrainingPosCal] consider 1 rank data
6632 22:59:08.555936 u2DelayCellTimex100 = 270/100 ps
6633 22:59:08.558969 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6634 22:59:08.562519 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6635 22:59:08.565507 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6636 22:59:08.572089 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6637 22:59:08.575662 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6638 22:59:08.578817 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6639 22:59:08.578897
6640 22:59:08.582409 CA PerBit enable=1, Macro0, CA PI delay=36
6641 22:59:08.582492
6642 22:59:08.585456 [CBTSetCACLKResult] CA Dly = 36
6643 22:59:08.585540 CS Dly: 1 (0~32)
6644 22:59:08.585605 ==
6645 22:59:08.589078 Dram Type= 6, Freq= 0, CH_1, rank 1
6646 22:59:08.595872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6647 22:59:08.596003 ==
6648 22:59:08.599127 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6649 22:59:08.605284 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6650 22:59:08.608620 [CA 0] Center 36 (8~64) winsize 57
6651 22:59:08.612463 [CA 1] Center 36 (8~64) winsize 57
6652 22:59:08.615564 [CA 2] Center 36 (8~64) winsize 57
6653 22:59:08.618755 [CA 3] Center 36 (8~64) winsize 57
6654 22:59:08.622581 [CA 4] Center 36 (8~64) winsize 57
6655 22:59:08.625625 [CA 5] Center 36 (8~64) winsize 57
6656 22:59:08.625706
6657 22:59:08.628818 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6658 22:59:08.628893
6659 22:59:08.632013 [CATrainingPosCal] consider 2 rank data
6660 22:59:08.635273 u2DelayCellTimex100 = 270/100 ps
6661 22:59:08.638999 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6662 22:59:08.642217 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6663 22:59:08.645396 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6664 22:59:08.648955 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6665 22:59:08.651996 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6666 22:59:08.655691 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6667 22:59:08.655782
6668 22:59:08.662172 CA PerBit enable=1, Macro0, CA PI delay=36
6669 22:59:08.662256
6670 22:59:08.665175 [CBTSetCACLKResult] CA Dly = 36
6671 22:59:08.665252 CS Dly: 1 (0~32)
6672 22:59:08.665316
6673 22:59:08.668265 ----->DramcWriteLeveling(PI) begin...
6674 22:59:08.668339 ==
6675 22:59:08.671960 Dram Type= 6, Freq= 0, CH_1, rank 0
6676 22:59:08.674961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6677 22:59:08.678586 ==
6678 22:59:08.678699 Write leveling (Byte 0): 40 => 8
6679 22:59:08.681624 Write leveling (Byte 1): 40 => 8
6680 22:59:08.685163 DramcWriteLeveling(PI) end<-----
6681 22:59:08.685255
6682 22:59:08.685321 ==
6683 22:59:08.688139 Dram Type= 6, Freq= 0, CH_1, rank 0
6684 22:59:08.694885 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6685 22:59:08.694998 ==
6686 22:59:08.695106 [Gating] SW mode calibration
6687 22:59:08.704773 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6688 22:59:08.708000 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6689 22:59:08.711774 0 11 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
6690 22:59:08.717935 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6691 22:59:08.721503 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6692 22:59:08.724640 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6693 22:59:08.731602 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6694 22:59:08.734805 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6695 22:59:08.738026 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6696 22:59:08.744907 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6697 22:59:08.748114 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6698 22:59:08.751738 Total UI for P1: 0, mck2ui 16
6699 22:59:08.754762 best dqsien dly found for B0: ( 0, 14, 24)
6700 22:59:08.757852 Total UI for P1: 0, mck2ui 16
6701 22:59:08.761438 best dqsien dly found for B1: ( 0, 14, 24)
6702 22:59:08.764415 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6703 22:59:08.768122 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6704 22:59:08.768207
6705 22:59:08.771162 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6706 22:59:08.774813 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6707 22:59:08.777902 [Gating] SW calibration Done
6708 22:59:08.777990 ==
6709 22:59:08.781032 Dram Type= 6, Freq= 0, CH_1, rank 0
6710 22:59:08.787783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6711 22:59:08.787902 ==
6712 22:59:08.788001 RX Vref Scan: 0
6713 22:59:08.788093
6714 22:59:08.791366 RX Vref 0 -> 0, step: 1
6715 22:59:08.791482
6716 22:59:08.794454 RX Delay -410 -> 252, step: 16
6717 22:59:08.797986 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6718 22:59:08.801154 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6719 22:59:08.804774 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6720 22:59:08.811113 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6721 22:59:08.814433 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6722 22:59:08.817643 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6723 22:59:08.820811 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6724 22:59:08.827642 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6725 22:59:08.830760 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6726 22:59:08.834589 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6727 22:59:08.840828 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6728 22:59:08.843910 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6729 22:59:08.847742 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6730 22:59:08.850875 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6731 22:59:08.857176 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6732 22:59:08.860713 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6733 22:59:08.860796 ==
6734 22:59:08.864308 Dram Type= 6, Freq= 0, CH_1, rank 0
6735 22:59:08.867535 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6736 22:59:08.867620 ==
6737 22:59:08.870650 DQS Delay:
6738 22:59:08.870735 DQS0 = 51, DQS1 = 59
6739 22:59:08.874126 DQM Delay:
6740 22:59:08.874232 DQM0 = 19, DQM1 = 18
6741 22:59:08.874332 DQ Delay:
6742 22:59:08.877178 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6743 22:59:08.880829 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6744 22:59:08.884009 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =16
6745 22:59:08.887117 DQ12 =32, DQ13 =24, DQ14 =24, DQ15 =24
6746 22:59:08.887223
6747 22:59:08.887319
6748 22:59:08.887421 ==
6749 22:59:08.890676 Dram Type= 6, Freq= 0, CH_1, rank 0
6750 22:59:08.897503 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6751 22:59:08.897594 ==
6752 22:59:08.897664
6753 22:59:08.897738
6754 22:59:08.897801 TX Vref Scan disable
6755 22:59:08.900591 == TX Byte 0 ==
6756 22:59:08.904152 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6757 22:59:08.907117 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6758 22:59:08.910665 == TX Byte 1 ==
6759 22:59:08.913888 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6760 22:59:08.917124 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6761 22:59:08.917206 ==
6762 22:59:08.920358 Dram Type= 6, Freq= 0, CH_1, rank 0
6763 22:59:08.927040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6764 22:59:08.927157 ==
6765 22:59:08.927258
6766 22:59:08.927370
6767 22:59:08.927436 TX Vref Scan disable
6768 22:59:08.930772 == TX Byte 0 ==
6769 22:59:08.933947 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6770 22:59:08.936996 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6771 22:59:08.940244 == TX Byte 1 ==
6772 22:59:08.943444 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6773 22:59:08.947267 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6774 22:59:08.947377
6775 22:59:08.950234 [DATLAT]
6776 22:59:08.950310 Freq=400, CH1 RK0
6777 22:59:08.950378
6778 22:59:08.953383 DATLAT Default: 0xf
6779 22:59:08.953465 0, 0xFFFF, sum = 0
6780 22:59:08.957279 1, 0xFFFF, sum = 0
6781 22:59:08.957359 2, 0xFFFF, sum = 0
6782 22:59:08.960394 3, 0xFFFF, sum = 0
6783 22:59:08.960480 4, 0xFFFF, sum = 0
6784 22:59:08.963336 5, 0xFFFF, sum = 0
6785 22:59:08.963433 6, 0xFFFF, sum = 0
6786 22:59:08.966753 7, 0xFFFF, sum = 0
6787 22:59:08.969908 8, 0xFFFF, sum = 0
6788 22:59:08.970021 9, 0xFFFF, sum = 0
6789 22:59:08.973648 10, 0xFFFF, sum = 0
6790 22:59:08.973731 11, 0xFFFF, sum = 0
6791 22:59:08.976572 12, 0xFFFF, sum = 0
6792 22:59:08.976652 13, 0x0, sum = 1
6793 22:59:08.980128 14, 0x0, sum = 2
6794 22:59:08.980252 15, 0x0, sum = 3
6795 22:59:08.983204 16, 0x0, sum = 4
6796 22:59:08.983333 best_step = 14
6797 22:59:08.983445
6798 22:59:08.983547 ==
6799 22:59:08.986687 Dram Type= 6, Freq= 0, CH_1, rank 0
6800 22:59:08.989919 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6801 22:59:08.990003 ==
6802 22:59:08.993533 RX Vref Scan: 1
6803 22:59:08.993616
6804 22:59:08.996598 RX Vref 0 -> 0, step: 1
6805 22:59:08.996718
6806 22:59:08.996848 RX Delay -359 -> 252, step: 8
6807 22:59:08.996976
6808 22:59:09.000296 Set Vref, RX VrefLevel [Byte0]: 54
6809 22:59:09.003149 [Byte1]: 51
6810 22:59:09.009009
6811 22:59:09.009092 Final RX Vref Byte 0 = 54 to rank0
6812 22:59:09.011946 Final RX Vref Byte 1 = 51 to rank0
6813 22:59:09.015763 Final RX Vref Byte 0 = 54 to rank1
6814 22:59:09.019010 Final RX Vref Byte 1 = 51 to rank1==
6815 22:59:09.022089 Dram Type= 6, Freq= 0, CH_1, rank 0
6816 22:59:09.029158 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6817 22:59:09.029273 ==
6818 22:59:09.029379 DQS Delay:
6819 22:59:09.032129 DQS0 = 48, DQS1 = 60
6820 22:59:09.032238 DQM Delay:
6821 22:59:09.032348 DQM0 = 12, DQM1 = 13
6822 22:59:09.035259 DQ Delay:
6823 22:59:09.038580 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6824 22:59:09.038690 DQ4 =12, DQ5 =20, DQ6 =24, DQ7 =8
6825 22:59:09.042437 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =8
6826 22:59:09.045613 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6827 22:59:09.045700
6828 22:59:09.048739
6829 22:59:09.055631 [DQSOSCAuto] RK0, (LSB)MR18= 0x852d, (MSB)MR19= 0xc0c, tDQSOscB0 = 404 ps tDQSOscB1 = 393 ps
6830 22:59:09.058770 CH1 RK0: MR19=C0C, MR18=852D
6831 22:59:09.065161 CH1_RK0: MR19=0xC0C, MR18=0x852D, DQSOSC=393, MR23=63, INC=382, DEC=254
6832 22:59:09.065294 ==
6833 22:59:09.068642 Dram Type= 6, Freq= 0, CH_1, rank 1
6834 22:59:09.072261 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6835 22:59:09.072374 ==
6836 22:59:09.075369 [Gating] SW mode calibration
6837 22:59:09.082109 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6838 22:59:09.085297 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6839 22:59:09.091911 0 11 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
6840 22:59:09.095562 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6841 22:59:09.098557 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6842 22:59:09.105381 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6843 22:59:09.108431 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6844 22:59:09.112024 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6845 22:59:09.118707 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6846 22:59:09.121845 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6847 22:59:09.125063 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6848 22:59:09.128339 Total UI for P1: 0, mck2ui 16
6849 22:59:09.131439 best dqsien dly found for B0: ( 0, 14, 24)
6850 22:59:09.134927 Total UI for P1: 0, mck2ui 16
6851 22:59:09.138569 best dqsien dly found for B1: ( 0, 14, 24)
6852 22:59:09.141734 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6853 22:59:09.144882 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6854 22:59:09.148708
6855 22:59:09.151752 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6856 22:59:09.155017 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6857 22:59:09.158678 [Gating] SW calibration Done
6858 22:59:09.158796 ==
6859 22:59:09.161994 Dram Type= 6, Freq= 0, CH_1, rank 1
6860 22:59:09.165168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6861 22:59:09.165283 ==
6862 22:59:09.165381 RX Vref Scan: 0
6863 22:59:09.165476
6864 22:59:09.168412 RX Vref 0 -> 0, step: 1
6865 22:59:09.168523
6866 22:59:09.171903 RX Delay -410 -> 252, step: 16
6867 22:59:09.174938 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6868 22:59:09.181638 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6869 22:59:09.185240 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6870 22:59:09.188203 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6871 22:59:09.191378 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6872 22:59:09.198526 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6873 22:59:09.201710 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6874 22:59:09.205261 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6875 22:59:09.208212 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6876 22:59:09.215019 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6877 22:59:09.217986 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6878 22:59:09.221587 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6879 22:59:09.225188 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6880 22:59:09.231662 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6881 22:59:09.234805 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6882 22:59:09.238592 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6883 22:59:09.238682 ==
6884 22:59:09.241719 Dram Type= 6, Freq= 0, CH_1, rank 1
6885 22:59:09.244995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6886 22:59:09.248107 ==
6887 22:59:09.248194 DQS Delay:
6888 22:59:09.248263 DQS0 = 51, DQS1 = 51
6889 22:59:09.251801 DQM Delay:
6890 22:59:09.251888 DQM0 = 17, DQM1 = 10
6891 22:59:09.254850 DQ Delay:
6892 22:59:09.258062 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6893 22:59:09.258177 DQ4 =16, DQ5 =24, DQ6 =32, DQ7 =16
6894 22:59:09.261883 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6895 22:59:09.264975 DQ12 =16, DQ13 =24, DQ14 =16, DQ15 =16
6896 22:59:09.265116
6897 22:59:09.265242
6898 22:59:09.268160 ==
6899 22:59:09.268272 Dram Type= 6, Freq= 0, CH_1, rank 1
6900 22:59:09.274853 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6901 22:59:09.274961 ==
6902 22:59:09.275056
6903 22:59:09.275170
6904 22:59:09.278385 TX Vref Scan disable
6905 22:59:09.278492 == TX Byte 0 ==
6906 22:59:09.281514 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6907 22:59:09.288259 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6908 22:59:09.288373 == TX Byte 1 ==
6909 22:59:09.291915 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6910 22:59:09.294962 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6911 22:59:09.298004 ==
6912 22:59:09.301560 Dram Type= 6, Freq= 0, CH_1, rank 1
6913 22:59:09.304868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6914 22:59:09.304980 ==
6915 22:59:09.305087
6916 22:59:09.305191
6917 22:59:09.307901 TX Vref Scan disable
6918 22:59:09.308007 == TX Byte 0 ==
6919 22:59:09.311511 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6920 22:59:09.318171 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6921 22:59:09.318283 == TX Byte 1 ==
6922 22:59:09.321074 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6923 22:59:09.327720 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6924 22:59:09.327836
6925 22:59:09.327944 [DATLAT]
6926 22:59:09.328048 Freq=400, CH1 RK1
6927 22:59:09.328152
6928 22:59:09.331554 DATLAT Default: 0xe
6929 22:59:09.331658 0, 0xFFFF, sum = 0
6930 22:59:09.334733 1, 0xFFFF, sum = 0
6931 22:59:09.337897 2, 0xFFFF, sum = 0
6932 22:59:09.338006 3, 0xFFFF, sum = 0
6933 22:59:09.341040 4, 0xFFFF, sum = 0
6934 22:59:09.341147 5, 0xFFFF, sum = 0
6935 22:59:09.344591 6, 0xFFFF, sum = 0
6936 22:59:09.344698 7, 0xFFFF, sum = 0
6937 22:59:09.347812 8, 0xFFFF, sum = 0
6938 22:59:09.347923 9, 0xFFFF, sum = 0
6939 22:59:09.350948 10, 0xFFFF, sum = 0
6940 22:59:09.351058 11, 0xFFFF, sum = 0
6941 22:59:09.354253 12, 0xFFFF, sum = 0
6942 22:59:09.354363 13, 0x0, sum = 1
6943 22:59:09.358008 14, 0x0, sum = 2
6944 22:59:09.358125 15, 0x0, sum = 3
6945 22:59:09.361281 16, 0x0, sum = 4
6946 22:59:09.361390 best_step = 14
6947 22:59:09.361496
6948 22:59:09.361598 ==
6949 22:59:09.364555 Dram Type= 6, Freq= 0, CH_1, rank 1
6950 22:59:09.367663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6951 22:59:09.370780 ==
6952 22:59:09.370902 RX Vref Scan: 0
6953 22:59:09.371003
6954 22:59:09.374578 RX Vref 0 -> 0, step: 1
6955 22:59:09.374666
6956 22:59:09.377318 RX Delay -343 -> 252, step: 8
6957 22:59:09.384466 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6958 22:59:09.387432 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
6959 22:59:09.391036 iDelay=217, Bit 2, Center -52 (-295 ~ 192) 488
6960 22:59:09.394236 iDelay=217, Bit 3, Center -44 (-287 ~ 200) 488
6961 22:59:09.400853 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
6962 22:59:09.403782 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6963 22:59:09.407456 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6964 22:59:09.410664 iDelay=217, Bit 7, Center -44 (-287 ~ 200) 488
6965 22:59:09.417135 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6966 22:59:09.420968 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6967 22:59:09.423823 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6968 22:59:09.426953 iDelay=217, Bit 11, Center -56 (-303 ~ 192) 496
6969 22:59:09.433777 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6970 22:59:09.436975 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6971 22:59:09.440900 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6972 22:59:09.443887 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6973 22:59:09.444016 ==
6974 22:59:09.446972 Dram Type= 6, Freq= 0, CH_1, rank 1
6975 22:59:09.453760 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6976 22:59:09.453851 ==
6977 22:59:09.453920 DQS Delay:
6978 22:59:09.456939 DQS0 = 52, DQS1 = 60
6979 22:59:09.457026 DQM Delay:
6980 22:59:09.460140 DQM0 = 12, DQM1 = 12
6981 22:59:09.460228 DQ Delay:
6982 22:59:09.463804 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6983 22:59:09.466984 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
6984 22:59:09.470315 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =4
6985 22:59:09.473366 DQ12 =16, DQ13 =20, DQ14 =20, DQ15 =20
6986 22:59:09.473483
6987 22:59:09.473588
6988 22:59:09.480246 [DQSOSCAuto] RK1, (LSB)MR18= 0x748b, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 395 ps
6989 22:59:09.483452 CH1 RK1: MR19=C0C, MR18=748B
6990 22:59:09.490076 CH1_RK1: MR19=0xC0C, MR18=0x748B, DQSOSC=392, MR23=63, INC=384, DEC=256
6991 22:59:09.493504 [RxdqsGatingPostProcess] freq 400
6992 22:59:09.496682 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6993 22:59:09.499783 best DQS0 dly(2T, 0.5T) = (0, 10)
6994 22:59:09.503457 best DQS1 dly(2T, 0.5T) = (0, 10)
6995 22:59:09.506593 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6996 22:59:09.509548 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6997 22:59:09.513243 best DQS0 dly(2T, 0.5T) = (0, 10)
6998 22:59:09.516163 best DQS1 dly(2T, 0.5T) = (0, 10)
6999 22:59:09.519900 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7000 22:59:09.522858 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7001 22:59:09.526100 Pre-setting of DQS Precalculation
7002 22:59:09.529653 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7003 22:59:09.539480 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7004 22:59:09.546400 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7005 22:59:09.546523
7006 22:59:09.546623
7007 22:59:09.549572 [Calibration Summary] 800 Mbps
7008 22:59:09.549647 CH 0, Rank 0
7009 22:59:09.552560 SW Impedance : PASS
7010 22:59:09.552666 DUTY Scan : NO K
7011 22:59:09.556376 ZQ Calibration : PASS
7012 22:59:09.559583 Jitter Meter : NO K
7013 22:59:09.559694 CBT Training : PASS
7014 22:59:09.562744 Write leveling : PASS
7015 22:59:09.565902 RX DQS gating : PASS
7016 22:59:09.565989 RX DQ/DQS(RDDQC) : PASS
7017 22:59:09.569220 TX DQ/DQS : PASS
7018 22:59:09.572472 RX DATLAT : PASS
7019 22:59:09.572559 RX DQ/DQS(Engine): PASS
7020 22:59:09.576209 TX OE : NO K
7021 22:59:09.576296 All Pass.
7022 22:59:09.576365
7023 22:59:09.579282 CH 0, Rank 1
7024 22:59:09.579380 SW Impedance : PASS
7025 22:59:09.583043 DUTY Scan : NO K
7026 22:59:09.586252 ZQ Calibration : PASS
7027 22:59:09.586381 Jitter Meter : NO K
7028 22:59:09.589314 CBT Training : PASS
7029 22:59:09.592432 Write leveling : NO K
7030 22:59:09.592516 RX DQS gating : PASS
7031 22:59:09.595997 RX DQ/DQS(RDDQC) : PASS
7032 22:59:09.599646 TX DQ/DQS : PASS
7033 22:59:09.599736 RX DATLAT : PASS
7034 22:59:09.602866 RX DQ/DQS(Engine): PASS
7035 22:59:09.602978 TX OE : NO K
7036 22:59:09.605817 All Pass.
7037 22:59:09.605902
7038 22:59:09.605970 CH 1, Rank 0
7039 22:59:09.609466 SW Impedance : PASS
7040 22:59:09.609552 DUTY Scan : NO K
7041 22:59:09.612445 ZQ Calibration : PASS
7042 22:59:09.616064 Jitter Meter : NO K
7043 22:59:09.616177 CBT Training : PASS
7044 22:59:09.618980 Write leveling : PASS
7045 22:59:09.622039 RX DQS gating : PASS
7046 22:59:09.622152 RX DQ/DQS(RDDQC) : PASS
7047 22:59:09.625717 TX DQ/DQS : PASS
7048 22:59:09.628829 RX DATLAT : PASS
7049 22:59:09.628915 RX DQ/DQS(Engine): PASS
7050 22:59:09.632317 TX OE : NO K
7051 22:59:09.632432 All Pass.
7052 22:59:09.632539
7053 22:59:09.636084 CH 1, Rank 1
7054 22:59:09.636196 SW Impedance : PASS
7055 22:59:09.639052 DUTY Scan : NO K
7056 22:59:09.642309 ZQ Calibration : PASS
7057 22:59:09.642423 Jitter Meter : NO K
7058 22:59:09.645281 CBT Training : PASS
7059 22:59:09.649179 Write leveling : NO K
7060 22:59:09.649291 RX DQS gating : PASS
7061 22:59:09.652270 RX DQ/DQS(RDDQC) : PASS
7062 22:59:09.655499 TX DQ/DQS : PASS
7063 22:59:09.655588 RX DATLAT : PASS
7064 22:59:09.658696 RX DQ/DQS(Engine): PASS
7065 22:59:09.658784 TX OE : NO K
7066 22:59:09.662295 All Pass.
7067 22:59:09.662399
7068 22:59:09.662477 DramC Write-DBI off
7069 22:59:09.665464 PER_BANK_REFRESH: Hybrid Mode
7070 22:59:09.668743 TX_TRACKING: ON
7071 22:59:09.675639 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7072 22:59:09.678736 [FAST_K] Save calibration result to emmc
7073 22:59:09.685250 dramc_set_vcore_voltage set vcore to 725000
7074 22:59:09.685360 Read voltage for 1600, 0
7075 22:59:09.688415 Vio18 = 0
7076 22:59:09.688493 Vcore = 725000
7077 22:59:09.688561 Vdram = 0
7078 22:59:09.688656 Vddq = 0
7079 22:59:09.692182 Vmddr = 0
7080 22:59:09.695325 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7081 22:59:09.701796 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7082 22:59:09.705001 MEM_TYPE=3, freq_sel=13
7083 22:59:09.705108 sv_algorithm_assistance_LP4_3733
7084 22:59:09.711637 ============ PULL DRAM RESETB DOWN ============
7085 22:59:09.715089 ========== PULL DRAM RESETB DOWN end =========
7086 22:59:09.718794 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7087 22:59:09.721762 ===================================
7088 22:59:09.725482 LPDDR4 DRAM CONFIGURATION
7089 22:59:09.728585 ===================================
7090 22:59:09.731697 EX_ROW_EN[0] = 0x0
7091 22:59:09.731808 EX_ROW_EN[1] = 0x0
7092 22:59:09.734812 LP4Y_EN = 0x0
7093 22:59:09.734917 WORK_FSP = 0x1
7094 22:59:09.738537 WL = 0x5
7095 22:59:09.738624 RL = 0x5
7096 22:59:09.741621 BL = 0x2
7097 22:59:09.741707 RPST = 0x0
7098 22:59:09.745134 RD_PRE = 0x0
7099 22:59:09.745307 WR_PRE = 0x1
7100 22:59:09.748225 WR_PST = 0x1
7101 22:59:09.748357 DBI_WR = 0x0
7102 22:59:09.752145 DBI_RD = 0x0
7103 22:59:09.752283 OTF = 0x1
7104 22:59:09.755231 ===================================
7105 22:59:09.758401 ===================================
7106 22:59:09.761381 ANA top config
7107 22:59:09.765155 ===================================
7108 22:59:09.768336 DLL_ASYNC_EN = 0
7109 22:59:09.768469 ALL_SLAVE_EN = 0
7110 22:59:09.771623 NEW_RANK_MODE = 1
7111 22:59:09.774778 DLL_IDLE_MODE = 1
7112 22:59:09.778500 LP45_APHY_COMB_EN = 1
7113 22:59:09.781632 TX_ODT_DIS = 0
7114 22:59:09.781777 NEW_8X_MODE = 1
7115 22:59:09.784810 ===================================
7116 22:59:09.787998 ===================================
7117 22:59:09.791668 data_rate = 3200
7118 22:59:09.794785 CKR = 1
7119 22:59:09.798122 DQ_P2S_RATIO = 8
7120 22:59:09.801711 ===================================
7121 22:59:09.804689 CA_P2S_RATIO = 8
7122 22:59:09.804773 DQ_CA_OPEN = 0
7123 22:59:09.808441 DQ_SEMI_OPEN = 0
7124 22:59:09.811901 CA_SEMI_OPEN = 0
7125 22:59:09.814940 CA_FULL_RATE = 0
7126 22:59:09.817885 DQ_CKDIV4_EN = 0
7127 22:59:09.821509 CA_CKDIV4_EN = 0
7128 22:59:09.821626 CA_PREDIV_EN = 0
7129 22:59:09.825136 PH8_DLY = 12
7130 22:59:09.828102 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7131 22:59:09.831094 DQ_AAMCK_DIV = 4
7132 22:59:09.834858 CA_AAMCK_DIV = 4
7133 22:59:09.837716 CA_ADMCK_DIV = 4
7134 22:59:09.837830 DQ_TRACK_CA_EN = 0
7135 22:59:09.841453 CA_PICK = 1600
7136 22:59:09.844504 CA_MCKIO = 1600
7137 22:59:09.848260 MCKIO_SEMI = 0
7138 22:59:09.851369 PLL_FREQ = 3068
7139 22:59:09.854633 DQ_UI_PI_RATIO = 32
7140 22:59:09.857749 CA_UI_PI_RATIO = 0
7141 22:59:09.860876 ===================================
7142 22:59:09.864605 ===================================
7143 22:59:09.864716 memory_type:LPDDR4
7144 22:59:09.867776 GP_NUM : 10
7145 22:59:09.870875 SRAM_EN : 1
7146 22:59:09.870994 MD32_EN : 0
7147 22:59:09.874767 ===================================
7148 22:59:09.877865 [ANA_INIT] >>>>>>>>>>>>>>
7149 22:59:09.881006 <<<<<< [CONFIGURE PHASE]: ANA_TX
7150 22:59:09.884572 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7151 22:59:09.887917 ===================================
7152 22:59:09.891086 data_rate = 3200,PCW = 0X7600
7153 22:59:09.894183 ===================================
7154 22:59:09.897333 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7155 22:59:09.901127 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7156 22:59:09.907442 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7157 22:59:09.911297 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7158 22:59:09.917774 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7159 22:59:09.920685 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7160 22:59:09.920774 [ANA_INIT] flow start
7161 22:59:09.924340 [ANA_INIT] PLL >>>>>>>>
7162 22:59:09.927234 [ANA_INIT] PLL <<<<<<<<
7163 22:59:09.927354 [ANA_INIT] MIDPI >>>>>>>>
7164 22:59:09.930771 [ANA_INIT] MIDPI <<<<<<<<
7165 22:59:09.934148 [ANA_INIT] DLL >>>>>>>>
7166 22:59:09.934235 [ANA_INIT] DLL <<<<<<<<
7167 22:59:09.937215 [ANA_INIT] flow end
7168 22:59:09.940654 ============ LP4 DIFF to SE enter ============
7169 22:59:09.944513 ============ LP4 DIFF to SE exit ============
7170 22:59:09.947574 [ANA_INIT] <<<<<<<<<<<<<
7171 22:59:09.950634 [Flow] Enable top DCM control >>>>>
7172 22:59:09.954338 [Flow] Enable top DCM control <<<<<
7173 22:59:09.957511 Enable DLL master slave shuffle
7174 22:59:09.964266 ==============================================================
7175 22:59:09.964412 Gating Mode config
7176 22:59:09.970778 ==============================================================
7177 22:59:09.970868 Config description:
7178 22:59:09.980393 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7179 22:59:09.987766 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7180 22:59:09.993856 SELPH_MODE 0: By rank 1: By Phase
7181 22:59:09.997032 ==============================================================
7182 22:59:10.000796 GAT_TRACK_EN = 1
7183 22:59:10.003899 RX_GATING_MODE = 2
7184 22:59:10.007177 RX_GATING_TRACK_MODE = 2
7185 22:59:10.010863 SELPH_MODE = 1
7186 22:59:10.014114 PICG_EARLY_EN = 1
7187 22:59:10.017288 VALID_LAT_VALUE = 1
7188 22:59:10.023803 ==============================================================
7189 22:59:10.027331 Enter into Gating configuration >>>>
7190 22:59:10.030602 Exit from Gating configuration <<<<
7191 22:59:10.030721 Enter into DVFS_PRE_config >>>>>
7192 22:59:10.043722 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7193 22:59:10.047280 Exit from DVFS_PRE_config <<<<<
7194 22:59:10.050253 Enter into PICG configuration >>>>
7195 22:59:10.053977 Exit from PICG configuration <<<<
7196 22:59:10.054100 [RX_INPUT] configuration >>>>>
7197 22:59:10.056907 [RX_INPUT] configuration <<<<<
7198 22:59:10.063422 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7199 22:59:10.067162 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7200 22:59:10.073355 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7201 22:59:10.080400 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7202 22:59:10.086703 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7203 22:59:10.093689 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7204 22:59:10.096880 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7205 22:59:10.099851 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7206 22:59:10.106811 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7207 22:59:10.110148 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7208 22:59:10.113266 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7209 22:59:10.116502 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7210 22:59:10.120326 ===================================
7211 22:59:10.123254 LPDDR4 DRAM CONFIGURATION
7212 22:59:10.126488 ===================================
7213 22:59:10.130023 EX_ROW_EN[0] = 0x0
7214 22:59:10.130154 EX_ROW_EN[1] = 0x0
7215 22:59:10.133669 LP4Y_EN = 0x0
7216 22:59:10.133801 WORK_FSP = 0x1
7217 22:59:10.136506 WL = 0x5
7218 22:59:10.136628 RL = 0x5
7219 22:59:10.140246 BL = 0x2
7220 22:59:10.140380 RPST = 0x0
7221 22:59:10.143186 RD_PRE = 0x0
7222 22:59:10.143329 WR_PRE = 0x1
7223 22:59:10.146656 WR_PST = 0x1
7224 22:59:10.146769 DBI_WR = 0x0
7225 22:59:10.150123 DBI_RD = 0x0
7226 22:59:10.150241 OTF = 0x1
7227 22:59:10.153153 ===================================
7228 22:59:10.160116 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7229 22:59:10.163160 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7230 22:59:10.166792 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7231 22:59:10.169974 ===================================
7232 22:59:10.173110 LPDDR4 DRAM CONFIGURATION
7233 22:59:10.176389 ===================================
7234 22:59:10.179887 EX_ROW_EN[0] = 0x10
7235 22:59:10.180020 EX_ROW_EN[1] = 0x0
7236 22:59:10.183015 LP4Y_EN = 0x0
7237 22:59:10.183135 WORK_FSP = 0x1
7238 22:59:10.186888 WL = 0x5
7239 22:59:10.187011 RL = 0x5
7240 22:59:10.190115 BL = 0x2
7241 22:59:10.190247 RPST = 0x0
7242 22:59:10.193280 RD_PRE = 0x0
7243 22:59:10.193398 WR_PRE = 0x1
7244 22:59:10.196575 WR_PST = 0x1
7245 22:59:10.196697 DBI_WR = 0x0
7246 22:59:10.199743 DBI_RD = 0x0
7247 22:59:10.199868 OTF = 0x1
7248 22:59:10.202813 ===================================
7249 22:59:10.209813 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7250 22:59:10.209955 ==
7251 22:59:10.212961 Dram Type= 6, Freq= 0, CH_0, rank 0
7252 22:59:10.219834 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7253 22:59:10.219970 ==
7254 22:59:10.220075 [Duty_Offset_Calibration]
7255 22:59:10.223058 B0:2 B1:-1 CA:1
7256 22:59:10.223171
7257 22:59:10.226295 [DutyScan_Calibration_Flow] k_type=0
7258 22:59:10.234958
7259 22:59:10.235107 ==CLK 0==
7260 22:59:10.237925 Final CLK duty delay cell = -4
7261 22:59:10.241394 [-4] MAX Duty = 5031%(X100), DQS PI = 22
7262 22:59:10.244479 [-4] MIN Duty = 4844%(X100), DQS PI = 32
7263 22:59:10.248117 [-4] AVG Duty = 4937%(X100)
7264 22:59:10.248253
7265 22:59:10.251652 CH0 CLK Duty spec in!! Max-Min= 187%
7266 22:59:10.254676 [DutyScan_Calibration_Flow] ====Done====
7267 22:59:10.254802
7268 22:59:10.257999 [DutyScan_Calibration_Flow] k_type=1
7269 22:59:10.274195
7270 22:59:10.274396 ==DQS 0 ==
7271 22:59:10.277488 Final DQS duty delay cell = 0
7272 22:59:10.280704 [0] MAX Duty = 5125%(X100), DQS PI = 56
7273 22:59:10.284412 [0] MIN Duty = 5000%(X100), DQS PI = 14
7274 22:59:10.287381 [0] AVG Duty = 5062%(X100)
7275 22:59:10.287519
7276 22:59:10.287645 ==DQS 1 ==
7277 22:59:10.290510 Final DQS duty delay cell = -4
7278 22:59:10.294259 [-4] MAX Duty = 5093%(X100), DQS PI = 0
7279 22:59:10.297470 [-4] MIN Duty = 5000%(X100), DQS PI = 40
7280 22:59:10.300658 [-4] AVG Duty = 5046%(X100)
7281 22:59:10.300790
7282 22:59:10.303937 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7283 22:59:10.304062
7284 22:59:10.307110 CH0 DQS 1 Duty spec in!! Max-Min= 93%
7285 22:59:10.310842 [DutyScan_Calibration_Flow] ====Done====
7286 22:59:10.310957
7287 22:59:10.314032 [DutyScan_Calibration_Flow] k_type=3
7288 22:59:10.331849
7289 22:59:10.332009 ==DQM 0 ==
7290 22:59:10.334846 Final DQM duty delay cell = 0
7291 22:59:10.338060 [0] MAX Duty = 5000%(X100), DQS PI = 20
7292 22:59:10.341875 [0] MIN Duty = 4875%(X100), DQS PI = 4
7293 22:59:10.342006 [0] AVG Duty = 4937%(X100)
7294 22:59:10.345215
7295 22:59:10.345325 ==DQM 1 ==
7296 22:59:10.348085 Final DQM duty delay cell = 0
7297 22:59:10.351691 [0] MAX Duty = 5218%(X100), DQS PI = 58
7298 22:59:10.355323 [0] MIN Duty = 4969%(X100), DQS PI = 18
7299 22:59:10.355474 [0] AVG Duty = 5093%(X100)
7300 22:59:10.358391
7301 22:59:10.361281 CH0 DQM 0 Duty spec in!! Max-Min= 125%
7302 22:59:10.361406
7303 22:59:10.364949 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7304 22:59:10.367953 [DutyScan_Calibration_Flow] ====Done====
7305 22:59:10.368080
7306 22:59:10.371531 [DutyScan_Calibration_Flow] k_type=2
7307 22:59:10.388883
7308 22:59:10.389034 ==DQ 0 ==
7309 22:59:10.391992 Final DQ duty delay cell = 0
7310 22:59:10.395905 [0] MAX Duty = 5156%(X100), DQS PI = 0
7311 22:59:10.399016 [0] MIN Duty = 5031%(X100), DQS PI = 10
7312 22:59:10.399137 [0] AVG Duty = 5093%(X100)
7313 22:59:10.399232
7314 22:59:10.402096 ==DQ 1 ==
7315 22:59:10.405266 Final DQ duty delay cell = 0
7316 22:59:10.408465 [0] MAX Duty = 5000%(X100), DQS PI = 0
7317 22:59:10.411718 [0] MIN Duty = 4907%(X100), DQS PI = 26
7318 22:59:10.411805 [0] AVG Duty = 4953%(X100)
7319 22:59:10.411870
7320 22:59:10.415440 CH0 DQ 0 Duty spec in!! Max-Min= 125%
7321 22:59:10.418373
7322 22:59:10.422276 CH0 DQ 1 Duty spec in!! Max-Min= 93%
7323 22:59:10.425334 [DutyScan_Calibration_Flow] ====Done====
7324 22:59:10.425448 ==
7325 22:59:10.428490 Dram Type= 6, Freq= 0, CH_1, rank 0
7326 22:59:10.431621 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7327 22:59:10.431724 ==
7328 22:59:10.435453 [Duty_Offset_Calibration]
7329 22:59:10.435545 B0:1 B1:1 CA:2
7330 22:59:10.435612
7331 22:59:10.438583 [DutyScan_Calibration_Flow] k_type=0
7332 22:59:10.448618
7333 22:59:10.448787 ==CLK 0==
7334 22:59:10.452321 Final CLK duty delay cell = 0
7335 22:59:10.454933 [0] MAX Duty = 5187%(X100), DQS PI = 24
7336 22:59:10.458502 [0] MIN Duty = 4938%(X100), DQS PI = 48
7337 22:59:10.462024 [0] AVG Duty = 5062%(X100)
7338 22:59:10.462154
7339 22:59:10.464926 CH1 CLK Duty spec in!! Max-Min= 249%
7340 22:59:10.468525 [DutyScan_Calibration_Flow] ====Done====
7341 22:59:10.468645
7342 22:59:10.471919 [DutyScan_Calibration_Flow] k_type=1
7343 22:59:10.488447
7344 22:59:10.488613 ==DQS 0 ==
7345 22:59:10.491359 Final DQS duty delay cell = 0
7346 22:59:10.495201 [0] MAX Duty = 5062%(X100), DQS PI = 20
7347 22:59:10.498383 [0] MIN Duty = 4844%(X100), DQS PI = 48
7348 22:59:10.501515 [0] AVG Duty = 4953%(X100)
7349 22:59:10.501607
7350 22:59:10.501672 ==DQS 1 ==
7351 22:59:10.505331 Final DQS duty delay cell = 0
7352 22:59:10.508568 [0] MAX Duty = 5062%(X100), DQS PI = 58
7353 22:59:10.511602 [0] MIN Duty = 4938%(X100), DQS PI = 12
7354 22:59:10.514696 [0] AVG Duty = 5000%(X100)
7355 22:59:10.514786
7356 22:59:10.518558 CH1 DQS 0 Duty spec in!! Max-Min= 218%
7357 22:59:10.518692
7358 22:59:10.521776 CH1 DQS 1 Duty spec in!! Max-Min= 124%
7359 22:59:10.524945 [DutyScan_Calibration_Flow] ====Done====
7360 22:59:10.525070
7361 22:59:10.528057 [DutyScan_Calibration_Flow] k_type=3
7362 22:59:10.545178
7363 22:59:10.545329 ==DQM 0 ==
7364 22:59:10.548394 Final DQM duty delay cell = 0
7365 22:59:10.551516 [0] MAX Duty = 5187%(X100), DQS PI = 20
7366 22:59:10.555322 [0] MIN Duty = 4844%(X100), DQS PI = 50
7367 22:59:10.558261 [0] AVG Duty = 5015%(X100)
7368 22:59:10.558360
7369 22:59:10.558427 ==DQM 1 ==
7370 22:59:10.561752 Final DQM duty delay cell = 0
7371 22:59:10.565041 [0] MAX Duty = 5156%(X100), DQS PI = 60
7372 22:59:10.568058 [0] MIN Duty = 4875%(X100), DQS PI = 20
7373 22:59:10.571768 [0] AVG Duty = 5015%(X100)
7374 22:59:10.571924
7375 22:59:10.574790 CH1 DQM 0 Duty spec in!! Max-Min= 343%
7376 22:59:10.574900
7377 22:59:10.578371 CH1 DQM 1 Duty spec in!! Max-Min= 281%
7378 22:59:10.581408 [DutyScan_Calibration_Flow] ====Done====
7379 22:59:10.581525
7380 22:59:10.584746 [DutyScan_Calibration_Flow] k_type=2
7381 22:59:10.602168
7382 22:59:10.602344 ==DQ 0 ==
7383 22:59:10.605528 Final DQ duty delay cell = 0
7384 22:59:10.608515 [0] MAX Duty = 5156%(X100), DQS PI = 20
7385 22:59:10.611576 [0] MIN Duty = 4938%(X100), DQS PI = 52
7386 22:59:10.615345 [0] AVG Duty = 5047%(X100)
7387 22:59:10.615486
7388 22:59:10.615586 ==DQ 1 ==
7389 22:59:10.618633 Final DQ duty delay cell = 0
7390 22:59:10.621764 [0] MAX Duty = 5093%(X100), DQS PI = 6
7391 22:59:10.625385 [0] MIN Duty = 5031%(X100), DQS PI = 0
7392 22:59:10.625476 [0] AVG Duty = 5062%(X100)
7393 22:59:10.628522
7394 22:59:10.631732 CH1 DQ 0 Duty spec in!! Max-Min= 218%
7395 22:59:10.631845
7396 22:59:10.634834 CH1 DQ 1 Duty spec in!! Max-Min= 62%
7397 22:59:10.637962 [DutyScan_Calibration_Flow] ====Done====
7398 22:59:10.641727 nWR fixed to 30
7399 22:59:10.641847 [ModeRegInit_LP4] CH0 RK0
7400 22:59:10.644867 [ModeRegInit_LP4] CH0 RK1
7401 22:59:10.648162 [ModeRegInit_LP4] CH1 RK0
7402 22:59:10.651334 [ModeRegInit_LP4] CH1 RK1
7403 22:59:10.651429 match AC timing 5
7404 22:59:10.657759 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7405 22:59:10.661591 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7406 22:59:10.664539 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7407 22:59:10.671138 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7408 22:59:10.674932 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7409 22:59:10.675031 [MiockJmeterHQA]
7410 22:59:10.675107
7411 22:59:10.677846 [DramcMiockJmeter] u1RxGatingPI = 0
7412 22:59:10.681309 0 : 4255, 4029
7413 22:59:10.681396 4 : 4363, 4137
7414 22:59:10.684979 8 : 4258, 4030
7415 22:59:10.685067 12 : 4252, 4027
7416 22:59:10.685135 16 : 4252, 4027
7417 22:59:10.687956 20 : 4258, 4031
7418 22:59:10.688041 24 : 4257, 4029
7419 22:59:10.691384 28 : 4255, 4029
7420 22:59:10.691477 32 : 4363, 4137
7421 22:59:10.694355 36 : 4254, 4029
7422 22:59:10.694436 40 : 4252, 4027
7423 22:59:10.697893 44 : 4257, 4029
7424 22:59:10.697984 48 : 4255, 4029
7425 22:59:10.698059 52 : 4255, 4029
7426 22:59:10.701192 56 : 4252, 4026
7427 22:59:10.701272 60 : 4250, 4026
7428 22:59:10.704578 64 : 4368, 4142
7429 22:59:10.704669 68 : 4253, 4026
7430 22:59:10.708048 72 : 4255, 4029
7431 22:59:10.708137 76 : 4366, 4140
7432 22:59:10.708221 80 : 4250, 4027
7433 22:59:10.711138 84 : 4254, 4030
7434 22:59:10.711248 88 : 4250, 4027
7435 22:59:10.714827 92 : 4250, 4026
7436 22:59:10.714911 96 : 4250, 3345
7437 22:59:10.718036 100 : 4250, 0
7438 22:59:10.718130 104 : 4361, 0
7439 22:59:10.718219 108 : 4255, 0
7440 22:59:10.721207 112 : 4252, 0
7441 22:59:10.721288 116 : 4363, 0
7442 22:59:10.724440 120 : 4253, 0
7443 22:59:10.724554 124 : 4250, 0
7444 22:59:10.724648 128 : 4255, 0
7445 22:59:10.727503 132 : 4368, 0
7446 22:59:10.727587 136 : 4253, 0
7447 22:59:10.731307 140 : 4253, 0
7448 22:59:10.731401 144 : 4255, 0
7449 22:59:10.731480 148 : 4254, 0
7450 22:59:10.734390 152 : 4250, 0
7451 22:59:10.734471 156 : 4253, 0
7452 22:59:10.737545 160 : 4368, 0
7453 22:59:10.737668 164 : 4250, 0
7454 22:59:10.737767 168 : 4360, 0
7455 22:59:10.740796 172 : 4250, 0
7456 22:59:10.740882 176 : 4249, 0
7457 22:59:10.740949 180 : 4255, 0
7458 22:59:10.744618 184 : 4368, 0
7459 22:59:10.744701 188 : 4250, 0
7460 22:59:10.747883 192 : 4250, 0
7461 22:59:10.747969 196 : 4255, 0
7462 22:59:10.748034 200 : 4257, 0
7463 22:59:10.751046 204 : 4255, 0
7464 22:59:10.751132 208 : 4255, 0
7465 22:59:10.754110 212 : 4252, 218
7466 22:59:10.754195 216 : 4363, 3997
7467 22:59:10.757857 220 : 4252, 4027
7468 22:59:10.757947 224 : 4252, 4029
7469 22:59:10.761093 228 : 4250, 4027
7470 22:59:10.761188 232 : 4249, 4027
7471 22:59:10.761257 236 : 4250, 4027
7472 22:59:10.764367 240 : 4250, 4027
7473 22:59:10.764464 244 : 4365, 4142
7474 22:59:10.767295 248 : 4250, 4027
7475 22:59:10.767414 252 : 4361, 4137
7476 22:59:10.770566 256 : 4252, 4027
7477 22:59:10.770661 260 : 4249, 4027
7478 22:59:10.774168 264 : 4363, 4137
7479 22:59:10.774260 268 : 4365, 4140
7480 22:59:10.777862 272 : 4250, 4027
7481 22:59:10.777955 276 : 4250, 4027
7482 22:59:10.780998 280 : 4361, 4138
7483 22:59:10.781093 284 : 4366, 4140
7484 22:59:10.781169 288 : 4250, 4027
7485 22:59:10.783967 292 : 4252, 4027
7486 22:59:10.784061 296 : 4255, 4032
7487 22:59:10.787480 300 : 4250, 4027
7488 22:59:10.787575 304 : 4252, 4030
7489 22:59:10.791168 308 : 4361, 4138
7490 22:59:10.791290 312 : 4253, 4029
7491 22:59:10.794242 316 : 4250, 4026
7492 22:59:10.794362 320 : 4360, 4137
7493 22:59:10.797170 324 : 4255, 4029
7494 22:59:10.797259 328 : 4253, 4029
7495 22:59:10.800892 332 : 4252, 2851
7496 22:59:10.800985 336 : 4366, 118
7497 22:59:10.801055
7498 22:59:10.804429 MIOCK jitter meter ch=0
7499 22:59:10.804521
7500 22:59:10.807435 1T = (336-100) = 236 dly cells
7501 22:59:10.810920 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7502 22:59:10.811016 ==
7503 22:59:10.813894 Dram Type= 6, Freq= 0, CH_0, rank 0
7504 22:59:10.820815 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7505 22:59:10.820931 ==
7506 22:59:10.823882 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7507 22:59:10.830743 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7508 22:59:10.834110 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7509 22:59:10.840708 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7510 22:59:10.848380 [CA 0] Center 44 (14~75) winsize 62
7511 22:59:10.852172 [CA 1] Center 44 (14~75) winsize 62
7512 22:59:10.855297 [CA 2] Center 40 (11~69) winsize 59
7513 22:59:10.858984 [CA 3] Center 39 (10~69) winsize 60
7514 22:59:10.862229 [CA 4] Center 38 (8~68) winsize 61
7515 22:59:10.865213 [CA 5] Center 37 (7~67) winsize 61
7516 22:59:10.865339
7517 22:59:10.868350 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7518 22:59:10.868480
7519 22:59:10.871685 [CATrainingPosCal] consider 1 rank data
7520 22:59:10.874881 u2DelayCellTimex100 = 275/100 ps
7521 22:59:10.881583 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7522 22:59:10.885011 CA1 delay=44 (14~75),Diff = 7 PI (24 cell)
7523 22:59:10.888589 CA2 delay=40 (11~69),Diff = 3 PI (10 cell)
7524 22:59:10.891580 CA3 delay=39 (10~69),Diff = 2 PI (7 cell)
7525 22:59:10.895367 CA4 delay=38 (8~68),Diff = 1 PI (3 cell)
7526 22:59:10.898309 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7527 22:59:10.898435
7528 22:59:10.902139 CA PerBit enable=1, Macro0, CA PI delay=37
7529 22:59:10.902257
7530 22:59:10.905135 [CBTSetCACLKResult] CA Dly = 37
7531 22:59:10.908559 CS Dly: 10 (0~41)
7532 22:59:10.911563 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7533 22:59:10.915234 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7534 22:59:10.915365 ==
7535 22:59:10.918278 Dram Type= 6, Freq= 0, CH_0, rank 1
7536 22:59:10.925043 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7537 22:59:10.925202 ==
7538 22:59:10.928339 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7539 22:59:10.932053 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7540 22:59:10.938424 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7541 22:59:10.945167 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7542 22:59:10.952268 [CA 0] Center 43 (13~74) winsize 62
7543 22:59:10.956050 [CA 1] Center 43 (13~74) winsize 62
7544 22:59:10.959176 [CA 2] Center 39 (10~69) winsize 60
7545 22:59:10.962416 [CA 3] Center 38 (9~68) winsize 60
7546 22:59:10.965687 [CA 4] Center 37 (7~67) winsize 61
7547 22:59:10.969458 [CA 5] Center 37 (7~67) winsize 61
7548 22:59:10.969582
7549 22:59:10.972441 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7550 22:59:10.972550
7551 22:59:10.975502 [CATrainingPosCal] consider 2 rank data
7552 22:59:10.979307 u2DelayCellTimex100 = 275/100 ps
7553 22:59:10.982417 CA0 delay=44 (14~74),Diff = 7 PI (24 cell)
7554 22:59:10.989023 CA1 delay=44 (14~74),Diff = 7 PI (24 cell)
7555 22:59:10.992159 CA2 delay=40 (11~69),Diff = 3 PI (10 cell)
7556 22:59:10.995593 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7557 22:59:10.998856 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7558 22:59:11.002454 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7559 22:59:11.002591
7560 22:59:11.005303 CA PerBit enable=1, Macro0, CA PI delay=37
7561 22:59:11.005432
7562 22:59:11.008950 [CBTSetCACLKResult] CA Dly = 37
7563 22:59:11.012635 CS Dly: 11 (0~44)
7564 22:59:11.015614 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7565 22:59:11.018717 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7566 22:59:11.018850
7567 22:59:11.021928 ----->DramcWriteLeveling(PI) begin...
7568 22:59:11.022045 ==
7569 22:59:11.025603 Dram Type= 6, Freq= 0, CH_0, rank 0
7570 22:59:11.032352 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7571 22:59:11.032500 ==
7572 22:59:11.035535 Write leveling (Byte 0): 31 => 31
7573 22:59:11.038509 Write leveling (Byte 1): 27 => 27
7574 22:59:11.038638 DramcWriteLeveling(PI) end<-----
7575 22:59:11.038747
7576 22:59:11.042247 ==
7577 22:59:11.045461 Dram Type= 6, Freq= 0, CH_0, rank 0
7578 22:59:11.048721 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7579 22:59:11.048847 ==
7580 22:59:11.051811 [Gating] SW mode calibration
7581 22:59:11.058912 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7582 22:59:11.061965 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7583 22:59:11.068381 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7584 22:59:11.072235 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7585 22:59:11.075385 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7586 22:59:11.082250 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7587 22:59:11.085433 1 4 16 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
7588 22:59:11.088432 1 4 20 | B1->B0 | 2625 3333 | 1 1 | (0 0) (1 1)
7589 22:59:11.095234 1 4 24 | B1->B0 | 2c2c 3434 | 1 1 | (0 0) (1 1)
7590 22:59:11.098951 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7591 22:59:11.101861 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7592 22:59:11.108561 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7593 22:59:11.111632 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7594 22:59:11.115230 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7595 22:59:11.121422 1 5 16 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 1)
7596 22:59:11.125134 1 5 20 | B1->B0 | 3434 2424 | 1 0 | (1 0) (0 0)
7597 22:59:11.128075 1 5 24 | B1->B0 | 2d2d 2323 | 0 0 | (1 0) (0 0)
7598 22:59:11.134746 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7599 22:59:11.138525 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7600 22:59:11.141714 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7601 22:59:11.145323 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7602 22:59:11.151541 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7603 22:59:11.154740 1 6 16 | B1->B0 | 2323 3131 | 0 1 | (0 0) (0 0)
7604 22:59:11.158504 1 6 20 | B1->B0 | 2424 4242 | 1 0 | (0 0) (0 0)
7605 22:59:11.164805 1 6 24 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
7606 22:59:11.168102 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7607 22:59:11.171854 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7608 22:59:11.177955 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7609 22:59:11.181244 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7610 22:59:11.185100 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7611 22:59:11.191334 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7612 22:59:11.194760 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7613 22:59:11.198074 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7614 22:59:11.204678 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7615 22:59:11.208296 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7616 22:59:11.211141 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7617 22:59:11.218523 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7618 22:59:11.221474 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7619 22:59:11.225062 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7620 22:59:11.231407 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7621 22:59:11.234552 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7622 22:59:11.238152 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7623 22:59:11.244463 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7624 22:59:11.247645 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7625 22:59:11.251447 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7626 22:59:11.257738 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7627 22:59:11.261601 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7628 22:59:11.264639 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7629 22:59:11.270920 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7630 22:59:11.271051 Total UI for P1: 0, mck2ui 16
7631 22:59:11.277897 best dqsien dly found for B0: ( 1, 9, 18)
7632 22:59:11.280969 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7633 22:59:11.284236 Total UI for P1: 0, mck2ui 16
7634 22:59:11.287315 best dqsien dly found for B1: ( 1, 9, 22)
7635 22:59:11.291110 best DQS0 dly(MCK, UI, PI) = (1, 9, 18)
7636 22:59:11.294147 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7637 22:59:11.294247
7638 22:59:11.297318 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 18)
7639 22:59:11.300827 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7640 22:59:11.304017 [Gating] SW calibration Done
7641 22:59:11.304113 ==
7642 22:59:11.307488 Dram Type= 6, Freq= 0, CH_0, rank 0
7643 22:59:11.310516 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7644 22:59:11.314103 ==
7645 22:59:11.314201 RX Vref Scan: 0
7646 22:59:11.314275
7647 22:59:11.317565 RX Vref 0 -> 0, step: 1
7648 22:59:11.317660
7649 22:59:11.317731 RX Delay 0 -> 252, step: 8
7650 22:59:11.324249 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
7651 22:59:11.327068 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7652 22:59:11.330639 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7653 22:59:11.333855 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7654 22:59:11.337502 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7655 22:59:11.344175 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7656 22:59:11.347203 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7657 22:59:11.350559 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
7658 22:59:11.353622 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7659 22:59:11.357490 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7660 22:59:11.363690 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7661 22:59:11.367659 iDelay=200, Bit 11, Center 119 (72 ~ 167) 96
7662 22:59:11.370681 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7663 22:59:11.373938 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7664 22:59:11.380166 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7665 22:59:11.383946 iDelay=200, Bit 15, Center 131 (80 ~ 183) 104
7666 22:59:11.384118 ==
7667 22:59:11.387154 Dram Type= 6, Freq= 0, CH_0, rank 0
7668 22:59:11.390366 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7669 22:59:11.390475 ==
7670 22:59:11.390547 DQS Delay:
7671 22:59:11.393538 DQS0 = 0, DQS1 = 0
7672 22:59:11.393622 DQM Delay:
7673 22:59:11.397125 DQM0 = 132, DQM1 = 124
7674 22:59:11.397212 DQ Delay:
7675 22:59:11.400243 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7676 22:59:11.403321 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
7677 22:59:11.407034 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =119
7678 22:59:11.413757 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =131
7679 22:59:11.413880
7680 22:59:11.413952
7681 22:59:11.414028 ==
7682 22:59:11.416698 Dram Type= 6, Freq= 0, CH_0, rank 0
7683 22:59:11.420176 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7684 22:59:11.420275 ==
7685 22:59:11.420344
7686 22:59:11.420405
7687 22:59:11.423296 TX Vref Scan disable
7688 22:59:11.423417 == TX Byte 0 ==
7689 22:59:11.430349 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7690 22:59:11.433645 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7691 22:59:11.433740 == TX Byte 1 ==
7692 22:59:11.440253 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7693 22:59:11.443253 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7694 22:59:11.443397 ==
7695 22:59:11.446550 Dram Type= 6, Freq= 0, CH_0, rank 0
7696 22:59:11.450046 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7697 22:59:11.450141 ==
7698 22:59:11.465283
7699 22:59:11.468979 TX Vref early break, caculate TX vref
7700 22:59:11.472188 TX Vref=16, minBit 4, minWin=21, winSum=355
7701 22:59:11.475298 TX Vref=18, minBit 0, minWin=22, winSum=368
7702 22:59:11.479150 TX Vref=20, minBit 1, minWin=22, winSum=379
7703 22:59:11.482189 TX Vref=22, minBit 4, minWin=23, winSum=391
7704 22:59:11.485416 TX Vref=24, minBit 1, minWin=24, winSum=402
7705 22:59:11.492319 TX Vref=26, minBit 4, minWin=24, winSum=409
7706 22:59:11.495611 TX Vref=28, minBit 0, minWin=25, winSum=417
7707 22:59:11.498667 TX Vref=30, minBit 4, minWin=24, winSum=413
7708 22:59:11.502357 TX Vref=32, minBit 10, minWin=24, winSum=408
7709 22:59:11.505444 TX Vref=34, minBit 3, minWin=23, winSum=396
7710 22:59:11.509114 TX Vref=36, minBit 3, minWin=23, winSum=386
7711 22:59:11.515329 [TxChooseVref] Worse bit 0, Min win 25, Win sum 417, Final Vref 28
7712 22:59:11.515453
7713 22:59:11.518952 Final TX Range 0 Vref 28
7714 22:59:11.519048
7715 22:59:11.519119 ==
7716 22:59:11.522421 Dram Type= 6, Freq= 0, CH_0, rank 0
7717 22:59:11.525495 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7718 22:59:11.525618 ==
7719 22:59:11.525725
7720 22:59:11.525824
7721 22:59:11.528574 TX Vref Scan disable
7722 22:59:11.535229 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7723 22:59:11.535380 == TX Byte 0 ==
7724 22:59:11.538930 u2DelayCellOfst[0]=17 cells (5 PI)
7725 22:59:11.541901 u2DelayCellOfst[1]=21 cells (6 PI)
7726 22:59:11.545100 u2DelayCellOfst[2]=14 cells (4 PI)
7727 22:59:11.548617 u2DelayCellOfst[3]=14 cells (4 PI)
7728 22:59:11.551672 u2DelayCellOfst[4]=10 cells (3 PI)
7729 22:59:11.554959 u2DelayCellOfst[5]=0 cells (0 PI)
7730 22:59:11.558644 u2DelayCellOfst[6]=21 cells (6 PI)
7731 22:59:11.561742 u2DelayCellOfst[7]=21 cells (6 PI)
7732 22:59:11.565505 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7733 22:59:11.568578 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7734 22:59:11.571898 == TX Byte 1 ==
7735 22:59:11.574996 u2DelayCellOfst[8]=0 cells (0 PI)
7736 22:59:11.578725 u2DelayCellOfst[9]=0 cells (0 PI)
7737 22:59:11.578849 u2DelayCellOfst[10]=7 cells (2 PI)
7738 22:59:11.581872 u2DelayCellOfst[11]=0 cells (0 PI)
7739 22:59:11.584997 u2DelayCellOfst[12]=14 cells (4 PI)
7740 22:59:11.588322 u2DelayCellOfst[13]=10 cells (3 PI)
7741 22:59:11.591462 u2DelayCellOfst[14]=17 cells (5 PI)
7742 22:59:11.595387 u2DelayCellOfst[15]=14 cells (4 PI)
7743 22:59:11.601613 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7744 22:59:11.604722 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7745 22:59:11.604858 DramC Write-DBI on
7746 22:59:11.604963 ==
7747 22:59:11.608432 Dram Type= 6, Freq= 0, CH_0, rank 0
7748 22:59:11.614561 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7749 22:59:11.614697 ==
7750 22:59:11.614799
7751 22:59:11.614891
7752 22:59:11.614984 TX Vref Scan disable
7753 22:59:11.618970 == TX Byte 0 ==
7754 22:59:11.621964 Update DQM dly =732 (2 ,6, 28) DQM OEN =(3 ,3)
7755 22:59:11.625465 == TX Byte 1 ==
7756 22:59:11.629121 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
7757 22:59:11.632173 DramC Write-DBI off
7758 22:59:11.632295
7759 22:59:11.632397 [DATLAT]
7760 22:59:11.632495 Freq=1600, CH0 RK0
7761 22:59:11.632591
7762 22:59:11.635169 DATLAT Default: 0xf
7763 22:59:11.635280 0, 0xFFFF, sum = 0
7764 22:59:11.638633 1, 0xFFFF, sum = 0
7765 22:59:11.642279 2, 0xFFFF, sum = 0
7766 22:59:11.642404 3, 0xFFFF, sum = 0
7767 22:59:11.645199 4, 0xFFFF, sum = 0
7768 22:59:11.645311 5, 0xFFFF, sum = 0
7769 22:59:11.648878 6, 0xFFFF, sum = 0
7770 22:59:11.648998 7, 0xFFFF, sum = 0
7771 22:59:11.652099 8, 0xFFFF, sum = 0
7772 22:59:11.652210 9, 0xFFFF, sum = 0
7773 22:59:11.655788 10, 0xFFFF, sum = 0
7774 22:59:11.655911 11, 0xFFFF, sum = 0
7775 22:59:11.658814 12, 0xFFFF, sum = 0
7776 22:59:11.658936 13, 0xFFFF, sum = 0
7777 22:59:11.661858 14, 0x0, sum = 1
7778 22:59:11.661976 15, 0x0, sum = 2
7779 22:59:11.665032 16, 0x0, sum = 3
7780 22:59:11.665153 17, 0x0, sum = 4
7781 22:59:11.668383 best_step = 15
7782 22:59:11.668498
7783 22:59:11.668610 ==
7784 22:59:11.671574 Dram Type= 6, Freq= 0, CH_0, rank 0
7785 22:59:11.675246 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7786 22:59:11.675395 ==
7787 22:59:11.678529 RX Vref Scan: 1
7788 22:59:11.678655
7789 22:59:11.678763 Set Vref Range= 24 -> 127
7790 22:59:11.678869
7791 22:59:11.681548 RX Vref 24 -> 127, step: 1
7792 22:59:11.681672
7793 22:59:11.685325 RX Delay 11 -> 252, step: 4
7794 22:59:11.685422
7795 22:59:11.688447 Set Vref, RX VrefLevel [Byte0]: 24
7796 22:59:11.691560 [Byte1]: 24
7797 22:59:11.691656
7798 22:59:11.695229 Set Vref, RX VrefLevel [Byte0]: 25
7799 22:59:11.698470 [Byte1]: 25
7800 22:59:11.701574
7801 22:59:11.701695 Set Vref, RX VrefLevel [Byte0]: 26
7802 22:59:11.704876 [Byte1]: 26
7803 22:59:11.709061
7804 22:59:11.709179 Set Vref, RX VrefLevel [Byte0]: 27
7805 22:59:11.712720 [Byte1]: 27
7806 22:59:11.717026
7807 22:59:11.717127 Set Vref, RX VrefLevel [Byte0]: 28
7808 22:59:11.720119 [Byte1]: 28
7809 22:59:11.724347
7810 22:59:11.724447 Set Vref, RX VrefLevel [Byte0]: 29
7811 22:59:11.727945 [Byte1]: 29
7812 22:59:11.732165
7813 22:59:11.732264 Set Vref, RX VrefLevel [Byte0]: 30
7814 22:59:11.735235 [Byte1]: 30
7815 22:59:11.740146
7816 22:59:11.743106 Set Vref, RX VrefLevel [Byte0]: 31
7817 22:59:11.745994 [Byte1]: 31
7818 22:59:11.746092
7819 22:59:11.749657 Set Vref, RX VrefLevel [Byte0]: 32
7820 22:59:11.752685 [Byte1]: 32
7821 22:59:11.752780
7822 22:59:11.756286 Set Vref, RX VrefLevel [Byte0]: 33
7823 22:59:11.759270 [Byte1]: 33
7824 22:59:11.762810
7825 22:59:11.762908 Set Vref, RX VrefLevel [Byte0]: 34
7826 22:59:11.765989 [Byte1]: 34
7827 22:59:11.770392
7828 22:59:11.770486 Set Vref, RX VrefLevel [Byte0]: 35
7829 22:59:11.773634 [Byte1]: 35
7830 22:59:11.778039
7831 22:59:11.778138 Set Vref, RX VrefLevel [Byte0]: 36
7832 22:59:11.781131 [Byte1]: 36
7833 22:59:11.785603
7834 22:59:11.785723 Set Vref, RX VrefLevel [Byte0]: 37
7835 22:59:11.789141 [Byte1]: 37
7836 22:59:11.793002
7837 22:59:11.793132 Set Vref, RX VrefLevel [Byte0]: 38
7838 22:59:11.796129 [Byte1]: 38
7839 22:59:11.800721
7840 22:59:11.800854 Set Vref, RX VrefLevel [Byte0]: 39
7841 22:59:11.803779 [Byte1]: 39
7842 22:59:11.808243
7843 22:59:11.808368 Set Vref, RX VrefLevel [Byte0]: 40
7844 22:59:11.811455 [Byte1]: 40
7845 22:59:11.815705
7846 22:59:11.815834 Set Vref, RX VrefLevel [Byte0]: 41
7847 22:59:11.819260 [Byte1]: 41
7848 22:59:11.823615
7849 22:59:11.823760 Set Vref, RX VrefLevel [Byte0]: 42
7850 22:59:11.826715 [Byte1]: 42
7851 22:59:11.830883
7852 22:59:11.831026 Set Vref, RX VrefLevel [Byte0]: 43
7853 22:59:11.834459 [Byte1]: 43
7854 22:59:11.838677
7855 22:59:11.838816 Set Vref, RX VrefLevel [Byte0]: 44
7856 22:59:11.842096 [Byte1]: 44
7857 22:59:11.846515
7858 22:59:11.846609 Set Vref, RX VrefLevel [Byte0]: 45
7859 22:59:11.849485 [Byte1]: 45
7860 22:59:11.853729
7861 22:59:11.853859 Set Vref, RX VrefLevel [Byte0]: 46
7862 22:59:11.857420 [Byte1]: 46
7863 22:59:11.861571
7864 22:59:11.861722 Set Vref, RX VrefLevel [Byte0]: 47
7865 22:59:11.864731 [Byte1]: 47
7866 22:59:11.869032
7867 22:59:11.869161 Set Vref, RX VrefLevel [Byte0]: 48
7868 22:59:11.875435 [Byte1]: 48
7869 22:59:11.875536
7870 22:59:11.879190 Set Vref, RX VrefLevel [Byte0]: 49
7871 22:59:11.882395 [Byte1]: 49
7872 22:59:11.882493
7873 22:59:11.885567 Set Vref, RX VrefLevel [Byte0]: 50
7874 22:59:11.888657 [Byte1]: 50
7875 22:59:11.892415
7876 22:59:11.892543 Set Vref, RX VrefLevel [Byte0]: 51
7877 22:59:11.895533 [Byte1]: 51
7878 22:59:11.899952
7879 22:59:11.900077 Set Vref, RX VrefLevel [Byte0]: 52
7880 22:59:11.903160 [Byte1]: 52
7881 22:59:11.907576
7882 22:59:11.907698 Set Vref, RX VrefLevel [Byte0]: 53
7883 22:59:11.910603 [Byte1]: 53
7884 22:59:11.915109
7885 22:59:11.915237 Set Vref, RX VrefLevel [Byte0]: 54
7886 22:59:11.918189 [Byte1]: 54
7887 22:59:11.922346
7888 22:59:11.922453 Set Vref, RX VrefLevel [Byte0]: 55
7889 22:59:11.925572 [Byte1]: 55
7890 22:59:11.930514
7891 22:59:11.930624 Set Vref, RX VrefLevel [Byte0]: 56
7892 22:59:11.933509 [Byte1]: 56
7893 22:59:11.937751
7894 22:59:11.937870 Set Vref, RX VrefLevel [Byte0]: 57
7895 22:59:11.941487 [Byte1]: 57
7896 22:59:11.945598
7897 22:59:11.945732 Set Vref, RX VrefLevel [Byte0]: 58
7898 22:59:11.948437 [Byte1]: 58
7899 22:59:11.952800
7900 22:59:11.952920 Set Vref, RX VrefLevel [Byte0]: 59
7901 22:59:11.956345 [Byte1]: 59
7902 22:59:11.960629
7903 22:59:11.960747 Set Vref, RX VrefLevel [Byte0]: 60
7904 22:59:11.963634 [Byte1]: 60
7905 22:59:11.968462
7906 22:59:11.968578 Set Vref, RX VrefLevel [Byte0]: 61
7907 22:59:11.971453 [Byte1]: 61
7908 22:59:11.975784
7909 22:59:11.975885 Set Vref, RX VrefLevel [Byte0]: 62
7910 22:59:11.978986 [Byte1]: 62
7911 22:59:11.983379
7912 22:59:11.983473 Set Vref, RX VrefLevel [Byte0]: 63
7913 22:59:11.986650 [Byte1]: 63
7914 22:59:11.990948
7915 22:59:11.991071 Set Vref, RX VrefLevel [Byte0]: 64
7916 22:59:11.994213 [Byte1]: 64
7917 22:59:11.998694
7918 22:59:11.998786 Set Vref, RX VrefLevel [Byte0]: 65
7919 22:59:12.001725 [Byte1]: 65
7920 22:59:12.006201
7921 22:59:12.006286 Set Vref, RX VrefLevel [Byte0]: 66
7922 22:59:12.009844 [Byte1]: 66
7923 22:59:12.013718
7924 22:59:12.013814 Set Vref, RX VrefLevel [Byte0]: 67
7925 22:59:12.017306 [Byte1]: 67
7926 22:59:12.021773
7927 22:59:12.021858 Set Vref, RX VrefLevel [Byte0]: 68
7928 22:59:12.024845 [Byte1]: 68
7929 22:59:12.028948
7930 22:59:12.029047 Set Vref, RX VrefLevel [Byte0]: 69
7931 22:59:12.032709 [Byte1]: 69
7932 22:59:12.037029
7933 22:59:12.037119 Set Vref, RX VrefLevel [Byte0]: 70
7934 22:59:12.040147 [Byte1]: 70
7935 22:59:12.044305
7936 22:59:12.044400 Set Vref, RX VrefLevel [Byte0]: 71
7937 22:59:12.047769 [Byte1]: 71
7938 22:59:12.051736
7939 22:59:12.051826 Set Vref, RX VrefLevel [Byte0]: 72
7940 22:59:12.055444 [Byte1]: 72
7941 22:59:12.059685
7942 22:59:12.059786 Set Vref, RX VrefLevel [Byte0]: 73
7943 22:59:12.062618 [Byte1]: 73
7944 22:59:12.066913
7945 22:59:12.066999 Set Vref, RX VrefLevel [Byte0]: 74
7946 22:59:12.070510 [Byte1]: 74
7947 22:59:12.074798
7948 22:59:12.074884 Set Vref, RX VrefLevel [Byte0]: 75
7949 22:59:12.077916 [Byte1]: 75
7950 22:59:12.082314
7951 22:59:12.082397 Set Vref, RX VrefLevel [Byte0]: 76
7952 22:59:12.085503 [Byte1]: 76
7953 22:59:12.090058
7954 22:59:12.090151 Final RX Vref Byte 0 = 63 to rank0
7955 22:59:12.093033 Final RX Vref Byte 1 = 62 to rank0
7956 22:59:12.096731 Final RX Vref Byte 0 = 63 to rank1
7957 22:59:12.099868 Final RX Vref Byte 1 = 62 to rank1==
7958 22:59:12.103011 Dram Type= 6, Freq= 0, CH_0, rank 0
7959 22:59:12.110117 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7960 22:59:12.110223 ==
7961 22:59:12.110323 DQS Delay:
7962 22:59:12.110393 DQS0 = 0, DQS1 = 0
7963 22:59:12.113268 DQM Delay:
7964 22:59:12.113345 DQM0 = 129, DQM1 = 122
7965 22:59:12.116393 DQ Delay:
7966 22:59:12.119522 DQ0 =130, DQ1 =132, DQ2 =126, DQ3 =126
7967 22:59:12.123210 DQ4 =132, DQ5 =118, DQ6 =136, DQ7 =138
7968 22:59:12.126438 DQ8 =110, DQ9 =110, DQ10 =122, DQ11 =118
7969 22:59:12.130020 DQ12 =128, DQ13 =126, DQ14 =132, DQ15 =134
7970 22:59:12.130106
7971 22:59:12.130186
7972 22:59:12.130257
7973 22:59:12.133172 [DramC_TX_OE_Calibration] TA2
7974 22:59:12.136178 Original DQ_B0 (3 6) =30, OEN = 27
7975 22:59:12.139935 Original DQ_B1 (3 6) =30, OEN = 27
7976 22:59:12.143105 24, 0x0, End_B0=24 End_B1=24
7977 22:59:12.143209 25, 0x0, End_B0=25 End_B1=25
7978 22:59:12.146579 26, 0x0, End_B0=26 End_B1=26
7979 22:59:12.149673 27, 0x0, End_B0=27 End_B1=27
7980 22:59:12.153257 28, 0x0, End_B0=28 End_B1=28
7981 22:59:12.153340 29, 0x0, End_B0=29 End_B1=29
7982 22:59:12.156346 30, 0x0, End_B0=30 End_B1=30
7983 22:59:12.160003 31, 0x4141, End_B0=30 End_B1=30
7984 22:59:12.162893 Byte0 end_step=30 best_step=27
7985 22:59:12.166534 Byte1 end_step=30 best_step=27
7986 22:59:12.169491 Byte0 TX OE(2T, 0.5T) = (3, 3)
7987 22:59:12.173128 Byte1 TX OE(2T, 0.5T) = (3, 3)
7988 22:59:12.173212
7989 22:59:12.173293
7990 22:59:12.179305 [DQSOSCAuto] RK0, (LSB)MR18= 0x1004, (MSB)MR19= 0x303, tDQSOscB0 = 408 ps tDQSOscB1 = 401 ps
7991 22:59:12.183087 CH0 RK0: MR19=303, MR18=1004
7992 22:59:12.189414 CH0_RK0: MR19=0x303, MR18=0x1004, DQSOSC=401, MR23=63, INC=22, DEC=15
7993 22:59:12.189509
7994 22:59:12.193056 ----->DramcWriteLeveling(PI) begin...
7995 22:59:12.193138 ==
7996 22:59:12.196662 Dram Type= 6, Freq= 0, CH_0, rank 1
7997 22:59:12.199916 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7998 22:59:12.200006 ==
7999 22:59:12.203037 Write leveling (Byte 0): 33 => 33
8000 22:59:12.206237 Write leveling (Byte 1): 27 => 27
8001 22:59:12.209507 DramcWriteLeveling(PI) end<-----
8002 22:59:12.209585
8003 22:59:12.209649 ==
8004 22:59:12.212634 Dram Type= 6, Freq= 0, CH_0, rank 1
8005 22:59:12.216594 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8006 22:59:12.216686 ==
8007 22:59:12.219687 [Gating] SW mode calibration
8008 22:59:12.225868 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8009 22:59:12.232774 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8010 22:59:12.236504 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8011 22:59:12.239488 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8012 22:59:12.245693 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8013 22:59:12.249424 1 4 12 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (1 1)
8014 22:59:12.252518 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8015 22:59:12.259556 1 4 20 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 1)
8016 22:59:12.262609 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8017 22:59:12.265670 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8018 22:59:12.272767 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8019 22:59:12.275818 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8020 22:59:12.278905 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8021 22:59:12.285621 1 5 12 | B1->B0 | 3434 2525 | 1 0 | (1 1) (0 0)
8022 22:59:12.289359 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8023 22:59:12.292553 1 5 20 | B1->B0 | 3030 2323 | 1 0 | (1 0) (0 0)
8024 22:59:12.299306 1 5 24 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
8025 22:59:12.302435 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8026 22:59:12.305521 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8027 22:59:12.312493 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8028 22:59:12.315611 1 6 8 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
8029 22:59:12.319558 1 6 12 | B1->B0 | 2323 4444 | 0 0 | (0 0) (0 0)
8030 22:59:12.325817 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8031 22:59:12.329441 1 6 20 | B1->B0 | 3939 4646 | 0 0 | (1 1) (0 0)
8032 22:59:12.332674 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8033 22:59:12.339483 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8034 22:59:12.342469 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8035 22:59:12.345657 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8036 22:59:12.352561 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8037 22:59:12.355517 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8038 22:59:12.358956 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8039 22:59:12.362133 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8040 22:59:12.368696 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8041 22:59:12.372321 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8042 22:59:12.375915 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8043 22:59:12.382505 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8044 22:59:12.385436 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8045 22:59:12.389157 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8046 22:59:12.395489 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8047 22:59:12.398679 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8048 22:59:12.401894 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8049 22:59:12.408744 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8050 22:59:12.412038 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8051 22:59:12.415094 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8052 22:59:12.422190 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8053 22:59:12.425408 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8054 22:59:12.428459 Total UI for P1: 0, mck2ui 16
8055 22:59:12.432221 best dqsien dly found for B0: ( 1, 9, 6)
8056 22:59:12.435307 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8057 22:59:12.442164 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8058 22:59:12.445122 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8059 22:59:12.448243 Total UI for P1: 0, mck2ui 16
8060 22:59:12.451498 best dqsien dly found for B1: ( 1, 9, 20)
8061 22:59:12.454970 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8062 22:59:12.458593 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
8063 22:59:12.458700
8064 22:59:12.461647 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8065 22:59:12.464601 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
8066 22:59:12.468321 [Gating] SW calibration Done
8067 22:59:12.468408 ==
8068 22:59:12.471291 Dram Type= 6, Freq= 0, CH_0, rank 1
8069 22:59:12.477952 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8070 22:59:12.478054 ==
8071 22:59:12.478122 RX Vref Scan: 0
8072 22:59:12.478199
8073 22:59:12.481472 RX Vref 0 -> 0, step: 1
8074 22:59:12.481550
8075 22:59:12.485149 RX Delay 0 -> 252, step: 8
8076 22:59:12.488308 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8077 22:59:12.491394 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8078 22:59:12.495140 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8079 22:59:12.498240 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8080 22:59:12.504513 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8081 22:59:12.507741 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8082 22:59:12.511513 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8083 22:59:12.514583 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8084 22:59:12.517827 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8085 22:59:12.524593 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8086 22:59:12.527739 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8087 22:59:12.531502 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8088 22:59:12.534635 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8089 22:59:12.537782 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8090 22:59:12.544772 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8091 22:59:12.547850 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8092 22:59:12.547936 ==
8093 22:59:12.550924 Dram Type= 6, Freq= 0, CH_0, rank 1
8094 22:59:12.554616 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8095 22:59:12.554708 ==
8096 22:59:12.557666 DQS Delay:
8097 22:59:12.557743 DQS0 = 0, DQS1 = 0
8098 22:59:12.557819 DQM Delay:
8099 22:59:12.561322 DQM0 = 130, DQM1 = 124
8100 22:59:12.561426 DQ Delay:
8101 22:59:12.564320 DQ0 =131, DQ1 =131, DQ2 =127, DQ3 =127
8102 22:59:12.568014 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
8103 22:59:12.570965 DQ8 =115, DQ9 =115, DQ10 =123, DQ11 =119
8104 22:59:12.577592 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
8105 22:59:12.577691
8106 22:59:12.577771
8107 22:59:12.577838 ==
8108 22:59:12.581221 Dram Type= 6, Freq= 0, CH_0, rank 1
8109 22:59:12.584388 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8110 22:59:12.584539 ==
8111 22:59:12.584607
8112 22:59:12.584680
8113 22:59:12.588006 TX Vref Scan disable
8114 22:59:12.588091 == TX Byte 0 ==
8115 22:59:12.594604 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8116 22:59:12.597701 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8117 22:59:12.597785 == TX Byte 1 ==
8118 22:59:12.604460 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8119 22:59:12.607708 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8120 22:59:12.607802 ==
8121 22:59:12.610825 Dram Type= 6, Freq= 0, CH_0, rank 1
8122 22:59:12.614540 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8123 22:59:12.614631 ==
8124 22:59:12.630303
8125 22:59:12.633539 TX Vref early break, caculate TX vref
8126 22:59:12.636623 TX Vref=16, minBit 9, minWin=22, winSum=376
8127 22:59:12.640367 TX Vref=18, minBit 9, minWin=22, winSum=387
8128 22:59:12.643616 TX Vref=20, minBit 3, minWin=23, winSum=396
8129 22:59:12.646795 TX Vref=22, minBit 3, minWin=24, winSum=398
8130 22:59:12.650581 TX Vref=24, minBit 1, minWin=25, winSum=410
8131 22:59:12.656737 TX Vref=26, minBit 9, minWin=24, winSum=411
8132 22:59:12.660528 TX Vref=28, minBit 10, minWin=25, winSum=422
8133 22:59:12.663535 TX Vref=30, minBit 3, minWin=25, winSum=422
8134 22:59:12.667071 TX Vref=32, minBit 8, minWin=24, winSum=411
8135 22:59:12.670108 TX Vref=34, minBit 0, minWin=25, winSum=405
8136 22:59:12.673716 TX Vref=36, minBit 0, minWin=24, winSum=394
8137 22:59:12.679943 [TxChooseVref] Worse bit 10, Min win 25, Win sum 422, Final Vref 28
8138 22:59:12.680039
8139 22:59:12.683380 Final TX Range 0 Vref 28
8140 22:59:12.683485
8141 22:59:12.683551 ==
8142 22:59:12.686497 Dram Type= 6, Freq= 0, CH_0, rank 1
8143 22:59:12.690198 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8144 22:59:12.690281 ==
8145 22:59:12.690355
8146 22:59:12.690433
8147 22:59:12.693165 TX Vref Scan disable
8148 22:59:12.699798 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8149 22:59:12.699896 == TX Byte 0 ==
8150 22:59:12.703492 u2DelayCellOfst[0]=14 cells (4 PI)
8151 22:59:12.706569 u2DelayCellOfst[1]=21 cells (6 PI)
8152 22:59:12.710391 u2DelayCellOfst[2]=14 cells (4 PI)
8153 22:59:12.713530 u2DelayCellOfst[3]=14 cells (4 PI)
8154 22:59:12.716675 u2DelayCellOfst[4]=10 cells (3 PI)
8155 22:59:12.719828 u2DelayCellOfst[5]=0 cells (0 PI)
8156 22:59:12.723177 u2DelayCellOfst[6]=21 cells (6 PI)
8157 22:59:12.726842 u2DelayCellOfst[7]=21 cells (6 PI)
8158 22:59:12.729847 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
8159 22:59:12.733155 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8160 22:59:12.736354 == TX Byte 1 ==
8161 22:59:12.739994 u2DelayCellOfst[8]=0 cells (0 PI)
8162 22:59:12.743283 u2DelayCellOfst[9]=0 cells (0 PI)
8163 22:59:12.746314 u2DelayCellOfst[10]=7 cells (2 PI)
8164 22:59:12.746403 u2DelayCellOfst[11]=0 cells (0 PI)
8165 22:59:12.750151 u2DelayCellOfst[12]=10 cells (3 PI)
8166 22:59:12.753234 u2DelayCellOfst[13]=10 cells (3 PI)
8167 22:59:12.756381 u2DelayCellOfst[14]=14 cells (4 PI)
8168 22:59:12.760037 u2DelayCellOfst[15]=10 cells (3 PI)
8169 22:59:12.766836 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8170 22:59:12.769779 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8171 22:59:12.769875 DramC Write-DBI on
8172 22:59:12.769954 ==
8173 22:59:12.773432 Dram Type= 6, Freq= 0, CH_0, rank 1
8174 22:59:12.779595 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8175 22:59:12.779697 ==
8176 22:59:12.779769
8177 22:59:12.779831
8178 22:59:12.779891 TX Vref Scan disable
8179 22:59:12.783954 == TX Byte 0 ==
8180 22:59:12.786937 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
8181 22:59:12.790453 == TX Byte 1 ==
8182 22:59:12.794121 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8183 22:59:12.797235 DramC Write-DBI off
8184 22:59:12.797335
8185 22:59:12.797400 [DATLAT]
8186 22:59:12.797474 Freq=1600, CH0 RK1
8187 22:59:12.797542
8188 22:59:12.800274 DATLAT Default: 0xf
8189 22:59:12.803933 0, 0xFFFF, sum = 0
8190 22:59:12.804016 1, 0xFFFF, sum = 0
8191 22:59:12.807059 2, 0xFFFF, sum = 0
8192 22:59:12.807151 3, 0xFFFF, sum = 0
8193 22:59:12.810122 4, 0xFFFF, sum = 0
8194 22:59:12.810197 5, 0xFFFF, sum = 0
8195 22:59:12.813900 6, 0xFFFF, sum = 0
8196 22:59:12.813990 7, 0xFFFF, sum = 0
8197 22:59:12.817060 8, 0xFFFF, sum = 0
8198 22:59:12.817151 9, 0xFFFF, sum = 0
8199 22:59:12.820246 10, 0xFFFF, sum = 0
8200 22:59:12.820322 11, 0xFFFF, sum = 0
8201 22:59:12.823418 12, 0xFFFF, sum = 0
8202 22:59:12.823494 13, 0xFFFF, sum = 0
8203 22:59:12.826693 14, 0x0, sum = 1
8204 22:59:12.826767 15, 0x0, sum = 2
8205 22:59:12.830330 16, 0x0, sum = 3
8206 22:59:12.830407 17, 0x0, sum = 4
8207 22:59:12.833553 best_step = 15
8208 22:59:12.833629
8209 22:59:12.833708 ==
8210 22:59:12.836586 Dram Type= 6, Freq= 0, CH_0, rank 1
8211 22:59:12.840475 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8212 22:59:12.840570 ==
8213 22:59:12.843552 RX Vref Scan: 0
8214 22:59:12.843634
8215 22:59:12.843697 RX Vref 0 -> 0, step: 1
8216 22:59:12.843758
8217 22:59:12.846750 RX Delay 11 -> 252, step: 4
8218 22:59:12.850600 iDelay=191, Bit 0, Center 128 (71 ~ 186) 116
8219 22:59:12.856769 iDelay=191, Bit 1, Center 130 (75 ~ 186) 112
8220 22:59:12.860354 iDelay=191, Bit 2, Center 124 (71 ~ 178) 108
8221 22:59:12.863299 iDelay=191, Bit 3, Center 126 (71 ~ 182) 112
8222 22:59:12.866490 iDelay=191, Bit 4, Center 128 (75 ~ 182) 108
8223 22:59:12.870214 iDelay=191, Bit 5, Center 116 (63 ~ 170) 108
8224 22:59:12.876894 iDelay=191, Bit 6, Center 136 (83 ~ 190) 108
8225 22:59:12.879862 iDelay=191, Bit 7, Center 136 (83 ~ 190) 108
8226 22:59:12.883666 iDelay=191, Bit 8, Center 114 (59 ~ 170) 112
8227 22:59:12.886654 iDelay=191, Bit 9, Center 110 (55 ~ 166) 112
8228 22:59:12.890248 iDelay=191, Bit 10, Center 122 (67 ~ 178) 112
8229 22:59:12.896793 iDelay=191, Bit 11, Center 116 (63 ~ 170) 108
8230 22:59:12.899912 iDelay=191, Bit 12, Center 126 (75 ~ 178) 104
8231 22:59:12.903591 iDelay=191, Bit 13, Center 130 (75 ~ 186) 112
8232 22:59:12.906505 iDelay=191, Bit 14, Center 134 (79 ~ 190) 112
8233 22:59:12.913269 iDelay=191, Bit 15, Center 132 (75 ~ 190) 116
8234 22:59:12.913378 ==
8235 22:59:12.916485 Dram Type= 6, Freq= 0, CH_0, rank 1
8236 22:59:12.919804 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8237 22:59:12.919885 ==
8238 22:59:12.919970 DQS Delay:
8239 22:59:12.922827 DQS0 = 0, DQS1 = 0
8240 22:59:12.922908 DQM Delay:
8241 22:59:12.926630 DQM0 = 128, DQM1 = 123
8242 22:59:12.926712 DQ Delay:
8243 22:59:12.929810 DQ0 =128, DQ1 =130, DQ2 =124, DQ3 =126
8244 22:59:12.932954 DQ4 =128, DQ5 =116, DQ6 =136, DQ7 =136
8245 22:59:12.936119 DQ8 =114, DQ9 =110, DQ10 =122, DQ11 =116
8246 22:59:12.939496 DQ12 =126, DQ13 =130, DQ14 =134, DQ15 =132
8247 22:59:12.939582
8248 22:59:12.939666
8249 22:59:12.939746
8250 22:59:12.943190 [DramC_TX_OE_Calibration] TA2
8251 22:59:12.946446 Original DQ_B0 (3 6) =30, OEN = 27
8252 22:59:12.949438 Original DQ_B1 (3 6) =30, OEN = 27
8253 22:59:12.953375 24, 0x0, End_B0=24 End_B1=24
8254 22:59:12.956506 25, 0x0, End_B0=25 End_B1=25
8255 22:59:12.956591 26, 0x0, End_B0=26 End_B1=26
8256 22:59:12.959746 27, 0x0, End_B0=27 End_B1=27
8257 22:59:12.962796 28, 0x0, End_B0=28 End_B1=28
8258 22:59:12.966500 29, 0x0, End_B0=29 End_B1=29
8259 22:59:12.969523 30, 0x0, End_B0=30 End_B1=30
8260 22:59:12.969612 31, 0x5151, End_B0=30 End_B1=30
8261 22:59:12.972695 Byte0 end_step=30 best_step=27
8262 22:59:12.976171 Byte1 end_step=30 best_step=27
8263 22:59:12.979785 Byte0 TX OE(2T, 0.5T) = (3, 3)
8264 22:59:12.982596 Byte1 TX OE(2T, 0.5T) = (3, 3)
8265 22:59:12.982678
8266 22:59:12.982743
8267 22:59:12.989360 [DQSOSCAuto] RK1, (LSB)MR18= 0x150a, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 399 ps
8268 22:59:12.992474 CH0 RK1: MR19=303, MR18=150A
8269 22:59:12.999619 CH0_RK1: MR19=0x303, MR18=0x150A, DQSOSC=399, MR23=63, INC=23, DEC=15
8270 22:59:13.002507 [RxdqsGatingPostProcess] freq 1600
8271 22:59:13.009842 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8272 22:59:13.012794 best DQS0 dly(2T, 0.5T) = (1, 1)
8273 22:59:13.012903 best DQS1 dly(2T, 0.5T) = (1, 1)
8274 22:59:13.015772 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8275 22:59:13.019492 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8276 22:59:13.022612 best DQS0 dly(2T, 0.5T) = (1, 1)
8277 22:59:13.025799 best DQS1 dly(2T, 0.5T) = (1, 1)
8278 22:59:13.029608 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8279 22:59:13.032770 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8280 22:59:13.036028 Pre-setting of DQS Precalculation
8281 22:59:13.039210 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8282 22:59:13.039299 ==
8283 22:59:13.042377 Dram Type= 6, Freq= 0, CH_1, rank 0
8284 22:59:13.049204 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8285 22:59:13.049317 ==
8286 22:59:13.052361 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8287 22:59:13.059528 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8288 22:59:13.062606 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8289 22:59:13.069330 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8290 22:59:13.076809 [CA 0] Center 42 (14~71) winsize 58
8291 22:59:13.080225 [CA 1] Center 42 (13~71) winsize 59
8292 22:59:13.083657 [CA 2] Center 37 (9~66) winsize 58
8293 22:59:13.086693 [CA 3] Center 37 (8~66) winsize 59
8294 22:59:13.090320 [CA 4] Center 37 (8~66) winsize 59
8295 22:59:13.093361 [CA 5] Center 36 (7~66) winsize 60
8296 22:59:13.093496
8297 22:59:13.096929 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8298 22:59:13.097020
8299 22:59:13.100024 [CATrainingPosCal] consider 1 rank data
8300 22:59:13.103624 u2DelayCellTimex100 = 275/100 ps
8301 22:59:13.106556 CA0 delay=42 (14~71),Diff = 6 PI (21 cell)
8302 22:59:13.113650 CA1 delay=42 (13~71),Diff = 6 PI (21 cell)
8303 22:59:13.116717 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8304 22:59:13.120516 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8305 22:59:13.123570 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8306 22:59:13.126774 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8307 22:59:13.126869
8308 22:59:13.129849 CA PerBit enable=1, Macro0, CA PI delay=36
8309 22:59:13.129936
8310 22:59:13.133715 [CBTSetCACLKResult] CA Dly = 36
8311 22:59:13.136760 CS Dly: 8 (0~39)
8312 22:59:13.139896 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8313 22:59:13.143607 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8314 22:59:13.143693 ==
8315 22:59:13.146772 Dram Type= 6, Freq= 0, CH_1, rank 1
8316 22:59:13.149877 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8317 22:59:13.150000 ==
8318 22:59:13.156784 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8319 22:59:13.159924 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8320 22:59:13.166414 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8321 22:59:13.170136 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8322 22:59:13.179799 [CA 0] Center 43 (15~72) winsize 58
8323 22:59:13.183476 [CA 1] Center 43 (14~72) winsize 59
8324 22:59:13.186557 [CA 2] Center 38 (9~67) winsize 59
8325 22:59:13.189598 [CA 3] Center 37 (8~67) winsize 60
8326 22:59:13.193078 [CA 4] Center 38 (9~68) winsize 60
8327 22:59:13.196765 [CA 5] Center 37 (8~66) winsize 59
8328 22:59:13.196893
8329 22:59:13.199700 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8330 22:59:13.199834
8331 22:59:13.203095 [CATrainingPosCal] consider 2 rank data
8332 22:59:13.206382 u2DelayCellTimex100 = 275/100 ps
8333 22:59:13.210202 CA0 delay=43 (15~71),Diff = 6 PI (21 cell)
8334 22:59:13.216912 CA1 delay=42 (14~71),Diff = 5 PI (17 cell)
8335 22:59:13.219819 CA2 delay=37 (9~66),Diff = 0 PI (0 cell)
8336 22:59:13.222959 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8337 22:59:13.226651 CA4 delay=37 (9~66),Diff = 0 PI (0 cell)
8338 22:59:13.229677 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8339 22:59:13.229822
8340 22:59:13.233343 CA PerBit enable=1, Macro0, CA PI delay=37
8341 22:59:13.233473
8342 22:59:13.236597 [CBTSetCACLKResult] CA Dly = 37
8343 22:59:13.239792 CS Dly: 11 (0~45)
8344 22:59:13.242890 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8345 22:59:13.246559 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8346 22:59:13.246698
8347 22:59:13.249767 ----->DramcWriteLeveling(PI) begin...
8348 22:59:13.249905 ==
8349 22:59:13.252933 Dram Type= 6, Freq= 0, CH_1, rank 0
8350 22:59:13.256050 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8351 22:59:13.259795 ==
8352 22:59:13.262858 Write leveling (Byte 0): 23 => 23
8353 22:59:13.262997 Write leveling (Byte 1): 27 => 27
8354 22:59:13.266619 DramcWriteLeveling(PI) end<-----
8355 22:59:13.266706
8356 22:59:13.266804 ==
8357 22:59:13.269657 Dram Type= 6, Freq= 0, CH_1, rank 0
8358 22:59:13.276018 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8359 22:59:13.276128 ==
8360 22:59:13.279704 [Gating] SW mode calibration
8361 22:59:13.285852 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8362 22:59:13.289504 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8363 22:59:13.296134 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8364 22:59:13.299622 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8365 22:59:13.302583 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8366 22:59:13.309307 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8367 22:59:13.313077 1 4 16 | B1->B0 | 2e2e 2b2b | 0 0 | (0 0) (0 0)
8368 22:59:13.315917 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8369 22:59:13.322731 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8370 22:59:13.325848 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8371 22:59:13.329068 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8372 22:59:13.332856 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8373 22:59:13.339195 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8374 22:59:13.342922 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8375 22:59:13.346077 1 5 16 | B1->B0 | 2b2b 3232 | 0 1 | (0 1) (1 0)
8376 22:59:13.352369 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8377 22:59:13.356105 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8378 22:59:13.359211 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8379 22:59:13.366075 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8380 22:59:13.369243 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8381 22:59:13.372478 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8382 22:59:13.379192 1 6 12 | B1->B0 | 2424 2525 | 0 0 | (0 0) (0 0)
8383 22:59:13.382298 1 6 16 | B1->B0 | 3737 2d2d | 0 0 | (0 0) (0 0)
8384 22:59:13.385857 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8385 22:59:13.392085 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8386 22:59:13.395749 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8387 22:59:13.398821 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8388 22:59:13.405649 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8389 22:59:13.409169 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8390 22:59:13.412267 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8391 22:59:13.419039 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8392 22:59:13.422608 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8393 22:59:13.425612 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8394 22:59:13.432305 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8395 22:59:13.435456 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8396 22:59:13.438541 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8397 22:59:13.445563 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8398 22:59:13.448587 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8399 22:59:13.452429 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8400 22:59:13.458918 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8401 22:59:13.461960 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8402 22:59:13.465201 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8403 22:59:13.472259 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8404 22:59:13.475331 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8405 22:59:13.479045 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8406 22:59:13.485141 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8407 22:59:13.488794 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8408 22:59:13.491933 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8409 22:59:13.495656 Total UI for P1: 0, mck2ui 16
8410 22:59:13.498594 best dqsien dly found for B0: ( 1, 9, 14)
8411 22:59:13.502272 Total UI for P1: 0, mck2ui 16
8412 22:59:13.505299 best dqsien dly found for B1: ( 1, 9, 16)
8413 22:59:13.508762 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8414 22:59:13.511799 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8415 22:59:13.511925
8416 22:59:13.514933 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8417 22:59:13.521639 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8418 22:59:13.521794 [Gating] SW calibration Done
8419 22:59:13.521897 ==
8420 22:59:13.525281 Dram Type= 6, Freq= 0, CH_1, rank 0
8421 22:59:13.532016 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8422 22:59:13.532179 ==
8423 22:59:13.532300 RX Vref Scan: 0
8424 22:59:13.532418
8425 22:59:13.534905 RX Vref 0 -> 0, step: 1
8426 22:59:13.535030
8427 22:59:13.538603 RX Delay 0 -> 252, step: 8
8428 22:59:13.541652 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8429 22:59:13.544912 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8430 22:59:13.548568 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8431 22:59:13.554993 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8432 22:59:13.558078 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8433 22:59:13.561214 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8434 22:59:13.565017 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
8435 22:59:13.568231 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8436 22:59:13.571473 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8437 22:59:13.578321 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
8438 22:59:13.581806 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8439 22:59:13.584441 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8440 22:59:13.587973 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8441 22:59:13.594873 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8442 22:59:13.597833 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8443 22:59:13.601529 iDelay=200, Bit 15, Center 131 (80 ~ 183) 104
8444 22:59:13.601649 ==
8445 22:59:13.604702 Dram Type= 6, Freq= 0, CH_1, rank 0
8446 22:59:13.608233 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8447 22:59:13.608326 ==
8448 22:59:13.611541 DQS Delay:
8449 22:59:13.611629 DQS0 = 0, DQS1 = 0
8450 22:59:13.614696 DQM Delay:
8451 22:59:13.614777 DQM0 = 134, DQM1 = 127
8452 22:59:13.614862 DQ Delay:
8453 22:59:13.617758 DQ0 =139, DQ1 =127, DQ2 =123, DQ3 =135
8454 22:59:13.621497 DQ4 =135, DQ5 =143, DQ6 =143, DQ7 =127
8455 22:59:13.627924 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =123
8456 22:59:13.631592 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =131
8457 22:59:13.631700
8458 22:59:13.631772
8459 22:59:13.631838 ==
8460 22:59:13.634618 Dram Type= 6, Freq= 0, CH_1, rank 0
8461 22:59:13.637755 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8462 22:59:13.637914 ==
8463 22:59:13.638010
8464 22:59:13.638107
8465 22:59:13.641291 TX Vref Scan disable
8466 22:59:13.644330 == TX Byte 0 ==
8467 22:59:13.648236 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8468 22:59:13.651319 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8469 22:59:13.654585 == TX Byte 1 ==
8470 22:59:13.657658 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8471 22:59:13.661431 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8472 22:59:13.661538 ==
8473 22:59:13.664456 Dram Type= 6, Freq= 0, CH_1, rank 0
8474 22:59:13.668293 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8475 22:59:13.668392 ==
8476 22:59:13.682384
8477 22:59:13.685512 TX Vref early break, caculate TX vref
8478 22:59:13.688801 TX Vref=16, minBit 8, minWin=21, winSum=367
8479 22:59:13.692254 TX Vref=18, minBit 5, minWin=22, winSum=377
8480 22:59:13.695255 TX Vref=20, minBit 8, minWin=23, winSum=390
8481 22:59:13.698888 TX Vref=22, minBit 8, minWin=23, winSum=399
8482 22:59:13.701930 TX Vref=24, minBit 8, minWin=23, winSum=407
8483 22:59:13.708774 TX Vref=26, minBit 5, minWin=25, winSum=418
8484 22:59:13.712311 TX Vref=28, minBit 11, minWin=25, winSum=425
8485 22:59:13.715194 TX Vref=30, minBit 1, minWin=25, winSum=422
8486 22:59:13.718916 TX Vref=32, minBit 11, minWin=24, winSum=413
8487 22:59:13.722136 TX Vref=34, minBit 11, minWin=23, winSum=396
8488 22:59:13.728720 [TxChooseVref] Worse bit 11, Min win 25, Win sum 425, Final Vref 28
8489 22:59:13.728844
8490 22:59:13.732289 Final TX Range 0 Vref 28
8491 22:59:13.732386
8492 22:59:13.732455 ==
8493 22:59:13.735366 Dram Type= 6, Freq= 0, CH_1, rank 0
8494 22:59:13.739062 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8495 22:59:13.739160 ==
8496 22:59:13.739230
8497 22:59:13.739293
8498 22:59:13.742108 TX Vref Scan disable
8499 22:59:13.748846 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8500 22:59:13.748962 == TX Byte 0 ==
8501 22:59:13.752050 u2DelayCellOfst[0]=17 cells (5 PI)
8502 22:59:13.755369 u2DelayCellOfst[1]=10 cells (3 PI)
8503 22:59:13.758448 u2DelayCellOfst[2]=0 cells (0 PI)
8504 22:59:13.762219 u2DelayCellOfst[3]=7 cells (2 PI)
8505 22:59:13.765499 u2DelayCellOfst[4]=7 cells (2 PI)
8506 22:59:13.768622 u2DelayCellOfst[5]=17 cells (5 PI)
8507 22:59:13.771698 u2DelayCellOfst[6]=17 cells (5 PI)
8508 22:59:13.774917 u2DelayCellOfst[7]=3 cells (1 PI)
8509 22:59:13.778665 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8510 22:59:13.781842 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8511 22:59:13.785090 == TX Byte 1 ==
8512 22:59:13.785186 u2DelayCellOfst[8]=0 cells (0 PI)
8513 22:59:13.788741 u2DelayCellOfst[9]=7 cells (2 PI)
8514 22:59:13.792088 u2DelayCellOfst[10]=14 cells (4 PI)
8515 22:59:13.795554 u2DelayCellOfst[11]=7 cells (2 PI)
8516 22:59:13.798461 u2DelayCellOfst[12]=17 cells (5 PI)
8517 22:59:13.802062 u2DelayCellOfst[13]=17 cells (5 PI)
8518 22:59:13.805111 u2DelayCellOfst[14]=21 cells (6 PI)
8519 22:59:13.808218 u2DelayCellOfst[15]=21 cells (6 PI)
8520 22:59:13.811378 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8521 22:59:13.818486 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8522 22:59:13.818617 DramC Write-DBI on
8523 22:59:13.818695 ==
8524 22:59:13.821545 Dram Type= 6, Freq= 0, CH_1, rank 0
8525 22:59:13.828483 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8526 22:59:13.828616 ==
8527 22:59:13.828691
8528 22:59:13.828757
8529 22:59:13.828865 TX Vref Scan disable
8530 22:59:13.832163 == TX Byte 0 ==
8531 22:59:13.835178 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8532 22:59:13.838243 == TX Byte 1 ==
8533 22:59:13.841838 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8534 22:59:13.845012 DramC Write-DBI off
8535 22:59:13.845106
8536 22:59:13.845206 [DATLAT]
8537 22:59:13.845272 Freq=1600, CH1 RK0
8538 22:59:13.845363
8539 22:59:13.848709 DATLAT Default: 0xf
8540 22:59:13.848797 0, 0xFFFF, sum = 0
8541 22:59:13.851738 1, 0xFFFF, sum = 0
8542 22:59:13.855625 2, 0xFFFF, sum = 0
8543 22:59:13.855757 3, 0xFFFF, sum = 0
8544 22:59:13.859204 4, 0xFFFF, sum = 0
8545 22:59:13.859327 5, 0xFFFF, sum = 0
8546 22:59:13.861646 6, 0xFFFF, sum = 0
8547 22:59:13.861739 7, 0xFFFF, sum = 0
8548 22:59:13.864777 8, 0xFFFF, sum = 0
8549 22:59:13.864883 9, 0xFFFF, sum = 0
8550 22:59:13.868738 10, 0xFFFF, sum = 0
8551 22:59:13.868835 11, 0xFFFF, sum = 0
8552 22:59:13.871763 12, 0xFFFF, sum = 0
8553 22:59:13.871860 13, 0xFFFF, sum = 0
8554 22:59:13.874975 14, 0x0, sum = 1
8555 22:59:13.875068 15, 0x0, sum = 2
8556 22:59:13.878068 16, 0x0, sum = 3
8557 22:59:13.878161 17, 0x0, sum = 4
8558 22:59:13.881366 best_step = 15
8559 22:59:13.881458
8560 22:59:13.881547 ==
8561 22:59:13.884991 Dram Type= 6, Freq= 0, CH_1, rank 0
8562 22:59:13.888404 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8563 22:59:13.888500 ==
8564 22:59:13.891334 RX Vref Scan: 1
8565 22:59:13.891441
8566 22:59:13.891530 Set Vref Range= 24 -> 127
8567 22:59:13.891612
8568 22:59:13.895032 RX Vref 24 -> 127, step: 1
8569 22:59:13.895142
8570 22:59:13.898179 RX Delay 19 -> 252, step: 4
8571 22:59:13.898273
8572 22:59:13.901827 Set Vref, RX VrefLevel [Byte0]: 24
8573 22:59:13.904837 [Byte1]: 24
8574 22:59:13.904933
8575 22:59:13.908378 Set Vref, RX VrefLevel [Byte0]: 25
8576 22:59:13.911520 [Byte1]: 25
8577 22:59:13.911616
8578 22:59:13.914625 Set Vref, RX VrefLevel [Byte0]: 26
8579 22:59:13.918175 [Byte1]: 26
8580 22:59:13.922332
8581 22:59:13.922455 Set Vref, RX VrefLevel [Byte0]: 27
8582 22:59:13.925293 [Byte1]: 27
8583 22:59:13.929587
8584 22:59:13.929722 Set Vref, RX VrefLevel [Byte0]: 28
8585 22:59:13.932792 [Byte1]: 28
8586 22:59:13.937466
8587 22:59:13.937595 Set Vref, RX VrefLevel [Byte0]: 29
8588 22:59:13.940563 [Byte1]: 29
8589 22:59:13.944848
8590 22:59:13.944970 Set Vref, RX VrefLevel [Byte0]: 30
8591 22:59:13.948042 [Byte1]: 30
8592 22:59:13.952251
8593 22:59:13.952398 Set Vref, RX VrefLevel [Byte0]: 31
8594 22:59:13.955812 [Byte1]: 31
8595 22:59:13.960163
8596 22:59:13.960304 Set Vref, RX VrefLevel [Byte0]: 32
8597 22:59:13.963384 [Byte1]: 32
8598 22:59:13.967264
8599 22:59:13.967418 Set Vref, RX VrefLevel [Byte0]: 33
8600 22:59:13.970955 [Byte1]: 33
8601 22:59:13.975343
8602 22:59:13.975480 Set Vref, RX VrefLevel [Byte0]: 34
8603 22:59:13.978455 [Byte1]: 34
8604 22:59:13.982774
8605 22:59:13.982901 Set Vref, RX VrefLevel [Byte0]: 35
8606 22:59:13.985927 [Byte1]: 35
8607 22:59:13.990389
8608 22:59:13.990532 Set Vref, RX VrefLevel [Byte0]: 36
8609 22:59:13.993596 [Byte1]: 36
8610 22:59:13.997841
8611 22:59:13.997974 Set Vref, RX VrefLevel [Byte0]: 37
8612 22:59:14.001214 [Byte1]: 37
8613 22:59:14.005135
8614 22:59:14.005254 Set Vref, RX VrefLevel [Byte0]: 38
8615 22:59:14.008840 [Byte1]: 38
8616 22:59:14.013187
8617 22:59:14.013311 Set Vref, RX VrefLevel [Byte0]: 39
8618 22:59:14.016473 [Byte1]: 39
8619 22:59:14.020644
8620 22:59:14.020760 Set Vref, RX VrefLevel [Byte0]: 40
8621 22:59:14.023653 [Byte1]: 40
8622 22:59:14.028386
8623 22:59:14.028526 Set Vref, RX VrefLevel [Byte0]: 41
8624 22:59:14.031465 [Byte1]: 41
8625 22:59:14.035652
8626 22:59:14.035751 Set Vref, RX VrefLevel [Byte0]: 42
8627 22:59:14.039306 [Byte1]: 42
8628 22:59:14.043535
8629 22:59:14.043634 Set Vref, RX VrefLevel [Byte0]: 43
8630 22:59:14.046607 [Byte1]: 43
8631 22:59:14.050871
8632 22:59:14.050998 Set Vref, RX VrefLevel [Byte0]: 44
8633 22:59:14.054064 [Byte1]: 44
8634 22:59:14.058212
8635 22:59:14.058316 Set Vref, RX VrefLevel [Byte0]: 45
8636 22:59:14.061804 [Byte1]: 45
8637 22:59:14.066278
8638 22:59:14.066432 Set Vref, RX VrefLevel [Byte0]: 46
8639 22:59:14.069367 [Byte1]: 46
8640 22:59:14.073715
8641 22:59:14.073841 Set Vref, RX VrefLevel [Byte0]: 47
8642 22:59:14.076830 [Byte1]: 47
8643 22:59:14.081337
8644 22:59:14.081457 Set Vref, RX VrefLevel [Byte0]: 48
8645 22:59:14.084403 [Byte1]: 48
8646 22:59:14.088831
8647 22:59:14.088952 Set Vref, RX VrefLevel [Byte0]: 49
8648 22:59:14.092120 [Byte1]: 49
8649 22:59:14.096400
8650 22:59:14.096532 Set Vref, RX VrefLevel [Byte0]: 50
8651 22:59:14.099561 [Byte1]: 50
8652 22:59:14.104055
8653 22:59:14.104193 Set Vref, RX VrefLevel [Byte0]: 51
8654 22:59:14.107051 [Byte1]: 51
8655 22:59:14.111420
8656 22:59:14.111539 Set Vref, RX VrefLevel [Byte0]: 52
8657 22:59:14.114854 [Byte1]: 52
8658 22:59:14.118691
8659 22:59:14.118820 Set Vref, RX VrefLevel [Byte0]: 53
8660 22:59:14.122510 [Byte1]: 53
8661 22:59:14.126767
8662 22:59:14.126892 Set Vref, RX VrefLevel [Byte0]: 54
8663 22:59:14.129759 [Byte1]: 54
8664 22:59:14.134444
8665 22:59:14.134568 Set Vref, RX VrefLevel [Byte0]: 55
8666 22:59:14.137501 [Byte1]: 55
8667 22:59:14.141787
8668 22:59:14.141914 Set Vref, RX VrefLevel [Byte0]: 56
8669 22:59:14.145011 [Byte1]: 56
8670 22:59:14.149022
8671 22:59:14.149150 Set Vref, RX VrefLevel [Byte0]: 57
8672 22:59:14.152633 [Byte1]: 57
8673 22:59:14.156919
8674 22:59:14.157047 Set Vref, RX VrefLevel [Byte0]: 58
8675 22:59:14.163149 [Byte1]: 58
8676 22:59:14.163296
8677 22:59:14.166719 Set Vref, RX VrefLevel [Byte0]: 59
8678 22:59:14.169882 [Byte1]: 59
8679 22:59:14.170017
8680 22:59:14.173594 Set Vref, RX VrefLevel [Byte0]: 60
8681 22:59:14.176675 [Byte1]: 60
8682 22:59:14.176795
8683 22:59:14.179727 Set Vref, RX VrefLevel [Byte0]: 61
8684 22:59:14.183097 [Byte1]: 61
8685 22:59:14.186886
8686 22:59:14.187005 Set Vref, RX VrefLevel [Byte0]: 62
8687 22:59:14.190728 [Byte1]: 62
8688 22:59:14.194588
8689 22:59:14.194715 Set Vref, RX VrefLevel [Byte0]: 63
8690 22:59:14.198183 [Byte1]: 63
8691 22:59:14.202046
8692 22:59:14.202172 Set Vref, RX VrefLevel [Byte0]: 64
8693 22:59:14.205732 [Byte1]: 64
8694 22:59:14.210166
8695 22:59:14.210289 Set Vref, RX VrefLevel [Byte0]: 65
8696 22:59:14.213186 [Byte1]: 65
8697 22:59:14.217504
8698 22:59:14.217621 Set Vref, RX VrefLevel [Byte0]: 66
8699 22:59:14.221123 [Byte1]: 66
8700 22:59:14.224723
8701 22:59:14.224837 Set Vref, RX VrefLevel [Byte0]: 67
8702 22:59:14.228400 [Byte1]: 67
8703 22:59:14.232640
8704 22:59:14.232759 Set Vref, RX VrefLevel [Byte0]: 68
8705 22:59:14.235766 [Byte1]: 68
8706 22:59:14.239938
8707 22:59:14.240056 Set Vref, RX VrefLevel [Byte0]: 69
8708 22:59:14.243580 [Byte1]: 69
8709 22:59:14.247968
8710 22:59:14.248094 Set Vref, RX VrefLevel [Byte0]: 70
8711 22:59:14.251141 [Byte1]: 70
8712 22:59:14.255208
8713 22:59:14.255345 Set Vref, RX VrefLevel [Byte0]: 71
8714 22:59:14.258347 [Byte1]: 71
8715 22:59:14.262665
8716 22:59:14.262809 Set Vref, RX VrefLevel [Byte0]: 72
8717 22:59:14.266036 [Byte1]: 72
8718 22:59:14.270365
8719 22:59:14.270504 Set Vref, RX VrefLevel [Byte0]: 73
8720 22:59:14.274174 [Byte1]: 73
8721 22:59:14.277854
8722 22:59:14.277979 Final RX Vref Byte 0 = 59 to rank0
8723 22:59:14.281000 Final RX Vref Byte 1 = 58 to rank0
8724 22:59:14.284839 Final RX Vref Byte 0 = 59 to rank1
8725 22:59:14.287983 Final RX Vref Byte 1 = 58 to rank1==
8726 22:59:14.291163 Dram Type= 6, Freq= 0, CH_1, rank 0
8727 22:59:14.297630 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8728 22:59:14.297781 ==
8729 22:59:14.297887 DQS Delay:
8730 22:59:14.301347 DQS0 = 0, DQS1 = 0
8731 22:59:14.301461 DQM Delay:
8732 22:59:14.301560 DQM0 = 131, DQM1 = 124
8733 22:59:14.304662 DQ Delay:
8734 22:59:14.307682 DQ0 =134, DQ1 =124, DQ2 =120, DQ3 =130
8735 22:59:14.311449 DQ4 =130, DQ5 =142, DQ6 =144, DQ7 =128
8736 22:59:14.314665 DQ8 =110, DQ9 =114, DQ10 =126, DQ11 =118
8737 22:59:14.317711 DQ12 =132, DQ13 =132, DQ14 =130, DQ15 =132
8738 22:59:14.317831
8739 22:59:14.317932
8740 22:59:14.318026
8741 22:59:14.321302 [DramC_TX_OE_Calibration] TA2
8742 22:59:14.324376 Original DQ_B0 (3 6) =30, OEN = 27
8743 22:59:14.327447 Original DQ_B1 (3 6) =30, OEN = 27
8744 22:59:14.331174 24, 0x0, End_B0=24 End_B1=24
8745 22:59:14.331297 25, 0x0, End_B0=25 End_B1=25
8746 22:59:14.334313 26, 0x0, End_B0=26 End_B1=26
8747 22:59:14.337882 27, 0x0, End_B0=27 End_B1=27
8748 22:59:14.340934 28, 0x0, End_B0=28 End_B1=28
8749 22:59:14.344568 29, 0x0, End_B0=29 End_B1=29
8750 22:59:14.344695 30, 0x0, End_B0=30 End_B1=30
8751 22:59:14.347579 31, 0x5151, End_B0=30 End_B1=30
8752 22:59:14.350562 Byte0 end_step=30 best_step=27
8753 22:59:14.354378 Byte1 end_step=30 best_step=27
8754 22:59:14.357434 Byte0 TX OE(2T, 0.5T) = (3, 3)
8755 22:59:14.360567 Byte1 TX OE(2T, 0.5T) = (3, 3)
8756 22:59:14.360682
8757 22:59:14.360780
8758 22:59:14.367107 [DQSOSCAuto] RK0, (LSB)MR18= 0x1701, (MSB)MR19= 0x303, tDQSOscB0 = 409 ps tDQSOscB1 = 398 ps
8759 22:59:14.370848 CH1 RK0: MR19=303, MR18=1701
8760 22:59:14.377606 CH1_RK0: MR19=0x303, MR18=0x1701, DQSOSC=398, MR23=63, INC=23, DEC=15
8761 22:59:14.377780
8762 22:59:14.380718 ----->DramcWriteLeveling(PI) begin...
8763 22:59:14.380846 ==
8764 22:59:14.383947 Dram Type= 6, Freq= 0, CH_1, rank 1
8765 22:59:14.387040 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8766 22:59:14.387168 ==
8767 22:59:14.390779 Write leveling (Byte 0): 26 => 26
8768 22:59:14.393960 Write leveling (Byte 1): 27 => 27
8769 22:59:14.397226 DramcWriteLeveling(PI) end<-----
8770 22:59:14.397349
8771 22:59:14.397455 ==
8772 22:59:14.400366 Dram Type= 6, Freq= 0, CH_1, rank 1
8773 22:59:14.404038 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8774 22:59:14.404156 ==
8775 22:59:14.407097 [Gating] SW mode calibration
8776 22:59:14.413903 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8777 22:59:14.420372 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8778 22:59:14.424055 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8779 22:59:14.430691 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8780 22:59:14.433726 1 4 8 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
8781 22:59:14.437270 1 4 12 | B1->B0 | 2828 3434 | 1 1 | (1 1) (1 1)
8782 22:59:14.444031 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8783 22:59:14.446959 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8784 22:59:14.450118 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8785 22:59:14.453375 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8786 22:59:14.460125 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8787 22:59:14.463695 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8788 22:59:14.467361 1 5 8 | B1->B0 | 3434 2d2d | 1 1 | (1 0) (1 0)
8789 22:59:14.473996 1 5 12 | B1->B0 | 2d2d 2323 | 1 0 | (1 0) (0 0)
8790 22:59:14.477055 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8791 22:59:14.480195 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8792 22:59:14.487109 1 5 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8793 22:59:14.490151 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8794 22:59:14.493335 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8795 22:59:14.500286 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8796 22:59:14.503545 1 6 8 | B1->B0 | 2323 3e3e | 0 0 | (0 0) (0 0)
8797 22:59:14.507338 1 6 12 | B1->B0 | 3737 4444 | 0 0 | (0 0) (0 0)
8798 22:59:14.513532 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8799 22:59:14.516649 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8800 22:59:14.520335 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8801 22:59:14.526617 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8802 22:59:14.530314 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8803 22:59:14.533180 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8804 22:59:14.540054 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8805 22:59:14.543666 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8806 22:59:14.546584 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8807 22:59:14.553437 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8808 22:59:14.556655 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8809 22:59:14.559720 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8810 22:59:14.566408 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8811 22:59:14.569960 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8812 22:59:14.573025 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8813 22:59:14.580031 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8814 22:59:14.583154 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8815 22:59:14.586795 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8816 22:59:14.589949 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8817 22:59:14.596327 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8818 22:59:14.599527 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8819 22:59:14.602830 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8820 22:59:14.609751 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8821 22:59:14.612889 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8822 22:59:14.616592 Total UI for P1: 0, mck2ui 16
8823 22:59:14.619888 best dqsien dly found for B0: ( 1, 9, 6)
8824 22:59:14.623124 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8825 22:59:14.629508 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8826 22:59:14.633182 Total UI for P1: 0, mck2ui 16
8827 22:59:14.636090 best dqsien dly found for B1: ( 1, 9, 14)
8828 22:59:14.639846 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8829 22:59:14.642920 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8830 22:59:14.643009
8831 22:59:14.645916 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8832 22:59:14.649533 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8833 22:59:14.652607 [Gating] SW calibration Done
8834 22:59:14.652700 ==
8835 22:59:14.656316 Dram Type= 6, Freq= 0, CH_1, rank 1
8836 22:59:14.659325 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8837 22:59:14.659430 ==
8838 22:59:14.663141 RX Vref Scan: 0
8839 22:59:14.663288
8840 22:59:14.663409 RX Vref 0 -> 0, step: 1
8841 22:59:14.666272
8842 22:59:14.666392 RX Delay 0 -> 252, step: 8
8843 22:59:14.672701 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8844 22:59:14.675812 iDelay=200, Bit 1, Center 123 (64 ~ 183) 120
8845 22:59:14.679374 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8846 22:59:14.682701 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8847 22:59:14.686323 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8848 22:59:14.689347 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8849 22:59:14.695681 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8850 22:59:14.698880 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8851 22:59:14.702705 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8852 22:59:14.705778 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8853 22:59:14.712213 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8854 22:59:14.715575 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8855 22:59:14.719330 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8856 22:59:14.722370 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8857 22:59:14.725759 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
8858 22:59:14.732065 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8859 22:59:14.732173 ==
8860 22:59:14.735646 Dram Type= 6, Freq= 0, CH_1, rank 1
8861 22:59:14.739272 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8862 22:59:14.739391 ==
8863 22:59:14.739459 DQS Delay:
8864 22:59:14.742222 DQS0 = 0, DQS1 = 0
8865 22:59:14.742323 DQM Delay:
8866 22:59:14.745435 DQM0 = 131, DQM1 = 129
8867 22:59:14.745544 DQ Delay:
8868 22:59:14.749081 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =131
8869 22:59:14.752119 DQ4 =131, DQ5 =147, DQ6 =139, DQ7 =127
8870 22:59:14.755199 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =123
8871 22:59:14.758803 DQ12 =135, DQ13 =135, DQ14 =139, DQ15 =135
8872 22:59:14.758903
8873 22:59:14.758973
8874 22:59:14.762401 ==
8875 22:59:14.765413 Dram Type= 6, Freq= 0, CH_1, rank 1
8876 22:59:14.769182 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8877 22:59:14.769288 ==
8878 22:59:14.769360
8879 22:59:14.769424
8880 22:59:14.771890 TX Vref Scan disable
8881 22:59:14.771968 == TX Byte 0 ==
8882 22:59:14.775122 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8883 22:59:14.782429 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8884 22:59:14.782574 == TX Byte 1 ==
8885 22:59:14.785399 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8886 22:59:14.792097 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8887 22:59:14.792215 ==
8888 22:59:14.795337 Dram Type= 6, Freq= 0, CH_1, rank 1
8889 22:59:14.798525 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8890 22:59:14.798627 ==
8891 22:59:14.812619
8892 22:59:14.816368 TX Vref early break, caculate TX vref
8893 22:59:14.819546 TX Vref=16, minBit 8, minWin=22, winSum=379
8894 22:59:14.822546 TX Vref=18, minBit 0, minWin=23, winSum=386
8895 22:59:14.825772 TX Vref=20, minBit 8, minWin=23, winSum=397
8896 22:59:14.829657 TX Vref=22, minBit 11, minWin=23, winSum=401
8897 22:59:14.832746 TX Vref=24, minBit 15, minWin=24, winSum=411
8898 22:59:14.839080 TX Vref=26, minBit 11, minWin=25, winSum=420
8899 22:59:14.842674 TX Vref=28, minBit 11, minWin=25, winSum=422
8900 22:59:14.845707 TX Vref=30, minBit 0, minWin=25, winSum=418
8901 22:59:14.849421 TX Vref=32, minBit 0, minWin=25, winSum=414
8902 22:59:14.852697 TX Vref=34, minBit 0, minWin=24, winSum=402
8903 22:59:14.859112 TX Vref=36, minBit 0, minWin=24, winSum=396
8904 22:59:14.862755 [TxChooseVref] Worse bit 11, Min win 25, Win sum 422, Final Vref 28
8905 22:59:14.862891
8906 22:59:14.865833 Final TX Range 0 Vref 28
8907 22:59:14.865957
8908 22:59:14.866055 ==
8909 22:59:14.869567 Dram Type= 6, Freq= 0, CH_1, rank 1
8910 22:59:14.872473 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8911 22:59:14.875609 ==
8912 22:59:14.875709
8913 22:59:14.875813
8914 22:59:14.875908 TX Vref Scan disable
8915 22:59:14.882261 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8916 22:59:14.882402 == TX Byte 0 ==
8917 22:59:14.885854 u2DelayCellOfst[0]=14 cells (4 PI)
8918 22:59:14.889442 u2DelayCellOfst[1]=10 cells (3 PI)
8919 22:59:14.892515 u2DelayCellOfst[2]=0 cells (0 PI)
8920 22:59:14.895623 u2DelayCellOfst[3]=7 cells (2 PI)
8921 22:59:14.899375 u2DelayCellOfst[4]=10 cells (3 PI)
8922 22:59:14.902569 u2DelayCellOfst[5]=17 cells (5 PI)
8923 22:59:14.905746 u2DelayCellOfst[6]=17 cells (5 PI)
8924 22:59:14.908959 u2DelayCellOfst[7]=7 cells (2 PI)
8925 22:59:14.912104 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8926 22:59:14.915756 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8927 22:59:14.918837 == TX Byte 1 ==
8928 22:59:14.922111 u2DelayCellOfst[8]=0 cells (0 PI)
8929 22:59:14.925250 u2DelayCellOfst[9]=3 cells (1 PI)
8930 22:59:14.928801 u2DelayCellOfst[10]=10 cells (3 PI)
8931 22:59:14.931954 u2DelayCellOfst[11]=7 cells (2 PI)
8932 22:59:14.935217 u2DelayCellOfst[12]=14 cells (4 PI)
8933 22:59:14.935331 u2DelayCellOfst[13]=17 cells (5 PI)
8934 22:59:14.938929 u2DelayCellOfst[14]=17 cells (5 PI)
8935 22:59:14.942183 u2DelayCellOfst[15]=17 cells (5 PI)
8936 22:59:14.948877 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8937 22:59:14.951957 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8938 22:59:14.952066 DramC Write-DBI on
8939 22:59:14.955731 ==
8940 22:59:14.955828 Dram Type= 6, Freq= 0, CH_1, rank 1
8941 22:59:14.962275 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8942 22:59:14.962393 ==
8943 22:59:14.962466
8944 22:59:14.962530
8945 22:59:14.965202 TX Vref Scan disable
8946 22:59:14.965288 == TX Byte 0 ==
8947 22:59:14.972230 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8948 22:59:14.972351 == TX Byte 1 ==
8949 22:59:14.975052 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8950 22:59:14.978711 DramC Write-DBI off
8951 22:59:14.978845
8952 22:59:14.978964 [DATLAT]
8953 22:59:14.981737 Freq=1600, CH1 RK1
8954 22:59:14.981860
8955 22:59:14.981961 DATLAT Default: 0xf
8956 22:59:14.985275 0, 0xFFFF, sum = 0
8957 22:59:14.985391 1, 0xFFFF, sum = 0
8958 22:59:14.988284 2, 0xFFFF, sum = 0
8959 22:59:14.988419 3, 0xFFFF, sum = 0
8960 22:59:14.991873 4, 0xFFFF, sum = 0
8961 22:59:14.991992 5, 0xFFFF, sum = 0
8962 22:59:14.995049 6, 0xFFFF, sum = 0
8963 22:59:14.995169 7, 0xFFFF, sum = 0
8964 22:59:14.997994 8, 0xFFFF, sum = 0
8965 22:59:15.001689 9, 0xFFFF, sum = 0
8966 22:59:15.001812 10, 0xFFFF, sum = 0
8967 22:59:15.004995 11, 0xFFFF, sum = 0
8968 22:59:15.005114 12, 0xFFFF, sum = 0
8969 22:59:15.008033 13, 0xFFFF, sum = 0
8970 22:59:15.008144 14, 0x0, sum = 1
8971 22:59:15.011298 15, 0x0, sum = 2
8972 22:59:15.011408 16, 0x0, sum = 3
8973 22:59:15.015028 17, 0x0, sum = 4
8974 22:59:15.015138 best_step = 15
8975 22:59:15.015237
8976 22:59:15.015330 ==
8977 22:59:15.018264 Dram Type= 6, Freq= 0, CH_1, rank 1
8978 22:59:15.021472 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8979 22:59:15.021588 ==
8980 22:59:15.025082 RX Vref Scan: 0
8981 22:59:15.025167
8982 22:59:15.028299 RX Vref 0 -> 0, step: 1
8983 22:59:15.028417
8984 22:59:15.028515 RX Delay 11 -> 252, step: 4
8985 22:59:15.035283 iDelay=195, Bit 0, Center 132 (83 ~ 182) 100
8986 22:59:15.038602 iDelay=195, Bit 1, Center 124 (71 ~ 178) 108
8987 22:59:15.041710 iDelay=195, Bit 2, Center 118 (67 ~ 170) 104
8988 22:59:15.045427 iDelay=195, Bit 3, Center 126 (75 ~ 178) 104
8989 22:59:15.048501 iDelay=195, Bit 4, Center 130 (79 ~ 182) 104
8990 22:59:15.055323 iDelay=195, Bit 5, Center 144 (95 ~ 194) 100
8991 22:59:15.058432 iDelay=195, Bit 6, Center 138 (87 ~ 190) 104
8992 22:59:15.062162 iDelay=195, Bit 7, Center 126 (75 ~ 178) 104
8993 22:59:15.065102 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
8994 22:59:15.068754 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8995 22:59:15.075485 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8996 22:59:15.078576 iDelay=195, Bit 11, Center 118 (63 ~ 174) 112
8997 22:59:15.081577 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
8998 22:59:15.084740 iDelay=195, Bit 13, Center 134 (83 ~ 186) 104
8999 22:59:15.091527 iDelay=195, Bit 14, Center 134 (79 ~ 190) 112
9000 22:59:15.095029 iDelay=195, Bit 15, Center 136 (83 ~ 190) 108
9001 22:59:15.095185 ==
9002 22:59:15.098127 Dram Type= 6, Freq= 0, CH_1, rank 1
9003 22:59:15.101109 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9004 22:59:15.101202 ==
9005 22:59:15.104854 DQS Delay:
9006 22:59:15.104947 DQS0 = 0, DQS1 = 0
9007 22:59:15.105035 DQM Delay:
9008 22:59:15.107893 DQM0 = 129, DQM1 = 126
9009 22:59:15.107997 DQ Delay:
9010 22:59:15.111102 DQ0 =132, DQ1 =124, DQ2 =118, DQ3 =126
9011 22:59:15.114859 DQ4 =130, DQ5 =144, DQ6 =138, DQ7 =126
9012 22:59:15.118072 DQ8 =114, DQ9 =112, DQ10 =128, DQ11 =118
9013 22:59:15.124444 DQ12 =132, DQ13 =134, DQ14 =134, DQ15 =136
9014 22:59:15.124555
9015 22:59:15.124644
9016 22:59:15.124710
9017 22:59:15.128303 [DramC_TX_OE_Calibration] TA2
9018 22:59:15.131320 Original DQ_B0 (3 6) =30, OEN = 27
9019 22:59:15.131457 Original DQ_B1 (3 6) =30, OEN = 27
9020 22:59:15.134650 24, 0x0, End_B0=24 End_B1=24
9021 22:59:15.137665 25, 0x0, End_B0=25 End_B1=25
9022 22:59:15.141022 26, 0x0, End_B0=26 End_B1=26
9023 22:59:15.144663 27, 0x0, End_B0=27 End_B1=27
9024 22:59:15.144815 28, 0x0, End_B0=28 End_B1=28
9025 22:59:15.147904 29, 0x0, End_B0=29 End_B1=29
9026 22:59:15.151004 30, 0x0, End_B0=30 End_B1=30
9027 22:59:15.154564 31, 0x4141, End_B0=30 End_B1=30
9028 22:59:15.157679 Byte0 end_step=30 best_step=27
9029 22:59:15.157822 Byte1 end_step=30 best_step=27
9030 22:59:15.161330 Byte0 TX OE(2T, 0.5T) = (3, 3)
9031 22:59:15.164425 Byte1 TX OE(2T, 0.5T) = (3, 3)
9032 22:59:15.164538
9033 22:59:15.164611
9034 22:59:15.174638 [DQSOSCAuto] RK1, (LSB)MR18= 0x1218, (MSB)MR19= 0x303, tDQSOscB0 = 397 ps tDQSOscB1 = 400 ps
9035 22:59:15.174823 CH1 RK1: MR19=303, MR18=1218
9036 22:59:15.180874 CH1_RK1: MR19=0x303, MR18=0x1218, DQSOSC=397, MR23=63, INC=23, DEC=15
9037 22:59:15.184450 [RxdqsGatingPostProcess] freq 1600
9038 22:59:15.191248 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9039 22:59:15.194310 best DQS0 dly(2T, 0.5T) = (1, 1)
9040 22:59:15.197875 best DQS1 dly(2T, 0.5T) = (1, 1)
9041 22:59:15.201073 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9042 22:59:15.204686 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9043 22:59:15.204787 best DQS0 dly(2T, 0.5T) = (1, 1)
9044 22:59:15.207919 best DQS1 dly(2T, 0.5T) = (1, 1)
9045 22:59:15.210881 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9046 22:59:15.214064 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9047 22:59:15.217750 Pre-setting of DQS Precalculation
9048 22:59:15.224141 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9049 22:59:15.230947 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9050 22:59:15.237929 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9051 22:59:15.238059
9052 22:59:15.238134
9053 22:59:15.241212 [Calibration Summary] 3200 Mbps
9054 22:59:15.241305 CH 0, Rank 0
9055 22:59:15.244333 SW Impedance : PASS
9056 22:59:15.247568 DUTY Scan : NO K
9057 22:59:15.247664 ZQ Calibration : PASS
9058 22:59:15.250761 Jitter Meter : NO K
9059 22:59:15.254024 CBT Training : PASS
9060 22:59:15.254177 Write leveling : PASS
9061 22:59:15.257597 RX DQS gating : PASS
9062 22:59:15.260687 RX DQ/DQS(RDDQC) : PASS
9063 22:59:15.260824 TX DQ/DQS : PASS
9064 22:59:15.264350 RX DATLAT : PASS
9065 22:59:15.264506 RX DQ/DQS(Engine): PASS
9066 22:59:15.267541 TX OE : PASS
9067 22:59:15.267666 All Pass.
9068 22:59:15.267769
9069 22:59:15.270584 CH 0, Rank 1
9070 22:59:15.270716 SW Impedance : PASS
9071 22:59:15.274197 DUTY Scan : NO K
9072 22:59:15.277382 ZQ Calibration : PASS
9073 22:59:15.277504 Jitter Meter : NO K
9074 22:59:15.280955 CBT Training : PASS
9075 22:59:15.284079 Write leveling : PASS
9076 22:59:15.284194 RX DQS gating : PASS
9077 22:59:15.287193 RX DQ/DQS(RDDQC) : PASS
9078 22:59:15.290817 TX DQ/DQS : PASS
9079 22:59:15.290939 RX DATLAT : PASS
9080 22:59:15.293981 RX DQ/DQS(Engine): PASS
9081 22:59:15.297672 TX OE : PASS
9082 22:59:15.297796 All Pass.
9083 22:59:15.297901
9084 22:59:15.297997 CH 1, Rank 0
9085 22:59:15.300512 SW Impedance : PASS
9086 22:59:15.304302 DUTY Scan : NO K
9087 22:59:15.304439 ZQ Calibration : PASS
9088 22:59:15.307201 Jitter Meter : NO K
9089 22:59:15.310844 CBT Training : PASS
9090 22:59:15.310972 Write leveling : PASS
9091 22:59:15.314636 RX DQS gating : PASS
9092 22:59:15.314733 RX DQ/DQS(RDDQC) : PASS
9093 22:59:15.317829 TX DQ/DQS : PASS
9094 22:59:15.320933 RX DATLAT : PASS
9095 22:59:15.321065 RX DQ/DQS(Engine): PASS
9096 22:59:15.323984 TX OE : PASS
9097 22:59:15.324109 All Pass.
9098 22:59:15.324207
9099 22:59:15.327256 CH 1, Rank 1
9100 22:59:15.327376 SW Impedance : PASS
9101 22:59:15.330311 DUTY Scan : NO K
9102 22:59:15.334058 ZQ Calibration : PASS
9103 22:59:15.334192 Jitter Meter : NO K
9104 22:59:15.337299 CBT Training : PASS
9105 22:59:15.340459 Write leveling : PASS
9106 22:59:15.340546 RX DQS gating : PASS
9107 22:59:15.343530 RX DQ/DQS(RDDQC) : PASS
9108 22:59:15.347317 TX DQ/DQS : PASS
9109 22:59:15.347445 RX DATLAT : PASS
9110 22:59:15.350476 RX DQ/DQS(Engine): PASS
9111 22:59:15.353505 TX OE : PASS
9112 22:59:15.353604 All Pass.
9113 22:59:15.353675
9114 22:59:15.353739 DramC Write-DBI on
9115 22:59:15.357364 PER_BANK_REFRESH: Hybrid Mode
9116 22:59:15.360431 TX_TRACKING: ON
9117 22:59:15.367036 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9118 22:59:15.377391 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9119 22:59:15.383545 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9120 22:59:15.386935 [FAST_K] Save calibration result to emmc
9121 22:59:15.390240 sync common calibartion params.
9122 22:59:15.393867 sync cbt_mode0:1, 1:1
9123 22:59:15.394016 dram_init: ddr_geometry: 2
9124 22:59:15.396918 dram_init: ddr_geometry: 2
9125 22:59:15.400485 dram_init: ddr_geometry: 2
9126 22:59:15.400601 0:dram_rank_size:100000000
9127 22:59:15.403511 1:dram_rank_size:100000000
9128 22:59:15.409986 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9129 22:59:15.413757 DFS_SHUFFLE_HW_MODE: ON
9130 22:59:15.416772 dramc_set_vcore_voltage set vcore to 725000
9131 22:59:15.416885 Read voltage for 1600, 0
9132 22:59:15.420500 Vio18 = 0
9133 22:59:15.420591 Vcore = 725000
9134 22:59:15.420681 Vdram = 0
9135 22:59:15.423724 Vddq = 0
9136 22:59:15.423823 Vmddr = 0
9137 22:59:15.426856 switch to 3200 Mbps bootup
9138 22:59:15.426964 [DramcRunTimeConfig]
9139 22:59:15.427076 PHYPLL
9140 22:59:15.429943 DPM_CONTROL_AFTERK: ON
9141 22:59:15.433678 PER_BANK_REFRESH: ON
9142 22:59:15.433774 REFRESH_OVERHEAD_REDUCTION: ON
9143 22:59:15.437044 CMD_PICG_NEW_MODE: OFF
9144 22:59:15.439976 XRTWTW_NEW_MODE: ON
9145 22:59:15.440101 XRTRTR_NEW_MODE: ON
9146 22:59:15.443694 TX_TRACKING: ON
9147 22:59:15.443819 RDSEL_TRACKING: OFF
9148 22:59:15.446808 DQS Precalculation for DVFS: ON
9149 22:59:15.446918 RX_TRACKING: OFF
9150 22:59:15.450126 HW_GATING DBG: ON
9151 22:59:15.450259 ZQCS_ENABLE_LP4: ON
9152 22:59:15.453230 RX_PICG_NEW_MODE: ON
9153 22:59:15.456520 TX_PICG_NEW_MODE: ON
9154 22:59:15.456642 ENABLE_RX_DCM_DPHY: ON
9155 22:59:15.460264 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9156 22:59:15.463404 DUMMY_READ_FOR_TRACKING: OFF
9157 22:59:15.466468 !!! SPM_CONTROL_AFTERK: OFF
9158 22:59:15.470125 !!! SPM could not control APHY
9159 22:59:15.470233 IMPEDANCE_TRACKING: ON
9160 22:59:15.473266 TEMP_SENSOR: ON
9161 22:59:15.473362 HW_SAVE_FOR_SR: OFF
9162 22:59:15.476465 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9163 22:59:15.479921 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9164 22:59:15.483116 Read ODT Tracking: ON
9165 22:59:15.483238 Refresh Rate DeBounce: ON
9166 22:59:15.486728 DFS_NO_QUEUE_FLUSH: ON
9167 22:59:15.489597 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9168 22:59:15.493294 ENABLE_DFS_RUNTIME_MRW: OFF
9169 22:59:15.493399 DDR_RESERVE_NEW_MODE: ON
9170 22:59:15.496343 MR_CBT_SWITCH_FREQ: ON
9171 22:59:15.500059 =========================
9172 22:59:15.517671 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9173 22:59:15.520750 dram_init: ddr_geometry: 2
9174 22:59:15.539665 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9175 22:59:15.542934 dram_init: dram init end (result: 0)
9176 22:59:15.549433 DRAM-K: Full calibration passed in 24577 msecs
9177 22:59:15.552561 MRC: failed to locate region type 0.
9178 22:59:15.552663 DRAM rank0 size:0x100000000,
9179 22:59:15.556231 DRAM rank1 size=0x100000000
9180 22:59:15.566236 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9181 22:59:15.572484 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9182 22:59:15.579355 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9183 22:59:15.585861 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9184 22:59:15.589111 DRAM rank0 size:0x100000000,
9185 22:59:15.592544 DRAM rank1 size=0x100000000
9186 22:59:15.592649 CBMEM:
9187 22:59:15.595688 IMD: root @ 0xfffff000 254 entries.
9188 22:59:15.599270 IMD: root @ 0xffffec00 62 entries.
9189 22:59:15.602544 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9190 22:59:15.606198 WARNING: RO_VPD is uninitialized or empty.
9191 22:59:15.612295 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9192 22:59:15.619522 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9193 22:59:15.632384 read SPI 0x42894 0xe01e: 6227 us, 9213 KB/s, 73.704 Mbps
9194 22:59:15.643525 BS: romstage times (exec / console): total (unknown) / 24083 ms
9195 22:59:15.643668
9196 22:59:15.643756
9197 22:59:15.653768 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9198 22:59:15.656791 ARM64: Exception handlers installed.
9199 22:59:15.660091 ARM64: Testing exception
9200 22:59:15.663819 ARM64: Done test exception
9201 22:59:15.663947 Enumerating buses...
9202 22:59:15.666925 Show all devs... Before device enumeration.
9203 22:59:15.670159 Root Device: enabled 1
9204 22:59:15.673771 CPU_CLUSTER: 0: enabled 1
9205 22:59:15.673893 CPU: 00: enabled 1
9206 22:59:15.676881 Compare with tree...
9207 22:59:15.676997 Root Device: enabled 1
9208 22:59:15.679811 CPU_CLUSTER: 0: enabled 1
9209 22:59:15.683562 CPU: 00: enabled 1
9210 22:59:15.683703 Root Device scanning...
9211 22:59:15.686652 scan_static_bus for Root Device
9212 22:59:15.690405 CPU_CLUSTER: 0 enabled
9213 22:59:15.693522 scan_static_bus for Root Device done
9214 22:59:15.696498 scan_bus: bus Root Device finished in 8 msecs
9215 22:59:15.696631 done
9216 22:59:15.703541 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9217 22:59:15.706599 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9218 22:59:15.713249 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9219 22:59:15.716823 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9220 22:59:15.719773 Allocating resources...
9221 22:59:15.723400 Reading resources...
9222 22:59:15.726446 Root Device read_resources bus 0 link: 0
9223 22:59:15.726584 DRAM rank0 size:0x100000000,
9224 22:59:15.729581 DRAM rank1 size=0x100000000
9225 22:59:15.733264 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9226 22:59:15.736398 CPU: 00 missing read_resources
9227 22:59:15.743108 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9228 22:59:15.746799 Root Device read_resources bus 0 link: 0 done
9229 22:59:15.746933 Done reading resources.
9230 22:59:15.753193 Show resources in subtree (Root Device)...After reading.
9231 22:59:15.756233 Root Device child on link 0 CPU_CLUSTER: 0
9232 22:59:15.759966 CPU_CLUSTER: 0 child on link 0 CPU: 00
9233 22:59:15.770116 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9234 22:59:15.770299 CPU: 00
9235 22:59:15.773112 Root Device assign_resources, bus 0 link: 0
9236 22:59:15.776215 CPU_CLUSTER: 0 missing set_resources
9237 22:59:15.783000 Root Device assign_resources, bus 0 link: 0 done
9238 22:59:15.783156 Done setting resources.
9239 22:59:15.789543 Show resources in subtree (Root Device)...After assigning values.
9240 22:59:15.793383 Root Device child on link 0 CPU_CLUSTER: 0
9241 22:59:15.796504 CPU_CLUSTER: 0 child on link 0 CPU: 00
9242 22:59:15.806072 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9243 22:59:15.806243 CPU: 00
9244 22:59:15.809704 Done allocating resources.
9245 22:59:15.812737 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9246 22:59:15.816376 Enabling resources...
9247 22:59:15.816499 done.
9248 22:59:15.823114 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9249 22:59:15.823256 Initializing devices...
9250 22:59:15.826198 Root Device init
9251 22:59:15.826309 init hardware done!
9252 22:59:15.829790 0x00000018: ctrlr->caps
9253 22:59:15.832850 52.000 MHz: ctrlr->f_max
9254 22:59:15.832943 0.400 MHz: ctrlr->f_min
9255 22:59:15.836128 0x40ff8080: ctrlr->voltages
9256 22:59:15.836228 sclk: 390625
9257 22:59:15.839232 Bus Width = 1
9258 22:59:15.839325 sclk: 390625
9259 22:59:15.843029 Bus Width = 1
9260 22:59:15.843136 Early init status = 3
9261 22:59:15.849209 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9262 22:59:15.852471 in-header: 03 fc 00 00 01 00 00 00
9263 22:59:15.852565 in-data: 00
9264 22:59:15.859493 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9265 22:59:15.862627 in-header: 03 fd 00 00 00 00 00 00
9266 22:59:15.865718 in-data:
9267 22:59:15.869525 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9268 22:59:15.872543 in-header: 03 fc 00 00 01 00 00 00
9269 22:59:15.875784 in-data: 00
9270 22:59:15.878820 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9271 22:59:15.886772 in-header: 03 fd 00 00 00 00 00 00
9272 22:59:15.886928 in-data:
9273 22:59:15.890523 [SSUSB] Setting up USB HOST controller...
9274 22:59:15.893403 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9275 22:59:15.897047 [SSUSB] phy power-on done.
9276 22:59:15.900092 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9277 22:59:15.906622 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9278 22:59:15.909793 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9279 22:59:15.916855 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9280 22:59:15.923064 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9281 22:59:15.930305 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9282 22:59:15.936497 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9283 22:59:15.943279 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9284 22:59:15.946537 SPM: binary array size = 0x9dc
9285 22:59:15.949606 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9286 22:59:15.956611 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9287 22:59:15.963148 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9288 22:59:15.969402 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9289 22:59:15.973278 configure_display: Starting display init
9290 22:59:16.006978 anx7625_power_on_init: Init interface.
9291 22:59:16.009985 anx7625_disable_pd_protocol: Disabled PD feature.
9292 22:59:16.013643 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9293 22:59:16.041207 anx7625_start_dp_work: Secure OCM version=00
9294 22:59:16.044834 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9295 22:59:16.059522 sp_tx_get_edid_block: EDID Block = 1
9296 22:59:16.161988 Extracted contents:
9297 22:59:16.165123 header: 00 ff ff ff ff ff ff 00
9298 22:59:16.168381 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9299 22:59:16.172111 version: 01 04
9300 22:59:16.175321 basic params: 95 1f 11 78 0a
9301 22:59:16.178490 chroma info: 76 90 94 55 54 90 27 21 50 54
9302 22:59:16.181648 established: 00 00 00
9303 22:59:16.188588 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9304 22:59:16.191846 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9305 22:59:16.198634 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9306 22:59:16.204976 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9307 22:59:16.211567 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9308 22:59:16.214968 extensions: 00
9309 22:59:16.215077 checksum: fb
9310 22:59:16.215143
9311 22:59:16.218093 Manufacturer: IVO Model 57d Serial Number 0
9312 22:59:16.221650 Made week 0 of 2020
9313 22:59:16.221745 EDID version: 1.4
9314 22:59:16.225117 Digital display
9315 22:59:16.228083 6 bits per primary color channel
9316 22:59:16.228175 DisplayPort interface
9317 22:59:16.231729 Maximum image size: 31 cm x 17 cm
9318 22:59:16.234715 Gamma: 220%
9319 22:59:16.234822 Check DPMS levels
9320 22:59:16.237826 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9321 22:59:16.244491 First detailed timing is preferred timing
9322 22:59:16.244619 Established timings supported:
9323 22:59:16.248167 Standard timings supported:
9324 22:59:16.251203 Detailed timings
9325 22:59:16.254881 Hex of detail: 383680a07038204018303c0035ae10000019
9326 22:59:16.258231 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9327 22:59:16.265119 0780 0798 07c8 0820 hborder 0
9328 22:59:16.268248 0438 043b 0447 0458 vborder 0
9329 22:59:16.271527 -hsync -vsync
9330 22:59:16.271641 Did detailed timing
9331 22:59:16.277851 Hex of detail: 000000000000000000000000000000000000
9332 22:59:16.277954 Manufacturer-specified data, tag 0
9333 22:59:16.284627 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9334 22:59:16.287809 ASCII string: InfoVision
9335 22:59:16.291626 Hex of detail: 000000fe00523134304e574635205248200a
9336 22:59:16.294690 ASCII string: R140NWF5 RH
9337 22:59:16.294838 Checksum
9338 22:59:16.298467 Checksum: 0xfb (valid)
9339 22:59:16.301644 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9340 22:59:16.304846 DSI data_rate: 832800000 bps
9341 22:59:16.307926 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9342 22:59:16.314644 anx7625_parse_edid: pixelclock(138800).
9343 22:59:16.318215 hactive(1920), hsync(48), hfp(24), hbp(88)
9344 22:59:16.321179 vactive(1080), vsync(12), vfp(3), vbp(17)
9345 22:59:16.324873 anx7625_dsi_config: config dsi.
9346 22:59:16.331305 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9347 22:59:16.343771 anx7625_dsi_config: success to config DSI
9348 22:59:16.347475 anx7625_dp_start: MIPI phy setup OK.
9349 22:59:16.350968 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9350 22:59:16.354068 mtk_ddp_mode_set invalid vrefresh 60
9351 22:59:16.357742 main_disp_path_setup
9352 22:59:16.357864 ovl_layer_smi_id_en
9353 22:59:16.360673 ovl_layer_smi_id_en
9354 22:59:16.360783 ccorr_config
9355 22:59:16.360886 aal_config
9356 22:59:16.363888 gamma_config
9357 22:59:16.363999 postmask_config
9358 22:59:16.367605 dither_config
9359 22:59:16.370697 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9360 22:59:16.377203 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9361 22:59:16.380820 Root Device init finished in 551 msecs
9362 22:59:16.380953 CPU_CLUSTER: 0 init
9363 22:59:16.390522 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9364 22:59:16.393640 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9365 22:59:16.397554 APU_MBOX 0x190000b0 = 0x10001
9366 22:59:16.400603 APU_MBOX 0x190001b0 = 0x10001
9367 22:59:16.403721 APU_MBOX 0x190005b0 = 0x10001
9368 22:59:16.407510 APU_MBOX 0x190006b0 = 0x10001
9369 22:59:16.410620 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9370 22:59:16.423293 read SPI 0x539f4 0xe237: 6250 us, 9265 KB/s, 74.120 Mbps
9371 22:59:16.435257 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9372 22:59:16.442372 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9373 22:59:16.453547 read SPI 0x61c74 0xe8ef: 6411 us, 9301 KB/s, 74.408 Mbps
9374 22:59:16.462600 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9375 22:59:16.466212 CPU_CLUSTER: 0 init finished in 81 msecs
9376 22:59:16.469391 Devices initialized
9377 22:59:16.473071 Show all devs... After init.
9378 22:59:16.473232 Root Device: enabled 1
9379 22:59:16.476264 CPU_CLUSTER: 0: enabled 1
9380 22:59:16.479360 CPU: 00: enabled 1
9381 22:59:16.483108 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9382 22:59:16.486236 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9383 22:59:16.489341 ELOG: NV offset 0x57f000 size 0x1000
9384 22:59:16.495642 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9385 22:59:16.502616 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9386 22:59:16.505880 ELOG: Event(17) added with size 13 at 2023-06-05 22:59:21 UTC
9387 22:59:16.512717 out: cmd=0x121: 03 db 21 01 00 00 00 00
9388 22:59:16.515833 in-header: 03 d1 00 00 2c 00 00 00
9389 22:59:16.525669 in-data: 8e 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9390 22:59:16.532815 ELOG: Event(A1) added with size 10 at 2023-06-05 22:59:21 UTC
9391 22:59:16.539484 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9392 22:59:16.545921 ELOG: Event(A0) added with size 9 at 2023-06-05 22:59:21 UTC
9393 22:59:16.549015 elog_add_boot_reason: Logged dev mode boot
9394 22:59:16.556012 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9395 22:59:16.556167 Finalize devices...
9396 22:59:16.559512 Devices finalized
9397 22:59:16.562828 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9398 22:59:16.565721 Writing coreboot table at 0xffe64000
9399 22:59:16.569496 0. 000000000010a000-0000000000113fff: RAMSTAGE
9400 22:59:16.572572 1. 0000000040000000-00000000400fffff: RAM
9401 22:59:16.578841 2. 0000000040100000-000000004032afff: RAMSTAGE
9402 22:59:16.582145 3. 000000004032b000-00000000545fffff: RAM
9403 22:59:16.585803 4. 0000000054600000-000000005465ffff: BL31
9404 22:59:16.588993 5. 0000000054660000-00000000ffe63fff: RAM
9405 22:59:16.595933 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9406 22:59:16.599052 7. 0000000100000000-000000023fffffff: RAM
9407 22:59:16.602086 Passing 5 GPIOs to payload:
9408 22:59:16.605645 NAME | PORT | POLARITY | VALUE
9409 22:59:16.608994 EC in RW | 0x000000aa | low | undefined
9410 22:59:16.615914 EC interrupt | 0x00000005 | low | undefined
9411 22:59:16.619066 TPM interrupt | 0x000000ab | high | undefined
9412 22:59:16.626001 SD card detect | 0x00000011 | high | undefined
9413 22:59:16.629102 speaker enable | 0x00000093 | high | undefined
9414 22:59:16.632228 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9415 22:59:16.635916 in-header: 03 f9 00 00 02 00 00 00
9416 22:59:16.639044 in-data: 02 00
9417 22:59:16.639170 ADC[4]: Raw value=900590 ID=7
9418 22:59:16.642460 ADC[3]: Raw value=213336 ID=1
9419 22:59:16.645527 RAM Code: 0x71
9420 22:59:16.645643 ADC[6]: Raw value=74557 ID=0
9421 22:59:16.649139 ADC[5]: Raw value=212229 ID=1
9422 22:59:16.651977 SKU Code: 0x1
9423 22:59:16.655714 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum ded1
9424 22:59:16.658603 coreboot table: 964 bytes.
9425 22:59:16.662107 IMD ROOT 0. 0xfffff000 0x00001000
9426 22:59:16.665628 IMD SMALL 1. 0xffffe000 0x00001000
9427 22:59:16.668484 RO MCACHE 2. 0xffffc000 0x00001104
9428 22:59:16.671895 CONSOLE 3. 0xfff7c000 0x00080000
9429 22:59:16.675529 FMAP 4. 0xfff7b000 0x00000452
9430 22:59:16.678696 TIME STAMP 5. 0xfff7a000 0x00000910
9431 22:59:16.682381 VBOOT WORK 6. 0xfff66000 0x00014000
9432 22:59:16.685574 RAMOOPS 7. 0xffe66000 0x00100000
9433 22:59:16.688662 COREBOOT 8. 0xffe64000 0x00002000
9434 22:59:16.688796 IMD small region:
9435 22:59:16.695637 IMD ROOT 0. 0xffffec00 0x00000400
9436 22:59:16.698775 VPD 1. 0xffffeba0 0x0000004c
9437 22:59:16.702014 MMC STATUS 2. 0xffffeb80 0x00000004
9438 22:59:16.705052 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9439 22:59:16.708604 Probing TPM: done!
9440 22:59:16.711784 Connected to device vid:did:rid of 1ae0:0028:00
9441 22:59:16.722505 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9442 22:59:16.725666 Initialized TPM device CR50 revision 0
9443 22:59:16.728977 Checking cr50 for pending updates
9444 22:59:16.733365 Reading cr50 TPM mode
9445 22:59:16.742339 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9446 22:59:16.748470 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9447 22:59:16.788466 read SPI 0x3990ec 0x4f1b0: 34858 us, 9295 KB/s, 74.360 Mbps
9448 22:59:16.791543 Checking segment from ROM address 0x40100000
9449 22:59:16.795271 Checking segment from ROM address 0x4010001c
9450 22:59:16.801545 Loading segment from ROM address 0x40100000
9451 22:59:16.801704 code (compression=0)
9452 22:59:16.811515 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9453 22:59:16.818365 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9454 22:59:16.818522 it's not compressed!
9455 22:59:16.824873 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9456 22:59:16.828665 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9457 22:59:16.848612 Loading segment from ROM address 0x4010001c
9458 22:59:16.848790 Entry Point 0x80000000
9459 22:59:16.852095 Loaded segments
9460 22:59:16.855314 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9461 22:59:16.861842 Jumping to boot code at 0x80000000(0xffe64000)
9462 22:59:16.868499 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9463 22:59:16.875015 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9464 22:59:16.883268 read SPI 0x8eb68 0x74a8: 3225 us, 9260 KB/s, 74.080 Mbps
9465 22:59:16.886168 Checking segment from ROM address 0x40100000
9466 22:59:16.889765 Checking segment from ROM address 0x4010001c
9467 22:59:16.896600 Loading segment from ROM address 0x40100000
9468 22:59:16.896752 code (compression=1)
9469 22:59:16.903016 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9470 22:59:16.913024 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9471 22:59:16.913156 using LZMA
9472 22:59:16.921353 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9473 22:59:16.928410 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9474 22:59:16.931451 Loading segment from ROM address 0x4010001c
9475 22:59:16.931560 Entry Point 0x54601000
9476 22:59:16.935095 Loaded segments
9477 22:59:16.938373 NOTICE: MT8192 bl31_setup
9478 22:59:16.945194 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9479 22:59:16.948213 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9480 22:59:16.951951 WARNING: region 0:
9481 22:59:16.954989 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9482 22:59:16.955108 WARNING: region 1:
9483 22:59:16.961802 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9484 22:59:16.964882 WARNING: region 2:
9485 22:59:16.968549 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9486 22:59:16.971550 WARNING: region 3:
9487 22:59:16.974732 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9488 22:59:16.978255 WARNING: region 4:
9489 22:59:16.984689 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9490 22:59:16.984850 WARNING: region 5:
9491 22:59:16.988242 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9492 22:59:16.991290 WARNING: region 6:
9493 22:59:16.994870 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9494 22:59:16.998008 WARNING: region 7:
9495 22:59:17.001703 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9496 22:59:17.008124 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9497 22:59:17.011807 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9498 22:59:17.014962 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9499 22:59:17.022058 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9500 22:59:17.025194 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9501 22:59:17.028434 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9502 22:59:17.035391 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9503 22:59:17.038564 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9504 22:59:17.044727 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9505 22:59:17.048621 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9506 22:59:17.051558 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9507 22:59:17.058271 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9508 22:59:17.061798 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9509 22:59:17.065013 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9510 22:59:17.071629 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9511 22:59:17.075224 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9512 22:59:17.082026 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9513 22:59:17.084889 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9514 22:59:17.088563 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9515 22:59:17.095383 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9516 22:59:17.098382 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9517 22:59:17.101888 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9518 22:59:17.108581 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9519 22:59:17.111800 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9520 22:59:17.118561 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9521 22:59:17.121660 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9522 22:59:17.125551 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9523 22:59:17.131823 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9524 22:59:17.135010 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9525 22:59:17.142008 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9526 22:59:17.145125 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9527 22:59:17.148288 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9528 22:59:17.154985 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9529 22:59:17.158150 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9530 22:59:17.161842 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9531 22:59:17.164905 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9532 22:59:17.171474 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9533 22:59:17.174987 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9534 22:59:17.178060 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9535 22:59:17.181800 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9536 22:59:17.188220 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9537 22:59:17.191979 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9538 22:59:17.194850 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9539 22:59:17.198503 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9540 22:59:17.205183 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9541 22:59:17.208774 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9542 22:59:17.211857 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9543 22:59:17.215500 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9544 22:59:17.221830 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9545 22:59:17.225061 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9546 22:59:17.231941 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9547 22:59:17.235004 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9548 22:59:17.238815 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9549 22:59:17.245111 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9550 22:59:17.248302 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9551 22:59:17.255128 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9552 22:59:17.258814 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9553 22:59:17.264955 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9554 22:59:17.268641 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9555 22:59:17.271656 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9556 22:59:17.278495 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9557 22:59:17.282015 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9558 22:59:17.288682 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9559 22:59:17.291879 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9560 22:59:17.298411 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9561 22:59:17.302052 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9562 22:59:17.305118 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9563 22:59:17.311874 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9564 22:59:17.314813 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9565 22:59:17.321473 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9566 22:59:17.325424 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9567 22:59:17.331721 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9568 22:59:17.334810 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9569 22:59:17.338061 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9570 22:59:17.344926 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9571 22:59:17.348137 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9572 22:59:17.355089 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9573 22:59:17.358240 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9574 22:59:17.364984 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9575 22:59:17.368690 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9576 22:59:17.375295 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9577 22:59:17.378393 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9578 22:59:17.382020 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9579 22:59:17.388493 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9580 22:59:17.391505 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9581 22:59:17.398299 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9582 22:59:17.401911 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9583 22:59:17.408219 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9584 22:59:17.411784 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9585 22:59:17.415453 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9586 22:59:17.422165 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9587 22:59:17.425420 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9588 22:59:17.431671 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9589 22:59:17.435409 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9590 22:59:17.441733 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9591 22:59:17.444907 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9592 22:59:17.448643 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9593 22:59:17.451851 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9594 22:59:17.458878 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9595 22:59:17.462107 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9596 22:59:17.465431 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9597 22:59:17.471801 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9598 22:59:17.475322 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9599 22:59:17.478365 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9600 22:59:17.485309 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9601 22:59:17.488911 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9602 22:59:17.495590 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9603 22:59:17.498533 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9604 22:59:17.501728 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9605 22:59:17.508864 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9606 22:59:17.512067 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9607 22:59:17.519027 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9608 22:59:17.521927 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9609 22:59:17.525581 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9610 22:59:17.532345 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9611 22:59:17.535550 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9612 22:59:17.538749 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9613 22:59:17.545470 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9614 22:59:17.548602 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9615 22:59:17.551810 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9616 22:59:17.555587 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9617 22:59:17.561836 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9618 22:59:17.565704 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9619 22:59:17.568926 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9620 22:59:17.575546 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9621 22:59:17.578503 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9622 22:59:17.582131 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9623 22:59:17.588409 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9624 22:59:17.592021 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9625 22:59:17.598715 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9626 22:59:17.602487 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9627 22:59:17.605555 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9628 22:59:17.612257 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9629 22:59:17.615334 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9630 22:59:17.619161 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9631 22:59:17.625263 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9632 22:59:17.629118 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9633 22:59:17.635310 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9634 22:59:17.638465 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9635 22:59:17.642158 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9636 22:59:17.648493 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9637 22:59:17.652215 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9638 22:59:17.658531 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9639 22:59:17.662331 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9640 22:59:17.665568 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9641 22:59:17.672407 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9642 22:59:17.675417 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9643 22:59:17.678533 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9644 22:59:17.685269 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9645 22:59:17.688976 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9646 22:59:17.695115 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9647 22:59:17.698842 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9648 22:59:17.702351 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9649 22:59:17.709022 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9650 22:59:17.712167 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9651 22:59:17.718774 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9652 22:59:17.721864 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9653 22:59:17.725574 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9654 22:59:17.732294 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9655 22:59:17.735197 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9656 22:59:17.738518 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9657 22:59:17.745392 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9658 22:59:17.748503 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9659 22:59:17.755401 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9660 22:59:17.758546 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9661 22:59:17.761784 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9662 22:59:17.768681 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9663 22:59:17.771854 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9664 22:59:17.778353 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9665 22:59:17.781976 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9666 22:59:17.784840 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9667 22:59:17.791441 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9668 22:59:17.795243 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9669 22:59:17.801633 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9670 22:59:17.804613 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9671 22:59:17.808204 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9672 22:59:17.814604 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9673 22:59:17.818064 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9674 22:59:17.824667 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9675 22:59:17.828431 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9676 22:59:17.831538 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9677 22:59:17.838265 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9678 22:59:17.841228 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9679 22:59:17.848104 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9680 22:59:17.851204 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9681 22:59:17.854438 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9682 22:59:17.861322 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9683 22:59:17.864418 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9684 22:59:17.871362 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9685 22:59:17.874496 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9686 22:59:17.878284 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9687 22:59:17.884678 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9688 22:59:17.887663 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9689 22:59:17.894318 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9690 22:59:17.897745 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9691 22:59:17.901465 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9692 22:59:17.907989 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9693 22:59:17.910886 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9694 22:59:17.917620 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9695 22:59:17.921350 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9696 22:59:17.924397 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9697 22:59:17.931066 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9698 22:59:17.934280 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9699 22:59:17.940860 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9700 22:59:17.944048 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9701 22:59:17.950711 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9702 22:59:17.954557 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9703 22:59:17.957745 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9704 22:59:17.964001 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9705 22:59:17.967324 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9706 22:59:17.974142 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9707 22:59:17.977371 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9708 22:59:17.984300 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9709 22:59:17.987437 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9710 22:59:17.990588 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9711 22:59:17.997514 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9712 22:59:18.000444 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9713 22:59:18.007253 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9714 22:59:18.010333 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9715 22:59:18.013872 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9716 22:59:18.020565 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9717 22:59:18.023723 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9718 22:59:18.030286 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9719 22:59:18.033989 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9720 22:59:18.040154 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9721 22:59:18.043721 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9722 22:59:18.046786 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9723 22:59:18.053510 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9724 22:59:18.057497 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9725 22:59:18.060537 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9726 22:59:18.066914 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9727 22:59:18.070767 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9728 22:59:18.073808 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9729 22:59:18.076967 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9730 22:59:18.083380 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9731 22:59:18.087107 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9732 22:59:18.090321 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9733 22:59:18.096634 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9734 22:59:18.100349 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9735 22:59:18.106763 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9736 22:59:18.110190 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9737 22:59:18.113633 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9738 22:59:18.120217 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9739 22:59:18.123595 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9740 22:59:18.127174 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9741 22:59:18.133393 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9742 22:59:18.136780 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9743 22:59:18.143570 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9744 22:59:18.146577 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9745 22:59:18.150376 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9746 22:59:18.156484 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9747 22:59:18.160187 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9748 22:59:18.163322 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9749 22:59:18.170287 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9750 22:59:18.173354 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9751 22:59:18.176487 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9752 22:59:18.183458 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9753 22:59:18.186607 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9754 22:59:18.189775 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9755 22:59:18.196890 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9756 22:59:18.200161 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9757 22:59:18.206295 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9758 22:59:18.210064 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9759 22:59:18.212939 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9760 22:59:18.219959 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9761 22:59:18.223456 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9762 22:59:18.226493 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9763 22:59:18.233018 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9764 22:59:18.236481 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9765 22:59:18.240025 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9766 22:59:18.242931 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9767 22:59:18.249721 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9768 22:59:18.252877 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9769 22:59:18.256439 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9770 22:59:18.259599 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9771 22:59:18.266254 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9772 22:59:18.269468 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9773 22:59:18.273129 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9774 22:59:18.276320 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9775 22:59:18.282747 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9776 22:59:18.285889 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9777 22:59:18.289727 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9778 22:59:18.296063 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9779 22:59:18.299228 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9780 22:59:18.306182 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9781 22:59:18.309287 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9782 22:59:18.312880 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9783 22:59:18.319249 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9784 22:59:18.323009 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9785 22:59:18.329379 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9786 22:59:18.332898 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9787 22:59:18.335856 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9788 22:59:18.342317 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9789 22:59:18.346019 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9790 22:59:18.352637 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9791 22:59:18.356066 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9792 22:59:18.359452 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9793 22:59:18.366019 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9794 22:59:18.369707 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9795 22:59:18.375785 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9796 22:59:18.379076 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9797 22:59:18.385940 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9798 22:59:18.389240 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9799 22:59:18.392310 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9800 22:59:18.398815 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9801 22:59:18.402576 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9802 22:59:18.408892 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9803 22:59:18.412604 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9804 22:59:18.415710 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9805 22:59:18.422286 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9806 22:59:18.425595 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9807 22:59:18.431868 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9808 22:59:18.435472 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9809 22:59:18.438630 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9810 22:59:18.445610 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9811 22:59:18.449028 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9812 22:59:18.455756 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9813 22:59:18.458754 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9814 22:59:18.462179 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9815 22:59:18.468429 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9816 22:59:18.472077 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9817 22:59:18.478577 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9818 22:59:18.481661 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9819 22:59:18.485461 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9820 22:59:18.491746 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9821 22:59:18.494993 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9822 22:59:18.501989 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9823 22:59:18.505141 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9824 22:59:18.511579 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9825 22:59:18.515425 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9826 22:59:18.518431 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9827 22:59:18.525022 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9828 22:59:18.528387 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9829 22:59:18.534628 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9830 22:59:18.538288 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9831 22:59:18.545123 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9832 22:59:18.548005 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9833 22:59:18.551502 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9834 22:59:18.557829 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9835 22:59:18.561438 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9836 22:59:18.568219 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9837 22:59:18.571257 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9838 22:59:18.574660 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9839 22:59:18.581424 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9840 22:59:18.584432 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9841 22:59:18.591355 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9842 22:59:18.594487 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9843 22:59:18.597555 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9844 22:59:18.604587 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9845 22:59:18.607781 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9846 22:59:18.614838 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9847 22:59:18.618048 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9848 22:59:18.624211 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9849 22:59:18.627688 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9850 22:59:18.630671 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9851 22:59:18.637539 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9852 22:59:18.640894 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9853 22:59:18.647639 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9854 22:59:18.650710 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9855 22:59:18.657366 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9856 22:59:18.660791 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9857 22:59:18.664177 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9858 22:59:18.670787 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9859 22:59:18.673996 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9860 22:59:18.680743 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9861 22:59:18.684420 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9862 22:59:18.690436 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9863 22:59:18.694106 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9864 22:59:18.697376 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9865 22:59:18.704195 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9866 22:59:18.707375 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9867 22:59:18.713784 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9868 22:59:18.717497 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9869 22:59:18.723879 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9870 22:59:18.727616 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9871 22:59:18.730449 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9872 22:59:18.737236 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9873 22:59:18.740505 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9874 22:59:18.747376 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9875 22:59:18.750481 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9876 22:59:18.757395 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9877 22:59:18.760489 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9878 22:59:18.763603 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9879 22:59:18.770479 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9880 22:59:18.773737 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9881 22:59:18.780535 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9882 22:59:18.783570 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9883 22:59:18.790053 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9884 22:59:18.793615 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9885 22:59:18.800269 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9886 22:59:18.803523 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9887 22:59:18.806675 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9888 22:59:18.813543 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9889 22:59:18.816752 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9890 22:59:18.823674 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9891 22:59:18.826769 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9892 22:59:18.833206 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9893 22:59:18.836698 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9894 22:59:18.840488 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9895 22:59:18.846596 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9896 22:59:18.850337 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9897 22:59:18.856793 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9898 22:59:18.860406 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9899 22:59:18.863457 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9900 22:59:18.870177 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9901 22:59:18.873030 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9902 22:59:18.880096 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9903 22:59:18.882989 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9904 22:59:18.890148 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9905 22:59:18.893078 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9906 22:59:18.900226 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9907 22:59:18.903172 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9908 22:59:18.910005 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9909 22:59:18.913127 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9910 22:59:18.919975 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9911 22:59:18.923209 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9912 22:59:18.930073 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9913 22:59:18.933252 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9914 22:59:18.939461 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9915 22:59:18.943048 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9916 22:59:18.949389 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9917 22:59:18.952549 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9918 22:59:18.959273 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9919 22:59:18.962942 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9920 22:59:18.969191 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9921 22:59:18.972414 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9922 22:59:18.979146 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9923 22:59:18.982696 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9924 22:59:18.989143 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9925 22:59:18.992909 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9926 22:59:18.999000 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9927 22:59:19.002422 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9928 22:59:19.009159 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9929 22:59:19.012277 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9930 22:59:19.015914 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9931 22:59:19.019183 INFO: [APUAPC] vio 0
9932 22:59:19.026157 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9933 22:59:19.029402 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9934 22:59:19.032470 INFO: [APUAPC] D0_APC_0: 0x400510
9935 22:59:19.035597 INFO: [APUAPC] D0_APC_1: 0x0
9936 22:59:19.038840 INFO: [APUAPC] D0_APC_2: 0x1540
9937 22:59:19.041989 INFO: [APUAPC] D0_APC_3: 0x0
9938 22:59:19.045528 INFO: [APUAPC] D1_APC_0: 0xffffffff
9939 22:59:19.049201 INFO: [APUAPC] D1_APC_1: 0xffffffff
9940 22:59:19.052341 INFO: [APUAPC] D1_APC_2: 0x3fffff
9941 22:59:19.055605 INFO: [APUAPC] D1_APC_3: 0x0
9942 22:59:19.059179 INFO: [APUAPC] D2_APC_0: 0xffffffff
9943 22:59:19.062325 INFO: [APUAPC] D2_APC_1: 0xffffffff
9944 22:59:19.065488 INFO: [APUAPC] D2_APC_2: 0x3fffff
9945 22:59:19.065577 INFO: [APUAPC] D2_APC_3: 0x0
9946 22:59:19.069016 INFO: [APUAPC] D3_APC_0: 0xffffffff
9947 22:59:19.075346 INFO: [APUAPC] D3_APC_1: 0xffffffff
9948 22:59:19.079000 INFO: [APUAPC] D3_APC_2: 0x3fffff
9949 22:59:19.079119 INFO: [APUAPC] D3_APC_3: 0x0
9950 22:59:19.082091 INFO: [APUAPC] D4_APC_0: 0xffffffff
9951 22:59:19.085264 INFO: [APUAPC] D4_APC_1: 0xffffffff
9952 22:59:19.088794 INFO: [APUAPC] D4_APC_2: 0x3fffff
9953 22:59:19.092236 INFO: [APUAPC] D4_APC_3: 0x0
9954 22:59:19.095017 INFO: [APUAPC] D5_APC_0: 0xffffffff
9955 22:59:19.098789 INFO: [APUAPC] D5_APC_1: 0xffffffff
9956 22:59:19.101696 INFO: [APUAPC] D5_APC_2: 0x3fffff
9957 22:59:19.105194 INFO: [APUAPC] D5_APC_3: 0x0
9958 22:59:19.108748 INFO: [APUAPC] D6_APC_0: 0xffffffff
9959 22:59:19.111820 INFO: [APUAPC] D6_APC_1: 0xffffffff
9960 22:59:19.115051 INFO: [APUAPC] D6_APC_2: 0x3fffff
9961 22:59:19.118659 INFO: [APUAPC] D6_APC_3: 0x0
9962 22:59:19.121854 INFO: [APUAPC] D7_APC_0: 0xffffffff
9963 22:59:19.125582 INFO: [APUAPC] D7_APC_1: 0xffffffff
9964 22:59:19.128666 INFO: [APUAPC] D7_APC_2: 0x3fffff
9965 22:59:19.131820 INFO: [APUAPC] D7_APC_3: 0x0
9966 22:59:19.134855 INFO: [APUAPC] D8_APC_0: 0xffffffff
9967 22:59:19.138789 INFO: [APUAPC] D8_APC_1: 0xffffffff
9968 22:59:19.141870 INFO: [APUAPC] D8_APC_2: 0x3fffff
9969 22:59:19.144892 INFO: [APUAPC] D8_APC_3: 0x0
9970 22:59:19.148633 INFO: [APUAPC] D9_APC_0: 0xffffffff
9971 22:59:19.151651 INFO: [APUAPC] D9_APC_1: 0xffffffff
9972 22:59:19.154878 INFO: [APUAPC] D9_APC_2: 0x3fffff
9973 22:59:19.158582 INFO: [APUAPC] D9_APC_3: 0x0
9974 22:59:19.161642 INFO: [APUAPC] D10_APC_0: 0xffffffff
9975 22:59:19.164799 INFO: [APUAPC] D10_APC_1: 0xffffffff
9976 22:59:19.168617 INFO: [APUAPC] D10_APC_2: 0x3fffff
9977 22:59:19.171596 INFO: [APUAPC] D10_APC_3: 0x0
9978 22:59:19.174722 INFO: [APUAPC] D11_APC_0: 0xffffffff
9979 22:59:19.178564 INFO: [APUAPC] D11_APC_1: 0xffffffff
9980 22:59:19.181655 INFO: [APUAPC] D11_APC_2: 0x3fffff
9981 22:59:19.184706 INFO: [APUAPC] D11_APC_3: 0x0
9982 22:59:19.188532 INFO: [APUAPC] D12_APC_0: 0xffffffff
9983 22:59:19.191687 INFO: [APUAPC] D12_APC_1: 0xffffffff
9984 22:59:19.195251 INFO: [APUAPC] D12_APC_2: 0x3fffff
9985 22:59:19.198176 INFO: [APUAPC] D12_APC_3: 0x0
9986 22:59:19.201841 INFO: [APUAPC] D13_APC_0: 0xffffffff
9987 22:59:19.204801 INFO: [APUAPC] D13_APC_1: 0xffffffff
9988 22:59:19.208593 INFO: [APUAPC] D13_APC_2: 0x3fffff
9989 22:59:19.211469 INFO: [APUAPC] D13_APC_3: 0x0
9990 22:59:19.215070 INFO: [APUAPC] D14_APC_0: 0xffffffff
9991 22:59:19.218185 INFO: [APUAPC] D14_APC_1: 0xffffffff
9992 22:59:19.221813 INFO: [APUAPC] D14_APC_2: 0x3fffff
9993 22:59:19.225328 INFO: [APUAPC] D14_APC_3: 0x0
9994 22:59:19.228482 INFO: [APUAPC] D15_APC_0: 0xffffffff
9995 22:59:19.231522 INFO: [APUAPC] D15_APC_1: 0xffffffff
9996 22:59:19.234673 INFO: [APUAPC] D15_APC_2: 0x3fffff
9997 22:59:19.238493 INFO: [APUAPC] D15_APC_3: 0x0
9998 22:59:19.241565 INFO: [APUAPC] APC_CON: 0x4
9999 22:59:19.244770 INFO: [NOCDAPC] D0_APC_0: 0x0
10000 22:59:19.247944 INFO: [NOCDAPC] D0_APC_1: 0x0
10001 22:59:19.251146 INFO: [NOCDAPC] D1_APC_0: 0x0
10002 22:59:19.251268 INFO: [NOCDAPC] D1_APC_1: 0xfff
10003 22:59:19.254803 INFO: [NOCDAPC] D2_APC_0: 0x0
10004 22:59:19.258076 INFO: [NOCDAPC] D2_APC_1: 0xfff
10005 22:59:19.261111 INFO: [NOCDAPC] D3_APC_0: 0x0
10006 22:59:19.264279 INFO: [NOCDAPC] D3_APC_1: 0xfff
10007 22:59:19.267776 INFO: [NOCDAPC] D4_APC_0: 0x0
10008 22:59:19.270917 INFO: [NOCDAPC] D4_APC_1: 0xfff
10009 22:59:19.274893 INFO: [NOCDAPC] D5_APC_0: 0x0
10010 22:59:19.277657 INFO: [NOCDAPC] D5_APC_1: 0xfff
10011 22:59:19.280935 INFO: [NOCDAPC] D6_APC_0: 0x0
10012 22:59:19.284089 INFO: [NOCDAPC] D6_APC_1: 0xfff
10013 22:59:19.284199 INFO: [NOCDAPC] D7_APC_0: 0x0
10014 22:59:19.287778 INFO: [NOCDAPC] D7_APC_1: 0xfff
10015 22:59:19.290829 INFO: [NOCDAPC] D8_APC_0: 0x0
10016 22:59:19.294067 INFO: [NOCDAPC] D8_APC_1: 0xfff
10017 22:59:19.297296 INFO: [NOCDAPC] D9_APC_0: 0x0
10018 22:59:19.300704 INFO: [NOCDAPC] D9_APC_1: 0xfff
10019 22:59:19.304250 INFO: [NOCDAPC] D10_APC_0: 0x0
10020 22:59:19.307291 INFO: [NOCDAPC] D10_APC_1: 0xfff
10021 22:59:19.311100 INFO: [NOCDAPC] D11_APC_0: 0x0
10022 22:59:19.314232 INFO: [NOCDAPC] D11_APC_1: 0xfff
10023 22:59:19.317669 INFO: [NOCDAPC] D12_APC_0: 0x0
10024 22:59:19.320677 INFO: [NOCDAPC] D12_APC_1: 0xfff
10025 22:59:19.324193 INFO: [NOCDAPC] D13_APC_0: 0x0
10026 22:59:19.327903 INFO: [NOCDAPC] D13_APC_1: 0xfff
10027 22:59:19.328023 INFO: [NOCDAPC] D14_APC_0: 0x0
10028 22:59:19.330971 INFO: [NOCDAPC] D14_APC_1: 0xfff
10029 22:59:19.334049 INFO: [NOCDAPC] D15_APC_0: 0x0
10030 22:59:19.337195 INFO: [NOCDAPC] D15_APC_1: 0xfff
10031 22:59:19.341055 INFO: [NOCDAPC] APC_CON: 0x4
10032 22:59:19.344077 INFO: [APUAPC] set_apusys_apc done
10033 22:59:19.347256 INFO: [DEVAPC] devapc_init done
10034 22:59:19.350565 INFO: GICv3 without legacy support detected.
10035 22:59:19.357123 INFO: ARM GICv3 driver initialized in EL3
10036 22:59:19.360878 INFO: Maximum SPI INTID supported: 639
10037 22:59:19.364004 INFO: BL31: Initializing runtime services
10038 22:59:19.370449 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10039 22:59:19.370570 INFO: SPM: enable CPC mode
10040 22:59:19.377131 INFO: mcdi ready for mcusys-off-idle and system suspend
10041 22:59:19.380730 INFO: BL31: Preparing for EL3 exit to normal world
10042 22:59:19.387044 INFO: Entry point address = 0x80000000
10043 22:59:19.387138 INFO: SPSR = 0x8
10044 22:59:19.393060
10045 22:59:19.393156
10046 22:59:19.393225
10047 22:59:19.396786 Starting depthcharge on Spherion...
10048 22:59:19.396875
10049 22:59:19.396944 Wipe memory regions:
10050 22:59:19.397010
10051 22:59:19.397679 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10052 22:59:19.397791 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10053 22:59:19.397881 Setting prompt string to ['asurada:']
10054 22:59:19.397963 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10055 22:59:19.400066 [0x00000040000000, 0x00000054600000)
10056 22:59:19.522493
10057 22:59:19.522762 [0x00000054660000, 0x00000080000000)
10058 22:59:19.782599
10059 22:59:19.782754 [0x000000821a7280, 0x000000ffe64000)
10060 22:59:20.527914
10061 22:59:20.528132 [0x00000100000000, 0x00000240000000)
10062 22:59:22.417674
10063 22:59:22.420634 Initializing XHCI USB controller at 0x11200000.
10064 22:59:23.459950
10065 22:59:23.462873 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10066 22:59:23.462975
10067 22:59:23.463043
10068 22:59:23.463107
10069 22:59:23.463399 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10071 22:59:23.563745 asurada: tftpboot 192.168.201.1 10597696/tftp-deploy-ndc77cb0/kernel/image.itb 10597696/tftp-deploy-ndc77cb0/kernel/cmdline
10072 22:59:23.563933 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10073 22:59:23.564033 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10074 22:59:23.567845 tftpboot 192.168.201.1 10597696/tftp-deploy-ndc77cb0/kernel/image.ittp-deploy-ndc77cb0/kernel/cmdline
10075 22:59:23.567936
10076 22:59:23.568004 Waiting for link
10077 22:59:23.728591
10078 22:59:23.728772 R8152: Initializing
10079 22:59:23.728868
10080 22:59:23.731725 Version 6 (ocp_data = 5c30)
10081 22:59:23.731853
10082 22:59:23.735039 R8152: Done initializing
10083 22:59:23.735122
10084 22:59:23.735188 Adding net device
10085 22:59:25.606619
10086 22:59:25.606763 done.
10087 22:59:25.606836
10088 22:59:25.606909 MAC: 00:24:32:30:78:52
10089 22:59:25.606972
10090 22:59:25.609721 Sending DHCP discover... done.
10091 22:59:25.609808
10092 22:59:29.315163 Waiting for reply... done.
10093 22:59:29.315344
10094 22:59:29.315453 Sending DHCP request... done.
10095 22:59:29.318778
10096 22:59:29.323028 Waiting for reply... done.
10097 22:59:29.323111
10098 22:59:29.323176 My ip is 192.168.201.14
10099 22:59:29.323236
10100 22:59:29.326155 The DHCP server ip is 192.168.201.1
10101 22:59:29.326238
10102 22:59:29.332517 TFTP server IP predefined by user: 192.168.201.1
10103 22:59:29.332629
10104 22:59:29.339425 Bootfile predefined by user: 10597696/tftp-deploy-ndc77cb0/kernel/image.itb
10105 22:59:29.339509
10106 22:59:29.339574 Sending tftp read request... done.
10107 22:59:29.342590
10108 22:59:29.346536 Waiting for the transfer...
10109 22:59:29.346623
10110 22:59:29.949173 00000000 ################################################################
10111 22:59:29.949323
10112 22:59:30.536583 00080000 ################################################################
10113 22:59:30.536756
10114 22:59:31.121674 00100000 ################################################################
10115 22:59:31.121820
10116 22:59:31.707172 00180000 ################################################################
10117 22:59:31.707318
10118 22:59:32.292897 00200000 ################################################################
10119 22:59:32.293041
10120 22:59:32.872468 00280000 ################################################################
10121 22:59:32.872604
10122 22:59:33.479546 00300000 ################################################################
10123 22:59:33.479719
10124 22:59:34.066908 00380000 ################################################################
10125 22:59:34.067093
10126 22:59:34.661431 00400000 ################################################################
10127 22:59:34.661578
10128 22:59:35.268218 00480000 ################################################################
10129 22:59:35.268400
10130 22:59:35.834144 00500000 ################################################################
10131 22:59:35.834295
10132 22:59:36.406153 00580000 ################################################################
10133 22:59:36.406313
10134 22:59:36.987985 00600000 ################################################################
10135 22:59:36.988138
10136 22:59:37.553048 00680000 ################################################################
10137 22:59:37.553199
10138 22:59:38.124872 00700000 ################################################################
10139 22:59:38.125043
10140 22:59:38.697774 00780000 ################################################################
10141 22:59:38.697950
10142 22:59:39.275590 00800000 ################################################################
10143 22:59:39.275754
10144 22:59:39.906579 00880000 ################################################################
10145 22:59:39.906720
10146 22:59:40.563652 00900000 ################################################################
10147 22:59:40.563805
10148 22:59:41.223009 00980000 ################################################################
10149 22:59:41.223175
10150 22:59:41.834085 00a00000 ################################################################
10151 22:59:41.834244
10152 22:59:42.403677 00a80000 ################################################################
10153 22:59:42.403829
10154 22:59:42.983247 00b00000 ################################################################
10155 22:59:42.983427
10156 22:59:43.535162 00b80000 ################################################################
10157 22:59:43.535303
10158 22:59:44.081579 00c00000 ################################################################
10159 22:59:44.081730
10160 22:59:44.618622 00c80000 ################################################################
10161 22:59:44.618803
10162 22:59:45.152612 00d00000 ################################################################
10163 22:59:45.152789
10164 22:59:45.691749 00d80000 ################################################################
10165 22:59:45.691932
10166 22:59:46.233045 00e00000 ################################################################
10167 22:59:46.233206
10168 22:59:46.773632 00e80000 ################################################################
10169 22:59:46.773783
10170 22:59:47.311868 00f00000 ################################################################
10171 22:59:47.312062
10172 22:59:47.852194 00f80000 ################################################################
10173 22:59:47.852345
10174 22:59:48.397656 01000000 ################################################################
10175 22:59:48.397836
10176 22:59:48.930051 01080000 ################################################################
10177 22:59:48.930230
10178 22:59:49.463540 01100000 ################################################################
10179 22:59:49.463741
10180 22:59:49.999538 01180000 ################################################################
10181 22:59:49.999697
10182 22:59:50.536409 01200000 ################################################################
10183 22:59:50.536564
10184 22:59:51.088598 01280000 ################################################################
10185 22:59:51.088764
10186 22:59:51.634559 01300000 ################################################################
10187 22:59:51.634740
10188 22:59:52.181588 01380000 ################################################################
10189 22:59:52.181739
10190 22:59:52.747635 01400000 ################################################################
10191 22:59:52.747823
10192 22:59:53.305244 01480000 ################################################################
10193 22:59:53.305402
10194 22:59:53.846476 01500000 ################################################################
10195 22:59:53.846636
10196 22:59:54.378134 01580000 ################################################################
10197 22:59:54.378319
10198 22:59:54.902692 01600000 ################################################################
10199 22:59:54.902869
10200 22:59:55.435810 01680000 ################################################################
10201 22:59:55.435962
10202 22:59:55.982191 01700000 ################################################################
10203 22:59:55.982350
10204 22:59:56.524917 01780000 ################################################################
10205 22:59:56.525072
10206 22:59:57.043335 01800000 ################################################################
10207 22:59:57.043494
10208 22:59:57.584962 01880000 ################################################################
10209 22:59:57.585110
10210 22:59:58.163322 01900000 ################################################################
10211 22:59:58.163542
10212 22:59:58.713986 01980000 ################################################################
10213 22:59:58.714149
10214 22:59:59.237133 01a00000 ################################################################
10215 22:59:59.237273
10216 22:59:59.760901 01a80000 ################################################################
10217 22:59:59.761071
10218 23:00:00.296593 01b00000 ################################################################
10219 23:00:00.296747
10220 23:00:00.821089 01b80000 ################################################################
10221 23:00:00.821238
10222 23:00:01.362610 01c00000 ################################################################
10223 23:00:01.362786
10224 23:00:01.884447 01c80000 ################################################################
10225 23:00:01.884616
10226 23:00:02.409664 01d00000 ################################################################
10227 23:00:02.409852
10228 23:00:02.990775 01d80000 ################################################################
10229 23:00:02.990965
10230 23:00:03.564890 01e00000 ################################################################
10231 23:00:03.565049
10232 23:00:04.110061 01e80000 ################################################################
10233 23:00:04.110244
10234 23:00:04.641534 01f00000 ################################################################
10235 23:00:04.641725
10236 23:00:05.215573 01f80000 ################################################################
10237 23:00:05.215726
10238 23:00:05.744664 02000000 ################################################################
10239 23:00:05.744819
10240 23:00:06.295249 02080000 ################################################################
10241 23:00:06.295411
10242 23:00:06.824394 02100000 ################################################################
10243 23:00:06.824640
10244 23:00:07.349774 02180000 ################################################################
10245 23:00:07.349968
10246 23:00:07.864532 02200000 ################################################################
10247 23:00:07.864786
10248 23:00:08.411540 02280000 ################################################################
10249 23:00:08.411748
10250 23:00:08.936340 02300000 ################################################################
10251 23:00:08.936503
10252 23:00:09.480938 02380000 ################################################################
10253 23:00:09.481125
10254 23:00:10.011492 02400000 ################################################################
10255 23:00:10.011660
10256 23:00:10.530036 02480000 ################################################################
10257 23:00:10.530177
10258 23:00:11.060651 02500000 ################################################################
10259 23:00:11.060809
10260 23:00:11.599745 02580000 ################################################################
10261 23:00:11.599897
10262 23:00:12.140062 02600000 ################################################################
10263 23:00:12.140213
10264 23:00:12.665179 02680000 ################################################################
10265 23:00:12.665335
10266 23:00:13.190019 02700000 ################################################################
10267 23:00:13.190173
10268 23:00:13.708234 02780000 ################################################################
10269 23:00:13.708397
10270 23:00:14.249376 02800000 ################################################################
10271 23:00:14.249540
10272 23:00:14.790442 02880000 ################################################################
10273 23:00:14.790601
10274 23:00:15.314353 02900000 ################################################################
10275 23:00:15.314503
10276 23:00:15.857008 02980000 ################################################################
10277 23:00:15.857162
10278 23:00:16.402220 02a00000 ################################################################
10279 23:00:16.402370
10280 23:00:16.930301 02a80000 ################################################################
10281 23:00:16.930483
10282 23:00:17.452782 02b00000 ################################################################
10283 23:00:17.452945
10284 23:00:17.968696 02b80000 ################################################################
10285 23:00:17.968879
10286 23:00:18.492206 02c00000 ################################################################
10287 23:00:18.492391
10288 23:00:19.014542 02c80000 ################################################################
10289 23:00:19.014707
10290 23:00:19.539982 02d00000 ################################################################
10291 23:00:19.540139
10292 23:00:20.066255 02d80000 ################################################################
10293 23:00:20.066471
10294 23:00:20.595037 02e00000 ################################################################
10295 23:00:20.595220
10296 23:00:21.117709 02e80000 ################################################################
10297 23:00:21.117887
10298 23:00:21.637889 02f00000 ################################################################
10299 23:00:21.638071
10300 23:00:22.168962 02f80000 ################################################################
10301 23:00:22.169131
10302 23:00:22.691005 03000000 ################################################################
10303 23:00:22.691160
10304 23:00:23.203722 03080000 ################################################################
10305 23:00:23.203904
10306 23:00:23.720242 03100000 ################################################################
10307 23:00:23.720403
10308 23:00:24.248251 03180000 ################################################################
10309 23:00:24.248439
10310 23:00:24.768066 03200000 ################################################################
10311 23:00:24.768246
10312 23:00:25.298055 03280000 ################################################################
10313 23:00:25.298207
10314 23:00:25.821508 03300000 ################################################################
10315 23:00:25.821653
10316 23:00:26.372781 03380000 ################################################################
10317 23:00:26.372971
10318 23:00:26.917624 03400000 ################################################################
10319 23:00:26.917816
10320 23:00:27.461031 03480000 ################################################################
10321 23:00:27.461201
10322 23:00:27.991056 03500000 ################################################################
10323 23:00:27.991240
10324 23:00:28.521560 03580000 ################################################################
10325 23:00:28.521714
10326 23:00:29.041253 03600000 ################################################################
10327 23:00:29.041439
10328 23:00:29.567421 03680000 ################################################################
10329 23:00:29.567573
10330 23:00:30.089378 03700000 ################################################################
10331 23:00:30.089536
10332 23:00:30.624325 03780000 ################################################################
10333 23:00:30.624482
10334 23:00:31.144216 03800000 ################################################################
10335 23:00:31.144371
10336 23:00:31.677840 03880000 ################################################################
10337 23:00:31.678015
10338 23:00:32.219567 03900000 ################################################################
10339 23:00:32.219702
10340 23:00:32.760648 03980000 ################################################################
10341 23:00:32.760805
10342 23:00:33.288377 03a00000 ################################################################
10343 23:00:33.288525
10344 23:00:33.859555 03a80000 ################################################################
10345 23:00:33.859711
10346 23:00:34.442992 03b00000 ################################################################
10347 23:00:34.443207
10348 23:00:35.001861 03b80000 ################################################################
10349 23:00:35.002046
10350 23:00:35.551915 03c00000 ################################################################
10351 23:00:35.552077
10352 23:00:36.096098 03c80000 ################################################################
10353 23:00:36.096250
10354 23:00:36.628596 03d00000 ################################################################
10355 23:00:36.628751
10356 23:00:37.178924 03d80000 ################################################################
10357 23:00:37.179081
10358 23:00:37.746791 03e00000 ################################################################
10359 23:00:37.746946
10360 23:00:38.273909 03e80000 ################################################################
10361 23:00:38.274067
10362 23:00:38.796859 03f00000 ################################################################
10363 23:00:38.797008
10364 23:00:39.430117 03f80000 ################################################################
10365 23:00:39.430274
10366 23:00:39.996581 04000000 ################################################################
10367 23:00:39.996738
10368 23:00:40.529611 04080000 ################################################################
10369 23:00:40.529762
10370 23:00:41.071331 04100000 ################################################################
10371 23:00:41.071495
10372 23:00:41.634769 04180000 ################################################################
10373 23:00:41.634930
10374 23:00:42.193447 04200000 ################################################################
10375 23:00:42.193605
10376 23:00:42.754123 04280000 ################################################################
10377 23:00:42.754280
10378 23:00:43.317765 04300000 ################################################################
10379 23:00:43.317919
10380 23:00:43.863048 04380000 ################################################################
10381 23:00:43.863203
10382 23:00:44.414447 04400000 ################################################################
10383 23:00:44.414628
10384 23:00:44.930897 04480000 ################################################################
10385 23:00:44.931075
10386 23:00:45.459249 04500000 ################################################################
10387 23:00:45.459439
10388 23:00:46.024662 04580000 ################################################################
10389 23:00:46.024840
10390 23:00:46.538309 04600000 ################################################################
10391 23:00:46.538513
10392 23:00:47.082780 04680000 ################################################################
10393 23:00:47.082934
10394 23:00:47.648931 04700000 ################################################################
10395 23:00:47.649098
10396 23:00:48.203264 04780000 ################################################################
10397 23:00:48.203470
10398 23:00:48.744840 04800000 ################################################################
10399 23:00:48.744993
10400 23:00:49.295220 04880000 ################################################################
10401 23:00:49.295435
10402 23:00:49.825074 04900000 ################################################################
10403 23:00:49.825216
10404 23:00:50.370089 04980000 ################################################################
10405 23:00:50.370236
10406 23:00:50.930492 04a00000 ################################################################
10407 23:00:50.930637
10408 23:00:51.476581 04a80000 ################################################################
10409 23:00:51.476735
10410 23:00:52.043489 04b00000 ################################################################
10411 23:00:52.043644
10412 23:00:52.592988 04b80000 ################################################################
10413 23:00:52.593127
10414 23:00:53.141006 04c00000 ################################################################
10415 23:00:53.141153
10416 23:00:53.700559 04c80000 ################################################################
10417 23:00:53.700733
10418 23:00:54.251423 04d00000 ################################################################
10419 23:00:54.251573
10420 23:00:54.787051 04d80000 ################################################################
10421 23:00:54.787206
10422 23:00:55.322357 04e00000 ################################################################
10423 23:00:55.322504
10424 23:00:55.860113 04e80000 ################################################################
10425 23:00:55.860265
10426 23:00:56.397135 04f00000 ################################################################
10427 23:00:56.397281
10428 23:00:56.943870 04f80000 ################################################################
10429 23:00:56.944047
10430 23:00:57.469824 05000000 ################################################################
10431 23:00:57.469969
10432 23:00:58.013891 05080000 ################################################################
10433 23:00:58.014037
10434 23:00:58.565444 05100000 ################################################################
10435 23:00:58.565600
10436 23:00:59.098147 05180000 ################################################################
10437 23:00:59.098332
10438 23:00:59.645879 05200000 ################################################################
10439 23:00:59.646064
10440 23:01:00.170576 05280000 ################################################################
10441 23:01:00.170757
10442 23:01:00.713714 05300000 ################################################################
10443 23:01:00.713887
10444 23:01:01.260707 05380000 ################################################################
10445 23:01:01.260882
10446 23:01:01.809117 05400000 ################################################################
10447 23:01:01.809266
10448 23:01:02.355332 05480000 ################################################################
10449 23:01:02.355524
10450 23:01:02.907238 05500000 ################################################################
10451 23:01:02.907447
10452 23:01:03.440281 05580000 ################################################################
10453 23:01:03.440435
10454 23:01:03.979493 05600000 ################################################################
10455 23:01:03.979726
10456 23:01:04.524795 05680000 ################################################################
10457 23:01:04.524949
10458 23:01:05.073946 05700000 ################################################################
10459 23:01:05.074102
10460 23:01:05.615412 05780000 ################################################################
10461 23:01:05.615628
10462 23:01:06.167227 05800000 ################################################################
10463 23:01:06.167405
10464 23:01:06.709764 05880000 ################################################################
10465 23:01:06.709919
10466 23:01:07.254317 05900000 ################################################################
10467 23:01:07.254464
10468 23:01:07.801181 05980000 ################################################################
10469 23:01:07.801340
10470 23:01:08.348325 05a00000 ################################################################
10471 23:01:08.348480
10472 23:01:08.886742 05a80000 ################################################################
10473 23:01:08.886897
10474 23:01:09.423931 05b00000 ################################################################
10475 23:01:09.424084
10476 23:01:09.973221 05b80000 ################################################################
10477 23:01:09.973376
10478 23:01:10.517001 05c00000 ################################################################
10479 23:01:10.517155
10480 23:01:11.071816 05c80000 ################################################################
10481 23:01:11.071993
10482 23:01:11.610301 05d00000 ################################################################
10483 23:01:11.610464
10484 23:01:12.144523 05d80000 ################################################################
10485 23:01:12.144681
10486 23:01:12.667535 05e00000 ################################################################
10487 23:01:12.667701
10488 23:01:13.204515 05e80000 ################################################################
10489 23:01:13.204679
10490 23:01:13.731579 05f00000 ################################################################
10491 23:01:13.731741
10492 23:01:14.250215 05f80000 ################################################################
10493 23:01:14.250404
10494 23:01:14.805539 06000000 ################################################################
10495 23:01:14.805696
10496 23:01:15.440568 06080000 ################################################################
10497 23:01:15.440722
10498 23:01:15.963220 06100000 ################################################################
10499 23:01:15.963400
10500 23:01:16.501500 06180000 ################################################################
10501 23:01:16.501664
10502 23:01:17.031758 06200000 ################################################################
10503 23:01:17.031987
10504 23:01:17.561944 06280000 ################################################################
10505 23:01:17.562153
10506 23:01:18.102002 06300000 ################################################################
10507 23:01:18.102215
10508 23:01:18.639593 06380000 ################################################################
10509 23:01:18.639804
10510 23:01:19.171969 06400000 ################################################################
10511 23:01:19.172141
10512 23:01:19.706804 06480000 ################################################################
10513 23:01:19.706955
10514 23:01:20.240873 06500000 ################################################################
10515 23:01:20.241058
10516 23:01:20.772649 06580000 ################################################################
10517 23:01:20.772800
10518 23:01:21.310139 06600000 ################################################################
10519 23:01:21.310314
10520 23:01:21.830768 06680000 ################################################################
10521 23:01:21.830951
10522 23:01:22.113712 06700000 ################################### done.
10523 23:01:22.113871
10524 23:01:22.116991 The bootfile was 108287838 bytes long.
10525 23:01:22.117110
10526 23:01:22.119863 Sending tftp read request... done.
10527 23:01:22.120013
10528 23:01:22.120087 Waiting for the transfer...
10529 23:01:22.123502
10530 23:01:22.123607 00000000 # done.
10531 23:01:22.123683
10532 23:01:22.130026 Command line loaded dynamically from TFTP file: 10597696/tftp-deploy-ndc77cb0/kernel/cmdline
10533 23:01:22.130159
10534 23:01:22.143399 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10535 23:01:22.143554
10536 23:01:22.143636 Loading FIT.
10537 23:01:22.143702
10538 23:01:22.146698 Image ramdisk-1 has 98152934 bytes.
10539 23:01:22.146816
10540 23:01:22.149827 Image fdt-1 has 46924 bytes.
10541 23:01:22.149924
10542 23:01:22.153347 Image kernel-1 has 10085945 bytes.
10543 23:01:22.153442
10544 23:01:22.159931 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10545 23:01:22.162995
10546 23:01:22.180048 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10547 23:01:22.180238
10548 23:01:22.183498 Choosing best match conf-1 for compat google,spherion-rev2.
10549 23:01:22.188610
10550 23:01:22.192889 Connected to device vid:did:rid of 1ae0:0028:00
10551 23:01:22.199804
10552 23:01:22.203216 tpm_get_response: command 0x17b, return code 0x0
10553 23:01:22.203346
10554 23:01:22.206176 ec_init: CrosEC protocol v3 supported (256, 248)
10555 23:01:22.210824
10556 23:01:22.214327 tpm_cleanup: add release locality here.
10557 23:01:22.214426
10558 23:01:22.214516 Shutting down all USB controllers.
10559 23:01:22.217282
10560 23:01:22.217373 Removing current net device
10561 23:01:22.217463
10562 23:01:22.224148 Exiting depthcharge with code 4 at timestamp: 152229928
10563 23:01:22.224269
10564 23:01:22.227179 LZMA decompressing kernel-1 to 0x821a6718
10565 23:01:22.227278
10566 23:01:22.230689 LZMA decompressing kernel-1 to 0x40000000
10567 23:01:23.497526
10568 23:01:23.497698 jumping to kernel
10569 23:01:23.498521 end: 2.2.4 bootloader-commands (duration 00:02:04) [common]
10570 23:01:23.498629 start: 2.2.5 auto-login-action (timeout 00:02:21) [common]
10571 23:01:23.498713 Setting prompt string to ['Linux version [0-9]']
10572 23:01:23.498787 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10573 23:01:23.498858 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10574 23:01:23.578990
10575 23:01:23.582358 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10576 23:01:23.586092 start: 2.2.5.1 login-action (timeout 00:02:21) [common]
10577 23:01:23.586210 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10578 23:01:23.586332 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10579 23:01:23.586440 Using line separator: #'\n'#
10580 23:01:23.586534 No login prompt set.
10581 23:01:23.586628 Parsing kernel messages
10582 23:01:23.586717 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10583 23:01:23.586896 [login-action] Waiting for messages, (timeout 00:02:21)
10584 23:01:23.605746 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j1612582-arm64-gcc-10-defconfig-arm64-chromebook-7xwc5) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Jun 5 22:41:02 UTC 2023
10585 23:01:23.609161 [ 0.000000] random: crng init done
10586 23:01:23.612181 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10587 23:01:23.615772 [ 0.000000] efi: UEFI not found.
10588 23:01:23.625568 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10589 23:01:23.632258 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10590 23:01:23.642144 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10591 23:01:23.652115 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10592 23:01:23.658755 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10593 23:01:23.662148 [ 0.000000] printk: bootconsole [mtk8250] enabled
10594 23:01:23.670314 [ 0.000000] NUMA: No NUMA configuration found
10595 23:01:23.677301 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10596 23:01:23.683400 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcda00-0x23efcffff]
10597 23:01:23.683497 [ 0.000000] Zone ranges:
10598 23:01:23.690195 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10599 23:01:23.693713 [ 0.000000] DMA32 empty
10600 23:01:23.700305 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10601 23:01:23.703448 [ 0.000000] Movable zone start for each node
10602 23:01:23.706462 [ 0.000000] Early memory node ranges
10603 23:01:23.713126 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10604 23:01:23.719900 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10605 23:01:23.726608 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10606 23:01:23.733136 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10607 23:01:23.739813 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10608 23:01:23.746501 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10609 23:01:23.802954 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10610 23:01:23.809649 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10611 23:01:23.816225 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10612 23:01:23.819787 [ 0.000000] psci: probing for conduit method from DT.
10613 23:01:23.826513 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10614 23:01:23.829544 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10615 23:01:23.836394 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10616 23:01:23.839430 [ 0.000000] psci: SMC Calling Convention v1.2
10617 23:01:23.846136 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10618 23:01:23.849188 [ 0.000000] Detected VIPT I-cache on CPU0
10619 23:01:23.856008 [ 0.000000] CPU features: detected: GIC system register CPU interface
10620 23:01:23.862755 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10621 23:01:23.869346 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10622 23:01:23.876301 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10623 23:01:23.882894 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10624 23:01:23.892636 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10625 23:01:23.896083 [ 0.000000] alternatives: applying boot alternatives
10626 23:01:23.902344 [ 0.000000] Fallback order for Node 0: 0
10627 23:01:23.908976 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10628 23:01:23.913279 [ 0.000000] Policy zone: Normal
10629 23:01:23.922315 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10630 23:01:23.932708 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10631 23:01:23.945349 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10632 23:01:23.955297 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10633 23:01:23.961692 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10634 23:01:23.965298 <6>[ 0.000000] software IO TLB: area num 8.
10635 23:01:24.021729 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10636 23:01:24.170193 <6>[ 0.000000] Memory: 7877088K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 475680K reserved, 32768K cma-reserved)
10637 23:01:24.177099 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10638 23:01:24.183498 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10639 23:01:24.186974 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10640 23:01:24.193614 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10641 23:01:24.200155 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10642 23:01:24.203336 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10643 23:01:24.213599 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10644 23:01:24.220182 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10645 23:01:24.226643 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10646 23:01:24.233565 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10647 23:01:24.236625 <6>[ 0.000000] GICv3: 608 SPIs implemented
10648 23:01:24.239600 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10649 23:01:24.246322 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10650 23:01:24.249883 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10651 23:01:24.256662 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10652 23:01:24.269754 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10653 23:01:24.280175 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10654 23:01:24.289939 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10655 23:01:24.297177 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10656 23:01:24.310289 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10657 23:01:24.317071 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10658 23:01:24.323510 <6>[ 0.009182] Console: colour dummy device 80x25
10659 23:01:24.333693 <6>[ 0.013909] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10660 23:01:24.340392 <6>[ 0.024351] pid_max: default: 32768 minimum: 301
10661 23:01:24.343595 <6>[ 0.029224] LSM: Security Framework initializing
10662 23:01:24.350239 <6>[ 0.034163] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10663 23:01:24.359964 <6>[ 0.041996] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10664 23:01:24.366796 <6>[ 0.051268] cblist_init_generic: Setting adjustable number of callback queues.
10665 23:01:24.373429 <6>[ 0.058722] cblist_init_generic: Setting shift to 3 and lim to 1.
10666 23:01:24.379916 <6>[ 0.065062] cblist_init_generic: Setting shift to 3 and lim to 1.
10667 23:01:24.386334 <6>[ 0.071470] rcu: Hierarchical SRCU implementation.
10668 23:01:24.389709 <6>[ 0.076485] rcu: Max phase no-delay instances is 1000.
10669 23:01:24.397820 <6>[ 0.083505] EFI services will not be available.
10670 23:01:24.400918 <6>[ 0.088506] smp: Bringing up secondary CPUs ...
10671 23:01:24.410040 <6>[ 0.093589] Detected VIPT I-cache on CPU1
10672 23:01:24.416992 <6>[ 0.093660] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10673 23:01:24.423469 <6>[ 0.093692] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10674 23:01:24.427056 <6>[ 0.094034] Detected VIPT I-cache on CPU2
10675 23:01:24.433563 <6>[ 0.094088] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10676 23:01:24.440245 <6>[ 0.094105] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10677 23:01:24.446593 <6>[ 0.094366] Detected VIPT I-cache on CPU3
10678 23:01:24.453307 <6>[ 0.094412] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10679 23:01:24.460017 <6>[ 0.094427] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10680 23:01:24.463423 <6>[ 0.094734] CPU features: detected: Spectre-v4
10681 23:01:24.469682 <6>[ 0.094741] CPU features: detected: Spectre-BHB
10682 23:01:24.473469 <6>[ 0.094747] Detected PIPT I-cache on CPU4
10683 23:01:24.480218 <6>[ 0.094803] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10684 23:01:24.486726 <6>[ 0.094820] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10685 23:01:24.493066 <6>[ 0.095115] Detected PIPT I-cache on CPU5
10686 23:01:24.499976 <6>[ 0.095177] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10687 23:01:24.506714 <6>[ 0.095194] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10688 23:01:24.509630 <6>[ 0.095476] Detected PIPT I-cache on CPU6
10689 23:01:24.516229 <6>[ 0.095540] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10690 23:01:24.523199 <6>[ 0.095557] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10691 23:01:24.529336 <6>[ 0.095857] Detected PIPT I-cache on CPU7
10692 23:01:24.536601 <6>[ 0.095922] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10693 23:01:24.542663 <6>[ 0.095938] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10694 23:01:24.546434 <6>[ 0.095985] smp: Brought up 1 node, 8 CPUs
10695 23:01:24.552483 <6>[ 0.237229] SMP: Total of 8 processors activated.
10696 23:01:24.556112 <6>[ 0.242181] CPU features: detected: 32-bit EL0 Support
10697 23:01:24.565791 <6>[ 0.247578] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10698 23:01:24.572492 <6>[ 0.256432] CPU features: detected: Common not Private translations
10699 23:01:24.575638 <6>[ 0.262907] CPU features: detected: CRC32 instructions
10700 23:01:24.582468 <6>[ 0.268259] CPU features: detected: RCpc load-acquire (LDAPR)
10701 23:01:24.588984 <6>[ 0.274219] CPU features: detected: LSE atomic instructions
10702 23:01:24.595842 <6>[ 0.280036] CPU features: detected: Privileged Access Never
10703 23:01:24.599163 <6>[ 0.285822] CPU features: detected: RAS Extension Support
10704 23:01:24.608680 <6>[ 0.291465] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10705 23:01:24.612290 <6>[ 0.298686] CPU: All CPU(s) started at EL2
10706 23:01:24.619053 <6>[ 0.303003] alternatives: applying system-wide alternatives
10707 23:01:24.628093 <6>[ 0.313738] devtmpfs: initialized
10708 23:01:24.643727 <6>[ 0.322594] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10709 23:01:24.649717 <6>[ 0.332556] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10710 23:01:24.656513 <6>[ 0.340803] pinctrl core: initialized pinctrl subsystem
10711 23:01:24.660221 <6>[ 0.347433] DMI not present or invalid.
10712 23:01:24.666680 <6>[ 0.351813] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10713 23:01:24.676390 <6>[ 0.358687] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10714 23:01:24.683230 <6>[ 0.366273] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10715 23:01:24.692803 <6>[ 0.374499] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10716 23:01:24.696420 <6>[ 0.382742] audit: initializing netlink subsys (disabled)
10717 23:01:24.706250 <5>[ 0.388436] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10718 23:01:24.712740 <6>[ 0.389133] thermal_sys: Registered thermal governor 'step_wise'
10719 23:01:24.719835 <6>[ 0.396401] thermal_sys: Registered thermal governor 'power_allocator'
10720 23:01:24.723059 <6>[ 0.402655] cpuidle: using governor menu
10721 23:01:24.729369 <6>[ 0.413614] NET: Registered PF_QIPCRTR protocol family
10722 23:01:24.736329 <6>[ 0.419063] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10723 23:01:24.739761 <6>[ 0.426163] ASID allocator initialised with 32768 entries
10724 23:01:24.747026 <6>[ 0.432717] Serial: AMBA PL011 UART driver
10725 23:01:24.755374 <4>[ 0.441313] Trying to register duplicate clock ID: 134
10726 23:01:24.809169 <6>[ 0.498359] KASLR enabled
10727 23:01:24.823319 <6>[ 0.506079] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10728 23:01:24.830114 <6>[ 0.513093] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10729 23:01:24.836509 <6>[ 0.519581] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10730 23:01:24.843108 <6>[ 0.526585] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10731 23:01:24.849705 <6>[ 0.533072] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10732 23:01:24.856766 <6>[ 0.540077] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10733 23:01:24.863325 <6>[ 0.546563] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10734 23:01:24.870194 <6>[ 0.553569] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10735 23:01:24.873292 <6>[ 0.561087] ACPI: Interpreter disabled.
10736 23:01:24.881801 <6>[ 0.567472] iommu: Default domain type: Translated
10737 23:01:24.888377 <6>[ 0.572585] iommu: DMA domain TLB invalidation policy: strict mode
10738 23:01:24.892003 <5>[ 0.579237] SCSI subsystem initialized
10739 23:01:24.898117 <6>[ 0.583401] usbcore: registered new interface driver usbfs
10740 23:01:24.904987 <6>[ 0.589134] usbcore: registered new interface driver hub
10741 23:01:24.908318 <6>[ 0.594687] usbcore: registered new device driver usb
10742 23:01:24.915006 <6>[ 0.600764] pps_core: LinuxPPS API ver. 1 registered
10743 23:01:24.924831 <6>[ 0.605959] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10744 23:01:24.928383 <6>[ 0.615309] PTP clock support registered
10745 23:01:24.931394 <6>[ 0.619551] EDAC MC: Ver: 3.0.0
10746 23:01:24.939047 <6>[ 0.624685] FPGA manager framework
10747 23:01:24.945399 <6>[ 0.628364] Advanced Linux Sound Architecture Driver Initialized.
10748 23:01:24.948769 <6>[ 0.635124] vgaarb: loaded
10749 23:01:24.955460 <6>[ 0.638293] clocksource: Switched to clocksource arch_sys_counter
10750 23:01:24.959183 <5>[ 0.644734] VFS: Disk quotas dquot_6.6.0
10751 23:01:24.965401 <6>[ 0.648915] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10752 23:01:24.968354 <6>[ 0.656107] pnp: PnP ACPI: disabled
10753 23:01:24.976905 <6>[ 0.662818] NET: Registered PF_INET protocol family
10754 23:01:24.986817 <6>[ 0.668417] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10755 23:01:24.998497 <6>[ 0.680719] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10756 23:01:25.008103 <6>[ 0.689535] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10757 23:01:25.014602 <6>[ 0.697506] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10758 23:01:25.024560 <6>[ 0.706201] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10759 23:01:25.031220 <6>[ 0.715945] TCP: Hash tables configured (established 65536 bind 65536)
10760 23:01:25.037815 <6>[ 0.722800] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10761 23:01:25.047234 <6>[ 0.729999] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10762 23:01:25.054506 <6>[ 0.737676] NET: Registered PF_UNIX/PF_LOCAL protocol family
10763 23:01:25.061041 <6>[ 0.743841] RPC: Registered named UNIX socket transport module.
10764 23:01:25.064143 <6>[ 0.749997] RPC: Registered udp transport module.
10765 23:01:25.070350 <6>[ 0.754931] RPC: Registered tcp transport module.
10766 23:01:25.077357 <6>[ 0.759862] RPC: Registered tcp NFSv4.1 backchannel transport module.
10767 23:01:25.080427 <6>[ 0.766530] PCI: CLS 0 bytes, default 64
10768 23:01:25.083481 <6>[ 0.770854] Unpacking initramfs...
10769 23:01:25.100603 <6>[ 0.782872] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10770 23:01:25.110432 <6>[ 0.791530] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10771 23:01:25.113378 <6>[ 0.800375] kvm [1]: IPA Size Limit: 40 bits
10772 23:01:25.120258 <6>[ 0.804907] kvm [1]: GICv3: no GICV resource entry
10773 23:01:25.123795 <6>[ 0.809929] kvm [1]: disabling GICv2 emulation
10774 23:01:25.130415 <6>[ 0.814618] kvm [1]: GIC system register CPU interface enabled
10775 23:01:25.133278 <6>[ 0.820786] kvm [1]: vgic interrupt IRQ18
10776 23:01:25.140488 <6>[ 0.825153] kvm [1]: VHE mode initialized successfully
10777 23:01:25.147199 <5>[ 0.831557] Initialise system trusted keyrings
10778 23:01:25.153391 <6>[ 0.836409] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10779 23:01:25.161147 <6>[ 0.846443] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10780 23:01:25.167582 <5>[ 0.852830] NFS: Registering the id_resolver key type
10781 23:01:25.170606 <5>[ 0.858132] Key type id_resolver registered
10782 23:01:25.177214 <5>[ 0.862546] Key type id_legacy registered
10783 23:01:25.184020 <6>[ 0.866826] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10784 23:01:25.190295 <6>[ 0.873748] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10785 23:01:25.196819 <6>[ 0.881460] 9p: Installing v9fs 9p2000 file system support
10786 23:01:25.234201 <5>[ 0.919657] Key type asymmetric registered
10787 23:01:25.237334 <5>[ 0.923989] Asymmetric key parser 'x509' registered
10788 23:01:25.246809 <6>[ 0.929135] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10789 23:01:25.250351 <6>[ 0.936752] io scheduler mq-deadline registered
10790 23:01:25.253739 <6>[ 0.941536] io scheduler kyber registered
10791 23:01:25.272450 <6>[ 0.958297] EINJ: ACPI disabled.
10792 23:01:25.304290 <4>[ 0.983308] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10793 23:01:25.314075 <4>[ 0.993934] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10794 23:01:25.328198 <6>[ 1.014266] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10795 23:01:25.336230 <6>[ 1.022209] printk: console [ttyS0] disabled
10796 23:01:25.364301 <6>[ 1.046857] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10797 23:01:25.371083 <6>[ 1.056327] printk: console [ttyS0] enabled
10798 23:01:25.374792 <6>[ 1.056327] printk: console [ttyS0] enabled
10799 23:01:25.381245 <6>[ 1.065223] printk: bootconsole [mtk8250] disabled
10800 23:01:25.384189 <6>[ 1.065223] printk: bootconsole [mtk8250] disabled
10801 23:01:25.390935 <6>[ 1.076204] SuperH (H)SCI(F) driver initialized
10802 23:01:25.394007 <6>[ 1.081468] msm_serial: driver initialized
10803 23:01:25.407528 <6>[ 1.090255] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10804 23:01:25.417781 <6>[ 1.098801] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10805 23:01:25.424375 <6>[ 1.107344] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10806 23:01:25.434428 <6>[ 1.115974] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10807 23:01:25.443919 <6>[ 1.124680] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10808 23:01:25.450718 <6>[ 1.133394] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10809 23:01:25.460897 <6>[ 1.141934] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10810 23:01:25.467398 <6>[ 1.150722] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10811 23:01:25.477258 <6>[ 1.159263] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10812 23:01:25.488175 <6>[ 1.174269] loop: module loaded
10813 23:01:25.494839 <6>[ 1.180213] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10814 23:01:25.517597 <4>[ 1.203180] mtk-pmic-keys: Failed to locate of_node [id: -1]
10815 23:01:25.523814 <6>[ 1.209774] megasas: 07.719.03.00-rc1
10816 23:01:25.533419 <6>[ 1.219379] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10817 23:01:25.540253 <6>[ 1.225680] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10818 23:01:25.556173 <6>[ 1.242126] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10819 23:01:25.616580 <6>[ 1.296245] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10820 23:01:29.054561 <6>[ 4.741103] Freeing initrd memory: 95848K
10821 23:01:29.065327 <6>[ 4.751456] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10822 23:01:29.076018 <6>[ 4.762329] tun: Universal TUN/TAP device driver, 1.6
10823 23:01:29.079664 <6>[ 4.768387] thunder_xcv, ver 1.0
10824 23:01:29.082792 <6>[ 4.771892] thunder_bgx, ver 1.0
10825 23:01:29.086295 <6>[ 4.775386] nicpf, ver 1.0
10826 23:01:29.096141 <6>[ 4.779387] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10827 23:01:29.099740 <6>[ 4.786862] hns3: Copyright (c) 2017 Huawei Corporation.
10828 23:01:29.106332 <6>[ 4.792448] hclge is initializing
10829 23:01:29.109374 <6>[ 4.796027] e1000: Intel(R) PRO/1000 Network Driver
10830 23:01:29.116344 <6>[ 4.801156] e1000: Copyright (c) 1999-2006 Intel Corporation.
10831 23:01:29.119282 <6>[ 4.807169] e1000e: Intel(R) PRO/1000 Network Driver
10832 23:01:29.125987 <6>[ 4.812384] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10833 23:01:29.132812 <6>[ 4.818572] igb: Intel(R) Gigabit Ethernet Network Driver
10834 23:01:29.139371 <6>[ 4.824221] igb: Copyright (c) 2007-2014 Intel Corporation.
10835 23:01:29.146090 <6>[ 4.830057] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10836 23:01:29.152932 <6>[ 4.836574] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10837 23:01:29.156015 <6>[ 4.843029] sky2: driver version 1.30
10838 23:01:29.162342 <6>[ 4.848008] VFIO - User Level meta-driver version: 0.3
10839 23:01:29.169945 <6>[ 4.856201] usbcore: registered new interface driver usb-storage
10840 23:01:29.176530 <6>[ 4.862644] usbcore: registered new device driver onboard-usb-hub
10841 23:01:29.185390 <6>[ 4.871734] mt6397-rtc mt6359-rtc: registered as rtc0
10842 23:01:29.195247 <6>[ 4.877219] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-05T23:01:34 UTC (1686006094)
10843 23:01:29.199000 <6>[ 4.886831] i2c_dev: i2c /dev entries driver
10844 23:01:29.215454 <6>[ 4.898444] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10845 23:01:29.222548 <6>[ 4.908591] sdhci: Secure Digital Host Controller Interface driver
10846 23:01:29.229149 <6>[ 4.915029] sdhci: Copyright(c) Pierre Ossman
10847 23:01:29.235281 <6>[ 4.920421] Synopsys Designware Multimedia Card Interface Driver
10848 23:01:29.238842 <6>[ 4.927051] mmc0: CQHCI version 5.10
10849 23:01:29.245615 <6>[ 4.927573] sdhci-pltfm: SDHCI platform and OF driver helper
10850 23:01:29.252996 <6>[ 4.939354] ledtrig-cpu: registered to indicate activity on CPUs
10851 23:01:29.263502 <6>[ 4.946716] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10852 23:01:29.267473 <6>[ 4.954111] usbcore: registered new interface driver usbhid
10853 23:01:29.273437 <6>[ 4.959944] usbhid: USB HID core driver
10854 23:01:29.280141 <6>[ 4.964190] spi_master spi0: will run message pump with realtime priority
10855 23:01:29.323081 <6>[ 5.002944] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10856 23:01:29.341453 <6>[ 5.018101] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10857 23:01:29.345062 <6>[ 5.031669] mmc0: Command Queue Engine enabled
10858 23:01:29.351838 <6>[ 5.036415] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10859 23:01:29.358465 <6>[ 5.043329] cros-ec-spi spi0.0: Chrome EC device registered
10860 23:01:29.361525 <6>[ 5.043674] mmcblk0: mmc0:0001 DA4128 116 GiB
10861 23:01:29.372690 <6>[ 5.059030] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10862 23:01:29.379975 <6>[ 5.066270] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10863 23:01:29.386510 <6>[ 5.072200] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10864 23:01:29.393129 <6>[ 5.078041] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10865 23:01:29.403534 <6>[ 5.085955] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10866 23:01:29.410936 <6>[ 5.097298] NET: Registered PF_PACKET protocol family
10867 23:01:29.417955 <6>[ 5.102732] 9pnet: Installing 9P2000 support
10868 23:01:29.420847 <5>[ 5.107308] Key type dns_resolver registered
10869 23:01:29.424527 <6>[ 5.112362] registered taskstats version 1
10870 23:01:29.430851 <5>[ 5.116758] Loading compiled-in X.509 certificates
10871 23:01:29.463683 <4>[ 5.143223] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10872 23:01:29.473782 <4>[ 5.153942] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10873 23:01:29.483786 <3>[ 5.166655] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10874 23:01:29.495727 <6>[ 5.182061] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10875 23:01:29.502379 <6>[ 5.188814] xhci-mtk 11200000.usb: xHCI Host Controller
10876 23:01:29.508915 <6>[ 5.194311] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10877 23:01:29.519054 <6>[ 5.202164] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10878 23:01:29.525626 <6>[ 5.211590] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10879 23:01:29.532332 <6>[ 5.217783] xhci-mtk 11200000.usb: xHCI Host Controller
10880 23:01:29.539066 <6>[ 5.223302] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10881 23:01:29.545416 <6>[ 5.230963] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10882 23:01:29.552800 <6>[ 5.238869] hub 1-0:1.0: USB hub found
10883 23:01:29.555769 <6>[ 5.242906] hub 1-0:1.0: 1 port detected
10884 23:01:29.566071 <6>[ 5.247253] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10885 23:01:29.569004 <6>[ 5.256093] hub 2-0:1.0: USB hub found
10886 23:01:29.572750 <6>[ 5.260130] hub 2-0:1.0: 1 port detected
10887 23:01:29.581604 <6>[ 5.267499] mtk-msdc 11f70000.mmc: Got CD GPIO
10888 23:01:29.597534 <6>[ 5.280534] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10889 23:01:29.603960 <6>[ 5.288570] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10890 23:01:29.614461 <4>[ 5.296537] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10891 23:01:29.623940 <6>[ 5.306205] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10892 23:01:29.630497 <6>[ 5.314288] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10893 23:01:29.637560 <6>[ 5.322323] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10894 23:01:29.647139 <6>[ 5.330245] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10895 23:01:29.653710 <6>[ 5.338067] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10896 23:01:29.663892 <6>[ 5.345888] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10897 23:01:29.673749 <6>[ 5.356540] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10898 23:01:29.680175 <6>[ 5.364906] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10899 23:01:29.690300 <6>[ 5.373257] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10900 23:01:29.699924 <6>[ 5.381610] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10901 23:01:29.706560 <6>[ 5.389953] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10902 23:01:29.716403 <6>[ 5.398296] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10903 23:01:29.723108 <6>[ 5.406639] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10904 23:01:29.732974 <6>[ 5.414982] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10905 23:01:29.739700 <6>[ 5.423325] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10906 23:01:29.750061 <6>[ 5.431668] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10907 23:01:29.756177 <6>[ 5.440011] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10908 23:01:29.765914 <6>[ 5.448354] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10909 23:01:29.772634 <6>[ 5.456698] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10910 23:01:29.782792 <6>[ 5.465040] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10911 23:01:29.789312 <6>[ 5.473392] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10912 23:01:29.795854 <6>[ 5.482295] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10913 23:01:29.803440 <6>[ 5.489689] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10914 23:01:29.810473 <6>[ 5.496734] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10915 23:01:29.820974 <6>[ 5.503851] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10916 23:01:29.827519 <6>[ 5.511141] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10917 23:01:29.837398 <6>[ 5.518040] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10918 23:01:29.843994 <6>[ 5.527181] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10919 23:01:29.853910 <6>[ 5.536309] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10920 23:01:29.863721 <6>[ 5.545611] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10921 23:01:29.873971 <6>[ 5.555086] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10922 23:01:29.883519 <6>[ 5.564560] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10923 23:01:29.890127 <6>[ 5.573687] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10924 23:01:29.899996 <6>[ 5.583163] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10925 23:01:29.909907 <6>[ 5.592294] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10926 23:01:29.920230 <6>[ 5.601595] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10927 23:01:29.930081 <6>[ 5.611761] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10928 23:01:29.940173 <6>[ 5.623096] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10929 23:01:29.963317 <6>[ 5.646574] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10930 23:01:29.991304 <6>[ 5.677106] hub 2-1:1.0: USB hub found
10931 23:01:29.994441 <6>[ 5.681501] hub 2-1:1.0: 3 ports detected
10932 23:01:30.115135 <6>[ 5.798474] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10933 23:01:30.269719 <6>[ 5.955986] hub 1-1:1.0: USB hub found
10934 23:01:30.272837 <6>[ 5.960438] hub 1-1:1.0: 4 ports detected
10935 23:01:30.347814 <6>[ 6.030815] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10936 23:01:30.595235 <6>[ 6.278571] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10937 23:01:30.728740 <6>[ 6.414861] hub 1-1.4:1.0: USB hub found
10938 23:01:30.731669 <6>[ 6.419519] hub 1-1.4:1.0: 2 ports detected
10939 23:01:31.027728 <6>[ 6.710564] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10940 23:01:31.219364 <6>[ 6.902604] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10941 23:01:42.240285 <6>[ 17.931221] ALSA device list:
10942 23:01:42.246417 <6>[ 17.934476] No soundcards found.
10943 23:01:42.259305 <6>[ 17.946889] Freeing unused kernel memory: 8384K
10944 23:01:42.262210 <6>[ 17.951814] Run /init as init process
10945 23:01:42.292151 <6>[ 17.980139] NET: Registered PF_INET6 protocol family
10946 23:01:42.298646 <6>[ 17.986225] Segment Routing with IPv6
10947 23:01:42.302274 <6>[ 17.990159] In-situ OAM (IOAM) with IPv6
10948 23:01:42.336093 <30>[ 18.004422] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10949 23:01:42.339682 <30>[ 18.028206] systemd[1]: Detected architecture arm64.
10950 23:01:42.339772
10951 23:01:42.346750 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10952 23:01:42.346835
10953 23:01:42.358935 <30>[ 18.046657] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10954 23:01:42.510351 <30>[ 18.194355] systemd[1]: Queued start job for default target Graphical Interface.
10955 23:01:42.548570 <30>[ 18.235765] systemd[1]: Created slice system-getty.slice.
10956 23:01:42.555181 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10957 23:01:42.572087 <30>[ 18.259166] systemd[1]: Created slice system-modprobe.slice.
10958 23:01:42.578174 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10959 23:01:42.595837 <30>[ 18.283081] systemd[1]: Created slice system-serial\x2dgetty.slice.
10960 23:01:42.605368 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10961 23:01:42.619959 <30>[ 18.307590] systemd[1]: Created slice User and Session Slice.
10962 23:01:42.626585 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10963 23:01:42.646889 <30>[ 18.331106] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10964 23:01:42.656944 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10965 23:01:42.675259 <30>[ 18.358726] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10966 23:01:42.680934 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10967 23:01:42.701804 <30>[ 18.382598] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10968 23:01:42.708097 <30>[ 18.394637] systemd[1]: Reached target Local Encrypted Volumes.
10969 23:01:42.714835 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10970 23:01:42.731283 <30>[ 18.418921] systemd[1]: Reached target Paths.
10971 23:01:42.734518 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10972 23:01:42.751012 <30>[ 18.438545] systemd[1]: Reached target Remote File Systems.
10973 23:01:42.757747 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10974 23:01:42.770708 <30>[ 18.458596] systemd[1]: Reached target Slices.
10975 23:01:42.777553 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10976 23:01:42.790838 <30>[ 18.478550] systemd[1]: Reached target Swap.
10977 23:01:42.794645 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10978 23:01:42.814636 <30>[ 18.498912] systemd[1]: Listening on initctl Compatibility Named Pipe.
10979 23:01:42.821693 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10980 23:01:42.828008 <30>[ 18.513564] systemd[1]: Listening on Journal Audit Socket.
10981 23:01:42.834697 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10982 23:01:42.847805 <30>[ 18.534865] systemd[1]: Listening on Journal Socket (/dev/log).
10983 23:01:42.854030 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10984 23:01:42.871687 <30>[ 18.558891] systemd[1]: Listening on Journal Socket.
10985 23:01:42.878226 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10986 23:01:42.891318 <30>[ 18.578820] systemd[1]: Listening on udev Control Socket.
10987 23:01:42.897924 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10988 23:01:42.911140 <30>[ 18.598785] systemd[1]: Listening on udev Kernel Socket.
10989 23:01:42.917836 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10990 23:01:42.951216 <30>[ 18.638746] systemd[1]: Mounting Huge Pages File System...
10991 23:01:42.958027 Mounting [0;1;39mHuge Pages File System[0m...
10992 23:01:42.976357 <30>[ 18.660591] systemd[1]: Mounting POSIX Message Queue File System...
10993 23:01:42.979473 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10994 23:01:42.997123 <30>[ 18.684532] systemd[1]: Mounting Kernel Debug File System...
10995 23:01:43.003951 Mounting [0;1;39mKernel Debug File System[0m...
10996 23:01:43.022601 <30>[ 18.706821] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10997 23:01:43.059268 <30>[ 18.743014] systemd[1]: Starting Create list of static device nodes for the current kernel...
10998 23:01:43.065703 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10999 23:01:43.085440 <30>[ 18.772779] systemd[1]: Starting Load Kernel Module configfs...
11000 23:01:43.091632 Starting [0;1;39mLoad Kernel Module configfs[0m...
11001 23:01:43.127653 <30>[ 18.815026] systemd[1]: Starting Load Kernel Module drm...
11002 23:01:43.133958 Starting [0;1;39mLoad Kernel Module drm[0m...
11003 23:01:43.150482 <30>[ 18.834863] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
11004 23:01:43.160950 <30>[ 18.848472] systemd[1]: Starting Journal Service...
11005 23:01:43.164110 Starting [0;1;39mJournal Service[0m...
11006 23:01:43.181950 <30>[ 18.869189] systemd[1]: Starting Load Kernel Modules...
11007 23:01:43.188291 Starting [0;1;39mLoad Kernel Modules[0m...
11008 23:01:43.208933 <30>[ 18.893131] systemd[1]: Starting Remount Root and Kernel File Systems...
11009 23:01:43.215781 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
11010 23:01:43.229859 <30>[ 18.916989] systemd[1]: Starting Coldplug All udev Devices...
11011 23:01:43.236391 Starting [0;1;39mColdplug All udev Devices[0m...
11012 23:01:43.253860 <30>[ 18.941144] systemd[1]: Mounted Huge Pages File System.
11013 23:01:43.259935 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
11014 23:01:43.276245 <30>[ 18.963280] systemd[1]: Started Journal Service.
11015 23:01:43.282709 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
11016 23:01:43.297179 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
11017 23:01:43.316771 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
11018 23:01:43.335875 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
11019 23:01:43.357014 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
11020 23:01:43.372940 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
11021 23:01:43.392159 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
11022 23:01:43.416198 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
11023 23:01:43.435562 See 'systemctl status systemd-remount-fs.service' for details.
11024 23:01:43.496110 Mounting [0;1;39mKernel Configuration File System[0m...
11025 23:01:43.514050 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
11026 23:01:43.531296 <46>[ 19.215298] systemd-journald[174]: Received client request to flush runtime journal.
11027 23:01:43.539836 Starting [0;1;39mLoad/Save Random Seed[0m...
11028 23:01:43.558584 Starting [0;1;39mApply Kernel Variables[0m...
11029 23:01:43.574707 Starting [0;1;39mCreate System Users[0m...
11030 23:01:43.596947 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
11031 23:01:43.615760 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
11032 23:01:43.627976 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
11033 23:01:43.644136 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
11034 23:01:43.664267 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
11035 23:01:43.679997 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
11036 23:01:43.728167 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
11037 23:01:43.749762 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
11038 23:01:43.763709 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
11039 23:01:43.779453 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
11040 23:01:43.819844 Starting [0;1;39mCreate Volatile Files and Directories[0m...
11041 23:01:43.842736 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
11042 23:01:43.864098 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
11043 23:01:43.883738 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
11044 23:01:43.944205 Starting [0;1;39mNetwork Time Synchronization[0m...
11045 23:01:43.965166 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
11046 23:01:44.000192 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
11047 23:01:44.037255 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
11048 23:01:44.054802 <6>[ 19.739366] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
11049 23:01:44.068485 <6>[ 19.756545] remoteproc remoteproc0: scp is available
11050 23:01:44.078766 <4>[ 19.761974] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
11051 23:01:44.085375 <6>[ 19.771874] remoteproc remoteproc0: powering up scp
11052 23:01:44.092296 <3>[ 19.776573] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11053 23:01:44.102370 <4>[ 19.777040] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
11054 23:01:44.111972 <3>[ 19.785885] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11055 23:01:44.115013 <3>[ 19.794906] remoteproc remoteproc0: request_firmware failed: -2
11056 23:01:44.125612 <3>[ 19.809989] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11057 23:01:44.132400 <6>[ 19.815341] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
11058 23:01:44.142893 <3>[ 19.818319] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11059 23:01:44.151963 Startin<6>[ 19.825754] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
11060 23:01:44.159097 <3>[ 19.833938] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11061 23:01:44.169330 <6>[ 19.844110] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
11062 23:01:44.175450 <6>[ 19.844499] usbcore: registered new interface driver r8152
11063 23:01:44.182168 <3>[ 19.851953] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11064 23:01:44.188510 <3>[ 19.851975] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11065 23:01:44.198420 g [0;1;39mLoad/<6>[ 19.868802] usbcore: registered new interface driver cdc_ether
11066 23:01:44.201960 <6>[ 19.872865] mc: Linux media interface: v0.10
11067 23:01:44.211786 Save Screen …o<3>[ 19.874504] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11068 23:01:44.221846 f leds:white:kbd<3>[ 19.874609] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11069 23:01:44.231737 _backlight[0m..<6>[ 19.885238] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
11070 23:01:44.238887 <3>[ 19.891458] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11071 23:01:44.239486 .
11072 23:01:44.244955 <6>[ 19.892371] videodev: Linux video capture interface: v2.00
11073 23:01:44.252019 <6>[ 19.892415] usbcore: registered new interface driver r8153_ecm
11074 23:01:44.258413 <4>[ 19.925614] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
11075 23:01:44.264703 <3>[ 19.931382] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11076 23:01:44.275220 <4>[ 19.939468] elants_i2c 4-0010: supply vccio not found, using dummy regulator
11077 23:01:44.281660 <3>[ 19.943214] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11078 23:01:44.291478 <4>[ 19.961927] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
11079 23:01:44.294533 <4>[ 19.961927] Fallback method does not support PEC.
11080 23:01:44.304320 <3>[ 19.974851] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11081 23:01:44.312006 <6>[ 19.982632] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
11082 23:01:44.318985 <3>[ 20.003161] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11083 23:01:44.325671 <6>[ 20.003348] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
11084 23:01:44.339154 [[0;32m OK [<6>[ 20.010735] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
11085 23:01:44.348438 0m] Started [0;<6>[ 20.011131] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
11086 23:01:44.355137 <3>[ 20.011741] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11087 23:01:44.362248 1;39mNetwork Tim<6>[ 20.018978] pci_bus 0000:00: root bus resource [bus 00-ff]
11088 23:01:44.371447 <3>[ 20.029662] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11089 23:01:44.381735 e Synchronizatio<3>[ 20.029676] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11090 23:01:44.388337 <6>[ 20.040236] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
11091 23:01:44.388943 n[0m.
11092 23:01:44.398358 <3>[ 20.048158] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11093 23:01:44.408201 <6>[ 20.055400] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
11094 23:01:44.414924 <6>[ 20.056946] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
11095 23:01:44.425056 <3>[ 20.063471] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11096 23:01:44.432325 <6>[ 20.073874] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
11097 23:01:44.435776 <6>[ 20.081722] Bluetooth: Core ver 2.22
11098 23:01:44.442770 <6>[ 20.089842] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
11099 23:01:44.448917 <6>[ 20.104700] NET: Registered PF_BLUETOOTH protocol family
11100 23:01:44.452546 <6>[ 20.108999] pci 0000:00:00.0: supports D1 D2
11101 23:01:44.458730 <6>[ 20.116943] Bluetooth: HCI device and connection manager initialized
11102 23:01:44.468568 <4>[ 20.121737] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
11103 23:01:44.475053 <4>[ 20.121748] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
11104 23:01:44.481595 <6>[ 20.123326] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11105 23:01:44.488885 <6>[ 20.127026] Bluetooth: HCI socket layer initialized
11106 23:01:44.495167 <6>[ 20.136729] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
11107 23:01:44.501531 <6>[ 20.140075] Bluetooth: L2CAP socket layer initialized
11108 23:01:44.505070 <6>[ 20.140096] Bluetooth: SCO socket layer initialized
11109 23:01:44.515431 <6>[ 20.141513] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
11110 23:01:44.525154 <6>[ 20.142715] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
11111 23:01:44.531831 <6>[ 20.142869] usbcore: registered new interface driver uvcvideo
11112 23:01:44.537863 <6>[ 20.144956] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
11113 23:01:44.542043 <6>[ 20.174487] r8152 2-1.3:1.0 eth0: v1.12.13
11114 23:01:44.551683 <6>[ 20.175280] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
11115 23:01:44.557908 <6>[ 20.176139] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
11116 23:01:44.561014 <6>[ 20.180232] remoteproc remoteproc0: powering up scp
11117 23:01:44.570982 <4>[ 20.180275] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
11118 23:01:44.577815 <3>[ 20.180284] remoteproc remoteproc0: request_firmware failed: -2
11119 23:01:44.583995 <3>[ 20.180287] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
11120 23:01:44.590903 <6>[ 20.193313] r8152 2-1.3:1.0 enx002432307852: renamed from eth0
11121 23:01:44.597968 <6>[ 20.194057] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
11122 23:01:44.608940 <3>[ 20.195838] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11123 23:01:44.612027 <6>[ 20.199999] usbcore: registered new interface driver btusb
11124 23:01:44.622206 <6>[ 20.206343] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
11125 23:01:44.632893 <4>[ 20.219033] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
11126 23:01:44.635802 <6>[ 20.224848] pci 0000:01:00.0: supports D1 D2
11127 23:01:44.642667 <3>[ 20.231020] Bluetooth: hci0: Failed to load firmware file (-2)
11128 23:01:44.649287 <6>[ 20.235341] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11129 23:01:44.655976 <3>[ 20.242845] power_supply sbs-5-000b: driver failed to report `temp' property: -6
11130 23:01:44.663126 <3>[ 20.243474] Bluetooth: hci0: Failed to set up firmware (-2)
11131 23:01:44.673079 <4>[ 20.243481] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
11132 23:01:44.679507 <6>[ 20.258556] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
11133 23:01:44.689666 <3>[ 20.294673] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
11134 23:01:44.696798 <3>[ 20.295495] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11135 23:01:44.706385 <3>[ 20.299947] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11136 23:01:44.713319 <6>[ 20.300491] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
11137 23:01:44.724222 <3>[ 20.322995] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11138 23:01:44.730669 <6>[ 20.324190] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
11139 23:01:44.740568 <3>[ 20.349363] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11140 23:01:44.746880 <6>[ 20.355127] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
11141 23:01:44.757458 <6>[ 20.355144] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
11142 23:01:44.764423 <3>[ 20.385287] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11143 23:01:44.771285 <6>[ 20.389971] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
11144 23:01:44.781643 <3>[ 20.419662] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11145 23:01:44.787877 <6>[ 20.423605] pci 0000:00:00.0: PCI bridge to [bus 01]
11146 23:01:44.794204 <6>[ 20.423613] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
11147 23:01:44.801526 <6>[ 20.487396] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
11148 23:01:44.808490 [[0;32m OK [<6>[ 20.494653] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
11149 23:01:44.815310 0m] Finished [0<6>[ 20.501680] pcieport 0000:00:00.0: AER: enabled with IRQ 283
11150 23:01:44.821586 ;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
11151 23:01:44.837518 <5>[ 20.521520] cfg80211: Loading compiled-in X.509 certificates for regulatory database
11152 23:01:44.845685 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
11153 23:01:44.856689 <5>[ 20.540964] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
11154 23:01:44.863885 <4>[ 20.547934] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
11155 23:01:44.869915 <6>[ 20.557018] cfg80211: failed to load regulatory.db
11156 23:01:44.914589 <6>[ 20.598388] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
11157 23:01:44.920814 <6>[ 20.605942] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
11158 23:01:44.945407 <6>[ 20.632749] mt7921e 0000:01:00.0: ASIC revision: 79610010
11159 23:01:45.029650 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
11160 23:01:45.053901 [[0;32m OK [0m] Reached target [0;1;39mSyst<4>[ 20.734563] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11161 23:01:45.057388 em Initialization[0m.
11162 23:01:45.078644 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
11163 23:01:45.091068 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
11164 23:01:45.107229 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
11165 23:01:45.131034 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
11166 23:01:45.143179 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
11167 23:01:45.162956 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
11168 23:01:45.176523 <4>[ 20.857641] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11169 23:01:45.183308 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
11170 23:01:45.199715 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
11171 23:01:45.218708 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
11172 23:01:45.264233 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
11173 23:01:45.294074 <4>[ 20.974760] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11174 23:01:45.303302 Starting [0;1;39mUser Login Management[0m...
11175 23:01:45.321785 Starting [0;1;39mPermit User Sessions[0m...
11176 23:01:45.339578 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
11177 23:01:45.355653 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
11178 23:01:45.372210 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11179 23:01:45.412237 <4>[ 21.093167] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11180 23:01:45.418868 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11181 23:01:45.434635 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11182 23:01:45.451111 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11183 23:01:45.468756 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11184 23:01:45.484215 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11185 23:01:45.499291 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11186 23:01:45.532497 <4>[ 21.213495] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11187 23:01:45.560995 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11188 23:01:45.587423 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11189 23:01:45.605623
11190 23:01:45.606076
11191 23:01:45.608408 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11192 23:01:45.608853
11193 23:01:45.612221 debian-bullseye-arm64 login: root (automatic login)
11194 23:01:45.612667
11195 23:01:45.613105
11196 23:01:45.629419 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Mon Jun 5 22:41:02 UTC 2023 aarch64
11197 23:01:45.629939
11198 23:01:45.636068 The programs included with the Debian GNU/Linux system are free software;
11199 23:01:45.652185 the exact distribution terms for each program are described<4>[ 21.332289] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11200 23:01:45.652613 in the
11201 23:01:45.655506 individual files in /usr/share/doc/*/copyright.
11202 23:01:45.655948
11203 23:01:45.662203 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11204 23:01:45.665600 permitted by applicable law.
11205 23:01:45.666609 Matched prompt #10: / #
11207 23:01:45.667805 Setting prompt string to ['/ #']
11208 23:01:45.668305 end: 2.2.5.1 login-action (duration 00:00:22) [common]
11210 23:01:45.669608 end: 2.2.5 auto-login-action (duration 00:00:22) [common]
11211 23:01:45.670146 start: 2.2.6 expect-shell-connection (timeout 00:01:59) [common]
11212 23:01:45.670743 Setting prompt string to ['/ #']
11213 23:01:45.671230 Forcing a shell prompt, looking for ['/ #']
11215 23:01:45.722389 / #
11216 23:01:45.722969 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11217 23:01:45.723492 Waiting using forced prompt support (timeout 00:02:30)
11218 23:01:45.728225
11219 23:01:45.728929 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11220 23:01:45.729376 start: 2.2.7 export-device-env (timeout 00:01:59) [common]
11221 23:01:45.729825 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11222 23:01:45.730245 end: 2.2 depthcharge-retry (duration 00:03:01) [common]
11223 23:01:45.730664 end: 2 depthcharge-action (duration 00:03:01) [common]
11224 23:01:45.731088 start: 3 lava-test-retry (timeout 00:05:00) [common]
11225 23:01:45.731539 start: 3.1 lava-test-shell (timeout 00:05:00) [common]
11226 23:01:45.731895 Using namespace: common
11228 23:01:45.832851 / # #
11229 23:01:45.833433 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:05:00)
11230 23:01:45.833972 <4>[ 21.456769] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11231 23:01:45.839155 #
11232 23:01:45.840047 Using /lava-10597696
11234 23:01:45.941080 / # export SHELL=/bin/sh
11235 23:01:45.941391 <4>[ 21.572670] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11236 23:01:45.947233 export SHELL=/bin/sh
11238 23:01:46.048175 / # . /lava-10597696/environment
11239 23:01:46.049052 <4>[ 21.688748] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11240 23:01:46.053678 . /lava-10597696/environment
11242 23:01:46.155068 / # /lava-10597696/bin/lava-test-runner /lava-10597696/0
11243 23:01:46.156017 Test shell timeout: 10s (minimum of the action and connection timeout)
11244 23:01:46.159240 /lava-10597696/bin/lava-test-run<4>[ 21.804490] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11245 23:01:46.161429 ner /lava-10597696/0
11246 23:01:46.203721 + export TESTRUN_ID=0_sleep
11247 23:01:46.204359 + cd /lava-10597696/0/tests/0_sleep
11248 23:01:46.204943 + cat uuid
11249 23:01:46.205481 + UUID=10597696_1.5.2.3.1
11250 23:01:46.206032 + set +x
11251 23:01:46.206877 <LAVA_SIGNAL_STARTRUN 0_sleep 10597696_1.5.2.3.1>
11252 23:01:46.207980 + ./config/lava/sleep/sleep.sh mem freeze
11253 23:01:46.208872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc-exist RESULT=pass>
11254 23:01:46.209656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc-wakeup-enabled RESULT=pass>
11255 23:01:46.210602 Received signal: <STARTRUN> 0_sleep 10597696_1.5.2.3.1
11256 23:01:46.211152 Starting test lava.0_sleep (10597696_1.5.2.3.1)
11257 23:01:46.211867 Skipping test definition patterns.
11258 23:01:46.212532 Received signal: <TESTCASE> TEST_CASE_ID=rtc-exist RESULT=pass
11260 23:01:46.214230 Received signal: <TESTCASE> TEST_CASE_ID=rtc-wakeup-enabled RESULT=pass
11262 23:01:46.216004 rtcwake: assuming RTC uses UTC ...
11263 23:01:46.222031 rtcwake: wakeup from "mem" using rtc0 at Mon<6>[ 21.908810] PM: suspend entry (deep)
11264 23:01:46.225180 Jun 5 23:01:57<6>[ 21.913390] Filesystems sync: 0.000 seconds
11265 23:01:46.225657 2023
11266 23:01:46.231587 <3>[ 21.918669] mt7921e 0000:01:00.0: hardware init failed
11267 23:01:46.238730 <6>[ 21.926737] Freezing user space processes
11268 23:01:46.248971 <6>[ 21.932789] Freezing user space processes completed (elapsed 0.001 seconds)
11269 23:01:46.252088 <6>[ 21.940068] OOM killer disabled.
11270 23:01:46.255061 <6>[ 21.943559] Freezing remaining freezable tasks
11271 23:01:46.264928 <6>[ 21.949497] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11272 23:01:46.271588 <6>[ 21.957193] printk: Suspending console(s) (use no_console_suspend to debug)
11273 23:01:49.700516 <3>[ 25.162657] mt7921e 0000:01:00.0: Message 00020007 (seq 6) timeout
11274 23:01:49.710141 <3>[ 25.162696] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11275 23:01:49.720131 <3>[ 25.162749] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11276 23:01:49.726691 <3>[ 25.162780] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11277 23:01:49.737036 <3>[ 25.163002] PM: Some devices failed to suspend, or early wake event detected
11278 23:01:49.743910 <4>[ 25.179134] typec port0-partner: PM: parent port0 should not be sleeping
11279 23:01:49.746755 <6>[ 25.435318] OOM killer enabled.
11280 23:01:49.753823 <6>[ 25.438726] Restarting tasks ... done.
11281 23:01:49.757114 <5>[ 25.446166] random: crng reseeded on system resumption
11282 23:01:49.760751 <6>[ 25.452540] PM: suspend exit
11283 23:01:49.763975 rtcwake: write error
11284 23:01:49.772683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-1 RESULT=fail>
11285 23:01:49.773396 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-1 RESULT=fail
11287 23:01:49.776059 rtcwake: assuming RTC uses UTC ...
11288 23:01:49.782415 rtcwake: wakeup from "mem" using rtc0 at Mon Jun 5 23:02:01 2023
11289 23:01:49.795252 <6>[ 25.483740] PM: suspend entry (deep)
11290 23:01:49.799311 <6>[ 25.487671] Filesystems sync: 0.000 seconds
11291 23:01:49.805273 <6>[ 25.492843] Freezing user space processes
11292 23:01:49.811907 <6>[ 25.498386] Freezing user space processes completed (elapsed 0.001 seconds)
11293 23:01:49.815842 <6>[ 25.505615] OOM killer disabled.
11294 23:01:49.822468 <6>[ 25.509106] Freezing remaining freezable tasks
11295 23:01:49.828581 <6>[ 25.515002] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11296 23:01:49.835591 <6>[ 25.522656] printk: Suspending console(s) (use no_console_suspend to debug)
11297 23:01:53.283009 <3>[ 28.746541] mt7921e 0000:01:00.0: Message 00020007 (seq 7) timeout
11298 23:01:53.293142 <3>[ 28.746564] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11299 23:01:53.303641 <3>[ 28.746591] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11300 23:01:53.309920 <3>[ 28.746612] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11301 23:01:53.316343 <3>[ 28.746861] PM: Some devices failed to suspend, or early wake event detected
11302 23:01:53.319883 <6>[ 29.011691] OOM killer enabled.
11303 23:01:53.328015 <6>[ 29.015090] Restarting tasks ... done.
11304 23:01:53.331124 <5>[ 29.020709] random: crng reseeded on system resumption
11305 23:01:53.334688 <6>[ 29.027069] PM: suspend exit
11306 23:01:53.337898 rtcwake: write error
11307 23:01:53.346593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-2 RESULT=fail>
11308 23:01:53.347232 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-2 RESULT=fail
11310 23:01:53.349591 rtcwake: assuming RTC uses UTC ...
11311 23:01:53.356417 rtcwake: wakeup from "mem" using rtc0 at Mon Jun 5 23:02:04 2023
11312 23:01:53.368325 <6>[ 29.057471] PM: suspend entry (deep)
11313 23:01:53.371521 <6>[ 29.061357] Filesystems sync: 0.000 seconds
11314 23:01:53.378168 <6>[ 29.066649] Freezing user space processes
11315 23:01:53.384714 <6>[ 29.072654] Freezing user space processes completed (elapsed 0.001 seconds)
11316 23:01:53.387881 <6>[ 29.079904] OOM killer disabled.
11317 23:01:53.394866 <6>[ 29.083388] Freezing remaining freezable tasks
11318 23:01:53.401623 <6>[ 29.089311] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11319 23:01:53.411022 <6>[ 29.096979] printk: Suspending console(s) (use no_console_suspend to debug)
11320 23:01:56.870066 <3>[ 32.330663] mt7921e 0000:01:00.0: Message 00020007 (seq 8) timeout
11321 23:01:56.880369 <3>[ 32.330742] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11322 23:01:56.890473 <3>[ 32.330831] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11323 23:01:56.896650 <3>[ 32.330916] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11324 23:01:56.903303 <3>[ 32.331238] PM: Some devices failed to suspend, or early wake event detected
11325 23:01:56.909990 <6>[ 32.599720] OOM killer enabled.
11326 23:01:56.913172 <6>[ 32.603119] Restarting tasks ... done.
11327 23:01:56.920023 <5>[ 32.608778] random: crng reseeded on system resumption
11328 23:01:56.923782 <6>[ 32.615178] PM: suspend exit
11329 23:01:56.926673 rtcwake: write error
11330 23:01:56.933708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-3 RESULT=fail>
11331 23:01:56.934007 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-3 RESULT=fail
11333 23:01:56.936767 rtcwake: assuming RTC uses UTC ...
11334 23:01:56.943624 rtcwake: wakeup from "mem" using rtc0 at Mon Jun 5 23:02:08 2023
11335 23:01:56.956164 <6>[ 32.645895] PM: suspend entry (deep)
11336 23:01:56.959837 <6>[ 32.649784] Filesystems sync: 0.000 seconds
11337 23:01:56.962813 <6>[ 32.654936] Freezing user space processes
11338 23:01:56.974650 <6>[ 32.660971] Freezing user space processes completed (elapsed 0.001 seconds)
11339 23:01:56.978178 <6>[ 32.668199] OOM killer disabled.
11340 23:01:56.981323 <6>[ 32.671681] Freezing remaining freezable tasks
11341 23:01:56.991265 <6>[ 32.677668] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11342 23:01:56.998076 <6>[ 32.685326] printk: Suspending console(s) (use no_console_suspend to debug)
11343 23:02:00.454491 <3>[ 35.914541] mt7921e 0000:01:00.0: Message 00020007 (seq 9) timeout
11344 23:02:00.464837 <3>[ 35.914565] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11345 23:02:00.474263 <3>[ 35.914590] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11346 23:02:00.481026 <3>[ 35.914611] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11347 23:02:00.488153 <3>[ 35.915087] PM: Some devices failed to suspend, or early wake event detected
11348 23:02:00.491420 <6>[ 36.184366] OOM killer enabled.
11349 23:02:00.499854 <6>[ 36.187767] Restarting tasks ... done.
11350 23:02:00.502871 <5>[ 36.193851] random: crng reseeded on system resumption
11351 23:02:00.506821 <6>[ 36.200486] PM: suspend exit
11352 23:02:00.510413 rtcwake: write error
11353 23:02:00.518281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-4 RESULT=fail>
11354 23:02:00.518543 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-4 RESULT=fail
11356 23:02:00.521702 rtcwake: assuming RTC uses UTC ...
11357 23:02:00.527794 rtcwake: wakeup from "mem" using rtc0 at Mon Jun 5 23:02:11 2023
11358 23:02:00.541010 <6>[ 36.230836] PM: suspend entry (deep)
11359 23:02:00.543945 <6>[ 36.234775] Filesystems sync: 0.000 seconds
11360 23:02:00.547824 <6>[ 36.239929] Freezing user space processes
11361 23:02:00.559655 <6>[ 36.245980] Freezing user space processes completed (elapsed 0.001 seconds)
11362 23:02:00.562538 <6>[ 36.253220] OOM killer disabled.
11363 23:02:00.565830 <6>[ 36.256703] Freezing remaining freezable tasks
11364 23:02:00.575909 <6>[ 36.262332] Freezing remaining freezable tasks completed (elapsed 0.000 seconds)
11365 23:02:00.582667 <6>[ 36.269987] printk: Suspending console(s) (use no_console_suspend to debug)
11366 23:02:04.034680 <3>[ 39.498565] mt7921e 0000:01:00.0: Message 00020007 (seq 10) timeout
11367 23:02:04.044917 <3>[ 39.498590] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11368 23:02:04.054776 <3>[ 39.498625] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11369 23:02:04.060859 <3>[ 39.498646] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11370 23:02:04.071480 <3>[ 39.499084] PM: Some devices failed to suspend, or early wake event detected
11371 23:02:04.074603 <6>[ 39.764413] OOM killer enabled.
11372 23:02:04.077976 <6>[ 39.767814] Restarting tasks ... done.
11373 23:02:04.084276 <5>[ 39.773799] random: crng reseeded on system resumption
11374 23:02:04.087722 <6>[ 39.780370] PM: suspend exit
11375 23:02:04.090478 rtcwake: write error
11376 23:02:04.098393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-5 RESULT=fail>
11377 23:02:04.099201 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-5 RESULT=fail
11379 23:02:04.101309 rtcwake: assuming RTC uses UTC ...
11380 23:02:04.108068 rtcwake: wakeup from "mem" using rtc0 at Mon Jun 5 23:02:15 2023
11381 23:02:04.121008 <6>[ 39.810676] PM: suspend entry (deep)
11382 23:02:04.123977 <6>[ 39.814565] Filesystems sync: 0.000 seconds
11383 23:02:04.127185 <6>[ 39.819608] Freezing user space processes
11384 23:02:04.139268 <6>[ 39.825551] Freezing user space processes completed (elapsed 0.001 seconds)
11385 23:02:04.142405 <6>[ 39.832778] OOM killer disabled.
11386 23:02:04.146334 <6>[ 39.836265] Freezing remaining freezable tasks
11387 23:02:04.156058 <6>[ 39.842234] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11388 23:02:04.162407 <6>[ 39.849893] printk: Suspending console(s) (use no_console_suspend to debug)
11389 23:02:07.621928 <3>[ 43.082587] mt7921e 0000:01:00.0: Message 00020007 (seq 11) timeout
11390 23:02:07.635525 <3>[ 43.082616] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11391 23:02:07.642025 <3>[ 43.082655] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11392 23:02:07.649069 <3>[ 43.082675] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11393 23:02:07.658676 <3>[ 43.083061] PM: Some devices failed to suspend, or early wake event detected
11394 23:02:07.661669 <6>[ 43.352336] OOM killer enabled.
11395 23:02:07.664660 <6>[ 43.355737] Restarting tasks ... done.
11396 23:02:07.671396 <5>[ 43.361404] random: crng reseeded on system resumption
11397 23:02:07.675118 <6>[ 43.367830] PM: suspend exit
11398 23:02:07.677883 rtcwake: write error
11399 23:02:07.685466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-6 RESULT=fail>
11400 23:02:07.686190 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-6 RESULT=fail
11402 23:02:07.689137 rtcwake: assuming RTC uses UTC ...
11403 23:02:07.695632 rtcwake: wakeup from "mem" using rtc0 at Mon Jun 5 23:02:18 2023
11404 23:02:07.708375 <6>[ 43.398605] PM: suspend entry (deep)
11405 23:02:07.712050 <6>[ 43.402520] Filesystems sync: 0.000 seconds
11406 23:02:07.714960 <6>[ 43.407581] Freezing user space processes
11407 23:02:07.726709 <6>[ 43.413588] Freezing user space processes completed (elapsed 0.001 seconds)
11408 23:02:07.729786 <6>[ 43.420884] OOM killer disabled.
11409 23:02:07.733487 <6>[ 43.424372] Freezing remaining freezable tasks
11410 23:02:07.743266 <6>[ 43.430389] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11411 23:02:07.750059 <6>[ 43.438043] printk: Suspending console(s) (use no_console_suspend to debug)
11412 23:02:11.201076 <3>[ 46.666573] mt7921e 0000:01:00.0: Message 00020007 (seq 12) timeout
11413 23:02:11.211026 <3>[ 46.666597] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11414 23:02:11.221258 <3>[ 46.666632] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11415 23:02:11.228099 <3>[ 46.666653] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11416 23:02:11.234754 <3>[ 46.666938] PM: Some devices failed to suspend, or early wake event detected
11417 23:02:11.237764 <6>[ 46.932254] OOM killer enabled.
11418 23:02:11.246231 <6>[ 46.935653] Restarting tasks ... done.
11419 23:02:11.249474 <5>[ 46.941388] random: crng reseeded on system resumption
11420 23:02:11.253441 <6>[ 46.947811] PM: suspend exit
11421 23:02:11.256589 rtcwake: write error
11422 23:02:11.264530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-7 RESULT=fail>
11423 23:02:11.264833 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-7 RESULT=fail
11425 23:02:11.268043 rtcwake: assuming RTC uses UTC ...
11426 23:02:11.274314 rtcwake: wakeup from "mem" using rtc0 at Mon Jun 5 23:02:22 2023
11427 23:02:11.287056 <6>[ 46.978453] PM: suspend entry (deep)
11428 23:02:11.290439 <6>[ 46.982366] Filesystems sync: 0.000 seconds
11429 23:02:11.293897 <6>[ 46.987403] Freezing user space processes
11430 23:02:11.305652 <6>[ 46.993439] Freezing user space processes completed (elapsed 0.001 seconds)
11431 23:02:11.308784 <6>[ 47.000775] OOM killer disabled.
11432 23:02:11.312010 <6>[ 47.004265] Freezing remaining freezable tasks
11433 23:02:11.322146 <6>[ 47.010312] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11434 23:02:11.328896 <6>[ 47.017986] printk: Suspending console(s) (use no_console_suspend to debug)
11435 23:02:14.786004 <6>[ 48.202632] vpu: disabling
11436 23:02:14.789834 <6>[ 48.202723] vproc2: disabling
11437 23:02:14.792829 <6>[ 48.202762] vproc1: disabling
11438 23:02:14.795809 <6>[ 48.202800] vaud18: disabling
11439 23:02:14.799432 <6>[ 48.202983] vsram_others: disabling
11440 23:02:14.802554 <6>[ 48.203128] va09: disabling
11441 23:02:14.805648 <6>[ 48.203183] vsram_md: disabling
11442 23:02:14.809340 <6>[ 48.203279] Vgpu: disabling
11443 23:02:14.815993 <3>[ 50.250563] mt7921e 0000:01:00.0: Message 00020007 (seq 13) timeout
11444 23:02:14.825899 <3>[ 50.250587] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11445 23:02:14.835909 <3>[ 50.250621] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11446 23:02:14.842465 <3>[ 50.250642] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11447 23:02:14.849118 <3>[ 50.251089] PM: Some devices failed to suspend, or early wake event detected
11448 23:02:14.852006 <6>[ 50.546482] OOM killer enabled.
11449 23:02:14.860034 <6>[ 50.549878] Restarting tasks ... done.
11450 23:02:14.864132 <5>[ 50.555337] random: crng reseeded on system resumption
11451 23:02:14.868331 <6>[ 50.562666] PM: suspend exit
11452 23:02:14.871471 rtcwake: write error
11453 23:02:14.879943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-8 RESULT=fail>
11454 23:02:14.880743 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-8 RESULT=fail
11456 23:02:14.882968 rtcwake: assuming RTC uses UTC ...
11457 23:02:14.889918 rtcwake: wakeup from "mem" using rtc0 at Mon Jun 5 23:02:26 2023
11458 23:02:14.903234 <6>[ 50.594130] PM: suspend entry (deep)
11459 23:02:14.906147 <6>[ 50.598042] Filesystems sync: 0.000 seconds
11460 23:02:14.913255 <6>[ 50.603303] Freezing user space processes
11461 23:02:14.919469 <6>[ 50.609364] Freezing user space processes completed (elapsed 0.001 seconds)
11462 23:02:14.923402 <6>[ 50.616611] OOM killer disabled.
11463 23:02:14.929716 <6>[ 50.620095] Freezing remaining freezable tasks
11464 23:02:14.936032 <6>[ 50.626120] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11465 23:02:14.946426 <6>[ 50.633816] printk: Suspending console(s) (use no_console_suspend to debug)
11466 23:02:18.372726 <3>[ 53.834582] mt7921e 0000:01:00.0: Message 00020007 (seq 14) timeout
11467 23:02:18.382751 <3>[ 53.834609] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11468 23:02:18.393378 <3>[ 53.834646] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11469 23:02:18.399446 <3>[ 53.834667] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11470 23:02:18.409448 <3>[ 53.835120] PM: Some devices failed to suspend, or early wake event detected
11471 23:02:18.412892 <6>[ 54.104448] OOM killer enabled.
11472 23:02:18.416116 <6>[ 54.107850] Restarting tasks ... done.
11473 23:02:18.422843 <5>[ 54.114243] random: crng reseeded on system resumption
11474 23:02:18.425953 <6>[ 54.120621] PM: suspend exit
11475 23:02:18.428973 rtcwake: write error
11476 23:02:18.436676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-9 RESULT=fail>
11477 23:02:18.437566 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-9 RESULT=fail
11479 23:02:18.440138 rtcwake: assuming RTC uses UTC ...
11480 23:02:18.446842 rtcwake: wakeup from "mem" using rtc0 at Mon Jun 5 23:02:29 2023
11481 23:02:18.459859 <6>[ 54.151423] PM: suspend entry (deep)
11482 23:02:18.463061 <6>[ 54.155331] Filesystems sync: 0.000 seconds
11483 23:02:18.469581 <6>[ 54.160471] Freezing user space processes
11484 23:02:18.476479 <6>[ 54.166529] Freezing user space processes completed (elapsed 0.001 seconds)
11485 23:02:18.479462 <6>[ 54.173762] OOM killer disabled.
11486 23:02:18.486288 <6>[ 54.177246] Freezing remaining freezable tasks
11487 23:02:18.493065 <6>[ 54.183166] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11488 23:02:18.503285 <6>[ 54.190826] printk: Suspending console(s) (use no_console_suspend to debug)
11489 23:02:21.959617 <3>[ 57.418565] mt7921e 0000:01:00.0: Message 00020007 (seq 15) timeout
11490 23:02:21.970086 <3>[ 57.418589] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11491 23:02:21.979584 <3>[ 57.418624] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11492 23:02:21.986226 <3>[ 57.418645] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11493 23:02:21.992785 <3>[ 57.419078] PM: Some devices failed to suspend, or early wake event detected
11494 23:02:21.999900 <6>[ 57.692322] OOM killer enabled.
11495 23:02:22.002804 <6>[ 57.695721] Restarting tasks ... done.
11496 23:02:22.009807 <5>[ 57.701395] random: crng reseeded on system resumption
11497 23:02:22.012945 <6>[ 57.708684] PM: suspend exit
11498 23:02:22.016562 rtcwake: write error
11499 23:02:22.023828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-10 RESULT=fail>
11500 23:02:22.024092 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-10 RESULT=fail
11502 23:02:22.027518 rtcwake: assuming RTC uses UTC ...
11503 23:02:22.034346 rtcwake: wakeup from "freeze" using rtc0 at Mon Jun 5 23:02:33 2023
11504 23:02:22.048340 <6>[ 57.741071] PM: suspend entry (s2idle)
11505 23:02:22.052313 <6>[ 57.745149] Filesystems sync: 0.000 seconds
11506 23:02:22.058275 <6>[ 57.750386] Freezing user space processes
11507 23:02:22.064961 <6>[ 57.756494] Freezing user space processes completed (elapsed 0.001 seconds)
11508 23:02:22.068083 <6>[ 57.763746] OOM killer disabled.
11509 23:02:22.074882 <6>[ 57.767228] Freezing remaining freezable tasks
11510 23:02:22.084979 <6>[ 57.773285] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11511 23:02:22.091661 <6>[ 57.780972] printk: Suspending console(s) (use no_console_suspend to debug)
11512 23:02:25.542930 <3>[ 61.002567] mt7921e 0000:01:00.0: Message 00020007 (seq 1) timeout
11513 23:02:25.552780 <3>[ 61.002591] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11514 23:02:25.562457 <3>[ 61.002626] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11515 23:02:25.569020 <3>[ 61.002647] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11516 23:02:25.579311 <3>[ 61.003095] PM: Some devices failed to suspend, or early wake event detected
11517 23:02:25.582417 <6>[ 61.275582] OOM killer enabled.
11518 23:02:25.585318 <6>[ 61.278983] Restarting tasks ... done.
11519 23:02:25.592475 <5>[ 61.284629] random: crng reseeded on system resumption
11520 23:02:25.595485 <6>[ 61.291105] PM: suspend exit
11521 23:02:25.599012 rtcwake: write error
11522 23:02:25.606840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-1 RESULT=fail>
11523 23:02:25.607132 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-1 RESULT=fail
11525 23:02:25.609756 rtcwake: assuming RTC uses UTC ...
11526 23:02:25.616500 rtcwake: wakeup from "freeze" using rtc0 at Mon Jun 5 23:02:36 2023
11527 23:02:25.629609 <6>[ 61.322439] PM: suspend entry (s2idle)
11528 23:02:25.632674 <6>[ 61.326531] Filesystems sync: 0.000 seconds
11529 23:02:25.639933 <6>[ 61.331716] Freezing user space processes
11530 23:02:25.646009 <6>[ 61.337802] Freezing user space processes completed (elapsed 0.001 seconds)
11531 23:02:25.649667 <6>[ 61.345052] OOM killer disabled.
11532 23:02:25.656333 <6>[ 61.348536] Freezing remaining freezable tasks
11533 23:02:25.663242 <6>[ 61.354569] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11534 23:02:25.672761 <6>[ 61.362243] printk: Suspending console(s) (use no_console_suspend to debug)
11535 23:02:29.126433 <3>[ 64.586514] mt7921e 0000:01:00.0: Message 00020007 (seq 2) timeout
11536 23:02:29.136527 <3>[ 64.586538] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11537 23:02:29.146163 <3>[ 64.586563] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11538 23:02:29.153442 <3>[ 64.586586] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11539 23:02:29.160013 <3>[ 64.587083] PM: Some devices failed to suspend, or early wake event detected
11540 23:02:29.163084 <6>[ 64.859715] OOM killer enabled.
11541 23:02:29.171098 <6>[ 64.863113] Restarting tasks ... done.
11542 23:02:29.174247 <5>[ 64.868827] random: crng reseeded on system resumption
11543 23:02:29.178646 <6>[ 64.875212] PM: suspend exit
11544 23:02:29.181598 rtcwake: write error
11545 23:02:29.189847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-2 RESULT=fail>
11546 23:02:29.190108 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-2 RESULT=fail
11548 23:02:29.193478 rtcwake: assuming RTC uses UTC ...
11549 23:02:29.199820 rtcwake: wakeup from "freeze" using rtc0 at Mon Jun 5 23:02:40 2023
11550 23:02:29.212948 <6>[ 64.906165] PM: suspend entry (s2idle)
11551 23:02:29.215923 <6>[ 64.910229] Filesystems sync: 0.000 seconds
11552 23:02:29.223023 <6>[ 64.915383] Freezing user space processes
11553 23:02:29.229648 <6>[ 64.921480] Freezing user space processes completed (elapsed 0.001 seconds)
11554 23:02:29.232598 <6>[ 64.928732] OOM killer disabled.
11555 23:02:29.239076 <6>[ 64.932215] Freezing remaining freezable tasks
11556 23:02:29.245737 <6>[ 64.938170] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11557 23:02:29.255864 <6>[ 64.945835] printk: Suspending console(s) (use no_console_suspend to debug)
11558 23:02:32.710303 <3>[ 68.170552] mt7921e 0000:01:00.0: Message 00020007 (seq 3) timeout
11559 23:02:32.720251 <3>[ 68.170576] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11560 23:02:32.730534 <3>[ 68.170602] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11561 23:02:32.737136 <3>[ 68.170623] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11562 23:02:32.746946 <3>[ 68.170906] PM: Some devices failed to suspend, or early wake event detected
11563 23:02:32.750374 <6>[ 68.444223] OOM killer enabled.
11564 23:02:32.753397 <6>[ 68.447623] Restarting tasks ... done.
11565 23:02:32.760190 <5>[ 68.453371] random: crng reseeded on system resumption
11566 23:02:32.763336 <6>[ 68.459781] PM: suspend exit
11567 23:02:32.766987 rtcwake: write error
11568 23:02:32.773806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-3 RESULT=fail>
11569 23:02:32.774063 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-3 RESULT=fail
11571 23:02:32.776783 rtcwake: assuming RTC uses UTC ...
11572 23:02:32.783443 rtcwake: wakeup from "freeze" using rtc0 at Mon Jun 5 23:02:44 2023
11573 23:02:32.796752 <6>[ 68.490559] PM: suspend entry (s2idle)
11574 23:02:32.799868 <6>[ 68.494623] Filesystems sync: 0.000 seconds
11575 23:02:32.806537 <6>[ 68.499805] Freezing user space processes
11576 23:02:32.813107 <6>[ 68.505852] Freezing user space processes completed (elapsed 0.001 seconds)
11577 23:02:32.816258 <6>[ 68.513171] OOM killer disabled.
11578 23:02:32.823295 <6>[ 68.516663] Freezing remaining freezable tasks
11579 23:02:32.829678 <6>[ 68.522329] Freezing remaining freezable tasks completed (elapsed 0.000 seconds)
11580 23:02:32.839259 <6>[ 68.529981] printk: Suspending console(s) (use no_console_suspend to debug)
11581 23:02:36.290557 <3>[ 71.754588] mt7921e 0000:01:00.0: Message 00020007 (seq 4) timeout
11582 23:02:36.300332 <3>[ 71.754616] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11583 23:02:36.310794 <3>[ 71.754652] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11584 23:02:36.317458 <3>[ 71.754672] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11585 23:02:36.324091 <3>[ 71.755161] PM: Some devices failed to suspend, or early wake event detected
11586 23:02:36.327344 <6>[ 72.024177] OOM killer enabled.
11587 23:02:36.335278 <6>[ 72.027575] Restarting tasks ... done.
11588 23:02:36.338403 <5>[ 72.033167] random: crng reseeded on system resumption
11589 23:02:36.342831 <6>[ 72.039642] PM: suspend exit
11590 23:02:36.345900 rtcwake: write error
11591 23:02:36.353991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-4 RESULT=fail>
11592 23:02:36.354772 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-4 RESULT=fail
11594 23:02:36.356936 rtcwake: assuming RTC uses UTC ...
11595 23:02:36.363699 rtcwake: wakeup from "freeze" using rtc0 at Mon Jun 5 23:02:47 2023
11596 23:02:36.376542 <6>[ 72.070437] PM: suspend entry (s2idle)
11597 23:02:36.380405 <6>[ 72.074519] Filesystems sync: 0.000 seconds
11598 23:02:36.386771 <6>[ 72.079688] Freezing user space processes
11599 23:02:36.393260 <6>[ 72.085748] Freezing user space processes completed (elapsed 0.001 seconds)
11600 23:02:36.396198 <6>[ 72.093040] OOM killer disabled.
11601 23:02:36.403747 <6>[ 72.096530] Freezing remaining freezable tasks
11602 23:02:36.410116 <6>[ 72.102383] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11603 23:02:36.419453 <6>[ 72.110046] printk: Suspending console(s) (use no_console_suspend to debug)
11604 23:02:39.878218 <3>[ 75.338565] mt7921e 0000:01:00.0: Message 00020007 (seq 5) timeout
11605 23:02:39.888034 <3>[ 75.338590] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11606 23:02:39.897709 <3>[ 75.338625] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11607 23:02:39.904435 <3>[ 75.338645] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11608 23:02:39.911229 <3>[ 75.339079] PM: Some devices failed to suspend, or early wake event detected
11609 23:02:39.917993 <6>[ 75.612280] OOM killer enabled.
11610 23:02:39.921068 <6>[ 75.615680] Restarting tasks ... done.
11611 23:02:39.927591 <5>[ 75.621389] random: crng reseeded on system resumption
11612 23:02:39.930959 <6>[ 75.627729] PM: suspend exit
11613 23:02:39.934417 rtcwake: write error
11614 23:02:39.941453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-5 RESULT=fail>
11615 23:02:39.942169 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-5 RESULT=fail
11617 23:02:39.945147 rtcwake: assuming RTC uses UTC ...
11618 23:02:39.951284 rtcwake: wakeup from "freeze" using rtc0 at Mon Jun 5 23:02:51 2023
11619 23:02:39.964079 <6>[ 75.658763] PM: suspend entry (s2idle)
11620 23:02:39.967718 <6>[ 75.662843] Filesystems sync: 0.000 seconds
11621 23:02:39.974244 <6>[ 75.667975] Freezing user space processes
11622 23:02:39.981378 <6>[ 75.674033] Freezing user space processes completed (elapsed 0.001 seconds)
11623 23:02:39.984463 <6>[ 75.681335] OOM killer disabled.
11624 23:02:39.990887 <6>[ 75.684822] Freezing remaining freezable tasks
11625 23:02:39.997253 <6>[ 75.690346] Freezing remaining freezable tasks completed (elapsed 0.000 seconds)
11626 23:02:40.004018 <6>[ 75.698007] printk: Suspending console(s) (use no_console_suspend to debug)
11627 23:02:43.457599 <3>[ 78.922590] mt7921e 0000:01:00.0: Message 00020007 (seq 6) timeout
11628 23:02:43.467776 <3>[ 78.922614] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11629 23:02:43.477726 <3>[ 78.922649] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11630 23:02:43.483761 <3>[ 78.922669] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11631 23:02:43.490762 <3>[ 78.923079] PM: Some devices failed to suspend, or early wake event detected
11632 23:02:43.497430 <6>[ 79.192233] OOM killer enabled.
11633 23:02:43.500502 <6>[ 79.195633] Restarting tasks ... done.
11634 23:02:43.507734 <5>[ 79.201219] random: crng reseeded on system resumption
11635 23:02:43.510788 <6>[ 79.207773] PM: suspend exit
11636 23:02:43.514432 rtcwake: write error
11637 23:02:43.521366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-6 RESULT=fail>
11638 23:02:43.522076 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-6 RESULT=fail
11640 23:02:43.524598 rtcwake: assuming RTC uses UTC ...
11641 23:02:43.531278 rtcwake: wakeup from "freeze" using rtc0 at Mon Jun 5 23:02:54 2023
11642 23:02:43.544562 <6>[ 79.238908] PM: suspend entry (s2idle)
11643 23:02:43.547450 <6>[ 79.242984] Filesystems sync: 0.000 seconds
11644 23:02:43.554395 <6>[ 79.248132] Freezing user space processes
11645 23:02:43.561045 <6>[ 79.254052] Freezing user space processes completed (elapsed 0.001 seconds)
11646 23:02:43.563907 <6>[ 79.261336] OOM killer disabled.
11647 23:02:43.570570 <6>[ 79.264828] Freezing remaining freezable tasks
11648 23:02:43.577384 <6>[ 79.270388] Freezing remaining freezable tasks completed (elapsed 0.000 seconds)
11649 23:02:43.584178 <6>[ 79.278043] printk: Suspending console(s) (use no_console_suspend to debug)
11650 23:02:47.040917 <3>[ 82.506572] mt7921e 0000:01:00.0: Message 00020007 (seq 7) timeout
11651 23:02:47.051067 <3>[ 82.506597] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11652 23:02:47.060658 <3>[ 82.506631] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11653 23:02:47.067313 <3>[ 82.506653] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11654 23:02:47.074014 <3>[ 82.507039] PM: Some devices failed to suspend, or early wake event detected
11655 23:02:47.077811 <6>[ 82.776380] OOM killer enabled.
11656 23:02:47.086373 <6>[ 82.779782] Restarting tasks ... done.
11657 23:02:47.089736 <5>[ 82.786133] random: crng reseeded on system resumption
11658 23:02:47.093344 <6>[ 82.792632] PM: suspend exit
11659 23:02:47.096994 rtcwake: write error
11660 23:02:47.105481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-7 RESULT=fail>
11661 23:02:47.105769 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-7 RESULT=fail
11663 23:02:47.108484 rtcwake: assuming RTC uses UTC ...
11664 23:02:47.115057 rtcwake: wakeup from "freeze" using rtc0 at Mon Jun 5 23:02:58 2023
11665 23:02:47.127963 <6>[ 82.823450] PM: suspend entry (s2idle)
11666 23:02:47.130989 <6>[ 82.827550] Filesystems sync: 0.000 seconds
11667 23:02:47.137633 <6>[ 82.832749] Freezing user space processes
11668 23:02:47.144361 <6>[ 82.838444] Freezing user space processes completed (elapsed 0.001 seconds)
11669 23:02:47.147817 <6>[ 82.845667] OOM killer disabled.
11670 23:02:47.154402 <6>[ 82.849160] Freezing remaining freezable tasks
11671 23:02:47.161315 <6>[ 82.855116] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11672 23:02:47.170884 <6>[ 82.862774] printk: Suspending console(s) (use no_console_suspend to debug)
11673 23:02:50.628191 <3>[ 86.090595] mt7921e 0000:01:00.0: Message 00020007 (seq 8) timeout
11674 23:02:50.638267 <3>[ 86.090620] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11675 23:02:50.648316 <3>[ 86.090658] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11676 23:02:50.654998 <3>[ 86.090678] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11677 23:02:50.661842 <3>[ 86.091090] PM: Some devices failed to suspend, or early wake event detected
11678 23:02:50.665090 <6>[ 86.364072] OOM killer enabled.
11679 23:02:50.672803 <6>[ 86.367472] Restarting tasks ... done.
11680 23:02:50.676480 <5>[ 86.373085] random: crng reseeded on system resumption
11681 23:02:50.680057 <6>[ 86.379552] PM: suspend exit
11682 23:02:50.683908 rtcwake: write error
11683 23:02:50.691801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-8 RESULT=fail>
11684 23:02:50.692063 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-8 RESULT=fail
11686 23:02:50.694748 rtcwake: assuming RTC uses UTC ...
11687 23:02:50.701366 rtcwake: wakeup from "freeze" using rtc0 at Mon Jun 5 23:03:01 2023
11688 23:02:50.713802 <6>[ 86.410135] PM: suspend entry (s2idle)
11689 23:02:50.717254 <6>[ 86.414213] Filesystems sync: 0.000 seconds
11690 23:02:50.723836 <6>[ 86.419389] Freezing user space processes
11691 23:02:50.731028 <6>[ 86.425577] Freezing user space processes completed (elapsed 0.001 seconds)
11692 23:02:50.733998 <6>[ 86.432820] OOM killer disabled.
11693 23:02:50.740607 <6>[ 86.436305] Freezing remaining freezable tasks
11694 23:02:50.747439 <6>[ 86.442312] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11695 23:02:50.757307 <6>[ 86.449973] printk: Suspending console(s) (use no_console_suspend to debug)
11696 23:02:54.212887 <3>[ 89.674599] mt7921e 0000:01:00.0: Message 00020007 (seq 9) timeout
11697 23:02:54.222672 <3>[ 89.674622] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11698 23:02:54.232815 <3>[ 89.674656] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11699 23:02:54.239799 <3>[ 89.674677] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11700 23:02:54.246395 <3>[ 89.675066] PM: Some devices failed to suspend, or early wake event detected
11701 23:02:54.249165 <6>[ 89.948390] OOM killer enabled.
11702 23:02:54.257435 <6>[ 89.951792] Restarting tasks ... done.
11703 23:02:54.261067 <5>[ 89.958036] random: crng reseeded on system resumption
11704 23:02:54.265515 <6>[ 89.965104] PM: suspend exit
11705 23:02:54.268700 rtcwake: write error
11706 23:02:54.277248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-9 RESULT=fail>
11707 23:02:54.277527 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-9 RESULT=fail
11709 23:02:54.280798 rtcwake: assuming RTC uses UTC ...
11710 23:02:54.286617 rtcwake: wakeup from "freeze" using rtc0 at Mon Jun 5 23:03:05 2023
11711 23:02:54.299913 <6>[ 89.995950] PM: suspend entry (s2idle)
11712 23:02:54.302933 <6>[ 90.000054] Filesystems sync: 0.000 seconds
11713 23:02:54.310442 <6>[ 90.005217] Freezing user space processes
11714 23:02:54.316907 <6>[ 90.011096] Freezing user space processes completed (elapsed 0.001 seconds)
11715 23:02:54.319901 <6>[ 90.018319] OOM killer disabled.
11716 23:02:54.326693 <6>[ 90.021796] Freezing remaining freezable tasks
11717 23:02:54.333093 <6>[ 90.027848] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11718 23:02:54.342553 <6>[ 90.035540] printk: Suspending console(s) (use no_console_suspend to debug)
11719 23:02:57.787773 <3>[ 93.258566] mt7921e 0000:01:00.0: Message 00020007 (seq 10) timeout
11720 23:02:57.797666 <3>[ 93.258591] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11721 23:02:57.807700 <3>[ 93.258625] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11722 23:02:57.814220 <3>[ 93.258645] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11723 23:02:57.820962 <3>[ 93.258941] PM: Some devices failed to suspend, or early wake event detected
11724 23:02:57.827668 <6>[ 93.524326] OOM killer enabled.
11725 23:02:57.830723 <6>[ 93.527725] Restarting tasks ... done.
11726 23:02:57.837202 <5>[ 93.533632] random: crng reseeded on system resumption
11727 23:02:57.840798 <6>[ 93.540132] PM: suspend exit
11728 23:02:57.843820 rtcwake: write error
11729 23:02:57.851176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-10 RESULT=fail>
11730 23:02:57.851477 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-10 RESULT=fail
11732 23:02:57.854710 + set +x
11733 23:02:57.857854 <LAVA_SIGNAL_ENDRUN 0_sleep 10597696_1.5.2.3.1>
11734 23:02:57.857981 <LAVA_TEST_RUNNER EXIT>
11735 23:02:57.858251 Received signal: <ENDRUN> 0_sleep 10597696_1.5.2.3.1
11736 23:02:57.858383 Ending use of test pattern.
11737 23:02:57.858476 Ending test lava.0_sleep (10597696_1.5.2.3.1), duration 71.65
11739 23:02:57.859123 ok: lava_test_shell seems to have completed
11740 23:02:57.859588 rtc-exist: pass
rtc-wakeup-enabled: pass
rtcwake-freeze-1: fail
rtcwake-freeze-10: fail
rtcwake-freeze-2: fail
rtcwake-freeze-3: fail
rtcwake-freeze-4: fail
rtcwake-freeze-5: fail
rtcwake-freeze-6: fail
rtcwake-freeze-7: fail
rtcwake-freeze-8: fail
rtcwake-freeze-9: fail
rtcwake-mem-1: fail
rtcwake-mem-10: fail
rtcwake-mem-2: fail
rtcwake-mem-3: fail
rtcwake-mem-4: fail
rtcwake-mem-5: fail
rtcwake-mem-6: fail
rtcwake-mem-7: fail
rtcwake-mem-8: fail
rtcwake-mem-9: fail
11741 23:02:57.859752 end: 3.1 lava-test-shell (duration 00:01:12) [common]
11742 23:02:57.859897 end: 3 lava-test-retry (duration 00:01:12) [common]
11743 23:02:57.860018 start: 4 finalize (timeout 00:05:15) [common]
11744 23:02:57.860196 start: 4.1 power-off (timeout 00:00:30) [common]
11745 23:02:57.860513 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=off'
11746 23:02:57.935230 >> Command sent successfully.
11747 23:02:57.937551 Returned 0 in 0 seconds
11748 23:02:58.037937 end: 4.1 power-off (duration 00:00:00) [common]
11750 23:02:58.038304 start: 4.2 read-feedback (timeout 00:05:15) [common]
11751 23:02:58.038569 Listened to connection for namespace 'common' for up to 1s
11752 23:02:58.038863 Listened to connection for namespace 'common' for up to 1s
11753 23:02:59.039448 Finalising connection for namespace 'common'
11754 23:02:59.039647 Disconnecting from shell: Finalise
11755 23:02:59.039737 / #
11756 23:02:59.140058 end: 4.2 read-feedback (duration 00:00:01) [common]
11757 23:02:59.140242 end: 4 finalize (duration 00:00:01) [common]
11758 23:02:59.140368 Cleaning after the job
11759 23:02:59.140470 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597696/tftp-deploy-ndc77cb0/ramdisk
11760 23:02:59.151691 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597696/tftp-deploy-ndc77cb0/kernel
11761 23:02:59.169086 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597696/tftp-deploy-ndc77cb0/dtb
11762 23:02:59.169314 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597696/tftp-deploy-ndc77cb0/modules
11763 23:02:59.174713 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10597696
11764 23:02:59.311876 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10597696
11765 23:02:59.312059 Job finished correctly