Boot log: mt8192-asurada-spherion-r0
- Errors: 2
- Kernel Errors: 27
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 22
1 22:55:08.406572 lava-dispatcher, installed at version: 2023.05.1
2 22:55:08.406769 start: 0 validate
3 22:55:08.406899 Start time: 2023-06-05 22:55:08.406889+00:00 (UTC)
4 22:55:08.407011 Using caching service: 'http://localhost/cache/?uri=%s'
5 22:55:08.407139 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230527.0%2Farm64%2Frootfs.cpio.gz exists
6 22:55:08.701971 Using caching service: 'http://localhost/cache/?uri=%s'
7 22:55:08.702778 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1314-g1ab0ac1d7e2e3%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 22:55:08.996820 Using caching service: 'http://localhost/cache/?uri=%s'
9 22:55:08.997608 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1314-g1ab0ac1d7e2e3%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 22:55:23.533608 Using caching service: 'http://localhost/cache/?uri=%s'
11 22:55:23.533782 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1314-g1ab0ac1d7e2e3%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 22:55:24.102730 validate duration: 15.70
14 22:55:24.103080 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 22:55:24.103224 start: 1.1 download-retry (timeout 00:10:00) [common]
16 22:55:24.103361 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 22:55:24.103525 Not decompressing ramdisk as can be used compressed.
18 22:55:24.103641 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230527.0/arm64/rootfs.cpio.gz
19 22:55:24.103728 saving as /var/lib/lava/dispatcher/tmp/10597683/tftp-deploy-bbro1pbo/ramdisk/rootfs.cpio.gz
20 22:55:24.103811 total size: 8186575 (7MB)
21 22:55:29.251803 progress 0% (0MB)
22 22:55:29.264897 progress 5% (0MB)
23 22:55:29.276590 progress 10% (0MB)
24 22:55:29.287005 progress 15% (1MB)
25 22:55:29.292989 progress 20% (1MB)
26 22:55:29.297952 progress 25% (1MB)
27 22:55:29.301836 progress 30% (2MB)
28 22:55:29.305555 progress 35% (2MB)
29 22:55:29.308772 progress 40% (3MB)
30 22:55:29.311975 progress 45% (3MB)
31 22:55:29.314653 progress 50% (3MB)
32 22:55:29.317403 progress 55% (4MB)
33 22:55:29.319728 progress 60% (4MB)
34 22:55:29.322177 progress 65% (5MB)
35 22:55:29.324292 progress 70% (5MB)
36 22:55:29.326513 progress 75% (5MB)
37 22:55:29.328546 progress 80% (6MB)
38 22:55:29.330708 progress 85% (6MB)
39 22:55:29.332713 progress 90% (7MB)
40 22:55:29.334834 progress 95% (7MB)
41 22:55:29.336865 progress 100% (7MB)
42 22:55:29.337075 7MB downloaded in 5.23s (1.49MB/s)
43 22:55:29.337219 end: 1.1.1 http-download (duration 00:00:05) [common]
45 22:55:29.337456 end: 1.1 download-retry (duration 00:00:05) [common]
46 22:55:29.337541 start: 1.2 download-retry (timeout 00:09:55) [common]
47 22:55:29.337624 start: 1.2.1 http-download (timeout 00:09:55) [common]
48 22:55:29.337755 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1314-g1ab0ac1d7e2e3/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 22:55:29.337824 saving as /var/lib/lava/dispatcher/tmp/10597683/tftp-deploy-bbro1pbo/kernel/Image
50 22:55:29.337884 total size: 45746688 (43MB)
51 22:55:29.337943 No compression specified
52 22:55:29.624526 progress 0% (0MB)
53 22:55:29.673662 progress 5% (2MB)
54 22:55:29.691243 progress 10% (4MB)
55 22:55:29.703942 progress 15% (6MB)
56 22:55:29.715280 progress 20% (8MB)
57 22:55:29.726592 progress 25% (10MB)
58 22:55:29.737822 progress 30% (13MB)
59 22:55:29.749639 progress 35% (15MB)
60 22:55:29.761150 progress 40% (17MB)
61 22:55:29.772782 progress 45% (19MB)
62 22:55:29.784110 progress 50% (21MB)
63 22:55:29.795278 progress 55% (24MB)
64 22:55:29.806507 progress 60% (26MB)
65 22:55:29.817741 progress 65% (28MB)
66 22:55:29.828834 progress 70% (30MB)
67 22:55:29.839919 progress 75% (32MB)
68 22:55:29.851059 progress 80% (34MB)
69 22:55:29.862575 progress 85% (37MB)
70 22:55:29.874068 progress 90% (39MB)
71 22:55:29.885159 progress 95% (41MB)
72 22:55:29.896193 progress 100% (43MB)
73 22:55:29.896308 43MB downloaded in 0.56s (78.13MB/s)
74 22:55:29.896453 end: 1.2.1 http-download (duration 00:00:01) [common]
76 22:55:29.896678 end: 1.2 download-retry (duration 00:00:01) [common]
77 22:55:29.896769 start: 1.3 download-retry (timeout 00:09:54) [common]
78 22:55:29.896855 start: 1.3.1 http-download (timeout 00:09:54) [common]
79 22:55:29.896987 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1314-g1ab0ac1d7e2e3/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 22:55:29.897056 saving as /var/lib/lava/dispatcher/tmp/10597683/tftp-deploy-bbro1pbo/dtb/mt8192-asurada-spherion-r0.dtb
81 22:55:29.897116 total size: 46924 (0MB)
82 22:55:29.897175 No compression specified
83 22:55:29.898360 progress 69% (0MB)
84 22:55:29.898639 progress 100% (0MB)
85 22:55:29.898787 0MB downloaded in 0.00s (26.83MB/s)
86 22:55:29.898904 end: 1.3.1 http-download (duration 00:00:00) [common]
88 22:55:29.899121 end: 1.3 download-retry (duration 00:00:00) [common]
89 22:55:29.899205 start: 1.4 download-retry (timeout 00:09:54) [common]
90 22:55:29.899287 start: 1.4.1 http-download (timeout 00:09:54) [common]
91 22:55:29.899437 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1314-g1ab0ac1d7e2e3/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 22:55:29.899505 saving as /var/lib/lava/dispatcher/tmp/10597683/tftp-deploy-bbro1pbo/modules/modules.tar
93 22:55:29.899565 total size: 8552396 (8MB)
94 22:55:29.899624 Using unxz to decompress xz
95 22:55:29.903043 progress 0% (0MB)
96 22:55:29.923215 progress 5% (0MB)
97 22:55:29.945697 progress 10% (0MB)
98 22:55:29.976154 progress 15% (1MB)
99 22:55:30.001379 progress 20% (1MB)
100 22:55:30.025413 progress 25% (2MB)
101 22:55:30.049413 progress 30% (2MB)
102 22:55:30.074887 progress 35% (2MB)
103 22:55:30.098974 progress 40% (3MB)
104 22:55:30.123371 progress 45% (3MB)
105 22:55:30.147091 progress 50% (4MB)
106 22:55:30.170751 progress 55% (4MB)
107 22:55:30.193874 progress 60% (4MB)
108 22:55:30.217501 progress 65% (5MB)
109 22:55:30.241359 progress 70% (5MB)
110 22:55:30.264581 progress 75% (6MB)
111 22:55:30.290046 progress 80% (6MB)
112 22:55:30.313979 progress 85% (6MB)
113 22:55:30.337482 progress 90% (7MB)
114 22:55:30.360115 progress 95% (7MB)
115 22:55:30.383789 progress 100% (8MB)
116 22:55:30.390140 8MB downloaded in 0.49s (16.63MB/s)
117 22:55:30.390428 end: 1.4.1 http-download (duration 00:00:00) [common]
119 22:55:30.390684 end: 1.4 download-retry (duration 00:00:00) [common]
120 22:55:30.390774 start: 1.5 prepare-tftp-overlay (timeout 00:09:54) [common]
121 22:55:30.390865 start: 1.5.1 extract-nfsrootfs (timeout 00:09:54) [common]
122 22:55:30.390946 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 22:55:30.391028 start: 1.5.2 lava-overlay (timeout 00:09:54) [common]
124 22:55:30.391239 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10597683/lava-overlay-x_i48vq2
125 22:55:30.391386 makedir: /var/lib/lava/dispatcher/tmp/10597683/lava-overlay-x_i48vq2/lava-10597683/bin
126 22:55:30.391500 makedir: /var/lib/lava/dispatcher/tmp/10597683/lava-overlay-x_i48vq2/lava-10597683/tests
127 22:55:30.391598 makedir: /var/lib/lava/dispatcher/tmp/10597683/lava-overlay-x_i48vq2/lava-10597683/results
128 22:55:30.391707 Creating /var/lib/lava/dispatcher/tmp/10597683/lava-overlay-x_i48vq2/lava-10597683/bin/lava-add-keys
129 22:55:30.391843 Creating /var/lib/lava/dispatcher/tmp/10597683/lava-overlay-x_i48vq2/lava-10597683/bin/lava-add-sources
130 22:55:30.391964 Creating /var/lib/lava/dispatcher/tmp/10597683/lava-overlay-x_i48vq2/lava-10597683/bin/lava-background-process-start
131 22:55:30.392087 Creating /var/lib/lava/dispatcher/tmp/10597683/lava-overlay-x_i48vq2/lava-10597683/bin/lava-background-process-stop
132 22:55:30.392203 Creating /var/lib/lava/dispatcher/tmp/10597683/lava-overlay-x_i48vq2/lava-10597683/bin/lava-common-functions
133 22:55:30.392321 Creating /var/lib/lava/dispatcher/tmp/10597683/lava-overlay-x_i48vq2/lava-10597683/bin/lava-echo-ipv4
134 22:55:30.392454 Creating /var/lib/lava/dispatcher/tmp/10597683/lava-overlay-x_i48vq2/lava-10597683/bin/lava-install-packages
135 22:55:30.392599 Creating /var/lib/lava/dispatcher/tmp/10597683/lava-overlay-x_i48vq2/lava-10597683/bin/lava-installed-packages
136 22:55:30.392713 Creating /var/lib/lava/dispatcher/tmp/10597683/lava-overlay-x_i48vq2/lava-10597683/bin/lava-os-build
137 22:55:30.392829 Creating /var/lib/lava/dispatcher/tmp/10597683/lava-overlay-x_i48vq2/lava-10597683/bin/lava-probe-channel
138 22:55:30.392946 Creating /var/lib/lava/dispatcher/tmp/10597683/lava-overlay-x_i48vq2/lava-10597683/bin/lava-probe-ip
139 22:55:30.393060 Creating /var/lib/lava/dispatcher/tmp/10597683/lava-overlay-x_i48vq2/lava-10597683/bin/lava-target-ip
140 22:55:30.393173 Creating /var/lib/lava/dispatcher/tmp/10597683/lava-overlay-x_i48vq2/lava-10597683/bin/lava-target-mac
141 22:55:30.393286 Creating /var/lib/lava/dispatcher/tmp/10597683/lava-overlay-x_i48vq2/lava-10597683/bin/lava-target-storage
142 22:55:30.393405 Creating /var/lib/lava/dispatcher/tmp/10597683/lava-overlay-x_i48vq2/lava-10597683/bin/lava-test-case
143 22:55:30.393520 Creating /var/lib/lava/dispatcher/tmp/10597683/lava-overlay-x_i48vq2/lava-10597683/bin/lava-test-event
144 22:55:30.393634 Creating /var/lib/lava/dispatcher/tmp/10597683/lava-overlay-x_i48vq2/lava-10597683/bin/lava-test-feedback
145 22:55:30.393749 Creating /var/lib/lava/dispatcher/tmp/10597683/lava-overlay-x_i48vq2/lava-10597683/bin/lava-test-raise
146 22:55:30.393865 Creating /var/lib/lava/dispatcher/tmp/10597683/lava-overlay-x_i48vq2/lava-10597683/bin/lava-test-reference
147 22:55:30.393980 Creating /var/lib/lava/dispatcher/tmp/10597683/lava-overlay-x_i48vq2/lava-10597683/bin/lava-test-runner
148 22:55:30.394095 Creating /var/lib/lava/dispatcher/tmp/10597683/lava-overlay-x_i48vq2/lava-10597683/bin/lava-test-set
149 22:55:30.394210 Creating /var/lib/lava/dispatcher/tmp/10597683/lava-overlay-x_i48vq2/lava-10597683/bin/lava-test-shell
150 22:55:30.394330 Updating /var/lib/lava/dispatcher/tmp/10597683/lava-overlay-x_i48vq2/lava-10597683/bin/lava-install-packages (oe)
151 22:55:30.394474 Updating /var/lib/lava/dispatcher/tmp/10597683/lava-overlay-x_i48vq2/lava-10597683/bin/lava-installed-packages (oe)
152 22:55:30.394643 Creating /var/lib/lava/dispatcher/tmp/10597683/lava-overlay-x_i48vq2/lava-10597683/environment
153 22:55:30.394736 LAVA metadata
154 22:55:30.394807 - LAVA_JOB_ID=10597683
155 22:55:30.394869 - LAVA_DISPATCHER_IP=192.168.201.1
156 22:55:30.394966 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:54) [common]
157 22:55:30.395029 skipped lava-vland-overlay
158 22:55:30.395101 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 22:55:30.395179 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:54) [common]
160 22:55:30.395239 skipped lava-multinode-overlay
161 22:55:30.395312 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 22:55:30.395461 start: 1.5.2.3 test-definition (timeout 00:09:54) [common]
163 22:55:30.395537 Loading test definitions
164 22:55:30.395625 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:54) [common]
165 22:55:30.395698 Using /lava-10597683 at stage 0
166 22:55:30.395993 uuid=10597683_1.5.2.3.1 testdef=None
167 22:55:30.396079 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 22:55:30.396161 start: 1.5.2.3.2 test-overlay (timeout 00:09:54) [common]
169 22:55:30.396753 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 22:55:30.396972 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:54) [common]
172 22:55:30.397571 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 22:55:30.397792 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:54) [common]
175 22:55:30.398373 runner path: /var/lib/lava/dispatcher/tmp/10597683/lava-overlay-x_i48vq2/lava-10597683/0/tests/0_dmesg test_uuid 10597683_1.5.2.3.1
176 22:55:30.398533 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 22:55:30.398791 start: 1.5.2.3.5 inline-repo-action (timeout 00:09:54) [common]
179 22:55:30.398860 Using /lava-10597683 at stage 1
180 22:55:30.399162 uuid=10597683_1.5.2.3.5 testdef=None
181 22:55:30.399264 end: 1.5.2.3.5 inline-repo-action (duration 00:00:00) [common]
182 22:55:30.399384 start: 1.5.2.3.6 test-overlay (timeout 00:09:54) [common]
183 22:55:30.399841 end: 1.5.2.3.6 test-overlay (duration 00:00:00) [common]
185 22:55:30.400050 start: 1.5.2.3.7 test-install-overlay (timeout 00:09:54) [common]
186 22:55:30.401131 end: 1.5.2.3.7 test-install-overlay (duration 00:00:00) [common]
188 22:55:30.401354 start: 1.5.2.3.8 test-runscript-overlay (timeout 00:09:54) [common]
189 22:55:30.401944 runner path: /var/lib/lava/dispatcher/tmp/10597683/lava-overlay-x_i48vq2/lava-10597683/1/tests/1_bootrr test_uuid 10597683_1.5.2.3.5
190 22:55:30.402090 end: 1.5.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
192 22:55:30.402291 Creating lava-test-runner.conf files
193 22:55:30.402353 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10597683/lava-overlay-x_i48vq2/lava-10597683/0 for stage 0
194 22:55:30.402437 - 0_dmesg
195 22:55:30.402570 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10597683/lava-overlay-x_i48vq2/lava-10597683/1 for stage 1
196 22:55:30.402670 - 1_bootrr
197 22:55:30.402759 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
198 22:55:30.402841 start: 1.5.2.4 compress-overlay (timeout 00:09:54) [common]
199 22:55:30.410537 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
200 22:55:30.410637 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:54) [common]
201 22:55:30.410721 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
202 22:55:30.410803 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
203 22:55:30.410886 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:54) [common]
204 22:55:30.642550 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:00) [common]
205 22:55:30.642906 start: 1.5.4 extract-modules (timeout 00:09:53) [common]
206 22:55:30.643036 extracting modules file /var/lib/lava/dispatcher/tmp/10597683/tftp-deploy-bbro1pbo/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10597683/extract-overlay-ramdisk-t4ekzmxl/ramdisk
207 22:55:30.838621 end: 1.5.4 extract-modules (duration 00:00:00) [common]
208 22:55:30.838791 start: 1.5.5 apply-overlay-tftp (timeout 00:09:53) [common]
209 22:55:30.838888 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10597683/compress-overlay-l6f59nj5/overlay-1.5.2.4.tar.gz to ramdisk
210 22:55:30.838960 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10597683/compress-overlay-l6f59nj5/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10597683/extract-overlay-ramdisk-t4ekzmxl/ramdisk
211 22:55:30.846664 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
212 22:55:30.846769 start: 1.5.6 configure-preseed-file (timeout 00:09:53) [common]
213 22:55:30.846852 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
214 22:55:30.846937 start: 1.5.7 compress-ramdisk (timeout 00:09:53) [common]
215 22:55:30.847016 Building ramdisk /var/lib/lava/dispatcher/tmp/10597683/extract-overlay-ramdisk-t4ekzmxl/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10597683/extract-overlay-ramdisk-t4ekzmxl/ramdisk
216 22:55:31.212765 >> 143719 blocks
217 22:55:33.497974 rename /var/lib/lava/dispatcher/tmp/10597683/extract-overlay-ramdisk-t4ekzmxl/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10597683/tftp-deploy-bbro1pbo/ramdisk/ramdisk.cpio.gz
218 22:55:33.498385 end: 1.5.7 compress-ramdisk (duration 00:00:03) [common]
219 22:55:33.498511 start: 1.5.8 prepare-kernel (timeout 00:09:51) [common]
220 22:55:33.498613 start: 1.5.8.1 prepare-fit (timeout 00:09:51) [common]
221 22:55:33.498724 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10597683/tftp-deploy-bbro1pbo/kernel/Image'
222 22:55:44.810962 Returned 0 in 11 seconds
223 22:55:44.911824 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10597683/tftp-deploy-bbro1pbo/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10597683/tftp-deploy-bbro1pbo/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10597683/tftp-deploy-bbro1pbo/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10597683/tftp-deploy-bbro1pbo/kernel/image.itb
224 22:55:45.312090 output: FIT description: Kernel Image image with one or more FDT blobs
225 22:55:45.312431 output: Created: Mon Jun 5 23:55:45 2023
226 22:55:45.312503 output: Image 0 (kernel-1)
227 22:55:45.312567 output: Description:
228 22:55:45.312626 output: Created: Mon Jun 5 23:55:45 2023
229 22:55:45.312685 output: Type: Kernel Image
230 22:55:45.312746 output: Compression: lzma compressed
231 22:55:45.312806 output: Data Size: 10085945 Bytes = 9849.56 KiB = 9.62 MiB
232 22:55:45.312865 output: Architecture: AArch64
233 22:55:45.312923 output: OS: Linux
234 22:55:45.313000 output: Load Address: 0x00000000
235 22:55:45.313100 output: Entry Point: 0x00000000
236 22:55:45.313152 output: Hash algo: crc32
237 22:55:45.313204 output: Hash value: b2943ff2
238 22:55:45.313255 output: Image 1 (fdt-1)
239 22:55:45.313306 output: Description: mt8192-asurada-spherion-r0
240 22:55:45.313357 output: Created: Mon Jun 5 23:55:45 2023
241 22:55:45.313408 output: Type: Flat Device Tree
242 22:55:45.313459 output: Compression: uncompressed
243 22:55:45.313510 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
244 22:55:45.313561 output: Architecture: AArch64
245 22:55:45.313612 output: Hash algo: crc32
246 22:55:45.313662 output: Hash value: 1df858fa
247 22:55:45.313712 output: Image 2 (ramdisk-1)
248 22:55:45.313763 output: Description: unavailable
249 22:55:45.313813 output: Created: Mon Jun 5 23:55:45 2023
250 22:55:45.313864 output: Type: RAMDisk Image
251 22:55:45.313915 output: Compression: Unknown Compression
252 22:55:45.313965 output: Data Size: 21245330 Bytes = 20747.39 KiB = 20.26 MiB
253 22:55:45.314017 output: Architecture: AArch64
254 22:55:45.314067 output: OS: Linux
255 22:55:45.314117 output: Load Address: unavailable
256 22:55:45.314168 output: Entry Point: unavailable
257 22:55:45.314218 output: Hash algo: crc32
258 22:55:45.314268 output: Hash value: bed2cbe4
259 22:55:45.314318 output: Default Configuration: 'conf-1'
260 22:55:45.314368 output: Configuration 0 (conf-1)
261 22:55:45.314420 output: Description: mt8192-asurada-spherion-r0
262 22:55:45.314471 output: Kernel: kernel-1
263 22:55:45.314521 output: Init Ramdisk: ramdisk-1
264 22:55:45.314572 output: FDT: fdt-1
265 22:55:45.314623 output: Loadables: kernel-1
266 22:55:45.314673 output:
267 22:55:45.314862 end: 1.5.8.1 prepare-fit (duration 00:00:12) [common]
268 22:55:45.315002 end: 1.5.8 prepare-kernel (duration 00:00:12) [common]
269 22:55:45.315145 end: 1.5 prepare-tftp-overlay (duration 00:00:15) [common]
270 22:55:45.315277 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:39) [common]
271 22:55:45.315414 No LXC device requested
272 22:55:45.315494 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
273 22:55:45.315584 start: 1.7 deploy-device-env (timeout 00:09:39) [common]
274 22:55:45.315661 end: 1.7 deploy-device-env (duration 00:00:00) [common]
275 22:55:45.315728 Checking files for TFTP limit of 4294967296 bytes.
276 22:55:45.316205 end: 1 tftp-deploy (duration 00:00:21) [common]
277 22:55:45.316311 start: 2 depthcharge-action (timeout 00:05:00) [common]
278 22:55:45.316402 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
279 22:55:45.316521 substitutions:
280 22:55:45.316586 - {DTB}: 10597683/tftp-deploy-bbro1pbo/dtb/mt8192-asurada-spherion-r0.dtb
281 22:55:45.316648 - {INITRD}: 10597683/tftp-deploy-bbro1pbo/ramdisk/ramdisk.cpio.gz
282 22:55:45.316704 - {KERNEL}: 10597683/tftp-deploy-bbro1pbo/kernel/Image
283 22:55:45.316760 - {LAVA_MAC}: None
284 22:55:45.316815 - {PRESEED_CONFIG}: None
285 22:55:45.316868 - {PRESEED_LOCAL}: None
286 22:55:45.316922 - {RAMDISK}: 10597683/tftp-deploy-bbro1pbo/ramdisk/ramdisk.cpio.gz
287 22:55:45.316974 - {ROOT_PART}: None
288 22:55:45.317026 - {ROOT}: None
289 22:55:45.317078 - {SERVER_IP}: 192.168.201.1
290 22:55:45.317130 - {TEE}: None
291 22:55:45.317190 Parsed boot commands:
292 22:55:45.317293 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
293 22:55:45.317461 Parsed boot commands: tftpboot 192.168.201.1 10597683/tftp-deploy-bbro1pbo/kernel/image.itb 10597683/tftp-deploy-bbro1pbo/kernel/cmdline
294 22:55:45.317549 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
295 22:55:45.317631 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
296 22:55:45.317720 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
297 22:55:45.317804 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
298 22:55:45.317874 Not connected, no need to disconnect.
299 22:55:45.317947 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
300 22:55:45.318022 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
301 22:55:45.318089 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-0'
302 22:55:45.321750 Setting prompt string to ['lava-test: # ']
303 22:55:45.322322 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
304 22:55:45.322419 end: 2.2.1 reset-connection (duration 00:00:00) [common]
305 22:55:45.322510 start: 2.2.2 reset-device (timeout 00:05:00) [common]
306 22:55:45.322598 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
307 22:55:45.322806 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=reboot'
308 22:55:50.488526 >> Command sent successfully.
309 22:55:50.494960 Returned 0 in 5 seconds
310 22:55:50.595789 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
312 22:55:50.597276 end: 2.2.2 reset-device (duration 00:00:05) [common]
313 22:55:50.597821 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
314 22:55:50.598413 Setting prompt string to 'Starting depthcharge on Spherion...'
315 22:55:50.598814 Changing prompt to 'Starting depthcharge on Spherion...'
316 22:55:50.599208 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
317 22:55:50.600535 [Enter `^Ec?' for help]
318 22:55:50.765859
319 22:55:50.766451
320 22:55:50.766837 F0: 102B 0000
321 22:55:50.767185
322 22:55:50.767561 F3: 1001 0000 [0200]
323 22:55:50.768451
324 22:55:50.769086 F3: 1001 0000
325 22:55:50.769470
326 22:55:50.769823 F7: 102D 0000
327 22:55:50.770160
328 22:55:50.772001 F1: 0000 0000
329 22:55:50.772466
330 22:55:50.772835 V0: 0000 0000 [0001]
331 22:55:50.773193
332 22:55:50.774902 00: 0007 8000
333 22:55:50.775412
334 22:55:50.775784 01: 0000 0000
335 22:55:50.776135
336 22:55:50.778500 BP: 0C00 0209 [0000]
337 22:55:50.778922
338 22:55:50.779253 G0: 1182 0000
339 22:55:50.779609
340 22:55:50.782423 EC: 0000 0021 [4000]
341 22:55:50.782860
342 22:55:50.783199 S7: 0000 0000 [0000]
343 22:55:50.783627
344 22:55:50.786109 CC: 0000 0000 [0001]
345 22:55:50.786650
346 22:55:50.786997 T0: 0000 0040 [010F]
347 22:55:50.787311
348 22:55:50.787664 Jump to BL
349 22:55:50.787964
350 22:55:50.812347
351 22:55:50.812907
352 22:55:50.813302
353 22:55:50.819866 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
354 22:55:50.823680 ARM64: Exception handlers installed.
355 22:55:50.827478 ARM64: Testing exception
356 22:55:50.830791 ARM64: Done test exception
357 22:55:50.837162 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
358 22:55:50.848020 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
359 22:55:50.854851 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
360 22:55:50.864559 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
361 22:55:50.870767 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
362 22:55:50.877753 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
363 22:55:50.889739 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
364 22:55:50.896593 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
365 22:55:50.914992 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
366 22:55:50.918444 WDT: Last reset was cold boot
367 22:55:50.922135 SPI1(PAD0) initialized at 2873684 Hz
368 22:55:50.924975 SPI5(PAD0) initialized at 992727 Hz
369 22:55:50.928348 VBOOT: Loading verstage.
370 22:55:50.934979 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
371 22:55:50.939456 FMAP: Found "FLASH" version 1.1 at 0x20000.
372 22:55:50.942855 FMAP: base = 0x0 size = 0x800000 #areas = 25
373 22:55:50.945703 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
374 22:55:50.952348 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
375 22:55:50.959682 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
376 22:55:50.970716 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
377 22:55:50.971289
378 22:55:50.971766
379 22:55:50.981198 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
380 22:55:50.984392 ARM64: Exception handlers installed.
381 22:55:50.984868 ARM64: Testing exception
382 22:55:50.988046 ARM64: Done test exception
383 22:55:50.991164 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
384 22:55:50.997536 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
385 22:55:51.011528 Probing TPM: . done!
386 22:55:51.012330 TPM ready after 0 ms
387 22:55:51.018481 Connected to device vid:did:rid of 1ae0:0028:00
388 22:55:51.025601 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.153/cr50_v3.94_pp.113-620c9b9523
389 22:55:51.084997 Initialized TPM device CR50 revision 0
390 22:55:51.096894 tlcl_send_startup: Startup return code is 0
391 22:55:51.097330 TPM: setup succeeded
392 22:55:51.108198 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
393 22:55:51.117458 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
394 22:55:51.131553 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
395 22:55:51.138671 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
396 22:55:51.142481 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
397 22:55:51.146195 in-header: 03 07 00 00 08 00 00 00
398 22:55:51.149351 in-data: aa e4 47 04 13 02 00 00
399 22:55:51.149779 Chrome EC: UHEPI supported
400 22:55:51.156676 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
401 22:55:51.161582 in-header: 03 95 00 00 08 00 00 00
402 22:55:51.165473 in-data: 18 20 20 08 00 00 00 00
403 22:55:51.165914 Phase 1
404 22:55:51.168757 FMAP: area GBB found @ 3f5000 (12032 bytes)
405 22:55:51.176661 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
406 22:55:51.184156 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
407 22:55:51.184589 Recovery requested (1009000e)
408 22:55:51.195747 TPM: Extending digest for VBOOT: boot mode into PCR 0
409 22:55:51.200114 tlcl_extend: response is 0
410 22:55:51.211271 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
411 22:55:51.215179 tlcl_extend: response is 0
412 22:55:51.222052 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
413 22:55:51.241080 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
414 22:55:51.248173 BS: bootblock times (exec / console): total (unknown) / 148 ms
415 22:55:51.248746
416 22:55:51.249202
417 22:55:51.257966 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
418 22:55:51.261678 ARM64: Exception handlers installed.
419 22:55:51.264905 ARM64: Testing exception
420 22:55:51.265512 ARM64: Done test exception
421 22:55:51.286911 pmic_efuse_setting: Set efuses in 11 msecs
422 22:55:51.290190 pmwrap_interface_init: Select PMIF_VLD_RDY
423 22:55:51.296476 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
424 22:55:51.300251 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
425 22:55:51.307505 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
426 22:55:51.311735 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
427 22:55:51.314635 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
428 22:55:51.322062 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
429 22:55:51.326363 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
430 22:55:51.330507 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
431 22:55:51.333876 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
432 22:55:51.337646 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
433 22:55:51.344828 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
434 22:55:51.348615 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
435 22:55:51.352177 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
436 22:55:51.359883 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
437 22:55:51.364112 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
438 22:55:51.371060 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
439 22:55:51.375122 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
440 22:55:51.382054 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
441 22:55:51.389150 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
442 22:55:51.393024 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
443 22:55:51.400459 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
444 22:55:51.404063 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
445 22:55:51.411179 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
446 22:55:51.414790 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
447 22:55:51.418443 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
448 22:55:51.426112 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
449 22:55:51.429692 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
450 22:55:51.437500 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
451 22:55:51.440915 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
452 22:55:51.444895 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
453 22:55:51.451943 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
454 22:55:51.455716 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
455 22:55:51.459398 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
456 22:55:51.467402 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
457 22:55:51.470335 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
458 22:55:51.474681 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
459 22:55:51.482269 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
460 22:55:51.486244 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
461 22:55:51.489544 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
462 22:55:51.492799 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
463 22:55:51.500182 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
464 22:55:51.504087 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
465 22:55:51.508047 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
466 22:55:51.511896 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
467 22:55:51.515374 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
468 22:55:51.522660 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
469 22:55:51.526201 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
470 22:55:51.530394 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
471 22:55:51.533886 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
472 22:55:51.537751 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
473 22:55:51.541094 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
474 22:55:51.547922 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
475 22:55:51.559942 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
476 22:55:51.563108 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
477 22:55:51.570259 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
478 22:55:51.580902 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
479 22:55:51.585035 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
480 22:55:51.588808 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
481 22:55:51.592112 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
482 22:55:51.600495 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x0
483 22:55:51.603432 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
484 22:55:51.611732 [RTC]rtc_osc_init,62: osc32con val = 0xde70
485 22:55:51.615516 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
486 22:55:51.624418 [RTC]rtc_get_frequency_meter,154: input=15, output=759
487 22:55:51.634376 [RTC]rtc_get_frequency_meter,154: input=23, output=943
488 22:55:51.642797 [RTC]rtc_get_frequency_meter,154: input=19, output=851
489 22:55:51.652595 [RTC]rtc_get_frequency_meter,154: input=17, output=806
490 22:55:51.662785 [RTC]rtc_get_frequency_meter,154: input=16, output=783
491 22:55:51.671784 [RTC]rtc_get_frequency_meter,154: input=16, output=781
492 22:55:51.681671 [RTC]rtc_get_frequency_meter,154: input=17, output=806
493 22:55:51.685131 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
494 22:55:51.688845 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
495 22:55:51.692677 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
496 22:55:51.700480 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
497 22:55:51.704169 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
498 22:55:51.707966 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
499 22:55:51.711480 ADC[4]: Raw value=906573 ID=7
500 22:55:51.712140 ADC[3]: Raw value=213810 ID=1
501 22:55:51.715417 RAM Code: 0x71
502 22:55:51.719222 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
503 22:55:51.723201 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
504 22:55:51.734398 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
505 22:55:51.738269 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
506 22:55:51.741773 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
507 22:55:51.745482 in-header: 03 07 00 00 08 00 00 00
508 22:55:51.748922 in-data: aa e4 47 04 13 02 00 00
509 22:55:51.752354 Chrome EC: UHEPI supported
510 22:55:51.759481 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
511 22:55:51.763095 in-header: 03 95 00 00 08 00 00 00
512 22:55:51.763575 in-data: 18 20 20 08 00 00 00 00
513 22:55:51.767085 MRC: failed to locate region type 0.
514 22:55:51.774703 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
515 22:55:51.778336 DRAM-K: Running full calibration
516 22:55:51.786426 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
517 22:55:51.786954 header.status = 0x0
518 22:55:51.789845 header.version = 0x6 (expected: 0x6)
519 22:55:51.793399 header.size = 0xd00 (expected: 0xd00)
520 22:55:51.793827 header.flags = 0x0
521 22:55:51.800431 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
522 22:55:51.818811 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
523 22:55:51.826334 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
524 22:55:51.826768 dram_init: ddr_geometry: 2
525 22:55:51.830194 [EMI] MDL number = 2
526 22:55:51.830671 [EMI] Get MDL freq = 0
527 22:55:51.833754 dram_init: ddr_type: 0
528 22:55:51.838241 is_discrete_lpddr4: 1
529 22:55:51.838819 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
530 22:55:51.839288
531 22:55:51.839756
532 22:55:51.841767 [Bian_co] ETT version 0.0.0.1
533 22:55:51.845963 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
534 22:55:51.846539
535 22:55:51.849208 dramc_set_vcore_voltage set vcore to 650000
536 22:55:51.852793 Read voltage for 800, 4
537 22:55:51.853238 Vio18 = 0
538 22:55:51.857012 Vcore = 650000
539 22:55:51.857459 Vdram = 0
540 22:55:51.857905 Vddq = 0
541 22:55:51.858322 Vmddr = 0
542 22:55:51.861121 dram_init: config_dvfs: 1
543 22:55:51.864959 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
544 22:55:51.872199 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
545 22:55:51.876116 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
546 22:55:51.879848 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
547 22:55:51.883484 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
548 22:55:51.887438 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
549 22:55:51.887973 MEM_TYPE=3, freq_sel=18
550 22:55:51.891197 sv_algorithm_assistance_LP4_1600
551 22:55:51.894457 ============ PULL DRAM RESETB DOWN ============
552 22:55:51.901210 ========== PULL DRAM RESETB DOWN end =========
553 22:55:51.904634 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
554 22:55:51.907892 ===================================
555 22:55:51.911635 LPDDR4 DRAM CONFIGURATION
556 22:55:51.914986 ===================================
557 22:55:51.915462 EX_ROW_EN[0] = 0x0
558 22:55:51.918885 EX_ROW_EN[1] = 0x0
559 22:55:51.919577 LP4Y_EN = 0x0
560 22:55:51.922490 WORK_FSP = 0x0
561 22:55:51.922972 WL = 0x2
562 22:55:51.923399 RL = 0x2
563 22:55:51.925937 BL = 0x2
564 22:55:51.926366 RPST = 0x0
565 22:55:51.929591 RD_PRE = 0x0
566 22:55:51.930056 WR_PRE = 0x1
567 22:55:51.933350 WR_PST = 0x0
568 22:55:51.933819 DBI_WR = 0x0
569 22:55:51.936660 DBI_RD = 0x0
570 22:55:51.937088 OTF = 0x1
571 22:55:51.939992 ===================================
572 22:55:51.943165 ===================================
573 22:55:51.947045 ANA top config
574 22:55:51.950010 ===================================
575 22:55:51.950521 DLL_ASYNC_EN = 0
576 22:55:51.953749 ALL_SLAVE_EN = 1
577 22:55:51.956642 NEW_RANK_MODE = 1
578 22:55:51.960020 DLL_IDLE_MODE = 1
579 22:55:51.963728 LP45_APHY_COMB_EN = 1
580 22:55:51.964154 TX_ODT_DIS = 1
581 22:55:51.967084 NEW_8X_MODE = 1
582 22:55:51.971253 ===================================
583 22:55:51.974312 ===================================
584 22:55:51.977838 data_rate = 1600
585 22:55:51.978352 CKR = 1
586 22:55:51.981203 DQ_P2S_RATIO = 8
587 22:55:51.984280 ===================================
588 22:55:51.987874 CA_P2S_RATIO = 8
589 22:55:51.991214 DQ_CA_OPEN = 0
590 22:55:51.994760 DQ_SEMI_OPEN = 0
591 22:55:51.997956 CA_SEMI_OPEN = 0
592 22:55:51.998479 CA_FULL_RATE = 0
593 22:55:52.001157 DQ_CKDIV4_EN = 1
594 22:55:52.004990 CA_CKDIV4_EN = 1
595 22:55:52.007879 CA_PREDIV_EN = 0
596 22:55:52.011208 PH8_DLY = 0
597 22:55:52.014405 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
598 22:55:52.014833 DQ_AAMCK_DIV = 4
599 22:55:52.017745 CA_AAMCK_DIV = 4
600 22:55:52.021095 CA_ADMCK_DIV = 4
601 22:55:52.024837 DQ_TRACK_CA_EN = 0
602 22:55:52.028374 CA_PICK = 800
603 22:55:52.031656 CA_MCKIO = 800
604 22:55:52.032330 MCKIO_SEMI = 0
605 22:55:52.035884 PLL_FREQ = 3068
606 22:55:52.039064 DQ_UI_PI_RATIO = 32
607 22:55:52.043388 CA_UI_PI_RATIO = 0
608 22:55:52.043878 ===================================
609 22:55:52.047252 ===================================
610 22:55:52.050631 memory_type:LPDDR4
611 22:55:52.054756 GP_NUM : 10
612 22:55:52.055521 SRAM_EN : 1
613 22:55:52.058470 MD32_EN : 0
614 22:55:52.059205 ===================================
615 22:55:52.062210 [ANA_INIT] >>>>>>>>>>>>>>
616 22:55:52.065915 <<<<<< [CONFIGURE PHASE]: ANA_TX
617 22:55:52.069489 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
618 22:55:52.073217 ===================================
619 22:55:52.076208 data_rate = 1600,PCW = 0X7600
620 22:55:52.080098 ===================================
621 22:55:52.082972 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
622 22:55:52.086147 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
623 22:55:52.092887 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
624 22:55:52.096275 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
625 22:55:52.099650 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
626 22:55:52.103051 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
627 22:55:52.106189 [ANA_INIT] flow start
628 22:55:52.109985 [ANA_INIT] PLL >>>>>>>>
629 22:55:52.110552 [ANA_INIT] PLL <<<<<<<<
630 22:55:52.112505 [ANA_INIT] MIDPI >>>>>>>>
631 22:55:52.116277 [ANA_INIT] MIDPI <<<<<<<<
632 22:55:52.116846 [ANA_INIT] DLL >>>>>>>>
633 22:55:52.119607 [ANA_INIT] flow end
634 22:55:52.122737 ============ LP4 DIFF to SE enter ============
635 22:55:52.126513 ============ LP4 DIFF to SE exit ============
636 22:55:52.129590 [ANA_INIT] <<<<<<<<<<<<<
637 22:55:52.132599 [Flow] Enable top DCM control >>>>>
638 22:55:52.136048 [Flow] Enable top DCM control <<<<<
639 22:55:52.139776 Enable DLL master slave shuffle
640 22:55:52.146081 ==============================================================
641 22:55:52.146574 Gating Mode config
642 22:55:52.152742 ==============================================================
643 22:55:52.153232 Config description:
644 22:55:52.162996 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
645 22:55:52.169458 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
646 22:55:52.176181 SELPH_MODE 0: By rank 1: By Phase
647 22:55:52.180118 ==============================================================
648 22:55:52.183411 GAT_TRACK_EN = 1
649 22:55:52.186794 RX_GATING_MODE = 2
650 22:55:52.189736 RX_GATING_TRACK_MODE = 2
651 22:55:52.193819 SELPH_MODE = 1
652 22:55:52.197060 PICG_EARLY_EN = 1
653 22:55:52.199949 VALID_LAT_VALUE = 1
654 22:55:52.203662 ==============================================================
655 22:55:52.206454 Enter into Gating configuration >>>>
656 22:55:52.210317 Exit from Gating configuration <<<<
657 22:55:52.213590 Enter into DVFS_PRE_config >>>>>
658 22:55:52.226865 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
659 22:55:52.227505 Exit from DVFS_PRE_config <<<<<
660 22:55:52.229755 Enter into PICG configuration >>>>
661 22:55:52.233022 Exit from PICG configuration <<<<
662 22:55:52.236711 [RX_INPUT] configuration >>>>>
663 22:55:52.239929 [RX_INPUT] configuration <<<<<
664 22:55:52.246990 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
665 22:55:52.249859 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
666 22:55:52.256571 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
667 22:55:52.263727 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
668 22:55:52.270210 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
669 22:55:52.277172 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
670 22:55:52.279958 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
671 22:55:52.283419 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
672 22:55:52.286640 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
673 22:55:52.293379 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
674 22:55:52.296899 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
675 22:55:52.300400 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
676 22:55:52.303702 ===================================
677 22:55:52.307108 LPDDR4 DRAM CONFIGURATION
678 22:55:52.310258 ===================================
679 22:55:52.310828 EX_ROW_EN[0] = 0x0
680 22:55:52.313559 EX_ROW_EN[1] = 0x0
681 22:55:52.314123 LP4Y_EN = 0x0
682 22:55:52.316829 WORK_FSP = 0x0
683 22:55:52.317397 WL = 0x2
684 22:55:52.320224 RL = 0x2
685 22:55:52.323517 BL = 0x2
686 22:55:52.324093 RPST = 0x0
687 22:55:52.327083 RD_PRE = 0x0
688 22:55:52.327595 WR_PRE = 0x1
689 22:55:52.330286 WR_PST = 0x0
690 22:55:52.330857 DBI_WR = 0x0
691 22:55:52.333631 DBI_RD = 0x0
692 22:55:52.334099 OTF = 0x1
693 22:55:52.336819 ===================================
694 22:55:52.340040 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
695 22:55:52.343170 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
696 22:55:52.350139 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
697 22:55:52.353309 ===================================
698 22:55:52.356556 LPDDR4 DRAM CONFIGURATION
699 22:55:52.360222 ===================================
700 22:55:52.360796 EX_ROW_EN[0] = 0x10
701 22:55:52.363741 EX_ROW_EN[1] = 0x0
702 22:55:52.364362 LP4Y_EN = 0x0
703 22:55:52.366912 WORK_FSP = 0x0
704 22:55:52.367425 WL = 0x2
705 22:55:52.370284 RL = 0x2
706 22:55:52.370857 BL = 0x2
707 22:55:52.373784 RPST = 0x0
708 22:55:52.374365 RD_PRE = 0x0
709 22:55:52.377042 WR_PRE = 0x1
710 22:55:52.377509 WR_PST = 0x0
711 22:55:52.380000 DBI_WR = 0x0
712 22:55:52.380470 DBI_RD = 0x0
713 22:55:52.383796 OTF = 0x1
714 22:55:52.386922 ===================================
715 22:55:52.393758 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
716 22:55:52.397416 nWR fixed to 40
717 22:55:52.400232 [ModeRegInit_LP4] CH0 RK0
718 22:55:52.400856 [ModeRegInit_LP4] CH0 RK1
719 22:55:52.403676 [ModeRegInit_LP4] CH1 RK0
720 22:55:52.407131 [ModeRegInit_LP4] CH1 RK1
721 22:55:52.407732 match AC timing 13
722 22:55:52.413472 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
723 22:55:52.417374 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
724 22:55:52.420213 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
725 22:55:52.426948 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
726 22:55:52.430675 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
727 22:55:52.431241 [EMI DOE] emi_dcm 0
728 22:55:52.437063 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
729 22:55:52.437633 ==
730 22:55:52.440032 Dram Type= 6, Freq= 0, CH_0, rank 0
731 22:55:52.443540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
732 22:55:52.444011 ==
733 22:55:52.450103 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
734 22:55:52.453311 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
735 22:55:52.463923 [CA 0] Center 36 (6~67) winsize 62
736 22:55:52.467430 [CA 1] Center 36 (6~67) winsize 62
737 22:55:52.470656 [CA 2] Center 34 (4~65) winsize 62
738 22:55:52.474136 [CA 3] Center 33 (3~64) winsize 62
739 22:55:52.477316 [CA 4] Center 33 (3~64) winsize 62
740 22:55:52.480698 [CA 5] Center 32 (3~62) winsize 60
741 22:55:52.481283
742 22:55:52.483843 [CmdBusTrainingLP45] Vref(ca) range 1: 34
743 22:55:52.484349
744 22:55:52.487474 [CATrainingPosCal] consider 1 rank data
745 22:55:52.490893 u2DelayCellTimex100 = 270/100 ps
746 22:55:52.494441 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
747 22:55:52.497792 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
748 22:55:52.504010 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
749 22:55:52.507231 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
750 22:55:52.511301 CA4 delay=33 (3~64),Diff = 1 PI (7 cell)
751 22:55:52.513964 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
752 22:55:52.514518
753 22:55:52.517426 CA PerBit enable=1, Macro0, CA PI delay=32
754 22:55:52.518012
755 22:55:52.520767 [CBTSetCACLKResult] CA Dly = 32
756 22:55:52.521439 CS Dly: 5 (0~36)
757 22:55:52.521835 ==
758 22:55:52.524304 Dram Type= 6, Freq= 0, CH_0, rank 1
759 22:55:52.531139 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
760 22:55:52.531813 ==
761 22:55:52.534219 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
762 22:55:52.540570 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
763 22:55:52.550144 [CA 0] Center 36 (6~67) winsize 62
764 22:55:52.553868 [CA 1] Center 36 (6~67) winsize 62
765 22:55:52.557167 [CA 2] Center 34 (4~65) winsize 62
766 22:55:52.560509 [CA 3] Center 34 (4~65) winsize 62
767 22:55:52.563850 [CA 4] Center 33 (2~64) winsize 63
768 22:55:52.566967 [CA 5] Center 32 (2~62) winsize 61
769 22:55:52.567486
770 22:55:52.570302 [CmdBusTrainingLP45] Vref(ca) range 1: 34
771 22:55:52.570884
772 22:55:52.573784 [CATrainingPosCal] consider 2 rank data
773 22:55:52.577047 u2DelayCellTimex100 = 270/100 ps
774 22:55:52.579895 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
775 22:55:52.583718 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
776 22:55:52.590271 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
777 22:55:52.593766 CA3 delay=34 (4~64),Diff = 2 PI (14 cell)
778 22:55:52.597056 CA4 delay=33 (3~64),Diff = 1 PI (7 cell)
779 22:55:52.600529 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
780 22:55:52.601108
781 22:55:52.603414 CA PerBit enable=1, Macro0, CA PI delay=32
782 22:55:52.603886
783 22:55:52.606655 [CBTSetCACLKResult] CA Dly = 32
784 22:55:52.607220 CS Dly: 5 (0~37)
785 22:55:52.607665
786 22:55:52.610464 ----->DramcWriteLeveling(PI) begin...
787 22:55:52.613866 ==
788 22:55:52.614350 Dram Type= 6, Freq= 0, CH_0, rank 0
789 22:55:52.620836 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
790 22:55:52.621384 ==
791 22:55:52.621781 Write leveling (Byte 0): 32 => 32
792 22:55:52.624801 Write leveling (Byte 1): 30 => 30
793 22:55:52.628255 DramcWriteLeveling(PI) end<-----
794 22:55:52.628746
795 22:55:52.629123 ==
796 22:55:52.631911 Dram Type= 6, Freq= 0, CH_0, rank 0
797 22:55:52.635111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
798 22:55:52.638581 ==
799 22:55:52.639054 [Gating] SW mode calibration
800 22:55:52.646052 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
801 22:55:52.652665 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
802 22:55:52.655483 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
803 22:55:52.658997 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
804 22:55:52.666064 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
805 22:55:52.668779 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 22:55:52.672860 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 22:55:52.678500 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 22:55:52.682310 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 22:55:52.685796 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 22:55:52.692483 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 22:55:52.695927 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 22:55:52.699098 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
813 22:55:52.705728 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
814 22:55:52.709058 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
815 22:55:52.711970 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
816 22:55:52.718779 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
817 22:55:52.722212 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
818 22:55:52.725798 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
819 22:55:52.732690 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
820 22:55:52.735674 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
821 22:55:52.739386 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
822 22:55:52.742507 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 22:55:52.749158 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 22:55:52.752699 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 22:55:52.755919 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 22:55:52.762187 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 22:55:52.765951 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 22:55:52.769272 0 9 8 | B1->B0 | 2323 3131 | 0 1 | (0 0) (0 0)
829 22:55:52.776261 0 9 12 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
830 22:55:52.779388 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
831 22:55:52.782260 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
832 22:55:52.789275 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
833 22:55:52.792340 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
834 22:55:52.795592 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
835 22:55:52.802888 0 10 4 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
836 22:55:52.805882 0 10 8 | B1->B0 | 3030 2727 | 1 0 | (1 0) (0 0)
837 22:55:52.809091 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
838 22:55:52.815962 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
839 22:55:52.819313 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
840 22:55:52.822765 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
841 22:55:52.826264 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
842 22:55:52.832867 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
843 22:55:52.836178 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
844 22:55:52.838691 0 11 8 | B1->B0 | 3030 3939 | 1 0 | (0 0) (0 0)
845 22:55:52.845337 0 11 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
846 22:55:52.849055 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
847 22:55:52.852700 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
848 22:55:52.859225 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
849 22:55:52.862271 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
850 22:55:52.865581 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
851 22:55:52.872266 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
852 22:55:52.875890 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
853 22:55:52.878881 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
854 22:55:52.885465 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
855 22:55:52.889128 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
856 22:55:52.892549 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
857 22:55:52.899069 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
858 22:55:52.902265 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
859 22:55:52.906048 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
860 22:55:52.909309 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
861 22:55:52.915991 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
862 22:55:52.919258 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
863 22:55:52.922586 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
864 22:55:52.928932 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
865 22:55:52.932900 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
866 22:55:52.935819 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
867 22:55:52.942929 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
868 22:55:52.945742 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
869 22:55:52.949546 Total UI for P1: 0, mck2ui 16
870 22:55:52.952593 best dqsien dly found for B0: ( 0, 14, 4)
871 22:55:52.956142 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
872 22:55:52.959017 Total UI for P1: 0, mck2ui 16
873 22:55:52.962354 best dqsien dly found for B1: ( 0, 14, 10)
874 22:55:52.966150 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
875 22:55:52.969963 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
876 22:55:52.970063
877 22:55:52.972892 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
878 22:55:52.976275 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
879 22:55:52.979985 [Gating] SW calibration Done
880 22:55:52.980067 ==
881 22:55:52.983010 Dram Type= 6, Freq= 0, CH_0, rank 0
882 22:55:52.989911 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
883 22:55:52.989994 ==
884 22:55:52.990059 RX Vref Scan: 0
885 22:55:52.990120
886 22:55:52.992984 RX Vref 0 -> 0, step: 1
887 22:55:52.993093
888 22:55:52.996740 RX Delay -130 -> 252, step: 16
889 22:55:52.999442 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
890 22:55:53.002850 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
891 22:55:53.006630 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
892 22:55:53.009929 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
893 22:55:53.016477 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
894 22:55:53.019844 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
895 22:55:53.023098 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
896 22:55:53.026319 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
897 22:55:53.029551 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
898 22:55:53.036384 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
899 22:55:53.039910 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
900 22:55:53.043260 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
901 22:55:53.047282 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
902 22:55:53.050460 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
903 22:55:53.057233 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
904 22:55:53.060952 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
905 22:55:53.061452 ==
906 22:55:53.063894 Dram Type= 6, Freq= 0, CH_0, rank 0
907 22:55:53.066736 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
908 22:55:53.067183 ==
909 22:55:53.070705 DQS Delay:
910 22:55:53.071126 DQS0 = 0, DQS1 = 0
911 22:55:53.071581 DQM Delay:
912 22:55:53.073711 DQM0 = 92, DQM1 = 85
913 22:55:53.074133 DQ Delay:
914 22:55:53.076905 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =93
915 22:55:53.079769 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101
916 22:55:53.083292 DQ8 =77, DQ9 =69, DQ10 =85, DQ11 =77
917 22:55:53.086990 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
918 22:55:53.087072
919 22:55:53.087137
920 22:55:53.087197 ==
921 22:55:53.090191 Dram Type= 6, Freq= 0, CH_0, rank 0
922 22:55:53.096783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
923 22:55:53.096928 ==
924 22:55:53.097002
925 22:55:53.097071
926 22:55:53.097138 TX Vref Scan disable
927 22:55:53.100534 == TX Byte 0 ==
928 22:55:53.103372 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
929 22:55:53.106822 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
930 22:55:53.110379 == TX Byte 1 ==
931 22:55:53.113354 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
932 22:55:53.116603 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
933 22:55:53.120779 ==
934 22:55:53.123493 Dram Type= 6, Freq= 0, CH_0, rank 0
935 22:55:53.126920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
936 22:55:53.127135 ==
937 22:55:53.139582 TX Vref=22, minBit 8, minWin=27, winSum=450
938 22:55:53.143235 TX Vref=24, minBit 10, minWin=27, winSum=453
939 22:55:53.146782 TX Vref=26, minBit 0, minWin=28, winSum=456
940 22:55:53.149813 TX Vref=28, minBit 0, minWin=28, winSum=456
941 22:55:53.152882 TX Vref=30, minBit 8, minWin=28, winSum=458
942 22:55:53.156622 TX Vref=32, minBit 5, minWin=28, winSum=455
943 22:55:53.163129 [TxChooseVref] Worse bit 8, Min win 28, Win sum 458, Final Vref 30
944 22:55:53.163774
945 22:55:53.166825 Final TX Range 1 Vref 30
946 22:55:53.167452
947 22:55:53.167841 ==
948 22:55:53.169796 Dram Type= 6, Freq= 0, CH_0, rank 0
949 22:55:53.173421 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
950 22:55:53.173998 ==
951 22:55:53.174380
952 22:55:53.174730
953 22:55:53.177142 TX Vref Scan disable
954 22:55:53.179861 == TX Byte 0 ==
955 22:55:53.183698 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
956 22:55:53.187126 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
957 22:55:53.189961 == TX Byte 1 ==
958 22:55:53.193364 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
959 22:55:53.196556 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
960 22:55:53.197051
961 22:55:53.199825 [DATLAT]
962 22:55:53.200296 Freq=800, CH0 RK0
963 22:55:53.200671
964 22:55:53.203374 DATLAT Default: 0xa
965 22:55:53.203854 0, 0xFFFF, sum = 0
966 22:55:53.206755 1, 0xFFFF, sum = 0
967 22:55:53.207369 2, 0xFFFF, sum = 0
968 22:55:53.210532 3, 0xFFFF, sum = 0
969 22:55:53.211103 4, 0xFFFF, sum = 0
970 22:55:53.213541 5, 0xFFFF, sum = 0
971 22:55:53.214169 6, 0xFFFF, sum = 0
972 22:55:53.216955 7, 0xFFFF, sum = 0
973 22:55:53.217433 8, 0xFFFF, sum = 0
974 22:55:53.219986 9, 0x0, sum = 1
975 22:55:53.220460 10, 0x0, sum = 2
976 22:55:53.223463 11, 0x0, sum = 3
977 22:55:53.224099 12, 0x0, sum = 4
978 22:55:53.226587 best_step = 10
979 22:55:53.227077
980 22:55:53.227501 ==
981 22:55:53.230372 Dram Type= 6, Freq= 0, CH_0, rank 0
982 22:55:53.233591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
983 22:55:53.234070 ==
984 22:55:53.236988 RX Vref Scan: 1
985 22:55:53.237455
986 22:55:53.237826 Set Vref Range= 32 -> 127
987 22:55:53.238177
988 22:55:53.240255 RX Vref 32 -> 127, step: 1
989 22:55:53.240724
990 22:55:53.243713 RX Delay -95 -> 252, step: 8
991 22:55:53.244180
992 22:55:53.246934 Set Vref, RX VrefLevel [Byte0]: 32
993 22:55:53.250460 [Byte1]: 32
994 22:55:53.251024
995 22:55:53.253781 Set Vref, RX VrefLevel [Byte0]: 33
996 22:55:53.256867 [Byte1]: 33
997 22:55:53.257360
998 22:55:53.260011 Set Vref, RX VrefLevel [Byte0]: 34
999 22:55:53.263914 [Byte1]: 34
1000 22:55:53.267674
1001 22:55:53.268260 Set Vref, RX VrefLevel [Byte0]: 35
1002 22:55:53.270946 [Byte1]: 35
1003 22:55:53.275874
1004 22:55:53.276432 Set Vref, RX VrefLevel [Byte0]: 36
1005 22:55:53.279504 [Byte1]: 36
1006 22:55:53.283072
1007 22:55:53.283676 Set Vref, RX VrefLevel [Byte0]: 37
1008 22:55:53.286522 [Byte1]: 37
1009 22:55:53.291226
1010 22:55:53.291792 Set Vref, RX VrefLevel [Byte0]: 38
1011 22:55:53.294649 [Byte1]: 38
1012 22:55:53.298349
1013 22:55:53.298822 Set Vref, RX VrefLevel [Byte0]: 39
1014 22:55:53.302203 [Byte1]: 39
1015 22:55:53.306031
1016 22:55:53.306605 Set Vref, RX VrefLevel [Byte0]: 40
1017 22:55:53.309653 [Byte1]: 40
1018 22:55:53.313430
1019 22:55:53.314006 Set Vref, RX VrefLevel [Byte0]: 41
1020 22:55:53.316920 [Byte1]: 41
1021 22:55:53.321398
1022 22:55:53.321964 Set Vref, RX VrefLevel [Byte0]: 42
1023 22:55:53.323913 [Byte1]: 42
1024 22:55:53.328066
1025 22:55:53.328582 Set Vref, RX VrefLevel [Byte0]: 43
1026 22:55:53.331504 [Byte1]: 43
1027 22:55:53.336098
1028 22:55:53.336557 Set Vref, RX VrefLevel [Byte0]: 44
1029 22:55:53.339500 [Byte1]: 44
1030 22:55:53.343379
1031 22:55:53.344021 Set Vref, RX VrefLevel [Byte0]: 45
1032 22:55:53.346953 [Byte1]: 45
1033 22:55:53.350853
1034 22:55:53.351315 Set Vref, RX VrefLevel [Byte0]: 46
1035 22:55:53.354350 [Byte1]: 46
1036 22:55:53.358956
1037 22:55:53.359577 Set Vref, RX VrefLevel [Byte0]: 47
1038 22:55:53.362223 [Byte1]: 47
1039 22:55:53.366896
1040 22:55:53.367522 Set Vref, RX VrefLevel [Byte0]: 48
1041 22:55:53.369323 [Byte1]: 48
1042 22:55:53.374320
1043 22:55:53.374907 Set Vref, RX VrefLevel [Byte0]: 49
1044 22:55:53.377386 [Byte1]: 49
1045 22:55:53.381845
1046 22:55:53.382412 Set Vref, RX VrefLevel [Byte0]: 50
1047 22:55:53.384682 [Byte1]: 50
1048 22:55:53.389684
1049 22:55:53.390303 Set Vref, RX VrefLevel [Byte0]: 51
1050 22:55:53.392467 [Byte1]: 51
1051 22:55:53.397034
1052 22:55:53.397499 Set Vref, RX VrefLevel [Byte0]: 52
1053 22:55:53.400266 [Byte1]: 52
1054 22:55:53.404711
1055 22:55:53.405173 Set Vref, RX VrefLevel [Byte0]: 53
1056 22:55:53.407629 [Byte1]: 53
1057 22:55:53.411732
1058 22:55:53.412195 Set Vref, RX VrefLevel [Byte0]: 54
1059 22:55:53.415214 [Byte1]: 54
1060 22:55:53.419449
1061 22:55:53.419934 Set Vref, RX VrefLevel [Byte0]: 55
1062 22:55:53.423458 [Byte1]: 55
1063 22:55:53.427477
1064 22:55:53.427944 Set Vref, RX VrefLevel [Byte0]: 56
1065 22:55:53.430240 [Byte1]: 56
1066 22:55:53.435295
1067 22:55:53.435904 Set Vref, RX VrefLevel [Byte0]: 57
1068 22:55:53.438025 [Byte1]: 57
1069 22:55:53.442270
1070 22:55:53.442832 Set Vref, RX VrefLevel [Byte0]: 58
1071 22:55:53.446297 [Byte1]: 58
1072 22:55:53.449987
1073 22:55:53.450454 Set Vref, RX VrefLevel [Byte0]: 59
1074 22:55:53.453124 [Byte1]: 59
1075 22:55:53.457596
1076 22:55:53.458057 Set Vref, RX VrefLevel [Byte0]: 60
1077 22:55:53.460969 [Byte1]: 60
1078 22:55:53.465009
1079 22:55:53.465473 Set Vref, RX VrefLevel [Byte0]: 61
1080 22:55:53.468972 [Byte1]: 61
1081 22:55:53.473698
1082 22:55:53.474278 Set Vref, RX VrefLevel [Byte0]: 62
1083 22:55:53.476543 [Byte1]: 62
1084 22:55:53.480771
1085 22:55:53.481346 Set Vref, RX VrefLevel [Byte0]: 63
1086 22:55:53.483515 [Byte1]: 63
1087 22:55:53.488028
1088 22:55:53.488493 Set Vref, RX VrefLevel [Byte0]: 64
1089 22:55:53.491552 [Byte1]: 64
1090 22:55:53.496146
1091 22:55:53.496707 Set Vref, RX VrefLevel [Byte0]: 65
1092 22:55:53.498696 [Byte1]: 65
1093 22:55:53.503564
1094 22:55:53.504026 Set Vref, RX VrefLevel [Byte0]: 66
1095 22:55:53.506712 [Byte1]: 66
1096 22:55:53.510726
1097 22:55:53.511289 Set Vref, RX VrefLevel [Byte0]: 67
1098 22:55:53.514446 [Byte1]: 67
1099 22:55:53.518577
1100 22:55:53.519133 Set Vref, RX VrefLevel [Byte0]: 68
1101 22:55:53.521685 [Byte1]: 68
1102 22:55:53.526021
1103 22:55:53.526489 Set Vref, RX VrefLevel [Byte0]: 69
1104 22:55:53.529219 [Byte1]: 69
1105 22:55:53.533483
1106 22:55:53.534037 Set Vref, RX VrefLevel [Byte0]: 70
1107 22:55:53.537061 [Byte1]: 70
1108 22:55:53.541102
1109 22:55:53.541570 Set Vref, RX VrefLevel [Byte0]: 71
1110 22:55:53.544500 [Byte1]: 71
1111 22:55:53.548870
1112 22:55:53.549424 Set Vref, RX VrefLevel [Byte0]: 72
1113 22:55:53.552206 [Byte1]: 72
1114 22:55:53.556666
1115 22:55:53.557128 Set Vref, RX VrefLevel [Byte0]: 73
1116 22:55:53.559961 [Byte1]: 73
1117 22:55:53.563988
1118 22:55:53.564547 Set Vref, RX VrefLevel [Byte0]: 74
1119 22:55:53.567475 [Byte1]: 74
1120 22:55:53.572144
1121 22:55:53.572704 Set Vref, RX VrefLevel [Byte0]: 75
1122 22:55:53.574597 [Byte1]: 75
1123 22:55:53.579052
1124 22:55:53.579679 Set Vref, RX VrefLevel [Byte0]: 76
1125 22:55:53.582249 [Byte1]: 76
1126 22:55:53.586712
1127 22:55:53.587268 Set Vref, RX VrefLevel [Byte0]: 77
1128 22:55:53.590441 [Byte1]: 77
1129 22:55:53.594698
1130 22:55:53.595274 Final RX Vref Byte 0 = 57 to rank0
1131 22:55:53.597762 Final RX Vref Byte 1 = 58 to rank0
1132 22:55:53.601077 Final RX Vref Byte 0 = 57 to rank1
1133 22:55:53.604389 Final RX Vref Byte 1 = 58 to rank1==
1134 22:55:53.608026 Dram Type= 6, Freq= 0, CH_0, rank 0
1135 22:55:53.611121 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1136 22:55:53.614775 ==
1137 22:55:53.615456 DQS Delay:
1138 22:55:53.615851 DQS0 = 0, DQS1 = 0
1139 22:55:53.617968 DQM Delay:
1140 22:55:53.618430 DQM0 = 92, DQM1 = 86
1141 22:55:53.621074 DQ Delay:
1142 22:55:53.624688 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1143 22:55:53.628043 DQ4 =96, DQ5 =80, DQ6 =100, DQ7 =100
1144 22:55:53.628513 DQ8 =76, DQ9 =76, DQ10 =88, DQ11 =80
1145 22:55:53.634915 DQ12 =92, DQ13 =92, DQ14 =92, DQ15 =92
1146 22:55:53.635521
1147 22:55:53.635896
1148 22:55:53.640877 [DQSOSCAuto] RK0, (LSB)MR18= 0x4d43, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 390 ps
1149 22:55:53.644227 CH0 RK0: MR19=606, MR18=4D43
1150 22:55:53.651306 CH0_RK0: MR19=0x606, MR18=0x4D43, DQSOSC=390, MR23=63, INC=97, DEC=64
1151 22:55:53.651801
1152 22:55:53.654600 ----->DramcWriteLeveling(PI) begin...
1153 22:55:53.655199 ==
1154 22:55:53.657609 Dram Type= 6, Freq= 0, CH_0, rank 1
1155 22:55:53.661326 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1156 22:55:53.661893 ==
1157 22:55:53.664120 Write leveling (Byte 0): 34 => 34
1158 22:55:53.667660 Write leveling (Byte 1): 29 => 29
1159 22:55:53.671014 DramcWriteLeveling(PI) end<-----
1160 22:55:53.671517
1161 22:55:53.671885 ==
1162 22:55:53.674745 Dram Type= 6, Freq= 0, CH_0, rank 1
1163 22:55:53.677887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1164 22:55:53.678447 ==
1165 22:55:53.681383 [Gating] SW mode calibration
1166 22:55:53.687714 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1167 22:55:53.727666 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1168 22:55:53.728759 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1169 22:55:53.729163 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1170 22:55:53.729519 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1171 22:55:53.729856 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 22:55:53.730183 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 22:55:53.730501 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 22:55:53.730816 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 22:55:53.731525 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 22:55:53.731872 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 22:55:53.738669 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 22:55:53.742253 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 22:55:53.745007 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 22:55:53.751521 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 22:55:53.755481 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 22:55:53.758292 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 22:55:53.765103 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 22:55:53.768145 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 22:55:53.771664 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1186 22:55:53.778749 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1187 22:55:53.782117 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 22:55:53.785602 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 22:55:53.788724 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 22:55:53.795991 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 22:55:53.798715 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 22:55:53.801903 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 22:55:53.809044 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 22:55:53.811697 0 9 8 | B1->B0 | 2e2d 2e2e | 1 1 | (0 0) (0 0)
1195 22:55:53.815378 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1196 22:55:53.822199 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1197 22:55:53.825592 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1198 22:55:53.828887 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1199 22:55:53.835586 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1200 22:55:53.838851 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1201 22:55:53.842415 0 10 4 | B1->B0 | 3232 3434 | 0 0 | (0 0) (0 0)
1202 22:55:53.849115 0 10 8 | B1->B0 | 2828 2c2c | 0 0 | (0 0) (0 0)
1203 22:55:53.852618 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1204 22:55:53.856192 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1205 22:55:53.859608 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1206 22:55:53.863399 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1207 22:55:53.871160 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1208 22:55:53.874464 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1209 22:55:53.877297 0 11 4 | B1->B0 | 2424 2323 | 1 0 | (0 0) (0 0)
1210 22:55:53.881192 0 11 8 | B1->B0 | 3c3c 3d3d | 1 0 | (0 0) (0 0)
1211 22:55:53.888368 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1212 22:55:53.891714 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1213 22:55:53.894826 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1214 22:55:53.901518 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1215 22:55:53.904800 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1216 22:55:53.908698 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1217 22:55:53.911688 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1218 22:55:53.918353 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1219 22:55:53.921861 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 22:55:53.925493 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1221 22:55:53.931852 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1222 22:55:53.935552 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1223 22:55:53.938905 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1224 22:55:53.945343 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1225 22:55:53.948172 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1226 22:55:53.952077 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1227 22:55:53.958896 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1228 22:55:53.961937 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1229 22:55:53.965583 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1230 22:55:53.972061 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1231 22:55:53.975496 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1232 22:55:53.978993 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1233 22:55:53.981985 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1234 22:55:53.988406 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1235 22:55:53.991747 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1236 22:55:53.995060 Total UI for P1: 0, mck2ui 16
1237 22:55:53.999034 best dqsien dly found for B0: ( 0, 14, 8)
1238 22:55:54.002336 Total UI for P1: 0, mck2ui 16
1239 22:55:54.005251 best dqsien dly found for B1: ( 0, 14, 8)
1240 22:55:54.008571 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1241 22:55:54.011812 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1242 22:55:54.012295
1243 22:55:54.015737 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1244 22:55:54.018807 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1245 22:55:54.022488 [Gating] SW calibration Done
1246 22:55:54.023063 ==
1247 22:55:54.025790 Dram Type= 6, Freq= 0, CH_0, rank 1
1248 22:55:54.028648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1249 22:55:54.031798 ==
1250 22:55:54.032263 RX Vref Scan: 0
1251 22:55:54.032631
1252 22:55:54.035170 RX Vref 0 -> 0, step: 1
1253 22:55:54.035683
1254 22:55:54.038700 RX Delay -130 -> 252, step: 16
1255 22:55:54.041861 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1256 22:55:54.044987 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1257 22:55:54.049151 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
1258 22:55:54.051864 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1259 22:55:54.059132 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1260 22:55:54.061998 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1261 22:55:54.065215 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1262 22:55:54.068331 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1263 22:55:54.071210 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1264 22:55:54.074884 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1265 22:55:54.081708 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1266 22:55:54.085169 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1267 22:55:54.087854 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1268 22:55:54.091821 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1269 22:55:54.098105 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1270 22:55:54.101578 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1271 22:55:54.101661 ==
1272 22:55:54.104682 Dram Type= 6, Freq= 0, CH_0, rank 1
1273 22:55:54.108079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1274 22:55:54.108162 ==
1275 22:55:54.111223 DQS Delay:
1276 22:55:54.111351 DQS0 = 0, DQS1 = 0
1277 22:55:54.111434 DQM Delay:
1278 22:55:54.114756 DQM0 = 93, DQM1 = 86
1279 22:55:54.114838 DQ Delay:
1280 22:55:54.118117 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =93
1281 22:55:54.121440 DQ4 =93, DQ5 =85, DQ6 =93, DQ7 =101
1282 22:55:54.124595 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =77
1283 22:55:54.128303 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1284 22:55:54.128385
1285 22:55:54.128450
1286 22:55:54.128511 ==
1287 22:55:54.131638 Dram Type= 6, Freq= 0, CH_0, rank 1
1288 22:55:54.135095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1289 22:55:54.137919 ==
1290 22:55:54.138001
1291 22:55:54.138065
1292 22:55:54.138123 TX Vref Scan disable
1293 22:55:54.141437 == TX Byte 0 ==
1294 22:55:54.144775 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1295 22:55:54.148215 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1296 22:55:54.151207 == TX Byte 1 ==
1297 22:55:54.154778 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1298 22:55:54.157968 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1299 22:55:54.161466 ==
1300 22:55:54.161547 Dram Type= 6, Freq= 0, CH_0, rank 1
1301 22:55:54.167936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1302 22:55:54.168018 ==
1303 22:55:54.180820 TX Vref=22, minBit 8, minWin=27, winSum=445
1304 22:55:54.184393 TX Vref=24, minBit 1, minWin=28, winSum=452
1305 22:55:54.187858 TX Vref=26, minBit 1, minWin=28, winSum=456
1306 22:55:54.190767 TX Vref=28, minBit 7, minWin=28, winSum=456
1307 22:55:54.194241 TX Vref=30, minBit 7, minWin=28, winSum=459
1308 22:55:54.197685 TX Vref=32, minBit 1, minWin=28, winSum=456
1309 22:55:54.204418 [TxChooseVref] Worse bit 7, Min win 28, Win sum 459, Final Vref 30
1310 22:55:54.204529
1311 22:55:54.207787 Final TX Range 1 Vref 30
1312 22:55:54.207868
1313 22:55:54.207931 ==
1314 22:55:54.210973 Dram Type= 6, Freq= 0, CH_0, rank 1
1315 22:55:54.214424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1316 22:55:54.214505 ==
1317 22:55:54.214569
1318 22:55:54.214627
1319 22:55:54.217662 TX Vref Scan disable
1320 22:55:54.220905 == TX Byte 0 ==
1321 22:55:54.224495 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1322 22:55:54.227864 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1323 22:55:54.231123 == TX Byte 1 ==
1324 22:55:54.234433 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1325 22:55:54.237503 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1326 22:55:54.241101
1327 22:55:54.241181 [DATLAT]
1328 22:55:54.241244 Freq=800, CH0 RK1
1329 22:55:54.241304
1330 22:55:54.244820 DATLAT Default: 0xa
1331 22:55:54.244900 0, 0xFFFF, sum = 0
1332 22:55:54.248132 1, 0xFFFF, sum = 0
1333 22:55:54.248214 2, 0xFFFF, sum = 0
1334 22:55:54.251309 3, 0xFFFF, sum = 0
1335 22:55:54.251434 4, 0xFFFF, sum = 0
1336 22:55:54.254658 5, 0xFFFF, sum = 0
1337 22:55:54.254739 6, 0xFFFF, sum = 0
1338 22:55:54.257869 7, 0xFFFF, sum = 0
1339 22:55:54.257951 8, 0xFFFF, sum = 0
1340 22:55:54.260916 9, 0x0, sum = 1
1341 22:55:54.260997 10, 0x0, sum = 2
1342 22:55:54.264644 11, 0x0, sum = 3
1343 22:55:54.264725 12, 0x0, sum = 4
1344 22:55:54.267650 best_step = 10
1345 22:55:54.267729
1346 22:55:54.267791 ==
1347 22:55:54.270978 Dram Type= 6, Freq= 0, CH_0, rank 1
1348 22:55:54.274284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1349 22:55:54.274365 ==
1350 22:55:54.277646 RX Vref Scan: 0
1351 22:55:54.277725
1352 22:55:54.277787 RX Vref 0 -> 0, step: 1
1353 22:55:54.277847
1354 22:55:54.281349 RX Delay -79 -> 252, step: 8
1355 22:55:54.287884 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1356 22:55:54.291074 iDelay=209, Bit 1, Center 96 (-7 ~ 200) 208
1357 22:55:54.294340 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1358 22:55:54.297752 iDelay=209, Bit 3, Center 88 (-23 ~ 200) 224
1359 22:55:54.301351 iDelay=209, Bit 4, Center 96 (-15 ~ 208) 224
1360 22:55:54.308019 iDelay=209, Bit 5, Center 88 (-23 ~ 200) 224
1361 22:55:54.311127 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1362 22:55:54.314361 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1363 22:55:54.318178 iDelay=209, Bit 8, Center 72 (-39 ~ 184) 224
1364 22:55:54.321315 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1365 22:55:54.324609 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1366 22:55:54.331176 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1367 22:55:54.334754 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1368 22:55:54.337932 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
1369 22:55:54.341223 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1370 22:55:54.347763 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
1371 22:55:54.347895 ==
1372 22:55:54.351187 Dram Type= 6, Freq= 0, CH_0, rank 1
1373 22:55:54.354747 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1374 22:55:54.354831 ==
1375 22:55:54.354939 DQS Delay:
1376 22:55:54.358312 DQS0 = 0, DQS1 = 0
1377 22:55:54.358412 DQM Delay:
1378 22:55:54.361457 DQM0 = 93, DQM1 = 82
1379 22:55:54.361555 DQ Delay:
1380 22:55:54.364854 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1381 22:55:54.367999 DQ4 =96, DQ5 =88, DQ6 =100, DQ7 =100
1382 22:55:54.371897 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =76
1383 22:55:54.375053 DQ12 =84, DQ13 =88, DQ14 =92, DQ15 =92
1384 22:55:54.375138
1385 22:55:54.375241
1386 22:55:54.381410 [DQSOSCAuto] RK1, (LSB)MR18= 0x4111, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 393 ps
1387 22:55:54.384685 CH0 RK1: MR19=606, MR18=4111
1388 22:55:54.391307 CH0_RK1: MR19=0x606, MR18=0x4111, DQSOSC=393, MR23=63, INC=95, DEC=63
1389 22:55:54.394842 [RxdqsGatingPostProcess] freq 800
1390 22:55:54.401327 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1391 22:55:54.401410 Pre-setting of DQS Precalculation
1392 22:55:54.408047 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1393 22:55:54.408131 ==
1394 22:55:54.411195 Dram Type= 6, Freq= 0, CH_1, rank 0
1395 22:55:54.414817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1396 22:55:54.414901 ==
1397 22:55:54.421347 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1398 22:55:54.427946 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1399 22:55:54.436154 [CA 0] Center 36 (6~67) winsize 62
1400 22:55:54.439642 [CA 1] Center 36 (6~67) winsize 62
1401 22:55:54.442404 [CA 2] Center 35 (5~66) winsize 62
1402 22:55:54.446281 [CA 3] Center 35 (5~65) winsize 61
1403 22:55:54.449254 [CA 4] Center 35 (5~65) winsize 61
1404 22:55:54.452424 [CA 5] Center 33 (3~64) winsize 62
1405 22:55:54.452508
1406 22:55:54.456117 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1407 22:55:54.456201
1408 22:55:54.459278 [CATrainingPosCal] consider 1 rank data
1409 22:55:54.462399 u2DelayCellTimex100 = 270/100 ps
1410 22:55:54.466003 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1411 22:55:54.469183 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1412 22:55:54.476064 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
1413 22:55:54.479037 CA3 delay=35 (5~65),Diff = 2 PI (14 cell)
1414 22:55:54.482817 CA4 delay=35 (5~65),Diff = 2 PI (14 cell)
1415 22:55:54.486327 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1416 22:55:54.486411
1417 22:55:54.489293 CA PerBit enable=1, Macro0, CA PI delay=33
1418 22:55:54.489376
1419 22:55:54.493011 [CBTSetCACLKResult] CA Dly = 33
1420 22:55:54.493095 CS Dly: 6 (0~37)
1421 22:55:54.496145 ==
1422 22:55:54.496228 Dram Type= 6, Freq= 0, CH_1, rank 1
1423 22:55:54.503072 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1424 22:55:54.503526 ==
1425 22:55:54.506715 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1426 22:55:54.513151 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1427 22:55:54.523379 [CA 0] Center 36 (6~67) winsize 62
1428 22:55:54.526949 [CA 1] Center 37 (6~68) winsize 63
1429 22:55:54.530654 [CA 2] Center 35 (5~66) winsize 62
1430 22:55:54.534699 [CA 3] Center 35 (5~65) winsize 61
1431 22:55:54.538206 [CA 4] Center 35 (5~66) winsize 62
1432 22:55:54.538780 [CA 5] Center 34 (4~65) winsize 62
1433 22:55:54.542009
1434 22:55:54.545816 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1435 22:55:54.546248
1436 22:55:54.549676 [CATrainingPosCal] consider 2 rank data
1437 22:55:54.550107 u2DelayCellTimex100 = 270/100 ps
1438 22:55:54.553027 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1439 22:55:54.556117 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1440 22:55:54.559436 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1441 22:55:54.566240 CA3 delay=35 (5~65),Diff = 1 PI (7 cell)
1442 22:55:54.569739 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1443 22:55:54.572966 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1444 22:55:54.573390
1445 22:55:54.576506 CA PerBit enable=1, Macro0, CA PI delay=34
1446 22:55:54.577034
1447 22:55:54.579910 [CBTSetCACLKResult] CA Dly = 34
1448 22:55:54.580333 CS Dly: 6 (0~38)
1449 22:55:54.580669
1450 22:55:54.582829 ----->DramcWriteLeveling(PI) begin...
1451 22:55:54.583257 ==
1452 22:55:54.586595 Dram Type= 6, Freq= 0, CH_1, rank 0
1453 22:55:54.593091 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1454 22:55:54.593616 ==
1455 22:55:54.596623 Write leveling (Byte 0): 28 => 28
1456 22:55:54.600396 Write leveling (Byte 1): 28 => 28
1457 22:55:54.600923 DramcWriteLeveling(PI) end<-----
1458 22:55:54.601263
1459 22:55:54.603403 ==
1460 22:55:54.606270 Dram Type= 6, Freq= 0, CH_1, rank 0
1461 22:55:54.610208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1462 22:55:54.610775 ==
1463 22:55:54.613253 [Gating] SW mode calibration
1464 22:55:54.620014 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1465 22:55:54.622825 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1466 22:55:54.630097 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1467 22:55:54.632870 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1468 22:55:54.636351 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 22:55:54.643537 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 22:55:54.646693 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 22:55:54.650034 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 22:55:54.653364 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 22:55:54.660141 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 22:55:54.663648 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 22:55:54.666530 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 22:55:54.673621 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 22:55:54.677084 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 22:55:54.680168 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 22:55:54.686885 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 22:55:54.689958 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 22:55:54.693607 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 22:55:54.699960 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1483 22:55:54.703695 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 22:55:54.706725 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 22:55:54.713365 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 22:55:54.717101 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 22:55:54.720638 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 22:55:54.726838 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 22:55:54.730361 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 22:55:54.733292 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 22:55:54.736756 0 9 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1492 22:55:54.743927 0 9 8 | B1->B0 | 3030 3434 | 0 0 | (0 0) (0 0)
1493 22:55:54.747205 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1494 22:55:54.750323 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1495 22:55:54.756713 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1496 22:55:54.760112 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1497 22:55:54.763797 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1498 22:55:54.770218 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
1499 22:55:54.773473 0 10 4 | B1->B0 | 3131 2e2e | 0 0 | (1 1) (0 1)
1500 22:55:54.776755 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1501 22:55:54.783495 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1502 22:55:54.787197 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1503 22:55:54.790143 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1504 22:55:54.797571 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1505 22:55:54.800027 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1506 22:55:54.803661 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1507 22:55:54.810816 0 11 4 | B1->B0 | 2626 3434 | 0 1 | (0 0) (0 0)
1508 22:55:54.814027 0 11 8 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
1509 22:55:54.816983 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1510 22:55:54.820603 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1511 22:55:54.827402 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1512 22:55:54.830790 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1513 22:55:54.833697 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1514 22:55:54.840285 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1515 22:55:54.843881 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1516 22:55:54.847426 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 22:55:54.853697 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1518 22:55:54.857010 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1519 22:55:54.860353 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1520 22:55:54.867562 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1521 22:55:54.870984 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1522 22:55:54.873545 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1523 22:55:54.880942 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1524 22:55:54.883805 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1525 22:55:54.887283 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1526 22:55:54.893919 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1527 22:55:54.897572 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1528 22:55:54.901163 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1529 22:55:54.903699 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1530 22:55:54.910934 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1531 22:55:54.914542 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1532 22:55:54.917809 Total UI for P1: 0, mck2ui 16
1533 22:55:54.920561 best dqsien dly found for B0: ( 0, 14, 2)
1534 22:55:54.924321 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1535 22:55:54.928012 Total UI for P1: 0, mck2ui 16
1536 22:55:54.930797 best dqsien dly found for B1: ( 0, 14, 2)
1537 22:55:54.934102 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1538 22:55:54.937283 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1539 22:55:54.937755
1540 22:55:54.944412 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1541 22:55:54.947724 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1542 22:55:54.948196 [Gating] SW calibration Done
1543 22:55:54.950666 ==
1544 22:55:54.951153 Dram Type= 6, Freq= 0, CH_1, rank 0
1545 22:55:54.957586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1546 22:55:54.958153 ==
1547 22:55:54.958530 RX Vref Scan: 0
1548 22:55:54.958880
1549 22:55:54.961037 RX Vref 0 -> 0, step: 1
1550 22:55:54.961504
1551 22:55:54.964237 RX Delay -130 -> 252, step: 16
1552 22:55:54.967669 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1553 22:55:54.970883 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1554 22:55:54.973997 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1555 22:55:54.981004 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1556 22:55:54.984597 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1557 22:55:54.987784 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1558 22:55:54.990847 iDelay=222, Bit 6, Center 109 (-2 ~ 221) 224
1559 22:55:54.994340 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1560 22:55:54.997621 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1561 22:55:55.004604 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1562 22:55:55.007404 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1563 22:55:55.011295 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1564 22:55:55.014859 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1565 22:55:55.021501 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1566 22:55:55.024371 iDelay=222, Bit 14, Center 101 (-2 ~ 205) 208
1567 22:55:55.028007 iDelay=222, Bit 15, Center 101 (-2 ~ 205) 208
1568 22:55:55.028569 ==
1569 22:55:55.030842 Dram Type= 6, Freq= 0, CH_1, rank 0
1570 22:55:55.034485 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1571 22:55:55.034948 ==
1572 22:55:55.037898 DQS Delay:
1573 22:55:55.038460 DQS0 = 0, DQS1 = 0
1574 22:55:55.038832 DQM Delay:
1575 22:55:55.040977 DQM0 = 94, DQM1 = 90
1576 22:55:55.041531 DQ Delay:
1577 22:55:55.044970 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1578 22:55:55.048337 DQ4 =93, DQ5 =109, DQ6 =109, DQ7 =93
1579 22:55:55.051302 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =85
1580 22:55:55.054523 DQ12 =93, DQ13 =101, DQ14 =101, DQ15 =101
1581 22:55:55.054989
1582 22:55:55.055399
1583 22:55:55.055756 ==
1584 22:55:55.058286 Dram Type= 6, Freq= 0, CH_1, rank 0
1585 22:55:55.064769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1586 22:55:55.065362 ==
1587 22:55:55.065732
1588 22:55:55.066070
1589 22:55:55.066392 TX Vref Scan disable
1590 22:55:55.068387 == TX Byte 0 ==
1591 22:55:55.072002 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1592 22:55:55.074956 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1593 22:55:55.078741 == TX Byte 1 ==
1594 22:55:55.081859 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1595 22:55:55.085385 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1596 22:55:55.088701 ==
1597 22:55:55.091658 Dram Type= 6, Freq= 0, CH_1, rank 0
1598 22:55:55.094925 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1599 22:55:55.095531 ==
1600 22:55:55.107918 TX Vref=22, minBit 4, minWin=26, winSum=440
1601 22:55:55.111522 TX Vref=24, minBit 0, minWin=27, winSum=442
1602 22:55:55.114514 TX Vref=26, minBit 1, minWin=27, winSum=446
1603 22:55:55.118164 TX Vref=28, minBit 2, minWin=27, winSum=449
1604 22:55:55.120989 TX Vref=30, minBit 1, minWin=27, winSum=453
1605 22:55:55.124649 TX Vref=32, minBit 1, minWin=27, winSum=450
1606 22:55:55.131357 [TxChooseVref] Worse bit 1, Min win 27, Win sum 453, Final Vref 30
1607 22:55:55.131913
1608 22:55:55.134820 Final TX Range 1 Vref 30
1609 22:55:55.135320
1610 22:55:55.135843 ==
1611 22:55:55.137704 Dram Type= 6, Freq= 0, CH_1, rank 0
1612 22:55:55.141476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1613 22:55:55.142054 ==
1614 22:55:55.142569
1615 22:55:55.142931
1616 22:55:55.144806 TX Vref Scan disable
1617 22:55:55.148164 == TX Byte 0 ==
1618 22:55:55.151280 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1619 22:55:55.154845 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1620 22:55:55.158446 == TX Byte 1 ==
1621 22:55:55.161647 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1622 22:55:55.164921 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1623 22:55:55.165483
1624 22:55:55.167892 [DATLAT]
1625 22:55:55.168356 Freq=800, CH1 RK0
1626 22:55:55.168732
1627 22:55:55.171731 DATLAT Default: 0xa
1628 22:55:55.172288 0, 0xFFFF, sum = 0
1629 22:55:55.174549 1, 0xFFFF, sum = 0
1630 22:55:55.175021 2, 0xFFFF, sum = 0
1631 22:55:55.178419 3, 0xFFFF, sum = 0
1632 22:55:55.178992 4, 0xFFFF, sum = 0
1633 22:55:55.181724 5, 0xFFFF, sum = 0
1634 22:55:55.182291 6, 0xFFFF, sum = 0
1635 22:55:55.184687 7, 0xFFFF, sum = 0
1636 22:55:55.185263 8, 0xFFFF, sum = 0
1637 22:55:55.188059 9, 0x0, sum = 1
1638 22:55:55.188532 10, 0x0, sum = 2
1639 22:55:55.191222 11, 0x0, sum = 3
1640 22:55:55.191721 12, 0x0, sum = 4
1641 22:55:55.194995 best_step = 10
1642 22:55:55.195598
1643 22:55:55.195979 ==
1644 22:55:55.198067 Dram Type= 6, Freq= 0, CH_1, rank 0
1645 22:55:55.201297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1646 22:55:55.201766 ==
1647 22:55:55.202135 RX Vref Scan: 1
1648 22:55:55.202481
1649 22:55:55.204863 Set Vref Range= 32 -> 127
1650 22:55:55.205430
1651 22:55:55.207998 RX Vref 32 -> 127, step: 1
1652 22:55:55.208466
1653 22:55:55.211550 RX Delay -79 -> 252, step: 8
1654 22:55:55.212020
1655 22:55:55.214901 Set Vref, RX VrefLevel [Byte0]: 32
1656 22:55:55.218442 [Byte1]: 32
1657 22:55:55.219009
1658 22:55:55.221627 Set Vref, RX VrefLevel [Byte0]: 33
1659 22:55:55.225311 [Byte1]: 33
1660 22:55:55.225875
1661 22:55:55.228705 Set Vref, RX VrefLevel [Byte0]: 34
1662 22:55:55.231707 [Byte1]: 34
1663 22:55:55.235445
1664 22:55:55.235910 Set Vref, RX VrefLevel [Byte0]: 35
1665 22:55:55.238428 [Byte1]: 35
1666 22:55:55.242826
1667 22:55:55.243421 Set Vref, RX VrefLevel [Byte0]: 36
1668 22:55:55.245863 [Byte1]: 36
1669 22:55:55.250134
1670 22:55:55.250691 Set Vref, RX VrefLevel [Byte0]: 37
1671 22:55:55.253836 [Byte1]: 37
1672 22:55:55.258093
1673 22:55:55.258656 Set Vref, RX VrefLevel [Byte0]: 38
1674 22:55:55.260681 [Byte1]: 38
1675 22:55:55.265789
1676 22:55:55.266343 Set Vref, RX VrefLevel [Byte0]: 39
1677 22:55:55.268582 [Byte1]: 39
1678 22:55:55.272784
1679 22:55:55.273367 Set Vref, RX VrefLevel [Byte0]: 40
1680 22:55:55.276212 [Byte1]: 40
1681 22:55:55.280284
1682 22:55:55.280840 Set Vref, RX VrefLevel [Byte0]: 41
1683 22:55:55.284003 [Byte1]: 41
1684 22:55:55.288184
1685 22:55:55.288739 Set Vref, RX VrefLevel [Byte0]: 42
1686 22:55:55.291117 [Byte1]: 42
1687 22:55:55.295391
1688 22:55:55.295948 Set Vref, RX VrefLevel [Byte0]: 43
1689 22:55:55.299072 [Byte1]: 43
1690 22:55:55.302923
1691 22:55:55.303541 Set Vref, RX VrefLevel [Byte0]: 44
1692 22:55:55.306017 [Byte1]: 44
1693 22:55:55.310442
1694 22:55:55.310999 Set Vref, RX VrefLevel [Byte0]: 45
1695 22:55:55.313653 [Byte1]: 45
1696 22:55:55.318261
1697 22:55:55.318814 Set Vref, RX VrefLevel [Byte0]: 46
1698 22:55:55.321036 [Byte1]: 46
1699 22:55:55.325880
1700 22:55:55.326453 Set Vref, RX VrefLevel [Byte0]: 47
1701 22:55:55.329133 [Byte1]: 47
1702 22:55:55.333138
1703 22:55:55.333615 Set Vref, RX VrefLevel [Byte0]: 48
1704 22:55:55.336254 [Byte1]: 48
1705 22:55:55.341054
1706 22:55:55.341627 Set Vref, RX VrefLevel [Byte0]: 49
1707 22:55:55.343837 [Byte1]: 49
1708 22:55:55.348429
1709 22:55:55.348892 Set Vref, RX VrefLevel [Byte0]: 50
1710 22:55:55.351629 [Byte1]: 50
1711 22:55:55.356087
1712 22:55:55.356552 Set Vref, RX VrefLevel [Byte0]: 51
1713 22:55:55.358934 [Byte1]: 51
1714 22:55:55.363307
1715 22:55:55.363797 Set Vref, RX VrefLevel [Byte0]: 52
1716 22:55:55.366808 [Byte1]: 52
1717 22:55:55.371104
1718 22:55:55.371700 Set Vref, RX VrefLevel [Byte0]: 53
1719 22:55:55.374101 [Byte1]: 53
1720 22:55:55.378981
1721 22:55:55.379573 Set Vref, RX VrefLevel [Byte0]: 54
1722 22:55:55.382355 [Byte1]: 54
1723 22:55:55.386455
1724 22:55:55.387012 Set Vref, RX VrefLevel [Byte0]: 55
1725 22:55:55.389959 [Byte1]: 55
1726 22:55:55.393567
1727 22:55:55.394125 Set Vref, RX VrefLevel [Byte0]: 56
1728 22:55:55.397126 [Byte1]: 56
1729 22:55:55.401440
1730 22:55:55.401996 Set Vref, RX VrefLevel [Byte0]: 57
1731 22:55:55.404130 [Byte1]: 57
1732 22:55:55.408546
1733 22:55:55.411937 Set Vref, RX VrefLevel [Byte0]: 58
1734 22:55:55.415190 [Byte1]: 58
1735 22:55:55.415799
1736 22:55:55.418331 Set Vref, RX VrefLevel [Byte0]: 59
1737 22:55:55.422022 [Byte1]: 59
1738 22:55:55.422489
1739 22:55:55.425253 Set Vref, RX VrefLevel [Byte0]: 60
1740 22:55:55.428452 [Byte1]: 60
1741 22:55:55.428919
1742 22:55:55.431701 Set Vref, RX VrefLevel [Byte0]: 61
1743 22:55:55.435007 [Byte1]: 61
1744 22:55:55.438617
1745 22:55:55.439084 Set Vref, RX VrefLevel [Byte0]: 62
1746 22:55:55.442246 [Byte1]: 62
1747 22:55:55.446228
1748 22:55:55.446787 Set Vref, RX VrefLevel [Byte0]: 63
1749 22:55:55.449366 [Byte1]: 63
1750 22:55:55.454244
1751 22:55:55.454840 Set Vref, RX VrefLevel [Byte0]: 64
1752 22:55:55.457559 [Byte1]: 64
1753 22:55:55.461932
1754 22:55:55.462488 Set Vref, RX VrefLevel [Byte0]: 65
1755 22:55:55.464764 [Byte1]: 65
1756 22:55:55.468907
1757 22:55:55.469370 Set Vref, RX VrefLevel [Byte0]: 66
1758 22:55:55.472435 [Byte1]: 66
1759 22:55:55.476738
1760 22:55:55.477290 Set Vref, RX VrefLevel [Byte0]: 67
1761 22:55:55.480302 [Byte1]: 67
1762 22:55:55.483811
1763 22:55:55.484275 Set Vref, RX VrefLevel [Byte0]: 68
1764 22:55:55.487549 [Byte1]: 68
1765 22:55:55.491587
1766 22:55:55.492144 Set Vref, RX VrefLevel [Byte0]: 69
1767 22:55:55.495140 [Byte1]: 69
1768 22:55:55.499069
1769 22:55:55.499676 Set Vref, RX VrefLevel [Byte0]: 70
1770 22:55:55.502500 [Byte1]: 70
1771 22:55:55.506711
1772 22:55:55.507238 Set Vref, RX VrefLevel [Byte0]: 71
1773 22:55:55.510174 [Byte1]: 71
1774 22:55:55.514368
1775 22:55:55.514831 Set Vref, RX VrefLevel [Byte0]: 72
1776 22:55:55.517877 [Byte1]: 72
1777 22:55:55.521750
1778 22:55:55.522218 Final RX Vref Byte 0 = 58 to rank0
1779 22:55:55.525506 Final RX Vref Byte 1 = 53 to rank0
1780 22:55:55.528457 Final RX Vref Byte 0 = 58 to rank1
1781 22:55:55.531567 Final RX Vref Byte 1 = 53 to rank1==
1782 22:55:55.535000 Dram Type= 6, Freq= 0, CH_1, rank 0
1783 22:55:55.541701 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1784 22:55:55.542168 ==
1785 22:55:55.542532 DQS Delay:
1786 22:55:55.542870 DQS0 = 0, DQS1 = 0
1787 22:55:55.545030 DQM Delay:
1788 22:55:55.545649 DQM0 = 96, DQM1 = 89
1789 22:55:55.548526 DQ Delay:
1790 22:55:55.551951 DQ0 =100, DQ1 =88, DQ2 =84, DQ3 =92
1791 22:55:55.555211 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =96
1792 22:55:55.558669 DQ8 =76, DQ9 =80, DQ10 =88, DQ11 =84
1793 22:55:55.561608 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
1794 22:55:55.562217
1795 22:55:55.562588
1796 22:55:55.568806 [DQSOSCAuto] RK0, (LSB)MR18= 0x2b48, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
1797 22:55:55.571673 CH1 RK0: MR19=606, MR18=2B48
1798 22:55:55.579049 CH1_RK0: MR19=0x606, MR18=0x2B48, DQSOSC=391, MR23=63, INC=96, DEC=64
1799 22:55:55.579660
1800 22:55:55.582546 ----->DramcWriteLeveling(PI) begin...
1801 22:55:55.583104 ==
1802 22:55:55.585354 Dram Type= 6, Freq= 0, CH_1, rank 1
1803 22:55:55.589226 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1804 22:55:55.589782 ==
1805 22:55:55.591989 Write leveling (Byte 0): 28 => 28
1806 22:55:55.595714 Write leveling (Byte 1): 27 => 27
1807 22:55:55.598442 DramcWriteLeveling(PI) end<-----
1808 22:55:55.598899
1809 22:55:55.599260 ==
1810 22:55:55.601595 Dram Type= 6, Freq= 0, CH_1, rank 1
1811 22:55:55.605032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1812 22:55:55.605495 ==
1813 22:55:55.608301 [Gating] SW mode calibration
1814 22:55:55.615054 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1815 22:55:55.621967 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1816 22:55:55.625063 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1817 22:55:55.628291 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1818 22:55:55.635441 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 22:55:55.638611 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 22:55:55.642118 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 22:55:55.648379 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 22:55:55.651758 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 22:55:55.655617 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 22:55:55.662290 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 22:55:55.665317 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 22:55:55.668861 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 22:55:55.672242 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 22:55:55.679019 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 22:55:55.682508 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 22:55:55.686194 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 22:55:55.692859 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 22:55:55.695741 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1833 22:55:55.699295 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1834 22:55:55.706026 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 22:55:55.709557 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 22:55:55.713183 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 22:55:55.719155 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 22:55:55.722557 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 22:55:55.726153 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 22:55:55.732277 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 22:55:55.736121 0 9 4 | B1->B0 | 3131 2323 | 0 0 | (0 0) (1 1)
1842 22:55:55.738890 0 9 8 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
1843 22:55:55.742501 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1844 22:55:55.749318 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1845 22:55:55.752463 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1846 22:55:55.755909 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1847 22:55:55.762554 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1848 22:55:55.766013 0 10 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1849 22:55:55.769580 0 10 4 | B1->B0 | 2b2b 3030 | 0 0 | (0 1) (1 0)
1850 22:55:55.775740 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 22:55:55.779017 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 22:55:55.782821 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 22:55:55.789655 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 22:55:55.793064 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 22:55:55.796249 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 22:55:55.802793 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1857 22:55:55.806392 0 11 4 | B1->B0 | 3939 2f2f | 0 1 | (0 0) (0 0)
1858 22:55:55.809799 0 11 8 | B1->B0 | 4646 4242 | 0 0 | (0 0) (0 0)
1859 22:55:55.813138 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1860 22:55:55.819420 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1861 22:55:55.822723 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1862 22:55:55.826856 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1863 22:55:55.833147 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1864 22:55:55.836314 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1865 22:55:55.839436 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1866 22:55:55.846425 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 22:55:55.849374 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 22:55:55.853060 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 22:55:55.859429 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 22:55:55.862935 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 22:55:55.866324 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 22:55:55.873205 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 22:55:55.876371 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 22:55:55.879364 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 22:55:55.886277 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 22:55:55.889407 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 22:55:55.892965 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 22:55:55.896026 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 22:55:55.903034 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1880 22:55:55.906459 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1881 22:55:55.910116 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1882 22:55:55.916771 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1883 22:55:55.917339 Total UI for P1: 0, mck2ui 16
1884 22:55:55.923245 best dqsien dly found for B0: ( 0, 14, 4)
1885 22:55:55.923837 Total UI for P1: 0, mck2ui 16
1886 22:55:55.930150 best dqsien dly found for B1: ( 0, 14, 4)
1887 22:55:55.933192 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1888 22:55:55.936735 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1889 22:55:55.937307
1890 22:55:55.939998 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1891 22:55:55.942865 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1892 22:55:55.946898 [Gating] SW calibration Done
1893 22:55:55.947502 ==
1894 22:55:55.949596 Dram Type= 6, Freq= 0, CH_1, rank 1
1895 22:55:55.953396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1896 22:55:55.953865 ==
1897 22:55:55.956559 RX Vref Scan: 0
1898 22:55:55.957022
1899 22:55:55.957386 RX Vref 0 -> 0, step: 1
1900 22:55:55.957730
1901 22:55:55.960317 RX Delay -130 -> 252, step: 16
1902 22:55:55.963301 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1903 22:55:55.969892 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1904 22:55:55.973299 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1905 22:55:55.976755 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1906 22:55:55.980626 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1907 22:55:55.983733 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1908 22:55:55.986613 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1909 22:55:55.993343 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1910 22:55:55.996634 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1911 22:55:56.000240 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1912 22:55:56.003734 iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224
1913 22:55:56.006921 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1914 22:55:56.013657 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1915 22:55:56.017335 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1916 22:55:56.020042 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1917 22:55:56.023641 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1918 22:55:56.024108 ==
1919 22:55:56.027120 Dram Type= 6, Freq= 0, CH_1, rank 1
1920 22:55:56.033712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1921 22:55:56.034283 ==
1922 22:55:56.034655 DQS Delay:
1923 22:55:56.036630 DQS0 = 0, DQS1 = 0
1924 22:55:56.037094 DQM Delay:
1925 22:55:56.037461 DQM0 = 91, DQM1 = 87
1926 22:55:56.039975 DQ Delay:
1927 22:55:56.043460 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =85
1928 22:55:56.046873 DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93
1929 22:55:56.050462 DQ8 =77, DQ9 =77, DQ10 =93, DQ11 =77
1930 22:55:56.053714 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1931 22:55:56.054184
1932 22:55:56.054553
1933 22:55:56.054897 ==
1934 22:55:56.056603 Dram Type= 6, Freq= 0, CH_1, rank 1
1935 22:55:56.060234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1936 22:55:56.060702 ==
1937 22:55:56.061068
1938 22:55:56.061407
1939 22:55:56.063511 TX Vref Scan disable
1940 22:55:56.063973 == TX Byte 0 ==
1941 22:55:56.070291 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1942 22:55:56.073525 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1943 22:55:56.074000 == TX Byte 1 ==
1944 22:55:56.080208 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1945 22:55:56.083209 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1946 22:55:56.083711 ==
1947 22:55:56.086996 Dram Type= 6, Freq= 0, CH_1, rank 1
1948 22:55:56.090313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1949 22:55:56.090911 ==
1950 22:55:56.104196 TX Vref=22, minBit 1, minWin=26, winSum=440
1951 22:55:56.107602 TX Vref=24, minBit 0, minWin=27, winSum=445
1952 22:55:56.110675 TX Vref=26, minBit 2, minWin=27, winSum=449
1953 22:55:56.114557 TX Vref=28, minBit 2, minWin=27, winSum=450
1954 22:55:56.117562 TX Vref=30, minBit 2, minWin=27, winSum=449
1955 22:55:56.121164 TX Vref=32, minBit 2, minWin=27, winSum=448
1956 22:55:56.128041 [TxChooseVref] Worse bit 2, Min win 27, Win sum 450, Final Vref 28
1957 22:55:56.128608
1958 22:55:56.131408 Final TX Range 1 Vref 28
1959 22:55:56.131973
1960 22:55:56.132388 ==
1961 22:55:56.134383 Dram Type= 6, Freq= 0, CH_1, rank 1
1962 22:55:56.137533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1963 22:55:56.138320 ==
1964 22:55:56.138958
1965 22:55:56.139672
1966 22:55:56.140682 TX Vref Scan disable
1967 22:55:56.144404 == TX Byte 0 ==
1968 22:55:56.147196 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1969 22:55:56.150643 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1970 22:55:56.154445 == TX Byte 1 ==
1971 22:55:56.157763 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1972 22:55:56.160975 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1973 22:55:56.164338
1974 22:55:56.164821 [DATLAT]
1975 22:55:56.165190 Freq=800, CH1 RK1
1976 22:55:56.165534
1977 22:55:56.167523 DATLAT Default: 0xa
1978 22:55:56.167989 0, 0xFFFF, sum = 0
1979 22:55:56.170815 1, 0xFFFF, sum = 0
1980 22:55:56.171435 2, 0xFFFF, sum = 0
1981 22:55:56.174106 3, 0xFFFF, sum = 0
1982 22:55:56.174741 4, 0xFFFF, sum = 0
1983 22:55:56.177901 5, 0xFFFF, sum = 0
1984 22:55:56.178461 6, 0xFFFF, sum = 0
1985 22:55:56.180612 7, 0xFFFF, sum = 0
1986 22:55:56.184185 8, 0xFFFF, sum = 0
1987 22:55:56.184749 9, 0x0, sum = 1
1988 22:55:56.185130 10, 0x0, sum = 2
1989 22:55:56.187731 11, 0x0, sum = 3
1990 22:55:56.188315 12, 0x0, sum = 4
1991 22:55:56.190944 best_step = 10
1992 22:55:56.191543
1993 22:55:56.191920 ==
1994 22:55:56.194363 Dram Type= 6, Freq= 0, CH_1, rank 1
1995 22:55:56.197587 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1996 22:55:56.198161 ==
1997 22:55:56.200632 RX Vref Scan: 0
1998 22:55:56.201099
1999 22:55:56.201466 RX Vref 0 -> 0, step: 1
2000 22:55:56.201807
2001 22:55:56.204191 RX Delay -79 -> 252, step: 8
2002 22:55:56.211057 iDelay=209, Bit 0, Center 104 (9 ~ 200) 192
2003 22:55:56.214400 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
2004 22:55:56.217313 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
2005 22:55:56.221406 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
2006 22:55:56.224872 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
2007 22:55:56.227659 iDelay=209, Bit 5, Center 112 (17 ~ 208) 192
2008 22:55:56.234516 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
2009 22:55:56.238070 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
2010 22:55:56.241040 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
2011 22:55:56.244554 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
2012 22:55:56.247595 iDelay=209, Bit 10, Center 88 (-15 ~ 192) 208
2013 22:55:56.254569 iDelay=209, Bit 11, Center 88 (-15 ~ 192) 208
2014 22:55:56.257666 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
2015 22:55:56.260889 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
2016 22:55:56.264487 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
2017 22:55:56.268037 iDelay=209, Bit 15, Center 96 (-7 ~ 200) 208
2018 22:55:56.268603 ==
2019 22:55:56.271169 Dram Type= 6, Freq= 0, CH_1, rank 1
2020 22:55:56.277830 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2021 22:55:56.278407 ==
2022 22:55:56.278781 DQS Delay:
2023 22:55:56.280766 DQS0 = 0, DQS1 = 0
2024 22:55:56.281233 DQM Delay:
2025 22:55:56.281607 DQM0 = 97, DQM1 = 90
2026 22:55:56.284118 DQ Delay:
2027 22:55:56.287671 DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92
2028 22:55:56.290811 DQ4 =92, DQ5 =112, DQ6 =108, DQ7 =96
2029 22:55:56.294301 DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =88
2030 22:55:56.297256 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =96
2031 22:55:56.297778
2032 22:55:56.298148
2033 22:55:56.304406 [DQSOSCAuto] RK1, (LSB)MR18= 0x450f, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 392 ps
2034 22:55:56.307462 CH1 RK1: MR19=606, MR18=450F
2035 22:55:56.314295 CH1_RK1: MR19=0x606, MR18=0x450F, DQSOSC=392, MR23=63, INC=96, DEC=64
2036 22:55:56.317932 [RxdqsGatingPostProcess] freq 800
2037 22:55:56.321247 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2038 22:55:56.324767 Pre-setting of DQS Precalculation
2039 22:55:56.331245 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2040 22:55:56.337867 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2041 22:55:56.344157 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2042 22:55:56.344625
2043 22:55:56.344992
2044 22:55:56.347676 [Calibration Summary] 1600 Mbps
2045 22:55:56.348139 CH 0, Rank 0
2046 22:55:56.351551 SW Impedance : PASS
2047 22:55:56.354798 DUTY Scan : NO K
2048 22:55:56.355400 ZQ Calibration : PASS
2049 22:55:56.357482 Jitter Meter : NO K
2050 22:55:56.361042 CBT Training : PASS
2051 22:55:56.361505 Write leveling : PASS
2052 22:55:56.364843 RX DQS gating : PASS
2053 22:55:56.368027 RX DQ/DQS(RDDQC) : PASS
2054 22:55:56.368584 TX DQ/DQS : PASS
2055 22:55:56.371206 RX DATLAT : PASS
2056 22:55:56.371707 RX DQ/DQS(Engine): PASS
2057 22:55:56.374810 TX OE : NO K
2058 22:55:56.375436 All Pass.
2059 22:55:56.375818
2060 22:55:56.378380 CH 0, Rank 1
2061 22:55:56.378937 SW Impedance : PASS
2062 22:55:56.381250 DUTY Scan : NO K
2063 22:55:56.384745 ZQ Calibration : PASS
2064 22:55:56.385336 Jitter Meter : NO K
2065 22:55:56.387992 CBT Training : PASS
2066 22:55:56.391206 Write leveling : PASS
2067 22:55:56.391689 RX DQS gating : PASS
2068 22:55:56.394526 RX DQ/DQS(RDDQC) : PASS
2069 22:55:56.398262 TX DQ/DQS : PASS
2070 22:55:56.398846 RX DATLAT : PASS
2071 22:55:56.401586 RX DQ/DQS(Engine): PASS
2072 22:55:56.404563 TX OE : NO K
2073 22:55:56.405033 All Pass.
2074 22:55:56.405402
2075 22:55:56.405737 CH 1, Rank 0
2076 22:55:56.407710 SW Impedance : PASS
2077 22:55:56.411698 DUTY Scan : NO K
2078 22:55:56.412253 ZQ Calibration : PASS
2079 22:55:56.414488 Jitter Meter : NO K
2080 22:55:56.414952 CBT Training : PASS
2081 22:55:56.418089 Write leveling : PASS
2082 22:55:56.421317 RX DQS gating : PASS
2083 22:55:56.421783 RX DQ/DQS(RDDQC) : PASS
2084 22:55:56.425001 TX DQ/DQS : PASS
2085 22:55:56.428279 RX DATLAT : PASS
2086 22:55:56.428832 RX DQ/DQS(Engine): PASS
2087 22:55:56.431834 TX OE : NO K
2088 22:55:56.432396 All Pass.
2089 22:55:56.432766
2090 22:55:56.434812 CH 1, Rank 1
2091 22:55:56.435274 SW Impedance : PASS
2092 22:55:56.437944 DUTY Scan : NO K
2093 22:55:56.441230 ZQ Calibration : PASS
2094 22:55:56.441763 Jitter Meter : NO K
2095 22:55:56.444832 CBT Training : PASS
2096 22:55:56.448894 Write leveling : PASS
2097 22:55:56.449462 RX DQS gating : PASS
2098 22:55:56.451702 RX DQ/DQS(RDDQC) : PASS
2099 22:55:56.452168 TX DQ/DQS : PASS
2100 22:55:56.454614 RX DATLAT : PASS
2101 22:55:56.458007 RX DQ/DQS(Engine): PASS
2102 22:55:56.458472 TX OE : NO K
2103 22:55:56.461805 All Pass.
2104 22:55:56.462362
2105 22:55:56.462727 DramC Write-DBI off
2106 22:55:56.464878 PER_BANK_REFRESH: Hybrid Mode
2107 22:55:56.468524 TX_TRACKING: ON
2108 22:55:56.471806 [GetDramInforAfterCalByMRR] Vendor 6.
2109 22:55:56.475433 [GetDramInforAfterCalByMRR] Revision 606.
2110 22:55:56.478216 [GetDramInforAfterCalByMRR] Revision 2 0.
2111 22:55:56.478770 MR0 0x3b3b
2112 22:55:56.479132 MR8 0x5151
2113 22:55:56.481665 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2114 22:55:56.484806
2115 22:55:56.485356 MR0 0x3b3b
2116 22:55:56.485723 MR8 0x5151
2117 22:55:56.488388 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2118 22:55:56.488941
2119 22:55:56.498349 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2120 22:55:56.502024 [FAST_K] Save calibration result to emmc
2121 22:55:56.504950 [FAST_K] Save calibration result to emmc
2122 22:55:56.508373 dram_init: config_dvfs: 1
2123 22:55:56.511669 dramc_set_vcore_voltage set vcore to 662500
2124 22:55:56.514818 Read voltage for 1200, 2
2125 22:55:56.515379 Vio18 = 0
2126 22:55:56.515783 Vcore = 662500
2127 22:55:56.518440 Vdram = 0
2128 22:55:56.518898 Vddq = 0
2129 22:55:56.519261 Vmddr = 0
2130 22:55:56.525305 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2131 22:55:56.528919 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2132 22:55:56.532202 MEM_TYPE=3, freq_sel=15
2133 22:55:56.535130 sv_algorithm_assistance_LP4_1600
2134 22:55:56.538613 ============ PULL DRAM RESETB DOWN ============
2135 22:55:56.541747 ========== PULL DRAM RESETB DOWN end =========
2136 22:55:56.548105 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2137 22:55:56.551534 ===================================
2138 22:55:56.552021 LPDDR4 DRAM CONFIGURATION
2139 22:55:56.555383 ===================================
2140 22:55:56.558818 EX_ROW_EN[0] = 0x0
2141 22:55:56.561604 EX_ROW_EN[1] = 0x0
2142 22:55:56.562163 LP4Y_EN = 0x0
2143 22:55:56.565185 WORK_FSP = 0x0
2144 22:55:56.565753 WL = 0x4
2145 22:55:56.568694 RL = 0x4
2146 22:55:56.569251 BL = 0x2
2147 22:55:56.572036 RPST = 0x0
2148 22:55:56.572582 RD_PRE = 0x0
2149 22:55:56.575182 WR_PRE = 0x1
2150 22:55:56.575683 WR_PST = 0x0
2151 22:55:56.578856 DBI_WR = 0x0
2152 22:55:56.579451 DBI_RD = 0x0
2153 22:55:56.581973 OTF = 0x1
2154 22:55:56.585162 ===================================
2155 22:55:56.588978 ===================================
2156 22:55:56.589542 ANA top config
2157 22:55:56.592052 ===================================
2158 22:55:56.595477 DLL_ASYNC_EN = 0
2159 22:55:56.598620 ALL_SLAVE_EN = 0
2160 22:55:56.599176 NEW_RANK_MODE = 1
2161 22:55:56.602012 DLL_IDLE_MODE = 1
2162 22:55:56.605062 LP45_APHY_COMB_EN = 1
2163 22:55:56.608848 TX_ODT_DIS = 1
2164 22:55:56.612240 NEW_8X_MODE = 1
2165 22:55:56.615398 ===================================
2166 22:55:56.618659 ===================================
2167 22:55:56.619217 data_rate = 2400
2168 22:55:56.621952 CKR = 1
2169 22:55:56.625005 DQ_P2S_RATIO = 8
2170 22:55:56.628466 ===================================
2171 22:55:56.632186 CA_P2S_RATIO = 8
2172 22:55:56.635580 DQ_CA_OPEN = 0
2173 22:55:56.639148 DQ_SEMI_OPEN = 0
2174 22:55:56.639764 CA_SEMI_OPEN = 0
2175 22:55:56.641614 CA_FULL_RATE = 0
2176 22:55:56.645048 DQ_CKDIV4_EN = 0
2177 22:55:56.648316 CA_CKDIV4_EN = 0
2178 22:55:56.651667 CA_PREDIV_EN = 0
2179 22:55:56.652152 PH8_DLY = 17
2180 22:55:56.655186 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2181 22:55:56.658485 DQ_AAMCK_DIV = 4
2182 22:55:56.661534 CA_AAMCK_DIV = 4
2183 22:55:56.665243 CA_ADMCK_DIV = 4
2184 22:55:56.668752 DQ_TRACK_CA_EN = 0
2185 22:55:56.671963 CA_PICK = 1200
2186 22:55:56.672575 CA_MCKIO = 1200
2187 22:55:56.675496 MCKIO_SEMI = 0
2188 22:55:56.679058 PLL_FREQ = 2366
2189 22:55:56.682141 DQ_UI_PI_RATIO = 32
2190 22:55:56.685527 CA_UI_PI_RATIO = 0
2191 22:55:56.689168 ===================================
2192 22:55:56.691851 ===================================
2193 22:55:56.695572 memory_type:LPDDR4
2194 22:55:56.696132 GP_NUM : 10
2195 22:55:56.699087 SRAM_EN : 1
2196 22:55:56.699691 MD32_EN : 0
2197 22:55:56.701943 ===================================
2198 22:55:56.705818 [ANA_INIT] >>>>>>>>>>>>>>
2199 22:55:56.709121 <<<<<< [CONFIGURE PHASE]: ANA_TX
2200 22:55:56.712225 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2201 22:55:56.715608 ===================================
2202 22:55:56.718863 data_rate = 2400,PCW = 0X5b00
2203 22:55:56.722169 ===================================
2204 22:55:56.725063 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2205 22:55:56.729183 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2206 22:55:56.735356 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2207 22:55:56.739448 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2208 22:55:56.742173 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2209 22:55:56.745964 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2210 22:55:56.748521 [ANA_INIT] flow start
2211 22:55:56.751848 [ANA_INIT] PLL >>>>>>>>
2212 22:55:56.752466 [ANA_INIT] PLL <<<<<<<<
2213 22:55:56.755669 [ANA_INIT] MIDPI >>>>>>>>
2214 22:55:56.758729 [ANA_INIT] MIDPI <<<<<<<<
2215 22:55:56.762329 [ANA_INIT] DLL >>>>>>>>
2216 22:55:56.762834 [ANA_INIT] DLL <<<<<<<<
2217 22:55:56.765293 [ANA_INIT] flow end
2218 22:55:56.768720 ============ LP4 DIFF to SE enter ============
2219 22:55:56.771900 ============ LP4 DIFF to SE exit ============
2220 22:55:56.776075 [ANA_INIT] <<<<<<<<<<<<<
2221 22:55:56.779111 [Flow] Enable top DCM control >>>>>
2222 22:55:56.782546 [Flow] Enable top DCM control <<<<<
2223 22:55:56.785521 Enable DLL master slave shuffle
2224 22:55:56.789274 ==============================================================
2225 22:55:56.792280 Gating Mode config
2226 22:55:56.799356 ==============================================================
2227 22:55:56.799919 Config description:
2228 22:55:56.808825 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2229 22:55:56.815944 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2230 22:55:56.822309 SELPH_MODE 0: By rank 1: By Phase
2231 22:55:56.825617 ==============================================================
2232 22:55:56.828972 GAT_TRACK_EN = 1
2233 22:55:56.832014 RX_GATING_MODE = 2
2234 22:55:56.835226 RX_GATING_TRACK_MODE = 2
2235 22:55:56.839130 SELPH_MODE = 1
2236 22:55:56.842345 PICG_EARLY_EN = 1
2237 22:55:56.845543 VALID_LAT_VALUE = 1
2238 22:55:56.848737 ==============================================================
2239 22:55:56.852411 Enter into Gating configuration >>>>
2240 22:55:56.855440 Exit from Gating configuration <<<<
2241 22:55:56.858486 Enter into DVFS_PRE_config >>>>>
2242 22:55:56.872787 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2243 22:55:56.873338 Exit from DVFS_PRE_config <<<<<
2244 22:55:56.875567 Enter into PICG configuration >>>>
2245 22:55:56.878757 Exit from PICG configuration <<<<
2246 22:55:56.882117 [RX_INPUT] configuration >>>>>
2247 22:55:56.885802 [RX_INPUT] configuration <<<<<
2248 22:55:56.892479 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2249 22:55:56.895629 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2250 22:55:56.902488 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2251 22:55:56.909244 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2252 22:55:56.916158 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2253 22:55:56.923004 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2254 22:55:56.925394 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2255 22:55:56.929415 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2256 22:55:56.932230 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2257 22:55:56.939264 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2258 22:55:56.942628 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2259 22:55:56.945318 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2260 22:55:56.948670 ===================================
2261 22:55:56.952455 LPDDR4 DRAM CONFIGURATION
2262 22:55:56.955402 ===================================
2263 22:55:56.955870 EX_ROW_EN[0] = 0x0
2264 22:55:56.958763 EX_ROW_EN[1] = 0x0
2265 22:55:56.959227 LP4Y_EN = 0x0
2266 22:55:56.962370 WORK_FSP = 0x0
2267 22:55:56.962837 WL = 0x4
2268 22:55:56.965396 RL = 0x4
2269 22:55:56.969073 BL = 0x2
2270 22:55:56.969538 RPST = 0x0
2271 22:55:56.972561 RD_PRE = 0x0
2272 22:55:56.973026 WR_PRE = 0x1
2273 22:55:56.975720 WR_PST = 0x0
2274 22:55:56.976324 DBI_WR = 0x0
2275 22:55:56.979094 DBI_RD = 0x0
2276 22:55:56.979591 OTF = 0x1
2277 22:55:56.982198 ===================================
2278 22:55:56.986083 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2279 22:55:56.992761 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2280 22:55:56.995525 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2281 22:55:56.999713 ===================================
2282 22:55:57.002434 LPDDR4 DRAM CONFIGURATION
2283 22:55:57.005566 ===================================
2284 22:55:57.006035 EX_ROW_EN[0] = 0x10
2285 22:55:57.009571 EX_ROW_EN[1] = 0x0
2286 22:55:57.010204 LP4Y_EN = 0x0
2287 22:55:57.012190 WORK_FSP = 0x0
2288 22:55:57.012660 WL = 0x4
2289 22:55:57.015599 RL = 0x4
2290 22:55:57.016076 BL = 0x2
2291 22:55:57.019187 RPST = 0x0
2292 22:55:57.019788 RD_PRE = 0x0
2293 22:55:57.023089 WR_PRE = 0x1
2294 22:55:57.023706 WR_PST = 0x0
2295 22:55:57.025656 DBI_WR = 0x0
2296 22:55:57.026123 DBI_RD = 0x0
2297 22:55:57.029563 OTF = 0x1
2298 22:55:57.032665 ===================================
2299 22:55:57.039361 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2300 22:55:57.039926 ==
2301 22:55:57.042493 Dram Type= 6, Freq= 0, CH_0, rank 0
2302 22:55:57.045717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2303 22:55:57.046192 ==
2304 22:55:57.049601 [Duty_Offset_Calibration]
2305 22:55:57.050164 B0:2 B1:1 CA:1
2306 22:55:57.050541
2307 22:55:57.052790 [DutyScan_Calibration_Flow] k_type=0
2308 22:55:57.062982
2309 22:55:57.063628 ==CLK 0==
2310 22:55:57.066481 Final CLK duty delay cell = 0
2311 22:55:57.069624 [0] MAX Duty = 5156%(X100), DQS PI = 24
2312 22:55:57.073087 [0] MIN Duty = 4875%(X100), DQS PI = 0
2313 22:55:57.073660 [0] AVG Duty = 5015%(X100)
2314 22:55:57.076099
2315 22:55:57.076516 CH0 CLK Duty spec in!! Max-Min= 281%
2316 22:55:57.082571 [DutyScan_Calibration_Flow] ====Done====
2317 22:55:57.082866
2318 22:55:57.086284 [DutyScan_Calibration_Flow] k_type=1
2319 22:55:57.100866
2320 22:55:57.101247 ==DQS 0 ==
2321 22:55:57.104032 Final DQS duty delay cell = -4
2322 22:55:57.107496 [-4] MAX Duty = 5124%(X100), DQS PI = 22
2323 22:55:57.110913 [-4] MIN Duty = 4751%(X100), DQS PI = 0
2324 22:55:57.114232 [-4] AVG Duty = 4937%(X100)
2325 22:55:57.114712
2326 22:55:57.115022 ==DQS 1 ==
2327 22:55:57.117633 Final DQS duty delay cell = -4
2328 22:55:57.121181 [-4] MAX Duty = 4969%(X100), DQS PI = 0
2329 22:55:57.124139 [-4] MIN Duty = 4844%(X100), DQS PI = 34
2330 22:55:57.127215 [-4] AVG Duty = 4906%(X100)
2331 22:55:57.127713
2332 22:55:57.131545 CH0 DQS 0 Duty spec in!! Max-Min= 373%
2333 22:55:57.132096
2334 22:55:57.134519 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2335 22:55:57.137444 [DutyScan_Calibration_Flow] ====Done====
2336 22:55:57.137903
2337 22:55:57.141022 [DutyScan_Calibration_Flow] k_type=3
2338 22:55:57.157338
2339 22:55:57.157885 ==DQM 0 ==
2340 22:55:57.160043 Final DQM duty delay cell = 0
2341 22:55:57.163832 [0] MAX Duty = 5156%(X100), DQS PI = 28
2342 22:55:57.167184 [0] MIN Duty = 4906%(X100), DQS PI = 52
2343 22:55:57.167806 [0] AVG Duty = 5031%(X100)
2344 22:55:57.170354
2345 22:55:57.170897 ==DQM 1 ==
2346 22:55:57.174179 Final DQM duty delay cell = -4
2347 22:55:57.176995 [-4] MAX Duty = 4969%(X100), DQS PI = 58
2348 22:55:57.180438 [-4] MIN Duty = 4875%(X100), DQS PI = 16
2349 22:55:57.183922 [-4] AVG Duty = 4922%(X100)
2350 22:55:57.184375
2351 22:55:57.187227 CH0 DQM 0 Duty spec in!! Max-Min= 250%
2352 22:55:57.187853
2353 22:55:57.190572 CH0 DQM 1 Duty spec in!! Max-Min= 94%
2354 22:55:57.194034 [DutyScan_Calibration_Flow] ====Done====
2355 22:55:57.194592
2356 22:55:57.196922 [DutyScan_Calibration_Flow] k_type=2
2357 22:55:57.213795
2358 22:55:57.214340 ==DQ 0 ==
2359 22:55:57.217397 Final DQ duty delay cell = 0
2360 22:55:57.220973 [0] MAX Duty = 5031%(X100), DQS PI = 24
2361 22:55:57.223941 [0] MIN Duty = 4906%(X100), DQS PI = 0
2362 22:55:57.224504 [0] AVG Duty = 4968%(X100)
2363 22:55:57.224868
2364 22:55:57.227093 ==DQ 1 ==
2365 22:55:57.231071 Final DQ duty delay cell = 0
2366 22:55:57.234027 [0] MAX Duty = 5093%(X100), DQS PI = 10
2367 22:55:57.237461 [0] MIN Duty = 4938%(X100), DQS PI = 36
2368 22:55:57.238021 [0] AVG Duty = 5015%(X100)
2369 22:55:57.238391
2370 22:55:57.241022 CH0 DQ 0 Duty spec in!! Max-Min= 125%
2371 22:55:57.241573
2372 22:55:57.244135 CH0 DQ 1 Duty spec in!! Max-Min= 155%
2373 22:55:57.250849 [DutyScan_Calibration_Flow] ====Done====
2374 22:55:57.251431 ==
2375 22:55:57.254510 Dram Type= 6, Freq= 0, CH_1, rank 0
2376 22:55:57.257438 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2377 22:55:57.257991 ==
2378 22:55:57.261006 [Duty_Offset_Calibration]
2379 22:55:57.261465 B0:1 B1:0 CA:1
2380 22:55:57.261829
2381 22:55:57.263617 [DutyScan_Calibration_Flow] k_type=0
2382 22:55:57.273270
2383 22:55:57.273854 ==CLK 0==
2384 22:55:57.276217 Final CLK duty delay cell = -4
2385 22:55:57.279443 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2386 22:55:57.282993 [-4] MIN Duty = 4907%(X100), DQS PI = 50
2387 22:55:57.286357 [-4] AVG Duty = 4969%(X100)
2388 22:55:57.286964
2389 22:55:57.289721 CH1 CLK Duty spec in!! Max-Min= 124%
2390 22:55:57.293167 [DutyScan_Calibration_Flow] ====Done====
2391 22:55:57.293729
2392 22:55:57.296129 [DutyScan_Calibration_Flow] k_type=1
2393 22:55:57.312615
2394 22:55:57.313169 ==DQS 0 ==
2395 22:55:57.315815 Final DQS duty delay cell = 0
2396 22:55:57.319266 [0] MAX Duty = 5094%(X100), DQS PI = 26
2397 22:55:57.322865 [0] MIN Duty = 4875%(X100), DQS PI = 0
2398 22:55:57.323460 [0] AVG Duty = 4984%(X100)
2399 22:55:57.323842
2400 22:55:57.326122 ==DQS 1 ==
2401 22:55:57.329817 Final DQS duty delay cell = 0
2402 22:55:57.333449 [0] MAX Duty = 5156%(X100), DQS PI = 18
2403 22:55:57.336668 [0] MIN Duty = 4969%(X100), DQS PI = 8
2404 22:55:57.337222 [0] AVG Duty = 5062%(X100)
2405 22:55:57.337596
2406 22:55:57.343088 CH1 DQS 0 Duty spec in!! Max-Min= 219%
2407 22:55:57.343689
2408 22:55:57.345938 CH1 DQS 1 Duty spec in!! Max-Min= 187%
2409 22:55:57.349798 [DutyScan_Calibration_Flow] ====Done====
2410 22:55:57.350358
2411 22:55:57.352579 [DutyScan_Calibration_Flow] k_type=3
2412 22:55:57.369687
2413 22:55:57.370240 ==DQM 0 ==
2414 22:55:57.372449 Final DQM duty delay cell = 0
2415 22:55:57.375661 [0] MAX Duty = 5156%(X100), DQS PI = 6
2416 22:55:57.379154 [0] MIN Duty = 5031%(X100), DQS PI = 0
2417 22:55:57.379847 [0] AVG Duty = 5093%(X100)
2418 22:55:57.382502
2419 22:55:57.383060 ==DQM 1 ==
2420 22:55:57.385623 Final DQM duty delay cell = 0
2421 22:55:57.389117 [0] MAX Duty = 5031%(X100), DQS PI = 16
2422 22:55:57.393341 [0] MIN Duty = 4907%(X100), DQS PI = 36
2423 22:55:57.393967 [0] AVG Duty = 4969%(X100)
2424 22:55:57.396579
2425 22:55:57.399590 CH1 DQM 0 Duty spec in!! Max-Min= 125%
2426 22:55:57.400165
2427 22:55:57.402924 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2428 22:55:57.406355 [DutyScan_Calibration_Flow] ====Done====
2429 22:55:57.406918
2430 22:55:57.409651 [DutyScan_Calibration_Flow] k_type=2
2431 22:55:57.424535
2432 22:55:57.425055 ==DQ 0 ==
2433 22:55:57.428126 Final DQ duty delay cell = -4
2434 22:55:57.431203 [-4] MAX Duty = 5062%(X100), DQS PI = 8
2435 22:55:57.434770 [-4] MIN Duty = 4938%(X100), DQS PI = 0
2436 22:55:57.435351 [-4] AVG Duty = 5000%(X100)
2437 22:55:57.438374
2438 22:55:57.438786 ==DQ 1 ==
2439 22:55:57.442191 Final DQ duty delay cell = 0
2440 22:55:57.444963 [0] MAX Duty = 5125%(X100), DQS PI = 20
2441 22:55:57.448232 [0] MIN Duty = 4969%(X100), DQS PI = 14
2442 22:55:57.448653 [0] AVG Duty = 5047%(X100)
2443 22:55:57.448987
2444 22:55:57.451486 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2445 22:55:57.454936
2446 22:55:57.458584 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2447 22:55:57.461685 [DutyScan_Calibration_Flow] ====Done====
2448 22:55:57.465262 nWR fixed to 30
2449 22:55:57.465683 [ModeRegInit_LP4] CH0 RK0
2450 22:55:57.468334 [ModeRegInit_LP4] CH0 RK1
2451 22:55:57.472017 [ModeRegInit_LP4] CH1 RK0
2452 22:55:57.472434 [ModeRegInit_LP4] CH1 RK1
2453 22:55:57.474909 match AC timing 7
2454 22:55:57.478421 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2455 22:55:57.481828 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2456 22:55:57.488725 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2457 22:55:57.491885 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2458 22:55:57.498542 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2459 22:55:57.498962 ==
2460 22:55:57.501520 Dram Type= 6, Freq= 0, CH_0, rank 0
2461 22:55:57.504675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2462 22:55:57.505189 ==
2463 22:55:57.511774 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2464 22:55:57.514754 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2465 22:55:57.525073 [CA 0] Center 39 (8~70) winsize 63
2466 22:55:57.528689 [CA 1] Center 39 (8~70) winsize 63
2467 22:55:57.532047 [CA 2] Center 35 (5~66) winsize 62
2468 22:55:57.535612 [CA 3] Center 34 (4~65) winsize 62
2469 22:55:57.538296 [CA 4] Center 33 (3~64) winsize 62
2470 22:55:57.541743 [CA 5] Center 32 (3~62) winsize 60
2471 22:55:57.542159
2472 22:55:57.545164 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2473 22:55:57.545585
2474 22:55:57.548716 [CATrainingPosCal] consider 1 rank data
2475 22:55:57.551846 u2DelayCellTimex100 = 270/100 ps
2476 22:55:57.555316 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2477 22:55:57.558930 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2478 22:55:57.565382 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2479 22:55:57.568385 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2480 22:55:57.572182 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2481 22:55:57.575383 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2482 22:55:57.575909
2483 22:55:57.578750 CA PerBit enable=1, Macro0, CA PI delay=32
2484 22:55:57.579167
2485 22:55:57.582646 [CBTSetCACLKResult] CA Dly = 32
2486 22:55:57.583175 CS Dly: 6 (0~37)
2487 22:55:57.583580 ==
2488 22:55:57.585457 Dram Type= 6, Freq= 0, CH_0, rank 1
2489 22:55:57.591917 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2490 22:55:57.592377 ==
2491 22:55:57.595437 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2492 22:55:57.601957 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2493 22:55:57.610640 [CA 0] Center 38 (8~69) winsize 62
2494 22:55:57.614025 [CA 1] Center 38 (8~69) winsize 62
2495 22:55:57.617696 [CA 2] Center 35 (4~66) winsize 63
2496 22:55:57.621024 [CA 3] Center 34 (4~65) winsize 62
2497 22:55:57.624165 [CA 4] Center 33 (3~64) winsize 62
2498 22:55:57.627520 [CA 5] Center 32 (3~62) winsize 60
2499 22:55:57.627947
2500 22:55:57.630815 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2501 22:55:57.631243
2502 22:55:57.634685 [CATrainingPosCal] consider 2 rank data
2503 22:55:57.637639 u2DelayCellTimex100 = 270/100 ps
2504 22:55:57.641441 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2505 22:55:57.644092 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2506 22:55:57.651128 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2507 22:55:57.654024 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2508 22:55:57.657523 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2509 22:55:57.660733 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2510 22:55:57.661157
2511 22:55:57.664514 CA PerBit enable=1, Macro0, CA PI delay=32
2512 22:55:57.664951
2513 22:55:57.667434 [CBTSetCACLKResult] CA Dly = 32
2514 22:55:57.667858 CS Dly: 6 (0~38)
2515 22:55:57.668194
2516 22:55:57.670992 ----->DramcWriteLeveling(PI) begin...
2517 22:55:57.674230 ==
2518 22:55:57.674651 Dram Type= 6, Freq= 0, CH_0, rank 0
2519 22:55:57.680811 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2520 22:55:57.681235 ==
2521 22:55:57.684666 Write leveling (Byte 0): 33 => 33
2522 22:55:57.687576 Write leveling (Byte 1): 29 => 29
2523 22:55:57.691096 DramcWriteLeveling(PI) end<-----
2524 22:55:57.691562
2525 22:55:57.691898 ==
2526 22:55:57.694051 Dram Type= 6, Freq= 0, CH_0, rank 0
2527 22:55:57.697415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2528 22:55:57.697840 ==
2529 22:55:57.700896 [Gating] SW mode calibration
2530 22:55:57.707579 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2531 22:55:57.710857 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2532 22:55:57.717359 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2533 22:55:57.720776 0 15 4 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
2534 22:55:57.724182 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2535 22:55:57.730925 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2536 22:55:57.734252 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2537 22:55:57.737366 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2538 22:55:57.744569 0 15 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
2539 22:55:57.747667 0 15 28 | B1->B0 | 3434 2424 | 1 0 | (1 0) (1 0)
2540 22:55:57.750752 1 0 0 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
2541 22:55:57.757885 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2542 22:55:57.760739 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2543 22:55:57.764530 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2544 22:55:57.770802 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2545 22:55:57.774432 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2546 22:55:57.778033 1 0 24 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
2547 22:55:57.781403 1 0 28 | B1->B0 | 2e2e 4646 | 0 0 | (0 0) (0 0)
2548 22:55:57.787487 1 1 0 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
2549 22:55:57.791096 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2550 22:55:57.794909 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2551 22:55:57.801194 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2552 22:55:57.804253 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2553 22:55:57.808132 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2554 22:55:57.814240 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2555 22:55:57.817479 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2556 22:55:57.820763 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2557 22:55:57.827687 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 22:55:57.831320 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 22:55:57.834649 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 22:55:57.840814 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 22:55:57.844555 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 22:55:57.847906 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 22:55:57.854561 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 22:55:57.857708 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 22:55:57.861100 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 22:55:57.864682 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 22:55:57.871078 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 22:55:57.874887 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 22:55:57.877775 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2570 22:55:57.884894 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2571 22:55:57.887945 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2572 22:55:57.891427 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2573 22:55:57.894635 Total UI for P1: 0, mck2ui 16
2574 22:55:57.898247 best dqsien dly found for B0: ( 1, 3, 26)
2575 22:55:57.904802 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2576 22:55:57.905225 Total UI for P1: 0, mck2ui 16
2577 22:55:57.911220 best dqsien dly found for B1: ( 1, 4, 0)
2578 22:55:57.914486 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2579 22:55:57.918032 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2580 22:55:57.918451
2581 22:55:57.921022 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2582 22:55:57.924682 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2583 22:55:57.928068 [Gating] SW calibration Done
2584 22:55:57.928598 ==
2585 22:55:57.931172 Dram Type= 6, Freq= 0, CH_0, rank 0
2586 22:55:57.934569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2587 22:55:57.935010 ==
2588 22:55:57.937971 RX Vref Scan: 0
2589 22:55:57.938388
2590 22:55:57.938759 RX Vref 0 -> 0, step: 1
2591 22:55:57.939246
2592 22:55:57.941234 RX Delay -40 -> 252, step: 8
2593 22:55:57.944472 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2594 22:55:57.951404 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2595 22:55:57.954360 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2596 22:55:57.957646 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2597 22:55:57.961469 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2598 22:55:57.964498 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2599 22:55:57.967991 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2600 22:55:57.974957 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2601 22:55:57.977888 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2602 22:55:57.981174 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
2603 22:55:57.984583 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2604 22:55:57.987884 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2605 22:55:57.994669 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2606 22:55:57.998166 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2607 22:55:58.001166 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2608 22:55:58.005027 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2609 22:55:58.005475 ==
2610 22:55:58.007720 Dram Type= 6, Freq= 0, CH_0, rank 0
2611 22:55:58.014954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2612 22:55:58.015420 ==
2613 22:55:58.015766 DQS Delay:
2614 22:55:58.017887 DQS0 = 0, DQS1 = 0
2615 22:55:58.018349 DQM Delay:
2616 22:55:58.018693 DQM0 = 121, DQM1 = 113
2617 22:55:58.021473 DQ Delay:
2618 22:55:58.024998 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2619 22:55:58.027642 DQ4 =123, DQ5 =115, DQ6 =127, DQ7 =127
2620 22:55:58.031609 DQ8 =99, DQ9 =107, DQ10 =111, DQ11 =107
2621 22:55:58.034605 DQ12 =115, DQ13 =123, DQ14 =123, DQ15 =119
2622 22:55:58.035033
2623 22:55:58.035456
2624 22:55:58.035789 ==
2625 22:55:58.037755 Dram Type= 6, Freq= 0, CH_0, rank 0
2626 22:55:58.041212 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2627 22:55:58.044744 ==
2628 22:55:58.045169
2629 22:55:58.045524
2630 22:55:58.045860 TX Vref Scan disable
2631 22:55:58.047894 == TX Byte 0 ==
2632 22:55:58.051234 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2633 22:55:58.054630 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2634 22:55:58.057819 == TX Byte 1 ==
2635 22:55:58.061269 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2636 22:55:58.064913 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2637 22:55:58.065341 ==
2638 22:55:58.067891 Dram Type= 6, Freq= 0, CH_0, rank 0
2639 22:55:58.074738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2640 22:55:58.075251 ==
2641 22:55:58.085684 TX Vref=22, minBit 0, minWin=25, winSum=412
2642 22:55:58.088835 TX Vref=24, minBit 0, minWin=25, winSum=417
2643 22:55:58.092147 TX Vref=26, minBit 3, minWin=25, winSum=423
2644 22:55:58.095489 TX Vref=28, minBit 0, minWin=26, winSum=424
2645 22:55:58.099107 TX Vref=30, minBit 0, minWin=26, winSum=425
2646 22:55:58.102300 TX Vref=32, minBit 0, minWin=26, winSum=424
2647 22:55:58.109427 [TxChooseVref] Worse bit 0, Min win 26, Win sum 425, Final Vref 30
2648 22:55:58.109959
2649 22:55:58.112142 Final TX Range 1 Vref 30
2650 22:55:58.112570
2651 22:55:58.112935 ==
2652 22:55:58.115304 Dram Type= 6, Freq= 0, CH_0, rank 0
2653 22:55:58.118874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2654 22:55:58.119302 ==
2655 22:55:58.119683
2656 22:55:58.122306
2657 22:55:58.122730 TX Vref Scan disable
2658 22:55:58.125872 == TX Byte 0 ==
2659 22:55:58.128567 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2660 22:55:58.132341 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2661 22:55:58.135286 == TX Byte 1 ==
2662 22:55:58.139000 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2663 22:55:58.141872 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2664 22:55:58.145183
2665 22:55:58.145606 [DATLAT]
2666 22:55:58.145942 Freq=1200, CH0 RK0
2667 22:55:58.146259
2668 22:55:58.148563 DATLAT Default: 0xd
2669 22:55:58.148990 0, 0xFFFF, sum = 0
2670 22:55:58.152272 1, 0xFFFF, sum = 0
2671 22:55:58.152704 2, 0xFFFF, sum = 0
2672 22:55:58.155547 3, 0xFFFF, sum = 0
2673 22:55:58.155982 4, 0xFFFF, sum = 0
2674 22:55:58.158564 5, 0xFFFF, sum = 0
2675 22:55:58.159075 6, 0xFFFF, sum = 0
2676 22:55:58.162197 7, 0xFFFF, sum = 0
2677 22:55:58.165885 8, 0xFFFF, sum = 0
2678 22:55:58.166458 9, 0xFFFF, sum = 0
2679 22:55:58.169062 10, 0xFFFF, sum = 0
2680 22:55:58.169495 11, 0xFFFF, sum = 0
2681 22:55:58.172321 12, 0x0, sum = 1
2682 22:55:58.172772 13, 0x0, sum = 2
2683 22:55:58.173111 14, 0x0, sum = 3
2684 22:55:58.175874 15, 0x0, sum = 4
2685 22:55:58.176383 best_step = 13
2686 22:55:58.176720
2687 22:55:58.178782 ==
2688 22:55:58.179201 Dram Type= 6, Freq= 0, CH_0, rank 0
2689 22:55:58.185917 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2690 22:55:58.186360 ==
2691 22:55:58.186697 RX Vref Scan: 1
2692 22:55:58.187006
2693 22:55:58.188779 Set Vref Range= 32 -> 127
2694 22:55:58.189198
2695 22:55:58.192198 RX Vref 32 -> 127, step: 1
2696 22:55:58.192619
2697 22:55:58.195448 RX Delay -13 -> 252, step: 4
2698 22:55:58.195868
2699 22:55:58.198522 Set Vref, RX VrefLevel [Byte0]: 32
2700 22:55:58.201557 [Byte1]: 32
2701 22:55:58.201642
2702 22:55:58.205046 Set Vref, RX VrefLevel [Byte0]: 33
2703 22:55:58.208078 [Byte1]: 33
2704 22:55:58.208159
2705 22:55:58.211895 Set Vref, RX VrefLevel [Byte0]: 34
2706 22:55:58.214644 [Byte1]: 34
2707 22:55:58.219135
2708 22:55:58.219220 Set Vref, RX VrefLevel [Byte0]: 35
2709 22:55:58.222573 [Byte1]: 35
2710 22:55:58.227160
2711 22:55:58.227236 Set Vref, RX VrefLevel [Byte0]: 36
2712 22:55:58.230361 [Byte1]: 36
2713 22:55:58.235094
2714 22:55:58.235176 Set Vref, RX VrefLevel [Byte0]: 37
2715 22:55:58.237974 [Byte1]: 37
2716 22:55:58.242641
2717 22:55:58.242724 Set Vref, RX VrefLevel [Byte0]: 38
2718 22:55:58.246003 [Byte1]: 38
2719 22:55:58.250975
2720 22:55:58.251062 Set Vref, RX VrefLevel [Byte0]: 39
2721 22:55:58.253772 [Byte1]: 39
2722 22:55:58.258314
2723 22:55:58.258400 Set Vref, RX VrefLevel [Byte0]: 40
2724 22:55:58.262212 [Byte1]: 40
2725 22:55:58.266195
2726 22:55:58.266277 Set Vref, RX VrefLevel [Byte0]: 41
2727 22:55:58.269575 [Byte1]: 41
2728 22:55:58.274369
2729 22:55:58.274451 Set Vref, RX VrefLevel [Byte0]: 42
2730 22:55:58.277804 [Byte1]: 42
2731 22:55:58.282300
2732 22:55:58.282385 Set Vref, RX VrefLevel [Byte0]: 43
2733 22:55:58.285808 [Byte1]: 43
2734 22:55:58.290155
2735 22:55:58.290240 Set Vref, RX VrefLevel [Byte0]: 44
2736 22:55:58.293651 [Byte1]: 44
2737 22:55:58.298323
2738 22:55:58.298398 Set Vref, RX VrefLevel [Byte0]: 45
2739 22:55:58.301580 [Byte1]: 45
2740 22:55:58.305998
2741 22:55:58.306070 Set Vref, RX VrefLevel [Byte0]: 46
2742 22:55:58.309541 [Byte1]: 46
2743 22:55:58.313564
2744 22:55:58.313649 Set Vref, RX VrefLevel [Byte0]: 47
2745 22:55:58.317305 [Byte1]: 47
2746 22:55:58.321626
2747 22:55:58.321710 Set Vref, RX VrefLevel [Byte0]: 48
2748 22:55:58.325140 [Byte1]: 48
2749 22:55:58.329897
2750 22:55:58.329974 Set Vref, RX VrefLevel [Byte0]: 49
2751 22:55:58.332801 [Byte1]: 49
2752 22:55:58.337411
2753 22:55:58.337484 Set Vref, RX VrefLevel [Byte0]: 50
2754 22:55:58.340603 [Byte1]: 50
2755 22:55:58.345407
2756 22:55:58.345478 Set Vref, RX VrefLevel [Byte0]: 51
2757 22:55:58.348454 [Byte1]: 51
2758 22:55:58.353075
2759 22:55:58.353154 Set Vref, RX VrefLevel [Byte0]: 52
2760 22:55:58.356431 [Byte1]: 52
2761 22:55:58.361350
2762 22:55:58.361428 Set Vref, RX VrefLevel [Byte0]: 53
2763 22:55:58.364505 [Byte1]: 53
2764 22:55:58.368843
2765 22:55:58.368919 Set Vref, RX VrefLevel [Byte0]: 54
2766 22:55:58.372324 [Byte1]: 54
2767 22:55:58.377066
2768 22:55:58.377145 Set Vref, RX VrefLevel [Byte0]: 55
2769 22:55:58.380444 [Byte1]: 55
2770 22:55:58.384829
2771 22:55:58.384903 Set Vref, RX VrefLevel [Byte0]: 56
2772 22:55:58.388214 [Byte1]: 56
2773 22:55:58.392514
2774 22:55:58.392586 Set Vref, RX VrefLevel [Byte0]: 57
2775 22:55:58.396179 [Byte1]: 57
2776 22:55:58.401003
2777 22:55:58.401077 Set Vref, RX VrefLevel [Byte0]: 58
2778 22:55:58.403845 [Byte1]: 58
2779 22:55:58.408376
2780 22:55:58.408445 Set Vref, RX VrefLevel [Byte0]: 59
2781 22:55:58.412059 [Byte1]: 59
2782 22:55:58.416510
2783 22:55:58.416588 Set Vref, RX VrefLevel [Byte0]: 60
2784 22:55:58.419597 [Byte1]: 60
2785 22:55:58.424479
2786 22:55:58.424548 Set Vref, RX VrefLevel [Byte0]: 61
2787 22:55:58.427409 [Byte1]: 61
2788 22:55:58.432315
2789 22:55:58.432385 Set Vref, RX VrefLevel [Byte0]: 62
2790 22:55:58.435382 [Byte1]: 62
2791 22:55:58.440041
2792 22:55:58.440115 Set Vref, RX VrefLevel [Byte0]: 63
2793 22:55:58.443278 [Byte1]: 63
2794 22:55:58.447947
2795 22:55:58.448016 Set Vref, RX VrefLevel [Byte0]: 64
2796 22:55:58.451032 [Byte1]: 64
2797 22:55:58.455722
2798 22:55:58.455797 Set Vref, RX VrefLevel [Byte0]: 65
2799 22:55:58.459434 [Byte1]: 65
2800 22:55:58.463785
2801 22:55:58.463864 Set Vref, RX VrefLevel [Byte0]: 66
2802 22:55:58.467277 [Byte1]: 66
2803 22:55:58.471409
2804 22:55:58.471516 Set Vref, RX VrefLevel [Byte0]: 67
2805 22:55:58.474694 [Byte1]: 67
2806 22:55:58.479634
2807 22:55:58.479706 Set Vref, RX VrefLevel [Byte0]: 68
2808 22:55:58.482851 [Byte1]: 68
2809 22:55:58.487396
2810 22:55:58.487470 Set Vref, RX VrefLevel [Byte0]: 69
2811 22:55:58.490757 [Byte1]: 69
2812 22:55:58.495432
2813 22:55:58.495501 Final RX Vref Byte 0 = 56 to rank0
2814 22:55:58.498685 Final RX Vref Byte 1 = 48 to rank0
2815 22:55:58.501912 Final RX Vref Byte 0 = 56 to rank1
2816 22:55:58.505278 Final RX Vref Byte 1 = 48 to rank1==
2817 22:55:58.508908 Dram Type= 6, Freq= 0, CH_0, rank 0
2818 22:55:58.515230 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2819 22:55:58.515310 ==
2820 22:55:58.515412 DQS Delay:
2821 22:55:58.515475 DQS0 = 0, DQS1 = 0
2822 22:55:58.518425 DQM Delay:
2823 22:55:58.518498 DQM0 = 120, DQM1 = 111
2824 22:55:58.522118 DQ Delay:
2825 22:55:58.525348 DQ0 =120, DQ1 =122, DQ2 =118, DQ3 =120
2826 22:55:58.528511 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =126
2827 22:55:58.532070 DQ8 =100, DQ9 =98, DQ10 =112, DQ11 =106
2828 22:55:58.535197 DQ12 =116, DQ13 =116, DQ14 =124, DQ15 =120
2829 22:55:58.535292
2830 22:55:58.535410
2831 22:55:58.542268 [DQSOSCAuto] RK0, (LSB)MR18= 0x1811, (MSB)MR19= 0x404, tDQSOscB0 = 403 ps tDQSOscB1 = 400 ps
2832 22:55:58.545360 CH0 RK0: MR19=404, MR18=1811
2833 22:55:58.551858 CH0_RK0: MR19=0x404, MR18=0x1811, DQSOSC=400, MR23=63, INC=40, DEC=27
2834 22:55:58.551937
2835 22:55:58.555444 ----->DramcWriteLeveling(PI) begin...
2836 22:55:58.555515 ==
2837 22:55:58.558961 Dram Type= 6, Freq= 0, CH_0, rank 1
2838 22:55:58.561764 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2839 22:55:58.565322 ==
2840 22:55:58.565424 Write leveling (Byte 0): 33 => 33
2841 22:55:58.569115 Write leveling (Byte 1): 30 => 30
2842 22:55:58.571970 DramcWriteLeveling(PI) end<-----
2843 22:55:58.572039
2844 22:55:58.572099 ==
2845 22:55:58.575509 Dram Type= 6, Freq= 0, CH_0, rank 1
2846 22:55:58.581951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2847 22:55:58.582025 ==
2848 22:55:58.582086 [Gating] SW mode calibration
2849 22:55:58.592350 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2850 22:55:58.595667 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2851 22:55:58.598900 0 15 0 | B1->B0 | 3434 3131 | 0 1 | (0 0) (0 0)
2852 22:55:58.605748 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2853 22:55:58.608946 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2854 22:55:58.612362 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2855 22:55:58.618899 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2856 22:55:58.622017 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2857 22:55:58.625252 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 0)
2858 22:55:58.632223 0 15 28 | B1->B0 | 3030 2e2e | 1 1 | (1 1) (1 0)
2859 22:55:58.635654 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
2860 22:55:58.639203 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2861 22:55:58.645858 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2862 22:55:58.649613 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2863 22:55:58.652305 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2864 22:55:58.659399 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2865 22:55:58.662170 1 0 24 | B1->B0 | 2525 2423 | 0 1 | (0 0) (0 0)
2866 22:55:58.665884 1 0 28 | B1->B0 | 3939 3939 | 0 0 | (0 0) (1 1)
2867 22:55:58.668940 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2868 22:55:58.675838 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2869 22:55:58.678912 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2870 22:55:58.682302 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2871 22:55:58.688893 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2872 22:55:58.692280 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2873 22:55:58.695621 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2874 22:55:58.702643 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2875 22:55:58.705780 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2876 22:55:58.709203 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2877 22:55:58.716424 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2878 22:55:58.719514 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2879 22:55:58.722707 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2880 22:55:58.729784 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2881 22:55:58.732892 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2882 22:55:58.736348 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2883 22:55:58.743235 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 22:55:58.746106 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 22:55:58.749499 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 22:55:58.753029 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 22:55:58.759814 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 22:55:58.763128 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2889 22:55:58.766242 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2890 22:55:58.773234 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2891 22:55:58.776198 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
2892 22:55:58.780012 Total UI for P1: 0, mck2ui 16
2893 22:55:58.782879 best dqsien dly found for B1: ( 1, 3, 26)
2894 22:55:58.786879 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2895 22:55:58.789654 Total UI for P1: 0, mck2ui 16
2896 22:55:58.793045 best dqsien dly found for B0: ( 1, 3, 28)
2897 22:55:58.796653 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2898 22:55:58.799613 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
2899 22:55:58.800080
2900 22:55:58.806777 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2901 22:55:58.810061 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
2902 22:55:58.810525 [Gating] SW calibration Done
2903 22:55:58.812702 ==
2904 22:55:58.816072 Dram Type= 6, Freq= 0, CH_0, rank 1
2905 22:55:58.819360 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2906 22:55:58.819784 ==
2907 22:55:58.820116 RX Vref Scan: 0
2908 22:55:58.820426
2909 22:55:58.822587 RX Vref 0 -> 0, step: 1
2910 22:55:58.823007
2911 22:55:58.826704 RX Delay -40 -> 252, step: 8
2912 22:55:58.829409 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2913 22:55:58.833553 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2914 22:55:58.836849 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2915 22:55:58.842903 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2916 22:55:58.846523 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2917 22:55:58.849844 iDelay=200, Bit 5, Center 119 (48 ~ 191) 144
2918 22:55:58.853246 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2919 22:55:58.856899 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2920 22:55:58.863388 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2921 22:55:58.866443 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2922 22:55:58.870016 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2923 22:55:58.873271 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2924 22:55:58.876583 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2925 22:55:58.883553 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2926 22:55:58.887104 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2927 22:55:58.889775 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
2928 22:55:58.890333 ==
2929 22:55:58.893487 Dram Type= 6, Freq= 0, CH_0, rank 1
2930 22:55:58.896232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2931 22:55:58.896707 ==
2932 22:55:58.900147 DQS Delay:
2933 22:55:58.900709 DQS0 = 0, DQS1 = 0
2934 22:55:58.903442 DQM Delay:
2935 22:55:58.903996 DQM0 = 122, DQM1 = 112
2936 22:55:58.904370 DQ Delay:
2937 22:55:58.906832 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =119
2938 22:55:58.910116 DQ4 =127, DQ5 =119, DQ6 =127, DQ7 =127
2939 22:55:58.916294 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
2940 22:55:58.920294 DQ12 =115, DQ13 =119, DQ14 =123, DQ15 =123
2941 22:55:58.920873
2942 22:55:58.921246
2943 22:55:58.921589 ==
2944 22:55:58.923625 Dram Type= 6, Freq= 0, CH_0, rank 1
2945 22:55:58.926560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2946 22:55:58.927181 ==
2947 22:55:58.927612
2948 22:55:58.927961
2949 22:55:58.929662 TX Vref Scan disable
2950 22:55:58.930122 == TX Byte 0 ==
2951 22:55:58.937207 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2952 22:55:58.940097 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2953 22:55:58.940569 == TX Byte 1 ==
2954 22:55:58.947155 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2955 22:55:58.950524 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2956 22:55:58.951085 ==
2957 22:55:58.953267 Dram Type= 6, Freq= 0, CH_0, rank 1
2958 22:55:58.956858 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2959 22:55:58.957395 ==
2960 22:55:58.969705 TX Vref=22, minBit 1, minWin=25, winSum=418
2961 22:55:58.973381 TX Vref=24, minBit 1, minWin=25, winSum=422
2962 22:55:58.976821 TX Vref=26, minBit 0, minWin=26, winSum=425
2963 22:55:58.979673 TX Vref=28, minBit 0, minWin=26, winSum=425
2964 22:55:58.983414 TX Vref=30, minBit 1, minWin=26, winSum=432
2965 22:55:58.986583 TX Vref=32, minBit 13, minWin=25, winSum=424
2966 22:55:58.993538 [TxChooseVref] Worse bit 1, Min win 26, Win sum 432, Final Vref 30
2967 22:55:58.994108
2968 22:55:58.996621 Final TX Range 1 Vref 30
2969 22:55:58.997196
2970 22:55:58.997572 ==
2971 22:55:59.000156 Dram Type= 6, Freq= 0, CH_0, rank 1
2972 22:55:59.003368 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2973 22:55:59.003944 ==
2974 22:55:59.004316
2975 22:55:59.004657
2976 22:55:59.006383 TX Vref Scan disable
2977 22:55:59.009712 == TX Byte 0 ==
2978 22:55:59.013067 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2979 22:55:59.016745 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2980 22:55:59.019703 == TX Byte 1 ==
2981 22:55:59.023760 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2982 22:55:59.026842 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2983 22:55:59.027450
2984 22:55:59.029878 [DATLAT]
2985 22:55:59.030340 Freq=1200, CH0 RK1
2986 22:55:59.030710
2987 22:55:59.033516 DATLAT Default: 0xd
2988 22:55:59.034102 0, 0xFFFF, sum = 0
2989 22:55:59.036643 1, 0xFFFF, sum = 0
2990 22:55:59.037117 2, 0xFFFF, sum = 0
2991 22:55:59.040060 3, 0xFFFF, sum = 0
2992 22:55:59.040638 4, 0xFFFF, sum = 0
2993 22:55:59.043310 5, 0xFFFF, sum = 0
2994 22:55:59.043831 6, 0xFFFF, sum = 0
2995 22:55:59.046633 7, 0xFFFF, sum = 0
2996 22:55:59.047265 8, 0xFFFF, sum = 0
2997 22:55:59.050036 9, 0xFFFF, sum = 0
2998 22:55:59.053145 10, 0xFFFF, sum = 0
2999 22:55:59.053655 11, 0xFFFF, sum = 0
3000 22:55:59.056457 12, 0x0, sum = 1
3001 22:55:59.056980 13, 0x0, sum = 2
3002 22:55:59.057411 14, 0x0, sum = 3
3003 22:55:59.060095 15, 0x0, sum = 4
3004 22:55:59.060691 best_step = 13
3005 22:55:59.061076
3006 22:55:59.063198 ==
3007 22:55:59.063742 Dram Type= 6, Freq= 0, CH_0, rank 1
3008 22:55:59.069966 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3009 22:55:59.070539 ==
3010 22:55:59.070916 RX Vref Scan: 0
3011 22:55:59.071289
3012 22:55:59.073791 RX Vref 0 -> 0, step: 1
3013 22:55:59.074429
3014 22:55:59.077129 RX Delay -13 -> 252, step: 4
3015 22:55:59.080208 iDelay=195, Bit 0, Center 120 (51 ~ 190) 140
3016 22:55:59.083015 iDelay=195, Bit 1, Center 120 (55 ~ 186) 132
3017 22:55:59.090235 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3018 22:55:59.093956 iDelay=195, Bit 3, Center 120 (51 ~ 190) 140
3019 22:55:59.097084 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3020 22:55:59.100715 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3021 22:55:59.103415 iDelay=195, Bit 6, Center 128 (63 ~ 194) 132
3022 22:55:59.107525 iDelay=195, Bit 7, Center 128 (63 ~ 194) 132
3023 22:55:59.113989 iDelay=195, Bit 8, Center 100 (35 ~ 166) 132
3024 22:55:59.116553 iDelay=195, Bit 9, Center 96 (31 ~ 162) 132
3025 22:55:59.120573 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3026 22:55:59.123226 iDelay=195, Bit 11, Center 100 (35 ~ 166) 132
3027 22:55:59.130351 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3028 22:55:59.133429 iDelay=195, Bit 13, Center 116 (55 ~ 178) 124
3029 22:55:59.136457 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3030 22:55:59.140204 iDelay=195, Bit 15, Center 120 (55 ~ 186) 132
3031 22:55:59.140766 ==
3032 22:55:59.143390 Dram Type= 6, Freq= 0, CH_0, rank 1
3033 22:55:59.146620 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3034 22:55:59.150289 ==
3035 22:55:59.150854 DQS Delay:
3036 22:55:59.151221 DQS0 = 0, DQS1 = 0
3037 22:55:59.153308 DQM Delay:
3038 22:55:59.153810 DQM0 = 121, DQM1 = 109
3039 22:55:59.157037 DQ Delay:
3040 22:55:59.159988 DQ0 =120, DQ1 =120, DQ2 =118, DQ3 =120
3041 22:55:59.163357 DQ4 =122, DQ5 =116, DQ6 =128, DQ7 =128
3042 22:55:59.167208 DQ8 =100, DQ9 =96, DQ10 =110, DQ11 =100
3043 22:55:59.170481 DQ12 =114, DQ13 =116, DQ14 =122, DQ15 =120
3044 22:55:59.170937
3045 22:55:59.171304
3046 22:55:59.177212 [DQSOSCAuto] RK1, (LSB)MR18= 0x12f2, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 403 ps
3047 22:55:59.180080 CH0 RK1: MR19=403, MR18=12F2
3048 22:55:59.187221 CH0_RK1: MR19=0x403, MR18=0x12F2, DQSOSC=403, MR23=63, INC=40, DEC=26
3049 22:55:59.189773 [RxdqsGatingPostProcess] freq 1200
3050 22:55:59.196689 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3051 22:55:59.200184 best DQS0 dly(2T, 0.5T) = (0, 11)
3052 22:55:59.200851 best DQS1 dly(2T, 0.5T) = (0, 12)
3053 22:55:59.203241 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3054 22:55:59.206734 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3055 22:55:59.209558 best DQS0 dly(2T, 0.5T) = (0, 11)
3056 22:55:59.213438 best DQS1 dly(2T, 0.5T) = (0, 11)
3057 22:55:59.216795 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3058 22:55:59.219773 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3059 22:55:59.223427 Pre-setting of DQS Precalculation
3060 22:55:59.230004 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3061 22:55:59.230542 ==
3062 22:55:59.232947 Dram Type= 6, Freq= 0, CH_1, rank 0
3063 22:55:59.236284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3064 22:55:59.236711 ==
3065 22:55:59.243290 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3066 22:55:59.246624 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3067 22:55:59.255706 [CA 0] Center 37 (7~68) winsize 62
3068 22:55:59.259317 [CA 1] Center 37 (7~68) winsize 62
3069 22:55:59.262469 [CA 2] Center 35 (5~65) winsize 61
3070 22:55:59.265780 [CA 3] Center 34 (4~64) winsize 61
3071 22:55:59.268970 [CA 4] Center 34 (5~64) winsize 60
3072 22:55:59.273005 [CA 5] Center 33 (3~63) winsize 61
3073 22:55:59.273429
3074 22:55:59.275834 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3075 22:55:59.276257
3076 22:55:59.279269 [CATrainingPosCal] consider 1 rank data
3077 22:55:59.282766 u2DelayCellTimex100 = 270/100 ps
3078 22:55:59.286156 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3079 22:55:59.289711 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3080 22:55:59.295845 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3081 22:55:59.299244 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3082 22:55:59.302637 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3083 22:55:59.306348 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3084 22:55:59.306768
3085 22:55:59.309374 CA PerBit enable=1, Macro0, CA PI delay=33
3086 22:55:59.309797
3087 22:55:59.313006 [CBTSetCACLKResult] CA Dly = 33
3088 22:55:59.313430 CS Dly: 8 (0~39)
3089 22:55:59.313760 ==
3090 22:55:59.316755 Dram Type= 6, Freq= 0, CH_1, rank 1
3091 22:55:59.323107 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3092 22:55:59.323580 ==
3093 22:55:59.326315 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3094 22:55:59.333063 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3095 22:55:59.341819 [CA 0] Center 37 (7~68) winsize 62
3096 22:55:59.344740 [CA 1] Center 38 (8~68) winsize 61
3097 22:55:59.347932 [CA 2] Center 35 (5~65) winsize 61
3098 22:55:59.351120 [CA 3] Center 34 (4~65) winsize 62
3099 22:55:59.354369 [CA 4] Center 34 (4~65) winsize 62
3100 22:55:59.357837 [CA 5] Center 34 (4~64) winsize 61
3101 22:55:59.357921
3102 22:55:59.361276 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3103 22:55:59.361360
3104 22:55:59.364588 [CATrainingPosCal] consider 2 rank data
3105 22:55:59.367783 u2DelayCellTimex100 = 270/100 ps
3106 22:55:59.371190 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3107 22:55:59.375108 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3108 22:55:59.378377 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3109 22:55:59.384869 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3110 22:55:59.388429 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3111 22:55:59.391560 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3112 22:55:59.391643
3113 22:55:59.394795 CA PerBit enable=1, Macro0, CA PI delay=33
3114 22:55:59.394878
3115 22:55:59.398406 [CBTSetCACLKResult] CA Dly = 33
3116 22:55:59.398515 CS Dly: 9 (0~41)
3117 22:55:59.398616
3118 22:55:59.401331 ----->DramcWriteLeveling(PI) begin...
3119 22:55:59.401440 ==
3120 22:55:59.404886 Dram Type= 6, Freq= 0, CH_1, rank 0
3121 22:55:59.411601 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3122 22:55:59.411685 ==
3123 22:55:59.415093 Write leveling (Byte 0): 28 => 28
3124 22:55:59.418616 Write leveling (Byte 1): 27 => 27
3125 22:55:59.418699 DramcWriteLeveling(PI) end<-----
3126 22:55:59.418782
3127 22:55:59.421544 ==
3128 22:55:59.425201 Dram Type= 6, Freq= 0, CH_1, rank 0
3129 22:55:59.428232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3130 22:55:59.428316 ==
3131 22:55:59.431839 [Gating] SW mode calibration
3132 22:55:59.438240 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3133 22:55:59.441601 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3134 22:55:59.448640 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3135 22:55:59.451693 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3136 22:55:59.455298 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3137 22:55:59.461855 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3138 22:55:59.464914 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3139 22:55:59.468521 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3140 22:55:59.475076 0 15 24 | B1->B0 | 3434 2e2e | 0 1 | (0 1) (1 0)
3141 22:55:59.478544 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
3142 22:55:59.481849 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3143 22:55:59.485304 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3144 22:55:59.491701 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3145 22:55:59.495220 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3146 22:55:59.498566 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3147 22:55:59.505478 1 0 20 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
3148 22:55:59.508945 1 0 24 | B1->B0 | 3434 3a3a | 1 0 | (0 0) (0 0)
3149 22:55:59.512183 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3150 22:55:59.518799 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3151 22:55:59.521777 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3152 22:55:59.525506 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3153 22:55:59.532248 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3154 22:55:59.535703 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3155 22:55:59.538612 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3156 22:55:59.545295 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3157 22:55:59.548650 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3158 22:55:59.551997 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3159 22:55:59.558430 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3160 22:55:59.562030 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3161 22:55:59.565480 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3162 22:55:59.568882 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3163 22:55:59.575412 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3164 22:55:59.578893 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3165 22:55:59.582083 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3166 22:55:59.588948 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 22:55:59.592389 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 22:55:59.595030 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 22:55:59.602023 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 22:55:59.605114 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 22:55:59.608339 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3172 22:55:59.615346 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3173 22:55:59.618473 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3174 22:55:59.622081 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3175 22:55:59.625208 Total UI for P1: 0, mck2ui 16
3176 22:55:59.628673 best dqsien dly found for B0: ( 1, 3, 26)
3177 22:55:59.632166 Total UI for P1: 0, mck2ui 16
3178 22:55:59.635079 best dqsien dly found for B1: ( 1, 3, 26)
3179 22:55:59.638723 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3180 22:55:59.641841 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3181 22:55:59.641955
3182 22:55:59.645464 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3183 22:55:59.651859 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3184 22:55:59.651978 [Gating] SW calibration Done
3185 22:55:59.652078 ==
3186 22:55:59.655484 Dram Type= 6, Freq= 0, CH_1, rank 0
3187 22:55:59.662067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3188 22:55:59.662177 ==
3189 22:55:59.662273 RX Vref Scan: 0
3190 22:55:59.662364
3191 22:55:59.665157 RX Vref 0 -> 0, step: 1
3192 22:55:59.665253
3193 22:55:59.668819 RX Delay -40 -> 252, step: 8
3194 22:55:59.671852 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3195 22:55:59.675240 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3196 22:55:59.678881 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3197 22:55:59.685165 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3198 22:55:59.688467 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3199 22:55:59.691705 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3200 22:55:59.695174 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3201 22:55:59.699078 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3202 22:55:59.701739 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3203 22:55:59.708647 iDelay=200, Bit 9, Center 103 (40 ~ 167) 128
3204 22:55:59.711978 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3205 22:55:59.715290 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3206 22:55:59.718498 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3207 22:55:59.725385 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3208 22:55:59.729018 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3209 22:55:59.732033 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3210 22:55:59.732114 ==
3211 22:55:59.735489 Dram Type= 6, Freq= 0, CH_1, rank 0
3212 22:55:59.738551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3213 22:55:59.738632 ==
3214 22:55:59.742237 DQS Delay:
3215 22:55:59.742318 DQS0 = 0, DQS1 = 0
3216 22:55:59.745730 DQM Delay:
3217 22:55:59.745810 DQM0 = 120, DQM1 = 116
3218 22:55:59.745874 DQ Delay:
3219 22:55:59.748612 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3220 22:55:59.752173 DQ4 =119, DQ5 =127, DQ6 =127, DQ7 =123
3221 22:55:59.758598 DQ8 =103, DQ9 =103, DQ10 =115, DQ11 =111
3222 22:55:59.762008 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3223 22:55:59.762090
3224 22:55:59.762154
3225 22:55:59.762212 ==
3226 22:55:59.765366 Dram Type= 6, Freq= 0, CH_1, rank 0
3227 22:55:59.768886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3228 22:55:59.768968 ==
3229 22:55:59.769034
3230 22:55:59.769092
3231 22:55:59.772000 TX Vref Scan disable
3232 22:55:59.772081 == TX Byte 0 ==
3233 22:55:59.778948 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3234 22:55:59.782128 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3235 22:55:59.782210 == TX Byte 1 ==
3236 22:55:59.789051 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3237 22:55:59.792085 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3238 22:55:59.792168 ==
3239 22:55:59.795575 Dram Type= 6, Freq= 0, CH_1, rank 0
3240 22:55:59.799252 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3241 22:55:59.799344 ==
3242 22:55:59.811570 TX Vref=22, minBit 9, minWin=24, winSum=407
3243 22:55:59.815058 TX Vref=24, minBit 0, minWin=25, winSum=417
3244 22:55:59.818164 TX Vref=26, minBit 9, minWin=25, winSum=424
3245 22:55:59.821543 TX Vref=28, minBit 1, minWin=26, winSum=428
3246 22:55:59.825054 TX Vref=30, minBit 1, minWin=26, winSum=427
3247 22:55:59.828185 TX Vref=32, minBit 10, minWin=25, winSum=430
3248 22:55:59.834837 [TxChooseVref] Worse bit 1, Min win 26, Win sum 428, Final Vref 28
3249 22:55:59.834919
3250 22:55:59.838430 Final TX Range 1 Vref 28
3251 22:55:59.838513
3252 22:55:59.838577 ==
3253 22:55:59.841524 Dram Type= 6, Freq= 0, CH_1, rank 0
3254 22:55:59.844727 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3255 22:55:59.844814 ==
3256 22:55:59.844879
3257 22:55:59.848199
3258 22:55:59.848294 TX Vref Scan disable
3259 22:55:59.851659 == TX Byte 0 ==
3260 22:55:59.854934 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3261 22:55:59.858701 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3262 22:55:59.862072 == TX Byte 1 ==
3263 22:55:59.865026 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3264 22:55:59.868047 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3265 22:55:59.868137
3266 22:55:59.871866 [DATLAT]
3267 22:55:59.871939 Freq=1200, CH1 RK0
3268 22:55:59.872002
3269 22:55:59.875044 DATLAT Default: 0xd
3270 22:55:59.875121 0, 0xFFFF, sum = 0
3271 22:55:59.878328 1, 0xFFFF, sum = 0
3272 22:55:59.878398 2, 0xFFFF, sum = 0
3273 22:55:59.881599 3, 0xFFFF, sum = 0
3274 22:55:59.881674 4, 0xFFFF, sum = 0
3275 22:55:59.885120 5, 0xFFFF, sum = 0
3276 22:55:59.885190 6, 0xFFFF, sum = 0
3277 22:55:59.888194 7, 0xFFFF, sum = 0
3278 22:55:59.888263 8, 0xFFFF, sum = 0
3279 22:55:59.891635 9, 0xFFFF, sum = 0
3280 22:55:59.891707 10, 0xFFFF, sum = 0
3281 22:55:59.894976 11, 0xFFFF, sum = 0
3282 22:55:59.895056 12, 0x0, sum = 1
3283 22:55:59.898673 13, 0x0, sum = 2
3284 22:55:59.898757 14, 0x0, sum = 3
3285 22:55:59.901923 15, 0x0, sum = 4
3286 22:55:59.901996 best_step = 13
3287 22:55:59.902072
3288 22:55:59.902160 ==
3289 22:55:59.905447 Dram Type= 6, Freq= 0, CH_1, rank 0
3290 22:55:59.912084 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3291 22:55:59.912157 ==
3292 22:55:59.912222 RX Vref Scan: 1
3293 22:55:59.912280
3294 22:55:59.915147 Set Vref Range= 32 -> 127
3295 22:55:59.915211
3296 22:55:59.918685 RX Vref 32 -> 127, step: 1
3297 22:55:59.918758
3298 22:55:59.918819 RX Delay -5 -> 252, step: 4
3299 22:55:59.922244
3300 22:55:59.922322 Set Vref, RX VrefLevel [Byte0]: 32
3301 22:55:59.925044 [Byte1]: 32
3302 22:55:59.929423
3303 22:55:59.929492 Set Vref, RX VrefLevel [Byte0]: 33
3304 22:55:59.933258 [Byte1]: 33
3305 22:55:59.938036
3306 22:55:59.938112 Set Vref, RX VrefLevel [Byte0]: 34
3307 22:55:59.940674 [Byte1]: 34
3308 22:55:59.944996
3309 22:55:59.945065 Set Vref, RX VrefLevel [Byte0]: 35
3310 22:55:59.948710 [Byte1]: 35
3311 22:55:59.952952
3312 22:55:59.953021 Set Vref, RX VrefLevel [Byte0]: 36
3313 22:55:59.956581 [Byte1]: 36
3314 22:55:59.961477
3315 22:55:59.961556 Set Vref, RX VrefLevel [Byte0]: 37
3316 22:55:59.964336 [Byte1]: 37
3317 22:55:59.969231
3318 22:55:59.969310 Set Vref, RX VrefLevel [Byte0]: 38
3319 22:55:59.972309 [Byte1]: 38
3320 22:55:59.976745
3321 22:55:59.976824 Set Vref, RX VrefLevel [Byte0]: 39
3322 22:55:59.980277 [Byte1]: 39
3323 22:55:59.984622
3324 22:55:59.984701 Set Vref, RX VrefLevel [Byte0]: 40
3325 22:55:59.987847 [Byte1]: 40
3326 22:55:59.992314
3327 22:55:59.992393 Set Vref, RX VrefLevel [Byte0]: 41
3328 22:55:59.995669 [Byte1]: 41
3329 22:56:00.000571
3330 22:56:00.000654 Set Vref, RX VrefLevel [Byte0]: 42
3331 22:56:00.003292 [Byte1]: 42
3332 22:56:00.008288
3333 22:56:00.008431 Set Vref, RX VrefLevel [Byte0]: 43
3334 22:56:00.011208 [Byte1]: 43
3335 22:56:00.016042
3336 22:56:00.016121 Set Vref, RX VrefLevel [Byte0]: 44
3337 22:56:00.019468 [Byte1]: 44
3338 22:56:00.023761
3339 22:56:00.026880 Set Vref, RX VrefLevel [Byte0]: 45
3340 22:56:00.026960 [Byte1]: 45
3341 22:56:00.031468
3342 22:56:00.031548 Set Vref, RX VrefLevel [Byte0]: 46
3343 22:56:00.034903 [Byte1]: 46
3344 22:56:00.039375
3345 22:56:00.039455 Set Vref, RX VrefLevel [Byte0]: 47
3346 22:56:00.042776 [Byte1]: 47
3347 22:56:00.047737
3348 22:56:00.047816 Set Vref, RX VrefLevel [Byte0]: 48
3349 22:56:00.050711 [Byte1]: 48
3350 22:56:00.054951
3351 22:56:00.055033 Set Vref, RX VrefLevel [Byte0]: 49
3352 22:56:00.058759 [Byte1]: 49
3353 22:56:00.062979
3354 22:56:00.063058 Set Vref, RX VrefLevel [Byte0]: 50
3355 22:56:00.066293 [Byte1]: 50
3356 22:56:00.071105
3357 22:56:00.071184 Set Vref, RX VrefLevel [Byte0]: 51
3358 22:56:00.074099 [Byte1]: 51
3359 22:56:00.078864
3360 22:56:00.078943 Set Vref, RX VrefLevel [Byte0]: 52
3361 22:56:00.081820 [Byte1]: 52
3362 22:56:00.087016
3363 22:56:00.087095 Set Vref, RX VrefLevel [Byte0]: 53
3364 22:56:00.089749 [Byte1]: 53
3365 22:56:00.094224
3366 22:56:00.094304 Set Vref, RX VrefLevel [Byte0]: 54
3367 22:56:00.098262 [Byte1]: 54
3368 22:56:00.102407
3369 22:56:00.102495 Set Vref, RX VrefLevel [Byte0]: 55
3370 22:56:00.105542 [Byte1]: 55
3371 22:56:00.110107
3372 22:56:00.110191 Set Vref, RX VrefLevel [Byte0]: 56
3373 22:56:00.113429 [Byte1]: 56
3374 22:56:00.118376
3375 22:56:00.118458 Set Vref, RX VrefLevel [Byte0]: 57
3376 22:56:00.121016 [Byte1]: 57
3377 22:56:00.125952
3378 22:56:00.126056 Set Vref, RX VrefLevel [Byte0]: 58
3379 22:56:00.129440 [Byte1]: 58
3380 22:56:00.133882
3381 22:56:00.133987 Set Vref, RX VrefLevel [Byte0]: 59
3382 22:56:00.136992 [Byte1]: 59
3383 22:56:00.141562
3384 22:56:00.141677 Set Vref, RX VrefLevel [Byte0]: 60
3385 22:56:00.144674 [Byte1]: 60
3386 22:56:00.149823
3387 22:56:00.149926 Set Vref, RX VrefLevel [Byte0]: 61
3388 22:56:00.152810 [Byte1]: 61
3389 22:56:00.157210
3390 22:56:00.157318 Set Vref, RX VrefLevel [Byte0]: 62
3391 22:56:00.160662 [Byte1]: 62
3392 22:56:00.164849
3393 22:56:00.164963 Set Vref, RX VrefLevel [Byte0]: 63
3394 22:56:00.168444 [Byte1]: 63
3395 22:56:00.173095
3396 22:56:00.173194 Set Vref, RX VrefLevel [Byte0]: 64
3397 22:56:00.176017 [Byte1]: 64
3398 22:56:00.180934
3399 22:56:00.181038 Set Vref, RX VrefLevel [Byte0]: 65
3400 22:56:00.183895 [Byte1]: 65
3401 22:56:00.188579
3402 22:56:00.191554 Set Vref, RX VrefLevel [Byte0]: 66
3403 22:56:00.195168 [Byte1]: 66
3404 22:56:00.195268
3405 22:56:00.198552 Set Vref, RX VrefLevel [Byte0]: 67
3406 22:56:00.201872 [Byte1]: 67
3407 22:56:00.201974
3408 22:56:00.204952 Set Vref, RX VrefLevel [Byte0]: 68
3409 22:56:00.208264 [Byte1]: 68
3410 22:56:00.212567
3411 22:56:00.212678 Set Vref, RX VrefLevel [Byte0]: 69
3412 22:56:00.215495 [Byte1]: 69
3413 22:56:00.220076
3414 22:56:00.220192 Final RX Vref Byte 0 = 54 to rank0
3415 22:56:00.223239 Final RX Vref Byte 1 = 47 to rank0
3416 22:56:00.226747 Final RX Vref Byte 0 = 54 to rank1
3417 22:56:00.229924 Final RX Vref Byte 1 = 47 to rank1==
3418 22:56:00.233853 Dram Type= 6, Freq= 0, CH_1, rank 0
3419 22:56:00.237104 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3420 22:56:00.240166 ==
3421 22:56:00.240270 DQS Delay:
3422 22:56:00.240376 DQS0 = 0, DQS1 = 0
3423 22:56:00.243464 DQM Delay:
3424 22:56:00.243579 DQM0 = 120, DQM1 = 116
3425 22:56:00.246851 DQ Delay:
3426 22:56:00.250315 DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =118
3427 22:56:00.253901 DQ4 =120, DQ5 =128, DQ6 =130, DQ7 =120
3428 22:56:00.257232 DQ8 =104, DQ9 =106, DQ10 =118, DQ11 =108
3429 22:56:00.260090 DQ12 =122, DQ13 =124, DQ14 =124, DQ15 =126
3430 22:56:00.260201
3431 22:56:00.260295
3432 22:56:00.266923 [DQSOSCAuto] RK0, (LSB)MR18= 0x416, (MSB)MR19= 0x404, tDQSOscB0 = 401 ps tDQSOscB1 = 408 ps
3433 22:56:00.270009 CH1 RK0: MR19=404, MR18=416
3434 22:56:00.277120 CH1_RK0: MR19=0x404, MR18=0x416, DQSOSC=401, MR23=63, INC=40, DEC=27
3435 22:56:00.277231
3436 22:56:00.280225 ----->DramcWriteLeveling(PI) begin...
3437 22:56:00.280335 ==
3438 22:56:00.284005 Dram Type= 6, Freq= 0, CH_1, rank 1
3439 22:56:00.286874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3440 22:56:00.286974 ==
3441 22:56:00.290282 Write leveling (Byte 0): 26 => 26
3442 22:56:00.294147 Write leveling (Byte 1): 27 => 27
3443 22:56:00.297044 DramcWriteLeveling(PI) end<-----
3444 22:56:00.297142
3445 22:56:00.297231 ==
3446 22:56:00.300415 Dram Type= 6, Freq= 0, CH_1, rank 1
3447 22:56:00.303888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3448 22:56:00.303991 ==
3449 22:56:00.307444 [Gating] SW mode calibration
3450 22:56:00.314133 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3451 22:56:00.320451 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3452 22:56:00.323749 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3453 22:56:00.330892 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3454 22:56:00.333718 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3455 22:56:00.337337 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3456 22:56:00.344019 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3457 22:56:00.347572 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
3458 22:56:00.350792 0 15 24 | B1->B0 | 2a2a 3333 | 0 1 | (0 0) (1 0)
3459 22:56:00.354308 0 15 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3460 22:56:00.360662 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3461 22:56:00.363929 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3462 22:56:00.367213 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3463 22:56:00.373800 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3464 22:56:00.377572 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3465 22:56:00.380485 1 0 20 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
3466 22:56:00.387253 1 0 24 | B1->B0 | 4343 2d2d | 0 0 | (0 0) (0 0)
3467 22:56:00.390594 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3468 22:56:00.394150 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3469 22:56:00.400588 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3470 22:56:00.403839 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3471 22:56:00.407654 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3472 22:56:00.414136 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3473 22:56:00.417653 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3474 22:56:00.420917 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3475 22:56:00.427539 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3476 22:56:00.430421 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3477 22:56:00.433810 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3478 22:56:00.440305 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3479 22:56:00.443916 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3480 22:56:00.446861 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3481 22:56:00.453922 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3482 22:56:00.457211 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3483 22:56:00.460490 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3484 22:56:00.463853 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3485 22:56:00.470209 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3486 22:56:00.474170 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3487 22:56:00.477000 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3488 22:56:00.483700 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3489 22:56:00.486830 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3490 22:56:00.490496 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3491 22:56:00.497138 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3492 22:56:00.500599 Total UI for P1: 0, mck2ui 16
3493 22:56:00.503637 best dqsien dly found for B0: ( 1, 3, 24)
3494 22:56:00.506678 Total UI for P1: 0, mck2ui 16
3495 22:56:00.510167 best dqsien dly found for B1: ( 1, 3, 24)
3496 22:56:00.513392 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3497 22:56:00.517496 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3498 22:56:00.517923
3499 22:56:00.520247 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3500 22:56:00.524001 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3501 22:56:00.527135 [Gating] SW calibration Done
3502 22:56:00.527573 ==
3503 22:56:00.530603 Dram Type= 6, Freq= 0, CH_1, rank 1
3504 22:56:00.534401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3505 22:56:00.534819 ==
3506 22:56:00.537009 RX Vref Scan: 0
3507 22:56:00.537468
3508 22:56:00.537798 RX Vref 0 -> 0, step: 1
3509 22:56:00.540497
3510 22:56:00.540927 RX Delay -40 -> 252, step: 8
3511 22:56:00.547482 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3512 22:56:00.550478 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
3513 22:56:00.554185 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3514 22:56:00.556920 iDelay=200, Bit 3, Center 119 (56 ~ 183) 128
3515 22:56:00.560385 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3516 22:56:00.567221 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3517 22:56:00.570683 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3518 22:56:00.574069 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3519 22:56:00.577480 iDelay=200, Bit 8, Center 107 (40 ~ 175) 136
3520 22:56:00.580208 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3521 22:56:00.583717 iDelay=200, Bit 10, Center 119 (56 ~ 183) 128
3522 22:56:00.590749 iDelay=200, Bit 11, Center 115 (48 ~ 183) 136
3523 22:56:00.593706 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3524 22:56:00.597247 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3525 22:56:00.600835 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3526 22:56:00.607243 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
3527 22:56:00.607845 ==
3528 22:56:00.610066 Dram Type= 6, Freq= 0, CH_1, rank 1
3529 22:56:00.613822 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3530 22:56:00.614386 ==
3531 22:56:00.614761 DQS Delay:
3532 22:56:00.616858 DQS0 = 0, DQS1 = 0
3533 22:56:00.617328 DQM Delay:
3534 22:56:00.620253 DQM0 = 120, DQM1 = 119
3535 22:56:00.620721 DQ Delay:
3536 22:56:00.623377 DQ0 =123, DQ1 =119, DQ2 =107, DQ3 =119
3537 22:56:00.626883 DQ4 =115, DQ5 =131, DQ6 =131, DQ7 =119
3538 22:56:00.630065 DQ8 =107, DQ9 =107, DQ10 =119, DQ11 =115
3539 22:56:00.633664 DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =127
3540 22:56:00.634234
3541 22:56:00.636616
3542 22:56:00.637084 ==
3543 22:56:00.640345 Dram Type= 6, Freq= 0, CH_1, rank 1
3544 22:56:00.643428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3545 22:56:00.643909 ==
3546 22:56:00.644283
3547 22:56:00.644628
3548 22:56:00.646583 TX Vref Scan disable
3549 22:56:00.647142 == TX Byte 0 ==
3550 22:56:00.650403 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3551 22:56:00.657163 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3552 22:56:00.657715 == TX Byte 1 ==
3553 22:56:00.660059 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3554 22:56:00.666594 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3555 22:56:00.667146 ==
3556 22:56:00.670421 Dram Type= 6, Freq= 0, CH_1, rank 1
3557 22:56:00.673758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3558 22:56:00.674233 ==
3559 22:56:00.685460 TX Vref=22, minBit 9, minWin=24, winSum=420
3560 22:56:00.689062 TX Vref=24, minBit 10, minWin=25, winSum=426
3561 22:56:00.692011 TX Vref=26, minBit 2, minWin=26, winSum=427
3562 22:56:00.695790 TX Vref=28, minBit 9, minWin=26, winSum=433
3563 22:56:00.698674 TX Vref=30, minBit 9, minWin=26, winSum=434
3564 22:56:00.702424 TX Vref=32, minBit 6, minWin=26, winSum=431
3565 22:56:00.709039 [TxChooseVref] Worse bit 9, Min win 26, Win sum 434, Final Vref 30
3566 22:56:00.709607
3567 22:56:00.712155 Final TX Range 1 Vref 30
3568 22:56:00.712716
3569 22:56:00.713088 ==
3570 22:56:00.715943 Dram Type= 6, Freq= 0, CH_1, rank 1
3571 22:56:00.718897 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3572 22:56:00.719555 ==
3573 22:56:00.720040
3574 22:56:00.722639
3575 22:56:00.723209 TX Vref Scan disable
3576 22:56:00.725269 == TX Byte 0 ==
3577 22:56:00.728695 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3578 22:56:00.731948 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3579 22:56:00.735188 == TX Byte 1 ==
3580 22:56:00.738677 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3581 22:56:00.742006 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3582 22:56:00.742620
3583 22:56:00.745137 [DATLAT]
3584 22:56:00.745620 Freq=1200, CH1 RK1
3585 22:56:00.746004
3586 22:56:00.748800 DATLAT Default: 0xd
3587 22:56:00.749266 0, 0xFFFF, sum = 0
3588 22:56:00.751791 1, 0xFFFF, sum = 0
3589 22:56:00.752268 2, 0xFFFF, sum = 0
3590 22:56:00.755290 3, 0xFFFF, sum = 0
3591 22:56:00.755918 4, 0xFFFF, sum = 0
3592 22:56:00.758309 5, 0xFFFF, sum = 0
3593 22:56:00.758806 6, 0xFFFF, sum = 0
3594 22:56:00.761824 7, 0xFFFF, sum = 0
3595 22:56:00.762302 8, 0xFFFF, sum = 0
3596 22:56:00.765302 9, 0xFFFF, sum = 0
3597 22:56:00.768763 10, 0xFFFF, sum = 0
3598 22:56:00.769243 11, 0xFFFF, sum = 0
3599 22:56:00.771841 12, 0x0, sum = 1
3600 22:56:00.772318 13, 0x0, sum = 2
3601 22:56:00.772697 14, 0x0, sum = 3
3602 22:56:00.775311 15, 0x0, sum = 4
3603 22:56:00.775832 best_step = 13
3604 22:56:00.776207
3605 22:56:00.778606 ==
3606 22:56:00.779075 Dram Type= 6, Freq= 0, CH_1, rank 1
3607 22:56:00.785678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3608 22:56:00.786248 ==
3609 22:56:00.786624 RX Vref Scan: 0
3610 22:56:00.786973
3611 22:56:00.789039 RX Vref 0 -> 0, step: 1
3612 22:56:00.789656
3613 22:56:00.791655 RX Delay -5 -> 252, step: 4
3614 22:56:00.795724 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3615 22:56:00.798845 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3616 22:56:00.805564 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3617 22:56:00.808666 iDelay=195, Bit 3, Center 118 (59 ~ 178) 120
3618 22:56:00.811867 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3619 22:56:00.815515 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3620 22:56:00.818430 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3621 22:56:00.825265 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3622 22:56:00.828413 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
3623 22:56:00.831988 iDelay=195, Bit 9, Center 106 (47 ~ 166) 120
3624 22:56:00.835383 iDelay=195, Bit 10, Center 116 (55 ~ 178) 124
3625 22:56:00.839171 iDelay=195, Bit 11, Center 110 (51 ~ 170) 120
3626 22:56:00.845387 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3627 22:56:00.848452 iDelay=195, Bit 13, Center 122 (63 ~ 182) 120
3628 22:56:00.851697 iDelay=195, Bit 14, Center 122 (63 ~ 182) 120
3629 22:56:00.855313 iDelay=195, Bit 15, Center 124 (63 ~ 186) 124
3630 22:56:00.855937 ==
3631 22:56:00.858698 Dram Type= 6, Freq= 0, CH_1, rank 1
3632 22:56:00.865071 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3633 22:56:00.865544 ==
3634 22:56:00.865960 DQS Delay:
3635 22:56:00.868330 DQS0 = 0, DQS1 = 0
3636 22:56:00.868813 DQM Delay:
3637 22:56:00.869186 DQM0 = 120, DQM1 = 116
3638 22:56:00.871431 DQ Delay:
3639 22:56:00.874651 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =118
3640 22:56:00.878139 DQ4 =116, DQ5 =130, DQ6 =130, DQ7 =120
3641 22:56:00.881392 DQ8 =106, DQ9 =106, DQ10 =116, DQ11 =110
3642 22:56:00.884799 DQ12 =126, DQ13 =122, DQ14 =122, DQ15 =124
3643 22:56:00.885271
3644 22:56:00.885640
3645 22:56:00.895218 [DQSOSCAuto] RK1, (LSB)MR18= 0x10ed, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 403 ps
3646 22:56:00.895838 CH1 RK1: MR19=403, MR18=10ED
3647 22:56:00.902008 CH1_RK1: MR19=0x403, MR18=0x10ED, DQSOSC=403, MR23=63, INC=40, DEC=26
3648 22:56:00.905329 [RxdqsGatingPostProcess] freq 1200
3649 22:56:00.911950 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3650 22:56:00.914851 best DQS0 dly(2T, 0.5T) = (0, 11)
3651 22:56:00.918359 best DQS1 dly(2T, 0.5T) = (0, 11)
3652 22:56:00.921388 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3653 22:56:00.924856 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3654 22:56:00.928485 best DQS0 dly(2T, 0.5T) = (0, 11)
3655 22:56:00.929058 best DQS1 dly(2T, 0.5T) = (0, 11)
3656 22:56:00.931307 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3657 22:56:00.935191 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3658 22:56:00.938341 Pre-setting of DQS Precalculation
3659 22:56:00.944818 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3660 22:56:00.951195 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3661 22:56:00.958098 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3662 22:56:00.958743
3663 22:56:00.959131
3664 22:56:00.961048 [Calibration Summary] 2400 Mbps
3665 22:56:00.964523 CH 0, Rank 0
3666 22:56:00.964989 SW Impedance : PASS
3667 22:56:00.967973 DUTY Scan : NO K
3668 22:56:00.968495 ZQ Calibration : PASS
3669 22:56:00.971224 Jitter Meter : NO K
3670 22:56:00.974945 CBT Training : PASS
3671 22:56:00.975688 Write leveling : PASS
3672 22:56:00.977722 RX DQS gating : PASS
3673 22:56:00.980778 RX DQ/DQS(RDDQC) : PASS
3674 22:56:00.981268 TX DQ/DQS : PASS
3675 22:56:00.984239 RX DATLAT : PASS
3676 22:56:00.987725 RX DQ/DQS(Engine): PASS
3677 22:56:00.988298 TX OE : NO K
3678 22:56:00.991038 All Pass.
3679 22:56:00.991541
3680 22:56:00.991914 CH 0, Rank 1
3681 22:56:00.994363 SW Impedance : PASS
3682 22:56:00.994938 DUTY Scan : NO K
3683 22:56:00.997569 ZQ Calibration : PASS
3684 22:56:01.000925 Jitter Meter : NO K
3685 22:56:01.001396 CBT Training : PASS
3686 22:56:01.004459 Write leveling : PASS
3687 22:56:01.008194 RX DQS gating : PASS
3688 22:56:01.008765 RX DQ/DQS(RDDQC) : PASS
3689 22:56:01.011029 TX DQ/DQS : PASS
3690 22:56:01.014935 RX DATLAT : PASS
3691 22:56:01.015542 RX DQ/DQS(Engine): PASS
3692 22:56:01.017637 TX OE : NO K
3693 22:56:01.018108 All Pass.
3694 22:56:01.018477
3695 22:56:01.021190 CH 1, Rank 0
3696 22:56:01.021661 SW Impedance : PASS
3697 22:56:01.024951 DUTY Scan : NO K
3698 22:56:01.025541 ZQ Calibration : PASS
3699 22:56:01.027393 Jitter Meter : NO K
3700 22:56:01.030847 CBT Training : PASS
3701 22:56:01.031319 Write leveling : PASS
3702 22:56:01.034618 RX DQS gating : PASS
3703 22:56:01.037704 RX DQ/DQS(RDDQC) : PASS
3704 22:56:01.038274 TX DQ/DQS : PASS
3705 22:56:01.041375 RX DATLAT : PASS
3706 22:56:01.044430 RX DQ/DQS(Engine): PASS
3707 22:56:01.045018 TX OE : NO K
3708 22:56:01.047949 All Pass.
3709 22:56:01.048518
3710 22:56:01.048890 CH 1, Rank 1
3711 22:56:01.050671 SW Impedance : PASS
3712 22:56:01.051142 DUTY Scan : NO K
3713 22:56:01.054227 ZQ Calibration : PASS
3714 22:56:01.057693 Jitter Meter : NO K
3715 22:56:01.058165 CBT Training : PASS
3716 22:56:01.060852 Write leveling : PASS
3717 22:56:01.064297 RX DQS gating : PASS
3718 22:56:01.064767 RX DQ/DQS(RDDQC) : PASS
3719 22:56:01.067431 TX DQ/DQS : PASS
3720 22:56:01.067907 RX DATLAT : PASS
3721 22:56:01.071223 RX DQ/DQS(Engine): PASS
3722 22:56:01.074336 TX OE : NO K
3723 22:56:01.074901 All Pass.
3724 22:56:01.075275
3725 22:56:01.077313 DramC Write-DBI off
3726 22:56:01.077885 PER_BANK_REFRESH: Hybrid Mode
3727 22:56:01.080949 TX_TRACKING: ON
3728 22:56:01.090627 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3729 22:56:01.094500 [FAST_K] Save calibration result to emmc
3730 22:56:01.097995 dramc_set_vcore_voltage set vcore to 650000
3731 22:56:01.098554 Read voltage for 600, 5
3732 22:56:01.101038 Vio18 = 0
3733 22:56:01.101600 Vcore = 650000
3734 22:56:01.101973 Vdram = 0
3735 22:56:01.104078 Vddq = 0
3736 22:56:01.104549 Vmddr = 0
3737 22:56:01.107609 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3738 22:56:01.114285 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3739 22:56:01.117471 MEM_TYPE=3, freq_sel=19
3740 22:56:01.120862 sv_algorithm_assistance_LP4_1600
3741 22:56:01.123953 ============ PULL DRAM RESETB DOWN ============
3742 22:56:01.127278 ========== PULL DRAM RESETB DOWN end =========
3743 22:56:01.134545 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3744 22:56:01.137590 ===================================
3745 22:56:01.138153 LPDDR4 DRAM CONFIGURATION
3746 22:56:01.140544 ===================================
3747 22:56:01.144282 EX_ROW_EN[0] = 0x0
3748 22:56:01.144841 EX_ROW_EN[1] = 0x0
3749 22:56:01.147876 LP4Y_EN = 0x0
3750 22:56:01.148345 WORK_FSP = 0x0
3751 22:56:01.151000 WL = 0x2
3752 22:56:01.151603 RL = 0x2
3753 22:56:01.154612 BL = 0x2
3754 22:56:01.157240 RPST = 0x0
3755 22:56:01.157802 RD_PRE = 0x0
3756 22:56:01.160588 WR_PRE = 0x1
3757 22:56:01.161083 WR_PST = 0x0
3758 22:56:01.163988 DBI_WR = 0x0
3759 22:56:01.164457 DBI_RD = 0x0
3760 22:56:01.167173 OTF = 0x1
3761 22:56:01.171165 ===================================
3762 22:56:01.173845 ===================================
3763 22:56:01.174316 ANA top config
3764 22:56:01.177665 ===================================
3765 22:56:01.180972 DLL_ASYNC_EN = 0
3766 22:56:01.184472 ALL_SLAVE_EN = 1
3767 22:56:01.185048 NEW_RANK_MODE = 1
3768 22:56:01.187650 DLL_IDLE_MODE = 1
3769 22:56:01.190798 LP45_APHY_COMB_EN = 1
3770 22:56:01.194257 TX_ODT_DIS = 1
3771 22:56:01.194840 NEW_8X_MODE = 1
3772 22:56:01.197303 ===================================
3773 22:56:01.200997 ===================================
3774 22:56:01.204267 data_rate = 1200
3775 22:56:01.207545 CKR = 1
3776 22:56:01.210576 DQ_P2S_RATIO = 8
3777 22:56:01.214100 ===================================
3778 22:56:01.217358 CA_P2S_RATIO = 8
3779 22:56:01.221019 DQ_CA_OPEN = 0
3780 22:56:01.221490 DQ_SEMI_OPEN = 0
3781 22:56:01.223830 CA_SEMI_OPEN = 0
3782 22:56:01.227534 CA_FULL_RATE = 0
3783 22:56:01.230515 DQ_CKDIV4_EN = 1
3784 22:56:01.233870 CA_CKDIV4_EN = 1
3785 22:56:01.237230 CA_PREDIV_EN = 0
3786 22:56:01.237789 PH8_DLY = 0
3787 22:56:01.240526 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3788 22:56:01.244065 DQ_AAMCK_DIV = 4
3789 22:56:01.246923 CA_AAMCK_DIV = 4
3790 22:56:01.250663 CA_ADMCK_DIV = 4
3791 22:56:01.254286 DQ_TRACK_CA_EN = 0
3792 22:56:01.254842 CA_PICK = 600
3793 22:56:01.256749 CA_MCKIO = 600
3794 22:56:01.260462 MCKIO_SEMI = 0
3795 22:56:01.263777 PLL_FREQ = 2288
3796 22:56:01.266689 DQ_UI_PI_RATIO = 32
3797 22:56:01.270229 CA_UI_PI_RATIO = 0
3798 22:56:01.273707 ===================================
3799 22:56:01.277144 ===================================
3800 22:56:01.280178 memory_type:LPDDR4
3801 22:56:01.280640 GP_NUM : 10
3802 22:56:01.283497 SRAM_EN : 1
3803 22:56:01.283978 MD32_EN : 0
3804 22:56:01.286750 ===================================
3805 22:56:01.290134 [ANA_INIT] >>>>>>>>>>>>>>
3806 22:56:01.293479 <<<<<< [CONFIGURE PHASE]: ANA_TX
3807 22:56:01.296422 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3808 22:56:01.300690 ===================================
3809 22:56:01.303576 data_rate = 1200,PCW = 0X5800
3810 22:56:01.307092 ===================================
3811 22:56:01.310266 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3812 22:56:01.313540 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3813 22:56:01.320087 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3814 22:56:01.326743 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3815 22:56:01.330415 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3816 22:56:01.333308 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3817 22:56:01.333881 [ANA_INIT] flow start
3818 22:56:01.337223 [ANA_INIT] PLL >>>>>>>>
3819 22:56:01.340484 [ANA_INIT] PLL <<<<<<<<
3820 22:56:01.341046 [ANA_INIT] MIDPI >>>>>>>>
3821 22:56:01.343363 [ANA_INIT] MIDPI <<<<<<<<
3822 22:56:01.346904 [ANA_INIT] DLL >>>>>>>>
3823 22:56:01.347502 [ANA_INIT] flow end
3824 22:56:01.350551 ============ LP4 DIFF to SE enter ============
3825 22:56:01.356991 ============ LP4 DIFF to SE exit ============
3826 22:56:01.357556 [ANA_INIT] <<<<<<<<<<<<<
3827 22:56:01.360028 [Flow] Enable top DCM control >>>>>
3828 22:56:01.363272 [Flow] Enable top DCM control <<<<<
3829 22:56:01.366767 Enable DLL master slave shuffle
3830 22:56:01.373544 ==============================================================
3831 22:56:01.374123 Gating Mode config
3832 22:56:01.379954 ==============================================================
3833 22:56:01.383603 Config description:
3834 22:56:01.393588 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3835 22:56:01.399762 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3836 22:56:01.403420 SELPH_MODE 0: By rank 1: By Phase
3837 22:56:01.410074 ==============================================================
3838 22:56:01.413181 GAT_TRACK_EN = 1
3839 22:56:01.416403 RX_GATING_MODE = 2
3840 22:56:01.416962 RX_GATING_TRACK_MODE = 2
3841 22:56:01.420261 SELPH_MODE = 1
3842 22:56:01.423371 PICG_EARLY_EN = 1
3843 22:56:01.426491 VALID_LAT_VALUE = 1
3844 22:56:01.432873 ==============================================================
3845 22:56:01.436836 Enter into Gating configuration >>>>
3846 22:56:01.440019 Exit from Gating configuration <<<<
3847 22:56:01.443320 Enter into DVFS_PRE_config >>>>>
3848 22:56:01.453369 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3849 22:56:01.456967 Exit from DVFS_PRE_config <<<<<
3850 22:56:01.459647 Enter into PICG configuration >>>>
3851 22:56:01.463148 Exit from PICG configuration <<<<
3852 22:56:01.466427 [RX_INPUT] configuration >>>>>
3853 22:56:01.469454 [RX_INPUT] configuration <<<<<
3854 22:56:01.473221 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3855 22:56:01.479916 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3856 22:56:01.485912 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3857 22:56:01.492602 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3858 22:56:01.496166 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3859 22:56:01.503116 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3860 22:56:01.506128 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3861 22:56:01.512988 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3862 22:56:01.516166 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3863 22:56:01.519177 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3864 22:56:01.522579 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3865 22:56:01.529491 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3866 22:56:01.533099 ===================================
3867 22:56:01.533642 LPDDR4 DRAM CONFIGURATION
3868 22:56:01.536096 ===================================
3869 22:56:01.539697 EX_ROW_EN[0] = 0x0
3870 22:56:01.542620 EX_ROW_EN[1] = 0x0
3871 22:56:01.543242 LP4Y_EN = 0x0
3872 22:56:01.546248 WORK_FSP = 0x0
3873 22:56:01.546831 WL = 0x2
3874 22:56:01.549235 RL = 0x2
3875 22:56:01.549793 BL = 0x2
3876 22:56:01.552668 RPST = 0x0
3877 22:56:01.553135 RD_PRE = 0x0
3878 22:56:01.555635 WR_PRE = 0x1
3879 22:56:01.556102 WR_PST = 0x0
3880 22:56:01.559586 DBI_WR = 0x0
3881 22:56:01.560138 DBI_RD = 0x0
3882 22:56:01.562267 OTF = 0x1
3883 22:56:01.566033 ===================================
3884 22:56:01.569239 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3885 22:56:01.572858 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3886 22:56:01.579216 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3887 22:56:01.582801 ===================================
3888 22:56:01.583434 LPDDR4 DRAM CONFIGURATION
3889 22:56:01.585545 ===================================
3890 22:56:01.588977 EX_ROW_EN[0] = 0x10
3891 22:56:01.592416 EX_ROW_EN[1] = 0x0
3892 22:56:01.592995 LP4Y_EN = 0x0
3893 22:56:01.595598 WORK_FSP = 0x0
3894 22:56:01.596184 WL = 0x2
3895 22:56:01.599110 RL = 0x2
3896 22:56:01.599703 BL = 0x2
3897 22:56:01.602274 RPST = 0x0
3898 22:56:01.602746 RD_PRE = 0x0
3899 22:56:01.605299 WR_PRE = 0x1
3900 22:56:01.605769 WR_PST = 0x0
3901 22:56:01.609039 DBI_WR = 0x0
3902 22:56:01.609606 DBI_RD = 0x0
3903 22:56:01.612406 OTF = 0x1
3904 22:56:01.615679 ===================================
3905 22:56:01.622072 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3906 22:56:01.625681 nWR fixed to 30
3907 22:56:01.626159 [ModeRegInit_LP4] CH0 RK0
3908 22:56:01.629318 [ModeRegInit_LP4] CH0 RK1
3909 22:56:01.632236 [ModeRegInit_LP4] CH1 RK0
3910 22:56:01.635500 [ModeRegInit_LP4] CH1 RK1
3911 22:56:01.635977 match AC timing 17
3912 22:56:01.638686 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3913 22:56:01.642828 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3914 22:56:01.649527 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3915 22:56:01.652187 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3916 22:56:01.659756 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3917 22:56:01.660328 ==
3918 22:56:01.662212 Dram Type= 6, Freq= 0, CH_0, rank 0
3919 22:56:01.665627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3920 22:56:01.666092 ==
3921 22:56:01.672274 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3922 22:56:01.679225 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3923 22:56:01.682124 [CA 0] Center 35 (5~66) winsize 62
3924 22:56:01.685674 [CA 1] Center 35 (5~66) winsize 62
3925 22:56:01.689286 [CA 2] Center 34 (3~65) winsize 63
3926 22:56:01.692642 [CA 3] Center 33 (2~64) winsize 63
3927 22:56:01.695941 [CA 4] Center 33 (2~64) winsize 63
3928 22:56:01.696405 [CA 5] Center 32 (2~63) winsize 62
3929 22:56:01.698764
3930 22:56:01.702066 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3931 22:56:01.702529
3932 22:56:01.705594 [CATrainingPosCal] consider 1 rank data
3933 22:56:01.709168 u2DelayCellTimex100 = 270/100 ps
3934 22:56:01.712464 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3935 22:56:01.715289 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3936 22:56:01.718505 CA2 delay=34 (3~65),Diff = 2 PI (19 cell)
3937 22:56:01.721860 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
3938 22:56:01.725272 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3939 22:56:01.728688 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3940 22:56:01.729248
3941 22:56:01.732229 CA PerBit enable=1, Macro0, CA PI delay=32
3942 22:56:01.735555
3943 22:56:01.736177 [CBTSetCACLKResult] CA Dly = 32
3944 22:56:01.739098 CS Dly: 4 (0~35)
3945 22:56:01.739716 ==
3946 22:56:01.741890 Dram Type= 6, Freq= 0, CH_0, rank 1
3947 22:56:01.745520 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3948 22:56:01.746123 ==
3949 22:56:01.752076 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3950 22:56:01.758693 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3951 22:56:01.762063 [CA 0] Center 35 (5~66) winsize 62
3952 22:56:01.765249 [CA 1] Center 35 (5~66) winsize 62
3953 22:56:01.768198 [CA 2] Center 34 (3~65) winsize 63
3954 22:56:01.772109 [CA 3] Center 33 (3~64) winsize 62
3955 22:56:01.775656 [CA 4] Center 33 (2~64) winsize 63
3956 22:56:01.778832 [CA 5] Center 32 (1~63) winsize 63
3957 22:56:01.779425
3958 22:56:01.782492 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3959 22:56:01.783140
3960 22:56:01.785139 [CATrainingPosCal] consider 2 rank data
3961 22:56:01.788302 u2DelayCellTimex100 = 270/100 ps
3962 22:56:01.792222 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3963 22:56:01.794919 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3964 22:56:01.798369 CA2 delay=34 (3~65),Diff = 2 PI (19 cell)
3965 22:56:01.802392 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
3966 22:56:01.805223 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3967 22:56:01.808883 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3968 22:56:01.809444
3969 22:56:01.815208 CA PerBit enable=1, Macro0, CA PI delay=32
3970 22:56:01.815827
3971 22:56:01.816202 [CBTSetCACLKResult] CA Dly = 32
3972 22:56:01.818210 CS Dly: 4 (0~36)
3973 22:56:01.818747
3974 22:56:01.821422 ----->DramcWriteLeveling(PI) begin...
3975 22:56:01.821909 ==
3976 22:56:01.824950 Dram Type= 6, Freq= 0, CH_0, rank 0
3977 22:56:01.828455 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3978 22:56:01.829038 ==
3979 22:56:01.831920 Write leveling (Byte 0): 34 => 34
3980 22:56:01.835174 Write leveling (Byte 1): 31 => 31
3981 22:56:01.838883 DramcWriteLeveling(PI) end<-----
3982 22:56:01.839502
3983 22:56:01.839884 ==
3984 22:56:01.842357 Dram Type= 6, Freq= 0, CH_0, rank 0
3985 22:56:01.845285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3986 22:56:01.848706 ==
3987 22:56:01.849272 [Gating] SW mode calibration
3988 22:56:01.858879 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3989 22:56:01.861785 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3990 22:56:01.865174 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3991 22:56:01.871675 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3992 22:56:01.875780 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3993 22:56:01.878417 0 9 12 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 1)
3994 22:56:01.884933 0 9 16 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
3995 22:56:01.888489 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3996 22:56:01.891867 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3997 22:56:01.898436 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3998 22:56:01.901752 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3999 22:56:01.904872 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4000 22:56:01.912044 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4001 22:56:01.914850 0 10 12 | B1->B0 | 2323 3939 | 0 0 | (0 0) (0 0)
4002 22:56:01.918433 0 10 16 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
4003 22:56:01.924811 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4004 22:56:01.928304 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4005 22:56:01.932000 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4006 22:56:01.934816 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4007 22:56:01.941586 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4008 22:56:01.944469 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4009 22:56:01.947995 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4010 22:56:01.955378 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4011 22:56:01.958288 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4012 22:56:01.962131 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4013 22:56:01.968374 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4014 22:56:01.971525 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4015 22:56:01.975746 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4016 22:56:01.982108 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4017 22:56:01.984891 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4018 22:56:01.988256 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4019 22:56:01.994902 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4020 22:56:01.998560 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4021 22:56:02.001659 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4022 22:56:02.008157 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4023 22:56:02.011281 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4024 22:56:02.014909 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4025 22:56:02.021431 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4026 22:56:02.021997 Total UI for P1: 0, mck2ui 16
4027 22:56:02.027638 best dqsien dly found for B0: ( 0, 13, 10)
4028 22:56:02.031396 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4029 22:56:02.034535 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4030 22:56:02.038116 Total UI for P1: 0, mck2ui 16
4031 22:56:02.041363 best dqsien dly found for B1: ( 0, 13, 14)
4032 22:56:02.044539 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4033 22:56:02.047836 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4034 22:56:02.048304
4035 22:56:02.051221 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4036 22:56:02.057992 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4037 22:56:02.058556 [Gating] SW calibration Done
4038 22:56:02.061897 ==
4039 22:56:02.062455 Dram Type= 6, Freq= 0, CH_0, rank 0
4040 22:56:02.067664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4041 22:56:02.068131 ==
4042 22:56:02.068503 RX Vref Scan: 0
4043 22:56:02.068916
4044 22:56:02.071114 RX Vref 0 -> 0, step: 1
4045 22:56:02.071607
4046 22:56:02.074709 RX Delay -230 -> 252, step: 16
4047 22:56:02.077535 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4048 22:56:02.080975 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4049 22:56:02.088212 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4050 22:56:02.091368 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4051 22:56:02.094756 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4052 22:56:02.097742 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4053 22:56:02.101532 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4054 22:56:02.107619 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4055 22:56:02.110929 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4056 22:56:02.114652 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4057 22:56:02.117909 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4058 22:56:02.124753 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4059 22:56:02.127757 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4060 22:56:02.130871 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4061 22:56:02.134428 iDelay=218, Bit 14, Center 65 (-86 ~ 217) 304
4062 22:56:02.141022 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4063 22:56:02.141536 ==
4064 22:56:02.144389 Dram Type= 6, Freq= 0, CH_0, rank 0
4065 22:56:02.147486 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4066 22:56:02.148058 ==
4067 22:56:02.148434 DQS Delay:
4068 22:56:02.150884 DQS0 = 0, DQS1 = 0
4069 22:56:02.151495 DQM Delay:
4070 22:56:02.154108 DQM0 = 53, DQM1 = 46
4071 22:56:02.154573 DQ Delay:
4072 22:56:02.157777 DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =41
4073 22:56:02.160751 DQ4 =57, DQ5 =41, DQ6 =65, DQ7 =65
4074 22:56:02.164048 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =41
4075 22:56:02.167569 DQ12 =49, DQ13 =49, DQ14 =65, DQ15 =57
4076 22:56:02.168035
4077 22:56:02.168402
4078 22:56:02.168761 ==
4079 22:56:02.170653 Dram Type= 6, Freq= 0, CH_0, rank 0
4080 22:56:02.174307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4081 22:56:02.174779 ==
4082 22:56:02.175144
4083 22:56:02.175541
4084 22:56:02.177900 TX Vref Scan disable
4085 22:56:02.180959 == TX Byte 0 ==
4086 22:56:02.184082 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4087 22:56:02.187433 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4088 22:56:02.191158 == TX Byte 1 ==
4089 22:56:02.194040 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4090 22:56:02.197646 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4091 22:56:02.198214 ==
4092 22:56:02.200703 Dram Type= 6, Freq= 0, CH_0, rank 0
4093 22:56:02.207766 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4094 22:56:02.208330 ==
4095 22:56:02.208699
4096 22:56:02.209038
4097 22:56:02.209359 TX Vref Scan disable
4098 22:56:02.211599 == TX Byte 0 ==
4099 22:56:02.215015 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4100 22:56:02.221762 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4101 22:56:02.222445 == TX Byte 1 ==
4102 22:56:02.224801 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4103 22:56:02.231632 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4104 22:56:02.232093
4105 22:56:02.232511 [DATLAT]
4106 22:56:02.232860 Freq=600, CH0 RK0
4107 22:56:02.233189
4108 22:56:02.234717 DATLAT Default: 0x9
4109 22:56:02.235195 0, 0xFFFF, sum = 0
4110 22:56:02.238260 1, 0xFFFF, sum = 0
4111 22:56:02.238740 2, 0xFFFF, sum = 0
4112 22:56:02.241530 3, 0xFFFF, sum = 0
4113 22:56:02.242009 4, 0xFFFF, sum = 0
4114 22:56:02.244664 5, 0xFFFF, sum = 0
4115 22:56:02.248033 6, 0xFFFF, sum = 0
4116 22:56:02.248513 7, 0xFFFF, sum = 0
4117 22:56:02.248892 8, 0x0, sum = 1
4118 22:56:02.251725 9, 0x0, sum = 2
4119 22:56:02.252301 10, 0x0, sum = 3
4120 22:56:02.254617 11, 0x0, sum = 4
4121 22:56:02.255112 best_step = 9
4122 22:56:02.255540
4123 22:56:02.255897 ==
4124 22:56:02.258546 Dram Type= 6, Freq= 0, CH_0, rank 0
4125 22:56:02.264640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4126 22:56:02.265120 ==
4127 22:56:02.265615 RX Vref Scan: 1
4128 22:56:02.266257
4129 22:56:02.268113 RX Vref 0 -> 0, step: 1
4130 22:56:02.268580
4131 22:56:02.271294 RX Delay -163 -> 252, step: 8
4132 22:56:02.271834
4133 22:56:02.275077 Set Vref, RX VrefLevel [Byte0]: 56
4134 22:56:02.278301 [Byte1]: 48
4135 22:56:02.278874
4136 22:56:02.281519 Final RX Vref Byte 0 = 56 to rank0
4137 22:56:02.285017 Final RX Vref Byte 1 = 48 to rank0
4138 22:56:02.287847 Final RX Vref Byte 0 = 56 to rank1
4139 22:56:02.291253 Final RX Vref Byte 1 = 48 to rank1==
4140 22:56:02.294575 Dram Type= 6, Freq= 0, CH_0, rank 0
4141 22:56:02.298207 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4142 22:56:02.298729 ==
4143 22:56:02.301321 DQS Delay:
4144 22:56:02.301829 DQS0 = 0, DQS1 = 0
4145 22:56:02.302295 DQM Delay:
4146 22:56:02.304387 DQM0 = 53, DQM1 = 46
4147 22:56:02.304825 DQ Delay:
4148 22:56:02.307975 DQ0 =52, DQ1 =56, DQ2 =48, DQ3 =52
4149 22:56:02.311622 DQ4 =52, DQ5 =44, DQ6 =60, DQ7 =60
4150 22:56:02.314795 DQ8 =32, DQ9 =36, DQ10 =48, DQ11 =40
4151 22:56:02.317673 DQ12 =56, DQ13 =48, DQ14 =56, DQ15 =56
4152 22:56:02.318097
4153 22:56:02.318436
4154 22:56:02.328309 [DQSOSCAuto] RK0, (LSB)MR18= 0x6f62, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 389 ps
4155 22:56:02.328742 CH0 RK0: MR19=808, MR18=6F62
4156 22:56:02.334379 CH0_RK0: MR19=0x808, MR18=0x6F62, DQSOSC=389, MR23=63, INC=173, DEC=115
4157 22:56:02.334861
4158 22:56:02.337710 ----->DramcWriteLeveling(PI) begin...
4159 22:56:02.341114 ==
4160 22:56:02.344530 Dram Type= 6, Freq= 0, CH_0, rank 1
4161 22:56:02.347641 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4162 22:56:02.348173 ==
4163 22:56:02.350998 Write leveling (Byte 0): 33 => 33
4164 22:56:02.354539 Write leveling (Byte 1): 32 => 32
4165 22:56:02.357926 DramcWriteLeveling(PI) end<-----
4166 22:56:02.358349
4167 22:56:02.358683 ==
4168 22:56:02.361127 Dram Type= 6, Freq= 0, CH_0, rank 1
4169 22:56:02.364390 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4170 22:56:02.364812 ==
4171 22:56:02.367719 [Gating] SW mode calibration
4172 22:56:02.374507 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4173 22:56:02.377789 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4174 22:56:02.384302 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4175 22:56:02.387998 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4176 22:56:02.391048 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4177 22:56:02.397833 0 9 12 | B1->B0 | 3434 3333 | 0 0 | (1 1) (0 1)
4178 22:56:02.400728 0 9 16 | B1->B0 | 2a2a 2525 | 1 0 | (1 0) (0 0)
4179 22:56:02.404062 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4180 22:56:02.410894 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4181 22:56:02.413821 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4182 22:56:02.417626 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4183 22:56:02.424016 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4184 22:56:02.427496 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4185 22:56:02.430601 0 10 12 | B1->B0 | 2a2a 2626 | 1 0 | (0 0) (0 0)
4186 22:56:02.437657 0 10 16 | B1->B0 | 4343 4444 | 0 0 | (0 0) (0 0)
4187 22:56:02.440442 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4188 22:56:02.443975 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4189 22:56:02.450373 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4190 22:56:02.454107 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4191 22:56:02.457183 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4192 22:56:02.463921 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4193 22:56:02.467164 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4194 22:56:02.470406 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4195 22:56:02.477194 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4196 22:56:02.480569 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4197 22:56:02.484135 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4198 22:56:02.490335 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4199 22:56:02.494060 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4200 22:56:02.497438 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4201 22:56:02.504000 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4202 22:56:02.507031 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4203 22:56:02.510195 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4204 22:56:02.517250 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4205 22:56:02.520413 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4206 22:56:02.524107 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4207 22:56:02.527369 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4208 22:56:02.534052 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4209 22:56:02.537566 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4210 22:56:02.540522 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4211 22:56:02.544016 Total UI for P1: 0, mck2ui 16
4212 22:56:02.546977 best dqsien dly found for B1: ( 0, 13, 14)
4213 22:56:02.553615 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4214 22:56:02.557286 Total UI for P1: 0, mck2ui 16
4215 22:56:02.560681 best dqsien dly found for B0: ( 0, 13, 16)
4216 22:56:02.563596 best DQS0 dly(MCK, UI, PI) = (0, 13, 16)
4217 22:56:02.566731 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4218 22:56:02.567566
4219 22:56:02.570214 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 16)
4220 22:56:02.573350 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4221 22:56:02.576496 [Gating] SW calibration Done
4222 22:56:02.576961 ==
4223 22:56:02.579880 Dram Type= 6, Freq= 0, CH_0, rank 1
4224 22:56:02.583493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4225 22:56:02.584051 ==
4226 22:56:02.586467 RX Vref Scan: 0
4227 22:56:02.586929
4228 22:56:02.590329 RX Vref 0 -> 0, step: 1
4229 22:56:02.590797
4230 22:56:02.591162 RX Delay -230 -> 252, step: 16
4231 22:56:02.596807 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4232 22:56:02.600806 iDelay=218, Bit 1, Center 57 (-86 ~ 201) 288
4233 22:56:02.602986 iDelay=218, Bit 2, Center 57 (-86 ~ 201) 288
4234 22:56:02.606912 iDelay=218, Bit 3, Center 57 (-86 ~ 201) 288
4235 22:56:02.609993 iDelay=218, Bit 4, Center 65 (-86 ~ 217) 304
4236 22:56:02.617010 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4237 22:56:02.619958 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4238 22:56:02.623168 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4239 22:56:02.626857 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4240 22:56:02.633438 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4241 22:56:02.636593 iDelay=218, Bit 10, Center 57 (-86 ~ 201) 288
4242 22:56:02.640051 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4243 22:56:02.643573 iDelay=218, Bit 12, Center 57 (-86 ~ 201) 288
4244 22:56:02.646407 iDelay=218, Bit 13, Center 57 (-86 ~ 201) 288
4245 22:56:02.653741 iDelay=218, Bit 14, Center 57 (-86 ~ 201) 288
4246 22:56:02.656637 iDelay=218, Bit 15, Center 57 (-86 ~ 201) 288
4247 22:56:02.657100 ==
4248 22:56:02.659942 Dram Type= 6, Freq= 0, CH_0, rank 1
4249 22:56:02.663102 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4250 22:56:02.663755 ==
4251 22:56:02.666469 DQS Delay:
4252 22:56:02.667124 DQS0 = 0, DQS1 = 0
4253 22:56:02.667596 DQM Delay:
4254 22:56:02.669439 DQM0 = 58, DQM1 = 48
4255 22:56:02.670056 DQ Delay:
4256 22:56:02.673050 DQ0 =57, DQ1 =57, DQ2 =57, DQ3 =57
4257 22:56:02.676660 DQ4 =65, DQ5 =41, DQ6 =65, DQ7 =65
4258 22:56:02.679583 DQ8 =33, DQ9 =33, DQ10 =57, DQ11 =33
4259 22:56:02.683128 DQ12 =57, DQ13 =57, DQ14 =57, DQ15 =57
4260 22:56:02.683650
4261 22:56:02.684066
4262 22:56:02.684404 ==
4263 22:56:02.686104 Dram Type= 6, Freq= 0, CH_0, rank 1
4264 22:56:02.693306 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4265 22:56:02.693866 ==
4266 22:56:02.694301
4267 22:56:02.694644
4268 22:56:02.694966 TX Vref Scan disable
4269 22:56:02.696443 == TX Byte 0 ==
4270 22:56:02.699861 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4271 22:56:02.706779 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4272 22:56:02.707388 == TX Byte 1 ==
4273 22:56:02.710283 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4274 22:56:02.717036 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4275 22:56:02.717658 ==
4276 22:56:02.719821 Dram Type= 6, Freq= 0, CH_0, rank 1
4277 22:56:02.722956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4278 22:56:02.723590 ==
4279 22:56:02.723972
4280 22:56:02.724308
4281 22:56:02.726233 TX Vref Scan disable
4282 22:56:02.730331 == TX Byte 0 ==
4283 22:56:02.733351 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4284 22:56:02.736327 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4285 22:56:02.740093 == TX Byte 1 ==
4286 22:56:02.743198 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4287 22:56:02.746583 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4288 22:56:02.747051
4289 22:56:02.747464 [DATLAT]
4290 22:56:02.749674 Freq=600, CH0 RK1
4291 22:56:02.750137
4292 22:56:02.750497 DATLAT Default: 0x9
4293 22:56:02.752938 0, 0xFFFF, sum = 0
4294 22:56:02.756178 1, 0xFFFF, sum = 0
4295 22:56:02.756745 2, 0xFFFF, sum = 0
4296 22:56:02.759538 3, 0xFFFF, sum = 0
4297 22:56:02.760102 4, 0xFFFF, sum = 0
4298 22:56:02.762943 5, 0xFFFF, sum = 0
4299 22:56:02.763567 6, 0xFFFF, sum = 0
4300 22:56:02.766474 7, 0xFFFF, sum = 0
4301 22:56:02.767005 8, 0x0, sum = 1
4302 22:56:02.767670 9, 0x0, sum = 2
4303 22:56:02.769482 10, 0x0, sum = 3
4304 22:56:02.769956 11, 0x0, sum = 4
4305 22:56:02.772763 best_step = 9
4306 22:56:02.773223
4307 22:56:02.773584 ==
4308 22:56:02.776197 Dram Type= 6, Freq= 0, CH_0, rank 1
4309 22:56:02.779191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4310 22:56:02.779643 ==
4311 22:56:02.782710 RX Vref Scan: 0
4312 22:56:02.783171
4313 22:56:02.783565 RX Vref 0 -> 0, step: 1
4314 22:56:02.783873
4315 22:56:02.785947 RX Delay -163 -> 252, step: 8
4316 22:56:02.793574 iDelay=197, Bit 0, Center 52 (-91 ~ 196) 288
4317 22:56:02.796540 iDelay=197, Bit 1, Center 56 (-83 ~ 196) 280
4318 22:56:02.799704 iDelay=197, Bit 2, Center 52 (-91 ~ 196) 288
4319 22:56:02.803714 iDelay=197, Bit 3, Center 52 (-91 ~ 196) 288
4320 22:56:02.807083 iDelay=197, Bit 4, Center 56 (-83 ~ 196) 280
4321 22:56:02.813596 iDelay=197, Bit 5, Center 44 (-99 ~ 188) 288
4322 22:56:02.816474 iDelay=197, Bit 6, Center 60 (-75 ~ 196) 272
4323 22:56:02.819515 iDelay=197, Bit 7, Center 60 (-75 ~ 196) 272
4324 22:56:02.822893 iDelay=197, Bit 8, Center 40 (-99 ~ 180) 280
4325 22:56:02.826716 iDelay=197, Bit 9, Center 36 (-107 ~ 180) 288
4326 22:56:02.833099 iDelay=197, Bit 10, Center 48 (-91 ~ 188) 280
4327 22:56:02.836755 iDelay=197, Bit 11, Center 40 (-99 ~ 180) 280
4328 22:56:02.840496 iDelay=197, Bit 12, Center 48 (-91 ~ 188) 280
4329 22:56:02.843203 iDelay=197, Bit 13, Center 52 (-91 ~ 196) 288
4330 22:56:02.850081 iDelay=197, Bit 14, Center 56 (-83 ~ 196) 280
4331 22:56:02.853366 iDelay=197, Bit 15, Center 52 (-91 ~ 196) 288
4332 22:56:02.853916 ==
4333 22:56:02.857161 Dram Type= 6, Freq= 0, CH_0, rank 1
4334 22:56:02.859999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4335 22:56:02.860456 ==
4336 22:56:02.860811 DQS Delay:
4337 22:56:02.863068 DQS0 = 0, DQS1 = 0
4338 22:56:02.863609 DQM Delay:
4339 22:56:02.866503 DQM0 = 54, DQM1 = 46
4340 22:56:02.866955 DQ Delay:
4341 22:56:02.870201 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4342 22:56:02.873188 DQ4 =56, DQ5 =44, DQ6 =60, DQ7 =60
4343 22:56:02.876726 DQ8 =40, DQ9 =36, DQ10 =48, DQ11 =40
4344 22:56:02.879753 DQ12 =48, DQ13 =52, DQ14 =56, DQ15 =52
4345 22:56:02.880159
4346 22:56:02.880476
4347 22:56:02.889893 [DQSOSCAuto] RK1, (LSB)MR18= 0x6626, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 390 ps
4348 22:56:02.890310 CH0 RK1: MR19=808, MR18=6626
4349 22:56:02.896411 CH0_RK1: MR19=0x808, MR18=0x6626, DQSOSC=390, MR23=63, INC=172, DEC=114
4350 22:56:02.899789 [RxdqsGatingPostProcess] freq 600
4351 22:56:02.906601 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4352 22:56:02.909921 Pre-setting of DQS Precalculation
4353 22:56:02.913208 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4354 22:56:02.913688 ==
4355 22:56:02.916297 Dram Type= 6, Freq= 0, CH_1, rank 0
4356 22:56:02.920051 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4357 22:56:02.922902 ==
4358 22:56:02.926685 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4359 22:56:02.933093 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4360 22:56:02.936274 [CA 0] Center 35 (5~66) winsize 62
4361 22:56:02.939642 [CA 1] Center 36 (5~67) winsize 63
4362 22:56:02.943545 [CA 2] Center 34 (4~65) winsize 62
4363 22:56:02.946451 [CA 3] Center 34 (4~65) winsize 62
4364 22:56:02.950084 [CA 4] Center 34 (4~65) winsize 62
4365 22:56:02.953235 [CA 5] Center 34 (4~65) winsize 62
4366 22:56:02.953788
4367 22:56:02.956564 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4368 22:56:02.957119
4369 22:56:02.959737 [CATrainingPosCal] consider 1 rank data
4370 22:56:02.963391 u2DelayCellTimex100 = 270/100 ps
4371 22:56:02.966214 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4372 22:56:02.969654 CA1 delay=36 (5~67),Diff = 2 PI (19 cell)
4373 22:56:02.973182 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4374 22:56:02.979490 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4375 22:56:02.982946 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4376 22:56:02.986041 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4377 22:56:02.986636
4378 22:56:02.989530 CA PerBit enable=1, Macro0, CA PI delay=34
4379 22:56:02.989990
4380 22:56:02.992962 [CBTSetCACLKResult] CA Dly = 34
4381 22:56:02.993421 CS Dly: 5 (0~36)
4382 22:56:02.993783 ==
4383 22:56:02.995999 Dram Type= 6, Freq= 0, CH_1, rank 1
4384 22:56:03.002675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4385 22:56:03.003250 ==
4386 22:56:03.005751 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4387 22:56:03.012554 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4388 22:56:03.015732 [CA 0] Center 36 (5~67) winsize 63
4389 22:56:03.018957 [CA 1] Center 36 (5~67) winsize 63
4390 22:56:03.022448 [CA 2] Center 35 (4~66) winsize 63
4391 22:56:03.025696 [CA 3] Center 34 (3~65) winsize 63
4392 22:56:03.029380 [CA 4] Center 34 (4~65) winsize 62
4393 22:56:03.032105 [CA 5] Center 34 (3~65) winsize 63
4394 22:56:03.032544
4395 22:56:03.036050 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4396 22:56:03.036596
4397 22:56:03.039142 [CATrainingPosCal] consider 2 rank data
4398 22:56:03.042191 u2DelayCellTimex100 = 270/100 ps
4399 22:56:03.045739 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4400 22:56:03.048955 CA1 delay=36 (5~67),Diff = 2 PI (19 cell)
4401 22:56:03.056176 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4402 22:56:03.059119 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4403 22:56:03.062375 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4404 22:56:03.065571 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4405 22:56:03.066006
4406 22:56:03.069419 CA PerBit enable=1, Macro0, CA PI delay=34
4407 22:56:03.069876
4408 22:56:03.072580 [CBTSetCACLKResult] CA Dly = 34
4409 22:56:03.073100 CS Dly: 5 (0~37)
4410 22:56:03.073440
4411 22:56:03.075265 ----->DramcWriteLeveling(PI) begin...
4412 22:56:03.079393 ==
4413 22:56:03.082124 Dram Type= 6, Freq= 0, CH_1, rank 0
4414 22:56:03.085637 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4415 22:56:03.086249 ==
4416 22:56:03.088570 Write leveling (Byte 0): 31 => 31
4417 22:56:03.092112 Write leveling (Byte 1): 32 => 32
4418 22:56:03.095633 DramcWriteLeveling(PI) end<-----
4419 22:56:03.096212
4420 22:56:03.096587 ==
4421 22:56:03.098908 Dram Type= 6, Freq= 0, CH_1, rank 0
4422 22:56:03.101879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4423 22:56:03.102463 ==
4424 22:56:03.105171 [Gating] SW mode calibration
4425 22:56:03.112008 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4426 22:56:03.118730 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4427 22:56:03.122189 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4428 22:56:03.125079 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4429 22:56:03.131966 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4430 22:56:03.135412 0 9 12 | B1->B0 | 2f2f 2f2f | 1 0 | (1 0) (0 0)
4431 22:56:03.138721 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4432 22:56:03.142079 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4433 22:56:03.148894 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4434 22:56:03.152174 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4435 22:56:03.155604 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4436 22:56:03.162036 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4437 22:56:03.165392 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4438 22:56:03.168277 0 10 12 | B1->B0 | 3535 3b3b | 0 0 | (0 0) (0 0)
4439 22:56:03.175271 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4440 22:56:03.179099 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4441 22:56:03.182139 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4442 22:56:03.188620 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4443 22:56:03.191667 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4444 22:56:03.195223 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4445 22:56:03.201676 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4446 22:56:03.204988 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4447 22:56:03.208697 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4448 22:56:03.214852 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4449 22:56:03.218130 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4450 22:56:03.221399 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4451 22:56:03.227966 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4452 22:56:03.231399 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4453 22:56:03.234946 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4454 22:56:03.241317 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4455 22:56:03.244870 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4456 22:56:03.247872 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4457 22:56:03.254783 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4458 22:56:03.257656 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4459 22:56:03.261170 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4460 22:56:03.268019 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4461 22:56:03.271417 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4462 22:56:03.274577 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4463 22:56:03.278395 Total UI for P1: 0, mck2ui 16
4464 22:56:03.281224 best dqsien dly found for B0: ( 0, 13, 10)
4465 22:56:03.287893 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4466 22:56:03.288464 Total UI for P1: 0, mck2ui 16
4467 22:56:03.291534 best dqsien dly found for B1: ( 0, 13, 12)
4468 22:56:03.297813 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4469 22:56:03.301394 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4470 22:56:03.302168
4471 22:56:03.304554 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4472 22:56:03.307809 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4473 22:56:03.311585 [Gating] SW calibration Done
4474 22:56:03.312320 ==
4475 22:56:03.314275 Dram Type= 6, Freq= 0, CH_1, rank 0
4476 22:56:03.317469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4477 22:56:03.317936 ==
4478 22:56:03.320902 RX Vref Scan: 0
4479 22:56:03.321412
4480 22:56:03.321819 RX Vref 0 -> 0, step: 1
4481 22:56:03.322168
4482 22:56:03.324055 RX Delay -230 -> 252, step: 16
4483 22:56:03.327451 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4484 22:56:03.334398 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4485 22:56:03.337657 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4486 22:56:03.341151 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4487 22:56:03.344520 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4488 22:56:03.351268 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4489 22:56:03.354298 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4490 22:56:03.357810 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4491 22:56:03.361253 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4492 22:56:03.364265 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4493 22:56:03.370935 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4494 22:56:03.374827 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4495 22:56:03.377876 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4496 22:56:03.380844 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4497 22:56:03.387887 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4498 22:56:03.391140 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4499 22:56:03.391739 ==
4500 22:56:03.394158 Dram Type= 6, Freq= 0, CH_1, rank 0
4501 22:56:03.397613 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4502 22:56:03.398177 ==
4503 22:56:03.401098 DQS Delay:
4504 22:56:03.401659 DQS0 = 0, DQS1 = 0
4505 22:56:03.402030 DQM Delay:
4506 22:56:03.404351 DQM0 = 49, DQM1 = 46
4507 22:56:03.404858 DQ Delay:
4508 22:56:03.407790 DQ0 =49, DQ1 =41, DQ2 =41, DQ3 =49
4509 22:56:03.411186 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4510 22:56:03.414368 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4511 22:56:03.417540 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4512 22:56:03.418093
4513 22:56:03.418463
4514 22:56:03.418806 ==
4515 22:56:03.420545 Dram Type= 6, Freq= 0, CH_1, rank 0
4516 22:56:03.427461 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4517 22:56:03.428023 ==
4518 22:56:03.428397
4519 22:56:03.428741
4520 22:56:03.429067 TX Vref Scan disable
4521 22:56:03.431078 == TX Byte 0 ==
4522 22:56:03.434472 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4523 22:56:03.441122 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4524 22:56:03.441695 == TX Byte 1 ==
4525 22:56:03.444697 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4526 22:56:03.447972 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4527 22:56:03.451044 ==
4528 22:56:03.454382 Dram Type= 6, Freq= 0, CH_1, rank 0
4529 22:56:03.457712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4530 22:56:03.458183 ==
4531 22:56:03.458553
4532 22:56:03.458892
4533 22:56:03.461326 TX Vref Scan disable
4534 22:56:03.461886 == TX Byte 0 ==
4535 22:56:03.467310 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4536 22:56:03.470718 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4537 22:56:03.471248 == TX Byte 1 ==
4538 22:56:03.478201 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4539 22:56:03.481198 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4540 22:56:03.481766
4541 22:56:03.482133 [DATLAT]
4542 22:56:03.484639 Freq=600, CH1 RK0
4543 22:56:03.485100
4544 22:56:03.485462 DATLAT Default: 0x9
4545 22:56:03.487449 0, 0xFFFF, sum = 0
4546 22:56:03.487954 1, 0xFFFF, sum = 0
4547 22:56:03.491417 2, 0xFFFF, sum = 0
4548 22:56:03.491985 3, 0xFFFF, sum = 0
4549 22:56:03.494389 4, 0xFFFF, sum = 0
4550 22:56:03.494951 5, 0xFFFF, sum = 0
4551 22:56:03.498009 6, 0xFFFF, sum = 0
4552 22:56:03.498575 7, 0xFFFF, sum = 0
4553 22:56:03.501163 8, 0x0, sum = 1
4554 22:56:03.501737 9, 0x0, sum = 2
4555 22:56:03.504645 10, 0x0, sum = 3
4556 22:56:03.505166 11, 0x0, sum = 4
4557 22:56:03.507836 best_step = 9
4558 22:56:03.508296
4559 22:56:03.508660 ==
4560 22:56:03.510702 Dram Type= 6, Freq= 0, CH_1, rank 0
4561 22:56:03.514272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4562 22:56:03.514737 ==
4563 22:56:03.517655 RX Vref Scan: 1
4564 22:56:03.518137
4565 22:56:03.518500 RX Vref 0 -> 0, step: 1
4566 22:56:03.518844
4567 22:56:03.520752 RX Delay -163 -> 252, step: 8
4568 22:56:03.521214
4569 22:56:03.524230 Set Vref, RX VrefLevel [Byte0]: 54
4570 22:56:03.527869 [Byte1]: 47
4571 22:56:03.531448
4572 22:56:03.531973 Final RX Vref Byte 0 = 54 to rank0
4573 22:56:03.534823 Final RX Vref Byte 1 = 47 to rank0
4574 22:56:03.537995 Final RX Vref Byte 0 = 54 to rank1
4575 22:56:03.541157 Final RX Vref Byte 1 = 47 to rank1==
4576 22:56:03.544650 Dram Type= 6, Freq= 0, CH_1, rank 0
4577 22:56:03.547663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4578 22:56:03.551365 ==
4579 22:56:03.551828 DQS Delay:
4580 22:56:03.552194 DQS0 = 0, DQS1 = 0
4581 22:56:03.555125 DQM Delay:
4582 22:56:03.555728 DQM0 = 48, DQM1 = 44
4583 22:56:03.558043 DQ Delay:
4584 22:56:03.561404 DQ0 =52, DQ1 =40, DQ2 =36, DQ3 =44
4585 22:56:03.561966 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4586 22:56:03.564887 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =36
4587 22:56:03.568039 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =52
4588 22:56:03.568503
4589 22:56:03.571322
4590 22:56:03.578079 [DQSOSCAuto] RK0, (LSB)MR18= 0x4b71, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps
4591 22:56:03.581736 CH1 RK0: MR19=808, MR18=4B71
4592 22:56:03.588143 CH1_RK0: MR19=0x808, MR18=0x4B71, DQSOSC=388, MR23=63, INC=174, DEC=116
4593 22:56:03.588709
4594 22:56:03.591302 ----->DramcWriteLeveling(PI) begin...
4595 22:56:03.591804 ==
4596 22:56:03.595069 Dram Type= 6, Freq= 0, CH_1, rank 1
4597 22:56:03.597983 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4598 22:56:03.598446 ==
4599 22:56:03.602098 Write leveling (Byte 0): 31 => 31
4600 22:56:03.604858 Write leveling (Byte 1): 31 => 31
4601 22:56:03.608297 DramcWriteLeveling(PI) end<-----
4602 22:56:03.608837
4603 22:56:03.609199 ==
4604 22:56:03.611369 Dram Type= 6, Freq= 0, CH_1, rank 1
4605 22:56:03.614460 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4606 22:56:03.614926 ==
4607 22:56:03.618207 [Gating] SW mode calibration
4608 22:56:03.624870 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4609 22:56:03.631290 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4610 22:56:03.635066 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4611 22:56:03.638049 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4612 22:56:03.644805 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4613 22:56:03.647850 0 9 12 | B1->B0 | 2e2e 2f2f | 0 0 | (0 1) (1 1)
4614 22:56:03.651405 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4615 22:56:03.657915 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4616 22:56:03.660955 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4617 22:56:03.664598 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4618 22:56:03.670916 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4619 22:56:03.674561 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4620 22:56:03.678328 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4621 22:56:03.684628 0 10 12 | B1->B0 | 3b3b 3837 | 1 1 | (0 0) (0 0)
4622 22:56:03.687642 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4623 22:56:03.691679 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4624 22:56:03.698029 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4625 22:56:03.701868 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4626 22:56:03.704698 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4627 22:56:03.711296 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4628 22:56:03.714656 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4629 22:56:03.717877 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4630 22:56:03.721071 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4631 22:56:03.727914 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4632 22:56:03.730737 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4633 22:56:03.735020 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4634 22:56:03.741166 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4635 22:56:03.744543 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4636 22:56:03.747358 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4637 22:56:03.754027 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4638 22:56:03.757297 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4639 22:56:03.761056 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4640 22:56:03.767527 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4641 22:56:03.770861 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4642 22:56:03.773769 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4643 22:56:03.780852 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4644 22:56:03.784474 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4645 22:56:03.787541 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4646 22:56:03.790759 Total UI for P1: 0, mck2ui 16
4647 22:56:03.794170 best dqsien dly found for B0: ( 0, 13, 10)
4648 22:56:03.800704 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4649 22:56:03.801275 Total UI for P1: 0, mck2ui 16
4650 22:56:03.807288 best dqsien dly found for B1: ( 0, 13, 12)
4651 22:56:03.810784 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4652 22:56:03.814612 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4653 22:56:03.815183
4654 22:56:03.817220 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4655 22:56:03.820985 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4656 22:56:03.823767 [Gating] SW calibration Done
4657 22:56:03.824336 ==
4658 22:56:03.827276 Dram Type= 6, Freq= 0, CH_1, rank 1
4659 22:56:03.830303 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4660 22:56:03.830775 ==
4661 22:56:03.833614 RX Vref Scan: 0
4662 22:56:03.834081
4663 22:56:03.834452 RX Vref 0 -> 0, step: 1
4664 22:56:03.834798
4665 22:56:03.837291 RX Delay -230 -> 252, step: 16
4666 22:56:03.843524 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4667 22:56:03.847009 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4668 22:56:03.850755 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4669 22:56:03.854266 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4670 22:56:03.857187 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4671 22:56:03.863489 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4672 22:56:03.867509 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4673 22:56:03.870292 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4674 22:56:03.873857 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4675 22:56:03.876933 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4676 22:56:03.883449 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4677 22:56:03.887122 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4678 22:56:03.890861 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4679 22:56:03.894388 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4680 22:56:03.900290 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4681 22:56:03.903981 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4682 22:56:03.904542 ==
4683 22:56:03.907355 Dram Type= 6, Freq= 0, CH_1, rank 1
4684 22:56:03.910407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4685 22:56:03.910970 ==
4686 22:56:03.914102 DQS Delay:
4687 22:56:03.914658 DQS0 = 0, DQS1 = 0
4688 22:56:03.916778 DQM Delay:
4689 22:56:03.917245 DQM0 = 50, DQM1 = 47
4690 22:56:03.917614 DQ Delay:
4691 22:56:03.920796 DQ0 =49, DQ1 =49, DQ2 =33, DQ3 =49
4692 22:56:03.923410 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4693 22:56:03.926535 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4694 22:56:03.930364 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4695 22:56:03.930955
4696 22:56:03.931375
4697 22:56:03.931740 ==
4698 22:56:03.933871 Dram Type= 6, Freq= 0, CH_1, rank 1
4699 22:56:03.940084 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4700 22:56:03.940633 ==
4701 22:56:03.941009
4702 22:56:03.941355
4703 22:56:03.943510 TX Vref Scan disable
4704 22:56:03.944075 == TX Byte 0 ==
4705 22:56:03.946900 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4706 22:56:03.953832 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4707 22:56:03.954400 == TX Byte 1 ==
4708 22:56:03.957391 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4709 22:56:03.962926 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4710 22:56:03.963563 ==
4711 22:56:03.965802 Dram Type= 6, Freq= 0, CH_1, rank 1
4712 22:56:03.969376 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4713 22:56:03.969459 ==
4714 22:56:03.969523
4715 22:56:03.969583
4716 22:56:03.972767 TX Vref Scan disable
4717 22:56:03.976222 == TX Byte 0 ==
4718 22:56:03.979394 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4719 22:56:03.982676 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4720 22:56:03.986068 == TX Byte 1 ==
4721 22:56:03.989092 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4722 22:56:03.992768 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4723 22:56:03.992851
4724 22:56:03.996008 [DATLAT]
4725 22:56:03.996089 Freq=600, CH1 RK1
4726 22:56:03.996153
4727 22:56:03.999672 DATLAT Default: 0x9
4728 22:56:03.999768 0, 0xFFFF, sum = 0
4729 22:56:04.002515 1, 0xFFFF, sum = 0
4730 22:56:04.002603 2, 0xFFFF, sum = 0
4731 22:56:04.005922 3, 0xFFFF, sum = 0
4732 22:56:04.006017 4, 0xFFFF, sum = 0
4733 22:56:04.009513 5, 0xFFFF, sum = 0
4734 22:56:04.009616 6, 0xFFFF, sum = 0
4735 22:56:04.012463 7, 0xFFFF, sum = 0
4736 22:56:04.012565 8, 0x0, sum = 1
4737 22:56:04.016175 9, 0x0, sum = 2
4738 22:56:04.016288 10, 0x0, sum = 3
4739 22:56:04.019217 11, 0x0, sum = 4
4740 22:56:04.019370 best_step = 9
4741 22:56:04.019459
4742 22:56:04.019540 ==
4743 22:56:04.022823 Dram Type= 6, Freq= 0, CH_1, rank 1
4744 22:56:04.025750 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4745 22:56:04.029576 ==
4746 22:56:04.029710 RX Vref Scan: 0
4747 22:56:04.029848
4748 22:56:04.032569 RX Vref 0 -> 0, step: 1
4749 22:56:04.032719
4750 22:56:04.036588 RX Delay -163 -> 252, step: 8
4751 22:56:04.039405 iDelay=205, Bit 0, Center 56 (-83 ~ 196) 280
4752 22:56:04.043236 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4753 22:56:04.049790 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4754 22:56:04.052743 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4755 22:56:04.056043 iDelay=205, Bit 4, Center 44 (-99 ~ 188) 288
4756 22:56:04.059263 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4757 22:56:04.062462 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4758 22:56:04.069583 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4759 22:56:04.072569 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4760 22:56:04.075897 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4761 22:56:04.079382 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4762 22:56:04.082776 iDelay=205, Bit 11, Center 36 (-107 ~ 180) 288
4763 22:56:04.089507 iDelay=205, Bit 12, Center 56 (-91 ~ 204) 296
4764 22:56:04.092701 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4765 22:56:04.096296 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4766 22:56:04.099306 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4767 22:56:04.099759 ==
4768 22:56:04.102757 Dram Type= 6, Freq= 0, CH_1, rank 1
4769 22:56:04.109169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4770 22:56:04.109715 ==
4771 22:56:04.110060 DQS Delay:
4772 22:56:04.112274 DQS0 = 0, DQS1 = 0
4773 22:56:04.112693 DQM Delay:
4774 22:56:04.113020 DQM0 = 49, DQM1 = 45
4775 22:56:04.116130 DQ Delay:
4776 22:56:04.119041 DQ0 =56, DQ1 =44, DQ2 =36, DQ3 =44
4777 22:56:04.122637 DQ4 =44, DQ5 =60, DQ6 =60, DQ7 =48
4778 22:56:04.126200 DQ8 =32, DQ9 =36, DQ10 =48, DQ11 =36
4779 22:56:04.129434 DQ12 =56, DQ13 =52, DQ14 =52, DQ15 =52
4780 22:56:04.129951
4781 22:56:04.130284
4782 22:56:04.136206 [DQSOSCAuto] RK1, (LSB)MR18= 0x6a20, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 389 ps
4783 22:56:04.138970 CH1 RK1: MR19=808, MR18=6A20
4784 22:56:04.146393 CH1_RK1: MR19=0x808, MR18=0x6A20, DQSOSC=389, MR23=63, INC=173, DEC=115
4785 22:56:04.149287 [RxdqsGatingPostProcess] freq 600
4786 22:56:04.152737 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4787 22:56:04.156042 Pre-setting of DQS Precalculation
4788 22:56:04.163076 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4789 22:56:04.168991 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4790 22:56:04.176007 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4791 22:56:04.176426
4792 22:56:04.176807
4793 22:56:04.178880 [Calibration Summary] 1200 Mbps
4794 22:56:04.179298 CH 0, Rank 0
4795 22:56:04.182806 SW Impedance : PASS
4796 22:56:04.186056 DUTY Scan : NO K
4797 22:56:04.186570 ZQ Calibration : PASS
4798 22:56:04.189317 Jitter Meter : NO K
4799 22:56:04.192601 CBT Training : PASS
4800 22:56:04.193073 Write leveling : PASS
4801 22:56:04.195539 RX DQS gating : PASS
4802 22:56:04.199571 RX DQ/DQS(RDDQC) : PASS
4803 22:56:04.200097 TX DQ/DQS : PASS
4804 22:56:04.202586 RX DATLAT : PASS
4805 22:56:04.203100 RX DQ/DQS(Engine): PASS
4806 22:56:04.206252 TX OE : NO K
4807 22:56:04.206765 All Pass.
4808 22:56:04.207097
4809 22:56:04.209182 CH 0, Rank 1
4810 22:56:04.209695 SW Impedance : PASS
4811 22:56:04.212602 DUTY Scan : NO K
4812 22:56:04.216002 ZQ Calibration : PASS
4813 22:56:04.216523 Jitter Meter : NO K
4814 22:56:04.219289 CBT Training : PASS
4815 22:56:04.222821 Write leveling : PASS
4816 22:56:04.223407 RX DQS gating : PASS
4817 22:56:04.225703 RX DQ/DQS(RDDQC) : PASS
4818 22:56:04.229512 TX DQ/DQS : PASS
4819 22:56:04.230034 RX DATLAT : PASS
4820 22:56:04.232421 RX DQ/DQS(Engine): PASS
4821 22:56:04.236092 TX OE : NO K
4822 22:56:04.236617 All Pass.
4823 22:56:04.236953
4824 22:56:04.237261 CH 1, Rank 0
4825 22:56:04.238970 SW Impedance : PASS
4826 22:56:04.242705 DUTY Scan : NO K
4827 22:56:04.243221 ZQ Calibration : PASS
4828 22:56:04.245769 Jitter Meter : NO K
4829 22:56:04.249213 CBT Training : PASS
4830 22:56:04.249729 Write leveling : PASS
4831 22:56:04.252707 RX DQS gating : PASS
4832 22:56:04.253248 RX DQ/DQS(RDDQC) : PASS
4833 22:56:04.255812 TX DQ/DQS : PASS
4834 22:56:04.258909 RX DATLAT : PASS
4835 22:56:04.259467 RX DQ/DQS(Engine): PASS
4836 22:56:04.262347 TX OE : NO K
4837 22:56:04.262868 All Pass.
4838 22:56:04.263201
4839 22:56:04.265396 CH 1, Rank 1
4840 22:56:04.265921 SW Impedance : PASS
4841 22:56:04.268944 DUTY Scan : NO K
4842 22:56:04.272259 ZQ Calibration : PASS
4843 22:56:04.272695 Jitter Meter : NO K
4844 22:56:04.275546 CBT Training : PASS
4845 22:56:04.279390 Write leveling : PASS
4846 22:56:04.279923 RX DQS gating : PASS
4847 22:56:04.282197 RX DQ/DQS(RDDQC) : PASS
4848 22:56:04.286159 TX DQ/DQS : PASS
4849 22:56:04.286773 RX DATLAT : PASS
4850 22:56:04.288725 RX DQ/DQS(Engine): PASS
4851 22:56:04.291981 TX OE : NO K
4852 22:56:04.292405 All Pass.
4853 22:56:04.292740
4854 22:56:04.293049 DramC Write-DBI off
4855 22:56:04.295452 PER_BANK_REFRESH: Hybrid Mode
4856 22:56:04.298933 TX_TRACKING: ON
4857 22:56:04.305554 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4858 22:56:04.308429 [FAST_K] Save calibration result to emmc
4859 22:56:04.315293 dramc_set_vcore_voltage set vcore to 662500
4860 22:56:04.315787 Read voltage for 933, 3
4861 22:56:04.318578 Vio18 = 0
4862 22:56:04.319001 Vcore = 662500
4863 22:56:04.319563 Vdram = 0
4864 22:56:04.320005 Vddq = 0
4865 22:56:04.321906 Vmddr = 0
4866 22:56:04.325371 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4867 22:56:04.331667 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4868 22:56:04.335088 MEM_TYPE=3, freq_sel=17
4869 22:56:04.335545 sv_algorithm_assistance_LP4_1600
4870 22:56:04.341684 ============ PULL DRAM RESETB DOWN ============
4871 22:56:04.345066 ========== PULL DRAM RESETB DOWN end =========
4872 22:56:04.348295 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4873 22:56:04.351876 ===================================
4874 22:56:04.354919 LPDDR4 DRAM CONFIGURATION
4875 22:56:04.358212 ===================================
4876 22:56:04.361771 EX_ROW_EN[0] = 0x0
4877 22:56:04.362191 EX_ROW_EN[1] = 0x0
4878 22:56:04.365188 LP4Y_EN = 0x0
4879 22:56:04.365692 WORK_FSP = 0x0
4880 22:56:04.368186 WL = 0x3
4881 22:56:04.368606 RL = 0x3
4882 22:56:04.372053 BL = 0x2
4883 22:56:04.372494 RPST = 0x0
4884 22:56:04.374968 RD_PRE = 0x0
4885 22:56:04.375562 WR_PRE = 0x1
4886 22:56:04.378407 WR_PST = 0x0
4887 22:56:04.379026 DBI_WR = 0x0
4888 22:56:04.381792 DBI_RD = 0x0
4889 22:56:04.382389 OTF = 0x1
4890 22:56:04.384933 ===================================
4891 22:56:04.388312 ===================================
4892 22:56:04.392100 ANA top config
4893 22:56:04.394938 ===================================
4894 22:56:04.398370 DLL_ASYNC_EN = 0
4895 22:56:04.398981 ALL_SLAVE_EN = 1
4896 22:56:04.401552 NEW_RANK_MODE = 1
4897 22:56:04.404934 DLL_IDLE_MODE = 1
4898 22:56:04.408006 LP45_APHY_COMB_EN = 1
4899 22:56:04.408564 TX_ODT_DIS = 1
4900 22:56:04.411322 NEW_8X_MODE = 1
4901 22:56:04.414979 ===================================
4902 22:56:04.417956 ===================================
4903 22:56:04.421392 data_rate = 1866
4904 22:56:04.424667 CKR = 1
4905 22:56:04.428348 DQ_P2S_RATIO = 8
4906 22:56:04.431581 ===================================
4907 22:56:04.434565 CA_P2S_RATIO = 8
4908 22:56:04.435189 DQ_CA_OPEN = 0
4909 22:56:04.438146 DQ_SEMI_OPEN = 0
4910 22:56:04.441817 CA_SEMI_OPEN = 0
4911 22:56:04.444900 CA_FULL_RATE = 0
4912 22:56:04.447932 DQ_CKDIV4_EN = 1
4913 22:56:04.451655 CA_CKDIV4_EN = 1
4914 22:56:04.452116 CA_PREDIV_EN = 0
4915 22:56:04.454640 PH8_DLY = 0
4916 22:56:04.458071 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4917 22:56:04.461892 DQ_AAMCK_DIV = 4
4918 22:56:04.464923 CA_AAMCK_DIV = 4
4919 22:56:04.467930 CA_ADMCK_DIV = 4
4920 22:56:04.468379 DQ_TRACK_CA_EN = 0
4921 22:56:04.471525 CA_PICK = 933
4922 22:56:04.475080 CA_MCKIO = 933
4923 22:56:04.477855 MCKIO_SEMI = 0
4924 22:56:04.481630 PLL_FREQ = 3732
4925 22:56:04.484696 DQ_UI_PI_RATIO = 32
4926 22:56:04.487757 CA_UI_PI_RATIO = 0
4927 22:56:04.491396 ===================================
4928 22:56:04.494695 ===================================
4929 22:56:04.495116 memory_type:LPDDR4
4930 22:56:04.498023 GP_NUM : 10
4931 22:56:04.501334 SRAM_EN : 1
4932 22:56:04.501749 MD32_EN : 0
4933 22:56:04.504660 ===================================
4934 22:56:04.507823 [ANA_INIT] >>>>>>>>>>>>>>
4935 22:56:04.510945 <<<<<< [CONFIGURE PHASE]: ANA_TX
4936 22:56:04.514971 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4937 22:56:04.517552 ===================================
4938 22:56:04.520913 data_rate = 1866,PCW = 0X8f00
4939 22:56:04.524462 ===================================
4940 22:56:04.528286 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4941 22:56:04.531316 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4942 22:56:04.537731 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4943 22:56:04.540842 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4944 22:56:04.544492 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4945 22:56:04.547699 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4946 22:56:04.550783 [ANA_INIT] flow start
4947 22:56:04.554262 [ANA_INIT] PLL >>>>>>>>
4948 22:56:04.554683 [ANA_INIT] PLL <<<<<<<<
4949 22:56:04.557838 [ANA_INIT] MIDPI >>>>>>>>
4950 22:56:04.561147 [ANA_INIT] MIDPI <<<<<<<<
4951 22:56:04.561570 [ANA_INIT] DLL >>>>>>>>
4952 22:56:04.564683 [ANA_INIT] flow end
4953 22:56:04.568027 ============ LP4 DIFF to SE enter ============
4954 22:56:04.573983 ============ LP4 DIFF to SE exit ============
4955 22:56:04.574407 [ANA_INIT] <<<<<<<<<<<<<
4956 22:56:04.577486 [Flow] Enable top DCM control >>>>>
4957 22:56:04.580705 [Flow] Enable top DCM control <<<<<
4958 22:56:04.583954 Enable DLL master slave shuffle
4959 22:56:04.590690 ==============================================================
4960 22:56:04.591115 Gating Mode config
4961 22:56:04.597246 ==============================================================
4962 22:56:04.600706 Config description:
4963 22:56:04.607360 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4964 22:56:04.613839 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4965 22:56:04.620570 SELPH_MODE 0: By rank 1: By Phase
4966 22:56:04.627031 ==============================================================
4967 22:56:04.627494 GAT_TRACK_EN = 1
4968 22:56:04.630509 RX_GATING_MODE = 2
4969 22:56:04.634095 RX_GATING_TRACK_MODE = 2
4970 22:56:04.637134 SELPH_MODE = 1
4971 22:56:04.640597 PICG_EARLY_EN = 1
4972 22:56:04.644331 VALID_LAT_VALUE = 1
4973 22:56:04.651208 ==============================================================
4974 22:56:04.654135 Enter into Gating configuration >>>>
4975 22:56:04.657253 Exit from Gating configuration <<<<
4976 22:56:04.660852 Enter into DVFS_PRE_config >>>>>
4977 22:56:04.670674 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4978 22:56:04.674241 Exit from DVFS_PRE_config <<<<<
4979 22:56:04.677706 Enter into PICG configuration >>>>
4980 22:56:04.680795 Exit from PICG configuration <<<<
4981 22:56:04.684155 [RX_INPUT] configuration >>>>>
4982 22:56:04.684582 [RX_INPUT] configuration <<<<<
4983 22:56:04.690776 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4984 22:56:04.698150 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4985 22:56:04.701319 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4986 22:56:04.707056 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4987 22:56:04.713846 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4988 22:56:04.720246 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4989 22:56:04.723850 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4990 22:56:04.727410 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4991 22:56:04.734176 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4992 22:56:04.737449 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4993 22:56:04.741183 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4994 22:56:04.747097 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4995 22:56:04.750197 ===================================
4996 22:56:04.750669 LPDDR4 DRAM CONFIGURATION
4997 22:56:04.753670 ===================================
4998 22:56:04.756921 EX_ROW_EN[0] = 0x0
4999 22:56:04.759960 EX_ROW_EN[1] = 0x0
5000 22:56:04.760431 LP4Y_EN = 0x0
5001 22:56:04.763484 WORK_FSP = 0x0
5002 22:56:04.764038 WL = 0x3
5003 22:56:04.767153 RL = 0x3
5004 22:56:04.767761 BL = 0x2
5005 22:56:04.769975 RPST = 0x0
5006 22:56:04.770444 RD_PRE = 0x0
5007 22:56:04.773521 WR_PRE = 0x1
5008 22:56:04.774038 WR_PST = 0x0
5009 22:56:04.776599 DBI_WR = 0x0
5010 22:56:04.777163 DBI_RD = 0x0
5011 22:56:04.779955 OTF = 0x1
5012 22:56:04.783162 ===================================
5013 22:56:04.787040 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5014 22:56:04.790612 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5015 22:56:04.796664 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5016 22:56:04.800300 ===================================
5017 22:56:04.800773 LPDDR4 DRAM CONFIGURATION
5018 22:56:04.803263 ===================================
5019 22:56:04.806513 EX_ROW_EN[0] = 0x10
5020 22:56:04.806939 EX_ROW_EN[1] = 0x0
5021 22:56:04.810277 LP4Y_EN = 0x0
5022 22:56:04.810806 WORK_FSP = 0x0
5023 22:56:04.813083 WL = 0x3
5024 22:56:04.813510 RL = 0x3
5025 22:56:04.816595 BL = 0x2
5026 22:56:04.819640 RPST = 0x0
5027 22:56:04.820090 RD_PRE = 0x0
5028 22:56:04.823167 WR_PRE = 0x1
5029 22:56:04.823622 WR_PST = 0x0
5030 22:56:04.826589 DBI_WR = 0x0
5031 22:56:04.827112 DBI_RD = 0x0
5032 22:56:04.830179 OTF = 0x1
5033 22:56:04.833510 ===================================
5034 22:56:04.836336 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5035 22:56:04.841801 nWR fixed to 30
5036 22:56:04.845499 [ModeRegInit_LP4] CH0 RK0
5037 22:56:04.845923 [ModeRegInit_LP4] CH0 RK1
5038 22:56:04.848649 [ModeRegInit_LP4] CH1 RK0
5039 22:56:04.852209 [ModeRegInit_LP4] CH1 RK1
5040 22:56:04.852663 match AC timing 9
5041 22:56:04.858667 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5042 22:56:04.862197 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5043 22:56:04.865360 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5044 22:56:04.871981 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5045 22:56:04.875059 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5046 22:56:04.875604 ==
5047 22:56:04.878289 Dram Type= 6, Freq= 0, CH_0, rank 0
5048 22:56:04.882331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5049 22:56:04.882850 ==
5050 22:56:04.888789 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5051 22:56:04.895164 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5052 22:56:04.898826 [CA 0] Center 37 (6~68) winsize 63
5053 22:56:04.901799 [CA 1] Center 37 (7~68) winsize 62
5054 22:56:04.904988 [CA 2] Center 34 (4~65) winsize 62
5055 22:56:04.908444 [CA 3] Center 33 (3~64) winsize 62
5056 22:56:04.911674 [CA 4] Center 33 (3~64) winsize 62
5057 22:56:04.915115 [CA 5] Center 32 (2~62) winsize 61
5058 22:56:04.915684
5059 22:56:04.918045 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5060 22:56:04.918471
5061 22:56:04.921732 [CATrainingPosCal] consider 1 rank data
5062 22:56:04.925145 u2DelayCellTimex100 = 270/100 ps
5063 22:56:04.928452 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5064 22:56:04.931706 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5065 22:56:04.934923 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5066 22:56:04.938591 CA3 delay=33 (3~64),Diff = 1 PI (6 cell)
5067 22:56:04.942040 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5068 22:56:04.945161 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5069 22:56:04.948083
5070 22:56:04.951389 CA PerBit enable=1, Macro0, CA PI delay=32
5071 22:56:04.951808
5072 22:56:04.955228 [CBTSetCACLKResult] CA Dly = 32
5073 22:56:04.955714 CS Dly: 5 (0~36)
5074 22:56:04.956049 ==
5075 22:56:04.958024 Dram Type= 6, Freq= 0, CH_0, rank 1
5076 22:56:04.961222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5077 22:56:04.961705 ==
5078 22:56:04.967976 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5079 22:56:04.974787 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5080 22:56:04.977833 [CA 0] Center 37 (6~68) winsize 63
5081 22:56:04.981598 [CA 1] Center 37 (7~68) winsize 62
5082 22:56:04.984625 [CA 2] Center 34 (4~65) winsize 62
5083 22:56:04.988216 [CA 3] Center 34 (4~64) winsize 61
5084 22:56:04.991358 [CA 4] Center 32 (2~63) winsize 62
5085 22:56:04.994700 [CA 5] Center 32 (2~62) winsize 61
5086 22:56:04.995219
5087 22:56:04.997989 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5088 22:56:04.998507
5089 22:56:05.001503 [CATrainingPosCal] consider 2 rank data
5090 22:56:05.004787 u2DelayCellTimex100 = 270/100 ps
5091 22:56:05.008070 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5092 22:56:05.011473 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5093 22:56:05.014361 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5094 22:56:05.017769 CA3 delay=34 (4~64),Diff = 2 PI (12 cell)
5095 22:56:05.024409 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5096 22:56:05.027689 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5097 22:56:05.028121
5098 22:56:05.031201 CA PerBit enable=1, Macro0, CA PI delay=32
5099 22:56:05.031723
5100 22:56:05.034533 [CBTSetCACLKResult] CA Dly = 32
5101 22:56:05.035104 CS Dly: 6 (0~38)
5102 22:56:05.035636
5103 22:56:05.037759 ----->DramcWriteLeveling(PI) begin...
5104 22:56:05.038238 ==
5105 22:56:05.041276 Dram Type= 6, Freq= 0, CH_0, rank 0
5106 22:56:05.047987 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5107 22:56:05.048585 ==
5108 22:56:05.051315 Write leveling (Byte 0): 32 => 32
5109 22:56:05.054476 Write leveling (Byte 1): 30 => 30
5110 22:56:05.055053 DramcWriteLeveling(PI) end<-----
5111 22:56:05.055606
5112 22:56:05.058192 ==
5113 22:56:05.061259 Dram Type= 6, Freq= 0, CH_0, rank 0
5114 22:56:05.064738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5115 22:56:05.065316 ==
5116 22:56:05.067638 [Gating] SW mode calibration
5117 22:56:05.073902 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5118 22:56:05.077772 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5119 22:56:05.084636 0 14 0 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
5120 22:56:05.087677 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5121 22:56:05.091420 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5122 22:56:05.097845 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5123 22:56:05.100903 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5124 22:56:05.104535 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5125 22:56:05.110819 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
5126 22:56:05.114456 0 14 28 | B1->B0 | 3333 2727 | 0 0 | (0 1) (1 0)
5127 22:56:05.118129 0 15 0 | B1->B0 | 2d2d 2323 | 0 0 | (1 0) (0 0)
5128 22:56:05.124350 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5129 22:56:05.127544 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5130 22:56:05.130610 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5131 22:56:05.137077 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5132 22:56:05.141011 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5133 22:56:05.144132 0 15 24 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
5134 22:56:05.151090 0 15 28 | B1->B0 | 2424 4040 | 0 1 | (0 0) (0 0)
5135 22:56:05.154261 1 0 0 | B1->B0 | 3838 4646 | 0 0 | (1 1) (0 0)
5136 22:56:05.157798 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5137 22:56:05.160963 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5138 22:56:05.167761 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5139 22:56:05.170459 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5140 22:56:05.174062 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5141 22:56:05.180617 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5142 22:56:05.183866 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5143 22:56:05.187094 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5144 22:56:05.194123 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5145 22:56:05.196987 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5146 22:56:05.200820 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5147 22:56:05.207527 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5148 22:56:05.210504 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5149 22:56:05.214146 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5150 22:56:05.220309 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5151 22:56:05.223437 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5152 22:56:05.226688 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5153 22:56:05.233413 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5154 22:56:05.236859 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5155 22:56:05.240076 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5156 22:56:05.246604 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5157 22:56:05.249920 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5158 22:56:05.253107 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5159 22:56:05.259605 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5160 22:56:05.259833 Total UI for P1: 0, mck2ui 16
5161 22:56:05.266348 best dqsien dly found for B0: ( 1, 2, 28)
5162 22:56:05.266509 Total UI for P1: 0, mck2ui 16
5163 22:56:05.273131 best dqsien dly found for B1: ( 1, 2, 28)
5164 22:56:05.276559 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5165 22:56:05.279631 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5166 22:56:05.279762
5167 22:56:05.283274 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5168 22:56:05.286467 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5169 22:56:05.289416 [Gating] SW calibration Done
5170 22:56:05.289568 ==
5171 22:56:05.292882 Dram Type= 6, Freq= 0, CH_0, rank 0
5172 22:56:05.296035 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5173 22:56:05.296121 ==
5174 22:56:05.299881 RX Vref Scan: 0
5175 22:56:05.299968
5176 22:56:05.300035 RX Vref 0 -> 0, step: 1
5177 22:56:05.300098
5178 22:56:05.302779 RX Delay -80 -> 252, step: 8
5179 22:56:05.306426 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5180 22:56:05.312833 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5181 22:56:05.316665 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5182 22:56:05.319670 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5183 22:56:05.322896 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5184 22:56:05.326272 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5185 22:56:05.330225 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5186 22:56:05.336390 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5187 22:56:05.340007 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5188 22:56:05.343304 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5189 22:56:05.346730 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5190 22:56:05.349567 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5191 22:56:05.353256 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5192 22:56:05.359863 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5193 22:56:05.362683 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5194 22:56:05.365698 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5195 22:56:05.365781 ==
5196 22:56:05.369261 Dram Type= 6, Freq= 0, CH_0, rank 0
5197 22:56:05.372605 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5198 22:56:05.372689 ==
5199 22:56:05.376172 DQS Delay:
5200 22:56:05.376254 DQS0 = 0, DQS1 = 0
5201 22:56:05.379213 DQM Delay:
5202 22:56:05.379342 DQM0 = 105, DQM1 = 93
5203 22:56:05.379428 DQ Delay:
5204 22:56:05.382515 DQ0 =107, DQ1 =107, DQ2 =99, DQ3 =99
5205 22:56:05.385749 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =115
5206 22:56:05.389331 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87
5207 22:56:05.392706 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =99
5208 22:56:05.392788
5209 22:56:05.395822
5210 22:56:05.395903 ==
5211 22:56:05.398990 Dram Type= 6, Freq= 0, CH_0, rank 0
5212 22:56:05.402487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5213 22:56:05.402575 ==
5214 22:56:05.402645
5215 22:56:05.402707
5216 22:56:05.405905 TX Vref Scan disable
5217 22:56:05.406077 == TX Byte 0 ==
5218 22:56:05.412985 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5219 22:56:05.416036 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5220 22:56:05.416221 == TX Byte 1 ==
5221 22:56:05.422461 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5222 22:56:05.426152 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5223 22:56:05.426327 ==
5224 22:56:05.428786 Dram Type= 6, Freq= 0, CH_0, rank 0
5225 22:56:05.432088 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5226 22:56:05.432248 ==
5227 22:56:05.432371
5228 22:56:05.432483
5229 22:56:05.435770 TX Vref Scan disable
5230 22:56:05.439024 == TX Byte 0 ==
5231 22:56:05.442554 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5232 22:56:05.445933 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5233 22:56:05.449243 == TX Byte 1 ==
5234 22:56:05.452620 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5235 22:56:05.456140 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5236 22:56:05.456583
5237 22:56:05.459290 [DATLAT]
5238 22:56:05.459739 Freq=933, CH0 RK0
5239 22:56:05.460077
5240 22:56:05.462561 DATLAT Default: 0xd
5241 22:56:05.462985 0, 0xFFFF, sum = 0
5242 22:56:05.465914 1, 0xFFFF, sum = 0
5243 22:56:05.466336 2, 0xFFFF, sum = 0
5244 22:56:05.468919 3, 0xFFFF, sum = 0
5245 22:56:05.469342 4, 0xFFFF, sum = 0
5246 22:56:05.472453 5, 0xFFFF, sum = 0
5247 22:56:05.472883 6, 0xFFFF, sum = 0
5248 22:56:05.475482 7, 0xFFFF, sum = 0
5249 22:56:05.475908 8, 0xFFFF, sum = 0
5250 22:56:05.479051 9, 0xFFFF, sum = 0
5251 22:56:05.479643 10, 0x0, sum = 1
5252 22:56:05.482308 11, 0x0, sum = 2
5253 22:56:05.482738 12, 0x0, sum = 3
5254 22:56:05.485967 13, 0x0, sum = 4
5255 22:56:05.486395 best_step = 11
5256 22:56:05.486773
5257 22:56:05.487089 ==
5258 22:56:05.489327 Dram Type= 6, Freq= 0, CH_0, rank 0
5259 22:56:05.495704 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5260 22:56:05.496133 ==
5261 22:56:05.496470 RX Vref Scan: 1
5262 22:56:05.496846
5263 22:56:05.498765 RX Vref 0 -> 0, step: 1
5264 22:56:05.499436
5265 22:56:05.502570 RX Delay -53 -> 252, step: 4
5266 22:56:05.502994
5267 22:56:05.505614 Set Vref, RX VrefLevel [Byte0]: 56
5268 22:56:05.508980 [Byte1]: 48
5269 22:56:05.509552
5270 22:56:05.512196 Final RX Vref Byte 0 = 56 to rank0
5271 22:56:05.515873 Final RX Vref Byte 1 = 48 to rank0
5272 22:56:05.519105 Final RX Vref Byte 0 = 56 to rank1
5273 22:56:05.522276 Final RX Vref Byte 1 = 48 to rank1==
5274 22:56:05.525693 Dram Type= 6, Freq= 0, CH_0, rank 0
5275 22:56:05.529162 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5276 22:56:05.529636 ==
5277 22:56:05.532214 DQS Delay:
5278 22:56:05.532782 DQS0 = 0, DQS1 = 0
5279 22:56:05.533161 DQM Delay:
5280 22:56:05.535700 DQM0 = 105, DQM1 = 95
5281 22:56:05.536269 DQ Delay:
5282 22:56:05.538985 DQ0 =104, DQ1 =108, DQ2 =102, DQ3 =102
5283 22:56:05.541834 DQ4 =106, DQ5 =96, DQ6 =110, DQ7 =112
5284 22:56:05.545675 DQ8 =82, DQ9 =84, DQ10 =98, DQ11 =88
5285 22:56:05.551646 DQ12 =102, DQ13 =102, DQ14 =104, DQ15 =104
5286 22:56:05.552117
5287 22:56:05.552483
5288 22:56:05.558601 [DQSOSCAuto] RK0, (LSB)MR18= 0x342b, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 405 ps
5289 22:56:05.562202 CH0 RK0: MR19=505, MR18=342B
5290 22:56:05.568460 CH0_RK0: MR19=0x505, MR18=0x342B, DQSOSC=405, MR23=63, INC=66, DEC=44
5291 22:56:05.569029
5292 22:56:05.571666 ----->DramcWriteLeveling(PI) begin...
5293 22:56:05.572141 ==
5294 22:56:05.574724 Dram Type= 6, Freq= 0, CH_0, rank 1
5295 22:56:05.578746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5296 22:56:05.579431 ==
5297 22:56:05.581714 Write leveling (Byte 0): 34 => 34
5298 22:56:05.585312 Write leveling (Byte 1): 28 => 28
5299 22:56:05.588356 DramcWriteLeveling(PI) end<-----
5300 22:56:05.588831
5301 22:56:05.589202 ==
5302 22:56:05.591844 Dram Type= 6, Freq= 0, CH_0, rank 1
5303 22:56:05.595425 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5304 22:56:05.595999 ==
5305 22:56:05.598307 [Gating] SW mode calibration
5306 22:56:05.605157 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5307 22:56:05.612225 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5308 22:56:05.615182 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5309 22:56:05.621817 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5310 22:56:05.624889 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5311 22:56:05.628314 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5312 22:56:05.631724 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5313 22:56:05.638633 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5314 22:56:05.641607 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5315 22:56:05.644754 0 14 28 | B1->B0 | 2424 2626 | 0 0 | (0 0) (1 0)
5316 22:56:05.651699 0 15 0 | B1->B0 | 2424 2a2a | 0 0 | (0 0) (0 0)
5317 22:56:05.655282 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5318 22:56:05.658488 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5319 22:56:05.664913 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5320 22:56:05.668173 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5321 22:56:05.671729 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5322 22:56:05.678313 0 15 24 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
5323 22:56:05.681181 0 15 28 | B1->B0 | 3737 3332 | 0 1 | (0 0) (0 0)
5324 22:56:05.684842 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5325 22:56:05.691303 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5326 22:56:05.694985 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5327 22:56:05.698249 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5328 22:56:05.704390 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5329 22:56:05.708086 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5330 22:56:05.711367 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5331 22:56:05.717926 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5332 22:56:05.721756 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5333 22:56:05.725040 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5334 22:56:05.731311 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5335 22:56:05.734988 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5336 22:56:05.738351 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5337 22:56:05.744255 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5338 22:56:05.747972 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5339 22:56:05.751501 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5340 22:56:05.757894 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5341 22:56:05.761235 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5342 22:56:05.764216 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5343 22:56:05.771490 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5344 22:56:05.774071 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5345 22:56:05.777835 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5346 22:56:05.784204 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5347 22:56:05.787410 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5348 22:56:05.791083 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5349 22:56:05.794203 Total UI for P1: 0, mck2ui 16
5350 22:56:05.797835 best dqsien dly found for B0: ( 1, 2, 26)
5351 22:56:05.801195 Total UI for P1: 0, mck2ui 16
5352 22:56:05.804514 best dqsien dly found for B1: ( 1, 2, 28)
5353 22:56:05.807422 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5354 22:56:05.810930 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5355 22:56:05.811538
5356 22:56:05.814205 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5357 22:56:05.821095 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5358 22:56:05.821655 [Gating] SW calibration Done
5359 22:56:05.822025 ==
5360 22:56:05.823922 Dram Type= 6, Freq= 0, CH_0, rank 1
5361 22:56:05.830923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5362 22:56:05.831503 ==
5363 22:56:05.831878 RX Vref Scan: 0
5364 22:56:05.832221
5365 22:56:05.834692 RX Vref 0 -> 0, step: 1
5366 22:56:05.835254
5367 22:56:05.837345 RX Delay -80 -> 252, step: 8
5368 22:56:05.840982 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5369 22:56:05.844160 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5370 22:56:05.847699 iDelay=208, Bit 2, Center 107 (16 ~ 199) 184
5371 22:56:05.851384 iDelay=208, Bit 3, Center 103 (16 ~ 191) 176
5372 22:56:05.857989 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5373 22:56:05.861021 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5374 22:56:05.864093 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5375 22:56:05.867794 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5376 22:56:05.871308 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5377 22:56:05.874189 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5378 22:56:05.880774 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5379 22:56:05.884258 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5380 22:56:05.887492 iDelay=208, Bit 12, Center 99 (16 ~ 183) 168
5381 22:56:05.890803 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5382 22:56:05.893935 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5383 22:56:05.900553 iDelay=208, Bit 15, Center 103 (16 ~ 191) 176
5384 22:56:05.901314 ==
5385 22:56:05.904104 Dram Type= 6, Freq= 0, CH_0, rank 1
5386 22:56:05.907317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5387 22:56:05.908048 ==
5388 22:56:05.908675 DQS Delay:
5389 22:56:05.911031 DQS0 = 0, DQS1 = 0
5390 22:56:05.911768 DQM Delay:
5391 22:56:05.914006 DQM0 = 105, DQM1 = 95
5392 22:56:05.914659 DQ Delay:
5393 22:56:05.917196 DQ0 =107, DQ1 =107, DQ2 =107, DQ3 =103
5394 22:56:05.920085 DQ4 =107, DQ5 =95, DQ6 =107, DQ7 =111
5395 22:56:05.923620 DQ8 =87, DQ9 =83, DQ10 =95, DQ11 =87
5396 22:56:05.926915 DQ12 =99, DQ13 =103, DQ14 =103, DQ15 =103
5397 22:56:05.927014
5398 22:56:05.927105
5399 22:56:05.927193 ==
5400 22:56:05.929906 Dram Type= 6, Freq= 0, CH_0, rank 1
5401 22:56:05.936559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5402 22:56:05.936648 ==
5403 22:56:05.936737
5404 22:56:05.936797
5405 22:56:05.936853 TX Vref Scan disable
5406 22:56:05.940932 == TX Byte 0 ==
5407 22:56:05.943805 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5408 22:56:05.950523 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5409 22:56:05.950621 == TX Byte 1 ==
5410 22:56:05.953913 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5411 22:56:05.960333 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5412 22:56:05.960441 ==
5413 22:56:05.963511 Dram Type= 6, Freq= 0, CH_0, rank 1
5414 22:56:05.966854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5415 22:56:05.966963 ==
5416 22:56:05.967055
5417 22:56:05.967143
5418 22:56:05.970334 TX Vref Scan disable
5419 22:56:05.970432 == TX Byte 0 ==
5420 22:56:05.976988 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5421 22:56:05.980553 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5422 22:56:05.980657 == TX Byte 1 ==
5423 22:56:05.986961 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5424 22:56:05.990355 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5425 22:56:05.990453
5426 22:56:05.990523 [DATLAT]
5427 22:56:05.993546 Freq=933, CH0 RK1
5428 22:56:05.993641
5429 22:56:05.993728 DATLAT Default: 0xb
5430 22:56:05.997106 0, 0xFFFF, sum = 0
5431 22:56:05.997192 1, 0xFFFF, sum = 0
5432 22:56:06.000576 2, 0xFFFF, sum = 0
5433 22:56:06.000661 3, 0xFFFF, sum = 0
5434 22:56:06.003830 4, 0xFFFF, sum = 0
5435 22:56:06.003914 5, 0xFFFF, sum = 0
5436 22:56:06.007263 6, 0xFFFF, sum = 0
5437 22:56:06.010518 7, 0xFFFF, sum = 0
5438 22:56:06.010603 8, 0xFFFF, sum = 0
5439 22:56:06.013916 9, 0xFFFF, sum = 0
5440 22:56:06.013999 10, 0x0, sum = 1
5441 22:56:06.014065 11, 0x0, sum = 2
5442 22:56:06.017009 12, 0x0, sum = 3
5443 22:56:06.017091 13, 0x0, sum = 4
5444 22:56:06.020618 best_step = 11
5445 22:56:06.020698
5446 22:56:06.020762 ==
5447 22:56:06.023892 Dram Type= 6, Freq= 0, CH_0, rank 1
5448 22:56:06.027619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5449 22:56:06.027701 ==
5450 22:56:06.030466 RX Vref Scan: 0
5451 22:56:06.030547
5452 22:56:06.030611 RX Vref 0 -> 0, step: 1
5453 22:56:06.030669
5454 22:56:06.033835 RX Delay -53 -> 252, step: 4
5455 22:56:06.041030 iDelay=199, Bit 0, Center 102 (11 ~ 194) 184
5456 22:56:06.044181 iDelay=199, Bit 1, Center 104 (19 ~ 190) 172
5457 22:56:06.047456 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5458 22:56:06.050753 iDelay=199, Bit 3, Center 100 (11 ~ 190) 180
5459 22:56:06.054346 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176
5460 22:56:06.061067 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5461 22:56:06.064076 iDelay=199, Bit 6, Center 108 (23 ~ 194) 172
5462 22:56:06.067881 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5463 22:56:06.070677 iDelay=199, Bit 8, Center 86 (3 ~ 170) 168
5464 22:56:06.074057 iDelay=199, Bit 9, Center 84 (3 ~ 166) 164
5465 22:56:06.077514 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5466 22:56:06.084339 iDelay=199, Bit 11, Center 88 (7 ~ 170) 164
5467 22:56:06.087600 iDelay=199, Bit 12, Center 100 (19 ~ 182) 164
5468 22:56:06.090699 iDelay=199, Bit 13, Center 100 (19 ~ 182) 164
5469 22:56:06.094120 iDelay=199, Bit 14, Center 104 (23 ~ 186) 164
5470 22:56:06.101105 iDelay=199, Bit 15, Center 102 (19 ~ 186) 168
5471 22:56:06.101187 ==
5472 22:56:06.104195 Dram Type= 6, Freq= 0, CH_0, rank 1
5473 22:56:06.107625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5474 22:56:06.107707 ==
5475 22:56:06.107772 DQS Delay:
5476 22:56:06.111049 DQS0 = 0, DQS1 = 0
5477 22:56:06.111129 DQM Delay:
5478 22:56:06.113943 DQM0 = 104, DQM1 = 94
5479 22:56:06.114024 DQ Delay:
5480 22:56:06.117038 DQ0 =102, DQ1 =104, DQ2 =102, DQ3 =100
5481 22:56:06.120509 DQ4 =106, DQ5 =98, DQ6 =108, DQ7 =112
5482 22:56:06.124317 DQ8 =86, DQ9 =84, DQ10 =94, DQ11 =88
5483 22:56:06.127107 DQ12 =100, DQ13 =100, DQ14 =104, DQ15 =102
5484 22:56:06.127191
5485 22:56:06.127255
5486 22:56:06.137724 [DQSOSCAuto] RK1, (LSB)MR18= 0x2801, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 409 ps
5487 22:56:06.137806 CH0 RK1: MR19=505, MR18=2801
5488 22:56:06.143712 CH0_RK1: MR19=0x505, MR18=0x2801, DQSOSC=409, MR23=63, INC=64, DEC=43
5489 22:56:06.147086 [RxdqsGatingPostProcess] freq 933
5490 22:56:06.153883 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5491 22:56:06.156955 best DQS0 dly(2T, 0.5T) = (0, 10)
5492 22:56:06.160385 best DQS1 dly(2T, 0.5T) = (0, 10)
5493 22:56:06.164185 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5494 22:56:06.167176 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5495 22:56:06.170236 best DQS0 dly(2T, 0.5T) = (0, 10)
5496 22:56:06.173623 best DQS1 dly(2T, 0.5T) = (0, 10)
5497 22:56:06.177075 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5498 22:56:06.180340 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5499 22:56:06.180421 Pre-setting of DQS Precalculation
5500 22:56:06.187010 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5501 22:56:06.187092 ==
5502 22:56:06.190419 Dram Type= 6, Freq= 0, CH_1, rank 0
5503 22:56:06.193466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5504 22:56:06.193548 ==
5505 22:56:06.200377 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5506 22:56:06.207093 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5507 22:56:06.209840 [CA 0] Center 36 (6~67) winsize 62
5508 22:56:06.213135 [CA 1] Center 36 (6~67) winsize 62
5509 22:56:06.216613 [CA 2] Center 35 (5~65) winsize 61
5510 22:56:06.220091 [CA 3] Center 34 (4~65) winsize 62
5511 22:56:06.223565 [CA 4] Center 34 (4~65) winsize 62
5512 22:56:06.227004 [CA 5] Center 33 (3~64) winsize 62
5513 22:56:06.227085
5514 22:56:06.229650 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5515 22:56:06.229732
5516 22:56:06.233237 [CATrainingPosCal] consider 1 rank data
5517 22:56:06.236456 u2DelayCellTimex100 = 270/100 ps
5518 22:56:06.239993 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5519 22:56:06.243286 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5520 22:56:06.246911 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5521 22:56:06.249917 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5522 22:56:06.253185 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5523 22:56:06.259537 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5524 22:56:06.259718
5525 22:56:06.263275 CA PerBit enable=1, Macro0, CA PI delay=33
5526 22:56:06.263409
5527 22:56:06.266435 [CBTSetCACLKResult] CA Dly = 33
5528 22:56:06.266518 CS Dly: 6 (0~37)
5529 22:56:06.266583 ==
5530 22:56:06.269998 Dram Type= 6, Freq= 0, CH_1, rank 1
5531 22:56:06.272904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5532 22:56:06.276092 ==
5533 22:56:06.279666 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5534 22:56:06.286471 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5535 22:56:06.289619 [CA 0] Center 36 (6~67) winsize 62
5536 22:56:06.293446 [CA 1] Center 37 (6~68) winsize 63
5537 22:56:06.296144 [CA 2] Center 34 (4~65) winsize 62
5538 22:56:06.299770 [CA 3] Center 34 (4~65) winsize 62
5539 22:56:06.303026 [CA 4] Center 34 (4~65) winsize 62
5540 22:56:06.306891 [CA 5] Center 34 (4~64) winsize 61
5541 22:56:06.307109
5542 22:56:06.309410 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5543 22:56:06.309630
5544 22:56:06.313325 [CATrainingPosCal] consider 2 rank data
5545 22:56:06.316693 u2DelayCellTimex100 = 270/100 ps
5546 22:56:06.319500 CA0 delay=36 (6~67),Diff = 2 PI (12 cell)
5547 22:56:06.322763 CA1 delay=36 (6~67),Diff = 2 PI (12 cell)
5548 22:56:06.326302 CA2 delay=35 (5~65),Diff = 1 PI (6 cell)
5549 22:56:06.329302 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5550 22:56:06.336529 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5551 22:56:06.339868 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5552 22:56:06.340556
5553 22:56:06.342885 CA PerBit enable=1, Macro0, CA PI delay=34
5554 22:56:06.343614
5555 22:56:06.346255 [CBTSetCACLKResult] CA Dly = 34
5556 22:56:06.346758 CS Dly: 7 (0~40)
5557 22:56:06.347283
5558 22:56:06.349288 ----->DramcWriteLeveling(PI) begin...
5559 22:56:06.349833 ==
5560 22:56:06.353137 Dram Type= 6, Freq= 0, CH_1, rank 0
5561 22:56:06.359147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5562 22:56:06.359867 ==
5563 22:56:06.362693 Write leveling (Byte 0): 27 => 27
5564 22:56:06.365987 Write leveling (Byte 1): 29 => 29
5565 22:56:06.366413 DramcWriteLeveling(PI) end<-----
5566 22:56:06.369558
5567 22:56:06.369898 ==
5568 22:56:06.372302 Dram Type= 6, Freq= 0, CH_1, rank 0
5569 22:56:06.375857 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5570 22:56:06.375976 ==
5571 22:56:06.378946 [Gating] SW mode calibration
5572 22:56:06.385957 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5573 22:56:06.388910 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5574 22:56:06.395362 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5575 22:56:06.398912 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5576 22:56:06.402809 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5577 22:56:06.408869 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5578 22:56:06.412266 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5579 22:56:06.415839 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5580 22:56:06.422099 0 14 24 | B1->B0 | 3434 2f2f | 1 1 | (1 0) (1 0)
5581 22:56:06.425764 0 14 28 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
5582 22:56:06.429173 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5583 22:56:06.435480 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5584 22:56:06.438834 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5585 22:56:06.442261 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5586 22:56:06.449224 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5587 22:56:06.452674 0 15 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5588 22:56:06.455548 0 15 24 | B1->B0 | 2828 3535 | 0 0 | (0 0) (0 0)
5589 22:56:06.458742 0 15 28 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
5590 22:56:06.465511 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5591 22:56:06.469060 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5592 22:56:06.472053 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5593 22:56:06.478911 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5594 22:56:06.482011 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5595 22:56:06.485842 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5596 22:56:06.492421 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5597 22:56:06.495321 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5598 22:56:06.499187 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5599 22:56:06.505332 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5600 22:56:06.509124 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5601 22:56:06.512040 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5602 22:56:06.518687 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5603 22:56:06.522038 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5604 22:56:06.525199 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5605 22:56:06.531856 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5606 22:56:06.535099 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5607 22:56:06.538526 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5608 22:56:06.545293 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5609 22:56:06.548935 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5610 22:56:06.552229 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5611 22:56:06.558960 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5612 22:56:06.561868 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5613 22:56:06.565033 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5614 22:56:06.571857 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5615 22:56:06.571979 Total UI for P1: 0, mck2ui 16
5616 22:56:06.578665 best dqsien dly found for B0: ( 1, 2, 26)
5617 22:56:06.578780 Total UI for P1: 0, mck2ui 16
5618 22:56:06.584764 best dqsien dly found for B1: ( 1, 2, 28)
5619 22:56:06.588209 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5620 22:56:06.591899 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5621 22:56:06.592006
5622 22:56:06.594648 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5623 22:56:06.598078 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5624 22:56:06.601505 [Gating] SW calibration Done
5625 22:56:06.601612 ==
5626 22:56:06.604970 Dram Type= 6, Freq= 0, CH_1, rank 0
5627 22:56:06.608228 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5628 22:56:06.608340 ==
5629 22:56:06.611271 RX Vref Scan: 0
5630 22:56:06.611405
5631 22:56:06.611476 RX Vref 0 -> 0, step: 1
5632 22:56:06.611536
5633 22:56:06.614546 RX Delay -80 -> 252, step: 8
5634 22:56:06.617957 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5635 22:56:06.624672 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5636 22:56:06.628337 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5637 22:56:06.631642 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5638 22:56:06.634977 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5639 22:56:06.638151 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5640 22:56:06.641155 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5641 22:56:06.648521 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5642 22:56:06.651172 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5643 22:56:06.654814 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5644 22:56:06.657999 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5645 22:56:06.661335 iDelay=208, Bit 11, Center 95 (8 ~ 183) 176
5646 22:56:06.664644 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5647 22:56:06.671156 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5648 22:56:06.674280 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5649 22:56:06.677945 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5650 22:56:06.678062 ==
5651 22:56:06.681423 Dram Type= 6, Freq= 0, CH_1, rank 0
5652 22:56:06.684631 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5653 22:56:06.684739 ==
5654 22:56:06.687891 DQS Delay:
5655 22:56:06.687993 DQS0 = 0, DQS1 = 0
5656 22:56:06.690947 DQM Delay:
5657 22:56:06.691045 DQM0 = 102, DQM1 = 98
5658 22:56:06.691135 DQ Delay:
5659 22:56:06.694217 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5660 22:56:06.698022 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =103
5661 22:56:06.701041 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =95
5662 22:56:06.707635 DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =107
5663 22:56:06.707737
5664 22:56:06.707832
5665 22:56:06.707923 ==
5666 22:56:06.711388 Dram Type= 6, Freq= 0, CH_1, rank 0
5667 22:56:06.714267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5668 22:56:06.714368 ==
5669 22:56:06.714453
5670 22:56:06.714514
5671 22:56:06.717597 TX Vref Scan disable
5672 22:56:06.717711 == TX Byte 0 ==
5673 22:56:06.724444 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5674 22:56:06.727742 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5675 22:56:06.727846 == TX Byte 1 ==
5676 22:56:06.734166 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5677 22:56:06.737466 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5678 22:56:06.737581 ==
5679 22:56:06.740606 Dram Type= 6, Freq= 0, CH_1, rank 0
5680 22:56:06.744020 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5681 22:56:06.744122 ==
5682 22:56:06.744218
5683 22:56:06.747526
5684 22:56:06.747608 TX Vref Scan disable
5685 22:56:06.750708 == TX Byte 0 ==
5686 22:56:06.754009 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5687 22:56:06.757388 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5688 22:56:06.761112 == TX Byte 1 ==
5689 22:56:06.763813 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5690 22:56:06.767822 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5691 22:56:06.767896
5692 22:56:06.771118 [DATLAT]
5693 22:56:06.771216 Freq=933, CH1 RK0
5694 22:56:06.771335
5695 22:56:06.773894 DATLAT Default: 0xd
5696 22:56:06.773994 0, 0xFFFF, sum = 0
5697 22:56:06.777346 1, 0xFFFF, sum = 0
5698 22:56:06.777449 2, 0xFFFF, sum = 0
5699 22:56:06.780540 3, 0xFFFF, sum = 0
5700 22:56:06.780659 4, 0xFFFF, sum = 0
5701 22:56:06.784163 5, 0xFFFF, sum = 0
5702 22:56:06.784307 6, 0xFFFF, sum = 0
5703 22:56:06.787293 7, 0xFFFF, sum = 0
5704 22:56:06.790803 8, 0xFFFF, sum = 0
5705 22:56:06.790909 9, 0xFFFF, sum = 0
5706 22:56:06.791009 10, 0x0, sum = 1
5707 22:56:06.793628 11, 0x0, sum = 2
5708 22:56:06.793730 12, 0x0, sum = 3
5709 22:56:06.797310 13, 0x0, sum = 4
5710 22:56:06.797414 best_step = 11
5711 22:56:06.797507
5712 22:56:06.797594 ==
5713 22:56:06.800947 Dram Type= 6, Freq= 0, CH_1, rank 0
5714 22:56:06.807504 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5715 22:56:06.807604 ==
5716 22:56:06.807700 RX Vref Scan: 1
5717 22:56:06.807794
5718 22:56:06.810503 RX Vref 0 -> 0, step: 1
5719 22:56:06.810603
5720 22:56:06.813691 RX Delay -45 -> 252, step: 4
5721 22:56:06.813792
5722 22:56:06.817148 Set Vref, RX VrefLevel [Byte0]: 54
5723 22:56:06.820402 [Byte1]: 47
5724 22:56:06.820475
5725 22:56:06.824213 Final RX Vref Byte 0 = 54 to rank0
5726 22:56:06.827404 Final RX Vref Byte 1 = 47 to rank0
5727 22:56:06.830672 Final RX Vref Byte 0 = 54 to rank1
5728 22:56:06.834400 Final RX Vref Byte 1 = 47 to rank1==
5729 22:56:06.837305 Dram Type= 6, Freq= 0, CH_1, rank 0
5730 22:56:06.840556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5731 22:56:06.840741 ==
5732 22:56:06.844212 DQS Delay:
5733 22:56:06.844366 DQS0 = 0, DQS1 = 0
5734 22:56:06.847257 DQM Delay:
5735 22:56:06.847449 DQM0 = 103, DQM1 = 99
5736 22:56:06.847581 DQ Delay:
5737 22:56:06.850878 DQ0 =106, DQ1 =98, DQ2 =94, DQ3 =100
5738 22:56:06.853960 DQ4 =102, DQ5 =112, DQ6 =110, DQ7 =104
5739 22:56:06.857091 DQ8 =88, DQ9 =88, DQ10 =100, DQ11 =96
5740 22:56:06.864052 DQ12 =106, DQ13 =104, DQ14 =108, DQ15 =108
5741 22:56:06.864227
5742 22:56:06.864435
5743 22:56:06.870789 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a32, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 413 ps
5744 22:56:06.874652 CH1 RK0: MR19=505, MR18=1A32
5745 22:56:06.881115 CH1_RK0: MR19=0x505, MR18=0x1A32, DQSOSC=406, MR23=63, INC=65, DEC=43
5746 22:56:06.881544
5747 22:56:06.884660 ----->DramcWriteLeveling(PI) begin...
5748 22:56:06.885296 ==
5749 22:56:06.887620 Dram Type= 6, Freq= 0, CH_1, rank 1
5750 22:56:06.891359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5751 22:56:06.891806 ==
5752 22:56:06.894434 Write leveling (Byte 0): 29 => 29
5753 22:56:06.897649 Write leveling (Byte 1): 28 => 28
5754 22:56:06.901360 DramcWriteLeveling(PI) end<-----
5755 22:56:06.901877
5756 22:56:06.902214 ==
5757 22:56:06.904867 Dram Type= 6, Freq= 0, CH_1, rank 1
5758 22:56:06.907909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5759 22:56:06.908464 ==
5760 22:56:06.911374 [Gating] SW mode calibration
5761 22:56:06.917933 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5762 22:56:06.924503 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5763 22:56:06.928001 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5764 22:56:06.930756 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5765 22:56:06.937633 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5766 22:56:06.941410 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5767 22:56:06.944502 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5768 22:56:06.950993 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5769 22:56:06.954270 0 14 24 | B1->B0 | 2d2d 3333 | 0 0 | (1 1) (0 1)
5770 22:56:06.957909 0 14 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
5771 22:56:06.964626 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5772 22:56:06.967727 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5773 22:56:06.971213 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5774 22:56:06.977975 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5775 22:56:06.981085 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5776 22:56:06.984117 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5777 22:56:06.991100 0 15 24 | B1->B0 | 3c3c 2c2c | 0 0 | (0 0) (0 0)
5778 22:56:06.994864 0 15 28 | B1->B0 | 4646 4242 | 0 0 | (0 0) (0 0)
5779 22:56:06.997909 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5780 22:56:07.004474 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5781 22:56:07.008246 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5782 22:56:07.011414 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5783 22:56:07.014895 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5784 22:56:07.021362 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5785 22:56:07.024331 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5786 22:56:07.027859 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5787 22:56:07.034619 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5788 22:56:07.037878 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5789 22:56:07.041013 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5790 22:56:07.047679 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5791 22:56:07.051406 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5792 22:56:07.054483 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5793 22:56:07.061477 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5794 22:56:07.064553 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5795 22:56:07.067923 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5796 22:56:07.074316 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5797 22:56:07.077408 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5798 22:56:07.080891 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5799 22:56:07.087203 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5800 22:56:07.090566 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5801 22:56:07.094248 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5802 22:56:07.100415 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5803 22:56:07.100881 Total UI for P1: 0, mck2ui 16
5804 22:56:07.107418 best dqsien dly found for B0: ( 1, 2, 26)
5805 22:56:07.107974 Total UI for P1: 0, mck2ui 16
5806 22:56:07.114229 best dqsien dly found for B1: ( 1, 2, 24)
5807 22:56:07.117482 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5808 22:56:07.120647 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5809 22:56:07.121241
5810 22:56:07.124145 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5811 22:56:07.127404 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5812 22:56:07.130596 [Gating] SW calibration Done
5813 22:56:07.131059 ==
5814 22:56:07.134180 Dram Type= 6, Freq= 0, CH_1, rank 1
5815 22:56:07.137666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5816 22:56:07.138242 ==
5817 22:56:07.140778 RX Vref Scan: 0
5818 22:56:07.141240
5819 22:56:07.141608 RX Vref 0 -> 0, step: 1
5820 22:56:07.141954
5821 22:56:07.143804 RX Delay -80 -> 252, step: 8
5822 22:56:07.147016 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5823 22:56:07.153668 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5824 22:56:07.157111 iDelay=208, Bit 2, Center 87 (0 ~ 175) 176
5825 22:56:07.160040 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5826 22:56:07.164115 iDelay=208, Bit 4, Center 99 (16 ~ 183) 168
5827 22:56:07.167199 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5828 22:56:07.170207 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5829 22:56:07.177006 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5830 22:56:07.180173 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5831 22:56:07.183450 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5832 22:56:07.186581 iDelay=208, Bit 10, Center 103 (16 ~ 191) 176
5833 22:56:07.190201 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5834 22:56:07.193619 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5835 22:56:07.200463 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5836 22:56:07.203353 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5837 22:56:07.206920 iDelay=208, Bit 15, Center 103 (16 ~ 191) 176
5838 22:56:07.207695 ==
5839 22:56:07.210171 Dram Type= 6, Freq= 0, CH_1, rank 1
5840 22:56:07.214006 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5841 22:56:07.216882 ==
5842 22:56:07.217447 DQS Delay:
5843 22:56:07.217844 DQS0 = 0, DQS1 = 0
5844 22:56:07.220827 DQM Delay:
5845 22:56:07.221411 DQM0 = 102, DQM1 = 97
5846 22:56:07.223316 DQ Delay:
5847 22:56:07.227372 DQ0 =107, DQ1 =99, DQ2 =87, DQ3 =99
5848 22:56:07.227938 DQ4 =99, DQ5 =115, DQ6 =115, DQ7 =99
5849 22:56:07.233807 DQ8 =83, DQ9 =87, DQ10 =103, DQ11 =91
5850 22:56:07.236657 DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =103
5851 22:56:07.237220
5852 22:56:07.237587
5853 22:56:07.237924 ==
5854 22:56:07.239828 Dram Type= 6, Freq= 0, CH_1, rank 1
5855 22:56:07.243765 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5856 22:56:07.244329 ==
5857 22:56:07.244703
5858 22:56:07.245043
5859 22:56:07.246497 TX Vref Scan disable
5860 22:56:07.250447 == TX Byte 0 ==
5861 22:56:07.253184 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5862 22:56:07.256806 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5863 22:56:07.259912 == TX Byte 1 ==
5864 22:56:07.263475 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5865 22:56:07.266521 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5866 22:56:07.267026 ==
5867 22:56:07.270172 Dram Type= 6, Freq= 0, CH_1, rank 1
5868 22:56:07.273010 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5869 22:56:07.273499 ==
5870 22:56:07.276365
5871 22:56:07.276878
5872 22:56:07.277260 TX Vref Scan disable
5873 22:56:07.279674 == TX Byte 0 ==
5874 22:56:07.283024 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5875 22:56:07.286856 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5876 22:56:07.290036 == TX Byte 1 ==
5877 22:56:07.292765 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5878 22:56:07.296230 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5879 22:56:07.300019
5880 22:56:07.300484 [DATLAT]
5881 22:56:07.300994 Freq=933, CH1 RK1
5882 22:56:07.301455
5883 22:56:07.303160 DATLAT Default: 0xb
5884 22:56:07.303761 0, 0xFFFF, sum = 0
5885 22:56:07.306731 1, 0xFFFF, sum = 0
5886 22:56:07.307250 2, 0xFFFF, sum = 0
5887 22:56:07.309850 3, 0xFFFF, sum = 0
5888 22:56:07.310379 4, 0xFFFF, sum = 0
5889 22:56:07.313139 5, 0xFFFF, sum = 0
5890 22:56:07.316264 6, 0xFFFF, sum = 0
5891 22:56:07.316696 7, 0xFFFF, sum = 0
5892 22:56:07.319982 8, 0xFFFF, sum = 0
5893 22:56:07.320412 9, 0xFFFF, sum = 0
5894 22:56:07.323209 10, 0x0, sum = 1
5895 22:56:07.323813 11, 0x0, sum = 2
5896 22:56:07.324163 12, 0x0, sum = 3
5897 22:56:07.326307 13, 0x0, sum = 4
5898 22:56:07.326838 best_step = 11
5899 22:56:07.327179
5900 22:56:07.329638 ==
5901 22:56:07.332980 Dram Type= 6, Freq= 0, CH_1, rank 1
5902 22:56:07.336476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5903 22:56:07.337007 ==
5904 22:56:07.337350 RX Vref Scan: 0
5905 22:56:07.337666
5906 22:56:07.339439 RX Vref 0 -> 0, step: 1
5907 22:56:07.339889
5908 22:56:07.343057 RX Delay -53 -> 252, step: 4
5909 22:56:07.349607 iDelay=203, Bit 0, Center 110 (27 ~ 194) 168
5910 22:56:07.352655 iDelay=203, Bit 1, Center 100 (19 ~ 182) 164
5911 22:56:07.356254 iDelay=203, Bit 2, Center 94 (11 ~ 178) 168
5912 22:56:07.359977 iDelay=203, Bit 3, Center 100 (19 ~ 182) 164
5913 22:56:07.362899 iDelay=203, Bit 4, Center 100 (19 ~ 182) 164
5914 22:56:07.366183 iDelay=203, Bit 5, Center 118 (35 ~ 202) 168
5915 22:56:07.372850 iDelay=203, Bit 6, Center 114 (31 ~ 198) 168
5916 22:56:07.375699 iDelay=203, Bit 7, Center 104 (19 ~ 190) 172
5917 22:56:07.379973 iDelay=203, Bit 8, Center 88 (3 ~ 174) 172
5918 22:56:07.382532 iDelay=203, Bit 9, Center 88 (3 ~ 174) 172
5919 22:56:07.386110 iDelay=203, Bit 10, Center 98 (15 ~ 182) 168
5920 22:56:07.392189 iDelay=203, Bit 11, Center 92 (7 ~ 178) 172
5921 22:56:07.395786 iDelay=203, Bit 12, Center 106 (19 ~ 194) 176
5922 22:56:07.399001 iDelay=203, Bit 13, Center 102 (19 ~ 186) 168
5923 22:56:07.402727 iDelay=203, Bit 14, Center 102 (19 ~ 186) 168
5924 22:56:07.406039 iDelay=203, Bit 15, Center 108 (23 ~ 194) 172
5925 22:56:07.406616 ==
5926 22:56:07.409329 Dram Type= 6, Freq= 0, CH_1, rank 1
5927 22:56:07.416127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5928 22:56:07.416713 ==
5929 22:56:07.417090 DQS Delay:
5930 22:56:07.419216 DQS0 = 0, DQS1 = 0
5931 22:56:07.419721 DQM Delay:
5932 22:56:07.422373 DQM0 = 105, DQM1 = 98
5933 22:56:07.422960 DQ Delay:
5934 22:56:07.425644 DQ0 =110, DQ1 =100, DQ2 =94, DQ3 =100
5935 22:56:07.429099 DQ4 =100, DQ5 =118, DQ6 =114, DQ7 =104
5936 22:56:07.432219 DQ8 =88, DQ9 =88, DQ10 =98, DQ11 =92
5937 22:56:07.436153 DQ12 =106, DQ13 =102, DQ14 =102, DQ15 =108
5938 22:56:07.436720
5939 22:56:07.437092
5940 22:56:07.446021 [DQSOSCAuto] RK1, (LSB)MR18= 0x2cff, (MSB)MR19= 0x504, tDQSOscB0 = 422 ps tDQSOscB1 = 408 ps
5941 22:56:07.446600 CH1 RK1: MR19=504, MR18=2CFF
5942 22:56:07.453064 CH1_RK1: MR19=0x504, MR18=0x2CFF, DQSOSC=408, MR23=63, INC=65, DEC=43
5943 22:56:07.455990 [RxdqsGatingPostProcess] freq 933
5944 22:56:07.462830 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5945 22:56:07.465675 best DQS0 dly(2T, 0.5T) = (0, 10)
5946 22:56:07.469393 best DQS1 dly(2T, 0.5T) = (0, 10)
5947 22:56:07.472232 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5948 22:56:07.475447 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5949 22:56:07.475921 best DQS0 dly(2T, 0.5T) = (0, 10)
5950 22:56:07.478704 best DQS1 dly(2T, 0.5T) = (0, 10)
5951 22:56:07.482091 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5952 22:56:07.485729 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5953 22:56:07.488845 Pre-setting of DQS Precalculation
5954 22:56:07.495651 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5955 22:56:07.502236 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5956 22:56:07.508903 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5957 22:56:07.509481
5958 22:56:07.509853
5959 22:56:07.512598 [Calibration Summary] 1866 Mbps
5960 22:56:07.513069 CH 0, Rank 0
5961 22:56:07.515758 SW Impedance : PASS
5962 22:56:07.519204 DUTY Scan : NO K
5963 22:56:07.519706 ZQ Calibration : PASS
5964 22:56:07.522607 Jitter Meter : NO K
5965 22:56:07.525978 CBT Training : PASS
5966 22:56:07.526448 Write leveling : PASS
5967 22:56:07.528959 RX DQS gating : PASS
5968 22:56:07.529429 RX DQ/DQS(RDDQC) : PASS
5969 22:56:07.532210 TX DQ/DQS : PASS
5970 22:56:07.535475 RX DATLAT : PASS
5971 22:56:07.535942 RX DQ/DQS(Engine): PASS
5972 22:56:07.539414 TX OE : NO K
5973 22:56:07.539983 All Pass.
5974 22:56:07.540362
5975 22:56:07.541974 CH 0, Rank 1
5976 22:56:07.542441 SW Impedance : PASS
5977 22:56:07.545438 DUTY Scan : NO K
5978 22:56:07.548777 ZQ Calibration : PASS
5979 22:56:07.549250 Jitter Meter : NO K
5980 22:56:07.552291 CBT Training : PASS
5981 22:56:07.555661 Write leveling : PASS
5982 22:56:07.556134 RX DQS gating : PASS
5983 22:56:07.558656 RX DQ/DQS(RDDQC) : PASS
5984 22:56:07.562223 TX DQ/DQS : PASS
5985 22:56:07.562796 RX DATLAT : PASS
5986 22:56:07.565053 RX DQ/DQS(Engine): PASS
5987 22:56:07.568709 TX OE : NO K
5988 22:56:07.569281 All Pass.
5989 22:56:07.569659
5990 22:56:07.570005 CH 1, Rank 0
5991 22:56:07.571591 SW Impedance : PASS
5992 22:56:07.575546 DUTY Scan : NO K
5993 22:56:07.576116 ZQ Calibration : PASS
5994 22:56:07.578833 Jitter Meter : NO K
5995 22:56:07.581806 CBT Training : PASS
5996 22:56:07.582419 Write leveling : PASS
5997 22:56:07.584948 RX DQS gating : PASS
5998 22:56:07.588558 RX DQ/DQS(RDDQC) : PASS
5999 22:56:07.589330 TX DQ/DQS : PASS
6000 22:56:07.591639 RX DATLAT : PASS
6001 22:56:07.592107 RX DQ/DQS(Engine): PASS
6002 22:56:07.594887 TX OE : NO K
6003 22:56:07.595409 All Pass.
6004 22:56:07.595790
6005 22:56:07.598521 CH 1, Rank 1
6006 22:56:07.598984 SW Impedance : PASS
6007 22:56:07.601636 DUTY Scan : NO K
6008 22:56:07.605204 ZQ Calibration : PASS
6009 22:56:07.605766 Jitter Meter : NO K
6010 22:56:07.608067 CBT Training : PASS
6011 22:56:07.611478 Write leveling : PASS
6012 22:56:07.611945 RX DQS gating : PASS
6013 22:56:07.615236 RX DQ/DQS(RDDQC) : PASS
6014 22:56:07.618836 TX DQ/DQS : PASS
6015 22:56:07.619449 RX DATLAT : PASS
6016 22:56:07.622165 RX DQ/DQS(Engine): PASS
6017 22:56:07.625507 TX OE : NO K
6018 22:56:07.626071 All Pass.
6019 22:56:07.626441
6020 22:56:07.628469 DramC Write-DBI off
6021 22:56:07.628957 PER_BANK_REFRESH: Hybrid Mode
6022 22:56:07.631431 TX_TRACKING: ON
6023 22:56:07.638262 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6024 22:56:07.645350 [FAST_K] Save calibration result to emmc
6025 22:56:07.648193 dramc_set_vcore_voltage set vcore to 650000
6026 22:56:07.648755 Read voltage for 400, 6
6027 22:56:07.651807 Vio18 = 0
6028 22:56:07.652363 Vcore = 650000
6029 22:56:07.652760 Vdram = 0
6030 22:56:07.654702 Vddq = 0
6031 22:56:07.655225 Vmddr = 0
6032 22:56:07.658022 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6033 22:56:07.665085 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6034 22:56:07.668523 MEM_TYPE=3, freq_sel=20
6035 22:56:07.671527 sv_algorithm_assistance_LP4_800
6036 22:56:07.674899 ============ PULL DRAM RESETB DOWN ============
6037 22:56:07.678070 ========== PULL DRAM RESETB DOWN end =========
6038 22:56:07.681896 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6039 22:56:07.685424 ===================================
6040 22:56:07.688261 LPDDR4 DRAM CONFIGURATION
6041 22:56:07.691733 ===================================
6042 22:56:07.694964 EX_ROW_EN[0] = 0x0
6043 22:56:07.695572 EX_ROW_EN[1] = 0x0
6044 22:56:07.697834 LP4Y_EN = 0x0
6045 22:56:07.698296 WORK_FSP = 0x0
6046 22:56:07.701382 WL = 0x2
6047 22:56:07.701904 RL = 0x2
6048 22:56:07.704804 BL = 0x2
6049 22:56:07.705265 RPST = 0x0
6050 22:56:07.708242 RD_PRE = 0x0
6051 22:56:07.708706 WR_PRE = 0x1
6052 22:56:07.711386 WR_PST = 0x0
6053 22:56:07.711864 DBI_WR = 0x0
6054 22:56:07.714952 DBI_RD = 0x0
6055 22:56:07.715554 OTF = 0x1
6056 22:56:07.717937 ===================================
6057 22:56:07.721606 ===================================
6058 22:56:07.724572 ANA top config
6059 22:56:07.728450 ===================================
6060 22:56:07.731642 DLL_ASYNC_EN = 0
6061 22:56:07.732271 ALL_SLAVE_EN = 1
6062 22:56:07.734549 NEW_RANK_MODE = 1
6063 22:56:07.738473 DLL_IDLE_MODE = 1
6064 22:56:07.741531 LP45_APHY_COMB_EN = 1
6065 22:56:07.744638 TX_ODT_DIS = 1
6066 22:56:07.745208 NEW_8X_MODE = 1
6067 22:56:07.747789 ===================================
6068 22:56:07.751320 ===================================
6069 22:56:07.754960 data_rate = 800
6070 22:56:07.757923 CKR = 1
6071 22:56:07.761450 DQ_P2S_RATIO = 4
6072 22:56:07.764815 ===================================
6073 22:56:07.768104 CA_P2S_RATIO = 4
6074 22:56:07.768674 DQ_CA_OPEN = 0
6075 22:56:07.771741 DQ_SEMI_OPEN = 1
6076 22:56:07.774743 CA_SEMI_OPEN = 1
6077 22:56:07.778064 CA_FULL_RATE = 0
6078 22:56:07.781447 DQ_CKDIV4_EN = 0
6079 22:56:07.784967 CA_CKDIV4_EN = 1
6080 22:56:07.785532 CA_PREDIV_EN = 0
6081 22:56:07.788049 PH8_DLY = 0
6082 22:56:07.791435 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6083 22:56:07.794696 DQ_AAMCK_DIV = 0
6084 22:56:07.797473 CA_AAMCK_DIV = 0
6085 22:56:07.801599 CA_ADMCK_DIV = 4
6086 22:56:07.802167 DQ_TRACK_CA_EN = 0
6087 22:56:07.804282 CA_PICK = 800
6088 22:56:07.807713 CA_MCKIO = 400
6089 22:56:07.810822 MCKIO_SEMI = 400
6090 22:56:07.814683 PLL_FREQ = 3016
6091 22:56:07.817908 DQ_UI_PI_RATIO = 32
6092 22:56:07.821326 CA_UI_PI_RATIO = 32
6093 22:56:07.824387 ===================================
6094 22:56:07.827466 ===================================
6095 22:56:07.827938 memory_type:LPDDR4
6096 22:56:07.831106 GP_NUM : 10
6097 22:56:07.834474 SRAM_EN : 1
6098 22:56:07.835065 MD32_EN : 0
6099 22:56:07.837706 ===================================
6100 22:56:07.840894 [ANA_INIT] >>>>>>>>>>>>>>
6101 22:56:07.844335 <<<<<< [CONFIGURE PHASE]: ANA_TX
6102 22:56:07.847428 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6103 22:56:07.850922 ===================================
6104 22:56:07.854261 data_rate = 800,PCW = 0X7400
6105 22:56:07.857659 ===================================
6106 22:56:07.861080 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6107 22:56:07.864471 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6108 22:56:07.877735 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6109 22:56:07.881702 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6110 22:56:07.884588 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6111 22:56:07.887544 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6112 22:56:07.891166 [ANA_INIT] flow start
6113 22:56:07.894064 [ANA_INIT] PLL >>>>>>>>
6114 22:56:07.894534 [ANA_INIT] PLL <<<<<<<<
6115 22:56:07.897309 [ANA_INIT] MIDPI >>>>>>>>
6116 22:56:07.900979 [ANA_INIT] MIDPI <<<<<<<<
6117 22:56:07.901548 [ANA_INIT] DLL >>>>>>>>
6118 22:56:07.904572 [ANA_INIT] flow end
6119 22:56:07.907316 ============ LP4 DIFF to SE enter ============
6120 22:56:07.910799 ============ LP4 DIFF to SE exit ============
6121 22:56:07.914316 [ANA_INIT] <<<<<<<<<<<<<
6122 22:56:07.917976 [Flow] Enable top DCM control >>>>>
6123 22:56:07.921150 [Flow] Enable top DCM control <<<<<
6124 22:56:07.924408 Enable DLL master slave shuffle
6125 22:56:07.931281 ==============================================================
6126 22:56:07.931908 Gating Mode config
6127 22:56:07.937660 ==============================================================
6128 22:56:07.938133 Config description:
6129 22:56:07.947647 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6130 22:56:07.954420 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6131 22:56:07.961035 SELPH_MODE 0: By rank 1: By Phase
6132 22:56:07.964638 ==============================================================
6133 22:56:07.967470 GAT_TRACK_EN = 0
6134 22:56:07.970530 RX_GATING_MODE = 2
6135 22:56:07.974033 RX_GATING_TRACK_MODE = 2
6136 22:56:07.977776 SELPH_MODE = 1
6137 22:56:07.980946 PICG_EARLY_EN = 1
6138 22:56:07.983855 VALID_LAT_VALUE = 1
6139 22:56:07.987443 ==============================================================
6140 22:56:07.991014 Enter into Gating configuration >>>>
6141 22:56:07.993867 Exit from Gating configuration <<<<
6142 22:56:07.997612 Enter into DVFS_PRE_config >>>>>
6143 22:56:08.010898 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6144 22:56:08.014076 Exit from DVFS_PRE_config <<<<<
6145 22:56:08.017445 Enter into PICG configuration >>>>
6146 22:56:08.018041 Exit from PICG configuration <<<<
6147 22:56:08.020449 [RX_INPUT] configuration >>>>>
6148 22:56:08.024592 [RX_INPUT] configuration <<<<<
6149 22:56:08.030562 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6150 22:56:08.033663 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6151 22:56:08.040575 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6152 22:56:08.047186 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6153 22:56:08.053956 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6154 22:56:08.060633 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6155 22:56:08.063937 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6156 22:56:08.067206 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6157 22:56:08.070954 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6158 22:56:08.077484 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6159 22:56:08.080879 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6160 22:56:08.083856 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6161 22:56:08.087585 ===================================
6162 22:56:08.090950 LPDDR4 DRAM CONFIGURATION
6163 22:56:08.093907 ===================================
6164 22:56:08.096987 EX_ROW_EN[0] = 0x0
6165 22:56:08.097493 EX_ROW_EN[1] = 0x0
6166 22:56:08.100482 LP4Y_EN = 0x0
6167 22:56:08.101071 WORK_FSP = 0x0
6168 22:56:08.103638 WL = 0x2
6169 22:56:08.104081 RL = 0x2
6170 22:56:08.107095 BL = 0x2
6171 22:56:08.107619 RPST = 0x0
6172 22:56:08.110142 RD_PRE = 0x0
6173 22:56:08.110709 WR_PRE = 0x1
6174 22:56:08.113837 WR_PST = 0x0
6175 22:56:08.114409 DBI_WR = 0x0
6176 22:56:08.116661 DBI_RD = 0x0
6177 22:56:08.117113 OTF = 0x1
6178 22:56:08.120370 ===================================
6179 22:56:08.126852 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6180 22:56:08.130739 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6181 22:56:08.133598 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6182 22:56:08.136693 ===================================
6183 22:56:08.140405 LPDDR4 DRAM CONFIGURATION
6184 22:56:08.143702 ===================================
6185 22:56:08.146855 EX_ROW_EN[0] = 0x10
6186 22:56:08.147278 EX_ROW_EN[1] = 0x0
6187 22:56:08.150298 LP4Y_EN = 0x0
6188 22:56:08.150718 WORK_FSP = 0x0
6189 22:56:08.153537 WL = 0x2
6190 22:56:08.154135 RL = 0x2
6191 22:56:08.156453 BL = 0x2
6192 22:56:08.157167 RPST = 0x0
6193 22:56:08.160237 RD_PRE = 0x0
6194 22:56:08.160893 WR_PRE = 0x1
6195 22:56:08.163021 WR_PST = 0x0
6196 22:56:08.163714 DBI_WR = 0x0
6197 22:56:08.166435 DBI_RD = 0x0
6198 22:56:08.167056 OTF = 0x1
6199 22:56:08.170159 ===================================
6200 22:56:08.176371 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6201 22:56:08.181049 nWR fixed to 30
6202 22:56:08.184664 [ModeRegInit_LP4] CH0 RK0
6203 22:56:08.185288 [ModeRegInit_LP4] CH0 RK1
6204 22:56:08.187735 [ModeRegInit_LP4] CH1 RK0
6205 22:56:08.191151 [ModeRegInit_LP4] CH1 RK1
6206 22:56:08.191905 match AC timing 19
6207 22:56:08.197766 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6208 22:56:08.200728 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6209 22:56:08.204412 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6210 22:56:08.210954 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6211 22:56:08.214032 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6212 22:56:08.214481 ==
6213 22:56:08.217451 Dram Type= 6, Freq= 0, CH_0, rank 0
6214 22:56:08.220613 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6215 22:56:08.221053 ==
6216 22:56:08.227164 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6217 22:56:08.233464 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6218 22:56:08.237286 [CA 0] Center 36 (8~64) winsize 57
6219 22:56:08.240138 [CA 1] Center 36 (8~64) winsize 57
6220 22:56:08.243763 [CA 2] Center 36 (8~64) winsize 57
6221 22:56:08.246558 [CA 3] Center 36 (8~64) winsize 57
6222 22:56:08.250231 [CA 4] Center 36 (8~64) winsize 57
6223 22:56:08.250352 [CA 5] Center 36 (8~64) winsize 57
6224 22:56:08.253722
6225 22:56:08.257045 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6226 22:56:08.257152
6227 22:56:08.260219 [CATrainingPosCal] consider 1 rank data
6228 22:56:08.262998 u2DelayCellTimex100 = 270/100 ps
6229 22:56:08.266465 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6230 22:56:08.270204 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6231 22:56:08.273009 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6232 22:56:08.276828 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6233 22:56:08.279772 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6234 22:56:08.283276 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6235 22:56:08.283391
6236 22:56:08.286742 CA PerBit enable=1, Macro0, CA PI delay=36
6237 22:56:08.286851
6238 22:56:08.289675 [CBTSetCACLKResult] CA Dly = 36
6239 22:56:08.293157 CS Dly: 1 (0~32)
6240 22:56:08.293268 ==
6241 22:56:08.296027 Dram Type= 6, Freq= 0, CH_0, rank 1
6242 22:56:08.299151 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6243 22:56:08.299261 ==
6244 22:56:08.305894 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6245 22:56:08.313060 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6246 22:56:08.316021 [CA 0] Center 36 (8~64) winsize 57
6247 22:56:08.319591 [CA 1] Center 36 (8~64) winsize 57
6248 22:56:08.322901 [CA 2] Center 36 (8~64) winsize 57
6249 22:56:08.323006 [CA 3] Center 36 (8~64) winsize 57
6250 22:56:08.325806 [CA 4] Center 36 (8~64) winsize 57
6251 22:56:08.329121 [CA 5] Center 36 (8~64) winsize 57
6252 22:56:08.329225
6253 22:56:08.335820 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6254 22:56:08.335924
6255 22:56:08.338967 [CATrainingPosCal] consider 2 rank data
6256 22:56:08.339075 u2DelayCellTimex100 = 270/100 ps
6257 22:56:08.346083 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6258 22:56:08.349343 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6259 22:56:08.352470 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6260 22:56:08.355869 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6261 22:56:08.358907 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6262 22:56:08.362735 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6263 22:56:08.362842
6264 22:56:08.366010 CA PerBit enable=1, Macro0, CA PI delay=36
6265 22:56:08.366111
6266 22:56:08.368773 [CBTSetCACLKResult] CA Dly = 36
6267 22:56:08.372167 CS Dly: 1 (0~32)
6268 22:56:08.372267
6269 22:56:08.376034 ----->DramcWriteLeveling(PI) begin...
6270 22:56:08.376142 ==
6271 22:56:08.379283 Dram Type= 6, Freq= 0, CH_0, rank 0
6272 22:56:08.382204 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6273 22:56:08.382305 ==
6274 22:56:08.385522 Write leveling (Byte 0): 40 => 8
6275 22:56:08.388804 Write leveling (Byte 1): 40 => 8
6276 22:56:08.391821 DramcWriteLeveling(PI) end<-----
6277 22:56:08.391925
6278 22:56:08.392027 ==
6279 22:56:08.395453 Dram Type= 6, Freq= 0, CH_0, rank 0
6280 22:56:08.398538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6281 22:56:08.398647 ==
6282 22:56:08.402134 [Gating] SW mode calibration
6283 22:56:08.409009 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6284 22:56:08.415311 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6285 22:56:08.419034 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6286 22:56:08.421999 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6287 22:56:08.428729 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6288 22:56:08.432285 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6289 22:56:08.435823 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6290 22:56:08.442200 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6291 22:56:08.445239 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6292 22:56:08.448542 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6293 22:56:08.455302 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6294 22:56:08.455488 Total UI for P1: 0, mck2ui 16
6295 22:56:08.462438 best dqsien dly found for B0: ( 0, 14, 24)
6296 22:56:08.462521 Total UI for P1: 0, mck2ui 16
6297 22:56:08.468922 best dqsien dly found for B1: ( 0, 14, 24)
6298 22:56:08.471692 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6299 22:56:08.475001 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6300 22:56:08.475083
6301 22:56:08.478365 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6302 22:56:08.481700 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6303 22:56:08.485305 [Gating] SW calibration Done
6304 22:56:08.485387 ==
6305 22:56:08.488522 Dram Type= 6, Freq= 0, CH_0, rank 0
6306 22:56:08.491584 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6307 22:56:08.491667 ==
6308 22:56:08.495161 RX Vref Scan: 0
6309 22:56:08.495245
6310 22:56:08.495309 RX Vref 0 -> 0, step: 1
6311 22:56:08.495410
6312 22:56:08.498290 RX Delay -410 -> 252, step: 16
6313 22:56:08.505452 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6314 22:56:08.508263 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6315 22:56:08.511557 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6316 22:56:08.515040 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6317 22:56:08.521671 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6318 22:56:08.524726 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6319 22:56:08.528204 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6320 22:56:08.531800 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6321 22:56:08.538382 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6322 22:56:08.541506 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6323 22:56:08.544880 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6324 22:56:08.548320 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6325 22:56:08.554607 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6326 22:56:08.558147 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6327 22:56:08.561895 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6328 22:56:08.565372 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6329 22:56:08.565453 ==
6330 22:56:08.568031 Dram Type= 6, Freq= 0, CH_0, rank 0
6331 22:56:08.574817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6332 22:56:08.574898 ==
6333 22:56:08.574962 DQS Delay:
6334 22:56:08.578322 DQS0 = 27, DQS1 = 35
6335 22:56:08.578403 DQM Delay:
6336 22:56:08.581532 DQM0 = 10, DQM1 = 11
6337 22:56:08.581612 DQ Delay:
6338 22:56:08.584850 DQ0 =8, DQ1 =16, DQ2 =0, DQ3 =8
6339 22:56:08.588521 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =24
6340 22:56:08.588602 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6341 22:56:08.595121 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6342 22:56:08.595228
6343 22:56:08.595331
6344 22:56:08.595425 ==
6345 22:56:08.597927 Dram Type= 6, Freq= 0, CH_0, rank 0
6346 22:56:08.601490 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6347 22:56:08.601600 ==
6348 22:56:08.601693
6349 22:56:08.601797
6350 22:56:08.604376 TX Vref Scan disable
6351 22:56:08.604477 == TX Byte 0 ==
6352 22:56:08.611439 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6353 22:56:08.614706 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6354 22:56:08.614803 == TX Byte 1 ==
6355 22:56:08.618066 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6356 22:56:08.624818 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6357 22:56:08.624899 ==
6358 22:56:08.628276 Dram Type= 6, Freq= 0, CH_0, rank 0
6359 22:56:08.631225 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6360 22:56:08.631306 ==
6361 22:56:08.631413
6362 22:56:08.631472
6363 22:56:08.634448 TX Vref Scan disable
6364 22:56:08.634528 == TX Byte 0 ==
6365 22:56:08.641564 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6366 22:56:08.644674 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6367 22:56:08.644755 == TX Byte 1 ==
6368 22:56:08.647908 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6369 22:56:08.654835 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6370 22:56:08.654916
6371 22:56:08.654979 [DATLAT]
6372 22:56:08.658127 Freq=400, CH0 RK0
6373 22:56:08.658207
6374 22:56:08.658270 DATLAT Default: 0xf
6375 22:56:08.661495 0, 0xFFFF, sum = 0
6376 22:56:08.661577 1, 0xFFFF, sum = 0
6377 22:56:08.664832 2, 0xFFFF, sum = 0
6378 22:56:08.664914 3, 0xFFFF, sum = 0
6379 22:56:08.668223 4, 0xFFFF, sum = 0
6380 22:56:08.668304 5, 0xFFFF, sum = 0
6381 22:56:08.671352 6, 0xFFFF, sum = 0
6382 22:56:08.671434 7, 0xFFFF, sum = 0
6383 22:56:08.674867 8, 0xFFFF, sum = 0
6384 22:56:08.674948 9, 0xFFFF, sum = 0
6385 22:56:08.677801 10, 0xFFFF, sum = 0
6386 22:56:08.677925 11, 0xFFFF, sum = 0
6387 22:56:08.681083 12, 0xFFFF, sum = 0
6388 22:56:08.681168 13, 0x0, sum = 1
6389 22:56:08.684449 14, 0x0, sum = 2
6390 22:56:08.684533 15, 0x0, sum = 3
6391 22:56:08.687819 16, 0x0, sum = 4
6392 22:56:08.687902 best_step = 14
6393 22:56:08.687968
6394 22:56:08.688029 ==
6395 22:56:08.691128 Dram Type= 6, Freq= 0, CH_0, rank 0
6396 22:56:08.698009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6397 22:56:08.698094 ==
6398 22:56:08.698160 RX Vref Scan: 1
6399 22:56:08.698223
6400 22:56:08.701199 RX Vref 0 -> 0, step: 1
6401 22:56:08.701282
6402 22:56:08.704767 RX Delay -311 -> 252, step: 8
6403 22:56:08.704850
6404 22:56:08.707886 Set Vref, RX VrefLevel [Byte0]: 56
6405 22:56:08.711127 [Byte1]: 48
6406 22:56:08.711209
6407 22:56:08.714734 Final RX Vref Byte 0 = 56 to rank0
6408 22:56:08.717701 Final RX Vref Byte 1 = 48 to rank0
6409 22:56:08.721114 Final RX Vref Byte 0 = 56 to rank1
6410 22:56:08.724893 Final RX Vref Byte 1 = 48 to rank1==
6411 22:56:08.727884 Dram Type= 6, Freq= 0, CH_0, rank 0
6412 22:56:08.731335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6413 22:56:08.731432 ==
6414 22:56:08.734538 DQS Delay:
6415 22:56:08.734621 DQS0 = 28, DQS1 = 36
6416 22:56:08.738137 DQM Delay:
6417 22:56:08.738224 DQM0 = 11, DQM1 = 13
6418 22:56:08.738289 DQ Delay:
6419 22:56:08.741224 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6420 22:56:08.744845 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6421 22:56:08.747903 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6422 22:56:08.750875 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6423 22:56:08.750958
6424 22:56:08.751024
6425 22:56:08.761078 [DQSOSCAuto] RK0, (LSB)MR18= 0xceba, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 384 ps
6426 22:56:08.764320 CH0 RK0: MR19=C0C, MR18=CEBA
6427 22:56:08.768016 CH0_RK0: MR19=0xC0C, MR18=0xCEBA, DQSOSC=384, MR23=63, INC=400, DEC=267
6428 22:56:08.771106 ==
6429 22:56:08.774508 Dram Type= 6, Freq= 0, CH_0, rank 1
6430 22:56:08.777704 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6431 22:56:08.777787 ==
6432 22:56:08.780964 [Gating] SW mode calibration
6433 22:56:08.788296 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6434 22:56:08.790990 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6435 22:56:08.797510 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6436 22:56:08.801349 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6437 22:56:08.804168 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6438 22:56:08.811174 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6439 22:56:08.814693 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6440 22:56:08.817476 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6441 22:56:08.824318 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6442 22:56:08.827749 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6443 22:56:08.830784 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6444 22:56:08.834365 Total UI for P1: 0, mck2ui 16
6445 22:56:08.837720 best dqsien dly found for B0: ( 0, 14, 24)
6446 22:56:08.840843 Total UI for P1: 0, mck2ui 16
6447 22:56:08.844372 best dqsien dly found for B1: ( 0, 14, 24)
6448 22:56:08.848191 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6449 22:56:08.850969 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6450 22:56:08.851065
6451 22:56:08.854738 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6452 22:56:08.861164 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6453 22:56:08.861263 [Gating] SW calibration Done
6454 22:56:08.861354 ==
6455 22:56:08.864265 Dram Type= 6, Freq= 0, CH_0, rank 1
6456 22:56:08.871068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6457 22:56:08.871172 ==
6458 22:56:08.871263 RX Vref Scan: 0
6459 22:56:08.871362
6460 22:56:08.874166 RX Vref 0 -> 0, step: 1
6461 22:56:08.874260
6462 22:56:08.877460 RX Delay -410 -> 252, step: 16
6463 22:56:08.881210 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6464 22:56:08.884613 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6465 22:56:08.890729 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6466 22:56:08.893887 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6467 22:56:08.897478 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6468 22:56:08.900748 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6469 22:56:08.907635 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6470 22:56:08.910806 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6471 22:56:08.914120 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6472 22:56:08.917895 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6473 22:56:08.924265 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6474 22:56:08.927416 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6475 22:56:08.930890 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6476 22:56:08.933993 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6477 22:56:08.940897 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6478 22:56:08.943815 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6479 22:56:08.943987 ==
6480 22:56:08.947363 Dram Type= 6, Freq= 0, CH_0, rank 1
6481 22:56:08.951063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6482 22:56:08.951303 ==
6483 22:56:08.954242 DQS Delay:
6484 22:56:08.954480 DQS0 = 27, DQS1 = 35
6485 22:56:08.957269 DQM Delay:
6486 22:56:08.957563 DQM0 = 12, DQM1 = 10
6487 22:56:08.957796 DQ Delay:
6488 22:56:08.960650 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6489 22:56:08.964031 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6490 22:56:08.967088 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6491 22:56:08.970571 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6492 22:56:08.970987
6493 22:56:08.971316
6494 22:56:08.971658 ==
6495 22:56:08.973982 Dram Type= 6, Freq= 0, CH_0, rank 1
6496 22:56:08.980569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6497 22:56:08.980989 ==
6498 22:56:08.981319
6499 22:56:08.981625
6500 22:56:08.981919 TX Vref Scan disable
6501 22:56:08.984174 == TX Byte 0 ==
6502 22:56:08.987440 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6503 22:56:08.991016 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6504 22:56:08.993727 == TX Byte 1 ==
6505 22:56:08.997180 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6506 22:56:09.000317 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6507 22:56:09.000738 ==
6508 22:56:09.003776 Dram Type= 6, Freq= 0, CH_0, rank 1
6509 22:56:09.010497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6510 22:56:09.011018 ==
6511 22:56:09.011403
6512 22:56:09.011723
6513 22:56:09.012023 TX Vref Scan disable
6514 22:56:09.013821 == TX Byte 0 ==
6515 22:56:09.017657 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6516 22:56:09.020557 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6517 22:56:09.024225 == TX Byte 1 ==
6518 22:56:09.027077 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6519 22:56:09.031025 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6520 22:56:09.031663
6521 22:56:09.034288 [DATLAT]
6522 22:56:09.034855 Freq=400, CH0 RK1
6523 22:56:09.035230
6524 22:56:09.037328 DATLAT Default: 0xe
6525 22:56:09.037832 0, 0xFFFF, sum = 0
6526 22:56:09.040730 1, 0xFFFF, sum = 0
6527 22:56:09.041312 2, 0xFFFF, sum = 0
6528 22:56:09.043882 3, 0xFFFF, sum = 0
6529 22:56:09.044450 4, 0xFFFF, sum = 0
6530 22:56:09.047559 5, 0xFFFF, sum = 0
6531 22:56:09.048033 6, 0xFFFF, sum = 0
6532 22:56:09.050720 7, 0xFFFF, sum = 0
6533 22:56:09.051245 8, 0xFFFF, sum = 0
6534 22:56:09.053797 9, 0xFFFF, sum = 0
6535 22:56:09.054362 10, 0xFFFF, sum = 0
6536 22:56:09.057153 11, 0xFFFF, sum = 0
6537 22:56:09.060468 12, 0xFFFF, sum = 0
6538 22:56:09.061032 13, 0x0, sum = 1
6539 22:56:09.061412 14, 0x0, sum = 2
6540 22:56:09.063890 15, 0x0, sum = 3
6541 22:56:09.064466 16, 0x0, sum = 4
6542 22:56:09.067589 best_step = 14
6543 22:56:09.068143
6544 22:56:09.068516 ==
6545 22:56:09.070468 Dram Type= 6, Freq= 0, CH_0, rank 1
6546 22:56:09.074124 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6547 22:56:09.074686 ==
6548 22:56:09.077009 RX Vref Scan: 0
6549 22:56:09.077566
6550 22:56:09.077937 RX Vref 0 -> 0, step: 1
6551 22:56:09.078295
6552 22:56:09.080472 RX Delay -311 -> 252, step: 8
6553 22:56:09.089058 iDelay=217, Bit 0, Center -20 (-247 ~ 208) 456
6554 22:56:09.091636 iDelay=217, Bit 1, Center -12 (-231 ~ 208) 440
6555 22:56:09.094804 iDelay=217, Bit 2, Center -20 (-247 ~ 208) 456
6556 22:56:09.101492 iDelay=217, Bit 3, Center -20 (-247 ~ 208) 456
6557 22:56:09.105058 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6558 22:56:09.108070 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6559 22:56:09.111778 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6560 22:56:09.114947 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6561 22:56:09.121794 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6562 22:56:09.125155 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6563 22:56:09.128277 iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440
6564 22:56:09.131883 iDelay=217, Bit 11, Center -28 (-247 ~ 192) 440
6565 22:56:09.138392 iDelay=217, Bit 12, Center -20 (-239 ~ 200) 440
6566 22:56:09.141662 iDelay=217, Bit 13, Center -16 (-231 ~ 200) 432
6567 22:56:09.144947 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440
6568 22:56:09.151811 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6569 22:56:09.152358 ==
6570 22:56:09.155424 Dram Type= 6, Freq= 0, CH_0, rank 1
6571 22:56:09.158294 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6572 22:56:09.158781 ==
6573 22:56:09.159155 DQS Delay:
6574 22:56:09.162100 DQS0 = 24, DQS1 = 32
6575 22:56:09.162657 DQM Delay:
6576 22:56:09.164722 DQM0 = 7, DQM1 = 10
6577 22:56:09.165182 DQ Delay:
6578 22:56:09.168656 DQ0 =4, DQ1 =12, DQ2 =4, DQ3 =4
6579 22:56:09.171625 DQ4 =8, DQ5 =0, DQ6 =12, DQ7 =16
6580 22:56:09.175452 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6581 22:56:09.178408 DQ12 =12, DQ13 =16, DQ14 =20, DQ15 =16
6582 22:56:09.178992
6583 22:56:09.179418
6584 22:56:09.184837 [DQSOSCAuto] RK1, (LSB)MR18= 0xbf5d, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 386 ps
6585 22:56:09.188135 CH0 RK1: MR19=C0C, MR18=BF5D
6586 22:56:09.195215 CH0_RK1: MR19=0xC0C, MR18=0xBF5D, DQSOSC=386, MR23=63, INC=396, DEC=264
6587 22:56:09.198243 [RxdqsGatingPostProcess] freq 400
6588 22:56:09.201478 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6589 22:56:09.204755 best DQS0 dly(2T, 0.5T) = (0, 10)
6590 22:56:09.208026 best DQS1 dly(2T, 0.5T) = (0, 10)
6591 22:56:09.211403 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6592 22:56:09.214481 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6593 22:56:09.217997 best DQS0 dly(2T, 0.5T) = (0, 10)
6594 22:56:09.221728 best DQS1 dly(2T, 0.5T) = (0, 10)
6595 22:56:09.224488 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6596 22:56:09.227960 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6597 22:56:09.231304 Pre-setting of DQS Precalculation
6598 22:56:09.234444 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6599 22:56:09.238391 ==
6600 22:56:09.238963 Dram Type= 6, Freq= 0, CH_1, rank 0
6601 22:56:09.244990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6602 22:56:09.245577 ==
6603 22:56:09.248267 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6604 22:56:09.254703 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6605 22:56:09.258218 [CA 0] Center 36 (8~64) winsize 57
6606 22:56:09.260963 [CA 1] Center 36 (8~64) winsize 57
6607 22:56:09.264339 [CA 2] Center 36 (8~64) winsize 57
6608 22:56:09.268105 [CA 3] Center 36 (8~64) winsize 57
6609 22:56:09.271556 [CA 4] Center 36 (8~64) winsize 57
6610 22:56:09.274871 [CA 5] Center 36 (8~64) winsize 57
6611 22:56:09.275474
6612 22:56:09.278232 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6613 22:56:09.278696
6614 22:56:09.281194 [CATrainingPosCal] consider 1 rank data
6615 22:56:09.284941 u2DelayCellTimex100 = 270/100 ps
6616 22:56:09.288323 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6617 22:56:09.291618 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6618 22:56:09.294872 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6619 22:56:09.297595 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6620 22:56:09.301194 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6621 22:56:09.307939 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6622 22:56:09.308503
6623 22:56:09.311286 CA PerBit enable=1, Macro0, CA PI delay=36
6624 22:56:09.311928
6625 22:56:09.314710 [CBTSetCACLKResult] CA Dly = 36
6626 22:56:09.315417 CS Dly: 1 (0~32)
6627 22:56:09.315804 ==
6628 22:56:09.318080 Dram Type= 6, Freq= 0, CH_1, rank 1
6629 22:56:09.321094 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6630 22:56:09.324412 ==
6631 22:56:09.327777 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6632 22:56:09.334448 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6633 22:56:09.337940 [CA 0] Center 36 (8~64) winsize 57
6634 22:56:09.341091 [CA 1] Center 36 (8~64) winsize 57
6635 22:56:09.344130 [CA 2] Center 36 (8~64) winsize 57
6636 22:56:09.347698 [CA 3] Center 36 (8~64) winsize 57
6637 22:56:09.351363 [CA 4] Center 36 (8~64) winsize 57
6638 22:56:09.354837 [CA 5] Center 36 (8~64) winsize 57
6639 22:56:09.355446
6640 22:56:09.357721 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6641 22:56:09.358185
6642 22:56:09.361115 [CATrainingPosCal] consider 2 rank data
6643 22:56:09.364715 u2DelayCellTimex100 = 270/100 ps
6644 22:56:09.367449 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6645 22:56:09.371416 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6646 22:56:09.374697 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6647 22:56:09.378307 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6648 22:56:09.380895 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6649 22:56:09.384742 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6650 22:56:09.385317
6651 22:56:09.388248 CA PerBit enable=1, Macro0, CA PI delay=36
6652 22:56:09.388815
6653 22:56:09.391401 [CBTSetCACLKResult] CA Dly = 36
6654 22:56:09.394403 CS Dly: 1 (0~32)
6655 22:56:09.394976
6656 22:56:09.397691 ----->DramcWriteLeveling(PI) begin...
6657 22:56:09.398165 ==
6658 22:56:09.401268 Dram Type= 6, Freq= 0, CH_1, rank 0
6659 22:56:09.404071 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6660 22:56:09.404704 ==
6661 22:56:09.407869 Write leveling (Byte 0): 40 => 8
6662 22:56:09.411032 Write leveling (Byte 1): 40 => 8
6663 22:56:09.414317 DramcWriteLeveling(PI) end<-----
6664 22:56:09.414780
6665 22:56:09.415145 ==
6666 22:56:09.417357 Dram Type= 6, Freq= 0, CH_1, rank 0
6667 22:56:09.420595 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6668 22:56:09.421065 ==
6669 22:56:09.424071 [Gating] SW mode calibration
6670 22:56:09.430435 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6671 22:56:09.437868 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6672 22:56:09.440532 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6673 22:56:09.447305 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6674 22:56:09.450445 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6675 22:56:09.454141 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6676 22:56:09.457592 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6677 22:56:09.464279 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6678 22:56:09.468012 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6679 22:56:09.470874 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6680 22:56:09.477213 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6681 22:56:09.480862 Total UI for P1: 0, mck2ui 16
6682 22:56:09.484407 best dqsien dly found for B0: ( 0, 14, 24)
6683 22:56:09.487357 Total UI for P1: 0, mck2ui 16
6684 22:56:09.491053 best dqsien dly found for B1: ( 0, 14, 24)
6685 22:56:09.493773 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6686 22:56:09.496949 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6687 22:56:09.497577
6688 22:56:09.500680 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6689 22:56:09.503730 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6690 22:56:09.507483 [Gating] SW calibration Done
6691 22:56:09.508054 ==
6692 22:56:09.510751 Dram Type= 6, Freq= 0, CH_1, rank 0
6693 22:56:09.514117 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6694 22:56:09.514703 ==
6695 22:56:09.517024 RX Vref Scan: 0
6696 22:56:09.517597
6697 22:56:09.520337 RX Vref 0 -> 0, step: 1
6698 22:56:09.520810
6699 22:56:09.521180 RX Delay -410 -> 252, step: 16
6700 22:56:09.526949 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6701 22:56:09.530435 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6702 22:56:09.533661 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6703 22:56:09.536954 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6704 22:56:09.543627 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6705 22:56:09.547078 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6706 22:56:09.550534 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6707 22:56:09.553660 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6708 22:56:09.560008 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6709 22:56:09.563936 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6710 22:56:09.566903 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6711 22:56:09.573847 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6712 22:56:09.577261 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6713 22:56:09.580473 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6714 22:56:09.583638 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6715 22:56:09.590428 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6716 22:56:09.590986 ==
6717 22:56:09.593625 Dram Type= 6, Freq= 0, CH_1, rank 0
6718 22:56:09.596820 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6719 22:56:09.597294 ==
6720 22:56:09.597666 DQS Delay:
6721 22:56:09.599961 DQS0 = 35, DQS1 = 35
6722 22:56:09.600430 DQM Delay:
6723 22:56:09.603439 DQM0 = 18, DQM1 = 13
6724 22:56:09.603912 DQ Delay:
6725 22:56:09.606865 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6726 22:56:09.610488 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6727 22:56:09.613612 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6728 22:56:09.616752 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6729 22:56:09.617224
6730 22:56:09.617598
6731 22:56:09.618189 ==
6732 22:56:09.619760 Dram Type= 6, Freq= 0, CH_1, rank 0
6733 22:56:09.623260 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6734 22:56:09.623895 ==
6735 22:56:09.624275
6736 22:56:09.624621
6737 22:56:09.626548 TX Vref Scan disable
6738 22:56:09.630263 == TX Byte 0 ==
6739 22:56:09.633272 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6740 22:56:09.636862 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6741 22:56:09.640079 == TX Byte 1 ==
6742 22:56:09.643473 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6743 22:56:09.647021 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6744 22:56:09.647699 ==
6745 22:56:09.650103 Dram Type= 6, Freq= 0, CH_1, rank 0
6746 22:56:09.653428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6747 22:56:09.654106 ==
6748 22:56:09.654632
6749 22:56:09.656708
6750 22:56:09.657175 TX Vref Scan disable
6751 22:56:09.659890 == TX Byte 0 ==
6752 22:56:09.663118 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6753 22:56:09.666424 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6754 22:56:09.670363 == TX Byte 1 ==
6755 22:56:09.673311 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6756 22:56:09.676368 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6757 22:56:09.676937
6758 22:56:09.677311 [DATLAT]
6759 22:56:09.679605 Freq=400, CH1 RK0
6760 22:56:09.680179
6761 22:56:09.680565 DATLAT Default: 0xf
6762 22:56:09.682654 0, 0xFFFF, sum = 0
6763 22:56:09.683131 1, 0xFFFF, sum = 0
6764 22:56:09.686661 2, 0xFFFF, sum = 0
6765 22:56:09.689548 3, 0xFFFF, sum = 0
6766 22:56:09.690045 4, 0xFFFF, sum = 0
6767 22:56:09.692970 5, 0xFFFF, sum = 0
6768 22:56:09.693446 6, 0xFFFF, sum = 0
6769 22:56:09.696270 7, 0xFFFF, sum = 0
6770 22:56:09.696747 8, 0xFFFF, sum = 0
6771 22:56:09.699712 9, 0xFFFF, sum = 0
6772 22:56:09.700187 10, 0xFFFF, sum = 0
6773 22:56:09.702731 11, 0xFFFF, sum = 0
6774 22:56:09.703205 12, 0xFFFF, sum = 0
6775 22:56:09.706631 13, 0x0, sum = 1
6776 22:56:09.707107 14, 0x0, sum = 2
6777 22:56:09.709345 15, 0x0, sum = 3
6778 22:56:09.709821 16, 0x0, sum = 4
6779 22:56:09.713100 best_step = 14
6780 22:56:09.713568
6781 22:56:09.713932 ==
6782 22:56:09.716136 Dram Type= 6, Freq= 0, CH_1, rank 0
6783 22:56:09.719796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6784 22:56:09.720224 ==
6785 22:56:09.720636 RX Vref Scan: 1
6786 22:56:09.723254
6787 22:56:09.723720 RX Vref 0 -> 0, step: 1
6788 22:56:09.724058
6789 22:56:09.726399 RX Delay -311 -> 252, step: 8
6790 22:56:09.726844
6791 22:56:09.729822 Set Vref, RX VrefLevel [Byte0]: 54
6792 22:56:09.732986 [Byte1]: 47
6793 22:56:09.736346
6794 22:56:09.736908 Final RX Vref Byte 0 = 54 to rank0
6795 22:56:09.739886 Final RX Vref Byte 1 = 47 to rank0
6796 22:56:09.743521 Final RX Vref Byte 0 = 54 to rank1
6797 22:56:09.746401 Final RX Vref Byte 1 = 47 to rank1==
6798 22:56:09.749670 Dram Type= 6, Freq= 0, CH_1, rank 0
6799 22:56:09.756359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6800 22:56:09.756908 ==
6801 22:56:09.757409 DQS Delay:
6802 22:56:09.757919 DQS0 = 32, DQS1 = 32
6803 22:56:09.759853 DQM Delay:
6804 22:56:09.760377 DQM0 = 13, DQM1 = 11
6805 22:56:09.763711 DQ Delay:
6806 22:56:09.766307 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =16
6807 22:56:09.766913 DQ4 =12, DQ5 =24, DQ6 =20, DQ7 =12
6808 22:56:09.769511 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6809 22:56:09.772875 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
6810 22:56:09.773298
6811 22:56:09.776383
6812 22:56:09.782982 [DQSOSCAuto] RK0, (LSB)MR18= 0x93cb, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 391 ps
6813 22:56:09.786545 CH1 RK0: MR19=C0C, MR18=93CB
6814 22:56:09.792980 CH1_RK0: MR19=0xC0C, MR18=0x93CB, DQSOSC=384, MR23=63, INC=400, DEC=267
6815 22:56:09.793400 ==
6816 22:56:09.796323 Dram Type= 6, Freq= 0, CH_1, rank 1
6817 22:56:09.799447 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6818 22:56:09.799559 ==
6819 22:56:09.802449 [Gating] SW mode calibration
6820 22:56:09.809512 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6821 22:56:09.816134 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6822 22:56:09.819106 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6823 22:56:09.822788 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6824 22:56:09.828976 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6825 22:56:09.832673 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6826 22:56:09.835696 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6827 22:56:09.839080 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6828 22:56:09.845479 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6829 22:56:09.849001 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6830 22:56:09.855600 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6831 22:56:09.855680 Total UI for P1: 0, mck2ui 16
6832 22:56:09.859106 best dqsien dly found for B0: ( 0, 14, 24)
6833 22:56:09.862318 Total UI for P1: 0, mck2ui 16
6834 22:56:09.865562 best dqsien dly found for B1: ( 0, 14, 24)
6835 22:56:09.869094 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6836 22:56:09.875709 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6837 22:56:09.875796
6838 22:56:09.878497 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6839 22:56:09.882029 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6840 22:56:09.885721 [Gating] SW calibration Done
6841 22:56:09.885794 ==
6842 22:56:09.888516 Dram Type= 6, Freq= 0, CH_1, rank 1
6843 22:56:09.892154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6844 22:56:09.892226 ==
6845 22:56:09.895196 RX Vref Scan: 0
6846 22:56:09.895263
6847 22:56:09.895329 RX Vref 0 -> 0, step: 1
6848 22:56:09.895397
6849 22:56:09.898969 RX Delay -410 -> 252, step: 16
6850 22:56:09.901962 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6851 22:56:09.908705 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6852 22:56:09.912163 iDelay=230, Bit 2, Center -27 (-250 ~ 197) 448
6853 22:56:09.915104 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6854 22:56:09.918641 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6855 22:56:09.925636 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6856 22:56:09.929400 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6857 22:56:09.932315 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6858 22:56:09.935732 iDelay=230, Bit 8, Center -27 (-250 ~ 197) 448
6859 22:56:09.942412 iDelay=230, Bit 9, Center -27 (-250 ~ 197) 448
6860 22:56:09.945629 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6861 22:56:09.949120 iDelay=230, Bit 11, Center -19 (-250 ~ 213) 464
6862 22:56:09.952371 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6863 22:56:09.959057 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6864 22:56:09.962321 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6865 22:56:09.965704 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6866 22:56:09.966263 ==
6867 22:56:09.968596 Dram Type= 6, Freq= 0, CH_1, rank 1
6868 22:56:09.975500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6869 22:56:09.975924 ==
6870 22:56:09.976256 DQS Delay:
6871 22:56:09.978837 DQS0 = 27, DQS1 = 27
6872 22:56:09.979280 DQM Delay:
6873 22:56:09.979685 DQM0 = 11, DQM1 = 8
6874 22:56:09.982107 DQ Delay:
6875 22:56:09.985597 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6876 22:56:09.986128 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6877 22:56:09.989091 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6878 22:56:09.992583 DQ12 =16, DQ13 =8, DQ14 =8, DQ15 =16
6879 22:56:09.993099
6880 22:56:09.993431
6881 22:56:09.995221 ==
6882 22:56:09.995685 Dram Type= 6, Freq= 0, CH_1, rank 1
6883 22:56:10.001862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6884 22:56:10.002338 ==
6885 22:56:10.002776
6886 22:56:10.003177
6887 22:56:10.005620 TX Vref Scan disable
6888 22:56:10.006047 == TX Byte 0 ==
6889 22:56:10.009356 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6890 22:56:10.012520 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6891 22:56:10.015399 == TX Byte 1 ==
6892 22:56:10.018598 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6893 22:56:10.021884 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6894 22:56:10.025863 ==
6895 22:56:10.028562 Dram Type= 6, Freq= 0, CH_1, rank 1
6896 22:56:10.032547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6897 22:56:10.033082 ==
6898 22:56:10.033520
6899 22:56:10.033923
6900 22:56:10.035290 TX Vref Scan disable
6901 22:56:10.035750 == TX Byte 0 ==
6902 22:56:10.038454 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6903 22:56:10.044860 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6904 22:56:10.045297 == TX Byte 1 ==
6905 22:56:10.048873 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6906 22:56:10.055694 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6907 22:56:10.056238
6908 22:56:10.056582 [DATLAT]
6909 22:56:10.056893 Freq=400, CH1 RK1
6910 22:56:10.057192
6911 22:56:10.058385 DATLAT Default: 0xe
6912 22:56:10.058802 0, 0xFFFF, sum = 0
6913 22:56:10.061860 1, 0xFFFF, sum = 0
6914 22:56:10.062342 2, 0xFFFF, sum = 0
6915 22:56:10.065077 3, 0xFFFF, sum = 0
6916 22:56:10.068201 4, 0xFFFF, sum = 0
6917 22:56:10.068764 5, 0xFFFF, sum = 0
6918 22:56:10.072091 6, 0xFFFF, sum = 0
6919 22:56:10.072512 7, 0xFFFF, sum = 0
6920 22:56:10.075364 8, 0xFFFF, sum = 0
6921 22:56:10.075887 9, 0xFFFF, sum = 0
6922 22:56:10.078825 10, 0xFFFF, sum = 0
6923 22:56:10.079249 11, 0xFFFF, sum = 0
6924 22:56:10.081924 12, 0xFFFF, sum = 0
6925 22:56:10.082455 13, 0x0, sum = 1
6926 22:56:10.085218 14, 0x0, sum = 2
6927 22:56:10.085641 15, 0x0, sum = 3
6928 22:56:10.088175 16, 0x0, sum = 4
6929 22:56:10.088679 best_step = 14
6930 22:56:10.089018
6931 22:56:10.089334 ==
6932 22:56:10.091914 Dram Type= 6, Freq= 0, CH_1, rank 1
6933 22:56:10.095171 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6934 22:56:10.095781 ==
6935 22:56:10.098328 RX Vref Scan: 0
6936 22:56:10.098852
6937 22:56:10.101471 RX Vref 0 -> 0, step: 1
6938 22:56:10.101940
6939 22:56:10.102310 RX Delay -295 -> 252, step: 8
6940 22:56:10.110719 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6941 22:56:10.113468 iDelay=217, Bit 1, Center -20 (-239 ~ 200) 440
6942 22:56:10.117187 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6943 22:56:10.119896 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6944 22:56:10.126832 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6945 22:56:10.130579 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6946 22:56:10.133500 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6947 22:56:10.137093 iDelay=217, Bit 7, Center -16 (-239 ~ 208) 448
6948 22:56:10.143803 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6949 22:56:10.147040 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6950 22:56:10.150267 iDelay=217, Bit 10, Center -20 (-247 ~ 208) 456
6951 22:56:10.153717 iDelay=217, Bit 11, Center -24 (-247 ~ 200) 448
6952 22:56:10.159987 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
6953 22:56:10.163526 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6954 22:56:10.167084 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6955 22:56:10.173532 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6956 22:56:10.174003 ==
6957 22:56:10.176806 Dram Type= 6, Freq= 0, CH_1, rank 1
6958 22:56:10.180064 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6959 22:56:10.180531 ==
6960 22:56:10.180911 DQS Delay:
6961 22:56:10.183263 DQS0 = 28, DQS1 = 32
6962 22:56:10.183763 DQM Delay:
6963 22:56:10.186884 DQM0 = 11, DQM1 = 11
6964 22:56:10.187307 DQ Delay:
6965 22:56:10.190173 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =4
6966 22:56:10.193723 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =12
6967 22:56:10.196821 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
6968 22:56:10.200265 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =16
6969 22:56:10.200734
6970 22:56:10.201102
6971 22:56:10.207204 [DQSOSCAuto] RK1, (LSB)MR18= 0xc95a, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 384 ps
6972 22:56:10.210163 CH1 RK1: MR19=C0C, MR18=C95A
6973 22:56:10.216657 CH1_RK1: MR19=0xC0C, MR18=0xC95A, DQSOSC=384, MR23=63, INC=400, DEC=267
6974 22:56:10.220108 [RxdqsGatingPostProcess] freq 400
6975 22:56:10.226962 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6976 22:56:10.227606 best DQS0 dly(2T, 0.5T) = (0, 10)
6977 22:56:10.230080 best DQS1 dly(2T, 0.5T) = (0, 10)
6978 22:56:10.233236 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6979 22:56:10.236748 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6980 22:56:10.239958 best DQS0 dly(2T, 0.5T) = (0, 10)
6981 22:56:10.243283 best DQS1 dly(2T, 0.5T) = (0, 10)
6982 22:56:10.247117 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6983 22:56:10.250396 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6984 22:56:10.253033 Pre-setting of DQS Precalculation
6985 22:56:10.256619 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6986 22:56:10.266585 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6987 22:56:10.273088 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6988 22:56:10.273646
6989 22:56:10.274020
6990 22:56:10.276545 [Calibration Summary] 800 Mbps
6991 22:56:10.277105 CH 0, Rank 0
6992 22:56:10.279868 SW Impedance : PASS
6993 22:56:10.280372 DUTY Scan : NO K
6994 22:56:10.283112 ZQ Calibration : PASS
6995 22:56:10.286494 Jitter Meter : NO K
6996 22:56:10.287080 CBT Training : PASS
6997 22:56:10.290148 Write leveling : PASS
6998 22:56:10.293022 RX DQS gating : PASS
6999 22:56:10.293580 RX DQ/DQS(RDDQC) : PASS
7000 22:56:10.296278 TX DQ/DQS : PASS
7001 22:56:10.299515 RX DATLAT : PASS
7002 22:56:10.300282 RX DQ/DQS(Engine): PASS
7003 22:56:10.302677 TX OE : NO K
7004 22:56:10.303141 All Pass.
7005 22:56:10.303568
7006 22:56:10.306005 CH 0, Rank 1
7007 22:56:10.306469 SW Impedance : PASS
7008 22:56:10.310025 DUTY Scan : NO K
7009 22:56:10.313391 ZQ Calibration : PASS
7010 22:56:10.313950 Jitter Meter : NO K
7011 22:56:10.316126 CBT Training : PASS
7012 22:56:10.316587 Write leveling : NO K
7013 22:56:10.319677 RX DQS gating : PASS
7014 22:56:10.323412 RX DQ/DQS(RDDQC) : PASS
7015 22:56:10.323966 TX DQ/DQS : PASS
7016 22:56:10.326435 RX DATLAT : PASS
7017 22:56:10.329896 RX DQ/DQS(Engine): PASS
7018 22:56:10.330468 TX OE : NO K
7019 22:56:10.332661 All Pass.
7020 22:56:10.333125
7021 22:56:10.333492 CH 1, Rank 0
7022 22:56:10.336219 SW Impedance : PASS
7023 22:56:10.336805 DUTY Scan : NO K
7024 22:56:10.339777 ZQ Calibration : PASS
7025 22:56:10.343088 Jitter Meter : NO K
7026 22:56:10.343679 CBT Training : PASS
7027 22:56:10.345989 Write leveling : PASS
7028 22:56:10.349639 RX DQS gating : PASS
7029 22:56:10.350207 RX DQ/DQS(RDDQC) : PASS
7030 22:56:10.352718 TX DQ/DQS : PASS
7031 22:56:10.356017 RX DATLAT : PASS
7032 22:56:10.356482 RX DQ/DQS(Engine): PASS
7033 22:56:10.359686 TX OE : NO K
7034 22:56:10.360256 All Pass.
7035 22:56:10.360625
7036 22:56:10.362699 CH 1, Rank 1
7037 22:56:10.363264 SW Impedance : PASS
7038 22:56:10.365779 DUTY Scan : NO K
7039 22:56:10.369448 ZQ Calibration : PASS
7040 22:56:10.370018 Jitter Meter : NO K
7041 22:56:10.372593 CBT Training : PASS
7042 22:56:10.373062 Write leveling : NO K
7043 22:56:10.376290 RX DQS gating : PASS
7044 22:56:10.379485 RX DQ/DQS(RDDQC) : PASS
7045 22:56:10.380055 TX DQ/DQS : PASS
7046 22:56:10.382713 RX DATLAT : PASS
7047 22:56:10.385878 RX DQ/DQS(Engine): PASS
7048 22:56:10.386453 TX OE : NO K
7049 22:56:10.389181 All Pass.
7050 22:56:10.389648
7051 22:56:10.390021 DramC Write-DBI off
7052 22:56:10.392953 PER_BANK_REFRESH: Hybrid Mode
7053 22:56:10.396009 TX_TRACKING: ON
7054 22:56:10.402488 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7055 22:56:10.405858 [FAST_K] Save calibration result to emmc
7056 22:56:10.409330 dramc_set_vcore_voltage set vcore to 725000
7057 22:56:10.412588 Read voltage for 1600, 0
7058 22:56:10.413169 Vio18 = 0
7059 22:56:10.415918 Vcore = 725000
7060 22:56:10.416382 Vdram = 0
7061 22:56:10.416753 Vddq = 0
7062 22:56:10.419233 Vmddr = 0
7063 22:56:10.422692 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7064 22:56:10.429971 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7065 22:56:10.430535 MEM_TYPE=3, freq_sel=13
7066 22:56:10.432656 sv_algorithm_assistance_LP4_3733
7067 22:56:10.439475 ============ PULL DRAM RESETB DOWN ============
7068 22:56:10.442890 ========== PULL DRAM RESETB DOWN end =========
7069 22:56:10.446225 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7070 22:56:10.449528 ===================================
7071 22:56:10.453138 LPDDR4 DRAM CONFIGURATION
7072 22:56:10.456047 ===================================
7073 22:56:10.456518 EX_ROW_EN[0] = 0x0
7074 22:56:10.459834 EX_ROW_EN[1] = 0x0
7075 22:56:10.462968 LP4Y_EN = 0x0
7076 22:56:10.463566 WORK_FSP = 0x1
7077 22:56:10.466074 WL = 0x5
7078 22:56:10.466538 RL = 0x5
7079 22:56:10.469389 BL = 0x2
7080 22:56:10.469858 RPST = 0x0
7081 22:56:10.472570 RD_PRE = 0x0
7082 22:56:10.473035 WR_PRE = 0x1
7083 22:56:10.476509 WR_PST = 0x1
7084 22:56:10.477070 DBI_WR = 0x0
7085 22:56:10.479098 DBI_RD = 0x0
7086 22:56:10.479597 OTF = 0x1
7087 22:56:10.482503 ===================================
7088 22:56:10.485849 ===================================
7089 22:56:10.489096 ANA top config
7090 22:56:10.492231 ===================================
7091 22:56:10.492695 DLL_ASYNC_EN = 0
7092 22:56:10.495645 ALL_SLAVE_EN = 0
7093 22:56:10.498879 NEW_RANK_MODE = 1
7094 22:56:10.502205 DLL_IDLE_MODE = 1
7095 22:56:10.505661 LP45_APHY_COMB_EN = 1
7096 22:56:10.506125 TX_ODT_DIS = 0
7097 22:56:10.508896 NEW_8X_MODE = 1
7098 22:56:10.512263 ===================================
7099 22:56:10.515586 ===================================
7100 22:56:10.519163 data_rate = 3200
7101 22:56:10.522225 CKR = 1
7102 22:56:10.525475 DQ_P2S_RATIO = 8
7103 22:56:10.528840 ===================================
7104 22:56:10.529307 CA_P2S_RATIO = 8
7105 22:56:10.531888 DQ_CA_OPEN = 0
7106 22:56:10.535709 DQ_SEMI_OPEN = 0
7107 22:56:10.539517 CA_SEMI_OPEN = 0
7108 22:56:10.542112 CA_FULL_RATE = 0
7109 22:56:10.545528 DQ_CKDIV4_EN = 0
7110 22:56:10.546110 CA_CKDIV4_EN = 0
7111 22:56:10.548772 CA_PREDIV_EN = 0
7112 22:56:10.551779 PH8_DLY = 12
7113 22:56:10.555217 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7114 22:56:10.558753 DQ_AAMCK_DIV = 4
7115 22:56:10.561821 CA_AAMCK_DIV = 4
7116 22:56:10.562250 CA_ADMCK_DIV = 4
7117 22:56:10.565243 DQ_TRACK_CA_EN = 0
7118 22:56:10.568809 CA_PICK = 1600
7119 22:56:10.571972 CA_MCKIO = 1600
7120 22:56:10.575264 MCKIO_SEMI = 0
7121 22:56:10.578862 PLL_FREQ = 3068
7122 22:56:10.581821 DQ_UI_PI_RATIO = 32
7123 22:56:10.585229 CA_UI_PI_RATIO = 0
7124 22:56:10.588921 ===================================
7125 22:56:10.591770 ===================================
7126 22:56:10.592391 memory_type:LPDDR4
7127 22:56:10.594882 GP_NUM : 10
7128 22:56:10.598820 SRAM_EN : 1
7129 22:56:10.599406 MD32_EN : 0
7130 22:56:10.601621 ===================================
7131 22:56:10.604891 [ANA_INIT] >>>>>>>>>>>>>>
7132 22:56:10.608413 <<<<<< [CONFIGURE PHASE]: ANA_TX
7133 22:56:10.611546 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7134 22:56:10.615091 ===================================
7135 22:56:10.618301 data_rate = 3200,PCW = 0X7600
7136 22:56:10.621703 ===================================
7137 22:56:10.625038 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7138 22:56:10.628117 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7139 22:56:10.634673 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7140 22:56:10.638330 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7141 22:56:10.642087 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7142 22:56:10.645124 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7143 22:56:10.648204 [ANA_INIT] flow start
7144 22:56:10.651779 [ANA_INIT] PLL >>>>>>>>
7145 22:56:10.652367 [ANA_INIT] PLL <<<<<<<<
7146 22:56:10.654621 [ANA_INIT] MIDPI >>>>>>>>
7147 22:56:10.658196 [ANA_INIT] MIDPI <<<<<<<<
7148 22:56:10.658789 [ANA_INIT] DLL >>>>>>>>
7149 22:56:10.661892 [ANA_INIT] DLL <<<<<<<<
7150 22:56:10.665354 [ANA_INIT] flow end
7151 22:56:10.668506 ============ LP4 DIFF to SE enter ============
7152 22:56:10.672083 ============ LP4 DIFF to SE exit ============
7153 22:56:10.674974 [ANA_INIT] <<<<<<<<<<<<<
7154 22:56:10.678816 [Flow] Enable top DCM control >>>>>
7155 22:56:10.681745 [Flow] Enable top DCM control <<<<<
7156 22:56:10.685073 Enable DLL master slave shuffle
7157 22:56:10.688403 ==============================================================
7158 22:56:10.692097 Gating Mode config
7159 22:56:10.698058 ==============================================================
7160 22:56:10.698627 Config description:
7161 22:56:10.708226 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7162 22:56:10.714953 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7163 22:56:10.718535 SELPH_MODE 0: By rank 1: By Phase
7164 22:56:10.724896 ==============================================================
7165 22:56:10.728230 GAT_TRACK_EN = 1
7166 22:56:10.731731 RX_GATING_MODE = 2
7167 22:56:10.734934 RX_GATING_TRACK_MODE = 2
7168 22:56:10.738145 SELPH_MODE = 1
7169 22:56:10.741893 PICG_EARLY_EN = 1
7170 22:56:10.744912 VALID_LAT_VALUE = 1
7171 22:56:10.748112 ==============================================================
7172 22:56:10.751763 Enter into Gating configuration >>>>
7173 22:56:10.755043 Exit from Gating configuration <<<<
7174 22:56:10.758102 Enter into DVFS_PRE_config >>>>>
7175 22:56:10.768104 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7176 22:56:10.771499 Exit from DVFS_PRE_config <<<<<
7177 22:56:10.774562 Enter into PICG configuration >>>>
7178 22:56:10.778711 Exit from PICG configuration <<<<
7179 22:56:10.781284 [RX_INPUT] configuration >>>>>
7180 22:56:10.784842 [RX_INPUT] configuration <<<<<
7181 22:56:10.791233 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7182 22:56:10.794974 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7183 22:56:10.801104 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7184 22:56:10.807959 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7185 22:56:10.814854 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7186 22:56:10.821253 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7187 22:56:10.825041 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7188 22:56:10.827707 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7189 22:56:10.830924 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7190 22:56:10.837941 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7191 22:56:10.841164 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7192 22:56:10.844778 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7193 22:56:10.847705 ===================================
7194 22:56:10.851526 LPDDR4 DRAM CONFIGURATION
7195 22:56:10.854293 ===================================
7196 22:56:10.854766 EX_ROW_EN[0] = 0x0
7197 22:56:10.857847 EX_ROW_EN[1] = 0x0
7198 22:56:10.861606 LP4Y_EN = 0x0
7199 22:56:10.862186 WORK_FSP = 0x1
7200 22:56:10.865102 WL = 0x5
7201 22:56:10.865671 RL = 0x5
7202 22:56:10.867834 BL = 0x2
7203 22:56:10.868302 RPST = 0x0
7204 22:56:10.871481 RD_PRE = 0x0
7205 22:56:10.872051 WR_PRE = 0x1
7206 22:56:10.874777 WR_PST = 0x1
7207 22:56:10.875244 DBI_WR = 0x0
7208 22:56:10.877888 DBI_RD = 0x0
7209 22:56:10.878357 OTF = 0x1
7210 22:56:10.881716 ===================================
7211 22:56:10.884510 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7212 22:56:10.891246 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7213 22:56:10.894621 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7214 22:56:10.898152 ===================================
7215 22:56:10.900827 LPDDR4 DRAM CONFIGURATION
7216 22:56:10.904226 ===================================
7217 22:56:10.904753 EX_ROW_EN[0] = 0x10
7218 22:56:10.907758 EX_ROW_EN[1] = 0x0
7219 22:56:10.908227 LP4Y_EN = 0x0
7220 22:56:10.911240 WORK_FSP = 0x1
7221 22:56:10.911859 WL = 0x5
7222 22:56:10.914376 RL = 0x5
7223 22:56:10.917633 BL = 0x2
7224 22:56:10.918054 RPST = 0x0
7225 22:56:10.921261 RD_PRE = 0x0
7226 22:56:10.921842 WR_PRE = 0x1
7227 22:56:10.924205 WR_PST = 0x1
7228 22:56:10.924673 DBI_WR = 0x0
7229 22:56:10.927669 DBI_RD = 0x0
7230 22:56:10.928134 OTF = 0x1
7231 22:56:10.930408 ===================================
7232 22:56:10.937051 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7233 22:56:10.937523 ==
7234 22:56:10.940463 Dram Type= 6, Freq= 0, CH_0, rank 0
7235 22:56:10.943843 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7236 22:56:10.944315 ==
7237 22:56:10.947073 [Duty_Offset_Calibration]
7238 22:56:10.950423 B0:2 B1:1 CA:1
7239 22:56:10.950883
7240 22:56:10.953409 [DutyScan_Calibration_Flow] k_type=0
7241 22:56:10.962761
7242 22:56:10.963321 ==CLK 0==
7243 22:56:10.965587 Final CLK duty delay cell = 0
7244 22:56:10.969017 [0] MAX Duty = 5156%(X100), DQS PI = 22
7245 22:56:10.972878 [0] MIN Duty = 4907%(X100), DQS PI = 0
7246 22:56:10.973462 [0] AVG Duty = 5031%(X100)
7247 22:56:10.975584
7248 22:56:10.979302 CH0 CLK Duty spec in!! Max-Min= 249%
7249 22:56:10.982420 [DutyScan_Calibration_Flow] ====Done====
7250 22:56:10.982992
7251 22:56:10.985301 [DutyScan_Calibration_Flow] k_type=1
7252 22:56:11.002062
7253 22:56:11.002621 ==DQS 0 ==
7254 22:56:11.004831 Final DQS duty delay cell = -4
7255 22:56:11.007872 [-4] MAX Duty = 5125%(X100), DQS PI = 24
7256 22:56:11.011935 [-4] MIN Duty = 4657%(X100), DQS PI = 0
7257 22:56:11.014754 [-4] AVG Duty = 4891%(X100)
7258 22:56:11.015241
7259 22:56:11.015667 ==DQS 1 ==
7260 22:56:11.017977 Final DQS duty delay cell = 0
7261 22:56:11.021317 [0] MAX Duty = 5218%(X100), DQS PI = 22
7262 22:56:11.025039 [0] MIN Duty = 5031%(X100), DQS PI = 52
7263 22:56:11.028145 [0] AVG Duty = 5124%(X100)
7264 22:56:11.028611
7265 22:56:11.031193 CH0 DQS 0 Duty spec in!! Max-Min= 468%
7266 22:56:11.031698
7267 22:56:11.034637 CH0 DQS 1 Duty spec in!! Max-Min= 187%
7268 22:56:11.037915 [DutyScan_Calibration_Flow] ====Done====
7269 22:56:11.038380
7270 22:56:11.041541 [DutyScan_Calibration_Flow] k_type=3
7271 22:56:11.058569
7272 22:56:11.059126 ==DQM 0 ==
7273 22:56:11.061808 Final DQM duty delay cell = 0
7274 22:56:11.064934 [0] MAX Duty = 5218%(X100), DQS PI = 34
7275 22:56:11.068477 [0] MIN Duty = 4907%(X100), DQS PI = 54
7276 22:56:11.069037 [0] AVG Duty = 5062%(X100)
7277 22:56:11.072222
7278 22:56:11.072780 ==DQM 1 ==
7279 22:56:11.074863 Final DQM duty delay cell = -4
7280 22:56:11.078383 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7281 22:56:11.081157 [-4] MIN Duty = 4844%(X100), DQS PI = 34
7282 22:56:11.084644 [-4] AVG Duty = 4922%(X100)
7283 22:56:11.085110
7284 22:56:11.088305 CH0 DQM 0 Duty spec in!! Max-Min= 311%
7285 22:56:11.088912
7286 22:56:11.091030 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7287 22:56:11.095027 [DutyScan_Calibration_Flow] ====Done====
7288 22:56:11.095632
7289 22:56:11.098336 [DutyScan_Calibration_Flow] k_type=2
7290 22:56:11.115704
7291 22:56:11.116260 ==DQ 0 ==
7292 22:56:11.119086 Final DQ duty delay cell = 0
7293 22:56:11.122291 [0] MAX Duty = 5062%(X100), DQS PI = 24
7294 22:56:11.125836 [0] MIN Duty = 4907%(X100), DQS PI = 0
7295 22:56:11.126397 [0] AVG Duty = 4984%(X100)
7296 22:56:11.126775
7297 22:56:11.129313 ==DQ 1 ==
7298 22:56:11.132002 Final DQ duty delay cell = 0
7299 22:56:11.135804 [0] MAX Duty = 5156%(X100), DQS PI = 22
7300 22:56:11.139002 [0] MIN Duty = 4907%(X100), DQS PI = 34
7301 22:56:11.139500 [0] AVG Duty = 5031%(X100)
7302 22:56:11.139874
7303 22:56:11.142054 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7304 22:56:11.145247
7305 22:56:11.148777 CH0 DQ 1 Duty spec in!! Max-Min= 249%
7306 22:56:11.152090 [DutyScan_Calibration_Flow] ====Done====
7307 22:56:11.152648 ==
7308 22:56:11.155498 Dram Type= 6, Freq= 0, CH_1, rank 0
7309 22:56:11.158770 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7310 22:56:11.159227 ==
7311 22:56:11.162047 [Duty_Offset_Calibration]
7312 22:56:11.162501 B0:1 B1:0 CA:1
7313 22:56:11.162862
7314 22:56:11.165000 [DutyScan_Calibration_Flow] k_type=0
7315 22:56:11.174663
7316 22:56:11.175074 ==CLK 0==
7317 22:56:11.178545 Final CLK duty delay cell = -4
7318 22:56:11.181631 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7319 22:56:11.185292 [-4] MIN Duty = 4876%(X100), DQS PI = 50
7320 22:56:11.188341 [-4] AVG Duty = 4938%(X100)
7321 22:56:11.188903
7322 22:56:11.191757 CH1 CLK Duty spec in!! Max-Min= 124%
7323 22:56:11.195069 [DutyScan_Calibration_Flow] ====Done====
7324 22:56:11.195678
7325 22:56:11.198497 [DutyScan_Calibration_Flow] k_type=1
7326 22:56:11.215299
7327 22:56:11.215912 ==DQS 0 ==
7328 22:56:11.218798 Final DQS duty delay cell = 0
7329 22:56:11.221773 [0] MAX Duty = 5094%(X100), DQS PI = 16
7330 22:56:11.225602 [0] MIN Duty = 4875%(X100), DQS PI = 0
7331 22:56:11.226170 [0] AVG Duty = 4984%(X100)
7332 22:56:11.228938
7333 22:56:11.229391 ==DQS 1 ==
7334 22:56:11.231754 Final DQS duty delay cell = 0
7335 22:56:11.234982 [0] MAX Duty = 5249%(X100), DQS PI = 16
7336 22:56:11.238162 [0] MIN Duty = 4938%(X100), DQS PI = 8
7337 22:56:11.241885 [0] AVG Duty = 5093%(X100)
7338 22:56:11.242450
7339 22:56:11.244853 CH1 DQS 0 Duty spec in!! Max-Min= 219%
7340 22:56:11.245309
7341 22:56:11.248476 CH1 DQS 1 Duty spec in!! Max-Min= 311%
7342 22:56:11.251764 [DutyScan_Calibration_Flow] ====Done====
7343 22:56:11.252220
7344 22:56:11.254954 [DutyScan_Calibration_Flow] k_type=3
7345 22:56:11.271944
7346 22:56:11.272492 ==DQM 0 ==
7347 22:56:11.275767 Final DQM duty delay cell = 0
7348 22:56:11.278533 [0] MAX Duty = 5218%(X100), DQS PI = 14
7349 22:56:11.281896 [0] MIN Duty = 4969%(X100), DQS PI = 48
7350 22:56:11.285282 [0] AVG Duty = 5093%(X100)
7351 22:56:11.285740
7352 22:56:11.286107 ==DQM 1 ==
7353 22:56:11.288300 Final DQM duty delay cell = 0
7354 22:56:11.291956 [0] MAX Duty = 5093%(X100), DQS PI = 18
7355 22:56:11.295035 [0] MIN Duty = 4907%(X100), DQS PI = 34
7356 22:56:11.298401 [0] AVG Duty = 5000%(X100)
7357 22:56:11.298959
7358 22:56:11.301738 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7359 22:56:11.302194
7360 22:56:11.305243 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7361 22:56:11.308548 [DutyScan_Calibration_Flow] ====Done====
7362 22:56:11.309100
7363 22:56:11.311924 [DutyScan_Calibration_Flow] k_type=2
7364 22:56:11.328337
7365 22:56:11.328893 ==DQ 0 ==
7366 22:56:11.331437 Final DQ duty delay cell = -4
7367 22:56:11.334858 [-4] MAX Duty = 5031%(X100), DQS PI = 10
7368 22:56:11.338114 [-4] MIN Duty = 4875%(X100), DQS PI = 46
7369 22:56:11.341741 [-4] AVG Duty = 4953%(X100)
7370 22:56:11.342311
7371 22:56:11.342679 ==DQ 1 ==
7372 22:56:11.344848 Final DQ duty delay cell = 0
7373 22:56:11.348182 [0] MAX Duty = 5124%(X100), DQS PI = 18
7374 22:56:11.351408 [0] MIN Duty = 4938%(X100), DQS PI = 8
7375 22:56:11.354749 [0] AVG Duty = 5031%(X100)
7376 22:56:11.355216
7377 22:56:11.358049 CH1 DQ 0 Duty spec in!! Max-Min= 156%
7378 22:56:11.358514
7379 22:56:11.361639 CH1 DQ 1 Duty spec in!! Max-Min= 186%
7380 22:56:11.364235 [DutyScan_Calibration_Flow] ====Done====
7381 22:56:11.367423 nWR fixed to 30
7382 22:56:11.371059 [ModeRegInit_LP4] CH0 RK0
7383 22:56:11.371561 [ModeRegInit_LP4] CH0 RK1
7384 22:56:11.374413 [ModeRegInit_LP4] CH1 RK0
7385 22:56:11.378106 [ModeRegInit_LP4] CH1 RK1
7386 22:56:11.378670 match AC timing 5
7387 22:56:11.384353 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7388 22:56:11.387899 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7389 22:56:11.391146 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7390 22:56:11.398268 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7391 22:56:11.401127 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7392 22:56:11.401763 [MiockJmeterHQA]
7393 22:56:11.402151
7394 22:56:11.404119 [DramcMiockJmeter] u1RxGatingPI = 0
7395 22:56:11.407435 0 : 4252, 4027
7396 22:56:11.408013 4 : 4252, 4027
7397 22:56:11.411365 8 : 4255, 4029
7398 22:56:11.411941 12 : 4252, 4027
7399 22:56:11.412323 16 : 4253, 4027
7400 22:56:11.414241 20 : 4252, 4027
7401 22:56:11.414803 24 : 4363, 4137
7402 22:56:11.417545 28 : 4363, 4137
7403 22:56:11.418114 32 : 4252, 4027
7404 22:56:11.420708 36 : 4252, 4027
7405 22:56:11.421180 40 : 4360, 4138
7406 22:56:11.424120 44 : 4360, 4138
7407 22:56:11.424592 48 : 4247, 4025
7408 22:56:11.424968 52 : 4360, 4138
7409 22:56:11.427675 56 : 4250, 4026
7410 22:56:11.428148 60 : 4250, 4027
7411 22:56:11.431436 64 : 4250, 4026
7412 22:56:11.431911 68 : 4250, 4027
7413 22:56:11.434463 72 : 4360, 4137
7414 22:56:11.434937 76 : 4250, 4026
7415 22:56:11.435312 80 : 4361, 4138
7416 22:56:11.437848 84 : 4250, 4026
7417 22:56:11.438320 88 : 4250, 178
7418 22:56:11.440751 92 : 4360, 0
7419 22:56:11.441221 96 : 4252, 0
7420 22:56:11.441599 100 : 4361, 0
7421 22:56:11.444054 104 : 4250, 0
7422 22:56:11.444523 108 : 4250, 0
7423 22:56:11.447516 112 : 4250, 0
7424 22:56:11.447987 116 : 4250, 0
7425 22:56:11.448366 120 : 4250, 0
7426 22:56:11.450585 124 : 4250, 0
7427 22:56:11.451057 128 : 4250, 0
7428 22:56:11.454574 132 : 4361, 0
7429 22:56:11.455141 136 : 4360, 0
7430 22:56:11.455558 140 : 4250, 0
7431 22:56:11.457543 144 : 4250, 0
7432 22:56:11.458022 148 : 4360, 0
7433 22:56:11.460619 152 : 4361, 0
7434 22:56:11.461150 156 : 4250, 0
7435 22:56:11.461600 160 : 4250, 0
7436 22:56:11.464161 164 : 4250, 0
7437 22:56:11.464639 168 : 4250, 0
7438 22:56:11.465018 172 : 4250, 0
7439 22:56:11.467309 176 : 4250, 0
7440 22:56:11.467844 180 : 4250, 0
7441 22:56:11.470738 184 : 4361, 0
7442 22:56:11.471317 188 : 4360, 0
7443 22:56:11.471752 192 : 4247, 0
7444 22:56:11.474021 196 : 4250, 0
7445 22:56:11.474657 200 : 4360, 0
7446 22:56:11.477459 204 : 4361, 1212
7447 22:56:11.477941 208 : 4360, 4114
7448 22:56:11.480582 212 : 4250, 4027
7449 22:56:11.481060 216 : 4250, 4026
7450 22:56:11.484090 220 : 4253, 4029
7451 22:56:11.484548 224 : 4250, 4027
7452 22:56:11.484931 228 : 4250, 4027
7453 22:56:11.487497 232 : 4250, 4026
7454 22:56:11.488029 236 : 4253, 4029
7455 22:56:11.491102 240 : 4250, 4027
7456 22:56:11.491719 244 : 4360, 4137
7457 22:56:11.494072 248 : 4361, 4137
7458 22:56:11.494606 252 : 4247, 4025
7459 22:56:11.497809 256 : 4361, 4137
7460 22:56:11.498348 260 : 4360, 4137
7461 22:56:11.500489 264 : 4250, 4027
7462 22:56:11.500922 268 : 4250, 4027
7463 22:56:11.503858 272 : 4253, 4029
7464 22:56:11.504291 276 : 4250, 4027
7465 22:56:11.507057 280 : 4250, 4026
7466 22:56:11.507528 284 : 4250, 4027
7467 22:56:11.510616 288 : 4250, 4027
7468 22:56:11.511050 292 : 4250, 4027
7469 22:56:11.511432 296 : 4360, 4137
7470 22:56:11.513887 300 : 4361, 4137
7471 22:56:11.514447 304 : 4250, 4027
7472 22:56:11.517340 308 : 4361, 4080
7473 22:56:11.517875 312 : 4360, 2155
7474 22:56:11.518219
7475 22:56:11.520700 MIOCK jitter meter ch=0
7476 22:56:11.521128
7477 22:56:11.523871 1T = (312-88) = 224 dly cells
7478 22:56:11.530495 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7479 22:56:11.531029 ==
7480 22:56:11.534550 Dram Type= 6, Freq= 0, CH_0, rank 0
7481 22:56:11.537283 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7482 22:56:11.537814 ==
7483 22:56:11.544369 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7484 22:56:11.547664 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7485 22:56:11.550385 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7486 22:56:11.557107 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7487 22:56:11.565693 [CA 0] Center 42 (12~73) winsize 62
7488 22:56:11.569736 [CA 1] Center 42 (12~73) winsize 62
7489 22:56:11.572767 [CA 2] Center 37 (8~67) winsize 60
7490 22:56:11.576035 [CA 3] Center 37 (7~67) winsize 61
7491 22:56:11.579528 [CA 4] Center 36 (6~66) winsize 61
7492 22:56:11.582177 [CA 5] Center 35 (6~64) winsize 59
7493 22:56:11.582751
7494 22:56:11.585498 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7495 22:56:11.585969
7496 22:56:11.588944 [CATrainingPosCal] consider 1 rank data
7497 22:56:11.592684 u2DelayCellTimex100 = 290/100 ps
7498 22:56:11.596259 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7499 22:56:11.602337 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7500 22:56:11.605809 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
7501 22:56:11.608882 CA3 delay=37 (7~67),Diff = 2 PI (6 cell)
7502 22:56:11.612044 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7503 22:56:11.615543 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7504 22:56:11.616009
7505 22:56:11.618577 CA PerBit enable=1, Macro0, CA PI delay=35
7506 22:56:11.619038
7507 22:56:11.622177 [CBTSetCACLKResult] CA Dly = 35
7508 22:56:11.625951 CS Dly: 9 (0~40)
7509 22:56:11.628569 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7510 22:56:11.632089 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7511 22:56:11.632556 ==
7512 22:56:11.635196 Dram Type= 6, Freq= 0, CH_0, rank 1
7513 22:56:11.638920 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7514 22:56:11.639603 ==
7515 22:56:11.645086 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7516 22:56:11.648358 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7517 22:56:11.656077 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7518 22:56:11.658623 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7519 22:56:11.669345 [CA 0] Center 42 (12~73) winsize 62
7520 22:56:11.672009 [CA 1] Center 42 (12~73) winsize 62
7521 22:56:11.676074 [CA 2] Center 38 (8~68) winsize 61
7522 22:56:11.679131 [CA 3] Center 37 (7~68) winsize 62
7523 22:56:11.682658 [CA 4] Center 35 (5~65) winsize 61
7524 22:56:11.685288 [CA 5] Center 35 (5~65) winsize 61
7525 22:56:11.685824
7526 22:56:11.689299 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7527 22:56:11.689765
7528 22:56:11.692736 [CATrainingPosCal] consider 2 rank data
7529 22:56:11.695480 u2DelayCellTimex100 = 290/100 ps
7530 22:56:11.699081 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7531 22:56:11.705400 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7532 22:56:11.708821 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
7533 22:56:11.712802 CA3 delay=37 (7~67),Diff = 2 PI (6 cell)
7534 22:56:11.715697 CA4 delay=35 (6~65),Diff = 0 PI (0 cell)
7535 22:56:11.719293 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7536 22:56:11.719911
7537 22:56:11.722551 CA PerBit enable=1, Macro0, CA PI delay=35
7538 22:56:11.723149
7539 22:56:11.725760 [CBTSetCACLKResult] CA Dly = 35
7540 22:56:11.728976 CS Dly: 10 (0~42)
7541 22:56:11.731986 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7542 22:56:11.735437 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7543 22:56:11.736007
7544 22:56:11.738941 ----->DramcWriteLeveling(PI) begin...
7545 22:56:11.739559 ==
7546 22:56:11.742652 Dram Type= 6, Freq= 0, CH_0, rank 0
7547 22:56:11.745458 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7548 22:56:11.748484 ==
7549 22:56:11.748949 Write leveling (Byte 0): 36 => 36
7550 22:56:11.751874 Write leveling (Byte 1): 29 => 29
7551 22:56:11.755512 DramcWriteLeveling(PI) end<-----
7552 22:56:11.756151
7553 22:56:11.756529 ==
7554 22:56:11.758617 Dram Type= 6, Freq= 0, CH_0, rank 0
7555 22:56:11.765505 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7556 22:56:11.766076 ==
7557 22:56:11.768920 [Gating] SW mode calibration
7558 22:56:11.775304 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7559 22:56:11.778702 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7560 22:56:11.785386 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7561 22:56:11.788613 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7562 22:56:11.792134 1 4 8 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
7563 22:56:11.795501 1 4 12 | B1->B0 | 2323 3131 | 0 0 | (0 0) (1 1)
7564 22:56:11.801695 1 4 16 | B1->B0 | 2424 3534 | 0 1 | (0 0) (1 1)
7565 22:56:11.805708 1 4 20 | B1->B0 | 3333 3535 | 1 0 | (1 1) (1 1)
7566 22:56:11.808519 1 4 24 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7567 22:56:11.815500 1 4 28 | B1->B0 | 3434 3535 | 1 0 | (1 1) (1 1)
7568 22:56:11.818570 1 5 0 | B1->B0 | 3434 3636 | 1 1 | (1 1) (1 1)
7569 22:56:11.822176 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7570 22:56:11.828542 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7571 22:56:11.831870 1 5 12 | B1->B0 | 3434 2626 | 1 0 | (1 1) (1 0)
7572 22:56:11.834912 1 5 16 | B1->B0 | 3434 2525 | 1 0 | (1 1) (1 0)
7573 22:56:11.842138 1 5 20 | B1->B0 | 2828 2323 | 0 0 | (0 1) (0 0)
7574 22:56:11.845239 1 5 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7575 22:56:11.848697 1 5 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7576 22:56:11.855022 1 6 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7577 22:56:11.858463 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 1)
7578 22:56:11.861652 1 6 8 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (0 0)
7579 22:56:11.869105 1 6 12 | B1->B0 | 2323 4645 | 0 1 | (0 0) (0 0)
7580 22:56:11.872028 1 6 16 | B1->B0 | 2d2d 4646 | 0 0 | (0 0) (0 0)
7581 22:56:11.875457 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7582 22:56:11.882188 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7583 22:56:11.885242 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7584 22:56:11.888819 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7585 22:56:11.895201 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7586 22:56:11.898304 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7587 22:56:11.901945 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7588 22:56:11.905105 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7589 22:56:11.911664 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7590 22:56:11.915493 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7591 22:56:11.918424 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7592 22:56:11.925209 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7593 22:56:11.928053 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7594 22:56:11.931396 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7595 22:56:11.938165 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7596 22:56:11.941780 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7597 22:56:11.945375 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7598 22:56:11.951863 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7599 22:56:11.955020 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7600 22:56:11.958677 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7601 22:56:11.964809 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7602 22:56:11.968448 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7603 22:56:11.971772 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7604 22:56:11.978363 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7605 22:56:11.978827 Total UI for P1: 0, mck2ui 16
7606 22:56:11.984978 best dqsien dly found for B0: ( 1, 9, 10)
7607 22:56:11.988706 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7608 22:56:11.991638 Total UI for P1: 0, mck2ui 16
7609 22:56:11.994964 best dqsien dly found for B1: ( 1, 9, 18)
7610 22:56:11.998560 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7611 22:56:12.001783 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7612 22:56:12.002256
7613 22:56:12.005147 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7614 22:56:12.008400 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7615 22:56:12.011894 [Gating] SW calibration Done
7616 22:56:12.012366 ==
7617 22:56:12.015060 Dram Type= 6, Freq= 0, CH_0, rank 0
7618 22:56:12.017984 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7619 22:56:12.018457 ==
7620 22:56:12.021960 RX Vref Scan: 0
7621 22:56:12.022534
7622 22:56:12.025326 RX Vref 0 -> 0, step: 1
7623 22:56:12.025921
7624 22:56:12.026379 RX Delay 0 -> 252, step: 8
7625 22:56:12.031752 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7626 22:56:12.034669 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7627 22:56:12.038575 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
7628 22:56:12.041500 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7629 22:56:12.044774 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7630 22:56:12.051506 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7631 22:56:12.054459 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7632 22:56:12.057938 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7633 22:56:12.061424 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7634 22:56:12.064817 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
7635 22:56:12.071523 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7636 22:56:12.074683 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7637 22:56:12.078256 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
7638 22:56:12.081802 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7639 22:56:12.084860 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7640 22:56:12.091136 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7641 22:56:12.091688 ==
7642 22:56:12.094624 Dram Type= 6, Freq= 0, CH_0, rank 0
7643 22:56:12.098028 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7644 22:56:12.098610 ==
7645 22:56:12.098984 DQS Delay:
7646 22:56:12.101900 DQS0 = 0, DQS1 = 0
7647 22:56:12.102459 DQM Delay:
7648 22:56:12.105002 DQM0 = 137, DQM1 = 129
7649 22:56:12.105624 DQ Delay:
7650 22:56:12.108240 DQ0 =135, DQ1 =143, DQ2 =135, DQ3 =131
7651 22:56:12.111142 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =143
7652 22:56:12.115215 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =119
7653 22:56:12.118343 DQ12 =135, DQ13 =135, DQ14 =139, DQ15 =135
7654 22:56:12.118906
7655 22:56:12.119383
7656 22:56:12.121282 ==
7657 22:56:12.124393 Dram Type= 6, Freq= 0, CH_0, rank 0
7658 22:56:12.127888 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7659 22:56:12.128356 ==
7660 22:56:12.128721
7661 22:56:12.129056
7662 22:56:12.131006 TX Vref Scan disable
7663 22:56:12.131561 == TX Byte 0 ==
7664 22:56:12.137940 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7665 22:56:12.141492 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7666 22:56:12.142055 == TX Byte 1 ==
7667 22:56:12.147819 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7668 22:56:12.151034 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7669 22:56:12.151531 ==
7670 22:56:12.154566 Dram Type= 6, Freq= 0, CH_0, rank 0
7671 22:56:12.157784 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7672 22:56:12.158251 ==
7673 22:56:12.170528
7674 22:56:12.173795 TX Vref early break, caculate TX vref
7675 22:56:12.177154 TX Vref=16, minBit 4, minWin=22, winSum=380
7676 22:56:12.180556 TX Vref=18, minBit 0, minWin=23, winSum=388
7677 22:56:12.183892 TX Vref=20, minBit 0, minWin=23, winSum=398
7678 22:56:12.187532 TX Vref=22, minBit 0, minWin=24, winSum=406
7679 22:56:12.190676 TX Vref=24, minBit 0, minWin=24, winSum=412
7680 22:56:12.197405 TX Vref=26, minBit 1, minWin=25, winSum=419
7681 22:56:12.200768 TX Vref=28, minBit 6, minWin=25, winSum=423
7682 22:56:12.204136 TX Vref=30, minBit 2, minWin=24, winSum=408
7683 22:56:12.207195 TX Vref=32, minBit 1, minWin=23, winSum=400
7684 22:56:12.213868 [TxChooseVref] Worse bit 6, Min win 25, Win sum 423, Final Vref 28
7685 22:56:12.214333
7686 22:56:12.214700 Final TX Range 0 Vref 28
7687 22:56:12.216889
7688 22:56:12.217446 ==
7689 22:56:12.220727 Dram Type= 6, Freq= 0, CH_0, rank 0
7690 22:56:12.223814 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7691 22:56:12.224282 ==
7692 22:56:12.224649
7693 22:56:12.225011
7694 22:56:12.227036 TX Vref Scan disable
7695 22:56:12.230606 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7696 22:56:12.234383 == TX Byte 0 ==
7697 22:56:12.237129 u2DelayCellOfst[0]=13 cells (4 PI)
7698 22:56:12.240804 u2DelayCellOfst[1]=13 cells (4 PI)
7699 22:56:12.243904 u2DelayCellOfst[2]=10 cells (3 PI)
7700 22:56:12.247195 u2DelayCellOfst[3]=10 cells (3 PI)
7701 22:56:12.247798 u2DelayCellOfst[4]=6 cells (2 PI)
7702 22:56:12.250887 u2DelayCellOfst[5]=0 cells (0 PI)
7703 22:56:12.253740 u2DelayCellOfst[6]=16 cells (5 PI)
7704 22:56:12.257221 u2DelayCellOfst[7]=16 cells (5 PI)
7705 22:56:12.263930 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7706 22:56:12.267889 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7707 22:56:12.268460 == TX Byte 1 ==
7708 22:56:12.270613 u2DelayCellOfst[8]=0 cells (0 PI)
7709 22:56:12.273637 u2DelayCellOfst[9]=0 cells (0 PI)
7710 22:56:12.277481 u2DelayCellOfst[10]=6 cells (2 PI)
7711 22:56:12.280206 u2DelayCellOfst[11]=6 cells (2 PI)
7712 22:56:12.283730 u2DelayCellOfst[12]=10 cells (3 PI)
7713 22:56:12.286589 u2DelayCellOfst[13]=10 cells (3 PI)
7714 22:56:12.290445 u2DelayCellOfst[14]=13 cells (4 PI)
7715 22:56:12.293590 u2DelayCellOfst[15]=10 cells (3 PI)
7716 22:56:12.296807 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7717 22:56:12.300113 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7718 22:56:12.304052 DramC Write-DBI on
7719 22:56:12.304616 ==
7720 22:56:12.306631 Dram Type= 6, Freq= 0, CH_0, rank 0
7721 22:56:12.310433 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7722 22:56:12.310928 ==
7723 22:56:12.311300
7724 22:56:12.311678
7725 22:56:12.313387 TX Vref Scan disable
7726 22:56:12.317273 == TX Byte 0 ==
7727 22:56:12.320330 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7728 22:56:12.320805 == TX Byte 1 ==
7729 22:56:12.326589 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7730 22:56:12.327064 DramC Write-DBI off
7731 22:56:12.327509
7732 22:56:12.329924 [DATLAT]
7733 22:56:12.330393 Freq=1600, CH0 RK0
7734 22:56:12.330765
7735 22:56:12.333321 DATLAT Default: 0xf
7736 22:56:12.333796 0, 0xFFFF, sum = 0
7737 22:56:12.337015 1, 0xFFFF, sum = 0
7738 22:56:12.337607 2, 0xFFFF, sum = 0
7739 22:56:12.340237 3, 0xFFFF, sum = 0
7740 22:56:12.340747 4, 0xFFFF, sum = 0
7741 22:56:12.343441 5, 0xFFFF, sum = 0
7742 22:56:12.343917 6, 0xFFFF, sum = 0
7743 22:56:12.346756 7, 0xFFFF, sum = 0
7744 22:56:12.347231 8, 0xFFFF, sum = 0
7745 22:56:12.350145 9, 0xFFFF, sum = 0
7746 22:56:12.350726 10, 0xFFFF, sum = 0
7747 22:56:12.353669 11, 0xFFFF, sum = 0
7748 22:56:12.356511 12, 0xFFFF, sum = 0
7749 22:56:12.357017 13, 0xFFFF, sum = 0
7750 22:56:12.359888 14, 0x0, sum = 1
7751 22:56:12.360366 15, 0x0, sum = 2
7752 22:56:12.360748 16, 0x0, sum = 3
7753 22:56:12.363506 17, 0x0, sum = 4
7754 22:56:12.363988 best_step = 15
7755 22:56:12.364359
7756 22:56:12.366720 ==
7757 22:56:12.367190 Dram Type= 6, Freq= 0, CH_0, rank 0
7758 22:56:12.373575 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7759 22:56:12.374150 ==
7760 22:56:12.374527 RX Vref Scan: 1
7761 22:56:12.374876
7762 22:56:12.376716 Set Vref Range= 24 -> 127
7763 22:56:12.377287
7764 22:56:12.380359 RX Vref 24 -> 127, step: 1
7765 22:56:12.380931
7766 22:56:12.383790 RX Delay 19 -> 252, step: 4
7767 22:56:12.384366
7768 22:56:12.384746 Set Vref, RX VrefLevel [Byte0]: 24
7769 22:56:12.387171 [Byte1]: 24
7770 22:56:12.391036
7771 22:56:12.391714 Set Vref, RX VrefLevel [Byte0]: 25
7772 22:56:12.395009 [Byte1]: 25
7773 22:56:12.398660
7774 22:56:12.399227 Set Vref, RX VrefLevel [Byte0]: 26
7775 22:56:12.402721 [Byte1]: 26
7776 22:56:12.406606
7777 22:56:12.407170 Set Vref, RX VrefLevel [Byte0]: 27
7778 22:56:12.409278 [Byte1]: 27
7779 22:56:12.413569
7780 22:56:12.414036 Set Vref, RX VrefLevel [Byte0]: 28
7781 22:56:12.417063 [Byte1]: 28
7782 22:56:12.421215
7783 22:56:12.421685 Set Vref, RX VrefLevel [Byte0]: 29
7784 22:56:12.424583 [Byte1]: 29
7785 22:56:12.429138
7786 22:56:12.429605 Set Vref, RX VrefLevel [Byte0]: 30
7787 22:56:12.432013 [Byte1]: 30
7788 22:56:12.436423
7789 22:56:12.436890 Set Vref, RX VrefLevel [Byte0]: 31
7790 22:56:12.439770 [Byte1]: 31
7791 22:56:12.444454
7792 22:56:12.445017 Set Vref, RX VrefLevel [Byte0]: 32
7793 22:56:12.447185 [Byte1]: 32
7794 22:56:12.451938
7795 22:56:12.452431 Set Vref, RX VrefLevel [Byte0]: 33
7796 22:56:12.455064 [Byte1]: 33
7797 22:56:12.459706
7798 22:56:12.460177 Set Vref, RX VrefLevel [Byte0]: 34
7799 22:56:12.462915 [Byte1]: 34
7800 22:56:12.467143
7801 22:56:12.467742 Set Vref, RX VrefLevel [Byte0]: 35
7802 22:56:12.470216 [Byte1]: 35
7803 22:56:12.474663
7804 22:56:12.475228 Set Vref, RX VrefLevel [Byte0]: 36
7805 22:56:12.477732 [Byte1]: 36
7806 22:56:12.481962
7807 22:56:12.482427 Set Vref, RX VrefLevel [Byte0]: 37
7808 22:56:12.485526 [Byte1]: 37
7809 22:56:12.490222
7810 22:56:12.490792 Set Vref, RX VrefLevel [Byte0]: 38
7811 22:56:12.493195 [Byte1]: 38
7812 22:56:12.497430
7813 22:56:12.497988 Set Vref, RX VrefLevel [Byte0]: 39
7814 22:56:12.500576 [Byte1]: 39
7815 22:56:12.504795
7816 22:56:12.505308 Set Vref, RX VrefLevel [Byte0]: 40
7817 22:56:12.508214 [Byte1]: 40
7818 22:56:12.512279
7819 22:56:12.512892 Set Vref, RX VrefLevel [Byte0]: 41
7820 22:56:12.518519 [Byte1]: 41
7821 22:56:12.519110
7822 22:56:12.521838 Set Vref, RX VrefLevel [Byte0]: 42
7823 22:56:12.525664 [Byte1]: 42
7824 22:56:12.526244
7825 22:56:12.528465 Set Vref, RX VrefLevel [Byte0]: 43
7826 22:56:12.531699 [Byte1]: 43
7827 22:56:12.532186
7828 22:56:12.535090 Set Vref, RX VrefLevel [Byte0]: 44
7829 22:56:12.538408 [Byte1]: 44
7830 22:56:12.542875
7831 22:56:12.543524 Set Vref, RX VrefLevel [Byte0]: 45
7832 22:56:12.546466 [Byte1]: 45
7833 22:56:12.549980
7834 22:56:12.550543 Set Vref, RX VrefLevel [Byte0]: 46
7835 22:56:12.553454 [Byte1]: 46
7836 22:56:12.558022
7837 22:56:12.558592 Set Vref, RX VrefLevel [Byte0]: 47
7838 22:56:12.561063 [Byte1]: 47
7839 22:56:12.565376
7840 22:56:12.565947 Set Vref, RX VrefLevel [Byte0]: 48
7841 22:56:12.568924 [Byte1]: 48
7842 22:56:12.573072
7843 22:56:12.573663 Set Vref, RX VrefLevel [Byte0]: 49
7844 22:56:12.576001 [Byte1]: 49
7845 22:56:12.580267
7846 22:56:12.580835 Set Vref, RX VrefLevel [Byte0]: 50
7847 22:56:12.583866 [Byte1]: 50
7848 22:56:12.587859
7849 22:56:12.588329 Set Vref, RX VrefLevel [Byte0]: 51
7850 22:56:12.591444 [Byte1]: 51
7851 22:56:12.595734
7852 22:56:12.596303 Set Vref, RX VrefLevel [Byte0]: 52
7853 22:56:12.599082 [Byte1]: 52
7854 22:56:12.603563
7855 22:56:12.604131 Set Vref, RX VrefLevel [Byte0]: 53
7856 22:56:12.606451 [Byte1]: 53
7857 22:56:12.610844
7858 22:56:12.611318 Set Vref, RX VrefLevel [Byte0]: 54
7859 22:56:12.614061 [Byte1]: 54
7860 22:56:12.618266
7861 22:56:12.618737 Set Vref, RX VrefLevel [Byte0]: 55
7862 22:56:12.621736 [Byte1]: 55
7863 22:56:12.625843
7864 22:56:12.626383 Set Vref, RX VrefLevel [Byte0]: 56
7865 22:56:12.629509 [Byte1]: 56
7866 22:56:12.633350
7867 22:56:12.633933 Set Vref, RX VrefLevel [Byte0]: 57
7868 22:56:12.637005 [Byte1]: 57
7869 22:56:12.640681
7870 22:56:12.641150 Set Vref, RX VrefLevel [Byte0]: 58
7871 22:56:12.644848 [Byte1]: 58
7872 22:56:12.648415
7873 22:56:12.648886 Set Vref, RX VrefLevel [Byte0]: 59
7874 22:56:12.651843 [Byte1]: 59
7875 22:56:12.656459
7876 22:56:12.657030 Set Vref, RX VrefLevel [Byte0]: 60
7877 22:56:12.659590 [Byte1]: 60
7878 22:56:12.664067
7879 22:56:12.664636 Set Vref, RX VrefLevel [Byte0]: 61
7880 22:56:12.666927 [Byte1]: 61
7881 22:56:12.671515
7882 22:56:12.672084 Set Vref, RX VrefLevel [Byte0]: 62
7883 22:56:12.675075 [Byte1]: 62
7884 22:56:12.679247
7885 22:56:12.679915 Set Vref, RX VrefLevel [Byte0]: 63
7886 22:56:12.682076 [Byte1]: 63
7887 22:56:12.686636
7888 22:56:12.687107 Set Vref, RX VrefLevel [Byte0]: 64
7889 22:56:12.689832 [Byte1]: 64
7890 22:56:12.694132
7891 22:56:12.694605 Set Vref, RX VrefLevel [Byte0]: 65
7892 22:56:12.698075 [Byte1]: 65
7893 22:56:12.701773
7894 22:56:12.702346 Set Vref, RX VrefLevel [Byte0]: 66
7895 22:56:12.705152 [Byte1]: 66
7896 22:56:12.709669
7897 22:56:12.710366 Set Vref, RX VrefLevel [Byte0]: 67
7898 22:56:12.712293 [Byte1]: 67
7899 22:56:12.717106
7900 22:56:12.717685 Set Vref, RX VrefLevel [Byte0]: 68
7901 22:56:12.719917 [Byte1]: 68
7902 22:56:12.724665
7903 22:56:12.725242 Set Vref, RX VrefLevel [Byte0]: 69
7904 22:56:12.727583 [Byte1]: 69
7905 22:56:12.732095
7906 22:56:12.732656 Set Vref, RX VrefLevel [Byte0]: 70
7907 22:56:12.735707 [Byte1]: 70
7908 22:56:12.739203
7909 22:56:12.739749 Set Vref, RX VrefLevel [Byte0]: 71
7910 22:56:12.742616 [Byte1]: 71
7911 22:56:12.747217
7912 22:56:12.747841 Set Vref, RX VrefLevel [Byte0]: 72
7913 22:56:12.750507 [Byte1]: 72
7914 22:56:12.754661
7915 22:56:12.755249 Set Vref, RX VrefLevel [Byte0]: 73
7916 22:56:12.758236 [Byte1]: 73
7917 22:56:12.762197
7918 22:56:12.762788 Final RX Vref Byte 0 = 54 to rank0
7919 22:56:12.765483 Final RX Vref Byte 1 = 60 to rank0
7920 22:56:12.768734 Final RX Vref Byte 0 = 54 to rank1
7921 22:56:12.772285 Final RX Vref Byte 1 = 60 to rank1==
7922 22:56:12.775859 Dram Type= 6, Freq= 0, CH_0, rank 0
7923 22:56:12.782299 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7924 22:56:12.782883 ==
7925 22:56:12.783425 DQS Delay:
7926 22:56:12.783886 DQS0 = 0, DQS1 = 0
7927 22:56:12.785937 DQM Delay:
7928 22:56:12.786516 DQM0 = 133, DQM1 = 128
7929 22:56:12.788585 DQ Delay:
7930 22:56:12.792062 DQ0 =134, DQ1 =136, DQ2 =134, DQ3 =130
7931 22:56:12.795563 DQ4 =132, DQ5 =124, DQ6 =142, DQ7 =138
7932 22:56:12.798967 DQ8 =116, DQ9 =118, DQ10 =130, DQ11 =120
7933 22:56:12.802594 DQ12 =134, DQ13 =134, DQ14 =138, DQ15 =134
7934 22:56:12.803171
7935 22:56:12.803696
7936 22:56:12.804148
7937 22:56:12.805341 [DramC_TX_OE_Calibration] TA2
7938 22:56:12.808915 Original DQ_B0 (3 6) =30, OEN = 27
7939 22:56:12.812252 Original DQ_B1 (3 6) =30, OEN = 27
7940 22:56:12.815588 24, 0x0, End_B0=24 End_B1=24
7941 22:56:12.816080 25, 0x0, End_B0=25 End_B1=25
7942 22:56:12.819349 26, 0x0, End_B0=26 End_B1=26
7943 22:56:12.822453 27, 0x0, End_B0=27 End_B1=27
7944 22:56:12.825809 28, 0x0, End_B0=28 End_B1=28
7945 22:56:12.826393 29, 0x0, End_B0=29 End_B1=29
7946 22:56:12.828813 30, 0x0, End_B0=30 End_B1=30
7947 22:56:12.832268 31, 0x4545, End_B0=30 End_B1=30
7948 22:56:12.835582 Byte0 end_step=30 best_step=27
7949 22:56:12.838697 Byte1 end_step=30 best_step=27
7950 22:56:12.842461 Byte0 TX OE(2T, 0.5T) = (3, 3)
7951 22:56:12.842942 Byte1 TX OE(2T, 0.5T) = (3, 3)
7952 22:56:12.843466
7953 22:56:12.845472
7954 22:56:12.851976 [DQSOSCAuto] RK0, (LSB)MR18= 0x241f, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 391 ps
7955 22:56:12.855223 CH0 RK0: MR19=303, MR18=241F
7956 22:56:12.862206 CH0_RK0: MR19=0x303, MR18=0x241F, DQSOSC=391, MR23=63, INC=24, DEC=16
7957 22:56:12.862770
7958 22:56:12.865708 ----->DramcWriteLeveling(PI) begin...
7959 22:56:12.866199 ==
7960 22:56:12.869428 Dram Type= 6, Freq= 0, CH_0, rank 1
7961 22:56:12.872338 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7962 22:56:12.872849 ==
7963 22:56:12.876224 Write leveling (Byte 0): 36 => 36
7964 22:56:12.879258 Write leveling (Byte 1): 29 => 29
7965 22:56:12.882176 DramcWriteLeveling(PI) end<-----
7966 22:56:12.882752
7967 22:56:12.883240 ==
7968 22:56:12.885760 Dram Type= 6, Freq= 0, CH_0, rank 1
7969 22:56:12.889588 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7970 22:56:12.890164 ==
7971 22:56:12.892238 [Gating] SW mode calibration
7972 22:56:12.898810 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7973 22:56:12.905666 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7974 22:56:12.909334 1 4 0 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
7975 22:56:12.912221 1 4 4 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
7976 22:56:12.919074 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7977 22:56:12.922063 1 4 12 | B1->B0 | 2323 2828 | 0 1 | (0 0) (0 0)
7978 22:56:12.925707 1 4 16 | B1->B0 | 3232 3938 | 1 1 | (1 1) (1 1)
7979 22:56:12.931589 1 4 20 | B1->B0 | 3434 3737 | 1 0 | (1 1) (0 0)
7980 22:56:12.934919 1 4 24 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
7981 22:56:12.938475 1 4 28 | B1->B0 | 3434 3b3a | 1 1 | (1 1) (0 0)
7982 22:56:12.945590 1 5 0 | B1->B0 | 3434 3636 | 1 0 | (1 1) (0 0)
7983 22:56:12.948388 1 5 4 | B1->B0 | 3434 3737 | 1 0 | (1 1) (0 0)
7984 22:56:12.951742 1 5 8 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 1)
7985 22:56:12.958679 1 5 12 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 0)
7986 22:56:12.961951 1 5 16 | B1->B0 | 2f2f 2928 | 0 1 | (0 1) (1 0)
7987 22:56:12.965083 1 5 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7988 22:56:12.972037 1 5 24 | B1->B0 | 2323 2726 | 0 1 | (0 0) (1 1)
7989 22:56:12.975469 1 5 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7990 22:56:12.978424 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7991 22:56:12.981418 1 6 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7992 22:56:12.988073 1 6 8 | B1->B0 | 2323 2626 | 0 1 | (0 0) (1 1)
7993 22:56:12.991937 1 6 12 | B1->B0 | 2323 3636 | 0 1 | (0 0) (0 0)
7994 22:56:12.994939 1 6 16 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
7995 22:56:13.001458 1 6 20 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
7996 22:56:13.004896 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7997 22:56:13.008455 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7998 22:56:13.014768 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7999 22:56:13.018185 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8000 22:56:13.021840 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8001 22:56:13.028297 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8002 22:56:13.031612 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8003 22:56:13.034967 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8004 22:56:13.041614 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8005 22:56:13.044857 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8006 22:56:13.047830 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8007 22:56:13.054609 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8008 22:56:13.058302 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8009 22:56:13.061706 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8010 22:56:13.067873 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8011 22:56:13.071932 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8012 22:56:13.074590 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8013 22:56:13.081546 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8014 22:56:13.084541 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8015 22:56:13.088076 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8016 22:56:13.094898 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8017 22:56:13.098288 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8018 22:56:13.101427 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8019 22:56:13.108487 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8020 22:56:13.109068 Total UI for P1: 0, mck2ui 16
8021 22:56:13.111222 best dqsien dly found for B0: ( 1, 9, 14)
8022 22:56:13.114722 Total UI for P1: 0, mck2ui 16
8023 22:56:13.117943 best dqsien dly found for B1: ( 1, 9, 14)
8024 22:56:13.121848 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8025 22:56:13.128198 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8026 22:56:13.128767
8027 22:56:13.131541 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8028 22:56:13.134648 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8029 22:56:13.138280 [Gating] SW calibration Done
8030 22:56:13.138843 ==
8031 22:56:13.141597 Dram Type= 6, Freq= 0, CH_0, rank 1
8032 22:56:13.144718 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8033 22:56:13.145277 ==
8034 22:56:13.148097 RX Vref Scan: 0
8035 22:56:13.148576
8036 22:56:13.148959 RX Vref 0 -> 0, step: 1
8037 22:56:13.149398
8038 22:56:13.151316 RX Delay 0 -> 252, step: 8
8039 22:56:13.155133 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8040 22:56:13.157822 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8041 22:56:13.164532 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8042 22:56:13.168035 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8043 22:56:13.171065 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8044 22:56:13.174461 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8045 22:56:13.178424 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8046 22:56:13.184289 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8047 22:56:13.187524 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8048 22:56:13.191182 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8049 22:56:13.194451 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8050 22:56:13.198215 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8051 22:56:13.204680 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8052 22:56:13.207578 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8053 22:56:13.211159 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8054 22:56:13.214706 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8055 22:56:13.215437 ==
8056 22:56:13.218430 Dram Type= 6, Freq= 0, CH_0, rank 1
8057 22:56:13.224243 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8058 22:56:13.224814 ==
8059 22:56:13.225346 DQS Delay:
8060 22:56:13.227741 DQS0 = 0, DQS1 = 0
8061 22:56:13.228209 DQM Delay:
8062 22:56:13.228584 DQM0 = 137, DQM1 = 128
8063 22:56:13.231208 DQ Delay:
8064 22:56:13.234501 DQ0 =139, DQ1 =139, DQ2 =135, DQ3 =135
8065 22:56:13.238078 DQ4 =139, DQ5 =127, DQ6 =139, DQ7 =143
8066 22:56:13.241248 DQ8 =119, DQ9 =119, DQ10 =127, DQ11 =119
8067 22:56:13.244489 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8068 22:56:13.245068
8069 22:56:13.245470
8070 22:56:13.245814 ==
8071 22:56:13.248049 Dram Type= 6, Freq= 0, CH_0, rank 1
8072 22:56:13.251609 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8073 22:56:13.252219 ==
8074 22:56:13.254276
8075 22:56:13.254734
8076 22:56:13.255095 TX Vref Scan disable
8077 22:56:13.257754 == TX Byte 0 ==
8078 22:56:13.261456 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
8079 22:56:13.264256 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8080 22:56:13.268192 == TX Byte 1 ==
8081 22:56:13.270942 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8082 22:56:13.274450 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8083 22:56:13.275016 ==
8084 22:56:13.277743 Dram Type= 6, Freq= 0, CH_0, rank 1
8085 22:56:13.284194 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8086 22:56:13.284752 ==
8087 22:56:13.297529
8088 22:56:13.300209 TX Vref early break, caculate TX vref
8089 22:56:13.303724 TX Vref=16, minBit 0, minWin=23, winSum=388
8090 22:56:13.306805 TX Vref=18, minBit 1, minWin=23, winSum=396
8091 22:56:13.310717 TX Vref=20, minBit 3, minWin=23, winSum=403
8092 22:56:13.313861 TX Vref=22, minBit 1, minWin=24, winSum=412
8093 22:56:13.316793 TX Vref=24, minBit 1, minWin=25, winSum=421
8094 22:56:13.323755 TX Vref=26, minBit 1, minWin=25, winSum=429
8095 22:56:13.327065 TX Vref=28, minBit 1, minWin=25, winSum=421
8096 22:56:13.330078 TX Vref=30, minBit 3, minWin=25, winSum=417
8097 22:56:13.333812 TX Vref=32, minBit 1, minWin=24, winSum=409
8098 22:56:13.337105 TX Vref=34, minBit 0, minWin=24, winSum=397
8099 22:56:13.343647 [TxChooseVref] Worse bit 1, Min win 25, Win sum 429, Final Vref 26
8100 22:56:13.344119
8101 22:56:13.347693 Final TX Range 0 Vref 26
8102 22:56:13.348266
8103 22:56:13.348643 ==
8104 22:56:13.350725 Dram Type= 6, Freq= 0, CH_0, rank 1
8105 22:56:13.353563 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8106 22:56:13.354040 ==
8107 22:56:13.354462
8108 22:56:13.354819
8109 22:56:13.356865 TX Vref Scan disable
8110 22:56:13.363549 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8111 22:56:13.364124 == TX Byte 0 ==
8112 22:56:13.366683 u2DelayCellOfst[0]=10 cells (3 PI)
8113 22:56:13.370027 u2DelayCellOfst[1]=13 cells (4 PI)
8114 22:56:13.373550 u2DelayCellOfst[2]=10 cells (3 PI)
8115 22:56:13.376710 u2DelayCellOfst[3]=10 cells (3 PI)
8116 22:56:13.380077 u2DelayCellOfst[4]=6 cells (2 PI)
8117 22:56:13.383215 u2DelayCellOfst[5]=0 cells (0 PI)
8118 22:56:13.386666 u2DelayCellOfst[6]=13 cells (4 PI)
8119 22:56:13.387136 u2DelayCellOfst[7]=13 cells (4 PI)
8120 22:56:13.393464 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8121 22:56:13.396574 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8122 22:56:13.397046 == TX Byte 1 ==
8123 22:56:13.400044 u2DelayCellOfst[8]=0 cells (0 PI)
8124 22:56:13.403395 u2DelayCellOfst[9]=0 cells (0 PI)
8125 22:56:13.406646 u2DelayCellOfst[10]=6 cells (2 PI)
8126 22:56:13.410416 u2DelayCellOfst[11]=3 cells (1 PI)
8127 22:56:13.413455 u2DelayCellOfst[12]=10 cells (3 PI)
8128 22:56:13.416864 u2DelayCellOfst[13]=10 cells (3 PI)
8129 22:56:13.419712 u2DelayCellOfst[14]=13 cells (4 PI)
8130 22:56:13.423586 u2DelayCellOfst[15]=10 cells (3 PI)
8131 22:56:13.426587 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8132 22:56:13.433272 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8133 22:56:13.433832 DramC Write-DBI on
8134 22:56:13.434203 ==
8135 22:56:13.436808 Dram Type= 6, Freq= 0, CH_0, rank 1
8136 22:56:13.439970 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8137 22:56:13.440442 ==
8138 22:56:13.442968
8139 22:56:13.443489
8140 22:56:13.443887 TX Vref Scan disable
8141 22:56:13.446685 == TX Byte 0 ==
8142 22:56:13.449581 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8143 22:56:13.453301 == TX Byte 1 ==
8144 22:56:13.456970 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8145 22:56:13.459979 DramC Write-DBI off
8146 22:56:13.460576
8147 22:56:13.460955 [DATLAT]
8148 22:56:13.461322 Freq=1600, CH0 RK1
8149 22:56:13.461657
8150 22:56:13.463116 DATLAT Default: 0xf
8151 22:56:13.463605 0, 0xFFFF, sum = 0
8152 22:56:13.466357 1, 0xFFFF, sum = 0
8153 22:56:13.469977 2, 0xFFFF, sum = 0
8154 22:56:13.470543 3, 0xFFFF, sum = 0
8155 22:56:13.472785 4, 0xFFFF, sum = 0
8156 22:56:13.473260 5, 0xFFFF, sum = 0
8157 22:56:13.476691 6, 0xFFFF, sum = 0
8158 22:56:13.477261 7, 0xFFFF, sum = 0
8159 22:56:13.479748 8, 0xFFFF, sum = 0
8160 22:56:13.480323 9, 0xFFFF, sum = 0
8161 22:56:13.482991 10, 0xFFFF, sum = 0
8162 22:56:13.483508 11, 0xFFFF, sum = 0
8163 22:56:13.486647 12, 0xFFFF, sum = 0
8164 22:56:13.487217 13, 0xFFFF, sum = 0
8165 22:56:13.489886 14, 0x0, sum = 1
8166 22:56:13.490361 15, 0x0, sum = 2
8167 22:56:13.492822 16, 0x0, sum = 3
8168 22:56:13.493381 17, 0x0, sum = 4
8169 22:56:13.496087 best_step = 15
8170 22:56:13.496549
8171 22:56:13.496918 ==
8172 22:56:13.499777 Dram Type= 6, Freq= 0, CH_0, rank 1
8173 22:56:13.502789 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8174 22:56:13.503262 ==
8175 22:56:13.503683 RX Vref Scan: 0
8176 22:56:13.506131
8177 22:56:13.506692 RX Vref 0 -> 0, step: 1
8178 22:56:13.507073
8179 22:56:13.509777 RX Delay 19 -> 252, step: 4
8180 22:56:13.513025 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8181 22:56:13.519857 iDelay=191, Bit 1, Center 136 (87 ~ 186) 100
8182 22:56:13.523279 iDelay=191, Bit 2, Center 132 (83 ~ 182) 100
8183 22:56:13.526527 iDelay=191, Bit 3, Center 134 (83 ~ 186) 104
8184 22:56:13.529685 iDelay=191, Bit 4, Center 136 (83 ~ 190) 108
8185 22:56:13.533002 iDelay=191, Bit 5, Center 126 (75 ~ 178) 104
8186 22:56:13.539550 iDelay=191, Bit 6, Center 138 (91 ~ 186) 96
8187 22:56:13.542729 iDelay=191, Bit 7, Center 142 (95 ~ 190) 96
8188 22:56:13.546450 iDelay=191, Bit 8, Center 118 (67 ~ 170) 104
8189 22:56:13.549683 iDelay=191, Bit 9, Center 116 (67 ~ 166) 100
8190 22:56:13.552904 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
8191 22:56:13.559880 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8192 22:56:13.562739 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8193 22:56:13.566518 iDelay=191, Bit 13, Center 134 (83 ~ 186) 104
8194 22:56:13.569920 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8195 22:56:13.573279 iDelay=191, Bit 15, Center 134 (83 ~ 186) 104
8196 22:56:13.574008 ==
8197 22:56:13.576392 Dram Type= 6, Freq= 0, CH_0, rank 1
8198 22:56:13.582912 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8199 22:56:13.583445 ==
8200 22:56:13.583832 DQS Delay:
8201 22:56:13.586063 DQS0 = 0, DQS1 = 0
8202 22:56:13.586663 DQM Delay:
8203 22:56:13.589145 DQM0 = 134, DQM1 = 127
8204 22:56:13.589643 DQ Delay:
8205 22:56:13.592530 DQ0 =134, DQ1 =136, DQ2 =132, DQ3 =134
8206 22:56:13.595829 DQ4 =136, DQ5 =126, DQ6 =138, DQ7 =142
8207 22:56:13.599585 DQ8 =118, DQ9 =116, DQ10 =128, DQ11 =118
8208 22:56:13.602844 DQ12 =134, DQ13 =134, DQ14 =136, DQ15 =134
8209 22:56:13.603267
8210 22:56:13.603650
8211 22:56:13.603966
8212 22:56:13.606143 [DramC_TX_OE_Calibration] TA2
8213 22:56:13.609611 Original DQ_B0 (3 6) =30, OEN = 27
8214 22:56:13.613043 Original DQ_B1 (3 6) =30, OEN = 27
8215 22:56:13.616331 24, 0x0, End_B0=24 End_B1=24
8216 22:56:13.616834 25, 0x0, End_B0=25 End_B1=25
8217 22:56:13.619529 26, 0x0, End_B0=26 End_B1=26
8218 22:56:13.623072 27, 0x0, End_B0=27 End_B1=27
8219 22:56:13.626183 28, 0x0, End_B0=28 End_B1=28
8220 22:56:13.629931 29, 0x0, End_B0=29 End_B1=29
8221 22:56:13.630465 30, 0x0, End_B0=30 End_B1=30
8222 22:56:13.633111 31, 0x4141, End_B0=30 End_B1=30
8223 22:56:13.636040 Byte0 end_step=30 best_step=27
8224 22:56:13.639514 Byte1 end_step=30 best_step=27
8225 22:56:13.642919 Byte0 TX OE(2T, 0.5T) = (3, 3)
8226 22:56:13.646064 Byte1 TX OE(2T, 0.5T) = (3, 3)
8227 22:56:13.646511
8228 22:56:13.646845
8229 22:56:13.653208 [DQSOSCAuto] RK1, (LSB)MR18= 0x2008, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 393 ps
8230 22:56:13.655865 CH0 RK1: MR19=303, MR18=2008
8231 22:56:13.663209 CH0_RK1: MR19=0x303, MR18=0x2008, DQSOSC=393, MR23=63, INC=23, DEC=15
8232 22:56:13.666497 [RxdqsGatingPostProcess] freq 1600
8233 22:56:13.669860 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8234 22:56:13.673007 best DQS0 dly(2T, 0.5T) = (1, 1)
8235 22:56:13.676277 best DQS1 dly(2T, 0.5T) = (1, 1)
8236 22:56:13.679636 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8237 22:56:13.682473 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8238 22:56:13.686171 best DQS0 dly(2T, 0.5T) = (1, 1)
8239 22:56:13.689308 best DQS1 dly(2T, 0.5T) = (1, 1)
8240 22:56:13.692943 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8241 22:56:13.696155 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8242 22:56:13.699862 Pre-setting of DQS Precalculation
8243 22:56:13.702798 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8244 22:56:13.703403 ==
8245 22:56:13.706273 Dram Type= 6, Freq= 0, CH_1, rank 0
8246 22:56:13.709529 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8247 22:56:13.712556 ==
8248 22:56:13.715531 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8249 22:56:13.719386 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8250 22:56:13.726261 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8251 22:56:13.728979 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8252 22:56:13.739926 [CA 0] Center 42 (12~72) winsize 61
8253 22:56:13.742719 [CA 1] Center 42 (12~72) winsize 61
8254 22:56:13.746433 [CA 2] Center 39 (10~68) winsize 59
8255 22:56:13.749473 [CA 3] Center 38 (9~67) winsize 59
8256 22:56:13.752779 [CA 4] Center 39 (10~68) winsize 59
8257 22:56:13.755973 [CA 5] Center 37 (8~67) winsize 60
8258 22:56:13.756448
8259 22:56:13.759725 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8260 22:56:13.760500
8261 22:56:13.766618 [CATrainingPosCal] consider 1 rank data
8262 22:56:13.767198 u2DelayCellTimex100 = 290/100 ps
8263 22:56:13.772664 CA0 delay=42 (12~72),Diff = 5 PI (16 cell)
8264 22:56:13.776150 CA1 delay=42 (12~72),Diff = 5 PI (16 cell)
8265 22:56:13.779400 CA2 delay=39 (10~68),Diff = 2 PI (6 cell)
8266 22:56:13.782472 CA3 delay=38 (9~67),Diff = 1 PI (3 cell)
8267 22:56:13.786175 CA4 delay=39 (10~68),Diff = 2 PI (6 cell)
8268 22:56:13.789006 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8269 22:56:13.789481
8270 22:56:13.792121 CA PerBit enable=1, Macro0, CA PI delay=37
8271 22:56:13.792594
8272 22:56:13.795617 [CBTSetCACLKResult] CA Dly = 37
8273 22:56:13.799364 CS Dly: 11 (0~42)
8274 22:56:13.802462 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8275 22:56:13.805927 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8276 22:56:13.806506 ==
8277 22:56:13.809003 Dram Type= 6, Freq= 0, CH_1, rank 1
8278 22:56:13.815785 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8279 22:56:13.816351 ==
8280 22:56:13.818557 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8281 22:56:13.825591 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8282 22:56:13.828642 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8283 22:56:13.835322 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8284 22:56:13.843185 [CA 0] Center 42 (12~72) winsize 61
8285 22:56:13.846332 [CA 1] Center 42 (12~72) winsize 61
8286 22:56:13.849424 [CA 2] Center 38 (9~68) winsize 60
8287 22:56:13.853257 [CA 3] Center 37 (8~67) winsize 60
8288 22:56:13.856026 [CA 4] Center 38 (8~68) winsize 61
8289 22:56:13.859497 [CA 5] Center 37 (8~66) winsize 59
8290 22:56:13.860066
8291 22:56:13.862988 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8292 22:56:13.863507
8293 22:56:13.866363 [CATrainingPosCal] consider 2 rank data
8294 22:56:13.869607 u2DelayCellTimex100 = 290/100 ps
8295 22:56:13.872722 CA0 delay=42 (12~72),Diff = 5 PI (16 cell)
8296 22:56:13.879483 CA1 delay=42 (12~72),Diff = 5 PI (16 cell)
8297 22:56:13.883092 CA2 delay=39 (10~68),Diff = 2 PI (6 cell)
8298 22:56:13.886116 CA3 delay=38 (9~67),Diff = 1 PI (3 cell)
8299 22:56:13.889696 CA4 delay=39 (10~68),Diff = 2 PI (6 cell)
8300 22:56:13.892717 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8301 22:56:13.893183
8302 22:56:13.896157 CA PerBit enable=1, Macro0, CA PI delay=37
8303 22:56:13.896626
8304 22:56:13.899407 [CBTSetCACLKResult] CA Dly = 37
8305 22:56:13.902513 CS Dly: 12 (0~45)
8306 22:56:13.906095 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8307 22:56:13.909103 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8308 22:56:13.909570
8309 22:56:13.912490 ----->DramcWriteLeveling(PI) begin...
8310 22:56:13.912954 ==
8311 22:56:13.915726 Dram Type= 6, Freq= 0, CH_1, rank 0
8312 22:56:13.922334 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8313 22:56:13.922796 ==
8314 22:56:13.925581 Write leveling (Byte 0): 25 => 25
8315 22:56:13.926041 Write leveling (Byte 1): 28 => 28
8316 22:56:13.929119 DramcWriteLeveling(PI) end<-----
8317 22:56:13.929531
8318 22:56:13.932346 ==
8319 22:56:13.932761 Dram Type= 6, Freq= 0, CH_1, rank 0
8320 22:56:13.939217 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8321 22:56:13.939681 ==
8322 22:56:13.942413 [Gating] SW mode calibration
8323 22:56:13.949119 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8324 22:56:13.952820 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8325 22:56:13.958885 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8326 22:56:13.962631 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8327 22:56:13.965840 1 4 8 | B1->B0 | 2322 2626 | 1 0 | (0 0) (0 0)
8328 22:56:13.972123 1 4 12 | B1->B0 | 3030 3434 | 1 1 | (0 0) (1 1)
8329 22:56:13.975406 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8330 22:56:13.978877 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8331 22:56:13.985488 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8332 22:56:13.989240 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8333 22:56:13.991875 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8334 22:56:13.998962 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8335 22:56:14.002177 1 5 8 | B1->B0 | 3434 2c2c | 1 0 | (1 0) (0 1)
8336 22:56:14.006231 1 5 12 | B1->B0 | 2b2b 2323 | 0 0 | (0 1) (1 0)
8337 22:56:14.011855 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8338 22:56:14.015543 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8339 22:56:14.018743 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8340 22:56:14.025338 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8341 22:56:14.028857 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8342 22:56:14.031835 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8343 22:56:14.035236 1 6 8 | B1->B0 | 2424 3f3f | 0 0 | (0 0) (0 0)
8344 22:56:14.042516 1 6 12 | B1->B0 | 4444 4646 | 1 0 | (0 0) (0 0)
8345 22:56:14.045382 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8346 22:56:14.048877 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8347 22:56:14.055769 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8348 22:56:14.058674 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8349 22:56:14.062582 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8350 22:56:14.068610 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8351 22:56:14.071845 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8352 22:56:14.075649 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8353 22:56:14.082118 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8354 22:56:14.085336 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8355 22:56:14.088761 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8356 22:56:14.095548 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8357 22:56:14.098957 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8358 22:56:14.102306 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8359 22:56:14.108772 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8360 22:56:14.112386 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8361 22:56:14.115653 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8362 22:56:14.121771 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8363 22:56:14.125168 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8364 22:56:14.128436 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8365 22:56:14.135048 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8366 22:56:14.138576 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8367 22:56:14.141688 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8368 22:56:14.144929 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8369 22:56:14.151749 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8370 22:56:14.155636 Total UI for P1: 0, mck2ui 16
8371 22:56:14.158538 best dqsien dly found for B0: ( 1, 9, 10)
8372 22:56:14.161741 Total UI for P1: 0, mck2ui 16
8373 22:56:14.164897 best dqsien dly found for B1: ( 1, 9, 10)
8374 22:56:14.168643 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8375 22:56:14.171594 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8376 22:56:14.172063
8377 22:56:14.175205 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8378 22:56:14.178063 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8379 22:56:14.181283 [Gating] SW calibration Done
8380 22:56:14.181747 ==
8381 22:56:14.184575 Dram Type= 6, Freq= 0, CH_1, rank 0
8382 22:56:14.188695 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8383 22:56:14.189272 ==
8384 22:56:14.191417 RX Vref Scan: 0
8385 22:56:14.191887
8386 22:56:14.195232 RX Vref 0 -> 0, step: 1
8387 22:56:14.195834
8388 22:56:14.196210 RX Delay 0 -> 252, step: 8
8389 22:56:14.202066 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8390 22:56:14.205175 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8391 22:56:14.208537 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8392 22:56:14.211455 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8393 22:56:14.214715 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8394 22:56:14.221461 iDelay=200, Bit 5, Center 151 (104 ~ 199) 96
8395 22:56:14.224894 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8396 22:56:14.228717 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8397 22:56:14.231115 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8398 22:56:14.235219 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8399 22:56:14.237836 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8400 22:56:14.244863 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8401 22:56:14.247883 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8402 22:56:14.251412 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8403 22:56:14.254729 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8404 22:56:14.261518 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8405 22:56:14.262085 ==
8406 22:56:14.264831 Dram Type= 6, Freq= 0, CH_1, rank 0
8407 22:56:14.267940 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8408 22:56:14.268505 ==
8409 22:56:14.268881 DQS Delay:
8410 22:56:14.271360 DQS0 = 0, DQS1 = 0
8411 22:56:14.271829 DQM Delay:
8412 22:56:14.274490 DQM0 = 137, DQM1 = 132
8413 22:56:14.274950 DQ Delay:
8414 22:56:14.278370 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8415 22:56:14.281311 DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135
8416 22:56:14.284734 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8417 22:56:14.288231 DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =139
8418 22:56:14.288804
8419 22:56:14.289181
8420 22:56:14.291443 ==
8421 22:56:14.291916 Dram Type= 6, Freq= 0, CH_1, rank 0
8422 22:56:14.297938 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8423 22:56:14.298408 ==
8424 22:56:14.298779
8425 22:56:14.299121
8426 22:56:14.299480 TX Vref Scan disable
8427 22:56:14.302357 == TX Byte 0 ==
8428 22:56:14.305181 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8429 22:56:14.308440 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8430 22:56:14.311920 == TX Byte 1 ==
8431 22:56:14.315378 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8432 22:56:14.321821 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8433 22:56:14.322373 ==
8434 22:56:14.325092 Dram Type= 6, Freq= 0, CH_1, rank 0
8435 22:56:14.327989 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8436 22:56:14.328462 ==
8437 22:56:14.340643
8438 22:56:14.343946 TX Vref early break, caculate TX vref
8439 22:56:14.347473 TX Vref=16, minBit 9, minWin=22, winSum=375
8440 22:56:14.350848 TX Vref=18, minBit 1, minWin=23, winSum=387
8441 22:56:14.354274 TX Vref=20, minBit 1, minWin=23, winSum=395
8442 22:56:14.357535 TX Vref=22, minBit 3, minWin=24, winSum=406
8443 22:56:14.360960 TX Vref=24, minBit 0, minWin=25, winSum=414
8444 22:56:14.367256 TX Vref=26, minBit 0, minWin=25, winSum=423
8445 22:56:14.370581 TX Vref=28, minBit 0, minWin=26, winSum=429
8446 22:56:14.373944 TX Vref=30, minBit 0, minWin=25, winSum=416
8447 22:56:14.377317 TX Vref=32, minBit 0, minWin=24, winSum=414
8448 22:56:14.381025 TX Vref=34, minBit 0, minWin=24, winSum=402
8449 22:56:14.387199 [TxChooseVref] Worse bit 0, Min win 26, Win sum 429, Final Vref 28
8450 22:56:14.387713
8451 22:56:14.390324 Final TX Range 0 Vref 28
8452 22:56:14.390789
8453 22:56:14.391158 ==
8454 22:56:14.393621 Dram Type= 6, Freq= 0, CH_1, rank 0
8455 22:56:14.397495 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8456 22:56:14.398061 ==
8457 22:56:14.398437
8458 22:56:14.398784
8459 22:56:14.400483 TX Vref Scan disable
8460 22:56:14.406986 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8461 22:56:14.407479 == TX Byte 0 ==
8462 22:56:14.410337 u2DelayCellOfst[0]=20 cells (6 PI)
8463 22:56:14.413774 u2DelayCellOfst[1]=13 cells (4 PI)
8464 22:56:14.416969 u2DelayCellOfst[2]=0 cells (0 PI)
8465 22:56:14.420327 u2DelayCellOfst[3]=10 cells (3 PI)
8466 22:56:14.423408 u2DelayCellOfst[4]=13 cells (4 PI)
8467 22:56:14.427010 u2DelayCellOfst[5]=20 cells (6 PI)
8468 22:56:14.430178 u2DelayCellOfst[6]=23 cells (7 PI)
8469 22:56:14.433414 u2DelayCellOfst[7]=10 cells (3 PI)
8470 22:56:14.436723 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8471 22:56:14.439921 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8472 22:56:14.443260 == TX Byte 1 ==
8473 22:56:14.446746 u2DelayCellOfst[8]=0 cells (0 PI)
8474 22:56:14.447307 u2DelayCellOfst[9]=3 cells (1 PI)
8475 22:56:14.449900 u2DelayCellOfst[10]=13 cells (4 PI)
8476 22:56:14.453008 u2DelayCellOfst[11]=3 cells (1 PI)
8477 22:56:14.456454 u2DelayCellOfst[12]=16 cells (5 PI)
8478 22:56:14.459880 u2DelayCellOfst[13]=16 cells (5 PI)
8479 22:56:14.463312 u2DelayCellOfst[14]=16 cells (5 PI)
8480 22:56:14.466793 u2DelayCellOfst[15]=16 cells (5 PI)
8481 22:56:14.469894 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8482 22:56:14.476631 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8483 22:56:14.477182 DramC Write-DBI on
8484 22:56:14.477554 ==
8485 22:56:14.480208 Dram Type= 6, Freq= 0, CH_1, rank 0
8486 22:56:14.486803 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8487 22:56:14.487385 ==
8488 22:56:14.487798
8489 22:56:14.488145
8490 22:56:14.488474 TX Vref Scan disable
8491 22:56:14.490075 == TX Byte 0 ==
8492 22:56:14.493116 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8493 22:56:14.496655 == TX Byte 1 ==
8494 22:56:14.500056 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8495 22:56:14.503488 DramC Write-DBI off
8496 22:56:14.504045
8497 22:56:14.504415 [DATLAT]
8498 22:56:14.504759 Freq=1600, CH1 RK0
8499 22:56:14.505097
8500 22:56:14.506895 DATLAT Default: 0xf
8501 22:56:14.507383 0, 0xFFFF, sum = 0
8502 22:56:14.510343 1, 0xFFFF, sum = 0
8503 22:56:14.510818 2, 0xFFFF, sum = 0
8504 22:56:14.514119 3, 0xFFFF, sum = 0
8505 22:56:14.516908 4, 0xFFFF, sum = 0
8506 22:56:14.517481 5, 0xFFFF, sum = 0
8507 22:56:14.520453 6, 0xFFFF, sum = 0
8508 22:56:14.521020 7, 0xFFFF, sum = 0
8509 22:56:14.523392 8, 0xFFFF, sum = 0
8510 22:56:14.523868 9, 0xFFFF, sum = 0
8511 22:56:14.526793 10, 0xFFFF, sum = 0
8512 22:56:14.527398 11, 0xFFFF, sum = 0
8513 22:56:14.530214 12, 0xFFFF, sum = 0
8514 22:56:14.530786 13, 0xFFFF, sum = 0
8515 22:56:14.533522 14, 0x0, sum = 1
8516 22:56:14.534090 15, 0x0, sum = 2
8517 22:56:14.536624 16, 0x0, sum = 3
8518 22:56:14.537094 17, 0x0, sum = 4
8519 22:56:14.540103 best_step = 15
8520 22:56:14.540567
8521 22:56:14.540935 ==
8522 22:56:14.543599 Dram Type= 6, Freq= 0, CH_1, rank 0
8523 22:56:14.546596 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8524 22:56:14.547161 ==
8525 22:56:14.547571 RX Vref Scan: 1
8526 22:56:14.550022
8527 22:56:14.550584 Set Vref Range= 24 -> 127
8528 22:56:14.550956
8529 22:56:14.553433 RX Vref 24 -> 127, step: 1
8530 22:56:14.553896
8531 22:56:14.556818 RX Delay 27 -> 252, step: 4
8532 22:56:14.557286
8533 22:56:14.560075 Set Vref, RX VrefLevel [Byte0]: 24
8534 22:56:14.563856 [Byte1]: 24
8535 22:56:14.564426
8536 22:56:14.566493 Set Vref, RX VrefLevel [Byte0]: 25
8537 22:56:14.569758 [Byte1]: 25
8538 22:56:14.570227
8539 22:56:14.573448 Set Vref, RX VrefLevel [Byte0]: 26
8540 22:56:14.576786 [Byte1]: 26
8541 22:56:14.580029
8542 22:56:14.580589 Set Vref, RX VrefLevel [Byte0]: 27
8543 22:56:14.583560 [Byte1]: 27
8544 22:56:14.588271
8545 22:56:14.588829 Set Vref, RX VrefLevel [Byte0]: 28
8546 22:56:14.591386 [Byte1]: 28
8547 22:56:14.595807
8548 22:56:14.596358 Set Vref, RX VrefLevel [Byte0]: 29
8549 22:56:14.598827 [Byte1]: 29
8550 22:56:14.602908
8551 22:56:14.603402 Set Vref, RX VrefLevel [Byte0]: 30
8552 22:56:14.606332 [Byte1]: 30
8553 22:56:14.611097
8554 22:56:14.611680 Set Vref, RX VrefLevel [Byte0]: 31
8555 22:56:14.614025 [Byte1]: 31
8556 22:56:14.618282
8557 22:56:14.618838 Set Vref, RX VrefLevel [Byte0]: 32
8558 22:56:14.621653 [Byte1]: 32
8559 22:56:14.626217
8560 22:56:14.626774 Set Vref, RX VrefLevel [Byte0]: 33
8561 22:56:14.628908 [Byte1]: 33
8562 22:56:14.633068
8563 22:56:14.633625 Set Vref, RX VrefLevel [Byte0]: 34
8564 22:56:14.636491 [Byte1]: 34
8565 22:56:14.640415
8566 22:56:14.640879 Set Vref, RX VrefLevel [Byte0]: 35
8567 22:56:14.643743 [Byte1]: 35
8568 22:56:14.648069
8569 22:56:14.648641 Set Vref, RX VrefLevel [Byte0]: 36
8570 22:56:14.651124 [Byte1]: 36
8571 22:56:14.655560
8572 22:56:14.656022 Set Vref, RX VrefLevel [Byte0]: 37
8573 22:56:14.658765 [Byte1]: 37
8574 22:56:14.663479
8575 22:56:14.664034 Set Vref, RX VrefLevel [Byte0]: 38
8576 22:56:14.666684 [Byte1]: 38
8577 22:56:14.670605
8578 22:56:14.671075 Set Vref, RX VrefLevel [Byte0]: 39
8579 22:56:14.673890 [Byte1]: 39
8580 22:56:14.678628
8581 22:56:14.679192 Set Vref, RX VrefLevel [Byte0]: 40
8582 22:56:14.681295 [Byte1]: 40
8583 22:56:14.685741
8584 22:56:14.686204 Set Vref, RX VrefLevel [Byte0]: 41
8585 22:56:14.688958 [Byte1]: 41
8586 22:56:14.693422
8587 22:56:14.693886 Set Vref, RX VrefLevel [Byte0]: 42
8588 22:56:14.697336 [Byte1]: 42
8589 22:56:14.700823
8590 22:56:14.701380 Set Vref, RX VrefLevel [Byte0]: 43
8591 22:56:14.704361 [Byte1]: 43
8592 22:56:14.708524
8593 22:56:14.709082 Set Vref, RX VrefLevel [Byte0]: 44
8594 22:56:14.711404 [Byte1]: 44
8595 22:56:14.715922
8596 22:56:14.716500 Set Vref, RX VrefLevel [Byte0]: 45
8597 22:56:14.718980 [Byte1]: 45
8598 22:56:14.723414
8599 22:56:14.727075 Set Vref, RX VrefLevel [Byte0]: 46
8600 22:56:14.727680 [Byte1]: 46
8601 22:56:14.731154
8602 22:56:14.731760 Set Vref, RX VrefLevel [Byte0]: 47
8603 22:56:14.734473 [Byte1]: 47
8604 22:56:14.738552
8605 22:56:14.739018 Set Vref, RX VrefLevel [Byte0]: 48
8606 22:56:14.742032 [Byte1]: 48
8607 22:56:14.746054
8608 22:56:14.746606 Set Vref, RX VrefLevel [Byte0]: 49
8609 22:56:14.749078 [Byte1]: 49
8610 22:56:14.753492
8611 22:56:14.753956 Set Vref, RX VrefLevel [Byte0]: 50
8612 22:56:14.756798 [Byte1]: 50
8613 22:56:14.761310
8614 22:56:14.761866 Set Vref, RX VrefLevel [Byte0]: 51
8615 22:56:14.764283 [Byte1]: 51
8616 22:56:14.768569
8617 22:56:14.769034 Set Vref, RX VrefLevel [Byte0]: 52
8618 22:56:14.771531 [Byte1]: 52
8619 22:56:14.776445
8620 22:56:14.776918 Set Vref, RX VrefLevel [Byte0]: 53
8621 22:56:14.779064 [Byte1]: 53
8622 22:56:14.783562
8623 22:56:14.783979 Set Vref, RX VrefLevel [Byte0]: 54
8624 22:56:14.787101 [Byte1]: 54
8625 22:56:14.791267
8626 22:56:14.791824 Set Vref, RX VrefLevel [Byte0]: 55
8627 22:56:14.794870 [Byte1]: 55
8628 22:56:14.798794
8629 22:56:14.799382 Set Vref, RX VrefLevel [Byte0]: 56
8630 22:56:14.802498 [Byte1]: 56
8631 22:56:14.806676
8632 22:56:14.807234 Set Vref, RX VrefLevel [Byte0]: 57
8633 22:56:14.809374 [Byte1]: 57
8634 22:56:14.814096
8635 22:56:14.814659 Set Vref, RX VrefLevel [Byte0]: 58
8636 22:56:14.817134 [Byte1]: 58
8637 22:56:14.821470
8638 22:56:14.822028 Set Vref, RX VrefLevel [Byte0]: 59
8639 22:56:14.824276 [Byte1]: 59
8640 22:56:14.828849
8641 22:56:14.829385 Set Vref, RX VrefLevel [Byte0]: 60
8642 22:56:14.832161 [Byte1]: 60
8643 22:56:14.836259
8644 22:56:14.836720 Set Vref, RX VrefLevel [Byte0]: 61
8645 22:56:14.839497 [Byte1]: 61
8646 22:56:14.843618
8647 22:56:14.844119 Set Vref, RX VrefLevel [Byte0]: 62
8648 22:56:14.847449 [Byte1]: 62
8649 22:56:14.851620
8650 22:56:14.852141 Set Vref, RX VrefLevel [Byte0]: 63
8651 22:56:14.854510 [Byte1]: 63
8652 22:56:14.858932
8653 22:56:14.859575 Set Vref, RX VrefLevel [Byte0]: 64
8654 22:56:14.862228 [Byte1]: 64
8655 22:56:14.866223
8656 22:56:14.866640 Set Vref, RX VrefLevel [Byte0]: 65
8657 22:56:14.869659 [Byte1]: 65
8658 22:56:14.873562
8659 22:56:14.874141 Set Vref, RX VrefLevel [Byte0]: 66
8660 22:56:14.876983 [Byte1]: 66
8661 22:56:14.881410
8662 22:56:14.881943 Set Vref, RX VrefLevel [Byte0]: 67
8663 22:56:14.884718 [Byte1]: 67
8664 22:56:14.889163
8665 22:56:14.889578 Set Vref, RX VrefLevel [Byte0]: 68
8666 22:56:14.892054 [Byte1]: 68
8667 22:56:14.896939
8668 22:56:14.897458 Set Vref, RX VrefLevel [Byte0]: 69
8669 22:56:14.899830 [Byte1]: 69
8670 22:56:14.904090
8671 22:56:14.904594 Set Vref, RX VrefLevel [Byte0]: 70
8672 22:56:14.907775 [Byte1]: 70
8673 22:56:14.911747
8674 22:56:14.912165 Set Vref, RX VrefLevel [Byte0]: 71
8675 22:56:14.914733 [Byte1]: 71
8676 22:56:14.919258
8677 22:56:14.919822 Set Vref, RX VrefLevel [Byte0]: 72
8678 22:56:14.922562 [Byte1]: 72
8679 22:56:14.926886
8680 22:56:14.927501 Set Vref, RX VrefLevel [Byte0]: 73
8681 22:56:14.929964 [Byte1]: 73
8682 22:56:14.934225
8683 22:56:14.934694 Final RX Vref Byte 0 = 57 to rank0
8684 22:56:14.937824 Final RX Vref Byte 1 = 56 to rank0
8685 22:56:14.941523 Final RX Vref Byte 0 = 57 to rank1
8686 22:56:14.944387 Final RX Vref Byte 1 = 56 to rank1==
8687 22:56:14.948237 Dram Type= 6, Freq= 0, CH_1, rank 0
8688 22:56:14.954076 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8689 22:56:14.954626 ==
8690 22:56:14.954996 DQS Delay:
8691 22:56:14.955375 DQS0 = 0, DQS1 = 0
8692 22:56:14.957494 DQM Delay:
8693 22:56:14.957951 DQM0 = 134, DQM1 = 131
8694 22:56:14.960785 DQ Delay:
8695 22:56:14.964299 DQ0 =140, DQ1 =128, DQ2 =124, DQ3 =130
8696 22:56:14.967694 DQ4 =134, DQ5 =144, DQ6 =144, DQ7 =132
8697 22:56:14.971179 DQ8 =116, DQ9 =122, DQ10 =132, DQ11 =124
8698 22:56:14.974659 DQ12 =138, DQ13 =140, DQ14 =140, DQ15 =140
8699 22:56:14.975268
8700 22:56:14.975697
8701 22:56:14.976041
8702 22:56:14.977532 [DramC_TX_OE_Calibration] TA2
8703 22:56:14.980919 Original DQ_B0 (3 6) =30, OEN = 27
8704 22:56:14.984293 Original DQ_B1 (3 6) =30, OEN = 27
8705 22:56:14.987630 24, 0x0, End_B0=24 End_B1=24
8706 22:56:14.988198 25, 0x0, End_B0=25 End_B1=25
8707 22:56:14.991438 26, 0x0, End_B0=26 End_B1=26
8708 22:56:14.994338 27, 0x0, End_B0=27 End_B1=27
8709 22:56:14.997653 28, 0x0, End_B0=28 End_B1=28
8710 22:56:14.998223 29, 0x0, End_B0=29 End_B1=29
8711 22:56:15.001070 30, 0x0, End_B0=30 End_B1=30
8712 22:56:15.004223 31, 0x4141, End_B0=30 End_B1=30
8713 22:56:15.007700 Byte0 end_step=30 best_step=27
8714 22:56:15.011002 Byte1 end_step=30 best_step=27
8715 22:56:15.014394 Byte0 TX OE(2T, 0.5T) = (3, 3)
8716 22:56:15.014865 Byte1 TX OE(2T, 0.5T) = (3, 3)
8717 22:56:15.015232
8718 22:56:15.018030
8719 22:56:15.024775 [DQSOSCAuto] RK0, (LSB)MR18= 0x1926, (MSB)MR19= 0x303, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
8720 22:56:15.027593 CH1 RK0: MR19=303, MR18=1926
8721 22:56:15.034606 CH1_RK0: MR19=0x303, MR18=0x1926, DQSOSC=390, MR23=63, INC=24, DEC=16
8722 22:56:15.035168
8723 22:56:15.037310 ----->DramcWriteLeveling(PI) begin...
8724 22:56:15.037777 ==
8725 22:56:15.040692 Dram Type= 6, Freq= 0, CH_1, rank 1
8726 22:56:15.044005 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8727 22:56:15.044472 ==
8728 22:56:15.047683 Write leveling (Byte 0): 24 => 24
8729 22:56:15.050893 Write leveling (Byte 1): 27 => 27
8730 22:56:15.053685 DramcWriteLeveling(PI) end<-----
8731 22:56:15.054205
8732 22:56:15.054583 ==
8733 22:56:15.057877 Dram Type= 6, Freq= 0, CH_1, rank 1
8734 22:56:15.060946 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8735 22:56:15.061505 ==
8736 22:56:15.064103 [Gating] SW mode calibration
8737 22:56:15.070798 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8738 22:56:15.077400 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8739 22:56:15.080514 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8740 22:56:15.084164 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8741 22:56:15.090879 1 4 8 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
8742 22:56:15.094057 1 4 12 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 1)
8743 22:56:15.097638 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8744 22:56:15.104120 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8745 22:56:15.107093 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8746 22:56:15.110791 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8747 22:56:15.116876 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8748 22:56:15.120455 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8749 22:56:15.124155 1 5 8 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 1)
8750 22:56:15.130877 1 5 12 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
8751 22:56:15.133929 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
8752 22:56:15.137377 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8753 22:56:15.144012 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8754 22:56:15.147572 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8755 22:56:15.150764 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8756 22:56:15.157523 1 6 4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
8757 22:56:15.160913 1 6 8 | B1->B0 | 3c3c 2323 | 0 0 | (0 0) (0 0)
8758 22:56:15.163859 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8759 22:56:15.167033 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8760 22:56:15.174118 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8761 22:56:15.177714 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8762 22:56:15.180682 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8763 22:56:15.187375 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8764 22:56:15.190699 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8765 22:56:15.193505 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8766 22:56:15.200716 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8767 22:56:15.203465 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8768 22:56:15.207122 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8769 22:56:15.213760 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8770 22:56:15.216800 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8771 22:56:15.220603 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8772 22:56:15.227212 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8773 22:56:15.230422 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8774 22:56:15.234031 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8775 22:56:15.240795 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8776 22:56:15.243527 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8777 22:56:15.247097 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8778 22:56:15.253667 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8779 22:56:15.257392 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8780 22:56:15.260510 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8781 22:56:15.264303 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8782 22:56:15.270856 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8783 22:56:15.274128 Total UI for P1: 0, mck2ui 16
8784 22:56:15.277088 best dqsien dly found for B1: ( 1, 9, 6)
8785 22:56:15.280364 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8786 22:56:15.283998 Total UI for P1: 0, mck2ui 16
8787 22:56:15.287175 best dqsien dly found for B0: ( 1, 9, 12)
8788 22:56:15.290381 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8789 22:56:15.293624 best DQS1 dly(MCK, UI, PI) = (1, 9, 6)
8790 22:56:15.294095
8791 22:56:15.297222 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8792 22:56:15.300330 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 6)
8793 22:56:15.304139 [Gating] SW calibration Done
8794 22:56:15.304763 ==
8795 22:56:15.307152 Dram Type= 6, Freq= 0, CH_1, rank 1
8796 22:56:15.314000 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8797 22:56:15.314623 ==
8798 22:56:15.314999 RX Vref Scan: 0
8799 22:56:15.315386
8800 22:56:15.317134 RX Vref 0 -> 0, step: 1
8801 22:56:15.317597
8802 22:56:15.320561 RX Delay 0 -> 252, step: 8
8803 22:56:15.323953 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8804 22:56:15.326950 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8805 22:56:15.330859 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8806 22:56:15.333890 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8807 22:56:15.340006 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8808 22:56:15.343542 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8809 22:56:15.347157 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8810 22:56:15.350356 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8811 22:56:15.353890 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8812 22:56:15.357684 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8813 22:56:15.363766 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8814 22:56:15.367189 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8815 22:56:15.370569 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8816 22:56:15.373963 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8817 22:56:15.380557 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8818 22:56:15.383712 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8819 22:56:15.384275 ==
8820 22:56:15.386949 Dram Type= 6, Freq= 0, CH_1, rank 1
8821 22:56:15.390110 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8822 22:56:15.390576 ==
8823 22:56:15.393427 DQS Delay:
8824 22:56:15.393887 DQS0 = 0, DQS1 = 0
8825 22:56:15.394256 DQM Delay:
8826 22:56:15.397113 DQM0 = 136, DQM1 = 133
8827 22:56:15.397738 DQ Delay:
8828 22:56:15.400231 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8829 22:56:15.403959 DQ4 =131, DQ5 =151, DQ6 =143, DQ7 =135
8830 22:56:15.406759 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =127
8831 22:56:15.413903 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8832 22:56:15.414474
8833 22:56:15.414849
8834 22:56:15.415396 ==
8835 22:56:15.416972 Dram Type= 6, Freq= 0, CH_1, rank 1
8836 22:56:15.420454 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8837 22:56:15.421018 ==
8838 22:56:15.421393
8839 22:56:15.421735
8840 22:56:15.423639 TX Vref Scan disable
8841 22:56:15.424101 == TX Byte 0 ==
8842 22:56:15.430225 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8843 22:56:15.433777 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8844 22:56:15.434349 == TX Byte 1 ==
8845 22:56:15.440120 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8846 22:56:15.443238 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8847 22:56:15.443768 ==
8848 22:56:15.446864 Dram Type= 6, Freq= 0, CH_1, rank 1
8849 22:56:15.449953 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8850 22:56:15.450520 ==
8851 22:56:15.464621
8852 22:56:15.467874 TX Vref early break, caculate TX vref
8853 22:56:15.471375 TX Vref=16, minBit 0, minWin=23, winSum=388
8854 22:56:15.475009 TX Vref=18, minBit 0, minWin=24, winSum=393
8855 22:56:15.477761 TX Vref=20, minBit 0, minWin=24, winSum=408
8856 22:56:15.481425 TX Vref=22, minBit 0, minWin=25, winSum=413
8857 22:56:15.484633 TX Vref=24, minBit 0, minWin=25, winSum=421
8858 22:56:15.491430 TX Vref=26, minBit 6, minWin=25, winSum=427
8859 22:56:15.494374 TX Vref=28, minBit 6, minWin=25, winSum=426
8860 22:56:15.497691 TX Vref=30, minBit 0, minWin=25, winSum=419
8861 22:56:15.501258 TX Vref=32, minBit 0, minWin=25, winSum=416
8862 22:56:15.504781 TX Vref=34, minBit 0, minWin=25, winSum=412
8863 22:56:15.508241 TX Vref=36, minBit 0, minWin=24, winSum=402
8864 22:56:15.514950 [TxChooseVref] Worse bit 6, Min win 25, Win sum 427, Final Vref 26
8865 22:56:15.515534
8866 22:56:15.517967 Final TX Range 0 Vref 26
8867 22:56:15.518465
8868 22:56:15.518839 ==
8869 22:56:15.520980 Dram Type= 6, Freq= 0, CH_1, rank 1
8870 22:56:15.524341 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8871 22:56:15.524817 ==
8872 22:56:15.525187
8873 22:56:15.525532
8874 22:56:15.527634 TX Vref Scan disable
8875 22:56:15.534372 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8876 22:56:15.534842 == TX Byte 0 ==
8877 22:56:15.537877 u2DelayCellOfst[0]=16 cells (5 PI)
8878 22:56:15.541120 u2DelayCellOfst[1]=13 cells (4 PI)
8879 22:56:15.544317 u2DelayCellOfst[2]=0 cells (0 PI)
8880 22:56:15.547569 u2DelayCellOfst[3]=6 cells (2 PI)
8881 22:56:15.551458 u2DelayCellOfst[4]=10 cells (3 PI)
8882 22:56:15.554911 u2DelayCellOfst[5]=16 cells (5 PI)
8883 22:56:15.557921 u2DelayCellOfst[6]=16 cells (5 PI)
8884 22:56:15.560908 u2DelayCellOfst[7]=3 cells (1 PI)
8885 22:56:15.564612 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8886 22:56:15.567923 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8887 22:56:15.571173 == TX Byte 1 ==
8888 22:56:15.574490 u2DelayCellOfst[8]=0 cells (0 PI)
8889 22:56:15.575048 u2DelayCellOfst[9]=6 cells (2 PI)
8890 22:56:15.578037 u2DelayCellOfst[10]=13 cells (4 PI)
8891 22:56:15.581328 u2DelayCellOfst[11]=6 cells (2 PI)
8892 22:56:15.584426 u2DelayCellOfst[12]=16 cells (5 PI)
8893 22:56:15.587949 u2DelayCellOfst[13]=16 cells (5 PI)
8894 22:56:15.591193 u2DelayCellOfst[14]=20 cells (6 PI)
8895 22:56:15.594279 u2DelayCellOfst[15]=20 cells (6 PI)
8896 22:56:15.597974 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8897 22:56:15.604655 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8898 22:56:15.605220 DramC Write-DBI on
8899 22:56:15.605601 ==
8900 22:56:15.608002 Dram Type= 6, Freq= 0, CH_1, rank 1
8901 22:56:15.611250 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8902 22:56:15.614224 ==
8903 22:56:15.614781
8904 22:56:15.615155
8905 22:56:15.615539 TX Vref Scan disable
8906 22:56:15.617712 == TX Byte 0 ==
8907 22:56:15.621925 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8908 22:56:15.624609 == TX Byte 1 ==
8909 22:56:15.627754 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8910 22:56:15.631061 DramC Write-DBI off
8911 22:56:15.631573
8912 22:56:15.631941 [DATLAT]
8913 22:56:15.632288 Freq=1600, CH1 RK1
8914 22:56:15.632624
8915 22:56:15.634373 DATLAT Default: 0xf
8916 22:56:15.634833 0, 0xFFFF, sum = 0
8917 22:56:15.637837 1, 0xFFFF, sum = 0
8918 22:56:15.638387 2, 0xFFFF, sum = 0
8919 22:56:15.641723 3, 0xFFFF, sum = 0
8920 22:56:15.644460 4, 0xFFFF, sum = 0
8921 22:56:15.644932 5, 0xFFFF, sum = 0
8922 22:56:15.647899 6, 0xFFFF, sum = 0
8923 22:56:15.648368 7, 0xFFFF, sum = 0
8924 22:56:15.651299 8, 0xFFFF, sum = 0
8925 22:56:15.651810 9, 0xFFFF, sum = 0
8926 22:56:15.654474 10, 0xFFFF, sum = 0
8927 22:56:15.655041 11, 0xFFFF, sum = 0
8928 22:56:15.658181 12, 0xFFFF, sum = 0
8929 22:56:15.658746 13, 0xFFFF, sum = 0
8930 22:56:15.660979 14, 0x0, sum = 1
8931 22:56:15.661450 15, 0x0, sum = 2
8932 22:56:15.664726 16, 0x0, sum = 3
8933 22:56:15.665293 17, 0x0, sum = 4
8934 22:56:15.668012 best_step = 15
8935 22:56:15.668469
8936 22:56:15.668831 ==
8937 22:56:15.671246 Dram Type= 6, Freq= 0, CH_1, rank 1
8938 22:56:15.675030 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8939 22:56:15.675651 ==
8940 22:56:15.677681 RX Vref Scan: 0
8941 22:56:15.678241
8942 22:56:15.678664 RX Vref 0 -> 0, step: 1
8943 22:56:15.679177
8944 22:56:15.681383 RX Delay 19 -> 252, step: 4
8945 22:56:15.684423 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
8946 22:56:15.691270 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
8947 22:56:15.694109 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
8948 22:56:15.697716 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
8949 22:56:15.701086 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
8950 22:56:15.704780 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
8951 22:56:15.707795 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
8952 22:56:15.714063 iDelay=195, Bit 7, Center 134 (83 ~ 186) 104
8953 22:56:15.717670 iDelay=195, Bit 8, Center 118 (67 ~ 170) 104
8954 22:56:15.721110 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8955 22:56:15.724222 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
8956 22:56:15.730390 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
8957 22:56:15.733904 iDelay=195, Bit 12, Center 140 (87 ~ 194) 108
8958 22:56:15.737206 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
8959 22:56:15.740961 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
8960 22:56:15.743899 iDelay=195, Bit 15, Center 140 (91 ~ 190) 100
8961 22:56:15.744599 ==
8962 22:56:15.747444 Dram Type= 6, Freq= 0, CH_1, rank 1
8963 22:56:15.754429 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8964 22:56:15.755000 ==
8965 22:56:15.755436 DQS Delay:
8966 22:56:15.757372 DQS0 = 0, DQS1 = 0
8967 22:56:15.757931 DQM Delay:
8968 22:56:15.760367 DQM0 = 134, DQM1 = 130
8969 22:56:15.760838 DQ Delay:
8970 22:56:15.764070 DQ0 =138, DQ1 =130, DQ2 =122, DQ3 =130
8971 22:56:15.767549 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =134
8972 22:56:15.771175 DQ8 =118, DQ9 =118, DQ10 =132, DQ11 =124
8973 22:56:15.774217 DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =140
8974 22:56:15.774779
8975 22:56:15.775150
8976 22:56:15.775620
8977 22:56:15.777013 [DramC_TX_OE_Calibration] TA2
8978 22:56:15.780862 Original DQ_B0 (3 6) =30, OEN = 27
8979 22:56:15.784138 Original DQ_B1 (3 6) =30, OEN = 27
8980 22:56:15.787226 24, 0x0, End_B0=24 End_B1=24
8981 22:56:15.790585 25, 0x0, End_B0=25 End_B1=25
8982 22:56:15.791154 26, 0x0, End_B0=26 End_B1=26
8983 22:56:15.793613 27, 0x0, End_B0=27 End_B1=27
8984 22:56:15.797555 28, 0x0, End_B0=28 End_B1=28
8985 22:56:15.800579 29, 0x0, End_B0=29 End_B1=29
8986 22:56:15.801146 30, 0x0, End_B0=30 End_B1=30
8987 22:56:15.804140 31, 0x4545, End_B0=30 End_B1=30
8988 22:56:15.807087 Byte0 end_step=30 best_step=27
8989 22:56:15.810852 Byte1 end_step=30 best_step=27
8990 22:56:15.814438 Byte0 TX OE(2T, 0.5T) = (3, 3)
8991 22:56:15.817228 Byte1 TX OE(2T, 0.5T) = (3, 3)
8992 22:56:15.817712
8993 22:56:15.818125
8994 22:56:15.823994 [DQSOSCAuto] RK1, (LSB)MR18= 0x2409, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 391 ps
8995 22:56:15.827566 CH1 RK1: MR19=303, MR18=2409
8996 22:56:15.834097 CH1_RK1: MR19=0x303, MR18=0x2409, DQSOSC=391, MR23=63, INC=24, DEC=16
8997 22:56:15.837121 [RxdqsGatingPostProcess] freq 1600
8998 22:56:15.840079 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8999 22:56:15.843559 best DQS0 dly(2T, 0.5T) = (1, 1)
9000 22:56:15.846804 best DQS1 dly(2T, 0.5T) = (1, 1)
9001 22:56:15.850594 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9002 22:56:15.853646 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9003 22:56:15.857095 best DQS0 dly(2T, 0.5T) = (1, 1)
9004 22:56:15.860083 best DQS1 dly(2T, 0.5T) = (1, 1)
9005 22:56:15.863865 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9006 22:56:15.867060 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9007 22:56:15.870664 Pre-setting of DQS Precalculation
9008 22:56:15.874134 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9009 22:56:15.883558 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9010 22:56:15.889948 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9011 22:56:15.890547
9012 22:56:15.890922
9013 22:56:15.893256 [Calibration Summary] 3200 Mbps
9014 22:56:15.893759 CH 0, Rank 0
9015 22:56:15.896370 SW Impedance : PASS
9016 22:56:15.896836 DUTY Scan : NO K
9017 22:56:15.899927 ZQ Calibration : PASS
9018 22:56:15.903623 Jitter Meter : NO K
9019 22:56:15.904187 CBT Training : PASS
9020 22:56:15.906711 Write leveling : PASS
9021 22:56:15.909815 RX DQS gating : PASS
9022 22:56:15.910385 RX DQ/DQS(RDDQC) : PASS
9023 22:56:15.913287 TX DQ/DQS : PASS
9024 22:56:15.913823 RX DATLAT : PASS
9025 22:56:15.916276 RX DQ/DQS(Engine): PASS
9026 22:56:15.920242 TX OE : PASS
9027 22:56:15.920809 All Pass.
9028 22:56:15.921184
9029 22:56:15.921529 CH 0, Rank 1
9030 22:56:15.923240 SW Impedance : PASS
9031 22:56:15.926775 DUTY Scan : NO K
9032 22:56:15.927448 ZQ Calibration : PASS
9033 22:56:15.929501 Jitter Meter : NO K
9034 22:56:15.933003 CBT Training : PASS
9035 22:56:15.933468 Write leveling : PASS
9036 22:56:15.936186 RX DQS gating : PASS
9037 22:56:15.939702 RX DQ/DQS(RDDQC) : PASS
9038 22:56:15.940167 TX DQ/DQS : PASS
9039 22:56:15.942864 RX DATLAT : PASS
9040 22:56:15.945849 RX DQ/DQS(Engine): PASS
9041 22:56:15.946316 TX OE : PASS
9042 22:56:15.949594 All Pass.
9043 22:56:15.950019
9044 22:56:15.950355 CH 1, Rank 0
9045 22:56:15.952538 SW Impedance : PASS
9046 22:56:15.952963 DUTY Scan : NO K
9047 22:56:15.955828 ZQ Calibration : PASS
9048 22:56:15.959290 Jitter Meter : NO K
9049 22:56:15.959751 CBT Training : PASS
9050 22:56:15.962659 Write leveling : PASS
9051 22:56:15.965852 RX DQS gating : PASS
9052 22:56:15.966365 RX DQ/DQS(RDDQC) : PASS
9053 22:56:15.969119 TX DQ/DQS : PASS
9054 22:56:15.972455 RX DATLAT : PASS
9055 22:56:15.972877 RX DQ/DQS(Engine): PASS
9056 22:56:15.975812 TX OE : PASS
9057 22:56:15.976333 All Pass.
9058 22:56:15.976676
9059 22:56:15.979727 CH 1, Rank 1
9060 22:56:15.980245 SW Impedance : PASS
9061 22:56:15.982620 DUTY Scan : NO K
9062 22:56:15.983133 ZQ Calibration : PASS
9063 22:56:15.986294 Jitter Meter : NO K
9064 22:56:15.988913 CBT Training : PASS
9065 22:56:15.989357 Write leveling : PASS
9066 22:56:15.992799 RX DQS gating : PASS
9067 22:56:15.995816 RX DQ/DQS(RDDQC) : PASS
9068 22:56:15.996245 TX DQ/DQS : PASS
9069 22:56:15.999616 RX DATLAT : PASS
9070 22:56:16.002715 RX DQ/DQS(Engine): PASS
9071 22:56:16.003237 TX OE : PASS
9072 22:56:16.006535 All Pass.
9073 22:56:16.007063
9074 22:56:16.007454 DramC Write-DBI on
9075 22:56:16.009483 PER_BANK_REFRESH: Hybrid Mode
9076 22:56:16.010001 TX_TRACKING: ON
9077 22:56:16.019755 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9078 22:56:16.026347 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9079 22:56:16.036251 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9080 22:56:16.039480 [FAST_K] Save calibration result to emmc
9081 22:56:16.042770 sync common calibartion params.
9082 22:56:16.043222 sync cbt_mode0:1, 1:1
9083 22:56:16.046177 dram_init: ddr_geometry: 2
9084 22:56:16.048976 dram_init: ddr_geometry: 2
9085 22:56:16.049398 dram_init: ddr_geometry: 2
9086 22:56:16.052887 0:dram_rank_size:100000000
9087 22:56:16.056019 1:dram_rank_size:100000000
9088 22:56:16.059415 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9089 22:56:16.063018 DFS_SHUFFLE_HW_MODE: ON
9090 22:56:16.065514 dramc_set_vcore_voltage set vcore to 725000
9091 22:56:16.068897 Read voltage for 1600, 0
9092 22:56:16.069345 Vio18 = 0
9093 22:56:16.072680 Vcore = 725000
9094 22:56:16.073223 Vdram = 0
9095 22:56:16.073632 Vddq = 0
9096 22:56:16.073949 Vmddr = 0
9097 22:56:16.075563 switch to 3200 Mbps bootup
9098 22:56:16.079444 [DramcRunTimeConfig]
9099 22:56:16.079965 PHYPLL
9100 22:56:16.082612 DPM_CONTROL_AFTERK: ON
9101 22:56:16.083195 PER_BANK_REFRESH: ON
9102 22:56:16.086109 REFRESH_OVERHEAD_REDUCTION: ON
9103 22:56:16.089658 CMD_PICG_NEW_MODE: OFF
9104 22:56:16.090080 XRTWTW_NEW_MODE: ON
9105 22:56:16.092635 XRTRTR_NEW_MODE: ON
9106 22:56:16.093057 TX_TRACKING: ON
9107 22:56:16.095826 RDSEL_TRACKING: OFF
9108 22:56:16.099562 DQS Precalculation for DVFS: ON
9109 22:56:16.100087 RX_TRACKING: OFF
9110 22:56:16.102694 HW_GATING DBG: ON
9111 22:56:16.103220 ZQCS_ENABLE_LP4: ON
9112 22:56:16.106064 RX_PICG_NEW_MODE: ON
9113 22:56:16.106593 TX_PICG_NEW_MODE: ON
9114 22:56:16.109712 ENABLE_RX_DCM_DPHY: ON
9115 22:56:16.112600 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9116 22:56:16.116231 DUMMY_READ_FOR_TRACKING: OFF
9117 22:56:16.116757 !!! SPM_CONTROL_AFTERK: OFF
9118 22:56:16.118943 !!! SPM could not control APHY
9119 22:56:16.122608 IMPEDANCE_TRACKING: ON
9120 22:56:16.123132 TEMP_SENSOR: ON
9121 22:56:16.126007 HW_SAVE_FOR_SR: OFF
9122 22:56:16.129117 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9123 22:56:16.132129 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9124 22:56:16.132698 Read ODT Tracking: ON
9125 22:56:16.135598 Refresh Rate DeBounce: ON
9126 22:56:16.139047 DFS_NO_QUEUE_FLUSH: ON
9127 22:56:16.142261 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9128 22:56:16.142900 ENABLE_DFS_RUNTIME_MRW: OFF
9129 22:56:16.145313 DDR_RESERVE_NEW_MODE: ON
9130 22:56:16.148647 MR_CBT_SWITCH_FREQ: ON
9131 22:56:16.149070 =========================
9132 22:56:16.169155 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9133 22:56:16.172440 dram_init: ddr_geometry: 2
9134 22:56:16.190867 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9135 22:56:16.193801 dram_init: dram init end (result: 0)
9136 22:56:16.200629 DRAM-K: Full calibration passed in 24410 msecs
9137 22:56:16.203862 MRC: failed to locate region type 0.
9138 22:56:16.204432 DRAM rank0 size:0x100000000,
9139 22:56:16.207430 DRAM rank1 size=0x100000000
9140 22:56:16.217422 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9141 22:56:16.223502 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9142 22:56:16.230297 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9143 22:56:16.237387 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9144 22:56:16.240093 DRAM rank0 size:0x100000000,
9145 22:56:16.243709 DRAM rank1 size=0x100000000
9146 22:56:16.244278 CBMEM:
9147 22:56:16.246694 IMD: root @ 0xfffff000 254 entries.
9148 22:56:16.250174 IMD: root @ 0xffffec00 62 entries.
9149 22:56:16.253770 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9150 22:56:16.256911 WARNING: RO_VPD is uninitialized or empty.
9151 22:56:16.263494 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9152 22:56:16.270813 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9153 22:56:16.283396 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9154 22:56:16.294710 BS: romstage times (exec / console): total (unknown) / 23948 ms
9155 22:56:16.295267
9156 22:56:16.295689
9157 22:56:16.304973 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9158 22:56:16.308902 ARM64: Exception handlers installed.
9159 22:56:16.311752 ARM64: Testing exception
9160 22:56:16.314648 ARM64: Done test exception
9161 22:56:16.315212 Enumerating buses...
9162 22:56:16.318282 Show all devs... Before device enumeration.
9163 22:56:16.321228 Root Device: enabled 1
9164 22:56:16.325142 CPU_CLUSTER: 0: enabled 1
9165 22:56:16.325707 CPU: 00: enabled 1
9166 22:56:16.328319 Compare with tree...
9167 22:56:16.328886 Root Device: enabled 1
9168 22:56:16.331522 CPU_CLUSTER: 0: enabled 1
9169 22:56:16.334629 CPU: 00: enabled 1
9170 22:56:16.335194 Root Device scanning...
9171 22:56:16.338287 scan_static_bus for Root Device
9172 22:56:16.341674 CPU_CLUSTER: 0 enabled
9173 22:56:16.344594 scan_static_bus for Root Device done
9174 22:56:16.347982 scan_bus: bus Root Device finished in 8 msecs
9175 22:56:16.348448 done
9176 22:56:16.354819 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9177 22:56:16.357775 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9178 22:56:16.364481 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9179 22:56:16.368013 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9180 22:56:16.371220 Allocating resources...
9181 22:56:16.371715 Reading resources...
9182 22:56:16.378215 Root Device read_resources bus 0 link: 0
9183 22:56:16.378796 DRAM rank0 size:0x100000000,
9184 22:56:16.381242 DRAM rank1 size=0x100000000
9185 22:56:16.384665 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9186 22:56:16.387722 CPU: 00 missing read_resources
9187 22:56:16.391232 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9188 22:56:16.397652 Root Device read_resources bus 0 link: 0 done
9189 22:56:16.398123 Done reading resources.
9190 22:56:16.404538 Show resources in subtree (Root Device)...After reading.
9191 22:56:16.407983 Root Device child on link 0 CPU_CLUSTER: 0
9192 22:56:16.410983 CPU_CLUSTER: 0 child on link 0 CPU: 00
9193 22:56:16.421584 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9194 22:56:16.422163 CPU: 00
9195 22:56:16.424497 Root Device assign_resources, bus 0 link: 0
9196 22:56:16.427813 CPU_CLUSTER: 0 missing set_resources
9197 22:56:16.433919 Root Device assign_resources, bus 0 link: 0 done
9198 22:56:16.434508 Done setting resources.
9199 22:56:16.441005 Show resources in subtree (Root Device)...After assigning values.
9200 22:56:16.443981 Root Device child on link 0 CPU_CLUSTER: 0
9201 22:56:16.447507 CPU_CLUSTER: 0 child on link 0 CPU: 00
9202 22:56:16.457862 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9203 22:56:16.458432 CPU: 00
9204 22:56:16.460514 Done allocating resources.
9205 22:56:16.463823 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9206 22:56:16.467193 Enabling resources...
9207 22:56:16.467845 done.
9208 22:56:16.473988 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9209 22:56:16.474637 Initializing devices...
9210 22:56:16.477748 Root Device init
9211 22:56:16.478312 init hardware done!
9212 22:56:16.480904 0x00000018: ctrlr->caps
9213 22:56:16.484237 52.000 MHz: ctrlr->f_max
9214 22:56:16.484886 0.400 MHz: ctrlr->f_min
9215 22:56:16.487607 0x40ff8080: ctrlr->voltages
9216 22:56:16.488180 sclk: 390625
9217 22:56:16.490869 Bus Width = 1
9218 22:56:16.491366 sclk: 390625
9219 22:56:16.494092 Bus Width = 1
9220 22:56:16.494612 Early init status = 3
9221 22:56:16.500494 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9222 22:56:16.503705 in-header: 03 fc 00 00 01 00 00 00
9223 22:56:16.504168 in-data: 00
9224 22:56:16.510669 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9225 22:56:16.514162 in-header: 03 fd 00 00 00 00 00 00
9226 22:56:16.516994 in-data:
9227 22:56:16.521046 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9228 22:56:16.524933 in-header: 03 fc 00 00 01 00 00 00
9229 22:56:16.528551 in-data: 00
9230 22:56:16.531616 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9231 22:56:16.537171 in-header: 03 fd 00 00 00 00 00 00
9232 22:56:16.540614 in-data:
9233 22:56:16.543961 [SSUSB] Setting up USB HOST controller...
9234 22:56:16.547105 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9235 22:56:16.550747 [SSUSB] phy power-on done.
9236 22:56:16.554092 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9237 22:56:16.560869 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9238 22:56:16.563773 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9239 22:56:16.570539 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9240 22:56:16.577633 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9241 22:56:16.583642 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9242 22:56:16.590493 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9243 22:56:16.597043 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9244 22:56:16.600372 SPM: binary array size = 0x9dc
9245 22:56:16.603738 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9246 22:56:16.610180 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9247 22:56:16.617539 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9248 22:56:16.620675 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9249 22:56:16.623854 configure_display: Starting display init
9250 22:56:16.660920 anx7625_power_on_init: Init interface.
9251 22:56:16.663934 anx7625_disable_pd_protocol: Disabled PD feature.
9252 22:56:16.667015 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9253 22:56:16.694646 anx7625_start_dp_work: Secure OCM version=00
9254 22:56:16.698402 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9255 22:56:16.713186 sp_tx_get_edid_block: EDID Block = 1
9256 22:56:16.815599 Extracted contents:
9257 22:56:16.819121 header: 00 ff ff ff ff ff ff 00
9258 22:56:16.822389 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9259 22:56:16.825752 version: 01 04
9260 22:56:16.828848 basic params: 95 1f 11 78 0a
9261 22:56:16.831878 chroma info: 76 90 94 55 54 90 27 21 50 54
9262 22:56:16.835227 established: 00 00 00
9263 22:56:16.842176 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9264 22:56:16.845921 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9265 22:56:16.852281 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9266 22:56:16.858607 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9267 22:56:16.864743 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9268 22:56:16.868586 extensions: 00
9269 22:56:16.869149 checksum: fb
9270 22:56:16.869524
9271 22:56:16.871209 Manufacturer: IVO Model 57d Serial Number 0
9272 22:56:16.875307 Made week 0 of 2020
9273 22:56:16.877993 EDID version: 1.4
9274 22:56:16.878455 Digital display
9275 22:56:16.881775 6 bits per primary color channel
9276 22:56:16.882349 DisplayPort interface
9277 22:56:16.884778 Maximum image size: 31 cm x 17 cm
9278 22:56:16.888289 Gamma: 220%
9279 22:56:16.889014 Check DPMS levels
9280 22:56:16.891856 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9281 22:56:16.898029 First detailed timing is preferred timing
9282 22:56:16.898501 Established timings supported:
9283 22:56:16.901174 Standard timings supported:
9284 22:56:16.904873 Detailed timings
9285 22:56:16.908164 Hex of detail: 383680a07038204018303c0035ae10000019
9286 22:56:16.914535 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9287 22:56:16.917817 0780 0798 07c8 0820 hborder 0
9288 22:56:16.921553 0438 043b 0447 0458 vborder 0
9289 22:56:16.924996 -hsync -vsync
9290 22:56:16.925565 Did detailed timing
9291 22:56:16.931435 Hex of detail: 000000000000000000000000000000000000
9292 22:56:16.934844 Manufacturer-specified data, tag 0
9293 22:56:16.938165 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9294 22:56:16.941142 ASCII string: InfoVision
9295 22:56:16.944526 Hex of detail: 000000fe00523134304e574635205248200a
9296 22:56:16.947690 ASCII string: R140NWF5 RH
9297 22:56:16.948155 Checksum
9298 22:56:16.951217 Checksum: 0xfb (valid)
9299 22:56:16.954926 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9300 22:56:16.957945 DSI data_rate: 832800000 bps
9301 22:56:16.964504 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9302 22:56:16.967796 anx7625_parse_edid: pixelclock(138800).
9303 22:56:16.971301 hactive(1920), hsync(48), hfp(24), hbp(88)
9304 22:56:16.974589 vactive(1080), vsync(12), vfp(3), vbp(17)
9305 22:56:16.978198 anx7625_dsi_config: config dsi.
9306 22:56:16.984937 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9307 22:56:16.997739 anx7625_dsi_config: success to config DSI
9308 22:56:17.001142 anx7625_dp_start: MIPI phy setup OK.
9309 22:56:17.004283 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9310 22:56:17.007279 mtk_ddp_mode_set invalid vrefresh 60
9311 22:56:17.010745 main_disp_path_setup
9312 22:56:17.011193 ovl_layer_smi_id_en
9313 22:56:17.014450 ovl_layer_smi_id_en
9314 22:56:17.014904 ccorr_config
9315 22:56:17.015260 aal_config
9316 22:56:17.017727 gamma_config
9317 22:56:17.018134 postmask_config
9318 22:56:17.020852 dither_config
9319 22:56:17.024275 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9320 22:56:17.030890 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9321 22:56:17.034127 Root Device init finished in 553 msecs
9322 22:56:17.034551 CPU_CLUSTER: 0 init
9323 22:56:17.044671 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9324 22:56:17.047720 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9325 22:56:17.050658 APU_MBOX 0x190000b0 = 0x10001
9326 22:56:17.054502 APU_MBOX 0x190001b0 = 0x10001
9327 22:56:17.057641 APU_MBOX 0x190005b0 = 0x10001
9328 22:56:17.060880 APU_MBOX 0x190006b0 = 0x10001
9329 22:56:17.064083 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9330 22:56:17.076413 read SPI 0x539f4 0xe237: 6249 us, 9267 KB/s, 74.136 Mbps
9331 22:56:17.089214 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9332 22:56:17.095639 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9333 22:56:17.107056 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9334 22:56:17.116578 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9335 22:56:17.119935 CPU_CLUSTER: 0 init finished in 81 msecs
9336 22:56:17.123364 Devices initialized
9337 22:56:17.126378 Show all devs... After init.
9338 22:56:17.126833 Root Device: enabled 1
9339 22:56:17.129758 CPU_CLUSTER: 0: enabled 1
9340 22:56:17.132906 CPU: 00: enabled 1
9341 22:56:17.136246 BS: BS_DEV_INIT run times (exec / console): 212 / 447 ms
9342 22:56:17.139595 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9343 22:56:17.142814 ELOG: NV offset 0x57f000 size 0x1000
9344 22:56:17.149794 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9345 22:56:17.156694 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9346 22:56:17.159773 ELOG: Event(17) added with size 13 at 2023-06-05 22:56:09 UTC
9347 22:56:17.163080 out: cmd=0x121: 03 db 21 01 00 00 00 00
9348 22:56:17.166860 in-header: 03 0a 00 00 2c 00 00 00
9349 22:56:17.179771 in-data: 55 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9350 22:56:17.186328 ELOG: Event(A1) added with size 10 at 2023-06-05 22:56:09 UTC
9351 22:56:17.193077 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9352 22:56:17.199848 ELOG: Event(A0) added with size 9 at 2023-06-05 22:56:09 UTC
9353 22:56:17.203521 elog_add_boot_reason: Logged dev mode boot
9354 22:56:17.206672 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9355 22:56:17.209807 Finalize devices...
9356 22:56:17.210375 Devices finalized
9357 22:56:17.216832 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9358 22:56:17.219952 Writing coreboot table at 0xffe64000
9359 22:56:17.223693 0. 000000000010a000-0000000000113fff: RAMSTAGE
9360 22:56:17.226581 1. 0000000040000000-00000000400fffff: RAM
9361 22:56:17.230165 2. 0000000040100000-000000004032afff: RAMSTAGE
9362 22:56:17.236841 3. 000000004032b000-00000000545fffff: RAM
9363 22:56:17.239852 4. 0000000054600000-000000005465ffff: BL31
9364 22:56:17.243080 5. 0000000054660000-00000000ffe63fff: RAM
9365 22:56:17.246368 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9366 22:56:17.253070 7. 0000000100000000-000000023fffffff: RAM
9367 22:56:17.253685 Passing 5 GPIOs to payload:
9368 22:56:17.259705 NAME | PORT | POLARITY | VALUE
9369 22:56:17.263408 EC in RW | 0x000000aa | low | undefined
9370 22:56:17.269258 EC interrupt | 0x00000005 | low | undefined
9371 22:56:17.272603 TPM interrupt | 0x000000ab | high | undefined
9372 22:56:17.276102 SD card detect | 0x00000011 | high | undefined
9373 22:56:17.283316 speaker enable | 0x00000093 | high | undefined
9374 22:56:17.286378 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9375 22:56:17.289764 in-header: 03 f9 00 00 02 00 00 00
9376 22:56:17.290339 in-data: 02 00
9377 22:56:17.292622 ADC[4]: Raw value=904357 ID=7
9378 22:56:17.296219 ADC[3]: Raw value=213072 ID=1
9379 22:56:17.296689 RAM Code: 0x71
9380 22:56:17.299534 ADC[6]: Raw value=75332 ID=0
9381 22:56:17.302913 ADC[5]: Raw value=213072 ID=1
9382 22:56:17.303515 SKU Code: 0x1
9383 22:56:17.309794 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 4e98
9384 22:56:17.313224 coreboot table: 964 bytes.
9385 22:56:17.316059 IMD ROOT 0. 0xfffff000 0x00001000
9386 22:56:17.320123 IMD SMALL 1. 0xffffe000 0x00001000
9387 22:56:17.322879 RO MCACHE 2. 0xffffc000 0x00001104
9388 22:56:17.326077 CONSOLE 3. 0xfff7c000 0x00080000
9389 22:56:17.329561 FMAP 4. 0xfff7b000 0x00000452
9390 22:56:17.332578 TIME STAMP 5. 0xfff7a000 0x00000910
9391 22:56:17.336189 VBOOT WORK 6. 0xfff66000 0x00014000
9392 22:56:17.339320 RAMOOPS 7. 0xffe66000 0x00100000
9393 22:56:17.342844 COREBOOT 8. 0xffe64000 0x00002000
9394 22:56:17.343316 IMD small region:
9395 22:56:17.346081 IMD ROOT 0. 0xffffec00 0x00000400
9396 22:56:17.349114 VPD 1. 0xffffeba0 0x0000004c
9397 22:56:17.352586 MMC STATUS 2. 0xffffeb80 0x00000004
9398 22:56:17.359180 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9399 22:56:17.359749 Probing TPM: done!
9400 22:56:17.366454 Connected to device vid:did:rid of 1ae0:0028:00
9401 22:56:17.376280 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.153/cr50_v3.94_pp.113-620c9b9523
9402 22:56:17.379807 Initialized TPM device CR50 revision 0
9403 22:56:17.380290 Checking cr50 for pending updates
9404 22:56:17.386058 Reading cr50 TPM mode
9405 22:56:17.394606 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9406 22:56:17.401712 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9407 22:56:17.442031 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9408 22:56:17.444772 Checking segment from ROM address 0x40100000
9409 22:56:17.448041 Checking segment from ROM address 0x4010001c
9410 22:56:17.454490 Loading segment from ROM address 0x40100000
9411 22:56:17.454609 code (compression=0)
9412 22:56:17.461047 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9413 22:56:17.471373 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9414 22:56:17.471482 it's not compressed!
9415 22:56:17.478261 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9416 22:56:17.481483 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9417 22:56:17.501971 Loading segment from ROM address 0x4010001c
9418 22:56:17.502362 Entry Point 0x80000000
9419 22:56:17.505334 Loaded segments
9420 22:56:17.508627 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9421 22:56:17.515391 Jumping to boot code at 0x80000000(0xffe64000)
9422 22:56:17.521709 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9423 22:56:17.528492 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9424 22:56:17.536233 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9425 22:56:17.539827 Checking segment from ROM address 0x40100000
9426 22:56:17.542985 Checking segment from ROM address 0x4010001c
9427 22:56:17.550188 Loading segment from ROM address 0x40100000
9428 22:56:17.550751 code (compression=1)
9429 22:56:17.556957 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9430 22:56:17.566144 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9431 22:56:17.566708 using LZMA
9432 22:56:17.574665 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9433 22:56:17.581699 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9434 22:56:17.585110 Loading segment from ROM address 0x4010001c
9435 22:56:17.585692 Entry Point 0x54601000
9436 22:56:17.588121 Loaded segments
9437 22:56:17.591485 NOTICE: MT8192 bl31_setup
9438 22:56:17.598121 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9439 22:56:17.601920 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9440 22:56:17.605532 WARNING: region 0:
9441 22:56:17.608698 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9442 22:56:17.609276 WARNING: region 1:
9443 22:56:17.615466 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9444 22:56:17.618391 WARNING: region 2:
9445 22:56:17.622306 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9446 22:56:17.625423 WARNING: region 3:
9447 22:56:17.628983 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9448 22:56:17.632071 WARNING: region 4:
9449 22:56:17.635723 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9450 22:56:17.638605 WARNING: region 5:
9451 22:56:17.642026 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9452 22:56:17.645683 WARNING: region 6:
9453 22:56:17.648545 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9454 22:56:17.649018 WARNING: region 7:
9455 22:56:17.655130 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9456 22:56:17.661992 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9457 22:56:17.665768 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9458 22:56:17.668565 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9459 22:56:17.675456 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9460 22:56:17.678921 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9461 22:56:17.682221 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9462 22:56:17.688778 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9463 22:56:17.691945 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9464 22:56:17.695016 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9465 22:56:17.702088 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9466 22:56:17.704930 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9467 22:56:17.712218 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9468 22:56:17.715709 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9469 22:56:17.718807 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9470 22:56:17.725475 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9471 22:56:17.728882 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9472 22:56:17.731815 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9473 22:56:17.738903 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9474 22:56:17.742537 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9475 22:56:17.745468 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9476 22:56:17.751989 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9477 22:56:17.755419 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9478 22:56:17.762622 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9479 22:56:17.765855 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9480 22:56:17.768918 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9481 22:56:17.775673 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9482 22:56:17.778411 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9483 22:56:17.785757 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9484 22:56:17.788885 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9485 22:56:17.792029 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9486 22:56:17.798661 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9487 22:56:17.801894 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9488 22:56:17.805759 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9489 22:56:17.812301 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9490 22:56:17.815806 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9491 22:56:17.819045 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9492 22:56:17.822166 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9493 22:56:17.828658 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9494 22:56:17.832369 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9495 22:56:17.835765 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9496 22:56:17.838952 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9497 22:56:17.842482 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9498 22:56:17.849026 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9499 22:56:17.852674 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9500 22:56:17.855576 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9501 22:56:17.862639 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9502 22:56:17.866336 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9503 22:56:17.869398 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9504 22:56:17.872886 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9505 22:56:17.879722 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9506 22:56:17.882762 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9507 22:56:17.889564 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9508 22:56:17.892455 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9509 22:56:17.899006 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9510 22:56:17.902707 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9511 22:56:17.906351 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9512 22:56:17.912468 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9513 22:56:17.916045 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9514 22:56:17.922733 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9515 22:56:17.926273 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9516 22:56:17.929281 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9517 22:56:17.936199 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9518 22:56:17.939651 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9519 22:56:17.945822 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9520 22:56:17.949283 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9521 22:56:17.955828 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9522 22:56:17.959685 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9523 22:56:17.966179 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9524 22:56:17.969878 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9525 22:56:17.972829 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9526 22:56:17.979220 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9527 22:56:17.982956 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9528 22:56:17.989220 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9529 22:56:17.992866 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9530 22:56:17.996818 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9531 22:56:18.002622 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9532 22:56:18.006467 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9533 22:56:18.012881 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9534 22:56:18.016253 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9535 22:56:18.022615 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9536 22:56:18.026188 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9537 22:56:18.032985 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9538 22:56:18.035965 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9539 22:56:18.039843 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9540 22:56:18.046247 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9541 22:56:18.049403 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9542 22:56:18.056408 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9543 22:56:18.059247 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9544 22:56:18.063034 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9545 22:56:18.069521 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9546 22:56:18.073183 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9547 22:56:18.079388 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9548 22:56:18.082346 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9549 22:56:18.088990 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9550 22:56:18.092530 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9551 22:56:18.099236 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9552 22:56:18.102761 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9553 22:56:18.106173 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9554 22:56:18.109484 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9555 22:56:18.116150 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9556 22:56:18.119271 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9557 22:56:18.122851 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9558 22:56:18.129418 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9559 22:56:18.132787 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9560 22:56:18.136655 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9561 22:56:18.142895 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9562 22:56:18.146306 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9563 22:56:18.152948 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9564 22:56:18.156264 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9565 22:56:18.159636 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9566 22:56:18.166644 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9567 22:56:18.169506 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9568 22:56:18.173036 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9569 22:56:18.179753 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9570 22:56:18.183226 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9571 22:56:18.189562 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9572 22:56:18.193341 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9573 22:56:18.196757 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9574 22:56:18.199935 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9575 22:56:18.206725 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9576 22:56:18.209946 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9577 22:56:18.213357 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9578 22:56:18.217436 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9579 22:56:18.223515 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9580 22:56:18.227074 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9581 22:56:18.230740 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9582 22:56:18.237668 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9583 22:56:18.240228 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9584 22:56:18.247000 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9585 22:56:18.250654 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9586 22:56:18.253888 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9587 22:56:18.260557 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9588 22:56:18.263878 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9589 22:56:18.267261 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9590 22:56:18.274221 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9591 22:56:18.277474 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9592 22:56:18.284291 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9593 22:56:18.287514 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9594 22:56:18.290716 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9595 22:56:18.297100 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9596 22:56:18.300941 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9597 22:56:18.304240 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9598 22:56:18.310462 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9599 22:56:18.314104 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9600 22:56:18.320834 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9601 22:56:18.324226 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9602 22:56:18.327419 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9603 22:56:18.334239 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9604 22:56:18.337434 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9605 22:56:18.343958 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9606 22:56:18.347812 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9607 22:56:18.350992 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9608 22:56:18.357641 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9609 22:56:18.361323 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9610 22:56:18.364273 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9611 22:56:18.370907 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9612 22:56:18.374338 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9613 22:56:18.381293 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9614 22:56:18.384634 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9615 22:56:18.387747 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9616 22:56:18.394253 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9617 22:56:18.397932 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9618 22:56:18.403872 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9619 22:56:18.407719 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9620 22:56:18.411145 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9621 22:56:18.417778 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9622 22:56:18.420774 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9623 22:56:18.424114 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9624 22:56:18.431162 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9625 22:56:18.434223 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9626 22:56:18.440900 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9627 22:56:18.444075 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9628 22:56:18.447083 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9629 22:56:18.454137 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9630 22:56:18.457791 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9631 22:56:18.463926 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9632 22:56:18.466954 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9633 22:56:18.470554 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9634 22:56:18.477420 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9635 22:56:18.479998 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9636 22:56:18.486980 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9637 22:56:18.490379 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9638 22:56:18.493351 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9639 22:56:18.500702 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9640 22:56:18.503779 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9641 22:56:18.510363 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9642 22:56:18.513965 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9643 22:56:18.516975 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9644 22:56:18.523537 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9645 22:56:18.526877 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9646 22:56:18.533563 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9647 22:56:18.536695 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9648 22:56:18.540212 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9649 22:56:18.546979 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9650 22:56:18.550077 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9651 22:56:18.556555 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9652 22:56:18.560223 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9653 22:56:18.563764 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9654 22:56:18.569814 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9655 22:56:18.573452 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9656 22:56:18.579877 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9657 22:56:18.583274 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9658 22:56:18.590216 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9659 22:56:18.593809 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9660 22:56:18.596430 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9661 22:56:18.602966 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9662 22:56:18.606838 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9663 22:56:18.613584 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9664 22:56:18.616934 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9665 22:56:18.620410 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9666 22:56:18.627183 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9667 22:56:18.630154 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9668 22:56:18.636526 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9669 22:56:18.639889 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9670 22:56:18.643461 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9671 22:56:18.649907 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9672 22:56:18.653139 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9673 22:56:18.660008 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9674 22:56:18.662884 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9675 22:56:18.669712 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9676 22:56:18.673244 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9677 22:56:18.676834 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9678 22:56:18.682918 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9679 22:56:18.686538 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9680 22:56:18.693668 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9681 22:56:18.696747 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9682 22:56:18.699883 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9683 22:56:18.707110 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9684 22:56:18.709906 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9685 22:56:18.713854 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9686 22:56:18.719701 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9687 22:56:18.723529 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9688 22:56:18.726370 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9689 22:56:18.730175 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9690 22:56:18.736616 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9691 22:56:18.739896 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9692 22:56:18.746287 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9693 22:56:18.749652 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9694 22:56:18.753039 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9695 22:56:18.759907 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9696 22:56:18.763161 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9697 22:56:18.766353 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9698 22:56:18.773320 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9699 22:56:18.775974 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9700 22:56:18.779699 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9701 22:56:18.786472 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9702 22:56:18.789201 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9703 22:56:18.796427 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9704 22:56:18.799578 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9705 22:56:18.802921 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9706 22:56:18.810205 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9707 22:56:18.812940 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9708 22:56:18.816259 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9709 22:56:18.823121 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9710 22:56:18.826006 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9711 22:56:18.829645 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9712 22:56:18.836054 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9713 22:56:18.839774 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9714 22:56:18.842607 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9715 22:56:18.849835 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9716 22:56:18.852735 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9717 22:56:18.859437 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9718 22:56:18.862441 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9719 22:56:18.866137 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9720 22:56:18.872768 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9721 22:56:18.875492 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9722 22:56:18.882945 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9723 22:56:18.885641 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9724 22:56:18.889343 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9725 22:56:18.892390 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9726 22:56:18.898793 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9727 22:56:18.902333 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9728 22:56:18.905610 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9729 22:56:18.909198 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9730 22:56:18.912671 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9731 22:56:18.919018 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9732 22:56:18.922807 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9733 22:56:18.925866 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9734 22:56:18.928877 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9735 22:56:18.935633 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9736 22:56:18.939420 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9737 22:56:18.942312 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9738 22:56:18.949019 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9739 22:56:18.952460 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9740 22:56:18.959371 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9741 22:56:18.962676 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9742 22:56:18.965527 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9743 22:56:18.971840 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9744 22:56:18.975888 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9745 22:56:18.982432 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9746 22:56:18.985749 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9747 22:56:18.989104 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9748 22:56:18.995541 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9749 22:56:18.998561 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9750 22:56:19.005951 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9751 22:56:19.008801 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9752 22:56:19.016035 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9753 22:56:19.018491 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9754 22:56:19.021773 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9755 22:56:19.029337 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9756 22:56:19.031945 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9757 22:56:19.038668 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9758 22:56:19.042423 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9759 22:56:19.045087 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9760 22:56:19.051844 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9761 22:56:19.055505 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9762 22:56:19.061637 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9763 22:56:19.065452 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9764 22:56:19.068628 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9765 22:56:19.075068 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9766 22:56:19.078193 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9767 22:56:19.085181 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9768 22:56:19.088206 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9769 22:56:19.091650 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9770 22:56:19.098637 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9771 22:56:19.102201 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9772 22:56:19.108568 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9773 22:56:19.111911 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9774 22:56:19.115554 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9775 22:56:19.121711 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9776 22:56:19.124883 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9777 22:56:19.131868 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9778 22:56:19.135284 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9779 22:56:19.138907 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9780 22:56:19.145235 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9781 22:56:19.148165 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9782 22:56:19.154705 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9783 22:56:19.158720 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9784 22:56:19.165226 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9785 22:56:19.168126 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9786 22:56:19.171966 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9787 22:56:19.177959 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9788 22:56:19.181586 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9789 22:56:19.187932 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9790 22:56:19.191401 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9791 22:56:19.194689 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9792 22:56:19.201667 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9793 22:56:19.204541 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9794 22:56:19.211617 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9795 22:56:19.215184 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9796 22:56:19.218000 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9797 22:56:19.225311 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9798 22:56:19.228032 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9799 22:56:19.234734 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9800 22:56:19.238216 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9801 22:56:19.241895 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9802 22:56:19.248200 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9803 22:56:19.251173 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9804 22:56:19.258130 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9805 22:56:19.261565 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9806 22:56:19.267906 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9807 22:56:19.271701 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9808 22:56:19.274548 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9809 22:56:19.281582 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9810 22:56:19.284595 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9811 22:56:19.290990 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9812 22:56:19.294242 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9813 22:56:19.298104 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9814 22:56:19.304302 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9815 22:56:19.307845 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9816 22:56:19.314339 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9817 22:56:19.317663 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9818 22:56:19.324152 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9819 22:56:19.327269 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9820 22:56:19.334431 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9821 22:56:19.337412 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9822 22:56:19.340913 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9823 22:56:19.347450 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9824 22:56:19.350941 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9825 22:56:19.357760 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9826 22:56:19.360837 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9827 22:56:19.368060 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9828 22:56:19.370730 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9829 22:56:19.374325 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9830 22:56:19.380660 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9831 22:56:19.383951 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9832 22:56:19.390664 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9833 22:56:19.394169 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9834 22:56:19.400233 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9835 22:56:19.403923 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9836 22:56:19.407048 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9837 22:56:19.413923 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9838 22:56:19.417548 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9839 22:56:19.423814 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9840 22:56:19.427002 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9841 22:56:19.434283 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9842 22:56:19.437100 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9843 22:56:19.440724 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9844 22:56:19.446891 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9845 22:56:19.450616 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9846 22:56:19.456830 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9847 22:56:19.460399 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9848 22:56:19.467163 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9849 22:56:19.470943 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9850 22:56:19.473631 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9851 22:56:19.480136 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9852 22:56:19.484255 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9853 22:56:19.490679 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9854 22:56:19.493782 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9855 22:56:19.500300 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9856 22:56:19.503704 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9857 22:56:19.507147 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9858 22:56:19.513379 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9859 22:56:19.516856 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9860 22:56:19.523916 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9861 22:56:19.526590 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9862 22:56:19.533695 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9863 22:56:19.537002 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9864 22:56:19.543687 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9865 22:56:19.546893 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9866 22:56:19.553590 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9867 22:56:19.557080 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9868 22:56:19.560564 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9869 22:56:19.567308 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9870 22:56:19.570163 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9871 22:56:19.576819 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9872 22:56:19.580192 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9873 22:56:19.587478 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9874 22:56:19.590129 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9875 22:56:19.597231 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9876 22:56:19.600162 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9877 22:56:19.606744 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9878 22:56:19.610057 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9879 22:56:19.616651 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9880 22:56:19.620056 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9881 22:56:19.626656 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9882 22:56:19.629794 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9883 22:56:19.637012 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9884 22:56:19.639761 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9885 22:56:19.646529 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9886 22:56:19.649871 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9887 22:56:19.656882 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9888 22:56:19.660121 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9889 22:56:19.666842 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9890 22:56:19.670374 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9891 22:56:19.673379 INFO: [APUAPC] vio 0
9892 22:56:19.677220 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9893 22:56:19.683513 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9894 22:56:19.686934 INFO: [APUAPC] D0_APC_0: 0x400510
9895 22:56:19.687547 INFO: [APUAPC] D0_APC_1: 0x0
9896 22:56:19.690473 INFO: [APUAPC] D0_APC_2: 0x1540
9897 22:56:19.693428 INFO: [APUAPC] D0_APC_3: 0x0
9898 22:56:19.696653 INFO: [APUAPC] D1_APC_0: 0xffffffff
9899 22:56:19.699764 INFO: [APUAPC] D1_APC_1: 0xffffffff
9900 22:56:19.703403 INFO: [APUAPC] D1_APC_2: 0x3fffff
9901 22:56:19.706824 INFO: [APUAPC] D1_APC_3: 0x0
9902 22:56:19.709873 INFO: [APUAPC] D2_APC_0: 0xffffffff
9903 22:56:19.713249 INFO: [APUAPC] D2_APC_1: 0xffffffff
9904 22:56:19.716652 INFO: [APUAPC] D2_APC_2: 0x3fffff
9905 22:56:19.719893 INFO: [APUAPC] D2_APC_3: 0x0
9906 22:56:19.723305 INFO: [APUAPC] D3_APC_0: 0xffffffff
9907 22:56:19.726646 INFO: [APUAPC] D3_APC_1: 0xffffffff
9908 22:56:19.729991 INFO: [APUAPC] D3_APC_2: 0x3fffff
9909 22:56:19.733261 INFO: [APUAPC] D3_APC_3: 0x0
9910 22:56:19.736550 INFO: [APUAPC] D4_APC_0: 0xffffffff
9911 22:56:19.739703 INFO: [APUAPC] D4_APC_1: 0xffffffff
9912 22:56:19.743170 INFO: [APUAPC] D4_APC_2: 0x3fffff
9913 22:56:19.746370 INFO: [APUAPC] D4_APC_3: 0x0
9914 22:56:19.750126 INFO: [APUAPC] D5_APC_0: 0xffffffff
9915 22:56:19.753135 INFO: [APUAPC] D5_APC_1: 0xffffffff
9916 22:56:19.756727 INFO: [APUAPC] D5_APC_2: 0x3fffff
9917 22:56:19.759428 INFO: [APUAPC] D5_APC_3: 0x0
9918 22:56:19.762926 INFO: [APUAPC] D6_APC_0: 0xffffffff
9919 22:56:19.766353 INFO: [APUAPC] D6_APC_1: 0xffffffff
9920 22:56:19.769300 INFO: [APUAPC] D6_APC_2: 0x3fffff
9921 22:56:19.773273 INFO: [APUAPC] D6_APC_3: 0x0
9922 22:56:19.775973 INFO: [APUAPC] D7_APC_0: 0xffffffff
9923 22:56:19.779502 INFO: [APUAPC] D7_APC_1: 0xffffffff
9924 22:56:19.782868 INFO: [APUAPC] D7_APC_2: 0x3fffff
9925 22:56:19.786391 INFO: [APUAPC] D7_APC_3: 0x0
9926 22:56:19.789393 INFO: [APUAPC] D8_APC_0: 0xffffffff
9927 22:56:19.792621 INFO: [APUAPC] D8_APC_1: 0xffffffff
9928 22:56:19.796396 INFO: [APUAPC] D8_APC_2: 0x3fffff
9929 22:56:19.799474 INFO: [APUAPC] D8_APC_3: 0x0
9930 22:56:19.803008 INFO: [APUAPC] D9_APC_0: 0xffffffff
9931 22:56:19.805804 INFO: [APUAPC] D9_APC_1: 0xffffffff
9932 22:56:19.809874 INFO: [APUAPC] D9_APC_2: 0x3fffff
9933 22:56:19.812857 INFO: [APUAPC] D9_APC_3: 0x0
9934 22:56:19.815949 INFO: [APUAPC] D10_APC_0: 0xffffffff
9935 22:56:19.819477 INFO: [APUAPC] D10_APC_1: 0xffffffff
9936 22:56:19.822240 INFO: [APUAPC] D10_APC_2: 0x3fffff
9937 22:56:19.825643 INFO: [APUAPC] D10_APC_3: 0x0
9938 22:56:19.829455 INFO: [APUAPC] D11_APC_0: 0xffffffff
9939 22:56:19.832475 INFO: [APUAPC] D11_APC_1: 0xffffffff
9940 22:56:19.836133 INFO: [APUAPC] D11_APC_2: 0x3fffff
9941 22:56:19.839580 INFO: [APUAPC] D11_APC_3: 0x0
9942 22:56:19.843078 INFO: [APUAPC] D12_APC_0: 0xffffffff
9943 22:56:19.845970 INFO: [APUAPC] D12_APC_1: 0xffffffff
9944 22:56:19.848946 INFO: [APUAPC] D12_APC_2: 0x3fffff
9945 22:56:19.852639 INFO: [APUAPC] D12_APC_3: 0x0
9946 22:56:19.855552 INFO: [APUAPC] D13_APC_0: 0xffffffff
9947 22:56:19.859125 INFO: [APUAPC] D13_APC_1: 0xffffffff
9948 22:56:19.862425 INFO: [APUAPC] D13_APC_2: 0x3fffff
9949 22:56:19.866078 INFO: [APUAPC] D13_APC_3: 0x0
9950 22:56:19.869314 INFO: [APUAPC] D14_APC_0: 0xffffffff
9951 22:56:19.872062 INFO: [APUAPC] D14_APC_1: 0xffffffff
9952 22:56:19.875997 INFO: [APUAPC] D14_APC_2: 0x3fffff
9953 22:56:19.878984 INFO: [APUAPC] D14_APC_3: 0x0
9954 22:56:19.882550 INFO: [APUAPC] D15_APC_0: 0xffffffff
9955 22:56:19.885678 INFO: [APUAPC] D15_APC_1: 0xffffffff
9956 22:56:19.889226 INFO: [APUAPC] D15_APC_2: 0x3fffff
9957 22:56:19.892116 INFO: [APUAPC] D15_APC_3: 0x0
9958 22:56:19.892674 INFO: [APUAPC] APC_CON: 0x4
9959 22:56:19.895980 INFO: [NOCDAPC] D0_APC_0: 0x0
9960 22:56:19.898776 INFO: [NOCDAPC] D0_APC_1: 0x0
9961 22:56:19.902312 INFO: [NOCDAPC] D1_APC_0: 0x0
9962 22:56:19.905569 INFO: [NOCDAPC] D1_APC_1: 0xfff
9963 22:56:19.908860 INFO: [NOCDAPC] D2_APC_0: 0x0
9964 22:56:19.912226 INFO: [NOCDAPC] D2_APC_1: 0xfff
9965 22:56:19.915478 INFO: [NOCDAPC] D3_APC_0: 0x0
9966 22:56:19.919245 INFO: [NOCDAPC] D3_APC_1: 0xfff
9967 22:56:19.922055 INFO: [NOCDAPC] D4_APC_0: 0x0
9968 22:56:19.925483 INFO: [NOCDAPC] D4_APC_1: 0xfff
9969 22:56:19.926054 INFO: [NOCDAPC] D5_APC_0: 0x0
9970 22:56:19.928799 INFO: [NOCDAPC] D5_APC_1: 0xfff
9971 22:56:19.932336 INFO: [NOCDAPC] D6_APC_0: 0x0
9972 22:56:19.935766 INFO: [NOCDAPC] D6_APC_1: 0xfff
9973 22:56:19.938435 INFO: [NOCDAPC] D7_APC_0: 0x0
9974 22:56:19.941852 INFO: [NOCDAPC] D7_APC_1: 0xfff
9975 22:56:19.945364 INFO: [NOCDAPC] D8_APC_0: 0x0
9976 22:56:19.948789 INFO: [NOCDAPC] D8_APC_1: 0xfff
9977 22:56:19.951758 INFO: [NOCDAPC] D9_APC_0: 0x0
9978 22:56:19.955253 INFO: [NOCDAPC] D9_APC_1: 0xfff
9979 22:56:19.958947 INFO: [NOCDAPC] D10_APC_0: 0x0
9980 22:56:19.959604 INFO: [NOCDAPC] D10_APC_1: 0xfff
9981 22:56:19.961690 INFO: [NOCDAPC] D11_APC_0: 0x0
9982 22:56:19.965817 INFO: [NOCDAPC] D11_APC_1: 0xfff
9983 22:56:19.968687 INFO: [NOCDAPC] D12_APC_0: 0x0
9984 22:56:19.971868 INFO: [NOCDAPC] D12_APC_1: 0xfff
9985 22:56:19.975476 INFO: [NOCDAPC] D13_APC_0: 0x0
9986 22:56:19.978747 INFO: [NOCDAPC] D13_APC_1: 0xfff
9987 22:56:19.981844 INFO: [NOCDAPC] D14_APC_0: 0x0
9988 22:56:19.985288 INFO: [NOCDAPC] D14_APC_1: 0xfff
9989 22:56:19.988690 INFO: [NOCDAPC] D15_APC_0: 0x0
9990 22:56:19.991815 INFO: [NOCDAPC] D15_APC_1: 0xfff
9991 22:56:19.995252 INFO: [NOCDAPC] APC_CON: 0x4
9992 22:56:19.998289 INFO: [APUAPC] set_apusys_apc done
9993 22:56:20.001486 INFO: [DEVAPC] devapc_init done
9994 22:56:20.004906 INFO: GICv3 without legacy support detected.
9995 22:56:20.008567 INFO: ARM GICv3 driver initialized in EL3
9996 22:56:20.011680 INFO: Maximum SPI INTID supported: 639
9997 22:56:20.015574 INFO: BL31: Initializing runtime services
9998 22:56:20.021811 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9999 22:56:20.025367 INFO: SPM: enable CPC mode
10000 22:56:20.031790 INFO: mcdi ready for mcusys-off-idle and system suspend
10001 22:56:20.034831 INFO: BL31: Preparing for EL3 exit to normal world
10002 22:56:20.038309 INFO: Entry point address = 0x80000000
10003 22:56:20.041403 INFO: SPSR = 0x8
10004 22:56:20.046247
10005 22:56:20.046807
10006 22:56:20.047175
10007 22:56:20.049152 Starting depthcharge on Spherion...
10008 22:56:20.049619
10009 22:56:20.049985 Wipe memory regions:
10010 22:56:20.050506
10011 22:56:20.053328 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10012 22:56:20.054140 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10013 22:56:20.054649 Setting prompt string to ['asurada:']
10014 22:56:20.055097 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10015 22:56:20.055874 [0x00000040000000, 0x00000054600000)
10016 22:56:20.175054
10017 22:56:20.175663 [0x00000054660000, 0x00000080000000)
10018 22:56:20.435975
10019 22:56:20.436533 [0x000000821a7280, 0x000000ffe64000)
10020 22:56:21.180794
10021 22:56:21.181356 [0x00000100000000, 0x00000240000000)
10022 22:56:23.070916
10023 22:56:23.074078 Initializing XHCI USB controller at 0x11200000.
10024 22:56:24.112211
10025 22:56:24.115435 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10026 22:56:24.115902
10027 22:56:24.116270
10028 22:56:24.116613
10029 22:56:24.117420 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10031 22:56:24.218649 asurada: tftpboot 192.168.201.1 10597683/tftp-deploy-bbro1pbo/kernel/image.itb 10597683/tftp-deploy-bbro1pbo/kernel/cmdline
10032 22:56:24.219314 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10033 22:56:24.219835 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10034 22:56:24.224657 tftpboot 192.168.201.1 10597683/tftp-deploy-bbro1pbo/kernel/image.itp-deploy-bbro1pbo/kernel/cmdline
10035 22:56:24.225244
10036 22:56:24.225616 Waiting for link
10037 22:56:24.385036
10038 22:56:24.385636 R8152: Initializing
10039 22:56:24.386014
10040 22:56:24.387826 Version 9 (ocp_data = 6010)
10041 22:56:24.388293
10042 22:56:24.391439 R8152: Done initializing
10043 22:56:24.391930
10044 22:56:24.392331 Adding net device
10045 22:56:26.333289
10046 22:56:26.333444 done.
10047 22:56:26.333514
10048 22:56:26.333575 MAC: 00:e0:4c:78:7a:aa
10049 22:56:26.333634
10050 22:56:26.336802 Sending DHCP discover... done.
10051 22:56:26.336886
10052 22:56:26.340183 Waiting for reply... done.
10053 22:56:26.340291
10054 22:56:26.343476 Sending DHCP request... done.
10055 22:56:26.343558
10056 22:56:26.343622 Waiting for reply... done.
10057 22:56:26.343682
10058 22:56:26.346989 My ip is 192.168.201.12
10059 22:56:26.347073
10060 22:56:26.350208 The DHCP server ip is 192.168.201.1
10061 22:56:26.350290
10062 22:56:26.353034 TFTP server IP predefined by user: 192.168.201.1
10063 22:56:26.353133
10064 22:56:26.360077 Bootfile predefined by user: 10597683/tftp-deploy-bbro1pbo/kernel/image.itb
10065 22:56:26.360160
10066 22:56:26.363585 Sending tftp read request... done.
10067 22:56:26.363666
10068 22:56:26.366695 Waiting for the transfer...
10069 22:56:26.366778
10070 22:56:26.617519 00000000 ################################################################
10071 22:56:26.617668
10072 22:56:26.871727 00080000 ################################################################
10073 22:56:26.871863
10074 22:56:27.156242 00100000 ################################################################
10075 22:56:27.156393
10076 22:56:27.412735 00180000 ################################################################
10077 22:56:27.412915
10078 22:56:27.678216 00200000 ################################################################
10079 22:56:27.678367
10080 22:56:27.927618 00280000 ################################################################
10081 22:56:27.927758
10082 22:56:28.187547 00300000 ################################################################
10083 22:56:28.187690
10084 22:56:28.487713 00380000 ################################################################
10085 22:56:28.487861
10086 22:56:28.788415 00400000 ################################################################
10087 22:56:28.788560
10088 22:56:29.088889 00480000 ################################################################
10089 22:56:29.089034
10090 22:56:29.388928 00500000 ################################################################
10091 22:56:29.389075
10092 22:56:29.689737 00580000 ################################################################
10093 22:56:29.689883
10094 22:56:29.989490 00600000 ################################################################
10095 22:56:29.989634
10096 22:56:30.296945 00680000 ################################################################
10097 22:56:30.297466
10098 22:56:30.679508 00700000 ################################################################
10099 22:56:30.680027
10100 22:56:30.998791 00780000 ################################################################
10101 22:56:30.998962
10102 22:56:31.264493 00800000 ################################################################
10103 22:56:31.264629
10104 22:56:31.564129 00880000 ################################################################
10105 22:56:31.564273
10106 22:56:31.863869 00900000 ################################################################
10107 22:56:31.864013
10108 22:56:32.164314 00980000 ################################################################
10109 22:56:32.164456
10110 22:56:32.464713 00a00000 ################################################################
10111 22:56:32.464860
10112 22:56:32.765515 00a80000 ################################################################
10113 22:56:32.765661
10114 22:56:33.053835 00b00000 ################################################################
10115 22:56:33.054014
10116 22:56:33.333961 00b80000 ################################################################
10117 22:56:33.334140
10118 22:56:33.601874 00c00000 ################################################################
10119 22:56:33.602089
10120 22:56:33.868842 00c80000 ################################################################
10121 22:56:33.868994
10122 22:56:34.130395 00d00000 ################################################################
10123 22:56:34.130535
10124 22:56:34.385038 00d80000 ################################################################
10125 22:56:34.385216
10126 22:56:34.652094 00e00000 ################################################################
10127 22:56:34.652242
10128 22:56:34.934891 00e80000 ################################################################
10129 22:56:34.935067
10130 22:56:35.230471 00f00000 ################################################################
10131 22:56:35.230616
10132 22:56:35.524859 00f80000 ################################################################
10133 22:56:35.525049
10134 22:56:35.769006 01000000 ################################################################
10135 22:56:35.769147
10136 22:56:36.047002 01080000 ################################################################
10137 22:56:36.047146
10138 22:56:36.347200 01100000 ################################################################
10139 22:56:36.347408
10140 22:56:36.646946 01180000 ################################################################
10141 22:56:36.647120
10142 22:56:36.946881 01200000 ################################################################
10143 22:56:36.947024
10144 22:56:37.246965 01280000 ################################################################
10145 22:56:37.247102
10146 22:56:37.543805 01300000 ################################################################
10147 22:56:37.543951
10148 22:56:37.843123 01380000 ################################################################
10149 22:56:37.843262
10150 22:56:38.137680 01400000 ################################################################
10151 22:56:38.137820
10152 22:56:38.422552 01480000 ################################################################
10153 22:56:38.422698
10154 22:56:38.671819 01500000 ################################################################
10155 22:56:38.671970
10156 22:56:38.959920 01580000 ################################################################
10157 22:56:38.960092
10158 22:56:39.253842 01600000 ################################################################
10159 22:56:39.254008
10160 22:56:39.553287 01680000 ################################################################
10161 22:56:39.553430
10162 22:56:39.853927 01700000 ################################################################
10163 22:56:39.854072
10164 22:56:40.154008 01780000 ################################################################
10165 22:56:40.154153
10166 22:56:40.453539 01800000 ################################################################
10167 22:56:40.453684
10168 22:56:40.753532 01880000 ################################################################
10169 22:56:40.753676
10170 22:56:41.048773 01900000 ################################################################
10171 22:56:41.048917
10172 22:56:41.335200 01980000 ################################################################
10173 22:56:41.335375
10174 22:56:41.630891 01a00000 ################################################################
10175 22:56:41.631062
10176 22:56:41.914133 01a80000 ################################################################
10177 22:56:41.914280
10178 22:56:42.194639 01b00000 ################################################################
10179 22:56:42.194783
10180 22:56:42.490376 01b80000 ################################################################
10181 22:56:42.490519
10182 22:56:42.777621 01c00000 ################################################################
10183 22:56:42.777793
10184 22:56:43.044275 01c80000 ################################################################
10185 22:56:43.044446
10186 22:56:43.337642 01d00000 ################################################################
10187 22:56:43.337812
10188 22:56:43.585352 01d80000 ####################################################### done.
10189 22:56:43.588074
10190 22:56:43.588160 The bootfile was 31380234 bytes long.
10191 22:56:43.591216
10192 22:56:43.591293 Sending tftp read request... done.
10193 22:56:43.591368
10194 22:56:43.594448 Waiting for the transfer...
10195 22:56:43.594535
10196 22:56:43.598099 00000000 # done.
10197 22:56:43.598265
10198 22:56:43.604889 Command line loaded dynamically from TFTP file: 10597683/tftp-deploy-bbro1pbo/kernel/cmdline
10199 22:56:43.605067
10200 22:56:43.614417 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10201 22:56:43.617954
10202 22:56:43.618168 Loading FIT.
10203 22:56:43.618289
10204 22:56:43.621547 Image ramdisk-1 has 21245330 bytes.
10205 22:56:43.621786
10206 22:56:43.624848 Image fdt-1 has 46924 bytes.
10207 22:56:43.625050
10208 22:56:43.628087 Image kernel-1 has 10085945 bytes.
10209 22:56:43.628312
10210 22:56:43.634462 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10211 22:56:43.634753
10212 22:56:43.654909 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10213 22:56:43.655529
10214 22:56:43.658248 Choosing best match conf-1 for compat google,spherion-rev2.
10215 22:56:43.663277
10216 22:56:43.667699 Connected to device vid:did:rid of 1ae0:0028:00
10217 22:56:43.675671
10218 22:56:43.679163 tpm_get_response: command 0x17b, return code 0x0
10219 22:56:43.679784
10220 22:56:43.682119 ec_init: CrosEC protocol v3 supported (256, 248)
10221 22:56:43.687700
10222 22:56:43.690717 tpm_cleanup: add release locality here.
10223 22:56:43.691184
10224 22:56:43.691585 Shutting down all USB controllers.
10225 22:56:43.694051
10226 22:56:43.694609 Removing current net device
10227 22:56:43.694990
10228 22:56:43.701076 Exiting depthcharge with code 4 at timestamp: 52884811
10229 22:56:43.701640
10230 22:56:43.704560 LZMA decompressing kernel-1 to 0x821a6718
10231 22:56:43.705147
10232 22:56:43.707234 LZMA decompressing kernel-1 to 0x40000000
10233 22:56:44.974057
10234 22:56:44.974630 jumping to kernel
10235 22:56:44.976117 end: 2.2.4 bootloader-commands (duration 00:00:25) [common]
10236 22:56:44.976659 start: 2.2.5 auto-login-action (timeout 00:04:00) [common]
10237 22:56:44.977081 Setting prompt string to ['Linux version [0-9]']
10238 22:56:44.977463 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10239 22:56:44.977845 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10240 22:56:45.056540
10241 22:56:45.059713 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10242 22:56:45.063712 start: 2.2.5.1 login-action (timeout 00:04:00) [common]
10243 22:56:45.064300 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10244 22:56:45.064798 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10245 22:56:45.065214 Using line separator: #'\n'#
10246 22:56:45.065559 No login prompt set.
10247 22:56:45.065918 Parsing kernel messages
10248 22:56:45.066238 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10249 22:56:45.066802 [login-action] Waiting for messages, (timeout 00:04:00)
10250 22:56:45.083062 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j1612582-arm64-gcc-10-defconfig-arm64-chromebook-7xwc5) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Jun 5 22:41:02 UTC 2023
10251 22:56:45.086609 [ 0.000000] random: crng init done
10252 22:56:45.089584 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10253 22:56:45.092669 [ 0.000000] efi: UEFI not found.
10254 22:56:45.103099 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10255 22:56:45.109497 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10256 22:56:45.119745 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10257 22:56:45.129700 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10258 22:56:45.135796 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10259 22:56:45.139151 [ 0.000000] printk: bootconsole [mtk8250] enabled
10260 22:56:45.148202 [ 0.000000] NUMA: No NUMA configuration found
10261 22:56:45.154557 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10262 22:56:45.161684 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcda00-0x23efcffff]
10263 22:56:45.162254 [ 0.000000] Zone ranges:
10264 22:56:45.167986 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10265 22:56:45.171002 [ 0.000000] DMA32 empty
10266 22:56:45.177826 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10267 22:56:45.181007 [ 0.000000] Movable zone start for each node
10268 22:56:45.184260 [ 0.000000] Early memory node ranges
10269 22:56:45.190783 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10270 22:56:45.197730 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10271 22:56:45.204765 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10272 22:56:45.210784 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10273 22:56:45.217285 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10274 22:56:45.224532 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10275 22:56:45.280436 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10276 22:56:45.287153 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10277 22:56:45.294406 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10278 22:56:45.297420 [ 0.000000] psci: probing for conduit method from DT.
10279 22:56:45.304146 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10280 22:56:45.306900 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10281 22:56:45.313537 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10282 22:56:45.317041 [ 0.000000] psci: SMC Calling Convention v1.2
10283 22:56:45.323512 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10284 22:56:45.326818 [ 0.000000] Detected VIPT I-cache on CPU0
10285 22:56:45.333843 [ 0.000000] CPU features: detected: GIC system register CPU interface
10286 22:56:45.340409 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10287 22:56:45.347398 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10288 22:56:45.353991 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10289 22:56:45.360400 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10290 22:56:45.367440 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10291 22:56:45.374040 [ 0.000000] alternatives: applying boot alternatives
10292 22:56:45.376967 [ 0.000000] Fallback order for Node 0: 0
10293 22:56:45.384136 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10294 22:56:45.387376 [ 0.000000] Policy zone: Normal
10295 22:56:45.400038 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10296 22:56:45.410092 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10297 22:56:45.421684 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10298 22:56:45.432268 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10299 22:56:45.437968 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10300 22:56:45.441300 <6>[ 0.000000] software IO TLB: area num 8.
10301 22:56:45.498268 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10302 22:56:45.647417 <6>[ 0.000000] Memory: 7952196K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 400572K reserved, 32768K cma-reserved)
10303 22:56:45.654366 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10304 22:56:45.660673 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10305 22:56:45.664041 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10306 22:56:45.670919 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10307 22:56:45.677621 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10308 22:56:45.680983 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10309 22:56:45.690994 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10310 22:56:45.697626 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10311 22:56:45.704212 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10312 22:56:45.710875 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10313 22:56:45.713634 <6>[ 0.000000] GICv3: 608 SPIs implemented
10314 22:56:45.717228 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10315 22:56:45.723455 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10316 22:56:45.727042 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10317 22:56:45.733463 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10318 22:56:45.746731 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10319 22:56:45.756781 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10320 22:56:45.766791 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10321 22:56:45.774057 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10322 22:56:45.786994 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10323 22:56:45.793815 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10324 22:56:45.800487 <6>[ 0.009175] Console: colour dummy device 80x25
10325 22:56:45.810407 <6>[ 0.013902] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10326 22:56:45.816991 <6>[ 0.024344] pid_max: default: 32768 minimum: 301
10327 22:56:45.820395 <6>[ 0.029217] LSM: Security Framework initializing
10328 22:56:45.827226 <6>[ 0.034154] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10329 22:56:45.836814 <6>[ 0.042016] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10330 22:56:45.844172 <6>[ 0.051446] cblist_init_generic: Setting adjustable number of callback queues.
10331 22:56:45.850373 <6>[ 0.058901] cblist_init_generic: Setting shift to 3 and lim to 1.
10332 22:56:45.857118 <6>[ 0.065239] cblist_init_generic: Setting shift to 3 and lim to 1.
10333 22:56:45.863616 <6>[ 0.071685] rcu: Hierarchical SRCU implementation.
10334 22:56:45.866780 <6>[ 0.076699] rcu: Max phase no-delay instances is 1000.
10335 22:56:45.875009 <6>[ 0.083723] EFI services will not be available.
10336 22:56:45.878140 <6>[ 0.088695] smp: Bringing up secondary CPUs ...
10337 22:56:45.887295 <6>[ 0.093749] Detected VIPT I-cache on CPU1
10338 22:56:45.893823 <6>[ 0.093822] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10339 22:56:45.900336 <6>[ 0.093851] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10340 22:56:45.904112 <6>[ 0.094180] Detected VIPT I-cache on CPU2
10341 22:56:45.913627 <6>[ 0.094224] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10342 22:56:45.920242 <6>[ 0.094239] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10343 22:56:45.923842 <6>[ 0.094488] Detected VIPT I-cache on CPU3
10344 22:56:45.930445 <6>[ 0.094530] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10345 22:56:45.937234 <6>[ 0.094544] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10346 22:56:45.939866 <6>[ 0.094848] CPU features: detected: Spectre-v4
10347 22:56:45.946711 <6>[ 0.094855] CPU features: detected: Spectre-BHB
10348 22:56:45.950090 <6>[ 0.094861] Detected PIPT I-cache on CPU4
10349 22:56:45.957117 <6>[ 0.094919] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10350 22:56:45.963515 <6>[ 0.094935] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10351 22:56:45.969916 <6>[ 0.095226] Detected PIPT I-cache on CPU5
10352 22:56:45.976232 <6>[ 0.095289] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10353 22:56:45.983087 <6>[ 0.095305] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10354 22:56:45.986588 <6>[ 0.095589] Detected PIPT I-cache on CPU6
10355 22:56:45.993216 <6>[ 0.095653] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10356 22:56:45.999935 <6>[ 0.095670] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10357 22:56:46.006172 <6>[ 0.095971] Detected PIPT I-cache on CPU7
10358 22:56:46.012903 <6>[ 0.096036] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10359 22:56:46.019914 <6>[ 0.096053] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10360 22:56:46.023019 <6>[ 0.096100] smp: Brought up 1 node, 8 CPUs
10361 22:56:46.029740 <6>[ 0.237467] SMP: Total of 8 processors activated.
10362 22:56:46.033557 <6>[ 0.242419] CPU features: detected: 32-bit EL0 Support
10363 22:56:46.042921 <6>[ 0.247782] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10364 22:56:46.049491 <6>[ 0.256582] CPU features: detected: Common not Private translations
10365 22:56:46.053245 <6>[ 0.263059] CPU features: detected: CRC32 instructions
10366 22:56:46.059895 <6>[ 0.268443] CPU features: detected: RCpc load-acquire (LDAPR)
10367 22:56:46.066505 <6>[ 0.274440] CPU features: detected: LSE atomic instructions
10368 22:56:46.072970 <6>[ 0.280221] CPU features: detected: Privileged Access Never
10369 22:56:46.076578 <6>[ 0.286037] CPU features: detected: RAS Extension Support
10370 22:56:46.086789 <6>[ 0.291645] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10371 22:56:46.089683 <6>[ 0.298864] CPU: All CPU(s) started at EL2
10372 22:56:46.095981 <6>[ 0.303207] alternatives: applying system-wide alternatives
10373 22:56:46.104835 <6>[ 0.313902] devtmpfs: initialized
10374 22:56:46.117446 <6>[ 0.322857] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10375 22:56:46.127081 <6>[ 0.332819] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10376 22:56:46.133670 <6>[ 0.341009] pinctrl core: initialized pinctrl subsystem
10377 22:56:46.137286 <6>[ 0.347649] DMI not present or invalid.
10378 22:56:46.143681 <6>[ 0.352058] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10379 22:56:46.154058 <6>[ 0.358947] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10380 22:56:46.160536 <6>[ 0.366520] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10381 22:56:46.170552 <6>[ 0.374742] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10382 22:56:46.173811 <6>[ 0.382987] audit: initializing netlink subsys (disabled)
10383 22:56:46.183898 <5>[ 0.388683] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10384 22:56:46.190714 <6>[ 0.389380] thermal_sys: Registered thermal governor 'step_wise'
10385 22:56:46.197332 <6>[ 0.396645] thermal_sys: Registered thermal governor 'power_allocator'
10386 22:56:46.201114 <6>[ 0.402898] cpuidle: using governor menu
10387 22:56:46.204157 <6>[ 0.413859] NET: Registered PF_QIPCRTR protocol family
10388 22:56:46.213817 <6>[ 0.419339] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10389 22:56:46.217074 <6>[ 0.426443] ASID allocator initialised with 32768 entries
10390 22:56:46.224030 <6>[ 0.433005] Serial: AMBA PL011 UART driver
10391 22:56:46.233030 <4>[ 0.441574] Trying to register duplicate clock ID: 134
10392 22:56:46.286443 <6>[ 0.498745] KASLR enabled
10393 22:56:46.300804 <6>[ 0.506466] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10394 22:56:46.307708 <6>[ 0.513482] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10395 22:56:46.314420 <6>[ 0.519970] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10396 22:56:46.320572 <6>[ 0.526972] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10397 22:56:46.327712 <6>[ 0.533460] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10398 22:56:46.334192 <6>[ 0.540463] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10399 22:56:46.340848 <6>[ 0.546951] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10400 22:56:46.347216 <6>[ 0.553954] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10401 22:56:46.350418 <6>[ 0.561433] ACPI: Interpreter disabled.
10402 22:56:46.359475 <6>[ 0.567850] iommu: Default domain type: Translated
10403 22:56:46.365676 <6>[ 0.572966] iommu: DMA domain TLB invalidation policy: strict mode
10404 22:56:46.369132 <5>[ 0.579622] SCSI subsystem initialized
10405 22:56:46.375978 <6>[ 0.583865] usbcore: registered new interface driver usbfs
10406 22:56:46.382531 <6>[ 0.589594] usbcore: registered new interface driver hub
10407 22:56:46.385709 <6>[ 0.595145] usbcore: registered new device driver usb
10408 22:56:46.392044 <6>[ 0.601247] pps_core: LinuxPPS API ver. 1 registered
10409 22:56:46.402407 <6>[ 0.606441] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10410 22:56:46.406062 <6>[ 0.615784] PTP clock support registered
10411 22:56:46.408633 <6>[ 0.620022] EDAC MC: Ver: 3.0.0
10412 22:56:46.416227 <6>[ 0.625192] FPGA manager framework
10413 22:56:46.422788 <6>[ 0.628871] Advanced Linux Sound Architecture Driver Initialized.
10414 22:56:46.426072 <6>[ 0.635637] vgaarb: loaded
10415 22:56:46.433072 <6>[ 0.638796] clocksource: Switched to clocksource arch_sys_counter
10416 22:56:46.435903 <5>[ 0.645245] VFS: Disk quotas dquot_6.6.0
10417 22:56:46.442817 <6>[ 0.649432] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10418 22:56:46.445853 <6>[ 0.656625] pnp: PnP ACPI: disabled
10419 22:56:46.454230 <6>[ 0.663295] NET: Registered PF_INET protocol family
10420 22:56:46.461554 <6>[ 0.668877] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10421 22:56:46.475842 <6>[ 0.681101] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10422 22:56:46.485668 <6>[ 0.689919] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10423 22:56:46.492213 <6>[ 0.697885] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10424 22:56:46.498710 <6>[ 0.706586] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10425 22:56:46.510863 <6>[ 0.716301] TCP: Hash tables configured (established 65536 bind 65536)
10426 22:56:46.517781 <6>[ 0.723160] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10427 22:56:46.524467 <6>[ 0.730361] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10428 22:56:46.530850 <6>[ 0.738065] NET: Registered PF_UNIX/PF_LOCAL protocol family
10429 22:56:46.537512 <6>[ 0.744221] RPC: Registered named UNIX socket transport module.
10430 22:56:46.540416 <6>[ 0.750377] RPC: Registered udp transport module.
10431 22:56:46.546974 <6>[ 0.755312] RPC: Registered tcp transport module.
10432 22:56:46.554022 <6>[ 0.760241] RPC: Registered tcp NFSv4.1 backchannel transport module.
10433 22:56:46.557626 <6>[ 0.766912] PCI: CLS 0 bytes, default 64
10434 22:56:46.560696 <6>[ 0.771280] Unpacking initramfs...
10435 22:56:46.578090 <6>[ 0.783361] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10436 22:56:46.587933 <6>[ 0.792018] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10437 22:56:46.591410 <6>[ 0.800861] kvm [1]: IPA Size Limit: 40 bits
10438 22:56:46.597625 <6>[ 0.805388] kvm [1]: GICv3: no GICV resource entry
10439 22:56:46.601432 <6>[ 0.810410] kvm [1]: disabling GICv2 emulation
10440 22:56:46.608088 <6>[ 0.815094] kvm [1]: GIC system register CPU interface enabled
10441 22:56:46.611484 <6>[ 0.821258] kvm [1]: vgic interrupt IRQ18
10442 22:56:46.618718 <6>[ 0.826884] kvm [1]: VHE mode initialized successfully
10443 22:56:46.624709 <5>[ 0.833278] Initialise system trusted keyrings
10444 22:56:46.631167 <6>[ 0.838080] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10445 22:56:46.639012 <6>[ 0.848170] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10446 22:56:46.646075 <5>[ 0.854561] NFS: Registering the id_resolver key type
10447 22:56:46.649556 <5>[ 0.859864] Key type id_resolver registered
10448 22:56:46.655934 <5>[ 0.864281] Key type id_legacy registered
10449 22:56:46.662376 <6>[ 0.868565] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10450 22:56:46.668786 <6>[ 0.875488] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10451 22:56:46.675615 <6>[ 0.883229] 9p: Installing v9fs 9p2000 file system support
10452 22:56:46.712966 <5>[ 0.921429] Key type asymmetric registered
10453 22:56:46.715845 <5>[ 0.925760] Asymmetric key parser 'x509' registered
10454 22:56:46.726224 <6>[ 0.930916] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10455 22:56:46.728830 <6>[ 0.938530] io scheduler mq-deadline registered
10456 22:56:46.732673 <6>[ 0.943290] io scheduler kyber registered
10457 22:56:46.751175 <6>[ 0.960086] EINJ: ACPI disabled.
10458 22:56:46.783413 <4>[ 0.985325] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10459 22:56:46.793048 <4>[ 0.996086] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10460 22:56:46.807918 <6>[ 1.016579] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10461 22:56:46.816074 <6>[ 1.024503] printk: console [ttyS0] disabled
10462 22:56:46.843928 <6>[ 1.049160] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10463 22:56:46.850655 <6>[ 1.058634] printk: console [ttyS0] enabled
10464 22:56:46.853685 <6>[ 1.058634] printk: console [ttyS0] enabled
10465 22:56:46.859832 <6>[ 1.067533] printk: bootconsole [mtk8250] disabled
10466 22:56:46.863447 <6>[ 1.067533] printk: bootconsole [mtk8250] disabled
10467 22:56:46.869784 <6>[ 1.078913] SuperH (H)SCI(F) driver initialized
10468 22:56:46.873424 <6>[ 1.084193] msm_serial: driver initialized
10469 22:56:46.887391 <6>[ 1.093179] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10470 22:56:46.897234 <6>[ 1.101729] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10471 22:56:46.904456 <6>[ 1.110277] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10472 22:56:46.914343 <6>[ 1.118905] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10473 22:56:46.924186 <6>[ 1.127611] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10474 22:56:46.930603 <6>[ 1.136325] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10475 22:56:46.940573 <6>[ 1.144868] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10476 22:56:46.947181 <6>[ 1.153675] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10477 22:56:46.957467 <6>[ 1.162221] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10478 22:56:46.968935 <6>[ 1.178091] loop: module loaded
10479 22:56:46.975890 <6>[ 1.184140] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10480 22:56:46.998496 <4>[ 1.207570] mtk-pmic-keys: Failed to locate of_node [id: -1]
10481 22:56:47.005652 <6>[ 1.214352] megasas: 07.719.03.00-rc1
10482 22:56:47.015421 <6>[ 1.224053] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10483 22:56:47.021968 <6>[ 1.230212] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10484 22:56:47.038011 <6>[ 1.246270] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10485 22:56:47.093638 <6>[ 1.296166] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.153/cr50_v3.94_pp.113-620c9
10486 22:56:47.441970 <6>[ 1.651018] Freeing initrd memory: 20740K
10487 22:56:47.457900 <6>[ 1.666812] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10488 22:56:47.469244 <6>[ 1.677915] tun: Universal TUN/TAP device driver, 1.6
10489 22:56:47.472247 <6>[ 1.683986] thunder_xcv, ver 1.0
10490 22:56:47.476184 <6>[ 1.687492] thunder_bgx, ver 1.0
10491 22:56:47.479055 <6>[ 1.690987] nicpf, ver 1.0
10492 22:56:47.489467 <6>[ 1.695028] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10493 22:56:47.492863 <6>[ 1.702503] hns3: Copyright (c) 2017 Huawei Corporation.
10494 22:56:47.496418 <6>[ 1.708090] hclge is initializing
10495 22:56:47.503064 <6>[ 1.711666] e1000: Intel(R) PRO/1000 Network Driver
10496 22:56:47.509965 <6>[ 1.716796] e1000: Copyright (c) 1999-2006 Intel Corporation.
10497 22:56:47.512872 <6>[ 1.722813] e1000e: Intel(R) PRO/1000 Network Driver
10498 22:56:47.519174 <6>[ 1.728029] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10499 22:56:47.525950 <6>[ 1.734215] igb: Intel(R) Gigabit Ethernet Network Driver
10500 22:56:47.532250 <6>[ 1.739865] igb: Copyright (c) 2007-2014 Intel Corporation.
10501 22:56:47.539321 <6>[ 1.745701] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10502 22:56:47.545585 <6>[ 1.752218] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10503 22:56:47.549826 <6>[ 1.758685] sky2: driver version 1.30
10504 22:56:47.555537 <6>[ 1.763670] VFIO - User Level meta-driver version: 0.3
10505 22:56:47.562954 <6>[ 1.771882] usbcore: registered new interface driver usb-storage
10506 22:56:47.569558 <6>[ 1.778327] usbcore: registered new device driver onboard-usb-hub
10507 22:56:47.578753 <6>[ 1.787448] mt6397-rtc mt6359-rtc: registered as rtc0
10508 22:56:47.588748 <6>[ 1.792914] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-05T22:56:40 UTC (1686005800)
10509 22:56:47.591478 <6>[ 1.802481] i2c_dev: i2c /dev entries driver
10510 22:56:47.609075 <6>[ 1.814200] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10511 22:56:47.616089 <6>[ 1.824433] sdhci: Secure Digital Host Controller Interface driver
10512 22:56:47.622173 <6>[ 1.830874] sdhci: Copyright(c) Pierre Ossman
10513 22:56:47.628748 <6>[ 1.836282] Synopsys Designware Multimedia Card Interface Driver
10514 22:56:47.631852 <6>[ 1.842889] mmc0: CQHCI version 5.10
10515 22:56:47.639009 <6>[ 1.843433] sdhci-pltfm: SDHCI platform and OF driver helper
10516 22:56:47.645651 <6>[ 1.854732] ledtrig-cpu: registered to indicate activity on CPUs
10517 22:56:47.656069 <6>[ 1.862062] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10518 22:56:47.659729 <6>[ 1.869447] usbcore: registered new interface driver usbhid
10519 22:56:47.666085 <6>[ 1.875279] usbhid: USB HID core driver
10520 22:56:47.672928 <6>[ 1.879523] spi_master spi0: will run message pump with realtime priority
10521 22:56:47.719310 <6>[ 1.921741] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10522 22:56:47.738662 <6>[ 1.937279] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10523 22:56:47.741854 <6>[ 1.950876] mmc0: Command Queue Engine enabled
10524 22:56:47.749087 <6>[ 1.952600] cros-ec-spi spi0.0: Chrome EC device registered
10525 22:56:47.755733 <6>[ 1.955607] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10526 22:56:47.758955 <6>[ 1.968970] mmcblk0: mmc0:0001 DA4128 116 GiB
10527 22:56:47.774169 <6>[ 1.979670] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10528 22:56:47.780575 <6>[ 1.980493] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10529 22:56:47.787211 <6>[ 1.991185] NET: Registered PF_PACKET protocol family
10530 22:56:47.790951 <6>[ 1.996356] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10531 22:56:47.797467 <6>[ 2.000345] 9pnet: Installing 9P2000 support
10532 22:56:47.800895 <6>[ 2.006094] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10533 22:56:47.807470 <5>[ 2.010016] Key type dns_resolver registered
10534 22:56:47.810891 <6>[ 2.015862] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10535 22:56:47.817798 <6>[ 2.020308] registered taskstats version 1
10536 22:56:47.820957 <5>[ 2.030619] Loading compiled-in X.509 certificates
10537 22:56:47.856794 <4>[ 2.058711] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10538 22:56:47.866374 <4>[ 2.069405] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10539 22:56:47.876384 <3>[ 2.082134] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10540 22:56:47.888664 <6>[ 2.097677] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10541 22:56:47.895233 <6>[ 2.104490] xhci-mtk 11200000.usb: xHCI Host Controller
10542 22:56:47.901787 <6>[ 2.109990] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10543 22:56:47.912663 <6>[ 2.117851] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10544 22:56:47.919000 <6>[ 2.127289] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10545 22:56:47.926345 <6>[ 2.133371] xhci-mtk 11200000.usb: xHCI Host Controller
10546 22:56:47.932303 <6>[ 2.138854] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10547 22:56:47.939287 <6>[ 2.146617] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10548 22:56:47.946155 <6>[ 2.154394] hub 1-0:1.0: USB hub found
10549 22:56:47.949489 <6>[ 2.158417] hub 1-0:1.0: 1 port detected
10550 22:56:47.955557 <6>[ 2.162754] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10551 22:56:47.962500 <6>[ 2.171539] hub 2-0:1.0: USB hub found
10552 22:56:47.965930 <6>[ 2.175571] hub 2-0:1.0: 1 port detected
10553 22:56:47.973754 <6>[ 2.182744] mtk-msdc 11f70000.mmc: Got CD GPIO
10554 22:56:47.992019 <6>[ 2.197188] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10555 22:56:47.998650 <6>[ 2.205246] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10556 22:56:48.008652 <4>[ 2.213233] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10557 22:56:48.018585 <6>[ 2.222892] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10558 22:56:48.025128 <6>[ 2.230980] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10559 22:56:48.031777 <6>[ 2.239006] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10560 22:56:48.042061 <6>[ 2.246924] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10561 22:56:48.048565 <6>[ 2.254746] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10562 22:56:48.058691 <6>[ 2.262567] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10563 22:56:48.068245 <6>[ 2.273137] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10564 22:56:48.075211 <6>[ 2.281502] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10565 22:56:48.085005 <6>[ 2.289858] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10566 22:56:48.092075 <6>[ 2.298203] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10567 22:56:48.101501 <6>[ 2.306547] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10568 22:56:48.108380 <6>[ 2.314891] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10569 22:56:48.118138 <6>[ 2.323235] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10570 22:56:48.124610 <6>[ 2.331579] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10571 22:56:48.135162 <6>[ 2.339923] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10572 22:56:48.141756 <6>[ 2.348267] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10573 22:56:48.151564 <6>[ 2.356611] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10574 22:56:48.158242 <6>[ 2.364959] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10575 22:56:48.168013 <6>[ 2.373303] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10576 22:56:48.175185 <6>[ 2.381646] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10577 22:56:48.184899 <6>[ 2.389989] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10578 22:56:48.191417 <6>[ 2.398875] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10579 22:56:48.197716 <6>[ 2.406263] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10580 22:56:48.204309 <6>[ 2.413327] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10581 22:56:48.214883 <6>[ 2.420449] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10582 22:56:48.221153 <6>[ 2.427749] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10583 22:56:48.231692 <6>[ 2.434661] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10584 22:56:48.238018 <6>[ 2.443801] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10585 22:56:48.247809 <6>[ 2.452928] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10586 22:56:48.258078 <6>[ 2.462230] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10587 22:56:48.267688 <6>[ 2.471705] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10588 22:56:48.277655 <6>[ 2.481179] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10589 22:56:48.284257 <6>[ 2.490305] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10590 22:56:48.293826 <6>[ 2.499784] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10591 22:56:48.304003 <6>[ 2.508910] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10592 22:56:48.313773 <6>[ 2.518213] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10593 22:56:48.323767 <6>[ 2.528378] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10594 22:56:48.334842 <6>[ 2.540144] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10595 22:56:48.377144 <6>[ 2.583072] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10596 22:56:48.530162 <6>[ 2.739743] hub 1-1:1.0: USB hub found
10597 22:56:48.533129 <6>[ 2.744168] hub 1-1:1.0: 4 ports detected
10598 22:56:48.656724 <6>[ 2.863269] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10599 22:56:48.682198 <6>[ 2.891384] hub 2-1:1.0: USB hub found
10600 22:56:48.685105 <6>[ 2.895782] hub 2-1:1.0: 3 ports detected
10601 22:56:48.852531 <6>[ 3.059069] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10602 22:56:48.985764 <6>[ 3.195236] hub 1-1.4:1.0: USB hub found
10603 22:56:48.988832 <6>[ 3.199879] hub 1-1.4:1.0: 2 ports detected
10604 22:56:49.065104 <6>[ 3.271344] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10605 22:56:49.288546 <6>[ 3.495070] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10606 22:56:49.480579 <6>[ 3.687069] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10607 22:57:00.613464 <6>[ 14.827638] ALSA device list:
10608 22:57:00.619915 <6>[ 14.830896] No soundcards found.
10609 22:57:00.632117 <6>[ 14.843298] Freeing unused kernel memory: 8384K
10610 22:57:00.635656 <6>[ 14.848231] Run /init as init process
10611 22:57:00.661664 Starting syslogd: OK
10612 22:57:00.665645 Starting klogd: OK
10613 22:57:00.675013 Running sysctl: OK
10614 22:57:00.684636 Populating /dev using udev: <30>[ 14.894713] udevd[187]: starting version 3.2.9
10615 22:57:00.691577 <27>[ 14.902820] udevd[187]: specified user 'tss' unknown
10616 22:57:00.698676 <27>[ 14.908183] udevd[187]: specified group 'tss' unknown
10617 22:57:00.704461 <30>[ 14.914690] udevd[188]: starting eudev-3.2.9
10618 22:57:00.733918 <27>[ 14.944686] udevd[188]: specified user 'tss' unknown
10619 22:57:00.740045 <27>[ 14.950063] udevd[188]: specified group 'tss' unknown
10620 22:57:00.940886 <6>[ 15.148605] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10621 22:57:00.951686 <6>[ 15.159571] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10622 22:57:00.955335 <6>[ 15.160014] remoteproc remoteproc0: scp is available
10623 22:57:00.965246 <6>[ 15.167227] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10624 22:57:00.975205 <4>[ 15.172691] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10625 22:57:00.984914 <6>[ 15.181183] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10626 22:57:00.988455 <6>[ 15.191039] remoteproc remoteproc0: powering up scp
10627 22:57:00.998752 <3>[ 15.195860] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10628 22:57:01.005189 <3>[ 15.195877] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10629 22:57:01.011621 <3>[ 15.195885] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10630 22:57:01.021672 <3>[ 15.196366] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10631 22:57:01.028190 <3>[ 15.196380] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10632 22:57:01.038201 <3>[ 15.196388] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10633 22:57:01.045254 <3>[ 15.196397] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10634 22:57:01.055319 <3>[ 15.196404] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10635 22:57:01.061548 <3>[ 15.196452] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10636 22:57:01.068504 <3>[ 15.196498] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10637 22:57:01.078464 <3>[ 15.196505] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10638 22:57:01.085544 <3>[ 15.196511] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10639 22:57:01.095505 <3>[ 15.196557] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10640 22:57:01.102785 <3>[ 15.196564] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10641 22:57:01.109868 <3>[ 15.196570] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10642 22:57:01.119653 <3>[ 15.196576] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10643 22:57:01.126308 <3>[ 15.196582] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10644 22:57:01.136417 <3>[ 15.196620] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10645 22:57:01.139567 <6>[ 15.196801] mc: Linux media interface: v0.10
10646 22:57:01.146518 <6>[ 15.207701] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10647 22:57:01.156325 <4>[ 15.213016] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10648 22:57:01.162723 <6>[ 15.214500] usbcore: registered new interface driver r8152
10649 22:57:01.169479 <6>[ 15.226296] videodev: Linux video capture interface: v2.00
10650 22:57:01.176096 <3>[ 15.229286] remoteproc remoteproc0: request_firmware failed: -2
10651 22:57:01.182601 <4>[ 15.256154] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10652 22:57:01.189545 <4>[ 15.256154] Fallback method does not support PEC.
10653 22:57:01.195867 <4>[ 15.263399] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10654 22:57:01.202562 <6>[ 15.275063] usbcore: registered new interface driver cdc_ether
10655 22:57:01.209502 <4>[ 15.279408] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10656 22:57:01.215988 <6>[ 15.295098] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10657 22:57:01.225856 <3>[ 15.299398] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10658 22:57:01.235922 <3>[ 15.322350] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10659 22:57:01.239246 <6>[ 15.334017] Bluetooth: Core ver 2.22
10660 22:57:01.245463 <6>[ 15.334535] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10661 22:57:01.252054 <6>[ 15.342625] NET: Registered PF_BLUETOOTH protocol family
10662 22:57:01.259045 <6>[ 15.342630] Bluetooth: HCI device and connection manager initialized
10663 22:57:01.262540 <6>[ 15.342665] Bluetooth: HCI socket layer initialized
10664 22:57:01.268935 <6>[ 15.342681] Bluetooth: L2CAP socket layer initialized
10665 22:57:01.271851 <6>[ 15.342703] Bluetooth: SCO socket layer initialized
10666 22:57:01.282129 <6>[ 15.467207] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10667 22:57:01.288984 <6>[ 15.473738] pci_bus 0000:00: root bus resource [bus 00-ff]
10668 22:57:01.298881 <6>[ 15.475207] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10669 22:57:01.308363 <6>[ 15.475570] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10670 22:57:01.315065 <4>[ 15.476026] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10671 22:57:01.325101 <4>[ 15.476036] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10672 22:57:01.331475 <6>[ 15.494211] usbcore: registered new interface driver r8153_ecm
10673 22:57:01.338204 <6>[ 15.498547] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10674 22:57:01.344962 <6>[ 15.507065] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10675 22:57:01.354740 <6>[ 15.514425] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10676 22:57:01.361778 <6>[ 15.514493] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10677 22:57:01.374772 <6>[ 15.525032] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10678 22:57:01.381322 <6>[ 15.532565] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10679 22:57:01.387779 <6>[ 15.533222] usbcore: registered new interface driver btusb
10680 22:57:01.394525 <6>[ 15.533988] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10681 22:57:01.404627 <4>[ 15.534014] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10682 22:57:01.411126 <3>[ 15.534024] Bluetooth: hci0: Failed to load firmware file (-2)
10683 22:57:01.414272 <3>[ 15.534028] Bluetooth: hci0: Failed to set up firmware (-2)
10684 22:57:01.424616 <4>[ 15.534032] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10685 22:57:01.430920 <6>[ 15.539004] remoteproc remoteproc0: powering up scp
10686 22:57:01.441003 <4>[ 15.539041] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10687 22:57:01.447891 <3>[ 15.539049] remoteproc remoteproc0: request_firmware failed: -2
10688 22:57:01.454343 <3>[ 15.539053] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
10689 22:57:01.461312 <6>[ 15.540936] usbcore: registered new interface driver uvcvideo
10690 22:57:01.464331 <6>[ 15.543038] r8152 2-1.3:1.0 eth0: v1.12.13
10691 22:57:01.470679 <6>[ 15.546814] pci 0000:00:00.0: supports D1 D2
10692 22:57:01.477248 <6>[ 15.685565] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10693 22:57:01.487266 <6>[ 15.694486] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10694 22:57:01.494504 <6>[ 15.703254] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10695 22:57:01.501197 <6>[ 15.709628] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10696 22:57:01.507698 <6>[ 15.717130] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10697 22:57:01.517618 <6>[ 15.724623] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10698 22:57:01.520786 <6>[ 15.732212] pci 0000:01:00.0: supports D1 D2
10699 22:57:01.527078 <6>[ 15.736739] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10700 22:57:01.551112 <6>[ 15.759013] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10701 22:57:01.557848 <6>[ 15.765953] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10702 22:57:01.564328 <6>[ 15.774046] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10703 22:57:01.574434 <6>[ 15.782053] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10704 22:57:01.581038 <6>[ 15.790062] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10705 22:57:01.591187 <6>[ 15.798068] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10706 22:57:01.594061 <6>[ 15.806077] pci 0000:00:00.0: PCI bridge to [bus 01]
10707 22:57:01.604163 <6>[ 15.811298] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10708 22:57:01.611014 <6>[ 15.819507] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10709 22:57:01.617510 <6>[ 15.826764] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10710 22:57:01.623966 <6>[ 15.833534] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10711 22:57:01.641915 <5>[ 15.849765] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10712 22:57:01.674807 <5>[ 15.882267] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10713 22:57:01.681047 <4>[ 15.889148] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10714 22:57:01.687674 <6>[ 15.898041] cfg80211: failed to load regulatory.db
10715 22:57:01.733625 <6>[ 15.941265] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10716 22:57:01.740369 <6>[ 15.948780] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10717 22:57:01.764386 <6>[ 15.975546] mt7921e 0000:01:00.0: ASIC revision: 79610010
10718 22:57:01.870114 <4>[ 16.074761] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10719 22:57:01.870265 done
10720 22:57:01.890444 Saving random seed: OK
10721 22:57:01.906174 Starting network: OK
10722 22:57:01.944947 Starting dropbear sshd: <6>[ 16.155761] NET: Registered PF_INET6 protocol family
10723 22:57:01.951055 <6>[ 16.162428] Segment Routing with IPv6
10724 22:57:01.954391 <6>[ 16.166451] In-situ OAM (IOAM) with IPv6
10725 22:57:01.958307 OK
10726 22:57:01.968438 /bin/sh: can't access tty; job control turned off
10727 22:57:01.968786 Matched prompt #10: / #
10729 22:57:01.968999 Setting prompt string to ['/ #']
10730 22:57:01.969092 end: 2.2.5.1 login-action (duration 00:00:17) [common]
10732 22:57:01.969282 end: 2.2.5 auto-login-action (duration 00:00:17) [common]
10733 22:57:01.969368 start: 2.2.6 expect-shell-connection (timeout 00:03:43) [common]
10734 22:57:01.969437 Setting prompt string to ['/ #']
10735 22:57:01.969499 Forcing a shell prompt, looking for ['/ #']
10737 22:57:02.019731 / #
10738 22:57:02.019910 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10739 22:57:02.019997 Waiting using forced prompt support (timeout 00:02:30)
10740 22:57:02.020101 <4>[ 16.197401] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10741 22:57:02.024721
10742 22:57:02.025002 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10743 22:57:02.025100 start: 2.2.7 export-device-env (timeout 00:03:43) [common]
10744 22:57:02.025197 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10745 22:57:02.025286 end: 2.2 depthcharge-retry (duration 00:01:17) [common]
10746 22:57:02.025372 end: 2 depthcharge-action (duration 00:01:17) [common]
10747 22:57:02.025457 start: 3 lava-test-retry (timeout 00:01:00) [common]
10748 22:57:02.025541 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
10749 22:57:02.025611 Using namespace: common
10751 22:57:02.125946 / # #
10752 22:57:02.126130 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10753 22:57:02.126281 #<4>[ 16.317450] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10754 22:57:02.131172
10755 22:57:02.131475 Using /lava-10597683
10757 22:57:02.231840 / # export SHELL=/bin/sh
10758 22:57:02.233292 export SHELL=/bin/sh<4>[ 16.437413] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10759 22:57:02.275509
10761 22:57:02.376148 / # . /lava-10597683/environment
10762 22:57:02.376400 . /lava-10597683/environment<4>[ 16.557814] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10763 22:57:02.381644
10765 22:57:02.482199 / # /lava-10597683/bin/lava-test-runner /lava-10597683/0
10766 22:57:02.482451 Test shell timeout: 10s (minimum of the action and connection timeout)
10767 22:57:02.483084 /lava-10597683/bin/lava-test-runner /lava-10597683/0<4>[ 16.677389] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10768 22:57:02.488543
10769 22:57:02.531477 + export 'TESTRUN_ID=0_dmesg'
10770 22:57:02.531702 +<8>[ 16.722393] <LAVA_SIGNAL_STARTRUN 0_dmesg 10597683_1.5.2.3.1>
10771 22:57:02.531832 cd /lava-10597683/0/tests/0_dmesg
10772 22:57:02.531956 + cat uuid
10773 22:57:02.532081 + UUID=10597683_1.5.2.3.1
10774 22:57:02.532199 + set +x
10775 22:57:02.532322 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
10776 22:57:02.532636 Received signal: <STARTRUN> 0_dmesg 10597683_1.5.2.3.1
10777 22:57:02.532773 Starting test lava.0_dmesg (10597683_1.5.2.3.1)
10778 22:57:02.532934 Skipping test definition patterns.
10779 22:57:02.535974 <8>[ 16.742394] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
10780 22:57:02.536290 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
10782 22:57:02.555338 <8>[ 16.762950] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
10783 22:57:02.555729 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
10785 22:57:02.576103 <8>[ 16.783928] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
10786 22:57:02.576512 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
10788 22:57:02.580277 + set +x
10789 22:57:02.583376 Received signal: <ENDRUN> 0_dmesg 10597683_1.5.2.3.1
10790 22:57:02.583561 Ending use of test pattern.
10791 22:57:02.583690 Ending test lava.0_dmesg (10597683_1.5.2.3.1), duration 0.05
10793 22:57:02.586522 <8>[ 16.794838] <LAVA_SIGNAL_ENDRUN 0_dmesg 10597683_1.5.2.3.1>
10794 22:57:02.596894 <4>[ 16.797751] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10795 22:57:02.599784 <LAVA_TEST_RUNNER EXIT>
10796 22:57:02.600108 ok: lava_test_shell seems to have completed
10797 22:57:02.600309 alert: pass
crit: pass
emerg: pass
10798 22:57:02.600469 end: 3.1 lava-test-shell (duration 00:00:01) [common]
10799 22:57:02.600625 end: 3 lava-test-retry (duration 00:00:01) [common]
10800 22:57:02.600775 start: 4 lava-test-retry (timeout 00:01:00) [common]
10801 22:57:02.600956 start: 4.1 lava-test-shell (timeout 00:01:00) [common]
10802 22:57:02.601081 Using namespace: common
10804 22:57:02.701530 / # #
10805 22:57:02.701786 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10806 22:57:02.701982 Using /lava-10597683
10808 22:57:02.802410 export SHELL=/bin/sh
10809 22:57:02.802716 #<4>[ 16.921319] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10810 22:57:02.802852
10812 22:57:02.903483 / # export SHELL=/bin/sh. /lava-10597683/environment
10813 22:57:02.903832
10814 22:57:02.903969 / # <4>[ 17.041467] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10816 22:57:03.004559 . /lava-10597683/environment/lava-10597683/bin/lava-test-runner /lava-10597683/1
10817 22:57:03.004734 Test shell timeout: 10s (minimum of the action and connection timeout)
10818 22:57:03.004857
10819 22:57:03.004925 / # <4>[ 17.161181] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10820 22:57:03.010280 /lava-10597683/bin/lava-test-runner /lava-10597683/1
10821 22:57:03.051570 + export 'TESTRUN_ID=1_bootrr'
10822 22:57:03.051735 <8>[ 17.243147] <LAVA_SIGNAL_STARTRUN 1_bootrr 10597683_1.5.2.3.5>
10823 22:57:03.051804 + cd /lava-10597683/1/tests/1_bootrr
10824 22:57:03.051866 + cat uuid
10825 22:57:03.051925 + UUID=10597683_1.5.2.3.5
10826 22:57:03.051983 + set +x
10827 22:57:03.052039 + export 'PATH=/opt/bootrr/libexec/bootrr/helpers:/lava-10597683/1/../bin:/sbin:/usr/sbin:/bin:/usr/bin'
10828 22:57:03.052282 Received signal: <STARTRUN> 1_bootrr 10597683_1.5.2.3.5
10829 22:57:03.052349 Starting test lava.1_bootrr (10597683_1.5.2.3.5)
10830 22:57:03.052428 Skipping test definition patterns.
10831 22:57:03.056652 <8>[ 17.265827] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=deferred-probe-empty RESULT=pass>
10832 22:57:03.056967 Received signal: <TESTCASE> TEST_CASE_ID=deferred-probe-empty RESULT=pass
10834 22:57:03.060127
10835 22:57:03.060224 + cd /opt/bootrr/libexec/bootrr
10836 22:57:03.063299 + sh helpers/bootrr-auto
10837 22:57:03.066630 /lava-10597683/1/../bin/lava-test-case
10838 22:57:03.077730 <3>[ 17.288648] mt7921e 0000:01:00.0: hardware init failed
10839 22:57:03.081127 /lava-10597683/1/../bin/lava-test-case
10840 22:57:03.090574 <8>[ 17.298129] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=all-cpus-are-online RESULT=pass>
10841 22:57:03.090901 Received signal: <TESTCASE> TEST_CASE_ID=all-cpus-are-online RESULT=pass
10843 22:57:03.094683 /usr/bin/tpm2_getcap
10844 22:57:03.128121 /lava-10597683/1/../bin/lava-test-case
10845 22:57:03.134422 <8>[ 17.342458] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm-chip-is-online RESULT=pass>
10846 22:57:03.134760 Received signal: <TESTCASE> TEST_CASE_ID=tpm-chip-is-online RESULT=pass
10848 22:57:03.150064 /lava-10597683/1/../bin/lava-test-case
10849 22:57:03.156939 <8>[ 17.364757] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass>
10850 22:57:03.157277 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass
10852 22:57:03.169140 /lava-10597683/1/../bin/lava-test-case
10853 22:57:03.175831 <8>[ 17.383836] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass>
10854 22:57:03.176157 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass
10856 22:57:03.187386 /lava-10597683/1/../bin/lava-test-case
10857 22:57:03.194244 <8>[ 17.401675] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass>
10858 22:57:03.194584 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass
10860 22:57:03.205894 /lava-10597683/1/../bin/lava-test-case
10861 22:57:03.212545 <8>[ 17.420549] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass>
10862 22:57:03.212884 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass
10864 22:57:03.223876 /lava-10597683/1/../bin/lava-test-case
10865 22:57:03.230656 <8>[ 17.438930] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass>
10866 22:57:03.230983 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass
10868 22:57:03.240691 /lava-10597683/1/../bin/lava-test-case
10869 22:57:03.247517 <8>[ 17.455381] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass>
10870 22:57:03.247859 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass
10872 22:57:03.259346 /lava-10597683/1/../bin/lava-test-case
10873 22:57:03.265639 <8>[ 17.473537] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass>
10874 22:57:03.265997 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass
10876 22:57:03.274956 /lava-10597683/1/../bin/lava-test-case
10877 22:57:03.281446 <8>[ 17.489479] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass>
10878 22:57:03.281774 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass
10880 22:57:03.294516 /lava-10597683/1/../bin/lava-test-case
10881 22:57:03.301044 <8>[ 17.509477] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass>
10882 22:57:03.301363 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass
10884 22:57:03.313229 /lava-10597683/1/../bin/lava-test-case
10885 22:57:03.319863 <8>[ 17.528240] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass>
10886 22:57:03.320147 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass
10888 22:57:03.332976 /lava-10597683/1/../bin/lava-test-case
10889 22:57:03.339356 <8>[ 17.547212] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass>
10890 22:57:03.339694 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass
10892 22:57:03.351010 /lava-10597683/1/../bin/lava-test-case
10893 22:57:03.357937 <8>[ 17.565980] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass>
10894 22:57:03.358283 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass
10896 22:57:03.368057 /lava-10597683/1/../bin/lava-test-case
10897 22:57:03.374766 <8>[ 17.583070] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass>
10898 22:57:03.375104 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass
10900 22:57:03.386827 /lava-10597683/1/../bin/lava-test-case
10901 22:57:03.393453 <8>[ 17.601472] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass>
10902 22:57:03.393779 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass
10904 22:57:03.402550 /lava-10597683/1/../bin/lava-test-case
10905 22:57:03.409554 <8>[ 17.617568] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass>
10906 22:57:03.409838 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass
10908 22:57:03.420728 /lava-10597683/1/../bin/lava-test-case
10909 22:57:03.427828 <8>[ 17.635638] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass>
10910 22:57:03.428094 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass
10912 22:57:03.436648 /lava-10597683/1/../bin/lava-test-case
10913 22:57:03.443253 <8>[ 17.651213] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass>
10914 22:57:03.443557 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass
10916 22:57:03.455149 /lava-10597683/1/../bin/lava-test-case
10917 22:57:03.461681 <8>[ 17.669632] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-probed RESULT=pass>
10918 22:57:03.461952 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-probed RESULT=pass
10920 22:57:03.470808 /lava-10597683/1/../bin/lava-test-case
10921 22:57:03.477063 <8>[ 17.685371] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass>
10922 22:57:03.477340 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass
10924 22:57:03.488677 /lava-10597683/1/../bin/lava-test-case
10925 22:57:03.495289 <8>[ 17.703753] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass>
10926 22:57:03.495667 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass
10928 22:57:03.504550 /lava-10597683/1/../bin/lava-test-case
10929 22:57:03.511121 <8>[ 17.719652] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass>
10930 22:57:03.511566 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass
10932 22:57:03.523498 /lava-10597683/1/../bin/lava-test-case
10933 22:57:03.530033 <8>[ 17.737966] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass>
10934 22:57:03.530423 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass
10936 22:57:03.541163 /lava-10597683/1/../bin/lava-test-case
10937 22:57:03.547622 <8>[ 17.755856] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass>
10938 22:57:03.547988 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass
10940 22:57:03.556596 /lava-10597683/1/../bin/lava-test-case
10941 22:57:03.563198 <8>[ 17.771137] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass>
10942 22:57:03.563592 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass
10944 22:57:03.575022 /lava-10597683/1/../bin/lava-test-case
10945 22:57:03.581385 <8>[ 17.789627] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass>
10946 22:57:03.581776 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass
10948 22:57:03.590834 /lava-10597683/1/../bin/lava-test-case
10949 22:57:03.597046 <8>[ 17.805571] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass>
10950 22:57:03.597446 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass
10952 22:57:03.609693 /lava-10597683/1/../bin/lava-test-case
10953 22:57:03.615976 <8>[ 17.824479] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass>
10954 22:57:03.616371 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass
10956 22:57:03.627057 /lava-10597683/1/../bin/lava-test-case
10957 22:57:03.633654 <8>[ 17.842034] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass>
10958 22:57:03.634081 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass
10960 22:57:03.645470 /lava-10597683/1/../bin/lava-test-case
10961 22:57:03.652080 <8>[ 17.859675] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass>
10962 22:57:03.652492 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass
10964 22:57:03.663419 /lava-10597683/1/../bin/lava-test-case
10965 22:57:03.669977 <8>[ 17.878246] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass>
10966 22:57:03.670398 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass
10968 22:57:03.679149 /lava-10597683/1/../bin/lava-test-case
10969 22:57:03.685711 <8>[ 17.893859] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass>
10970 22:57:03.686119 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass
10972 22:57:03.697671 /lava-10597683/1/../bin/lava-test-case
10973 22:57:03.703841 <8>[ 17.912195] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass>
10974 22:57:03.704246 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass
10976 22:57:03.715107 /lava-10597683/1/../bin/lava-test-case
10977 22:57:03.722087 <8>[ 17.930072] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass>
10978 22:57:03.722484 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass
10980 22:57:03.730725 /lava-10597683/1/../bin/lava-test-case
10981 22:57:03.737772 <8>[ 17.945321] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass>
10982 22:57:03.738197 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass
10984 22:57:03.749052 /lava-10597683/1/../bin/lava-test-case
10985 22:57:03.755511 <8>[ 17.963106] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass>
10986 22:57:03.755911 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass
10988 22:57:03.764328 /lava-10597683/1/../bin/lava-test-case
10989 22:57:03.770982 <8>[ 17.978930] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass>
10990 22:57:03.771404 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass
10992 22:57:03.782910 /lava-10597683/1/../bin/lava-test-case
10993 22:57:03.789115 <8>[ 17.997532] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass>
10994 22:57:03.789535 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass
10996 22:57:03.798549 /lava-10597683/1/../bin/lava-test-case
10997 22:57:03.804998 <8>[ 18.013422] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass>
10998 22:57:03.805422 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass
11000 22:57:03.843602 /lava-10597683/1/../bin/lava-test-case
11001 22:57:03.843877 <8>[ 18.031793] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass>
11002 22:57:03.844084 /lava-10597683/1/../bin/lava-test-case
11003 22:57:03.844260 <8>[ 18.047174] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass>
11004 22:57:03.844593 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass
11006 22:57:03.845026 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass
11008 22:57:03.852006 /lava-10597683/1/../bin/lava-test-case
11009 22:57:03.858232 <8>[ 18.066659] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-probed RESULT=pass>
11010 22:57:03.858636 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-probed RESULT=pass
11012 22:57:03.868629 /lava-10597683/1/../bin/lava-test-case
11013 22:57:03.875203 <8>[ 18.082611] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass>
11014 22:57:03.875670 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass
11016 22:57:03.886413 /lava-10597683/1/../bin/lava-test-case
11017 22:57:03.892961 <8>[ 18.101631] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass>
11018 22:57:03.893240 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass
11020 22:57:03.902777 /lava-10597683/1/../bin/lava-test-case
11021 22:57:03.909526 <8>[ 18.117100] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass>
11022 22:57:03.910251 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass
11024 22:57:03.921825 /lava-10597683/1/../bin/lava-test-case
11025 22:57:03.928306 <8>[ 18.135694] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-probed RESULT=pass>
11026 22:57:03.929037 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-probed RESULT=pass
11028 22:57:03.936696 /lava-10597683/1/../bin/lava-test-case
11029 22:57:03.943817 <8>[ 18.150781] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass>
11030 22:57:03.944559 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass
11032 22:57:03.955068 /lava-10597683/1/../bin/lava-test-case
11033 22:57:03.961764 <8>[ 18.169277] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass>
11034 22:57:03.962550 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass
11036 22:57:03.973367 /lava-10597683/1/../bin/lava-test-case
11037 22:57:03.979808 <8>[ 18.187582] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass>
11038 22:57:03.980481 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass
11040 22:57:04.990801 /lava-10597683/1/../bin/lava-test-case
11041 22:57:04.997261 <8>[ 19.206178] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=fail>
11042 22:57:04.998042 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=fail
11044 22:57:06.010845 /lava-10597683/1/../bin/lava-test-case
11045 22:57:06.017409 <8>[ 20.225901] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=blocked>
11046 22:57:06.017688 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=blocked
11047 22:57:06.017778 Bad test result: blocked
11048 22:57:06.026175 /lava-10597683/1/../bin/lava-test-case
11049 22:57:06.033177 <8>[ 20.241370] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass>
11050 22:57:06.033428 Received signal: <TESTCASE> TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass
11052 22:57:06.044333 /lava-10597683/1/../bin/lava-test-case
11053 22:57:06.051175 <8>[ 20.259486] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass>
11054 22:57:06.051424 Received signal: <TESTCASE> TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass
11056 22:57:06.061871 /lava-10597683/1/../bin/lava-test-case
11057 22:57:06.068612 <8>[ 20.277163] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass>
11058 22:57:06.068861 Received signal: <TESTCASE> TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass
11060 22:57:06.079546 /lava-10597683/1/../bin/lava-test-case
11061 22:57:06.086044 <8>[ 20.294871] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass>
11062 22:57:06.086295 Received signal: <TESTCASE> TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass
11064 22:57:06.097250 /lava-10597683/1/../bin/lava-test-case
11065 22:57:06.103951 <8>[ 20.312244] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass>
11066 22:57:06.104201 Received signal: <TESTCASE> TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass
11068 22:57:06.114289 /lava-10597683/1/../bin/lava-test-case
11069 22:57:06.120754 <8>[ 20.329624] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass>
11070 22:57:06.121003 Received signal: <TESTCASE> TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass
11072 22:57:06.130168 /lava-10597683/1/../bin/lava-test-case
11073 22:57:06.137002 <8>[ 20.345209] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-driver-present RESULT=pass>
11074 22:57:06.137256 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-driver-present RESULT=pass
11076 22:57:06.148338 /lava-10597683/1/../bin/lava-test-case
11077 22:57:06.154439 <8>[ 20.362975] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi1-probed RESULT=pass>
11078 22:57:06.154700 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi1-probed RESULT=pass
11080 22:57:06.165167 /lava-10597683/1/../bin/lava-test-case
11081 22:57:06.171920 <8>[ 20.380713] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi5-probed RESULT=pass>
11082 22:57:06.172172 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi5-probed RESULT=pass
11084 22:57:06.180781 /lava-10597683/1/../bin/lava-test-case
11085 22:57:06.187688 <8>[ 20.395937] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass>
11086 22:57:06.187939 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass
11088 22:57:06.198720 /lava-10597683/1/../bin/lava-test-case
11089 22:57:06.205332 <8>[ 20.413938] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-probed RESULT=pass>
11090 22:57:06.205584 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-probed RESULT=pass
11092 22:57:06.214536 /lava-10597683/1/../bin/lava-test-case
11093 22:57:06.221256 <8>[ 20.429565] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass>
11094 22:57:06.221510 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass
11096 22:57:06.233056 /lava-10597683/1/../bin/lava-test-case
11097 22:57:06.239683 <8>[ 20.448575] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-probed RESULT=pass>
11098 22:57:06.239934 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-probed RESULT=pass
11100 22:57:06.249674 /lava-10597683/1/../bin/lava-test-case
11101 22:57:06.256217 <8>[ 20.464273] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass>
11102 22:57:06.256466 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass
11104 22:57:06.267856 /lava-10597683/1/../bin/lava-test-case
11105 22:57:06.274112 <8>[ 20.482334] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass>
11106 22:57:06.274363 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass
11108 22:57:06.285994 /lava-10597683/1/../bin/lava-test-case
11109 22:57:06.292612 <8>[ 20.501090] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass>
11110 22:57:06.292867 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass
11112 22:57:06.303130 /lava-10597683/1/../bin/lava-test-case
11113 22:57:06.309714 <8>[ 20.518633] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass>
11114 22:57:06.309956 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass
11116 22:57:06.321344 /lava-10597683/1/../bin/lava-test-case
11117 22:57:06.327357 <8>[ 20.536536] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass>
11118 22:57:06.327619 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass
11120 22:57:06.339659 /lava-10597683/1/../bin/lava-test-case
11121 22:57:06.345687 <8>[ 20.554260] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass>
11122 22:57:06.345937 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass
11124 22:57:06.356636 /lava-10597683/1/../bin/lava-test-case
11125 22:57:06.363443 <8>[ 20.572018] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass>
11126 22:57:06.363694 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass
11128 22:57:06.374032 /lava-10597683/1/../bin/lava-test-case
11129 22:57:06.381027 <8>[ 20.589442] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass>
11130 22:57:06.381277 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass
11132 22:57:06.392056 /lava-10597683/1/../bin/lava-test-case
11133 22:57:06.399078 <8>[ 20.607267] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass>
11134 22:57:06.399333 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass
11136 22:57:06.409793 /lava-10597683/1/../bin/lava-test-case
11137 22:57:06.416499 <8>[ 20.624735] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass>
11138 22:57:06.416752 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass
11140 22:57:06.427573 /lava-10597683/1/../bin/lava-test-case
11141 22:57:06.434077 <8>[ 20.643021] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass>
11142 22:57:06.434329 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass
11144 22:57:06.445445 /lava-10597683/1/../bin/lava-test-case
11145 22:57:06.452368 <8>[ 20.660663] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass>
11146 22:57:06.452620 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass
11148 22:57:06.463599 /lava-10597683/1/../bin/lava-test-case
11149 22:57:06.470276 <8>[ 20.678654] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass>
11150 22:57:06.470528 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass
11152 22:57:06.481607 /lava-10597683/1/../bin/lava-test-case
11153 22:57:06.488398 <8>[ 20.696260] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass>
11154 22:57:06.488653 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass
11156 22:57:06.498936 /lava-10597683/1/../bin/lava-test-case
11157 22:57:06.505260 <8>[ 20.713385] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass>
11158 22:57:06.505511 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass
11160 22:57:06.516282 /lava-10597683/1/../bin/lava-test-case
11161 22:57:06.522889 <8>[ 20.731488] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass>
11162 22:57:06.523175 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass
11164 22:57:06.531804 /lava-10597683/1/../bin/lava-test-case
11165 22:57:06.538591 <8>[ 20.746800] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass>
11166 22:57:06.538849 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass
11168 22:57:06.550361 /lava-10597683/1/../bin/lava-test-case
11169 22:57:06.556939 <8>[ 20.765510] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-probed RESULT=pass>
11170 22:57:06.557192 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-probed RESULT=pass
11172 22:57:06.565611 /lava-10597683/1/../bin/lava-test-case
11173 22:57:06.572423 <8>[ 20.780831] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass>
11174 22:57:06.572675 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass
11176 22:57:06.583617 /lava-10597683/1/../bin/lava-test-case
11177 22:57:06.590391 <8>[ 20.799174] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-probed RESULT=pass>
11178 22:57:06.590644 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-probed RESULT=pass
11180 22:57:06.599980 /lava-10597683/1/../bin/lava-test-case
11181 22:57:06.605805 <8>[ 20.814526] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass>
11182 22:57:06.606057 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass
11184 22:57:06.618034 /lava-10597683/1/../bin/lava-test-case
11185 22:57:06.624428 <8>[ 20.833203] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass>
11186 22:57:06.624691 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass
11188 22:57:06.634391 /lava-10597683/1/../bin/lava-test-case
11189 22:57:06.640621 <8>[ 20.849393] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass>
11190 22:57:06.640873 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass
11192 22:57:06.652636 /lava-10597683/1/../bin/lava-test-case
11193 22:57:06.659971 <8>[ 20.868204] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-probed RESULT=pass>
11194 22:57:06.660224 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-probed RESULT=pass
11196 22:57:06.668928 /lava-10597683/1/../bin/lava-test-case
11197 22:57:06.675103 <8>[ 20.883624] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass>
11198 22:57:06.675364 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass
11200 22:57:06.686390 /lava-10597683/1/../bin/lava-test-case
11201 22:57:06.693261 <8>[ 20.901769] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass>
11202 22:57:06.693514 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass
11204 22:57:06.701983 /lava-10597683/1/../bin/lava-test-case
11205 22:57:06.708812 <8>[ 20.917188] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass>
11206 22:57:06.709062 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass
11208 22:57:06.721126 /lava-10597683/1/../bin/lava-test-case
11209 22:57:06.727104 <8>[ 20.935861] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass>
11210 22:57:06.727394 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass
11212 22:57:06.739002 /lava-10597683/1/../bin/lava-test-case
11213 22:57:06.746096 <8>[ 20.953981] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass>
11214 22:57:06.746469 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass
11216 22:57:06.755432 /lava-10597683/1/../bin/lava-test-case
11217 22:57:06.761730 <8>[ 20.969865] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass>
11218 22:57:06.762053 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass
11220 22:57:06.773461 /lava-10597683/1/../bin/lava-test-case
11221 22:57:06.780513 <8>[ 20.989079] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass>
11222 22:57:06.780966 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass
11224 22:57:06.790102 /lava-10597683/1/../bin/lava-test-case
11225 22:57:06.796944 <8>[ 21.004789] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-driver-present RESULT=pass>
11226 22:57:06.797703 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-driver-present RESULT=pass
11228 22:57:06.808278 /lava-10597683/1/../bin/lava-test-case
11229 22:57:06.814802 <8>[ 21.022939] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-probed RESULT=pass>
11230 22:57:06.815614 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-probed RESULT=pass
11232 22:57:06.823473 /lava-10597683/1/../bin/lava-test-case
11233 22:57:06.829979 <8>[ 21.037882] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-driver-present RESULT=pass>
11234 22:57:06.830678 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-driver-present RESULT=pass
11236 22:57:07.843930 /lava-10597683/1/../bin/lava-test-case
11237 22:57:07.850641 <8>[ 22.059533] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-probed RESULT=fail>
11238 22:57:07.850921 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-probed RESULT=fail
11240 22:57:07.859056 /lava-10597683/1/../bin/lava-test-case
11241 22:57:07.865786 <8>[ 22.075087] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-driver-present RESULT=pass>
11242 22:57:07.866037 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-driver-present RESULT=pass
11244 22:57:08.879777 /lava-10597683/1/../bin/lava-test-case
11245 22:57:08.886664 <8>[ 23.095497] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-probed RESULT=fail>
11246 22:57:08.886978 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-probed RESULT=fail
11248 22:57:08.895678 /lava-10597683/1/../bin/lava-test-case
11249 22:57:08.902152 <8>[ 23.111542] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass>
11250 22:57:08.902455 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass
11252 22:57:09.916627 /lava-10597683/1/../bin/lava-test-case
11253 22:57:09.923275 <8>[ 24.132552] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail>
11254 22:57:09.923609 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail
11256 22:57:09.933080 /lava-10597683/1/../bin/lava-test-case
11257 22:57:09.939321 <8>[ 24.148904] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass>
11258 22:57:09.939630 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass
11260 22:57:10.953184 /lava-10597683/1/../bin/lava-test-case
11261 22:57:10.959859 <8>[ 25.169105] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-probed RESULT=fail>
11262 22:57:10.960185 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-probed RESULT=fail
11264 22:57:10.968445 /lava-10597683/1/../bin/lava-test-case
11265 22:57:10.974980 <8>[ 25.184473] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-driver-present RESULT=pass>
11266 22:57:10.975316 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-driver-present RESULT=pass
11268 22:57:11.989203 /lava-10597683/1/../bin/lava-test-case
11269 22:57:11.995254 <8>[ 26.204976] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-3-probed RESULT=fail>
11270 22:57:11.995599 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-3-probed RESULT=fail
11272 22:57:12.004670 /lava-10597683/1/../bin/lava-test-case
11273 22:57:12.010830 <8>[ 26.220491] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass>
11274 22:57:12.011180 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass
11276 22:57:13.025671 /lava-10597683/1/../bin/lava-test-case
11277 22:57:13.031963 <8>[ 27.241576] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail>
11278 22:57:13.032386 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail
11280 22:57:13.041334 /lava-10597683/1/../bin/lava-test-case
11281 22:57:13.048516 <8>[ 27.257959] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass>
11282 22:57:13.048914 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass
11284 22:57:14.062291 /lava-10597683/1/../bin/lava-test-case
11285 22:57:14.068440 <8>[ 28.278278] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-probed RESULT=fail>
11286 22:57:14.068808 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-probed RESULT=fail
11288 22:57:14.078193 /lava-10597683/1/../bin/lava-test-case
11289 22:57:14.084208 <8>[ 28.294342] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-edp-driver-present RESULT=pass>
11290 22:57:14.084587 Received signal: <TESTCASE> TEST_CASE_ID=panel-edp-driver-present RESULT=pass
11292 22:57:14.093981 /lava-10597683/1/../bin/lava-test-case
11293 22:57:14.100872 <8>[ 28.310378] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass>
11294 22:57:14.101248 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass
11296 22:57:15.115067 /lava-10597683/1/../bin/lava-test-case
11297 22:57:15.121675 <8>[ 29.332259] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail>
11298 22:57:15.122048 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail
11300 22:57:15.132305 /lava-10597683/1/../bin/lava-test-case
11301 22:57:15.139155 <8>[ 29.348624] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass>
11302 22:57:15.139547 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass
11304 22:57:15.151087 /lava-10597683/1/../bin/lava-test-case
11305 22:57:15.157723 <8>[ 29.366826] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-probed RESULT=pass>
11306 22:57:15.158081 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-probed RESULT=pass
11308 22:57:15.166345 /lava-10597683/1/../bin/lava-test-case
11309 22:57:15.173200 <8>[ 29.382644] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass>
11310 22:57:15.173572 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass
11312 22:57:15.185493 /lava-10597683/1/../bin/lava-test-case
11313 22:57:15.191826 <8>[ 29.401170] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass>
11314 22:57:15.192158 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass
11316 22:57:15.203035 /lava-10597683/1/../bin/lava-test-case
11317 22:57:15.209683 <8>[ 29.419274] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass>
11318 22:57:15.210063 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass
11320 22:57:15.221059 /lava-10597683/1/../bin/lava-test-case
11321 22:57:15.227821 <8>[ 29.437337] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass>
11322 22:57:15.228199 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass
11324 22:57:15.237842 /lava-10597683/1/../bin/lava-test-case
11325 22:57:15.243697 <8>[ 29.453277] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass>
11326 22:57:15.244083 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass
11328 22:57:15.255890 /lava-10597683/1/../bin/lava-test-case
11329 22:57:15.262361 <8>[ 29.471996] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass>
11330 22:57:15.262724 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass
11332 22:57:15.273720 /lava-10597683/1/../bin/lava-test-case
11333 22:57:15.280485 <8>[ 29.490274] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass>
11334 22:57:15.280813 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass
11336 22:57:15.290462 /lava-10597683/1/../bin/lava-test-case
11337 22:57:15.296274 <8>[ 29.506401] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass>
11338 22:57:15.296671 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass
11340 22:57:15.308701 /lava-10597683/1/../bin/lava-test-case
11341 22:57:15.315444 <8>[ 29.525415] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass>
11342 22:57:15.315806 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass
11344 22:57:15.325610 /lava-10597683/1/../bin/lava-test-case
11345 22:57:15.331673 <8>[ 29.541329] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass>
11346 22:57:15.332050 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass
11348 22:57:15.343726 /lava-10597683/1/../bin/lava-test-case
11349 22:57:15.350693 <8>[ 29.560343] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass>
11350 22:57:15.351026 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass
11352 22:57:15.360649 /lava-10597683/1/../bin/lava-test-case
11353 22:57:15.367164 <8>[ 29.576621] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass>
11354 22:57:15.367487 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass
11356 22:57:15.379241 /lava-10597683/1/../bin/lava-test-case
11357 22:57:15.385434 <8>[ 29.595627] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass>
11358 22:57:15.385798 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass
11360 22:57:15.395888 /lava-10597683/1/../bin/lava-test-case
11361 22:57:15.402268 <8>[ 29.611794] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass>
11362 22:57:15.402601 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass
11364 22:57:15.414744 /lava-10597683/1/../bin/lava-test-case
11365 22:57:15.420889 <8>[ 29.630739] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass>
11366 22:57:15.421211 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass
11368 22:57:15.430380 /lava-10597683/1/../bin/lava-test-case
11369 22:57:15.436970 <8>[ 29.647078] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass>
11370 22:57:15.437303 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass
11372 22:57:15.449034 /lava-10597683/1/../bin/lava-test-case
11373 22:57:15.455719 <8>[ 29.665208] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-probed RESULT=pass>
11374 22:57:15.456041 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-probed RESULT=pass
11376 22:57:15.464432 /lava-10597683/1/../bin/lava-test-case
11377 22:57:15.471042 <8>[ 29.680623] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass>
11378 22:57:15.471367 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass
11380 22:57:16.485053 /lava-10597683/1/../bin/lava-test-case
11381 22:57:16.491778 <8>[ 30.702077] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-probed RESULT=fail>
11382 22:57:16.492224 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-probed RESULT=fail
11384 22:57:17.505503 /lava-10597683/1/../bin/lava-test-case
11385 22:57:17.511675 <8>[ 31.722280] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-7-probed RESULT=fail>
11386 22:57:17.511996 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-7-probed RESULT=fail
11388 22:57:17.521061 /lava-10597683/1/../bin/lava-test-case
11389 22:57:17.527781 <8>[ 31.737979] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-driver-present RESULT=pass>
11390 22:57:17.528188 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-driver-present RESULT=pass
11392 22:57:17.539654 /lava-10597683/1/../bin/lava-test-case
11393 22:57:17.546246 <8>[ 31.755800] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-probed RESULT=pass>
11394 22:57:17.546556 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-probed RESULT=pass
11396 22:57:17.555493 /lava-10597683/1/../bin/lava-test-case
11397 22:57:17.561546 <8>[ 31.771621] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass>
11398 22:57:17.561854 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass
11400 22:57:17.573414 /lava-10597683/1/../bin/lava-test-case
11401 22:57:17.579964 <8>[ 31.789705] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass>
11402 22:57:17.580267 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass
11404 22:57:17.589296 /lava-10597683/1/../bin/lava-test-case
11405 22:57:17.595475 <8>[ 31.805655] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-driver-present RESULT=pass>
11406 22:57:17.595828 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-driver-present RESULT=pass
11408 22:57:17.607180 /lava-10597683/1/../bin/lava-test-case
11409 22:57:17.614033 <8>[ 31.822918] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-probed RESULT=pass>
11410 22:57:17.614337 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-probed RESULT=pass
11412 22:57:17.622101 /lava-10597683/1/../bin/lava-test-case
11413 22:57:17.628414 <8>[ 31.838160] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass>
11414 22:57:17.628698 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass
11416 22:57:17.639962 /lava-10597683/1/../bin/lava-test-case
11417 22:57:17.646369 <8>[ 31.856209] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass>
11418 22:57:17.646713 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass
11420 22:57:17.654949 /lava-10597683/1/../bin/lava-test-case
11421 22:57:17.661551 <8>[ 31.871783] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass>
11422 22:57:17.661828 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass
11424 22:57:17.673800 /lava-10597683/1/../bin/lava-test-case
11425 22:57:17.680348 <8>[ 31.890395] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-probed RESULT=pass>
11426 22:57:17.680676 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-probed RESULT=pass
11428 22:57:17.689313 /lava-10597683/1/../bin/lava-test-case
11429 22:57:17.695899 <8>[ 31.905506] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass>
11430 22:57:17.696268 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass
11432 22:57:17.707389 /lava-10597683/1/../bin/lava-test-case
11433 22:57:17.713901 <8>[ 31.924490] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass>
11434 22:57:17.714225 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass
11436 22:57:17.723543 /lava-10597683/1/../bin/lava-test-case
11437 22:57:17.730112 <8>[ 31.939687] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass>
11438 22:57:17.730375 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass
11440 22:57:17.741640 /lava-10597683/1/../bin/lava-test-case
11441 22:57:17.747974 <8>[ 31.957460] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-probed RESULT=pass>
11442 22:57:17.748288 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-probed RESULT=pass
11444 22:57:17.756734 /lava-10597683/1/../bin/lava-test-case
11445 22:57:17.763255 <8>[ 31.973457] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass>
11446 22:57:17.763587 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass
11448 22:57:17.774720 /lava-10597683/1/../bin/lava-test-case
11449 22:57:17.781407 <8>[ 31.991159] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-probed RESULT=pass>
11450 22:57:17.781765 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-probed RESULT=pass
11452 22:57:17.790096 /lava-10597683/1/../bin/lava-test-case
11453 22:57:17.797066 <8>[ 32.006144] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-driver-present RESULT=pass>
11454 22:57:17.797351 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-driver-present RESULT=pass
11456 22:57:17.807631 /lava-10597683/1/../bin/lava-test-case
11457 22:57:17.814576 <8>[ 32.023780] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-probed RESULT=pass>
11458 22:57:17.815386 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-probed RESULT=pass
11460 22:57:17.822730 /lava-10597683/1/../bin/lava-test-case
11461 22:57:17.829209 <8>[ 32.038820] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass>
11462 22:57:17.829789 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass
11464 22:57:17.841454 /lava-10597683/1/../bin/lava-test-case
11465 22:57:17.848263 <8>[ 32.058089] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass>
11466 22:57:17.848596 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass
11468 22:57:18.859121 /lava-10597683/1/../bin/lava-test-case
11469 22:57:18.865902 <8>[ 33.077119] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail>
11470 22:57:18.866196 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail
11472 22:57:19.880061 /lava-10597683/1/../bin/lava-test-case
11473 22:57:19.886347 <8>[ 34.097484] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked>
11474 22:57:19.886713 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked
11475 22:57:19.886845 Bad test result: blocked
11476 22:57:19.897104 /lava-10597683/1/../bin/lava-test-case
11477 22:57:19.903611 <8>[ 34.113576] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-driver-present RESULT=pass>
11478 22:57:19.903963 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-driver-present RESULT=pass
11480 22:57:20.917414 /lava-10597683/1/../bin/lava-test-case
11481 22:57:20.924398 <8>[ 35.135289] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-probed RESULT=fail>
11482 22:57:20.924724 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-probed RESULT=fail
11484 22:57:20.934453 /lava-10597683/1/../bin/lava-test-case
11485 22:57:20.941277 <8>[ 35.151353] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo-driver-present RESULT=pass>
11486 22:57:20.941548 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo-driver-present RESULT=pass
11488 22:57:20.952801 /lava-10597683/1/../bin/lava-test-case
11489 22:57:20.959556 <8>[ 35.169546] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo0-probed RESULT=pass>
11490 22:57:20.959865 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo0-probed RESULT=pass
11492 22:57:20.970290 /lava-10597683/1/../bin/lava-test-case
11493 22:57:20.976982 <8>[ 35.187344] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo1-probed RESULT=pass>
11494 22:57:20.977260 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo1-probed RESULT=pass
11496 22:57:20.986236 /lava-10597683/1/../bin/lava-test-case
11497 22:57:20.992843 <8>[ 35.202703] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass>
11498 22:57:20.993209 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass
11500 22:57:21.004410 /lava-10597683/1/../bin/lava-test-case
11501 22:57:21.010889 <8>[ 35.221456] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-probed RESULT=pass>
11502 22:57:21.011151 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-probed RESULT=pass
11504 22:57:21.020752 /lava-10597683/1/../bin/lava-test-case
11505 22:57:21.027715 <8>[ 35.237203] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-driver-present RESULT=pass>
11506 22:57:21.028025 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-driver-present RESULT=pass
11508 22:57:22.040887 /lava-10597683/1/../bin/lava-test-case
11509 22:57:22.047381 <8>[ 36.258918] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-probed RESULT=fail>
11510 22:57:22.047774 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-probed RESULT=fail
11512 22:57:22.058249 /lava-10597683/1/../bin/lava-test-case
11513 22:57:22.064984 <8>[ 36.274914] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-driver-present RESULT=pass>
11514 22:57:22.065258 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-driver-present RESULT=pass
11516 22:57:23.078366 /lava-10597683/1/../bin/lava-test-case
11517 22:57:23.084538 <8>[ 37.295435] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-probed RESULT=fail>
11518 22:57:23.084902 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-probed RESULT=fail
11520 22:57:23.093763 /lava-10597683/1/../bin/lava-test-case
11521 22:57:23.100626 <8>[ 37.311343] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-driver-present RESULT=pass>
11522 22:57:23.100927 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-driver-present RESULT=pass
11524 22:57:24.113761 /lava-10597683/1/../bin/lava-test-case
11525 22:57:24.120575 <8>[ 38.331296] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-probed RESULT=fail>
11526 22:57:24.120940 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-probed RESULT=fail
11528 22:57:24.129881 /lava-10597683/1/../bin/lava-test-case
11529 22:57:24.136391 <8>[ 38.347039] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass>
11530 22:57:24.136738 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass
11532 22:57:25.149772 /lava-10597683/1/../bin/lava-test-case
11533 22:57:25.156430 <8>[ 39.367471] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail>
11534 22:57:25.156845 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail
11536 22:57:25.166354 /lava-10597683/1/../bin/lava-test-case
11537 22:57:25.172865 <8>[ 39.383119] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb-driver-present RESULT=pass>
11538 22:57:25.173149 Received signal: <TESTCASE> TEST_CASE_ID=btusb-driver-present RESULT=pass
11540 22:57:25.183838 /lava-10597683/1/../bin/lava-test-case
11541 22:57:25.190102 <8>[ 39.400725] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb0-probed RESULT=pass>
11542 22:57:25.190506 Received signal: <TESTCASE> TEST_CASE_ID=btusb0-probed RESULT=pass
11544 22:57:25.200690 /lava-10597683/1/../bin/lava-test-case
11545 22:57:25.207003 <8>[ 39.418078] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb1-probed RESULT=pass>
11546 22:57:25.207286 Received signal: <TESTCASE> TEST_CASE_ID=btusb1-probed RESULT=pass
11548 22:57:25.216172 /lava-10597683/1/../bin/lava-test-case
11549 22:57:25.222990 <8>[ 39.433571] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass>
11550 22:57:25.223370 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass
11552 22:57:25.234688 /lava-10597683/1/../bin/lava-test-case
11553 22:57:25.241045 <8>[ 39.452034] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-probed RESULT=pass>
11554 22:57:25.241425 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-probed RESULT=pass
11556 22:57:25.249982 /lava-10597683/1/../bin/lava-test-case
11557 22:57:25.256715 <8>[ 39.467534] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass>
11558 22:57:25.257112 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass
11560 22:57:25.269601 /lava-10597683/1/../bin/lava-test-case
11561 22:57:25.275477 <8>[ 39.486201] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-probed RESULT=pass>
11562 22:57:25.275843 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-probed RESULT=pass
11564 22:57:25.285404 /lava-10597683/1/../bin/lava-test-case
11565 22:57:25.292058 <8>[ 39.502298] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass>
11566 22:57:25.292425 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass
11568 22:57:26.306124 /lava-10597683/1/../bin/lava-test-case
11569 22:57:26.313187 <8>[ 40.524596] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=fail>
11570 22:57:26.313555 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=fail
11572 22:57:26.317377 + set +x
11573 22:57:26.321188 Received signal: <ENDRUN> 1_bootrr 10597683_1.5.2.3.5
11574 22:57:26.321338 Ending use of test pattern.
11575 22:57:26.321461 Ending test lava.1_bootrr (10597683_1.5.2.3.5), duration 23.27
11577 22:57:26.324046 <8>[ 40.534585] <LAVA_SIGNAL_ENDRUN 1_bootrr 10597683_1.5.2.3.5>
11578 22:57:26.324202 <LAVA_TEST_RUNNER EXIT>
11579 22:57:26.324508 ok: lava_test_shell seems to have completed
11580 22:57:26.326437 all-cpus-are-online: pass
anx7625-3-probed: fail
anx7625-7-probed: fail
anx7625-driver-present: pass
btusb-driver-present: pass
btusb0-probed: pass
btusb1-probed: pass
clk-mt8192-apmixedsys-probed: pass
clk-mt8192-aud-driver-present: pass
clk-mt8192-aud-probed: pass
clk-mt8192-cam-driver-present: pass
clk-mt8192-cam-probed: pass
clk-mt8192-cam_rawa-probed: pass
clk-mt8192-cam_rawb-probed: pass
clk-mt8192-cam_rawc-probed: pass
clk-mt8192-driver-present: pass
clk-mt8192-img-driver-present: pass
clk-mt8192-img-probed: pass
clk-mt8192-img2-probed: pass
clk-mt8192-imp_iic_wrap-driver-present: pass
clk-mt8192-imp_iic_wrap_e-probed: pass
clk-mt8192-imp_iic_wrap_n-probed: pass
clk-mt8192-imp_iic_wrap_s-probed: pass
clk-mt8192-imp_iic_wrap_ws-probed: pass
clk-mt8192-infracfg-probed: pass
clk-mt8192-ipe-driver-present: pass
clk-mt8192-ipe-probed: pass
clk-mt8192-mdp-driver-present: pass
clk-mt8192-mdp-probed: pass
clk-mt8192-mfg-driver-present: pass
clk-mt8192-mfg-probed: pass
clk-mt8192-mm-driver-present: pass
clk-mt8192-mm-probed: pass
clk-mt8192-msdc-driver-present: pass
clk-mt8192-msdc-probed: pass
clk-mt8192-pericfg-probed: pass
clk-mt8192-topckgen-probed: pass
clk-mt8192-vdec-driver-present: pass
clk-mt8192-vdec-probed: pass
clk-mt8192-vdec_soc-probed: pass
clk-mt8192-venc-driver-present: pass
clk-mt8192-venc-probed: pass
cros-ec-i2c-tunnel-driver-present: pass
cros-ec-i2c-tunnel-probed: pass
cros-ec-keyb-driver-present: pass
cros-ec-keyb-probed: pass
cros-ec-pwm-driver-present: pass
cros-ec-pwm-probed: pass
cros-ec-regulator-driver-present: pass
cros-ec-regulator0-probed: pass
cros-ec-regulator1-probed: pass
cros-ec-rpmsg-driver-present: fail
cros-ec-spi-driver-present: pass
cros-ec-spi-probed: pass
cros-ec-typec-driver-present: pass
cros-ec-typec-probed: pass
deferred-probe-empty: pass
dmic-codec-driver-present: pass
dmic-codec-probed: fail
elan_i2c-driver-present: pass
elan_i2c-probed: fail
elants_i2c-driver-present: pass
elants_i2c-probed: fail
i2c-mt65xx-driver-present: pass
i2c0-mt65xx-probed: pass
i2c1-mt65xx-probed: pass
i2c2-mt65xx-probed: pass
i2c3-mt65xx-probed: pass
i2c7-mt65xx-probed: pass
leds_pwm-driver-present: pass
leds_pwm-probed: pass
mediatek,efuse-driver-present: pass
mediatek,efuse-probed: pass
mediatek-disp-aal-driver-present: pass
mediatek-disp-aal-probed: pass
mediatek-disp-ccorr-driver-present: pass
mediatek-disp-ccorr-probed: pass
mediatek-disp-color-driver-present: pass
mediatek-disp-color-probed: pass
mediatek-disp-gamma-driver-present: pass
mediatek-disp-gamma-probed: pass
mediatek-disp-ovl-driver-present: pass
mediatek-disp-ovl0-probed: pass
mediatek-disp-ovl2l0-probed: pass
mediatek-disp-ovl2l2-probed: pass
mediatek-disp-pwm-driver-present: pass
mediatek-disp-pwm-probed: fail
mediatek-disp-rdma-driver-present: pass
mediatek-disp-rdma0-probed: pass
mediatek-disp-rdma4-probed: pass
mediatek-dpi-driver-present: pass
mediatek-dpi-probed: fail
mediatek-drm-driver-present: pass
mediatek-drm-probed: pass
mediatek-mipi-tx-driver-present: pass
mediatek-mipi-tx-probed: fail
mediatek-mutex-driver-present: pass
mediatek-mutex-probed: pass
mt-pmic-pwrap-driver-present: pass
mt-pmic-pwrap-probed: pass
mt6315-regulator-driver-present: pass
mt6315-regulator6-probed: pass
mt6315-regulator7-probed: pass
mt6577-uart-driver-present: pass
mt6577-uart-probed: pass
mt7921e-driver-present: pass
mt7921e-probed: pass
mt8192-audio-driver-present: pass
mt8192-audio-probed: pass
mt8192-pinctrl-driver-present: pass
mt8192-pinctrl-probed: pass
mt8192_mt6359-driver-present: pass
mt8192_mt6359-probed: fail
mtk-cpufreq-hw-driver-present: pass
mtk-cpufreq-hw-probed: fail
mtk-dsi-driver-present: pass
mtk-dsi-probed: fail
mtk-iommu-driver-present: pass
mtk-iommu-probed: pass
mtk-mmsys-driver-present: pass
mtk-mmsys-probed: pass
mtk-msdc-driver-present: pass
mtk-msdc-probed: pass
mtk-pcie-gen3-driver-present: pass
mtk-pcie-gen3-probed: pass
mtk-power-controller-driver-present: pass
mtk-power-controller-probed: pass
mtk-scp-driver-present: pass
mtk-scp-probed: pass
mtk-smi-common-driver-present: pass
mtk-smi-common-probed: pass
mtk-smi-larb-driver-present: pass
mtk-smi-larb0-probed: pass
mtk-smi-larb1-probed: pass
mtk-smi-larb11-probed: pass
mtk-smi-larb13-probed: pass
mtk-smi-larb14-probed: pass
mtk-smi-larb16-probed: pass
mtk-smi-larb17-probed: pass
mtk-smi-larb18-probed: pass
mtk-smi-larb19-probed: pass
mtk-smi-larb2-probed: pass
mtk-smi-larb20-probed: pass
mtk-smi-larb4-probed: pass
mtk-smi-larb5-probed: pass
mtk-smi-larb7-probed: pass
mtk-smi-larb9-probed: pass
mtk-spi-driver-present: pass
mtk-spi-nor-driver-present: pass
mtk-spi-nor-probed: pass
mtk-spi1-probed: pass
mtk-spi5-probed: pass
mtk-tphy-driver-present: pass
mtk-tphy-probed: pass
mtk-vcodec-dec-driver-present: fail
mtk-vcodec-enc-driver-present: pass
mtk-vcodec-enc-probed: pass
mtk-wdt-driver-present: pass
mtk-wdt-probed: pass
panel-edp-driver-present: pass
panel-simple-dp-aux-driver-present: pass
panel-simple-dp-aux-probed: fail
panfrost-driver-present: pass
panfrost-probed: fail
pwm-backlight-driver-present: pass
pwm-backlight-probed: fail
rt1015p-driver-present: pass
rt1015p-probed: fail
rt5682-driver-present: pass
rt5682-probed: fail
sbs-battery-driver-present: pass
sbs-battery-probed: pass
spmi-mtk-driver-present: pass
spmi-mtk-probed: pass
tpm-chip-is-online: pass
tpm_tis_spi-driver-present: pass
tpm_tis_spi-probed: pass
uvcvideo-driver-present: pass
uvcvideo0-probed: pass
uvcvideo1-probed: pass
xhci-mtk-driver-present: pass
xhci-mtk-probed: pass
11581 22:57:26.326705 end: 4.1 lava-test-shell (duration 00:00:24) [common]
11582 22:57:26.326866 end: 4 lava-test-retry (duration 00:00:24) [common]
11583 22:57:26.327030 start: 5 finalize (timeout 00:07:58) [common]
11584 22:57:26.327254 start: 5.1 power-off (timeout 00:00:30) [common]
11585 22:57:26.327579 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=off'
11586 22:57:26.420438 >> Command sent successfully.
11587 22:57:26.423030 Returned 0 in 0 seconds
11588 22:57:26.523450 end: 5.1 power-off (duration 00:00:00) [common]
11590 22:57:26.523792 start: 5.2 read-feedback (timeout 00:07:58) [common]
11591 22:57:26.524062 Listened to connection for namespace 'common' for up to 1s
11592 22:57:26.524351 Listened to connection for namespace 'common' for up to 1s
11593 22:57:27.524988 Finalising connection for namespace 'common'
11594 22:57:27.525227 Disconnecting from shell: Finalise
11595 22:57:27.525360 / #
11596 22:57:27.625726 end: 5.2 read-feedback (duration 00:00:01) [common]
11597 22:57:27.625906 end: 5 finalize (duration 00:00:01) [common]
11598 22:57:27.626035 Cleaning after the job
11599 22:57:27.626140 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597683/tftp-deploy-bbro1pbo/ramdisk
11600 22:57:27.628853 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597683/tftp-deploy-bbro1pbo/kernel
11601 22:57:27.635625 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597683/tftp-deploy-bbro1pbo/dtb
11602 22:57:27.635840 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597683/tftp-deploy-bbro1pbo/modules
11603 22:57:27.642021 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10597683
11604 22:57:27.681581 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10597683
11605 22:57:27.681748 Job finished correctly