Boot log: mt8192-asurada-spherion-r0
- Errors: 2
- Kernel Errors: 38
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 30
1 22:54:45.866731 lava-dispatcher, installed at version: 2023.05.1
2 22:54:45.866934 start: 0 validate
3 22:54:45.867065 Start time: 2023-06-05 22:54:45.867058+00:00 (UTC)
4 22:54:45.867184 Using caching service: 'http://localhost/cache/?uri=%s'
5 22:54:45.867309 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230527.0%2Farm64%2Finitrd.cpio.gz exists
6 22:54:46.152598 Using caching service: 'http://localhost/cache/?uri=%s'
7 22:54:46.153488 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1314-g1ab0ac1d7e2e3%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 22:54:54.442568 Using caching service: 'http://localhost/cache/?uri=%s'
9 22:54:54.443505 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1314-g1ab0ac1d7e2e3%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 22:54:54.736968 Using caching service: 'http://localhost/cache/?uri=%s'
11 22:54:54.737547 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230527.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 22:54:55.307353 Using caching service: 'http://localhost/cache/?uri=%s'
13 22:54:55.308097 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1314-g1ab0ac1d7e2e3%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 22:54:58.818626 validate duration: 12.95
16 22:54:58.818879 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 22:54:58.818980 start: 1.1 download-retry (timeout 00:10:00) [common]
18 22:54:58.819063 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 22:54:58.819182 Not decompressing ramdisk as can be used compressed.
20 22:54:58.819265 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230527.0/arm64/initrd.cpio.gz
21 22:54:58.819327 saving as /var/lib/lava/dispatcher/tmp/10597665/tftp-deploy-ltd01qmt/ramdisk/initrd.cpio.gz
22 22:54:58.819386 total size: 4665395 (4MB)
23 22:54:59.109898 progress 0% (0MB)
24 22:54:59.111341 progress 5% (0MB)
25 22:54:59.112617 progress 10% (0MB)
26 22:54:59.113830 progress 15% (0MB)
27 22:54:59.115041 progress 20% (0MB)
28 22:54:59.116364 progress 25% (1MB)
29 22:54:59.117633 progress 30% (1MB)
30 22:54:59.118827 progress 35% (1MB)
31 22:54:59.120191 progress 40% (1MB)
32 22:54:59.121586 progress 45% (2MB)
33 22:54:59.122780 progress 50% (2MB)
34 22:54:59.123974 progress 55% (2MB)
35 22:54:59.125242 progress 60% (2MB)
36 22:54:59.126447 progress 65% (2MB)
37 22:54:59.127636 progress 70% (3MB)
38 22:54:59.128859 progress 75% (3MB)
39 22:54:59.130168 progress 80% (3MB)
40 22:54:59.131570 progress 85% (3MB)
41 22:54:59.132811 progress 90% (4MB)
42 22:54:59.134044 progress 95% (4MB)
43 22:54:59.135279 progress 100% (4MB)
44 22:54:59.135478 4MB downloaded in 0.32s (14.08MB/s)
45 22:54:59.135625 end: 1.1.1 http-download (duration 00:00:00) [common]
47 22:54:59.135868 end: 1.1 download-retry (duration 00:00:00) [common]
48 22:54:59.135955 start: 1.2 download-retry (timeout 00:10:00) [common]
49 22:54:59.136065 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 22:54:59.136217 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1314-g1ab0ac1d7e2e3/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 22:54:59.136288 saving as /var/lib/lava/dispatcher/tmp/10597665/tftp-deploy-ltd01qmt/kernel/Image
52 22:54:59.136351 total size: 45746688 (43MB)
53 22:54:59.136412 No compression specified
54 22:54:59.137636 progress 0% (0MB)
55 22:54:59.149468 progress 5% (2MB)
56 22:54:59.161203 progress 10% (4MB)
57 22:54:59.172820 progress 15% (6MB)
58 22:54:59.184491 progress 20% (8MB)
59 22:54:59.196124 progress 25% (10MB)
60 22:54:59.207470 progress 30% (13MB)
61 22:54:59.219064 progress 35% (15MB)
62 22:54:59.231073 progress 40% (17MB)
63 22:54:59.243018 progress 45% (19MB)
64 22:54:59.254923 progress 50% (21MB)
65 22:54:59.266514 progress 55% (24MB)
66 22:54:59.278149 progress 60% (26MB)
67 22:54:59.289942 progress 65% (28MB)
68 22:54:59.301494 progress 70% (30MB)
69 22:54:59.313151 progress 75% (32MB)
70 22:54:59.324607 progress 80% (34MB)
71 22:54:59.336279 progress 85% (37MB)
72 22:54:59.348286 progress 90% (39MB)
73 22:54:59.359939 progress 95% (41MB)
74 22:54:59.371551 progress 100% (43MB)
75 22:54:59.371730 43MB downloaded in 0.24s (185.35MB/s)
76 22:54:59.371886 end: 1.2.1 http-download (duration 00:00:00) [common]
78 22:54:59.372172 end: 1.2 download-retry (duration 00:00:00) [common]
79 22:54:59.372260 start: 1.3 download-retry (timeout 00:09:59) [common]
80 22:54:59.372348 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 22:54:59.372483 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1314-g1ab0ac1d7e2e3/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 22:54:59.372556 saving as /var/lib/lava/dispatcher/tmp/10597665/tftp-deploy-ltd01qmt/dtb/mt8192-asurada-spherion-r0.dtb
83 22:54:59.372618 total size: 46924 (0MB)
84 22:54:59.372678 No compression specified
85 22:54:59.373780 progress 69% (0MB)
86 22:54:59.374053 progress 100% (0MB)
87 22:54:59.374205 0MB downloaded in 0.00s (28.24MB/s)
88 22:54:59.374323 end: 1.3.1 http-download (duration 00:00:00) [common]
90 22:54:59.374546 end: 1.3 download-retry (duration 00:00:00) [common]
91 22:54:59.374631 start: 1.4 download-retry (timeout 00:09:59) [common]
92 22:54:59.374714 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 22:54:59.374822 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230527.0/arm64/full.rootfs.tar.xz
94 22:54:59.374889 saving as /var/lib/lava/dispatcher/tmp/10597665/tftp-deploy-ltd01qmt/nfsrootfs/full.rootfs.tar
95 22:54:59.374949 total size: 125267308 (119MB)
96 22:54:59.375009 Using unxz to decompress xz
97 22:54:59.378652 progress 0% (0MB)
98 22:54:59.706790 progress 5% (6MB)
99 22:55:00.042433 progress 10% (11MB)
100 22:55:00.368111 progress 15% (17MB)
101 22:55:00.554967 progress 20% (23MB)
102 22:55:00.740671 progress 25% (29MB)
103 22:55:01.095561 progress 30% (35MB)
104 22:55:01.448208 progress 35% (41MB)
105 22:55:01.832302 progress 40% (47MB)
106 22:55:02.205781 progress 45% (53MB)
107 22:55:02.591694 progress 50% (59MB)
108 22:55:02.939691 progress 55% (65MB)
109 22:55:03.302557 progress 60% (71MB)
110 22:55:03.640083 progress 65% (77MB)
111 22:55:04.015222 progress 70% (83MB)
112 22:55:04.403307 progress 75% (89MB)
113 22:55:04.816986 progress 80% (95MB)
114 22:55:05.233419 progress 85% (101MB)
115 22:55:05.472579 progress 90% (107MB)
116 22:55:05.827926 progress 95% (113MB)
117 22:55:06.199119 progress 100% (119MB)
118 22:55:06.205321 119MB downloaded in 6.83s (17.49MB/s)
119 22:55:06.205703 end: 1.4.1 http-download (duration 00:00:07) [common]
121 22:55:06.206116 end: 1.4 download-retry (duration 00:00:07) [common]
122 22:55:06.206253 start: 1.5 download-retry (timeout 00:09:53) [common]
123 22:55:06.206388 start: 1.5.1 http-download (timeout 00:09:53) [common]
124 22:55:06.206593 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1314-g1ab0ac1d7e2e3/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 22:55:06.206705 saving as /var/lib/lava/dispatcher/tmp/10597665/tftp-deploy-ltd01qmt/modules/modules.tar
126 22:55:06.206805 total size: 8552396 (8MB)
127 22:55:06.206906 Using unxz to decompress xz
128 22:55:06.211436 progress 0% (0MB)
129 22:55:06.232720 progress 5% (0MB)
130 22:55:06.256461 progress 10% (0MB)
131 22:55:06.287091 progress 15% (1MB)
132 22:55:06.312783 progress 20% (1MB)
133 22:55:06.337143 progress 25% (2MB)
134 22:55:06.362288 progress 30% (2MB)
135 22:55:06.387991 progress 35% (2MB)
136 22:55:06.413611 progress 40% (3MB)
137 22:55:06.439695 progress 45% (3MB)
138 22:55:06.466261 progress 50% (4MB)
139 22:55:06.491975 progress 55% (4MB)
140 22:55:06.516679 progress 60% (4MB)
141 22:55:06.541827 progress 65% (5MB)
142 22:55:06.568108 progress 70% (5MB)
143 22:55:06.593727 progress 75% (6MB)
144 22:55:06.619802 progress 80% (6MB)
145 22:55:06.644574 progress 85% (6MB)
146 22:55:06.669596 progress 90% (7MB)
147 22:55:06.692734 progress 95% (7MB)
148 22:55:06.716730 progress 100% (8MB)
149 22:55:06.723115 8MB downloaded in 0.52s (15.80MB/s)
150 22:55:06.723383 end: 1.5.1 http-download (duration 00:00:01) [common]
152 22:55:06.723647 end: 1.5 download-retry (duration 00:00:01) [common]
153 22:55:06.723740 start: 1.6 prepare-tftp-overlay (timeout 00:09:52) [common]
154 22:55:06.723830 start: 1.6.1 extract-nfsrootfs (timeout 00:09:52) [common]
155 22:55:08.662093 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/10597665/extract-nfsrootfs-u6sgcmb6
156 22:55:08.662309 end: 1.6.1 extract-nfsrootfs (duration 00:00:02) [common]
157 22:55:08.662429 start: 1.6.2 lava-overlay (timeout 00:09:50) [common]
158 22:55:08.662595 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10597665/lava-overlay-7r5ipb6c
159 22:55:08.662732 makedir: /var/lib/lava/dispatcher/tmp/10597665/lava-overlay-7r5ipb6c/lava-10597665/bin
160 22:55:08.662847 makedir: /var/lib/lava/dispatcher/tmp/10597665/lava-overlay-7r5ipb6c/lava-10597665/tests
161 22:55:08.662958 makedir: /var/lib/lava/dispatcher/tmp/10597665/lava-overlay-7r5ipb6c/lava-10597665/results
162 22:55:08.663073 Creating /var/lib/lava/dispatcher/tmp/10597665/lava-overlay-7r5ipb6c/lava-10597665/bin/lava-add-keys
163 22:55:08.663252 Creating /var/lib/lava/dispatcher/tmp/10597665/lava-overlay-7r5ipb6c/lava-10597665/bin/lava-add-sources
164 22:55:08.663420 Creating /var/lib/lava/dispatcher/tmp/10597665/lava-overlay-7r5ipb6c/lava-10597665/bin/lava-background-process-start
165 22:55:08.663585 Creating /var/lib/lava/dispatcher/tmp/10597665/lava-overlay-7r5ipb6c/lava-10597665/bin/lava-background-process-stop
166 22:55:08.663725 Creating /var/lib/lava/dispatcher/tmp/10597665/lava-overlay-7r5ipb6c/lava-10597665/bin/lava-common-functions
167 22:55:08.663889 Creating /var/lib/lava/dispatcher/tmp/10597665/lava-overlay-7r5ipb6c/lava-10597665/bin/lava-echo-ipv4
168 22:55:08.664077 Creating /var/lib/lava/dispatcher/tmp/10597665/lava-overlay-7r5ipb6c/lava-10597665/bin/lava-install-packages
169 22:55:08.664226 Creating /var/lib/lava/dispatcher/tmp/10597665/lava-overlay-7r5ipb6c/lava-10597665/bin/lava-installed-packages
170 22:55:08.664361 Creating /var/lib/lava/dispatcher/tmp/10597665/lava-overlay-7r5ipb6c/lava-10597665/bin/lava-os-build
171 22:55:08.664499 Creating /var/lib/lava/dispatcher/tmp/10597665/lava-overlay-7r5ipb6c/lava-10597665/bin/lava-probe-channel
172 22:55:08.664665 Creating /var/lib/lava/dispatcher/tmp/10597665/lava-overlay-7r5ipb6c/lava-10597665/bin/lava-probe-ip
173 22:55:08.664828 Creating /var/lib/lava/dispatcher/tmp/10597665/lava-overlay-7r5ipb6c/lava-10597665/bin/lava-target-ip
174 22:55:08.664990 Creating /var/lib/lava/dispatcher/tmp/10597665/lava-overlay-7r5ipb6c/lava-10597665/bin/lava-target-mac
175 22:55:08.665126 Creating /var/lib/lava/dispatcher/tmp/10597665/lava-overlay-7r5ipb6c/lava-10597665/bin/lava-target-storage
176 22:55:08.665263 Creating /var/lib/lava/dispatcher/tmp/10597665/lava-overlay-7r5ipb6c/lava-10597665/bin/lava-test-case
177 22:55:08.665402 Creating /var/lib/lava/dispatcher/tmp/10597665/lava-overlay-7r5ipb6c/lava-10597665/bin/lava-test-event
178 22:55:08.665537 Creating /var/lib/lava/dispatcher/tmp/10597665/lava-overlay-7r5ipb6c/lava-10597665/bin/lava-test-feedback
179 22:55:08.665673 Creating /var/lib/lava/dispatcher/tmp/10597665/lava-overlay-7r5ipb6c/lava-10597665/bin/lava-test-raise
180 22:55:08.665812 Creating /var/lib/lava/dispatcher/tmp/10597665/lava-overlay-7r5ipb6c/lava-10597665/bin/lava-test-reference
181 22:55:08.665977 Creating /var/lib/lava/dispatcher/tmp/10597665/lava-overlay-7r5ipb6c/lava-10597665/bin/lava-test-runner
182 22:55:08.666141 Creating /var/lib/lava/dispatcher/tmp/10597665/lava-overlay-7r5ipb6c/lava-10597665/bin/lava-test-set
183 22:55:08.666305 Creating /var/lib/lava/dispatcher/tmp/10597665/lava-overlay-7r5ipb6c/lava-10597665/bin/lava-test-shell
184 22:55:08.666470 Updating /var/lib/lava/dispatcher/tmp/10597665/lava-overlay-7r5ipb6c/lava-10597665/bin/lava-install-packages (oe)
185 22:55:08.666663 Updating /var/lib/lava/dispatcher/tmp/10597665/lava-overlay-7r5ipb6c/lava-10597665/bin/lava-installed-packages (oe)
186 22:55:08.666822 Creating /var/lib/lava/dispatcher/tmp/10597665/lava-overlay-7r5ipb6c/lava-10597665/environment
187 22:55:08.666954 LAVA metadata
188 22:55:08.667060 - LAVA_JOB_ID=10597665
189 22:55:08.667138 - LAVA_DISPATCHER_IP=192.168.201.1
190 22:55:08.667260 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:50) [common]
191 22:55:08.667334 skipped lava-vland-overlay
192 22:55:08.667431 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
193 22:55:08.667552 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:50) [common]
194 22:55:08.667647 skipped lava-multinode-overlay
195 22:55:08.667765 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
196 22:55:08.667886 start: 1.6.2.3 test-definition (timeout 00:09:50) [common]
197 22:55:08.668005 Loading test definitions
198 22:55:08.668179 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:50) [common]
199 22:55:08.668261 Using /lava-10597665 at stage 0
200 22:55:08.668679 uuid=10597665_1.6.2.3.1 testdef=None
201 22:55:08.668802 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
202 22:55:08.668926 start: 1.6.2.3.2 test-overlay (timeout 00:09:50) [common]
203 22:55:08.669644 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
205 22:55:08.670012 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:50) [common]
206 22:55:08.670924 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
208 22:55:08.671204 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:50) [common]
209 22:55:08.672464 runner path: /var/lib/lava/dispatcher/tmp/10597665/lava-overlay-7r5ipb6c/lava-10597665/0/tests/0_dmesg test_uuid 10597665_1.6.2.3.1
210 22:55:08.672630 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
212 22:55:08.672881 start: 1.6.2.3.5 inline-repo-action (timeout 00:09:50) [common]
213 22:55:08.672963 Using /lava-10597665 at stage 1
214 22:55:08.673349 uuid=10597665_1.6.2.3.5 testdef=None
215 22:55:08.673471 end: 1.6.2.3.5 inline-repo-action (duration 00:00:00) [common]
216 22:55:08.673595 start: 1.6.2.3.6 test-overlay (timeout 00:09:50) [common]
217 22:55:08.674276 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
219 22:55:08.674635 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:50) [common]
220 22:55:08.675556 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
222 22:55:08.675934 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:50) [common]
223 22:55:08.676613 runner path: /var/lib/lava/dispatcher/tmp/10597665/lava-overlay-7r5ipb6c/lava-10597665/1/tests/1_bootrr test_uuid 10597665_1.6.2.3.5
224 22:55:08.676774 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
226 22:55:08.677000 Creating lava-test-runner.conf files
227 22:55:08.677080 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10597665/lava-overlay-7r5ipb6c/lava-10597665/0 for stage 0
228 22:55:08.677194 - 0_dmesg
229 22:55:08.677285 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10597665/lava-overlay-7r5ipb6c/lava-10597665/1 for stage 1
230 22:55:08.677393 - 1_bootrr
231 22:55:08.677527 end: 1.6.2.3 test-definition (duration 00:00:00) [common]
232 22:55:08.677652 start: 1.6.2.4 compress-overlay (timeout 00:09:50) [common]
233 22:55:08.684721 end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
234 22:55:08.684832 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:50) [common]
235 22:55:08.684933 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
236 22:55:08.685038 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
237 22:55:08.685137 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:50) [common]
238 22:55:08.799866 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
239 22:55:08.800266 start: 1.6.4 extract-modules (timeout 00:09:50) [common]
240 22:55:08.800408 extracting modules file /var/lib/lava/dispatcher/tmp/10597665/tftp-deploy-ltd01qmt/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10597665/extract-nfsrootfs-u6sgcmb6
241 22:55:08.999468 extracting modules file /var/lib/lava/dispatcher/tmp/10597665/tftp-deploy-ltd01qmt/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10597665/extract-overlay-ramdisk-_lcf0e7v/ramdisk
242 22:55:09.204931 end: 1.6.4 extract-modules (duration 00:00:00) [common]
243 22:55:09.205115 start: 1.6.5 apply-overlay-tftp (timeout 00:09:50) [common]
244 22:55:09.205251 [common] Applying overlay to NFS
245 22:55:09.205356 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10597665/compress-overlay-ydat524c/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10597665/extract-nfsrootfs-u6sgcmb6
246 22:55:09.213905 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
247 22:55:09.214017 start: 1.6.6 configure-preseed-file (timeout 00:09:50) [common]
248 22:55:09.214105 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
249 22:55:09.214193 start: 1.6.7 compress-ramdisk (timeout 00:09:50) [common]
250 22:55:09.214276 Building ramdisk /var/lib/lava/dispatcher/tmp/10597665/extract-overlay-ramdisk-_lcf0e7v/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10597665/extract-overlay-ramdisk-_lcf0e7v/ramdisk
251 22:55:09.515558 >> 117807 blocks
252 22:55:11.441223 rename /var/lib/lava/dispatcher/tmp/10597665/extract-overlay-ramdisk-_lcf0e7v/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10597665/tftp-deploy-ltd01qmt/ramdisk/ramdisk.cpio.gz
253 22:55:11.441665 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
254 22:55:11.441790 start: 1.6.8 prepare-kernel (timeout 00:09:47) [common]
255 22:55:11.441894 start: 1.6.8.1 prepare-fit (timeout 00:09:47) [common]
256 22:55:11.442002 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10597665/tftp-deploy-ltd01qmt/kernel/Image'
257 22:55:23.065438 Returned 0 in 11 seconds
258 22:55:23.166061 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10597665/tftp-deploy-ltd01qmt/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10597665/tftp-deploy-ltd01qmt/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10597665/tftp-deploy-ltd01qmt/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10597665/tftp-deploy-ltd01qmt/kernel/image.itb
259 22:55:23.480328 output: FIT description: Kernel Image image with one or more FDT blobs
260 22:55:23.480691 output: Created: Mon Jun 5 23:55:23 2023
261 22:55:23.480768 output: Image 0 (kernel-1)
262 22:55:23.480833 output: Description:
263 22:55:23.480899 output: Created: Mon Jun 5 23:55:23 2023
264 22:55:23.480962 output: Type: Kernel Image
265 22:55:23.481026 output: Compression: lzma compressed
266 22:55:23.481086 output: Data Size: 10085945 Bytes = 9849.56 KiB = 9.62 MiB
267 22:55:23.481147 output: Architecture: AArch64
268 22:55:23.481206 output: OS: Linux
269 22:55:23.481264 output: Load Address: 0x00000000
270 22:55:23.481321 output: Entry Point: 0x00000000
271 22:55:23.481374 output: Hash algo: crc32
272 22:55:23.481428 output: Hash value: b2943ff2
273 22:55:23.481482 output: Image 1 (fdt-1)
274 22:55:23.481535 output: Description: mt8192-asurada-spherion-r0
275 22:55:23.481588 output: Created: Mon Jun 5 23:55:23 2023
276 22:55:23.481641 output: Type: Flat Device Tree
277 22:55:23.481694 output: Compression: uncompressed
278 22:55:23.481747 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
279 22:55:23.481800 output: Architecture: AArch64
280 22:55:23.481852 output: Hash algo: crc32
281 22:55:23.481905 output: Hash value: 1df858fa
282 22:55:23.481958 output: Image 2 (ramdisk-1)
283 22:55:23.482010 output: Description: unavailable
284 22:55:23.482063 output: Created: Mon Jun 5 23:55:23 2023
285 22:55:23.482116 output: Type: RAMDisk Image
286 22:55:23.482168 output: Compression: Unknown Compression
287 22:55:23.482221 output: Data Size: 17639152 Bytes = 17225.73 KiB = 16.82 MiB
288 22:55:23.482273 output: Architecture: AArch64
289 22:55:23.482325 output: OS: Linux
290 22:55:23.482377 output: Load Address: unavailable
291 22:55:23.482429 output: Entry Point: unavailable
292 22:55:23.482481 output: Hash algo: crc32
293 22:55:23.482533 output: Hash value: 8bddf8cc
294 22:55:23.482585 output: Default Configuration: 'conf-1'
295 22:55:23.482637 output: Configuration 0 (conf-1)
296 22:55:23.482690 output: Description: mt8192-asurada-spherion-r0
297 22:55:23.482741 output: Kernel: kernel-1
298 22:55:23.482794 output: Init Ramdisk: ramdisk-1
299 22:55:23.482846 output: FDT: fdt-1
300 22:55:23.482898 output: Loadables: kernel-1
301 22:55:23.482950 output:
302 22:55:23.483147 end: 1.6.8.1 prepare-fit (duration 00:00:12) [common]
303 22:55:23.483246 end: 1.6.8 prepare-kernel (duration 00:00:12) [common]
304 22:55:23.483350 end: 1.6 prepare-tftp-overlay (duration 00:00:17) [common]
305 22:55:23.483440 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:35) [common]
306 22:55:23.483518 No LXC device requested
307 22:55:23.483600 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
308 22:55:23.483723 start: 1.8 deploy-device-env (timeout 00:09:35) [common]
309 22:55:23.483801 end: 1.8 deploy-device-env (duration 00:00:00) [common]
310 22:55:23.483867 Checking files for TFTP limit of 4294967296 bytes.
311 22:55:23.484404 end: 1 tftp-deploy (duration 00:00:25) [common]
312 22:55:23.484512 start: 2 depthcharge-action (timeout 00:05:00) [common]
313 22:55:23.484604 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
314 22:55:23.484735 substitutions:
315 22:55:23.484804 - {DTB}: 10597665/tftp-deploy-ltd01qmt/dtb/mt8192-asurada-spherion-r0.dtb
316 22:55:23.484870 - {INITRD}: 10597665/tftp-deploy-ltd01qmt/ramdisk/ramdisk.cpio.gz
317 22:55:23.484929 - {KERNEL}: 10597665/tftp-deploy-ltd01qmt/kernel/Image
318 22:55:23.484987 - {LAVA_MAC}: None
319 22:55:23.485043 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/10597665/extract-nfsrootfs-u6sgcmb6
320 22:55:23.485099 - {NFS_SERVER_IP}: 192.168.201.1
321 22:55:23.485154 - {PRESEED_CONFIG}: None
322 22:55:23.485208 - {PRESEED_LOCAL}: None
323 22:55:23.485261 - {RAMDISK}: 10597665/tftp-deploy-ltd01qmt/ramdisk/ramdisk.cpio.gz
324 22:55:23.485315 - {ROOT_PART}: None
325 22:55:23.485369 - {ROOT}: None
326 22:55:23.485423 - {SERVER_IP}: 192.168.201.1
327 22:55:23.485475 - {TEE}: None
328 22:55:23.485528 Parsed boot commands:
329 22:55:23.485581 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
330 22:55:23.485790 Parsed boot commands: tftpboot 192.168.201.1 10597665/tftp-deploy-ltd01qmt/kernel/image.itb 10597665/tftp-deploy-ltd01qmt/kernel/cmdline
331 22:55:23.485935 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
332 22:55:23.486023 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
333 22:55:23.486116 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
334 22:55:23.486199 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
335 22:55:23.486271 Not connected, no need to disconnect.
336 22:55:23.486346 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
337 22:55:23.486427 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
338 22:55:23.486493 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-2'
339 22:55:23.490088 Setting prompt string to ['lava-test: # ']
340 22:55:23.490466 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
341 22:55:23.490584 end: 2.2.1 reset-connection (duration 00:00:00) [common]
342 22:55:23.490685 start: 2.2.2 reset-device (timeout 00:05:00) [common]
343 22:55:23.490777 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
344 22:55:23.490973 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=reboot'
345 22:55:28.625901 >> Command sent successfully.
346 22:55:28.628408 Returned 0 in 5 seconds
347 22:55:28.728869 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
349 22:55:28.729262 end: 2.2.2 reset-device (duration 00:00:05) [common]
350 22:55:28.729383 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
351 22:55:28.729487 Setting prompt string to 'Starting depthcharge on Spherion...'
352 22:55:28.729564 Changing prompt to 'Starting depthcharge on Spherion...'
353 22:55:28.729653 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
354 22:55:28.730015 [Enter `^Ec?' for help]
355 22:55:28.900876
356 22:55:28.901047
357 22:55:28.901147 F0: 102B 0000
358 22:55:28.901230
359 22:55:28.905482 F3: 1001 0000 [0200]
360 22:55:28.905605
361 22:55:28.905700 F3: 1001 0000
362 22:55:28.905783
363 22:55:28.905861 F7: 102D 0000
364 22:55:28.905938
365 22:55:28.907856 F1: 0000 0000
366 22:55:28.907947
367 22:55:28.908079 V0: 0000 0000 [0001]
368 22:55:28.908195
369 22:55:28.911481 00: 0007 8000
370 22:55:28.911595
371 22:55:28.911683 01: 0000 0000
372 22:55:28.911766
373 22:55:28.911866 BP: 0C00 0209 [0000]
374 22:55:28.911966
375 22:55:28.914852 G0: 1182 0000
376 22:55:28.914968
377 22:55:28.915056 EC: 0000 0021 [4000]
378 22:55:28.915135
379 22:55:28.919605 S7: 0000 0000 [0000]
380 22:55:28.919724
381 22:55:28.919816 CC: 0000 0000 [0001]
382 22:55:28.919917
383 22:55:28.921871 T0: 0000 0040 [010F]
384 22:55:28.921961
385 22:55:28.922029 Jump to BL
386 22:55:28.922090
387 22:55:28.947892
388 22:55:28.948065
389 22:55:28.948143
390 22:55:28.955897 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
391 22:55:28.959763 ARM64: Exception handlers installed.
392 22:55:28.963312 ARM64: Testing exception
393 22:55:28.966302 ARM64: Done test exception
394 22:55:28.973666 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
395 22:55:28.980814 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
396 22:55:28.987923 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
397 22:55:28.998977 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
398 22:55:29.005762 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
399 22:55:29.015589 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
400 22:55:29.026206 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
401 22:55:29.032844 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
402 22:55:29.050939 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
403 22:55:29.054300 WDT: Last reset was cold boot
404 22:55:29.057576 SPI1(PAD0) initialized at 2873684 Hz
405 22:55:29.060747 SPI5(PAD0) initialized at 992727 Hz
406 22:55:29.064183 VBOOT: Loading verstage.
407 22:55:29.070748 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
408 22:55:29.074192 FMAP: Found "FLASH" version 1.1 at 0x20000.
409 22:55:29.077732 FMAP: base = 0x0 size = 0x800000 #areas = 25
410 22:55:29.080717 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
411 22:55:29.088373 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
412 22:55:29.095038 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
413 22:55:29.106458 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
414 22:55:29.106620
415 22:55:29.106721
416 22:55:29.115583 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
417 22:55:29.119165 ARM64: Exception handlers installed.
418 22:55:29.122356 ARM64: Testing exception
419 22:55:29.122477 ARM64: Done test exception
420 22:55:29.129699 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
421 22:55:29.133095 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 22:55:29.146936 Probing TPM: . done!
423 22:55:29.147101 TPM ready after 0 ms
424 22:55:29.156048 Connected to device vid:did:rid of 1ae0:0028:00
425 22:55:29.162402 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
426 22:55:29.221059 Initialized TPM device CR50 revision 0
427 22:55:29.230812 tlcl_send_startup: Startup return code is 0
428 22:55:29.230978 TPM: setup succeeded
429 22:55:29.242311 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
430 22:55:29.251339 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
431 22:55:29.263539 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
432 22:55:29.273360 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
433 22:55:29.277158 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
434 22:55:29.282410 in-header: 03 07 00 00 08 00 00 00
435 22:55:29.286043 in-data: aa e4 47 04 13 02 00 00
436 22:55:29.288719 Chrome EC: UHEPI supported
437 22:55:29.296637 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
438 22:55:29.299566 in-header: 03 95 00 00 08 00 00 00
439 22:55:29.303317 in-data: 18 20 20 08 00 00 00 00
440 22:55:29.303450 Phase 1
441 22:55:29.306944 FMAP: area GBB found @ 3f5000 (12032 bytes)
442 22:55:29.314869 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
443 22:55:29.317989 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
444 22:55:29.322335 Recovery requested (1009000e)
445 22:55:29.330599 TPM: Extending digest for VBOOT: boot mode into PCR 0
446 22:55:29.336244 tlcl_extend: response is 0
447 22:55:29.345763 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
448 22:55:29.350722 tlcl_extend: response is 0
449 22:55:29.358014 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
450 22:55:29.377776 read SPI 0x210d4 0x2173b: 15142 us, 9048 KB/s, 72.384 Mbps
451 22:55:29.384213 BS: bootblock times (exec / console): total (unknown) / 148 ms
452 22:55:29.384365
453 22:55:29.384439
454 22:55:29.394516 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
455 22:55:29.398205 ARM64: Exception handlers installed.
456 22:55:29.401522 ARM64: Testing exception
457 22:55:29.401656 ARM64: Done test exception
458 22:55:29.423395 pmic_efuse_setting: Set efuses in 11 msecs
459 22:55:29.426576 pmwrap_interface_init: Select PMIF_VLD_RDY
460 22:55:29.432921 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
461 22:55:29.436563 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
462 22:55:29.443932 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
463 22:55:29.447833 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
464 22:55:29.450870 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
465 22:55:29.457800 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
466 22:55:29.462617 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
467 22:55:29.466234 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
468 22:55:29.472653 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
469 22:55:29.476629 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
470 22:55:29.479836 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
471 22:55:29.483873 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
472 22:55:29.487757 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
473 22:55:29.495628 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
474 22:55:29.503137 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
475 22:55:29.506547 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
476 22:55:29.513709 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
477 22:55:29.518086 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
478 22:55:29.525009 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
479 22:55:29.529031 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
480 22:55:29.536132 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
481 22:55:29.539644 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
482 22:55:29.546946 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
483 22:55:29.551119 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
484 22:55:29.558660 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
485 22:55:29.561972 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
486 22:55:29.569430 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
487 22:55:29.572501 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
488 22:55:29.577216 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
489 22:55:29.583535 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
490 22:55:29.587088 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
491 22:55:29.594150 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
492 22:55:29.597892 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
493 22:55:29.601416 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
494 22:55:29.609077 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
495 22:55:29.612448 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
496 22:55:29.616223 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
497 22:55:29.623473 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
498 22:55:29.627127 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
499 22:55:29.630617 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
500 22:55:29.634739 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
501 22:55:29.638424 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
502 22:55:29.645719 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
503 22:55:29.648779 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
504 22:55:29.652858 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
505 22:55:29.656690 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
506 22:55:29.659983 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
507 22:55:29.664020 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
508 22:55:29.671133 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
509 22:55:29.675010 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
510 22:55:29.678815 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
511 22:55:29.686016 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
512 22:55:29.693928 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
513 22:55:29.700514 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
514 22:55:29.707367 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
515 22:55:29.715740 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
516 22:55:29.722374 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
517 22:55:29.725423 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
518 22:55:29.728728 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
519 22:55:29.735982 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6b, sec=0x3
520 22:55:29.743735 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
521 22:55:29.747301 [RTC]rtc_osc_init,62: osc32con val = 0xde6b
522 22:55:29.750699 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
523 22:55:29.760653 [RTC]rtc_get_frequency_meter,154: input=15, output=853
524 22:55:29.770762 [RTC]rtc_get_frequency_meter,154: input=7, output=725
525 22:55:29.779738 [RTC]rtc_get_frequency_meter,154: input=11, output=789
526 22:55:29.789104 [RTC]rtc_get_frequency_meter,154: input=13, output=820
527 22:55:29.798787 [RTC]rtc_get_frequency_meter,154: input=12, output=805
528 22:55:29.808212 [RTC]rtc_get_frequency_meter,154: input=11, output=789
529 22:55:29.818299 [RTC]rtc_get_frequency_meter,154: input=12, output=805
530 22:55:29.821614 [RTC]rtc_eosc_cali,47: left: 11, middle: 11, right: 12
531 22:55:29.828764 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6b
532 22:55:29.832101 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
533 22:55:29.835922 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
534 22:55:29.839531 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
535 22:55:29.843740 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
536 22:55:29.847225 ADC[4]: Raw value=905541 ID=7
537 22:55:29.850623 ADC[3]: Raw value=213546 ID=1
538 22:55:29.850749 RAM Code: 0x71
539 22:55:29.853878 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
540 22:55:29.861619 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
541 22:55:29.868491 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
542 22:55:29.875881 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
543 22:55:29.879881 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
544 22:55:29.883143 in-header: 03 07 00 00 08 00 00 00
545 22:55:29.887419 in-data: aa e4 47 04 13 02 00 00
546 22:55:29.887528 Chrome EC: UHEPI supported
547 22:55:29.893821 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
548 22:55:29.898456 in-header: 03 95 00 00 08 00 00 00
549 22:55:29.901200 in-data: 18 20 20 08 00 00 00 00
550 22:55:29.904881 MRC: failed to locate region type 0.
551 22:55:29.913229 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
552 22:55:29.916349 DRAM-K: Running full calibration
553 22:55:29.919773 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
554 22:55:29.923706 header.status = 0x0
555 22:55:29.926947 header.version = 0x6 (expected: 0x6)
556 22:55:29.930711 header.size = 0xd00 (expected: 0xd00)
557 22:55:29.930842 header.flags = 0x0
558 22:55:29.937843 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
559 22:55:29.954953 read SPI 0x72590 0x1c583: 12500 us, 9287 KB/s, 74.296 Mbps
560 22:55:29.963215 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
561 22:55:29.966535 dram_init: ddr_geometry: 2
562 22:55:29.966675 [EMI] MDL number = 2
563 22:55:29.969343 [EMI] Get MDL freq = 0
564 22:55:29.969443 dram_init: ddr_type: 0
565 22:55:29.973382 is_discrete_lpddr4: 1
566 22:55:29.977440 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
567 22:55:29.977543
568 22:55:29.977634
569 22:55:29.977716 [Bian_co] ETT version 0.0.0.1
570 22:55:29.984247 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
571 22:55:29.984385
572 22:55:29.988542 dramc_set_vcore_voltage set vcore to 650000
573 22:55:29.988643 Read voltage for 800, 4
574 22:55:29.991483 Vio18 = 0
575 22:55:29.991575 Vcore = 650000
576 22:55:29.991664 Vdram = 0
577 22:55:29.994847 Vddq = 0
578 22:55:29.995000 Vmddr = 0
579 22:55:29.999569 dram_init: config_dvfs: 1
580 22:55:30.002076 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
581 22:55:30.008608 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
582 22:55:30.012670 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
583 22:55:30.016280 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
584 22:55:30.020364 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
585 22:55:30.023351 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
586 22:55:30.023462 MEM_TYPE=3, freq_sel=18
587 22:55:30.027343 sv_algorithm_assistance_LP4_1600
588 22:55:30.031097 ============ PULL DRAM RESETB DOWN ============
589 22:55:30.037323 ========== PULL DRAM RESETB DOWN end =========
590 22:55:30.040676 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
591 22:55:30.044351 ===================================
592 22:55:30.047089 LPDDR4 DRAM CONFIGURATION
593 22:55:30.050540 ===================================
594 22:55:30.050646 EX_ROW_EN[0] = 0x0
595 22:55:30.054069 EX_ROW_EN[1] = 0x0
596 22:55:30.054161 LP4Y_EN = 0x0
597 22:55:30.058117 WORK_FSP = 0x0
598 22:55:30.058212 WL = 0x2
599 22:55:30.061186 RL = 0x2
600 22:55:30.061277 BL = 0x2
601 22:55:30.064171 RPST = 0x0
602 22:55:30.064260 RD_PRE = 0x0
603 22:55:30.067498 WR_PRE = 0x1
604 22:55:30.070732 WR_PST = 0x0
605 22:55:30.070833 DBI_WR = 0x0
606 22:55:30.073879 DBI_RD = 0x0
607 22:55:30.073969 OTF = 0x1
608 22:55:30.077071 ===================================
609 22:55:30.080961 ===================================
610 22:55:30.081059 ANA top config
611 22:55:30.084449 ===================================
612 22:55:30.087521 DLL_ASYNC_EN = 0
613 22:55:30.091274 ALL_SLAVE_EN = 1
614 22:55:30.093810 NEW_RANK_MODE = 1
615 22:55:30.097254 DLL_IDLE_MODE = 1
616 22:55:30.097352 LP45_APHY_COMB_EN = 1
617 22:55:30.100616 TX_ODT_DIS = 1
618 22:55:30.103749 NEW_8X_MODE = 1
619 22:55:30.107112 ===================================
620 22:55:30.110538 ===================================
621 22:55:30.113955 data_rate = 1600
622 22:55:30.116928 CKR = 1
623 22:55:30.117021 DQ_P2S_RATIO = 8
624 22:55:30.120277 ===================================
625 22:55:30.123790 CA_P2S_RATIO = 8
626 22:55:30.127097 DQ_CA_OPEN = 0
627 22:55:30.131082 DQ_SEMI_OPEN = 0
628 22:55:30.134544 CA_SEMI_OPEN = 0
629 22:55:30.134690 CA_FULL_RATE = 0
630 22:55:30.137651 DQ_CKDIV4_EN = 1
631 22:55:30.140998 CA_CKDIV4_EN = 1
632 22:55:30.144394 CA_PREDIV_EN = 0
633 22:55:30.148008 PH8_DLY = 0
634 22:55:30.150980 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
635 22:55:30.151094 DQ_AAMCK_DIV = 4
636 22:55:30.154330 CA_AAMCK_DIV = 4
637 22:55:30.158152 CA_ADMCK_DIV = 4
638 22:55:30.160912 DQ_TRACK_CA_EN = 0
639 22:55:30.165093 CA_PICK = 800
640 22:55:30.167763 CA_MCKIO = 800
641 22:55:30.167857 MCKIO_SEMI = 0
642 22:55:30.170794 PLL_FREQ = 3068
643 22:55:30.174352 DQ_UI_PI_RATIO = 32
644 22:55:30.178203 CA_UI_PI_RATIO = 0
645 22:55:30.181958 ===================================
646 22:55:30.185350 ===================================
647 22:55:30.185452 memory_type:LPDDR4
648 22:55:30.188804 GP_NUM : 10
649 22:55:30.192715 SRAM_EN : 1
650 22:55:30.192817 MD32_EN : 0
651 22:55:30.196336 ===================================
652 22:55:30.199933 [ANA_INIT] >>>>>>>>>>>>>>
653 22:55:30.200088 <<<<<< [CONFIGURE PHASE]: ANA_TX
654 22:55:30.203573 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
655 22:55:30.207176 ===================================
656 22:55:30.210289 data_rate = 1600,PCW = 0X7600
657 22:55:30.213558 ===================================
658 22:55:30.216804 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
659 22:55:30.223839 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
660 22:55:30.227584 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
661 22:55:30.233539 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
662 22:55:30.237448 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
663 22:55:30.240549 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
664 22:55:30.243594 [ANA_INIT] flow start
665 22:55:30.243691 [ANA_INIT] PLL >>>>>>>>
666 22:55:30.246780 [ANA_INIT] PLL <<<<<<<<
667 22:55:30.250245 [ANA_INIT] MIDPI >>>>>>>>
668 22:55:30.250340 [ANA_INIT] MIDPI <<<<<<<<
669 22:55:30.253680 [ANA_INIT] DLL >>>>>>>>
670 22:55:30.257093 [ANA_INIT] flow end
671 22:55:30.259946 ============ LP4 DIFF to SE enter ============
672 22:55:30.263703 ============ LP4 DIFF to SE exit ============
673 22:55:30.266829 [ANA_INIT] <<<<<<<<<<<<<
674 22:55:30.270569 [Flow] Enable top DCM control >>>>>
675 22:55:30.273526 [Flow] Enable top DCM control <<<<<
676 22:55:30.277028 Enable DLL master slave shuffle
677 22:55:30.280089 ==============================================================
678 22:55:30.284200 Gating Mode config
679 22:55:30.286945 ==============================================================
680 22:55:30.290861 Config description:
681 22:55:30.300263 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
682 22:55:30.306634 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
683 22:55:30.309913 SELPH_MODE 0: By rank 1: By Phase
684 22:55:30.317264 ==============================================================
685 22:55:30.320497 GAT_TRACK_EN = 1
686 22:55:30.323424 RX_GATING_MODE = 2
687 22:55:30.326750 RX_GATING_TRACK_MODE = 2
688 22:55:30.330043 SELPH_MODE = 1
689 22:55:30.333691 PICG_EARLY_EN = 1
690 22:55:30.336604 VALID_LAT_VALUE = 1
691 22:55:30.339859 ==============================================================
692 22:55:30.344252 Enter into Gating configuration >>>>
693 22:55:30.346846 Exit from Gating configuration <<<<
694 22:55:30.350193 Enter into DVFS_PRE_config >>>>>
695 22:55:30.359740 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
696 22:55:30.362933 Exit from DVFS_PRE_config <<<<<
697 22:55:30.366652 Enter into PICG configuration >>>>
698 22:55:30.370942 Exit from PICG configuration <<<<
699 22:55:30.373580 [RX_INPUT] configuration >>>>>
700 22:55:30.376402 [RX_INPUT] configuration <<<<<
701 22:55:30.383199 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
702 22:55:30.386180 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
703 22:55:30.392769 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
704 22:55:30.400181 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
705 22:55:30.406015 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
706 22:55:30.412724 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
707 22:55:30.415980 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
708 22:55:30.419304 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
709 22:55:30.422835 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
710 22:55:30.429747 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
711 22:55:30.432917 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
712 22:55:30.436180 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
713 22:55:30.439492 ===================================
714 22:55:30.442706 LPDDR4 DRAM CONFIGURATION
715 22:55:30.446160 ===================================
716 22:55:30.446254 EX_ROW_EN[0] = 0x0
717 22:55:30.449608 EX_ROW_EN[1] = 0x0
718 22:55:30.452441 LP4Y_EN = 0x0
719 22:55:30.452530 WORK_FSP = 0x0
720 22:55:30.455960 WL = 0x2
721 22:55:30.456071 RL = 0x2
722 22:55:30.459799 BL = 0x2
723 22:55:30.459889 RPST = 0x0
724 22:55:30.462722 RD_PRE = 0x0
725 22:55:30.462811 WR_PRE = 0x1
726 22:55:30.465888 WR_PST = 0x0
727 22:55:30.465977 DBI_WR = 0x0
728 22:55:30.469289 DBI_RD = 0x0
729 22:55:30.469377 OTF = 0x1
730 22:55:30.472463 ===================================
731 22:55:30.475861 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
732 22:55:30.482826 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
733 22:55:30.485706 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
734 22:55:30.489412 ===================================
735 22:55:30.492574 LPDDR4 DRAM CONFIGURATION
736 22:55:30.495701 ===================================
737 22:55:30.495831 EX_ROW_EN[0] = 0x10
738 22:55:30.499054 EX_ROW_EN[1] = 0x0
739 22:55:30.499164 LP4Y_EN = 0x0
740 22:55:30.502740 WORK_FSP = 0x0
741 22:55:30.502862 WL = 0x2
742 22:55:30.505966 RL = 0x2
743 22:55:30.509314 BL = 0x2
744 22:55:30.509432 RPST = 0x0
745 22:55:30.512202 RD_PRE = 0x0
746 22:55:30.512313 WR_PRE = 0x1
747 22:55:30.516199 WR_PST = 0x0
748 22:55:30.516311 DBI_WR = 0x0
749 22:55:30.519074 DBI_RD = 0x0
750 22:55:30.519185 OTF = 0x1
751 22:55:30.522503 ===================================
752 22:55:30.528866 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
753 22:55:30.532767 nWR fixed to 40
754 22:55:30.536530 [ModeRegInit_LP4] CH0 RK0
755 22:55:30.536663 [ModeRegInit_LP4] CH0 RK1
756 22:55:30.539639 [ModeRegInit_LP4] CH1 RK0
757 22:55:30.542658 [ModeRegInit_LP4] CH1 RK1
758 22:55:30.542769 match AC timing 13
759 22:55:30.550132 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
760 22:55:30.553643 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
761 22:55:30.556313 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
762 22:55:30.562795 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
763 22:55:30.566416 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
764 22:55:30.566546 [EMI DOE] emi_dcm 0
765 22:55:30.572750 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
766 22:55:30.572895 ==
767 22:55:30.576409 Dram Type= 6, Freq= 0, CH_0, rank 0
768 22:55:30.579569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
769 22:55:30.579691 ==
770 22:55:30.586002 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
771 22:55:30.592447 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
772 22:55:30.600501 [CA 0] Center 37 (7~68) winsize 62
773 22:55:30.603854 [CA 1] Center 37 (7~68) winsize 62
774 22:55:30.606951 [CA 2] Center 34 (4~65) winsize 62
775 22:55:30.610494 [CA 3] Center 35 (4~66) winsize 63
776 22:55:30.613607 [CA 4] Center 33 (3~64) winsize 62
777 22:55:30.616587 [CA 5] Center 33 (3~64) winsize 62
778 22:55:30.616704
779 22:55:30.620411 [CmdBusTrainingLP45] Vref(ca) range 1: 34
780 22:55:30.620522
781 22:55:30.623244 [CATrainingPosCal] consider 1 rank data
782 22:55:30.627079 u2DelayCellTimex100 = 270/100 ps
783 22:55:30.630445 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
784 22:55:30.636600 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
785 22:55:30.639733 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
786 22:55:30.643075 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
787 22:55:30.646599 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
788 22:55:30.649836 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
789 22:55:30.649951
790 22:55:30.653087 CA PerBit enable=1, Macro0, CA PI delay=33
791 22:55:30.653205
792 22:55:30.656880 [CBTSetCACLKResult] CA Dly = 33
793 22:55:30.659927 CS Dly: 5 (0~36)
794 22:55:30.660066 ==
795 22:55:30.663303 Dram Type= 6, Freq= 0, CH_0, rank 1
796 22:55:30.666245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
797 22:55:30.666362 ==
798 22:55:30.672952 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
799 22:55:30.676044 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
800 22:55:30.686818 [CA 0] Center 38 (7~69) winsize 63
801 22:55:30.690025 [CA 1] Center 37 (7~68) winsize 62
802 22:55:30.693264 [CA 2] Center 35 (4~66) winsize 63
803 22:55:30.696993 [CA 3] Center 35 (4~66) winsize 63
804 22:55:30.700005 [CA 4] Center 34 (3~65) winsize 63
805 22:55:30.703433 [CA 5] Center 33 (3~64) winsize 62
806 22:55:30.703577
807 22:55:30.706795 [CmdBusTrainingLP45] Vref(ca) range 1: 34
808 22:55:30.706913
809 22:55:30.710522 [CATrainingPosCal] consider 2 rank data
810 22:55:30.713141 u2DelayCellTimex100 = 270/100 ps
811 22:55:30.716968 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
812 22:55:30.723033 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
813 22:55:30.726681 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
814 22:55:30.729838 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
815 22:55:30.733186 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
816 22:55:30.736413 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
817 22:55:30.736539
818 22:55:30.739785 CA PerBit enable=1, Macro0, CA PI delay=33
819 22:55:30.739895
820 22:55:30.743385 [CBTSetCACLKResult] CA Dly = 33
821 22:55:30.743498 CS Dly: 6 (0~38)
822 22:55:30.746175
823 22:55:30.749512 ----->DramcWriteLeveling(PI) begin...
824 22:55:30.749628 ==
825 22:55:30.753427 Dram Type= 6, Freq= 0, CH_0, rank 0
826 22:55:30.756962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
827 22:55:30.757086 ==
828 22:55:30.760806 Write leveling (Byte 0): 29 => 29
829 22:55:30.760923 Write leveling (Byte 1): 28 => 28
830 22:55:30.764803 DramcWriteLeveling(PI) end<-----
831 22:55:30.764922
832 22:55:30.765019 ==
833 22:55:30.768681 Dram Type= 6, Freq= 0, CH_0, rank 0
834 22:55:30.771746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
835 22:55:30.775018 ==
836 22:55:30.775141 [Gating] SW mode calibration
837 22:55:30.781871 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
838 22:55:30.789103 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
839 22:55:30.793058 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
840 22:55:30.795532 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
841 22:55:30.802484 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
842 22:55:30.805507 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
843 22:55:30.808595 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
844 22:55:30.815575 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
845 22:55:30.818743 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
846 22:55:30.822204 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
847 22:55:30.828869 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
848 22:55:30.832365 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
849 22:55:30.835309 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
850 22:55:30.841905 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
851 22:55:30.845161 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
852 22:55:30.849221 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
853 22:55:30.855395 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
854 22:55:30.859065 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 22:55:30.863497 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
856 22:55:30.868689 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
857 22:55:30.871921 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
858 22:55:30.875456 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
859 22:55:30.882045 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 22:55:30.885240 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 22:55:30.888346 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 22:55:30.894954 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 22:55:30.898387 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 22:55:30.901509 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 22:55:30.908567 0 9 8 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
866 22:55:30.911818 0 9 12 | B1->B0 | 2c2c 3434 | 0 1 | (0 0) (1 1)
867 22:55:30.914906 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
868 22:55:30.921245 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
869 22:55:30.924830 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
870 22:55:30.927883 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
871 22:55:30.934644 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
872 22:55:30.938469 0 10 4 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
873 22:55:30.941130 0 10 8 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
874 22:55:30.944564 0 10 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
875 22:55:30.951341 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 22:55:30.955527 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 22:55:30.957920 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 22:55:30.964446 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
879 22:55:30.968820 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
880 22:55:30.971078 0 11 4 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
881 22:55:30.977966 0 11 8 | B1->B0 | 2727 3d3d | 0 0 | (0 0) (0 0)
882 22:55:30.981600 0 11 12 | B1->B0 | 3c3c 4646 | 0 0 | (1 1) (0 0)
883 22:55:30.984721 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
884 22:55:30.990973 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
885 22:55:30.994224 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
886 22:55:30.997821 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
887 22:55:31.004434 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
888 22:55:31.007765 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
889 22:55:31.011706 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
890 22:55:31.017498 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
891 22:55:31.021200 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
892 22:55:31.024248 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
893 22:55:31.031425 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
894 22:55:31.034252 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
895 22:55:31.037538 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
896 22:55:31.044652 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
897 22:55:31.048280 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
898 22:55:31.051281 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
899 22:55:31.058013 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
900 22:55:31.060832 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
901 22:55:31.063986 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
902 22:55:31.070771 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
903 22:55:31.074141 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
904 22:55:31.077770 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
905 22:55:31.080526 Total UI for P1: 0, mck2ui 16
906 22:55:31.083990 best dqsien dly found for B0: ( 0, 14, 2)
907 22:55:31.087301 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
908 22:55:31.090849 Total UI for P1: 0, mck2ui 16
909 22:55:31.093992 best dqsien dly found for B1: ( 0, 14, 6)
910 22:55:31.100958 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
911 22:55:31.104051 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
912 22:55:31.104217
913 22:55:31.107506 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
914 22:55:31.111029 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
915 22:55:31.114388 [Gating] SW calibration Done
916 22:55:31.114523 ==
917 22:55:31.117605 Dram Type= 6, Freq= 0, CH_0, rank 0
918 22:55:31.120524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
919 22:55:31.120645 ==
920 22:55:31.120745 RX Vref Scan: 0
921 22:55:31.124303
922 22:55:31.124422 RX Vref 0 -> 0, step: 1
923 22:55:31.124520
924 22:55:31.128619 RX Delay -130 -> 252, step: 16
925 22:55:31.131217 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
926 22:55:31.134506 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
927 22:55:31.137658 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
928 22:55:31.144612 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
929 22:55:31.147768 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
930 22:55:31.152175 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
931 22:55:31.154311 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
932 22:55:31.158026 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
933 22:55:31.164882 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
934 22:55:31.168179 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
935 22:55:31.171045 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
936 22:55:31.174743 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
937 22:55:31.177911 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
938 22:55:31.184562 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
939 22:55:31.187505 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
940 22:55:31.191457 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
941 22:55:31.191603 ==
942 22:55:31.194320 Dram Type= 6, Freq= 0, CH_0, rank 0
943 22:55:31.197612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
944 22:55:31.201077 ==
945 22:55:31.201207 DQS Delay:
946 22:55:31.201309 DQS0 = 0, DQS1 = 0
947 22:55:31.204324 DQM Delay:
948 22:55:31.204451 DQM0 = 88, DQM1 = 75
949 22:55:31.207662 DQ Delay:
950 22:55:31.207785 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
951 22:55:31.210995 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =93
952 22:55:31.214703 DQ8 =69, DQ9 =53, DQ10 =69, DQ11 =69
953 22:55:31.217523 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
954 22:55:31.221519
955 22:55:31.221652
956 22:55:31.221753 ==
957 22:55:31.224217 Dram Type= 6, Freq= 0, CH_0, rank 0
958 22:55:31.228395 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
959 22:55:31.228534 ==
960 22:55:31.228636
961 22:55:31.228765
962 22:55:31.230847 TX Vref Scan disable
963 22:55:31.230957 == TX Byte 0 ==
964 22:55:31.238214 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
965 22:55:31.240749 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
966 22:55:31.240879 == TX Byte 1 ==
967 22:55:31.247753 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
968 22:55:31.250830 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
969 22:55:31.250970 ==
970 22:55:31.254044 Dram Type= 6, Freq= 0, CH_0, rank 0
971 22:55:31.257368 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
972 22:55:31.257502 ==
973 22:55:31.271124 TX Vref=22, minBit 0, minWin=27, winSum=440
974 22:55:31.274371 TX Vref=24, minBit 1, minWin=27, winSum=442
975 22:55:31.278303 TX Vref=26, minBit 1, minWin=27, winSum=444
976 22:55:31.281558 TX Vref=28, minBit 3, minWin=27, winSum=449
977 22:55:31.284358 TX Vref=30, minBit 6, minWin=27, winSum=449
978 22:55:31.290775 TX Vref=32, minBit 1, minWin=27, winSum=447
979 22:55:31.294277 [TxChooseVref] Worse bit 3, Min win 27, Win sum 449, Final Vref 28
980 22:55:31.294410
981 22:55:31.297968 Final TX Range 1 Vref 28
982 22:55:31.298084
983 22:55:31.298180 ==
984 22:55:31.301184 Dram Type= 6, Freq= 0, CH_0, rank 0
985 22:55:31.304352 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
986 22:55:31.304486 ==
987 22:55:31.304589
988 22:55:31.307690
989 22:55:31.307801 TX Vref Scan disable
990 22:55:31.311156 == TX Byte 0 ==
991 22:55:31.314191 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
992 22:55:31.318322 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
993 22:55:31.320693 == TX Byte 1 ==
994 22:55:31.324088 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
995 22:55:31.327463 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
996 22:55:31.331045
997 22:55:31.331186 [DATLAT]
998 22:55:31.331286 Freq=800, CH0 RK0
999 22:55:31.331380
1000 22:55:31.333981 DATLAT Default: 0xa
1001 22:55:31.334094 0, 0xFFFF, sum = 0
1002 22:55:31.337200 1, 0xFFFF, sum = 0
1003 22:55:31.337331 2, 0xFFFF, sum = 0
1004 22:55:31.340834 3, 0xFFFF, sum = 0
1005 22:55:31.343976 4, 0xFFFF, sum = 0
1006 22:55:31.344111 5, 0xFFFF, sum = 0
1007 22:55:31.347451 6, 0xFFFF, sum = 0
1008 22:55:31.347574 7, 0xFFFF, sum = 0
1009 22:55:31.350644 8, 0xFFFF, sum = 0
1010 22:55:31.350772 9, 0x0, sum = 1
1011 22:55:31.353674 10, 0x0, sum = 2
1012 22:55:31.353795 11, 0x0, sum = 3
1013 22:55:31.353894 12, 0x0, sum = 4
1014 22:55:31.357364 best_step = 10
1015 22:55:31.357482
1016 22:55:31.357579 ==
1017 22:55:31.360878 Dram Type= 6, Freq= 0, CH_0, rank 0
1018 22:55:31.364082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1019 22:55:31.364209 ==
1020 22:55:31.366928 RX Vref Scan: 1
1021 22:55:31.367042
1022 22:55:31.370162 Set Vref Range= 32 -> 127
1023 22:55:31.370277
1024 22:55:31.370375 RX Vref 32 -> 127, step: 1
1025 22:55:31.370475
1026 22:55:31.373766 RX Delay -111 -> 252, step: 8
1027 22:55:31.373879
1028 22:55:31.376882 Set Vref, RX VrefLevel [Byte0]: 32
1029 22:55:31.380150 [Byte1]: 32
1030 22:55:31.383961
1031 22:55:31.384121 Set Vref, RX VrefLevel [Byte0]: 33
1032 22:55:31.387199 [Byte1]: 33
1033 22:55:31.391297
1034 22:55:31.391420 Set Vref, RX VrefLevel [Byte0]: 34
1035 22:55:31.395254 [Byte1]: 34
1036 22:55:31.399355
1037 22:55:31.399482 Set Vref, RX VrefLevel [Byte0]: 35
1038 22:55:31.402702 [Byte1]: 35
1039 22:55:31.406648
1040 22:55:31.406784 Set Vref, RX VrefLevel [Byte0]: 36
1041 22:55:31.409806 [Byte1]: 36
1042 22:55:31.414406
1043 22:55:31.414532 Set Vref, RX VrefLevel [Byte0]: 37
1044 22:55:31.417531 [Byte1]: 37
1045 22:55:31.423552
1046 22:55:31.423719 Set Vref, RX VrefLevel [Byte0]: 38
1047 22:55:31.425921 [Byte1]: 38
1048 22:55:31.429823
1049 22:55:31.429966 Set Vref, RX VrefLevel [Byte0]: 39
1050 22:55:31.433243 [Byte1]: 39
1051 22:55:31.437659
1052 22:55:31.437824 Set Vref, RX VrefLevel [Byte0]: 40
1053 22:55:31.440930 [Byte1]: 40
1054 22:55:31.445408
1055 22:55:31.445561 Set Vref, RX VrefLevel [Byte0]: 41
1056 22:55:31.448818 [Byte1]: 41
1057 22:55:31.452768
1058 22:55:31.452916 Set Vref, RX VrefLevel [Byte0]: 42
1059 22:55:31.456336 [Byte1]: 42
1060 22:55:31.460266
1061 22:55:31.460412 Set Vref, RX VrefLevel [Byte0]: 43
1062 22:55:31.463575 [Byte1]: 43
1063 22:55:31.467950
1064 22:55:31.468138 Set Vref, RX VrefLevel [Byte0]: 44
1065 22:55:31.471018 [Byte1]: 44
1066 22:55:31.475517
1067 22:55:31.475662 Set Vref, RX VrefLevel [Byte0]: 45
1068 22:55:31.479219 [Byte1]: 45
1069 22:55:31.482970
1070 22:55:31.483102 Set Vref, RX VrefLevel [Byte0]: 46
1071 22:55:31.486788 [Byte1]: 46
1072 22:55:31.490737
1073 22:55:31.490870 Set Vref, RX VrefLevel [Byte0]: 47
1074 22:55:31.494114 [Byte1]: 47
1075 22:55:31.498271
1076 22:55:31.498402 Set Vref, RX VrefLevel [Byte0]: 48
1077 22:55:31.501833 [Byte1]: 48
1078 22:55:31.505813
1079 22:55:31.505960 Set Vref, RX VrefLevel [Byte0]: 49
1080 22:55:31.509507 [Byte1]: 49
1081 22:55:31.513793
1082 22:55:31.513933 Set Vref, RX VrefLevel [Byte0]: 50
1083 22:55:31.517036 [Byte1]: 50
1084 22:55:31.521116
1085 22:55:31.521249 Set Vref, RX VrefLevel [Byte0]: 51
1086 22:55:31.525306 [Byte1]: 51
1087 22:55:31.528730
1088 22:55:31.528857 Set Vref, RX VrefLevel [Byte0]: 52
1089 22:55:31.532213 [Byte1]: 52
1090 22:55:31.536380
1091 22:55:31.536528 Set Vref, RX VrefLevel [Byte0]: 53
1092 22:55:31.539908 [Byte1]: 53
1093 22:55:31.544337
1094 22:55:31.544477 Set Vref, RX VrefLevel [Byte0]: 54
1095 22:55:31.547872 [Byte1]: 54
1096 22:55:31.552000
1097 22:55:31.552141 Set Vref, RX VrefLevel [Byte0]: 55
1098 22:55:31.555542 [Byte1]: 55
1099 22:55:31.559626
1100 22:55:31.559763 Set Vref, RX VrefLevel [Byte0]: 56
1101 22:55:31.562801 [Byte1]: 56
1102 22:55:31.567128
1103 22:55:31.567269 Set Vref, RX VrefLevel [Byte0]: 57
1104 22:55:31.570720 [Byte1]: 57
1105 22:55:31.574810
1106 22:55:31.574953 Set Vref, RX VrefLevel [Byte0]: 58
1107 22:55:31.578902 [Byte1]: 58
1108 22:55:31.582330
1109 22:55:31.582454 Set Vref, RX VrefLevel [Byte0]: 59
1110 22:55:31.585762 [Byte1]: 59
1111 22:55:31.589995
1112 22:55:31.590124 Set Vref, RX VrefLevel [Byte0]: 60
1113 22:55:31.593853 [Byte1]: 60
1114 22:55:31.597876
1115 22:55:31.598009 Set Vref, RX VrefLevel [Byte0]: 61
1116 22:55:31.600752 [Byte1]: 61
1117 22:55:31.605164
1118 22:55:31.605318 Set Vref, RX VrefLevel [Byte0]: 62
1119 22:55:31.608669 [Byte1]: 62
1120 22:55:31.613053
1121 22:55:31.613184 Set Vref, RX VrefLevel [Byte0]: 63
1122 22:55:31.616367 [Byte1]: 63
1123 22:55:31.620880
1124 22:55:31.621017 Set Vref, RX VrefLevel [Byte0]: 64
1125 22:55:31.623865 [Byte1]: 64
1126 22:55:31.629075
1127 22:55:31.629228 Set Vref, RX VrefLevel [Byte0]: 65
1128 22:55:31.632006 [Byte1]: 65
1129 22:55:31.635723
1130 22:55:31.635866 Set Vref, RX VrefLevel [Byte0]: 66
1131 22:55:31.639130 [Byte1]: 66
1132 22:55:31.643424
1133 22:55:31.643608 Set Vref, RX VrefLevel [Byte0]: 67
1134 22:55:31.646813 [Byte1]: 67
1135 22:55:31.651281
1136 22:55:31.651431 Set Vref, RX VrefLevel [Byte0]: 68
1137 22:55:31.655086 [Byte1]: 68
1138 22:55:31.659054
1139 22:55:31.659188 Set Vref, RX VrefLevel [Byte0]: 69
1140 22:55:31.663400 [Byte1]: 69
1141 22:55:31.666494
1142 22:55:31.666624 Set Vref, RX VrefLevel [Byte0]: 70
1143 22:55:31.669989 [Byte1]: 70
1144 22:55:31.674560
1145 22:55:31.674711 Set Vref, RX VrefLevel [Byte0]: 71
1146 22:55:31.677549 [Byte1]: 71
1147 22:55:31.682005
1148 22:55:31.682153 Set Vref, RX VrefLevel [Byte0]: 72
1149 22:55:31.685436 [Byte1]: 72
1150 22:55:31.689825
1151 22:55:31.689959 Set Vref, RX VrefLevel [Byte0]: 73
1152 22:55:31.693138 [Byte1]: 73
1153 22:55:31.697054
1154 22:55:31.697188 Final RX Vref Byte 0 = 53 to rank0
1155 22:55:31.700941 Final RX Vref Byte 1 = 59 to rank0
1156 22:55:31.704078 Final RX Vref Byte 0 = 53 to rank1
1157 22:55:31.707008 Final RX Vref Byte 1 = 59 to rank1==
1158 22:55:31.710725 Dram Type= 6, Freq= 0, CH_0, rank 0
1159 22:55:31.717179 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1160 22:55:31.717350 ==
1161 22:55:31.717457 DQS Delay:
1162 22:55:31.717548 DQS0 = 0, DQS1 = 0
1163 22:55:31.720191 DQM Delay:
1164 22:55:31.720299 DQM0 = 88, DQM1 = 76
1165 22:55:31.723422 DQ Delay:
1166 22:55:31.727324 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =88
1167 22:55:31.730486 DQ4 =88, DQ5 =80, DQ6 =96, DQ7 =96
1168 22:55:31.734008 DQ8 =68, DQ9 =60, DQ10 =76, DQ11 =76
1169 22:55:31.737276 DQ12 =84, DQ13 =80, DQ14 =84, DQ15 =84
1170 22:55:31.737400
1171 22:55:31.737498
1172 22:55:31.743584 [DQSOSCAuto] RK0, (LSB)MR18= 0x322b, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 397 ps
1173 22:55:31.746857 CH0 RK0: MR19=606, MR18=322B
1174 22:55:31.753735 CH0_RK0: MR19=0x606, MR18=0x322B, DQSOSC=397, MR23=63, INC=93, DEC=62
1175 22:55:31.753882
1176 22:55:31.756827 ----->DramcWriteLeveling(PI) begin...
1177 22:55:31.756924 ==
1178 22:55:31.760349 Dram Type= 6, Freq= 0, CH_0, rank 1
1179 22:55:31.763802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1180 22:55:31.763903 ==
1181 22:55:31.766780 Write leveling (Byte 0): 31 => 31
1182 22:55:31.770647 Write leveling (Byte 1): 25 => 25
1183 22:55:31.773444 DramcWriteLeveling(PI) end<-----
1184 22:55:31.773546
1185 22:55:31.773655 ==
1186 22:55:31.777155 Dram Type= 6, Freq= 0, CH_0, rank 1
1187 22:55:31.780490 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1188 22:55:31.780592 ==
1189 22:55:31.784059 [Gating] SW mode calibration
1190 22:55:31.790388 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1191 22:55:31.797637 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1192 22:55:31.799996 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1193 22:55:31.803316 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1194 22:55:31.810315 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1195 22:55:31.813736 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 22:55:31.857864 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1197 22:55:31.858215 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1198 22:55:31.858961 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1199 22:55:31.859046 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1200 22:55:31.859574 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1201 22:55:31.860079 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1202 22:55:31.860456 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1203 22:55:31.860869 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1204 22:55:31.860954 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1205 22:55:31.861247 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1206 22:55:31.902098 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1207 22:55:31.902456 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1208 22:55:31.902547 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1209 22:55:31.902613 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1210 22:55:31.902919 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1211 22:55:31.903594 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1212 22:55:31.903933 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1213 22:55:31.904148 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1214 22:55:31.904233 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1215 22:55:31.904495 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1216 22:55:31.945541 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1217 22:55:31.945887 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
1218 22:55:31.946262 0 9 8 | B1->B0 | 2323 3434 | 1 1 | (0 0) (1 1)
1219 22:55:31.946348 0 9 12 | B1->B0 | 3333 3434 | 1 1 | (0 0) (1 1)
1220 22:55:31.946662 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1221 22:55:31.947044 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1222 22:55:31.947341 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1223 22:55:31.947616 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1224 22:55:31.947689 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1225 22:55:31.948309 0 10 4 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 1)
1226 22:55:31.961064 0 10 8 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (1 0)
1227 22:55:31.961420 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 22:55:31.964006 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 22:55:31.964121 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 22:55:31.967083 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 22:55:31.970444 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 22:55:31.977899 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 22:55:31.980729 0 11 4 | B1->B0 | 2323 3434 | 0 1 | (0 0) (0 0)
1234 22:55:31.984301 0 11 8 | B1->B0 | 3333 4646 | 0 0 | (0 0) (0 0)
1235 22:55:31.990475 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1236 22:55:31.993783 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1237 22:55:31.997076 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1238 22:55:32.001075 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1239 22:55:32.008017 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1240 22:55:32.012041 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1241 22:55:32.015182 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1242 22:55:32.018991 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1243 22:55:32.025200 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1244 22:55:32.029065 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1245 22:55:32.032860 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1246 22:55:32.039191 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1247 22:55:32.042495 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1248 22:55:32.045977 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1249 22:55:32.052754 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1250 22:55:32.056045 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1251 22:55:32.059228 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1252 22:55:32.065566 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1253 22:55:32.068949 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1254 22:55:32.072403 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1255 22:55:32.078719 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1256 22:55:32.082273 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1257 22:55:32.085831 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1258 22:55:32.088897 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1259 22:55:32.091985 Total UI for P1: 0, mck2ui 16
1260 22:55:32.095898 best dqsien dly found for B0: ( 0, 14, 4)
1261 22:55:32.102146 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1262 22:55:32.106275 Total UI for P1: 0, mck2ui 16
1263 22:55:32.109986 best dqsien dly found for B1: ( 0, 14, 8)
1264 22:55:32.112318 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1265 22:55:32.115569 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1266 22:55:32.115654
1267 22:55:32.118729 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1268 22:55:32.122034 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1269 22:55:32.125163 [Gating] SW calibration Done
1270 22:55:32.125272 ==
1271 22:55:32.128755 Dram Type= 6, Freq= 0, CH_0, rank 1
1272 22:55:32.132377 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1273 22:55:32.132461 ==
1274 22:55:32.135196 RX Vref Scan: 0
1275 22:55:32.135278
1276 22:55:32.135344 RX Vref 0 -> 0, step: 1
1277 22:55:32.138527
1278 22:55:32.138610 RX Delay -130 -> 252, step: 16
1279 22:55:32.145267 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1280 22:55:32.148582 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1281 22:55:32.151951 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1282 22:55:32.155131 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1283 22:55:32.159411 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1284 22:55:32.166231 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
1285 22:55:32.168649 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1286 22:55:32.172052 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1287 22:55:32.175214 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1288 22:55:32.178168 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1289 22:55:32.185013 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1290 22:55:32.188390 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1291 22:55:32.191848 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1292 22:55:32.194641 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1293 22:55:32.198106 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1294 22:55:32.204642 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1295 22:55:32.204737 ==
1296 22:55:32.208060 Dram Type= 6, Freq= 0, CH_0, rank 1
1297 22:55:32.211482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1298 22:55:32.211567 ==
1299 22:55:32.211633 DQS Delay:
1300 22:55:32.214793 DQS0 = 0, DQS1 = 0
1301 22:55:32.214876 DQM Delay:
1302 22:55:32.218175 DQM0 = 85, DQM1 = 76
1303 22:55:32.218259 DQ Delay:
1304 22:55:32.221384 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =85
1305 22:55:32.224770 DQ4 =85, DQ5 =77, DQ6 =93, DQ7 =93
1306 22:55:32.227993 DQ8 =69, DQ9 =61, DQ10 =69, DQ11 =69
1307 22:55:32.231163 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1308 22:55:32.231246
1309 22:55:32.231312
1310 22:55:32.231373 ==
1311 22:55:32.234633 Dram Type= 6, Freq= 0, CH_0, rank 1
1312 22:55:32.238522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1313 22:55:32.241354 ==
1314 22:55:32.241439
1315 22:55:32.241504
1316 22:55:32.241565 TX Vref Scan disable
1317 22:55:32.244415 == TX Byte 0 ==
1318 22:55:32.248261 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1319 22:55:32.251950 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1320 22:55:32.254463 == TX Byte 1 ==
1321 22:55:32.258124 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1322 22:55:32.261288 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1323 22:55:32.264592 ==
1324 22:55:32.267986 Dram Type= 6, Freq= 0, CH_0, rank 1
1325 22:55:32.270789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1326 22:55:32.270873 ==
1327 22:55:32.284414 TX Vref=22, minBit 1, minWin=27, winSum=443
1328 22:55:32.287142 TX Vref=24, minBit 0, minWin=27, winSum=442
1329 22:55:32.290636 TX Vref=26, minBit 2, minWin=27, winSum=449
1330 22:55:32.294090 TX Vref=28, minBit 1, minWin=27, winSum=450
1331 22:55:32.296980 TX Vref=30, minBit 9, minWin=27, winSum=451
1332 22:55:32.300446 TX Vref=32, minBit 1, minWin=27, winSum=452
1333 22:55:32.307698 [TxChooseVref] Worse bit 1, Min win 27, Win sum 452, Final Vref 32
1334 22:55:32.307809
1335 22:55:32.310418 Final TX Range 1 Vref 32
1336 22:55:32.310532
1337 22:55:32.310603 ==
1338 22:55:32.313976 Dram Type= 6, Freq= 0, CH_0, rank 1
1339 22:55:32.317148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1340 22:55:32.317234 ==
1341 22:55:32.317301
1342 22:55:32.320741
1343 22:55:32.320826 TX Vref Scan disable
1344 22:55:32.323999 == TX Byte 0 ==
1345 22:55:32.327084 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1346 22:55:32.333856 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1347 22:55:32.333950 == TX Byte 1 ==
1348 22:55:32.337219 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1349 22:55:32.343735 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1350 22:55:32.343822
1351 22:55:32.343887 [DATLAT]
1352 22:55:32.343948 Freq=800, CH0 RK1
1353 22:55:32.344007
1354 22:55:32.347295 DATLAT Default: 0xa
1355 22:55:32.347377 0, 0xFFFF, sum = 0
1356 22:55:32.350666 1, 0xFFFF, sum = 0
1357 22:55:32.350749 2, 0xFFFF, sum = 0
1358 22:55:32.353879 3, 0xFFFF, sum = 0
1359 22:55:32.353962 4, 0xFFFF, sum = 0
1360 22:55:32.357472 5, 0xFFFF, sum = 0
1361 22:55:32.360715 6, 0xFFFF, sum = 0
1362 22:55:32.360799 7, 0xFFFF, sum = 0
1363 22:55:32.363981 8, 0xFFFF, sum = 0
1364 22:55:32.364085 9, 0x0, sum = 1
1365 22:55:32.364152 10, 0x0, sum = 2
1366 22:55:32.367083 11, 0x0, sum = 3
1367 22:55:32.367166 12, 0x0, sum = 4
1368 22:55:32.370625 best_step = 10
1369 22:55:32.370706
1370 22:55:32.370771 ==
1371 22:55:32.373948 Dram Type= 6, Freq= 0, CH_0, rank 1
1372 22:55:32.377288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1373 22:55:32.377375 ==
1374 22:55:32.381008 RX Vref Scan: 0
1375 22:55:32.381089
1376 22:55:32.381155 RX Vref 0 -> 0, step: 1
1377 22:55:32.381216
1378 22:55:32.383808 RX Delay -95 -> 252, step: 8
1379 22:55:32.390545 iDelay=209, Bit 0, Center 84 (-23 ~ 192) 216
1380 22:55:32.393691 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1381 22:55:32.397371 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1382 22:55:32.400396 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1383 22:55:32.404038 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1384 22:55:32.410919 iDelay=209, Bit 5, Center 80 (-31 ~ 192) 224
1385 22:55:32.413757 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1386 22:55:32.417092 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1387 22:55:32.420616 iDelay=209, Bit 8, Center 64 (-47 ~ 176) 224
1388 22:55:32.423348 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1389 22:55:32.430214 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1390 22:55:32.434201 iDelay=209, Bit 11, Center 72 (-39 ~ 184) 224
1391 22:55:32.436657 iDelay=209, Bit 12, Center 84 (-31 ~ 200) 232
1392 22:55:32.440836 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1393 22:55:32.446619 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1394 22:55:32.449825 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1395 22:55:32.449908 ==
1396 22:55:32.453084 Dram Type= 6, Freq= 0, CH_0, rank 1
1397 22:55:32.456776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1398 22:55:32.456859 ==
1399 22:55:32.459985 DQS Delay:
1400 22:55:32.460094 DQS0 = 0, DQS1 = 0
1401 22:55:32.460160 DQM Delay:
1402 22:55:32.463067 DQM0 = 86, DQM1 = 77
1403 22:55:32.463148 DQ Delay:
1404 22:55:32.466469 DQ0 =84, DQ1 =88, DQ2 =80, DQ3 =80
1405 22:55:32.470429 DQ4 =88, DQ5 =80, DQ6 =96, DQ7 =96
1406 22:55:32.473560 DQ8 =64, DQ9 =64, DQ10 =80, DQ11 =72
1407 22:55:32.476535 DQ12 =84, DQ13 =80, DQ14 =88, DQ15 =84
1408 22:55:32.476618
1409 22:55:32.476682
1410 22:55:32.487297 [DQSOSCAuto] RK1, (LSB)MR18= 0x2f2b, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 397 ps
1411 22:55:32.487386 CH0 RK1: MR19=606, MR18=2F2B
1412 22:55:32.493160 CH0_RK1: MR19=0x606, MR18=0x2F2B, DQSOSC=397, MR23=63, INC=93, DEC=62
1413 22:55:32.496562 [RxdqsGatingPostProcess] freq 800
1414 22:55:32.503211 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1415 22:55:32.506186 Pre-setting of DQS Precalculation
1416 22:55:32.509876 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1417 22:55:32.509962 ==
1418 22:55:32.513504 Dram Type= 6, Freq= 0, CH_1, rank 0
1419 22:55:32.519695 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1420 22:55:32.519786 ==
1421 22:55:32.523162 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1422 22:55:32.529491 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1423 22:55:32.538762 [CA 0] Center 36 (6~67) winsize 62
1424 22:55:32.542430 [CA 1] Center 37 (6~68) winsize 63
1425 22:55:32.545347 [CA 2] Center 35 (4~66) winsize 63
1426 22:55:32.548741 [CA 3] Center 34 (4~65) winsize 62
1427 22:55:32.552299 [CA 4] Center 35 (4~66) winsize 63
1428 22:55:32.555821 [CA 5] Center 34 (4~65) winsize 62
1429 22:55:32.555903
1430 22:55:32.558761 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1431 22:55:32.558843
1432 22:55:32.562420 [CATrainingPosCal] consider 1 rank data
1433 22:55:32.565491 u2DelayCellTimex100 = 270/100 ps
1434 22:55:32.569217 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1435 22:55:32.575505 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
1436 22:55:32.578621 CA2 delay=35 (4~66),Diff = 1 PI (7 cell)
1437 22:55:32.582199 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1438 22:55:32.585393 CA4 delay=35 (4~66),Diff = 1 PI (7 cell)
1439 22:55:32.589165 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1440 22:55:32.589250
1441 22:55:32.591687 CA PerBit enable=1, Macro0, CA PI delay=34
1442 22:55:32.591771
1443 22:55:32.595065 [CBTSetCACLKResult] CA Dly = 34
1444 22:55:32.598342 CS Dly: 5 (0~36)
1445 22:55:32.598426 ==
1446 22:55:32.601557 Dram Type= 6, Freq= 0, CH_1, rank 1
1447 22:55:32.606101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1448 22:55:32.606193 ==
1449 22:55:32.611806 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1450 22:55:32.615044 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1451 22:55:32.624874 [CA 0] Center 36 (6~67) winsize 62
1452 22:55:32.628228 [CA 1] Center 36 (6~67) winsize 62
1453 22:55:32.631817 [CA 2] Center 35 (5~66) winsize 62
1454 22:55:32.635153 [CA 3] Center 34 (4~65) winsize 62
1455 22:55:32.638021 [CA 4] Center 34 (4~65) winsize 62
1456 22:55:32.641409 [CA 5] Center 34 (4~65) winsize 62
1457 22:55:32.641493
1458 22:55:32.644947 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1459 22:55:32.645032
1460 22:55:32.648379 [CATrainingPosCal] consider 2 rank data
1461 22:55:32.651550 u2DelayCellTimex100 = 270/100 ps
1462 22:55:32.654892 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1463 22:55:32.661565 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1464 22:55:32.665191 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1465 22:55:32.668718 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1466 22:55:32.672068 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1467 22:55:32.676164 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1468 22:55:32.676251
1469 22:55:32.679381 CA PerBit enable=1, Macro0, CA PI delay=34
1470 22:55:32.679466
1471 22:55:32.683421 [CBTSetCACLKResult] CA Dly = 34
1472 22:55:32.683506 CS Dly: 5 (0~37)
1473 22:55:32.683574
1474 22:55:32.687539 ----->DramcWriteLeveling(PI) begin...
1475 22:55:32.687626 ==
1476 22:55:32.690877 Dram Type= 6, Freq= 0, CH_1, rank 0
1477 22:55:32.694574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1478 22:55:32.694667 ==
1479 22:55:32.698351 Write leveling (Byte 0): 26 => 26
1480 22:55:32.701844 Write leveling (Byte 1): 27 => 27
1481 22:55:32.701934 DramcWriteLeveling(PI) end<-----
1482 22:55:32.704954
1483 22:55:32.705076 ==
1484 22:55:32.709054 Dram Type= 6, Freq= 0, CH_1, rank 0
1485 22:55:32.711579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1486 22:55:32.711666 ==
1487 22:55:32.715086 [Gating] SW mode calibration
1488 22:55:32.721698 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1489 22:55:32.724753 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1490 22:55:32.731637 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1491 22:55:32.735169 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1492 22:55:32.738433 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 22:55:32.744832 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 22:55:32.748197 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1495 22:55:32.751167 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1496 22:55:32.758002 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1497 22:55:32.761252 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1498 22:55:32.765167 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1499 22:55:32.771185 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1500 22:55:32.774696 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1501 22:55:32.777948 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1502 22:55:32.784527 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1503 22:55:32.787574 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1504 22:55:32.791443 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1505 22:55:32.798363 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1506 22:55:32.800808 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1507 22:55:32.804547 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1508 22:55:32.811617 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1509 22:55:32.814446 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1510 22:55:32.817821 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1511 22:55:32.824485 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1512 22:55:32.827761 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1513 22:55:32.831357 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1514 22:55:32.838314 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1515 22:55:32.841151 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1516 22:55:32.844449 0 9 8 | B1->B0 | 2c2c 3333 | 1 0 | (1 1) (0 0)
1517 22:55:32.850970 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1518 22:55:32.854653 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1519 22:55:32.858174 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1520 22:55:32.864596 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1521 22:55:32.867903 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1522 22:55:32.871593 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1523 22:55:32.877721 0 10 4 | B1->B0 | 3434 3232 | 0 0 | (0 1) (0 0)
1524 22:55:32.881778 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1525 22:55:32.884291 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 22:55:32.887450 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 22:55:32.894305 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 22:55:32.897647 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 22:55:32.900604 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 22:55:32.908009 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 22:55:32.910565 0 11 4 | B1->B0 | 2727 3434 | 0 0 | (0 0) (0 0)
1532 22:55:32.914174 0 11 8 | B1->B0 | 3d3d 4343 | 0 0 | (1 1) (0 0)
1533 22:55:32.920587 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1534 22:55:32.923932 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1535 22:55:32.927068 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1536 22:55:32.933976 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1537 22:55:32.937516 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1538 22:55:32.940843 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1539 22:55:32.947512 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1540 22:55:32.950786 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1541 22:55:32.953919 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1542 22:55:32.960349 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1543 22:55:32.963753 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1544 22:55:32.967072 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1545 22:55:32.974648 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1546 22:55:32.977060 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1547 22:55:32.980444 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1548 22:55:32.987482 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1549 22:55:32.990585 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1550 22:55:32.993964 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1551 22:55:33.000367 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1552 22:55:33.003465 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1553 22:55:33.007398 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1554 22:55:33.013307 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1555 22:55:33.016754 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1556 22:55:33.019846 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1557 22:55:33.026568 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1558 22:55:33.026721 Total UI for P1: 0, mck2ui 16
1559 22:55:33.033310 best dqsien dly found for B0: ( 0, 14, 6)
1560 22:55:33.033406 Total UI for P1: 0, mck2ui 16
1561 22:55:33.039672 best dqsien dly found for B1: ( 0, 14, 6)
1562 22:55:33.042987 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1563 22:55:33.046466 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1564 22:55:33.046557
1565 22:55:33.049658 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1566 22:55:33.052772 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1567 22:55:33.056284 [Gating] SW calibration Done
1568 22:55:33.056372 ==
1569 22:55:33.059314 Dram Type= 6, Freq= 0, CH_1, rank 0
1570 22:55:33.062802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1571 22:55:33.062890 ==
1572 22:55:33.066102 RX Vref Scan: 0
1573 22:55:33.066189
1574 22:55:33.066255 RX Vref 0 -> 0, step: 1
1575 22:55:33.066317
1576 22:55:33.069835 RX Delay -130 -> 252, step: 16
1577 22:55:33.073112 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1578 22:55:33.079694 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1579 22:55:33.082552 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1580 22:55:33.085917 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1581 22:55:33.089193 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1582 22:55:33.092947 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1583 22:55:33.099303 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1584 22:55:33.102688 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1585 22:55:33.106338 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1586 22:55:33.109173 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1587 22:55:33.112620 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1588 22:55:33.119032 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1589 22:55:33.122654 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1590 22:55:33.125751 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1591 22:55:33.129055 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1592 22:55:33.136282 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1593 22:55:33.136381 ==
1594 22:55:33.139616 Dram Type= 6, Freq= 0, CH_1, rank 0
1595 22:55:33.142755 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1596 22:55:33.142844 ==
1597 22:55:33.142912 DQS Delay:
1598 22:55:33.145718 DQS0 = 0, DQS1 = 0
1599 22:55:33.145803 DQM Delay:
1600 22:55:33.149061 DQM0 = 89, DQM1 = 82
1601 22:55:33.149146 DQ Delay:
1602 22:55:33.152287 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =85
1603 22:55:33.156473 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1604 22:55:33.159073 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =77
1605 22:55:33.162398 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1606 22:55:33.162485
1607 22:55:33.162552
1608 22:55:33.162613 ==
1609 22:55:33.165643 Dram Type= 6, Freq= 0, CH_1, rank 0
1610 22:55:33.169346 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1611 22:55:33.169435 ==
1612 22:55:33.169502
1613 22:55:33.169564
1614 22:55:33.172982 TX Vref Scan disable
1615 22:55:33.176141 == TX Byte 0 ==
1616 22:55:33.179415 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1617 22:55:33.182444 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1618 22:55:33.185807 == TX Byte 1 ==
1619 22:55:33.188990 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1620 22:55:33.193212 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1621 22:55:33.193303 ==
1622 22:55:33.195921 Dram Type= 6, Freq= 0, CH_1, rank 0
1623 22:55:33.202303 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1624 22:55:33.202401 ==
1625 22:55:33.213978 TX Vref=22, minBit 0, minWin=26, winSum=439
1626 22:55:33.217524 TX Vref=24, minBit 2, minWin=26, winSum=444
1627 22:55:33.220707 TX Vref=26, minBit 1, minWin=27, winSum=449
1628 22:55:33.224457 TX Vref=28, minBit 3, minWin=27, winSum=454
1629 22:55:33.227331 TX Vref=30, minBit 0, minWin=28, winSum=456
1630 22:55:33.231216 TX Vref=32, minBit 1, minWin=27, winSum=450
1631 22:55:33.237829 [TxChooseVref] Worse bit 0, Min win 28, Win sum 456, Final Vref 30
1632 22:55:33.237926
1633 22:55:33.241139 Final TX Range 1 Vref 30
1634 22:55:33.241227
1635 22:55:33.241293 ==
1636 22:55:33.244147 Dram Type= 6, Freq= 0, CH_1, rank 0
1637 22:55:33.248568 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1638 22:55:33.248659 ==
1639 22:55:33.248727
1640 22:55:33.248789
1641 22:55:33.251706 TX Vref Scan disable
1642 22:55:33.254806 == TX Byte 0 ==
1643 22:55:33.257993 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1644 22:55:33.261225 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1645 22:55:33.264947 == TX Byte 1 ==
1646 22:55:33.267982 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1647 22:55:33.271039 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1648 22:55:33.271125
1649 22:55:33.275300 [DATLAT]
1650 22:55:33.275386 Freq=800, CH1 RK0
1651 22:55:33.275453
1652 22:55:33.278205 DATLAT Default: 0xa
1653 22:55:33.278287 0, 0xFFFF, sum = 0
1654 22:55:33.281231 1, 0xFFFF, sum = 0
1655 22:55:33.281316 2, 0xFFFF, sum = 0
1656 22:55:33.285486 3, 0xFFFF, sum = 0
1657 22:55:33.285570 4, 0xFFFF, sum = 0
1658 22:55:33.288058 5, 0xFFFF, sum = 0
1659 22:55:33.288157 6, 0xFFFF, sum = 0
1660 22:55:33.290979 7, 0xFFFF, sum = 0
1661 22:55:33.291063 8, 0xFFFF, sum = 0
1662 22:55:33.294224 9, 0x0, sum = 1
1663 22:55:33.294307 10, 0x0, sum = 2
1664 22:55:33.297873 11, 0x0, sum = 3
1665 22:55:33.297957 12, 0x0, sum = 4
1666 22:55:33.300964 best_step = 10
1667 22:55:33.301046
1668 22:55:33.301110 ==
1669 22:55:33.304345 Dram Type= 6, Freq= 0, CH_1, rank 0
1670 22:55:33.307863 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1671 22:55:33.307979 ==
1672 22:55:33.310808 RX Vref Scan: 1
1673 22:55:33.310892
1674 22:55:33.310957 Set Vref Range= 32 -> 127
1675 22:55:33.311018
1676 22:55:33.314458 RX Vref 32 -> 127, step: 1
1677 22:55:33.314541
1678 22:55:33.317754 RX Delay -79 -> 252, step: 8
1679 22:55:33.317837
1680 22:55:33.320732 Set Vref, RX VrefLevel [Byte0]: 32
1681 22:55:33.324443 [Byte1]: 32
1682 22:55:33.324526
1683 22:55:33.327355 Set Vref, RX VrefLevel [Byte0]: 33
1684 22:55:33.331108 [Byte1]: 33
1685 22:55:33.334327
1686 22:55:33.334412 Set Vref, RX VrefLevel [Byte0]: 34
1687 22:55:33.337552 [Byte1]: 34
1688 22:55:33.341744
1689 22:55:33.341834 Set Vref, RX VrefLevel [Byte0]: 35
1690 22:55:33.345261 [Byte1]: 35
1691 22:55:33.348914
1692 22:55:33.349002 Set Vref, RX VrefLevel [Byte0]: 36
1693 22:55:33.352220 [Byte1]: 36
1694 22:55:33.357448
1695 22:55:33.357546 Set Vref, RX VrefLevel [Byte0]: 37
1696 22:55:33.360004 [Byte1]: 37
1697 22:55:33.364337
1698 22:55:33.364428 Set Vref, RX VrefLevel [Byte0]: 38
1699 22:55:33.367457 [Byte1]: 38
1700 22:55:33.371655
1701 22:55:33.371748 Set Vref, RX VrefLevel [Byte0]: 39
1702 22:55:33.375406 [Byte1]: 39
1703 22:55:33.379566
1704 22:55:33.379695 Set Vref, RX VrefLevel [Byte0]: 40
1705 22:55:33.382665 [Byte1]: 40
1706 22:55:33.386752
1707 22:55:33.386845 Set Vref, RX VrefLevel [Byte0]: 41
1708 22:55:33.390172 [Byte1]: 41
1709 22:55:33.394759
1710 22:55:33.394850 Set Vref, RX VrefLevel [Byte0]: 42
1711 22:55:33.397636 [Byte1]: 42
1712 22:55:33.402113
1713 22:55:33.402201 Set Vref, RX VrefLevel [Byte0]: 43
1714 22:55:33.405731 [Byte1]: 43
1715 22:55:33.409343
1716 22:55:33.409433 Set Vref, RX VrefLevel [Byte0]: 44
1717 22:55:33.412810 [Byte1]: 44
1718 22:55:33.417351
1719 22:55:33.417442 Set Vref, RX VrefLevel [Byte0]: 45
1720 22:55:33.420377 [Byte1]: 45
1721 22:55:33.424905
1722 22:55:33.424993 Set Vref, RX VrefLevel [Byte0]: 46
1723 22:55:33.427886 [Byte1]: 46
1724 22:55:33.432579
1725 22:55:33.432663 Set Vref, RX VrefLevel [Byte0]: 47
1726 22:55:33.435678 [Byte1]: 47
1727 22:55:33.439774
1728 22:55:33.439880 Set Vref, RX VrefLevel [Byte0]: 48
1729 22:55:33.443022 [Byte1]: 48
1730 22:55:33.447406
1731 22:55:33.447492 Set Vref, RX VrefLevel [Byte0]: 49
1732 22:55:33.450793 [Byte1]: 49
1733 22:55:33.455350
1734 22:55:33.455440 Set Vref, RX VrefLevel [Byte0]: 50
1735 22:55:33.458069 [Byte1]: 50
1736 22:55:33.462231
1737 22:55:33.462319 Set Vref, RX VrefLevel [Byte0]: 51
1738 22:55:33.465627 [Byte1]: 51
1739 22:55:33.469955
1740 22:55:33.470045 Set Vref, RX VrefLevel [Byte0]: 52
1741 22:55:33.473419 [Byte1]: 52
1742 22:55:33.477948
1743 22:55:33.478042 Set Vref, RX VrefLevel [Byte0]: 53
1744 22:55:33.480799 [Byte1]: 53
1745 22:55:33.485052
1746 22:55:33.485139 Set Vref, RX VrefLevel [Byte0]: 54
1747 22:55:33.488630 [Byte1]: 54
1748 22:55:33.492350
1749 22:55:33.492442 Set Vref, RX VrefLevel [Byte0]: 55
1750 22:55:33.495927 [Byte1]: 55
1751 22:55:33.500019
1752 22:55:33.500133 Set Vref, RX VrefLevel [Byte0]: 56
1753 22:55:33.503626 [Byte1]: 56
1754 22:55:33.507731
1755 22:55:33.507827 Set Vref, RX VrefLevel [Byte0]: 57
1756 22:55:33.510745 [Byte1]: 57
1757 22:55:33.515087
1758 22:55:33.515175 Set Vref, RX VrefLevel [Byte0]: 58
1759 22:55:33.519226 [Byte1]: 58
1760 22:55:33.523026
1761 22:55:33.523114 Set Vref, RX VrefLevel [Byte0]: 59
1762 22:55:33.526048 [Byte1]: 59
1763 22:55:33.530194
1764 22:55:33.530281 Set Vref, RX VrefLevel [Byte0]: 60
1765 22:55:33.533646 [Byte1]: 60
1766 22:55:33.538017
1767 22:55:33.538107 Set Vref, RX VrefLevel [Byte0]: 61
1768 22:55:33.541088 [Byte1]: 61
1769 22:55:33.545716
1770 22:55:33.545806 Set Vref, RX VrefLevel [Byte0]: 62
1771 22:55:33.548533 [Byte1]: 62
1772 22:55:33.553395
1773 22:55:33.553487 Set Vref, RX VrefLevel [Byte0]: 63
1774 22:55:33.556490 [Byte1]: 63
1775 22:55:33.560687
1776 22:55:33.560773 Set Vref, RX VrefLevel [Byte0]: 64
1777 22:55:33.563767 [Byte1]: 64
1778 22:55:33.568752
1779 22:55:33.568841 Set Vref, RX VrefLevel [Byte0]: 65
1780 22:55:33.571306 [Byte1]: 65
1781 22:55:33.575932
1782 22:55:33.576019 Set Vref, RX VrefLevel [Byte0]: 66
1783 22:55:33.579288 [Byte1]: 66
1784 22:55:33.583122
1785 22:55:33.583210 Set Vref, RX VrefLevel [Byte0]: 67
1786 22:55:33.586376 [Byte1]: 67
1787 22:55:33.590597
1788 22:55:33.590684 Set Vref, RX VrefLevel [Byte0]: 68
1789 22:55:33.594089 [Byte1]: 68
1790 22:55:33.598435
1791 22:55:33.598530 Set Vref, RX VrefLevel [Byte0]: 69
1792 22:55:33.602694 [Byte1]: 69
1793 22:55:33.605959
1794 22:55:33.609163 Set Vref, RX VrefLevel [Byte0]: 70
1795 22:55:33.611949 [Byte1]: 70
1796 22:55:33.612062
1797 22:55:33.615606 Set Vref, RX VrefLevel [Byte0]: 71
1798 22:55:33.618854 [Byte1]: 71
1799 22:55:33.618941
1800 22:55:33.622073 Set Vref, RX VrefLevel [Byte0]: 72
1801 22:55:33.625293 [Byte1]: 72
1802 22:55:33.625379
1803 22:55:33.629151 Set Vref, RX VrefLevel [Byte0]: 73
1804 22:55:33.632384 [Byte1]: 73
1805 22:55:33.636159
1806 22:55:33.636243 Final RX Vref Byte 0 = 60 to rank0
1807 22:55:33.639117 Final RX Vref Byte 1 = 58 to rank0
1808 22:55:33.642431 Final RX Vref Byte 0 = 60 to rank1
1809 22:55:33.646007 Final RX Vref Byte 1 = 58 to rank1==
1810 22:55:33.649886 Dram Type= 6, Freq= 0, CH_1, rank 0
1811 22:55:33.655720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1812 22:55:33.655809 ==
1813 22:55:33.655877 DQS Delay:
1814 22:55:33.658996 DQS0 = 0, DQS1 = 0
1815 22:55:33.659080 DQM Delay:
1816 22:55:33.659146 DQM0 = 87, DQM1 = 81
1817 22:55:33.662312 DQ Delay:
1818 22:55:33.665787 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1819 22:55:33.669494 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =84
1820 22:55:33.672397 DQ8 =72, DQ9 =72, DQ10 =80, DQ11 =72
1821 22:55:33.675403 DQ12 =88, DQ13 =92, DQ14 =88, DQ15 =88
1822 22:55:33.675488
1823 22:55:33.675553
1824 22:55:33.682290 [DQSOSCAuto] RK0, (LSB)MR18= 0x1d30, (MSB)MR19= 0x606, tDQSOscB0 = 397 ps tDQSOscB1 = 402 ps
1825 22:55:33.685875 CH1 RK0: MR19=606, MR18=1D30
1826 22:55:33.691960 CH1_RK0: MR19=0x606, MR18=0x1D30, DQSOSC=397, MR23=63, INC=93, DEC=62
1827 22:55:33.692070
1828 22:55:33.695438 ----->DramcWriteLeveling(PI) begin...
1829 22:55:33.695528 ==
1830 22:55:33.698520 Dram Type= 6, Freq= 0, CH_1, rank 1
1831 22:55:33.701900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1832 22:55:33.701990 ==
1833 22:55:33.705156 Write leveling (Byte 0): 28 => 28
1834 22:55:33.708518 Write leveling (Byte 1): 28 => 28
1835 22:55:33.712327 DramcWriteLeveling(PI) end<-----
1836 22:55:33.712428
1837 22:55:33.712494 ==
1838 22:55:33.715332 Dram Type= 6, Freq= 0, CH_1, rank 1
1839 22:55:33.718463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1840 22:55:33.718551 ==
1841 22:55:33.722212 [Gating] SW mode calibration
1842 22:55:33.728678 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1843 22:55:33.735679 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1844 22:55:33.738565 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1845 22:55:33.745367 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1846 22:55:33.748260 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 22:55:33.753085 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 22:55:33.758422 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 22:55:33.761814 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 22:55:33.765341 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 22:55:33.771625 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 22:55:33.774775 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 22:55:33.779406 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 22:55:33.781863 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 22:55:33.788511 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 22:55:33.792364 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1857 22:55:33.795005 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 22:55:33.801851 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 22:55:33.805259 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1860 22:55:33.807916 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1861 22:55:33.814660 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1862 22:55:33.818083 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1863 22:55:33.821857 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1864 22:55:33.827977 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1865 22:55:33.831490 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1866 22:55:33.834881 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1867 22:55:33.841132 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1868 22:55:33.844668 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1869 22:55:33.847953 0 9 4 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (1 1)
1870 22:55:33.855144 0 9 8 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
1871 22:55:33.858066 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1872 22:55:33.861829 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1873 22:55:33.868198 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1874 22:55:33.871677 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1875 22:55:33.874664 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1876 22:55:33.881627 0 10 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1877 22:55:33.884990 0 10 4 | B1->B0 | 3434 2e2e | 0 1 | (0 1) (1 0)
1878 22:55:33.888187 0 10 8 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
1879 22:55:33.894745 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 22:55:33.897902 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 22:55:33.901188 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 22:55:33.907813 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 22:55:33.911037 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 22:55:33.914570 0 11 0 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
1885 22:55:33.921071 0 11 4 | B1->B0 | 2727 3c3c | 0 0 | (0 0) (0 0)
1886 22:55:33.924221 0 11 8 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
1887 22:55:33.927664 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1888 22:55:33.935119 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1889 22:55:33.937801 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1890 22:55:33.940897 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1891 22:55:33.948054 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1892 22:55:33.951432 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1893 22:55:33.954231 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1894 22:55:33.957425 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1895 22:55:33.964616 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1896 22:55:33.967433 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1897 22:55:33.971005 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1898 22:55:33.977704 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1899 22:55:33.981331 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1900 22:55:33.984456 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1901 22:55:33.991602 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1902 22:55:33.994113 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1903 22:55:33.997423 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1904 22:55:34.004206 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1905 22:55:34.007782 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1906 22:55:34.010899 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1907 22:55:34.017706 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1908 22:55:34.021030 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1909 22:55:34.024383 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1910 22:55:34.027640 Total UI for P1: 0, mck2ui 16
1911 22:55:34.030887 best dqsien dly found for B0: ( 0, 14, 0)
1912 22:55:34.037493 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1913 22:55:34.037593 Total UI for P1: 0, mck2ui 16
1914 22:55:34.040610 best dqsien dly found for B1: ( 0, 14, 4)
1915 22:55:34.047346 best DQS0 dly(MCK, UI, PI) = (0, 14, 0)
1916 22:55:34.050797 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1917 22:55:34.050893
1918 22:55:34.053859 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 0)
1919 22:55:34.057587 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1920 22:55:34.060974 [Gating] SW calibration Done
1921 22:55:34.061064 ==
1922 22:55:34.064325 Dram Type= 6, Freq= 0, CH_1, rank 1
1923 22:55:34.067337 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1924 22:55:34.067424 ==
1925 22:55:34.070355 RX Vref Scan: 0
1926 22:55:34.070441
1927 22:55:34.070509 RX Vref 0 -> 0, step: 1
1928 22:55:34.070571
1929 22:55:34.073933 RX Delay -130 -> 252, step: 16
1930 22:55:34.077527 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1931 22:55:34.083747 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1932 22:55:34.087304 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1933 22:55:34.090542 iDelay=206, Bit 3, Center 77 (-34 ~ 189) 224
1934 22:55:34.093572 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1935 22:55:34.097486 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1936 22:55:34.103809 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1937 22:55:34.107256 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1938 22:55:34.110523 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1939 22:55:34.114037 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1940 22:55:34.116823 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1941 22:55:34.123585 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1942 22:55:34.127158 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1943 22:55:34.129974 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1944 22:55:34.133897 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1945 22:55:34.136736 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1946 22:55:34.140142 ==
1947 22:55:34.143760 Dram Type= 6, Freq= 0, CH_1, rank 1
1948 22:55:34.146823 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1949 22:55:34.146911 ==
1950 22:55:34.146978 DQS Delay:
1951 22:55:34.149912 DQS0 = 0, DQS1 = 0
1952 22:55:34.149996 DQM Delay:
1953 22:55:34.153622 DQM0 = 83, DQM1 = 80
1954 22:55:34.153706 DQ Delay:
1955 22:55:34.156895 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =77
1956 22:55:34.159773 DQ4 =85, DQ5 =93, DQ6 =85, DQ7 =85
1957 22:55:34.163070 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1958 22:55:34.166595 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1959 22:55:34.166682
1960 22:55:34.166748
1961 22:55:34.166808 ==
1962 22:55:34.169822 Dram Type= 6, Freq= 0, CH_1, rank 1
1963 22:55:34.173280 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1964 22:55:34.173366 ==
1965 22:55:34.173431
1966 22:55:34.173492
1967 22:55:34.176942 TX Vref Scan disable
1968 22:55:34.180156 == TX Byte 0 ==
1969 22:55:34.183101 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1970 22:55:34.186729 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1971 22:55:34.189782 == TX Byte 1 ==
1972 22:55:34.193656 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1973 22:55:34.196741 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1974 22:55:34.196828 ==
1975 22:55:34.200426 Dram Type= 6, Freq= 0, CH_1, rank 1
1976 22:55:34.206360 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1977 22:55:34.206455 ==
1978 22:55:34.217927 TX Vref=22, minBit 4, minWin=26, winSum=443
1979 22:55:34.220854 TX Vref=24, minBit 0, minWin=27, winSum=447
1980 22:55:34.224480 TX Vref=26, minBit 1, minWin=27, winSum=449
1981 22:55:34.227933 TX Vref=28, minBit 5, minWin=27, winSum=452
1982 22:55:34.230890 TX Vref=30, minBit 5, minWin=27, winSum=453
1983 22:55:34.237438 TX Vref=32, minBit 0, minWin=27, winSum=450
1984 22:55:34.240724 [TxChooseVref] Worse bit 5, Min win 27, Win sum 453, Final Vref 30
1985 22:55:34.240820
1986 22:55:34.244477 Final TX Range 1 Vref 30
1987 22:55:34.244565
1988 22:55:34.244630 ==
1989 22:55:34.247507 Dram Type= 6, Freq= 0, CH_1, rank 1
1990 22:55:34.250856 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1991 22:55:34.250943 ==
1992 22:55:34.251008
1993 22:55:34.254331
1994 22:55:34.254416 TX Vref Scan disable
1995 22:55:34.257715 == TX Byte 0 ==
1996 22:55:34.261392 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1997 22:55:34.264814 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1998 22:55:34.267779 == TX Byte 1 ==
1999 22:55:34.271143 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2000 22:55:34.274489 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2001 22:55:34.277610
2002 22:55:34.277696 [DATLAT]
2003 22:55:34.277762 Freq=800, CH1 RK1
2004 22:55:34.277824
2005 22:55:34.281281 DATLAT Default: 0xa
2006 22:55:34.281369 0, 0xFFFF, sum = 0
2007 22:55:34.284240 1, 0xFFFF, sum = 0
2008 22:55:34.284326 2, 0xFFFF, sum = 0
2009 22:55:34.287502 3, 0xFFFF, sum = 0
2010 22:55:34.291043 4, 0xFFFF, sum = 0
2011 22:55:34.291130 5, 0xFFFF, sum = 0
2012 22:55:34.294323 6, 0xFFFF, sum = 0
2013 22:55:34.294409 7, 0xFFFF, sum = 0
2014 22:55:34.297470 8, 0xFFFF, sum = 0
2015 22:55:34.297557 9, 0x0, sum = 1
2016 22:55:34.301112 10, 0x0, sum = 2
2017 22:55:34.301198 11, 0x0, sum = 3
2018 22:55:34.301264 12, 0x0, sum = 4
2019 22:55:34.304257 best_step = 10
2020 22:55:34.304341
2021 22:55:34.304406 ==
2022 22:55:34.307770 Dram Type= 6, Freq= 0, CH_1, rank 1
2023 22:55:34.310513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2024 22:55:34.310602 ==
2025 22:55:34.313880 RX Vref Scan: 0
2026 22:55:34.313964
2027 22:55:34.314029 RX Vref 0 -> 0, step: 1
2028 22:55:34.317317
2029 22:55:34.317416 RX Delay -95 -> 252, step: 8
2030 22:55:34.324240 iDelay=209, Bit 0, Center 92 (-23 ~ 208) 232
2031 22:55:34.328195 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
2032 22:55:34.331116 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
2033 22:55:34.334098 iDelay=209, Bit 3, Center 84 (-23 ~ 192) 216
2034 22:55:34.338174 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
2035 22:55:34.344355 iDelay=209, Bit 5, Center 96 (-15 ~ 208) 224
2036 22:55:34.347638 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
2037 22:55:34.351050 iDelay=209, Bit 7, Center 84 (-31 ~ 200) 232
2038 22:55:34.354129 iDelay=209, Bit 8, Center 72 (-39 ~ 184) 224
2039 22:55:34.357675 iDelay=209, Bit 9, Center 76 (-31 ~ 184) 216
2040 22:55:34.364051 iDelay=209, Bit 10, Center 88 (-23 ~ 200) 224
2041 22:55:34.367418 iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224
2042 22:55:34.370591 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
2043 22:55:34.373958 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2044 22:55:34.377520 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2045 22:55:34.383987 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
2046 22:55:34.384078 ==
2047 22:55:34.387628 Dram Type= 6, Freq= 0, CH_1, rank 1
2048 22:55:34.391073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2049 22:55:34.391156 ==
2050 22:55:34.391221 DQS Delay:
2051 22:55:34.394742 DQS0 = 0, DQS1 = 0
2052 22:55:34.394824 DQM Delay:
2053 22:55:34.397394 DQM0 = 87, DQM1 = 84
2054 22:55:34.397476 DQ Delay:
2055 22:55:34.400521 DQ0 =92, DQ1 =84, DQ2 =76, DQ3 =84
2056 22:55:34.403915 DQ4 =88, DQ5 =96, DQ6 =96, DQ7 =84
2057 22:55:34.407590 DQ8 =72, DQ9 =76, DQ10 =88, DQ11 =80
2058 22:55:34.411056 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =88
2059 22:55:34.411139
2060 22:55:34.411204
2061 22:55:34.420720 [DQSOSCAuto] RK1, (LSB)MR18= 0x233f, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 401 ps
2062 22:55:34.420803 CH1 RK1: MR19=606, MR18=233F
2063 22:55:34.427352 CH1_RK1: MR19=0x606, MR18=0x233F, DQSOSC=393, MR23=63, INC=95, DEC=63
2064 22:55:34.430405 [RxdqsGatingPostProcess] freq 800
2065 22:55:34.437227 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2066 22:55:34.441083 Pre-setting of DQS Precalculation
2067 22:55:34.443797 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2068 22:55:34.450214 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2069 22:55:34.459957 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2070 22:55:34.460069
2071 22:55:34.460136
2072 22:55:34.463599 [Calibration Summary] 1600 Mbps
2073 22:55:34.463698 CH 0, Rank 0
2074 22:55:34.467058 SW Impedance : PASS
2075 22:55:34.467141 DUTY Scan : NO K
2076 22:55:34.470140 ZQ Calibration : PASS
2077 22:55:34.470222 Jitter Meter : NO K
2078 22:55:34.473290 CBT Training : PASS
2079 22:55:34.477127 Write leveling : PASS
2080 22:55:34.477210 RX DQS gating : PASS
2081 22:55:34.480063 RX DQ/DQS(RDDQC) : PASS
2082 22:55:34.483628 TX DQ/DQS : PASS
2083 22:55:34.483737 RX DATLAT : PASS
2084 22:55:34.487214 RX DQ/DQS(Engine): PASS
2085 22:55:34.490160 TX OE : NO K
2086 22:55:34.490243 All Pass.
2087 22:55:34.490308
2088 22:55:34.490368 CH 0, Rank 1
2089 22:55:34.493429 SW Impedance : PASS
2090 22:55:34.496634 DUTY Scan : NO K
2091 22:55:34.496717 ZQ Calibration : PASS
2092 22:55:34.500280 Jitter Meter : NO K
2093 22:55:34.503456 CBT Training : PASS
2094 22:55:34.503540 Write leveling : PASS
2095 22:55:34.507081 RX DQS gating : PASS
2096 22:55:34.510508 RX DQ/DQS(RDDQC) : PASS
2097 22:55:34.510593 TX DQ/DQS : PASS
2098 22:55:34.514047 RX DATLAT : PASS
2099 22:55:34.516732 RX DQ/DQS(Engine): PASS
2100 22:55:34.516815 TX OE : NO K
2101 22:55:34.516883 All Pass.
2102 22:55:34.516945
2103 22:55:34.519838 CH 1, Rank 0
2104 22:55:34.523160 SW Impedance : PASS
2105 22:55:34.523244 DUTY Scan : NO K
2106 22:55:34.526769 ZQ Calibration : PASS
2107 22:55:34.526853 Jitter Meter : NO K
2108 22:55:34.530234 CBT Training : PASS
2109 22:55:34.533539 Write leveling : PASS
2110 22:55:34.533623 RX DQS gating : PASS
2111 22:55:34.536676 RX DQ/DQS(RDDQC) : PASS
2112 22:55:34.542329 TX DQ/DQS : PASS
2113 22:55:34.542416 RX DATLAT : PASS
2114 22:55:34.544104 RX DQ/DQS(Engine): PASS
2115 22:55:34.546482 TX OE : NO K
2116 22:55:34.546566 All Pass.
2117 22:55:34.546632
2118 22:55:34.546693 CH 1, Rank 1
2119 22:55:34.549825 SW Impedance : PASS
2120 22:55:34.553402 DUTY Scan : NO K
2121 22:55:34.553486 ZQ Calibration : PASS
2122 22:55:34.556321 Jitter Meter : NO K
2123 22:55:34.559511 CBT Training : PASS
2124 22:55:34.559595 Write leveling : PASS
2125 22:55:34.562984 RX DQS gating : PASS
2126 22:55:34.566389 RX DQ/DQS(RDDQC) : PASS
2127 22:55:34.566474 TX DQ/DQS : PASS
2128 22:55:34.569589 RX DATLAT : PASS
2129 22:55:34.572924 RX DQ/DQS(Engine): PASS
2130 22:55:34.573008 TX OE : NO K
2131 22:55:34.573075 All Pass.
2132 22:55:34.576651
2133 22:55:34.576735 DramC Write-DBI off
2134 22:55:34.579267 PER_BANK_REFRESH: Hybrid Mode
2135 22:55:34.579350 TX_TRACKING: ON
2136 22:55:34.582976 [GetDramInforAfterCalByMRR] Vendor 6.
2137 22:55:34.585915 [GetDramInforAfterCalByMRR] Revision 606.
2138 22:55:34.592697 [GetDramInforAfterCalByMRR] Revision 2 0.
2139 22:55:34.592783 MR0 0x3b3b
2140 22:55:34.592849 MR8 0x5151
2141 22:55:34.596069 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2142 22:55:34.596152
2143 22:55:34.599366 MR0 0x3b3b
2144 22:55:34.599448 MR8 0x5151
2145 22:55:34.602857 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2146 22:55:34.602942
2147 22:55:34.612689 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2148 22:55:34.616536 [FAST_K] Save calibration result to emmc
2149 22:55:34.619269 [FAST_K] Save calibration result to emmc
2150 22:55:34.622645 dram_init: config_dvfs: 1
2151 22:55:34.625712 dramc_set_vcore_voltage set vcore to 662500
2152 22:55:34.629665 Read voltage for 1200, 2
2153 22:55:34.629751 Vio18 = 0
2154 22:55:34.629817 Vcore = 662500
2155 22:55:34.632074 Vdram = 0
2156 22:55:34.632169 Vddq = 0
2157 22:55:34.632233 Vmddr = 0
2158 22:55:34.639333 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2159 22:55:34.642152 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2160 22:55:34.645557 MEM_TYPE=3, freq_sel=15
2161 22:55:34.649081 sv_algorithm_assistance_LP4_1600
2162 22:55:34.651986 ============ PULL DRAM RESETB DOWN ============
2163 22:55:34.655160 ========== PULL DRAM RESETB DOWN end =========
2164 22:55:34.662237 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2165 22:55:34.665410 ===================================
2166 22:55:34.665495 LPDDR4 DRAM CONFIGURATION
2167 22:55:34.668810 ===================================
2168 22:55:34.672322 EX_ROW_EN[0] = 0x0
2169 22:55:34.675324 EX_ROW_EN[1] = 0x0
2170 22:55:34.675407 LP4Y_EN = 0x0
2171 22:55:34.678827 WORK_FSP = 0x0
2172 22:55:34.678910 WL = 0x4
2173 22:55:34.682393 RL = 0x4
2174 22:55:34.682475 BL = 0x2
2175 22:55:34.685456 RPST = 0x0
2176 22:55:34.685538 RD_PRE = 0x0
2177 22:55:34.688578 WR_PRE = 0x1
2178 22:55:34.688660 WR_PST = 0x0
2179 22:55:34.692328 DBI_WR = 0x0
2180 22:55:34.692410 DBI_RD = 0x0
2181 22:55:34.695648 OTF = 0x1
2182 22:55:34.698680 ===================================
2183 22:55:34.701761 ===================================
2184 22:55:34.701844 ANA top config
2185 22:55:34.706416 ===================================
2186 22:55:34.708551 DLL_ASYNC_EN = 0
2187 22:55:34.711783 ALL_SLAVE_EN = 0
2188 22:55:34.715051 NEW_RANK_MODE = 1
2189 22:55:34.715135 DLL_IDLE_MODE = 1
2190 22:55:34.719084 LP45_APHY_COMB_EN = 1
2191 22:55:34.721761 TX_ODT_DIS = 1
2192 22:55:34.725294 NEW_8X_MODE = 1
2193 22:55:34.728391 ===================================
2194 22:55:34.731666 ===================================
2195 22:55:34.734875 data_rate = 2400
2196 22:55:34.734958 CKR = 1
2197 22:55:34.738178 DQ_P2S_RATIO = 8
2198 22:55:34.742005 ===================================
2199 22:55:34.745449 CA_P2S_RATIO = 8
2200 22:55:34.748388 DQ_CA_OPEN = 0
2201 22:55:34.751397 DQ_SEMI_OPEN = 0
2202 22:55:34.756790 CA_SEMI_OPEN = 0
2203 22:55:34.756877 CA_FULL_RATE = 0
2204 22:55:34.758143 DQ_CKDIV4_EN = 0
2205 22:55:34.762316 CA_CKDIV4_EN = 0
2206 22:55:34.764971 CA_PREDIV_EN = 0
2207 22:55:34.768158 PH8_DLY = 17
2208 22:55:34.771809 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2209 22:55:34.771895 DQ_AAMCK_DIV = 4
2210 22:55:34.775167 CA_AAMCK_DIV = 4
2211 22:55:34.778195 CA_ADMCK_DIV = 4
2212 22:55:34.781415 DQ_TRACK_CA_EN = 0
2213 22:55:34.784729 CA_PICK = 1200
2214 22:55:34.788160 CA_MCKIO = 1200
2215 22:55:34.791959 MCKIO_SEMI = 0
2216 22:55:34.792048 PLL_FREQ = 2366
2217 22:55:34.794775 DQ_UI_PI_RATIO = 32
2218 22:55:34.798229 CA_UI_PI_RATIO = 0
2219 22:55:34.801516 ===================================
2220 22:55:34.804815 ===================================
2221 22:55:34.808159 memory_type:LPDDR4
2222 22:55:34.808244 GP_NUM : 10
2223 22:55:34.812312 SRAM_EN : 1
2224 22:55:34.814816 MD32_EN : 0
2225 22:55:34.817931 ===================================
2226 22:55:34.818017 [ANA_INIT] >>>>>>>>>>>>>>
2227 22:55:34.822195 <<<<<< [CONFIGURE PHASE]: ANA_TX
2228 22:55:34.824852 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2229 22:55:34.828147 ===================================
2230 22:55:34.831570 data_rate = 2400,PCW = 0X5b00
2231 22:55:34.834541 ===================================
2232 22:55:34.838609 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2233 22:55:34.844735 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2234 22:55:34.848571 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2235 22:55:34.855246 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2236 22:55:34.857895 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2237 22:55:34.862104 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2238 22:55:34.865043 [ANA_INIT] flow start
2239 22:55:34.865211 [ANA_INIT] PLL >>>>>>>>
2240 22:55:34.868332 [ANA_INIT] PLL <<<<<<<<
2241 22:55:34.871376 [ANA_INIT] MIDPI >>>>>>>>
2242 22:55:34.871512 [ANA_INIT] MIDPI <<<<<<<<
2243 22:55:34.874888 [ANA_INIT] DLL >>>>>>>>
2244 22:55:34.878539 [ANA_INIT] DLL <<<<<<<<
2245 22:55:34.878668 [ANA_INIT] flow end
2246 22:55:34.881491 ============ LP4 DIFF to SE enter ============
2247 22:55:34.887666 ============ LP4 DIFF to SE exit ============
2248 22:55:34.887796 [ANA_INIT] <<<<<<<<<<<<<
2249 22:55:34.890968 [Flow] Enable top DCM control >>>>>
2250 22:55:34.894550 [Flow] Enable top DCM control <<<<<
2251 22:55:34.898064 Enable DLL master slave shuffle
2252 22:55:34.904158 ==============================================================
2253 22:55:34.907627 Gating Mode config
2254 22:55:34.911130 ==============================================================
2255 22:55:34.914530 Config description:
2256 22:55:34.924233 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2257 22:55:34.930998 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2258 22:55:34.934008 SELPH_MODE 0: By rank 1: By Phase
2259 22:55:34.941049 ==============================================================
2260 22:55:34.944223 GAT_TRACK_EN = 1
2261 22:55:34.947734 RX_GATING_MODE = 2
2262 22:55:34.951662 RX_GATING_TRACK_MODE = 2
2263 22:55:34.951748 SELPH_MODE = 1
2264 22:55:34.954345 PICG_EARLY_EN = 1
2265 22:55:34.957735 VALID_LAT_VALUE = 1
2266 22:55:34.964048 ==============================================================
2267 22:55:34.967583 Enter into Gating configuration >>>>
2268 22:55:34.971008 Exit from Gating configuration <<<<
2269 22:55:34.974563 Enter into DVFS_PRE_config >>>>>
2270 22:55:34.985032 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2271 22:55:34.987385 Exit from DVFS_PRE_config <<<<<
2272 22:55:34.990538 Enter into PICG configuration >>>>
2273 22:55:34.994007 Exit from PICG configuration <<<<
2274 22:55:34.997723 [RX_INPUT] configuration >>>>>
2275 22:55:35.001354 [RX_INPUT] configuration <<<<<
2276 22:55:35.004700 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2277 22:55:35.011156 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2278 22:55:35.017569 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2279 22:55:35.024064 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2280 22:55:35.027411 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2281 22:55:35.033740 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2282 22:55:35.037365 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2283 22:55:35.043752 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2284 22:55:35.047457 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2285 22:55:35.050904 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2286 22:55:35.053774 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2287 22:55:35.060494 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2288 22:55:35.064376 ===================================
2289 22:55:35.067190 LPDDR4 DRAM CONFIGURATION
2290 22:55:35.070358 ===================================
2291 22:55:35.070442 EX_ROW_EN[0] = 0x0
2292 22:55:35.073512 EX_ROW_EN[1] = 0x0
2293 22:55:35.073595 LP4Y_EN = 0x0
2294 22:55:35.076786 WORK_FSP = 0x0
2295 22:55:35.076869 WL = 0x4
2296 22:55:35.080411 RL = 0x4
2297 22:55:35.080495 BL = 0x2
2298 22:55:35.083723 RPST = 0x0
2299 22:55:35.083805 RD_PRE = 0x0
2300 22:55:35.087186 WR_PRE = 0x1
2301 22:55:35.087269 WR_PST = 0x0
2302 22:55:35.090603 DBI_WR = 0x0
2303 22:55:35.090687 DBI_RD = 0x0
2304 22:55:35.094422 OTF = 0x1
2305 22:55:35.097012 ===================================
2306 22:55:35.100364 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2307 22:55:35.103479 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2308 22:55:35.110637 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2309 22:55:35.113364 ===================================
2310 22:55:35.113453 LPDDR4 DRAM CONFIGURATION
2311 22:55:35.117239 ===================================
2312 22:55:35.119986 EX_ROW_EN[0] = 0x10
2313 22:55:35.123550 EX_ROW_EN[1] = 0x0
2314 22:55:35.123633 LP4Y_EN = 0x0
2315 22:55:35.126723 WORK_FSP = 0x0
2316 22:55:35.126808 WL = 0x4
2317 22:55:35.130656 RL = 0x4
2318 22:55:35.130741 BL = 0x2
2319 22:55:35.133444 RPST = 0x0
2320 22:55:35.133528 RD_PRE = 0x0
2321 22:55:35.136635 WR_PRE = 0x1
2322 22:55:35.136717 WR_PST = 0x0
2323 22:55:35.139936 DBI_WR = 0x0
2324 22:55:35.140018 DBI_RD = 0x0
2325 22:55:35.143927 OTF = 0x1
2326 22:55:35.146642 ===================================
2327 22:55:35.153184 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2328 22:55:35.153277 ==
2329 22:55:35.157012 Dram Type= 6, Freq= 0, CH_0, rank 0
2330 22:55:35.160398 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2331 22:55:35.160482 ==
2332 22:55:35.163159 [Duty_Offset_Calibration]
2333 22:55:35.163242 B0:2 B1:0 CA:4
2334 22:55:35.163308
2335 22:55:35.166724 [DutyScan_Calibration_Flow] k_type=0
2336 22:55:35.176548
2337 22:55:35.176633 ==CLK 0==
2338 22:55:35.179577 Final CLK duty delay cell = -4
2339 22:55:35.183021 [-4] MAX Duty = 5031%(X100), DQS PI = 14
2340 22:55:35.185840 [-4] MIN Duty = 4844%(X100), DQS PI = 8
2341 22:55:35.189261 [-4] AVG Duty = 4937%(X100)
2342 22:55:35.189366
2343 22:55:35.192827 CH0 CLK Duty spec in!! Max-Min= 187%
2344 22:55:35.195901 [DutyScan_Calibration_Flow] ====Done====
2345 22:55:35.196027
2346 22:55:35.199359 [DutyScan_Calibration_Flow] k_type=1
2347 22:55:35.214737
2348 22:55:35.214881 ==DQS 0 ==
2349 22:55:35.218335 Final DQS duty delay cell = -4
2350 22:55:35.221334 [-4] MAX Duty = 4969%(X100), DQS PI = 14
2351 22:55:35.224582 [-4] MIN Duty = 4876%(X100), DQS PI = 0
2352 22:55:35.227853 [-4] AVG Duty = 4922%(X100)
2353 22:55:35.227933
2354 22:55:35.227997 ==DQS 1 ==
2355 22:55:35.231364 Final DQS duty delay cell = 0
2356 22:55:35.234864 [0] MAX Duty = 5125%(X100), DQS PI = 4
2357 22:55:35.238390 [0] MIN Duty = 4969%(X100), DQS PI = 62
2358 22:55:35.241532 [0] AVG Duty = 5047%(X100)
2359 22:55:35.241645
2360 22:55:35.244763 CH0 DQS 0 Duty spec in!! Max-Min= 93%
2361 22:55:35.244845
2362 22:55:35.247841 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2363 22:55:35.251660 [DutyScan_Calibration_Flow] ====Done====
2364 22:55:35.251740
2365 22:55:35.254682 [DutyScan_Calibration_Flow] k_type=3
2366 22:55:35.271752
2367 22:55:35.271843 ==DQM 0 ==
2368 22:55:35.274656 Final DQM duty delay cell = 0
2369 22:55:35.278802 [0] MAX Duty = 5094%(X100), DQS PI = 20
2370 22:55:35.281383 [0] MIN Duty = 4844%(X100), DQS PI = 54
2371 22:55:35.285085 [0] AVG Duty = 4969%(X100)
2372 22:55:35.285166
2373 22:55:35.285230 ==DQM 1 ==
2374 22:55:35.288561 Final DQM duty delay cell = 0
2375 22:55:35.291480 [0] MAX Duty = 4969%(X100), DQS PI = 0
2376 22:55:35.295240 [0] MIN Duty = 4875%(X100), DQS PI = 22
2377 22:55:35.298315 [0] AVG Duty = 4922%(X100)
2378 22:55:35.298396
2379 22:55:35.301406 CH0 DQM 0 Duty spec in!! Max-Min= 250%
2380 22:55:35.301487
2381 22:55:35.304992 CH0 DQM 1 Duty spec in!! Max-Min= 94%
2382 22:55:35.308251 [DutyScan_Calibration_Flow] ====Done====
2383 22:55:35.308332
2384 22:55:35.312055 [DutyScan_Calibration_Flow] k_type=2
2385 22:55:35.327826
2386 22:55:35.327924 ==DQ 0 ==
2387 22:55:35.331100 Final DQ duty delay cell = 0
2388 22:55:35.335085 [0] MAX Duty = 5125%(X100), DQS PI = 18
2389 22:55:35.337794 [0] MIN Duty = 4969%(X100), DQS PI = 58
2390 22:55:35.341525 [0] AVG Duty = 5047%(X100)
2391 22:55:35.341608
2392 22:55:35.341678 ==DQ 1 ==
2393 22:55:35.344409 Final DQ duty delay cell = 0
2394 22:55:35.347813 [0] MAX Duty = 5125%(X100), DQS PI = 4
2395 22:55:35.350843 [0] MIN Duty = 4938%(X100), DQS PI = 16
2396 22:55:35.350926 [0] AVG Duty = 5031%(X100)
2397 22:55:35.354064
2398 22:55:35.357952 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2399 22:55:35.358036
2400 22:55:35.361168 CH0 DQ 1 Duty spec in!! Max-Min= 187%
2401 22:55:35.364152 [DutyScan_Calibration_Flow] ====Done====
2402 22:55:35.364235 ==
2403 22:55:35.367620 Dram Type= 6, Freq= 0, CH_1, rank 0
2404 22:55:35.370759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2405 22:55:35.370842 ==
2406 22:55:35.374534 [Duty_Offset_Calibration]
2407 22:55:35.374617 B0:0 B1:-1 CA:3
2408 22:55:35.374682
2409 22:55:35.377471 [DutyScan_Calibration_Flow] k_type=0
2410 22:55:35.386891
2411 22:55:35.386975 ==CLK 0==
2412 22:55:35.390975 Final CLK duty delay cell = -4
2413 22:55:35.394115 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2414 22:55:35.397163 [-4] MIN Duty = 4876%(X100), DQS PI = 36
2415 22:55:35.400463 [-4] AVG Duty = 4938%(X100)
2416 22:55:35.400545
2417 22:55:35.403518 CH1 CLK Duty spec in!! Max-Min= 124%
2418 22:55:35.406940 [DutyScan_Calibration_Flow] ====Done====
2419 22:55:35.407022
2420 22:55:35.410517 [DutyScan_Calibration_Flow] k_type=1
2421 22:55:35.426768
2422 22:55:35.426866 ==DQS 0 ==
2423 22:55:35.429979 Final DQS duty delay cell = 0
2424 22:55:35.433075 [0] MAX Duty = 5187%(X100), DQS PI = 18
2425 22:55:35.436405 [0] MIN Duty = 4907%(X100), DQS PI = 38
2426 22:55:35.440143 [0] AVG Duty = 5047%(X100)
2427 22:55:35.440224
2428 22:55:35.440288 ==DQS 1 ==
2429 22:55:35.443295 Final DQS duty delay cell = 0
2430 22:55:35.446667 [0] MAX Duty = 5156%(X100), DQS PI = 10
2431 22:55:35.449840 [0] MIN Duty = 5031%(X100), DQS PI = 24
2432 22:55:35.453199 [0] AVG Duty = 5093%(X100)
2433 22:55:35.453281
2434 22:55:35.456442 CH1 DQS 0 Duty spec in!! Max-Min= 280%
2435 22:55:35.456523
2436 22:55:35.460053 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2437 22:55:35.463127 [DutyScan_Calibration_Flow] ====Done====
2438 22:55:35.463225
2439 22:55:35.466691 [DutyScan_Calibration_Flow] k_type=3
2440 22:55:35.483923
2441 22:55:35.484035 ==DQM 0 ==
2442 22:55:35.487131 Final DQM duty delay cell = 0
2443 22:55:35.490531 [0] MAX Duty = 5031%(X100), DQS PI = 28
2444 22:55:35.494104 [0] MIN Duty = 4782%(X100), DQS PI = 38
2445 22:55:35.494185 [0] AVG Duty = 4906%(X100)
2446 22:55:35.497446
2447 22:55:35.497540 ==DQM 1 ==
2448 22:55:35.500903 Final DQM duty delay cell = 4
2449 22:55:35.504372 [4] MAX Duty = 5187%(X100), DQS PI = 30
2450 22:55:35.507740 [4] MIN Duty = 5062%(X100), DQS PI = 0
2451 22:55:35.507824 [4] AVG Duty = 5124%(X100)
2452 22:55:35.510612
2453 22:55:35.513741 CH1 DQM 0 Duty spec in!! Max-Min= 249%
2454 22:55:35.513826
2455 22:55:35.517508 CH1 DQM 1 Duty spec in!! Max-Min= 125%
2456 22:55:35.520664 [DutyScan_Calibration_Flow] ====Done====
2457 22:55:35.520748
2458 22:55:35.524939 [DutyScan_Calibration_Flow] k_type=2
2459 22:55:35.539405
2460 22:55:35.539498 ==DQ 0 ==
2461 22:55:35.542676 Final DQ duty delay cell = -4
2462 22:55:35.546305 [-4] MAX Duty = 5031%(X100), DQS PI = 30
2463 22:55:35.549624 [-4] MIN Duty = 4876%(X100), DQS PI = 20
2464 22:55:35.553436 [-4] AVG Duty = 4953%(X100)
2465 22:55:35.553520
2466 22:55:35.553586 ==DQ 1 ==
2467 22:55:35.555951 Final DQ duty delay cell = 0
2468 22:55:35.559541 [0] MAX Duty = 5031%(X100), DQS PI = 32
2469 22:55:35.563640 [0] MIN Duty = 4844%(X100), DQS PI = 0
2470 22:55:35.563725 [0] AVG Duty = 4937%(X100)
2471 22:55:35.566023
2472 22:55:35.569436 CH1 DQ 0 Duty spec in!! Max-Min= 155%
2473 22:55:35.569521
2474 22:55:35.572919 CH1 DQ 1 Duty spec in!! Max-Min= 187%
2475 22:55:35.576406 [DutyScan_Calibration_Flow] ====Done====
2476 22:55:35.579562 nWR fixed to 30
2477 22:55:35.579646 [ModeRegInit_LP4] CH0 RK0
2478 22:55:35.583244 [ModeRegInit_LP4] CH0 RK1
2479 22:55:35.586463 [ModeRegInit_LP4] CH1 RK0
2480 22:55:35.589641 [ModeRegInit_LP4] CH1 RK1
2481 22:55:35.589725 match AC timing 7
2482 22:55:35.596214 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2483 22:55:35.600227 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2484 22:55:35.602661 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2485 22:55:35.609784 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2486 22:55:35.612500 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2487 22:55:35.612589 ==
2488 22:55:35.615637 Dram Type= 6, Freq= 0, CH_0, rank 0
2489 22:55:35.619109 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2490 22:55:35.619194 ==
2491 22:55:35.625662 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2492 22:55:35.633485 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2493 22:55:35.639649 [CA 0] Center 39 (9~70) winsize 62
2494 22:55:35.643125 [CA 1] Center 39 (9~70) winsize 62
2495 22:55:35.647004 [CA 2] Center 35 (5~66) winsize 62
2496 22:55:35.650167 [CA 3] Center 35 (5~66) winsize 62
2497 22:55:35.653200 [CA 4] Center 33 (3~64) winsize 62
2498 22:55:35.656785 [CA 5] Center 33 (3~63) winsize 61
2499 22:55:35.656870
2500 22:55:35.660430 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2501 22:55:35.660519
2502 22:55:35.663063 [CATrainingPosCal] consider 1 rank data
2503 22:55:35.666326 u2DelayCellTimex100 = 270/100 ps
2504 22:55:35.669794 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2505 22:55:35.676790 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2506 22:55:35.679997 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2507 22:55:35.682856 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2508 22:55:35.686598 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2509 22:55:35.689919 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2510 22:55:35.690003
2511 22:55:35.693136 CA PerBit enable=1, Macro0, CA PI delay=33
2512 22:55:35.693220
2513 22:55:35.696535 [CBTSetCACLKResult] CA Dly = 33
2514 22:55:35.696618 CS Dly: 7 (0~38)
2515 22:55:35.699657 ==
2516 22:55:35.702913 Dram Type= 6, Freq= 0, CH_0, rank 1
2517 22:55:35.706653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2518 22:55:35.706737 ==
2519 22:55:35.709655 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2520 22:55:35.715847 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2521 22:55:35.725935 [CA 0] Center 39 (9~70) winsize 62
2522 22:55:35.729193 [CA 1] Center 39 (9~70) winsize 62
2523 22:55:35.731942 [CA 2] Center 35 (5~66) winsize 62
2524 22:55:35.735976 [CA 3] Center 35 (5~66) winsize 62
2525 22:55:35.739284 [CA 4] Center 34 (4~65) winsize 62
2526 22:55:35.742396 [CA 5] Center 33 (3~64) winsize 62
2527 22:55:35.742543
2528 22:55:35.745371 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2529 22:55:35.745454
2530 22:55:35.748858 [CATrainingPosCal] consider 2 rank data
2531 22:55:35.751811 u2DelayCellTimex100 = 270/100 ps
2532 22:55:35.755444 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2533 22:55:35.761901 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2534 22:55:35.765239 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2535 22:55:35.768907 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2536 22:55:35.771765 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2537 22:55:35.775541 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2538 22:55:35.775625
2539 22:55:35.778975 CA PerBit enable=1, Macro0, CA PI delay=33
2540 22:55:35.779059
2541 22:55:35.781868 [CBTSetCACLKResult] CA Dly = 33
2542 22:55:35.781951 CS Dly: 8 (0~41)
2543 22:55:35.785392
2544 22:55:35.788983 ----->DramcWriteLeveling(PI) begin...
2545 22:55:35.789068 ==
2546 22:55:35.792091 Dram Type= 6, Freq= 0, CH_0, rank 0
2547 22:55:35.794997 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2548 22:55:35.795079 ==
2549 22:55:35.798419 Write leveling (Byte 0): 33 => 33
2550 22:55:35.802004 Write leveling (Byte 1): 27 => 27
2551 22:55:35.805213 DramcWriteLeveling(PI) end<-----
2552 22:55:35.805296
2553 22:55:35.805361 ==
2554 22:55:35.808181 Dram Type= 6, Freq= 0, CH_0, rank 0
2555 22:55:35.811571 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2556 22:55:35.811655 ==
2557 22:55:35.814851 [Gating] SW mode calibration
2558 22:55:35.821616 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2559 22:55:35.828279 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2560 22:55:35.831656 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2561 22:55:35.834951 0 15 4 | B1->B0 | 2f2f 3434 | 1 1 | (0 0) (1 1)
2562 22:55:35.841781 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2563 22:55:35.844859 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2564 22:55:35.848254 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2565 22:55:35.855167 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2566 22:55:35.858159 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2567 22:55:35.861553 0 15 28 | B1->B0 | 3434 2929 | 1 0 | (1 1) (0 1)
2568 22:55:35.867960 1 0 0 | B1->B0 | 3232 2323 | 1 0 | (1 0) (0 0)
2569 22:55:35.871763 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2570 22:55:35.874697 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2571 22:55:35.881287 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2572 22:55:35.884697 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2573 22:55:35.888313 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2574 22:55:35.894658 1 0 24 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
2575 22:55:35.897715 1 0 28 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
2576 22:55:35.901301 1 1 0 | B1->B0 | 2929 4646 | 0 0 | (0 0) (0 0)
2577 22:55:35.907847 1 1 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
2578 22:55:35.911764 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2579 22:55:35.914940 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2580 22:55:35.918043 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2581 22:55:35.924583 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2582 22:55:35.927734 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2583 22:55:35.931122 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2584 22:55:35.938701 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2585 22:55:35.941380 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2586 22:55:35.944627 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2587 22:55:35.951066 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2588 22:55:35.954761 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2589 22:55:35.957532 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2590 22:55:35.964309 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2591 22:55:35.968779 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2592 22:55:35.971249 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2593 22:55:35.977437 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2594 22:55:35.981122 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2595 22:55:35.984037 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2596 22:55:35.990979 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2597 22:55:35.994158 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2598 22:55:35.997720 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2599 22:55:36.004283 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2600 22:55:36.007617 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2601 22:55:36.010621 Total UI for P1: 0, mck2ui 16
2602 22:55:36.014823 best dqsien dly found for B0: ( 1, 3, 26)
2603 22:55:36.017957 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2604 22:55:36.020961 Total UI for P1: 0, mck2ui 16
2605 22:55:36.024346 best dqsien dly found for B1: ( 1, 4, 0)
2606 22:55:36.027151 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2607 22:55:36.030603 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2608 22:55:36.030687
2609 22:55:36.033775 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2610 22:55:36.040825 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2611 22:55:36.040910 [Gating] SW calibration Done
2612 22:55:36.040977 ==
2613 22:55:36.044114 Dram Type= 6, Freq= 0, CH_0, rank 0
2614 22:55:36.050619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2615 22:55:36.050703 ==
2616 22:55:36.050770 RX Vref Scan: 0
2617 22:55:36.050832
2618 22:55:36.053985 RX Vref 0 -> 0, step: 1
2619 22:55:36.054069
2620 22:55:36.056854 RX Delay -40 -> 252, step: 8
2621 22:55:36.060437 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2622 22:55:36.063619 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2623 22:55:36.066914 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2624 22:55:36.073492 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2625 22:55:36.077100 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2626 22:55:36.080077 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2627 22:55:36.083483 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2628 22:55:36.087078 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2629 22:55:36.093667 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2630 22:55:36.096798 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2631 22:55:36.100100 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2632 22:55:36.103703 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2633 22:55:36.106917 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2634 22:55:36.113653 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2635 22:55:36.117159 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2636 22:55:36.120149 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2637 22:55:36.120233 ==
2638 22:55:36.123657 Dram Type= 6, Freq= 0, CH_0, rank 0
2639 22:55:36.126735 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2640 22:55:36.126819 ==
2641 22:55:36.129966 DQS Delay:
2642 22:55:36.130050 DQS0 = 0, DQS1 = 0
2643 22:55:36.133518 DQM Delay:
2644 22:55:36.133601 DQM0 = 118, DQM1 = 107
2645 22:55:36.137116 DQ Delay:
2646 22:55:36.141030 DQ0 =115, DQ1 =119, DQ2 =119, DQ3 =111
2647 22:55:36.143445 DQ4 =119, DQ5 =111, DQ6 =123, DQ7 =127
2648 22:55:36.146649 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2649 22:55:36.149954 DQ12 =119, DQ13 =111, DQ14 =119, DQ15 =111
2650 22:55:36.150037
2651 22:55:36.150103
2652 22:55:36.150163 ==
2653 22:55:36.153402 Dram Type= 6, Freq= 0, CH_0, rank 0
2654 22:55:36.157104 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2655 22:55:36.157188 ==
2656 22:55:36.157254
2657 22:55:36.157315
2658 22:55:36.160131 TX Vref Scan disable
2659 22:55:36.163122 == TX Byte 0 ==
2660 22:55:36.166387 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2661 22:55:36.170193 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2662 22:55:36.173006 == TX Byte 1 ==
2663 22:55:36.176492 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2664 22:55:36.180139 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2665 22:55:36.180223 ==
2666 22:55:36.182991 Dram Type= 6, Freq= 0, CH_0, rank 0
2667 22:55:36.189529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2668 22:55:36.189614 ==
2669 22:55:36.200534 TX Vref=22, minBit 4, minWin=24, winSum=410
2670 22:55:36.203687 TX Vref=24, minBit 10, minWin=24, winSum=416
2671 22:55:36.207061 TX Vref=26, minBit 4, minWin=25, winSum=422
2672 22:55:36.210485 TX Vref=28, minBit 1, minWin=26, winSum=427
2673 22:55:36.214081 TX Vref=30, minBit 1, minWin=26, winSum=426
2674 22:55:36.220309 TX Vref=32, minBit 4, minWin=26, winSum=427
2675 22:55:36.223552 [TxChooseVref] Worse bit 1, Min win 26, Win sum 427, Final Vref 28
2676 22:55:36.223635
2677 22:55:36.226868 Final TX Range 1 Vref 28
2678 22:55:36.226951
2679 22:55:36.227017 ==
2680 22:55:36.230819 Dram Type= 6, Freq= 0, CH_0, rank 0
2681 22:55:36.233494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2682 22:55:36.233578 ==
2683 22:55:36.236759
2684 22:55:36.236845
2685 22:55:36.236928 TX Vref Scan disable
2686 22:55:36.240173 == TX Byte 0 ==
2687 22:55:36.243329 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2688 22:55:36.250504 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2689 22:55:36.250589 == TX Byte 1 ==
2690 22:55:36.253952 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2691 22:55:36.260408 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2692 22:55:36.260494
2693 22:55:36.260578 [DATLAT]
2694 22:55:36.260657 Freq=1200, CH0 RK0
2695 22:55:36.260734
2696 22:55:36.263648 DATLAT Default: 0xd
2697 22:55:36.263731 0, 0xFFFF, sum = 0
2698 22:55:36.267161 1, 0xFFFF, sum = 0
2699 22:55:36.269968 2, 0xFFFF, sum = 0
2700 22:55:36.270053 3, 0xFFFF, sum = 0
2701 22:55:36.273314 4, 0xFFFF, sum = 0
2702 22:55:36.273399 5, 0xFFFF, sum = 0
2703 22:55:36.276912 6, 0xFFFF, sum = 0
2704 22:55:36.276998 7, 0xFFFF, sum = 0
2705 22:55:36.280163 8, 0xFFFF, sum = 0
2706 22:55:36.280248 9, 0xFFFF, sum = 0
2707 22:55:36.283235 10, 0xFFFF, sum = 0
2708 22:55:36.283320 11, 0xFFFF, sum = 0
2709 22:55:36.286528 12, 0x0, sum = 1
2710 22:55:36.286613 13, 0x0, sum = 2
2711 22:55:36.290456 14, 0x0, sum = 3
2712 22:55:36.290540 15, 0x0, sum = 4
2713 22:55:36.293257 best_step = 13
2714 22:55:36.293340
2715 22:55:36.293405 ==
2716 22:55:36.296792 Dram Type= 6, Freq= 0, CH_0, rank 0
2717 22:55:36.299748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2718 22:55:36.299831 ==
2719 22:55:36.299897 RX Vref Scan: 1
2720 22:55:36.299958
2721 22:55:36.303206 Set Vref Range= 32 -> 127
2722 22:55:36.303289
2723 22:55:36.306580 RX Vref 32 -> 127, step: 1
2724 22:55:36.306663
2725 22:55:36.309712 RX Delay -21 -> 252, step: 4
2726 22:55:36.309794
2727 22:55:36.312978 Set Vref, RX VrefLevel [Byte0]: 32
2728 22:55:36.316414 [Byte1]: 32
2729 22:55:36.316496
2730 22:55:36.319781 Set Vref, RX VrefLevel [Byte0]: 33
2731 22:55:36.322988 [Byte1]: 33
2732 22:55:36.327084
2733 22:55:36.327166 Set Vref, RX VrefLevel [Byte0]: 34
2734 22:55:36.330134 [Byte1]: 34
2735 22:55:36.334643
2736 22:55:36.334725 Set Vref, RX VrefLevel [Byte0]: 35
2737 22:55:36.338169 [Byte1]: 35
2738 22:55:36.342706
2739 22:55:36.342789 Set Vref, RX VrefLevel [Byte0]: 36
2740 22:55:36.345928 [Byte1]: 36
2741 22:55:36.350315
2742 22:55:36.350398 Set Vref, RX VrefLevel [Byte0]: 37
2743 22:55:36.353805 [Byte1]: 37
2744 22:55:36.358703
2745 22:55:36.358786 Set Vref, RX VrefLevel [Byte0]: 38
2746 22:55:36.361695 [Byte1]: 38
2747 22:55:36.366757
2748 22:55:36.366840 Set Vref, RX VrefLevel [Byte0]: 39
2749 22:55:36.369583 [Byte1]: 39
2750 22:55:36.374183
2751 22:55:36.374266 Set Vref, RX VrefLevel [Byte0]: 40
2752 22:55:36.377691 [Byte1]: 40
2753 22:55:36.382156
2754 22:55:36.382239 Set Vref, RX VrefLevel [Byte0]: 41
2755 22:55:36.385417 [Byte1]: 41
2756 22:55:36.391067
2757 22:55:36.391151 Set Vref, RX VrefLevel [Byte0]: 42
2758 22:55:36.393632 [Byte1]: 42
2759 22:55:36.398228
2760 22:55:36.398316 Set Vref, RX VrefLevel [Byte0]: 43
2761 22:55:36.401313 [Byte1]: 43
2762 22:55:36.406000
2763 22:55:36.406084 Set Vref, RX VrefLevel [Byte0]: 44
2764 22:55:36.409356 [Byte1]: 44
2765 22:55:36.414233
2766 22:55:36.414318 Set Vref, RX VrefLevel [Byte0]: 45
2767 22:55:36.417714 [Byte1]: 45
2768 22:55:36.421976
2769 22:55:36.422059 Set Vref, RX VrefLevel [Byte0]: 46
2770 22:55:36.425307 [Byte1]: 46
2771 22:55:36.430356
2772 22:55:36.430438 Set Vref, RX VrefLevel [Byte0]: 47
2773 22:55:36.433049 [Byte1]: 47
2774 22:55:36.437504
2775 22:55:36.437586 Set Vref, RX VrefLevel [Byte0]: 48
2776 22:55:36.441144 [Byte1]: 48
2777 22:55:36.445748
2778 22:55:36.445831 Set Vref, RX VrefLevel [Byte0]: 49
2779 22:55:36.449918 [Byte1]: 49
2780 22:55:36.453902
2781 22:55:36.453985 Set Vref, RX VrefLevel [Byte0]: 50
2782 22:55:36.456824 [Byte1]: 50
2783 22:55:36.462870
2784 22:55:36.462954 Set Vref, RX VrefLevel [Byte0]: 51
2785 22:55:36.464637 [Byte1]: 51
2786 22:55:36.469407
2787 22:55:36.469489 Set Vref, RX VrefLevel [Byte0]: 52
2788 22:55:36.472623 [Byte1]: 52
2789 22:55:36.477722
2790 22:55:36.477804 Set Vref, RX VrefLevel [Byte0]: 53
2791 22:55:36.480515 [Byte1]: 53
2792 22:55:36.485289
2793 22:55:36.485371 Set Vref, RX VrefLevel [Byte0]: 54
2794 22:55:36.488454 [Byte1]: 54
2795 22:55:36.493353
2796 22:55:36.493435 Set Vref, RX VrefLevel [Byte0]: 55
2797 22:55:36.496578 [Byte1]: 55
2798 22:55:36.501475
2799 22:55:36.501557 Set Vref, RX VrefLevel [Byte0]: 56
2800 22:55:36.504698 [Byte1]: 56
2801 22:55:36.509890
2802 22:55:36.509973 Set Vref, RX VrefLevel [Byte0]: 57
2803 22:55:36.512192 [Byte1]: 57
2804 22:55:36.517197
2805 22:55:36.517283 Set Vref, RX VrefLevel [Byte0]: 58
2806 22:55:36.520650 [Byte1]: 58
2807 22:55:36.525037
2808 22:55:36.525120 Set Vref, RX VrefLevel [Byte0]: 59
2809 22:55:36.528100 [Byte1]: 59
2810 22:55:36.532763
2811 22:55:36.532848 Set Vref, RX VrefLevel [Byte0]: 60
2812 22:55:36.536676 [Byte1]: 60
2813 22:55:36.540623
2814 22:55:36.540706 Set Vref, RX VrefLevel [Byte0]: 61
2815 22:55:36.544090 [Byte1]: 61
2816 22:55:36.548788
2817 22:55:36.548869 Set Vref, RX VrefLevel [Byte0]: 62
2818 22:55:36.551809 [Byte1]: 62
2819 22:55:36.556428
2820 22:55:36.556525 Set Vref, RX VrefLevel [Byte0]: 63
2821 22:55:36.559895 [Byte1]: 63
2822 22:55:36.564568
2823 22:55:36.564654 Set Vref, RX VrefLevel [Byte0]: 64
2824 22:55:36.567635 [Byte1]: 64
2825 22:55:36.572841
2826 22:55:36.572938 Set Vref, RX VrefLevel [Byte0]: 65
2827 22:55:36.575800 [Byte1]: 65
2828 22:55:36.580421
2829 22:55:36.580503 Set Vref, RX VrefLevel [Byte0]: 66
2830 22:55:36.583881 [Byte1]: 66
2831 22:55:36.588205
2832 22:55:36.588302 Set Vref, RX VrefLevel [Byte0]: 67
2833 22:55:36.591533 [Byte1]: 67
2834 22:55:36.596233
2835 22:55:36.596314 Final RX Vref Byte 0 = 53 to rank0
2836 22:55:36.599692 Final RX Vref Byte 1 = 49 to rank0
2837 22:55:36.602793 Final RX Vref Byte 0 = 53 to rank1
2838 22:55:36.606076 Final RX Vref Byte 1 = 49 to rank1==
2839 22:55:36.609337 Dram Type= 6, Freq= 0, CH_0, rank 0
2840 22:55:36.616504 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2841 22:55:36.616590 ==
2842 22:55:36.616658 DQS Delay:
2843 22:55:36.619759 DQS0 = 0, DQS1 = 0
2844 22:55:36.619842 DQM Delay:
2845 22:55:36.619908 DQM0 = 117, DQM1 = 104
2846 22:55:36.622566 DQ Delay:
2847 22:55:36.626258 DQ0 =118, DQ1 =116, DQ2 =114, DQ3 =114
2848 22:55:36.629422 DQ4 =120, DQ5 =110, DQ6 =124, DQ7 =122
2849 22:55:36.632528 DQ8 =92, DQ9 =88, DQ10 =106, DQ11 =100
2850 22:55:36.636277 DQ12 =112, DQ13 =108, DQ14 =116, DQ15 =112
2851 22:55:36.636360
2852 22:55:36.636426
2853 22:55:36.646089 [DQSOSCAuto] RK0, (LSB)MR18= 0x4ff, (MSB)MR19= 0x403, tDQSOscB0 = 410 ps tDQSOscB1 = 408 ps
2854 22:55:36.646176 CH0 RK0: MR19=403, MR18=4FF
2855 22:55:36.652536 CH0_RK0: MR19=0x403, MR18=0x4FF, DQSOSC=408, MR23=63, INC=39, DEC=26
2856 22:55:36.652622
2857 22:55:36.655901 ----->DramcWriteLeveling(PI) begin...
2858 22:55:36.655986 ==
2859 22:55:36.659148 Dram Type= 6, Freq= 0, CH_0, rank 1
2860 22:55:36.662262 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2861 22:55:36.665782 ==
2862 22:55:36.665866 Write leveling (Byte 0): 33 => 33
2863 22:55:36.669136 Write leveling (Byte 1): 29 => 29
2864 22:55:36.672186 DramcWriteLeveling(PI) end<-----
2865 22:55:36.672269
2866 22:55:36.672336 ==
2867 22:55:36.675557 Dram Type= 6, Freq= 0, CH_0, rank 1
2868 22:55:36.682428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2869 22:55:36.682513 ==
2870 22:55:36.685504 [Gating] SW mode calibration
2871 22:55:36.692261 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2872 22:55:36.696312 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2873 22:55:36.702443 0 15 0 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
2874 22:55:36.706349 0 15 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
2875 22:55:36.709433 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2876 22:55:36.712174 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2877 22:55:36.718785 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2878 22:55:36.722177 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2879 22:55:36.725515 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2880 22:55:36.732059 0 15 28 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (1 0)
2881 22:55:36.735795 1 0 0 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0)
2882 22:55:36.738775 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2883 22:55:36.745901 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2884 22:55:36.749304 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2885 22:55:36.751981 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2886 22:55:36.759346 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2887 22:55:36.762022 1 0 24 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
2888 22:55:36.765635 1 0 28 | B1->B0 | 2828 4646 | 0 0 | (0 0) (0 0)
2889 22:55:36.772202 1 1 0 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
2890 22:55:36.775501 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2891 22:55:36.779076 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2892 22:55:36.785389 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2893 22:55:36.788585 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2894 22:55:36.791979 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2895 22:55:36.798232 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2896 22:55:36.802208 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2897 22:55:36.805191 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2898 22:55:36.811618 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2899 22:55:36.814856 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2900 22:55:36.818622 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2901 22:55:36.825007 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2902 22:55:36.828661 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2903 22:55:36.831842 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2904 22:55:36.838261 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2905 22:55:36.841894 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2906 22:55:36.845050 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2907 22:55:36.851510 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2908 22:55:36.854762 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2909 22:55:36.858193 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2910 22:55:36.864796 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2911 22:55:36.868059 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2912 22:55:36.871340 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2913 22:55:36.875289 Total UI for P1: 0, mck2ui 16
2914 22:55:36.877845 best dqsien dly found for B0: ( 1, 3, 24)
2915 22:55:36.884746 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2916 22:55:36.887856 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2917 22:55:36.891468 Total UI for P1: 0, mck2ui 16
2918 22:55:36.895165 best dqsien dly found for B1: ( 1, 3, 30)
2919 22:55:36.897799 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
2920 22:55:36.901534 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2921 22:55:36.901617
2922 22:55:36.904510 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
2923 22:55:36.907834 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2924 22:55:36.911506 [Gating] SW calibration Done
2925 22:55:36.911588 ==
2926 22:55:36.914405 Dram Type= 6, Freq= 0, CH_0, rank 1
2927 22:55:36.918386 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2928 22:55:36.918469 ==
2929 22:55:36.921371 RX Vref Scan: 0
2930 22:55:36.921458
2931 22:55:36.925064 RX Vref 0 -> 0, step: 1
2932 22:55:36.925148
2933 22:55:36.925214 RX Delay -40 -> 252, step: 8
2934 22:55:36.931051 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2935 22:55:36.934566 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2936 22:55:36.938183 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2937 22:55:36.941313 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2938 22:55:36.944384 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2939 22:55:36.951439 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2940 22:55:36.955200 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2941 22:55:36.957872 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2942 22:55:36.961339 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2943 22:55:36.964422 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2944 22:55:36.971295 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2945 22:55:36.974756 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2946 22:55:36.977567 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2947 22:55:36.981351 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2948 22:55:36.985076 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2949 22:55:36.991251 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2950 22:55:36.991423 ==
2951 22:55:36.995310 Dram Type= 6, Freq= 0, CH_0, rank 1
2952 22:55:36.997925 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2953 22:55:36.998104 ==
2954 22:55:36.998195 DQS Delay:
2955 22:55:37.001243 DQS0 = 0, DQS1 = 0
2956 22:55:37.001435 DQM Delay:
2957 22:55:37.004458 DQM0 = 116, DQM1 = 106
2958 22:55:37.004655 DQ Delay:
2959 22:55:37.007868 DQ0 =111, DQ1 =119, DQ2 =111, DQ3 =115
2960 22:55:37.011822 DQ4 =119, DQ5 =107, DQ6 =127, DQ7 =123
2961 22:55:37.014420 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2962 22:55:37.017886 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2963 22:55:37.018119
2964 22:55:37.018252
2965 22:55:37.021648 ==
2966 22:55:37.024119 Dram Type= 6, Freq= 0, CH_0, rank 1
2967 22:55:37.027700 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2968 22:55:37.028053 ==
2969 22:55:37.028259
2970 22:55:37.028421
2971 22:55:37.030845 TX Vref Scan disable
2972 22:55:37.031172 == TX Byte 0 ==
2973 22:55:37.034244 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2974 22:55:37.041036 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2975 22:55:37.041483 == TX Byte 1 ==
2976 22:55:37.047398 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2977 22:55:37.050689 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2978 22:55:37.051060 ==
2979 22:55:37.054180 Dram Type= 6, Freq= 0, CH_0, rank 1
2980 22:55:37.057356 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2981 22:55:37.057744 ==
2982 22:55:37.070114 TX Vref=22, minBit 10, minWin=25, winSum=424
2983 22:55:37.073597 TX Vref=24, minBit 1, minWin=26, winSum=426
2984 22:55:37.076790 TX Vref=26, minBit 1, minWin=26, winSum=431
2985 22:55:37.079711 TX Vref=28, minBit 13, minWin=26, winSum=432
2986 22:55:37.083670 TX Vref=30, minBit 12, minWin=26, winSum=433
2987 22:55:37.089718 TX Vref=32, minBit 4, minWin=26, winSum=433
2988 22:55:37.092987 [TxChooseVref] Worse bit 12, Min win 26, Win sum 433, Final Vref 30
2989 22:55:37.093200
2990 22:55:37.096793 Final TX Range 1 Vref 30
2991 22:55:37.096965
2992 22:55:37.097098 ==
2993 22:55:37.099766 Dram Type= 6, Freq= 0, CH_0, rank 1
2994 22:55:37.103586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2995 22:55:37.106391 ==
2996 22:55:37.106524
2997 22:55:37.106623
2998 22:55:37.106717 TX Vref Scan disable
2999 22:55:37.109839 == TX Byte 0 ==
3000 22:55:37.113754 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
3001 22:55:37.119739 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
3002 22:55:37.119838 == TX Byte 1 ==
3003 22:55:37.123311 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3004 22:55:37.130018 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3005 22:55:37.130156
3006 22:55:37.130225 [DATLAT]
3007 22:55:37.130285 Freq=1200, CH0 RK1
3008 22:55:37.130344
3009 22:55:37.133469 DATLAT Default: 0xd
3010 22:55:37.133552 0, 0xFFFF, sum = 0
3011 22:55:37.136340 1, 0xFFFF, sum = 0
3012 22:55:37.139689 2, 0xFFFF, sum = 0
3013 22:55:37.139775 3, 0xFFFF, sum = 0
3014 22:55:37.142746 4, 0xFFFF, sum = 0
3015 22:55:37.142830 5, 0xFFFF, sum = 0
3016 22:55:37.146157 6, 0xFFFF, sum = 0
3017 22:55:37.146241 7, 0xFFFF, sum = 0
3018 22:55:37.150107 8, 0xFFFF, sum = 0
3019 22:55:37.150191 9, 0xFFFF, sum = 0
3020 22:55:37.152872 10, 0xFFFF, sum = 0
3021 22:55:37.152955 11, 0xFFFF, sum = 0
3022 22:55:37.156351 12, 0x0, sum = 1
3023 22:55:37.156434 13, 0x0, sum = 2
3024 22:55:37.159580 14, 0x0, sum = 3
3025 22:55:37.159664 15, 0x0, sum = 4
3026 22:55:37.163234 best_step = 13
3027 22:55:37.163316
3028 22:55:37.163381 ==
3029 22:55:37.166122 Dram Type= 6, Freq= 0, CH_0, rank 1
3030 22:55:37.169757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3031 22:55:37.169840 ==
3032 22:55:37.169905 RX Vref Scan: 0
3033 22:55:37.169965
3034 22:55:37.172775 RX Vref 0 -> 0, step: 1
3035 22:55:37.172858
3036 22:55:37.176148 RX Delay -21 -> 252, step: 4
3037 22:55:37.179640 iDelay=195, Bit 0, Center 112 (47 ~ 178) 132
3038 22:55:37.186053 iDelay=195, Bit 1, Center 116 (47 ~ 186) 140
3039 22:55:37.189454 iDelay=195, Bit 2, Center 112 (47 ~ 178) 132
3040 22:55:37.192839 iDelay=195, Bit 3, Center 112 (47 ~ 178) 132
3041 22:55:37.196040 iDelay=195, Bit 4, Center 118 (51 ~ 186) 136
3042 22:55:37.202615 iDelay=195, Bit 5, Center 108 (43 ~ 174) 132
3043 22:55:37.205747 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3044 22:55:37.209850 iDelay=195, Bit 7, Center 122 (55 ~ 190) 136
3045 22:55:37.212698 iDelay=195, Bit 8, Center 96 (27 ~ 166) 140
3046 22:55:37.216171 iDelay=195, Bit 9, Center 92 (23 ~ 162) 140
3047 22:55:37.219099 iDelay=195, Bit 10, Center 106 (39 ~ 174) 136
3048 22:55:37.225744 iDelay=195, Bit 11, Center 98 (31 ~ 166) 136
3049 22:55:37.228972 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3050 22:55:37.232458 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3051 22:55:37.235672 iDelay=195, Bit 14, Center 118 (51 ~ 186) 136
3052 22:55:37.239507 iDelay=195, Bit 15, Center 112 (47 ~ 178) 132
3053 22:55:37.242674 ==
3054 22:55:37.246229 Dram Type= 6, Freq= 0, CH_0, rank 1
3055 22:55:37.248910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3056 22:55:37.248993 ==
3057 22:55:37.249060 DQS Delay:
3058 22:55:37.252340 DQS0 = 0, DQS1 = 0
3059 22:55:37.252424 DQM Delay:
3060 22:55:37.255769 DQM0 = 115, DQM1 = 105
3061 22:55:37.255853 DQ Delay:
3062 22:55:37.259221 DQ0 =112, DQ1 =116, DQ2 =112, DQ3 =112
3063 22:55:37.262527 DQ4 =118, DQ5 =108, DQ6 =126, DQ7 =122
3064 22:55:37.265985 DQ8 =96, DQ9 =92, DQ10 =106, DQ11 =98
3065 22:55:37.268796 DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =112
3066 22:55:37.268879
3067 22:55:37.268945
3068 22:55:37.279221 [DQSOSCAuto] RK1, (LSB)MR18= 0x1fe, (MSB)MR19= 0x403, tDQSOscB0 = 410 ps tDQSOscB1 = 409 ps
3069 22:55:37.279306 CH0 RK1: MR19=403, MR18=1FE
3070 22:55:37.285833 CH0_RK1: MR19=0x403, MR18=0x1FE, DQSOSC=409, MR23=63, INC=39, DEC=26
3071 22:55:37.289544 [RxdqsGatingPostProcess] freq 1200
3072 22:55:37.295558 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3073 22:55:37.298786 best DQS0 dly(2T, 0.5T) = (0, 11)
3074 22:55:37.302397 best DQS1 dly(2T, 0.5T) = (0, 12)
3075 22:55:37.305672 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3076 22:55:37.309019 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3077 22:55:37.311931 best DQS0 dly(2T, 0.5T) = (0, 11)
3078 22:55:37.312044 best DQS1 dly(2T, 0.5T) = (0, 11)
3079 22:55:37.315272 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3080 22:55:37.318870 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3081 22:55:37.322071 Pre-setting of DQS Precalculation
3082 22:55:37.328807 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3083 22:55:37.328892 ==
3084 22:55:37.332090 Dram Type= 6, Freq= 0, CH_1, rank 0
3085 22:55:37.335490 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3086 22:55:37.335574 ==
3087 22:55:37.341889 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3088 22:55:37.348901 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3089 22:55:37.355900 [CA 0] Center 38 (8~68) winsize 61
3090 22:55:37.359397 [CA 1] Center 37 (7~68) winsize 62
3091 22:55:37.362611 [CA 2] Center 35 (5~65) winsize 61
3092 22:55:37.365453 [CA 3] Center 34 (4~64) winsize 61
3093 22:55:37.369174 [CA 4] Center 34 (5~64) winsize 60
3094 22:55:37.372506 [CA 5] Center 33 (3~64) winsize 62
3095 22:55:37.372590
3096 22:55:37.375372 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3097 22:55:37.375456
3098 22:55:37.378922 [CATrainingPosCal] consider 1 rank data
3099 22:55:37.382160 u2DelayCellTimex100 = 270/100 ps
3100 22:55:37.385396 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3101 22:55:37.392116 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3102 22:55:37.395290 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3103 22:55:37.398709 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3104 22:55:37.402036 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3105 22:55:37.405792 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3106 22:55:37.405895
3107 22:55:37.408772 CA PerBit enable=1, Macro0, CA PI delay=33
3108 22:55:37.408859
3109 22:55:37.412337 [CBTSetCACLKResult] CA Dly = 33
3110 22:55:37.415345 CS Dly: 4 (0~35)
3111 22:55:37.415436 ==
3112 22:55:37.419217 Dram Type= 6, Freq= 0, CH_1, rank 1
3113 22:55:37.422276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3114 22:55:37.422379 ==
3115 22:55:37.425450 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3116 22:55:37.432015 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3117 22:55:37.441343 [CA 0] Center 37 (7~68) winsize 62
3118 22:55:37.444518 [CA 1] Center 38 (8~68) winsize 61
3119 22:55:37.448139 [CA 2] Center 35 (5~65) winsize 61
3120 22:55:37.451721 [CA 3] Center 33 (3~64) winsize 62
3121 22:55:37.454986 [CA 4] Center 34 (4~64) winsize 61
3122 22:55:37.458225 [CA 5] Center 33 (3~64) winsize 62
3123 22:55:37.458418
3124 22:55:37.461367 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3125 22:55:37.461537
3126 22:55:37.464519 [CATrainingPosCal] consider 2 rank data
3127 22:55:37.468312 u2DelayCellTimex100 = 270/100 ps
3128 22:55:37.471548 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3129 22:55:37.478266 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3130 22:55:37.481402 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3131 22:55:37.484894 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3132 22:55:37.487934 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3133 22:55:37.491445 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3134 22:55:37.491849
3135 22:55:37.495126 CA PerBit enable=1, Macro0, CA PI delay=33
3136 22:55:37.495628
3137 22:55:37.498461 [CBTSetCACLKResult] CA Dly = 33
3138 22:55:37.498946 CS Dly: 6 (0~39)
3139 22:55:37.501832
3140 22:55:37.504859 ----->DramcWriteLeveling(PI) begin...
3141 22:55:37.505354 ==
3142 22:55:37.508521 Dram Type= 6, Freq= 0, CH_1, rank 0
3143 22:55:37.511797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3144 22:55:37.512314 ==
3145 22:55:37.514750 Write leveling (Byte 0): 24 => 24
3146 22:55:37.518228 Write leveling (Byte 1): 28 => 28
3147 22:55:37.521306 DramcWriteLeveling(PI) end<-----
3148 22:55:37.521826
3149 22:55:37.522161 ==
3150 22:55:37.524733 Dram Type= 6, Freq= 0, CH_1, rank 0
3151 22:55:37.527855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3152 22:55:37.528306 ==
3153 22:55:37.531385 [Gating] SW mode calibration
3154 22:55:37.537843 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3155 22:55:37.544860 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3156 22:55:37.547586 0 15 0 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
3157 22:55:37.551617 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3158 22:55:37.557920 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3159 22:55:37.561880 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3160 22:55:37.564121 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3161 22:55:37.570973 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3162 22:55:37.574020 0 15 24 | B1->B0 | 3434 2f2f | 0 1 | (0 1) (1 0)
3163 22:55:37.577382 0 15 28 | B1->B0 | 2929 2424 | 0 0 | (0 0) (1 0)
3164 22:55:37.584621 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3165 22:55:37.587537 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3166 22:55:37.590799 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3167 22:55:37.597286 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3168 22:55:37.600727 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3169 22:55:37.604195 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3170 22:55:37.611132 1 0 24 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
3171 22:55:37.614444 1 0 28 | B1->B0 | 3c3c 4545 | 0 0 | (0 0) (0 0)
3172 22:55:37.617546 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3173 22:55:37.624226 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3174 22:55:37.627420 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3175 22:55:37.631203 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3176 22:55:37.634305 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3177 22:55:37.640701 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3178 22:55:37.644019 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3179 22:55:37.647296 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3180 22:55:37.654170 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3181 22:55:37.657968 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3182 22:55:37.660943 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3183 22:55:37.667360 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3184 22:55:37.670756 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3185 22:55:37.674646 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3186 22:55:37.681298 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3187 22:55:37.684144 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3188 22:55:37.687311 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3189 22:55:37.693985 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3190 22:55:37.697055 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3191 22:55:37.700418 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3192 22:55:37.706909 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3193 22:55:37.710651 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3194 22:55:37.713428 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3195 22:55:37.720405 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3196 22:55:37.723811 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3197 22:55:37.727030 Total UI for P1: 0, mck2ui 16
3198 22:55:37.730598 best dqsien dly found for B0: ( 1, 3, 26)
3199 22:55:37.733656 Total UI for P1: 0, mck2ui 16
3200 22:55:37.737163 best dqsien dly found for B1: ( 1, 3, 28)
3201 22:55:37.740150 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3202 22:55:37.743454 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3203 22:55:37.743982
3204 22:55:37.746510 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3205 22:55:37.750229 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3206 22:55:37.754120 [Gating] SW calibration Done
3207 22:55:37.754652 ==
3208 22:55:37.757128 Dram Type= 6, Freq= 0, CH_1, rank 0
3209 22:55:37.760547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3210 22:55:37.763905 ==
3211 22:55:37.764468 RX Vref Scan: 0
3212 22:55:37.764813
3213 22:55:37.767175 RX Vref 0 -> 0, step: 1
3214 22:55:37.767706
3215 22:55:37.768077 RX Delay -40 -> 252, step: 8
3216 22:55:37.773630 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3217 22:55:37.777147 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3218 22:55:37.780072 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3219 22:55:37.783624 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3220 22:55:37.786847 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3221 22:55:37.793669 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3222 22:55:37.797270 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3223 22:55:37.799956 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3224 22:55:37.802907 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3225 22:55:37.806663 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3226 22:55:37.813139 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3227 22:55:37.816084 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3228 22:55:37.819835 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3229 22:55:37.823085 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3230 22:55:37.829906 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3231 22:55:37.832694 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3232 22:55:37.833115 ==
3233 22:55:37.836425 Dram Type= 6, Freq= 0, CH_1, rank 0
3234 22:55:37.839845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3235 22:55:37.840415 ==
3236 22:55:37.842568 DQS Delay:
3237 22:55:37.842985 DQS0 = 0, DQS1 = 0
3238 22:55:37.843315 DQM Delay:
3239 22:55:37.846165 DQM0 = 115, DQM1 = 112
3240 22:55:37.846596 DQ Delay:
3241 22:55:37.849448 DQ0 =119, DQ1 =111, DQ2 =107, DQ3 =115
3242 22:55:37.852752 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =111
3243 22:55:37.859713 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
3244 22:55:37.862997 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3245 22:55:37.863534
3246 22:55:37.863873
3247 22:55:37.864230 ==
3248 22:55:37.866108 Dram Type= 6, Freq= 0, CH_1, rank 0
3249 22:55:37.869150 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3250 22:55:37.869692 ==
3251 22:55:37.870046
3252 22:55:37.870361
3253 22:55:37.873010 TX Vref Scan disable
3254 22:55:37.873560 == TX Byte 0 ==
3255 22:55:37.879137 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3256 22:55:37.882592 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3257 22:55:37.885668 == TX Byte 1 ==
3258 22:55:37.888999 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3259 22:55:37.892250 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3260 22:55:37.892776 ==
3261 22:55:37.895562 Dram Type= 6, Freq= 0, CH_1, rank 0
3262 22:55:37.899541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3263 22:55:37.900147 ==
3264 22:55:37.912149 TX Vref=22, minBit 8, minWin=24, winSum=410
3265 22:55:37.915684 TX Vref=24, minBit 2, minWin=25, winSum=417
3266 22:55:37.918397 TX Vref=26, minBit 8, minWin=25, winSum=425
3267 22:55:37.921926 TX Vref=28, minBit 9, minWin=25, winSum=426
3268 22:55:37.925265 TX Vref=30, minBit 3, minWin=26, winSum=431
3269 22:55:37.931752 TX Vref=32, minBit 11, minWin=25, winSum=429
3270 22:55:37.935051 [TxChooseVref] Worse bit 3, Min win 26, Win sum 431, Final Vref 30
3271 22:55:37.935502
3272 22:55:37.938521 Final TX Range 1 Vref 30
3273 22:55:37.939056
3274 22:55:37.939507 ==
3275 22:55:37.941951 Dram Type= 6, Freq= 0, CH_1, rank 0
3276 22:55:37.944990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3277 22:55:37.948100 ==
3278 22:55:37.948541
3279 22:55:37.948980
3280 22:55:37.949394 TX Vref Scan disable
3281 22:55:37.951978 == TX Byte 0 ==
3282 22:55:37.955341 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3283 22:55:37.961748 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3284 22:55:37.962196 == TX Byte 1 ==
3285 22:55:37.965443 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3286 22:55:37.971989 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3287 22:55:37.972584
3288 22:55:37.973032 [DATLAT]
3289 22:55:37.973447 Freq=1200, CH1 RK0
3290 22:55:37.973871
3291 22:55:37.975214 DATLAT Default: 0xd
3292 22:55:37.975655 0, 0xFFFF, sum = 0
3293 22:55:37.978408 1, 0xFFFF, sum = 0
3294 22:55:37.981727 2, 0xFFFF, sum = 0
3295 22:55:37.982257 3, 0xFFFF, sum = 0
3296 22:55:37.985331 4, 0xFFFF, sum = 0
3297 22:55:37.985870 5, 0xFFFF, sum = 0
3298 22:55:37.988450 6, 0xFFFF, sum = 0
3299 22:55:37.988991 7, 0xFFFF, sum = 0
3300 22:55:37.991766 8, 0xFFFF, sum = 0
3301 22:55:37.992404 9, 0xFFFF, sum = 0
3302 22:55:37.995843 10, 0xFFFF, sum = 0
3303 22:55:37.996429 11, 0xFFFF, sum = 0
3304 22:55:37.998658 12, 0x0, sum = 1
3305 22:55:37.999202 13, 0x0, sum = 2
3306 22:55:38.001983 14, 0x0, sum = 3
3307 22:55:38.002524 15, 0x0, sum = 4
3308 22:55:38.005603 best_step = 13
3309 22:55:38.006151
3310 22:55:38.006632 ==
3311 22:55:38.008354 Dram Type= 6, Freq= 0, CH_1, rank 0
3312 22:55:38.011308 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3313 22:55:38.011751 ==
3314 22:55:38.012299 RX Vref Scan: 1
3315 22:55:38.015515
3316 22:55:38.015956 Set Vref Range= 32 -> 127
3317 22:55:38.016552
3318 22:55:38.018318 RX Vref 32 -> 127, step: 1
3319 22:55:38.018900
3320 22:55:38.021538 RX Delay -13 -> 252, step: 4
3321 22:55:38.021962
3322 22:55:38.024783 Set Vref, RX VrefLevel [Byte0]: 32
3323 22:55:38.028170 [Byte1]: 32
3324 22:55:38.028561
3325 22:55:38.031418 Set Vref, RX VrefLevel [Byte0]: 33
3326 22:55:38.034684 [Byte1]: 33
3327 22:55:38.038775
3328 22:55:38.039342 Set Vref, RX VrefLevel [Byte0]: 34
3329 22:55:38.041594 [Byte1]: 34
3330 22:55:38.046314
3331 22:55:38.046793 Set Vref, RX VrefLevel [Byte0]: 35
3332 22:55:38.049675 [Byte1]: 35
3333 22:55:38.054647
3334 22:55:38.055168 Set Vref, RX VrefLevel [Byte0]: 36
3335 22:55:38.058083 [Byte1]: 36
3336 22:55:38.062420
3337 22:55:38.062989 Set Vref, RX VrefLevel [Byte0]: 37
3338 22:55:38.065607 [Byte1]: 37
3339 22:55:38.070171
3340 22:55:38.070690 Set Vref, RX VrefLevel [Byte0]: 38
3341 22:55:38.073586 [Byte1]: 38
3342 22:55:38.079000
3343 22:55:38.079515 Set Vref, RX VrefLevel [Byte0]: 39
3344 22:55:38.080817 [Byte1]: 39
3345 22:55:38.085371
3346 22:55:38.085782 Set Vref, RX VrefLevel [Byte0]: 40
3347 22:55:38.088923 [Byte1]: 40
3348 22:55:38.093279
3349 22:55:38.093692 Set Vref, RX VrefLevel [Byte0]: 41
3350 22:55:38.096762 [Byte1]: 41
3351 22:55:38.101240
3352 22:55:38.101619 Set Vref, RX VrefLevel [Byte0]: 42
3353 22:55:38.104390 [Byte1]: 42
3354 22:55:38.109190
3355 22:55:38.109565 Set Vref, RX VrefLevel [Byte0]: 43
3356 22:55:38.113168 [Byte1]: 43
3357 22:55:38.117069
3358 22:55:38.117544 Set Vref, RX VrefLevel [Byte0]: 44
3359 22:55:38.121334 [Byte1]: 44
3360 22:55:38.125000
3361 22:55:38.125677 Set Vref, RX VrefLevel [Byte0]: 45
3362 22:55:38.128344 [Byte1]: 45
3363 22:55:38.133281
3364 22:55:38.133846 Set Vref, RX VrefLevel [Byte0]: 46
3365 22:55:38.136091 [Byte1]: 46
3366 22:55:38.140862
3367 22:55:38.141439 Set Vref, RX VrefLevel [Byte0]: 47
3368 22:55:38.144386 [Byte1]: 47
3369 22:55:38.148592
3370 22:55:38.149004 Set Vref, RX VrefLevel [Byte0]: 48
3371 22:55:38.152086 [Byte1]: 48
3372 22:55:38.156725
3373 22:55:38.157230 Set Vref, RX VrefLevel [Byte0]: 49
3374 22:55:38.160220 [Byte1]: 49
3375 22:55:38.164871
3376 22:55:38.165377 Set Vref, RX VrefLevel [Byte0]: 50
3377 22:55:38.167819 [Byte1]: 50
3378 22:55:38.172392
3379 22:55:38.172913 Set Vref, RX VrefLevel [Byte0]: 51
3380 22:55:38.175704 [Byte1]: 51
3381 22:55:38.180630
3382 22:55:38.181138 Set Vref, RX VrefLevel [Byte0]: 52
3383 22:55:38.183548 [Byte1]: 52
3384 22:55:38.188393
3385 22:55:38.188903 Set Vref, RX VrefLevel [Byte0]: 53
3386 22:55:38.191729 [Byte1]: 53
3387 22:55:38.196115
3388 22:55:38.196619 Set Vref, RX VrefLevel [Byte0]: 54
3389 22:55:38.199287 [Byte1]: 54
3390 22:55:38.204187
3391 22:55:38.204691 Set Vref, RX VrefLevel [Byte0]: 55
3392 22:55:38.207641 [Byte1]: 55
3393 22:55:38.211988
3394 22:55:38.212537 Set Vref, RX VrefLevel [Byte0]: 56
3395 22:55:38.215032 [Byte1]: 56
3396 22:55:38.219399
3397 22:55:38.219815 Set Vref, RX VrefLevel [Byte0]: 57
3398 22:55:38.223439 [Byte1]: 57
3399 22:55:38.228186
3400 22:55:38.228693 Set Vref, RX VrefLevel [Byte0]: 58
3401 22:55:38.230982 [Byte1]: 58
3402 22:55:38.235500
3403 22:55:38.235938 Set Vref, RX VrefLevel [Byte0]: 59
3404 22:55:38.238400 [Byte1]: 59
3405 22:55:38.243570
3406 22:55:38.244148 Set Vref, RX VrefLevel [Byte0]: 60
3407 22:55:38.246722 [Byte1]: 60
3408 22:55:38.251881
3409 22:55:38.252490 Set Vref, RX VrefLevel [Byte0]: 61
3410 22:55:38.254419 [Byte1]: 61
3411 22:55:38.258854
3412 22:55:38.259370 Set Vref, RX VrefLevel [Byte0]: 62
3413 22:55:38.262804 [Byte1]: 62
3414 22:55:38.267498
3415 22:55:38.268017 Set Vref, RX VrefLevel [Byte0]: 63
3416 22:55:38.270383 [Byte1]: 63
3417 22:55:38.275188
3418 22:55:38.275707 Set Vref, RX VrefLevel [Byte0]: 64
3419 22:55:38.278925 [Byte1]: 64
3420 22:55:38.282542
3421 22:55:38.283063 Set Vref, RX VrefLevel [Byte0]: 65
3422 22:55:38.286433 [Byte1]: 65
3423 22:55:38.290803
3424 22:55:38.291322 Set Vref, RX VrefLevel [Byte0]: 66
3425 22:55:38.294011 [Byte1]: 66
3426 22:55:38.299134
3427 22:55:38.299652 Final RX Vref Byte 0 = 50 to rank0
3428 22:55:38.301869 Final RX Vref Byte 1 = 49 to rank0
3429 22:55:38.305260 Final RX Vref Byte 0 = 50 to rank1
3430 22:55:38.308594 Final RX Vref Byte 1 = 49 to rank1==
3431 22:55:38.311927 Dram Type= 6, Freq= 0, CH_1, rank 0
3432 22:55:38.318893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3433 22:55:38.319450 ==
3434 22:55:38.319805 DQS Delay:
3435 22:55:38.320166 DQS0 = 0, DQS1 = 0
3436 22:55:38.321732 DQM Delay:
3437 22:55:38.322283 DQM0 = 115, DQM1 = 112
3438 22:55:38.325459 DQ Delay:
3439 22:55:38.328499 DQ0 =120, DQ1 =110, DQ2 =106, DQ3 =116
3440 22:55:38.332065 DQ4 =110, DQ5 =122, DQ6 =126, DQ7 =110
3441 22:55:38.335394 DQ8 =98, DQ9 =102, DQ10 =114, DQ11 =106
3442 22:55:38.338292 DQ12 =120, DQ13 =120, DQ14 =118, DQ15 =120
3443 22:55:38.338963
3444 22:55:38.339454
3445 22:55:38.347992 [DQSOSCAuto] RK0, (LSB)MR18= 0xf3ff, (MSB)MR19= 0x303, tDQSOscB0 = 410 ps tDQSOscB1 = 415 ps
3446 22:55:38.348675 CH1 RK0: MR19=303, MR18=F3FF
3447 22:55:38.354924 CH1_RK0: MR19=0x303, MR18=0xF3FF, DQSOSC=410, MR23=63, INC=39, DEC=26
3448 22:55:38.355441
3449 22:55:38.357829 ----->DramcWriteLeveling(PI) begin...
3450 22:55:38.358258 ==
3451 22:55:38.361434 Dram Type= 6, Freq= 0, CH_1, rank 1
3452 22:55:38.368774 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3453 22:55:38.369300 ==
3454 22:55:38.371229 Write leveling (Byte 0): 25 => 25
3455 22:55:38.371650 Write leveling (Byte 1): 27 => 27
3456 22:55:38.374773 DramcWriteLeveling(PI) end<-----
3457 22:55:38.375290
3458 22:55:38.378266 ==
3459 22:55:38.378786 Dram Type= 6, Freq= 0, CH_1, rank 1
3460 22:55:38.384497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3461 22:55:38.384920 ==
3462 22:55:38.387955 [Gating] SW mode calibration
3463 22:55:38.394742 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3464 22:55:38.398553 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3465 22:55:38.404639 0 15 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
3466 22:55:38.408246 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3467 22:55:38.411689 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3468 22:55:38.418361 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3469 22:55:38.421627 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3470 22:55:38.424684 0 15 20 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
3471 22:55:38.431378 0 15 24 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (0 1)
3472 22:55:38.434989 0 15 28 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)
3473 22:55:38.437729 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3474 22:55:38.444801 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3475 22:55:38.447648 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3476 22:55:38.451360 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3477 22:55:38.457884 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3478 22:55:38.460685 1 0 20 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
3479 22:55:38.464316 1 0 24 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)
3480 22:55:38.471550 1 0 28 | B1->B0 | 3d3d 4646 | 0 0 | (1 1) (0 0)
3481 22:55:38.474301 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3482 22:55:38.477183 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3483 22:55:38.484488 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3484 22:55:38.487598 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3485 22:55:38.490491 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3486 22:55:38.497566 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3487 22:55:38.500335 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3488 22:55:38.504026 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3489 22:55:38.510710 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3490 22:55:38.513403 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3491 22:55:38.517059 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3492 22:55:38.523323 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3493 22:55:38.527053 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3494 22:55:38.529904 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3495 22:55:38.536565 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3496 22:55:38.539571 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3497 22:55:38.543454 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3498 22:55:38.549510 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3499 22:55:38.552612 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3500 22:55:38.556195 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3501 22:55:38.562785 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3502 22:55:38.566025 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3503 22:55:38.569573 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3504 22:55:38.576120 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3505 22:55:38.580215 Total UI for P1: 0, mck2ui 16
3506 22:55:38.582496 best dqsien dly found for B0: ( 1, 3, 22)
3507 22:55:38.585466 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3508 22:55:38.588372 Total UI for P1: 0, mck2ui 16
3509 22:55:38.592077 best dqsien dly found for B1: ( 1, 3, 28)
3510 22:55:38.595523 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3511 22:55:38.599147 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3512 22:55:38.599680
3513 22:55:38.601840 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3514 22:55:38.605861 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3515 22:55:38.608906 [Gating] SW calibration Done
3516 22:55:38.609439 ==
3517 22:55:38.612255 Dram Type= 6, Freq= 0, CH_1, rank 1
3518 22:55:38.618853 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3519 22:55:38.619396 ==
3520 22:55:38.619743 RX Vref Scan: 0
3521 22:55:38.620098
3522 22:55:38.621743 RX Vref 0 -> 0, step: 1
3523 22:55:38.622172
3524 22:55:38.625268 RX Delay -40 -> 252, step: 8
3525 22:55:38.628410 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3526 22:55:38.631593 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3527 22:55:38.634976 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3528 22:55:38.641805 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3529 22:55:38.644755 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3530 22:55:38.648363 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3531 22:55:38.651909 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3532 22:55:38.654772 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3533 22:55:38.661880 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3534 22:55:38.664608 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3535 22:55:38.668459 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3536 22:55:38.671506 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3537 22:55:38.674475 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3538 22:55:38.680840 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3539 22:55:38.684469 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3540 22:55:38.687503 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3541 22:55:38.688080 ==
3542 22:55:38.690965 Dram Type= 6, Freq= 0, CH_1, rank 1
3543 22:55:38.693961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3544 22:55:38.697529 ==
3545 22:55:38.698061 DQS Delay:
3546 22:55:38.698406 DQS0 = 0, DQS1 = 0
3547 22:55:38.700909 DQM Delay:
3548 22:55:38.701459 DQM0 = 115, DQM1 = 111
3549 22:55:38.704178 DQ Delay:
3550 22:55:38.707457 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =115
3551 22:55:38.710580 DQ4 =119, DQ5 =123, DQ6 =119, DQ7 =111
3552 22:55:38.714210 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3553 22:55:38.717792 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3554 22:55:38.718326
3555 22:55:38.718666
3556 22:55:38.718983 ==
3557 22:55:38.720476 Dram Type= 6, Freq= 0, CH_1, rank 1
3558 22:55:38.723591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3559 22:55:38.724025 ==
3560 22:55:38.726931
3561 22:55:38.727356
3562 22:55:38.727693 TX Vref Scan disable
3563 22:55:38.730468 == TX Byte 0 ==
3564 22:55:38.733877 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3565 22:55:38.736690 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3566 22:55:38.740107 == TX Byte 1 ==
3567 22:55:38.743818 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3568 22:55:38.746895 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3569 22:55:38.749956 ==
3570 22:55:38.750394 Dram Type= 6, Freq= 0, CH_1, rank 1
3571 22:55:38.756925 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3572 22:55:38.757471 ==
3573 22:55:38.767467 TX Vref=22, minBit 9, minWin=25, winSum=421
3574 22:55:38.770702 TX Vref=24, minBit 9, minWin=25, winSum=422
3575 22:55:38.773976 TX Vref=26, minBit 9, minWin=25, winSum=427
3576 22:55:38.777312 TX Vref=28, minBit 9, minWin=25, winSum=430
3577 22:55:38.781083 TX Vref=30, minBit 1, minWin=26, winSum=429
3578 22:55:38.787286 TX Vref=32, minBit 9, minWin=25, winSum=429
3579 22:55:38.790427 [TxChooseVref] Worse bit 1, Min win 26, Win sum 429, Final Vref 30
3580 22:55:38.790972
3581 22:55:38.793637 Final TX Range 1 Vref 30
3582 22:55:38.794066
3583 22:55:38.794410 ==
3584 22:55:38.796656 Dram Type= 6, Freq= 0, CH_1, rank 1
3585 22:55:38.800337 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3586 22:55:38.803580 ==
3587 22:55:38.804009
3588 22:55:38.804427
3589 22:55:38.804748 TX Vref Scan disable
3590 22:55:38.806861 == TX Byte 0 ==
3591 22:55:38.810501 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3592 22:55:38.816981 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3593 22:55:38.817514 == TX Byte 1 ==
3594 22:55:38.820785 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3595 22:55:38.827030 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3596 22:55:38.827571
3597 22:55:38.827916 [DATLAT]
3598 22:55:38.828296 Freq=1200, CH1 RK1
3599 22:55:38.828613
3600 22:55:38.830553 DATLAT Default: 0xd
3601 22:55:38.833427 0, 0xFFFF, sum = 0
3602 22:55:38.833864 1, 0xFFFF, sum = 0
3603 22:55:38.836848 2, 0xFFFF, sum = 0
3604 22:55:38.837287 3, 0xFFFF, sum = 0
3605 22:55:38.840081 4, 0xFFFF, sum = 0
3606 22:55:38.840517 5, 0xFFFF, sum = 0
3607 22:55:38.843610 6, 0xFFFF, sum = 0
3608 22:55:38.844186 7, 0xFFFF, sum = 0
3609 22:55:38.846583 8, 0xFFFF, sum = 0
3610 22:55:38.847015 9, 0xFFFF, sum = 0
3611 22:55:38.849906 10, 0xFFFF, sum = 0
3612 22:55:38.850343 11, 0xFFFF, sum = 0
3613 22:55:38.853065 12, 0x0, sum = 1
3614 22:55:38.853599 13, 0x0, sum = 2
3615 22:55:38.856680 14, 0x0, sum = 3
3616 22:55:38.857221 15, 0x0, sum = 4
3617 22:55:38.859694 best_step = 13
3618 22:55:38.860253
3619 22:55:38.860598 ==
3620 22:55:38.863196 Dram Type= 6, Freq= 0, CH_1, rank 1
3621 22:55:38.866552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3622 22:55:38.867089 ==
3623 22:55:38.869653 RX Vref Scan: 0
3624 22:55:38.870183
3625 22:55:38.870528 RX Vref 0 -> 0, step: 1
3626 22:55:38.870850
3627 22:55:38.872717 RX Delay -13 -> 252, step: 4
3628 22:55:38.879529 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3629 22:55:38.882662 iDelay=195, Bit 1, Center 112 (43 ~ 182) 140
3630 22:55:38.886737 iDelay=195, Bit 2, Center 106 (39 ~ 174) 136
3631 22:55:38.889758 iDelay=195, Bit 3, Center 114 (47 ~ 182) 136
3632 22:55:38.892957 iDelay=195, Bit 4, Center 114 (47 ~ 182) 136
3633 22:55:38.899249 iDelay=195, Bit 5, Center 124 (55 ~ 194) 140
3634 22:55:38.902570 iDelay=195, Bit 6, Center 122 (55 ~ 190) 136
3635 22:55:38.905946 iDelay=195, Bit 7, Center 112 (43 ~ 182) 140
3636 22:55:38.908942 iDelay=195, Bit 8, Center 100 (39 ~ 162) 124
3637 22:55:38.915627 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3638 22:55:38.918961 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3639 22:55:38.921972 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3640 22:55:38.925698 iDelay=195, Bit 12, Center 120 (59 ~ 182) 124
3641 22:55:38.928832 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3642 22:55:38.935270 iDelay=195, Bit 14, Center 116 (55 ~ 178) 124
3643 22:55:38.938691 iDelay=195, Bit 15, Center 122 (59 ~ 186) 128
3644 22:55:38.939226 ==
3645 22:55:38.942440 Dram Type= 6, Freq= 0, CH_1, rank 1
3646 22:55:38.945514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3647 22:55:38.946054 ==
3648 22:55:38.948645 DQS Delay:
3649 22:55:38.949174 DQS0 = 0, DQS1 = 0
3650 22:55:38.949524 DQM Delay:
3651 22:55:38.951713 DQM0 = 115, DQM1 = 112
3652 22:55:38.952181 DQ Delay:
3653 22:55:38.955277 DQ0 =118, DQ1 =112, DQ2 =106, DQ3 =114
3654 22:55:38.958749 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =112
3655 22:55:38.965521 DQ8 =100, DQ9 =102, DQ10 =114, DQ11 =106
3656 22:55:38.968263 DQ12 =120, DQ13 =118, DQ14 =116, DQ15 =122
3657 22:55:38.968776
3658 22:55:38.969114
3659 22:55:38.975206 [DQSOSCAuto] RK1, (LSB)MR18= 0xf80a, (MSB)MR19= 0x304, tDQSOscB0 = 406 ps tDQSOscB1 = 413 ps
3660 22:55:38.978298 CH1 RK1: MR19=304, MR18=F80A
3661 22:55:38.985487 CH1_RK1: MR19=0x304, MR18=0xF80A, DQSOSC=406, MR23=63, INC=39, DEC=26
3662 22:55:38.988357 [RxdqsGatingPostProcess] freq 1200
3663 22:55:38.995069 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3664 22:55:38.995604 best DQS0 dly(2T, 0.5T) = (0, 11)
3665 22:55:38.997927 best DQS1 dly(2T, 0.5T) = (0, 11)
3666 22:55:39.001294 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3667 22:55:39.005001 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3668 22:55:39.008109 best DQS0 dly(2T, 0.5T) = (0, 11)
3669 22:55:39.011014 best DQS1 dly(2T, 0.5T) = (0, 11)
3670 22:55:39.014739 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3671 22:55:39.017611 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3672 22:55:39.021200 Pre-setting of DQS Precalculation
3673 22:55:39.028181 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3674 22:55:39.034058 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3675 22:55:39.040549 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3676 22:55:39.040994
3677 22:55:39.041334
3678 22:55:39.044418 [Calibration Summary] 2400 Mbps
3679 22:55:39.044849 CH 0, Rank 0
3680 22:55:39.047186 SW Impedance : PASS
3681 22:55:39.050900 DUTY Scan : NO K
3682 22:55:39.051432 ZQ Calibration : PASS
3683 22:55:39.054015 Jitter Meter : NO K
3684 22:55:39.057520 CBT Training : PASS
3685 22:55:39.058052 Write leveling : PASS
3686 22:55:39.060310 RX DQS gating : PASS
3687 22:55:39.063945 RX DQ/DQS(RDDQC) : PASS
3688 22:55:39.064510 TX DQ/DQS : PASS
3689 22:55:39.066868 RX DATLAT : PASS
3690 22:55:39.070492 RX DQ/DQS(Engine): PASS
3691 22:55:39.071029 TX OE : NO K
3692 22:55:39.073467 All Pass.
3693 22:55:39.073897
3694 22:55:39.074240 CH 0, Rank 1
3695 22:55:39.076918 SW Impedance : PASS
3696 22:55:39.077448 DUTY Scan : NO K
3697 22:55:39.080670 ZQ Calibration : PASS
3698 22:55:39.083619 Jitter Meter : NO K
3699 22:55:39.084078 CBT Training : PASS
3700 22:55:39.087074 Write leveling : PASS
3701 22:55:39.090323 RX DQS gating : PASS
3702 22:55:39.090854 RX DQ/DQS(RDDQC) : PASS
3703 22:55:39.093067 TX DQ/DQS : PASS
3704 22:55:39.096671 RX DATLAT : PASS
3705 22:55:39.097203 RX DQ/DQS(Engine): PASS
3706 22:55:39.099879 TX OE : NO K
3707 22:55:39.100463 All Pass.
3708 22:55:39.100815
3709 22:55:39.103321 CH 1, Rank 0
3710 22:55:39.103851 SW Impedance : PASS
3711 22:55:39.106596 DUTY Scan : NO K
3712 22:55:39.107126 ZQ Calibration : PASS
3713 22:55:39.109715 Jitter Meter : NO K
3714 22:55:39.112848 CBT Training : PASS
3715 22:55:39.113275 Write leveling : PASS
3716 22:55:39.116610 RX DQS gating : PASS
3717 22:55:39.119622 RX DQ/DQS(RDDQC) : PASS
3718 22:55:39.120180 TX DQ/DQS : PASS
3719 22:55:39.122903 RX DATLAT : PASS
3720 22:55:39.126619 RX DQ/DQS(Engine): PASS
3721 22:55:39.127050 TX OE : NO K
3722 22:55:39.129499 All Pass.
3723 22:55:39.129930
3724 22:55:39.130272 CH 1, Rank 1
3725 22:55:39.132743 SW Impedance : PASS
3726 22:55:39.133171 DUTY Scan : NO K
3727 22:55:39.136002 ZQ Calibration : PASS
3728 22:55:39.139782 Jitter Meter : NO K
3729 22:55:39.140357 CBT Training : PASS
3730 22:55:39.142796 Write leveling : PASS
3731 22:55:39.146153 RX DQS gating : PASS
3732 22:55:39.146699 RX DQ/DQS(RDDQC) : PASS
3733 22:55:39.149417 TX DQ/DQS : PASS
3734 22:55:39.152598 RX DATLAT : PASS
3735 22:55:39.153027 RX DQ/DQS(Engine): PASS
3736 22:55:39.156562 TX OE : NO K
3737 22:55:39.157095 All Pass.
3738 22:55:39.157438
3739 22:55:39.159253 DramC Write-DBI off
3740 22:55:39.162757 PER_BANK_REFRESH: Hybrid Mode
3741 22:55:39.163288 TX_TRACKING: ON
3742 22:55:39.172539 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3743 22:55:39.175881 [FAST_K] Save calibration result to emmc
3744 22:55:39.179102 dramc_set_vcore_voltage set vcore to 650000
3745 22:55:39.182557 Read voltage for 600, 5
3746 22:55:39.182991 Vio18 = 0
3747 22:55:39.183358 Vcore = 650000
3748 22:55:39.185622 Vdram = 0
3749 22:55:39.186152 Vddq = 0
3750 22:55:39.186496 Vmddr = 0
3751 22:55:39.192378 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3752 22:55:39.196119 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3753 22:55:39.199098 MEM_TYPE=3, freq_sel=19
3754 22:55:39.202191 sv_algorithm_assistance_LP4_1600
3755 22:55:39.205669 ============ PULL DRAM RESETB DOWN ============
3756 22:55:39.211769 ========== PULL DRAM RESETB DOWN end =========
3757 22:55:39.215373 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3758 22:55:39.218546 ===================================
3759 22:55:39.221963 LPDDR4 DRAM CONFIGURATION
3760 22:55:39.225306 ===================================
3761 22:55:39.225740 EX_ROW_EN[0] = 0x0
3762 22:55:39.228712 EX_ROW_EN[1] = 0x0
3763 22:55:39.229145 LP4Y_EN = 0x0
3764 22:55:39.231839 WORK_FSP = 0x0
3765 22:55:39.232287 WL = 0x2
3766 22:55:39.235063 RL = 0x2
3767 22:55:39.235491 BL = 0x2
3768 22:55:39.238822 RPST = 0x0
3769 22:55:39.239250 RD_PRE = 0x0
3770 22:55:39.242367 WR_PRE = 0x1
3771 22:55:39.242894 WR_PST = 0x0
3772 22:55:39.245194 DBI_WR = 0x0
3773 22:55:39.245625 DBI_RD = 0x0
3774 22:55:39.248308 OTF = 0x1
3775 22:55:39.251877 ===================================
3776 22:55:39.255160 ===================================
3777 22:55:39.255684 ANA top config
3778 22:55:39.258684 ===================================
3779 22:55:39.261938 DLL_ASYNC_EN = 0
3780 22:55:39.264801 ALL_SLAVE_EN = 1
3781 22:55:39.268196 NEW_RANK_MODE = 1
3782 22:55:39.271732 DLL_IDLE_MODE = 1
3783 22:55:39.272300 LP45_APHY_COMB_EN = 1
3784 22:55:39.274796 TX_ODT_DIS = 1
3785 22:55:39.278224 NEW_8X_MODE = 1
3786 22:55:39.281637 ===================================
3787 22:55:39.285183 ===================================
3788 22:55:39.288143 data_rate = 1200
3789 22:55:39.291190 CKR = 1
3790 22:55:39.291712 DQ_P2S_RATIO = 8
3791 22:55:39.294778 ===================================
3792 22:55:39.298277 CA_P2S_RATIO = 8
3793 22:55:39.301142 DQ_CA_OPEN = 0
3794 22:55:39.304928 DQ_SEMI_OPEN = 0
3795 22:55:39.308331 CA_SEMI_OPEN = 0
3796 22:55:39.311422 CA_FULL_RATE = 0
3797 22:55:39.311961 DQ_CKDIV4_EN = 1
3798 22:55:39.314447 CA_CKDIV4_EN = 1
3799 22:55:39.317525 CA_PREDIV_EN = 0
3800 22:55:39.320974 PH8_DLY = 0
3801 22:55:39.324173 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3802 22:55:39.328195 DQ_AAMCK_DIV = 4
3803 22:55:39.328883 CA_AAMCK_DIV = 4
3804 22:55:39.331520 CA_ADMCK_DIV = 4
3805 22:55:39.333979 DQ_TRACK_CA_EN = 0
3806 22:55:39.337449 CA_PICK = 600
3807 22:55:39.340577 CA_MCKIO = 600
3808 22:55:39.344237 MCKIO_SEMI = 0
3809 22:55:39.347639 PLL_FREQ = 2288
3810 22:55:39.350118 DQ_UI_PI_RATIO = 32
3811 22:55:39.350555 CA_UI_PI_RATIO = 0
3812 22:55:39.354012 ===================================
3813 22:55:39.356972 ===================================
3814 22:55:39.360918 memory_type:LPDDR4
3815 22:55:39.364186 GP_NUM : 10
3816 22:55:39.364718 SRAM_EN : 1
3817 22:55:39.366754 MD32_EN : 0
3818 22:55:39.370349 ===================================
3819 22:55:39.373463 [ANA_INIT] >>>>>>>>>>>>>>
3820 22:55:39.376937 <<<<<< [CONFIGURE PHASE]: ANA_TX
3821 22:55:39.380625 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3822 22:55:39.383405 ===================================
3823 22:55:39.383948 data_rate = 1200,PCW = 0X5800
3824 22:55:39.386715 ===================================
3825 22:55:39.393783 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3826 22:55:39.396441 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3827 22:55:39.403352 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3828 22:55:39.406588 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3829 22:55:39.409973 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3830 22:55:39.413469 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3831 22:55:39.416220 [ANA_INIT] flow start
3832 22:55:39.420538 [ANA_INIT] PLL >>>>>>>>
3833 22:55:39.421068 [ANA_INIT] PLL <<<<<<<<
3834 22:55:39.423022 [ANA_INIT] MIDPI >>>>>>>>
3835 22:55:39.426396 [ANA_INIT] MIDPI <<<<<<<<
3836 22:55:39.426945 [ANA_INIT] DLL >>>>>>>>
3837 22:55:39.430201 [ANA_INIT] flow end
3838 22:55:39.432851 ============ LP4 DIFF to SE enter ============
3839 22:55:39.439690 ============ LP4 DIFF to SE exit ============
3840 22:55:39.440259 [ANA_INIT] <<<<<<<<<<<<<
3841 22:55:39.443013 [Flow] Enable top DCM control >>>>>
3842 22:55:39.446000 [Flow] Enable top DCM control <<<<<
3843 22:55:39.449025 Enable DLL master slave shuffle
3844 22:55:39.455918 ==============================================================
3845 22:55:39.456478 Gating Mode config
3846 22:55:39.462870 ==============================================================
3847 22:55:39.465659 Config description:
3848 22:55:39.476127 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3849 22:55:39.482570 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3850 22:55:39.485659 SELPH_MODE 0: By rank 1: By Phase
3851 22:55:39.492539 ==============================================================
3852 22:55:39.495622 GAT_TRACK_EN = 1
3853 22:55:39.498838 RX_GATING_MODE = 2
3854 22:55:39.499367 RX_GATING_TRACK_MODE = 2
3855 22:55:39.502331 SELPH_MODE = 1
3856 22:55:39.505670 PICG_EARLY_EN = 1
3857 22:55:39.508520 VALID_LAT_VALUE = 1
3858 22:55:39.515204 ==============================================================
3859 22:55:39.518857 Enter into Gating configuration >>>>
3860 22:55:39.522107 Exit from Gating configuration <<<<
3861 22:55:39.525140 Enter into DVFS_PRE_config >>>>>
3862 22:55:39.535085 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3863 22:55:39.539091 Exit from DVFS_PRE_config <<<<<
3864 22:55:39.541367 Enter into PICG configuration >>>>
3865 22:55:39.544633 Exit from PICG configuration <<<<
3866 22:55:39.548026 [RX_INPUT] configuration >>>>>
3867 22:55:39.551540 [RX_INPUT] configuration <<<<<
3868 22:55:39.554534 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3869 22:55:39.561368 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3870 22:55:39.567923 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3871 22:55:39.574466 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3872 22:55:39.581453 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3873 22:55:39.584161 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3874 22:55:39.590960 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3875 22:55:39.594796 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3876 22:55:39.597932 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3877 22:55:39.600976 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3878 22:55:39.607750 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3879 22:55:39.610971 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3880 22:55:39.614585 ===================================
3881 22:55:39.618010 LPDDR4 DRAM CONFIGURATION
3882 22:55:39.620811 ===================================
3883 22:55:39.621380 EX_ROW_EN[0] = 0x0
3884 22:55:39.623965 EX_ROW_EN[1] = 0x0
3885 22:55:39.624566 LP4Y_EN = 0x0
3886 22:55:39.627463 WORK_FSP = 0x0
3887 22:55:39.627930 WL = 0x2
3888 22:55:39.630698 RL = 0x2
3889 22:55:39.634202 BL = 0x2
3890 22:55:39.634730 RPST = 0x0
3891 22:55:39.636924 RD_PRE = 0x0
3892 22:55:39.637366 WR_PRE = 0x1
3893 22:55:39.640267 WR_PST = 0x0
3894 22:55:39.640691 DBI_WR = 0x0
3895 22:55:39.644199 DBI_RD = 0x0
3896 22:55:39.644717 OTF = 0x1
3897 22:55:39.647049 ===================================
3898 22:55:39.650639 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3899 22:55:39.656868 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3900 22:55:39.660575 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3901 22:55:39.663554 ===================================
3902 22:55:39.666655 LPDDR4 DRAM CONFIGURATION
3903 22:55:39.670082 ===================================
3904 22:55:39.670633 EX_ROW_EN[0] = 0x10
3905 22:55:39.673040 EX_ROW_EN[1] = 0x0
3906 22:55:39.673483 LP4Y_EN = 0x0
3907 22:55:39.676384 WORK_FSP = 0x0
3908 22:55:39.680218 WL = 0x2
3909 22:55:39.680763 RL = 0x2
3910 22:55:39.682896 BL = 0x2
3911 22:55:39.683336 RPST = 0x0
3912 22:55:39.686779 RD_PRE = 0x0
3913 22:55:39.687325 WR_PRE = 0x1
3914 22:55:39.689785 WR_PST = 0x0
3915 22:55:39.690331 DBI_WR = 0x0
3916 22:55:39.692959 DBI_RD = 0x0
3917 22:55:39.693512 OTF = 0x1
3918 22:55:39.696551 ===================================
3919 22:55:39.702847 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3920 22:55:39.707498 nWR fixed to 30
3921 22:55:39.710608 [ModeRegInit_LP4] CH0 RK0
3922 22:55:39.711159 [ModeRegInit_LP4] CH0 RK1
3923 22:55:39.714112 [ModeRegInit_LP4] CH1 RK0
3924 22:55:39.717205 [ModeRegInit_LP4] CH1 RK1
3925 22:55:39.717752 match AC timing 17
3926 22:55:39.724141 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3927 22:55:39.726976 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3928 22:55:39.729998 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3929 22:55:39.736668 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3930 22:55:39.740226 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3931 22:55:39.740772 ==
3932 22:55:39.743635 Dram Type= 6, Freq= 0, CH_0, rank 0
3933 22:55:39.746940 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3934 22:55:39.747476 ==
3935 22:55:39.753316 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3936 22:55:39.760900 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3937 22:55:39.763417 [CA 0] Center 36 (6~67) winsize 62
3938 22:55:39.766598 [CA 1] Center 36 (6~67) winsize 62
3939 22:55:39.770000 [CA 2] Center 34 (4~65) winsize 62
3940 22:55:39.772841 [CA 3] Center 34 (4~65) winsize 62
3941 22:55:39.775985 [CA 4] Center 33 (3~64) winsize 62
3942 22:55:39.779196 [CA 5] Center 33 (3~64) winsize 62
3943 22:55:39.779640
3944 22:55:39.782704 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3945 22:55:39.783245
3946 22:55:39.786445 [CATrainingPosCal] consider 1 rank data
3947 22:55:39.789686 u2DelayCellTimex100 = 270/100 ps
3948 22:55:39.792945 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3949 22:55:39.796328 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3950 22:55:39.800065 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3951 22:55:39.806031 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3952 22:55:39.809571 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3953 22:55:39.812851 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3954 22:55:39.813389
3955 22:55:39.815818 CA PerBit enable=1, Macro0, CA PI delay=33
3956 22:55:39.816402
3957 22:55:39.819610 [CBTSetCACLKResult] CA Dly = 33
3958 22:55:39.820188 CS Dly: 5 (0~36)
3959 22:55:39.820648 ==
3960 22:55:39.822574 Dram Type= 6, Freq= 0, CH_0, rank 1
3961 22:55:39.828804 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3962 22:55:39.829338 ==
3963 22:55:39.832512 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3964 22:55:39.838250 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3965 22:55:39.842481 [CA 0] Center 36 (6~67) winsize 62
3966 22:55:39.845990 [CA 1] Center 36 (6~67) winsize 62
3967 22:55:39.849338 [CA 2] Center 34 (4~65) winsize 62
3968 22:55:39.852187 [CA 3] Center 34 (4~65) winsize 62
3969 22:55:39.855938 [CA 4] Center 34 (3~65) winsize 63
3970 22:55:39.859750 [CA 5] Center 33 (3~64) winsize 62
3971 22:55:39.860347
3972 22:55:39.862346 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3973 22:55:39.862880
3974 22:55:39.865800 [CATrainingPosCal] consider 2 rank data
3975 22:55:39.869105 u2DelayCellTimex100 = 270/100 ps
3976 22:55:39.872348 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3977 22:55:39.878698 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3978 22:55:39.882251 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3979 22:55:39.885164 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3980 22:55:39.888869 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3981 22:55:39.891916 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3982 22:55:39.892519
3983 22:55:39.895107 CA PerBit enable=1, Macro0, CA PI delay=33
3984 22:55:39.895641
3985 22:55:39.898901 [CBTSetCACLKResult] CA Dly = 33
3986 22:55:39.901955 CS Dly: 5 (0~37)
3987 22:55:39.902490
3988 22:55:39.904769 ----->DramcWriteLeveling(PI) begin...
3989 22:55:39.905217 ==
3990 22:55:39.908255 Dram Type= 6, Freq= 0, CH_0, rank 0
3991 22:55:39.912102 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3992 22:55:39.912644 ==
3993 22:55:39.915814 Write leveling (Byte 0): 32 => 32
3994 22:55:39.919018 Write leveling (Byte 1): 30 => 30
3995 22:55:39.922061 DramcWriteLeveling(PI) end<-----
3996 22:55:39.922600
3997 22:55:39.923049 ==
3998 22:55:39.924836 Dram Type= 6, Freq= 0, CH_0, rank 0
3999 22:55:39.927938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4000 22:55:39.928535 ==
4001 22:55:39.931472 [Gating] SW mode calibration
4002 22:55:39.937974 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4003 22:55:39.944459 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4004 22:55:39.948231 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4005 22:55:39.953964 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4006 22:55:39.957826 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4007 22:55:39.961199 0 9 12 | B1->B0 | 3434 3131 | 1 0 | (1 0) (1 1)
4008 22:55:39.967955 0 9 16 | B1->B0 | 2f2f 2929 | 1 0 | (1 1) (0 0)
4009 22:55:39.970483 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4010 22:55:39.974270 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4011 22:55:39.980264 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4012 22:55:39.983808 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4013 22:55:39.987240 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4014 22:55:39.994323 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4015 22:55:39.997211 0 10 12 | B1->B0 | 2929 3131 | 1 0 | (0 0) (0 0)
4016 22:55:40.000289 0 10 16 | B1->B0 | 4141 4444 | 0 0 | (0 0) (0 0)
4017 22:55:40.006970 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4018 22:55:40.010118 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4019 22:55:40.013383 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4020 22:55:40.020408 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4021 22:55:40.023140 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4022 22:55:40.026997 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4023 22:55:40.032702 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4024 22:55:40.036517 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4025 22:55:40.039409 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4026 22:55:40.046337 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4027 22:55:40.049297 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4028 22:55:40.053002 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4029 22:55:40.059163 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4030 22:55:40.062902 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4031 22:55:40.066301 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4032 22:55:40.072909 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4033 22:55:40.076107 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4034 22:55:40.079176 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4035 22:55:40.085949 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4036 22:55:40.088892 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4037 22:55:40.092313 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4038 22:55:40.099555 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4039 22:55:40.102047 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4040 22:55:40.105595 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4041 22:55:40.108710 Total UI for P1: 0, mck2ui 16
4042 22:55:40.112024 best dqsien dly found for B0: ( 0, 13, 12)
4043 22:55:40.118661 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4044 22:55:40.119205 Total UI for P1: 0, mck2ui 16
4045 22:55:40.125267 best dqsien dly found for B1: ( 0, 13, 14)
4046 22:55:40.128937 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4047 22:55:40.131378 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4048 22:55:40.131870
4049 22:55:40.135038 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4050 22:55:40.138651 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4051 22:55:40.141527 [Gating] SW calibration Done
4052 22:55:40.142070 ==
4053 22:55:40.145311 Dram Type= 6, Freq= 0, CH_0, rank 0
4054 22:55:40.148395 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4055 22:55:40.148935 ==
4056 22:55:40.151167 RX Vref Scan: 0
4057 22:55:40.151620
4058 22:55:40.155215 RX Vref 0 -> 0, step: 1
4059 22:55:40.155752
4060 22:55:40.156279 RX Delay -230 -> 252, step: 16
4061 22:55:40.162016 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4062 22:55:40.164625 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4063 22:55:40.168065 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4064 22:55:40.171572 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4065 22:55:40.177868 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4066 22:55:40.181266 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4067 22:55:40.184307 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4068 22:55:40.187467 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4069 22:55:40.194487 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4070 22:55:40.197581 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4071 22:55:40.200506 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4072 22:55:40.203744 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4073 22:55:40.211073 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4074 22:55:40.214070 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4075 22:55:40.217126 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4076 22:55:40.220573 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4077 22:55:40.221113 ==
4078 22:55:40.223894 Dram Type= 6, Freq= 0, CH_0, rank 0
4079 22:55:40.230704 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4080 22:55:40.231161 ==
4081 22:55:40.231609 DQS Delay:
4082 22:55:40.233649 DQS0 = 0, DQS1 = 0
4083 22:55:40.234154 DQM Delay:
4084 22:55:40.234607 DQM0 = 40, DQM1 = 34
4085 22:55:40.237338 DQ Delay:
4086 22:55:40.240493 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4087 22:55:40.243692 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4088 22:55:40.246793 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =33
4089 22:55:40.250306 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4090 22:55:40.250776
4091 22:55:40.251227
4092 22:55:40.251640 ==
4093 22:55:40.253818 Dram Type= 6, Freq= 0, CH_0, rank 0
4094 22:55:40.256665 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4095 22:55:40.257108 ==
4096 22:55:40.257554
4097 22:55:40.257968
4098 22:55:40.260074 TX Vref Scan disable
4099 22:55:40.263517 == TX Byte 0 ==
4100 22:55:40.266798 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4101 22:55:40.270013 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4102 22:55:40.273685 == TX Byte 1 ==
4103 22:55:40.276881 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4104 22:55:40.280007 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4105 22:55:40.280594 ==
4106 22:55:40.284123 Dram Type= 6, Freq= 0, CH_0, rank 0
4107 22:55:40.287179 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4108 22:55:40.290092 ==
4109 22:55:40.290635
4110 22:55:40.291089
4111 22:55:40.291511 TX Vref Scan disable
4112 22:55:40.293675 == TX Byte 0 ==
4113 22:55:40.297246 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4114 22:55:40.303901 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4115 22:55:40.304389 == TX Byte 1 ==
4116 22:55:40.306704 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4117 22:55:40.313282 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4118 22:55:40.313938
4119 22:55:40.314489 [DATLAT]
4120 22:55:40.315012 Freq=600, CH0 RK0
4121 22:55:40.315528
4122 22:55:40.316853 DATLAT Default: 0x9
4123 22:55:40.317283 0, 0xFFFF, sum = 0
4124 22:55:40.320004 1, 0xFFFF, sum = 0
4125 22:55:40.323446 2, 0xFFFF, sum = 0
4126 22:55:40.324120 3, 0xFFFF, sum = 0
4127 22:55:40.326526 4, 0xFFFF, sum = 0
4128 22:55:40.326975 5, 0xFFFF, sum = 0
4129 22:55:40.330346 6, 0xFFFF, sum = 0
4130 22:55:40.330942 7, 0xFFFF, sum = 0
4131 22:55:40.333611 8, 0x0, sum = 1
4132 22:55:40.334058 9, 0x0, sum = 2
4133 22:55:40.336386 10, 0x0, sum = 3
4134 22:55:40.336852 11, 0x0, sum = 4
4135 22:55:40.337300 best_step = 9
4136 22:55:40.337718
4137 22:55:40.339526 ==
4138 22:55:40.343161 Dram Type= 6, Freq= 0, CH_0, rank 0
4139 22:55:40.346594 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4140 22:55:40.347036 ==
4141 22:55:40.347479 RX Vref Scan: 1
4142 22:55:40.347895
4143 22:55:40.349759 RX Vref 0 -> 0, step: 1
4144 22:55:40.350200
4145 22:55:40.353150 RX Delay -195 -> 252, step: 8
4146 22:55:40.353610
4147 22:55:40.356298 Set Vref, RX VrefLevel [Byte0]: 53
4148 22:55:40.359419 [Byte1]: 49
4149 22:55:40.359840
4150 22:55:40.362752 Final RX Vref Byte 0 = 53 to rank0
4151 22:55:40.365999 Final RX Vref Byte 1 = 49 to rank0
4152 22:55:40.369185 Final RX Vref Byte 0 = 53 to rank1
4153 22:55:40.372880 Final RX Vref Byte 1 = 49 to rank1==
4154 22:55:40.375785 Dram Type= 6, Freq= 0, CH_0, rank 0
4155 22:55:40.382692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4156 22:55:40.383274 ==
4157 22:55:40.383800 DQS Delay:
4158 22:55:40.384355 DQS0 = 0, DQS1 = 0
4159 22:55:40.385603 DQM Delay:
4160 22:55:40.386031 DQM0 = 40, DQM1 = 33
4161 22:55:40.388898 DQ Delay:
4162 22:55:40.392658 DQ0 =44, DQ1 =40, DQ2 =36, DQ3 =36
4163 22:55:40.395524 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =44
4164 22:55:40.398952 DQ8 =24, DQ9 =24, DQ10 =32, DQ11 =28
4165 22:55:40.402240 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =40
4166 22:55:40.402667
4167 22:55:40.403040
4168 22:55:40.409322 [DQSOSCAuto] RK0, (LSB)MR18= 0x4d44, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 395 ps
4169 22:55:40.412427 CH0 RK0: MR19=808, MR18=4D44
4170 22:55:40.418725 CH0_RK0: MR19=0x808, MR18=0x4D44, DQSOSC=395, MR23=63, INC=168, DEC=112
4171 22:55:40.419154
4172 22:55:40.422421 ----->DramcWriteLeveling(PI) begin...
4173 22:55:40.422850 ==
4174 22:55:40.425683 Dram Type= 6, Freq= 0, CH_0, rank 1
4175 22:55:40.428919 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4176 22:55:40.429448 ==
4177 22:55:40.431659 Write leveling (Byte 0): 33 => 33
4178 22:55:40.434990 Write leveling (Byte 1): 29 => 29
4179 22:55:40.438551 DramcWriteLeveling(PI) end<-----
4180 22:55:40.438978
4181 22:55:40.439331 ==
4182 22:55:40.442129 Dram Type= 6, Freq= 0, CH_0, rank 1
4183 22:55:40.445614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4184 22:55:40.448399 ==
4185 22:55:40.448824 [Gating] SW mode calibration
4186 22:55:40.459100 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4187 22:55:40.462035 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4188 22:55:40.465206 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4189 22:55:40.471307 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4190 22:55:40.474901 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4191 22:55:40.478365 0 9 12 | B1->B0 | 3434 3030 | 1 1 | (1 1) (0 1)
4192 22:55:40.484506 0 9 16 | B1->B0 | 3030 2525 | 1 0 | (1 1) (0 0)
4193 22:55:40.488122 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4194 22:55:40.491555 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4195 22:55:40.497917 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4196 22:55:40.501328 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4197 22:55:40.504609 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4198 22:55:40.511196 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4199 22:55:40.514463 0 10 12 | B1->B0 | 2828 3737 | 0 0 | (0 0) (1 1)
4200 22:55:40.517813 0 10 16 | B1->B0 | 3939 4646 | 1 0 | (0 0) (0 0)
4201 22:55:40.524271 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4202 22:55:40.527507 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4203 22:55:40.530819 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4204 22:55:40.537199 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4205 22:55:40.540767 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4206 22:55:40.544268 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4207 22:55:40.550596 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4208 22:55:40.553637 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4209 22:55:40.557551 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4210 22:55:40.563424 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4211 22:55:40.566856 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4212 22:55:40.569881 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4213 22:55:40.578047 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4214 22:55:40.580004 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4215 22:55:40.583403 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4216 22:55:40.589886 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4217 22:55:40.593190 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4218 22:55:40.596664 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4219 22:55:40.603555 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4220 22:55:40.606528 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4221 22:55:40.610099 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4222 22:55:40.616264 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4223 22:55:40.619900 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4224 22:55:40.623185 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4225 22:55:40.626655 Total UI for P1: 0, mck2ui 16
4226 22:55:40.629857 best dqsien dly found for B0: ( 0, 13, 14)
4227 22:55:40.636158 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4228 22:55:40.639239 Total UI for P1: 0, mck2ui 16
4229 22:55:40.642837 best dqsien dly found for B1: ( 0, 13, 16)
4230 22:55:40.646121 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4231 22:55:40.649319 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4232 22:55:40.649860
4233 22:55:40.652411 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4234 22:55:40.656095 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4235 22:55:40.659475 [Gating] SW calibration Done
4236 22:55:40.659995 ==
4237 22:55:40.662848 Dram Type= 6, Freq= 0, CH_0, rank 1
4238 22:55:40.665896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4239 22:55:40.666420 ==
4240 22:55:40.669162 RX Vref Scan: 0
4241 22:55:40.669681
4242 22:55:40.672401 RX Vref 0 -> 0, step: 1
4243 22:55:40.672923
4244 22:55:40.675921 RX Delay -230 -> 252, step: 16
4245 22:55:40.679362 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4246 22:55:40.682410 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4247 22:55:40.685337 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4248 22:55:40.688906 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4249 22:55:40.695409 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4250 22:55:40.699420 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4251 22:55:40.702125 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4252 22:55:40.705807 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4253 22:55:40.712381 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4254 22:55:40.715048 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4255 22:55:40.718824 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4256 22:55:40.722110 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4257 22:55:40.728350 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4258 22:55:40.731808 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4259 22:55:40.734764 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4260 22:55:40.738720 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4261 22:55:40.739141 ==
4262 22:55:40.741579 Dram Type= 6, Freq= 0, CH_0, rank 1
4263 22:55:40.748148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4264 22:55:40.748573 ==
4265 22:55:40.748908 DQS Delay:
4266 22:55:40.751328 DQS0 = 0, DQS1 = 0
4267 22:55:40.751746 DQM Delay:
4268 22:55:40.754473 DQM0 = 43, DQM1 = 34
4269 22:55:40.754892 DQ Delay:
4270 22:55:40.758020 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4271 22:55:40.761274 DQ4 =41, DQ5 =41, DQ6 =49, DQ7 =49
4272 22:55:40.764846 DQ8 =17, DQ9 =17, DQ10 =41, DQ11 =25
4273 22:55:40.768140 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4274 22:55:40.768656
4275 22:55:40.768990
4276 22:55:40.769297 ==
4277 22:55:40.771095 Dram Type= 6, Freq= 0, CH_0, rank 1
4278 22:55:40.774976 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4279 22:55:40.775500 ==
4280 22:55:40.775839
4281 22:55:40.776193
4282 22:55:40.777824 TX Vref Scan disable
4283 22:55:40.781128 == TX Byte 0 ==
4284 22:55:40.784263 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4285 22:55:40.787464 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4286 22:55:40.790539 == TX Byte 1 ==
4287 22:55:40.794320 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4288 22:55:40.797003 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4289 22:55:40.797426 ==
4290 22:55:40.800257 Dram Type= 6, Freq= 0, CH_0, rank 1
4291 22:55:40.806834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4292 22:55:40.807258 ==
4293 22:55:40.807592
4294 22:55:40.807903
4295 22:55:40.808253 TX Vref Scan disable
4296 22:55:40.811438 == TX Byte 0 ==
4297 22:55:40.814760 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4298 22:55:40.821363 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4299 22:55:40.821814 == TX Byte 1 ==
4300 22:55:40.825234 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4301 22:55:40.831480 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4302 22:55:40.831901
4303 22:55:40.832501 [DATLAT]
4304 22:55:40.832853 Freq=600, CH0 RK1
4305 22:55:40.833395
4306 22:55:40.834841 DATLAT Default: 0x9
4307 22:55:40.835262 0, 0xFFFF, sum = 0
4308 22:55:40.838093 1, 0xFFFF, sum = 0
4309 22:55:40.841334 2, 0xFFFF, sum = 0
4310 22:55:40.841760 3, 0xFFFF, sum = 0
4311 22:55:40.844608 4, 0xFFFF, sum = 0
4312 22:55:40.845035 5, 0xFFFF, sum = 0
4313 22:55:40.848700 6, 0xFFFF, sum = 0
4314 22:55:40.849131 7, 0xFFFF, sum = 0
4315 22:55:40.851410 8, 0x0, sum = 1
4316 22:55:40.851836 9, 0x0, sum = 2
4317 22:55:40.854384 10, 0x0, sum = 3
4318 22:55:40.854829 11, 0x0, sum = 4
4319 22:55:40.855172 best_step = 9
4320 22:55:40.855485
4321 22:55:40.857675 ==
4322 22:55:40.861041 Dram Type= 6, Freq= 0, CH_0, rank 1
4323 22:55:40.864679 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4324 22:55:40.865106 ==
4325 22:55:40.865441 RX Vref Scan: 0
4326 22:55:40.865755
4327 22:55:40.867193 RX Vref 0 -> 0, step: 1
4328 22:55:40.867274
4329 22:55:40.870742 RX Delay -195 -> 252, step: 8
4330 22:55:40.877119 iDelay=205, Bit 0, Center 40 (-107 ~ 188) 296
4331 22:55:40.880483 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4332 22:55:40.884321 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4333 22:55:40.887515 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4334 22:55:40.893705 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4335 22:55:40.896928 iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304
4336 22:55:40.900392 iDelay=205, Bit 6, Center 52 (-99 ~ 204) 304
4337 22:55:40.903393 iDelay=205, Bit 7, Center 44 (-107 ~ 196) 304
4338 22:55:40.906744 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4339 22:55:40.913346 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4340 22:55:40.916987 iDelay=205, Bit 10, Center 36 (-115 ~ 188) 304
4341 22:55:40.920022 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4342 22:55:40.923314 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4343 22:55:40.929831 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4344 22:55:40.933643 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4345 22:55:40.936421 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4346 22:55:40.936506 ==
4347 22:55:40.939768 Dram Type= 6, Freq= 0, CH_0, rank 1
4348 22:55:40.946408 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4349 22:55:40.946567 ==
4350 22:55:40.946646 DQS Delay:
4351 22:55:40.946720 DQS0 = 0, DQS1 = 0
4352 22:55:40.949539 DQM Delay:
4353 22:55:40.949639 DQM0 = 40, DQM1 = 34
4354 22:55:40.953063 DQ Delay:
4355 22:55:40.956095 DQ0 =40, DQ1 =44, DQ2 =36, DQ3 =36
4356 22:55:40.959481 DQ4 =44, DQ5 =28, DQ6 =52, DQ7 =44
4357 22:55:40.962919 DQ8 =24, DQ9 =20, DQ10 =36, DQ11 =28
4358 22:55:40.966800 DQ12 =40, DQ13 =44, DQ14 =44, DQ15 =40
4359 22:55:40.966965
4360 22:55:40.967083
4361 22:55:40.972812 [DQSOSCAuto] RK1, (LSB)MR18= 0x3f3a, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 397 ps
4362 22:55:40.975984 CH0 RK1: MR19=808, MR18=3F3A
4363 22:55:40.982675 CH0_RK1: MR19=0x808, MR18=0x3F3A, DQSOSC=397, MR23=63, INC=166, DEC=110
4364 22:55:40.986260 [RxdqsGatingPostProcess] freq 600
4365 22:55:40.989323 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4366 22:55:40.993024 Pre-setting of DQS Precalculation
4367 22:55:40.999911 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4368 22:55:41.000487 ==
4369 22:55:41.002928 Dram Type= 6, Freq= 0, CH_1, rank 0
4370 22:55:41.006410 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4371 22:55:41.006859 ==
4372 22:55:41.012716 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4373 22:55:41.019715 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4374 22:55:41.022635 [CA 0] Center 35 (5~66) winsize 62
4375 22:55:41.026054 [CA 1] Center 35 (5~66) winsize 62
4376 22:55:41.029694 [CA 2] Center 34 (4~65) winsize 62
4377 22:55:41.033046 [CA 3] Center 34 (3~65) winsize 63
4378 22:55:41.035673 [CA 4] Center 34 (4~65) winsize 62
4379 22:55:41.038658 [CA 5] Center 34 (3~65) winsize 63
4380 22:55:41.039255
4381 22:55:41.042405 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4382 22:55:41.042999
4383 22:55:41.045915 [CATrainingPosCal] consider 1 rank data
4384 22:55:41.048780 u2DelayCellTimex100 = 270/100 ps
4385 22:55:41.052383 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4386 22:55:41.055145 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4387 22:55:41.058836 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4388 22:55:41.061887 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
4389 22:55:41.065521 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4390 22:55:41.068716 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4391 22:55:41.069224
4392 22:55:41.075241 CA PerBit enable=1, Macro0, CA PI delay=34
4393 22:55:41.075767
4394 22:55:41.078322 [CBTSetCACLKResult] CA Dly = 34
4395 22:55:41.078732 CS Dly: 4 (0~35)
4396 22:55:41.079056 ==
4397 22:55:41.081688 Dram Type= 6, Freq= 0, CH_1, rank 1
4398 22:55:41.085437 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4399 22:55:41.085974 ==
4400 22:55:41.092400 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4401 22:55:41.098407 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4402 22:55:41.101505 [CA 0] Center 35 (5~66) winsize 62
4403 22:55:41.105554 [CA 1] Center 36 (6~66) winsize 61
4404 22:55:41.108200 [CA 2] Center 34 (4~65) winsize 62
4405 22:55:41.111658 [CA 3] Center 33 (3~64) winsize 62
4406 22:55:41.115450 [CA 4] Center 34 (4~64) winsize 61
4407 22:55:41.118116 [CA 5] Center 33 (3~64) winsize 62
4408 22:55:41.118639
4409 22:55:41.121643 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4410 22:55:41.122222
4411 22:55:41.124356 [CATrainingPosCal] consider 2 rank data
4412 22:55:41.127689 u2DelayCellTimex100 = 270/100 ps
4413 22:55:41.131174 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4414 22:55:41.134585 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4415 22:55:41.138132 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4416 22:55:41.141278 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4417 22:55:41.147569 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4418 22:55:41.150882 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4419 22:55:41.151255
4420 22:55:41.153653 CA PerBit enable=1, Macro0, CA PI delay=33
4421 22:55:41.153765
4422 22:55:41.157237 [CBTSetCACLKResult] CA Dly = 33
4423 22:55:41.157319 CS Dly: 4 (0~36)
4424 22:55:41.157388
4425 22:55:41.160717 ----->DramcWriteLeveling(PI) begin...
4426 22:55:41.160801 ==
4427 22:55:41.163745 Dram Type= 6, Freq= 0, CH_1, rank 0
4428 22:55:41.170430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4429 22:55:41.170511 ==
4430 22:55:41.173463 Write leveling (Byte 0): 28 => 28
4431 22:55:41.177186 Write leveling (Byte 1): 29 => 29
4432 22:55:41.180745 DramcWriteLeveling(PI) end<-----
4433 22:55:41.181166
4434 22:55:41.181502 ==
4435 22:55:41.183921 Dram Type= 6, Freq= 0, CH_1, rank 0
4436 22:55:41.186810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4437 22:55:41.187234 ==
4438 22:55:41.190755 [Gating] SW mode calibration
4439 22:55:41.197284 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4440 22:55:41.203437 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4441 22:55:41.206685 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4442 22:55:41.210613 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4443 22:55:41.213448 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4444 22:55:41.220391 0 9 12 | B1->B0 | 2f2f 2f2f | 0 0 | (0 0) (0 1)
4445 22:55:41.223767 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4446 22:55:41.230229 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4447 22:55:41.233745 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4448 22:55:41.236340 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4449 22:55:41.243635 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4450 22:55:41.246936 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4451 22:55:41.249941 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4452 22:55:41.256400 0 10 12 | B1->B0 | 3434 3737 | 1 0 | (0 0) (0 0)
4453 22:55:41.259813 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4454 22:55:41.263506 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4455 22:55:41.269573 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4456 22:55:41.273290 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4457 22:55:41.276542 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4458 22:55:41.282712 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4459 22:55:41.285856 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4460 22:55:41.289730 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4461 22:55:41.295980 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4462 22:55:41.299803 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4463 22:55:41.303135 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4464 22:55:41.309568 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4465 22:55:41.312192 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4466 22:55:41.315747 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4467 22:55:41.322451 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4468 22:55:41.325832 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4469 22:55:41.328908 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4470 22:55:41.335503 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4471 22:55:41.338330 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4472 22:55:41.341947 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4473 22:55:41.348551 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4474 22:55:41.351985 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4475 22:55:41.354747 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4476 22:55:41.362075 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4477 22:55:41.364739 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4478 22:55:41.368477 Total UI for P1: 0, mck2ui 16
4479 22:55:41.371676 best dqsien dly found for B0: ( 0, 13, 12)
4480 22:55:41.374657 Total UI for P1: 0, mck2ui 16
4481 22:55:41.378178 best dqsien dly found for B1: ( 0, 13, 14)
4482 22:55:41.381925 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4483 22:55:41.384864 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4484 22:55:41.385384
4485 22:55:41.387694 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4486 22:55:41.391384 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4487 22:55:41.394310 [Gating] SW calibration Done
4488 22:55:41.394802 ==
4489 22:55:41.397845 Dram Type= 6, Freq= 0, CH_1, rank 0
4490 22:55:41.403956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4491 22:55:41.404425 ==
4492 22:55:41.404765 RX Vref Scan: 0
4493 22:55:41.405083
4494 22:55:41.407365 RX Vref 0 -> 0, step: 1
4495 22:55:41.407789
4496 22:55:41.410944 RX Delay -230 -> 252, step: 16
4497 22:55:41.414209 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4498 22:55:41.417718 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4499 22:55:41.420640 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4500 22:55:41.427765 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4501 22:55:41.430741 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4502 22:55:41.433627 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4503 22:55:41.436507 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4504 22:55:41.443375 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4505 22:55:41.446517 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4506 22:55:41.449801 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4507 22:55:41.453131 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4508 22:55:41.459925 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4509 22:55:41.462794 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4510 22:55:41.466477 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4511 22:55:41.469758 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4512 22:55:41.476059 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4513 22:55:41.476215 ==
4514 22:55:41.479476 Dram Type= 6, Freq= 0, CH_1, rank 0
4515 22:55:41.482913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4516 22:55:41.483143 ==
4517 22:55:41.483340 DQS Delay:
4518 22:55:41.486740 DQS0 = 0, DQS1 = 0
4519 22:55:41.487032 DQM Delay:
4520 22:55:41.489819 DQM0 = 46, DQM1 = 39
4521 22:55:41.490023 DQ Delay:
4522 22:55:41.492884 DQ0 =57, DQ1 =41, DQ2 =33, DQ3 =41
4523 22:55:41.496138 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4524 22:55:41.499218 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4525 22:55:41.502742 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =41
4526 22:55:41.503158
4527 22:55:41.503493
4528 22:55:41.503819 ==
4529 22:55:41.506351 Dram Type= 6, Freq= 0, CH_1, rank 0
4530 22:55:41.509588 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4531 22:55:41.512770 ==
4532 22:55:41.513196
4533 22:55:41.513533
4534 22:55:41.513846 TX Vref Scan disable
4535 22:55:41.515882 == TX Byte 0 ==
4536 22:55:41.519259 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4537 22:55:41.522876 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4538 22:55:41.525884 == TX Byte 1 ==
4539 22:55:41.529254 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4540 22:55:41.535338 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4541 22:55:41.535441 ==
4542 22:55:41.539175 Dram Type= 6, Freq= 0, CH_1, rank 0
4543 22:55:41.542654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4544 22:55:41.542802 ==
4545 22:55:41.542929
4546 22:55:41.543049
4547 22:55:41.545122 TX Vref Scan disable
4548 22:55:41.548767 == TX Byte 0 ==
4549 22:55:41.552021 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4550 22:55:41.555639 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4551 22:55:41.558948 == TX Byte 1 ==
4552 22:55:41.562348 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4553 22:55:41.565386 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4554 22:55:41.565673
4555 22:55:41.565847 [DATLAT]
4556 22:55:41.568345 Freq=600, CH1 RK0
4557 22:55:41.568567
4558 22:55:41.571823 DATLAT Default: 0x9
4559 22:55:41.572082 0, 0xFFFF, sum = 0
4560 22:55:41.574963 1, 0xFFFF, sum = 0
4561 22:55:41.575243 2, 0xFFFF, sum = 0
4562 22:55:41.578171 3, 0xFFFF, sum = 0
4563 22:55:41.578489 4, 0xFFFF, sum = 0
4564 22:55:41.581738 5, 0xFFFF, sum = 0
4565 22:55:41.582158 6, 0xFFFF, sum = 0
4566 22:55:41.585119 7, 0xFFFF, sum = 0
4567 22:55:41.585570 8, 0x0, sum = 1
4568 22:55:41.588400 9, 0x0, sum = 2
4569 22:55:41.588859 10, 0x0, sum = 3
4570 22:55:41.591233 11, 0x0, sum = 4
4571 22:55:41.591776 best_step = 9
4572 22:55:41.592250
4573 22:55:41.592604 ==
4574 22:55:41.594751 Dram Type= 6, Freq= 0, CH_1, rank 0
4575 22:55:41.597923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4576 22:55:41.598509 ==
4577 22:55:41.601511 RX Vref Scan: 1
4578 22:55:41.601955
4579 22:55:41.604533 RX Vref 0 -> 0, step: 1
4580 22:55:41.604959
4581 22:55:41.608262 RX Delay -179 -> 252, step: 8
4582 22:55:41.608688
4583 22:55:41.611814 Set Vref, RX VrefLevel [Byte0]: 50
4584 22:55:41.612283 [Byte1]: 49
4585 22:55:41.616394
4586 22:55:41.616817 Final RX Vref Byte 0 = 50 to rank0
4587 22:55:41.619481 Final RX Vref Byte 1 = 49 to rank0
4588 22:55:41.622848 Final RX Vref Byte 0 = 50 to rank1
4589 22:55:41.626330 Final RX Vref Byte 1 = 49 to rank1==
4590 22:55:41.629187 Dram Type= 6, Freq= 0, CH_1, rank 0
4591 22:55:41.635866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4592 22:55:41.636350 ==
4593 22:55:41.636697 DQS Delay:
4594 22:55:41.639259 DQS0 = 0, DQS1 = 0
4595 22:55:41.639811 DQM Delay:
4596 22:55:41.640332 DQM0 = 41, DQM1 = 34
4597 22:55:41.642332 DQ Delay:
4598 22:55:41.646185 DQ0 =48, DQ1 =40, DQ2 =28, DQ3 =40
4599 22:55:41.648969 DQ4 =36, DQ5 =48, DQ6 =52, DQ7 =36
4600 22:55:41.652425 DQ8 =20, DQ9 =24, DQ10 =36, DQ11 =28
4601 22:55:41.655659 DQ12 =44, DQ13 =40, DQ14 =40, DQ15 =40
4602 22:55:41.656250
4603 22:55:41.656639
4604 22:55:41.662338 [DQSOSCAuto] RK0, (LSB)MR18= 0x2c46, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 401 ps
4605 22:55:41.665289 CH1 RK0: MR19=808, MR18=2C46
4606 22:55:41.672551 CH1_RK0: MR19=0x808, MR18=0x2C46, DQSOSC=396, MR23=63, INC=167, DEC=111
4607 22:55:41.672979
4608 22:55:41.675631 ----->DramcWriteLeveling(PI) begin...
4609 22:55:41.676101 ==
4610 22:55:41.678644 Dram Type= 6, Freq= 0, CH_1, rank 1
4611 22:55:41.682225 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4612 22:55:41.682653 ==
4613 22:55:41.685099 Write leveling (Byte 0): 30 => 30
4614 22:55:41.688522 Write leveling (Byte 1): 29 => 29
4615 22:55:41.692077 DramcWriteLeveling(PI) end<-----
4616 22:55:41.692506
4617 22:55:41.692887 ==
4618 22:55:41.695087 Dram Type= 6, Freq= 0, CH_1, rank 1
4619 22:55:41.701978 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4620 22:55:41.702410 ==
4621 22:55:41.702752 [Gating] SW mode calibration
4622 22:55:41.711463 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4623 22:55:41.715503 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4624 22:55:41.718184 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4625 22:55:41.724754 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4626 22:55:41.728200 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4627 22:55:41.731339 0 9 12 | B1->B0 | 3030 2c2c | 0 0 | (0 0) (0 0)
4628 22:55:41.738236 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4629 22:55:41.741529 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4630 22:55:41.744387 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4631 22:55:41.750566 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4632 22:55:41.754521 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4633 22:55:41.757304 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4634 22:55:41.763913 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4635 22:55:41.767222 0 10 12 | B1->B0 | 3333 4040 | 0 0 | (0 0) (1 1)
4636 22:55:41.770297 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4637 22:55:41.777628 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4638 22:55:41.780856 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4639 22:55:41.784161 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4640 22:55:41.790713 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4641 22:55:41.793839 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4642 22:55:41.800352 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4643 22:55:41.803372 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4644 22:55:41.807061 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4645 22:55:41.813341 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4646 22:55:41.817039 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4647 22:55:41.820548 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4648 22:55:41.826820 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4649 22:55:41.830112 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4650 22:55:41.833722 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4651 22:55:41.839997 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4652 22:55:41.843490 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4653 22:55:41.847158 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4654 22:55:41.853088 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4655 22:55:41.856586 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4656 22:55:41.860399 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4657 22:55:41.866718 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4658 22:55:41.870565 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4659 22:55:41.873384 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4660 22:55:41.876641 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4661 22:55:41.880392 Total UI for P1: 0, mck2ui 16
4662 22:55:41.883756 best dqsien dly found for B0: ( 0, 13, 14)
4663 22:55:41.886757 Total UI for P1: 0, mck2ui 16
4664 22:55:41.889537 best dqsien dly found for B1: ( 0, 13, 12)
4665 22:55:41.896235 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4666 22:55:41.900224 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4667 22:55:41.900800
4668 22:55:41.902577 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4669 22:55:41.906159 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4670 22:55:41.909283 [Gating] SW calibration Done
4671 22:55:41.909841 ==
4672 22:55:41.912587 Dram Type= 6, Freq= 0, CH_1, rank 1
4673 22:55:41.916472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4674 22:55:41.916902 ==
4675 22:55:41.919166 RX Vref Scan: 0
4676 22:55:41.919714
4677 22:55:41.920086 RX Vref 0 -> 0, step: 1
4678 22:55:41.920409
4679 22:55:41.922853 RX Delay -230 -> 252, step: 16
4680 22:55:41.929002 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4681 22:55:41.932848 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4682 22:55:41.935797 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4683 22:55:41.938728 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4684 22:55:41.942167 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4685 22:55:41.949008 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4686 22:55:41.951960 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4687 22:55:41.955248 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4688 22:55:41.958672 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4689 22:55:41.965211 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4690 22:55:41.968569 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4691 22:55:41.971734 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4692 22:55:41.974856 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4693 22:55:41.981668 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4694 22:55:41.984869 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4695 22:55:41.988453 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4696 22:55:41.988799 ==
4697 22:55:41.991600 Dram Type= 6, Freq= 0, CH_1, rank 1
4698 22:55:41.994896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4699 22:55:41.998375 ==
4700 22:55:41.998561 DQS Delay:
4701 22:55:41.998708 DQS0 = 0, DQS1 = 0
4702 22:55:42.001805 DQM Delay:
4703 22:55:42.001961 DQM0 = 41, DQM1 = 38
4704 22:55:42.005199 DQ Delay:
4705 22:55:42.005335 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =41
4706 22:55:42.007755 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =33
4707 22:55:42.011514 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4708 22:55:42.014609 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =49
4709 22:55:42.014729
4710 22:55:42.017666
4711 22:55:42.017769 ==
4712 22:55:42.021846 Dram Type= 6, Freq= 0, CH_1, rank 1
4713 22:55:42.024378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4714 22:55:42.024473 ==
4715 22:55:42.024548
4716 22:55:42.024616
4717 22:55:42.027615 TX Vref Scan disable
4718 22:55:42.027701 == TX Byte 0 ==
4719 22:55:42.034249 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4720 22:55:42.037124 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4721 22:55:42.037222 == TX Byte 1 ==
4722 22:55:42.043954 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4723 22:55:42.047418 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4724 22:55:42.047515 ==
4725 22:55:42.050551 Dram Type= 6, Freq= 0, CH_1, rank 1
4726 22:55:42.054082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4727 22:55:42.054171 ==
4728 22:55:42.054238
4729 22:55:42.054302
4730 22:55:42.057085 TX Vref Scan disable
4731 22:55:42.060705 == TX Byte 0 ==
4732 22:55:42.063808 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4733 22:55:42.070533 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4734 22:55:42.070618 == TX Byte 1 ==
4735 22:55:42.073644 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4736 22:55:42.080709 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4737 22:55:42.080795
4738 22:55:42.080862 [DATLAT]
4739 22:55:42.080924 Freq=600, CH1 RK1
4740 22:55:42.080984
4741 22:55:42.083924 DATLAT Default: 0x9
4742 22:55:42.087074 0, 0xFFFF, sum = 0
4743 22:55:42.087159 1, 0xFFFF, sum = 0
4744 22:55:42.090190 2, 0xFFFF, sum = 0
4745 22:55:42.090274 3, 0xFFFF, sum = 0
4746 22:55:42.093620 4, 0xFFFF, sum = 0
4747 22:55:42.093704 5, 0xFFFF, sum = 0
4748 22:55:42.096591 6, 0xFFFF, sum = 0
4749 22:55:42.096676 7, 0xFFFF, sum = 0
4750 22:55:42.100048 8, 0x0, sum = 1
4751 22:55:42.100134 9, 0x0, sum = 2
4752 22:55:42.103603 10, 0x0, sum = 3
4753 22:55:42.103688 11, 0x0, sum = 4
4754 22:55:42.103755 best_step = 9
4755 22:55:42.103818
4756 22:55:42.106816 ==
4757 22:55:42.109790 Dram Type= 6, Freq= 0, CH_1, rank 1
4758 22:55:42.113279 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4759 22:55:42.113364 ==
4760 22:55:42.113431 RX Vref Scan: 0
4761 22:55:42.113492
4762 22:55:42.116491 RX Vref 0 -> 0, step: 1
4763 22:55:42.116589
4764 22:55:42.119806 RX Delay -179 -> 252, step: 8
4765 22:55:42.126267 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4766 22:55:42.129494 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4767 22:55:42.132927 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4768 22:55:42.136232 iDelay=205, Bit 3, Center 36 (-123 ~ 196) 320
4769 22:55:42.142928 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4770 22:55:42.146494 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4771 22:55:42.149310 iDelay=205, Bit 6, Center 44 (-107 ~ 196) 304
4772 22:55:42.152293 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4773 22:55:42.155605 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4774 22:55:42.162475 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4775 22:55:42.165890 iDelay=205, Bit 10, Center 36 (-115 ~ 188) 304
4776 22:55:42.169057 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4777 22:55:42.172250 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4778 22:55:42.179153 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4779 22:55:42.182373 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4780 22:55:42.185655 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4781 22:55:42.185801 ==
4782 22:55:42.188993 Dram Type= 6, Freq= 0, CH_1, rank 1
4783 22:55:42.195162 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4784 22:55:42.195352 ==
4785 22:55:42.195524 DQS Delay:
4786 22:55:42.195642 DQS0 = 0, DQS1 = 0
4787 22:55:42.198703 DQM Delay:
4788 22:55:42.198912 DQM0 = 37, DQM1 = 34
4789 22:55:42.201919 DQ Delay:
4790 22:55:42.205170 DQ0 =40, DQ1 =36, DQ2 =28, DQ3 =36
4791 22:55:42.208728 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =32
4792 22:55:42.211845 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =24
4793 22:55:42.215458 DQ12 =44, DQ13 =44, DQ14 =40, DQ15 =40
4794 22:55:42.215645
4795 22:55:42.215851
4796 22:55:42.222020 [DQSOSCAuto] RK1, (LSB)MR18= 0x3a60, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
4797 22:55:42.225650 CH1 RK1: MR19=808, MR18=3A60
4798 22:55:42.232268 CH1_RK1: MR19=0x808, MR18=0x3A60, DQSOSC=391, MR23=63, INC=171, DEC=114
4799 22:55:42.235190 [RxdqsGatingPostProcess] freq 600
4800 22:55:42.238133 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4801 22:55:42.241380 Pre-setting of DQS Precalculation
4802 22:55:42.248412 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4803 22:55:42.255284 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4804 22:55:42.261470 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4805 22:55:42.261608
4806 22:55:42.261713
4807 22:55:42.264602 [Calibration Summary] 1200 Mbps
4808 22:55:42.264734 CH 0, Rank 0
4809 22:55:42.268005 SW Impedance : PASS
4810 22:55:42.271537 DUTY Scan : NO K
4811 22:55:42.271673 ZQ Calibration : PASS
4812 22:55:42.275135 Jitter Meter : NO K
4813 22:55:42.277780 CBT Training : PASS
4814 22:55:42.277927 Write leveling : PASS
4815 22:55:42.281343 RX DQS gating : PASS
4816 22:55:42.284059 RX DQ/DQS(RDDQC) : PASS
4817 22:55:42.284230 TX DQ/DQS : PASS
4818 22:55:42.287949 RX DATLAT : PASS
4819 22:55:42.290863 RX DQ/DQS(Engine): PASS
4820 22:55:42.291022 TX OE : NO K
4821 22:55:42.294212 All Pass.
4822 22:55:42.294350
4823 22:55:42.294457 CH 0, Rank 1
4824 22:55:42.297681 SW Impedance : PASS
4825 22:55:42.297878 DUTY Scan : NO K
4826 22:55:42.300545 ZQ Calibration : PASS
4827 22:55:42.304056 Jitter Meter : NO K
4828 22:55:42.304141 CBT Training : PASS
4829 22:55:42.307434 Write leveling : PASS
4830 22:55:42.310532 RX DQS gating : PASS
4831 22:55:42.310638 RX DQ/DQS(RDDQC) : PASS
4832 22:55:42.314141 TX DQ/DQS : PASS
4833 22:55:42.317467 RX DATLAT : PASS
4834 22:55:42.317584 RX DQ/DQS(Engine): PASS
4835 22:55:42.320771 TX OE : NO K
4836 22:55:42.320893 All Pass.
4837 22:55:42.320968
4838 22:55:42.323697 CH 1, Rank 0
4839 22:55:42.323795 SW Impedance : PASS
4840 22:55:42.327164 DUTY Scan : NO K
4841 22:55:42.327262 ZQ Calibration : PASS
4842 22:55:42.330744 Jitter Meter : NO K
4843 22:55:42.333618 CBT Training : PASS
4844 22:55:42.333716 Write leveling : PASS
4845 22:55:42.337158 RX DQS gating : PASS
4846 22:55:42.340498 RX DQ/DQS(RDDQC) : PASS
4847 22:55:42.340588 TX DQ/DQS : PASS
4848 22:55:42.343877 RX DATLAT : PASS
4849 22:55:42.347229 RX DQ/DQS(Engine): PASS
4850 22:55:42.347356 TX OE : NO K
4851 22:55:42.349991 All Pass.
4852 22:55:42.350135
4853 22:55:42.350266 CH 1, Rank 1
4854 22:55:42.353850 SW Impedance : PASS
4855 22:55:42.353955 DUTY Scan : NO K
4856 22:55:42.357195 ZQ Calibration : PASS
4857 22:55:42.360092 Jitter Meter : NO K
4858 22:55:42.360230 CBT Training : PASS
4859 22:55:42.363506 Write leveling : PASS
4860 22:55:42.366532 RX DQS gating : PASS
4861 22:55:42.366656 RX DQ/DQS(RDDQC) : PASS
4862 22:55:42.369808 TX DQ/DQS : PASS
4863 22:55:42.373032 RX DATLAT : PASS
4864 22:55:42.373171 RX DQ/DQS(Engine): PASS
4865 22:55:42.377014 TX OE : NO K
4866 22:55:42.377119 All Pass.
4867 22:55:42.377239
4868 22:55:42.379890 DramC Write-DBI off
4869 22:55:42.383118 PER_BANK_REFRESH: Hybrid Mode
4870 22:55:42.383237 TX_TRACKING: ON
4871 22:55:42.393348 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4872 22:55:42.396558 [FAST_K] Save calibration result to emmc
4873 22:55:42.399713 dramc_set_vcore_voltage set vcore to 662500
4874 22:55:42.403132 Read voltage for 933, 3
4875 22:55:42.403244 Vio18 = 0
4876 22:55:42.403348 Vcore = 662500
4877 22:55:42.406706 Vdram = 0
4878 22:55:42.406792 Vddq = 0
4879 22:55:42.406860 Vmddr = 0
4880 22:55:42.413279 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4881 22:55:42.416182 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4882 22:55:42.419603 MEM_TYPE=3, freq_sel=17
4883 22:55:42.422701 sv_algorithm_assistance_LP4_1600
4884 22:55:42.426022 ============ PULL DRAM RESETB DOWN ============
4885 22:55:42.429110 ========== PULL DRAM RESETB DOWN end =========
4886 22:55:42.435871 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4887 22:55:42.439392 ===================================
4888 22:55:42.443205 LPDDR4 DRAM CONFIGURATION
4889 22:55:42.445662 ===================================
4890 22:55:42.445774 EX_ROW_EN[0] = 0x0
4891 22:55:42.449021 EX_ROW_EN[1] = 0x0
4892 22:55:42.449109 LP4Y_EN = 0x0
4893 22:55:42.452319 WORK_FSP = 0x0
4894 22:55:42.452414 WL = 0x3
4895 22:55:42.455480 RL = 0x3
4896 22:55:42.455570 BL = 0x2
4897 22:55:42.459125 RPST = 0x0
4898 22:55:42.459212 RD_PRE = 0x0
4899 22:55:42.462439 WR_PRE = 0x1
4900 22:55:42.465682 WR_PST = 0x0
4901 22:55:42.465790 DBI_WR = 0x0
4902 22:55:42.468999 DBI_RD = 0x0
4903 22:55:42.469098 OTF = 0x1
4904 22:55:42.472017 ===================================
4905 22:55:42.475128 ===================================
4906 22:55:42.478983 ANA top config
4907 22:55:42.481812 ===================================
4908 22:55:42.481899 DLL_ASYNC_EN = 0
4909 22:55:42.485724 ALL_SLAVE_EN = 1
4910 22:55:42.488528 NEW_RANK_MODE = 1
4911 22:55:42.493165 DLL_IDLE_MODE = 1
4912 22:55:42.493589 LP45_APHY_COMB_EN = 1
4913 22:55:42.495416 TX_ODT_DIS = 1
4914 22:55:42.498634 NEW_8X_MODE = 1
4915 22:55:42.501915 ===================================
4916 22:55:42.505064 ===================================
4917 22:55:42.508927 data_rate = 1866
4918 22:55:42.511582 CKR = 1
4919 22:55:42.514677 DQ_P2S_RATIO = 8
4920 22:55:42.518523 ===================================
4921 22:55:42.519236 CA_P2S_RATIO = 8
4922 22:55:42.522006 DQ_CA_OPEN = 0
4923 22:55:42.525025 DQ_SEMI_OPEN = 0
4924 22:55:42.528545 CA_SEMI_OPEN = 0
4925 22:55:42.531648 CA_FULL_RATE = 0
4926 22:55:42.534463 DQ_CKDIV4_EN = 1
4927 22:55:42.534959 CA_CKDIV4_EN = 1
4928 22:55:42.538095 CA_PREDIV_EN = 0
4929 22:55:42.541238 PH8_DLY = 0
4930 22:55:42.545061 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4931 22:55:42.548008 DQ_AAMCK_DIV = 4
4932 22:55:42.551162 CA_AAMCK_DIV = 4
4933 22:55:42.554402 CA_ADMCK_DIV = 4
4934 22:55:42.554536 DQ_TRACK_CA_EN = 0
4935 22:55:42.557248 CA_PICK = 933
4936 22:55:42.561192 CA_MCKIO = 933
4937 22:55:42.564297 MCKIO_SEMI = 0
4938 22:55:42.567402 PLL_FREQ = 3732
4939 22:55:42.570396 DQ_UI_PI_RATIO = 32
4940 22:55:42.573483 CA_UI_PI_RATIO = 0
4941 22:55:42.577315 ===================================
4942 22:55:42.580636 ===================================
4943 22:55:42.580791 memory_type:LPDDR4
4944 22:55:42.583704 GP_NUM : 10
4945 22:55:42.587050 SRAM_EN : 1
4946 22:55:42.587142 MD32_EN : 0
4947 22:55:42.590043 ===================================
4948 22:55:42.593582 [ANA_INIT] >>>>>>>>>>>>>>
4949 22:55:42.596938 <<<<<< [CONFIGURE PHASE]: ANA_TX
4950 22:55:42.600411 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4951 22:55:42.603244 ===================================
4952 22:55:42.606497 data_rate = 1866,PCW = 0X8f00
4953 22:55:42.609915 ===================================
4954 22:55:42.613663 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4955 22:55:42.616499 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4956 22:55:42.623703 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4957 22:55:42.626644 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4958 22:55:42.629788 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4959 22:55:42.636726 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4960 22:55:42.636813 [ANA_INIT] flow start
4961 22:55:42.639913 [ANA_INIT] PLL >>>>>>>>
4962 22:55:42.643437 [ANA_INIT] PLL <<<<<<<<
4963 22:55:42.643524 [ANA_INIT] MIDPI >>>>>>>>
4964 22:55:42.646499 [ANA_INIT] MIDPI <<<<<<<<
4965 22:55:42.649987 [ANA_INIT] DLL >>>>>>>>
4966 22:55:42.650072 [ANA_INIT] flow end
4967 22:55:42.656289 ============ LP4 DIFF to SE enter ============
4968 22:55:42.659107 ============ LP4 DIFF to SE exit ============
4969 22:55:42.662758 [ANA_INIT] <<<<<<<<<<<<<
4970 22:55:42.665833 [Flow] Enable top DCM control >>>>>
4971 22:55:42.669254 [Flow] Enable top DCM control <<<<<
4972 22:55:42.669344 Enable DLL master slave shuffle
4973 22:55:42.675617 ==============================================================
4974 22:55:42.679228 Gating Mode config
4975 22:55:42.682209 ==============================================================
4976 22:55:42.685896 Config description:
4977 22:55:42.695537 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4978 22:55:42.702789 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4979 22:55:42.705595 SELPH_MODE 0: By rank 1: By Phase
4980 22:55:42.712022 ==============================================================
4981 22:55:42.715417 GAT_TRACK_EN = 1
4982 22:55:42.719066 RX_GATING_MODE = 2
4983 22:55:42.722161 RX_GATING_TRACK_MODE = 2
4984 22:55:42.725281 SELPH_MODE = 1
4985 22:55:42.728681 PICG_EARLY_EN = 1
4986 22:55:42.729010 VALID_LAT_VALUE = 1
4987 22:55:42.735039 ==============================================================
4988 22:55:42.738341 Enter into Gating configuration >>>>
4989 22:55:42.741903 Exit from Gating configuration <<<<
4990 22:55:42.745130 Enter into DVFS_PRE_config >>>>>
4991 22:55:42.754817 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4992 22:55:42.758694 Exit from DVFS_PRE_config <<<<<
4993 22:55:42.761221 Enter into PICG configuration >>>>
4994 22:55:42.764678 Exit from PICG configuration <<<<
4995 22:55:42.768302 [RX_INPUT] configuration >>>>>
4996 22:55:42.771430 [RX_INPUT] configuration <<<<<
4997 22:55:42.778036 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4998 22:55:42.780820 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4999 22:55:42.787775 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5000 22:55:42.794634 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5001 22:55:42.800923 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5002 22:55:42.807272 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5003 22:55:42.811103 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5004 22:55:42.813851 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5005 22:55:42.817594 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5006 22:55:42.823725 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5007 22:55:42.827302 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5008 22:55:42.830713 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5009 22:55:42.833507 ===================================
5010 22:55:42.836958 LPDDR4 DRAM CONFIGURATION
5011 22:55:42.840396 ===================================
5012 22:55:42.843685 EX_ROW_EN[0] = 0x0
5013 22:55:42.843768 EX_ROW_EN[1] = 0x0
5014 22:55:42.847134 LP4Y_EN = 0x0
5015 22:55:42.847558 WORK_FSP = 0x0
5016 22:55:42.850694 WL = 0x3
5017 22:55:42.851122 RL = 0x3
5018 22:55:42.853407 BL = 0x2
5019 22:55:42.853836 RPST = 0x0
5020 22:55:42.856836 RD_PRE = 0x0
5021 22:55:42.857369 WR_PRE = 0x1
5022 22:55:42.860162 WR_PST = 0x0
5023 22:55:42.863317 DBI_WR = 0x0
5024 22:55:42.863744 DBI_RD = 0x0
5025 22:55:42.866725 OTF = 0x1
5026 22:55:42.869950 ===================================
5027 22:55:42.873202 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5028 22:55:42.876838 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5029 22:55:42.880250 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5030 22:55:42.883135 ===================================
5031 22:55:42.886919 LPDDR4 DRAM CONFIGURATION
5032 22:55:42.890064 ===================================
5033 22:55:42.893343 EX_ROW_EN[0] = 0x10
5034 22:55:42.893866 EX_ROW_EN[1] = 0x0
5035 22:55:42.896227 LP4Y_EN = 0x0
5036 22:55:42.896657 WORK_FSP = 0x0
5037 22:55:42.899593 WL = 0x3
5038 22:55:42.900156 RL = 0x3
5039 22:55:42.902910 BL = 0x2
5040 22:55:42.906617 RPST = 0x0
5041 22:55:42.907138 RD_PRE = 0x0
5042 22:55:42.909996 WR_PRE = 0x1
5043 22:55:42.910417 WR_PST = 0x0
5044 22:55:42.913029 DBI_WR = 0x0
5045 22:55:42.913604 DBI_RD = 0x0
5046 22:55:42.916214 OTF = 0x1
5047 22:55:42.919299 ===================================
5048 22:55:42.923003 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5049 22:55:42.928559 nWR fixed to 30
5050 22:55:42.931581 [ModeRegInit_LP4] CH0 RK0
5051 22:55:42.931864 [ModeRegInit_LP4] CH0 RK1
5052 22:55:42.934396 [ModeRegInit_LP4] CH1 RK0
5053 22:55:42.937840 [ModeRegInit_LP4] CH1 RK1
5054 22:55:42.938024 match AC timing 9
5055 22:55:42.944898 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5056 22:55:42.947547 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5057 22:55:42.951082 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5058 22:55:42.957395 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5059 22:55:42.960950 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5060 22:55:42.961069 ==
5061 22:55:42.964322 Dram Type= 6, Freq= 0, CH_0, rank 0
5062 22:55:42.967319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5063 22:55:42.967410 ==
5064 22:55:42.974181 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5065 22:55:42.980699 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5066 22:55:42.983769 [CA 0] Center 37 (7~68) winsize 62
5067 22:55:42.987412 [CA 1] Center 37 (7~68) winsize 62
5068 22:55:42.990179 [CA 2] Center 34 (4~65) winsize 62
5069 22:55:42.994072 [CA 3] Center 34 (4~65) winsize 62
5070 22:55:42.996776 [CA 4] Center 33 (3~63) winsize 61
5071 22:55:43.000259 [CA 5] Center 32 (2~63) winsize 62
5072 22:55:43.000366
5073 22:55:43.004311 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5074 22:55:43.004434
5075 22:55:43.006715 [CATrainingPosCal] consider 1 rank data
5076 22:55:43.010420 u2DelayCellTimex100 = 270/100 ps
5077 22:55:43.013265 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5078 22:55:43.016665 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5079 22:55:43.019891 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5080 22:55:43.026595 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5081 22:55:43.030020 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5082 22:55:43.033062 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5083 22:55:43.033158
5084 22:55:43.036413 CA PerBit enable=1, Macro0, CA PI delay=32
5085 22:55:43.036504
5086 22:55:43.039866 [CBTSetCACLKResult] CA Dly = 32
5087 22:55:43.039961 CS Dly: 6 (0~37)
5088 22:55:43.040130 ==
5089 22:55:43.043074 Dram Type= 6, Freq= 0, CH_0, rank 1
5090 22:55:43.049965 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5091 22:55:43.050053 ==
5092 22:55:43.053162 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5093 22:55:43.059959 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5094 22:55:43.063129 [CA 0] Center 37 (7~68) winsize 62
5095 22:55:43.066476 [CA 1] Center 37 (7~68) winsize 62
5096 22:55:43.069612 [CA 2] Center 34 (4~65) winsize 62
5097 22:55:43.073147 [CA 3] Center 34 (4~65) winsize 62
5098 22:55:43.076297 [CA 4] Center 33 (3~64) winsize 62
5099 22:55:43.079626 [CA 5] Center 32 (2~63) winsize 62
5100 22:55:43.079712
5101 22:55:43.082795 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5102 22:55:43.082882
5103 22:55:43.086139 [CATrainingPosCal] consider 2 rank data
5104 22:55:43.089217 u2DelayCellTimex100 = 270/100 ps
5105 22:55:43.092685 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5106 22:55:43.099150 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5107 22:55:43.103007 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5108 22:55:43.106671 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5109 22:55:43.109076 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5110 22:55:43.112208 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5111 22:55:43.112309
5112 22:55:43.116125 CA PerBit enable=1, Macro0, CA PI delay=32
5113 22:55:43.116212
5114 22:55:43.119373 [CBTSetCACLKResult] CA Dly = 32
5115 22:55:43.123001 CS Dly: 7 (0~39)
5116 22:55:43.123174
5117 22:55:43.125904 ----->DramcWriteLeveling(PI) begin...
5118 22:55:43.125999 ==
5119 22:55:43.129490 Dram Type= 6, Freq= 0, CH_0, rank 0
5120 22:55:43.132255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5121 22:55:43.132342 ==
5122 22:55:43.136043 Write leveling (Byte 0): 35 => 35
5123 22:55:43.139013 Write leveling (Byte 1): 26 => 26
5124 22:55:43.142270 DramcWriteLeveling(PI) end<-----
5125 22:55:43.142357
5126 22:55:43.142443 ==
5127 22:55:43.145995 Dram Type= 6, Freq= 0, CH_0, rank 0
5128 22:55:43.149604 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5129 22:55:43.149694 ==
5130 22:55:43.152582 [Gating] SW mode calibration
5131 22:55:43.159023 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5132 22:55:43.165999 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5133 22:55:43.168870 0 14 0 | B1->B0 | 2525 3434 | 1 1 | (0 0) (1 1)
5134 22:55:43.172339 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5135 22:55:43.179140 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5136 22:55:43.181817 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5137 22:55:43.189225 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5138 22:55:43.192225 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5139 22:55:43.195010 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5140 22:55:43.201484 0 14 28 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (0 1)
5141 22:55:43.204949 0 15 0 | B1->B0 | 3030 2323 | 1 0 | (1 1) (0 0)
5142 22:55:43.208006 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5143 22:55:43.215172 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5144 22:55:43.218147 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5145 22:55:43.221468 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5146 22:55:43.228256 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5147 22:55:43.231384 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5148 22:55:43.234697 0 15 28 | B1->B0 | 2424 4040 | 0 0 | (0 0) (0 0)
5149 22:55:43.240904 1 0 0 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
5150 22:55:43.244230 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5151 22:55:43.247802 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5152 22:55:43.254280 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5153 22:55:43.257787 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5154 22:55:43.260732 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5155 22:55:43.264250 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5156 22:55:43.270793 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5157 22:55:43.273724 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
5158 22:55:43.280345 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5159 22:55:43.284131 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5160 22:55:43.287154 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5161 22:55:43.293869 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5162 22:55:43.297314 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5163 22:55:43.300817 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5164 22:55:43.307406 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5165 22:55:43.311121 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5166 22:55:43.313964 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5167 22:55:43.320203 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5168 22:55:43.323922 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5169 22:55:43.326971 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5170 22:55:43.333727 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5171 22:55:43.337271 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5172 22:55:43.339995 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5173 22:55:43.347159 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5174 22:55:43.347699 Total UI for P1: 0, mck2ui 16
5175 22:55:43.353534 best dqsien dly found for B0: ( 1, 2, 28)
5176 22:55:43.356928 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5177 22:55:43.360107 Total UI for P1: 0, mck2ui 16
5178 22:55:43.363316 best dqsien dly found for B1: ( 1, 3, 0)
5179 22:55:43.366388 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5180 22:55:43.369527 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5181 22:55:43.369947
5182 22:55:43.373435 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5183 22:55:43.376096 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5184 22:55:43.379589 [Gating] SW calibration Done
5185 22:55:43.380007 ==
5186 22:55:43.382979 Dram Type= 6, Freq= 0, CH_0, rank 0
5187 22:55:43.386015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5188 22:55:43.389136 ==
5189 22:55:43.389572 RX Vref Scan: 0
5190 22:55:43.389906
5191 22:55:43.392760 RX Vref 0 -> 0, step: 1
5192 22:55:43.393182
5193 22:55:43.395657 RX Delay -80 -> 252, step: 8
5194 22:55:43.399156 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5195 22:55:43.402390 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5196 22:55:43.405910 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5197 22:55:43.409365 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5198 22:55:43.412257 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5199 22:55:43.419306 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5200 22:55:43.422360 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5201 22:55:43.425246 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5202 22:55:43.428648 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5203 22:55:43.431940 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5204 22:55:43.438942 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5205 22:55:43.441584 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5206 22:55:43.445209 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5207 22:55:43.448393 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5208 22:55:43.451605 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5209 22:55:43.458100 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5210 22:55:43.458408 ==
5211 22:55:43.461780 Dram Type= 6, Freq= 0, CH_0, rank 0
5212 22:55:43.465093 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5213 22:55:43.465304 ==
5214 22:55:43.465450 DQS Delay:
5215 22:55:43.467894 DQS0 = 0, DQS1 = 0
5216 22:55:43.468082 DQM Delay:
5217 22:55:43.471711 DQM0 = 100, DQM1 = 88
5218 22:55:43.472016 DQ Delay:
5219 22:55:43.474659 DQ0 =99, DQ1 =99, DQ2 =95, DQ3 =95
5220 22:55:43.478522 DQ4 =103, DQ5 =87, DQ6 =111, DQ7 =111
5221 22:55:43.482187 DQ8 =83, DQ9 =75, DQ10 =87, DQ11 =83
5222 22:55:43.484734 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5223 22:55:43.485061
5224 22:55:43.485472
5225 22:55:43.485795 ==
5226 22:55:43.488176 Dram Type= 6, Freq= 0, CH_0, rank 0
5227 22:55:43.491828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5228 22:55:43.494901 ==
5229 22:55:43.495326
5230 22:55:43.495662
5231 22:55:43.495975 TX Vref Scan disable
5232 22:55:43.497825 == TX Byte 0 ==
5233 22:55:43.501230 Update DQ dly =720 (2 ,6, 16) DQ OEN =(2 ,3)
5234 22:55:43.504742 Update DQM dly =720 (2 ,6, 16) DQM OEN =(2 ,3)
5235 22:55:43.507762 == TX Byte 1 ==
5236 22:55:43.511359 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5237 22:55:43.514562 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5238 22:55:43.518125 ==
5239 22:55:43.521129 Dram Type= 6, Freq= 0, CH_0, rank 0
5240 22:55:43.524314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5241 22:55:43.524741 ==
5242 22:55:43.525080
5243 22:55:43.525448
5244 22:55:43.527853 TX Vref Scan disable
5245 22:55:43.528434 == TX Byte 0 ==
5246 22:55:43.534571 Update DQ dly =719 (2 ,6, 15) DQ OEN =(2 ,3)
5247 22:55:43.537336 Update DQM dly =719 (2 ,6, 15) DQM OEN =(2 ,3)
5248 22:55:43.537811 == TX Byte 1 ==
5249 22:55:43.544108 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5250 22:55:43.547498 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5251 22:55:43.547928
5252 22:55:43.548319 [DATLAT]
5253 22:55:43.550667 Freq=933, CH0 RK0
5254 22:55:43.551097
5255 22:55:43.551435 DATLAT Default: 0xd
5256 22:55:43.553960 0, 0xFFFF, sum = 0
5257 22:55:43.554398 1, 0xFFFF, sum = 0
5258 22:55:43.557646 2, 0xFFFF, sum = 0
5259 22:55:43.560582 3, 0xFFFF, sum = 0
5260 22:55:43.561016 4, 0xFFFF, sum = 0
5261 22:55:43.564174 5, 0xFFFF, sum = 0
5262 22:55:43.564608 6, 0xFFFF, sum = 0
5263 22:55:43.567729 7, 0xFFFF, sum = 0
5264 22:55:43.568206 8, 0xFFFF, sum = 0
5265 22:55:43.570821 9, 0xFFFF, sum = 0
5266 22:55:43.571253 10, 0x0, sum = 1
5267 22:55:43.573873 11, 0x0, sum = 2
5268 22:55:43.574308 12, 0x0, sum = 3
5269 22:55:43.576924 13, 0x0, sum = 4
5270 22:55:43.577630 best_step = 11
5271 22:55:43.577989
5272 22:55:43.578494 ==
5273 22:55:43.580899 Dram Type= 6, Freq= 0, CH_0, rank 0
5274 22:55:43.583185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5275 22:55:43.583742 ==
5276 22:55:43.586679 RX Vref Scan: 1
5277 22:55:43.587105
5278 22:55:43.590356 RX Vref 0 -> 0, step: 1
5279 22:55:43.590766
5280 22:55:43.591322 RX Delay -61 -> 252, step: 4
5281 22:55:43.593754
5282 22:55:43.594190 Set Vref, RX VrefLevel [Byte0]: 53
5283 22:55:43.596695 [Byte1]: 49
5284 22:55:43.601444
5285 22:55:43.601868 Final RX Vref Byte 0 = 53 to rank0
5286 22:55:43.605440 Final RX Vref Byte 1 = 49 to rank0
5287 22:55:43.607990 Final RX Vref Byte 0 = 53 to rank1
5288 22:55:43.611328 Final RX Vref Byte 1 = 49 to rank1==
5289 22:55:43.614747 Dram Type= 6, Freq= 0, CH_0, rank 0
5290 22:55:43.621037 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5291 22:55:43.621338 ==
5292 22:55:43.621644 DQS Delay:
5293 22:55:43.624735 DQS0 = 0, DQS1 = 0
5294 22:55:43.625039 DQM Delay:
5295 22:55:43.625258 DQM0 = 99, DQM1 = 87
5296 22:55:43.628008 DQ Delay:
5297 22:55:43.631463 DQ0 =100, DQ1 =98, DQ2 =94, DQ3 =94
5298 22:55:43.634301 DQ4 =100, DQ5 =90, DQ6 =110, DQ7 =106
5299 22:55:43.637945 DQ8 =80, DQ9 =74, DQ10 =88, DQ11 =82
5300 22:55:43.641330 DQ12 =92, DQ13 =92, DQ14 =96, DQ15 =94
5301 22:55:43.641615
5302 22:55:43.641864
5303 22:55:43.647683 [DQSOSCAuto] RK0, (LSB)MR18= 0x1711, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 414 ps
5304 22:55:43.650811 CH0 RK0: MR19=505, MR18=1711
5305 22:55:43.657693 CH0_RK0: MR19=0x505, MR18=0x1711, DQSOSC=414, MR23=63, INC=63, DEC=42
5306 22:55:43.658075
5307 22:55:43.661115 ----->DramcWriteLeveling(PI) begin...
5308 22:55:43.661487 ==
5309 22:55:43.664131 Dram Type= 6, Freq= 0, CH_0, rank 1
5310 22:55:43.668195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5311 22:55:43.668714 ==
5312 22:55:43.671765 Write leveling (Byte 0): 34 => 34
5313 22:55:43.674169 Write leveling (Byte 1): 29 => 29
5314 22:55:43.677767 DramcWriteLeveling(PI) end<-----
5315 22:55:43.678330
5316 22:55:43.678706 ==
5317 22:55:43.680848 Dram Type= 6, Freq= 0, CH_0, rank 1
5318 22:55:43.687432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5319 22:55:43.687998 ==
5320 22:55:43.688430 [Gating] SW mode calibration
5321 22:55:43.697112 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5322 22:55:43.700643 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5323 22:55:43.707062 0 14 0 | B1->B0 | 2929 3434 | 1 1 | (0 0) (1 1)
5324 22:55:43.710601 0 14 4 | B1->B0 | 3333 3434 | 1 1 | (0 0) (1 1)
5325 22:55:43.713664 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5326 22:55:43.720199 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5327 22:55:43.723748 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5328 22:55:43.727509 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5329 22:55:43.733464 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5330 22:55:43.736898 0 14 28 | B1->B0 | 3434 2929 | 0 0 | (0 0) (1 1)
5331 22:55:43.740412 0 15 0 | B1->B0 | 2f2f 2323 | 0 0 | (1 1) (0 0)
5332 22:55:43.747053 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5333 22:55:43.750279 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5334 22:55:43.754337 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5335 22:55:43.759459 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5336 22:55:43.763038 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5337 22:55:43.767026 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5338 22:55:43.773287 0 15 28 | B1->B0 | 2626 3c3c | 0 0 | (0 0) (0 0)
5339 22:55:43.776510 1 0 0 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
5340 22:55:43.779587 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5341 22:55:43.786260 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5342 22:55:43.789753 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5343 22:55:43.792882 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5344 22:55:43.799461 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5345 22:55:43.802635 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5346 22:55:43.805930 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5347 22:55:43.812407 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5348 22:55:43.815850 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5349 22:55:43.818905 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5350 22:55:43.825647 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5351 22:55:43.829112 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5352 22:55:43.832531 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5353 22:55:43.838888 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5354 22:55:43.842375 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5355 22:55:43.845279 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5356 22:55:43.851863 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5357 22:55:43.855778 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5358 22:55:43.858415 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5359 22:55:43.866020 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5360 22:55:43.868372 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5361 22:55:43.871484 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5362 22:55:43.878587 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5363 22:55:43.879105 Total UI for P1: 0, mck2ui 16
5364 22:55:43.885191 best dqsien dly found for B0: ( 1, 2, 26)
5365 22:55:43.888164 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5366 22:55:43.891583 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5367 22:55:43.898181 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5368 22:55:43.898741 Total UI for P1: 0, mck2ui 16
5369 22:55:43.904825 best dqsien dly found for B1: ( 1, 3, 2)
5370 22:55:43.907732 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5371 22:55:43.911554 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5372 22:55:43.912119
5373 22:55:43.914573 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5374 22:55:43.917580 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5375 22:55:43.921544 [Gating] SW calibration Done
5376 22:55:43.922095 ==
5377 22:55:43.924171 Dram Type= 6, Freq= 0, CH_0, rank 1
5378 22:55:43.927650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5379 22:55:43.928252 ==
5380 22:55:43.931030 RX Vref Scan: 0
5381 22:55:43.931485
5382 22:55:43.931855 RX Vref 0 -> 0, step: 1
5383 22:55:43.932255
5384 22:55:43.934965 RX Delay -80 -> 252, step: 8
5385 22:55:43.936946 iDelay=200, Bit 0, Center 99 (8 ~ 191) 184
5386 22:55:43.944184 iDelay=200, Bit 1, Center 99 (0 ~ 199) 200
5387 22:55:43.947376 iDelay=200, Bit 2, Center 91 (-8 ~ 191) 200
5388 22:55:43.950850 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5389 22:55:43.954005 iDelay=200, Bit 4, Center 103 (8 ~ 199) 192
5390 22:55:43.957005 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5391 22:55:43.960290 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5392 22:55:43.967478 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5393 22:55:43.970527 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5394 22:55:43.974017 iDelay=200, Bit 9, Center 75 (-16 ~ 167) 184
5395 22:55:43.977003 iDelay=200, Bit 10, Center 87 (0 ~ 175) 176
5396 22:55:43.979952 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5397 22:55:43.986800 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5398 22:55:43.990371 iDelay=200, Bit 13, Center 91 (0 ~ 183) 184
5399 22:55:43.994090 iDelay=200, Bit 14, Center 99 (8 ~ 191) 184
5400 22:55:43.996727 iDelay=200, Bit 15, Center 95 (8 ~ 183) 176
5401 22:55:43.997193 ==
5402 22:55:43.999727 Dram Type= 6, Freq= 0, CH_0, rank 1
5403 22:55:44.003226 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5404 22:55:44.006309 ==
5405 22:55:44.006725 DQS Delay:
5406 22:55:44.007060 DQS0 = 0, DQS1 = 0
5407 22:55:44.009878 DQM Delay:
5408 22:55:44.010295 DQM0 = 97, DQM1 = 88
5409 22:55:44.012950 DQ Delay:
5410 22:55:44.016156 DQ0 =99, DQ1 =99, DQ2 =91, DQ3 =95
5411 22:55:44.019671 DQ4 =103, DQ5 =87, DQ6 =103, DQ7 =103
5412 22:55:44.023262 DQ8 =83, DQ9 =75, DQ10 =87, DQ11 =83
5413 22:55:44.026088 DQ12 =95, DQ13 =91, DQ14 =99, DQ15 =95
5414 22:55:44.026506
5415 22:55:44.026834
5416 22:55:44.027171 ==
5417 22:55:44.029705 Dram Type= 6, Freq= 0, CH_0, rank 1
5418 22:55:44.032686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5419 22:55:44.033264 ==
5420 22:55:44.033604
5421 22:55:44.033910
5422 22:55:44.036165 TX Vref Scan disable
5423 22:55:44.036591 == TX Byte 0 ==
5424 22:55:44.042483 Update DQ dly =719 (2 ,6, 15) DQ OEN =(2 ,3)
5425 22:55:44.045968 Update DQM dly =719 (2 ,6, 15) DQM OEN =(2 ,3)
5426 22:55:44.049324 == TX Byte 1 ==
5427 22:55:44.052816 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5428 22:55:44.055559 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5429 22:55:44.055987 ==
5430 22:55:44.058951 Dram Type= 6, Freq= 0, CH_0, rank 1
5431 22:55:44.062263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5432 22:55:44.065601 ==
5433 22:55:44.066181
5434 22:55:44.066529
5435 22:55:44.066848 TX Vref Scan disable
5436 22:55:44.068938 == TX Byte 0 ==
5437 22:55:44.072595 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5438 22:55:44.079202 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5439 22:55:44.079711 == TX Byte 1 ==
5440 22:55:44.082567 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5441 22:55:44.088584 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5442 22:55:44.089051
5443 22:55:44.089393 [DATLAT]
5444 22:55:44.089707 Freq=933, CH0 RK1
5445 22:55:44.090014
5446 22:55:44.092273 DATLAT Default: 0xb
5447 22:55:44.095920 0, 0xFFFF, sum = 0
5448 22:55:44.096495 1, 0xFFFF, sum = 0
5449 22:55:44.098664 2, 0xFFFF, sum = 0
5450 22:55:44.099248 3, 0xFFFF, sum = 0
5451 22:55:44.101928 4, 0xFFFF, sum = 0
5452 22:55:44.102521 5, 0xFFFF, sum = 0
5453 22:55:44.105773 6, 0xFFFF, sum = 0
5454 22:55:44.106277 7, 0xFFFF, sum = 0
5455 22:55:44.108786 8, 0xFFFF, sum = 0
5456 22:55:44.109318 9, 0xFFFF, sum = 0
5457 22:55:44.111903 10, 0x0, sum = 1
5458 22:55:44.112530 11, 0x0, sum = 2
5459 22:55:44.115126 12, 0x0, sum = 3
5460 22:55:44.115627 13, 0x0, sum = 4
5461 22:55:44.118795 best_step = 11
5462 22:55:44.119318
5463 22:55:44.119659 ==
5464 22:55:44.121837 Dram Type= 6, Freq= 0, CH_0, rank 1
5465 22:55:44.125153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5466 22:55:44.125589 ==
5467 22:55:44.125960 RX Vref Scan: 0
5468 22:55:44.128152
5469 22:55:44.128579 RX Vref 0 -> 0, step: 1
5470 22:55:44.128919
5471 22:55:44.131413 RX Delay -61 -> 252, step: 4
5472 22:55:44.138577 iDelay=195, Bit 0, Center 98 (11 ~ 186) 176
5473 22:55:44.141196 iDelay=195, Bit 1, Center 98 (7 ~ 190) 184
5474 22:55:44.144757 iDelay=195, Bit 2, Center 92 (3 ~ 182) 180
5475 22:55:44.147829 iDelay=195, Bit 3, Center 96 (7 ~ 186) 180
5476 22:55:44.151318 iDelay=195, Bit 4, Center 100 (7 ~ 194) 188
5477 22:55:44.155042 iDelay=195, Bit 5, Center 86 (-5 ~ 178) 184
5478 22:55:44.161513 iDelay=195, Bit 6, Center 108 (23 ~ 194) 172
5479 22:55:44.164303 iDelay=195, Bit 7, Center 106 (19 ~ 194) 176
5480 22:55:44.167924 iDelay=195, Bit 8, Center 78 (-9 ~ 166) 176
5481 22:55:44.170853 iDelay=195, Bit 9, Center 76 (-13 ~ 166) 180
5482 22:55:44.174912 iDelay=195, Bit 10, Center 90 (3 ~ 178) 176
5483 22:55:44.181069 iDelay=195, Bit 11, Center 82 (-5 ~ 170) 176
5484 22:55:44.184146 iDelay=195, Bit 12, Center 92 (7 ~ 178) 172
5485 22:55:44.187998 iDelay=195, Bit 13, Center 92 (7 ~ 178) 172
5486 22:55:44.191018 iDelay=195, Bit 14, Center 98 (11 ~ 186) 176
5487 22:55:44.194457 iDelay=195, Bit 15, Center 94 (7 ~ 182) 176
5488 22:55:44.195019 ==
5489 22:55:44.197752 Dram Type= 6, Freq= 0, CH_0, rank 1
5490 22:55:44.204445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5491 22:55:44.205006 ==
5492 22:55:44.205375 DQS Delay:
5493 22:55:44.207222 DQS0 = 0, DQS1 = 0
5494 22:55:44.207706 DQM Delay:
5495 22:55:44.211002 DQM0 = 98, DQM1 = 87
5496 22:55:44.211421 DQ Delay:
5497 22:55:44.214312 DQ0 =98, DQ1 =98, DQ2 =92, DQ3 =96
5498 22:55:44.217354 DQ4 =100, DQ5 =86, DQ6 =108, DQ7 =106
5499 22:55:44.220523 DQ8 =78, DQ9 =76, DQ10 =90, DQ11 =82
5500 22:55:44.223733 DQ12 =92, DQ13 =92, DQ14 =98, DQ15 =94
5501 22:55:44.224274
5502 22:55:44.224734
5503 22:55:44.231207 [DQSOSCAuto] RK1, (LSB)MR18= 0x1512, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 415 ps
5504 22:55:44.233630 CH0 RK1: MR19=505, MR18=1512
5505 22:55:44.240781 CH0_RK1: MR19=0x505, MR18=0x1512, DQSOSC=415, MR23=63, INC=62, DEC=41
5506 22:55:44.243817 [RxdqsGatingPostProcess] freq 933
5507 22:55:44.250656 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5508 22:55:44.253673 best DQS0 dly(2T, 0.5T) = (0, 10)
5509 22:55:44.254149 best DQS1 dly(2T, 0.5T) = (0, 11)
5510 22:55:44.256585 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5511 22:55:44.259931 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5512 22:55:44.263106 best DQS0 dly(2T, 0.5T) = (0, 10)
5513 22:55:44.267079 best DQS1 dly(2T, 0.5T) = (0, 11)
5514 22:55:44.270194 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5515 22:55:44.273411 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5516 22:55:44.276668 Pre-setting of DQS Precalculation
5517 22:55:44.283830 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5518 22:55:44.284451 ==
5519 22:55:44.287027 Dram Type= 6, Freq= 0, CH_1, rank 0
5520 22:55:44.289483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5521 22:55:44.289968 ==
5522 22:55:44.296593 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5523 22:55:44.303309 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5524 22:55:44.306180 [CA 0] Center 36 (6~67) winsize 62
5525 22:55:44.309722 [CA 1] Center 36 (6~67) winsize 62
5526 22:55:44.312594 [CA 2] Center 34 (4~65) winsize 62
5527 22:55:44.315906 [CA 3] Center 34 (3~65) winsize 63
5528 22:55:44.319842 [CA 4] Center 34 (4~65) winsize 62
5529 22:55:44.323109 [CA 5] Center 33 (3~64) winsize 62
5530 22:55:44.323684
5531 22:55:44.326238 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5532 22:55:44.326806
5533 22:55:44.329356 [CATrainingPosCal] consider 1 rank data
5534 22:55:44.332505 u2DelayCellTimex100 = 270/100 ps
5535 22:55:44.336210 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5536 22:55:44.338999 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5537 22:55:44.342961 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5538 22:55:44.345505 CA3 delay=34 (3~65),Diff = 1 PI (6 cell)
5539 22:55:44.348798 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5540 22:55:44.352575 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5541 22:55:44.353180
5542 22:55:44.359751 CA PerBit enable=1, Macro0, CA PI delay=33
5543 22:55:44.360442
5544 22:55:44.360945 [CBTSetCACLKResult] CA Dly = 33
5545 22:55:44.362072 CS Dly: 4 (0~35)
5546 22:55:44.362545 ==
5547 22:55:44.365200 Dram Type= 6, Freq= 0, CH_1, rank 1
5548 22:55:44.368690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5549 22:55:44.369125 ==
5550 22:55:44.375628 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5551 22:55:44.382158 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5552 22:55:44.385166 [CA 0] Center 36 (6~67) winsize 62
5553 22:55:44.388970 [CA 1] Center 36 (6~67) winsize 62
5554 22:55:44.391853 [CA 2] Center 34 (4~65) winsize 62
5555 22:55:44.395262 [CA 3] Center 33 (3~64) winsize 62
5556 22:55:44.398855 [CA 4] Center 33 (3~64) winsize 62
5557 22:55:44.401800 [CA 5] Center 33 (3~64) winsize 62
5558 22:55:44.402371
5559 22:55:44.405223 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5560 22:55:44.405795
5561 22:55:44.408445 [CATrainingPosCal] consider 2 rank data
5562 22:55:44.411963 u2DelayCellTimex100 = 270/100 ps
5563 22:55:44.415284 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5564 22:55:44.418393 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5565 22:55:44.421357 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5566 22:55:44.425040 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5567 22:55:44.428314 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5568 22:55:44.435003 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5569 22:55:44.435577
5570 22:55:44.438032 CA PerBit enable=1, Macro0, CA PI delay=33
5571 22:55:44.438501
5572 22:55:44.441138 [CBTSetCACLKResult] CA Dly = 33
5573 22:55:44.441607 CS Dly: 5 (0~38)
5574 22:55:44.441984
5575 22:55:44.444518 ----->DramcWriteLeveling(PI) begin...
5576 22:55:44.444992 ==
5577 22:55:44.447796 Dram Type= 6, Freq= 0, CH_1, rank 0
5578 22:55:44.454411 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5579 22:55:44.454931 ==
5580 22:55:44.458756 Write leveling (Byte 0): 25 => 25
5581 22:55:44.461036 Write leveling (Byte 1): 29 => 29
5582 22:55:44.461485 DramcWriteLeveling(PI) end<-----
5583 22:55:44.461830
5584 22:55:44.464499 ==
5585 22:55:44.467646 Dram Type= 6, Freq= 0, CH_1, rank 0
5586 22:55:44.471271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5587 22:55:44.471710 ==
5588 22:55:44.474208 [Gating] SW mode calibration
5589 22:55:44.481295 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5590 22:55:44.484346 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5591 22:55:44.490778 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5592 22:55:44.494543 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5593 22:55:44.497825 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5594 22:55:44.504183 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5595 22:55:44.507051 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5596 22:55:44.510874 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5597 22:55:44.517091 0 14 24 | B1->B0 | 3333 3030 | 0 0 | (1 0) (0 0)
5598 22:55:44.520585 0 14 28 | B1->B0 | 3030 2525 | 0 0 | (0 1) (0 0)
5599 22:55:44.524169 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5600 22:55:44.530794 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5601 22:55:44.534013 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5602 22:55:44.536979 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5603 22:55:44.543028 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5604 22:55:44.547083 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5605 22:55:44.549940 0 15 24 | B1->B0 | 2424 2d2d | 0 0 | (0 0) (0 0)
5606 22:55:44.557721 0 15 28 | B1->B0 | 3434 4141 | 0 0 | (0 0) (0 0)
5607 22:55:44.560203 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5608 22:55:44.563140 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5609 22:55:44.569885 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5610 22:55:44.573252 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5611 22:55:44.576488 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5612 22:55:44.582874 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5613 22:55:44.586408 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5614 22:55:44.589439 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5615 22:55:44.595796 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5616 22:55:44.599365 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5617 22:55:44.602575 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5618 22:55:44.609058 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5619 22:55:44.612565 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5620 22:55:44.615569 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5621 22:55:44.622222 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5622 22:55:44.625817 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5623 22:55:44.628995 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5624 22:55:44.635902 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5625 22:55:44.638767 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5626 22:55:44.642254 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5627 22:55:44.648508 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5628 22:55:44.652166 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5629 22:55:44.655847 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5630 22:55:44.662423 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5631 22:55:44.665363 Total UI for P1: 0, mck2ui 16
5632 22:55:44.668274 best dqsien dly found for B1: ( 1, 2, 26)
5633 22:55:44.671497 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5634 22:55:44.675168 Total UI for P1: 0, mck2ui 16
5635 22:55:44.678118 best dqsien dly found for B0: ( 1, 2, 26)
5636 22:55:44.681663 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5637 22:55:44.684642 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5638 22:55:44.685065
5639 22:55:44.688104 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5640 22:55:44.694493 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5641 22:55:44.695005 [Gating] SW calibration Done
5642 22:55:44.695344 ==
5643 22:55:44.697973 Dram Type= 6, Freq= 0, CH_1, rank 0
5644 22:55:44.704523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5645 22:55:44.705012 ==
5646 22:55:44.705346 RX Vref Scan: 0
5647 22:55:44.705659
5648 22:55:44.707912 RX Vref 0 -> 0, step: 1
5649 22:55:44.708379
5650 22:55:44.710741 RX Delay -80 -> 252, step: 8
5651 22:55:44.714309 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5652 22:55:44.718043 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5653 22:55:44.720587 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5654 22:55:44.727377 iDelay=208, Bit 3, Center 99 (0 ~ 199) 200
5655 22:55:44.731033 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5656 22:55:44.734308 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5657 22:55:44.737098 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5658 22:55:44.740153 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5659 22:55:44.743851 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5660 22:55:44.750166 iDelay=208, Bit 9, Center 87 (-8 ~ 183) 192
5661 22:55:44.753938 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5662 22:55:44.757254 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5663 22:55:44.760430 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5664 22:55:44.764763 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5665 22:55:44.770625 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5666 22:55:44.773419 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5667 22:55:44.773854 ==
5668 22:55:44.776852 Dram Type= 6, Freq= 0, CH_1, rank 0
5669 22:55:44.779858 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5670 22:55:44.780327 ==
5671 22:55:44.783204 DQS Delay:
5672 22:55:44.783648 DQS0 = 0, DQS1 = 0
5673 22:55:44.784123 DQM Delay:
5674 22:55:44.786513 DQM0 = 100, DQM1 = 96
5675 22:55:44.786945 DQ Delay:
5676 22:55:44.789477 DQ0 =103, DQ1 =95, DQ2 =91, DQ3 =99
5677 22:55:44.792878 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =95
5678 22:55:44.796373 DQ8 =83, DQ9 =87, DQ10 =95, DQ11 =91
5679 22:55:44.799423 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5680 22:55:44.802594
5681 22:55:44.803139
5682 22:55:44.803583 ==
5683 22:55:44.806115 Dram Type= 6, Freq= 0, CH_1, rank 0
5684 22:55:44.809625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5685 22:55:44.810139 ==
5686 22:55:44.810587
5687 22:55:44.811003
5688 22:55:44.813152 TX Vref Scan disable
5689 22:55:44.813589 == TX Byte 0 ==
5690 22:55:44.819095 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5691 22:55:44.822810 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5692 22:55:44.823343 == TX Byte 1 ==
5693 22:55:44.829221 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5694 22:55:44.832525 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5695 22:55:44.833037 ==
5696 22:55:44.836144 Dram Type= 6, Freq= 0, CH_1, rank 0
5697 22:55:44.839093 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5698 22:55:44.839622 ==
5699 22:55:44.840101
5700 22:55:44.840514
5701 22:55:44.842757 TX Vref Scan disable
5702 22:55:44.845522 == TX Byte 0 ==
5703 22:55:44.849120 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5704 22:55:44.852264 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5705 22:55:44.856188 == TX Byte 1 ==
5706 22:55:44.859229 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5707 22:55:44.862421 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5708 22:55:44.862886
5709 22:55:44.865510 [DATLAT]
5710 22:55:44.865946 Freq=933, CH1 RK0
5711 22:55:44.866391
5712 22:55:44.868955 DATLAT Default: 0xd
5713 22:55:44.869392 0, 0xFFFF, sum = 0
5714 22:55:44.872019 1, 0xFFFF, sum = 0
5715 22:55:44.872489 2, 0xFFFF, sum = 0
5716 22:55:44.875168 3, 0xFFFF, sum = 0
5717 22:55:44.875609 4, 0xFFFF, sum = 0
5718 22:55:44.878525 5, 0xFFFF, sum = 0
5719 22:55:44.882097 6, 0xFFFF, sum = 0
5720 22:55:44.882651 7, 0xFFFF, sum = 0
5721 22:55:44.885352 8, 0xFFFF, sum = 0
5722 22:55:44.885909 9, 0xFFFF, sum = 0
5723 22:55:44.888642 10, 0x0, sum = 1
5724 22:55:44.889213 11, 0x0, sum = 2
5725 22:55:44.892275 12, 0x0, sum = 3
5726 22:55:44.892769 13, 0x0, sum = 4
5727 22:55:44.893212 best_step = 11
5728 22:55:44.893627
5729 22:55:44.895412 ==
5730 22:55:44.898498 Dram Type= 6, Freq= 0, CH_1, rank 0
5731 22:55:44.901712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5732 22:55:44.902151 ==
5733 22:55:44.902596 RX Vref Scan: 1
5734 22:55:44.903014
5735 22:55:44.904999 RX Vref 0 -> 0, step: 1
5736 22:55:44.905441
5737 22:55:44.908512 RX Delay -53 -> 252, step: 4
5738 22:55:44.908948
5739 22:55:44.911989 Set Vref, RX VrefLevel [Byte0]: 50
5740 22:55:44.914974 [Byte1]: 49
5741 22:55:44.915414
5742 22:55:44.918687 Final RX Vref Byte 0 = 50 to rank0
5743 22:55:44.921978 Final RX Vref Byte 1 = 49 to rank0
5744 22:55:44.925174 Final RX Vref Byte 0 = 50 to rank1
5745 22:55:44.928883 Final RX Vref Byte 1 = 49 to rank1==
5746 22:55:44.931815 Dram Type= 6, Freq= 0, CH_1, rank 0
5747 22:55:44.937560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5748 22:55:44.938068 ==
5749 22:55:44.938515 DQS Delay:
5750 22:55:44.938934 DQS0 = 0, DQS1 = 0
5751 22:55:44.941257 DQM Delay:
5752 22:55:44.941800 DQM0 = 98, DQM1 = 94
5753 22:55:44.944329 DQ Delay:
5754 22:55:44.947426 DQ0 =102, DQ1 =94, DQ2 =88, DQ3 =100
5755 22:55:44.951282 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =94
5756 22:55:44.954245 DQ8 =80, DQ9 =84, DQ10 =94, DQ11 =88
5757 22:55:44.957386 DQ12 =100, DQ13 =104, DQ14 =100, DQ15 =102
5758 22:55:44.957821
5759 22:55:44.958261
5760 22:55:44.963847 [DQSOSCAuto] RK0, (LSB)MR18= 0x615, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 420 ps
5761 22:55:44.967804 CH1 RK0: MR19=505, MR18=615
5762 22:55:44.974143 CH1_RK0: MR19=0x505, MR18=0x615, DQSOSC=415, MR23=63, INC=62, DEC=41
5763 22:55:44.974687
5764 22:55:44.977722 ----->DramcWriteLeveling(PI) begin...
5765 22:55:44.978264 ==
5766 22:55:44.980910 Dram Type= 6, Freq= 0, CH_1, rank 1
5767 22:55:44.983884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5768 22:55:44.984461 ==
5769 22:55:44.988093 Write leveling (Byte 0): 26 => 26
5770 22:55:44.990459 Write leveling (Byte 1): 29 => 29
5771 22:55:44.994107 DramcWriteLeveling(PI) end<-----
5772 22:55:44.994544
5773 22:55:44.994985 ==
5774 22:55:44.997561 Dram Type= 6, Freq= 0, CH_1, rank 1
5775 22:55:45.003753 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5776 22:55:45.004319 ==
5777 22:55:45.004770 [Gating] SW mode calibration
5778 22:55:45.014074 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5779 22:55:45.017119 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5780 22:55:45.020232 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5781 22:55:45.026906 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5782 22:55:45.030311 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5783 22:55:45.036774 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5784 22:55:45.040013 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5785 22:55:45.043321 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5786 22:55:45.049948 0 14 24 | B1->B0 | 3333 3030 | 1 1 | (1 1) (1 0)
5787 22:55:45.052747 0 14 28 | B1->B0 | 2d2d 2323 | 0 0 | (1 1) (0 0)
5788 22:55:45.056801 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5789 22:55:45.062830 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5790 22:55:45.066388 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5791 22:55:45.069317 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5792 22:55:45.076576 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5793 22:55:45.079753 0 15 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5794 22:55:45.082850 0 15 24 | B1->B0 | 2626 3939 | 0 0 | (0 0) (0 0)
5795 22:55:45.088991 0 15 28 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
5796 22:55:45.092435 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5797 22:55:45.096430 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5798 22:55:45.102702 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5799 22:55:45.105500 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5800 22:55:45.109695 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5801 22:55:45.115383 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5802 22:55:45.118905 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5803 22:55:45.121967 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5804 22:55:45.128716 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5805 22:55:45.132173 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5806 22:55:45.135391 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5807 22:55:45.142128 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5808 22:55:45.145383 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5809 22:55:45.148486 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5810 22:55:45.154735 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5811 22:55:45.158875 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5812 22:55:45.161871 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5813 22:55:45.167978 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5814 22:55:45.172027 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5815 22:55:45.175261 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5816 22:55:45.181603 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5817 22:55:45.184610 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5818 22:55:45.187674 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5819 22:55:45.191234 Total UI for P1: 0, mck2ui 16
5820 22:55:45.194276 best dqsien dly found for B0: ( 1, 2, 22)
5821 22:55:45.201298 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5822 22:55:45.204686 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5823 22:55:45.207582 Total UI for P1: 0, mck2ui 16
5824 22:55:45.211525 best dqsien dly found for B1: ( 1, 2, 26)
5825 22:55:45.214170 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5826 22:55:45.217568 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5827 22:55:45.218073
5828 22:55:45.220712 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5829 22:55:45.224123 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5830 22:55:45.227329 [Gating] SW calibration Done
5831 22:55:45.227799 ==
5832 22:55:45.230674 Dram Type= 6, Freq= 0, CH_1, rank 1
5833 22:55:45.236900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5834 22:55:45.237397 ==
5835 22:55:45.237743 RX Vref Scan: 0
5836 22:55:45.238067
5837 22:55:45.240698 RX Vref 0 -> 0, step: 1
5838 22:55:45.241125
5839 22:55:45.243630 RX Delay -80 -> 252, step: 8
5840 22:55:45.247528 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5841 22:55:45.250457 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5842 22:55:45.253504 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5843 22:55:45.256762 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5844 22:55:45.263335 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5845 22:55:45.266369 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5846 22:55:45.270072 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5847 22:55:45.272969 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5848 22:55:45.276904 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5849 22:55:45.279547 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5850 22:55:45.286430 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5851 22:55:45.290059 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5852 22:55:45.293243 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5853 22:55:45.296620 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5854 22:55:45.299314 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5855 22:55:45.306223 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5856 22:55:45.306638 ==
5857 22:55:45.309323 Dram Type= 6, Freq= 0, CH_1, rank 1
5858 22:55:45.312647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5859 22:55:45.313080 ==
5860 22:55:45.313446 DQS Delay:
5861 22:55:45.315981 DQS0 = 0, DQS1 = 0
5862 22:55:45.316512 DQM Delay:
5863 22:55:45.319138 DQM0 = 97, DQM1 = 94
5864 22:55:45.319784 DQ Delay:
5865 22:55:45.322863 DQ0 =103, DQ1 =95, DQ2 =87, DQ3 =95
5866 22:55:45.326188 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =95
5867 22:55:45.329319 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87
5868 22:55:45.332720 DQ12 =103, DQ13 =103, DQ14 =95, DQ15 =103
5869 22:55:45.333254
5870 22:55:45.333696
5871 22:55:45.334105 ==
5872 22:55:45.335475 Dram Type= 6, Freq= 0, CH_1, rank 1
5873 22:55:45.342051 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5874 22:55:45.342581 ==
5875 22:55:45.343025
5876 22:55:45.343439
5877 22:55:45.343840 TX Vref Scan disable
5878 22:55:45.345529 == TX Byte 0 ==
5879 22:55:45.349201 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5880 22:55:45.355770 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5881 22:55:45.356338 == TX Byte 1 ==
5882 22:55:45.358631 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5883 22:55:45.365228 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5884 22:55:45.365714 ==
5885 22:55:45.368915 Dram Type= 6, Freq= 0, CH_1, rank 1
5886 22:55:45.371735 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5887 22:55:45.372304 ==
5888 22:55:45.372767
5889 22:55:45.373095
5890 22:55:45.375486 TX Vref Scan disable
5891 22:55:45.378363 == TX Byte 0 ==
5892 22:55:45.381703 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5893 22:55:45.385574 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5894 22:55:45.388546 == TX Byte 1 ==
5895 22:55:45.391667 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5896 22:55:45.395091 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5897 22:55:45.395609
5898 22:55:45.395958 [DATLAT]
5899 22:55:45.398338 Freq=933, CH1 RK1
5900 22:55:45.398881
5901 22:55:45.401383 DATLAT Default: 0xb
5902 22:55:45.401919 0, 0xFFFF, sum = 0
5903 22:55:45.404700 1, 0xFFFF, sum = 0
5904 22:55:45.405245 2, 0xFFFF, sum = 0
5905 22:55:45.408137 3, 0xFFFF, sum = 0
5906 22:55:45.408682 4, 0xFFFF, sum = 0
5907 22:55:45.411565 5, 0xFFFF, sum = 0
5908 22:55:45.412066 6, 0xFFFF, sum = 0
5909 22:55:45.414794 7, 0xFFFF, sum = 0
5910 22:55:45.415342 8, 0xFFFF, sum = 0
5911 22:55:45.417827 9, 0xFFFF, sum = 0
5912 22:55:45.418264 10, 0x0, sum = 1
5913 22:55:45.421447 11, 0x0, sum = 2
5914 22:55:45.421964 12, 0x0, sum = 3
5915 22:55:45.424686 13, 0x0, sum = 4
5916 22:55:45.425121 best_step = 11
5917 22:55:45.425599
5918 22:55:45.425972 ==
5919 22:55:45.427894 Dram Type= 6, Freq= 0, CH_1, rank 1
5920 22:55:45.430792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5921 22:55:45.434316 ==
5922 22:55:45.434846 RX Vref Scan: 0
5923 22:55:45.435187
5924 22:55:45.437878 RX Vref 0 -> 0, step: 1
5925 22:55:45.438305
5926 22:55:45.440658 RX Delay -53 -> 252, step: 4
5927 22:55:45.444112 iDelay=203, Bit 0, Center 102 (11 ~ 194) 184
5928 22:55:45.447240 iDelay=203, Bit 1, Center 94 (-1 ~ 190) 192
5929 22:55:45.454009 iDelay=203, Bit 2, Center 86 (-5 ~ 178) 184
5930 22:55:45.457854 iDelay=203, Bit 3, Center 96 (3 ~ 190) 188
5931 22:55:45.460556 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5932 22:55:45.463791 iDelay=203, Bit 5, Center 108 (15 ~ 202) 188
5933 22:55:45.466990 iDelay=203, Bit 6, Center 104 (15 ~ 194) 180
5934 22:55:45.471029 iDelay=203, Bit 7, Center 94 (3 ~ 186) 184
5935 22:55:45.477626 iDelay=203, Bit 8, Center 78 (-13 ~ 170) 184
5936 22:55:45.480407 iDelay=203, Bit 9, Center 82 (-9 ~ 174) 184
5937 22:55:45.484186 iDelay=203, Bit 10, Center 92 (-1 ~ 186) 188
5938 22:55:45.487377 iDelay=203, Bit 11, Center 84 (-9 ~ 178) 188
5939 22:55:45.490356 iDelay=203, Bit 12, Center 100 (11 ~ 190) 180
5940 22:55:45.496755 iDelay=203, Bit 13, Center 100 (11 ~ 190) 180
5941 22:55:45.500291 iDelay=203, Bit 14, Center 96 (7 ~ 186) 180
5942 22:55:45.503221 iDelay=203, Bit 15, Center 100 (7 ~ 194) 188
5943 22:55:45.503715 ==
5944 22:55:45.507735 Dram Type= 6, Freq= 0, CH_1, rank 1
5945 22:55:45.509922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5946 22:55:45.513208 ==
5947 22:55:45.513638 DQS Delay:
5948 22:55:45.513979 DQS0 = 0, DQS1 = 0
5949 22:55:45.517226 DQM Delay:
5950 22:55:45.517759 DQM0 = 97, DQM1 = 91
5951 22:55:45.520626 DQ Delay:
5952 22:55:45.523744 DQ0 =102, DQ1 =94, DQ2 =86, DQ3 =96
5953 22:55:45.526664 DQ4 =96, DQ5 =108, DQ6 =104, DQ7 =94
5954 22:55:45.530147 DQ8 =78, DQ9 =82, DQ10 =92, DQ11 =84
5955 22:55:45.533147 DQ12 =100, DQ13 =100, DQ14 =96, DQ15 =100
5956 22:55:45.533693
5957 22:55:45.534037
5958 22:55:45.539863 [DQSOSCAuto] RK1, (LSB)MR18= 0x1026, (MSB)MR19= 0x505, tDQSOscB0 = 409 ps tDQSOscB1 = 416 ps
5959 22:55:45.543438 CH1 RK1: MR19=505, MR18=1026
5960 22:55:45.550051 CH1_RK1: MR19=0x505, MR18=0x1026, DQSOSC=409, MR23=63, INC=64, DEC=43
5961 22:55:45.552439 [RxdqsGatingPostProcess] freq 933
5962 22:55:45.555885 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5963 22:55:45.559504 best DQS0 dly(2T, 0.5T) = (0, 10)
5964 22:55:45.562567 best DQS1 dly(2T, 0.5T) = (0, 10)
5965 22:55:45.565952 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5966 22:55:45.570044 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5967 22:55:45.572578 best DQS0 dly(2T, 0.5T) = (0, 10)
5968 22:55:45.576134 best DQS1 dly(2T, 0.5T) = (0, 10)
5969 22:55:45.579500 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5970 22:55:45.582520 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5971 22:55:45.585792 Pre-setting of DQS Precalculation
5972 22:55:45.592583 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5973 22:55:45.599007 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5974 22:55:45.606022 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5975 22:55:45.606554
5976 22:55:45.606895
5977 22:55:45.609367 [Calibration Summary] 1866 Mbps
5978 22:55:45.609899 CH 0, Rank 0
5979 22:55:45.612605 SW Impedance : PASS
5980 22:55:45.615396 DUTY Scan : NO K
5981 22:55:45.615929 ZQ Calibration : PASS
5982 22:55:45.618660 Jitter Meter : NO K
5983 22:55:45.622145 CBT Training : PASS
5984 22:55:45.622676 Write leveling : PASS
5985 22:55:45.625416 RX DQS gating : PASS
5986 22:55:45.625950 RX DQ/DQS(RDDQC) : PASS
5987 22:55:45.628623 TX DQ/DQS : PASS
5988 22:55:45.632178 RX DATLAT : PASS
5989 22:55:45.632708 RX DQ/DQS(Engine): PASS
5990 22:55:45.635430 TX OE : NO K
5991 22:55:45.635964 All Pass.
5992 22:55:45.636347
5993 22:55:45.638363 CH 0, Rank 1
5994 22:55:45.638894 SW Impedance : PASS
5995 22:55:45.641802 DUTY Scan : NO K
5996 22:55:45.645427 ZQ Calibration : PASS
5997 22:55:45.645960 Jitter Meter : NO K
5998 22:55:45.648400 CBT Training : PASS
5999 22:55:45.651621 Write leveling : PASS
6000 22:55:45.652084 RX DQS gating : PASS
6001 22:55:45.654630 RX DQ/DQS(RDDQC) : PASS
6002 22:55:45.658368 TX DQ/DQS : PASS
6003 22:55:45.658909 RX DATLAT : PASS
6004 22:55:45.661628 RX DQ/DQS(Engine): PASS
6005 22:55:45.664340 TX OE : NO K
6006 22:55:45.664772 All Pass.
6007 22:55:45.665111
6008 22:55:45.665425 CH 1, Rank 0
6009 22:55:45.668161 SW Impedance : PASS
6010 22:55:45.670998 DUTY Scan : NO K
6011 22:55:45.671428 ZQ Calibration : PASS
6012 22:55:45.675189 Jitter Meter : NO K
6013 22:55:45.677769 CBT Training : PASS
6014 22:55:45.678295 Write leveling : PASS
6015 22:55:45.681451 RX DQS gating : PASS
6016 22:55:45.684594 RX DQ/DQS(RDDQC) : PASS
6017 22:55:45.685122 TX DQ/DQS : PASS
6018 22:55:45.687978 RX DATLAT : PASS
6019 22:55:45.690832 RX DQ/DQS(Engine): PASS
6020 22:55:45.691259 TX OE : NO K
6021 22:55:45.694558 All Pass.
6022 22:55:45.694984
6023 22:55:45.695324 CH 1, Rank 1
6024 22:55:45.697480 SW Impedance : PASS
6025 22:55:45.698005 DUTY Scan : NO K
6026 22:55:45.700775 ZQ Calibration : PASS
6027 22:55:45.704631 Jitter Meter : NO K
6028 22:55:45.705158 CBT Training : PASS
6029 22:55:45.707263 Write leveling : PASS
6030 22:55:45.710873 RX DQS gating : PASS
6031 22:55:45.711398 RX DQ/DQS(RDDQC) : PASS
6032 22:55:45.714429 TX DQ/DQS : PASS
6033 22:55:45.714956 RX DATLAT : PASS
6034 22:55:45.717965 RX DQ/DQS(Engine): PASS
6035 22:55:45.720834 TX OE : NO K
6036 22:55:45.721357 All Pass.
6037 22:55:45.721703
6038 22:55:45.723881 DramC Write-DBI off
6039 22:55:45.727099 PER_BANK_REFRESH: Hybrid Mode
6040 22:55:45.727636 TX_TRACKING: ON
6041 22:55:45.736910 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6042 22:55:45.740477 [FAST_K] Save calibration result to emmc
6043 22:55:45.744024 dramc_set_vcore_voltage set vcore to 650000
6044 22:55:45.747304 Read voltage for 400, 6
6045 22:55:45.747738 Vio18 = 0
6046 22:55:45.748122 Vcore = 650000
6047 22:55:45.750270 Vdram = 0
6048 22:55:45.750796 Vddq = 0
6049 22:55:45.751144 Vmddr = 0
6050 22:55:45.756548 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6051 22:55:45.760321 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6052 22:55:45.763251 MEM_TYPE=3, freq_sel=20
6053 22:55:45.766287 sv_algorithm_assistance_LP4_800
6054 22:55:45.769637 ============ PULL DRAM RESETB DOWN ============
6055 22:55:45.773184 ========== PULL DRAM RESETB DOWN end =========
6056 22:55:45.779818 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6057 22:55:45.783482 ===================================
6058 22:55:45.786145 LPDDR4 DRAM CONFIGURATION
6059 22:55:45.789680 ===================================
6060 22:55:45.790110 EX_ROW_EN[0] = 0x0
6061 22:55:45.793069 EX_ROW_EN[1] = 0x0
6062 22:55:45.793498 LP4Y_EN = 0x0
6063 22:55:45.796119 WORK_FSP = 0x0
6064 22:55:45.796548 WL = 0x2
6065 22:55:45.799349 RL = 0x2
6066 22:55:45.799860 BL = 0x2
6067 22:55:45.803066 RPST = 0x0
6068 22:55:45.803586 RD_PRE = 0x0
6069 22:55:45.806495 WR_PRE = 0x1
6070 22:55:45.807013 WR_PST = 0x0
6071 22:55:45.809738 DBI_WR = 0x0
6072 22:55:45.810285 DBI_RD = 0x0
6073 22:55:45.812950 OTF = 0x1
6074 22:55:45.816317 ===================================
6075 22:55:45.819959 ===================================
6076 22:55:45.820550 ANA top config
6077 22:55:45.822764 ===================================
6078 22:55:45.826311 DLL_ASYNC_EN = 0
6079 22:55:45.829078 ALL_SLAVE_EN = 1
6080 22:55:45.832536 NEW_RANK_MODE = 1
6081 22:55:45.836067 DLL_IDLE_MODE = 1
6082 22:55:45.836629 LP45_APHY_COMB_EN = 1
6083 22:55:45.838816 TX_ODT_DIS = 1
6084 22:55:45.842347 NEW_8X_MODE = 1
6085 22:55:45.846135 ===================================
6086 22:55:45.849234 ===================================
6087 22:55:45.852266 data_rate = 800
6088 22:55:45.855254 CKR = 1
6089 22:55:45.855726 DQ_P2S_RATIO = 4
6090 22:55:45.859555 ===================================
6091 22:55:45.861823 CA_P2S_RATIO = 4
6092 22:55:45.865181 DQ_CA_OPEN = 0
6093 22:55:45.868701 DQ_SEMI_OPEN = 1
6094 22:55:45.872006 CA_SEMI_OPEN = 1
6095 22:55:45.875349 CA_FULL_RATE = 0
6096 22:55:45.878507 DQ_CKDIV4_EN = 0
6097 22:55:45.879082 CA_CKDIV4_EN = 1
6098 22:55:45.882318 CA_PREDIV_EN = 0
6099 22:55:45.885184 PH8_DLY = 0
6100 22:55:45.888513 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6101 22:55:45.891779 DQ_AAMCK_DIV = 0
6102 22:55:45.894864 CA_AAMCK_DIV = 0
6103 22:55:45.895338 CA_ADMCK_DIV = 4
6104 22:55:45.898442 DQ_TRACK_CA_EN = 0
6105 22:55:45.901243 CA_PICK = 800
6106 22:55:45.905203 CA_MCKIO = 400
6107 22:55:45.907906 MCKIO_SEMI = 400
6108 22:55:45.911109 PLL_FREQ = 3016
6109 22:55:45.914892 DQ_UI_PI_RATIO = 32
6110 22:55:45.917997 CA_UI_PI_RATIO = 32
6111 22:55:45.921448 ===================================
6112 22:55:45.924595 ===================================
6113 22:55:45.925171 memory_type:LPDDR4
6114 22:55:45.927622 GP_NUM : 10
6115 22:55:45.931141 SRAM_EN : 1
6116 22:55:45.931715 MD32_EN : 0
6117 22:55:45.934261 ===================================
6118 22:55:45.937933 [ANA_INIT] >>>>>>>>>>>>>>
6119 22:55:45.940977 <<<<<< [CONFIGURE PHASE]: ANA_TX
6120 22:55:45.944599 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6121 22:55:45.947454 ===================================
6122 22:55:45.950880 data_rate = 800,PCW = 0X7400
6123 22:55:45.954252 ===================================
6124 22:55:45.957498 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6125 22:55:45.960884 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6126 22:55:45.974204 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6127 22:55:45.977563 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6128 22:55:45.980260 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6129 22:55:45.983677 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6130 22:55:45.986879 [ANA_INIT] flow start
6131 22:55:45.990320 [ANA_INIT] PLL >>>>>>>>
6132 22:55:45.990792 [ANA_INIT] PLL <<<<<<<<
6133 22:55:45.993843 [ANA_INIT] MIDPI >>>>>>>>
6134 22:55:45.997462 [ANA_INIT] MIDPI <<<<<<<<
6135 22:55:45.998035 [ANA_INIT] DLL >>>>>>>>
6136 22:55:46.000605 [ANA_INIT] flow end
6137 22:55:46.003959 ============ LP4 DIFF to SE enter ============
6138 22:55:46.007018 ============ LP4 DIFF to SE exit ============
6139 22:55:46.010170 [ANA_INIT] <<<<<<<<<<<<<
6140 22:55:46.013897 [Flow] Enable top DCM control >>>>>
6141 22:55:46.017027 [Flow] Enable top DCM control <<<<<
6142 22:55:46.020287 Enable DLL master slave shuffle
6143 22:55:46.026645 ==============================================================
6144 22:55:46.027224 Gating Mode config
6145 22:55:46.033651 ==============================================================
6146 22:55:46.036492 Config description:
6147 22:55:46.045951 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6148 22:55:46.052777 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6149 22:55:46.055979 SELPH_MODE 0: By rank 1: By Phase
6150 22:55:46.062796 ==============================================================
6151 22:55:46.066084 GAT_TRACK_EN = 0
6152 22:55:46.066790 RX_GATING_MODE = 2
6153 22:55:46.069038 RX_GATING_TRACK_MODE = 2
6154 22:55:46.072347 SELPH_MODE = 1
6155 22:55:46.075736 PICG_EARLY_EN = 1
6156 22:55:46.079337 VALID_LAT_VALUE = 1
6157 22:55:46.085484 ==============================================================
6158 22:55:46.088752 Enter into Gating configuration >>>>
6159 22:55:46.092259 Exit from Gating configuration <<<<
6160 22:55:46.095408 Enter into DVFS_PRE_config >>>>>
6161 22:55:46.105588 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6162 22:55:46.108896 Exit from DVFS_PRE_config <<<<<
6163 22:55:46.112254 Enter into PICG configuration >>>>
6164 22:55:46.115800 Exit from PICG configuration <<<<
6165 22:55:46.118643 [RX_INPUT] configuration >>>>>
6166 22:55:46.122187 [RX_INPUT] configuration <<<<<
6167 22:55:46.124914 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6168 22:55:46.131991 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6169 22:55:46.138738 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6170 22:55:46.145165 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6171 22:55:46.151763 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6172 22:55:46.154783 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6173 22:55:46.161098 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6174 22:55:46.165101 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6175 22:55:46.168100 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6176 22:55:46.171380 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6177 22:55:46.177655 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6178 22:55:46.181084 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6179 22:55:46.184244 ===================================
6180 22:55:46.187880 LPDDR4 DRAM CONFIGURATION
6181 22:55:46.190759 ===================================
6182 22:55:46.191278 EX_ROW_EN[0] = 0x0
6183 22:55:46.194434 EX_ROW_EN[1] = 0x0
6184 22:55:46.194948 LP4Y_EN = 0x0
6185 22:55:46.197303 WORK_FSP = 0x0
6186 22:55:46.197723 WL = 0x2
6187 22:55:46.201488 RL = 0x2
6188 22:55:46.204176 BL = 0x2
6189 22:55:46.204694 RPST = 0x0
6190 22:55:46.207520 RD_PRE = 0x0
6191 22:55:46.208073 WR_PRE = 0x1
6192 22:55:46.210953 WR_PST = 0x0
6193 22:55:46.211467 DBI_WR = 0x0
6194 22:55:46.214283 DBI_RD = 0x0
6195 22:55:46.214795 OTF = 0x1
6196 22:55:46.217192 ===================================
6197 22:55:46.220359 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6198 22:55:46.227268 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6199 22:55:46.230289 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6200 22:55:46.234006 ===================================
6201 22:55:46.236849 LPDDR4 DRAM CONFIGURATION
6202 22:55:46.240653 ===================================
6203 22:55:46.241169 EX_ROW_EN[0] = 0x10
6204 22:55:46.243598 EX_ROW_EN[1] = 0x0
6205 22:55:46.246769 LP4Y_EN = 0x0
6206 22:55:46.247191 WORK_FSP = 0x0
6207 22:55:46.250335 WL = 0x2
6208 22:55:46.250907 RL = 0x2
6209 22:55:46.253508 BL = 0x2
6210 22:55:46.253927 RPST = 0x0
6211 22:55:46.256828 RD_PRE = 0x0
6212 22:55:46.257269 WR_PRE = 0x1
6213 22:55:46.259989 WR_PST = 0x0
6214 22:55:46.260455 DBI_WR = 0x0
6215 22:55:46.263606 DBI_RD = 0x0
6216 22:55:46.264185 OTF = 0x1
6217 22:55:46.266684 ===================================
6218 22:55:46.273044 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6219 22:55:46.277801 nWR fixed to 30
6220 22:55:46.280800 [ModeRegInit_LP4] CH0 RK0
6221 22:55:46.281270 [ModeRegInit_LP4] CH0 RK1
6222 22:55:46.284008 [ModeRegInit_LP4] CH1 RK0
6223 22:55:46.287219 [ModeRegInit_LP4] CH1 RK1
6224 22:55:46.287683 match AC timing 19
6225 22:55:46.294276 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6226 22:55:46.296972 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6227 22:55:46.300621 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6228 22:55:46.307065 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6229 22:55:46.310420 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6230 22:55:46.310992 ==
6231 22:55:46.313900 Dram Type= 6, Freq= 0, CH_0, rank 0
6232 22:55:46.317376 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6233 22:55:46.317950 ==
6234 22:55:46.324106 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6235 22:55:46.330242 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6236 22:55:46.333462 [CA 0] Center 36 (8~64) winsize 57
6237 22:55:46.336976 [CA 1] Center 36 (8~64) winsize 57
6238 22:55:46.340172 [CA 2] Center 36 (8~64) winsize 57
6239 22:55:46.343082 [CA 3] Center 36 (8~64) winsize 57
6240 22:55:46.347086 [CA 4] Center 36 (8~64) winsize 57
6241 22:55:46.349691 [CA 5] Center 36 (8~64) winsize 57
6242 22:55:46.350159
6243 22:55:46.352998 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6244 22:55:46.353571
6245 22:55:46.356338 [CATrainingPosCal] consider 1 rank data
6246 22:55:46.359626 u2DelayCellTimex100 = 270/100 ps
6247 22:55:46.362951 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6248 22:55:46.365936 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6249 22:55:46.369519 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6250 22:55:46.372869 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6251 22:55:46.376173 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6252 22:55:46.379343 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6253 22:55:46.379817
6254 22:55:46.386022 CA PerBit enable=1, Macro0, CA PI delay=36
6255 22:55:46.386607
6256 22:55:46.389032 [CBTSetCACLKResult] CA Dly = 36
6257 22:55:46.389501 CS Dly: 1 (0~32)
6258 22:55:46.389876 ==
6259 22:55:46.392250 Dram Type= 6, Freq= 0, CH_0, rank 1
6260 22:55:46.395634 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6261 22:55:46.396107 ==
6262 22:55:46.402688 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6263 22:55:46.409177 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6264 22:55:46.412421 [CA 0] Center 36 (8~64) winsize 57
6265 22:55:46.415557 [CA 1] Center 36 (8~64) winsize 57
6266 22:55:46.419125 [CA 2] Center 36 (8~64) winsize 57
6267 22:55:46.422063 [CA 3] Center 36 (8~64) winsize 57
6268 22:55:46.426374 [CA 4] Center 36 (8~64) winsize 57
6269 22:55:46.428408 [CA 5] Center 36 (8~64) winsize 57
6270 22:55:46.428876
6271 22:55:46.432356 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6272 22:55:46.432925
6273 22:55:46.435571 [CATrainingPosCal] consider 2 rank data
6274 22:55:46.439466 u2DelayCellTimex100 = 270/100 ps
6275 22:55:46.442181 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6276 22:55:46.445434 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6277 22:55:46.448287 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6278 22:55:46.452198 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6279 22:55:46.455662 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6280 22:55:46.458431 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6281 22:55:46.458915
6282 22:55:46.465170 CA PerBit enable=1, Macro0, CA PI delay=36
6283 22:55:46.465678
6284 22:55:46.466196 [CBTSetCACLKResult] CA Dly = 36
6285 22:55:46.468531 CS Dly: 1 (0~32)
6286 22:55:46.469015
6287 22:55:46.471755 ----->DramcWriteLeveling(PI) begin...
6288 22:55:46.472363 ==
6289 22:55:46.475168 Dram Type= 6, Freq= 0, CH_0, rank 0
6290 22:55:46.478516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6291 22:55:46.479082 ==
6292 22:55:46.481797 Write leveling (Byte 0): 40 => 8
6293 22:55:46.484546 Write leveling (Byte 1): 40 => 8
6294 22:55:46.488495 DramcWriteLeveling(PI) end<-----
6295 22:55:46.489060
6296 22:55:46.489430 ==
6297 22:55:46.491224 Dram Type= 6, Freq= 0, CH_0, rank 0
6298 22:55:46.494322 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6299 22:55:46.497787 ==
6300 22:55:46.498254 [Gating] SW mode calibration
6301 22:55:46.507821 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6302 22:55:46.511188 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6303 22:55:46.514439 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6304 22:55:46.521393 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6305 22:55:46.524203 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6306 22:55:46.527564 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6307 22:55:46.533780 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6308 22:55:46.537400 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6309 22:55:46.540882 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6310 22:55:46.547661 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6311 22:55:46.550460 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6312 22:55:46.553876 Total UI for P1: 0, mck2ui 16
6313 22:55:46.557508 best dqsien dly found for B0: ( 0, 14, 24)
6314 22:55:46.560296 Total UI for P1: 0, mck2ui 16
6315 22:55:46.563952 best dqsien dly found for B1: ( 0, 14, 24)
6316 22:55:46.567204 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6317 22:55:46.570676 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6318 22:55:46.571265
6319 22:55:46.573898 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6320 22:55:46.580205 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6321 22:55:46.580763 [Gating] SW calibration Done
6322 22:55:46.581137 ==
6323 22:55:46.583232 Dram Type= 6, Freq= 0, CH_0, rank 0
6324 22:55:46.589786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6325 22:55:46.590323 ==
6326 22:55:46.590696 RX Vref Scan: 0
6327 22:55:46.591037
6328 22:55:46.593867 RX Vref 0 -> 0, step: 1
6329 22:55:46.594431
6330 22:55:46.596409 RX Delay -410 -> 252, step: 16
6331 22:55:46.600075 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6332 22:55:46.603493 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6333 22:55:46.609552 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6334 22:55:46.613136 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6335 22:55:46.616020 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6336 22:55:46.620294 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6337 22:55:46.626772 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6338 22:55:46.629624 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6339 22:55:46.632597 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6340 22:55:46.639126 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6341 22:55:46.642748 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6342 22:55:46.646002 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6343 22:55:46.649646 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6344 22:55:46.656309 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6345 22:55:46.659032 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6346 22:55:46.662490 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6347 22:55:46.662939 ==
6348 22:55:46.665294 Dram Type= 6, Freq= 0, CH_0, rank 0
6349 22:55:46.671835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6350 22:55:46.672299 ==
6351 22:55:46.672628 DQS Delay:
6352 22:55:46.675130 DQS0 = 35, DQS1 = 51
6353 22:55:46.675539 DQM Delay:
6354 22:55:46.675861 DQM0 = 5, DQM1 = 10
6355 22:55:46.679234 DQ Delay:
6356 22:55:46.682325 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6357 22:55:46.682832 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6358 22:55:46.685297 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6359 22:55:46.688897 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6360 22:55:46.689411
6361 22:55:46.689739
6362 22:55:46.691975 ==
6363 22:55:46.695089 Dram Type= 6, Freq= 0, CH_0, rank 0
6364 22:55:46.698555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6365 22:55:46.699065 ==
6366 22:55:46.699395
6367 22:55:46.699698
6368 22:55:46.702050 TX Vref Scan disable
6369 22:55:46.702605 == TX Byte 0 ==
6370 22:55:46.705021 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6371 22:55:46.711956 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6372 22:55:46.712495 == TX Byte 1 ==
6373 22:55:46.715051 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6374 22:55:46.721610 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6375 22:55:46.722118 ==
6376 22:55:46.724736 Dram Type= 6, Freq= 0, CH_0, rank 0
6377 22:55:46.727954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6378 22:55:46.728409 ==
6379 22:55:46.728737
6380 22:55:46.729034
6381 22:55:46.731658 TX Vref Scan disable
6382 22:55:46.732235 == TX Byte 0 ==
6383 22:55:46.734755 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6384 22:55:46.741358 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6385 22:55:46.741883 == TX Byte 1 ==
6386 22:55:46.744341 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6387 22:55:46.751137 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6388 22:55:46.751641
6389 22:55:46.751965 [DATLAT]
6390 22:55:46.754831 Freq=400, CH0 RK0
6391 22:55:46.755338
6392 22:55:46.755663 DATLAT Default: 0xf
6393 22:55:46.757691 0, 0xFFFF, sum = 0
6394 22:55:46.758145 1, 0xFFFF, sum = 0
6395 22:55:46.761376 2, 0xFFFF, sum = 0
6396 22:55:46.761892 3, 0xFFFF, sum = 0
6397 22:55:46.764405 4, 0xFFFF, sum = 0
6398 22:55:46.764822 5, 0xFFFF, sum = 0
6399 22:55:46.767937 6, 0xFFFF, sum = 0
6400 22:55:46.768421 7, 0xFFFF, sum = 0
6401 22:55:46.771518 8, 0xFFFF, sum = 0
6402 22:55:46.772071 9, 0xFFFF, sum = 0
6403 22:55:46.774805 10, 0xFFFF, sum = 0
6404 22:55:46.775324 11, 0xFFFF, sum = 0
6405 22:55:46.778106 12, 0xFFFF, sum = 0
6406 22:55:46.778622 13, 0x0, sum = 1
6407 22:55:46.781245 14, 0x0, sum = 2
6408 22:55:46.781760 15, 0x0, sum = 3
6409 22:55:46.784247 16, 0x0, sum = 4
6410 22:55:46.784761 best_step = 14
6411 22:55:46.785087
6412 22:55:46.785385 ==
6413 22:55:46.787687 Dram Type= 6, Freq= 0, CH_0, rank 0
6414 22:55:46.794541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6415 22:55:46.795051 ==
6416 22:55:46.795380 RX Vref Scan: 1
6417 22:55:46.795684
6418 22:55:46.797975 RX Vref 0 -> 0, step: 1
6419 22:55:46.798484
6420 22:55:46.800606 RX Delay -343 -> 252, step: 8
6421 22:55:46.801015
6422 22:55:46.804133 Set Vref, RX VrefLevel [Byte0]: 53
6423 22:55:46.807581 [Byte1]: 49
6424 22:55:46.810571
6425 22:55:46.811039 Final RX Vref Byte 0 = 53 to rank0
6426 22:55:46.814515 Final RX Vref Byte 1 = 49 to rank0
6427 22:55:46.817556 Final RX Vref Byte 0 = 53 to rank1
6428 22:55:46.820714 Final RX Vref Byte 1 = 49 to rank1==
6429 22:55:46.824332 Dram Type= 6, Freq= 0, CH_0, rank 0
6430 22:55:46.830640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6431 22:55:46.831156 ==
6432 22:55:46.831491 DQS Delay:
6433 22:55:46.833805 DQS0 = 44, DQS1 = 60
6434 22:55:46.834319 DQM Delay:
6435 22:55:46.834650 DQM0 = 10, DQM1 = 18
6436 22:55:46.836737 DQ Delay:
6437 22:55:46.840234 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =4
6438 22:55:46.843788 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =12
6439 22:55:46.844361 DQ8 =8, DQ9 =0, DQ10 =20, DQ11 =12
6440 22:55:46.850094 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =28
6441 22:55:46.850606
6442 22:55:46.850959
6443 22:55:46.856840 [DQSOSCAuto] RK0, (LSB)MR18= 0x9386, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps
6444 22:55:46.860140 CH0 RK0: MR19=C0C, MR18=9386
6445 22:55:46.866745 CH0_RK0: MR19=0xC0C, MR18=0x9386, DQSOSC=391, MR23=63, INC=386, DEC=257
6446 22:55:46.867285 ==
6447 22:55:46.870347 Dram Type= 6, Freq= 0, CH_0, rank 1
6448 22:55:46.873760 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6449 22:55:46.874284 ==
6450 22:55:46.876893 [Gating] SW mode calibration
6451 22:55:46.883390 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6452 22:55:46.889588 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6453 22:55:46.893097 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6454 22:55:46.896315 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6455 22:55:46.903350 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6456 22:55:46.906352 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6457 22:55:46.909566 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6458 22:55:46.916391 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6459 22:55:46.919527 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6460 22:55:46.923358 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6461 22:55:46.929232 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6462 22:55:46.932591 Total UI for P1: 0, mck2ui 16
6463 22:55:46.936108 best dqsien dly found for B0: ( 0, 14, 24)
6464 22:55:46.938994 Total UI for P1: 0, mck2ui 16
6465 22:55:46.942363 best dqsien dly found for B1: ( 0, 14, 24)
6466 22:55:46.945746 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6467 22:55:46.948624 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6468 22:55:46.949071
6469 22:55:46.952117 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6470 22:55:46.955620 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6471 22:55:46.958539 [Gating] SW calibration Done
6472 22:55:46.958961 ==
6473 22:55:46.962070 Dram Type= 6, Freq= 0, CH_0, rank 1
6474 22:55:46.965581 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6475 22:55:46.966099 ==
6476 22:55:46.968849 RX Vref Scan: 0
6477 22:55:46.969268
6478 22:55:46.971678 RX Vref 0 -> 0, step: 1
6479 22:55:46.972122
6480 22:55:46.975338 RX Delay -410 -> 252, step: 16
6481 22:55:46.978372 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6482 22:55:46.982199 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6483 22:55:46.984955 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6484 22:55:46.991389 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6485 22:55:46.995608 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6486 22:55:46.998370 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6487 22:55:47.001259 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6488 22:55:47.008172 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6489 22:55:47.010982 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6490 22:55:47.014470 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6491 22:55:47.020811 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6492 22:55:47.024252 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6493 22:55:47.027851 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6494 22:55:47.031027 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6495 22:55:47.037327 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6496 22:55:47.040691 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6497 22:55:47.041105 ==
6498 22:55:47.043944 Dram Type= 6, Freq= 0, CH_0, rank 1
6499 22:55:47.047339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6500 22:55:47.047721 ==
6501 22:55:47.050766 DQS Delay:
6502 22:55:47.051180 DQS0 = 35, DQS1 = 59
6503 22:55:47.053799 DQM Delay:
6504 22:55:47.054183 DQM0 = 6, DQM1 = 17
6505 22:55:47.054504 DQ Delay:
6506 22:55:47.056892 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6507 22:55:47.060326 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6508 22:55:47.063666 DQ8 =8, DQ9 =0, DQ10 =24, DQ11 =8
6509 22:55:47.067384 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6510 22:55:47.067844
6511 22:55:47.068242
6512 22:55:47.068598 ==
6513 22:55:47.070225 Dram Type= 6, Freq= 0, CH_0, rank 1
6514 22:55:47.076779 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6515 22:55:47.077315 ==
6516 22:55:47.077796
6517 22:55:47.078256
6518 22:55:47.078634 TX Vref Scan disable
6519 22:55:47.080123 == TX Byte 0 ==
6520 22:55:47.083986 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6521 22:55:47.086806 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6522 22:55:47.089862 == TX Byte 1 ==
6523 22:55:47.093187 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6524 22:55:47.096532 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6525 22:55:47.096980 ==
6526 22:55:47.100059 Dram Type= 6, Freq= 0, CH_0, rank 1
6527 22:55:47.106174 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6528 22:55:47.106690 ==
6529 22:55:47.107163
6530 22:55:47.107484
6531 22:55:47.109591 TX Vref Scan disable
6532 22:55:47.109960 == TX Byte 0 ==
6533 22:55:47.112791 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6534 22:55:47.116345 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6535 22:55:47.119450 == TX Byte 1 ==
6536 22:55:47.123309 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6537 22:55:47.126330 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6538 22:55:47.129861
6539 22:55:47.130443 [DATLAT]
6540 22:55:47.130988 Freq=400, CH0 RK1
6541 22:55:47.131377
6542 22:55:47.132908 DATLAT Default: 0xe
6543 22:55:47.133402 0, 0xFFFF, sum = 0
6544 22:55:47.135958 1, 0xFFFF, sum = 0
6545 22:55:47.136494 2, 0xFFFF, sum = 0
6546 22:55:47.139567 3, 0xFFFF, sum = 0
6547 22:55:47.140222 4, 0xFFFF, sum = 0
6548 22:55:47.142753 5, 0xFFFF, sum = 0
6549 22:55:47.146074 6, 0xFFFF, sum = 0
6550 22:55:47.146630 7, 0xFFFF, sum = 0
6551 22:55:47.149067 8, 0xFFFF, sum = 0
6552 22:55:47.149611 9, 0xFFFF, sum = 0
6553 22:55:47.152873 10, 0xFFFF, sum = 0
6554 22:55:47.153296 11, 0xFFFF, sum = 0
6555 22:55:47.155813 12, 0xFFFF, sum = 0
6556 22:55:47.155899 13, 0x0, sum = 1
6557 22:55:47.158934 14, 0x0, sum = 2
6558 22:55:47.159016 15, 0x0, sum = 3
6559 22:55:47.162894 16, 0x0, sum = 4
6560 22:55:47.162979 best_step = 14
6561 22:55:47.163043
6562 22:55:47.163104 ==
6563 22:55:47.165761 Dram Type= 6, Freq= 0, CH_0, rank 1
6564 22:55:47.169209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6565 22:55:47.172221 ==
6566 22:55:47.172303 RX Vref Scan: 0
6567 22:55:47.172368
6568 22:55:47.175236 RX Vref 0 -> 0, step: 1
6569 22:55:47.175319
6570 22:55:47.179007 RX Delay -359 -> 252, step: 8
6571 22:55:47.185159 iDelay=209, Bit 0, Center -36 (-271 ~ 200) 472
6572 22:55:47.188949 iDelay=209, Bit 1, Center -32 (-271 ~ 208) 480
6573 22:55:47.192074 iDelay=209, Bit 2, Center -40 (-279 ~ 200) 480
6574 22:55:47.195105 iDelay=209, Bit 3, Center -36 (-271 ~ 200) 472
6575 22:55:47.202009 iDelay=209, Bit 4, Center -32 (-271 ~ 208) 480
6576 22:55:47.205426 iDelay=209, Bit 5, Center -44 (-279 ~ 192) 472
6577 22:55:47.208154 iDelay=209, Bit 6, Center -28 (-263 ~ 208) 472
6578 22:55:47.211565 iDelay=209, Bit 7, Center -28 (-263 ~ 208) 472
6579 22:55:47.217860 iDelay=209, Bit 8, Center -52 (-295 ~ 192) 488
6580 22:55:47.221656 iDelay=209, Bit 9, Center -60 (-303 ~ 184) 488
6581 22:55:47.224538 iDelay=209, Bit 10, Center -44 (-287 ~ 200) 488
6582 22:55:47.227998 iDelay=209, Bit 11, Center -52 (-295 ~ 192) 488
6583 22:55:47.234668 iDelay=209, Bit 12, Center -44 (-287 ~ 200) 488
6584 22:55:47.238079 iDelay=209, Bit 13, Center -40 (-279 ~ 200) 480
6585 22:55:47.241296 iDelay=209, Bit 14, Center -32 (-271 ~ 208) 480
6586 22:55:47.247425 iDelay=209, Bit 15, Center -40 (-279 ~ 200) 480
6587 22:55:47.247508 ==
6588 22:55:47.250690 Dram Type= 6, Freq= 0, CH_0, rank 1
6589 22:55:47.253979 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6590 22:55:47.254054 ==
6591 22:55:47.254116 DQS Delay:
6592 22:55:47.257438 DQS0 = 44, DQS1 = 60
6593 22:55:47.257507 DQM Delay:
6594 22:55:47.260816 DQM0 = 9, DQM1 = 14
6595 22:55:47.260901 DQ Delay:
6596 22:55:47.263840 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =8
6597 22:55:47.267319 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6598 22:55:47.270494 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6599 22:55:47.273664 DQ12 =16, DQ13 =20, DQ14 =28, DQ15 =20
6600 22:55:47.273745
6601 22:55:47.273810
6602 22:55:47.280372 [DQSOSCAuto] RK1, (LSB)MR18= 0x8f88, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 391 ps
6603 22:55:47.283955 CH0 RK1: MR19=C0C, MR18=8F88
6604 22:55:47.290079 CH0_RK1: MR19=0xC0C, MR18=0x8F88, DQSOSC=391, MR23=63, INC=386, DEC=257
6605 22:55:47.293372 [RxdqsGatingPostProcess] freq 400
6606 22:55:47.299886 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6607 22:55:47.303281 best DQS0 dly(2T, 0.5T) = (0, 10)
6608 22:55:47.306515 best DQS1 dly(2T, 0.5T) = (0, 10)
6609 22:55:47.309823 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6610 22:55:47.313244 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6611 22:55:47.313326 best DQS0 dly(2T, 0.5T) = (0, 10)
6612 22:55:47.316751 best DQS1 dly(2T, 0.5T) = (0, 10)
6613 22:55:47.319998 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6614 22:55:47.322862 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6615 22:55:47.326403 Pre-setting of DQS Precalculation
6616 22:55:47.333150 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6617 22:55:47.333232 ==
6618 22:55:47.336169 Dram Type= 6, Freq= 0, CH_1, rank 0
6619 22:55:47.339539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6620 22:55:47.339621 ==
6621 22:55:47.346254 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6622 22:55:47.353038 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6623 22:55:47.356368 [CA 0] Center 36 (8~64) winsize 57
6624 22:55:47.359128 [CA 1] Center 36 (8~64) winsize 57
6625 22:55:47.359212 [CA 2] Center 36 (8~64) winsize 57
6626 22:55:47.362774 [CA 3] Center 36 (8~64) winsize 57
6627 22:55:47.365869 [CA 4] Center 36 (8~64) winsize 57
6628 22:55:47.369423 [CA 5] Center 36 (8~64) winsize 57
6629 22:55:47.369523
6630 22:55:47.372432 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6631 22:55:47.376096
6632 22:55:47.379253 [CATrainingPosCal] consider 1 rank data
6633 22:55:47.379338 u2DelayCellTimex100 = 270/100 ps
6634 22:55:47.385685 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6635 22:55:47.389099 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6636 22:55:47.392634 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6637 22:55:47.395562 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6638 22:55:47.399317 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6639 22:55:47.401862 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6640 22:55:47.401948
6641 22:55:47.405523 CA PerBit enable=1, Macro0, CA PI delay=36
6642 22:55:47.405609
6643 22:55:47.408506 [CBTSetCACLKResult] CA Dly = 36
6644 22:55:47.412017 CS Dly: 1 (0~32)
6645 22:55:47.412113 ==
6646 22:55:47.415098 Dram Type= 6, Freq= 0, CH_1, rank 1
6647 22:55:47.418925 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6648 22:55:47.419011 ==
6649 22:55:47.424773 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6650 22:55:47.431704 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6651 22:55:47.435141 [CA 0] Center 36 (8~64) winsize 57
6652 22:55:47.435230 [CA 1] Center 36 (8~64) winsize 57
6653 22:55:47.438263 [CA 2] Center 36 (8~64) winsize 57
6654 22:55:47.441992 [CA 3] Center 36 (8~64) winsize 57
6655 22:55:47.444795 [CA 4] Center 36 (8~64) winsize 57
6656 22:55:47.448253 [CA 5] Center 36 (8~64) winsize 57
6657 22:55:47.448338
6658 22:55:47.451559 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6659 22:55:47.451644
6660 22:55:47.455108 [CATrainingPosCal] consider 2 rank data
6661 22:55:47.458444 u2DelayCellTimex100 = 270/100 ps
6662 22:55:47.461637 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6663 22:55:47.467865 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6664 22:55:47.471259 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6665 22:55:47.474383 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6666 22:55:47.477740 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6667 22:55:47.481313 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6668 22:55:47.481399
6669 22:55:47.484306 CA PerBit enable=1, Macro0, CA PI delay=36
6670 22:55:47.484392
6671 22:55:47.487938 [CBTSetCACLKResult] CA Dly = 36
6672 22:55:47.491133 CS Dly: 1 (0~32)
6673 22:55:47.491218
6674 22:55:47.494358 ----->DramcWriteLeveling(PI) begin...
6675 22:55:47.494444 ==
6676 22:55:47.497998 Dram Type= 6, Freq= 0, CH_1, rank 0
6677 22:55:47.501013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6678 22:55:47.501098 ==
6679 22:55:47.503968 Write leveling (Byte 0): 40 => 8
6680 22:55:47.507691 Write leveling (Byte 1): 40 => 8
6681 22:55:47.510800 DramcWriteLeveling(PI) end<-----
6682 22:55:47.510885
6683 22:55:47.510988 ==
6684 22:55:47.514376 Dram Type= 6, Freq= 0, CH_1, rank 0
6685 22:55:47.517906 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6686 22:55:47.517992 ==
6687 22:55:47.520612 [Gating] SW mode calibration
6688 22:55:47.527182 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6689 22:55:47.534025 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6690 22:55:47.537154 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6691 22:55:47.540314 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6692 22:55:47.547170 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6693 22:55:47.550040 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6694 22:55:47.553691 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6695 22:55:47.560018 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6696 22:55:47.563601 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6697 22:55:47.566592 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6698 22:55:47.573186 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6699 22:55:47.576526 Total UI for P1: 0, mck2ui 16
6700 22:55:47.579684 best dqsien dly found for B0: ( 0, 14, 24)
6701 22:55:47.583091 Total UI for P1: 0, mck2ui 16
6702 22:55:47.586820 best dqsien dly found for B1: ( 0, 14, 24)
6703 22:55:47.589809 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6704 22:55:47.592872 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6705 22:55:47.592957
6706 22:55:47.596214 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6707 22:55:47.599566 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6708 22:55:47.603311 [Gating] SW calibration Done
6709 22:55:47.603396 ==
6710 22:55:47.606124 Dram Type= 6, Freq= 0, CH_1, rank 0
6711 22:55:47.609538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6712 22:55:47.612840 ==
6713 22:55:47.612923 RX Vref Scan: 0
6714 22:55:47.612990
6715 22:55:47.616311 RX Vref 0 -> 0, step: 1
6716 22:55:47.616394
6717 22:55:47.619380 RX Delay -410 -> 252, step: 16
6718 22:55:47.622560 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6719 22:55:47.625690 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6720 22:55:47.629049 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6721 22:55:47.635628 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6722 22:55:47.639507 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6723 22:55:47.642519 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6724 22:55:47.646209 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6725 22:55:47.652453 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6726 22:55:47.655703 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6727 22:55:47.658784 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6728 22:55:47.662514 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6729 22:55:47.668762 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6730 22:55:47.672444 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6731 22:55:47.675216 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6732 22:55:47.682171 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6733 22:55:47.685776 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6734 22:55:47.685860 ==
6735 22:55:47.688606 Dram Type= 6, Freq= 0, CH_1, rank 0
6736 22:55:47.692255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6737 22:55:47.692339 ==
6738 22:55:47.695094 DQS Delay:
6739 22:55:47.695177 DQS0 = 35, DQS1 = 51
6740 22:55:47.695243 DQM Delay:
6741 22:55:47.698438 DQM0 = 6, DQM1 = 13
6742 22:55:47.698524 DQ Delay:
6743 22:55:47.701671 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6744 22:55:47.705149 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6745 22:55:47.708523 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6746 22:55:47.711937 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =16
6747 22:55:47.712020
6748 22:55:47.712092
6749 22:55:47.712154 ==
6750 22:55:47.714814 Dram Type= 6, Freq= 0, CH_1, rank 0
6751 22:55:47.718400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6752 22:55:47.721409 ==
6753 22:55:47.721492
6754 22:55:47.721558
6755 22:55:47.721618 TX Vref Scan disable
6756 22:55:47.724804 == TX Byte 0 ==
6757 22:55:47.728178 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6758 22:55:47.731153 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6759 22:55:47.734811 == TX Byte 1 ==
6760 22:55:47.738112 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6761 22:55:47.741090 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6762 22:55:47.741173 ==
6763 22:55:47.744510 Dram Type= 6, Freq= 0, CH_1, rank 0
6764 22:55:47.750914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6765 22:55:47.750998 ==
6766 22:55:47.751064
6767 22:55:47.751124
6768 22:55:47.751182 TX Vref Scan disable
6769 22:55:47.754682 == TX Byte 0 ==
6770 22:55:47.758020 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6771 22:55:47.761205 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6772 22:55:47.764318 == TX Byte 1 ==
6773 22:55:47.767395 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6774 22:55:47.771366 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6775 22:55:47.771450
6776 22:55:47.774210 [DATLAT]
6777 22:55:47.774293 Freq=400, CH1 RK0
6778 22:55:47.774359
6779 22:55:47.777330 DATLAT Default: 0xf
6780 22:55:47.777413 0, 0xFFFF, sum = 0
6781 22:55:47.780554 1, 0xFFFF, sum = 0
6782 22:55:47.780639 2, 0xFFFF, sum = 0
6783 22:55:47.783832 3, 0xFFFF, sum = 0
6784 22:55:47.783917 4, 0xFFFF, sum = 0
6785 22:55:47.787558 5, 0xFFFF, sum = 0
6786 22:55:47.791162 6, 0xFFFF, sum = 0
6787 22:55:47.791246 7, 0xFFFF, sum = 0
6788 22:55:47.793677 8, 0xFFFF, sum = 0
6789 22:55:47.793761 9, 0xFFFF, sum = 0
6790 22:55:47.797011 10, 0xFFFF, sum = 0
6791 22:55:47.797096 11, 0xFFFF, sum = 0
6792 22:55:47.800236 12, 0xFFFF, sum = 0
6793 22:55:47.800320 13, 0x0, sum = 1
6794 22:55:47.804184 14, 0x0, sum = 2
6795 22:55:47.804267 15, 0x0, sum = 3
6796 22:55:47.807163 16, 0x0, sum = 4
6797 22:55:47.807247 best_step = 14
6798 22:55:47.807313
6799 22:55:47.807413 ==
6800 22:55:47.810050 Dram Type= 6, Freq= 0, CH_1, rank 0
6801 22:55:47.813927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6802 22:55:47.817011 ==
6803 22:55:47.817095 RX Vref Scan: 1
6804 22:55:47.817161
6805 22:55:47.820365 RX Vref 0 -> 0, step: 1
6806 22:55:47.820448
6807 22:55:47.823438 RX Delay -343 -> 252, step: 8
6808 22:55:47.823520
6809 22:55:47.826750 Set Vref, RX VrefLevel [Byte0]: 50
6810 22:55:47.830724 [Byte1]: 49
6811 22:55:47.830808
6812 22:55:47.833134 Final RX Vref Byte 0 = 50 to rank0
6813 22:55:47.836443 Final RX Vref Byte 1 = 49 to rank0
6814 22:55:47.839838 Final RX Vref Byte 0 = 50 to rank1
6815 22:55:47.843403 Final RX Vref Byte 1 = 49 to rank1==
6816 22:55:47.846542 Dram Type= 6, Freq= 0, CH_1, rank 0
6817 22:55:47.849793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6818 22:55:47.849877 ==
6819 22:55:47.853298 DQS Delay:
6820 22:55:47.853384 DQS0 = 44, DQS1 = 56
6821 22:55:47.856785 DQM Delay:
6822 22:55:47.856868 DQM0 = 11, DQM1 = 13
6823 22:55:47.856935 DQ Delay:
6824 22:55:47.859717 DQ0 =20, DQ1 =4, DQ2 =0, DQ3 =12
6825 22:55:47.862980 DQ4 =8, DQ5 =20, DQ6 =24, DQ7 =4
6826 22:55:47.866425 DQ8 =0, DQ9 =4, DQ10 =12, DQ11 =4
6827 22:55:47.869465 DQ12 =24, DQ13 =24, DQ14 =20, DQ15 =20
6828 22:55:47.869548
6829 22:55:47.869614
6830 22:55:47.879513 [DQSOSCAuto] RK0, (LSB)MR18= 0x6b91, (MSB)MR19= 0xc0c, tDQSOscB0 = 391 ps tDQSOscB1 = 396 ps
6831 22:55:47.882670 CH1 RK0: MR19=C0C, MR18=6B91
6832 22:55:47.889333 CH1_RK0: MR19=0xC0C, MR18=0x6B91, DQSOSC=391, MR23=63, INC=386, DEC=257
6833 22:55:47.889417 ==
6834 22:55:47.892455 Dram Type= 6, Freq= 0, CH_1, rank 1
6835 22:55:47.895931 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6836 22:55:47.896015 ==
6837 22:55:47.899330 [Gating] SW mode calibration
6838 22:55:47.905668 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6839 22:55:47.909217 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6840 22:55:47.915649 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6841 22:55:47.918972 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6842 22:55:47.925401 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6843 22:55:47.929105 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6844 22:55:47.931944 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6845 22:55:47.938815 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6846 22:55:47.942626 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6847 22:55:47.945540 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6848 22:55:47.951885 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6849 22:55:47.951968 Total UI for P1: 0, mck2ui 16
6850 22:55:47.955154 best dqsien dly found for B0: ( 0, 14, 24)
6851 22:55:47.958728 Total UI for P1: 0, mck2ui 16
6852 22:55:47.961826 best dqsien dly found for B1: ( 0, 14, 24)
6853 22:55:47.968154 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6854 22:55:47.971949 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6855 22:55:47.972038
6856 22:55:47.975290 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6857 22:55:47.978116 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6858 22:55:47.981716 [Gating] SW calibration Done
6859 22:55:47.981800 ==
6860 22:55:47.985277 Dram Type= 6, Freq= 0, CH_1, rank 1
6861 22:55:47.988214 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6862 22:55:47.988297 ==
6863 22:55:47.991732 RX Vref Scan: 0
6864 22:55:47.991817
6865 22:55:47.991883 RX Vref 0 -> 0, step: 1
6866 22:55:47.991946
6867 22:55:47.994780 RX Delay -410 -> 252, step: 16
6868 22:55:48.001177 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6869 22:55:48.004475 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6870 22:55:48.008180 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6871 22:55:48.011101 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6872 22:55:48.017637 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6873 22:55:48.020924 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6874 22:55:48.024335 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6875 22:55:48.027385 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6876 22:55:48.034165 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6877 22:55:48.038001 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6878 22:55:48.040707 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6879 22:55:48.044424 iDelay=230, Bit 11, Center -43 (-282 ~ 197) 480
6880 22:55:48.051256 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6881 22:55:48.054158 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6882 22:55:48.057078 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6883 22:55:48.063913 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6884 22:55:48.063996 ==
6885 22:55:48.067209 Dram Type= 6, Freq= 0, CH_1, rank 1
6886 22:55:48.070427 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6887 22:55:48.070526 ==
6888 22:55:48.070593 DQS Delay:
6889 22:55:48.073560 DQS0 = 43, DQS1 = 51
6890 22:55:48.073643 DQM Delay:
6891 22:55:48.077124 DQM0 = 9, DQM1 = 14
6892 22:55:48.077208 DQ Delay:
6893 22:55:48.080251 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6894 22:55:48.083531 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6895 22:55:48.087284 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6896 22:55:48.090415 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6897 22:55:48.090498
6898 22:55:48.090564
6899 22:55:48.090626 ==
6900 22:55:48.093646 Dram Type= 6, Freq= 0, CH_1, rank 1
6901 22:55:48.096911 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6902 22:55:48.096995 ==
6903 22:55:48.097062
6904 22:55:48.097125
6905 22:55:48.100295 TX Vref Scan disable
6906 22:55:48.100379 == TX Byte 0 ==
6907 22:55:48.107026 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6908 22:55:48.110226 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6909 22:55:48.110310 == TX Byte 1 ==
6910 22:55:48.116460 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6911 22:55:48.120107 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6912 22:55:48.120190 ==
6913 22:55:48.123310 Dram Type= 6, Freq= 0, CH_1, rank 1
6914 22:55:48.126372 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6915 22:55:48.126455 ==
6916 22:55:48.126522
6917 22:55:48.126581
6918 22:55:48.129547 TX Vref Scan disable
6919 22:55:48.133230 == TX Byte 0 ==
6920 22:55:48.136657 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6921 22:55:48.139751 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6922 22:55:48.143135 == TX Byte 1 ==
6923 22:55:48.146424 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6924 22:55:48.149640 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6925 22:55:48.149723
6926 22:55:48.149790 [DATLAT]
6927 22:55:48.153063 Freq=400, CH1 RK1
6928 22:55:48.153147
6929 22:55:48.153213 DATLAT Default: 0xe
6930 22:55:48.155919 0, 0xFFFF, sum = 0
6931 22:55:48.159607 1, 0xFFFF, sum = 0
6932 22:55:48.159692 2, 0xFFFF, sum = 0
6933 22:55:48.163050 3, 0xFFFF, sum = 0
6934 22:55:48.163136 4, 0xFFFF, sum = 0
6935 22:55:48.165986 5, 0xFFFF, sum = 0
6936 22:55:48.166071 6, 0xFFFF, sum = 0
6937 22:55:48.169110 7, 0xFFFF, sum = 0
6938 22:55:48.169194 8, 0xFFFF, sum = 0
6939 22:55:48.172703 9, 0xFFFF, sum = 0
6940 22:55:48.172792 10, 0xFFFF, sum = 0
6941 22:55:48.175769 11, 0xFFFF, sum = 0
6942 22:55:48.175856 12, 0xFFFF, sum = 0
6943 22:55:48.179800 13, 0x0, sum = 1
6944 22:55:48.179886 14, 0x0, sum = 2
6945 22:55:48.183167 15, 0x0, sum = 3
6946 22:55:48.183254 16, 0x0, sum = 4
6947 22:55:48.186069 best_step = 14
6948 22:55:48.186155
6949 22:55:48.186240 ==
6950 22:55:48.188849 Dram Type= 6, Freq= 0, CH_1, rank 1
6951 22:55:48.192534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6952 22:55:48.192620 ==
6953 22:55:48.195991 RX Vref Scan: 0
6954 22:55:48.196115
6955 22:55:48.196201 RX Vref 0 -> 0, step: 1
6956 22:55:48.196283
6957 22:55:48.199248 RX Delay -343 -> 252, step: 8
6958 22:55:48.206586 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6959 22:55:48.210452 iDelay=217, Bit 1, Center -40 (-287 ~ 208) 496
6960 22:55:48.213625 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6961 22:55:48.220196 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6962 22:55:48.222857 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6963 22:55:48.226426 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6964 22:55:48.230164 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6965 22:55:48.236074 iDelay=217, Bit 7, Center -40 (-287 ~ 208) 496
6966 22:55:48.239862 iDelay=217, Bit 8, Center -56 (-295 ~ 184) 480
6967 22:55:48.243303 iDelay=217, Bit 9, Center -52 (-295 ~ 192) 488
6968 22:55:48.246288 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
6969 22:55:48.253301 iDelay=217, Bit 11, Center -48 (-287 ~ 192) 480
6970 22:55:48.256505 iDelay=217, Bit 12, Center -32 (-271 ~ 208) 480
6971 22:55:48.259789 iDelay=217, Bit 13, Center -36 (-279 ~ 208) 488
6972 22:55:48.262557 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6973 22:55:48.269112 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6974 22:55:48.269196 ==
6975 22:55:48.272904 Dram Type= 6, Freq= 0, CH_1, rank 1
6976 22:55:48.276023 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6977 22:55:48.276153 ==
6978 22:55:48.276224 DQS Delay:
6979 22:55:48.279362 DQS0 = 48, DQS1 = 56
6980 22:55:48.279469 DQM Delay:
6981 22:55:48.283037 DQM0 = 11, DQM1 = 14
6982 22:55:48.283135 DQ Delay:
6983 22:55:48.286012 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6984 22:55:48.289674 DQ4 =12, DQ5 =20, DQ6 =20, DQ7 =8
6985 22:55:48.292539 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6986 22:55:48.296128 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =20
6987 22:55:48.296197
6988 22:55:48.296258
6989 22:55:48.305891 [DQSOSCAuto] RK1, (LSB)MR18= 0x7cb4, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 394 ps
6990 22:55:48.305994 CH1 RK1: MR19=C0C, MR18=7CB4
6991 22:55:48.312355 CH1_RK1: MR19=0xC0C, MR18=0x7CB4, DQSOSC=387, MR23=63, INC=394, DEC=262
6992 22:55:48.315548 [RxdqsGatingPostProcess] freq 400
6993 22:55:48.322190 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6994 22:55:48.325155 best DQS0 dly(2T, 0.5T) = (0, 10)
6995 22:55:48.328556 best DQS1 dly(2T, 0.5T) = (0, 10)
6996 22:55:48.332174 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6997 22:55:48.334957 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6998 22:55:48.338184 best DQS0 dly(2T, 0.5T) = (0, 10)
6999 22:55:48.342006 best DQS1 dly(2T, 0.5T) = (0, 10)
7000 22:55:48.344887 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7001 22:55:48.348353 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7002 22:55:48.348436 Pre-setting of DQS Precalculation
7003 22:55:48.354847 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7004 22:55:48.361441 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7005 22:55:48.367859 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7006 22:55:48.367942
7007 22:55:48.368008
7008 22:55:48.371495 [Calibration Summary] 800 Mbps
7009 22:55:48.374421 CH 0, Rank 0
7010 22:55:48.374504 SW Impedance : PASS
7011 22:55:48.377871 DUTY Scan : NO K
7012 22:55:48.381251 ZQ Calibration : PASS
7013 22:55:48.381334 Jitter Meter : NO K
7014 22:55:48.384529 CBT Training : PASS
7015 22:55:48.387822 Write leveling : PASS
7016 22:55:48.387904 RX DQS gating : PASS
7017 22:55:48.391259 RX DQ/DQS(RDDQC) : PASS
7018 22:55:48.394406 TX DQ/DQS : PASS
7019 22:55:48.394489 RX DATLAT : PASS
7020 22:55:48.397869 RX DQ/DQS(Engine): PASS
7021 22:55:48.397952 TX OE : NO K
7022 22:55:48.400813 All Pass.
7023 22:55:48.400895
7024 22:55:48.400960 CH 0, Rank 1
7025 22:55:48.404262 SW Impedance : PASS
7026 22:55:48.404344 DUTY Scan : NO K
7027 22:55:48.407754 ZQ Calibration : PASS
7028 22:55:48.411135 Jitter Meter : NO K
7029 22:55:48.411218 CBT Training : PASS
7030 22:55:48.414024 Write leveling : NO K
7031 22:55:48.417657 RX DQS gating : PASS
7032 22:55:48.417739 RX DQ/DQS(RDDQC) : PASS
7033 22:55:48.420611 TX DQ/DQS : PASS
7034 22:55:48.423970 RX DATLAT : PASS
7035 22:55:48.424087 RX DQ/DQS(Engine): PASS
7036 22:55:48.427104 TX OE : NO K
7037 22:55:48.427186 All Pass.
7038 22:55:48.427252
7039 22:55:48.430408 CH 1, Rank 0
7040 22:55:48.430490 SW Impedance : PASS
7041 22:55:48.433828 DUTY Scan : NO K
7042 22:55:48.437099 ZQ Calibration : PASS
7043 22:55:48.437181 Jitter Meter : NO K
7044 22:55:48.440604 CBT Training : PASS
7045 22:55:48.443812 Write leveling : PASS
7046 22:55:48.443894 RX DQS gating : PASS
7047 22:55:48.446999 RX DQ/DQS(RDDQC) : PASS
7048 22:55:48.450088 TX DQ/DQS : PASS
7049 22:55:48.450171 RX DATLAT : PASS
7050 22:55:48.453652 RX DQ/DQS(Engine): PASS
7051 22:55:48.456948 TX OE : NO K
7052 22:55:48.457030 All Pass.
7053 22:55:48.457095
7054 22:55:48.457155 CH 1, Rank 1
7055 22:55:48.461147 SW Impedance : PASS
7056 22:55:48.463390 DUTY Scan : NO K
7057 22:55:48.463471 ZQ Calibration : PASS
7058 22:55:48.466836 Jitter Meter : NO K
7059 22:55:48.469960 CBT Training : PASS
7060 22:55:48.470042 Write leveling : NO K
7061 22:55:48.473585 RX DQS gating : PASS
7062 22:55:48.476735 RX DQ/DQS(RDDQC) : PASS
7063 22:55:48.476818 TX DQ/DQS : PASS
7064 22:55:48.479986 RX DATLAT : PASS
7065 22:55:48.480106 RX DQ/DQS(Engine): PASS
7066 22:55:48.483352 TX OE : NO K
7067 22:55:48.483434 All Pass.
7068 22:55:48.483499
7069 22:55:48.486391 DramC Write-DBI off
7070 22:55:48.489861 PER_BANK_REFRESH: Hybrid Mode
7071 22:55:48.489943 TX_TRACKING: ON
7072 22:55:48.499438 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7073 22:55:48.502996 [FAST_K] Save calibration result to emmc
7074 22:55:48.506221 dramc_set_vcore_voltage set vcore to 725000
7075 22:55:48.509518 Read voltage for 1600, 0
7076 22:55:48.509601 Vio18 = 0
7077 22:55:48.512653 Vcore = 725000
7078 22:55:48.512736 Vdram = 0
7079 22:55:48.512802 Vddq = 0
7080 22:55:48.516228 Vmddr = 0
7081 22:55:48.519545 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7082 22:55:48.526048 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7083 22:55:48.526132 MEM_TYPE=3, freq_sel=13
7084 22:55:48.529042 sv_algorithm_assistance_LP4_3733
7085 22:55:48.536213 ============ PULL DRAM RESETB DOWN ============
7086 22:55:48.539186 ========== PULL DRAM RESETB DOWN end =========
7087 22:55:48.542889 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7088 22:55:48.546304 ===================================
7089 22:55:48.548870 LPDDR4 DRAM CONFIGURATION
7090 22:55:48.552210 ===================================
7091 22:55:48.552293 EX_ROW_EN[0] = 0x0
7092 22:55:48.555915 EX_ROW_EN[1] = 0x0
7093 22:55:48.559252 LP4Y_EN = 0x0
7094 22:55:48.559335 WORK_FSP = 0x1
7095 22:55:48.562250 WL = 0x5
7096 22:55:48.562334 RL = 0x5
7097 22:55:48.566004 BL = 0x2
7098 22:55:48.566087 RPST = 0x0
7099 22:55:48.569148 RD_PRE = 0x0
7100 22:55:48.569295 WR_PRE = 0x1
7101 22:55:48.572281 WR_PST = 0x1
7102 22:55:48.572381 DBI_WR = 0x0
7103 22:55:48.575219 DBI_RD = 0x0
7104 22:55:48.575302 OTF = 0x1
7105 22:55:48.578580 ===================================
7106 22:55:48.582604 ===================================
7107 22:55:48.585162 ANA top config
7108 22:55:48.588609 ===================================
7109 22:55:48.591938 DLL_ASYNC_EN = 0
7110 22:55:48.592070 ALL_SLAVE_EN = 0
7111 22:55:48.594804 NEW_RANK_MODE = 1
7112 22:55:48.598440 DLL_IDLE_MODE = 1
7113 22:55:48.601672 LP45_APHY_COMB_EN = 1
7114 22:55:48.601755 TX_ODT_DIS = 0
7115 22:55:48.605155 NEW_8X_MODE = 1
7116 22:55:48.608574 ===================================
7117 22:55:48.611692 ===================================
7118 22:55:48.615113 data_rate = 3200
7119 22:55:48.618128 CKR = 1
7120 22:55:48.621862 DQ_P2S_RATIO = 8
7121 22:55:48.625101 ===================================
7122 22:55:48.627959 CA_P2S_RATIO = 8
7123 22:55:48.628108 DQ_CA_OPEN = 0
7124 22:55:48.631896 DQ_SEMI_OPEN = 0
7125 22:55:48.635132 CA_SEMI_OPEN = 0
7126 22:55:48.638118 CA_FULL_RATE = 0
7127 22:55:48.641608 DQ_CKDIV4_EN = 0
7128 22:55:48.644778 CA_CKDIV4_EN = 0
7129 22:55:48.644861 CA_PREDIV_EN = 0
7130 22:55:48.648285 PH8_DLY = 12
7131 22:55:48.651258 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7132 22:55:48.654678 DQ_AAMCK_DIV = 4
7133 22:55:48.657911 CA_AAMCK_DIV = 4
7134 22:55:48.660836 CA_ADMCK_DIV = 4
7135 22:55:48.664270 DQ_TRACK_CA_EN = 0
7136 22:55:48.664354 CA_PICK = 1600
7137 22:55:48.667867 CA_MCKIO = 1600
7138 22:55:48.671303 MCKIO_SEMI = 0
7139 22:55:48.674542 PLL_FREQ = 3068
7140 22:55:48.677508 DQ_UI_PI_RATIO = 32
7141 22:55:48.680708 CA_UI_PI_RATIO = 0
7142 22:55:48.683790 ===================================
7143 22:55:48.687192 ===================================
7144 22:55:48.690614 memory_type:LPDDR4
7145 22:55:48.690684 GP_NUM : 10
7146 22:55:48.693975 SRAM_EN : 1
7147 22:55:48.694044 MD32_EN : 0
7148 22:55:48.697255 ===================================
7149 22:55:48.700170 [ANA_INIT] >>>>>>>>>>>>>>
7150 22:55:48.703636 <<<<<< [CONFIGURE PHASE]: ANA_TX
7151 22:55:48.707248 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7152 22:55:48.710254 ===================================
7153 22:55:48.713668 data_rate = 3200,PCW = 0X7600
7154 22:55:48.717203 ===================================
7155 22:55:48.721452 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7156 22:55:48.726716 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7157 22:55:48.730305 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7158 22:55:48.736647 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7159 22:55:48.739739 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7160 22:55:48.743521 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7161 22:55:48.743602 [ANA_INIT] flow start
7162 22:55:48.747008 [ANA_INIT] PLL >>>>>>>>
7163 22:55:48.749955 [ANA_INIT] PLL <<<<<<<<
7164 22:55:48.753225 [ANA_INIT] MIDPI >>>>>>>>
7165 22:55:48.753297 [ANA_INIT] MIDPI <<<<<<<<
7166 22:55:48.756341 [ANA_INIT] DLL >>>>>>>>
7167 22:55:48.759637 [ANA_INIT] DLL <<<<<<<<
7168 22:55:48.759704 [ANA_INIT] flow end
7169 22:55:48.763626 ============ LP4 DIFF to SE enter ============
7170 22:55:48.769594 ============ LP4 DIFF to SE exit ============
7171 22:55:48.769675 [ANA_INIT] <<<<<<<<<<<<<
7172 22:55:48.773722 [Flow] Enable top DCM control >>>>>
7173 22:55:48.776270 [Flow] Enable top DCM control <<<<<
7174 22:55:48.779561 Enable DLL master slave shuffle
7175 22:55:48.786311 ==============================================================
7176 22:55:48.786394 Gating Mode config
7177 22:55:48.792590 ==============================================================
7178 22:55:48.795929 Config description:
7179 22:55:48.805658 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7180 22:55:48.812665 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7181 22:55:48.815970 SELPH_MODE 0: By rank 1: By Phase
7182 22:55:48.822535 ==============================================================
7183 22:55:48.825862 GAT_TRACK_EN = 1
7184 22:55:48.828734 RX_GATING_MODE = 2
7185 22:55:48.832222 RX_GATING_TRACK_MODE = 2
7186 22:55:48.832301 SELPH_MODE = 1
7187 22:55:48.835719 PICG_EARLY_EN = 1
7188 22:55:48.838805 VALID_LAT_VALUE = 1
7189 22:55:48.845981 ==============================================================
7190 22:55:48.848705 Enter into Gating configuration >>>>
7191 22:55:48.851970 Exit from Gating configuration <<<<
7192 22:55:48.855389 Enter into DVFS_PRE_config >>>>>
7193 22:55:48.865259 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7194 22:55:48.869348 Exit from DVFS_PRE_config <<<<<
7195 22:55:48.871939 Enter into PICG configuration >>>>
7196 22:55:48.874965 Exit from PICG configuration <<<<
7197 22:55:48.878583 [RX_INPUT] configuration >>>>>
7198 22:55:48.881548 [RX_INPUT] configuration <<<<<
7199 22:55:48.884903 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7200 22:55:48.891781 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7201 22:55:48.897984 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7202 22:55:48.904434 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7203 22:55:48.910988 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7204 22:55:48.917809 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7205 22:55:48.920928 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7206 22:55:48.924377 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7207 22:55:48.927507 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7208 22:55:48.933967 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7209 22:55:48.937578 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7210 22:55:48.941177 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7211 22:55:48.944242 ===================================
7212 22:55:48.947173 LPDDR4 DRAM CONFIGURATION
7213 22:55:48.950398 ===================================
7214 22:55:48.950469 EX_ROW_EN[0] = 0x0
7215 22:55:48.953916 EX_ROW_EN[1] = 0x0
7216 22:55:48.957438 LP4Y_EN = 0x0
7217 22:55:48.957512 WORK_FSP = 0x1
7218 22:55:48.960485 WL = 0x5
7219 22:55:48.960556 RL = 0x5
7220 22:55:48.963769 BL = 0x2
7221 22:55:48.963851 RPST = 0x0
7222 22:55:48.966910 RD_PRE = 0x0
7223 22:55:48.966985 WR_PRE = 0x1
7224 22:55:48.970767 WR_PST = 0x1
7225 22:55:48.970845 DBI_WR = 0x0
7226 22:55:48.973640 DBI_RD = 0x0
7227 22:55:48.973712 OTF = 0x1
7228 22:55:48.977936 ===================================
7229 22:55:48.983525 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7230 22:55:48.986639 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7231 22:55:48.990306 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7232 22:55:48.993238 ===================================
7233 22:55:48.996472 LPDDR4 DRAM CONFIGURATION
7234 22:55:49.000283 ===================================
7235 22:55:49.003146 EX_ROW_EN[0] = 0x10
7236 22:55:49.003229 EX_ROW_EN[1] = 0x0
7237 22:55:49.006406 LP4Y_EN = 0x0
7238 22:55:49.006515 WORK_FSP = 0x1
7239 22:55:49.009670 WL = 0x5
7240 22:55:49.009752 RL = 0x5
7241 22:55:49.013024 BL = 0x2
7242 22:55:49.013105 RPST = 0x0
7243 22:55:49.016229 RD_PRE = 0x0
7244 22:55:49.016310 WR_PRE = 0x1
7245 22:55:49.019451 WR_PST = 0x1
7246 22:55:49.019533 DBI_WR = 0x0
7247 22:55:49.022918 DBI_RD = 0x0
7248 22:55:49.022999 OTF = 0x1
7249 22:55:49.026088 ===================================
7250 22:55:49.032750 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7251 22:55:49.032832 ==
7252 22:55:49.036260 Dram Type= 6, Freq= 0, CH_0, rank 0
7253 22:55:49.042747 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7254 22:55:49.042828 ==
7255 22:55:49.042894 [Duty_Offset_Calibration]
7256 22:55:49.045966 B0:2 B1:0 CA:4
7257 22:55:49.046076
7258 22:55:49.049296 [DutyScan_Calibration_Flow] k_type=0
7259 22:55:49.058233
7260 22:55:49.058314 ==CLK 0==
7261 22:55:49.061604 Final CLK duty delay cell = -4
7262 22:55:49.064731 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7263 22:55:49.067927 [-4] MIN Duty = 4844%(X100), DQS PI = 4
7264 22:55:49.071145 [-4] AVG Duty = 4937%(X100)
7265 22:55:49.071227
7266 22:55:49.074588 CH0 CLK Duty spec in!! Max-Min= 187%
7267 22:55:49.077893 [DutyScan_Calibration_Flow] ====Done====
7268 22:55:49.078002
7269 22:55:49.081447 [DutyScan_Calibration_Flow] k_type=1
7270 22:55:49.098766
7271 22:55:49.098848 ==DQS 0 ==
7272 22:55:49.101658 Final DQS duty delay cell = 0
7273 22:55:49.105025 [0] MAX Duty = 5249%(X100), DQS PI = 38
7274 22:55:49.108592 [0] MIN Duty = 5093%(X100), DQS PI = 12
7275 22:55:49.111252 [0] AVG Duty = 5171%(X100)
7276 22:55:49.111333
7277 22:55:49.111398 ==DQS 1 ==
7278 22:55:49.114714 Final DQS duty delay cell = 0
7279 22:55:49.118126 [0] MAX Duty = 5187%(X100), DQS PI = 46
7280 22:55:49.121291 [0] MIN Duty = 4969%(X100), DQS PI = 10
7281 22:55:49.124684 [0] AVG Duty = 5078%(X100)
7282 22:55:49.124765
7283 22:55:49.127950 CH0 DQS 0 Duty spec in!! Max-Min= 156%
7284 22:55:49.128058
7285 22:55:49.131632 CH0 DQS 1 Duty spec in!! Max-Min= 218%
7286 22:55:49.134461 [DutyScan_Calibration_Flow] ====Done====
7287 22:55:49.134542
7288 22:55:49.137571 [DutyScan_Calibration_Flow] k_type=3
7289 22:55:49.155519
7290 22:55:49.155601 ==DQM 0 ==
7291 22:55:49.158832 Final DQM duty delay cell = 0
7292 22:55:49.162161 [0] MAX Duty = 5124%(X100), DQS PI = 20
7293 22:55:49.165575 [0] MIN Duty = 4875%(X100), DQS PI = 56
7294 22:55:49.168595 [0] AVG Duty = 4999%(X100)
7295 22:55:49.168676
7296 22:55:49.168741 ==DQM 1 ==
7297 22:55:49.172256 Final DQM duty delay cell = 0
7298 22:55:49.175280 [0] MAX Duty = 4969%(X100), DQS PI = 0
7299 22:55:49.178997 [0] MIN Duty = 4844%(X100), DQS PI = 16
7300 22:55:49.181713 [0] AVG Duty = 4906%(X100)
7301 22:55:49.181794
7302 22:55:49.185355 CH0 DQM 0 Duty spec in!! Max-Min= 249%
7303 22:55:49.185436
7304 22:55:49.188870 CH0 DQM 1 Duty spec in!! Max-Min= 125%
7305 22:55:49.191932 [DutyScan_Calibration_Flow] ====Done====
7306 22:55:49.192013
7307 22:55:49.195401 [DutyScan_Calibration_Flow] k_type=2
7308 22:55:49.212769
7309 22:55:49.212851 ==DQ 0 ==
7310 22:55:49.216120 Final DQ duty delay cell = 0
7311 22:55:49.219567 [0] MAX Duty = 5156%(X100), DQS PI = 22
7312 22:55:49.222542 [0] MIN Duty = 4969%(X100), DQS PI = 8
7313 22:55:49.222623 [0] AVG Duty = 5062%(X100)
7314 22:55:49.225986
7315 22:55:49.226067 ==DQ 1 ==
7316 22:55:49.229042 Final DQ duty delay cell = 0
7317 22:55:49.232185 [0] MAX Duty = 5187%(X100), DQS PI = 2
7318 22:55:49.235925 [0] MIN Duty = 4907%(X100), DQS PI = 32
7319 22:55:49.236006 [0] AVG Duty = 5047%(X100)
7320 22:55:49.238845
7321 22:55:49.242508 CH0 DQ 0 Duty spec in!! Max-Min= 187%
7322 22:55:49.242608
7323 22:55:49.245913 CH0 DQ 1 Duty spec in!! Max-Min= 280%
7324 22:55:49.249213 [DutyScan_Calibration_Flow] ====Done====
7325 22:55:49.249296 ==
7326 22:55:49.252229 Dram Type= 6, Freq= 0, CH_1, rank 0
7327 22:55:49.255298 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7328 22:55:49.255380 ==
7329 22:55:49.258803 [Duty_Offset_Calibration]
7330 22:55:49.258885 B0:0 B1:-1 CA:3
7331 22:55:49.258959
7332 22:55:49.261865 [DutyScan_Calibration_Flow] k_type=0
7333 22:55:49.271870
7334 22:55:49.271978 ==CLK 0==
7335 22:55:49.275431 Final CLK duty delay cell = -4
7336 22:55:49.278367 [-4] MAX Duty = 5000%(X100), DQS PI = 4
7337 22:55:49.281692 [-4] MIN Duty = 4844%(X100), DQS PI = 38
7338 22:55:49.285473 [-4] AVG Duty = 4922%(X100)
7339 22:55:49.285555
7340 22:55:49.288752 CH1 CLK Duty spec in!! Max-Min= 156%
7341 22:55:49.291498 [DutyScan_Calibration_Flow] ====Done====
7342 22:55:49.291580
7343 22:55:49.294801 [DutyScan_Calibration_Flow] k_type=1
7344 22:55:49.311002
7345 22:55:49.311083 ==DQS 0 ==
7346 22:55:49.314598 Final DQS duty delay cell = 0
7347 22:55:49.317461 [0] MAX Duty = 5250%(X100), DQS PI = 28
7348 22:55:49.320874 [0] MIN Duty = 4907%(X100), DQS PI = 60
7349 22:55:49.324579 [0] AVG Duty = 5078%(X100)
7350 22:55:49.324658
7351 22:55:49.324721 ==DQS 1 ==
7352 22:55:49.327728 Final DQS duty delay cell = -4
7353 22:55:49.330529 [-4] MAX Duty = 5000%(X100), DQS PI = 30
7354 22:55:49.333989 [-4] MIN Duty = 4813%(X100), DQS PI = 0
7355 22:55:49.337103 [-4] AVG Duty = 4906%(X100)
7356 22:55:49.337183
7357 22:55:49.340532 CH1 DQS 0 Duty spec in!! Max-Min= 343%
7358 22:55:49.340612
7359 22:55:49.343980 CH1 DQS 1 Duty spec in!! Max-Min= 187%
7360 22:55:49.347495 [DutyScan_Calibration_Flow] ====Done====
7361 22:55:49.347574
7362 22:55:49.350337 [DutyScan_Calibration_Flow] k_type=3
7363 22:55:49.368685
7364 22:55:49.368766 ==DQM 0 ==
7365 22:55:49.371427 Final DQM duty delay cell = 0
7366 22:55:49.374761 [0] MAX Duty = 5062%(X100), DQS PI = 30
7367 22:55:49.377998 [0] MIN Duty = 4782%(X100), DQS PI = 38
7368 22:55:49.382332 [0] AVG Duty = 4922%(X100)
7369 22:55:49.382411
7370 22:55:49.382474 ==DQM 1 ==
7371 22:55:49.385222 Final DQM duty delay cell = 0
7372 22:55:49.388310 [0] MAX Duty = 5000%(X100), DQS PI = 32
7373 22:55:49.391466 [0] MIN Duty = 4813%(X100), DQS PI = 0
7374 22:55:49.394704 [0] AVG Duty = 4906%(X100)
7375 22:55:49.394784
7376 22:55:49.397835 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7377 22:55:49.397929
7378 22:55:49.401129 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7379 22:55:49.405002 [DutyScan_Calibration_Flow] ====Done====
7380 22:55:49.405082
7381 22:55:49.407627 [DutyScan_Calibration_Flow] k_type=2
7382 22:55:49.424550
7383 22:55:49.424629 ==DQ 0 ==
7384 22:55:49.428175 Final DQ duty delay cell = -4
7385 22:55:49.430707 [-4] MAX Duty = 4938%(X100), DQS PI = 0
7386 22:55:49.434097 [-4] MIN Duty = 4813%(X100), DQS PI = 38
7387 22:55:49.438104 [-4] AVG Duty = 4875%(X100)
7388 22:55:49.438185
7389 22:55:49.438249 ==DQ 1 ==
7390 22:55:49.440661 Final DQ duty delay cell = 0
7391 22:55:49.444126 [0] MAX Duty = 5062%(X100), DQS PI = 32
7392 22:55:49.447539 [0] MIN Duty = 4875%(X100), DQS PI = 0
7393 22:55:49.450787 [0] AVG Duty = 4968%(X100)
7394 22:55:49.450886
7395 22:55:49.454203 CH1 DQ 0 Duty spec in!! Max-Min= 125%
7396 22:55:49.454285
7397 22:55:49.457268 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7398 22:55:49.460871 [DutyScan_Calibration_Flow] ====Done====
7399 22:55:49.463694 nWR fixed to 30
7400 22:55:49.467118 [ModeRegInit_LP4] CH0 RK0
7401 22:55:49.467200 [ModeRegInit_LP4] CH0 RK1
7402 22:55:49.470482 [ModeRegInit_LP4] CH1 RK0
7403 22:55:49.473911 [ModeRegInit_LP4] CH1 RK1
7404 22:55:49.473992 match AC timing 5
7405 22:55:49.480277 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7406 22:55:49.483480 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7407 22:55:49.487045 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7408 22:55:49.493579 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7409 22:55:49.496666 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7410 22:55:49.496748 [MiockJmeterHQA]
7411 22:55:49.500226
7412 22:55:49.500310 [DramcMiockJmeter] u1RxGatingPI = 0
7413 22:55:49.503664 0 : 4252, 4027
7414 22:55:49.503747 4 : 4253, 4026
7415 22:55:49.506906 8 : 4255, 4029
7416 22:55:49.506989 12 : 4252, 4027
7417 22:55:49.509857 16 : 4253, 4027
7418 22:55:49.509940 20 : 4253, 4027
7419 22:55:49.513413 24 : 4252, 4027
7420 22:55:49.513496 28 : 4363, 4137
7421 22:55:49.513562 32 : 4255, 4029
7422 22:55:49.516813 36 : 4363, 4138
7423 22:55:49.516896 40 : 4252, 4027
7424 22:55:49.520184 44 : 4253, 4026
7425 22:55:49.520266 48 : 4255, 4029
7426 22:55:49.523246 52 : 4252, 4027
7427 22:55:49.523329 56 : 4366, 4140
7428 22:55:49.526326 60 : 4363, 4139
7429 22:55:49.526422 64 : 4250, 4027
7430 22:55:49.526492 68 : 4253, 4029
7431 22:55:49.529825 72 : 4360, 4138
7432 22:55:49.529908 76 : 4250, 4026
7433 22:55:49.533036 80 : 4363, 4140
7434 22:55:49.533118 84 : 4250, 4027
7435 22:55:49.536546 88 : 4250, 4027
7436 22:55:49.536629 92 : 4250, 4027
7437 22:55:49.536696 96 : 4252, 2957
7438 22:55:49.540370 100 : 4360, 0
7439 22:55:49.540453 104 : 4252, 0
7440 22:55:49.542811 108 : 4255, 0
7441 22:55:49.542893 112 : 4363, 0
7442 22:55:49.542959 116 : 4252, 0
7443 22:55:49.546622 120 : 4250, 0
7444 22:55:49.546705 124 : 4365, 0
7445 22:55:49.549681 128 : 4360, 0
7446 22:55:49.549764 132 : 4250, 0
7447 22:55:49.549838 136 : 4249, 0
7448 22:55:49.553558 140 : 4250, 0
7449 22:55:49.553641 144 : 4252, 0
7450 22:55:49.556207 148 : 4250, 0
7451 22:55:49.556290 152 : 4250, 0
7452 22:55:49.556356 156 : 4255, 0
7453 22:55:49.559780 160 : 4361, 0
7454 22:55:49.559863 164 : 4250, 0
7455 22:55:49.562500 168 : 4360, 0
7456 22:55:49.562583 172 : 4250, 0
7457 22:55:49.562648 176 : 4360, 0
7458 22:55:49.566395 180 : 4250, 0
7459 22:55:49.566478 184 : 4250, 0
7460 22:55:49.569541 188 : 4250, 0
7461 22:55:49.569625 192 : 4250, 0
7462 22:55:49.569692 196 : 4253, 0
7463 22:55:49.572742 200 : 4360, 0
7464 22:55:49.572824 204 : 4250, 0
7465 22:55:49.575679 208 : 4250, 0
7466 22:55:49.575762 212 : 4361, 0
7467 22:55:49.575828 216 : 4361, 0
7468 22:55:49.578905 220 : 4250, 674
7469 22:55:49.578988 224 : 4360, 4068
7470 22:55:49.582397 228 : 4360, 4138
7471 22:55:49.582480 232 : 4250, 4027
7472 22:55:49.586804 236 : 4250, 4026
7473 22:55:49.586887 240 : 4363, 4140
7474 22:55:49.589727 244 : 4360, 4138
7475 22:55:49.589809 248 : 4250, 4027
7476 22:55:49.589876 252 : 4250, 4027
7477 22:55:49.592654 256 : 4250, 4027
7478 22:55:49.592737 260 : 4252, 4027
7479 22:55:49.595436 264 : 4250, 4027
7480 22:55:49.595519 268 : 4252, 4029
7481 22:55:49.598912 272 : 4250, 4027
7482 22:55:49.598994 276 : 4363, 4139
7483 22:55:49.602367 280 : 4250, 4027
7484 22:55:49.602450 284 : 4250, 4027
7485 22:55:49.606046 288 : 4250, 4026
7486 22:55:49.606129 292 : 4363, 4140
7487 22:55:49.608897 296 : 4360, 4138
7488 22:55:49.608979 300 : 4249, 4027
7489 22:55:49.612404 304 : 4363, 4140
7490 22:55:49.612487 308 : 4253, 4029
7491 22:55:49.615318 312 : 4250, 4027
7492 22:55:49.615401 316 : 4250, 4027
7493 22:55:49.615467 320 : 4252, 4029
7494 22:55:49.618792 324 : 4250, 4027
7495 22:55:49.618874 328 : 4363, 4139
7496 22:55:49.622375 332 : 4250, 4022
7497 22:55:49.622457 336 : 4252, 2329
7498 22:55:49.625650 340 : 4250, 26
7499 22:55:49.625734
7500 22:55:49.628741 MIOCK jitter meter ch=0
7501 22:55:49.628823
7502 22:55:49.628886 1T = (340-100) = 240 dly cells
7503 22:55:49.635220 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 271/100 ps
7504 22:55:49.635305 ==
7505 22:55:49.638950 Dram Type= 6, Freq= 0, CH_0, rank 0
7506 22:55:49.641849 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7507 22:55:49.644898 ==
7508 22:55:49.648310 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7509 22:55:49.651514 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7510 22:55:49.658264 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7511 22:55:49.664846 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7512 22:55:49.672476 [CA 0] Center 44 (14~74) winsize 61
7513 22:55:49.675619 [CA 1] Center 43 (13~74) winsize 62
7514 22:55:49.678668 [CA 2] Center 39 (10~68) winsize 59
7515 22:55:49.681908 [CA 3] Center 38 (9~68) winsize 60
7516 22:55:49.685974 [CA 4] Center 36 (7~66) winsize 60
7517 22:55:49.688767 [CA 5] Center 36 (6~66) winsize 61
7518 22:55:49.688848
7519 22:55:49.692252 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7520 22:55:49.692334
7521 22:55:49.698945 [CATrainingPosCal] consider 1 rank data
7522 22:55:49.699026 u2DelayCellTimex100 = 271/100 ps
7523 22:55:49.705171 CA0 delay=44 (14~74),Diff = 8 PI (28 cell)
7524 22:55:49.708382 CA1 delay=43 (13~74),Diff = 7 PI (25 cell)
7525 22:55:49.711698 CA2 delay=39 (10~68),Diff = 3 PI (10 cell)
7526 22:55:49.715007 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7527 22:55:49.718663 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7528 22:55:49.721647 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7529 22:55:49.721729
7530 22:55:49.725197 CA PerBit enable=1, Macro0, CA PI delay=36
7531 22:55:49.725279
7532 22:55:49.728408 [CBTSetCACLKResult] CA Dly = 36
7533 22:55:49.731626 CS Dly: 11 (0~42)
7534 22:55:49.735342 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7535 22:55:49.738478 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7536 22:55:49.738559 ==
7537 22:55:49.741522 Dram Type= 6, Freq= 0, CH_0, rank 1
7538 22:55:49.747729 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7539 22:55:49.747811 ==
7540 22:55:49.751072 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7541 22:55:49.758015 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7542 22:55:49.760857 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7543 22:55:49.767823 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7544 22:55:49.776148 [CA 0] Center 43 (13~74) winsize 62
7545 22:55:49.778991 [CA 1] Center 43 (13~73) winsize 61
7546 22:55:49.782567 [CA 2] Center 38 (9~68) winsize 60
7547 22:55:49.786125 [CA 3] Center 38 (9~68) winsize 60
7548 22:55:49.788949 [CA 4] Center 36 (6~66) winsize 61
7549 22:55:49.792368 [CA 5] Center 36 (6~66) winsize 61
7550 22:55:49.792450
7551 22:55:49.795595 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7552 22:55:49.795677
7553 22:55:49.802187 [CATrainingPosCal] consider 2 rank data
7554 22:55:49.802269 u2DelayCellTimex100 = 271/100 ps
7555 22:55:49.808585 CA0 delay=44 (14~74),Diff = 8 PI (28 cell)
7556 22:55:49.811765 CA1 delay=43 (13~73),Diff = 7 PI (25 cell)
7557 22:55:49.815975 CA2 delay=39 (10~68),Diff = 3 PI (10 cell)
7558 22:55:49.818403 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7559 22:55:49.821901 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7560 22:55:49.825187 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7561 22:55:49.825269
7562 22:55:49.828491 CA PerBit enable=1, Macro0, CA PI delay=36
7563 22:55:49.828573
7564 22:55:49.831928 [CBTSetCACLKResult] CA Dly = 36
7565 22:55:49.834884 CS Dly: 11 (0~43)
7566 22:55:49.838163 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7567 22:55:49.841425 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7568 22:55:49.841507
7569 22:55:49.845012 ----->DramcWriteLeveling(PI) begin...
7570 22:55:49.847943 ==
7571 22:55:49.851457 Dram Type= 6, Freq= 0, CH_0, rank 0
7572 22:55:49.855119 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7573 22:55:49.855201 ==
7574 22:55:49.858235 Write leveling (Byte 0): 35 => 35
7575 22:55:49.861290 Write leveling (Byte 1): 24 => 24
7576 22:55:49.864698 DramcWriteLeveling(PI) end<-----
7577 22:55:49.864780
7578 22:55:49.864845 ==
7579 22:55:49.867691 Dram Type= 6, Freq= 0, CH_0, rank 0
7580 22:55:49.871202 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7581 22:55:49.871283 ==
7582 22:55:49.874256 [Gating] SW mode calibration
7583 22:55:49.880902 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7584 22:55:49.887758 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7585 22:55:49.890826 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7586 22:55:49.894506 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7587 22:55:49.900574 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7588 22:55:49.903942 1 4 12 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
7589 22:55:49.907567 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7590 22:55:49.914038 1 4 20 | B1->B0 | 2828 3434 | 1 1 | (1 1) (1 1)
7591 22:55:49.917105 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7592 22:55:49.920304 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7593 22:55:49.926831 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7594 22:55:49.929938 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7595 22:55:49.933546 1 5 8 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
7596 22:55:49.940275 1 5 12 | B1->B0 | 3434 2626 | 1 0 | (1 1) (0 0)
7597 22:55:49.943563 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7598 22:55:49.946746 1 5 20 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
7599 22:55:49.953112 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
7600 22:55:49.956435 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7601 22:55:49.960014 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7602 22:55:49.966459 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7603 22:55:49.969575 1 6 8 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
7604 22:55:49.973180 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7605 22:55:49.979517 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7606 22:55:49.982994 1 6 20 | B1->B0 | 3131 4646 | 1 0 | (0 0) (0 0)
7607 22:55:49.985839 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7608 22:55:49.992757 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7609 22:55:49.995888 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7610 22:55:49.999217 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7611 22:55:50.005863 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7612 22:55:50.009182 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7613 22:55:50.012638 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7614 22:55:50.018937 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7615 22:55:50.022011 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7616 22:55:50.025431 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7617 22:55:50.031822 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7618 22:55:50.035258 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7619 22:55:50.038776 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7620 22:55:50.045308 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7621 22:55:50.048253 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7622 22:55:50.052293 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7623 22:55:50.058006 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7624 22:55:50.061285 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7625 22:55:50.064897 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7626 22:55:50.071541 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7627 22:55:50.074645 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7628 22:55:50.081397 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7629 22:55:50.084889 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7630 22:55:50.087667 Total UI for P1: 0, mck2ui 16
7631 22:55:50.090895 best dqsien dly found for B0: ( 1, 9, 8)
7632 22:55:50.094326 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7633 22:55:50.101199 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7634 22:55:50.104012 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7635 22:55:50.107707 Total UI for P1: 0, mck2ui 16
7636 22:55:50.110825 best dqsien dly found for B1: ( 1, 9, 22)
7637 22:55:50.114175 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
7638 22:55:50.117128 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7639 22:55:50.117212
7640 22:55:50.120546 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
7641 22:55:50.124325 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7642 22:55:50.126979 [Gating] SW calibration Done
7643 22:55:50.127062 ==
7644 22:55:50.130226 Dram Type= 6, Freq= 0, CH_0, rank 0
7645 22:55:50.133814 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7646 22:55:50.137225 ==
7647 22:55:50.137307 RX Vref Scan: 0
7648 22:55:50.137375
7649 22:55:50.140270 RX Vref 0 -> 0, step: 1
7650 22:55:50.140353
7651 22:55:50.143717 RX Delay 0 -> 252, step: 8
7652 22:55:50.146910 iDelay=192, Bit 0, Center 131 (80 ~ 183) 104
7653 22:55:50.150049 iDelay=192, Bit 1, Center 135 (80 ~ 191) 112
7654 22:55:50.153554 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7655 22:55:50.156525 iDelay=192, Bit 3, Center 131 (80 ~ 183) 104
7656 22:55:50.163188 iDelay=192, Bit 4, Center 135 (80 ~ 191) 112
7657 22:55:50.166724 iDelay=192, Bit 5, Center 119 (64 ~ 175) 112
7658 22:55:50.169932 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7659 22:55:50.173799 iDelay=192, Bit 7, Center 139 (88 ~ 191) 104
7660 22:55:50.176427 iDelay=192, Bit 8, Center 115 (64 ~ 167) 104
7661 22:55:50.183065 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7662 22:55:50.186566 iDelay=192, Bit 10, Center 127 (80 ~ 175) 96
7663 22:55:50.189596 iDelay=192, Bit 11, Center 123 (72 ~ 175) 104
7664 22:55:50.192823 iDelay=192, Bit 12, Center 135 (80 ~ 191) 112
7665 22:55:50.199670 iDelay=192, Bit 13, Center 131 (80 ~ 183) 104
7666 22:55:50.202545 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7667 22:55:50.205912 iDelay=192, Bit 15, Center 135 (80 ~ 191) 112
7668 22:55:50.205995 ==
7669 22:55:50.209238 Dram Type= 6, Freq= 0, CH_0, rank 0
7670 22:55:50.212820 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7671 22:55:50.212903 ==
7672 22:55:50.215797 DQS Delay:
7673 22:55:50.215879 DQS0 = 0, DQS1 = 0
7674 22:55:50.218952 DQM Delay:
7675 22:55:50.219035 DQM0 = 132, DQM1 = 126
7676 22:55:50.222576 DQ Delay:
7677 22:55:50.225534 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =131
7678 22:55:50.229105 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
7679 22:55:50.232100 DQ8 =115, DQ9 =111, DQ10 =127, DQ11 =123
7680 22:55:50.235685 DQ12 =135, DQ13 =131, DQ14 =135, DQ15 =135
7681 22:55:50.235768
7682 22:55:50.235834
7683 22:55:50.235894 ==
7684 22:55:50.238993 Dram Type= 6, Freq= 0, CH_0, rank 0
7685 22:55:50.242535 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7686 22:55:50.242619 ==
7687 22:55:50.242685
7688 22:55:50.242745
7689 22:55:50.245850 TX Vref Scan disable
7690 22:55:50.248830 == TX Byte 0 ==
7691 22:55:50.252099 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7692 22:55:50.255570 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7693 22:55:50.258684 == TX Byte 1 ==
7694 22:55:50.261777 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7695 22:55:50.265023 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7696 22:55:50.265106 ==
7697 22:55:50.268632 Dram Type= 6, Freq= 0, CH_0, rank 0
7698 22:55:50.275097 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7699 22:55:50.275181 ==
7700 22:55:50.287978
7701 22:55:50.291276 TX Vref early break, caculate TX vref
7702 22:55:50.294674 TX Vref=16, minBit 1, minWin=22, winSum=366
7703 22:55:50.297489 TX Vref=18, minBit 8, minWin=22, winSum=377
7704 22:55:50.300883 TX Vref=20, minBit 3, minWin=23, winSum=388
7705 22:55:50.304300 TX Vref=22, minBit 1, minWin=24, winSum=396
7706 22:55:50.307625 TX Vref=24, minBit 7, minWin=24, winSum=403
7707 22:55:50.314276 TX Vref=26, minBit 1, minWin=25, winSum=414
7708 22:55:50.317779 TX Vref=28, minBit 2, minWin=25, winSum=415
7709 22:55:50.320574 TX Vref=30, minBit 2, minWin=25, winSum=416
7710 22:55:50.324034 TX Vref=32, minBit 1, minWin=24, winSum=399
7711 22:55:50.327068 TX Vref=34, minBit 0, minWin=24, winSum=392
7712 22:55:50.333770 [TxChooseVref] Worse bit 2, Min win 25, Win sum 416, Final Vref 30
7713 22:55:50.333854
7714 22:55:50.337057 Final TX Range 0 Vref 30
7715 22:55:50.337143
7716 22:55:50.337208 ==
7717 22:55:50.340946 Dram Type= 6, Freq= 0, CH_0, rank 0
7718 22:55:50.343741 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7719 22:55:50.343839 ==
7720 22:55:50.343933
7721 22:55:50.346762
7722 22:55:50.346836 TX Vref Scan disable
7723 22:55:50.353489 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7724 22:55:50.353594 == TX Byte 0 ==
7725 22:55:50.356723 u2DelayCellOfst[0]=10 cells (3 PI)
7726 22:55:50.360093 u2DelayCellOfst[1]=18 cells (5 PI)
7727 22:55:50.363290 u2DelayCellOfst[2]=10 cells (3 PI)
7728 22:55:50.366826 u2DelayCellOfst[3]=10 cells (3 PI)
7729 22:55:50.369909 u2DelayCellOfst[4]=7 cells (2 PI)
7730 22:55:50.373281 u2DelayCellOfst[5]=0 cells (0 PI)
7731 22:55:50.376712 u2DelayCellOfst[6]=18 cells (5 PI)
7732 22:55:50.379813 u2DelayCellOfst[7]=14 cells (4 PI)
7733 22:55:50.383126 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7734 22:55:50.386471 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7735 22:55:50.389691 == TX Byte 1 ==
7736 22:55:50.393157 u2DelayCellOfst[8]=0 cells (0 PI)
7737 22:55:50.396349 u2DelayCellOfst[9]=0 cells (0 PI)
7738 22:55:50.399567 u2DelayCellOfst[10]=7 cells (2 PI)
7739 22:55:50.402948 u2DelayCellOfst[11]=0 cells (0 PI)
7740 22:55:50.406584 u2DelayCellOfst[12]=7 cells (2 PI)
7741 22:55:50.406683 u2DelayCellOfst[13]=10 cells (3 PI)
7742 22:55:50.409598 u2DelayCellOfst[14]=14 cells (4 PI)
7743 22:55:50.413019 u2DelayCellOfst[15]=7 cells (2 PI)
7744 22:55:50.419182 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7745 22:55:50.422650 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7746 22:55:50.426097 DramC Write-DBI on
7747 22:55:50.426196 ==
7748 22:55:50.429621 Dram Type= 6, Freq= 0, CH_0, rank 0
7749 22:55:50.432763 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7750 22:55:50.432862 ==
7751 22:55:50.432951
7752 22:55:50.433036
7753 22:55:50.436062 TX Vref Scan disable
7754 22:55:50.436129 == TX Byte 0 ==
7755 22:55:50.442137 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7756 22:55:50.442236 == TX Byte 1 ==
7757 22:55:50.445625 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
7758 22:55:50.448983 DramC Write-DBI off
7759 22:55:50.449074
7760 22:55:50.449141 [DATLAT]
7761 22:55:50.452497 Freq=1600, CH0 RK0
7762 22:55:50.452570
7763 22:55:50.452632 DATLAT Default: 0xf
7764 22:55:50.455679 0, 0xFFFF, sum = 0
7765 22:55:50.458740 1, 0xFFFF, sum = 0
7766 22:55:50.458843 2, 0xFFFF, sum = 0
7767 22:55:50.462002 3, 0xFFFF, sum = 0
7768 22:55:50.462074 4, 0xFFFF, sum = 0
7769 22:55:50.465606 5, 0xFFFF, sum = 0
7770 22:55:50.465683 6, 0xFFFF, sum = 0
7771 22:55:50.468534 7, 0xFFFF, sum = 0
7772 22:55:50.468636 8, 0xFFFF, sum = 0
7773 22:55:50.471725 9, 0xFFFF, sum = 0
7774 22:55:50.471802 10, 0xFFFF, sum = 0
7775 22:55:50.475153 11, 0xFFFF, sum = 0
7776 22:55:50.475252 12, 0xFFFF, sum = 0
7777 22:55:50.478531 13, 0xFFFF, sum = 0
7778 22:55:50.478630 14, 0x0, sum = 1
7779 22:55:50.482096 15, 0x0, sum = 2
7780 22:55:50.482167 16, 0x0, sum = 3
7781 22:55:50.484871 17, 0x0, sum = 4
7782 22:55:50.484971 best_step = 15
7783 22:55:50.485063
7784 22:55:50.485149 ==
7785 22:55:50.488562 Dram Type= 6, Freq= 0, CH_0, rank 0
7786 22:55:50.494973 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7787 22:55:50.495072 ==
7788 22:55:50.495136 RX Vref Scan: 1
7789 22:55:50.495195
7790 22:55:50.498271 Set Vref Range= 24 -> 127
7791 22:55:50.498367
7792 22:55:50.501387 RX Vref 24 -> 127, step: 1
7793 22:55:50.501462
7794 22:55:50.505137 RX Delay 11 -> 252, step: 4
7795 22:55:50.505209
7796 22:55:50.508036 Set Vref, RX VrefLevel [Byte0]: 24
7797 22:55:50.511506 [Byte1]: 24
7798 22:55:50.511603
7799 22:55:50.514515 Set Vref, RX VrefLevel [Byte0]: 25
7800 22:55:50.517817 [Byte1]: 25
7801 22:55:50.517888
7802 22:55:50.521389 Set Vref, RX VrefLevel [Byte0]: 26
7803 22:55:50.524610 [Byte1]: 26
7804 22:55:50.528169
7805 22:55:50.528268 Set Vref, RX VrefLevel [Byte0]: 27
7806 22:55:50.530930 [Byte1]: 27
7807 22:55:50.535302
7808 22:55:50.535399 Set Vref, RX VrefLevel [Byte0]: 28
7809 22:55:50.538387 [Byte1]: 28
7810 22:55:50.542914
7811 22:55:50.542997 Set Vref, RX VrefLevel [Byte0]: 29
7812 22:55:50.546261 [Byte1]: 29
7813 22:55:50.550426
7814 22:55:50.550525 Set Vref, RX VrefLevel [Byte0]: 30
7815 22:55:50.554036 [Byte1]: 30
7816 22:55:50.558348
7817 22:55:50.558431 Set Vref, RX VrefLevel [Byte0]: 31
7818 22:55:50.561255 [Byte1]: 31
7819 22:55:50.566038
7820 22:55:50.566121 Set Vref, RX VrefLevel [Byte0]: 32
7821 22:55:50.569374 [Byte1]: 32
7822 22:55:50.573586
7823 22:55:50.573669 Set Vref, RX VrefLevel [Byte0]: 33
7824 22:55:50.576879 [Byte1]: 33
7825 22:55:50.581150
7826 22:55:50.581232 Set Vref, RX VrefLevel [Byte0]: 34
7827 22:55:50.584526 [Byte1]: 34
7828 22:55:50.588790
7829 22:55:50.588872 Set Vref, RX VrefLevel [Byte0]: 35
7830 22:55:50.592344 [Byte1]: 35
7831 22:55:50.596143
7832 22:55:50.596226 Set Vref, RX VrefLevel [Byte0]: 36
7833 22:55:50.599657 [Byte1]: 36
7834 22:55:50.604182
7835 22:55:50.604264 Set Vref, RX VrefLevel [Byte0]: 37
7836 22:55:50.607570 [Byte1]: 37
7837 22:55:50.611448
7838 22:55:50.611531 Set Vref, RX VrefLevel [Byte0]: 38
7839 22:55:50.614772 [Byte1]: 38
7840 22:55:50.619199
7841 22:55:50.619283 Set Vref, RX VrefLevel [Byte0]: 39
7842 22:55:50.622399 [Byte1]: 39
7843 22:55:50.626812
7844 22:55:50.626894 Set Vref, RX VrefLevel [Byte0]: 40
7845 22:55:50.629913 [Byte1]: 40
7846 22:55:50.634472
7847 22:55:50.634555 Set Vref, RX VrefLevel [Byte0]: 41
7848 22:55:50.637410 [Byte1]: 41
7849 22:55:50.641930
7850 22:55:50.642013 Set Vref, RX VrefLevel [Byte0]: 42
7851 22:55:50.645292 [Byte1]: 42
7852 22:55:50.649784
7853 22:55:50.649867 Set Vref, RX VrefLevel [Byte0]: 43
7854 22:55:50.653313 [Byte1]: 43
7855 22:55:50.657581
7856 22:55:50.657664 Set Vref, RX VrefLevel [Byte0]: 44
7857 22:55:50.660409 [Byte1]: 44
7858 22:55:50.664784
7859 22:55:50.664867 Set Vref, RX VrefLevel [Byte0]: 45
7860 22:55:50.667976 [Byte1]: 45
7861 22:55:50.672390
7862 22:55:50.672472 Set Vref, RX VrefLevel [Byte0]: 46
7863 22:55:50.675607 [Byte1]: 46
7864 22:55:50.679886
7865 22:55:50.679969 Set Vref, RX VrefLevel [Byte0]: 47
7866 22:55:50.683319 [Byte1]: 47
7867 22:55:50.687424
7868 22:55:50.687506 Set Vref, RX VrefLevel [Byte0]: 48
7869 22:55:50.691275 [Byte1]: 48
7870 22:55:50.695519
7871 22:55:50.695601 Set Vref, RX VrefLevel [Byte0]: 49
7872 22:55:50.698338 [Byte1]: 49
7873 22:55:50.702706
7874 22:55:50.702789 Set Vref, RX VrefLevel [Byte0]: 50
7875 22:55:50.705945 [Byte1]: 50
7876 22:55:50.710582
7877 22:55:50.710665 Set Vref, RX VrefLevel [Byte0]: 51
7878 22:55:50.713753 [Byte1]: 51
7879 22:55:50.717968
7880 22:55:50.718050 Set Vref, RX VrefLevel [Byte0]: 52
7881 22:55:50.721548 [Byte1]: 52
7882 22:55:50.725634
7883 22:55:50.725717 Set Vref, RX VrefLevel [Byte0]: 53
7884 22:55:50.728955 [Byte1]: 53
7885 22:55:50.733335
7886 22:55:50.733417 Set Vref, RX VrefLevel [Byte0]: 54
7887 22:55:50.736882 [Byte1]: 54
7888 22:55:50.740713
7889 22:55:50.740797 Set Vref, RX VrefLevel [Byte0]: 55
7890 22:55:50.744024 [Byte1]: 55
7891 22:55:50.748714
7892 22:55:50.748797 Set Vref, RX VrefLevel [Byte0]: 56
7893 22:55:50.751849 [Byte1]: 56
7894 22:55:50.755907
7895 22:55:50.755990 Set Vref, RX VrefLevel [Byte0]: 57
7896 22:55:50.760212 [Byte1]: 57
7897 22:55:50.764389
7898 22:55:50.764472 Set Vref, RX VrefLevel [Byte0]: 58
7899 22:55:50.767365 [Byte1]: 58
7900 22:55:50.771829
7901 22:55:50.771912 Set Vref, RX VrefLevel [Byte0]: 59
7902 22:55:50.774356 [Byte1]: 59
7903 22:55:50.778946
7904 22:55:50.779029 Set Vref, RX VrefLevel [Byte0]: 60
7905 22:55:50.782168 [Byte1]: 60
7906 22:55:50.786769
7907 22:55:50.786852 Set Vref, RX VrefLevel [Byte0]: 61
7908 22:55:50.789961 [Byte1]: 61
7909 22:55:50.794478
7910 22:55:50.794561 Set Vref, RX VrefLevel [Byte0]: 62
7911 22:55:50.797349 [Byte1]: 62
7912 22:55:50.801695
7913 22:55:50.801778 Set Vref, RX VrefLevel [Byte0]: 63
7914 22:55:50.805103 [Byte1]: 63
7915 22:55:50.810197
7916 22:55:50.810280 Set Vref, RX VrefLevel [Byte0]: 64
7917 22:55:50.812685 [Byte1]: 64
7918 22:55:50.817517
7919 22:55:50.817600 Set Vref, RX VrefLevel [Byte0]: 65
7920 22:55:50.820580 [Byte1]: 65
7921 22:55:50.824703
7922 22:55:50.824785 Set Vref, RX VrefLevel [Byte0]: 66
7923 22:55:50.828624 [Byte1]: 66
7924 22:55:50.832137
7925 22:55:50.832220 Set Vref, RX VrefLevel [Byte0]: 67
7926 22:55:50.835786 [Byte1]: 67
7927 22:55:50.840269
7928 22:55:50.840352 Set Vref, RX VrefLevel [Byte0]: 68
7929 22:55:50.842986 [Byte1]: 68
7930 22:55:50.847463
7931 22:55:50.847546 Set Vref, RX VrefLevel [Byte0]: 69
7932 22:55:50.850972 [Byte1]: 69
7933 22:55:50.855308
7934 22:55:50.855391 Set Vref, RX VrefLevel [Byte0]: 70
7935 22:55:50.858577 [Byte1]: 70
7936 22:55:50.862598
7937 22:55:50.862680 Set Vref, RX VrefLevel [Byte0]: 71
7938 22:55:50.865914 [Byte1]: 71
7939 22:55:50.870892
7940 22:55:50.870974 Set Vref, RX VrefLevel [Byte0]: 72
7941 22:55:50.873403 [Byte1]: 72
7942 22:55:50.877671
7943 22:55:50.877754 Set Vref, RX VrefLevel [Byte0]: 73
7944 22:55:50.881001 [Byte1]: 73
7945 22:55:50.885603
7946 22:55:50.885686 Set Vref, RX VrefLevel [Byte0]: 74
7947 22:55:50.888667 [Byte1]: 74
7948 22:55:50.893193
7949 22:55:50.893276 Set Vref, RX VrefLevel [Byte0]: 75
7950 22:55:50.896671 [Byte1]: 75
7951 22:55:50.900945
7952 22:55:50.901027 Final RX Vref Byte 0 = 62 to rank0
7953 22:55:50.903830 Final RX Vref Byte 1 = 59 to rank0
7954 22:55:50.907497 Final RX Vref Byte 0 = 62 to rank1
7955 22:55:50.910832 Final RX Vref Byte 1 = 59 to rank1==
7956 22:55:50.913859 Dram Type= 6, Freq= 0, CH_0, rank 0
7957 22:55:50.920569 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7958 22:55:50.920653 ==
7959 22:55:50.920720 DQS Delay:
7960 22:55:50.923697 DQS0 = 0, DQS1 = 0
7961 22:55:50.923780 DQM Delay:
7962 22:55:50.923847 DQM0 = 129, DQM1 = 124
7963 22:55:50.926941 DQ Delay:
7964 22:55:50.930359 DQ0 =130, DQ1 =130, DQ2 =126, DQ3 =124
7965 22:55:50.933909 DQ4 =132, DQ5 =120, DQ6 =138, DQ7 =136
7966 22:55:50.936867 DQ8 =112, DQ9 =112, DQ10 =124, DQ11 =120
7967 22:55:50.940326 DQ12 =132, DQ13 =128, DQ14 =134, DQ15 =132
7968 22:55:50.940409
7969 22:55:50.940475
7970 22:55:50.940535
7971 22:55:50.943706 [DramC_TX_OE_Calibration] TA2
7972 22:55:50.946992 Original DQ_B0 (3 6) =30, OEN = 27
7973 22:55:50.950005 Original DQ_B1 (3 6) =30, OEN = 27
7974 22:55:50.953925 24, 0x0, End_B0=24 End_B1=24
7975 22:55:50.956870 25, 0x0, End_B0=25 End_B1=25
7976 22:55:50.956954 26, 0x0, End_B0=26 End_B1=26
7977 22:55:50.959810 27, 0x0, End_B0=27 End_B1=27
7978 22:55:50.963104 28, 0x0, End_B0=28 End_B1=28
7979 22:55:50.966752 29, 0x0, End_B0=29 End_B1=29
7980 22:55:50.966837 30, 0x0, End_B0=30 End_B1=30
7981 22:55:50.970409 31, 0x4141, End_B0=30 End_B1=30
7982 22:55:50.973171 Byte0 end_step=30 best_step=27
7983 22:55:50.977211 Byte1 end_step=30 best_step=27
7984 22:55:50.979960 Byte0 TX OE(2T, 0.5T) = (3, 3)
7985 22:55:50.983336 Byte1 TX OE(2T, 0.5T) = (3, 3)
7986 22:55:50.983419
7987 22:55:50.983484
7988 22:55:50.989534 [DQSOSCAuto] RK0, (LSB)MR18= 0x1512, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 399 ps
7989 22:55:50.993108 CH0 RK0: MR19=303, MR18=1512
7990 22:55:50.999880 CH0_RK0: MR19=0x303, MR18=0x1512, DQSOSC=399, MR23=63, INC=23, DEC=15
7991 22:55:50.999964
7992 22:55:51.002782 ----->DramcWriteLeveling(PI) begin...
7993 22:55:51.002866 ==
7994 22:55:51.006424 Dram Type= 6, Freq= 0, CH_0, rank 1
7995 22:55:51.009477 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7996 22:55:51.009561 ==
7997 22:55:51.012893 Write leveling (Byte 0): 33 => 33
7998 22:55:51.016211 Write leveling (Byte 1): 23 => 23
7999 22:55:51.019408 DramcWriteLeveling(PI) end<-----
8000 22:55:51.019490
8001 22:55:51.019556 ==
8002 22:55:51.022545 Dram Type= 6, Freq= 0, CH_0, rank 1
8003 22:55:51.025946 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8004 22:55:51.029419 ==
8005 22:55:51.029501 [Gating] SW mode calibration
8006 22:55:51.039030 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8007 22:55:51.042462 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8008 22:55:51.046033 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8009 22:55:51.052503 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8010 22:55:51.055327 1 4 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8011 22:55:51.064006 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8012 22:55:51.065394 1 4 16 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
8013 22:55:51.069130 1 4 20 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
8014 22:55:51.072375 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8015 22:55:51.078915 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8016 22:55:51.081844 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8017 22:55:51.085116 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8018 22:55:51.091664 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8019 22:55:51.095531 1 5 12 | B1->B0 | 3434 2626 | 1 0 | (1 1) (0 0)
8020 22:55:51.101510 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8021 22:55:51.105206 1 5 20 | B1->B0 | 2828 2323 | 0 0 | (1 0) (0 0)
8022 22:55:51.108028 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8023 22:55:51.114793 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8024 22:55:51.117948 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8025 22:55:51.121174 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8026 22:55:51.127773 1 6 8 | B1->B0 | 2323 3a3a | 0 0 | (0 0) (0 0)
8027 22:55:51.131293 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8028 22:55:51.134619 1 6 16 | B1->B0 | 2e2e 4646 | 0 0 | (1 1) (0 0)
8029 22:55:51.140995 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8030 22:55:51.144112 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8031 22:55:51.147717 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8032 22:55:51.153935 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8033 22:55:51.157406 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8034 22:55:51.161045 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8035 22:55:51.167136 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8036 22:55:51.170391 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8037 22:55:51.173884 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8038 22:55:51.180314 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8039 22:55:51.183942 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8040 22:55:51.187295 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8041 22:55:51.193612 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8042 22:55:51.196740 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8043 22:55:51.200296 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8044 22:55:51.206977 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8045 22:55:51.210092 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8046 22:55:51.213364 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8047 22:55:51.220267 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8048 22:55:51.223447 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8049 22:55:51.227347 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8050 22:55:51.233273 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8051 22:55:51.236645 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8052 22:55:51.239755 Total UI for P1: 0, mck2ui 16
8053 22:55:51.243080 best dqsien dly found for B0: ( 1, 9, 6)
8054 22:55:51.246229 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8055 22:55:51.253305 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8056 22:55:51.256189 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8057 22:55:51.259872 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8058 22:55:51.263059 Total UI for P1: 0, mck2ui 16
8059 22:55:51.266224 best dqsien dly found for B1: ( 1, 9, 20)
8060 22:55:51.269536 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8061 22:55:51.273024 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
8062 22:55:51.273100
8063 22:55:51.275933 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8064 22:55:51.283786 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
8065 22:55:51.283869 [Gating] SW calibration Done
8066 22:55:51.283935 ==
8067 22:55:51.286104 Dram Type= 6, Freq= 0, CH_0, rank 1
8068 22:55:51.292591 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8069 22:55:51.292691 ==
8070 22:55:51.292773 RX Vref Scan: 0
8071 22:55:51.292867
8072 22:55:51.295684 RX Vref 0 -> 0, step: 1
8073 22:55:51.295791
8074 22:55:51.298914 RX Delay 0 -> 252, step: 8
8075 22:55:51.302119 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8076 22:55:51.306274 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8077 22:55:51.308784 iDelay=200, Bit 2, Center 127 (80 ~ 175) 96
8078 22:55:51.315579 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8079 22:55:51.319148 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8080 22:55:51.322151 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8081 22:55:51.325552 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8082 22:55:51.329703 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8083 22:55:51.335417 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8084 22:55:51.338467 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8085 22:55:51.341905 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8086 22:55:51.345272 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8087 22:55:51.351965 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8088 22:55:51.354872 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8089 22:55:51.358327 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8090 22:55:51.361639 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8091 22:55:51.361766 ==
8092 22:55:51.364985 Dram Type= 6, Freq= 0, CH_0, rank 1
8093 22:55:51.371221 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8094 22:55:51.371322 ==
8095 22:55:51.371419 DQS Delay:
8096 22:55:51.374715 DQS0 = 0, DQS1 = 0
8097 22:55:51.374814 DQM Delay:
8098 22:55:51.374912 DQM0 = 131, DQM1 = 127
8099 22:55:51.378016 DQ Delay:
8100 22:55:51.381504 DQ0 =127, DQ1 =135, DQ2 =127, DQ3 =127
8101 22:55:51.384764 DQ4 =131, DQ5 =119, DQ6 =143, DQ7 =143
8102 22:55:51.387801 DQ8 =119, DQ9 =111, DQ10 =131, DQ11 =119
8103 22:55:51.391501 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8104 22:55:51.391601
8105 22:55:51.391699
8106 22:55:51.391789 ==
8107 22:55:51.394480 Dram Type= 6, Freq= 0, CH_0, rank 1
8108 22:55:51.401208 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8109 22:55:51.401307 ==
8110 22:55:51.401405
8111 22:55:51.401498
8112 22:55:51.401571 TX Vref Scan disable
8113 22:55:51.404300 == TX Byte 0 ==
8114 22:55:51.407807 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8115 22:55:51.414347 Update DQM dly =988 (3 ,6, 28) DQM OEN =(3 ,3)
8116 22:55:51.414446 == TX Byte 1 ==
8117 22:55:51.417308 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8118 22:55:51.423911 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8119 22:55:51.424040 ==
8120 22:55:51.427540 Dram Type= 6, Freq= 0, CH_0, rank 1
8121 22:55:51.430352 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8122 22:55:51.430450 ==
8123 22:55:51.444166
8124 22:55:51.447848 TX Vref early break, caculate TX vref
8125 22:55:51.451234 TX Vref=16, minBit 8, minWin=22, winSum=379
8126 22:55:51.454074 TX Vref=18, minBit 9, minWin=23, winSum=387
8127 22:55:51.457457 TX Vref=20, minBit 2, minWin=24, winSum=396
8128 22:55:51.460839 TX Vref=22, minBit 9, minWin=24, winSum=406
8129 22:55:51.463906 TX Vref=24, minBit 1, minWin=25, winSum=414
8130 22:55:51.470706 TX Vref=26, minBit 4, minWin=25, winSum=417
8131 22:55:51.473787 TX Vref=28, minBit 3, minWin=25, winSum=417
8132 22:55:51.477597 TX Vref=30, minBit 1, minWin=25, winSum=415
8133 22:55:51.480846 TX Vref=32, minBit 0, minWin=25, winSum=409
8134 22:55:51.483702 TX Vref=34, minBit 8, minWin=23, winSum=393
8135 22:55:51.490270 [TxChooseVref] Worse bit 4, Min win 25, Win sum 417, Final Vref 26
8136 22:55:51.490355
8137 22:55:51.493554 Final TX Range 0 Vref 26
8138 22:55:51.493654
8139 22:55:51.493752 ==
8140 22:55:51.497361 Dram Type= 6, Freq= 0, CH_0, rank 1
8141 22:55:51.500409 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8142 22:55:51.500511 ==
8143 22:55:51.500579
8144 22:55:51.500642
8145 22:55:51.503683 TX Vref Scan disable
8146 22:55:51.510306 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8147 22:55:51.510405 == TX Byte 0 ==
8148 22:55:51.513144 u2DelayCellOfst[0]=10 cells (3 PI)
8149 22:55:51.516661 u2DelayCellOfst[1]=14 cells (4 PI)
8150 22:55:51.519966 u2DelayCellOfst[2]=7 cells (2 PI)
8151 22:55:51.522998 u2DelayCellOfst[3]=7 cells (2 PI)
8152 22:55:51.526683 u2DelayCellOfst[4]=7 cells (2 PI)
8153 22:55:51.529533 u2DelayCellOfst[5]=0 cells (0 PI)
8154 22:55:51.532982 u2DelayCellOfst[6]=14 cells (4 PI)
8155 22:55:51.536446 u2DelayCellOfst[7]=14 cells (4 PI)
8156 22:55:51.539418 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
8157 22:55:51.543062 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8158 22:55:51.546291 == TX Byte 1 ==
8159 22:55:51.549303 u2DelayCellOfst[8]=3 cells (1 PI)
8160 22:55:51.552476 u2DelayCellOfst[9]=0 cells (0 PI)
8161 22:55:51.555900 u2DelayCellOfst[10]=7 cells (2 PI)
8162 22:55:51.559177 u2DelayCellOfst[11]=3 cells (1 PI)
8163 22:55:51.562554 u2DelayCellOfst[12]=10 cells (3 PI)
8164 22:55:51.562637 u2DelayCellOfst[13]=10 cells (3 PI)
8165 22:55:51.565667 u2DelayCellOfst[14]=14 cells (4 PI)
8166 22:55:51.569222 u2DelayCellOfst[15]=10 cells (3 PI)
8167 22:55:51.575891 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8168 22:55:51.579532 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8169 22:55:51.582172 DramC Write-DBI on
8170 22:55:51.582255 ==
8171 22:55:51.585803 Dram Type= 6, Freq= 0, CH_0, rank 1
8172 22:55:51.589506 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8173 22:55:51.589590 ==
8174 22:55:51.589656
8175 22:55:51.589717
8176 22:55:51.592421 TX Vref Scan disable
8177 22:55:51.592504 == TX Byte 0 ==
8178 22:55:51.599159 Update DQM dly =732 (2 ,6, 28) DQM OEN =(3 ,3)
8179 22:55:51.599242 == TX Byte 1 ==
8180 22:55:51.602217 Update DQM dly =719 (2 ,6, 15) DQM OEN =(3 ,3)
8181 22:55:51.605829 DramC Write-DBI off
8182 22:55:51.605912
8183 22:55:51.605978 [DATLAT]
8184 22:55:51.608745 Freq=1600, CH0 RK1
8185 22:55:51.608829
8186 22:55:51.608895 DATLAT Default: 0xf
8187 22:55:51.612225 0, 0xFFFF, sum = 0
8188 22:55:51.612310 1, 0xFFFF, sum = 0
8189 22:55:51.615436 2, 0xFFFF, sum = 0
8190 22:55:51.618693 3, 0xFFFF, sum = 0
8191 22:55:51.618778 4, 0xFFFF, sum = 0
8192 22:55:51.621853 5, 0xFFFF, sum = 0
8193 22:55:51.621938 6, 0xFFFF, sum = 0
8194 22:55:51.625139 7, 0xFFFF, sum = 0
8195 22:55:51.625223 8, 0xFFFF, sum = 0
8196 22:55:51.628338 9, 0xFFFF, sum = 0
8197 22:55:51.628423 10, 0xFFFF, sum = 0
8198 22:55:51.632019 11, 0xFFFF, sum = 0
8199 22:55:51.632126 12, 0xFFFF, sum = 0
8200 22:55:51.635375 13, 0xFFFF, sum = 0
8201 22:55:51.635459 14, 0x0, sum = 1
8202 22:55:51.638443 15, 0x0, sum = 2
8203 22:55:51.638528 16, 0x0, sum = 3
8204 22:55:51.642129 17, 0x0, sum = 4
8205 22:55:51.642244 best_step = 15
8206 22:55:51.642311
8207 22:55:51.642372 ==
8208 22:55:51.644942 Dram Type= 6, Freq= 0, CH_0, rank 1
8209 22:55:51.651334 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8210 22:55:51.651419 ==
8211 22:55:51.651488 RX Vref Scan: 0
8212 22:55:51.651565
8213 22:55:51.654750 RX Vref 0 -> 0, step: 1
8214 22:55:51.654847
8215 22:55:51.657930 RX Delay 11 -> 252, step: 4
8216 22:55:51.661507 iDelay=191, Bit 0, Center 126 (75 ~ 178) 104
8217 22:55:51.664605 iDelay=191, Bit 1, Center 130 (79 ~ 182) 104
8218 22:55:51.668248 iDelay=191, Bit 2, Center 124 (75 ~ 174) 100
8219 22:55:51.674611 iDelay=191, Bit 3, Center 126 (75 ~ 178) 104
8220 22:55:51.677981 iDelay=191, Bit 4, Center 130 (83 ~ 178) 96
8221 22:55:51.681165 iDelay=191, Bit 5, Center 120 (67 ~ 174) 108
8222 22:55:51.684962 iDelay=191, Bit 6, Center 138 (87 ~ 190) 104
8223 22:55:51.687771 iDelay=191, Bit 7, Center 134 (83 ~ 186) 104
8224 22:55:51.694233 iDelay=191, Bit 8, Center 114 (63 ~ 166) 104
8225 22:55:51.697856 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8226 22:55:51.700902 iDelay=191, Bit 10, Center 124 (71 ~ 178) 108
8227 22:55:51.704035 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8228 22:55:51.710540 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8229 22:55:51.714229 iDelay=191, Bit 13, Center 130 (79 ~ 182) 104
8230 22:55:51.717371 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8231 22:55:51.720557 iDelay=191, Bit 15, Center 132 (79 ~ 186) 108
8232 22:55:51.720640 ==
8233 22:55:51.724004 Dram Type= 6, Freq= 0, CH_0, rank 1
8234 22:55:51.730437 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8235 22:55:51.730521 ==
8236 22:55:51.730588 DQS Delay:
8237 22:55:51.733904 DQS0 = 0, DQS1 = 0
8238 22:55:51.733987 DQM Delay:
8239 22:55:51.734054 DQM0 = 128, DQM1 = 124
8240 22:55:51.737146 DQ Delay:
8241 22:55:51.740630 DQ0 =126, DQ1 =130, DQ2 =124, DQ3 =126
8242 22:55:51.743504 DQ4 =130, DQ5 =120, DQ6 =138, DQ7 =134
8243 22:55:51.746891 DQ8 =114, DQ9 =110, DQ10 =124, DQ11 =118
8244 22:55:51.751155 DQ12 =128, DQ13 =130, DQ14 =136, DQ15 =132
8245 22:55:51.751238
8246 22:55:51.751304
8247 22:55:51.751365
8248 22:55:51.753876 [DramC_TX_OE_Calibration] TA2
8249 22:55:51.757112 Original DQ_B0 (3 6) =30, OEN = 27
8250 22:55:51.760058 Original DQ_B1 (3 6) =30, OEN = 27
8251 22:55:51.763643 24, 0x0, End_B0=24 End_B1=24
8252 22:55:51.766662 25, 0x0, End_B0=25 End_B1=25
8253 22:55:51.766746 26, 0x0, End_B0=26 End_B1=26
8254 22:55:51.770147 27, 0x0, End_B0=27 End_B1=27
8255 22:55:51.773240 28, 0x0, End_B0=28 End_B1=28
8256 22:55:51.776468 29, 0x0, End_B0=29 End_B1=29
8257 22:55:51.776552 30, 0x0, End_B0=30 End_B1=30
8258 22:55:51.779798 31, 0x4545, End_B0=30 End_B1=30
8259 22:55:51.783417 Byte0 end_step=30 best_step=27
8260 22:55:51.786464 Byte1 end_step=30 best_step=27
8261 22:55:51.789968 Byte0 TX OE(2T, 0.5T) = (3, 3)
8262 22:55:51.793202 Byte1 TX OE(2T, 0.5T) = (3, 3)
8263 22:55:51.793285
8264 22:55:51.793351
8265 22:55:51.799685 [DQSOSCAuto] RK1, (LSB)MR18= 0x1310, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 400 ps
8266 22:55:51.802810 CH0 RK1: MR19=303, MR18=1310
8267 22:55:51.809557 CH0_RK1: MR19=0x303, MR18=0x1310, DQSOSC=400, MR23=63, INC=23, DEC=15
8268 22:55:51.812686 [RxdqsGatingPostProcess] freq 1600
8269 22:55:51.819472 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8270 22:55:51.819578 best DQS0 dly(2T, 0.5T) = (1, 1)
8271 22:55:51.822447 best DQS1 dly(2T, 0.5T) = (1, 1)
8272 22:55:51.826083 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8273 22:55:51.829227 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8274 22:55:51.832491 best DQS0 dly(2T, 0.5T) = (1, 1)
8275 22:55:51.836013 best DQS1 dly(2T, 0.5T) = (1, 1)
8276 22:55:51.839353 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8277 22:55:51.842544 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8278 22:55:51.845707 Pre-setting of DQS Precalculation
8279 22:55:51.848972 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8280 22:55:51.852531 ==
8281 22:55:51.855926 Dram Type= 6, Freq= 0, CH_1, rank 0
8282 22:55:51.858853 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8283 22:55:51.858956 ==
8284 22:55:51.862107 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8285 22:55:51.868595 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8286 22:55:51.871799 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8287 22:55:51.879115 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8288 22:55:51.887022 [CA 0] Center 41 (12~71) winsize 60
8289 22:55:51.890068 [CA 1] Center 41 (11~72) winsize 62
8290 22:55:51.893507 [CA 2] Center 38 (9~67) winsize 59
8291 22:55:51.896880 [CA 3] Center 37 (8~66) winsize 59
8292 22:55:51.899936 [CA 4] Center 37 (7~67) winsize 61
8293 22:55:51.903940 [CA 5] Center 36 (6~66) winsize 61
8294 22:55:51.904052
8295 22:55:51.906636 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8296 22:55:51.906734
8297 22:55:51.913126 [CATrainingPosCal] consider 1 rank data
8298 22:55:51.913205 u2DelayCellTimex100 = 271/100 ps
8299 22:55:51.919369 CA0 delay=41 (12~71),Diff = 5 PI (18 cell)
8300 22:55:51.923177 CA1 delay=41 (11~72),Diff = 5 PI (18 cell)
8301 22:55:51.926044 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8302 22:55:51.929394 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8303 22:55:51.932999 CA4 delay=37 (7~67),Diff = 1 PI (3 cell)
8304 22:55:51.936221 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
8305 22:55:51.936292
8306 22:55:51.939238 CA PerBit enable=1, Macro0, CA PI delay=36
8307 22:55:51.939343
8308 22:55:51.943222 [CBTSetCACLKResult] CA Dly = 36
8309 22:55:51.946034 CS Dly: 7 (0~38)
8310 22:55:51.949043 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8311 22:55:51.952183 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8312 22:55:51.952289 ==
8313 22:55:51.956013 Dram Type= 6, Freq= 0, CH_1, rank 1
8314 22:55:51.962128 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8315 22:55:51.962213 ==
8316 22:55:51.965549 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8317 22:55:51.972026 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8318 22:55:51.975166 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8319 22:55:51.981621 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8320 22:55:51.989999 [CA 0] Center 42 (12~72) winsize 61
8321 22:55:51.993207 [CA 1] Center 42 (12~72) winsize 61
8322 22:55:51.997874 [CA 2] Center 38 (9~68) winsize 60
8323 22:55:51.999753 [CA 3] Center 37 (7~67) winsize 61
8324 22:55:52.003325 [CA 4] Center 37 (8~67) winsize 60
8325 22:55:52.006556 [CA 5] Center 37 (7~67) winsize 61
8326 22:55:52.006655
8327 22:55:52.009502 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8328 22:55:52.009599
8329 22:55:52.016006 [CATrainingPosCal] consider 2 rank data
8330 22:55:52.016126 u2DelayCellTimex100 = 271/100 ps
8331 22:55:52.022846 CA0 delay=41 (12~71),Diff = 5 PI (18 cell)
8332 22:55:52.026085 CA1 delay=42 (12~72),Diff = 6 PI (21 cell)
8333 22:55:52.029318 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8334 22:55:52.032947 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8335 22:55:52.036230 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8336 22:55:52.039276 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8337 22:55:52.039359
8338 22:55:52.042925 CA PerBit enable=1, Macro0, CA PI delay=36
8339 22:55:52.042999
8340 22:55:52.046120 [CBTSetCACLKResult] CA Dly = 36
8341 22:55:52.049329 CS Dly: 9 (0~42)
8342 22:55:52.052494 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8343 22:55:52.056497 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8344 22:55:52.056570
8345 22:55:52.059558 ----->DramcWriteLeveling(PI) begin...
8346 22:55:52.059632 ==
8347 22:55:52.062620 Dram Type= 6, Freq= 0, CH_1, rank 0
8348 22:55:52.069062 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8349 22:55:52.069143 ==
8350 22:55:52.072149 Write leveling (Byte 0): 24 => 24
8351 22:55:52.075762 Write leveling (Byte 1): 26 => 26
8352 22:55:52.075842 DramcWriteLeveling(PI) end<-----
8353 22:55:52.078706
8354 22:55:52.078794 ==
8355 22:55:52.082695 Dram Type= 6, Freq= 0, CH_1, rank 0
8356 22:55:52.085153 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8357 22:55:52.085223 ==
8358 22:55:52.089049 [Gating] SW mode calibration
8359 22:55:52.095420 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8360 22:55:52.098986 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8361 22:55:52.104967 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8362 22:55:52.108161 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8363 22:55:52.115104 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8364 22:55:52.118218 1 4 12 | B1->B0 | 2323 3232 | 1 1 | (0 0) (1 1)
8365 22:55:52.121686 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8366 22:55:52.125295 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8367 22:55:52.131476 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8368 22:55:52.134745 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8369 22:55:52.141460 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8370 22:55:52.144645 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8371 22:55:52.147847 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 0)
8372 22:55:52.154745 1 5 12 | B1->B0 | 2e2e 2424 | 1 0 | (1 0) (1 0)
8373 22:55:52.157605 1 5 16 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
8374 22:55:52.160970 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8375 22:55:52.167508 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8376 22:55:52.171638 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8377 22:55:52.174318 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8378 22:55:52.181132 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8379 22:55:52.183901 1 6 8 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
8380 22:55:52.187397 1 6 12 | B1->B0 | 3535 4646 | 1 0 | (0 0) (0 0)
8381 22:55:52.193716 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8382 22:55:52.197240 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8383 22:55:52.200664 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8384 22:55:52.206940 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8385 22:55:52.210457 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8386 22:55:52.213506 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8387 22:55:52.220162 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8388 22:55:52.223815 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8389 22:55:52.226770 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8390 22:55:52.233356 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8391 22:55:52.236740 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8392 22:55:52.239583 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8393 22:55:52.246789 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8394 22:55:52.249665 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8395 22:55:52.252947 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8396 22:55:52.259970 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8397 22:55:52.262851 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8398 22:55:52.266208 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8399 22:55:52.272634 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8400 22:55:52.276186 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8401 22:55:52.279642 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8402 22:55:52.286133 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8403 22:55:52.289762 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8404 22:55:52.292508 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8405 22:55:52.299307 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8406 22:55:52.299390 Total UI for P1: 0, mck2ui 16
8407 22:55:52.305897 best dqsien dly found for B0: ( 1, 9, 10)
8408 22:55:52.309241 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8409 22:55:52.312733 Total UI for P1: 0, mck2ui 16
8410 22:55:52.315742 best dqsien dly found for B1: ( 1, 9, 14)
8411 22:55:52.318936 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8412 22:55:52.322335 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8413 22:55:52.322407
8414 22:55:52.325555 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8415 22:55:52.329114 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8416 22:55:52.332151 [Gating] SW calibration Done
8417 22:55:52.332225 ==
8418 22:55:52.335474 Dram Type= 6, Freq= 0, CH_1, rank 0
8419 22:55:52.338769 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8420 22:55:52.342445 ==
8421 22:55:52.342520 RX Vref Scan: 0
8422 22:55:52.342581
8423 22:55:52.345691 RX Vref 0 -> 0, step: 1
8424 22:55:52.345764
8425 22:55:52.345826 RX Delay 0 -> 252, step: 8
8426 22:55:52.352348 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8427 22:55:52.355667 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8428 22:55:52.359485 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8429 22:55:52.362516 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8430 22:55:52.365992 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8431 22:55:52.372162 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8432 22:55:52.376129 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8433 22:55:52.378705 iDelay=200, Bit 7, Center 131 (80 ~ 183) 104
8434 22:55:52.382159 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8435 22:55:52.388457 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8436 22:55:52.391702 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8437 22:55:52.395138 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8438 22:55:52.398291 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8439 22:55:52.402033 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8440 22:55:52.408148 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8441 22:55:52.411707 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8442 22:55:52.411788 ==
8443 22:55:52.415086 Dram Type= 6, Freq= 0, CH_1, rank 0
8444 22:55:52.418173 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8445 22:55:52.418255 ==
8446 22:55:52.421558 DQS Delay:
8447 22:55:52.421639 DQS0 = 0, DQS1 = 0
8448 22:55:52.421704 DQM Delay:
8449 22:55:52.424453 DQM0 = 135, DQM1 = 128
8450 22:55:52.424534 DQ Delay:
8451 22:55:52.427866 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8452 22:55:52.434848 DQ4 =131, DQ5 =143, DQ6 =147, DQ7 =131
8453 22:55:52.437766 DQ8 =111, DQ9 =119, DQ10 =127, DQ11 =123
8454 22:55:52.441327 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =135
8455 22:55:52.441432
8456 22:55:52.441533
8457 22:55:52.441624 ==
8458 22:55:52.444423 Dram Type= 6, Freq= 0, CH_1, rank 0
8459 22:55:52.447560 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8460 22:55:52.447670 ==
8461 22:55:52.447764
8462 22:55:52.447852
8463 22:55:52.450809 TX Vref Scan disable
8464 22:55:52.454444 == TX Byte 0 ==
8465 22:55:52.457804 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8466 22:55:52.460927 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8467 22:55:52.463924 == TX Byte 1 ==
8468 22:55:52.467826 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8469 22:55:52.471041 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8470 22:55:52.471131 ==
8471 22:55:52.474011 Dram Type= 6, Freq= 0, CH_1, rank 0
8472 22:55:52.480557 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8473 22:55:52.480656 ==
8474 22:55:52.492964
8475 22:55:52.496198 TX Vref early break, caculate TX vref
8476 22:55:52.499606 TX Vref=16, minBit 8, minWin=21, winSum=369
8477 22:55:52.503326 TX Vref=18, minBit 8, minWin=22, winSum=377
8478 22:55:52.506249 TX Vref=20, minBit 8, minWin=23, winSum=386
8479 22:55:52.509666 TX Vref=22, minBit 8, minWin=23, winSum=400
8480 22:55:52.513074 TX Vref=24, minBit 8, minWin=24, winSum=407
8481 22:55:52.519255 TX Vref=26, minBit 9, minWin=24, winSum=415
8482 22:55:52.522879 TX Vref=28, minBit 8, minWin=25, winSum=418
8483 22:55:52.525875 TX Vref=30, minBit 9, minWin=24, winSum=414
8484 22:55:52.529308 TX Vref=32, minBit 0, minWin=25, winSum=410
8485 22:55:52.532344 TX Vref=34, minBit 0, minWin=23, winSum=397
8486 22:55:52.539559 TX Vref=36, minBit 0, minWin=23, winSum=387
8487 22:55:52.542032 [TxChooseVref] Worse bit 8, Min win 25, Win sum 418, Final Vref 28
8488 22:55:52.542117
8489 22:55:52.545589 Final TX Range 0 Vref 28
8490 22:55:52.545690
8491 22:55:52.545768 ==
8492 22:55:52.549018 Dram Type= 6, Freq= 0, CH_1, rank 0
8493 22:55:52.552145 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8494 22:55:52.555794 ==
8495 22:55:52.555875
8496 22:55:52.555939
8497 22:55:52.555998 TX Vref Scan disable
8498 22:55:52.562634 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8499 22:55:52.562715 == TX Byte 0 ==
8500 22:55:52.565475 u2DelayCellOfst[0]=14 cells (4 PI)
8501 22:55:52.568617 u2DelayCellOfst[1]=10 cells (3 PI)
8502 22:55:52.571863 u2DelayCellOfst[2]=0 cells (0 PI)
8503 22:55:52.575282 u2DelayCellOfst[3]=3 cells (1 PI)
8504 22:55:52.578708 u2DelayCellOfst[4]=7 cells (2 PI)
8505 22:55:52.582468 u2DelayCellOfst[5]=18 cells (5 PI)
8506 22:55:52.585068 u2DelayCellOfst[6]=18 cells (5 PI)
8507 22:55:52.589011 u2DelayCellOfst[7]=7 cells (2 PI)
8508 22:55:52.592208 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8509 22:55:52.595223 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8510 22:55:52.598615 == TX Byte 1 ==
8511 22:55:52.602316 u2DelayCellOfst[8]=0 cells (0 PI)
8512 22:55:52.605082 u2DelayCellOfst[9]=7 cells (2 PI)
8513 22:55:52.608229 u2DelayCellOfst[10]=10 cells (3 PI)
8514 22:55:52.611498 u2DelayCellOfst[11]=7 cells (2 PI)
8515 22:55:52.614802 u2DelayCellOfst[12]=14 cells (4 PI)
8516 22:55:52.618536 u2DelayCellOfst[13]=14 cells (4 PI)
8517 22:55:52.621584 u2DelayCellOfst[14]=18 cells (5 PI)
8518 22:55:52.621666 u2DelayCellOfst[15]=18 cells (5 PI)
8519 22:55:52.627881 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8520 22:55:52.631382 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8521 22:55:52.634764 DramC Write-DBI on
8522 22:55:52.634847 ==
8523 22:55:52.637752 Dram Type= 6, Freq= 0, CH_1, rank 0
8524 22:55:52.641370 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8525 22:55:52.641454 ==
8526 22:55:52.641520
8527 22:55:52.641581
8528 22:55:52.644362 TX Vref Scan disable
8529 22:55:52.644445 == TX Byte 0 ==
8530 22:55:52.651006 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8531 22:55:52.651093 == TX Byte 1 ==
8532 22:55:52.654530 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8533 22:55:52.657850 DramC Write-DBI off
8534 22:55:52.657934
8535 22:55:52.657999 [DATLAT]
8536 22:55:52.660944 Freq=1600, CH1 RK0
8537 22:55:52.661028
8538 22:55:52.661094 DATLAT Default: 0xf
8539 22:55:52.664227 0, 0xFFFF, sum = 0
8540 22:55:52.667877 1, 0xFFFF, sum = 0
8541 22:55:52.667961 2, 0xFFFF, sum = 0
8542 22:55:52.670719 3, 0xFFFF, sum = 0
8543 22:55:52.670810 4, 0xFFFF, sum = 0
8544 22:55:52.674060 5, 0xFFFF, sum = 0
8545 22:55:52.674160 6, 0xFFFF, sum = 0
8546 22:55:52.677128 7, 0xFFFF, sum = 0
8547 22:55:52.677226 8, 0xFFFF, sum = 0
8548 22:55:52.680713 9, 0xFFFF, sum = 0
8549 22:55:52.680798 10, 0xFFFF, sum = 0
8550 22:55:52.683852 11, 0xFFFF, sum = 0
8551 22:55:52.683937 12, 0xFFFF, sum = 0
8552 22:55:52.687378 13, 0xFFFF, sum = 0
8553 22:55:52.687463 14, 0x0, sum = 1
8554 22:55:52.690684 15, 0x0, sum = 2
8555 22:55:52.690770 16, 0x0, sum = 3
8556 22:55:52.693721 17, 0x0, sum = 4
8557 22:55:52.693805 best_step = 15
8558 22:55:52.693871
8559 22:55:52.693950 ==
8560 22:55:52.697071 Dram Type= 6, Freq= 0, CH_1, rank 0
8561 22:55:52.703450 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8562 22:55:52.703549 ==
8563 22:55:52.703616 RX Vref Scan: 1
8564 22:55:52.703678
8565 22:55:52.706959 Set Vref Range= 24 -> 127
8566 22:55:52.707042
8567 22:55:52.710420 RX Vref 24 -> 127, step: 1
8568 22:55:52.710504
8569 22:55:52.713830 RX Delay 11 -> 252, step: 4
8570 22:55:52.713945
8571 22:55:52.716976 Set Vref, RX VrefLevel [Byte0]: 24
8572 22:55:52.719960 [Byte1]: 24
8573 22:55:52.720051
8574 22:55:52.723942 Set Vref, RX VrefLevel [Byte0]: 25
8575 22:55:52.726795 [Byte1]: 25
8576 22:55:52.726893
8577 22:55:52.729966 Set Vref, RX VrefLevel [Byte0]: 26
8578 22:55:52.733417 [Byte1]: 26
8579 22:55:52.736671
8580 22:55:52.736756 Set Vref, RX VrefLevel [Byte0]: 27
8581 22:55:52.739748 [Byte1]: 27
8582 22:55:52.744243
8583 22:55:52.744325 Set Vref, RX VrefLevel [Byte0]: 28
8584 22:55:52.747363 [Byte1]: 28
8585 22:55:52.751766
8586 22:55:52.751913 Set Vref, RX VrefLevel [Byte0]: 29
8587 22:55:52.755205 [Byte1]: 29
8588 22:55:52.759549
8589 22:55:52.759679 Set Vref, RX VrefLevel [Byte0]: 30
8590 22:55:52.762478 [Byte1]: 30
8591 22:55:52.766966
8592 22:55:52.767049 Set Vref, RX VrefLevel [Byte0]: 31
8593 22:55:52.770374 [Byte1]: 31
8594 22:55:52.774881
8595 22:55:52.774963 Set Vref, RX VrefLevel [Byte0]: 32
8596 22:55:52.778579 [Byte1]: 32
8597 22:55:52.782506
8598 22:55:52.782589 Set Vref, RX VrefLevel [Byte0]: 33
8599 22:55:52.785404 [Byte1]: 33
8600 22:55:52.790067
8601 22:55:52.790150 Set Vref, RX VrefLevel [Byte0]: 34
8602 22:55:52.792919 [Byte1]: 34
8603 22:55:52.797506
8604 22:55:52.797589 Set Vref, RX VrefLevel [Byte0]: 35
8605 22:55:52.801002 [Byte1]: 35
8606 22:55:52.805294
8607 22:55:52.805376 Set Vref, RX VrefLevel [Byte0]: 36
8608 22:55:52.808491 [Byte1]: 36
8609 22:55:52.812974
8610 22:55:52.813057 Set Vref, RX VrefLevel [Byte0]: 37
8611 22:55:52.815992 [Byte1]: 37
8612 22:55:52.820418
8613 22:55:52.820500 Set Vref, RX VrefLevel [Byte0]: 38
8614 22:55:52.823296 [Byte1]: 38
8615 22:55:52.828084
8616 22:55:52.828181 Set Vref, RX VrefLevel [Byte0]: 39
8617 22:55:52.831116 [Byte1]: 39
8618 22:55:52.835264
8619 22:55:52.835347 Set Vref, RX VrefLevel [Byte0]: 40
8620 22:55:52.838646 [Byte1]: 40
8621 22:55:52.843141
8622 22:55:52.843224 Set Vref, RX VrefLevel [Byte0]: 41
8623 22:55:52.846212 [Byte1]: 41
8624 22:55:52.850794
8625 22:55:52.850892 Set Vref, RX VrefLevel [Byte0]: 42
8626 22:55:52.853705 [Byte1]: 42
8627 22:55:52.858593
8628 22:55:52.858679 Set Vref, RX VrefLevel [Byte0]: 43
8629 22:55:52.861279 [Byte1]: 43
8630 22:55:52.866105
8631 22:55:52.866202 Set Vref, RX VrefLevel [Byte0]: 44
8632 22:55:52.869087 [Byte1]: 44
8633 22:55:52.873537
8634 22:55:52.877136 Set Vref, RX VrefLevel [Byte0]: 45
8635 22:55:52.880132 [Byte1]: 45
8636 22:55:52.880215
8637 22:55:52.883978 Set Vref, RX VrefLevel [Byte0]: 46
8638 22:55:52.886556 [Byte1]: 46
8639 22:55:52.886639
8640 22:55:52.889923 Set Vref, RX VrefLevel [Byte0]: 47
8641 22:55:52.893106 [Byte1]: 47
8642 22:55:52.893210
8643 22:55:52.896991 Set Vref, RX VrefLevel [Byte0]: 48
8644 22:55:52.900439 [Byte1]: 48
8645 22:55:52.903785
8646 22:55:52.903867 Set Vref, RX VrefLevel [Byte0]: 49
8647 22:55:52.907155 [Byte1]: 49
8648 22:55:52.911385
8649 22:55:52.911469 Set Vref, RX VrefLevel [Byte0]: 50
8650 22:55:52.914914 [Byte1]: 50
8651 22:55:52.918962
8652 22:55:52.919044 Set Vref, RX VrefLevel [Byte0]: 51
8653 22:55:52.922548 [Byte1]: 51
8654 22:55:52.926935
8655 22:55:52.927018 Set Vref, RX VrefLevel [Byte0]: 52
8656 22:55:52.929989 [Byte1]: 52
8657 22:55:52.934524
8658 22:55:52.934606 Set Vref, RX VrefLevel [Byte0]: 53
8659 22:55:52.938032 [Byte1]: 53
8660 22:55:52.941968
8661 22:55:52.942051 Set Vref, RX VrefLevel [Byte0]: 54
8662 22:55:52.945309 [Byte1]: 54
8663 22:55:52.949382
8664 22:55:52.949465 Set Vref, RX VrefLevel [Byte0]: 55
8665 22:55:52.952728 [Byte1]: 55
8666 22:55:52.957453
8667 22:55:52.957536 Set Vref, RX VrefLevel [Byte0]: 56
8668 22:55:52.960320 [Byte1]: 56
8669 22:55:52.964754
8670 22:55:52.964853 Set Vref, RX VrefLevel [Byte0]: 57
8671 22:55:52.968388 [Byte1]: 57
8672 22:55:52.972241
8673 22:55:52.972345 Set Vref, RX VrefLevel [Byte0]: 58
8674 22:55:52.976059 [Byte1]: 58
8675 22:55:52.980352
8676 22:55:52.980435 Set Vref, RX VrefLevel [Byte0]: 59
8677 22:55:52.983879 [Byte1]: 59
8678 22:55:52.987647
8679 22:55:52.987730 Set Vref, RX VrefLevel [Byte0]: 60
8680 22:55:52.991223 [Byte1]: 60
8681 22:55:52.995152
8682 22:55:52.995235 Set Vref, RX VrefLevel [Byte0]: 61
8683 22:55:52.998963 [Byte1]: 61
8684 22:55:53.003236
8685 22:55:53.003319 Set Vref, RX VrefLevel [Byte0]: 62
8686 22:55:53.006456 [Byte1]: 62
8687 22:55:53.010301
8688 22:55:53.010385 Set Vref, RX VrefLevel [Byte0]: 63
8689 22:55:53.013654 [Byte1]: 63
8690 22:55:53.018208
8691 22:55:53.018290 Set Vref, RX VrefLevel [Byte0]: 64
8692 22:55:53.021870 [Byte1]: 64
8693 22:55:53.025969
8694 22:55:53.026094 Set Vref, RX VrefLevel [Byte0]: 65
8695 22:55:53.028933 [Byte1]: 65
8696 22:55:53.033390
8697 22:55:53.033502 Set Vref, RX VrefLevel [Byte0]: 66
8698 22:55:53.036762 [Byte1]: 66
8699 22:55:53.040880
8700 22:55:53.040969 Set Vref, RX VrefLevel [Byte0]: 67
8701 22:55:53.044636 [Byte1]: 67
8702 22:55:53.048470
8703 22:55:53.048545 Set Vref, RX VrefLevel [Byte0]: 68
8704 22:55:53.052130 [Byte1]: 68
8705 22:55:53.055965
8706 22:55:53.056068 Set Vref, RX VrefLevel [Byte0]: 69
8707 22:55:53.059738 [Byte1]: 69
8708 22:55:53.063616
8709 22:55:53.063719 Set Vref, RX VrefLevel [Byte0]: 70
8710 22:55:53.067019 [Byte1]: 70
8711 22:55:53.071418
8712 22:55:53.071523 Set Vref, RX VrefLevel [Byte0]: 71
8713 22:55:53.074589 [Byte1]: 71
8714 22:55:53.079414
8715 22:55:53.079517 Set Vref, RX VrefLevel [Byte0]: 72
8716 22:55:53.082288 [Byte1]: 72
8717 22:55:53.086478
8718 22:55:53.086584 Final RX Vref Byte 0 = 58 to rank0
8719 22:55:53.090194 Final RX Vref Byte 1 = 56 to rank0
8720 22:55:53.093269 Final RX Vref Byte 0 = 58 to rank1
8721 22:55:53.096720 Final RX Vref Byte 1 = 56 to rank1==
8722 22:55:53.099825 Dram Type= 6, Freq= 0, CH_1, rank 0
8723 22:55:53.106757 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8724 22:55:53.106865 ==
8725 22:55:53.106956 DQS Delay:
8726 22:55:53.107051 DQS0 = 0, DQS1 = 0
8727 22:55:53.110469 DQM Delay:
8728 22:55:53.110566 DQM0 = 132, DQM1 = 127
8729 22:55:53.112973 DQ Delay:
8730 22:55:53.116120 DQ0 =140, DQ1 =128, DQ2 =118, DQ3 =130
8731 22:55:53.119895 DQ4 =128, DQ5 =142, DQ6 =144, DQ7 =126
8732 22:55:53.123097 DQ8 =112, DQ9 =116, DQ10 =128, DQ11 =122
8733 22:55:53.126089 DQ12 =136, DQ13 =136, DQ14 =134, DQ15 =138
8734 22:55:53.126196
8735 22:55:53.126287
8736 22:55:53.126374
8737 22:55:53.129712 [DramC_TX_OE_Calibration] TA2
8738 22:55:53.132880 Original DQ_B0 (3 6) =30, OEN = 27
8739 22:55:53.136288 Original DQ_B1 (3 6) =30, OEN = 27
8740 22:55:53.139653 24, 0x0, End_B0=24 End_B1=24
8741 22:55:53.139750 25, 0x0, End_B0=25 End_B1=25
8742 22:55:53.142907 26, 0x0, End_B0=26 End_B1=26
8743 22:55:53.146249 27, 0x0, End_B0=27 End_B1=27
8744 22:55:53.149468 28, 0x0, End_B0=28 End_B1=28
8745 22:55:53.152360 29, 0x0, End_B0=29 End_B1=29
8746 22:55:53.152445 30, 0x0, End_B0=30 End_B1=30
8747 22:55:53.155967 31, 0x4141, End_B0=30 End_B1=30
8748 22:55:53.159088 Byte0 end_step=30 best_step=27
8749 22:55:53.162287 Byte1 end_step=30 best_step=27
8750 22:55:53.165544 Byte0 TX OE(2T, 0.5T) = (3, 3)
8751 22:55:53.169247 Byte1 TX OE(2T, 0.5T) = (3, 3)
8752 22:55:53.169352
8753 22:55:53.169417
8754 22:55:53.175931 [DQSOSCAuto] RK0, (LSB)MR18= 0xa14, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 404 ps
8755 22:55:53.178859 CH1 RK0: MR19=303, MR18=A14
8756 22:55:53.185888 CH1_RK0: MR19=0x303, MR18=0xA14, DQSOSC=399, MR23=63, INC=23, DEC=15
8757 22:55:53.185986
8758 22:55:53.189088 ----->DramcWriteLeveling(PI) begin...
8759 22:55:53.189186 ==
8760 22:55:53.192330 Dram Type= 6, Freq= 0, CH_1, rank 1
8761 22:55:53.195781 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8762 22:55:53.195863 ==
8763 22:55:53.199466 Write leveling (Byte 0): 25 => 25
8764 22:55:53.202305 Write leveling (Byte 1): 26 => 26
8765 22:55:53.205423 DramcWriteLeveling(PI) end<-----
8766 22:55:53.205518
8767 22:55:53.205584 ==
8768 22:55:53.208634 Dram Type= 6, Freq= 0, CH_1, rank 1
8769 22:55:53.211770 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8770 22:55:53.215302 ==
8771 22:55:53.215392 [Gating] SW mode calibration
8772 22:55:53.221877 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8773 22:55:53.228250 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8774 22:55:53.231870 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8775 22:55:53.238397 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8776 22:55:53.241804 1 4 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8777 22:55:53.244979 1 4 12 | B1->B0 | 2929 3434 | 0 1 | (0 0) (1 1)
8778 22:55:53.251793 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8779 22:55:53.254817 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8780 22:55:53.258372 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8781 22:55:53.265101 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8782 22:55:53.267798 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8783 22:55:53.270984 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8784 22:55:53.277618 1 5 8 | B1->B0 | 3434 2323 | 1 0 | (1 0) (1 0)
8785 22:55:53.280978 1 5 12 | B1->B0 | 3434 2323 | 0 0 | (1 0) (0 0)
8786 22:55:53.284519 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8787 22:55:53.291079 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8788 22:55:53.294014 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8789 22:55:53.297203 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8790 22:55:53.304063 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8791 22:55:53.307362 1 6 4 | B1->B0 | 2323 3131 | 0 1 | (0 0) (1 1)
8792 22:55:53.310553 1 6 8 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
8793 22:55:53.317382 1 6 12 | B1->B0 | 3636 4646 | 1 0 | (1 1) (0 0)
8794 22:55:53.320739 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8795 22:55:53.323898 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8796 22:55:53.330711 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8797 22:55:53.333910 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8798 22:55:53.337174 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8799 22:55:53.344526 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8800 22:55:53.347032 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8801 22:55:53.350263 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8802 22:55:53.356760 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8803 22:55:53.359934 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8804 22:55:53.363111 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8805 22:55:53.369856 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8806 22:55:53.373312 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8807 22:55:53.376619 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8808 22:55:53.383036 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8809 22:55:53.386768 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8810 22:55:53.389584 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8811 22:55:53.396239 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8812 22:55:53.399417 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8813 22:55:53.402955 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8814 22:55:53.409395 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8815 22:55:53.412832 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8816 22:55:53.416223 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8817 22:55:53.422712 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8818 22:55:53.426171 Total UI for P1: 0, mck2ui 16
8819 22:55:53.428935 best dqsien dly found for B0: ( 1, 9, 6)
8820 22:55:53.432452 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8821 22:55:53.435587 Total UI for P1: 0, mck2ui 16
8822 22:55:53.439145 best dqsien dly found for B1: ( 1, 9, 12)
8823 22:55:53.442431 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8824 22:55:53.446060 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8825 22:55:53.446151
8826 22:55:53.448719 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8827 22:55:53.455481 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8828 22:55:53.455556 [Gating] SW calibration Done
8829 22:55:53.455624 ==
8830 22:55:53.458841 Dram Type= 6, Freq= 0, CH_1, rank 1
8831 22:55:53.465575 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8832 22:55:53.465653 ==
8833 22:55:53.465720 RX Vref Scan: 0
8834 22:55:53.465782
8835 22:55:53.468680 RX Vref 0 -> 0, step: 1
8836 22:55:53.468753
8837 22:55:53.471933 RX Delay 0 -> 252, step: 8
8838 22:55:53.475173 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8839 22:55:53.478699 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8840 22:55:53.482146 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8841 22:55:53.488373 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8842 22:55:53.491927 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8843 22:55:53.494762 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8844 22:55:53.498342 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8845 22:55:53.501593 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8846 22:55:53.508281 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8847 22:55:53.511442 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8848 22:55:53.514853 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8849 22:55:53.518078 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8850 22:55:53.521824 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8851 22:55:53.527768 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8852 22:55:53.530806 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8853 22:55:53.534291 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8854 22:55:53.534368 ==
8855 22:55:53.537736 Dram Type= 6, Freq= 0, CH_1, rank 1
8856 22:55:53.544444 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8857 22:55:53.544528 ==
8858 22:55:53.544594 DQS Delay:
8859 22:55:53.544655 DQS0 = 0, DQS1 = 0
8860 22:55:53.547928 DQM Delay:
8861 22:55:53.548005 DQM0 = 134, DQM1 = 130
8862 22:55:53.550988 DQ Delay:
8863 22:55:53.554213 DQ0 =135, DQ1 =131, DQ2 =123, DQ3 =131
8864 22:55:53.557274 DQ4 =135, DQ5 =143, DQ6 =139, DQ7 =135
8865 22:55:53.560548 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =123
8866 22:55:53.564082 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8867 22:55:53.564189
8868 22:55:53.564253
8869 22:55:53.564314 ==
8870 22:55:53.567451 Dram Type= 6, Freq= 0, CH_1, rank 1
8871 22:55:53.570908 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8872 22:55:53.573661 ==
8873 22:55:53.573737
8874 22:55:53.573800
8875 22:55:53.573863 TX Vref Scan disable
8876 22:55:53.577108 == TX Byte 0 ==
8877 22:55:53.580649 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8878 22:55:53.583902 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8879 22:55:53.586868 == TX Byte 1 ==
8880 22:55:53.590329 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8881 22:55:53.597136 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8882 22:55:53.597216 ==
8883 22:55:53.600025 Dram Type= 6, Freq= 0, CH_1, rank 1
8884 22:55:53.603859 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8885 22:55:53.603935 ==
8886 22:55:53.616750
8887 22:55:53.620273 TX Vref early break, caculate TX vref
8888 22:55:53.623371 TX Vref=16, minBit 9, minWin=21, winSum=376
8889 22:55:53.626589 TX Vref=18, minBit 9, minWin=22, winSum=381
8890 22:55:53.630110 TX Vref=20, minBit 9, minWin=23, winSum=394
8891 22:55:53.633329 TX Vref=22, minBit 9, minWin=23, winSum=400
8892 22:55:53.636682 TX Vref=24, minBit 9, minWin=23, winSum=410
8893 22:55:53.642645 TX Vref=26, minBit 9, minWin=23, winSum=417
8894 22:55:53.646420 TX Vref=28, minBit 1, minWin=25, winSum=419
8895 22:55:53.650004 TX Vref=30, minBit 0, minWin=25, winSum=418
8896 22:55:53.652946 TX Vref=32, minBit 0, minWin=24, winSum=410
8897 22:55:53.656070 TX Vref=34, minBit 9, minWin=23, winSum=404
8898 22:55:53.662864 TX Vref=36, minBit 8, minWin=23, winSum=396
8899 22:55:53.665793 [TxChooseVref] Worse bit 1, Min win 25, Win sum 419, Final Vref 28
8900 22:55:53.665874
8901 22:55:53.669280 Final TX Range 0 Vref 28
8902 22:55:53.669358
8903 22:55:53.669463 ==
8904 22:55:53.672847 Dram Type= 6, Freq= 0, CH_1, rank 1
8905 22:55:53.675905 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8906 22:55:53.678819 ==
8907 22:55:53.678900
8908 22:55:53.678990
8909 22:55:53.679068 TX Vref Scan disable
8910 22:55:53.685498 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8911 22:55:53.685577 == TX Byte 0 ==
8912 22:55:53.688833 u2DelayCellOfst[0]=14 cells (4 PI)
8913 22:55:53.692735 u2DelayCellOfst[1]=10 cells (3 PI)
8914 22:55:53.695994 u2DelayCellOfst[2]=0 cells (0 PI)
8915 22:55:53.699232 u2DelayCellOfst[3]=7 cells (2 PI)
8916 22:55:53.702118 u2DelayCellOfst[4]=7 cells (2 PI)
8917 22:55:53.705521 u2DelayCellOfst[5]=18 cells (5 PI)
8918 22:55:53.708865 u2DelayCellOfst[6]=14 cells (4 PI)
8919 22:55:53.712516 u2DelayCellOfst[7]=3 cells (1 PI)
8920 22:55:53.715384 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8921 22:55:53.718976 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8922 22:55:53.722213 == TX Byte 1 ==
8923 22:55:53.725309 u2DelayCellOfst[8]=0 cells (0 PI)
8924 22:55:53.728806 u2DelayCellOfst[9]=7 cells (2 PI)
8925 22:55:53.731896 u2DelayCellOfst[10]=14 cells (4 PI)
8926 22:55:53.735522 u2DelayCellOfst[11]=7 cells (2 PI)
8927 22:55:53.738370 u2DelayCellOfst[12]=18 cells (5 PI)
8928 22:55:53.741828 u2DelayCellOfst[13]=18 cells (5 PI)
8929 22:55:53.741954 u2DelayCellOfst[14]=18 cells (5 PI)
8930 22:55:53.745253 u2DelayCellOfst[15]=21 cells (6 PI)
8931 22:55:53.751660 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8932 22:55:53.755480 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8933 22:55:53.758468 DramC Write-DBI on
8934 22:55:53.758565 ==
8935 22:55:53.761524 Dram Type= 6, Freq= 0, CH_1, rank 1
8936 22:55:53.765092 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8937 22:55:53.765219 ==
8938 22:55:53.765313
8939 22:55:53.765384
8940 22:55:53.768287 TX Vref Scan disable
8941 22:55:53.768374 == TX Byte 0 ==
8942 22:55:53.774829 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8943 22:55:53.774940 == TX Byte 1 ==
8944 22:55:53.778430 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8945 22:55:53.781266 DramC Write-DBI off
8946 22:55:53.781360
8947 22:55:53.781431 [DATLAT]
8948 22:55:53.784895 Freq=1600, CH1 RK1
8949 22:55:53.784987
8950 22:55:53.785049 DATLAT Default: 0xf
8951 22:55:53.787997 0, 0xFFFF, sum = 0
8952 22:55:53.788100 1, 0xFFFF, sum = 0
8953 22:55:53.791291 2, 0xFFFF, sum = 0
8954 22:55:53.794447 3, 0xFFFF, sum = 0
8955 22:55:53.794534 4, 0xFFFF, sum = 0
8956 22:55:53.797916 5, 0xFFFF, sum = 0
8957 22:55:53.798009 6, 0xFFFF, sum = 0
8958 22:55:53.800892 7, 0xFFFF, sum = 0
8959 22:55:53.800983 8, 0xFFFF, sum = 0
8960 22:55:53.804568 9, 0xFFFF, sum = 0
8961 22:55:53.804660 10, 0xFFFF, sum = 0
8962 22:55:53.807627 11, 0xFFFF, sum = 0
8963 22:55:53.807703 12, 0xFFFF, sum = 0
8964 22:55:53.811830 13, 0xFFFF, sum = 0
8965 22:55:53.811929 14, 0x0, sum = 1
8966 22:55:53.814786 15, 0x0, sum = 2
8967 22:55:53.814871 16, 0x0, sum = 3
8968 22:55:53.817623 17, 0x0, sum = 4
8969 22:55:53.817708 best_step = 15
8970 22:55:53.817772
8971 22:55:53.817832 ==
8972 22:55:53.821214 Dram Type= 6, Freq= 0, CH_1, rank 1
8973 22:55:53.827124 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8974 22:55:53.827208 ==
8975 22:55:53.827274 RX Vref Scan: 0
8976 22:55:53.827335
8977 22:55:53.830785 RX Vref 0 -> 0, step: 1
8978 22:55:53.830881
8979 22:55:53.833942 RX Delay 11 -> 252, step: 4
8980 22:55:53.837007 iDelay=195, Bit 0, Center 134 (83 ~ 186) 104
8981 22:55:53.840204 iDelay=195, Bit 1, Center 130 (79 ~ 182) 104
8982 22:55:53.846907 iDelay=195, Bit 2, Center 120 (67 ~ 174) 108
8983 22:55:53.850289 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8984 22:55:53.853573 iDelay=195, Bit 4, Center 130 (75 ~ 186) 112
8985 22:55:53.857281 iDelay=195, Bit 5, Center 142 (91 ~ 194) 104
8986 22:55:53.860330 iDelay=195, Bit 6, Center 140 (87 ~ 194) 108
8987 22:55:53.867010 iDelay=195, Bit 7, Center 128 (75 ~ 182) 108
8988 22:55:53.870122 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
8989 22:55:53.873784 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8990 22:55:53.876475 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8991 22:55:53.880021 iDelay=195, Bit 11, Center 122 (67 ~ 178) 112
8992 22:55:53.886410 iDelay=195, Bit 12, Center 136 (83 ~ 190) 108
8993 22:55:53.889655 iDelay=195, Bit 13, Center 134 (83 ~ 186) 104
8994 22:55:53.893326 iDelay=195, Bit 14, Center 134 (83 ~ 186) 104
8995 22:55:53.896410 iDelay=195, Bit 15, Center 138 (87 ~ 190) 104
8996 22:55:53.896511 ==
8997 22:55:53.899621 Dram Type= 6, Freq= 0, CH_1, rank 1
8998 22:55:53.906370 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8999 22:55:53.906451 ==
9000 22:55:53.906539 DQS Delay:
9001 22:55:53.909666 DQS0 = 0, DQS1 = 0
9002 22:55:53.909742 DQM Delay:
9003 22:55:53.912860 DQM0 = 131, DQM1 = 128
9004 22:55:53.912944 DQ Delay:
9005 22:55:53.916376 DQ0 =134, DQ1 =130, DQ2 =120, DQ3 =128
9006 22:55:53.919633 DQ4 =130, DQ5 =142, DQ6 =140, DQ7 =128
9007 22:55:53.922855 DQ8 =114, DQ9 =118, DQ10 =128, DQ11 =122
9008 22:55:53.925991 DQ12 =136, DQ13 =134, DQ14 =134, DQ15 =138
9009 22:55:53.926065
9010 22:55:53.926129
9011 22:55:53.926197
9012 22:55:53.929506 [DramC_TX_OE_Calibration] TA2
9013 22:55:53.932379 Original DQ_B0 (3 6) =30, OEN = 27
9014 22:55:53.935677 Original DQ_B1 (3 6) =30, OEN = 27
9015 22:55:53.938844 24, 0x0, End_B0=24 End_B1=24
9016 22:55:53.942260 25, 0x0, End_B0=25 End_B1=25
9017 22:55:53.942334 26, 0x0, End_B0=26 End_B1=26
9018 22:55:53.946093 27, 0x0, End_B0=27 End_B1=27
9019 22:55:53.948850 28, 0x0, End_B0=28 End_B1=28
9020 22:55:53.951973 29, 0x0, End_B0=29 End_B1=29
9021 22:55:53.955783 30, 0x0, End_B0=30 End_B1=30
9022 22:55:53.955863 31, 0x4141, End_B0=30 End_B1=30
9023 22:55:53.958934 Byte0 end_step=30 best_step=27
9024 22:55:53.961729 Byte1 end_step=30 best_step=27
9025 22:55:53.965325 Byte0 TX OE(2T, 0.5T) = (3, 3)
9026 22:55:53.968625 Byte1 TX OE(2T, 0.5T) = (3, 3)
9027 22:55:53.968700
9028 22:55:53.968764
9029 22:55:53.975036 [DQSOSCAuto] RK1, (LSB)MR18= 0xf1c, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 402 ps
9030 22:55:53.978752 CH1 RK1: MR19=303, MR18=F1C
9031 22:55:53.984992 CH1_RK1: MR19=0x303, MR18=0xF1C, DQSOSC=395, MR23=63, INC=23, DEC=15
9032 22:55:53.988704 [RxdqsGatingPostProcess] freq 1600
9033 22:55:53.995005 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9034 22:55:53.998053 best DQS0 dly(2T, 0.5T) = (1, 1)
9035 22:55:53.998159 best DQS1 dly(2T, 0.5T) = (1, 1)
9036 22:55:54.001279 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9037 22:55:54.004488 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9038 22:55:54.008086 best DQS0 dly(2T, 0.5T) = (1, 1)
9039 22:55:54.011099 best DQS1 dly(2T, 0.5T) = (1, 1)
9040 22:55:54.014556 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9041 22:55:54.017958 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9042 22:55:54.021388 Pre-setting of DQS Precalculation
9043 22:55:54.027824 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9044 22:55:54.034123 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9045 22:55:54.040584 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9046 22:55:54.040663
9047 22:55:54.040727
9048 22:55:54.044267 [Calibration Summary] 3200 Mbps
9049 22:55:54.044340 CH 0, Rank 0
9050 22:55:54.047312 SW Impedance : PASS
9051 22:55:54.050969 DUTY Scan : NO K
9052 22:55:54.051069 ZQ Calibration : PASS
9053 22:55:54.053934 Jitter Meter : NO K
9054 22:55:54.057401 CBT Training : PASS
9055 22:55:54.057476 Write leveling : PASS
9056 22:55:54.060546 RX DQS gating : PASS
9057 22:55:54.064108 RX DQ/DQS(RDDQC) : PASS
9058 22:55:54.064181 TX DQ/DQS : PASS
9059 22:55:54.067902 RX DATLAT : PASS
9060 22:55:54.067970 RX DQ/DQS(Engine): PASS
9061 22:55:54.070345 TX OE : PASS
9062 22:55:54.070463 All Pass.
9063 22:55:54.070527
9064 22:55:54.073840 CH 0, Rank 1
9065 22:55:54.077220 SW Impedance : PASS
9066 22:55:54.077299 DUTY Scan : NO K
9067 22:55:54.080511 ZQ Calibration : PASS
9068 22:55:54.080580 Jitter Meter : NO K
9069 22:55:54.083685 CBT Training : PASS
9070 22:55:54.086722 Write leveling : PASS
9071 22:55:54.086800 RX DQS gating : PASS
9072 22:55:54.090308 RX DQ/DQS(RDDQC) : PASS
9073 22:55:54.093547 TX DQ/DQS : PASS
9074 22:55:54.093629 RX DATLAT : PASS
9075 22:55:54.096708 RX DQ/DQS(Engine): PASS
9076 22:55:54.099903 TX OE : PASS
9077 22:55:54.099982 All Pass.
9078 22:55:54.100054
9079 22:55:54.100114 CH 1, Rank 0
9080 22:55:54.103220 SW Impedance : PASS
9081 22:55:54.106638 DUTY Scan : NO K
9082 22:55:54.106724 ZQ Calibration : PASS
9083 22:55:54.110211 Jitter Meter : NO K
9084 22:55:54.113143 CBT Training : PASS
9085 22:55:54.113217 Write leveling : PASS
9086 22:55:54.117491 RX DQS gating : PASS
9087 22:55:54.119845 RX DQ/DQS(RDDQC) : PASS
9088 22:55:54.119954 TX DQ/DQS : PASS
9089 22:55:54.123196 RX DATLAT : PASS
9090 22:55:54.126688 RX DQ/DQS(Engine): PASS
9091 22:55:54.126785 TX OE : PASS
9092 22:55:54.129531 All Pass.
9093 22:55:54.129625
9094 22:55:54.129687 CH 1, Rank 1
9095 22:55:54.132873 SW Impedance : PASS
9096 22:55:54.132943 DUTY Scan : NO K
9097 22:55:54.136332 ZQ Calibration : PASS
9098 22:55:54.139493 Jitter Meter : NO K
9099 22:55:54.139588 CBT Training : PASS
9100 22:55:54.143219 Write leveling : PASS
9101 22:55:54.146562 RX DQS gating : PASS
9102 22:55:54.146660 RX DQ/DQS(RDDQC) : PASS
9103 22:55:54.149416 TX DQ/DQS : PASS
9104 22:55:54.153011 RX DATLAT : PASS
9105 22:55:54.153092 RX DQ/DQS(Engine): PASS
9106 22:55:54.155791 TX OE : PASS
9107 22:55:54.155892 All Pass.
9108 22:55:54.155993
9109 22:55:54.159096 DramC Write-DBI on
9110 22:55:54.162496 PER_BANK_REFRESH: Hybrid Mode
9111 22:55:54.162581 TX_TRACKING: ON
9112 22:55:54.172504 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9113 22:55:54.179295 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9114 22:55:54.186213 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9115 22:55:54.188776 [FAST_K] Save calibration result to emmc
9116 22:55:54.192324 sync common calibartion params.
9117 22:55:54.196298 sync cbt_mode0:1, 1:1
9118 22:55:54.199129 dram_init: ddr_geometry: 2
9119 22:55:54.199206 dram_init: ddr_geometry: 2
9120 22:55:54.202517 dram_init: ddr_geometry: 2
9121 22:55:54.205566 0:dram_rank_size:100000000
9122 22:55:54.208928 1:dram_rank_size:100000000
9123 22:55:54.211911 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9124 22:55:54.215605 DFS_SHUFFLE_HW_MODE: ON
9125 22:55:54.219620 dramc_set_vcore_voltage set vcore to 725000
9126 22:55:54.222146 Read voltage for 1600, 0
9127 22:55:54.222253 Vio18 = 0
9128 22:55:54.222344 Vcore = 725000
9129 22:55:54.225118 Vdram = 0
9130 22:55:54.225192 Vddq = 0
9131 22:55:54.225254 Vmddr = 0
9132 22:55:54.228429 switch to 3200 Mbps bootup
9133 22:55:54.231725 [DramcRunTimeConfig]
9134 22:55:54.231819 PHYPLL
9135 22:55:54.231919 DPM_CONTROL_AFTERK: ON
9136 22:55:54.235117 PER_BANK_REFRESH: ON
9137 22:55:54.238714 REFRESH_OVERHEAD_REDUCTION: ON
9138 22:55:54.238822 CMD_PICG_NEW_MODE: OFF
9139 22:55:54.241706 XRTWTW_NEW_MODE: ON
9140 22:55:54.245440 XRTRTR_NEW_MODE: ON
9141 22:55:54.245516 TX_TRACKING: ON
9142 22:55:54.248171 RDSEL_TRACKING: OFF
9143 22:55:54.248252 DQS Precalculation for DVFS: ON
9144 22:55:54.251416 RX_TRACKING: OFF
9145 22:55:54.251510 HW_GATING DBG: ON
9146 22:55:54.254977 ZQCS_ENABLE_LP4: ON
9147 22:55:54.258174 RX_PICG_NEW_MODE: ON
9148 22:55:54.258253 TX_PICG_NEW_MODE: ON
9149 22:55:54.261856 ENABLE_RX_DCM_DPHY: ON
9150 22:55:54.265073 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9151 22:55:54.265172 DUMMY_READ_FOR_TRACKING: OFF
9152 22:55:54.268474 !!! SPM_CONTROL_AFTERK: OFF
9153 22:55:54.271093 !!! SPM could not control APHY
9154 22:55:54.274787 IMPEDANCE_TRACKING: ON
9155 22:55:54.274865 TEMP_SENSOR: ON
9156 22:55:54.277783 HW_SAVE_FOR_SR: OFF
9157 22:55:54.281103 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9158 22:55:54.284575 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9159 22:55:54.284649 Read ODT Tracking: ON
9160 22:55:54.288081 Refresh Rate DeBounce: ON
9161 22:55:54.291028 DFS_NO_QUEUE_FLUSH: ON
9162 22:55:54.294135 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9163 22:55:54.294207 ENABLE_DFS_RUNTIME_MRW: OFF
9164 22:55:54.297790 DDR_RESERVE_NEW_MODE: ON
9165 22:55:54.300669 MR_CBT_SWITCH_FREQ: ON
9166 22:55:54.300737 =========================
9167 22:55:54.320930 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9168 22:55:54.323983 dram_init: ddr_geometry: 2
9169 22:55:54.342364 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9170 22:55:54.346212 dram_init: dram init end (result: 0)
9171 22:55:54.352726 DRAM-K: Full calibration passed in 24426 msecs
9172 22:55:54.355552 MRC: failed to locate region type 0.
9173 22:55:54.355621 DRAM rank0 size:0x100000000,
9174 22:55:54.358940 DRAM rank1 size=0x100000000
9175 22:55:54.368653 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9176 22:55:54.375778 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9177 22:55:54.382748 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9178 22:55:54.391993 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9179 22:55:54.392101 DRAM rank0 size:0x100000000,
9180 22:55:54.395286 DRAM rank1 size=0x100000000
9181 22:55:54.395369 CBMEM:
9182 22:55:54.398371 IMD: root @ 0xfffff000 254 entries.
9183 22:55:54.401822 IMD: root @ 0xffffec00 62 entries.
9184 22:55:54.404870 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9185 22:55:54.411769 WARNING: RO_VPD is uninitialized or empty.
9186 22:55:54.415192 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9187 22:55:54.423607 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9188 22:55:54.435175 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9189 22:55:54.446506 BS: romstage times (exec / console): total (unknown) / 23957 ms
9190 22:55:54.446589
9191 22:55:54.446654
9192 22:55:54.456592 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9193 22:55:54.459761 ARM64: Exception handlers installed.
9194 22:55:54.463155 ARM64: Testing exception
9195 22:55:54.466507 ARM64: Done test exception
9196 22:55:54.466590 Enumerating buses...
9197 22:55:54.469871 Show all devs... Before device enumeration.
9198 22:55:54.472861 Root Device: enabled 1
9199 22:55:54.476054 CPU_CLUSTER: 0: enabled 1
9200 22:55:54.476149 CPU: 00: enabled 1
9201 22:55:54.480027 Compare with tree...
9202 22:55:54.480131 Root Device: enabled 1
9203 22:55:54.482723 CPU_CLUSTER: 0: enabled 1
9204 22:55:54.486291 CPU: 00: enabled 1
9205 22:55:54.486373 Root Device scanning...
9206 22:55:54.489611 scan_static_bus for Root Device
9207 22:55:54.492841 CPU_CLUSTER: 0 enabled
9208 22:55:54.495715 scan_static_bus for Root Device done
9209 22:55:54.499371 scan_bus: bus Root Device finished in 8 msecs
9210 22:55:54.499480 done
9211 22:55:54.506173 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9212 22:55:54.508994 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9213 22:55:54.515635 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9214 22:55:54.522534 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9215 22:55:54.522616 Allocating resources...
9216 22:55:54.525367 Reading resources...
9217 22:55:54.529201 Root Device read_resources bus 0 link: 0
9218 22:55:54.532056 DRAM rank0 size:0x100000000,
9219 22:55:54.532153 DRAM rank1 size=0x100000000
9220 22:55:54.538681 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9221 22:55:54.538780 CPU: 00 missing read_resources
9222 22:55:54.545165 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9223 22:55:54.548726 Root Device read_resources bus 0 link: 0 done
9224 22:55:54.551909 Done reading resources.
9225 22:55:54.555113 Show resources in subtree (Root Device)...After reading.
9226 22:55:54.558556 Root Device child on link 0 CPU_CLUSTER: 0
9227 22:55:54.561802 CPU_CLUSTER: 0 child on link 0 CPU: 00
9228 22:55:54.571487 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9229 22:55:54.571570 CPU: 00
9230 22:55:54.578261 Root Device assign_resources, bus 0 link: 0
9231 22:55:54.581369 CPU_CLUSTER: 0 missing set_resources
9232 22:55:54.584813 Root Device assign_resources, bus 0 link: 0 done
9233 22:55:54.587718 Done setting resources.
9234 22:55:54.591250 Show resources in subtree (Root Device)...After assigning values.
9235 22:55:54.598148 Root Device child on link 0 CPU_CLUSTER: 0
9236 22:55:54.601015 CPU_CLUSTER: 0 child on link 0 CPU: 00
9237 22:55:54.607676 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9238 22:55:54.611573 CPU: 00
9239 22:55:54.611654 Done allocating resources.
9240 22:55:54.617441 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9241 22:55:54.620896 Enabling resources...
9242 22:55:54.620988 done.
9243 22:55:54.623965 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9244 22:55:54.627579 Initializing devices...
9245 22:55:54.627650 Root Device init
9246 22:55:54.630855 init hardware done!
9247 22:55:54.634052 0x00000018: ctrlr->caps
9248 22:55:54.634152 52.000 MHz: ctrlr->f_max
9249 22:55:54.637217 0.400 MHz: ctrlr->f_min
9250 22:55:54.640820 0x40ff8080: ctrlr->voltages
9251 22:55:54.640893 sclk: 390625
9252 22:55:54.640953 Bus Width = 1
9253 22:55:54.643680 sclk: 390625
9254 22:55:54.643775 Bus Width = 1
9255 22:55:54.647445 Early init status = 3
9256 22:55:54.650502 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9257 22:55:54.654082 in-header: 03 fc 00 00 01 00 00 00
9258 22:55:54.657572 in-data: 00
9259 22:55:54.661060 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9260 22:55:54.666063 in-header: 03 fd 00 00 00 00 00 00
9261 22:55:54.668998 in-data:
9262 22:55:54.671969 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9263 22:55:54.676020 in-header: 03 fc 00 00 01 00 00 00
9264 22:55:54.679606 in-data: 00
9265 22:55:54.682527 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9266 22:55:54.688211 in-header: 03 fd 00 00 00 00 00 00
9267 22:55:54.691373 in-data:
9268 22:55:54.694607 [SSUSB] Setting up USB HOST controller...
9269 22:55:54.697997 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9270 22:55:54.701134 [SSUSB] phy power-on done.
9271 22:55:54.704943 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9272 22:55:54.711470 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9273 22:55:54.715093 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9274 22:55:54.721125 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9275 22:55:54.727680 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9276 22:55:54.734284 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9277 22:55:54.741512 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9278 22:55:54.748231 read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps
9279 22:55:54.751140 SPM: binary array size = 0x9dc
9280 22:55:54.754620 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9281 22:55:54.760823 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9282 22:55:54.768278 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9283 22:55:54.774205 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9284 22:55:54.777280 configure_display: Starting display init
9285 22:55:54.811199 anx7625_power_on_init: Init interface.
9286 22:55:54.814875 anx7625_disable_pd_protocol: Disabled PD feature.
9287 22:55:54.818043 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9288 22:55:54.845828 anx7625_start_dp_work: Secure OCM version=00
9289 22:55:54.848992 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9290 22:55:54.863800 sp_tx_get_edid_block: EDID Block = 1
9291 22:55:54.966788 Extracted contents:
9292 22:55:54.969859 header: 00 ff ff ff ff ff ff 00
9293 22:55:54.973167 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9294 22:55:54.976199 version: 01 04
9295 22:55:54.979708 basic params: 95 1f 11 78 0a
9296 22:55:54.982905 chroma info: 76 90 94 55 54 90 27 21 50 54
9297 22:55:54.986253 established: 00 00 00
9298 22:55:54.992666 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9299 22:55:54.999621 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9300 22:55:55.002933 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9301 22:55:55.009459 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9302 22:55:55.015774 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9303 22:55:55.019459 extensions: 00
9304 22:55:55.019533 checksum: fb
9305 22:55:55.019595
9306 22:55:55.025738 Manufacturer: IVO Model 57d Serial Number 0
9307 22:55:55.025815 Made week 0 of 2020
9308 22:55:55.028682 EDID version: 1.4
9309 22:55:55.028783 Digital display
9310 22:55:55.032531 6 bits per primary color channel
9311 22:55:55.035489 DisplayPort interface
9312 22:55:55.035566 Maximum image size: 31 cm x 17 cm
9313 22:55:55.039337 Gamma: 220%
9314 22:55:55.039436 Check DPMS levels
9315 22:55:55.045858 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9316 22:55:55.049000 First detailed timing is preferred timing
9317 22:55:55.052080 Established timings supported:
9318 22:55:55.052161 Standard timings supported:
9319 22:55:55.055263 Detailed timings
9320 22:55:55.058754 Hex of detail: 383680a07038204018303c0035ae10000019
9321 22:55:55.064949 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9322 22:55:55.068511 0780 0798 07c8 0820 hborder 0
9323 22:55:55.071596 0438 043b 0447 0458 vborder 0
9324 22:55:55.075141 -hsync -vsync
9325 22:55:55.075240 Did detailed timing
9326 22:55:55.081887 Hex of detail: 000000000000000000000000000000000000
9327 22:55:55.085239 Manufacturer-specified data, tag 0
9328 22:55:55.088451 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9329 22:55:55.091374 ASCII string: InfoVision
9330 22:55:55.094786 Hex of detail: 000000fe00523134304e574635205248200a
9331 22:55:55.098411 ASCII string: R140NWF5 RH
9332 22:55:55.098492 Checksum
9333 22:55:55.101488 Checksum: 0xfb (valid)
9334 22:55:55.105161 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9335 22:55:55.108015 DSI data_rate: 832800000 bps
9336 22:55:55.115091 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9337 22:55:55.118116 anx7625_parse_edid: pixelclock(138800).
9338 22:55:55.121115 hactive(1920), hsync(48), hfp(24), hbp(88)
9339 22:55:55.124980 vactive(1080), vsync(12), vfp(3), vbp(17)
9340 22:55:55.127687 anx7625_dsi_config: config dsi.
9341 22:55:55.134670 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9342 22:55:55.148766 anx7625_dsi_config: success to config DSI
9343 22:55:55.152285 anx7625_dp_start: MIPI phy setup OK.
9344 22:55:55.155134 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9345 22:55:55.158288 mtk_ddp_mode_set invalid vrefresh 60
9346 22:55:55.161831 main_disp_path_setup
9347 22:55:55.161911 ovl_layer_smi_id_en
9348 22:55:55.164960 ovl_layer_smi_id_en
9349 22:55:55.165039 ccorr_config
9350 22:55:55.165101 aal_config
9351 22:55:55.168621 gamma_config
9352 22:55:55.168701 postmask_config
9353 22:55:55.171909 dither_config
9354 22:55:55.174729 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9355 22:55:55.181786 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9356 22:55:55.185034 Root Device init finished in 553 msecs
9357 22:55:55.187757 CPU_CLUSTER: 0 init
9358 22:55:55.194443 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9359 22:55:55.201322 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9360 22:55:55.201403 APU_MBOX 0x190000b0 = 0x10001
9361 22:55:55.204487 APU_MBOX 0x190001b0 = 0x10001
9362 22:55:55.208152 APU_MBOX 0x190005b0 = 0x10001
9363 22:55:55.211609 APU_MBOX 0x190006b0 = 0x10001
9364 22:55:55.217627 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9365 22:55:55.227436 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9366 22:55:55.240239 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9367 22:55:55.246964 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9368 22:55:55.258141 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9369 22:55:55.267603 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9370 22:55:55.270617 CPU_CLUSTER: 0 init finished in 81 msecs
9371 22:55:55.274029 Devices initialized
9372 22:55:55.277167 Show all devs... After init.
9373 22:55:55.277247 Root Device: enabled 1
9374 22:55:55.280569 CPU_CLUSTER: 0: enabled 1
9375 22:55:55.283904 CPU: 00: enabled 1
9376 22:55:55.287104 BS: BS_DEV_INIT run times (exec / console): 211 / 447 ms
9377 22:55:55.290477 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9378 22:55:55.293579 ELOG: NV offset 0x57f000 size 0x1000
9379 22:55:55.300993 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9380 22:55:55.307212 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9381 22:55:55.310658 ELOG: Event(17) added with size 13 at 2023-06-05 22:55:55 UTC
9382 22:55:55.317065 out: cmd=0x121: 03 db 21 01 00 00 00 00
9383 22:55:55.319973 in-header: 03 2c 00 00 2c 00 00 00
9384 22:55:55.330136 in-data: 33 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9385 22:55:55.336484 ELOG: Event(A1) added with size 10 at 2023-06-05 22:55:55 UTC
9386 22:55:55.343215 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9387 22:55:55.350912 ELOG: Event(A0) added with size 9 at 2023-06-05 22:55:55 UTC
9388 22:55:55.353202 elog_add_boot_reason: Logged dev mode boot
9389 22:55:55.360065 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9390 22:55:55.360160 Finalize devices...
9391 22:55:55.362875 Devices finalized
9392 22:55:55.366377 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9393 22:55:55.369919 Writing coreboot table at 0xffe64000
9394 22:55:55.373023 0. 000000000010a000-0000000000113fff: RAMSTAGE
9395 22:55:55.379763 1. 0000000040000000-00000000400fffff: RAM
9396 22:55:55.383488 2. 0000000040100000-000000004032afff: RAMSTAGE
9397 22:55:55.386078 3. 000000004032b000-00000000545fffff: RAM
9398 22:55:55.389977 4. 0000000054600000-000000005465ffff: BL31
9399 22:55:55.393129 5. 0000000054660000-00000000ffe63fff: RAM
9400 22:55:55.399297 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9401 22:55:55.402775 7. 0000000100000000-000000023fffffff: RAM
9402 22:55:55.405918 Passing 5 GPIOs to payload:
9403 22:55:55.409178 NAME | PORT | POLARITY | VALUE
9404 22:55:55.415921 EC in RW | 0x000000aa | low | undefined
9405 22:55:55.419029 EC interrupt | 0x00000005 | low | undefined
9406 22:55:55.422912 TPM interrupt | 0x000000ab | high | undefined
9407 22:55:55.429190 SD card detect | 0x00000011 | high | undefined
9408 22:55:55.432649 speaker enable | 0x00000093 | high | undefined
9409 22:55:55.435483 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9410 22:55:55.439468 in-header: 03 f9 00 00 02 00 00 00
9411 22:55:55.443146 in-data: 02 00
9412 22:55:55.446335 ADC[4]: Raw value=903325 ID=7
9413 22:55:55.449483 ADC[3]: Raw value=213546 ID=1
9414 22:55:55.449564 RAM Code: 0x71
9415 22:55:55.452716 ADC[6]: Raw value=74630 ID=0
9416 22:55:55.456059 ADC[5]: Raw value=213546 ID=1
9417 22:55:55.456156 SKU Code: 0x1
9418 22:55:55.462924 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum a53a
9419 22:55:55.463007 coreboot table: 964 bytes.
9420 22:55:55.466082 IMD ROOT 0. 0xfffff000 0x00001000
9421 22:55:55.469976 IMD SMALL 1. 0xffffe000 0x00001000
9422 22:55:55.473250 RO MCACHE 2. 0xffffc000 0x00001104
9423 22:55:55.475970 CONSOLE 3. 0xfff7c000 0x00080000
9424 22:55:55.479162 FMAP 4. 0xfff7b000 0x00000452
9425 22:55:55.482708 TIME STAMP 5. 0xfff7a000 0x00000910
9426 22:55:55.485954 VBOOT WORK 6. 0xfff66000 0x00014000
9427 22:55:55.489098 RAMOOPS 7. 0xffe66000 0x00100000
9428 22:55:55.493106 COREBOOT 8. 0xffe64000 0x00002000
9429 22:55:55.495640 IMD small region:
9430 22:55:55.498973 IMD ROOT 0. 0xffffec00 0x00000400
9431 22:55:55.502231 VPD 1. 0xffffeba0 0x0000004c
9432 22:55:55.505890 MMC STATUS 2. 0xffffeb80 0x00000004
9433 22:55:55.512237 BS: BS_WRITE_TABLES run times (exec / console): 2 / 137 ms
9434 22:55:55.512336 Probing TPM: done!
9435 22:55:55.519110 Connected to device vid:did:rid of 1ae0:0028:00
9436 22:55:55.525802 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
9437 22:55:55.529077 Initialized TPM device CR50 revision 0
9438 22:55:55.532163 Checking cr50 for pending updates
9439 22:55:55.537607 Reading cr50 TPM mode
9440 22:55:55.546529 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9441 22:55:55.552914 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9442 22:55:55.593293 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9443 22:55:55.596788 Checking segment from ROM address 0x40100000
9444 22:55:55.599958 Checking segment from ROM address 0x4010001c
9445 22:55:55.606304 Loading segment from ROM address 0x40100000
9446 22:55:55.606403 code (compression=0)
9447 22:55:55.616213 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9448 22:55:55.622875 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9449 22:55:55.622993 it's not compressed!
9450 22:55:55.629481 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9451 22:55:55.636420 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9452 22:55:55.653546 Loading segment from ROM address 0x4010001c
9453 22:55:55.653628 Entry Point 0x80000000
9454 22:55:55.657023 Loaded segments
9455 22:55:55.660171 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9456 22:55:55.666656 Jumping to boot code at 0x80000000(0xffe64000)
9457 22:55:55.673369 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9458 22:55:55.680017 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9459 22:55:55.687939 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9460 22:55:55.691223 Checking segment from ROM address 0x40100000
9461 22:55:55.694601 Checking segment from ROM address 0x4010001c
9462 22:55:55.701405 Loading segment from ROM address 0x40100000
9463 22:55:55.701484 code (compression=1)
9464 22:55:55.708089 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9465 22:55:55.718032 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9466 22:55:55.718122 using LZMA
9467 22:55:55.726136 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9468 22:55:55.732902 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9469 22:55:55.736393 Loading segment from ROM address 0x4010001c
9470 22:55:55.736465 Entry Point 0x54601000
9471 22:55:55.740130 Loaded segments
9472 22:55:55.742854 NOTICE: MT8192 bl31_setup
9473 22:55:55.750114 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9474 22:55:55.753446 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9475 22:55:55.756684 WARNING: region 0:
9476 22:55:55.760364 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9477 22:55:55.760441 WARNING: region 1:
9478 22:55:55.766939 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9479 22:55:55.769543 WARNING: region 2:
9480 22:55:55.773281 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9481 22:55:55.776335 WARNING: region 3:
9482 22:55:55.780201 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9483 22:55:55.783130 WARNING: region 4:
9484 22:55:55.790720 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9485 22:55:55.790800 WARNING: region 5:
9486 22:55:55.793140 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9487 22:55:55.796799 WARNING: region 6:
9488 22:55:55.800139 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9489 22:55:55.800207 WARNING: region 7:
9490 22:55:55.806652 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9491 22:55:55.813166 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9492 22:55:55.816974 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9493 22:55:55.820099 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9494 22:55:55.826417 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9495 22:55:55.829953 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9496 22:55:55.832953 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9497 22:55:55.839720 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9498 22:55:55.843171 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9499 22:55:55.849954 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9500 22:55:55.853219 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9501 22:55:55.856202 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9502 22:55:55.863094 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9503 22:55:55.866272 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9504 22:55:55.869753 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9505 22:55:55.876321 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9506 22:55:55.879701 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9507 22:55:55.886084 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9508 22:55:55.889530 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9509 22:55:55.892585 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9510 22:55:55.899576 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9511 22:55:55.902503 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9512 22:55:55.909463 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9513 22:55:55.912799 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9514 22:55:55.915978 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9515 22:55:55.922908 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9516 22:55:55.926431 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9517 22:55:55.932614 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9518 22:55:55.936164 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9519 22:55:55.939506 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9520 22:55:55.945694 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9521 22:55:55.949408 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9522 22:55:55.955919 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9523 22:55:55.959052 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9524 22:55:55.962803 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9525 22:55:55.965900 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9526 22:55:55.969037 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9527 22:55:55.975550 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9528 22:55:55.979371 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9529 22:55:55.982520 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9530 22:55:55.985950 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9531 22:55:55.992382 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9532 22:55:55.995566 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9533 22:55:55.998966 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9534 22:55:56.005645 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9535 22:55:56.009267 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9536 22:55:56.012646 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9537 22:55:56.016152 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9538 22:55:56.022176 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9539 22:55:56.025938 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9540 22:55:56.029247 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9541 22:55:56.035503 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9542 22:55:56.038920 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9543 22:55:56.045397 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9544 22:55:56.048814 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9545 22:55:56.055806 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9546 22:55:56.059312 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9547 22:55:56.065794 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9548 22:55:56.068708 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9549 22:55:56.072422 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9550 22:55:56.078841 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9551 22:55:56.082355 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9552 22:55:56.089310 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9553 22:55:56.092298 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9554 22:55:56.099184 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9555 22:55:56.102213 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9556 22:55:56.105514 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9557 22:55:56.112324 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9558 22:55:56.115415 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9559 22:55:56.122072 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9560 22:55:56.125050 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9561 22:55:56.132628 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9562 22:55:56.135381 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9563 22:55:56.138888 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9564 22:55:56.145216 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9565 22:55:56.148886 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9566 22:55:56.155220 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9567 22:55:56.158750 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9568 22:55:56.165746 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9569 22:55:56.168664 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9570 22:55:56.172259 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9571 22:55:56.178711 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9572 22:55:56.181830 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9573 22:55:56.188601 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9574 22:55:56.192228 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9575 22:55:56.198506 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9576 22:55:56.202087 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9577 22:55:56.208611 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9578 22:55:56.211961 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9579 22:55:56.214992 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9580 22:55:56.221722 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9581 22:55:56.224717 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9582 22:55:56.231798 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9583 22:55:56.235211 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9584 22:55:56.241540 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9585 22:55:56.244941 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9586 22:55:56.251346 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9587 22:55:56.254799 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9588 22:55:56.258312 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9589 22:55:56.261124 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9590 22:55:56.267800 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9591 22:55:56.271206 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9592 22:55:56.274498 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9593 22:55:56.281602 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9594 22:55:56.284750 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9595 22:55:56.291203 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9596 22:55:56.294691 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9597 22:55:56.297755 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9598 22:55:56.304848 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9599 22:55:56.308015 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9600 22:55:56.314265 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9601 22:55:56.317532 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9602 22:55:56.321270 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9603 22:55:56.327889 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9604 22:55:56.330756 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9605 22:55:56.337918 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9606 22:55:56.340998 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9607 22:55:56.344145 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9608 22:55:56.347792 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9609 22:55:56.354202 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9610 22:55:56.357475 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9611 22:55:56.360980 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9612 22:55:56.364330 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9613 22:55:56.370798 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9614 22:55:56.374298 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9615 22:55:56.377322 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9616 22:55:56.384136 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9617 22:55:56.387375 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9618 22:55:56.393852 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9619 22:55:56.397005 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9620 22:55:56.400601 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9621 22:55:56.407140 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9622 22:55:56.410556 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9623 22:55:56.417505 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9624 22:55:56.420295 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9625 22:55:56.423753 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9626 22:55:56.430592 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9627 22:55:56.434269 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9628 22:55:56.437385 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9629 22:55:56.443754 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9630 22:55:56.447242 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9631 22:55:56.453556 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9632 22:55:56.457566 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9633 22:55:56.460427 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9634 22:55:56.467481 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9635 22:55:56.470566 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9636 22:55:56.476859 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9637 22:55:56.480501 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9638 22:55:56.483598 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9639 22:55:56.490328 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9640 22:55:56.493637 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9641 22:55:56.500589 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9642 22:55:56.503646 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9643 22:55:56.506860 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9644 22:55:56.514038 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9645 22:55:56.516951 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9646 22:55:56.523556 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9647 22:55:56.526779 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9648 22:55:56.530154 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9649 22:55:56.537506 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9650 22:55:56.540449 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9651 22:55:56.543272 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9652 22:55:56.550617 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9653 22:55:56.553126 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9654 22:55:56.560153 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9655 22:55:56.563167 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9656 22:55:56.567160 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9657 22:55:56.573218 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9658 22:55:56.576762 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9659 22:55:56.582815 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9660 22:55:56.586261 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9661 22:55:56.592937 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9662 22:55:56.596527 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9663 22:55:56.599454 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9664 22:55:56.606804 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9665 22:55:56.609583 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9666 22:55:56.612986 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9667 22:55:56.619498 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9668 22:55:56.622619 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9669 22:55:56.629380 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9670 22:55:56.632477 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9671 22:55:56.636042 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9672 22:55:56.643088 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9673 22:55:56.645491 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9674 22:55:56.652310 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9675 22:55:56.655623 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9676 22:55:56.662490 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9677 22:55:56.665618 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9678 22:55:56.668682 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9679 22:55:56.675718 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9680 22:55:56.678764 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9681 22:55:56.685143 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9682 22:55:56.688756 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9683 22:55:56.695439 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9684 22:55:56.698458 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9685 22:55:56.701502 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9686 22:55:56.708410 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9687 22:55:56.711152 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9688 22:55:56.718164 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9689 22:55:56.721647 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9690 22:55:56.727756 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9691 22:55:56.731221 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9692 22:55:56.734492 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9693 22:55:56.741011 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9694 22:55:56.744654 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9695 22:55:56.750913 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9696 22:55:56.754244 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9697 22:55:56.757908 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9698 22:55:56.764452 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9699 22:55:56.767770 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9700 22:55:56.774067 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9701 22:55:56.777820 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9702 22:55:56.784191 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9703 22:55:56.787476 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9704 22:55:56.790803 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9705 22:55:56.797327 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9706 22:55:56.800748 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9707 22:55:56.807493 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9708 22:55:56.810670 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9709 22:55:56.817503 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9710 22:55:56.820638 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9711 22:55:56.823731 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9712 22:55:56.830436 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9713 22:55:56.833596 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9714 22:55:56.840214 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9715 22:55:56.843551 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9716 22:55:56.847092 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9717 22:55:56.853991 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9718 22:55:56.856876 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9719 22:55:56.863360 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9720 22:55:56.866820 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9721 22:55:56.870040 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9722 22:55:56.873631 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9723 22:55:56.879759 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9724 22:55:56.883357 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9725 22:55:56.887144 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9726 22:55:56.893136 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9727 22:55:56.896395 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9728 22:55:56.900014 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9729 22:55:56.906893 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9730 22:55:56.910039 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9731 22:55:56.912882 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9732 22:55:56.919647 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9733 22:55:56.923099 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9734 22:55:56.929557 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9735 22:55:56.933198 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9736 22:55:56.936393 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9737 22:55:56.943026 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9738 22:55:56.946876 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9739 22:55:56.949841 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9740 22:55:56.956091 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9741 22:55:56.959534 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9742 22:55:56.966245 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9743 22:55:56.969085 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9744 22:55:56.972410 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9745 22:55:56.979108 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9746 22:55:56.982085 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9747 22:55:56.988626 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9748 22:55:56.992084 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9749 22:55:56.995216 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9750 22:55:57.002249 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9751 22:55:57.005183 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9752 22:55:57.008649 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9753 22:55:57.015301 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9754 22:55:57.018949 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9755 22:55:57.021994 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9756 22:55:57.028246 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9757 22:55:57.031811 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9758 22:55:57.038265 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9759 22:55:57.041784 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9760 22:55:57.044682 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9761 22:55:57.048451 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9762 22:55:57.054894 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9763 22:55:57.057874 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9764 22:55:57.061175 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9765 22:55:57.064339 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9766 22:55:57.071463 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9767 22:55:57.074333 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9768 22:55:57.077776 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9769 22:55:57.081113 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9770 22:55:57.087575 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9771 22:55:57.090817 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9772 22:55:57.094357 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9773 22:55:57.100768 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9774 22:55:57.103891 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9775 22:55:57.110820 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9776 22:55:57.114148 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9777 22:55:57.117520 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9778 22:55:57.123687 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9779 22:55:57.127175 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9780 22:55:57.133936 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9781 22:55:57.137210 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9782 22:55:57.143631 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9783 22:55:57.146868 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9784 22:55:57.150462 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9785 22:55:57.156914 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9786 22:55:57.160264 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9787 22:55:57.166708 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9788 22:55:57.170024 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9789 22:55:57.173143 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9790 22:55:57.179831 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9791 22:55:57.183431 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9792 22:55:57.189722 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9793 22:55:57.192862 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9794 22:55:57.200048 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9795 22:55:57.203121 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9796 22:55:57.206272 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9797 22:55:57.213234 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9798 22:55:57.216119 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9799 22:55:57.222917 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9800 22:55:57.225752 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9801 22:55:57.232997 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9802 22:55:57.236060 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9803 22:55:57.239610 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9804 22:55:57.245869 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9805 22:55:57.249115 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9806 22:55:57.255771 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9807 22:55:57.259014 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9808 22:55:57.262269 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9809 22:55:57.269806 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9810 22:55:57.272193 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9811 22:55:57.278651 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9812 22:55:57.282016 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9813 22:55:57.285176 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9814 22:55:57.291805 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9815 22:55:57.295163 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9816 22:55:57.302066 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9817 22:55:57.305312 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9818 22:55:57.312099 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9819 22:55:57.315199 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9820 22:55:57.318125 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9821 22:55:57.324573 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9822 22:55:57.328203 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9823 22:55:57.334642 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9824 22:55:57.338028 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9825 22:55:57.344614 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9826 22:55:57.347645 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9827 22:55:57.351227 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9828 22:55:57.357468 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9829 22:55:57.360787 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9830 22:55:57.367987 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9831 22:55:57.370560 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9832 22:55:57.377812 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9833 22:55:57.380943 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9834 22:55:57.384189 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9835 22:55:57.390604 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9836 22:55:57.394238 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9837 22:55:57.400594 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9838 22:55:57.404014 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9839 22:55:57.407363 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9840 22:55:57.413856 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9841 22:55:57.417108 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9842 22:55:57.423601 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9843 22:55:57.427192 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9844 22:55:57.430334 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9845 22:55:57.437207 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9846 22:55:57.440281 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9847 22:55:57.446635 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9848 22:55:57.450190 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9849 22:55:57.456516 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9850 22:55:57.460155 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9851 22:55:57.466883 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9852 22:55:57.469535 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9853 22:55:57.473175 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9854 22:55:57.480160 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9855 22:55:57.482831 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9856 22:55:57.489561 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9857 22:55:57.492661 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9858 22:55:57.499022 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9859 22:55:57.502385 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9860 22:55:57.509307 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9861 22:55:57.512697 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9862 22:55:57.519189 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9863 22:55:57.522468 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9864 22:55:57.525849 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9865 22:55:57.532109 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9866 22:55:57.535336 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9867 22:55:57.542515 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9868 22:55:57.545518 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9869 22:55:57.551866 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9870 22:55:57.555540 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9871 22:55:57.561935 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9872 22:55:57.565366 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9873 22:55:57.568846 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9874 22:55:57.575243 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9875 22:55:57.578176 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9876 22:55:57.584714 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9877 22:55:57.588421 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9878 22:55:57.594947 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9879 22:55:57.598513 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9880 22:55:57.604978 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9881 22:55:57.607905 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9882 22:55:57.614489 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9883 22:55:57.618226 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9884 22:55:57.621224 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9885 22:55:57.627759 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9886 22:55:57.630977 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9887 22:55:57.637584 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9888 22:55:57.640988 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9889 22:55:57.647566 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9890 22:55:57.651152 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9891 22:55:57.657315 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9892 22:55:57.660513 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9893 22:55:57.664080 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9894 22:55:57.670485 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9895 22:55:57.673885 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9896 22:55:57.680634 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9897 22:55:57.684124 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9898 22:55:57.690178 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9899 22:55:57.693696 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9900 22:55:57.700708 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9901 22:55:57.703421 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9902 22:55:57.710662 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9903 22:55:57.713986 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9904 22:55:57.719990 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9905 22:55:57.723442 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9906 22:55:57.729857 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9907 22:55:57.733312 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9908 22:55:57.736422 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9909 22:55:57.742990 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9910 22:55:57.746501 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9911 22:55:57.752925 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9912 22:55:57.756066 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9913 22:55:57.762765 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9914 22:55:57.769112 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9915 22:55:57.772785 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9916 22:55:57.779421 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9917 22:55:57.782634 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9918 22:55:57.789283 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9919 22:55:57.792238 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9920 22:55:57.798777 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9921 22:55:57.802562 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9922 22:55:57.808632 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9923 22:55:57.812522 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9924 22:55:57.818525 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9925 22:55:57.822763 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9926 22:55:57.825088 INFO: [APUAPC] vio 0
9927 22:55:57.829471 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9928 22:55:57.835302 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9929 22:55:57.838606 INFO: [APUAPC] D0_APC_0: 0x400510
9930 22:55:57.838688 INFO: [APUAPC] D0_APC_1: 0x0
9931 22:55:57.841993 INFO: [APUAPC] D0_APC_2: 0x1540
9932 22:55:57.845474 INFO: [APUAPC] D0_APC_3: 0x0
9933 22:55:57.848488 INFO: [APUAPC] D1_APC_0: 0xffffffff
9934 22:55:57.851512 INFO: [APUAPC] D1_APC_1: 0xffffffff
9935 22:55:57.855452 INFO: [APUAPC] D1_APC_2: 0x3fffff
9936 22:55:57.858069 INFO: [APUAPC] D1_APC_3: 0x0
9937 22:55:57.861631 INFO: [APUAPC] D2_APC_0: 0xffffffff
9938 22:55:57.864764 INFO: [APUAPC] D2_APC_1: 0xffffffff
9939 22:55:57.868184 INFO: [APUAPC] D2_APC_2: 0x3fffff
9940 22:55:57.871448 INFO: [APUAPC] D2_APC_3: 0x0
9941 22:55:57.874934 INFO: [APUAPC] D3_APC_0: 0xffffffff
9942 22:55:57.878095 INFO: [APUAPC] D3_APC_1: 0xffffffff
9943 22:55:57.881754 INFO: [APUAPC] D3_APC_2: 0x3fffff
9944 22:55:57.885046 INFO: [APUAPC] D3_APC_3: 0x0
9945 22:55:57.887937 INFO: [APUAPC] D4_APC_0: 0xffffffff
9946 22:55:57.891026 INFO: [APUAPC] D4_APC_1: 0xffffffff
9947 22:55:57.894210 INFO: [APUAPC] D4_APC_2: 0x3fffff
9948 22:55:57.897739 INFO: [APUAPC] D4_APC_3: 0x0
9949 22:55:57.900884 INFO: [APUAPC] D5_APC_0: 0xffffffff
9950 22:55:57.904491 INFO: [APUAPC] D5_APC_1: 0xffffffff
9951 22:55:57.907411 INFO: [APUAPC] D5_APC_2: 0x3fffff
9952 22:55:57.911110 INFO: [APUAPC] D5_APC_3: 0x0
9953 22:55:57.914074 INFO: [APUAPC] D6_APC_0: 0xffffffff
9954 22:55:57.917549 INFO: [APUAPC] D6_APC_1: 0xffffffff
9955 22:55:57.921319 INFO: [APUAPC] D6_APC_2: 0x3fffff
9956 22:55:57.924305 INFO: [APUAPC] D6_APC_3: 0x0
9957 22:55:57.927582 INFO: [APUAPC] D7_APC_0: 0xffffffff
9958 22:55:57.930847 INFO: [APUAPC] D7_APC_1: 0xffffffff
9959 22:55:57.934363 INFO: [APUAPC] D7_APC_2: 0x3fffff
9960 22:55:57.937474 INFO: [APUAPC] D7_APC_3: 0x0
9961 22:55:57.940350 INFO: [APUAPC] D8_APC_0: 0xffffffff
9962 22:55:57.943721 INFO: [APUAPC] D8_APC_1: 0xffffffff
9963 22:55:57.947103 INFO: [APUAPC] D8_APC_2: 0x3fffff
9964 22:55:57.950447 INFO: [APUAPC] D8_APC_3: 0x0
9965 22:55:57.953657 INFO: [APUAPC] D9_APC_0: 0xffffffff
9966 22:55:57.956955 INFO: [APUAPC] D9_APC_1: 0xffffffff
9967 22:55:57.960370 INFO: [APUAPC] D9_APC_2: 0x3fffff
9968 22:55:57.963570 INFO: [APUAPC] D9_APC_3: 0x0
9969 22:55:57.966886 INFO: [APUAPC] D10_APC_0: 0xffffffff
9970 22:55:57.970337 INFO: [APUAPC] D10_APC_1: 0xffffffff
9971 22:55:57.973836 INFO: [APUAPC] D10_APC_2: 0x3fffff
9972 22:55:57.976639 INFO: [APUAPC] D10_APC_3: 0x0
9973 22:55:57.980424 INFO: [APUAPC] D11_APC_0: 0xffffffff
9974 22:55:57.983670 INFO: [APUAPC] D11_APC_1: 0xffffffff
9975 22:55:57.986614 INFO: [APUAPC] D11_APC_2: 0x3fffff
9976 22:55:57.990374 INFO: [APUAPC] D11_APC_3: 0x0
9977 22:55:57.993406 INFO: [APUAPC] D12_APC_0: 0xffffffff
9978 22:55:57.997022 INFO: [APUAPC] D12_APC_1: 0xffffffff
9979 22:55:57.999898 INFO: [APUAPC] D12_APC_2: 0x3fffff
9980 22:55:58.003182 INFO: [APUAPC] D12_APC_3: 0x0
9981 22:55:58.006818 INFO: [APUAPC] D13_APC_0: 0xffffffff
9982 22:55:58.009806 INFO: [APUAPC] D13_APC_1: 0xffffffff
9983 22:55:58.013078 INFO: [APUAPC] D13_APC_2: 0x3fffff
9984 22:55:58.016513 INFO: [APUAPC] D13_APC_3: 0x0
9985 22:55:58.019727 INFO: [APUAPC] D14_APC_0: 0xffffffff
9986 22:55:58.023161 INFO: [APUAPC] D14_APC_1: 0xffffffff
9987 22:55:58.026669 INFO: [APUAPC] D14_APC_2: 0x3fffff
9988 22:55:58.030518 INFO: [APUAPC] D14_APC_3: 0x0
9989 22:55:58.033737 INFO: [APUAPC] D15_APC_0: 0xffffffff
9990 22:55:58.036747 INFO: [APUAPC] D15_APC_1: 0xffffffff
9991 22:55:58.039715 INFO: [APUAPC] D15_APC_2: 0x3fffff
9992 22:55:58.042898 INFO: [APUAPC] D15_APC_3: 0x0
9993 22:55:58.046126 INFO: [APUAPC] APC_CON: 0x4
9994 22:55:58.049393 INFO: [NOCDAPC] D0_APC_0: 0x0
9995 22:55:58.052573 INFO: [NOCDAPC] D0_APC_1: 0x0
9996 22:55:58.056117 INFO: [NOCDAPC] D1_APC_0: 0x0
9997 22:55:58.056191 INFO: [NOCDAPC] D1_APC_1: 0xfff
9998 22:55:58.059223 INFO: [NOCDAPC] D2_APC_0: 0x0
9999 22:55:58.062808 INFO: [NOCDAPC] D2_APC_1: 0xfff
10000 22:55:58.065812 INFO: [NOCDAPC] D3_APC_0: 0x0
10001 22:55:58.069238 INFO: [NOCDAPC] D3_APC_1: 0xfff
10002 22:55:58.072369 INFO: [NOCDAPC] D4_APC_0: 0x0
10003 22:55:58.075498 INFO: [NOCDAPC] D4_APC_1: 0xfff
10004 22:55:58.078788 INFO: [NOCDAPC] D5_APC_0: 0x0
10005 22:55:58.082582 INFO: [NOCDAPC] D5_APC_1: 0xfff
10006 22:55:58.085943 INFO: [NOCDAPC] D6_APC_0: 0x0
10007 22:55:58.088995 INFO: [NOCDAPC] D6_APC_1: 0xfff
10008 22:55:58.091985 INFO: [NOCDAPC] D7_APC_0: 0x0
10009 22:55:58.095431 INFO: [NOCDAPC] D7_APC_1: 0xfff
10010 22:55:58.095543 INFO: [NOCDAPC] D8_APC_0: 0x0
10011 22:55:58.098930 INFO: [NOCDAPC] D8_APC_1: 0xfff
10012 22:55:58.101592 INFO: [NOCDAPC] D9_APC_0: 0x0
10013 22:55:58.105229 INFO: [NOCDAPC] D9_APC_1: 0xfff
10014 22:55:58.108277 INFO: [NOCDAPC] D10_APC_0: 0x0
10015 22:55:58.112075 INFO: [NOCDAPC] D10_APC_1: 0xfff
10016 22:55:58.114969 INFO: [NOCDAPC] D11_APC_0: 0x0
10017 22:55:58.118308 INFO: [NOCDAPC] D11_APC_1: 0xfff
10018 22:55:58.121875 INFO: [NOCDAPC] D12_APC_0: 0x0
10019 22:55:58.125144 INFO: [NOCDAPC] D12_APC_1: 0xfff
10020 22:55:58.128134 INFO: [NOCDAPC] D13_APC_0: 0x0
10021 22:55:58.131557 INFO: [NOCDAPC] D13_APC_1: 0xfff
10022 22:55:58.135022 INFO: [NOCDAPC] D14_APC_0: 0x0
10023 22:55:58.138112 INFO: [NOCDAPC] D14_APC_1: 0xfff
10024 22:55:58.138197 INFO: [NOCDAPC] D15_APC_0: 0x0
10025 22:55:58.141441 INFO: [NOCDAPC] D15_APC_1: 0xfff
10026 22:55:58.144689 INFO: [NOCDAPC] APC_CON: 0x4
10027 22:55:58.148988 INFO: [APUAPC] set_apusys_apc done
10028 22:55:58.151585 INFO: [DEVAPC] devapc_init done
10029 22:55:58.158140 INFO: GICv3 without legacy support detected.
10030 22:55:58.161871 INFO: ARM GICv3 driver initialized in EL3
10031 22:55:58.164832 INFO: Maximum SPI INTID supported: 639
10032 22:55:58.167807 INFO: BL31: Initializing runtime services
10033 22:55:58.174373 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10034 22:55:58.177839 INFO: SPM: enable CPC mode
10035 22:55:58.181102 INFO: mcdi ready for mcusys-off-idle and system suspend
10036 22:55:58.188138 INFO: BL31: Preparing for EL3 exit to normal world
10037 22:55:58.190770 INFO: Entry point address = 0x80000000
10038 22:55:58.190853 INFO: SPSR = 0x8
10039 22:55:58.197844
10040 22:55:58.197928
10041 22:55:58.197992
10042 22:55:58.201112 Starting depthcharge on Spherion...
10043 22:55:58.201185
10044 22:55:58.201246 Wipe memory regions:
10045 22:55:58.201310
10046 22:55:58.201947 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10047 22:55:58.202051 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10048 22:55:58.202138 Setting prompt string to ['asurada:']
10049 22:55:58.202440 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10050 22:55:58.204502 [0x00000040000000, 0x00000054600000)
10051 22:55:58.326957
10052 22:55:58.327083 [0x00000054660000, 0x00000080000000)
10053 22:55:58.587182
10054 22:55:58.587314 [0x000000821a7280, 0x000000ffe64000)
10055 22:55:59.332056
10056 22:55:59.332208 [0x00000100000000, 0x00000240000000)
10057 22:56:01.223014
10058 22:56:01.225796 Initializing XHCI USB controller at 0x11200000.
10059 22:56:02.263519
10060 22:56:02.266734 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10061 22:56:02.266843
10062 22:56:02.266923
10063 22:56:02.266985
10064 22:56:02.267275 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10066 22:56:02.367559 asurada: tftpboot 192.168.201.1 10597665/tftp-deploy-ltd01qmt/kernel/image.itb 10597665/tftp-deploy-ltd01qmt/kernel/cmdline
10067 22:56:02.367679 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10068 22:56:02.367784 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10069 22:56:02.371987 tftpboot 192.168.201.1 10597665/tftp-deploy-ltd01qmt/kernel/image.ittp-deploy-ltd01qmt/kernel/cmdline
10070 22:56:02.372124
10071 22:56:02.372198 Waiting for link
10072 22:56:02.532731
10073 22:56:02.532855 R8152: Initializing
10074 22:56:02.532922
10075 22:56:02.535894 Version 6 (ocp_data = 5c30)
10076 22:56:02.535997
10077 22:56:02.539045 R8152: Done initializing
10078 22:56:02.539119
10079 22:56:02.539186 Adding net device
10080 22:56:04.583424
10081 22:56:04.583560 done.
10082 22:56:04.583637
10083 22:56:04.583700 MAC: 00:24:32:30:7c:7b
10084 22:56:04.583760
10085 22:56:04.586842 Sending DHCP discover... done.
10086 22:56:04.586955
10087 22:56:07.597161 Waiting for reply... done.
10088 22:56:07.597321
10089 22:56:07.597415 Sending DHCP request... done.
10090 22:56:07.600989
10091 22:56:07.601090 Waiting for reply... done.
10092 22:56:07.601171
10093 22:56:07.603781 My ip is 192.168.201.14
10094 22:56:07.603917
10095 22:56:07.607730 The DHCP server ip is 192.168.201.1
10096 22:56:07.607882
10097 22:56:07.610591 TFTP server IP predefined by user: 192.168.201.1
10098 22:56:07.610720
10099 22:56:07.617066 Bootfile predefined by user: 10597665/tftp-deploy-ltd01qmt/kernel/image.itb
10100 22:56:07.617229
10101 22:56:07.620789 Sending tftp read request... done.
10102 22:56:07.620960
10103 22:56:07.623664 Waiting for the transfer...
10104 22:56:07.623855
10105 22:56:08.177251 00000000 ################################################################
10106 22:56:08.177388
10107 22:56:08.717739 00080000 ################################################################
10108 22:56:08.717877
10109 22:56:09.284151 00100000 ################################################################
10110 22:56:09.284285
10111 22:56:09.893466 00180000 ################################################################
10112 22:56:09.893602
10113 22:56:10.514574 00200000 ################################################################
10114 22:56:10.515102
10115 22:56:11.215115 00280000 ################################################################
10116 22:56:11.215649
10117 22:56:11.920362 00300000 ################################################################
10118 22:56:11.920902
10119 22:56:12.647565 00380000 ################################################################
10120 22:56:12.648180
10121 22:56:13.385372 00400000 ################################################################
10122 22:56:13.385954
10123 22:56:14.117223 00480000 ################################################################
10124 22:56:14.117799
10125 22:56:14.828373 00500000 ################################################################
10126 22:56:14.828937
10127 22:56:15.548730 00580000 ################################################################
10128 22:56:15.549252
10129 22:56:16.262189 00600000 ################################################################
10130 22:56:16.262730
10131 22:56:17.010266 00680000 ################################################################
10132 22:56:17.010814
10133 22:56:17.746879 00700000 ################################################################
10134 22:56:17.747415
10135 22:56:18.476200 00780000 ################################################################
10136 22:56:18.476773
10137 22:56:19.193138 00800000 ################################################################
10138 22:56:19.193652
10139 22:56:19.913796 00880000 ################################################################
10140 22:56:19.914361
10141 22:56:20.645366 00900000 ################################################################
10142 22:56:20.645919
10143 22:56:21.331653 00980000 ################################################################
10144 22:56:21.331802
10145 22:56:21.951283 00a00000 ################################################################
10146 22:56:21.951846
10147 22:56:22.634670 00a80000 ################################################################
10148 22:56:22.635422
10149 22:56:23.312149 00b00000 ################################################################
10150 22:56:23.312708
10151 22:56:24.012963 00b80000 ################################################################
10152 22:56:24.013576
10153 22:56:24.639438 00c00000 ################################################################
10154 22:56:24.639970
10155 22:56:25.274058 00c80000 ################################################################
10156 22:56:25.274206
10157 22:56:25.873076 00d00000 ################################################################
10158 22:56:25.873226
10159 22:56:26.411045 00d80000 ################################################################
10160 22:56:26.411223
10161 22:56:26.966835 00e00000 ################################################################
10162 22:56:26.967032
10163 22:56:27.550134 00e80000 ################################################################
10164 22:56:27.550311
10165 22:56:28.104932 00f00000 ################################################################
10166 22:56:28.105089
10167 22:56:28.665382 00f80000 ################################################################
10168 22:56:28.665537
10169 22:56:29.224213 01000000 ################################################################
10170 22:56:29.224355
10171 22:56:29.776563 01080000 ################################################################
10172 22:56:29.776754
10173 22:56:30.316701 01100000 ################################################################
10174 22:56:30.316852
10175 22:56:30.886095 01180000 ################################################################
10176 22:56:30.886239
10177 22:56:31.454055 01200000 ################################################################
10178 22:56:31.454196
10179 22:56:32.014002 01280000 ################################################################
10180 22:56:32.014154
10181 22:56:32.591405 01300000 ################################################################
10182 22:56:32.591564
10183 22:56:33.185691 01380000 ################################################################
10184 22:56:33.185837
10185 22:56:33.757688 01400000 ################################################################
10186 22:56:33.757835
10187 22:56:34.307514 01480000 ################################################################
10188 22:56:34.307661
10189 22:56:34.858498 01500000 ################################################################
10190 22:56:34.858644
10191 22:56:35.395938 01580000 ################################################################
10192 22:56:35.396119
10193 22:56:35.924636 01600000 ################################################################
10194 22:56:35.924787
10195 22:56:36.445085 01680000 ################################################################
10196 22:56:36.445243
10197 22:56:36.986120 01700000 ################################################################
10198 22:56:36.986274
10199 22:56:37.540148 01780000 ################################################################
10200 22:56:37.540303
10201 22:56:38.079808 01800000 ################################################################
10202 22:56:38.079947
10203 22:56:38.624933 01880000 ################################################################
10204 22:56:38.625106
10205 22:56:39.146479 01900000 ################################################################
10206 22:56:39.146625
10207 22:56:39.670411 01980000 ################################################################
10208 22:56:39.670571
10209 22:56:40.187157 01a00000 ############################################################### done.
10210 22:56:40.187316
10211 22:56:40.190508 The bootfile was 27774054 bytes long.
10212 22:56:40.190628
10213 22:56:40.193729 Sending tftp read request... done.
10214 22:56:40.193845
10215 22:56:40.193954 Waiting for the transfer...
10216 22:56:40.194061
10217 22:56:40.196788 00000000 # done.
10218 22:56:40.196912
10219 22:56:40.203635 Command line loaded dynamically from TFTP file: 10597665/tftp-deploy-ltd01qmt/kernel/cmdline
10220 22:56:40.203775
10221 22:56:40.223550 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10597665/extract-nfsrootfs-u6sgcmb6,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10222 22:56:40.223689
10223 22:56:40.226681 Loading FIT.
10224 22:56:40.226788
10225 22:56:40.230279 Image ramdisk-1 has 17639152 bytes.
10226 22:56:40.230388
10227 22:56:40.230482 Image fdt-1 has 46924 bytes.
10228 22:56:40.230572
10229 22:56:40.233775 Image kernel-1 has 10085945 bytes.
10230 22:56:40.233854
10231 22:56:40.243032 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10232 22:56:40.243121
10233 22:56:40.259407 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10234 22:56:40.262904
10235 22:56:40.266237 Choosing best match conf-1 for compat google,spherion-rev2.
10236 22:56:40.270942
10237 22:56:40.274982 Connected to device vid:did:rid of 1ae0:0028:00
10238 22:56:40.282328
10239 22:56:40.285322 tpm_get_response: command 0x17b, return code 0x0
10240 22:56:40.285407
10241 22:56:40.292453 ec_init: CrosEC protocol v3 supported (256, 248)
10242 22:56:40.292538
10243 22:56:40.295544 tpm_cleanup: add release locality here.
10244 22:56:40.298576
10245 22:56:40.298663 Shutting down all USB controllers.
10246 22:56:40.298731
10247 22:56:40.302013 Removing current net device
10248 22:56:40.302099
10249 22:56:40.308639 Exiting depthcharge with code 4 at timestamp: 71357026
10250 22:56:40.308761
10251 22:56:40.311820 LZMA decompressing kernel-1 to 0x821a6718
10252 22:56:40.311912
10253 22:56:40.315506 LZMA decompressing kernel-1 to 0x40000000
10254 22:56:41.581485
10255 22:56:41.581632 jumping to kernel
10256 22:56:41.582071 end: 2.2.4 bootloader-commands (duration 00:00:43) [common]
10257 22:56:41.582186 start: 2.2.5 auto-login-action (timeout 00:03:42) [common]
10258 22:56:41.582273 Setting prompt string to ['Linux version [0-9]']
10259 22:56:41.582352 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10260 22:56:41.582434 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10261 22:56:41.663664
10262 22:56:41.666791 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10263 22:56:41.670740 start: 2.2.5.1 login-action (timeout 00:03:42) [common]
10264 22:56:41.671129 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10265 22:56:41.671480 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10266 22:56:41.671795 Using line separator: #'\n'#
10267 22:56:41.671957 No login prompt set.
10268 22:56:41.672018 Parsing kernel messages
10269 22:56:41.672119 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10270 22:56:41.672223 [login-action] Waiting for messages, (timeout 00:03:42)
10271 22:56:41.689640 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j1612582-arm64-gcc-10-defconfig-arm64-chromebook-7xwc5) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Jun 5 22:41:02 UTC 2023
10272 22:56:41.693011 [ 0.000000] random: crng init done
10273 22:56:41.699824 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10274 22:56:41.703184 [ 0.000000] efi: UEFI not found.
10275 22:56:41.709375 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10276 22:56:41.716173 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10277 22:56:41.725686 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10278 22:56:41.735625 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10279 22:56:41.742321 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10280 22:56:41.749320 [ 0.000000] printk: bootconsole [mtk8250] enabled
10281 22:56:41.755758 [ 0.000000] NUMA: No NUMA configuration found
10282 22:56:41.762197 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10283 22:56:41.765198 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcda00-0x23efcffff]
10284 22:56:41.768859 [ 0.000000] Zone ranges:
10285 22:56:41.775492 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10286 22:56:41.778318 [ 0.000000] DMA32 empty
10287 22:56:41.785076 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10288 22:56:41.788271 [ 0.000000] Movable zone start for each node
10289 22:56:41.791707 [ 0.000000] Early memory node ranges
10290 22:56:41.798181 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10291 22:56:41.804601 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10292 22:56:41.811485 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10293 22:56:41.817658 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10294 22:56:41.824313 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10295 22:56:41.830868 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10296 22:56:41.887460 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10297 22:56:41.894246 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10298 22:56:41.901273 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10299 22:56:41.904664 [ 0.000000] psci: probing for conduit method from DT.
10300 22:56:41.910719 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10301 22:56:41.914079 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10302 22:56:41.920714 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10303 22:56:41.924193 [ 0.000000] psci: SMC Calling Convention v1.2
10304 22:56:41.930964 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10305 22:56:41.934055 [ 0.000000] Detected VIPT I-cache on CPU0
10306 22:56:41.940685 [ 0.000000] CPU features: detected: GIC system register CPU interface
10307 22:56:41.947020 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10308 22:56:41.953630 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10309 22:56:41.960256 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10310 22:56:41.970285 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10311 22:56:41.976794 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10312 22:56:41.980024 [ 0.000000] alternatives: applying boot alternatives
10313 22:56:41.986557 [ 0.000000] Fallback order for Node 0: 0
10314 22:56:41.993060 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10315 22:56:41.996405 [ 0.000000] Policy zone: Normal
10316 22:56:42.016012 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10597665/extract-nfsrootfs-u6sgcmb6,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10317 22:56:42.025985 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10318 22:56:42.037034 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10319 22:56:42.047070 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10320 22:56:42.053560 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10321 22:56:42.056894 <6>[ 0.000000] software IO TLB: area num 8.
10322 22:56:42.113335 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10323 22:56:42.262981 <6>[ 0.000000] Memory: 7955720K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 397048K reserved, 32768K cma-reserved)
10324 22:56:42.270082 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10325 22:56:42.276474 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10326 22:56:42.279737 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10327 22:56:42.286133 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10328 22:56:42.292927 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10329 22:56:42.296235 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10330 22:56:42.305896 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10331 22:56:42.312715 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10332 22:56:42.319167 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10333 22:56:42.325728 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10334 22:56:42.328952 <6>[ 0.000000] GICv3: 608 SPIs implemented
10335 22:56:42.332499 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10336 22:56:42.339051 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10337 22:56:42.341928 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10338 22:56:42.348786 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10339 22:56:42.362149 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10340 22:56:42.375165 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10341 22:56:42.381033 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10342 22:56:42.389672 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10343 22:56:42.402269 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10344 22:56:42.408863 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10345 22:56:42.416098 <6>[ 0.009182] Console: colour dummy device 80x25
10346 22:56:42.426093 <6>[ 0.013909] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10347 22:56:42.432643 <6>[ 0.024351] pid_max: default: 32768 minimum: 301
10348 22:56:42.435963 <6>[ 0.029218] LSM: Security Framework initializing
10349 22:56:42.442675 <6>[ 0.034155] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10350 22:56:42.452145 <6>[ 0.042016] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10351 22:56:42.461942 <6>[ 0.051486] cblist_init_generic: Setting adjustable number of callback queues.
10352 22:56:42.465223 <6>[ 0.058942] cblist_init_generic: Setting shift to 3 and lim to 1.
10353 22:56:42.472001 <6>[ 0.065282] cblist_init_generic: Setting shift to 3 and lim to 1.
10354 22:56:42.478270 <6>[ 0.071691] rcu: Hierarchical SRCU implementation.
10355 22:56:42.484790 <6>[ 0.076705] rcu: Max phase no-delay instances is 1000.
10356 22:56:42.491238 <6>[ 0.083725] EFI services will not be available.
10357 22:56:42.494549 <6>[ 0.088697] smp: Bringing up secondary CPUs ...
10358 22:56:42.502530 <6>[ 0.093752] Detected VIPT I-cache on CPU1
10359 22:56:42.508944 <6>[ 0.093822] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10360 22:56:42.516073 <6>[ 0.093852] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10361 22:56:42.519228 <6>[ 0.094186] Detected VIPT I-cache on CPU2
10362 22:56:42.525541 <6>[ 0.094237] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10363 22:56:42.535565 <6>[ 0.094252] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10364 22:56:42.539053 <6>[ 0.094508] Detected VIPT I-cache on CPU3
10365 22:56:42.545582 <6>[ 0.094556] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10366 22:56:42.551933 <6>[ 0.094569] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10367 22:56:42.558576 <6>[ 0.094875] CPU features: detected: Spectre-v4
10368 22:56:42.561950 <6>[ 0.094882] CPU features: detected: Spectre-BHB
10369 22:56:42.565114 <6>[ 0.094889] Detected PIPT I-cache on CPU4
10370 22:56:42.571687 <6>[ 0.094948] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10371 22:56:42.578462 <6>[ 0.094965] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10372 22:56:42.584822 <6>[ 0.095257] Detected PIPT I-cache on CPU5
10373 22:56:42.591830 <6>[ 0.095321] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10374 22:56:42.597951 <6>[ 0.095337] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10375 22:56:42.601770 <6>[ 0.095620] Detected PIPT I-cache on CPU6
10376 22:56:42.611296 <6>[ 0.095688] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10377 22:56:42.618097 <6>[ 0.095704] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10378 22:56:42.621092 <6>[ 0.096002] Detected PIPT I-cache on CPU7
10379 22:56:42.627878 <6>[ 0.096062] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10380 22:56:42.634603 <6>[ 0.096077] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10381 22:56:42.638270 <6>[ 0.096124] smp: Brought up 1 node, 8 CPUs
10382 22:56:42.644635 <6>[ 0.237540] SMP: Total of 8 processors activated.
10383 22:56:42.651187 <6>[ 0.242461] CPU features: detected: 32-bit EL0 Support
10384 22:56:42.657923 <6>[ 0.247857] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10385 22:56:42.664540 <6>[ 0.256713] CPU features: detected: Common not Private translations
10386 22:56:42.671129 <6>[ 0.263229] CPU features: detected: CRC32 instructions
10387 22:56:42.677557 <6>[ 0.268580] CPU features: detected: RCpc load-acquire (LDAPR)
10388 22:56:42.680601 <6>[ 0.274577] CPU features: detected: LSE atomic instructions
10389 22:56:42.688023 <6>[ 0.280394] CPU features: detected: Privileged Access Never
10390 22:56:42.694132 <6>[ 0.286174] CPU features: detected: RAS Extension Support
10391 22:56:42.700766 <6>[ 0.291783] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10392 22:56:42.703670 <6>[ 0.299005] CPU: All CPU(s) started at EL2
10393 22:56:42.710283 <6>[ 0.303321] alternatives: applying system-wide alternatives
10394 22:56:42.720540 <6>[ 0.313963] devtmpfs: initialized
10395 22:56:42.732979 <6>[ 0.322909] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10396 22:56:42.743426 <6>[ 0.332871] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10397 22:56:42.749775 <6>[ 0.341056] pinctrl core: initialized pinctrl subsystem
10398 22:56:42.752666 <6>[ 0.347903] DMI not present or invalid.
10399 22:56:42.759761 <6>[ 0.352306] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10400 22:56:42.769343 <6>[ 0.359178] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10401 22:56:42.776007 <6>[ 0.366763] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10402 22:56:42.785782 <6>[ 0.374982] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10403 22:56:42.789306 <6>[ 0.383222] audit: initializing netlink subsys (disabled)
10404 22:56:42.799003 <5>[ 0.388916] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10405 22:56:42.805743 <6>[ 0.389674] thermal_sys: Registered thermal governor 'step_wise'
10406 22:56:42.812106 <6>[ 0.396880] thermal_sys: Registered thermal governor 'power_allocator'
10407 22:56:42.815321 <6>[ 0.403134] cpuidle: using governor menu
10408 22:56:42.821899 <6>[ 0.414094] NET: Registered PF_QIPCRTR protocol family
10409 22:56:42.828571 <6>[ 0.419581] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10410 22:56:42.835054 <6>[ 0.426682] ASID allocator initialised with 32768 entries
10411 22:56:42.838298 <6>[ 0.433328] Serial: AMBA PL011 UART driver
10412 22:56:42.849034 <4>[ 0.442304] Trying to register duplicate clock ID: 134
10413 22:56:42.905388 <6>[ 0.502303] KASLR enabled
10414 22:56:42.920402 <6>[ 0.510090] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10415 22:56:42.926525 <6>[ 0.517100] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10416 22:56:42.933007 <6>[ 0.523590] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10417 22:56:42.940179 <6>[ 0.530596] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10418 22:56:42.946392 <6>[ 0.537083] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10419 22:56:42.953127 <6>[ 0.544088] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10420 22:56:42.959575 <6>[ 0.550576] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10421 22:56:42.965979 <6>[ 0.557582] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10422 22:56:42.969452 <6>[ 0.565110] ACPI: Interpreter disabled.
10423 22:56:42.978148 <6>[ 0.571599] iommu: Default domain type: Translated
10424 22:56:42.984424 <6>[ 0.576712] iommu: DMA domain TLB invalidation policy: strict mode
10425 22:56:42.987951 <5>[ 0.583367] SCSI subsystem initialized
10426 22:56:42.994881 <6>[ 0.587541] usbcore: registered new interface driver usbfs
10427 22:56:43.001312 <6>[ 0.593275] usbcore: registered new interface driver hub
10428 22:56:43.004283 <6>[ 0.598823] usbcore: registered new device driver usb
10429 22:56:43.011778 <6>[ 0.604955] pps_core: LinuxPPS API ver. 1 registered
10430 22:56:43.021383 <6>[ 0.610149] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10431 22:56:43.024919 <6>[ 0.619491] PTP clock support registered
10432 22:56:43.027839 <6>[ 0.623731] EDAC MC: Ver: 3.0.0
10433 22:56:43.035550 <6>[ 0.628939] FPGA manager framework
10434 22:56:43.041819 <6>[ 0.632622] Advanced Linux Sound Architecture Driver Initialized.
10435 22:56:43.045429 <6>[ 0.639397] vgaarb: loaded
10436 22:56:43.051650 <6>[ 0.642581] clocksource: Switched to clocksource arch_sys_counter
10437 22:56:43.055184 <5>[ 0.649004] VFS: Disk quotas dquot_6.6.0
10438 22:56:43.062206 <6>[ 0.653187] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10439 22:56:43.064911 <6>[ 0.660378] pnp: PnP ACPI: disabled
10440 22:56:43.073629 <6>[ 0.667078] NET: Registered PF_INET protocol family
10441 22:56:43.083341 <6>[ 0.672659] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10442 22:56:43.094539 <6>[ 0.684959] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10443 22:56:43.104886 <6>[ 0.693774] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10444 22:56:43.111197 <6>[ 0.701743] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10445 22:56:43.121066 <6>[ 0.710441] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10446 22:56:43.127518 <6>[ 0.720187] TCP: Hash tables configured (established 65536 bind 65536)
10447 22:56:43.134052 <6>[ 0.727047] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10448 22:56:43.144280 <6>[ 0.734245] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10449 22:56:43.150592 <6>[ 0.741940] NET: Registered PF_UNIX/PF_LOCAL protocol family
10450 22:56:43.157257 <6>[ 0.748121] RPC: Registered named UNIX socket transport module.
10451 22:56:43.160286 <6>[ 0.754274] RPC: Registered udp transport module.
10452 22:56:43.167196 <6>[ 0.759207] RPC: Registered tcp transport module.
10453 22:56:43.173444 <6>[ 0.764140] RPC: Registered tcp NFSv4.1 backchannel transport module.
10454 22:56:43.176775 <6>[ 0.770810] PCI: CLS 0 bytes, default 64
10455 22:56:43.180315 <6>[ 0.775154] Unpacking initramfs...
10456 22:56:43.189989 <6>[ 0.779305] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10457 22:56:43.196758 <6>[ 0.787955] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10458 22:56:43.203479 <6>[ 0.796825] kvm [1]: IPA Size Limit: 40 bits
10459 22:56:43.206954 <6>[ 0.801348] kvm [1]: GICv3: no GICV resource entry
10460 22:56:43.213445 <6>[ 0.806365] kvm [1]: disabling GICv2 emulation
10461 22:56:43.219996 <6>[ 0.811052] kvm [1]: GIC system register CPU interface enabled
10462 22:56:43.223297 <6>[ 0.817212] kvm [1]: vgic interrupt IRQ18
10463 22:56:43.230026 <6>[ 0.821563] kvm [1]: VHE mode initialized successfully
10464 22:56:43.233360 <5>[ 0.828106] Initialise system trusted keyrings
10465 22:56:43.239926 <6>[ 0.832898] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10466 22:56:43.250015 <6>[ 0.843286] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10467 22:56:43.256592 <5>[ 0.849716] NFS: Registering the id_resolver key type
10468 22:56:43.259358 <5>[ 0.855025] Key type id_resolver registered
10469 22:56:43.266047 <5>[ 0.859444] Key type id_legacy registered
10470 22:56:43.273241 <6>[ 0.863727] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10471 22:56:43.279720 <6>[ 0.870651] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10472 22:56:43.286408 <6>[ 0.878411] 9p: Installing v9fs 9p2000 file system support
10473 22:56:43.323310 <5>[ 0.916333] Key type asymmetric registered
10474 22:56:43.326240 <5>[ 0.920662] Asymmetric key parser 'x509' registered
10475 22:56:43.336312 <6>[ 0.925803] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10476 22:56:43.339517 <6>[ 0.933414] io scheduler mq-deadline registered
10477 22:56:43.342558 <6>[ 0.938176] io scheduler kyber registered
10478 22:56:43.362421 <6>[ 0.955901] EINJ: ACPI disabled.
10479 22:56:43.395312 <4>[ 0.982210] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10480 22:56:43.405775 <4>[ 0.992864] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10481 22:56:43.420725 <6>[ 1.014017] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10482 22:56:43.428529 <6>[ 1.022059] printk: console [ttyS0] disabled
10483 22:56:43.456446 <6>[ 1.046725] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10484 22:56:43.462992 <6>[ 1.056200] printk: console [ttyS0] enabled
10485 22:56:43.466435 <6>[ 1.056200] printk: console [ttyS0] enabled
10486 22:56:43.473331 <6>[ 1.065095] printk: bootconsole [mtk8250] disabled
10487 22:56:43.476651 <6>[ 1.065095] printk: bootconsole [mtk8250] disabled
10488 22:56:43.483078 <6>[ 1.076389] SuperH (H)SCI(F) driver initialized
10489 22:56:43.486778 <6>[ 1.081694] msm_serial: driver initialized
10490 22:56:43.501129 <6>[ 1.090759] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10491 22:56:43.510662 <6>[ 1.099312] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10492 22:56:43.517491 <6>[ 1.107854] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10493 22:56:43.527250 <6>[ 1.116481] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10494 22:56:43.537474 <6>[ 1.125187] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10495 22:56:43.544095 <6>[ 1.133907] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10496 22:56:43.553784 <6>[ 1.142449] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10497 22:56:43.560375 <6>[ 1.151266] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10498 22:56:43.570273 <6>[ 1.159811] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10499 22:56:43.582601 <6>[ 1.175672] loop: module loaded
10500 22:56:43.588493 <6>[ 1.181680] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10501 22:56:43.611383 <4>[ 1.205082] mtk-pmic-keys: Failed to locate of_node [id: -1]
10502 22:56:43.618074 <6>[ 1.211866] megasas: 07.719.03.00-rc1
10503 22:56:43.628199 <6>[ 1.221487] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10504 22:56:43.637088 <6>[ 1.229952] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10505 22:56:43.653232 <6>[ 1.246641] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10506 22:56:43.709635 <6>[ 1.296460] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9
10507 22:56:43.955767 <6>[ 1.549535] Freeing initrd memory: 17220K
10508 22:56:43.965969 <6>[ 1.559772] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10509 22:56:43.977008 <6>[ 1.570762] tun: Universal TUN/TAP device driver, 1.6
10510 22:56:43.980502 <6>[ 1.576851] thunder_xcv, ver 1.0
10511 22:56:43.983645 <6>[ 1.580357] thunder_bgx, ver 1.0
10512 22:56:43.986789 <6>[ 1.583852] nicpf, ver 1.0
10513 22:56:43.997450 <6>[ 1.587916] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10514 22:56:44.001189 <6>[ 1.595393] hns3: Copyright (c) 2017 Huawei Corporation.
10515 22:56:44.007706 <6>[ 1.600982] hclge is initializing
10516 22:56:44.011210 <6>[ 1.604556] e1000: Intel(R) PRO/1000 Network Driver
10517 22:56:44.017782 <6>[ 1.609685] e1000: Copyright (c) 1999-2006 Intel Corporation.
10518 22:56:44.020725 <6>[ 1.615697] e1000e: Intel(R) PRO/1000 Network Driver
10519 22:56:44.027315 <6>[ 1.620912] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10520 22:56:44.033888 <6>[ 1.627098] igb: Intel(R) Gigabit Ethernet Network Driver
10521 22:56:44.041166 <6>[ 1.632747] igb: Copyright (c) 2007-2014 Intel Corporation.
10522 22:56:44.047292 <6>[ 1.638590] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10523 22:56:44.053931 <6>[ 1.645109] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10524 22:56:44.057407 <6>[ 1.651585] sky2: driver version 1.30
10525 22:56:44.063891 <6>[ 1.656635] VFIO - User Level meta-driver version: 0.3
10526 22:56:44.071262 <6>[ 1.664975] usbcore: registered new interface driver usb-storage
10527 22:56:44.078231 <6>[ 1.671417] usbcore: registered new device driver onboard-usb-hub
10528 22:56:44.087062 <6>[ 1.680614] mt6397-rtc mt6359-rtc: registered as rtc0
10529 22:56:44.097194 <6>[ 1.686081] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-05T22:56:44 UTC (1686005804)
10530 22:56:44.099947 <6>[ 1.695680] i2c_dev: i2c /dev entries driver
10531 22:56:44.117721 <6>[ 1.707735] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10532 22:56:44.124567 <6>[ 1.718030] sdhci: Secure Digital Host Controller Interface driver
10533 22:56:44.131255 <6>[ 1.724468] sdhci: Copyright(c) Pierre Ossman
10534 22:56:44.137528 <6>[ 1.729908] Synopsys Designware Multimedia Card Interface Driver
10535 22:56:44.141090 <6>[ 1.736515] mmc0: CQHCI version 5.10
10536 22:56:44.148257 <6>[ 1.737123] sdhci-pltfm: SDHCI platform and OF driver helper
10537 22:56:44.154789 <6>[ 1.748530] ledtrig-cpu: registered to indicate activity on CPUs
10538 22:56:44.165687 <6>[ 1.755687] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10539 22:56:44.169276 <6>[ 1.763104] usbcore: registered new interface driver usbhid
10540 22:56:44.175552 <6>[ 1.768939] usbhid: USB HID core driver
10541 22:56:44.182274 <6>[ 1.773183] spi_master spi0: will run message pump with realtime priority
10542 22:56:44.226271 <6>[ 1.813143] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10543 22:56:44.245409 <6>[ 1.828320] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10544 22:56:44.248960 <6>[ 1.841894] mmc0: Command Queue Engine enabled
10545 22:56:44.255447 <6>[ 1.843940] cros-ec-spi spi0.0: Chrome EC device registered
10546 22:56:44.262290 <6>[ 1.846628] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10547 22:56:44.265237 <6>[ 1.859755] mmcblk0: mmc0:0001 DA4128 116 GiB
10548 22:56:44.279744 <6>[ 1.869899] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10549 22:56:44.286274 <6>[ 1.870644] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10550 22:56:44.292874 <6>[ 1.881353] NET: Registered PF_PACKET protocol family
10551 22:56:44.296465 <6>[ 1.886443] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10552 22:56:44.302841 <6>[ 1.890530] 9pnet: Installing 9P2000 support
10553 22:56:44.306274 <6>[ 1.896364] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10554 22:56:44.313090 <5>[ 1.900238] Key type dns_resolver registered
10555 22:56:44.319653 <6>[ 1.906022] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10556 22:56:44.323149 <6>[ 1.910420] registered taskstats version 1
10557 22:56:44.325870 <5>[ 1.920826] Loading compiled-in X.509 certificates
10558 22:56:44.367915 <4>[ 1.954327] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10559 22:56:44.377262 <4>[ 1.965067] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10560 22:56:44.388193 <3>[ 1.978046] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10561 22:56:44.400072 <6>[ 1.993685] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10562 22:56:44.406497 <6>[ 2.000454] xhci-mtk 11200000.usb: xHCI Host Controller
10563 22:56:44.413662 <6>[ 2.005965] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10564 22:56:44.423564 <6>[ 2.013824] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10565 22:56:44.429866 <6>[ 2.023254] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10566 22:56:44.436896 <6>[ 2.029358] xhci-mtk 11200000.usb: xHCI Host Controller
10567 22:56:44.443462 <6>[ 2.034975] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10568 22:56:44.450364 <6>[ 2.042654] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10569 22:56:44.456899 <6>[ 2.050543] hub 1-0:1.0: USB hub found
10570 22:56:44.460012 <6>[ 2.054601] hub 1-0:1.0: 1 port detected
10571 22:56:44.470335 <6>[ 2.058961] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10572 22:56:44.473445 <6>[ 2.067786] hub 2-0:1.0: USB hub found
10573 22:56:44.477022 <6>[ 2.071820] hub 2-0:1.0: 1 port detected
10574 22:56:44.485507 <6>[ 2.078990] mtk-msdc 11f70000.mmc: Got CD GPIO
10575 22:56:44.506894 <6>[ 2.096761] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10576 22:56:44.513626 <6>[ 2.104795] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10577 22:56:44.523383 <4>[ 2.112768] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10578 22:56:44.532956 <6>[ 2.122433] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10579 22:56:44.539476 <6>[ 2.130516] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10580 22:56:44.549852 <6>[ 2.138542] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10581 22:56:44.556190 <6>[ 2.146457] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10582 22:56:44.562895 <6>[ 2.154278] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10583 22:56:44.572495 <6>[ 2.162102] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10584 22:56:44.582886 <6>[ 2.172853] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10585 22:56:44.592775 <6>[ 2.181228] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10586 22:56:44.599053 <6>[ 2.189582] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10587 22:56:44.609461 <6>[ 2.197925] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10588 22:56:44.616429 <6>[ 2.206268] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10589 22:56:44.625854 <6>[ 2.214612] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10590 22:56:44.632588 <6>[ 2.222955] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10591 22:56:44.642484 <6>[ 2.231297] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10592 22:56:44.649143 <6>[ 2.239640] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10593 22:56:44.658734 <6>[ 2.247987] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10594 22:56:44.665594 <6>[ 2.256331] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10595 22:56:44.675516 <6>[ 2.264676] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10596 22:56:44.681972 <6>[ 2.273018] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10597 22:56:44.691830 <6>[ 2.281362] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10598 22:56:44.698304 <6>[ 2.289708] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10599 22:56:44.705516 <6>[ 2.298640] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10600 22:56:44.712724 <6>[ 2.306084] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10601 22:56:44.719515 <6>[ 2.313101] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10602 22:56:44.730780 <6>[ 2.320192] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10603 22:56:44.737119 <6>[ 2.327484] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10604 22:56:44.746721 <6>[ 2.334390] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10605 22:56:44.753725 <6>[ 2.343531] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10606 22:56:44.763379 <6>[ 2.352659] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10607 22:56:44.773362 <6>[ 2.361966] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10608 22:56:44.782840 <6>[ 2.371443] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10609 22:56:44.793212 <6>[ 2.380917] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10610 22:56:44.802824 <6>[ 2.390044] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10611 22:56:44.809162 <6>[ 2.399518] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10612 22:56:44.819457 <6>[ 2.408645] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10613 22:56:44.828996 <6>[ 2.417948] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10614 22:56:44.839062 <6>[ 2.428116] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10615 22:56:44.849889 <6>[ 2.439826] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10616 22:56:44.856564 <6>[ 2.449757] Trying to probe devices needed for running init ...
10617 22:56:44.893022 <6>[ 2.482861] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10618 22:56:45.047326 <6>[ 2.640191] hub 1-1:1.0: USB hub found
10619 22:56:45.049935 <6>[ 2.644680] hub 1-1:1.0: 4 ports detected
10620 22:56:45.172863 <6>[ 2.763021] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10621 22:56:45.197979 <6>[ 2.790840] hub 2-1:1.0: USB hub found
10622 22:56:45.200699 <6>[ 2.795204] hub 2-1:1.0: 3 ports detected
10623 22:56:45.372499 <6>[ 2.962855] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10624 22:56:45.505123 <6>[ 3.098797] hub 1-1.4:1.0: USB hub found
10625 22:56:45.508469 <6>[ 3.103471] hub 1-1.4:1.0: 2 ports detected
10626 22:56:45.584951 <6>[ 3.175091] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10627 22:56:45.805285 <6>[ 3.394872] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10628 22:56:45.996153 <6>[ 3.586855] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10629 22:56:57.132815 <6>[ 14.731412] ALSA device list:
10630 22:56:57.139142 <6>[ 14.734669] No soundcards found.
10631 22:56:57.151746 <6>[ 14.747052] Freeing unused kernel memory: 8384K
10632 22:56:57.154748 <6>[ 14.751979] Run /init as init process
10633 22:56:57.165119 Loading, please wait...
10634 22:56:57.184379 Starting version 247.3-7+deb11u2
10635 22:56:57.503965 <6>[ 15.095955] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10636 22:56:57.514572 <6>[ 15.109648] remoteproc remoteproc0: scp is available
10637 22:56:57.524863 <4>[ 15.115957] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10638 22:56:57.531059 <6>[ 15.125873] remoteproc remoteproc0: powering up scp
10639 22:56:57.540758 <4>[ 15.131078] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10640 22:56:57.547448 <3>[ 15.140929] remoteproc remoteproc0: request_firmware failed: -2
10641 22:56:57.558801 <6>[ 15.150565] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10642 22:56:57.565035 <6>[ 15.158406] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10643 22:56:57.575878 <6>[ 15.167642] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10644 22:56:57.586763 <6>[ 15.178471] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10645 22:56:57.596254 <3>[ 15.187517] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10646 22:56:57.603294 <3>[ 15.195705] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10647 22:56:57.609907 <6>[ 15.198363] mc: Linux media interface: v0.10
10648 22:56:57.616926 <4>[ 15.199876] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10649 22:56:57.620416 <4>[ 15.199876] Fallback method does not support PEC.
10650 22:56:57.630222 <3>[ 15.203834] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10651 22:56:57.637118 <4>[ 15.205294] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10652 22:56:57.643584 <4>[ 15.205471] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10653 22:56:57.653490 <3>[ 15.217047] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10654 22:56:57.661151 <3>[ 15.228432] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10655 22:56:57.667466 <6>[ 15.255965] videodev: Linux video capture interface: v2.00
10656 22:56:57.677557 <3>[ 15.261119] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10657 22:56:57.684122 <3>[ 15.261686] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10658 22:56:57.690243 <6>[ 15.278076] usbcore: registered new interface driver r8152
10659 22:56:57.697023 <3>[ 15.284408] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10660 22:56:57.703492 <6>[ 15.296095] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10661 22:56:57.713729 <3>[ 15.298248] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10662 22:56:57.719963 <6>[ 15.305115] pci_bus 0000:00: root bus resource [bus 00-ff]
10663 22:56:57.727027 <3>[ 15.313184] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10664 22:56:57.733207 <3>[ 15.313251] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10665 22:56:57.743436 <6>[ 15.317244] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10666 22:56:57.750129 <6>[ 15.318927] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10667 22:56:57.759526 <3>[ 15.327042] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10668 22:56:57.769632 <6>[ 15.335086] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10669 22:56:57.776664 <3>[ 15.344388] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10670 22:56:57.783095 <6>[ 15.351634] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10671 22:56:57.793034 <3>[ 15.359593] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10672 22:56:57.799886 <3>[ 15.359653] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10673 22:56:57.806197 <6>[ 15.369518] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10674 22:56:57.816082 <6>[ 15.375368] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10675 22:56:57.825814 <6>[ 15.375713] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10676 22:56:57.835797 <3>[ 15.377587] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10677 22:56:57.842594 <6>[ 15.384136] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10678 22:56:57.845873 <6>[ 15.384929] pci 0000:00:00.0: supports D1 D2
10679 22:56:57.852687 <6>[ 15.384936] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10680 22:56:57.862263 <6>[ 15.386850] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10681 22:56:57.869051 <6>[ 15.386967] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10682 22:56:57.875889 <6>[ 15.386997] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10683 22:56:57.882093 <6>[ 15.387016] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10684 22:56:57.888644 <6>[ 15.387034] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10685 22:56:57.895526 <6>[ 15.387145] pci 0000:01:00.0: supports D1 D2
10686 22:56:57.902230 <6>[ 15.387149] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10687 22:56:57.909069 <3>[ 15.391965] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10688 22:56:57.915199 <6>[ 15.399247] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10689 22:56:57.925435 <6>[ 15.399601] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10690 22:56:57.931854 <6>[ 15.399625] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10691 22:56:57.942028 <6>[ 15.399689] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10692 22:56:57.948663 <6>[ 15.399732] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10693 22:56:57.958767 <6>[ 15.399760] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10694 22:56:57.961449 <6>[ 15.399803] pci 0000:00:00.0: PCI bridge to [bus 01]
10695 22:56:57.971238 <6>[ 15.399841] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10696 22:56:57.979252 <6>[ 15.400547] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10697 22:56:57.984674 <3>[ 15.407563] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10698 22:56:57.992156 <3>[ 15.407572] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10699 22:56:58.001147 <3>[ 15.407618] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10700 22:56:58.008086 <6>[ 15.407891] usbcore: registered new interface driver cdc_ether
10701 22:56:58.014600 <6>[ 15.418045] usbcore: registered new interface driver r8153_ecm
10702 22:56:58.017813 <6>[ 15.418906] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10703 22:56:58.024319 <6>[ 15.419252] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10704 22:56:58.034211 <4>[ 15.422657] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10705 22:56:58.040726 <4>[ 15.422668] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10706 22:56:58.047232 <6>[ 15.428136] Bluetooth: Core ver 2.22
10707 22:56:58.054363 <6>[ 15.438131] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10708 22:56:58.060783 <5>[ 15.438171] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10709 22:56:58.067400 <6>[ 15.442161] NET: Registered PF_BLUETOOTH protocol family
10710 22:56:58.073818 <6>[ 15.442164] Bluetooth: HCI device and connection manager initialized
10711 22:56:58.077085 <6>[ 15.442189] Bluetooth: HCI socket layer initialized
10712 22:56:58.083942 <6>[ 15.442198] Bluetooth: L2CAP socket layer initialized
10713 22:56:58.086841 <6>[ 15.442211] Bluetooth: SCO socket layer initialized
10714 22:56:58.096969 <5>[ 15.450063] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10715 22:56:58.103693 <6>[ 15.455651] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10716 22:56:58.113357 <6>[ 15.456004] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10717 22:56:58.120202 <6>[ 15.456273] usbcore: registered new interface driver uvcvideo
10718 22:56:58.129726 <4>[ 15.462041] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10719 22:56:58.133221 <6>[ 15.478758] r8152 2-1.3:1.0 eth0: v1.12.13
10720 22:56:58.140251 <6>[ 15.483182] cfg80211: failed to load regulatory.db
10721 22:56:58.143081 <6>[ 15.492827] usbcore: registered new interface driver btusb
10722 22:56:58.156059 <4>[ 15.493570] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10723 22:56:58.159485 <3>[ 15.493580] Bluetooth: hci0: Failed to load firmware file (-2)
10724 22:56:58.166671 <3>[ 15.493584] Bluetooth: hci0: Failed to set up firmware (-2)
10725 22:56:58.175892 <4>[ 15.493587] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10726 22:56:58.182672 <6>[ 15.503939] r8152 2-1.3:1.0 enx002432307c7b: renamed from eth0
10727 22:56:58.189840 <6>[ 15.560899] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10728 22:56:58.196348 <6>[ 15.791055] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10729 22:56:58.222442 <6>[ 15.817820] mt7921e 0000:01:00.0: ASIC revision: 79610010
10730 22:56:58.329675 <4>[ 15.918383] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10731 22:56:58.333132 Begin: Loading essential drivers ... done.
10732 22:56:58.336384 Begin: Running /scripts/init-premount ... done.
10733 22:56:58.346550 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10734 22:56:58.352853 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10735 22:56:58.355899 Device /sys/class/net/enx002432307c7b found
10736 22:56:58.359344 done.
10737 22:56:58.452921 <4>[ 16.041225] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10738 22:56:58.467069 IP-Config: enx002432307c7b hardware address 00:24:32:30:7c:7b mtu 1500 DHCP
10739 22:56:58.571972 <4>[ 16.160608] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10740 22:56:58.687899 <4>[ 16.276413] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10741 22:56:58.803650 <4>[ 16.392364] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10742 22:56:58.919867 <4>[ 16.508268] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10743 22:56:59.035960 <4>[ 16.624238] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10744 22:56:59.382507 <4>[ 16.740081] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10745 22:56:59.382684 <4>[ 16.856157] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10746 22:56:59.383612 <4>[ 16.972146] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10747 22:56:59.490293 <3>[ 17.085996] mt7921e 0000:01:00.0: hardware init failed
10748 22:56:59.529447 <6>[ 17.125088] r8152 2-1.3:1.0 enx002432307c7b: carrier on
10749 22:56:59.590496 IP-Config: no response after 2 secs - giving up
10750 22:56:59.630668 IP-Config: enx002432307c7b hardware address 00:24:32:30:7c:7b mtu 1500 DHCP
10751 22:57:00.283121 IP-Config: enx002432307c7b complete (dhcp from 192.168.201.1):
10752 22:57:00.289864 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10753 22:57:00.299445 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10754 22:57:00.305863 host : mt8192-asurada-spherion-r0-cbg-2
10755 22:57:00.313001 domain : lava-rack
10756 22:57:00.315584 rootserver: 192.168.201.1 rootpath:
10757 22:57:00.315820 filename :
10758 22:57:00.327244 done.
10759 22:57:00.333610 Begin: Running /scripts/nfs-bottom ... done.
10760 22:57:00.351125 Begin: Running /scripts/init-bottom ... done.
10761 22:57:01.489101 <6>[ 19.084599] NET: Registered PF_INET6 protocol family
10762 22:57:01.495668 <6>[ 19.091570] Segment Routing with IPv6
10763 22:57:01.499145 <6>[ 19.095577] In-situ OAM (IOAM) with IPv6
10764 22:57:01.618249 <30>[ 19.193699] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10765 22:57:01.621391 <30>[ 19.217635] systemd[1]: Detected architecture arm64.
10766 22:57:01.643895
10767 22:57:01.646871 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10768 22:57:01.647014
10769 22:57:01.665613 <30>[ 19.261072] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10770 22:57:02.252051 <30>[ 19.844727] systemd[1]: Queued start job for default target Graphical Interface.
10771 22:57:02.288017 <30>[ 19.883959] systemd[1]: Created slice system-getty.slice.
10772 22:57:02.294595 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10773 22:57:02.311724 <30>[ 19.907583] systemd[1]: Created slice system-modprobe.slice.
10774 22:57:02.318635 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10775 22:57:02.335843 <30>[ 19.931441] systemd[1]: Created slice system-serial\x2dgetty.slice.
10776 22:57:02.345636 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10777 22:57:02.360218 <30>[ 19.955896] systemd[1]: Created slice User and Session Slice.
10778 22:57:02.366606 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10779 22:57:02.386776 <30>[ 19.979475] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10780 22:57:02.396680 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10781 22:57:02.414724 <30>[ 20.007000] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10782 22:57:02.420905 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10783 22:57:02.441867 <30>[ 20.030985] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10784 22:57:02.448713 <30>[ 20.043017] systemd[1]: Reached target Local Encrypted Volumes.
10785 22:57:02.455527 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10786 22:57:02.471182 <30>[ 20.067045] systemd[1]: Reached target Paths.
10787 22:57:02.474328 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10788 22:57:02.491286 <30>[ 20.086958] systemd[1]: Reached target Remote File Systems.
10789 22:57:02.497897 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10790 22:57:02.515468 <30>[ 20.111127] systemd[1]: Reached target Slices.
10791 22:57:02.521731 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10792 22:57:02.535746 <30>[ 20.130922] systemd[1]: Reached target Swap.
10793 22:57:02.538628 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10794 22:57:02.558946 <30>[ 20.151240] systemd[1]: Listening on initctl Compatibility Named Pipe.
10795 22:57:02.565580 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10796 22:57:02.581195 <30>[ 20.176811] systemd[1]: Listening on Journal Audit Socket.
10797 22:57:02.588024 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10798 22:57:02.604863 <30>[ 20.200570] systemd[1]: Listening on Journal Socket (/dev/log).
10799 22:57:02.611399 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10800 22:57:02.627099 <30>[ 20.223205] systemd[1]: Listening on Journal Socket.
10801 22:57:02.634120 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10802 22:57:02.651622 <30>[ 20.244189] systemd[1]: Listening on Network Service Netlink Socket.
10803 22:57:02.658263 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10804 22:57:02.674728 <30>[ 20.270048] systemd[1]: Listening on udev Control Socket.
10805 22:57:02.680847 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10806 22:57:02.695644 <30>[ 20.291179] systemd[1]: Listening on udev Kernel Socket.
10807 22:57:02.702269 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10808 22:57:02.735936 <30>[ 20.331148] systemd[1]: Mounting Huge Pages File System...
10809 22:57:02.742305 Mounting [0;1;39mHuge Pages File System[0m...
10810 22:57:02.760701 <30>[ 20.353435] systemd[1]: Mounting POSIX Message Queue File System...
10811 22:57:02.763973 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10812 22:57:02.782064 <30>[ 20.377460] systemd[1]: Mounting Kernel Debug File System...
10813 22:57:02.787933 Mounting [0;1;39mKernel Debug File System[0m...
10814 22:57:02.806938 <30>[ 20.399250] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10815 22:57:02.819099 <30>[ 20.411342] systemd[1]: Starting Create list of static device nodes for the current kernel...
10816 22:57:02.825175 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10817 22:57:02.845659 <30>[ 20.441759] systemd[1]: Starting Load Kernel Module configfs...
10818 22:57:02.852569 Starting [0;1;39mLoad Kernel Module configfs[0m...
10819 22:57:02.869730 <30>[ 20.465430] systemd[1]: Starting Load Kernel Module drm...
10820 22:57:02.876289 Starting [0;1;39mLoad Kernel Module drm[0m...
10821 22:57:02.893519 <30>[ 20.489407] systemd[1]: Starting Load Kernel Module fuse...
10822 22:57:02.901874 Starting [0;1;39mLoad Kernel Module fuse[0m...
10823 22:57:02.932631 <6>[ 20.528476] fuse: init (API version 7.37)
10824 22:57:02.942348 <30>[ 20.530859] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10825 22:57:02.950884 <30>[ 20.547061] systemd[1]: Starting Journal Service...
10826 22:57:02.957638 Starting [0;1;39mJournal Service[0m...
10827 22:57:02.980235 <30>[ 20.575985] systemd[1]: Starting Load Kernel Modules...
10828 22:57:02.986992 Starting [0;1;39mLoad Kernel Modules[0m...
10829 22:57:03.004753 <30>[ 20.597284] systemd[1]: Starting Remount Root and Kernel File Systems...
10830 22:57:03.010898 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10831 22:57:03.026531 <30>[ 20.622641] systemd[1]: Starting Coldplug All udev Devices...
10832 22:57:03.033778 Starting [0;1;39mColdplug All udev Devices[0m...
10833 22:57:03.050297 <30>[ 20.646145] systemd[1]: Mounted Huge Pages File System.
10834 22:57:03.056845 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10835 22:57:03.071392 <30>[ 20.667413] systemd[1]: Mounted POSIX Message Queue File System.
10836 22:57:03.078090 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10837 22:57:03.095227 <30>[ 20.691333] systemd[1]: Mounted Kernel Debug File System.
10838 22:57:03.101983 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10839 22:57:03.116202 <3>[ 20.708968] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10840 22:57:03.126257 <30>[ 20.719108] systemd[1]: Finished Create list of static device nodes for the current kernel.
10841 22:57:03.136726 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10842 22:57:03.147073 <3>[ 20.739745] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10843 22:57:03.154199 <30>[ 20.749552] systemd[1]: modprobe@configfs.service: Succeeded.
10844 22:57:03.160433 <30>[ 20.756216] systemd[1]: Finished Load Kernel Module configfs.
10845 22:57:03.167041 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10846 22:57:03.183881 <30>[ 20.779825] systemd[1]: modprobe@drm.service: Succeeded.
10847 22:57:03.191357 <30>[ 20.786065] systemd[1]: Finished Load Kernel Module drm.
10848 22:57:03.200625 <3>[ 20.788579] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10849 22:57:03.207693 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10850 22:57:03.220874 <30>[ 20.816187] systemd[1]: modprobe@fuse.service: Succeeded.
10851 22:57:03.227669 <30>[ 20.822638] systemd[1]: Finished Load Kernel Module fuse.
10852 22:57:03.237705 <3>[ 20.823310] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10853 22:57:03.243796 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10854 22:57:03.260974 <30>[ 20.856032] systemd[1]: Finished Load Kernel Modules.
10855 22:57:03.270997 <3>[ 20.858588] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10856 22:57:03.273815 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10857 22:57:03.292843 <30>[ 20.888259] systemd[1]: Finished Remount Root and Kernel File Systems.
10858 22:57:03.303110 <3>[ 20.892803] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10859 22:57:03.309758 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10860 22:57:03.335620 <3>[ 20.927718] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10861 22:57:03.365978 <3>[ 20.957996] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10862 22:57:03.372454 <30>[ 20.958820] systemd[1]: Mounting FUSE Control File System...
10863 22:57:03.378955 Mounting [0;1;39mFUSE Control File System[0m...
10864 22:57:03.396572 <3>[ 20.988033] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10865 22:57:03.407912 <30>[ 21.000060] systemd[1]: Mounting Kernel Configuration File System...
10866 22:57:03.411003 Mounting [0;1;39mKernel Configuration File System[0m...
10867 22:57:03.425712 <3>[ 21.017650] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10868 22:57:03.441016 <30>[ 21.033253] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10869 22:57:03.450878 <30>[ 21.042270] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10870 22:57:03.459348 <30>[ 21.054892] systemd[1]: Starting Load/Save Random Seed...
10871 22:57:03.466365 Starting [0;1;39mLoad/Save Random Seed[0m...
10872 22:57:03.482650 <30>[ 21.077387] systemd[1]: Starting Apply Kernel Variables...
10873 22:57:03.489420 Starting [0;1;39mApply Kernel Variables[0m...
10874 22:57:03.506773 <30>[ 21.102014] systemd[1]: Starting Create System Users...
10875 22:57:03.513066 Starting [0;1;39mCreate System Users[0m...
10876 22:57:03.529319 <30>[ 21.124705] systemd[1]: Started Journal Service.
10877 22:57:03.535709 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10878 22:57:03.549321 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10879 22:57:03.570213 <4>[ 21.156335] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10880 22:57:03.580693 <3>[ 21.172012] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10881 22:57:03.586774 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10882 22:57:03.600401 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10883 22:57:03.620054 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10884 22:57:03.631189 See 'systemctl status systemd-udev-trigger.service' for details.
10885 22:57:03.648280 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10886 22:57:03.695837 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10887 22:57:03.716444 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10888 22:57:03.750664 <46>[ 21.343499] systemd-journald[291]: Received client request to flush runtime journal.
10889 22:57:03.767756 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10890 22:57:04.951114 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10891 22:57:04.963607 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10892 22:57:04.978819 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10893 22:57:05.030501 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10894 22:57:05.279314 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10895 22:57:05.328495 Starting [0;1;39mNetwork Service[0m...
10896 22:57:05.367948 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10897 22:57:05.386934 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10898 22:57:05.663814 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10899 22:57:05.685187 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10900 22:57:05.722841 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10901 22:57:05.905545 <6>[ 23.501858] remoteproc remoteproc0: powering up scp
10902 22:57:05.928791 <4>[ 23.521698] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10903 22:57:05.935231 <3>[ 23.531560] remoteproc remoteproc0: request_firmware failed: -2
10904 22:57:05.945182 <3>[ 23.537748] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
10905 22:57:06.063736 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10906 22:57:06.082178 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10907 22:57:06.095311 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10908 22:57:06.115483 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10909 22:57:06.167034 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10910 22:57:06.738988 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10911 22:57:07.409346 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10912 22:57:07.451357 Starting [0;1;39mNetwork Name Resolution[0m...
10913 22:57:07.477767 Starting [0;1;39mNetwork Time Synchronization[0m...
10914 22:57:07.493814 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10915 22:57:07.541229 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10916 22:57:07.790682 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10917 22:57:07.806863 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10918 22:57:07.826251 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10919 22:57:07.838724 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10920 22:57:07.855146 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10921 22:57:07.950252 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10922 22:57:07.978208 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10923 22:57:07.997062 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10924 22:57:08.026253 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10925 22:57:08.038601 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10926 22:57:08.064099 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10927 22:57:08.082731 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10928 22:57:08.099143 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10929 22:57:08.139479 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10930 22:57:08.847744 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10931 22:57:09.215093 Starting [0;1;39mUser Login Management[0m...
10932 22:57:09.236108 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10933 22:57:09.251607 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10934 22:57:09.269600 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10935 22:57:09.306863 Starting [0;1;39mPermit User Sessions[0m...
10936 22:57:09.430798 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10937 22:57:09.444480 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10938 22:57:09.491741 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10939 22:57:09.510008 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10940 22:57:09.527263 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10941 22:57:09.544309 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10942 22:57:09.560022 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10943 22:57:09.575060 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10944 22:57:09.627374 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10945 22:57:09.915763 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10946 22:57:10.269219
10947 22:57:10.269384
10948 22:57:10.272799 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10949 22:57:10.272897
10950 22:57:10.275917 debian-bullseye-arm64 login: root (automatic login)
10951 22:57:10.276028
10952 22:57:10.276118
10953 22:57:10.566094 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Mon Jun 5 22:41:02 UTC 2023 aarch64
10954 22:57:10.566234
10955 22:57:10.572714 The programs included with the Debian GNU/Linux system are free software;
10956 22:57:10.579329 the exact distribution terms for each program are described in the
10957 22:57:10.582975 individual files in /usr/share/doc/*/copyright.
10958 22:57:10.583058
10959 22:57:10.589435 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10960 22:57:10.592600 permitted by applicable law.
10961 22:57:10.882311 Matched prompt #10: / #
10963 22:57:10.883632 Setting prompt string to ['/ #']
10964 22:57:10.884228 end: 2.2.5.1 login-action (duration 00:00:29) [common]
10966 22:57:10.885252 end: 2.2.5 auto-login-action (duration 00:00:29) [common]
10967 22:57:10.885701 start: 2.2.6 expect-shell-connection (timeout 00:03:13) [common]
10968 22:57:10.886068 Setting prompt string to ['/ #']
10969 22:57:10.886397 Forcing a shell prompt, looking for ['/ #']
10971 22:57:10.936927 / #
10972 22:57:10.937603 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10973 22:57:10.938079 Waiting using forced prompt support (timeout 00:02:30)
10974 22:57:10.943379
10975 22:57:10.944164 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10976 22:57:10.944645 start: 2.2.7 export-device-env (timeout 00:03:13) [common]
10978 22:57:11.045788 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10597665/extract-nfsrootfs-u6sgcmb6'
10979 22:57:11.051940 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10597665/extract-nfsrootfs-u6sgcmb6'
10981 22:57:11.153309 / # export NFS_SERVER_IP='192.168.201.1'
10982 22:57:11.158846 export NFS_SERVER_IP='192.168.201.1'
10983 22:57:11.159187 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10984 22:57:11.159322 end: 2.2 depthcharge-retry (duration 00:01:48) [common]
10985 22:57:11.159445 end: 2 depthcharge-action (duration 00:01:48) [common]
10986 22:57:11.159542 start: 3 lava-test-retry (timeout 00:01:00) [common]
10987 22:57:11.159631 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
10988 22:57:11.159716 Using namespace: common
10990 22:57:11.260132 / # #
10991 22:57:11.260792 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10992 22:57:11.266635 #
10993 22:57:11.267578 Using /lava-10597665
10995 22:57:11.368824 / # export SHELL=/bin/sh
10996 22:57:11.375128 export SHELL=/bin/sh
10998 22:57:11.476752 / # . /lava-10597665/environment
10999 22:57:11.482645 . /lava-10597665/environment
11001 22:57:11.588880 / # /lava-10597665/bin/lava-test-runner /lava-10597665/0
11002 22:57:11.589233 Test shell timeout: 10s (minimum of the action and connection timeout)
11003 22:57:11.594997 /lava-10597665/bin/lava-test-runner /lava-10597665/0
11004 22:57:11.855502 + export TESTRUN_ID=0_dmesg
11005 22:57:11.858909 + cd /lava-10597665/0/tests/0_dmesg
11006 22:57:11.861870 + cat uuid
11007 22:57:11.881269 + UUID=10597665_<8>[ 29.474169] <LAVA_SIGNAL_STARTRUN 0_dmesg 10597665_1.6.2.3.1>
11008 22:57:11.881709 1.6.2.3.1
11009 22:57:11.882057 + set +x
11010 22:57:11.882654 Received signal: <STARTRUN> 0_dmesg 10597665_1.6.2.3.1
11011 22:57:11.883007 Starting test lava.0_dmesg (10597665_1.6.2.3.1)
11012 22:57:11.883418 Skipping test definition patterns.
11013 22:57:11.887341 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
11014 22:57:12.106831 <8>[ 29.700402] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
11015 22:57:12.107837 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
11017 22:57:12.250870 <8>[ 29.844206] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
11018 22:57:12.251768 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
11020 22:57:12.736000 <8>[ 30.329135] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
11021 22:57:12.737005 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
11023 22:57:12.742202 + <8>[ 30.338630] <LAVA_SIGNAL_ENDRUN 0_dmesg 10597665_1.6.2.3.1>
11024 22:57:12.742802 set +x
11025 22:57:12.743542 Received signal: <ENDRUN> 0_dmesg 10597665_1.6.2.3.1
11026 22:57:12.744108 Ending use of test pattern.
11027 22:57:12.744442 Ending test lava.0_dmesg (10597665_1.6.2.3.1), duration 0.86
11029 22:57:12.750005 <LAVA_TEST_RUNNER EXIT>
11030 22:57:12.750713 ok: lava_test_shell seems to have completed
11031 22:57:12.751258 alert: pass
crit: pass
emerg: pass
11032 22:57:12.751665 end: 3.1 lava-test-shell (duration 00:00:02) [common]
11033 22:57:12.752124 end: 3 lava-test-retry (duration 00:00:02) [common]
11034 22:57:12.752563 start: 4 lava-test-retry (timeout 00:01:00) [common]
11035 22:57:12.752967 start: 4.1 lava-test-shell (timeout 00:01:00) [common]
11036 22:57:12.753301 Using namespace: common
11038 22:57:12.854403 / # #
11039 22:57:12.854593 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
11040 22:57:12.854757 Using /lava-10597665
11042 22:57:12.955167 export SHELL=/bin/sh
11043 22:57:12.955981 #
11045 22:57:13.057414 / # export SHELL=/bin/sh. /lava-10597665/environment
11046 22:57:13.057860
11048 22:57:13.158869 / # . /lava-10597665/environment/lava-10597665/bin/lava-test-runner /lava-10597665/1
11049 22:57:13.159192 Test shell timeout: 10s (minimum of the action and connection timeout)
11050 22:57:13.159505
11051 22:57:13.164328 / # /lava-10597665/bin/lava-test-runner /lava-10597665/1
11052 22:57:13.290995 + export TESTRUN_ID=1_bootrr
11053 22:57:13.294015 + cd /lava-10597665/1/tests/1_bootrr
11054 22:57:13.297384 + cat uuid
11055 22:57:13.310078 + UUID=10597665_1.<8>[ 30.903874] <LAVA_SIGNAL_STARTRUN 1_bootrr 10597665_1.6.2.3.5>
11056 22:57:13.310194 6.2.3.5
11057 22:57:13.310293 + set +x
11058 22:57:13.310534 Received signal: <STARTRUN> 1_bootrr 10597665_1.6.2.3.5
11059 22:57:13.310603 Starting test lava.1_bootrr (10597665_1.6.2.3.5)
11060 22:57:13.310685 Skipping test definition patterns.
11061 22:57:13.323264 + export PATH=/opt/bootrr/libexec/bootrr/helpers:/lava-10597665/1/../bin:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin
11062 22:57:13.326383 + cd /opt/bootrr/libexec/bootrr
11063 22:57:13.326503 + sh helpers/bootrr-auto
11064 22:57:13.391067 /lava-10597665/1/../bin/lava-test-case
11065 22:57:13.495423 <8>[ 31.089034] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=deferred-probe-empty RESULT=pass>
11066 22:57:13.496408 Received signal: <TESTCASE> TEST_CASE_ID=deferred-probe-empty RESULT=pass
11068 22:57:13.548354 /lava-10597665/1/../bin/lava-test-case
11069 22:57:13.595634 <8>[ 31.189260] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=all-cpus-are-online RESULT=pass>
11070 22:57:13.596024 Received signal: <TESTCASE> TEST_CASE_ID=all-cpus-are-online RESULT=pass
11072 22:57:13.622748 /lava-10597665/1/../bin/lava-test-case
11073 22:57:13.653284 <8>[ 31.247148] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm-chip-is-online RESULT=skip>
11074 22:57:13.653667 Received signal: <TESTCASE> TEST_CASE_ID=tpm-chip-is-online RESULT=skip
11076 22:57:13.712360 /lava-10597665/1/../bin/lava-test-case
11077 22:57:13.738730 <8>[ 31.332749] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass>
11078 22:57:13.739048 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass
11080 22:57:13.776166 /lava-10597665/1/../bin/lava-test-case
11081 22:57:13.806782 <8>[ 31.400647] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass>
11082 22:57:13.807128 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass
11084 22:57:13.839563 /lava-10597665/1/../bin/lava-test-case
11085 22:57:13.864967 <8>[ 31.458868] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass>
11086 22:57:13.865322 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass
11088 22:57:13.904484 /lava-10597665/1/../bin/lava-test-case
11089 22:57:13.938455 <8>[ 31.532130] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass>
11090 22:57:13.938775 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass
11092 22:57:13.976588 /lava-10597665/1/../bin/lava-test-case
11093 22:57:14.004887 <8>[ 31.598669] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass>
11094 22:57:14.005199 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass
11096 22:57:14.028541 /lava-10597665/1/../bin/lava-test-case
11097 22:57:14.054994 <8>[ 31.648645] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass>
11098 22:57:14.055332 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass
11100 22:57:14.091115 /lava-10597665/1/../bin/lava-test-case
11101 22:57:14.119292 <8>[ 31.713339] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass>
11102 22:57:14.119646 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass
11104 22:57:14.143029 /lava-10597665/1/../bin/lava-test-case
11105 22:57:14.183136 <8>[ 31.777308] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass>
11106 22:57:14.183471 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass
11108 22:57:14.216589 /lava-10597665/1/../bin/lava-test-case
11109 22:57:14.254619 <8>[ 31.848586] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass>
11110 22:57:14.255014 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass
11112 22:57:14.290361 /lava-10597665/1/../bin/lava-test-case
11113 22:57:14.318399 <8>[ 31.912530] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass>
11114 22:57:14.318792 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass
11116 22:57:14.368536 /lava-10597665/1/../bin/lava-test-case
11117 22:57:14.405291 <8>[ 31.998927] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass>
11118 22:57:14.406241 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass
11120 22:57:14.443131 /lava-10597665/1/../bin/lava-test-case
11121 22:57:14.468332 <8>[ 32.062505] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass>
11122 22:57:14.468740 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass
11124 22:57:14.491301 /lava-10597665/1/../bin/lava-test-case
11125 22:57:14.774739 <8>[ 32.368150] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass>
11126 22:57:14.775575 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass
11128 22:57:14.817335 /lava-10597665/1/../bin/lava-test-case
11129 22:57:14.848519 <8>[ 32.442008] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass>
11130 22:57:14.849249 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass
11132 22:57:14.871878 /lava-10597665/1/../bin/lava-test-case
11133 22:57:14.904265 <8>[ 32.498075] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass>
11134 22:57:14.905363 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass
11136 22:57:14.940673 /lava-10597665/1/../bin/lava-test-case
11137 22:57:14.973421 <8>[ 32.566732] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass>
11138 22:57:14.974524 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass
11140 22:57:14.998813 /lava-10597665/1/../bin/lava-test-case
11141 22:57:15.027548 <8>[ 32.621258] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass>
11142 22:57:15.027854 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass
11144 22:57:15.064996 /lava-10597665/1/../bin/lava-test-case
11145 22:57:15.095568 <8>[ 32.689426] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-probed RESULT=pass>
11146 22:57:15.095895 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-probed RESULT=pass
11148 22:57:15.117460 /lava-10597665/1/../bin/lava-test-case
11149 22:57:15.147711 <8>[ 32.741663] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass>
11150 22:57:15.148052 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass
11152 22:57:15.182141 /lava-10597665/1/../bin/lava-test-case
11153 22:57:15.220362 <8>[ 32.814551] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass>
11154 22:57:15.220695 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass
11156 22:57:15.241655 /lava-10597665/1/../bin/lava-test-case
11157 22:57:15.662131 <8>[ 33.256066] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass>
11158 22:57:15.662905 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass
11160 22:57:15.702747 /lava-10597665/1/../bin/lava-test-case
11161 22:57:15.730644 <8>[ 33.324586] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass>
11162 22:57:15.730956 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass
11164 22:57:15.767955 /lava-10597665/1/../bin/lava-test-case
11165 22:57:15.945366 <8>[ 33.539356] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass>
11166 22:57:15.945776 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass
11168 22:57:15.975484 /lava-10597665/1/../bin/lava-test-case
11169 22:57:16.007303 <8>[ 33.600967] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass>
11170 22:57:16.008109 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass
11172 22:57:16.049011 /lava-10597665/1/../bin/lava-test-case
11173 22:57:16.084894 <8>[ 33.678419] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass>
11174 22:57:16.085697 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass
11176 22:57:16.110768 /lava-10597665/1/../bin/lava-test-case
11177 22:57:16.506550 <8>[ 34.100587] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass>
11178 22:57:16.507346 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass
11180 22:57:16.547236 /lava-10597665/1/../bin/lava-test-case
11181 22:57:16.573606 <8>[ 34.167800] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass>
11182 22:57:16.573916 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass
11184 22:57:16.608399 /lava-10597665/1/../bin/lava-test-case
11185 22:57:17.009395 <8>[ 34.603376] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass>
11186 22:57:17.010170 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass
11188 22:57:17.051826 /lava-10597665/1/../bin/lava-test-case
11189 22:57:17.083674 <8>[ 34.677450] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass>
11190 22:57:17.083988 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass
11192 22:57:17.123134 /lava-10597665/1/../bin/lava-test-case
11193 22:57:17.427153 <8>[ 35.021068] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass>
11194 22:57:17.427981 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass
11196 22:57:17.456962 /lava-10597665/1/../bin/lava-test-case
11197 22:57:17.482996 <8>[ 35.077089] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass>
11198 22:57:17.483308 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass
11200 22:57:17.520242 /lava-10597665/1/../bin/lava-test-case
11201 22:57:17.966242 <8>[ 35.560048] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass>
11202 22:57:17.967028 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass
11204 22:57:18.004371 /lava-10597665/1/../bin/lava-test-case
11205 22:57:18.262476 <8>[ 35.856378] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass>
11206 22:57:18.263225 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass
11208 22:57:18.295656 /lava-10597665/1/../bin/lava-test-case
11209 22:57:18.323559 <8>[ 35.917643] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass>
11210 22:57:18.323870 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass
11212 22:57:18.360519 /lava-10597665/1/../bin/lava-test-case
11213 22:57:18.641474 <8>[ 36.227172] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass>
11214 22:57:18.641796 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass
11216 22:57:18.658742 /lava-10597665/1/../bin/lava-test-case
11217 22:57:18.841408 <8>[ 36.436127] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass>
11218 22:57:18.841729 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass
11220 22:57:18.880379 /lava-10597665/1/../bin/lava-test-case
11221 22:57:19.237530 <8>[ 36.831860] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass>
11222 22:57:19.238270 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass
11224 22:57:19.264245 /lava-10597665/1/../bin/lava-test-case
11225 22:57:19.294702 <8>[ 36.888782] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass>
11226 22:57:19.295009 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass
11228 22:57:19.336138 /lava-10597665/1/../bin/lava-test-case
11229 22:57:19.622005 <8>[ 37.216655] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass>
11230 22:57:19.622315 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass
11232 22:57:19.652072 /lava-10597665/1/../bin/lava-test-case
11233 22:57:20.031638 <8>[ 37.625967] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass>
11234 22:57:20.031948 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass
11236 22:57:20.070410 /lava-10597665/1/../bin/lava-test-case
11237 22:57:20.404548 <8>[ 37.999021] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-probed RESULT=pass>
11238 22:57:20.404893 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-probed RESULT=pass
11240 22:57:20.435170 /lava-10597665/1/../bin/lava-test-case
11241 22:57:20.507128 <8>[ 38.101469] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass>
11242 22:57:20.507439 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass
11244 22:57:20.544376 /lava-10597665/1/../bin/lava-test-case
11245 22:57:20.571975 <8>[ 38.166311] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass>
11246 22:57:20.572820 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass
11248 22:57:20.600541 /lava-10597665/1/../bin/lava-test-case
11249 22:57:20.630450 <8>[ 38.225305] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass>
11250 22:57:20.630831 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass
11252 22:57:20.665238 /lava-10597665/1/../bin/lava-test-case
11253 22:57:20.692537 <8>[ 38.287254] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-probed RESULT=pass>
11254 22:57:20.692904 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-probed RESULT=pass
11256 22:57:20.717100 /lava-10597665/1/../bin/lava-test-case
11257 22:57:20.750470 <8>[ 38.345021] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass>
11258 22:57:20.751168 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass
11260 22:57:20.790985 /lava-10597665/1/../bin/lava-test-case
11261 22:57:20.824251 <8>[ 38.418646] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass>
11262 22:57:20.824691 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass
11264 22:57:20.866308 /lava-10597665/1/../bin/lava-test-case
11265 22:57:20.895692 <8>[ 38.490347] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass>
11266 22:57:20.896176 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass
11268 22:57:21.942574 /lava-10597665/1/../bin/lava-test-case
11269 22:57:21.977153 <8>[ 39.571867] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=fail>
11270 22:57:21.977879 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=fail
11272 22:57:23.017721 /lava-10597665/1/../bin/lava-test-case
11273 22:57:23.056637 <8>[ 40.651028] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=blocked>
11274 22:57:23.057336 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=blocked
11275 22:57:23.057761 Bad test result: blocked
11276 22:57:23.081787 /lava-10597665/1/../bin/lava-test-case
11277 22:57:23.117262 <8>[ 40.712018] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass>
11278 22:57:23.117521 Received signal: <TESTCASE> TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass
11280 22:57:23.158724 /lava-10597665/1/../bin/lava-test-case
11281 22:57:23.190386 <8>[ 40.785029] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass>
11282 22:57:23.190673 Received signal: <TESTCASE> TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass
11284 22:57:23.223480 /lava-10597665/1/../bin/lava-test-case
11285 22:57:23.251807 <8>[ 40.846602] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass>
11286 22:57:23.252068 Received signal: <TESTCASE> TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass
11288 22:57:23.286956 /lava-10597665/1/../bin/lava-test-case
11289 22:57:23.315896 <8>[ 40.910905] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass>
11290 22:57:23.316168 Received signal: <TESTCASE> TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass
11292 22:57:23.356916 /lava-10597665/1/../bin/lava-test-case
11293 22:57:23.382909 <8>[ 40.978156] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass>
11294 22:57:23.383172 Received signal: <TESTCASE> TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass
11296 22:57:23.419546 /lava-10597665/1/../bin/lava-test-case
11297 22:57:23.449094 <8>[ 41.044034] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass>
11298 22:57:23.449381 Received signal: <TESTCASE> TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass
11300 22:57:23.470239 /lava-10597665/1/../bin/lava-test-case
11301 22:57:23.500865 <8>[ 41.096140] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-driver-present RESULT=pass>
11302 22:57:23.501126 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-driver-present RESULT=pass
11304 22:57:23.536178 /lava-10597665/1/../bin/lava-test-case
11305 22:57:23.564020 <8>[ 41.159218] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi1-probed RESULT=pass>
11306 22:57:23.564320 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi1-probed RESULT=pass
11308 22:57:23.599178 /lava-10597665/1/../bin/lava-test-case
11309 22:57:23.625361 <8>[ 41.220569] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi5-probed RESULT=pass>
11310 22:57:23.625628 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi5-probed RESULT=pass
11312 22:57:23.645566 /lava-10597665/1/../bin/lava-test-case
11313 22:57:23.674261 <8>[ 41.269473] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass>
11314 22:57:23.674532 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass
11316 22:57:23.715749 /lava-10597665/1/../bin/lava-test-case
11317 22:57:23.744249 <8>[ 41.339559] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-probed RESULT=pass>
11318 22:57:23.744509 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-probed RESULT=pass
11320 22:57:23.765639 /lava-10597665/1/../bin/lava-test-case
11321 22:57:23.792896 <8>[ 41.387579] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass>
11322 22:57:23.793150 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass
11324 22:57:23.826782 /lava-10597665/1/../bin/lava-test-case
11325 22:57:23.853284 <8>[ 41.448475] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-probed RESULT=pass>
11326 22:57:23.853550 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-probed RESULT=pass
11328 22:57:23.877392 /lava-10597665/1/../bin/lava-test-case
11329 22:57:23.907111 <8>[ 41.502081] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass>
11330 22:57:23.907362 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass
11332 22:57:23.942221 /lava-10597665/1/../bin/lava-test-case
11333 22:57:23.967460 <8>[ 41.562268] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass>
11334 22:57:23.967727 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass
11336 22:57:24.002783 /lava-10597665/1/../bin/lava-test-case
11337 22:57:24.034746 <8>[ 41.629472] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass>
11338 22:57:24.035018 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass
11340 22:57:24.074662 /lava-10597665/1/../bin/lava-test-case
11341 22:57:24.100705 <8>[ 41.695972] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass>
11342 22:57:24.100989 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass
11344 22:57:24.135380 /lava-10597665/1/../bin/lava-test-case
11345 22:57:24.160923 <8>[ 41.755819] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass>
11346 22:57:24.161195 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass
11348 22:57:24.194916 /lava-10597665/1/../bin/lava-test-case
11349 22:57:24.220864 <8>[ 41.815887] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass>
11350 22:57:24.221135 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass
11352 22:57:24.255955 /lava-10597665/1/../bin/lava-test-case
11353 22:57:24.283387 <8>[ 41.878469] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass>
11354 22:57:24.283687 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass
11356 22:57:24.320520 /lava-10597665/1/../bin/lava-test-case
11357 22:57:24.348116 <8>[ 41.943192] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass>
11358 22:57:24.348381 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass
11360 22:57:24.382827 /lava-10597665/1/../bin/lava-test-case
11361 22:57:24.409302 <8>[ 42.004708] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass>
11362 22:57:24.409567 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass
11364 22:57:24.451144 /lava-10597665/1/../bin/lava-test-case
11365 22:57:24.479484 <8>[ 42.074783] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass>
11366 22:57:24.479755 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass
11368 22:57:24.512583 /lava-10597665/1/../bin/lava-test-case
11369 22:57:24.541932 <8>[ 42.137217] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass>
11370 22:57:24.542198 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass
11372 22:57:24.573226 /lava-10597665/1/../bin/lava-test-case
11373 22:57:24.600579 <8>[ 42.195559] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass>
11374 22:57:24.600853 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass
11376 22:57:24.635653 /lava-10597665/1/../bin/lava-test-case
11377 22:57:24.667987 <8>[ 42.262784] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass>
11378 22:57:24.668298 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass
11380 22:57:24.701816 /lava-10597665/1/../bin/lava-test-case
11381 22:57:24.732300 <8>[ 42.327697] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass>
11382 22:57:24.732568 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass
11384 22:57:24.775605 /lava-10597665/1/../bin/lava-test-case
11385 22:57:24.804531 <8>[ 42.399706] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass>
11386 22:57:24.804871 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass
11388 22:57:24.840590 /lava-10597665/1/../bin/lava-test-case
11389 22:57:24.868020 <8>[ 42.463428] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass>
11390 22:57:24.868307 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass
11392 22:57:24.890425 /lava-10597665/1/../bin/lava-test-case
11393 22:57:24.921079 <8>[ 42.516344] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass>
11394 22:57:24.921371 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass
11396 22:57:24.957602 /lava-10597665/1/../bin/lava-test-case
11397 22:57:24.987464 <8>[ 42.582629] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-probed RESULT=pass>
11398 22:57:24.987744 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-probed RESULT=pass
11400 22:57:25.010594 /lava-10597665/1/../bin/lava-test-case
11401 22:57:25.039581 <8>[ 42.634975] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass>
11402 22:57:25.039878 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass
11404 22:57:25.076027 /lava-10597665/1/../bin/lava-test-case
11405 22:57:25.105108 <8>[ 42.700411] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-probed RESULT=pass>
11406 22:57:25.105381 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-probed RESULT=pass
11408 22:57:25.136506 /lava-10597665/1/../bin/lava-test-case
11409 22:57:25.169179 <8>[ 42.764400] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass>
11410 22:57:25.169462 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass
11412 22:57:25.205455 /lava-10597665/1/../bin/lava-test-case
11413 22:57:25.231715 <8>[ 42.826969] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass>
11414 22:57:25.232017 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass
11416 22:57:25.256336 /lava-10597665/1/../bin/lava-test-case
11417 22:57:25.283300 <8>[ 42.878355] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass>
11418 22:57:25.283557 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass
11420 22:57:25.320628 /lava-10597665/1/../bin/lava-test-case
11421 22:57:25.347508 <8>[ 42.942470] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-probed RESULT=pass>
11422 22:57:25.347786 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-probed RESULT=pass
11424 22:57:25.370784 /lava-10597665/1/../bin/lava-test-case
11425 22:57:25.399498 <8>[ 42.994936] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass>
11426 22:57:25.399760 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass
11428 22:57:25.435506 /lava-10597665/1/../bin/lava-test-case
11429 22:57:25.470754 <8>[ 43.066115] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass>
11430 22:57:25.471060 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass
11432 22:57:25.490690 /lava-10597665/1/../bin/lava-test-case
11433 22:57:25.519133 <8>[ 43.114286] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass>
11434 22:57:25.519403 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass
11436 22:57:25.554496 /lava-10597665/1/../bin/lava-test-case
11437 22:57:25.581784 <8>[ 43.176795] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass>
11438 22:57:25.582059 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass
11440 22:57:25.613857 /lava-10597665/1/../bin/lava-test-case
11441 22:57:25.639282 <8>[ 43.234272] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass>
11442 22:57:25.639586 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass
11444 22:57:25.662043 /lava-10597665/1/../bin/lava-test-case
11445 22:57:25.689826 <8>[ 43.285263] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass>
11446 22:57:25.690088 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass
11448 22:57:25.727639 /lava-10597665/1/../bin/lava-test-case
11449 22:57:25.756455 <8>[ 43.351775] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass>
11450 22:57:25.756796 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass
11452 22:57:25.784558 /lava-10597665/1/../bin/lava-test-case
11453 22:57:25.810859 <8>[ 43.405926] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-driver-present RESULT=pass>
11454 22:57:25.811202 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-driver-present RESULT=pass
11456 22:57:25.843941 /lava-10597665/1/../bin/lava-test-case
11457 22:57:25.869379 <8>[ 43.464453] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-probed RESULT=pass>
11458 22:57:25.869695 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-probed RESULT=pass
11460 22:57:25.891098 /lava-10597665/1/../bin/lava-test-case
11461 22:57:25.920196 <8>[ 43.515399] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-driver-present RESULT=pass>
11462 22:57:25.920517 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-driver-present RESULT=pass
11464 22:57:26.964832 /lava-10597665/1/../bin/lava-test-case
11465 22:57:26.994352 <8>[ 44.589777] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-probed RESULT=fail>
11466 22:57:26.994634 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-probed RESULT=fail
11468 22:57:27.019331 /lava-10597665/1/../bin/lava-test-case
11469 22:57:27.050671 <8>[ 44.646219] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-driver-present RESULT=pass>
11470 22:57:27.050959 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-driver-present RESULT=pass
11472 22:57:28.095731 /lava-10597665/1/../bin/lava-test-case
11473 22:57:28.122515 <8>[ 45.718160] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-probed RESULT=fail>
11474 22:57:28.122846 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-probed RESULT=fail
11476 22:57:28.146516 /lava-10597665/1/../bin/lava-test-case
11477 22:57:28.173049 <8>[ 45.768727] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass>
11478 22:57:28.173354 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass
11480 22:57:28.553078 <6>[ 46.154905] vpu: disabling
11481 22:57:28.556251 <6>[ 46.157958] vproc2: disabling
11482 22:57:28.559226 <6>[ 46.161234] vproc1: disabling
11483 22:57:28.562708 <6>[ 46.164494] vaud18: disabling
11484 22:57:28.569170 <6>[ 46.167896] vsram_others: disabling
11485 22:57:28.569270 <6>[ 46.171769] va09: disabling
11486 22:57:28.576248 <6>[ 46.174871] vsram_md: disabling
11487 22:57:28.576337 <6>[ 46.178356] Vgpu: disabling
11488 22:57:29.217817 /lava-10597665/1/../bin/lava-test-case
11489 22:57:29.250112 <8>[ 46.845683] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail>
11490 22:57:29.250431 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail
11492 22:57:29.273856 /lava-10597665/1/../bin/lava-test-case
11493 22:57:29.300863 <8>[ 46.896361] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass>
11494 22:57:29.301206 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass
11496 22:57:30.346989 /lava-10597665/1/../bin/lava-test-case
11497 22:57:30.376330 <8>[ 47.971917] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-probed RESULT=fail>
11498 22:57:30.376650 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-probed RESULT=fail
11500 22:57:30.398703 /lava-10597665/1/../bin/lava-test-case
11501 22:57:30.431243 <8>[ 48.026955] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-driver-present RESULT=pass>
11502 22:57:30.431557 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-driver-present RESULT=pass
11504 22:57:31.475504 /lava-10597665/1/../bin/lava-test-case
11505 22:57:31.508639 <8>[ 49.104480] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-3-probed RESULT=fail>
11506 22:57:31.508941 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-3-probed RESULT=fail
11508 22:57:31.530785 /lava-10597665/1/../bin/lava-test-case
11509 22:57:31.559523 <8>[ 49.155260] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass>
11510 22:57:31.559820 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass
11512 22:57:32.608019 /lava-10597665/1/../bin/lava-test-case
11513 22:57:32.645029 <8>[ 50.241009] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail>
11514 22:57:32.645376 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail
11516 22:57:32.666543 /lava-10597665/1/../bin/lava-test-case
11517 22:57:32.691498 <8>[ 50.287502] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass>
11518 22:57:32.691822 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass
11520 22:57:33.733431 /lava-10597665/1/../bin/lava-test-case
11521 22:57:33.759214 <8>[ 51.355406] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-probed RESULT=fail>
11522 22:57:33.759512 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-probed RESULT=fail
11524 22:57:33.781886 /lava-10597665/1/../bin/lava-test-case
11525 22:57:33.807462 <8>[ 51.403687] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-edp-driver-present RESULT=pass>
11526 22:57:33.807749 Received signal: <TESTCASE> TEST_CASE_ID=panel-edp-driver-present RESULT=pass
11528 22:57:33.829545 /lava-10597665/1/../bin/lava-test-case
11529 22:57:33.856279 <8>[ 51.452621] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass>
11530 22:57:33.856593 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass
11532 22:57:34.902706 /lava-10597665/1/../bin/lava-test-case
11533 22:57:34.935259 <8>[ 52.531758] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail>
11534 22:57:34.935589 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail
11536 22:57:34.961398 /lava-10597665/1/../bin/lava-test-case
11537 22:57:34.986327 <8>[ 52.582469] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass>
11538 22:57:34.986647 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass
11540 22:57:35.018994 /lava-10597665/1/../bin/lava-test-case
11541 22:57:35.043035 <8>[ 52.639535] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-probed RESULT=pass>
11542 22:57:35.043372 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-probed RESULT=pass
11544 22:57:35.062976 /lava-10597665/1/../bin/lava-test-case
11545 22:57:35.088595 <8>[ 52.685107] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass>
11546 22:57:35.088905 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass
11548 22:57:35.126214 /lava-10597665/1/../bin/lava-test-case
11549 22:57:35.154097 <8>[ 52.750560] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass>
11550 22:57:35.154402 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass
11552 22:57:35.192190 /lava-10597665/1/../bin/lava-test-case
11553 22:57:35.224381 <8>[ 52.820667] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass>
11554 22:57:35.224701 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass
11556 22:57:35.257862 /lava-10597665/1/../bin/lava-test-case
11557 22:57:35.282772 <8>[ 52.878782] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass>
11558 22:57:35.283100 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass
11560 22:57:35.303968 /lava-10597665/1/../bin/lava-test-case
11561 22:57:35.329651 <8>[ 52.925947] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass>
11562 22:57:35.329969 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass
11564 22:57:35.365859 /lava-10597665/1/../bin/lava-test-case
11565 22:57:35.394702 <8>[ 52.990986] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass>
11566 22:57:35.395019 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass
11568 22:57:35.428639 /lava-10597665/1/../bin/lava-test-case
11569 22:57:35.455053 <8>[ 53.051687] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass>
11570 22:57:35.455359 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass
11572 22:57:35.477133 /lava-10597665/1/../bin/lava-test-case
11573 22:57:35.501824 <8>[ 53.098447] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass>
11574 22:57:35.502123 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass
11576 22:57:35.542648 /lava-10597665/1/../bin/lava-test-case
11577 22:57:35.570269 <8>[ 53.166407] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass>
11578 22:57:35.570570 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass
11580 22:57:35.593455 /lava-10597665/1/../bin/lava-test-case
11581 22:57:35.621660 <8>[ 53.218298] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass>
11582 22:57:35.621968 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass
11584 22:57:35.659124 /lava-10597665/1/../bin/lava-test-case
11585 22:57:35.688331 <8>[ 53.284807] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass>
11586 22:57:35.688640 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass
11588 22:57:35.711762 /lava-10597665/1/../bin/lava-test-case
11589 22:57:35.743587 <8>[ 53.339940] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass>
11590 22:57:35.743887 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass
11592 22:57:35.783099 /lava-10597665/1/../bin/lava-test-case
11593 22:57:35.809595 <8>[ 53.406312] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass>
11594 22:57:35.809928 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass
11596 22:57:35.830206 /lava-10597665/1/../bin/lava-test-case
11597 22:57:35.858051 <8>[ 53.454290] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass>
11598 22:57:35.858368 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass
11600 22:57:35.902455 /lava-10597665/1/../bin/lava-test-case
11601 22:57:35.934164 <8>[ 53.530468] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass>
11602 22:57:35.934486 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass
11604 22:57:35.957564 /lava-10597665/1/../bin/lava-test-case
11605 22:57:35.985466 <8>[ 53.581734] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass>
11606 22:57:35.985761 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass
11608 22:57:36.021757 /lava-10597665/1/../bin/lava-test-case
11609 22:57:36.049976 <8>[ 53.646133] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-probed RESULT=pass>
11610 22:57:36.050294 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-probed RESULT=pass
11612 22:57:36.071534 /lava-10597665/1/../bin/lava-test-case
11613 22:57:36.099243 <8>[ 53.695809] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass>
11614 22:57:36.099533 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass
11616 22:57:37.145929 /lava-10597665/1/../bin/lava-test-case
11617 22:57:37.175909 <8>[ 54.772429] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-probed RESULT=fail>
11618 22:57:37.176187 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-probed RESULT=fail
11620 22:57:38.224170 /lava-10597665/1/../bin/lava-test-case
11621 22:57:38.258086 <8>[ 55.854958] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-7-probed RESULT=fail>
11622 22:57:38.258409 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-7-probed RESULT=fail
11624 22:57:38.282027 /lava-10597665/1/../bin/lava-test-case
11625 22:57:38.307881 <8>[ 55.904607] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-driver-present RESULT=pass>
11626 22:57:38.308212 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-driver-present RESULT=pass
11628 22:57:38.340987 /lava-10597665/1/../bin/lava-test-case
11629 22:57:38.366665 <8>[ 55.963169] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-probed RESULT=pass>
11630 22:57:38.366970 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-probed RESULT=pass
11632 22:57:38.390274 /lava-10597665/1/../bin/lava-test-case
11633 22:57:38.418101 <8>[ 56.014619] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass>
11634 22:57:38.418408 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass
11636 22:57:38.452835 /lava-10597665/1/../bin/lava-test-case
11637 22:57:38.479621 <8>[ 56.076018] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass>
11638 22:57:38.479920 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass
11640 22:57:38.502089 /lava-10597665/1/../bin/lava-test-case
11641 22:57:38.531213 <8>[ 56.127928] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-driver-present RESULT=pass>
11642 22:57:38.531537 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-driver-present RESULT=pass
11644 22:57:38.573029 /lava-10597665/1/../bin/lava-test-case
11645 22:57:38.600549 <8>[ 56.197129] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-probed RESULT=pass>
11646 22:57:38.600870 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-probed RESULT=pass
11648 22:57:38.622370 /lava-10597665/1/../bin/lava-test-case
11649 22:57:38.649922 <8>[ 56.246519] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass>
11650 22:57:38.650271 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass
11652 22:57:38.686131 /lava-10597665/1/../bin/lava-test-case
11653 22:57:38.715473 <8>[ 56.312412] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass>
11654 22:57:38.715787 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass
11656 22:57:38.737182 /lava-10597665/1/../bin/lava-test-case
11657 22:57:38.767397 <8>[ 56.364047] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass>
11658 22:57:38.767718 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass
11660 22:57:38.806472 /lava-10597665/1/../bin/lava-test-case
11661 22:57:38.834952 <8>[ 56.431783] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-probed RESULT=pass>
11662 22:57:38.835273 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-probed RESULT=pass
11664 22:57:38.859780 /lava-10597665/1/../bin/lava-test-case
11665 22:57:38.886142 <8>[ 56.482907] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass>
11666 22:57:38.886467 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass
11668 22:57:38.928010 /lava-10597665/1/../bin/lava-test-case
11669 22:57:38.955861 <8>[ 56.552455] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass>
11670 22:57:38.956186 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass
11672 22:57:38.978222 /lava-10597665/1/../bin/lava-test-case
11673 22:57:39.008927 <8>[ 56.605781] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass>
11674 22:57:39.009251 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass
11676 22:57:39.047910 /lava-10597665/1/../bin/lava-test-case
11677 22:57:39.079120 <8>[ 56.675794] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-probed RESULT=pass>
11678 22:57:39.079444 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-probed RESULT=pass
11680 22:57:39.102963 /lava-10597665/1/../bin/lava-test-case
11681 22:57:39.128551 <8>[ 56.725184] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass>
11682 22:57:39.128867 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass
11684 22:57:39.162137 /lava-10597665/1/../bin/lava-test-case
11685 22:57:39.189701 <8>[ 56.786496] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-probed RESULT=pass>
11686 22:57:39.190028 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-probed RESULT=pass
11688 22:57:39.210053 /lava-10597665/1/../bin/lava-test-case
11689 22:57:39.239655 <8>[ 56.836480] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-driver-present RESULT=pass>
11690 22:57:39.239995 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-driver-present RESULT=pass
11692 22:57:39.287409 /lava-10597665/1/../bin/lava-test-case
11693 22:57:39.319972 <8>[ 56.916738] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-probed RESULT=pass>
11694 22:57:39.320321 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-probed RESULT=pass
11696 22:57:39.343818 /lava-10597665/1/../bin/lava-test-case
11697 22:57:39.371245 <8>[ 56.968053] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass>
11698 22:57:39.371581 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass
11700 22:57:39.406301 /lava-10597665/1/../bin/lava-test-case
11701 22:57:39.435886 <8>[ 57.032826] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass>
11702 22:57:39.436190 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass
11704 22:57:40.472239 /lava-10597665/1/../bin/lava-test-case
11705 22:57:40.503143 <8>[ 58.100241] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail>
11706 22:57:40.503461 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail
11708 22:57:41.540533 /lava-10597665/1/../bin/lava-test-case
11709 22:57:41.583601 <8>[ 59.180805] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked>
11710 22:57:41.583948 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked
11711 22:57:41.584073 Bad test result: blocked
11712 22:57:41.608386 /lava-10597665/1/../bin/lava-test-case
11713 22:57:41.636905 <8>[ 59.234018] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-driver-present RESULT=pass>
11714 22:57:41.637251 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-driver-present RESULT=pass
11716 22:57:42.684528 /lava-10597665/1/../bin/lava-test-case
11717 22:57:42.713139 <8>[ 60.310431] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-probed RESULT=fail>
11718 22:57:42.713444 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-probed RESULT=fail
11720 22:57:42.735645 /lava-10597665/1/../bin/lava-test-case
11721 22:57:42.760876 <8>[ 60.357860] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo-driver-present RESULT=pass>
11722 22:57:42.761194 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo-driver-present RESULT=pass
11724 22:57:42.791603 /lava-10597665/1/../bin/lava-test-case
11725 22:57:42.817743 <8>[ 60.414878] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo0-probed RESULT=pass>
11726 22:57:42.818062 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo0-probed RESULT=pass
11728 22:57:42.847911 /lava-10597665/1/../bin/lava-test-case
11729 22:57:42.875568 <8>[ 60.472799] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo1-probed RESULT=pass>
11730 22:57:42.875965 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo1-probed RESULT=pass
11732 22:57:42.897166 /lava-10597665/1/../bin/lava-test-case
11733 22:57:43.045264 <8>[ 60.642408] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass>
11734 22:57:43.045649 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass
11736 22:57:43.085208 /lava-10597665/1/../bin/lava-test-case
11737 22:57:43.192858 <8>[ 60.790113] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-probed RESULT=pass>
11738 22:57:43.193213 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-probed RESULT=pass
11740 22:57:43.214620 /lava-10597665/1/../bin/lava-test-case
11741 22:57:43.339525 <8>[ 60.936769] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-driver-present RESULT=pass>
11742 22:57:43.339867 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-driver-present RESULT=pass
11744 22:57:44.388941 /lava-10597665/1/../bin/lava-test-case
11745 22:57:44.418192 <8>[ 62.015721] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-probed RESULT=fail>
11746 22:57:44.418560 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-probed RESULT=fail
11748 22:57:44.443799 /lava-10597665/1/../bin/lava-test-case
11749 22:57:44.475591 <8>[ 62.073258] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-driver-present RESULT=pass>
11750 22:57:44.475907 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-driver-present RESULT=pass
11752 22:57:45.522159 /lava-10597665/1/../bin/lava-test-case
11753 22:57:45.549769 <8>[ 63.147183] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-probed RESULT=fail>
11754 22:57:45.550088 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-probed RESULT=fail
11756 22:57:45.573461 /lava-10597665/1/../bin/lava-test-case
11757 22:57:45.600886 <8>[ 63.197984] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-driver-present RESULT=pass>
11758 22:57:45.601150 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-driver-present RESULT=pass
11760 22:57:46.643391 /lava-10597665/1/../bin/lava-test-case
11761 22:57:46.674462 <8>[ 64.271784] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-probed RESULT=fail>
11762 22:57:46.674743 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-probed RESULT=fail
11764 22:57:46.698821 /lava-10597665/1/../bin/lava-test-case
11765 22:57:46.732521 <8>[ 64.330380] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass>
11766 22:57:46.732785 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass
11768 22:57:47.781330 /lava-10597665/1/../bin/lava-test-case
11769 22:57:47.811189 <8>[ 65.409204] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail>
11770 22:57:47.811531 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail
11772 22:57:47.830894 /lava-10597665/1/../bin/lava-test-case
11773 22:57:47.858979 <8>[ 65.456857] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb-driver-present RESULT=pass>
11774 22:57:47.859320 Received signal: <TESTCASE> TEST_CASE_ID=btusb-driver-present RESULT=pass
11776 22:57:47.892053 /lava-10597665/1/../bin/lava-test-case
11777 22:57:47.918420 <8>[ 65.516193] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb0-probed RESULT=pass>
11778 22:57:47.918748 Received signal: <TESTCASE> TEST_CASE_ID=btusb0-probed RESULT=pass
11780 22:57:47.953123 /lava-10597665/1/../bin/lava-test-case
11781 22:57:47.978147 <8>[ 65.576246] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb1-probed RESULT=pass>
11782 22:57:47.978482 Received signal: <TESTCASE> TEST_CASE_ID=btusb1-probed RESULT=pass
11784 22:57:47.998592 /lava-10597665/1/../bin/lava-test-case
11785 22:57:48.023949 <8>[ 65.621582] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass>
11786 22:57:48.024273 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass
11788 22:57:48.055920 /lava-10597665/1/../bin/lava-test-case
11789 22:57:48.081079 <8>[ 65.678827] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-probed RESULT=pass>
11790 22:57:48.081377 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-probed RESULT=pass
11792 22:57:48.112180 /lava-10597665/1/../bin/lava-test-case
11793 22:57:48.139764 <8>[ 65.737591] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass>
11794 22:57:48.140056 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass
11796 22:57:48.176399 /lava-10597665/1/../bin/lava-test-case
11797 22:57:48.201779 <8>[ 65.799583] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-probed RESULT=pass>
11798 22:57:48.202096 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-probed RESULT=pass
11800 22:57:48.227356 /lava-10597665/1/../bin/lava-test-case
11801 22:57:48.256227 <8>[ 65.853948] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass>
11802 22:57:48.256591 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass
11804 22:57:49.307619 /lava-10597665/1/../bin/lava-test-case
11805 22:57:49.336180 <8>[ 66.934402] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=fail>
11806 22:57:49.336502 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=fail
11808 22:57:49.345460 + <8>[ 66.946759] <LAVA_SIGNAL_ENDRUN 1_bootrr 10597665_1.6.2.3.5>
11809 22:57:49.345730 Received signal: <ENDRUN> 1_bootrr 10597665_1.6.2.3.5
11810 22:57:49.345823 Ending use of test pattern.
11811 22:57:49.345906 Ending test lava.1_bootrr (10597665_1.6.2.3.5), duration 36.04
11813 22:57:49.348446 set +x
11814 22:57:49.352709 <LAVA_TEST_RUNNER EXIT>
11815 22:57:49.352983 ok: lava_test_shell seems to have completed
11816 22:57:49.354057 all-cpus-are-online: pass
anx7625-3-probed: fail
anx7625-7-probed: fail
anx7625-driver-present: pass
btusb-driver-present: pass
btusb0-probed: pass
btusb1-probed: pass
clk-mt8192-apmixedsys-probed: pass
clk-mt8192-aud-driver-present: pass
clk-mt8192-aud-probed: pass
clk-mt8192-cam-driver-present: pass
clk-mt8192-cam-probed: pass
clk-mt8192-cam_rawa-probed: pass
clk-mt8192-cam_rawb-probed: pass
clk-mt8192-cam_rawc-probed: pass
clk-mt8192-driver-present: pass
clk-mt8192-img-driver-present: pass
clk-mt8192-img-probed: pass
clk-mt8192-img2-probed: pass
clk-mt8192-imp_iic_wrap-driver-present: pass
clk-mt8192-imp_iic_wrap_e-probed: pass
clk-mt8192-imp_iic_wrap_n-probed: pass
clk-mt8192-imp_iic_wrap_s-probed: pass
clk-mt8192-imp_iic_wrap_ws-probed: pass
clk-mt8192-infracfg-probed: pass
clk-mt8192-ipe-driver-present: pass
clk-mt8192-ipe-probed: pass
clk-mt8192-mdp-driver-present: pass
clk-mt8192-mdp-probed: pass
clk-mt8192-mfg-driver-present: pass
clk-mt8192-mfg-probed: pass
clk-mt8192-mm-driver-present: pass
clk-mt8192-mm-probed: pass
clk-mt8192-msdc-driver-present: pass
clk-mt8192-msdc-probed: pass
clk-mt8192-pericfg-probed: pass
clk-mt8192-topckgen-probed: pass
clk-mt8192-vdec-driver-present: pass
clk-mt8192-vdec-probed: pass
clk-mt8192-vdec_soc-probed: pass
clk-mt8192-venc-driver-present: pass
clk-mt8192-venc-probed: pass
cros-ec-i2c-tunnel-driver-present: pass
cros-ec-i2c-tunnel-probed: pass
cros-ec-keyb-driver-present: pass
cros-ec-keyb-probed: pass
cros-ec-pwm-driver-present: pass
cros-ec-pwm-probed: pass
cros-ec-regulator-driver-present: pass
cros-ec-regulator0-probed: pass
cros-ec-regulator1-probed: pass
cros-ec-rpmsg-driver-present: fail
cros-ec-spi-driver-present: pass
cros-ec-spi-probed: pass
cros-ec-typec-driver-present: pass
cros-ec-typec-probed: pass
deferred-probe-empty: pass
dmic-codec-driver-present: pass
dmic-codec-probed: fail
elan_i2c-driver-present: pass
elan_i2c-probed: fail
elants_i2c-driver-present: pass
elants_i2c-probed: fail
i2c-mt65xx-driver-present: pass
i2c0-mt65xx-probed: pass
i2c1-mt65xx-probed: pass
i2c2-mt65xx-probed: pass
i2c3-mt65xx-probed: pass
i2c7-mt65xx-probed: pass
leds_pwm-driver-present: pass
leds_pwm-probed: pass
mediatek,efuse-driver-present: pass
mediatek,efuse-probed: pass
mediatek-disp-aal-driver-present: pass
mediatek-disp-aal-probed: pass
mediatek-disp-ccorr-driver-present: pass
mediatek-disp-ccorr-probed: pass
mediatek-disp-color-driver-present: pass
mediatek-disp-color-probed: pass
mediatek-disp-gamma-driver-present: pass
mediatek-disp-gamma-probed: pass
mediatek-disp-ovl-driver-present: pass
mediatek-disp-ovl0-probed: pass
mediatek-disp-ovl2l0-probed: pass
mediatek-disp-ovl2l2-probed: pass
mediatek-disp-pwm-driver-present: pass
mediatek-disp-pwm-probed: fail
mediatek-disp-rdma-driver-present: pass
mediatek-disp-rdma0-probed: pass
mediatek-disp-rdma4-probed: pass
mediatek-dpi-driver-present: pass
mediatek-dpi-probed: fail
mediatek-drm-driver-present: pass
mediatek-drm-probed: pass
mediatek-mipi-tx-driver-present: pass
mediatek-mipi-tx-probed: fail
mediatek-mutex-driver-present: pass
mediatek-mutex-probed: pass
mt-pmic-pwrap-driver-present: pass
mt-pmic-pwrap-probed: pass
mt6315-regulator-driver-present: pass
mt6315-regulator6-probed: pass
mt6315-regulator7-probed: pass
mt6577-uart-driver-present: pass
mt6577-uart-probed: pass
mt7921e-driver-present: pass
mt7921e-probed: pass
mt8192-audio-driver-present: pass
mt8192-audio-probed: pass
mt8192-pinctrl-driver-present: pass
mt8192-pinctrl-probed: pass
mt8192_mt6359-driver-present: pass
mt8192_mt6359-probed: fail
mtk-cpufreq-hw-driver-present: pass
mtk-cpufreq-hw-probed: fail
mtk-dsi-driver-present: pass
mtk-dsi-probed: fail
mtk-iommu-driver-present: pass
mtk-iommu-probed: pass
mtk-mmsys-driver-present: pass
mtk-mmsys-probed: pass
mtk-msdc-driver-present: pass
mtk-msdc-probed: pass
mtk-pcie-gen3-driver-present: pass
mtk-pcie-gen3-probed: pass
mtk-power-controller-driver-present: pass
mtk-power-controller-probed: pass
mtk-scp-driver-present: pass
mtk-scp-probed: pass
mtk-smi-common-driver-present: pass
mtk-smi-common-probed: pass
mtk-smi-larb-driver-present: pass
mtk-smi-larb0-probed: pass
mtk-smi-larb1-probed: pass
mtk-smi-larb11-probed: pass
mtk-smi-larb13-probed: pass
mtk-smi-larb14-probed: pass
mtk-smi-larb16-probed: pass
mtk-smi-larb17-probed: pass
mtk-smi-larb18-probed: pass
mtk-smi-larb19-probed: pass
mtk-smi-larb2-probed: pass
mtk-smi-larb20-probed: pass
mtk-smi-larb4-probed: pass
mtk-smi-larb5-probed: pass
mtk-smi-larb7-probed: pass
mtk-smi-larb9-probed: pass
mtk-spi-driver-present: pass
mtk-spi-nor-driver-present: pass
mtk-spi-nor-probed: pass
mtk-spi1-probed: pass
mtk-spi5-probed: pass
mtk-tphy-driver-present: pass
mtk-tphy-probed: pass
mtk-vcodec-dec-driver-present: fail
mtk-vcodec-enc-driver-present: pass
mtk-vcodec-enc-probed: pass
mtk-wdt-driver-present: pass
mtk-wdt-probed: pass
panel-edp-driver-present: pass
panel-simple-dp-aux-driver-present: pass
panel-simple-dp-aux-probed: fail
panfrost-driver-present: pass
panfrost-probed: fail
pwm-backlight-driver-present: pass
pwm-backlight-probed: fail
rt1015p-driver-present: pass
rt1015p-probed: fail
rt5682-driver-present: pass
rt5682-probed: fail
sbs-battery-driver-present: pass
sbs-battery-probed: pass
spmi-mtk-driver-present: pass
spmi-mtk-probed: pass
tpm-chip-is-online: skip
tpm_tis_spi-driver-present: pass
tpm_tis_spi-probed: pass
uvcvideo-driver-present: pass
uvcvideo0-probed: pass
uvcvideo1-probed: pass
xhci-mtk-driver-present: pass
xhci-mtk-probed: pass
11817 22:57:49.354202 end: 4.1 lava-test-shell (duration 00:00:37) [common]
11818 22:57:49.354323 end: 4 lava-test-retry (duration 00:00:37) [common]
11819 22:57:49.354411 start: 5 finalize (timeout 00:07:09) [common]
11820 22:57:49.354502 start: 5.1 power-off (timeout 00:00:30) [common]
11821 22:57:49.354687 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=off'
11822 22:57:49.434282 >> Command sent successfully.
11823 22:57:49.437038 Returned 0 in 0 seconds
11824 22:57:49.537448 end: 5.1 power-off (duration 00:00:00) [common]
11826 22:57:49.537784 start: 5.2 read-feedback (timeout 00:07:09) [common]
11827 22:57:49.538047 Listened to connection for namespace 'common' for up to 1s
11828 22:57:50.538102 Finalising connection for namespace 'common'
11829 22:57:50.538328 Disconnecting from shell: Finalise
11830 22:57:50.538476 / #
11831 22:57:50.638843 end: 5.2 read-feedback (duration 00:00:01) [common]
11832 22:57:50.639070 end: 5 finalize (duration 00:00:01) [common]
11833 22:57:50.639226 Cleaning after the job
11834 22:57:50.639329 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597665/tftp-deploy-ltd01qmt/ramdisk
11835 22:57:50.641481 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597665/tftp-deploy-ltd01qmt/kernel
11836 22:57:50.651219 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597665/tftp-deploy-ltd01qmt/dtb
11837 22:57:50.651495 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597665/tftp-deploy-ltd01qmt/nfsrootfs
11838 22:57:50.709643 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597665/tftp-deploy-ltd01qmt/modules
11839 22:57:50.715471 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10597665
11840 22:57:51.060618 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10597665
11841 22:57:51.060826 Job finished correctly