Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 31
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 26
1 22:54:50.946459 lava-dispatcher, installed at version: 2023.05.1
2 22:54:50.946670 start: 0 validate
3 22:54:50.946794 Start time: 2023-06-05 22:54:50.946787+00:00 (UTC)
4 22:54:50.946916 Using caching service: 'http://localhost/cache/?uri=%s'
5 22:54:50.947044 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-cros-ec%2F20230527.0%2Farm64%2Frootfs.cpio.gz exists
6 22:54:51.238647 Using caching service: 'http://localhost/cache/?uri=%s'
7 22:54:51.238833 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1314-g1ab0ac1d7e2e3%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 22:54:51.239917 Using caching service: 'http://localhost/cache/?uri=%s'
9 22:54:51.240046 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1314-g1ab0ac1d7e2e3%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 22:54:51.525727 Using caching service: 'http://localhost/cache/?uri=%s'
11 22:54:51.525924 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1314-g1ab0ac1d7e2e3%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 22:54:51.811892 validate duration: 0.87
14 22:54:51.812178 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 22:54:51.812278 start: 1.1 download-retry (timeout 00:10:00) [common]
16 22:54:51.812406 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 22:54:51.812535 Not decompressing ramdisk as can be used compressed.
18 22:54:51.812622 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-cros-ec/20230527.0/arm64/rootfs.cpio.gz
19 22:54:51.812687 saving as /var/lib/lava/dispatcher/tmp/10597662/tftp-deploy-29_5pyne/ramdisk/rootfs.cpio.gz
20 22:54:51.812751 total size: 34405874 (32MB)
21 22:54:51.813770 progress 0% (0MB)
22 22:54:51.823034 progress 5% (1MB)
23 22:54:51.832686 progress 10% (3MB)
24 22:54:51.842032 progress 15% (4MB)
25 22:54:51.851071 progress 20% (6MB)
26 22:54:51.861660 progress 25% (8MB)
27 22:54:51.871430 progress 30% (9MB)
28 22:54:51.880651 progress 35% (11MB)
29 22:54:51.889708 progress 40% (13MB)
30 22:54:51.898800 progress 45% (14MB)
31 22:54:51.907799 progress 50% (16MB)
32 22:54:51.917135 progress 55% (18MB)
33 22:54:51.926413 progress 60% (19MB)
34 22:54:51.935811 progress 65% (21MB)
35 22:54:51.944764 progress 70% (22MB)
36 22:54:51.953909 progress 75% (24MB)
37 22:54:51.962849 progress 80% (26MB)
38 22:54:51.972012 progress 85% (27MB)
39 22:54:51.980862 progress 90% (29MB)
40 22:54:51.989863 progress 95% (31MB)
41 22:54:51.998633 progress 100% (32MB)
42 22:54:51.998939 32MB downloaded in 0.19s (176.23MB/s)
43 22:54:51.999120 end: 1.1.1 http-download (duration 00:00:00) [common]
45 22:54:51.999394 end: 1.1 download-retry (duration 00:00:00) [common]
46 22:54:51.999485 start: 1.2 download-retry (timeout 00:10:00) [common]
47 22:54:51.999575 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 22:54:51.999706 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1314-g1ab0ac1d7e2e3/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 22:54:51.999787 saving as /var/lib/lava/dispatcher/tmp/10597662/tftp-deploy-29_5pyne/kernel/Image
50 22:54:51.999854 total size: 45746688 (43MB)
51 22:54:51.999919 No compression specified
52 22:54:52.001047 progress 0% (0MB)
53 22:54:52.012786 progress 5% (2MB)
54 22:54:52.024690 progress 10% (4MB)
55 22:54:52.036511 progress 15% (6MB)
56 22:54:52.048371 progress 20% (8MB)
57 22:54:52.060150 progress 25% (10MB)
58 22:54:52.071682 progress 30% (13MB)
59 22:54:52.083394 progress 35% (15MB)
60 22:54:52.095015 progress 40% (17MB)
61 22:54:52.106588 progress 45% (19MB)
62 22:54:52.118214 progress 50% (21MB)
63 22:54:52.129874 progress 55% (24MB)
64 22:54:52.142137 progress 60% (26MB)
65 22:54:52.153901 progress 65% (28MB)
66 22:54:52.166833 progress 70% (30MB)
67 22:54:52.178878 progress 75% (32MB)
68 22:54:52.190608 progress 80% (34MB)
69 22:54:52.202538 progress 85% (37MB)
70 22:54:52.214354 progress 90% (39MB)
71 22:54:52.226088 progress 95% (41MB)
72 22:54:52.238137 progress 100% (43MB)
73 22:54:52.238321 43MB downloaded in 0.24s (182.95MB/s)
74 22:54:52.238483 end: 1.2.1 http-download (duration 00:00:00) [common]
76 22:54:52.238716 end: 1.2 download-retry (duration 00:00:00) [common]
77 22:54:52.238805 start: 1.3 download-retry (timeout 00:10:00) [common]
78 22:54:52.238895 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 22:54:52.239030 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1314-g1ab0ac1d7e2e3/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 22:54:52.239100 saving as /var/lib/lava/dispatcher/tmp/10597662/tftp-deploy-29_5pyne/dtb/mt8192-asurada-spherion-r0.dtb
81 22:54:52.239161 total size: 46924 (0MB)
82 22:54:52.239225 No compression specified
83 22:54:52.240393 progress 69% (0MB)
84 22:54:52.240671 progress 100% (0MB)
85 22:54:52.240826 0MB downloaded in 0.00s (26.91MB/s)
86 22:54:52.240952 end: 1.3.1 http-download (duration 00:00:00) [common]
88 22:54:52.241187 end: 1.3 download-retry (duration 00:00:00) [common]
89 22:54:52.241273 start: 1.4 download-retry (timeout 00:10:00) [common]
90 22:54:52.241355 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 22:54:52.241466 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1314-g1ab0ac1d7e2e3/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 22:54:52.241537 saving as /var/lib/lava/dispatcher/tmp/10597662/tftp-deploy-29_5pyne/modules/modules.tar
93 22:54:52.241598 total size: 8552396 (8MB)
94 22:54:52.241658 Using unxz to decompress xz
95 22:54:52.245348 progress 0% (0MB)
96 22:54:52.268572 progress 5% (0MB)
97 22:54:52.293689 progress 10% (0MB)
98 22:54:52.325864 progress 15% (1MB)
99 22:54:52.353777 progress 20% (1MB)
100 22:54:52.381755 progress 25% (2MB)
101 22:54:52.409689 progress 30% (2MB)
102 22:54:52.438261 progress 35% (2MB)
103 22:54:52.465637 progress 40% (3MB)
104 22:54:52.494313 progress 45% (3MB)
105 22:54:52.522086 progress 50% (4MB)
106 22:54:52.549179 progress 55% (4MB)
107 22:54:52.575106 progress 60% (4MB)
108 22:54:52.601913 progress 65% (5MB)
109 22:54:52.629050 progress 70% (5MB)
110 22:54:52.653821 progress 75% (6MB)
111 22:54:52.680536 progress 80% (6MB)
112 22:54:52.706809 progress 85% (6MB)
113 22:54:52.732059 progress 90% (7MB)
114 22:54:52.756665 progress 95% (7MB)
115 22:54:52.781573 progress 100% (8MB)
116 22:54:52.788680 8MB downloaded in 0.55s (14.91MB/s)
117 22:54:52.788997 end: 1.4.1 http-download (duration 00:00:01) [common]
119 22:54:52.789263 end: 1.4 download-retry (duration 00:00:01) [common]
120 22:54:52.789357 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 22:54:52.789454 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 22:54:52.789537 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 22:54:52.789624 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 22:54:52.789846 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10597662/lava-overlay-dtkqlhj3
125 22:54:52.789972 makedir: /var/lib/lava/dispatcher/tmp/10597662/lava-overlay-dtkqlhj3/lava-10597662/bin
126 22:54:52.790072 makedir: /var/lib/lava/dispatcher/tmp/10597662/lava-overlay-dtkqlhj3/lava-10597662/tests
127 22:54:52.790167 makedir: /var/lib/lava/dispatcher/tmp/10597662/lava-overlay-dtkqlhj3/lava-10597662/results
128 22:54:52.790279 Creating /var/lib/lava/dispatcher/tmp/10597662/lava-overlay-dtkqlhj3/lava-10597662/bin/lava-add-keys
129 22:54:52.790419 Creating /var/lib/lava/dispatcher/tmp/10597662/lava-overlay-dtkqlhj3/lava-10597662/bin/lava-add-sources
130 22:54:52.790562 Creating /var/lib/lava/dispatcher/tmp/10597662/lava-overlay-dtkqlhj3/lava-10597662/bin/lava-background-process-start
131 22:54:52.790726 Creating /var/lib/lava/dispatcher/tmp/10597662/lava-overlay-dtkqlhj3/lava-10597662/bin/lava-background-process-stop
132 22:54:52.790849 Creating /var/lib/lava/dispatcher/tmp/10597662/lava-overlay-dtkqlhj3/lava-10597662/bin/lava-common-functions
133 22:54:52.790968 Creating /var/lib/lava/dispatcher/tmp/10597662/lava-overlay-dtkqlhj3/lava-10597662/bin/lava-echo-ipv4
134 22:54:52.791086 Creating /var/lib/lava/dispatcher/tmp/10597662/lava-overlay-dtkqlhj3/lava-10597662/bin/lava-install-packages
135 22:54:52.791203 Creating /var/lib/lava/dispatcher/tmp/10597662/lava-overlay-dtkqlhj3/lava-10597662/bin/lava-installed-packages
136 22:54:52.791320 Creating /var/lib/lava/dispatcher/tmp/10597662/lava-overlay-dtkqlhj3/lava-10597662/bin/lava-os-build
137 22:54:52.791492 Creating /var/lib/lava/dispatcher/tmp/10597662/lava-overlay-dtkqlhj3/lava-10597662/bin/lava-probe-channel
138 22:54:52.791612 Creating /var/lib/lava/dispatcher/tmp/10597662/lava-overlay-dtkqlhj3/lava-10597662/bin/lava-probe-ip
139 22:54:52.791729 Creating /var/lib/lava/dispatcher/tmp/10597662/lava-overlay-dtkqlhj3/lava-10597662/bin/lava-target-ip
140 22:54:52.791885 Creating /var/lib/lava/dispatcher/tmp/10597662/lava-overlay-dtkqlhj3/lava-10597662/bin/lava-target-mac
141 22:54:52.792224 Creating /var/lib/lava/dispatcher/tmp/10597662/lava-overlay-dtkqlhj3/lava-10597662/bin/lava-target-storage
142 22:54:52.792426 Creating /var/lib/lava/dispatcher/tmp/10597662/lava-overlay-dtkqlhj3/lava-10597662/bin/lava-test-case
143 22:54:52.792623 Creating /var/lib/lava/dispatcher/tmp/10597662/lava-overlay-dtkqlhj3/lava-10597662/bin/lava-test-event
144 22:54:52.792898 Creating /var/lib/lava/dispatcher/tmp/10597662/lava-overlay-dtkqlhj3/lava-10597662/bin/lava-test-feedback
145 22:54:52.793074 Creating /var/lib/lava/dispatcher/tmp/10597662/lava-overlay-dtkqlhj3/lava-10597662/bin/lava-test-raise
146 22:54:52.793271 Creating /var/lib/lava/dispatcher/tmp/10597662/lava-overlay-dtkqlhj3/lava-10597662/bin/lava-test-reference
147 22:54:52.793456 Creating /var/lib/lava/dispatcher/tmp/10597662/lava-overlay-dtkqlhj3/lava-10597662/bin/lava-test-runner
148 22:54:52.793638 Creating /var/lib/lava/dispatcher/tmp/10597662/lava-overlay-dtkqlhj3/lava-10597662/bin/lava-test-set
149 22:54:52.793792 Creating /var/lib/lava/dispatcher/tmp/10597662/lava-overlay-dtkqlhj3/lava-10597662/bin/lava-test-shell
150 22:54:52.793975 Updating /var/lib/lava/dispatcher/tmp/10597662/lava-overlay-dtkqlhj3/lava-10597662/bin/lava-install-packages (oe)
151 22:54:52.794168 Updating /var/lib/lava/dispatcher/tmp/10597662/lava-overlay-dtkqlhj3/lava-10597662/bin/lava-installed-packages (oe)
152 22:54:52.794317 Creating /var/lib/lava/dispatcher/tmp/10597662/lava-overlay-dtkqlhj3/lava-10597662/environment
153 22:54:52.794458 LAVA metadata
154 22:54:52.794578 - LAVA_JOB_ID=10597662
155 22:54:52.794689 - LAVA_DISPATCHER_IP=192.168.201.1
156 22:54:52.794847 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 22:54:52.794956 skipped lava-vland-overlay
158 22:54:52.795062 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 22:54:52.795222 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 22:54:52.795318 skipped lava-multinode-overlay
161 22:54:52.795449 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 22:54:52.795564 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 22:54:52.795668 Loading test definitions
164 22:54:52.795794 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 22:54:52.795899 Using /lava-10597662 at stage 0
166 22:54:52.796306 uuid=10597662_1.5.2.3.1 testdef=None
167 22:54:52.796423 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 22:54:52.796540 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 22:54:52.797243 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 22:54:52.797593 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 22:54:52.798452 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 22:54:52.798814 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 22:54:52.799591 runner path: /var/lib/lava/dispatcher/tmp/10597662/lava-overlay-dtkqlhj3/lava-10597662/0/tests/0_cros-ec test_uuid 10597662_1.5.2.3.1
176 22:54:52.799741 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 22:54:52.799951 Creating lava-test-runner.conf files
179 22:54:52.800015 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10597662/lava-overlay-dtkqlhj3/lava-10597662/0 for stage 0
180 22:54:52.800104 - 0_cros-ec
181 22:54:52.800198 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 22:54:52.800281 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 22:54:52.807775 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 22:54:52.807909 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 22:54:52.808000 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 22:54:52.808089 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 22:54:52.808183 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 22:54:53.773945 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 22:54:53.774325 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 22:54:53.774447 extracting modules file /var/lib/lava/dispatcher/tmp/10597662/tftp-deploy-29_5pyne/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10597662/extract-overlay-ramdisk-vgllf9lj/ramdisk
191 22:54:53.983806 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 22:54:53.983984 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 22:54:53.984080 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10597662/compress-overlay-_l13bwno/overlay-1.5.2.4.tar.gz to ramdisk
194 22:54:53.984153 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10597662/compress-overlay-_l13bwno/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10597662/extract-overlay-ramdisk-vgllf9lj/ramdisk
195 22:54:53.990387 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 22:54:53.990515 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 22:54:53.990608 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 22:54:53.990713 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 22:54:53.990797 Building ramdisk /var/lib/lava/dispatcher/tmp/10597662/extract-overlay-ramdisk-vgllf9lj/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10597662/extract-overlay-ramdisk-vgllf9lj/ramdisk
200 22:54:54.687140 >> 269476 blocks
201 22:54:59.396999 rename /var/lib/lava/dispatcher/tmp/10597662/extract-overlay-ramdisk-vgllf9lj/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10597662/tftp-deploy-29_5pyne/ramdisk/ramdisk.cpio.gz
202 22:54:59.397430 end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
203 22:54:59.397565 start: 1.5.8 prepare-kernel (timeout 00:09:52) [common]
204 22:54:59.397663 start: 1.5.8.1 prepare-fit (timeout 00:09:52) [common]
205 22:54:59.397773 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10597662/tftp-deploy-29_5pyne/kernel/Image'
206 22:55:11.072413 Returned 0 in 11 seconds
207 22:55:11.173009 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10597662/tftp-deploy-29_5pyne/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10597662/tftp-deploy-29_5pyne/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10597662/tftp-deploy-29_5pyne/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10597662/tftp-deploy-29_5pyne/kernel/image.itb
208 22:55:11.823488 output: FIT description: Kernel Image image with one or more FDT blobs
209 22:55:11.823835 output: Created: Mon Jun 5 23:55:11 2023
210 22:55:11.823918 output: Image 0 (kernel-1)
211 22:55:11.823985 output: Description:
212 22:55:11.824050 output: Created: Mon Jun 5 23:55:11 2023
213 22:55:11.824109 output: Type: Kernel Image
214 22:55:11.824166 output: Compression: lzma compressed
215 22:55:11.824225 output: Data Size: 10085945 Bytes = 9849.56 KiB = 9.62 MiB
216 22:55:11.824282 output: Architecture: AArch64
217 22:55:11.824339 output: OS: Linux
218 22:55:11.824398 output: Load Address: 0x00000000
219 22:55:11.824456 output: Entry Point: 0x00000000
220 22:55:11.824511 output: Hash algo: crc32
221 22:55:11.824564 output: Hash value: b2943ff2
222 22:55:11.824617 output: Image 1 (fdt-1)
223 22:55:11.824669 output: Description: mt8192-asurada-spherion-r0
224 22:55:11.824722 output: Created: Mon Jun 5 23:55:11 2023
225 22:55:11.824775 output: Type: Flat Device Tree
226 22:55:11.824828 output: Compression: uncompressed
227 22:55:11.824881 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
228 22:55:11.824934 output: Architecture: AArch64
229 22:55:11.824986 output: Hash algo: crc32
230 22:55:11.825039 output: Hash value: 1df858fa
231 22:55:11.825092 output: Image 2 (ramdisk-1)
232 22:55:11.825143 output: Description: unavailable
233 22:55:11.825195 output: Created: Mon Jun 5 23:55:11 2023
234 22:55:11.825248 output: Type: RAMDisk Image
235 22:55:11.825301 output: Compression: Unknown Compression
236 22:55:11.825353 output: Data Size: 47379105 Bytes = 46268.66 KiB = 45.18 MiB
237 22:55:11.825406 output: Architecture: AArch64
238 22:55:11.825458 output: OS: Linux
239 22:55:11.825510 output: Load Address: unavailable
240 22:55:11.825562 output: Entry Point: unavailable
241 22:55:11.825615 output: Hash algo: crc32
242 22:55:11.825666 output: Hash value: 66608d4a
243 22:55:11.825718 output: Default Configuration: 'conf-1'
244 22:55:11.825771 output: Configuration 0 (conf-1)
245 22:55:11.825823 output: Description: mt8192-asurada-spherion-r0
246 22:55:11.825875 output: Kernel: kernel-1
247 22:55:11.825927 output: Init Ramdisk: ramdisk-1
248 22:55:11.825979 output: FDT: fdt-1
249 22:55:11.826032 output: Loadables: kernel-1
250 22:55:11.826084 output:
251 22:55:11.826273 end: 1.5.8.1 prepare-fit (duration 00:00:12) [common]
252 22:55:11.826374 end: 1.5.8 prepare-kernel (duration 00:00:12) [common]
253 22:55:11.826483 end: 1.5 prepare-tftp-overlay (duration 00:00:19) [common]
254 22:55:11.826579 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:40) [common]
255 22:55:11.826655 No LXC device requested
256 22:55:11.826734 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 22:55:11.826823 start: 1.7 deploy-device-env (timeout 00:09:40) [common]
258 22:55:11.826900 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 22:55:11.826972 Checking files for TFTP limit of 4294967296 bytes.
260 22:55:11.827531 end: 1 tftp-deploy (duration 00:00:20) [common]
261 22:55:11.827636 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 22:55:11.827727 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 22:55:11.827848 substitutions:
264 22:55:11.827916 - {DTB}: 10597662/tftp-deploy-29_5pyne/dtb/mt8192-asurada-spherion-r0.dtb
265 22:55:11.827981 - {INITRD}: 10597662/tftp-deploy-29_5pyne/ramdisk/ramdisk.cpio.gz
266 22:55:11.828041 - {KERNEL}: 10597662/tftp-deploy-29_5pyne/kernel/Image
267 22:55:11.828098 - {LAVA_MAC}: None
268 22:55:11.828153 - {PRESEED_CONFIG}: None
269 22:55:11.828208 - {PRESEED_LOCAL}: None
270 22:55:11.828262 - {RAMDISK}: 10597662/tftp-deploy-29_5pyne/ramdisk/ramdisk.cpio.gz
271 22:55:11.828315 - {ROOT_PART}: None
272 22:55:11.828368 - {ROOT}: None
273 22:55:11.828421 - {SERVER_IP}: 192.168.201.1
274 22:55:11.828474 - {TEE}: None
275 22:55:11.828528 Parsed boot commands:
276 22:55:11.828582 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 22:55:11.828752 Parsed boot commands: tftpboot 192.168.201.1 10597662/tftp-deploy-29_5pyne/kernel/image.itb 10597662/tftp-deploy-29_5pyne/kernel/cmdline
278 22:55:11.828840 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 22:55:11.828922 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 22:55:11.829012 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 22:55:11.829099 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 22:55:11.829167 Not connected, no need to disconnect.
283 22:55:11.829240 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 22:55:11.829319 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 22:55:11.829385 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-3'
286 22:55:11.832780 Setting prompt string to ['lava-test: # ']
287 22:55:11.833113 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 22:55:11.833221 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 22:55:11.833318 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 22:55:11.833415 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 22:55:11.833664 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=reboot'
292 22:55:16.966475 >> Command sent successfully.
293 22:55:16.968856 Returned 0 in 5 seconds
294 22:55:17.069246 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 22:55:17.069845 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 22:55:17.069960 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 22:55:17.070060 Setting prompt string to 'Starting depthcharge on Spherion...'
299 22:55:17.070143 Changing prompt to 'Starting depthcharge on Spherion...'
300 22:55:17.070231 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 22:55:17.070542 [Enter `^Ec?' for help]
302 22:55:17.242614
303 22:55:17.242791
304 22:55:17.242889 F0: 102B 0000
305 22:55:17.242971
306 22:55:17.243071 F3: 1001 0000 [0200]
307 22:55:17.245523
308 22:55:17.245609 F3: 1001 0000
309 22:55:17.245695
310 22:55:17.245795 F7: 102D 0000
311 22:55:17.245895
312 22:55:17.249426 F1: 0000 0000
313 22:55:17.249513
314 22:55:17.249597 V0: 0000 0000 [0001]
315 22:55:17.249678
316 22:55:17.252159 00: 0007 8000
317 22:55:17.252247
318 22:55:17.252332 01: 0000 0000
319 22:55:17.252415
320 22:55:17.255558 BP: 0C00 0209 [0000]
321 22:55:17.255644
322 22:55:17.255728 G0: 1182 0000
323 22:55:17.255808
324 22:55:17.259304 EC: 0000 0021 [4000]
325 22:55:17.259413
326 22:55:17.259497 S7: 0000 0000 [0000]
327 22:55:17.259578
328 22:55:17.262880 CC: 0000 0000 [0001]
329 22:55:17.262966
330 22:55:17.263051 T0: 0000 0040 [010F]
331 22:55:17.263152
332 22:55:17.263250 Jump to BL
333 22:55:17.263353
334 22:55:17.289429
335 22:55:17.289517
336 22:55:17.289603
337 22:55:17.296132 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 22:55:17.299893 ARM64: Exception handlers installed.
339 22:55:17.303590 ARM64: Testing exception
340 22:55:17.306888 ARM64: Done test exception
341 22:55:17.313303 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 22:55:17.323718 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 22:55:17.330304 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 22:55:17.340373 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 22:55:17.346649 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 22:55:17.357253 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 22:55:17.367451 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 22:55:17.374019 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 22:55:17.392261 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 22:55:17.396108 WDT: Last reset was cold boot
351 22:55:17.399065 SPI1(PAD0) initialized at 2873684 Hz
352 22:55:17.402237 SPI5(PAD0) initialized at 992727 Hz
353 22:55:17.405723 VBOOT: Loading verstage.
354 22:55:17.412451 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 22:55:17.415569 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 22:55:17.418810 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 22:55:17.422020 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 22:55:17.429699 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 22:55:17.436022 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 22:55:17.446974 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
361 22:55:17.447079
362 22:55:17.447172
363 22:55:17.456940 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 22:55:17.460317 ARM64: Exception handlers installed.
365 22:55:17.463823 ARM64: Testing exception
366 22:55:17.463925 ARM64: Done test exception
367 22:55:17.470308 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 22:55:17.473982 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 22:55:17.488022 Probing TPM: . done!
370 22:55:17.488138 TPM ready after 0 ms
371 22:55:17.492900 Connected to device vid:did:rid of 1ae0:0028:00
372 22:55:17.504490 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
373 22:55:17.561390 Initialized TPM device CR50 revision 0
374 22:55:17.572592 tlcl_send_startup: Startup return code is 0
375 22:55:17.572706 TPM: setup succeeded
376 22:55:17.584407 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 22:55:17.592877 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 22:55:17.605421 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 22:55:17.615213 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 22:55:17.618418 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 22:55:17.622967 in-header: 03 07 00 00 08 00 00 00
382 22:55:17.626421 in-data: aa e4 47 04 13 02 00 00
383 22:55:17.629451 Chrome EC: UHEPI supported
384 22:55:17.636878 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 22:55:17.640926 in-header: 03 ad 00 00 08 00 00 00
386 22:55:17.644465 in-data: 00 20 20 08 00 00 00 00
387 22:55:17.644538 Phase 1
388 22:55:17.648424 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 22:55:17.655714 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 22:55:17.659480 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 22:55:17.662955 Recovery requested (1009000e)
392 22:55:17.672801 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 22:55:17.679376 tlcl_extend: response is 0
394 22:55:17.689077 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 22:55:17.694951 tlcl_extend: response is 0
396 22:55:17.701774 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 22:55:17.721925 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
398 22:55:17.728581 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 22:55:17.728666
400 22:55:17.728732
401 22:55:17.738618 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 22:55:17.742440 ARM64: Exception handlers installed.
403 22:55:17.742524 ARM64: Testing exception
404 22:55:17.746121 ARM64: Done test exception
405 22:55:17.767549 pmic_efuse_setting: Set efuses in 11 msecs
406 22:55:17.770813 pmwrap_interface_init: Select PMIF_VLD_RDY
407 22:55:17.777538 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 22:55:17.780876 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 22:55:17.784376 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 22:55:17.791991 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 22:55:17.795076 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 22:55:17.798916 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 22:55:17.805976 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 22:55:17.809830 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 22:55:17.813707 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 22:55:17.820709 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 22:55:17.824363 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 22:55:17.828291 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 22:55:17.831874 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 22:55:17.838952 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 22:55:17.846683 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 22:55:17.849988 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 22:55:17.857314 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 22:55:17.861527 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 22:55:17.868494 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 22:55:17.871791 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 22:55:17.879375 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 22:55:17.883237 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 22:55:17.890594 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 22:55:17.894491 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 22:55:17.900836 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 22:55:17.908406 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 22:55:17.911899 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 22:55:17.915815 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 22:55:17.922918 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 22:55:17.926350 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 22:55:17.930246 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 22:55:17.937706 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 22:55:17.941181 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 22:55:17.944929 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 22:55:17.951799 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 22:55:17.955950 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 22:55:17.963033 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 22:55:17.966767 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 22:55:17.970906 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 22:55:17.974294 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 22:55:17.978103 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 22:55:17.985555 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 22:55:17.989571 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 22:55:17.992604 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 22:55:17.996195 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 22:55:18.003409 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 22:55:18.006820 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 22:55:18.010770 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 22:55:18.014158 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 22:55:18.017885 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 22:55:18.021768 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 22:55:18.029066 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 22:55:18.039846 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 22:55:18.044062 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 22:55:18.051106 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 22:55:18.058118 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 22:55:18.065610 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 22:55:18.069050 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 22:55:18.072552 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 22:55:18.080307 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x0
467 22:55:18.084427 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 22:55:18.091938 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
469 22:55:18.094957 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 22:55:18.104236 [RTC]rtc_get_frequency_meter,154: input=15, output=790
471 22:55:18.114304 [RTC]rtc_get_frequency_meter,154: input=23, output=979
472 22:55:18.123611 [RTC]rtc_get_frequency_meter,154: input=19, output=884
473 22:55:18.133476 [RTC]rtc_get_frequency_meter,154: input=17, output=838
474 22:55:18.142747 [RTC]rtc_get_frequency_meter,154: input=16, output=815
475 22:55:18.152009 [RTC]rtc_get_frequency_meter,154: input=15, output=790
476 22:55:18.162097 [RTC]rtc_get_frequency_meter,154: input=16, output=814
477 22:55:18.165734 [RTC]rtc_eosc_cali,47: left: 15, middle: 15, right: 16
478 22:55:18.169337 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
479 22:55:18.176969 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 22:55:18.180415 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
481 22:55:18.183916 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 22:55:18.187408 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
483 22:55:18.191306 ADC[4]: Raw value=902436 ID=7
484 22:55:18.195285 ADC[3]: Raw value=213336 ID=1
485 22:55:18.195397 RAM Code: 0x71
486 22:55:18.199513 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 22:55:18.203277 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 22:55:18.213401 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 22:55:18.220895 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 22:55:18.220986 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 22:55:18.224882 in-header: 03 07 00 00 08 00 00 00
492 22:55:18.228804 in-data: aa e4 47 04 13 02 00 00
493 22:55:18.232337 Chrome EC: UHEPI supported
494 22:55:18.239432 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 22:55:18.243174 in-header: 03 ed 00 00 08 00 00 00
496 22:55:18.246769 in-data: 80 20 60 08 00 00 00 00
497 22:55:18.250613 MRC: failed to locate region type 0.
498 22:55:18.254193 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 22:55:18.258264 DRAM-K: Running full calibration
500 22:55:18.265631 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 22:55:18.265718 header.status = 0x0
502 22:55:18.269465 header.version = 0x6 (expected: 0x6)
503 22:55:18.273373 header.size = 0xd00 (expected: 0xd00)
504 22:55:18.276868 header.flags = 0x0
505 22:55:18.280398 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 22:55:18.299686 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
507 22:55:18.306802 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 22:55:18.311082 dram_init: ddr_geometry: 2
509 22:55:18.311168 [EMI] MDL number = 2
510 22:55:18.314414 [EMI] Get MDL freq = 0
511 22:55:18.314500 dram_init: ddr_type: 0
512 22:55:18.318140 is_discrete_lpddr4: 1
513 22:55:18.322201 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 22:55:18.322287
515 22:55:18.322372
516 22:55:18.322453 [Bian_co] ETT version 0.0.0.1
517 22:55:18.329335 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 22:55:18.329422
519 22:55:18.333234 dramc_set_vcore_voltage set vcore to 650000
520 22:55:18.333320 Read voltage for 800, 4
521 22:55:18.336671 Vio18 = 0
522 22:55:18.336757 Vcore = 650000
523 22:55:18.336842 Vdram = 0
524 22:55:18.336921 Vddq = 0
525 22:55:18.339935 Vmddr = 0
526 22:55:18.340024 dram_init: config_dvfs: 1
527 22:55:18.347235 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 22:55:18.353455 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 22:55:18.356680 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=10
530 22:55:18.360307 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=10
531 22:55:18.363617 [SwImpedanceCal] DRVP=12, DRVN=25, ODTN=9
532 22:55:18.367499 freq_region=1, Reg: DRVP=12, DRVN=25, ODTN=9
533 22:55:18.370560 MEM_TYPE=3, freq_sel=18
534 22:55:18.373741 sv_algorithm_assistance_LP4_1600
535 22:55:18.376932 ============ PULL DRAM RESETB DOWN ============
536 22:55:18.380273 ========== PULL DRAM RESETB DOWN end =========
537 22:55:18.386738 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 22:55:18.390683 ===================================
539 22:55:18.390770 LPDDR4 DRAM CONFIGURATION
540 22:55:18.393963 ===================================
541 22:55:18.396897 EX_ROW_EN[0] = 0x0
542 22:55:18.396982 EX_ROW_EN[1] = 0x0
543 22:55:18.400504 LP4Y_EN = 0x0
544 22:55:18.400590 WORK_FSP = 0x0
545 22:55:18.403727 WL = 0x2
546 22:55:18.403813 RL = 0x2
547 22:55:18.406792 BL = 0x2
548 22:55:18.410027 RPST = 0x0
549 22:55:18.410113 RD_PRE = 0x0
550 22:55:18.413936 WR_PRE = 0x1
551 22:55:18.414023 WR_PST = 0x0
552 22:55:18.416635 DBI_WR = 0x0
553 22:55:18.416721 DBI_RD = 0x0
554 22:55:18.419930 OTF = 0x1
555 22:55:18.423198 ===================================
556 22:55:18.426583 ===================================
557 22:55:18.426667 ANA top config
558 22:55:18.430265 ===================================
559 22:55:18.433490 DLL_ASYNC_EN = 0
560 22:55:18.436695 ALL_SLAVE_EN = 1
561 22:55:18.436778 NEW_RANK_MODE = 1
562 22:55:18.440242 DLL_IDLE_MODE = 1
563 22:55:18.443598 LP45_APHY_COMB_EN = 1
564 22:55:18.446686 TX_ODT_DIS = 1
565 22:55:18.446816 NEW_8X_MODE = 1
566 22:55:18.450113 ===================================
567 22:55:18.453631 ===================================
568 22:55:18.457183 data_rate = 1600
569 22:55:18.460144 CKR = 1
570 22:55:18.463729 DQ_P2S_RATIO = 8
571 22:55:18.467094 ===================================
572 22:55:18.470356 CA_P2S_RATIO = 8
573 22:55:18.473300 DQ_CA_OPEN = 0
574 22:55:18.473383 DQ_SEMI_OPEN = 0
575 22:55:18.477202 CA_SEMI_OPEN = 0
576 22:55:18.480005 CA_FULL_RATE = 0
577 22:55:18.483646 DQ_CKDIV4_EN = 1
578 22:55:18.487042 CA_CKDIV4_EN = 1
579 22:55:18.490251 CA_PREDIV_EN = 0
580 22:55:18.490334 PH8_DLY = 0
581 22:55:18.493494 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 22:55:18.496841 DQ_AAMCK_DIV = 4
583 22:55:18.500156 CA_AAMCK_DIV = 4
584 22:55:18.503589 CA_ADMCK_DIV = 4
585 22:55:18.503672 DQ_TRACK_CA_EN = 0
586 22:55:18.506812 CA_PICK = 800
587 22:55:18.510233 CA_MCKIO = 800
588 22:55:18.514161 MCKIO_SEMI = 0
589 22:55:18.517211 PLL_FREQ = 3068
590 22:55:18.520513 DQ_UI_PI_RATIO = 32
591 22:55:18.524298 CA_UI_PI_RATIO = 0
592 22:55:18.524385 ===================================
593 22:55:18.527762 ===================================
594 22:55:18.531607 memory_type:LPDDR4
595 22:55:18.535454 GP_NUM : 10
596 22:55:18.535540 SRAM_EN : 1
597 22:55:18.538962 MD32_EN : 0
598 22:55:18.542746 ===================================
599 22:55:18.542833 [ANA_INIT] >>>>>>>>>>>>>>
600 22:55:18.546704 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 22:55:18.549958 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 22:55:18.553800 ===================================
603 22:55:18.556758 data_rate = 1600,PCW = 0X7600
604 22:55:18.560308 ===================================
605 22:55:18.563496 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 22:55:18.566756 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 22:55:18.573366 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 22:55:18.576809 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 22:55:18.580179 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 22:55:18.583298 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 22:55:18.587522 [ANA_INIT] flow start
612 22:55:18.590820 [ANA_INIT] PLL >>>>>>>>
613 22:55:18.590904 [ANA_INIT] PLL <<<<<<<<
614 22:55:18.593660 [ANA_INIT] MIDPI >>>>>>>>
615 22:55:18.597391 [ANA_INIT] MIDPI <<<<<<<<
616 22:55:18.597493 [ANA_INIT] DLL >>>>>>>>
617 22:55:18.600153 [ANA_INIT] flow end
618 22:55:18.603624 ============ LP4 DIFF to SE enter ============
619 22:55:18.606789 ============ LP4 DIFF to SE exit ============
620 22:55:18.610488 [ANA_INIT] <<<<<<<<<<<<<
621 22:55:18.613904 [Flow] Enable top DCM control >>>>>
622 22:55:18.617406 [Flow] Enable top DCM control <<<<<
623 22:55:18.620499 Enable DLL master slave shuffle
624 22:55:18.627160 ==============================================================
625 22:55:18.627271 Gating Mode config
626 22:55:18.633878 ==============================================================
627 22:55:18.633989 Config description:
628 22:55:18.643718 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 22:55:18.650360 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 22:55:18.657401 SELPH_MODE 0: By rank 1: By Phase
631 22:55:18.660390 ==============================================================
632 22:55:18.664316 GAT_TRACK_EN = 1
633 22:55:18.667050 RX_GATING_MODE = 2
634 22:55:18.670674 RX_GATING_TRACK_MODE = 2
635 22:55:18.674258 SELPH_MODE = 1
636 22:55:18.677237 PICG_EARLY_EN = 1
637 22:55:18.680795 VALID_LAT_VALUE = 1
638 22:55:18.683776 ==============================================================
639 22:55:18.687119 Enter into Gating configuration >>>>
640 22:55:18.690441 Exit from Gating configuration <<<<
641 22:55:18.694194 Enter into DVFS_PRE_config >>>>>
642 22:55:18.707222 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 22:55:18.710423 Exit from DVFS_PRE_config <<<<<
644 22:55:18.710507 Enter into PICG configuration >>>>
645 22:55:18.713940 Exit from PICG configuration <<<<
646 22:55:18.717148 [RX_INPUT] configuration >>>>>
647 22:55:18.721036 [RX_INPUT] configuration <<<<<
648 22:55:18.727289 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 22:55:18.730663 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 22:55:18.737835 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 22:55:18.744767 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 22:55:18.751469 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 22:55:18.758224 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 22:55:18.761643 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 22:55:18.764808 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 22:55:18.767774 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 22:55:18.774873 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 22:55:18.778267 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 22:55:18.781142 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 22:55:18.784344 ===================================
661 22:55:18.787870 LPDDR4 DRAM CONFIGURATION
662 22:55:18.791818 ===================================
663 22:55:18.791902 EX_ROW_EN[0] = 0x0
664 22:55:18.794543 EX_ROW_EN[1] = 0x0
665 22:55:18.794630 LP4Y_EN = 0x0
666 22:55:18.798160 WORK_FSP = 0x0
667 22:55:18.798250 WL = 0x2
668 22:55:18.801300 RL = 0x2
669 22:55:18.801384 BL = 0x2
670 22:55:18.804692 RPST = 0x0
671 22:55:18.807851 RD_PRE = 0x0
672 22:55:18.807935 WR_PRE = 0x1
673 22:55:18.811157 WR_PST = 0x0
674 22:55:18.811267 DBI_WR = 0x0
675 22:55:18.814194 DBI_RD = 0x0
676 22:55:18.814278 OTF = 0x1
677 22:55:18.817814 ===================================
678 22:55:18.820992 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 22:55:18.824303 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 22:55:18.831176 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 22:55:18.834595 ===================================
682 22:55:18.838236 LPDDR4 DRAM CONFIGURATION
683 22:55:18.841428 ===================================
684 22:55:18.841513 EX_ROW_EN[0] = 0x10
685 22:55:18.844942 EX_ROW_EN[1] = 0x0
686 22:55:18.845026 LP4Y_EN = 0x0
687 22:55:18.848217 WORK_FSP = 0x0
688 22:55:18.848301 WL = 0x2
689 22:55:18.851610 RL = 0x2
690 22:55:18.851694 BL = 0x2
691 22:55:18.854787 RPST = 0x0
692 22:55:18.854871 RD_PRE = 0x0
693 22:55:18.858131 WR_PRE = 0x1
694 22:55:18.858215 WR_PST = 0x0
695 22:55:18.861797 DBI_WR = 0x0
696 22:55:18.861881 DBI_RD = 0x0
697 22:55:18.864762 OTF = 0x1
698 22:55:18.867960 ===================================
699 22:55:18.874664 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 22:55:18.877795 nWR fixed to 40
701 22:55:18.881296 [ModeRegInit_LP4] CH0 RK0
702 22:55:18.881380 [ModeRegInit_LP4] CH0 RK1
703 22:55:18.884849 [ModeRegInit_LP4] CH1 RK0
704 22:55:18.888309 [ModeRegInit_LP4] CH1 RK1
705 22:55:18.888393 match AC timing 13
706 22:55:18.894639 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 22:55:18.898027 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 22:55:18.901102 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 22:55:18.908193 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 22:55:18.911293 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 22:55:18.911384 [EMI DOE] emi_dcm 0
712 22:55:18.917957 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 22:55:18.918041 ==
714 22:55:18.921400 Dram Type= 6, Freq= 0, CH_0, rank 0
715 22:55:18.924880 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 22:55:18.924966 ==
717 22:55:18.931475 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 22:55:18.934421 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 22:55:18.945437 [CA 0] Center 37 (7~68) winsize 62
720 22:55:18.948204 [CA 1] Center 37 (6~68) winsize 63
721 22:55:18.951589 [CA 2] Center 35 (5~66) winsize 62
722 22:55:18.955264 [CA 3] Center 34 (4~65) winsize 62
723 22:55:18.958284 [CA 4] Center 33 (3~64) winsize 62
724 22:55:18.961554 [CA 5] Center 33 (3~64) winsize 62
725 22:55:18.961639
726 22:55:18.965450 [CmdBusTrainingLP45] Vref(ca) range 1: 34
727 22:55:18.965534
728 22:55:18.968701 [CATrainingPosCal] consider 1 rank data
729 22:55:18.972059 u2DelayCellTimex100 = 270/100 ps
730 22:55:18.975546 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
731 22:55:18.978652 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
732 22:55:18.985334 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
733 22:55:18.988369 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
734 22:55:18.992154 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
735 22:55:18.995557 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
736 22:55:18.995641
737 22:55:18.998514 CA PerBit enable=1, Macro0, CA PI delay=33
738 22:55:18.998598
739 22:55:19.001787 [CBTSetCACLKResult] CA Dly = 33
740 22:55:19.001870 CS Dly: 4 (0~35)
741 22:55:19.001938 ==
742 22:55:19.005171 Dram Type= 6, Freq= 0, CH_0, rank 1
743 22:55:19.011783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 22:55:19.011875 ==
745 22:55:19.015276 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 22:55:19.021829 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 22:55:19.031297 [CA 0] Center 37 (6~68) winsize 63
748 22:55:19.034715 [CA 1] Center 37 (7~68) winsize 62
749 22:55:19.037885 [CA 2] Center 35 (4~66) winsize 63
750 22:55:19.041135 [CA 3] Center 34 (4~65) winsize 62
751 22:55:19.044333 [CA 4] Center 34 (3~65) winsize 63
752 22:55:19.047991 [CA 5] Center 33 (3~64) winsize 62
753 22:55:19.048075
754 22:55:19.051172 [CmdBusTrainingLP45] Vref(ca) range 1: 34
755 22:55:19.051256
756 22:55:19.054796 [CATrainingPosCal] consider 2 rank data
757 22:55:19.058116 u2DelayCellTimex100 = 270/100 ps
758 22:55:19.061604 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
759 22:55:19.064784 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
760 22:55:19.071773 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
761 22:55:19.074610 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
762 22:55:19.077868 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
763 22:55:19.081567 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
764 22:55:19.081652
765 22:55:19.084648 CA PerBit enable=1, Macro0, CA PI delay=33
766 22:55:19.084733
767 22:55:19.088187 [CBTSetCACLKResult] CA Dly = 33
768 22:55:19.088271 CS Dly: 5 (0~38)
769 22:55:19.088338
770 22:55:19.091887 ----->DramcWriteLeveling(PI) begin...
771 22:55:19.094570 ==
772 22:55:19.098142 Dram Type= 6, Freq= 0, CH_0, rank 0
773 22:55:19.101417 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 22:55:19.101502 ==
775 22:55:19.105818 Write leveling (Byte 0): 31 => 31
776 22:55:19.105903 Write leveling (Byte 1): 27 => 27
777 22:55:19.109134 DramcWriteLeveling(PI) end<-----
778 22:55:19.109235
779 22:55:19.109303 ==
780 22:55:19.112836 Dram Type= 6, Freq= 0, CH_0, rank 0
781 22:55:19.116425 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 22:55:19.116509 ==
783 22:55:19.119637 [Gating] SW mode calibration
784 22:55:19.126953 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 22:55:19.133405 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 22:55:19.136798 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 22:55:19.140254 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
788 22:55:19.146987 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
789 22:55:19.150190 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
790 22:55:19.153502 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 22:55:19.160530 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 22:55:19.163746 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 22:55:19.166989 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 22:55:19.173649 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 22:55:19.176964 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 22:55:19.180260 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 22:55:19.187294 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 22:55:19.190279 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 22:55:19.193945 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 22:55:19.197238 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 22:55:19.203312 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 22:55:19.207233 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 22:55:19.210445 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 22:55:19.216949 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
805 22:55:19.220534 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
806 22:55:19.223385 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 22:55:19.230566 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 22:55:19.233378 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 22:55:19.236594 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 22:55:19.243833 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 22:55:19.247202 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 22:55:19.250130 0 9 8 | B1->B0 | 2323 2424 | 0 1 | (0 0) (1 1)
813 22:55:19.256835 0 9 12 | B1->B0 | 2929 3030 | 0 1 | (0 0) (1 1)
814 22:55:19.260270 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 22:55:19.263781 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 22:55:19.270235 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 22:55:19.273739 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 22:55:19.277069 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 22:55:19.283254 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
820 22:55:19.286642 0 10 8 | B1->B0 | 3333 2f2f | 0 1 | (0 0) (1 0)
821 22:55:19.290375 0 10 12 | B1->B0 | 2b2b 2525 | 0 0 | (0 0) (0 0)
822 22:55:19.297016 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 22:55:19.299842 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 22:55:19.303589 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 22:55:19.310229 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 22:55:19.313487 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 22:55:19.316576 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 22:55:19.320225 0 11 8 | B1->B0 | 2727 2c2c | 0 1 | (0 0) (0 0)
829 22:55:19.326874 0 11 12 | B1->B0 | 3a3a 4343 | 0 0 | (0 0) (0 0)
830 22:55:19.330376 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 22:55:19.333239 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 22:55:19.340155 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 22:55:19.343647 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 22:55:19.346959 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 22:55:19.353685 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
836 22:55:19.356691 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
837 22:55:19.359932 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
838 22:55:19.366828 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 22:55:19.370280 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 22:55:19.373697 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 22:55:19.380399 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 22:55:19.383664 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 22:55:19.386693 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 22:55:19.393256 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 22:55:19.397415 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 22:55:19.400015 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 22:55:19.406555 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 22:55:19.410551 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 22:55:19.413244 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 22:55:19.420143 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 22:55:19.423489 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
852 22:55:19.426872 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
853 22:55:19.430121 Total UI for P1: 0, mck2ui 16
854 22:55:19.433632 best dqsien dly found for B0: ( 0, 14, 6)
855 22:55:19.436715 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
856 22:55:19.443698 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
857 22:55:19.446511 Total UI for P1: 0, mck2ui 16
858 22:55:19.450021 best dqsien dly found for B1: ( 0, 14, 10)
859 22:55:19.453307 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
860 22:55:19.456852 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
861 22:55:19.456952
862 22:55:19.460387 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
863 22:55:19.463553 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
864 22:55:19.466839 [Gating] SW calibration Done
865 22:55:19.466936 ==
866 22:55:19.470170 Dram Type= 6, Freq= 0, CH_0, rank 0
867 22:55:19.473185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
868 22:55:19.473285 ==
869 22:55:19.476866 RX Vref Scan: 0
870 22:55:19.476964
871 22:55:19.477061 RX Vref 0 -> 0, step: 1
872 22:55:19.477151
873 22:55:19.480233 RX Delay -130 -> 252, step: 16
874 22:55:19.483313 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
875 22:55:19.490259 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
876 22:55:19.493620 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
877 22:55:19.496954 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
878 22:55:19.500185 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
879 22:55:19.503501 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
880 22:55:19.510074 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
881 22:55:19.513510 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
882 22:55:19.517044 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
883 22:55:19.520135 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
884 22:55:19.523309 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
885 22:55:19.530001 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
886 22:55:19.533776 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
887 22:55:19.536917 iDelay=222, Bit 13, Center 77 (-34 ~ 189) 224
888 22:55:19.540178 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
889 22:55:19.546646 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
890 22:55:19.546731 ==
891 22:55:19.549939 Dram Type= 6, Freq= 0, CH_0, rank 0
892 22:55:19.553589 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
893 22:55:19.553673 ==
894 22:55:19.553740 DQS Delay:
895 22:55:19.556932 DQS0 = 0, DQS1 = 0
896 22:55:19.557016 DQM Delay:
897 22:55:19.560158 DQM0 = 85, DQM1 = 77
898 22:55:19.560264 DQ Delay:
899 22:55:19.563282 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
900 22:55:19.566545 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =85
901 22:55:19.570372 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
902 22:55:19.573350 DQ12 =85, DQ13 =77, DQ14 =85, DQ15 =85
903 22:55:19.573433
904 22:55:19.573499
905 22:55:19.573559 ==
906 22:55:19.576811 Dram Type= 6, Freq= 0, CH_0, rank 0
907 22:55:19.580127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
908 22:55:19.580211 ==
909 22:55:19.580279
910 22:55:19.580339
911 22:55:19.583746 TX Vref Scan disable
912 22:55:19.586821 == TX Byte 0 ==
913 22:55:19.589887 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
914 22:55:19.593258 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
915 22:55:19.596810 == TX Byte 1 ==
916 22:55:19.599887 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
917 22:55:19.603185 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
918 22:55:19.603284 ==
919 22:55:19.606484 Dram Type= 6, Freq= 0, CH_0, rank 0
920 22:55:19.613277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
921 22:55:19.613357 ==
922 22:55:19.625223 TX Vref=22, minBit 12, minWin=26, winSum=436
923 22:55:19.628458 TX Vref=24, minBit 5, minWin=27, winSum=441
924 22:55:19.631991 TX Vref=26, minBit 8, minWin=27, winSum=446
925 22:55:19.635650 TX Vref=28, minBit 8, minWin=27, winSum=450
926 22:55:19.638817 TX Vref=30, minBit 8, minWin=27, winSum=451
927 22:55:19.641881 TX Vref=32, minBit 9, minWin=27, winSum=452
928 22:55:19.648792 [TxChooseVref] Worse bit 9, Min win 27, Win sum 452, Final Vref 32
929 22:55:19.648878
930 22:55:19.652364 Final TX Range 1 Vref 32
931 22:55:19.652464
932 22:55:19.652562 ==
933 22:55:19.655564 Dram Type= 6, Freq= 0, CH_0, rank 0
934 22:55:19.658979 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
935 22:55:19.659072 ==
936 22:55:19.659163
937 22:55:19.661816
938 22:55:19.661900 TX Vref Scan disable
939 22:55:19.665645 == TX Byte 0 ==
940 22:55:19.668684 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
941 22:55:19.672337 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
942 22:55:19.675818 == TX Byte 1 ==
943 22:55:19.678656 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
944 22:55:19.682536 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
945 22:55:19.685706
946 22:55:19.685829 [DATLAT]
947 22:55:19.685932 Freq=800, CH0 RK0
948 22:55:19.686029
949 22:55:19.689157 DATLAT Default: 0xa
950 22:55:19.689260 0, 0xFFFF, sum = 0
951 22:55:19.692309 1, 0xFFFF, sum = 0
952 22:55:19.692393 2, 0xFFFF, sum = 0
953 22:55:19.695623 3, 0xFFFF, sum = 0
954 22:55:19.695730 4, 0xFFFF, sum = 0
955 22:55:19.698834 5, 0xFFFF, sum = 0
956 22:55:19.698933 6, 0xFFFF, sum = 0
957 22:55:19.702245 7, 0xFFFF, sum = 0
958 22:55:19.705348 8, 0xFFFF, sum = 0
959 22:55:19.705447 9, 0x0, sum = 1
960 22:55:19.705539 10, 0x0, sum = 2
961 22:55:19.708812 11, 0x0, sum = 3
962 22:55:19.708883 12, 0x0, sum = 4
963 22:55:19.712249 best_step = 10
964 22:55:19.712320
965 22:55:19.712386 ==
966 22:55:19.715373 Dram Type= 6, Freq= 0, CH_0, rank 0
967 22:55:19.719095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
968 22:55:19.719200 ==
969 22:55:19.722423 RX Vref Scan: 1
970 22:55:19.722520
971 22:55:19.722616 Set Vref Range= 32 -> 127
972 22:55:19.722704
973 22:55:19.725230 RX Vref 32 -> 127, step: 1
974 22:55:19.725316
975 22:55:19.728657 RX Delay -95 -> 252, step: 8
976 22:55:19.728739
977 22:55:19.732089 Set Vref, RX VrefLevel [Byte0]: 32
978 22:55:19.735482 [Byte1]: 32
979 22:55:19.735565
980 22:55:19.739302 Set Vref, RX VrefLevel [Byte0]: 33
981 22:55:19.742589 [Byte1]: 33
982 22:55:19.745934
983 22:55:19.746016 Set Vref, RX VrefLevel [Byte0]: 34
984 22:55:19.749070 [Byte1]: 34
985 22:55:19.753110
986 22:55:19.753193 Set Vref, RX VrefLevel [Byte0]: 35
987 22:55:19.756680 [Byte1]: 35
988 22:55:19.760704
989 22:55:19.760789 Set Vref, RX VrefLevel [Byte0]: 36
990 22:55:19.764415 [Byte1]: 36
991 22:55:19.769079
992 22:55:19.769179 Set Vref, RX VrefLevel [Byte0]: 37
993 22:55:19.772558 [Byte1]: 37
994 22:55:19.776394
995 22:55:19.776476 Set Vref, RX VrefLevel [Byte0]: 38
996 22:55:19.779707 [Byte1]: 38
997 22:55:19.783496
998 22:55:19.783578 Set Vref, RX VrefLevel [Byte0]: 39
999 22:55:19.787168 [Byte1]: 39
1000 22:55:19.791741
1001 22:55:19.791826 Set Vref, RX VrefLevel [Byte0]: 40
1002 22:55:19.794978 [Byte1]: 40
1003 22:55:19.799034
1004 22:55:19.799120 Set Vref, RX VrefLevel [Byte0]: 41
1005 22:55:19.802304 [Byte1]: 41
1006 22:55:19.806289
1007 22:55:19.806375 Set Vref, RX VrefLevel [Byte0]: 42
1008 22:55:19.809535 [Byte1]: 42
1009 22:55:19.814142
1010 22:55:19.814227 Set Vref, RX VrefLevel [Byte0]: 43
1011 22:55:19.817777 [Byte1]: 43
1012 22:55:19.822050
1013 22:55:19.822131 Set Vref, RX VrefLevel [Byte0]: 44
1014 22:55:19.824932 [Byte1]: 44
1015 22:55:19.829067
1016 22:55:19.829146 Set Vref, RX VrefLevel [Byte0]: 45
1017 22:55:19.832475 [Byte1]: 45
1018 22:55:19.836691
1019 22:55:19.836767 Set Vref, RX VrefLevel [Byte0]: 46
1020 22:55:19.840305 [Byte1]: 46
1021 22:55:19.844625
1022 22:55:19.844709 Set Vref, RX VrefLevel [Byte0]: 47
1023 22:55:19.847879 [Byte1]: 47
1024 22:55:19.852183
1025 22:55:19.852271 Set Vref, RX VrefLevel [Byte0]: 48
1026 22:55:19.855662 [Byte1]: 48
1027 22:55:19.859538
1028 22:55:19.859613 Set Vref, RX VrefLevel [Byte0]: 49
1029 22:55:19.862812 [Byte1]: 49
1030 22:55:19.866835
1031 22:55:19.870526 Set Vref, RX VrefLevel [Byte0]: 50
1032 22:55:19.870609 [Byte1]: 50
1033 22:55:19.875055
1034 22:55:19.875129 Set Vref, RX VrefLevel [Byte0]: 51
1035 22:55:19.878056 [Byte1]: 51
1036 22:55:19.882226
1037 22:55:19.882301 Set Vref, RX VrefLevel [Byte0]: 52
1038 22:55:19.885789 [Byte1]: 52
1039 22:55:19.889833
1040 22:55:19.889907 Set Vref, RX VrefLevel [Byte0]: 53
1041 22:55:19.893247 [Byte1]: 53
1042 22:55:19.898119
1043 22:55:19.898195 Set Vref, RX VrefLevel [Byte0]: 54
1044 22:55:19.901229 [Byte1]: 54
1045 22:55:19.905534
1046 22:55:19.905609 Set Vref, RX VrefLevel [Byte0]: 55
1047 22:55:19.908647 [Byte1]: 55
1048 22:55:19.913060
1049 22:55:19.913138 Set Vref, RX VrefLevel [Byte0]: 56
1050 22:55:19.916228 [Byte1]: 56
1051 22:55:19.920584
1052 22:55:19.920693 Set Vref, RX VrefLevel [Byte0]: 57
1053 22:55:19.923633 [Byte1]: 57
1054 22:55:19.927811
1055 22:55:19.927894 Set Vref, RX VrefLevel [Byte0]: 58
1056 22:55:19.930958 [Byte1]: 58
1057 22:55:19.935580
1058 22:55:19.935662 Set Vref, RX VrefLevel [Byte0]: 59
1059 22:55:19.939270 [Byte1]: 59
1060 22:55:19.943012
1061 22:55:19.943094 Set Vref, RX VrefLevel [Byte0]: 60
1062 22:55:19.946210 [Byte1]: 60
1063 22:55:19.950892
1064 22:55:19.950974 Set Vref, RX VrefLevel [Byte0]: 61
1065 22:55:19.954256 [Byte1]: 61
1066 22:55:19.958552
1067 22:55:19.958635 Set Vref, RX VrefLevel [Byte0]: 62
1068 22:55:19.961507 [Byte1]: 62
1069 22:55:19.965787
1070 22:55:19.965869 Set Vref, RX VrefLevel [Byte0]: 63
1071 22:55:19.969207 [Byte1]: 63
1072 22:55:19.973737
1073 22:55:19.973819 Set Vref, RX VrefLevel [Byte0]: 64
1074 22:55:19.977513 [Byte1]: 64
1075 22:55:19.980980
1076 22:55:19.981062 Set Vref, RX VrefLevel [Byte0]: 65
1077 22:55:19.984209 [Byte1]: 65
1078 22:55:19.989030
1079 22:55:19.989113 Set Vref, RX VrefLevel [Byte0]: 66
1080 22:55:19.992305 [Byte1]: 66
1081 22:55:19.996093
1082 22:55:19.996191 Set Vref, RX VrefLevel [Byte0]: 67
1083 22:55:20.002608 [Byte1]: 67
1084 22:55:20.002706
1085 22:55:20.006158 Set Vref, RX VrefLevel [Byte0]: 68
1086 22:55:20.009630 [Byte1]: 68
1087 22:55:20.009713
1088 22:55:20.012797 Set Vref, RX VrefLevel [Byte0]: 69
1089 22:55:20.015946 [Byte1]: 69
1090 22:55:20.016029
1091 22:55:20.019941 Set Vref, RX VrefLevel [Byte0]: 70
1092 22:55:20.022464 [Byte1]: 70
1093 22:55:20.026539
1094 22:55:20.026621 Set Vref, RX VrefLevel [Byte0]: 71
1095 22:55:20.029948 [Byte1]: 71
1096 22:55:20.034367
1097 22:55:20.034448 Set Vref, RX VrefLevel [Byte0]: 72
1098 22:55:20.037871 [Byte1]: 72
1099 22:55:20.041860
1100 22:55:20.041942 Set Vref, RX VrefLevel [Byte0]: 73
1101 22:55:20.045253 [Byte1]: 73
1102 22:55:20.049536
1103 22:55:20.049618 Set Vref, RX VrefLevel [Byte0]: 74
1104 22:55:20.052753 [Byte1]: 74
1105 22:55:20.057176
1106 22:55:20.057258 Set Vref, RX VrefLevel [Byte0]: 75
1107 22:55:20.060427 [Byte1]: 75
1108 22:55:20.064976
1109 22:55:20.065058 Set Vref, RX VrefLevel [Byte0]: 76
1110 22:55:20.067768 [Byte1]: 76
1111 22:55:20.071973
1112 22:55:20.072048 Final RX Vref Byte 0 = 60 to rank0
1113 22:55:20.075390 Final RX Vref Byte 1 = 56 to rank0
1114 22:55:20.078859 Final RX Vref Byte 0 = 60 to rank1
1115 22:55:20.082226 Final RX Vref Byte 1 = 56 to rank1==
1116 22:55:20.085693 Dram Type= 6, Freq= 0, CH_0, rank 0
1117 22:55:20.092800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1118 22:55:20.092883 ==
1119 22:55:20.092949 DQS Delay:
1120 22:55:20.093010 DQS0 = 0, DQS1 = 0
1121 22:55:20.095647 DQM Delay:
1122 22:55:20.095729 DQM0 = 87, DQM1 = 79
1123 22:55:20.098717 DQ Delay:
1124 22:55:20.101995 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1125 22:55:20.105359 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96
1126 22:55:20.105442 DQ8 =68, DQ9 =64, DQ10 =80, DQ11 =76
1127 22:55:20.112729 DQ12 =84, DQ13 =84, DQ14 =92, DQ15 =88
1128 22:55:20.112811
1129 22:55:20.112877
1130 22:55:20.119369 [DQSOSCAuto] RK0, (LSB)MR18= 0x2a10, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 399 ps
1131 22:55:20.122065 CH0 RK0: MR19=606, MR18=2A10
1132 22:55:20.129164 CH0_RK0: MR19=0x606, MR18=0x2A10, DQSOSC=399, MR23=63, INC=92, DEC=61
1133 22:55:20.129248
1134 22:55:20.132114 ----->DramcWriteLeveling(PI) begin...
1135 22:55:20.132198 ==
1136 22:55:20.135700 Dram Type= 6, Freq= 0, CH_0, rank 1
1137 22:55:20.139012 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1138 22:55:20.139094 ==
1139 22:55:20.142174 Write leveling (Byte 0): 31 => 31
1140 22:55:20.145395 Write leveling (Byte 1): 28 => 28
1141 22:55:20.148827 DramcWriteLeveling(PI) end<-----
1142 22:55:20.148909
1143 22:55:20.148973 ==
1144 22:55:20.152071 Dram Type= 6, Freq= 0, CH_0, rank 1
1145 22:55:20.155809 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1146 22:55:20.155901 ==
1147 22:55:20.159098 [Gating] SW mode calibration
1148 22:55:20.165978 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1149 22:55:20.172120 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1150 22:55:20.175223 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1151 22:55:20.179115 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1152 22:55:20.223060 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1153 22:55:20.223328 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1154 22:55:20.223854 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 22:55:20.224419 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 22:55:20.224526 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 22:55:20.225115 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 22:55:20.225382 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 22:55:20.225457 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 22:55:20.225531 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 22:55:20.225608 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 22:55:20.267099 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 22:55:20.267412 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 22:55:20.267526 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 22:55:20.268224 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 22:55:20.268297 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1167 22:55:20.268607 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1168 22:55:20.269188 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1169 22:55:20.269901 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 22:55:20.270161 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 22:55:20.270230 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 22:55:20.292963 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 22:55:20.293283 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 22:55:20.293364 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 22:55:20.294032 0 9 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
1176 22:55:20.294114 0 9 8 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
1177 22:55:20.296865 0 9 12 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
1178 22:55:20.300130 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1179 22:55:20.303608 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1180 22:55:20.306621 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 22:55:20.313237 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1182 22:55:20.316617 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1183 22:55:20.320567 0 10 4 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (1 1)
1184 22:55:20.323619 0 10 8 | B1->B0 | 3232 2424 | 1 0 | (1 0) (0 0)
1185 22:55:20.329865 0 10 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1186 22:55:20.333278 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 22:55:20.336583 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 22:55:20.343584 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 22:55:20.347219 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 22:55:20.350651 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 22:55:20.355117 0 11 4 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (1 1)
1192 22:55:20.361593 0 11 8 | B1->B0 | 3131 4444 | 0 1 | (0 0) (0 0)
1193 22:55:20.364881 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1194 22:55:20.368265 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1195 22:55:20.371937 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1196 22:55:20.379156 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 22:55:20.382659 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 22:55:20.386048 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 22:55:20.392447 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1200 22:55:20.395931 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1201 22:55:20.398885 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1202 22:55:20.405585 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 22:55:20.409463 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 22:55:20.412167 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 22:55:20.416177 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 22:55:20.422329 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 22:55:20.425462 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 22:55:20.428832 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 22:55:20.435650 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 22:55:20.438886 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 22:55:20.442735 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 22:55:20.449253 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 22:55:20.452390 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 22:55:20.455786 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 22:55:20.462128 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1216 22:55:20.465829 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1217 22:55:20.469224 Total UI for P1: 0, mck2ui 16
1218 22:55:20.472185 best dqsien dly found for B0: ( 0, 14, 4)
1219 22:55:20.475787 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1220 22:55:20.478963 Total UI for P1: 0, mck2ui 16
1221 22:55:20.482072 best dqsien dly found for B1: ( 0, 14, 8)
1222 22:55:20.485948 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1223 22:55:20.489628 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1224 22:55:20.489709
1225 22:55:20.492453 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1226 22:55:20.499182 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1227 22:55:20.499265 [Gating] SW calibration Done
1228 22:55:20.499329 ==
1229 22:55:20.502235 Dram Type= 6, Freq= 0, CH_0, rank 1
1230 22:55:20.509398 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1231 22:55:20.509480 ==
1232 22:55:20.509544 RX Vref Scan: 0
1233 22:55:20.509604
1234 22:55:20.512495 RX Vref 0 -> 0, step: 1
1235 22:55:20.512576
1236 22:55:20.515893 RX Delay -130 -> 252, step: 16
1237 22:55:20.518997 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1238 22:55:20.522321 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1239 22:55:20.525808 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1240 22:55:20.532606 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1241 22:55:20.535713 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1242 22:55:20.539066 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
1243 22:55:20.542332 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1244 22:55:20.545703 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1245 22:55:20.548996 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1246 22:55:20.555792 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1247 22:55:20.558769 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1248 22:55:20.562515 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1249 22:55:20.565802 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1250 22:55:20.572165 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1251 22:55:20.575742 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1252 22:55:20.579114 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1253 22:55:20.579221 ==
1254 22:55:20.582394 Dram Type= 6, Freq= 0, CH_0, rank 1
1255 22:55:20.585825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1256 22:55:20.585908 ==
1257 22:55:20.589019 DQS Delay:
1258 22:55:20.589101 DQS0 = 0, DQS1 = 0
1259 22:55:20.592693 DQM Delay:
1260 22:55:20.592775 DQM0 = 85, DQM1 = 78
1261 22:55:20.592839 DQ Delay:
1262 22:55:20.595341 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
1263 22:55:20.598954 DQ4 =85, DQ5 =77, DQ6 =93, DQ7 =85
1264 22:55:20.602224 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =77
1265 22:55:20.605623 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
1266 22:55:20.605705
1267 22:55:20.605769
1268 22:55:20.605827 ==
1269 22:55:20.609019 Dram Type= 6, Freq= 0, CH_0, rank 1
1270 22:55:20.615716 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1271 22:55:20.615798 ==
1272 22:55:20.615863
1273 22:55:20.615923
1274 22:55:20.615980 TX Vref Scan disable
1275 22:55:20.619634 == TX Byte 0 ==
1276 22:55:20.622604 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1277 22:55:20.629408 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1278 22:55:20.629490 == TX Byte 1 ==
1279 22:55:20.632827 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1280 22:55:20.639540 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1281 22:55:20.639621 ==
1282 22:55:20.642705 Dram Type= 6, Freq= 0, CH_0, rank 1
1283 22:55:20.646029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1284 22:55:20.646111 ==
1285 22:55:20.659119 TX Vref=22, minBit 3, minWin=27, winSum=445
1286 22:55:20.662057 TX Vref=24, minBit 3, minWin=27, winSum=446
1287 22:55:20.665603 TX Vref=26, minBit 8, minWin=27, winSum=451
1288 22:55:20.668863 TX Vref=28, minBit 3, minWin=27, winSum=450
1289 22:55:20.672131 TX Vref=30, minBit 4, minWin=28, winSum=457
1290 22:55:20.679143 TX Vref=32, minBit 12, minWin=27, winSum=456
1291 22:55:20.682321 [TxChooseVref] Worse bit 4, Min win 28, Win sum 457, Final Vref 30
1292 22:55:20.682404
1293 22:55:20.685306 Final TX Range 1 Vref 30
1294 22:55:20.685386
1295 22:55:20.685448 ==
1296 22:55:20.688884 Dram Type= 6, Freq= 0, CH_0, rank 1
1297 22:55:20.692066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1298 22:55:20.692146 ==
1299 22:55:20.695344
1300 22:55:20.695460
1301 22:55:20.695522 TX Vref Scan disable
1302 22:55:20.699175 == TX Byte 0 ==
1303 22:55:20.702235 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1304 22:55:20.705719 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1305 22:55:20.709019 == TX Byte 1 ==
1306 22:55:20.712296 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1307 22:55:20.715394 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1308 22:55:20.718859
1309 22:55:20.718938 [DATLAT]
1310 22:55:20.718999 Freq=800, CH0 RK1
1311 22:55:20.719057
1312 22:55:20.722059 DATLAT Default: 0xa
1313 22:55:20.722138 0, 0xFFFF, sum = 0
1314 22:55:20.725475 1, 0xFFFF, sum = 0
1315 22:55:20.725556 2, 0xFFFF, sum = 0
1316 22:55:20.729159 3, 0xFFFF, sum = 0
1317 22:55:20.732132 4, 0xFFFF, sum = 0
1318 22:55:20.732213 5, 0xFFFF, sum = 0
1319 22:55:20.735483 6, 0xFFFF, sum = 0
1320 22:55:20.735564 7, 0xFFFF, sum = 0
1321 22:55:20.739110 8, 0xFFFF, sum = 0
1322 22:55:20.739191 9, 0x0, sum = 1
1323 22:55:20.739255 10, 0x0, sum = 2
1324 22:55:20.741807 11, 0x0, sum = 3
1325 22:55:20.741888 12, 0x0, sum = 4
1326 22:55:20.745745 best_step = 10
1327 22:55:20.745824
1328 22:55:20.745886 ==
1329 22:55:20.748983 Dram Type= 6, Freq= 0, CH_0, rank 1
1330 22:55:20.752452 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1331 22:55:20.752532 ==
1332 22:55:20.755125 RX Vref Scan: 0
1333 22:55:20.755204
1334 22:55:20.755266 RX Vref 0 -> 0, step: 1
1335 22:55:20.755325
1336 22:55:20.758725 RX Delay -95 -> 252, step: 8
1337 22:55:20.765517 iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232
1338 22:55:20.768930 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1339 22:55:20.771961 iDelay=209, Bit 2, Center 84 (-31 ~ 200) 232
1340 22:55:20.775779 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1341 22:55:20.779119 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1342 22:55:20.785942 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1343 22:55:20.789090 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1344 22:55:20.792211 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1345 22:55:20.795464 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1346 22:55:20.798603 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1347 22:55:20.805922 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1348 22:55:20.808799 iDelay=209, Bit 11, Center 68 (-39 ~ 176) 216
1349 22:55:20.812251 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1350 22:55:20.815597 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1351 22:55:20.818960 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1352 22:55:20.825536 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1353 22:55:20.825617 ==
1354 22:55:20.828786 Dram Type= 6, Freq= 0, CH_0, rank 1
1355 22:55:20.831959 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1356 22:55:20.832039 ==
1357 22:55:20.832102 DQS Delay:
1358 22:55:20.835295 DQS0 = 0, DQS1 = 0
1359 22:55:20.835426 DQM Delay:
1360 22:55:20.838892 DQM0 = 87, DQM1 = 77
1361 22:55:20.838971 DQ Delay:
1362 22:55:20.842215 DQ0 =84, DQ1 =88, DQ2 =84, DQ3 =84
1363 22:55:20.846040 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1364 22:55:20.849111 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1365 22:55:20.852406 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =88
1366 22:55:20.852485
1367 22:55:20.852547
1368 22:55:20.861932 [DQSOSCAuto] RK1, (LSB)MR18= 0x311a, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 397 ps
1369 22:55:20.862013 CH0 RK1: MR19=606, MR18=311A
1370 22:55:20.869199 CH0_RK1: MR19=0x606, MR18=0x311A, DQSOSC=397, MR23=63, INC=93, DEC=62
1371 22:55:20.872143 [RxdqsGatingPostProcess] freq 800
1372 22:55:20.878571 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1373 22:55:20.882174 Pre-setting of DQS Precalculation
1374 22:55:20.885270 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1375 22:55:20.885351 ==
1376 22:55:20.888861 Dram Type= 6, Freq= 0, CH_1, rank 0
1377 22:55:20.892323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1378 22:55:20.895329 ==
1379 22:55:20.898531 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1380 22:55:20.905090 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1381 22:55:20.913621 [CA 0] Center 36 (6~67) winsize 62
1382 22:55:20.917063 [CA 1] Center 36 (5~67) winsize 63
1383 22:55:20.920466 [CA 2] Center 34 (4~64) winsize 61
1384 22:55:20.924104 [CA 3] Center 33 (3~64) winsize 62
1385 22:55:20.927396 [CA 4] Center 34 (3~65) winsize 63
1386 22:55:20.930198 [CA 5] Center 33 (3~64) winsize 62
1387 22:55:20.930280
1388 22:55:20.933901 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1389 22:55:20.933983
1390 22:55:20.937266 [CATrainingPosCal] consider 1 rank data
1391 22:55:20.940895 u2DelayCellTimex100 = 270/100 ps
1392 22:55:20.944028 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1393 22:55:20.947024 CA1 delay=36 (5~67),Diff = 3 PI (21 cell)
1394 22:55:20.953548 CA2 delay=34 (4~64),Diff = 1 PI (7 cell)
1395 22:55:20.957335 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1396 22:55:20.960242 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
1397 22:55:20.963613 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1398 22:55:20.963695
1399 22:55:20.967318 CA PerBit enable=1, Macro0, CA PI delay=33
1400 22:55:20.967448
1401 22:55:20.970728 [CBTSetCACLKResult] CA Dly = 33
1402 22:55:20.970810 CS Dly: 4 (0~35)
1403 22:55:20.973799 ==
1404 22:55:20.973882 Dram Type= 6, Freq= 0, CH_1, rank 1
1405 22:55:20.980085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1406 22:55:20.980169 ==
1407 22:55:20.983942 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1408 22:55:20.990188 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1409 22:55:20.999807 [CA 0] Center 36 (5~67) winsize 63
1410 22:55:21.003360 [CA 1] Center 36 (5~67) winsize 63
1411 22:55:21.006633 [CA 2] Center 33 (3~64) winsize 62
1412 22:55:21.009598 [CA 3] Center 33 (3~64) winsize 62
1413 22:55:21.013196 [CA 4] Center 34 (3~65) winsize 63
1414 22:55:21.016599 [CA 5] Center 33 (3~64) winsize 62
1415 22:55:21.016682
1416 22:55:21.021084 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1417 22:55:21.021167
1418 22:55:21.024071 [CATrainingPosCal] consider 2 rank data
1419 22:55:21.027753 u2DelayCellTimex100 = 270/100 ps
1420 22:55:21.031863 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1421 22:55:21.035002 CA1 delay=36 (5~67),Diff = 3 PI (21 cell)
1422 22:55:21.038967 CA2 delay=34 (4~64),Diff = 1 PI (7 cell)
1423 22:55:21.042849 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1424 22:55:21.046030 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
1425 22:55:21.049862 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1426 22:55:21.049945
1427 22:55:21.053292 CA PerBit enable=1, Macro0, CA PI delay=33
1428 22:55:21.053374
1429 22:55:21.056655 [CBTSetCACLKResult] CA Dly = 33
1430 22:55:21.056738 CS Dly: 5 (0~37)
1431 22:55:21.056803
1432 22:55:21.060067 ----->DramcWriteLeveling(PI) begin...
1433 22:55:21.060151 ==
1434 22:55:21.063290 Dram Type= 6, Freq= 0, CH_1, rank 0
1435 22:55:21.070179 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1436 22:55:21.070262 ==
1437 22:55:21.073390 Write leveling (Byte 0): 25 => 25
1438 22:55:21.076909 Write leveling (Byte 1): 31 => 31
1439 22:55:21.076992 DramcWriteLeveling(PI) end<-----
1440 22:55:21.080186
1441 22:55:21.080268 ==
1442 22:55:21.083501 Dram Type= 6, Freq= 0, CH_1, rank 0
1443 22:55:21.086479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1444 22:55:21.086562 ==
1445 22:55:21.089914 [Gating] SW mode calibration
1446 22:55:21.096977 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1447 22:55:21.100218 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1448 22:55:21.107126 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1449 22:55:21.110070 0 6 4 | B1->B0 | 2424 2323 | 0 0 | (1 1) (1 1)
1450 22:55:21.113391 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1451 22:55:21.119738 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 22:55:21.123582 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 22:55:21.126951 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 22:55:21.133317 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 22:55:21.136926 0 6 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1456 22:55:21.140204 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 22:55:21.146840 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 22:55:21.150056 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 22:55:21.153365 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 22:55:21.156765 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 22:55:21.163154 0 7 20 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1462 22:55:21.166789 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 22:55:21.169731 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 22:55:21.176457 0 8 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1465 22:55:21.180241 0 8 4 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1466 22:55:21.183207 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1467 22:55:21.189834 0 8 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1468 22:55:21.193212 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 22:55:21.196849 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 22:55:21.203256 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 22:55:21.206850 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 22:55:21.210283 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 22:55:21.216501 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
1474 22:55:21.220331 0 9 8 | B1->B0 | 2929 2d2d | 0 0 | (0 0) (0 0)
1475 22:55:21.223247 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1476 22:55:21.229892 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1477 22:55:21.233431 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1478 22:55:21.236719 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1479 22:55:21.243513 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1480 22:55:21.246710 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1481 22:55:21.250175 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1482 22:55:21.253344 0 10 8 | B1->B0 | 2d2d 2f2f | 0 0 | (1 0) (1 1)
1483 22:55:21.259999 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1484 22:55:21.263822 0 10 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1485 22:55:21.266823 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 22:55:21.273391 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 22:55:21.276337 0 10 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1488 22:55:21.279626 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 22:55:21.286648 0 11 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1490 22:55:21.290099 0 11 8 | B1->B0 | 3a3a 3838 | 0 0 | (1 1) (0 0)
1491 22:55:21.293223 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1492 22:55:21.300259 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1493 22:55:21.303619 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1494 22:55:21.306620 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 22:55:21.313542 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 22:55:21.316904 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 22:55:21.320222 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 22:55:21.327280 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1499 22:55:21.330147 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 22:55:21.333733 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 22:55:21.339750 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 22:55:21.343304 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 22:55:21.346434 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 22:55:21.353517 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 22:55:21.356313 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 22:55:21.359733 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 22:55:21.366360 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 22:55:21.369834 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 22:55:21.373134 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 22:55:21.376168 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 22:55:21.383853 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 22:55:21.386679 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 22:55:21.390185 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1514 22:55:21.396600 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1515 22:55:21.399877 Total UI for P1: 0, mck2ui 16
1516 22:55:21.403357 best dqsien dly found for B0: ( 0, 14, 6)
1517 22:55:21.403460 Total UI for P1: 0, mck2ui 16
1518 22:55:21.409933 best dqsien dly found for B1: ( 0, 14, 4)
1519 22:55:21.413147 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1520 22:55:21.416474 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1521 22:55:21.416557
1522 22:55:21.419911 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1523 22:55:21.422900 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1524 22:55:21.426672 [Gating] SW calibration Done
1525 22:55:21.426754 ==
1526 22:55:21.429467 Dram Type= 6, Freq= 0, CH_1, rank 0
1527 22:55:21.432974 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1528 22:55:21.433057 ==
1529 22:55:21.436297 RX Vref Scan: 0
1530 22:55:21.436379
1531 22:55:21.436444 RX Vref 0 -> 0, step: 1
1532 22:55:21.436505
1533 22:55:21.439922 RX Delay -130 -> 252, step: 16
1534 22:55:21.443163 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1535 22:55:21.449814 iDelay=206, Bit 1, Center 77 (-34 ~ 189) 224
1536 22:55:21.453299 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1537 22:55:21.456761 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1538 22:55:21.459574 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1539 22:55:21.463270 iDelay=206, Bit 5, Center 85 (-34 ~ 205) 240
1540 22:55:21.469924 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1541 22:55:21.473032 iDelay=206, Bit 7, Center 77 (-34 ~ 189) 224
1542 22:55:21.476488 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1543 22:55:21.479900 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1544 22:55:21.483600 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1545 22:55:21.489702 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1546 22:55:21.492885 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1547 22:55:21.496389 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1548 22:55:21.499775 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1549 22:55:21.502856 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1550 22:55:21.506838 ==
1551 22:55:21.509861 Dram Type= 6, Freq= 0, CH_1, rank 0
1552 22:55:21.513542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1553 22:55:21.513625 ==
1554 22:55:21.513690 DQS Delay:
1555 22:55:21.516543 DQS0 = 0, DQS1 = 0
1556 22:55:21.516625 DQM Delay:
1557 22:55:21.519950 DQM0 = 82, DQM1 = 77
1558 22:55:21.520033 DQ Delay:
1559 22:55:21.522848 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =85
1560 22:55:21.526262 DQ4 =85, DQ5 =85, DQ6 =93, DQ7 =77
1561 22:55:21.529497 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =69
1562 22:55:21.532974 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1563 22:55:21.533056
1564 22:55:21.533121
1565 22:55:21.533181 ==
1566 22:55:21.536272 Dram Type= 6, Freq= 0, CH_1, rank 0
1567 22:55:21.539586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1568 22:55:21.539669 ==
1569 22:55:21.539734
1570 22:55:21.539794
1571 22:55:21.542986 TX Vref Scan disable
1572 22:55:21.546829 == TX Byte 0 ==
1573 22:55:21.549817 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1574 22:55:21.553586 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1575 22:55:21.556076 == TX Byte 1 ==
1576 22:55:21.559790 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1577 22:55:21.563174 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1578 22:55:21.563257 ==
1579 22:55:21.566260 Dram Type= 6, Freq= 0, CH_1, rank 0
1580 22:55:21.569566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1581 22:55:21.572917 ==
1582 22:55:21.584749 TX Vref=22, minBit 8, minWin=26, winSum=433
1583 22:55:21.588023 TX Vref=24, minBit 8, minWin=26, winSum=434
1584 22:55:21.591648 TX Vref=26, minBit 5, minWin=27, winSum=442
1585 22:55:21.594986 TX Vref=28, minBit 0, minWin=27, winSum=448
1586 22:55:21.598256 TX Vref=30, minBit 13, minWin=27, winSum=453
1587 22:55:21.602275 TX Vref=32, minBit 0, minWin=28, winSum=453
1588 22:55:21.608767 [TxChooseVref] Worse bit 0, Min win 28, Win sum 453, Final Vref 32
1589 22:55:21.608851
1590 22:55:21.611931 Final TX Range 1 Vref 32
1591 22:55:21.612014
1592 22:55:21.612079 ==
1593 22:55:21.615497 Dram Type= 6, Freq= 0, CH_1, rank 0
1594 22:55:21.618701 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1595 22:55:21.618784 ==
1596 22:55:21.618849
1597 22:55:21.618909
1598 22:55:21.622115 TX Vref Scan disable
1599 22:55:21.625261 == TX Byte 0 ==
1600 22:55:21.628492 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1601 22:55:21.632041 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1602 22:55:21.635329 == TX Byte 1 ==
1603 22:55:21.638896 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1604 22:55:21.642050 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1605 22:55:21.642132
1606 22:55:21.645249 [DATLAT]
1607 22:55:21.645331 Freq=800, CH1 RK0
1608 22:55:21.645396
1609 22:55:21.648683 DATLAT Default: 0xa
1610 22:55:21.648765 0, 0xFFFF, sum = 0
1611 22:55:21.652027 1, 0xFFFF, sum = 0
1612 22:55:21.652110 2, 0xFFFF, sum = 0
1613 22:55:21.655824 3, 0xFFFF, sum = 0
1614 22:55:21.655908 4, 0xFFFF, sum = 0
1615 22:55:21.658668 5, 0xFFFF, sum = 0
1616 22:55:21.658799 6, 0xFFFF, sum = 0
1617 22:55:21.662270 7, 0xFFFF, sum = 0
1618 22:55:21.662385 8, 0xFFFF, sum = 0
1619 22:55:21.665676 9, 0x0, sum = 1
1620 22:55:21.665759 10, 0x0, sum = 2
1621 22:55:21.668618 11, 0x0, sum = 3
1622 22:55:21.668701 12, 0x0, sum = 4
1623 22:55:21.671866 best_step = 10
1624 22:55:21.671947
1625 22:55:21.672012 ==
1626 22:55:21.675323 Dram Type= 6, Freq= 0, CH_1, rank 0
1627 22:55:21.678654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1628 22:55:21.678738 ==
1629 22:55:21.681724 RX Vref Scan: 1
1630 22:55:21.681839
1631 22:55:21.681921 Set Vref Range= 32 -> 127
1632 22:55:21.681984
1633 22:55:21.685147 RX Vref 32 -> 127, step: 1
1634 22:55:21.685230
1635 22:55:21.688713 RX Delay -95 -> 252, step: 8
1636 22:55:21.688795
1637 22:55:21.692174 Set Vref, RX VrefLevel [Byte0]: 32
1638 22:55:21.695352 [Byte1]: 32
1639 22:55:21.695448
1640 22:55:21.698568 Set Vref, RX VrefLevel [Byte0]: 33
1641 22:55:21.702175 [Byte1]: 33
1642 22:55:21.702257
1643 22:55:21.705194 Set Vref, RX VrefLevel [Byte0]: 34
1644 22:55:21.708474 [Byte1]: 34
1645 22:55:21.712721
1646 22:55:21.712804 Set Vref, RX VrefLevel [Byte0]: 35
1647 22:55:21.716297 [Byte1]: 35
1648 22:55:21.720339
1649 22:55:21.720421 Set Vref, RX VrefLevel [Byte0]: 36
1650 22:55:21.723698 [Byte1]: 36
1651 22:55:21.727917
1652 22:55:21.727999 Set Vref, RX VrefLevel [Byte0]: 37
1653 22:55:21.731145 [Byte1]: 37
1654 22:55:21.735949
1655 22:55:21.736031 Set Vref, RX VrefLevel [Byte0]: 38
1656 22:55:21.738881 [Byte1]: 38
1657 22:55:21.742921
1658 22:55:21.743003 Set Vref, RX VrefLevel [Byte0]: 39
1659 22:55:21.746771 [Byte1]: 39
1660 22:55:21.750769
1661 22:55:21.750850 Set Vref, RX VrefLevel [Byte0]: 40
1662 22:55:21.754127 [Byte1]: 40
1663 22:55:21.758216
1664 22:55:21.758302 Set Vref, RX VrefLevel [Byte0]: 41
1665 22:55:21.761930 [Byte1]: 41
1666 22:55:21.766061
1667 22:55:21.766143 Set Vref, RX VrefLevel [Byte0]: 42
1668 22:55:21.769148 [Byte1]: 42
1669 22:55:21.773422
1670 22:55:21.773505 Set Vref, RX VrefLevel [Byte0]: 43
1671 22:55:21.776684 [Byte1]: 43
1672 22:55:21.781178
1673 22:55:21.781260 Set Vref, RX VrefLevel [Byte0]: 44
1674 22:55:21.784549 [Byte1]: 44
1675 22:55:21.788588
1676 22:55:21.788697 Set Vref, RX VrefLevel [Byte0]: 45
1677 22:55:21.791862 [Byte1]: 45
1678 22:55:21.796646
1679 22:55:21.796727 Set Vref, RX VrefLevel [Byte0]: 46
1680 22:55:21.799388 [Byte1]: 46
1681 22:55:21.803909
1682 22:55:21.803993 Set Vref, RX VrefLevel [Byte0]: 47
1683 22:55:21.807602 [Byte1]: 47
1684 22:55:21.811453
1685 22:55:21.811535 Set Vref, RX VrefLevel [Byte0]: 48
1686 22:55:21.814566 [Byte1]: 48
1687 22:55:21.818859
1688 22:55:21.818941 Set Vref, RX VrefLevel [Byte0]: 49
1689 22:55:21.825618 [Byte1]: 49
1690 22:55:21.825700
1691 22:55:21.829018 Set Vref, RX VrefLevel [Byte0]: 50
1692 22:55:21.832323 [Byte1]: 50
1693 22:55:21.832405
1694 22:55:21.835318 Set Vref, RX VrefLevel [Byte0]: 51
1695 22:55:21.838780 [Byte1]: 51
1696 22:55:21.838886
1697 22:55:21.842287 Set Vref, RX VrefLevel [Byte0]: 52
1698 22:55:21.845771 [Byte1]: 52
1699 22:55:21.849633
1700 22:55:21.849715 Set Vref, RX VrefLevel [Byte0]: 53
1701 22:55:21.852904 [Byte1]: 53
1702 22:55:21.857589
1703 22:55:21.857671 Set Vref, RX VrefLevel [Byte0]: 54
1704 22:55:21.860219 [Byte1]: 54
1705 22:55:21.864440
1706 22:55:21.864536 Set Vref, RX VrefLevel [Byte0]: 55
1707 22:55:21.867717 [Byte1]: 55
1708 22:55:21.872247
1709 22:55:21.872329 Set Vref, RX VrefLevel [Byte0]: 56
1710 22:55:21.875364 [Byte1]: 56
1711 22:55:21.879993
1712 22:55:21.880099 Set Vref, RX VrefLevel [Byte0]: 57
1713 22:55:21.883076 [Byte1]: 57
1714 22:55:21.887181
1715 22:55:21.887285 Set Vref, RX VrefLevel [Byte0]: 58
1716 22:55:21.891069 [Byte1]: 58
1717 22:55:21.895286
1718 22:55:21.895418 Set Vref, RX VrefLevel [Byte0]: 59
1719 22:55:21.898535 [Byte1]: 59
1720 22:55:21.902728
1721 22:55:21.902818 Set Vref, RX VrefLevel [Byte0]: 60
1722 22:55:21.905695 [Byte1]: 60
1723 22:55:21.910028
1724 22:55:21.910133 Set Vref, RX VrefLevel [Byte0]: 61
1725 22:55:21.913587 [Byte1]: 61
1726 22:55:21.917673
1727 22:55:21.917776 Set Vref, RX VrefLevel [Byte0]: 62
1728 22:55:21.921029 [Byte1]: 62
1729 22:55:21.925291
1730 22:55:21.925377 Set Vref, RX VrefLevel [Byte0]: 63
1731 22:55:21.928914 [Byte1]: 63
1732 22:55:21.933092
1733 22:55:21.933194 Set Vref, RX VrefLevel [Byte0]: 64
1734 22:55:21.936456 [Byte1]: 64
1735 22:55:21.940715
1736 22:55:21.940790 Set Vref, RX VrefLevel [Byte0]: 65
1737 22:55:21.943858 [Byte1]: 65
1738 22:55:21.947894
1739 22:55:21.947985 Set Vref, RX VrefLevel [Byte0]: 66
1740 22:55:21.951282 [Byte1]: 66
1741 22:55:21.955880
1742 22:55:21.955953 Set Vref, RX VrefLevel [Byte0]: 67
1743 22:55:21.959359 [Byte1]: 67
1744 22:55:21.963153
1745 22:55:21.963225 Set Vref, RX VrefLevel [Byte0]: 68
1746 22:55:21.966446 [Byte1]: 68
1747 22:55:21.971152
1748 22:55:21.971223 Set Vref, RX VrefLevel [Byte0]: 69
1749 22:55:21.974486 [Byte1]: 69
1750 22:55:21.979047
1751 22:55:21.979120 Set Vref, RX VrefLevel [Byte0]: 70
1752 22:55:21.982313 [Byte1]: 70
1753 22:55:21.986201
1754 22:55:21.986298 Set Vref, RX VrefLevel [Byte0]: 71
1755 22:55:21.989277 [Byte1]: 71
1756 22:55:21.993961
1757 22:55:21.994055 Set Vref, RX VrefLevel [Byte0]: 72
1758 22:55:21.997313 [Byte1]: 72
1759 22:55:22.001327
1760 22:55:22.001400 Set Vref, RX VrefLevel [Byte0]: 73
1761 22:55:22.004668 [Byte1]: 73
1762 22:55:22.008928
1763 22:55:22.009022 Set Vref, RX VrefLevel [Byte0]: 74
1764 22:55:22.012064 [Byte1]: 74
1765 22:55:22.016360
1766 22:55:22.016433 Set Vref, RX VrefLevel [Byte0]: 75
1767 22:55:22.020111 [Byte1]: 75
1768 22:55:22.024203
1769 22:55:22.024298 Set Vref, RX VrefLevel [Byte0]: 76
1770 22:55:22.028003 [Byte1]: 76
1771 22:55:22.031817
1772 22:55:22.031897 Final RX Vref Byte 0 = 61 to rank0
1773 22:55:22.035307 Final RX Vref Byte 1 = 60 to rank0
1774 22:55:22.038162 Final RX Vref Byte 0 = 61 to rank1
1775 22:55:22.041687 Final RX Vref Byte 1 = 60 to rank1==
1776 22:55:22.045254 Dram Type= 6, Freq= 0, CH_1, rank 0
1777 22:55:22.051788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1778 22:55:22.051865 ==
1779 22:55:22.051954 DQS Delay:
1780 22:55:22.052031 DQS0 = 0, DQS1 = 0
1781 22:55:22.055294 DQM Delay:
1782 22:55:22.055390 DQM0 = 83, DQM1 = 74
1783 22:55:22.058416 DQ Delay:
1784 22:55:22.061794 DQ0 =88, DQ1 =76, DQ2 =76, DQ3 =84
1785 22:55:22.061874 DQ4 =80, DQ5 =92, DQ6 =92, DQ7 =80
1786 22:55:22.064955 DQ8 =60, DQ9 =60, DQ10 =76, DQ11 =72
1787 22:55:22.068415 DQ12 =84, DQ13 =84, DQ14 =80, DQ15 =76
1788 22:55:22.071627
1789 22:55:22.071703
1790 22:55:22.078739 [DQSOSCAuto] RK0, (LSB)MR18= 0x27fd, (MSB)MR19= 0x605, tDQSOscB0 = 410 ps tDQSOscB1 = 400 ps
1791 22:55:22.081646 CH1 RK0: MR19=605, MR18=27FD
1792 22:55:22.088184 CH1_RK0: MR19=0x605, MR18=0x27FD, DQSOSC=400, MR23=63, INC=92, DEC=61
1793 22:55:22.088266
1794 22:55:22.092038 ----->DramcWriteLeveling(PI) begin...
1795 22:55:22.092113 ==
1796 22:55:22.095055 Dram Type= 6, Freq= 0, CH_1, rank 1
1797 22:55:22.098394 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1798 22:55:22.098469 ==
1799 22:55:22.101821 Write leveling (Byte 0): 28 => 28
1800 22:55:22.105165 Write leveling (Byte 1): 31 => 31
1801 22:55:22.108368 DramcWriteLeveling(PI) end<-----
1802 22:55:22.108449
1803 22:55:22.108528 ==
1804 22:55:22.111705 Dram Type= 6, Freq= 0, CH_1, rank 1
1805 22:55:22.115565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1806 22:55:22.115640 ==
1807 22:55:22.118338 [Gating] SW mode calibration
1808 22:55:22.125412 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1809 22:55:22.131699 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1810 22:55:22.135360 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1811 22:55:22.138821 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1812 22:55:22.145257 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 22:55:22.148493 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 22:55:22.152304 0 6 16 | B1->B0 | 2322 2323 | 1 0 | (0 0) (0 0)
1815 22:55:22.158751 0 6 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1816 22:55:22.162068 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 22:55:22.165566 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 22:55:22.168873 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 22:55:22.175430 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 22:55:22.178914 0 7 8 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1821 22:55:22.181968 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 22:55:22.188703 0 7 16 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1823 22:55:22.191966 0 7 20 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1824 22:55:22.195370 0 7 24 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1825 22:55:22.202185 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 22:55:22.205130 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1827 22:55:22.208923 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1828 22:55:22.215463 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 22:55:22.218901 0 8 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1830 22:55:22.222038 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 22:55:22.228666 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 22:55:22.232255 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 22:55:22.235500 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 22:55:22.242056 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 22:55:22.245297 0 9 4 | B1->B0 | 2424 2525 | 0 1 | (0 0) (0 0)
1836 22:55:22.248548 0 9 8 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
1837 22:55:22.255120 0 9 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1838 22:55:22.258368 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1839 22:55:22.261749 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1840 22:55:22.265130 0 9 24 | B1->B0 | 3535 3434 | 1 1 | (0 0) (1 1)
1841 22:55:22.272040 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1842 22:55:22.275743 0 10 0 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 0)
1843 22:55:22.278510 0 10 4 | B1->B0 | 3131 2f2f | 1 0 | (1 0) (0 1)
1844 22:55:22.285358 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 22:55:22.288673 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 22:55:22.291975 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 22:55:22.298700 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 22:55:22.301736 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 22:55:22.305558 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 22:55:22.311752 0 11 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1851 22:55:22.315248 0 11 4 | B1->B0 | 2525 2b2b | 1 0 | (0 0) (0 0)
1852 22:55:22.318396 0 11 8 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
1853 22:55:22.325549 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1854 22:55:22.328836 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1855 22:55:22.332096 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1856 22:55:22.338563 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1857 22:55:22.342178 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1858 22:55:22.345362 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1859 22:55:22.352068 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1860 22:55:22.355200 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1861 22:55:22.358963 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 22:55:22.365117 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 22:55:22.368469 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 22:55:22.371867 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 22:55:22.375535 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 22:55:22.382014 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 22:55:22.385305 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 22:55:22.388605 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 22:55:22.395181 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 22:55:22.398934 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 22:55:22.401893 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 22:55:22.409072 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 22:55:22.411759 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 22:55:22.415062 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1875 22:55:22.422320 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1876 22:55:22.422403 Total UI for P1: 0, mck2ui 16
1877 22:55:22.428810 best dqsien dly found for B0: ( 0, 14, 0)
1878 22:55:22.432029 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1879 22:55:22.435010 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1880 22:55:22.438491 Total UI for P1: 0, mck2ui 16
1881 22:55:22.442306 best dqsien dly found for B1: ( 0, 14, 6)
1882 22:55:22.445209 best DQS0 dly(MCK, UI, PI) = (0, 14, 0)
1883 22:55:22.448643 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1884 22:55:22.448726
1885 22:55:22.452084 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 0)
1886 22:55:22.455291 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1887 22:55:22.458580 [Gating] SW calibration Done
1888 22:55:22.458662 ==
1889 22:55:22.462234 Dram Type= 6, Freq= 0, CH_1, rank 1
1890 22:55:22.468827 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1891 22:55:22.468911 ==
1892 22:55:22.468976 RX Vref Scan: 0
1893 22:55:22.469037
1894 22:55:22.472288 RX Vref 0 -> 0, step: 1
1895 22:55:22.472370
1896 22:55:22.475499 RX Delay -130 -> 252, step: 16
1897 22:55:22.478925 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1898 22:55:22.482203 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1899 22:55:22.485211 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1900 22:55:22.492112 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1901 22:55:22.495517 iDelay=206, Bit 4, Center 77 (-50 ~ 205) 256
1902 22:55:22.499079 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1903 22:55:22.502181 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1904 22:55:22.505347 iDelay=206, Bit 7, Center 69 (-50 ~ 189) 240
1905 22:55:22.508670 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1906 22:55:22.515264 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1907 22:55:22.518676 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1908 22:55:22.521901 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1909 22:55:22.525518 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1910 22:55:22.531836 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1911 22:55:22.535332 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1912 22:55:22.538934 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1913 22:55:22.539031 ==
1914 22:55:22.541801 Dram Type= 6, Freq= 0, CH_1, rank 1
1915 22:55:22.545296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1916 22:55:22.545380 ==
1917 22:55:22.548525 DQS Delay:
1918 22:55:22.548607 DQS0 = 0, DQS1 = 0
1919 22:55:22.548702 DQM Delay:
1920 22:55:22.552300 DQM0 = 79, DQM1 = 77
1921 22:55:22.552383 DQ Delay:
1922 22:55:22.555318 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =85
1923 22:55:22.558350 DQ4 =77, DQ5 =93, DQ6 =85, DQ7 =69
1924 22:55:22.562227 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
1925 22:55:22.565382 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1926 22:55:22.565480
1927 22:55:22.565586
1928 22:55:22.565646 ==
1929 22:55:22.568695 Dram Type= 6, Freq= 0, CH_1, rank 1
1930 22:55:22.574990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1931 22:55:22.575075 ==
1932 22:55:22.575142
1933 22:55:22.575204
1934 22:55:22.575264 TX Vref Scan disable
1935 22:55:22.578988 == TX Byte 0 ==
1936 22:55:22.582092 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1937 22:55:22.588900 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1938 22:55:22.588984 == TX Byte 1 ==
1939 22:55:22.591912 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1940 22:55:22.598657 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1941 22:55:22.598783 ==
1942 22:55:22.601958 Dram Type= 6, Freq= 0, CH_1, rank 1
1943 22:55:22.605319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1944 22:55:22.605405 ==
1945 22:55:22.618430 TX Vref=22, minBit 0, minWin=27, winSum=440
1946 22:55:22.621407 TX Vref=24, minBit 0, minWin=27, winSum=449
1947 22:55:22.624956 TX Vref=26, minBit 10, minWin=27, winSum=450
1948 22:55:22.628356 TX Vref=28, minBit 2, minWin=28, winSum=453
1949 22:55:22.631471 TX Vref=30, minBit 2, minWin=28, winSum=453
1950 22:55:22.634928 TX Vref=32, minBit 3, minWin=28, winSum=455
1951 22:55:22.641720 [TxChooseVref] Worse bit 3, Min win 28, Win sum 455, Final Vref 32
1952 22:55:22.641805
1953 22:55:22.645024 Final TX Range 1 Vref 32
1954 22:55:22.645109
1955 22:55:22.645176 ==
1956 22:55:22.648415 Dram Type= 6, Freq= 0, CH_1, rank 1
1957 22:55:22.652103 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1958 22:55:22.652189 ==
1959 22:55:22.652256
1960 22:55:22.654698
1961 22:55:22.654782 TX Vref Scan disable
1962 22:55:22.657999 == TX Byte 0 ==
1963 22:55:22.661824 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1964 22:55:22.665197 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1965 22:55:22.668406 == TX Byte 1 ==
1966 22:55:22.672050 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1967 22:55:22.675021 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1968 22:55:22.675105
1969 22:55:22.678548 [DATLAT]
1970 22:55:22.678632 Freq=800, CH1 RK1
1971 22:55:22.678699
1972 22:55:22.681561 DATLAT Default: 0xa
1973 22:55:22.681645 0, 0xFFFF, sum = 0
1974 22:55:22.684888 1, 0xFFFF, sum = 0
1975 22:55:22.684975 2, 0xFFFF, sum = 0
1976 22:55:22.688031 3, 0xFFFF, sum = 0
1977 22:55:22.688116 4, 0xFFFF, sum = 0
1978 22:55:22.691573 5, 0xFFFF, sum = 0
1979 22:55:22.691659 6, 0xFFFF, sum = 0
1980 22:55:22.694885 7, 0xFFFF, sum = 0
1981 22:55:22.698114 8, 0xFFFF, sum = 0
1982 22:55:22.698200 9, 0x0, sum = 1
1983 22:55:22.698268 10, 0x0, sum = 2
1984 22:55:22.701522 11, 0x0, sum = 3
1985 22:55:22.701608 12, 0x0, sum = 4
1986 22:55:22.705344 best_step = 10
1987 22:55:22.705428
1988 22:55:22.705494 ==
1989 22:55:22.708502 Dram Type= 6, Freq= 0, CH_1, rank 1
1990 22:55:22.711562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1991 22:55:22.711647 ==
1992 22:55:22.714990 RX Vref Scan: 0
1993 22:55:22.715074
1994 22:55:22.715140 RX Vref 0 -> 0, step: 1
1995 22:55:22.715202
1996 22:55:22.717921 RX Delay -95 -> 252, step: 8
1997 22:55:22.724828 iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232
1998 22:55:22.728020 iDelay=209, Bit 1, Center 76 (-39 ~ 192) 232
1999 22:55:22.731769 iDelay=209, Bit 2, Center 68 (-47 ~ 184) 232
2000 22:55:22.735068 iDelay=209, Bit 3, Center 76 (-39 ~ 192) 232
2001 22:55:22.738231 iDelay=209, Bit 4, Center 80 (-39 ~ 200) 240
2002 22:55:22.745298 iDelay=209, Bit 5, Center 96 (-15 ~ 208) 224
2003 22:55:22.748456 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
2004 22:55:22.751537 iDelay=209, Bit 7, Center 76 (-39 ~ 192) 232
2005 22:55:22.754712 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
2006 22:55:22.758386 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
2007 22:55:22.764734 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
2008 22:55:22.768467 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
2009 22:55:22.771656 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
2010 22:55:22.775027 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
2011 22:55:22.778164 iDelay=209, Bit 14, Center 84 (-31 ~ 200) 232
2012 22:55:22.785099 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
2013 22:55:22.785199 ==
2014 22:55:22.788574 Dram Type= 6, Freq= 0, CH_1, rank 1
2015 22:55:22.791307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2016 22:55:22.791447 ==
2017 22:55:22.791544 DQS Delay:
2018 22:55:22.794792 DQS0 = 0, DQS1 = 0
2019 22:55:22.794890 DQM Delay:
2020 22:55:22.797990 DQM0 = 81, DQM1 = 74
2021 22:55:22.798091 DQ Delay:
2022 22:55:22.801344 DQ0 =84, DQ1 =76, DQ2 =68, DQ3 =76
2023 22:55:22.804972 DQ4 =80, DQ5 =96, DQ6 =92, DQ7 =76
2024 22:55:22.808367 DQ8 =64, DQ9 =64, DQ10 =72, DQ11 =68
2025 22:55:22.811465 DQ12 =80, DQ13 =84, DQ14 =84, DQ15 =80
2026 22:55:22.811547
2027 22:55:22.811613
2028 22:55:22.818278 [DQSOSCAuto] RK1, (LSB)MR18= 0x242f, (MSB)MR19= 0x606, tDQSOscB0 = 397 ps tDQSOscB1 = 400 ps
2029 22:55:22.821651 CH1 RK1: MR19=606, MR18=242F
2030 22:55:22.828404 CH1_RK1: MR19=0x606, MR18=0x242F, DQSOSC=397, MR23=63, INC=93, DEC=62
2031 22:55:22.831225 [RxdqsGatingPostProcess] freq 800
2032 22:55:22.838448 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2033 22:55:22.841487 Pre-setting of DQS Precalculation
2034 22:55:22.844938 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2035 22:55:22.851238 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2036 22:55:22.857954 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2037 22:55:22.858038
2038 22:55:22.858103
2039 22:55:22.861656 [Calibration Summary] 1600 Mbps
2040 22:55:22.864604 CH 0, Rank 0
2041 22:55:22.864713 SW Impedance : PASS
2042 22:55:22.868374 DUTY Scan : NO K
2043 22:55:22.871760 ZQ Calibration : PASS
2044 22:55:22.871843 Jitter Meter : NO K
2045 22:55:22.874831 CBT Training : PASS
2046 22:55:22.878067 Write leveling : PASS
2047 22:55:22.878149 RX DQS gating : PASS
2048 22:55:22.881657 RX DQ/DQS(RDDQC) : PASS
2049 22:55:22.884855 TX DQ/DQS : PASS
2050 22:55:22.884938 RX DATLAT : PASS
2051 22:55:22.888138 RX DQ/DQS(Engine): PASS
2052 22:55:22.888220 TX OE : NO K
2053 22:55:22.891531 All Pass.
2054 22:55:22.891613
2055 22:55:22.891678 CH 0, Rank 1
2056 22:55:22.894891 SW Impedance : PASS
2057 22:55:22.894973 DUTY Scan : NO K
2058 22:55:22.898355 ZQ Calibration : PASS
2059 22:55:22.901664 Jitter Meter : NO K
2060 22:55:22.901747 CBT Training : PASS
2061 22:55:22.905021 Write leveling : PASS
2062 22:55:22.908167 RX DQS gating : PASS
2063 22:55:22.908250 RX DQ/DQS(RDDQC) : PASS
2064 22:55:22.911121 TX DQ/DQS : PASS
2065 22:55:22.915171 RX DATLAT : PASS
2066 22:55:22.915279 RX DQ/DQS(Engine): PASS
2067 22:55:22.918334 TX OE : NO K
2068 22:55:22.918416 All Pass.
2069 22:55:22.918482
2070 22:55:22.921686 CH 1, Rank 0
2071 22:55:22.921768 SW Impedance : PASS
2072 22:55:22.924993 DUTY Scan : NO K
2073 22:55:22.928392 ZQ Calibration : PASS
2074 22:55:22.928474 Jitter Meter : NO K
2075 22:55:22.931673 CBT Training : PASS
2076 22:55:22.931755 Write leveling : PASS
2077 22:55:22.934720 RX DQS gating : PASS
2078 22:55:22.938121 RX DQ/DQS(RDDQC) : PASS
2079 22:55:22.938203 TX DQ/DQS : PASS
2080 22:55:22.941960 RX DATLAT : PASS
2081 22:55:22.944705 RX DQ/DQS(Engine): PASS
2082 22:55:22.944788 TX OE : NO K
2083 22:55:22.948143 All Pass.
2084 22:55:22.948225
2085 22:55:22.948289 CH 1, Rank 1
2086 22:55:22.951702 SW Impedance : PASS
2087 22:55:22.951785 DUTY Scan : NO K
2088 22:55:22.954643 ZQ Calibration : PASS
2089 22:55:22.958465 Jitter Meter : NO K
2090 22:55:22.958548 CBT Training : PASS
2091 22:55:22.961663 Write leveling : PASS
2092 22:55:22.964914 RX DQS gating : PASS
2093 22:55:22.964997 RX DQ/DQS(RDDQC) : PASS
2094 22:55:22.967853 TX DQ/DQS : PASS
2095 22:55:22.971669 RX DATLAT : PASS
2096 22:55:22.971751 RX DQ/DQS(Engine): PASS
2097 22:55:22.974864 TX OE : NO K
2098 22:55:22.974947 All Pass.
2099 22:55:22.975012
2100 22:55:22.977872 DramC Write-DBI off
2101 22:55:22.981201 PER_BANK_REFRESH: Hybrid Mode
2102 22:55:22.981284 TX_TRACKING: ON
2103 22:55:22.984725 [GetDramInforAfterCalByMRR] Vendor 6.
2104 22:55:22.987947 [GetDramInforAfterCalByMRR] Revision 606.
2105 22:55:22.991269 [GetDramInforAfterCalByMRR] Revision 2 0.
2106 22:55:22.995030 MR0 0x3b3b
2107 22:55:22.995112 MR8 0x5151
2108 22:55:22.998267 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2109 22:55:22.998349
2110 22:55:22.998413 MR0 0x3b3b
2111 22:55:23.001572 MR8 0x5151
2112 22:55:23.004998 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2113 22:55:23.005080
2114 22:55:23.011425 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2115 22:55:23.015538 [FAST_K] Save calibration result to emmc
2116 22:55:23.021441 [FAST_K] Save calibration result to emmc
2117 22:55:23.021523 dram_init: config_dvfs: 1
2118 22:55:23.024693 dramc_set_vcore_voltage set vcore to 662500
2119 22:55:23.027992 Read voltage for 1200, 2
2120 22:55:23.028074 Vio18 = 0
2121 22:55:23.031304 Vcore = 662500
2122 22:55:23.031421 Vdram = 0
2123 22:55:23.031486 Vddq = 0
2124 22:55:23.034551 Vmddr = 0
2125 22:55:23.037748 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2126 22:55:23.044708 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2127 22:55:23.044791 MEM_TYPE=3, freq_sel=15
2128 22:55:23.047789 sv_algorithm_assistance_LP4_1600
2129 22:55:23.054580 ============ PULL DRAM RESETB DOWN ============
2130 22:55:23.058251 ========== PULL DRAM RESETB DOWN end =========
2131 22:55:23.061765 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2132 22:55:23.064533 ===================================
2133 22:55:23.067677 LPDDR4 DRAM CONFIGURATION
2134 22:55:23.071469 ===================================
2135 22:55:23.074358 EX_ROW_EN[0] = 0x0
2136 22:55:23.074440 EX_ROW_EN[1] = 0x0
2137 22:55:23.078378 LP4Y_EN = 0x0
2138 22:55:23.078460 WORK_FSP = 0x0
2139 22:55:23.081000 WL = 0x4
2140 22:55:23.081083 RL = 0x4
2141 22:55:23.084673 BL = 0x2
2142 22:55:23.084755 RPST = 0x0
2143 22:55:23.088065 RD_PRE = 0x0
2144 22:55:23.088147 WR_PRE = 0x1
2145 22:55:23.091041 WR_PST = 0x0
2146 22:55:23.091123 DBI_WR = 0x0
2147 22:55:23.094727 DBI_RD = 0x0
2148 22:55:23.094809 OTF = 0x1
2149 22:55:23.098205 ===================================
2150 22:55:23.100914 ===================================
2151 22:55:23.104711 ANA top config
2152 22:55:23.107707 ===================================
2153 22:55:23.107789 DLL_ASYNC_EN = 0
2154 22:55:23.111565 ALL_SLAVE_EN = 0
2155 22:55:23.114602 NEW_RANK_MODE = 1
2156 22:55:23.117901 DLL_IDLE_MODE = 1
2157 22:55:23.121262 LP45_APHY_COMB_EN = 1
2158 22:55:23.121345 TX_ODT_DIS = 1
2159 22:55:23.124425 NEW_8X_MODE = 1
2160 22:55:23.127769 ===================================
2161 22:55:23.131157 ===================================
2162 22:55:23.134652 data_rate = 2400
2163 22:55:23.137735 CKR = 1
2164 22:55:23.142189 DQ_P2S_RATIO = 8
2165 22:55:23.144667 ===================================
2166 22:55:23.144750 CA_P2S_RATIO = 8
2167 22:55:23.148057 DQ_CA_OPEN = 0
2168 22:55:23.151194 DQ_SEMI_OPEN = 0
2169 22:55:23.154537 CA_SEMI_OPEN = 0
2170 22:55:23.157792 CA_FULL_RATE = 0
2171 22:55:23.161005 DQ_CKDIV4_EN = 0
2172 22:55:23.161087 CA_CKDIV4_EN = 0
2173 22:55:23.164467 CA_PREDIV_EN = 0
2174 22:55:23.167872 PH8_DLY = 17
2175 22:55:23.171250 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2176 22:55:23.174269 DQ_AAMCK_DIV = 4
2177 22:55:23.177888 CA_AAMCK_DIV = 4
2178 22:55:23.177970 CA_ADMCK_DIV = 4
2179 22:55:23.181301 DQ_TRACK_CA_EN = 0
2180 22:55:23.184558 CA_PICK = 1200
2181 22:55:23.187746 CA_MCKIO = 1200
2182 22:55:23.191254 MCKIO_SEMI = 0
2183 22:55:23.194333 PLL_FREQ = 2366
2184 22:55:23.197976 DQ_UI_PI_RATIO = 32
2185 22:55:23.198058 CA_UI_PI_RATIO = 0
2186 22:55:23.201362 ===================================
2187 22:55:23.204370 ===================================
2188 22:55:23.207942 memory_type:LPDDR4
2189 22:55:23.211168 GP_NUM : 10
2190 22:55:23.211251 SRAM_EN : 1
2191 22:55:23.214709 MD32_EN : 0
2192 22:55:23.217988 ===================================
2193 22:55:23.221303 [ANA_INIT] >>>>>>>>>>>>>>
2194 22:55:23.224723 <<<<<< [CONFIGURE PHASE]: ANA_TX
2195 22:55:23.228072 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2196 22:55:23.231287 ===================================
2197 22:55:23.231405 data_rate = 2400,PCW = 0X5b00
2198 22:55:23.234454 ===================================
2199 22:55:23.237943 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2200 22:55:23.244477 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2201 22:55:23.250794 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2202 22:55:23.254441 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2203 22:55:23.257759 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2204 22:55:23.261227 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2205 22:55:23.264192 [ANA_INIT] flow start
2206 22:55:23.264274 [ANA_INIT] PLL >>>>>>>>
2207 22:55:23.267496 [ANA_INIT] PLL <<<<<<<<
2208 22:55:23.271480 [ANA_INIT] MIDPI >>>>>>>>
2209 22:55:23.274420 [ANA_INIT] MIDPI <<<<<<<<
2210 22:55:23.274502 [ANA_INIT] DLL >>>>>>>>
2211 22:55:23.277645 [ANA_INIT] DLL <<<<<<<<
2212 22:55:23.277728 [ANA_INIT] flow end
2213 22:55:23.284551 ============ LP4 DIFF to SE enter ============
2214 22:55:23.287871 ============ LP4 DIFF to SE exit ============
2215 22:55:23.290901 [ANA_INIT] <<<<<<<<<<<<<
2216 22:55:23.294522 [Flow] Enable top DCM control >>>>>
2217 22:55:23.297927 [Flow] Enable top DCM control <<<<<
2218 22:55:23.300995 Enable DLL master slave shuffle
2219 22:55:23.304218 ==============================================================
2220 22:55:23.307831 Gating Mode config
2221 22:55:23.310781 ==============================================================
2222 22:55:23.314714 Config description:
2223 22:55:23.324608 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2224 22:55:23.330796 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2225 22:55:23.334591 SELPH_MODE 0: By rank 1: By Phase
2226 22:55:23.340784 ==============================================================
2227 22:55:23.344160 GAT_TRACK_EN = 1
2228 22:55:23.347473 RX_GATING_MODE = 2
2229 22:55:23.350711 RX_GATING_TRACK_MODE = 2
2230 22:55:23.354093 SELPH_MODE = 1
2231 22:55:23.357463 PICG_EARLY_EN = 1
2232 22:55:23.357545 VALID_LAT_VALUE = 1
2233 22:55:23.364221 ==============================================================
2234 22:55:23.367546 Enter into Gating configuration >>>>
2235 22:55:23.370798 Exit from Gating configuration <<<<
2236 22:55:23.374255 Enter into DVFS_PRE_config >>>>>
2237 22:55:23.384124 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2238 22:55:23.387442 Exit from DVFS_PRE_config <<<<<
2239 22:55:23.390569 Enter into PICG configuration >>>>
2240 22:55:23.394159 Exit from PICG configuration <<<<
2241 22:55:23.397661 [RX_INPUT] configuration >>>>>
2242 22:55:23.400899 [RX_INPUT] configuration <<<<<
2243 22:55:23.403984 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2244 22:55:23.410687 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2245 22:55:23.417213 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2246 22:55:23.424505 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2247 22:55:23.431076 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2248 22:55:23.434258 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2249 22:55:23.440925 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2250 22:55:23.444396 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2251 22:55:23.447760 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2252 22:55:23.450564 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2253 22:55:23.457519 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2254 22:55:23.460847 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2255 22:55:23.464160 ===================================
2256 22:55:23.467421 LPDDR4 DRAM CONFIGURATION
2257 22:55:23.470822 ===================================
2258 22:55:23.470918 EX_ROW_EN[0] = 0x0
2259 22:55:23.474198 EX_ROW_EN[1] = 0x0
2260 22:55:23.474295 LP4Y_EN = 0x0
2261 22:55:23.477378 WORK_FSP = 0x0
2262 22:55:23.477473 WL = 0x4
2263 22:55:23.480694 RL = 0x4
2264 22:55:23.480790 BL = 0x2
2265 22:55:23.483645 RPST = 0x0
2266 22:55:23.483718 RD_PRE = 0x0
2267 22:55:23.487448 WR_PRE = 0x1
2268 22:55:23.487520 WR_PST = 0x0
2269 22:55:23.490692 DBI_WR = 0x0
2270 22:55:23.490785 DBI_RD = 0x0
2271 22:55:23.494180 OTF = 0x1
2272 22:55:23.497233 ===================================
2273 22:55:23.500299 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2274 22:55:23.503711 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2275 22:55:23.510328 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2276 22:55:23.513616 ===================================
2277 22:55:23.516864 LPDDR4 DRAM CONFIGURATION
2278 22:55:23.516940 ===================================
2279 22:55:23.520536 EX_ROW_EN[0] = 0x10
2280 22:55:23.524098 EX_ROW_EN[1] = 0x0
2281 22:55:23.524172 LP4Y_EN = 0x0
2282 22:55:23.527150 WORK_FSP = 0x0
2283 22:55:23.527250 WL = 0x4
2284 22:55:23.531008 RL = 0x4
2285 22:55:23.531114 BL = 0x2
2286 22:55:23.533797 RPST = 0x0
2287 22:55:23.533897 RD_PRE = 0x0
2288 22:55:23.537213 WR_PRE = 0x1
2289 22:55:23.537310 WR_PST = 0x0
2290 22:55:23.540554 DBI_WR = 0x0
2291 22:55:23.540650 DBI_RD = 0x0
2292 22:55:23.543806 OTF = 0x1
2293 22:55:23.547679 ===================================
2294 22:55:23.554217 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2295 22:55:23.554317 ==
2296 22:55:23.557057 Dram Type= 6, Freq= 0, CH_0, rank 0
2297 22:55:23.560529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2298 22:55:23.560624 ==
2299 22:55:23.564034 [Duty_Offset_Calibration]
2300 22:55:23.564147 B0:2 B1:-1 CA:1
2301 22:55:23.564243
2302 22:55:23.567219 [DutyScan_Calibration_Flow] k_type=0
2303 22:55:23.576513
2304 22:55:23.576601 ==CLK 0==
2305 22:55:23.579957 Final CLK duty delay cell = -4
2306 22:55:23.583310 [-4] MAX Duty = 5031%(X100), DQS PI = 4
2307 22:55:23.586489 [-4] MIN Duty = 4875%(X100), DQS PI = 32
2308 22:55:23.589815 [-4] AVG Duty = 4953%(X100)
2309 22:55:23.589894
2310 22:55:23.593639 CH0 CLK Duty spec in!! Max-Min= 156%
2311 22:55:23.596962 [DutyScan_Calibration_Flow] ====Done====
2312 22:55:23.597066
2313 22:55:23.600329 [DutyScan_Calibration_Flow] k_type=1
2314 22:55:23.615043
2315 22:55:23.615169 ==DQS 0 ==
2316 22:55:23.618231 Final DQS duty delay cell = -4
2317 22:55:23.621615 [-4] MAX Duty = 5000%(X100), DQS PI = 54
2318 22:55:23.624953 [-4] MIN Duty = 4876%(X100), DQS PI = 12
2319 22:55:23.628237 [-4] AVG Duty = 4938%(X100)
2320 22:55:23.628342
2321 22:55:23.628438 ==DQS 1 ==
2322 22:55:23.631706 Final DQS duty delay cell = -4
2323 22:55:23.634852 [-4] MAX Duty = 5124%(X100), DQS PI = 6
2324 22:55:23.638297 [-4] MIN Duty = 5000%(X100), DQS PI = 44
2325 22:55:23.642025 [-4] AVG Duty = 5062%(X100)
2326 22:55:23.642095
2327 22:55:23.645279 CH0 DQS 0 Duty spec in!! Max-Min= 124%
2328 22:55:23.645380
2329 22:55:23.648329 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2330 22:55:23.651538 [DutyScan_Calibration_Flow] ====Done====
2331 22:55:23.651606
2332 22:55:23.654654 [DutyScan_Calibration_Flow] k_type=3
2333 22:55:23.672304
2334 22:55:23.672383 ==DQM 0 ==
2335 22:55:23.675518 Final DQM duty delay cell = 0
2336 22:55:23.678798 [0] MAX Duty = 5000%(X100), DQS PI = 54
2337 22:55:23.682303 [0] MIN Duty = 4876%(X100), DQS PI = 8
2338 22:55:23.682383 [0] AVG Duty = 4938%(X100)
2339 22:55:23.685528
2340 22:55:23.685607 ==DQM 1 ==
2341 22:55:23.688496 Final DQM duty delay cell = 0
2342 22:55:23.692316 [0] MAX Duty = 5156%(X100), DQS PI = 62
2343 22:55:23.695431 [0] MIN Duty = 5000%(X100), DQS PI = 8
2344 22:55:23.695513 [0] AVG Duty = 5078%(X100)
2345 22:55:23.698924
2346 22:55:23.702154 CH0 DQM 0 Duty spec in!! Max-Min= 124%
2347 22:55:23.702236
2348 22:55:23.705227 CH0 DQM 1 Duty spec in!! Max-Min= 156%
2349 22:55:23.708548 [DutyScan_Calibration_Flow] ====Done====
2350 22:55:23.708631
2351 22:55:23.712341 [DutyScan_Calibration_Flow] k_type=2
2352 22:55:23.727850
2353 22:55:23.727933 ==DQ 0 ==
2354 22:55:23.731069 Final DQ duty delay cell = -4
2355 22:55:23.734734 [-4] MAX Duty = 5062%(X100), DQS PI = 54
2356 22:55:23.737926 [-4] MIN Duty = 4876%(X100), DQS PI = 18
2357 22:55:23.741371 [-4] AVG Duty = 4969%(X100)
2358 22:55:23.741454
2359 22:55:23.741520 ==DQ 1 ==
2360 22:55:23.744664 Final DQ duty delay cell = 0
2361 22:55:23.747849 [0] MAX Duty = 5031%(X100), DQS PI = 18
2362 22:55:23.751309 [0] MIN Duty = 4907%(X100), DQS PI = 46
2363 22:55:23.751391 [0] AVG Duty = 4969%(X100)
2364 22:55:23.754473
2365 22:55:23.757980 CH0 DQ 0 Duty spec in!! Max-Min= 186%
2366 22:55:23.758059
2367 22:55:23.761327 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2368 22:55:23.764595 [DutyScan_Calibration_Flow] ====Done====
2369 22:55:23.764667 ==
2370 22:55:23.767693 Dram Type= 6, Freq= 0, CH_1, rank 0
2371 22:55:23.771093 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2372 22:55:23.771173 ==
2373 22:55:23.774575 [Duty_Offset_Calibration]
2374 22:55:23.774652 B0:1 B1:1 CA:2
2375 22:55:23.774715
2376 22:55:23.778035 [DutyScan_Calibration_Flow] k_type=0
2377 22:55:23.787822
2378 22:55:23.787903 ==CLK 0==
2379 22:55:23.791291 Final CLK duty delay cell = 0
2380 22:55:23.794811 [0] MAX Duty = 5156%(X100), DQS PI = 24
2381 22:55:23.798125 [0] MIN Duty = 4969%(X100), DQS PI = 40
2382 22:55:23.798239 [0] AVG Duty = 5062%(X100)
2383 22:55:23.801225
2384 22:55:23.801298 CH1 CLK Duty spec in!! Max-Min= 187%
2385 22:55:23.807920 [DutyScan_Calibration_Flow] ====Done====
2386 22:55:23.807994
2387 22:55:23.811390 [DutyScan_Calibration_Flow] k_type=1
2388 22:55:23.827108
2389 22:55:23.827180 ==DQS 0 ==
2390 22:55:23.830790 Final DQS duty delay cell = 0
2391 22:55:23.833779 [0] MAX Duty = 5031%(X100), DQS PI = 18
2392 22:55:23.837173 [0] MIN Duty = 4844%(X100), DQS PI = 50
2393 22:55:23.840859 [0] AVG Duty = 4937%(X100)
2394 22:55:23.840941
2395 22:55:23.841006 ==DQS 1 ==
2396 22:55:23.844078 Final DQS duty delay cell = 0
2397 22:55:23.847866 [0] MAX Duty = 5031%(X100), DQS PI = 34
2398 22:55:23.851026 [0] MIN Duty = 4907%(X100), DQS PI = 14
2399 22:55:23.851135 [0] AVG Duty = 4969%(X100)
2400 22:55:23.854754
2401 22:55:23.857558 CH1 DQS 0 Duty spec in!! Max-Min= 187%
2402 22:55:23.857630
2403 22:55:23.860762 CH1 DQS 1 Duty spec in!! Max-Min= 124%
2404 22:55:23.864318 [DutyScan_Calibration_Flow] ====Done====
2405 22:55:23.864389
2406 22:55:23.867252 [DutyScan_Calibration_Flow] k_type=3
2407 22:55:23.883608
2408 22:55:23.883686 ==DQM 0 ==
2409 22:55:23.887417 Final DQM duty delay cell = 0
2410 22:55:23.890664 [0] MAX Duty = 5093%(X100), DQS PI = 18
2411 22:55:23.893574 [0] MIN Duty = 4876%(X100), DQS PI = 50
2412 22:55:23.897047 [0] AVG Duty = 4984%(X100)
2413 22:55:23.897147
2414 22:55:23.897235 ==DQM 1 ==
2415 22:55:23.900486 Final DQM duty delay cell = 0
2416 22:55:23.903685 [0] MAX Duty = 5156%(X100), DQS PI = 62
2417 22:55:23.907048 [0] MIN Duty = 4938%(X100), DQS PI = 22
2418 22:55:23.910625 [0] AVG Duty = 5047%(X100)
2419 22:55:23.910721
2420 22:55:23.914312 CH1 DQM 0 Duty spec in!! Max-Min= 217%
2421 22:55:23.914408
2422 22:55:23.917055 CH1 DQM 1 Duty spec in!! Max-Min= 218%
2423 22:55:23.920491 [DutyScan_Calibration_Flow] ====Done====
2424 22:55:23.920587
2425 22:55:23.923779 [DutyScan_Calibration_Flow] k_type=2
2426 22:55:23.940308
2427 22:55:23.940415 ==DQ 0 ==
2428 22:55:23.943595 Final DQ duty delay cell = 0
2429 22:55:23.947297 [0] MAX Duty = 5124%(X100), DQS PI = 18
2430 22:55:23.950113 [0] MIN Duty = 4938%(X100), DQS PI = 50
2431 22:55:23.950196 [0] AVG Duty = 5031%(X100)
2432 22:55:23.953721
2433 22:55:23.953803 ==DQ 1 ==
2434 22:55:23.956869 Final DQ duty delay cell = 0
2435 22:55:23.960598 [0] MAX Duty = 5124%(X100), DQS PI = 58
2436 22:55:23.963850 [0] MIN Duty = 5031%(X100), DQS PI = 4
2437 22:55:23.963980 [0] AVG Duty = 5077%(X100)
2438 22:55:23.964105
2439 22:55:23.967171 CH1 DQ 0 Duty spec in!! Max-Min= 186%
2440 22:55:23.967244
2441 22:55:23.970795 CH1 DQ 1 Duty spec in!! Max-Min= 93%
2442 22:55:23.976911 [DutyScan_Calibration_Flow] ====Done====
2443 22:55:23.980641 nWR fixed to 30
2444 22:55:23.980747 [ModeRegInit_LP4] CH0 RK0
2445 22:55:23.984053 [ModeRegInit_LP4] CH0 RK1
2446 22:55:23.987132 [ModeRegInit_LP4] CH1 RK0
2447 22:55:23.987235 [ModeRegInit_LP4] CH1 RK1
2448 22:55:23.990390 match AC timing 7
2449 22:55:23.994083 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2450 22:55:23.997150 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2451 22:55:24.004131 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2452 22:55:24.007762 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2453 22:55:24.013826 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2454 22:55:24.013925 ==
2455 22:55:24.017563 Dram Type= 6, Freq= 0, CH_0, rank 0
2456 22:55:24.020390 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2457 22:55:24.020476 ==
2458 22:55:24.027087 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2459 22:55:24.030228 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2460 22:55:24.040043 [CA 0] Center 40 (10~71) winsize 62
2461 22:55:24.043738 [CA 1] Center 39 (9~70) winsize 62
2462 22:55:24.046763 [CA 2] Center 36 (6~67) winsize 62
2463 22:55:24.050190 [CA 3] Center 35 (5~66) winsize 62
2464 22:55:24.053408 [CA 4] Center 35 (5~65) winsize 61
2465 22:55:24.056800 [CA 5] Center 34 (4~65) winsize 62
2466 22:55:24.056901
2467 22:55:24.060816 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2468 22:55:24.060915
2469 22:55:24.063854 [CATrainingPosCal] consider 1 rank data
2470 22:55:24.067120 u2DelayCellTimex100 = 270/100 ps
2471 22:55:24.070694 CA0 delay=40 (10~71),Diff = 6 PI (28 cell)
2472 22:55:24.076739 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2473 22:55:24.080558 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2474 22:55:24.083666 CA3 delay=35 (5~66),Diff = 1 PI (4 cell)
2475 22:55:24.086910 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
2476 22:55:24.089996 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
2477 22:55:24.090101
2478 22:55:24.093801 CA PerBit enable=1, Macro0, CA PI delay=34
2479 22:55:24.093883
2480 22:55:24.096806 [CBTSetCACLKResult] CA Dly = 34
2481 22:55:24.096887 CS Dly: 7 (0~38)
2482 22:55:24.100389 ==
2483 22:55:24.103561 Dram Type= 6, Freq= 0, CH_0, rank 1
2484 22:55:24.107050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2485 22:55:24.107159 ==
2486 22:55:24.110647 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2487 22:55:24.117167 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2488 22:55:24.126587 [CA 0] Center 39 (9~70) winsize 62
2489 22:55:24.129526 [CA 1] Center 40 (10~70) winsize 61
2490 22:55:24.132905 [CA 2] Center 36 (6~67) winsize 62
2491 22:55:24.136333 [CA 3] Center 36 (5~67) winsize 63
2492 22:55:24.139548 [CA 4] Center 34 (4~65) winsize 62
2493 22:55:24.143086 [CA 5] Center 34 (4~64) winsize 61
2494 22:55:24.143193
2495 22:55:24.145935 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2496 22:55:24.146017
2497 22:55:24.149795 [CATrainingPosCal] consider 2 rank data
2498 22:55:24.153044 u2DelayCellTimex100 = 270/100 ps
2499 22:55:24.156228 CA0 delay=40 (10~70),Diff = 6 PI (28 cell)
2500 22:55:24.162760 CA1 delay=40 (10~70),Diff = 6 PI (28 cell)
2501 22:55:24.166283 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2502 22:55:24.169887 CA3 delay=35 (5~66),Diff = 1 PI (4 cell)
2503 22:55:24.173136 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
2504 22:55:24.176231 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2505 22:55:24.176325
2506 22:55:24.179534 CA PerBit enable=1, Macro0, CA PI delay=34
2507 22:55:24.179623
2508 22:55:24.182776 [CBTSetCACLKResult] CA Dly = 34
2509 22:55:24.182870 CS Dly: 8 (0~41)
2510 22:55:24.182961
2511 22:55:24.186282 ----->DramcWriteLeveling(PI) begin...
2512 22:55:24.189630 ==
2513 22:55:24.192794 Dram Type= 6, Freq= 0, CH_0, rank 0
2514 22:55:24.196210 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2515 22:55:24.196299 ==
2516 22:55:24.200105 Write leveling (Byte 0): 30 => 30
2517 22:55:24.202874 Write leveling (Byte 1): 29 => 29
2518 22:55:24.206244 DramcWriteLeveling(PI) end<-----
2519 22:55:24.206351
2520 22:55:24.206443 ==
2521 22:55:24.209789 Dram Type= 6, Freq= 0, CH_0, rank 0
2522 22:55:24.213338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2523 22:55:24.213424 ==
2524 22:55:24.216570 [Gating] SW mode calibration
2525 22:55:24.223455 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2526 22:55:24.226341 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2527 22:55:24.233602 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2528 22:55:24.236531 0 15 4 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (1 1)
2529 22:55:24.239756 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (0 0) (1 1)
2530 22:55:24.247045 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2531 22:55:24.250461 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2532 22:55:24.253352 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2533 22:55:24.259991 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2534 22:55:24.263111 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2535 22:55:24.267411 1 0 0 | B1->B0 | 3434 2f2f | 1 1 | (1 0) (1 0)
2536 22:55:24.273659 1 0 4 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
2537 22:55:24.277164 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2538 22:55:24.280022 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2539 22:55:24.283436 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2540 22:55:24.290104 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2541 22:55:24.293445 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2542 22:55:24.297255 1 0 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2543 22:55:24.303587 1 1 0 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
2544 22:55:24.306816 1 1 4 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
2545 22:55:24.310161 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2546 22:55:24.316822 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2547 22:55:24.320231 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2548 22:55:24.323454 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2549 22:55:24.330046 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2550 22:55:24.333391 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2551 22:55:24.336747 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2552 22:55:24.343362 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2553 22:55:24.346788 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 22:55:24.350088 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 22:55:24.356733 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 22:55:24.359825 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 22:55:24.363267 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 22:55:24.370240 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 22:55:24.373436 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 22:55:24.376566 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 22:55:24.380134 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 22:55:24.386667 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 22:55:24.390241 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 22:55:24.393679 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 22:55:24.400231 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 22:55:24.403420 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2567 22:55:24.406708 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2568 22:55:24.413679 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2569 22:55:24.417041 Total UI for P1: 0, mck2ui 16
2570 22:55:24.420349 best dqsien dly found for B0: ( 1, 3, 30)
2571 22:55:24.420453 Total UI for P1: 0, mck2ui 16
2572 22:55:24.426955 best dqsien dly found for B1: ( 1, 4, 0)
2573 22:55:24.430174 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2574 22:55:24.433620 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2575 22:55:24.433728
2576 22:55:24.436869 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2577 22:55:24.440591 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2578 22:55:24.443667 [Gating] SW calibration Done
2579 22:55:24.443746 ==
2580 22:55:24.446817 Dram Type= 6, Freq= 0, CH_0, rank 0
2581 22:55:24.449985 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2582 22:55:24.450091 ==
2583 22:55:24.453770 RX Vref Scan: 0
2584 22:55:24.453870
2585 22:55:24.453965 RX Vref 0 -> 0, step: 1
2586 22:55:24.454054
2587 22:55:24.457143 RX Delay -40 -> 252, step: 8
2588 22:55:24.460226 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2589 22:55:24.467485 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2590 22:55:24.470223 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2591 22:55:24.473645 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2592 22:55:24.476847 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2593 22:55:24.480624 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2594 22:55:24.483677 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2595 22:55:24.490799 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2596 22:55:24.493877 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2597 22:55:24.497289 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2598 22:55:24.500469 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2599 22:55:24.503479 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2600 22:55:24.510377 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2601 22:55:24.513985 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2602 22:55:24.516916 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2603 22:55:24.520204 iDelay=200, Bit 15, Center 115 (40 ~ 191) 152
2604 22:55:24.520275 ==
2605 22:55:24.523684 Dram Type= 6, Freq= 0, CH_0, rank 0
2606 22:55:24.530632 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2607 22:55:24.530717 ==
2608 22:55:24.530784 DQS Delay:
2609 22:55:24.533365 DQS0 = 0, DQS1 = 0
2610 22:55:24.533449 DQM Delay:
2611 22:55:24.533511 DQM0 = 115, DQM1 = 107
2612 22:55:24.537320 DQ Delay:
2613 22:55:24.540025 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =111
2614 22:55:24.543859 DQ4 =115, DQ5 =111, DQ6 =123, DQ7 =123
2615 22:55:24.546894 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2616 22:55:24.550284 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115
2617 22:55:24.550381
2618 22:55:24.550470
2619 22:55:24.550559 ==
2620 22:55:24.553918 Dram Type= 6, Freq= 0, CH_0, rank 0
2621 22:55:24.557116 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2622 22:55:24.557216 ==
2623 22:55:24.560283
2624 22:55:24.560354
2625 22:55:24.560415 TX Vref Scan disable
2626 22:55:24.563518 == TX Byte 0 ==
2627 22:55:24.566849 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2628 22:55:24.570297 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2629 22:55:24.573683 == TX Byte 1 ==
2630 22:55:24.576875 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2631 22:55:24.580339 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2632 22:55:24.580414 ==
2633 22:55:24.583666 Dram Type= 6, Freq= 0, CH_0, rank 0
2634 22:55:24.590299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2635 22:55:24.590374 ==
2636 22:55:24.601102 TX Vref=22, minBit 7, minWin=24, winSum=417
2637 22:55:24.604344 TX Vref=24, minBit 5, minWin=25, winSum=421
2638 22:55:24.607515 TX Vref=26, minBit 1, minWin=25, winSum=423
2639 22:55:24.610994 TX Vref=28, minBit 0, minWin=26, winSum=430
2640 22:55:24.614051 TX Vref=30, minBit 1, minWin=26, winSum=432
2641 22:55:24.620387 TX Vref=32, minBit 1, minWin=26, winSum=430
2642 22:55:24.623749 [TxChooseVref] Worse bit 1, Min win 26, Win sum 432, Final Vref 30
2643 22:55:24.623832
2644 22:55:24.627256 Final TX Range 1 Vref 30
2645 22:55:24.627395
2646 22:55:24.627477 ==
2647 22:55:24.630408 Dram Type= 6, Freq= 0, CH_0, rank 0
2648 22:55:24.633682 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2649 22:55:24.637302 ==
2650 22:55:24.637384
2651 22:55:24.637449
2652 22:55:24.637507 TX Vref Scan disable
2653 22:55:24.640661 == TX Byte 0 ==
2654 22:55:24.643679 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2655 22:55:24.650354 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2656 22:55:24.650437 == TX Byte 1 ==
2657 22:55:24.653939 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2658 22:55:24.660198 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2659 22:55:24.660281
2660 22:55:24.660346 [DATLAT]
2661 22:55:24.660406 Freq=1200, CH0 RK0
2662 22:55:24.660464
2663 22:55:24.663960 DATLAT Default: 0xd
2664 22:55:24.664042 0, 0xFFFF, sum = 0
2665 22:55:24.667242 1, 0xFFFF, sum = 0
2666 22:55:24.670360 2, 0xFFFF, sum = 0
2667 22:55:24.670443 3, 0xFFFF, sum = 0
2668 22:55:24.673564 4, 0xFFFF, sum = 0
2669 22:55:24.673648 5, 0xFFFF, sum = 0
2670 22:55:24.676801 6, 0xFFFF, sum = 0
2671 22:55:24.676884 7, 0xFFFF, sum = 0
2672 22:55:24.680484 8, 0xFFFF, sum = 0
2673 22:55:24.680567 9, 0xFFFF, sum = 0
2674 22:55:24.683377 10, 0xFFFF, sum = 0
2675 22:55:24.683475 11, 0xFFFF, sum = 0
2676 22:55:24.686930 12, 0x0, sum = 1
2677 22:55:24.687014 13, 0x0, sum = 2
2678 22:55:24.690176 14, 0x0, sum = 3
2679 22:55:24.690259 15, 0x0, sum = 4
2680 22:55:24.693661 best_step = 13
2681 22:55:24.693742
2682 22:55:24.693806 ==
2683 22:55:24.696720 Dram Type= 6, Freq= 0, CH_0, rank 0
2684 22:55:24.700268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2685 22:55:24.700378 ==
2686 22:55:24.700451 RX Vref Scan: 1
2687 22:55:24.700512
2688 22:55:24.703476 Set Vref Range= 32 -> 127
2689 22:55:24.703558
2690 22:55:24.707037 RX Vref 32 -> 127, step: 1
2691 22:55:24.707119
2692 22:55:24.710351 RX Delay -21 -> 252, step: 4
2693 22:55:24.710433
2694 22:55:24.713281 Set Vref, RX VrefLevel [Byte0]: 32
2695 22:55:24.716578 [Byte1]: 32
2696 22:55:24.716661
2697 22:55:24.720441 Set Vref, RX VrefLevel [Byte0]: 33
2698 22:55:24.723700 [Byte1]: 33
2699 22:55:24.726907
2700 22:55:24.726989 Set Vref, RX VrefLevel [Byte0]: 34
2701 22:55:24.730181 [Byte1]: 34
2702 22:55:24.734848
2703 22:55:24.734929 Set Vref, RX VrefLevel [Byte0]: 35
2704 22:55:24.738191 [Byte1]: 35
2705 22:55:24.742850
2706 22:55:24.742931 Set Vref, RX VrefLevel [Byte0]: 36
2707 22:55:24.746023 [Byte1]: 36
2708 22:55:24.750752
2709 22:55:24.750834 Set Vref, RX VrefLevel [Byte0]: 37
2710 22:55:24.754143 [Byte1]: 37
2711 22:55:24.758624
2712 22:55:24.758706 Set Vref, RX VrefLevel [Byte0]: 38
2713 22:55:24.762033 [Byte1]: 38
2714 22:55:24.766794
2715 22:55:24.766875 Set Vref, RX VrefLevel [Byte0]: 39
2716 22:55:24.770135 [Byte1]: 39
2717 22:55:24.774928
2718 22:55:24.775009 Set Vref, RX VrefLevel [Byte0]: 40
2719 22:55:24.778206 [Byte1]: 40
2720 22:55:24.782478
2721 22:55:24.782560 Set Vref, RX VrefLevel [Byte0]: 41
2722 22:55:24.785721 [Byte1]: 41
2723 22:55:24.790203
2724 22:55:24.790285 Set Vref, RX VrefLevel [Byte0]: 42
2725 22:55:24.793597 [Byte1]: 42
2726 22:55:24.798179
2727 22:55:24.798261 Set Vref, RX VrefLevel [Byte0]: 43
2728 22:55:24.801433 [Byte1]: 43
2729 22:55:24.806292
2730 22:55:24.806374 Set Vref, RX VrefLevel [Byte0]: 44
2731 22:55:24.809743 [Byte1]: 44
2732 22:55:24.814211
2733 22:55:24.814293 Set Vref, RX VrefLevel [Byte0]: 45
2734 22:55:24.817450 [Byte1]: 45
2735 22:55:24.822061
2736 22:55:24.822143 Set Vref, RX VrefLevel [Byte0]: 46
2737 22:55:24.825470 [Byte1]: 46
2738 22:55:24.829923
2739 22:55:24.830005 Set Vref, RX VrefLevel [Byte0]: 47
2740 22:55:24.833708 [Byte1]: 47
2741 22:55:24.838184
2742 22:55:24.838266 Set Vref, RX VrefLevel [Byte0]: 48
2743 22:55:24.841281 [Byte1]: 48
2744 22:55:24.845844
2745 22:55:24.845926 Set Vref, RX VrefLevel [Byte0]: 49
2746 22:55:24.849473 [Byte1]: 49
2747 22:55:24.853690
2748 22:55:24.853772 Set Vref, RX VrefLevel [Byte0]: 50
2749 22:55:24.857310 [Byte1]: 50
2750 22:55:24.861999
2751 22:55:24.862080 Set Vref, RX VrefLevel [Byte0]: 51
2752 22:55:24.865409 [Byte1]: 51
2753 22:55:24.869561
2754 22:55:24.869670 Set Vref, RX VrefLevel [Byte0]: 52
2755 22:55:24.873056 [Byte1]: 52
2756 22:55:24.877650
2757 22:55:24.877732 Set Vref, RX VrefLevel [Byte0]: 53
2758 22:55:24.880980 [Byte1]: 53
2759 22:55:24.886189
2760 22:55:24.886271 Set Vref, RX VrefLevel [Byte0]: 54
2761 22:55:24.888856 [Byte1]: 54
2762 22:55:24.893549
2763 22:55:24.893631 Set Vref, RX VrefLevel [Byte0]: 55
2764 22:55:24.896832 [Byte1]: 55
2765 22:55:24.901132
2766 22:55:24.901235 Set Vref, RX VrefLevel [Byte0]: 56
2767 22:55:24.904591 [Byte1]: 56
2768 22:55:24.908984
2769 22:55:24.909066 Set Vref, RX VrefLevel [Byte0]: 57
2770 22:55:24.912656 [Byte1]: 57
2771 22:55:24.916874
2772 22:55:24.916956 Set Vref, RX VrefLevel [Byte0]: 58
2773 22:55:24.920794 [Byte1]: 58
2774 22:55:24.925312
2775 22:55:24.925393 Set Vref, RX VrefLevel [Byte0]: 59
2776 22:55:24.928144 [Byte1]: 59
2777 22:55:24.933308
2778 22:55:24.933391 Set Vref, RX VrefLevel [Byte0]: 60
2779 22:55:24.936551 [Byte1]: 60
2780 22:55:24.940860
2781 22:55:24.940942 Set Vref, RX VrefLevel [Byte0]: 61
2782 22:55:24.944184 [Byte1]: 61
2783 22:55:24.948696
2784 22:55:24.948778 Set Vref, RX VrefLevel [Byte0]: 62
2785 22:55:24.952906 [Byte1]: 62
2786 22:55:24.956810
2787 22:55:24.956893 Set Vref, RX VrefLevel [Byte0]: 63
2788 22:55:24.960155 [Byte1]: 63
2789 22:55:24.964718
2790 22:55:24.964799 Set Vref, RX VrefLevel [Byte0]: 64
2791 22:55:24.968027 [Byte1]: 64
2792 22:55:24.972693
2793 22:55:24.972775 Set Vref, RX VrefLevel [Byte0]: 65
2794 22:55:24.975812 [Byte1]: 65
2795 22:55:24.980351
2796 22:55:24.980433 Set Vref, RX VrefLevel [Byte0]: 66
2797 22:55:24.983778 [Byte1]: 66
2798 22:55:24.988534
2799 22:55:24.988616 Set Vref, RX VrefLevel [Byte0]: 67
2800 22:55:24.991695 [Byte1]: 67
2801 22:55:24.996425
2802 22:55:24.996506 Final RX Vref Byte 0 = 51 to rank0
2803 22:55:25.000133 Final RX Vref Byte 1 = 52 to rank0
2804 22:55:25.003336 Final RX Vref Byte 0 = 51 to rank1
2805 22:55:25.006557 Final RX Vref Byte 1 = 52 to rank1==
2806 22:55:25.009883 Dram Type= 6, Freq= 0, CH_0, rank 0
2807 22:55:25.013200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2808 22:55:25.016454 ==
2809 22:55:25.016536 DQS Delay:
2810 22:55:25.016602 DQS0 = 0, DQS1 = 0
2811 22:55:25.020150 DQM Delay:
2812 22:55:25.020232 DQM0 = 115, DQM1 = 106
2813 22:55:25.023582 DQ Delay:
2814 22:55:25.027050 DQ0 =112, DQ1 =114, DQ2 =112, DQ3 =114
2815 22:55:25.030031 DQ4 =116, DQ5 =108, DQ6 =122, DQ7 =122
2816 22:55:25.033244 DQ8 =94, DQ9 =92, DQ10 =106, DQ11 =96
2817 22:55:25.036586 DQ12 =114, DQ13 =112, DQ14 =120, DQ15 =114
2818 22:55:25.036668
2819 22:55:25.036732
2820 22:55:25.043515 [DQSOSCAuto] RK0, (LSB)MR18= 0xfceb, (MSB)MR19= 0x303, tDQSOscB0 = 418 ps tDQSOscB1 = 411 ps
2821 22:55:25.046750 CH0 RK0: MR19=303, MR18=FCEB
2822 22:55:25.052976 CH0_RK0: MR19=0x303, MR18=0xFCEB, DQSOSC=411, MR23=63, INC=38, DEC=25
2823 22:55:25.053059
2824 22:55:25.056307 ----->DramcWriteLeveling(PI) begin...
2825 22:55:25.056391 ==
2826 22:55:25.059967 Dram Type= 6, Freq= 0, CH_0, rank 1
2827 22:55:25.063785 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2828 22:55:25.063868 ==
2829 22:55:25.066622 Write leveling (Byte 0): 35 => 35
2830 22:55:25.070137 Write leveling (Byte 1): 29 => 29
2831 22:55:25.073469 DramcWriteLeveling(PI) end<-----
2832 22:55:25.073550
2833 22:55:25.073615 ==
2834 22:55:25.076446 Dram Type= 6, Freq= 0, CH_0, rank 1
2835 22:55:25.083276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2836 22:55:25.083403 ==
2837 22:55:25.083498 [Gating] SW mode calibration
2838 22:55:25.093536 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2839 22:55:25.096772 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2840 22:55:25.099971 0 15 0 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
2841 22:55:25.106285 0 15 4 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
2842 22:55:25.110034 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2843 22:55:25.113236 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2844 22:55:25.120356 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2845 22:55:25.123138 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2846 22:55:25.126786 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
2847 22:55:25.133105 0 15 28 | B1->B0 | 3434 2323 | 1 0 | (1 0) (1 0)
2848 22:55:25.136820 1 0 0 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
2849 22:55:25.140146 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2850 22:55:25.146931 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2851 22:55:25.150182 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2852 22:55:25.153412 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2853 22:55:25.156920 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2854 22:55:25.163191 1 0 24 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
2855 22:55:25.166686 1 0 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
2856 22:55:25.170074 1 1 0 | B1->B0 | 3635 4545 | 1 0 | (0 0) (0 0)
2857 22:55:25.176766 1 1 4 | B1->B0 | 4241 4646 | 1 0 | (0 0) (0 0)
2858 22:55:25.179921 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2859 22:55:25.183273 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2860 22:55:25.190375 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2861 22:55:25.193284 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2862 22:55:25.196606 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2863 22:55:25.203468 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2864 22:55:25.206697 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2865 22:55:25.209691 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2866 22:55:25.216386 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2867 22:55:25.220123 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2868 22:55:25.223074 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2869 22:55:25.229988 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2870 22:55:25.233048 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2871 22:55:25.236325 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2872 22:55:25.242997 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2873 22:55:25.246199 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2874 22:55:25.249544 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2875 22:55:25.256797 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2876 22:55:25.259626 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2877 22:55:25.263095 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2878 22:55:25.266875 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2879 22:55:25.273145 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2880 22:55:25.276683 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2881 22:55:25.280097 Total UI for P1: 0, mck2ui 16
2882 22:55:25.283653 best dqsien dly found for B0: ( 1, 3, 26)
2883 22:55:25.286974 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2884 22:55:25.290352 Total UI for P1: 0, mck2ui 16
2885 22:55:25.293504 best dqsien dly found for B1: ( 1, 4, 0)
2886 22:55:25.296996 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2887 22:55:25.299927 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2888 22:55:25.300035
2889 22:55:25.307030 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2890 22:55:25.310334 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2891 22:55:25.310418 [Gating] SW calibration Done
2892 22:55:25.313305 ==
2893 22:55:25.316735 Dram Type= 6, Freq= 0, CH_0, rank 1
2894 22:55:25.319774 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2895 22:55:25.319859 ==
2896 22:55:25.319943 RX Vref Scan: 0
2897 22:55:25.320023
2898 22:55:25.323334 RX Vref 0 -> 0, step: 1
2899 22:55:25.323458
2900 22:55:25.326715 RX Delay -40 -> 252, step: 8
2901 22:55:25.330118 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2902 22:55:25.333223 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2903 22:55:25.336750 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2904 22:55:25.343131 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2905 22:55:25.346707 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2906 22:55:25.349961 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2907 22:55:25.353263 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2908 22:55:25.356637 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2909 22:55:25.363691 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2910 22:55:25.366889 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2911 22:55:25.369693 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2912 22:55:25.373558 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2913 22:55:25.376261 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2914 22:55:25.383314 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2915 22:55:25.386661 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2916 22:55:25.390014 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2917 22:55:25.390098 ==
2918 22:55:25.393263 Dram Type= 6, Freq= 0, CH_0, rank 1
2919 22:55:25.396518 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2920 22:55:25.396602 ==
2921 22:55:25.399356 DQS Delay:
2922 22:55:25.399454 DQS0 = 0, DQS1 = 0
2923 22:55:25.403303 DQM Delay:
2924 22:55:25.403442 DQM0 = 115, DQM1 = 106
2925 22:55:25.403525 DQ Delay:
2926 22:55:25.409901 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =115
2927 22:55:25.412830 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2928 22:55:25.416484 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =99
2929 22:55:25.419613 DQ12 =115, DQ13 =115, DQ14 =119, DQ15 =111
2930 22:55:25.419699
2931 22:55:25.419782
2932 22:55:25.419879 ==
2933 22:55:25.422875 Dram Type= 6, Freq= 0, CH_0, rank 1
2934 22:55:25.426540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2935 22:55:25.426624 ==
2936 22:55:25.426707
2937 22:55:25.426785
2938 22:55:25.429921 TX Vref Scan disable
2939 22:55:25.433452 == TX Byte 0 ==
2940 22:55:25.436547 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2941 22:55:25.440211 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2942 22:55:25.443562 == TX Byte 1 ==
2943 22:55:25.446583 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2944 22:55:25.450181 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2945 22:55:25.450265 ==
2946 22:55:25.453085 Dram Type= 6, Freq= 0, CH_0, rank 1
2947 22:55:25.456543 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2948 22:55:25.456628 ==
2949 22:55:25.470357 TX Vref=22, minBit 1, minWin=25, winSum=422
2950 22:55:25.473818 TX Vref=24, minBit 1, minWin=25, winSum=424
2951 22:55:25.476673 TX Vref=26, minBit 1, minWin=26, winSum=432
2952 22:55:25.480344 TX Vref=28, minBit 0, minWin=27, winSum=437
2953 22:55:25.483737 TX Vref=30, minBit 1, minWin=26, winSum=436
2954 22:55:25.490504 TX Vref=32, minBit 13, minWin=26, winSum=436
2955 22:55:25.493498 [TxChooseVref] Worse bit 0, Min win 27, Win sum 437, Final Vref 28
2956 22:55:25.493587
2957 22:55:25.496785 Final TX Range 1 Vref 28
2958 22:55:25.496868
2959 22:55:25.496951 ==
2960 22:55:25.500014 Dram Type= 6, Freq= 0, CH_0, rank 1
2961 22:55:25.503296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2962 22:55:25.503417 ==
2963 22:55:25.506437
2964 22:55:25.506545
2965 22:55:25.506628 TX Vref Scan disable
2966 22:55:25.509761 == TX Byte 0 ==
2967 22:55:25.513233 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2968 22:55:25.516518 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2969 22:55:25.520196 == TX Byte 1 ==
2970 22:55:25.523181 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2971 22:55:25.526750 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2972 22:55:25.529996
2973 22:55:25.530079 [DATLAT]
2974 22:55:25.530179 Freq=1200, CH0 RK1
2975 22:55:25.530277
2976 22:55:25.533343 DATLAT Default: 0xd
2977 22:55:25.533446 0, 0xFFFF, sum = 0
2978 22:55:25.536904 1, 0xFFFF, sum = 0
2979 22:55:25.536989 2, 0xFFFF, sum = 0
2980 22:55:25.540289 3, 0xFFFF, sum = 0
2981 22:55:25.540374 4, 0xFFFF, sum = 0
2982 22:55:25.543615 5, 0xFFFF, sum = 0
2983 22:55:25.546782 6, 0xFFFF, sum = 0
2984 22:55:25.546868 7, 0xFFFF, sum = 0
2985 22:55:25.550047 8, 0xFFFF, sum = 0
2986 22:55:25.550133 9, 0xFFFF, sum = 0
2987 22:55:25.553226 10, 0xFFFF, sum = 0
2988 22:55:25.553345 11, 0xFFFF, sum = 0
2989 22:55:25.556754 12, 0x0, sum = 1
2990 22:55:25.556839 13, 0x0, sum = 2
2991 22:55:25.560228 14, 0x0, sum = 3
2992 22:55:25.560313 15, 0x0, sum = 4
2993 22:55:25.560417 best_step = 13
2994 22:55:25.560515
2995 22:55:25.563482 ==
2996 22:55:25.566938 Dram Type= 6, Freq= 0, CH_0, rank 1
2997 22:55:25.569953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2998 22:55:25.570037 ==
2999 22:55:25.570120 RX Vref Scan: 0
3000 22:55:25.570199
3001 22:55:25.573305 RX Vref 0 -> 0, step: 1
3002 22:55:25.573389
3003 22:55:25.577098 RX Delay -21 -> 252, step: 4
3004 22:55:25.580324 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3005 22:55:25.586803 iDelay=195, Bit 1, Center 114 (43 ~ 186) 144
3006 22:55:25.590240 iDelay=195, Bit 2, Center 110 (39 ~ 182) 144
3007 22:55:25.593418 iDelay=195, Bit 3, Center 114 (43 ~ 186) 144
3008 22:55:25.596774 iDelay=195, Bit 4, Center 114 (47 ~ 182) 136
3009 22:55:25.600127 iDelay=195, Bit 5, Center 104 (35 ~ 174) 140
3010 22:55:25.606494 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3011 22:55:25.610096 iDelay=195, Bit 7, Center 120 (51 ~ 190) 140
3012 22:55:25.613428 iDelay=195, Bit 8, Center 94 (27 ~ 162) 136
3013 22:55:25.616655 iDelay=195, Bit 9, Center 92 (23 ~ 162) 140
3014 22:55:25.619916 iDelay=195, Bit 10, Center 108 (39 ~ 178) 140
3015 22:55:25.623356 iDelay=195, Bit 11, Center 94 (27 ~ 162) 136
3016 22:55:25.630154 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3017 22:55:25.633360 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3018 22:55:25.636733 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3019 22:55:25.639888 iDelay=195, Bit 15, Center 114 (47 ~ 182) 136
3020 22:55:25.639964 ==
3021 22:55:25.643276 Dram Type= 6, Freq= 0, CH_0, rank 1
3022 22:55:25.650200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3023 22:55:25.650302 ==
3024 22:55:25.650394 DQS Delay:
3025 22:55:25.653181 DQS0 = 0, DQS1 = 0
3026 22:55:25.653253 DQM Delay:
3027 22:55:25.653315 DQM0 = 114, DQM1 = 104
3028 22:55:25.656584 DQ Delay:
3029 22:55:25.659999 DQ0 =114, DQ1 =114, DQ2 =110, DQ3 =114
3030 22:55:25.663320 DQ4 =114, DQ5 =104, DQ6 =122, DQ7 =120
3031 22:55:25.666698 DQ8 =94, DQ9 =92, DQ10 =108, DQ11 =94
3032 22:55:25.670009 DQ12 =110, DQ13 =110, DQ14 =116, DQ15 =114
3033 22:55:25.670107
3034 22:55:25.670203
3035 22:55:25.676575 [DQSOSCAuto] RK1, (LSB)MR18= 0x2f3, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 409 ps
3036 22:55:25.680237 CH0 RK1: MR19=403, MR18=2F3
3037 22:55:25.686861 CH0_RK1: MR19=0x403, MR18=0x2F3, DQSOSC=409, MR23=63, INC=39, DEC=26
3038 22:55:25.689706 [RxdqsGatingPostProcess] freq 1200
3039 22:55:25.696429 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3040 22:55:25.700106 best DQS0 dly(2T, 0.5T) = (0, 11)
3041 22:55:25.700179 best DQS1 dly(2T, 0.5T) = (0, 12)
3042 22:55:25.703102 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3043 22:55:25.706485 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3044 22:55:25.709774 best DQS0 dly(2T, 0.5T) = (0, 11)
3045 22:55:25.713393 best DQS1 dly(2T, 0.5T) = (0, 12)
3046 22:55:25.716776 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3047 22:55:25.720147 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3048 22:55:25.722978 Pre-setting of DQS Precalculation
3049 22:55:25.726853 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3050 22:55:25.729901 ==
3051 22:55:25.733313 Dram Type= 6, Freq= 0, CH_1, rank 0
3052 22:55:25.736707 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3053 22:55:25.736784 ==
3054 22:55:25.740133 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3055 22:55:25.746713 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3056 22:55:25.756311 [CA 0] Center 38 (8~68) winsize 61
3057 22:55:25.759284 [CA 1] Center 38 (8~68) winsize 61
3058 22:55:25.762646 [CA 2] Center 35 (6~65) winsize 60
3059 22:55:25.765918 [CA 3] Center 34 (4~65) winsize 62
3060 22:55:25.769638 [CA 4] Center 34 (4~65) winsize 62
3061 22:55:25.772531 [CA 5] Center 34 (4~64) winsize 61
3062 22:55:25.772602
3063 22:55:25.775975 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3064 22:55:25.776048
3065 22:55:25.779513 [CATrainingPosCal] consider 1 rank data
3066 22:55:25.782696 u2DelayCellTimex100 = 270/100 ps
3067 22:55:25.785843 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3068 22:55:25.789601 CA1 delay=38 (8~68),Diff = 4 PI (19 cell)
3069 22:55:25.795900 CA2 delay=35 (6~65),Diff = 1 PI (4 cell)
3070 22:55:25.799335 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3071 22:55:25.802516 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3072 22:55:25.806376 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3073 22:55:25.806475
3074 22:55:25.809076 CA PerBit enable=1, Macro0, CA PI delay=34
3075 22:55:25.809178
3076 22:55:25.812532 [CBTSetCACLKResult] CA Dly = 34
3077 22:55:25.812609 CS Dly: 6 (0~37)
3078 22:55:25.815838 ==
3079 22:55:25.815919 Dram Type= 6, Freq= 0, CH_1, rank 1
3080 22:55:25.822092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3081 22:55:25.822169 ==
3082 22:55:25.825714 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3083 22:55:25.832427 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3084 22:55:25.841643 [CA 0] Center 38 (8~68) winsize 61
3085 22:55:25.844534 [CA 1] Center 38 (8~68) winsize 61
3086 22:55:25.848182 [CA 2] Center 34 (4~65) winsize 62
3087 22:55:25.851445 [CA 3] Center 34 (4~65) winsize 62
3088 22:55:25.854704 [CA 4] Center 34 (4~65) winsize 62
3089 22:55:25.858068 [CA 5] Center 33 (3~64) winsize 62
3090 22:55:25.858145
3091 22:55:25.861327 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3092 22:55:25.861400
3093 22:55:25.864805 [CATrainingPosCal] consider 2 rank data
3094 22:55:25.868142 u2DelayCellTimex100 = 270/100 ps
3095 22:55:25.871927 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3096 22:55:25.874799 CA1 delay=38 (8~68),Diff = 4 PI (19 cell)
3097 22:55:25.878124 CA2 delay=35 (6~65),Diff = 1 PI (4 cell)
3098 22:55:25.884669 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3099 22:55:25.888098 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3100 22:55:25.891563 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3101 22:55:25.891656
3102 22:55:25.894724 CA PerBit enable=1, Macro0, CA PI delay=34
3103 22:55:25.894798
3104 22:55:25.898407 [CBTSetCACLKResult] CA Dly = 34
3105 22:55:25.898481 CS Dly: 7 (0~40)
3106 22:55:25.898546
3107 22:55:25.901832 ----->DramcWriteLeveling(PI) begin...
3108 22:55:25.901927 ==
3109 22:55:25.905092 Dram Type= 6, Freq= 0, CH_1, rank 0
3110 22:55:25.911381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3111 22:55:25.911458 ==
3112 22:55:25.915299 Write leveling (Byte 0): 25 => 25
3113 22:55:25.918099 Write leveling (Byte 1): 30 => 30
3114 22:55:25.918196 DramcWriteLeveling(PI) end<-----
3115 22:55:25.921466
3116 22:55:25.921537 ==
3117 22:55:25.925039 Dram Type= 6, Freq= 0, CH_1, rank 0
3118 22:55:25.928374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3119 22:55:25.928448 ==
3120 22:55:25.931535 [Gating] SW mode calibration
3121 22:55:25.938099 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3122 22:55:25.941659 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3123 22:55:25.947899 0 15 0 | B1->B0 | 2929 2323 | 1 0 | (0 0) (0 0)
3124 22:55:25.951583 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3125 22:55:25.954953 0 15 8 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3126 22:55:25.961721 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3127 22:55:25.964885 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3128 22:55:25.968065 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3129 22:55:25.974807 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3130 22:55:25.978320 0 15 28 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 0)
3131 22:55:25.981811 1 0 0 | B1->B0 | 2525 2a2a | 0 0 | (0 0) (0 1)
3132 22:55:25.987823 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3133 22:55:25.991239 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3134 22:55:25.994649 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3135 22:55:26.001539 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3136 22:55:26.005134 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3137 22:55:26.007934 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3138 22:55:26.014728 1 0 28 | B1->B0 | 2c2c 2626 | 0 0 | (0 0) (0 0)
3139 22:55:26.018040 1 1 0 | B1->B0 | 4343 3737 | 0 0 | (0 0) (0 0)
3140 22:55:26.021696 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3141 22:55:26.024923 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3142 22:55:26.031617 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3143 22:55:26.034815 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3144 22:55:26.038114 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3145 22:55:26.044672 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3146 22:55:26.048616 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3147 22:55:26.051768 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3148 22:55:26.058602 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3149 22:55:26.061752 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3150 22:55:26.065081 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3151 22:55:26.071442 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3152 22:55:26.074822 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3153 22:55:26.078519 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3154 22:55:26.085242 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3155 22:55:26.088285 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3156 22:55:26.092213 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3157 22:55:26.094712 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3158 22:55:26.101952 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3159 22:55:26.105134 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3160 22:55:26.108287 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3161 22:55:26.115299 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3162 22:55:26.118420 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3163 22:55:26.121919 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3164 22:55:26.128548 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3165 22:55:26.128628 Total UI for P1: 0, mck2ui 16
3166 22:55:26.135450 best dqsien dly found for B0: ( 1, 3, 30)
3167 22:55:26.135530 Total UI for P1: 0, mck2ui 16
3168 22:55:26.138550 best dqsien dly found for B1: ( 1, 4, 0)
3169 22:55:26.145179 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
3170 22:55:26.148982 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
3171 22:55:26.149057
3172 22:55:26.151894 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
3173 22:55:26.155684 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
3174 22:55:26.158962 [Gating] SW calibration Done
3175 22:55:26.159045 ==
3176 22:55:26.162265 Dram Type= 6, Freq= 0, CH_1, rank 0
3177 22:55:26.165779 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3178 22:55:26.165878 ==
3179 22:55:26.165967 RX Vref Scan: 0
3180 22:55:26.168863
3181 22:55:26.168935 RX Vref 0 -> 0, step: 1
3182 22:55:26.168997
3183 22:55:26.172221 RX Delay -40 -> 252, step: 8
3184 22:55:26.175714 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3185 22:55:26.178908 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3186 22:55:26.185600 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3187 22:55:26.188900 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3188 22:55:26.192243 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3189 22:55:26.195498 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3190 22:55:26.199022 iDelay=200, Bit 6, Center 123 (56 ~ 191) 136
3191 22:55:26.205660 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3192 22:55:26.209107 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3193 22:55:26.212320 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3194 22:55:26.215459 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3195 22:55:26.218717 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3196 22:55:26.225539 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3197 22:55:26.228692 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
3198 22:55:26.232229 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3199 22:55:26.235745 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3200 22:55:26.235856 ==
3201 22:55:26.239214 Dram Type= 6, Freq= 0, CH_1, rank 0
3202 22:55:26.242490 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3203 22:55:26.245874 ==
3204 22:55:26.245976 DQS Delay:
3205 22:55:26.246069 DQS0 = 0, DQS1 = 0
3206 22:55:26.248815 DQM Delay:
3207 22:55:26.248913 DQM0 = 115, DQM1 = 108
3208 22:55:26.252032 DQ Delay:
3209 22:55:26.255653 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =115
3210 22:55:26.259191 DQ4 =111, DQ5 =127, DQ6 =123, DQ7 =115
3211 22:55:26.262606 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =107
3212 22:55:26.265847 DQ12 =119, DQ13 =115, DQ14 =111, DQ15 =111
3213 22:55:26.265953
3214 22:55:26.266042
3215 22:55:26.266139 ==
3216 22:55:26.269269 Dram Type= 6, Freq= 0, CH_1, rank 0
3217 22:55:26.272085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3218 22:55:26.272188 ==
3219 22:55:26.272284
3220 22:55:26.272371
3221 22:55:26.275490 TX Vref Scan disable
3222 22:55:26.279257 == TX Byte 0 ==
3223 22:55:26.282188 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3224 22:55:26.285393 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3225 22:55:26.288797 == TX Byte 1 ==
3226 22:55:26.292082 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3227 22:55:26.295862 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3228 22:55:26.295961 ==
3229 22:55:26.298739 Dram Type= 6, Freq= 0, CH_1, rank 0
3230 22:55:26.302114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3231 22:55:26.305508 ==
3232 22:55:26.316216 TX Vref=22, minBit 1, minWin=24, winSum=408
3233 22:55:26.318929 TX Vref=24, minBit 1, minWin=25, winSum=418
3234 22:55:26.322694 TX Vref=26, minBit 1, minWin=25, winSum=421
3235 22:55:26.326133 TX Vref=28, minBit 0, minWin=26, winSum=428
3236 22:55:26.329054 TX Vref=30, minBit 1, minWin=26, winSum=432
3237 22:55:26.335698 TX Vref=32, minBit 10, minWin=26, winSum=430
3238 22:55:26.339069 [TxChooseVref] Worse bit 1, Min win 26, Win sum 432, Final Vref 30
3239 22:55:26.339171
3240 22:55:26.342716 Final TX Range 1 Vref 30
3241 22:55:26.342789
3242 22:55:26.342865 ==
3243 22:55:26.346262 Dram Type= 6, Freq= 0, CH_1, rank 0
3244 22:55:26.349523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3245 22:55:26.349612 ==
3246 22:55:26.349703
3247 22:55:26.352701
3248 22:55:26.352775 TX Vref Scan disable
3249 22:55:26.355980 == TX Byte 0 ==
3250 22:55:26.359016 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3251 22:55:26.362369 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3252 22:55:26.365824 == TX Byte 1 ==
3253 22:55:26.369291 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3254 22:55:26.372505 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3255 22:55:26.375884
3256 22:55:26.375981 [DATLAT]
3257 22:55:26.376070 Freq=1200, CH1 RK0
3258 22:55:26.376158
3259 22:55:26.379657 DATLAT Default: 0xd
3260 22:55:26.379730 0, 0xFFFF, sum = 0
3261 22:55:26.382889 1, 0xFFFF, sum = 0
3262 22:55:26.382960 2, 0xFFFF, sum = 0
3263 22:55:26.385618 3, 0xFFFF, sum = 0
3264 22:55:26.385698 4, 0xFFFF, sum = 0
3265 22:55:26.388988 5, 0xFFFF, sum = 0
3266 22:55:26.389063 6, 0xFFFF, sum = 0
3267 22:55:26.392559 7, 0xFFFF, sum = 0
3268 22:55:26.396214 8, 0xFFFF, sum = 0
3269 22:55:26.396294 9, 0xFFFF, sum = 0
3270 22:55:26.399705 10, 0xFFFF, sum = 0
3271 22:55:26.399784 11, 0xFFFF, sum = 0
3272 22:55:26.402854 12, 0x0, sum = 1
3273 22:55:26.402960 13, 0x0, sum = 2
3274 22:55:26.403052 14, 0x0, sum = 3
3275 22:55:26.405908 15, 0x0, sum = 4
3276 22:55:26.406009 best_step = 13
3277 22:55:26.406108
3278 22:55:26.409477 ==
3279 22:55:26.409576 Dram Type= 6, Freq= 0, CH_1, rank 0
3280 22:55:26.415956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3281 22:55:26.416066 ==
3282 22:55:26.416158 RX Vref Scan: 1
3283 22:55:26.416245
3284 22:55:26.419686 Set Vref Range= 32 -> 127
3285 22:55:26.419759
3286 22:55:26.422600 RX Vref 32 -> 127, step: 1
3287 22:55:26.422699
3288 22:55:26.425976 RX Delay -21 -> 252, step: 4
3289 22:55:26.426083
3290 22:55:26.429613 Set Vref, RX VrefLevel [Byte0]: 32
3291 22:55:26.432697 [Byte1]: 32
3292 22:55:26.432798
3293 22:55:26.435963 Set Vref, RX VrefLevel [Byte0]: 33
3294 22:55:26.439273 [Byte1]: 33
3295 22:55:26.439402
3296 22:55:26.442603 Set Vref, RX VrefLevel [Byte0]: 34
3297 22:55:26.446074 [Byte1]: 34
3298 22:55:26.449839
3299 22:55:26.449938 Set Vref, RX VrefLevel [Byte0]: 35
3300 22:55:26.453717 [Byte1]: 35
3301 22:55:26.458584
3302 22:55:26.458669 Set Vref, RX VrefLevel [Byte0]: 36
3303 22:55:26.461346 [Byte1]: 36
3304 22:55:26.465714
3305 22:55:26.465811 Set Vref, RX VrefLevel [Byte0]: 37
3306 22:55:26.469020 [Byte1]: 37
3307 22:55:26.473850
3308 22:55:26.473936 Set Vref, RX VrefLevel [Byte0]: 38
3309 22:55:26.477151 [Byte1]: 38
3310 22:55:26.481611
3311 22:55:26.481717 Set Vref, RX VrefLevel [Byte0]: 39
3312 22:55:26.485099 [Byte1]: 39
3313 22:55:26.489412
3314 22:55:26.489490 Set Vref, RX VrefLevel [Byte0]: 40
3315 22:55:26.492810 [Byte1]: 40
3316 22:55:26.497654
3317 22:55:26.497730 Set Vref, RX VrefLevel [Byte0]: 41
3318 22:55:26.500918 [Byte1]: 41
3319 22:55:26.505463
3320 22:55:26.505541 Set Vref, RX VrefLevel [Byte0]: 42
3321 22:55:26.508794 [Byte1]: 42
3322 22:55:26.513308
3323 22:55:26.513378 Set Vref, RX VrefLevel [Byte0]: 43
3324 22:55:26.516466 [Byte1]: 43
3325 22:55:26.521145
3326 22:55:26.521215 Set Vref, RX VrefLevel [Byte0]: 44
3327 22:55:26.524740 [Byte1]: 44
3328 22:55:26.529060
3329 22:55:26.529156 Set Vref, RX VrefLevel [Byte0]: 45
3330 22:55:26.533060 [Byte1]: 45
3331 22:55:26.537426
3332 22:55:26.537526 Set Vref, RX VrefLevel [Byte0]: 46
3333 22:55:26.540505 [Byte1]: 46
3334 22:55:26.545146
3335 22:55:26.545245 Set Vref, RX VrefLevel [Byte0]: 47
3336 22:55:26.548592 [Byte1]: 47
3337 22:55:26.552991
3338 22:55:26.553096 Set Vref, RX VrefLevel [Byte0]: 48
3339 22:55:26.556189 [Byte1]: 48
3340 22:55:26.560984
3341 22:55:26.561054 Set Vref, RX VrefLevel [Byte0]: 49
3342 22:55:26.564412 [Byte1]: 49
3343 22:55:26.569211
3344 22:55:26.569282 Set Vref, RX VrefLevel [Byte0]: 50
3345 22:55:26.571922 [Byte1]: 50
3346 22:55:26.576802
3347 22:55:26.576875 Set Vref, RX VrefLevel [Byte0]: 51
3348 22:55:26.580170 [Byte1]: 51
3349 22:55:26.584709
3350 22:55:26.584808 Set Vref, RX VrefLevel [Byte0]: 52
3351 22:55:26.588105 [Byte1]: 52
3352 22:55:26.592725
3353 22:55:26.592799 Set Vref, RX VrefLevel [Byte0]: 53
3354 22:55:26.596178 [Byte1]: 53
3355 22:55:26.600289
3356 22:55:26.600361 Set Vref, RX VrefLevel [Byte0]: 54
3357 22:55:26.607084 [Byte1]: 54
3358 22:55:26.607161
3359 22:55:26.610183 Set Vref, RX VrefLevel [Byte0]: 55
3360 22:55:26.613461 [Byte1]: 55
3361 22:55:26.613533
3362 22:55:26.616727 Set Vref, RX VrefLevel [Byte0]: 56
3363 22:55:26.620259 [Byte1]: 56
3364 22:55:26.624410
3365 22:55:26.624487 Set Vref, RX VrefLevel [Byte0]: 57
3366 22:55:26.627532 [Byte1]: 57
3367 22:55:26.632140
3368 22:55:26.632248 Set Vref, RX VrefLevel [Byte0]: 58
3369 22:55:26.636193 [Byte1]: 58
3370 22:55:26.640798
3371 22:55:26.640901 Set Vref, RX VrefLevel [Byte0]: 59
3372 22:55:26.643315 [Byte1]: 59
3373 22:55:26.648498
3374 22:55:26.648578 Set Vref, RX VrefLevel [Byte0]: 60
3375 22:55:26.651319 [Byte1]: 60
3376 22:55:26.656321
3377 22:55:26.656395 Set Vref, RX VrefLevel [Byte0]: 61
3378 22:55:26.659164 [Byte1]: 61
3379 22:55:26.663831
3380 22:55:26.663909 Set Vref, RX VrefLevel [Byte0]: 62
3381 22:55:26.667107 [Byte1]: 62
3382 22:55:26.672827
3383 22:55:26.672905 Set Vref, RX VrefLevel [Byte0]: 63
3384 22:55:26.675234 [Byte1]: 63
3385 22:55:26.679602
3386 22:55:26.679676 Set Vref, RX VrefLevel [Byte0]: 64
3387 22:55:26.682975 [Byte1]: 64
3388 22:55:26.688047
3389 22:55:26.688125 Set Vref, RX VrefLevel [Byte0]: 65
3390 22:55:26.690857 [Byte1]: 65
3391 22:55:26.695734
3392 22:55:26.695805 Set Vref, RX VrefLevel [Byte0]: 66
3393 22:55:26.698835 [Byte1]: 66
3394 22:55:26.703660
3395 22:55:26.707192 Set Vref, RX VrefLevel [Byte0]: 67
3396 22:55:26.709949 [Byte1]: 67
3397 22:55:26.710020
3398 22:55:26.713713 Set Vref, RX VrefLevel [Byte0]: 68
3399 22:55:26.717060 [Byte1]: 68
3400 22:55:26.717135
3401 22:55:26.719951 Set Vref, RX VrefLevel [Byte0]: 69
3402 22:55:26.723313 [Byte1]: 69
3403 22:55:26.727200
3404 22:55:26.727296 Set Vref, RX VrefLevel [Byte0]: 70
3405 22:55:26.730814 [Byte1]: 70
3406 22:55:26.735574
3407 22:55:26.735654 Final RX Vref Byte 0 = 55 to rank0
3408 22:55:26.738887 Final RX Vref Byte 1 = 51 to rank0
3409 22:55:26.742024 Final RX Vref Byte 0 = 55 to rank1
3410 22:55:26.745468 Final RX Vref Byte 1 = 51 to rank1==
3411 22:55:26.748772 Dram Type= 6, Freq= 0, CH_1, rank 0
3412 22:55:26.755341 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3413 22:55:26.755459 ==
3414 22:55:26.755553 DQS Delay:
3415 22:55:26.755642 DQS0 = 0, DQS1 = 0
3416 22:55:26.758600 DQM Delay:
3417 22:55:26.758701 DQM0 = 115, DQM1 = 109
3418 22:55:26.761804 DQ Delay:
3419 22:55:26.765552 DQ0 =116, DQ1 =110, DQ2 =106, DQ3 =114
3420 22:55:26.769240 DQ4 =116, DQ5 =124, DQ6 =126, DQ7 =114
3421 22:55:26.772001 DQ8 =98, DQ9 =98, DQ10 =110, DQ11 =106
3422 22:55:26.775339 DQ12 =116, DQ13 =116, DQ14 =116, DQ15 =114
3423 22:55:26.775432
3424 22:55:26.775492
3425 22:55:26.781966 [DQSOSCAuto] RK0, (LSB)MR18= 0x1e6, (MSB)MR19= 0x403, tDQSOscB0 = 420 ps tDQSOscB1 = 409 ps
3426 22:55:26.785347 CH1 RK0: MR19=403, MR18=1E6
3427 22:55:26.792300 CH1_RK0: MR19=0x403, MR18=0x1E6, DQSOSC=409, MR23=63, INC=39, DEC=26
3428 22:55:26.792383
3429 22:55:26.795714 ----->DramcWriteLeveling(PI) begin...
3430 22:55:26.795787 ==
3431 22:55:26.798929 Dram Type= 6, Freq= 0, CH_1, rank 1
3432 22:55:26.802116 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3433 22:55:26.802191 ==
3434 22:55:26.805407 Write leveling (Byte 0): 27 => 27
3435 22:55:26.809119 Write leveling (Byte 1): 27 => 27
3436 22:55:26.812408 DramcWriteLeveling(PI) end<-----
3437 22:55:26.812478
3438 22:55:26.812538 ==
3439 22:55:26.815916 Dram Type= 6, Freq= 0, CH_1, rank 1
3440 22:55:26.819017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3441 22:55:26.819091 ==
3442 22:55:26.822131 [Gating] SW mode calibration
3443 22:55:26.829221 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3444 22:55:26.835851 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3445 22:55:26.839123 0 15 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
3446 22:55:26.845532 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3447 22:55:26.848770 0 15 8 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3448 22:55:26.852280 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3449 22:55:26.859209 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3450 22:55:26.862111 0 15 20 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3451 22:55:26.865437 0 15 24 | B1->B0 | 3535 2929 | 1 0 | (0 0) (0 1)
3452 22:55:26.868747 0 15 28 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
3453 22:55:26.875312 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3454 22:55:26.878745 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3455 22:55:26.882379 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3456 22:55:26.889258 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3457 22:55:26.892381 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3458 22:55:26.895850 1 0 20 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
3459 22:55:26.902263 1 0 24 | B1->B0 | 2929 4040 | 0 0 | (0 0) (0 0)
3460 22:55:26.905503 1 0 28 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
3461 22:55:26.908695 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3462 22:55:26.915519 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3463 22:55:26.918636 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3464 22:55:26.921972 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3465 22:55:26.928747 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3466 22:55:26.931973 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3467 22:55:26.935601 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3468 22:55:26.942195 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3469 22:55:26.945383 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3470 22:55:26.948765 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3471 22:55:26.955268 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3472 22:55:26.958667 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3473 22:55:26.961931 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3474 22:55:26.968601 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3475 22:55:26.972057 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3476 22:55:26.975344 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3477 22:55:26.982053 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3478 22:55:26.985303 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3479 22:55:26.988358 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3480 22:55:26.994902 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3481 22:55:26.998644 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3482 22:55:27.002091 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3483 22:55:27.005396 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3484 22:55:27.012266 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3485 22:55:27.015058 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3486 22:55:27.018624 Total UI for P1: 0, mck2ui 16
3487 22:55:27.021958 best dqsien dly found for B0: ( 1, 3, 26)
3488 22:55:27.025022 Total UI for P1: 0, mck2ui 16
3489 22:55:27.028281 best dqsien dly found for B1: ( 1, 3, 28)
3490 22:55:27.031476 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3491 22:55:27.035051 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3492 22:55:27.035151
3493 22:55:27.038163 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3494 22:55:27.041784 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3495 22:55:27.045196 [Gating] SW calibration Done
3496 22:55:27.045297 ==
3497 22:55:27.048342 Dram Type= 6, Freq= 0, CH_1, rank 1
3498 22:55:27.054906 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3499 22:55:27.055006 ==
3500 22:55:27.055099 RX Vref Scan: 0
3501 22:55:27.055186
3502 22:55:27.058373 RX Vref 0 -> 0, step: 1
3503 22:55:27.058468
3504 22:55:27.061863 RX Delay -40 -> 252, step: 8
3505 22:55:27.064982 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
3506 22:55:27.068228 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3507 22:55:27.071673 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3508 22:55:27.074814 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3509 22:55:27.081517 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3510 22:55:27.084668 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3511 22:55:27.088199 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3512 22:55:27.091507 iDelay=200, Bit 7, Center 107 (40 ~ 175) 136
3513 22:55:27.094672 iDelay=200, Bit 8, Center 99 (24 ~ 175) 152
3514 22:55:27.101308 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3515 22:55:27.104638 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3516 22:55:27.108183 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3517 22:55:27.111289 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
3518 22:55:27.115081 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3519 22:55:27.121197 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3520 22:55:27.124631 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3521 22:55:27.124713 ==
3522 22:55:27.127893 Dram Type= 6, Freq= 0, CH_1, rank 1
3523 22:55:27.131226 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3524 22:55:27.131308 ==
3525 22:55:27.134712 DQS Delay:
3526 22:55:27.134793 DQS0 = 0, DQS1 = 0
3527 22:55:27.134857 DQM Delay:
3528 22:55:27.138072 DQM0 = 112, DQM1 = 110
3529 22:55:27.138153 DQ Delay:
3530 22:55:27.141445 DQ0 =111, DQ1 =111, DQ2 =103, DQ3 =111
3531 22:55:27.144534 DQ4 =111, DQ5 =127, DQ6 =119, DQ7 =107
3532 22:55:27.148122 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =103
3533 22:55:27.154526 DQ12 =115, DQ13 =119, DQ14 =119, DQ15 =119
3534 22:55:27.154608
3535 22:55:27.154672
3536 22:55:27.154730 ==
3537 22:55:27.158089 Dram Type= 6, Freq= 0, CH_1, rank 1
3538 22:55:27.161557 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3539 22:55:27.161639 ==
3540 22:55:27.161703
3541 22:55:27.161762
3542 22:55:27.164663 TX Vref Scan disable
3543 22:55:27.164733 == TX Byte 0 ==
3544 22:55:27.171376 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3545 22:55:27.174546 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3546 22:55:27.174628 == TX Byte 1 ==
3547 22:55:27.181136 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3548 22:55:27.184620 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3549 22:55:27.184702 ==
3550 22:55:27.187959 Dram Type= 6, Freq= 0, CH_1, rank 1
3551 22:55:27.191069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3552 22:55:27.191151 ==
3553 22:55:27.203952 TX Vref=22, minBit 1, minWin=25, winSum=417
3554 22:55:27.207605 TX Vref=24, minBit 3, minWin=25, winSum=420
3555 22:55:27.210425 TX Vref=26, minBit 3, minWin=26, winSum=427
3556 22:55:27.214026 TX Vref=28, minBit 4, minWin=26, winSum=432
3557 22:55:27.217193 TX Vref=30, minBit 9, minWin=26, winSum=432
3558 22:55:27.223620 TX Vref=32, minBit 0, minWin=26, winSum=430
3559 22:55:27.226956 [TxChooseVref] Worse bit 4, Min win 26, Win sum 432, Final Vref 28
3560 22:55:27.227036
3561 22:55:27.230670 Final TX Range 1 Vref 28
3562 22:55:27.230742
3563 22:55:27.230803 ==
3564 22:55:27.233544 Dram Type= 6, Freq= 0, CH_1, rank 1
3565 22:55:27.236883 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3566 22:55:27.236960 ==
3567 22:55:27.240119
3568 22:55:27.240194
3569 22:55:27.240255 TX Vref Scan disable
3570 22:55:27.243877 == TX Byte 0 ==
3571 22:55:27.247004 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3572 22:55:27.249990 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3573 22:55:27.253413 == TX Byte 1 ==
3574 22:55:27.256837 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3575 22:55:27.263635 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3576 22:55:27.263710
3577 22:55:27.263773 [DATLAT]
3578 22:55:27.263831 Freq=1200, CH1 RK1
3579 22:55:27.263893
3580 22:55:27.266882 DATLAT Default: 0xd
3581 22:55:27.266950 0, 0xFFFF, sum = 0
3582 22:55:27.270198 1, 0xFFFF, sum = 0
3583 22:55:27.270273 2, 0xFFFF, sum = 0
3584 22:55:27.273492 3, 0xFFFF, sum = 0
3585 22:55:27.277014 4, 0xFFFF, sum = 0
3586 22:55:27.277089 5, 0xFFFF, sum = 0
3587 22:55:27.280261 6, 0xFFFF, sum = 0
3588 22:55:27.280332 7, 0xFFFF, sum = 0
3589 22:55:27.283324 8, 0xFFFF, sum = 0
3590 22:55:27.283437 9, 0xFFFF, sum = 0
3591 22:55:27.286502 10, 0xFFFF, sum = 0
3592 22:55:27.286594 11, 0xFFFF, sum = 0
3593 22:55:27.289961 12, 0x0, sum = 1
3594 22:55:27.290035 13, 0x0, sum = 2
3595 22:55:27.293500 14, 0x0, sum = 3
3596 22:55:27.293574 15, 0x0, sum = 4
3597 22:55:27.296989 best_step = 13
3598 22:55:27.297059
3599 22:55:27.297119 ==
3600 22:55:27.300237 Dram Type= 6, Freq= 0, CH_1, rank 1
3601 22:55:27.303570 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3602 22:55:27.303651 ==
3603 22:55:27.303734 RX Vref Scan: 0
3604 22:55:27.303811
3605 22:55:27.306835 RX Vref 0 -> 0, step: 1
3606 22:55:27.306920
3607 22:55:27.310189 RX Delay -21 -> 252, step: 4
3608 22:55:27.313705 iDelay=191, Bit 0, Center 112 (43 ~ 182) 140
3609 22:55:27.320068 iDelay=191, Bit 1, Center 110 (43 ~ 178) 136
3610 22:55:27.323604 iDelay=191, Bit 2, Center 104 (39 ~ 170) 132
3611 22:55:27.326350 iDelay=191, Bit 3, Center 112 (47 ~ 178) 132
3612 22:55:27.329692 iDelay=191, Bit 4, Center 114 (47 ~ 182) 136
3613 22:55:27.333285 iDelay=191, Bit 5, Center 122 (55 ~ 190) 136
3614 22:55:27.339820 iDelay=191, Bit 6, Center 122 (55 ~ 190) 136
3615 22:55:27.342958 iDelay=191, Bit 7, Center 112 (47 ~ 178) 132
3616 22:55:27.346425 iDelay=191, Bit 8, Center 98 (31 ~ 166) 136
3617 22:55:27.349589 iDelay=191, Bit 9, Center 98 (35 ~ 162) 128
3618 22:55:27.353008 iDelay=191, Bit 10, Center 110 (43 ~ 178) 136
3619 22:55:27.360251 iDelay=191, Bit 11, Center 102 (35 ~ 170) 136
3620 22:55:27.363177 iDelay=191, Bit 12, Center 114 (51 ~ 178) 128
3621 22:55:27.366695 iDelay=191, Bit 13, Center 120 (55 ~ 186) 132
3622 22:55:27.369877 iDelay=191, Bit 14, Center 118 (55 ~ 182) 128
3623 22:55:27.373133 iDelay=191, Bit 15, Center 118 (55 ~ 182) 128
3624 22:55:27.376712 ==
3625 22:55:27.380196 Dram Type= 6, Freq= 0, CH_1, rank 1
3626 22:55:27.382808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3627 22:55:27.382892 ==
3628 22:55:27.382975 DQS Delay:
3629 22:55:27.386289 DQS0 = 0, DQS1 = 0
3630 22:55:27.386372 DQM Delay:
3631 22:55:27.389623 DQM0 = 113, DQM1 = 109
3632 22:55:27.389707 DQ Delay:
3633 22:55:27.393239 DQ0 =112, DQ1 =110, DQ2 =104, DQ3 =112
3634 22:55:27.396215 DQ4 =114, DQ5 =122, DQ6 =122, DQ7 =112
3635 22:55:27.399803 DQ8 =98, DQ9 =98, DQ10 =110, DQ11 =102
3636 22:55:27.403158 DQ12 =114, DQ13 =120, DQ14 =118, DQ15 =118
3637 22:55:27.403241
3638 22:55:27.403353
3639 22:55:27.412642 [DQSOSCAuto] RK1, (LSB)MR18= 0xf8ff, (MSB)MR19= 0x303, tDQSOscB0 = 410 ps tDQSOscB1 = 413 ps
3640 22:55:27.412724 CH1 RK1: MR19=303, MR18=F8FF
3641 22:55:27.419226 CH1_RK1: MR19=0x303, MR18=0xF8FF, DQSOSC=410, MR23=63, INC=39, DEC=26
3642 22:55:27.422739 [RxdqsGatingPostProcess] freq 1200
3643 22:55:27.429305 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3644 22:55:27.432663 best DQS0 dly(2T, 0.5T) = (0, 11)
3645 22:55:27.436012 best DQS1 dly(2T, 0.5T) = (0, 12)
3646 22:55:27.439149 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3647 22:55:27.442932 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3648 22:55:27.446173 best DQS0 dly(2T, 0.5T) = (0, 11)
3649 22:55:27.449173 best DQS1 dly(2T, 0.5T) = (0, 11)
3650 22:55:27.453095 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3651 22:55:27.456081 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3652 22:55:27.456163 Pre-setting of DQS Precalculation
3653 22:55:27.463201 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3654 22:55:27.468992 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3655 22:55:27.476065 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3656 22:55:27.476147
3657 22:55:27.476210
3658 22:55:27.479242 [Calibration Summary] 2400 Mbps
3659 22:55:27.482381 CH 0, Rank 0
3660 22:55:27.482462 SW Impedance : PASS
3661 22:55:27.485831 DUTY Scan : NO K
3662 22:55:27.489049 ZQ Calibration : PASS
3663 22:55:27.489130 Jitter Meter : NO K
3664 22:55:27.492446 CBT Training : PASS
3665 22:55:27.492527 Write leveling : PASS
3666 22:55:27.496257 RX DQS gating : PASS
3667 22:55:27.499493 RX DQ/DQS(RDDQC) : PASS
3668 22:55:27.499574 TX DQ/DQS : PASS
3669 22:55:27.502550 RX DATLAT : PASS
3670 22:55:27.506032 RX DQ/DQS(Engine): PASS
3671 22:55:27.506114 TX OE : NO K
3672 22:55:27.509124 All Pass.
3673 22:55:27.509219
3674 22:55:27.509285 CH 0, Rank 1
3675 22:55:27.512642 SW Impedance : PASS
3676 22:55:27.512723 DUTY Scan : NO K
3677 22:55:27.515635 ZQ Calibration : PASS
3678 22:55:27.519059 Jitter Meter : NO K
3679 22:55:27.519140 CBT Training : PASS
3680 22:55:27.522690 Write leveling : PASS
3681 22:55:27.525866 RX DQS gating : PASS
3682 22:55:27.525951 RX DQ/DQS(RDDQC) : PASS
3683 22:55:27.528772 TX DQ/DQS : PASS
3684 22:55:27.532185 RX DATLAT : PASS
3685 22:55:27.532268 RX DQ/DQS(Engine): PASS
3686 22:55:27.535686 TX OE : NO K
3687 22:55:27.535787 All Pass.
3688 22:55:27.535882
3689 22:55:27.539470 CH 1, Rank 0
3690 22:55:27.539605 SW Impedance : PASS
3691 22:55:27.541898 DUTY Scan : NO K
3692 22:55:27.545804 ZQ Calibration : PASS
3693 22:55:27.545910 Jitter Meter : NO K
3694 22:55:27.549280 CBT Training : PASS
3695 22:55:27.552113 Write leveling : PASS
3696 22:55:27.552194 RX DQS gating : PASS
3697 22:55:27.555484 RX DQ/DQS(RDDQC) : PASS
3698 22:55:27.555566 TX DQ/DQS : PASS
3699 22:55:27.558784 RX DATLAT : PASS
3700 22:55:27.562027 RX DQ/DQS(Engine): PASS
3701 22:55:27.562110 TX OE : NO K
3702 22:55:27.565436 All Pass.
3703 22:55:27.565567
3704 22:55:27.565679 CH 1, Rank 1
3705 22:55:27.569273 SW Impedance : PASS
3706 22:55:27.569398 DUTY Scan : NO K
3707 22:55:27.572050 ZQ Calibration : PASS
3708 22:55:27.575188 Jitter Meter : NO K
3709 22:55:27.575303 CBT Training : PASS
3710 22:55:27.578601 Write leveling : PASS
3711 22:55:27.581780 RX DQS gating : PASS
3712 22:55:27.581919 RX DQ/DQS(RDDQC) : PASS
3713 22:55:27.585142 TX DQ/DQS : PASS
3714 22:55:27.588685 RX DATLAT : PASS
3715 22:55:27.588805 RX DQ/DQS(Engine): PASS
3716 22:55:27.591725 TX OE : NO K
3717 22:55:27.591831 All Pass.
3718 22:55:27.591930
3719 22:55:27.595334 DramC Write-DBI off
3720 22:55:27.598540 PER_BANK_REFRESH: Hybrid Mode
3721 22:55:27.598679 TX_TRACKING: ON
3722 22:55:27.608570 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3723 22:55:27.611995 [FAST_K] Save calibration result to emmc
3724 22:55:27.614969 dramc_set_vcore_voltage set vcore to 650000
3725 22:55:27.618821 Read voltage for 600, 5
3726 22:55:27.618943 Vio18 = 0
3727 22:55:27.619038 Vcore = 650000
3728 22:55:27.622113 Vdram = 0
3729 22:55:27.622240 Vddq = 0
3730 22:55:27.622336 Vmddr = 0
3731 22:55:27.628660 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3732 22:55:27.631845 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3733 22:55:27.635151 MEM_TYPE=3, freq_sel=19
3734 22:55:27.638479 sv_algorithm_assistance_LP4_1600
3735 22:55:27.641722 ============ PULL DRAM RESETB DOWN ============
3736 22:55:27.645246 ========== PULL DRAM RESETB DOWN end =========
3737 22:55:27.651837 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3738 22:55:27.655165 ===================================
3739 22:55:27.655285 LPDDR4 DRAM CONFIGURATION
3740 22:55:27.658582 ===================================
3741 22:55:27.661731 EX_ROW_EN[0] = 0x0
3742 22:55:27.665095 EX_ROW_EN[1] = 0x0
3743 22:55:27.665200 LP4Y_EN = 0x0
3744 22:55:27.668345 WORK_FSP = 0x0
3745 22:55:27.668460 WL = 0x2
3746 22:55:27.672080 RL = 0x2
3747 22:55:27.672189 BL = 0x2
3748 22:55:27.675551 RPST = 0x0
3749 22:55:27.675647 RD_PRE = 0x0
3750 22:55:27.678542 WR_PRE = 0x1
3751 22:55:27.678647 WR_PST = 0x0
3752 22:55:27.681918 DBI_WR = 0x0
3753 22:55:27.682024 DBI_RD = 0x0
3754 22:55:27.684966 OTF = 0x1
3755 22:55:27.688705 ===================================
3756 22:55:27.691834 ===================================
3757 22:55:27.691947 ANA top config
3758 22:55:27.695005 ===================================
3759 22:55:27.698552 DLL_ASYNC_EN = 0
3760 22:55:27.702506 ALL_SLAVE_EN = 1
3761 22:55:27.702601 NEW_RANK_MODE = 1
3762 22:55:27.705036 DLL_IDLE_MODE = 1
3763 22:55:27.708228 LP45_APHY_COMB_EN = 1
3764 22:55:27.711623 TX_ODT_DIS = 1
3765 22:55:27.715342 NEW_8X_MODE = 1
3766 22:55:27.718469 ===================================
3767 22:55:27.721806 ===================================
3768 22:55:27.721913 data_rate = 1200
3769 22:55:27.725199 CKR = 1
3770 22:55:27.728759 DQ_P2S_RATIO = 8
3771 22:55:27.731712 ===================================
3772 22:55:27.735285 CA_P2S_RATIO = 8
3773 22:55:27.738240 DQ_CA_OPEN = 0
3774 22:55:27.741539 DQ_SEMI_OPEN = 0
3775 22:55:27.741647 CA_SEMI_OPEN = 0
3776 22:55:27.745211 CA_FULL_RATE = 0
3777 22:55:27.748670 DQ_CKDIV4_EN = 1
3778 22:55:27.751341 CA_CKDIV4_EN = 1
3779 22:55:27.755024 CA_PREDIV_EN = 0
3780 22:55:27.758277 PH8_DLY = 0
3781 22:55:27.758384 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3782 22:55:27.761495 DQ_AAMCK_DIV = 4
3783 22:55:27.764812 CA_AAMCK_DIV = 4
3784 22:55:27.768278 CA_ADMCK_DIV = 4
3785 22:55:27.771824 DQ_TRACK_CA_EN = 0
3786 22:55:27.774877 CA_PICK = 600
3787 22:55:27.774986 CA_MCKIO = 600
3788 22:55:27.778272 MCKIO_SEMI = 0
3789 22:55:27.781377 PLL_FREQ = 2288
3790 22:55:27.784743 DQ_UI_PI_RATIO = 32
3791 22:55:27.788043 CA_UI_PI_RATIO = 0
3792 22:55:27.791606 ===================================
3793 22:55:27.794554 ===================================
3794 22:55:27.798376 memory_type:LPDDR4
3795 22:55:27.798483 GP_NUM : 10
3796 22:55:27.801802 SRAM_EN : 1
3797 22:55:27.801914 MD32_EN : 0
3798 22:55:27.805099 ===================================
3799 22:55:27.807897 [ANA_INIT] >>>>>>>>>>>>>>
3800 22:55:27.811304 <<<<<< [CONFIGURE PHASE]: ANA_TX
3801 22:55:27.814510 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3802 22:55:27.817689 ===================================
3803 22:55:27.821001 data_rate = 1200,PCW = 0X5800
3804 22:55:27.824560 ===================================
3805 22:55:27.827728 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3806 22:55:27.834165 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3807 22:55:27.837640 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3808 22:55:27.844137 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3809 22:55:27.847973 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3810 22:55:27.850913 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3811 22:55:27.851049 [ANA_INIT] flow start
3812 22:55:27.854502 [ANA_INIT] PLL >>>>>>>>
3813 22:55:27.857560 [ANA_INIT] PLL <<<<<<<<
3814 22:55:27.857692 [ANA_INIT] MIDPI >>>>>>>>
3815 22:55:27.861079 [ANA_INIT] MIDPI <<<<<<<<
3816 22:55:27.864534 [ANA_INIT] DLL >>>>>>>>
3817 22:55:27.864670 [ANA_INIT] flow end
3818 22:55:27.870760 ============ LP4 DIFF to SE enter ============
3819 22:55:27.874089 ============ LP4 DIFF to SE exit ============
3820 22:55:27.877523 [ANA_INIT] <<<<<<<<<<<<<
3821 22:55:27.880611 [Flow] Enable top DCM control >>>>>
3822 22:55:27.884040 [Flow] Enable top DCM control <<<<<
3823 22:55:27.884120 Enable DLL master slave shuffle
3824 22:55:27.890963 ==============================================================
3825 22:55:27.894187 Gating Mode config
3826 22:55:27.897385 ==============================================================
3827 22:55:27.900842 Config description:
3828 22:55:27.910693 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3829 22:55:27.917295 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3830 22:55:27.920732 SELPH_MODE 0: By rank 1: By Phase
3831 22:55:27.927266 ==============================================================
3832 22:55:27.930715 GAT_TRACK_EN = 1
3833 22:55:27.933645 RX_GATING_MODE = 2
3834 22:55:27.937225 RX_GATING_TRACK_MODE = 2
3835 22:55:27.940497 SELPH_MODE = 1
3836 22:55:27.940605 PICG_EARLY_EN = 1
3837 22:55:27.943647 VALID_LAT_VALUE = 1
3838 22:55:27.950419 ==============================================================
3839 22:55:27.953946 Enter into Gating configuration >>>>
3840 22:55:27.957280 Exit from Gating configuration <<<<
3841 22:55:27.960559 Enter into DVFS_PRE_config >>>>>
3842 22:55:27.970634 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3843 22:55:27.973680 Exit from DVFS_PRE_config <<<<<
3844 22:55:27.976895 Enter into PICG configuration >>>>
3845 22:55:27.980583 Exit from PICG configuration <<<<
3846 22:55:27.984243 [RX_INPUT] configuration >>>>>
3847 22:55:27.987001 [RX_INPUT] configuration <<<<<
3848 22:55:27.990264 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3849 22:55:27.996776 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3850 22:55:28.003770 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3851 22:55:28.010337 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3852 22:55:28.017063 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3853 22:55:28.020285 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3854 22:55:28.027000 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3855 22:55:28.030201 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3856 22:55:28.033542 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3857 22:55:28.036778 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3858 22:55:28.043690 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3859 22:55:28.047030 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3860 22:55:28.050282 ===================================
3861 22:55:28.053292 LPDDR4 DRAM CONFIGURATION
3862 22:55:28.056777 ===================================
3863 22:55:28.056855 EX_ROW_EN[0] = 0x0
3864 22:55:28.060105 EX_ROW_EN[1] = 0x0
3865 22:55:28.060178 LP4Y_EN = 0x0
3866 22:55:28.063662 WORK_FSP = 0x0
3867 22:55:28.063746 WL = 0x2
3868 22:55:28.067155 RL = 0x2
3869 22:55:28.067242 BL = 0x2
3870 22:55:28.070090 RPST = 0x0
3871 22:55:28.070216 RD_PRE = 0x0
3872 22:55:28.073437 WR_PRE = 0x1
3873 22:55:28.076884 WR_PST = 0x0
3874 22:55:28.077055 DBI_WR = 0x0
3875 22:55:28.079885 DBI_RD = 0x0
3876 22:55:28.079969 OTF = 0x1
3877 22:55:28.083098 ===================================
3878 22:55:28.086645 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3879 22:55:28.093203 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3880 22:55:28.096411 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3881 22:55:28.100074 ===================================
3882 22:55:28.103072 LPDDR4 DRAM CONFIGURATION
3883 22:55:28.106490 ===================================
3884 22:55:28.106575 EX_ROW_EN[0] = 0x10
3885 22:55:28.109671 EX_ROW_EN[1] = 0x0
3886 22:55:28.109755 LP4Y_EN = 0x0
3887 22:55:28.112873 WORK_FSP = 0x0
3888 22:55:28.112949 WL = 0x2
3889 22:55:28.116332 RL = 0x2
3890 22:55:28.116406 BL = 0x2
3891 22:55:28.119820 RPST = 0x0
3892 22:55:28.119903 RD_PRE = 0x0
3893 22:55:28.123111 WR_PRE = 0x1
3894 22:55:28.123214 WR_PST = 0x0
3895 22:55:28.126617 DBI_WR = 0x0
3896 22:55:28.129906 DBI_RD = 0x0
3897 22:55:28.129989 OTF = 0x1
3898 22:55:28.133141 ===================================
3899 22:55:28.139688 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3900 22:55:28.143076 nWR fixed to 30
3901 22:55:28.146519 [ModeRegInit_LP4] CH0 RK0
3902 22:55:28.146594 [ModeRegInit_LP4] CH0 RK1
3903 22:55:28.149591 [ModeRegInit_LP4] CH1 RK0
3904 22:55:28.152863 [ModeRegInit_LP4] CH1 RK1
3905 22:55:28.152939 match AC timing 17
3906 22:55:28.160136 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3907 22:55:28.162839 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3908 22:55:28.166083 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3909 22:55:28.172977 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3910 22:55:28.175913 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3911 22:55:28.175992 ==
3912 22:55:28.179714 Dram Type= 6, Freq= 0, CH_0, rank 0
3913 22:55:28.182808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3914 22:55:28.182883 ==
3915 22:55:28.189186 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3916 22:55:28.195707 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3917 22:55:28.199140 [CA 0] Center 36 (6~66) winsize 61
3918 22:55:28.202685 [CA 1] Center 35 (5~66) winsize 62
3919 22:55:28.205978 [CA 2] Center 34 (4~65) winsize 62
3920 22:55:28.208953 [CA 3] Center 34 (4~65) winsize 62
3921 22:55:28.212840 [CA 4] Center 33 (3~64) winsize 62
3922 22:55:28.215614 [CA 5] Center 33 (3~64) winsize 62
3923 22:55:28.215734
3924 22:55:28.219201 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3925 22:55:28.219323
3926 22:55:28.222865 [CATrainingPosCal] consider 1 rank data
3927 22:55:28.225723 u2DelayCellTimex100 = 270/100 ps
3928 22:55:28.229122 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3929 22:55:28.232580 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3930 22:55:28.235775 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3931 22:55:28.239381 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3932 22:55:28.245701 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3933 22:55:28.249270 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3934 22:55:28.249353
3935 22:55:28.252563 CA PerBit enable=1, Macro0, CA PI delay=33
3936 22:55:28.252677
3937 22:55:28.255711 [CBTSetCACLKResult] CA Dly = 33
3938 22:55:28.255794 CS Dly: 4 (0~35)
3939 22:55:28.255859 ==
3940 22:55:28.258783 Dram Type= 6, Freq= 0, CH_0, rank 1
3941 22:55:28.265807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3942 22:55:28.265890 ==
3943 22:55:28.269300 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3944 22:55:28.275230 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3945 22:55:28.278604 [CA 0] Center 36 (6~66) winsize 61
3946 22:55:28.282163 [CA 1] Center 36 (6~66) winsize 61
3947 22:55:28.285585 [CA 2] Center 34 (4~65) winsize 62
3948 22:55:28.288838 [CA 3] Center 34 (4~65) winsize 62
3949 22:55:28.292358 [CA 4] Center 33 (3~64) winsize 62
3950 22:55:28.295300 [CA 5] Center 33 (3~64) winsize 62
3951 22:55:28.295419
3952 22:55:28.299106 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3953 22:55:28.299214
3954 22:55:28.302206 [CATrainingPosCal] consider 2 rank data
3955 22:55:28.305612 u2DelayCellTimex100 = 270/100 ps
3956 22:55:28.308692 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3957 22:55:28.311974 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3958 22:55:28.315807 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3959 22:55:28.322193 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3960 22:55:28.325127 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3961 22:55:28.328525 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3962 22:55:28.328608
3963 22:55:28.332404 CA PerBit enable=1, Macro0, CA PI delay=33
3964 22:55:28.332486
3965 22:55:28.335296 [CBTSetCACLKResult] CA Dly = 33
3966 22:55:28.335421 CS Dly: 4 (0~36)
3967 22:55:28.335517
3968 22:55:28.338660 ----->DramcWriteLeveling(PI) begin...
3969 22:55:28.338743 ==
3970 22:55:28.341859 Dram Type= 6, Freq= 0, CH_0, rank 0
3971 22:55:28.348795 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3972 22:55:28.348878 ==
3973 22:55:28.352323 Write leveling (Byte 0): 32 => 32
3974 22:55:28.355156 Write leveling (Byte 1): 32 => 32
3975 22:55:28.355264 DramcWriteLeveling(PI) end<-----
3976 22:55:28.358648
3977 22:55:28.358729 ==
3978 22:55:28.362100 Dram Type= 6, Freq= 0, CH_0, rank 0
3979 22:55:28.365954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3980 22:55:28.366037 ==
3981 22:55:28.368643 [Gating] SW mode calibration
3982 22:55:28.375058 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3983 22:55:28.378743 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3984 22:55:28.385227 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3985 22:55:28.388775 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3986 22:55:28.391949 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3987 22:55:28.398108 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
3988 22:55:28.401432 0 9 16 | B1->B0 | 3131 2d2d | 0 0 | (1 1) (1 1)
3989 22:55:28.404951 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3990 22:55:28.411500 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3991 22:55:28.415080 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3992 22:55:28.418270 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3993 22:55:28.424607 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3994 22:55:28.428517 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3995 22:55:28.431640 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3996 22:55:28.438314 0 10 16 | B1->B0 | 3131 3b3b | 0 0 | (0 0) (0 0)
3997 22:55:28.441757 0 10 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
3998 22:55:28.444649 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3999 22:55:28.451254 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4000 22:55:28.454724 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4001 22:55:28.457897 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4002 22:55:28.464996 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4003 22:55:28.467815 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4004 22:55:28.471591 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4005 22:55:28.477695 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 22:55:28.481019 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 22:55:28.485010 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 22:55:28.491780 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 22:55:28.494568 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4010 22:55:28.498224 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4011 22:55:28.504968 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4012 22:55:28.507896 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4013 22:55:28.511472 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4014 22:55:28.514585 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4015 22:55:28.521208 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4016 22:55:28.524477 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4017 22:55:28.527735 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4018 22:55:28.534604 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4019 22:55:28.537871 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4020 22:55:28.541087 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4021 22:55:28.544565 Total UI for P1: 0, mck2ui 16
4022 22:55:28.547621 best dqsien dly found for B0: ( 0, 13, 12)
4023 22:55:28.554260 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4024 22:55:28.554340 Total UI for P1: 0, mck2ui 16
4025 22:55:28.560865 best dqsien dly found for B1: ( 0, 13, 16)
4026 22:55:28.564142 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4027 22:55:28.567626 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4028 22:55:28.567725
4029 22:55:28.570891 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4030 22:55:28.574542 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4031 22:55:28.577599 [Gating] SW calibration Done
4032 22:55:28.577695 ==
4033 22:55:28.581067 Dram Type= 6, Freq= 0, CH_0, rank 0
4034 22:55:28.584037 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4035 22:55:28.584108 ==
4036 22:55:28.587524 RX Vref Scan: 0
4037 22:55:28.587627
4038 22:55:28.587725 RX Vref 0 -> 0, step: 1
4039 22:55:28.590769
4040 22:55:28.590850 RX Delay -230 -> 252, step: 16
4041 22:55:28.597425 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4042 22:55:28.600601 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4043 22:55:28.604048 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4044 22:55:28.607660 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4045 22:55:28.614590 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4046 22:55:28.617707 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4047 22:55:28.620893 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4048 22:55:28.623690 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4049 22:55:28.627272 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4050 22:55:28.633995 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4051 22:55:28.637542 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4052 22:55:28.640343 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4053 22:55:28.643823 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4054 22:55:28.650679 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4055 22:55:28.653926 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4056 22:55:28.657395 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4057 22:55:28.657512 ==
4058 22:55:28.660252 Dram Type= 6, Freq= 0, CH_0, rank 0
4059 22:55:28.663663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4060 22:55:28.667010 ==
4061 22:55:28.667118 DQS Delay:
4062 22:55:28.667222 DQS0 = 0, DQS1 = 0
4063 22:55:28.670352 DQM Delay:
4064 22:55:28.670455 DQM0 = 42, DQM1 = 35
4065 22:55:28.673776 DQ Delay:
4066 22:55:28.673859 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4067 22:55:28.677481 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4068 22:55:28.680422 DQ8 =17, DQ9 =17, DQ10 =41, DQ11 =25
4069 22:55:28.683947 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =49
4070 22:55:28.686749
4071 22:55:28.686833
4072 22:55:28.686933 ==
4073 22:55:28.690205 Dram Type= 6, Freq= 0, CH_0, rank 0
4074 22:55:28.693633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4075 22:55:28.693715 ==
4076 22:55:28.693795
4077 22:55:28.693872
4078 22:55:28.696877 TX Vref Scan disable
4079 22:55:28.696983 == TX Byte 0 ==
4080 22:55:28.703654 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4081 22:55:28.707130 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4082 22:55:28.707232 == TX Byte 1 ==
4083 22:55:28.713386 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4084 22:55:28.716653 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4085 22:55:28.716730 ==
4086 22:55:28.720706 Dram Type= 6, Freq= 0, CH_0, rank 0
4087 22:55:28.723781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4088 22:55:28.723886 ==
4089 22:55:28.724067
4090 22:55:28.724132
4091 22:55:28.726661 TX Vref Scan disable
4092 22:55:28.730410 == TX Byte 0 ==
4093 22:55:28.733297 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4094 22:55:28.736714 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4095 22:55:28.740358 == TX Byte 1 ==
4096 22:55:28.743714 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4097 22:55:28.747208 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4098 22:55:28.747315
4099 22:55:28.750206 [DATLAT]
4100 22:55:28.750288 Freq=600, CH0 RK0
4101 22:55:28.750353
4102 22:55:28.753641 DATLAT Default: 0x9
4103 22:55:28.753723 0, 0xFFFF, sum = 0
4104 22:55:28.757225 1, 0xFFFF, sum = 0
4105 22:55:28.757321 2, 0xFFFF, sum = 0
4106 22:55:28.760336 3, 0xFFFF, sum = 0
4107 22:55:28.760422 4, 0xFFFF, sum = 0
4108 22:55:28.763680 5, 0xFFFF, sum = 0
4109 22:55:28.763765 6, 0xFFFF, sum = 0
4110 22:55:28.766792 7, 0xFFFF, sum = 0
4111 22:55:28.766877 8, 0x0, sum = 1
4112 22:55:28.769803 9, 0x0, sum = 2
4113 22:55:28.769888 10, 0x0, sum = 3
4114 22:55:28.773160 11, 0x0, sum = 4
4115 22:55:28.773245 best_step = 9
4116 22:55:28.773328
4117 22:55:28.773406 ==
4118 22:55:28.776455 Dram Type= 6, Freq= 0, CH_0, rank 0
4119 22:55:28.782957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4120 22:55:28.783042 ==
4121 22:55:28.783143 RX Vref Scan: 1
4122 22:55:28.783240
4123 22:55:28.786399 RX Vref 0 -> 0, step: 1
4124 22:55:28.786482
4125 22:55:28.789717 RX Delay -195 -> 252, step: 8
4126 22:55:28.789799
4127 22:55:28.793220 Set Vref, RX VrefLevel [Byte0]: 51
4128 22:55:28.796636 [Byte1]: 52
4129 22:55:28.796718
4130 22:55:28.799887 Final RX Vref Byte 0 = 51 to rank0
4131 22:55:28.803121 Final RX Vref Byte 1 = 52 to rank0
4132 22:55:28.806530 Final RX Vref Byte 0 = 51 to rank1
4133 22:55:28.810024 Final RX Vref Byte 1 = 52 to rank1==
4134 22:55:28.813387 Dram Type= 6, Freq= 0, CH_0, rank 0
4135 22:55:28.816709 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4136 22:55:28.816791 ==
4137 22:55:28.820205 DQS Delay:
4138 22:55:28.820287 DQS0 = 0, DQS1 = 0
4139 22:55:28.820352 DQM Delay:
4140 22:55:28.823113 DQM0 = 42, DQM1 = 33
4141 22:55:28.823195 DQ Delay:
4142 22:55:28.826667 DQ0 =44, DQ1 =44, DQ2 =36, DQ3 =40
4143 22:55:28.829894 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =48
4144 22:55:28.833420 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =28
4145 22:55:28.836357 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44
4146 22:55:28.836440
4147 22:55:28.836504
4148 22:55:28.846672 [DQSOSCAuto] RK0, (LSB)MR18= 0x4826, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 396 ps
4149 22:55:28.846755 CH0 RK0: MR19=808, MR18=4826
4150 22:55:28.853248 CH0_RK0: MR19=0x808, MR18=0x4826, DQSOSC=396, MR23=63, INC=167, DEC=111
4151 22:55:28.853331
4152 22:55:28.856608 ----->DramcWriteLeveling(PI) begin...
4153 22:55:28.856692 ==
4154 22:55:28.859680 Dram Type= 6, Freq= 0, CH_0, rank 1
4155 22:55:28.866350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4156 22:55:28.866433 ==
4157 22:55:28.869943 Write leveling (Byte 0): 31 => 31
4158 22:55:28.873184 Write leveling (Byte 1): 31 => 31
4159 22:55:28.873266 DramcWriteLeveling(PI) end<-----
4160 22:55:28.876485
4161 22:55:28.876567 ==
4162 22:55:28.879724 Dram Type= 6, Freq= 0, CH_0, rank 1
4163 22:55:28.882997 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4164 22:55:28.883079 ==
4165 22:55:28.886469 [Gating] SW mode calibration
4166 22:55:28.893014 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4167 22:55:28.896203 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4168 22:55:28.902882 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4169 22:55:28.906710 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4170 22:55:28.910179 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4171 22:55:28.916851 0 9 12 | B1->B0 | 3434 3030 | 1 1 | (1 0) (1 0)
4172 22:55:28.919518 0 9 16 | B1->B0 | 2f2f 2424 | 1 0 | (1 1) (0 0)
4173 22:55:28.923218 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4174 22:55:28.930008 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4175 22:55:28.932997 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4176 22:55:28.935948 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4177 22:55:28.942709 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4178 22:55:28.946139 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4179 22:55:28.949527 0 10 12 | B1->B0 | 2323 3b3b | 0 0 | (0 0) (0 0)
4180 22:55:28.956231 0 10 16 | B1->B0 | 3838 4646 | 1 0 | (0 0) (0 0)
4181 22:55:28.959676 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4182 22:55:28.963091 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4183 22:55:28.969470 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4184 22:55:28.972792 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4185 22:55:28.976153 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4186 22:55:28.982583 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4187 22:55:28.985921 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4188 22:55:28.989293 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4189 22:55:28.996001 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4190 22:55:28.999274 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4191 22:55:29.002166 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4192 22:55:29.008996 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4193 22:55:29.012238 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4194 22:55:29.015519 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4195 22:55:29.022183 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4196 22:55:29.025824 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4197 22:55:29.028831 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4198 22:55:29.035156 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4199 22:55:29.038716 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4200 22:55:29.042085 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4201 22:55:29.048857 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4202 22:55:29.052575 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4203 22:55:29.055342 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4204 22:55:29.058406 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4205 22:55:29.062250 Total UI for P1: 0, mck2ui 16
4206 22:55:29.065102 best dqsien dly found for B0: ( 0, 13, 12)
4207 22:55:29.071946 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4208 22:55:29.075177 Total UI for P1: 0, mck2ui 16
4209 22:55:29.079080 best dqsien dly found for B1: ( 0, 13, 16)
4210 22:55:29.082092 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4211 22:55:29.085578 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4212 22:55:29.085661
4213 22:55:29.088423 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4214 22:55:29.092428 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4215 22:55:29.095712 [Gating] SW calibration Done
4216 22:55:29.095794 ==
4217 22:55:29.098643 Dram Type= 6, Freq= 0, CH_0, rank 1
4218 22:55:29.101898 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4219 22:55:29.101981 ==
4220 22:55:29.104956 RX Vref Scan: 0
4221 22:55:29.105038
4222 22:55:29.108373 RX Vref 0 -> 0, step: 1
4223 22:55:29.108456
4224 22:55:29.108521 RX Delay -230 -> 252, step: 16
4225 22:55:29.115011 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4226 22:55:29.118344 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4227 22:55:29.121995 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4228 22:55:29.125034 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4229 22:55:29.131809 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4230 22:55:29.134914 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4231 22:55:29.138212 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4232 22:55:29.142034 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4233 22:55:29.144751 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4234 22:55:29.151383 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4235 22:55:29.154763 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4236 22:55:29.158226 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4237 22:55:29.161461 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4238 22:55:29.168365 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4239 22:55:29.171418 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4240 22:55:29.174971 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4241 22:55:29.175054 ==
4242 22:55:29.178112 Dram Type= 6, Freq= 0, CH_0, rank 1
4243 22:55:29.181569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4244 22:55:29.184679 ==
4245 22:55:29.184762 DQS Delay:
4246 22:55:29.184827 DQS0 = 0, DQS1 = 0
4247 22:55:29.188278 DQM Delay:
4248 22:55:29.188361 DQM0 = 40, DQM1 = 33
4249 22:55:29.191607 DQ Delay:
4250 22:55:29.194440 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4251 22:55:29.194523 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4252 22:55:29.197927 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =25
4253 22:55:29.201613 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =41
4254 22:55:29.204345
4255 22:55:29.204428
4256 22:55:29.204492 ==
4257 22:55:29.208074 Dram Type= 6, Freq= 0, CH_0, rank 1
4258 22:55:29.211250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4259 22:55:29.211366 ==
4260 22:55:29.211448
4261 22:55:29.211509
4262 22:55:29.214253 TX Vref Scan disable
4263 22:55:29.214365 == TX Byte 0 ==
4264 22:55:29.221167 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4265 22:55:29.224547 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4266 22:55:29.224630 == TX Byte 1 ==
4267 22:55:29.231201 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4268 22:55:29.234477 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4269 22:55:29.234589 ==
4270 22:55:29.237853 Dram Type= 6, Freq= 0, CH_0, rank 1
4271 22:55:29.241169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4272 22:55:29.241282 ==
4273 22:55:29.241348
4274 22:55:29.241408
4275 22:55:29.244308 TX Vref Scan disable
4276 22:55:29.247488 == TX Byte 0 ==
4277 22:55:29.250993 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4278 22:55:29.254192 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4279 22:55:29.257419 == TX Byte 1 ==
4280 22:55:29.260774 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4281 22:55:29.264124 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4282 22:55:29.264235
4283 22:55:29.267802 [DATLAT]
4284 22:55:29.267913 Freq=600, CH0 RK1
4285 22:55:29.267978
4286 22:55:29.270999 DATLAT Default: 0x9
4287 22:55:29.271082 0, 0xFFFF, sum = 0
4288 22:55:29.274340 1, 0xFFFF, sum = 0
4289 22:55:29.274452 2, 0xFFFF, sum = 0
4290 22:55:29.277643 3, 0xFFFF, sum = 0
4291 22:55:29.277749 4, 0xFFFF, sum = 0
4292 22:55:29.280789 5, 0xFFFF, sum = 0
4293 22:55:29.280897 6, 0xFFFF, sum = 0
4294 22:55:29.284457 7, 0xFFFF, sum = 0
4295 22:55:29.284536 8, 0x0, sum = 1
4296 22:55:29.287615 9, 0x0, sum = 2
4297 22:55:29.287688 10, 0x0, sum = 3
4298 22:55:29.290837 11, 0x0, sum = 4
4299 22:55:29.290915 best_step = 9
4300 22:55:29.290984
4301 22:55:29.291044 ==
4302 22:55:29.293940 Dram Type= 6, Freq= 0, CH_0, rank 1
4303 22:55:29.301370 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4304 22:55:29.301479 ==
4305 22:55:29.301570 RX Vref Scan: 0
4306 22:55:29.301667
4307 22:55:29.304600 RX Vref 0 -> 0, step: 1
4308 22:55:29.304674
4309 22:55:29.307431 RX Delay -179 -> 252, step: 8
4310 22:55:29.311510 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4311 22:55:29.317463 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4312 22:55:29.320671 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4313 22:55:29.324003 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4314 22:55:29.327303 iDelay=205, Bit 4, Center 40 (-107 ~ 188) 296
4315 22:55:29.330846 iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304
4316 22:55:29.337390 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4317 22:55:29.340555 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4318 22:55:29.344553 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4319 22:55:29.347940 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4320 22:55:29.354227 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4321 22:55:29.357776 iDelay=205, Bit 11, Center 24 (-123 ~ 172) 296
4322 22:55:29.361100 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4323 22:55:29.363924 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4324 22:55:29.367766 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4325 22:55:29.374099 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4326 22:55:29.374210 ==
4327 22:55:29.377398 Dram Type= 6, Freq= 0, CH_0, rank 1
4328 22:55:29.380619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4329 22:55:29.380722 ==
4330 22:55:29.380784 DQS Delay:
4331 22:55:29.383872 DQS0 = 0, DQS1 = 0
4332 22:55:29.383944 DQM Delay:
4333 22:55:29.387098 DQM0 = 40, DQM1 = 33
4334 22:55:29.387250 DQ Delay:
4335 22:55:29.390592 DQ0 =40, DQ1 =40, DQ2 =36, DQ3 =40
4336 22:55:29.394263 DQ4 =40, DQ5 =28, DQ6 =48, DQ7 =48
4337 22:55:29.397135 DQ8 =24, DQ9 =24, DQ10 =32, DQ11 =24
4338 22:55:29.400960 DQ12 =36, DQ13 =40, DQ14 =44, DQ15 =40
4339 22:55:29.401065
4340 22:55:29.401155
4341 22:55:29.410836 [DQSOSCAuto] RK1, (LSB)MR18= 0x4b2c, (MSB)MR19= 0x808, tDQSOscB0 = 401 ps tDQSOscB1 = 395 ps
4342 22:55:29.410941 CH0 RK1: MR19=808, MR18=4B2C
4343 22:55:29.417640 CH0_RK1: MR19=0x808, MR18=0x4B2C, DQSOSC=395, MR23=63, INC=168, DEC=112
4344 22:55:29.420434 [RxdqsGatingPostProcess] freq 600
4345 22:55:29.427599 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4346 22:55:29.430838 Pre-setting of DQS Precalculation
4347 22:55:29.433725 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4348 22:55:29.433835 ==
4349 22:55:29.437104 Dram Type= 6, Freq= 0, CH_1, rank 0
4350 22:55:29.440551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4351 22:55:29.440628 ==
4352 22:55:29.447901 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4353 22:55:29.453961 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4354 22:55:29.457585 [CA 0] Center 35 (5~65) winsize 61
4355 22:55:29.460373 [CA 1] Center 35 (5~66) winsize 62
4356 22:55:29.464113 [CA 2] Center 34 (4~65) winsize 62
4357 22:55:29.467307 [CA 3] Center 33 (3~64) winsize 62
4358 22:55:29.470653 [CA 4] Center 34 (3~65) winsize 63
4359 22:55:29.473883 [CA 5] Center 33 (3~64) winsize 62
4360 22:55:29.473980
4361 22:55:29.477132 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4362 22:55:29.477206
4363 22:55:29.481224 [CATrainingPosCal] consider 1 rank data
4364 22:55:29.483727 u2DelayCellTimex100 = 270/100 ps
4365 22:55:29.487558 CA0 delay=35 (5~65),Diff = 2 PI (19 cell)
4366 22:55:29.490524 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4367 22:55:29.493872 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4368 22:55:29.496920 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4369 22:55:29.500645 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4370 22:55:29.507041 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4371 22:55:29.507125
4372 22:55:29.510599 CA PerBit enable=1, Macro0, CA PI delay=33
4373 22:55:29.510674
4374 22:55:29.513817 [CBTSetCACLKResult] CA Dly = 33
4375 22:55:29.513896 CS Dly: 5 (0~36)
4376 22:55:29.513959 ==
4377 22:55:29.517275 Dram Type= 6, Freq= 0, CH_1, rank 1
4378 22:55:29.520469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4379 22:55:29.523602 ==
4380 22:55:29.526928 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4381 22:55:29.533712 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4382 22:55:29.536582 [CA 0] Center 35 (5~66) winsize 62
4383 22:55:29.540367 [CA 1] Center 35 (5~66) winsize 62
4384 22:55:29.543881 [CA 2] Center 34 (4~65) winsize 62
4385 22:55:29.547111 [CA 3] Center 33 (3~64) winsize 62
4386 22:55:29.550342 [CA 4] Center 34 (4~65) winsize 62
4387 22:55:29.553760 [CA 5] Center 33 (3~64) winsize 62
4388 22:55:29.553859
4389 22:55:29.557200 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4390 22:55:29.557273
4391 22:55:29.559879 [CATrainingPosCal] consider 2 rank data
4392 22:55:29.563679 u2DelayCellTimex100 = 270/100 ps
4393 22:55:29.567147 CA0 delay=35 (5~65),Diff = 2 PI (19 cell)
4394 22:55:29.569786 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4395 22:55:29.573652 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4396 22:55:29.580347 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4397 22:55:29.583277 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4398 22:55:29.586775 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4399 22:55:29.586875
4400 22:55:29.590096 CA PerBit enable=1, Macro0, CA PI delay=33
4401 22:55:29.590187
4402 22:55:29.593311 [CBTSetCACLKResult] CA Dly = 33
4403 22:55:29.593385 CS Dly: 5 (0~36)
4404 22:55:29.593449
4405 22:55:29.596721 ----->DramcWriteLeveling(PI) begin...
4406 22:55:29.599749 ==
4407 22:55:29.599823 Dram Type= 6, Freq= 0, CH_1, rank 0
4408 22:55:29.607054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4409 22:55:29.607164 ==
4410 22:55:29.609679 Write leveling (Byte 0): 28 => 28
4411 22:55:29.613288 Write leveling (Byte 1): 31 => 31
4412 22:55:29.616432 DramcWriteLeveling(PI) end<-----
4413 22:55:29.616514
4414 22:55:29.616577 ==
4415 22:55:29.619796 Dram Type= 6, Freq= 0, CH_1, rank 0
4416 22:55:29.623039 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4417 22:55:29.623141 ==
4418 22:55:29.626743 [Gating] SW mode calibration
4419 22:55:29.633029 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4420 22:55:29.636308 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4421 22:55:29.643058 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4422 22:55:29.646514 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4423 22:55:29.649946 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4424 22:55:29.656434 0 9 12 | B1->B0 | 3232 3333 | 1 0 | (1 1) (0 0)
4425 22:55:29.659837 0 9 16 | B1->B0 | 2f2f 2c2c | 0 0 | (0 0) (0 0)
4426 22:55:29.662892 0 9 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4427 22:55:29.669635 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4428 22:55:29.673064 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4429 22:55:29.676332 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4430 22:55:29.683185 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4431 22:55:29.686144 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4432 22:55:29.689476 0 10 12 | B1->B0 | 2424 2525 | 0 0 | (0 0) (0 0)
4433 22:55:29.696071 0 10 16 | B1->B0 | 3e3e 4545 | 0 0 | (0 0) (0 0)
4434 22:55:29.699956 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4435 22:55:29.702656 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4436 22:55:29.709639 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4437 22:55:29.712994 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4438 22:55:29.716333 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4439 22:55:29.722756 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4440 22:55:29.726124 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4441 22:55:29.730004 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4442 22:55:29.735906 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 22:55:29.739889 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4444 22:55:29.742943 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4445 22:55:29.746745 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4446 22:55:29.752743 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4447 22:55:29.756100 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4448 22:55:29.759956 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4449 22:55:29.766018 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4450 22:55:29.769912 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4451 22:55:29.772901 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4452 22:55:29.779691 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4453 22:55:29.782559 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4454 22:55:29.785939 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4455 22:55:29.792745 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4456 22:55:29.795831 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4457 22:55:29.799100 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4458 22:55:29.806185 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4459 22:55:29.806260 Total UI for P1: 0, mck2ui 16
4460 22:55:29.812559 best dqsien dly found for B0: ( 0, 13, 16)
4461 22:55:29.812634 Total UI for P1: 0, mck2ui 16
4462 22:55:29.819390 best dqsien dly found for B1: ( 0, 13, 16)
4463 22:55:29.822582 best DQS0 dly(MCK, UI, PI) = (0, 13, 16)
4464 22:55:29.825680 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4465 22:55:29.825755
4466 22:55:29.829068 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 16)
4467 22:55:29.832668 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4468 22:55:29.835783 [Gating] SW calibration Done
4469 22:55:29.835880 ==
4470 22:55:29.839086 Dram Type= 6, Freq= 0, CH_1, rank 0
4471 22:55:29.842889 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4472 22:55:29.842991 ==
4473 22:55:29.845664 RX Vref Scan: 0
4474 22:55:29.845761
4475 22:55:29.845854 RX Vref 0 -> 0, step: 1
4476 22:55:29.845941
4477 22:55:29.848961 RX Delay -230 -> 252, step: 16
4478 22:55:29.855498 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4479 22:55:29.858791 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4480 22:55:29.862827 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4481 22:55:29.865945 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4482 22:55:29.869087 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4483 22:55:29.875632 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4484 22:55:29.878919 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4485 22:55:29.882089 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4486 22:55:29.885593 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4487 22:55:29.892444 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4488 22:55:29.895649 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4489 22:55:29.899167 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4490 22:55:29.902689 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4491 22:55:29.908757 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4492 22:55:29.912140 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4493 22:55:29.915603 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4494 22:55:29.915677 ==
4495 22:55:29.919065 Dram Type= 6, Freq= 0, CH_1, rank 0
4496 22:55:29.922361 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4497 22:55:29.922458 ==
4498 22:55:29.925676 DQS Delay:
4499 22:55:29.925779 DQS0 = 0, DQS1 = 0
4500 22:55:29.929213 DQM Delay:
4501 22:55:29.929313 DQM0 = 44, DQM1 = 37
4502 22:55:29.929402 DQ Delay:
4503 22:55:29.932494 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4504 22:55:29.935556 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4505 22:55:29.939265 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4506 22:55:29.942596 DQ12 =49, DQ13 =41, DQ14 =41, DQ15 =41
4507 22:55:29.942698
4508 22:55:29.942799
4509 22:55:29.945482 ==
4510 22:55:29.945582 Dram Type= 6, Freq= 0, CH_1, rank 0
4511 22:55:29.952041 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4512 22:55:29.952118 ==
4513 22:55:29.952181
4514 22:55:29.952241
4515 22:55:29.955326 TX Vref Scan disable
4516 22:55:29.955465 == TX Byte 0 ==
4517 22:55:29.958695 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4518 22:55:29.965522 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4519 22:55:29.965624 == TX Byte 1 ==
4520 22:55:29.972007 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4521 22:55:29.975274 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4522 22:55:29.975417 ==
4523 22:55:29.978601 Dram Type= 6, Freq= 0, CH_1, rank 0
4524 22:55:29.981989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4525 22:55:29.982097 ==
4526 22:55:29.982187
4527 22:55:29.982281
4528 22:55:29.985093 TX Vref Scan disable
4529 22:55:29.988450 == TX Byte 0 ==
4530 22:55:29.991904 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4531 22:55:29.994780 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4532 22:55:29.998598 == TX Byte 1 ==
4533 22:55:30.001878 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4534 22:55:30.005315 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4535 22:55:30.005421
4536 22:55:30.008447 [DATLAT]
4537 22:55:30.008521 Freq=600, CH1 RK0
4538 22:55:30.008601
4539 22:55:30.011604 DATLAT Default: 0x9
4540 22:55:30.011676 0, 0xFFFF, sum = 0
4541 22:55:30.015263 1, 0xFFFF, sum = 0
4542 22:55:30.015389 2, 0xFFFF, sum = 0
4543 22:55:30.018374 3, 0xFFFF, sum = 0
4544 22:55:30.018474 4, 0xFFFF, sum = 0
4545 22:55:30.021640 5, 0xFFFF, sum = 0
4546 22:55:30.021741 6, 0xFFFF, sum = 0
4547 22:55:30.025372 7, 0xFFFF, sum = 0
4548 22:55:30.025464 8, 0x0, sum = 1
4549 22:55:30.028411 9, 0x0, sum = 2
4550 22:55:30.028489 10, 0x0, sum = 3
4551 22:55:30.031656 11, 0x0, sum = 4
4552 22:55:30.031741 best_step = 9
4553 22:55:30.031805
4554 22:55:30.031862 ==
4555 22:55:30.035441 Dram Type= 6, Freq= 0, CH_1, rank 0
4556 22:55:30.038332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4557 22:55:30.041616 ==
4558 22:55:30.041721 RX Vref Scan: 1
4559 22:55:30.041811
4560 22:55:30.045250 RX Vref 0 -> 0, step: 1
4561 22:55:30.045347
4562 22:55:30.048324 RX Delay -179 -> 252, step: 8
4563 22:55:30.048416
4564 22:55:30.051444 Set Vref, RX VrefLevel [Byte0]: 55
4565 22:55:30.054802 [Byte1]: 51
4566 22:55:30.054873
4567 22:55:30.058246 Final RX Vref Byte 0 = 55 to rank0
4568 22:55:30.061699 Final RX Vref Byte 1 = 51 to rank0
4569 22:55:30.064644 Final RX Vref Byte 0 = 55 to rank1
4570 22:55:30.068515 Final RX Vref Byte 1 = 51 to rank1==
4571 22:55:30.071480 Dram Type= 6, Freq= 0, CH_1, rank 0
4572 22:55:30.074727 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4573 22:55:30.074825 ==
4574 22:55:30.074914 DQS Delay:
4575 22:55:30.078212 DQS0 = 0, DQS1 = 0
4576 22:55:30.078307 DQM Delay:
4577 22:55:30.081896 DQM0 = 40, DQM1 = 32
4578 22:55:30.081972 DQ Delay:
4579 22:55:30.084833 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =40
4580 22:55:30.088141 DQ4 =40, DQ5 =48, DQ6 =52, DQ7 =36
4581 22:55:30.091798 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =24
4582 22:55:30.094732 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =40
4583 22:55:30.094804
4584 22:55:30.094865
4585 22:55:30.104610 [DQSOSCAuto] RK0, (LSB)MR18= 0x3f06, (MSB)MR19= 0x808, tDQSOscB0 = 408 ps tDQSOscB1 = 397 ps
4586 22:55:30.104687 CH1 RK0: MR19=808, MR18=3F06
4587 22:55:30.111258 CH1_RK0: MR19=0x808, MR18=0x3F06, DQSOSC=397, MR23=63, INC=166, DEC=110
4588 22:55:30.111332
4589 22:55:30.115277 ----->DramcWriteLeveling(PI) begin...
4590 22:55:30.115409 ==
4591 22:55:30.118130 Dram Type= 6, Freq= 0, CH_1, rank 1
4592 22:55:30.124630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4593 22:55:30.124704 ==
4594 22:55:30.128491 Write leveling (Byte 0): 29 => 29
4595 22:55:30.131267 Write leveling (Byte 1): 29 => 29
4596 22:55:30.131386 DramcWriteLeveling(PI) end<-----
4597 22:55:30.131468
4598 22:55:30.134512 ==
4599 22:55:30.138367 Dram Type= 6, Freq= 0, CH_1, rank 1
4600 22:55:30.141836 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4601 22:55:30.141939 ==
4602 22:55:30.144386 [Gating] SW mode calibration
4603 22:55:30.151059 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4604 22:55:30.154365 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4605 22:55:30.161419 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4606 22:55:30.164267 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4607 22:55:30.167588 0 9 8 | B1->B0 | 3535 3434 | 0 0 | (0 0) (0 0)
4608 22:55:30.174636 0 9 12 | B1->B0 | 3131 2a2a | 0 0 | (0 1) (0 1)
4609 22:55:30.178170 0 9 16 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
4610 22:55:30.181251 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4611 22:55:30.187984 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4612 22:55:30.191317 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4613 22:55:30.194363 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4614 22:55:30.201374 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4615 22:55:30.204211 0 10 8 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
4616 22:55:30.207602 0 10 12 | B1->B0 | 3737 3e3e | 0 0 | (1 1) (0 0)
4617 22:55:30.214248 0 10 16 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
4618 22:55:30.217759 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4619 22:55:30.221157 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4620 22:55:30.227587 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4621 22:55:30.230723 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4622 22:55:30.234354 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4623 22:55:30.241042 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4624 22:55:30.244292 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4625 22:55:30.247436 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4626 22:55:30.250580 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4627 22:55:30.257444 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4628 22:55:30.261099 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4629 22:55:30.264437 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4630 22:55:30.270628 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4631 22:55:30.273952 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4632 22:55:30.277361 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4633 22:55:30.284191 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4634 22:55:30.287206 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4635 22:55:30.290937 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4636 22:55:30.297546 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4637 22:55:30.300771 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4638 22:55:30.303839 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4639 22:55:30.310586 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4640 22:55:30.314411 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4641 22:55:30.317114 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4642 22:55:30.320711 Total UI for P1: 0, mck2ui 16
4643 22:55:30.323751 best dqsien dly found for B0: ( 0, 13, 12)
4644 22:55:30.327225 Total UI for P1: 0, mck2ui 16
4645 22:55:30.330477 best dqsien dly found for B1: ( 0, 13, 14)
4646 22:55:30.334278 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4647 22:55:30.337168 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4648 22:55:30.337283
4649 22:55:30.344002 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4650 22:55:30.347252 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4651 22:55:30.350499 [Gating] SW calibration Done
4652 22:55:30.350657 ==
4653 22:55:30.353483 Dram Type= 6, Freq= 0, CH_1, rank 1
4654 22:55:30.356802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4655 22:55:30.356984 ==
4656 22:55:30.357163 RX Vref Scan: 0
4657 22:55:30.357331
4658 22:55:30.360380 RX Vref 0 -> 0, step: 1
4659 22:55:30.360588
4660 22:55:30.363370 RX Delay -230 -> 252, step: 16
4661 22:55:30.367066 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4662 22:55:30.373590 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4663 22:55:30.376928 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4664 22:55:30.380396 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4665 22:55:30.383664 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4666 22:55:30.386856 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4667 22:55:30.393618 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4668 22:55:30.397367 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4669 22:55:30.400240 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4670 22:55:30.403572 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4671 22:55:30.407084 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4672 22:55:30.414262 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4673 22:55:30.417333 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4674 22:55:30.421067 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4675 22:55:30.424148 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4676 22:55:30.431093 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4677 22:55:30.431712 ==
4678 22:55:30.434032 Dram Type= 6, Freq= 0, CH_1, rank 1
4679 22:55:30.437288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4680 22:55:30.437766 ==
4681 22:55:30.438138 DQS Delay:
4682 22:55:30.440718 DQS0 = 0, DQS1 = 0
4683 22:55:30.441189 DQM Delay:
4684 22:55:30.444032 DQM0 = 39, DQM1 = 35
4685 22:55:30.444502 DQ Delay:
4686 22:55:30.447389 DQ0 =41, DQ1 =33, DQ2 =25, DQ3 =41
4687 22:55:30.451070 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =33
4688 22:55:30.454365 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =25
4689 22:55:30.457232 DQ12 =41, DQ13 =49, DQ14 =41, DQ15 =41
4690 22:55:30.457709
4691 22:55:30.458084
4692 22:55:30.458430 ==
4693 22:55:30.460834 Dram Type= 6, Freq= 0, CH_1, rank 1
4694 22:55:30.464096 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4695 22:55:30.464573 ==
4696 22:55:30.467308
4697 22:55:30.467810
4698 22:55:30.468181 TX Vref Scan disable
4699 22:55:30.470473 == TX Byte 0 ==
4700 22:55:30.473969 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4701 22:55:30.476990 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4702 22:55:30.480506 == TX Byte 1 ==
4703 22:55:30.483790 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4704 22:55:30.487242 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4705 22:55:30.487860 ==
4706 22:55:30.491488 Dram Type= 6, Freq= 0, CH_1, rank 1
4707 22:55:30.497477 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4708 22:55:30.498048 ==
4709 22:55:30.498424
4710 22:55:30.498770
4711 22:55:30.499102 TX Vref Scan disable
4712 22:55:30.502086 == TX Byte 0 ==
4713 22:55:30.505028 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4714 22:55:30.512227 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4715 22:55:30.512793 == TX Byte 1 ==
4716 22:55:30.514996 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4717 22:55:30.521752 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4718 22:55:30.522316
4719 22:55:30.522687 [DATLAT]
4720 22:55:30.523031 Freq=600, CH1 RK1
4721 22:55:30.523386
4722 22:55:30.525382 DATLAT Default: 0x9
4723 22:55:30.525945 0, 0xFFFF, sum = 0
4724 22:55:30.527991 1, 0xFFFF, sum = 0
4725 22:55:30.528471 2, 0xFFFF, sum = 0
4726 22:55:30.531957 3, 0xFFFF, sum = 0
4727 22:55:30.535503 4, 0xFFFF, sum = 0
4728 22:55:30.536082 5, 0xFFFF, sum = 0
4729 22:55:30.538458 6, 0xFFFF, sum = 0
4730 22:55:30.538941 7, 0xFFFF, sum = 0
4731 22:55:30.541498 8, 0x0, sum = 1
4732 22:55:30.542098 9, 0x0, sum = 2
4733 22:55:30.542486 10, 0x0, sum = 3
4734 22:55:30.545009 11, 0x0, sum = 4
4735 22:55:30.545667 best_step = 9
4736 22:55:30.546047
4737 22:55:30.546398 ==
4738 22:55:30.548092 Dram Type= 6, Freq= 0, CH_1, rank 1
4739 22:55:30.555525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4740 22:55:30.556089 ==
4741 22:55:30.556468 RX Vref Scan: 0
4742 22:55:30.556817
4743 22:55:30.558631 RX Vref 0 -> 0, step: 1
4744 22:55:30.559279
4745 22:55:30.561388 RX Delay -179 -> 252, step: 8
4746 22:55:30.564571 iDelay=205, Bit 0, Center 44 (-107 ~ 196) 304
4747 22:55:30.571623 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4748 22:55:30.574919 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4749 22:55:30.577894 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4750 22:55:30.581245 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4751 22:55:30.585012 iDelay=205, Bit 5, Center 52 (-99 ~ 204) 304
4752 22:55:30.591713 iDelay=205, Bit 6, Center 52 (-99 ~ 204) 304
4753 22:55:30.594844 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4754 22:55:30.598135 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4755 22:55:30.602138 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4756 22:55:30.608158 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4757 22:55:30.611704 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4758 22:55:30.615006 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4759 22:55:30.617960 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4760 22:55:30.625090 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4761 22:55:30.628126 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4762 22:55:30.628605 ==
4763 22:55:30.631889 Dram Type= 6, Freq= 0, CH_1, rank 1
4764 22:55:30.635089 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4765 22:55:30.635618 ==
4766 22:55:30.637962 DQS Delay:
4767 22:55:30.638430 DQS0 = 0, DQS1 = 0
4768 22:55:30.638802 DQM Delay:
4769 22:55:30.641310 DQM0 = 39, DQM1 = 33
4770 22:55:30.641781 DQ Delay:
4771 22:55:30.644409 DQ0 =44, DQ1 =32, DQ2 =24, DQ3 =36
4772 22:55:30.647920 DQ4 =40, DQ5 =52, DQ6 =52, DQ7 =32
4773 22:55:30.651313 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =24
4774 22:55:30.654479 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4775 22:55:30.655048
4776 22:55:30.655476
4777 22:55:30.664537 [DQSOSCAuto] RK1, (LSB)MR18= 0x3c4b, (MSB)MR19= 0x808, tDQSOscB0 = 395 ps tDQSOscB1 = 398 ps
4778 22:55:30.665096 CH1 RK1: MR19=808, MR18=3C4B
4779 22:55:30.671302 CH1_RK1: MR19=0x808, MR18=0x3C4B, DQSOSC=395, MR23=63, INC=168, DEC=112
4780 22:55:30.674357 [RxdqsGatingPostProcess] freq 600
4781 22:55:30.681141 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4782 22:55:30.684577 Pre-setting of DQS Precalculation
4783 22:55:30.687913 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4784 22:55:30.694614 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4785 22:55:30.704445 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4786 22:55:30.705011
4787 22:55:30.705383
4788 22:55:30.705731 [Calibration Summary] 1200 Mbps
4789 22:55:30.707626 CH 0, Rank 0
4790 22:55:30.708098 SW Impedance : PASS
4791 22:55:30.711514 DUTY Scan : NO K
4792 22:55:30.714682 ZQ Calibration : PASS
4793 22:55:30.715112 Jitter Meter : NO K
4794 22:55:30.717625 CBT Training : PASS
4795 22:55:30.721825 Write leveling : PASS
4796 22:55:30.722390 RX DQS gating : PASS
4797 22:55:30.724273 RX DQ/DQS(RDDQC) : PASS
4798 22:55:30.727715 TX DQ/DQS : PASS
4799 22:55:30.728191 RX DATLAT : PASS
4800 22:55:30.731318 RX DQ/DQS(Engine): PASS
4801 22:55:30.734646 TX OE : NO K
4802 22:55:30.735212 All Pass.
4803 22:55:30.735679
4804 22:55:30.736001 CH 0, Rank 1
4805 22:55:30.738020 SW Impedance : PASS
4806 22:55:30.740913 DUTY Scan : NO K
4807 22:55:30.741343 ZQ Calibration : PASS
4808 22:55:30.745094 Jitter Meter : NO K
4809 22:55:30.748244 CBT Training : PASS
4810 22:55:30.748766 Write leveling : PASS
4811 22:55:30.750975 RX DQS gating : PASS
4812 22:55:30.751539 RX DQ/DQS(RDDQC) : PASS
4813 22:55:30.754601 TX DQ/DQS : PASS
4814 22:55:30.757607 RX DATLAT : PASS
4815 22:55:30.758034 RX DQ/DQS(Engine): PASS
4816 22:55:30.761236 TX OE : NO K
4817 22:55:30.761665 All Pass.
4818 22:55:30.762002
4819 22:55:30.764484 CH 1, Rank 0
4820 22:55:30.764913 SW Impedance : PASS
4821 22:55:30.767683 DUTY Scan : NO K
4822 22:55:30.770852 ZQ Calibration : PASS
4823 22:55:30.771281 Jitter Meter : NO K
4824 22:55:30.774170 CBT Training : PASS
4825 22:55:30.777527 Write leveling : PASS
4826 22:55:30.778052 RX DQS gating : PASS
4827 22:55:30.781272 RX DQ/DQS(RDDQC) : PASS
4828 22:55:30.783890 TX DQ/DQS : PASS
4829 22:55:30.784321 RX DATLAT : PASS
4830 22:55:30.787691 RX DQ/DQS(Engine): PASS
4831 22:55:30.790636 TX OE : NO K
4832 22:55:30.791117 All Pass.
4833 22:55:30.791687
4834 22:55:30.792082 CH 1, Rank 1
4835 22:55:30.794398 SW Impedance : PASS
4836 22:55:30.797577 DUTY Scan : NO K
4837 22:55:30.798000 ZQ Calibration : PASS
4838 22:55:30.800852 Jitter Meter : NO K
4839 22:55:30.804688 CBT Training : PASS
4840 22:55:30.805227 Write leveling : PASS
4841 22:55:30.807666 RX DQS gating : PASS
4842 22:55:30.808093 RX DQ/DQS(RDDQC) : PASS
4843 22:55:30.810579 TX DQ/DQS : PASS
4844 22:55:30.814442 RX DATLAT : PASS
4845 22:55:30.814967 RX DQ/DQS(Engine): PASS
4846 22:55:30.817003 TX OE : NO K
4847 22:55:30.817435 All Pass.
4848 22:55:30.817771
4849 22:55:30.820380 DramC Write-DBI off
4850 22:55:30.823952 PER_BANK_REFRESH: Hybrid Mode
4851 22:55:30.824380 TX_TRACKING: ON
4852 22:55:30.834464 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4853 22:55:30.837209 [FAST_K] Save calibration result to emmc
4854 22:55:30.841100 dramc_set_vcore_voltage set vcore to 662500
4855 22:55:30.844072 Read voltage for 933, 3
4856 22:55:30.844544 Vio18 = 0
4857 22:55:30.844912 Vcore = 662500
4858 22:55:30.847130 Vdram = 0
4859 22:55:30.847732 Vddq = 0
4860 22:55:30.848109 Vmddr = 0
4861 22:55:30.853884 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4862 22:55:30.857599 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4863 22:55:30.860194 MEM_TYPE=3, freq_sel=17
4864 22:55:30.864018 sv_algorithm_assistance_LP4_1600
4865 22:55:30.867071 ============ PULL DRAM RESETB DOWN ============
4866 22:55:30.873806 ========== PULL DRAM RESETB DOWN end =========
4867 22:55:30.876726 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4868 22:55:30.879887 ===================================
4869 22:55:30.883324 LPDDR4 DRAM CONFIGURATION
4870 22:55:30.886769 ===================================
4871 22:55:30.887243 EX_ROW_EN[0] = 0x0
4872 22:55:30.889994 EX_ROW_EN[1] = 0x0
4873 22:55:30.890520 LP4Y_EN = 0x0
4874 22:55:30.893418 WORK_FSP = 0x0
4875 22:55:30.893876 WL = 0x3
4876 22:55:30.896858 RL = 0x3
4877 22:55:30.897283 BL = 0x2
4878 22:55:30.899966 RPST = 0x0
4879 22:55:30.900386 RD_PRE = 0x0
4880 22:55:30.903317 WR_PRE = 0x1
4881 22:55:30.906626 WR_PST = 0x0
4882 22:55:30.907047 DBI_WR = 0x0
4883 22:55:30.909822 DBI_RD = 0x0
4884 22:55:30.910245 OTF = 0x1
4885 22:55:30.913495 ===================================
4886 22:55:30.916792 ===================================
4887 22:55:30.917219 ANA top config
4888 22:55:30.920203 ===================================
4889 22:55:30.923010 DLL_ASYNC_EN = 0
4890 22:55:30.926115 ALL_SLAVE_EN = 1
4891 22:55:30.929956 NEW_RANK_MODE = 1
4892 22:55:30.932939 DLL_IDLE_MODE = 1
4893 22:55:30.933362 LP45_APHY_COMB_EN = 1
4894 22:55:30.936330 TX_ODT_DIS = 1
4895 22:55:30.939630 NEW_8X_MODE = 1
4896 22:55:30.943101 ===================================
4897 22:55:30.946696 ===================================
4898 22:55:30.949867 data_rate = 1866
4899 22:55:30.953222 CKR = 1
4900 22:55:30.953644 DQ_P2S_RATIO = 8
4901 22:55:30.956396 ===================================
4902 22:55:30.959878 CA_P2S_RATIO = 8
4903 22:55:30.962791 DQ_CA_OPEN = 0
4904 22:55:30.966482 DQ_SEMI_OPEN = 0
4905 22:55:30.970222 CA_SEMI_OPEN = 0
4906 22:55:30.973262 CA_FULL_RATE = 0
4907 22:55:30.973691 DQ_CKDIV4_EN = 1
4908 22:55:30.976430 CA_CKDIV4_EN = 1
4909 22:55:30.979823 CA_PREDIV_EN = 0
4910 22:55:30.983246 PH8_DLY = 0
4911 22:55:30.986607 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4912 22:55:30.989758 DQ_AAMCK_DIV = 4
4913 22:55:30.990303 CA_AAMCK_DIV = 4
4914 22:55:30.993075 CA_ADMCK_DIV = 4
4915 22:55:30.996212 DQ_TRACK_CA_EN = 0
4916 22:55:30.999534 CA_PICK = 933
4917 22:55:31.003105 CA_MCKIO = 933
4918 22:55:31.006488 MCKIO_SEMI = 0
4919 22:55:31.010069 PLL_FREQ = 3732
4920 22:55:31.010599 DQ_UI_PI_RATIO = 32
4921 22:55:31.013352 CA_UI_PI_RATIO = 0
4922 22:55:31.016382 ===================================
4923 22:55:31.019561 ===================================
4924 22:55:31.022962 memory_type:LPDDR4
4925 22:55:31.026396 GP_NUM : 10
4926 22:55:31.026821 SRAM_EN : 1
4927 22:55:31.029835 MD32_EN : 0
4928 22:55:31.033470 ===================================
4929 22:55:31.033992 [ANA_INIT] >>>>>>>>>>>>>>
4930 22:55:31.036808 <<<<<< [CONFIGURE PHASE]: ANA_TX
4931 22:55:31.040169 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4932 22:55:31.043163 ===================================
4933 22:55:31.046019 data_rate = 1866,PCW = 0X8f00
4934 22:55:31.049608 ===================================
4935 22:55:31.053134 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4936 22:55:31.059421 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4937 22:55:31.063294 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4938 22:55:31.070027 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4939 22:55:31.073230 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4940 22:55:31.076146 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4941 22:55:31.079901 [ANA_INIT] flow start
4942 22:55:31.080427 [ANA_INIT] PLL >>>>>>>>
4943 22:55:31.082894 [ANA_INIT] PLL <<<<<<<<
4944 22:55:31.086200 [ANA_INIT] MIDPI >>>>>>>>
4945 22:55:31.086743 [ANA_INIT] MIDPI <<<<<<<<
4946 22:55:31.089714 [ANA_INIT] DLL >>>>>>>>
4947 22:55:31.092465 [ANA_INIT] flow end
4948 22:55:31.096005 ============ LP4 DIFF to SE enter ============
4949 22:55:31.099011 ============ LP4 DIFF to SE exit ============
4950 22:55:31.102880 [ANA_INIT] <<<<<<<<<<<<<
4951 22:55:31.105963 [Flow] Enable top DCM control >>>>>
4952 22:55:31.109093 [Flow] Enable top DCM control <<<<<
4953 22:55:31.112939 Enable DLL master slave shuffle
4954 22:55:31.116134 ==============================================================
4955 22:55:31.119327 Gating Mode config
4956 22:55:31.125938 ==============================================================
4957 22:55:31.126457 Config description:
4958 22:55:31.136051 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4959 22:55:31.142576 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4960 22:55:31.146008 SELPH_MODE 0: By rank 1: By Phase
4961 22:55:31.152416 ==============================================================
4962 22:55:31.155503 GAT_TRACK_EN = 1
4963 22:55:31.158943 RX_GATING_MODE = 2
4964 22:55:31.162350 RX_GATING_TRACK_MODE = 2
4965 22:55:31.165233 SELPH_MODE = 1
4966 22:55:31.168802 PICG_EARLY_EN = 1
4967 22:55:31.172257 VALID_LAT_VALUE = 1
4968 22:55:31.175377 ==============================================================
4969 22:55:31.178898 Enter into Gating configuration >>>>
4970 22:55:31.181491 Exit from Gating configuration <<<<
4971 22:55:31.184950 Enter into DVFS_PRE_config >>>>>
4972 22:55:31.198494 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4973 22:55:31.201652 Exit from DVFS_PRE_config <<<<<
4974 22:55:31.201759 Enter into PICG configuration >>>>
4975 22:55:31.204949 Exit from PICG configuration <<<<
4976 22:55:31.208581 [RX_INPUT] configuration >>>>>
4977 22:55:31.211266 [RX_INPUT] configuration <<<<<
4978 22:55:31.218501 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4979 22:55:31.221282 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4980 22:55:31.228396 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4981 22:55:31.235029 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4982 22:55:31.241521 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4983 22:55:31.247884 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4984 22:55:31.251337 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4985 22:55:31.254784 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4986 22:55:31.258153 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4987 22:55:31.264914 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4988 22:55:31.267800 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4989 22:55:31.271002 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4990 22:55:31.274375 ===================================
4991 22:55:31.277732 LPDDR4 DRAM CONFIGURATION
4992 22:55:31.281632 ===================================
4993 22:55:31.285101 EX_ROW_EN[0] = 0x0
4994 22:55:31.285183 EX_ROW_EN[1] = 0x0
4995 22:55:31.287938 LP4Y_EN = 0x0
4996 22:55:31.288020 WORK_FSP = 0x0
4997 22:55:31.291598 WL = 0x3
4998 22:55:31.291681 RL = 0x3
4999 22:55:31.294435 BL = 0x2
5000 22:55:31.294517 RPST = 0x0
5001 22:55:31.297869 RD_PRE = 0x0
5002 22:55:31.297951 WR_PRE = 0x1
5003 22:55:31.300961 WR_PST = 0x0
5004 22:55:31.301044 DBI_WR = 0x0
5005 22:55:31.304560 DBI_RD = 0x0
5006 22:55:31.304642 OTF = 0x1
5007 22:55:31.307667 ===================================
5008 22:55:31.310876 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5009 22:55:31.318365 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5010 22:55:31.321402 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5011 22:55:31.324443 ===================================
5012 22:55:31.328123 LPDDR4 DRAM CONFIGURATION
5013 22:55:31.331706 ===================================
5014 22:55:31.331789 EX_ROW_EN[0] = 0x10
5015 22:55:31.334508 EX_ROW_EN[1] = 0x0
5016 22:55:31.338111 LP4Y_EN = 0x0
5017 22:55:31.338193 WORK_FSP = 0x0
5018 22:55:31.341170 WL = 0x3
5019 22:55:31.341269 RL = 0x3
5020 22:55:31.344313 BL = 0x2
5021 22:55:31.344397 RPST = 0x0
5022 22:55:31.347632 RD_PRE = 0x0
5023 22:55:31.347715 WR_PRE = 0x1
5024 22:55:31.351257 WR_PST = 0x0
5025 22:55:31.351384 DBI_WR = 0x0
5026 22:55:31.354347 DBI_RD = 0x0
5027 22:55:31.354455 OTF = 0x1
5028 22:55:31.357397 ===================================
5029 22:55:31.364172 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5030 22:55:31.368204 nWR fixed to 30
5031 22:55:31.371993 [ModeRegInit_LP4] CH0 RK0
5032 22:55:31.372093 [ModeRegInit_LP4] CH0 RK1
5033 22:55:31.375278 [ModeRegInit_LP4] CH1 RK0
5034 22:55:31.378521 [ModeRegInit_LP4] CH1 RK1
5035 22:55:31.378599 match AC timing 9
5036 22:55:31.384972 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5037 22:55:31.388624 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5038 22:55:31.391963 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5039 22:55:31.398318 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5040 22:55:31.401830 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5041 22:55:31.401912 ==
5042 22:55:31.404956 Dram Type= 6, Freq= 0, CH_0, rank 0
5043 22:55:31.408678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5044 22:55:31.408765 ==
5045 22:55:31.414868 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5046 22:55:31.421752 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5047 22:55:31.424626 [CA 0] Center 38 (8~69) winsize 62
5048 22:55:31.428096 [CA 1] Center 38 (8~69) winsize 62
5049 22:55:31.431488 [CA 2] Center 35 (5~66) winsize 62
5050 22:55:31.434609 [CA 3] Center 34 (4~65) winsize 62
5051 22:55:31.438256 [CA 4] Center 34 (4~64) winsize 61
5052 22:55:31.441771 [CA 5] Center 34 (4~64) winsize 61
5053 22:55:31.441853
5054 22:55:31.445111 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5055 22:55:31.445194
5056 22:55:31.447945 [CATrainingPosCal] consider 1 rank data
5057 22:55:31.451528 u2DelayCellTimex100 = 270/100 ps
5058 22:55:31.454530 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5059 22:55:31.457810 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5060 22:55:31.461164 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5061 22:55:31.464544 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5062 22:55:31.468066 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5063 22:55:31.474780 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5064 22:55:31.474863
5065 22:55:31.477891 CA PerBit enable=1, Macro0, CA PI delay=34
5066 22:55:31.477973
5067 22:55:31.481451 [CBTSetCACLKResult] CA Dly = 34
5068 22:55:31.481534 CS Dly: 6 (0~37)
5069 22:55:31.481598 ==
5070 22:55:31.484845 Dram Type= 6, Freq= 0, CH_0, rank 1
5071 22:55:31.487806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5072 22:55:31.490884 ==
5073 22:55:31.494740 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5074 22:55:31.500943 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5075 22:55:31.504228 [CA 0] Center 38 (7~69) winsize 63
5076 22:55:31.507647 [CA 1] Center 37 (7~68) winsize 62
5077 22:55:31.511230 [CA 2] Center 35 (5~66) winsize 62
5078 22:55:31.514175 [CA 3] Center 35 (4~66) winsize 63
5079 22:55:31.517698 [CA 4] Center 34 (4~64) winsize 61
5080 22:55:31.521193 [CA 5] Center 33 (3~64) winsize 62
5081 22:55:31.521275
5082 22:55:31.524321 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5083 22:55:31.524404
5084 22:55:31.527697 [CATrainingPosCal] consider 2 rank data
5085 22:55:31.531269 u2DelayCellTimex100 = 270/100 ps
5086 22:55:31.534465 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5087 22:55:31.537946 CA1 delay=38 (8~68),Diff = 4 PI (24 cell)
5088 22:55:31.541038 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5089 22:55:31.544158 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5090 22:55:31.550736 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5091 22:55:31.554093 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5092 22:55:31.554175
5093 22:55:31.557149 CA PerBit enable=1, Macro0, CA PI delay=34
5094 22:55:31.557231
5095 22:55:31.560552 [CBTSetCACLKResult] CA Dly = 34
5096 22:55:31.560634 CS Dly: 7 (0~39)
5097 22:55:31.560699
5098 22:55:31.564148 ----->DramcWriteLeveling(PI) begin...
5099 22:55:31.564231 ==
5100 22:55:31.567324 Dram Type= 6, Freq= 0, CH_0, rank 0
5101 22:55:31.573769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5102 22:55:31.573853 ==
5103 22:55:31.577200 Write leveling (Byte 0): 28 => 28
5104 22:55:31.577281 Write leveling (Byte 1): 27 => 27
5105 22:55:31.580612 DramcWriteLeveling(PI) end<-----
5106 22:55:31.580694
5107 22:55:31.584253 ==
5108 22:55:31.584335 Dram Type= 6, Freq= 0, CH_0, rank 0
5109 22:55:31.590541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5110 22:55:31.590624 ==
5111 22:55:31.593897 [Gating] SW mode calibration
5112 22:55:31.600347 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5113 22:55:31.603878 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5114 22:55:31.610806 0 14 0 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (1 1)
5115 22:55:31.614096 0 14 4 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
5116 22:55:31.617121 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5117 22:55:31.623669 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5118 22:55:31.627005 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5119 22:55:31.630359 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5120 22:55:31.636744 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5121 22:55:31.640056 0 14 28 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
5122 22:55:31.643713 0 15 0 | B1->B0 | 3434 2f2f | 1 1 | (0 1) (0 1)
5123 22:55:31.649901 0 15 4 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
5124 22:55:31.653334 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5125 22:55:31.657038 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5126 22:55:31.663503 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5127 22:55:31.666768 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5128 22:55:31.670190 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5129 22:55:31.676791 0 15 28 | B1->B0 | 2323 2828 | 0 1 | (0 0) (0 0)
5130 22:55:31.680376 1 0 0 | B1->B0 | 3030 3e3e | 0 0 | (0 0) (0 0)
5131 22:55:31.683624 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5132 22:55:31.689899 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5133 22:55:31.693910 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5134 22:55:31.697053 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5135 22:55:31.703711 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5136 22:55:31.707190 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5137 22:55:31.710335 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5138 22:55:31.717211 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5139 22:55:31.720532 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5140 22:55:31.723836 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5141 22:55:31.727041 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5142 22:55:31.733573 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5143 22:55:31.736911 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5144 22:55:31.740046 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5145 22:55:31.746779 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5146 22:55:31.750194 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5147 22:55:31.753259 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5148 22:55:31.760576 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5149 22:55:31.763287 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5150 22:55:31.766873 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5151 22:55:31.773570 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5152 22:55:31.776737 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5153 22:55:31.780106 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5154 22:55:31.786580 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5155 22:55:31.790404 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5156 22:55:31.793042 Total UI for P1: 0, mck2ui 16
5157 22:55:31.796999 best dqsien dly found for B0: ( 1, 2, 30)
5158 22:55:31.800370 Total UI for P1: 0, mck2ui 16
5159 22:55:31.803221 best dqsien dly found for B1: ( 1, 3, 0)
5160 22:55:31.807475 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5161 22:55:31.810198 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5162 22:55:31.810669
5163 22:55:31.813619 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5164 22:55:31.816502 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5165 22:55:31.820058 [Gating] SW calibration Done
5166 22:55:31.820585 ==
5167 22:55:31.823500 Dram Type= 6, Freq= 0, CH_0, rank 0
5168 22:55:31.826607 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5169 22:55:31.829515 ==
5170 22:55:31.829982 RX Vref Scan: 0
5171 22:55:31.830399
5172 22:55:31.832886 RX Vref 0 -> 0, step: 1
5173 22:55:31.833349
5174 22:55:31.836546 RX Delay -80 -> 252, step: 8
5175 22:55:31.839696 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5176 22:55:31.842778 iDelay=200, Bit 1, Center 103 (8 ~ 199) 192
5177 22:55:31.846220 iDelay=200, Bit 2, Center 91 (-8 ~ 191) 200
5178 22:55:31.849600 iDelay=200, Bit 3, Center 91 (-8 ~ 191) 200
5179 22:55:31.852967 iDelay=200, Bit 4, Center 99 (0 ~ 199) 200
5180 22:55:31.859463 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5181 22:55:31.863033 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5182 22:55:31.866646 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5183 22:55:31.869408 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5184 22:55:31.872848 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5185 22:55:31.879507 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5186 22:55:31.882863 iDelay=200, Bit 11, Center 79 (-16 ~ 175) 192
5187 22:55:31.886298 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5188 22:55:31.889758 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5189 22:55:31.892559 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5190 22:55:31.896152 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5191 22:55:31.899979 ==
5192 22:55:31.900548 Dram Type= 6, Freq= 0, CH_0, rank 0
5193 22:55:31.905915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5194 22:55:31.906471 ==
5195 22:55:31.906838 DQS Delay:
5196 22:55:31.909353 DQS0 = 0, DQS1 = 0
5197 22:55:31.910040 DQM Delay:
5198 22:55:31.912813 DQM0 = 97, DQM1 = 88
5199 22:55:31.913302 DQ Delay:
5200 22:55:31.915914 DQ0 =95, DQ1 =103, DQ2 =91, DQ3 =91
5201 22:55:31.918968 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =103
5202 22:55:31.922363 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =79
5203 22:55:31.925947 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5204 22:55:31.926438
5205 22:55:31.926841
5206 22:55:31.927219 ==
5207 22:55:31.929372 Dram Type= 6, Freq= 0, CH_0, rank 0
5208 22:55:31.932511 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5209 22:55:31.932960 ==
5210 22:55:31.933302
5211 22:55:31.933618
5212 22:55:31.936044 TX Vref Scan disable
5213 22:55:31.939164 == TX Byte 0 ==
5214 22:55:31.942986 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5215 22:55:31.946120 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5216 22:55:31.949345 == TX Byte 1 ==
5217 22:55:31.952725 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5218 22:55:31.955826 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5219 22:55:31.956254 ==
5220 22:55:31.959620 Dram Type= 6, Freq= 0, CH_0, rank 0
5221 22:55:31.962558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5222 22:55:31.966056 ==
5223 22:55:31.966631
5224 22:55:31.966977
5225 22:55:31.967294 TX Vref Scan disable
5226 22:55:31.969664 == TX Byte 0 ==
5227 22:55:31.972639 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5228 22:55:31.979775 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5229 22:55:31.980242 == TX Byte 1 ==
5230 22:55:31.983135 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5231 22:55:31.990220 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5232 22:55:31.990748
5233 22:55:31.991089 [DATLAT]
5234 22:55:31.991471 Freq=933, CH0 RK0
5235 22:55:31.991794
5236 22:55:31.993124 DATLAT Default: 0xd
5237 22:55:31.993554 0, 0xFFFF, sum = 0
5238 22:55:31.995780 1, 0xFFFF, sum = 0
5239 22:55:31.996207 2, 0xFFFF, sum = 0
5240 22:55:31.999395 3, 0xFFFF, sum = 0
5241 22:55:32.003724 4, 0xFFFF, sum = 0
5242 22:55:32.004297 5, 0xFFFF, sum = 0
5243 22:55:32.005825 6, 0xFFFF, sum = 0
5244 22:55:32.006369 7, 0xFFFF, sum = 0
5245 22:55:32.009539 8, 0xFFFF, sum = 0
5246 22:55:32.010150 9, 0xFFFF, sum = 0
5247 22:55:32.012486 10, 0x0, sum = 1
5248 22:55:32.013247 11, 0x0, sum = 2
5249 22:55:32.016363 12, 0x0, sum = 3
5250 22:55:32.016789 13, 0x0, sum = 4
5251 22:55:32.017127 best_step = 11
5252 22:55:32.017437
5253 22:55:32.019682 ==
5254 22:55:32.020101 Dram Type= 6, Freq= 0, CH_0, rank 0
5255 22:55:32.026358 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5256 22:55:32.026885 ==
5257 22:55:32.027224 RX Vref Scan: 1
5258 22:55:32.027593
5259 22:55:32.029379 RX Vref 0 -> 0, step: 1
5260 22:55:32.029949
5261 22:55:32.032956 RX Delay -61 -> 252, step: 4
5262 22:55:32.033377
5263 22:55:32.036081 Set Vref, RX VrefLevel [Byte0]: 51
5264 22:55:32.039455 [Byte1]: 52
5265 22:55:32.039994
5266 22:55:32.042704 Final RX Vref Byte 0 = 51 to rank0
5267 22:55:32.045823 Final RX Vref Byte 1 = 52 to rank0
5268 22:55:32.048863 Final RX Vref Byte 0 = 51 to rank1
5269 22:55:32.052283 Final RX Vref Byte 1 = 52 to rank1==
5270 22:55:32.056044 Dram Type= 6, Freq= 0, CH_0, rank 0
5271 22:55:32.058738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5272 22:55:32.062401 ==
5273 22:55:32.063094 DQS Delay:
5274 22:55:32.063598 DQS0 = 0, DQS1 = 0
5275 22:55:32.065572 DQM Delay:
5276 22:55:32.065989 DQM0 = 97, DQM1 = 88
5277 22:55:32.069136 DQ Delay:
5278 22:55:32.069579 DQ0 =98, DQ1 =98, DQ2 =94, DQ3 =96
5279 22:55:32.072027 DQ4 =98, DQ5 =86, DQ6 =104, DQ7 =104
5280 22:55:32.075321 DQ8 =78, DQ9 =78, DQ10 =88, DQ11 =80
5281 22:55:32.079064 DQ12 =96, DQ13 =90, DQ14 =98, DQ15 =98
5282 22:55:32.082560
5283 22:55:32.083076
5284 22:55:32.088979 [DQSOSCAuto] RK0, (LSB)MR18= 0x1602, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 414 ps
5285 22:55:32.092250 CH0 RK0: MR19=505, MR18=1602
5286 22:55:32.098924 CH0_RK0: MR19=0x505, MR18=0x1602, DQSOSC=414, MR23=63, INC=63, DEC=42
5287 22:55:32.099415
5288 22:55:32.102074 ----->DramcWriteLeveling(PI) begin...
5289 22:55:32.102501 ==
5290 22:55:32.105669 Dram Type= 6, Freq= 0, CH_0, rank 1
5291 22:55:32.108534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5292 22:55:32.108958 ==
5293 22:55:32.111721 Write leveling (Byte 0): 31 => 31
5294 22:55:32.115055 Write leveling (Byte 1): 26 => 26
5295 22:55:32.118291 DramcWriteLeveling(PI) end<-----
5296 22:55:32.118701
5297 22:55:32.119218 ==
5298 22:55:32.121850 Dram Type= 6, Freq= 0, CH_0, rank 1
5299 22:55:32.125218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5300 22:55:32.125629 ==
5301 22:55:32.128562 [Gating] SW mode calibration
5302 22:55:32.135170 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5303 22:55:32.141479 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5304 22:55:32.145047 0 14 0 | B1->B0 | 2525 3434 | 1 1 | (1 1) (1 1)
5305 22:55:32.148492 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (0 0) (1 1)
5306 22:55:32.155008 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5307 22:55:32.158249 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5308 22:55:32.162163 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5309 22:55:32.168570 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5310 22:55:32.171810 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5311 22:55:32.175319 0 14 28 | B1->B0 | 3232 2b2b | 1 0 | (1 1) (1 0)
5312 22:55:32.181832 0 15 0 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)
5313 22:55:32.185731 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5314 22:55:32.188546 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5315 22:55:32.195029 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5316 22:55:32.198466 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5317 22:55:32.201401 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5318 22:55:32.208093 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5319 22:55:32.211632 0 15 28 | B1->B0 | 2626 3434 | 0 0 | (0 0) (0 0)
5320 22:55:32.215150 1 0 0 | B1->B0 | 3636 4646 | 0 0 | (1 1) (0 0)
5321 22:55:32.220928 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5322 22:55:32.225000 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5323 22:55:32.227661 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5324 22:55:32.234494 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5325 22:55:32.238007 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5326 22:55:32.241292 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5327 22:55:32.247818 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5328 22:55:32.251046 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5329 22:55:32.254138 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5330 22:55:32.260936 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5331 22:55:32.264709 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5332 22:55:32.267904 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5333 22:55:32.274311 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5334 22:55:32.277675 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5335 22:55:32.281016 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5336 22:55:32.287451 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5337 22:55:32.290908 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5338 22:55:32.294160 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5339 22:55:32.300962 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5340 22:55:32.304175 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5341 22:55:32.307577 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5342 22:55:32.310897 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5343 22:55:32.317823 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5344 22:55:32.320653 Total UI for P1: 0, mck2ui 16
5345 22:55:32.323949 best dqsien dly found for B0: ( 1, 2, 24)
5346 22:55:32.327424 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5347 22:55:32.330528 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5348 22:55:32.333934 Total UI for P1: 0, mck2ui 16
5349 22:55:32.337630 best dqsien dly found for B1: ( 1, 3, 0)
5350 22:55:32.340998 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5351 22:55:32.344035 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5352 22:55:32.344662
5353 22:55:32.350347 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5354 22:55:32.354029 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5355 22:55:32.357557 [Gating] SW calibration Done
5356 22:55:32.357966 ==
5357 22:55:32.360526 Dram Type= 6, Freq= 0, CH_0, rank 1
5358 22:55:32.363902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5359 22:55:32.364338 ==
5360 22:55:32.364672 RX Vref Scan: 0
5361 22:55:32.364982
5362 22:55:32.367081 RX Vref 0 -> 0, step: 1
5363 22:55:32.367601
5364 22:55:32.370317 RX Delay -80 -> 252, step: 8
5365 22:55:32.374161 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5366 22:55:32.377130 iDelay=200, Bit 1, Center 95 (0 ~ 191) 192
5367 22:55:32.380278 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5368 22:55:32.387319 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5369 22:55:32.390471 iDelay=200, Bit 4, Center 99 (8 ~ 191) 184
5370 22:55:32.393934 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5371 22:55:32.397366 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5372 22:55:32.400292 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5373 22:55:32.403837 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5374 22:55:32.410089 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5375 22:55:32.413896 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5376 22:55:32.417178 iDelay=200, Bit 11, Center 79 (-16 ~ 175) 192
5377 22:55:32.420083 iDelay=200, Bit 12, Center 91 (0 ~ 183) 184
5378 22:55:32.423580 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5379 22:55:32.430424 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5380 22:55:32.433608 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5381 22:55:32.434173 ==
5382 22:55:32.436920 Dram Type= 6, Freq= 0, CH_0, rank 1
5383 22:55:32.440481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5384 22:55:32.440913 ==
5385 22:55:32.441249 DQS Delay:
5386 22:55:32.443599 DQS0 = 0, DQS1 = 0
5387 22:55:32.444025 DQM Delay:
5388 22:55:32.447059 DQM0 = 96, DQM1 = 87
5389 22:55:32.447511 DQ Delay:
5390 22:55:32.449983 DQ0 =95, DQ1 =95, DQ2 =95, DQ3 =95
5391 22:55:32.453419 DQ4 =99, DQ5 =87, DQ6 =103, DQ7 =103
5392 22:55:32.456814 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =79
5393 22:55:32.460135 DQ12 =91, DQ13 =95, DQ14 =95, DQ15 =95
5394 22:55:32.460563
5395 22:55:32.460898
5396 22:55:32.461214 ==
5397 22:55:32.463584 Dram Type= 6, Freq= 0, CH_0, rank 1
5398 22:55:32.470125 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5399 22:55:32.470561 ==
5400 22:55:32.470900
5401 22:55:32.471210
5402 22:55:32.471562 TX Vref Scan disable
5403 22:55:32.473256 == TX Byte 0 ==
5404 22:55:32.476514 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5405 22:55:32.483042 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5406 22:55:32.483527 == TX Byte 1 ==
5407 22:55:32.486245 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5408 22:55:32.492907 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5409 22:55:32.493339 ==
5410 22:55:32.496528 Dram Type= 6, Freq= 0, CH_0, rank 1
5411 22:55:32.499711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5412 22:55:32.500163 ==
5413 22:55:32.500526
5414 22:55:32.500880
5415 22:55:32.503146 TX Vref Scan disable
5416 22:55:32.503617 == TX Byte 0 ==
5417 22:55:32.509772 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5418 22:55:32.513250 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5419 22:55:32.516411 == TX Byte 1 ==
5420 22:55:32.519959 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5421 22:55:32.523011 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5422 22:55:32.523585
5423 22:55:32.523942 [DATLAT]
5424 22:55:32.525875 Freq=933, CH0 RK1
5425 22:55:32.526304
5426 22:55:32.526636 DATLAT Default: 0xb
5427 22:55:32.529481 0, 0xFFFF, sum = 0
5428 22:55:32.532972 1, 0xFFFF, sum = 0
5429 22:55:32.533412 2, 0xFFFF, sum = 0
5430 22:55:32.536127 3, 0xFFFF, sum = 0
5431 22:55:32.536562 4, 0xFFFF, sum = 0
5432 22:55:32.539648 5, 0xFFFF, sum = 0
5433 22:55:32.540082 6, 0xFFFF, sum = 0
5434 22:55:32.543506 7, 0xFFFF, sum = 0
5435 22:55:32.544039 8, 0xFFFF, sum = 0
5436 22:55:32.546292 9, 0xFFFF, sum = 0
5437 22:55:32.546843 10, 0x0, sum = 1
5438 22:55:32.549410 11, 0x0, sum = 2
5439 22:55:32.549844 12, 0x0, sum = 3
5440 22:55:32.552792 13, 0x0, sum = 4
5441 22:55:32.553314 best_step = 11
5442 22:55:32.553653
5443 22:55:32.553969 ==
5444 22:55:32.556091 Dram Type= 6, Freq= 0, CH_0, rank 1
5445 22:55:32.559505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5446 22:55:32.560033 ==
5447 22:55:32.562904 RX Vref Scan: 0
5448 22:55:32.563333
5449 22:55:32.566059 RX Vref 0 -> 0, step: 1
5450 22:55:32.566582
5451 22:55:32.566925 RX Delay -61 -> 252, step: 4
5452 22:55:32.573608 iDelay=199, Bit 0, Center 96 (3 ~ 190) 188
5453 22:55:32.576936 iDelay=199, Bit 1, Center 96 (3 ~ 190) 188
5454 22:55:32.580262 iDelay=199, Bit 2, Center 94 (3 ~ 186) 184
5455 22:55:32.583706 iDelay=199, Bit 3, Center 94 (-1 ~ 190) 192
5456 22:55:32.586633 iDelay=199, Bit 4, Center 96 (7 ~ 186) 180
5457 22:55:32.590228 iDelay=199, Bit 5, Center 84 (-9 ~ 178) 188
5458 22:55:32.596524 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5459 22:55:32.600025 iDelay=199, Bit 7, Center 102 (11 ~ 194) 184
5460 22:55:32.603394 iDelay=199, Bit 8, Center 82 (-5 ~ 170) 176
5461 22:55:32.606728 iDelay=199, Bit 9, Center 78 (-9 ~ 166) 176
5462 22:55:32.609808 iDelay=199, Bit 10, Center 88 (-1 ~ 178) 180
5463 22:55:32.616372 iDelay=199, Bit 11, Center 80 (-5 ~ 166) 172
5464 22:55:32.619945 iDelay=199, Bit 12, Center 90 (-1 ~ 182) 184
5465 22:55:32.623410 iDelay=199, Bit 13, Center 92 (3 ~ 182) 180
5466 22:55:32.626705 iDelay=199, Bit 14, Center 96 (7 ~ 186) 180
5467 22:55:32.629723 iDelay=199, Bit 15, Center 96 (7 ~ 186) 180
5468 22:55:32.630168 ==
5469 22:55:32.633004 Dram Type= 6, Freq= 0, CH_0, rank 1
5470 22:55:32.640069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5471 22:55:32.640521 ==
5472 22:55:32.640890 DQS Delay:
5473 22:55:32.643303 DQS0 = 0, DQS1 = 0
5474 22:55:32.643803 DQM Delay:
5475 22:55:32.644172 DQM0 = 95, DQM1 = 87
5476 22:55:32.646650 DQ Delay:
5477 22:55:32.650148 DQ0 =96, DQ1 =96, DQ2 =94, DQ3 =94
5478 22:55:32.652959 DQ4 =96, DQ5 =84, DQ6 =104, DQ7 =102
5479 22:55:32.656478 DQ8 =82, DQ9 =78, DQ10 =88, DQ11 =80
5480 22:55:32.659619 DQ12 =90, DQ13 =92, DQ14 =96, DQ15 =96
5481 22:55:32.660041
5482 22:55:32.660371
5483 22:55:32.666774 [DQSOSCAuto] RK1, (LSB)MR18= 0x1a08, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 413 ps
5484 22:55:32.670416 CH0 RK1: MR19=505, MR18=1A08
5485 22:55:32.676418 CH0_RK1: MR19=0x505, MR18=0x1A08, DQSOSC=413, MR23=63, INC=63, DEC=42
5486 22:55:32.680024 [RxdqsGatingPostProcess] freq 933
5487 22:55:32.683331 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5488 22:55:32.686403 best DQS0 dly(2T, 0.5T) = (0, 10)
5489 22:55:32.689807 best DQS1 dly(2T, 0.5T) = (0, 11)
5490 22:55:32.692706 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5491 22:55:32.696121 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5492 22:55:32.699606 best DQS0 dly(2T, 0.5T) = (0, 10)
5493 22:55:32.702815 best DQS1 dly(2T, 0.5T) = (0, 11)
5494 22:55:32.706339 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5495 22:55:32.709290 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5496 22:55:32.712795 Pre-setting of DQS Precalculation
5497 22:55:32.716081 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5498 22:55:32.719335 ==
5499 22:55:32.722885 Dram Type= 6, Freq= 0, CH_1, rank 0
5500 22:55:32.725648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5501 22:55:32.726074 ==
5502 22:55:32.729144 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5503 22:55:32.735946 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5504 22:55:32.739377 [CA 0] Center 37 (7~67) winsize 61
5505 22:55:32.742577 [CA 1] Center 36 (6~67) winsize 62
5506 22:55:32.745944 [CA 2] Center 34 (4~64) winsize 61
5507 22:55:32.749072 [CA 3] Center 33 (3~64) winsize 62
5508 22:55:32.752737 [CA 4] Center 34 (4~64) winsize 61
5509 22:55:32.756283 [CA 5] Center 33 (3~63) winsize 61
5510 22:55:32.756798
5511 22:55:32.759605 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5512 22:55:32.760196
5513 22:55:32.762355 [CATrainingPosCal] consider 1 rank data
5514 22:55:32.765883 u2DelayCellTimex100 = 270/100 ps
5515 22:55:32.769014 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5516 22:55:32.775765 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5517 22:55:32.779316 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5518 22:55:32.782656 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5519 22:55:32.785822 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5520 22:55:32.789134 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5521 22:55:32.789745
5522 22:55:32.792021 CA PerBit enable=1, Macro0, CA PI delay=33
5523 22:55:32.792587
5524 22:55:32.795575 [CBTSetCACLKResult] CA Dly = 33
5525 22:55:32.799089 CS Dly: 4 (0~35)
5526 22:55:32.799673 ==
5527 22:55:32.802287 Dram Type= 6, Freq= 0, CH_1, rank 1
5528 22:55:32.805489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5529 22:55:32.806055 ==
5530 22:55:32.812145 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5531 22:55:32.815129 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5532 22:55:32.819193 [CA 0] Center 36 (6~67) winsize 62
5533 22:55:32.822825 [CA 1] Center 37 (7~67) winsize 61
5534 22:55:32.826013 [CA 2] Center 34 (4~64) winsize 61
5535 22:55:32.829558 [CA 3] Center 33 (3~64) winsize 62
5536 22:55:32.832163 [CA 4] Center 34 (4~64) winsize 61
5537 22:55:32.835601 [CA 5] Center 33 (3~63) winsize 61
5538 22:55:32.835857
5539 22:55:32.839330 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5540 22:55:32.839549
5541 22:55:32.842803 [CATrainingPosCal] consider 2 rank data
5542 22:55:32.845554 u2DelayCellTimex100 = 270/100 ps
5543 22:55:32.848936 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5544 22:55:32.852091 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5545 22:55:32.858960 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5546 22:55:32.862242 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5547 22:55:32.865747 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5548 22:55:32.868937 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5549 22:55:32.869279
5550 22:55:32.872458 CA PerBit enable=1, Macro0, CA PI delay=33
5551 22:55:32.872774
5552 22:55:32.875887 [CBTSetCACLKResult] CA Dly = 33
5553 22:55:32.876207 CS Dly: 5 (0~37)
5554 22:55:32.876496
5555 22:55:32.879062 ----->DramcWriteLeveling(PI) begin...
5556 22:55:32.882601 ==
5557 22:55:32.885972 Dram Type= 6, Freq= 0, CH_1, rank 0
5558 22:55:32.889074 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5559 22:55:32.889301 ==
5560 22:55:32.892433 Write leveling (Byte 0): 28 => 28
5561 22:55:32.895660 Write leveling (Byte 1): 32 => 32
5562 22:55:32.898976 DramcWriteLeveling(PI) end<-----
5563 22:55:32.899205
5564 22:55:32.899407 ==
5565 22:55:32.902156 Dram Type= 6, Freq= 0, CH_1, rank 0
5566 22:55:32.905397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5567 22:55:32.905639 ==
5568 22:55:32.909128 [Gating] SW mode calibration
5569 22:55:32.915183 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5570 22:55:32.922098 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5571 22:55:32.925205 0 14 0 | B1->B0 | 3131 3333 | 0 1 | (0 0) (1 1)
5572 22:55:32.928724 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5573 22:55:32.935622 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5574 22:55:32.938453 0 14 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5575 22:55:32.941804 0 14 16 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5576 22:55:32.948583 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5577 22:55:32.951742 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
5578 22:55:32.954899 0 14 28 | B1->B0 | 3030 3030 | 0 1 | (1 0) (1 0)
5579 22:55:32.962099 0 15 0 | B1->B0 | 2525 2a2a | 0 0 | (1 0) (0 1)
5580 22:55:32.965053 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5581 22:55:32.968502 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5582 22:55:32.974836 0 15 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5583 22:55:32.978561 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5584 22:55:32.981961 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5585 22:55:32.988135 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5586 22:55:32.991458 0 15 28 | B1->B0 | 3737 2d2d | 0 0 | (0 0) (0 0)
5587 22:55:32.994710 1 0 0 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
5588 22:55:33.001438 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5589 22:55:33.005298 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5590 22:55:33.007898 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5591 22:55:33.014481 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5592 22:55:33.018468 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5593 22:55:33.021610 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5594 22:55:33.028288 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5595 22:55:33.031270 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5596 22:55:33.034577 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5597 22:55:33.037884 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5598 22:55:33.044440 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5599 22:55:33.047866 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5600 22:55:33.053910 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5601 22:55:33.057549 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5602 22:55:33.060876 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5603 22:55:33.064019 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5604 22:55:33.071054 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5605 22:55:33.074150 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5606 22:55:33.077447 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5607 22:55:33.084479 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5608 22:55:33.087528 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5609 22:55:33.091034 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5610 22:55:33.097032 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5611 22:55:33.100458 Total UI for P1: 0, mck2ui 16
5612 22:55:33.104071 best dqsien dly found for B1: ( 1, 2, 24)
5613 22:55:33.107287 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5614 22:55:33.110554 Total UI for P1: 0, mck2ui 16
5615 22:55:33.114027 best dqsien dly found for B0: ( 1, 2, 26)
5616 22:55:33.117282 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5617 22:55:33.120543 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5618 22:55:33.120967
5619 22:55:33.123873 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5620 22:55:33.130413 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5621 22:55:33.130837 [Gating] SW calibration Done
5622 22:55:33.131171 ==
5623 22:55:33.134051 Dram Type= 6, Freq= 0, CH_1, rank 0
5624 22:55:33.140641 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5625 22:55:33.141091 ==
5626 22:55:33.141425 RX Vref Scan: 0
5627 22:55:33.141737
5628 22:55:33.143740 RX Vref 0 -> 0, step: 1
5629 22:55:33.144169
5630 22:55:33.147038 RX Delay -80 -> 252, step: 8
5631 22:55:33.150500 iDelay=200, Bit 0, Center 99 (8 ~ 191) 184
5632 22:55:33.153551 iDelay=200, Bit 1, Center 95 (0 ~ 191) 192
5633 22:55:33.157073 iDelay=200, Bit 2, Center 83 (-8 ~ 175) 184
5634 22:55:33.159901 iDelay=200, Bit 3, Center 99 (8 ~ 191) 184
5635 22:55:33.166949 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5636 22:55:33.170471 iDelay=200, Bit 5, Center 107 (16 ~ 199) 184
5637 22:55:33.173934 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5638 22:55:33.176651 iDelay=200, Bit 7, Center 95 (0 ~ 191) 192
5639 22:55:33.179933 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5640 22:55:33.183910 iDelay=200, Bit 9, Center 75 (-24 ~ 175) 200
5641 22:55:33.189953 iDelay=200, Bit 10, Center 91 (-8 ~ 191) 200
5642 22:55:33.193156 iDelay=200, Bit 11, Center 83 (-16 ~ 183) 200
5643 22:55:33.196506 iDelay=200, Bit 12, Center 99 (8 ~ 191) 184
5644 22:55:33.200039 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5645 22:55:33.202999 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5646 22:55:33.209780 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5647 22:55:33.210260 ==
5648 22:55:33.213029 Dram Type= 6, Freq= 0, CH_1, rank 0
5649 22:55:33.216388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5650 22:55:33.216821 ==
5651 22:55:33.217157 DQS Delay:
5652 22:55:33.219490 DQS0 = 0, DQS1 = 0
5653 22:55:33.219920 DQM Delay:
5654 22:55:33.223447 DQM0 = 97, DQM1 = 89
5655 22:55:33.224048 DQ Delay:
5656 22:55:33.226312 DQ0 =99, DQ1 =95, DQ2 =83, DQ3 =99
5657 22:55:33.229704 DQ4 =95, DQ5 =107, DQ6 =107, DQ7 =95
5658 22:55:33.233112 DQ8 =79, DQ9 =75, DQ10 =91, DQ11 =83
5659 22:55:33.236145 DQ12 =99, DQ13 =95, DQ14 =95, DQ15 =95
5660 22:55:33.236738
5661 22:55:33.237276
5662 22:55:33.237789 ==
5663 22:55:33.239705 Dram Type= 6, Freq= 0, CH_1, rank 0
5664 22:55:33.242965 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5665 22:55:33.243392 ==
5666 22:55:33.243771
5667 22:55:33.246112
5668 22:55:33.246490 TX Vref Scan disable
5669 22:55:33.249551 == TX Byte 0 ==
5670 22:55:33.252625 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5671 22:55:33.256137 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5672 22:55:33.259587 == TX Byte 1 ==
5673 22:55:33.262997 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5674 22:55:33.266393 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5675 22:55:33.266623 ==
5676 22:55:33.269720 Dram Type= 6, Freq= 0, CH_1, rank 0
5677 22:55:33.276158 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5678 22:55:33.276388 ==
5679 22:55:33.276587
5680 22:55:33.276762
5681 22:55:33.276922 TX Vref Scan disable
5682 22:55:33.280323 == TX Byte 0 ==
5683 22:55:33.283681 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5684 22:55:33.290286 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5685 22:55:33.290516 == TX Byte 1 ==
5686 22:55:33.293683 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5687 22:55:33.299760 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5688 22:55:33.299988
5689 22:55:33.300192 [DATLAT]
5690 22:55:33.300378 Freq=933, CH1 RK0
5691 22:55:33.300611
5692 22:55:33.303526 DATLAT Default: 0xd
5693 22:55:33.303755 0, 0xFFFF, sum = 0
5694 22:55:33.306754 1, 0xFFFF, sum = 0
5695 22:55:33.309807 2, 0xFFFF, sum = 0
5696 22:55:33.310099 3, 0xFFFF, sum = 0
5697 22:55:33.312999 4, 0xFFFF, sum = 0
5698 22:55:33.313231 5, 0xFFFF, sum = 0
5699 22:55:33.316769 6, 0xFFFF, sum = 0
5700 22:55:33.317000 7, 0xFFFF, sum = 0
5701 22:55:33.319685 8, 0xFFFF, sum = 0
5702 22:55:33.319945 9, 0xFFFF, sum = 0
5703 22:55:33.322953 10, 0x0, sum = 1
5704 22:55:33.323184 11, 0x0, sum = 2
5705 22:55:33.326777 12, 0x0, sum = 3
5706 22:55:33.327014 13, 0x0, sum = 4
5707 22:55:33.327197 best_step = 11
5708 22:55:33.327381
5709 22:55:33.329580 ==
5710 22:55:33.333232 Dram Type= 6, Freq= 0, CH_1, rank 0
5711 22:55:33.336612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5712 22:55:33.336850 ==
5713 22:55:33.337031 RX Vref Scan: 1
5714 22:55:33.337244
5715 22:55:33.339446 RX Vref 0 -> 0, step: 1
5716 22:55:33.339687
5717 22:55:33.342888 RX Delay -69 -> 252, step: 4
5718 22:55:33.343143
5719 22:55:33.346158 Set Vref, RX VrefLevel [Byte0]: 55
5720 22:55:33.349746 [Byte1]: 51
5721 22:55:33.350062
5722 22:55:33.353280 Final RX Vref Byte 0 = 55 to rank0
5723 22:55:33.356659 Final RX Vref Byte 1 = 51 to rank0
5724 22:55:33.359626 Final RX Vref Byte 0 = 55 to rank1
5725 22:55:33.362972 Final RX Vref Byte 1 = 51 to rank1==
5726 22:55:33.366412 Dram Type= 6, Freq= 0, CH_1, rank 0
5727 22:55:33.369466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5728 22:55:33.372893 ==
5729 22:55:33.373120 DQS Delay:
5730 22:55:33.373300 DQS0 = 0, DQS1 = 0
5731 22:55:33.376171 DQM Delay:
5732 22:55:33.376418 DQM0 = 98, DQM1 = 90
5733 22:55:33.379687 DQ Delay:
5734 22:55:33.382771 DQ0 =100, DQ1 =94, DQ2 =86, DQ3 =98
5735 22:55:33.386013 DQ4 =98, DQ5 =108, DQ6 =108, DQ7 =94
5736 22:55:33.389606 DQ8 =80, DQ9 =78, DQ10 =90, DQ11 =88
5737 22:55:33.393106 DQ12 =98, DQ13 =96, DQ14 =96, DQ15 =94
5738 22:55:33.393387
5739 22:55:33.393609
5740 22:55:33.399552 [DQSOSCAuto] RK0, (LSB)MR18= 0x19f6, (MSB)MR19= 0x504, tDQSOscB0 = 425 ps tDQSOscB1 = 413 ps
5741 22:55:33.402367 CH1 RK0: MR19=504, MR18=19F6
5742 22:55:33.408929 CH1_RK0: MR19=0x504, MR18=0x19F6, DQSOSC=413, MR23=63, INC=63, DEC=42
5743 22:55:33.409013
5744 22:55:33.412649 ----->DramcWriteLeveling(PI) begin...
5745 22:55:33.412733 ==
5746 22:55:33.415962 Dram Type= 6, Freq= 0, CH_1, rank 1
5747 22:55:33.419317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5748 22:55:33.419464 ==
5749 22:55:33.422222 Write leveling (Byte 0): 30 => 30
5750 22:55:33.425886 Write leveling (Byte 1): 31 => 31
5751 22:55:33.428955 DramcWriteLeveling(PI) end<-----
5752 22:55:33.429068
5753 22:55:33.429141 ==
5754 22:55:33.432151 Dram Type= 6, Freq= 0, CH_1, rank 1
5755 22:55:33.435566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5756 22:55:33.435668 ==
5757 22:55:33.438705 [Gating] SW mode calibration
5758 22:55:33.445812 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5759 22:55:33.451992 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5760 22:55:33.455621 0 14 0 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5761 22:55:33.462180 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5762 22:55:33.465682 0 14 8 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5763 22:55:33.469217 0 14 12 | B1->B0 | 3534 3434 | 1 1 | (0 0) (1 1)
5764 22:55:33.475183 0 14 16 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5765 22:55:33.478426 0 14 20 | B1->B0 | 3535 3434 | 0 0 | (0 0) (0 0)
5766 22:55:33.481737 0 14 24 | B1->B0 | 3030 2e2e | 0 0 | (1 0) (0 0)
5767 22:55:33.488967 0 14 28 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
5768 22:55:33.491986 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5769 22:55:33.496060 0 15 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5770 22:55:33.498929 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5771 22:55:33.505224 0 15 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5772 22:55:33.508546 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5773 22:55:33.511692 0 15 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5774 22:55:33.518490 0 15 24 | B1->B0 | 2626 3939 | 0 0 | (0 0) (0 0)
5775 22:55:33.522366 0 15 28 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
5776 22:55:33.525824 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5777 22:55:33.532306 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5778 22:55:33.535889 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5779 22:55:33.538861 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5780 22:55:33.545306 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5781 22:55:33.548599 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5782 22:55:33.552443 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5783 22:55:33.558636 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5784 22:55:33.562376 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5785 22:55:33.565299 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5786 22:55:33.572879 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5787 22:55:33.575389 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5788 22:55:33.579030 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5789 22:55:33.585138 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5790 22:55:33.588885 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5791 22:55:33.592570 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5792 22:55:33.599016 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5793 22:55:33.602133 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5794 22:55:33.605513 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5795 22:55:33.612057 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5796 22:55:33.615519 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5797 22:55:33.618697 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5798 22:55:33.625012 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5799 22:55:33.625564 Total UI for P1: 0, mck2ui 16
5800 22:55:33.628553 best dqsien dly found for B0: ( 1, 2, 20)
5801 22:55:33.635176 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5802 22:55:33.639100 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5803 22:55:33.641987 Total UI for P1: 0, mck2ui 16
5804 22:55:33.645796 best dqsien dly found for B1: ( 1, 2, 26)
5805 22:55:33.648572 best DQS0 dly(MCK, UI, PI) = (1, 2, 20)
5806 22:55:33.651532 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5807 22:55:33.651969
5808 22:55:33.655494 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 20)
5809 22:55:33.658500 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5810 22:55:33.662165 [Gating] SW calibration Done
5811 22:55:33.662835 ==
5812 22:55:33.665482 Dram Type= 6, Freq= 0, CH_1, rank 1
5813 22:55:33.671785 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5814 22:55:33.672363 ==
5815 22:55:33.672711 RX Vref Scan: 0
5816 22:55:33.673036
5817 22:55:33.674995 RX Vref 0 -> 0, step: 1
5818 22:55:33.675661
5819 22:55:33.678682 RX Delay -80 -> 252, step: 8
5820 22:55:33.682063 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5821 22:55:33.685443 iDelay=200, Bit 1, Center 87 (-8 ~ 183) 192
5822 22:55:33.688492 iDelay=200, Bit 2, Center 83 (-16 ~ 183) 200
5823 22:55:33.691877 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5824 22:55:33.698126 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5825 22:55:33.701707 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5826 22:55:33.704901 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5827 22:55:33.708293 iDelay=200, Bit 7, Center 87 (-8 ~ 183) 192
5828 22:55:33.711639 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5829 22:55:33.715191 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5830 22:55:33.721918 iDelay=200, Bit 10, Center 91 (0 ~ 183) 184
5831 22:55:33.724952 iDelay=200, Bit 11, Center 79 (-16 ~ 175) 192
5832 22:55:33.727921 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5833 22:55:33.731459 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5834 22:55:33.734673 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5835 22:55:33.741632 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5836 22:55:33.742082 ==
5837 22:55:33.744731 Dram Type= 6, Freq= 0, CH_1, rank 1
5838 22:55:33.747866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5839 22:55:33.748293 ==
5840 22:55:33.748626 DQS Delay:
5841 22:55:33.751283 DQS0 = 0, DQS1 = 0
5842 22:55:33.751886 DQM Delay:
5843 22:55:33.754590 DQM0 = 93, DQM1 = 88
5844 22:55:33.755016 DQ Delay:
5845 22:55:33.758184 DQ0 =95, DQ1 =87, DQ2 =83, DQ3 =95
5846 22:55:33.761564 DQ4 =95, DQ5 =103, DQ6 =103, DQ7 =87
5847 22:55:33.764919 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =79
5848 22:55:33.767734 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5849 22:55:33.768158
5850 22:55:33.768489
5851 22:55:33.768800 ==
5852 22:55:33.771168 Dram Type= 6, Freq= 0, CH_1, rank 1
5853 22:55:33.774816 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5854 22:55:33.775245 ==
5855 22:55:33.775620
5856 22:55:33.775937
5857 22:55:33.777820 TX Vref Scan disable
5858 22:55:33.781118 == TX Byte 0 ==
5859 22:55:33.784588 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5860 22:55:33.787846 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5861 22:55:33.791642 == TX Byte 1 ==
5862 22:55:33.794390 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5863 22:55:33.797686 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5864 22:55:33.798119 ==
5865 22:55:33.801337 Dram Type= 6, Freq= 0, CH_1, rank 1
5866 22:55:33.808781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5867 22:55:33.809305 ==
5868 22:55:33.809645
5869 22:55:33.809960
5870 22:55:33.810261 TX Vref Scan disable
5871 22:55:33.812085 == TX Byte 0 ==
5872 22:55:33.815107 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5873 22:55:33.821479 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5874 22:55:33.821910 == TX Byte 1 ==
5875 22:55:33.825164 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5876 22:55:33.832134 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5877 22:55:33.832668
5878 22:55:33.833011 [DATLAT]
5879 22:55:33.833327 Freq=933, CH1 RK1
5880 22:55:33.833633
5881 22:55:33.835236 DATLAT Default: 0xb
5882 22:55:33.835701 0, 0xFFFF, sum = 0
5883 22:55:33.838411 1, 0xFFFF, sum = 0
5884 22:55:33.841998 2, 0xFFFF, sum = 0
5885 22:55:33.842667 3, 0xFFFF, sum = 0
5886 22:55:33.845206 4, 0xFFFF, sum = 0
5887 22:55:33.845739 5, 0xFFFF, sum = 0
5888 22:55:33.848343 6, 0xFFFF, sum = 0
5889 22:55:33.848778 7, 0xFFFF, sum = 0
5890 22:55:33.851943 8, 0xFFFF, sum = 0
5891 22:55:33.852584 9, 0xFFFF, sum = 0
5892 22:55:33.855218 10, 0x0, sum = 1
5893 22:55:33.855836 11, 0x0, sum = 2
5894 22:55:33.858388 12, 0x0, sum = 3
5895 22:55:33.858821 13, 0x0, sum = 4
5896 22:55:33.859162 best_step = 11
5897 22:55:33.859519
5898 22:55:33.861568 ==
5899 22:55:33.865142 Dram Type= 6, Freq= 0, CH_1, rank 1
5900 22:55:33.868515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5901 22:55:33.869038 ==
5902 22:55:33.869380 RX Vref Scan: 0
5903 22:55:33.869695
5904 22:55:33.871771 RX Vref 0 -> 0, step: 1
5905 22:55:33.872252
5906 22:55:33.874885 RX Delay -61 -> 252, step: 4
5907 22:55:33.878914 iDelay=199, Bit 0, Center 96 (7 ~ 186) 180
5908 22:55:33.885445 iDelay=199, Bit 1, Center 90 (-1 ~ 182) 184
5909 22:55:33.887884 iDelay=199, Bit 2, Center 86 (-5 ~ 178) 184
5910 22:55:33.891262 iDelay=199, Bit 3, Center 94 (3 ~ 186) 184
5911 22:55:33.895447 iDelay=199, Bit 4, Center 96 (3 ~ 190) 188
5912 22:55:33.898073 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5913 22:55:33.902004 iDelay=199, Bit 6, Center 102 (11 ~ 194) 184
5914 22:55:33.908789 iDelay=199, Bit 7, Center 92 (3 ~ 182) 180
5915 22:55:33.911175 iDelay=199, Bit 8, Center 80 (-13 ~ 174) 188
5916 22:55:33.914819 iDelay=199, Bit 9, Center 78 (-13 ~ 170) 184
5917 22:55:33.918272 iDelay=199, Bit 10, Center 90 (-1 ~ 182) 184
5918 22:55:33.922137 iDelay=199, Bit 11, Center 84 (-5 ~ 174) 180
5919 22:55:33.928028 iDelay=199, Bit 12, Center 98 (11 ~ 186) 176
5920 22:55:33.931170 iDelay=199, Bit 13, Center 100 (11 ~ 190) 180
5921 22:55:33.935071 iDelay=199, Bit 14, Center 100 (11 ~ 190) 180
5922 22:55:33.938174 iDelay=199, Bit 15, Center 98 (11 ~ 186) 176
5923 22:55:33.938606 ==
5924 22:55:33.941309 Dram Type= 6, Freq= 0, CH_1, rank 1
5925 22:55:33.947936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5926 22:55:33.948458 ==
5927 22:55:33.948797 DQS Delay:
5928 22:55:33.949110 DQS0 = 0, DQS1 = 0
5929 22:55:33.951295 DQM Delay:
5930 22:55:33.951855 DQM0 = 95, DQM1 = 91
5931 22:55:33.955155 DQ Delay:
5932 22:55:33.958324 DQ0 =96, DQ1 =90, DQ2 =86, DQ3 =94
5933 22:55:33.961205 DQ4 =96, DQ5 =106, DQ6 =102, DQ7 =92
5934 22:55:33.965249 DQ8 =80, DQ9 =78, DQ10 =90, DQ11 =84
5935 22:55:33.967617 DQ12 =98, DQ13 =100, DQ14 =100, DQ15 =98
5936 22:55:33.968049
5937 22:55:33.968386
5938 22:55:33.974916 [DQSOSCAuto] RK1, (LSB)MR18= 0x1019, (MSB)MR19= 0x505, tDQSOscB0 = 413 ps tDQSOscB1 = 416 ps
5939 22:55:33.977423 CH1 RK1: MR19=505, MR18=1019
5940 22:55:33.984788 CH1_RK1: MR19=0x505, MR18=0x1019, DQSOSC=413, MR23=63, INC=63, DEC=42
5941 22:55:33.987884 [RxdqsGatingPostProcess] freq 933
5942 22:55:33.990957 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5943 22:55:33.994664 best DQS0 dly(2T, 0.5T) = (0, 10)
5944 22:55:33.997417 best DQS1 dly(2T, 0.5T) = (0, 10)
5945 22:55:34.001226 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5946 22:55:34.004020 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5947 22:55:34.007929 best DQS0 dly(2T, 0.5T) = (0, 10)
5948 22:55:34.011280 best DQS1 dly(2T, 0.5T) = (0, 10)
5949 22:55:34.014262 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5950 22:55:34.018103 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5951 22:55:34.020697 Pre-setting of DQS Precalculation
5952 22:55:34.024123 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5953 22:55:34.034024 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5954 22:55:34.040664 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5955 22:55:34.041141
5956 22:55:34.041510
5957 22:55:34.044095 [Calibration Summary] 1866 Mbps
5958 22:55:34.044628 CH 0, Rank 0
5959 22:55:34.047289 SW Impedance : PASS
5960 22:55:34.047840 DUTY Scan : NO K
5961 22:55:34.050424 ZQ Calibration : PASS
5962 22:55:34.053605 Jitter Meter : NO K
5963 22:55:34.054043 CBT Training : PASS
5964 22:55:34.056879 Write leveling : PASS
5965 22:55:34.060590 RX DQS gating : PASS
5966 22:55:34.061030 RX DQ/DQS(RDDQC) : PASS
5967 22:55:34.063936 TX DQ/DQS : PASS
5968 22:55:34.067757 RX DATLAT : PASS
5969 22:55:34.068290 RX DQ/DQS(Engine): PASS
5970 22:55:34.070868 TX OE : NO K
5971 22:55:34.071435 All Pass.
5972 22:55:34.071879
5973 22:55:34.073853 CH 0, Rank 1
5974 22:55:34.074290 SW Impedance : PASS
5975 22:55:34.077431 DUTY Scan : NO K
5976 22:55:34.080589 ZQ Calibration : PASS
5977 22:55:34.081029 Jitter Meter : NO K
5978 22:55:34.083807 CBT Training : PASS
5979 22:55:34.084244 Write leveling : PASS
5980 22:55:34.087761 RX DQS gating : PASS
5981 22:55:34.090475 RX DQ/DQS(RDDQC) : PASS
5982 22:55:34.090910 TX DQ/DQS : PASS
5983 22:55:34.094058 RX DATLAT : PASS
5984 22:55:34.096908 RX DQ/DQS(Engine): PASS
5985 22:55:34.097385 TX OE : NO K
5986 22:55:34.100212 All Pass.
5987 22:55:34.100645
5988 22:55:34.101081 CH 1, Rank 0
5989 22:55:34.103568 SW Impedance : PASS
5990 22:55:34.104005 DUTY Scan : NO K
5991 22:55:34.107171 ZQ Calibration : PASS
5992 22:55:34.110777 Jitter Meter : NO K
5993 22:55:34.111311 CBT Training : PASS
5994 22:55:34.114119 Write leveling : PASS
5995 22:55:34.117495 RX DQS gating : PASS
5996 22:55:34.118041 RX DQ/DQS(RDDQC) : PASS
5997 22:55:34.120412 TX DQ/DQS : PASS
5998 22:55:34.123887 RX DATLAT : PASS
5999 22:55:34.124325 RX DQ/DQS(Engine): PASS
6000 22:55:34.126983 TX OE : NO K
6001 22:55:34.127534 All Pass.
6002 22:55:34.127980
6003 22:55:34.130385 CH 1, Rank 1
6004 22:55:34.130823 SW Impedance : PASS
6005 22:55:34.133830 DUTY Scan : NO K
6006 22:55:34.134267 ZQ Calibration : PASS
6007 22:55:34.136434 Jitter Meter : NO K
6008 22:55:34.139818 CBT Training : PASS
6009 22:55:34.140256 Write leveling : PASS
6010 22:55:34.143482 RX DQS gating : PASS
6011 22:55:34.146918 RX DQ/DQS(RDDQC) : PASS
6012 22:55:34.147482 TX DQ/DQS : PASS
6013 22:55:34.149963 RX DATLAT : PASS
6014 22:55:34.153314 RX DQ/DQS(Engine): PASS
6015 22:55:34.153943 TX OE : NO K
6016 22:55:34.156474 All Pass.
6017 22:55:34.157055
6018 22:55:34.157400 DramC Write-DBI off
6019 22:55:34.160113 PER_BANK_REFRESH: Hybrid Mode
6020 22:55:34.163310 TX_TRACKING: ON
6021 22:55:34.169975 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6022 22:55:34.173366 [FAST_K] Save calibration result to emmc
6023 22:55:34.176810 dramc_set_vcore_voltage set vcore to 650000
6024 22:55:34.180200 Read voltage for 400, 6
6025 22:55:34.180661 Vio18 = 0
6026 22:55:34.183039 Vcore = 650000
6027 22:55:34.183518 Vdram = 0
6028 22:55:34.183859 Vddq = 0
6029 22:55:34.186566 Vmddr = 0
6030 22:55:34.190103 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6031 22:55:34.196729 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6032 22:55:34.197156 MEM_TYPE=3, freq_sel=20
6033 22:55:34.199608 sv_algorithm_assistance_LP4_800
6034 22:55:34.206317 ============ PULL DRAM RESETB DOWN ============
6035 22:55:34.209413 ========== PULL DRAM RESETB DOWN end =========
6036 22:55:34.213065 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6037 22:55:34.216827 ===================================
6038 22:55:34.219569 LPDDR4 DRAM CONFIGURATION
6039 22:55:34.223240 ===================================
6040 22:55:34.223712 EX_ROW_EN[0] = 0x0
6041 22:55:34.226212 EX_ROW_EN[1] = 0x0
6042 22:55:34.229342 LP4Y_EN = 0x0
6043 22:55:34.229769 WORK_FSP = 0x0
6044 22:55:34.232954 WL = 0x2
6045 22:55:34.233515 RL = 0x2
6046 22:55:34.236796 BL = 0x2
6047 22:55:34.237251 RPST = 0x0
6048 22:55:34.239867 RD_PRE = 0x0
6049 22:55:34.240472 WR_PRE = 0x1
6050 22:55:34.243174 WR_PST = 0x0
6051 22:55:34.243716 DBI_WR = 0x0
6052 22:55:34.246505 DBI_RD = 0x0
6053 22:55:34.246914 OTF = 0x1
6054 22:55:34.249770 ===================================
6055 22:55:34.253149 ===================================
6056 22:55:34.255925 ANA top config
6057 22:55:34.259571 ===================================
6058 22:55:34.260025 DLL_ASYNC_EN = 0
6059 22:55:34.262626 ALL_SLAVE_EN = 1
6060 22:55:34.265915 NEW_RANK_MODE = 1
6061 22:55:34.269803 DLL_IDLE_MODE = 1
6062 22:55:34.272530 LP45_APHY_COMB_EN = 1
6063 22:55:34.273015 TX_ODT_DIS = 1
6064 22:55:34.275744 NEW_8X_MODE = 1
6065 22:55:34.279333 ===================================
6066 22:55:34.282913 ===================================
6067 22:55:34.286107 data_rate = 800
6068 22:55:34.288974 CKR = 1
6069 22:55:34.292192 DQ_P2S_RATIO = 4
6070 22:55:34.296082 ===================================
6071 22:55:34.299462 CA_P2S_RATIO = 4
6072 22:55:34.299889 DQ_CA_OPEN = 0
6073 22:55:34.302609 DQ_SEMI_OPEN = 1
6074 22:55:34.306192 CA_SEMI_OPEN = 1
6075 22:55:34.309408 CA_FULL_RATE = 0
6076 22:55:34.312469 DQ_CKDIV4_EN = 0
6077 22:55:34.316161 CA_CKDIV4_EN = 1
6078 22:55:34.316683 CA_PREDIV_EN = 0
6079 22:55:34.319739 PH8_DLY = 0
6080 22:55:34.322183 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6081 22:55:34.325934 DQ_AAMCK_DIV = 0
6082 22:55:34.328988 CA_AAMCK_DIV = 0
6083 22:55:34.329419 CA_ADMCK_DIV = 4
6084 22:55:34.332848 DQ_TRACK_CA_EN = 0
6085 22:55:34.335650 CA_PICK = 800
6086 22:55:34.338835 CA_MCKIO = 400
6087 22:55:34.342553 MCKIO_SEMI = 400
6088 22:55:34.345404 PLL_FREQ = 3016
6089 22:55:34.349066 DQ_UI_PI_RATIO = 32
6090 22:55:34.352151 CA_UI_PI_RATIO = 32
6091 22:55:34.355415 ===================================
6092 22:55:34.358639 ===================================
6093 22:55:34.359068 memory_type:LPDDR4
6094 22:55:34.362598 GP_NUM : 10
6095 22:55:34.365710 SRAM_EN : 1
6096 22:55:34.366233 MD32_EN : 0
6097 22:55:34.368749 ===================================
6098 22:55:34.372220 [ANA_INIT] >>>>>>>>>>>>>>
6099 22:55:34.375113 <<<<<< [CONFIGURE PHASE]: ANA_TX
6100 22:55:34.378356 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6101 22:55:34.382110 ===================================
6102 22:55:34.385435 data_rate = 800,PCW = 0X7400
6103 22:55:34.388640 ===================================
6104 22:55:34.391920 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6105 22:55:34.395134 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6106 22:55:34.408687 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6107 22:55:34.411979 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6108 22:55:34.415122 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6109 22:55:34.418319 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6110 22:55:34.421624 [ANA_INIT] flow start
6111 22:55:34.422071 [ANA_INIT] PLL >>>>>>>>
6112 22:55:34.425241 [ANA_INIT] PLL <<<<<<<<
6113 22:55:34.428612 [ANA_INIT] MIDPI >>>>>>>>
6114 22:55:34.431605 [ANA_INIT] MIDPI <<<<<<<<
6115 22:55:34.432034 [ANA_INIT] DLL >>>>>>>>
6116 22:55:34.434810 [ANA_INIT] flow end
6117 22:55:34.438206 ============ LP4 DIFF to SE enter ============
6118 22:55:34.441974 ============ LP4 DIFF to SE exit ============
6119 22:55:34.445256 [ANA_INIT] <<<<<<<<<<<<<
6120 22:55:34.448383 [Flow] Enable top DCM control >>>>>
6121 22:55:34.451445 [Flow] Enable top DCM control <<<<<
6122 22:55:34.454911 Enable DLL master slave shuffle
6123 22:55:34.461866 ==============================================================
6124 22:55:34.462299 Gating Mode config
6125 22:55:34.468350 ==============================================================
6126 22:55:34.468805 Config description:
6127 22:55:34.478057 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6128 22:55:34.484689 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6129 22:55:34.492021 SELPH_MODE 0: By rank 1: By Phase
6130 22:55:34.494811 ==============================================================
6131 22:55:34.498150 GAT_TRACK_EN = 0
6132 22:55:34.501445 RX_GATING_MODE = 2
6133 22:55:34.505416 RX_GATING_TRACK_MODE = 2
6134 22:55:34.508640 SELPH_MODE = 1
6135 22:55:34.511468 PICG_EARLY_EN = 1
6136 22:55:34.514839 VALID_LAT_VALUE = 1
6137 22:55:34.517958 ==============================================================
6138 22:55:34.521361 Enter into Gating configuration >>>>
6139 22:55:34.524830 Exit from Gating configuration <<<<
6140 22:55:34.528521 Enter into DVFS_PRE_config >>>>>
6141 22:55:34.541101 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6142 22:55:34.544338 Exit from DVFS_PRE_config <<<<<
6143 22:55:34.547622 Enter into PICG configuration >>>>
6144 22:55:34.547709 Exit from PICG configuration <<<<
6145 22:55:34.551502 [RX_INPUT] configuration >>>>>
6146 22:55:34.554396 [RX_INPUT] configuration <<<<<
6147 22:55:34.561258 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6148 22:55:34.564413 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6149 22:55:34.570745 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6150 22:55:34.578162 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6151 22:55:34.584976 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6152 22:55:34.591406 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6153 22:55:34.594522 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6154 22:55:34.598633 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6155 22:55:34.604554 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6156 22:55:34.608536 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6157 22:55:34.610934 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6158 22:55:34.615325 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6159 22:55:34.617785 ===================================
6160 22:55:34.620969 LPDDR4 DRAM CONFIGURATION
6161 22:55:34.624299 ===================================
6162 22:55:34.627778 EX_ROW_EN[0] = 0x0
6163 22:55:34.628199 EX_ROW_EN[1] = 0x0
6164 22:55:34.631107 LP4Y_EN = 0x0
6165 22:55:34.631570 WORK_FSP = 0x0
6166 22:55:34.634307 WL = 0x2
6167 22:55:34.634728 RL = 0x2
6168 22:55:34.637711 BL = 0x2
6169 22:55:34.638129 RPST = 0x0
6170 22:55:34.641571 RD_PRE = 0x0
6171 22:55:34.641989 WR_PRE = 0x1
6172 22:55:34.644811 WR_PST = 0x0
6173 22:55:34.645325 DBI_WR = 0x0
6174 22:55:34.647855 DBI_RD = 0x0
6175 22:55:34.648276 OTF = 0x1
6176 22:55:34.650861 ===================================
6177 22:55:34.657365 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6178 22:55:34.661097 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6179 22:55:34.664210 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6180 22:55:34.667249 ===================================
6181 22:55:34.670778 LPDDR4 DRAM CONFIGURATION
6182 22:55:34.674275 ===================================
6183 22:55:34.677601 EX_ROW_EN[0] = 0x10
6184 22:55:34.678025 EX_ROW_EN[1] = 0x0
6185 22:55:34.680488 LP4Y_EN = 0x0
6186 22:55:34.681092 WORK_FSP = 0x0
6187 22:55:34.683953 WL = 0x2
6188 22:55:34.684373 RL = 0x2
6189 22:55:34.687138 BL = 0x2
6190 22:55:34.687741 RPST = 0x0
6191 22:55:34.690460 RD_PRE = 0x0
6192 22:55:34.691039 WR_PRE = 0x1
6193 22:55:34.694403 WR_PST = 0x0
6194 22:55:34.694822 DBI_WR = 0x0
6195 22:55:34.697455 DBI_RD = 0x0
6196 22:55:34.697875 OTF = 0x1
6197 22:55:34.700791 ===================================
6198 22:55:34.707197 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6199 22:55:34.711736 nWR fixed to 30
6200 22:55:34.715627 [ModeRegInit_LP4] CH0 RK0
6201 22:55:34.716057 [ModeRegInit_LP4] CH0 RK1
6202 22:55:34.718881 [ModeRegInit_LP4] CH1 RK0
6203 22:55:34.722167 [ModeRegInit_LP4] CH1 RK1
6204 22:55:34.722586 match AC timing 19
6205 22:55:34.728831 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6206 22:55:34.732070 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6207 22:55:34.735231 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6208 22:55:34.742229 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6209 22:55:34.745279 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6210 22:55:34.745676 ==
6211 22:55:34.748446 Dram Type= 6, Freq= 0, CH_0, rank 0
6212 22:55:34.752165 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6213 22:55:34.752508 ==
6214 22:55:34.758246 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6215 22:55:34.764965 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6216 22:55:34.768757 [CA 0] Center 36 (8~64) winsize 57
6217 22:55:34.771914 [CA 1] Center 36 (8~64) winsize 57
6218 22:55:34.775389 [CA 2] Center 36 (8~64) winsize 57
6219 22:55:34.778330 [CA 3] Center 36 (8~64) winsize 57
6220 22:55:34.778756 [CA 4] Center 36 (8~64) winsize 57
6221 22:55:34.781689 [CA 5] Center 36 (8~64) winsize 57
6222 22:55:34.782110
6223 22:55:34.788717 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6224 22:55:34.789245
6225 22:55:34.792052 [CATrainingPosCal] consider 1 rank data
6226 22:55:34.795053 u2DelayCellTimex100 = 270/100 ps
6227 22:55:34.799019 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6228 22:55:34.802059 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6229 22:55:34.805222 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6230 22:55:34.808263 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6231 22:55:34.811690 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6232 22:55:34.815308 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6233 22:55:34.815909
6234 22:55:34.818560 CA PerBit enable=1, Macro0, CA PI delay=36
6235 22:55:34.819144
6236 22:55:34.821899 [CBTSetCACLKResult] CA Dly = 36
6237 22:55:34.825013 CS Dly: 1 (0~32)
6238 22:55:34.825434 ==
6239 22:55:34.828742 Dram Type= 6, Freq= 0, CH_0, rank 1
6240 22:55:34.831712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6241 22:55:34.832239 ==
6242 22:55:34.838832 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6243 22:55:34.841527 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6244 22:55:34.844989 [CA 0] Center 36 (8~64) winsize 57
6245 22:55:34.848675 [CA 1] Center 36 (8~64) winsize 57
6246 22:55:34.852310 [CA 2] Center 36 (8~64) winsize 57
6247 22:55:34.855101 [CA 3] Center 36 (8~64) winsize 57
6248 22:55:34.857966 [CA 4] Center 36 (8~64) winsize 57
6249 22:55:34.861335 [CA 5] Center 36 (8~64) winsize 57
6250 22:55:34.861902
6251 22:55:34.865036 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6252 22:55:34.865463
6253 22:55:34.867889 [CATrainingPosCal] consider 2 rank data
6254 22:55:34.871040 u2DelayCellTimex100 = 270/100 ps
6255 22:55:34.874454 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6256 22:55:34.877694 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6257 22:55:34.884415 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6258 22:55:34.887726 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6259 22:55:34.891112 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6260 22:55:34.894599 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6261 22:55:34.895024
6262 22:55:34.898096 CA PerBit enable=1, Macro0, CA PI delay=36
6263 22:55:34.898520
6264 22:55:34.901312 [CBTSetCACLKResult] CA Dly = 36
6265 22:55:34.901736 CS Dly: 1 (0~32)
6266 22:55:34.902088
6267 22:55:34.904972 ----->DramcWriteLeveling(PI) begin...
6268 22:55:34.908315 ==
6269 22:55:34.908847 Dram Type= 6, Freq= 0, CH_0, rank 0
6270 22:55:34.915232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6271 22:55:34.915797 ==
6272 22:55:34.918360 Write leveling (Byte 0): 40 => 8
6273 22:55:34.921231 Write leveling (Byte 1): 32 => 0
6274 22:55:34.924847 DramcWriteLeveling(PI) end<-----
6275 22:55:34.925373
6276 22:55:34.925706 ==
6277 22:55:34.928396 Dram Type= 6, Freq= 0, CH_0, rank 0
6278 22:55:34.931781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6279 22:55:34.932314 ==
6280 22:55:34.934651 [Gating] SW mode calibration
6281 22:55:34.941654 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6282 22:55:34.944680 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6283 22:55:34.951867 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6284 22:55:34.954566 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6285 22:55:34.957774 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6286 22:55:34.964099 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6287 22:55:34.968184 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6288 22:55:34.971223 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6289 22:55:34.977371 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6290 22:55:34.980998 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6291 22:55:34.984687 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6292 22:55:34.987549 Total UI for P1: 0, mck2ui 16
6293 22:55:34.990839 best dqsien dly found for B0: ( 0, 14, 24)
6294 22:55:34.994581 Total UI for P1: 0, mck2ui 16
6295 22:55:34.997348 best dqsien dly found for B1: ( 0, 14, 24)
6296 22:55:35.001023 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6297 22:55:35.004331 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6298 22:55:35.004751
6299 22:55:35.010967 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6300 22:55:35.014469 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6301 22:55:35.017608 [Gating] SW calibration Done
6302 22:55:35.018131 ==
6303 22:55:35.020775 Dram Type= 6, Freq= 0, CH_0, rank 0
6304 22:55:35.024566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6305 22:55:35.025112 ==
6306 22:55:35.025446 RX Vref Scan: 0
6307 22:55:35.025754
6308 22:55:35.027854 RX Vref 0 -> 0, step: 1
6309 22:55:35.028273
6310 22:55:35.030874 RX Delay -410 -> 252, step: 16
6311 22:55:35.033966 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6312 22:55:35.040729 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6313 22:55:35.043812 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6314 22:55:35.047181 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6315 22:55:35.051103 iDelay=230, Bit 4, Center -19 (-266 ~ 229) 496
6316 22:55:35.057097 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6317 22:55:35.060547 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6318 22:55:35.063790 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6319 22:55:35.067008 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6320 22:55:35.073972 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6321 22:55:35.077042 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6322 22:55:35.080783 iDelay=230, Bit 11, Center -43 (-282 ~ 197) 480
6323 22:55:35.083577 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6324 22:55:35.090895 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6325 22:55:35.093743 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6326 22:55:35.097399 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6327 22:55:35.097928 ==
6328 22:55:35.100121 Dram Type= 6, Freq= 0, CH_0, rank 0
6329 22:55:35.103865 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6330 22:55:35.107173 ==
6331 22:55:35.107643 DQS Delay:
6332 22:55:35.107978 DQS0 = 35, DQS1 = 51
6333 22:55:35.110438 DQM Delay:
6334 22:55:35.110854 DQM0 = 7, DQM1 = 11
6335 22:55:35.113481 DQ Delay:
6336 22:55:35.113898 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6337 22:55:35.117143 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6338 22:55:35.120481 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6339 22:55:35.123925 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6340 22:55:35.124344
6341 22:55:35.124759
6342 22:55:35.125073 ==
6343 22:55:35.127229 Dram Type= 6, Freq= 0, CH_0, rank 0
6344 22:55:35.133330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6345 22:55:35.133696 ==
6346 22:55:35.133759
6347 22:55:35.133818
6348 22:55:35.133875 TX Vref Scan disable
6349 22:55:35.136875 == TX Byte 0 ==
6350 22:55:35.139643 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6351 22:55:35.143062 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6352 22:55:35.146470 == TX Byte 1 ==
6353 22:55:35.149953 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6354 22:55:35.153265 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6355 22:55:35.156562 ==
6356 22:55:35.159843 Dram Type= 6, Freq= 0, CH_0, rank 0
6357 22:55:35.163289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6358 22:55:35.163426 ==
6359 22:55:35.163525
6360 22:55:35.163607
6361 22:55:35.166310 TX Vref Scan disable
6362 22:55:35.166423 == TX Byte 0 ==
6363 22:55:35.169843 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6364 22:55:35.176345 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6365 22:55:35.176442 == TX Byte 1 ==
6366 22:55:35.179827 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6367 22:55:35.186511 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6368 22:55:35.186630
6369 22:55:35.186721 [DATLAT]
6370 22:55:35.186804 Freq=400, CH0 RK0
6371 22:55:35.186885
6372 22:55:35.189420 DATLAT Default: 0xf
6373 22:55:35.192798 0, 0xFFFF, sum = 0
6374 22:55:35.192968 1, 0xFFFF, sum = 0
6375 22:55:35.196758 2, 0xFFFF, sum = 0
6376 22:55:35.196899 3, 0xFFFF, sum = 0
6377 22:55:35.199735 4, 0xFFFF, sum = 0
6378 22:55:35.199892 5, 0xFFFF, sum = 0
6379 22:55:35.203178 6, 0xFFFF, sum = 0
6380 22:55:35.203335 7, 0xFFFF, sum = 0
6381 22:55:35.206400 8, 0xFFFF, sum = 0
6382 22:55:35.206598 9, 0xFFFF, sum = 0
6383 22:55:35.209921 10, 0xFFFF, sum = 0
6384 22:55:35.210130 11, 0xFFFF, sum = 0
6385 22:55:35.213267 12, 0xFFFF, sum = 0
6386 22:55:35.213475 13, 0x0, sum = 1
6387 22:55:35.216098 14, 0x0, sum = 2
6388 22:55:35.216347 15, 0x0, sum = 3
6389 22:55:35.220221 16, 0x0, sum = 4
6390 22:55:35.220533 best_step = 14
6391 22:55:35.220773
6392 22:55:35.220998 ==
6393 22:55:35.223035 Dram Type= 6, Freq= 0, CH_0, rank 0
6394 22:55:35.226748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6395 22:55:35.229937 ==
6396 22:55:35.230373 RX Vref Scan: 1
6397 22:55:35.230715
6398 22:55:35.233298 RX Vref 0 -> 0, step: 1
6399 22:55:35.233740
6400 22:55:35.236313 RX Delay -343 -> 252, step: 8
6401 22:55:35.236749
6402 22:55:35.240284 Set Vref, RX VrefLevel [Byte0]: 51
6403 22:55:35.242921 [Byte1]: 52
6404 22:55:35.243380
6405 22:55:35.246323 Final RX Vref Byte 0 = 51 to rank0
6406 22:55:35.249434 Final RX Vref Byte 1 = 52 to rank0
6407 22:55:35.253027 Final RX Vref Byte 0 = 51 to rank1
6408 22:55:35.256308 Final RX Vref Byte 1 = 52 to rank1==
6409 22:55:35.259581 Dram Type= 6, Freq= 0, CH_0, rank 0
6410 22:55:35.262821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6411 22:55:35.263449 ==
6412 22:55:35.266476 DQS Delay:
6413 22:55:35.267067 DQS0 = 40, DQS1 = 60
6414 22:55:35.269350 DQM Delay:
6415 22:55:35.269934 DQM0 = 7, DQM1 = 15
6416 22:55:35.272650 DQ Delay:
6417 22:55:35.273248 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6418 22:55:35.276259 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =12
6419 22:55:35.279447 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =12
6420 22:55:35.282650 DQ12 =20, DQ13 =20, DQ14 =28, DQ15 =28
6421 22:55:35.283221
6422 22:55:35.283789
6423 22:55:35.293016 [DQSOSCAuto] RK0, (LSB)MR18= 0x8e5b, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 392 ps
6424 22:55:35.295954 CH0 RK0: MR19=C0C, MR18=8E5B
6425 22:55:35.299576 CH0_RK0: MR19=0xC0C, MR18=0x8E5B, DQSOSC=392, MR23=63, INC=384, DEC=256
6426 22:55:35.302850 ==
6427 22:55:35.303269 Dram Type= 6, Freq= 0, CH_0, rank 1
6428 22:55:35.309259 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6429 22:55:35.309718 ==
6430 22:55:35.312455 [Gating] SW mode calibration
6431 22:55:35.319596 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6432 22:55:35.322664 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6433 22:55:35.329890 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6434 22:55:35.332705 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6435 22:55:35.336027 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6436 22:55:35.342292 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6437 22:55:35.346228 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6438 22:55:35.349912 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6439 22:55:35.356244 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6440 22:55:35.359071 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6441 22:55:35.362505 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6442 22:55:35.365853 Total UI for P1: 0, mck2ui 16
6443 22:55:35.369505 best dqsien dly found for B0: ( 0, 14, 24)
6444 22:55:35.372560 Total UI for P1: 0, mck2ui 16
6445 22:55:35.375651 best dqsien dly found for B1: ( 0, 14, 24)
6446 22:55:35.380269 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6447 22:55:35.382839 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6448 22:55:35.383258
6449 22:55:35.386002 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6450 22:55:35.393187 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6451 22:55:35.393609 [Gating] SW calibration Done
6452 22:55:35.393944 ==
6453 22:55:35.395830 Dram Type= 6, Freq= 0, CH_0, rank 1
6454 22:55:35.402228 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6455 22:55:35.402654 ==
6456 22:55:35.402987 RX Vref Scan: 0
6457 22:55:35.403297
6458 22:55:35.405658 RX Vref 0 -> 0, step: 1
6459 22:55:35.406076
6460 22:55:35.408983 RX Delay -410 -> 252, step: 16
6461 22:55:35.412399 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6462 22:55:35.415946 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6463 22:55:35.422481 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6464 22:55:35.426050 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6465 22:55:35.429077 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6466 22:55:35.431914 iDelay=230, Bit 5, Center -43 (-282 ~ 197) 480
6467 22:55:35.438696 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6468 22:55:35.442106 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6469 22:55:35.445794 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6470 22:55:35.449052 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6471 22:55:35.455621 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6472 22:55:35.458683 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6473 22:55:35.462292 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6474 22:55:35.465496 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6475 22:55:35.471837 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6476 22:55:35.475234 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6477 22:55:35.475318 ==
6478 22:55:35.478384 Dram Type= 6, Freq= 0, CH_0, rank 1
6479 22:55:35.481768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6480 22:55:35.481888 ==
6481 22:55:35.485000 DQS Delay:
6482 22:55:35.485088 DQS0 = 43, DQS1 = 51
6483 22:55:35.488616 DQM Delay:
6484 22:55:35.488693 DQM0 = 11, DQM1 = 10
6485 22:55:35.488758 DQ Delay:
6486 22:55:35.491860 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6487 22:55:35.494906 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =24
6488 22:55:35.498649 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6489 22:55:35.501814 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6490 22:55:35.501923
6491 22:55:35.502023
6492 22:55:35.502123 ==
6493 22:55:35.505320 Dram Type= 6, Freq= 0, CH_0, rank 1
6494 22:55:35.508552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6495 22:55:35.511919 ==
6496 22:55:35.512010
6497 22:55:35.512086
6498 22:55:35.512156 TX Vref Scan disable
6499 22:55:35.515191 == TX Byte 0 ==
6500 22:55:35.518388 Update DQ dly =586 (4 ,2, 10) DQ OEN =(3 ,3)
6501 22:55:35.521692 Update DQM dly =586 (4 ,2, 10) DQM OEN =(3 ,3)
6502 22:55:35.524847 == TX Byte 1 ==
6503 22:55:35.528652 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6504 22:55:35.531821 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6505 22:55:35.532196 ==
6506 22:55:35.535627 Dram Type= 6, Freq= 0, CH_0, rank 1
6507 22:55:35.541609 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6508 22:55:35.542065 ==
6509 22:55:35.542452
6510 22:55:35.542768
6511 22:55:35.543067 TX Vref Scan disable
6512 22:55:35.545086 == TX Byte 0 ==
6513 22:55:35.548412 Update DQ dly =586 (4 ,2, 10) DQ OEN =(3 ,3)
6514 22:55:35.552153 Update DQM dly =586 (4 ,2, 10) DQM OEN =(3 ,3)
6515 22:55:35.555582 == TX Byte 1 ==
6516 22:55:35.558458 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6517 22:55:35.561749 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6518 22:55:35.562230
6519 22:55:35.565459 [DATLAT]
6520 22:55:35.566052 Freq=400, CH0 RK1
6521 22:55:35.566564
6522 22:55:35.568273 DATLAT Default: 0xe
6523 22:55:35.568852 0, 0xFFFF, sum = 0
6524 22:55:35.571500 1, 0xFFFF, sum = 0
6525 22:55:35.572030 2, 0xFFFF, sum = 0
6526 22:55:35.574886 3, 0xFFFF, sum = 0
6527 22:55:35.575515 4, 0xFFFF, sum = 0
6528 22:55:35.578223 5, 0xFFFF, sum = 0
6529 22:55:35.578798 6, 0xFFFF, sum = 0
6530 22:55:35.581498 7, 0xFFFF, sum = 0
6531 22:55:35.581905 8, 0xFFFF, sum = 0
6532 22:55:35.584716 9, 0xFFFF, sum = 0
6533 22:55:35.588440 10, 0xFFFF, sum = 0
6534 22:55:35.588686 11, 0xFFFF, sum = 0
6535 22:55:35.591320 12, 0xFFFF, sum = 0
6536 22:55:35.591573 13, 0x0, sum = 1
6537 22:55:35.594890 14, 0x0, sum = 2
6538 22:55:35.595123 15, 0x0, sum = 3
6539 22:55:35.595308 16, 0x0, sum = 4
6540 22:55:35.598019 best_step = 14
6541 22:55:35.598245
6542 22:55:35.598422 ==
6543 22:55:35.601633 Dram Type= 6, Freq= 0, CH_0, rank 1
6544 22:55:35.604717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6545 22:55:35.604947 ==
6546 22:55:35.608424 RX Vref Scan: 0
6547 22:55:35.608652
6548 22:55:35.608829 RX Vref 0 -> 0, step: 1
6549 22:55:35.611369
6550 22:55:35.611595 RX Delay -343 -> 252, step: 8
6551 22:55:35.619734 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6552 22:55:35.622882 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6553 22:55:35.626795 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6554 22:55:35.630034 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6555 22:55:35.637099 iDelay=217, Bit 4, Center -36 (-271 ~ 200) 472
6556 22:55:35.640481 iDelay=217, Bit 5, Center -48 (-287 ~ 192) 480
6557 22:55:35.643900 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6558 22:55:35.646845 iDelay=217, Bit 7, Center -28 (-263 ~ 208) 472
6559 22:55:35.653347 iDelay=217, Bit 8, Center -56 (-295 ~ 184) 480
6560 22:55:35.656709 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
6561 22:55:35.659930 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6562 22:55:35.663095 iDelay=217, Bit 11, Center -56 (-295 ~ 184) 480
6563 22:55:35.670042 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6564 22:55:35.673126 iDelay=217, Bit 13, Center -40 (-279 ~ 200) 480
6565 22:55:35.676363 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6566 22:55:35.683776 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6567 22:55:35.684213 ==
6568 22:55:35.686917 Dram Type= 6, Freq= 0, CH_0, rank 1
6569 22:55:35.690290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6570 22:55:35.690828 ==
6571 22:55:35.691272 DQS Delay:
6572 22:55:35.693495 DQS0 = 48, DQS1 = 56
6573 22:55:35.694033 DQM Delay:
6574 22:55:35.696426 DQM0 = 13, DQM1 = 10
6575 22:55:35.696860 DQ Delay:
6576 22:55:35.700441 DQ0 =16, DQ1 =16, DQ2 =8, DQ3 =12
6577 22:55:35.703093 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6578 22:55:35.706633 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =0
6579 22:55:35.710543 DQ12 =12, DQ13 =16, DQ14 =20, DQ15 =20
6580 22:55:35.711079
6581 22:55:35.711583
6582 22:55:35.716648 [DQSOSCAuto] RK1, (LSB)MR18= 0x9263, (MSB)MR19= 0xc0c, tDQSOscB0 = 397 ps tDQSOscB1 = 391 ps
6583 22:55:35.720145 CH0 RK1: MR19=C0C, MR18=9263
6584 22:55:35.726372 CH0_RK1: MR19=0xC0C, MR18=0x9263, DQSOSC=391, MR23=63, INC=386, DEC=257
6585 22:55:35.729685 [RxdqsGatingPostProcess] freq 400
6586 22:55:35.736791 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6587 22:55:35.737318 best DQS0 dly(2T, 0.5T) = (0, 10)
6588 22:55:35.740090 best DQS1 dly(2T, 0.5T) = (0, 10)
6589 22:55:35.743590 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6590 22:55:35.746610 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6591 22:55:35.750393 best DQS0 dly(2T, 0.5T) = (0, 10)
6592 22:55:35.753149 best DQS1 dly(2T, 0.5T) = (0, 10)
6593 22:55:35.757032 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6594 22:55:35.760029 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6595 22:55:35.762755 Pre-setting of DQS Precalculation
6596 22:55:35.769888 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6597 22:55:35.770415 ==
6598 22:55:35.773238 Dram Type= 6, Freq= 0, CH_1, rank 0
6599 22:55:35.776174 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6600 22:55:35.776608 ==
6601 22:55:35.783211 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6602 22:55:35.786302 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6603 22:55:35.790312 [CA 0] Center 36 (8~64) winsize 57
6604 22:55:35.793336 [CA 1] Center 36 (8~64) winsize 57
6605 22:55:35.796395 [CA 2] Center 36 (8~64) winsize 57
6606 22:55:35.800191 [CA 3] Center 36 (8~64) winsize 57
6607 22:55:35.802762 [CA 4] Center 36 (8~64) winsize 57
6608 22:55:35.806698 [CA 5] Center 36 (8~64) winsize 57
6609 22:55:35.807225
6610 22:55:35.809846 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6611 22:55:35.810387
6612 22:55:35.812760 [CATrainingPosCal] consider 1 rank data
6613 22:55:35.816216 u2DelayCellTimex100 = 270/100 ps
6614 22:55:35.819695 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6615 22:55:35.822740 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6616 22:55:35.826509 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6617 22:55:35.829688 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6618 22:55:35.836032 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6619 22:55:35.839209 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6620 22:55:35.839680
6621 22:55:35.842603 CA PerBit enable=1, Macro0, CA PI delay=36
6622 22:55:35.843024
6623 22:55:35.846520 [CBTSetCACLKResult] CA Dly = 36
6624 22:55:35.846941 CS Dly: 1 (0~32)
6625 22:55:35.847288 ==
6626 22:55:35.849486 Dram Type= 6, Freq= 0, CH_1, rank 1
6627 22:55:35.856209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6628 22:55:35.856726 ==
6629 22:55:35.859802 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6630 22:55:35.866728 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6631 22:55:35.869519 [CA 0] Center 36 (8~64) winsize 57
6632 22:55:35.873435 [CA 1] Center 36 (8~64) winsize 57
6633 22:55:35.876264 [CA 2] Center 36 (8~64) winsize 57
6634 22:55:35.879503 [CA 3] Center 36 (8~64) winsize 57
6635 22:55:35.882753 [CA 4] Center 36 (8~64) winsize 57
6636 22:55:35.886211 [CA 5] Center 36 (8~64) winsize 57
6637 22:55:35.886630
6638 22:55:35.889777 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6639 22:55:35.890301
6640 22:55:35.893177 [CATrainingPosCal] consider 2 rank data
6641 22:55:35.896304 u2DelayCellTimex100 = 270/100 ps
6642 22:55:35.899210 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6643 22:55:35.902694 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6644 22:55:35.906727 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6645 22:55:35.909947 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6646 22:55:35.913188 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6647 22:55:35.915938 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6648 22:55:35.916458
6649 22:55:35.922768 CA PerBit enable=1, Macro0, CA PI delay=36
6650 22:55:35.923324
6651 22:55:35.923713 [CBTSetCACLKResult] CA Dly = 36
6652 22:55:35.926274 CS Dly: 1 (0~32)
6653 22:55:35.926806
6654 22:55:35.929652 ----->DramcWriteLeveling(PI) begin...
6655 22:55:35.930185 ==
6656 22:55:35.932202 Dram Type= 6, Freq= 0, CH_1, rank 0
6657 22:55:35.936143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6658 22:55:35.936661 ==
6659 22:55:35.939460 Write leveling (Byte 0): 40 => 8
6660 22:55:35.942574 Write leveling (Byte 1): 40 => 8
6661 22:55:35.946122 DramcWriteLeveling(PI) end<-----
6662 22:55:35.946646
6663 22:55:35.946978 ==
6664 22:55:35.949400 Dram Type= 6, Freq= 0, CH_1, rank 0
6665 22:55:35.952407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6666 22:55:35.952919 ==
6667 22:55:35.956033 [Gating] SW mode calibration
6668 22:55:35.962549 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6669 22:55:35.969534 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6670 22:55:35.972064 0 11 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
6671 22:55:35.979461 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6672 22:55:35.982409 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6673 22:55:35.985787 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6674 22:55:35.992049 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6675 22:55:35.995546 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6676 22:55:35.998898 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6677 22:55:36.005539 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6678 22:55:36.008921 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6679 22:55:36.012215 Total UI for P1: 0, mck2ui 16
6680 22:55:36.015761 best dqsien dly found for B0: ( 0, 14, 24)
6681 22:55:36.019108 Total UI for P1: 0, mck2ui 16
6682 22:55:36.022558 best dqsien dly found for B1: ( 0, 14, 24)
6683 22:55:36.025977 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6684 22:55:36.029541 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6685 22:55:36.030078
6686 22:55:36.032208 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6687 22:55:36.036341 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6688 22:55:36.039597 [Gating] SW calibration Done
6689 22:55:36.040144 ==
6690 22:55:36.042511 Dram Type= 6, Freq= 0, CH_1, rank 0
6691 22:55:36.045633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6692 22:55:36.046255 ==
6693 22:55:36.048594 RX Vref Scan: 0
6694 22:55:36.049056
6695 22:55:36.051794 RX Vref 0 -> 0, step: 1
6696 22:55:36.052236
6697 22:55:36.055516 RX Delay -410 -> 252, step: 16
6698 22:55:36.058426 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6699 22:55:36.061746 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6700 22:55:36.065672 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6701 22:55:36.071749 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6702 22:55:36.074990 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6703 22:55:36.078988 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6704 22:55:36.081991 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6705 22:55:36.088600 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6706 22:55:36.091595 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6707 22:55:36.094952 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6708 22:55:36.098683 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6709 22:55:36.104946 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6710 22:55:36.108384 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6711 22:55:36.111837 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6712 22:55:36.114854 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6713 22:55:36.121644 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6714 22:55:36.121727 ==
6715 22:55:36.124497 Dram Type= 6, Freq= 0, CH_1, rank 0
6716 22:55:36.127846 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6717 22:55:36.127929 ==
6718 22:55:36.127995 DQS Delay:
6719 22:55:36.131186 DQS0 = 51, DQS1 = 59
6720 22:55:36.131268 DQM Delay:
6721 22:55:36.134169 DQM0 = 19, DQM1 = 17
6722 22:55:36.134251 DQ Delay:
6723 22:55:36.137655 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6724 22:55:36.141716 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6725 22:55:36.144440 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6726 22:55:36.147809 DQ12 =32, DQ13 =24, DQ14 =24, DQ15 =24
6727 22:55:36.147891
6728 22:55:36.147955
6729 22:55:36.148014 ==
6730 22:55:36.150908 Dram Type= 6, Freq= 0, CH_1, rank 0
6731 22:55:36.154294 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6732 22:55:36.157922 ==
6733 22:55:36.158004
6734 22:55:36.158069
6735 22:55:36.158129 TX Vref Scan disable
6736 22:55:36.161097 == TX Byte 0 ==
6737 22:55:36.164233 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6738 22:55:36.167598 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6739 22:55:36.170780 == TX Byte 1 ==
6740 22:55:36.174543 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6741 22:55:36.177693 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6742 22:55:36.177776 ==
6743 22:55:36.180663 Dram Type= 6, Freq= 0, CH_1, rank 0
6744 22:55:36.184025 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6745 22:55:36.187789 ==
6746 22:55:36.187871
6747 22:55:36.187934
6748 22:55:36.187994 TX Vref Scan disable
6749 22:55:36.190831 == TX Byte 0 ==
6750 22:55:36.194259 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6751 22:55:36.197526 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6752 22:55:36.200819 == TX Byte 1 ==
6753 22:55:36.204114 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6754 22:55:36.207784 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6755 22:55:36.207867
6756 22:55:36.210756 [DATLAT]
6757 22:55:36.210838 Freq=400, CH1 RK0
6758 22:55:36.210904
6759 22:55:36.214651 DATLAT Default: 0xf
6760 22:55:36.214737 0, 0xFFFF, sum = 0
6761 22:55:36.217305 1, 0xFFFF, sum = 0
6762 22:55:36.217389 2, 0xFFFF, sum = 0
6763 22:55:36.220503 3, 0xFFFF, sum = 0
6764 22:55:36.220587 4, 0xFFFF, sum = 0
6765 22:55:36.223877 5, 0xFFFF, sum = 0
6766 22:55:36.223961 6, 0xFFFF, sum = 0
6767 22:55:36.227317 7, 0xFFFF, sum = 0
6768 22:55:36.227406 8, 0xFFFF, sum = 0
6769 22:55:36.230588 9, 0xFFFF, sum = 0
6770 22:55:36.230671 10, 0xFFFF, sum = 0
6771 22:55:36.234118 11, 0xFFFF, sum = 0
6772 22:55:36.234202 12, 0xFFFF, sum = 0
6773 22:55:36.237267 13, 0x0, sum = 1
6774 22:55:36.237351 14, 0x0, sum = 2
6775 22:55:36.240335 15, 0x0, sum = 3
6776 22:55:36.240419 16, 0x0, sum = 4
6777 22:55:36.243744 best_step = 14
6778 22:55:36.243826
6779 22:55:36.243890 ==
6780 22:55:36.247629 Dram Type= 6, Freq= 0, CH_1, rank 0
6781 22:55:36.250727 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6782 22:55:36.250811 ==
6783 22:55:36.254415 RX Vref Scan: 1
6784 22:55:36.254498
6785 22:55:36.254562 RX Vref 0 -> 0, step: 1
6786 22:55:36.254624
6787 22:55:36.257082 RX Delay -359 -> 252, step: 8
6788 22:55:36.257165
6789 22:55:36.260827 Set Vref, RX VrefLevel [Byte0]: 55
6790 22:55:36.263906 [Byte1]: 51
6791 22:55:36.269060
6792 22:55:36.269143 Final RX Vref Byte 0 = 55 to rank0
6793 22:55:36.272095 Final RX Vref Byte 1 = 51 to rank0
6794 22:55:36.275162 Final RX Vref Byte 0 = 55 to rank1
6795 22:55:36.278754 Final RX Vref Byte 1 = 51 to rank1==
6796 22:55:36.282101 Dram Type= 6, Freq= 0, CH_1, rank 0
6797 22:55:36.288595 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6798 22:55:36.288678 ==
6799 22:55:36.288744 DQS Delay:
6800 22:55:36.292032 DQS0 = 48, DQS1 = 60
6801 22:55:36.292115 DQM Delay:
6802 22:55:36.292181 DQM0 = 13, DQM1 = 12
6803 22:55:36.295126 DQ Delay:
6804 22:55:36.298644 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6805 22:55:36.301923 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
6806 22:55:36.302046 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
6807 22:55:36.305311 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6808 22:55:36.308265
6809 22:55:36.308346
6810 22:55:36.315081 [DQSOSCAuto] RK0, (LSB)MR18= 0x8a33, (MSB)MR19= 0xc0c, tDQSOscB0 = 403 ps tDQSOscB1 = 392 ps
6811 22:55:36.318466 CH1 RK0: MR19=C0C, MR18=8A33
6812 22:55:36.324730 CH1_RK0: MR19=0xC0C, MR18=0x8A33, DQSOSC=392, MR23=63, INC=384, DEC=256
6813 22:55:36.324813 ==
6814 22:55:36.328088 Dram Type= 6, Freq= 0, CH_1, rank 1
6815 22:55:36.331825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6816 22:55:36.331908 ==
6817 22:55:36.335273 [Gating] SW mode calibration
6818 22:55:36.341399 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6819 22:55:36.348169 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6820 22:55:36.351755 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6821 22:55:36.354694 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6822 22:55:36.361192 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6823 22:55:36.364903 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6824 22:55:36.368108 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6825 22:55:36.374749 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6826 22:55:36.377847 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6827 22:55:36.381457 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6828 22:55:36.388127 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6829 22:55:36.388210 Total UI for P1: 0, mck2ui 16
6830 22:55:36.391249 best dqsien dly found for B0: ( 0, 14, 24)
6831 22:55:36.394670 Total UI for P1: 0, mck2ui 16
6832 22:55:36.398655 best dqsien dly found for B1: ( 0, 14, 24)
6833 22:55:36.404585 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6834 22:55:36.407937 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6835 22:55:36.408021
6836 22:55:36.411130 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6837 22:55:36.414890 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6838 22:55:36.417883 [Gating] SW calibration Done
6839 22:55:36.417965 ==
6840 22:55:36.421348 Dram Type= 6, Freq= 0, CH_1, rank 1
6841 22:55:36.424790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6842 22:55:36.424873 ==
6843 22:55:36.427640 RX Vref Scan: 0
6844 22:55:36.427722
6845 22:55:36.427787 RX Vref 0 -> 0, step: 1
6846 22:55:36.427846
6847 22:55:36.431777 RX Delay -410 -> 252, step: 16
6848 22:55:36.435083 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6849 22:55:36.441335 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6850 22:55:36.444654 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6851 22:55:36.448155 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6852 22:55:36.451133 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6853 22:55:36.457588 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6854 22:55:36.460911 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6855 22:55:36.464308 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6856 22:55:36.468456 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6857 22:55:36.474043 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6858 22:55:36.477679 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6859 22:55:36.480747 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6860 22:55:36.487310 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6861 22:55:36.491023 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6862 22:55:36.494071 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6863 22:55:36.497468 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6864 22:55:36.497541 ==
6865 22:55:36.501241 Dram Type= 6, Freq= 0, CH_1, rank 1
6866 22:55:36.507358 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6867 22:55:36.507478 ==
6868 22:55:36.507542 DQS Delay:
6869 22:55:36.510735 DQS0 = 43, DQS1 = 51
6870 22:55:36.510829 DQM Delay:
6871 22:55:36.514015 DQM0 = 10, DQM1 = 11
6872 22:55:36.514096 DQ Delay:
6873 22:55:36.517879 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6874 22:55:36.521050 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6875 22:55:36.521133 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6876 22:55:36.524303 DQ12 =16, DQ13 =24, DQ14 =16, DQ15 =24
6877 22:55:36.524386
6878 22:55:36.527691
6879 22:55:36.527773 ==
6880 22:55:36.530667 Dram Type= 6, Freq= 0, CH_1, rank 1
6881 22:55:36.534164 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6882 22:55:36.534246 ==
6883 22:55:36.534312
6884 22:55:36.534371
6885 22:55:36.537333 TX Vref Scan disable
6886 22:55:36.537415 == TX Byte 0 ==
6887 22:55:36.540681 Update DQ dly =586 (4 ,2, 10) DQ OEN =(3 ,3)
6888 22:55:36.547698 Update DQM dly =586 (4 ,2, 10) DQM OEN =(3 ,3)
6889 22:55:36.547805 == TX Byte 1 ==
6890 22:55:36.551297 Update DQ dly =586 (4 ,2, 10) DQ OEN =(3 ,3)
6891 22:55:36.557287 Update DQM dly =586 (4 ,2, 10) DQM OEN =(3 ,3)
6892 22:55:36.557472 ==
6893 22:55:36.560457 Dram Type= 6, Freq= 0, CH_1, rank 1
6894 22:55:36.563907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6895 22:55:36.563988 ==
6896 22:55:36.564055
6897 22:55:36.564120
6898 22:55:36.567032 TX Vref Scan disable
6899 22:55:36.567106 == TX Byte 0 ==
6900 22:55:36.574047 Update DQ dly =586 (4 ,2, 10) DQ OEN =(3 ,3)
6901 22:55:36.577378 Update DQM dly =586 (4 ,2, 10) DQM OEN =(3 ,3)
6902 22:55:36.577463 == TX Byte 1 ==
6903 22:55:36.584361 Update DQ dly =586 (4 ,2, 10) DQ OEN =(3 ,3)
6904 22:55:36.587483 Update DQM dly =586 (4 ,2, 10) DQM OEN =(3 ,3)
6905 22:55:36.587579
6906 22:55:36.587675 [DATLAT]
6907 22:55:36.590539 Freq=400, CH1 RK1
6908 22:55:36.590644
6909 22:55:36.590748 DATLAT Default: 0xe
6910 22:55:36.593894 0, 0xFFFF, sum = 0
6911 22:55:36.594082 1, 0xFFFF, sum = 0
6912 22:55:36.597564 2, 0xFFFF, sum = 0
6913 22:55:36.597762 3, 0xFFFF, sum = 0
6914 22:55:36.600648 4, 0xFFFF, sum = 0
6915 22:55:36.600831 5, 0xFFFF, sum = 0
6916 22:55:36.604142 6, 0xFFFF, sum = 0
6917 22:55:36.604339 7, 0xFFFF, sum = 0
6918 22:55:36.607525 8, 0xFFFF, sum = 0
6919 22:55:36.607761 9, 0xFFFF, sum = 0
6920 22:55:36.611346 10, 0xFFFF, sum = 0
6921 22:55:36.611606 11, 0xFFFF, sum = 0
6922 22:55:36.614126 12, 0xFFFF, sum = 0
6923 22:55:36.614396 13, 0x0, sum = 1
6924 22:55:36.617182 14, 0x0, sum = 2
6925 22:55:36.617426 15, 0x0, sum = 3
6926 22:55:36.621751 16, 0x0, sum = 4
6927 22:55:36.622293 best_step = 14
6928 22:55:36.622733
6929 22:55:36.623236 ==
6930 22:55:36.624039 Dram Type= 6, Freq= 0, CH_1, rank 1
6931 22:55:36.631134 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6932 22:55:36.631720 ==
6933 22:55:36.632170 RX Vref Scan: 0
6934 22:55:36.632584
6935 22:55:36.634255 RX Vref 0 -> 0, step: 1
6936 22:55:36.634797
6937 22:55:36.637699 RX Delay -343 -> 252, step: 8
6938 22:55:36.644620 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6939 22:55:36.647833 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
6940 22:55:36.650823 iDelay=217, Bit 2, Center -52 (-295 ~ 192) 488
6941 22:55:36.654636 iDelay=217, Bit 3, Center -40 (-279 ~ 200) 480
6942 22:55:36.660665 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6943 22:55:36.663881 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6944 22:55:36.667458 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6945 22:55:36.671004 iDelay=217, Bit 7, Center -44 (-287 ~ 200) 488
6946 22:55:36.677672 iDelay=217, Bit 8, Center -60 (-311 ~ 192) 504
6947 22:55:36.680743 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6948 22:55:36.683971 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6949 22:55:36.687643 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6950 22:55:36.693570 iDelay=217, Bit 12, Center -40 (-279 ~ 200) 480
6951 22:55:36.697030 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6952 22:55:36.700357 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6953 22:55:36.707507 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6954 22:55:36.707937 ==
6955 22:55:36.710332 Dram Type= 6, Freq= 0, CH_1, rank 1
6956 22:55:36.714281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6957 22:55:36.714707 ==
6958 22:55:36.715045 DQS Delay:
6959 22:55:36.717075 DQS0 = 52, DQS1 = 60
6960 22:55:36.717502 DQM Delay:
6961 22:55:36.720913 DQM0 = 13, DQM1 = 12
6962 22:55:36.721486 DQ Delay:
6963 22:55:36.723904 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6964 22:55:36.727163 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =8
6965 22:55:36.730805 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
6966 22:55:36.733727 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6967 22:55:36.734259
6968 22:55:36.734599
6969 22:55:36.740315 [DQSOSCAuto] RK1, (LSB)MR18= 0x788e, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 394 ps
6970 22:55:36.743950 CH1 RK1: MR19=C0C, MR18=788E
6971 22:55:36.750453 CH1_RK1: MR19=0xC0C, MR18=0x788E, DQSOSC=392, MR23=63, INC=384, DEC=256
6972 22:55:36.754097 [RxdqsGatingPostProcess] freq 400
6973 22:55:36.760222 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6974 22:55:36.763346 best DQS0 dly(2T, 0.5T) = (0, 10)
6975 22:55:36.764030 best DQS1 dly(2T, 0.5T) = (0, 10)
6976 22:55:36.766977 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6977 22:55:36.770920 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6978 22:55:36.773926 best DQS0 dly(2T, 0.5T) = (0, 10)
6979 22:55:36.777198 best DQS1 dly(2T, 0.5T) = (0, 10)
6980 22:55:36.780314 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6981 22:55:36.783336 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6982 22:55:36.786740 Pre-setting of DQS Precalculation
6983 22:55:36.793193 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6984 22:55:36.800118 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6985 22:55:36.806444 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6986 22:55:36.806872
6987 22:55:36.807205
6988 22:55:36.810128 [Calibration Summary] 800 Mbps
6989 22:55:36.810553 CH 0, Rank 0
6990 22:55:36.813508 SW Impedance : PASS
6991 22:55:36.817090 DUTY Scan : NO K
6992 22:55:36.817617 ZQ Calibration : PASS
6993 22:55:36.819814 Jitter Meter : NO K
6994 22:55:36.820241 CBT Training : PASS
6995 22:55:36.823425 Write leveling : PASS
6996 22:55:36.826433 RX DQS gating : PASS
6997 22:55:36.826858 RX DQ/DQS(RDDQC) : PASS
6998 22:55:36.829619 TX DQ/DQS : PASS
6999 22:55:36.833488 RX DATLAT : PASS
7000 22:55:36.834016 RX DQ/DQS(Engine): PASS
7001 22:55:36.836606 TX OE : NO K
7002 22:55:36.837032 All Pass.
7003 22:55:36.837430
7004 22:55:36.840495 CH 0, Rank 1
7005 22:55:36.841028 SW Impedance : PASS
7006 22:55:36.843185 DUTY Scan : NO K
7007 22:55:36.846763 ZQ Calibration : PASS
7008 22:55:36.847297 Jitter Meter : NO K
7009 22:55:36.849849 CBT Training : PASS
7010 22:55:36.853203 Write leveling : NO K
7011 22:55:36.853730 RX DQS gating : PASS
7012 22:55:36.856619 RX DQ/DQS(RDDQC) : PASS
7013 22:55:36.859683 TX DQ/DQS : PASS
7014 22:55:36.860116 RX DATLAT : PASS
7015 22:55:36.862937 RX DQ/DQS(Engine): PASS
7016 22:55:36.866699 TX OE : NO K
7017 22:55:36.867131 All Pass.
7018 22:55:36.867516
7019 22:55:36.867836 CH 1, Rank 0
7020 22:55:36.869692 SW Impedance : PASS
7021 22:55:36.873785 DUTY Scan : NO K
7022 22:55:36.874314 ZQ Calibration : PASS
7023 22:55:36.876621 Jitter Meter : NO K
7024 22:55:36.877154 CBT Training : PASS
7025 22:55:36.879733 Write leveling : PASS
7026 22:55:36.883213 RX DQS gating : PASS
7027 22:55:36.883718 RX DQ/DQS(RDDQC) : PASS
7028 22:55:36.886134 TX DQ/DQS : PASS
7029 22:55:36.889889 RX DATLAT : PASS
7030 22:55:36.890420 RX DQ/DQS(Engine): PASS
7031 22:55:36.892912 TX OE : NO K
7032 22:55:36.893369 All Pass.
7033 22:55:36.893711
7034 22:55:36.896387 CH 1, Rank 1
7035 22:55:36.896810 SW Impedance : PASS
7036 22:55:36.899806 DUTY Scan : NO K
7037 22:55:36.903222 ZQ Calibration : PASS
7038 22:55:36.903840 Jitter Meter : NO K
7039 22:55:36.906112 CBT Training : PASS
7040 22:55:36.909573 Write leveling : NO K
7041 22:55:36.910102 RX DQS gating : PASS
7042 22:55:36.912896 RX DQ/DQS(RDDQC) : PASS
7043 22:55:36.916211 TX DQ/DQS : PASS
7044 22:55:36.916732 RX DATLAT : PASS
7045 22:55:36.919601 RX DQ/DQS(Engine): PASS
7046 22:55:36.922622 TX OE : NO K
7047 22:55:36.923160 All Pass.
7048 22:55:36.923571
7049 22:55:36.923892 DramC Write-DBI off
7050 22:55:36.926533 PER_BANK_REFRESH: Hybrid Mode
7051 22:55:36.929424 TX_TRACKING: ON
7052 22:55:36.935817 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7053 22:55:36.939164 [FAST_K] Save calibration result to emmc
7054 22:55:36.945858 dramc_set_vcore_voltage set vcore to 725000
7055 22:55:36.946380 Read voltage for 1600, 0
7056 22:55:36.949497 Vio18 = 0
7057 22:55:36.949963 Vcore = 725000
7058 22:55:36.950304 Vdram = 0
7059 22:55:36.952411 Vddq = 0
7060 22:55:36.952837 Vmddr = 0
7061 22:55:36.955654 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7062 22:55:36.962980 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7063 22:55:36.966193 MEM_TYPE=3, freq_sel=13
7064 22:55:36.966629 sv_algorithm_assistance_LP4_3733
7065 22:55:36.972708 ============ PULL DRAM RESETB DOWN ============
7066 22:55:36.976062 ========== PULL DRAM RESETB DOWN end =========
7067 22:55:36.979744 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7068 22:55:36.982856 ===================================
7069 22:55:36.985793 LPDDR4 DRAM CONFIGURATION
7070 22:55:36.989294 ===================================
7071 22:55:36.992378 EX_ROW_EN[0] = 0x0
7072 22:55:36.992815 EX_ROW_EN[1] = 0x0
7073 22:55:36.996044 LP4Y_EN = 0x0
7074 22:55:36.996569 WORK_FSP = 0x1
7075 22:55:36.999460 WL = 0x5
7076 22:55:36.999991 RL = 0x5
7077 22:55:37.002584 BL = 0x2
7078 22:55:37.003147 RPST = 0x0
7079 22:55:37.005568 RD_PRE = 0x0
7080 22:55:37.006182 WR_PRE = 0x1
7081 22:55:37.009212 WR_PST = 0x1
7082 22:55:37.009797 DBI_WR = 0x0
7083 22:55:37.012996 DBI_RD = 0x0
7084 22:55:37.015629 OTF = 0x1
7085 22:55:37.016064 ===================================
7086 22:55:37.018901 ===================================
7087 22:55:37.022366 ANA top config
7088 22:55:37.025976 ===================================
7089 22:55:37.028863 DLL_ASYNC_EN = 0
7090 22:55:37.029295 ALL_SLAVE_EN = 0
7091 22:55:37.032033 NEW_RANK_MODE = 1
7092 22:55:37.035585 DLL_IDLE_MODE = 1
7093 22:55:37.038896 LP45_APHY_COMB_EN = 1
7094 22:55:37.042291 TX_ODT_DIS = 0
7095 22:55:37.042824 NEW_8X_MODE = 1
7096 22:55:37.045724 ===================================
7097 22:55:37.048980 ===================================
7098 22:55:37.052757 data_rate = 3200
7099 22:55:37.055974 CKR = 1
7100 22:55:37.059236 DQ_P2S_RATIO = 8
7101 22:55:37.062297 ===================================
7102 22:55:37.065205 CA_P2S_RATIO = 8
7103 22:55:37.068799 DQ_CA_OPEN = 0
7104 22:55:37.069222 DQ_SEMI_OPEN = 0
7105 22:55:37.072394 CA_SEMI_OPEN = 0
7106 22:55:37.075751 CA_FULL_RATE = 0
7107 22:55:37.079063 DQ_CKDIV4_EN = 0
7108 22:55:37.081937 CA_CKDIV4_EN = 0
7109 22:55:37.085085 CA_PREDIV_EN = 0
7110 22:55:37.085511 PH8_DLY = 12
7111 22:55:37.089238 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7112 22:55:37.091910 DQ_AAMCK_DIV = 4
7113 22:55:37.095935 CA_AAMCK_DIV = 4
7114 22:55:37.098955 CA_ADMCK_DIV = 4
7115 22:55:37.101822 DQ_TRACK_CA_EN = 0
7116 22:55:37.102258 CA_PICK = 1600
7117 22:55:37.105121 CA_MCKIO = 1600
7118 22:55:37.108861 MCKIO_SEMI = 0
7119 22:55:37.111878 PLL_FREQ = 3068
7120 22:55:37.115482 DQ_UI_PI_RATIO = 32
7121 22:55:37.118882 CA_UI_PI_RATIO = 0
7122 22:55:37.121783 ===================================
7123 22:55:37.125135 ===================================
7124 22:55:37.128474 memory_type:LPDDR4
7125 22:55:37.128960 GP_NUM : 10
7126 22:55:37.131702 SRAM_EN : 1
7127 22:55:37.132164 MD32_EN : 0
7128 22:55:37.135526 ===================================
7129 22:55:37.138350 [ANA_INIT] >>>>>>>>>>>>>>
7130 22:55:37.141333 <<<<<< [CONFIGURE PHASE]: ANA_TX
7131 22:55:37.144974 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7132 22:55:37.148152 ===================================
7133 22:55:37.151841 data_rate = 3200,PCW = 0X7600
7134 22:55:37.155321 ===================================
7135 22:55:37.158816 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7136 22:55:37.161823 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7137 22:55:37.167994 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7138 22:55:37.175687 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7139 22:55:37.178105 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7140 22:55:37.181760 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7141 22:55:37.182298 [ANA_INIT] flow start
7142 22:55:37.184401 [ANA_INIT] PLL >>>>>>>>
7143 22:55:37.188415 [ANA_INIT] PLL <<<<<<<<
7144 22:55:37.188839 [ANA_INIT] MIDPI >>>>>>>>
7145 22:55:37.192046 [ANA_INIT] MIDPI <<<<<<<<
7146 22:55:37.194870 [ANA_INIT] DLL >>>>>>>>
7147 22:55:37.195466 [ANA_INIT] DLL <<<<<<<<
7148 22:55:37.197873 [ANA_INIT] flow end
7149 22:55:37.201405 ============ LP4 DIFF to SE enter ============
7150 22:55:37.204738 ============ LP4 DIFF to SE exit ============
7151 22:55:37.208270 [ANA_INIT] <<<<<<<<<<<<<
7152 22:55:37.211996 [Flow] Enable top DCM control >>>>>
7153 22:55:37.214699 [Flow] Enable top DCM control <<<<<
7154 22:55:37.217792 Enable DLL master slave shuffle
7155 22:55:37.224782 ==============================================================
7156 22:55:37.225316 Gating Mode config
7157 22:55:37.231490 ==============================================================
7158 22:55:37.232036 Config description:
7159 22:55:37.241225 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7160 22:55:37.247778 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7161 22:55:37.254955 SELPH_MODE 0: By rank 1: By Phase
7162 22:55:37.257899 ==============================================================
7163 22:55:37.261326 GAT_TRACK_EN = 1
7164 22:55:37.264441 RX_GATING_MODE = 2
7165 22:55:37.267874 RX_GATING_TRACK_MODE = 2
7166 22:55:37.271117 SELPH_MODE = 1
7167 22:55:37.274457 PICG_EARLY_EN = 1
7168 22:55:37.278312 VALID_LAT_VALUE = 1
7169 22:55:37.284292 ==============================================================
7170 22:55:37.287504 Enter into Gating configuration >>>>
7171 22:55:37.291002 Exit from Gating configuration <<<<
7172 22:55:37.294424 Enter into DVFS_PRE_config >>>>>
7173 22:55:37.304390 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7174 22:55:37.307198 Exit from DVFS_PRE_config <<<<<
7175 22:55:37.311153 Enter into PICG configuration >>>>
7176 22:55:37.314085 Exit from PICG configuration <<<<
7177 22:55:37.314620 [RX_INPUT] configuration >>>>>
7178 22:55:37.317807 [RX_INPUT] configuration <<<<<
7179 22:55:37.324285 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7180 22:55:37.331067 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7181 22:55:37.334482 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7182 22:55:37.340929 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7183 22:55:37.347404 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7184 22:55:37.353909 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7185 22:55:37.357350 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7186 22:55:37.360566 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7187 22:55:37.367377 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7188 22:55:37.370428 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7189 22:55:37.373637 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7190 22:55:37.380241 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7191 22:55:37.383480 ===================================
7192 22:55:37.383983 LPDDR4 DRAM CONFIGURATION
7193 22:55:37.387445 ===================================
7194 22:55:37.390723 EX_ROW_EN[0] = 0x0
7195 22:55:37.391260 EX_ROW_EN[1] = 0x0
7196 22:55:37.393482 LP4Y_EN = 0x0
7197 22:55:37.393911 WORK_FSP = 0x1
7198 22:55:37.397391 WL = 0x5
7199 22:55:37.397929 RL = 0x5
7200 22:55:37.400769 BL = 0x2
7201 22:55:37.403706 RPST = 0x0
7202 22:55:37.404247 RD_PRE = 0x0
7203 22:55:37.406836 WR_PRE = 0x1
7204 22:55:37.407269 WR_PST = 0x1
7205 22:55:37.410498 DBI_WR = 0x0
7206 22:55:37.411034 DBI_RD = 0x0
7207 22:55:37.413783 OTF = 0x1
7208 22:55:37.416831 ===================================
7209 22:55:37.420001 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7210 22:55:37.423974 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7211 22:55:37.427176 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7212 22:55:37.430620 ===================================
7213 22:55:37.434348 LPDDR4 DRAM CONFIGURATION
7214 22:55:37.436729 ===================================
7215 22:55:37.440113 EX_ROW_EN[0] = 0x10
7216 22:55:37.440647 EX_ROW_EN[1] = 0x0
7217 22:55:37.443830 LP4Y_EN = 0x0
7218 22:55:37.444371 WORK_FSP = 0x1
7219 22:55:37.447034 WL = 0x5
7220 22:55:37.447623 RL = 0x5
7221 22:55:37.450843 BL = 0x2
7222 22:55:37.451421 RPST = 0x0
7223 22:55:37.453297 RD_PRE = 0x0
7224 22:55:37.453728 WR_PRE = 0x1
7225 22:55:37.457420 WR_PST = 0x1
7226 22:55:37.458080 DBI_WR = 0x0
7227 22:55:37.460156 DBI_RD = 0x0
7228 22:55:37.464242 OTF = 0x1
7229 22:55:37.466616 ===================================
7230 22:55:37.469892 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7231 22:55:37.470327 ==
7232 22:55:37.473600 Dram Type= 6, Freq= 0, CH_0, rank 0
7233 22:55:37.479908 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7234 22:55:37.480345 ==
7235 22:55:37.480689 [Duty_Offset_Calibration]
7236 22:55:37.483651 B0:2 B1:-1 CA:1
7237 22:55:37.484126
7238 22:55:37.486937 [DutyScan_Calibration_Flow] k_type=0
7239 22:55:37.496034
7240 22:55:37.496566 ==CLK 0==
7241 22:55:37.498992 Final CLK duty delay cell = -4
7242 22:55:37.502465 [-4] MAX Duty = 5031%(X100), DQS PI = 22
7243 22:55:37.505509 [-4] MIN Duty = 4844%(X100), DQS PI = 32
7244 22:55:37.508736 [-4] AVG Duty = 4937%(X100)
7245 22:55:37.509166
7246 22:55:37.512492 CH0 CLK Duty spec in!! Max-Min= 187%
7247 22:55:37.515662 [DutyScan_Calibration_Flow] ====Done====
7248 22:55:37.516102
7249 22:55:37.519186 [DutyScan_Calibration_Flow] k_type=1
7250 22:55:37.535803
7251 22:55:37.536340 ==DQS 0 ==
7252 22:55:37.538595 Final DQS duty delay cell = 0
7253 22:55:37.542095 [0] MAX Duty = 5125%(X100), DQS PI = 20
7254 22:55:37.545082 [0] MIN Duty = 5000%(X100), DQS PI = 14
7255 22:55:37.548132 [0] AVG Duty = 5062%(X100)
7256 22:55:37.548563
7257 22:55:37.548904 ==DQS 1 ==
7258 22:55:37.551648 Final DQS duty delay cell = -4
7259 22:55:37.554876 [-4] MAX Duty = 5093%(X100), DQS PI = 0
7260 22:55:37.558350 [-4] MIN Duty = 5000%(X100), DQS PI = 40
7261 22:55:37.561885 [-4] AVG Duty = 5046%(X100)
7262 22:55:37.562442
7263 22:55:37.564745 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7264 22:55:37.565339
7265 22:55:37.568178 CH0 DQS 1 Duty spec in!! Max-Min= 93%
7266 22:55:37.571833 [DutyScan_Calibration_Flow] ====Done====
7267 22:55:37.572263
7268 22:55:37.574530 [DutyScan_Calibration_Flow] k_type=3
7269 22:55:37.592867
7270 22:55:37.593403 ==DQM 0 ==
7271 22:55:37.596120 Final DQM duty delay cell = 0
7272 22:55:37.599603 [0] MAX Duty = 5000%(X100), DQS PI = 20
7273 22:55:37.602558 [0] MIN Duty = 4875%(X100), DQS PI = 4
7274 22:55:37.605572 [0] AVG Duty = 4937%(X100)
7275 22:55:37.606005
7276 22:55:37.606345 ==DQM 1 ==
7277 22:55:37.609685 Final DQM duty delay cell = 0
7278 22:55:37.612178 [0] MAX Duty = 5218%(X100), DQS PI = 58
7279 22:55:37.615852 [0] MIN Duty = 4969%(X100), DQS PI = 20
7280 22:55:37.619013 [0] AVG Duty = 5093%(X100)
7281 22:55:37.619472
7282 22:55:37.622805 CH0 DQM 0 Duty spec in!! Max-Min= 125%
7283 22:55:37.623342
7284 22:55:37.626238 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7285 22:55:37.629359 [DutyScan_Calibration_Flow] ====Done====
7286 22:55:37.629895
7287 22:55:37.632290 [DutyScan_Calibration_Flow] k_type=2
7288 22:55:37.649640
7289 22:55:37.650173 ==DQ 0 ==
7290 22:55:37.652003 Final DQ duty delay cell = -4
7291 22:55:37.656017 [-4] MAX Duty = 5031%(X100), DQS PI = 56
7292 22:55:37.658682 [-4] MIN Duty = 4844%(X100), DQS PI = 12
7293 22:55:37.661933 [-4] AVG Duty = 4937%(X100)
7294 22:55:37.662354
7295 22:55:37.662684 ==DQ 1 ==
7296 22:55:37.665552 Final DQ duty delay cell = 0
7297 22:55:37.668937 [0] MAX Duty = 5031%(X100), DQS PI = 30
7298 22:55:37.671793 [0] MIN Duty = 4907%(X100), DQS PI = 42
7299 22:55:37.675236 [0] AVG Duty = 4969%(X100)
7300 22:55:37.675685
7301 22:55:37.678819 CH0 DQ 0 Duty spec in!! Max-Min= 187%
7302 22:55:37.679240
7303 22:55:37.682320 CH0 DQ 1 Duty spec in!! Max-Min= 124%
7304 22:55:37.685238 [DutyScan_Calibration_Flow] ====Done====
7305 22:55:37.685658 ==
7306 22:55:37.688582 Dram Type= 6, Freq= 0, CH_1, rank 0
7307 22:55:37.691881 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7308 22:55:37.692303 ==
7309 22:55:37.695604 [Duty_Offset_Calibration]
7310 22:55:37.696021 B0:1 B1:1 CA:2
7311 22:55:37.696346
7312 22:55:37.699139 [DutyScan_Calibration_Flow] k_type=0
7313 22:55:37.709951
7314 22:55:37.710479 ==CLK 0==
7315 22:55:37.712930 Final CLK duty delay cell = 0
7316 22:55:37.716198 [0] MAX Duty = 5187%(X100), DQS PI = 24
7317 22:55:37.719378 [0] MIN Duty = 4969%(X100), DQS PI = 48
7318 22:55:37.722642 [0] AVG Duty = 5078%(X100)
7319 22:55:37.723166
7320 22:55:37.726360 CH1 CLK Duty spec in!! Max-Min= 218%
7321 22:55:37.729898 [DutyScan_Calibration_Flow] ====Done====
7322 22:55:37.730421
7323 22:55:37.732821 [DutyScan_Calibration_Flow] k_type=1
7324 22:55:37.749233
7325 22:55:37.749758 ==DQS 0 ==
7326 22:55:37.752549 Final DQS duty delay cell = 0
7327 22:55:37.756259 [0] MAX Duty = 5062%(X100), DQS PI = 22
7328 22:55:37.759203 [0] MIN Duty = 4813%(X100), DQS PI = 52
7329 22:55:37.763598 [0] AVG Duty = 4937%(X100)
7330 22:55:37.764125
7331 22:55:37.764457 ==DQS 1 ==
7332 22:55:37.765242 Final DQS duty delay cell = 0
7333 22:55:37.769091 [0] MAX Duty = 5031%(X100), DQS PI = 36
7334 22:55:37.772053 [0] MIN Duty = 4938%(X100), DQS PI = 12
7335 22:55:37.775482 [0] AVG Duty = 4984%(X100)
7336 22:55:37.775902
7337 22:55:37.779476 CH1 DQS 0 Duty spec in!! Max-Min= 249%
7338 22:55:37.779985
7339 22:55:37.782839 CH1 DQS 1 Duty spec in!! Max-Min= 93%
7340 22:55:37.786227 [DutyScan_Calibration_Flow] ====Done====
7341 22:55:37.786638
7342 22:55:37.788810 [DutyScan_Calibration_Flow] k_type=3
7343 22:55:37.806153
7344 22:55:37.806662 ==DQM 0 ==
7345 22:55:37.809501 Final DQM duty delay cell = 0
7346 22:55:37.812925 [0] MAX Duty = 5187%(X100), DQS PI = 20
7347 22:55:37.816198 [0] MIN Duty = 4813%(X100), DQS PI = 50
7348 22:55:37.819552 [0] AVG Duty = 5000%(X100)
7349 22:55:37.820066
7350 22:55:37.820396 ==DQM 1 ==
7351 22:55:37.822622 Final DQM duty delay cell = 0
7352 22:55:37.826078 [0] MAX Duty = 5125%(X100), DQS PI = 8
7353 22:55:37.829636 [0] MIN Duty = 4875%(X100), DQS PI = 22
7354 22:55:37.832621 [0] AVG Duty = 5000%(X100)
7355 22:55:37.833047
7356 22:55:37.835674 CH1 DQM 0 Duty spec in!! Max-Min= 374%
7357 22:55:37.836106
7358 22:55:37.838985 CH1 DQM 1 Duty spec in!! Max-Min= 250%
7359 22:55:37.843136 [DutyScan_Calibration_Flow] ====Done====
7360 22:55:37.843710
7361 22:55:37.846148 [DutyScan_Calibration_Flow] k_type=2
7362 22:55:37.862840
7363 22:55:37.863403 ==DQ 0 ==
7364 22:55:37.866698 Final DQ duty delay cell = 0
7365 22:55:37.869854 [0] MAX Duty = 5156%(X100), DQS PI = 20
7366 22:55:37.872696 [0] MIN Duty = 4938%(X100), DQS PI = 52
7367 22:55:37.873127 [0] AVG Duty = 5047%(X100)
7368 22:55:37.876414
7369 22:55:37.876842 ==DQ 1 ==
7370 22:55:37.879512 Final DQ duty delay cell = 0
7371 22:55:37.882904 [0] MAX Duty = 5093%(X100), DQS PI = 8
7372 22:55:37.886085 [0] MIN Duty = 5031%(X100), DQS PI = 0
7373 22:55:37.886534 [0] AVG Duty = 5062%(X100)
7374 22:55:37.886877
7375 22:55:37.889710 CH1 DQ 0 Duty spec in!! Max-Min= 218%
7376 22:55:37.890140
7377 22:55:37.892671 CH1 DQ 1 Duty spec in!! Max-Min= 62%
7378 22:55:37.899691 [DutyScan_Calibration_Flow] ====Done====
7379 22:55:37.903450 nWR fixed to 30
7380 22:55:37.903971 [ModeRegInit_LP4] CH0 RK0
7381 22:55:37.905830 [ModeRegInit_LP4] CH0 RK1
7382 22:55:37.909703 [ModeRegInit_LP4] CH1 RK0
7383 22:55:37.910129 [ModeRegInit_LP4] CH1 RK1
7384 22:55:37.913243 match AC timing 5
7385 22:55:37.916331 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7386 22:55:37.919498 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7387 22:55:37.926464 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7388 22:55:37.929401 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7389 22:55:37.935839 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7390 22:55:37.936371 [MiockJmeterHQA]
7391 22:55:37.936714
7392 22:55:37.939271 [DramcMiockJmeter] u1RxGatingPI = 0
7393 22:55:37.942729 0 : 4363, 4138
7394 22:55:37.943274 4 : 4253, 4027
7395 22:55:37.943679 8 : 4252, 4027
7396 22:55:37.945650 12 : 4253, 4026
7397 22:55:37.946086 16 : 4252, 4027
7398 22:55:37.949416 20 : 4252, 4027
7399 22:55:37.949851 24 : 4253, 4026
7400 22:55:37.952752 28 : 4363, 4138
7401 22:55:37.953284 32 : 4252, 4027
7402 22:55:37.953634 36 : 4252, 4027
7403 22:55:37.955857 40 : 4253, 4027
7404 22:55:37.956296 44 : 4253, 4026
7405 22:55:37.959530 48 : 4252, 4027
7406 22:55:37.960054 52 : 4363, 4137
7407 22:55:37.962566 56 : 4363, 4137
7408 22:55:37.962999 60 : 4252, 4027
7409 22:55:37.965962 64 : 4250, 4027
7410 22:55:37.966410 68 : 4252, 4027
7411 22:55:37.966758 72 : 4250, 4026
7412 22:55:37.969278 76 : 4250, 4027
7413 22:55:37.969732 80 : 4360, 4137
7414 22:55:37.972502 84 : 4250, 4027
7415 22:55:37.972934 88 : 4250, 4027
7416 22:55:37.976044 92 : 4250, 4026
7417 22:55:37.976474 96 : 4250, 3228
7418 22:55:37.979512 100 : 4250, 0
7419 22:55:37.979941 104 : 4250, 0
7420 22:55:37.980288 108 : 4366, 0
7421 22:55:37.982164 112 : 4360, 0
7422 22:55:37.982596 116 : 4361, 0
7423 22:55:37.982936 120 : 4250, 0
7424 22:55:37.986086 124 : 4250, 0
7425 22:55:37.986539 128 : 4363, 0
7426 22:55:37.989231 132 : 4250, 0
7427 22:55:37.989661 136 : 4250, 0
7428 22:55:37.989999 140 : 4250, 0
7429 22:55:37.992209 144 : 4250, 0
7430 22:55:37.992653 148 : 4253, 0
7431 22:55:37.996238 152 : 4250, 0
7432 22:55:37.996670 156 : 4250, 0
7433 22:55:37.997013 160 : 4361, 0
7434 22:55:37.998932 164 : 4360, 0
7435 22:55:37.999398 168 : 4361, 0
7436 22:55:38.002917 172 : 4250, 0
7437 22:55:38.003500 176 : 4250, 0
7438 22:55:38.003855 180 : 4250, 0
7439 22:55:38.005789 184 : 4250, 0
7440 22:55:38.006244 188 : 4250, 0
7441 22:55:38.006589 192 : 4250, 0
7442 22:55:38.008974 196 : 4250, 0
7443 22:55:38.009407 200 : 4253, 0
7444 22:55:38.012197 204 : 4250, 0
7445 22:55:38.012635 208 : 4250, 0
7446 22:55:38.012983 212 : 4361, 147
7447 22:55:38.015402 216 : 4361, 4028
7448 22:55:38.015834 220 : 4250, 4027
7449 22:55:38.019644 224 : 4250, 4026
7450 22:55:38.020175 228 : 4250, 4027
7451 22:55:38.022055 232 : 4250, 4026
7452 22:55:38.022487 236 : 4250, 4027
7453 22:55:38.025670 240 : 4253, 4026
7454 22:55:38.026224 244 : 4361, 4137
7455 22:55:38.029156 248 : 4250, 4026
7456 22:55:38.029686 252 : 4250, 4027
7457 22:55:38.032172 256 : 4360, 4138
7458 22:55:38.032702 260 : 4250, 4026
7459 22:55:38.035500 264 : 4250, 4027
7460 22:55:38.036029 268 : 4361, 4137
7461 22:55:38.036377 272 : 4250, 4027
7462 22:55:38.039544 276 : 4250, 4026
7463 22:55:38.040074 280 : 4250, 4027
7464 22:55:38.042637 284 : 4250, 4026
7465 22:55:38.043164 288 : 4250, 4027
7466 22:55:38.045463 292 : 4250, 4026
7467 22:55:38.046043 296 : 4361, 4137
7468 22:55:38.049376 300 : 4250, 4026
7469 22:55:38.049910 304 : 4250, 4027
7470 22:55:38.052553 308 : 4360, 4138
7471 22:55:38.053083 312 : 4250, 4027
7472 22:55:38.055516 316 : 4250, 4027
7473 22:55:38.056046 320 : 4361, 4137
7474 22:55:38.059323 324 : 4250, 4027
7475 22:55:38.059908 328 : 4250, 4026
7476 22:55:38.062149 332 : 4250, 2882
7477 22:55:38.062579 336 : 4250, 20
7478 22:55:38.062921
7479 22:55:38.065032 MIOCK jitter meter ch=0
7480 22:55:38.065457
7481 22:55:38.068264 1T = (336-100) = 236 dly cells
7482 22:55:38.071784 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7483 22:55:38.072213 ==
7484 22:55:38.075140 Dram Type= 6, Freq= 0, CH_0, rank 0
7485 22:55:38.082043 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7486 22:55:38.082474 ==
7487 22:55:38.085115 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7488 22:55:38.088259 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7489 22:55:38.095229 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7490 22:55:38.101989 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7491 22:55:38.109168 [CA 0] Center 44 (14~75) winsize 62
7492 22:55:38.113254 [CA 1] Center 44 (14~74) winsize 61
7493 22:55:38.115818 [CA 2] Center 39 (10~68) winsize 59
7494 22:55:38.120314 [CA 3] Center 38 (9~68) winsize 60
7495 22:55:38.123222 [CA 4] Center 37 (7~67) winsize 61
7496 22:55:38.125834 [CA 5] Center 37 (7~67) winsize 61
7497 22:55:38.126261
7498 22:55:38.129479 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7499 22:55:38.130006
7500 22:55:38.132549 [CATrainingPosCal] consider 1 rank data
7501 22:55:38.136034 u2DelayCellTimex100 = 275/100 ps
7502 22:55:38.142824 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7503 22:55:38.146145 CA1 delay=44 (14~74),Diff = 7 PI (24 cell)
7504 22:55:38.149512 CA2 delay=39 (10~68),Diff = 2 PI (7 cell)
7505 22:55:38.152641 CA3 delay=38 (9~68),Diff = 1 PI (3 cell)
7506 22:55:38.156230 CA4 delay=37 (7~67),Diff = 0 PI (0 cell)
7507 22:55:38.159516 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7508 22:55:38.160043
7509 22:55:38.162791 CA PerBit enable=1, Macro0, CA PI delay=37
7510 22:55:38.163314
7511 22:55:38.166247 [CBTSetCACLKResult] CA Dly = 37
7512 22:55:38.169635 CS Dly: 10 (0~41)
7513 22:55:38.172752 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7514 22:55:38.175415 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7515 22:55:38.175840 ==
7516 22:55:38.179033 Dram Type= 6, Freq= 0, CH_0, rank 1
7517 22:55:38.182419 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7518 22:55:38.185539 ==
7519 22:55:38.188734 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7520 22:55:38.192567 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7521 22:55:38.198720 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7522 22:55:38.205472 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7523 22:55:38.213265 [CA 0] Center 44 (14~75) winsize 62
7524 22:55:38.216288 [CA 1] Center 44 (14~75) winsize 62
7525 22:55:38.219560 [CA 2] Center 39 (10~69) winsize 60
7526 22:55:38.222578 [CA 3] Center 39 (10~69) winsize 60
7527 22:55:38.226155 [CA 4] Center 37 (8~67) winsize 60
7528 22:55:38.229743 [CA 5] Center 37 (7~67) winsize 61
7529 22:55:38.230274
7530 22:55:38.233304 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7531 22:55:38.233834
7532 22:55:38.239547 [CATrainingPosCal] consider 2 rank data
7533 22:55:38.240075 u2DelayCellTimex100 = 275/100 ps
7534 22:55:38.246342 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7535 22:55:38.250091 CA1 delay=44 (14~74),Diff = 7 PI (24 cell)
7536 22:55:38.252513 CA2 delay=39 (10~68),Diff = 2 PI (7 cell)
7537 22:55:38.256546 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7538 22:55:38.259475 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7539 22:55:38.262733 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7540 22:55:38.263270
7541 22:55:38.265935 CA PerBit enable=1, Macro0, CA PI delay=37
7542 22:55:38.266365
7543 22:55:38.269882 [CBTSetCACLKResult] CA Dly = 37
7544 22:55:38.273004 CS Dly: 11 (0~44)
7545 22:55:38.275665 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7546 22:55:38.279269 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7547 22:55:38.279840
7548 22:55:38.282645 ----->DramcWriteLeveling(PI) begin...
7549 22:55:38.283202 ==
7550 22:55:38.285787 Dram Type= 6, Freq= 0, CH_0, rank 0
7551 22:55:38.292121 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7552 22:55:38.292557 ==
7553 22:55:38.295513 Write leveling (Byte 0): 33 => 33
7554 22:55:38.299044 Write leveling (Byte 1): 29 => 29
7555 22:55:38.299621 DramcWriteLeveling(PI) end<-----
7556 22:55:38.302333
7557 22:55:38.302858 ==
7558 22:55:38.306158 Dram Type= 6, Freq= 0, CH_0, rank 0
7559 22:55:38.309297 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7560 22:55:38.309736 ==
7561 22:55:38.312420 [Gating] SW mode calibration
7562 22:55:38.319237 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7563 22:55:38.322120 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7564 22:55:38.328997 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7565 22:55:38.331927 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7566 22:55:38.335414 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7567 22:55:38.342594 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7568 22:55:38.346209 1 4 16 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
7569 22:55:38.349176 1 4 20 | B1->B0 | 2322 3434 | 1 0 | (0 0) (0 0)
7570 22:55:38.355758 1 4 24 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
7571 22:55:38.359113 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7572 22:55:38.362157 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7573 22:55:38.368389 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7574 22:55:38.371959 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7575 22:55:38.375255 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7576 22:55:38.381825 1 5 16 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 0)
7577 22:55:38.385311 1 5 20 | B1->B0 | 3434 2727 | 1 0 | (1 0) (0 0)
7578 22:55:38.388678 1 5 24 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
7579 22:55:38.395201 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7580 22:55:38.399065 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7581 22:55:38.401764 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7582 22:55:38.408773 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7583 22:55:38.412020 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7584 22:55:38.415084 1 6 16 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
7585 22:55:38.421695 1 6 20 | B1->B0 | 2a2a 4646 | 0 0 | (1 1) (0 0)
7586 22:55:38.425229 1 6 24 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
7587 22:55:38.428420 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7588 22:55:38.435018 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7589 22:55:38.438253 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7590 22:55:38.442047 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7591 22:55:38.445970 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7592 22:55:38.451909 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7593 22:55:38.455221 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7594 22:55:38.458261 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7595 22:55:38.465259 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7596 22:55:38.468505 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7597 22:55:38.471434 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7598 22:55:38.478524 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7599 22:55:38.481953 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7600 22:55:38.484947 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7601 22:55:38.491832 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7602 22:55:38.495077 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7603 22:55:38.498094 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7604 22:55:38.505100 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7605 22:55:38.507712 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7606 22:55:38.511306 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7607 22:55:38.518022 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7608 22:55:38.521325 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7609 22:55:38.524841 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7610 22:55:38.531053 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7611 22:55:38.534552 Total UI for P1: 0, mck2ui 16
7612 22:55:38.537821 best dqsien dly found for B0: ( 1, 9, 18)
7613 22:55:38.538246 Total UI for P1: 0, mck2ui 16
7614 22:55:38.544199 best dqsien dly found for B1: ( 1, 9, 22)
7615 22:55:38.547585 best DQS0 dly(MCK, UI, PI) = (1, 9, 18)
7616 22:55:38.551072 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7617 22:55:38.551558
7618 22:55:38.554686 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 18)
7619 22:55:38.558062 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7620 22:55:38.561266 [Gating] SW calibration Done
7621 22:55:38.561801 ==
7622 22:55:38.564704 Dram Type= 6, Freq= 0, CH_0, rank 0
7623 22:55:38.568300 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7624 22:55:38.568733 ==
7625 22:55:38.571177 RX Vref Scan: 0
7626 22:55:38.571794
7627 22:55:38.572145 RX Vref 0 -> 0, step: 1
7628 22:55:38.572470
7629 22:55:38.574363 RX Delay 0 -> 252, step: 8
7630 22:55:38.578263 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
7631 22:55:38.584052 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7632 22:55:38.587407 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7633 22:55:38.590662 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
7634 22:55:38.594481 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7635 22:55:38.597943 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7636 22:55:38.604243 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7637 22:55:38.607855 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
7638 22:55:38.610689 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7639 22:55:38.614303 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7640 22:55:38.617622 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7641 22:55:38.623870 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7642 22:55:38.627845 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7643 22:55:38.630477 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7644 22:55:38.633721 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7645 22:55:38.640779 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7646 22:55:38.641310 ==
7647 22:55:38.644213 Dram Type= 6, Freq= 0, CH_0, rank 0
7648 22:55:38.647435 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7649 22:55:38.648001 ==
7650 22:55:38.648382 DQS Delay:
7651 22:55:38.650896 DQS0 = 0, DQS1 = 0
7652 22:55:38.651465 DQM Delay:
7653 22:55:38.654126 DQM0 = 132, DQM1 = 124
7654 22:55:38.654807 DQ Delay:
7655 22:55:38.657839 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =131
7656 22:55:38.660900 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
7657 22:55:38.663649 DQ8 =111, DQ9 =111, DQ10 =123, DQ11 =119
7658 22:55:38.667626 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7659 22:55:38.668168
7660 22:55:38.668512
7661 22:55:38.670420 ==
7662 22:55:38.673648 Dram Type= 6, Freq= 0, CH_0, rank 0
7663 22:55:38.676967 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7664 22:55:38.677402 ==
7665 22:55:38.677743
7666 22:55:38.678060
7667 22:55:38.680194 TX Vref Scan disable
7668 22:55:38.680625 == TX Byte 0 ==
7669 22:55:38.683984 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7670 22:55:38.690133 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7671 22:55:38.690565 == TX Byte 1 ==
7672 22:55:38.694021 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7673 22:55:38.700805 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7674 22:55:38.701359 ==
7675 22:55:38.703629 Dram Type= 6, Freq= 0, CH_0, rank 0
7676 22:55:38.707402 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7677 22:55:38.708071 ==
7678 22:55:38.721536
7679 22:55:38.725060 TX Vref early break, caculate TX vref
7680 22:55:38.728294 TX Vref=16, minBit 4, minWin=21, winSum=365
7681 22:55:38.731677 TX Vref=18, minBit 0, minWin=22, winSum=374
7682 22:55:38.734876 TX Vref=20, minBit 4, minWin=22, winSum=384
7683 22:55:38.738207 TX Vref=22, minBit 4, minWin=22, winSum=397
7684 22:55:38.741287 TX Vref=24, minBit 2, minWin=24, winSum=407
7685 22:55:38.747708 TX Vref=26, minBit 4, minWin=24, winSum=415
7686 22:55:38.751078 TX Vref=28, minBit 0, minWin=25, winSum=419
7687 22:55:38.754420 TX Vref=30, minBit 4, minWin=25, winSum=419
7688 22:55:38.758184 TX Vref=32, minBit 0, minWin=24, winSum=410
7689 22:55:38.761518 TX Vref=34, minBit 4, minWin=23, winSum=405
7690 22:55:38.764770 TX Vref=36, minBit 0, minWin=23, winSum=392
7691 22:55:38.771261 [TxChooseVref] Worse bit 0, Min win 25, Win sum 419, Final Vref 28
7692 22:55:38.771860
7693 22:55:38.774308 Final TX Range 0 Vref 28
7694 22:55:38.774739
7695 22:55:38.775093 ==
7696 22:55:38.778470 Dram Type= 6, Freq= 0, CH_0, rank 0
7697 22:55:38.781350 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7698 22:55:38.781876 ==
7699 22:55:38.782267
7700 22:55:38.782587
7701 22:55:38.784485 TX Vref Scan disable
7702 22:55:38.791094 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7703 22:55:38.791565 == TX Byte 0 ==
7704 22:55:38.794989 u2DelayCellOfst[0]=14 cells (4 PI)
7705 22:55:38.798284 u2DelayCellOfst[1]=17 cells (5 PI)
7706 22:55:38.801373 u2DelayCellOfst[2]=7 cells (2 PI)
7707 22:55:38.804853 u2DelayCellOfst[3]=14 cells (4 PI)
7708 22:55:38.808249 u2DelayCellOfst[4]=7 cells (2 PI)
7709 22:55:38.810950 u2DelayCellOfst[5]=0 cells (0 PI)
7710 22:55:38.815317 u2DelayCellOfst[6]=17 cells (5 PI)
7711 22:55:38.817749 u2DelayCellOfst[7]=17 cells (5 PI)
7712 22:55:38.821590 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7713 22:55:38.824748 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7714 22:55:38.827867 == TX Byte 1 ==
7715 22:55:38.831562 u2DelayCellOfst[8]=0 cells (0 PI)
7716 22:55:38.832089 u2DelayCellOfst[9]=0 cells (0 PI)
7717 22:55:38.834762 u2DelayCellOfst[10]=7 cells (2 PI)
7718 22:55:38.838014 u2DelayCellOfst[11]=0 cells (0 PI)
7719 22:55:38.841503 u2DelayCellOfst[12]=10 cells (3 PI)
7720 22:55:38.844711 u2DelayCellOfst[13]=10 cells (3 PI)
7721 22:55:38.848021 u2DelayCellOfst[14]=10 cells (3 PI)
7722 22:55:38.851939 u2DelayCellOfst[15]=10 cells (3 PI)
7723 22:55:38.854329 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7724 22:55:38.861095 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7725 22:55:38.861629 DramC Write-DBI on
7726 22:55:38.861974 ==
7727 22:55:38.864171 Dram Type= 6, Freq= 0, CH_0, rank 0
7728 22:55:38.871226 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7729 22:55:38.871817 ==
7730 22:55:38.872169
7731 22:55:38.872486
7732 22:55:38.872789 TX Vref Scan disable
7733 22:55:38.874615 == TX Byte 0 ==
7734 22:55:38.878184 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7735 22:55:38.881968 == TX Byte 1 ==
7736 22:55:38.885069 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
7737 22:55:38.887777 DramC Write-DBI off
7738 22:55:38.888224
7739 22:55:38.888563 [DATLAT]
7740 22:55:38.888882 Freq=1600, CH0 RK0
7741 22:55:38.889203
7742 22:55:38.891130 DATLAT Default: 0xf
7743 22:55:38.891602 0, 0xFFFF, sum = 0
7744 22:55:38.894341 1, 0xFFFF, sum = 0
7745 22:55:38.898224 2, 0xFFFF, sum = 0
7746 22:55:38.898754 3, 0xFFFF, sum = 0
7747 22:55:38.901396 4, 0xFFFF, sum = 0
7748 22:55:38.901925 5, 0xFFFF, sum = 0
7749 22:55:38.904833 6, 0xFFFF, sum = 0
7750 22:55:38.905373 7, 0xFFFF, sum = 0
7751 22:55:38.908200 8, 0xFFFF, sum = 0
7752 22:55:38.908743 9, 0xFFFF, sum = 0
7753 22:55:38.910994 10, 0xFFFF, sum = 0
7754 22:55:38.911471 11, 0xFFFF, sum = 0
7755 22:55:38.914321 12, 0xFFFF, sum = 0
7756 22:55:38.914756 13, 0xFFFF, sum = 0
7757 22:55:38.917433 14, 0x0, sum = 1
7758 22:55:38.917868 15, 0x0, sum = 2
7759 22:55:38.921141 16, 0x0, sum = 3
7760 22:55:38.921668 17, 0x0, sum = 4
7761 22:55:38.924160 best_step = 15
7762 22:55:38.924587
7763 22:55:38.924927 ==
7764 22:55:38.927891 Dram Type= 6, Freq= 0, CH_0, rank 0
7765 22:55:38.931439 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7766 22:55:38.931965 ==
7767 22:55:38.934590 RX Vref Scan: 1
7768 22:55:38.935112
7769 22:55:38.935487 Set Vref Range= 24 -> 127
7770 22:55:38.935809
7771 22:55:38.937929 RX Vref 24 -> 127, step: 1
7772 22:55:38.938454
7773 22:55:38.941326 RX Delay 11 -> 252, step: 4
7774 22:55:38.941854
7775 22:55:38.944117 Set Vref, RX VrefLevel [Byte0]: 24
7776 22:55:38.947586 [Byte1]: 24
7777 22:55:38.948116
7778 22:55:38.951119 Set Vref, RX VrefLevel [Byte0]: 25
7779 22:55:38.954094 [Byte1]: 25
7780 22:55:38.957537
7781 22:55:38.958063 Set Vref, RX VrefLevel [Byte0]: 26
7782 22:55:38.960778 [Byte1]: 26
7783 22:55:38.965164
7784 22:55:38.965687 Set Vref, RX VrefLevel [Byte0]: 27
7785 22:55:38.968251 [Byte1]: 27
7786 22:55:38.972531
7787 22:55:38.973062 Set Vref, RX VrefLevel [Byte0]: 28
7788 22:55:38.976161 [Byte1]: 28
7789 22:55:38.980140
7790 22:55:38.980567 Set Vref, RX VrefLevel [Byte0]: 29
7791 22:55:38.983228 [Byte1]: 29
7792 22:55:38.987960
7793 22:55:38.988390 Set Vref, RX VrefLevel [Byte0]: 30
7794 22:55:38.990872 [Byte1]: 30
7795 22:55:38.995947
7796 22:55:38.996511 Set Vref, RX VrefLevel [Byte0]: 31
7797 22:55:38.998867 [Byte1]: 31
7798 22:55:39.003229
7799 22:55:39.003792 Set Vref, RX VrefLevel [Byte0]: 32
7800 22:55:39.006554 [Byte1]: 32
7801 22:55:39.011180
7802 22:55:39.011666 Set Vref, RX VrefLevel [Byte0]: 33
7803 22:55:39.014514 [Byte1]: 33
7804 22:55:39.018620
7805 22:55:39.019143 Set Vref, RX VrefLevel [Byte0]: 34
7806 22:55:39.022169 [Byte1]: 34
7807 22:55:39.026047
7808 22:55:39.026562 Set Vref, RX VrefLevel [Byte0]: 35
7809 22:55:39.029752 [Byte1]: 35
7810 22:55:39.033661
7811 22:55:39.034241 Set Vref, RX VrefLevel [Byte0]: 36
7812 22:55:39.036739 [Byte1]: 36
7813 22:55:39.041590
7814 22:55:39.042114 Set Vref, RX VrefLevel [Byte0]: 37
7815 22:55:39.044515 [Byte1]: 37
7816 22:55:39.048719
7817 22:55:39.049286 Set Vref, RX VrefLevel [Byte0]: 38
7818 22:55:39.052536 [Byte1]: 38
7819 22:55:39.056747
7820 22:55:39.057264 Set Vref, RX VrefLevel [Byte0]: 39
7821 22:55:39.059637 [Byte1]: 39
7822 22:55:39.064289
7823 22:55:39.064810 Set Vref, RX VrefLevel [Byte0]: 40
7824 22:55:39.067404 [Byte1]: 40
7825 22:55:39.072182
7826 22:55:39.072714 Set Vref, RX VrefLevel [Byte0]: 41
7827 22:55:39.074627 [Byte1]: 41
7828 22:55:39.079275
7829 22:55:39.079746 Set Vref, RX VrefLevel [Byte0]: 42
7830 22:55:39.082757 [Byte1]: 42
7831 22:55:39.087029
7832 22:55:39.087570 Set Vref, RX VrefLevel [Byte0]: 43
7833 22:55:39.090184 [Byte1]: 43
7834 22:55:39.095002
7835 22:55:39.095567 Set Vref, RX VrefLevel [Byte0]: 44
7836 22:55:39.097690 [Byte1]: 44
7837 22:55:39.102380
7838 22:55:39.102892 Set Vref, RX VrefLevel [Byte0]: 45
7839 22:55:39.105876 [Byte1]: 45
7840 22:55:39.109380
7841 22:55:39.109806 Set Vref, RX VrefLevel [Byte0]: 46
7842 22:55:39.113073 [Byte1]: 46
7843 22:55:39.117661
7844 22:55:39.118183 Set Vref, RX VrefLevel [Byte0]: 47
7845 22:55:39.120931 [Byte1]: 47
7846 22:55:39.124814
7847 22:55:39.125236 Set Vref, RX VrefLevel [Byte0]: 48
7848 22:55:39.127957 [Byte1]: 48
7849 22:55:39.132790
7850 22:55:39.133310 Set Vref, RX VrefLevel [Byte0]: 49
7851 22:55:39.136022 [Byte1]: 49
7852 22:55:39.140221
7853 22:55:39.140740 Set Vref, RX VrefLevel [Byte0]: 50
7854 22:55:39.143637 [Byte1]: 50
7855 22:55:39.147827
7856 22:55:39.148338 Set Vref, RX VrefLevel [Byte0]: 51
7857 22:55:39.151174 [Byte1]: 51
7858 22:55:39.155692
7859 22:55:39.156202 Set Vref, RX VrefLevel [Byte0]: 52
7860 22:55:39.158647 [Byte1]: 52
7861 22:55:39.163495
7862 22:55:39.164010 Set Vref, RX VrefLevel [Byte0]: 53
7863 22:55:39.166618 [Byte1]: 53
7864 22:55:39.171077
7865 22:55:39.171650 Set Vref, RX VrefLevel [Byte0]: 54
7866 22:55:39.173660 [Byte1]: 54
7867 22:55:39.178018
7868 22:55:39.181880 Set Vref, RX VrefLevel [Byte0]: 55
7869 22:55:39.184993 [Byte1]: 55
7870 22:55:39.185531
7871 22:55:39.188160 Set Vref, RX VrefLevel [Byte0]: 56
7872 22:55:39.191553 [Byte1]: 56
7873 22:55:39.191977
7874 22:55:39.194556 Set Vref, RX VrefLevel [Byte0]: 57
7875 22:55:39.197559 [Byte1]: 57
7876 22:55:39.201297
7877 22:55:39.201820 Set Vref, RX VrefLevel [Byte0]: 58
7878 22:55:39.204213 [Byte1]: 58
7879 22:55:39.208857
7880 22:55:39.209413 Set Vref, RX VrefLevel [Byte0]: 59
7881 22:55:39.211852 [Byte1]: 59
7882 22:55:39.216559
7883 22:55:39.217077 Set Vref, RX VrefLevel [Byte0]: 60
7884 22:55:39.220083 [Byte1]: 60
7885 22:55:39.224207
7886 22:55:39.224730 Set Vref, RX VrefLevel [Byte0]: 61
7887 22:55:39.227571 [Byte1]: 61
7888 22:55:39.231720
7889 22:55:39.232240 Set Vref, RX VrefLevel [Byte0]: 62
7890 22:55:39.235713 [Byte1]: 62
7891 22:55:39.239481
7892 22:55:39.239994 Set Vref, RX VrefLevel [Byte0]: 63
7893 22:55:39.242710 [Byte1]: 63
7894 22:55:39.247111
7895 22:55:39.247706 Set Vref, RX VrefLevel [Byte0]: 64
7896 22:55:39.250285 [Byte1]: 64
7897 22:55:39.254357
7898 22:55:39.254881 Set Vref, RX VrefLevel [Byte0]: 65
7899 22:55:39.258361 [Byte1]: 65
7900 22:55:39.262059
7901 22:55:39.262581 Set Vref, RX VrefLevel [Byte0]: 66
7902 22:55:39.265181 [Byte1]: 66
7903 22:55:39.269532
7904 22:55:39.270056 Set Vref, RX VrefLevel [Byte0]: 67
7905 22:55:39.273128 [Byte1]: 67
7906 22:55:39.277269
7907 22:55:39.277715 Set Vref, RX VrefLevel [Byte0]: 68
7908 22:55:39.280770 [Byte1]: 68
7909 22:55:39.285023
7910 22:55:39.285546 Set Vref, RX VrefLevel [Byte0]: 69
7911 22:55:39.287953 [Byte1]: 69
7912 22:55:39.292417
7913 22:55:39.292840 Set Vref, RX VrefLevel [Byte0]: 70
7914 22:55:39.295667 [Byte1]: 70
7915 22:55:39.300144
7916 22:55:39.300670 Set Vref, RX VrefLevel [Byte0]: 71
7917 22:55:39.303312 [Byte1]: 71
7918 22:55:39.308139
7919 22:55:39.308655 Set Vref, RX VrefLevel [Byte0]: 72
7920 22:55:39.314561 [Byte1]: 72
7921 22:55:39.315081
7922 22:55:39.318309 Set Vref, RX VrefLevel [Byte0]: 73
7923 22:55:39.321220 [Byte1]: 73
7924 22:55:39.321746
7925 22:55:39.324079 Set Vref, RX VrefLevel [Byte0]: 74
7926 22:55:39.327274 [Byte1]: 74
7927 22:55:39.327728
7928 22:55:39.330903 Set Vref, RX VrefLevel [Byte0]: 75
7929 22:55:39.334277 [Byte1]: 75
7930 22:55:39.338204
7931 22:55:39.338725 Set Vref, RX VrefLevel [Byte0]: 76
7932 22:55:39.341950 [Byte1]: 76
7933 22:55:39.345853
7934 22:55:39.346387 Set Vref, RX VrefLevel [Byte0]: 77
7935 22:55:39.348852 [Byte1]: 77
7936 22:55:39.353190
7937 22:55:39.353712 Final RX Vref Byte 0 = 62 to rank0
7938 22:55:39.356700 Final RX Vref Byte 1 = 61 to rank0
7939 22:55:39.360267 Final RX Vref Byte 0 = 62 to rank1
7940 22:55:39.363229 Final RX Vref Byte 1 = 61 to rank1==
7941 22:55:39.366402 Dram Type= 6, Freq= 0, CH_0, rank 0
7942 22:55:39.373418 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7943 22:55:39.373847 ==
7944 22:55:39.374185 DQS Delay:
7945 22:55:39.374496 DQS0 = 0, DQS1 = 0
7946 22:55:39.376669 DQM Delay:
7947 22:55:39.377092 DQM0 = 129, DQM1 = 121
7948 22:55:39.379952 DQ Delay:
7949 22:55:39.383396 DQ0 =130, DQ1 =132, DQ2 =126, DQ3 =126
7950 22:55:39.386313 DQ4 =132, DQ5 =118, DQ6 =136, DQ7 =138
7951 22:55:39.390044 DQ8 =110, DQ9 =110, DQ10 =122, DQ11 =116
7952 22:55:39.393133 DQ12 =126, DQ13 =126, DQ14 =132, DQ15 =132
7953 22:55:39.393803
7954 22:55:39.394421
7955 22:55:39.394971
7956 22:55:39.396244 [DramC_TX_OE_Calibration] TA2
7957 22:55:39.399646 Original DQ_B0 (3 6) =30, OEN = 27
7958 22:55:39.402866 Original DQ_B1 (3 6) =30, OEN = 27
7959 22:55:39.405978 24, 0x0, End_B0=24 End_B1=24
7960 22:55:39.406608 25, 0x0, End_B0=25 End_B1=25
7961 22:55:39.409442 26, 0x0, End_B0=26 End_B1=26
7962 22:55:39.412827 27, 0x0, End_B0=27 End_B1=27
7963 22:55:39.416107 28, 0x0, End_B0=28 End_B1=28
7964 22:55:39.416782 29, 0x0, End_B0=29 End_B1=29
7965 22:55:39.419391 30, 0x0, End_B0=30 End_B1=30
7966 22:55:39.422947 31, 0x4141, End_B0=30 End_B1=30
7967 22:55:39.426209 Byte0 end_step=30 best_step=27
7968 22:55:39.429722 Byte1 end_step=30 best_step=27
7969 22:55:39.433151 Byte0 TX OE(2T, 0.5T) = (3, 3)
7970 22:55:39.436038 Byte1 TX OE(2T, 0.5T) = (3, 3)
7971 22:55:39.436531
7972 22:55:39.436931
7973 22:55:39.443109 [DQSOSCAuto] RK0, (LSB)MR18= 0x1307, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 400 ps
7974 22:55:39.445905 CH0 RK0: MR19=303, MR18=1307
7975 22:55:39.452841 CH0_RK0: MR19=0x303, MR18=0x1307, DQSOSC=400, MR23=63, INC=23, DEC=15
7976 22:55:39.453344
7977 22:55:39.455902 ----->DramcWriteLeveling(PI) begin...
7978 22:55:39.456426 ==
7979 22:55:39.459650 Dram Type= 6, Freq= 0, CH_0, rank 1
7980 22:55:39.462895 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7981 22:55:39.463411 ==
7982 22:55:39.466254 Write leveling (Byte 0): 35 => 35
7983 22:55:39.469187 Write leveling (Byte 1): 27 => 27
7984 22:55:39.472425 DramcWriteLeveling(PI) end<-----
7985 22:55:39.472821
7986 22:55:39.473282 ==
7987 22:55:39.476246 Dram Type= 6, Freq= 0, CH_0, rank 1
7988 22:55:39.479085 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7989 22:55:39.479698 ==
7990 22:55:39.482709 [Gating] SW mode calibration
7991 22:55:39.488955 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7992 22:55:39.495993 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7993 22:55:39.499123 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7994 22:55:39.502864 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7995 22:55:39.508953 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7996 22:55:39.512845 1 4 12 | B1->B0 | 2323 3131 | 0 1 | (0 0) (1 1)
7997 22:55:39.516024 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7998 22:55:39.522556 1 4 20 | B1->B0 | 2c2c 3434 | 0 1 | (0 0) (1 1)
7999 22:55:39.525805 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8000 22:55:39.529295 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8001 22:55:39.535500 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8002 22:55:39.539017 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8003 22:55:39.542561 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8004 22:55:39.548864 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
8005 22:55:39.552186 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8006 22:55:39.555007 1 5 20 | B1->B0 | 3232 2323 | 0 0 | (1 0) (0 0)
8007 22:55:39.562115 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8008 22:55:39.564871 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8009 22:55:39.568611 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8010 22:55:39.575127 1 6 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
8011 22:55:39.578396 1 6 8 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
8012 22:55:39.581686 1 6 12 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
8013 22:55:39.588577 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8014 22:55:39.591756 1 6 20 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
8015 22:55:39.595191 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8016 22:55:39.601405 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8017 22:55:39.605012 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8018 22:55:39.608146 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8019 22:55:39.614539 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8020 22:55:39.618216 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8021 22:55:39.621291 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8022 22:55:39.628149 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8023 22:55:39.631584 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8024 22:55:39.634542 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8025 22:55:39.641806 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8026 22:55:39.644936 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8027 22:55:39.648294 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8028 22:55:39.654958 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8029 22:55:39.657917 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8030 22:55:39.661395 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8031 22:55:39.667876 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8032 22:55:39.671261 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8033 22:55:39.674405 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8034 22:55:39.677799 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8035 22:55:39.684832 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8036 22:55:39.688070 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8037 22:55:39.691023 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8038 22:55:39.694745 Total UI for P1: 0, mck2ui 16
8039 22:55:39.698180 best dqsien dly found for B0: ( 1, 9, 10)
8040 22:55:39.704528 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8041 22:55:39.707709 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8042 22:55:39.711259 Total UI for P1: 0, mck2ui 16
8043 22:55:39.714375 best dqsien dly found for B1: ( 1, 9, 18)
8044 22:55:39.717645 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8045 22:55:39.720996 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8046 22:55:39.721078
8047 22:55:39.724206 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8048 22:55:39.727546 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8049 22:55:39.731031 [Gating] SW calibration Done
8050 22:55:39.731112 ==
8051 22:55:39.734450 Dram Type= 6, Freq= 0, CH_0, rank 1
8052 22:55:39.741429 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8053 22:55:39.741511 ==
8054 22:55:39.741575 RX Vref Scan: 0
8055 22:55:39.741634
8056 22:55:39.744376 RX Vref 0 -> 0, step: 1
8057 22:55:39.744457
8058 22:55:39.747560 RX Delay 0 -> 252, step: 8
8059 22:55:39.750888 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8060 22:55:39.754240 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8061 22:55:39.757711 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
8062 22:55:39.761146 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8063 22:55:39.767890 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8064 22:55:39.771247 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8065 22:55:39.774041 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8066 22:55:39.777694 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8067 22:55:39.781034 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8068 22:55:39.787448 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8069 22:55:39.791130 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8070 22:55:39.794074 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8071 22:55:39.797331 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8072 22:55:39.800626 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8073 22:55:39.807538 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8074 22:55:39.810847 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8075 22:55:39.810929 ==
8076 22:55:39.814302 Dram Type= 6, Freq= 0, CH_0, rank 1
8077 22:55:39.817722 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8078 22:55:39.817805 ==
8079 22:55:39.820733 DQS Delay:
8080 22:55:39.820814 DQS0 = 0, DQS1 = 0
8081 22:55:39.820878 DQM Delay:
8082 22:55:39.824271 DQM0 = 131, DQM1 = 123
8083 22:55:39.824352 DQ Delay:
8084 22:55:39.827238 DQ0 =131, DQ1 =131, DQ2 =131, DQ3 =127
8085 22:55:39.830983 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
8086 22:55:39.837048 DQ8 =115, DQ9 =115, DQ10 =123, DQ11 =115
8087 22:55:39.840450 DQ12 =127, DQ13 =131, DQ14 =131, DQ15 =131
8088 22:55:39.840532
8089 22:55:39.840596
8090 22:55:39.840654 ==
8091 22:55:39.843853 Dram Type= 6, Freq= 0, CH_0, rank 1
8092 22:55:39.847826 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8093 22:55:39.847907 ==
8094 22:55:39.847972
8095 22:55:39.848031
8096 22:55:39.850906 TX Vref Scan disable
8097 22:55:39.853663 == TX Byte 0 ==
8098 22:55:39.857068 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8099 22:55:39.860504 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8100 22:55:39.863707 == TX Byte 1 ==
8101 22:55:39.867036 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8102 22:55:39.870585 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8103 22:55:39.870667 ==
8104 22:55:39.873653 Dram Type= 6, Freq= 0, CH_0, rank 1
8105 22:55:39.876933 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8106 22:55:39.877014 ==
8107 22:55:39.893331
8108 22:55:39.896773 TX Vref early break, caculate TX vref
8109 22:55:39.899969 TX Vref=16, minBit 8, minWin=22, winSum=374
8110 22:55:39.903755 TX Vref=18, minBit 9, minWin=22, winSum=383
8111 22:55:39.906864 TX Vref=20, minBit 9, minWin=23, winSum=391
8112 22:55:39.909972 TX Vref=22, minBit 9, minWin=23, winSum=401
8113 22:55:39.913389 TX Vref=24, minBit 4, minWin=24, winSum=411
8114 22:55:39.919670 TX Vref=26, minBit 2, minWin=25, winSum=420
8115 22:55:39.923387 TX Vref=28, minBit 4, minWin=24, winSum=419
8116 22:55:39.926861 TX Vref=30, minBit 0, minWin=25, winSum=419
8117 22:55:39.929641 TX Vref=32, minBit 0, minWin=25, winSum=411
8118 22:55:39.933197 TX Vref=34, minBit 8, minWin=24, winSum=403
8119 22:55:39.936689 TX Vref=36, minBit 4, minWin=23, winSum=393
8120 22:55:39.943521 [TxChooseVref] Worse bit 2, Min win 25, Win sum 420, Final Vref 26
8121 22:55:39.943603
8122 22:55:39.946550 Final TX Range 0 Vref 26
8123 22:55:39.946632
8124 22:55:39.946697 ==
8125 22:55:39.949886 Dram Type= 6, Freq= 0, CH_0, rank 1
8126 22:55:39.952985 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8127 22:55:39.953068 ==
8128 22:55:39.953132
8129 22:55:39.953192
8130 22:55:39.956659 TX Vref Scan disable
8131 22:55:39.963080 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8132 22:55:39.963162 == TX Byte 0 ==
8133 22:55:39.966430 u2DelayCellOfst[0]=10 cells (3 PI)
8134 22:55:39.969748 u2DelayCellOfst[1]=17 cells (5 PI)
8135 22:55:39.973112 u2DelayCellOfst[2]=10 cells (3 PI)
8136 22:55:39.976481 u2DelayCellOfst[3]=10 cells (3 PI)
8137 22:55:39.979760 u2DelayCellOfst[4]=10 cells (3 PI)
8138 22:55:39.983090 u2DelayCellOfst[5]=0 cells (0 PI)
8139 22:55:39.986405 u2DelayCellOfst[6]=17 cells (5 PI)
8140 22:55:39.989642 u2DelayCellOfst[7]=17 cells (5 PI)
8141 22:55:39.993068 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8142 22:55:39.996371 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8143 22:55:39.999174 == TX Byte 1 ==
8144 22:55:40.002625 u2DelayCellOfst[8]=0 cells (0 PI)
8145 22:55:40.006266 u2DelayCellOfst[9]=0 cells (0 PI)
8146 22:55:40.009487 u2DelayCellOfst[10]=3 cells (1 PI)
8147 22:55:40.009569 u2DelayCellOfst[11]=0 cells (0 PI)
8148 22:55:40.012769 u2DelayCellOfst[12]=10 cells (3 PI)
8149 22:55:40.016016 u2DelayCellOfst[13]=10 cells (3 PI)
8150 22:55:40.019265 u2DelayCellOfst[14]=14 cells (4 PI)
8151 22:55:40.022359 u2DelayCellOfst[15]=10 cells (3 PI)
8152 22:55:40.029302 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8153 22:55:40.032472 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8154 22:55:40.032554 DramC Write-DBI on
8155 22:55:40.035651 ==
8156 22:55:40.035732 Dram Type= 6, Freq= 0, CH_0, rank 1
8157 22:55:40.042400 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8158 22:55:40.042482 ==
8159 22:55:40.042546
8160 22:55:40.042606
8161 22:55:40.045861 TX Vref Scan disable
8162 22:55:40.045943 == TX Byte 0 ==
8163 22:55:40.052402 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8164 22:55:40.052484 == TX Byte 1 ==
8165 22:55:40.055917 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8166 22:55:40.059038 DramC Write-DBI off
8167 22:55:40.059120
8168 22:55:40.059184 [DATLAT]
8169 22:55:40.062445 Freq=1600, CH0 RK1
8170 22:55:40.062527
8171 22:55:40.062590 DATLAT Default: 0xf
8172 22:55:40.065846 0, 0xFFFF, sum = 0
8173 22:55:40.065929 1, 0xFFFF, sum = 0
8174 22:55:40.069397 2, 0xFFFF, sum = 0
8175 22:55:40.069480 3, 0xFFFF, sum = 0
8176 22:55:40.072350 4, 0xFFFF, sum = 0
8177 22:55:40.072433 5, 0xFFFF, sum = 0
8178 22:55:40.075566 6, 0xFFFF, sum = 0
8179 22:55:40.075676 7, 0xFFFF, sum = 0
8180 22:55:40.079099 8, 0xFFFF, sum = 0
8181 22:55:40.079182 9, 0xFFFF, sum = 0
8182 22:55:40.082061 10, 0xFFFF, sum = 0
8183 22:55:40.085746 11, 0xFFFF, sum = 0
8184 22:55:40.085829 12, 0xFFFF, sum = 0
8185 22:55:40.088801 13, 0xFFFF, sum = 0
8186 22:55:40.088884 14, 0x0, sum = 1
8187 22:55:40.092180 15, 0x0, sum = 2
8188 22:55:40.092263 16, 0x0, sum = 3
8189 22:55:40.095856 17, 0x0, sum = 4
8190 22:55:40.095939 best_step = 15
8191 22:55:40.096002
8192 22:55:40.096062 ==
8193 22:55:40.098570 Dram Type= 6, Freq= 0, CH_0, rank 1
8194 22:55:40.102288 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8195 22:55:40.102371 ==
8196 22:55:40.105401 RX Vref Scan: 0
8197 22:55:40.105483
8198 22:55:40.108713 RX Vref 0 -> 0, step: 1
8199 22:55:40.108795
8200 22:55:40.108860 RX Delay 11 -> 252, step: 4
8201 22:55:40.115975 iDelay=195, Bit 0, Center 126 (71 ~ 182) 112
8202 22:55:40.119118 iDelay=195, Bit 1, Center 130 (75 ~ 186) 112
8203 22:55:40.122511 iDelay=195, Bit 2, Center 126 (71 ~ 182) 112
8204 22:55:40.125564 iDelay=195, Bit 3, Center 126 (71 ~ 182) 112
8205 22:55:40.129118 iDelay=195, Bit 4, Center 128 (75 ~ 182) 108
8206 22:55:40.135711 iDelay=195, Bit 5, Center 116 (63 ~ 170) 108
8207 22:55:40.139457 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8208 22:55:40.142718 iDelay=195, Bit 7, Center 136 (83 ~ 190) 108
8209 22:55:40.145649 iDelay=195, Bit 8, Center 112 (59 ~ 166) 108
8210 22:55:40.149323 iDelay=195, Bit 9, Center 110 (55 ~ 166) 112
8211 22:55:40.155519 iDelay=195, Bit 10, Center 122 (67 ~ 178) 112
8212 22:55:40.159008 iDelay=195, Bit 11, Center 116 (63 ~ 170) 108
8213 22:55:40.162761 iDelay=195, Bit 12, Center 126 (75 ~ 178) 104
8214 22:55:40.165438 iDelay=195, Bit 13, Center 128 (75 ~ 182) 108
8215 22:55:40.168905 iDelay=195, Bit 14, Center 134 (79 ~ 190) 112
8216 22:55:40.175672 iDelay=195, Bit 15, Center 130 (75 ~ 186) 112
8217 22:55:40.175744 ==
8218 22:55:40.179046 Dram Type= 6, Freq= 0, CH_0, rank 1
8219 22:55:40.182245 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8220 22:55:40.182316 ==
8221 22:55:40.182376 DQS Delay:
8222 22:55:40.185525 DQS0 = 0, DQS1 = 0
8223 22:55:40.185592 DQM Delay:
8224 22:55:40.189092 DQM0 = 128, DQM1 = 122
8225 22:55:40.189192 DQ Delay:
8226 22:55:40.191978 DQ0 =126, DQ1 =130, DQ2 =126, DQ3 =126
8227 22:55:40.196165 DQ4 =128, DQ5 =116, DQ6 =138, DQ7 =136
8228 22:55:40.198926 DQ8 =112, DQ9 =110, DQ10 =122, DQ11 =116
8229 22:55:40.202391 DQ12 =126, DQ13 =128, DQ14 =134, DQ15 =130
8230 22:55:40.205536
8231 22:55:40.205619
8232 22:55:40.205684
8233 22:55:40.205744 [DramC_TX_OE_Calibration] TA2
8234 22:55:40.208721 Original DQ_B0 (3 6) =30, OEN = 27
8235 22:55:40.212832 Original DQ_B1 (3 6) =30, OEN = 27
8236 22:55:40.215575 24, 0x0, End_B0=24 End_B1=24
8237 22:55:40.218736 25, 0x0, End_B0=25 End_B1=25
8238 22:55:40.222019 26, 0x0, End_B0=26 End_B1=26
8239 22:55:40.222104 27, 0x0, End_B0=27 End_B1=27
8240 22:55:40.225250 28, 0x0, End_B0=28 End_B1=28
8241 22:55:40.228902 29, 0x0, End_B0=29 End_B1=29
8242 22:55:40.231810 30, 0x0, End_B0=30 End_B1=30
8243 22:55:40.235681 31, 0x4141, End_B0=30 End_B1=30
8244 22:55:40.238532 Byte0 end_step=30 best_step=27
8245 22:55:40.238615 Byte1 end_step=30 best_step=27
8246 22:55:40.241734 Byte0 TX OE(2T, 0.5T) = (3, 3)
8247 22:55:40.245049 Byte1 TX OE(2T, 0.5T) = (3, 3)
8248 22:55:40.245133
8249 22:55:40.245198
8250 22:55:40.255295 [DQSOSCAuto] RK1, (LSB)MR18= 0x1a0e, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 396 ps
8251 22:55:40.255401 CH0 RK1: MR19=303, MR18=1A0E
8252 22:55:40.261969 CH0_RK1: MR19=0x303, MR18=0x1A0E, DQSOSC=396, MR23=63, INC=23, DEC=15
8253 22:55:40.264907 [RxdqsGatingPostProcess] freq 1600
8254 22:55:40.271688 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8255 22:55:40.275304 best DQS0 dly(2T, 0.5T) = (1, 1)
8256 22:55:40.278167 best DQS1 dly(2T, 0.5T) = (1, 1)
8257 22:55:40.281848 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8258 22:55:40.285297 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8259 22:55:40.285381 best DQS0 dly(2T, 0.5T) = (1, 1)
8260 22:55:40.288337 best DQS1 dly(2T, 0.5T) = (1, 1)
8261 22:55:40.291382 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8262 22:55:40.295296 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8263 22:55:40.298284 Pre-setting of DQS Precalculation
8264 22:55:40.304461 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8265 22:55:40.304539 ==
8266 22:55:40.308439 Dram Type= 6, Freq= 0, CH_1, rank 0
8267 22:55:40.311389 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8268 22:55:40.311471 ==
8269 22:55:40.318319 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8270 22:55:40.321244 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8271 22:55:40.324762 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8272 22:55:40.331337 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8273 22:55:40.339888 [CA 0] Center 43 (14~73) winsize 60
8274 22:55:40.342999 [CA 1] Center 43 (14~72) winsize 59
8275 22:55:40.346864 [CA 2] Center 38 (9~67) winsize 59
8276 22:55:40.350164 [CA 3] Center 36 (7~66) winsize 60
8277 22:55:40.353067 [CA 4] Center 38 (9~68) winsize 60
8278 22:55:40.356278 [CA 5] Center 37 (8~66) winsize 59
8279 22:55:40.356355
8280 22:55:40.359747 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8281 22:55:40.359829
8282 22:55:40.363237 [CATrainingPosCal] consider 1 rank data
8283 22:55:40.366621 u2DelayCellTimex100 = 275/100 ps
8284 22:55:40.370134 CA0 delay=43 (14~73),Diff = 7 PI (24 cell)
8285 22:55:40.376734 CA1 delay=43 (14~72),Diff = 7 PI (24 cell)
8286 22:55:40.379697 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8287 22:55:40.383079 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8288 22:55:40.387032 CA4 delay=38 (9~68),Diff = 2 PI (7 cell)
8289 22:55:40.389625 CA5 delay=37 (8~66),Diff = 1 PI (3 cell)
8290 22:55:40.389704
8291 22:55:40.393159 CA PerBit enable=1, Macro0, CA PI delay=36
8292 22:55:40.393234
8293 22:55:40.396379 [CBTSetCACLKResult] CA Dly = 36
8294 22:55:40.399970 CS Dly: 9 (0~40)
8295 22:55:40.403527 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8296 22:55:40.406780 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8297 22:55:40.406860 ==
8298 22:55:40.409859 Dram Type= 6, Freq= 0, CH_1, rank 1
8299 22:55:40.413093 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8300 22:55:40.413174 ==
8301 22:55:40.419642 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8302 22:55:40.422754 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8303 22:55:40.429863 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8304 22:55:40.432830 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8305 22:55:40.442904 [CA 0] Center 43 (14~72) winsize 59
8306 22:55:40.446717 [CA 1] Center 43 (14~72) winsize 59
8307 22:55:40.449867 [CA 2] Center 38 (9~67) winsize 59
8308 22:55:40.452938 [CA 3] Center 37 (7~67) winsize 61
8309 22:55:40.456434 [CA 4] Center 38 (9~68) winsize 60
8310 22:55:40.459993 [CA 5] Center 36 (7~66) winsize 60
8311 22:55:40.460070
8312 22:55:40.462797 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8313 22:55:40.462868
8314 22:55:40.466340 [CATrainingPosCal] consider 2 rank data
8315 22:55:40.469509 u2DelayCellTimex100 = 275/100 ps
8316 22:55:40.472747 CA0 delay=43 (14~72),Diff = 7 PI (24 cell)
8317 22:55:40.479588 CA1 delay=43 (14~72),Diff = 7 PI (24 cell)
8318 22:55:40.482557 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8319 22:55:40.486015 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8320 22:55:40.489204 CA4 delay=38 (9~68),Diff = 2 PI (7 cell)
8321 22:55:40.492606 CA5 delay=37 (8~66),Diff = 1 PI (3 cell)
8322 22:55:40.492685
8323 22:55:40.496813 CA PerBit enable=1, Macro0, CA PI delay=36
8324 22:55:40.497158
8325 22:55:40.500196 [CBTSetCACLKResult] CA Dly = 36
8326 22:55:40.503209 CS Dly: 11 (0~44)
8327 22:55:40.507009 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8328 22:55:40.509923 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8329 22:55:40.510434
8330 22:55:40.512984 ----->DramcWriteLeveling(PI) begin...
8331 22:55:40.513404 ==
8332 22:55:40.517286 Dram Type= 6, Freq= 0, CH_1, rank 0
8333 22:55:40.519812 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8334 22:55:40.523478 ==
8335 22:55:40.523889 Write leveling (Byte 0): 26 => 26
8336 22:55:40.526729 Write leveling (Byte 1): 29 => 29
8337 22:55:40.530143 DramcWriteLeveling(PI) end<-----
8338 22:55:40.530564
8339 22:55:40.530885 ==
8340 22:55:40.533470 Dram Type= 6, Freq= 0, CH_1, rank 0
8341 22:55:40.539736 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8342 22:55:40.540238 ==
8343 22:55:40.540611 [Gating] SW mode calibration
8344 22:55:40.549714 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8345 22:55:40.553590 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8346 22:55:40.559806 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8347 22:55:40.562732 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8348 22:55:40.566500 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8349 22:55:40.573384 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8350 22:55:40.576233 1 4 16 | B1->B0 | 2f2f 2525 | 1 0 | (1 1) (0 0)
8351 22:55:40.579294 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8352 22:55:40.586354 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8353 22:55:40.589882 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8354 22:55:40.592858 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8355 22:55:40.596071 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8356 22:55:40.603325 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8357 22:55:40.606281 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8358 22:55:40.609984 1 5 16 | B1->B0 | 2828 2f2f | 0 0 | (0 1) (0 1)
8359 22:55:40.616397 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8360 22:55:40.619703 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8361 22:55:40.623306 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8362 22:55:40.629941 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8363 22:55:40.632774 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8364 22:55:40.636006 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8365 22:55:40.642817 1 6 12 | B1->B0 | 2424 2424 | 0 0 | (0 0) (0 0)
8366 22:55:40.646198 1 6 16 | B1->B0 | 3737 2c2c | 1 0 | (0 0) (0 0)
8367 22:55:40.649344 1 6 20 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
8368 22:55:40.656251 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8369 22:55:40.659559 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8370 22:55:40.662772 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8371 22:55:40.669259 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8372 22:55:40.672570 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8373 22:55:40.676167 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8374 22:55:40.682806 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8375 22:55:40.685908 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8376 22:55:40.689482 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8377 22:55:40.696195 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8378 22:55:40.698993 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8379 22:55:40.702675 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8380 22:55:40.709292 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8381 22:55:40.712406 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8382 22:55:40.715413 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8383 22:55:40.722589 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8384 22:55:40.725721 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8385 22:55:40.729276 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8386 22:55:40.736220 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8387 22:55:40.739925 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8388 22:55:40.742267 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8389 22:55:40.749400 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8390 22:55:40.752134 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8391 22:55:40.755762 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8392 22:55:40.758918 Total UI for P1: 0, mck2ui 16
8393 22:55:40.762192 best dqsien dly found for B0: ( 1, 9, 14)
8394 22:55:40.765415 Total UI for P1: 0, mck2ui 16
8395 22:55:40.768606 best dqsien dly found for B1: ( 1, 9, 16)
8396 22:55:40.772097 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8397 22:55:40.775313 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8398 22:55:40.775771
8399 22:55:40.778756 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8400 22:55:40.785337 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8401 22:55:40.785865 [Gating] SW calibration Done
8402 22:55:40.786200 ==
8403 22:55:40.788699 Dram Type= 6, Freq= 0, CH_1, rank 0
8404 22:55:40.795474 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8405 22:55:40.795990 ==
8406 22:55:40.796324 RX Vref Scan: 0
8407 22:55:40.796634
8408 22:55:40.798713 RX Vref 0 -> 0, step: 1
8409 22:55:40.799266
8410 22:55:40.801689 RX Delay 0 -> 252, step: 8
8411 22:55:40.805426 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8412 22:55:40.808501 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8413 22:55:40.812388 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8414 22:55:40.815256 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8415 22:55:40.821995 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8416 22:55:40.825572 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8417 22:55:40.828173 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
8418 22:55:40.832157 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8419 22:55:40.835277 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8420 22:55:40.842191 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
8421 22:55:40.845564 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8422 22:55:40.848873 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8423 22:55:40.851529 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8424 22:55:40.858164 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8425 22:55:40.862107 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8426 22:55:40.865248 iDelay=200, Bit 15, Center 131 (80 ~ 183) 104
8427 22:55:40.865677 ==
8428 22:55:40.868087 Dram Type= 6, Freq= 0, CH_1, rank 0
8429 22:55:40.871820 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8430 22:55:40.872370 ==
8431 22:55:40.874962 DQS Delay:
8432 22:55:40.875507 DQS0 = 0, DQS1 = 0
8433 22:55:40.878615 DQM Delay:
8434 22:55:40.879139 DQM0 = 135, DQM1 = 126
8435 22:55:40.879532 DQ Delay:
8436 22:55:40.881822 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8437 22:55:40.888328 DQ4 =135, DQ5 =143, DQ6 =143, DQ7 =135
8438 22:55:40.891527 DQ8 =111, DQ9 =115, DQ10 =127, DQ11 =123
8439 22:55:40.894713 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =131
8440 22:55:40.895264
8441 22:55:40.895659
8442 22:55:40.895973 ==
8443 22:55:40.898085 Dram Type= 6, Freq= 0, CH_1, rank 0
8444 22:55:40.901422 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8445 22:55:40.901999 ==
8446 22:55:40.902346
8447 22:55:40.902655
8448 22:55:40.905043 TX Vref Scan disable
8449 22:55:40.907887 == TX Byte 0 ==
8450 22:55:40.911604 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8451 22:55:40.914715 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8452 22:55:40.918187 == TX Byte 1 ==
8453 22:55:40.921643 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8454 22:55:40.925158 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8455 22:55:40.925683 ==
8456 22:55:40.928020 Dram Type= 6, Freq= 0, CH_1, rank 0
8457 22:55:40.931868 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8458 22:55:40.935201 ==
8459 22:55:40.945426
8460 22:55:40.948621 TX Vref early break, caculate TX vref
8461 22:55:40.952053 TX Vref=16, minBit 8, minWin=21, winSum=358
8462 22:55:40.955245 TX Vref=18, minBit 8, minWin=21, winSum=371
8463 22:55:40.958660 TX Vref=20, minBit 8, minWin=21, winSum=377
8464 22:55:40.961749 TX Vref=22, minBit 0, minWin=23, winSum=394
8465 22:55:40.965066 TX Vref=24, minBit 8, minWin=22, winSum=395
8466 22:55:40.971946 TX Vref=26, minBit 11, minWin=24, winSum=409
8467 22:55:40.975003 TX Vref=28, minBit 5, minWin=25, winSum=414
8468 22:55:40.978707 TX Vref=30, minBit 1, minWin=25, winSum=416
8469 22:55:40.981472 TX Vref=32, minBit 6, minWin=24, winSum=408
8470 22:55:40.984811 TX Vref=34, minBit 11, minWin=23, winSum=394
8471 22:55:40.991646 [TxChooseVref] Worse bit 1, Min win 25, Win sum 416, Final Vref 30
8472 22:55:40.991755
8473 22:55:40.994904 Final TX Range 0 Vref 30
8474 22:55:40.994986
8475 22:55:40.995050 ==
8476 22:55:40.998521 Dram Type= 6, Freq= 0, CH_1, rank 0
8477 22:55:41.001248 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8478 22:55:41.001331 ==
8479 22:55:41.001396
8480 22:55:41.001456
8481 22:55:41.004864 TX Vref Scan disable
8482 22:55:41.011308 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8483 22:55:41.011414 == TX Byte 0 ==
8484 22:55:41.014397 u2DelayCellOfst[0]=17 cells (5 PI)
8485 22:55:41.018345 u2DelayCellOfst[1]=10 cells (3 PI)
8486 22:55:41.021241 u2DelayCellOfst[2]=0 cells (0 PI)
8487 22:55:41.024786 u2DelayCellOfst[3]=7 cells (2 PI)
8488 22:55:41.027726 u2DelayCellOfst[4]=10 cells (3 PI)
8489 22:55:41.030892 u2DelayCellOfst[5]=17 cells (5 PI)
8490 22:55:41.034247 u2DelayCellOfst[6]=17 cells (5 PI)
8491 22:55:41.037618 u2DelayCellOfst[7]=7 cells (2 PI)
8492 22:55:41.040907 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8493 22:55:41.044200 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8494 22:55:41.047862 == TX Byte 1 ==
8495 22:55:41.051013 u2DelayCellOfst[8]=0 cells (0 PI)
8496 22:55:41.051095 u2DelayCellOfst[9]=3 cells (1 PI)
8497 22:55:41.054190 u2DelayCellOfst[10]=7 cells (2 PI)
8498 22:55:41.057515 u2DelayCellOfst[11]=3 cells (1 PI)
8499 22:55:41.061353 u2DelayCellOfst[12]=10 cells (3 PI)
8500 22:55:41.064663 u2DelayCellOfst[13]=14 cells (4 PI)
8501 22:55:41.067896 u2DelayCellOfst[14]=14 cells (4 PI)
8502 22:55:41.070924 u2DelayCellOfst[15]=17 cells (5 PI)
8503 22:55:41.074290 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8504 22:55:41.080525 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8505 22:55:41.080608 DramC Write-DBI on
8506 22:55:41.080673 ==
8507 22:55:41.084417 Dram Type= 6, Freq= 0, CH_1, rank 0
8508 22:55:41.090553 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8509 22:55:41.090636 ==
8510 22:55:41.090701
8511 22:55:41.090760
8512 22:55:41.090818 TX Vref Scan disable
8513 22:55:41.094525 == TX Byte 0 ==
8514 22:55:41.097669 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8515 22:55:41.101386 == TX Byte 1 ==
8516 22:55:41.104539 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8517 22:55:41.107910 DramC Write-DBI off
8518 22:55:41.107991
8519 22:55:41.108055 [DATLAT]
8520 22:55:41.108114 Freq=1600, CH1 RK0
8521 22:55:41.108172
8522 22:55:41.111216 DATLAT Default: 0xf
8523 22:55:41.111339 0, 0xFFFF, sum = 0
8524 22:55:41.114530 1, 0xFFFF, sum = 0
8525 22:55:41.117719 2, 0xFFFF, sum = 0
8526 22:55:41.117793 3, 0xFFFF, sum = 0
8527 22:55:41.121418 4, 0xFFFF, sum = 0
8528 22:55:41.121492 5, 0xFFFF, sum = 0
8529 22:55:41.124348 6, 0xFFFF, sum = 0
8530 22:55:41.124417 7, 0xFFFF, sum = 0
8531 22:55:41.127918 8, 0xFFFF, sum = 0
8532 22:55:41.128001 9, 0xFFFF, sum = 0
8533 22:55:41.130981 10, 0xFFFF, sum = 0
8534 22:55:41.131064 11, 0xFFFF, sum = 0
8535 22:55:41.134176 12, 0xFFFF, sum = 0
8536 22:55:41.134259 13, 0xFFFF, sum = 0
8537 22:55:41.138260 14, 0x0, sum = 1
8538 22:55:41.138373 15, 0x0, sum = 2
8539 22:55:41.140868 16, 0x0, sum = 3
8540 22:55:41.140951 17, 0x0, sum = 4
8541 22:55:41.144484 best_step = 15
8542 22:55:41.144565
8543 22:55:41.144630 ==
8544 22:55:41.147959 Dram Type= 6, Freq= 0, CH_1, rank 0
8545 22:55:41.150996 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8546 22:55:41.151079 ==
8547 22:55:41.153982 RX Vref Scan: 1
8548 22:55:41.154076
8549 22:55:41.154140 Set Vref Range= 24 -> 127
8550 22:55:41.154200
8551 22:55:41.157398 RX Vref 24 -> 127, step: 1
8552 22:55:41.157479
8553 22:55:41.161281 RX Delay 11 -> 252, step: 4
8554 22:55:41.161385
8555 22:55:41.164370 Set Vref, RX VrefLevel [Byte0]: 24
8556 22:55:41.167214 [Byte1]: 24
8557 22:55:41.167296
8558 22:55:41.170710 Set Vref, RX VrefLevel [Byte0]: 25
8559 22:55:41.173838 [Byte1]: 25
8560 22:55:41.177879
8561 22:55:41.177960 Set Vref, RX VrefLevel [Byte0]: 26
8562 22:55:41.180858 [Byte1]: 26
8563 22:55:41.185774
8564 22:55:41.185857 Set Vref, RX VrefLevel [Byte0]: 27
8565 22:55:41.188065 [Byte1]: 27
8566 22:55:41.192894
8567 22:55:41.192975 Set Vref, RX VrefLevel [Byte0]: 28
8568 22:55:41.196304 [Byte1]: 28
8569 22:55:41.200271
8570 22:55:41.200353 Set Vref, RX VrefLevel [Byte0]: 29
8571 22:55:41.203897 [Byte1]: 29
8572 22:55:41.208183
8573 22:55:41.208264 Set Vref, RX VrefLevel [Byte0]: 30
8574 22:55:41.211394 [Byte1]: 30
8575 22:55:41.215327
8576 22:55:41.215428 Set Vref, RX VrefLevel [Byte0]: 31
8577 22:55:41.218568 [Byte1]: 31
8578 22:55:41.223168
8579 22:55:41.223249 Set Vref, RX VrefLevel [Byte0]: 32
8580 22:55:41.226357 [Byte1]: 32
8581 22:55:41.230747
8582 22:55:41.230828 Set Vref, RX VrefLevel [Byte0]: 33
8583 22:55:41.234114 [Byte1]: 33
8584 22:55:41.238605
8585 22:55:41.238686 Set Vref, RX VrefLevel [Byte0]: 34
8586 22:55:41.241559 [Byte1]: 34
8587 22:55:41.246271
8588 22:55:41.246352 Set Vref, RX VrefLevel [Byte0]: 35
8589 22:55:41.249551 [Byte1]: 35
8590 22:55:41.253672
8591 22:55:41.253753 Set Vref, RX VrefLevel [Byte0]: 36
8592 22:55:41.257238 [Byte1]: 36
8593 22:55:41.261352
8594 22:55:41.261433 Set Vref, RX VrefLevel [Byte0]: 37
8595 22:55:41.264801 [Byte1]: 37
8596 22:55:41.268704
8597 22:55:41.268786 Set Vref, RX VrefLevel [Byte0]: 38
8598 22:55:41.272004 [Byte1]: 38
8599 22:55:41.276267
8600 22:55:41.276348 Set Vref, RX VrefLevel [Byte0]: 39
8601 22:55:41.279714 [Byte1]: 39
8602 22:55:41.283766
8603 22:55:41.283848 Set Vref, RX VrefLevel [Byte0]: 40
8604 22:55:41.287324 [Byte1]: 40
8605 22:55:41.291774
8606 22:55:41.291892 Set Vref, RX VrefLevel [Byte0]: 41
8607 22:55:41.295470 [Byte1]: 41
8608 22:55:41.299107
8609 22:55:41.299188 Set Vref, RX VrefLevel [Byte0]: 42
8610 22:55:41.302312 [Byte1]: 42
8611 22:55:41.306923
8612 22:55:41.307004 Set Vref, RX VrefLevel [Byte0]: 43
8613 22:55:41.310438 [Byte1]: 43
8614 22:55:41.314203
8615 22:55:41.314284 Set Vref, RX VrefLevel [Byte0]: 44
8616 22:55:41.317827 [Byte1]: 44
8617 22:55:41.321837
8618 22:55:41.321918 Set Vref, RX VrefLevel [Byte0]: 45
8619 22:55:41.325312 [Byte1]: 45
8620 22:55:41.329629
8621 22:55:41.329710 Set Vref, RX VrefLevel [Byte0]: 46
8622 22:55:41.332918 [Byte1]: 46
8623 22:55:41.337334
8624 22:55:41.337415 Set Vref, RX VrefLevel [Byte0]: 47
8625 22:55:41.340377 [Byte1]: 47
8626 22:55:41.344814
8627 22:55:41.344895 Set Vref, RX VrefLevel [Byte0]: 48
8628 22:55:41.348421 [Byte1]: 48
8629 22:55:41.352681
8630 22:55:41.352762 Set Vref, RX VrefLevel [Byte0]: 49
8631 22:55:41.355776 [Byte1]: 49
8632 22:55:41.360100
8633 22:55:41.360181 Set Vref, RX VrefLevel [Byte0]: 50
8634 22:55:41.363672 [Byte1]: 50
8635 22:55:41.367774
8636 22:55:41.367855 Set Vref, RX VrefLevel [Byte0]: 51
8637 22:55:41.370969 [Byte1]: 51
8638 22:55:41.375380
8639 22:55:41.375474 Set Vref, RX VrefLevel [Byte0]: 52
8640 22:55:41.378471 [Byte1]: 52
8641 22:55:41.382861
8642 22:55:41.382943 Set Vref, RX VrefLevel [Byte0]: 53
8643 22:55:41.386358 [Byte1]: 53
8644 22:55:41.390486
8645 22:55:41.390568 Set Vref, RX VrefLevel [Byte0]: 54
8646 22:55:41.394173 [Byte1]: 54
8647 22:55:41.398005
8648 22:55:41.398086 Set Vref, RX VrefLevel [Byte0]: 55
8649 22:55:41.401159 [Byte1]: 55
8650 22:55:41.405826
8651 22:55:41.405908 Set Vref, RX VrefLevel [Byte0]: 56
8652 22:55:41.409197 [Byte1]: 56
8653 22:55:41.413471
8654 22:55:41.413553 Set Vref, RX VrefLevel [Byte0]: 57
8655 22:55:41.416725 [Byte1]: 57
8656 22:55:41.421370
8657 22:55:41.421450 Set Vref, RX VrefLevel [Byte0]: 58
8658 22:55:41.424039 [Byte1]: 58
8659 22:55:41.428679
8660 22:55:41.428761 Set Vref, RX VrefLevel [Byte0]: 59
8661 22:55:41.432067 [Byte1]: 59
8662 22:55:41.436108
8663 22:55:41.436189 Set Vref, RX VrefLevel [Byte0]: 60
8664 22:55:41.439200 [Byte1]: 60
8665 22:55:41.444081
8666 22:55:41.444162 Set Vref, RX VrefLevel [Byte0]: 61
8667 22:55:41.447124 [Byte1]: 61
8668 22:55:41.451336
8669 22:55:41.451457 Set Vref, RX VrefLevel [Byte0]: 62
8670 22:55:41.454941 [Byte1]: 62
8671 22:55:41.459109
8672 22:55:41.459190 Set Vref, RX VrefLevel [Byte0]: 63
8673 22:55:41.462608 [Byte1]: 63
8674 22:55:41.466870
8675 22:55:41.466952 Set Vref, RX VrefLevel [Byte0]: 64
8676 22:55:41.470061 [Byte1]: 64
8677 22:55:41.474513
8678 22:55:41.474594 Set Vref, RX VrefLevel [Byte0]: 65
8679 22:55:41.477353 [Byte1]: 65
8680 22:55:41.481843
8681 22:55:41.481930 Set Vref, RX VrefLevel [Byte0]: 66
8682 22:55:41.485182 [Byte1]: 66
8683 22:55:41.489776
8684 22:55:41.489858 Set Vref, RX VrefLevel [Byte0]: 67
8685 22:55:41.493075 [Byte1]: 67
8686 22:55:41.497230
8687 22:55:41.497312 Set Vref, RX VrefLevel [Byte0]: 68
8688 22:55:41.500486 [Byte1]: 68
8689 22:55:41.505093
8690 22:55:41.505174 Set Vref, RX VrefLevel [Byte0]: 69
8691 22:55:41.508074 [Byte1]: 69
8692 22:55:41.512250
8693 22:55:41.512332 Set Vref, RX VrefLevel [Byte0]: 70
8694 22:55:41.515552 [Byte1]: 70
8695 22:55:41.520035
8696 22:55:41.520116 Set Vref, RX VrefLevel [Byte0]: 71
8697 22:55:41.522979 [Byte1]: 71
8698 22:55:41.527578
8699 22:55:41.527659 Set Vref, RX VrefLevel [Byte0]: 72
8700 22:55:41.531071 [Byte1]: 72
8701 22:55:41.535204
8702 22:55:41.535285 Set Vref, RX VrefLevel [Byte0]: 73
8703 22:55:41.538345 [Byte1]: 73
8704 22:55:41.542637
8705 22:55:41.542718 Set Vref, RX VrefLevel [Byte0]: 74
8706 22:55:41.546085 [Byte1]: 74
8707 22:55:41.550207
8708 22:55:41.550288 Set Vref, RX VrefLevel [Byte0]: 75
8709 22:55:41.553554 [Byte1]: 75
8710 22:55:41.558052
8711 22:55:41.558133 Final RX Vref Byte 0 = 52 to rank0
8712 22:55:41.561556 Final RX Vref Byte 1 = 58 to rank0
8713 22:55:41.564681 Final RX Vref Byte 0 = 52 to rank1
8714 22:55:41.567935 Final RX Vref Byte 1 = 58 to rank1==
8715 22:55:41.570894 Dram Type= 6, Freq= 0, CH_1, rank 0
8716 22:55:41.577600 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8717 22:55:41.577708 ==
8718 22:55:41.577806 DQS Delay:
8719 22:55:41.581128 DQS0 = 0, DQS1 = 0
8720 22:55:41.581229 DQM Delay:
8721 22:55:41.581337 DQM0 = 131, DQM1 = 124
8722 22:55:41.584241 DQ Delay:
8723 22:55:41.587594 DQ0 =136, DQ1 =126, DQ2 =118, DQ3 =128
8724 22:55:41.591147 DQ4 =132, DQ5 =142, DQ6 =140, DQ7 =128
8725 22:55:41.594259 DQ8 =110, DQ9 =114, DQ10 =126, DQ11 =118
8726 22:55:41.597366 DQ12 =132, DQ13 =132, DQ14 =130, DQ15 =132
8727 22:55:41.597465
8728 22:55:41.597558
8729 22:55:41.597646
8730 22:55:41.600925 [DramC_TX_OE_Calibration] TA2
8731 22:55:41.604236 Original DQ_B0 (3 6) =30, OEN = 27
8732 22:55:41.607907 Original DQ_B1 (3 6) =30, OEN = 27
8733 22:55:41.611157 24, 0x0, End_B0=24 End_B1=24
8734 22:55:41.611275 25, 0x0, End_B0=25 End_B1=25
8735 22:55:41.614299 26, 0x0, End_B0=26 End_B1=26
8736 22:55:41.617577 27, 0x0, End_B0=27 End_B1=27
8737 22:55:41.620557 28, 0x0, End_B0=28 End_B1=28
8738 22:55:41.624170 29, 0x0, End_B0=29 End_B1=29
8739 22:55:41.624253 30, 0x0, End_B0=30 End_B1=30
8740 22:55:41.627544 31, 0x4141, End_B0=30 End_B1=30
8741 22:55:41.630731 Byte0 end_step=30 best_step=27
8742 22:55:41.634114 Byte1 end_step=30 best_step=27
8743 22:55:41.637461 Byte0 TX OE(2T, 0.5T) = (3, 3)
8744 22:55:41.641222 Byte1 TX OE(2T, 0.5T) = (3, 3)
8745 22:55:41.641304
8746 22:55:41.641368
8747 22:55:41.647172 [DQSOSCAuto] RK0, (LSB)MR18= 0x14ff, (MSB)MR19= 0x302, tDQSOscB0 = 410 ps tDQSOscB1 = 399 ps
8748 22:55:41.650584 CH1 RK0: MR19=302, MR18=14FF
8749 22:55:41.657293 CH1_RK0: MR19=0x302, MR18=0x14FF, DQSOSC=399, MR23=63, INC=23, DEC=15
8750 22:55:41.657468
8751 22:55:41.660780 ----->DramcWriteLeveling(PI) begin...
8752 22:55:41.660957 ==
8753 22:55:41.663968 Dram Type= 6, Freq= 0, CH_1, rank 1
8754 22:55:41.667049 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8755 22:55:41.667205 ==
8756 22:55:41.670668 Write leveling (Byte 0): 24 => 24
8757 22:55:41.673763 Write leveling (Byte 1): 29 => 29
8758 22:55:41.677473 DramcWriteLeveling(PI) end<-----
8759 22:55:41.677608
8760 22:55:41.677714 ==
8761 22:55:41.680924 Dram Type= 6, Freq= 0, CH_1, rank 1
8762 22:55:41.683655 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8763 22:55:41.683808 ==
8764 22:55:41.687415 [Gating] SW mode calibration
8765 22:55:41.694205 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8766 22:55:41.700574 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8767 22:55:41.704417 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8768 22:55:41.710741 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8769 22:55:41.714041 1 4 8 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (1 1)
8770 22:55:41.717783 1 4 12 | B1->B0 | 2b2b 3434 | 1 1 | (1 1) (1 1)
8771 22:55:41.724586 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8772 22:55:41.728066 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8773 22:55:41.730963 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8774 22:55:41.737661 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8775 22:55:41.740884 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8776 22:55:41.743743 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8777 22:55:41.747715 1 5 8 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 0)
8778 22:55:41.754240 1 5 12 | B1->B0 | 2f2f 2525 | 1 0 | (1 0) (0 0)
8779 22:55:41.757376 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8780 22:55:41.760456 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8781 22:55:41.767166 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8782 22:55:41.770942 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8783 22:55:41.773545 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8784 22:55:41.780286 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8785 22:55:41.783913 1 6 8 | B1->B0 | 2424 2e2e | 0 0 | (0 0) (0 0)
8786 22:55:41.787329 1 6 12 | B1->B0 | 3c3c 4646 | 0 0 | (1 1) (0 0)
8787 22:55:41.793775 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8788 22:55:41.797005 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8789 22:55:41.800442 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8790 22:55:41.807535 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8791 22:55:41.810487 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8792 22:55:41.813578 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8793 22:55:41.820161 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8794 22:55:41.824095 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8795 22:55:41.827401 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8796 22:55:41.833759 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8797 22:55:41.837082 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8798 22:55:41.840263 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8799 22:55:41.846535 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8800 22:55:41.850225 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8801 22:55:41.853308 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8802 22:55:41.860064 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8803 22:55:41.863514 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8804 22:55:41.867130 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8805 22:55:41.873783 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8806 22:55:41.876831 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8807 22:55:41.879942 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8808 22:55:41.886428 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8809 22:55:41.890844 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8810 22:55:41.893242 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8811 22:55:41.896855 Total UI for P1: 0, mck2ui 16
8812 22:55:41.899824 best dqsien dly found for B0: ( 1, 9, 6)
8813 22:55:41.903168 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8814 22:55:41.910618 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8815 22:55:41.913218 Total UI for P1: 0, mck2ui 16
8816 22:55:41.917023 best dqsien dly found for B1: ( 1, 9, 14)
8817 22:55:41.919652 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8818 22:55:41.923743 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8819 22:55:41.924279
8820 22:55:41.926669 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8821 22:55:41.930150 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8822 22:55:41.933231 [Gating] SW calibration Done
8823 22:55:41.933661 ==
8824 22:55:41.936494 Dram Type= 6, Freq= 0, CH_1, rank 1
8825 22:55:41.939917 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8826 22:55:41.940416 ==
8827 22:55:41.943766 RX Vref Scan: 0
8828 22:55:41.944295
8829 22:55:41.944639 RX Vref 0 -> 0, step: 1
8830 22:55:41.947114
8831 22:55:41.947689 RX Delay 0 -> 252, step: 8
8832 22:55:41.949977 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8833 22:55:41.956651 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8834 22:55:41.960338 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8835 22:55:41.963196 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8836 22:55:41.966949 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8837 22:55:41.969769 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8838 22:55:41.976756 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8839 22:55:41.979779 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8840 22:55:41.983122 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8841 22:55:41.986597 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8842 22:55:41.990080 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8843 22:55:41.996672 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8844 22:55:41.999982 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8845 22:55:42.003108 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8846 22:55:42.006577 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8847 22:55:42.013202 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8848 22:55:42.013766 ==
8849 22:55:42.016647 Dram Type= 6, Freq= 0, CH_1, rank 1
8850 22:55:42.020322 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8851 22:55:42.020758 ==
8852 22:55:42.021099 DQS Delay:
8853 22:55:42.023281 DQS0 = 0, DQS1 = 0
8854 22:55:42.023885 DQM Delay:
8855 22:55:42.026466 DQM0 = 132, DQM1 = 128
8856 22:55:42.026999 DQ Delay:
8857 22:55:42.029878 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =135
8858 22:55:42.033540 DQ4 =131, DQ5 =143, DQ6 =143, DQ7 =127
8859 22:55:42.036401 DQ8 =119, DQ9 =115, DQ10 =131, DQ11 =119
8860 22:55:42.039685 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8861 22:55:42.040229
8862 22:55:42.040638
8863 22:55:42.042872 ==
8864 22:55:42.043302 Dram Type= 6, Freq= 0, CH_1, rank 1
8865 22:55:42.049674 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8866 22:55:42.050210 ==
8867 22:55:42.050560
8868 22:55:42.050878
8869 22:55:42.053067 TX Vref Scan disable
8870 22:55:42.053597 == TX Byte 0 ==
8871 22:55:42.056381 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8872 22:55:42.062669 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8873 22:55:42.063208 == TX Byte 1 ==
8874 22:55:42.066257 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8875 22:55:42.073185 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8876 22:55:42.073726 ==
8877 22:55:42.076895 Dram Type= 6, Freq= 0, CH_1, rank 1
8878 22:55:42.079457 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8879 22:55:42.080061 ==
8880 22:55:42.093751
8881 22:55:42.097024 TX Vref early break, caculate TX vref
8882 22:55:42.100187 TX Vref=16, minBit 8, minWin=21, winSum=374
8883 22:55:42.103498 TX Vref=18, minBit 8, minWin=22, winSum=383
8884 22:55:42.106730 TX Vref=20, minBit 8, minWin=22, winSum=394
8885 22:55:42.110094 TX Vref=22, minBit 8, minWin=23, winSum=401
8886 22:55:42.113661 TX Vref=24, minBit 8, minWin=24, winSum=410
8887 22:55:42.120818 TX Vref=26, minBit 0, minWin=25, winSum=417
8888 22:55:42.123544 TX Vref=28, minBit 9, minWin=25, winSum=423
8889 22:55:42.126890 TX Vref=30, minBit 0, minWin=25, winSum=417
8890 22:55:42.130712 TX Vref=32, minBit 0, minWin=25, winSum=415
8891 22:55:42.133715 TX Vref=34, minBit 0, minWin=24, winSum=404
8892 22:55:42.136981 TX Vref=36, minBit 9, minWin=23, winSum=396
8893 22:55:42.143718 [TxChooseVref] Worse bit 9, Min win 25, Win sum 423, Final Vref 28
8894 22:55:42.144252
8895 22:55:42.147066 Final TX Range 0 Vref 28
8896 22:55:42.147653
8897 22:55:42.148003 ==
8898 22:55:42.150251 Dram Type= 6, Freq= 0, CH_1, rank 1
8899 22:55:42.153808 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8900 22:55:42.154340 ==
8901 22:55:42.154690
8902 22:55:42.155005
8903 22:55:42.157249 TX Vref Scan disable
8904 22:55:42.163161 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8905 22:55:42.163712 == TX Byte 0 ==
8906 22:55:42.166977 u2DelayCellOfst[0]=17 cells (5 PI)
8907 22:55:42.170508 u2DelayCellOfst[1]=14 cells (4 PI)
8908 22:55:42.173666 u2DelayCellOfst[2]=0 cells (0 PI)
8909 22:55:42.177054 u2DelayCellOfst[3]=7 cells (2 PI)
8910 22:55:42.179959 u2DelayCellOfst[4]=7 cells (2 PI)
8911 22:55:42.183166 u2DelayCellOfst[5]=17 cells (5 PI)
8912 22:55:42.186404 u2DelayCellOfst[6]=17 cells (5 PI)
8913 22:55:42.190114 u2DelayCellOfst[7]=3 cells (1 PI)
8914 22:55:42.193093 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8915 22:55:42.196420 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8916 22:55:42.199871 == TX Byte 1 ==
8917 22:55:42.203303 u2DelayCellOfst[8]=0 cells (0 PI)
8918 22:55:42.203775 u2DelayCellOfst[9]=7 cells (2 PI)
8919 22:55:42.206623 u2DelayCellOfst[10]=10 cells (3 PI)
8920 22:55:42.209695 u2DelayCellOfst[11]=7 cells (2 PI)
8921 22:55:42.213031 u2DelayCellOfst[12]=14 cells (4 PI)
8922 22:55:42.216478 u2DelayCellOfst[13]=14 cells (4 PI)
8923 22:55:42.219697 u2DelayCellOfst[14]=17 cells (5 PI)
8924 22:55:42.223176 u2DelayCellOfst[15]=17 cells (5 PI)
8925 22:55:42.226565 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8926 22:55:42.233142 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8927 22:55:42.233687 DramC Write-DBI on
8928 22:55:42.234034 ==
8929 22:55:42.236508 Dram Type= 6, Freq= 0, CH_1, rank 1
8930 22:55:42.243001 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8931 22:55:42.243474 ==
8932 22:55:42.243823
8933 22:55:42.244142
8934 22:55:42.244446 TX Vref Scan disable
8935 22:55:42.246660 == TX Byte 0 ==
8936 22:55:42.250883 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8937 22:55:42.253854 == TX Byte 1 ==
8938 22:55:42.257206 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8939 22:55:42.260703 DramC Write-DBI off
8940 22:55:42.261243
8941 22:55:42.261589 [DATLAT]
8942 22:55:42.261906 Freq=1600, CH1 RK1
8943 22:55:42.262211
8944 22:55:42.263789 DATLAT Default: 0xf
8945 22:55:42.264218 0, 0xFFFF, sum = 0
8946 22:55:42.266834 1, 0xFFFF, sum = 0
8947 22:55:42.267415 2, 0xFFFF, sum = 0
8948 22:55:42.270321 3, 0xFFFF, sum = 0
8949 22:55:42.274188 4, 0xFFFF, sum = 0
8950 22:55:42.274732 5, 0xFFFF, sum = 0
8951 22:55:42.277304 6, 0xFFFF, sum = 0
8952 22:55:42.277848 7, 0xFFFF, sum = 0
8953 22:55:42.280759 8, 0xFFFF, sum = 0
8954 22:55:42.281303 9, 0xFFFF, sum = 0
8955 22:55:42.283389 10, 0xFFFF, sum = 0
8956 22:55:42.283852 11, 0xFFFF, sum = 0
8957 22:55:42.286835 12, 0xFFFF, sum = 0
8958 22:55:42.287269 13, 0xFFFF, sum = 0
8959 22:55:42.290677 14, 0x0, sum = 1
8960 22:55:42.291222 15, 0x0, sum = 2
8961 22:55:42.294046 16, 0x0, sum = 3
8962 22:55:42.294442 17, 0x0, sum = 4
8963 22:55:42.296786 best_step = 15
8964 22:55:42.297215
8965 22:55:42.297558 ==
8966 22:55:42.300123 Dram Type= 6, Freq= 0, CH_1, rank 1
8967 22:55:42.303231 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8968 22:55:42.303707 ==
8969 22:55:42.306319 RX Vref Scan: 0
8970 22:55:42.306750
8971 22:55:42.307088 RX Vref 0 -> 0, step: 1
8972 22:55:42.307463
8973 22:55:42.309797 RX Delay 11 -> 252, step: 4
8974 22:55:42.313009 iDelay=195, Bit 0, Center 132 (83 ~ 182) 100
8975 22:55:42.320012 iDelay=195, Bit 1, Center 124 (71 ~ 178) 108
8976 22:55:42.323143 iDelay=195, Bit 2, Center 116 (63 ~ 170) 108
8977 22:55:42.327049 iDelay=195, Bit 3, Center 126 (75 ~ 178) 104
8978 22:55:42.329759 iDelay=195, Bit 4, Center 128 (75 ~ 182) 108
8979 22:55:42.332975 iDelay=195, Bit 5, Center 142 (91 ~ 194) 104
8980 22:55:42.340027 iDelay=195, Bit 6, Center 138 (87 ~ 190) 104
8981 22:55:42.343392 iDelay=195, Bit 7, Center 124 (71 ~ 178) 108
8982 22:55:42.346475 iDelay=195, Bit 8, Center 112 (55 ~ 170) 116
8983 22:55:42.349896 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8984 22:55:42.353092 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8985 22:55:42.359923 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8986 22:55:42.363470 iDelay=195, Bit 12, Center 134 (83 ~ 186) 104
8987 22:55:42.366013 iDelay=195, Bit 13, Center 134 (83 ~ 186) 104
8988 22:55:42.369714 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
8989 22:55:42.376021 iDelay=195, Bit 15, Center 136 (83 ~ 190) 108
8990 22:55:42.376453 ==
8991 22:55:42.379801 Dram Type= 6, Freq= 0, CH_1, rank 1
8992 22:55:42.382987 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8993 22:55:42.383612 ==
8994 22:55:42.383985 DQS Delay:
8995 22:55:42.386048 DQS0 = 0, DQS1 = 0
8996 22:55:42.386479 DQM Delay:
8997 22:55:42.389854 DQM0 = 128, DQM1 = 126
8998 22:55:42.390387 DQ Delay:
8999 22:55:42.392708 DQ0 =132, DQ1 =124, DQ2 =116, DQ3 =126
9000 22:55:42.396250 DQ4 =128, DQ5 =142, DQ6 =138, DQ7 =124
9001 22:55:42.399817 DQ8 =112, DQ9 =112, DQ10 =128, DQ11 =120
9002 22:55:42.402811 DQ12 =134, DQ13 =134, DQ14 =136, DQ15 =136
9003 22:55:42.403244
9004 22:55:42.403630
9005 22:55:42.405852
9006 22:55:42.406301 [DramC_TX_OE_Calibration] TA2
9007 22:55:42.408976 Original DQ_B0 (3 6) =30, OEN = 27
9008 22:55:42.413286 Original DQ_B1 (3 6) =30, OEN = 27
9009 22:55:42.415696 24, 0x0, End_B0=24 End_B1=24
9010 22:55:42.419205 25, 0x0, End_B0=25 End_B1=25
9011 22:55:42.422635 26, 0x0, End_B0=26 End_B1=26
9012 22:55:42.423208 27, 0x0, End_B0=27 End_B1=27
9013 22:55:42.425762 28, 0x0, End_B0=28 End_B1=28
9014 22:55:42.429057 29, 0x0, End_B0=29 End_B1=29
9015 22:55:42.432170 30, 0x0, End_B0=30 End_B1=30
9016 22:55:42.435570 31, 0x4545, End_B0=30 End_B1=30
9017 22:55:42.436006 Byte0 end_step=30 best_step=27
9018 22:55:42.439195 Byte1 end_step=30 best_step=27
9019 22:55:42.442241 Byte0 TX OE(2T, 0.5T) = (3, 3)
9020 22:55:42.445860 Byte1 TX OE(2T, 0.5T) = (3, 3)
9021 22:55:42.446426
9022 22:55:42.446772
9023 22:55:42.453116 [DQSOSCAuto] RK1, (LSB)MR18= 0x1218, (MSB)MR19= 0x303, tDQSOscB0 = 397 ps tDQSOscB1 = 400 ps
9024 22:55:42.455410 CH1 RK1: MR19=303, MR18=1218
9025 22:55:42.462649 CH1_RK1: MR19=0x303, MR18=0x1218, DQSOSC=397, MR23=63, INC=23, DEC=15
9026 22:55:42.466056 [RxdqsGatingPostProcess] freq 1600
9027 22:55:42.472812 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9028 22:55:42.475937 best DQS0 dly(2T, 0.5T) = (1, 1)
9029 22:55:42.476493 best DQS1 dly(2T, 0.5T) = (1, 1)
9030 22:55:42.478999 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9031 22:55:42.482173 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9032 22:55:42.485688 best DQS0 dly(2T, 0.5T) = (1, 1)
9033 22:55:42.488595 best DQS1 dly(2T, 0.5T) = (1, 1)
9034 22:55:42.492468 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9035 22:55:42.495791 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9036 22:55:42.499227 Pre-setting of DQS Precalculation
9037 22:55:42.502217 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9038 22:55:42.512499 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9039 22:55:42.519394 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9040 22:55:42.519828
9041 22:55:42.520166
9042 22:55:42.522364 [Calibration Summary] 3200 Mbps
9043 22:55:42.522901 CH 0, Rank 0
9044 22:55:42.525470 SW Impedance : PASS
9045 22:55:42.526008 DUTY Scan : NO K
9046 22:55:42.528620 ZQ Calibration : PASS
9047 22:55:42.532324 Jitter Meter : NO K
9048 22:55:42.532861 CBT Training : PASS
9049 22:55:42.535453 Write leveling : PASS
9050 22:55:42.538946 RX DQS gating : PASS
9051 22:55:42.539522 RX DQ/DQS(RDDQC) : PASS
9052 22:55:42.542205 TX DQ/DQS : PASS
9053 22:55:42.545592 RX DATLAT : PASS
9054 22:55:42.546175 RX DQ/DQS(Engine): PASS
9055 22:55:42.548672 TX OE : PASS
9056 22:55:42.549235 All Pass.
9057 22:55:42.549712
9058 22:55:42.552165 CH 0, Rank 1
9059 22:55:42.552592 SW Impedance : PASS
9060 22:55:42.555565 DUTY Scan : NO K
9061 22:55:42.558516 ZQ Calibration : PASS
9062 22:55:42.558943 Jitter Meter : NO K
9063 22:55:42.561866 CBT Training : PASS
9064 22:55:42.565169 Write leveling : PASS
9065 22:55:42.565761 RX DQS gating : PASS
9066 22:55:42.568573 RX DQ/DQS(RDDQC) : PASS
9067 22:55:42.569251 TX DQ/DQS : PASS
9068 22:55:42.571680 RX DATLAT : PASS
9069 22:55:42.575476 RX DQ/DQS(Engine): PASS
9070 22:55:42.575904 TX OE : PASS
9071 22:55:42.578354 All Pass.
9072 22:55:42.578778
9073 22:55:42.579189 CH 1, Rank 0
9074 22:55:42.581864 SW Impedance : PASS
9075 22:55:42.582294 DUTY Scan : NO K
9076 22:55:42.585672 ZQ Calibration : PASS
9077 22:55:42.588392 Jitter Meter : NO K
9078 22:55:42.588829 CBT Training : PASS
9079 22:55:42.591910 Write leveling : PASS
9080 22:55:42.595260 RX DQS gating : PASS
9081 22:55:42.595723 RX DQ/DQS(RDDQC) : PASS
9082 22:55:42.598929 TX DQ/DQS : PASS
9083 22:55:42.602061 RX DATLAT : PASS
9084 22:55:42.602494 RX DQ/DQS(Engine): PASS
9085 22:55:42.605726 TX OE : PASS
9086 22:55:42.606263 All Pass.
9087 22:55:42.606607
9088 22:55:42.608149 CH 1, Rank 1
9089 22:55:42.608578 SW Impedance : PASS
9090 22:55:42.611701 DUTY Scan : NO K
9091 22:55:42.615121 ZQ Calibration : PASS
9092 22:55:42.615829 Jitter Meter : NO K
9093 22:55:42.618330 CBT Training : PASS
9094 22:55:42.621615 Write leveling : PASS
9095 22:55:42.622082 RX DQS gating : PASS
9096 22:55:42.624884 RX DQ/DQS(RDDQC) : PASS
9097 22:55:42.625312 TX DQ/DQS : PASS
9098 22:55:42.628108 RX DATLAT : PASS
9099 22:55:42.631844 RX DQ/DQS(Engine): PASS
9100 22:55:42.632423 TX OE : PASS
9101 22:55:42.634661 All Pass.
9102 22:55:42.635088
9103 22:55:42.635478 DramC Write-DBI on
9104 22:55:42.638793 PER_BANK_REFRESH: Hybrid Mode
9105 22:55:42.641153 TX_TRACKING: ON
9106 22:55:42.647980 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9107 22:55:42.658782 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9108 22:55:42.665063 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9109 22:55:42.667872 [FAST_K] Save calibration result to emmc
9110 22:55:42.671116 sync common calibartion params.
9111 22:55:42.671684 sync cbt_mode0:1, 1:1
9112 22:55:42.675121 dram_init: ddr_geometry: 2
9113 22:55:42.678568 dram_init: ddr_geometry: 2
9114 22:55:42.681469 dram_init: ddr_geometry: 2
9115 22:55:42.682030 0:dram_rank_size:100000000
9116 22:55:42.684573 1:dram_rank_size:100000000
9117 22:55:42.691824 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9118 22:55:42.692257 DFS_SHUFFLE_HW_MODE: ON
9119 22:55:42.694596 dramc_set_vcore_voltage set vcore to 725000
9120 22:55:42.697920 Read voltage for 1600, 0
9121 22:55:42.698352 Vio18 = 0
9122 22:55:42.701416 Vcore = 725000
9123 22:55:42.701847 Vdram = 0
9124 22:55:42.702189 Vddq = 0
9125 22:55:42.705379 Vmddr = 0
9126 22:55:42.705916 switch to 3200 Mbps bootup
9127 22:55:42.708248 [DramcRunTimeConfig]
9128 22:55:42.708782 PHYPLL
9129 22:55:42.711188 DPM_CONTROL_AFTERK: ON
9130 22:55:42.711658 PER_BANK_REFRESH: ON
9131 22:55:42.714960 REFRESH_OVERHEAD_REDUCTION: ON
9132 22:55:42.718164 CMD_PICG_NEW_MODE: OFF
9133 22:55:42.718630 XRTWTW_NEW_MODE: ON
9134 22:55:42.721335 XRTRTR_NEW_MODE: ON
9135 22:55:42.721869 TX_TRACKING: ON
9136 22:55:42.724426 RDSEL_TRACKING: OFF
9137 22:55:42.728157 DQS Precalculation for DVFS: ON
9138 22:55:42.728688 RX_TRACKING: OFF
9139 22:55:42.731237 HW_GATING DBG: ON
9140 22:55:42.731707 ZQCS_ENABLE_LP4: ON
9141 22:55:42.734562 RX_PICG_NEW_MODE: ON
9142 22:55:42.734987 TX_PICG_NEW_MODE: ON
9143 22:55:42.737571 ENABLE_RX_DCM_DPHY: ON
9144 22:55:42.741701 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9145 22:55:42.744766 DUMMY_READ_FOR_TRACKING: OFF
9146 22:55:42.745201 !!! SPM_CONTROL_AFTERK: OFF
9147 22:55:42.748116 !!! SPM could not control APHY
9148 22:55:42.751422 IMPEDANCE_TRACKING: ON
9149 22:55:42.751855 TEMP_SENSOR: ON
9150 22:55:42.754214 HW_SAVE_FOR_SR: OFF
9151 22:55:42.757432 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9152 22:55:42.760716 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9153 22:55:42.764189 Read ODT Tracking: ON
9154 22:55:42.764715 Refresh Rate DeBounce: ON
9155 22:55:42.767542 DFS_NO_QUEUE_FLUSH: ON
9156 22:55:42.771142 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9157 22:55:42.774828 ENABLE_DFS_RUNTIME_MRW: OFF
9158 22:55:42.775397 DDR_RESERVE_NEW_MODE: ON
9159 22:55:42.778103 MR_CBT_SWITCH_FREQ: ON
9160 22:55:42.781092 =========================
9161 22:55:42.798998 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9162 22:55:42.801746 dram_init: ddr_geometry: 2
9163 22:55:42.820220 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9164 22:55:42.823509 dram_init: dram init end (result: 0)
9165 22:55:42.829745 DRAM-K: Full calibration passed in 24558 msecs
9166 22:55:42.833360 MRC: failed to locate region type 0.
9167 22:55:42.833893 DRAM rank0 size:0x100000000,
9168 22:55:42.837240 DRAM rank1 size=0x100000000
9169 22:55:42.846495 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9170 22:55:42.853085 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9171 22:55:42.859888 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9172 22:55:42.869418 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9173 22:55:42.869940 DRAM rank0 size:0x100000000,
9174 22:55:42.872936 DRAM rank1 size=0x100000000
9175 22:55:42.873457 CBMEM:
9176 22:55:42.876469 IMD: root @ 0xfffff000 254 entries.
9177 22:55:42.879926 IMD: root @ 0xffffec00 62 entries.
9178 22:55:42.882741 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9179 22:55:42.889149 WARNING: RO_VPD is uninitialized or empty.
9180 22:55:42.892539 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9181 22:55:42.899854 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9182 22:55:42.913250 read SPI 0x42894 0xe01e: 6226 us, 9215 KB/s, 73.720 Mbps
9183 22:55:42.924377 BS: romstage times (exec / console): total (unknown) / 24065 ms
9184 22:55:42.924903
9185 22:55:42.925242
9186 22:55:42.934268 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9187 22:55:42.937628 ARM64: Exception handlers installed.
9188 22:55:42.940759 ARM64: Testing exception
9189 22:55:42.944057 ARM64: Done test exception
9190 22:55:42.944482 Enumerating buses...
9191 22:55:42.947570 Show all devs... Before device enumeration.
9192 22:55:42.950959 Root Device: enabled 1
9193 22:55:42.954311 CPU_CLUSTER: 0: enabled 1
9194 22:55:42.954833 CPU: 00: enabled 1
9195 22:55:42.957656 Compare with tree...
9196 22:55:42.958137 Root Device: enabled 1
9197 22:55:42.961109 CPU_CLUSTER: 0: enabled 1
9198 22:55:42.964165 CPU: 00: enabled 1
9199 22:55:42.964592 Root Device scanning...
9200 22:55:42.967473 scan_static_bus for Root Device
9201 22:55:42.970861 CPU_CLUSTER: 0 enabled
9202 22:55:42.974146 scan_static_bus for Root Device done
9203 22:55:42.977512 scan_bus: bus Root Device finished in 8 msecs
9204 22:55:42.977947 done
9205 22:55:42.984548 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9206 22:55:42.987523 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9207 22:55:42.994537 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9208 22:55:42.997495 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9209 22:55:43.001119 Allocating resources...
9210 22:55:43.001601 Reading resources...
9211 22:55:43.007693 Root Device read_resources bus 0 link: 0
9212 22:55:43.008183 DRAM rank0 size:0x100000000,
9213 22:55:43.011166 DRAM rank1 size=0x100000000
9214 22:55:43.014472 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9215 22:55:43.017385 CPU: 00 missing read_resources
9216 22:55:43.020999 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9217 22:55:43.027209 Root Device read_resources bus 0 link: 0 done
9218 22:55:43.027774 Done reading resources.
9219 22:55:43.033792 Show resources in subtree (Root Device)...After reading.
9220 22:55:43.037404 Root Device child on link 0 CPU_CLUSTER: 0
9221 22:55:43.040852 CPU_CLUSTER: 0 child on link 0 CPU: 00
9222 22:55:43.050940 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9223 22:55:43.051414 CPU: 00
9224 22:55:43.054322 Root Device assign_resources, bus 0 link: 0
9225 22:55:43.057036 CPU_CLUSTER: 0 missing set_resources
9226 22:55:43.060735 Root Device assign_resources, bus 0 link: 0 done
9227 22:55:43.064037 Done setting resources.
9228 22:55:43.070530 Show resources in subtree (Root Device)...After assigning values.
9229 22:55:43.073947 Root Device child on link 0 CPU_CLUSTER: 0
9230 22:55:43.077446 CPU_CLUSTER: 0 child on link 0 CPU: 00
9231 22:55:43.086991 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9232 22:55:43.087571 CPU: 00
9233 22:55:43.090078 Done allocating resources.
9234 22:55:43.093805 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9235 22:55:43.097091 Enabling resources...
9236 22:55:43.097599 done.
9237 22:55:43.103865 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9238 22:55:43.104392 Initializing devices...
9239 22:55:43.106512 Root Device init
9240 22:55:43.106933 init hardware done!
9241 22:55:43.110267 0x00000018: ctrlr->caps
9242 22:55:43.113621 52.000 MHz: ctrlr->f_max
9243 22:55:43.114164 0.400 MHz: ctrlr->f_min
9244 22:55:43.116520 0x40ff8080: ctrlr->voltages
9245 22:55:43.116957 sclk: 390625
9246 22:55:43.120222 Bus Width = 1
9247 22:55:43.120645 sclk: 390625
9248 22:55:43.123392 Bus Width = 1
9249 22:55:43.123930 Early init status = 3
9250 22:55:43.130134 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9251 22:55:43.133405 in-header: 03 fc 00 00 01 00 00 00
9252 22:55:43.136545 in-data: 00
9253 22:55:43.139590 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9254 22:55:43.145308 in-header: 03 fd 00 00 00 00 00 00
9255 22:55:43.148163 in-data:
9256 22:55:43.151860 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9257 22:55:43.156025 in-header: 03 fc 00 00 01 00 00 00
9258 22:55:43.159461 in-data: 00
9259 22:55:43.162802 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9260 22:55:43.168175 in-header: 03 fd 00 00 00 00 00 00
9261 22:55:43.171720 in-data:
9262 22:55:43.174737 [SSUSB] Setting up USB HOST controller...
9263 22:55:43.178421 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9264 22:55:43.181757 [SSUSB] phy power-on done.
9265 22:55:43.184487 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9266 22:55:43.191166 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9267 22:55:43.194587 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9268 22:55:43.201154 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9269 22:55:43.208146 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9270 22:55:43.214622 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9271 22:55:43.221627 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9272 22:55:43.228204 read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps
9273 22:55:43.231192 SPM: binary array size = 0x9dc
9274 22:55:43.235025 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9275 22:55:43.241358 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9276 22:55:43.247727 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9277 22:55:43.251086 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9278 22:55:43.257377 configure_display: Starting display init
9279 22:55:43.291496 anx7625_power_on_init: Init interface.
9280 22:55:43.295527 anx7625_disable_pd_protocol: Disabled PD feature.
9281 22:55:43.298387 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9282 22:55:43.326101 anx7625_start_dp_work: Secure OCM version=00
9283 22:55:43.329301 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9284 22:55:43.344199 sp_tx_get_edid_block: EDID Block = 1
9285 22:55:43.446632 Extracted contents:
9286 22:55:43.450386 header: 00 ff ff ff ff ff ff 00
9287 22:55:43.452945 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9288 22:55:43.456946 version: 01 04
9289 22:55:43.460205 basic params: 95 1f 11 78 0a
9290 22:55:43.462979 chroma info: 76 90 94 55 54 90 27 21 50 54
9291 22:55:43.466822 established: 00 00 00
9292 22:55:43.472869 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9293 22:55:43.476215 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9294 22:55:43.482949 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9295 22:55:43.489442 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9296 22:55:43.496130 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9297 22:55:43.500069 extensions: 00
9298 22:55:43.500483 checksum: fb
9299 22:55:43.500950
9300 22:55:43.502952 Manufacturer: IVO Model 57d Serial Number 0
9301 22:55:43.507046 Made week 0 of 2020
9302 22:55:43.507618 EDID version: 1.4
9303 22:55:43.510067 Digital display
9304 22:55:43.513383 6 bits per primary color channel
9305 22:55:43.513902 DisplayPort interface
9306 22:55:43.516588 Maximum image size: 31 cm x 17 cm
9307 22:55:43.519535 Gamma: 220%
9308 22:55:43.519971 Check DPMS levels
9309 22:55:43.523103 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9310 22:55:43.526289 First detailed timing is preferred timing
9311 22:55:43.529835 Established timings supported:
9312 22:55:43.533069 Standard timings supported:
9313 22:55:43.536101 Detailed timings
9314 22:55:43.539395 Hex of detail: 383680a07038204018303c0035ae10000019
9315 22:55:43.543145 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9316 22:55:43.549984 0780 0798 07c8 0820 hborder 0
9317 22:55:43.552767 0438 043b 0447 0458 vborder 0
9318 22:55:43.556281 -hsync -vsync
9319 22:55:43.556791 Did detailed timing
9320 22:55:43.563054 Hex of detail: 000000000000000000000000000000000000
9321 22:55:43.563619 Manufacturer-specified data, tag 0
9322 22:55:43.569278 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9323 22:55:43.573012 ASCII string: InfoVision
9324 22:55:43.576225 Hex of detail: 000000fe00523134304e574635205248200a
9325 22:55:43.579703 ASCII string: R140NWF5 RH
9326 22:55:43.580123 Checksum
9327 22:55:43.582411 Checksum: 0xfb (valid)
9328 22:55:43.585922 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9329 22:55:43.589573 DSI data_rate: 832800000 bps
9330 22:55:43.595830 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9331 22:55:43.599512 anx7625_parse_edid: pixelclock(138800).
9332 22:55:43.603172 hactive(1920), hsync(48), hfp(24), hbp(88)
9333 22:55:43.605974 vactive(1080), vsync(12), vfp(3), vbp(17)
9334 22:55:43.609295 anx7625_dsi_config: config dsi.
9335 22:55:43.616039 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9336 22:55:43.629202 anx7625_dsi_config: success to config DSI
9337 22:55:43.631902 anx7625_dp_start: MIPI phy setup OK.
9338 22:55:43.635593 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9339 22:55:43.638508 mtk_ddp_mode_set invalid vrefresh 60
9340 22:55:43.642032 main_disp_path_setup
9341 22:55:43.642561 ovl_layer_smi_id_en
9342 22:55:43.645065 ovl_layer_smi_id_en
9343 22:55:43.645483 ccorr_config
9344 22:55:43.645810 aal_config
9345 22:55:43.648450 gamma_config
9346 22:55:43.648971 postmask_config
9347 22:55:43.651988 dither_config
9348 22:55:43.655734 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9349 22:55:43.661835 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9350 22:55:43.665172 Root Device init finished in 555 msecs
9351 22:55:43.668578 CPU_CLUSTER: 0 init
9352 22:55:43.675412 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9353 22:55:43.678352 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9354 22:55:43.682171 APU_MBOX 0x190000b0 = 0x10001
9355 22:55:43.685116 APU_MBOX 0x190001b0 = 0x10001
9356 22:55:43.688506 APU_MBOX 0x190005b0 = 0x10001
9357 22:55:43.691664 APU_MBOX 0x190006b0 = 0x10001
9358 22:55:43.695068 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9359 22:55:43.707906 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9360 22:55:43.719740 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9361 22:55:43.726362 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9362 22:55:43.738126 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9363 22:55:43.747669 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9364 22:55:43.751249 CPU_CLUSTER: 0 init finished in 81 msecs
9365 22:55:43.753954 Devices initialized
9366 22:55:43.757618 Show all devs... After init.
9367 22:55:43.758049 Root Device: enabled 1
9368 22:55:43.760966 CPU_CLUSTER: 0: enabled 1
9369 22:55:43.764093 CPU: 00: enabled 1
9370 22:55:43.767283 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9371 22:55:43.770426 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9372 22:55:43.774029 ELOG: NV offset 0x57f000 size 0x1000
9373 22:55:43.780415 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9374 22:55:43.787024 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9375 22:55:43.791021 ELOG: Event(17) added with size 13 at 2023-06-05 22:55:49 UTC
9376 22:55:43.796907 out: cmd=0x121: 03 db 21 01 00 00 00 00
9377 22:55:43.800175 in-header: 03 e4 00 00 2c 00 00 00
9378 22:55:43.813719 in-data: 7b 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9379 22:55:43.817115 ELOG: Event(A1) added with size 10 at 2023-06-05 22:55:49 UTC
9380 22:55:43.823952 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9381 22:55:43.830627 ELOG: Event(A0) added with size 9 at 2023-06-05 22:55:49 UTC
9382 22:55:43.833936 elog_add_boot_reason: Logged dev mode boot
9383 22:55:43.839934 BS: BS_POST_DEVICE entry times (exec / console): 3 / 64 ms
9384 22:55:43.840465 Finalize devices...
9385 22:55:43.843409 Devices finalized
9386 22:55:43.846933 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9387 22:55:43.850123 Writing coreboot table at 0xffe64000
9388 22:55:43.856867 0. 000000000010a000-0000000000113fff: RAMSTAGE
9389 22:55:43.860103 1. 0000000040000000-00000000400fffff: RAM
9390 22:55:43.863694 2. 0000000040100000-000000004032afff: RAMSTAGE
9391 22:55:43.866565 3. 000000004032b000-00000000545fffff: RAM
9392 22:55:43.870082 4. 0000000054600000-000000005465ffff: BL31
9393 22:55:43.876734 5. 0000000054660000-00000000ffe63fff: RAM
9394 22:55:43.879604 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9395 22:55:43.883180 7. 0000000100000000-000000023fffffff: RAM
9396 22:55:43.887338 Passing 5 GPIOs to payload:
9397 22:55:43.889783 NAME | PORT | POLARITY | VALUE
9398 22:55:43.896274 EC in RW | 0x000000aa | low | undefined
9399 22:55:43.899583 EC interrupt | 0x00000005 | low | undefined
9400 22:55:43.906338 TPM interrupt | 0x000000ab | high | undefined
9401 22:55:43.909269 SD card detect | 0x00000011 | high | undefined
9402 22:55:43.912925 speaker enable | 0x00000093 | high | undefined
9403 22:55:43.919664 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9404 22:55:43.923162 in-header: 03 f9 00 00 02 00 00 00
9405 22:55:43.923714 in-data: 02 00
9406 22:55:43.926598 ADC[4]: Raw value=900959 ID=7
9407 22:55:43.929599 ADC[3]: Raw value=212967 ID=1
9408 22:55:43.930120 RAM Code: 0x71
9409 22:55:43.932921 ADC[6]: Raw value=74557 ID=0
9410 22:55:43.936198 ADC[5]: Raw value=211860 ID=1
9411 22:55:43.936723 SKU Code: 0x1
9412 22:55:43.943928 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum ded1
9413 22:55:43.945844 coreboot table: 964 bytes.
9414 22:55:43.949739 IMD ROOT 0. 0xfffff000 0x00001000
9415 22:55:43.952699 IMD SMALL 1. 0xffffe000 0x00001000
9416 22:55:43.956216 RO MCACHE 2. 0xffffc000 0x00001104
9417 22:55:43.956754 CONSOLE 3. 0xfff7c000 0x00080000
9418 22:55:43.959480 FMAP 4. 0xfff7b000 0x00000452
9419 22:55:43.963093 TIME STAMP 5. 0xfff7a000 0x00000910
9420 22:55:43.966035 VBOOT WORK 6. 0xfff66000 0x00014000
9421 22:55:43.969317 RAMOOPS 7. 0xffe66000 0x00100000
9422 22:55:43.972582 COREBOOT 8. 0xffe64000 0x00002000
9423 22:55:43.976146 IMD small region:
9424 22:55:43.979089 IMD ROOT 0. 0xffffec00 0x00000400
9425 22:55:43.982348 VPD 1. 0xffffeba0 0x0000004c
9426 22:55:43.986497 MMC STATUS 2. 0xffffeb80 0x00000004
9427 22:55:43.992235 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9428 22:55:43.992750 Probing TPM: done!
9429 22:55:43.999386 Connected to device vid:did:rid of 1ae0:0028:00
9430 22:55:44.006221 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9431 22:55:44.009504 Initialized TPM device CR50 revision 0
9432 22:55:44.012889 Checking cr50 for pending updates
9433 22:55:44.018569 Reading cr50 TPM mode
9434 22:55:44.027507 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9435 22:55:44.033956 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9436 22:55:44.073790 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9437 22:55:44.077351 Checking segment from ROM address 0x40100000
9438 22:55:44.080209 Checking segment from ROM address 0x4010001c
9439 22:55:44.087184 Loading segment from ROM address 0x40100000
9440 22:55:44.087751 code (compression=0)
9441 22:55:44.096595 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9442 22:55:44.103494 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9443 22:55:44.103917 it's not compressed!
9444 22:55:44.110132 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9445 22:55:44.113253 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9446 22:55:44.134147 Loading segment from ROM address 0x4010001c
9447 22:55:44.134661 Entry Point 0x80000000
9448 22:55:44.137586 Loaded segments
9449 22:55:44.140491 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9450 22:55:44.147476 Jumping to boot code at 0x80000000(0xffe64000)
9451 22:55:44.154343 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9452 22:55:44.160705 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9453 22:55:44.168469 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9454 22:55:44.171731 Checking segment from ROM address 0x40100000
9455 22:55:44.175516 Checking segment from ROM address 0x4010001c
9456 22:55:44.181694 Loading segment from ROM address 0x40100000
9457 22:55:44.182232 code (compression=1)
9458 22:55:44.188540 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9459 22:55:44.198252 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9460 22:55:44.198764 using LZMA
9461 22:55:44.207185 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9462 22:55:44.213427 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9463 22:55:44.216846 Loading segment from ROM address 0x4010001c
9464 22:55:44.217373 Entry Point 0x54601000
9465 22:55:44.219854 Loaded segments
9466 22:55:44.223657 NOTICE: MT8192 bl31_setup
9467 22:55:44.230329 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9468 22:55:44.233582 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9469 22:55:44.237675 WARNING: region 0:
9470 22:55:44.240488 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9471 22:55:44.241013 WARNING: region 1:
9472 22:55:44.247489 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9473 22:55:44.250425 WARNING: region 2:
9474 22:55:44.254090 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9475 22:55:44.257156 WARNING: region 3:
9476 22:55:44.260303 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9477 22:55:44.263712 WARNING: region 4:
9478 22:55:44.270456 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9479 22:55:44.270984 WARNING: region 5:
9480 22:55:44.273748 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9481 22:55:44.277445 WARNING: region 6:
9482 22:55:44.280699 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9483 22:55:44.284044 WARNING: region 7:
9484 22:55:44.287138 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9485 22:55:44.293452 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9486 22:55:44.296973 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9487 22:55:44.300068 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9488 22:55:44.306761 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9489 22:55:44.310631 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9490 22:55:44.314130 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9491 22:55:44.320800 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9492 22:55:44.323620 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9493 22:55:44.330562 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9494 22:55:44.333726 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9495 22:55:44.337740 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9496 22:55:44.344322 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9497 22:55:44.347436 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9498 22:55:44.350276 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9499 22:55:44.357020 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9500 22:55:44.360490 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9501 22:55:44.363996 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9502 22:55:44.370700 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9503 22:55:44.374376 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9504 22:55:44.380951 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9505 22:55:44.383714 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9506 22:55:44.387467 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9507 22:55:44.393728 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9508 22:55:44.397303 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9509 22:55:44.403576 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9510 22:55:44.407484 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9511 22:55:44.410274 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9512 22:55:44.417052 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9513 22:55:44.420099 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9514 22:55:44.423918 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9515 22:55:44.430891 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9516 22:55:44.433403 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9517 22:55:44.440514 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9518 22:55:44.443691 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9519 22:55:44.447304 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9520 22:55:44.450846 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9521 22:55:44.454037 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9522 22:55:44.460557 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9523 22:55:44.464148 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9524 22:55:44.467903 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9525 22:55:44.470801 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9526 22:55:44.477320 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9527 22:55:44.480740 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9528 22:55:44.484154 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9529 22:55:44.490316 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9530 22:55:44.494037 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9531 22:55:44.497179 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9532 22:55:44.500475 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9533 22:55:44.507336 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9534 22:55:44.510265 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9535 22:55:44.517322 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9536 22:55:44.520178 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9537 22:55:44.523460 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9538 22:55:44.530480 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9539 22:55:44.533737 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9540 22:55:44.540174 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9541 22:55:44.543884 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9542 22:55:44.547256 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9543 22:55:44.553332 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9544 22:55:44.556802 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9545 22:55:44.563624 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9546 22:55:44.567097 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9547 22:55:44.573694 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9548 22:55:44.577207 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9549 22:55:44.583207 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9550 22:55:44.586974 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9551 22:55:44.590216 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9552 22:55:44.596775 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9553 22:55:44.600403 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9554 22:55:44.606737 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9555 22:55:44.610074 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9556 22:55:44.617108 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9557 22:55:44.619831 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9558 22:55:44.623633 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9559 22:55:44.630315 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9560 22:55:44.633299 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9561 22:55:44.640326 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9562 22:55:44.643618 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9563 22:55:44.650244 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9564 22:55:44.653692 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9565 22:55:44.659829 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9566 22:55:44.663207 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9567 22:55:44.666216 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9568 22:55:44.673006 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9569 22:55:44.676635 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9570 22:55:44.682959 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9571 22:55:44.686171 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9572 22:55:44.692811 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9573 22:55:44.696238 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9574 22:55:44.699795 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9575 22:55:44.707105 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9576 22:55:44.709616 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9577 22:55:44.716488 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9578 22:55:44.720395 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9579 22:55:44.726835 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9580 22:55:44.730007 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9581 22:55:44.733287 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9582 22:55:44.736816 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9583 22:55:44.743087 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9584 22:55:44.746842 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9585 22:55:44.749498 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9586 22:55:44.756208 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9587 22:55:44.759856 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9588 22:55:44.766312 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9589 22:55:44.769571 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9590 22:55:44.772910 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9591 22:55:44.779560 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9592 22:55:44.783249 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9593 22:55:44.789376 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9594 22:55:44.792734 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9595 22:55:44.796209 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9596 22:55:44.802914 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9597 22:55:44.806211 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9598 22:55:44.813016 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9599 22:55:44.816196 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9600 22:55:44.819267 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9601 22:55:44.823174 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9602 22:55:44.829799 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9603 22:55:44.832942 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9604 22:55:44.836012 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9605 22:55:44.843027 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9606 22:55:44.846327 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9607 22:55:44.849870 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9608 22:55:44.853171 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9609 22:55:44.859320 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9610 22:55:44.862757 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9611 22:55:44.869620 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9612 22:55:44.872648 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9613 22:55:44.876200 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9614 22:55:44.882659 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9615 22:55:44.886172 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9616 22:55:44.889552 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9617 22:55:44.895951 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9618 22:55:44.899639 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9619 22:55:44.905981 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9620 22:55:44.909541 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9621 22:55:44.912834 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9622 22:55:44.919775 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9623 22:55:44.923122 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9624 22:55:44.926803 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9625 22:55:44.932970 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9626 22:55:44.936847 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9627 22:55:44.942954 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9628 22:55:44.946357 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9629 22:55:44.949738 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9630 22:55:44.956597 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9631 22:55:44.959920 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9632 22:55:44.963613 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9633 22:55:44.970201 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9634 22:55:44.973532 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9635 22:55:44.979799 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9636 22:55:44.983451 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9637 22:55:44.987272 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9638 22:55:44.993263 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9639 22:55:44.996550 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9640 22:55:45.003696 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9641 22:55:45.006545 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9642 22:55:45.010460 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9643 22:55:45.017161 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9644 22:55:45.020382 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9645 22:55:45.023160 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9646 22:55:45.029843 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9647 22:55:45.033177 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9648 22:55:45.039890 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9649 22:55:45.043268 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9650 22:55:45.046512 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9651 22:55:45.053193 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9652 22:55:45.056852 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9653 22:55:45.063262 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9654 22:55:45.066538 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9655 22:55:45.069974 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9656 22:55:45.076411 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9657 22:55:45.079879 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9658 22:55:45.087134 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9659 22:55:45.089518 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9660 22:55:45.092996 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9661 22:55:45.100444 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9662 22:55:45.103186 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9663 22:55:45.109930 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9664 22:55:45.113002 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9665 22:55:45.116290 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9666 22:55:45.123208 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9667 22:55:45.126292 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9668 22:55:45.129524 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9669 22:55:45.136535 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9670 22:55:45.139747 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9671 22:55:45.146241 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9672 22:55:45.149626 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9673 22:55:45.153089 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9674 22:55:45.159517 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9675 22:55:45.162821 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9676 22:55:45.169611 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9677 22:55:45.173427 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9678 22:55:45.176898 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9679 22:55:45.182757 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9680 22:55:45.186125 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9681 22:55:45.192532 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9682 22:55:45.196016 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9683 22:55:45.202958 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9684 22:55:45.206585 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9685 22:55:45.209357 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9686 22:55:45.216187 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9687 22:55:45.219156 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9688 22:55:45.225950 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9689 22:55:45.229013 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9690 22:55:45.236064 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9691 22:55:45.239022 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9692 22:55:45.242360 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9693 22:55:45.248693 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9694 22:55:45.252063 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9695 22:55:45.259224 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9696 22:55:45.262380 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9697 22:55:45.269134 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9698 22:55:45.272398 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9699 22:55:45.275744 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9700 22:55:45.282169 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9701 22:55:45.285610 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9702 22:55:45.292172 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9703 22:55:45.295515 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9704 22:55:45.299209 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9705 22:55:45.305331 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9706 22:55:45.308791 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9707 22:55:45.315361 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9708 22:55:45.318679 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9709 22:55:45.322193 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9710 22:55:45.328473 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9711 22:55:45.332178 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9712 22:55:45.338562 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9713 22:55:45.341778 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9714 22:55:45.345687 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9715 22:55:45.348635 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9716 22:55:45.355599 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9717 22:55:45.358666 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9718 22:55:45.362190 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9719 22:55:45.368700 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9720 22:55:45.372082 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9721 22:55:45.375283 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9722 22:55:45.382046 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9723 22:55:45.385461 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9724 22:55:45.388788 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9725 22:55:45.395231 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9726 22:55:45.398697 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9727 22:55:45.405216 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9728 22:55:45.408516 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9729 22:55:45.411823 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9730 22:55:45.418868 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9731 22:55:45.422021 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9732 22:55:45.425286 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9733 22:55:45.432057 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9734 22:55:45.435453 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9735 22:55:45.438775 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9736 22:55:45.445359 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9737 22:55:45.448752 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9738 22:55:45.452037 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9739 22:55:45.458473 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9740 22:55:45.461644 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9741 22:55:45.468342 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9742 22:55:45.471906 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9743 22:55:45.474813 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9744 22:55:45.481675 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9745 22:55:45.485009 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9746 22:55:45.488091 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9747 22:55:45.495103 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9748 22:55:45.498353 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9749 22:55:45.501707 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9750 22:55:45.508478 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9751 22:55:45.511765 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9752 22:55:45.518390 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9753 22:55:45.521747 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9754 22:55:45.525512 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9755 22:55:45.528098 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9756 22:55:45.535198 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9757 22:55:45.538290 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9758 22:55:45.541728 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9759 22:55:45.545069 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9760 22:55:45.551797 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9761 22:55:45.555163 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9762 22:55:45.558514 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9763 22:55:45.561662 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9764 22:55:45.568132 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9765 22:55:45.571668 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9766 22:55:45.574996 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9767 22:55:45.581317 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9768 22:55:45.585090 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9769 22:55:45.587978 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9770 22:55:45.594611 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9771 22:55:45.598379 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9772 22:55:45.604791 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9773 22:55:45.607882 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9774 22:55:45.611397 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9775 22:55:45.617872 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9776 22:55:45.621340 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9777 22:55:45.627758 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9778 22:55:45.631085 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9779 22:55:45.637957 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9780 22:55:45.641298 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9781 22:55:45.644706 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9782 22:55:45.651244 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9783 22:55:45.655346 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9784 22:55:45.658086 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9785 22:55:45.664651 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9786 22:55:45.667750 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9787 22:55:45.674651 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9788 22:55:45.678259 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9789 22:55:45.684506 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9790 22:55:45.688029 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9791 22:55:45.691271 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9792 22:55:45.698087 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9793 22:55:45.701054 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9794 22:55:45.708190 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9795 22:55:45.711908 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9796 22:55:45.715003 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9797 22:55:45.721515 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9798 22:55:45.724575 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9799 22:55:45.731477 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9800 22:55:45.734860 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9801 22:55:45.738580 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9802 22:55:45.744977 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9803 22:55:45.748198 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9804 22:55:45.755101 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9805 22:55:45.758591 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9806 22:55:45.761577 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9807 22:55:45.768668 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9808 22:55:45.772045 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9809 22:55:45.778444 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9810 22:55:45.781827 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9811 22:55:45.784554 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9812 22:55:45.791504 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9813 22:55:45.794433 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9814 22:55:45.801620 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9815 22:55:45.805168 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9816 22:55:45.808174 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9817 22:55:45.814751 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9818 22:55:45.818260 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9819 22:55:45.824629 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9820 22:55:45.827701 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9821 22:55:45.834798 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9822 22:55:45.837908 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9823 22:55:45.841409 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9824 22:55:45.847421 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9825 22:55:45.851244 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9826 22:55:45.858106 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9827 22:55:45.860939 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9828 22:55:45.864015 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9829 22:55:45.870909 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9830 22:55:45.873843 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9831 22:55:45.881449 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9832 22:55:45.884200 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9833 22:55:45.887476 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9834 22:55:45.894056 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9835 22:55:45.897251 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9836 22:55:45.904093 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9837 22:55:45.907075 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9838 22:55:45.911030 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9839 22:55:45.917718 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9840 22:55:45.921025 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9841 22:55:45.927126 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9842 22:55:45.930897 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9843 22:55:45.937607 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9844 22:55:45.940839 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9845 22:55:45.947129 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9846 22:55:45.950693 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9847 22:55:45.954393 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9848 22:55:45.960409 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9849 22:55:45.963556 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9850 22:55:45.970480 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9851 22:55:45.973966 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9852 22:55:45.980391 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9853 22:55:45.983818 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9854 22:55:45.987060 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9855 22:55:45.993478 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9856 22:55:45.996753 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9857 22:55:46.003280 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9858 22:55:46.006590 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9859 22:55:46.013298 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9860 22:55:46.016914 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9861 22:55:46.023774 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9862 22:55:46.026658 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9863 22:55:46.030029 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9864 22:55:46.037030 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9865 22:55:46.040024 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9866 22:55:46.047247 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9867 22:55:46.050485 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9868 22:55:46.056987 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9869 22:55:46.060415 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9870 22:55:46.063936 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9871 22:55:46.070097 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9872 22:55:46.073963 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9873 22:55:46.079981 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9874 22:55:46.083289 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9875 22:55:46.090221 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9876 22:55:46.093169 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9877 22:55:46.096856 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9878 22:55:46.103097 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9879 22:55:46.106552 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9880 22:55:46.113842 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9881 22:55:46.117370 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9882 22:55:46.123719 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9883 22:55:46.126546 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9884 22:55:46.130235 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9885 22:55:46.136623 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9886 22:55:46.139815 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9887 22:55:46.146783 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9888 22:55:46.149953 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9889 22:55:46.153321 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9890 22:55:46.159703 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9891 22:55:46.163216 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9892 22:55:46.170080 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9893 22:55:46.173292 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9894 22:55:46.180772 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9895 22:55:46.183417 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9896 22:55:46.190078 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9897 22:55:46.193366 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9898 22:55:46.199769 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9899 22:55:46.202821 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9900 22:55:46.210298 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9901 22:55:46.212696 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9902 22:55:46.219876 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9903 22:55:46.223560 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9904 22:55:46.229719 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9905 22:55:46.233252 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9906 22:55:46.239749 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9907 22:55:46.243424 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9908 22:55:46.249399 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9909 22:55:46.253121 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9910 22:55:46.259970 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9911 22:55:46.262924 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9912 22:55:46.269890 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9913 22:55:46.272826 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9914 22:55:46.279621 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9915 22:55:46.282833 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9916 22:55:46.289538 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9917 22:55:46.293031 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9918 22:55:46.299135 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9919 22:55:46.303301 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9920 22:55:46.303771 INFO: [APUAPC] vio 0
9921 22:55:46.310363 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9922 22:55:46.313616 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9923 22:55:46.317263 INFO: [APUAPC] D0_APC_0: 0x400510
9924 22:55:46.320401 INFO: [APUAPC] D0_APC_1: 0x0
9925 22:55:46.323534 INFO: [APUAPC] D0_APC_2: 0x1540
9926 22:55:46.327053 INFO: [APUAPC] D0_APC_3: 0x0
9927 22:55:46.330866 INFO: [APUAPC] D1_APC_0: 0xffffffff
9928 22:55:46.334043 INFO: [APUAPC] D1_APC_1: 0xffffffff
9929 22:55:46.337835 INFO: [APUAPC] D1_APC_2: 0x3fffff
9930 22:55:46.340471 INFO: [APUAPC] D1_APC_3: 0x0
9931 22:55:46.342981 INFO: [APUAPC] D2_APC_0: 0xffffffff
9932 22:55:46.346326 INFO: [APUAPC] D2_APC_1: 0xffffffff
9933 22:55:46.349842 INFO: [APUAPC] D2_APC_2: 0x3fffff
9934 22:55:46.353158 INFO: [APUAPC] D2_APC_3: 0x0
9935 22:55:46.356739 INFO: [APUAPC] D3_APC_0: 0xffffffff
9936 22:55:46.360551 INFO: [APUAPC] D3_APC_1: 0xffffffff
9937 22:55:46.363198 INFO: [APUAPC] D3_APC_2: 0x3fffff
9938 22:55:46.366653 INFO: [APUAPC] D3_APC_3: 0x0
9939 22:55:46.370267 INFO: [APUAPC] D4_APC_0: 0xffffffff
9940 22:55:46.373425 INFO: [APUAPC] D4_APC_1: 0xffffffff
9941 22:55:46.376786 INFO: [APUAPC] D4_APC_2: 0x3fffff
9942 22:55:46.377312 INFO: [APUAPC] D4_APC_3: 0x0
9943 22:55:46.379939 INFO: [APUAPC] D5_APC_0: 0xffffffff
9944 22:55:46.386537 INFO: [APUAPC] D5_APC_1: 0xffffffff
9945 22:55:46.389731 INFO: [APUAPC] D5_APC_2: 0x3fffff
9946 22:55:46.390169 INFO: [APUAPC] D5_APC_3: 0x0
9947 22:55:46.393431 INFO: [APUAPC] D6_APC_0: 0xffffffff
9948 22:55:46.396726 INFO: [APUAPC] D6_APC_1: 0xffffffff
9949 22:55:46.400185 INFO: [APUAPC] D6_APC_2: 0x3fffff
9950 22:55:46.402811 INFO: [APUAPC] D6_APC_3: 0x0
9951 22:55:46.406683 INFO: [APUAPC] D7_APC_0: 0xffffffff
9952 22:55:46.409991 INFO: [APUAPC] D7_APC_1: 0xffffffff
9953 22:55:46.413067 INFO: [APUAPC] D7_APC_2: 0x3fffff
9954 22:55:46.416471 INFO: [APUAPC] D7_APC_3: 0x0
9955 22:55:46.419902 INFO: [APUAPC] D8_APC_0: 0xffffffff
9956 22:55:46.423203 INFO: [APUAPC] D8_APC_1: 0xffffffff
9957 22:55:46.426412 INFO: [APUAPC] D8_APC_2: 0x3fffff
9958 22:55:46.430153 INFO: [APUAPC] D8_APC_3: 0x0
9959 22:55:46.433392 INFO: [APUAPC] D9_APC_0: 0xffffffff
9960 22:55:46.436323 INFO: [APUAPC] D9_APC_1: 0xffffffff
9961 22:55:46.440192 INFO: [APUAPC] D9_APC_2: 0x3fffff
9962 22:55:46.443404 INFO: [APUAPC] D9_APC_3: 0x0
9963 22:55:46.446320 INFO: [APUAPC] D10_APC_0: 0xffffffff
9964 22:55:46.449747 INFO: [APUAPC] D10_APC_1: 0xffffffff
9965 22:55:46.452748 INFO: [APUAPC] D10_APC_2: 0x3fffff
9966 22:55:46.456139 INFO: [APUAPC] D10_APC_3: 0x0
9967 22:55:46.459502 INFO: [APUAPC] D11_APC_0: 0xffffffff
9968 22:55:46.462645 INFO: [APUAPC] D11_APC_1: 0xffffffff
9969 22:55:46.466363 INFO: [APUAPC] D11_APC_2: 0x3fffff
9970 22:55:46.469705 INFO: [APUAPC] D11_APC_3: 0x0
9971 22:55:46.472864 INFO: [APUAPC] D12_APC_0: 0xffffffff
9972 22:55:46.476335 INFO: [APUAPC] D12_APC_1: 0xffffffff
9973 22:55:46.479254 INFO: [APUAPC] D12_APC_2: 0x3fffff
9974 22:55:46.482677 INFO: [APUAPC] D12_APC_3: 0x0
9975 22:55:46.485657 INFO: [APUAPC] D13_APC_0: 0xffffffff
9976 22:55:46.489157 INFO: [APUAPC] D13_APC_1: 0xffffffff
9977 22:55:46.492468 INFO: [APUAPC] D13_APC_2: 0x3fffff
9978 22:55:46.495623 INFO: [APUAPC] D13_APC_3: 0x0
9979 22:55:46.498813 INFO: [APUAPC] D14_APC_0: 0xffffffff
9980 22:55:46.502399 INFO: [APUAPC] D14_APC_1: 0xffffffff
9981 22:55:46.505991 INFO: [APUAPC] D14_APC_2: 0x3fffff
9982 22:55:46.509150 INFO: [APUAPC] D14_APC_3: 0x0
9983 22:55:46.512639 INFO: [APUAPC] D15_APC_0: 0xffffffff
9984 22:55:46.515746 INFO: [APUAPC] D15_APC_1: 0xffffffff
9985 22:55:46.518967 INFO: [APUAPC] D15_APC_2: 0x3fffff
9986 22:55:46.522545 INFO: [APUAPC] D15_APC_3: 0x0
9987 22:55:46.525438 INFO: [APUAPC] APC_CON: 0x4
9988 22:55:46.529403 INFO: [NOCDAPC] D0_APC_0: 0x0
9989 22:55:46.532488 INFO: [NOCDAPC] D0_APC_1: 0x0
9990 22:55:46.535739 INFO: [NOCDAPC] D1_APC_0: 0x0
9991 22:55:46.539421 INFO: [NOCDAPC] D1_APC_1: 0xfff
9992 22:55:46.542256 INFO: [NOCDAPC] D2_APC_0: 0x0
9993 22:55:46.542782 INFO: [NOCDAPC] D2_APC_1: 0xfff
9994 22:55:46.545822 INFO: [NOCDAPC] D3_APC_0: 0x0
9995 22:55:46.549117 INFO: [NOCDAPC] D3_APC_1: 0xfff
9996 22:55:46.552243 INFO: [NOCDAPC] D4_APC_0: 0x0
9997 22:55:46.555799 INFO: [NOCDAPC] D4_APC_1: 0xfff
9998 22:55:46.559494 INFO: [NOCDAPC] D5_APC_0: 0x0
9999 22:55:46.562301 INFO: [NOCDAPC] D5_APC_1: 0xfff
10000 22:55:46.566254 INFO: [NOCDAPC] D6_APC_0: 0x0
10001 22:55:46.569222 INFO: [NOCDAPC] D6_APC_1: 0xfff
10002 22:55:46.572214 INFO: [NOCDAPC] D7_APC_0: 0x0
10003 22:55:46.576268 INFO: [NOCDAPC] D7_APC_1: 0xfff
10004 22:55:46.576793 INFO: [NOCDAPC] D8_APC_0: 0x0
10005 22:55:46.579309 INFO: [NOCDAPC] D8_APC_1: 0xfff
10006 22:55:46.582586 INFO: [NOCDAPC] D9_APC_0: 0x0
10007 22:55:46.585881 INFO: [NOCDAPC] D9_APC_1: 0xfff
10008 22:55:46.589546 INFO: [NOCDAPC] D10_APC_0: 0x0
10009 22:55:46.592056 INFO: [NOCDAPC] D10_APC_1: 0xfff
10010 22:55:46.595246 INFO: [NOCDAPC] D11_APC_0: 0x0
10011 22:55:46.598827 INFO: [NOCDAPC] D11_APC_1: 0xfff
10012 22:55:46.601971 INFO: [NOCDAPC] D12_APC_0: 0x0
10013 22:55:46.605340 INFO: [NOCDAPC] D12_APC_1: 0xfff
10014 22:55:46.608842 INFO: [NOCDAPC] D13_APC_0: 0x0
10015 22:55:46.612077 INFO: [NOCDAPC] D13_APC_1: 0xfff
10016 22:55:46.615403 INFO: [NOCDAPC] D14_APC_0: 0x0
10017 22:55:46.618676 INFO: [NOCDAPC] D14_APC_1: 0xfff
10018 22:55:46.619189 INFO: [NOCDAPC] D15_APC_0: 0x0
10019 22:55:46.621925 INFO: [NOCDAPC] D15_APC_1: 0xfff
10020 22:55:46.625190 INFO: [NOCDAPC] APC_CON: 0x4
10021 22:55:46.628481 INFO: [APUAPC] set_apusys_apc done
10022 22:55:46.631699 INFO: [DEVAPC] devapc_init done
10023 22:55:46.635512 INFO: GICv3 without legacy support detected.
10024 22:55:46.642083 INFO: ARM GICv3 driver initialized in EL3
10025 22:55:46.645603 INFO: Maximum SPI INTID supported: 639
10026 22:55:46.648908 INFO: BL31: Initializing runtime services
10027 22:55:46.655385 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10028 22:55:46.659025 INFO: SPM: enable CPC mode
10029 22:55:46.661901 INFO: mcdi ready for mcusys-off-idle and system suspend
10030 22:55:46.668387 INFO: BL31: Preparing for EL3 exit to normal world
10031 22:55:46.671728 INFO: Entry point address = 0x80000000
10032 22:55:46.672251 INFO: SPSR = 0x8
10033 22:55:46.678737
10034 22:55:46.679262
10035 22:55:46.679660
10036 22:55:46.681454 Starting depthcharge on Spherion...
10037 22:55:46.681875
10038 22:55:46.682206 Wipe memory regions:
10039 22:55:46.682515
10040 22:55:46.684861 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10041 22:55:46.685358 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10042 22:55:46.685760 Setting prompt string to ['asurada:']
10043 22:55:46.686134 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10044 22:55:46.686785 [0x00000040000000, 0x00000054600000)
10045 22:55:46.807625
10046 22:55:46.808151 [0x00000054660000, 0x00000080000000)
10047 22:55:47.068746
10048 22:55:47.069275 [0x000000821a7280, 0x000000ffe64000)
10049 22:55:47.812948
10050 22:55:47.813474 [0x00000100000000, 0x00000240000000)
10051 22:55:49.703245
10052 22:55:49.706258 Initializing XHCI USB controller at 0x11200000.
10053 22:55:50.744267
10054 22:55:50.748225 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10055 22:55:50.748762
10056 22:55:50.749106
10057 22:55:50.749426
10058 22:55:50.750165 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10060 22:55:50.851577 asurada: tftpboot 192.168.201.1 10597662/tftp-deploy-29_5pyne/kernel/image.itb 10597662/tftp-deploy-29_5pyne/kernel/cmdline
10061 22:55:50.852205 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10062 22:55:50.852658 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10063 22:55:50.856734 tftpboot 192.168.201.1 10597662/tftp-deploy-29_5pyne/kernel/image.ittp-deploy-29_5pyne/kernel/cmdline
10064 22:55:50.856906
10065 22:55:50.856986 Waiting for link
10066 22:55:51.017826
10067 22:55:51.018358 R8152: Initializing
10068 22:55:51.018722
10069 22:55:51.021400 Version 6 (ocp_data = 5c30)
10070 22:55:51.021936
10071 22:55:51.024333 R8152: Done initializing
10072 22:55:51.024794
10073 22:55:51.025339 Adding net device
10074 22:55:52.891635
10075 22:55:52.892161 done.
10076 22:55:52.892503
10077 22:55:52.892821 MAC: 00:24:32:30:78:52
10078 22:55:52.893130
10079 22:55:52.895211 Sending DHCP discover... done.
10080 22:55:52.895777
10081 22:56:01.341806 Waiting for reply... done.
10082 22:56:01.342344
10083 22:56:01.342695 Sending DHCP request... done.
10084 22:56:01.344981
10085 22:56:01.348006 Waiting for reply... done.
10086 22:56:01.348437
10087 22:56:01.348777 My ip is 192.168.201.14
10088 22:56:01.349096
10089 22:56:01.351461 The DHCP server ip is 192.168.201.1
10090 22:56:01.351895
10091 22:56:01.354707 TFTP server IP predefined by user: 192.168.201.1
10092 22:56:01.358126
10093 22:56:01.361635 Bootfile predefined by user: 10597662/tftp-deploy-29_5pyne/kernel/image.itb
10094 22:56:01.365015
10095 22:56:01.365683 Sending tftp read request... done.
10096 22:56:01.366349
10097 22:56:01.373442 Waiting for the transfer...
10098 22:56:01.373931
10099 22:56:02.083943 00000000 ################################################################
10100 22:56:02.084455
10101 22:56:02.827483 00080000 ################################################################
10102 22:56:02.828041
10103 22:56:03.575602 00100000 ################################################################
10104 22:56:03.576150
10105 22:56:04.300300 00180000 ################################################################
10106 22:56:04.300855
10107 22:56:05.058092 00200000 ################################################################
10108 22:56:05.058711
10109 22:56:05.813178 00280000 ################################################################
10110 22:56:05.813709
10111 22:56:06.502169 00300000 ################################################################
10112 22:56:06.502356
10113 22:56:07.248487 00380000 ################################################################
10114 22:56:07.249037
10115 22:56:07.926012 00400000 ################################################################
10116 22:56:07.926177
10117 22:56:08.646338 00480000 ################################################################
10118 22:56:08.646919
10119 22:56:09.376742 00500000 ################################################################
10120 22:56:09.376898
10121 22:56:10.078138 00580000 ################################################################
10122 22:56:10.078659
10123 22:56:10.804362 00600000 ################################################################
10124 22:56:10.805032
10125 22:56:11.527414 00680000 ################################################################
10126 22:56:11.527971
10127 22:56:12.248969 00700000 ################################################################
10128 22:56:12.249491
10129 22:56:12.982204 00780000 ################################################################
10130 22:56:12.982727
10131 22:56:13.689104 00800000 ################################################################
10132 22:56:13.689611
10133 22:56:14.421287 00880000 ################################################################
10134 22:56:14.421824
10135 22:56:15.135631 00900000 ################################################################
10136 22:56:15.136176
10137 22:56:15.724765 00980000 ################################################################
10138 22:56:15.724918
10139 22:56:16.297105 00a00000 ################################################################
10140 22:56:16.297254
10141 22:56:16.971974 00a80000 ################################################################
10142 22:56:16.972493
10143 22:56:17.685785 00b00000 ################################################################
10144 22:56:17.685975
10145 22:56:18.386433 00b80000 ################################################################
10146 22:56:18.386960
10147 22:56:19.071279 00c00000 ################################################################
10148 22:56:19.071821
10149 22:56:19.787861 00c80000 ################################################################
10150 22:56:19.788378
10151 22:56:20.523191 00d00000 ################################################################
10152 22:56:20.523895
10153 22:56:21.243991 00d80000 ################################################################
10154 22:56:21.244571
10155 22:56:21.972718 00e00000 ################################################################
10156 22:56:21.973277
10157 22:56:22.701339 00e80000 ################################################################
10158 22:56:22.701932
10159 22:56:23.440926 00f00000 ################################################################
10160 22:56:23.441443
10161 22:56:24.169217 00f80000 ################################################################
10162 22:56:24.169816
10163 22:56:24.887542 01000000 ################################################################
10164 22:56:24.888227
10165 22:56:25.567319 01080000 ################################################################
10166 22:56:25.567947
10167 22:56:26.297122 01100000 ################################################################
10168 22:56:26.297656
10169 22:56:27.014512 01180000 ################################################################
10170 22:56:27.015042
10171 22:56:27.732069 01200000 ################################################################
10172 22:56:27.732223
10173 22:56:28.427475 01280000 ################################################################
10174 22:56:28.427628
10175 22:56:29.111728 01300000 ################################################################
10176 22:56:29.112252
10177 22:56:29.838870 01380000 ################################################################
10178 22:56:29.839450
10179 22:56:30.537958 01400000 ################################################################
10180 22:56:30.538488
10181 22:56:31.146507 01480000 ################################################################
10182 22:56:31.146723
10183 22:56:31.697977 01500000 ################################################################
10184 22:56:31.698183
10185 22:56:32.282776 01580000 ################################################################
10186 22:56:32.282965
10187 22:56:32.837267 01600000 ################################################################
10188 22:56:32.837447
10189 22:56:33.415026 01680000 ################################################################
10190 22:56:33.415192
10191 22:56:33.953362 01700000 ################################################################
10192 22:56:33.953573
10193 22:56:34.509651 01780000 ################################################################
10194 22:56:34.509863
10195 22:56:35.043605 01800000 ################################################################
10196 22:56:35.043857
10197 22:56:35.592238 01880000 ################################################################
10198 22:56:35.592445
10199 22:56:36.159711 01900000 ################################################################
10200 22:56:36.159920
10201 22:56:36.732312 01980000 ################################################################
10202 22:56:36.732537
10203 22:56:37.276952 01a00000 ################################################################
10204 22:56:37.277167
10205 22:56:37.825348 01a80000 ################################################################
10206 22:56:37.825502
10207 22:56:38.361527 01b00000 ################################################################
10208 22:56:38.361711
10209 22:56:38.932355 01b80000 ################################################################
10210 22:56:38.932507
10211 22:56:39.484794 01c00000 ################################################################
10212 22:56:39.484941
10213 22:56:40.056314 01c80000 ################################################################
10214 22:56:40.056531
10215 22:56:40.607956 01d00000 ################################################################
10216 22:56:40.608106
10217 22:56:41.144533 01d80000 ################################################################
10218 22:56:41.144701
10219 22:56:41.704027 01e00000 ################################################################
10220 22:56:41.704190
10221 22:56:42.225530 01e80000 ################################################################
10222 22:56:42.225695
10223 22:56:42.735170 01f00000 ################################################################
10224 22:56:42.735444
10225 22:56:43.244871 01f80000 ################################################################
10226 22:56:43.245038
10227 22:56:43.783802 02000000 ################################################################
10228 22:56:43.783968
10229 22:56:44.369654 02080000 ################################################################
10230 22:56:44.369830
10231 22:56:44.941293 02100000 ################################################################
10232 22:56:44.941526
10233 22:56:45.495139 02180000 ################################################################
10234 22:56:45.495321
10235 22:56:46.050649 02200000 ################################################################
10236 22:56:46.050813
10237 22:56:46.582765 02280000 ################################################################
10238 22:56:46.582941
10239 22:56:47.142912 02300000 ################################################################
10240 22:56:47.143093
10241 22:56:47.706545 02380000 ################################################################
10242 22:56:47.706717
10243 22:56:48.264016 02400000 ################################################################
10244 22:56:48.264183
10245 22:56:48.840092 02480000 ################################################################
10246 22:56:48.840300
10247 22:56:49.435732 02500000 ################################################################
10248 22:56:49.435894
10249 22:56:50.022027 02580000 ################################################################
10250 22:56:50.022191
10251 22:56:50.607194 02600000 ################################################################
10252 22:56:50.607354
10253 22:56:51.179651 02680000 ################################################################
10254 22:56:51.179862
10255 22:56:51.716086 02700000 ################################################################
10256 22:56:51.716249
10257 22:56:52.475424 02780000 ################################################################
10258 22:56:52.475665
10259 22:56:52.815323 02800000 ################################################################
10260 22:56:52.815520
10261 22:56:53.345079 02880000 ################################################################
10262 22:56:53.345276
10263 22:56:53.904338 02900000 ################################################################
10264 22:56:53.904587
10265 22:56:54.442808 02980000 ################################################################
10266 22:56:54.443000
10267 22:56:54.988007 02a00000 ################################################################
10268 22:56:54.988216
10269 22:56:55.529506 02a80000 ################################################################
10270 22:56:55.529688
10271 22:56:56.071807 02b00000 ################################################################
10272 22:56:56.072001
10273 22:56:56.631548 02b80000 ################################################################
10274 22:56:56.631725
10275 22:56:57.165879 02c00000 ################################################################
10276 22:56:57.166021
10277 22:56:57.734955 02c80000 ################################################################
10278 22:56:57.735128
10279 22:56:58.314061 02d00000 ################################################################
10280 22:56:58.314552
10281 22:56:58.870700 02d80000 ################################################################
10282 22:56:58.871335
10283 22:56:59.443989 02e00000 ################################################################
10284 22:56:59.444159
10285 22:57:00.014727 02e80000 ################################################################
10286 22:57:00.014879
10287 22:57:00.586074 02f00000 ################################################################
10288 22:57:00.586854
10289 22:57:01.180598 02f80000 ################################################################
10290 22:57:01.180748
10291 22:57:01.743513 03000000 ################################################################
10292 22:57:01.743694
10293 22:57:02.311934 03080000 ################################################################
10294 22:57:02.312465
10295 22:57:02.859309 03100000 ################################################################
10296 22:57:02.859487
10297 22:57:03.415655 03180000 ################################################################
10298 22:57:03.416714
10299 22:57:03.978499 03200000 ################################################################
10300 22:57:03.978671
10301 22:57:04.519387 03280000 ################################################################
10302 22:57:04.519541
10303 22:57:05.061615 03300000 ################################################################
10304 22:57:05.061778
10305 22:57:06.023491 03380000 ################################################################
10306 22:57:06.023716
10307 22:57:06.225142 03400000 ################################################################
10308 22:57:06.225360
10309 22:57:06.751149 03480000 ################################################################
10310 22:57:06.751331
10311 22:57:07.275952 03500000 ################################################################
10312 22:57:07.276113
10313 22:57:07.841932 03580000 ################################################################
10314 22:57:07.842108
10315 22:57:08.384156 03600000 ################################################################
10316 22:57:08.384355
10317 22:57:08.761256 03680000 ############################################# done.
10318 22:57:08.761405
10319 22:57:08.764940 The bootfile was 57514010 bytes long.
10320 22:57:08.765067
10321 22:57:08.767707 Sending tftp read request... done.
10322 22:57:08.767814
10323 22:57:08.767906 Waiting for the transfer...
10324 22:57:08.767985
10325 22:57:08.771179 00000000 # done.
10326 22:57:08.771291
10327 22:57:08.777575 Command line loaded dynamically from TFTP file: 10597662/tftp-deploy-29_5pyne/kernel/cmdline
10328 22:57:08.777706
10329 22:57:08.790894 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10330 22:57:08.791072
10331 22:57:08.791176 Loading FIT.
10332 22:57:08.791290
10333 22:57:08.794435 Image ramdisk-1 has 47379105 bytes.
10334 22:57:08.794561
10335 22:57:08.797390 Image fdt-1 has 46924 bytes.
10336 22:57:08.797477
10337 22:57:08.801140 Image kernel-1 has 10085945 bytes.
10338 22:57:08.801229
10339 22:57:08.807986 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10340 22:57:08.810886
10341 22:57:08.827570 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10342 22:57:08.827711
10343 22:57:08.830970 Choosing best match conf-1 for compat google,spherion-rev2.
10344 22:57:08.836455
10345 22:57:08.840609 Connected to device vid:did:rid of 1ae0:0028:00
10346 22:57:08.847747
10347 22:57:08.851187 tpm_get_response: command 0x17b, return code 0x0
10348 22:57:08.851301
10349 22:57:08.854054 ec_init: CrosEC protocol v3 supported (256, 248)
10350 22:57:08.858513
10351 22:57:08.861878 tpm_cleanup: add release locality here.
10352 22:57:08.862021
10353 22:57:08.862121 Shutting down all USB controllers.
10354 22:57:08.865408
10355 22:57:08.865497 Removing current net device
10356 22:57:08.865566
10357 22:57:08.871921 Exiting depthcharge with code 4 at timestamp: 111579114
10358 22:57:08.872017
10359 22:57:08.874805 LZMA decompressing kernel-1 to 0x821a6718
10360 22:57:08.874894
10361 22:57:08.878457 LZMA decompressing kernel-1 to 0x40000000
10362 22:57:10.145332
10363 22:57:10.145573 jumping to kernel
10364 22:57:10.146112 end: 2.2.4 bootloader-commands (duration 00:01:23) [common]
10365 22:57:10.146216 start: 2.2.5 auto-login-action (timeout 00:03:02) [common]
10366 22:57:10.146297 Setting prompt string to ['Linux version [0-9]']
10367 22:57:10.146370 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10368 22:57:10.146440 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10369 22:57:10.226825
10370 22:57:10.230262 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10371 22:57:10.233856 start: 2.2.5.1 login-action (timeout 00:03:02) [common]
10372 22:57:10.233983 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10373 22:57:10.234103 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10374 22:57:10.234213 Using line separator: #'\n'#
10375 22:57:10.234313 No login prompt set.
10376 22:57:10.234406 Parsing kernel messages
10377 22:57:10.234493 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10378 22:57:10.234673 [login-action] Waiting for messages, (timeout 00:03:02)
10379 22:57:10.253394 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j1612582-arm64-gcc-10-defconfig-arm64-chromebook-7xwc5) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Jun 5 22:41:02 UTC 2023
10380 22:57:10.256903 [ 0.000000] random: crng init done
10381 22:57:10.259889 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10382 22:57:10.263561 [ 0.000000] efi: UEFI not found.
10383 22:57:10.273442 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10384 22:57:10.279604 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10385 22:57:10.289875 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10386 22:57:10.299601 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10387 22:57:10.306220 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10388 22:57:10.309635 [ 0.000000] printk: bootconsole [mtk8250] enabled
10389 22:57:10.318525 [ 0.000000] NUMA: No NUMA configuration found
10390 22:57:10.324981 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10391 22:57:10.331294 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcda00-0x23efcffff]
10392 22:57:10.331414 [ 0.000000] Zone ranges:
10393 22:57:10.338409 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10394 22:57:10.341444 [ 0.000000] DMA32 empty
10395 22:57:10.348020 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10396 22:57:10.351320 [ 0.000000] Movable zone start for each node
10397 22:57:10.354398 [ 0.000000] Early memory node ranges
10398 22:57:10.361586 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10399 22:57:10.367902 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10400 22:57:10.374793 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10401 22:57:10.381289 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10402 22:57:10.388069 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10403 22:57:10.394337 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10404 22:57:10.451329 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10405 22:57:10.457710 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10406 22:57:10.463996 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10407 22:57:10.467610 [ 0.000000] psci: probing for conduit method from DT.
10408 22:57:10.474178 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10409 22:57:10.477764 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10410 22:57:10.483720 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10411 22:57:10.487221 [ 0.000000] psci: SMC Calling Convention v1.2
10412 22:57:10.493777 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10413 22:57:10.497188 [ 0.000000] Detected VIPT I-cache on CPU0
10414 22:57:10.503729 [ 0.000000] CPU features: detected: GIC system register CPU interface
10415 22:57:10.510241 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10416 22:57:10.517100 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10417 22:57:10.524035 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10418 22:57:10.530359 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10419 22:57:10.540279 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10420 22:57:10.543388 [ 0.000000] alternatives: applying boot alternatives
10421 22:57:10.550060 [ 0.000000] Fallback order for Node 0: 0
10422 22:57:10.556742 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10423 22:57:10.560354 [ 0.000000] Policy zone: Normal
10424 22:57:10.570188 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10425 22:57:10.580118 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10426 22:57:10.593193 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10427 22:57:10.603035 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10428 22:57:10.609600 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10429 22:57:10.612926 <6>[ 0.000000] software IO TLB: area num 8.
10430 22:57:10.669640 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10431 22:57:10.818464 <6>[ 0.000000] Memory: 7926672K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 426096K reserved, 32768K cma-reserved)
10432 22:57:10.825025 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10433 22:57:10.831590 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10434 22:57:10.834949 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10435 22:57:10.841562 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10436 22:57:10.848618 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10437 22:57:10.851370 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10438 22:57:10.861167 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10439 22:57:10.868289 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10440 22:57:10.874724 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10441 22:57:10.881254 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10442 22:57:10.884885 <6>[ 0.000000] GICv3: 608 SPIs implemented
10443 22:57:10.887653 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10444 22:57:10.894464 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10445 22:57:10.898046 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10446 22:57:10.904619 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10447 22:57:10.918027 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10448 22:57:10.928111 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10449 22:57:10.937756 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10450 22:57:10.945046 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10451 22:57:10.958371 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10452 22:57:10.964725 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10453 22:57:10.971450 <6>[ 0.009178] Console: colour dummy device 80x25
10454 22:57:10.981507 <6>[ 0.013906] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10455 22:57:10.988149 <6>[ 0.024348] pid_max: default: 32768 minimum: 301
10456 22:57:10.991167 <6>[ 0.029251] LSM: Security Framework initializing
10457 22:57:10.998212 <6>[ 0.034187] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10458 22:57:11.007859 <6>[ 0.042049] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10459 22:57:11.014448 <6>[ 0.051450] cblist_init_generic: Setting adjustable number of callback queues.
10460 22:57:11.021695 <6>[ 0.058950] cblist_init_generic: Setting shift to 3 and lim to 1.
10461 22:57:11.027538 <6>[ 0.065289] cblist_init_generic: Setting shift to 3 and lim to 1.
10462 22:57:11.034168 <6>[ 0.071696] rcu: Hierarchical SRCU implementation.
10463 22:57:11.041046 <6>[ 0.076710] rcu: Max phase no-delay instances is 1000.
10464 22:57:11.044484 <6>[ 0.083737] EFI services will not be available.
10465 22:57:11.051228 <6>[ 0.088738] smp: Bringing up secondary CPUs ...
10466 22:57:11.058648 <6>[ 0.093823] Detected VIPT I-cache on CPU1
10467 22:57:11.064994 <6>[ 0.093896] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10468 22:57:11.071946 <6>[ 0.093926] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10469 22:57:11.075344 <6>[ 0.094256] Detected VIPT I-cache on CPU2
10470 22:57:11.081774 <6>[ 0.094304] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10471 22:57:11.088173 <6>[ 0.094319] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10472 22:57:11.095215 <6>[ 0.094575] Detected VIPT I-cache on CPU3
10473 22:57:11.101554 <6>[ 0.094621] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10474 22:57:11.108381 <6>[ 0.094635] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10475 22:57:11.111221 <6>[ 0.094941] CPU features: detected: Spectre-v4
10476 22:57:11.118371 <6>[ 0.094948] CPU features: detected: Spectre-BHB
10477 22:57:11.121427 <6>[ 0.094954] Detected PIPT I-cache on CPU4
10478 22:57:11.128296 <6>[ 0.095009] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10479 22:57:11.134716 <6>[ 0.095026] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10480 22:57:11.141527 <6>[ 0.095328] Detected PIPT I-cache on CPU5
10481 22:57:11.147744 <6>[ 0.095390] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10482 22:57:11.154904 <6>[ 0.095407] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10483 22:57:11.157725 <6>[ 0.095690] Detected PIPT I-cache on CPU6
10484 22:57:11.164662 <6>[ 0.095757] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10485 22:57:11.171253 <6>[ 0.095773] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10486 22:57:11.178089 <6>[ 0.096066] Detected PIPT I-cache on CPU7
10487 22:57:11.185033 <6>[ 0.096129] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10488 22:57:11.191489 <6>[ 0.096145] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10489 22:57:11.194659 <6>[ 0.096194] smp: Brought up 1 node, 8 CPUs
10490 22:57:11.200982 <6>[ 0.237515] SMP: Total of 8 processors activated.
10491 22:57:11.204628 <6>[ 0.242436] CPU features: detected: 32-bit EL0 Support
10492 22:57:11.214768 <6>[ 0.247833] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10493 22:57:11.220872 <6>[ 0.256687] CPU features: detected: Common not Private translations
10494 22:57:11.224362 <6>[ 0.263163] CPU features: detected: CRC32 instructions
10495 22:57:11.230727 <6>[ 0.268514] CPU features: detected: RCpc load-acquire (LDAPR)
10496 22:57:11.237363 <6>[ 0.274474] CPU features: detected: LSE atomic instructions
10497 22:57:11.244336 <6>[ 0.280255] CPU features: detected: Privileged Access Never
10498 22:57:11.247689 <6>[ 0.286035] CPU features: detected: RAS Extension Support
10499 22:57:11.257192 <6>[ 0.291678] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10500 22:57:11.260576 <6>[ 0.298898] CPU: All CPU(s) started at EL2
10501 22:57:11.266949 <6>[ 0.303214] alternatives: applying system-wide alternatives
10502 22:57:11.275976 <6>[ 0.313959] devtmpfs: initialized
10503 22:57:11.288066 <6>[ 0.322682] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10504 22:57:11.298266 <6>[ 0.332643] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10505 22:57:11.304648 <6>[ 0.340830] pinctrl core: initialized pinctrl subsystem
10506 22:57:11.307994 <6>[ 0.347456] DMI not present or invalid.
10507 22:57:11.314609 <6>[ 0.351862] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10508 22:57:11.324849 <6>[ 0.358743] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10509 22:57:11.331663 <6>[ 0.366322] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10510 22:57:11.341598 <6>[ 0.374544] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10511 22:57:11.344564 <6>[ 0.382783] audit: initializing netlink subsys (disabled)
10512 22:57:11.354672 <5>[ 0.388476] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10513 22:57:11.361002 <6>[ 0.389163] thermal_sys: Registered thermal governor 'step_wise'
10514 22:57:11.367612 <6>[ 0.396445] thermal_sys: Registered thermal governor 'power_allocator'
10515 22:57:11.371216 <6>[ 0.402700] cpuidle: using governor menu
10516 22:57:11.377632 <6>[ 0.413658] NET: Registered PF_QIPCRTR protocol family
10517 22:57:11.384307 <6>[ 0.419135] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10518 22:57:11.387722 <6>[ 0.426236] ASID allocator initialised with 32768 entries
10519 22:57:11.395140 <6>[ 0.432787] Serial: AMBA PL011 UART driver
10520 22:57:11.403873 <4>[ 0.441358] Trying to register duplicate clock ID: 134
10521 22:57:11.456894 <6>[ 0.498209] KASLR enabled
10522 22:57:11.471482 <6>[ 0.505907] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10523 22:57:11.478012 <6>[ 0.512920] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10524 22:57:11.484536 <6>[ 0.519413] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10525 22:57:11.491234 <6>[ 0.526418] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10526 22:57:11.497942 <6>[ 0.532905] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10527 22:57:11.504731 <6>[ 0.539910] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10528 22:57:11.510890 <6>[ 0.546396] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10529 22:57:11.517445 <6>[ 0.553401] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10530 22:57:11.521006 <6>[ 0.560903] ACPI: Interpreter disabled.
10531 22:57:11.529547 <6>[ 0.567289] iommu: Default domain type: Translated
10532 22:57:11.536157 <6>[ 0.572402] iommu: DMA domain TLB invalidation policy: strict mode
10533 22:57:11.539587 <5>[ 0.579059] SCSI subsystem initialized
10534 22:57:11.546442 <6>[ 0.583224] usbcore: registered new interface driver usbfs
10535 22:57:11.552853 <6>[ 0.588955] usbcore: registered new interface driver hub
10536 22:57:11.556387 <6>[ 0.594506] usbcore: registered new device driver usb
10537 22:57:11.562634 <6>[ 0.600594] pps_core: LinuxPPS API ver. 1 registered
10538 22:57:11.572704 <6>[ 0.605789] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10539 22:57:11.575921 <6>[ 0.615137] PTP clock support registered
10540 22:57:11.579054 <6>[ 0.619379] EDAC MC: Ver: 3.0.0
10541 22:57:11.586664 <6>[ 0.624509] FPGA manager framework
10542 22:57:11.593271 <6>[ 0.628187] Advanced Linux Sound Architecture Driver Initialized.
10543 22:57:11.596647 <6>[ 0.634949] vgaarb: loaded
10544 22:57:11.600022 <6>[ 0.638045] clocksource: Switched to clocksource arch_sys_counter
10545 22:57:11.606377 <5>[ 0.644477] VFS: Disk quotas dquot_6.6.0
10546 22:57:11.613428 <6>[ 0.648662] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10547 22:57:11.616329 <6>[ 0.655850] pnp: PnP ACPI: disabled
10548 22:57:11.624502 <6>[ 0.662516] NET: Registered PF_INET protocol family
10549 22:57:11.634638 <6>[ 0.668099] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10550 22:57:11.645606 <6>[ 0.680378] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10551 22:57:11.655567 <6>[ 0.689191] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10552 22:57:11.662492 <6>[ 0.697159] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10553 22:57:11.672209 <6>[ 0.705859] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10554 22:57:11.678727 <6>[ 0.715608] TCP: Hash tables configured (established 65536 bind 65536)
10555 22:57:11.685701 <6>[ 0.722461] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10556 22:57:11.695121 <6>[ 0.729658] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10557 22:57:11.701969 <6>[ 0.737358] NET: Registered PF_UNIX/PF_LOCAL protocol family
10558 22:57:11.708504 <6>[ 0.743529] RPC: Registered named UNIX socket transport module.
10559 22:57:11.711608 <6>[ 0.749682] RPC: Registered udp transport module.
10560 22:57:11.718695 <6>[ 0.754612] RPC: Registered tcp transport module.
10561 22:57:11.725121 <6>[ 0.759546] RPC: Registered tcp NFSv4.1 backchannel transport module.
10562 22:57:11.728510 <6>[ 0.766217] PCI: CLS 0 bytes, default 64
10563 22:57:11.731505 <6>[ 0.770562] Unpacking initramfs...
10564 22:57:11.748132 <6>[ 0.782702] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10565 22:57:11.758378 <6>[ 0.791336] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10566 22:57:11.761502 <6>[ 0.800172] kvm [1]: IPA Size Limit: 40 bits
10567 22:57:11.767769 <6>[ 0.804698] kvm [1]: GICv3: no GICV resource entry
10568 22:57:11.771240 <6>[ 0.809719] kvm [1]: disabling GICv2 emulation
10569 22:57:11.778065 <6>[ 0.814412] kvm [1]: GIC system register CPU interface enabled
10570 22:57:11.781165 <6>[ 0.820568] kvm [1]: vgic interrupt IRQ18
10571 22:57:11.788551 <6>[ 0.826250] kvm [1]: VHE mode initialized successfully
10572 22:57:11.795113 <5>[ 0.832604] Initialise system trusted keyrings
10573 22:57:11.801196 <6>[ 0.837434] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10574 22:57:11.809246 <6>[ 0.847402] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10575 22:57:11.816341 <5>[ 0.853795] NFS: Registering the id_resolver key type
10576 22:57:11.819717 <5>[ 0.859101] Key type id_resolver registered
10577 22:57:11.826133 <5>[ 0.863522] Key type id_legacy registered
10578 22:57:11.832536 <6>[ 0.867803] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10579 22:57:11.839576 <6>[ 0.874724] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10580 22:57:11.846149 <6>[ 0.882455] 9p: Installing v9fs 9p2000 file system support
10581 22:57:11.882203 <5>[ 0.920172] Key type asymmetric registered
10582 22:57:11.885929 <5>[ 0.924500] Asymmetric key parser 'x509' registered
10583 22:57:11.895879 <6>[ 0.929645] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10584 22:57:11.898867 <6>[ 0.937259] io scheduler mq-deadline registered
10585 22:57:11.902411 <6>[ 0.942018] io scheduler kyber registered
10586 22:57:11.920849 <6>[ 0.958732] EINJ: ACPI disabled.
10587 22:57:11.952773 <4>[ 0.983912] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10588 22:57:11.962574 <4>[ 0.994551] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10589 22:57:11.976928 <6>[ 1.015048] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10590 22:57:11.985054 <6>[ 1.023093] printk: console [ttyS0] disabled
10591 22:57:12.013099 <6>[ 1.047755] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10592 22:57:12.019970 <6>[ 1.057229] printk: console [ttyS0] enabled
10593 22:57:12.023003 <6>[ 1.057229] printk: console [ttyS0] enabled
10594 22:57:12.030054 <6>[ 1.066121] printk: bootconsole [mtk8250] disabled
10595 22:57:12.032986 <6>[ 1.066121] printk: bootconsole [mtk8250] disabled
10596 22:57:12.040078 <6>[ 1.077412] SuperH (H)SCI(F) driver initialized
10597 22:57:12.043154 <6>[ 1.082693] msm_serial: driver initialized
10598 22:57:12.057308 <6>[ 1.091597] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10599 22:57:12.066876 <6>[ 1.100144] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10600 22:57:12.073669 <6>[ 1.108693] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10601 22:57:12.083787 <6>[ 1.117325] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10602 22:57:12.090075 <6>[ 1.126031] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10603 22:57:12.100107 <6>[ 1.134744] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10604 22:57:12.110134 <6>[ 1.143284] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10605 22:57:12.116633 <6>[ 1.152095] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10606 22:57:12.126371 <6>[ 1.160639] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10607 22:57:12.138159 <6>[ 1.176162] loop: module loaded
10608 22:57:12.145132 <6>[ 1.182119] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10609 22:57:12.167721 <4>[ 1.205558] mtk-pmic-keys: Failed to locate of_node [id: -1]
10610 22:57:12.174276 <6>[ 1.212376] megasas: 07.719.03.00-rc1
10611 22:57:12.184083 <6>[ 1.222150] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10612 22:57:12.192138 <6>[ 1.229463] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10613 22:57:12.208483 <6>[ 1.246095] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10614 22:57:12.268627 <6>[ 1.300175] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10615 22:57:13.746115 <6>[ 2.782107] Freeing initrd memory: 46264K
10616 22:57:13.754472 <6>[ 2.792327] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10617 22:57:13.765452 <6>[ 2.803430] tun: Universal TUN/TAP device driver, 1.6
10618 22:57:13.768447 <6>[ 2.809492] thunder_xcv, ver 1.0
10619 22:57:13.771978 <6>[ 2.812995] thunder_bgx, ver 1.0
10620 22:57:13.775035 <6>[ 2.816489] nicpf, ver 1.0
10621 22:57:13.785615 <6>[ 2.820508] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10622 22:57:13.789170 <6>[ 2.827984] hns3: Copyright (c) 2017 Huawei Corporation.
10623 22:57:13.795644 <6>[ 2.833573] hclge is initializing
10624 22:57:13.799054 <6>[ 2.837158] e1000: Intel(R) PRO/1000 Network Driver
10625 22:57:13.805537 <6>[ 2.842287] e1000: Copyright (c) 1999-2006 Intel Corporation.
10626 22:57:13.809014 <6>[ 2.848300] e1000e: Intel(R) PRO/1000 Network Driver
10627 22:57:13.816183 <6>[ 2.853516] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10628 22:57:13.822158 <6>[ 2.859724] igb: Intel(R) Gigabit Ethernet Network Driver
10629 22:57:13.829367 <6>[ 2.865379] igb: Copyright (c) 2007-2014 Intel Corporation.
10630 22:57:13.835541 <6>[ 2.871219] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10631 22:57:13.842072 <6>[ 2.877738] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10632 22:57:13.845552 <6>[ 2.884197] sky2: driver version 1.30
10633 22:57:13.851994 <6>[ 2.889176] VFIO - User Level meta-driver version: 0.3
10634 22:57:13.859846 <6>[ 2.897384] usbcore: registered new interface driver usb-storage
10635 22:57:13.865758 <6>[ 2.903836] usbcore: registered new device driver onboard-usb-hub
10636 22:57:13.875067 <6>[ 2.912964] mt6397-rtc mt6359-rtc: registered as rtc0
10637 22:57:13.884785 <6>[ 2.918452] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-05T22:57:19 UTC (1686005839)
10638 22:57:13.888217 <6>[ 2.928059] i2c_dev: i2c /dev entries driver
10639 22:57:13.904896 <6>[ 2.939657] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10640 22:57:13.912028 <6>[ 2.949875] sdhci: Secure Digital Host Controller Interface driver
10641 22:57:13.918478 <6>[ 2.956313] sdhci: Copyright(c) Pierre Ossman
10642 22:57:13.925207 <6>[ 2.961704] Synopsys Designware Multimedia Card Interface Driver
10643 22:57:13.928232 <6>[ 2.968301] mmc0: CQHCI version 5.10
10644 22:57:13.934742 <6>[ 2.968854] sdhci-pltfm: SDHCI platform and OF driver helper
10645 22:57:13.942718 <6>[ 2.980456] ledtrig-cpu: registered to indicate activity on CPUs
10646 22:57:13.953164 <6>[ 2.987875] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10647 22:57:13.956655 <6>[ 2.995295] usbcore: registered new interface driver usbhid
10648 22:57:13.963053 <6>[ 3.001129] usbhid: USB HID core driver
10649 22:57:13.969524 <6>[ 3.005380] spi_master spi0: will run message pump with realtime priority
10650 22:57:14.016041 <6>[ 3.047670] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10651 22:57:14.036204 <6>[ 3.063528] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10652 22:57:14.039272 <6>[ 3.077106] mmc0: Command Queue Engine enabled
10653 22:57:14.046714 <6>[ 3.078529] cros-ec-spi spi0.0: Chrome EC device registered
10654 22:57:14.049639 <6>[ 3.081854] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10655 22:57:14.057204 <6>[ 3.095195] mmcblk0: mmc0:0001 DA4128 116 GiB
10656 22:57:14.070542 <6>[ 3.105628] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10657 22:57:14.077638 <6>[ 3.108321] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10658 22:57:14.084148 <6>[ 3.117036] NET: Registered PF_PACKET protocol family
10659 22:57:14.087586 <6>[ 3.122004] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10660 22:57:14.093995 <6>[ 3.126292] 9pnet: Installing 9P2000 support
10661 22:57:14.097483 <6>[ 3.132029] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10662 22:57:14.104339 <5>[ 3.135969] Key type dns_resolver registered
10663 22:57:14.110629 <6>[ 3.141752] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10664 22:57:14.113671 <6>[ 3.146236] registered taskstats version 1
10665 22:57:14.117029 <5>[ 3.156584] Loading compiled-in X.509 certificates
10666 22:57:14.151839 <4>[ 3.183213] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10667 22:57:14.161679 <4>[ 3.193889] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10668 22:57:14.171928 <3>[ 3.206689] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10669 22:57:14.184191 <6>[ 3.222187] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10670 22:57:14.190847 <6>[ 3.228941] xhci-mtk 11200000.usb: xHCI Host Controller
10671 22:57:14.197293 <6>[ 3.234440] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10672 22:57:14.207309 <6>[ 3.242298] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10673 22:57:14.214397 <6>[ 3.251739] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10674 22:57:14.220884 <6>[ 3.257819] xhci-mtk 11200000.usb: xHCI Host Controller
10675 22:57:14.227366 <6>[ 3.263439] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10676 22:57:14.233936 <6>[ 3.271128] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10677 22:57:14.241103 <6>[ 3.279032] hub 1-0:1.0: USB hub found
10678 22:57:14.244692 <6>[ 3.283067] hub 1-0:1.0: 1 port detected
10679 22:57:14.254616 <6>[ 3.287420] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10680 22:57:14.257363 <6>[ 3.296059] hub 2-0:1.0: USB hub found
10681 22:57:14.260932 <6>[ 3.300073] hub 2-0:1.0: 1 port detected
10682 22:57:14.268855 <6>[ 3.307214] mtk-msdc 11f70000.mmc: Got CD GPIO
10683 22:57:14.286681 <6>[ 3.321271] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10684 22:57:14.292819 <6>[ 3.329302] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10685 22:57:14.303177 <4>[ 3.337293] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10686 22:57:14.312882 <6>[ 3.346960] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10687 22:57:14.319327 <6>[ 3.355041] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10688 22:57:14.329389 <6>[ 3.363062] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10689 22:57:14.335854 <6>[ 3.370981] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10690 22:57:14.342513 <6>[ 3.378807] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10691 22:57:14.352466 <6>[ 3.386630] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10692 22:57:14.362912 <6>[ 3.397328] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10693 22:57:14.372318 <6>[ 3.405696] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10694 22:57:14.379047 <6>[ 3.414062] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10695 22:57:14.388991 <6>[ 3.422406] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10696 22:57:14.395310 <6>[ 3.430749] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10697 22:57:14.405451 <6>[ 3.439092] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10698 22:57:14.411935 <6>[ 3.447435] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10699 22:57:14.422643 <6>[ 3.455777] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10700 22:57:14.428682 <6>[ 3.464119] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10701 22:57:14.438866 <6>[ 3.472462] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10702 22:57:14.445365 <6>[ 3.480804] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10703 22:57:14.454910 <6>[ 3.489153] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10704 22:57:14.461747 <6>[ 3.497496] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10705 22:57:14.471741 <6>[ 3.505840] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10706 22:57:14.478253 <6>[ 3.514184] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10707 22:57:14.485062 <6>[ 3.523071] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10708 22:57:14.492298 <6>[ 3.530482] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10709 22:57:14.499558 <6>[ 3.537525] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10710 22:57:14.510004 <6>[ 3.544657] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10711 22:57:14.516356 <6>[ 3.551963] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10712 22:57:14.526755 <6>[ 3.558877] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10713 22:57:14.533208 <6>[ 3.568016] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10714 22:57:14.543152 <6>[ 3.577143] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10715 22:57:14.553184 <6>[ 3.586446] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10716 22:57:14.562742 <6>[ 3.595920] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10717 22:57:14.572728 <6>[ 3.605395] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10718 22:57:14.579632 <6>[ 3.614522] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10719 22:57:14.589431 <6>[ 3.623999] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10720 22:57:14.599011 <6>[ 3.633131] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10721 22:57:14.609127 <6>[ 3.642434] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10722 22:57:14.619187 <6>[ 3.652600] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10723 22:57:14.629485 <6>[ 3.664044] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10724 22:57:14.675856 <6>[ 3.710331] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10725 22:57:14.829696 <6>[ 3.867633] hub 1-1:1.0: USB hub found
10726 22:57:14.832516 <6>[ 3.872093] hub 1-1:1.0: 4 ports detected
10727 22:57:14.955328 <6>[ 3.990521] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10728 22:57:14.980256 <6>[ 4.018674] hub 2-1:1.0: USB hub found
10729 22:57:14.983971 <6>[ 4.023067] hub 2-1:1.0: 3 ports detected
10730 22:57:15.155368 <6>[ 4.190325] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10731 22:57:15.287733 <6>[ 4.326204] hub 1-1.4:1.0: USB hub found
10732 22:57:15.291324 <6>[ 4.330861] hub 1-1.4:1.0: 2 ports detected
10733 22:57:15.367394 <6>[ 4.402561] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10734 22:57:15.587395 <6>[ 4.622183] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10735 22:57:15.779322 <6>[ 4.814324] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10736 22:57:26.904145 <6>[ 15.946875] ALSA device list:
10737 22:57:26.910642 <6>[ 15.950130] No soundcards found.
10738 22:57:26.923097 <6>[ 15.962533] Freeing unused kernel memory: 8384K
10739 22:57:26.926088 <6>[ 15.967446] Run /init as init process
10740 22:57:26.956423 <6>[ 15.996174] NET: Registered PF_INET6 protocol family
10741 22:57:26.963465 <6>[ 16.002587] Segment Routing with IPv6
10742 22:57:26.966378 <6>[ 16.006564] In-situ OAM (IOAM) with IPv6
10743 22:57:26.998246 <30>[ 16.021003] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10744 22:57:27.005283 <30>[ 16.044823] systemd[1]: Detected architecture arm64.
10745 22:57:27.005438
10746 22:57:27.011580 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10747 22:57:27.011698
10748 22:57:27.030620 <30>[ 16.070427] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10749 22:57:27.196142 <30>[ 16.232715] systemd[1]: Queued start job for default target Graphical Interface.
10750 22:57:27.243869 <30>[ 16.283589] systemd[1]: Created slice system-getty.slice.
10751 22:57:27.250439 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10752 22:57:27.267620 <30>[ 16.306972] systemd[1]: Created slice system-modprobe.slice.
10753 22:57:27.273743 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10754 22:57:27.291983 <30>[ 16.331451] systemd[1]: Created slice system-serial\x2dgetty.slice.
10755 22:57:27.301837 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10756 22:57:27.315486 <30>[ 16.354845] systemd[1]: Created slice User and Session Slice.
10757 22:57:27.321835 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10758 22:57:27.342566 <30>[ 16.378887] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10759 22:57:27.352597 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10760 22:57:27.369826 <30>[ 16.406427] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10761 22:57:27.376365 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10762 22:57:27.397398 <30>[ 16.430434] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10763 22:57:27.404188 <30>[ 16.442484] systemd[1]: Reached target Local Encrypted Volumes.
10764 22:57:27.411203 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10765 22:57:27.427192 <30>[ 16.466693] systemd[1]: Reached target Paths.
10766 22:57:27.430116 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10767 22:57:27.446517 <30>[ 16.486371] systemd[1]: Reached target Remote File Systems.
10768 22:57:27.453044 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10769 22:57:27.470788 <30>[ 16.510605] systemd[1]: Reached target Slices.
10770 22:57:27.477216 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10771 22:57:27.490750 <30>[ 16.530398] systemd[1]: Reached target Swap.
10772 22:57:27.494284 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10773 22:57:27.514467 <30>[ 16.550696] systemd[1]: Listening on initctl Compatibility Named Pipe.
10774 22:57:27.520889 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10775 22:57:27.527483 <30>[ 16.565403] systemd[1]: Listening on Journal Audit Socket.
10776 22:57:27.533732 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10777 22:57:27.547105 <30>[ 16.586647] systemd[1]: Listening on Journal Socket (/dev/log).
10778 22:57:27.553792 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10779 22:57:27.571463 <30>[ 16.611120] systemd[1]: Listening on Journal Socket.
10780 22:57:27.578084 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10781 22:57:27.594356 <30>[ 16.630751] systemd[1]: Listening on Network Service Netlink Socket.
10782 22:57:27.600846 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10783 22:57:27.615791 <30>[ 16.655105] systemd[1]: Listening on udev Control Socket.
10784 22:57:27.622110 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10785 22:57:27.639364 <30>[ 16.679040] systemd[1]: Listening on udev Kernel Socket.
10786 22:57:27.646134 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10787 22:57:27.683040 <30>[ 16.722741] systemd[1]: Mounting Huge Pages File System...
10788 22:57:27.689480 Mounting [0;1;39mHuge Pages File System[0m...
10789 22:57:27.704931 <30>[ 16.744575] systemd[1]: Mounting POSIX Message Queue File System...
10790 22:57:27.711554 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10791 22:57:27.728909 <30>[ 16.768562] systemd[1]: Mounting Kernel Debug File System...
10792 22:57:27.735344 Mounting [0;1;39mKernel Debug File System[0m...
10793 22:57:27.754700 <30>[ 16.790812] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10794 22:57:27.774366 <30>[ 16.810937] systemd[1]: Starting Create list of static device nodes for the current kernel...
10795 22:57:27.781009 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10796 22:57:27.801127 <30>[ 16.840853] systemd[1]: Starting Load Kernel Module configfs...
10797 22:57:27.807500 Starting [0;1;39mLoad Kernel Module configfs[0m...
10798 22:57:27.825758 <30>[ 16.865141] systemd[1]: Starting Load Kernel Module drm...
10799 22:57:27.831949 Starting [0;1;39mLoad Kernel Module drm[0m...
10800 22:57:27.850018 <30>[ 16.886559] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10801 22:57:27.883002 <30>[ 16.922919] systemd[1]: Starting Journal Service...
10802 22:57:27.886586 Starting [0;1;39mJournal Service[0m...
10803 22:57:27.905783 <30>[ 16.945350] systemd[1]: Starting Load Kernel Modules...
10804 22:57:27.912301 Starting [0;1;39mLoad Kernel Modules[0m...
10805 22:57:27.933049 <30>[ 16.969273] systemd[1]: Starting Remount Root and Kernel File Systems...
10806 22:57:27.939361 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10807 22:57:27.961054 <30>[ 17.000986] systemd[1]: Starting Coldplug All udev Devices...
10808 22:57:27.967734 Starting [0;1;39mColdplug All udev Devices[0m...
10809 22:57:27.985149 <30>[ 17.024869] systemd[1]: Started Journal Service.
10810 22:57:27.991734 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10811 22:57:28.008571 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10812 22:57:28.023808 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10813 22:57:28.039754 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10814 22:57:28.059308 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10815 22:57:28.076438 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10816 22:57:28.092472 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10817 22:57:28.112151 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10818 22:57:28.135679 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10819 22:57:28.150737 See 'systemctl status systemd-remount-fs.service' for details.
10820 22:57:28.196981 Mounting [0;1;39mKernel Configuration File System[0m...
10821 22:57:28.217459 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10822 22:57:28.235334 <46>[ 17.271706] systemd-journald[176]: Received client request to flush runtime journal.
10823 22:57:28.244093 Starting [0;1;39mLoad/Save Random Seed[0m...
10824 22:57:28.265415 Starting [0;1;39mApply Kernel Variables[0m...
10825 22:57:28.285441 Starting [0;1;39mCreate System Users[0m...
10826 22:57:28.307474 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10827 22:57:28.331292 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10828 22:57:28.343983 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10829 22:57:28.359943 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10830 22:57:28.379518 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10831 22:57:28.395651 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10832 22:57:28.435823 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10833 22:57:28.458849 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10834 22:57:28.475411 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10835 22:57:28.494410 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10836 22:57:28.531562 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10837 22:57:28.554371 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10838 22:57:28.572090 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10839 22:57:28.592057 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10840 22:57:28.636439 Starting [0;1;39mNetwork Service[0m...
10841 22:57:28.657598 Starting [0;1;39mNetwork Time Synchronization[0m...
10842 22:57:28.675556 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10843 22:57:28.717961 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10844 22:57:28.732173 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10845 22:57:28.783608 <6>[ 17.819840] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10846 22:57:28.794492 Starting [0;1;39mNetwork Name Resolution[0m...
10847 22:57:28.813231 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10848 22:57:28.844286 <6>[ 17.883729] remoteproc remoteproc0: scp is available
10849 22:57:28.853799 <4>[ 17.889166] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10850 22:57:28.860722 [[0;32m OK [<6>[ 17.899464] remoteproc remoteproc0: powering up scp
10851 22:57:28.866922 <6>[ 17.903799] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10852 22:57:28.880437 0m] Found device<4>[ 17.905876] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10853 22:57:28.886957 <4>[ 17.910559] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10854 22:57:28.897175 [0;1;39m/dev/t<6>[ 17.914085] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10855 22:57:28.897341 tyS0[0m.
10856 22:57:28.906971 <4>[ 17.920758] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10857 22:57:28.909918 <3>[ 17.924594] remoteproc remoteproc0: request_firmware failed: -2
10858 22:57:28.920165 <6>[ 17.932098] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10859 22:57:28.929699 <3>[ 17.966336] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10860 22:57:28.936828 <3>[ 17.974458] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10861 22:57:28.946580 [[0;32m OK [<3>[ 17.983081] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10862 22:57:28.953504 0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10863 22:57:28.963040 <3>[ 17.999462] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10864 22:57:28.969728 <3>[ 18.007664] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10865 22:57:28.979452 <3>[ 18.015967] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10866 22:57:28.986327 <3>[ 18.024064] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10867 22:57:28.996154 <3>[ 18.032160] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10868 22:57:29.006154 [[0;32m OK [<6>[ 18.033869] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10869 22:57:29.012759 0m] Reached target [0;1;39mSystem Time Set[0m.<6>[ 18.052774] mc: Linux media interface: v0.10
10870 22:57:29.012874
10871 22:57:29.022816 <6>[ 18.059323] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10872 22:57:29.033559 <3>[ 18.069681] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10873 22:57:29.040035 <6>[ 18.070638] videodev: Linux video capture interface: v2.00
10874 22:57:29.046438 <4>[ 18.083760] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10875 22:57:29.053214 <4>[ 18.083760] Fallback method does not support PEC.
10876 22:57:29.059689 <3>[ 18.087047] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10877 22:57:29.066282 <6>[ 18.103348] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10878 22:57:29.076027 [[0;32m OK [<3>[ 18.105787] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10879 22:57:29.083184 0m] Reached targ<6>[ 18.112772] pci_bus 0000:00: root bus resource [bus 00-ff]
10880 22:57:29.095795 et [0;1;39mSyst<6>[ 18.114905] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10881 22:57:29.106151 em Time Synchron<6>[ 18.116497] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10882 22:57:29.106289 ized[0m.
10883 22:57:29.115907 <3>[ 18.121919] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10884 22:57:29.122457 <6>[ 18.125094] usbcore: registered new interface driver r8152
10885 22:57:29.128930 <6>[ 18.129178] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10886 22:57:29.135512 <3>[ 18.167679] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10887 22:57:29.145523 <6>[ 18.172921] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10888 22:57:29.152118 <6>[ 18.178248] usbcore: registered new interface driver cdc_ether
10889 22:57:29.158967 <3>[ 18.181096] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10890 22:57:29.165684 <6>[ 18.191087] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10891 22:57:29.175483 <3>[ 18.197140] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10892 22:57:29.181964 <6>[ 18.205315] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10893 22:57:29.192048 <3>[ 18.211508] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10894 22:57:29.195417 <6>[ 18.217112] Bluetooth: Core ver 2.22
10895 22:57:29.198313 <6>[ 18.217511] NET: Registered PF_BLUETOOTH protocol family
10896 22:57:29.205342 <6>[ 18.217514] Bluetooth: HCI device and connection manager initialized
10897 22:57:29.212298 <6>[ 18.217534] Bluetooth: HCI socket layer initialized
10898 22:57:29.218234 <6>[ 18.217540] Bluetooth: L2CAP socket layer initialized
10899 22:57:29.221845 <6>[ 18.217554] Bluetooth: SCO socket layer initialized
10900 22:57:29.224838 <6>[ 18.219786] pci 0000:00:00.0: supports D1 D2
10901 22:57:29.234917 <3>[ 18.227246] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10902 22:57:29.241954 <6>[ 18.235193] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10903 22:57:29.248729 <6>[ 18.239259] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10904 22:57:29.258467 <3>[ 18.247904] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10905 22:57:29.261986 <6>[ 18.247999] usbcore: registered new interface driver r8153_ecm
10906 22:57:29.271610 <6>[ 18.272048] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10907 22:57:29.281790 <4>[ 18.283544] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10908 22:57:29.288083 <6>[ 18.287877] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10909 22:57:29.294817 <4>[ 18.293724] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10910 22:57:29.301105 <6>[ 18.295017] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10911 22:57:29.308157 <6>[ 18.301879] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10912 22:57:29.321022 <4>[ 18.325426] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10913 22:57:29.324631 <6>[ 18.327308] usbcore: registered new interface driver btusb
10914 22:57:29.334897 <6>[ 18.331514] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10915 22:57:29.337877 <3>[ 18.339588] Bluetooth: hci0: Failed to load firmware file (-2)
10916 22:57:29.344309 <6>[ 18.341053] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10917 22:57:29.357953 <6>[ 18.343266] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10918 22:57:29.364462 <6>[ 18.344275] usbcore: registered new interface driver uvcvideo
10919 22:57:29.370955 <6>[ 18.347319] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10920 22:57:29.378033 <6>[ 18.349646] remoteproc remoteproc0: powering up scp
10921 22:57:29.387688 <4>[ 18.349708] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10922 22:57:29.394288 <3>[ 18.349716] remoteproc remoteproc0: request_firmware failed: -2
10923 22:57:29.400886 <3>[ 18.349787] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
10924 22:57:29.407598 <3>[ 18.354146] Bluetooth: hci0: Failed to set up firmware (-2)
10925 22:57:29.410920 <6>[ 18.364788] pci 0000:01:00.0: supports D1 D2
10926 22:57:29.421148 <4>[ 18.370446] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10927 22:57:29.427821 <6>[ 18.377885] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10928 22:57:29.431311 <6>[ 18.386461] r8152 2-1.3:1.0 eth0: v1.12.13
10929 22:57:29.438636 <6>[ 18.402322] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10930 22:57:29.448882 <3>[ 18.411188] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10931 22:57:29.452498 <6>[ 18.416071] r8152 2-1.3:1.0 enx002432307852: renamed from eth0
10932 22:57:29.463214 <6>[ 18.416422] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10933 22:57:29.469661 <3>[ 18.485728] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10934 22:57:29.479600 <6>[ 18.492699] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10935 22:57:29.486412 <6>[ 18.492714] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10936 22:57:29.496189 <6>[ 18.531637] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10937 22:57:29.502568 <6>[ 18.531653] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10938 22:57:29.509071 <6>[ 18.531669] pci 0000:00:00.0: PCI bridge to [bus 01]
10939 22:57:29.515516 <6>[ 18.531676] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10940 22:57:29.522627 <6>[ 18.531870] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10941 22:57:29.529071 Startin<6>[ 18.568214] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10942 22:57:29.535673 g [0;1;39mLoad/<6>[ 18.575121] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10943 22:57:29.542152 Save Screen …of leds:white:kbd_backlight[0m...
10944 22:57:29.559466 <5>[ 18.595522] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10945 22:57:29.565954 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10946 22:57:29.579638 <5>[ 18.615985] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10947 22:57:29.586189 <4>[ 18.623649] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10948 22:57:29.593036 <6>[ 18.632613] cfg80211: failed to load regulatory.db
10949 22:57:29.602774 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10950 22:57:29.640245 <6>[ 18.676878] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10951 22:57:29.646752 <6>[ 18.684481] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10952 22:57:29.670042 <6>[ 18.710102] mt7921e 0000:01:00.0: ASIC revision: 79610010
10953 22:57:29.729706 <3>[ 18.765190] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10954 22:57:29.739308 <3>[ 18.765926] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10955 22:57:29.745841 <3>[ 18.774451] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10956 22:57:29.788647 [[0;32m OK [0m] Reached targ<4>[ 18.819856] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10957 22:57:29.795257 <3>[ 18.821285] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10958 22:57:29.798695 et [0;1;39mBluetooth[0m.
10959 22:57:29.815070 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10960 22:57:29.828746 <3>[ 18.865132] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10961 22:57:29.835547 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10962 22:57:29.851172 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10963 22:57:29.861162 <3>[ 18.897442] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10964 22:57:29.868374 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10965 22:57:29.886778 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10966 22:57:29.896444 [[0;32m OK [<3>[ 18.931169] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10967 22:57:29.906540 <4>[ 18.940736] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10968 22:57:29.909580 0m] Reached target [0;1;39mTimers[0m.
10969 22:57:29.939448 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message B<3>[ 18.974511] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10970 22:57:29.939687 us Socket[0m.
10971 22:57:29.954489 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10972 22:57:29.970678 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10973 22:57:29.990448 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10974 22:57:30.031318 <4>[ 19.064607] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10975 22:57:30.049284 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10976 22:57:30.077216 Starting [0;1;39mUser Login Management[0m...
10977 22:57:30.093098 Starting [0;1;39mPermit User Sessions[0m...
10978 22:57:30.110649 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10979 22:57:30.127000 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10980 22:57:30.147795 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10981 22:57:30.162127 <4>[ 19.195005] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10982 22:57:30.173389 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10983 22:57:30.194092 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10984 22:57:30.214537 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10985 22:57:30.235868 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10986 22:57:30.251472 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10987 22:57:30.266451 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10988 22:57:30.287161 <4>[ 19.320603] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10989 22:57:30.335064 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10990 22:57:30.358525 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10991 22:57:30.377247
10992 22:57:30.377418
10993 22:57:30.380179 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10994 22:57:30.380283
10995 22:57:30.383551 debian-bullseye-arm64 login: root (automatic login)
10996 22:57:30.383656
10997 22:57:30.383766
10998 22:57:30.408662 <4>[ 19.442287] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10999 22:57:30.415409 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Mon Jun 5 22:41:02 UTC 2023 aarch64
11000 22:57:30.415535
11001 22:57:30.422138 The programs included with the Debian GNU/Linux system are free software;
11002 22:57:30.428901 the exact distribution terms for each program are described in the
11003 22:57:30.432180 individual files in /usr/share/doc/*/copyright.
11004 22:57:30.435182
11005 22:57:30.438801 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11006 22:57:30.442127 permitted by applicable law.
11007 22:57:30.442674 Matched prompt #10: / #
11009 22:57:30.442994 Setting prompt string to ['/ #']
11010 22:57:30.443119 end: 2.2.5.1 login-action (duration 00:00:20) [common]
11012 22:57:30.443462 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
11013 22:57:30.443631 start: 2.2.6 expect-shell-connection (timeout 00:02:41) [common]
11014 22:57:30.443779 Setting prompt string to ['/ #']
11015 22:57:30.443911 Forcing a shell prompt, looking for ['/ #']
11017 22:57:30.494252 / #
11018 22:57:30.494412 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11019 22:57:30.494496 Waiting using forced prompt support (timeout 00:02:30)
11020 22:57:30.499322
11021 22:57:30.499639 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11022 22:57:30.499737 start: 2.2.7 export-device-env (timeout 00:02:41) [common]
11023 22:57:30.499836 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11024 22:57:30.499927 end: 2.2 depthcharge-retry (duration 00:02:19) [common]
11025 22:57:30.500013 end: 2 depthcharge-action (duration 00:02:19) [common]
11026 22:57:30.500102 start: 3 lava-test-retry (timeout 00:05:00) [common]
11027 22:57:30.500184 start: 3.1 lava-test-shell (timeout 00:05:00) [common]
11028 22:57:30.500257 Using namespace: common
11030 22:57:30.600550 / # #
11031 22:57:30.600739 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:05:00)
11032 22:57:30.600897 <4>[ 19.564492] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11033 22:57:30.606030 #
11034 22:57:30.606337 Using /lava-10597662
11036 22:57:30.706743 / # export SHELL=/bin/sh
11037 22:57:30.706977 <4>[ 19.684549] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11038 22:57:30.711708 export SHELL=/bin/sh
11040 22:57:30.812293 / # . /lava-10597662/environment
11041 22:57:30.812534 <4>[ 19.803935] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11042 22:57:30.817592 . /lava-10597662/environment
11044 22:57:30.918200 / # /lava-10597662/bin/lava-test-runner /lava-10597662/0
11045 22:57:30.918428 Test shell timeout: 10s (minimum of the action and connection timeout)
11046 22:57:30.918900 /lava-10597662/bin/lava-test-runner /l<4>[ 19.920113] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11047 22:57:30.923183 ava-10597662/0
11048 22:57:30.963433 + export TESTRUN_ID=0_cros-ec
11049 22:57:30.963583 +<8>[ 19.987417] <LAVA_SIGNAL_STARTRUN 0_cros-ec 10597662_1.5.2.3.1>
11050 22:57:30.963660 cd /lava-10597662/0/tests/0_cros-ec
11051 22:57:30.963911 Received signal: <STARTRUN> 0_cros-ec 10597662_1.5.2.3.1
11052 22:57:30.963985 Starting test lava.0_cros-ec (10597662_1.5.2.3.1)
11053 22:57:30.964078 Skipping test definition patterns.
11054 22:57:30.964189 + cat uuid
11055 22:57:30.964257 + UUID=10597662_1.5.2.3.1
11056 22:57:30.964329 + set +x
11057 22:57:30.964391 + python3 -m cros.runners.lava_runner -v
11058 22:57:30.981102 <6>[ 20.017514] IPv6: ADDRCONF(NETDEV_CHANGE): enx002432307852: link becomes ready
11059 22:57:30.987308 <6>[ 20.025485] r8152 2-1.3:1.0 enx002432307852: carrier on
11060 22:57:31.002325 <3>[ 20.042533] mt7921e 0000:01:00.0: hardware init failed
11061 22:57:31.661633 test_cros_ec_accel_iio_abi (cros.tests.cros_ec_accel.TestCrosECAccel)
11062 22:57:31.668008 Checks the cros-ec accelerometer IIO ABI. ... skipped 'No cros-ec-accel found'
11063 22:57:31.670983
11064 22:57:31.677860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_accel_iio_abi RESULT=skip>
11065 22:57:31.678189 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_accel_iio_abi RESULT=skip
11067 22:57:31.684200 test_cros_ec_accel_iio_data_is_valid (cros.tests.cros_ec_accel.TestCrosECAccel)
11068 22:57:31.690803 Validates accelerometer data by computing the magnitude. If the ... skipped 'No accelerometer found'
11069 22:57:31.690933
11070 22:57:31.701212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_accel_iio_data_is_valid RESULT=skip>
11071 22:57:31.701587 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_accel_iio_data_is_valid RESULT=skip
11073 22:57:31.707578 test_cros_ec_gyro_iio_abi (cros.tests.cros_ec_gyro.TestCrosECGyro)
11074 22:57:31.711383 Received signal: <ENDRUN> 0_cros-ec 10597662_1.5.2.3.1
11075 22:57:31.711490 Ending use of test pattern.
11076 22:57:31.711555 Ending test lava.0_cros-ec (10597662_1.5.2.3.1), duration 0.75
11078 22:57:31.714291 Checks t<8>[ 20.751381] <LAVA_SIGNAL_ENDRUN 0_cros-ec 10597662_1.5.2.3.1>
11079 22:57:31.717737 he cros-ec gyroscope IIO ABI. ... skipped 'No cros-ec-gyro found'
11080 22:57:31.717836
11081 22:57:31.724162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_gyro_iio_abi RESULT=skip>
11082 22:57:31.724434 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_gyro_iio_abi RESULT=skip
11084 22:57:31.730714 test_cros_ec_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11085 22:57:31.737408 Checks the standard ABI for the main Embedded Controller. ... ok
11086 22:57:31.737488
11087 22:57:31.740896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_abi RESULT=pass>
11088 22:57:31.741175 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_abi RESULT=pass
11090 22:57:31.747253 test_cros_ec_chardev (cros.tests.cros_ec_mcu.TestCrosECMCU)
11091 22:57:31.754319 Checks the main Embedded controller character device. ... ok
11092 22:57:31.754438
11093 22:57:31.757279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_chardev RESULT=pass>
11094 22:57:31.757542 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_chardev RESULT=pass
11096 22:57:31.763794 test_cros_ec_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11097 22:57:31.769901 Checks basic comunication with the main Embedded controller. ... ok
11098 22:57:31.770030
11099 22:57:31.777140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_hello RESULT=pass>
11100 22:57:31.777452 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_hello RESULT=pass
11102 22:57:31.780457 test_cros_fp_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11103 22:57:31.790241 Checks the standard ABI for the Fingerprint EC. ... skipped 'MCU cros_fp not supported'
11104 22:57:31.790465
11105 22:57:31.793635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_abi RESULT=skip>
11106 22:57:31.794032 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_abi RESULT=skip
11108 22:57:31.800164 test_cros_fp_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11109 22:57:31.807006 Checks basic comunication with the fingerprint controller. ... skipped 'MCU cros_fp not found'
11110 22:57:31.807581
11111 22:57:31.813474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_hello RESULT=skip>
11112 22:57:31.814039 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_hello RESULT=skip
11114 22:57:31.819650 test_cros_fp_reboot (cros.tests.cros_ec_mcu.TestCrosECMCU)
11115 22:57:31.826483 Test reboot command on Fingerprint MCU. ... skipped 'MCU cros_fp not found'
11116 22:57:31.826849
11117 22:57:31.832782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_reboot RESULT=skip>
11118 22:57:31.833382 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_reboot RESULT=skip
11120 22:57:31.836337 test_cros_pd_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11121 22:57:31.846406 Checks the standard ABI for the Power Delivery EC. ... skipped 'MCU cros_pd not supported'
11122 22:57:31.846882
11123 22:57:31.849791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_pd_abi RESULT=skip>
11124 22:57:31.850554 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_pd_abi RESULT=skip
11126 22:57:31.855961 test_cros_pd_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11127 22:57:31.866325 Checks basic comunication with the power delivery controller. ... skipped 'MCU cros_pd not found'
11128 22:57:31.866526
11129 22:57:31.869305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_pd_hello RESULT=skip>
11130 22:57:31.869695 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_pd_hello RESULT=skip
11132 22:57:31.875897 test_cros_tp_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11133 22:57:31.882574 Checks the standard ABI for the Touchpad EC. ... skipped 'MCU cros_tp not supported'
11134 22:57:31.882774
11135 22:57:31.889268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_tp_abi RESULT=skip>
11136 22:57:31.889636 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_tp_abi RESULT=skip
11138 22:57:31.895778 test_cros_tp_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11139 22:57:31.902473 Checks basic comunication with the touchpad controller. ... skipped 'MCU cros_tp not found'
11140 22:57:31.902689
11141 22:57:31.909056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_tp_hello RESULT=skip>
11142 22:57:31.909443 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_tp_hello RESULT=skip
11144 22:57:31.915614 test_cros_ec_pwm_backlight (cros.tests.cros_ec_pwm.TestCrosECPWM)
11145 22:57:31.922119 Check that the backlight is connected to a pwm of the EC and that ... skipped 'No backlight pwm found'
11146 22:57:31.922334
11147 22:57:31.929114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_pwm_backlight RESULT=skip>
11148 22:57:31.929515 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_pwm_backlight RESULT=skip
11150 22:57:31.935448 test_cros_ec_battery_abi (cros.tests.cros_ec_power.TestCrosECPower)
11151 22:57:31.941795 Check the cros battery ABI. ... skipped 'No BAT found'
11152 22:57:31.942015
11153 22:57:31.948890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_battery_abi RESULT=skip>
11154 22:57:31.949211 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_battery_abi RESULT=skip
11156 22:57:31.955206 test_cros_ec_usbpd_charger_abi (cros.tests.cros_ec_power.TestCrosECPower)
11157 22:57:31.962005 Check the cros USBPD charger ABI. ... skipped 'No CROS_USBPD_CHARGER found'
11158 22:57:31.962122
11159 22:57:31.968087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_usbpd_charger_abi RESULT=skip>
11160 22:57:31.968382 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_usbpd_charger_abi RESULT=skip
11162 22:57:31.971580 test_cros_ec_rtc_abi (cros.tests.cros_ec_rtc.TestCrosECRTC)
11163 22:57:31.978024 Check the cros RTC ABI. ... skipped 'EC_FEATURE_RTC not supported, skipping'
11164 22:57:31.978138
11165 22:57:31.984999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_rtc_abi RESULT=skip>
11166 22:57:31.985262 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_rtc_abi RESULT=skip
11168 22:57:31.991598 test_cros_ec_extcon_usbc_abi (cros.tests.cros_ec_extcon.TestCrosECextcon)
11169 22:57:31.998399 Checks the cros-ec extcon ABI. ... skipped 'No extcon device found'
11170 22:57:31.998491
11171 22:57:32.004887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_extcon_usbc_abi RESULT=skip>
11172 22:57:32.004991
11173 22:57:32.005236 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_extcon_usbc_abi RESULT=skip
11175 22:57:32.011155 ----------------------------------------------------------------------
11176 22:57:32.014675 Ran 18 tests in 0.010s
11177 22:57:32.014783
11178 22:57:32.014859 OK (skipped=15)
11179 22:57:32.018031 + set +x
11180 22:57:32.018137 <LAVA_TEST_RUNNER EXIT>
11181 22:57:32.018397 ok: lava_test_shell seems to have completed
11182 22:57:32.018614 test_cros_ec_abi: pass
test_cros_ec_accel_iio_abi: skip
test_cros_ec_accel_iio_data_is_valid: skip
test_cros_ec_battery_abi: skip
test_cros_ec_chardev: pass
test_cros_ec_extcon_usbc_abi: skip
test_cros_ec_gyro_iio_abi: skip
test_cros_ec_hello: pass
test_cros_ec_pwm_backlight: skip
test_cros_ec_rtc_abi: skip
test_cros_ec_usbpd_charger_abi: skip
test_cros_fp_abi: skip
test_cros_fp_hello: skip
test_cros_fp_reboot: skip
test_cros_pd_abi: skip
test_cros_pd_hello: skip
test_cros_tp_abi: skip
test_cros_tp_hello: skip
11183 22:57:32.018735 end: 3.1 lava-test-shell (duration 00:00:02) [common]
11184 22:57:32.018846 end: 3 lava-test-retry (duration 00:00:02) [common]
11185 22:57:32.018979 start: 4 finalize (timeout 00:07:20) [common]
11186 22:57:32.019100 start: 4.1 power-off (timeout 00:00:30) [common]
11187 22:57:32.019295 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=off'
11188 22:57:32.104899 >> Command sent successfully.
11189 22:57:32.109082 Returned 0 in 0 seconds
11190 22:57:32.210013 end: 4.1 power-off (duration 00:00:00) [common]
11192 22:57:32.211796 start: 4.2 read-feedback (timeout 00:07:20) [common]
11193 22:57:32.213121 Listened to connection for namespace 'common' for up to 1s
11194 22:57:33.213711 Finalising connection for namespace 'common'
11195 22:57:33.213905 Disconnecting from shell: Finalise
11196 22:57:33.214009 / #
11197 22:57:33.314390 end: 4.2 read-feedback (duration 00:00:01) [common]
11198 22:57:33.314625 end: 4 finalize (duration 00:00:01) [common]
11199 22:57:33.314790 Cleaning after the job
11200 22:57:33.314928 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597662/tftp-deploy-29_5pyne/ramdisk
11201 22:57:33.321169 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597662/tftp-deploy-29_5pyne/kernel
11202 22:57:33.327657 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597662/tftp-deploy-29_5pyne/dtb
11203 22:57:33.327849 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597662/tftp-deploy-29_5pyne/modules
11204 22:57:33.333257 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10597662
11205 22:57:33.433941 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10597662
11206 22:57:33.434173 Job finished correctly